1 /* tc-mips.c -- assemble code for a MIPS chip.
2 Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,
3 2003, 2004, 2005 Free Software Foundation, Inc.
4 Contributed by the OSF and Ralph Campbell.
5 Written by Keith Knowles and Ralph Campbell, working independently.
6 Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus
9 This file is part of GAS.
11 GAS is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 2, or (at your option)
16 GAS is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
21 You should have received a copy of the GNU General Public License
22 along with GAS; see the file COPYING. If not, write to the Free
23 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
29 #include "safe-ctype.h"
33 #include "opcode/mips.h"
35 #include "dwarf2dbg.h"
38 #define DBG(x) printf x
44 /* Clean up namespace so we can include obj-elf.h too. */
45 static int mips_output_flavor (void);
46 static int mips_output_flavor (void) { return OUTPUT_FLAVOR
; }
47 #undef OBJ_PROCESS_STAB
54 #undef obj_frob_file_after_relocs
55 #undef obj_frob_symbol
57 #undef obj_sec_sym_ok_for_reloc
58 #undef OBJ_COPY_SYMBOL_ATTRIBUTES
61 /* Fix any of them that we actually care about. */
63 #define OUTPUT_FLAVOR mips_output_flavor()
70 #ifndef ECOFF_DEBUGGING
71 #define NO_ECOFF_DEBUGGING
72 #define ECOFF_DEBUGGING 0
75 int mips_flag_mdebug
= -1;
77 /* Control generation of .pdr sections. Off by default on IRIX: the native
78 linker doesn't know about and discards them, but relocations against them
79 remain, leading to rld crashes. */
81 int mips_flag_pdr
= FALSE
;
83 int mips_flag_pdr
= TRUE
;
88 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
89 static char *mips_regmask_frag
;
95 #define PIC_CALL_REG 25
103 #define ILLEGAL_REG (32)
105 /* Allow override of standard little-endian ECOFF format. */
107 #ifndef ECOFF_LITTLE_FORMAT
108 #define ECOFF_LITTLE_FORMAT "ecoff-littlemips"
111 extern int target_big_endian
;
113 /* The name of the readonly data section. */
114 #define RDATA_SECTION_NAME (OUTPUT_FLAVOR == bfd_target_ecoff_flavour \
116 : OUTPUT_FLAVOR == bfd_target_coff_flavour \
118 : OUTPUT_FLAVOR == bfd_target_elf_flavour \
122 /* Information about an instruction, including its format, operands
126 /* The opcode's entry in mips_opcodes or mips16_opcodes. */
127 const struct mips_opcode
*insn_mo
;
129 /* True if this is a mips16 instruction and if we want the extended
131 bfd_boolean use_extend
;
133 /* The 16-bit extension instruction to use when USE_EXTEND is true. */
134 unsigned short extend
;
136 /* The 16-bit or 32-bit bitstring of the instruction itself. This is
137 a copy of INSN_MO->match with the operands filled in. */
138 unsigned long insn_opcode
;
140 /* The frag that contains the instruction. */
143 /* The offset into FRAG of the first instruction byte. */
146 /* The relocs associated with the instruction, if any. */
149 /* True if this entry describes a real instruction. */
150 unsigned int valid_p
: 1;
152 /* True if this instruction occured in a .set noreorder block. */
153 unsigned int noreorder_p
: 1;
155 /* True if this instruction corresponds to an assembler-filled
156 delay slot. Always false if noreorder_p. */
157 unsigned int delay_slot_p
: 1;
159 /* True for extended mips16 instructions. */
160 unsigned int extended_p
: 1;
162 /* True for mips16 instructions that jump to an absolute address. */
163 unsigned int mips16_absolute_jump_p
: 1;
166 /* The ABI to use. */
177 /* MIPS ABI we are using for this output file. */
178 static enum mips_abi_level mips_abi
= NO_ABI
;
180 /* Whether or not we have code that can call pic code. */
181 int mips_abicalls
= FALSE
;
183 /* Whether or not we have code which can be put into a shared
185 static bfd_boolean mips_in_shared
= TRUE
;
187 /* This is the set of options which may be modified by the .set
188 pseudo-op. We use a struct so that .set push and .set pop are more
191 struct mips_set_options
193 /* MIPS ISA (Instruction Set Architecture) level. This is set to -1
194 if it has not been initialized. Changed by `.set mipsN', and the
195 -mipsN command line option, and the default CPU. */
197 /* Enabled Application Specific Extensions (ASEs). These are set to -1
198 if they have not been initialized. Changed by `.set <asename>', by
199 command line options, and based on the default architecture. */
202 /* Whether we are assembling for the mips16 processor. 0 if we are
203 not, 1 if we are, and -1 if the value has not been initialized.
204 Changed by `.set mips16' and `.set nomips16', and the -mips16 and
205 -nomips16 command line options, and the default CPU. */
207 /* Non-zero if we should not reorder instructions. Changed by `.set
208 reorder' and `.set noreorder'. */
210 /* Non-zero if we should not permit the $at ($1) register to be used
211 in instructions. Changed by `.set at' and `.set noat'. */
213 /* Non-zero if we should warn when a macro instruction expands into
214 more than one machine instruction. Changed by `.set nomacro' and
216 int warn_about_macros
;
217 /* Non-zero if we should not move instructions. Changed by `.set
218 move', `.set volatile', `.set nomove', and `.set novolatile'. */
220 /* Non-zero if we should not optimize branches by moving the target
221 of the branch into the delay slot. Actually, we don't perform
222 this optimization anyhow. Changed by `.set bopt' and `.set
225 /* Non-zero if we should not autoextend mips16 instructions.
226 Changed by `.set autoextend' and `.set noautoextend'. */
228 /* Restrict general purpose registers and floating point registers
229 to 32 bit. This is initially determined when -mgp32 or -mfp32
230 is passed but can changed if the assembler code uses .set mipsN. */
233 /* MIPS architecture (CPU) type. Changed by .set arch=FOO, the -march
234 command line option, and the default CPU. */
236 /* True if ".set sym32" is in effect. */
240 /* True if -mgp32 was passed. */
241 static int file_mips_gp32
= -1;
243 /* True if -mfp32 was passed. */
244 static int file_mips_fp32
= -1;
246 /* This is the struct we use to hold the current set of options. Note
247 that we must set the isa field to ISA_UNKNOWN and the ASE fields to
248 -1 to indicate that they have not been initialized. */
250 static struct mips_set_options mips_opts
=
252 ISA_UNKNOWN
, -1, -1, -1, 0, 0, 0, 0, 0, 0, 0, 0, CPU_UNKNOWN
, FALSE
255 /* These variables are filled in with the masks of registers used.
256 The object format code reads them and puts them in the appropriate
258 unsigned long mips_gprmask
;
259 unsigned long mips_cprmask
[4];
261 /* MIPS ISA we are using for this output file. */
262 static int file_mips_isa
= ISA_UNKNOWN
;
264 /* True if -mips16 was passed or implied by arguments passed on the
265 command line (e.g., by -march). */
266 static int file_ase_mips16
;
268 /* True if -mips3d was passed or implied by arguments passed on the
269 command line (e.g., by -march). */
270 static int file_ase_mips3d
;
272 /* True if -mdmx was passed or implied by arguments passed on the
273 command line (e.g., by -march). */
274 static int file_ase_mdmx
;
276 /* The argument of the -march= flag. The architecture we are assembling. */
277 static int file_mips_arch
= CPU_UNKNOWN
;
278 static const char *mips_arch_string
;
280 /* The argument of the -mtune= flag. The architecture for which we
282 static int mips_tune
= CPU_UNKNOWN
;
283 static const char *mips_tune_string
;
285 /* True when generating 32-bit code for a 64-bit processor. */
286 static int mips_32bitmode
= 0;
288 /* True if the given ABI requires 32-bit registers. */
289 #define ABI_NEEDS_32BIT_REGS(ABI) ((ABI) == O32_ABI)
291 /* Likewise 64-bit registers. */
292 #define ABI_NEEDS_64BIT_REGS(ABI) \
294 || (ABI) == N64_ABI \
297 /* Return true if ISA supports 64 bit gp register instructions. */
298 #define ISA_HAS_64BIT_REGS(ISA) ( \
300 || (ISA) == ISA_MIPS4 \
301 || (ISA) == ISA_MIPS5 \
302 || (ISA) == ISA_MIPS64 \
303 || (ISA) == ISA_MIPS64R2 \
306 /* Return true if ISA supports 64-bit right rotate (dror et al.)
308 #define ISA_HAS_DROR(ISA) ( \
309 (ISA) == ISA_MIPS64R2 \
312 /* Return true if ISA supports 32-bit right rotate (ror et al.)
314 #define ISA_HAS_ROR(ISA) ( \
315 (ISA) == ISA_MIPS32R2 \
316 || (ISA) == ISA_MIPS64R2 \
319 #define HAVE_32BIT_GPRS \
320 (mips_opts.gp32 || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
322 #define HAVE_32BIT_FPRS \
323 (mips_opts.fp32 || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
325 #define HAVE_64BIT_GPRS (! HAVE_32BIT_GPRS)
326 #define HAVE_64BIT_FPRS (! HAVE_32BIT_FPRS)
328 #define HAVE_NEWABI (mips_abi == N32_ABI || mips_abi == N64_ABI)
330 #define HAVE_64BIT_OBJECTS (mips_abi == N64_ABI)
332 /* True if relocations are stored in-place. */
333 #define HAVE_IN_PLACE_ADDENDS (!HAVE_NEWABI)
335 /* The ABI-derived address size. */
336 #define HAVE_64BIT_ADDRESSES \
337 (HAVE_64BIT_GPRS && (mips_abi == EABI_ABI || mips_abi == N64_ABI))
338 #define HAVE_32BIT_ADDRESSES (!HAVE_64BIT_ADDRESSES)
340 /* The size of symbolic constants (i.e., expressions of the form
341 "SYMBOL" or "SYMBOL + OFFSET"). */
342 #define HAVE_32BIT_SYMBOLS \
343 (HAVE_32BIT_ADDRESSES || !HAVE_64BIT_OBJECTS || mips_opts.sym32)
344 #define HAVE_64BIT_SYMBOLS (!HAVE_32BIT_SYMBOLS)
346 /* Addresses are loaded in different ways, depending on the address size
347 in use. The n32 ABI Documentation also mandates the use of additions
348 with overflow checking, but existing implementations don't follow it. */
349 #define ADDRESS_ADD_INSN \
350 (HAVE_32BIT_ADDRESSES ? "addu" : "daddu")
352 #define ADDRESS_ADDI_INSN \
353 (HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu")
355 #define ADDRESS_LOAD_INSN \
356 (HAVE_32BIT_ADDRESSES ? "lw" : "ld")
358 #define ADDRESS_STORE_INSN \
359 (HAVE_32BIT_ADDRESSES ? "sw" : "sd")
361 /* Return true if the given CPU supports the MIPS16 ASE. */
362 #define CPU_HAS_MIPS16(cpu) \
363 (strncmp (TARGET_CPU, "mips16", sizeof ("mips16") - 1) == 0 \
364 || strncmp (TARGET_CANONICAL, "mips-lsi-elf", sizeof ("mips-lsi-elf") - 1) == 0)
366 /* Return true if the given CPU supports the MIPS3D ASE. */
367 #define CPU_HAS_MIPS3D(cpu) ((cpu) == CPU_SB1 \
370 /* Return true if the given CPU supports the MDMX ASE. */
371 #define CPU_HAS_MDMX(cpu) (FALSE \
374 /* True if CPU has a dror instruction. */
375 #define CPU_HAS_DROR(CPU) ((CPU) == CPU_VR5400 || (CPU) == CPU_VR5500)
377 /* True if CPU has a ror instruction. */
378 #define CPU_HAS_ROR(CPU) CPU_HAS_DROR (CPU)
380 /* True if mflo and mfhi can be immediately followed by instructions
381 which write to the HI and LO registers.
383 According to MIPS specifications, MIPS ISAs I, II, and III need
384 (at least) two instructions between the reads of HI/LO and
385 instructions which write them, and later ISAs do not. Contradicting
386 the MIPS specifications, some MIPS IV processor user manuals (e.g.
387 the UM for the NEC Vr5000) document needing the instructions between
388 HI/LO reads and writes, as well. Therefore, we declare only MIPS32,
389 MIPS64 and later ISAs to have the interlocks, plus any specific
390 earlier-ISA CPUs for which CPU documentation declares that the
391 instructions are really interlocked. */
392 #define hilo_interlocks \
393 (mips_opts.isa == ISA_MIPS32 \
394 || mips_opts.isa == ISA_MIPS32R2 \
395 || mips_opts.isa == ISA_MIPS64 \
396 || mips_opts.isa == ISA_MIPS64R2 \
397 || mips_opts.arch == CPU_R4010 \
398 || mips_opts.arch == CPU_R10000 \
399 || mips_opts.arch == CPU_R12000 \
400 || mips_opts.arch == CPU_RM7000 \
401 || mips_opts.arch == CPU_VR5500 \
404 /* Whether the processor uses hardware interlocks to protect reads
405 from the GPRs after they are loaded from memory, and thus does not
406 require nops to be inserted. This applies to instructions marked
407 INSN_LOAD_MEMORY_DELAY. These nops are only required at MIPS ISA
409 #define gpr_interlocks \
410 (mips_opts.isa != ISA_MIPS1 \
411 || mips_opts.arch == CPU_R3900)
413 /* Whether the processor uses hardware interlocks to avoid delays
414 required by coprocessor instructions, and thus does not require
415 nops to be inserted. This applies to instructions marked
416 INSN_LOAD_COPROC_DELAY, INSN_COPROC_MOVE_DELAY, and to delays
417 between instructions marked INSN_WRITE_COND_CODE and ones marked
418 INSN_READ_COND_CODE. These nops are only required at MIPS ISA
419 levels I, II, and III. */
420 /* Itbl support may require additional care here. */
421 #define cop_interlocks \
422 ((mips_opts.isa != ISA_MIPS1 \
423 && mips_opts.isa != ISA_MIPS2 \
424 && mips_opts.isa != ISA_MIPS3) \
425 || mips_opts.arch == CPU_R4300 \
428 /* Whether the processor uses hardware interlocks to protect reads
429 from coprocessor registers after they are loaded from memory, and
430 thus does not require nops to be inserted. This applies to
431 instructions marked INSN_COPROC_MEMORY_DELAY. These nops are only
432 requires at MIPS ISA level I. */
433 #define cop_mem_interlocks (mips_opts.isa != ISA_MIPS1)
435 /* Is this a mfhi or mflo instruction? */
436 #define MF_HILO_INSN(PINFO) \
437 ((PINFO & INSN_READ_HI) || (PINFO & INSN_READ_LO))
439 /* MIPS PIC level. */
441 enum mips_pic_level mips_pic
;
443 /* 1 if we should generate 32 bit offsets from the $gp register in
444 SVR4_PIC mode. Currently has no meaning in other modes. */
445 static int mips_big_got
= 0;
447 /* 1 if trap instructions should used for overflow rather than break
449 static int mips_trap
= 0;
451 /* 1 if double width floating point constants should not be constructed
452 by assembling two single width halves into two single width floating
453 point registers which just happen to alias the double width destination
454 register. On some architectures this aliasing can be disabled by a bit
455 in the status register, and the setting of this bit cannot be determined
456 automatically at assemble time. */
457 static int mips_disable_float_construction
;
459 /* Non-zero if any .set noreorder directives were used. */
461 static int mips_any_noreorder
;
463 /* Non-zero if nops should be inserted when the register referenced in
464 an mfhi/mflo instruction is read in the next two instructions. */
465 static int mips_7000_hilo_fix
;
467 /* The size of the small data section. */
468 static unsigned int g_switch_value
= 8;
469 /* Whether the -G option was used. */
470 static int g_switch_seen
= 0;
475 /* If we can determine in advance that GP optimization won't be
476 possible, we can skip the relaxation stuff that tries to produce
477 GP-relative references. This makes delay slot optimization work
480 This function can only provide a guess, but it seems to work for
481 gcc output. It needs to guess right for gcc, otherwise gcc
482 will put what it thinks is a GP-relative instruction in a branch
485 I don't know if a fix is needed for the SVR4_PIC mode. I've only
486 fixed it for the non-PIC mode. KR 95/04/07 */
487 static int nopic_need_relax (symbolS
*, int);
489 /* handle of the OPCODE hash table */
490 static struct hash_control
*op_hash
= NULL
;
492 /* The opcode hash table we use for the mips16. */
493 static struct hash_control
*mips16_op_hash
= NULL
;
495 /* This array holds the chars that always start a comment. If the
496 pre-processor is disabled, these aren't very useful */
497 const char comment_chars
[] = "#";
499 /* This array holds the chars that only start a comment at the beginning of
500 a line. If the line seems to have the form '# 123 filename'
501 .line and .file directives will appear in the pre-processed output */
502 /* Note that input_file.c hand checks for '#' at the beginning of the
503 first line of the input file. This is because the compiler outputs
504 #NO_APP at the beginning of its output. */
505 /* Also note that C style comments are always supported. */
506 const char line_comment_chars
[] = "#";
508 /* This array holds machine specific line separator characters. */
509 const char line_separator_chars
[] = ";";
511 /* Chars that can be used to separate mant from exp in floating point nums */
512 const char EXP_CHARS
[] = "eE";
514 /* Chars that mean this number is a floating point constant */
517 const char FLT_CHARS
[] = "rRsSfFdDxXpP";
519 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
520 changed in read.c . Ideally it shouldn't have to know about it at all,
521 but nothing is ideal around here.
524 static char *insn_error
;
526 static int auto_align
= 1;
528 /* When outputting SVR4 PIC code, the assembler needs to know the
529 offset in the stack frame from which to restore the $gp register.
530 This is set by the .cprestore pseudo-op, and saved in this
532 static offsetT mips_cprestore_offset
= -1;
534 /* Similar for NewABI PIC code, where $gp is callee-saved. NewABI has some
535 more optimizations, it can use a register value instead of a memory-saved
536 offset and even an other register than $gp as global pointer. */
537 static offsetT mips_cpreturn_offset
= -1;
538 static int mips_cpreturn_register
= -1;
539 static int mips_gp_register
= GP
;
540 static int mips_gprel_offset
= 0;
542 /* Whether mips_cprestore_offset has been set in the current function
543 (or whether it has already been warned about, if not). */
544 static int mips_cprestore_valid
= 0;
546 /* This is the register which holds the stack frame, as set by the
547 .frame pseudo-op. This is needed to implement .cprestore. */
548 static int mips_frame_reg
= SP
;
550 /* Whether mips_frame_reg has been set in the current function
551 (or whether it has already been warned about, if not). */
552 static int mips_frame_reg_valid
= 0;
554 /* To output NOP instructions correctly, we need to keep information
555 about the previous two instructions. */
557 /* Whether we are optimizing. The default value of 2 means to remove
558 unneeded NOPs and swap branch instructions when possible. A value
559 of 1 means to not swap branches. A value of 0 means to always
561 static int mips_optimize
= 2;
563 /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is
564 equivalent to seeing no -g option at all. */
565 static int mips_debug
= 0;
567 /* A list of previous instructions, with index 0 being the most recent. */
568 static struct mips_cl_insn history
[2];
570 /* If we don't want information for a history[] entry, we
571 point the insn_mo field at this dummy integer. */
572 static const struct mips_opcode dummy_opcode
= { NULL
, NULL
, 0, 0, 0, 0, 0 };
574 /* If this is set, it points to a frag holding nop instructions which
575 were inserted before the start of a noreorder section. If those
576 nops turn out to be unnecessary, the size of the frag can be
578 static fragS
*prev_nop_frag
;
580 /* The number of nop instructions we created in prev_nop_frag. */
581 static int prev_nop_frag_holds
;
583 /* The number of nop instructions that we know we need in
585 static int prev_nop_frag_required
;
587 /* The number of instructions we've seen since prev_nop_frag. */
588 static int prev_nop_frag_since
;
590 /* For ECOFF and ELF, relocations against symbols are done in two
591 parts, with a HI relocation and a LO relocation. Each relocation
592 has only 16 bits of space to store an addend. This means that in
593 order for the linker to handle carries correctly, it must be able
594 to locate both the HI and the LO relocation. This means that the
595 relocations must appear in order in the relocation table.
597 In order to implement this, we keep track of each unmatched HI
598 relocation. We then sort them so that they immediately precede the
599 corresponding LO relocation. */
604 struct mips_hi_fixup
*next
;
607 /* The section this fixup is in. */
611 /* The list of unmatched HI relocs. */
613 static struct mips_hi_fixup
*mips_hi_fixup_list
;
615 /* The frag containing the last explicit relocation operator.
616 Null if explicit relocations have not been used. */
618 static fragS
*prev_reloc_op_frag
;
620 /* Map normal MIPS register numbers to mips16 register numbers. */
622 #define X ILLEGAL_REG
623 static const int mips32_to_16_reg_map
[] =
625 X
, X
, 2, 3, 4, 5, 6, 7,
626 X
, X
, X
, X
, X
, X
, X
, X
,
627 0, 1, X
, X
, X
, X
, X
, X
,
628 X
, X
, X
, X
, X
, X
, X
, X
632 /* Map mips16 register numbers to normal MIPS register numbers. */
634 static const unsigned int mips16_to_32_reg_map
[] =
636 16, 17, 2, 3, 4, 5, 6, 7
639 static int mips_fix_vr4120
;
641 /* We don't relax branches by default, since this causes us to expand
642 `la .l2 - .l1' if there's a branch between .l1 and .l2, because we
643 fail to compute the offset before expanding the macro to the most
644 efficient expansion. */
646 static int mips_relax_branch
;
648 /* The expansion of many macros depends on the type of symbol that
649 they refer to. For example, when generating position-dependent code,
650 a macro that refers to a symbol may have two different expansions,
651 one which uses GP-relative addresses and one which uses absolute
652 addresses. When generating SVR4-style PIC, a macro may have
653 different expansions for local and global symbols.
655 We handle these situations by generating both sequences and putting
656 them in variant frags. In position-dependent code, the first sequence
657 will be the GP-relative one and the second sequence will be the
658 absolute one. In SVR4 PIC, the first sequence will be for global
659 symbols and the second will be for local symbols.
661 The frag's "subtype" is RELAX_ENCODE (FIRST, SECOND), where FIRST and
662 SECOND are the lengths of the two sequences in bytes. These fields
663 can be extracted using RELAX_FIRST() and RELAX_SECOND(). In addition,
664 the subtype has the following flags:
667 Set if it has been decided that we should use the second
668 sequence instead of the first.
671 Set in the first variant frag if the macro's second implementation
672 is longer than its first. This refers to the macro as a whole,
673 not an individual relaxation.
676 Set in the first variant frag if the macro appeared in a .set nomacro
677 block and if one alternative requires a warning but the other does not.
680 Like RELAX_NOMACRO, but indicates that the macro appears in a branch
683 The frag's "opcode" points to the first fixup for relaxable code.
685 Relaxable macros are generated using a sequence such as:
687 relax_start (SYMBOL);
688 ... generate first expansion ...
690 ... generate second expansion ...
693 The code and fixups for the unwanted alternative are discarded
694 by md_convert_frag. */
695 #define RELAX_ENCODE(FIRST, SECOND) (((FIRST) << 8) | (SECOND))
697 #define RELAX_FIRST(X) (((X) >> 8) & 0xff)
698 #define RELAX_SECOND(X) ((X) & 0xff)
699 #define RELAX_USE_SECOND 0x10000
700 #define RELAX_SECOND_LONGER 0x20000
701 #define RELAX_NOMACRO 0x40000
702 #define RELAX_DELAY_SLOT 0x80000
704 /* Branch without likely bit. If label is out of range, we turn:
706 beq reg1, reg2, label
716 with the following opcode replacements:
723 bltzal <-> bgezal (with jal label instead of j label)
725 Even though keeping the delay slot instruction in the delay slot of
726 the branch would be more efficient, it would be very tricky to do
727 correctly, because we'd have to introduce a variable frag *after*
728 the delay slot instruction, and expand that instead. Let's do it
729 the easy way for now, even if the branch-not-taken case now costs
730 one additional instruction. Out-of-range branches are not supposed
731 to be common, anyway.
733 Branch likely. If label is out of range, we turn:
735 beql reg1, reg2, label
736 delay slot (annulled if branch not taken)
745 delay slot (executed only if branch taken)
748 It would be possible to generate a shorter sequence by losing the
749 likely bit, generating something like:
754 delay slot (executed only if branch taken)
766 bltzall -> bgezal (with jal label instead of j label)
767 bgezall -> bltzal (ditto)
770 but it's not clear that it would actually improve performance. */
771 #define RELAX_BRANCH_ENCODE(uncond, likely, link, toofar) \
774 | ((toofar) ? 1 : 0) \
776 | ((likely) ? 4 : 0) \
777 | ((uncond) ? 8 : 0)))
778 #define RELAX_BRANCH_P(i) (((i) & 0xf0000000) == 0xc0000000)
779 #define RELAX_BRANCH_UNCOND(i) (((i) & 8) != 0)
780 #define RELAX_BRANCH_LIKELY(i) (((i) & 4) != 0)
781 #define RELAX_BRANCH_LINK(i) (((i) & 2) != 0)
782 #define RELAX_BRANCH_TOOFAR(i) (((i) & 1) != 0)
784 /* For mips16 code, we use an entirely different form of relaxation.
785 mips16 supports two versions of most instructions which take
786 immediate values: a small one which takes some small value, and a
787 larger one which takes a 16 bit value. Since branches also follow
788 this pattern, relaxing these values is required.
790 We can assemble both mips16 and normal MIPS code in a single
791 object. Therefore, we need to support this type of relaxation at
792 the same time that we support the relaxation described above. We
793 use the high bit of the subtype field to distinguish these cases.
795 The information we store for this type of relaxation is the
796 argument code found in the opcode file for this relocation, whether
797 the user explicitly requested a small or extended form, and whether
798 the relocation is in a jump or jal delay slot. That tells us the
799 size of the value, and how it should be stored. We also store
800 whether the fragment is considered to be extended or not. We also
801 store whether this is known to be a branch to a different section,
802 whether we have tried to relax this frag yet, and whether we have
803 ever extended a PC relative fragment because of a shift count. */
804 #define RELAX_MIPS16_ENCODE(type, small, ext, dslot, jal_dslot) \
807 | ((small) ? 0x100 : 0) \
808 | ((ext) ? 0x200 : 0) \
809 | ((dslot) ? 0x400 : 0) \
810 | ((jal_dslot) ? 0x800 : 0))
811 #define RELAX_MIPS16_P(i) (((i) & 0xc0000000) == 0x80000000)
812 #define RELAX_MIPS16_TYPE(i) ((i) & 0xff)
813 #define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x100) != 0)
814 #define RELAX_MIPS16_USER_EXT(i) (((i) & 0x200) != 0)
815 #define RELAX_MIPS16_DSLOT(i) (((i) & 0x400) != 0)
816 #define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x800) != 0)
817 #define RELAX_MIPS16_EXTENDED(i) (((i) & 0x1000) != 0)
818 #define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x1000)
819 #define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) &~ 0x1000)
820 #define RELAX_MIPS16_LONG_BRANCH(i) (((i) & 0x2000) != 0)
821 #define RELAX_MIPS16_MARK_LONG_BRANCH(i) ((i) | 0x2000)
822 #define RELAX_MIPS16_CLEAR_LONG_BRANCH(i) ((i) &~ 0x2000)
824 /* Is the given value a sign-extended 32-bit value? */
825 #define IS_SEXT_32BIT_NUM(x) \
826 (((x) &~ (offsetT) 0x7fffffff) == 0 \
827 || (((x) &~ (offsetT) 0x7fffffff) == ~ (offsetT) 0x7fffffff))
829 /* Is the given value a sign-extended 16-bit value? */
830 #define IS_SEXT_16BIT_NUM(x) \
831 (((x) &~ (offsetT) 0x7fff) == 0 \
832 || (((x) &~ (offsetT) 0x7fff) == ~ (offsetT) 0x7fff))
835 /* Global variables used when generating relaxable macros. See the
836 comment above RELAX_ENCODE for more details about how relaxation
839 /* 0 if we're not emitting a relaxable macro.
840 1 if we're emitting the first of the two relaxation alternatives.
841 2 if we're emitting the second alternative. */
844 /* The first relaxable fixup in the current frag. (In other words,
845 the first fixup that refers to relaxable code.) */
848 /* sizes[0] says how many bytes of the first alternative are stored in
849 the current frag. Likewise sizes[1] for the second alternative. */
850 unsigned int sizes
[2];
852 /* The symbol on which the choice of sequence depends. */
856 /* Global variables used to decide whether a macro needs a warning. */
858 /* True if the macro is in a branch delay slot. */
859 bfd_boolean delay_slot_p
;
861 /* For relaxable macros, sizes[0] is the length of the first alternative
862 in bytes and sizes[1] is the length of the second alternative.
863 For non-relaxable macros, both elements give the length of the
865 unsigned int sizes
[2];
867 /* The first variant frag for this macro. */
869 } mips_macro_warning
;
871 /* Prototypes for static functions. */
873 #define internalError() \
874 as_fatal (_("internal Error, line %d, %s"), __LINE__, __FILE__)
876 enum mips_regclass
{ MIPS_GR_REG
, MIPS_FP_REG
, MIPS16_REG
};
878 static void append_insn
879 (struct mips_cl_insn
*ip
, expressionS
*p
, bfd_reloc_code_real_type
*r
);
880 static void mips_no_prev_insn (int);
881 static void mips16_macro_build
882 (expressionS
*, const char *, const char *, va_list);
883 static void load_register (int, expressionS
*, int);
884 static void macro_start (void);
885 static void macro_end (void);
886 static void macro (struct mips_cl_insn
* ip
);
887 static void mips16_macro (struct mips_cl_insn
* ip
);
888 #ifdef LOSING_COMPILER
889 static void macro2 (struct mips_cl_insn
* ip
);
891 static void mips_ip (char *str
, struct mips_cl_insn
* ip
);
892 static void mips16_ip (char *str
, struct mips_cl_insn
* ip
);
893 static void mips16_immed
894 (char *, unsigned int, int, offsetT
, bfd_boolean
, bfd_boolean
, bfd_boolean
,
895 unsigned long *, bfd_boolean
*, unsigned short *);
896 static size_t my_getSmallExpression
897 (expressionS
*, bfd_reloc_code_real_type
*, char *);
898 static void my_getExpression (expressionS
*, char *);
899 static void s_align (int);
900 static void s_change_sec (int);
901 static void s_change_section (int);
902 static void s_cons (int);
903 static void s_float_cons (int);
904 static void s_mips_globl (int);
905 static void s_option (int);
906 static void s_mipsset (int);
907 static void s_abicalls (int);
908 static void s_cpload (int);
909 static void s_cpsetup (int);
910 static void s_cplocal (int);
911 static void s_cprestore (int);
912 static void s_cpreturn (int);
913 static void s_gpvalue (int);
914 static void s_gpword (int);
915 static void s_gpdword (int);
916 static void s_cpadd (int);
917 static void s_insn (int);
918 static void md_obj_begin (void);
919 static void md_obj_end (void);
920 static void s_mips_ent (int);
921 static void s_mips_end (int);
922 static void s_mips_frame (int);
923 static void s_mips_mask (int reg_type
);
924 static void s_mips_stab (int);
925 static void s_mips_weakext (int);
926 static void s_mips_file (int);
927 static void s_mips_loc (int);
928 static bfd_boolean
pic_need_relax (symbolS
*, asection
*);
929 static int relaxed_branch_length (fragS
*, asection
*, int);
930 static int validate_mips_insn (const struct mips_opcode
*);
932 /* Table and functions used to map between CPU/ISA names, and
933 ISA levels, and CPU numbers. */
937 const char *name
; /* CPU or ISA name. */
938 int is_isa
; /* Is this an ISA? (If 0, a CPU.) */
939 int isa
; /* ISA level. */
940 int cpu
; /* CPU number (default CPU if ISA). */
943 static const struct mips_cpu_info
*mips_parse_cpu (const char *, const char *);
944 static const struct mips_cpu_info
*mips_cpu_info_from_isa (int);
945 static const struct mips_cpu_info
*mips_cpu_info_from_arch (int);
949 The following pseudo-ops from the Kane and Heinrich MIPS book
950 should be defined here, but are currently unsupported: .alias,
951 .galive, .gjaldef, .gjrlive, .livereg, .noalias.
953 The following pseudo-ops from the Kane and Heinrich MIPS book are
954 specific to the type of debugging information being generated, and
955 should be defined by the object format: .aent, .begin, .bend,
956 .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp,
959 The following pseudo-ops from the Kane and Heinrich MIPS book are
960 not MIPS CPU specific, but are also not specific to the object file
961 format. This file is probably the best place to define them, but
962 they are not currently supported: .asm0, .endr, .lab, .repeat,
965 static const pseudo_typeS mips_pseudo_table
[] =
967 /* MIPS specific pseudo-ops. */
968 {"option", s_option
, 0},
969 {"set", s_mipsset
, 0},
970 {"rdata", s_change_sec
, 'r'},
971 {"sdata", s_change_sec
, 's'},
972 {"livereg", s_ignore
, 0},
973 {"abicalls", s_abicalls
, 0},
974 {"cpload", s_cpload
, 0},
975 {"cpsetup", s_cpsetup
, 0},
976 {"cplocal", s_cplocal
, 0},
977 {"cprestore", s_cprestore
, 0},
978 {"cpreturn", s_cpreturn
, 0},
979 {"gpvalue", s_gpvalue
, 0},
980 {"gpword", s_gpword
, 0},
981 {"gpdword", s_gpdword
, 0},
982 {"cpadd", s_cpadd
, 0},
985 /* Relatively generic pseudo-ops that happen to be used on MIPS
987 {"asciiz", stringer
, 1},
988 {"bss", s_change_sec
, 'b'},
991 {"dword", s_cons
, 3},
992 {"weakext", s_mips_weakext
, 0},
994 /* These pseudo-ops are defined in read.c, but must be overridden
995 here for one reason or another. */
996 {"align", s_align
, 0},
998 {"data", s_change_sec
, 'd'},
999 {"double", s_float_cons
, 'd'},
1000 {"float", s_float_cons
, 'f'},
1001 {"globl", s_mips_globl
, 0},
1002 {"global", s_mips_globl
, 0},
1003 {"hword", s_cons
, 1},
1005 {"long", s_cons
, 2},
1006 {"octa", s_cons
, 4},
1007 {"quad", s_cons
, 3},
1008 {"section", s_change_section
, 0},
1009 {"short", s_cons
, 1},
1010 {"single", s_float_cons
, 'f'},
1011 {"stabn", s_mips_stab
, 'n'},
1012 {"text", s_change_sec
, 't'},
1013 {"word", s_cons
, 2},
1015 { "extern", ecoff_directive_extern
, 0},
1020 static const pseudo_typeS mips_nonecoff_pseudo_table
[] =
1022 /* These pseudo-ops should be defined by the object file format.
1023 However, a.out doesn't support them, so we have versions here. */
1024 {"aent", s_mips_ent
, 1},
1025 {"bgnb", s_ignore
, 0},
1026 {"end", s_mips_end
, 0},
1027 {"endb", s_ignore
, 0},
1028 {"ent", s_mips_ent
, 0},
1029 {"file", s_mips_file
, 0},
1030 {"fmask", s_mips_mask
, 'F'},
1031 {"frame", s_mips_frame
, 0},
1032 {"loc", s_mips_loc
, 0},
1033 {"mask", s_mips_mask
, 'R'},
1034 {"verstamp", s_ignore
, 0},
1038 extern void pop_insert (const pseudo_typeS
*);
1041 mips_pop_insert (void)
1043 pop_insert (mips_pseudo_table
);
1044 if (! ECOFF_DEBUGGING
)
1045 pop_insert (mips_nonecoff_pseudo_table
);
1048 /* Symbols labelling the current insn. */
1050 struct insn_label_list
1052 struct insn_label_list
*next
;
1056 static struct insn_label_list
*insn_labels
;
1057 static struct insn_label_list
*free_insn_labels
;
1059 static void mips_clear_insn_labels (void);
1062 mips_clear_insn_labels (void)
1064 register struct insn_label_list
**pl
;
1066 for (pl
= &free_insn_labels
; *pl
!= NULL
; pl
= &(*pl
)->next
)
1072 static char *expr_end
;
1074 /* Expressions which appear in instructions. These are set by
1077 static expressionS imm_expr
;
1078 static expressionS imm2_expr
;
1079 static expressionS offset_expr
;
1081 /* Relocs associated with imm_expr and offset_expr. */
1083 static bfd_reloc_code_real_type imm_reloc
[3]
1084 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
1085 static bfd_reloc_code_real_type offset_reloc
[3]
1086 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
1088 /* These are set by mips16_ip if an explicit extension is used. */
1090 static bfd_boolean mips16_small
, mips16_ext
;
1093 /* The pdr segment for per procedure frame/regmask info. Not used for
1096 static segT pdr_seg
;
1099 /* The default target format to use. */
1102 mips_target_format (void)
1104 switch (OUTPUT_FLAVOR
)
1106 case bfd_target_ecoff_flavour
:
1107 return target_big_endian
? "ecoff-bigmips" : ECOFF_LITTLE_FORMAT
;
1108 case bfd_target_coff_flavour
:
1110 case bfd_target_elf_flavour
:
1112 /* This is traditional mips. */
1113 return (target_big_endian
1114 ? (HAVE_64BIT_OBJECTS
1115 ? "elf64-tradbigmips"
1117 ? "elf32-ntradbigmips" : "elf32-tradbigmips"))
1118 : (HAVE_64BIT_OBJECTS
1119 ? "elf64-tradlittlemips"
1121 ? "elf32-ntradlittlemips" : "elf32-tradlittlemips")));
1123 return (target_big_endian
1124 ? (HAVE_64BIT_OBJECTS
1127 ? "elf32-nbigmips" : "elf32-bigmips"))
1128 : (HAVE_64BIT_OBJECTS
1129 ? "elf64-littlemips"
1131 ? "elf32-nlittlemips" : "elf32-littlemips")));
1139 /* This function is called once, at assembler startup time. It should
1140 set up all the tables, etc. that the MD part of the assembler will need. */
1145 register const char *retval
= NULL
;
1149 if (! bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, file_mips_arch
))
1150 as_warn (_("Could not set architecture and machine"));
1152 op_hash
= hash_new ();
1154 for (i
= 0; i
< NUMOPCODES
;)
1156 const char *name
= mips_opcodes
[i
].name
;
1158 retval
= hash_insert (op_hash
, name
, (void *) &mips_opcodes
[i
]);
1161 fprintf (stderr
, _("internal error: can't hash `%s': %s\n"),
1162 mips_opcodes
[i
].name
, retval
);
1163 /* Probably a memory allocation problem? Give up now. */
1164 as_fatal (_("Broken assembler. No assembly attempted."));
1168 if (mips_opcodes
[i
].pinfo
!= INSN_MACRO
)
1170 if (!validate_mips_insn (&mips_opcodes
[i
]))
1175 while ((i
< NUMOPCODES
) && !strcmp (mips_opcodes
[i
].name
, name
));
1178 mips16_op_hash
= hash_new ();
1181 while (i
< bfd_mips16_num_opcodes
)
1183 const char *name
= mips16_opcodes
[i
].name
;
1185 retval
= hash_insert (mips16_op_hash
, name
, (void *) &mips16_opcodes
[i
]);
1187 as_fatal (_("internal: can't hash `%s': %s"),
1188 mips16_opcodes
[i
].name
, retval
);
1191 if (mips16_opcodes
[i
].pinfo
!= INSN_MACRO
1192 && ((mips16_opcodes
[i
].match
& mips16_opcodes
[i
].mask
)
1193 != mips16_opcodes
[i
].match
))
1195 fprintf (stderr
, _("internal error: bad mips16 opcode: %s %s\n"),
1196 mips16_opcodes
[i
].name
, mips16_opcodes
[i
].args
);
1201 while (i
< bfd_mips16_num_opcodes
1202 && strcmp (mips16_opcodes
[i
].name
, name
) == 0);
1206 as_fatal (_("Broken assembler. No assembly attempted."));
1208 /* We add all the general register names to the symbol table. This
1209 helps us detect invalid uses of them. */
1210 for (i
= 0; i
< 32; i
++)
1214 sprintf (buf
, "$%d", i
);
1215 symbol_table_insert (symbol_new (buf
, reg_section
, i
,
1216 &zero_address_frag
));
1218 symbol_table_insert (symbol_new ("$ra", reg_section
, RA
,
1219 &zero_address_frag
));
1220 symbol_table_insert (symbol_new ("$fp", reg_section
, FP
,
1221 &zero_address_frag
));
1222 symbol_table_insert (symbol_new ("$sp", reg_section
, SP
,
1223 &zero_address_frag
));
1224 symbol_table_insert (symbol_new ("$gp", reg_section
, GP
,
1225 &zero_address_frag
));
1226 symbol_table_insert (symbol_new ("$at", reg_section
, AT
,
1227 &zero_address_frag
));
1228 symbol_table_insert (symbol_new ("$kt0", reg_section
, KT0
,
1229 &zero_address_frag
));
1230 symbol_table_insert (symbol_new ("$kt1", reg_section
, KT1
,
1231 &zero_address_frag
));
1232 symbol_table_insert (symbol_new ("$zero", reg_section
, ZERO
,
1233 &zero_address_frag
));
1234 symbol_table_insert (symbol_new ("$pc", reg_section
, -1,
1235 &zero_address_frag
));
1237 /* If we don't add these register names to the symbol table, they
1238 may end up being added as regular symbols by operand(), and then
1239 make it to the object file as undefined in case they're not
1240 regarded as local symbols. They're local in o32, since `$' is a
1241 local symbol prefix, but not in n32 or n64. */
1242 for (i
= 0; i
< 8; i
++)
1246 sprintf (buf
, "$fcc%i", i
);
1247 symbol_table_insert (symbol_new (buf
, reg_section
, -1,
1248 &zero_address_frag
));
1251 mips_no_prev_insn (FALSE
);
1254 mips_cprmask
[0] = 0;
1255 mips_cprmask
[1] = 0;
1256 mips_cprmask
[2] = 0;
1257 mips_cprmask
[3] = 0;
1259 /* set the default alignment for the text section (2**2) */
1260 record_alignment (text_section
, 2);
1262 bfd_set_gp_size (stdoutput
, g_switch_value
);
1264 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
1266 /* On a native system, sections must be aligned to 16 byte
1267 boundaries. When configured for an embedded ELF target, we
1269 if (strcmp (TARGET_OS
, "elf") != 0)
1271 (void) bfd_set_section_alignment (stdoutput
, text_section
, 4);
1272 (void) bfd_set_section_alignment (stdoutput
, data_section
, 4);
1273 (void) bfd_set_section_alignment (stdoutput
, bss_section
, 4);
1276 /* Create a .reginfo section for register masks and a .mdebug
1277 section for debugging information. */
1285 subseg
= now_subseg
;
1287 /* The ABI says this section should be loaded so that the
1288 running program can access it. However, we don't load it
1289 if we are configured for an embedded target */
1290 flags
= SEC_READONLY
| SEC_DATA
;
1291 if (strcmp (TARGET_OS
, "elf") != 0)
1292 flags
|= SEC_ALLOC
| SEC_LOAD
;
1294 if (mips_abi
!= N64_ABI
)
1296 sec
= subseg_new (".reginfo", (subsegT
) 0);
1298 bfd_set_section_flags (stdoutput
, sec
, flags
);
1299 bfd_set_section_alignment (stdoutput
, sec
, HAVE_NEWABI
? 3 : 2);
1302 mips_regmask_frag
= frag_more (sizeof (Elf32_External_RegInfo
));
1307 /* The 64-bit ABI uses a .MIPS.options section rather than
1308 .reginfo section. */
1309 sec
= subseg_new (".MIPS.options", (subsegT
) 0);
1310 bfd_set_section_flags (stdoutput
, sec
, flags
);
1311 bfd_set_section_alignment (stdoutput
, sec
, 3);
1314 /* Set up the option header. */
1316 Elf_Internal_Options opthdr
;
1319 opthdr
.kind
= ODK_REGINFO
;
1320 opthdr
.size
= (sizeof (Elf_External_Options
)
1321 + sizeof (Elf64_External_RegInfo
));
1324 f
= frag_more (sizeof (Elf_External_Options
));
1325 bfd_mips_elf_swap_options_out (stdoutput
, &opthdr
,
1326 (Elf_External_Options
*) f
);
1328 mips_regmask_frag
= frag_more (sizeof (Elf64_External_RegInfo
));
1333 if (ECOFF_DEBUGGING
)
1335 sec
= subseg_new (".mdebug", (subsegT
) 0);
1336 (void) bfd_set_section_flags (stdoutput
, sec
,
1337 SEC_HAS_CONTENTS
| SEC_READONLY
);
1338 (void) bfd_set_section_alignment (stdoutput
, sec
, 2);
1341 else if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
&& mips_flag_pdr
)
1343 pdr_seg
= subseg_new (".pdr", (subsegT
) 0);
1344 (void) bfd_set_section_flags (stdoutput
, pdr_seg
,
1345 SEC_READONLY
| SEC_RELOC
1347 (void) bfd_set_section_alignment (stdoutput
, pdr_seg
, 2);
1351 subseg_set (seg
, subseg
);
1355 if (! ECOFF_DEBUGGING
)
1362 if (! ECOFF_DEBUGGING
)
1367 md_assemble (char *str
)
1369 struct mips_cl_insn insn
;
1370 bfd_reloc_code_real_type unused_reloc
[3]
1371 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
1373 imm_expr
.X_op
= O_absent
;
1374 imm2_expr
.X_op
= O_absent
;
1375 offset_expr
.X_op
= O_absent
;
1376 imm_reloc
[0] = BFD_RELOC_UNUSED
;
1377 imm_reloc
[1] = BFD_RELOC_UNUSED
;
1378 imm_reloc
[2] = BFD_RELOC_UNUSED
;
1379 offset_reloc
[0] = BFD_RELOC_UNUSED
;
1380 offset_reloc
[1] = BFD_RELOC_UNUSED
;
1381 offset_reloc
[2] = BFD_RELOC_UNUSED
;
1383 if (mips_opts
.mips16
)
1384 mips16_ip (str
, &insn
);
1387 mips_ip (str
, &insn
);
1388 DBG ((_("returned from mips_ip(%s) insn_opcode = 0x%x\n"),
1389 str
, insn
.insn_opcode
));
1394 as_bad ("%s `%s'", insn_error
, str
);
1398 if (insn
.insn_mo
->pinfo
== INSN_MACRO
)
1401 if (mips_opts
.mips16
)
1402 mips16_macro (&insn
);
1409 if (imm_expr
.X_op
!= O_absent
)
1410 append_insn (&insn
, &imm_expr
, imm_reloc
);
1411 else if (offset_expr
.X_op
!= O_absent
)
1412 append_insn (&insn
, &offset_expr
, offset_reloc
);
1414 append_insn (&insn
, NULL
, unused_reloc
);
1418 /* Return true if the given relocation might need a matching %lo().
1419 Note that R_MIPS_GOT16 relocations only need a matching %lo() when
1420 applied to local symbols. */
1422 static inline bfd_boolean
1423 reloc_needs_lo_p (bfd_reloc_code_real_type reloc
)
1425 return (HAVE_IN_PLACE_ADDENDS
1426 && (reloc
== BFD_RELOC_HI16_S
1427 || reloc
== BFD_RELOC_MIPS_GOT16
1428 || reloc
== BFD_RELOC_MIPS16_HI16_S
));
1431 /* Return true if the given fixup is followed by a matching R_MIPS_LO16
1434 static inline bfd_boolean
1435 fixup_has_matching_lo_p (fixS
*fixp
)
1437 return (fixp
->fx_next
!= NULL
1438 && (fixp
->fx_next
->fx_r_type
== BFD_RELOC_LO16
1439 || fixp
->fx_next
->fx_r_type
== BFD_RELOC_MIPS16_LO16
)
1440 && fixp
->fx_addsy
== fixp
->fx_next
->fx_addsy
1441 && fixp
->fx_offset
== fixp
->fx_next
->fx_offset
);
1444 /* See whether instruction IP reads register REG. CLASS is the type
1448 insn_uses_reg (struct mips_cl_insn
*ip
, unsigned int reg
,
1449 enum mips_regclass
class)
1451 if (class == MIPS16_REG
)
1453 assert (mips_opts
.mips16
);
1454 reg
= mips16_to_32_reg_map
[reg
];
1455 class = MIPS_GR_REG
;
1458 /* Don't report on general register ZERO, since it never changes. */
1459 if (class == MIPS_GR_REG
&& reg
== ZERO
)
1462 if (class == MIPS_FP_REG
)
1464 assert (! mips_opts
.mips16
);
1465 /* If we are called with either $f0 or $f1, we must check $f0.
1466 This is not optimal, because it will introduce an unnecessary
1467 NOP between "lwc1 $f0" and "swc1 $f1". To fix this we would
1468 need to distinguish reading both $f0 and $f1 or just one of
1469 them. Note that we don't have to check the other way,
1470 because there is no instruction that sets both $f0 and $f1
1471 and requires a delay. */
1472 if ((ip
->insn_mo
->pinfo
& INSN_READ_FPR_S
)
1473 && ((((ip
->insn_opcode
>> OP_SH_FS
) & OP_MASK_FS
) &~(unsigned)1)
1474 == (reg
&~ (unsigned) 1)))
1476 if ((ip
->insn_mo
->pinfo
& INSN_READ_FPR_T
)
1477 && ((((ip
->insn_opcode
>> OP_SH_FT
) & OP_MASK_FT
) &~(unsigned)1)
1478 == (reg
&~ (unsigned) 1)))
1481 else if (! mips_opts
.mips16
)
1483 if ((ip
->insn_mo
->pinfo
& INSN_READ_GPR_S
)
1484 && ((ip
->insn_opcode
>> OP_SH_RS
) & OP_MASK_RS
) == reg
)
1486 if ((ip
->insn_mo
->pinfo
& INSN_READ_GPR_T
)
1487 && ((ip
->insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
) == reg
)
1492 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_X
)
1493 && (mips16_to_32_reg_map
[((ip
->insn_opcode
>> MIPS16OP_SH_RX
)
1494 & MIPS16OP_MASK_RX
)]
1497 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_Y
)
1498 && (mips16_to_32_reg_map
[((ip
->insn_opcode
>> MIPS16OP_SH_RY
)
1499 & MIPS16OP_MASK_RY
)]
1502 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_Z
)
1503 && (mips16_to_32_reg_map
[((ip
->insn_opcode
>> MIPS16OP_SH_MOVE32Z
)
1504 & MIPS16OP_MASK_MOVE32Z
)]
1507 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_T
) && reg
== TREG
)
1509 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_SP
) && reg
== SP
)
1511 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_31
) && reg
== RA
)
1513 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_GPR_X
)
1514 && ((ip
->insn_opcode
>> MIPS16OP_SH_REGR32
)
1515 & MIPS16OP_MASK_REGR32
) == reg
)
1522 /* This function returns true if modifying a register requires a
1526 reg_needs_delay (unsigned int reg
)
1528 unsigned long prev_pinfo
;
1530 prev_pinfo
= history
[0].insn_mo
->pinfo
;
1531 if (! mips_opts
.noreorder
1532 && (((prev_pinfo
& INSN_LOAD_MEMORY_DELAY
)
1533 && ! gpr_interlocks
)
1534 || ((prev_pinfo
& INSN_LOAD_COPROC_DELAY
)
1535 && ! cop_interlocks
)))
1537 /* A load from a coprocessor or from memory. All load delays
1538 delay the use of general register rt for one instruction. */
1539 /* Itbl support may require additional care here. */
1540 know (prev_pinfo
& INSN_WRITE_GPR_T
);
1541 if (reg
== ((history
[0].insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
))
1548 /* Mark instruction labels in mips16 mode. This permits the linker to
1549 handle them specially, such as generating jalx instructions when
1550 needed. We also make them odd for the duration of the assembly, in
1551 order to generate the right sort of code. We will make them even
1552 in the adjust_symtab routine, while leaving them marked. This is
1553 convenient for the debugger and the disassembler. The linker knows
1554 to make them odd again. */
1557 mips16_mark_labels (void)
1559 if (mips_opts
.mips16
)
1561 struct insn_label_list
*l
;
1564 for (l
= insn_labels
; l
!= NULL
; l
= l
->next
)
1567 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
1568 S_SET_OTHER (l
->label
, STO_MIPS16
);
1570 val
= S_GET_VALUE (l
->label
);
1572 S_SET_VALUE (l
->label
, val
+ 1);
1577 /* End the current frag. Make it a variant frag and record the
1581 relax_close_frag (void)
1583 mips_macro_warning
.first_frag
= frag_now
;
1584 frag_var (rs_machine_dependent
, 0, 0,
1585 RELAX_ENCODE (mips_relax
.sizes
[0], mips_relax
.sizes
[1]),
1586 mips_relax
.symbol
, 0, (char *) mips_relax
.first_fixup
);
1588 memset (&mips_relax
.sizes
, 0, sizeof (mips_relax
.sizes
));
1589 mips_relax
.first_fixup
= 0;
1592 /* Start a new relaxation sequence whose expansion depends on SYMBOL.
1593 See the comment above RELAX_ENCODE for more details. */
1596 relax_start (symbolS
*symbol
)
1598 assert (mips_relax
.sequence
== 0);
1599 mips_relax
.sequence
= 1;
1600 mips_relax
.symbol
= symbol
;
1603 /* Start generating the second version of a relaxable sequence.
1604 See the comment above RELAX_ENCODE for more details. */
1609 assert (mips_relax
.sequence
== 1);
1610 mips_relax
.sequence
= 2;
1613 /* End the current relaxable sequence. */
1618 assert (mips_relax
.sequence
== 2);
1619 relax_close_frag ();
1620 mips_relax
.sequence
= 0;
1623 /* Output an instruction. IP is the instruction information.
1624 ADDRESS_EXPR is an operand of the instruction to be used with
1628 append_insn (struct mips_cl_insn
*ip
, expressionS
*address_expr
,
1629 bfd_reloc_code_real_type
*reloc_type
)
1631 register unsigned long prev_pinfo
, pinfo
;
1635 relax_stateT prev_insn_frag_type
= 0;
1636 bfd_boolean relaxed_branch
= FALSE
;
1637 bfd_boolean force_new_frag
= FALSE
;
1639 /* Mark instruction labels in mips16 mode. */
1640 mips16_mark_labels ();
1642 prev_pinfo
= history
[0].insn_mo
->pinfo
;
1643 pinfo
= ip
->insn_mo
->pinfo
;
1645 if (mips_relax
.sequence
!= 2
1646 && (!mips_opts
.noreorder
|| prev_nop_frag
!= NULL
))
1650 /* If the previous insn required any delay slots, see if we need
1651 to insert a NOP or two. There are eight kinds of possible
1652 hazards, of which an instruction can have at most one type.
1653 (1) a load from memory delay
1654 (2) a load from a coprocessor delay
1655 (3) an unconditional branch delay
1656 (4) a conditional branch delay
1657 (5) a move to coprocessor register delay
1658 (6) a load coprocessor register from memory delay
1659 (7) a coprocessor condition code delay
1660 (8) a HI/LO special register delay
1662 There are a lot of optimizations we could do that we don't.
1663 In particular, we do not, in general, reorder instructions.
1664 If you use gcc with optimization, it will reorder
1665 instructions and generally do much more optimization then we
1666 do here; repeating all that work in the assembler would only
1667 benefit hand written assembly code, and does not seem worth
1670 /* This is how a NOP is emitted. */
1671 #define emit_nop() \
1673 ? md_number_to_chars (frag_more (2), 0x6500, 2) \
1674 : md_number_to_chars (frag_more (4), 0, 4))
1676 /* The previous insn might require a delay slot, depending upon
1677 the contents of the current insn. */
1678 if (! mips_opts
.mips16
1679 && (((prev_pinfo
& INSN_LOAD_MEMORY_DELAY
)
1680 && ! gpr_interlocks
)
1681 || ((prev_pinfo
& INSN_LOAD_COPROC_DELAY
)
1682 && ! cop_interlocks
)))
1684 /* A load from a coprocessor or from memory. All load
1685 delays delay the use of general register rt for one
1687 /* Itbl support may require additional care here. */
1688 know (prev_pinfo
& INSN_WRITE_GPR_T
);
1689 if (mips_optimize
== 0
1690 || insn_uses_reg (ip
,
1691 ((history
[0].insn_opcode
>> OP_SH_RT
)
1696 else if (! mips_opts
.mips16
1697 && (((prev_pinfo
& INSN_COPROC_MOVE_DELAY
)
1698 && ! cop_interlocks
)
1699 || ((prev_pinfo
& INSN_COPROC_MEMORY_DELAY
)
1700 && ! cop_mem_interlocks
)))
1702 /* A generic coprocessor delay. The previous instruction
1703 modified a coprocessor general or control register. If
1704 it modified a control register, we need to avoid any
1705 coprocessor instruction (this is probably not always
1706 required, but it sometimes is). If it modified a general
1707 register, we avoid using that register.
1709 This case is not handled very well. There is no special
1710 knowledge of CP0 handling, and the coprocessors other
1711 than the floating point unit are not distinguished at
1713 /* Itbl support may require additional care here. FIXME!
1714 Need to modify this to include knowledge about
1715 user specified delays! */
1716 if (prev_pinfo
& INSN_WRITE_FPR_T
)
1718 if (mips_optimize
== 0
1719 || insn_uses_reg (ip
,
1720 ((history
[0].insn_opcode
>> OP_SH_FT
)
1725 else if (prev_pinfo
& INSN_WRITE_FPR_S
)
1727 if (mips_optimize
== 0
1728 || insn_uses_reg (ip
,
1729 ((history
[0].insn_opcode
>> OP_SH_FS
)
1736 /* We don't know exactly what the previous instruction
1737 does. If the current instruction uses a coprocessor
1738 register, we must insert a NOP. If previous
1739 instruction may set the condition codes, and the
1740 current instruction uses them, we must insert two
1742 /* Itbl support may require additional care here. */
1743 if (mips_optimize
== 0
1744 || ((prev_pinfo
& INSN_WRITE_COND_CODE
)
1745 && (pinfo
& INSN_READ_COND_CODE
)))
1747 else if (pinfo
& INSN_COP
)
1751 else if (! mips_opts
.mips16
1752 && (prev_pinfo
& INSN_WRITE_COND_CODE
)
1753 && ! cop_interlocks
)
1755 /* The previous instruction sets the coprocessor condition
1756 codes, but does not require a general coprocessor delay
1757 (this means it is a floating point comparison
1758 instruction). If this instruction uses the condition
1759 codes, we need to insert a single NOP. */
1760 /* Itbl support may require additional care here. */
1761 if (mips_optimize
== 0
1762 || (pinfo
& INSN_READ_COND_CODE
))
1766 /* If we're fixing up mfhi/mflo for the r7000 and the
1767 previous insn was an mfhi/mflo and the current insn
1768 reads the register that the mfhi/mflo wrote to, then
1771 else if (mips_7000_hilo_fix
1772 && MF_HILO_INSN (prev_pinfo
)
1773 && insn_uses_reg (ip
, ((history
[0].insn_opcode
>> OP_SH_RD
)
1780 /* If we're fixing up mfhi/mflo for the r7000 and the
1781 2nd previous insn was an mfhi/mflo and the current insn
1782 reads the register that the mfhi/mflo wrote to, then
1785 else if (mips_7000_hilo_fix
1786 && MF_HILO_INSN (history
[1].insn_opcode
)
1787 && insn_uses_reg (ip
, ((history
[1].insn_opcode
>> OP_SH_RD
)
1795 else if (prev_pinfo
& INSN_READ_LO
)
1797 /* The previous instruction reads the LO register; if the
1798 current instruction writes to the LO register, we must
1799 insert two NOPS. Some newer processors have interlocks.
1800 Also the tx39's multiply instructions can be executed
1801 immediately after a read from HI/LO (without the delay),
1802 though the tx39's divide insns still do require the
1804 if (! (hilo_interlocks
1805 || (mips_opts
.arch
== CPU_R3900
&& (pinfo
& INSN_MULT
)))
1806 && (mips_optimize
== 0
1807 || (pinfo
& INSN_WRITE_LO
)))
1809 /* Most mips16 branch insns don't have a delay slot.
1810 If a read from LO is immediately followed by a branch
1811 to a write to LO we have a read followed by a write
1812 less than 2 insns away. We assume the target of
1813 a branch might be a write to LO, and insert a nop
1814 between a read and an immediately following branch. */
1815 else if (mips_opts
.mips16
1816 && (mips_optimize
== 0
1817 || (pinfo
& MIPS16_INSN_BRANCH
)))
1820 else if (history
[0].insn_mo
->pinfo
& INSN_READ_HI
)
1822 /* The previous instruction reads the HI register; if the
1823 current instruction writes to the HI register, we must
1824 insert a NOP. Some newer processors have interlocks.
1825 Also the note tx39's multiply above. */
1826 if (! (hilo_interlocks
1827 || (mips_opts
.arch
== CPU_R3900
&& (pinfo
& INSN_MULT
)))
1828 && (mips_optimize
== 0
1829 || (pinfo
& INSN_WRITE_HI
)))
1831 /* Most mips16 branch insns don't have a delay slot.
1832 If a read from HI is immediately followed by a branch
1833 to a write to HI we have a read followed by a write
1834 less than 2 insns away. We assume the target of
1835 a branch might be a write to HI, and insert a nop
1836 between a read and an immediately following branch. */
1837 else if (mips_opts
.mips16
1838 && (mips_optimize
== 0
1839 || (pinfo
& MIPS16_INSN_BRANCH
)))
1843 /* If the previous instruction was in a noreorder section, then
1844 we don't want to insert the nop after all. */
1845 /* Itbl support may require additional care here. */
1846 if (history
[0].noreorder_p
)
1849 /* There are two cases which require two intervening
1850 instructions: 1) setting the condition codes using a move to
1851 coprocessor instruction which requires a general coprocessor
1852 delay and then reading the condition codes 2) reading the HI
1853 or LO register and then writing to it (except on processors
1854 which have interlocks). If we are not already emitting a NOP
1855 instruction, we must check for these cases compared to the
1856 instruction previous to the previous instruction. */
1857 if ((! mips_opts
.mips16
1858 && (history
[1].insn_mo
->pinfo
& INSN_COPROC_MOVE_DELAY
)
1859 && (history
[1].insn_mo
->pinfo
& INSN_WRITE_COND_CODE
)
1860 && (pinfo
& INSN_READ_COND_CODE
)
1861 && ! cop_interlocks
)
1862 || ((history
[1].insn_mo
->pinfo
& INSN_READ_LO
)
1863 && (pinfo
& INSN_WRITE_LO
)
1864 && ! (hilo_interlocks
1865 || (mips_opts
.arch
== CPU_R3900
&& (pinfo
& INSN_MULT
))))
1866 || ((history
[1].insn_mo
->pinfo
& INSN_READ_HI
)
1867 && (pinfo
& INSN_WRITE_HI
)
1868 && ! (hilo_interlocks
1869 || (mips_opts
.arch
== CPU_R3900
&& (pinfo
& INSN_MULT
)))))
1874 if (history
[1].noreorder_p
)
1877 if (prev_prev_nop
&& nops
== 0)
1880 if (mips_fix_vr4120
&& history
[0].insn_mo
->name
)
1882 /* We're out of bits in pinfo, so we must resort to string
1883 ops here. Shortcuts are selected based on opcodes being
1884 limited to the VR4120 instruction set. */
1886 const char *pn
= history
[0].insn_mo
->name
;
1887 const char *tn
= ip
->insn_mo
->name
;
1888 if (strncmp (pn
, "macc", 4) == 0
1889 || strncmp (pn
, "dmacc", 5) == 0)
1891 /* Errata 21 - [D]DIV[U] after [D]MACC */
1892 if (strstr (tn
, "div"))
1895 /* VR4181A errata MD(1): "If a MULT, MULTU, DMULT or DMULTU
1896 instruction is executed immediately after a MACC or
1897 DMACC instruction, the result of [either instruction]
1899 if (strncmp (tn
, "mult", 4) == 0
1900 || strncmp (tn
, "dmult", 5) == 0)
1903 /* Errata 23 - Continuous DMULT[U]/DMACC instructions.
1904 Applies on top of VR4181A MD(1) errata. */
1905 if (pn
[0] == 'd' && strncmp (tn
, "dmacc", 5) == 0)
1908 /* Errata 24 - MT{LO,HI} after [D]MACC */
1909 if (strcmp (tn
, "mtlo") == 0
1910 || strcmp (tn
, "mthi") == 0)
1913 else if (strncmp (pn
, "dmult", 5) == 0
1914 && (strncmp (tn
, "dmult", 5) == 0
1915 || strncmp (tn
, "dmacc", 5) == 0))
1917 /* Here is the rest of errata 23. */
1920 else if ((strncmp (pn
, "dmult", 5) == 0 || strstr (pn
, "div"))
1921 && (strncmp (tn
, "macc", 4) == 0
1922 || strncmp (tn
, "dmacc", 5) == 0))
1924 /* VR4181A errata MD(4): "If a MACC or DMACC instruction is
1925 executed immediately after a DMULT, DMULTU, DIV, DIVU,
1926 DDIV or DDIVU instruction, the result of the MACC or
1927 DMACC instruction is incorrect.". This partly overlaps
1928 the workaround for errata 23. */
1931 if (nops
< min_nops
)
1935 /* If we are being given a nop instruction, don't bother with
1936 one of the nops we would otherwise output. This will only
1937 happen when a nop instruction is used with mips_optimize set
1940 && ! mips_opts
.noreorder
1941 && ip
->insn_opcode
== (unsigned) (mips_opts
.mips16
? 0x6500 : 0))
1944 /* Now emit the right number of NOP instructions. */
1945 if (nops
> 0 && ! mips_opts
.noreorder
)
1948 unsigned long old_frag_offset
;
1950 struct insn_label_list
*l
;
1952 old_frag
= frag_now
;
1953 old_frag_offset
= frag_now_fix ();
1955 for (i
= 0; i
< nops
; i
++)
1960 listing_prev_line ();
1961 /* We may be at the start of a variant frag. In case we
1962 are, make sure there is enough space for the frag
1963 after the frags created by listing_prev_line. The
1964 argument to frag_grow here must be at least as large
1965 as the argument to all other calls to frag_grow in
1966 this file. We don't have to worry about being in the
1967 middle of a variant frag, because the variants insert
1968 all needed nop instructions themselves. */
1972 for (l
= insn_labels
; l
!= NULL
; l
= l
->next
)
1976 assert (S_GET_SEGMENT (l
->label
) == now_seg
);
1977 symbol_set_frag (l
->label
, frag_now
);
1978 val
= (valueT
) frag_now_fix ();
1979 /* mips16 text labels are stored as odd. */
1980 if (mips_opts
.mips16
)
1982 S_SET_VALUE (l
->label
, val
);
1985 #ifndef NO_ECOFF_DEBUGGING
1986 if (ECOFF_DEBUGGING
)
1987 ecoff_fix_loc (old_frag
, old_frag_offset
);
1990 else if (prev_nop_frag
!= NULL
)
1992 /* We have a frag holding nops we may be able to remove. If
1993 we don't need any nops, we can decrease the size of
1994 prev_nop_frag by the size of one instruction. If we do
1995 need some nops, we count them in prev_nops_required. */
1996 if (prev_nop_frag_since
== 0)
2000 prev_nop_frag
->fr_fix
-= mips_opts
.mips16
? 2 : 4;
2001 --prev_nop_frag_holds
;
2004 prev_nop_frag_required
+= nops
;
2008 if (prev_prev_nop
== 0)
2010 prev_nop_frag
->fr_fix
-= mips_opts
.mips16
? 2 : 4;
2011 --prev_nop_frag_holds
;
2014 ++prev_nop_frag_required
;
2017 if (prev_nop_frag_holds
<= prev_nop_frag_required
)
2018 prev_nop_frag
= NULL
;
2020 ++prev_nop_frag_since
;
2022 /* Sanity check: by the time we reach the second instruction
2023 after prev_nop_frag, we should have used up all the nops
2024 one way or another. */
2025 assert (prev_nop_frag_since
<= 1 || prev_nop_frag
== NULL
);
2030 /* The value passed to dwarf2_emit_insn is the distance between
2031 the beginning of the current instruction and the address that
2032 should be recorded in the debug tables. For MIPS16 debug info
2033 we want to use ISA-encoded addresses, so we pass -1 for an
2034 address higher by one than the current. */
2035 dwarf2_emit_insn (mips_opts
.mips16
? -1 : 0);
2038 /* Record the frag type before frag_var. */
2039 if (history
[0].frag
)
2040 prev_insn_frag_type
= history
[0].frag
->fr_type
;
2043 && *reloc_type
== BFD_RELOC_16_PCREL_S2
2044 && (pinfo
& INSN_UNCOND_BRANCH_DELAY
|| pinfo
& INSN_COND_BRANCH_DELAY
2045 || pinfo
& INSN_COND_BRANCH_LIKELY
)
2046 && mips_relax_branch
2047 /* Don't try branch relaxation within .set nomacro, or within
2048 .set noat if we use $at for PIC computations. If it turns
2049 out that the branch was out-of-range, we'll get an error. */
2050 && !mips_opts
.warn_about_macros
2051 && !(mips_opts
.noat
&& mips_pic
!= NO_PIC
)
2052 && !mips_opts
.mips16
)
2054 relaxed_branch
= TRUE
;
2055 f
= frag_var (rs_machine_dependent
,
2056 relaxed_branch_length
2058 (pinfo
& INSN_UNCOND_BRANCH_DELAY
) ? -1
2059 : (pinfo
& INSN_COND_BRANCH_LIKELY
) ? 1 : 0), 4,
2061 (pinfo
& INSN_UNCOND_BRANCH_DELAY
,
2062 pinfo
& INSN_COND_BRANCH_LIKELY
,
2063 pinfo
& INSN_WRITE_GPR_31
,
2065 address_expr
->X_add_symbol
,
2066 address_expr
->X_add_number
,
2068 *reloc_type
= BFD_RELOC_UNUSED
;
2070 else if (*reloc_type
> BFD_RELOC_UNUSED
)
2072 /* We need to set up a variant frag. */
2073 assert (mips_opts
.mips16
&& address_expr
!= NULL
);
2074 f
= frag_var (rs_machine_dependent
, 4, 0,
2075 RELAX_MIPS16_ENCODE (*reloc_type
- BFD_RELOC_UNUSED
,
2076 mips16_small
, mips16_ext
,
2078 & INSN_UNCOND_BRANCH_DELAY
),
2079 history
[0].mips16_absolute_jump_p
),
2080 make_expr_symbol (address_expr
), 0, NULL
);
2082 else if (mips_opts
.mips16
2084 && *reloc_type
!= BFD_RELOC_MIPS16_JMP
)
2086 /* Make sure there is enough room to swap this instruction with
2087 a following jump instruction. */
2093 if (mips_opts
.mips16
2094 && mips_opts
.noreorder
2095 && (prev_pinfo
& INSN_UNCOND_BRANCH_DELAY
) != 0)
2096 as_warn (_("extended instruction in delay slot"));
2098 if (mips_relax
.sequence
)
2100 /* If we've reached the end of this frag, turn it into a variant
2101 frag and record the information for the instructions we've
2103 if (frag_room () < 4)
2104 relax_close_frag ();
2105 mips_relax
.sizes
[mips_relax
.sequence
- 1] += 4;
2108 if (mips_relax
.sequence
!= 2)
2109 mips_macro_warning
.sizes
[0] += 4;
2110 if (mips_relax
.sequence
!= 1)
2111 mips_macro_warning
.sizes
[1] += 4;
2116 fixp
[0] = fixp
[1] = fixp
[2] = NULL
;
2117 if (address_expr
!= NULL
&& *reloc_type
<= BFD_RELOC_UNUSED
)
2119 if (address_expr
->X_op
== O_constant
)
2123 switch (*reloc_type
)
2126 ip
->insn_opcode
|= address_expr
->X_add_number
;
2129 case BFD_RELOC_MIPS_HIGHEST
:
2130 tmp
= (address_expr
->X_add_number
+ 0x800080008000ull
) >> 48;
2131 ip
->insn_opcode
|= tmp
& 0xffff;
2134 case BFD_RELOC_MIPS_HIGHER
:
2135 tmp
= (address_expr
->X_add_number
+ 0x80008000ull
) >> 32;
2136 ip
->insn_opcode
|= tmp
& 0xffff;
2139 case BFD_RELOC_HI16_S
:
2140 tmp
= (address_expr
->X_add_number
+ 0x8000) >> 16;
2141 ip
->insn_opcode
|= tmp
& 0xffff;
2144 case BFD_RELOC_HI16
:
2145 ip
->insn_opcode
|= (address_expr
->X_add_number
>> 16) & 0xffff;
2148 case BFD_RELOC_UNUSED
:
2149 case BFD_RELOC_LO16
:
2150 case BFD_RELOC_MIPS_GOT_DISP
:
2151 ip
->insn_opcode
|= address_expr
->X_add_number
& 0xffff;
2154 case BFD_RELOC_MIPS_JMP
:
2155 if ((address_expr
->X_add_number
& 3) != 0)
2156 as_bad (_("jump to misaligned address (0x%lx)"),
2157 (unsigned long) address_expr
->X_add_number
);
2158 if (address_expr
->X_add_number
& ~0xfffffff)
2159 as_bad (_("jump address range overflow (0x%lx)"),
2160 (unsigned long) address_expr
->X_add_number
);
2161 ip
->insn_opcode
|= (address_expr
->X_add_number
>> 2) & 0x3ffffff;
2164 case BFD_RELOC_MIPS16_JMP
:
2165 if ((address_expr
->X_add_number
& 3) != 0)
2166 as_bad (_("jump to misaligned address (0x%lx)"),
2167 (unsigned long) address_expr
->X_add_number
);
2168 if (address_expr
->X_add_number
& ~0xfffffff)
2169 as_bad (_("jump address range overflow (0x%lx)"),
2170 (unsigned long) address_expr
->X_add_number
);
2172 (((address_expr
->X_add_number
& 0x7c0000) << 3)
2173 | ((address_expr
->X_add_number
& 0xf800000) >> 7)
2174 | ((address_expr
->X_add_number
& 0x3fffc) >> 2));
2177 case BFD_RELOC_16_PCREL_S2
:
2184 else if (*reloc_type
< BFD_RELOC_UNUSED
)
2187 reloc_howto_type
*howto
;
2190 /* In a compound relocation, it is the final (outermost)
2191 operator that determines the relocated field. */
2192 for (i
= 1; i
< 3; i
++)
2193 if (reloc_type
[i
] == BFD_RELOC_UNUSED
)
2196 howto
= bfd_reloc_type_lookup (stdoutput
, reloc_type
[i
- 1]);
2197 fixp
[0] = fix_new_exp (frag_now
, f
- frag_now
->fr_literal
,
2198 bfd_get_reloc_size(howto
),
2200 reloc_type
[0] == BFD_RELOC_16_PCREL_S2
,
2203 /* These relocations can have an addend that won't fit in
2204 4 octets for 64bit assembly. */
2206 && ! howto
->partial_inplace
2207 && (reloc_type
[0] == BFD_RELOC_16
2208 || reloc_type
[0] == BFD_RELOC_32
2209 || reloc_type
[0] == BFD_RELOC_MIPS_JMP
2210 || reloc_type
[0] == BFD_RELOC_HI16_S
2211 || reloc_type
[0] == BFD_RELOC_LO16
2212 || reloc_type
[0] == BFD_RELOC_GPREL16
2213 || reloc_type
[0] == BFD_RELOC_MIPS_LITERAL
2214 || reloc_type
[0] == BFD_RELOC_GPREL32
2215 || reloc_type
[0] == BFD_RELOC_64
2216 || reloc_type
[0] == BFD_RELOC_CTOR
2217 || reloc_type
[0] == BFD_RELOC_MIPS_SUB
2218 || reloc_type
[0] == BFD_RELOC_MIPS_HIGHEST
2219 || reloc_type
[0] == BFD_RELOC_MIPS_HIGHER
2220 || reloc_type
[0] == BFD_RELOC_MIPS_SCN_DISP
2221 || reloc_type
[0] == BFD_RELOC_MIPS_REL16
2222 || reloc_type
[0] == BFD_RELOC_MIPS_RELGOT
2223 || reloc_type
[0] == BFD_RELOC_MIPS16_GPREL
2224 || reloc_type
[0] == BFD_RELOC_MIPS16_HI16_S
2225 || reloc_type
[0] == BFD_RELOC_MIPS16_LO16
))
2226 fixp
[0]->fx_no_overflow
= 1;
2228 if (mips_relax
.sequence
)
2230 if (mips_relax
.first_fixup
== 0)
2231 mips_relax
.first_fixup
= fixp
[0];
2233 else if (reloc_needs_lo_p (*reloc_type
))
2235 struct mips_hi_fixup
*hi_fixup
;
2237 /* Reuse the last entry if it already has a matching %lo. */
2238 hi_fixup
= mips_hi_fixup_list
;
2240 || !fixup_has_matching_lo_p (hi_fixup
->fixp
))
2242 hi_fixup
= ((struct mips_hi_fixup
*)
2243 xmalloc (sizeof (struct mips_hi_fixup
)));
2244 hi_fixup
->next
= mips_hi_fixup_list
;
2245 mips_hi_fixup_list
= hi_fixup
;
2247 hi_fixup
->fixp
= fixp
[0];
2248 hi_fixup
->seg
= now_seg
;
2251 /* Add fixups for the second and third relocations, if given.
2252 Note that the ABI allows the second relocation to be
2253 against RSS_UNDEF, RSS_GP, RSS_GP0 or RSS_LOC. At the
2254 moment we only use RSS_UNDEF, but we could add support
2255 for the others if it ever becomes necessary. */
2256 for (i
= 1; i
< 3; i
++)
2257 if (reloc_type
[i
] != BFD_RELOC_UNUSED
)
2259 fixp
[i
] = fix_new (frag_now
, fixp
[0]->fx_where
,
2260 fixp
[0]->fx_size
, NULL
, 0,
2261 FALSE
, reloc_type
[i
]);
2263 /* Use fx_tcbit to mark compound relocs. */
2264 fixp
[0]->fx_tcbit
= 1;
2265 fixp
[i
]->fx_tcbit
= 1;
2270 if (! mips_opts
.mips16
)
2271 md_number_to_chars (f
, ip
->insn_opcode
, 4);
2272 else if (*reloc_type
== BFD_RELOC_MIPS16_JMP
)
2274 md_number_to_chars (f
, ip
->insn_opcode
>> 16, 2);
2275 md_number_to_chars (f
+ 2, ip
->insn_opcode
& 0xffff, 2);
2281 md_number_to_chars (f
, 0xf000 | ip
->extend
, 2);
2284 md_number_to_chars (f
, ip
->insn_opcode
, 2);
2287 /* Update the register mask information. */
2288 if (! mips_opts
.mips16
)
2290 if (pinfo
& INSN_WRITE_GPR_D
)
2291 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
);
2292 if ((pinfo
& (INSN_WRITE_GPR_T
| INSN_READ_GPR_T
)) != 0)
2293 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
);
2294 if (pinfo
& INSN_READ_GPR_S
)
2295 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> OP_SH_RS
) & OP_MASK_RS
);
2296 if (pinfo
& INSN_WRITE_GPR_31
)
2297 mips_gprmask
|= 1 << RA
;
2298 if (pinfo
& INSN_WRITE_FPR_D
)
2299 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FD
) & OP_MASK_FD
);
2300 if ((pinfo
& (INSN_WRITE_FPR_S
| INSN_READ_FPR_S
)) != 0)
2301 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FS
) & OP_MASK_FS
);
2302 if ((pinfo
& (INSN_WRITE_FPR_T
| INSN_READ_FPR_T
)) != 0)
2303 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FT
) & OP_MASK_FT
);
2304 if ((pinfo
& INSN_READ_FPR_R
) != 0)
2305 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FR
) & OP_MASK_FR
);
2306 if (pinfo
& INSN_COP
)
2308 /* We don't keep enough information to sort these cases out.
2309 The itbl support does keep this information however, although
2310 we currently don't support itbl fprmats as part of the cop
2311 instruction. May want to add this support in the future. */
2313 /* Never set the bit for $0, which is always zero. */
2314 mips_gprmask
&= ~1 << 0;
2318 if (pinfo
& (MIPS16_INSN_WRITE_X
| MIPS16_INSN_READ_X
))
2319 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_RX
)
2320 & MIPS16OP_MASK_RX
);
2321 if (pinfo
& (MIPS16_INSN_WRITE_Y
| MIPS16_INSN_READ_Y
))
2322 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_RY
)
2323 & MIPS16OP_MASK_RY
);
2324 if (pinfo
& MIPS16_INSN_WRITE_Z
)
2325 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_RZ
)
2326 & MIPS16OP_MASK_RZ
);
2327 if (pinfo
& (MIPS16_INSN_WRITE_T
| MIPS16_INSN_READ_T
))
2328 mips_gprmask
|= 1 << TREG
;
2329 if (pinfo
& (MIPS16_INSN_WRITE_SP
| MIPS16_INSN_READ_SP
))
2330 mips_gprmask
|= 1 << SP
;
2331 if (pinfo
& (MIPS16_INSN_WRITE_31
| MIPS16_INSN_READ_31
))
2332 mips_gprmask
|= 1 << RA
;
2333 if (pinfo
& MIPS16_INSN_WRITE_GPR_Y
)
2334 mips_gprmask
|= 1 << MIPS16OP_EXTRACT_REG32R (ip
->insn_opcode
);
2335 if (pinfo
& MIPS16_INSN_READ_Z
)
2336 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_MOVE32Z
)
2337 & MIPS16OP_MASK_MOVE32Z
);
2338 if (pinfo
& MIPS16_INSN_READ_GPR_X
)
2339 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_REGR32
)
2340 & MIPS16OP_MASK_REGR32
);
2343 if (mips_relax
.sequence
!= 2 && !mips_opts
.noreorder
)
2345 /* Filling the branch delay slot is more complex. We try to
2346 switch the branch with the previous instruction, which we can
2347 do if the previous instruction does not set up a condition
2348 that the branch tests and if the branch is not itself the
2349 target of any branch. */
2350 if ((pinfo
& INSN_UNCOND_BRANCH_DELAY
)
2351 || (pinfo
& INSN_COND_BRANCH_DELAY
))
2353 if (mips_optimize
< 2
2354 /* If we have seen .set volatile or .set nomove, don't
2356 || mips_opts
.nomove
!= 0
2357 /* If we had to emit any NOP instructions, then we
2358 already know we can not swap. */
2360 /* If we don't even know the previous insn, we can not
2362 || ! history
[0].valid_p
2363 /* If the previous insn is already in a branch delay
2364 slot, then we can not swap. */
2365 || history
[0].delay_slot_p
2366 /* If the previous previous insn was in a .set
2367 noreorder, we can't swap. Actually, the MIPS
2368 assembler will swap in this situation. However, gcc
2369 configured -with-gnu-as will generate code like
2375 in which we can not swap the bne and INSN. If gcc is
2376 not configured -with-gnu-as, it does not output the
2377 .set pseudo-ops. We don't have to check
2378 history[0].noreorder_p, because history[0].valid_p will
2379 be 0 in that case. We don't want to use
2380 history[1].valid_p, because we do want to be able
2381 to swap at the start of a function. */
2382 || history
[1].noreorder_p
2383 /* If the branch is itself the target of a branch, we
2384 can not swap. We cheat on this; all we check for is
2385 whether there is a label on this instruction. If
2386 there are any branches to anything other than a
2387 label, users must use .set noreorder. */
2388 || insn_labels
!= NULL
2389 /* If the previous instruction is in a variant frag
2390 other than this branch's one, we cannot do the swap.
2391 This does not apply to the mips16, which uses variant
2392 frags for different purposes. */
2393 || (! mips_opts
.mips16
2394 && prev_insn_frag_type
== rs_machine_dependent
)
2395 /* If the branch reads the condition codes, we don't
2396 even try to swap, because in the sequence
2401 we can not swap, and I don't feel like handling that
2403 || (! mips_opts
.mips16
2404 && (pinfo
& INSN_READ_COND_CODE
)
2405 && ! cop_interlocks
)
2406 /* We can not swap with an instruction that requires a
2407 delay slot, because the target of the branch might
2408 interfere with that instruction. */
2409 || (! mips_opts
.mips16
2411 /* Itbl support may require additional care here. */
2412 & (INSN_LOAD_COPROC_DELAY
2413 | INSN_COPROC_MOVE_DELAY
2414 | INSN_WRITE_COND_CODE
))
2415 && ! cop_interlocks
)
2416 || (! (hilo_interlocks
2417 || (mips_opts
.arch
== CPU_R3900
&& (pinfo
& INSN_MULT
)))
2421 || (! mips_opts
.mips16
2422 && (prev_pinfo
& INSN_LOAD_MEMORY_DELAY
)
2423 && ! gpr_interlocks
)
2424 || (! mips_opts
.mips16
2425 /* Itbl support may require additional care here. */
2426 && (prev_pinfo
& INSN_COPROC_MEMORY_DELAY
)
2427 && ! cop_mem_interlocks
)
2428 /* We can not swap with a branch instruction. */
2430 & (INSN_UNCOND_BRANCH_DELAY
2431 | INSN_COND_BRANCH_DELAY
2432 | INSN_COND_BRANCH_LIKELY
))
2433 /* We do not swap with a trap instruction, since it
2434 complicates trap handlers to have the trap
2435 instruction be in a delay slot. */
2436 || (prev_pinfo
& INSN_TRAP
)
2437 /* If the branch reads a register that the previous
2438 instruction sets, we can not swap. */
2439 || (! mips_opts
.mips16
2440 && (prev_pinfo
& INSN_WRITE_GPR_T
)
2441 && insn_uses_reg (ip
,
2442 ((history
[0].insn_opcode
>> OP_SH_RT
)
2445 || (! mips_opts
.mips16
2446 && (prev_pinfo
& INSN_WRITE_GPR_D
)
2447 && insn_uses_reg (ip
,
2448 ((history
[0].insn_opcode
>> OP_SH_RD
)
2451 || (mips_opts
.mips16
2452 && (((prev_pinfo
& MIPS16_INSN_WRITE_X
)
2453 && insn_uses_reg (ip
,
2454 ((history
[0].insn_opcode
2456 & MIPS16OP_MASK_RX
),
2458 || ((prev_pinfo
& MIPS16_INSN_WRITE_Y
)
2459 && insn_uses_reg (ip
,
2460 ((history
[0].insn_opcode
2462 & MIPS16OP_MASK_RY
),
2464 || ((prev_pinfo
& MIPS16_INSN_WRITE_Z
)
2465 && insn_uses_reg (ip
,
2466 ((history
[0].insn_opcode
2468 & MIPS16OP_MASK_RZ
),
2470 || ((prev_pinfo
& MIPS16_INSN_WRITE_T
)
2471 && insn_uses_reg (ip
, TREG
, MIPS_GR_REG
))
2472 || ((prev_pinfo
& MIPS16_INSN_WRITE_31
)
2473 && insn_uses_reg (ip
, RA
, MIPS_GR_REG
))
2474 || ((prev_pinfo
& MIPS16_INSN_WRITE_GPR_Y
)
2475 && insn_uses_reg (ip
,
2476 MIPS16OP_EXTRACT_REG32R
2477 (history
[0].insn_opcode
),
2479 /* If the branch writes a register that the previous
2480 instruction sets, we can not swap (we know that
2481 branches write only to RD or to $31). */
2482 || (! mips_opts
.mips16
2483 && (prev_pinfo
& INSN_WRITE_GPR_T
)
2484 && (((pinfo
& INSN_WRITE_GPR_D
)
2485 && (((history
[0].insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
)
2486 == ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)))
2487 || ((pinfo
& INSN_WRITE_GPR_31
)
2488 && (((history
[0].insn_opcode
>> OP_SH_RT
)
2491 || (! mips_opts
.mips16
2492 && (prev_pinfo
& INSN_WRITE_GPR_D
)
2493 && (((pinfo
& INSN_WRITE_GPR_D
)
2494 && (((history
[0].insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)
2495 == ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)))
2496 || ((pinfo
& INSN_WRITE_GPR_31
)
2497 && (((history
[0].insn_opcode
>> OP_SH_RD
)
2500 || (mips_opts
.mips16
2501 && (pinfo
& MIPS16_INSN_WRITE_31
)
2502 && ((prev_pinfo
& MIPS16_INSN_WRITE_31
)
2503 || ((prev_pinfo
& MIPS16_INSN_WRITE_GPR_Y
)
2504 && (MIPS16OP_EXTRACT_REG32R (history
[0].insn_opcode
)
2506 /* If the branch writes a register that the previous
2507 instruction reads, we can not swap (we know that
2508 branches only write to RD or to $31). */
2509 || (! mips_opts
.mips16
2510 && (pinfo
& INSN_WRITE_GPR_D
)
2511 && insn_uses_reg (&history
[0],
2512 ((ip
->insn_opcode
>> OP_SH_RD
)
2515 || (! mips_opts
.mips16
2516 && (pinfo
& INSN_WRITE_GPR_31
)
2517 && insn_uses_reg (&history
[0], RA
, MIPS_GR_REG
))
2518 || (mips_opts
.mips16
2519 && (pinfo
& MIPS16_INSN_WRITE_31
)
2520 && insn_uses_reg (&history
[0], RA
, MIPS_GR_REG
))
2521 /* If the previous previous instruction has a load
2522 delay, and sets a register that the branch reads, we
2524 || (! mips_opts
.mips16
2525 /* Itbl support may require additional care here. */
2526 && (((history
[1].insn_mo
->pinfo
& INSN_LOAD_COPROC_DELAY
)
2527 && ! cop_interlocks
)
2528 || ((history
[1].insn_mo
->pinfo
2529 & INSN_LOAD_MEMORY_DELAY
)
2530 && ! gpr_interlocks
))
2531 && insn_uses_reg (ip
,
2532 ((history
[1].insn_opcode
>> OP_SH_RT
)
2535 /* If one instruction sets a condition code and the
2536 other one uses a condition code, we can not swap. */
2537 || ((pinfo
& INSN_READ_COND_CODE
)
2538 && (prev_pinfo
& INSN_WRITE_COND_CODE
))
2539 || ((pinfo
& INSN_WRITE_COND_CODE
)
2540 && (prev_pinfo
& INSN_READ_COND_CODE
))
2541 /* If the previous instruction uses the PC, we can not
2543 || (mips_opts
.mips16
2544 && (prev_pinfo
& MIPS16_INSN_READ_PC
))
2545 /* If the previous instruction was extended, we can not
2547 || (mips_opts
.mips16
&& history
[0].extended_p
)
2548 /* If the previous instruction had a fixup in mips16
2549 mode, we can not swap. This normally means that the
2550 previous instruction was a 4 byte branch anyhow. */
2551 || (mips_opts
.mips16
&& history
[0].fixp
[0])
2552 /* If the previous instruction is a sync, sync.l, or
2553 sync.p, we can not swap. */
2554 || (prev_pinfo
& INSN_SYNC
))
2556 /* We could do even better for unconditional branches to
2557 portions of this object file; we could pick up the
2558 instruction at the destination, put it in the delay
2559 slot, and bump the destination address. */
2561 if (mips_relax
.sequence
)
2562 mips_relax
.sizes
[mips_relax
.sequence
- 1] += 4;
2563 /* Update the previous insn information. */
2564 history
[1].insn_mo
= ip
->insn_mo
;
2565 history
[1].use_extend
= ip
->use_extend
;
2566 history
[1].extend
= ip
->extend
;
2567 history
[1].insn_opcode
= ip
->insn_opcode
;
2568 history
[0].insn_mo
= &dummy_opcode
;
2572 /* It looks like we can actually do the swap. */
2573 if (! mips_opts
.mips16
)
2578 prev_f
= history
[0].frag
->fr_literal
+ history
[0].where
;
2579 if (!relaxed_branch
)
2581 /* If this is not a relaxed branch, then just
2582 swap the instructions. */
2583 memcpy (temp
, prev_f
, 4);
2584 memcpy (prev_f
, f
, 4);
2585 memcpy (f
, temp
, 4);
2589 /* If this is a relaxed branch, then we move the
2590 instruction to be placed in the delay slot to
2591 the current frag, shrinking the fixed part of
2592 the originating frag. If the branch occupies
2593 the tail of the latter, we move it backwards,
2594 into the space freed by the moved instruction. */
2596 memcpy (f
, prev_f
, 4);
2597 history
[0].frag
->fr_fix
-= 4;
2598 if (history
[0].frag
->fr_type
== rs_machine_dependent
)
2599 memmove (prev_f
, prev_f
+ 4, history
[0].frag
->fr_var
);
2602 if (history
[0].fixp
[0])
2604 history
[0].fixp
[0]->fx_frag
= frag_now
;
2605 history
[0].fixp
[0]->fx_where
= f
- frag_now
->fr_literal
;
2607 if (history
[0].fixp
[1])
2609 history
[0].fixp
[1]->fx_frag
= frag_now
;
2610 history
[0].fixp
[1]->fx_where
= f
- frag_now
->fr_literal
;
2612 if (history
[0].fixp
[2])
2614 history
[0].fixp
[2]->fx_frag
= frag_now
;
2615 history
[0].fixp
[2]->fx_where
= f
- frag_now
->fr_literal
;
2617 if (history
[0].fixp
[0] && HAVE_NEWABI
2618 && history
[0].frag
!= frag_now
2619 && (history
[0].fixp
[0]->fx_r_type
2620 == BFD_RELOC_MIPS_GOT_DISP
2621 || (history
[0].fixp
[0]->fx_r_type
2622 == BFD_RELOC_MIPS_CALL16
)))
2624 /* To avoid confusion in tc_gen_reloc, we must
2625 ensure that this does not become a variant
2627 force_new_frag
= TRUE
;
2630 if (!relaxed_branch
)
2634 fixp
[0]->fx_frag
= history
[0].frag
;
2635 fixp
[0]->fx_where
= history
[0].where
;
2639 fixp
[1]->fx_frag
= history
[0].frag
;
2640 fixp
[1]->fx_where
= history
[0].where
;
2644 fixp
[2]->fx_frag
= history
[0].frag
;
2645 fixp
[2]->fx_where
= history
[0].where
;
2648 else if (history
[0].frag
->fr_type
== rs_machine_dependent
)
2651 fixp
[0]->fx_where
-= 4;
2653 fixp
[1]->fx_where
-= 4;
2655 fixp
[2]->fx_where
-= 4;
2663 assert (history
[0].fixp
[0] == NULL
);
2664 assert (history
[0].fixp
[1] == NULL
);
2665 assert (history
[0].fixp
[2] == NULL
);
2666 prev_f
= history
[0].frag
->fr_literal
+ history
[0].where
;
2667 memcpy (temp
, prev_f
, 2);
2668 memcpy (prev_f
, f
, 2);
2669 if (*reloc_type
!= BFD_RELOC_MIPS16_JMP
)
2671 assert (*reloc_type
== BFD_RELOC_UNUSED
);
2672 memcpy (f
, temp
, 2);
2676 memcpy (f
, f
+ 2, 2);
2677 memcpy (f
+ 2, temp
, 2);
2681 fixp
[0]->fx_frag
= history
[0].frag
;
2682 fixp
[0]->fx_where
= history
[0].where
;
2686 fixp
[1]->fx_frag
= history
[0].frag
;
2687 fixp
[1]->fx_where
= history
[0].where
;
2691 fixp
[2]->fx_frag
= history
[0].frag
;
2692 fixp
[2]->fx_where
= history
[0].where
;
2696 /* Update the previous insn information; leave history[0]
2698 history
[1].insn_mo
= ip
->insn_mo
;
2699 history
[1].use_extend
= ip
->use_extend
;
2700 history
[1].extend
= ip
->extend
;
2701 history
[1].insn_opcode
= ip
->insn_opcode
;
2703 history
[0].delay_slot_p
= 1;
2705 /* If that was an unconditional branch, forget the previous
2706 insn information. */
2707 if (pinfo
& INSN_UNCOND_BRANCH_DELAY
)
2709 history
[1].insn_mo
= &dummy_opcode
;
2710 history
[0].insn_mo
= &dummy_opcode
;
2713 history
[0].fixp
[0] = NULL
;
2714 history
[0].fixp
[1] = NULL
;
2715 history
[0].fixp
[2] = NULL
;
2716 history
[0].mips16_absolute_jump_p
= 0;
2717 history
[0].extended_p
= 0;
2719 else if (pinfo
& INSN_COND_BRANCH_LIKELY
)
2721 /* We don't yet optimize a branch likely. What we should do
2722 is look at the target, copy the instruction found there
2723 into the delay slot, and increment the branch to jump to
2724 the next instruction. */
2726 /* Update the previous insn information. */
2727 history
[1].insn_mo
= ip
->insn_mo
;
2728 history
[1].use_extend
= ip
->use_extend
;
2729 history
[1].extend
= ip
->extend
;
2730 history
[1].insn_opcode
= ip
->insn_opcode
;
2731 history
[0].insn_mo
= &dummy_opcode
;
2732 history
[0].fixp
[0] = NULL
;
2733 history
[0].fixp
[1] = NULL
;
2734 history
[0].fixp
[2] = NULL
;
2735 history
[0].mips16_absolute_jump_p
= 0;
2736 history
[0].extended_p
= 0;
2737 history
[0].delay_slot_p
= 1;
2741 /* Update the previous insn information. */
2743 history
[1].insn_mo
= &dummy_opcode
;
2746 history
[1].insn_mo
= history
[0].insn_mo
;
2747 history
[1].use_extend
= history
[0].use_extend
;
2748 history
[1].extend
= history
[0].extend
;
2749 history
[1].insn_opcode
= history
[0].insn_opcode
;
2751 history
[0].insn_mo
= ip
->insn_mo
;
2752 history
[0].use_extend
= ip
->use_extend
;
2753 history
[0].extend
= ip
->extend
;
2754 history
[0].insn_opcode
= ip
->insn_opcode
;
2756 /* Any time we see a branch, we always fill the delay slot
2757 immediately; since this insn is not a branch, we know it
2758 is not in a delay slot. */
2759 history
[0].delay_slot_p
= 0;
2761 history
[0].fixp
[0] = fixp
[0];
2762 history
[0].fixp
[1] = fixp
[1];
2763 history
[0].fixp
[2] = fixp
[2];
2764 history
[0].mips16_absolute_jump_p
= (reloc_type
[0]
2765 == BFD_RELOC_MIPS16_JMP
);
2766 if (mips_opts
.mips16
)
2767 history
[0].extended_p
= (ip
->use_extend
2768 || *reloc_type
> BFD_RELOC_UNUSED
);
2771 history
[1].noreorder_p
= history
[0].noreorder_p
;
2772 history
[0].noreorder_p
= 0;
2773 history
[0].frag
= frag_now
;
2774 history
[0].where
= f
- frag_now
->fr_literal
;
2775 history
[0].valid_p
= 1;
2777 else if (mips_relax
.sequence
!= 2)
2779 /* We need to record a bit of information even when we are not
2780 reordering, in order to determine the base address for mips16
2781 PC relative relocs. */
2782 history
[1].insn_mo
= history
[0].insn_mo
;
2783 history
[1].use_extend
= history
[0].use_extend
;
2784 history
[1].extend
= history
[0].extend
;
2785 history
[1].insn_opcode
= history
[0].insn_opcode
;
2786 history
[0].insn_mo
= ip
->insn_mo
;
2787 history
[0].use_extend
= ip
->use_extend
;
2788 history
[0].extend
= ip
->extend
;
2789 history
[0].insn_opcode
= ip
->insn_opcode
;
2790 history
[0].mips16_absolute_jump_p
= (reloc_type
[0]
2791 == BFD_RELOC_MIPS16_JMP
);
2792 history
[1].noreorder_p
= history
[0].noreorder_p
;
2793 history
[0].noreorder_p
= 1;
2796 /* We just output an insn, so the next one doesn't have a label. */
2797 mips_clear_insn_labels ();
2800 /* This function forgets that there was any previous instruction or
2801 label. If PRESERVE is non-zero, it remembers enough information to
2802 know whether nops are needed before a noreorder section. */
2805 mips_no_prev_insn (int preserve
)
2809 history
[0].insn_mo
= &dummy_opcode
;
2810 history
[1].insn_mo
= &dummy_opcode
;
2811 prev_nop_frag
= NULL
;
2812 prev_nop_frag_holds
= 0;
2813 prev_nop_frag_required
= 0;
2814 prev_nop_frag_since
= 0;
2816 history
[0].valid_p
= 0;
2817 history
[0].delay_slot_p
= 0;
2818 history
[0].noreorder_p
= 0;
2819 history
[0].extended_p
= 0;
2820 history
[0].mips16_absolute_jump_p
= 0;
2821 history
[1].noreorder_p
= 0;
2822 mips_clear_insn_labels ();
2825 /* This function must be called whenever we turn on noreorder or emit
2826 something other than instructions. It inserts any NOPS which might
2827 be needed by the previous instruction, and clears the information
2828 kept for the previous instructions. The INSNS parameter is true if
2829 instructions are to follow. */
2832 mips_emit_delays (bfd_boolean insns
)
2834 if (! mips_opts
.noreorder
)
2839 if ((! mips_opts
.mips16
2840 && ((history
[0].insn_mo
->pinfo
2841 & (INSN_LOAD_COPROC_DELAY
2842 | INSN_COPROC_MOVE_DELAY
2843 | INSN_WRITE_COND_CODE
))
2844 && ! cop_interlocks
))
2845 || (! hilo_interlocks
2846 && (history
[0].insn_mo
->pinfo
2849 || (! mips_opts
.mips16
2850 && (history
[0].insn_mo
->pinfo
& INSN_LOAD_MEMORY_DELAY
)
2851 && ! gpr_interlocks
)
2852 || (! mips_opts
.mips16
2853 && (history
[0].insn_mo
->pinfo
& INSN_COPROC_MEMORY_DELAY
)
2854 && ! cop_mem_interlocks
))
2856 /* Itbl support may require additional care here. */
2858 if ((! mips_opts
.mips16
2859 && ((history
[0].insn_mo
->pinfo
& INSN_WRITE_COND_CODE
)
2860 && ! cop_interlocks
))
2861 || (! hilo_interlocks
2862 && ((history
[0].insn_mo
->pinfo
& INSN_READ_HI
)
2863 || (history
[0].insn_mo
->pinfo
& INSN_READ_LO
))))
2866 if (history
[0].noreorder_p
)
2869 else if ((! mips_opts
.mips16
2870 && ((history
[1].insn_mo
->pinfo
& INSN_WRITE_COND_CODE
)
2871 && ! cop_interlocks
))
2872 || (! hilo_interlocks
2873 && ((history
[1].insn_mo
->pinfo
& INSN_READ_HI
)
2874 || (history
[1].insn_mo
->pinfo
& INSN_READ_LO
))))
2876 /* Itbl support may require additional care here. */
2877 if (! history
[1].noreorder_p
)
2881 if (mips_fix_vr4120
&& history
[0].insn_mo
->name
)
2884 const char *pn
= history
[0].insn_mo
->name
;
2885 if (strncmp (pn
, "macc", 4) == 0
2886 || strncmp (pn
, "dmacc", 5) == 0
2887 || strncmp (pn
, "dmult", 5) == 0
2888 || strstr (pn
, "div"))
2890 if (nops
< min_nops
)
2896 struct insn_label_list
*l
;
2900 /* Record the frag which holds the nop instructions, so
2901 that we can remove them if we don't need them. */
2902 frag_grow (mips_opts
.mips16
? nops
* 2 : nops
* 4);
2903 prev_nop_frag
= frag_now
;
2904 prev_nop_frag_holds
= nops
;
2905 prev_nop_frag_required
= 0;
2906 prev_nop_frag_since
= 0;
2909 for (; nops
> 0; --nops
)
2914 /* Move on to a new frag, so that it is safe to simply
2915 decrease the size of prev_nop_frag. */
2916 frag_wane (frag_now
);
2920 for (l
= insn_labels
; l
!= NULL
; l
= l
->next
)
2924 assert (S_GET_SEGMENT (l
->label
) == now_seg
);
2925 symbol_set_frag (l
->label
, frag_now
);
2926 val
= (valueT
) frag_now_fix ();
2927 /* mips16 text labels are stored as odd. */
2928 if (mips_opts
.mips16
)
2930 S_SET_VALUE (l
->label
, val
);
2935 /* Mark instruction labels in mips16 mode. */
2937 mips16_mark_labels ();
2939 mips_no_prev_insn (insns
);
2942 /* Set up global variables for the start of a new macro. */
2947 memset (&mips_macro_warning
.sizes
, 0, sizeof (mips_macro_warning
.sizes
));
2948 mips_macro_warning
.delay_slot_p
= (mips_opts
.noreorder
2949 && (history
[0].insn_mo
->pinfo
2950 & (INSN_UNCOND_BRANCH_DELAY
2951 | INSN_COND_BRANCH_DELAY
2952 | INSN_COND_BRANCH_LIKELY
)) != 0);
2955 /* Given that a macro is longer than 4 bytes, return the appropriate warning
2956 for it. Return null if no warning is needed. SUBTYPE is a bitmask of
2957 RELAX_DELAY_SLOT and RELAX_NOMACRO. */
2960 macro_warning (relax_substateT subtype
)
2962 if (subtype
& RELAX_DELAY_SLOT
)
2963 return _("Macro instruction expanded into multiple instructions"
2964 " in a branch delay slot");
2965 else if (subtype
& RELAX_NOMACRO
)
2966 return _("Macro instruction expanded into multiple instructions");
2971 /* Finish up a macro. Emit warnings as appropriate. */
2976 if (mips_macro_warning
.sizes
[0] > 4 || mips_macro_warning
.sizes
[1] > 4)
2978 relax_substateT subtype
;
2980 /* Set up the relaxation warning flags. */
2982 if (mips_macro_warning
.sizes
[1] > mips_macro_warning
.sizes
[0])
2983 subtype
|= RELAX_SECOND_LONGER
;
2984 if (mips_opts
.warn_about_macros
)
2985 subtype
|= RELAX_NOMACRO
;
2986 if (mips_macro_warning
.delay_slot_p
)
2987 subtype
|= RELAX_DELAY_SLOT
;
2989 if (mips_macro_warning
.sizes
[0] > 4 && mips_macro_warning
.sizes
[1] > 4)
2991 /* Either the macro has a single implementation or both
2992 implementations are longer than 4 bytes. Emit the
2994 const char *msg
= macro_warning (subtype
);
3000 /* One implementation might need a warning but the other
3001 definitely doesn't. */
3002 mips_macro_warning
.first_frag
->fr_subtype
|= subtype
;
3007 /* Read a macro's relocation codes from *ARGS and store them in *R.
3008 The first argument in *ARGS will be either the code for a single
3009 relocation or -1 followed by the three codes that make up a
3010 composite relocation. */
3013 macro_read_relocs (va_list *args
, bfd_reloc_code_real_type
*r
)
3017 next
= va_arg (*args
, int);
3019 r
[0] = (bfd_reloc_code_real_type
) next
;
3021 for (i
= 0; i
< 3; i
++)
3022 r
[i
] = (bfd_reloc_code_real_type
) va_arg (*args
, int);
3025 /* Build an instruction created by a macro expansion. This is passed
3026 a pointer to the count of instructions created so far, an
3027 expression, the name of the instruction to build, an operand format
3028 string, and corresponding arguments. */
3031 macro_build (expressionS
*ep
, const char *name
, const char *fmt
, ...)
3033 struct mips_cl_insn insn
;
3034 bfd_reloc_code_real_type r
[3];
3037 va_start (args
, fmt
);
3039 if (mips_opts
.mips16
)
3041 mips16_macro_build (ep
, name
, fmt
, args
);
3046 r
[0] = BFD_RELOC_UNUSED
;
3047 r
[1] = BFD_RELOC_UNUSED
;
3048 r
[2] = BFD_RELOC_UNUSED
;
3049 insn
.insn_mo
= (struct mips_opcode
*) hash_find (op_hash
, name
);
3050 assert (insn
.insn_mo
);
3051 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
3053 /* Search until we get a match for NAME. */
3056 /* It is assumed here that macros will never generate
3057 MDMX or MIPS-3D instructions. */
3058 if (strcmp (fmt
, insn
.insn_mo
->args
) == 0
3059 && insn
.insn_mo
->pinfo
!= INSN_MACRO
3060 && OPCODE_IS_MEMBER (insn
.insn_mo
,
3062 | (file_ase_mips16
? INSN_MIPS16
: 0)),
3064 && (mips_opts
.arch
!= CPU_R4650
|| (insn
.insn_mo
->pinfo
& FP_D
) == 0))
3068 assert (insn
.insn_mo
->name
);
3069 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
3072 insn
.insn_opcode
= insn
.insn_mo
->match
;
3090 insn
.insn_opcode
|= (va_arg (args
, int)
3091 & OP_MASK_SHAMT
) << OP_SH_SHAMT
;
3096 /* Note that in the macro case, these arguments are already
3097 in MSB form. (When handling the instruction in the
3098 non-macro case, these arguments are sizes from which
3099 MSB values must be calculated.) */
3100 insn
.insn_opcode
|= (va_arg (args
, int)
3101 & OP_MASK_INSMSB
) << OP_SH_INSMSB
;
3107 /* Note that in the macro case, these arguments are already
3108 in MSBD form. (When handling the instruction in the
3109 non-macro case, these arguments are sizes from which
3110 MSBD values must be calculated.) */
3111 insn
.insn_opcode
|= (va_arg (args
, int)
3112 & OP_MASK_EXTMSBD
) << OP_SH_EXTMSBD
;
3123 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_RT
;
3127 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_CODE
;
3132 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_FT
;
3138 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_RD
;
3143 int tmp
= va_arg (args
, int);
3145 insn
.insn_opcode
|= tmp
<< OP_SH_RT
;
3146 insn
.insn_opcode
|= tmp
<< OP_SH_RD
;
3152 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_FS
;
3159 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_SHAMT
;
3163 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_FD
;
3167 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_CODE20
;
3171 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_CODE19
;
3175 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_CODE2
;
3182 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_RS
;
3188 macro_read_relocs (&args
, r
);
3189 assert (*r
== BFD_RELOC_GPREL16
3190 || *r
== BFD_RELOC_MIPS_LITERAL
3191 || *r
== BFD_RELOC_MIPS_HIGHER
3192 || *r
== BFD_RELOC_HI16_S
3193 || *r
== BFD_RELOC_LO16
3194 || *r
== BFD_RELOC_MIPS_GOT16
3195 || *r
== BFD_RELOC_MIPS_CALL16
3196 || *r
== BFD_RELOC_MIPS_GOT_DISP
3197 || *r
== BFD_RELOC_MIPS_GOT_PAGE
3198 || *r
== BFD_RELOC_MIPS_GOT_OFST
3199 || *r
== BFD_RELOC_MIPS_GOT_LO16
3200 || *r
== BFD_RELOC_MIPS_CALL_LO16
);
3204 macro_read_relocs (&args
, r
);
3206 && (ep
->X_op
== O_constant
3207 || (ep
->X_op
== O_symbol
3208 && (*r
== BFD_RELOC_MIPS_HIGHEST
3209 || *r
== BFD_RELOC_HI16_S
3210 || *r
== BFD_RELOC_HI16
3211 || *r
== BFD_RELOC_GPREL16
3212 || *r
== BFD_RELOC_MIPS_GOT_HI16
3213 || *r
== BFD_RELOC_MIPS_CALL_HI16
))));
3217 assert (ep
!= NULL
);
3219 * This allows macro() to pass an immediate expression for
3220 * creating short branches without creating a symbol.
3221 * Note that the expression still might come from the assembly
3222 * input, in which case the value is not checked for range nor
3223 * is a relocation entry generated (yuck).
3225 if (ep
->X_op
== O_constant
)
3227 insn
.insn_opcode
|= (ep
->X_add_number
>> 2) & 0xffff;
3231 *r
= BFD_RELOC_16_PCREL_S2
;
3235 assert (ep
!= NULL
);
3236 *r
= BFD_RELOC_MIPS_JMP
;
3240 insn
.insn_opcode
|= va_arg (args
, unsigned long);
3249 assert (*r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
3251 append_insn (&insn
, ep
, r
);
3255 mips16_macro_build (expressionS
*ep
, const char *name
, const char *fmt
,
3258 struct mips_cl_insn insn
;
3259 bfd_reloc_code_real_type r
[3]
3260 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
3262 insn
.insn_mo
= (struct mips_opcode
*) hash_find (mips16_op_hash
, name
);
3263 assert (insn
.insn_mo
);
3264 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
3266 while (strcmp (fmt
, insn
.insn_mo
->args
) != 0
3267 || insn
.insn_mo
->pinfo
== INSN_MACRO
)
3270 assert (insn
.insn_mo
->name
);
3271 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
3274 insn
.insn_opcode
= insn
.insn_mo
->match
;
3275 insn
.use_extend
= FALSE
;
3294 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_RY
;
3299 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_RX
;
3303 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_RZ
;
3307 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_MOVE32Z
;
3317 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_REGR32
;
3324 regno
= va_arg (args
, int);
3325 regno
= ((regno
& 7) << 2) | ((regno
& 0x18) >> 3);
3326 insn
.insn_opcode
|= regno
<< MIPS16OP_SH_REG32R
;
3347 assert (ep
!= NULL
);
3349 if (ep
->X_op
!= O_constant
)
3350 *r
= (int) BFD_RELOC_UNUSED
+ c
;
3353 mips16_immed (NULL
, 0, c
, ep
->X_add_number
, FALSE
, FALSE
,
3354 FALSE
, &insn
.insn_opcode
, &insn
.use_extend
,
3357 *r
= BFD_RELOC_UNUSED
;
3363 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_IMM6
;
3370 assert (*r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
3372 append_insn (&insn
, ep
, r
);
3376 * Generate a "jalr" instruction with a relocation hint to the called
3377 * function. This occurs in NewABI PIC code.
3380 macro_build_jalr (expressionS
*ep
)
3389 macro_build (NULL
, "jalr", "d,s", RA
, PIC_CALL_REG
);
3391 fix_new_exp (frag_now
, f
- frag_now
->fr_literal
,
3392 4, ep
, FALSE
, BFD_RELOC_MIPS_JALR
);
3396 * Generate a "lui" instruction.
3399 macro_build_lui (expressionS
*ep
, int regnum
)
3401 expressionS high_expr
;
3402 struct mips_cl_insn insn
;
3403 bfd_reloc_code_real_type r
[3]
3404 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
3405 const char *name
= "lui";
3406 const char *fmt
= "t,u";
3408 assert (! mips_opts
.mips16
);
3412 if (high_expr
.X_op
== O_constant
)
3414 /* we can compute the instruction now without a relocation entry */
3415 high_expr
.X_add_number
= ((high_expr
.X_add_number
+ 0x8000)
3417 *r
= BFD_RELOC_UNUSED
;
3421 assert (ep
->X_op
== O_symbol
);
3422 /* _gp_disp is a special case, used from s_cpload.
3423 __gnu_local_gp is used if mips_no_shared. */
3424 assert (mips_pic
== NO_PIC
3426 && strcmp (S_GET_NAME (ep
->X_add_symbol
), "_gp_disp") == 0)
3427 || (! mips_in_shared
3428 && strcmp (S_GET_NAME (ep
->X_add_symbol
),
3429 "__gnu_local_gp") == 0));
3430 *r
= BFD_RELOC_HI16_S
;
3433 insn
.insn_mo
= (struct mips_opcode
*) hash_find (op_hash
, name
);
3434 assert (insn
.insn_mo
);
3435 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
3436 assert (strcmp (fmt
, insn
.insn_mo
->args
) == 0);
3438 insn
.insn_opcode
= insn
.insn_mo
->match
| (regnum
<< OP_SH_RT
);
3439 if (*r
== BFD_RELOC_UNUSED
)
3441 insn
.insn_opcode
|= high_expr
.X_add_number
;
3442 append_insn (&insn
, NULL
, r
);
3445 append_insn (&insn
, &high_expr
, r
);
3448 /* Generate a sequence of instructions to do a load or store from a constant
3449 offset off of a base register (breg) into/from a target register (treg),
3450 using AT if necessary. */
3452 macro_build_ldst_constoffset (expressionS
*ep
, const char *op
,
3453 int treg
, int breg
, int dbl
)
3455 assert (ep
->X_op
== O_constant
);
3457 /* Sign-extending 32-bit constants makes their handling easier. */
3458 if (! dbl
&& ! ((ep
->X_add_number
& ~((bfd_vma
) 0x7fffffff))
3459 == ~((bfd_vma
) 0x7fffffff)))
3461 if (ep
->X_add_number
& ~((bfd_vma
) 0xffffffff))
3462 as_bad (_("constant too large"));
3464 ep
->X_add_number
= (((ep
->X_add_number
& 0xffffffff) ^ 0x80000000)
3468 /* Right now, this routine can only handle signed 32-bit constants. */
3469 if (! IS_SEXT_32BIT_NUM(ep
->X_add_number
+ 0x8000))
3470 as_warn (_("operand overflow"));
3472 if (IS_SEXT_16BIT_NUM(ep
->X_add_number
))
3474 /* Signed 16-bit offset will fit in the op. Easy! */
3475 macro_build (ep
, op
, "t,o(b)", treg
, BFD_RELOC_LO16
, breg
);
3479 /* 32-bit offset, need multiple instructions and AT, like:
3480 lui $tempreg,const_hi (BFD_RELOC_HI16_S)
3481 addu $tempreg,$tempreg,$breg
3482 <op> $treg,const_lo($tempreg) (BFD_RELOC_LO16)
3483 to handle the complete offset. */
3484 macro_build_lui (ep
, AT
);
3485 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, AT
, breg
);
3486 macro_build (ep
, op
, "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
3489 as_bad (_("Macro used $at after \".set noat\""));
3494 * Generates code to set the $at register to true (one)
3495 * if reg is less than the immediate expression.
3498 set_at (int reg
, int unsignedp
)
3500 if (imm_expr
.X_op
== O_constant
3501 && imm_expr
.X_add_number
>= -0x8000
3502 && imm_expr
.X_add_number
< 0x8000)
3503 macro_build (&imm_expr
, unsignedp
? "sltiu" : "slti", "t,r,j",
3504 AT
, reg
, BFD_RELOC_LO16
);
3507 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
3508 macro_build (NULL
, unsignedp
? "sltu" : "slt", "d,v,t", AT
, reg
, AT
);
3513 normalize_constant_expr (expressionS
*ex
)
3515 if (ex
->X_op
== O_constant
&& HAVE_32BIT_GPRS
)
3516 ex
->X_add_number
= (((ex
->X_add_number
& 0xffffffff) ^ 0x80000000)
3520 /* Warn if an expression is not a constant. */
3523 check_absolute_expr (struct mips_cl_insn
*ip
, expressionS
*ex
)
3525 if (ex
->X_op
== O_big
)
3526 as_bad (_("unsupported large constant"));
3527 else if (ex
->X_op
!= O_constant
)
3528 as_bad (_("Instruction %s requires absolute expression"), ip
->insn_mo
->name
);
3530 normalize_constant_expr (ex
);
3533 /* Count the leading zeroes by performing a binary chop. This is a
3534 bulky bit of source, but performance is a LOT better for the
3535 majority of values than a simple loop to count the bits:
3536 for (lcnt = 0; (lcnt < 32); lcnt++)
3537 if ((v) & (1 << (31 - lcnt)))
3539 However it is not code size friendly, and the gain will drop a bit
3540 on certain cached systems.
3542 #define COUNT_TOP_ZEROES(v) \
3543 (((v) & ~0xffff) == 0 \
3544 ? ((v) & ~0xff) == 0 \
3545 ? ((v) & ~0xf) == 0 \
3546 ? ((v) & ~0x3) == 0 \
3547 ? ((v) & ~0x1) == 0 \
3552 : ((v) & ~0x7) == 0 \
3555 : ((v) & ~0x3f) == 0 \
3556 ? ((v) & ~0x1f) == 0 \
3559 : ((v) & ~0x7f) == 0 \
3562 : ((v) & ~0xfff) == 0 \
3563 ? ((v) & ~0x3ff) == 0 \
3564 ? ((v) & ~0x1ff) == 0 \
3567 : ((v) & ~0x7ff) == 0 \
3570 : ((v) & ~0x3fff) == 0 \
3571 ? ((v) & ~0x1fff) == 0 \
3574 : ((v) & ~0x7fff) == 0 \
3577 : ((v) & ~0xffffff) == 0 \
3578 ? ((v) & ~0xfffff) == 0 \
3579 ? ((v) & ~0x3ffff) == 0 \
3580 ? ((v) & ~0x1ffff) == 0 \
3583 : ((v) & ~0x7ffff) == 0 \
3586 : ((v) & ~0x3fffff) == 0 \
3587 ? ((v) & ~0x1fffff) == 0 \
3590 : ((v) & ~0x7fffff) == 0 \
3593 : ((v) & ~0xfffffff) == 0 \
3594 ? ((v) & ~0x3ffffff) == 0 \
3595 ? ((v) & ~0x1ffffff) == 0 \
3598 : ((v) & ~0x7ffffff) == 0 \
3601 : ((v) & ~0x3fffffff) == 0 \
3602 ? ((v) & ~0x1fffffff) == 0 \
3605 : ((v) & ~0x7fffffff) == 0 \
3610 * This routine generates the least number of instructions necessary to load
3611 * an absolute expression value into a register.
3614 load_register (int reg
, expressionS
*ep
, int dbl
)
3617 expressionS hi32
, lo32
;
3619 if (ep
->X_op
!= O_big
)
3621 assert (ep
->X_op
== O_constant
);
3623 /* Sign-extending 32-bit constants makes their handling easier. */
3624 if (! dbl
&& ! ((ep
->X_add_number
& ~((bfd_vma
) 0x7fffffff))
3625 == ~((bfd_vma
) 0x7fffffff)))
3627 if (ep
->X_add_number
& ~((bfd_vma
) 0xffffffff))
3628 as_bad (_("constant too large"));
3630 ep
->X_add_number
= (((ep
->X_add_number
& 0xffffffff) ^ 0x80000000)
3634 if (IS_SEXT_16BIT_NUM (ep
->X_add_number
))
3636 /* We can handle 16 bit signed values with an addiu to
3637 $zero. No need to ever use daddiu here, since $zero and
3638 the result are always correct in 32 bit mode. */
3639 macro_build (ep
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
3642 else if (ep
->X_add_number
>= 0 && ep
->X_add_number
< 0x10000)
3644 /* We can handle 16 bit unsigned values with an ori to
3646 macro_build (ep
, "ori", "t,r,i", reg
, 0, BFD_RELOC_LO16
);
3649 else if ((IS_SEXT_32BIT_NUM (ep
->X_add_number
)))
3651 /* 32 bit values require an lui. */
3652 macro_build (ep
, "lui", "t,u", reg
, BFD_RELOC_HI16
);
3653 if ((ep
->X_add_number
& 0xffff) != 0)
3654 macro_build (ep
, "ori", "t,r,i", reg
, reg
, BFD_RELOC_LO16
);
3659 /* The value is larger than 32 bits. */
3661 if (HAVE_32BIT_GPRS
)
3663 as_bad (_("Number (0x%lx) larger than 32 bits"),
3664 (unsigned long) ep
->X_add_number
);
3665 macro_build (ep
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
3669 if (ep
->X_op
!= O_big
)
3672 hi32
.X_add_number
= (valueT
) hi32
.X_add_number
>> 16;
3673 hi32
.X_add_number
= (valueT
) hi32
.X_add_number
>> 16;
3674 hi32
.X_add_number
&= 0xffffffff;
3676 lo32
.X_add_number
&= 0xffffffff;
3680 assert (ep
->X_add_number
> 2);
3681 if (ep
->X_add_number
== 3)
3682 generic_bignum
[3] = 0;
3683 else if (ep
->X_add_number
> 4)
3684 as_bad (_("Number larger than 64 bits"));
3685 lo32
.X_op
= O_constant
;
3686 lo32
.X_add_number
= generic_bignum
[0] + (generic_bignum
[1] << 16);
3687 hi32
.X_op
= O_constant
;
3688 hi32
.X_add_number
= generic_bignum
[2] + (generic_bignum
[3] << 16);
3691 if (hi32
.X_add_number
== 0)
3696 unsigned long hi
, lo
;
3698 if (hi32
.X_add_number
== (offsetT
) 0xffffffff)
3700 if ((lo32
.X_add_number
& 0xffff8000) == 0xffff8000)
3702 macro_build (&lo32
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
3705 if (lo32
.X_add_number
& 0x80000000)
3707 macro_build (&lo32
, "lui", "t,u", reg
, BFD_RELOC_HI16
);
3708 if (lo32
.X_add_number
& 0xffff)
3709 macro_build (&lo32
, "ori", "t,r,i", reg
, reg
, BFD_RELOC_LO16
);
3714 /* Check for 16bit shifted constant. We know that hi32 is
3715 non-zero, so start the mask on the first bit of the hi32
3720 unsigned long himask
, lomask
;
3724 himask
= 0xffff >> (32 - shift
);
3725 lomask
= (0xffff << shift
) & 0xffffffff;
3729 himask
= 0xffff << (shift
- 32);
3732 if ((hi32
.X_add_number
& ~(offsetT
) himask
) == 0
3733 && (lo32
.X_add_number
& ~(offsetT
) lomask
) == 0)
3737 tmp
.X_op
= O_constant
;
3739 tmp
.X_add_number
= ((hi32
.X_add_number
<< (32 - shift
))
3740 | (lo32
.X_add_number
>> shift
));
3742 tmp
.X_add_number
= hi32
.X_add_number
>> (shift
- 32);
3743 macro_build (&tmp
, "ori", "t,r,i", reg
, 0, BFD_RELOC_LO16
);
3744 macro_build (NULL
, (shift
>= 32) ? "dsll32" : "dsll", "d,w,<",
3745 reg
, reg
, (shift
>= 32) ? shift
- 32 : shift
);
3750 while (shift
<= (64 - 16));
3752 /* Find the bit number of the lowest one bit, and store the
3753 shifted value in hi/lo. */
3754 hi
= (unsigned long) (hi32
.X_add_number
& 0xffffffff);
3755 lo
= (unsigned long) (lo32
.X_add_number
& 0xffffffff);
3759 while ((lo
& 1) == 0)
3764 lo
|= (hi
& (((unsigned long) 1 << bit
) - 1)) << (32 - bit
);
3770 while ((hi
& 1) == 0)
3779 /* Optimize if the shifted value is a (power of 2) - 1. */
3780 if ((hi
== 0 && ((lo
+ 1) & lo
) == 0)
3781 || (lo
== 0xffffffff && ((hi
+ 1) & hi
) == 0))
3783 shift
= COUNT_TOP_ZEROES ((unsigned int) hi32
.X_add_number
);
3788 /* This instruction will set the register to be all
3790 tmp
.X_op
= O_constant
;
3791 tmp
.X_add_number
= (offsetT
) -1;
3792 macro_build (&tmp
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
3796 macro_build (NULL
, (bit
>= 32) ? "dsll32" : "dsll", "d,w,<",
3797 reg
, reg
, (bit
>= 32) ? bit
- 32 : bit
);
3799 macro_build (NULL
, (shift
>= 32) ? "dsrl32" : "dsrl", "d,w,<",
3800 reg
, reg
, (shift
>= 32) ? shift
- 32 : shift
);
3805 /* Sign extend hi32 before calling load_register, because we can
3806 generally get better code when we load a sign extended value. */
3807 if ((hi32
.X_add_number
& 0x80000000) != 0)
3808 hi32
.X_add_number
|= ~(offsetT
) 0xffffffff;
3809 load_register (reg
, &hi32
, 0);
3812 if ((lo32
.X_add_number
& 0xffff0000) == 0)
3816 macro_build (NULL
, "dsll32", "d,w,<", reg
, freg
, 0);
3824 if ((freg
== 0) && (lo32
.X_add_number
== (offsetT
) 0xffffffff))
3826 macro_build (&lo32
, "lui", "t,u", reg
, BFD_RELOC_HI16
);
3827 macro_build (NULL
, "dsrl32", "d,w,<", reg
, reg
, 0);
3833 macro_build (NULL
, "dsll", "d,w,<", reg
, freg
, 16);
3837 mid16
.X_add_number
>>= 16;
3838 macro_build (&mid16
, "ori", "t,r,i", reg
, freg
, BFD_RELOC_LO16
);
3839 macro_build (NULL
, "dsll", "d,w,<", reg
, reg
, 16);
3842 if ((lo32
.X_add_number
& 0xffff) != 0)
3843 macro_build (&lo32
, "ori", "t,r,i", reg
, freg
, BFD_RELOC_LO16
);
3847 load_delay_nop (void)
3849 if (!gpr_interlocks
)
3850 macro_build (NULL
, "nop", "");
3853 /* Load an address into a register. */
3856 load_address (int reg
, expressionS
*ep
, int *used_at
)
3858 if (ep
->X_op
!= O_constant
3859 && ep
->X_op
!= O_symbol
)
3861 as_bad (_("expression too complex"));
3862 ep
->X_op
= O_constant
;
3865 if (ep
->X_op
== O_constant
)
3867 load_register (reg
, ep
, HAVE_64BIT_ADDRESSES
);
3871 if (mips_pic
== NO_PIC
)
3873 /* If this is a reference to a GP relative symbol, we want
3874 addiu $reg,$gp,<sym> (BFD_RELOC_GPREL16)
3876 lui $reg,<sym> (BFD_RELOC_HI16_S)
3877 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
3878 If we have an addend, we always use the latter form.
3880 With 64bit address space and a usable $at we want
3881 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
3882 lui $at,<sym> (BFD_RELOC_HI16_S)
3883 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
3884 daddiu $at,<sym> (BFD_RELOC_LO16)
3888 If $at is already in use, we use a path which is suboptimal
3889 on superscalar processors.
3890 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
3891 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
3893 daddiu $reg,<sym> (BFD_RELOC_HI16_S)
3895 daddiu $reg,<sym> (BFD_RELOC_LO16)
3897 For GP relative symbols in 64bit address space we can use
3898 the same sequence as in 32bit address space. */
3899 if (HAVE_64BIT_SYMBOLS
)
3901 if ((valueT
) ep
->X_add_number
<= MAX_GPREL_OFFSET
3902 && !nopic_need_relax (ep
->X_add_symbol
, 1))
3904 relax_start (ep
->X_add_symbol
);
3905 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
,
3906 mips_gp_register
, BFD_RELOC_GPREL16
);
3910 if (*used_at
== 0 && !mips_opts
.noat
)
3912 macro_build (ep
, "lui", "t,u", reg
, BFD_RELOC_MIPS_HIGHEST
);
3913 macro_build (ep
, "lui", "t,u", AT
, BFD_RELOC_HI16_S
);
3914 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
,
3915 BFD_RELOC_MIPS_HIGHER
);
3916 macro_build (ep
, "daddiu", "t,r,j", AT
, AT
, BFD_RELOC_LO16
);
3917 macro_build (NULL
, "dsll32", "d,w,<", reg
, reg
, 0);
3918 macro_build (NULL
, "daddu", "d,v,t", reg
, reg
, AT
);
3923 macro_build (ep
, "lui", "t,u", reg
, BFD_RELOC_MIPS_HIGHEST
);
3924 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
,
3925 BFD_RELOC_MIPS_HIGHER
);
3926 macro_build (NULL
, "dsll", "d,w,<", reg
, reg
, 16);
3927 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
, BFD_RELOC_HI16_S
);
3928 macro_build (NULL
, "dsll", "d,w,<", reg
, reg
, 16);
3929 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
, BFD_RELOC_LO16
);
3932 if (mips_relax
.sequence
)
3937 if ((valueT
) ep
->X_add_number
<= MAX_GPREL_OFFSET
3938 && !nopic_need_relax (ep
->X_add_symbol
, 1))
3940 relax_start (ep
->X_add_symbol
);
3941 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
,
3942 mips_gp_register
, BFD_RELOC_GPREL16
);
3945 macro_build_lui (ep
, reg
);
3946 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j",
3947 reg
, reg
, BFD_RELOC_LO16
);
3948 if (mips_relax
.sequence
)
3952 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
3956 /* If this is a reference to an external symbol, we want
3957 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3959 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3961 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
3962 If there is a constant, it must be added in after.
3964 If we have NewABI, we want
3965 lw $reg,<sym+cst>($gp) (BFD_RELOC_MIPS_GOT_DISP)
3966 unless we're referencing a global symbol with a non-zero
3967 offset, in which case cst must be added separately. */
3970 if (ep
->X_add_number
)
3972 ex
.X_add_number
= ep
->X_add_number
;
3973 ep
->X_add_number
= 0;
3974 relax_start (ep
->X_add_symbol
);
3975 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
3976 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
3977 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
3978 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
3979 ex
.X_op
= O_constant
;
3980 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j",
3981 reg
, reg
, BFD_RELOC_LO16
);
3982 ep
->X_add_number
= ex
.X_add_number
;
3985 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
3986 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
3987 if (mips_relax
.sequence
)
3992 ex
.X_add_number
= ep
->X_add_number
;
3993 ep
->X_add_number
= 0;
3994 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
3995 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
3997 relax_start (ep
->X_add_symbol
);
3999 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
4003 if (ex
.X_add_number
!= 0)
4005 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
4006 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
4007 ex
.X_op
= O_constant
;
4008 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j",
4009 reg
, reg
, BFD_RELOC_LO16
);
4013 else if (mips_pic
== SVR4_PIC
)
4017 /* This is the large GOT case. If this is a reference to an
4018 external symbol, we want
4019 lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
4021 lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16)
4023 Otherwise, for a reference to a local symbol in old ABI, we want
4024 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4026 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
4027 If there is a constant, it must be added in after.
4029 In the NewABI, for local symbols, with or without offsets, we want:
4030 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
4031 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
4035 ex
.X_add_number
= ep
->X_add_number
;
4036 ep
->X_add_number
= 0;
4037 relax_start (ep
->X_add_symbol
);
4038 macro_build (ep
, "lui", "t,u", reg
, BFD_RELOC_MIPS_GOT_HI16
);
4039 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
4040 reg
, reg
, mips_gp_register
);
4041 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)",
4042 reg
, BFD_RELOC_MIPS_GOT_LO16
, reg
);
4043 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
4044 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
4045 else if (ex
.X_add_number
)
4047 ex
.X_op
= O_constant
;
4048 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
4052 ep
->X_add_number
= ex
.X_add_number
;
4054 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
4055 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
4056 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
4057 BFD_RELOC_MIPS_GOT_OFST
);
4062 ex
.X_add_number
= ep
->X_add_number
;
4063 ep
->X_add_number
= 0;
4064 relax_start (ep
->X_add_symbol
);
4065 macro_build (ep
, "lui", "t,u", reg
, BFD_RELOC_MIPS_GOT_HI16
);
4066 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
4067 reg
, reg
, mips_gp_register
);
4068 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)",
4069 reg
, BFD_RELOC_MIPS_GOT_LO16
, reg
);
4071 if (reg_needs_delay (mips_gp_register
))
4073 /* We need a nop before loading from $gp. This special
4074 check is required because the lui which starts the main
4075 instruction stream does not refer to $gp, and so will not
4076 insert the nop which may be required. */
4077 macro_build (NULL
, "nop", "");
4079 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
4080 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
4082 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
4086 if (ex
.X_add_number
!= 0)
4088 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
4089 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
4090 ex
.X_op
= O_constant
;
4091 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
4099 if (mips_opts
.noat
&& *used_at
== 1)
4100 as_bad (_("Macro used $at after \".set noat\""));
4103 /* Move the contents of register SOURCE into register DEST. */
4106 move_register (int dest
, int source
)
4108 macro_build (NULL
, HAVE_32BIT_GPRS
? "addu" : "daddu", "d,v,t",
4112 /* Emit an SVR4 PIC sequence to load address LOCAL into DEST, where
4113 LOCAL is the sum of a symbol and a 16-bit or 32-bit displacement.
4114 The two alternatives are:
4116 Global symbol Local sybmol
4117 ------------- ------------
4118 lw DEST,%got(SYMBOL) lw DEST,%got(SYMBOL + OFFSET)
4120 addiu DEST,DEST,OFFSET addiu DEST,DEST,%lo(SYMBOL + OFFSET)
4122 load_got_offset emits the first instruction and add_got_offset
4123 emits the second for a 16-bit offset or add_got_offset_hilo emits
4124 a sequence to add a 32-bit offset using a scratch register. */
4127 load_got_offset (int dest
, expressionS
*local
)
4132 global
.X_add_number
= 0;
4134 relax_start (local
->X_add_symbol
);
4135 macro_build (&global
, ADDRESS_LOAD_INSN
, "t,o(b)", dest
,
4136 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
4138 macro_build (local
, ADDRESS_LOAD_INSN
, "t,o(b)", dest
,
4139 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
4144 add_got_offset (int dest
, expressionS
*local
)
4148 global
.X_op
= O_constant
;
4149 global
.X_op_symbol
= NULL
;
4150 global
.X_add_symbol
= NULL
;
4151 global
.X_add_number
= local
->X_add_number
;
4153 relax_start (local
->X_add_symbol
);
4154 macro_build (&global
, ADDRESS_ADDI_INSN
, "t,r,j",
4155 dest
, dest
, BFD_RELOC_LO16
);
4157 macro_build (local
, ADDRESS_ADDI_INSN
, "t,r,j", dest
, dest
, BFD_RELOC_LO16
);
4162 add_got_offset_hilo (int dest
, expressionS
*local
, int tmp
)
4165 int hold_mips_optimize
;
4167 global
.X_op
= O_constant
;
4168 global
.X_op_symbol
= NULL
;
4169 global
.X_add_symbol
= NULL
;
4170 global
.X_add_number
= local
->X_add_number
;
4172 relax_start (local
->X_add_symbol
);
4173 load_register (tmp
, &global
, HAVE_64BIT_ADDRESSES
);
4175 /* Set mips_optimize around the lui instruction to avoid
4176 inserting an unnecessary nop after the lw. */
4177 hold_mips_optimize
= mips_optimize
;
4179 macro_build_lui (&global
, tmp
);
4180 mips_optimize
= hold_mips_optimize
;
4181 macro_build (local
, ADDRESS_ADDI_INSN
, "t,r,j", tmp
, tmp
, BFD_RELOC_LO16
);
4184 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", dest
, dest
, tmp
);
4189 * This routine implements the seemingly endless macro or synthesized
4190 * instructions and addressing modes in the mips assembly language. Many
4191 * of these macros are simple and are similar to each other. These could
4192 * probably be handled by some kind of table or grammar approach instead of
4193 * this verbose method. Others are not simple macros but are more like
4194 * optimizing code generation.
4195 * One interesting optimization is when several store macros appear
4196 * consecutively that would load AT with the upper half of the same address.
4197 * The ensuing load upper instructions are ommited. This implies some kind
4198 * of global optimization. We currently only optimize within a single macro.
4199 * For many of the load and store macros if the address is specified as a
4200 * constant expression in the first 64k of memory (ie ld $2,0x4000c) we
4201 * first load register 'at' with zero and use it as the base register. The
4202 * mips assembler simply uses register $zero. Just one tiny optimization
4206 macro (struct mips_cl_insn
*ip
)
4208 register int treg
, sreg
, dreg
, breg
;
4224 bfd_reloc_code_real_type r
;
4225 int hold_mips_optimize
;
4227 assert (! mips_opts
.mips16
);
4229 treg
= (ip
->insn_opcode
>> 16) & 0x1f;
4230 dreg
= (ip
->insn_opcode
>> 11) & 0x1f;
4231 sreg
= breg
= (ip
->insn_opcode
>> 21) & 0x1f;
4232 mask
= ip
->insn_mo
->mask
;
4234 expr1
.X_op
= O_constant
;
4235 expr1
.X_op_symbol
= NULL
;
4236 expr1
.X_add_symbol
= NULL
;
4237 expr1
.X_add_number
= 1;
4249 mips_emit_delays (TRUE
);
4250 ++mips_opts
.noreorder
;
4251 mips_any_noreorder
= 1;
4253 expr1
.X_add_number
= 8;
4254 macro_build (&expr1
, "bgez", "s,p", sreg
);
4256 macro_build (NULL
, "nop", "", 0);
4258 move_register (dreg
, sreg
);
4259 macro_build (NULL
, dbl
? "dsub" : "sub", "d,v,t", dreg
, 0, sreg
);
4261 --mips_opts
.noreorder
;
4282 if (imm_expr
.X_op
== O_constant
4283 && imm_expr
.X_add_number
>= -0x8000
4284 && imm_expr
.X_add_number
< 0x8000)
4286 macro_build (&imm_expr
, s
, "t,r,j", treg
, sreg
, BFD_RELOC_LO16
);
4290 load_register (AT
, &imm_expr
, dbl
);
4291 macro_build (NULL
, s2
, "d,v,t", treg
, sreg
, AT
);
4310 if (imm_expr
.X_op
== O_constant
4311 && imm_expr
.X_add_number
>= 0
4312 && imm_expr
.X_add_number
< 0x10000)
4314 if (mask
!= M_NOR_I
)
4315 macro_build (&imm_expr
, s
, "t,r,i", treg
, sreg
, BFD_RELOC_LO16
);
4318 macro_build (&imm_expr
, "ori", "t,r,i",
4319 treg
, sreg
, BFD_RELOC_LO16
);
4320 macro_build (NULL
, "nor", "d,v,t", treg
, treg
, 0);
4326 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
4327 macro_build (NULL
, s2
, "d,v,t", treg
, sreg
, AT
);
4344 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
4346 macro_build (&offset_expr
, s
, "s,t,p", sreg
, 0);
4350 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
4351 macro_build (&offset_expr
, s
, "s,t,p", sreg
, AT
);
4359 macro_build (&offset_expr
, likely
? "bgezl" : "bgez", "s,p", sreg
);
4364 macro_build (&offset_expr
, likely
? "blezl" : "blez", "s,p", treg
);
4368 macro_build (NULL
, "slt", "d,v,t", AT
, sreg
, treg
);
4369 macro_build (&offset_expr
, likely
? "beql" : "beq", "s,t,p", AT
, 0);
4375 /* check for > max integer */
4376 maxnum
= 0x7fffffff;
4377 if (HAVE_64BIT_GPRS
&& sizeof (maxnum
) > 4)
4384 if (imm_expr
.X_op
== O_constant
4385 && imm_expr
.X_add_number
>= maxnum
4386 && (HAVE_32BIT_GPRS
|| sizeof (maxnum
) > 4))
4389 /* result is always false */
4391 macro_build (NULL
, "nop", "", 0);
4393 macro_build (&offset_expr
, "bnel", "s,t,p", 0, 0);
4396 if (imm_expr
.X_op
!= O_constant
)
4397 as_bad (_("Unsupported large constant"));
4398 ++imm_expr
.X_add_number
;
4402 if (mask
== M_BGEL_I
)
4404 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
4406 macro_build (&offset_expr
, likely
? "bgezl" : "bgez", "s,p", sreg
);
4409 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
4411 macro_build (&offset_expr
, likely
? "bgtzl" : "bgtz", "s,p", sreg
);
4414 maxnum
= 0x7fffffff;
4415 if (HAVE_64BIT_GPRS
&& sizeof (maxnum
) > 4)
4422 maxnum
= - maxnum
- 1;
4423 if (imm_expr
.X_op
== O_constant
4424 && imm_expr
.X_add_number
<= maxnum
4425 && (HAVE_32BIT_GPRS
|| sizeof (maxnum
) > 4))
4428 /* result is always true */
4429 as_warn (_("Branch %s is always true"), ip
->insn_mo
->name
);
4430 macro_build (&offset_expr
, "b", "p");
4435 macro_build (&offset_expr
, likely
? "beql" : "beq", "s,t,p", AT
, 0);
4445 macro_build (&offset_expr
, likely
? "beql" : "beq",
4450 macro_build (NULL
, "sltu", "d,v,t", AT
, sreg
, treg
);
4451 macro_build (&offset_expr
, likely
? "beql" : "beq", "s,t,p", AT
, 0);
4459 && imm_expr
.X_op
== O_constant
4460 && imm_expr
.X_add_number
== (offsetT
) 0xffffffff))
4462 if (imm_expr
.X_op
!= O_constant
)
4463 as_bad (_("Unsupported large constant"));
4464 ++imm_expr
.X_add_number
;
4468 if (mask
== M_BGEUL_I
)
4470 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
4472 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
4474 macro_build (&offset_expr
, likely
? "bnel" : "bne",
4480 macro_build (&offset_expr
, likely
? "beql" : "beq", "s,t,p", AT
, 0);
4488 macro_build (&offset_expr
, likely
? "bgtzl" : "bgtz", "s,p", sreg
);
4493 macro_build (&offset_expr
, likely
? "bltzl" : "bltz", "s,p", treg
);
4497 macro_build (NULL
, "slt", "d,v,t", AT
, treg
, sreg
);
4498 macro_build (&offset_expr
, likely
? "bnel" : "bne", "s,t,p", AT
, 0);
4506 macro_build (&offset_expr
, likely
? "bnel" : "bne",
4513 macro_build (NULL
, "sltu", "d,v,t", AT
, treg
, sreg
);
4514 macro_build (&offset_expr
, likely
? "bnel" : "bne", "s,t,p", AT
, 0);
4522 macro_build (&offset_expr
, likely
? "blezl" : "blez", "s,p", sreg
);
4527 macro_build (&offset_expr
, likely
? "bgezl" : "bgez", "s,p", treg
);
4531 macro_build (NULL
, "slt", "d,v,t", AT
, treg
, sreg
);
4532 macro_build (&offset_expr
, likely
? "beql" : "beq", "s,t,p", AT
, 0);
4538 maxnum
= 0x7fffffff;
4539 if (HAVE_64BIT_GPRS
&& sizeof (maxnum
) > 4)
4546 if (imm_expr
.X_op
== O_constant
4547 && imm_expr
.X_add_number
>= maxnum
4548 && (HAVE_32BIT_GPRS
|| sizeof (maxnum
) > 4))
4550 if (imm_expr
.X_op
!= O_constant
)
4551 as_bad (_("Unsupported large constant"));
4552 ++imm_expr
.X_add_number
;
4556 if (mask
== M_BLTL_I
)
4558 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
4560 macro_build (&offset_expr
, likely
? "bltzl" : "bltz", "s,p", sreg
);
4563 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
4565 macro_build (&offset_expr
, likely
? "blezl" : "blez", "s,p", sreg
);
4570 macro_build (&offset_expr
, likely
? "bnel" : "bne", "s,t,p", AT
, 0);
4578 macro_build (&offset_expr
, likely
? "beql" : "beq",
4585 macro_build (NULL
, "sltu", "d,v,t", AT
, treg
, sreg
);
4586 macro_build (&offset_expr
, likely
? "beql" : "beq", "s,t,p", AT
, 0);
4594 && imm_expr
.X_op
== O_constant
4595 && imm_expr
.X_add_number
== (offsetT
) 0xffffffff))
4597 if (imm_expr
.X_op
!= O_constant
)
4598 as_bad (_("Unsupported large constant"));
4599 ++imm_expr
.X_add_number
;
4603 if (mask
== M_BLTUL_I
)
4605 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
4607 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
4609 macro_build (&offset_expr
, likely
? "beql" : "beq",
4615 macro_build (&offset_expr
, likely
? "bnel" : "bne", "s,t,p", AT
, 0);
4623 macro_build (&offset_expr
, likely
? "bltzl" : "bltz", "s,p", sreg
);
4628 macro_build (&offset_expr
, likely
? "bgtzl" : "bgtz", "s,p", treg
);
4632 macro_build (NULL
, "slt", "d,v,t", AT
, sreg
, treg
);
4633 macro_build (&offset_expr
, likely
? "bnel" : "bne", "s,t,p", AT
, 0);
4643 macro_build (&offset_expr
, likely
? "bnel" : "bne",
4648 macro_build (NULL
, "sltu", "d,v,t", AT
, sreg
, treg
);
4649 macro_build (&offset_expr
, likely
? "bnel" : "bne", "s,t,p", AT
, 0);
4657 if (imm_expr
.X_op
!= O_constant
|| imm2_expr
.X_op
!= O_constant
)
4659 as_bad (_("Unsupported large constant"));
4664 pos
= (unsigned long) imm_expr
.X_add_number
;
4665 size
= (unsigned long) imm2_expr
.X_add_number
;
4670 as_bad (_("Improper position (%lu)"), pos
);
4673 if (size
== 0 || size
> 64
4674 || (pos
+ size
- 1) > 63)
4676 as_bad (_("Improper extract size (%lu, position %lu)"),
4681 if (size
<= 32 && pos
< 32)
4686 else if (size
<= 32)
4696 macro_build ((expressionS
*) NULL
, s
, fmt
, treg
, sreg
, pos
, size
- 1);
4705 if (imm_expr
.X_op
!= O_constant
|| imm2_expr
.X_op
!= O_constant
)
4707 as_bad (_("Unsupported large constant"));
4712 pos
= (unsigned long) imm_expr
.X_add_number
;
4713 size
= (unsigned long) imm2_expr
.X_add_number
;
4718 as_bad (_("Improper position (%lu)"), pos
);
4721 if (size
== 0 || size
> 64
4722 || (pos
+ size
- 1) > 63)
4724 as_bad (_("Improper insert size (%lu, position %lu)"),
4729 if (pos
< 32 && (pos
+ size
- 1) < 32)
4744 macro_build ((expressionS
*) NULL
, s
, fmt
, treg
, sreg
, pos
,
4761 as_warn (_("Divide by zero."));
4763 macro_build (NULL
, "teq", "s,t,q", 0, 0, 7);
4765 macro_build (NULL
, "break", "c", 7);
4769 mips_emit_delays (TRUE
);
4770 ++mips_opts
.noreorder
;
4771 mips_any_noreorder
= 1;
4774 macro_build (NULL
, "teq", "s,t,q", treg
, 0, 7);
4775 macro_build (NULL
, dbl
? "ddiv" : "div", "z,s,t", sreg
, treg
);
4779 expr1
.X_add_number
= 8;
4780 macro_build (&expr1
, "bne", "s,t,p", treg
, 0);
4781 macro_build (NULL
, dbl
? "ddiv" : "div", "z,s,t", sreg
, treg
);
4782 macro_build (NULL
, "break", "c", 7);
4784 expr1
.X_add_number
= -1;
4786 load_register (AT
, &expr1
, dbl
);
4787 expr1
.X_add_number
= mips_trap
? (dbl
? 12 : 8) : (dbl
? 20 : 16);
4788 macro_build (&expr1
, "bne", "s,t,p", treg
, AT
);
4791 expr1
.X_add_number
= 1;
4792 load_register (AT
, &expr1
, dbl
);
4793 macro_build (NULL
, "dsll32", "d,w,<", AT
, AT
, 31);
4797 expr1
.X_add_number
= 0x80000000;
4798 macro_build (&expr1
, "lui", "t,u", AT
, BFD_RELOC_HI16
);
4802 macro_build (NULL
, "teq", "s,t,q", sreg
, AT
, 6);
4803 /* We want to close the noreorder block as soon as possible, so
4804 that later insns are available for delay slot filling. */
4805 --mips_opts
.noreorder
;
4809 expr1
.X_add_number
= 8;
4810 macro_build (&expr1
, "bne", "s,t,p", sreg
, AT
);
4811 macro_build (NULL
, "nop", "", 0);
4813 /* We want to close the noreorder block as soon as possible, so
4814 that later insns are available for delay slot filling. */
4815 --mips_opts
.noreorder
;
4817 macro_build (NULL
, "break", "c", 6);
4819 macro_build (NULL
, s
, "d", dreg
);
4858 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
4860 as_warn (_("Divide by zero."));
4862 macro_build (NULL
, "teq", "s,t,q", 0, 0, 7);
4864 macro_build (NULL
, "break", "c", 7);
4867 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
4869 if (strcmp (s2
, "mflo") == 0)
4870 move_register (dreg
, sreg
);
4872 move_register (dreg
, 0);
4875 if (imm_expr
.X_op
== O_constant
4876 && imm_expr
.X_add_number
== -1
4877 && s
[strlen (s
) - 1] != 'u')
4879 if (strcmp (s2
, "mflo") == 0)
4881 macro_build (NULL
, dbl
? "dneg" : "neg", "d,w", dreg
, sreg
);
4884 move_register (dreg
, 0);
4889 load_register (AT
, &imm_expr
, dbl
);
4890 macro_build (NULL
, s
, "z,s,t", sreg
, AT
);
4891 macro_build (NULL
, s2
, "d", dreg
);
4910 mips_emit_delays (TRUE
);
4911 ++mips_opts
.noreorder
;
4912 mips_any_noreorder
= 1;
4915 macro_build (NULL
, "teq", "s,t,q", treg
, 0, 7);
4916 macro_build (NULL
, s
, "z,s,t", sreg
, treg
);
4917 /* We want to close the noreorder block as soon as possible, so
4918 that later insns are available for delay slot filling. */
4919 --mips_opts
.noreorder
;
4923 expr1
.X_add_number
= 8;
4924 macro_build (&expr1
, "bne", "s,t,p", treg
, 0);
4925 macro_build (NULL
, s
, "z,s,t", sreg
, treg
);
4927 /* We want to close the noreorder block as soon as possible, so
4928 that later insns are available for delay slot filling. */
4929 --mips_opts
.noreorder
;
4930 macro_build (NULL
, "break", "c", 7);
4932 macro_build (NULL
, s2
, "d", dreg
);
4944 /* Load the address of a symbol into a register. If breg is not
4945 zero, we then add a base register to it. */
4947 if (dbl
&& HAVE_32BIT_GPRS
)
4948 as_warn (_("dla used to load 32-bit register"));
4950 if (! dbl
&& HAVE_64BIT_OBJECTS
)
4951 as_warn (_("la used to load 64-bit address"));
4953 if (offset_expr
.X_op
== O_constant
4954 && offset_expr
.X_add_number
>= -0x8000
4955 && offset_expr
.X_add_number
< 0x8000)
4957 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
,
4958 "t,r,j", treg
, sreg
, BFD_RELOC_LO16
);
4962 if (!mips_opts
.noat
&& (treg
== breg
))
4972 if (offset_expr
.X_op
!= O_symbol
4973 && offset_expr
.X_op
!= O_constant
)
4975 as_bad (_("expression too complex"));
4976 offset_expr
.X_op
= O_constant
;
4979 if (offset_expr
.X_op
== O_constant
)
4980 load_register (tempreg
, &offset_expr
, HAVE_64BIT_ADDRESSES
);
4981 else if (mips_pic
== NO_PIC
)
4983 /* If this is a reference to a GP relative symbol, we want
4984 addiu $tempreg,$gp,<sym> (BFD_RELOC_GPREL16)
4986 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
4987 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
4988 If we have a constant, we need two instructions anyhow,
4989 so we may as well always use the latter form.
4991 With 64bit address space and a usable $at we want
4992 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
4993 lui $at,<sym> (BFD_RELOC_HI16_S)
4994 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
4995 daddiu $at,<sym> (BFD_RELOC_LO16)
4997 daddu $tempreg,$tempreg,$at
4999 If $at is already in use, we use a path which is suboptimal
5000 on superscalar processors.
5001 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5002 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
5004 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
5006 daddiu $tempreg,<sym> (BFD_RELOC_LO16)
5008 For GP relative symbols in 64bit address space we can use
5009 the same sequence as in 32bit address space. */
5010 if (HAVE_64BIT_SYMBOLS
)
5012 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
5013 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
5015 relax_start (offset_expr
.X_add_symbol
);
5016 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
5017 tempreg
, mips_gp_register
, BFD_RELOC_GPREL16
);
5021 if (used_at
== 0 && !mips_opts
.noat
)
5023 macro_build (&offset_expr
, "lui", "t,u",
5024 tempreg
, BFD_RELOC_MIPS_HIGHEST
);
5025 macro_build (&offset_expr
, "lui", "t,u",
5026 AT
, BFD_RELOC_HI16_S
);
5027 macro_build (&offset_expr
, "daddiu", "t,r,j",
5028 tempreg
, tempreg
, BFD_RELOC_MIPS_HIGHER
);
5029 macro_build (&offset_expr
, "daddiu", "t,r,j",
5030 AT
, AT
, BFD_RELOC_LO16
);
5031 macro_build (NULL
, "dsll32", "d,w,<", tempreg
, tempreg
, 0);
5032 macro_build (NULL
, "daddu", "d,v,t", tempreg
, tempreg
, AT
);
5037 macro_build (&offset_expr
, "lui", "t,u",
5038 tempreg
, BFD_RELOC_MIPS_HIGHEST
);
5039 macro_build (&offset_expr
, "daddiu", "t,r,j",
5040 tempreg
, tempreg
, BFD_RELOC_MIPS_HIGHER
);
5041 macro_build (NULL
, "dsll", "d,w,<", tempreg
, tempreg
, 16);
5042 macro_build (&offset_expr
, "daddiu", "t,r,j",
5043 tempreg
, tempreg
, BFD_RELOC_HI16_S
);
5044 macro_build (NULL
, "dsll", "d,w,<", tempreg
, tempreg
, 16);
5045 macro_build (&offset_expr
, "daddiu", "t,r,j",
5046 tempreg
, tempreg
, BFD_RELOC_LO16
);
5049 if (mips_relax
.sequence
)
5054 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
5055 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
5057 relax_start (offset_expr
.X_add_symbol
);
5058 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
5059 tempreg
, mips_gp_register
, BFD_RELOC_GPREL16
);
5062 if (!IS_SEXT_32BIT_NUM (offset_expr
.X_add_number
))
5063 as_bad (_("offset too large"));
5064 macro_build_lui (&offset_expr
, tempreg
);
5065 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
5066 tempreg
, tempreg
, BFD_RELOC_LO16
);
5067 if (mips_relax
.sequence
)
5071 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
&& ! HAVE_NEWABI
)
5073 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT16
;
5075 /* If this is a reference to an external symbol, and there
5076 is no constant, we want
5077 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5078 or for lca or if tempreg is PIC_CALL_REG
5079 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
5080 For a local symbol, we want
5081 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5083 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
5085 If we have a small constant, and this is a reference to
5086 an external symbol, we want
5087 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5089 addiu $tempreg,$tempreg,<constant>
5090 For a local symbol, we want the same instruction
5091 sequence, but we output a BFD_RELOC_LO16 reloc on the
5094 If we have a large constant, and this is a reference to
5095 an external symbol, we want
5096 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5097 lui $at,<hiconstant>
5098 addiu $at,$at,<loconstant>
5099 addu $tempreg,$tempreg,$at
5100 For a local symbol, we want the same instruction
5101 sequence, but we output a BFD_RELOC_LO16 reloc on the
5105 if (offset_expr
.X_add_number
== 0)
5107 if (breg
== 0 && (call
|| tempreg
== PIC_CALL_REG
))
5108 lw_reloc_type
= (int) BFD_RELOC_MIPS_CALL16
;
5110 relax_start (offset_expr
.X_add_symbol
);
5111 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
5112 lw_reloc_type
, mips_gp_register
);
5115 /* We're going to put in an addu instruction using
5116 tempreg, so we may as well insert the nop right
5121 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
5122 tempreg
, BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
5124 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
5125 tempreg
, tempreg
, BFD_RELOC_LO16
);
5127 /* FIXME: If breg == 0, and the next instruction uses
5128 $tempreg, then if this variant case is used an extra
5129 nop will be generated. */
5131 else if (offset_expr
.X_add_number
>= -0x8000
5132 && offset_expr
.X_add_number
< 0x8000)
5134 load_got_offset (tempreg
, &offset_expr
);
5136 add_got_offset (tempreg
, &offset_expr
);
5140 expr1
.X_add_number
= offset_expr
.X_add_number
;
5141 offset_expr
.X_add_number
=
5142 ((offset_expr
.X_add_number
+ 0x8000) & 0xffff) - 0x8000;
5143 load_got_offset (tempreg
, &offset_expr
);
5144 offset_expr
.X_add_number
= expr1
.X_add_number
;
5145 /* If we are going to add in a base register, and the
5146 target register and the base register are the same,
5147 then we are using AT as a temporary register. Since
5148 we want to load the constant into AT, we add our
5149 current AT (from the global offset table) and the
5150 register into the register now, and pretend we were
5151 not using a base register. */
5155 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5160 add_got_offset_hilo (tempreg
, &offset_expr
, AT
);
5164 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
&& HAVE_NEWABI
)
5166 int add_breg_early
= 0;
5168 /* If this is a reference to an external, and there is no
5169 constant, or local symbol (*), with or without a
5171 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
5172 or for lca or if tempreg is PIC_CALL_REG
5173 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
5175 If we have a small constant, and this is a reference to
5176 an external symbol, we want
5177 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
5178 addiu $tempreg,$tempreg,<constant>
5180 If we have a large constant, and this is a reference to
5181 an external symbol, we want
5182 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
5183 lui $at,<hiconstant>
5184 addiu $at,$at,<loconstant>
5185 addu $tempreg,$tempreg,$at
5187 (*) Other assemblers seem to prefer GOT_PAGE/GOT_OFST for
5188 local symbols, even though it introduces an additional
5191 if (offset_expr
.X_add_number
)
5193 expr1
.X_add_number
= offset_expr
.X_add_number
;
5194 offset_expr
.X_add_number
= 0;
5196 relax_start (offset_expr
.X_add_symbol
);
5197 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
5198 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
5200 if (expr1
.X_add_number
>= -0x8000
5201 && expr1
.X_add_number
< 0x8000)
5203 macro_build (&expr1
, ADDRESS_ADDI_INSN
, "t,r,j",
5204 tempreg
, tempreg
, BFD_RELOC_LO16
);
5206 else if (IS_SEXT_32BIT_NUM (expr1
.X_add_number
+ 0x8000))
5210 /* If we are going to add in a base register, and the
5211 target register and the base register are the same,
5212 then we are using AT as a temporary register. Since
5213 we want to load the constant into AT, we add our
5214 current AT (from the global offset table) and the
5215 register into the register now, and pretend we were
5216 not using a base register. */
5221 assert (tempreg
== AT
);
5222 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5228 load_register (AT
, &expr1
, HAVE_64BIT_ADDRESSES
);
5229 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5235 as_bad (_("PIC code offset overflow (max 32 signed bits)"));
5238 offset_expr
.X_add_number
= expr1
.X_add_number
;
5240 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
5241 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
5244 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5245 treg
, tempreg
, breg
);
5251 else if (breg
== 0 && (call
|| tempreg
== PIC_CALL_REG
))
5253 relax_start (offset_expr
.X_add_symbol
);
5254 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
5255 BFD_RELOC_MIPS_CALL16
, mips_gp_register
);
5257 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
5258 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
5263 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
5264 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
5267 else if (mips_pic
== SVR4_PIC
&& ! HAVE_NEWABI
)
5270 int lui_reloc_type
= (int) BFD_RELOC_MIPS_GOT_HI16
;
5271 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT_LO16
;
5272 int local_reloc_type
= (int) BFD_RELOC_MIPS_GOT16
;
5274 /* This is the large GOT case. If this is a reference to an
5275 external symbol, and there is no constant, we want
5276 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5277 addu $tempreg,$tempreg,$gp
5278 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5279 or for lca or if tempreg is PIC_CALL_REG
5280 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
5281 addu $tempreg,$tempreg,$gp
5282 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
5283 For a local symbol, we want
5284 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5286 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
5288 If we have a small constant, and this is a reference to
5289 an external symbol, we want
5290 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5291 addu $tempreg,$tempreg,$gp
5292 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5294 addiu $tempreg,$tempreg,<constant>
5295 For a local symbol, we want
5296 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5298 addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16)
5300 If we have a large constant, and this is a reference to
5301 an external symbol, we want
5302 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5303 addu $tempreg,$tempreg,$gp
5304 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5305 lui $at,<hiconstant>
5306 addiu $at,$at,<loconstant>
5307 addu $tempreg,$tempreg,$at
5308 For a local symbol, we want
5309 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5310 lui $at,<hiconstant>
5311 addiu $at,$at,<loconstant> (BFD_RELOC_LO16)
5312 addu $tempreg,$tempreg,$at
5315 expr1
.X_add_number
= offset_expr
.X_add_number
;
5316 offset_expr
.X_add_number
= 0;
5317 relax_start (offset_expr
.X_add_symbol
);
5318 gpdelay
= reg_needs_delay (mips_gp_register
);
5319 if (expr1
.X_add_number
== 0 && breg
== 0
5320 && (call
|| tempreg
== PIC_CALL_REG
))
5322 lui_reloc_type
= (int) BFD_RELOC_MIPS_CALL_HI16
;
5323 lw_reloc_type
= (int) BFD_RELOC_MIPS_CALL_LO16
;
5325 macro_build (&offset_expr
, "lui", "t,u", tempreg
, lui_reloc_type
);
5326 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5327 tempreg
, tempreg
, mips_gp_register
);
5328 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
5329 tempreg
, lw_reloc_type
, tempreg
);
5330 if (expr1
.X_add_number
== 0)
5334 /* We're going to put in an addu instruction using
5335 tempreg, so we may as well insert the nop right
5340 else if (expr1
.X_add_number
>= -0x8000
5341 && expr1
.X_add_number
< 0x8000)
5344 macro_build (&expr1
, ADDRESS_ADDI_INSN
, "t,r,j",
5345 tempreg
, tempreg
, BFD_RELOC_LO16
);
5351 /* If we are going to add in a base register, and the
5352 target register and the base register are the same,
5353 then we are using AT as a temporary register. Since
5354 we want to load the constant into AT, we add our
5355 current AT (from the global offset table) and the
5356 register into the register now, and pretend we were
5357 not using a base register. */
5362 assert (tempreg
== AT
);
5364 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5369 load_register (AT
, &expr1
, HAVE_64BIT_ADDRESSES
);
5370 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", dreg
, dreg
, AT
);
5374 offset_expr
.X_add_number
=
5375 ((expr1
.X_add_number
+ 0x8000) & 0xffff) - 0x8000;
5380 /* This is needed because this instruction uses $gp, but
5381 the first instruction on the main stream does not. */
5382 macro_build (NULL
, "nop", "");
5385 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
5386 local_reloc_type
, mips_gp_register
);
5387 if (expr1
.X_add_number
>= -0x8000
5388 && expr1
.X_add_number
< 0x8000)
5391 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
5392 tempreg
, tempreg
, BFD_RELOC_LO16
);
5393 /* FIXME: If add_number is 0, and there was no base
5394 register, the external symbol case ended with a load,
5395 so if the symbol turns out to not be external, and
5396 the next instruction uses tempreg, an unnecessary nop
5397 will be inserted. */
5403 /* We must add in the base register now, as in the
5404 external symbol case. */
5405 assert (tempreg
== AT
);
5407 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5410 /* We set breg to 0 because we have arranged to add
5411 it in in both cases. */
5415 macro_build_lui (&expr1
, AT
);
5416 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
5417 AT
, AT
, BFD_RELOC_LO16
);
5418 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5419 tempreg
, tempreg
, AT
);
5424 else if (mips_pic
== SVR4_PIC
&& HAVE_NEWABI
)
5426 int lui_reloc_type
= (int) BFD_RELOC_MIPS_GOT_HI16
;
5427 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT_LO16
;
5428 int add_breg_early
= 0;
5430 /* This is the large GOT case. If this is a reference to an
5431 external symbol, and there is no constant, we want
5432 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5433 add $tempreg,$tempreg,$gp
5434 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5435 or for lca or if tempreg is PIC_CALL_REG
5436 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
5437 add $tempreg,$tempreg,$gp
5438 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
5440 If we have a small constant, and this is a reference to
5441 an external symbol, we want
5442 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5443 add $tempreg,$tempreg,$gp
5444 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5445 addi $tempreg,$tempreg,<constant>
5447 If we have a large constant, and this is a reference to
5448 an external symbol, we want
5449 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5450 addu $tempreg,$tempreg,$gp
5451 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5452 lui $at,<hiconstant>
5453 addi $at,$at,<loconstant>
5454 add $tempreg,$tempreg,$at
5456 If we have NewABI, and we know it's a local symbol, we want
5457 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
5458 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
5459 otherwise we have to resort to GOT_HI16/GOT_LO16. */
5461 relax_start (offset_expr
.X_add_symbol
);
5463 expr1
.X_add_number
= offset_expr
.X_add_number
;
5464 offset_expr
.X_add_number
= 0;
5466 if (expr1
.X_add_number
== 0 && breg
== 0
5467 && (call
|| tempreg
== PIC_CALL_REG
))
5469 lui_reloc_type
= (int) BFD_RELOC_MIPS_CALL_HI16
;
5470 lw_reloc_type
= (int) BFD_RELOC_MIPS_CALL_LO16
;
5472 macro_build (&offset_expr
, "lui", "t,u", tempreg
, lui_reloc_type
);
5473 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5474 tempreg
, tempreg
, mips_gp_register
);
5475 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
5476 tempreg
, lw_reloc_type
, tempreg
);
5478 if (expr1
.X_add_number
== 0)
5480 else if (expr1
.X_add_number
>= -0x8000
5481 && expr1
.X_add_number
< 0x8000)
5483 macro_build (&expr1
, ADDRESS_ADDI_INSN
, "t,r,j",
5484 tempreg
, tempreg
, BFD_RELOC_LO16
);
5486 else if (IS_SEXT_32BIT_NUM (expr1
.X_add_number
+ 0x8000))
5490 /* If we are going to add in a base register, and the
5491 target register and the base register are the same,
5492 then we are using AT as a temporary register. Since
5493 we want to load the constant into AT, we add our
5494 current AT (from the global offset table) and the
5495 register into the register now, and pretend we were
5496 not using a base register. */
5501 assert (tempreg
== AT
);
5502 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5508 load_register (AT
, &expr1
, HAVE_64BIT_ADDRESSES
);
5509 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", dreg
, dreg
, AT
);
5514 as_bad (_("PIC code offset overflow (max 32 signed bits)"));
5517 offset_expr
.X_add_number
= expr1
.X_add_number
;
5518 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
5519 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
5520 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j", tempreg
,
5521 tempreg
, BFD_RELOC_MIPS_GOT_OFST
);
5524 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5525 treg
, tempreg
, breg
);
5535 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", treg
, tempreg
, breg
);
5539 /* The j instruction may not be used in PIC code, since it
5540 requires an absolute address. We convert it to a b
5542 if (mips_pic
== NO_PIC
)
5543 macro_build (&offset_expr
, "j", "a");
5545 macro_build (&offset_expr
, "b", "p");
5548 /* The jal instructions must be handled as macros because when
5549 generating PIC code they expand to multi-instruction
5550 sequences. Normally they are simple instructions. */
5555 if (mips_pic
== NO_PIC
)
5556 macro_build (NULL
, "jalr", "d,s", dreg
, sreg
);
5557 else if (mips_pic
== SVR4_PIC
)
5559 if (sreg
!= PIC_CALL_REG
)
5560 as_warn (_("MIPS PIC call to register other than $25"));
5562 macro_build (NULL
, "jalr", "d,s", dreg
, sreg
);
5565 if (mips_cprestore_offset
< 0)
5566 as_warn (_("No .cprestore pseudo-op used in PIC code"));
5569 if (! mips_frame_reg_valid
)
5571 as_warn (_("No .frame pseudo-op used in PIC code"));
5572 /* Quiet this warning. */
5573 mips_frame_reg_valid
= 1;
5575 if (! mips_cprestore_valid
)
5577 as_warn (_("No .cprestore pseudo-op used in PIC code"));
5578 /* Quiet this warning. */
5579 mips_cprestore_valid
= 1;
5581 expr1
.X_add_number
= mips_cprestore_offset
;
5582 macro_build_ldst_constoffset (&expr1
, ADDRESS_LOAD_INSN
,
5585 HAVE_64BIT_ADDRESSES
);
5595 if (mips_pic
== NO_PIC
)
5596 macro_build (&offset_expr
, "jal", "a");
5597 else if (mips_pic
== SVR4_PIC
)
5599 /* If this is a reference to an external symbol, and we are
5600 using a small GOT, we want
5601 lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
5605 lw $gp,cprestore($sp)
5606 The cprestore value is set using the .cprestore
5607 pseudo-op. If we are using a big GOT, we want
5608 lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16)
5610 lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16)
5614 lw $gp,cprestore($sp)
5615 If the symbol is not external, we want
5616 lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5618 addiu $25,$25,<sym> (BFD_RELOC_LO16)
5621 lw $gp,cprestore($sp)
5623 For NewABI, we use the same CALL16 or CALL_HI16/CALL_LO16
5624 sequences above, minus nops, unless the symbol is local,
5625 which enables us to use GOT_PAGE/GOT_OFST (big got) or
5631 relax_start (offset_expr
.X_add_symbol
);
5632 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
5633 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL16
,
5636 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
5637 PIC_CALL_REG
, BFD_RELOC_MIPS_GOT_DISP
,
5643 relax_start (offset_expr
.X_add_symbol
);
5644 macro_build (&offset_expr
, "lui", "t,u", PIC_CALL_REG
,
5645 BFD_RELOC_MIPS_CALL_HI16
);
5646 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", PIC_CALL_REG
,
5647 PIC_CALL_REG
, mips_gp_register
);
5648 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
5649 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL_LO16
,
5652 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
5653 PIC_CALL_REG
, BFD_RELOC_MIPS_GOT_PAGE
,
5655 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
5656 PIC_CALL_REG
, PIC_CALL_REG
,
5657 BFD_RELOC_MIPS_GOT_OFST
);
5661 macro_build_jalr (&offset_expr
);
5665 relax_start (offset_expr
.X_add_symbol
);
5668 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
5669 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL16
,
5678 gpdelay
= reg_needs_delay (mips_gp_register
);
5679 macro_build (&offset_expr
, "lui", "t,u", PIC_CALL_REG
,
5680 BFD_RELOC_MIPS_CALL_HI16
);
5681 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", PIC_CALL_REG
,
5682 PIC_CALL_REG
, mips_gp_register
);
5683 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
5684 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL_LO16
,
5689 macro_build (NULL
, "nop", "");
5691 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
5692 PIC_CALL_REG
, BFD_RELOC_MIPS_GOT16
,
5695 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
5696 PIC_CALL_REG
, PIC_CALL_REG
, BFD_RELOC_LO16
);
5698 macro_build_jalr (&offset_expr
);
5700 if (mips_cprestore_offset
< 0)
5701 as_warn (_("No .cprestore pseudo-op used in PIC code"));
5704 if (! mips_frame_reg_valid
)
5706 as_warn (_("No .frame pseudo-op used in PIC code"));
5707 /* Quiet this warning. */
5708 mips_frame_reg_valid
= 1;
5710 if (! mips_cprestore_valid
)
5712 as_warn (_("No .cprestore pseudo-op used in PIC code"));
5713 /* Quiet this warning. */
5714 mips_cprestore_valid
= 1;
5716 if (mips_opts
.noreorder
)
5717 macro_build (NULL
, "nop", "");
5718 expr1
.X_add_number
= mips_cprestore_offset
;
5719 macro_build_ldst_constoffset (&expr1
, ADDRESS_LOAD_INSN
,
5722 HAVE_64BIT_ADDRESSES
);
5748 /* Itbl support may require additional care here. */
5753 /* Itbl support may require additional care here. */
5758 /* Itbl support may require additional care here. */
5763 /* Itbl support may require additional care here. */
5775 if (mips_opts
.arch
== CPU_R4650
)
5777 as_bad (_("opcode not supported on this processor"));
5781 /* Itbl support may require additional care here. */
5786 /* Itbl support may require additional care here. */
5791 /* Itbl support may require additional care here. */
5811 if (breg
== treg
|| coproc
|| lr
)
5832 /* Itbl support may require additional care here. */
5837 /* Itbl support may require additional care here. */
5842 /* Itbl support may require additional care here. */
5847 /* Itbl support may require additional care here. */
5863 if (mips_opts
.arch
== CPU_R4650
)
5865 as_bad (_("opcode not supported on this processor"));
5870 /* Itbl support may require additional care here. */
5874 /* Itbl support may require additional care here. */
5879 /* Itbl support may require additional care here. */
5891 /* Itbl support may require additional care here. */
5892 if (mask
== M_LWC1_AB
5893 || mask
== M_SWC1_AB
5894 || mask
== M_LDC1_AB
5895 || mask
== M_SDC1_AB
5904 if (offset_expr
.X_op
!= O_constant
5905 && offset_expr
.X_op
!= O_symbol
)
5907 as_bad (_("expression too complex"));
5908 offset_expr
.X_op
= O_constant
;
5911 /* A constant expression in PIC code can be handled just as it
5912 is in non PIC code. */
5913 if (offset_expr
.X_op
== O_constant
)
5915 if (HAVE_32BIT_ADDRESSES
5916 && !IS_SEXT_32BIT_NUM (offset_expr
.X_add_number
))
5917 as_bad (_("constant too large"));
5919 expr1
.X_add_number
= ((offset_expr
.X_add_number
+ 0x8000)
5920 & ~(bfd_vma
) 0xffff);
5921 load_register (tempreg
, &expr1
, HAVE_64BIT_ADDRESSES
);
5923 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5924 tempreg
, tempreg
, breg
);
5925 macro_build (&offset_expr
, s
, fmt
, treg
, BFD_RELOC_LO16
, tempreg
);
5927 else if (mips_pic
== NO_PIC
)
5929 /* If this is a reference to a GP relative symbol, and there
5930 is no base register, we want
5931 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
5932 Otherwise, if there is no base register, we want
5933 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
5934 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5935 If we have a constant, we need two instructions anyhow,
5936 so we always use the latter form.
5938 If we have a base register, and this is a reference to a
5939 GP relative symbol, we want
5940 addu $tempreg,$breg,$gp
5941 <op> $treg,<sym>($tempreg) (BFD_RELOC_GPREL16)
5943 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
5944 addu $tempreg,$tempreg,$breg
5945 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5946 With a constant we always use the latter case.
5948 With 64bit address space and no base register and $at usable,
5950 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5951 lui $at,<sym> (BFD_RELOC_HI16_S)
5952 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
5955 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5956 If we have a base register, we want
5957 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5958 lui $at,<sym> (BFD_RELOC_HI16_S)
5959 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
5963 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5965 Without $at we can't generate the optimal path for superscalar
5966 processors here since this would require two temporary registers.
5967 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5968 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
5970 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
5972 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5973 If we have a base register, we want
5974 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5975 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
5977 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
5979 daddu $tempreg,$tempreg,$breg
5980 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5982 For GP relative symbols in 64bit address space we can use
5983 the same sequence as in 32bit address space. */
5984 if (HAVE_64BIT_SYMBOLS
)
5986 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
5987 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
5989 relax_start (offset_expr
.X_add_symbol
);
5992 macro_build (&offset_expr
, s
, fmt
, treg
,
5993 BFD_RELOC_GPREL16
, mips_gp_register
);
5997 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5998 tempreg
, breg
, mips_gp_register
);
5999 macro_build (&offset_expr
, s
, fmt
, treg
,
6000 BFD_RELOC_GPREL16
, tempreg
);
6005 if (used_at
== 0 && !mips_opts
.noat
)
6007 macro_build (&offset_expr
, "lui", "t,u", tempreg
,
6008 BFD_RELOC_MIPS_HIGHEST
);
6009 macro_build (&offset_expr
, "lui", "t,u", AT
,
6011 macro_build (&offset_expr
, "daddiu", "t,r,j", tempreg
,
6012 tempreg
, BFD_RELOC_MIPS_HIGHER
);
6014 macro_build (NULL
, "daddu", "d,v,t", AT
, AT
, breg
);
6015 macro_build (NULL
, "dsll32", "d,w,<", tempreg
, tempreg
, 0);
6016 macro_build (NULL
, "daddu", "d,v,t", tempreg
, tempreg
, AT
);
6017 macro_build (&offset_expr
, s
, fmt
, treg
, BFD_RELOC_LO16
,
6023 macro_build (&offset_expr
, "lui", "t,u", tempreg
,
6024 BFD_RELOC_MIPS_HIGHEST
);
6025 macro_build (&offset_expr
, "daddiu", "t,r,j", tempreg
,
6026 tempreg
, BFD_RELOC_MIPS_HIGHER
);
6027 macro_build (NULL
, "dsll", "d,w,<", tempreg
, tempreg
, 16);
6028 macro_build (&offset_expr
, "daddiu", "t,r,j", tempreg
,
6029 tempreg
, BFD_RELOC_HI16_S
);
6030 macro_build (NULL
, "dsll", "d,w,<", tempreg
, tempreg
, 16);
6032 macro_build (NULL
, "daddu", "d,v,t",
6033 tempreg
, tempreg
, breg
);
6034 macro_build (&offset_expr
, s
, fmt
, treg
,
6035 BFD_RELOC_LO16
, tempreg
);
6038 if (mips_relax
.sequence
)
6045 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
6046 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
6048 relax_start (offset_expr
.X_add_symbol
);
6049 macro_build (&offset_expr
, s
, fmt
, treg
, BFD_RELOC_GPREL16
,
6053 macro_build_lui (&offset_expr
, tempreg
);
6054 macro_build (&offset_expr
, s
, fmt
, treg
,
6055 BFD_RELOC_LO16
, tempreg
);
6056 if (mips_relax
.sequence
)
6061 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
6062 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
6064 relax_start (offset_expr
.X_add_symbol
);
6065 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6066 tempreg
, breg
, mips_gp_register
);
6067 macro_build (&offset_expr
, s
, fmt
, treg
,
6068 BFD_RELOC_GPREL16
, tempreg
);
6071 macro_build_lui (&offset_expr
, tempreg
);
6072 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6073 tempreg
, tempreg
, breg
);
6074 macro_build (&offset_expr
, s
, fmt
, treg
,
6075 BFD_RELOC_LO16
, tempreg
);
6076 if (mips_relax
.sequence
)
6080 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
6082 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT16
;
6084 /* If this is a reference to an external symbol, we want
6085 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6087 <op> $treg,0($tempreg)
6089 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6091 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
6092 <op> $treg,0($tempreg)
6095 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
6096 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST)
6098 If there is a base register, we add it to $tempreg before
6099 the <op>. If there is a constant, we stick it in the
6100 <op> instruction. We don't handle constants larger than
6101 16 bits, because we have no way to load the upper 16 bits
6102 (actually, we could handle them for the subset of cases
6103 in which we are not using $at). */
6104 assert (offset_expr
.X_op
== O_symbol
);
6107 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
6108 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
6110 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6111 tempreg
, tempreg
, breg
);
6112 macro_build (&offset_expr
, s
, fmt
, treg
,
6113 BFD_RELOC_MIPS_GOT_OFST
, tempreg
);
6116 expr1
.X_add_number
= offset_expr
.X_add_number
;
6117 offset_expr
.X_add_number
= 0;
6118 if (expr1
.X_add_number
< -0x8000
6119 || expr1
.X_add_number
>= 0x8000)
6120 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6121 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
6122 lw_reloc_type
, mips_gp_register
);
6124 relax_start (offset_expr
.X_add_symbol
);
6126 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j", tempreg
,
6127 tempreg
, BFD_RELOC_LO16
);
6130 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6131 tempreg
, tempreg
, breg
);
6132 macro_build (&expr1
, s
, fmt
, treg
, BFD_RELOC_LO16
, tempreg
);
6134 else if (mips_pic
== SVR4_PIC
&& ! HAVE_NEWABI
)
6138 /* If this is a reference to an external symbol, we want
6139 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
6140 addu $tempreg,$tempreg,$gp
6141 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
6142 <op> $treg,0($tempreg)
6144 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6146 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
6147 <op> $treg,0($tempreg)
6148 If there is a base register, we add it to $tempreg before
6149 the <op>. If there is a constant, we stick it in the
6150 <op> instruction. We don't handle constants larger than
6151 16 bits, because we have no way to load the upper 16 bits
6152 (actually, we could handle them for the subset of cases
6153 in which we are not using $at). */
6154 assert (offset_expr
.X_op
== O_symbol
);
6155 expr1
.X_add_number
= offset_expr
.X_add_number
;
6156 offset_expr
.X_add_number
= 0;
6157 if (expr1
.X_add_number
< -0x8000
6158 || expr1
.X_add_number
>= 0x8000)
6159 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6160 gpdelay
= reg_needs_delay (mips_gp_register
);
6161 relax_start (offset_expr
.X_add_symbol
);
6162 macro_build (&offset_expr
, "lui", "t,u", tempreg
,
6163 BFD_RELOC_MIPS_GOT_HI16
);
6164 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", tempreg
, tempreg
,
6166 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
6167 BFD_RELOC_MIPS_GOT_LO16
, tempreg
);
6170 macro_build (NULL
, "nop", "");
6171 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
6172 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
6174 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j", tempreg
,
6175 tempreg
, BFD_RELOC_LO16
);
6179 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6180 tempreg
, tempreg
, breg
);
6181 macro_build (&expr1
, s
, fmt
, treg
, BFD_RELOC_LO16
, tempreg
);
6183 else if (mips_pic
== SVR4_PIC
&& HAVE_NEWABI
)
6185 /* If this is a reference to an external symbol, we want
6186 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
6187 add $tempreg,$tempreg,$gp
6188 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
6189 <op> $treg,<ofst>($tempreg)
6190 Otherwise, for local symbols, we want:
6191 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
6192 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST) */
6193 assert (offset_expr
.X_op
== O_symbol
);
6194 expr1
.X_add_number
= offset_expr
.X_add_number
;
6195 offset_expr
.X_add_number
= 0;
6196 if (expr1
.X_add_number
< -0x8000
6197 || expr1
.X_add_number
>= 0x8000)
6198 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6199 relax_start (offset_expr
.X_add_symbol
);
6200 macro_build (&offset_expr
, "lui", "t,u", tempreg
,
6201 BFD_RELOC_MIPS_GOT_HI16
);
6202 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", tempreg
, tempreg
,
6204 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
6205 BFD_RELOC_MIPS_GOT_LO16
, tempreg
);
6207 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6208 tempreg
, tempreg
, breg
);
6209 macro_build (&expr1
, s
, fmt
, treg
, BFD_RELOC_LO16
, tempreg
);
6212 offset_expr
.X_add_number
= expr1
.X_add_number
;
6213 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
6214 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
6216 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6217 tempreg
, tempreg
, breg
);
6218 macro_build (&offset_expr
, s
, fmt
, treg
,
6219 BFD_RELOC_MIPS_GOT_OFST
, tempreg
);
6229 load_register (treg
, &imm_expr
, 0);
6233 load_register (treg
, &imm_expr
, 1);
6237 if (imm_expr
.X_op
== O_constant
)
6240 load_register (AT
, &imm_expr
, 0);
6241 macro_build (NULL
, "mtc1", "t,G", AT
, treg
);
6246 assert (offset_expr
.X_op
== O_symbol
6247 && strcmp (segment_name (S_GET_SEGMENT
6248 (offset_expr
.X_add_symbol
)),
6250 && offset_expr
.X_add_number
== 0);
6251 macro_build (&offset_expr
, "lwc1", "T,o(b)", treg
,
6252 BFD_RELOC_MIPS_LITERAL
, mips_gp_register
);
6257 /* Check if we have a constant in IMM_EXPR. If the GPRs are 64 bits
6258 wide, IMM_EXPR is the entire value. Otherwise IMM_EXPR is the high
6259 order 32 bits of the value and the low order 32 bits are either
6260 zero or in OFFSET_EXPR. */
6261 if (imm_expr
.X_op
== O_constant
|| imm_expr
.X_op
== O_big
)
6263 if (HAVE_64BIT_GPRS
)
6264 load_register (treg
, &imm_expr
, 1);
6269 if (target_big_endian
)
6281 load_register (hreg
, &imm_expr
, 0);
6284 if (offset_expr
.X_op
== O_absent
)
6285 move_register (lreg
, 0);
6288 assert (offset_expr
.X_op
== O_constant
);
6289 load_register (lreg
, &offset_expr
, 0);
6296 /* We know that sym is in the .rdata section. First we get the
6297 upper 16 bits of the address. */
6298 if (mips_pic
== NO_PIC
)
6300 macro_build_lui (&offset_expr
, AT
);
6303 else if (mips_pic
== SVR4_PIC
)
6305 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", AT
,
6306 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
6312 /* Now we load the register(s). */
6313 if (HAVE_64BIT_GPRS
)
6316 macro_build (&offset_expr
, "ld", "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
6321 macro_build (&offset_expr
, "lw", "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
6324 /* FIXME: How in the world do we deal with the possible
6326 offset_expr
.X_add_number
+= 4;
6327 macro_build (&offset_expr
, "lw", "t,o(b)",
6328 treg
+ 1, BFD_RELOC_LO16
, AT
);
6334 /* Check if we have a constant in IMM_EXPR. If the FPRs are 64 bits
6335 wide, IMM_EXPR is the entire value and the GPRs are known to be 64
6336 bits wide as well. Otherwise IMM_EXPR is the high order 32 bits of
6337 the value and the low order 32 bits are either zero or in
6339 if (imm_expr
.X_op
== O_constant
|| imm_expr
.X_op
== O_big
)
6342 load_register (AT
, &imm_expr
, HAVE_64BIT_FPRS
);
6343 if (HAVE_64BIT_FPRS
)
6345 assert (HAVE_64BIT_GPRS
);
6346 macro_build (NULL
, "dmtc1", "t,S", AT
, treg
);
6350 macro_build (NULL
, "mtc1", "t,G", AT
, treg
+ 1);
6351 if (offset_expr
.X_op
== O_absent
)
6352 macro_build (NULL
, "mtc1", "t,G", 0, treg
);
6355 assert (offset_expr
.X_op
== O_constant
);
6356 load_register (AT
, &offset_expr
, 0);
6357 macro_build (NULL
, "mtc1", "t,G", AT
, treg
);
6363 assert (offset_expr
.X_op
== O_symbol
6364 && offset_expr
.X_add_number
== 0);
6365 s
= segment_name (S_GET_SEGMENT (offset_expr
.X_add_symbol
));
6366 if (strcmp (s
, ".lit8") == 0)
6368 if (mips_opts
.isa
!= ISA_MIPS1
)
6370 macro_build (&offset_expr
, "ldc1", "T,o(b)", treg
,
6371 BFD_RELOC_MIPS_LITERAL
, mips_gp_register
);
6374 breg
= mips_gp_register
;
6375 r
= BFD_RELOC_MIPS_LITERAL
;
6380 assert (strcmp (s
, RDATA_SECTION_NAME
) == 0);
6382 if (mips_pic
== SVR4_PIC
)
6383 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", AT
,
6384 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
6387 /* FIXME: This won't work for a 64 bit address. */
6388 macro_build_lui (&offset_expr
, AT
);
6391 if (mips_opts
.isa
!= ISA_MIPS1
)
6393 macro_build (&offset_expr
, "ldc1", "T,o(b)",
6394 treg
, BFD_RELOC_LO16
, AT
);
6403 if (mips_opts
.arch
== CPU_R4650
)
6405 as_bad (_("opcode not supported on this processor"));
6408 /* Even on a big endian machine $fn comes before $fn+1. We have
6409 to adjust when loading from memory. */
6412 assert (mips_opts
.isa
== ISA_MIPS1
);
6413 macro_build (&offset_expr
, "lwc1", "T,o(b)",
6414 target_big_endian
? treg
+ 1 : treg
, r
, breg
);
6415 /* FIXME: A possible overflow which I don't know how to deal
6417 offset_expr
.X_add_number
+= 4;
6418 macro_build (&offset_expr
, "lwc1", "T,o(b)",
6419 target_big_endian
? treg
: treg
+ 1, r
, breg
);
6424 * The MIPS assembler seems to check for X_add_number not
6425 * being double aligned and generating:
6428 * addiu at,at,%lo(foo+1)
6431 * But, the resulting address is the same after relocation so why
6432 * generate the extra instruction?
6434 if (mips_opts
.arch
== CPU_R4650
)
6436 as_bad (_("opcode not supported on this processor"));
6439 /* Itbl support may require additional care here. */
6441 if (mips_opts
.isa
!= ISA_MIPS1
)
6452 if (mips_opts
.arch
== CPU_R4650
)
6454 as_bad (_("opcode not supported on this processor"));
6458 if (mips_opts
.isa
!= ISA_MIPS1
)
6466 /* Itbl support may require additional care here. */
6471 if (HAVE_64BIT_GPRS
)
6482 if (HAVE_64BIT_GPRS
)
6492 if (offset_expr
.X_op
!= O_symbol
6493 && offset_expr
.X_op
!= O_constant
)
6495 as_bad (_("expression too complex"));
6496 offset_expr
.X_op
= O_constant
;
6499 /* Even on a big endian machine $fn comes before $fn+1. We have
6500 to adjust when loading from memory. We set coproc if we must
6501 load $fn+1 first. */
6502 /* Itbl support may require additional care here. */
6503 if (! target_big_endian
)
6506 if (mips_pic
== NO_PIC
6507 || offset_expr
.X_op
== O_constant
)
6509 /* If this is a reference to a GP relative symbol, we want
6510 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
6511 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_GPREL16)
6512 If we have a base register, we use this
6514 <op> $treg,<sym>($at) (BFD_RELOC_GPREL16)
6515 <op> $treg+1,<sym>+4($at) (BFD_RELOC_GPREL16)
6516 If this is not a GP relative symbol, we want
6517 lui $at,<sym> (BFD_RELOC_HI16_S)
6518 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
6519 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
6520 If there is a base register, we add it to $at after the
6521 lui instruction. If there is a constant, we always use
6523 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
6524 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
6526 relax_start (offset_expr
.X_add_symbol
);
6529 tempreg
= mips_gp_register
;
6533 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6534 AT
, breg
, mips_gp_register
);
6539 /* Itbl support may require additional care here. */
6540 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
+ 1 : treg
,
6541 BFD_RELOC_GPREL16
, tempreg
);
6542 offset_expr
.X_add_number
+= 4;
6544 /* Set mips_optimize to 2 to avoid inserting an
6546 hold_mips_optimize
= mips_optimize
;
6548 /* Itbl support may require additional care here. */
6549 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
: treg
+ 1,
6550 BFD_RELOC_GPREL16
, tempreg
);
6551 mips_optimize
= hold_mips_optimize
;
6555 /* We just generated two relocs. When tc_gen_reloc
6556 handles this case, it will skip the first reloc and
6557 handle the second. The second reloc already has an
6558 extra addend of 4, which we added above. We must
6559 subtract it out, and then subtract another 4 to make
6560 the first reloc come out right. The second reloc
6561 will come out right because we are going to add 4 to
6562 offset_expr when we build its instruction below.
6564 If we have a symbol, then we don't want to include
6565 the offset, because it will wind up being included
6566 when we generate the reloc. */
6568 if (offset_expr
.X_op
== O_constant
)
6569 offset_expr
.X_add_number
-= 8;
6572 offset_expr
.X_add_number
= -4;
6573 offset_expr
.X_op
= O_constant
;
6577 macro_build_lui (&offset_expr
, AT
);
6579 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
6580 /* Itbl support may require additional care here. */
6581 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
+ 1 : treg
,
6582 BFD_RELOC_LO16
, AT
);
6583 /* FIXME: How do we handle overflow here? */
6584 offset_expr
.X_add_number
+= 4;
6585 /* Itbl support may require additional care here. */
6586 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
: treg
+ 1,
6587 BFD_RELOC_LO16
, AT
);
6588 if (mips_relax
.sequence
)
6591 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
6593 /* If this is a reference to an external symbol, we want
6594 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6599 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6601 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
6602 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
6603 If there is a base register we add it to $at before the
6604 lwc1 instructions. If there is a constant we include it
6605 in the lwc1 instructions. */
6607 expr1
.X_add_number
= offset_expr
.X_add_number
;
6608 if (expr1
.X_add_number
< -0x8000
6609 || expr1
.X_add_number
>= 0x8000 - 4)
6610 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6611 load_got_offset (AT
, &offset_expr
);
6614 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
6616 /* Set mips_optimize to 2 to avoid inserting an undesired
6618 hold_mips_optimize
= mips_optimize
;
6621 /* Itbl support may require additional care here. */
6622 relax_start (offset_expr
.X_add_symbol
);
6623 macro_build (&expr1
, s
, fmt
, coproc
? treg
+ 1 : treg
,
6624 BFD_RELOC_LO16
, AT
);
6625 expr1
.X_add_number
+= 4;
6626 macro_build (&expr1
, s
, fmt
, coproc
? treg
: treg
+ 1,
6627 BFD_RELOC_LO16
, AT
);
6629 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
+ 1 : treg
,
6630 BFD_RELOC_LO16
, AT
);
6631 offset_expr
.X_add_number
+= 4;
6632 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
: treg
+ 1,
6633 BFD_RELOC_LO16
, AT
);
6636 mips_optimize
= hold_mips_optimize
;
6638 else if (mips_pic
== SVR4_PIC
)
6642 /* If this is a reference to an external symbol, we want
6643 lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16)
6645 lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16)
6650 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6652 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
6653 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
6654 If there is a base register we add it to $at before the
6655 lwc1 instructions. If there is a constant we include it
6656 in the lwc1 instructions. */
6658 expr1
.X_add_number
= offset_expr
.X_add_number
;
6659 offset_expr
.X_add_number
= 0;
6660 if (expr1
.X_add_number
< -0x8000
6661 || expr1
.X_add_number
>= 0x8000 - 4)
6662 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6663 gpdelay
= reg_needs_delay (mips_gp_register
);
6664 relax_start (offset_expr
.X_add_symbol
);
6665 macro_build (&offset_expr
, "lui", "t,u",
6666 AT
, BFD_RELOC_MIPS_GOT_HI16
);
6667 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6668 AT
, AT
, mips_gp_register
);
6669 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
6670 AT
, BFD_RELOC_MIPS_GOT_LO16
, AT
);
6673 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
6674 /* Itbl support may require additional care here. */
6675 macro_build (&expr1
, s
, fmt
, coproc
? treg
+ 1 : treg
,
6676 BFD_RELOC_LO16
, AT
);
6677 expr1
.X_add_number
+= 4;
6679 /* Set mips_optimize to 2 to avoid inserting an undesired
6681 hold_mips_optimize
= mips_optimize
;
6683 /* Itbl support may require additional care here. */
6684 macro_build (&expr1
, s
, fmt
, coproc
? treg
: treg
+ 1,
6685 BFD_RELOC_LO16
, AT
);
6686 mips_optimize
= hold_mips_optimize
;
6687 expr1
.X_add_number
-= 4;
6690 offset_expr
.X_add_number
= expr1
.X_add_number
;
6692 macro_build (NULL
, "nop", "");
6693 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", AT
,
6694 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
6697 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
6698 /* Itbl support may require additional care here. */
6699 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
+ 1 : treg
,
6700 BFD_RELOC_LO16
, AT
);
6701 offset_expr
.X_add_number
+= 4;
6703 /* Set mips_optimize to 2 to avoid inserting an undesired
6705 hold_mips_optimize
= mips_optimize
;
6707 /* Itbl support may require additional care here. */
6708 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
: treg
+ 1,
6709 BFD_RELOC_LO16
, AT
);
6710 mips_optimize
= hold_mips_optimize
;
6724 assert (HAVE_32BIT_ADDRESSES
);
6725 macro_build (&offset_expr
, s
, "t,o(b)", treg
, BFD_RELOC_LO16
, breg
);
6726 offset_expr
.X_add_number
+= 4;
6727 macro_build (&offset_expr
, s
, "t,o(b)", treg
+ 1, BFD_RELOC_LO16
, breg
);
6730 /* New code added to support COPZ instructions.
6731 This code builds table entries out of the macros in mip_opcodes.
6732 R4000 uses interlocks to handle coproc delays.
6733 Other chips (like the R3000) require nops to be inserted for delays.
6735 FIXME: Currently, we require that the user handle delays.
6736 In order to fill delay slots for non-interlocked chips,
6737 we must have a way to specify delays based on the coprocessor.
6738 Eg. 4 cycles if load coproc reg from memory, 1 if in cache, etc.
6739 What are the side-effects of the cop instruction?
6740 What cache support might we have and what are its effects?
6741 Both coprocessor & memory require delays. how long???
6742 What registers are read/set/modified?
6744 If an itbl is provided to interpret cop instructions,
6745 this knowledge can be encoded in the itbl spec. */
6759 /* For now we just do C (same as Cz). The parameter will be
6760 stored in insn_opcode by mips_ip. */
6761 macro_build (NULL
, s
, "C", ip
->insn_opcode
);
6765 move_register (dreg
, sreg
);
6768 #ifdef LOSING_COMPILER
6770 /* Try and see if this is a new itbl instruction.
6771 This code builds table entries out of the macros in mip_opcodes.
6772 FIXME: For now we just assemble the expression and pass it's
6773 value along as a 32-bit immediate.
6774 We may want to have the assembler assemble this value,
6775 so that we gain the assembler's knowledge of delay slots,
6777 Would it be more efficient to use mask (id) here? */
6778 if (itbl_have_entries
6779 && (immed_expr
= itbl_assemble (ip
->insn_mo
->name
, "")))
6781 s
= ip
->insn_mo
->name
;
6783 coproc
= ITBL_DECODE_PNUM (immed_expr
);;
6784 macro_build (&immed_expr
, s
, "C");
6790 if (mips_opts
.noat
&& used_at
)
6791 as_bad (_("Macro used $at after \".set noat\""));
6795 macro2 (struct mips_cl_insn
*ip
)
6797 register int treg
, sreg
, dreg
, breg
;
6812 bfd_reloc_code_real_type r
;
6814 treg
= (ip
->insn_opcode
>> 16) & 0x1f;
6815 dreg
= (ip
->insn_opcode
>> 11) & 0x1f;
6816 sreg
= breg
= (ip
->insn_opcode
>> 21) & 0x1f;
6817 mask
= ip
->insn_mo
->mask
;
6819 expr1
.X_op
= O_constant
;
6820 expr1
.X_op_symbol
= NULL
;
6821 expr1
.X_add_symbol
= NULL
;
6822 expr1
.X_add_number
= 1;
6826 #endif /* LOSING_COMPILER */
6831 macro_build (NULL
, dbl
? "dmultu" : "multu", "s,t", sreg
, treg
);
6832 macro_build (NULL
, "mflo", "d", dreg
);
6838 /* The MIPS assembler some times generates shifts and adds. I'm
6839 not trying to be that fancy. GCC should do this for us
6842 load_register (AT
, &imm_expr
, dbl
);
6843 macro_build (NULL
, dbl
? "dmult" : "mult", "s,t", sreg
, AT
);
6844 macro_build (NULL
, "mflo", "d", dreg
);
6857 mips_emit_delays (TRUE
);
6858 ++mips_opts
.noreorder
;
6859 mips_any_noreorder
= 1;
6862 load_register (AT
, &imm_expr
, dbl
);
6863 macro_build (NULL
, dbl
? "dmult" : "mult", "s,t", sreg
, imm
? AT
: treg
);
6864 macro_build (NULL
, "mflo", "d", dreg
);
6865 macro_build (NULL
, dbl
? "dsra32" : "sra", "d,w,<", dreg
, dreg
, RA
);
6866 macro_build (NULL
, "mfhi", "d", AT
);
6868 macro_build (NULL
, "tne", "s,t,q", dreg
, AT
, 6);
6871 expr1
.X_add_number
= 8;
6872 macro_build (&expr1
, "beq", "s,t,p", dreg
, AT
);
6873 macro_build (NULL
, "nop", "", 0);
6874 macro_build (NULL
, "break", "c", 6);
6876 --mips_opts
.noreorder
;
6877 macro_build (NULL
, "mflo", "d", dreg
);
6890 mips_emit_delays (TRUE
);
6891 ++mips_opts
.noreorder
;
6892 mips_any_noreorder
= 1;
6895 load_register (AT
, &imm_expr
, dbl
);
6896 macro_build (NULL
, dbl
? "dmultu" : "multu", "s,t",
6897 sreg
, imm
? AT
: treg
);
6898 macro_build (NULL
, "mfhi", "d", AT
);
6899 macro_build (NULL
, "mflo", "d", dreg
);
6901 macro_build (NULL
, "tne", "s,t,q", AT
, 0, 6);
6904 expr1
.X_add_number
= 8;
6905 macro_build (&expr1
, "beq", "s,t,p", AT
, 0);
6906 macro_build (NULL
, "nop", "", 0);
6907 macro_build (NULL
, "break", "c", 6);
6909 --mips_opts
.noreorder
;
6913 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
6924 macro_build (NULL
, "dnegu", "d,w", tempreg
, treg
);
6925 macro_build (NULL
, "drorv", "d,t,s", dreg
, sreg
, tempreg
);
6929 macro_build (NULL
, "dsubu", "d,v,t", AT
, 0, treg
);
6930 macro_build (NULL
, "dsrlv", "d,t,s", AT
, sreg
, AT
);
6931 macro_build (NULL
, "dsllv", "d,t,s", dreg
, sreg
, treg
);
6932 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
6936 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
6947 macro_build (NULL
, "negu", "d,w", tempreg
, treg
);
6948 macro_build (NULL
, "rorv", "d,t,s", dreg
, sreg
, tempreg
);
6952 macro_build (NULL
, "subu", "d,v,t", AT
, 0, treg
);
6953 macro_build (NULL
, "srlv", "d,t,s", AT
, sreg
, AT
);
6954 macro_build (NULL
, "sllv", "d,t,s", dreg
, sreg
, treg
);
6955 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
6963 if (imm_expr
.X_op
!= O_constant
)
6964 as_bad (_("Improper rotate count"));
6965 rot
= imm_expr
.X_add_number
& 0x3f;
6966 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
6968 rot
= (64 - rot
) & 0x3f;
6970 macro_build (NULL
, "dror32", "d,w,<", dreg
, sreg
, rot
- 32);
6972 macro_build (NULL
, "dror", "d,w,<", dreg
, sreg
, rot
);
6977 macro_build (NULL
, "dsrl", "d,w,<", dreg
, sreg
, 0);
6980 l
= (rot
< 0x20) ? "dsll" : "dsll32";
6981 r
= ((0x40 - rot
) < 0x20) ? "dsrl" : "dsrl32";
6984 macro_build (NULL
, l
, "d,w,<", AT
, sreg
, rot
);
6985 macro_build (NULL
, r
, "d,w,<", dreg
, sreg
, (0x20 - rot
) & 0x1f);
6986 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
6994 if (imm_expr
.X_op
!= O_constant
)
6995 as_bad (_("Improper rotate count"));
6996 rot
= imm_expr
.X_add_number
& 0x1f;
6997 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
6999 macro_build (NULL
, "ror", "d,w,<", dreg
, sreg
, (32 - rot
) & 0x1f);
7004 macro_build (NULL
, "srl", "d,w,<", dreg
, sreg
, 0);
7008 macro_build (NULL
, "sll", "d,w,<", AT
, sreg
, rot
);
7009 macro_build (NULL
, "srl", "d,w,<", dreg
, sreg
, (0x20 - rot
) & 0x1f);
7010 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
7015 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
7017 macro_build (NULL
, "drorv", "d,t,s", dreg
, sreg
, treg
);
7021 macro_build (NULL
, "dsubu", "d,v,t", AT
, 0, treg
);
7022 macro_build (NULL
, "dsllv", "d,t,s", AT
, sreg
, AT
);
7023 macro_build (NULL
, "dsrlv", "d,t,s", dreg
, sreg
, treg
);
7024 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
7028 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
7030 macro_build (NULL
, "rorv", "d,t,s", dreg
, sreg
, treg
);
7034 macro_build (NULL
, "subu", "d,v,t", AT
, 0, treg
);
7035 macro_build (NULL
, "sllv", "d,t,s", AT
, sreg
, AT
);
7036 macro_build (NULL
, "srlv", "d,t,s", dreg
, sreg
, treg
);
7037 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
7045 if (imm_expr
.X_op
!= O_constant
)
7046 as_bad (_("Improper rotate count"));
7047 rot
= imm_expr
.X_add_number
& 0x3f;
7048 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
7051 macro_build (NULL
, "dror32", "d,w,<", dreg
, sreg
, rot
- 32);
7053 macro_build (NULL
, "dror", "d,w,<", dreg
, sreg
, rot
);
7058 macro_build (NULL
, "dsrl", "d,w,<", dreg
, sreg
, 0);
7061 r
= (rot
< 0x20) ? "dsrl" : "dsrl32";
7062 l
= ((0x40 - rot
) < 0x20) ? "dsll" : "dsll32";
7065 macro_build (NULL
, r
, "d,w,<", AT
, sreg
, rot
);
7066 macro_build (NULL
, l
, "d,w,<", dreg
, sreg
, (0x20 - rot
) & 0x1f);
7067 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
7075 if (imm_expr
.X_op
!= O_constant
)
7076 as_bad (_("Improper rotate count"));
7077 rot
= imm_expr
.X_add_number
& 0x1f;
7078 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
7080 macro_build (NULL
, "ror", "d,w,<", dreg
, sreg
, rot
);
7085 macro_build (NULL
, "srl", "d,w,<", dreg
, sreg
, 0);
7089 macro_build (NULL
, "srl", "d,w,<", AT
, sreg
, rot
);
7090 macro_build (NULL
, "sll", "d,w,<", dreg
, sreg
, (0x20 - rot
) & 0x1f);
7091 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
7096 if (mips_opts
.arch
== CPU_R4650
)
7098 as_bad (_("opcode not supported on this processor"));
7101 assert (mips_opts
.isa
== ISA_MIPS1
);
7102 /* Even on a big endian machine $fn comes before $fn+1. We have
7103 to adjust when storing to memory. */
7104 macro_build (&offset_expr
, "swc1", "T,o(b)",
7105 target_big_endian
? treg
+ 1 : treg
, BFD_RELOC_LO16
, breg
);
7106 offset_expr
.X_add_number
+= 4;
7107 macro_build (&offset_expr
, "swc1", "T,o(b)",
7108 target_big_endian
? treg
: treg
+ 1, BFD_RELOC_LO16
, breg
);
7113 macro_build (&expr1
, "sltiu", "t,r,j", dreg
, treg
, BFD_RELOC_LO16
);
7115 macro_build (&expr1
, "sltiu", "t,r,j", dreg
, sreg
, BFD_RELOC_LO16
);
7118 macro_build (NULL
, "xor", "d,v,t", dreg
, sreg
, treg
);
7119 macro_build (&expr1
, "sltiu", "t,r,j", dreg
, dreg
, BFD_RELOC_LO16
);
7124 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
7126 macro_build (&expr1
, "sltiu", "t,r,j", dreg
, sreg
, BFD_RELOC_LO16
);
7131 as_warn (_("Instruction %s: result is always false"),
7133 move_register (dreg
, 0);
7136 if (imm_expr
.X_op
== O_constant
7137 && imm_expr
.X_add_number
>= 0
7138 && imm_expr
.X_add_number
< 0x10000)
7140 macro_build (&imm_expr
, "xori", "t,r,i", dreg
, sreg
, BFD_RELOC_LO16
);
7142 else if (imm_expr
.X_op
== O_constant
7143 && imm_expr
.X_add_number
> -0x8000
7144 && imm_expr
.X_add_number
< 0)
7146 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
7147 macro_build (&imm_expr
, HAVE_32BIT_GPRS
? "addiu" : "daddiu",
7148 "t,r,j", dreg
, sreg
, BFD_RELOC_LO16
);
7152 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7153 macro_build (NULL
, "xor", "d,v,t", dreg
, sreg
, AT
);
7156 macro_build (&expr1
, "sltiu", "t,r,j", dreg
, dreg
, BFD_RELOC_LO16
);
7159 case M_SGE
: /* sreg >= treg <==> not (sreg < treg) */
7165 macro_build (NULL
, s
, "d,v,t", dreg
, sreg
, treg
);
7166 macro_build (&expr1
, "xori", "t,r,i", dreg
, dreg
, BFD_RELOC_LO16
);
7169 case M_SGE_I
: /* sreg >= I <==> not (sreg < I) */
7171 if (imm_expr
.X_op
== O_constant
7172 && imm_expr
.X_add_number
>= -0x8000
7173 && imm_expr
.X_add_number
< 0x8000)
7175 macro_build (&imm_expr
, mask
== M_SGE_I
? "slti" : "sltiu", "t,r,j",
7176 dreg
, sreg
, BFD_RELOC_LO16
);
7180 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7181 macro_build (NULL
, mask
== M_SGE_I
? "slt" : "sltu", "d,v,t",
7185 macro_build (&expr1
, "xori", "t,r,i", dreg
, dreg
, BFD_RELOC_LO16
);
7188 case M_SGT
: /* sreg > treg <==> treg < sreg */
7194 macro_build (NULL
, s
, "d,v,t", dreg
, treg
, sreg
);
7197 case M_SGT_I
: /* sreg > I <==> I < sreg */
7204 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7205 macro_build (NULL
, s
, "d,v,t", dreg
, AT
, sreg
);
7208 case M_SLE
: /* sreg <= treg <==> treg >= sreg <==> not (treg < sreg) */
7214 macro_build (NULL
, s
, "d,v,t", dreg
, treg
, sreg
);
7215 macro_build (&expr1
, "xori", "t,r,i", dreg
, dreg
, BFD_RELOC_LO16
);
7218 case M_SLE_I
: /* sreg <= I <==> I >= sreg <==> not (I < sreg) */
7225 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7226 macro_build (NULL
, s
, "d,v,t", dreg
, AT
, sreg
);
7227 macro_build (&expr1
, "xori", "t,r,i", dreg
, dreg
, BFD_RELOC_LO16
);
7231 if (imm_expr
.X_op
== O_constant
7232 && imm_expr
.X_add_number
>= -0x8000
7233 && imm_expr
.X_add_number
< 0x8000)
7235 macro_build (&imm_expr
, "slti", "t,r,j", dreg
, sreg
, BFD_RELOC_LO16
);
7239 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7240 macro_build (NULL
, "slt", "d,v,t", dreg
, sreg
, AT
);
7244 if (imm_expr
.X_op
== O_constant
7245 && imm_expr
.X_add_number
>= -0x8000
7246 && imm_expr
.X_add_number
< 0x8000)
7248 macro_build (&imm_expr
, "sltiu", "t,r,j", dreg
, sreg
,
7253 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7254 macro_build (NULL
, "sltu", "d,v,t", dreg
, sreg
, AT
);
7259 macro_build (NULL
, "sltu", "d,v,t", dreg
, 0, treg
);
7261 macro_build (NULL
, "sltu", "d,v,t", dreg
, 0, sreg
);
7264 macro_build (NULL
, "xor", "d,v,t", dreg
, sreg
, treg
);
7265 macro_build (NULL
, "sltu", "d,v,t", dreg
, 0, dreg
);
7270 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
7272 macro_build (NULL
, "sltu", "d,v,t", dreg
, 0, sreg
);
7277 as_warn (_("Instruction %s: result is always true"),
7279 macro_build (&expr1
, HAVE_32BIT_GPRS
? "addiu" : "daddiu", "t,r,j",
7280 dreg
, 0, BFD_RELOC_LO16
);
7283 if (imm_expr
.X_op
== O_constant
7284 && imm_expr
.X_add_number
>= 0
7285 && imm_expr
.X_add_number
< 0x10000)
7287 macro_build (&imm_expr
, "xori", "t,r,i", dreg
, sreg
, BFD_RELOC_LO16
);
7289 else if (imm_expr
.X_op
== O_constant
7290 && imm_expr
.X_add_number
> -0x8000
7291 && imm_expr
.X_add_number
< 0)
7293 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
7294 macro_build (&imm_expr
, HAVE_32BIT_GPRS
? "addiu" : "daddiu",
7295 "t,r,j", dreg
, sreg
, BFD_RELOC_LO16
);
7299 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7300 macro_build (NULL
, "xor", "d,v,t", dreg
, sreg
, AT
);
7303 macro_build (NULL
, "sltu", "d,v,t", dreg
, 0, dreg
);
7309 if (imm_expr
.X_op
== O_constant
7310 && imm_expr
.X_add_number
> -0x8000
7311 && imm_expr
.X_add_number
<= 0x8000)
7313 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
7314 macro_build (&imm_expr
, dbl
? "daddi" : "addi", "t,r,j",
7315 dreg
, sreg
, BFD_RELOC_LO16
);
7319 load_register (AT
, &imm_expr
, dbl
);
7320 macro_build (NULL
, dbl
? "dsub" : "sub", "d,v,t", dreg
, sreg
, AT
);
7326 if (imm_expr
.X_op
== O_constant
7327 && imm_expr
.X_add_number
> -0x8000
7328 && imm_expr
.X_add_number
<= 0x8000)
7330 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
7331 macro_build (&imm_expr
, dbl
? "daddiu" : "addiu", "t,r,j",
7332 dreg
, sreg
, BFD_RELOC_LO16
);
7336 load_register (AT
, &imm_expr
, dbl
);
7337 macro_build (NULL
, dbl
? "dsubu" : "subu", "d,v,t", dreg
, sreg
, AT
);
7359 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7360 macro_build (NULL
, s
, "s,t", sreg
, AT
);
7365 assert (mips_opts
.isa
== ISA_MIPS1
);
7367 sreg
= (ip
->insn_opcode
>> 11) & 0x1f; /* floating reg */
7368 dreg
= (ip
->insn_opcode
>> 06) & 0x1f; /* floating reg */
7371 * Is the double cfc1 instruction a bug in the mips assembler;
7372 * or is there a reason for it?
7374 mips_emit_delays (TRUE
);
7375 ++mips_opts
.noreorder
;
7376 mips_any_noreorder
= 1;
7377 macro_build (NULL
, "cfc1", "t,G", treg
, RA
);
7378 macro_build (NULL
, "cfc1", "t,G", treg
, RA
);
7379 macro_build (NULL
, "nop", "");
7380 expr1
.X_add_number
= 3;
7381 macro_build (&expr1
, "ori", "t,r,i", AT
, treg
, BFD_RELOC_LO16
);
7382 expr1
.X_add_number
= 2;
7383 macro_build (&expr1
, "xori", "t,r,i", AT
, AT
, BFD_RELOC_LO16
);
7384 macro_build (NULL
, "ctc1", "t,G", AT
, RA
);
7385 macro_build (NULL
, "nop", "");
7386 macro_build (NULL
, mask
== M_TRUNCWD
? "cvt.w.d" : "cvt.w.s", "D,S",
7388 macro_build (NULL
, "ctc1", "t,G", treg
, RA
);
7389 macro_build (NULL
, "nop", "");
7390 --mips_opts
.noreorder
;
7400 if (offset_expr
.X_add_number
>= 0x7fff)
7401 as_bad (_("operand overflow"));
7402 if (! target_big_endian
)
7403 ++offset_expr
.X_add_number
;
7404 macro_build (&offset_expr
, s
, "t,o(b)", AT
, BFD_RELOC_LO16
, breg
);
7405 if (! target_big_endian
)
7406 --offset_expr
.X_add_number
;
7408 ++offset_expr
.X_add_number
;
7409 macro_build (&offset_expr
, "lbu", "t,o(b)", treg
, BFD_RELOC_LO16
, breg
);
7410 macro_build (NULL
, "sll", "d,w,<", AT
, AT
, 8);
7411 macro_build (NULL
, "or", "d,v,t", treg
, treg
, AT
);
7424 if (offset_expr
.X_add_number
>= 0x8000 - off
)
7425 as_bad (_("operand overflow"));
7433 if (! target_big_endian
)
7434 offset_expr
.X_add_number
+= off
;
7435 macro_build (&offset_expr
, s
, "t,o(b)", tempreg
, BFD_RELOC_LO16
, breg
);
7436 if (! target_big_endian
)
7437 offset_expr
.X_add_number
-= off
;
7439 offset_expr
.X_add_number
+= off
;
7440 macro_build (&offset_expr
, s2
, "t,o(b)", tempreg
, BFD_RELOC_LO16
, breg
);
7442 /* If necessary, move the result in tempreg the final destination. */
7443 if (treg
== tempreg
)
7445 /* Protect second load's delay slot. */
7447 move_register (treg
, tempreg
);
7461 load_address (AT
, &offset_expr
, &used_at
);
7463 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, AT
, breg
);
7464 if (! target_big_endian
)
7465 expr1
.X_add_number
= off
;
7467 expr1
.X_add_number
= 0;
7468 macro_build (&expr1
, s
, "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
7469 if (! target_big_endian
)
7470 expr1
.X_add_number
= 0;
7472 expr1
.X_add_number
= off
;
7473 macro_build (&expr1
, s2
, "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
7479 load_address (AT
, &offset_expr
, &used_at
);
7481 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, AT
, breg
);
7482 if (target_big_endian
)
7483 expr1
.X_add_number
= 0;
7484 macro_build (&expr1
, mask
== M_ULH_A
? "lb" : "lbu", "t,o(b)",
7485 treg
, BFD_RELOC_LO16
, AT
);
7486 if (target_big_endian
)
7487 expr1
.X_add_number
= 1;
7489 expr1
.X_add_number
= 0;
7490 macro_build (&expr1
, "lbu", "t,o(b)", AT
, BFD_RELOC_LO16
, AT
);
7491 macro_build (NULL
, "sll", "d,w,<", treg
, treg
, 8);
7492 macro_build (NULL
, "or", "d,v,t", treg
, treg
, AT
);
7497 if (offset_expr
.X_add_number
>= 0x7fff)
7498 as_bad (_("operand overflow"));
7499 if (target_big_endian
)
7500 ++offset_expr
.X_add_number
;
7501 macro_build (&offset_expr
, "sb", "t,o(b)", treg
, BFD_RELOC_LO16
, breg
);
7502 macro_build (NULL
, "srl", "d,w,<", AT
, treg
, 8);
7503 if (target_big_endian
)
7504 --offset_expr
.X_add_number
;
7506 ++offset_expr
.X_add_number
;
7507 macro_build (&offset_expr
, "sb", "t,o(b)", AT
, BFD_RELOC_LO16
, breg
);
7520 if (offset_expr
.X_add_number
>= 0x8000 - off
)
7521 as_bad (_("operand overflow"));
7522 if (! target_big_endian
)
7523 offset_expr
.X_add_number
+= off
;
7524 macro_build (&offset_expr
, s
, "t,o(b)", treg
, BFD_RELOC_LO16
, breg
);
7525 if (! target_big_endian
)
7526 offset_expr
.X_add_number
-= off
;
7528 offset_expr
.X_add_number
+= off
;
7529 macro_build (&offset_expr
, s2
, "t,o(b)", treg
, BFD_RELOC_LO16
, breg
);
7543 load_address (AT
, &offset_expr
, &used_at
);
7545 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, AT
, breg
);
7546 if (! target_big_endian
)
7547 expr1
.X_add_number
= off
;
7549 expr1
.X_add_number
= 0;
7550 macro_build (&expr1
, s
, "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
7551 if (! target_big_endian
)
7552 expr1
.X_add_number
= 0;
7554 expr1
.X_add_number
= off
;
7555 macro_build (&expr1
, s2
, "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
7560 load_address (AT
, &offset_expr
, &used_at
);
7562 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, AT
, breg
);
7563 if (! target_big_endian
)
7564 expr1
.X_add_number
= 0;
7565 macro_build (&expr1
, "sb", "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
7566 macro_build (NULL
, "srl", "d,w,<", treg
, treg
, 8);
7567 if (! target_big_endian
)
7568 expr1
.X_add_number
= 1;
7570 expr1
.X_add_number
= 0;
7571 macro_build (&expr1
, "sb", "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
7572 if (! target_big_endian
)
7573 expr1
.X_add_number
= 0;
7575 expr1
.X_add_number
= 1;
7576 macro_build (&expr1
, "lbu", "t,o(b)", AT
, BFD_RELOC_LO16
, AT
);
7577 macro_build (NULL
, "sll", "d,w,<", treg
, treg
, 8);
7578 macro_build (NULL
, "or", "d,v,t", treg
, treg
, AT
);
7582 /* FIXME: Check if this is one of the itbl macros, since they
7583 are added dynamically. */
7584 as_bad (_("Macro %s not implemented yet"), ip
->insn_mo
->name
);
7587 if (mips_opts
.noat
&& used_at
)
7588 as_bad (_("Macro used $at after \".set noat\""));
7591 /* Implement macros in mips16 mode. */
7594 mips16_macro (struct mips_cl_insn
*ip
)
7597 int xreg
, yreg
, zreg
, tmp
;
7600 const char *s
, *s2
, *s3
;
7602 mask
= ip
->insn_mo
->mask
;
7604 xreg
= (ip
->insn_opcode
>> MIPS16OP_SH_RX
) & MIPS16OP_MASK_RX
;
7605 yreg
= (ip
->insn_opcode
>> MIPS16OP_SH_RY
) & MIPS16OP_MASK_RY
;
7606 zreg
= (ip
->insn_opcode
>> MIPS16OP_SH_RZ
) & MIPS16OP_MASK_RZ
;
7608 expr1
.X_op
= O_constant
;
7609 expr1
.X_op_symbol
= NULL
;
7610 expr1
.X_add_symbol
= NULL
;
7611 expr1
.X_add_number
= 1;
7630 mips_emit_delays (TRUE
);
7631 ++mips_opts
.noreorder
;
7632 mips_any_noreorder
= 1;
7633 macro_build (NULL
, dbl
? "ddiv" : "div", "0,x,y", xreg
, yreg
);
7634 expr1
.X_add_number
= 2;
7635 macro_build (&expr1
, "bnez", "x,p", yreg
);
7636 macro_build (NULL
, "break", "6", 7);
7638 /* FIXME: The normal code checks for of -1 / -0x80000000 here,
7639 since that causes an overflow. We should do that as well,
7640 but I don't see how to do the comparisons without a temporary
7642 --mips_opts
.noreorder
;
7643 macro_build (NULL
, s
, "x", zreg
);
7662 mips_emit_delays (TRUE
);
7663 ++mips_opts
.noreorder
;
7664 mips_any_noreorder
= 1;
7665 macro_build (NULL
, s
, "0,x,y", xreg
, yreg
);
7666 expr1
.X_add_number
= 2;
7667 macro_build (&expr1
, "bnez", "x,p", yreg
);
7668 macro_build (NULL
, "break", "6", 7);
7669 --mips_opts
.noreorder
;
7670 macro_build (NULL
, s2
, "x", zreg
);
7676 macro_build (NULL
, dbl
? "dmultu" : "multu", "x,y", xreg
, yreg
);
7677 macro_build (NULL
, "mflo", "x", zreg
);
7685 if (imm_expr
.X_op
!= O_constant
)
7686 as_bad (_("Unsupported large constant"));
7687 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
7688 macro_build (&imm_expr
, dbl
? "daddiu" : "addiu", "y,x,4", yreg
, xreg
);
7692 if (imm_expr
.X_op
!= O_constant
)
7693 as_bad (_("Unsupported large constant"));
7694 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
7695 macro_build (&imm_expr
, "addiu", "x,k", xreg
);
7699 if (imm_expr
.X_op
!= O_constant
)
7700 as_bad (_("Unsupported large constant"));
7701 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
7702 macro_build (&imm_expr
, "daddiu", "y,j", yreg
);
7724 goto do_reverse_branch
;
7728 goto do_reverse_branch
;
7740 goto do_reverse_branch
;
7751 macro_build (NULL
, s
, "x,y", xreg
, yreg
);
7752 macro_build (&offset_expr
, s2
, "p");
7779 goto do_addone_branch_i
;
7784 goto do_addone_branch_i
;
7799 goto do_addone_branch_i
;
7806 if (imm_expr
.X_op
!= O_constant
)
7807 as_bad (_("Unsupported large constant"));
7808 ++imm_expr
.X_add_number
;
7811 macro_build (&imm_expr
, s
, s3
, xreg
);
7812 macro_build (&offset_expr
, s2
, "p");
7816 expr1
.X_add_number
= 0;
7817 macro_build (&expr1
, "slti", "x,8", yreg
);
7819 move_register (xreg
, yreg
);
7820 expr1
.X_add_number
= 2;
7821 macro_build (&expr1
, "bteqz", "p");
7822 macro_build (NULL
, "neg", "x,w", xreg
, xreg
);
7826 /* For consistency checking, verify that all bits are specified either
7827 by the match/mask part of the instruction definition, or by the
7830 validate_mips_insn (const struct mips_opcode
*opc
)
7832 const char *p
= opc
->args
;
7834 unsigned long used_bits
= opc
->mask
;
7836 if ((used_bits
& opc
->match
) != opc
->match
)
7838 as_bad (_("internal: bad mips opcode (mask error): %s %s"),
7839 opc
->name
, opc
->args
);
7842 #define USE_BITS(mask,shift) (used_bits |= ((mask) << (shift)))
7852 case 'A': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
7853 case 'B': USE_BITS (OP_MASK_INSMSB
, OP_SH_INSMSB
); break;
7854 case 'C': USE_BITS (OP_MASK_EXTMSBD
, OP_SH_EXTMSBD
); break;
7855 case 'D': USE_BITS (OP_MASK_RD
, OP_SH_RD
);
7856 USE_BITS (OP_MASK_SEL
, OP_SH_SEL
); break;
7857 case 'E': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
7858 case 'F': USE_BITS (OP_MASK_INSMSB
, OP_SH_INSMSB
); break;
7859 case 'G': USE_BITS (OP_MASK_EXTMSBD
, OP_SH_EXTMSBD
); break;
7860 case 'H': USE_BITS (OP_MASK_EXTMSBD
, OP_SH_EXTMSBD
); break;
7863 as_bad (_("internal: bad mips opcode (unknown extension operand type `+%c'): %s %s"),
7864 c
, opc
->name
, opc
->args
);
7868 case '<': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
7869 case '>': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
7871 case 'B': USE_BITS (OP_MASK_CODE20
, OP_SH_CODE20
); break;
7872 case 'C': USE_BITS (OP_MASK_COPZ
, OP_SH_COPZ
); break;
7873 case 'D': USE_BITS (OP_MASK_FD
, OP_SH_FD
); break;
7874 case 'E': USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
7876 case 'G': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
7877 case 'H': USE_BITS (OP_MASK_SEL
, OP_SH_SEL
); break;
7879 case 'J': USE_BITS (OP_MASK_CODE19
, OP_SH_CODE19
); break;
7880 case 'K': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
7882 case 'M': USE_BITS (OP_MASK_CCC
, OP_SH_CCC
); break;
7883 case 'N': USE_BITS (OP_MASK_BCC
, OP_SH_BCC
); break;
7884 case 'O': USE_BITS (OP_MASK_ALN
, OP_SH_ALN
); break;
7885 case 'Q': USE_BITS (OP_MASK_VSEL
, OP_SH_VSEL
);
7886 USE_BITS (OP_MASK_FT
, OP_SH_FT
); break;
7887 case 'R': USE_BITS (OP_MASK_FR
, OP_SH_FR
); break;
7888 case 'S': USE_BITS (OP_MASK_FS
, OP_SH_FS
); break;
7889 case 'T': USE_BITS (OP_MASK_FT
, OP_SH_FT
); break;
7890 case 'V': USE_BITS (OP_MASK_FS
, OP_SH_FS
); break;
7891 case 'W': USE_BITS (OP_MASK_FT
, OP_SH_FT
); break;
7892 case 'X': USE_BITS (OP_MASK_FD
, OP_SH_FD
); break;
7893 case 'Y': USE_BITS (OP_MASK_FS
, OP_SH_FS
); break;
7894 case 'Z': USE_BITS (OP_MASK_FT
, OP_SH_FT
); break;
7895 case 'a': USE_BITS (OP_MASK_TARGET
, OP_SH_TARGET
); break;
7896 case 'b': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
7897 case 'c': USE_BITS (OP_MASK_CODE
, OP_SH_CODE
); break;
7898 case 'd': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
7900 case 'h': USE_BITS (OP_MASK_PREFX
, OP_SH_PREFX
); break;
7901 case 'i': USE_BITS (OP_MASK_IMMEDIATE
, OP_SH_IMMEDIATE
); break;
7902 case 'j': USE_BITS (OP_MASK_DELTA
, OP_SH_DELTA
); break;
7903 case 'k': USE_BITS (OP_MASK_CACHE
, OP_SH_CACHE
); break;
7905 case 'o': USE_BITS (OP_MASK_DELTA
, OP_SH_DELTA
); break;
7906 case 'p': USE_BITS (OP_MASK_DELTA
, OP_SH_DELTA
); break;
7907 case 'q': USE_BITS (OP_MASK_CODE2
, OP_SH_CODE2
); break;
7908 case 'r': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
7909 case 's': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
7910 case 't': USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
7911 case 'u': USE_BITS (OP_MASK_IMMEDIATE
, OP_SH_IMMEDIATE
); break;
7912 case 'v': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
7913 case 'w': USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
7916 case 'P': USE_BITS (OP_MASK_PERFREG
, OP_SH_PERFREG
); break;
7917 case 'U': USE_BITS (OP_MASK_RD
, OP_SH_RD
);
7918 USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
7919 case 'e': USE_BITS (OP_MASK_VECBYTE
, OP_SH_VECBYTE
); break;
7920 case '%': USE_BITS (OP_MASK_VECALIGN
, OP_SH_VECALIGN
); break;
7924 as_bad (_("internal: bad mips opcode (unknown operand type `%c'): %s %s"),
7925 c
, opc
->name
, opc
->args
);
7929 if (used_bits
!= 0xffffffff)
7931 as_bad (_("internal: bad mips opcode (bits 0x%lx undefined): %s %s"),
7932 ~used_bits
& 0xffffffff, opc
->name
, opc
->args
);
7938 /* This routine assembles an instruction into its binary format. As a
7939 side effect, it sets one of the global variables imm_reloc or
7940 offset_reloc to the type of relocation to do if one of the operands
7941 is an address expression. */
7944 mips_ip (char *str
, struct mips_cl_insn
*ip
)
7949 struct mips_opcode
*insn
;
7952 unsigned int lastregno
= 0;
7953 unsigned int lastpos
= 0;
7954 unsigned int limlo
, limhi
;
7960 /* If the instruction contains a '.', we first try to match an instruction
7961 including the '.'. Then we try again without the '.'. */
7963 for (s
= str
; *s
!= '\0' && !ISSPACE (*s
); ++s
)
7966 /* If we stopped on whitespace, then replace the whitespace with null for
7967 the call to hash_find. Save the character we replaced just in case we
7968 have to re-parse the instruction. */
7975 insn
= (struct mips_opcode
*) hash_find (op_hash
, str
);
7977 /* If we didn't find the instruction in the opcode table, try again, but
7978 this time with just the instruction up to, but not including the
7982 /* Restore the character we overwrite above (if any). */
7986 /* Scan up to the first '.' or whitespace. */
7988 *s
!= '\0' && *s
!= '.' && !ISSPACE (*s
);
7992 /* If we did not find a '.', then we can quit now. */
7995 insn_error
= "unrecognized opcode";
7999 /* Lookup the instruction in the hash table. */
8001 if ((insn
= (struct mips_opcode
*) hash_find (op_hash
, str
)) == NULL
)
8003 insn_error
= "unrecognized opcode";
8013 assert (strcmp (insn
->name
, str
) == 0);
8015 if (OPCODE_IS_MEMBER (insn
,
8017 | (file_ase_mips16
? INSN_MIPS16
: 0)
8018 | (mips_opts
.ase_mdmx
? INSN_MDMX
: 0)
8019 | (mips_opts
.ase_mips3d
? INSN_MIPS3D
: 0)),
8025 if (insn
->pinfo
!= INSN_MACRO
)
8027 if (mips_opts
.arch
== CPU_R4650
&& (insn
->pinfo
& FP_D
) != 0)
8033 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
]
8034 && strcmp (insn
->name
, insn
[1].name
) == 0)
8043 static char buf
[100];
8045 _("opcode not supported on this processor: %s (%s)"),
8046 mips_cpu_info_from_arch (mips_opts
.arch
)->name
,
8047 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
8057 ip
->insn_opcode
= insn
->match
;
8059 for (args
= insn
->args
;; ++args
)
8063 s
+= strspn (s
, " \t");
8067 case '\0': /* end of args */
8080 ip
->insn_opcode
|= lastregno
<< OP_SH_RS
;
8084 ip
->insn_opcode
|= lastregno
<< OP_SH_RT
;
8088 ip
->insn_opcode
|= lastregno
<< OP_SH_FT
;
8092 ip
->insn_opcode
|= lastregno
<< OP_SH_FS
;
8098 /* Handle optional base register.
8099 Either the base register is omitted or
8100 we must have a left paren. */
8101 /* This is dependent on the next operand specifier
8102 is a base register specification. */
8103 assert (args
[1] == 'b' || args
[1] == '5'
8104 || args
[1] == '-' || args
[1] == '4');
8108 case ')': /* these must match exactly */
8115 case '+': /* Opcode extension character. */
8118 case 'A': /* ins/ext position, becomes LSB. */
8127 my_getExpression (&imm_expr
, s
);
8128 check_absolute_expr (ip
, &imm_expr
);
8129 if ((unsigned long) imm_expr
.X_add_number
< limlo
8130 || (unsigned long) imm_expr
.X_add_number
> limhi
)
8132 as_bad (_("Improper position (%lu)"),
8133 (unsigned long) imm_expr
.X_add_number
);
8134 imm_expr
.X_add_number
= limlo
;
8136 lastpos
= imm_expr
.X_add_number
;
8137 ip
->insn_opcode
|= (imm_expr
.X_add_number
8138 & OP_MASK_SHAMT
) << OP_SH_SHAMT
;
8139 imm_expr
.X_op
= O_absent
;
8143 case 'B': /* ins size, becomes MSB. */
8152 my_getExpression (&imm_expr
, s
);
8153 check_absolute_expr (ip
, &imm_expr
);
8154 /* Check for negative input so that small negative numbers
8155 will not succeed incorrectly. The checks against
8156 (pos+size) transitively check "size" itself,
8157 assuming that "pos" is reasonable. */
8158 if ((long) imm_expr
.X_add_number
< 0
8159 || ((unsigned long) imm_expr
.X_add_number
8161 || ((unsigned long) imm_expr
.X_add_number
8164 as_bad (_("Improper insert size (%lu, position %lu)"),
8165 (unsigned long) imm_expr
.X_add_number
,
8166 (unsigned long) lastpos
);
8167 imm_expr
.X_add_number
= limlo
- lastpos
;
8169 ip
->insn_opcode
|= ((lastpos
+ imm_expr
.X_add_number
- 1)
8170 & OP_MASK_INSMSB
) << OP_SH_INSMSB
;
8171 imm_expr
.X_op
= O_absent
;
8175 case 'C': /* ext size, becomes MSBD. */
8188 my_getExpression (&imm_expr
, s
);
8189 check_absolute_expr (ip
, &imm_expr
);
8190 /* Check for negative input so that small negative numbers
8191 will not succeed incorrectly. The checks against
8192 (pos+size) transitively check "size" itself,
8193 assuming that "pos" is reasonable. */
8194 if ((long) imm_expr
.X_add_number
< 0
8195 || ((unsigned long) imm_expr
.X_add_number
8197 || ((unsigned long) imm_expr
.X_add_number
8200 as_bad (_("Improper extract size (%lu, position %lu)"),
8201 (unsigned long) imm_expr
.X_add_number
,
8202 (unsigned long) lastpos
);
8203 imm_expr
.X_add_number
= limlo
- lastpos
;
8205 ip
->insn_opcode
|= ((imm_expr
.X_add_number
- 1)
8206 & OP_MASK_EXTMSBD
) << OP_SH_EXTMSBD
;
8207 imm_expr
.X_op
= O_absent
;
8212 /* +D is for disassembly only; never match. */
8216 /* "+I" is like "I", except that imm2_expr is used. */
8217 my_getExpression (&imm2_expr
, s
);
8218 if (imm2_expr
.X_op
!= O_big
8219 && imm2_expr
.X_op
!= O_constant
)
8220 insn_error
= _("absolute expression required");
8221 normalize_constant_expr (&imm2_expr
);
8226 as_bad (_("internal: bad mips opcode (unknown extension operand type `+%c'): %s %s"),
8227 *args
, insn
->name
, insn
->args
);
8228 /* Further processing is fruitless. */
8233 case '<': /* must be at least one digit */
8235 * According to the manual, if the shift amount is greater
8236 * than 31 or less than 0, then the shift amount should be
8237 * mod 32. In reality the mips assembler issues an error.
8238 * We issue a warning and mask out all but the low 5 bits.
8240 my_getExpression (&imm_expr
, s
);
8241 check_absolute_expr (ip
, &imm_expr
);
8242 if ((unsigned long) imm_expr
.X_add_number
> 31)
8244 as_warn (_("Improper shift amount (%lu)"),
8245 (unsigned long) imm_expr
.X_add_number
);
8246 imm_expr
.X_add_number
&= OP_MASK_SHAMT
;
8248 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_SHAMT
;
8249 imm_expr
.X_op
= O_absent
;
8253 case '>': /* shift amount minus 32 */
8254 my_getExpression (&imm_expr
, s
);
8255 check_absolute_expr (ip
, &imm_expr
);
8256 if ((unsigned long) imm_expr
.X_add_number
< 32
8257 || (unsigned long) imm_expr
.X_add_number
> 63)
8259 ip
->insn_opcode
|= (imm_expr
.X_add_number
- 32) << OP_SH_SHAMT
;
8260 imm_expr
.X_op
= O_absent
;
8264 case 'k': /* cache code */
8265 case 'h': /* prefx code */
8266 my_getExpression (&imm_expr
, s
);
8267 check_absolute_expr (ip
, &imm_expr
);
8268 if ((unsigned long) imm_expr
.X_add_number
> 31)
8270 as_warn (_("Invalid value for `%s' (%lu)"),
8272 (unsigned long) imm_expr
.X_add_number
);
8273 imm_expr
.X_add_number
&= 0x1f;
8276 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_CACHE
;
8278 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_PREFX
;
8279 imm_expr
.X_op
= O_absent
;
8283 case 'c': /* break code */
8284 my_getExpression (&imm_expr
, s
);
8285 check_absolute_expr (ip
, &imm_expr
);
8286 if ((unsigned long) imm_expr
.X_add_number
> 1023)
8288 as_warn (_("Illegal break code (%lu)"),
8289 (unsigned long) imm_expr
.X_add_number
);
8290 imm_expr
.X_add_number
&= OP_MASK_CODE
;
8292 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_CODE
;
8293 imm_expr
.X_op
= O_absent
;
8297 case 'q': /* lower break code */
8298 my_getExpression (&imm_expr
, s
);
8299 check_absolute_expr (ip
, &imm_expr
);
8300 if ((unsigned long) imm_expr
.X_add_number
> 1023)
8302 as_warn (_("Illegal lower break code (%lu)"),
8303 (unsigned long) imm_expr
.X_add_number
);
8304 imm_expr
.X_add_number
&= OP_MASK_CODE2
;
8306 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_CODE2
;
8307 imm_expr
.X_op
= O_absent
;
8311 case 'B': /* 20-bit syscall/break code. */
8312 my_getExpression (&imm_expr
, s
);
8313 check_absolute_expr (ip
, &imm_expr
);
8314 if ((unsigned long) imm_expr
.X_add_number
> OP_MASK_CODE20
)
8315 as_warn (_("Illegal 20-bit code (%lu)"),
8316 (unsigned long) imm_expr
.X_add_number
);
8317 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_CODE20
;
8318 imm_expr
.X_op
= O_absent
;
8322 case 'C': /* Coprocessor code */
8323 my_getExpression (&imm_expr
, s
);
8324 check_absolute_expr (ip
, &imm_expr
);
8325 if ((unsigned long) imm_expr
.X_add_number
>= (1 << 25))
8327 as_warn (_("Coproccesor code > 25 bits (%lu)"),
8328 (unsigned long) imm_expr
.X_add_number
);
8329 imm_expr
.X_add_number
&= ((1 << 25) - 1);
8331 ip
->insn_opcode
|= imm_expr
.X_add_number
;
8332 imm_expr
.X_op
= O_absent
;
8336 case 'J': /* 19-bit wait code. */
8337 my_getExpression (&imm_expr
, s
);
8338 check_absolute_expr (ip
, &imm_expr
);
8339 if ((unsigned long) imm_expr
.X_add_number
> OP_MASK_CODE19
)
8340 as_warn (_("Illegal 19-bit code (%lu)"),
8341 (unsigned long) imm_expr
.X_add_number
);
8342 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_CODE19
;
8343 imm_expr
.X_op
= O_absent
;
8347 case 'P': /* Performance register */
8348 my_getExpression (&imm_expr
, s
);
8349 check_absolute_expr (ip
, &imm_expr
);
8350 if (imm_expr
.X_add_number
!= 0 && imm_expr
.X_add_number
!= 1)
8352 as_warn (_("Invalid performance register (%lu)"),
8353 (unsigned long) imm_expr
.X_add_number
);
8354 imm_expr
.X_add_number
&= OP_MASK_PERFREG
;
8356 ip
->insn_opcode
|= (imm_expr
.X_add_number
<< OP_SH_PERFREG
);
8357 imm_expr
.X_op
= O_absent
;
8361 case 'b': /* base register */
8362 case 'd': /* destination register */
8363 case 's': /* source register */
8364 case 't': /* target register */
8365 case 'r': /* both target and source */
8366 case 'v': /* both dest and source */
8367 case 'w': /* both dest and target */
8368 case 'E': /* coprocessor target register */
8369 case 'G': /* coprocessor destination register */
8370 case 'K': /* 'rdhwr' destination register */
8371 case 'x': /* ignore register name */
8372 case 'z': /* must be zero register */
8373 case 'U': /* destination register (clo/clz). */
8388 while (ISDIGIT (*s
));
8390 as_bad (_("Invalid register number (%d)"), regno
);
8392 else if (*args
== 'E' || *args
== 'G' || *args
== 'K')
8396 if (s
[1] == 'r' && s
[2] == 'a')
8401 else if (s
[1] == 'f' && s
[2] == 'p')
8406 else if (s
[1] == 's' && s
[2] == 'p')
8411 else if (s
[1] == 'g' && s
[2] == 'p')
8416 else if (s
[1] == 'a' && s
[2] == 't')
8421 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '0')
8426 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '1')
8431 else if (s
[1] == 'z' && s
[2] == 'e' && s
[3] == 'r' && s
[4] == 'o')
8436 else if (itbl_have_entries
)
8441 p
= s
+ 1; /* advance past '$' */
8442 n
= itbl_get_field (&p
); /* n is name */
8444 /* See if this is a register defined in an
8446 if (itbl_get_reg_val (n
, &r
))
8448 /* Get_field advances to the start of
8449 the next field, so we need to back
8450 rack to the end of the last field. */
8454 s
= strchr (s
, '\0');
8468 as_warn (_("Used $at without \".set noat\""));
8474 if (c
== 'r' || c
== 'v' || c
== 'w')
8481 /* 'z' only matches $0. */
8482 if (c
== 'z' && regno
!= 0)
8485 /* Now that we have assembled one operand, we use the args string
8486 * to figure out where it goes in the instruction. */
8493 ip
->insn_opcode
|= regno
<< OP_SH_RS
;
8498 ip
->insn_opcode
|= regno
<< OP_SH_RD
;
8501 ip
->insn_opcode
|= regno
<< OP_SH_RD
;
8502 ip
->insn_opcode
|= regno
<< OP_SH_RT
;
8507 ip
->insn_opcode
|= regno
<< OP_SH_RT
;
8510 /* This case exists because on the r3000 trunc
8511 expands into a macro which requires a gp
8512 register. On the r6000 or r4000 it is
8513 assembled into a single instruction which
8514 ignores the register. Thus the insn version
8515 is MIPS_ISA2 and uses 'x', and the macro
8516 version is MIPS_ISA1 and uses 't'. */
8519 /* This case is for the div instruction, which
8520 acts differently if the destination argument
8521 is $0. This only matches $0, and is checked
8522 outside the switch. */
8525 /* Itbl operand; not yet implemented. FIXME ?? */
8527 /* What about all other operands like 'i', which
8528 can be specified in the opcode table? */
8538 ip
->insn_opcode
|= lastregno
<< OP_SH_RS
;
8541 ip
->insn_opcode
|= lastregno
<< OP_SH_RT
;
8546 case 'O': /* MDMX alignment immediate constant. */
8547 my_getExpression (&imm_expr
, s
);
8548 check_absolute_expr (ip
, &imm_expr
);
8549 if ((unsigned long) imm_expr
.X_add_number
> OP_MASK_ALN
)
8551 as_warn ("Improper align amount (%ld), using low bits",
8552 (long) imm_expr
.X_add_number
);
8553 imm_expr
.X_add_number
&= OP_MASK_ALN
;
8555 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_ALN
;
8556 imm_expr
.X_op
= O_absent
;
8560 case 'Q': /* MDMX vector, element sel, or const. */
8563 /* MDMX Immediate. */
8564 my_getExpression (&imm_expr
, s
);
8565 check_absolute_expr (ip
, &imm_expr
);
8566 if ((unsigned long) imm_expr
.X_add_number
> OP_MASK_FT
)
8568 as_warn (_("Invalid MDMX Immediate (%ld)"),
8569 (long) imm_expr
.X_add_number
);
8570 imm_expr
.X_add_number
&= OP_MASK_FT
;
8572 imm_expr
.X_add_number
&= OP_MASK_FT
;
8573 if (ip
->insn_opcode
& (OP_MASK_VSEL
<< OP_SH_VSEL
))
8574 ip
->insn_opcode
|= MDMX_FMTSEL_IMM_QH
<< OP_SH_VSEL
;
8576 ip
->insn_opcode
|= MDMX_FMTSEL_IMM_OB
<< OP_SH_VSEL
;
8577 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_FT
;
8578 imm_expr
.X_op
= O_absent
;
8582 /* Not MDMX Immediate. Fall through. */
8583 case 'X': /* MDMX destination register. */
8584 case 'Y': /* MDMX source register. */
8585 case 'Z': /* MDMX target register. */
8587 case 'D': /* floating point destination register */
8588 case 'S': /* floating point source register */
8589 case 'T': /* floating point target register */
8590 case 'R': /* floating point source register */
8594 /* Accept $fN for FP and MDMX register numbers, and in
8595 addition accept $vN for MDMX register numbers. */
8596 if ((s
[0] == '$' && s
[1] == 'f' && ISDIGIT (s
[2]))
8597 || (is_mdmx
!= 0 && s
[0] == '$' && s
[1] == 'v'
8608 while (ISDIGIT (*s
));
8611 as_bad (_("Invalid float register number (%d)"), regno
);
8613 if ((regno
& 1) != 0
8615 && ! (strcmp (str
, "mtc1") == 0
8616 || strcmp (str
, "mfc1") == 0
8617 || strcmp (str
, "lwc1") == 0
8618 || strcmp (str
, "swc1") == 0
8619 || strcmp (str
, "l.s") == 0
8620 || strcmp (str
, "s.s") == 0))
8621 as_warn (_("Float register should be even, was %d"),
8629 if (c
== 'V' || c
== 'W')
8640 ip
->insn_opcode
|= regno
<< OP_SH_FD
;
8645 ip
->insn_opcode
|= regno
<< OP_SH_FS
;
8648 /* This is like 'Z', but also needs to fix the MDMX
8649 vector/scalar select bits. Note that the
8650 scalar immediate case is handled above. */
8653 int is_qh
= (ip
->insn_opcode
& (1 << OP_SH_VSEL
));
8654 int max_el
= (is_qh
? 3 : 7);
8656 my_getExpression(&imm_expr
, s
);
8657 check_absolute_expr (ip
, &imm_expr
);
8659 if (imm_expr
.X_add_number
> max_el
)
8660 as_bad(_("Bad element selector %ld"),
8661 (long) imm_expr
.X_add_number
);
8662 imm_expr
.X_add_number
&= max_el
;
8663 ip
->insn_opcode
|= (imm_expr
.X_add_number
8666 imm_expr
.X_op
= O_absent
;
8668 as_warn(_("Expecting ']' found '%s'"), s
);
8674 if (ip
->insn_opcode
& (OP_MASK_VSEL
<< OP_SH_VSEL
))
8675 ip
->insn_opcode
|= (MDMX_FMTSEL_VEC_QH
8678 ip
->insn_opcode
|= (MDMX_FMTSEL_VEC_OB
<<
8685 ip
->insn_opcode
|= regno
<< OP_SH_FT
;
8688 ip
->insn_opcode
|= regno
<< OP_SH_FR
;
8698 ip
->insn_opcode
|= lastregno
<< OP_SH_FS
;
8701 ip
->insn_opcode
|= lastregno
<< OP_SH_FT
;
8707 my_getExpression (&imm_expr
, s
);
8708 if (imm_expr
.X_op
!= O_big
8709 && imm_expr
.X_op
!= O_constant
)
8710 insn_error
= _("absolute expression required");
8711 normalize_constant_expr (&imm_expr
);
8716 my_getExpression (&offset_expr
, s
);
8717 *imm_reloc
= BFD_RELOC_32
;
8730 unsigned char temp
[8];
8732 unsigned int length
;
8737 /* These only appear as the last operand in an
8738 instruction, and every instruction that accepts
8739 them in any variant accepts them in all variants.
8740 This means we don't have to worry about backing out
8741 any changes if the instruction does not match.
8743 The difference between them is the size of the
8744 floating point constant and where it goes. For 'F'
8745 and 'L' the constant is 64 bits; for 'f' and 'l' it
8746 is 32 bits. Where the constant is placed is based
8747 on how the MIPS assembler does things:
8750 f -- immediate value
8753 The .lit4 and .lit8 sections are only used if
8754 permitted by the -G argument.
8756 The code below needs to know whether the target register
8757 is 32 or 64 bits wide. It relies on the fact 'f' and
8758 'F' are used with GPR-based instructions and 'l' and
8759 'L' are used with FPR-based instructions. */
8761 f64
= *args
== 'F' || *args
== 'L';
8762 using_gprs
= *args
== 'F' || *args
== 'f';
8764 save_in
= input_line_pointer
;
8765 input_line_pointer
= s
;
8766 err
= md_atof (f64
? 'd' : 'f', (char *) temp
, &len
);
8768 s
= input_line_pointer
;
8769 input_line_pointer
= save_in
;
8770 if (err
!= NULL
&& *err
!= '\0')
8772 as_bad (_("Bad floating point constant: %s"), err
);
8773 memset (temp
, '\0', sizeof temp
);
8774 length
= f64
? 8 : 4;
8777 assert (length
== (unsigned) (f64
? 8 : 4));
8781 && (g_switch_value
< 4
8782 || (temp
[0] == 0 && temp
[1] == 0)
8783 || (temp
[2] == 0 && temp
[3] == 0))))
8785 imm_expr
.X_op
= O_constant
;
8786 if (! target_big_endian
)
8787 imm_expr
.X_add_number
= bfd_getl32 (temp
);
8789 imm_expr
.X_add_number
= bfd_getb32 (temp
);
8792 && ! mips_disable_float_construction
8793 /* Constants can only be constructed in GPRs and
8794 copied to FPRs if the GPRs are at least as wide
8795 as the FPRs. Force the constant into memory if
8796 we are using 64-bit FPRs but the GPRs are only
8799 || ! (HAVE_64BIT_FPRS
&& HAVE_32BIT_GPRS
))
8800 && ((temp
[0] == 0 && temp
[1] == 0)
8801 || (temp
[2] == 0 && temp
[3] == 0))
8802 && ((temp
[4] == 0 && temp
[5] == 0)
8803 || (temp
[6] == 0 && temp
[7] == 0)))
8805 /* The value is simple enough to load with a couple of
8806 instructions. If using 32-bit registers, set
8807 imm_expr to the high order 32 bits and offset_expr to
8808 the low order 32 bits. Otherwise, set imm_expr to
8809 the entire 64 bit constant. */
8810 if (using_gprs
? HAVE_32BIT_GPRS
: HAVE_32BIT_FPRS
)
8812 imm_expr
.X_op
= O_constant
;
8813 offset_expr
.X_op
= O_constant
;
8814 if (! target_big_endian
)
8816 imm_expr
.X_add_number
= bfd_getl32 (temp
+ 4);
8817 offset_expr
.X_add_number
= bfd_getl32 (temp
);
8821 imm_expr
.X_add_number
= bfd_getb32 (temp
);
8822 offset_expr
.X_add_number
= bfd_getb32 (temp
+ 4);
8824 if (offset_expr
.X_add_number
== 0)
8825 offset_expr
.X_op
= O_absent
;
8827 else if (sizeof (imm_expr
.X_add_number
) > 4)
8829 imm_expr
.X_op
= O_constant
;
8830 if (! target_big_endian
)
8831 imm_expr
.X_add_number
= bfd_getl64 (temp
);
8833 imm_expr
.X_add_number
= bfd_getb64 (temp
);
8837 imm_expr
.X_op
= O_big
;
8838 imm_expr
.X_add_number
= 4;
8839 if (! target_big_endian
)
8841 generic_bignum
[0] = bfd_getl16 (temp
);
8842 generic_bignum
[1] = bfd_getl16 (temp
+ 2);
8843 generic_bignum
[2] = bfd_getl16 (temp
+ 4);
8844 generic_bignum
[3] = bfd_getl16 (temp
+ 6);
8848 generic_bignum
[0] = bfd_getb16 (temp
+ 6);
8849 generic_bignum
[1] = bfd_getb16 (temp
+ 4);
8850 generic_bignum
[2] = bfd_getb16 (temp
+ 2);
8851 generic_bignum
[3] = bfd_getb16 (temp
);
8857 const char *newname
;
8860 /* Switch to the right section. */
8862 subseg
= now_subseg
;
8865 default: /* unused default case avoids warnings. */
8867 newname
= RDATA_SECTION_NAME
;
8868 if (g_switch_value
>= 8)
8872 newname
= RDATA_SECTION_NAME
;
8875 assert (g_switch_value
>= 4);
8879 new_seg
= subseg_new (newname
, (subsegT
) 0);
8880 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
8881 bfd_set_section_flags (stdoutput
, new_seg
,
8886 frag_align (*args
== 'l' ? 2 : 3, 0, 0);
8887 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
8888 && strcmp (TARGET_OS
, "elf") != 0)
8889 record_alignment (new_seg
, 4);
8891 record_alignment (new_seg
, *args
== 'l' ? 2 : 3);
8893 as_bad (_("Can't use floating point insn in this section"));
8895 /* Set the argument to the current address in the
8897 offset_expr
.X_op
= O_symbol
;
8898 offset_expr
.X_add_symbol
=
8899 symbol_new ("L0\001", now_seg
,
8900 (valueT
) frag_now_fix (), frag_now
);
8901 offset_expr
.X_add_number
= 0;
8903 /* Put the floating point number into the section. */
8904 p
= frag_more ((int) length
);
8905 memcpy (p
, temp
, length
);
8907 /* Switch back to the original section. */
8908 subseg_set (seg
, subseg
);
8913 case 'i': /* 16 bit unsigned immediate */
8914 case 'j': /* 16 bit signed immediate */
8915 *imm_reloc
= BFD_RELOC_LO16
;
8916 if (my_getSmallExpression (&imm_expr
, imm_reloc
, s
) == 0)
8919 offsetT minval
, maxval
;
8921 more
= (insn
+ 1 < &mips_opcodes
[NUMOPCODES
]
8922 && strcmp (insn
->name
, insn
[1].name
) == 0);
8924 /* If the expression was written as an unsigned number,
8925 only treat it as signed if there are no more
8929 && sizeof (imm_expr
.X_add_number
) <= 4
8930 && imm_expr
.X_op
== O_constant
8931 && imm_expr
.X_add_number
< 0
8932 && imm_expr
.X_unsigned
8936 /* For compatibility with older assemblers, we accept
8937 0x8000-0xffff as signed 16-bit numbers when only
8938 signed numbers are allowed. */
8940 minval
= 0, maxval
= 0xffff;
8942 minval
= -0x8000, maxval
= 0x7fff;
8944 minval
= -0x8000, maxval
= 0xffff;
8946 if (imm_expr
.X_op
!= O_constant
8947 || imm_expr
.X_add_number
< minval
8948 || imm_expr
.X_add_number
> maxval
)
8952 if (imm_expr
.X_op
== O_constant
8953 || imm_expr
.X_op
== O_big
)
8954 as_bad (_("expression out of range"));
8960 case 'o': /* 16 bit offset */
8961 /* Check whether there is only a single bracketed expression
8962 left. If so, it must be the base register and the
8963 constant must be zero. */
8964 if (*s
== '(' && strchr (s
+ 1, '(') == 0)
8966 offset_expr
.X_op
= O_constant
;
8967 offset_expr
.X_add_number
= 0;
8971 /* If this value won't fit into a 16 bit offset, then go
8972 find a macro that will generate the 32 bit offset
8974 if (my_getSmallExpression (&offset_expr
, offset_reloc
, s
) == 0
8975 && (offset_expr
.X_op
!= O_constant
8976 || offset_expr
.X_add_number
>= 0x8000
8977 || offset_expr
.X_add_number
< -0x8000))
8983 case 'p': /* pc relative offset */
8984 *offset_reloc
= BFD_RELOC_16_PCREL_S2
;
8985 my_getExpression (&offset_expr
, s
);
8989 case 'u': /* upper 16 bits */
8990 if (my_getSmallExpression (&imm_expr
, imm_reloc
, s
) == 0
8991 && imm_expr
.X_op
== O_constant
8992 && (imm_expr
.X_add_number
< 0
8993 || imm_expr
.X_add_number
>= 0x10000))
8994 as_bad (_("lui expression not in range 0..65535"));
8998 case 'a': /* 26 bit address */
8999 my_getExpression (&offset_expr
, s
);
9001 *offset_reloc
= BFD_RELOC_MIPS_JMP
;
9004 case 'N': /* 3 bit branch condition code */
9005 case 'M': /* 3 bit compare condition code */
9006 if (strncmp (s
, "$fcc", 4) != 0)
9016 while (ISDIGIT (*s
));
9018 as_bad (_("Invalid condition code register $fcc%d"), regno
);
9019 if ((strcmp(str
+ strlen(str
) - 3, ".ps") == 0
9020 || strcmp(str
+ strlen(str
) - 5, "any2f") == 0
9021 || strcmp(str
+ strlen(str
) - 5, "any2t") == 0)
9022 && (regno
& 1) != 0)
9023 as_warn(_("Condition code register should be even for %s, was %d"),
9025 if ((strcmp(str
+ strlen(str
) - 5, "any4f") == 0
9026 || strcmp(str
+ strlen(str
) - 5, "any4t") == 0)
9027 && (regno
& 3) != 0)
9028 as_warn(_("Condition code register should be 0 or 4 for %s, was %d"),
9031 ip
->insn_opcode
|= regno
<< OP_SH_BCC
;
9033 ip
->insn_opcode
|= regno
<< OP_SH_CCC
;
9037 if (s
[0] == '0' && (s
[1] == 'x' || s
[1] == 'X'))
9048 while (ISDIGIT (*s
));
9051 c
= 8; /* Invalid sel value. */
9054 as_bad (_("invalid coprocessor sub-selection value (0-7)"));
9055 ip
->insn_opcode
|= c
;
9059 /* Must be at least one digit. */
9060 my_getExpression (&imm_expr
, s
);
9061 check_absolute_expr (ip
, &imm_expr
);
9063 if ((unsigned long) imm_expr
.X_add_number
9064 > (unsigned long) OP_MASK_VECBYTE
)
9066 as_bad (_("bad byte vector index (%ld)"),
9067 (long) imm_expr
.X_add_number
);
9068 imm_expr
.X_add_number
= 0;
9071 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_VECBYTE
;
9072 imm_expr
.X_op
= O_absent
;
9077 my_getExpression (&imm_expr
, s
);
9078 check_absolute_expr (ip
, &imm_expr
);
9080 if ((unsigned long) imm_expr
.X_add_number
9081 > (unsigned long) OP_MASK_VECALIGN
)
9083 as_bad (_("bad byte vector index (%ld)"),
9084 (long) imm_expr
.X_add_number
);
9085 imm_expr
.X_add_number
= 0;
9088 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_VECALIGN
;
9089 imm_expr
.X_op
= O_absent
;
9094 as_bad (_("bad char = '%c'\n"), *args
);
9099 /* Args don't match. */
9100 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
9101 !strcmp (insn
->name
, insn
[1].name
))
9105 insn_error
= _("illegal operands");
9110 insn_error
= _("illegal operands");
9115 /* This routine assembles an instruction into its binary format when
9116 assembling for the mips16. As a side effect, it sets one of the
9117 global variables imm_reloc or offset_reloc to the type of
9118 relocation to do if one of the operands is an address expression.
9119 It also sets mips16_small and mips16_ext if the user explicitly
9120 requested a small or extended instruction. */
9123 mips16_ip (char *str
, struct mips_cl_insn
*ip
)
9127 struct mips_opcode
*insn
;
9130 unsigned int lastregno
= 0;
9136 mips16_small
= FALSE
;
9139 for (s
= str
; ISLOWER (*s
); ++s
)
9151 if (s
[1] == 't' && s
[2] == ' ')
9154 mips16_small
= TRUE
;
9158 else if (s
[1] == 'e' && s
[2] == ' ')
9167 insn_error
= _("unknown opcode");
9171 if (mips_opts
.noautoextend
&& ! mips16_ext
)
9172 mips16_small
= TRUE
;
9174 if ((insn
= (struct mips_opcode
*) hash_find (mips16_op_hash
, str
)) == NULL
)
9176 insn_error
= _("unrecognized opcode");
9183 assert (strcmp (insn
->name
, str
) == 0);
9186 ip
->insn_opcode
= insn
->match
;
9187 ip
->use_extend
= FALSE
;
9188 imm_expr
.X_op
= O_absent
;
9189 imm_reloc
[0] = BFD_RELOC_UNUSED
;
9190 imm_reloc
[1] = BFD_RELOC_UNUSED
;
9191 imm_reloc
[2] = BFD_RELOC_UNUSED
;
9192 imm2_expr
.X_op
= O_absent
;
9193 offset_expr
.X_op
= O_absent
;
9194 offset_reloc
[0] = BFD_RELOC_UNUSED
;
9195 offset_reloc
[1] = BFD_RELOC_UNUSED
;
9196 offset_reloc
[2] = BFD_RELOC_UNUSED
;
9197 for (args
= insn
->args
; 1; ++args
)
9204 /* In this switch statement we call break if we did not find
9205 a match, continue if we did find a match, or return if we
9214 /* Stuff the immediate value in now, if we can. */
9215 if (imm_expr
.X_op
== O_constant
9216 && *imm_reloc
> BFD_RELOC_UNUSED
9217 && insn
->pinfo
!= INSN_MACRO
)
9221 switch (*offset_reloc
)
9223 case BFD_RELOC_MIPS16_HI16_S
:
9224 tmp
= (imm_expr
.X_add_number
+ 0x8000) >> 16;
9227 case BFD_RELOC_MIPS16_HI16
:
9228 tmp
= imm_expr
.X_add_number
>> 16;
9231 case BFD_RELOC_MIPS16_LO16
:
9232 tmp
= ((imm_expr
.X_add_number
+ 0x8000) & 0xffff)
9236 case BFD_RELOC_UNUSED
:
9237 tmp
= imm_expr
.X_add_number
;
9243 *offset_reloc
= BFD_RELOC_UNUSED
;
9245 mips16_immed (NULL
, 0, *imm_reloc
- BFD_RELOC_UNUSED
,
9246 tmp
, TRUE
, mips16_small
,
9247 mips16_ext
, &ip
->insn_opcode
,
9248 &ip
->use_extend
, &ip
->extend
);
9249 imm_expr
.X_op
= O_absent
;
9250 *imm_reloc
= BFD_RELOC_UNUSED
;
9264 ip
->insn_opcode
|= lastregno
<< MIPS16OP_SH_RX
;
9267 ip
->insn_opcode
|= lastregno
<< MIPS16OP_SH_RY
;
9283 ip
->insn_opcode
|= lastregno
<< MIPS16OP_SH_RX
;
9285 ip
->insn_opcode
|= lastregno
<< MIPS16OP_SH_RY
;
9312 while (ISDIGIT (*s
));
9315 as_bad (_("invalid register number (%d)"), regno
);
9321 if (s
[1] == 'r' && s
[2] == 'a')
9326 else if (s
[1] == 'f' && s
[2] == 'p')
9331 else if (s
[1] == 's' && s
[2] == 'p')
9336 else if (s
[1] == 'g' && s
[2] == 'p')
9341 else if (s
[1] == 'a' && s
[2] == 't')
9346 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '0')
9351 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '1')
9356 else if (s
[1] == 'z' && s
[2] == 'e' && s
[3] == 'r' && s
[4] == 'o')
9369 if (c
== 'v' || c
== 'w')
9371 regno
= mips16_to_32_reg_map
[lastregno
];
9385 regno
= mips32_to_16_reg_map
[regno
];
9390 regno
= ILLEGAL_REG
;
9395 regno
= ILLEGAL_REG
;
9400 regno
= ILLEGAL_REG
;
9405 if (regno
== AT
&& ! mips_opts
.noat
)
9406 as_warn (_("used $at without \".set noat\""));
9413 if (regno
== ILLEGAL_REG
)
9420 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_RX
;
9424 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_RY
;
9427 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_RZ
;
9430 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_MOVE32Z
;
9436 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_REGR32
;
9439 regno
= ((regno
& 7) << 2) | ((regno
& 0x18) >> 3);
9440 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_REG32R
;
9450 if (strncmp (s
, "$pc", 3) == 0)
9467 i
= my_getSmallExpression (&imm_expr
, imm_reloc
, s
);
9470 if (imm_expr
.X_op
!= O_constant
)
9473 ip
->use_extend
= TRUE
;
9478 /* We need to relax this instruction. */
9479 *offset_reloc
= *imm_reloc
;
9480 *imm_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
9485 *imm_reloc
= BFD_RELOC_UNUSED
;
9493 my_getExpression (&imm_expr
, s
);
9494 if (imm_expr
.X_op
== O_register
)
9496 /* What we thought was an expression turned out to
9499 if (s
[0] == '(' && args
[1] == '(')
9501 /* It looks like the expression was omitted
9502 before a register indirection, which means
9503 that the expression is implicitly zero. We
9504 still set up imm_expr, so that we handle
9505 explicit extensions correctly. */
9506 imm_expr
.X_op
= O_constant
;
9507 imm_expr
.X_add_number
= 0;
9508 *imm_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
9515 /* We need to relax this instruction. */
9516 *imm_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
9525 /* We use offset_reloc rather than imm_reloc for the PC
9526 relative operands. This lets macros with both
9527 immediate and address operands work correctly. */
9528 my_getExpression (&offset_expr
, s
);
9530 if (offset_expr
.X_op
== O_register
)
9533 /* We need to relax this instruction. */
9534 *offset_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
9538 case '6': /* break code */
9539 my_getExpression (&imm_expr
, s
);
9540 check_absolute_expr (ip
, &imm_expr
);
9541 if ((unsigned long) imm_expr
.X_add_number
> 63)
9543 as_warn (_("Invalid value for `%s' (%lu)"),
9545 (unsigned long) imm_expr
.X_add_number
);
9546 imm_expr
.X_add_number
&= 0x3f;
9548 ip
->insn_opcode
|= imm_expr
.X_add_number
<< MIPS16OP_SH_IMM6
;
9549 imm_expr
.X_op
= O_absent
;
9553 case 'a': /* 26 bit address */
9554 my_getExpression (&offset_expr
, s
);
9556 *offset_reloc
= BFD_RELOC_MIPS16_JMP
;
9557 ip
->insn_opcode
<<= 16;
9560 case 'l': /* register list for entry macro */
9561 case 'L': /* register list for exit macro */
9571 int freg
, reg1
, reg2
;
9573 while (*s
== ' ' || *s
== ',')
9577 as_bad (_("can't parse register list"));
9589 while (ISDIGIT (*s
))
9611 as_bad (_("invalid register list"));
9616 while (ISDIGIT (*s
))
9623 if (freg
&& reg1
== 0 && reg2
== 0 && c
== 'L')
9628 else if (freg
&& reg1
== 0 && reg2
== 1 && c
== 'L')
9633 else if (reg1
== 4 && reg2
>= 4 && reg2
<= 7 && c
!= 'L')
9634 mask
|= (reg2
- 3) << 3;
9635 else if (reg1
== 16 && reg2
>= 16 && reg2
<= 17)
9636 mask
|= (reg2
- 15) << 1;
9637 else if (reg1
== RA
&& reg2
== RA
)
9641 as_bad (_("invalid register list"));
9645 /* The mask is filled in in the opcode table for the
9646 benefit of the disassembler. We remove it before
9647 applying the actual mask. */
9648 ip
->insn_opcode
&= ~ ((7 << 3) << MIPS16OP_SH_IMM6
);
9649 ip
->insn_opcode
|= mask
<< MIPS16OP_SH_IMM6
;
9653 case 'e': /* extend code */
9654 my_getExpression (&imm_expr
, s
);
9655 check_absolute_expr (ip
, &imm_expr
);
9656 if ((unsigned long) imm_expr
.X_add_number
> 0x7ff)
9658 as_warn (_("Invalid value for `%s' (%lu)"),
9660 (unsigned long) imm_expr
.X_add_number
);
9661 imm_expr
.X_add_number
&= 0x7ff;
9663 ip
->insn_opcode
|= imm_expr
.X_add_number
;
9664 imm_expr
.X_op
= O_absent
;
9674 /* Args don't match. */
9675 if (insn
+ 1 < &mips16_opcodes
[bfd_mips16_num_opcodes
] &&
9676 strcmp (insn
->name
, insn
[1].name
) == 0)
9683 insn_error
= _("illegal operands");
9689 /* This structure holds information we know about a mips16 immediate
9692 struct mips16_immed_operand
9694 /* The type code used in the argument string in the opcode table. */
9696 /* The number of bits in the short form of the opcode. */
9698 /* The number of bits in the extended form of the opcode. */
9700 /* The amount by which the short form is shifted when it is used;
9701 for example, the sw instruction has a shift count of 2. */
9703 /* The amount by which the short form is shifted when it is stored
9704 into the instruction code. */
9706 /* Non-zero if the short form is unsigned. */
9708 /* Non-zero if the extended form is unsigned. */
9710 /* Non-zero if the value is PC relative. */
9714 /* The mips16 immediate operand types. */
9716 static const struct mips16_immed_operand mips16_immed_operands
[] =
9718 { '<', 3, 5, 0, MIPS16OP_SH_RZ
, 1, 1, 0 },
9719 { '>', 3, 5, 0, MIPS16OP_SH_RX
, 1, 1, 0 },
9720 { '[', 3, 6, 0, MIPS16OP_SH_RZ
, 1, 1, 0 },
9721 { ']', 3, 6, 0, MIPS16OP_SH_RX
, 1, 1, 0 },
9722 { '4', 4, 15, 0, MIPS16OP_SH_IMM4
, 0, 0, 0 },
9723 { '5', 5, 16, 0, MIPS16OP_SH_IMM5
, 1, 0, 0 },
9724 { 'H', 5, 16, 1, MIPS16OP_SH_IMM5
, 1, 0, 0 },
9725 { 'W', 5, 16, 2, MIPS16OP_SH_IMM5
, 1, 0, 0 },
9726 { 'D', 5, 16, 3, MIPS16OP_SH_IMM5
, 1, 0, 0 },
9727 { 'j', 5, 16, 0, MIPS16OP_SH_IMM5
, 0, 0, 0 },
9728 { '8', 8, 16, 0, MIPS16OP_SH_IMM8
, 1, 0, 0 },
9729 { 'V', 8, 16, 2, MIPS16OP_SH_IMM8
, 1, 0, 0 },
9730 { 'C', 8, 16, 3, MIPS16OP_SH_IMM8
, 1, 0, 0 },
9731 { 'U', 8, 16, 0, MIPS16OP_SH_IMM8
, 1, 1, 0 },
9732 { 'k', 8, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 0 },
9733 { 'K', 8, 16, 3, MIPS16OP_SH_IMM8
, 0, 0, 0 },
9734 { 'p', 8, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 1 },
9735 { 'q', 11, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 1 },
9736 { 'A', 8, 16, 2, MIPS16OP_SH_IMM8
, 1, 0, 1 },
9737 { 'B', 5, 16, 3, MIPS16OP_SH_IMM5
, 1, 0, 1 },
9738 { 'E', 5, 16, 2, MIPS16OP_SH_IMM5
, 1, 0, 1 }
9741 #define MIPS16_NUM_IMMED \
9742 (sizeof mips16_immed_operands / sizeof mips16_immed_operands[0])
9744 /* Handle a mips16 instruction with an immediate value. This or's the
9745 small immediate value into *INSN. It sets *USE_EXTEND to indicate
9746 whether an extended value is needed; if one is needed, it sets
9747 *EXTEND to the value. The argument type is TYPE. The value is VAL.
9748 If SMALL is true, an unextended opcode was explicitly requested.
9749 If EXT is true, an extended opcode was explicitly requested. If
9750 WARN is true, warn if EXT does not match reality. */
9753 mips16_immed (char *file
, unsigned int line
, int type
, offsetT val
,
9754 bfd_boolean warn
, bfd_boolean small
, bfd_boolean ext
,
9755 unsigned long *insn
, bfd_boolean
*use_extend
,
9756 unsigned short *extend
)
9758 register const struct mips16_immed_operand
*op
;
9759 int mintiny
, maxtiny
;
9760 bfd_boolean needext
;
9762 op
= mips16_immed_operands
;
9763 while (op
->type
!= type
)
9766 assert (op
< mips16_immed_operands
+ MIPS16_NUM_IMMED
);
9771 if (type
== '<' || type
== '>' || type
== '[' || type
== ']')
9774 maxtiny
= 1 << op
->nbits
;
9779 maxtiny
= (1 << op
->nbits
) - 1;
9784 mintiny
= - (1 << (op
->nbits
- 1));
9785 maxtiny
= (1 << (op
->nbits
- 1)) - 1;
9788 /* Branch offsets have an implicit 0 in the lowest bit. */
9789 if (type
== 'p' || type
== 'q')
9792 if ((val
& ((1 << op
->shift
) - 1)) != 0
9793 || val
< (mintiny
<< op
->shift
)
9794 || val
> (maxtiny
<< op
->shift
))
9799 if (warn
&& ext
&& ! needext
)
9800 as_warn_where (file
, line
,
9801 _("extended operand requested but not required"));
9802 if (small
&& needext
)
9803 as_bad_where (file
, line
, _("invalid unextended operand value"));
9805 if (small
|| (! ext
&& ! needext
))
9809 *use_extend
= FALSE
;
9810 insnval
= ((val
>> op
->shift
) & ((1 << op
->nbits
) - 1));
9811 insnval
<<= op
->op_shift
;
9816 long minext
, maxext
;
9822 maxext
= (1 << op
->extbits
) - 1;
9826 minext
= - (1 << (op
->extbits
- 1));
9827 maxext
= (1 << (op
->extbits
- 1)) - 1;
9829 if (val
< minext
|| val
> maxext
)
9830 as_bad_where (file
, line
,
9831 _("operand value out of range for instruction"));
9834 if (op
->extbits
== 16)
9836 extval
= ((val
>> 11) & 0x1f) | (val
& 0x7e0);
9839 else if (op
->extbits
== 15)
9841 extval
= ((val
>> 11) & 0xf) | (val
& 0x7f0);
9846 extval
= ((val
& 0x1f) << 6) | (val
& 0x20);
9850 *extend
= (unsigned short) extval
;
9855 struct percent_op_match
9858 bfd_reloc_code_real_type reloc
;
9861 static const struct percent_op_match mips_percent_op
[] =
9863 {"%lo", BFD_RELOC_LO16
},
9865 {"%call_hi", BFD_RELOC_MIPS_CALL_HI16
},
9866 {"%call_lo", BFD_RELOC_MIPS_CALL_LO16
},
9867 {"%call16", BFD_RELOC_MIPS_CALL16
},
9868 {"%got_disp", BFD_RELOC_MIPS_GOT_DISP
},
9869 {"%got_page", BFD_RELOC_MIPS_GOT_PAGE
},
9870 {"%got_ofst", BFD_RELOC_MIPS_GOT_OFST
},
9871 {"%got_hi", BFD_RELOC_MIPS_GOT_HI16
},
9872 {"%got_lo", BFD_RELOC_MIPS_GOT_LO16
},
9873 {"%got", BFD_RELOC_MIPS_GOT16
},
9874 {"%gp_rel", BFD_RELOC_GPREL16
},
9875 {"%half", BFD_RELOC_16
},
9876 {"%highest", BFD_RELOC_MIPS_HIGHEST
},
9877 {"%higher", BFD_RELOC_MIPS_HIGHER
},
9878 {"%neg", BFD_RELOC_MIPS_SUB
},
9879 {"%tlsgd", BFD_RELOC_MIPS_TLS_GD
},
9880 {"%tlsldm", BFD_RELOC_MIPS_TLS_LDM
},
9881 {"%dtprel_hi", BFD_RELOC_MIPS_TLS_DTPREL_HI16
},
9882 {"%dtprel_lo", BFD_RELOC_MIPS_TLS_DTPREL_LO16
},
9883 {"%tprel_hi", BFD_RELOC_MIPS_TLS_TPREL_HI16
},
9884 {"%tprel_lo", BFD_RELOC_MIPS_TLS_TPREL_LO16
},
9885 {"%gottprel", BFD_RELOC_MIPS_TLS_GOTTPREL
},
9887 {"%hi", BFD_RELOC_HI16_S
}
9890 static const struct percent_op_match mips16_percent_op
[] =
9892 {"%lo", BFD_RELOC_MIPS16_LO16
},
9893 {"%gprel", BFD_RELOC_MIPS16_GPREL
},
9894 {"%hi", BFD_RELOC_MIPS16_HI16_S
}
9898 /* Return true if *STR points to a relocation operator. When returning true,
9899 move *STR over the operator and store its relocation code in *RELOC.
9900 Leave both *STR and *RELOC alone when returning false. */
9903 parse_relocation (char **str
, bfd_reloc_code_real_type
*reloc
)
9905 const struct percent_op_match
*percent_op
;
9908 if (mips_opts
.mips16
)
9910 percent_op
= mips16_percent_op
;
9911 limit
= ARRAY_SIZE (mips16_percent_op
);
9915 percent_op
= mips_percent_op
;
9916 limit
= ARRAY_SIZE (mips_percent_op
);
9919 for (i
= 0; i
< limit
; i
++)
9920 if (strncasecmp (*str
, percent_op
[i
].str
, strlen (percent_op
[i
].str
)) == 0)
9922 int len
= strlen (percent_op
[i
].str
);
9924 if (!ISSPACE ((*str
)[len
]) && (*str
)[len
] != '(')
9927 *str
+= strlen (percent_op
[i
].str
);
9928 *reloc
= percent_op
[i
].reloc
;
9930 /* Check whether the output BFD supports this relocation.
9931 If not, issue an error and fall back on something safe. */
9932 if (!bfd_reloc_type_lookup (stdoutput
, percent_op
[i
].reloc
))
9934 as_bad ("relocation %s isn't supported by the current ABI",
9936 *reloc
= BFD_RELOC_UNUSED
;
9944 /* Parse string STR as a 16-bit relocatable operand. Store the
9945 expression in *EP and the relocations in the array starting
9946 at RELOC. Return the number of relocation operators used.
9948 On exit, EXPR_END points to the first character after the expression. */
9951 my_getSmallExpression (expressionS
*ep
, bfd_reloc_code_real_type
*reloc
,
9954 bfd_reloc_code_real_type reversed_reloc
[3];
9955 size_t reloc_index
, i
;
9956 int crux_depth
, str_depth
;
9959 /* Search for the start of the main expression, recoding relocations
9960 in REVERSED_RELOC. End the loop with CRUX pointing to the start
9961 of the main expression and with CRUX_DEPTH containing the number
9962 of open brackets at that point. */
9969 crux_depth
= str_depth
;
9971 /* Skip over whitespace and brackets, keeping count of the number
9973 while (*str
== ' ' || *str
== '\t' || *str
== '(')
9978 && reloc_index
< (HAVE_NEWABI
? 3 : 1)
9979 && parse_relocation (&str
, &reversed_reloc
[reloc_index
]));
9981 my_getExpression (ep
, crux
);
9984 /* Match every open bracket. */
9985 while (crux_depth
> 0 && (*str
== ')' || *str
== ' ' || *str
== '\t'))
9990 as_bad ("unclosed '('");
9994 if (reloc_index
!= 0)
9996 prev_reloc_op_frag
= frag_now
;
9997 for (i
= 0; i
< reloc_index
; i
++)
9998 reloc
[i
] = reversed_reloc
[reloc_index
- 1 - i
];
10001 return reloc_index
;
10005 my_getExpression (expressionS
*ep
, char *str
)
10010 save_in
= input_line_pointer
;
10011 input_line_pointer
= str
;
10013 expr_end
= input_line_pointer
;
10014 input_line_pointer
= save_in
;
10016 /* If we are in mips16 mode, and this is an expression based on `.',
10017 then we bump the value of the symbol by 1 since that is how other
10018 text symbols are handled. We don't bother to handle complex
10019 expressions, just `.' plus or minus a constant. */
10020 if (mips_opts
.mips16
10021 && ep
->X_op
== O_symbol
10022 && strcmp (S_GET_NAME (ep
->X_add_symbol
), FAKE_LABEL_NAME
) == 0
10023 && S_GET_SEGMENT (ep
->X_add_symbol
) == now_seg
10024 && symbol_get_frag (ep
->X_add_symbol
) == frag_now
10025 && symbol_constant_p (ep
->X_add_symbol
)
10026 && (val
= S_GET_VALUE (ep
->X_add_symbol
)) == frag_now_fix ())
10027 S_SET_VALUE (ep
->X_add_symbol
, val
+ 1);
10030 /* Turn a string in input_line_pointer into a floating point constant
10031 of type TYPE, and store the appropriate bytes in *LITP. The number
10032 of LITTLENUMS emitted is stored in *SIZEP. An error message is
10033 returned, or NULL on OK. */
10036 md_atof (int type
, char *litP
, int *sizeP
)
10039 LITTLENUM_TYPE words
[4];
10055 return _("bad call to md_atof");
10058 t
= atof_ieee (input_line_pointer
, type
, words
);
10060 input_line_pointer
= t
;
10064 if (! target_big_endian
)
10066 for (i
= prec
- 1; i
>= 0; i
--)
10068 md_number_to_chars (litP
, words
[i
], 2);
10074 for (i
= 0; i
< prec
; i
++)
10076 md_number_to_chars (litP
, words
[i
], 2);
10085 md_number_to_chars (char *buf
, valueT val
, int n
)
10087 if (target_big_endian
)
10088 number_to_chars_bigendian (buf
, val
, n
);
10090 number_to_chars_littleendian (buf
, val
, n
);
10094 static int support_64bit_objects(void)
10096 const char **list
, **l
;
10099 list
= bfd_target_list ();
10100 for (l
= list
; *l
!= NULL
; l
++)
10102 /* This is traditional mips */
10103 if (strcmp (*l
, "elf64-tradbigmips") == 0
10104 || strcmp (*l
, "elf64-tradlittlemips") == 0)
10106 if (strcmp (*l
, "elf64-bigmips") == 0
10107 || strcmp (*l
, "elf64-littlemips") == 0)
10110 yes
= (*l
!= NULL
);
10114 #endif /* OBJ_ELF */
10116 const char *md_shortopts
= "O::g::G:";
10118 struct option md_longopts
[] =
10120 /* Options which specify architecture. */
10121 #define OPTION_ARCH_BASE (OPTION_MD_BASE)
10122 #define OPTION_MARCH (OPTION_ARCH_BASE + 0)
10123 {"march", required_argument
, NULL
, OPTION_MARCH
},
10124 #define OPTION_MTUNE (OPTION_ARCH_BASE + 1)
10125 {"mtune", required_argument
, NULL
, OPTION_MTUNE
},
10126 #define OPTION_MIPS1 (OPTION_ARCH_BASE + 2)
10127 {"mips0", no_argument
, NULL
, OPTION_MIPS1
},
10128 {"mips1", no_argument
, NULL
, OPTION_MIPS1
},
10129 #define OPTION_MIPS2 (OPTION_ARCH_BASE + 3)
10130 {"mips2", no_argument
, NULL
, OPTION_MIPS2
},
10131 #define OPTION_MIPS3 (OPTION_ARCH_BASE + 4)
10132 {"mips3", no_argument
, NULL
, OPTION_MIPS3
},
10133 #define OPTION_MIPS4 (OPTION_ARCH_BASE + 5)
10134 {"mips4", no_argument
, NULL
, OPTION_MIPS4
},
10135 #define OPTION_MIPS5 (OPTION_ARCH_BASE + 6)
10136 {"mips5", no_argument
, NULL
, OPTION_MIPS5
},
10137 #define OPTION_MIPS32 (OPTION_ARCH_BASE + 7)
10138 {"mips32", no_argument
, NULL
, OPTION_MIPS32
},
10139 #define OPTION_MIPS64 (OPTION_ARCH_BASE + 8)
10140 {"mips64", no_argument
, NULL
, OPTION_MIPS64
},
10141 #define OPTION_MIPS32R2 (OPTION_ARCH_BASE + 9)
10142 {"mips32r2", no_argument
, NULL
, OPTION_MIPS32R2
},
10143 #define OPTION_MIPS64R2 (OPTION_ARCH_BASE + 10)
10144 {"mips64r2", no_argument
, NULL
, OPTION_MIPS64R2
},
10146 /* Options which specify Application Specific Extensions (ASEs). */
10147 #define OPTION_ASE_BASE (OPTION_ARCH_BASE + 11)
10148 #define OPTION_MIPS16 (OPTION_ASE_BASE + 0)
10149 {"mips16", no_argument
, NULL
, OPTION_MIPS16
},
10150 #define OPTION_NO_MIPS16 (OPTION_ASE_BASE + 1)
10151 {"no-mips16", no_argument
, NULL
, OPTION_NO_MIPS16
},
10152 #define OPTION_MIPS3D (OPTION_ASE_BASE + 2)
10153 {"mips3d", no_argument
, NULL
, OPTION_MIPS3D
},
10154 #define OPTION_NO_MIPS3D (OPTION_ASE_BASE + 3)
10155 {"no-mips3d", no_argument
, NULL
, OPTION_NO_MIPS3D
},
10156 #define OPTION_MDMX (OPTION_ASE_BASE + 4)
10157 {"mdmx", no_argument
, NULL
, OPTION_MDMX
},
10158 #define OPTION_NO_MDMX (OPTION_ASE_BASE + 5)
10159 {"no-mdmx", no_argument
, NULL
, OPTION_NO_MDMX
},
10161 /* Old-style architecture options. Don't add more of these. */
10162 #define OPTION_COMPAT_ARCH_BASE (OPTION_ASE_BASE + 6)
10163 #define OPTION_M4650 (OPTION_COMPAT_ARCH_BASE + 0)
10164 {"m4650", no_argument
, NULL
, OPTION_M4650
},
10165 #define OPTION_NO_M4650 (OPTION_COMPAT_ARCH_BASE + 1)
10166 {"no-m4650", no_argument
, NULL
, OPTION_NO_M4650
},
10167 #define OPTION_M4010 (OPTION_COMPAT_ARCH_BASE + 2)
10168 {"m4010", no_argument
, NULL
, OPTION_M4010
},
10169 #define OPTION_NO_M4010 (OPTION_COMPAT_ARCH_BASE + 3)
10170 {"no-m4010", no_argument
, NULL
, OPTION_NO_M4010
},
10171 #define OPTION_M4100 (OPTION_COMPAT_ARCH_BASE + 4)
10172 {"m4100", no_argument
, NULL
, OPTION_M4100
},
10173 #define OPTION_NO_M4100 (OPTION_COMPAT_ARCH_BASE + 5)
10174 {"no-m4100", no_argument
, NULL
, OPTION_NO_M4100
},
10175 #define OPTION_M3900 (OPTION_COMPAT_ARCH_BASE + 6)
10176 {"m3900", no_argument
, NULL
, OPTION_M3900
},
10177 #define OPTION_NO_M3900 (OPTION_COMPAT_ARCH_BASE + 7)
10178 {"no-m3900", no_argument
, NULL
, OPTION_NO_M3900
},
10180 /* Options which enable bug fixes. */
10181 #define OPTION_FIX_BASE (OPTION_COMPAT_ARCH_BASE + 8)
10182 #define OPTION_M7000_HILO_FIX (OPTION_FIX_BASE + 0)
10183 {"mfix7000", no_argument
, NULL
, OPTION_M7000_HILO_FIX
},
10184 #define OPTION_MNO_7000_HILO_FIX (OPTION_FIX_BASE + 1)
10185 {"no-fix-7000", no_argument
, NULL
, OPTION_MNO_7000_HILO_FIX
},
10186 {"mno-fix7000", no_argument
, NULL
, OPTION_MNO_7000_HILO_FIX
},
10187 #define OPTION_FIX_VR4120 (OPTION_FIX_BASE + 2)
10188 #define OPTION_NO_FIX_VR4120 (OPTION_FIX_BASE + 3)
10189 {"mfix-vr4120", no_argument
, NULL
, OPTION_FIX_VR4120
},
10190 {"mno-fix-vr4120", no_argument
, NULL
, OPTION_NO_FIX_VR4120
},
10192 /* Miscellaneous options. */
10193 #define OPTION_MISC_BASE (OPTION_FIX_BASE + 4)
10194 #define OPTION_TRAP (OPTION_MISC_BASE + 0)
10195 {"trap", no_argument
, NULL
, OPTION_TRAP
},
10196 {"no-break", no_argument
, NULL
, OPTION_TRAP
},
10197 #define OPTION_BREAK (OPTION_MISC_BASE + 1)
10198 {"break", no_argument
, NULL
, OPTION_BREAK
},
10199 {"no-trap", no_argument
, NULL
, OPTION_BREAK
},
10200 #define OPTION_EB (OPTION_MISC_BASE + 2)
10201 {"EB", no_argument
, NULL
, OPTION_EB
},
10202 #define OPTION_EL (OPTION_MISC_BASE + 3)
10203 {"EL", no_argument
, NULL
, OPTION_EL
},
10204 #define OPTION_FP32 (OPTION_MISC_BASE + 4)
10205 {"mfp32", no_argument
, NULL
, OPTION_FP32
},
10206 #define OPTION_GP32 (OPTION_MISC_BASE + 5)
10207 {"mgp32", no_argument
, NULL
, OPTION_GP32
},
10208 #define OPTION_CONSTRUCT_FLOATS (OPTION_MISC_BASE + 6)
10209 {"construct-floats", no_argument
, NULL
, OPTION_CONSTRUCT_FLOATS
},
10210 #define OPTION_NO_CONSTRUCT_FLOATS (OPTION_MISC_BASE + 7)
10211 {"no-construct-floats", no_argument
, NULL
, OPTION_NO_CONSTRUCT_FLOATS
},
10212 #define OPTION_FP64 (OPTION_MISC_BASE + 8)
10213 {"mfp64", no_argument
, NULL
, OPTION_FP64
},
10214 #define OPTION_GP64 (OPTION_MISC_BASE + 9)
10215 {"mgp64", no_argument
, NULL
, OPTION_GP64
},
10216 #define OPTION_RELAX_BRANCH (OPTION_MISC_BASE + 10)
10217 #define OPTION_NO_RELAX_BRANCH (OPTION_MISC_BASE + 11)
10218 {"relax-branch", no_argument
, NULL
, OPTION_RELAX_BRANCH
},
10219 {"no-relax-branch", no_argument
, NULL
, OPTION_NO_RELAX_BRANCH
},
10220 #define OPTION_MSHARED (OPTION_MISC_BASE + 12)
10221 #define OPTION_MNO_SHARED (OPTION_MISC_BASE + 13)
10222 {"mshared", no_argument
, NULL
, OPTION_MSHARED
},
10223 {"mno-shared", no_argument
, NULL
, OPTION_MNO_SHARED
},
10224 #define OPTION_MSYM32 (OPTION_MISC_BASE + 14)
10225 #define OPTION_MNO_SYM32 (OPTION_MISC_BASE + 15)
10226 {"msym32", no_argument
, NULL
, OPTION_MSYM32
},
10227 {"mno-sym32", no_argument
, NULL
, OPTION_MNO_SYM32
},
10229 /* ELF-specific options. */
10231 #define OPTION_ELF_BASE (OPTION_MISC_BASE + 16)
10232 #define OPTION_CALL_SHARED (OPTION_ELF_BASE + 0)
10233 {"KPIC", no_argument
, NULL
, OPTION_CALL_SHARED
},
10234 {"call_shared", no_argument
, NULL
, OPTION_CALL_SHARED
},
10235 #define OPTION_NON_SHARED (OPTION_ELF_BASE + 1)
10236 {"non_shared", no_argument
, NULL
, OPTION_NON_SHARED
},
10237 #define OPTION_XGOT (OPTION_ELF_BASE + 2)
10238 {"xgot", no_argument
, NULL
, OPTION_XGOT
},
10239 #define OPTION_MABI (OPTION_ELF_BASE + 3)
10240 {"mabi", required_argument
, NULL
, OPTION_MABI
},
10241 #define OPTION_32 (OPTION_ELF_BASE + 4)
10242 {"32", no_argument
, NULL
, OPTION_32
},
10243 #define OPTION_N32 (OPTION_ELF_BASE + 5)
10244 {"n32", no_argument
, NULL
, OPTION_N32
},
10245 #define OPTION_64 (OPTION_ELF_BASE + 6)
10246 {"64", no_argument
, NULL
, OPTION_64
},
10247 #define OPTION_MDEBUG (OPTION_ELF_BASE + 7)
10248 {"mdebug", no_argument
, NULL
, OPTION_MDEBUG
},
10249 #define OPTION_NO_MDEBUG (OPTION_ELF_BASE + 8)
10250 {"no-mdebug", no_argument
, NULL
, OPTION_NO_MDEBUG
},
10251 #define OPTION_PDR (OPTION_ELF_BASE + 9)
10252 {"mpdr", no_argument
, NULL
, OPTION_PDR
},
10253 #define OPTION_NO_PDR (OPTION_ELF_BASE + 10)
10254 {"mno-pdr", no_argument
, NULL
, OPTION_NO_PDR
},
10255 #endif /* OBJ_ELF */
10257 {NULL
, no_argument
, NULL
, 0}
10259 size_t md_longopts_size
= sizeof (md_longopts
);
10261 /* Set STRING_PTR (either &mips_arch_string or &mips_tune_string) to
10262 NEW_VALUE. Warn if another value was already specified. Note:
10263 we have to defer parsing the -march and -mtune arguments in order
10264 to handle 'from-abi' correctly, since the ABI might be specified
10265 in a later argument. */
10268 mips_set_option_string (const char **string_ptr
, const char *new_value
)
10270 if (*string_ptr
!= 0 && strcasecmp (*string_ptr
, new_value
) != 0)
10271 as_warn (_("A different %s was already specified, is now %s"),
10272 string_ptr
== &mips_arch_string
? "-march" : "-mtune",
10275 *string_ptr
= new_value
;
10279 md_parse_option (int c
, char *arg
)
10283 case OPTION_CONSTRUCT_FLOATS
:
10284 mips_disable_float_construction
= 0;
10287 case OPTION_NO_CONSTRUCT_FLOATS
:
10288 mips_disable_float_construction
= 1;
10300 target_big_endian
= 1;
10304 target_big_endian
= 0;
10308 if (arg
&& arg
[1] == '0')
10318 mips_debug
= atoi (arg
);
10319 /* When the MIPS assembler sees -g or -g2, it does not do
10320 optimizations which limit full symbolic debugging. We take
10321 that to be equivalent to -O0. */
10322 if (mips_debug
== 2)
10327 file_mips_isa
= ISA_MIPS1
;
10331 file_mips_isa
= ISA_MIPS2
;
10335 file_mips_isa
= ISA_MIPS3
;
10339 file_mips_isa
= ISA_MIPS4
;
10343 file_mips_isa
= ISA_MIPS5
;
10346 case OPTION_MIPS32
:
10347 file_mips_isa
= ISA_MIPS32
;
10350 case OPTION_MIPS32R2
:
10351 file_mips_isa
= ISA_MIPS32R2
;
10354 case OPTION_MIPS64R2
:
10355 file_mips_isa
= ISA_MIPS64R2
;
10358 case OPTION_MIPS64
:
10359 file_mips_isa
= ISA_MIPS64
;
10363 mips_set_option_string (&mips_tune_string
, arg
);
10367 mips_set_option_string (&mips_arch_string
, arg
);
10371 mips_set_option_string (&mips_arch_string
, "4650");
10372 mips_set_option_string (&mips_tune_string
, "4650");
10375 case OPTION_NO_M4650
:
10379 mips_set_option_string (&mips_arch_string
, "4010");
10380 mips_set_option_string (&mips_tune_string
, "4010");
10383 case OPTION_NO_M4010
:
10387 mips_set_option_string (&mips_arch_string
, "4100");
10388 mips_set_option_string (&mips_tune_string
, "4100");
10391 case OPTION_NO_M4100
:
10395 mips_set_option_string (&mips_arch_string
, "3900");
10396 mips_set_option_string (&mips_tune_string
, "3900");
10399 case OPTION_NO_M3900
:
10403 mips_opts
.ase_mdmx
= 1;
10406 case OPTION_NO_MDMX
:
10407 mips_opts
.ase_mdmx
= 0;
10410 case OPTION_MIPS16
:
10411 mips_opts
.mips16
= 1;
10412 mips_no_prev_insn (FALSE
);
10415 case OPTION_NO_MIPS16
:
10416 mips_opts
.mips16
= 0;
10417 mips_no_prev_insn (FALSE
);
10420 case OPTION_MIPS3D
:
10421 mips_opts
.ase_mips3d
= 1;
10424 case OPTION_NO_MIPS3D
:
10425 mips_opts
.ase_mips3d
= 0;
10428 case OPTION_FIX_VR4120
:
10429 mips_fix_vr4120
= 1;
10432 case OPTION_NO_FIX_VR4120
:
10433 mips_fix_vr4120
= 0;
10436 case OPTION_RELAX_BRANCH
:
10437 mips_relax_branch
= 1;
10440 case OPTION_NO_RELAX_BRANCH
:
10441 mips_relax_branch
= 0;
10444 case OPTION_MSHARED
:
10445 mips_in_shared
= TRUE
;
10448 case OPTION_MNO_SHARED
:
10449 mips_in_shared
= FALSE
;
10452 case OPTION_MSYM32
:
10453 mips_opts
.sym32
= TRUE
;
10456 case OPTION_MNO_SYM32
:
10457 mips_opts
.sym32
= FALSE
;
10461 /* When generating ELF code, we permit -KPIC and -call_shared to
10462 select SVR4_PIC, and -non_shared to select no PIC. This is
10463 intended to be compatible with Irix 5. */
10464 case OPTION_CALL_SHARED
:
10465 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
10467 as_bad (_("-call_shared is supported only for ELF format"));
10470 mips_pic
= SVR4_PIC
;
10471 mips_abicalls
= TRUE
;
10472 if (g_switch_seen
&& g_switch_value
!= 0)
10474 as_bad (_("-G may not be used with SVR4 PIC code"));
10477 g_switch_value
= 0;
10480 case OPTION_NON_SHARED
:
10481 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
10483 as_bad (_("-non_shared is supported only for ELF format"));
10487 mips_abicalls
= FALSE
;
10490 /* The -xgot option tells the assembler to use 32 offsets when
10491 accessing the got in SVR4_PIC mode. It is for Irix
10496 #endif /* OBJ_ELF */
10499 g_switch_value
= atoi (arg
);
10501 if (mips_pic
== SVR4_PIC
&& g_switch_value
!= 0)
10503 as_bad (_("-G may not be used with SVR4 PIC code"));
10509 /* The -32, -n32 and -64 options are shortcuts for -mabi=32, -mabi=n32
10512 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
10514 as_bad (_("-32 is supported for ELF format only"));
10517 mips_abi
= O32_ABI
;
10521 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
10523 as_bad (_("-n32 is supported for ELF format only"));
10526 mips_abi
= N32_ABI
;
10530 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
10532 as_bad (_("-64 is supported for ELF format only"));
10535 mips_abi
= N64_ABI
;
10536 if (! support_64bit_objects())
10537 as_fatal (_("No compiled in support for 64 bit object file format"));
10539 #endif /* OBJ_ELF */
10542 file_mips_gp32
= 1;
10546 file_mips_gp32
= 0;
10550 file_mips_fp32
= 1;
10554 file_mips_fp32
= 0;
10559 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
10561 as_bad (_("-mabi is supported for ELF format only"));
10564 if (strcmp (arg
, "32") == 0)
10565 mips_abi
= O32_ABI
;
10566 else if (strcmp (arg
, "o64") == 0)
10567 mips_abi
= O64_ABI
;
10568 else if (strcmp (arg
, "n32") == 0)
10569 mips_abi
= N32_ABI
;
10570 else if (strcmp (arg
, "64") == 0)
10572 mips_abi
= N64_ABI
;
10573 if (! support_64bit_objects())
10574 as_fatal (_("No compiled in support for 64 bit object file "
10577 else if (strcmp (arg
, "eabi") == 0)
10578 mips_abi
= EABI_ABI
;
10581 as_fatal (_("invalid abi -mabi=%s"), arg
);
10585 #endif /* OBJ_ELF */
10587 case OPTION_M7000_HILO_FIX
:
10588 mips_7000_hilo_fix
= TRUE
;
10591 case OPTION_MNO_7000_HILO_FIX
:
10592 mips_7000_hilo_fix
= FALSE
;
10596 case OPTION_MDEBUG
:
10597 mips_flag_mdebug
= TRUE
;
10600 case OPTION_NO_MDEBUG
:
10601 mips_flag_mdebug
= FALSE
;
10605 mips_flag_pdr
= TRUE
;
10608 case OPTION_NO_PDR
:
10609 mips_flag_pdr
= FALSE
;
10611 #endif /* OBJ_ELF */
10620 /* Set up globals to generate code for the ISA or processor
10621 described by INFO. */
10624 mips_set_architecture (const struct mips_cpu_info
*info
)
10628 file_mips_arch
= info
->cpu
;
10629 mips_opts
.arch
= info
->cpu
;
10630 mips_opts
.isa
= info
->isa
;
10635 /* Likewise for tuning. */
10638 mips_set_tune (const struct mips_cpu_info
*info
)
10641 mips_tune
= info
->cpu
;
10646 mips_after_parse_args (void)
10648 const struct mips_cpu_info
*arch_info
= 0;
10649 const struct mips_cpu_info
*tune_info
= 0;
10651 /* GP relative stuff not working for PE */
10652 if (strncmp (TARGET_OS
, "pe", 2) == 0)
10654 if (g_switch_seen
&& g_switch_value
!= 0)
10655 as_bad (_("-G not supported in this configuration."));
10656 g_switch_value
= 0;
10659 if (mips_abi
== NO_ABI
)
10660 mips_abi
= MIPS_DEFAULT_ABI
;
10662 /* The following code determines the architecture and register size.
10663 Similar code was added to GCC 3.3 (see override_options() in
10664 config/mips/mips.c). The GAS and GCC code should be kept in sync
10665 as much as possible. */
10667 if (mips_arch_string
!= 0)
10668 arch_info
= mips_parse_cpu ("-march", mips_arch_string
);
10670 if (file_mips_isa
!= ISA_UNKNOWN
)
10672 /* Handle -mipsN. At this point, file_mips_isa contains the
10673 ISA level specified by -mipsN, while arch_info->isa contains
10674 the -march selection (if any). */
10675 if (arch_info
!= 0)
10677 /* -march takes precedence over -mipsN, since it is more descriptive.
10678 There's no harm in specifying both as long as the ISA levels
10680 if (file_mips_isa
!= arch_info
->isa
)
10681 as_bad (_("-%s conflicts with the other architecture options, which imply -%s"),
10682 mips_cpu_info_from_isa (file_mips_isa
)->name
,
10683 mips_cpu_info_from_isa (arch_info
->isa
)->name
);
10686 arch_info
= mips_cpu_info_from_isa (file_mips_isa
);
10689 if (arch_info
== 0)
10690 arch_info
= mips_parse_cpu ("default CPU", MIPS_CPU_STRING_DEFAULT
);
10692 if (ABI_NEEDS_64BIT_REGS (mips_abi
) && !ISA_HAS_64BIT_REGS (arch_info
->isa
))
10693 as_bad ("-march=%s is not compatible with the selected ABI",
10696 mips_set_architecture (arch_info
);
10698 /* Optimize for file_mips_arch, unless -mtune selects a different processor. */
10699 if (mips_tune_string
!= 0)
10700 tune_info
= mips_parse_cpu ("-mtune", mips_tune_string
);
10702 if (tune_info
== 0)
10703 mips_set_tune (arch_info
);
10705 mips_set_tune (tune_info
);
10707 if (file_mips_gp32
>= 0)
10709 /* The user specified the size of the integer registers. Make sure
10710 it agrees with the ABI and ISA. */
10711 if (file_mips_gp32
== 0 && !ISA_HAS_64BIT_REGS (mips_opts
.isa
))
10712 as_bad (_("-mgp64 used with a 32-bit processor"));
10713 else if (file_mips_gp32
== 1 && ABI_NEEDS_64BIT_REGS (mips_abi
))
10714 as_bad (_("-mgp32 used with a 64-bit ABI"));
10715 else if (file_mips_gp32
== 0 && ABI_NEEDS_32BIT_REGS (mips_abi
))
10716 as_bad (_("-mgp64 used with a 32-bit ABI"));
10720 /* Infer the integer register size from the ABI and processor.
10721 Restrict ourselves to 32-bit registers if that's all the
10722 processor has, or if the ABI cannot handle 64-bit registers. */
10723 file_mips_gp32
= (ABI_NEEDS_32BIT_REGS (mips_abi
)
10724 || !ISA_HAS_64BIT_REGS (mips_opts
.isa
));
10727 /* ??? GAS treats single-float processors as though they had 64-bit
10728 float registers (although it complains when double-precision
10729 instructions are used). As things stand, saying they have 32-bit
10730 registers would lead to spurious "register must be even" messages.
10731 So here we assume float registers are always the same size as
10732 integer ones, unless the user says otherwise. */
10733 if (file_mips_fp32
< 0)
10734 file_mips_fp32
= file_mips_gp32
;
10736 /* End of GCC-shared inference code. */
10738 /* This flag is set when we have a 64-bit capable CPU but use only
10739 32-bit wide registers. Note that EABI does not use it. */
10740 if (ISA_HAS_64BIT_REGS (mips_opts
.isa
)
10741 && ((mips_abi
== NO_ABI
&& file_mips_gp32
== 1)
10742 || mips_abi
== O32_ABI
))
10743 mips_32bitmode
= 1;
10745 if (mips_opts
.isa
== ISA_MIPS1
&& mips_trap
)
10746 as_bad (_("trap exception not supported at ISA 1"));
10748 /* If the selected architecture includes support for ASEs, enable
10749 generation of code for them. */
10750 if (mips_opts
.mips16
== -1)
10751 mips_opts
.mips16
= (CPU_HAS_MIPS16 (file_mips_arch
)) ? 1 : 0;
10752 if (mips_opts
.ase_mips3d
== -1)
10753 mips_opts
.ase_mips3d
= (CPU_HAS_MIPS3D (file_mips_arch
)) ? 1 : 0;
10754 if (mips_opts
.ase_mdmx
== -1)
10755 mips_opts
.ase_mdmx
= (CPU_HAS_MDMX (file_mips_arch
)) ? 1 : 0;
10757 file_mips_isa
= mips_opts
.isa
;
10758 file_ase_mips16
= mips_opts
.mips16
;
10759 file_ase_mips3d
= mips_opts
.ase_mips3d
;
10760 file_ase_mdmx
= mips_opts
.ase_mdmx
;
10761 mips_opts
.gp32
= file_mips_gp32
;
10762 mips_opts
.fp32
= file_mips_fp32
;
10764 if (mips_flag_mdebug
< 0)
10766 #ifdef OBJ_MAYBE_ECOFF
10767 if (OUTPUT_FLAVOR
== bfd_target_ecoff_flavour
)
10768 mips_flag_mdebug
= 1;
10770 #endif /* OBJ_MAYBE_ECOFF */
10771 mips_flag_mdebug
= 0;
10776 mips_init_after_args (void)
10778 /* initialize opcodes */
10779 bfd_mips_num_opcodes
= bfd_mips_num_builtin_opcodes
;
10780 mips_opcodes
= (struct mips_opcode
*) mips_builtin_opcodes
;
10784 md_pcrel_from (fixS
*fixP
)
10786 valueT addr
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
10787 switch (fixP
->fx_r_type
)
10789 case BFD_RELOC_16_PCREL_S2
:
10790 case BFD_RELOC_MIPS_JMP
:
10791 /* Return the address of the delay slot. */
10798 /* This is called before the symbol table is processed. In order to
10799 work with gcc when using mips-tfile, we must keep all local labels.
10800 However, in other cases, we want to discard them. If we were
10801 called with -g, but we didn't see any debugging information, it may
10802 mean that gcc is smuggling debugging information through to
10803 mips-tfile, in which case we must generate all local labels. */
10806 mips_frob_file_before_adjust (void)
10808 #ifndef NO_ECOFF_DEBUGGING
10809 if (ECOFF_DEBUGGING
10811 && ! ecoff_debugging_seen
)
10812 flag_keep_locals
= 1;
10816 /* Sort any unmatched HI16 and GOT16 relocs so that they immediately precede
10817 the corresponding LO16 reloc. This is called before md_apply_fix3 and
10818 tc_gen_reloc. Unmatched relocs can only be generated by use of explicit
10819 relocation operators.
10821 For our purposes, a %lo() expression matches a %got() or %hi()
10824 (a) it refers to the same symbol; and
10825 (b) the offset applied in the %lo() expression is no lower than
10826 the offset applied in the %got() or %hi().
10828 (b) allows us to cope with code like:
10831 lh $4,%lo(foo+2)($4)
10833 ...which is legal on RELA targets, and has a well-defined behaviour
10834 if the user knows that adding 2 to "foo" will not induce a carry to
10837 When several %lo()s match a particular %got() or %hi(), we use the
10838 following rules to distinguish them:
10840 (1) %lo()s with smaller offsets are a better match than %lo()s with
10843 (2) %lo()s with no matching %got() or %hi() are better than those
10844 that already have a matching %got() or %hi().
10846 (3) later %lo()s are better than earlier %lo()s.
10848 These rules are applied in order.
10850 (1) means, among other things, that %lo()s with identical offsets are
10851 chosen if they exist.
10853 (2) means that we won't associate several high-part relocations with
10854 the same low-part relocation unless there's no alternative. Having
10855 several high parts for the same low part is a GNU extension; this rule
10856 allows careful users to avoid it.
10858 (3) is purely cosmetic. mips_hi_fixup_list is is in reverse order,
10859 with the last high-part relocation being at the front of the list.
10860 It therefore makes sense to choose the last matching low-part
10861 relocation, all other things being equal. It's also easier
10862 to code that way. */
10865 mips_frob_file (void)
10867 struct mips_hi_fixup
*l
;
10869 for (l
= mips_hi_fixup_list
; l
!= NULL
; l
= l
->next
)
10871 segment_info_type
*seginfo
;
10872 bfd_boolean matched_lo_p
;
10873 fixS
**hi_pos
, **lo_pos
, **pos
;
10875 assert (reloc_needs_lo_p (l
->fixp
->fx_r_type
));
10877 /* If a GOT16 relocation turns out to be against a global symbol,
10878 there isn't supposed to be a matching LO. */
10879 if (l
->fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT16
10880 && !pic_need_relax (l
->fixp
->fx_addsy
, l
->seg
))
10883 /* Check quickly whether the next fixup happens to be a matching %lo. */
10884 if (fixup_has_matching_lo_p (l
->fixp
))
10887 seginfo
= seg_info (l
->seg
);
10889 /* Set HI_POS to the position of this relocation in the chain.
10890 Set LO_POS to the position of the chosen low-part relocation.
10891 MATCHED_LO_P is true on entry to the loop if *POS is a low-part
10892 relocation that matches an immediately-preceding high-part
10896 matched_lo_p
= FALSE
;
10897 for (pos
= &seginfo
->fix_root
; *pos
!= NULL
; pos
= &(*pos
)->fx_next
)
10899 if (*pos
== l
->fixp
)
10902 if ((*pos
)->fx_r_type
== BFD_RELOC_LO16
10903 && (*pos
)->fx_addsy
== l
->fixp
->fx_addsy
10904 && (*pos
)->fx_offset
>= l
->fixp
->fx_offset
10906 || (*pos
)->fx_offset
< (*lo_pos
)->fx_offset
10908 && (*pos
)->fx_offset
== (*lo_pos
)->fx_offset
)))
10911 matched_lo_p
= (reloc_needs_lo_p ((*pos
)->fx_r_type
)
10912 && fixup_has_matching_lo_p (*pos
));
10915 /* If we found a match, remove the high-part relocation from its
10916 current position and insert it before the low-part relocation.
10917 Make the offsets match so that fixup_has_matching_lo_p()
10920 We don't warn about unmatched high-part relocations since some
10921 versions of gcc have been known to emit dead "lui ...%hi(...)"
10923 if (lo_pos
!= NULL
)
10925 l
->fixp
->fx_offset
= (*lo_pos
)->fx_offset
;
10926 if (l
->fixp
->fx_next
!= *lo_pos
)
10928 *hi_pos
= l
->fixp
->fx_next
;
10929 l
->fixp
->fx_next
= *lo_pos
;
10936 /* We may have combined relocations without symbols in the N32/N64 ABI.
10937 We have to prevent gas from dropping them. */
10940 mips_force_relocation (fixS
*fixp
)
10942 if (generic_force_reloc (fixp
))
10946 && S_GET_SEGMENT (fixp
->fx_addsy
) == bfd_abs_section_ptr
10947 && (fixp
->fx_r_type
== BFD_RELOC_MIPS_SUB
10948 || fixp
->fx_r_type
== BFD_RELOC_HI16_S
10949 || fixp
->fx_r_type
== BFD_RELOC_LO16
))
10955 /* This hook is called before a fix is simplified. We don't really
10956 decide whether to skip a fix here. Rather, we turn global symbols
10957 used as branch targets into local symbols, such that they undergo
10958 simplification. We can only do this if the symbol is defined and
10959 it is in the same section as the branch. If this doesn't hold, we
10960 emit a better error message than just saying the relocation is not
10961 valid for the selected object format.
10963 FIXP is the fix-up we're going to try to simplify, SEG is the
10964 segment in which the fix up occurs. The return value should be
10965 non-zero to indicate the fix-up is valid for further
10966 simplifications. */
10969 mips_validate_fix (struct fix
*fixP
, asection
*seg
)
10971 /* There's a lot of discussion on whether it should be possible to
10972 use R_MIPS_PC16 to represent branch relocations. The outcome
10973 seems to be that it can, but gas/bfd are very broken in creating
10974 RELA relocations for this, so for now we only accept branches to
10975 symbols in the same section. Anything else is of dubious value,
10976 since there's no guarantee that at link time the symbol would be
10977 in range. Even for branches to local symbols this is arguably
10978 wrong, since it we assume the symbol is not going to be
10979 overridden, which should be possible per ELF library semantics,
10980 but then, there isn't a dynamic relocation that could be used to
10981 this effect, and the target would likely be out of range as well.
10983 Unfortunately, it seems that there is too much code out there
10984 that relies on branches to symbols that are global to be resolved
10985 as if they were local, like the IRIX tools do, so we do it as
10986 well, but with a warning so that people are reminded to fix their
10987 code. If we ever get back to using R_MIPS_PC16 for branch
10988 targets, this entire block should go away (and probably the
10989 whole function). */
10991 if (fixP
->fx_r_type
== BFD_RELOC_16_PCREL_S2
10992 && ((OUTPUT_FLAVOR
== bfd_target_ecoff_flavour
10993 || OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
10994 || bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_16_PCREL_S2
) == NULL
)
10997 if (! S_IS_DEFINED (fixP
->fx_addsy
))
10999 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
11000 _("Cannot branch to undefined symbol."));
11001 /* Avoid any further errors about this fixup. */
11004 else if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
11006 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
11007 _("Cannot branch to symbol in another section."));
11010 else if (S_IS_EXTERNAL (fixP
->fx_addsy
))
11012 symbolS
*sym
= fixP
->fx_addsy
;
11014 if (mips_pic
== SVR4_PIC
)
11015 as_warn_where (fixP
->fx_file
, fixP
->fx_line
,
11016 _("Pretending global symbol used as branch target is local."));
11018 fixP
->fx_addsy
= symbol_create (S_GET_NAME (sym
),
11019 S_GET_SEGMENT (sym
),
11021 symbol_get_frag (sym
));
11022 copy_symbol_attributes (fixP
->fx_addsy
, sym
);
11023 S_CLEAR_EXTERNAL (fixP
->fx_addsy
);
11024 assert (symbol_resolved_p (sym
));
11025 symbol_mark_resolved (fixP
->fx_addsy
);
11032 /* Apply a fixup to the object file. */
11035 md_apply_fix3 (fixS
*fixP
, valueT
*valP
, segT seg ATTRIBUTE_UNUSED
)
11039 reloc_howto_type
*howto
;
11041 /* We ignore generic BFD relocations we don't know about. */
11042 howto
= bfd_reloc_type_lookup (stdoutput
, fixP
->fx_r_type
);
11046 assert (fixP
->fx_size
== 4
11047 || fixP
->fx_r_type
== BFD_RELOC_16
11048 || fixP
->fx_r_type
== BFD_RELOC_64
11049 || fixP
->fx_r_type
== BFD_RELOC_CTOR
11050 || fixP
->fx_r_type
== BFD_RELOC_MIPS_SUB
11051 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
11052 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
);
11054 buf
= (bfd_byte
*) (fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
);
11056 assert (! fixP
->fx_pcrel
);
11058 /* Don't treat parts of a composite relocation as done. There are two
11061 (1) The second and third parts will be against 0 (RSS_UNDEF) but
11062 should nevertheless be emitted if the first part is.
11064 (2) In normal usage, composite relocations are never assembly-time
11065 constants. The easiest way of dealing with the pathological
11066 exceptions is to generate a relocation against STN_UNDEF and
11067 leave everything up to the linker. */
11068 if (fixP
->fx_addsy
== NULL
&& fixP
->fx_tcbit
== 0)
11071 switch (fixP
->fx_r_type
)
11073 case BFD_RELOC_MIPS_TLS_GD
:
11074 case BFD_RELOC_MIPS_TLS_LDM
:
11075 case BFD_RELOC_MIPS_TLS_DTPREL_HI16
:
11076 case BFD_RELOC_MIPS_TLS_DTPREL_LO16
:
11077 case BFD_RELOC_MIPS_TLS_GOTTPREL
:
11078 case BFD_RELOC_MIPS_TLS_TPREL_HI16
:
11079 case BFD_RELOC_MIPS_TLS_TPREL_LO16
:
11080 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
11083 case BFD_RELOC_MIPS_JMP
:
11084 case BFD_RELOC_MIPS_SHIFT5
:
11085 case BFD_RELOC_MIPS_SHIFT6
:
11086 case BFD_RELOC_MIPS_GOT_DISP
:
11087 case BFD_RELOC_MIPS_GOT_PAGE
:
11088 case BFD_RELOC_MIPS_GOT_OFST
:
11089 case BFD_RELOC_MIPS_SUB
:
11090 case BFD_RELOC_MIPS_INSERT_A
:
11091 case BFD_RELOC_MIPS_INSERT_B
:
11092 case BFD_RELOC_MIPS_DELETE
:
11093 case BFD_RELOC_MIPS_HIGHEST
:
11094 case BFD_RELOC_MIPS_HIGHER
:
11095 case BFD_RELOC_MIPS_SCN_DISP
:
11096 case BFD_RELOC_MIPS_REL16
:
11097 case BFD_RELOC_MIPS_RELGOT
:
11098 case BFD_RELOC_MIPS_JALR
:
11099 case BFD_RELOC_HI16
:
11100 case BFD_RELOC_HI16_S
:
11101 case BFD_RELOC_GPREL16
:
11102 case BFD_RELOC_MIPS_LITERAL
:
11103 case BFD_RELOC_MIPS_CALL16
:
11104 case BFD_RELOC_MIPS_GOT16
:
11105 case BFD_RELOC_GPREL32
:
11106 case BFD_RELOC_MIPS_GOT_HI16
:
11107 case BFD_RELOC_MIPS_GOT_LO16
:
11108 case BFD_RELOC_MIPS_CALL_HI16
:
11109 case BFD_RELOC_MIPS_CALL_LO16
:
11110 case BFD_RELOC_MIPS16_GPREL
:
11111 case BFD_RELOC_MIPS16_HI16
:
11112 case BFD_RELOC_MIPS16_HI16_S
:
11113 assert (! fixP
->fx_pcrel
);
11114 /* Nothing needed to do. The value comes from the reloc entry */
11117 case BFD_RELOC_MIPS16_JMP
:
11118 /* We currently always generate a reloc against a symbol, which
11119 means that we don't want an addend even if the symbol is
11125 /* This is handled like BFD_RELOC_32, but we output a sign
11126 extended value if we are only 32 bits. */
11129 if (8 <= sizeof (valueT
))
11130 md_number_to_chars ((char *) buf
, *valP
, 8);
11135 if ((*valP
& 0x80000000) != 0)
11139 md_number_to_chars ((char *)(buf
+ target_big_endian
? 4 : 0),
11141 md_number_to_chars ((char *)(buf
+ target_big_endian
? 0 : 4),
11147 case BFD_RELOC_RVA
:
11149 /* If we are deleting this reloc entry, we must fill in the
11150 value now. This can happen if we have a .word which is not
11151 resolved when it appears but is later defined. */
11153 md_number_to_chars ((char *) buf
, *valP
, 4);
11157 /* If we are deleting this reloc entry, we must fill in the
11160 md_number_to_chars ((char *) buf
, *valP
, 2);
11163 case BFD_RELOC_LO16
:
11164 case BFD_RELOC_MIPS16_LO16
:
11165 /* FIXME: Now that embedded-PIC is gone, some of this code/comment
11166 may be safe to remove, but if so it's not obvious. */
11167 /* When handling an embedded PIC switch statement, we can wind
11168 up deleting a LO16 reloc. See the 'o' case in mips_ip. */
11171 if (*valP
+ 0x8000 > 0xffff)
11172 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
11173 _("relocation overflow"));
11174 if (target_big_endian
)
11176 md_number_to_chars ((char *) buf
, *valP
, 2);
11180 case BFD_RELOC_16_PCREL_S2
:
11181 if ((*valP
& 0x3) != 0)
11182 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
11183 _("Branch to odd address (%lx)"), (long) *valP
);
11186 * We need to save the bits in the instruction since fixup_segment()
11187 * might be deleting the relocation entry (i.e., a branch within
11188 * the current segment).
11190 if (! fixP
->fx_done
)
11193 /* update old instruction data */
11194 if (target_big_endian
)
11195 insn
= (buf
[0] << 24) | (buf
[1] << 16) | (buf
[2] << 8) | buf
[3];
11197 insn
= (buf
[3] << 24) | (buf
[2] << 16) | (buf
[1] << 8) | buf
[0];
11199 if (*valP
+ 0x20000 <= 0x3ffff)
11201 insn
|= (*valP
>> 2) & 0xffff;
11202 md_number_to_chars ((char *) buf
, insn
, 4);
11204 else if (mips_pic
== NO_PIC
11206 && fixP
->fx_frag
->fr_address
>= text_section
->vma
11207 && (fixP
->fx_frag
->fr_address
11208 < text_section
->vma
+ bfd_get_section_size (text_section
))
11209 && ((insn
& 0xffff0000) == 0x10000000 /* beq $0,$0 */
11210 || (insn
& 0xffff0000) == 0x04010000 /* bgez $0 */
11211 || (insn
& 0xffff0000) == 0x04110000)) /* bgezal $0 */
11213 /* The branch offset is too large. If this is an
11214 unconditional branch, and we are not generating PIC code,
11215 we can convert it to an absolute jump instruction. */
11216 if ((insn
& 0xffff0000) == 0x04110000) /* bgezal $0 */
11217 insn
= 0x0c000000; /* jal */
11219 insn
= 0x08000000; /* j */
11220 fixP
->fx_r_type
= BFD_RELOC_MIPS_JMP
;
11222 fixP
->fx_addsy
= section_symbol (text_section
);
11223 *valP
+= md_pcrel_from (fixP
);
11224 md_number_to_chars ((char *) buf
, insn
, 4);
11228 /* If we got here, we have branch-relaxation disabled,
11229 and there's nothing we can do to fix this instruction
11230 without turning it into a longer sequence. */
11231 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
11232 _("Branch out of range"));
11236 case BFD_RELOC_VTABLE_INHERIT
:
11239 && !S_IS_DEFINED (fixP
->fx_addsy
)
11240 && !S_IS_WEAK (fixP
->fx_addsy
))
11241 S_SET_WEAK (fixP
->fx_addsy
);
11244 case BFD_RELOC_VTABLE_ENTRY
:
11252 /* Remember value for tc_gen_reloc. */
11253 fixP
->fx_addnumber
= *valP
;
11263 name
= input_line_pointer
;
11264 c
= get_symbol_end ();
11265 p
= (symbolS
*) symbol_find_or_make (name
);
11266 *input_line_pointer
= c
;
11270 /* Align the current frag to a given power of two. The MIPS assembler
11271 also automatically adjusts any preceding label. */
11274 mips_align (int to
, int fill
, symbolS
*label
)
11276 mips_emit_delays (FALSE
);
11277 frag_align (to
, fill
, 0);
11278 record_alignment (now_seg
, to
);
11281 assert (S_GET_SEGMENT (label
) == now_seg
);
11282 symbol_set_frag (label
, frag_now
);
11283 S_SET_VALUE (label
, (valueT
) frag_now_fix ());
11287 /* Align to a given power of two. .align 0 turns off the automatic
11288 alignment used by the data creating pseudo-ops. */
11291 s_align (int x ATTRIBUTE_UNUSED
)
11294 register long temp_fill
;
11295 long max_alignment
= 15;
11299 o Note that the assembler pulls down any immediately preceding label
11300 to the aligned address.
11301 o It's not documented but auto alignment is reinstated by
11302 a .align pseudo instruction.
11303 o Note also that after auto alignment is turned off the mips assembler
11304 issues an error on attempt to assemble an improperly aligned data item.
11309 temp
= get_absolute_expression ();
11310 if (temp
> max_alignment
)
11311 as_bad (_("Alignment too large: %d. assumed."), temp
= max_alignment
);
11314 as_warn (_("Alignment negative: 0 assumed."));
11317 if (*input_line_pointer
== ',')
11319 ++input_line_pointer
;
11320 temp_fill
= get_absolute_expression ();
11327 mips_align (temp
, (int) temp_fill
,
11328 insn_labels
!= NULL
? insn_labels
->label
: NULL
);
11335 demand_empty_rest_of_line ();
11339 mips_flush_pending_output (void)
11341 mips_emit_delays (FALSE
);
11342 mips_clear_insn_labels ();
11346 s_change_sec (int sec
)
11351 /* The ELF backend needs to know that we are changing sections, so
11352 that .previous works correctly. We could do something like check
11353 for an obj_section_change_hook macro, but that might be confusing
11354 as it would not be appropriate to use it in the section changing
11355 functions in read.c, since obj-elf.c intercepts those. FIXME:
11356 This should be cleaner, somehow. */
11357 obj_elf_section_change_hook ();
11360 mips_emit_delays (FALSE
);
11370 subseg_set (bss_section
, (subsegT
) get_absolute_expression ());
11371 demand_empty_rest_of_line ();
11375 seg
= subseg_new (RDATA_SECTION_NAME
,
11376 (subsegT
) get_absolute_expression ());
11377 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
11379 bfd_set_section_flags (stdoutput
, seg
, (SEC_ALLOC
| SEC_LOAD
11380 | SEC_READONLY
| SEC_RELOC
11382 if (strcmp (TARGET_OS
, "elf") != 0)
11383 record_alignment (seg
, 4);
11385 demand_empty_rest_of_line ();
11389 seg
= subseg_new (".sdata", (subsegT
) get_absolute_expression ());
11390 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
11392 bfd_set_section_flags (stdoutput
, seg
,
11393 SEC_ALLOC
| SEC_LOAD
| SEC_RELOC
| SEC_DATA
);
11394 if (strcmp (TARGET_OS
, "elf") != 0)
11395 record_alignment (seg
, 4);
11397 demand_empty_rest_of_line ();
11405 s_change_section (int ignore ATTRIBUTE_UNUSED
)
11408 char *section_name
;
11413 int section_entry_size
;
11414 int section_alignment
;
11416 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
11419 section_name
= input_line_pointer
;
11420 c
= get_symbol_end ();
11422 next_c
= *(input_line_pointer
+ 1);
11424 /* Do we have .section Name<,"flags">? */
11425 if (c
!= ',' || (c
== ',' && next_c
== '"'))
11427 /* just after name is now '\0'. */
11428 *input_line_pointer
= c
;
11429 input_line_pointer
= section_name
;
11430 obj_elf_section (ignore
);
11433 input_line_pointer
++;
11435 /* Do we have .section Name<,type><,flag><,entry_size><,alignment> */
11437 section_type
= get_absolute_expression ();
11440 if (*input_line_pointer
++ == ',')
11441 section_flag
= get_absolute_expression ();
11444 if (*input_line_pointer
++ == ',')
11445 section_entry_size
= get_absolute_expression ();
11447 section_entry_size
= 0;
11448 if (*input_line_pointer
++ == ',')
11449 section_alignment
= get_absolute_expression ();
11451 section_alignment
= 0;
11453 section_name
= xstrdup (section_name
);
11455 /* When using the generic form of .section (as implemented by obj-elf.c),
11456 there's no way to set the section type to SHT_MIPS_DWARF. Users have
11457 traditionally had to fall back on the more common @progbits instead.
11459 There's nothing really harmful in this, since bfd will correct
11460 SHT_PROGBITS to SHT_MIPS_DWARF before writing out the file. But it
11461 means that, for backwards compatibiltiy, the special_section entries
11462 for dwarf sections must use SHT_PROGBITS rather than SHT_MIPS_DWARF.
11464 Even so, we shouldn't force users of the MIPS .section syntax to
11465 incorrectly label the sections as SHT_PROGBITS. The best compromise
11466 seems to be to map SHT_MIPS_DWARF to SHT_PROGBITS before calling the
11467 generic type-checking code. */
11468 if (section_type
== SHT_MIPS_DWARF
)
11469 section_type
= SHT_PROGBITS
;
11471 obj_elf_change_section (section_name
, section_type
, section_flag
,
11472 section_entry_size
, 0, 0, 0);
11474 if (now_seg
->name
!= section_name
)
11475 free (section_name
);
11476 #endif /* OBJ_ELF */
11480 mips_enable_auto_align (void)
11486 s_cons (int log_size
)
11490 label
= insn_labels
!= NULL
? insn_labels
->label
: NULL
;
11491 mips_emit_delays (FALSE
);
11492 if (log_size
> 0 && auto_align
)
11493 mips_align (log_size
, 0, label
);
11494 mips_clear_insn_labels ();
11495 cons (1 << log_size
);
11499 s_float_cons (int type
)
11503 label
= insn_labels
!= NULL
? insn_labels
->label
: NULL
;
11505 mips_emit_delays (FALSE
);
11510 mips_align (3, 0, label
);
11512 mips_align (2, 0, label
);
11515 mips_clear_insn_labels ();
11520 /* Handle .globl. We need to override it because on Irix 5 you are
11523 where foo is an undefined symbol, to mean that foo should be
11524 considered to be the address of a function. */
11527 s_mips_globl (int x ATTRIBUTE_UNUSED
)
11534 name
= input_line_pointer
;
11535 c
= get_symbol_end ();
11536 symbolP
= symbol_find_or_make (name
);
11537 *input_line_pointer
= c
;
11538 SKIP_WHITESPACE ();
11540 /* On Irix 5, every global symbol that is not explicitly labelled as
11541 being a function is apparently labelled as being an object. */
11544 if (! is_end_of_line
[(unsigned char) *input_line_pointer
])
11549 secname
= input_line_pointer
;
11550 c
= get_symbol_end ();
11551 sec
= bfd_get_section_by_name (stdoutput
, secname
);
11553 as_bad (_("%s: no such section"), secname
);
11554 *input_line_pointer
= c
;
11556 if (sec
!= NULL
&& (sec
->flags
& SEC_CODE
) != 0)
11557 flag
= BSF_FUNCTION
;
11560 symbol_get_bfdsym (symbolP
)->flags
|= flag
;
11562 S_SET_EXTERNAL (symbolP
);
11563 demand_empty_rest_of_line ();
11567 s_option (int x ATTRIBUTE_UNUSED
)
11572 opt
= input_line_pointer
;
11573 c
= get_symbol_end ();
11577 /* FIXME: What does this mean? */
11579 else if (strncmp (opt
, "pic", 3) == 0)
11583 i
= atoi (opt
+ 3);
11588 mips_pic
= SVR4_PIC
;
11589 mips_abicalls
= TRUE
;
11592 as_bad (_(".option pic%d not supported"), i
);
11594 if (mips_pic
== SVR4_PIC
)
11596 if (g_switch_seen
&& g_switch_value
!= 0)
11597 as_warn (_("-G may not be used with SVR4 PIC code"));
11598 g_switch_value
= 0;
11599 bfd_set_gp_size (stdoutput
, 0);
11603 as_warn (_("Unrecognized option \"%s\""), opt
);
11605 *input_line_pointer
= c
;
11606 demand_empty_rest_of_line ();
11609 /* This structure is used to hold a stack of .set values. */
11611 struct mips_option_stack
11613 struct mips_option_stack
*next
;
11614 struct mips_set_options options
;
11617 static struct mips_option_stack
*mips_opts_stack
;
11619 /* Handle the .set pseudo-op. */
11622 s_mipsset (int x ATTRIBUTE_UNUSED
)
11624 char *name
= input_line_pointer
, ch
;
11626 while (!is_end_of_line
[(unsigned char) *input_line_pointer
])
11627 ++input_line_pointer
;
11628 ch
= *input_line_pointer
;
11629 *input_line_pointer
= '\0';
11631 if (strcmp (name
, "reorder") == 0)
11633 if (mips_opts
.noreorder
&& prev_nop_frag
!= NULL
)
11635 /* If we still have pending nops, we can discard them. The
11636 usual nop handling will insert any that are still
11638 prev_nop_frag
->fr_fix
-= (prev_nop_frag_holds
11639 * (mips_opts
.mips16
? 2 : 4));
11640 prev_nop_frag
= NULL
;
11642 mips_opts
.noreorder
= 0;
11644 else if (strcmp (name
, "noreorder") == 0)
11646 mips_emit_delays (TRUE
);
11647 mips_opts
.noreorder
= 1;
11648 mips_any_noreorder
= 1;
11650 else if (strcmp (name
, "at") == 0)
11652 mips_opts
.noat
= 0;
11654 else if (strcmp (name
, "noat") == 0)
11656 mips_opts
.noat
= 1;
11658 else if (strcmp (name
, "macro") == 0)
11660 mips_opts
.warn_about_macros
= 0;
11662 else if (strcmp (name
, "nomacro") == 0)
11664 if (mips_opts
.noreorder
== 0)
11665 as_bad (_("`noreorder' must be set before `nomacro'"));
11666 mips_opts
.warn_about_macros
= 1;
11668 else if (strcmp (name
, "move") == 0 || strcmp (name
, "novolatile") == 0)
11670 mips_opts
.nomove
= 0;
11672 else if (strcmp (name
, "nomove") == 0 || strcmp (name
, "volatile") == 0)
11674 mips_opts
.nomove
= 1;
11676 else if (strcmp (name
, "bopt") == 0)
11678 mips_opts
.nobopt
= 0;
11680 else if (strcmp (name
, "nobopt") == 0)
11682 mips_opts
.nobopt
= 1;
11684 else if (strcmp (name
, "mips16") == 0
11685 || strcmp (name
, "MIPS-16") == 0)
11686 mips_opts
.mips16
= 1;
11687 else if (strcmp (name
, "nomips16") == 0
11688 || strcmp (name
, "noMIPS-16") == 0)
11689 mips_opts
.mips16
= 0;
11690 else if (strcmp (name
, "mips3d") == 0)
11691 mips_opts
.ase_mips3d
= 1;
11692 else if (strcmp (name
, "nomips3d") == 0)
11693 mips_opts
.ase_mips3d
= 0;
11694 else if (strcmp (name
, "mdmx") == 0)
11695 mips_opts
.ase_mdmx
= 1;
11696 else if (strcmp (name
, "nomdmx") == 0)
11697 mips_opts
.ase_mdmx
= 0;
11698 else if (strncmp (name
, "mips", 4) == 0 || strncmp (name
, "arch=", 5) == 0)
11702 /* Permit the user to change the ISA and architecture on the fly.
11703 Needless to say, misuse can cause serious problems. */
11704 if (strcmp (name
, "mips0") == 0 || strcmp (name
, "arch=default") == 0)
11707 mips_opts
.isa
= file_mips_isa
;
11708 mips_opts
.arch
= file_mips_arch
;
11710 else if (strncmp (name
, "arch=", 5) == 0)
11712 const struct mips_cpu_info
*p
;
11714 p
= mips_parse_cpu("internal use", name
+ 5);
11716 as_bad (_("unknown architecture %s"), name
+ 5);
11719 mips_opts
.arch
= p
->cpu
;
11720 mips_opts
.isa
= p
->isa
;
11723 else if (strncmp (name
, "mips", 4) == 0)
11725 const struct mips_cpu_info
*p
;
11727 p
= mips_parse_cpu("internal use", name
);
11729 as_bad (_("unknown ISA level %s"), name
+ 4);
11732 mips_opts
.arch
= p
->cpu
;
11733 mips_opts
.isa
= p
->isa
;
11737 as_bad (_("unknown ISA or architecture %s"), name
);
11739 switch (mips_opts
.isa
)
11747 mips_opts
.gp32
= 1;
11748 mips_opts
.fp32
= 1;
11755 mips_opts
.gp32
= 0;
11756 mips_opts
.fp32
= 0;
11759 as_bad (_("unknown ISA level %s"), name
+ 4);
11764 mips_opts
.gp32
= file_mips_gp32
;
11765 mips_opts
.fp32
= file_mips_fp32
;
11768 else if (strcmp (name
, "autoextend") == 0)
11769 mips_opts
.noautoextend
= 0;
11770 else if (strcmp (name
, "noautoextend") == 0)
11771 mips_opts
.noautoextend
= 1;
11772 else if (strcmp (name
, "push") == 0)
11774 struct mips_option_stack
*s
;
11776 s
= (struct mips_option_stack
*) xmalloc (sizeof *s
);
11777 s
->next
= mips_opts_stack
;
11778 s
->options
= mips_opts
;
11779 mips_opts_stack
= s
;
11781 else if (strcmp (name
, "pop") == 0)
11783 struct mips_option_stack
*s
;
11785 s
= mips_opts_stack
;
11787 as_bad (_(".set pop with no .set push"));
11790 /* If we're changing the reorder mode we need to handle
11791 delay slots correctly. */
11792 if (s
->options
.noreorder
&& ! mips_opts
.noreorder
)
11793 mips_emit_delays (TRUE
);
11794 else if (! s
->options
.noreorder
&& mips_opts
.noreorder
)
11796 if (prev_nop_frag
!= NULL
)
11798 prev_nop_frag
->fr_fix
-= (prev_nop_frag_holds
11799 * (mips_opts
.mips16
? 2 : 4));
11800 prev_nop_frag
= NULL
;
11804 mips_opts
= s
->options
;
11805 mips_opts_stack
= s
->next
;
11809 else if (strcmp (name
, "sym32") == 0)
11810 mips_opts
.sym32
= TRUE
;
11811 else if (strcmp (name
, "nosym32") == 0)
11812 mips_opts
.sym32
= FALSE
;
11815 as_warn (_("Tried to set unrecognized symbol: %s\n"), name
);
11817 *input_line_pointer
= ch
;
11818 demand_empty_rest_of_line ();
11821 /* Handle the .abicalls pseudo-op. I believe this is equivalent to
11822 .option pic2. It means to generate SVR4 PIC calls. */
11825 s_abicalls (int ignore ATTRIBUTE_UNUSED
)
11827 mips_pic
= SVR4_PIC
;
11828 mips_abicalls
= TRUE
;
11830 if (g_switch_seen
&& g_switch_value
!= 0)
11831 as_warn (_("-G may not be used with SVR4 PIC code"));
11832 g_switch_value
= 0;
11834 bfd_set_gp_size (stdoutput
, 0);
11835 demand_empty_rest_of_line ();
11838 /* Handle the .cpload pseudo-op. This is used when generating SVR4
11839 PIC code. It sets the $gp register for the function based on the
11840 function address, which is in the register named in the argument.
11841 This uses a relocation against _gp_disp, which is handled specially
11842 by the linker. The result is:
11843 lui $gp,%hi(_gp_disp)
11844 addiu $gp,$gp,%lo(_gp_disp)
11845 addu $gp,$gp,.cpload argument
11846 The .cpload argument is normally $25 == $t9.
11848 The -mno-shared option changes this to:
11849 lui $gp,%hi(__gnu_local_gp)
11850 addiu $gp,$gp,%lo(__gnu_local_gp)
11851 and the argument is ignored. This saves an instruction, but the
11852 resulting code is not position independent; it uses an absolute
11853 address for __gnu_local_gp. Thus code assembled with -mno-shared
11854 can go into an ordinary executable, but not into a shared library. */
11857 s_cpload (int ignore ATTRIBUTE_UNUSED
)
11863 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
11864 .cpload is ignored. */
11865 if (mips_pic
!= SVR4_PIC
|| HAVE_NEWABI
)
11871 /* .cpload should be in a .set noreorder section. */
11872 if (mips_opts
.noreorder
== 0)
11873 as_warn (_(".cpload not in noreorder section"));
11875 reg
= tc_get_register (0);
11877 /* If we need to produce a 64-bit address, we are better off using
11878 the default instruction sequence. */
11879 in_shared
= mips_in_shared
|| HAVE_64BIT_SYMBOLS
;
11881 ex
.X_op
= O_symbol
;
11882 ex
.X_add_symbol
= symbol_find_or_make (in_shared
? "_gp_disp" :
11884 ex
.X_op_symbol
= NULL
;
11885 ex
.X_add_number
= 0;
11887 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
11888 symbol_get_bfdsym (ex
.X_add_symbol
)->flags
|= BSF_OBJECT
;
11891 macro_build_lui (&ex
, mips_gp_register
);
11892 macro_build (&ex
, "addiu", "t,r,j", mips_gp_register
,
11893 mips_gp_register
, BFD_RELOC_LO16
);
11895 macro_build (NULL
, "addu", "d,v,t", mips_gp_register
,
11896 mips_gp_register
, reg
);
11899 demand_empty_rest_of_line ();
11902 /* Handle the .cpsetup pseudo-op defined for NewABI PIC code. The syntax is:
11903 .cpsetup $reg1, offset|$reg2, label
11905 If offset is given, this results in:
11906 sd $gp, offset($sp)
11907 lui $gp, %hi(%neg(%gp_rel(label)))
11908 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
11909 daddu $gp, $gp, $reg1
11911 If $reg2 is given, this results in:
11912 daddu $reg2, $gp, $0
11913 lui $gp, %hi(%neg(%gp_rel(label)))
11914 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
11915 daddu $gp, $gp, $reg1
11916 $reg1 is normally $25 == $t9.
11918 The -mno-shared option replaces the last three instructions with
11920 addiu $gp,$gp,%lo(_gp)
11924 s_cpsetup (int ignore ATTRIBUTE_UNUSED
)
11926 expressionS ex_off
;
11927 expressionS ex_sym
;
11930 /* If we are not generating SVR4 PIC code, .cpsetup is ignored.
11931 We also need NewABI support. */
11932 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
11938 reg1
= tc_get_register (0);
11939 SKIP_WHITESPACE ();
11940 if (*input_line_pointer
!= ',')
11942 as_bad (_("missing argument separator ',' for .cpsetup"));
11946 ++input_line_pointer
;
11947 SKIP_WHITESPACE ();
11948 if (*input_line_pointer
== '$')
11950 mips_cpreturn_register
= tc_get_register (0);
11951 mips_cpreturn_offset
= -1;
11955 mips_cpreturn_offset
= get_absolute_expression ();
11956 mips_cpreturn_register
= -1;
11958 SKIP_WHITESPACE ();
11959 if (*input_line_pointer
!= ',')
11961 as_bad (_("missing argument separator ',' for .cpsetup"));
11965 ++input_line_pointer
;
11966 SKIP_WHITESPACE ();
11967 expression (&ex_sym
);
11970 if (mips_cpreturn_register
== -1)
11972 ex_off
.X_op
= O_constant
;
11973 ex_off
.X_add_symbol
= NULL
;
11974 ex_off
.X_op_symbol
= NULL
;
11975 ex_off
.X_add_number
= mips_cpreturn_offset
;
11977 macro_build (&ex_off
, "sd", "t,o(b)", mips_gp_register
,
11978 BFD_RELOC_LO16
, SP
);
11981 macro_build (NULL
, "daddu", "d,v,t", mips_cpreturn_register
,
11982 mips_gp_register
, 0);
11984 if (mips_in_shared
|| HAVE_64BIT_SYMBOLS
)
11986 macro_build (&ex_sym
, "lui", "t,u", mips_gp_register
,
11987 -1, BFD_RELOC_GPREL16
, BFD_RELOC_MIPS_SUB
,
11990 macro_build (&ex_sym
, "addiu", "t,r,j", mips_gp_register
,
11991 mips_gp_register
, -1, BFD_RELOC_GPREL16
,
11992 BFD_RELOC_MIPS_SUB
, BFD_RELOC_LO16
);
11994 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", mips_gp_register
,
11995 mips_gp_register
, reg1
);
12001 ex
.X_op
= O_symbol
;
12002 ex
.X_add_symbol
= symbol_find_or_make ("_gp");
12003 ex
.X_op_symbol
= NULL
;
12004 ex
.X_add_number
= 0;
12006 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
12007 symbol_get_bfdsym (ex
.X_add_symbol
)->flags
|= BSF_OBJECT
;
12009 macro_build_lui (&ex
, mips_gp_register
);
12010 macro_build (&ex
, "addiu", "t,r,j", mips_gp_register
,
12011 mips_gp_register
, BFD_RELOC_LO16
);
12016 demand_empty_rest_of_line ();
12020 s_cplocal (int ignore ATTRIBUTE_UNUSED
)
12022 /* If we are not generating SVR4 PIC code, or if this is not NewABI code,
12023 .cplocal is ignored. */
12024 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
12030 mips_gp_register
= tc_get_register (0);
12031 demand_empty_rest_of_line ();
12034 /* Handle the .cprestore pseudo-op. This stores $gp into a given
12035 offset from $sp. The offset is remembered, and after making a PIC
12036 call $gp is restored from that location. */
12039 s_cprestore (int ignore ATTRIBUTE_UNUSED
)
12043 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
12044 .cprestore is ignored. */
12045 if (mips_pic
!= SVR4_PIC
|| HAVE_NEWABI
)
12051 mips_cprestore_offset
= get_absolute_expression ();
12052 mips_cprestore_valid
= 1;
12054 ex
.X_op
= O_constant
;
12055 ex
.X_add_symbol
= NULL
;
12056 ex
.X_op_symbol
= NULL
;
12057 ex
.X_add_number
= mips_cprestore_offset
;
12060 macro_build_ldst_constoffset (&ex
, ADDRESS_STORE_INSN
, mips_gp_register
,
12061 SP
, HAVE_64BIT_ADDRESSES
);
12064 demand_empty_rest_of_line ();
12067 /* Handle the .cpreturn pseudo-op defined for NewABI PIC code. If an offset
12068 was given in the preceding .cpsetup, it results in:
12069 ld $gp, offset($sp)
12071 If a register $reg2 was given there, it results in:
12072 daddu $gp, $reg2, $0
12075 s_cpreturn (int ignore ATTRIBUTE_UNUSED
)
12079 /* If we are not generating SVR4 PIC code, .cpreturn is ignored.
12080 We also need NewABI support. */
12081 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
12088 if (mips_cpreturn_register
== -1)
12090 ex
.X_op
= O_constant
;
12091 ex
.X_add_symbol
= NULL
;
12092 ex
.X_op_symbol
= NULL
;
12093 ex
.X_add_number
= mips_cpreturn_offset
;
12095 macro_build (&ex
, "ld", "t,o(b)", mips_gp_register
, BFD_RELOC_LO16
, SP
);
12098 macro_build (NULL
, "daddu", "d,v,t", mips_gp_register
,
12099 mips_cpreturn_register
, 0);
12102 demand_empty_rest_of_line ();
12105 /* Handle the .gpvalue pseudo-op. This is used when generating NewABI PIC
12106 code. It sets the offset to use in gp_rel relocations. */
12109 s_gpvalue (int ignore ATTRIBUTE_UNUSED
)
12111 /* If we are not generating SVR4 PIC code, .gpvalue is ignored.
12112 We also need NewABI support. */
12113 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
12119 mips_gprel_offset
= get_absolute_expression ();
12121 demand_empty_rest_of_line ();
12124 /* Handle the .gpword pseudo-op. This is used when generating PIC
12125 code. It generates a 32 bit GP relative reloc. */
12128 s_gpword (int ignore ATTRIBUTE_UNUSED
)
12134 /* When not generating PIC code, this is treated as .word. */
12135 if (mips_pic
!= SVR4_PIC
)
12141 label
= insn_labels
!= NULL
? insn_labels
->label
: NULL
;
12142 mips_emit_delays (TRUE
);
12144 mips_align (2, 0, label
);
12145 mips_clear_insn_labels ();
12149 if (ex
.X_op
!= O_symbol
|| ex
.X_add_number
!= 0)
12151 as_bad (_("Unsupported use of .gpword"));
12152 ignore_rest_of_line ();
12156 md_number_to_chars (p
, 0, 4);
12157 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 4, &ex
, FALSE
,
12158 BFD_RELOC_GPREL32
);
12160 demand_empty_rest_of_line ();
12164 s_gpdword (int ignore ATTRIBUTE_UNUSED
)
12170 /* When not generating PIC code, this is treated as .dword. */
12171 if (mips_pic
!= SVR4_PIC
)
12177 label
= insn_labels
!= NULL
? insn_labels
->label
: NULL
;
12178 mips_emit_delays (TRUE
);
12180 mips_align (3, 0, label
);
12181 mips_clear_insn_labels ();
12185 if (ex
.X_op
!= O_symbol
|| ex
.X_add_number
!= 0)
12187 as_bad (_("Unsupported use of .gpdword"));
12188 ignore_rest_of_line ();
12192 md_number_to_chars (p
, 0, 8);
12193 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 4, &ex
, FALSE
,
12194 BFD_RELOC_GPREL32
)->fx_tcbit
= 1;
12196 /* GPREL32 composed with 64 gives a 64-bit GP offset. */
12197 fix_new (frag_now
, p
- frag_now
->fr_literal
, 8, NULL
, 0,
12198 FALSE
, BFD_RELOC_64
)->fx_tcbit
= 1;
12200 demand_empty_rest_of_line ();
12203 /* Handle the .cpadd pseudo-op. This is used when dealing with switch
12204 tables in SVR4 PIC code. */
12207 s_cpadd (int ignore ATTRIBUTE_UNUSED
)
12211 /* This is ignored when not generating SVR4 PIC code. */
12212 if (mips_pic
!= SVR4_PIC
)
12218 /* Add $gp to the register named as an argument. */
12220 reg
= tc_get_register (0);
12221 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", reg
, reg
, mips_gp_register
);
12224 demand_empty_rest_of_line ();
12227 /* Handle the .insn pseudo-op. This marks instruction labels in
12228 mips16 mode. This permits the linker to handle them specially,
12229 such as generating jalx instructions when needed. We also make
12230 them odd for the duration of the assembly, in order to generate the
12231 right sort of code. We will make them even in the adjust_symtab
12232 routine, while leaving them marked. This is convenient for the
12233 debugger and the disassembler. The linker knows to make them odd
12237 s_insn (int ignore ATTRIBUTE_UNUSED
)
12239 mips16_mark_labels ();
12241 demand_empty_rest_of_line ();
12244 /* Handle a .stabn directive. We need these in order to mark a label
12245 as being a mips16 text label correctly. Sometimes the compiler
12246 will emit a label, followed by a .stabn, and then switch sections.
12247 If the label and .stabn are in mips16 mode, then the label is
12248 really a mips16 text label. */
12251 s_mips_stab (int type
)
12254 mips16_mark_labels ();
12259 /* Handle the .weakext pseudo-op as defined in Kane and Heinrich.
12263 s_mips_weakext (int ignore ATTRIBUTE_UNUSED
)
12270 name
= input_line_pointer
;
12271 c
= get_symbol_end ();
12272 symbolP
= symbol_find_or_make (name
);
12273 S_SET_WEAK (symbolP
);
12274 *input_line_pointer
= c
;
12276 SKIP_WHITESPACE ();
12278 if (! is_end_of_line
[(unsigned char) *input_line_pointer
])
12280 if (S_IS_DEFINED (symbolP
))
12282 as_bad ("ignoring attempt to redefine symbol %s",
12283 S_GET_NAME (symbolP
));
12284 ignore_rest_of_line ();
12288 if (*input_line_pointer
== ',')
12290 ++input_line_pointer
;
12291 SKIP_WHITESPACE ();
12295 if (exp
.X_op
!= O_symbol
)
12297 as_bad ("bad .weakext directive");
12298 ignore_rest_of_line ();
12301 symbol_set_value_expression (symbolP
, &exp
);
12304 demand_empty_rest_of_line ();
12307 /* Parse a register string into a number. Called from the ECOFF code
12308 to parse .frame. The argument is non-zero if this is the frame
12309 register, so that we can record it in mips_frame_reg. */
12312 tc_get_register (int frame
)
12316 SKIP_WHITESPACE ();
12317 if (*input_line_pointer
++ != '$')
12319 as_warn (_("expected `$'"));
12322 else if (ISDIGIT (*input_line_pointer
))
12324 reg
= get_absolute_expression ();
12325 if (reg
< 0 || reg
>= 32)
12327 as_warn (_("Bad register number"));
12333 if (strncmp (input_line_pointer
, "ra", 2) == 0)
12336 input_line_pointer
+= 2;
12338 else if (strncmp (input_line_pointer
, "fp", 2) == 0)
12341 input_line_pointer
+= 2;
12343 else if (strncmp (input_line_pointer
, "sp", 2) == 0)
12346 input_line_pointer
+= 2;
12348 else if (strncmp (input_line_pointer
, "gp", 2) == 0)
12351 input_line_pointer
+= 2;
12353 else if (strncmp (input_line_pointer
, "at", 2) == 0)
12356 input_line_pointer
+= 2;
12358 else if (strncmp (input_line_pointer
, "kt0", 3) == 0)
12361 input_line_pointer
+= 3;
12363 else if (strncmp (input_line_pointer
, "kt1", 3) == 0)
12366 input_line_pointer
+= 3;
12368 else if (strncmp (input_line_pointer
, "zero", 4) == 0)
12371 input_line_pointer
+= 4;
12375 as_warn (_("Unrecognized register name"));
12377 while (ISALNUM(*input_line_pointer
))
12378 input_line_pointer
++;
12383 mips_frame_reg
= reg
!= 0 ? reg
: SP
;
12384 mips_frame_reg_valid
= 1;
12385 mips_cprestore_valid
= 0;
12391 md_section_align (asection
*seg
, valueT addr
)
12393 int align
= bfd_get_section_alignment (stdoutput
, seg
);
12396 /* We don't need to align ELF sections to the full alignment.
12397 However, Irix 5 may prefer that we align them at least to a 16
12398 byte boundary. We don't bother to align the sections if we are
12399 targeted for an embedded system. */
12400 if (strcmp (TARGET_OS
, "elf") == 0)
12406 return ((addr
+ (1 << align
) - 1) & (-1 << align
));
12409 /* Utility routine, called from above as well. If called while the
12410 input file is still being read, it's only an approximation. (For
12411 example, a symbol may later become defined which appeared to be
12412 undefined earlier.) */
12415 nopic_need_relax (symbolS
*sym
, int before_relaxing
)
12420 if (g_switch_value
> 0)
12422 const char *symname
;
12425 /* Find out whether this symbol can be referenced off the $gp
12426 register. It can be if it is smaller than the -G size or if
12427 it is in the .sdata or .sbss section. Certain symbols can
12428 not be referenced off the $gp, although it appears as though
12430 symname
= S_GET_NAME (sym
);
12431 if (symname
!= (const char *) NULL
12432 && (strcmp (symname
, "eprol") == 0
12433 || strcmp (symname
, "etext") == 0
12434 || strcmp (symname
, "_gp") == 0
12435 || strcmp (symname
, "edata") == 0
12436 || strcmp (symname
, "_fbss") == 0
12437 || strcmp (symname
, "_fdata") == 0
12438 || strcmp (symname
, "_ftext") == 0
12439 || strcmp (symname
, "end") == 0
12440 || strcmp (symname
, "_gp_disp") == 0))
12442 else if ((! S_IS_DEFINED (sym
) || S_IS_COMMON (sym
))
12444 #ifndef NO_ECOFF_DEBUGGING
12445 || (symbol_get_obj (sym
)->ecoff_extern_size
!= 0
12446 && (symbol_get_obj (sym
)->ecoff_extern_size
12447 <= g_switch_value
))
12449 /* We must defer this decision until after the whole
12450 file has been read, since there might be a .extern
12451 after the first use of this symbol. */
12452 || (before_relaxing
12453 #ifndef NO_ECOFF_DEBUGGING
12454 && symbol_get_obj (sym
)->ecoff_extern_size
== 0
12456 && S_GET_VALUE (sym
) == 0)
12457 || (S_GET_VALUE (sym
) != 0
12458 && S_GET_VALUE (sym
) <= g_switch_value
)))
12462 const char *segname
;
12464 segname
= segment_name (S_GET_SEGMENT (sym
));
12465 assert (strcmp (segname
, ".lit8") != 0
12466 && strcmp (segname
, ".lit4") != 0);
12467 change
= (strcmp (segname
, ".sdata") != 0
12468 && strcmp (segname
, ".sbss") != 0
12469 && strncmp (segname
, ".sdata.", 7) != 0
12470 && strncmp (segname
, ".gnu.linkonce.s.", 16) != 0);
12475 /* We are not optimizing for the $gp register. */
12480 /* Return true if the given symbol should be considered local for SVR4 PIC. */
12483 pic_need_relax (symbolS
*sym
, asection
*segtype
)
12486 bfd_boolean linkonce
;
12488 /* Handle the case of a symbol equated to another symbol. */
12489 while (symbol_equated_reloc_p (sym
))
12493 /* It's possible to get a loop here in a badly written
12495 n
= symbol_get_value_expression (sym
)->X_add_symbol
;
12501 symsec
= S_GET_SEGMENT (sym
);
12503 /* duplicate the test for LINK_ONCE sections as in adjust_reloc_syms */
12505 if (symsec
!= segtype
&& ! S_IS_LOCAL (sym
))
12507 if ((bfd_get_section_flags (stdoutput
, symsec
) & SEC_LINK_ONCE
)
12511 /* The GNU toolchain uses an extension for ELF: a section
12512 beginning with the magic string .gnu.linkonce is a linkonce
12514 if (strncmp (segment_name (symsec
), ".gnu.linkonce",
12515 sizeof ".gnu.linkonce" - 1) == 0)
12519 /* This must duplicate the test in adjust_reloc_syms. */
12520 return (symsec
!= &bfd_und_section
12521 && symsec
!= &bfd_abs_section
12522 && ! bfd_is_com_section (symsec
)
12525 /* A global or weak symbol is treated as external. */
12526 && (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
12527 || (! S_IS_WEAK (sym
) && ! S_IS_EXTERNAL (sym
)))
12533 /* Given a mips16 variant frag FRAGP, return non-zero if it needs an
12534 extended opcode. SEC is the section the frag is in. */
12537 mips16_extended_frag (fragS
*fragp
, asection
*sec
, long stretch
)
12540 register const struct mips16_immed_operand
*op
;
12542 int mintiny
, maxtiny
;
12546 if (RELAX_MIPS16_USER_SMALL (fragp
->fr_subtype
))
12548 if (RELAX_MIPS16_USER_EXT (fragp
->fr_subtype
))
12551 type
= RELAX_MIPS16_TYPE (fragp
->fr_subtype
);
12552 op
= mips16_immed_operands
;
12553 while (op
->type
!= type
)
12556 assert (op
< mips16_immed_operands
+ MIPS16_NUM_IMMED
);
12561 if (type
== '<' || type
== '>' || type
== '[' || type
== ']')
12564 maxtiny
= 1 << op
->nbits
;
12569 maxtiny
= (1 << op
->nbits
) - 1;
12574 mintiny
= - (1 << (op
->nbits
- 1));
12575 maxtiny
= (1 << (op
->nbits
- 1)) - 1;
12578 sym_frag
= symbol_get_frag (fragp
->fr_symbol
);
12579 val
= S_GET_VALUE (fragp
->fr_symbol
);
12580 symsec
= S_GET_SEGMENT (fragp
->fr_symbol
);
12586 /* We won't have the section when we are called from
12587 mips_relax_frag. However, we will always have been called
12588 from md_estimate_size_before_relax first. If this is a
12589 branch to a different section, we mark it as such. If SEC is
12590 NULL, and the frag is not marked, then it must be a branch to
12591 the same section. */
12594 if (RELAX_MIPS16_LONG_BRANCH (fragp
->fr_subtype
))
12599 /* Must have been called from md_estimate_size_before_relax. */
12602 fragp
->fr_subtype
=
12603 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
12605 /* FIXME: We should support this, and let the linker
12606 catch branches and loads that are out of range. */
12607 as_bad_where (fragp
->fr_file
, fragp
->fr_line
,
12608 _("unsupported PC relative reference to different section"));
12612 if (fragp
!= sym_frag
&& sym_frag
->fr_address
== 0)
12613 /* Assume non-extended on the first relaxation pass.
12614 The address we have calculated will be bogus if this is
12615 a forward branch to another frag, as the forward frag
12616 will have fr_address == 0. */
12620 /* In this case, we know for sure that the symbol fragment is in
12621 the same section. If the relax_marker of the symbol fragment
12622 differs from the relax_marker of this fragment, we have not
12623 yet adjusted the symbol fragment fr_address. We want to add
12624 in STRETCH in order to get a better estimate of the address.
12625 This particularly matters because of the shift bits. */
12627 && sym_frag
->relax_marker
!= fragp
->relax_marker
)
12631 /* Adjust stretch for any alignment frag. Note that if have
12632 been expanding the earlier code, the symbol may be
12633 defined in what appears to be an earlier frag. FIXME:
12634 This doesn't handle the fr_subtype field, which specifies
12635 a maximum number of bytes to skip when doing an
12637 for (f
= fragp
; f
!= NULL
&& f
!= sym_frag
; f
= f
->fr_next
)
12639 if (f
->fr_type
== rs_align
|| f
->fr_type
== rs_align_code
)
12642 stretch
= - ((- stretch
)
12643 & ~ ((1 << (int) f
->fr_offset
) - 1));
12645 stretch
&= ~ ((1 << (int) f
->fr_offset
) - 1);
12654 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
12656 /* The base address rules are complicated. The base address of
12657 a branch is the following instruction. The base address of a
12658 PC relative load or add is the instruction itself, but if it
12659 is in a delay slot (in which case it can not be extended) use
12660 the address of the instruction whose delay slot it is in. */
12661 if (type
== 'p' || type
== 'q')
12665 /* If we are currently assuming that this frag should be
12666 extended, then, the current address is two bytes
12668 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
12671 /* Ignore the low bit in the target, since it will be set
12672 for a text label. */
12673 if ((val
& 1) != 0)
12676 else if (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
))
12678 else if (RELAX_MIPS16_DSLOT (fragp
->fr_subtype
))
12681 val
-= addr
& ~ ((1 << op
->shift
) - 1);
12683 /* Branch offsets have an implicit 0 in the lowest bit. */
12684 if (type
== 'p' || type
== 'q')
12687 /* If any of the shifted bits are set, we must use an extended
12688 opcode. If the address depends on the size of this
12689 instruction, this can lead to a loop, so we arrange to always
12690 use an extended opcode. We only check this when we are in
12691 the main relaxation loop, when SEC is NULL. */
12692 if ((val
& ((1 << op
->shift
) - 1)) != 0 && sec
== NULL
)
12694 fragp
->fr_subtype
=
12695 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
12699 /* If we are about to mark a frag as extended because the value
12700 is precisely maxtiny + 1, then there is a chance of an
12701 infinite loop as in the following code:
12706 In this case when the la is extended, foo is 0x3fc bytes
12707 away, so the la can be shrunk, but then foo is 0x400 away, so
12708 the la must be extended. To avoid this loop, we mark the
12709 frag as extended if it was small, and is about to become
12710 extended with a value of maxtiny + 1. */
12711 if (val
== ((maxtiny
+ 1) << op
->shift
)
12712 && ! RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
)
12715 fragp
->fr_subtype
=
12716 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
12720 else if (symsec
!= absolute_section
&& sec
!= NULL
)
12721 as_bad_where (fragp
->fr_file
, fragp
->fr_line
, _("unsupported relocation"));
12723 if ((val
& ((1 << op
->shift
) - 1)) != 0
12724 || val
< (mintiny
<< op
->shift
)
12725 || val
> (maxtiny
<< op
->shift
))
12731 /* Compute the length of a branch sequence, and adjust the
12732 RELAX_BRANCH_TOOFAR bit accordingly. If FRAGP is NULL, the
12733 worst-case length is computed, with UPDATE being used to indicate
12734 whether an unconditional (-1), branch-likely (+1) or regular (0)
12735 branch is to be computed. */
12737 relaxed_branch_length (fragS
*fragp
, asection
*sec
, int update
)
12739 bfd_boolean toofar
;
12743 && S_IS_DEFINED (fragp
->fr_symbol
)
12744 && sec
== S_GET_SEGMENT (fragp
->fr_symbol
))
12749 val
= S_GET_VALUE (fragp
->fr_symbol
) + fragp
->fr_offset
;
12751 addr
= fragp
->fr_address
+ fragp
->fr_fix
+ 4;
12755 toofar
= val
< - (0x8000 << 2) || val
>= (0x8000 << 2);
12758 /* If the symbol is not defined or it's in a different segment,
12759 assume the user knows what's going on and emit a short
12765 if (fragp
&& update
&& toofar
!= RELAX_BRANCH_TOOFAR (fragp
->fr_subtype
))
12767 = RELAX_BRANCH_ENCODE (RELAX_BRANCH_UNCOND (fragp
->fr_subtype
),
12768 RELAX_BRANCH_LIKELY (fragp
->fr_subtype
),
12769 RELAX_BRANCH_LINK (fragp
->fr_subtype
),
12775 if (fragp
? RELAX_BRANCH_LIKELY (fragp
->fr_subtype
) : (update
> 0))
12778 if (mips_pic
!= NO_PIC
)
12780 /* Additional space for PIC loading of target address. */
12782 if (mips_opts
.isa
== ISA_MIPS1
)
12783 /* Additional space for $at-stabilizing nop. */
12787 /* If branch is conditional. */
12788 if (fragp
? !RELAX_BRANCH_UNCOND (fragp
->fr_subtype
) : (update
>= 0))
12795 /* Estimate the size of a frag before relaxing. Unless this is the
12796 mips16, we are not really relaxing here, and the final size is
12797 encoded in the subtype information. For the mips16, we have to
12798 decide whether we are using an extended opcode or not. */
12801 md_estimate_size_before_relax (fragS
*fragp
, asection
*segtype
)
12805 if (RELAX_BRANCH_P (fragp
->fr_subtype
))
12808 fragp
->fr_var
= relaxed_branch_length (fragp
, segtype
, FALSE
);
12810 return fragp
->fr_var
;
12813 if (RELAX_MIPS16_P (fragp
->fr_subtype
))
12814 /* We don't want to modify the EXTENDED bit here; it might get us
12815 into infinite loops. We change it only in mips_relax_frag(). */
12816 return (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
) ? 4 : 2);
12818 if (mips_pic
== NO_PIC
)
12819 change
= nopic_need_relax (fragp
->fr_symbol
, 0);
12820 else if (mips_pic
== SVR4_PIC
)
12821 change
= pic_need_relax (fragp
->fr_symbol
, segtype
);
12827 fragp
->fr_subtype
|= RELAX_USE_SECOND
;
12828 return -RELAX_FIRST (fragp
->fr_subtype
);
12831 return -RELAX_SECOND (fragp
->fr_subtype
);
12834 /* This is called to see whether a reloc against a defined symbol
12835 should be converted into a reloc against a section. */
12838 mips_fix_adjustable (fixS
*fixp
)
12840 /* Don't adjust MIPS16 jump relocations, so we don't have to worry
12841 about the format of the offset in the .o file. */
12842 if (fixp
->fx_r_type
== BFD_RELOC_MIPS16_JMP
)
12845 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
12846 || fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
12849 if (fixp
->fx_addsy
== NULL
)
12852 /* If symbol SYM is in a mergeable section, relocations of the form
12853 SYM + 0 can usually be made section-relative. The mergeable data
12854 is then identified by the section offset rather than by the symbol.
12856 However, if we're generating REL LO16 relocations, the offset is split
12857 between the LO16 and parterning high part relocation. The linker will
12858 need to recalculate the complete offset in order to correctly identify
12861 The linker has traditionally not looked for the parterning high part
12862 relocation, and has thus allowed orphaned R_MIPS_LO16 relocations to be
12863 placed anywhere. Rather than break backwards compatibility by changing
12864 this, it seems better not to force the issue, and instead keep the
12865 original symbol. This will work with either linker behavior. */
12866 if ((fixp
->fx_r_type
== BFD_RELOC_LO16
|| reloc_needs_lo_p (fixp
->fx_r_type
))
12867 && HAVE_IN_PLACE_ADDENDS
12868 && (S_GET_SEGMENT (fixp
->fx_addsy
)->flags
& SEC_MERGE
) != 0)
12872 /* Don't adjust relocations against mips16 symbols, so that the linker
12873 can find them if it needs to set up a stub. */
12874 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
12875 && S_GET_OTHER (fixp
->fx_addsy
) == STO_MIPS16
12876 && fixp
->fx_subsy
== NULL
)
12883 /* Translate internal representation of relocation info to BFD target
12887 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
, fixS
*fixp
)
12889 static arelent
*retval
[4];
12891 bfd_reloc_code_real_type code
;
12893 memset (retval
, 0, sizeof(retval
));
12894 reloc
= retval
[0] = (arelent
*) xcalloc (1, sizeof (arelent
));
12895 reloc
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
12896 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
12897 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
12899 assert (! fixp
->fx_pcrel
);
12900 reloc
->addend
= fixp
->fx_addnumber
;
12902 /* Since the old MIPS ELF ABI uses Rel instead of Rela, encode the vtable
12903 entry to be used in the relocation's section offset. */
12904 if (! HAVE_NEWABI
&& fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
12906 reloc
->address
= reloc
->addend
;
12910 code
= fixp
->fx_r_type
;
12912 /* To support a PC relative reloc, we used a Cygnus extension.
12913 We check for that here to make sure that we don't let such a
12914 reloc escape normally. (FIXME: This was formerly used by
12915 embedded-PIC support, but is now used by branch handling in
12916 general. That probably should be fixed.) */
12917 if ((OUTPUT_FLAVOR
== bfd_target_ecoff_flavour
12918 || OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
12919 && code
== BFD_RELOC_16_PCREL_S2
)
12920 reloc
->howto
= NULL
;
12922 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
12924 if (reloc
->howto
== NULL
)
12926 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
12927 _("Can not represent %s relocation in this object file format"),
12928 bfd_get_reloc_code_name (code
));
12935 /* Relax a machine dependent frag. This returns the amount by which
12936 the current size of the frag should change. */
12939 mips_relax_frag (asection
*sec
, fragS
*fragp
, long stretch
)
12941 if (RELAX_BRANCH_P (fragp
->fr_subtype
))
12943 offsetT old_var
= fragp
->fr_var
;
12945 fragp
->fr_var
= relaxed_branch_length (fragp
, sec
, TRUE
);
12947 return fragp
->fr_var
- old_var
;
12950 if (! RELAX_MIPS16_P (fragp
->fr_subtype
))
12953 if (mips16_extended_frag (fragp
, NULL
, stretch
))
12955 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
12957 fragp
->fr_subtype
= RELAX_MIPS16_MARK_EXTENDED (fragp
->fr_subtype
);
12962 if (! RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
12964 fragp
->fr_subtype
= RELAX_MIPS16_CLEAR_EXTENDED (fragp
->fr_subtype
);
12971 /* Convert a machine dependent frag. */
12974 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
, segT asec
, fragS
*fragp
)
12976 if (RELAX_BRANCH_P (fragp
->fr_subtype
))
12979 unsigned long insn
;
12983 buf
= (bfd_byte
*)fragp
->fr_literal
+ fragp
->fr_fix
;
12985 if (target_big_endian
)
12986 insn
= bfd_getb32 (buf
);
12988 insn
= bfd_getl32 (buf
);
12990 if (!RELAX_BRANCH_TOOFAR (fragp
->fr_subtype
))
12992 /* We generate a fixup instead of applying it right now
12993 because, if there are linker relaxations, we're going to
12994 need the relocations. */
12995 exp
.X_op
= O_symbol
;
12996 exp
.X_add_symbol
= fragp
->fr_symbol
;
12997 exp
.X_add_number
= fragp
->fr_offset
;
12999 fixp
= fix_new_exp (fragp
, buf
- (bfd_byte
*)fragp
->fr_literal
,
13001 BFD_RELOC_16_PCREL_S2
);
13002 fixp
->fx_file
= fragp
->fr_file
;
13003 fixp
->fx_line
= fragp
->fr_line
;
13005 md_number_to_chars ((char *) buf
, insn
, 4);
13012 as_warn_where (fragp
->fr_file
, fragp
->fr_line
,
13013 _("relaxed out-of-range branch into a jump"));
13015 if (RELAX_BRANCH_UNCOND (fragp
->fr_subtype
))
13018 if (!RELAX_BRANCH_LIKELY (fragp
->fr_subtype
))
13020 /* Reverse the branch. */
13021 switch ((insn
>> 28) & 0xf)
13024 /* bc[0-3][tf]l? and bc1any[24][ft] instructions can
13025 have the condition reversed by tweaking a single
13026 bit, and their opcodes all have 0x4???????. */
13027 assert ((insn
& 0xf1000000) == 0x41000000);
13028 insn
^= 0x00010000;
13032 /* bltz 0x04000000 bgez 0x04010000
13033 bltzal 0x04100000 bgezal 0x04110000 */
13034 assert ((insn
& 0xfc0e0000) == 0x04000000);
13035 insn
^= 0x00010000;
13039 /* beq 0x10000000 bne 0x14000000
13040 blez 0x18000000 bgtz 0x1c000000 */
13041 insn
^= 0x04000000;
13049 if (RELAX_BRANCH_LINK (fragp
->fr_subtype
))
13051 /* Clear the and-link bit. */
13052 assert ((insn
& 0xfc1c0000) == 0x04100000);
13054 /* bltzal 0x04100000 bgezal 0x04110000
13055 bltzall 0x04120000 bgezall 0x04130000 */
13056 insn
&= ~0x00100000;
13059 /* Branch over the branch (if the branch was likely) or the
13060 full jump (not likely case). Compute the offset from the
13061 current instruction to branch to. */
13062 if (RELAX_BRANCH_LIKELY (fragp
->fr_subtype
))
13066 /* How many bytes in instructions we've already emitted? */
13067 i
= buf
- (bfd_byte
*)fragp
->fr_literal
- fragp
->fr_fix
;
13068 /* How many bytes in instructions from here to the end? */
13069 i
= fragp
->fr_var
- i
;
13071 /* Convert to instruction count. */
13073 /* Branch counts from the next instruction. */
13076 /* Branch over the jump. */
13077 md_number_to_chars ((char *) buf
, insn
, 4);
13081 md_number_to_chars ((char *) buf
, 0, 4);
13084 if (RELAX_BRANCH_LIKELY (fragp
->fr_subtype
))
13086 /* beql $0, $0, 2f */
13088 /* Compute the PC offset from the current instruction to
13089 the end of the variable frag. */
13090 /* How many bytes in instructions we've already emitted? */
13091 i
= buf
- (bfd_byte
*)fragp
->fr_literal
- fragp
->fr_fix
;
13092 /* How many bytes in instructions from here to the end? */
13093 i
= fragp
->fr_var
- i
;
13094 /* Convert to instruction count. */
13096 /* Don't decrement i, because we want to branch over the
13100 md_number_to_chars ((char *) buf
, insn
, 4);
13103 md_number_to_chars ((char *) buf
, 0, 4);
13108 if (mips_pic
== NO_PIC
)
13111 insn
= (RELAX_BRANCH_LINK (fragp
->fr_subtype
)
13112 ? 0x0c000000 : 0x08000000);
13113 exp
.X_op
= O_symbol
;
13114 exp
.X_add_symbol
= fragp
->fr_symbol
;
13115 exp
.X_add_number
= fragp
->fr_offset
;
13117 fixp
= fix_new_exp (fragp
, buf
- (bfd_byte
*)fragp
->fr_literal
,
13118 4, &exp
, 0, BFD_RELOC_MIPS_JMP
);
13119 fixp
->fx_file
= fragp
->fr_file
;
13120 fixp
->fx_line
= fragp
->fr_line
;
13122 md_number_to_chars ((char *) buf
, insn
, 4);
13127 /* lw/ld $at, <sym>($gp) R_MIPS_GOT16 */
13128 insn
= HAVE_64BIT_ADDRESSES
? 0xdf810000 : 0x8f810000;
13129 exp
.X_op
= O_symbol
;
13130 exp
.X_add_symbol
= fragp
->fr_symbol
;
13131 exp
.X_add_number
= fragp
->fr_offset
;
13133 if (fragp
->fr_offset
)
13135 exp
.X_add_symbol
= make_expr_symbol (&exp
);
13136 exp
.X_add_number
= 0;
13139 fixp
= fix_new_exp (fragp
, buf
- (bfd_byte
*)fragp
->fr_literal
,
13140 4, &exp
, 0, BFD_RELOC_MIPS_GOT16
);
13141 fixp
->fx_file
= fragp
->fr_file
;
13142 fixp
->fx_line
= fragp
->fr_line
;
13144 md_number_to_chars ((char *) buf
, insn
, 4);
13147 if (mips_opts
.isa
== ISA_MIPS1
)
13150 md_number_to_chars ((char *) buf
, 0, 4);
13154 /* d/addiu $at, $at, <sym> R_MIPS_LO16 */
13155 insn
= HAVE_64BIT_ADDRESSES
? 0x64210000 : 0x24210000;
13157 fixp
= fix_new_exp (fragp
, buf
- (bfd_byte
*)fragp
->fr_literal
,
13158 4, &exp
, 0, BFD_RELOC_LO16
);
13159 fixp
->fx_file
= fragp
->fr_file
;
13160 fixp
->fx_line
= fragp
->fr_line
;
13162 md_number_to_chars ((char *) buf
, insn
, 4);
13166 if (RELAX_BRANCH_LINK (fragp
->fr_subtype
))
13171 md_number_to_chars ((char *) buf
, insn
, 4);
13176 assert (buf
== (bfd_byte
*)fragp
->fr_literal
13177 + fragp
->fr_fix
+ fragp
->fr_var
);
13179 fragp
->fr_fix
+= fragp
->fr_var
;
13184 if (RELAX_MIPS16_P (fragp
->fr_subtype
))
13187 register const struct mips16_immed_operand
*op
;
13188 bfd_boolean small
, ext
;
13191 unsigned long insn
;
13192 bfd_boolean use_extend
;
13193 unsigned short extend
;
13195 type
= RELAX_MIPS16_TYPE (fragp
->fr_subtype
);
13196 op
= mips16_immed_operands
;
13197 while (op
->type
!= type
)
13200 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
13211 resolve_symbol_value (fragp
->fr_symbol
);
13212 val
= S_GET_VALUE (fragp
->fr_symbol
);
13217 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
13219 /* The rules for the base address of a PC relative reloc are
13220 complicated; see mips16_extended_frag. */
13221 if (type
== 'p' || type
== 'q')
13226 /* Ignore the low bit in the target, since it will be
13227 set for a text label. */
13228 if ((val
& 1) != 0)
13231 else if (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
))
13233 else if (RELAX_MIPS16_DSLOT (fragp
->fr_subtype
))
13236 addr
&= ~ (addressT
) ((1 << op
->shift
) - 1);
13239 /* Make sure the section winds up with the alignment we have
13242 record_alignment (asec
, op
->shift
);
13246 && (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
)
13247 || RELAX_MIPS16_DSLOT (fragp
->fr_subtype
)))
13248 as_warn_where (fragp
->fr_file
, fragp
->fr_line
,
13249 _("extended instruction in delay slot"));
13251 buf
= (bfd_byte
*) (fragp
->fr_literal
+ fragp
->fr_fix
);
13253 if (target_big_endian
)
13254 insn
= bfd_getb16 (buf
);
13256 insn
= bfd_getl16 (buf
);
13258 mips16_immed (fragp
->fr_file
, fragp
->fr_line
, type
, val
,
13259 RELAX_MIPS16_USER_EXT (fragp
->fr_subtype
),
13260 small
, ext
, &insn
, &use_extend
, &extend
);
13264 md_number_to_chars ((char *) buf
, 0xf000 | extend
, 2);
13265 fragp
->fr_fix
+= 2;
13269 md_number_to_chars ((char *) buf
, insn
, 2);
13270 fragp
->fr_fix
+= 2;
13278 first
= RELAX_FIRST (fragp
->fr_subtype
);
13279 second
= RELAX_SECOND (fragp
->fr_subtype
);
13280 fixp
= (fixS
*) fragp
->fr_opcode
;
13282 /* Possibly emit a warning if we've chosen the longer option. */
13283 if (((fragp
->fr_subtype
& RELAX_USE_SECOND
) != 0)
13284 == ((fragp
->fr_subtype
& RELAX_SECOND_LONGER
) != 0))
13286 const char *msg
= macro_warning (fragp
->fr_subtype
);
13288 as_warn_where (fragp
->fr_file
, fragp
->fr_line
, msg
);
13291 /* Go through all the fixups for the first sequence. Disable them
13292 (by marking them as done) if we're going to use the second
13293 sequence instead. */
13295 && fixp
->fx_frag
== fragp
13296 && fixp
->fx_where
< fragp
->fr_fix
- second
)
13298 if (fragp
->fr_subtype
& RELAX_USE_SECOND
)
13300 fixp
= fixp
->fx_next
;
13303 /* Go through the fixups for the second sequence. Disable them if
13304 we're going to use the first sequence, otherwise adjust their
13305 addresses to account for the relaxation. */
13306 while (fixp
&& fixp
->fx_frag
== fragp
)
13308 if (fragp
->fr_subtype
& RELAX_USE_SECOND
)
13309 fixp
->fx_where
-= first
;
13312 fixp
= fixp
->fx_next
;
13315 /* Now modify the frag contents. */
13316 if (fragp
->fr_subtype
& RELAX_USE_SECOND
)
13320 start
= fragp
->fr_literal
+ fragp
->fr_fix
- first
- second
;
13321 memmove (start
, start
+ first
, second
);
13322 fragp
->fr_fix
-= first
;
13325 fragp
->fr_fix
-= second
;
13331 /* This function is called after the relocs have been generated.
13332 We've been storing mips16 text labels as odd. Here we convert them
13333 back to even for the convenience of the debugger. */
13336 mips_frob_file_after_relocs (void)
13339 unsigned int count
, i
;
13341 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
13344 syms
= bfd_get_outsymbols (stdoutput
);
13345 count
= bfd_get_symcount (stdoutput
);
13346 for (i
= 0; i
< count
; i
++, syms
++)
13348 if (elf_symbol (*syms
)->internal_elf_sym
.st_other
== STO_MIPS16
13349 && ((*syms
)->value
& 1) != 0)
13351 (*syms
)->value
&= ~1;
13352 /* If the symbol has an odd size, it was probably computed
13353 incorrectly, so adjust that as well. */
13354 if ((elf_symbol (*syms
)->internal_elf_sym
.st_size
& 1) != 0)
13355 ++elf_symbol (*syms
)->internal_elf_sym
.st_size
;
13362 /* This function is called whenever a label is defined. It is used
13363 when handling branch delays; if a branch has a label, we assume we
13364 can not move it. */
13367 mips_define_label (symbolS
*sym
)
13369 struct insn_label_list
*l
;
13371 if (free_insn_labels
== NULL
)
13372 l
= (struct insn_label_list
*) xmalloc (sizeof *l
);
13375 l
= free_insn_labels
;
13376 free_insn_labels
= l
->next
;
13380 l
->next
= insn_labels
;
13384 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13386 /* Some special processing for a MIPS ELF file. */
13389 mips_elf_final_processing (void)
13391 /* Write out the register information. */
13392 if (mips_abi
!= N64_ABI
)
13396 s
.ri_gprmask
= mips_gprmask
;
13397 s
.ri_cprmask
[0] = mips_cprmask
[0];
13398 s
.ri_cprmask
[1] = mips_cprmask
[1];
13399 s
.ri_cprmask
[2] = mips_cprmask
[2];
13400 s
.ri_cprmask
[3] = mips_cprmask
[3];
13401 /* The gp_value field is set by the MIPS ELF backend. */
13403 bfd_mips_elf32_swap_reginfo_out (stdoutput
, &s
,
13404 ((Elf32_External_RegInfo
*)
13405 mips_regmask_frag
));
13409 Elf64_Internal_RegInfo s
;
13411 s
.ri_gprmask
= mips_gprmask
;
13413 s
.ri_cprmask
[0] = mips_cprmask
[0];
13414 s
.ri_cprmask
[1] = mips_cprmask
[1];
13415 s
.ri_cprmask
[2] = mips_cprmask
[2];
13416 s
.ri_cprmask
[3] = mips_cprmask
[3];
13417 /* The gp_value field is set by the MIPS ELF backend. */
13419 bfd_mips_elf64_swap_reginfo_out (stdoutput
, &s
,
13420 ((Elf64_External_RegInfo
*)
13421 mips_regmask_frag
));
13424 /* Set the MIPS ELF flag bits. FIXME: There should probably be some
13425 sort of BFD interface for this. */
13426 if (mips_any_noreorder
)
13427 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_NOREORDER
;
13428 if (mips_pic
!= NO_PIC
)
13430 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_PIC
;
13431 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_CPIC
;
13434 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_CPIC
;
13436 /* Set MIPS ELF flags for ASEs. */
13437 if (file_ase_mips16
)
13438 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ARCH_ASE_M16
;
13439 #if 0 /* XXX FIXME */
13440 if (file_ase_mips3d
)
13441 elf_elfheader (stdoutput
)->e_flags
|= ???;
13444 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ARCH_ASE_MDMX
;
13446 /* Set the MIPS ELF ABI flags. */
13447 if (mips_abi
== O32_ABI
&& USE_E_MIPS_ABI_O32
)
13448 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_O32
;
13449 else if (mips_abi
== O64_ABI
)
13450 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_O64
;
13451 else if (mips_abi
== EABI_ABI
)
13453 if (!file_mips_gp32
)
13454 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_EABI64
;
13456 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_EABI32
;
13458 else if (mips_abi
== N32_ABI
)
13459 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ABI2
;
13461 /* Nothing to do for N64_ABI. */
13463 if (mips_32bitmode
)
13464 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_32BITMODE
;
13467 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */
13469 typedef struct proc
{
13471 symbolS
*func_end_sym
;
13472 unsigned long reg_mask
;
13473 unsigned long reg_offset
;
13474 unsigned long fpreg_mask
;
13475 unsigned long fpreg_offset
;
13476 unsigned long frame_offset
;
13477 unsigned long frame_reg
;
13478 unsigned long pc_reg
;
13481 static procS cur_proc
;
13482 static procS
*cur_proc_ptr
;
13483 static int numprocs
;
13485 /* Fill in an rs_align_code fragment. */
13488 mips_handle_align (fragS
*fragp
)
13490 if (fragp
->fr_type
!= rs_align_code
)
13493 if (mips_opts
.mips16
)
13495 static const unsigned char be_nop
[] = { 0x65, 0x00 };
13496 static const unsigned char le_nop
[] = { 0x00, 0x65 };
13501 bytes
= fragp
->fr_next
->fr_address
- fragp
->fr_address
- fragp
->fr_fix
;
13502 p
= fragp
->fr_literal
+ fragp
->fr_fix
;
13510 memcpy (p
, (target_big_endian
? be_nop
: le_nop
), 2);
13514 /* For mips32, a nop is a zero, which we trivially get by doing nothing. */
13518 md_obj_begin (void)
13525 /* check for premature end, nesting errors, etc */
13527 as_warn (_("missing .end at end of assembly"));
13536 if (*input_line_pointer
== '-')
13538 ++input_line_pointer
;
13541 if (!ISDIGIT (*input_line_pointer
))
13542 as_bad (_("expected simple number"));
13543 if (input_line_pointer
[0] == '0')
13545 if (input_line_pointer
[1] == 'x')
13547 input_line_pointer
+= 2;
13548 while (ISXDIGIT (*input_line_pointer
))
13551 val
|= hex_value (*input_line_pointer
++);
13553 return negative
? -val
: val
;
13557 ++input_line_pointer
;
13558 while (ISDIGIT (*input_line_pointer
))
13561 val
|= *input_line_pointer
++ - '0';
13563 return negative
? -val
: val
;
13566 if (!ISDIGIT (*input_line_pointer
))
13568 printf (_(" *input_line_pointer == '%c' 0x%02x\n"),
13569 *input_line_pointer
, *input_line_pointer
);
13570 as_warn (_("invalid number"));
13573 while (ISDIGIT (*input_line_pointer
))
13576 val
+= *input_line_pointer
++ - '0';
13578 return negative
? -val
: val
;
13581 /* The .file directive; just like the usual .file directive, but there
13582 is an initial number which is the ECOFF file index. In the non-ECOFF
13583 case .file implies DWARF-2. */
13586 s_mips_file (int x ATTRIBUTE_UNUSED
)
13588 static int first_file_directive
= 0;
13590 if (ECOFF_DEBUGGING
)
13599 filename
= dwarf2_directive_file (0);
13601 /* Versions of GCC up to 3.1 start files with a ".file"
13602 directive even for stabs output. Make sure that this
13603 ".file" is handled. Note that you need a version of GCC
13604 after 3.1 in order to support DWARF-2 on MIPS. */
13605 if (filename
!= NULL
&& ! first_file_directive
)
13607 (void) new_logical_line (filename
, -1);
13608 s_app_file_string (filename
, 0);
13610 first_file_directive
= 1;
13614 /* The .loc directive, implying DWARF-2. */
13617 s_mips_loc (int x ATTRIBUTE_UNUSED
)
13619 if (!ECOFF_DEBUGGING
)
13620 dwarf2_directive_loc (0);
13623 /* The .end directive. */
13626 s_mips_end (int x ATTRIBUTE_UNUSED
)
13630 /* Following functions need their own .frame and .cprestore directives. */
13631 mips_frame_reg_valid
= 0;
13632 mips_cprestore_valid
= 0;
13634 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
13637 demand_empty_rest_of_line ();
13642 if ((bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) == 0)
13643 as_warn (_(".end not in text section"));
13647 as_warn (_(".end directive without a preceding .ent directive."));
13648 demand_empty_rest_of_line ();
13654 assert (S_GET_NAME (p
));
13655 if (strcmp (S_GET_NAME (p
), S_GET_NAME (cur_proc_ptr
->func_sym
)))
13656 as_warn (_(".end symbol does not match .ent symbol."));
13658 if (debug_type
== DEBUG_STABS
)
13659 stabs_generate_asm_endfunc (S_GET_NAME (p
),
13663 as_warn (_(".end directive missing or unknown symbol"));
13666 /* Create an expression to calculate the size of the function. */
13667 if (p
&& cur_proc_ptr
)
13669 OBJ_SYMFIELD_TYPE
*obj
= symbol_get_obj (p
);
13670 expressionS
*exp
= xmalloc (sizeof (expressionS
));
13673 exp
->X_op
= O_subtract
;
13674 exp
->X_add_symbol
= symbol_temp_new_now ();
13675 exp
->X_op_symbol
= p
;
13676 exp
->X_add_number
= 0;
13678 cur_proc_ptr
->func_end_sym
= exp
->X_add_symbol
;
13681 /* Generate a .pdr section. */
13682 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
&& ! ECOFF_DEBUGGING
13685 segT saved_seg
= now_seg
;
13686 subsegT saved_subseg
= now_subseg
;
13691 dot
= frag_now_fix ();
13693 #ifdef md_flush_pending_output
13694 md_flush_pending_output ();
13698 subseg_set (pdr_seg
, 0);
13700 /* Write the symbol. */
13701 exp
.X_op
= O_symbol
;
13702 exp
.X_add_symbol
= p
;
13703 exp
.X_add_number
= 0;
13704 emit_expr (&exp
, 4);
13706 fragp
= frag_more (7 * 4);
13708 md_number_to_chars (fragp
, cur_proc_ptr
->reg_mask
, 4);
13709 md_number_to_chars (fragp
+ 4, cur_proc_ptr
->reg_offset
, 4);
13710 md_number_to_chars (fragp
+ 8, cur_proc_ptr
->fpreg_mask
, 4);
13711 md_number_to_chars (fragp
+ 12, cur_proc_ptr
->fpreg_offset
, 4);
13712 md_number_to_chars (fragp
+ 16, cur_proc_ptr
->frame_offset
, 4);
13713 md_number_to_chars (fragp
+ 20, cur_proc_ptr
->frame_reg
, 4);
13714 md_number_to_chars (fragp
+ 24, cur_proc_ptr
->pc_reg
, 4);
13716 subseg_set (saved_seg
, saved_subseg
);
13718 #endif /* OBJ_ELF */
13720 cur_proc_ptr
= NULL
;
13723 /* The .aent and .ent directives. */
13726 s_mips_ent (int aent
)
13730 symbolP
= get_symbol ();
13731 if (*input_line_pointer
== ',')
13732 ++input_line_pointer
;
13733 SKIP_WHITESPACE ();
13734 if (ISDIGIT (*input_line_pointer
)
13735 || *input_line_pointer
== '-')
13738 if ((bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) == 0)
13739 as_warn (_(".ent or .aent not in text section."));
13741 if (!aent
&& cur_proc_ptr
)
13742 as_warn (_("missing .end"));
13746 /* This function needs its own .frame and .cprestore directives. */
13747 mips_frame_reg_valid
= 0;
13748 mips_cprestore_valid
= 0;
13750 cur_proc_ptr
= &cur_proc
;
13751 memset (cur_proc_ptr
, '\0', sizeof (procS
));
13753 cur_proc_ptr
->func_sym
= symbolP
;
13755 symbol_get_bfdsym (symbolP
)->flags
|= BSF_FUNCTION
;
13759 if (debug_type
== DEBUG_STABS
)
13760 stabs_generate_asm_func (S_GET_NAME (symbolP
),
13761 S_GET_NAME (symbolP
));
13764 demand_empty_rest_of_line ();
13767 /* The .frame directive. If the mdebug section is present (IRIX 5 native)
13768 then ecoff.c (ecoff_directive_frame) is used. For embedded targets,
13769 s_mips_frame is used so that we can set the PDR information correctly.
13770 We can't use the ecoff routines because they make reference to the ecoff
13771 symbol table (in the mdebug section). */
13774 s_mips_frame (int ignore ATTRIBUTE_UNUSED
)
13777 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
&& ! ECOFF_DEBUGGING
)
13781 if (cur_proc_ptr
== (procS
*) NULL
)
13783 as_warn (_(".frame outside of .ent"));
13784 demand_empty_rest_of_line ();
13788 cur_proc_ptr
->frame_reg
= tc_get_register (1);
13790 SKIP_WHITESPACE ();
13791 if (*input_line_pointer
++ != ','
13792 || get_absolute_expression_and_terminator (&val
) != ',')
13794 as_warn (_("Bad .frame directive"));
13795 --input_line_pointer
;
13796 demand_empty_rest_of_line ();
13800 cur_proc_ptr
->frame_offset
= val
;
13801 cur_proc_ptr
->pc_reg
= tc_get_register (0);
13803 demand_empty_rest_of_line ();
13806 #endif /* OBJ_ELF */
13810 /* The .fmask and .mask directives. If the mdebug section is present
13811 (IRIX 5 native) then ecoff.c (ecoff_directive_mask) is used. For
13812 embedded targets, s_mips_mask is used so that we can set the PDR
13813 information correctly. We can't use the ecoff routines because they
13814 make reference to the ecoff symbol table (in the mdebug section). */
13817 s_mips_mask (int reg_type
)
13820 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
&& ! ECOFF_DEBUGGING
)
13824 if (cur_proc_ptr
== (procS
*) NULL
)
13826 as_warn (_(".mask/.fmask outside of .ent"));
13827 demand_empty_rest_of_line ();
13831 if (get_absolute_expression_and_terminator (&mask
) != ',')
13833 as_warn (_("Bad .mask/.fmask directive"));
13834 --input_line_pointer
;
13835 demand_empty_rest_of_line ();
13839 off
= get_absolute_expression ();
13841 if (reg_type
== 'F')
13843 cur_proc_ptr
->fpreg_mask
= mask
;
13844 cur_proc_ptr
->fpreg_offset
= off
;
13848 cur_proc_ptr
->reg_mask
= mask
;
13849 cur_proc_ptr
->reg_offset
= off
;
13852 demand_empty_rest_of_line ();
13855 #endif /* OBJ_ELF */
13856 s_ignore (reg_type
);
13859 /* A table describing all the processors gas knows about. Names are
13860 matched in the order listed.
13862 To ease comparison, please keep this table in the same order as
13863 gcc's mips_cpu_info_table[]. */
13864 static const struct mips_cpu_info mips_cpu_info_table
[] =
13866 /* Entries for generic ISAs */
13867 { "mips1", 1, ISA_MIPS1
, CPU_R3000
},
13868 { "mips2", 1, ISA_MIPS2
, CPU_R6000
},
13869 { "mips3", 1, ISA_MIPS3
, CPU_R4000
},
13870 { "mips4", 1, ISA_MIPS4
, CPU_R8000
},
13871 { "mips5", 1, ISA_MIPS5
, CPU_MIPS5
},
13872 { "mips32", 1, ISA_MIPS32
, CPU_MIPS32
},
13873 { "mips32r2", 1, ISA_MIPS32R2
, CPU_MIPS32R2
},
13874 { "mips64", 1, ISA_MIPS64
, CPU_MIPS64
},
13875 { "mips64r2", 1, ISA_MIPS64R2
, CPU_MIPS64R2
},
13878 { "r3000", 0, ISA_MIPS1
, CPU_R3000
},
13879 { "r2000", 0, ISA_MIPS1
, CPU_R3000
},
13880 { "r3900", 0, ISA_MIPS1
, CPU_R3900
},
13883 { "r6000", 0, ISA_MIPS2
, CPU_R6000
},
13886 { "r4000", 0, ISA_MIPS3
, CPU_R4000
},
13887 { "r4010", 0, ISA_MIPS2
, CPU_R4010
},
13888 { "vr4100", 0, ISA_MIPS3
, CPU_VR4100
},
13889 { "vr4111", 0, ISA_MIPS3
, CPU_R4111
},
13890 { "vr4120", 0, ISA_MIPS3
, CPU_VR4120
},
13891 { "vr4130", 0, ISA_MIPS3
, CPU_VR4120
},
13892 { "vr4181", 0, ISA_MIPS3
, CPU_R4111
},
13893 { "vr4300", 0, ISA_MIPS3
, CPU_R4300
},
13894 { "r4400", 0, ISA_MIPS3
, CPU_R4400
},
13895 { "r4600", 0, ISA_MIPS3
, CPU_R4600
},
13896 { "orion", 0, ISA_MIPS3
, CPU_R4600
},
13897 { "r4650", 0, ISA_MIPS3
, CPU_R4650
},
13900 { "r8000", 0, ISA_MIPS4
, CPU_R8000
},
13901 { "r10000", 0, ISA_MIPS4
, CPU_R10000
},
13902 { "r12000", 0, ISA_MIPS4
, CPU_R12000
},
13903 { "vr5000", 0, ISA_MIPS4
, CPU_R5000
},
13904 { "vr5400", 0, ISA_MIPS4
, CPU_VR5400
},
13905 { "vr5500", 0, ISA_MIPS4
, CPU_VR5500
},
13906 { "rm5200", 0, ISA_MIPS4
, CPU_R5000
},
13907 { "rm5230", 0, ISA_MIPS4
, CPU_R5000
},
13908 { "rm5231", 0, ISA_MIPS4
, CPU_R5000
},
13909 { "rm5261", 0, ISA_MIPS4
, CPU_R5000
},
13910 { "rm5721", 0, ISA_MIPS4
, CPU_R5000
},
13911 { "rm7000", 0, ISA_MIPS4
, CPU_RM7000
},
13912 { "rm9000", 0, ISA_MIPS4
, CPU_RM9000
},
13915 { "4kc", 0, ISA_MIPS32
, CPU_MIPS32
},
13916 { "4km", 0, ISA_MIPS32
, CPU_MIPS32
},
13917 { "4kp", 0, ISA_MIPS32
, CPU_MIPS32
},
13920 { "5kc", 0, ISA_MIPS64
, CPU_MIPS64
},
13921 { "20kc", 0, ISA_MIPS64
, CPU_MIPS64
},
13923 /* Broadcom SB-1 CPU core */
13924 { "sb1", 0, ISA_MIPS64
, CPU_SB1
},
13931 /* Return true if GIVEN is the same as CANONICAL, or if it is CANONICAL
13932 with a final "000" replaced by "k". Ignore case.
13934 Note: this function is shared between GCC and GAS. */
13937 mips_strict_matching_cpu_name_p (const char *canonical
, const char *given
)
13939 while (*given
!= 0 && TOLOWER (*given
) == TOLOWER (*canonical
))
13940 given
++, canonical
++;
13942 return ((*given
== 0 && *canonical
== 0)
13943 || (strcmp (canonical
, "000") == 0 && strcasecmp (given
, "k") == 0));
13947 /* Return true if GIVEN matches CANONICAL, where GIVEN is a user-supplied
13948 CPU name. We've traditionally allowed a lot of variation here.
13950 Note: this function is shared between GCC and GAS. */
13953 mips_matching_cpu_name_p (const char *canonical
, const char *given
)
13955 /* First see if the name matches exactly, or with a final "000"
13956 turned into "k". */
13957 if (mips_strict_matching_cpu_name_p (canonical
, given
))
13960 /* If not, try comparing based on numerical designation alone.
13961 See if GIVEN is an unadorned number, or 'r' followed by a number. */
13962 if (TOLOWER (*given
) == 'r')
13964 if (!ISDIGIT (*given
))
13967 /* Skip over some well-known prefixes in the canonical name,
13968 hoping to find a number there too. */
13969 if (TOLOWER (canonical
[0]) == 'v' && TOLOWER (canonical
[1]) == 'r')
13971 else if (TOLOWER (canonical
[0]) == 'r' && TOLOWER (canonical
[1]) == 'm')
13973 else if (TOLOWER (canonical
[0]) == 'r')
13976 return mips_strict_matching_cpu_name_p (canonical
, given
);
13980 /* Parse an option that takes the name of a processor as its argument.
13981 OPTION is the name of the option and CPU_STRING is the argument.
13982 Return the corresponding processor enumeration if the CPU_STRING is
13983 recognized, otherwise report an error and return null.
13985 A similar function exists in GCC. */
13987 static const struct mips_cpu_info
*
13988 mips_parse_cpu (const char *option
, const char *cpu_string
)
13990 const struct mips_cpu_info
*p
;
13992 /* 'from-abi' selects the most compatible architecture for the given
13993 ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit ABIs. For the
13994 EABIs, we have to decide whether we're using the 32-bit or 64-bit
13995 version. Look first at the -mgp options, if given, otherwise base
13996 the choice on MIPS_DEFAULT_64BIT.
13998 Treat NO_ABI like the EABIs. One reason to do this is that the
13999 plain 'mips' and 'mips64' configs have 'from-abi' as their default
14000 architecture. This code picks MIPS I for 'mips' and MIPS III for
14001 'mips64', just as we did in the days before 'from-abi'. */
14002 if (strcasecmp (cpu_string
, "from-abi") == 0)
14004 if (ABI_NEEDS_32BIT_REGS (mips_abi
))
14005 return mips_cpu_info_from_isa (ISA_MIPS1
);
14007 if (ABI_NEEDS_64BIT_REGS (mips_abi
))
14008 return mips_cpu_info_from_isa (ISA_MIPS3
);
14010 if (file_mips_gp32
>= 0)
14011 return mips_cpu_info_from_isa (file_mips_gp32
? ISA_MIPS1
: ISA_MIPS3
);
14013 return mips_cpu_info_from_isa (MIPS_DEFAULT_64BIT
14018 /* 'default' has traditionally been a no-op. Probably not very useful. */
14019 if (strcasecmp (cpu_string
, "default") == 0)
14022 for (p
= mips_cpu_info_table
; p
->name
!= 0; p
++)
14023 if (mips_matching_cpu_name_p (p
->name
, cpu_string
))
14026 as_bad ("Bad value (%s) for %s", cpu_string
, option
);
14030 /* Return the canonical processor information for ISA (a member of the
14031 ISA_MIPS* enumeration). */
14033 static const struct mips_cpu_info
*
14034 mips_cpu_info_from_isa (int isa
)
14038 for (i
= 0; mips_cpu_info_table
[i
].name
!= NULL
; i
++)
14039 if (mips_cpu_info_table
[i
].is_isa
14040 && isa
== mips_cpu_info_table
[i
].isa
)
14041 return (&mips_cpu_info_table
[i
]);
14046 static const struct mips_cpu_info
*
14047 mips_cpu_info_from_arch (int arch
)
14051 for (i
= 0; mips_cpu_info_table
[i
].name
!= NULL
; i
++)
14052 if (arch
== mips_cpu_info_table
[i
].cpu
)
14053 return (&mips_cpu_info_table
[i
]);
14059 show (FILE *stream
, const char *string
, int *col_p
, int *first_p
)
14063 fprintf (stream
, "%24s", "");
14068 fprintf (stream
, ", ");
14072 if (*col_p
+ strlen (string
) > 72)
14074 fprintf (stream
, "\n%24s", "");
14078 fprintf (stream
, "%s", string
);
14079 *col_p
+= strlen (string
);
14085 md_show_usage (FILE *stream
)
14090 fprintf (stream
, _("\
14092 -EB generate big endian output\n\
14093 -EL generate little endian output\n\
14094 -g, -g2 do not remove unneeded NOPs or swap branches\n\
14095 -G NUM allow referencing objects up to NUM bytes\n\
14096 implicitly with the gp register [default 8]\n"));
14097 fprintf (stream
, _("\
14098 -mips1 generate MIPS ISA I instructions\n\
14099 -mips2 generate MIPS ISA II instructions\n\
14100 -mips3 generate MIPS ISA III instructions\n\
14101 -mips4 generate MIPS ISA IV instructions\n\
14102 -mips5 generate MIPS ISA V instructions\n\
14103 -mips32 generate MIPS32 ISA instructions\n\
14104 -mips32r2 generate MIPS32 release 2 ISA instructions\n\
14105 -mips64 generate MIPS64 ISA instructions\n\
14106 -mips64r2 generate MIPS64 release 2 ISA instructions\n\
14107 -march=CPU/-mtune=CPU generate code/schedule for CPU, where CPU is one of:\n"));
14111 for (i
= 0; mips_cpu_info_table
[i
].name
!= NULL
; i
++)
14112 show (stream
, mips_cpu_info_table
[i
].name
, &column
, &first
);
14113 show (stream
, "from-abi", &column
, &first
);
14114 fputc ('\n', stream
);
14116 fprintf (stream
, _("\
14117 -mCPU equivalent to -march=CPU -mtune=CPU. Deprecated.\n\
14118 -no-mCPU don't generate code specific to CPU.\n\
14119 For -mCPU and -no-mCPU, CPU must be one of:\n"));
14123 show (stream
, "3900", &column
, &first
);
14124 show (stream
, "4010", &column
, &first
);
14125 show (stream
, "4100", &column
, &first
);
14126 show (stream
, "4650", &column
, &first
);
14127 fputc ('\n', stream
);
14129 fprintf (stream
, _("\
14130 -mips16 generate mips16 instructions\n\
14131 -no-mips16 do not generate mips16 instructions\n"));
14132 fprintf (stream
, _("\
14133 -mfix-vr4120 work around certain VR4120 errata\n\
14134 -mgp32 use 32-bit GPRs, regardless of the chosen ISA\n\
14135 -mfp32 use 32-bit FPRs, regardless of the chosen ISA\n\
14136 -mno-shared optimize output for executables\n\
14137 -msym32 assume all symbols have 32-bit values\n\
14138 -O0 remove unneeded NOPs, do not swap branches\n\
14139 -O remove unneeded NOPs and swap branches\n\
14140 --[no-]construct-floats [dis]allow floating point values to be constructed\n\
14141 --trap, --no-break trap exception on div by 0 and mult overflow\n\
14142 --break, --no-trap break exception on div by 0 and mult overflow\n"));
14144 fprintf (stream
, _("\
14145 -KPIC, -call_shared generate SVR4 position independent code\n\
14146 -non_shared do not generate position independent code\n\
14147 -xgot assume a 32 bit GOT\n\
14148 -mpdr, -mno-pdr enable/disable creation of .pdr sections\n\
14149 -mshared, -mno-shared disable/enable .cpload optimization for\n\
14151 -mabi=ABI create ABI conformant object file for:\n"));
14155 show (stream
, "32", &column
, &first
);
14156 show (stream
, "o64", &column
, &first
);
14157 show (stream
, "n32", &column
, &first
);
14158 show (stream
, "64", &column
, &first
);
14159 show (stream
, "eabi", &column
, &first
);
14161 fputc ('\n', stream
);
14163 fprintf (stream
, _("\
14164 -32 create o32 ABI object file (default)\n\
14165 -n32 create n32 ABI object file\n\
14166 -64 create 64 ABI object file\n"));
14171 mips_dwarf2_format (void)
14173 if (mips_abi
== N64_ABI
)
14176 return dwarf2_format_64bit_irix
;
14178 return dwarf2_format_64bit
;
14182 return dwarf2_format_32bit
;
14186 mips_dwarf2_addr_size (void)
14188 if (mips_abi
== N64_ABI
)