1 /* tc-mips.c -- assemble code for a MIPS chip.
2 Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,
3 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011, 2012, 2013
4 Free Software Foundation, Inc.
5 Contributed by the OSF and Ralph Campbell.
6 Written by Keith Knowles and Ralph Campbell, working independently.
7 Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus
10 This file is part of GAS.
12 GAS is free software; you can redistribute it and/or modify
13 it under the terms of the GNU General Public License as published by
14 the Free Software Foundation; either version 3, or (at your option)
17 GAS is distributed in the hope that it will be useful,
18 but WITHOUT ANY WARRANTY; without even the implied warranty of
19 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 GNU General Public License for more details.
22 You should have received a copy of the GNU General Public License
23 along with GAS; see the file COPYING. If not, write to the Free
24 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
30 #include "safe-ctype.h"
32 #include "opcode/mips.h"
34 #include "dwarf2dbg.h"
35 #include "dw2gencfi.h"
37 /* Check assumptions made in this file. */
38 typedef char static_assert1
[sizeof (offsetT
) < 8 ? -1 : 1];
39 typedef char static_assert2
[sizeof (valueT
) < 8 ? -1 : 1];
42 #define DBG(x) printf x
47 #define SKIP_SPACE_TABS(S) \
48 do { while (*(S) == ' ' || *(S) == '\t') ++(S); } while (0)
50 /* Clean up namespace so we can include obj-elf.h too. */
51 static int mips_output_flavor (void);
52 static int mips_output_flavor (void) { return OUTPUT_FLAVOR
; }
53 #undef OBJ_PROCESS_STAB
60 #undef obj_frob_file_after_relocs
61 #undef obj_frob_symbol
63 #undef obj_sec_sym_ok_for_reloc
64 #undef OBJ_COPY_SYMBOL_ATTRIBUTES
67 /* Fix any of them that we actually care about. */
69 #define OUTPUT_FLAVOR mips_output_flavor()
73 #ifndef ECOFF_DEBUGGING
74 #define NO_ECOFF_DEBUGGING
75 #define ECOFF_DEBUGGING 0
78 int mips_flag_mdebug
= -1;
80 /* Control generation of .pdr sections. Off by default on IRIX: the native
81 linker doesn't know about and discards them, but relocations against them
82 remain, leading to rld crashes. */
84 int mips_flag_pdr
= FALSE
;
86 int mips_flag_pdr
= TRUE
;
91 static char *mips_regmask_frag
;
98 #define PIC_CALL_REG 25
106 #define ILLEGAL_REG (32)
108 #define AT mips_opts.at
110 extern int target_big_endian
;
112 /* The name of the readonly data section. */
113 #define RDATA_SECTION_NAME ".rodata"
115 /* Ways in which an instruction can be "appended" to the output. */
117 /* Just add it normally. */
120 /* Add it normally and then add a nop. */
123 /* Turn an instruction with a delay slot into a "compact" version. */
126 /* Insert the instruction before the last one. */
130 /* Information about an instruction, including its format, operands
134 /* The opcode's entry in mips_opcodes or mips16_opcodes. */
135 const struct mips_opcode
*insn_mo
;
137 /* The 16-bit or 32-bit bitstring of the instruction itself. This is
138 a copy of INSN_MO->match with the operands filled in. If we have
139 decided to use an extended MIPS16 instruction, this includes the
141 unsigned long insn_opcode
;
143 /* The frag that contains the instruction. */
146 /* The offset into FRAG of the first instruction byte. */
149 /* The relocs associated with the instruction, if any. */
152 /* True if this entry cannot be moved from its current position. */
153 unsigned int fixed_p
: 1;
155 /* True if this instruction occurred in a .set noreorder block. */
156 unsigned int noreorder_p
: 1;
158 /* True for mips16 instructions that jump to an absolute address. */
159 unsigned int mips16_absolute_jump_p
: 1;
161 /* True if this instruction is complete. */
162 unsigned int complete_p
: 1;
164 /* True if this instruction is cleared from history by unconditional
166 unsigned int cleared_p
: 1;
169 /* The ABI to use. */
180 /* MIPS ABI we are using for this output file. */
181 static enum mips_abi_level mips_abi
= NO_ABI
;
183 /* Whether or not we have code that can call pic code. */
184 int mips_abicalls
= FALSE
;
186 /* Whether or not we have code which can be put into a shared
188 static bfd_boolean mips_in_shared
= TRUE
;
190 /* This is the set of options which may be modified by the .set
191 pseudo-op. We use a struct so that .set push and .set pop are more
194 struct mips_set_options
196 /* MIPS ISA (Instruction Set Architecture) level. This is set to -1
197 if it has not been initialized. Changed by `.set mipsN', and the
198 -mipsN command line option, and the default CPU. */
200 /* Enabled Application Specific Extensions (ASEs). Changed by `.set
201 <asename>', by command line options, and based on the default
204 /* Whether we are assembling for the mips16 processor. 0 if we are
205 not, 1 if we are, and -1 if the value has not been initialized.
206 Changed by `.set mips16' and `.set nomips16', and the -mips16 and
207 -nomips16 command line options, and the default CPU. */
209 /* Whether we are assembling for the mipsMIPS ASE. 0 if we are not,
210 1 if we are, and -1 if the value has not been initialized. Changed
211 by `.set micromips' and `.set nomicromips', and the -mmicromips
212 and -mno-micromips command line options, and the default CPU. */
214 /* Non-zero if we should not reorder instructions. Changed by `.set
215 reorder' and `.set noreorder'. */
217 /* Non-zero if we should not permit the register designated "assembler
218 temporary" to be used in instructions. The value is the register
219 number, normally $at ($1). Changed by `.set at=REG', `.set noat'
220 (same as `.set at=$0') and `.set at' (same as `.set at=$1'). */
222 /* Non-zero if we should warn when a macro instruction expands into
223 more than one machine instruction. Changed by `.set nomacro' and
225 int warn_about_macros
;
226 /* Non-zero if we should not move instructions. Changed by `.set
227 move', `.set volatile', `.set nomove', and `.set novolatile'. */
229 /* Non-zero if we should not optimize branches by moving the target
230 of the branch into the delay slot. Actually, we don't perform
231 this optimization anyhow. Changed by `.set bopt' and `.set
234 /* Non-zero if we should not autoextend mips16 instructions.
235 Changed by `.set autoextend' and `.set noautoextend'. */
237 /* True if we should only emit 32-bit microMIPS instructions.
238 Changed by `.set insn32' and `.set noinsn32', and the -minsn32
239 and -mno-insn32 command line options. */
241 /* Restrict general purpose registers and floating point registers
242 to 32 bit. This is initially determined when -mgp32 or -mfp32
243 is passed but can changed if the assembler code uses .set mipsN. */
246 /* MIPS architecture (CPU) type. Changed by .set arch=FOO, the -march
247 command line option, and the default CPU. */
249 /* True if ".set sym32" is in effect. */
251 /* True if floating-point operations are not allowed. Changed by .set
252 softfloat or .set hardfloat, by command line options -msoft-float or
253 -mhard-float. The default is false. */
254 bfd_boolean soft_float
;
256 /* True if only single-precision floating-point operations are allowed.
257 Changed by .set singlefloat or .set doublefloat, command-line options
258 -msingle-float or -mdouble-float. The default is false. */
259 bfd_boolean single_float
;
262 /* This is the struct we use to hold the current set of options. Note
263 that we must set the isa field to ISA_UNKNOWN and the ASE fields to
264 -1 to indicate that they have not been initialized. */
266 /* True if -mgp32 was passed. */
267 static int file_mips_gp32
= -1;
269 /* True if -mfp32 was passed. */
270 static int file_mips_fp32
= -1;
272 /* 1 if -msoft-float, 0 if -mhard-float. The default is 0. */
273 static int file_mips_soft_float
= 0;
275 /* 1 if -msingle-float, 0 if -mdouble-float. The default is 0. */
276 static int file_mips_single_float
= 0;
278 /* True if -mnan=2008, false if -mnan=legacy. */
279 static bfd_boolean mips_flag_nan2008
= FALSE
;
281 static struct mips_set_options mips_opts
=
283 /* isa */ ISA_UNKNOWN
, /* ase */ 0, /* mips16 */ -1, /* micromips */ -1,
284 /* noreorder */ 0, /* at */ ATREG
, /* warn_about_macros */ 0,
285 /* nomove */ 0, /* nobopt */ 0, /* noautoextend */ 0, /* insn32 */ FALSE
,
286 /* gp32 */ 0, /* fp32 */ 0, /* arch */ CPU_UNKNOWN
, /* sym32 */ FALSE
,
287 /* soft_float */ FALSE
, /* single_float */ FALSE
290 /* The set of ASEs that were selected on the command line, either
291 explicitly via ASE options or implicitly through things like -march. */
292 static unsigned int file_ase
;
294 /* Which bits of file_ase were explicitly set or cleared by ASE options. */
295 static unsigned int file_ase_explicit
;
297 /* These variables are filled in with the masks of registers used.
298 The object format code reads them and puts them in the appropriate
300 unsigned long mips_gprmask
;
301 unsigned long mips_cprmask
[4];
303 /* MIPS ISA we are using for this output file. */
304 static int file_mips_isa
= ISA_UNKNOWN
;
306 /* True if any MIPS16 code was produced. */
307 static int file_ase_mips16
;
309 #define ISA_SUPPORTS_MIPS16E (mips_opts.isa == ISA_MIPS32 \
310 || mips_opts.isa == ISA_MIPS32R2 \
311 || mips_opts.isa == ISA_MIPS64 \
312 || mips_opts.isa == ISA_MIPS64R2)
314 /* True if any microMIPS code was produced. */
315 static int file_ase_micromips
;
317 /* True if we want to create R_MIPS_JALR for jalr $25. */
319 #define MIPS_JALR_HINT_P(EXPR) HAVE_NEWABI
321 /* As a GNU extension, we use R_MIPS_JALR for o32 too. However,
322 because there's no place for any addend, the only acceptable
323 expression is a bare symbol. */
324 #define MIPS_JALR_HINT_P(EXPR) \
325 (!HAVE_IN_PLACE_ADDENDS \
326 || ((EXPR)->X_op == O_symbol && (EXPR)->X_add_number == 0))
329 /* The argument of the -march= flag. The architecture we are assembling. */
330 static int file_mips_arch
= CPU_UNKNOWN
;
331 static const char *mips_arch_string
;
333 /* The argument of the -mtune= flag. The architecture for which we
335 static int mips_tune
= CPU_UNKNOWN
;
336 static const char *mips_tune_string
;
338 /* True when generating 32-bit code for a 64-bit processor. */
339 static int mips_32bitmode
= 0;
341 /* True if the given ABI requires 32-bit registers. */
342 #define ABI_NEEDS_32BIT_REGS(ABI) ((ABI) == O32_ABI)
344 /* Likewise 64-bit registers. */
345 #define ABI_NEEDS_64BIT_REGS(ABI) \
347 || (ABI) == N64_ABI \
350 /* Return true if ISA supports 64 bit wide gp registers. */
351 #define ISA_HAS_64BIT_REGS(ISA) \
352 ((ISA) == ISA_MIPS3 \
353 || (ISA) == ISA_MIPS4 \
354 || (ISA) == ISA_MIPS5 \
355 || (ISA) == ISA_MIPS64 \
356 || (ISA) == ISA_MIPS64R2)
358 /* Return true if ISA supports 64 bit wide float registers. */
359 #define ISA_HAS_64BIT_FPRS(ISA) \
360 ((ISA) == ISA_MIPS3 \
361 || (ISA) == ISA_MIPS4 \
362 || (ISA) == ISA_MIPS5 \
363 || (ISA) == ISA_MIPS32R2 \
364 || (ISA) == ISA_MIPS64 \
365 || (ISA) == ISA_MIPS64R2)
367 /* Return true if ISA supports 64-bit right rotate (dror et al.)
369 #define ISA_HAS_DROR(ISA) \
370 ((ISA) == ISA_MIPS64R2 \
371 || (mips_opts.micromips \
372 && ISA_HAS_64BIT_REGS (ISA)) \
375 /* Return true if ISA supports 32-bit right rotate (ror et al.)
377 #define ISA_HAS_ROR(ISA) \
378 ((ISA) == ISA_MIPS32R2 \
379 || (ISA) == ISA_MIPS64R2 \
380 || (mips_opts.ase & ASE_SMARTMIPS) \
381 || mips_opts.micromips \
384 /* Return true if ISA supports single-precision floats in odd registers. */
385 #define ISA_HAS_ODD_SINGLE_FPR(ISA) \
386 ((ISA) == ISA_MIPS32 \
387 || (ISA) == ISA_MIPS32R2 \
388 || (ISA) == ISA_MIPS64 \
389 || (ISA) == ISA_MIPS64R2)
391 /* Return true if ISA supports move to/from high part of a 64-bit
392 floating-point register. */
393 #define ISA_HAS_MXHC1(ISA) \
394 ((ISA) == ISA_MIPS32R2 \
395 || (ISA) == ISA_MIPS64R2)
397 #define HAVE_32BIT_GPRS \
398 (mips_opts.gp32 || !ISA_HAS_64BIT_REGS (mips_opts.isa))
400 #define HAVE_32BIT_FPRS \
401 (mips_opts.fp32 || !ISA_HAS_64BIT_FPRS (mips_opts.isa))
403 #define HAVE_64BIT_GPRS (!HAVE_32BIT_GPRS)
404 #define HAVE_64BIT_FPRS (!HAVE_32BIT_FPRS)
406 #define HAVE_NEWABI (mips_abi == N32_ABI || mips_abi == N64_ABI)
408 #define HAVE_64BIT_OBJECTS (mips_abi == N64_ABI)
410 /* True if relocations are stored in-place. */
411 #define HAVE_IN_PLACE_ADDENDS (!HAVE_NEWABI)
413 /* The ABI-derived address size. */
414 #define HAVE_64BIT_ADDRESSES \
415 (HAVE_64BIT_GPRS && (mips_abi == EABI_ABI || mips_abi == N64_ABI))
416 #define HAVE_32BIT_ADDRESSES (!HAVE_64BIT_ADDRESSES)
418 /* The size of symbolic constants (i.e., expressions of the form
419 "SYMBOL" or "SYMBOL + OFFSET"). */
420 #define HAVE_32BIT_SYMBOLS \
421 (HAVE_32BIT_ADDRESSES || !HAVE_64BIT_OBJECTS || mips_opts.sym32)
422 #define HAVE_64BIT_SYMBOLS (!HAVE_32BIT_SYMBOLS)
424 /* Addresses are loaded in different ways, depending on the address size
425 in use. The n32 ABI Documentation also mandates the use of additions
426 with overflow checking, but existing implementations don't follow it. */
427 #define ADDRESS_ADD_INSN \
428 (HAVE_32BIT_ADDRESSES ? "addu" : "daddu")
430 #define ADDRESS_ADDI_INSN \
431 (HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu")
433 #define ADDRESS_LOAD_INSN \
434 (HAVE_32BIT_ADDRESSES ? "lw" : "ld")
436 #define ADDRESS_STORE_INSN \
437 (HAVE_32BIT_ADDRESSES ? "sw" : "sd")
439 /* Return true if the given CPU supports the MIPS16 ASE. */
440 #define CPU_HAS_MIPS16(cpu) \
441 (strncmp (TARGET_CPU, "mips16", sizeof ("mips16") - 1) == 0 \
442 || strncmp (TARGET_CANONICAL, "mips-lsi-elf", sizeof ("mips-lsi-elf") - 1) == 0)
444 /* Return true if the given CPU supports the microMIPS ASE. */
445 #define CPU_HAS_MICROMIPS(cpu) 0
447 /* True if CPU has a dror instruction. */
448 #define CPU_HAS_DROR(CPU) ((CPU) == CPU_VR5400 || (CPU) == CPU_VR5500)
450 /* True if CPU has a ror instruction. */
451 #define CPU_HAS_ROR(CPU) CPU_HAS_DROR (CPU)
453 /* True if CPU is in the Octeon family */
454 #define CPU_IS_OCTEON(CPU) ((CPU) == CPU_OCTEON || (CPU) == CPU_OCTEONP || (CPU) == CPU_OCTEON2)
456 /* True if CPU has seq/sne and seqi/snei instructions. */
457 #define CPU_HAS_SEQ(CPU) (CPU_IS_OCTEON (CPU))
459 /* True, if CPU has support for ldc1 and sdc1. */
460 #define CPU_HAS_LDC1_SDC1(CPU) \
461 ((mips_opts.isa != ISA_MIPS1) && ((CPU) != CPU_R5900))
463 /* True if mflo and mfhi can be immediately followed by instructions
464 which write to the HI and LO registers.
466 According to MIPS specifications, MIPS ISAs I, II, and III need
467 (at least) two instructions between the reads of HI/LO and
468 instructions which write them, and later ISAs do not. Contradicting
469 the MIPS specifications, some MIPS IV processor user manuals (e.g.
470 the UM for the NEC Vr5000) document needing the instructions between
471 HI/LO reads and writes, as well. Therefore, we declare only MIPS32,
472 MIPS64 and later ISAs to have the interlocks, plus any specific
473 earlier-ISA CPUs for which CPU documentation declares that the
474 instructions are really interlocked. */
475 #define hilo_interlocks \
476 (mips_opts.isa == ISA_MIPS32 \
477 || mips_opts.isa == ISA_MIPS32R2 \
478 || mips_opts.isa == ISA_MIPS64 \
479 || mips_opts.isa == ISA_MIPS64R2 \
480 || mips_opts.arch == CPU_R4010 \
481 || mips_opts.arch == CPU_R5900 \
482 || mips_opts.arch == CPU_R10000 \
483 || mips_opts.arch == CPU_R12000 \
484 || mips_opts.arch == CPU_R14000 \
485 || mips_opts.arch == CPU_R16000 \
486 || mips_opts.arch == CPU_RM7000 \
487 || mips_opts.arch == CPU_VR5500 \
488 || mips_opts.micromips \
491 /* Whether the processor uses hardware interlocks to protect reads
492 from the GPRs after they are loaded from memory, and thus does not
493 require nops to be inserted. This applies to instructions marked
494 INSN_LOAD_MEMORY_DELAY. These nops are only required at MIPS ISA
495 level I and microMIPS mode instructions are always interlocked. */
496 #define gpr_interlocks \
497 (mips_opts.isa != ISA_MIPS1 \
498 || mips_opts.arch == CPU_R3900 \
499 || mips_opts.arch == CPU_R5900 \
500 || mips_opts.micromips \
503 /* Whether the processor uses hardware interlocks to avoid delays
504 required by coprocessor instructions, and thus does not require
505 nops to be inserted. This applies to instructions marked
506 INSN_LOAD_COPROC_DELAY, INSN_COPROC_MOVE_DELAY, and to delays
507 between instructions marked INSN_WRITE_COND_CODE and ones marked
508 INSN_READ_COND_CODE. These nops are only required at MIPS ISA
509 levels I, II, and III and microMIPS mode instructions are always
511 /* Itbl support may require additional care here. */
512 #define cop_interlocks \
513 ((mips_opts.isa != ISA_MIPS1 \
514 && mips_opts.isa != ISA_MIPS2 \
515 && mips_opts.isa != ISA_MIPS3) \
516 || mips_opts.arch == CPU_R4300 \
517 || mips_opts.micromips \
520 /* Whether the processor uses hardware interlocks to protect reads
521 from coprocessor registers after they are loaded from memory, and
522 thus does not require nops to be inserted. This applies to
523 instructions marked INSN_COPROC_MEMORY_DELAY. These nops are only
524 requires at MIPS ISA level I and microMIPS mode instructions are
525 always interlocked. */
526 #define cop_mem_interlocks \
527 (mips_opts.isa != ISA_MIPS1 \
528 || mips_opts.micromips \
531 /* Is this a mfhi or mflo instruction? */
532 #define MF_HILO_INSN(PINFO) \
533 ((PINFO & INSN_READ_HI) || (PINFO & INSN_READ_LO))
535 /* Whether code compression (either of the MIPS16 or the microMIPS ASEs)
536 has been selected. This implies, in particular, that addresses of text
537 labels have their LSB set. */
538 #define HAVE_CODE_COMPRESSION \
539 ((mips_opts.mips16 | mips_opts.micromips) != 0)
541 /* The minimum and maximum signed values that can be stored in a GPR. */
542 #define GPR_SMAX ((offsetT) (((valueT) 1 << (HAVE_64BIT_GPRS ? 63 : 31)) - 1))
543 #define GPR_SMIN (-GPR_SMAX - 1)
545 /* MIPS PIC level. */
547 enum mips_pic_level mips_pic
;
549 /* 1 if we should generate 32 bit offsets from the $gp register in
550 SVR4_PIC mode. Currently has no meaning in other modes. */
551 static int mips_big_got
= 0;
553 /* 1 if trap instructions should used for overflow rather than break
555 static int mips_trap
= 0;
557 /* 1 if double width floating point constants should not be constructed
558 by assembling two single width halves into two single width floating
559 point registers which just happen to alias the double width destination
560 register. On some architectures this aliasing can be disabled by a bit
561 in the status register, and the setting of this bit cannot be determined
562 automatically at assemble time. */
563 static int mips_disable_float_construction
;
565 /* Non-zero if any .set noreorder directives were used. */
567 static int mips_any_noreorder
;
569 /* Non-zero if nops should be inserted when the register referenced in
570 an mfhi/mflo instruction is read in the next two instructions. */
571 static int mips_7000_hilo_fix
;
573 /* The size of objects in the small data section. */
574 static unsigned int g_switch_value
= 8;
575 /* Whether the -G option was used. */
576 static int g_switch_seen
= 0;
581 /* If we can determine in advance that GP optimization won't be
582 possible, we can skip the relaxation stuff that tries to produce
583 GP-relative references. This makes delay slot optimization work
586 This function can only provide a guess, but it seems to work for
587 gcc output. It needs to guess right for gcc, otherwise gcc
588 will put what it thinks is a GP-relative instruction in a branch
591 I don't know if a fix is needed for the SVR4_PIC mode. I've only
592 fixed it for the non-PIC mode. KR 95/04/07 */
593 static int nopic_need_relax (symbolS
*, int);
595 /* handle of the OPCODE hash table */
596 static struct hash_control
*op_hash
= NULL
;
598 /* The opcode hash table we use for the mips16. */
599 static struct hash_control
*mips16_op_hash
= NULL
;
601 /* The opcode hash table we use for the microMIPS ASE. */
602 static struct hash_control
*micromips_op_hash
= NULL
;
604 /* This array holds the chars that always start a comment. If the
605 pre-processor is disabled, these aren't very useful */
606 const char comment_chars
[] = "#";
608 /* This array holds the chars that only start a comment at the beginning of
609 a line. If the line seems to have the form '# 123 filename'
610 .line and .file directives will appear in the pre-processed output */
611 /* Note that input_file.c hand checks for '#' at the beginning of the
612 first line of the input file. This is because the compiler outputs
613 #NO_APP at the beginning of its output. */
614 /* Also note that C style comments are always supported. */
615 const char line_comment_chars
[] = "#";
617 /* This array holds machine specific line separator characters. */
618 const char line_separator_chars
[] = ";";
620 /* Chars that can be used to separate mant from exp in floating point nums */
621 const char EXP_CHARS
[] = "eE";
623 /* Chars that mean this number is a floating point constant */
626 const char FLT_CHARS
[] = "rRsSfFdDxXpP";
628 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
629 changed in read.c . Ideally it shouldn't have to know about it at all,
630 but nothing is ideal around here.
633 static char *insn_error
;
635 static int auto_align
= 1;
637 /* When outputting SVR4 PIC code, the assembler needs to know the
638 offset in the stack frame from which to restore the $gp register.
639 This is set by the .cprestore pseudo-op, and saved in this
641 static offsetT mips_cprestore_offset
= -1;
643 /* Similar for NewABI PIC code, where $gp is callee-saved. NewABI has some
644 more optimizations, it can use a register value instead of a memory-saved
645 offset and even an other register than $gp as global pointer. */
646 static offsetT mips_cpreturn_offset
= -1;
647 static int mips_cpreturn_register
= -1;
648 static int mips_gp_register
= GP
;
649 static int mips_gprel_offset
= 0;
651 /* Whether mips_cprestore_offset has been set in the current function
652 (or whether it has already been warned about, if not). */
653 static int mips_cprestore_valid
= 0;
655 /* This is the register which holds the stack frame, as set by the
656 .frame pseudo-op. This is needed to implement .cprestore. */
657 static int mips_frame_reg
= SP
;
659 /* Whether mips_frame_reg has been set in the current function
660 (or whether it has already been warned about, if not). */
661 static int mips_frame_reg_valid
= 0;
663 /* To output NOP instructions correctly, we need to keep information
664 about the previous two instructions. */
666 /* Whether we are optimizing. The default value of 2 means to remove
667 unneeded NOPs and swap branch instructions when possible. A value
668 of 1 means to not swap branches. A value of 0 means to always
670 static int mips_optimize
= 2;
672 /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is
673 equivalent to seeing no -g option at all. */
674 static int mips_debug
= 0;
676 /* The maximum number of NOPs needed to avoid the VR4130 mflo/mfhi errata. */
677 #define MAX_VR4130_NOPS 4
679 /* The maximum number of NOPs needed to fill delay slots. */
680 #define MAX_DELAY_NOPS 2
682 /* The maximum number of NOPs needed for any purpose. */
685 /* A list of previous instructions, with index 0 being the most recent.
686 We need to look back MAX_NOPS instructions when filling delay slots
687 or working around processor errata. We need to look back one
688 instruction further if we're thinking about using history[0] to
689 fill a branch delay slot. */
690 static struct mips_cl_insn history
[1 + MAX_NOPS
];
692 /* Nop instructions used by emit_nop. */
693 static struct mips_cl_insn nop_insn
;
694 static struct mips_cl_insn mips16_nop_insn
;
695 static struct mips_cl_insn micromips_nop16_insn
;
696 static struct mips_cl_insn micromips_nop32_insn
;
698 /* The appropriate nop for the current mode. */
699 #define NOP_INSN (mips_opts.mips16 \
701 : (mips_opts.micromips \
702 ? (mips_opts.insn32 \
703 ? µmips_nop32_insn \
704 : µmips_nop16_insn) \
707 /* The size of NOP_INSN in bytes. */
708 #define NOP_INSN_SIZE ((mips_opts.mips16 \
709 || (mips_opts.micromips && !mips_opts.insn32)) \
712 /* If this is set, it points to a frag holding nop instructions which
713 were inserted before the start of a noreorder section. If those
714 nops turn out to be unnecessary, the size of the frag can be
716 static fragS
*prev_nop_frag
;
718 /* The number of nop instructions we created in prev_nop_frag. */
719 static int prev_nop_frag_holds
;
721 /* The number of nop instructions that we know we need in
723 static int prev_nop_frag_required
;
725 /* The number of instructions we've seen since prev_nop_frag. */
726 static int prev_nop_frag_since
;
728 /* Relocations against symbols are sometimes done in two parts, with a HI
729 relocation and a LO relocation. Each relocation has only 16 bits of
730 space to store an addend. This means that in order for the linker to
731 handle carries correctly, it must be able to locate both the HI and
732 the LO relocation. This means that the relocations must appear in
733 order in the relocation table.
735 In order to implement this, we keep track of each unmatched HI
736 relocation. We then sort them so that they immediately precede the
737 corresponding LO relocation. */
742 struct mips_hi_fixup
*next
;
745 /* The section this fixup is in. */
749 /* The list of unmatched HI relocs. */
751 static struct mips_hi_fixup
*mips_hi_fixup_list
;
753 /* The frag containing the last explicit relocation operator.
754 Null if explicit relocations have not been used. */
756 static fragS
*prev_reloc_op_frag
;
758 /* Map mips16 register numbers to normal MIPS register numbers. */
760 static const unsigned int mips16_to_32_reg_map
[] =
762 16, 17, 2, 3, 4, 5, 6, 7
765 /* Map microMIPS register numbers to normal MIPS register numbers. */
767 #define micromips_to_32_reg_b_map mips16_to_32_reg_map
768 #define micromips_to_32_reg_c_map mips16_to_32_reg_map
769 #define micromips_to_32_reg_d_map mips16_to_32_reg_map
770 #define micromips_to_32_reg_e_map mips16_to_32_reg_map
771 #define micromips_to_32_reg_f_map mips16_to_32_reg_map
772 #define micromips_to_32_reg_g_map mips16_to_32_reg_map
774 /* The microMIPS registers with type h. */
775 static const unsigned int micromips_to_32_reg_h_map1
[] =
777 5, 5, 6, 4, 4, 4, 4, 4
779 static const unsigned int micromips_to_32_reg_h_map2
[] =
781 6, 7, 7, 21, 22, 5, 6, 7
784 #define micromips_to_32_reg_l_map mips16_to_32_reg_map
786 /* The microMIPS registers with type m. */
787 static const unsigned int micromips_to_32_reg_m_map
[] =
789 0, 17, 2, 3, 16, 18, 19, 20
792 #define micromips_to_32_reg_n_map micromips_to_32_reg_m_map
794 /* The microMIPS registers with type q. */
795 static const unsigned int micromips_to_32_reg_q_map
[] =
797 0, 17, 2, 3, 4, 5, 6, 7
800 /* Classifies the kind of instructions we're interested in when
801 implementing -mfix-vr4120. */
802 enum fix_vr4120_class
810 NUM_FIX_VR4120_CLASSES
813 /* ...likewise -mfix-loongson2f-jump. */
814 static bfd_boolean mips_fix_loongson2f_jump
;
816 /* ...likewise -mfix-loongson2f-nop. */
817 static bfd_boolean mips_fix_loongson2f_nop
;
819 /* True if -mfix-loongson2f-nop or -mfix-loongson2f-jump passed. */
820 static bfd_boolean mips_fix_loongson2f
;
822 /* Given two FIX_VR4120_* values X and Y, bit Y of element X is set if
823 there must be at least one other instruction between an instruction
824 of type X and an instruction of type Y. */
825 static unsigned int vr4120_conflicts
[NUM_FIX_VR4120_CLASSES
];
827 /* True if -mfix-vr4120 is in force. */
828 static int mips_fix_vr4120
;
830 /* ...likewise -mfix-vr4130. */
831 static int mips_fix_vr4130
;
833 /* ...likewise -mfix-24k. */
834 static int mips_fix_24k
;
836 /* ...likewise -mfix-cn63xxp1 */
837 static bfd_boolean mips_fix_cn63xxp1
;
839 /* We don't relax branches by default, since this causes us to expand
840 `la .l2 - .l1' if there's a branch between .l1 and .l2, because we
841 fail to compute the offset before expanding the macro to the most
842 efficient expansion. */
844 static int mips_relax_branch
;
846 /* The expansion of many macros depends on the type of symbol that
847 they refer to. For example, when generating position-dependent code,
848 a macro that refers to a symbol may have two different expansions,
849 one which uses GP-relative addresses and one which uses absolute
850 addresses. When generating SVR4-style PIC, a macro may have
851 different expansions for local and global symbols.
853 We handle these situations by generating both sequences and putting
854 them in variant frags. In position-dependent code, the first sequence
855 will be the GP-relative one and the second sequence will be the
856 absolute one. In SVR4 PIC, the first sequence will be for global
857 symbols and the second will be for local symbols.
859 The frag's "subtype" is RELAX_ENCODE (FIRST, SECOND), where FIRST and
860 SECOND are the lengths of the two sequences in bytes. These fields
861 can be extracted using RELAX_FIRST() and RELAX_SECOND(). In addition,
862 the subtype has the following flags:
865 Set if it has been decided that we should use the second
866 sequence instead of the first.
869 Set in the first variant frag if the macro's second implementation
870 is longer than its first. This refers to the macro as a whole,
871 not an individual relaxation.
874 Set in the first variant frag if the macro appeared in a .set nomacro
875 block and if one alternative requires a warning but the other does not.
878 Like RELAX_NOMACRO, but indicates that the macro appears in a branch
881 RELAX_DELAY_SLOT_16BIT
882 Like RELAX_DELAY_SLOT, but indicates that the delay slot requires a
885 RELAX_DELAY_SLOT_SIZE_FIRST
886 Like RELAX_DELAY_SLOT, but indicates that the first implementation of
887 the macro is of the wrong size for the branch delay slot.
889 RELAX_DELAY_SLOT_SIZE_SECOND
890 Like RELAX_DELAY_SLOT, but indicates that the second implementation of
891 the macro is of the wrong size for the branch delay slot.
893 The frag's "opcode" points to the first fixup for relaxable code.
895 Relaxable macros are generated using a sequence such as:
897 relax_start (SYMBOL);
898 ... generate first expansion ...
900 ... generate second expansion ...
903 The code and fixups for the unwanted alternative are discarded
904 by md_convert_frag. */
905 #define RELAX_ENCODE(FIRST, SECOND) (((FIRST) << 8) | (SECOND))
907 #define RELAX_FIRST(X) (((X) >> 8) & 0xff)
908 #define RELAX_SECOND(X) ((X) & 0xff)
909 #define RELAX_USE_SECOND 0x10000
910 #define RELAX_SECOND_LONGER 0x20000
911 #define RELAX_NOMACRO 0x40000
912 #define RELAX_DELAY_SLOT 0x80000
913 #define RELAX_DELAY_SLOT_16BIT 0x100000
914 #define RELAX_DELAY_SLOT_SIZE_FIRST 0x200000
915 #define RELAX_DELAY_SLOT_SIZE_SECOND 0x400000
917 /* Branch without likely bit. If label is out of range, we turn:
919 beq reg1, reg2, label
929 with the following opcode replacements:
936 bltzal <-> bgezal (with jal label instead of j label)
938 Even though keeping the delay slot instruction in the delay slot of
939 the branch would be more efficient, it would be very tricky to do
940 correctly, because we'd have to introduce a variable frag *after*
941 the delay slot instruction, and expand that instead. Let's do it
942 the easy way for now, even if the branch-not-taken case now costs
943 one additional instruction. Out-of-range branches are not supposed
944 to be common, anyway.
946 Branch likely. If label is out of range, we turn:
948 beql reg1, reg2, label
949 delay slot (annulled if branch not taken)
958 delay slot (executed only if branch taken)
961 It would be possible to generate a shorter sequence by losing the
962 likely bit, generating something like:
967 delay slot (executed only if branch taken)
979 bltzall -> bgezal (with jal label instead of j label)
980 bgezall -> bltzal (ditto)
983 but it's not clear that it would actually improve performance. */
984 #define RELAX_BRANCH_ENCODE(at, uncond, likely, link, toofar) \
988 | ((toofar) ? 0x20 : 0) \
989 | ((link) ? 0x40 : 0) \
990 | ((likely) ? 0x80 : 0) \
991 | ((uncond) ? 0x100 : 0)))
992 #define RELAX_BRANCH_P(i) (((i) & 0xf0000000) == 0xc0000000)
993 #define RELAX_BRANCH_UNCOND(i) (((i) & 0x100) != 0)
994 #define RELAX_BRANCH_LIKELY(i) (((i) & 0x80) != 0)
995 #define RELAX_BRANCH_LINK(i) (((i) & 0x40) != 0)
996 #define RELAX_BRANCH_TOOFAR(i) (((i) & 0x20) != 0)
997 #define RELAX_BRANCH_AT(i) ((i) & 0x1f)
999 /* For mips16 code, we use an entirely different form of relaxation.
1000 mips16 supports two versions of most instructions which take
1001 immediate values: a small one which takes some small value, and a
1002 larger one which takes a 16 bit value. Since branches also follow
1003 this pattern, relaxing these values is required.
1005 We can assemble both mips16 and normal MIPS code in a single
1006 object. Therefore, we need to support this type of relaxation at
1007 the same time that we support the relaxation described above. We
1008 use the high bit of the subtype field to distinguish these cases.
1010 The information we store for this type of relaxation is the
1011 argument code found in the opcode file for this relocation, whether
1012 the user explicitly requested a small or extended form, and whether
1013 the relocation is in a jump or jal delay slot. That tells us the
1014 size of the value, and how it should be stored. We also store
1015 whether the fragment is considered to be extended or not. We also
1016 store whether this is known to be a branch to a different section,
1017 whether we have tried to relax this frag yet, and whether we have
1018 ever extended a PC relative fragment because of a shift count. */
1019 #define RELAX_MIPS16_ENCODE(type, small, ext, dslot, jal_dslot) \
1022 | ((small) ? 0x100 : 0) \
1023 | ((ext) ? 0x200 : 0) \
1024 | ((dslot) ? 0x400 : 0) \
1025 | ((jal_dslot) ? 0x800 : 0))
1026 #define RELAX_MIPS16_P(i) (((i) & 0xc0000000) == 0x80000000)
1027 #define RELAX_MIPS16_TYPE(i) ((i) & 0xff)
1028 #define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x100) != 0)
1029 #define RELAX_MIPS16_USER_EXT(i) (((i) & 0x200) != 0)
1030 #define RELAX_MIPS16_DSLOT(i) (((i) & 0x400) != 0)
1031 #define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x800) != 0)
1032 #define RELAX_MIPS16_EXTENDED(i) (((i) & 0x1000) != 0)
1033 #define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x1000)
1034 #define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) &~ 0x1000)
1035 #define RELAX_MIPS16_LONG_BRANCH(i) (((i) & 0x2000) != 0)
1036 #define RELAX_MIPS16_MARK_LONG_BRANCH(i) ((i) | 0x2000)
1037 #define RELAX_MIPS16_CLEAR_LONG_BRANCH(i) ((i) &~ 0x2000)
1039 /* For microMIPS code, we use relaxation similar to one we use for
1040 MIPS16 code. Some instructions that take immediate values support
1041 two encodings: a small one which takes some small value, and a
1042 larger one which takes a 16 bit value. As some branches also follow
1043 this pattern, relaxing these values is required.
1045 We can assemble both microMIPS and normal MIPS code in a single
1046 object. Therefore, we need to support this type of relaxation at
1047 the same time that we support the relaxation described above. We
1048 use one of the high bits of the subtype field to distinguish these
1051 The information we store for this type of relaxation is the argument
1052 code found in the opcode file for this relocation, the register
1053 selected as the assembler temporary, whether the branch is
1054 unconditional, whether it is compact, whether it stores the link
1055 address implicitly in $ra, whether relaxation of out-of-range 32-bit
1056 branches to a sequence of instructions is enabled, and whether the
1057 displacement of a branch is too large to fit as an immediate argument
1058 of a 16-bit and a 32-bit branch, respectively. */
1059 #define RELAX_MICROMIPS_ENCODE(type, at, uncond, compact, link, \
1060 relax32, toofar16, toofar32) \
1063 | (((at) & 0x1f) << 8) \
1064 | ((uncond) ? 0x2000 : 0) \
1065 | ((compact) ? 0x4000 : 0) \
1066 | ((link) ? 0x8000 : 0) \
1067 | ((relax32) ? 0x10000 : 0) \
1068 | ((toofar16) ? 0x20000 : 0) \
1069 | ((toofar32) ? 0x40000 : 0))
1070 #define RELAX_MICROMIPS_P(i) (((i) & 0xc0000000) == 0x40000000)
1071 #define RELAX_MICROMIPS_TYPE(i) ((i) & 0xff)
1072 #define RELAX_MICROMIPS_AT(i) (((i) >> 8) & 0x1f)
1073 #define RELAX_MICROMIPS_UNCOND(i) (((i) & 0x2000) != 0)
1074 #define RELAX_MICROMIPS_COMPACT(i) (((i) & 0x4000) != 0)
1075 #define RELAX_MICROMIPS_LINK(i) (((i) & 0x8000) != 0)
1076 #define RELAX_MICROMIPS_RELAX32(i) (((i) & 0x10000) != 0)
1078 #define RELAX_MICROMIPS_TOOFAR16(i) (((i) & 0x20000) != 0)
1079 #define RELAX_MICROMIPS_MARK_TOOFAR16(i) ((i) | 0x20000)
1080 #define RELAX_MICROMIPS_CLEAR_TOOFAR16(i) ((i) & ~0x20000)
1081 #define RELAX_MICROMIPS_TOOFAR32(i) (((i) & 0x40000) != 0)
1082 #define RELAX_MICROMIPS_MARK_TOOFAR32(i) ((i) | 0x40000)
1083 #define RELAX_MICROMIPS_CLEAR_TOOFAR32(i) ((i) & ~0x40000)
1085 /* Sign-extend 16-bit value X. */
1086 #define SEXT_16BIT(X) ((((X) + 0x8000) & 0xffff) - 0x8000)
1088 /* Is the given value a sign-extended 32-bit value? */
1089 #define IS_SEXT_32BIT_NUM(x) \
1090 (((x) &~ (offsetT) 0x7fffffff) == 0 \
1091 || (((x) &~ (offsetT) 0x7fffffff) == ~ (offsetT) 0x7fffffff))
1093 /* Is the given value a sign-extended 16-bit value? */
1094 #define IS_SEXT_16BIT_NUM(x) \
1095 (((x) &~ (offsetT) 0x7fff) == 0 \
1096 || (((x) &~ (offsetT) 0x7fff) == ~ (offsetT) 0x7fff))
1098 /* Is the given value a sign-extended 12-bit value? */
1099 #define IS_SEXT_12BIT_NUM(x) \
1100 (((((x) & 0xfff) ^ 0x800LL) - 0x800LL) == (x))
1102 /* Is the given value a sign-extended 9-bit value? */
1103 #define IS_SEXT_9BIT_NUM(x) \
1104 (((((x) & 0x1ff) ^ 0x100LL) - 0x100LL) == (x))
1106 /* Is the given value a zero-extended 32-bit value? Or a negated one? */
1107 #define IS_ZEXT_32BIT_NUM(x) \
1108 (((x) &~ (offsetT) 0xffffffff) == 0 \
1109 || (((x) &~ (offsetT) 0xffffffff) == ~ (offsetT) 0xffffffff))
1111 /* Extract bits MASK << SHIFT from STRUCT and shift them right
1113 #define EXTRACT_BITS(STRUCT, MASK, SHIFT) \
1114 (((STRUCT) >> (SHIFT)) & (MASK))
1116 /* Extract the operand given by FIELD from mips_cl_insn INSN. */
1117 #define EXTRACT_OPERAND(MICROMIPS, FIELD, INSN) \
1119 ? EXTRACT_BITS ((INSN).insn_opcode, OP_MASK_##FIELD, OP_SH_##FIELD) \
1120 : EXTRACT_BITS ((INSN).insn_opcode, \
1121 MICROMIPSOP_MASK_##FIELD, MICROMIPSOP_SH_##FIELD))
1122 #define MIPS16_EXTRACT_OPERAND(FIELD, INSN) \
1123 EXTRACT_BITS ((INSN).insn_opcode, \
1124 MIPS16OP_MASK_##FIELD, \
1125 MIPS16OP_SH_##FIELD)
1127 /* The MIPS16 EXTEND opcode, shifted left 16 places. */
1128 #define MIPS16_EXTEND (0xf000U << 16)
1130 /* Whether or not we are emitting a branch-likely macro. */
1131 static bfd_boolean emit_branch_likely_macro
= FALSE
;
1133 /* Global variables used when generating relaxable macros. See the
1134 comment above RELAX_ENCODE for more details about how relaxation
1137 /* 0 if we're not emitting a relaxable macro.
1138 1 if we're emitting the first of the two relaxation alternatives.
1139 2 if we're emitting the second alternative. */
1142 /* The first relaxable fixup in the current frag. (In other words,
1143 the first fixup that refers to relaxable code.) */
1146 /* sizes[0] says how many bytes of the first alternative are stored in
1147 the current frag. Likewise sizes[1] for the second alternative. */
1148 unsigned int sizes
[2];
1150 /* The symbol on which the choice of sequence depends. */
1154 /* Global variables used to decide whether a macro needs a warning. */
1156 /* True if the macro is in a branch delay slot. */
1157 bfd_boolean delay_slot_p
;
1159 /* Set to the length in bytes required if the macro is in a delay slot
1160 that requires a specific length of instruction, otherwise zero. */
1161 unsigned int delay_slot_length
;
1163 /* For relaxable macros, sizes[0] is the length of the first alternative
1164 in bytes and sizes[1] is the length of the second alternative.
1165 For non-relaxable macros, both elements give the length of the
1167 unsigned int sizes
[2];
1169 /* For relaxable macros, first_insn_sizes[0] is the length of the first
1170 instruction of the first alternative in bytes and first_insn_sizes[1]
1171 is the length of the first instruction of the second alternative.
1172 For non-relaxable macros, both elements give the length of the first
1173 instruction in bytes.
1175 Set to zero if we haven't yet seen the first instruction. */
1176 unsigned int first_insn_sizes
[2];
1178 /* For relaxable macros, insns[0] is the number of instructions for the
1179 first alternative and insns[1] is the number of instructions for the
1182 For non-relaxable macros, both elements give the number of
1183 instructions for the macro. */
1184 unsigned int insns
[2];
1186 /* The first variant frag for this macro. */
1188 } mips_macro_warning
;
1190 /* Prototypes for static functions. */
1192 enum mips_regclass
{ MIPS_GR_REG
, MIPS_FP_REG
, MIPS16_REG
};
1194 static void append_insn
1195 (struct mips_cl_insn
*, expressionS
*, bfd_reloc_code_real_type
*,
1196 bfd_boolean expansionp
);
1197 static void mips_no_prev_insn (void);
1198 static void macro_build (expressionS
*, const char *, const char *, ...);
1199 static void mips16_macro_build
1200 (expressionS
*, const char *, const char *, va_list *);
1201 static void load_register (int, expressionS
*, int);
1202 static void macro_start (void);
1203 static void macro_end (void);
1204 static void macro (struct mips_cl_insn
*ip
, char *str
);
1205 static void mips16_macro (struct mips_cl_insn
* ip
);
1206 static void mips_ip (char *str
, struct mips_cl_insn
* ip
);
1207 static void mips16_ip (char *str
, struct mips_cl_insn
* ip
);
1208 static void mips16_immed
1209 (char *, unsigned int, int, bfd_reloc_code_real_type
, offsetT
,
1210 unsigned int, unsigned long *);
1211 static size_t my_getSmallExpression
1212 (expressionS
*, bfd_reloc_code_real_type
*, char *);
1213 static void my_getExpression (expressionS
*, char *);
1214 static void s_align (int);
1215 static void s_change_sec (int);
1216 static void s_change_section (int);
1217 static void s_cons (int);
1218 static void s_float_cons (int);
1219 static void s_mips_globl (int);
1220 static void s_option (int);
1221 static void s_mipsset (int);
1222 static void s_abicalls (int);
1223 static void s_cpload (int);
1224 static void s_cpsetup (int);
1225 static void s_cplocal (int);
1226 static void s_cprestore (int);
1227 static void s_cpreturn (int);
1228 static void s_dtprelword (int);
1229 static void s_dtpreldword (int);
1230 static void s_tprelword (int);
1231 static void s_tpreldword (int);
1232 static void s_gpvalue (int);
1233 static void s_gpword (int);
1234 static void s_gpdword (int);
1235 static void s_ehword (int);
1236 static void s_cpadd (int);
1237 static void s_insn (int);
1238 static void s_nan (int);
1239 static void md_obj_begin (void);
1240 static void md_obj_end (void);
1241 static void s_mips_ent (int);
1242 static void s_mips_end (int);
1243 static void s_mips_frame (int);
1244 static void s_mips_mask (int reg_type
);
1245 static void s_mips_stab (int);
1246 static void s_mips_weakext (int);
1247 static void s_mips_file (int);
1248 static void s_mips_loc (int);
1249 static bfd_boolean
pic_need_relax (symbolS
*, asection
*);
1250 static int relaxed_branch_length (fragS
*, asection
*, int);
1251 static int relaxed_micromips_16bit_branch_length (fragS
*, asection
*, int);
1252 static int relaxed_micromips_32bit_branch_length (fragS
*, asection
*, int);
1254 /* Table and functions used to map between CPU/ISA names, and
1255 ISA levels, and CPU numbers. */
1257 struct mips_cpu_info
1259 const char *name
; /* CPU or ISA name. */
1260 int flags
; /* MIPS_CPU_* flags. */
1261 int ase
; /* Set of ASEs implemented by the CPU. */
1262 int isa
; /* ISA level. */
1263 int cpu
; /* CPU number (default CPU if ISA). */
1266 #define MIPS_CPU_IS_ISA 0x0001 /* Is this an ISA? (If 0, a CPU.) */
1268 static const struct mips_cpu_info
*mips_parse_cpu (const char *, const char *);
1269 static const struct mips_cpu_info
*mips_cpu_info_from_isa (int);
1270 static const struct mips_cpu_info
*mips_cpu_info_from_arch (int);
1272 /* Command-line options. */
1273 const char *md_shortopts
= "O::g::G:";
1277 OPTION_MARCH
= OPTION_MD_BASE
,
1301 OPTION_NO_SMARTMIPS
,
1307 OPTION_NO_MICROMIPS
,
1310 OPTION_COMPAT_ARCH_BASE
,
1319 OPTION_M7000_HILO_FIX
,
1320 OPTION_MNO_7000_HILO_FIX
,
1323 OPTION_FIX_LOONGSON2F_JUMP
,
1324 OPTION_NO_FIX_LOONGSON2F_JUMP
,
1325 OPTION_FIX_LOONGSON2F_NOP
,
1326 OPTION_NO_FIX_LOONGSON2F_NOP
,
1328 OPTION_NO_FIX_VR4120
,
1330 OPTION_NO_FIX_VR4130
,
1331 OPTION_FIX_CN63XXP1
,
1332 OPTION_NO_FIX_CN63XXP1
,
1339 OPTION_CONSTRUCT_FLOATS
,
1340 OPTION_NO_CONSTRUCT_FLOATS
,
1343 OPTION_RELAX_BRANCH
,
1344 OPTION_NO_RELAX_BRANCH
,
1353 OPTION_SINGLE_FLOAT
,
1354 OPTION_DOUBLE_FLOAT
,
1367 OPTION_MVXWORKS_PIC
,
1372 struct option md_longopts
[] =
1374 /* Options which specify architecture. */
1375 {"march", required_argument
, NULL
, OPTION_MARCH
},
1376 {"mtune", required_argument
, NULL
, OPTION_MTUNE
},
1377 {"mips0", no_argument
, NULL
, OPTION_MIPS1
},
1378 {"mips1", no_argument
, NULL
, OPTION_MIPS1
},
1379 {"mips2", no_argument
, NULL
, OPTION_MIPS2
},
1380 {"mips3", no_argument
, NULL
, OPTION_MIPS3
},
1381 {"mips4", no_argument
, NULL
, OPTION_MIPS4
},
1382 {"mips5", no_argument
, NULL
, OPTION_MIPS5
},
1383 {"mips32", no_argument
, NULL
, OPTION_MIPS32
},
1384 {"mips64", no_argument
, NULL
, OPTION_MIPS64
},
1385 {"mips32r2", no_argument
, NULL
, OPTION_MIPS32R2
},
1386 {"mips64r2", no_argument
, NULL
, OPTION_MIPS64R2
},
1388 /* Options which specify Application Specific Extensions (ASEs). */
1389 {"mips16", no_argument
, NULL
, OPTION_MIPS16
},
1390 {"no-mips16", no_argument
, NULL
, OPTION_NO_MIPS16
},
1391 {"mips3d", no_argument
, NULL
, OPTION_MIPS3D
},
1392 {"no-mips3d", no_argument
, NULL
, OPTION_NO_MIPS3D
},
1393 {"mdmx", no_argument
, NULL
, OPTION_MDMX
},
1394 {"no-mdmx", no_argument
, NULL
, OPTION_NO_MDMX
},
1395 {"mdsp", no_argument
, NULL
, OPTION_DSP
},
1396 {"mno-dsp", no_argument
, NULL
, OPTION_NO_DSP
},
1397 {"mmt", no_argument
, NULL
, OPTION_MT
},
1398 {"mno-mt", no_argument
, NULL
, OPTION_NO_MT
},
1399 {"msmartmips", no_argument
, NULL
, OPTION_SMARTMIPS
},
1400 {"mno-smartmips", no_argument
, NULL
, OPTION_NO_SMARTMIPS
},
1401 {"mdspr2", no_argument
, NULL
, OPTION_DSPR2
},
1402 {"mno-dspr2", no_argument
, NULL
, OPTION_NO_DSPR2
},
1403 {"meva", no_argument
, NULL
, OPTION_EVA
},
1404 {"mno-eva", no_argument
, NULL
, OPTION_NO_EVA
},
1405 {"mmicromips", no_argument
, NULL
, OPTION_MICROMIPS
},
1406 {"mno-micromips", no_argument
, NULL
, OPTION_NO_MICROMIPS
},
1407 {"mmcu", no_argument
, NULL
, OPTION_MCU
},
1408 {"mno-mcu", no_argument
, NULL
, OPTION_NO_MCU
},
1409 {"mvirt", no_argument
, NULL
, OPTION_VIRT
},
1410 {"mno-virt", no_argument
, NULL
, OPTION_NO_VIRT
},
1412 /* Old-style architecture options. Don't add more of these. */
1413 {"m4650", no_argument
, NULL
, OPTION_M4650
},
1414 {"no-m4650", no_argument
, NULL
, OPTION_NO_M4650
},
1415 {"m4010", no_argument
, NULL
, OPTION_M4010
},
1416 {"no-m4010", no_argument
, NULL
, OPTION_NO_M4010
},
1417 {"m4100", no_argument
, NULL
, OPTION_M4100
},
1418 {"no-m4100", no_argument
, NULL
, OPTION_NO_M4100
},
1419 {"m3900", no_argument
, NULL
, OPTION_M3900
},
1420 {"no-m3900", no_argument
, NULL
, OPTION_NO_M3900
},
1422 /* Options which enable bug fixes. */
1423 {"mfix7000", no_argument
, NULL
, OPTION_M7000_HILO_FIX
},
1424 {"no-fix-7000", no_argument
, NULL
, OPTION_MNO_7000_HILO_FIX
},
1425 {"mno-fix7000", no_argument
, NULL
, OPTION_MNO_7000_HILO_FIX
},
1426 {"mfix-loongson2f-jump", no_argument
, NULL
, OPTION_FIX_LOONGSON2F_JUMP
},
1427 {"mno-fix-loongson2f-jump", no_argument
, NULL
, OPTION_NO_FIX_LOONGSON2F_JUMP
},
1428 {"mfix-loongson2f-nop", no_argument
, NULL
, OPTION_FIX_LOONGSON2F_NOP
},
1429 {"mno-fix-loongson2f-nop", no_argument
, NULL
, OPTION_NO_FIX_LOONGSON2F_NOP
},
1430 {"mfix-vr4120", no_argument
, NULL
, OPTION_FIX_VR4120
},
1431 {"mno-fix-vr4120", no_argument
, NULL
, OPTION_NO_FIX_VR4120
},
1432 {"mfix-vr4130", no_argument
, NULL
, OPTION_FIX_VR4130
},
1433 {"mno-fix-vr4130", no_argument
, NULL
, OPTION_NO_FIX_VR4130
},
1434 {"mfix-24k", no_argument
, NULL
, OPTION_FIX_24K
},
1435 {"mno-fix-24k", no_argument
, NULL
, OPTION_NO_FIX_24K
},
1436 {"mfix-cn63xxp1", no_argument
, NULL
, OPTION_FIX_CN63XXP1
},
1437 {"mno-fix-cn63xxp1", no_argument
, NULL
, OPTION_NO_FIX_CN63XXP1
},
1439 /* Miscellaneous options. */
1440 {"trap", no_argument
, NULL
, OPTION_TRAP
},
1441 {"no-break", no_argument
, NULL
, OPTION_TRAP
},
1442 {"break", no_argument
, NULL
, OPTION_BREAK
},
1443 {"no-trap", no_argument
, NULL
, OPTION_BREAK
},
1444 {"EB", no_argument
, NULL
, OPTION_EB
},
1445 {"EL", no_argument
, NULL
, OPTION_EL
},
1446 {"mfp32", no_argument
, NULL
, OPTION_FP32
},
1447 {"mgp32", no_argument
, NULL
, OPTION_GP32
},
1448 {"construct-floats", no_argument
, NULL
, OPTION_CONSTRUCT_FLOATS
},
1449 {"no-construct-floats", no_argument
, NULL
, OPTION_NO_CONSTRUCT_FLOATS
},
1450 {"mfp64", no_argument
, NULL
, OPTION_FP64
},
1451 {"mgp64", no_argument
, NULL
, OPTION_GP64
},
1452 {"relax-branch", no_argument
, NULL
, OPTION_RELAX_BRANCH
},
1453 {"no-relax-branch", no_argument
, NULL
, OPTION_NO_RELAX_BRANCH
},
1454 {"minsn32", no_argument
, NULL
, OPTION_INSN32
},
1455 {"mno-insn32", no_argument
, NULL
, OPTION_NO_INSN32
},
1456 {"mshared", no_argument
, NULL
, OPTION_MSHARED
},
1457 {"mno-shared", no_argument
, NULL
, OPTION_MNO_SHARED
},
1458 {"msym32", no_argument
, NULL
, OPTION_MSYM32
},
1459 {"mno-sym32", no_argument
, NULL
, OPTION_MNO_SYM32
},
1460 {"msoft-float", no_argument
, NULL
, OPTION_SOFT_FLOAT
},
1461 {"mhard-float", no_argument
, NULL
, OPTION_HARD_FLOAT
},
1462 {"msingle-float", no_argument
, NULL
, OPTION_SINGLE_FLOAT
},
1463 {"mdouble-float", no_argument
, NULL
, OPTION_DOUBLE_FLOAT
},
1465 /* Strictly speaking this next option is ELF specific,
1466 but we allow it for other ports as well in order to
1467 make testing easier. */
1468 {"32", no_argument
, NULL
, OPTION_32
},
1470 /* ELF-specific options. */
1471 {"KPIC", no_argument
, NULL
, OPTION_CALL_SHARED
},
1472 {"call_shared", no_argument
, NULL
, OPTION_CALL_SHARED
},
1473 {"call_nonpic", no_argument
, NULL
, OPTION_CALL_NONPIC
},
1474 {"non_shared", no_argument
, NULL
, OPTION_NON_SHARED
},
1475 {"xgot", no_argument
, NULL
, OPTION_XGOT
},
1476 {"mabi", required_argument
, NULL
, OPTION_MABI
},
1477 {"n32", no_argument
, NULL
, OPTION_N32
},
1478 {"64", no_argument
, NULL
, OPTION_64
},
1479 {"mdebug", no_argument
, NULL
, OPTION_MDEBUG
},
1480 {"no-mdebug", no_argument
, NULL
, OPTION_NO_MDEBUG
},
1481 {"mpdr", no_argument
, NULL
, OPTION_PDR
},
1482 {"mno-pdr", no_argument
, NULL
, OPTION_NO_PDR
},
1483 {"mvxworks-pic", no_argument
, NULL
, OPTION_MVXWORKS_PIC
},
1484 {"mnan", required_argument
, NULL
, OPTION_NAN
},
1486 {NULL
, no_argument
, NULL
, 0}
1488 size_t md_longopts_size
= sizeof (md_longopts
);
1490 /* Information about either an Application Specific Extension or an
1491 optional architecture feature that, for simplicity, we treat in the
1492 same way as an ASE. */
1495 /* The name of the ASE, used in both the command-line and .set options. */
1498 /* The associated ASE_* flags. If the ASE is available on both 32-bit
1499 and 64-bit architectures, the flags here refer to the subset that
1500 is available on both. */
1503 /* The ASE_* flag used for instructions that are available on 64-bit
1504 architectures but that are not included in FLAGS. */
1505 unsigned int flags64
;
1507 /* The command-line options that turn the ASE on and off. */
1511 /* The minimum required architecture revisions for MIPS32, MIPS64,
1512 microMIPS32 and microMIPS64, or -1 if the extension isn't supported. */
1515 int micromips32_rev
;
1516 int micromips64_rev
;
1519 /* A table of all supported ASEs. */
1520 static const struct mips_ase mips_ases
[] = {
1521 { "dsp", ASE_DSP
, ASE_DSP64
,
1522 OPTION_DSP
, OPTION_NO_DSP
,
1525 { "dspr2", ASE_DSP
| ASE_DSPR2
, 0,
1526 OPTION_DSPR2
, OPTION_NO_DSPR2
,
1529 { "eva", ASE_EVA
, 0,
1530 OPTION_EVA
, OPTION_NO_EVA
,
1533 { "mcu", ASE_MCU
, 0,
1534 OPTION_MCU
, OPTION_NO_MCU
,
1537 /* Deprecated in MIPS64r5, but we don't implement that yet. */
1538 { "mdmx", ASE_MDMX
, 0,
1539 OPTION_MDMX
, OPTION_NO_MDMX
,
1542 /* Requires 64-bit FPRs, so the minimum MIPS32 revision is 2. */
1543 { "mips3d", ASE_MIPS3D
, 0,
1544 OPTION_MIPS3D
, OPTION_NO_MIPS3D
,
1548 OPTION_MT
, OPTION_NO_MT
,
1551 { "smartmips", ASE_SMARTMIPS
, 0,
1552 OPTION_SMARTMIPS
, OPTION_NO_SMARTMIPS
,
1555 { "virt", ASE_VIRT
, ASE_VIRT64
,
1556 OPTION_VIRT
, OPTION_NO_VIRT
,
1560 /* The set of ASEs that require -mfp64. */
1561 #define FP64_ASES (ASE_MIPS3D | ASE_MDMX)
1563 /* Groups of ASE_* flags that represent different revisions of an ASE. */
1564 static const unsigned int mips_ase_groups
[] = {
1570 The following pseudo-ops from the Kane and Heinrich MIPS book
1571 should be defined here, but are currently unsupported: .alias,
1572 .galive, .gjaldef, .gjrlive, .livereg, .noalias.
1574 The following pseudo-ops from the Kane and Heinrich MIPS book are
1575 specific to the type of debugging information being generated, and
1576 should be defined by the object format: .aent, .begin, .bend,
1577 .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp,
1580 The following pseudo-ops from the Kane and Heinrich MIPS book are
1581 not MIPS CPU specific, but are also not specific to the object file
1582 format. This file is probably the best place to define them, but
1583 they are not currently supported: .asm0, .endr, .lab, .struct. */
1585 static const pseudo_typeS mips_pseudo_table
[] =
1587 /* MIPS specific pseudo-ops. */
1588 {"option", s_option
, 0},
1589 {"set", s_mipsset
, 0},
1590 {"rdata", s_change_sec
, 'r'},
1591 {"sdata", s_change_sec
, 's'},
1592 {"livereg", s_ignore
, 0},
1593 {"abicalls", s_abicalls
, 0},
1594 {"cpload", s_cpload
, 0},
1595 {"cpsetup", s_cpsetup
, 0},
1596 {"cplocal", s_cplocal
, 0},
1597 {"cprestore", s_cprestore
, 0},
1598 {"cpreturn", s_cpreturn
, 0},
1599 {"dtprelword", s_dtprelword
, 0},
1600 {"dtpreldword", s_dtpreldword
, 0},
1601 {"tprelword", s_tprelword
, 0},
1602 {"tpreldword", s_tpreldword
, 0},
1603 {"gpvalue", s_gpvalue
, 0},
1604 {"gpword", s_gpword
, 0},
1605 {"gpdword", s_gpdword
, 0},
1606 {"ehword", s_ehword
, 0},
1607 {"cpadd", s_cpadd
, 0},
1608 {"insn", s_insn
, 0},
1611 /* Relatively generic pseudo-ops that happen to be used on MIPS
1613 {"asciiz", stringer
, 8 + 1},
1614 {"bss", s_change_sec
, 'b'},
1616 {"half", s_cons
, 1},
1617 {"dword", s_cons
, 3},
1618 {"weakext", s_mips_weakext
, 0},
1619 {"origin", s_org
, 0},
1620 {"repeat", s_rept
, 0},
1622 /* For MIPS this is non-standard, but we define it for consistency. */
1623 {"sbss", s_change_sec
, 'B'},
1625 /* These pseudo-ops are defined in read.c, but must be overridden
1626 here for one reason or another. */
1627 {"align", s_align
, 0},
1628 {"byte", s_cons
, 0},
1629 {"data", s_change_sec
, 'd'},
1630 {"double", s_float_cons
, 'd'},
1631 {"float", s_float_cons
, 'f'},
1632 {"globl", s_mips_globl
, 0},
1633 {"global", s_mips_globl
, 0},
1634 {"hword", s_cons
, 1},
1636 {"long", s_cons
, 2},
1637 {"octa", s_cons
, 4},
1638 {"quad", s_cons
, 3},
1639 {"section", s_change_section
, 0},
1640 {"short", s_cons
, 1},
1641 {"single", s_float_cons
, 'f'},
1642 {"stabd", s_mips_stab
, 'd'},
1643 {"stabn", s_mips_stab
, 'n'},
1644 {"stabs", s_mips_stab
, 's'},
1645 {"text", s_change_sec
, 't'},
1646 {"word", s_cons
, 2},
1648 { "extern", ecoff_directive_extern
, 0},
1653 static const pseudo_typeS mips_nonecoff_pseudo_table
[] =
1655 /* These pseudo-ops should be defined by the object file format.
1656 However, a.out doesn't support them, so we have versions here. */
1657 {"aent", s_mips_ent
, 1},
1658 {"bgnb", s_ignore
, 0},
1659 {"end", s_mips_end
, 0},
1660 {"endb", s_ignore
, 0},
1661 {"ent", s_mips_ent
, 0},
1662 {"file", s_mips_file
, 0},
1663 {"fmask", s_mips_mask
, 'F'},
1664 {"frame", s_mips_frame
, 0},
1665 {"loc", s_mips_loc
, 0},
1666 {"mask", s_mips_mask
, 'R'},
1667 {"verstamp", s_ignore
, 0},
1671 /* Export the ABI address size for use by TC_ADDRESS_BYTES for the
1672 purpose of the `.dc.a' internal pseudo-op. */
1675 mips_address_bytes (void)
1677 return HAVE_64BIT_ADDRESSES
? 8 : 4;
1680 extern void pop_insert (const pseudo_typeS
*);
1683 mips_pop_insert (void)
1685 pop_insert (mips_pseudo_table
);
1686 if (! ECOFF_DEBUGGING
)
1687 pop_insert (mips_nonecoff_pseudo_table
);
1690 /* Symbols labelling the current insn. */
1692 struct insn_label_list
1694 struct insn_label_list
*next
;
1698 static struct insn_label_list
*free_insn_labels
;
1699 #define label_list tc_segment_info_data.labels
1701 static void mips_clear_insn_labels (void);
1702 static void mips_mark_labels (void);
1703 static void mips_compressed_mark_labels (void);
1706 mips_clear_insn_labels (void)
1708 register struct insn_label_list
**pl
;
1709 segment_info_type
*si
;
1713 for (pl
= &free_insn_labels
; *pl
!= NULL
; pl
= &(*pl
)->next
)
1716 si
= seg_info (now_seg
);
1717 *pl
= si
->label_list
;
1718 si
->label_list
= NULL
;
1722 /* Mark instruction labels in MIPS16/microMIPS mode. */
1725 mips_mark_labels (void)
1727 if (HAVE_CODE_COMPRESSION
)
1728 mips_compressed_mark_labels ();
1731 static char *expr_end
;
1733 /* Expressions which appear in macro instructions. These are set by
1734 mips_ip and read by macro. */
1736 static expressionS imm_expr
;
1737 static expressionS imm2_expr
;
1739 /* The relocatable field in an instruction and the relocs associated
1740 with it. These variables are used for instructions like LUI and
1741 JAL as well as true offsets. They are also used for address
1742 operands in macros. */
1744 static expressionS offset_expr
;
1745 static bfd_reloc_code_real_type offset_reloc
[3]
1746 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
1748 /* This is set to the resulting size of the instruction to be produced
1749 by mips16_ip if an explicit extension is used or by mips_ip if an
1750 explicit size is supplied. */
1752 static unsigned int forced_insn_length
;
1754 /* True if we are assembling an instruction. All dot symbols defined during
1755 this time should be treated as code labels. */
1757 static bfd_boolean mips_assembling_insn
;
1759 /* The pdr segment for per procedure frame/regmask info. Not used for
1762 static segT pdr_seg
;
1764 /* The default target format to use. */
1766 #if defined (TE_FreeBSD)
1767 #define ELF_TARGET(PREFIX, ENDIAN) PREFIX "trad" ENDIAN "mips-freebsd"
1768 #elif defined (TE_TMIPS)
1769 #define ELF_TARGET(PREFIX, ENDIAN) PREFIX "trad" ENDIAN "mips"
1771 #define ELF_TARGET(PREFIX, ENDIAN) PREFIX ENDIAN "mips"
1775 mips_target_format (void)
1777 switch (OUTPUT_FLAVOR
)
1779 case bfd_target_elf_flavour
:
1781 if (!HAVE_64BIT_OBJECTS
&& !HAVE_NEWABI
)
1782 return (target_big_endian
1783 ? "elf32-bigmips-vxworks"
1784 : "elf32-littlemips-vxworks");
1786 return (target_big_endian
1787 ? (HAVE_64BIT_OBJECTS
1788 ? ELF_TARGET ("elf64-", "big")
1790 ? ELF_TARGET ("elf32-n", "big")
1791 : ELF_TARGET ("elf32-", "big")))
1792 : (HAVE_64BIT_OBJECTS
1793 ? ELF_TARGET ("elf64-", "little")
1795 ? ELF_TARGET ("elf32-n", "little")
1796 : ELF_TARGET ("elf32-", "little"))));
1803 /* Return the ISA revision that is currently in use, or 0 if we are
1804 generating code for MIPS V or below. */
1809 if (mips_opts
.isa
== ISA_MIPS32R2
|| mips_opts
.isa
== ISA_MIPS64R2
)
1812 /* microMIPS implies revision 2 or above. */
1813 if (mips_opts
.micromips
)
1816 if (mips_opts
.isa
== ISA_MIPS32
|| mips_opts
.isa
== ISA_MIPS64
)
1822 /* Return the mask of all ASEs that are revisions of those in FLAGS. */
1825 mips_ase_mask (unsigned int flags
)
1829 for (i
= 0; i
< ARRAY_SIZE (mips_ase_groups
); i
++)
1830 if (flags
& mips_ase_groups
[i
])
1831 flags
|= mips_ase_groups
[i
];
1835 /* Check whether the current ISA supports ASE. Issue a warning if
1839 mips_check_isa_supports_ase (const struct mips_ase
*ase
)
1843 static unsigned int warned_isa
;
1844 static unsigned int warned_fp32
;
1846 if (ISA_HAS_64BIT_REGS (mips_opts
.isa
))
1847 min_rev
= mips_opts
.micromips
? ase
->micromips64_rev
: ase
->mips64_rev
;
1849 min_rev
= mips_opts
.micromips
? ase
->micromips32_rev
: ase
->mips32_rev
;
1850 if ((min_rev
< 0 || mips_isa_rev () < min_rev
)
1851 && (warned_isa
& ase
->flags
) != ase
->flags
)
1853 warned_isa
|= ase
->flags
;
1854 base
= mips_opts
.micromips
? "microMIPS" : "MIPS";
1855 size
= ISA_HAS_64BIT_REGS (mips_opts
.isa
) ? 64 : 32;
1857 as_warn (_("The %d-bit %s architecture does not support the"
1858 " `%s' extension"), size
, base
, ase
->name
);
1860 as_warn (_("The `%s' extension requires %s%d revision %d or greater"),
1861 ase
->name
, base
, size
, min_rev
);
1863 if ((ase
->flags
& FP64_ASES
)
1865 && (warned_fp32
& ase
->flags
) != ase
->flags
)
1867 warned_fp32
|= ase
->flags
;
1868 as_warn (_("The `%s' extension requires 64-bit FPRs"), ase
->name
);
1872 /* Check all enabled ASEs to see whether they are supported by the
1873 chosen architecture. */
1876 mips_check_isa_supports_ases (void)
1878 unsigned int i
, mask
;
1880 for (i
= 0; i
< ARRAY_SIZE (mips_ases
); i
++)
1882 mask
= mips_ase_mask (mips_ases
[i
].flags
);
1883 if ((mips_opts
.ase
& mask
) == mips_ases
[i
].flags
)
1884 mips_check_isa_supports_ase (&mips_ases
[i
]);
1888 /* Set the state of ASE to ENABLED_P. Return the mask of ASE_* flags
1889 that were affected. */
1892 mips_set_ase (const struct mips_ase
*ase
, bfd_boolean enabled_p
)
1896 mask
= mips_ase_mask (ase
->flags
);
1897 mips_opts
.ase
&= ~mask
;
1899 mips_opts
.ase
|= ase
->flags
;
1903 /* Return the ASE called NAME, or null if none. */
1905 static const struct mips_ase
*
1906 mips_lookup_ase (const char *name
)
1910 for (i
= 0; i
< ARRAY_SIZE (mips_ases
); i
++)
1911 if (strcmp (name
, mips_ases
[i
].name
) == 0)
1912 return &mips_ases
[i
];
1916 /* Return the length of a microMIPS instruction in bytes. If bits of
1917 the mask beyond the low 16 are 0, then it is a 16-bit instruction.
1918 Otherwise assume a 32-bit instruction; 48-bit instructions (0x1f
1919 major opcode) will require further modifications to the opcode
1922 static inline unsigned int
1923 micromips_insn_length (const struct mips_opcode
*mo
)
1925 return (mo
->mask
>> 16) == 0 ? 2 : 4;
1928 /* Return the length of MIPS16 instruction OPCODE. */
1930 static inline unsigned int
1931 mips16_opcode_length (unsigned long opcode
)
1933 return (opcode
>> 16) == 0 ? 2 : 4;
1936 /* Return the length of instruction INSN. */
1938 static inline unsigned int
1939 insn_length (const struct mips_cl_insn
*insn
)
1941 if (mips_opts
.micromips
)
1942 return micromips_insn_length (insn
->insn_mo
);
1943 else if (mips_opts
.mips16
)
1944 return mips16_opcode_length (insn
->insn_opcode
);
1949 /* Initialise INSN from opcode entry MO. Leave its position unspecified. */
1952 create_insn (struct mips_cl_insn
*insn
, const struct mips_opcode
*mo
)
1957 insn
->insn_opcode
= mo
->match
;
1960 for (i
= 0; i
< ARRAY_SIZE (insn
->fixp
); i
++)
1961 insn
->fixp
[i
] = NULL
;
1962 insn
->fixed_p
= (mips_opts
.noreorder
> 0);
1963 insn
->noreorder_p
= (mips_opts
.noreorder
> 0);
1964 insn
->mips16_absolute_jump_p
= 0;
1965 insn
->complete_p
= 0;
1966 insn
->cleared_p
= 0;
1969 /* Install UVAL as the value of OPERAND in INSN. */
1972 insn_insert_operand (struct mips_cl_insn
*insn
,
1973 const struct mips_operand
*operand
, unsigned int uval
)
1975 insn
->insn_opcode
= mips_insert_operand (operand
, insn
->insn_opcode
, uval
);
1978 /* Record the current MIPS16/microMIPS mode in now_seg. */
1981 mips_record_compressed_mode (void)
1983 segment_info_type
*si
;
1985 si
= seg_info (now_seg
);
1986 if (si
->tc_segment_info_data
.mips16
!= mips_opts
.mips16
)
1987 si
->tc_segment_info_data
.mips16
= mips_opts
.mips16
;
1988 if (si
->tc_segment_info_data
.micromips
!= mips_opts
.micromips
)
1989 si
->tc_segment_info_data
.micromips
= mips_opts
.micromips
;
1992 /* Read a standard MIPS instruction from BUF. */
1994 static unsigned long
1995 read_insn (char *buf
)
1997 if (target_big_endian
)
1998 return bfd_getb32 ((bfd_byte
*) buf
);
2000 return bfd_getl32 ((bfd_byte
*) buf
);
2003 /* Write standard MIPS instruction INSN to BUF. Return a pointer to
2007 write_insn (char *buf
, unsigned int insn
)
2009 md_number_to_chars (buf
, insn
, 4);
2013 /* Read a microMIPS or MIPS16 opcode from BUF, given that it
2014 has length LENGTH. */
2016 static unsigned long
2017 read_compressed_insn (char *buf
, unsigned int length
)
2023 for (i
= 0; i
< length
; i
+= 2)
2026 if (target_big_endian
)
2027 insn
|= bfd_getb16 ((char *) buf
);
2029 insn
|= bfd_getl16 ((char *) buf
);
2035 /* Write microMIPS or MIPS16 instruction INSN to BUF, given that the
2036 instruction is LENGTH bytes long. Return a pointer to the next byte. */
2039 write_compressed_insn (char *buf
, unsigned int insn
, unsigned int length
)
2043 for (i
= 0; i
< length
; i
+= 2)
2044 md_number_to_chars (buf
+ i
, insn
>> ((length
- i
- 2) * 8), 2);
2045 return buf
+ length
;
2048 /* Install INSN at the location specified by its "frag" and "where" fields. */
2051 install_insn (const struct mips_cl_insn
*insn
)
2053 char *f
= insn
->frag
->fr_literal
+ insn
->where
;
2054 if (HAVE_CODE_COMPRESSION
)
2055 write_compressed_insn (f
, insn
->insn_opcode
, insn_length (insn
));
2057 write_insn (f
, insn
->insn_opcode
);
2058 mips_record_compressed_mode ();
2061 /* Move INSN to offset WHERE in FRAG. Adjust the fixups accordingly
2062 and install the opcode in the new location. */
2065 move_insn (struct mips_cl_insn
*insn
, fragS
*frag
, long where
)
2070 insn
->where
= where
;
2071 for (i
= 0; i
< ARRAY_SIZE (insn
->fixp
); i
++)
2072 if (insn
->fixp
[i
] != NULL
)
2074 insn
->fixp
[i
]->fx_frag
= frag
;
2075 insn
->fixp
[i
]->fx_where
= where
;
2077 install_insn (insn
);
2080 /* Add INSN to the end of the output. */
2083 add_fixed_insn (struct mips_cl_insn
*insn
)
2085 char *f
= frag_more (insn_length (insn
));
2086 move_insn (insn
, frag_now
, f
- frag_now
->fr_literal
);
2089 /* Start a variant frag and move INSN to the start of the variant part,
2090 marking it as fixed. The other arguments are as for frag_var. */
2093 add_relaxed_insn (struct mips_cl_insn
*insn
, int max_chars
, int var
,
2094 relax_substateT subtype
, symbolS
*symbol
, offsetT offset
)
2096 frag_grow (max_chars
);
2097 move_insn (insn
, frag_now
, frag_more (0) - frag_now
->fr_literal
);
2099 frag_var (rs_machine_dependent
, max_chars
, var
,
2100 subtype
, symbol
, offset
, NULL
);
2103 /* Insert N copies of INSN into the history buffer, starting at
2104 position FIRST. Neither FIRST nor N need to be clipped. */
2107 insert_into_history (unsigned int first
, unsigned int n
,
2108 const struct mips_cl_insn
*insn
)
2110 if (mips_relax
.sequence
!= 2)
2114 for (i
= ARRAY_SIZE (history
); i
-- > first
;)
2116 history
[i
] = history
[i
- n
];
2122 /* Initialize vr4120_conflicts. There is a bit of duplication here:
2123 the idea is to make it obvious at a glance that each errata is
2127 init_vr4120_conflicts (void)
2129 #define CONFLICT(FIRST, SECOND) \
2130 vr4120_conflicts[FIX_VR4120_##FIRST] |= 1 << FIX_VR4120_##SECOND
2132 /* Errata 21 - [D]DIV[U] after [D]MACC */
2133 CONFLICT (MACC
, DIV
);
2134 CONFLICT (DMACC
, DIV
);
2136 /* Errata 23 - Continuous DMULT[U]/DMACC instructions. */
2137 CONFLICT (DMULT
, DMULT
);
2138 CONFLICT (DMULT
, DMACC
);
2139 CONFLICT (DMACC
, DMULT
);
2140 CONFLICT (DMACC
, DMACC
);
2142 /* Errata 24 - MT{LO,HI} after [D]MACC */
2143 CONFLICT (MACC
, MTHILO
);
2144 CONFLICT (DMACC
, MTHILO
);
2146 /* VR4181A errata MD(1): "If a MULT, MULTU, DMULT or DMULTU
2147 instruction is executed immediately after a MACC or DMACC
2148 instruction, the result of [either instruction] is incorrect." */
2149 CONFLICT (MACC
, MULT
);
2150 CONFLICT (MACC
, DMULT
);
2151 CONFLICT (DMACC
, MULT
);
2152 CONFLICT (DMACC
, DMULT
);
2154 /* VR4181A errata MD(4): "If a MACC or DMACC instruction is
2155 executed immediately after a DMULT, DMULTU, DIV, DIVU,
2156 DDIV or DDIVU instruction, the result of the MACC or
2157 DMACC instruction is incorrect.". */
2158 CONFLICT (DMULT
, MACC
);
2159 CONFLICT (DMULT
, DMACC
);
2160 CONFLICT (DIV
, MACC
);
2161 CONFLICT (DIV
, DMACC
);
2171 #define RTYPE_MASK 0x1ff00
2172 #define RTYPE_NUM 0x00100
2173 #define RTYPE_FPU 0x00200
2174 #define RTYPE_FCC 0x00400
2175 #define RTYPE_VEC 0x00800
2176 #define RTYPE_GP 0x01000
2177 #define RTYPE_CP0 0x02000
2178 #define RTYPE_PC 0x04000
2179 #define RTYPE_ACC 0x08000
2180 #define RTYPE_CCC 0x10000
2181 #define RNUM_MASK 0x000ff
2182 #define RWARN 0x80000
2184 #define GENERIC_REGISTER_NUMBERS \
2185 {"$0", RTYPE_NUM | 0}, \
2186 {"$1", RTYPE_NUM | 1}, \
2187 {"$2", RTYPE_NUM | 2}, \
2188 {"$3", RTYPE_NUM | 3}, \
2189 {"$4", RTYPE_NUM | 4}, \
2190 {"$5", RTYPE_NUM | 5}, \
2191 {"$6", RTYPE_NUM | 6}, \
2192 {"$7", RTYPE_NUM | 7}, \
2193 {"$8", RTYPE_NUM | 8}, \
2194 {"$9", RTYPE_NUM | 9}, \
2195 {"$10", RTYPE_NUM | 10}, \
2196 {"$11", RTYPE_NUM | 11}, \
2197 {"$12", RTYPE_NUM | 12}, \
2198 {"$13", RTYPE_NUM | 13}, \
2199 {"$14", RTYPE_NUM | 14}, \
2200 {"$15", RTYPE_NUM | 15}, \
2201 {"$16", RTYPE_NUM | 16}, \
2202 {"$17", RTYPE_NUM | 17}, \
2203 {"$18", RTYPE_NUM | 18}, \
2204 {"$19", RTYPE_NUM | 19}, \
2205 {"$20", RTYPE_NUM | 20}, \
2206 {"$21", RTYPE_NUM | 21}, \
2207 {"$22", RTYPE_NUM | 22}, \
2208 {"$23", RTYPE_NUM | 23}, \
2209 {"$24", RTYPE_NUM | 24}, \
2210 {"$25", RTYPE_NUM | 25}, \
2211 {"$26", RTYPE_NUM | 26}, \
2212 {"$27", RTYPE_NUM | 27}, \
2213 {"$28", RTYPE_NUM | 28}, \
2214 {"$29", RTYPE_NUM | 29}, \
2215 {"$30", RTYPE_NUM | 30}, \
2216 {"$31", RTYPE_NUM | 31}
2218 #define FPU_REGISTER_NAMES \
2219 {"$f0", RTYPE_FPU | 0}, \
2220 {"$f1", RTYPE_FPU | 1}, \
2221 {"$f2", RTYPE_FPU | 2}, \
2222 {"$f3", RTYPE_FPU | 3}, \
2223 {"$f4", RTYPE_FPU | 4}, \
2224 {"$f5", RTYPE_FPU | 5}, \
2225 {"$f6", RTYPE_FPU | 6}, \
2226 {"$f7", RTYPE_FPU | 7}, \
2227 {"$f8", RTYPE_FPU | 8}, \
2228 {"$f9", RTYPE_FPU | 9}, \
2229 {"$f10", RTYPE_FPU | 10}, \
2230 {"$f11", RTYPE_FPU | 11}, \
2231 {"$f12", RTYPE_FPU | 12}, \
2232 {"$f13", RTYPE_FPU | 13}, \
2233 {"$f14", RTYPE_FPU | 14}, \
2234 {"$f15", RTYPE_FPU | 15}, \
2235 {"$f16", RTYPE_FPU | 16}, \
2236 {"$f17", RTYPE_FPU | 17}, \
2237 {"$f18", RTYPE_FPU | 18}, \
2238 {"$f19", RTYPE_FPU | 19}, \
2239 {"$f20", RTYPE_FPU | 20}, \
2240 {"$f21", RTYPE_FPU | 21}, \
2241 {"$f22", RTYPE_FPU | 22}, \
2242 {"$f23", RTYPE_FPU | 23}, \
2243 {"$f24", RTYPE_FPU | 24}, \
2244 {"$f25", RTYPE_FPU | 25}, \
2245 {"$f26", RTYPE_FPU | 26}, \
2246 {"$f27", RTYPE_FPU | 27}, \
2247 {"$f28", RTYPE_FPU | 28}, \
2248 {"$f29", RTYPE_FPU | 29}, \
2249 {"$f30", RTYPE_FPU | 30}, \
2250 {"$f31", RTYPE_FPU | 31}
2252 #define FPU_CONDITION_CODE_NAMES \
2253 {"$fcc0", RTYPE_FCC | 0}, \
2254 {"$fcc1", RTYPE_FCC | 1}, \
2255 {"$fcc2", RTYPE_FCC | 2}, \
2256 {"$fcc3", RTYPE_FCC | 3}, \
2257 {"$fcc4", RTYPE_FCC | 4}, \
2258 {"$fcc5", RTYPE_FCC | 5}, \
2259 {"$fcc6", RTYPE_FCC | 6}, \
2260 {"$fcc7", RTYPE_FCC | 7}
2262 #define COPROC_CONDITION_CODE_NAMES \
2263 {"$cc0", RTYPE_FCC | RTYPE_CCC | 0}, \
2264 {"$cc1", RTYPE_FCC | RTYPE_CCC | 1}, \
2265 {"$cc2", RTYPE_FCC | RTYPE_CCC | 2}, \
2266 {"$cc3", RTYPE_FCC | RTYPE_CCC | 3}, \
2267 {"$cc4", RTYPE_FCC | RTYPE_CCC | 4}, \
2268 {"$cc5", RTYPE_FCC | RTYPE_CCC | 5}, \
2269 {"$cc6", RTYPE_FCC | RTYPE_CCC | 6}, \
2270 {"$cc7", RTYPE_FCC | RTYPE_CCC | 7}
2272 #define N32N64_SYMBOLIC_REGISTER_NAMES \
2273 {"$a4", RTYPE_GP | 8}, \
2274 {"$a5", RTYPE_GP | 9}, \
2275 {"$a6", RTYPE_GP | 10}, \
2276 {"$a7", RTYPE_GP | 11}, \
2277 {"$ta0", RTYPE_GP | 8}, /* alias for $a4 */ \
2278 {"$ta1", RTYPE_GP | 9}, /* alias for $a5 */ \
2279 {"$ta2", RTYPE_GP | 10}, /* alias for $a6 */ \
2280 {"$ta3", RTYPE_GP | 11}, /* alias for $a7 */ \
2281 {"$t0", RTYPE_GP | 12}, \
2282 {"$t1", RTYPE_GP | 13}, \
2283 {"$t2", RTYPE_GP | 14}, \
2284 {"$t3", RTYPE_GP | 15}
2286 #define O32_SYMBOLIC_REGISTER_NAMES \
2287 {"$t0", RTYPE_GP | 8}, \
2288 {"$t1", RTYPE_GP | 9}, \
2289 {"$t2", RTYPE_GP | 10}, \
2290 {"$t3", RTYPE_GP | 11}, \
2291 {"$t4", RTYPE_GP | 12}, \
2292 {"$t5", RTYPE_GP | 13}, \
2293 {"$t6", RTYPE_GP | 14}, \
2294 {"$t7", RTYPE_GP | 15}, \
2295 {"$ta0", RTYPE_GP | 12}, /* alias for $t4 */ \
2296 {"$ta1", RTYPE_GP | 13}, /* alias for $t5 */ \
2297 {"$ta2", RTYPE_GP | 14}, /* alias for $t6 */ \
2298 {"$ta3", RTYPE_GP | 15} /* alias for $t7 */
2300 /* Remaining symbolic register names */
2301 #define SYMBOLIC_REGISTER_NAMES \
2302 {"$zero", RTYPE_GP | 0}, \
2303 {"$at", RTYPE_GP | 1}, \
2304 {"$AT", RTYPE_GP | 1}, \
2305 {"$v0", RTYPE_GP | 2}, \
2306 {"$v1", RTYPE_GP | 3}, \
2307 {"$a0", RTYPE_GP | 4}, \
2308 {"$a1", RTYPE_GP | 5}, \
2309 {"$a2", RTYPE_GP | 6}, \
2310 {"$a3", RTYPE_GP | 7}, \
2311 {"$s0", RTYPE_GP | 16}, \
2312 {"$s1", RTYPE_GP | 17}, \
2313 {"$s2", RTYPE_GP | 18}, \
2314 {"$s3", RTYPE_GP | 19}, \
2315 {"$s4", RTYPE_GP | 20}, \
2316 {"$s5", RTYPE_GP | 21}, \
2317 {"$s6", RTYPE_GP | 22}, \
2318 {"$s7", RTYPE_GP | 23}, \
2319 {"$t8", RTYPE_GP | 24}, \
2320 {"$t9", RTYPE_GP | 25}, \
2321 {"$k0", RTYPE_GP | 26}, \
2322 {"$kt0", RTYPE_GP | 26}, \
2323 {"$k1", RTYPE_GP | 27}, \
2324 {"$kt1", RTYPE_GP | 27}, \
2325 {"$gp", RTYPE_GP | 28}, \
2326 {"$sp", RTYPE_GP | 29}, \
2327 {"$s8", RTYPE_GP | 30}, \
2328 {"$fp", RTYPE_GP | 30}, \
2329 {"$ra", RTYPE_GP | 31}
2331 #define MIPS16_SPECIAL_REGISTER_NAMES \
2332 {"$pc", RTYPE_PC | 0}
2334 #define MDMX_VECTOR_REGISTER_NAMES \
2335 /* {"$v0", RTYPE_VEC | 0}, clash with REG 2 above */ \
2336 /* {"$v1", RTYPE_VEC | 1}, clash with REG 3 above */ \
2337 {"$v2", RTYPE_VEC | 2}, \
2338 {"$v3", RTYPE_VEC | 3}, \
2339 {"$v4", RTYPE_VEC | 4}, \
2340 {"$v5", RTYPE_VEC | 5}, \
2341 {"$v6", RTYPE_VEC | 6}, \
2342 {"$v7", RTYPE_VEC | 7}, \
2343 {"$v8", RTYPE_VEC | 8}, \
2344 {"$v9", RTYPE_VEC | 9}, \
2345 {"$v10", RTYPE_VEC | 10}, \
2346 {"$v11", RTYPE_VEC | 11}, \
2347 {"$v12", RTYPE_VEC | 12}, \
2348 {"$v13", RTYPE_VEC | 13}, \
2349 {"$v14", RTYPE_VEC | 14}, \
2350 {"$v15", RTYPE_VEC | 15}, \
2351 {"$v16", RTYPE_VEC | 16}, \
2352 {"$v17", RTYPE_VEC | 17}, \
2353 {"$v18", RTYPE_VEC | 18}, \
2354 {"$v19", RTYPE_VEC | 19}, \
2355 {"$v20", RTYPE_VEC | 20}, \
2356 {"$v21", RTYPE_VEC | 21}, \
2357 {"$v22", RTYPE_VEC | 22}, \
2358 {"$v23", RTYPE_VEC | 23}, \
2359 {"$v24", RTYPE_VEC | 24}, \
2360 {"$v25", RTYPE_VEC | 25}, \
2361 {"$v26", RTYPE_VEC | 26}, \
2362 {"$v27", RTYPE_VEC | 27}, \
2363 {"$v28", RTYPE_VEC | 28}, \
2364 {"$v29", RTYPE_VEC | 29}, \
2365 {"$v30", RTYPE_VEC | 30}, \
2366 {"$v31", RTYPE_VEC | 31}
2368 #define MIPS_DSP_ACCUMULATOR_NAMES \
2369 {"$ac0", RTYPE_ACC | 0}, \
2370 {"$ac1", RTYPE_ACC | 1}, \
2371 {"$ac2", RTYPE_ACC | 2}, \
2372 {"$ac3", RTYPE_ACC | 3}
2374 static const struct regname reg_names
[] = {
2375 GENERIC_REGISTER_NUMBERS
,
2377 FPU_CONDITION_CODE_NAMES
,
2378 COPROC_CONDITION_CODE_NAMES
,
2380 /* The $txx registers depends on the abi,
2381 these will be added later into the symbol table from
2382 one of the tables below once mips_abi is set after
2383 parsing of arguments from the command line. */
2384 SYMBOLIC_REGISTER_NAMES
,
2386 MIPS16_SPECIAL_REGISTER_NAMES
,
2387 MDMX_VECTOR_REGISTER_NAMES
,
2388 MIPS_DSP_ACCUMULATOR_NAMES
,
2392 static const struct regname reg_names_o32
[] = {
2393 O32_SYMBOLIC_REGISTER_NAMES
,
2397 static const struct regname reg_names_n32n64
[] = {
2398 N32N64_SYMBOLIC_REGISTER_NAMES
,
2402 /* Check if S points at a valid register specifier according to TYPES.
2403 If so, then return 1, advance S to consume the specifier and store
2404 the register's number in REGNOP, otherwise return 0. */
2407 reg_lookup (char **s
, unsigned int types
, unsigned int *regnop
)
2414 /* Find end of name. */
2416 if (is_name_beginner (*e
))
2418 while (is_part_of_name (*e
))
2421 /* Terminate name. */
2425 /* Look for a register symbol. */
2426 if ((symbolP
= symbol_find (*s
)) && S_GET_SEGMENT (symbolP
) == reg_section
)
2428 int r
= S_GET_VALUE (symbolP
);
2430 reg
= r
& RNUM_MASK
;
2431 else if ((types
& RTYPE_VEC
) && (r
& ~1) == (RTYPE_GP
| 2))
2432 /* Convert GP reg $v0/1 to MDMX reg $v0/1! */
2433 reg
= (r
& RNUM_MASK
) - 2;
2435 /* Else see if this is a register defined in an itbl entry. */
2436 else if ((types
& RTYPE_GP
) && itbl_have_entries
)
2443 if (itbl_get_reg_val (n
, &r
))
2444 reg
= r
& RNUM_MASK
;
2447 /* Advance to next token if a register was recognised. */
2450 else if (types
& RWARN
)
2451 as_warn (_("Unrecognized register name `%s'"), *s
);
2459 /* Check if S points at a valid register list according to TYPES.
2460 If so, then return 1, advance S to consume the list and store
2461 the registers present on the list as a bitmask of ones in REGLISTP,
2462 otherwise return 0. A valid list comprises a comma-separated
2463 enumeration of valid single registers and/or dash-separated
2464 contiguous register ranges as determined by their numbers.
2466 As a special exception if one of s0-s7 registers is specified as
2467 the range's lower delimiter and s8 (fp) is its upper one, then no
2468 registers whose numbers place them between s7 and s8 (i.e. $24-$29)
2469 are selected; they have to be listed separately if needed. */
2472 reglist_lookup (char **s
, unsigned int types
, unsigned int *reglistp
)
2474 unsigned int reglist
= 0;
2475 unsigned int lastregno
;
2476 bfd_boolean ok
= TRUE
;
2477 unsigned int regmask
;
2478 char *s_endlist
= *s
;
2482 while (reg_lookup (s
, types
, ®no
))
2488 ok
= reg_lookup (s
, types
, &lastregno
);
2489 if (ok
&& lastregno
< regno
)
2495 if (lastregno
== FP
&& regno
>= S0
&& regno
<= S7
)
2500 regmask
= 1 << lastregno
;
2501 regmask
= (regmask
<< 1) - 1;
2502 regmask
^= (1 << regno
) - 1;
2516 *reglistp
= reglist
;
2517 return ok
&& reglist
!= 0;
2520 /* Return TRUE if opcode MO is valid on the currently selected ISA, ASE
2521 and architecture. Use is_opcode_valid_16 for MIPS16 opcodes. */
2524 is_opcode_valid (const struct mips_opcode
*mo
)
2526 int isa
= mips_opts
.isa
;
2527 int ase
= mips_opts
.ase
;
2531 if (ISA_HAS_64BIT_REGS (mips_opts
.isa
))
2532 for (i
= 0; i
< ARRAY_SIZE (mips_ases
); i
++)
2533 if ((ase
& mips_ases
[i
].flags
) == mips_ases
[i
].flags
)
2534 ase
|= mips_ases
[i
].flags64
;
2536 if (!opcode_is_member (mo
, isa
, ase
, mips_opts
.arch
))
2539 /* Check whether the instruction or macro requires single-precision or
2540 double-precision floating-point support. Note that this information is
2541 stored differently in the opcode table for insns and macros. */
2542 if (mo
->pinfo
== INSN_MACRO
)
2544 fp_s
= mo
->pinfo2
& INSN2_M_FP_S
;
2545 fp_d
= mo
->pinfo2
& INSN2_M_FP_D
;
2549 fp_s
= mo
->pinfo
& FP_S
;
2550 fp_d
= mo
->pinfo
& FP_D
;
2553 if (fp_d
&& (mips_opts
.soft_float
|| mips_opts
.single_float
))
2556 if (fp_s
&& mips_opts
.soft_float
)
2562 /* Return TRUE if the MIPS16 opcode MO is valid on the currently
2563 selected ISA and architecture. */
2566 is_opcode_valid_16 (const struct mips_opcode
*mo
)
2568 return opcode_is_member (mo
, mips_opts
.isa
, 0, mips_opts
.arch
);
2571 /* Return TRUE if the size of the microMIPS opcode MO matches one
2572 explicitly requested. Always TRUE in the standard MIPS mode. */
2575 is_size_valid (const struct mips_opcode
*mo
)
2577 if (!mips_opts
.micromips
)
2580 if (mips_opts
.insn32
)
2582 if (mo
->pinfo
!= INSN_MACRO
&& micromips_insn_length (mo
) != 4)
2584 if ((mo
->pinfo2
& INSN2_BRANCH_DELAY_16BIT
) != 0)
2587 if (!forced_insn_length
)
2589 if (mo
->pinfo
== INSN_MACRO
)
2591 return forced_insn_length
== micromips_insn_length (mo
);
2594 /* Return TRUE if the microMIPS opcode MO is valid for the delay slot
2595 of the preceding instruction. Always TRUE in the standard MIPS mode.
2597 We don't accept macros in 16-bit delay slots to avoid a case where
2598 a macro expansion fails because it relies on a preceding 32-bit real
2599 instruction to have matched and does not handle the operands correctly.
2600 The only macros that may expand to 16-bit instructions are JAL that
2601 cannot be placed in a delay slot anyway, and corner cases of BALIGN
2602 and BGT (that likewise cannot be placed in a delay slot) that decay to
2603 a NOP. In all these cases the macros precede any corresponding real
2604 instruction definitions in the opcode table, so they will match in the
2605 second pass where the size of the delay slot is ignored and therefore
2606 produce correct code. */
2609 is_delay_slot_valid (const struct mips_opcode
*mo
)
2611 if (!mips_opts
.micromips
)
2614 if (mo
->pinfo
== INSN_MACRO
)
2615 return (history
[0].insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_16BIT
) == 0;
2616 if ((history
[0].insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_32BIT
) != 0
2617 && micromips_insn_length (mo
) != 4)
2619 if ((history
[0].insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_16BIT
) != 0
2620 && micromips_insn_length (mo
) != 2)
2626 /* For consistency checking, verify that all bits of OPCODE are
2627 specified either by the match/mask part of the instruction
2628 definition, or by the operand list. INSN_BITS says which
2629 bits of the instruction are significant and DECODE_OPERAND
2630 provides the mips_operand description of each operand. */
2633 validate_mips_insn (const struct mips_opcode
*opcode
,
2634 unsigned long insn_bits
,
2635 const struct mips_operand
*(*decode_operand
) (const char *))
2638 unsigned long used_bits
, doubled
, undefined
;
2639 const struct mips_operand
*operand
;
2641 if ((opcode
->mask
& opcode
->match
) != opcode
->match
)
2643 as_bad (_("internal: bad mips opcode (mask error): %s %s"),
2644 opcode
->name
, opcode
->args
);
2648 for (s
= opcode
->args
; *s
; ++s
)
2657 operand
= decode_operand (s
);
2660 as_bad (_("internal: unknown operand type: %s %s"),
2661 opcode
->name
, opcode
->args
);
2664 used_bits
|= ((1 << operand
->size
) - 1) << operand
->lsb
;
2665 if (operand
->type
== OP_MDMX_IMM_REG
)
2666 /* Bit 5 is the format selector (OB vs QH). The opcode table
2667 has separate entries for each format. */
2668 used_bits
&= ~(1 << (operand
->lsb
+ 5));
2669 /* Skip prefix characters. */
2670 if (*s
== '+' || *s
== 'm')
2674 doubled
= used_bits
& opcode
->mask
& insn_bits
;
2677 as_bad (_("internal: bad mips opcode (bits 0x%08lx doubly defined):"
2678 " %s %s"), doubled
, opcode
->name
, opcode
->args
);
2681 used_bits
|= opcode
->mask
;
2682 undefined
= ~used_bits
& insn_bits
;
2685 as_bad (_("internal: bad mips opcode (bits 0x%08lx undefined): %s %s"),
2686 undefined
, opcode
->name
, opcode
->args
);
2689 used_bits
&= ~insn_bits
;
2692 as_bad (_("internal: bad mips opcode (bits 0x%08lx defined): %s %s"),
2693 used_bits
, opcode
->name
, opcode
->args
);
2699 /* The microMIPS version of validate_mips_insn. */
2702 validate_micromips_insn (const struct mips_opcode
*opc
)
2704 unsigned long insn_bits
;
2705 unsigned long major
;
2706 unsigned int length
;
2708 length
= micromips_insn_length (opc
);
2709 if (length
!= 2 && length
!= 4)
2711 as_bad (_("Internal error: bad microMIPS opcode (incorrect length: %u): "
2712 "%s %s"), length
, opc
->name
, opc
->args
);
2715 major
= opc
->match
>> (10 + 8 * (length
- 2));
2716 if ((length
== 2 && (major
& 7) != 1 && (major
& 6) != 2)
2717 || (length
== 4 && (major
& 7) != 0 && (major
& 4) != 4))
2719 as_bad (_("Internal error: bad microMIPS opcode "
2720 "(opcode/length mismatch): %s %s"), opc
->name
, opc
->args
);
2724 /* Shift piecewise to avoid an overflow where unsigned long is 32-bit. */
2725 insn_bits
= 1 << 4 * length
;
2726 insn_bits
<<= 4 * length
;
2728 return validate_mips_insn (opc
, insn_bits
, decode_micromips_operand
);
2731 /* This function is called once, at assembler startup time. It should set up
2732 all the tables, etc. that the MD part of the assembler will need. */
2737 const char *retval
= NULL
;
2741 if (mips_pic
!= NO_PIC
)
2743 if (g_switch_seen
&& g_switch_value
!= 0)
2744 as_bad (_("-G may not be used in position-independent code"));
2748 if (! bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, file_mips_arch
))
2749 as_warn (_("Could not set architecture and machine"));
2751 op_hash
= hash_new ();
2753 for (i
= 0; i
< NUMOPCODES
;)
2755 const char *name
= mips_opcodes
[i
].name
;
2757 retval
= hash_insert (op_hash
, name
, (void *) &mips_opcodes
[i
]);
2760 fprintf (stderr
, _("internal error: can't hash `%s': %s\n"),
2761 mips_opcodes
[i
].name
, retval
);
2762 /* Probably a memory allocation problem? Give up now. */
2763 as_fatal (_("Broken assembler. No assembly attempted."));
2767 if (mips_opcodes
[i
].pinfo
!= INSN_MACRO
)
2769 if (!validate_mips_insn (&mips_opcodes
[i
], 0xffffffff,
2770 decode_mips_operand
))
2772 if (nop_insn
.insn_mo
== NULL
&& strcmp (name
, "nop") == 0)
2774 create_insn (&nop_insn
, mips_opcodes
+ i
);
2775 if (mips_fix_loongson2f_nop
)
2776 nop_insn
.insn_opcode
= LOONGSON2F_NOP_INSN
;
2777 nop_insn
.fixed_p
= 1;
2782 while ((i
< NUMOPCODES
) && !strcmp (mips_opcodes
[i
].name
, name
));
2785 mips16_op_hash
= hash_new ();
2788 while (i
< bfd_mips16_num_opcodes
)
2790 const char *name
= mips16_opcodes
[i
].name
;
2792 retval
= hash_insert (mips16_op_hash
, name
, (void *) &mips16_opcodes
[i
]);
2794 as_fatal (_("internal: can't hash `%s': %s"),
2795 mips16_opcodes
[i
].name
, retval
);
2798 if (mips16_opcodes
[i
].pinfo
!= INSN_MACRO
2799 && ((mips16_opcodes
[i
].match
& mips16_opcodes
[i
].mask
)
2800 != mips16_opcodes
[i
].match
))
2802 fprintf (stderr
, _("internal error: bad mips16 opcode: %s %s\n"),
2803 mips16_opcodes
[i
].name
, mips16_opcodes
[i
].args
);
2806 if (mips16_nop_insn
.insn_mo
== NULL
&& strcmp (name
, "nop") == 0)
2808 create_insn (&mips16_nop_insn
, mips16_opcodes
+ i
);
2809 mips16_nop_insn
.fixed_p
= 1;
2813 while (i
< bfd_mips16_num_opcodes
2814 && strcmp (mips16_opcodes
[i
].name
, name
) == 0);
2817 micromips_op_hash
= hash_new ();
2820 while (i
< bfd_micromips_num_opcodes
)
2822 const char *name
= micromips_opcodes
[i
].name
;
2824 retval
= hash_insert (micromips_op_hash
, name
,
2825 (void *) µmips_opcodes
[i
]);
2827 as_fatal (_("internal: can't hash `%s': %s"),
2828 micromips_opcodes
[i
].name
, retval
);
2830 if (micromips_opcodes
[i
].pinfo
!= INSN_MACRO
)
2832 struct mips_cl_insn
*micromips_nop_insn
;
2834 if (!validate_micromips_insn (µmips_opcodes
[i
]))
2837 if (micromips_insn_length (micromips_opcodes
+ i
) == 2)
2838 micromips_nop_insn
= µmips_nop16_insn
;
2839 else if (micromips_insn_length (micromips_opcodes
+ i
) == 4)
2840 micromips_nop_insn
= µmips_nop32_insn
;
2844 if (micromips_nop_insn
->insn_mo
== NULL
2845 && strcmp (name
, "nop") == 0)
2847 create_insn (micromips_nop_insn
, micromips_opcodes
+ i
);
2848 micromips_nop_insn
->fixed_p
= 1;
2851 while (++i
< bfd_micromips_num_opcodes
2852 && strcmp (micromips_opcodes
[i
].name
, name
) == 0);
2856 as_fatal (_("Broken assembler. No assembly attempted."));
2858 /* We add all the general register names to the symbol table. This
2859 helps us detect invalid uses of them. */
2860 for (i
= 0; reg_names
[i
].name
; i
++)
2861 symbol_table_insert (symbol_new (reg_names
[i
].name
, reg_section
,
2862 reg_names
[i
].num
, /* & RNUM_MASK, */
2863 &zero_address_frag
));
2865 for (i
= 0; reg_names_n32n64
[i
].name
; i
++)
2866 symbol_table_insert (symbol_new (reg_names_n32n64
[i
].name
, reg_section
,
2867 reg_names_n32n64
[i
].num
, /* & RNUM_MASK, */
2868 &zero_address_frag
));
2870 for (i
= 0; reg_names_o32
[i
].name
; i
++)
2871 symbol_table_insert (symbol_new (reg_names_o32
[i
].name
, reg_section
,
2872 reg_names_o32
[i
].num
, /* & RNUM_MASK, */
2873 &zero_address_frag
));
2875 mips_no_prev_insn ();
2878 mips_cprmask
[0] = 0;
2879 mips_cprmask
[1] = 0;
2880 mips_cprmask
[2] = 0;
2881 mips_cprmask
[3] = 0;
2883 /* set the default alignment for the text section (2**2) */
2884 record_alignment (text_section
, 2);
2886 bfd_set_gp_size (stdoutput
, g_switch_value
);
2888 /* On a native system other than VxWorks, sections must be aligned
2889 to 16 byte boundaries. When configured for an embedded ELF
2890 target, we don't bother. */
2891 if (strncmp (TARGET_OS
, "elf", 3) != 0
2892 && strncmp (TARGET_OS
, "vxworks", 7) != 0)
2894 (void) bfd_set_section_alignment (stdoutput
, text_section
, 4);
2895 (void) bfd_set_section_alignment (stdoutput
, data_section
, 4);
2896 (void) bfd_set_section_alignment (stdoutput
, bss_section
, 4);
2899 /* Create a .reginfo section for register masks and a .mdebug
2900 section for debugging information. */
2908 subseg
= now_subseg
;
2910 /* The ABI says this section should be loaded so that the
2911 running program can access it. However, we don't load it
2912 if we are configured for an embedded target */
2913 flags
= SEC_READONLY
| SEC_DATA
;
2914 if (strncmp (TARGET_OS
, "elf", 3) != 0)
2915 flags
|= SEC_ALLOC
| SEC_LOAD
;
2917 if (mips_abi
!= N64_ABI
)
2919 sec
= subseg_new (".reginfo", (subsegT
) 0);
2921 bfd_set_section_flags (stdoutput
, sec
, flags
);
2922 bfd_set_section_alignment (stdoutput
, sec
, HAVE_NEWABI
? 3 : 2);
2924 mips_regmask_frag
= frag_more (sizeof (Elf32_External_RegInfo
));
2928 /* The 64-bit ABI uses a .MIPS.options section rather than
2929 .reginfo section. */
2930 sec
= subseg_new (".MIPS.options", (subsegT
) 0);
2931 bfd_set_section_flags (stdoutput
, sec
, flags
);
2932 bfd_set_section_alignment (stdoutput
, sec
, 3);
2934 /* Set up the option header. */
2936 Elf_Internal_Options opthdr
;
2939 opthdr
.kind
= ODK_REGINFO
;
2940 opthdr
.size
= (sizeof (Elf_External_Options
)
2941 + sizeof (Elf64_External_RegInfo
));
2944 f
= frag_more (sizeof (Elf_External_Options
));
2945 bfd_mips_elf_swap_options_out (stdoutput
, &opthdr
,
2946 (Elf_External_Options
*) f
);
2948 mips_regmask_frag
= frag_more (sizeof (Elf64_External_RegInfo
));
2952 if (ECOFF_DEBUGGING
)
2954 sec
= subseg_new (".mdebug", (subsegT
) 0);
2955 (void) bfd_set_section_flags (stdoutput
, sec
,
2956 SEC_HAS_CONTENTS
| SEC_READONLY
);
2957 (void) bfd_set_section_alignment (stdoutput
, sec
, 2);
2959 else if (mips_flag_pdr
)
2961 pdr_seg
= subseg_new (".pdr", (subsegT
) 0);
2962 (void) bfd_set_section_flags (stdoutput
, pdr_seg
,
2963 SEC_READONLY
| SEC_RELOC
2965 (void) bfd_set_section_alignment (stdoutput
, pdr_seg
, 2);
2968 subseg_set (seg
, subseg
);
2971 if (! ECOFF_DEBUGGING
)
2974 if (mips_fix_vr4120
)
2975 init_vr4120_conflicts ();
2981 mips_emit_delays ();
2982 if (! ECOFF_DEBUGGING
)
2987 md_assemble (char *str
)
2989 struct mips_cl_insn insn
;
2990 bfd_reloc_code_real_type unused_reloc
[3]
2991 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
2993 imm_expr
.X_op
= O_absent
;
2994 imm2_expr
.X_op
= O_absent
;
2995 offset_expr
.X_op
= O_absent
;
2996 offset_reloc
[0] = BFD_RELOC_UNUSED
;
2997 offset_reloc
[1] = BFD_RELOC_UNUSED
;
2998 offset_reloc
[2] = BFD_RELOC_UNUSED
;
3000 mips_mark_labels ();
3001 mips_assembling_insn
= TRUE
;
3003 if (mips_opts
.mips16
)
3004 mips16_ip (str
, &insn
);
3007 mips_ip (str
, &insn
);
3008 DBG ((_("returned from mips_ip(%s) insn_opcode = 0x%x\n"),
3009 str
, insn
.insn_opcode
));
3013 as_bad ("%s `%s'", insn_error
, str
);
3014 else if (insn
.insn_mo
->pinfo
== INSN_MACRO
)
3017 if (mips_opts
.mips16
)
3018 mips16_macro (&insn
);
3025 if (offset_expr
.X_op
!= O_absent
)
3026 append_insn (&insn
, &offset_expr
, offset_reloc
, FALSE
);
3028 append_insn (&insn
, NULL
, unused_reloc
, FALSE
);
3031 mips_assembling_insn
= FALSE
;
3034 /* Convenience functions for abstracting away the differences between
3035 MIPS16 and non-MIPS16 relocations. */
3037 static inline bfd_boolean
3038 mips16_reloc_p (bfd_reloc_code_real_type reloc
)
3042 case BFD_RELOC_MIPS16_JMP
:
3043 case BFD_RELOC_MIPS16_GPREL
:
3044 case BFD_RELOC_MIPS16_GOT16
:
3045 case BFD_RELOC_MIPS16_CALL16
:
3046 case BFD_RELOC_MIPS16_HI16_S
:
3047 case BFD_RELOC_MIPS16_HI16
:
3048 case BFD_RELOC_MIPS16_LO16
:
3056 static inline bfd_boolean
3057 micromips_reloc_p (bfd_reloc_code_real_type reloc
)
3061 case BFD_RELOC_MICROMIPS_7_PCREL_S1
:
3062 case BFD_RELOC_MICROMIPS_10_PCREL_S1
:
3063 case BFD_RELOC_MICROMIPS_16_PCREL_S1
:
3064 case BFD_RELOC_MICROMIPS_GPREL16
:
3065 case BFD_RELOC_MICROMIPS_JMP
:
3066 case BFD_RELOC_MICROMIPS_HI16
:
3067 case BFD_RELOC_MICROMIPS_HI16_S
:
3068 case BFD_RELOC_MICROMIPS_LO16
:
3069 case BFD_RELOC_MICROMIPS_LITERAL
:
3070 case BFD_RELOC_MICROMIPS_GOT16
:
3071 case BFD_RELOC_MICROMIPS_CALL16
:
3072 case BFD_RELOC_MICROMIPS_GOT_HI16
:
3073 case BFD_RELOC_MICROMIPS_GOT_LO16
:
3074 case BFD_RELOC_MICROMIPS_CALL_HI16
:
3075 case BFD_RELOC_MICROMIPS_CALL_LO16
:
3076 case BFD_RELOC_MICROMIPS_SUB
:
3077 case BFD_RELOC_MICROMIPS_GOT_PAGE
:
3078 case BFD_RELOC_MICROMIPS_GOT_OFST
:
3079 case BFD_RELOC_MICROMIPS_GOT_DISP
:
3080 case BFD_RELOC_MICROMIPS_HIGHEST
:
3081 case BFD_RELOC_MICROMIPS_HIGHER
:
3082 case BFD_RELOC_MICROMIPS_SCN_DISP
:
3083 case BFD_RELOC_MICROMIPS_JALR
:
3091 static inline bfd_boolean
3092 jmp_reloc_p (bfd_reloc_code_real_type reloc
)
3094 return reloc
== BFD_RELOC_MIPS_JMP
|| reloc
== BFD_RELOC_MICROMIPS_JMP
;
3097 static inline bfd_boolean
3098 got16_reloc_p (bfd_reloc_code_real_type reloc
)
3100 return (reloc
== BFD_RELOC_MIPS_GOT16
|| reloc
== BFD_RELOC_MIPS16_GOT16
3101 || reloc
== BFD_RELOC_MICROMIPS_GOT16
);
3104 static inline bfd_boolean
3105 hi16_reloc_p (bfd_reloc_code_real_type reloc
)
3107 return (reloc
== BFD_RELOC_HI16_S
|| reloc
== BFD_RELOC_MIPS16_HI16_S
3108 || reloc
== BFD_RELOC_MICROMIPS_HI16_S
);
3111 static inline bfd_boolean
3112 lo16_reloc_p (bfd_reloc_code_real_type reloc
)
3114 return (reloc
== BFD_RELOC_LO16
|| reloc
== BFD_RELOC_MIPS16_LO16
3115 || reloc
== BFD_RELOC_MICROMIPS_LO16
);
3118 static inline bfd_boolean
3119 jalr_reloc_p (bfd_reloc_code_real_type reloc
)
3121 return reloc
== BFD_RELOC_MIPS_JALR
|| reloc
== BFD_RELOC_MICROMIPS_JALR
;
3124 static inline bfd_boolean
3125 gprel16_reloc_p (bfd_reloc_code_real_type reloc
)
3127 return (reloc
== BFD_RELOC_GPREL16
|| reloc
== BFD_RELOC_MIPS16_GPREL
3128 || reloc
== BFD_RELOC_MICROMIPS_GPREL16
);
3131 /* Return true if RELOC is a PC-relative relocation that does not have
3132 full address range. */
3134 static inline bfd_boolean
3135 limited_pcrel_reloc_p (bfd_reloc_code_real_type reloc
)
3139 case BFD_RELOC_16_PCREL_S2
:
3140 case BFD_RELOC_MICROMIPS_7_PCREL_S1
:
3141 case BFD_RELOC_MICROMIPS_10_PCREL_S1
:
3142 case BFD_RELOC_MICROMIPS_16_PCREL_S1
:
3145 case BFD_RELOC_32_PCREL
:
3146 return HAVE_64BIT_ADDRESSES
;
3153 /* Return true if the given relocation might need a matching %lo().
3154 This is only "might" because SVR4 R_MIPS_GOT16 relocations only
3155 need a matching %lo() when applied to local symbols. */
3157 static inline bfd_boolean
3158 reloc_needs_lo_p (bfd_reloc_code_real_type reloc
)
3160 return (HAVE_IN_PLACE_ADDENDS
3161 && (hi16_reloc_p (reloc
)
3162 /* VxWorks R_MIPS_GOT16 relocs never need a matching %lo();
3163 all GOT16 relocations evaluate to "G". */
3164 || (got16_reloc_p (reloc
) && mips_pic
!= VXWORKS_PIC
)));
3167 /* Return the type of %lo() reloc needed by RELOC, given that
3168 reloc_needs_lo_p. */
3170 static inline bfd_reloc_code_real_type
3171 matching_lo_reloc (bfd_reloc_code_real_type reloc
)
3173 return (mips16_reloc_p (reloc
) ? BFD_RELOC_MIPS16_LO16
3174 : (micromips_reloc_p (reloc
) ? BFD_RELOC_MICROMIPS_LO16
3178 /* Return true if the given fixup is followed by a matching R_MIPS_LO16
3181 static inline bfd_boolean
3182 fixup_has_matching_lo_p (fixS
*fixp
)
3184 return (fixp
->fx_next
!= NULL
3185 && fixp
->fx_next
->fx_r_type
== matching_lo_reloc (fixp
->fx_r_type
)
3186 && fixp
->fx_addsy
== fixp
->fx_next
->fx_addsy
3187 && fixp
->fx_offset
== fixp
->fx_next
->fx_offset
);
3190 /* This function returns true if modifying a register requires a
3194 reg_needs_delay (unsigned int reg
)
3196 unsigned long prev_pinfo
;
3198 prev_pinfo
= history
[0].insn_mo
->pinfo
;
3199 if (! mips_opts
.noreorder
3200 && (((prev_pinfo
& INSN_LOAD_MEMORY_DELAY
)
3201 && ! gpr_interlocks
)
3202 || ((prev_pinfo
& INSN_LOAD_COPROC_DELAY
)
3203 && ! cop_interlocks
)))
3205 /* A load from a coprocessor or from memory. All load delays
3206 delay the use of general register rt for one instruction. */
3207 /* Itbl support may require additional care here. */
3208 know (prev_pinfo
& INSN_WRITE_GPR_T
);
3209 if (reg
== EXTRACT_OPERAND (mips_opts
.micromips
, RT
, history
[0]))
3216 /* Move all labels in LABELS to the current insertion point. TEXT_P
3217 says whether the labels refer to text or data. */
3220 mips_move_labels (struct insn_label_list
*labels
, bfd_boolean text_p
)
3222 struct insn_label_list
*l
;
3225 for (l
= labels
; l
!= NULL
; l
= l
->next
)
3227 gas_assert (S_GET_SEGMENT (l
->label
) == now_seg
);
3228 symbol_set_frag (l
->label
, frag_now
);
3229 val
= (valueT
) frag_now_fix ();
3230 /* MIPS16/microMIPS text labels are stored as odd. */
3231 if (text_p
&& HAVE_CODE_COMPRESSION
)
3233 S_SET_VALUE (l
->label
, val
);
3237 /* Move all labels in insn_labels to the current insertion point
3238 and treat them as text labels. */
3241 mips_move_text_labels (void)
3243 mips_move_labels (seg_info (now_seg
)->label_list
, TRUE
);
3247 s_is_linkonce (symbolS
*sym
, segT from_seg
)
3249 bfd_boolean linkonce
= FALSE
;
3250 segT symseg
= S_GET_SEGMENT (sym
);
3252 if (symseg
!= from_seg
&& !S_IS_LOCAL (sym
))
3254 if ((bfd_get_section_flags (stdoutput
, symseg
) & SEC_LINK_ONCE
))
3256 /* The GNU toolchain uses an extension for ELF: a section
3257 beginning with the magic string .gnu.linkonce is a
3258 linkonce section. */
3259 if (strncmp (segment_name (symseg
), ".gnu.linkonce",
3260 sizeof ".gnu.linkonce" - 1) == 0)
3266 /* Mark MIPS16 or microMIPS instruction label LABEL. This permits the
3267 linker to handle them specially, such as generating jalx instructions
3268 when needed. We also make them odd for the duration of the assembly,
3269 in order to generate the right sort of code. We will make them even
3270 in the adjust_symtab routine, while leaving them marked. This is
3271 convenient for the debugger and the disassembler. The linker knows
3272 to make them odd again. */
3275 mips_compressed_mark_label (symbolS
*label
)
3277 gas_assert (HAVE_CODE_COMPRESSION
);
3279 if (mips_opts
.mips16
)
3280 S_SET_OTHER (label
, ELF_ST_SET_MIPS16 (S_GET_OTHER (label
)));
3282 S_SET_OTHER (label
, ELF_ST_SET_MICROMIPS (S_GET_OTHER (label
)));
3283 if ((S_GET_VALUE (label
) & 1) == 0
3284 /* Don't adjust the address if the label is global or weak, or
3285 in a link-once section, since we'll be emitting symbol reloc
3286 references to it which will be patched up by the linker, and
3287 the final value of the symbol may or may not be MIPS16/microMIPS. */
3288 && !S_IS_WEAK (label
)
3289 && !S_IS_EXTERNAL (label
)
3290 && !s_is_linkonce (label
, now_seg
))
3291 S_SET_VALUE (label
, S_GET_VALUE (label
) | 1);
3294 /* Mark preceding MIPS16 or microMIPS instruction labels. */
3297 mips_compressed_mark_labels (void)
3299 struct insn_label_list
*l
;
3301 for (l
= seg_info (now_seg
)->label_list
; l
!= NULL
; l
= l
->next
)
3302 mips_compressed_mark_label (l
->label
);
3305 /* End the current frag. Make it a variant frag and record the
3309 relax_close_frag (void)
3311 mips_macro_warning
.first_frag
= frag_now
;
3312 frag_var (rs_machine_dependent
, 0, 0,
3313 RELAX_ENCODE (mips_relax
.sizes
[0], mips_relax
.sizes
[1]),
3314 mips_relax
.symbol
, 0, (char *) mips_relax
.first_fixup
);
3316 memset (&mips_relax
.sizes
, 0, sizeof (mips_relax
.sizes
));
3317 mips_relax
.first_fixup
= 0;
3320 /* Start a new relaxation sequence whose expansion depends on SYMBOL.
3321 See the comment above RELAX_ENCODE for more details. */
3324 relax_start (symbolS
*symbol
)
3326 gas_assert (mips_relax
.sequence
== 0);
3327 mips_relax
.sequence
= 1;
3328 mips_relax
.symbol
= symbol
;
3331 /* Start generating the second version of a relaxable sequence.
3332 See the comment above RELAX_ENCODE for more details. */
3337 gas_assert (mips_relax
.sequence
== 1);
3338 mips_relax
.sequence
= 2;
3341 /* End the current relaxable sequence. */
3346 gas_assert (mips_relax
.sequence
== 2);
3347 relax_close_frag ();
3348 mips_relax
.sequence
= 0;
3351 /* Return true if IP is a delayed branch or jump. */
3353 static inline bfd_boolean
3354 delayed_branch_p (const struct mips_cl_insn
*ip
)
3356 return (ip
->insn_mo
->pinfo
& (INSN_UNCOND_BRANCH_DELAY
3357 | INSN_COND_BRANCH_DELAY
3358 | INSN_COND_BRANCH_LIKELY
)) != 0;
3361 /* Return true if IP is a compact branch or jump. */
3363 static inline bfd_boolean
3364 compact_branch_p (const struct mips_cl_insn
*ip
)
3366 if (mips_opts
.mips16
)
3367 return (ip
->insn_mo
->pinfo
& (MIPS16_INSN_UNCOND_BRANCH
3368 | MIPS16_INSN_COND_BRANCH
)) != 0;
3370 return (ip
->insn_mo
->pinfo2
& (INSN2_UNCOND_BRANCH
3371 | INSN2_COND_BRANCH
)) != 0;
3374 /* Return true if IP is an unconditional branch or jump. */
3376 static inline bfd_boolean
3377 uncond_branch_p (const struct mips_cl_insn
*ip
)
3379 return ((ip
->insn_mo
->pinfo
& INSN_UNCOND_BRANCH_DELAY
) != 0
3380 || (mips_opts
.mips16
3381 ? (ip
->insn_mo
->pinfo
& MIPS16_INSN_UNCOND_BRANCH
) != 0
3382 : (ip
->insn_mo
->pinfo2
& INSN2_UNCOND_BRANCH
) != 0));
3385 /* Return true if IP is a branch-likely instruction. */
3387 static inline bfd_boolean
3388 branch_likely_p (const struct mips_cl_insn
*ip
)
3390 return (ip
->insn_mo
->pinfo
& INSN_COND_BRANCH_LIKELY
) != 0;
3393 /* Return the type of nop that should be used to fill the delay slot
3394 of delayed branch IP. */
3396 static struct mips_cl_insn
*
3397 get_delay_slot_nop (const struct mips_cl_insn
*ip
)
3399 if (mips_opts
.micromips
3400 && (ip
->insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_32BIT
))
3401 return µmips_nop32_insn
;
3405 /* Return the mask of core registers that IP reads or writes. */
3408 gpr_mod_mask (const struct mips_cl_insn
*ip
)
3410 unsigned long pinfo2
;
3414 pinfo2
= ip
->insn_mo
->pinfo2
;
3415 if (mips_opts
.micromips
)
3417 if (pinfo2
& INSN2_MOD_GPR_MD
)
3418 mask
|= 1 << micromips_to_32_reg_d_map
[EXTRACT_OPERAND (1, MD
, *ip
)];
3419 if (pinfo2
& INSN2_MOD_GPR_MF
)
3420 mask
|= 1 << micromips_to_32_reg_f_map
[EXTRACT_OPERAND (1, MF
, *ip
)];
3421 if (pinfo2
& INSN2_MOD_SP
)
3427 /* Return the mask of core registers that IP reads. */
3430 gpr_read_mask (const struct mips_cl_insn
*ip
)
3432 unsigned long pinfo
, pinfo2
;
3435 mask
= gpr_mod_mask (ip
);
3436 pinfo
= ip
->insn_mo
->pinfo
;
3437 pinfo2
= ip
->insn_mo
->pinfo2
;
3438 if (mips_opts
.mips16
)
3440 if (pinfo
& MIPS16_INSN_READ_X
)
3441 mask
|= 1 << mips16_to_32_reg_map
[MIPS16_EXTRACT_OPERAND (RX
, *ip
)];
3442 if (pinfo
& MIPS16_INSN_READ_Y
)
3443 mask
|= 1 << mips16_to_32_reg_map
[MIPS16_EXTRACT_OPERAND (RY
, *ip
)];
3444 if (pinfo
& MIPS16_INSN_READ_T
)
3446 if (pinfo
& MIPS16_INSN_READ_SP
)
3448 if (pinfo
& MIPS16_INSN_READ_31
)
3450 if (pinfo
& MIPS16_INSN_READ_Z
)
3451 mask
|= 1 << (mips16_to_32_reg_map
3452 [MIPS16_EXTRACT_OPERAND (MOVE32Z
, *ip
)]);
3453 if (pinfo
& MIPS16_INSN_READ_GPR_X
)
3454 mask
|= 1 << MIPS16_EXTRACT_OPERAND (REGR32
, *ip
);
3458 if (pinfo2
& INSN2_READ_GPR_D
)
3459 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, RD
, *ip
);
3460 if (pinfo
& INSN_READ_GPR_T
)
3461 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, RT
, *ip
);
3462 if (pinfo
& INSN_READ_GPR_S
)
3463 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, RS
, *ip
);
3464 if (pinfo2
& INSN2_READ_GP
)
3466 if (pinfo2
& INSN2_READ_GPR_31
)
3468 if (pinfo2
& INSN2_READ_GPR_Z
)
3469 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, RZ
, *ip
);
3471 if (mips_opts
.micromips
)
3473 if (pinfo2
& INSN2_READ_GPR_MC
)
3474 mask
|= 1 << micromips_to_32_reg_c_map
[EXTRACT_OPERAND (1, MC
, *ip
)];
3475 if (pinfo2
& INSN2_READ_GPR_ME
)
3476 mask
|= 1 << micromips_to_32_reg_e_map
[EXTRACT_OPERAND (1, ME
, *ip
)];
3477 if (pinfo2
& INSN2_READ_GPR_MG
)
3478 mask
|= 1 << micromips_to_32_reg_g_map
[EXTRACT_OPERAND (1, MG
, *ip
)];
3479 if (pinfo2
& INSN2_READ_GPR_MJ
)
3480 mask
|= 1 << EXTRACT_OPERAND (1, MJ
, *ip
);
3481 if (pinfo2
& INSN2_READ_GPR_MMN
)
3483 mask
|= 1 << micromips_to_32_reg_m_map
[EXTRACT_OPERAND (1, MM
, *ip
)];
3484 mask
|= 1 << micromips_to_32_reg_n_map
[EXTRACT_OPERAND (1, MN
, *ip
)];
3486 if (pinfo2
& INSN2_READ_GPR_MP
)
3487 mask
|= 1 << EXTRACT_OPERAND (1, MP
, *ip
);
3488 if (pinfo2
& INSN2_READ_GPR_MQ
)
3489 mask
|= 1 << micromips_to_32_reg_q_map
[EXTRACT_OPERAND (1, MQ
, *ip
)];
3491 /* Don't include register 0. */
3495 /* Return the mask of core registers that IP writes. */
3498 gpr_write_mask (const struct mips_cl_insn
*ip
)
3500 unsigned long pinfo
, pinfo2
;
3503 mask
= gpr_mod_mask (ip
);
3504 pinfo
= ip
->insn_mo
->pinfo
;
3505 pinfo2
= ip
->insn_mo
->pinfo2
;
3506 if (mips_opts
.mips16
)
3508 if (pinfo
& MIPS16_INSN_WRITE_X
)
3509 mask
|= 1 << mips16_to_32_reg_map
[MIPS16_EXTRACT_OPERAND (RX
, *ip
)];
3510 if (pinfo
& MIPS16_INSN_WRITE_Y
)
3511 mask
|= 1 << mips16_to_32_reg_map
[MIPS16_EXTRACT_OPERAND (RY
, *ip
)];
3512 if (pinfo
& MIPS16_INSN_WRITE_Z
)
3513 mask
|= 1 << mips16_to_32_reg_map
[MIPS16_EXTRACT_OPERAND (RZ
, *ip
)];
3514 if (pinfo
& MIPS16_INSN_WRITE_T
)
3516 if (pinfo
& MIPS16_INSN_WRITE_SP
)
3518 if (pinfo
& MIPS16_INSN_WRITE_31
)
3520 if (pinfo
& MIPS16_INSN_WRITE_GPR_Y
)
3521 mask
|= 1 << MIPS16OP_EXTRACT_REG32R (ip
->insn_opcode
);
3525 if (pinfo
& INSN_WRITE_GPR_D
)
3526 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, RD
, *ip
);
3527 if (pinfo
& INSN_WRITE_GPR_T
)
3528 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, RT
, *ip
);
3529 if (pinfo
& INSN_WRITE_GPR_S
)
3530 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, RS
, *ip
);
3531 if (pinfo
& INSN_WRITE_GPR_31
)
3533 if (pinfo2
& INSN2_WRITE_GPR_Z
)
3534 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, RZ
, *ip
);
3536 if (mips_opts
.micromips
)
3538 if (pinfo2
& INSN2_WRITE_GPR_MB
)
3539 mask
|= 1 << micromips_to_32_reg_b_map
[EXTRACT_OPERAND (1, MB
, *ip
)];
3540 if (pinfo2
& INSN2_WRITE_GPR_MH
)
3542 mask
|= 1 << micromips_to_32_reg_h_map1
[EXTRACT_OPERAND (1, MH
, *ip
)];
3543 mask
|= 1 << micromips_to_32_reg_h_map2
[EXTRACT_OPERAND (1, MH
, *ip
)];
3545 if (pinfo2
& INSN2_WRITE_GPR_MJ
)
3546 mask
|= 1 << EXTRACT_OPERAND (1, MJ
, *ip
);
3547 if (pinfo2
& INSN2_WRITE_GPR_MP
)
3548 mask
|= 1 << EXTRACT_OPERAND (1, MP
, *ip
);
3550 /* Don't include register 0. */
3554 /* Return the mask of floating-point registers that IP reads. */
3557 fpr_read_mask (const struct mips_cl_insn
*ip
)
3559 unsigned long pinfo
, pinfo2
;
3563 pinfo
= ip
->insn_mo
->pinfo
;
3564 pinfo2
= ip
->insn_mo
->pinfo2
;
3565 if (!mips_opts
.mips16
)
3567 if (pinfo2
& INSN2_READ_FPR_D
)
3568 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, FD
, *ip
);
3569 if (pinfo
& INSN_READ_FPR_S
)
3570 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, FS
, *ip
);
3571 if (pinfo
& INSN_READ_FPR_T
)
3572 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, FT
, *ip
);
3573 if (pinfo
& INSN_READ_FPR_R
)
3574 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, FR
, *ip
);
3575 if (pinfo2
& INSN2_READ_FPR_Z
)
3576 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, FZ
, *ip
);
3578 /* Conservatively treat all operands to an FP_D instruction are doubles.
3579 (This is overly pessimistic for things like cvt.d.s.) */
3580 if (HAVE_32BIT_FPRS
&& (pinfo
& FP_D
))
3585 /* Return the mask of floating-point registers that IP writes. */
3588 fpr_write_mask (const struct mips_cl_insn
*ip
)
3590 unsigned long pinfo
, pinfo2
;
3594 pinfo
= ip
->insn_mo
->pinfo
;
3595 pinfo2
= ip
->insn_mo
->pinfo2
;
3596 if (!mips_opts
.mips16
)
3598 if (pinfo
& INSN_WRITE_FPR_D
)
3599 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, FD
, *ip
);
3600 if (pinfo
& INSN_WRITE_FPR_S
)
3601 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, FS
, *ip
);
3602 if (pinfo
& INSN_WRITE_FPR_T
)
3603 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, FT
, *ip
);
3604 if (pinfo2
& INSN2_WRITE_FPR_Z
)
3605 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, FZ
, *ip
);
3607 /* Conservatively treat all operands to an FP_D instruction are doubles.
3608 (This is overly pessimistic for things like cvt.s.d.) */
3609 if (HAVE_32BIT_FPRS
&& (pinfo
& FP_D
))
3614 /* Operand OPNUM of INSN is an odd-numbered floating-point register.
3615 Check whether that is allowed. */
3618 mips_oddfpreg_ok (const struct mips_opcode
*insn
, int opnum
)
3620 const char *s
= insn
->name
;
3622 if (insn
->pinfo
== INSN_MACRO
)
3623 /* Let a macro pass, we'll catch it later when it is expanded. */
3626 if (ISA_HAS_ODD_SINGLE_FPR (mips_opts
.isa
) || mips_opts
.arch
== CPU_R5900
)
3628 /* Allow odd registers for single-precision ops. */
3629 switch (insn
->pinfo
& (FP_S
| FP_D
))
3640 /* Cvt.w.x and cvt.x.w allow an odd register for a 'w' or 's' operand. */
3641 s
= strchr (insn
->name
, '.');
3642 if (s
!= NULL
&& opnum
== 2)
3643 s
= strchr (s
+ 1, '.');
3644 return (s
!= NULL
&& (s
[1] == 'w' || s
[1] == 's'));
3647 /* Single-precision coprocessor loads and moves are OK too. */
3648 if ((insn
->pinfo
& FP_S
)
3649 && (insn
->pinfo
& (INSN_COPROC_MEMORY_DELAY
| INSN_STORE_MEMORY
3650 | INSN_LOAD_COPROC_DELAY
| INSN_COPROC_MOVE_DELAY
)))
3656 /* Report that user-supplied argument ARGNUM for INSN was VAL, but should
3657 have been in the range [MIN_VAL, MAX_VAL]. PRINT_HEX says whether
3658 this operand is normally printed in hex or decimal. */
3661 report_bad_range (struct mips_cl_insn
*insn
, int argnum
,
3662 offsetT val
, int min_val
, int max_val
,
3663 bfd_boolean print_hex
)
3665 if (print_hex
&& val
>= 0)
3666 as_bad (_("Operand %d of `%s' must be in the range [0x%x, 0x%x],"
3668 argnum
, insn
->insn_mo
->name
, min_val
, max_val
, (unsigned long) val
);
3670 as_bad (_("Operand %d of `%s' must be in the range [0x%x, 0x%x],"
3672 argnum
, insn
->insn_mo
->name
, min_val
, max_val
, (unsigned long) val
);
3674 as_bad (_("Operand %d of `%s' must be in the range [%d, %d],"
3676 argnum
, insn
->insn_mo
->name
, min_val
, max_val
, (unsigned long) val
);
3679 /* Report an invalid combination of position and size operands for a bitfield
3680 operation. POS and SIZE are the values that were given. */
3683 report_bad_field (offsetT pos
, offsetT size
)
3685 as_bad (_("Invalid field specification (position %ld, size %ld)"),
3686 (unsigned long) pos
, (unsigned long) size
);
3689 /* Information about an instruction argument that we're trying to match. */
3690 struct mips_arg_info
3692 /* The instruction so far. */
3693 struct mips_cl_insn
*insn
;
3695 /* The 1-based operand number, in terms of insn->insn_mo->args. */
3698 /* The 1-based argument number, for error reporting. This does not
3699 count elided optional registers, etc.. */
3702 /* The last OP_REG operand seen, or ILLEGAL_REG if none. */
3703 unsigned int last_regno
;
3705 /* If the first operand was an OP_REG, this is the register that it
3706 specified, otherwise it is ILLEGAL_REG. */
3707 unsigned int dest_regno
;
3709 /* The value of the last OP_INT operand. Only used for OP_MSB,
3710 where it gives the lsb position. */
3711 unsigned int last_op_int
;
3713 /* If true, match routines should silently reject invalid arguments.
3714 If false, match routines can accept invalid arguments as long as
3715 they report an appropriate error. They still have the option of
3716 silently rejecting arguments, in which case a generic "Invalid operands"
3717 style of error will be used instead. */
3718 bfd_boolean soft_match
;
3720 /* If true, the OP_INT match routine should treat plain symbolic operands
3721 as if a relocation operator like %lo(...) had been used. This is only
3722 ever true if the operand can be relocated. */
3723 bfd_boolean allow_nonconst
;
3725 /* When true, the OP_INT match routine should allow unsigned N-bit
3726 arguments to be used where a signed N-bit operand is expected. */
3727 bfd_boolean lax_max
;
3729 /* When true, the OP_REG match routine should assume that another operand
3730 appears after this one. It should fail the match if the register it
3731 sees is at the end of the argument list. */
3732 bfd_boolean optional_reg
;
3734 /* True if a reference to the current AT register was seen. */
3735 bfd_boolean seen_at
;
3738 /* Match a constant integer at S for ARG. Return null if the match failed.
3739 Otherwise return the end of the matched string and store the constant value
3740 in *VALUE. In the latter case, use FALLBACK as the value if the match
3741 succeeded with an error. */
3744 match_const_int (struct mips_arg_info
*arg
, char *s
, offsetT
*value
,
3748 bfd_reloc_code_real_type r
[3];
3751 num_relocs
= my_getSmallExpression (&ex
, r
, s
);
3752 if (*s
== '(' && ex
.X_op
== O_register
)
3754 /* Assume that the constant has been elided and that S is a base
3755 register. The rest of the match will fail if the assumption
3756 turns out to be wrong. */
3761 if (num_relocs
== 0 && ex
.X_op
== O_constant
)
3762 *value
= ex
.X_add_number
;
3765 /* If we got a register rather than an expression, the default
3766 "Invalid operands" style of error seems more appropriate. */
3767 if (arg
->soft_match
|| ex
.X_op
== O_register
)
3769 as_bad (_("Operand %d of `%s' must be constant"),
3770 arg
->argnum
, arg
->insn
->insn_mo
->name
);
3776 /* Return the RTYPE_* flags for a register operand of type TYPE that
3777 appears in instruction OPCODE. */
3780 convert_reg_type (const struct mips_opcode
*opcode
,
3781 enum mips_reg_operand_type type
)
3786 return RTYPE_NUM
| RTYPE_GP
;
3789 /* Allow vector register names for MDMX if the instruction is a 64-bit
3790 FPR load, store or move (including moves to and from GPRs). */
3791 if ((mips_opts
.ase
& ASE_MDMX
)
3792 && (opcode
->pinfo
& FP_D
)
3793 && (opcode
->pinfo
& (INSN_COPROC_MOVE_DELAY
3794 | INSN_COPROC_MEMORY_DELAY
3795 | INSN_LOAD_COPROC_DELAY
3796 | INSN_LOAD_MEMORY_DELAY
3797 | INSN_STORE_MEMORY
)))
3798 return RTYPE_FPU
| RTYPE_VEC
;
3802 if (opcode
->pinfo
& (FP_D
| FP_S
))
3803 return RTYPE_CCC
| RTYPE_FCC
;
3807 if (opcode
->membership
& INSN_5400
)
3809 return RTYPE_FPU
| RTYPE_VEC
;
3815 if (opcode
->name
[strlen (opcode
->name
) - 1] == '0')
3816 return RTYPE_NUM
| RTYPE_CP0
;
3825 /* ARG is register REGNO, of type TYPE. Warn about any dubious registers. */
3828 check_regno (struct mips_arg_info
*arg
,
3829 enum mips_reg_operand_type type
, unsigned int regno
)
3831 if (AT
&& type
== OP_REG_GP
&& regno
== AT
)
3832 arg
->seen_at
= TRUE
;
3834 if (type
== OP_REG_FP
3837 && !mips_oddfpreg_ok (arg
->insn
->insn_mo
, arg
->opnum
))
3838 as_warn (_("Float register should be even, was %d"), regno
);
3840 if (type
== OP_REG_CCC
)
3845 name
= arg
->insn
->insn_mo
->name
;
3846 length
= strlen (name
);
3847 if ((regno
& 1) != 0
3848 && ((length
>= 3 && strcmp (name
+ length
- 3, ".ps") == 0)
3849 || (length
>= 5 && strncmp (name
+ length
- 5, "any2", 4) == 0)))
3850 as_warn (_("Condition code register should be even for %s, was %d"),
3853 if ((regno
& 3) != 0
3854 && (length
>= 5 && strncmp (name
+ length
- 5, "any4", 4) == 0))
3855 as_warn (_("Condition code register should be 0 or 4 for %s, was %d"),
3860 /* OP_INT matcher. */
3863 match_int_operand (struct mips_arg_info
*arg
,
3864 const struct mips_operand
*operand_base
, char *s
)
3866 const struct mips_int_operand
*operand
;
3867 unsigned int uval
, mask
;
3868 int min_val
, max_val
, factor
;
3870 bfd_boolean print_hex
;
3872 operand
= (const struct mips_int_operand
*) operand_base
;
3873 factor
= 1 << operand
->shift
;
3874 mask
= (1 << operand_base
->size
) - 1;
3875 max_val
= (operand
->max_val
+ operand
->bias
) << operand
->shift
;
3876 min_val
= max_val
- (mask
<< operand
->shift
);
3878 max_val
= mask
<< operand
->shift
;
3880 if (operand_base
->lsb
== 0
3881 && operand_base
->size
== 16
3882 && operand
->shift
== 0
3883 && operand
->bias
== 0
3884 && (operand
->max_val
== 32767 || operand
->max_val
== 65535))
3886 /* The operand can be relocated. */
3887 offset_reloc
[0] = BFD_RELOC_LO16
;
3888 offset_reloc
[1] = BFD_RELOC_UNUSED
;
3889 offset_reloc
[2] = BFD_RELOC_UNUSED
;
3890 if (my_getSmallExpression (&offset_expr
, offset_reloc
, s
) > 0)
3891 /* Relocation operators were used. Accept the arguent and
3892 leave the relocation value in offset_expr and offset_relocs
3893 for the caller to process. */
3895 if (*s
== '(' && offset_expr
.X_op
== O_register
)
3896 /* Assume that the constant has been elided and that S is a base
3897 register. The rest of the match will fail if the assumption
3898 turns out to be wrong. */
3903 if (offset_expr
.X_op
!= O_constant
)
3904 /* If non-constant operands are allowed then leave them for
3905 the caller to process, otherwise fail the match. */
3906 return arg
->allow_nonconst
? s
: 0;
3907 sval
= offset_expr
.X_add_number
;
3909 /* Clear the global state; we're going to install the operand
3911 offset_reloc
[0] = BFD_RELOC_UNUSED
;
3912 offset_expr
.X_op
= O_absent
;
3916 s
= match_const_int (arg
, s
, &sval
, min_val
);
3921 arg
->last_op_int
= sval
;
3923 /* Check the range. If there's a problem, record the lowest acceptable
3924 value in arg->last_op_int in order to prevent an unhelpful error
3927 Bit counts have traditionally been printed in hex by the disassembler
3928 but printed as decimal in error messages. Only resort to hex if
3929 the operand is bigger than 6 bits. */
3930 print_hex
= operand
->print_hex
&& operand_base
->size
> 6;
3931 if (sval
< min_val
|| sval
> max_val
)
3933 if (arg
->soft_match
)
3935 report_bad_range (arg
->insn
, arg
->argnum
, sval
, min_val
, max_val
,
3937 arg
->last_op_int
= min_val
;
3939 else if (sval
% factor
)
3941 if (arg
->soft_match
)
3943 as_bad (print_hex
&& sval
>= 0
3944 ? _("Operand %d of `%s' must be a factor of %d, was 0x%lx.")
3945 : _("Operand %d of `%s' must be a factor of %d, was %ld."),
3946 arg
->argnum
, arg
->insn
->insn_mo
->name
, factor
,
3947 (unsigned long) sval
);
3948 arg
->last_op_int
= min_val
;
3951 uval
= (unsigned int) sval
>> operand
->shift
;
3952 uval
-= operand
->bias
;
3954 /* Handle -mfix-cn63xxp1. */
3956 && mips_fix_cn63xxp1
3957 && !mips_opts
.micromips
3958 && strcmp ("pref", arg
->insn
->insn_mo
->name
) == 0)
3973 /* The rest must be changed to 28. */
3978 insn_insert_operand (arg
->insn
, operand_base
, uval
);
3982 /* OP_MAPPED_INT matcher. */
3985 match_mapped_int_operand (struct mips_arg_info
*arg
,
3986 const struct mips_operand
*operand_base
, char *s
)
3988 const struct mips_mapped_int_operand
*operand
;
3989 unsigned int uval
, num_vals
;
3992 operand
= (const struct mips_mapped_int_operand
*) operand_base
;
3993 s
= match_const_int (arg
, s
, &sval
, operand
->int_map
[0]);
3997 num_vals
= 1 << operand_base
->size
;
3998 for (uval
= 0; uval
< num_vals
; uval
++)
3999 if (operand
->int_map
[uval
] == sval
)
4001 if (uval
== num_vals
)
4004 insn_insert_operand (arg
->insn
, operand_base
, uval
);
4008 /* OP_MSB matcher. */
4011 match_msb_operand (struct mips_arg_info
*arg
,
4012 const struct mips_operand
*operand_base
, char *s
)
4014 const struct mips_msb_operand
*operand
;
4015 int min_val
, max_val
, max_high
;
4016 offsetT size
, sval
, high
;
4018 operand
= (const struct mips_msb_operand
*) operand_base
;
4019 min_val
= operand
->bias
;
4020 max_val
= min_val
+ (1 << operand_base
->size
) - 1;
4021 max_high
= operand
->opsize
;
4023 s
= match_const_int (arg
, s
, &size
, 1);
4027 high
= size
+ arg
->last_op_int
;
4028 sval
= operand
->add_lsb
? high
: size
;
4030 if (size
< 0 || high
> max_high
|| sval
< min_val
|| sval
> max_val
)
4032 if (arg
->soft_match
)
4034 report_bad_field (arg
->last_op_int
, size
);
4037 insn_insert_operand (arg
->insn
, operand_base
, sval
- min_val
);
4041 /* OP_REG matcher. */
4044 match_reg_operand (struct mips_arg_info
*arg
,
4045 const struct mips_operand
*operand_base
, char *s
)
4047 const struct mips_reg_operand
*operand
;
4048 unsigned int regno
, uval
, num_vals
, types
;
4050 operand
= (const struct mips_reg_operand
*) operand_base
;
4051 types
= convert_reg_type (arg
->insn
->insn_mo
, operand
->reg_type
);
4052 if (!reg_lookup (&s
, types
, ®no
))
4055 SKIP_SPACE_TABS (s
);
4056 if (arg
->optional_reg
&& *s
== 0)
4059 if (operand
->reg_map
)
4061 num_vals
= 1 << operand
->root
.size
;
4062 for (uval
= 0; uval
< num_vals
; uval
++)
4063 if (operand
->reg_map
[uval
] == regno
)
4065 if (num_vals
== uval
)
4071 check_regno (arg
, operand
->reg_type
, regno
);
4072 arg
->last_regno
= regno
;
4073 if (arg
->opnum
== 1)
4074 arg
->dest_regno
= regno
;
4075 insn_insert_operand (arg
->insn
, operand_base
, uval
);
4079 /* OP_REG_PAIR matcher. */
4082 match_reg_pair_operand (struct mips_arg_info
*arg
,
4083 const struct mips_operand
*operand_base
, char *s
)
4085 const struct mips_reg_pair_operand
*operand
;
4086 unsigned int regno1
, regno2
, uval
, num_vals
, types
;
4088 operand
= (const struct mips_reg_pair_operand
*) operand_base
;
4089 types
= convert_reg_type (arg
->insn
->insn_mo
, operand
->reg_type
);
4091 if (!reg_lookup (&s
, types
, ®no1
))
4094 SKIP_SPACE_TABS (s
);
4099 if (!reg_lookup (&s
, types
, ®no2
))
4102 num_vals
= 1 << operand_base
->size
;
4103 for (uval
= 0; uval
< num_vals
; uval
++)
4104 if (operand
->reg1_map
[uval
] == regno1
&& operand
->reg2_map
[uval
] == regno2
)
4106 if (uval
== num_vals
)
4109 check_regno (arg
, operand
->reg_type
, regno1
);
4110 check_regno (arg
, operand
->reg_type
, regno2
);
4111 insn_insert_operand (arg
->insn
, operand_base
, uval
);
4115 /* OP_PCREL matcher. The caller chooses the relocation type. */
4118 match_pcrel_operand (char *s
)
4120 my_getExpression (&offset_expr
, s
);
4124 /* OP_PERF_REG matcher. */
4127 match_perf_reg_operand (struct mips_arg_info
*arg
,
4128 const struct mips_operand
*operand
, char *s
)
4132 s
= match_const_int (arg
, s
, &sval
, 0);
4138 || (mips_opts
.arch
== CPU_R5900
4139 && (strcmp (arg
->insn
->insn_mo
->name
, "mfps") == 0
4140 || strcmp (arg
->insn
->insn_mo
->name
, "mtps") == 0))))
4142 if (arg
->soft_match
)
4144 as_bad (_("Invalid performance register (%ld)"), (unsigned long) sval
);
4147 insn_insert_operand (arg
->insn
, operand
, sval
);
4151 /* OP_ADDIUSP matcher. */
4154 match_addiusp_operand (struct mips_arg_info
*arg
,
4155 const struct mips_operand
*operand
, char *s
)
4160 s
= match_const_int (arg
, s
, &sval
, -256);
4168 if (!(sval
>= -258 && sval
<= 257) || (sval
>= -2 && sval
<= 1))
4171 uval
= (unsigned int) sval
;
4172 uval
= ((uval
>> 1) & ~0xff) | (uval
& 0xff);
4173 insn_insert_operand (arg
->insn
, operand
, uval
);
4177 /* OP_CLO_CLZ_DEST matcher. */
4180 match_clo_clz_dest_operand (struct mips_arg_info
*arg
,
4181 const struct mips_operand
*operand
, char *s
)
4185 if (!reg_lookup (&s
, RTYPE_NUM
| RTYPE_GP
, ®no
))
4188 check_regno (arg
, OP_REG_GP
, regno
);
4189 insn_insert_operand (arg
->insn
, operand
, regno
| (regno
<< 5));
4193 /* OP_LWM_SWM_LIST matcher. */
4196 match_lwm_swm_list_operand (struct mips_arg_info
*arg
,
4197 const struct mips_operand
*operand
, char *s
)
4199 unsigned int reglist
, sregs
, ra
;
4201 if (!reglist_lookup (&s
, RTYPE_NUM
| RTYPE_GP
, ®list
))
4204 if (operand
->size
== 2)
4206 /* The list must include both ra and s0-sN, for 0 <= N <= 3. E.g.:
4212 and any permutations of these. */
4213 if ((reglist
& 0xfff1ffff) != 0x80010000)
4216 sregs
= (reglist
>> 17) & 7;
4221 /* The list must include at least one of ra and s0-sN,
4222 for 0 <= N <= 8. (Note that there is a gap between s7 and s8,
4223 which are $23 and $30 respectively.) E.g.:
4231 and any permutations of these. */
4232 if ((reglist
& 0x3f00ffff) != 0)
4235 ra
= (reglist
>> 27) & 0x10;
4236 sregs
= ((reglist
>> 22) & 0x100) | ((reglist
>> 16) & 0xff);
4239 if ((sregs
& -sregs
) != sregs
)
4242 insn_insert_operand (arg
->insn
, operand
, (ffs (sregs
) - 1) | ra
);
4246 /* OP_ENTRY_EXIT_LIST matcher. */
4249 match_entry_exit_operand (struct mips_arg_info
*arg
,
4250 const struct mips_operand
*operand
, char *s
)
4253 bfd_boolean is_exit
;
4255 /* The format is the same for both ENTRY and EXIT, but the constraints
4257 is_exit
= strcmp (arg
->insn
->insn_mo
->name
, "exit") == 0;
4258 mask
= (is_exit
? 7 << 3 : 0);
4261 unsigned int regno1
, regno2
;
4262 bfd_boolean is_freg
;
4264 if (reg_lookup (&s
, RTYPE_GP
| RTYPE_NUM
, ®no1
))
4266 else if (reg_lookup (&s
, RTYPE_FPU
, ®no1
))
4271 SKIP_SPACE_TABS (s
);
4275 SKIP_SPACE_TABS (s
);
4276 if (!reg_lookup (&s
, (is_freg
? RTYPE_FPU
4277 : RTYPE_GP
| RTYPE_NUM
), ®no2
))
4279 SKIP_SPACE_TABS (s
);
4284 if (is_exit
&& is_freg
&& regno1
== 0 && regno2
< 2)
4287 mask
|= (5 + regno2
) << 3;
4289 else if (!is_exit
&& regno1
== 4 && regno2
>= 4 && regno2
<= 7)
4290 mask
|= (regno2
- 3) << 3;
4291 else if (regno1
== 16 && regno2
>= 16 && regno2
<= 17)
4292 mask
|= (regno2
- 15) << 1;
4293 else if (regno1
== RA
&& regno2
== RA
)
4304 SKIP_SPACE_TABS (s
);
4306 insn_insert_operand (arg
->insn
, operand
, mask
);
4310 /* OP_SAVE_RESTORE_LIST matcher. */
4313 match_save_restore_list_operand (struct mips_arg_info
*arg
, char *s
)
4315 unsigned int opcode
, args
, statics
, sregs
;
4316 unsigned int num_frame_sizes
, num_args
, num_statics
, num_sregs
;
4322 opcode
= arg
->insn
->insn_opcode
;
4324 num_frame_sizes
= 0;
4330 unsigned int regno1
, regno2
;
4332 my_getExpression (&value
, s
);
4333 if (value
.X_op
== O_constant
)
4335 /* Handle the frame size. */
4336 num_frame_sizes
+= 1;
4337 frame_size
= value
.X_add_number
;
4339 SKIP_SPACE_TABS (s
);
4343 if (!reg_lookup (&s
, RTYPE_GP
| RTYPE_NUM
, ®no1
))
4346 SKIP_SPACE_TABS (s
);
4350 SKIP_SPACE_TABS (s
);
4351 if (!reg_lookup (&s
, RTYPE_GP
| RTYPE_NUM
, ®no2
)
4354 SKIP_SPACE_TABS (s
);
4359 while (regno1
<= regno2
)
4361 if (regno1
>= 4 && regno1
<= 7)
4363 if (num_frame_sizes
== 0)
4365 args
|= 1 << (regno1
- 4);
4367 /* statics $a0-$a3 */
4368 statics
|= 1 << (regno1
- 4);
4370 else if (regno1
>= 16 && regno1
<= 23)
4372 sregs
|= 1 << (regno1
- 16);
4373 else if (regno1
== 30)
4376 else if (regno1
== 31)
4377 /* Add $ra to insn. */
4392 SKIP_SPACE_TABS (s
);
4395 /* Encode args/statics combination. */
4398 else if (args
== 0xf)
4399 /* All $a0-$a3 are args. */
4400 opcode
|= MIPS16_ALL_ARGS
<< 16;
4401 else if (statics
== 0xf)
4402 /* All $a0-$a3 are statics. */
4403 opcode
|= MIPS16_ALL_STATICS
<< 16;
4406 /* Count arg registers. */
4416 /* Count static registers. */
4418 while (statics
& 0x8)
4420 statics
= (statics
<< 1) & 0xf;
4426 /* Encode args/statics. */
4427 opcode
|= ((num_args
<< 2) | num_statics
) << 16;
4430 /* Encode $s0/$s1. */
4431 if (sregs
& (1 << 0)) /* $s0 */
4433 if (sregs
& (1 << 1)) /* $s1 */
4437 /* Encode $s2-$s8. */
4446 opcode
|= num_sregs
<< 24;
4448 /* Encode frame size. */
4449 if (num_frame_sizes
== 0)
4450 error
= _("Missing frame size");
4451 else if (num_frame_sizes
> 1)
4452 error
= _("Frame size specified twice");
4453 else if ((frame_size
& 7) != 0 || frame_size
< 0 || frame_size
> 0xff * 8)
4454 error
= _("Invalid frame size");
4455 else if (frame_size
!= 128 || (opcode
>> 16) != 0)
4458 opcode
|= (((frame_size
& 0xf0) << 16)
4459 | (frame_size
& 0x0f));
4464 if (arg
->soft_match
)
4469 /* Finally build the instruction. */
4470 if ((opcode
>> 16) != 0 || frame_size
== 0)
4471 opcode
|= MIPS16_EXTEND
;
4472 arg
->insn
->insn_opcode
= opcode
;
4476 /* OP_MDMX_IMM_REG matcher. */
4479 match_mdmx_imm_reg_operand (struct mips_arg_info
*arg
,
4480 const struct mips_operand
*operand
, char *s
)
4482 unsigned int regno
, uval
, types
;
4484 const struct mips_opcode
*opcode
;
4486 /* The mips_opcode records whether this is an octobyte or quadhalf
4487 instruction. Start out with that bit in place. */
4488 opcode
= arg
->insn
->insn_mo
;
4489 uval
= mips_extract_operand (operand
, opcode
->match
);
4490 is_qh
= (uval
!= 0);
4492 types
= convert_reg_type (arg
->insn
->insn_mo
, OP_REG_VEC
);
4493 if (reg_lookup (&s
, types
, ®no
))
4495 if ((opcode
->membership
& INSN_5400
)
4496 && strcmp (opcode
->name
, "rzu.ob") == 0)
4498 if (arg
->soft_match
)
4500 as_bad (_("Operand %d of `%s' must be an immediate"),
4501 arg
->argnum
, opcode
->name
);
4504 /* Check whether this is a vector register or a broadcast of
4505 a single element. */
4506 SKIP_SPACE_TABS (s
);
4509 /* Read the element number. */
4513 SKIP_SPACE_TABS (s
);
4514 my_getExpression (&value
, s
);
4516 if (value
.X_op
!= O_constant
4517 || value
.X_add_number
< 0
4518 || value
.X_add_number
> (is_qh
? 3 : 7))
4520 if (arg
->soft_match
)
4522 as_bad (_("Invalid element selector"));
4523 value
.X_add_number
= 0;
4525 uval
|= (unsigned int) value
.X_add_number
<< (is_qh
? 2 : 1) << 5;
4526 SKIP_SPACE_TABS (s
);
4531 if (arg
->soft_match
)
4533 as_bad (_("Expecting ']' found '%s'"), s
);
4538 /* A full vector. */
4539 if ((opcode
->membership
& INSN_5400
)
4540 && (strcmp (opcode
->name
, "sll.ob") == 0
4541 || strcmp (opcode
->name
, "srl.ob") == 0))
4543 if (arg
->soft_match
)
4545 as_bad (_("Operand %d of `%s' must be scalar"),
4546 arg
->argnum
, opcode
->name
);
4550 uval
|= MDMX_FMTSEL_VEC_QH
<< 5;
4552 uval
|= MDMX_FMTSEL_VEC_OB
<< 5;
4554 check_regno (arg
, OP_REG_FP
, regno
);
4561 s
= match_const_int (arg
, s
, &sval
, 0);
4564 if (sval
< 0 || sval
> 31)
4566 if (arg
->soft_match
)
4568 report_bad_range (arg
->insn
, arg
->argnum
, sval
, 0, 31, FALSE
);
4570 uval
|= (sval
& 31);
4572 uval
|= MDMX_FMTSEL_IMM_QH
<< 5;
4574 uval
|= MDMX_FMTSEL_IMM_OB
<< 5;
4576 insn_insert_operand (arg
->insn
, operand
, uval
);
4580 /* OP_PC matcher. */
4583 match_pc_operand (char *s
)
4585 if (strncmp (s
, "$pc", 3) != 0)
4588 SKIP_SPACE_TABS (s
);
4592 /* OP_REPEAT_DEST_REG and OP_REPEAT_PREV_REG matcher. OTHER_REGNO is the
4593 register that we need to match. */
4596 match_tied_reg_operand (struct mips_arg_info
*arg
, char *s
,
4597 unsigned int other_regno
)
4601 if (!reg_lookup (&s
, RTYPE_NUM
| RTYPE_GP
, ®no
)
4602 || regno
!= other_regno
)
4604 SKIP_SPACE_TABS (s
);
4605 if (arg
->optional_reg
&& *s
== 0)
4610 /* S is the text seen for ARG. Match it against OPERAND. Return the end
4611 of the argument text if the match is successful, otherwise return null. */
4614 match_operand (struct mips_arg_info
*arg
,
4615 const struct mips_operand
*operand
, char *s
)
4617 switch (operand
->type
)
4620 return match_int_operand (arg
, operand
, s
);
4623 return match_mapped_int_operand (arg
, operand
, s
);
4626 return match_msb_operand (arg
, operand
, s
);
4629 return match_reg_operand (arg
, operand
, s
);
4632 return match_reg_pair_operand (arg
, operand
, s
);
4635 return match_pcrel_operand (s
);
4638 return match_perf_reg_operand (arg
, operand
, s
);
4640 case OP_ADDIUSP_INT
:
4641 return match_addiusp_operand (arg
, operand
, s
);
4643 case OP_CLO_CLZ_DEST
:
4644 return match_clo_clz_dest_operand (arg
, operand
, s
);
4646 case OP_LWM_SWM_LIST
:
4647 return match_lwm_swm_list_operand (arg
, operand
, s
);
4649 case OP_ENTRY_EXIT_LIST
:
4650 return match_entry_exit_operand (arg
, operand
, s
);
4652 case OP_SAVE_RESTORE_LIST
:
4653 return match_save_restore_list_operand (arg
, s
);
4655 case OP_MDMX_IMM_REG
:
4656 return match_mdmx_imm_reg_operand (arg
, operand
, s
);
4658 case OP_REPEAT_DEST_REG
:
4659 return match_tied_reg_operand (arg
, s
, arg
->dest_regno
);
4661 case OP_REPEAT_PREV_REG
:
4662 return match_tied_reg_operand (arg
, s
, arg
->last_regno
);
4665 return match_pc_operand (s
);
4670 /* ARG is the state after successfully matching an instruction.
4671 Issue any queued-up warnings. */
4674 check_completed_insn (struct mips_arg_info
*arg
)
4679 as_warn (_("Used $at without \".set noat\""));
4681 as_warn (_("Used $%u with \".set at=$%u\""), AT
, AT
);
4685 /* Classify an instruction according to the FIX_VR4120_* enumeration.
4686 Return NUM_FIX_VR4120_CLASSES if the instruction isn't affected
4687 by VR4120 errata. */
4690 classify_vr4120_insn (const char *name
)
4692 if (strncmp (name
, "macc", 4) == 0)
4693 return FIX_VR4120_MACC
;
4694 if (strncmp (name
, "dmacc", 5) == 0)
4695 return FIX_VR4120_DMACC
;
4696 if (strncmp (name
, "mult", 4) == 0)
4697 return FIX_VR4120_MULT
;
4698 if (strncmp (name
, "dmult", 5) == 0)
4699 return FIX_VR4120_DMULT
;
4700 if (strstr (name
, "div"))
4701 return FIX_VR4120_DIV
;
4702 if (strcmp (name
, "mtlo") == 0 || strcmp (name
, "mthi") == 0)
4703 return FIX_VR4120_MTHILO
;
4704 return NUM_FIX_VR4120_CLASSES
;
4707 #define INSN_ERET 0x42000018
4708 #define INSN_DERET 0x4200001f
4710 /* Return the number of instructions that must separate INSN1 and INSN2,
4711 where INSN1 is the earlier instruction. Return the worst-case value
4712 for any INSN2 if INSN2 is null. */
4715 insns_between (const struct mips_cl_insn
*insn1
,
4716 const struct mips_cl_insn
*insn2
)
4718 unsigned long pinfo1
, pinfo2
;
4721 /* This function needs to know which pinfo flags are set for INSN2
4722 and which registers INSN2 uses. The former is stored in PINFO2 and
4723 the latter is tested via INSN2_USES_GPR. If INSN2 is null, PINFO2
4724 will have every flag set and INSN2_USES_GPR will always return true. */
4725 pinfo1
= insn1
->insn_mo
->pinfo
;
4726 pinfo2
= insn2
? insn2
->insn_mo
->pinfo
: ~0U;
4728 #define INSN2_USES_GPR(REG) \
4729 (insn2 == NULL || (gpr_read_mask (insn2) & (1U << (REG))) != 0)
4731 /* For most targets, write-after-read dependencies on the HI and LO
4732 registers must be separated by at least two instructions. */
4733 if (!hilo_interlocks
)
4735 if ((pinfo1
& INSN_READ_LO
) && (pinfo2
& INSN_WRITE_LO
))
4737 if ((pinfo1
& INSN_READ_HI
) && (pinfo2
& INSN_WRITE_HI
))
4741 /* If we're working around r7000 errata, there must be two instructions
4742 between an mfhi or mflo and any instruction that uses the result. */
4743 if (mips_7000_hilo_fix
4744 && !mips_opts
.micromips
4745 && MF_HILO_INSN (pinfo1
)
4746 && INSN2_USES_GPR (EXTRACT_OPERAND (0, RD
, *insn1
)))
4749 /* If we're working around 24K errata, one instruction is required
4750 if an ERET or DERET is followed by a branch instruction. */
4751 if (mips_fix_24k
&& !mips_opts
.micromips
)
4753 if (insn1
->insn_opcode
== INSN_ERET
4754 || insn1
->insn_opcode
== INSN_DERET
)
4757 || insn2
->insn_opcode
== INSN_ERET
4758 || insn2
->insn_opcode
== INSN_DERET
4759 || delayed_branch_p (insn2
))
4764 /* If working around VR4120 errata, check for combinations that need
4765 a single intervening instruction. */
4766 if (mips_fix_vr4120
&& !mips_opts
.micromips
)
4768 unsigned int class1
, class2
;
4770 class1
= classify_vr4120_insn (insn1
->insn_mo
->name
);
4771 if (class1
!= NUM_FIX_VR4120_CLASSES
&& vr4120_conflicts
[class1
] != 0)
4775 class2
= classify_vr4120_insn (insn2
->insn_mo
->name
);
4776 if (vr4120_conflicts
[class1
] & (1 << class2
))
4781 if (!HAVE_CODE_COMPRESSION
)
4783 /* Check for GPR or coprocessor load delays. All such delays
4784 are on the RT register. */
4785 /* Itbl support may require additional care here. */
4786 if ((!gpr_interlocks
&& (pinfo1
& INSN_LOAD_MEMORY_DELAY
))
4787 || (!cop_interlocks
&& (pinfo1
& INSN_LOAD_COPROC_DELAY
)))
4789 know (pinfo1
& INSN_WRITE_GPR_T
);
4790 if (INSN2_USES_GPR (EXTRACT_OPERAND (0, RT
, *insn1
)))
4794 /* Check for generic coprocessor hazards.
4796 This case is not handled very well. There is no special
4797 knowledge of CP0 handling, and the coprocessors other than
4798 the floating point unit are not distinguished at all. */
4799 /* Itbl support may require additional care here. FIXME!
4800 Need to modify this to include knowledge about
4801 user specified delays! */
4802 else if ((!cop_interlocks
&& (pinfo1
& INSN_COPROC_MOVE_DELAY
))
4803 || (!cop_mem_interlocks
&& (pinfo1
& INSN_COPROC_MEMORY_DELAY
)))
4805 /* Handle cases where INSN1 writes to a known general coprocessor
4806 register. There must be a one instruction delay before INSN2
4807 if INSN2 reads that register, otherwise no delay is needed. */
4808 mask
= fpr_write_mask (insn1
);
4811 if (!insn2
|| (mask
& fpr_read_mask (insn2
)) != 0)
4816 /* Read-after-write dependencies on the control registers
4817 require a two-instruction gap. */
4818 if ((pinfo1
& INSN_WRITE_COND_CODE
)
4819 && (pinfo2
& INSN_READ_COND_CODE
))
4822 /* We don't know exactly what INSN1 does. If INSN2 is
4823 also a coprocessor instruction, assume there must be
4824 a one instruction gap. */
4825 if (pinfo2
& INSN_COP
)
4830 /* Check for read-after-write dependencies on the coprocessor
4831 control registers in cases where INSN1 does not need a general
4832 coprocessor delay. This means that INSN1 is a floating point
4833 comparison instruction. */
4834 /* Itbl support may require additional care here. */
4835 else if (!cop_interlocks
4836 && (pinfo1
& INSN_WRITE_COND_CODE
)
4837 && (pinfo2
& INSN_READ_COND_CODE
))
4841 #undef INSN2_USES_GPR
4846 /* Return the number of nops that would be needed to work around the
4847 VR4130 mflo/mfhi errata if instruction INSN immediately followed
4848 the MAX_VR4130_NOPS instructions described by HIST. Ignore hazards
4849 that are contained within the first IGNORE instructions of HIST. */
4852 nops_for_vr4130 (int ignore
, const struct mips_cl_insn
*hist
,
4853 const struct mips_cl_insn
*insn
)
4858 /* Check if the instruction writes to HI or LO. MTHI and MTLO
4859 are not affected by the errata. */
4861 && ((insn
->insn_mo
->pinfo
& (INSN_WRITE_HI
| INSN_WRITE_LO
)) == 0
4862 || strcmp (insn
->insn_mo
->name
, "mtlo") == 0
4863 || strcmp (insn
->insn_mo
->name
, "mthi") == 0))
4866 /* Search for the first MFLO or MFHI. */
4867 for (i
= 0; i
< MAX_VR4130_NOPS
; i
++)
4868 if (MF_HILO_INSN (hist
[i
].insn_mo
->pinfo
))
4870 /* Extract the destination register. */
4871 mask
= gpr_write_mask (&hist
[i
]);
4873 /* No nops are needed if INSN reads that register. */
4874 if (insn
!= NULL
&& (gpr_read_mask (insn
) & mask
) != 0)
4877 /* ...or if any of the intervening instructions do. */
4878 for (j
= 0; j
< i
; j
++)
4879 if (gpr_read_mask (&hist
[j
]) & mask
)
4883 return MAX_VR4130_NOPS
- i
;
4888 #define BASE_REG_EQ(INSN1, INSN2) \
4889 ((((INSN1) >> OP_SH_RS) & OP_MASK_RS) \
4890 == (((INSN2) >> OP_SH_RS) & OP_MASK_RS))
4892 /* Return the minimum alignment for this store instruction. */
4895 fix_24k_align_to (const struct mips_opcode
*mo
)
4897 if (strcmp (mo
->name
, "sh") == 0)
4900 if (strcmp (mo
->name
, "swc1") == 0
4901 || strcmp (mo
->name
, "swc2") == 0
4902 || strcmp (mo
->name
, "sw") == 0
4903 || strcmp (mo
->name
, "sc") == 0
4904 || strcmp (mo
->name
, "s.s") == 0)
4907 if (strcmp (mo
->name
, "sdc1") == 0
4908 || strcmp (mo
->name
, "sdc2") == 0
4909 || strcmp (mo
->name
, "s.d") == 0)
4916 struct fix_24k_store_info
4918 /* Immediate offset, if any, for this store instruction. */
4920 /* Alignment required by this store instruction. */
4922 /* True for register offsets. */
4923 int register_offset
;
4926 /* Comparison function used by qsort. */
4929 fix_24k_sort (const void *a
, const void *b
)
4931 const struct fix_24k_store_info
*pos1
= a
;
4932 const struct fix_24k_store_info
*pos2
= b
;
4934 return (pos1
->off
- pos2
->off
);
4937 /* INSN is a store instruction. Try to record the store information
4938 in STINFO. Return false if the information isn't known. */
4941 fix_24k_record_store_info (struct fix_24k_store_info
*stinfo
,
4942 const struct mips_cl_insn
*insn
)
4944 /* The instruction must have a known offset. */
4945 if (!insn
->complete_p
|| !strstr (insn
->insn_mo
->args
, "o("))
4948 stinfo
->off
= (insn
->insn_opcode
>> OP_SH_IMMEDIATE
) & OP_MASK_IMMEDIATE
;
4949 stinfo
->align_to
= fix_24k_align_to (insn
->insn_mo
);
4953 /* Return the number of nops that would be needed to work around the 24k
4954 "lost data on stores during refill" errata if instruction INSN
4955 immediately followed the 2 instructions described by HIST.
4956 Ignore hazards that are contained within the first IGNORE
4957 instructions of HIST.
4959 Problem: The FSB (fetch store buffer) acts as an intermediate buffer
4960 for the data cache refills and store data. The following describes
4961 the scenario where the store data could be lost.
4963 * A data cache miss, due to either a load or a store, causing fill
4964 data to be supplied by the memory subsystem
4965 * The first three doublewords of fill data are returned and written
4967 * A sequence of four stores occurs in consecutive cycles around the
4968 final doubleword of the fill:
4972 * Zero, One or more instructions
4975 The four stores A-D must be to different doublewords of the line that
4976 is being filled. The fourth instruction in the sequence above permits
4977 the fill of the final doubleword to be transferred from the FSB into
4978 the cache. In the sequence above, the stores may be either integer
4979 (sb, sh, sw, swr, swl, sc) or coprocessor (swc1/swc2, sdc1/sdc2,
4980 swxc1, sdxc1, suxc1) stores, as long as the four stores are to
4981 different doublewords on the line. If the floating point unit is
4982 running in 1:2 mode, it is not possible to create the sequence above
4983 using only floating point store instructions.
4985 In this case, the cache line being filled is incorrectly marked
4986 invalid, thereby losing the data from any store to the line that
4987 occurs between the original miss and the completion of the five
4988 cycle sequence shown above.
4990 The workarounds are:
4992 * Run the data cache in write-through mode.
4993 * Insert a non-store instruction between
4994 Store A and Store B or Store B and Store C. */
4997 nops_for_24k (int ignore
, const struct mips_cl_insn
*hist
,
4998 const struct mips_cl_insn
*insn
)
5000 struct fix_24k_store_info pos
[3];
5001 int align
, i
, base_offset
;
5006 /* If the previous instruction wasn't a store, there's nothing to
5008 if ((hist
[0].insn_mo
->pinfo
& INSN_STORE_MEMORY
) == 0)
5011 /* If the instructions after the previous one are unknown, we have
5012 to assume the worst. */
5016 /* Check whether we are dealing with three consecutive stores. */
5017 if ((insn
->insn_mo
->pinfo
& INSN_STORE_MEMORY
) == 0
5018 || (hist
[1].insn_mo
->pinfo
& INSN_STORE_MEMORY
) == 0)
5021 /* If we don't know the relationship between the store addresses,
5022 assume the worst. */
5023 if (!BASE_REG_EQ (insn
->insn_opcode
, hist
[0].insn_opcode
)
5024 || !BASE_REG_EQ (insn
->insn_opcode
, hist
[1].insn_opcode
))
5027 if (!fix_24k_record_store_info (&pos
[0], insn
)
5028 || !fix_24k_record_store_info (&pos
[1], &hist
[0])
5029 || !fix_24k_record_store_info (&pos
[2], &hist
[1]))
5032 qsort (&pos
, 3, sizeof (struct fix_24k_store_info
), fix_24k_sort
);
5034 /* Pick a value of ALIGN and X such that all offsets are adjusted by
5035 X bytes and such that the base register + X is known to be aligned
5038 if (((insn
->insn_opcode
>> OP_SH_RS
) & OP_MASK_RS
) == SP
)
5042 align
= pos
[0].align_to
;
5043 base_offset
= pos
[0].off
;
5044 for (i
= 1; i
< 3; i
++)
5045 if (align
< pos
[i
].align_to
)
5047 align
= pos
[i
].align_to
;
5048 base_offset
= pos
[i
].off
;
5050 for (i
= 0; i
< 3; i
++)
5051 pos
[i
].off
-= base_offset
;
5054 pos
[0].off
&= ~align
+ 1;
5055 pos
[1].off
&= ~align
+ 1;
5056 pos
[2].off
&= ~align
+ 1;
5058 /* If any two stores write to the same chunk, they also write to the
5059 same doubleword. The offsets are still sorted at this point. */
5060 if (pos
[0].off
== pos
[1].off
|| pos
[1].off
== pos
[2].off
)
5063 /* A range of at least 9 bytes is needed for the stores to be in
5064 non-overlapping doublewords. */
5065 if (pos
[2].off
- pos
[0].off
<= 8)
5068 if (pos
[2].off
- pos
[1].off
>= 24
5069 || pos
[1].off
- pos
[0].off
>= 24
5070 || pos
[2].off
- pos
[0].off
>= 32)
5076 /* Return the number of nops that would be needed if instruction INSN
5077 immediately followed the MAX_NOPS instructions given by HIST,
5078 where HIST[0] is the most recent instruction. Ignore hazards
5079 between INSN and the first IGNORE instructions in HIST.
5081 If INSN is null, return the worse-case number of nops for any
5085 nops_for_insn (int ignore
, const struct mips_cl_insn
*hist
,
5086 const struct mips_cl_insn
*insn
)
5088 int i
, nops
, tmp_nops
;
5091 for (i
= ignore
; i
< MAX_DELAY_NOPS
; i
++)
5093 tmp_nops
= insns_between (hist
+ i
, insn
) - i
;
5094 if (tmp_nops
> nops
)
5098 if (mips_fix_vr4130
&& !mips_opts
.micromips
)
5100 tmp_nops
= nops_for_vr4130 (ignore
, hist
, insn
);
5101 if (tmp_nops
> nops
)
5105 if (mips_fix_24k
&& !mips_opts
.micromips
)
5107 tmp_nops
= nops_for_24k (ignore
, hist
, insn
);
5108 if (tmp_nops
> nops
)
5115 /* The variable arguments provide NUM_INSNS extra instructions that
5116 might be added to HIST. Return the largest number of nops that
5117 would be needed after the extended sequence, ignoring hazards
5118 in the first IGNORE instructions. */
5121 nops_for_sequence (int num_insns
, int ignore
,
5122 const struct mips_cl_insn
*hist
, ...)
5125 struct mips_cl_insn buffer
[MAX_NOPS
];
5126 struct mips_cl_insn
*cursor
;
5129 va_start (args
, hist
);
5130 cursor
= buffer
+ num_insns
;
5131 memcpy (cursor
, hist
, (MAX_NOPS
- num_insns
) * sizeof (*cursor
));
5132 while (cursor
> buffer
)
5133 *--cursor
= *va_arg (args
, const struct mips_cl_insn
*);
5135 nops
= nops_for_insn (ignore
, buffer
, NULL
);
5140 /* Like nops_for_insn, but if INSN is a branch, take into account the
5141 worst-case delay for the branch target. */
5144 nops_for_insn_or_target (int ignore
, const struct mips_cl_insn
*hist
,
5145 const struct mips_cl_insn
*insn
)
5149 nops
= nops_for_insn (ignore
, hist
, insn
);
5150 if (delayed_branch_p (insn
))
5152 tmp_nops
= nops_for_sequence (2, ignore
? ignore
+ 2 : 0,
5153 hist
, insn
, get_delay_slot_nop (insn
));
5154 if (tmp_nops
> nops
)
5157 else if (compact_branch_p (insn
))
5159 tmp_nops
= nops_for_sequence (1, ignore
? ignore
+ 1 : 0, hist
, insn
);
5160 if (tmp_nops
> nops
)
5166 /* Fix NOP issue: Replace nops by "or at,at,zero". */
5169 fix_loongson2f_nop (struct mips_cl_insn
* ip
)
5171 gas_assert (!HAVE_CODE_COMPRESSION
);
5172 if (strcmp (ip
->insn_mo
->name
, "nop") == 0)
5173 ip
->insn_opcode
= LOONGSON2F_NOP_INSN
;
5176 /* Fix Jump Issue: Eliminate instruction fetch from outside 256M region
5177 jr target pc &= 'hffff_ffff_cfff_ffff. */
5180 fix_loongson2f_jump (struct mips_cl_insn
* ip
)
5182 gas_assert (!HAVE_CODE_COMPRESSION
);
5183 if (strcmp (ip
->insn_mo
->name
, "j") == 0
5184 || strcmp (ip
->insn_mo
->name
, "jr") == 0
5185 || strcmp (ip
->insn_mo
->name
, "jalr") == 0)
5193 sreg
= EXTRACT_OPERAND (0, RS
, *ip
);
5194 if (sreg
== ZERO
|| sreg
== KT0
|| sreg
== KT1
|| sreg
== ATREG
)
5197 ep
.X_op
= O_constant
;
5198 ep
.X_add_number
= 0xcfff0000;
5199 macro_build (&ep
, "lui", "t,u", ATREG
, BFD_RELOC_HI16
);
5200 ep
.X_add_number
= 0xffff;
5201 macro_build (&ep
, "ori", "t,r,i", ATREG
, ATREG
, BFD_RELOC_LO16
);
5202 macro_build (NULL
, "and", "d,v,t", sreg
, sreg
, ATREG
);
5207 fix_loongson2f (struct mips_cl_insn
* ip
)
5209 if (mips_fix_loongson2f_nop
)
5210 fix_loongson2f_nop (ip
);
5212 if (mips_fix_loongson2f_jump
)
5213 fix_loongson2f_jump (ip
);
5216 /* IP is a branch that has a delay slot, and we need to fill it
5217 automatically. Return true if we can do that by swapping IP
5218 with the previous instruction.
5219 ADDRESS_EXPR is an operand of the instruction to be used with
5223 can_swap_branch_p (struct mips_cl_insn
*ip
, expressionS
*address_expr
,
5224 bfd_reloc_code_real_type
*reloc_type
)
5226 unsigned long pinfo
, pinfo2
, prev_pinfo
, prev_pinfo2
;
5227 unsigned int gpr_read
, gpr_write
, prev_gpr_read
, prev_gpr_write
;
5229 /* -O2 and above is required for this optimization. */
5230 if (mips_optimize
< 2)
5233 /* If we have seen .set volatile or .set nomove, don't optimize. */
5234 if (mips_opts
.nomove
)
5237 /* We can't swap if the previous instruction's position is fixed. */
5238 if (history
[0].fixed_p
)
5241 /* If the previous previous insn was in a .set noreorder, we can't
5242 swap. Actually, the MIPS assembler will swap in this situation.
5243 However, gcc configured -with-gnu-as will generate code like
5251 in which we can not swap the bne and INSN. If gcc is not configured
5252 -with-gnu-as, it does not output the .set pseudo-ops. */
5253 if (history
[1].noreorder_p
)
5256 /* If the previous instruction had a fixup in mips16 mode, we can not swap.
5257 This means that the previous instruction was a 4-byte one anyhow. */
5258 if (mips_opts
.mips16
&& history
[0].fixp
[0])
5261 /* If the branch is itself the target of a branch, we can not swap.
5262 We cheat on this; all we check for is whether there is a label on
5263 this instruction. If there are any branches to anything other than
5264 a label, users must use .set noreorder. */
5265 if (seg_info (now_seg
)->label_list
)
5268 /* If the previous instruction is in a variant frag other than this
5269 branch's one, we cannot do the swap. This does not apply to
5270 MIPS16 code, which uses variant frags for different purposes. */
5271 if (!mips_opts
.mips16
5273 && history
[0].frag
->fr_type
== rs_machine_dependent
)
5276 /* We do not swap with instructions that cannot architecturally
5277 be placed in a branch delay slot, such as SYNC or ERET. We
5278 also refrain from swapping with a trap instruction, since it
5279 complicates trap handlers to have the trap instruction be in
5281 prev_pinfo
= history
[0].insn_mo
->pinfo
;
5282 if (prev_pinfo
& INSN_NO_DELAY_SLOT
)
5285 /* Check for conflicts between the branch and the instructions
5286 before the candidate delay slot. */
5287 if (nops_for_insn (0, history
+ 1, ip
) > 0)
5290 /* Check for conflicts between the swapped sequence and the
5291 target of the branch. */
5292 if (nops_for_sequence (2, 0, history
+ 1, ip
, history
) > 0)
5295 /* If the branch reads a register that the previous
5296 instruction sets, we can not swap. */
5297 gpr_read
= gpr_read_mask (ip
);
5298 prev_gpr_write
= gpr_write_mask (&history
[0]);
5299 if (gpr_read
& prev_gpr_write
)
5302 /* If the branch writes a register that the previous
5303 instruction sets, we can not swap. */
5304 gpr_write
= gpr_write_mask (ip
);
5305 if (gpr_write
& prev_gpr_write
)
5308 /* If the branch writes a register that the previous
5309 instruction reads, we can not swap. */
5310 prev_gpr_read
= gpr_read_mask (&history
[0]);
5311 if (gpr_write
& prev_gpr_read
)
5314 /* If one instruction sets a condition code and the
5315 other one uses a condition code, we can not swap. */
5316 pinfo
= ip
->insn_mo
->pinfo
;
5317 if ((pinfo
& INSN_READ_COND_CODE
)
5318 && (prev_pinfo
& INSN_WRITE_COND_CODE
))
5320 if ((pinfo
& INSN_WRITE_COND_CODE
)
5321 && (prev_pinfo
& INSN_READ_COND_CODE
))
5324 /* If the previous instruction uses the PC, we can not swap. */
5325 prev_pinfo2
= history
[0].insn_mo
->pinfo2
;
5326 if (mips_opts
.mips16
&& (prev_pinfo
& MIPS16_INSN_READ_PC
))
5328 if (mips_opts
.micromips
&& (prev_pinfo2
& INSN2_READ_PC
))
5331 /* If the previous instruction has an incorrect size for a fixed
5332 branch delay slot in microMIPS mode, we cannot swap. */
5333 pinfo2
= ip
->insn_mo
->pinfo2
;
5334 if (mips_opts
.micromips
5335 && (pinfo2
& INSN2_BRANCH_DELAY_16BIT
)
5336 && insn_length (history
) != 2)
5338 if (mips_opts
.micromips
5339 && (pinfo2
& INSN2_BRANCH_DELAY_32BIT
)
5340 && insn_length (history
) != 4)
5343 /* On R5900 short loops need to be fixed by inserting a nop in
5344 the branch delay slots.
5345 A short loop can be terminated too early. */
5346 if (mips_opts
.arch
== CPU_R5900
5347 /* Check if instruction has a parameter, ignore "j $31". */
5348 && (address_expr
!= NULL
)
5349 /* Parameter must be 16 bit. */
5350 && (*reloc_type
== BFD_RELOC_16_PCREL_S2
)
5351 /* Branch to same segment. */
5352 && (S_GET_SEGMENT(address_expr
->X_add_symbol
) == now_seg
)
5353 /* Branch to same code fragment. */
5354 && (symbol_get_frag(address_expr
->X_add_symbol
) == frag_now
)
5355 /* Can only calculate branch offset if value is known. */
5356 && symbol_constant_p(address_expr
->X_add_symbol
)
5357 /* Check if branch is really conditional. */
5358 && !((ip
->insn_opcode
& 0xffff0000) == 0x10000000 /* beq $0,$0 */
5359 || (ip
->insn_opcode
& 0xffff0000) == 0x04010000 /* bgez $0 */
5360 || (ip
->insn_opcode
& 0xffff0000) == 0x04110000)) /* bgezal $0 */
5363 /* Check if loop is shorter than 6 instructions including
5364 branch and delay slot. */
5365 distance
= frag_now_fix() - S_GET_VALUE(address_expr
->X_add_symbol
);
5372 /* When the loop includes branches or jumps,
5373 it is not a short loop. */
5374 for (i
= 0; i
< (distance
/ 4); i
++)
5376 if ((history
[i
].cleared_p
)
5377 || delayed_branch_p(&history
[i
]))
5385 /* Insert nop after branch to fix short loop. */
5394 /* Decide how we should add IP to the instruction stream.
5395 ADDRESS_EXPR is an operand of the instruction to be used with
5398 static enum append_method
5399 get_append_method (struct mips_cl_insn
*ip
, expressionS
*address_expr
,
5400 bfd_reloc_code_real_type
*reloc_type
)
5402 unsigned long pinfo
;
5404 /* The relaxed version of a macro sequence must be inherently
5406 if (mips_relax
.sequence
== 2)
5409 /* We must not dabble with instructions in a ".set norerorder" block. */
5410 if (mips_opts
.noreorder
)
5413 /* Otherwise, it's our responsibility to fill branch delay slots. */
5414 if (delayed_branch_p (ip
))
5416 if (!branch_likely_p (ip
)
5417 && can_swap_branch_p (ip
, address_expr
, reloc_type
))
5420 pinfo
= ip
->insn_mo
->pinfo
;
5421 if (mips_opts
.mips16
5422 && ISA_SUPPORTS_MIPS16E
5423 && (pinfo
& (MIPS16_INSN_READ_X
| MIPS16_INSN_READ_31
)))
5424 return APPEND_ADD_COMPACT
;
5426 return APPEND_ADD_WITH_NOP
;
5432 /* IP is a MIPS16 instruction whose opcode we have just changed.
5433 Point IP->insn_mo to the new opcode's definition. */
5436 find_altered_mips16_opcode (struct mips_cl_insn
*ip
)
5438 const struct mips_opcode
*mo
, *end
;
5440 end
= &mips16_opcodes
[bfd_mips16_num_opcodes
];
5441 for (mo
= ip
->insn_mo
; mo
< end
; mo
++)
5442 if ((ip
->insn_opcode
& mo
->mask
) == mo
->match
)
5450 /* For microMIPS macros, we need to generate a local number label
5451 as the target of branches. */
5452 #define MICROMIPS_LABEL_CHAR '\037'
5453 static unsigned long micromips_target_label
;
5454 static char micromips_target_name
[32];
5457 micromips_label_name (void)
5459 char *p
= micromips_target_name
;
5460 char symbol_name_temporary
[24];
5468 l
= micromips_target_label
;
5469 #ifdef LOCAL_LABEL_PREFIX
5470 *p
++ = LOCAL_LABEL_PREFIX
;
5473 *p
++ = MICROMIPS_LABEL_CHAR
;
5476 symbol_name_temporary
[i
++] = l
% 10 + '0';
5481 *p
++ = symbol_name_temporary
[--i
];
5484 return micromips_target_name
;
5488 micromips_label_expr (expressionS
*label_expr
)
5490 label_expr
->X_op
= O_symbol
;
5491 label_expr
->X_add_symbol
= symbol_find_or_make (micromips_label_name ());
5492 label_expr
->X_add_number
= 0;
5496 micromips_label_inc (void)
5498 micromips_target_label
++;
5499 *micromips_target_name
= '\0';
5503 micromips_add_label (void)
5507 s
= colon (micromips_label_name ());
5508 micromips_label_inc ();
5509 S_SET_OTHER (s
, ELF_ST_SET_MICROMIPS (S_GET_OTHER (s
)));
5512 /* If assembling microMIPS code, then return the microMIPS reloc
5513 corresponding to the requested one if any. Otherwise return
5514 the reloc unchanged. */
5516 static bfd_reloc_code_real_type
5517 micromips_map_reloc (bfd_reloc_code_real_type reloc
)
5519 static const bfd_reloc_code_real_type relocs
[][2] =
5521 /* Keep sorted incrementally by the left-hand key. */
5522 { BFD_RELOC_16_PCREL_S2
, BFD_RELOC_MICROMIPS_16_PCREL_S1
},
5523 { BFD_RELOC_GPREL16
, BFD_RELOC_MICROMIPS_GPREL16
},
5524 { BFD_RELOC_MIPS_JMP
, BFD_RELOC_MICROMIPS_JMP
},
5525 { BFD_RELOC_HI16
, BFD_RELOC_MICROMIPS_HI16
},
5526 { BFD_RELOC_HI16_S
, BFD_RELOC_MICROMIPS_HI16_S
},
5527 { BFD_RELOC_LO16
, BFD_RELOC_MICROMIPS_LO16
},
5528 { BFD_RELOC_MIPS_LITERAL
, BFD_RELOC_MICROMIPS_LITERAL
},
5529 { BFD_RELOC_MIPS_GOT16
, BFD_RELOC_MICROMIPS_GOT16
},
5530 { BFD_RELOC_MIPS_CALL16
, BFD_RELOC_MICROMIPS_CALL16
},
5531 { BFD_RELOC_MIPS_GOT_HI16
, BFD_RELOC_MICROMIPS_GOT_HI16
},
5532 { BFD_RELOC_MIPS_GOT_LO16
, BFD_RELOC_MICROMIPS_GOT_LO16
},
5533 { BFD_RELOC_MIPS_CALL_HI16
, BFD_RELOC_MICROMIPS_CALL_HI16
},
5534 { BFD_RELOC_MIPS_CALL_LO16
, BFD_RELOC_MICROMIPS_CALL_LO16
},
5535 { BFD_RELOC_MIPS_SUB
, BFD_RELOC_MICROMIPS_SUB
},
5536 { BFD_RELOC_MIPS_GOT_PAGE
, BFD_RELOC_MICROMIPS_GOT_PAGE
},
5537 { BFD_RELOC_MIPS_GOT_OFST
, BFD_RELOC_MICROMIPS_GOT_OFST
},
5538 { BFD_RELOC_MIPS_GOT_DISP
, BFD_RELOC_MICROMIPS_GOT_DISP
},
5539 { BFD_RELOC_MIPS_HIGHEST
, BFD_RELOC_MICROMIPS_HIGHEST
},
5540 { BFD_RELOC_MIPS_HIGHER
, BFD_RELOC_MICROMIPS_HIGHER
},
5541 { BFD_RELOC_MIPS_SCN_DISP
, BFD_RELOC_MICROMIPS_SCN_DISP
},
5542 { BFD_RELOC_MIPS_TLS_GD
, BFD_RELOC_MICROMIPS_TLS_GD
},
5543 { BFD_RELOC_MIPS_TLS_LDM
, BFD_RELOC_MICROMIPS_TLS_LDM
},
5544 { BFD_RELOC_MIPS_TLS_DTPREL_HI16
, BFD_RELOC_MICROMIPS_TLS_DTPREL_HI16
},
5545 { BFD_RELOC_MIPS_TLS_DTPREL_LO16
, BFD_RELOC_MICROMIPS_TLS_DTPREL_LO16
},
5546 { BFD_RELOC_MIPS_TLS_GOTTPREL
, BFD_RELOC_MICROMIPS_TLS_GOTTPREL
},
5547 { BFD_RELOC_MIPS_TLS_TPREL_HI16
, BFD_RELOC_MICROMIPS_TLS_TPREL_HI16
},
5548 { BFD_RELOC_MIPS_TLS_TPREL_LO16
, BFD_RELOC_MICROMIPS_TLS_TPREL_LO16
}
5550 bfd_reloc_code_real_type r
;
5553 if (!mips_opts
.micromips
)
5555 for (i
= 0; i
< ARRAY_SIZE (relocs
); i
++)
5561 return relocs
[i
][1];
5566 /* Try to resolve relocation RELOC against constant OPERAND at assembly time.
5567 Return true on success, storing the resolved value in RESULT. */
5570 calculate_reloc (bfd_reloc_code_real_type reloc
, offsetT operand
,
5575 case BFD_RELOC_MIPS_HIGHEST
:
5576 case BFD_RELOC_MICROMIPS_HIGHEST
:
5577 *result
= ((operand
+ 0x800080008000ull
) >> 48) & 0xffff;
5580 case BFD_RELOC_MIPS_HIGHER
:
5581 case BFD_RELOC_MICROMIPS_HIGHER
:
5582 *result
= ((operand
+ 0x80008000ull
) >> 32) & 0xffff;
5585 case BFD_RELOC_HI16_S
:
5586 case BFD_RELOC_MICROMIPS_HI16_S
:
5587 case BFD_RELOC_MIPS16_HI16_S
:
5588 *result
= ((operand
+ 0x8000) >> 16) & 0xffff;
5591 case BFD_RELOC_HI16
:
5592 case BFD_RELOC_MICROMIPS_HI16
:
5593 case BFD_RELOC_MIPS16_HI16
:
5594 *result
= (operand
>> 16) & 0xffff;
5597 case BFD_RELOC_LO16
:
5598 case BFD_RELOC_MICROMIPS_LO16
:
5599 case BFD_RELOC_MIPS16_LO16
:
5600 *result
= operand
& 0xffff;
5603 case BFD_RELOC_UNUSED
:
5612 /* Output an instruction. IP is the instruction information.
5613 ADDRESS_EXPR is an operand of the instruction to be used with
5614 RELOC_TYPE. EXPANSIONP is true if the instruction is part of
5615 a macro expansion. */
5618 append_insn (struct mips_cl_insn
*ip
, expressionS
*address_expr
,
5619 bfd_reloc_code_real_type
*reloc_type
, bfd_boolean expansionp
)
5621 unsigned long prev_pinfo2
, pinfo
;
5622 bfd_boolean relaxed_branch
= FALSE
;
5623 enum append_method method
;
5624 bfd_boolean relax32
;
5627 if (mips_fix_loongson2f
&& !HAVE_CODE_COMPRESSION
)
5628 fix_loongson2f (ip
);
5630 file_ase_mips16
|= mips_opts
.mips16
;
5631 file_ase_micromips
|= mips_opts
.micromips
;
5633 prev_pinfo2
= history
[0].insn_mo
->pinfo2
;
5634 pinfo
= ip
->insn_mo
->pinfo
;
5636 if (mips_opts
.micromips
5638 && (((prev_pinfo2
& INSN2_BRANCH_DELAY_16BIT
) != 0
5639 && micromips_insn_length (ip
->insn_mo
) != 2)
5640 || ((prev_pinfo2
& INSN2_BRANCH_DELAY_32BIT
) != 0
5641 && micromips_insn_length (ip
->insn_mo
) != 4)))
5642 as_warn (_("Wrong size instruction in a %u-bit branch delay slot"),
5643 (prev_pinfo2
& INSN2_BRANCH_DELAY_16BIT
) != 0 ? 16 : 32);
5645 if (address_expr
== NULL
)
5647 else if (reloc_type
[0] <= BFD_RELOC_UNUSED
5648 && reloc_type
[1] == BFD_RELOC_UNUSED
5649 && reloc_type
[2] == BFD_RELOC_UNUSED
5650 && address_expr
->X_op
== O_constant
)
5652 switch (*reloc_type
)
5654 case BFD_RELOC_MIPS_JMP
:
5658 shift
= mips_opts
.micromips
? 1 : 2;
5659 if ((address_expr
->X_add_number
& ((1 << shift
) - 1)) != 0)
5660 as_bad (_("jump to misaligned address (0x%lx)"),
5661 (unsigned long) address_expr
->X_add_number
);
5662 ip
->insn_opcode
|= ((address_expr
->X_add_number
>> shift
)
5668 case BFD_RELOC_MIPS16_JMP
:
5669 if ((address_expr
->X_add_number
& 3) != 0)
5670 as_bad (_("jump to misaligned address (0x%lx)"),
5671 (unsigned long) address_expr
->X_add_number
);
5673 (((address_expr
->X_add_number
& 0x7c0000) << 3)
5674 | ((address_expr
->X_add_number
& 0xf800000) >> 7)
5675 | ((address_expr
->X_add_number
& 0x3fffc) >> 2));
5679 case BFD_RELOC_16_PCREL_S2
:
5683 shift
= mips_opts
.micromips
? 1 : 2;
5684 if ((address_expr
->X_add_number
& ((1 << shift
) - 1)) != 0)
5685 as_bad (_("branch to misaligned address (0x%lx)"),
5686 (unsigned long) address_expr
->X_add_number
);
5687 if (!mips_relax_branch
)
5689 if ((address_expr
->X_add_number
+ (1 << (shift
+ 15)))
5690 & ~((1 << (shift
+ 16)) - 1))
5691 as_bad (_("branch address range overflow (0x%lx)"),
5692 (unsigned long) address_expr
->X_add_number
);
5693 ip
->insn_opcode
|= ((address_expr
->X_add_number
>> shift
)
5703 if (calculate_reloc (*reloc_type
, address_expr
->X_add_number
,
5706 ip
->insn_opcode
|= value
& 0xffff;
5714 if (mips_relax
.sequence
!= 2 && !mips_opts
.noreorder
)
5716 /* There are a lot of optimizations we could do that we don't.
5717 In particular, we do not, in general, reorder instructions.
5718 If you use gcc with optimization, it will reorder
5719 instructions and generally do much more optimization then we
5720 do here; repeating all that work in the assembler would only
5721 benefit hand written assembly code, and does not seem worth
5723 int nops
= (mips_optimize
== 0
5724 ? nops_for_insn (0, history
, NULL
)
5725 : nops_for_insn_or_target (0, history
, ip
));
5729 unsigned long old_frag_offset
;
5732 old_frag
= frag_now
;
5733 old_frag_offset
= frag_now_fix ();
5735 for (i
= 0; i
< nops
; i
++)
5736 add_fixed_insn (NOP_INSN
);
5737 insert_into_history (0, nops
, NOP_INSN
);
5741 listing_prev_line ();
5742 /* We may be at the start of a variant frag. In case we
5743 are, make sure there is enough space for the frag
5744 after the frags created by listing_prev_line. The
5745 argument to frag_grow here must be at least as large
5746 as the argument to all other calls to frag_grow in
5747 this file. We don't have to worry about being in the
5748 middle of a variant frag, because the variants insert
5749 all needed nop instructions themselves. */
5753 mips_move_text_labels ();
5755 #ifndef NO_ECOFF_DEBUGGING
5756 if (ECOFF_DEBUGGING
)
5757 ecoff_fix_loc (old_frag
, old_frag_offset
);
5761 else if (mips_relax
.sequence
!= 2 && prev_nop_frag
!= NULL
)
5765 /* Work out how many nops in prev_nop_frag are needed by IP,
5766 ignoring hazards generated by the first prev_nop_frag_since
5768 nops
= nops_for_insn_or_target (prev_nop_frag_since
, history
, ip
);
5769 gas_assert (nops
<= prev_nop_frag_holds
);
5771 /* Enforce NOPS as a minimum. */
5772 if (nops
> prev_nop_frag_required
)
5773 prev_nop_frag_required
= nops
;
5775 if (prev_nop_frag_holds
== prev_nop_frag_required
)
5777 /* Settle for the current number of nops. Update the history
5778 accordingly (for the benefit of any future .set reorder code). */
5779 prev_nop_frag
= NULL
;
5780 insert_into_history (prev_nop_frag_since
,
5781 prev_nop_frag_holds
, NOP_INSN
);
5785 /* Allow this instruction to replace one of the nops that was
5786 tentatively added to prev_nop_frag. */
5787 prev_nop_frag
->fr_fix
-= NOP_INSN_SIZE
;
5788 prev_nop_frag_holds
--;
5789 prev_nop_frag_since
++;
5793 method
= get_append_method (ip
, address_expr
, reloc_type
);
5794 branch_disp
= method
== APPEND_SWAP
? insn_length (history
) : 0;
5796 dwarf2_emit_insn (0);
5797 /* We want MIPS16 and microMIPS debug info to use ISA-encoded addresses,
5798 so "move" the instruction address accordingly.
5800 Also, it doesn't seem appropriate for the assembler to reorder .loc
5801 entries. If this instruction is a branch that we are going to swap
5802 with the previous instruction, the two instructions should be
5803 treated as a unit, and the debug information for both instructions
5804 should refer to the start of the branch sequence. Using the
5805 current position is certainly wrong when swapping a 32-bit branch
5806 and a 16-bit delay slot, since the current position would then be
5807 in the middle of a branch. */
5808 dwarf2_move_insn ((HAVE_CODE_COMPRESSION
? 1 : 0) - branch_disp
);
5810 relax32
= (mips_relax_branch
5811 /* Don't try branch relaxation within .set nomacro, or within
5812 .set noat if we use $at for PIC computations. If it turns
5813 out that the branch was out-of-range, we'll get an error. */
5814 && !mips_opts
.warn_about_macros
5815 && (mips_opts
.at
|| mips_pic
== NO_PIC
)
5816 /* Don't relax BPOSGE32/64 or BC1ANY2T/F and BC1ANY4T/F
5817 as they have no complementing branches. */
5818 && !(ip
->insn_mo
->ase
& (ASE_MIPS3D
| ASE_DSP64
| ASE_DSP
)));
5820 if (!HAVE_CODE_COMPRESSION
5823 && *reloc_type
== BFD_RELOC_16_PCREL_S2
5824 && delayed_branch_p (ip
))
5826 relaxed_branch
= TRUE
;
5827 add_relaxed_insn (ip
, (relaxed_branch_length
5829 uncond_branch_p (ip
) ? -1
5830 : branch_likely_p (ip
) ? 1
5834 uncond_branch_p (ip
),
5835 branch_likely_p (ip
),
5836 pinfo
& INSN_WRITE_GPR_31
,
5838 address_expr
->X_add_symbol
,
5839 address_expr
->X_add_number
);
5840 *reloc_type
= BFD_RELOC_UNUSED
;
5842 else if (mips_opts
.micromips
5844 && ((relax32
&& *reloc_type
== BFD_RELOC_16_PCREL_S2
)
5845 || *reloc_type
> BFD_RELOC_UNUSED
)
5846 && (delayed_branch_p (ip
) || compact_branch_p (ip
))
5847 /* Don't try branch relaxation when users specify
5848 16-bit/32-bit instructions. */
5849 && !forced_insn_length
)
5851 bfd_boolean relax16
= *reloc_type
> BFD_RELOC_UNUSED
;
5852 int type
= relax16
? *reloc_type
- BFD_RELOC_UNUSED
: 0;
5853 int uncond
= uncond_branch_p (ip
) ? -1 : 0;
5854 int compact
= compact_branch_p (ip
);
5855 int al
= pinfo
& INSN_WRITE_GPR_31
;
5858 gas_assert (address_expr
!= NULL
);
5859 gas_assert (!mips_relax
.sequence
);
5861 relaxed_branch
= TRUE
;
5862 length32
= relaxed_micromips_32bit_branch_length (NULL
, NULL
, uncond
);
5863 add_relaxed_insn (ip
, relax32
? length32
: 4, relax16
? 2 : 4,
5864 RELAX_MICROMIPS_ENCODE (type
, AT
, uncond
, compact
, al
,
5866 address_expr
->X_add_symbol
,
5867 address_expr
->X_add_number
);
5868 *reloc_type
= BFD_RELOC_UNUSED
;
5870 else if (mips_opts
.mips16
&& *reloc_type
> BFD_RELOC_UNUSED
)
5872 /* We need to set up a variant frag. */
5873 gas_assert (address_expr
!= NULL
);
5874 add_relaxed_insn (ip
, 4, 0,
5876 (*reloc_type
- BFD_RELOC_UNUSED
,
5877 forced_insn_length
== 2, forced_insn_length
== 4,
5878 delayed_branch_p (&history
[0]),
5879 history
[0].mips16_absolute_jump_p
),
5880 make_expr_symbol (address_expr
), 0);
5882 else if (mips_opts
.mips16
&& insn_length (ip
) == 2)
5884 if (!delayed_branch_p (ip
))
5885 /* Make sure there is enough room to swap this instruction with
5886 a following jump instruction. */
5888 add_fixed_insn (ip
);
5892 if (mips_opts
.mips16
5893 && mips_opts
.noreorder
5894 && delayed_branch_p (&history
[0]))
5895 as_warn (_("extended instruction in delay slot"));
5897 if (mips_relax
.sequence
)
5899 /* If we've reached the end of this frag, turn it into a variant
5900 frag and record the information for the instructions we've
5902 if (frag_room () < 4)
5903 relax_close_frag ();
5904 mips_relax
.sizes
[mips_relax
.sequence
- 1] += insn_length (ip
);
5907 if (mips_relax
.sequence
!= 2)
5909 if (mips_macro_warning
.first_insn_sizes
[0] == 0)
5910 mips_macro_warning
.first_insn_sizes
[0] = insn_length (ip
);
5911 mips_macro_warning
.sizes
[0] += insn_length (ip
);
5912 mips_macro_warning
.insns
[0]++;
5914 if (mips_relax
.sequence
!= 1)
5916 if (mips_macro_warning
.first_insn_sizes
[1] == 0)
5917 mips_macro_warning
.first_insn_sizes
[1] = insn_length (ip
);
5918 mips_macro_warning
.sizes
[1] += insn_length (ip
);
5919 mips_macro_warning
.insns
[1]++;
5922 if (mips_opts
.mips16
)
5925 ip
->mips16_absolute_jump_p
= (*reloc_type
== BFD_RELOC_MIPS16_JMP
);
5927 add_fixed_insn (ip
);
5930 if (!ip
->complete_p
&& *reloc_type
< BFD_RELOC_UNUSED
)
5932 bfd_reloc_code_real_type final_type
[3];
5933 reloc_howto_type
*howto0
;
5934 reloc_howto_type
*howto
;
5937 /* Perform any necessary conversion to microMIPS relocations
5938 and find out how many relocations there actually are. */
5939 for (i
= 0; i
< 3 && reloc_type
[i
] != BFD_RELOC_UNUSED
; i
++)
5940 final_type
[i
] = micromips_map_reloc (reloc_type
[i
]);
5942 /* In a compound relocation, it is the final (outermost)
5943 operator that determines the relocated field. */
5944 howto
= howto0
= bfd_reloc_type_lookup (stdoutput
, final_type
[i
- 1]);
5949 howto0
= bfd_reloc_type_lookup (stdoutput
, final_type
[0]);
5950 ip
->fixp
[0] = fix_new_exp (ip
->frag
, ip
->where
,
5951 bfd_get_reloc_size (howto
),
5953 howto0
&& howto0
->pc_relative
,
5956 /* Tag symbols that have a R_MIPS16_26 relocation against them. */
5957 if (final_type
[0] == BFD_RELOC_MIPS16_JMP
&& ip
->fixp
[0]->fx_addsy
)
5958 *symbol_get_tc (ip
->fixp
[0]->fx_addsy
) = 1;
5960 /* These relocations can have an addend that won't fit in
5961 4 octets for 64bit assembly. */
5963 && ! howto
->partial_inplace
5964 && (reloc_type
[0] == BFD_RELOC_16
5965 || reloc_type
[0] == BFD_RELOC_32
5966 || reloc_type
[0] == BFD_RELOC_MIPS_JMP
5967 || reloc_type
[0] == BFD_RELOC_GPREL16
5968 || reloc_type
[0] == BFD_RELOC_MIPS_LITERAL
5969 || reloc_type
[0] == BFD_RELOC_GPREL32
5970 || reloc_type
[0] == BFD_RELOC_64
5971 || reloc_type
[0] == BFD_RELOC_CTOR
5972 || reloc_type
[0] == BFD_RELOC_MIPS_SUB
5973 || reloc_type
[0] == BFD_RELOC_MIPS_HIGHEST
5974 || reloc_type
[0] == BFD_RELOC_MIPS_HIGHER
5975 || reloc_type
[0] == BFD_RELOC_MIPS_SCN_DISP
5976 || reloc_type
[0] == BFD_RELOC_MIPS_REL16
5977 || reloc_type
[0] == BFD_RELOC_MIPS_RELGOT
5978 || reloc_type
[0] == BFD_RELOC_MIPS16_GPREL
5979 || hi16_reloc_p (reloc_type
[0])
5980 || lo16_reloc_p (reloc_type
[0])))
5981 ip
->fixp
[0]->fx_no_overflow
= 1;
5983 /* These relocations can have an addend that won't fit in 2 octets. */
5984 if (reloc_type
[0] == BFD_RELOC_MICROMIPS_7_PCREL_S1
5985 || reloc_type
[0] == BFD_RELOC_MICROMIPS_10_PCREL_S1
)
5986 ip
->fixp
[0]->fx_no_overflow
= 1;
5988 if (mips_relax
.sequence
)
5990 if (mips_relax
.first_fixup
== 0)
5991 mips_relax
.first_fixup
= ip
->fixp
[0];
5993 else if (reloc_needs_lo_p (*reloc_type
))
5995 struct mips_hi_fixup
*hi_fixup
;
5997 /* Reuse the last entry if it already has a matching %lo. */
5998 hi_fixup
= mips_hi_fixup_list
;
6000 || !fixup_has_matching_lo_p (hi_fixup
->fixp
))
6002 hi_fixup
= ((struct mips_hi_fixup
*)
6003 xmalloc (sizeof (struct mips_hi_fixup
)));
6004 hi_fixup
->next
= mips_hi_fixup_list
;
6005 mips_hi_fixup_list
= hi_fixup
;
6007 hi_fixup
->fixp
= ip
->fixp
[0];
6008 hi_fixup
->seg
= now_seg
;
6011 /* Add fixups for the second and third relocations, if given.
6012 Note that the ABI allows the second relocation to be
6013 against RSS_UNDEF, RSS_GP, RSS_GP0 or RSS_LOC. At the
6014 moment we only use RSS_UNDEF, but we could add support
6015 for the others if it ever becomes necessary. */
6016 for (i
= 1; i
< 3; i
++)
6017 if (reloc_type
[i
] != BFD_RELOC_UNUSED
)
6019 ip
->fixp
[i
] = fix_new (ip
->frag
, ip
->where
,
6020 ip
->fixp
[0]->fx_size
, NULL
, 0,
6021 FALSE
, final_type
[i
]);
6023 /* Use fx_tcbit to mark compound relocs. */
6024 ip
->fixp
[0]->fx_tcbit
= 1;
6025 ip
->fixp
[i
]->fx_tcbit
= 1;
6030 /* Update the register mask information. */
6031 mips_gprmask
|= gpr_read_mask (ip
) | gpr_write_mask (ip
);
6032 mips_cprmask
[1] |= fpr_read_mask (ip
) | fpr_write_mask (ip
);
6037 insert_into_history (0, 1, ip
);
6040 case APPEND_ADD_WITH_NOP
:
6042 struct mips_cl_insn
*nop
;
6044 insert_into_history (0, 1, ip
);
6045 nop
= get_delay_slot_nop (ip
);
6046 add_fixed_insn (nop
);
6047 insert_into_history (0, 1, nop
);
6048 if (mips_relax
.sequence
)
6049 mips_relax
.sizes
[mips_relax
.sequence
- 1] += insn_length (nop
);
6053 case APPEND_ADD_COMPACT
:
6054 /* Convert MIPS16 jr/jalr into a "compact" jump. */
6055 gas_assert (mips_opts
.mips16
);
6056 ip
->insn_opcode
|= 0x0080;
6057 find_altered_mips16_opcode (ip
);
6059 insert_into_history (0, 1, ip
);
6064 struct mips_cl_insn delay
= history
[0];
6065 if (mips_opts
.mips16
)
6067 know (delay
.frag
== ip
->frag
);
6068 move_insn (ip
, delay
.frag
, delay
.where
);
6069 move_insn (&delay
, ip
->frag
, ip
->where
+ insn_length (ip
));
6071 else if (relaxed_branch
|| delay
.frag
!= ip
->frag
)
6073 /* Add the delay slot instruction to the end of the
6074 current frag and shrink the fixed part of the
6075 original frag. If the branch occupies the tail of
6076 the latter, move it backwards to cover the gap. */
6077 delay
.frag
->fr_fix
-= branch_disp
;
6078 if (delay
.frag
== ip
->frag
)
6079 move_insn (ip
, ip
->frag
, ip
->where
- branch_disp
);
6080 add_fixed_insn (&delay
);
6084 move_insn (&delay
, ip
->frag
,
6085 ip
->where
- branch_disp
+ insn_length (ip
));
6086 move_insn (ip
, history
[0].frag
, history
[0].where
);
6090 insert_into_history (0, 1, &delay
);
6095 /* If we have just completed an unconditional branch, clear the history. */
6096 if ((delayed_branch_p (&history
[1]) && uncond_branch_p (&history
[1]))
6097 || (compact_branch_p (&history
[0]) && uncond_branch_p (&history
[0])))
6101 mips_no_prev_insn ();
6103 for (i
= 0; i
< ARRAY_SIZE (history
); i
++)
6104 history
[i
].cleared_p
= 1;
6107 /* We need to emit a label at the end of branch-likely macros. */
6108 if (emit_branch_likely_macro
)
6110 emit_branch_likely_macro
= FALSE
;
6111 micromips_add_label ();
6114 /* We just output an insn, so the next one doesn't have a label. */
6115 mips_clear_insn_labels ();
6118 /* Forget that there was any previous instruction or label.
6119 When BRANCH is true, the branch history is also flushed. */
6122 mips_no_prev_insn (void)
6124 prev_nop_frag
= NULL
;
6125 insert_into_history (0, ARRAY_SIZE (history
), NOP_INSN
);
6126 mips_clear_insn_labels ();
6129 /* This function must be called before we emit something other than
6130 instructions. It is like mips_no_prev_insn except that it inserts
6131 any NOPS that might be needed by previous instructions. */
6134 mips_emit_delays (void)
6136 if (! mips_opts
.noreorder
)
6138 int nops
= nops_for_insn (0, history
, NULL
);
6142 add_fixed_insn (NOP_INSN
);
6143 mips_move_text_labels ();
6146 mips_no_prev_insn ();
6149 /* Start a (possibly nested) noreorder block. */
6152 start_noreorder (void)
6154 if (mips_opts
.noreorder
== 0)
6159 /* None of the instructions before the .set noreorder can be moved. */
6160 for (i
= 0; i
< ARRAY_SIZE (history
); i
++)
6161 history
[i
].fixed_p
= 1;
6163 /* Insert any nops that might be needed between the .set noreorder
6164 block and the previous instructions. We will later remove any
6165 nops that turn out not to be needed. */
6166 nops
= nops_for_insn (0, history
, NULL
);
6169 if (mips_optimize
!= 0)
6171 /* Record the frag which holds the nop instructions, so
6172 that we can remove them if we don't need them. */
6173 frag_grow (nops
* NOP_INSN_SIZE
);
6174 prev_nop_frag
= frag_now
;
6175 prev_nop_frag_holds
= nops
;
6176 prev_nop_frag_required
= 0;
6177 prev_nop_frag_since
= 0;
6180 for (; nops
> 0; --nops
)
6181 add_fixed_insn (NOP_INSN
);
6183 /* Move on to a new frag, so that it is safe to simply
6184 decrease the size of prev_nop_frag. */
6185 frag_wane (frag_now
);
6187 mips_move_text_labels ();
6189 mips_mark_labels ();
6190 mips_clear_insn_labels ();
6192 mips_opts
.noreorder
++;
6193 mips_any_noreorder
= 1;
6196 /* End a nested noreorder block. */
6199 end_noreorder (void)
6201 mips_opts
.noreorder
--;
6202 if (mips_opts
.noreorder
== 0 && prev_nop_frag
!= NULL
)
6204 /* Commit to inserting prev_nop_frag_required nops and go back to
6205 handling nop insertion the .set reorder way. */
6206 prev_nop_frag
->fr_fix
-= ((prev_nop_frag_holds
- prev_nop_frag_required
)
6208 insert_into_history (prev_nop_frag_since
,
6209 prev_nop_frag_required
, NOP_INSN
);
6210 prev_nop_frag
= NULL
;
6214 /* Set up global variables for the start of a new macro. */
6219 memset (&mips_macro_warning
.sizes
, 0, sizeof (mips_macro_warning
.sizes
));
6220 memset (&mips_macro_warning
.first_insn_sizes
, 0,
6221 sizeof (mips_macro_warning
.first_insn_sizes
));
6222 memset (&mips_macro_warning
.insns
, 0, sizeof (mips_macro_warning
.insns
));
6223 mips_macro_warning
.delay_slot_p
= (mips_opts
.noreorder
6224 && delayed_branch_p (&history
[0]));
6225 switch (history
[0].insn_mo
->pinfo2
6226 & (INSN2_BRANCH_DELAY_32BIT
| INSN2_BRANCH_DELAY_16BIT
))
6228 case INSN2_BRANCH_DELAY_32BIT
:
6229 mips_macro_warning
.delay_slot_length
= 4;
6231 case INSN2_BRANCH_DELAY_16BIT
:
6232 mips_macro_warning
.delay_slot_length
= 2;
6235 mips_macro_warning
.delay_slot_length
= 0;
6238 mips_macro_warning
.first_frag
= NULL
;
6241 /* Given that a macro is longer than one instruction or of the wrong size,
6242 return the appropriate warning for it. Return null if no warning is
6243 needed. SUBTYPE is a bitmask of RELAX_DELAY_SLOT, RELAX_DELAY_SLOT_16BIT,
6244 RELAX_DELAY_SLOT_SIZE_FIRST, RELAX_DELAY_SLOT_SIZE_SECOND,
6245 and RELAX_NOMACRO. */
6248 macro_warning (relax_substateT subtype
)
6250 if (subtype
& RELAX_DELAY_SLOT
)
6251 return _("Macro instruction expanded into multiple instructions"
6252 " in a branch delay slot");
6253 else if (subtype
& RELAX_NOMACRO
)
6254 return _("Macro instruction expanded into multiple instructions");
6255 else if (subtype
& (RELAX_DELAY_SLOT_SIZE_FIRST
6256 | RELAX_DELAY_SLOT_SIZE_SECOND
))
6257 return ((subtype
& RELAX_DELAY_SLOT_16BIT
)
6258 ? _("Macro instruction expanded into a wrong size instruction"
6259 " in a 16-bit branch delay slot")
6260 : _("Macro instruction expanded into a wrong size instruction"
6261 " in a 32-bit branch delay slot"));
6266 /* Finish up a macro. Emit warnings as appropriate. */
6271 /* Relaxation warning flags. */
6272 relax_substateT subtype
= 0;
6274 /* Check delay slot size requirements. */
6275 if (mips_macro_warning
.delay_slot_length
== 2)
6276 subtype
|= RELAX_DELAY_SLOT_16BIT
;
6277 if (mips_macro_warning
.delay_slot_length
!= 0)
6279 if (mips_macro_warning
.delay_slot_length
6280 != mips_macro_warning
.first_insn_sizes
[0])
6281 subtype
|= RELAX_DELAY_SLOT_SIZE_FIRST
;
6282 if (mips_macro_warning
.delay_slot_length
6283 != mips_macro_warning
.first_insn_sizes
[1])
6284 subtype
|= RELAX_DELAY_SLOT_SIZE_SECOND
;
6287 /* Check instruction count requirements. */
6288 if (mips_macro_warning
.insns
[0] > 1 || mips_macro_warning
.insns
[1] > 1)
6290 if (mips_macro_warning
.insns
[1] > mips_macro_warning
.insns
[0])
6291 subtype
|= RELAX_SECOND_LONGER
;
6292 if (mips_opts
.warn_about_macros
)
6293 subtype
|= RELAX_NOMACRO
;
6294 if (mips_macro_warning
.delay_slot_p
)
6295 subtype
|= RELAX_DELAY_SLOT
;
6298 /* If both alternatives fail to fill a delay slot correctly,
6299 emit the warning now. */
6300 if ((subtype
& RELAX_DELAY_SLOT_SIZE_FIRST
) != 0
6301 && (subtype
& RELAX_DELAY_SLOT_SIZE_SECOND
) != 0)
6306 s
= subtype
& (RELAX_DELAY_SLOT_16BIT
6307 | RELAX_DELAY_SLOT_SIZE_FIRST
6308 | RELAX_DELAY_SLOT_SIZE_SECOND
);
6309 msg
= macro_warning (s
);
6311 as_warn ("%s", msg
);
6315 /* If both implementations are longer than 1 instruction, then emit the
6317 if (mips_macro_warning
.insns
[0] > 1 && mips_macro_warning
.insns
[1] > 1)
6322 s
= subtype
& (RELAX_SECOND_LONGER
| RELAX_NOMACRO
| RELAX_DELAY_SLOT
);
6323 msg
= macro_warning (s
);
6325 as_warn ("%s", msg
);
6329 /* If any flags still set, then one implementation might need a warning
6330 and the other either will need one of a different kind or none at all.
6331 Pass any remaining flags over to relaxation. */
6332 if (mips_macro_warning
.first_frag
!= NULL
)
6333 mips_macro_warning
.first_frag
->fr_subtype
|= subtype
;
6336 /* Instruction operand formats used in macros that vary between
6337 standard MIPS and microMIPS code. */
6339 static const char * const brk_fmt
[2][2] = { { "c", "c" }, { "mF", "c" } };
6340 static const char * const cop12_fmt
[2] = { "E,o(b)", "E,~(b)" };
6341 static const char * const jalr_fmt
[2] = { "d,s", "t,s" };
6342 static const char * const lui_fmt
[2] = { "t,u", "s,u" };
6343 static const char * const mem12_fmt
[2] = { "t,o(b)", "t,~(b)" };
6344 static const char * const mfhl_fmt
[2][2] = { { "d", "d" }, { "mj", "s" } };
6345 static const char * const shft_fmt
[2] = { "d,w,<", "t,r,<" };
6346 static const char * const trap_fmt
[2] = { "s,t,q", "s,t,|" };
6348 #define BRK_FMT (brk_fmt[mips_opts.micromips][mips_opts.insn32])
6349 #define COP12_FMT (cop12_fmt[mips_opts.micromips])
6350 #define JALR_FMT (jalr_fmt[mips_opts.micromips])
6351 #define LUI_FMT (lui_fmt[mips_opts.micromips])
6352 #define MEM12_FMT (mem12_fmt[mips_opts.micromips])
6353 #define MFHL_FMT (mfhl_fmt[mips_opts.micromips][mips_opts.insn32])
6354 #define SHFT_FMT (shft_fmt[mips_opts.micromips])
6355 #define TRAP_FMT (trap_fmt[mips_opts.micromips])
6357 /* Read a macro's relocation codes from *ARGS and store them in *R.
6358 The first argument in *ARGS will be either the code for a single
6359 relocation or -1 followed by the three codes that make up a
6360 composite relocation. */
6363 macro_read_relocs (va_list *args
, bfd_reloc_code_real_type
*r
)
6367 next
= va_arg (*args
, int);
6369 r
[0] = (bfd_reloc_code_real_type
) next
;
6372 for (i
= 0; i
< 3; i
++)
6373 r
[i
] = (bfd_reloc_code_real_type
) va_arg (*args
, int);
6374 /* This function is only used for 16-bit relocation fields.
6375 To make the macro code simpler, treat an unrelocated value
6376 in the same way as BFD_RELOC_LO16. */
6377 if (r
[0] == BFD_RELOC_UNUSED
)
6378 r
[0] = BFD_RELOC_LO16
;
6382 /* Build an instruction created by a macro expansion. This is passed
6383 a pointer to the count of instructions created so far, an
6384 expression, the name of the instruction to build, an operand format
6385 string, and corresponding arguments. */
6388 macro_build (expressionS
*ep
, const char *name
, const char *fmt
, ...)
6390 const struct mips_opcode
*mo
= NULL
;
6391 bfd_reloc_code_real_type r
[3];
6392 const struct mips_opcode
*amo
;
6393 const struct mips_operand
*operand
;
6394 struct hash_control
*hash
;
6395 struct mips_cl_insn insn
;
6399 va_start (args
, fmt
);
6401 if (mips_opts
.mips16
)
6403 mips16_macro_build (ep
, name
, fmt
, &args
);
6408 r
[0] = BFD_RELOC_UNUSED
;
6409 r
[1] = BFD_RELOC_UNUSED
;
6410 r
[2] = BFD_RELOC_UNUSED
;
6411 hash
= mips_opts
.micromips
? micromips_op_hash
: op_hash
;
6412 amo
= (struct mips_opcode
*) hash_find (hash
, name
);
6414 gas_assert (strcmp (name
, amo
->name
) == 0);
6418 /* Search until we get a match for NAME. It is assumed here that
6419 macros will never generate MDMX, MIPS-3D, or MT instructions.
6420 We try to match an instruction that fulfils the branch delay
6421 slot instruction length requirement (if any) of the previous
6422 instruction. While doing this we record the first instruction
6423 seen that matches all the other conditions and use it anyway
6424 if the requirement cannot be met; we will issue an appropriate
6425 warning later on. */
6426 if (strcmp (fmt
, amo
->args
) == 0
6427 && amo
->pinfo
!= INSN_MACRO
6428 && is_opcode_valid (amo
)
6429 && is_size_valid (amo
))
6431 if (is_delay_slot_valid (amo
))
6441 gas_assert (amo
->name
);
6443 while (strcmp (name
, amo
->name
) == 0);
6446 create_insn (&insn
, mo
);
6459 macro_read_relocs (&args
, r
);
6460 gas_assert (*r
== BFD_RELOC_GPREL16
6461 || *r
== BFD_RELOC_MIPS_HIGHER
6462 || *r
== BFD_RELOC_HI16_S
6463 || *r
== BFD_RELOC_LO16
6464 || *r
== BFD_RELOC_MIPS_GOT_OFST
);
6468 macro_read_relocs (&args
, r
);
6472 macro_read_relocs (&args
, r
);
6473 gas_assert (ep
!= NULL
6474 && (ep
->X_op
== O_constant
6475 || (ep
->X_op
== O_symbol
6476 && (*r
== BFD_RELOC_MIPS_HIGHEST
6477 || *r
== BFD_RELOC_HI16_S
6478 || *r
== BFD_RELOC_HI16
6479 || *r
== BFD_RELOC_GPREL16
6480 || *r
== BFD_RELOC_MIPS_GOT_HI16
6481 || *r
== BFD_RELOC_MIPS_CALL_HI16
))));
6485 gas_assert (ep
!= NULL
);
6488 * This allows macro() to pass an immediate expression for
6489 * creating short branches without creating a symbol.
6491 * We don't allow branch relaxation for these branches, as
6492 * they should only appear in ".set nomacro" anyway.
6494 if (ep
->X_op
== O_constant
)
6496 /* For microMIPS we always use relocations for branches.
6497 So we should not resolve immediate values. */
6498 gas_assert (!mips_opts
.micromips
);
6500 if ((ep
->X_add_number
& 3) != 0)
6501 as_bad (_("branch to misaligned address (0x%lx)"),
6502 (unsigned long) ep
->X_add_number
);
6503 if ((ep
->X_add_number
+ 0x20000) & ~0x3ffff)
6504 as_bad (_("branch address range overflow (0x%lx)"),
6505 (unsigned long) ep
->X_add_number
);
6506 insn
.insn_opcode
|= (ep
->X_add_number
>> 2) & 0xffff;
6510 *r
= BFD_RELOC_16_PCREL_S2
;
6514 gas_assert (ep
!= NULL
);
6515 *r
= BFD_RELOC_MIPS_JMP
;
6519 operand
= (mips_opts
.micromips
6520 ? decode_micromips_operand (fmt
)
6521 : decode_mips_operand (fmt
));
6525 uval
= va_arg (args
, int);
6526 if (operand
->type
== OP_CLO_CLZ_DEST
)
6527 uval
|= (uval
<< 5);
6528 insn_insert_operand (&insn
, operand
, uval
);
6530 if (*fmt
== '+' || *fmt
== 'm')
6536 gas_assert (*r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
6538 append_insn (&insn
, ep
, r
, TRUE
);
6542 mips16_macro_build (expressionS
*ep
, const char *name
, const char *fmt
,
6545 struct mips_opcode
*mo
;
6546 struct mips_cl_insn insn
;
6547 const struct mips_operand
*operand
;
6548 bfd_reloc_code_real_type r
[3]
6549 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
6551 mo
= (struct mips_opcode
*) hash_find (mips16_op_hash
, name
);
6553 gas_assert (strcmp (name
, mo
->name
) == 0);
6555 while (strcmp (fmt
, mo
->args
) != 0 || mo
->pinfo
== INSN_MACRO
)
6558 gas_assert (mo
->name
);
6559 gas_assert (strcmp (name
, mo
->name
) == 0);
6562 create_insn (&insn
, mo
);
6600 gas_assert (ep
!= NULL
);
6602 if (ep
->X_op
!= O_constant
)
6603 *r
= (int) BFD_RELOC_UNUSED
+ c
;
6604 else if (calculate_reloc (*r
, ep
->X_add_number
, &value
))
6606 mips16_immed (NULL
, 0, c
, *r
, value
, 0, &insn
.insn_opcode
);
6608 *r
= BFD_RELOC_UNUSED
;
6614 operand
= decode_mips16_operand (c
, FALSE
);
6618 insn_insert_operand (&insn
, operand
, va_arg (args
, int));
6623 gas_assert (*r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
6625 append_insn (&insn
, ep
, r
, TRUE
);
6629 * Sign-extend 32-bit mode constants that have bit 31 set and all
6630 * higher bits unset.
6633 normalize_constant_expr (expressionS
*ex
)
6635 if (ex
->X_op
== O_constant
6636 && IS_ZEXT_32BIT_NUM (ex
->X_add_number
))
6637 ex
->X_add_number
= (((ex
->X_add_number
& 0xffffffff) ^ 0x80000000)
6642 * Sign-extend 32-bit mode address offsets that have bit 31 set and
6643 * all higher bits unset.
6646 normalize_address_expr (expressionS
*ex
)
6648 if (((ex
->X_op
== O_constant
&& HAVE_32BIT_ADDRESSES
)
6649 || (ex
->X_op
== O_symbol
&& HAVE_32BIT_SYMBOLS
))
6650 && IS_ZEXT_32BIT_NUM (ex
->X_add_number
))
6651 ex
->X_add_number
= (((ex
->X_add_number
& 0xffffffff) ^ 0x80000000)
6656 * Generate a "jalr" instruction with a relocation hint to the called
6657 * function. This occurs in NewABI PIC code.
6660 macro_build_jalr (expressionS
*ep
, int cprestore
)
6662 static const bfd_reloc_code_real_type jalr_relocs
[2]
6663 = { BFD_RELOC_MIPS_JALR
, BFD_RELOC_MICROMIPS_JALR
};
6664 bfd_reloc_code_real_type jalr_reloc
= jalr_relocs
[mips_opts
.micromips
];
6668 if (MIPS_JALR_HINT_P (ep
))
6673 if (mips_opts
.micromips
)
6675 jalr
= ((mips_opts
.noreorder
&& !cprestore
) || mips_opts
.insn32
6676 ? "jalr" : "jalrs");
6677 if (MIPS_JALR_HINT_P (ep
)
6679 || (history
[0].insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_32BIT
))
6680 macro_build (NULL
, jalr
, "t,s", RA
, PIC_CALL_REG
);
6682 macro_build (NULL
, jalr
, "mj", PIC_CALL_REG
);
6685 macro_build (NULL
, "jalr", "d,s", RA
, PIC_CALL_REG
);
6686 if (MIPS_JALR_HINT_P (ep
))
6687 fix_new_exp (frag_now
, f
- frag_now
->fr_literal
, 4, ep
, FALSE
, jalr_reloc
);
6691 * Generate a "lui" instruction.
6694 macro_build_lui (expressionS
*ep
, int regnum
)
6696 gas_assert (! mips_opts
.mips16
);
6698 if (ep
->X_op
!= O_constant
)
6700 gas_assert (ep
->X_op
== O_symbol
);
6701 /* _gp_disp is a special case, used from s_cpload.
6702 __gnu_local_gp is used if mips_no_shared. */
6703 gas_assert (mips_pic
== NO_PIC
6705 && strcmp (S_GET_NAME (ep
->X_add_symbol
), "_gp_disp") == 0)
6706 || (! mips_in_shared
6707 && strcmp (S_GET_NAME (ep
->X_add_symbol
),
6708 "__gnu_local_gp") == 0));
6711 macro_build (ep
, "lui", LUI_FMT
, regnum
, BFD_RELOC_HI16_S
);
6714 /* Generate a sequence of instructions to do a load or store from a constant
6715 offset off of a base register (breg) into/from a target register (treg),
6716 using AT if necessary. */
6718 macro_build_ldst_constoffset (expressionS
*ep
, const char *op
,
6719 int treg
, int breg
, int dbl
)
6721 gas_assert (ep
->X_op
== O_constant
);
6723 /* Sign-extending 32-bit constants makes their handling easier. */
6725 normalize_constant_expr (ep
);
6727 /* Right now, this routine can only handle signed 32-bit constants. */
6728 if (! IS_SEXT_32BIT_NUM(ep
->X_add_number
+ 0x8000))
6729 as_warn (_("operand overflow"));
6731 if (IS_SEXT_16BIT_NUM(ep
->X_add_number
))
6733 /* Signed 16-bit offset will fit in the op. Easy! */
6734 macro_build (ep
, op
, "t,o(b)", treg
, BFD_RELOC_LO16
, breg
);
6738 /* 32-bit offset, need multiple instructions and AT, like:
6739 lui $tempreg,const_hi (BFD_RELOC_HI16_S)
6740 addu $tempreg,$tempreg,$breg
6741 <op> $treg,const_lo($tempreg) (BFD_RELOC_LO16)
6742 to handle the complete offset. */
6743 macro_build_lui (ep
, AT
);
6744 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, AT
, breg
);
6745 macro_build (ep
, op
, "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
6748 as_bad (_("Macro used $at after \".set noat\""));
6753 * Generates code to set the $at register to true (one)
6754 * if reg is less than the immediate expression.
6757 set_at (int reg
, int unsignedp
)
6759 if (imm_expr
.X_op
== O_constant
6760 && imm_expr
.X_add_number
>= -0x8000
6761 && imm_expr
.X_add_number
< 0x8000)
6762 macro_build (&imm_expr
, unsignedp
? "sltiu" : "slti", "t,r,j",
6763 AT
, reg
, BFD_RELOC_LO16
);
6766 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
6767 macro_build (NULL
, unsignedp
? "sltu" : "slt", "d,v,t", AT
, reg
, AT
);
6771 /* Count the leading zeroes by performing a binary chop. This is a
6772 bulky bit of source, but performance is a LOT better for the
6773 majority of values than a simple loop to count the bits:
6774 for (lcnt = 0; (lcnt < 32); lcnt++)
6775 if ((v) & (1 << (31 - lcnt)))
6777 However it is not code size friendly, and the gain will drop a bit
6778 on certain cached systems.
6780 #define COUNT_TOP_ZEROES(v) \
6781 (((v) & ~0xffff) == 0 \
6782 ? ((v) & ~0xff) == 0 \
6783 ? ((v) & ~0xf) == 0 \
6784 ? ((v) & ~0x3) == 0 \
6785 ? ((v) & ~0x1) == 0 \
6790 : ((v) & ~0x7) == 0 \
6793 : ((v) & ~0x3f) == 0 \
6794 ? ((v) & ~0x1f) == 0 \
6797 : ((v) & ~0x7f) == 0 \
6800 : ((v) & ~0xfff) == 0 \
6801 ? ((v) & ~0x3ff) == 0 \
6802 ? ((v) & ~0x1ff) == 0 \
6805 : ((v) & ~0x7ff) == 0 \
6808 : ((v) & ~0x3fff) == 0 \
6809 ? ((v) & ~0x1fff) == 0 \
6812 : ((v) & ~0x7fff) == 0 \
6815 : ((v) & ~0xffffff) == 0 \
6816 ? ((v) & ~0xfffff) == 0 \
6817 ? ((v) & ~0x3ffff) == 0 \
6818 ? ((v) & ~0x1ffff) == 0 \
6821 : ((v) & ~0x7ffff) == 0 \
6824 : ((v) & ~0x3fffff) == 0 \
6825 ? ((v) & ~0x1fffff) == 0 \
6828 : ((v) & ~0x7fffff) == 0 \
6831 : ((v) & ~0xfffffff) == 0 \
6832 ? ((v) & ~0x3ffffff) == 0 \
6833 ? ((v) & ~0x1ffffff) == 0 \
6836 : ((v) & ~0x7ffffff) == 0 \
6839 : ((v) & ~0x3fffffff) == 0 \
6840 ? ((v) & ~0x1fffffff) == 0 \
6843 : ((v) & ~0x7fffffff) == 0 \
6848 * This routine generates the least number of instructions necessary to load
6849 * an absolute expression value into a register.
6852 load_register (int reg
, expressionS
*ep
, int dbl
)
6855 expressionS hi32
, lo32
;
6857 if (ep
->X_op
!= O_big
)
6859 gas_assert (ep
->X_op
== O_constant
);
6861 /* Sign-extending 32-bit constants makes their handling easier. */
6863 normalize_constant_expr (ep
);
6865 if (IS_SEXT_16BIT_NUM (ep
->X_add_number
))
6867 /* We can handle 16 bit signed values with an addiu to
6868 $zero. No need to ever use daddiu here, since $zero and
6869 the result are always correct in 32 bit mode. */
6870 macro_build (ep
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
6873 else if (ep
->X_add_number
>= 0 && ep
->X_add_number
< 0x10000)
6875 /* We can handle 16 bit unsigned values with an ori to
6877 macro_build (ep
, "ori", "t,r,i", reg
, 0, BFD_RELOC_LO16
);
6880 else if ((IS_SEXT_32BIT_NUM (ep
->X_add_number
)))
6882 /* 32 bit values require an lui. */
6883 macro_build (ep
, "lui", LUI_FMT
, reg
, BFD_RELOC_HI16
);
6884 if ((ep
->X_add_number
& 0xffff) != 0)
6885 macro_build (ep
, "ori", "t,r,i", reg
, reg
, BFD_RELOC_LO16
);
6890 /* The value is larger than 32 bits. */
6892 if (!dbl
|| HAVE_32BIT_GPRS
)
6896 sprintf_vma (value
, ep
->X_add_number
);
6897 as_bad (_("Number (0x%s) larger than 32 bits"), value
);
6898 macro_build (ep
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
6902 if (ep
->X_op
!= O_big
)
6905 hi32
.X_add_number
= (valueT
) hi32
.X_add_number
>> 16;
6906 hi32
.X_add_number
= (valueT
) hi32
.X_add_number
>> 16;
6907 hi32
.X_add_number
&= 0xffffffff;
6909 lo32
.X_add_number
&= 0xffffffff;
6913 gas_assert (ep
->X_add_number
> 2);
6914 if (ep
->X_add_number
== 3)
6915 generic_bignum
[3] = 0;
6916 else if (ep
->X_add_number
> 4)
6917 as_bad (_("Number larger than 64 bits"));
6918 lo32
.X_op
= O_constant
;
6919 lo32
.X_add_number
= generic_bignum
[0] + (generic_bignum
[1] << 16);
6920 hi32
.X_op
= O_constant
;
6921 hi32
.X_add_number
= generic_bignum
[2] + (generic_bignum
[3] << 16);
6924 if (hi32
.X_add_number
== 0)
6929 unsigned long hi
, lo
;
6931 if (hi32
.X_add_number
== (offsetT
) 0xffffffff)
6933 if ((lo32
.X_add_number
& 0xffff8000) == 0xffff8000)
6935 macro_build (&lo32
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
6938 if (lo32
.X_add_number
& 0x80000000)
6940 macro_build (&lo32
, "lui", LUI_FMT
, reg
, BFD_RELOC_HI16
);
6941 if (lo32
.X_add_number
& 0xffff)
6942 macro_build (&lo32
, "ori", "t,r,i", reg
, reg
, BFD_RELOC_LO16
);
6947 /* Check for 16bit shifted constant. We know that hi32 is
6948 non-zero, so start the mask on the first bit of the hi32
6953 unsigned long himask
, lomask
;
6957 himask
= 0xffff >> (32 - shift
);
6958 lomask
= (0xffff << shift
) & 0xffffffff;
6962 himask
= 0xffff << (shift
- 32);
6965 if ((hi32
.X_add_number
& ~(offsetT
) himask
) == 0
6966 && (lo32
.X_add_number
& ~(offsetT
) lomask
) == 0)
6970 tmp
.X_op
= O_constant
;
6972 tmp
.X_add_number
= ((hi32
.X_add_number
<< (32 - shift
))
6973 | (lo32
.X_add_number
>> shift
));
6975 tmp
.X_add_number
= hi32
.X_add_number
>> (shift
- 32);
6976 macro_build (&tmp
, "ori", "t,r,i", reg
, 0, BFD_RELOC_LO16
);
6977 macro_build (NULL
, (shift
>= 32) ? "dsll32" : "dsll", SHFT_FMT
,
6978 reg
, reg
, (shift
>= 32) ? shift
- 32 : shift
);
6983 while (shift
<= (64 - 16));
6985 /* Find the bit number of the lowest one bit, and store the
6986 shifted value in hi/lo. */
6987 hi
= (unsigned long) (hi32
.X_add_number
& 0xffffffff);
6988 lo
= (unsigned long) (lo32
.X_add_number
& 0xffffffff);
6992 while ((lo
& 1) == 0)
6997 lo
|= (hi
& (((unsigned long) 1 << bit
) - 1)) << (32 - bit
);
7003 while ((hi
& 1) == 0)
7012 /* Optimize if the shifted value is a (power of 2) - 1. */
7013 if ((hi
== 0 && ((lo
+ 1) & lo
) == 0)
7014 || (lo
== 0xffffffff && ((hi
+ 1) & hi
) == 0))
7016 shift
= COUNT_TOP_ZEROES ((unsigned int) hi32
.X_add_number
);
7021 /* This instruction will set the register to be all
7023 tmp
.X_op
= O_constant
;
7024 tmp
.X_add_number
= (offsetT
) -1;
7025 macro_build (&tmp
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
7029 macro_build (NULL
, (bit
>= 32) ? "dsll32" : "dsll", SHFT_FMT
,
7030 reg
, reg
, (bit
>= 32) ? bit
- 32 : bit
);
7032 macro_build (NULL
, (shift
>= 32) ? "dsrl32" : "dsrl", SHFT_FMT
,
7033 reg
, reg
, (shift
>= 32) ? shift
- 32 : shift
);
7038 /* Sign extend hi32 before calling load_register, because we can
7039 generally get better code when we load a sign extended value. */
7040 if ((hi32
.X_add_number
& 0x80000000) != 0)
7041 hi32
.X_add_number
|= ~(offsetT
) 0xffffffff;
7042 load_register (reg
, &hi32
, 0);
7045 if ((lo32
.X_add_number
& 0xffff0000) == 0)
7049 macro_build (NULL
, "dsll32", SHFT_FMT
, reg
, freg
, 0);
7057 if ((freg
== 0) && (lo32
.X_add_number
== (offsetT
) 0xffffffff))
7059 macro_build (&lo32
, "lui", LUI_FMT
, reg
, BFD_RELOC_HI16
);
7060 macro_build (NULL
, "dsrl32", SHFT_FMT
, reg
, reg
, 0);
7066 macro_build (NULL
, "dsll", SHFT_FMT
, reg
, freg
, 16);
7070 mid16
.X_add_number
>>= 16;
7071 macro_build (&mid16
, "ori", "t,r,i", reg
, freg
, BFD_RELOC_LO16
);
7072 macro_build (NULL
, "dsll", SHFT_FMT
, reg
, reg
, 16);
7075 if ((lo32
.X_add_number
& 0xffff) != 0)
7076 macro_build (&lo32
, "ori", "t,r,i", reg
, freg
, BFD_RELOC_LO16
);
7080 load_delay_nop (void)
7082 if (!gpr_interlocks
)
7083 macro_build (NULL
, "nop", "");
7086 /* Load an address into a register. */
7089 load_address (int reg
, expressionS
*ep
, int *used_at
)
7091 if (ep
->X_op
!= O_constant
7092 && ep
->X_op
!= O_symbol
)
7094 as_bad (_("expression too complex"));
7095 ep
->X_op
= O_constant
;
7098 if (ep
->X_op
== O_constant
)
7100 load_register (reg
, ep
, HAVE_64BIT_ADDRESSES
);
7104 if (mips_pic
== NO_PIC
)
7106 /* If this is a reference to a GP relative symbol, we want
7107 addiu $reg,$gp,<sym> (BFD_RELOC_GPREL16)
7109 lui $reg,<sym> (BFD_RELOC_HI16_S)
7110 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
7111 If we have an addend, we always use the latter form.
7113 With 64bit address space and a usable $at we want
7114 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
7115 lui $at,<sym> (BFD_RELOC_HI16_S)
7116 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
7117 daddiu $at,<sym> (BFD_RELOC_LO16)
7121 If $at is already in use, we use a path which is suboptimal
7122 on superscalar processors.
7123 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
7124 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
7126 daddiu $reg,<sym> (BFD_RELOC_HI16_S)
7128 daddiu $reg,<sym> (BFD_RELOC_LO16)
7130 For GP relative symbols in 64bit address space we can use
7131 the same sequence as in 32bit address space. */
7132 if (HAVE_64BIT_SYMBOLS
)
7134 if ((valueT
) ep
->X_add_number
<= MAX_GPREL_OFFSET
7135 && !nopic_need_relax (ep
->X_add_symbol
, 1))
7137 relax_start (ep
->X_add_symbol
);
7138 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
,
7139 mips_gp_register
, BFD_RELOC_GPREL16
);
7143 if (*used_at
== 0 && mips_opts
.at
)
7145 macro_build (ep
, "lui", LUI_FMT
, reg
, BFD_RELOC_MIPS_HIGHEST
);
7146 macro_build (ep
, "lui", LUI_FMT
, AT
, BFD_RELOC_HI16_S
);
7147 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
,
7148 BFD_RELOC_MIPS_HIGHER
);
7149 macro_build (ep
, "daddiu", "t,r,j", AT
, AT
, BFD_RELOC_LO16
);
7150 macro_build (NULL
, "dsll32", SHFT_FMT
, reg
, reg
, 0);
7151 macro_build (NULL
, "daddu", "d,v,t", reg
, reg
, AT
);
7156 macro_build (ep
, "lui", LUI_FMT
, reg
, BFD_RELOC_MIPS_HIGHEST
);
7157 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
,
7158 BFD_RELOC_MIPS_HIGHER
);
7159 macro_build (NULL
, "dsll", SHFT_FMT
, reg
, reg
, 16);
7160 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
, BFD_RELOC_HI16_S
);
7161 macro_build (NULL
, "dsll", SHFT_FMT
, reg
, reg
, 16);
7162 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
, BFD_RELOC_LO16
);
7165 if (mips_relax
.sequence
)
7170 if ((valueT
) ep
->X_add_number
<= MAX_GPREL_OFFSET
7171 && !nopic_need_relax (ep
->X_add_symbol
, 1))
7173 relax_start (ep
->X_add_symbol
);
7174 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
,
7175 mips_gp_register
, BFD_RELOC_GPREL16
);
7178 macro_build_lui (ep
, reg
);
7179 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j",
7180 reg
, reg
, BFD_RELOC_LO16
);
7181 if (mips_relax
.sequence
)
7185 else if (!mips_big_got
)
7189 /* If this is a reference to an external symbol, we want
7190 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7192 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7194 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
7195 If there is a constant, it must be added in after.
7197 If we have NewABI, we want
7198 lw $reg,<sym+cst>($gp) (BFD_RELOC_MIPS_GOT_DISP)
7199 unless we're referencing a global symbol with a non-zero
7200 offset, in which case cst must be added separately. */
7203 if (ep
->X_add_number
)
7205 ex
.X_add_number
= ep
->X_add_number
;
7206 ep
->X_add_number
= 0;
7207 relax_start (ep
->X_add_symbol
);
7208 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
7209 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
7210 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
7211 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
7212 ex
.X_op
= O_constant
;
7213 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j",
7214 reg
, reg
, BFD_RELOC_LO16
);
7215 ep
->X_add_number
= ex
.X_add_number
;
7218 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
7219 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
7220 if (mips_relax
.sequence
)
7225 ex
.X_add_number
= ep
->X_add_number
;
7226 ep
->X_add_number
= 0;
7227 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
7228 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
7230 relax_start (ep
->X_add_symbol
);
7232 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
7236 if (ex
.X_add_number
!= 0)
7238 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
7239 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
7240 ex
.X_op
= O_constant
;
7241 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j",
7242 reg
, reg
, BFD_RELOC_LO16
);
7246 else if (mips_big_got
)
7250 /* This is the large GOT case. If this is a reference to an
7251 external symbol, we want
7252 lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
7254 lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16)
7256 Otherwise, for a reference to a local symbol in old ABI, we want
7257 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7259 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
7260 If there is a constant, it must be added in after.
7262 In the NewABI, for local symbols, with or without offsets, we want:
7263 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
7264 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
7268 ex
.X_add_number
= ep
->X_add_number
;
7269 ep
->X_add_number
= 0;
7270 relax_start (ep
->X_add_symbol
);
7271 macro_build (ep
, "lui", LUI_FMT
, reg
, BFD_RELOC_MIPS_GOT_HI16
);
7272 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
7273 reg
, reg
, mips_gp_register
);
7274 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)",
7275 reg
, BFD_RELOC_MIPS_GOT_LO16
, reg
);
7276 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
7277 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
7278 else if (ex
.X_add_number
)
7280 ex
.X_op
= O_constant
;
7281 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
7285 ep
->X_add_number
= ex
.X_add_number
;
7287 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
7288 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
7289 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
7290 BFD_RELOC_MIPS_GOT_OFST
);
7295 ex
.X_add_number
= ep
->X_add_number
;
7296 ep
->X_add_number
= 0;
7297 relax_start (ep
->X_add_symbol
);
7298 macro_build (ep
, "lui", LUI_FMT
, reg
, BFD_RELOC_MIPS_GOT_HI16
);
7299 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
7300 reg
, reg
, mips_gp_register
);
7301 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)",
7302 reg
, BFD_RELOC_MIPS_GOT_LO16
, reg
);
7304 if (reg_needs_delay (mips_gp_register
))
7306 /* We need a nop before loading from $gp. This special
7307 check is required because the lui which starts the main
7308 instruction stream does not refer to $gp, and so will not
7309 insert the nop which may be required. */
7310 macro_build (NULL
, "nop", "");
7312 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
7313 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
7315 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
7319 if (ex
.X_add_number
!= 0)
7321 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
7322 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
7323 ex
.X_op
= O_constant
;
7324 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
7332 if (!mips_opts
.at
&& *used_at
== 1)
7333 as_bad (_("Macro used $at after \".set noat\""));
7336 /* Move the contents of register SOURCE into register DEST. */
7339 move_register (int dest
, int source
)
7341 /* Prefer to use a 16-bit microMIPS instruction unless the previous
7342 instruction specifically requires a 32-bit one. */
7343 if (mips_opts
.micromips
7344 && !mips_opts
.insn32
7345 && !(history
[0].insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_32BIT
))
7346 macro_build (NULL
, "move", "mp,mj", dest
, source
);
7348 macro_build (NULL
, HAVE_32BIT_GPRS
? "addu" : "daddu", "d,v,t",
7352 /* Emit an SVR4 PIC sequence to load address LOCAL into DEST, where
7353 LOCAL is the sum of a symbol and a 16-bit or 32-bit displacement.
7354 The two alternatives are:
7356 Global symbol Local sybmol
7357 ------------- ------------
7358 lw DEST,%got(SYMBOL) lw DEST,%got(SYMBOL + OFFSET)
7360 addiu DEST,DEST,OFFSET addiu DEST,DEST,%lo(SYMBOL + OFFSET)
7362 load_got_offset emits the first instruction and add_got_offset
7363 emits the second for a 16-bit offset or add_got_offset_hilo emits
7364 a sequence to add a 32-bit offset using a scratch register. */
7367 load_got_offset (int dest
, expressionS
*local
)
7372 global
.X_add_number
= 0;
7374 relax_start (local
->X_add_symbol
);
7375 macro_build (&global
, ADDRESS_LOAD_INSN
, "t,o(b)", dest
,
7376 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
7378 macro_build (local
, ADDRESS_LOAD_INSN
, "t,o(b)", dest
,
7379 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
7384 add_got_offset (int dest
, expressionS
*local
)
7388 global
.X_op
= O_constant
;
7389 global
.X_op_symbol
= NULL
;
7390 global
.X_add_symbol
= NULL
;
7391 global
.X_add_number
= local
->X_add_number
;
7393 relax_start (local
->X_add_symbol
);
7394 macro_build (&global
, ADDRESS_ADDI_INSN
, "t,r,j",
7395 dest
, dest
, BFD_RELOC_LO16
);
7397 macro_build (local
, ADDRESS_ADDI_INSN
, "t,r,j", dest
, dest
, BFD_RELOC_LO16
);
7402 add_got_offset_hilo (int dest
, expressionS
*local
, int tmp
)
7405 int hold_mips_optimize
;
7407 global
.X_op
= O_constant
;
7408 global
.X_op_symbol
= NULL
;
7409 global
.X_add_symbol
= NULL
;
7410 global
.X_add_number
= local
->X_add_number
;
7412 relax_start (local
->X_add_symbol
);
7413 load_register (tmp
, &global
, HAVE_64BIT_ADDRESSES
);
7415 /* Set mips_optimize around the lui instruction to avoid
7416 inserting an unnecessary nop after the lw. */
7417 hold_mips_optimize
= mips_optimize
;
7419 macro_build_lui (&global
, tmp
);
7420 mips_optimize
= hold_mips_optimize
;
7421 macro_build (local
, ADDRESS_ADDI_INSN
, "t,r,j", tmp
, tmp
, BFD_RELOC_LO16
);
7424 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", dest
, dest
, tmp
);
7427 /* Emit a sequence of instructions to emulate a branch likely operation.
7428 BR is an ordinary branch corresponding to one to be emulated. BRNEG
7429 is its complementing branch with the original condition negated.
7430 CALL is set if the original branch specified the link operation.
7431 EP, FMT, SREG and TREG specify the usual macro_build() parameters.
7433 Code like this is produced in the noreorder mode:
7438 delay slot (executed only if branch taken)
7446 delay slot (executed only if branch taken)
7449 In the reorder mode the delay slot would be filled with a nop anyway,
7450 so code produced is simply:
7455 This function is used when producing code for the microMIPS ASE that
7456 does not implement branch likely instructions in hardware. */
7459 macro_build_branch_likely (const char *br
, const char *brneg
,
7460 int call
, expressionS
*ep
, const char *fmt
,
7461 unsigned int sreg
, unsigned int treg
)
7463 int noreorder
= mips_opts
.noreorder
;
7466 gas_assert (mips_opts
.micromips
);
7470 micromips_label_expr (&expr1
);
7471 macro_build (&expr1
, brneg
, fmt
, sreg
, treg
);
7472 macro_build (NULL
, "nop", "");
7473 macro_build (ep
, call
? "bal" : "b", "p");
7475 /* Set to true so that append_insn adds a label. */
7476 emit_branch_likely_macro
= TRUE
;
7480 macro_build (ep
, br
, fmt
, sreg
, treg
);
7481 macro_build (NULL
, "nop", "");
7486 /* Emit a coprocessor branch-likely macro specified by TYPE, using CC as
7487 the condition code tested. EP specifies the branch target. */
7490 macro_build_branch_ccl (int type
, expressionS
*ep
, unsigned int cc
)
7517 macro_build_branch_likely (br
, brneg
, call
, ep
, "N,p", cc
, ZERO
);
7520 /* Emit a two-argument branch macro specified by TYPE, using SREG as
7521 the register tested. EP specifies the branch target. */
7524 macro_build_branch_rs (int type
, expressionS
*ep
, unsigned int sreg
)
7526 const char *brneg
= NULL
;
7536 br
= mips_opts
.micromips
? "bgez" : "bgezl";
7540 gas_assert (mips_opts
.micromips
);
7541 br
= mips_opts
.insn32
? "bgezal" : "bgezals";
7549 br
= mips_opts
.micromips
? "bgtz" : "bgtzl";
7556 br
= mips_opts
.micromips
? "blez" : "blezl";
7563 br
= mips_opts
.micromips
? "bltz" : "bltzl";
7567 gas_assert (mips_opts
.micromips
);
7568 br
= mips_opts
.insn32
? "bltzal" : "bltzals";
7575 if (mips_opts
.micromips
&& brneg
)
7576 macro_build_branch_likely (br
, brneg
, call
, ep
, "s,p", sreg
, ZERO
);
7578 macro_build (ep
, br
, "s,p", sreg
);
7581 /* Emit a three-argument branch macro specified by TYPE, using SREG and
7582 TREG as the registers tested. EP specifies the branch target. */
7585 macro_build_branch_rsrt (int type
, expressionS
*ep
,
7586 unsigned int sreg
, unsigned int treg
)
7588 const char *brneg
= NULL
;
7600 br
= mips_opts
.micromips
? "beq" : "beql";
7609 br
= mips_opts
.micromips
? "bne" : "bnel";
7615 if (mips_opts
.micromips
&& brneg
)
7616 macro_build_branch_likely (br
, brneg
, call
, ep
, "s,t,p", sreg
, treg
);
7618 macro_build (ep
, br
, "s,t,p", sreg
, treg
);
7621 /* Return the high part that should be loaded in order to make the low
7622 part of VALUE accessible using an offset of OFFBITS bits. */
7625 offset_high_part (offsetT value
, unsigned int offbits
)
7632 bias
= 1 << (offbits
- 1);
7633 low_mask
= bias
* 2 - 1;
7634 return (value
+ bias
) & ~low_mask
;
7637 /* Return true if the value stored in offset_expr and offset_reloc
7638 fits into a signed offset of OFFBITS bits. RANGE is the maximum
7639 amount that the caller wants to add without inducing overflow
7640 and ALIGN is the known alignment of the value in bytes. */
7643 small_offset_p (unsigned int range
, unsigned int align
, unsigned int offbits
)
7647 /* Accept any relocation operator if overflow isn't a concern. */
7648 if (range
< align
&& *offset_reloc
!= BFD_RELOC_UNUSED
)
7651 /* These relocations are guaranteed not to overflow in correct links. */
7652 if (*offset_reloc
== BFD_RELOC_MIPS_LITERAL
7653 || gprel16_reloc_p (*offset_reloc
))
7656 if (offset_expr
.X_op
== O_constant
7657 && offset_high_part (offset_expr
.X_add_number
, offbits
) == 0
7658 && offset_high_part (offset_expr
.X_add_number
+ range
, offbits
) == 0)
7665 * This routine implements the seemingly endless macro or synthesized
7666 * instructions and addressing modes in the mips assembly language. Many
7667 * of these macros are simple and are similar to each other. These could
7668 * probably be handled by some kind of table or grammar approach instead of
7669 * this verbose method. Others are not simple macros but are more like
7670 * optimizing code generation.
7671 * One interesting optimization is when several store macros appear
7672 * consecutively that would load AT with the upper half of the same address.
7673 * The ensuing load upper instructions are ommited. This implies some kind
7674 * of global optimization. We currently only optimize within a single macro.
7675 * For many of the load and store macros if the address is specified as a
7676 * constant expression in the first 64k of memory (ie ld $2,0x4000c) we
7677 * first load register 'at' with zero and use it as the base register. The
7678 * mips assembler simply uses register $zero. Just one tiny optimization
7682 macro (struct mips_cl_insn
*ip
, char *str
)
7684 unsigned int treg
, sreg
, dreg
, breg
;
7685 unsigned int tempreg
;
7688 expressionS label_expr
;
7703 bfd_boolean large_offset
;
7705 int hold_mips_optimize
;
7708 gas_assert (! mips_opts
.mips16
);
7710 treg
= EXTRACT_OPERAND (mips_opts
.micromips
, RT
, *ip
);
7711 dreg
= EXTRACT_OPERAND (mips_opts
.micromips
, RD
, *ip
);
7712 sreg
= breg
= EXTRACT_OPERAND (mips_opts
.micromips
, RS
, *ip
);
7713 mask
= ip
->insn_mo
->mask
;
7715 label_expr
.X_op
= O_constant
;
7716 label_expr
.X_op_symbol
= NULL
;
7717 label_expr
.X_add_symbol
= NULL
;
7718 label_expr
.X_add_number
= 0;
7720 expr1
.X_op
= O_constant
;
7721 expr1
.X_op_symbol
= NULL
;
7722 expr1
.X_add_symbol
= NULL
;
7723 expr1
.X_add_number
= 1;
7739 if (mips_opts
.micromips
)
7740 micromips_label_expr (&label_expr
);
7742 label_expr
.X_add_number
= 8;
7743 macro_build (&label_expr
, "bgez", "s,p", sreg
);
7745 macro_build (NULL
, "nop", "");
7747 move_register (dreg
, sreg
);
7748 macro_build (NULL
, dbl
? "dsub" : "sub", "d,v,t", dreg
, 0, sreg
);
7749 if (mips_opts
.micromips
)
7750 micromips_add_label ();
7767 if (!mips_opts
.micromips
)
7769 if (imm_expr
.X_op
== O_constant
7770 && imm_expr
.X_add_number
>= -0x200
7771 && imm_expr
.X_add_number
< 0x200)
7773 macro_build (NULL
, s
, "t,r,.", treg
, sreg
, imm_expr
.X_add_number
);
7782 if (imm_expr
.X_op
== O_constant
7783 && imm_expr
.X_add_number
>= -0x8000
7784 && imm_expr
.X_add_number
< 0x8000)
7786 macro_build (&imm_expr
, s
, "t,r,j", treg
, sreg
, BFD_RELOC_LO16
);
7791 load_register (AT
, &imm_expr
, dbl
);
7792 macro_build (NULL
, s2
, "d,v,t", treg
, sreg
, AT
);
7811 if (imm_expr
.X_op
== O_constant
7812 && imm_expr
.X_add_number
>= 0
7813 && imm_expr
.X_add_number
< 0x10000)
7815 if (mask
!= M_NOR_I
)
7816 macro_build (&imm_expr
, s
, "t,r,i", treg
, sreg
, BFD_RELOC_LO16
);
7819 macro_build (&imm_expr
, "ori", "t,r,i",
7820 treg
, sreg
, BFD_RELOC_LO16
);
7821 macro_build (NULL
, "nor", "d,v,t", treg
, treg
, 0);
7827 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7828 macro_build (NULL
, s2
, "d,v,t", treg
, sreg
, AT
);
7832 switch (imm_expr
.X_add_number
)
7835 macro_build (NULL
, "nop", "");
7838 macro_build (NULL
, "packrl.ph", "d,s,t", treg
, treg
, sreg
);
7842 macro_build (NULL
, "balign", "t,s,2", treg
, sreg
,
7843 (int) imm_expr
.X_add_number
);
7846 as_bad (_("BALIGN immediate not 0, 1, 2 or 3 (%lu)"),
7847 (unsigned long) imm_expr
.X_add_number
);
7856 gas_assert (mips_opts
.micromips
);
7857 macro_build_branch_ccl (mask
, &offset_expr
,
7858 EXTRACT_OPERAND (1, BCC
, *ip
));
7865 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
7871 load_register (treg
, &imm_expr
, HAVE_64BIT_GPRS
);
7876 macro_build_branch_rsrt (mask
, &offset_expr
, sreg
, treg
);
7883 macro_build_branch_rs (likely
? M_BGEZL
: M_BGEZ
, &offset_expr
, sreg
);
7885 macro_build_branch_rs (likely
? M_BLEZL
: M_BLEZ
, &offset_expr
, treg
);
7889 macro_build (NULL
, "slt", "d,v,t", AT
, sreg
, treg
);
7890 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
7891 &offset_expr
, AT
, ZERO
);
7901 macro_build_branch_rs (mask
, &offset_expr
, sreg
);
7907 /* Check for > max integer. */
7908 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
>= GPR_SMAX
)
7911 /* Result is always false. */
7913 macro_build (NULL
, "nop", "");
7915 macro_build_branch_rsrt (M_BNEL
, &offset_expr
, ZERO
, ZERO
);
7918 if (imm_expr
.X_op
!= O_constant
)
7919 as_bad (_("Unsupported large constant"));
7920 ++imm_expr
.X_add_number
;
7924 if (mask
== M_BGEL_I
)
7926 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
7928 macro_build_branch_rs (likely
? M_BGEZL
: M_BGEZ
,
7929 &offset_expr
, sreg
);
7932 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
7934 macro_build_branch_rs (likely
? M_BGTZL
: M_BGTZ
,
7935 &offset_expr
, sreg
);
7938 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
<= GPR_SMIN
)
7941 /* result is always true */
7942 as_warn (_("Branch %s is always true"), ip
->insn_mo
->name
);
7943 macro_build (&offset_expr
, "b", "p");
7948 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
7949 &offset_expr
, AT
, ZERO
);
7958 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
7959 &offset_expr
, ZERO
, treg
);
7963 macro_build (NULL
, "sltu", "d,v,t", AT
, sreg
, treg
);
7964 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
7965 &offset_expr
, AT
, ZERO
);
7974 && imm_expr
.X_op
== O_constant
7975 && imm_expr
.X_add_number
== -1))
7977 if (imm_expr
.X_op
!= O_constant
)
7978 as_bad (_("Unsupported large constant"));
7979 ++imm_expr
.X_add_number
;
7983 if (mask
== M_BGEUL_I
)
7985 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
7987 else if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
7988 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
7989 &offset_expr
, sreg
, ZERO
);
7994 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
7995 &offset_expr
, AT
, ZERO
);
8003 macro_build_branch_rs (likely
? M_BGTZL
: M_BGTZ
, &offset_expr
, sreg
);
8005 macro_build_branch_rs (likely
? M_BLTZL
: M_BLTZ
, &offset_expr
, treg
);
8009 macro_build (NULL
, "slt", "d,v,t", AT
, treg
, sreg
);
8010 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
8011 &offset_expr
, AT
, ZERO
);
8019 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
8020 &offset_expr
, sreg
, ZERO
);
8026 macro_build (NULL
, "sltu", "d,v,t", AT
, treg
, sreg
);
8027 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
8028 &offset_expr
, AT
, ZERO
);
8036 macro_build_branch_rs (likely
? M_BLEZL
: M_BLEZ
, &offset_expr
, sreg
);
8038 macro_build_branch_rs (likely
? M_BGEZL
: M_BGEZ
, &offset_expr
, treg
);
8042 macro_build (NULL
, "slt", "d,v,t", AT
, treg
, sreg
);
8043 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
8044 &offset_expr
, AT
, ZERO
);
8051 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
>= GPR_SMAX
)
8053 if (imm_expr
.X_op
!= O_constant
)
8054 as_bad (_("Unsupported large constant"));
8055 ++imm_expr
.X_add_number
;
8059 if (mask
== M_BLTL_I
)
8061 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
8062 macro_build_branch_rs (likely
? M_BLTZL
: M_BLTZ
, &offset_expr
, sreg
);
8063 else if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
8064 macro_build_branch_rs (likely
? M_BLEZL
: M_BLEZ
, &offset_expr
, sreg
);
8069 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
8070 &offset_expr
, AT
, ZERO
);
8078 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
8079 &offset_expr
, sreg
, ZERO
);
8085 macro_build (NULL
, "sltu", "d,v,t", AT
, treg
, sreg
);
8086 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
8087 &offset_expr
, AT
, ZERO
);
8096 && imm_expr
.X_op
== O_constant
8097 && imm_expr
.X_add_number
== -1))
8099 if (imm_expr
.X_op
!= O_constant
)
8100 as_bad (_("Unsupported large constant"));
8101 ++imm_expr
.X_add_number
;
8105 if (mask
== M_BLTUL_I
)
8107 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
8109 else if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
8110 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
8111 &offset_expr
, sreg
, ZERO
);
8116 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
8117 &offset_expr
, AT
, ZERO
);
8125 macro_build_branch_rs (likely
? M_BLTZL
: M_BLTZ
, &offset_expr
, sreg
);
8127 macro_build_branch_rs (likely
? M_BGTZL
: M_BGTZ
, &offset_expr
, treg
);
8131 macro_build (NULL
, "slt", "d,v,t", AT
, sreg
, treg
);
8132 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
8133 &offset_expr
, AT
, ZERO
);
8143 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
8144 &offset_expr
, ZERO
, treg
);
8148 macro_build (NULL
, "sltu", "d,v,t", AT
, sreg
, treg
);
8149 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
8150 &offset_expr
, AT
, ZERO
);
8156 /* Use unsigned arithmetic. */
8160 if (imm_expr
.X_op
!= O_constant
|| imm2_expr
.X_op
!= O_constant
)
8162 as_bad (_("Unsupported large constant"));
8167 pos
= imm_expr
.X_add_number
;
8168 size
= imm2_expr
.X_add_number
;
8173 report_bad_range (ip
, 3, pos
, 0, 63, FALSE
);
8176 if (size
== 0 || size
> 64 || (pos
+ size
- 1) > 63)
8178 report_bad_field (pos
, size
);
8182 if (size
<= 32 && pos
< 32)
8187 else if (size
<= 32)
8197 macro_build ((expressionS
*) NULL
, s
, fmt
, treg
, sreg
, (int) pos
,
8204 /* Use unsigned arithmetic. */
8208 if (imm_expr
.X_op
!= O_constant
|| imm2_expr
.X_op
!= O_constant
)
8210 as_bad (_("Unsupported large constant"));
8215 pos
= imm_expr
.X_add_number
;
8216 size
= imm2_expr
.X_add_number
;
8221 report_bad_range (ip
, 3, pos
, 0, 63, FALSE
);
8224 if (size
== 0 || size
> 64 || (pos
+ size
- 1) > 63)
8226 report_bad_field (pos
, size
);
8230 if (pos
< 32 && (pos
+ size
- 1) < 32)
8245 macro_build ((expressionS
*) NULL
, s
, fmt
, treg
, sreg
, (int) pos
,
8246 (int) (pos
+ size
- 1));
8262 as_warn (_("Divide by zero."));
8264 macro_build (NULL
, "teq", TRAP_FMT
, ZERO
, ZERO
, 7);
8266 macro_build (NULL
, "break", BRK_FMT
, 7);
8273 macro_build (NULL
, "teq", TRAP_FMT
, treg
, ZERO
, 7);
8274 macro_build (NULL
, dbl
? "ddiv" : "div", "z,s,t", sreg
, treg
);
8278 if (mips_opts
.micromips
)
8279 micromips_label_expr (&label_expr
);
8281 label_expr
.X_add_number
= 8;
8282 macro_build (&label_expr
, "bne", "s,t,p", treg
, ZERO
);
8283 macro_build (NULL
, dbl
? "ddiv" : "div", "z,s,t", sreg
, treg
);
8284 macro_build (NULL
, "break", BRK_FMT
, 7);
8285 if (mips_opts
.micromips
)
8286 micromips_add_label ();
8288 expr1
.X_add_number
= -1;
8290 load_register (AT
, &expr1
, dbl
);
8291 if (mips_opts
.micromips
)
8292 micromips_label_expr (&label_expr
);
8294 label_expr
.X_add_number
= mips_trap
? (dbl
? 12 : 8) : (dbl
? 20 : 16);
8295 macro_build (&label_expr
, "bne", "s,t,p", treg
, AT
);
8298 expr1
.X_add_number
= 1;
8299 load_register (AT
, &expr1
, dbl
);
8300 macro_build (NULL
, "dsll32", SHFT_FMT
, AT
, AT
, 31);
8304 expr1
.X_add_number
= 0x80000000;
8305 macro_build (&expr1
, "lui", LUI_FMT
, AT
, BFD_RELOC_HI16
);
8309 macro_build (NULL
, "teq", TRAP_FMT
, sreg
, AT
, 6);
8310 /* We want to close the noreorder block as soon as possible, so
8311 that later insns are available for delay slot filling. */
8316 if (mips_opts
.micromips
)
8317 micromips_label_expr (&label_expr
);
8319 label_expr
.X_add_number
= 8;
8320 macro_build (&label_expr
, "bne", "s,t,p", sreg
, AT
);
8321 macro_build (NULL
, "nop", "");
8323 /* We want to close the noreorder block as soon as possible, so
8324 that later insns are available for delay slot filling. */
8327 macro_build (NULL
, "break", BRK_FMT
, 6);
8329 if (mips_opts
.micromips
)
8330 micromips_add_label ();
8331 macro_build (NULL
, s
, MFHL_FMT
, dreg
);
8370 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
8372 as_warn (_("Divide by zero."));
8374 macro_build (NULL
, "teq", TRAP_FMT
, ZERO
, ZERO
, 7);
8376 macro_build (NULL
, "break", BRK_FMT
, 7);
8379 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
8381 if (strcmp (s2
, "mflo") == 0)
8382 move_register (dreg
, sreg
);
8384 move_register (dreg
, ZERO
);
8387 if (imm_expr
.X_op
== O_constant
8388 && imm_expr
.X_add_number
== -1
8389 && s
[strlen (s
) - 1] != 'u')
8391 if (strcmp (s2
, "mflo") == 0)
8393 macro_build (NULL
, dbl
? "dneg" : "neg", "d,w", dreg
, sreg
);
8396 move_register (dreg
, ZERO
);
8401 load_register (AT
, &imm_expr
, dbl
);
8402 macro_build (NULL
, s
, "z,s,t", sreg
, AT
);
8403 macro_build (NULL
, s2
, MFHL_FMT
, dreg
);
8425 macro_build (NULL
, "teq", TRAP_FMT
, treg
, ZERO
, 7);
8426 macro_build (NULL
, s
, "z,s,t", sreg
, treg
);
8427 /* We want to close the noreorder block as soon as possible, so
8428 that later insns are available for delay slot filling. */
8433 if (mips_opts
.micromips
)
8434 micromips_label_expr (&label_expr
);
8436 label_expr
.X_add_number
= 8;
8437 macro_build (&label_expr
, "bne", "s,t,p", treg
, ZERO
);
8438 macro_build (NULL
, s
, "z,s,t", sreg
, treg
);
8440 /* We want to close the noreorder block as soon as possible, so
8441 that later insns are available for delay slot filling. */
8443 macro_build (NULL
, "break", BRK_FMT
, 7);
8444 if (mips_opts
.micromips
)
8445 micromips_add_label ();
8447 macro_build (NULL
, s2
, MFHL_FMT
, dreg
);
8459 /* Load the address of a symbol into a register. If breg is not
8460 zero, we then add a base register to it. */
8462 if (dbl
&& HAVE_32BIT_GPRS
)
8463 as_warn (_("dla used to load 32-bit register"));
8465 if (!dbl
&& HAVE_64BIT_OBJECTS
)
8466 as_warn (_("la used to load 64-bit address"));
8468 if (small_offset_p (0, align
, 16))
8470 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j", treg
, breg
,
8471 -1, offset_reloc
[0], offset_reloc
[1], offset_reloc
[2]);
8475 if (mips_opts
.at
&& (treg
== breg
))
8485 if (offset_expr
.X_op
!= O_symbol
8486 && offset_expr
.X_op
!= O_constant
)
8488 as_bad (_("Expression too complex"));
8489 offset_expr
.X_op
= O_constant
;
8492 if (offset_expr
.X_op
== O_constant
)
8493 load_register (tempreg
, &offset_expr
, HAVE_64BIT_ADDRESSES
);
8494 else if (mips_pic
== NO_PIC
)
8496 /* If this is a reference to a GP relative symbol, we want
8497 addiu $tempreg,$gp,<sym> (BFD_RELOC_GPREL16)
8499 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
8500 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
8501 If we have a constant, we need two instructions anyhow,
8502 so we may as well always use the latter form.
8504 With 64bit address space and a usable $at we want
8505 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
8506 lui $at,<sym> (BFD_RELOC_HI16_S)
8507 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
8508 daddiu $at,<sym> (BFD_RELOC_LO16)
8510 daddu $tempreg,$tempreg,$at
8512 If $at is already in use, we use a path which is suboptimal
8513 on superscalar processors.
8514 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
8515 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
8517 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
8519 daddiu $tempreg,<sym> (BFD_RELOC_LO16)
8521 For GP relative symbols in 64bit address space we can use
8522 the same sequence as in 32bit address space. */
8523 if (HAVE_64BIT_SYMBOLS
)
8525 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
8526 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
8528 relax_start (offset_expr
.X_add_symbol
);
8529 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
8530 tempreg
, mips_gp_register
, BFD_RELOC_GPREL16
);
8534 if (used_at
== 0 && mips_opts
.at
)
8536 macro_build (&offset_expr
, "lui", LUI_FMT
,
8537 tempreg
, BFD_RELOC_MIPS_HIGHEST
);
8538 macro_build (&offset_expr
, "lui", LUI_FMT
,
8539 AT
, BFD_RELOC_HI16_S
);
8540 macro_build (&offset_expr
, "daddiu", "t,r,j",
8541 tempreg
, tempreg
, BFD_RELOC_MIPS_HIGHER
);
8542 macro_build (&offset_expr
, "daddiu", "t,r,j",
8543 AT
, AT
, BFD_RELOC_LO16
);
8544 macro_build (NULL
, "dsll32", SHFT_FMT
, tempreg
, tempreg
, 0);
8545 macro_build (NULL
, "daddu", "d,v,t", tempreg
, tempreg
, AT
);
8550 macro_build (&offset_expr
, "lui", LUI_FMT
,
8551 tempreg
, BFD_RELOC_MIPS_HIGHEST
);
8552 macro_build (&offset_expr
, "daddiu", "t,r,j",
8553 tempreg
, tempreg
, BFD_RELOC_MIPS_HIGHER
);
8554 macro_build (NULL
, "dsll", SHFT_FMT
, tempreg
, tempreg
, 16);
8555 macro_build (&offset_expr
, "daddiu", "t,r,j",
8556 tempreg
, tempreg
, BFD_RELOC_HI16_S
);
8557 macro_build (NULL
, "dsll", SHFT_FMT
, tempreg
, tempreg
, 16);
8558 macro_build (&offset_expr
, "daddiu", "t,r,j",
8559 tempreg
, tempreg
, BFD_RELOC_LO16
);
8562 if (mips_relax
.sequence
)
8567 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
8568 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
8570 relax_start (offset_expr
.X_add_symbol
);
8571 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
8572 tempreg
, mips_gp_register
, BFD_RELOC_GPREL16
);
8575 if (!IS_SEXT_32BIT_NUM (offset_expr
.X_add_number
))
8576 as_bad (_("Offset too large"));
8577 macro_build_lui (&offset_expr
, tempreg
);
8578 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
8579 tempreg
, tempreg
, BFD_RELOC_LO16
);
8580 if (mips_relax
.sequence
)
8584 else if (!mips_big_got
&& !HAVE_NEWABI
)
8586 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT16
;
8588 /* If this is a reference to an external symbol, and there
8589 is no constant, we want
8590 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
8591 or for lca or if tempreg is PIC_CALL_REG
8592 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
8593 For a local symbol, we want
8594 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
8596 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
8598 If we have a small constant, and this is a reference to
8599 an external symbol, we want
8600 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
8602 addiu $tempreg,$tempreg,<constant>
8603 For a local symbol, we want the same instruction
8604 sequence, but we output a BFD_RELOC_LO16 reloc on the
8607 If we have a large constant, and this is a reference to
8608 an external symbol, we want
8609 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
8610 lui $at,<hiconstant>
8611 addiu $at,$at,<loconstant>
8612 addu $tempreg,$tempreg,$at
8613 For a local symbol, we want the same instruction
8614 sequence, but we output a BFD_RELOC_LO16 reloc on the
8618 if (offset_expr
.X_add_number
== 0)
8620 if (mips_pic
== SVR4_PIC
8622 && (call
|| tempreg
== PIC_CALL_REG
))
8623 lw_reloc_type
= (int) BFD_RELOC_MIPS_CALL16
;
8625 relax_start (offset_expr
.X_add_symbol
);
8626 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
8627 lw_reloc_type
, mips_gp_register
);
8630 /* We're going to put in an addu instruction using
8631 tempreg, so we may as well insert the nop right
8636 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
8637 tempreg
, BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
8639 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
8640 tempreg
, tempreg
, BFD_RELOC_LO16
);
8642 /* FIXME: If breg == 0, and the next instruction uses
8643 $tempreg, then if this variant case is used an extra
8644 nop will be generated. */
8646 else if (offset_expr
.X_add_number
>= -0x8000
8647 && offset_expr
.X_add_number
< 0x8000)
8649 load_got_offset (tempreg
, &offset_expr
);
8651 add_got_offset (tempreg
, &offset_expr
);
8655 expr1
.X_add_number
= offset_expr
.X_add_number
;
8656 offset_expr
.X_add_number
=
8657 SEXT_16BIT (offset_expr
.X_add_number
);
8658 load_got_offset (tempreg
, &offset_expr
);
8659 offset_expr
.X_add_number
= expr1
.X_add_number
;
8660 /* If we are going to add in a base register, and the
8661 target register and the base register are the same,
8662 then we are using AT as a temporary register. Since
8663 we want to load the constant into AT, we add our
8664 current AT (from the global offset table) and the
8665 register into the register now, and pretend we were
8666 not using a base register. */
8670 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
8675 add_got_offset_hilo (tempreg
, &offset_expr
, AT
);
8679 else if (!mips_big_got
&& HAVE_NEWABI
)
8681 int add_breg_early
= 0;
8683 /* If this is a reference to an external, and there is no
8684 constant, or local symbol (*), with or without a
8686 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
8687 or for lca or if tempreg is PIC_CALL_REG
8688 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
8690 If we have a small constant, and this is a reference to
8691 an external symbol, we want
8692 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
8693 addiu $tempreg,$tempreg,<constant>
8695 If we have a large constant, and this is a reference to
8696 an external symbol, we want
8697 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
8698 lui $at,<hiconstant>
8699 addiu $at,$at,<loconstant>
8700 addu $tempreg,$tempreg,$at
8702 (*) Other assemblers seem to prefer GOT_PAGE/GOT_OFST for
8703 local symbols, even though it introduces an additional
8706 if (offset_expr
.X_add_number
)
8708 expr1
.X_add_number
= offset_expr
.X_add_number
;
8709 offset_expr
.X_add_number
= 0;
8711 relax_start (offset_expr
.X_add_symbol
);
8712 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
8713 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
8715 if (expr1
.X_add_number
>= -0x8000
8716 && expr1
.X_add_number
< 0x8000)
8718 macro_build (&expr1
, ADDRESS_ADDI_INSN
, "t,r,j",
8719 tempreg
, tempreg
, BFD_RELOC_LO16
);
8721 else if (IS_SEXT_32BIT_NUM (expr1
.X_add_number
+ 0x8000))
8723 /* If we are going to add in a base register, and the
8724 target register and the base register are the same,
8725 then we are using AT as a temporary register. Since
8726 we want to load the constant into AT, we add our
8727 current AT (from the global offset table) and the
8728 register into the register now, and pretend we were
8729 not using a base register. */
8734 gas_assert (tempreg
== AT
);
8735 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
8741 load_register (AT
, &expr1
, HAVE_64BIT_ADDRESSES
);
8742 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
8748 as_bad (_("PIC code offset overflow (max 32 signed bits)"));
8751 offset_expr
.X_add_number
= expr1
.X_add_number
;
8753 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
8754 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
8757 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
8758 treg
, tempreg
, breg
);
8764 else if (breg
== 0 && (call
|| tempreg
== PIC_CALL_REG
))
8766 relax_start (offset_expr
.X_add_symbol
);
8767 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
8768 BFD_RELOC_MIPS_CALL16
, mips_gp_register
);
8770 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
8771 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
8776 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
8777 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
8780 else if (mips_big_got
&& !HAVE_NEWABI
)
8783 int lui_reloc_type
= (int) BFD_RELOC_MIPS_GOT_HI16
;
8784 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT_LO16
;
8785 int local_reloc_type
= (int) BFD_RELOC_MIPS_GOT16
;
8787 /* This is the large GOT case. If this is a reference to an
8788 external symbol, and there is no constant, we want
8789 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
8790 addu $tempreg,$tempreg,$gp
8791 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
8792 or for lca or if tempreg is PIC_CALL_REG
8793 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
8794 addu $tempreg,$tempreg,$gp
8795 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
8796 For a local symbol, we want
8797 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
8799 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
8801 If we have a small constant, and this is a reference to
8802 an external symbol, we want
8803 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
8804 addu $tempreg,$tempreg,$gp
8805 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
8807 addiu $tempreg,$tempreg,<constant>
8808 For a local symbol, we want
8809 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
8811 addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16)
8813 If we have a large constant, and this is a reference to
8814 an external symbol, we want
8815 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
8816 addu $tempreg,$tempreg,$gp
8817 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
8818 lui $at,<hiconstant>
8819 addiu $at,$at,<loconstant>
8820 addu $tempreg,$tempreg,$at
8821 For a local symbol, we want
8822 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
8823 lui $at,<hiconstant>
8824 addiu $at,$at,<loconstant> (BFD_RELOC_LO16)
8825 addu $tempreg,$tempreg,$at
8828 expr1
.X_add_number
= offset_expr
.X_add_number
;
8829 offset_expr
.X_add_number
= 0;
8830 relax_start (offset_expr
.X_add_symbol
);
8831 gpdelay
= reg_needs_delay (mips_gp_register
);
8832 if (expr1
.X_add_number
== 0 && breg
== 0
8833 && (call
|| tempreg
== PIC_CALL_REG
))
8835 lui_reloc_type
= (int) BFD_RELOC_MIPS_CALL_HI16
;
8836 lw_reloc_type
= (int) BFD_RELOC_MIPS_CALL_LO16
;
8838 macro_build (&offset_expr
, "lui", LUI_FMT
, tempreg
, lui_reloc_type
);
8839 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
8840 tempreg
, tempreg
, mips_gp_register
);
8841 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
8842 tempreg
, lw_reloc_type
, tempreg
);
8843 if (expr1
.X_add_number
== 0)
8847 /* We're going to put in an addu instruction using
8848 tempreg, so we may as well insert the nop right
8853 else if (expr1
.X_add_number
>= -0x8000
8854 && expr1
.X_add_number
< 0x8000)
8857 macro_build (&expr1
, ADDRESS_ADDI_INSN
, "t,r,j",
8858 tempreg
, tempreg
, BFD_RELOC_LO16
);
8862 /* If we are going to add in a base register, and the
8863 target register and the base register are the same,
8864 then we are using AT as a temporary register. Since
8865 we want to load the constant into AT, we add our
8866 current AT (from the global offset table) and the
8867 register into the register now, and pretend we were
8868 not using a base register. */
8873 gas_assert (tempreg
== AT
);
8875 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
8880 load_register (AT
, &expr1
, HAVE_64BIT_ADDRESSES
);
8881 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", dreg
, dreg
, AT
);
8885 offset_expr
.X_add_number
= SEXT_16BIT (expr1
.X_add_number
);
8890 /* This is needed because this instruction uses $gp, but
8891 the first instruction on the main stream does not. */
8892 macro_build (NULL
, "nop", "");
8895 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
8896 local_reloc_type
, mips_gp_register
);
8897 if (expr1
.X_add_number
>= -0x8000
8898 && expr1
.X_add_number
< 0x8000)
8901 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
8902 tempreg
, tempreg
, BFD_RELOC_LO16
);
8903 /* FIXME: If add_number is 0, and there was no base
8904 register, the external symbol case ended with a load,
8905 so if the symbol turns out to not be external, and
8906 the next instruction uses tempreg, an unnecessary nop
8907 will be inserted. */
8913 /* We must add in the base register now, as in the
8914 external symbol case. */
8915 gas_assert (tempreg
== AT
);
8917 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
8920 /* We set breg to 0 because we have arranged to add
8921 it in in both cases. */
8925 macro_build_lui (&expr1
, AT
);
8926 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
8927 AT
, AT
, BFD_RELOC_LO16
);
8928 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
8929 tempreg
, tempreg
, AT
);
8934 else if (mips_big_got
&& HAVE_NEWABI
)
8936 int lui_reloc_type
= (int) BFD_RELOC_MIPS_GOT_HI16
;
8937 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT_LO16
;
8938 int add_breg_early
= 0;
8940 /* This is the large GOT case. If this is a reference to an
8941 external symbol, and there is no constant, we want
8942 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
8943 add $tempreg,$tempreg,$gp
8944 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
8945 or for lca or if tempreg is PIC_CALL_REG
8946 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
8947 add $tempreg,$tempreg,$gp
8948 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
8950 If we have a small constant, and this is a reference to
8951 an external symbol, we want
8952 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
8953 add $tempreg,$tempreg,$gp
8954 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
8955 addi $tempreg,$tempreg,<constant>
8957 If we have a large constant, and this is a reference to
8958 an external symbol, we want
8959 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
8960 addu $tempreg,$tempreg,$gp
8961 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
8962 lui $at,<hiconstant>
8963 addi $at,$at,<loconstant>
8964 add $tempreg,$tempreg,$at
8966 If we have NewABI, and we know it's a local symbol, we want
8967 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
8968 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
8969 otherwise we have to resort to GOT_HI16/GOT_LO16. */
8971 relax_start (offset_expr
.X_add_symbol
);
8973 expr1
.X_add_number
= offset_expr
.X_add_number
;
8974 offset_expr
.X_add_number
= 0;
8976 if (expr1
.X_add_number
== 0 && breg
== 0
8977 && (call
|| tempreg
== PIC_CALL_REG
))
8979 lui_reloc_type
= (int) BFD_RELOC_MIPS_CALL_HI16
;
8980 lw_reloc_type
= (int) BFD_RELOC_MIPS_CALL_LO16
;
8982 macro_build (&offset_expr
, "lui", LUI_FMT
, tempreg
, lui_reloc_type
);
8983 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
8984 tempreg
, tempreg
, mips_gp_register
);
8985 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
8986 tempreg
, lw_reloc_type
, tempreg
);
8988 if (expr1
.X_add_number
== 0)
8990 else if (expr1
.X_add_number
>= -0x8000
8991 && expr1
.X_add_number
< 0x8000)
8993 macro_build (&expr1
, ADDRESS_ADDI_INSN
, "t,r,j",
8994 tempreg
, tempreg
, BFD_RELOC_LO16
);
8996 else if (IS_SEXT_32BIT_NUM (expr1
.X_add_number
+ 0x8000))
8998 /* If we are going to add in a base register, and the
8999 target register and the base register are the same,
9000 then we are using AT as a temporary register. Since
9001 we want to load the constant into AT, we add our
9002 current AT (from the global offset table) and the
9003 register into the register now, and pretend we were
9004 not using a base register. */
9009 gas_assert (tempreg
== AT
);
9010 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
9016 load_register (AT
, &expr1
, HAVE_64BIT_ADDRESSES
);
9017 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", dreg
, dreg
, AT
);
9022 as_bad (_("PIC code offset overflow (max 32 signed bits)"));
9025 offset_expr
.X_add_number
= expr1
.X_add_number
;
9026 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
9027 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
9028 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j", tempreg
,
9029 tempreg
, BFD_RELOC_MIPS_GOT_OFST
);
9032 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
9033 treg
, tempreg
, breg
);
9043 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", treg
, tempreg
, breg
);
9047 gas_assert (!mips_opts
.micromips
);
9048 macro_build (NULL
, "c2", "C", (treg
<< 16) | 0x01);
9052 gas_assert (!mips_opts
.micromips
);
9053 macro_build (NULL
, "c2", "C", 0x02);
9057 gas_assert (!mips_opts
.micromips
);
9058 macro_build (NULL
, "c2", "C", (treg
<< 16) | 0x02);
9062 gas_assert (!mips_opts
.micromips
);
9063 macro_build (NULL
, "c2", "C", 3);
9067 gas_assert (!mips_opts
.micromips
);
9068 macro_build (NULL
, "c2", "C", (treg
<< 16) | 0x03);
9072 /* The j instruction may not be used in PIC code, since it
9073 requires an absolute address. We convert it to a b
9075 if (mips_pic
== NO_PIC
)
9076 macro_build (&offset_expr
, "j", "a");
9078 macro_build (&offset_expr
, "b", "p");
9081 /* The jal instructions must be handled as macros because when
9082 generating PIC code they expand to multi-instruction
9083 sequences. Normally they are simple instructions. */
9088 gas_assert (mips_opts
.micromips
);
9089 if (mips_opts
.insn32
)
9091 as_bad (_("Opcode not supported in the `insn32' mode `%s'"), str
);
9101 if (mips_pic
== NO_PIC
)
9103 s
= jals
? "jalrs" : "jalr";
9104 if (mips_opts
.micromips
9105 && !mips_opts
.insn32
9107 && !(history
[0].insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_32BIT
))
9108 macro_build (NULL
, s
, "mj", sreg
);
9110 macro_build (NULL
, s
, JALR_FMT
, dreg
, sreg
);
9114 int cprestore
= (mips_pic
== SVR4_PIC
&& !HAVE_NEWABI
9115 && mips_cprestore_offset
>= 0);
9117 if (sreg
!= PIC_CALL_REG
)
9118 as_warn (_("MIPS PIC call to register other than $25"));
9120 s
= ((mips_opts
.micromips
9121 && !mips_opts
.insn32
9122 && (!mips_opts
.noreorder
|| cprestore
))
9123 ? "jalrs" : "jalr");
9124 if (mips_opts
.micromips
9125 && !mips_opts
.insn32
9127 && !(history
[0].insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_32BIT
))
9128 macro_build (NULL
, s
, "mj", sreg
);
9130 macro_build (NULL
, s
, JALR_FMT
, dreg
, sreg
);
9131 if (mips_pic
== SVR4_PIC
&& !HAVE_NEWABI
)
9133 if (mips_cprestore_offset
< 0)
9134 as_warn (_("No .cprestore pseudo-op used in PIC code"));
9137 if (!mips_frame_reg_valid
)
9139 as_warn (_("No .frame pseudo-op used in PIC code"));
9140 /* Quiet this warning. */
9141 mips_frame_reg_valid
= 1;
9143 if (!mips_cprestore_valid
)
9145 as_warn (_("No .cprestore pseudo-op used in PIC code"));
9146 /* Quiet this warning. */
9147 mips_cprestore_valid
= 1;
9149 if (mips_opts
.noreorder
)
9150 macro_build (NULL
, "nop", "");
9151 expr1
.X_add_number
= mips_cprestore_offset
;
9152 macro_build_ldst_constoffset (&expr1
, ADDRESS_LOAD_INSN
,
9155 HAVE_64BIT_ADDRESSES
);
9163 gas_assert (mips_opts
.micromips
);
9164 if (mips_opts
.insn32
)
9166 as_bad (_("Opcode not supported in the `insn32' mode `%s'"), str
);
9172 if (mips_pic
== NO_PIC
)
9173 macro_build (&offset_expr
, jals
? "jals" : "jal", "a");
9174 else if (mips_pic
== SVR4_PIC
)
9176 /* If this is a reference to an external symbol, and we are
9177 using a small GOT, we want
9178 lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
9182 lw $gp,cprestore($sp)
9183 The cprestore value is set using the .cprestore
9184 pseudo-op. If we are using a big GOT, we want
9185 lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16)
9187 lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16)
9191 lw $gp,cprestore($sp)
9192 If the symbol is not external, we want
9193 lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
9195 addiu $25,$25,<sym> (BFD_RELOC_LO16)
9198 lw $gp,cprestore($sp)
9200 For NewABI, we use the same CALL16 or CALL_HI16/CALL_LO16
9201 sequences above, minus nops, unless the symbol is local,
9202 which enables us to use GOT_PAGE/GOT_OFST (big got) or
9208 relax_start (offset_expr
.X_add_symbol
);
9209 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
9210 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL16
,
9213 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
9214 PIC_CALL_REG
, BFD_RELOC_MIPS_GOT_DISP
,
9220 relax_start (offset_expr
.X_add_symbol
);
9221 macro_build (&offset_expr
, "lui", LUI_FMT
, PIC_CALL_REG
,
9222 BFD_RELOC_MIPS_CALL_HI16
);
9223 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", PIC_CALL_REG
,
9224 PIC_CALL_REG
, mips_gp_register
);
9225 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
9226 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL_LO16
,
9229 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
9230 PIC_CALL_REG
, BFD_RELOC_MIPS_GOT_PAGE
,
9232 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
9233 PIC_CALL_REG
, PIC_CALL_REG
,
9234 BFD_RELOC_MIPS_GOT_OFST
);
9238 macro_build_jalr (&offset_expr
, 0);
9242 relax_start (offset_expr
.X_add_symbol
);
9245 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
9246 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL16
,
9255 gpdelay
= reg_needs_delay (mips_gp_register
);
9256 macro_build (&offset_expr
, "lui", LUI_FMT
, PIC_CALL_REG
,
9257 BFD_RELOC_MIPS_CALL_HI16
);
9258 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", PIC_CALL_REG
,
9259 PIC_CALL_REG
, mips_gp_register
);
9260 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
9261 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL_LO16
,
9266 macro_build (NULL
, "nop", "");
9268 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
9269 PIC_CALL_REG
, BFD_RELOC_MIPS_GOT16
,
9272 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
9273 PIC_CALL_REG
, PIC_CALL_REG
, BFD_RELOC_LO16
);
9275 macro_build_jalr (&offset_expr
, mips_cprestore_offset
>= 0);
9277 if (mips_cprestore_offset
< 0)
9278 as_warn (_("No .cprestore pseudo-op used in PIC code"));
9281 if (!mips_frame_reg_valid
)
9283 as_warn (_("No .frame pseudo-op used in PIC code"));
9284 /* Quiet this warning. */
9285 mips_frame_reg_valid
= 1;
9287 if (!mips_cprestore_valid
)
9289 as_warn (_("No .cprestore pseudo-op used in PIC code"));
9290 /* Quiet this warning. */
9291 mips_cprestore_valid
= 1;
9293 if (mips_opts
.noreorder
)
9294 macro_build (NULL
, "nop", "");
9295 expr1
.X_add_number
= mips_cprestore_offset
;
9296 macro_build_ldst_constoffset (&expr1
, ADDRESS_LOAD_INSN
,
9299 HAVE_64BIT_ADDRESSES
);
9303 else if (mips_pic
== VXWORKS_PIC
)
9304 as_bad (_("Non-PIC jump used in PIC library"));
9382 treg
= EXTRACT_OPERAND (mips_opts
.micromips
, 3BITPOS
, *ip
);
9388 treg
= EXTRACT_OPERAND (mips_opts
.micromips
, 3BITPOS
, *ip
);
9413 gas_assert (!mips_opts
.micromips
);
9416 /* Itbl support may require additional care here. */
9422 /* Itbl support may require additional care here. */
9428 offbits
= (mips_opts
.micromips
? 12 : 16);
9429 /* Itbl support may require additional care here. */
9433 gas_assert (!mips_opts
.micromips
);
9436 /* Itbl support may require additional care here. */
9442 offbits
= (mips_opts
.micromips
? 12 : 16);
9447 offbits
= (mips_opts
.micromips
? 12 : 16);
9452 /* Itbl support may require additional care here. */
9458 offbits
= (mips_opts
.micromips
? 12 : 16);
9459 /* Itbl support may require additional care here. */
9465 /* Itbl support may require additional care here. */
9471 /* Itbl support may require additional care here. */
9477 offbits
= (mips_opts
.micromips
? 12 : 16);
9482 offbits
= (mips_opts
.micromips
? 12 : 16);
9487 offbits
= (mips_opts
.micromips
? 12 : 16);
9492 offbits
= (mips_opts
.micromips
? 12 : 16);
9497 offbits
= (mips_opts
.micromips
? 12 : 16);
9500 gas_assert (mips_opts
.micromips
);
9507 gas_assert (mips_opts
.micromips
);
9514 gas_assert (mips_opts
.micromips
);
9520 gas_assert (mips_opts
.micromips
);
9527 /* We don't want to use $0 as tempreg. */
9528 if (breg
== treg
+ lp
|| treg
+ lp
== ZERO
)
9531 tempreg
= treg
+ lp
;
9547 gas_assert (!mips_opts
.micromips
);
9550 /* Itbl support may require additional care here. */
9556 /* Itbl support may require additional care here. */
9562 offbits
= (mips_opts
.micromips
? 12 : 16);
9563 /* Itbl support may require additional care here. */
9567 gas_assert (!mips_opts
.micromips
);
9570 /* Itbl support may require additional care here. */
9576 offbits
= (mips_opts
.micromips
? 12 : 16);
9581 offbits
= (mips_opts
.micromips
? 12 : 16);
9586 offbits
= (mips_opts
.micromips
? 12 : 16);
9591 offbits
= (mips_opts
.micromips
? 12 : 16);
9595 fmt
= mips_opts
.micromips
? "k,~(b)" : "k,o(b)";
9596 offbits
= (mips_opts
.micromips
? 12 : 16);
9605 fmt
= !mips_opts
.micromips
? "k,o(b)" : "k,~(b)";
9606 offbits
= (mips_opts
.micromips
? 12 : 16);
9617 /* Itbl support may require additional care here. */
9622 offbits
= (mips_opts
.micromips
? 12 : 16);
9623 /* Itbl support may require additional care here. */
9629 /* Itbl support may require additional care here. */
9633 gas_assert (!mips_opts
.micromips
);
9636 /* Itbl support may require additional care here. */
9642 offbits
= (mips_opts
.micromips
? 12 : 16);
9647 offbits
= (mips_opts
.micromips
? 12 : 16);
9650 gas_assert (mips_opts
.micromips
);
9656 gas_assert (mips_opts
.micromips
);
9662 gas_assert (mips_opts
.micromips
);
9668 gas_assert (mips_opts
.micromips
);
9676 if (small_offset_p (0, align
, 16))
9678 /* The first case exists for M_LD_AB and M_SD_AB, which are
9679 macros for o32 but which should act like normal instructions
9682 macro_build (&offset_expr
, s
, fmt
, treg
, -1, offset_reloc
[0],
9683 offset_reloc
[1], offset_reloc
[2], breg
);
9684 else if (small_offset_p (0, align
, offbits
))
9687 macro_build (NULL
, s
, fmt
, treg
, breg
);
9689 macro_build (NULL
, s
, fmt
, treg
,
9690 (int) offset_expr
.X_add_number
, breg
);
9696 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
9697 tempreg
, breg
, -1, offset_reloc
[0],
9698 offset_reloc
[1], offset_reloc
[2]);
9700 macro_build (NULL
, s
, fmt
, treg
, tempreg
);
9702 macro_build (NULL
, s
, fmt
, treg
, 0, tempreg
);
9710 if (offset_expr
.X_op
!= O_constant
9711 && offset_expr
.X_op
!= O_symbol
)
9713 as_bad (_("Expression too complex"));
9714 offset_expr
.X_op
= O_constant
;
9717 if (HAVE_32BIT_ADDRESSES
9718 && !IS_SEXT_32BIT_NUM (offset_expr
.X_add_number
))
9722 sprintf_vma (value
, offset_expr
.X_add_number
);
9723 as_bad (_("Number (0x%s) larger than 32 bits"), value
);
9726 /* A constant expression in PIC code can be handled just as it
9727 is in non PIC code. */
9728 if (offset_expr
.X_op
== O_constant
)
9730 expr1
.X_add_number
= offset_high_part (offset_expr
.X_add_number
,
9731 offbits
== 0 ? 16 : offbits
);
9732 offset_expr
.X_add_number
-= expr1
.X_add_number
;
9734 load_register (tempreg
, &expr1
, HAVE_64BIT_ADDRESSES
);
9736 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
9737 tempreg
, tempreg
, breg
);
9740 if (offset_expr
.X_add_number
!= 0)
9741 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
,
9742 "t,r,j", tempreg
, tempreg
, BFD_RELOC_LO16
);
9743 macro_build (NULL
, s
, fmt
, treg
, tempreg
);
9745 else if (offbits
== 16)
9746 macro_build (&offset_expr
, s
, fmt
, treg
, BFD_RELOC_LO16
, tempreg
);
9748 macro_build (NULL
, s
, fmt
, treg
,
9749 (int) offset_expr
.X_add_number
, tempreg
);
9751 else if (offbits
!= 16)
9753 /* The offset field is too narrow to be used for a low-part
9754 relocation, so load the whole address into the auxillary
9756 load_address (tempreg
, &offset_expr
, &used_at
);
9758 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
9759 tempreg
, tempreg
, breg
);
9761 macro_build (NULL
, s
, fmt
, treg
, tempreg
);
9763 macro_build (NULL
, s
, fmt
, treg
, 0, tempreg
);
9765 else if (mips_pic
== NO_PIC
)
9767 /* If this is a reference to a GP relative symbol, and there
9768 is no base register, we want
9769 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
9770 Otherwise, if there is no base register, we want
9771 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
9772 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
9773 If we have a constant, we need two instructions anyhow,
9774 so we always use the latter form.
9776 If we have a base register, and this is a reference to a
9777 GP relative symbol, we want
9778 addu $tempreg,$breg,$gp
9779 <op> $treg,<sym>($tempreg) (BFD_RELOC_GPREL16)
9781 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
9782 addu $tempreg,$tempreg,$breg
9783 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
9784 With a constant we always use the latter case.
9786 With 64bit address space and no base register and $at usable,
9788 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
9789 lui $at,<sym> (BFD_RELOC_HI16_S)
9790 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
9793 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
9794 If we have a base register, we want
9795 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
9796 lui $at,<sym> (BFD_RELOC_HI16_S)
9797 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
9801 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
9803 Without $at we can't generate the optimal path for superscalar
9804 processors here since this would require two temporary registers.
9805 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
9806 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
9808 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
9810 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
9811 If we have a base register, we want
9812 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
9813 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
9815 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
9817 daddu $tempreg,$tempreg,$breg
9818 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
9820 For GP relative symbols in 64bit address space we can use
9821 the same sequence as in 32bit address space. */
9822 if (HAVE_64BIT_SYMBOLS
)
9824 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
9825 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
9827 relax_start (offset_expr
.X_add_symbol
);
9830 macro_build (&offset_expr
, s
, fmt
, treg
,
9831 BFD_RELOC_GPREL16
, mips_gp_register
);
9835 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
9836 tempreg
, breg
, mips_gp_register
);
9837 macro_build (&offset_expr
, s
, fmt
, treg
,
9838 BFD_RELOC_GPREL16
, tempreg
);
9843 if (used_at
== 0 && mips_opts
.at
)
9845 macro_build (&offset_expr
, "lui", LUI_FMT
, tempreg
,
9846 BFD_RELOC_MIPS_HIGHEST
);
9847 macro_build (&offset_expr
, "lui", LUI_FMT
, AT
,
9849 macro_build (&offset_expr
, "daddiu", "t,r,j", tempreg
,
9850 tempreg
, BFD_RELOC_MIPS_HIGHER
);
9852 macro_build (NULL
, "daddu", "d,v,t", AT
, AT
, breg
);
9853 macro_build (NULL
, "dsll32", SHFT_FMT
, tempreg
, tempreg
, 0);
9854 macro_build (NULL
, "daddu", "d,v,t", tempreg
, tempreg
, AT
);
9855 macro_build (&offset_expr
, s
, fmt
, treg
, BFD_RELOC_LO16
,
9861 macro_build (&offset_expr
, "lui", LUI_FMT
, tempreg
,
9862 BFD_RELOC_MIPS_HIGHEST
);
9863 macro_build (&offset_expr
, "daddiu", "t,r,j", tempreg
,
9864 tempreg
, BFD_RELOC_MIPS_HIGHER
);
9865 macro_build (NULL
, "dsll", SHFT_FMT
, tempreg
, tempreg
, 16);
9866 macro_build (&offset_expr
, "daddiu", "t,r,j", tempreg
,
9867 tempreg
, BFD_RELOC_HI16_S
);
9868 macro_build (NULL
, "dsll", SHFT_FMT
, tempreg
, tempreg
, 16);
9870 macro_build (NULL
, "daddu", "d,v,t",
9871 tempreg
, tempreg
, breg
);
9872 macro_build (&offset_expr
, s
, fmt
, treg
,
9873 BFD_RELOC_LO16
, tempreg
);
9876 if (mips_relax
.sequence
)
9883 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
9884 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
9886 relax_start (offset_expr
.X_add_symbol
);
9887 macro_build (&offset_expr
, s
, fmt
, treg
, BFD_RELOC_GPREL16
,
9891 macro_build_lui (&offset_expr
, tempreg
);
9892 macro_build (&offset_expr
, s
, fmt
, treg
,
9893 BFD_RELOC_LO16
, tempreg
);
9894 if (mips_relax
.sequence
)
9899 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
9900 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
9902 relax_start (offset_expr
.X_add_symbol
);
9903 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
9904 tempreg
, breg
, mips_gp_register
);
9905 macro_build (&offset_expr
, s
, fmt
, treg
,
9906 BFD_RELOC_GPREL16
, tempreg
);
9909 macro_build_lui (&offset_expr
, tempreg
);
9910 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
9911 tempreg
, tempreg
, breg
);
9912 macro_build (&offset_expr
, s
, fmt
, treg
,
9913 BFD_RELOC_LO16
, tempreg
);
9914 if (mips_relax
.sequence
)
9918 else if (!mips_big_got
)
9920 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT16
;
9922 /* If this is a reference to an external symbol, we want
9923 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
9925 <op> $treg,0($tempreg)
9927 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
9929 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
9930 <op> $treg,0($tempreg)
9933 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
9934 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST)
9936 If there is a base register, we add it to $tempreg before
9937 the <op>. If there is a constant, we stick it in the
9938 <op> instruction. We don't handle constants larger than
9939 16 bits, because we have no way to load the upper 16 bits
9940 (actually, we could handle them for the subset of cases
9941 in which we are not using $at). */
9942 gas_assert (offset_expr
.X_op
== O_symbol
);
9945 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
9946 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
9948 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
9949 tempreg
, tempreg
, breg
);
9950 macro_build (&offset_expr
, s
, fmt
, treg
,
9951 BFD_RELOC_MIPS_GOT_OFST
, tempreg
);
9954 expr1
.X_add_number
= offset_expr
.X_add_number
;
9955 offset_expr
.X_add_number
= 0;
9956 if (expr1
.X_add_number
< -0x8000
9957 || expr1
.X_add_number
>= 0x8000)
9958 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
9959 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
9960 lw_reloc_type
, mips_gp_register
);
9962 relax_start (offset_expr
.X_add_symbol
);
9964 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j", tempreg
,
9965 tempreg
, BFD_RELOC_LO16
);
9968 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
9969 tempreg
, tempreg
, breg
);
9970 macro_build (&expr1
, s
, fmt
, treg
, BFD_RELOC_LO16
, tempreg
);
9972 else if (mips_big_got
&& !HAVE_NEWABI
)
9976 /* If this is a reference to an external symbol, we want
9977 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
9978 addu $tempreg,$tempreg,$gp
9979 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
9980 <op> $treg,0($tempreg)
9982 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
9984 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
9985 <op> $treg,0($tempreg)
9986 If there is a base register, we add it to $tempreg before
9987 the <op>. If there is a constant, we stick it in the
9988 <op> instruction. We don't handle constants larger than
9989 16 bits, because we have no way to load the upper 16 bits
9990 (actually, we could handle them for the subset of cases
9991 in which we are not using $at). */
9992 gas_assert (offset_expr
.X_op
== O_symbol
);
9993 expr1
.X_add_number
= offset_expr
.X_add_number
;
9994 offset_expr
.X_add_number
= 0;
9995 if (expr1
.X_add_number
< -0x8000
9996 || expr1
.X_add_number
>= 0x8000)
9997 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
9998 gpdelay
= reg_needs_delay (mips_gp_register
);
9999 relax_start (offset_expr
.X_add_symbol
);
10000 macro_build (&offset_expr
, "lui", LUI_FMT
, tempreg
,
10001 BFD_RELOC_MIPS_GOT_HI16
);
10002 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", tempreg
, tempreg
,
10004 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
10005 BFD_RELOC_MIPS_GOT_LO16
, tempreg
);
10008 macro_build (NULL
, "nop", "");
10009 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
10010 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
10012 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j", tempreg
,
10013 tempreg
, BFD_RELOC_LO16
);
10017 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
10018 tempreg
, tempreg
, breg
);
10019 macro_build (&expr1
, s
, fmt
, treg
, BFD_RELOC_LO16
, tempreg
);
10021 else if (mips_big_got
&& HAVE_NEWABI
)
10023 /* If this is a reference to an external symbol, we want
10024 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
10025 add $tempreg,$tempreg,$gp
10026 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
10027 <op> $treg,<ofst>($tempreg)
10028 Otherwise, for local symbols, we want:
10029 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
10030 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST) */
10031 gas_assert (offset_expr
.X_op
== O_symbol
);
10032 expr1
.X_add_number
= offset_expr
.X_add_number
;
10033 offset_expr
.X_add_number
= 0;
10034 if (expr1
.X_add_number
< -0x8000
10035 || expr1
.X_add_number
>= 0x8000)
10036 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
10037 relax_start (offset_expr
.X_add_symbol
);
10038 macro_build (&offset_expr
, "lui", LUI_FMT
, tempreg
,
10039 BFD_RELOC_MIPS_GOT_HI16
);
10040 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", tempreg
, tempreg
,
10042 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
10043 BFD_RELOC_MIPS_GOT_LO16
, tempreg
);
10045 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
10046 tempreg
, tempreg
, breg
);
10047 macro_build (&expr1
, s
, fmt
, treg
, BFD_RELOC_LO16
, tempreg
);
10050 offset_expr
.X_add_number
= expr1
.X_add_number
;
10051 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
10052 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
10054 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
10055 tempreg
, tempreg
, breg
);
10056 macro_build (&offset_expr
, s
, fmt
, treg
,
10057 BFD_RELOC_MIPS_GOT_OFST
, tempreg
);
10066 gas_assert (mips_opts
.micromips
);
10067 gas_assert (mips_opts
.insn32
);
10068 start_noreorder ();
10069 macro_build (NULL
, "jr", "s", RA
);
10070 expr1
.X_add_number
= EXTRACT_OPERAND (1, IMMP
, *ip
) << 2;
10071 macro_build (&expr1
, "addiu", "t,r,j", SP
, SP
, BFD_RELOC_LO16
);
10076 gas_assert (mips_opts
.micromips
);
10077 gas_assert (mips_opts
.insn32
);
10078 macro_build (NULL
, "jr", "s", sreg
);
10079 if (mips_opts
.noreorder
)
10080 macro_build (NULL
, "nop", "");
10085 load_register (treg
, &imm_expr
, 0);
10089 load_register (treg
, &imm_expr
, 1);
10093 if (imm_expr
.X_op
== O_constant
)
10096 load_register (AT
, &imm_expr
, 0);
10097 macro_build (NULL
, "mtc1", "t,G", AT
, treg
);
10102 gas_assert (offset_expr
.X_op
== O_symbol
10103 && strcmp (segment_name (S_GET_SEGMENT
10104 (offset_expr
.X_add_symbol
)),
10106 && offset_expr
.X_add_number
== 0);
10107 macro_build (&offset_expr
, "lwc1", "T,o(b)", treg
,
10108 BFD_RELOC_MIPS_LITERAL
, mips_gp_register
);
10113 /* Check if we have a constant in IMM_EXPR. If the GPRs are 64 bits
10114 wide, IMM_EXPR is the entire value. Otherwise IMM_EXPR is the high
10115 order 32 bits of the value and the low order 32 bits are either
10116 zero or in OFFSET_EXPR. */
10117 if (imm_expr
.X_op
== O_constant
|| imm_expr
.X_op
== O_big
)
10119 if (HAVE_64BIT_GPRS
)
10120 load_register (treg
, &imm_expr
, 1);
10125 if (target_big_endian
)
10137 load_register (hreg
, &imm_expr
, 0);
10140 if (offset_expr
.X_op
== O_absent
)
10141 move_register (lreg
, 0);
10144 gas_assert (offset_expr
.X_op
== O_constant
);
10145 load_register (lreg
, &offset_expr
, 0);
10152 /* We know that sym is in the .rdata section. First we get the
10153 upper 16 bits of the address. */
10154 if (mips_pic
== NO_PIC
)
10156 macro_build_lui (&offset_expr
, AT
);
10161 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", AT
,
10162 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
10166 /* Now we load the register(s). */
10167 if (HAVE_64BIT_GPRS
)
10170 macro_build (&offset_expr
, "ld", "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
10175 macro_build (&offset_expr
, "lw", "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
10178 /* FIXME: How in the world do we deal with the possible
10180 offset_expr
.X_add_number
+= 4;
10181 macro_build (&offset_expr
, "lw", "t,o(b)",
10182 treg
+ 1, BFD_RELOC_LO16
, AT
);
10188 /* Check if we have a constant in IMM_EXPR. If the FPRs are 64 bits
10189 wide, IMM_EXPR is the entire value and the GPRs are known to be 64
10190 bits wide as well. Otherwise IMM_EXPR is the high order 32 bits of
10191 the value and the low order 32 bits are either zero or in
10193 if (imm_expr
.X_op
== O_constant
|| imm_expr
.X_op
== O_big
)
10196 load_register (AT
, &imm_expr
, HAVE_64BIT_FPRS
);
10197 if (HAVE_64BIT_FPRS
)
10199 gas_assert (HAVE_64BIT_GPRS
);
10200 macro_build (NULL
, "dmtc1", "t,S", AT
, treg
);
10204 macro_build (NULL
, "mtc1", "t,G", AT
, treg
+ 1);
10205 if (offset_expr
.X_op
== O_absent
)
10206 macro_build (NULL
, "mtc1", "t,G", 0, treg
);
10209 gas_assert (offset_expr
.X_op
== O_constant
);
10210 load_register (AT
, &offset_expr
, 0);
10211 macro_build (NULL
, "mtc1", "t,G", AT
, treg
);
10217 gas_assert (offset_expr
.X_op
== O_symbol
10218 && offset_expr
.X_add_number
== 0);
10219 s
= segment_name (S_GET_SEGMENT (offset_expr
.X_add_symbol
));
10220 if (strcmp (s
, ".lit8") == 0)
10222 breg
= mips_gp_register
;
10223 offset_reloc
[0] = BFD_RELOC_MIPS_LITERAL
;
10224 offset_reloc
[1] = BFD_RELOC_UNUSED
;
10225 offset_reloc
[2] = BFD_RELOC_UNUSED
;
10229 gas_assert (strcmp (s
, RDATA_SECTION_NAME
) == 0);
10231 if (mips_pic
!= NO_PIC
)
10232 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", AT
,
10233 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
10236 /* FIXME: This won't work for a 64 bit address. */
10237 macro_build_lui (&offset_expr
, AT
);
10241 offset_reloc
[0] = BFD_RELOC_LO16
;
10242 offset_reloc
[1] = BFD_RELOC_UNUSED
;
10243 offset_reloc
[2] = BFD_RELOC_UNUSED
;
10250 * The MIPS assembler seems to check for X_add_number not
10251 * being double aligned and generating:
10252 * lui at,%hi(foo+1)
10254 * addiu at,at,%lo(foo+1)
10257 * But, the resulting address is the same after relocation so why
10258 * generate the extra instruction?
10260 /* Itbl support may require additional care here. */
10263 if (CPU_HAS_LDC1_SDC1 (mips_opts
.arch
))
10272 gas_assert (!mips_opts
.micromips
);
10273 /* Itbl support may require additional care here. */
10276 if (CPU_HAS_LDC1_SDC1 (mips_opts
.arch
))
10296 if (HAVE_64BIT_GPRS
)
10306 if (HAVE_64BIT_GPRS
)
10314 /* Even on a big endian machine $fn comes before $fn+1. We have
10315 to adjust when loading from memory. We set coproc if we must
10316 load $fn+1 first. */
10317 /* Itbl support may require additional care here. */
10318 if (!target_big_endian
)
10321 if (small_offset_p (0, align
, 16))
10324 if (!small_offset_p (4, align
, 16))
10326 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j", AT
, breg
,
10327 -1, offset_reloc
[0], offset_reloc
[1],
10329 expr1
.X_add_number
= 0;
10333 offset_reloc
[0] = BFD_RELOC_LO16
;
10334 offset_reloc
[1] = BFD_RELOC_UNUSED
;
10335 offset_reloc
[2] = BFD_RELOC_UNUSED
;
10337 if (strcmp (s
, "lw") == 0 && treg
== breg
)
10339 ep
->X_add_number
+= 4;
10340 macro_build (ep
, s
, fmt
, treg
+ 1, -1, offset_reloc
[0],
10341 offset_reloc
[1], offset_reloc
[2], breg
);
10342 ep
->X_add_number
-= 4;
10343 macro_build (ep
, s
, fmt
, treg
, -1, offset_reloc
[0],
10344 offset_reloc
[1], offset_reloc
[2], breg
);
10348 macro_build (ep
, s
, fmt
, coproc
? treg
+ 1 : treg
, -1,
10349 offset_reloc
[0], offset_reloc
[1], offset_reloc
[2],
10351 ep
->X_add_number
+= 4;
10352 macro_build (ep
, s
, fmt
, coproc
? treg
: treg
+ 1, -1,
10353 offset_reloc
[0], offset_reloc
[1], offset_reloc
[2],
10359 if (offset_expr
.X_op
!= O_symbol
10360 && offset_expr
.X_op
!= O_constant
)
10362 as_bad (_("Expression too complex"));
10363 offset_expr
.X_op
= O_constant
;
10366 if (HAVE_32BIT_ADDRESSES
10367 && !IS_SEXT_32BIT_NUM (offset_expr
.X_add_number
))
10371 sprintf_vma (value
, offset_expr
.X_add_number
);
10372 as_bad (_("Number (0x%s) larger than 32 bits"), value
);
10375 if (mips_pic
== NO_PIC
|| offset_expr
.X_op
== O_constant
)
10377 /* If this is a reference to a GP relative symbol, we want
10378 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
10379 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_GPREL16)
10380 If we have a base register, we use this
10382 <op> $treg,<sym>($at) (BFD_RELOC_GPREL16)
10383 <op> $treg+1,<sym>+4($at) (BFD_RELOC_GPREL16)
10384 If this is not a GP relative symbol, we want
10385 lui $at,<sym> (BFD_RELOC_HI16_S)
10386 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
10387 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
10388 If there is a base register, we add it to $at after the
10389 lui instruction. If there is a constant, we always use
10391 if (offset_expr
.X_op
== O_symbol
10392 && (valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
10393 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
10395 relax_start (offset_expr
.X_add_symbol
);
10398 tempreg
= mips_gp_register
;
10402 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
10403 AT
, breg
, mips_gp_register
);
10408 /* Itbl support may require additional care here. */
10409 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
+ 1 : treg
,
10410 BFD_RELOC_GPREL16
, tempreg
);
10411 offset_expr
.X_add_number
+= 4;
10413 /* Set mips_optimize to 2 to avoid inserting an
10415 hold_mips_optimize
= mips_optimize
;
10417 /* Itbl support may require additional care here. */
10418 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
: treg
+ 1,
10419 BFD_RELOC_GPREL16
, tempreg
);
10420 mips_optimize
= hold_mips_optimize
;
10424 offset_expr
.X_add_number
-= 4;
10427 if (offset_high_part (offset_expr
.X_add_number
, 16)
10428 != offset_high_part (offset_expr
.X_add_number
+ 4, 16))
10430 load_address (AT
, &offset_expr
, &used_at
);
10431 offset_expr
.X_op
= O_constant
;
10432 offset_expr
.X_add_number
= 0;
10435 macro_build_lui (&offset_expr
, AT
);
10437 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
10438 /* Itbl support may require additional care here. */
10439 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
+ 1 : treg
,
10440 BFD_RELOC_LO16
, AT
);
10441 /* FIXME: How do we handle overflow here? */
10442 offset_expr
.X_add_number
+= 4;
10443 /* Itbl support may require additional care here. */
10444 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
: treg
+ 1,
10445 BFD_RELOC_LO16
, AT
);
10446 if (mips_relax
.sequence
)
10449 else if (!mips_big_got
)
10451 /* If this is a reference to an external symbol, we want
10452 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
10455 <op> $treg+1,4($at)
10457 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
10459 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
10460 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
10461 If there is a base register we add it to $at before the
10462 lwc1 instructions. If there is a constant we include it
10463 in the lwc1 instructions. */
10465 expr1
.X_add_number
= offset_expr
.X_add_number
;
10466 if (expr1
.X_add_number
< -0x8000
10467 || expr1
.X_add_number
>= 0x8000 - 4)
10468 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
10469 load_got_offset (AT
, &offset_expr
);
10472 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
10474 /* Set mips_optimize to 2 to avoid inserting an undesired
10476 hold_mips_optimize
= mips_optimize
;
10479 /* Itbl support may require additional care here. */
10480 relax_start (offset_expr
.X_add_symbol
);
10481 macro_build (&expr1
, s
, fmt
, coproc
? treg
+ 1 : treg
,
10482 BFD_RELOC_LO16
, AT
);
10483 expr1
.X_add_number
+= 4;
10484 macro_build (&expr1
, s
, fmt
, coproc
? treg
: treg
+ 1,
10485 BFD_RELOC_LO16
, AT
);
10487 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
+ 1 : treg
,
10488 BFD_RELOC_LO16
, AT
);
10489 offset_expr
.X_add_number
+= 4;
10490 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
: treg
+ 1,
10491 BFD_RELOC_LO16
, AT
);
10494 mips_optimize
= hold_mips_optimize
;
10496 else if (mips_big_got
)
10500 /* If this is a reference to an external symbol, we want
10501 lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16)
10503 lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16)
10506 <op> $treg+1,4($at)
10508 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
10510 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
10511 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
10512 If there is a base register we add it to $at before the
10513 lwc1 instructions. If there is a constant we include it
10514 in the lwc1 instructions. */
10516 expr1
.X_add_number
= offset_expr
.X_add_number
;
10517 offset_expr
.X_add_number
= 0;
10518 if (expr1
.X_add_number
< -0x8000
10519 || expr1
.X_add_number
>= 0x8000 - 4)
10520 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
10521 gpdelay
= reg_needs_delay (mips_gp_register
);
10522 relax_start (offset_expr
.X_add_symbol
);
10523 macro_build (&offset_expr
, "lui", LUI_FMT
,
10524 AT
, BFD_RELOC_MIPS_GOT_HI16
);
10525 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
10526 AT
, AT
, mips_gp_register
);
10527 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
10528 AT
, BFD_RELOC_MIPS_GOT_LO16
, AT
);
10531 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
10532 /* Itbl support may require additional care here. */
10533 macro_build (&expr1
, s
, fmt
, coproc
? treg
+ 1 : treg
,
10534 BFD_RELOC_LO16
, AT
);
10535 expr1
.X_add_number
+= 4;
10537 /* Set mips_optimize to 2 to avoid inserting an undesired
10539 hold_mips_optimize
= mips_optimize
;
10541 /* Itbl support may require additional care here. */
10542 macro_build (&expr1
, s
, fmt
, coproc
? treg
: treg
+ 1,
10543 BFD_RELOC_LO16
, AT
);
10544 mips_optimize
= hold_mips_optimize
;
10545 expr1
.X_add_number
-= 4;
10548 offset_expr
.X_add_number
= expr1
.X_add_number
;
10550 macro_build (NULL
, "nop", "");
10551 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", AT
,
10552 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
10555 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
10556 /* Itbl support may require additional care here. */
10557 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
+ 1 : treg
,
10558 BFD_RELOC_LO16
, AT
);
10559 offset_expr
.X_add_number
+= 4;
10561 /* Set mips_optimize to 2 to avoid inserting an undesired
10563 hold_mips_optimize
= mips_optimize
;
10565 /* Itbl support may require additional care here. */
10566 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
: treg
+ 1,
10567 BFD_RELOC_LO16
, AT
);
10568 mips_optimize
= hold_mips_optimize
;
10587 /* New code added to support COPZ instructions.
10588 This code builds table entries out of the macros in mip_opcodes.
10589 R4000 uses interlocks to handle coproc delays.
10590 Other chips (like the R3000) require nops to be inserted for delays.
10592 FIXME: Currently, we require that the user handle delays.
10593 In order to fill delay slots for non-interlocked chips,
10594 we must have a way to specify delays based on the coprocessor.
10595 Eg. 4 cycles if load coproc reg from memory, 1 if in cache, etc.
10596 What are the side-effects of the cop instruction?
10597 What cache support might we have and what are its effects?
10598 Both coprocessor & memory require delays. how long???
10599 What registers are read/set/modified?
10601 If an itbl is provided to interpret cop instructions,
10602 this knowledge can be encoded in the itbl spec. */
10616 gas_assert (!mips_opts
.micromips
);
10617 /* For now we just do C (same as Cz). The parameter will be
10618 stored in insn_opcode by mips_ip. */
10619 macro_build (NULL
, s
, "C", (int) ip
->insn_opcode
);
10623 move_register (dreg
, sreg
);
10627 gas_assert (mips_opts
.micromips
);
10628 gas_assert (mips_opts
.insn32
);
10629 dreg
= micromips_to_32_reg_h_map1
[EXTRACT_OPERAND (1, MH
, *ip
)];
10630 breg
= micromips_to_32_reg_h_map2
[EXTRACT_OPERAND (1, MH
, *ip
)];
10631 sreg
= micromips_to_32_reg_m_map
[EXTRACT_OPERAND (1, MM
, *ip
)];
10632 treg
= micromips_to_32_reg_n_map
[EXTRACT_OPERAND (1, MN
, *ip
)];
10633 move_register (dreg
, sreg
);
10634 move_register (breg
, treg
);
10640 if (mips_opts
.arch
== CPU_R5900
)
10642 macro_build (NULL
, dbl
? "dmultu" : "multu", "d,s,t", dreg
, sreg
, treg
);
10646 macro_build (NULL
, dbl
? "dmultu" : "multu", "s,t", sreg
, treg
);
10647 macro_build (NULL
, "mflo", MFHL_FMT
, dreg
);
10654 /* The MIPS assembler some times generates shifts and adds. I'm
10655 not trying to be that fancy. GCC should do this for us
10658 load_register (AT
, &imm_expr
, dbl
);
10659 macro_build (NULL
, dbl
? "dmult" : "mult", "s,t", sreg
, AT
);
10660 macro_build (NULL
, "mflo", MFHL_FMT
, dreg
);
10673 start_noreorder ();
10676 load_register (AT
, &imm_expr
, dbl
);
10677 macro_build (NULL
, dbl
? "dmult" : "mult", "s,t", sreg
, imm
? AT
: treg
);
10678 macro_build (NULL
, "mflo", MFHL_FMT
, dreg
);
10679 macro_build (NULL
, dbl
? "dsra32" : "sra", SHFT_FMT
, dreg
, dreg
, RA
);
10680 macro_build (NULL
, "mfhi", MFHL_FMT
, AT
);
10682 macro_build (NULL
, "tne", TRAP_FMT
, dreg
, AT
, 6);
10685 if (mips_opts
.micromips
)
10686 micromips_label_expr (&label_expr
);
10688 label_expr
.X_add_number
= 8;
10689 macro_build (&label_expr
, "beq", "s,t,p", dreg
, AT
);
10690 macro_build (NULL
, "nop", "");
10691 macro_build (NULL
, "break", BRK_FMT
, 6);
10692 if (mips_opts
.micromips
)
10693 micromips_add_label ();
10696 macro_build (NULL
, "mflo", MFHL_FMT
, dreg
);
10709 start_noreorder ();
10712 load_register (AT
, &imm_expr
, dbl
);
10713 macro_build (NULL
, dbl
? "dmultu" : "multu", "s,t",
10714 sreg
, imm
? AT
: treg
);
10715 macro_build (NULL
, "mfhi", MFHL_FMT
, AT
);
10716 macro_build (NULL
, "mflo", MFHL_FMT
, dreg
);
10718 macro_build (NULL
, "tne", TRAP_FMT
, AT
, ZERO
, 6);
10721 if (mips_opts
.micromips
)
10722 micromips_label_expr (&label_expr
);
10724 label_expr
.X_add_number
= 8;
10725 macro_build (&label_expr
, "beq", "s,t,p", AT
, ZERO
);
10726 macro_build (NULL
, "nop", "");
10727 macro_build (NULL
, "break", BRK_FMT
, 6);
10728 if (mips_opts
.micromips
)
10729 micromips_add_label ();
10735 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
10746 macro_build (NULL
, "dnegu", "d,w", tempreg
, treg
);
10747 macro_build (NULL
, "drorv", "d,t,s", dreg
, sreg
, tempreg
);
10751 macro_build (NULL
, "dsubu", "d,v,t", AT
, ZERO
, treg
);
10752 macro_build (NULL
, "dsrlv", "d,t,s", AT
, sreg
, AT
);
10753 macro_build (NULL
, "dsllv", "d,t,s", dreg
, sreg
, treg
);
10754 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
10758 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
10769 macro_build (NULL
, "negu", "d,w", tempreg
, treg
);
10770 macro_build (NULL
, "rorv", "d,t,s", dreg
, sreg
, tempreg
);
10774 macro_build (NULL
, "subu", "d,v,t", AT
, ZERO
, treg
);
10775 macro_build (NULL
, "srlv", "d,t,s", AT
, sreg
, AT
);
10776 macro_build (NULL
, "sllv", "d,t,s", dreg
, sreg
, treg
);
10777 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
10786 if (imm_expr
.X_op
!= O_constant
)
10787 as_bad (_("Improper rotate count"));
10788 rot
= imm_expr
.X_add_number
& 0x3f;
10789 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
10791 rot
= (64 - rot
) & 0x3f;
10793 macro_build (NULL
, "dror32", SHFT_FMT
, dreg
, sreg
, rot
- 32);
10795 macro_build (NULL
, "dror", SHFT_FMT
, dreg
, sreg
, rot
);
10800 macro_build (NULL
, "dsrl", SHFT_FMT
, dreg
, sreg
, 0);
10803 l
= (rot
< 0x20) ? "dsll" : "dsll32";
10804 rr
= ((0x40 - rot
) < 0x20) ? "dsrl" : "dsrl32";
10807 macro_build (NULL
, l
, SHFT_FMT
, AT
, sreg
, rot
);
10808 macro_build (NULL
, rr
, SHFT_FMT
, dreg
, sreg
, (0x20 - rot
) & 0x1f);
10809 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
10817 if (imm_expr
.X_op
!= O_constant
)
10818 as_bad (_("Improper rotate count"));
10819 rot
= imm_expr
.X_add_number
& 0x1f;
10820 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
10822 macro_build (NULL
, "ror", SHFT_FMT
, dreg
, sreg
, (32 - rot
) & 0x1f);
10827 macro_build (NULL
, "srl", SHFT_FMT
, dreg
, sreg
, 0);
10831 macro_build (NULL
, "sll", SHFT_FMT
, AT
, sreg
, rot
);
10832 macro_build (NULL
, "srl", SHFT_FMT
, dreg
, sreg
, (0x20 - rot
) & 0x1f);
10833 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
10838 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
10840 macro_build (NULL
, "drorv", "d,t,s", dreg
, sreg
, treg
);
10844 macro_build (NULL
, "dsubu", "d,v,t", AT
, ZERO
, treg
);
10845 macro_build (NULL
, "dsllv", "d,t,s", AT
, sreg
, AT
);
10846 macro_build (NULL
, "dsrlv", "d,t,s", dreg
, sreg
, treg
);
10847 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
10851 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
10853 macro_build (NULL
, "rorv", "d,t,s", dreg
, sreg
, treg
);
10857 macro_build (NULL
, "subu", "d,v,t", AT
, ZERO
, treg
);
10858 macro_build (NULL
, "sllv", "d,t,s", AT
, sreg
, AT
);
10859 macro_build (NULL
, "srlv", "d,t,s", dreg
, sreg
, treg
);
10860 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
10869 if (imm_expr
.X_op
!= O_constant
)
10870 as_bad (_("Improper rotate count"));
10871 rot
= imm_expr
.X_add_number
& 0x3f;
10872 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
10875 macro_build (NULL
, "dror32", SHFT_FMT
, dreg
, sreg
, rot
- 32);
10877 macro_build (NULL
, "dror", SHFT_FMT
, dreg
, sreg
, rot
);
10882 macro_build (NULL
, "dsrl", SHFT_FMT
, dreg
, sreg
, 0);
10885 rr
= (rot
< 0x20) ? "dsrl" : "dsrl32";
10886 l
= ((0x40 - rot
) < 0x20) ? "dsll" : "dsll32";
10889 macro_build (NULL
, rr
, SHFT_FMT
, AT
, sreg
, rot
);
10890 macro_build (NULL
, l
, SHFT_FMT
, dreg
, sreg
, (0x20 - rot
) & 0x1f);
10891 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
10899 if (imm_expr
.X_op
!= O_constant
)
10900 as_bad (_("Improper rotate count"));
10901 rot
= imm_expr
.X_add_number
& 0x1f;
10902 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
10904 macro_build (NULL
, "ror", SHFT_FMT
, dreg
, sreg
, rot
);
10909 macro_build (NULL
, "srl", SHFT_FMT
, dreg
, sreg
, 0);
10913 macro_build (NULL
, "srl", SHFT_FMT
, AT
, sreg
, rot
);
10914 macro_build (NULL
, "sll", SHFT_FMT
, dreg
, sreg
, (0x20 - rot
) & 0x1f);
10915 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
10921 macro_build (&expr1
, "sltiu", "t,r,j", dreg
, treg
, BFD_RELOC_LO16
);
10922 else if (treg
== 0)
10923 macro_build (&expr1
, "sltiu", "t,r,j", dreg
, sreg
, BFD_RELOC_LO16
);
10926 macro_build (NULL
, "xor", "d,v,t", dreg
, sreg
, treg
);
10927 macro_build (&expr1
, "sltiu", "t,r,j", dreg
, dreg
, BFD_RELOC_LO16
);
10932 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
10934 macro_build (&expr1
, "sltiu", "t,r,j", dreg
, sreg
, BFD_RELOC_LO16
);
10939 as_warn (_("Instruction %s: result is always false"),
10940 ip
->insn_mo
->name
);
10941 move_register (dreg
, 0);
10944 if (CPU_HAS_SEQ (mips_opts
.arch
)
10945 && -512 <= imm_expr
.X_add_number
10946 && imm_expr
.X_add_number
< 512)
10948 macro_build (NULL
, "seqi", "t,r,+Q", dreg
, sreg
,
10949 (int) imm_expr
.X_add_number
);
10952 if (imm_expr
.X_op
== O_constant
10953 && imm_expr
.X_add_number
>= 0
10954 && imm_expr
.X_add_number
< 0x10000)
10956 macro_build (&imm_expr
, "xori", "t,r,i", dreg
, sreg
, BFD_RELOC_LO16
);
10958 else if (imm_expr
.X_op
== O_constant
10959 && imm_expr
.X_add_number
> -0x8000
10960 && imm_expr
.X_add_number
< 0)
10962 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
10963 macro_build (&imm_expr
, HAVE_32BIT_GPRS
? "addiu" : "daddiu",
10964 "t,r,j", dreg
, sreg
, BFD_RELOC_LO16
);
10966 else if (CPU_HAS_SEQ (mips_opts
.arch
))
10969 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
10970 macro_build (NULL
, "seq", "d,v,t", dreg
, sreg
, AT
);
10975 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
10976 macro_build (NULL
, "xor", "d,v,t", dreg
, sreg
, AT
);
10979 macro_build (&expr1
, "sltiu", "t,r,j", dreg
, dreg
, BFD_RELOC_LO16
);
10982 case M_SGE
: /* sreg >= treg <==> not (sreg < treg) */
10988 macro_build (NULL
, s
, "d,v,t", dreg
, sreg
, treg
);
10989 macro_build (&expr1
, "xori", "t,r,i", dreg
, dreg
, BFD_RELOC_LO16
);
10992 case M_SGE_I
: /* sreg >= I <==> not (sreg < I) */
10994 if (imm_expr
.X_op
== O_constant
10995 && imm_expr
.X_add_number
>= -0x8000
10996 && imm_expr
.X_add_number
< 0x8000)
10998 macro_build (&imm_expr
, mask
== M_SGE_I
? "slti" : "sltiu", "t,r,j",
10999 dreg
, sreg
, BFD_RELOC_LO16
);
11003 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
11004 macro_build (NULL
, mask
== M_SGE_I
? "slt" : "sltu", "d,v,t",
11008 macro_build (&expr1
, "xori", "t,r,i", dreg
, dreg
, BFD_RELOC_LO16
);
11011 case M_SGT
: /* sreg > treg <==> treg < sreg */
11017 macro_build (NULL
, s
, "d,v,t", dreg
, treg
, sreg
);
11020 case M_SGT_I
: /* sreg > I <==> I < sreg */
11027 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
11028 macro_build (NULL
, s
, "d,v,t", dreg
, AT
, sreg
);
11031 case M_SLE
: /* sreg <= treg <==> treg >= sreg <==> not (treg < sreg) */
11037 macro_build (NULL
, s
, "d,v,t", dreg
, treg
, sreg
);
11038 macro_build (&expr1
, "xori", "t,r,i", dreg
, dreg
, BFD_RELOC_LO16
);
11041 case M_SLE_I
: /* sreg <= I <==> I >= sreg <==> not (I < sreg) */
11048 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
11049 macro_build (NULL
, s
, "d,v,t", dreg
, AT
, sreg
);
11050 macro_build (&expr1
, "xori", "t,r,i", dreg
, dreg
, BFD_RELOC_LO16
);
11054 if (imm_expr
.X_op
== O_constant
11055 && imm_expr
.X_add_number
>= -0x8000
11056 && imm_expr
.X_add_number
< 0x8000)
11058 macro_build (&imm_expr
, "slti", "t,r,j", dreg
, sreg
, BFD_RELOC_LO16
);
11062 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
11063 macro_build (NULL
, "slt", "d,v,t", dreg
, sreg
, AT
);
11067 if (imm_expr
.X_op
== O_constant
11068 && imm_expr
.X_add_number
>= -0x8000
11069 && imm_expr
.X_add_number
< 0x8000)
11071 macro_build (&imm_expr
, "sltiu", "t,r,j", dreg
, sreg
,
11076 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
11077 macro_build (NULL
, "sltu", "d,v,t", dreg
, sreg
, AT
);
11082 macro_build (NULL
, "sltu", "d,v,t", dreg
, 0, treg
);
11083 else if (treg
== 0)
11084 macro_build (NULL
, "sltu", "d,v,t", dreg
, 0, sreg
);
11087 macro_build (NULL
, "xor", "d,v,t", dreg
, sreg
, treg
);
11088 macro_build (NULL
, "sltu", "d,v,t", dreg
, 0, dreg
);
11093 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
11095 macro_build (NULL
, "sltu", "d,v,t", dreg
, 0, sreg
);
11100 as_warn (_("Instruction %s: result is always true"),
11101 ip
->insn_mo
->name
);
11102 macro_build (&expr1
, HAVE_32BIT_GPRS
? "addiu" : "daddiu", "t,r,j",
11103 dreg
, 0, BFD_RELOC_LO16
);
11106 if (CPU_HAS_SEQ (mips_opts
.arch
)
11107 && -512 <= imm_expr
.X_add_number
11108 && imm_expr
.X_add_number
< 512)
11110 macro_build (NULL
, "snei", "t,r,+Q", dreg
, sreg
,
11111 (int) imm_expr
.X_add_number
);
11114 if (imm_expr
.X_op
== O_constant
11115 && imm_expr
.X_add_number
>= 0
11116 && imm_expr
.X_add_number
< 0x10000)
11118 macro_build (&imm_expr
, "xori", "t,r,i", dreg
, sreg
, BFD_RELOC_LO16
);
11120 else if (imm_expr
.X_op
== O_constant
11121 && imm_expr
.X_add_number
> -0x8000
11122 && imm_expr
.X_add_number
< 0)
11124 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
11125 macro_build (&imm_expr
, HAVE_32BIT_GPRS
? "addiu" : "daddiu",
11126 "t,r,j", dreg
, sreg
, BFD_RELOC_LO16
);
11128 else if (CPU_HAS_SEQ (mips_opts
.arch
))
11131 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
11132 macro_build (NULL
, "sne", "d,v,t", dreg
, sreg
, AT
);
11137 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
11138 macro_build (NULL
, "xor", "d,v,t", dreg
, sreg
, AT
);
11141 macro_build (NULL
, "sltu", "d,v,t", dreg
, 0, dreg
);
11156 if (!mips_opts
.micromips
)
11158 if (imm_expr
.X_op
== O_constant
11159 && imm_expr
.X_add_number
> -0x200
11160 && imm_expr
.X_add_number
<= 0x200)
11162 macro_build (NULL
, s
, "t,r,.", dreg
, sreg
, -imm_expr
.X_add_number
);
11171 if (imm_expr
.X_op
== O_constant
11172 && imm_expr
.X_add_number
> -0x8000
11173 && imm_expr
.X_add_number
<= 0x8000)
11175 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
11176 macro_build (&imm_expr
, s
, "t,r,j", dreg
, sreg
, BFD_RELOC_LO16
);
11181 load_register (AT
, &imm_expr
, dbl
);
11182 macro_build (NULL
, s2
, "d,v,t", dreg
, sreg
, AT
);
11204 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
11205 macro_build (NULL
, s
, "s,t", sreg
, AT
);
11210 gas_assert (!mips_opts
.micromips
);
11211 gas_assert (mips_opts
.isa
== ISA_MIPS1
);
11213 sreg
= (ip
->insn_opcode
>> 11) & 0x1f; /* floating reg */
11214 dreg
= (ip
->insn_opcode
>> 06) & 0x1f; /* floating reg */
11217 * Is the double cfc1 instruction a bug in the mips assembler;
11218 * or is there a reason for it?
11220 start_noreorder ();
11221 macro_build (NULL
, "cfc1", "t,G", treg
, RA
);
11222 macro_build (NULL
, "cfc1", "t,G", treg
, RA
);
11223 macro_build (NULL
, "nop", "");
11224 expr1
.X_add_number
= 3;
11225 macro_build (&expr1
, "ori", "t,r,i", AT
, treg
, BFD_RELOC_LO16
);
11226 expr1
.X_add_number
= 2;
11227 macro_build (&expr1
, "xori", "t,r,i", AT
, AT
, BFD_RELOC_LO16
);
11228 macro_build (NULL
, "ctc1", "t,G", AT
, RA
);
11229 macro_build (NULL
, "nop", "");
11230 macro_build (NULL
, mask
== M_TRUNCWD
? "cvt.w.d" : "cvt.w.s", "D,S",
11232 macro_build (NULL
, "ctc1", "t,G", treg
, RA
);
11233 macro_build (NULL
, "nop", "");
11250 offbits
= (mips_opts
.micromips
? 12 : 16);
11256 offbits
= (mips_opts
.micromips
? 12 : 16);
11268 offbits
= (mips_opts
.micromips
? 12 : 16);
11275 offbits
= (mips_opts
.micromips
? 12 : 16);
11280 large_offset
= !small_offset_p (off
, align
, offbits
);
11282 expr1
.X_add_number
= 0;
11287 if (small_offset_p (0, align
, 16))
11288 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", tempreg
, breg
, -1,
11289 offset_reloc
[0], offset_reloc
[1], offset_reloc
[2]);
11292 load_address (tempreg
, ep
, &used_at
);
11294 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
11295 tempreg
, tempreg
, breg
);
11297 offset_reloc
[0] = BFD_RELOC_LO16
;
11298 offset_reloc
[1] = BFD_RELOC_UNUSED
;
11299 offset_reloc
[2] = BFD_RELOC_UNUSED
;
11304 else if (!ust
&& treg
== breg
)
11315 if (!target_big_endian
)
11316 ep
->X_add_number
+= off
;
11318 macro_build (NULL
, s
, "t,~(b)", tempreg
, (int) ep
->X_add_number
, breg
);
11320 macro_build (ep
, s
, "t,o(b)", tempreg
, -1,
11321 offset_reloc
[0], offset_reloc
[1], offset_reloc
[2], breg
);
11323 if (!target_big_endian
)
11324 ep
->X_add_number
-= off
;
11326 ep
->X_add_number
+= off
;
11328 macro_build (NULL
, s2
, "t,~(b)",
11329 tempreg
, (int) ep
->X_add_number
, breg
);
11331 macro_build (ep
, s2
, "t,o(b)", tempreg
, -1,
11332 offset_reloc
[0], offset_reloc
[1], offset_reloc
[2], breg
);
11334 /* If necessary, move the result in tempreg to the final destination. */
11335 if (!ust
&& treg
!= tempreg
)
11337 /* Protect second load's delay slot. */
11339 move_register (treg
, tempreg
);
11345 if (target_big_endian
== ust
)
11346 ep
->X_add_number
+= off
;
11347 tempreg
= ust
|| large_offset
? treg
: AT
;
11348 macro_build (ep
, s
, "t,o(b)", tempreg
, -1,
11349 offset_reloc
[0], offset_reloc
[1], offset_reloc
[2], breg
);
11351 /* For halfword transfers we need a temporary register to shuffle
11352 bytes. Unfortunately for M_USH_A we have none available before
11353 the next store as AT holds the base address. We deal with this
11354 case by clobbering TREG and then restoring it as with ULH. */
11355 tempreg
= ust
== large_offset
? treg
: AT
;
11357 macro_build (NULL
, "srl", SHFT_FMT
, tempreg
, treg
, 8);
11359 if (target_big_endian
== ust
)
11360 ep
->X_add_number
-= off
;
11362 ep
->X_add_number
+= off
;
11363 macro_build (ep
, s2
, "t,o(b)", tempreg
, -1,
11364 offset_reloc
[0], offset_reloc
[1], offset_reloc
[2], breg
);
11366 /* For M_USH_A re-retrieve the LSB. */
11367 if (ust
&& large_offset
)
11369 if (target_big_endian
)
11370 ep
->X_add_number
+= off
;
11372 ep
->X_add_number
-= off
;
11373 macro_build (&expr1
, "lbu", "t,o(b)", AT
, -1,
11374 offset_reloc
[0], offset_reloc
[1], offset_reloc
[2], AT
);
11376 /* For ULH and M_USH_A OR the LSB in. */
11377 if (!ust
|| large_offset
)
11379 tempreg
= !large_offset
? AT
: treg
;
11380 macro_build (NULL
, "sll", SHFT_FMT
, tempreg
, tempreg
, 8);
11381 macro_build (NULL
, "or", "d,v,t", treg
, treg
, AT
);
11386 /* FIXME: Check if this is one of the itbl macros, since they
11387 are added dynamically. */
11388 as_bad (_("Macro %s not implemented yet"), ip
->insn_mo
->name
);
11391 if (!mips_opts
.at
&& used_at
)
11392 as_bad (_("Macro used $at after \".set noat\""));
11395 /* Implement macros in mips16 mode. */
11398 mips16_macro (struct mips_cl_insn
*ip
)
11401 int xreg
, yreg
, zreg
, tmp
;
11404 const char *s
, *s2
, *s3
;
11406 mask
= ip
->insn_mo
->mask
;
11408 xreg
= MIPS16_EXTRACT_OPERAND (RX
, *ip
);
11409 yreg
= MIPS16_EXTRACT_OPERAND (RY
, *ip
);
11410 zreg
= MIPS16_EXTRACT_OPERAND (RZ
, *ip
);
11412 expr1
.X_op
= O_constant
;
11413 expr1
.X_op_symbol
= NULL
;
11414 expr1
.X_add_symbol
= NULL
;
11415 expr1
.X_add_number
= 1;
11434 start_noreorder ();
11435 macro_build (NULL
, dbl
? "ddiv" : "div", "0,x,y", xreg
, yreg
);
11436 expr1
.X_add_number
= 2;
11437 macro_build (&expr1
, "bnez", "x,p", yreg
);
11438 macro_build (NULL
, "break", "6", 7);
11440 /* FIXME: The normal code checks for of -1 / -0x80000000 here,
11441 since that causes an overflow. We should do that as well,
11442 but I don't see how to do the comparisons without a temporary
11445 macro_build (NULL
, s
, "x", zreg
);
11464 start_noreorder ();
11465 macro_build (NULL
, s
, "0,x,y", xreg
, yreg
);
11466 expr1
.X_add_number
= 2;
11467 macro_build (&expr1
, "bnez", "x,p", yreg
);
11468 macro_build (NULL
, "break", "6", 7);
11470 macro_build (NULL
, s2
, "x", zreg
);
11476 macro_build (NULL
, dbl
? "dmultu" : "multu", "x,y", xreg
, yreg
);
11477 macro_build (NULL
, "mflo", "x", zreg
);
11485 if (imm_expr
.X_op
!= O_constant
)
11486 as_bad (_("Unsupported large constant"));
11487 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
11488 macro_build (&imm_expr
, dbl
? "daddiu" : "addiu", "y,x,4", yreg
, xreg
);
11492 if (imm_expr
.X_op
!= O_constant
)
11493 as_bad (_("Unsupported large constant"));
11494 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
11495 macro_build (&imm_expr
, "addiu", "x,k", xreg
);
11499 if (imm_expr
.X_op
!= O_constant
)
11500 as_bad (_("Unsupported large constant"));
11501 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
11502 macro_build (&imm_expr
, "daddiu", "y,j", yreg
);
11524 goto do_reverse_branch
;
11528 goto do_reverse_branch
;
11540 goto do_reverse_branch
;
11551 macro_build (NULL
, s
, "x,y", xreg
, yreg
);
11552 macro_build (&offset_expr
, s2
, "p");
11579 goto do_addone_branch_i
;
11584 goto do_addone_branch_i
;
11599 goto do_addone_branch_i
;
11605 do_addone_branch_i
:
11606 if (imm_expr
.X_op
!= O_constant
)
11607 as_bad (_("Unsupported large constant"));
11608 ++imm_expr
.X_add_number
;
11611 macro_build (&imm_expr
, s
, s3
, xreg
);
11612 macro_build (&offset_expr
, s2
, "p");
11616 expr1
.X_add_number
= 0;
11617 macro_build (&expr1
, "slti", "x,8", yreg
);
11619 move_register (xreg
, yreg
);
11620 expr1
.X_add_number
= 2;
11621 macro_build (&expr1
, "bteqz", "p");
11622 macro_build (NULL
, "neg", "x,w", xreg
, xreg
);
11626 /* Assemble an instruction into its binary format. If the instruction
11627 is a macro, set imm_expr, imm2_expr and offset_expr to the values
11628 associated with "I", "+I" and "A" operands respectively. Otherwise
11629 store the value of the relocatable field (if any) in offset_expr.
11630 In both cases set offset_reloc to the relocation operators applied
11634 mips_ip (char *str
, struct mips_cl_insn
*ip
)
11636 bfd_boolean wrong_delay_slot_insns
= FALSE
;
11637 bfd_boolean need_delay_slot_ok
= TRUE
;
11638 struct mips_opcode
*firstinsn
= NULL
;
11639 const struct mips_opcode
*past
;
11640 struct hash_control
*hash
;
11644 struct mips_opcode
*insn
;
11650 const struct mips_operand
*operand
;
11651 struct mips_arg_info arg
;
11655 if (mips_opts
.micromips
)
11657 hash
= micromips_op_hash
;
11658 past
= µmips_opcodes
[bfd_micromips_num_opcodes
];
11663 past
= &mips_opcodes
[NUMOPCODES
];
11665 forced_insn_length
= 0;
11668 /* We first try to match an instruction up to a space or to the end. */
11669 for (end
= 0; str
[end
] != '\0' && !ISSPACE (str
[end
]); end
++)
11672 /* Make a copy of the instruction so that we can fiddle with it. */
11673 name
= alloca (end
+ 1);
11674 memcpy (name
, str
, end
);
11679 insn
= (struct mips_opcode
*) hash_find (hash
, name
);
11681 if (insn
!= NULL
|| !mips_opts
.micromips
)
11683 if (forced_insn_length
)
11686 /* See if there's an instruction size override suffix,
11687 either `16' or `32', at the end of the mnemonic proper,
11688 that defines the operation, i.e. before the first `.'
11689 character if any. Strip it and retry. */
11690 dot
= strchr (name
, '.');
11691 opend
= dot
!= NULL
? dot
- name
: end
;
11694 if (name
[opend
- 2] == '1' && name
[opend
- 1] == '6')
11695 forced_insn_length
= 2;
11696 else if (name
[opend
- 2] == '3' && name
[opend
- 1] == '2')
11697 forced_insn_length
= 4;
11700 memcpy (name
+ opend
- 2, name
+ opend
, end
- opend
+ 1);
11704 insn_error
= _("Unrecognized opcode");
11708 /* For microMIPS instructions placed in a fixed-length branch delay slot
11709 we make up to two passes over the relevant fragment of the opcode
11710 table. First we try instructions that meet the delay slot's length
11711 requirement. If none matched, then we retry with the remaining ones
11712 and if one matches, then we use it and then issue an appropriate
11713 warning later on. */
11714 argsStart
= s
= str
+ end
;
11717 bfd_boolean delay_slot_ok
;
11718 bfd_boolean size_ok
;
11720 bfd_boolean more_alts
;
11722 gas_assert (strcmp (insn
->name
, name
) == 0);
11724 ok
= is_opcode_valid (insn
);
11725 size_ok
= is_size_valid (insn
);
11726 delay_slot_ok
= is_delay_slot_valid (insn
);
11727 if (!delay_slot_ok
&& !wrong_delay_slot_insns
)
11730 wrong_delay_slot_insns
= TRUE
;
11732 more_alts
= (insn
+ 1 < past
11733 && strcmp (insn
[0].name
, insn
[1].name
) == 0);
11734 if (!ok
|| !size_ok
|| delay_slot_ok
!= need_delay_slot_ok
)
11736 static char buf
[256];
11743 if (wrong_delay_slot_insns
&& need_delay_slot_ok
)
11745 gas_assert (firstinsn
);
11746 need_delay_slot_ok
= FALSE
;
11756 sprintf (buf
, _("Opcode not supported on this processor: %s (%s)"),
11757 mips_cpu_info_from_arch (mips_opts
.arch
)->name
,
11758 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
11759 else if (mips_opts
.insn32
)
11760 sprintf (buf
, _("Opcode not supported in the `insn32' mode"));
11762 sprintf (buf
, _("Unrecognized %u-bit version of microMIPS opcode"),
11763 8 * forced_insn_length
);
11769 imm_expr
.X_op
= O_absent
;
11770 imm2_expr
.X_op
= O_absent
;
11771 offset_expr
.X_op
= O_absent
;
11772 offset_reloc
[0] = BFD_RELOC_UNUSED
;
11773 offset_reloc
[1] = BFD_RELOC_UNUSED
;
11774 offset_reloc
[2] = BFD_RELOC_UNUSED
;
11776 create_insn (ip
, insn
);
11778 memset (&arg
, 0, sizeof (arg
));
11781 arg
.last_regno
= ILLEGAL_REG
;
11782 arg
.dest_regno
= ILLEGAL_REG
;
11783 arg
.soft_match
= (more_alts
11784 || (wrong_delay_slot_insns
&& need_delay_slot_ok
));
11785 for (args
= insn
->args
;; ++args
)
11787 SKIP_SPACE_TABS (s
);
11790 /* Handle unary instructions in which only one operand is given.
11791 The source is then the same as the destination. */
11792 if (arg
.opnum
== 1 && *args
== ',')
11805 /* Treat elided base registers as $0. */
11806 if (strcmp (args
, "(b)") == 0)
11809 /* Fail the match if there were too few operands. */
11813 /* Successful match. */
11814 if (arg
.dest_regno
== arg
.last_regno
11815 && strncmp (ip
->insn_mo
->name
, "jalr", 4) == 0)
11817 if (arg
.opnum
== 2)
11818 as_bad (_("Source and destination must be different"));
11819 else if (arg
.last_regno
== 31)
11820 as_bad (_("A destination register must be supplied"));
11822 check_completed_insn (&arg
);
11826 /* Fail the match if the line has too many operands. */
11830 /* Handle characters that need to match exactly. */
11831 if (*args
== '(' || *args
== ')' || *args
== ',')
11841 /* Handle special macro operands. Work out the properties of
11844 arg
.optional_reg
= FALSE
;
11845 arg
.lax_max
= FALSE
;
11864 /* If these integer forms come last, there is no other
11865 form of the instruction that could match. Prefer to
11866 give detailed error messages where possible. */
11868 arg
.soft_match
= FALSE
;
11872 /* "+I" is like "I", except that imm2_expr is used. */
11873 my_getExpression (&imm2_expr
, s
);
11874 if (imm2_expr
.X_op
!= O_big
11875 && imm2_expr
.X_op
!= O_constant
)
11876 insn_error
= _("absolute expression required");
11877 if (HAVE_32BIT_GPRS
)
11878 normalize_constant_expr (&imm2_expr
);
11884 *offset_reloc
= BFD_RELOC_MIPS_JMP
;
11914 /* If these integer forms come last, there is no other
11915 form of the instruction that could match. Prefer to
11916 give detailed error messages where possible. */
11918 arg
.soft_match
= FALSE
;
11926 /* We have already matched a comma by this point, so the register
11927 is only optional if there is another operand to come. */
11928 gas_assert (arg
.opnum
== 2);
11929 arg
.optional_reg
= (args
[1] == ',');
11933 my_getExpression (&imm_expr
, s
);
11934 if (imm_expr
.X_op
!= O_big
11935 && imm_expr
.X_op
!= O_constant
)
11936 insn_error
= _("absolute expression required");
11937 if (HAVE_32BIT_GPRS
)
11938 normalize_constant_expr (&imm_expr
);
11943 my_getSmallExpression (&offset_expr
, offset_reloc
, s
);
11944 if (offset_expr
.X_op
== O_register
)
11946 /* Assume that the offset has been elided and that what
11947 we saw was a base register. The match will fail later
11948 if that assumption turns out to be wrong. */
11949 offset_expr
.X_op
= O_constant
;
11950 offset_expr
.X_add_number
= 0;
11954 normalize_address_expr (&offset_expr
);
11968 unsigned char temp
[8];
11970 unsigned int length
;
11975 /* These only appear as the last operand in an
11976 instruction, and every instruction that accepts
11977 them in any variant accepts them in all variants.
11978 This means we don't have to worry about backing out
11979 any changes if the instruction does not match.
11981 The difference between them is the size of the
11982 floating point constant and where it goes. For 'F'
11983 and 'L' the constant is 64 bits; for 'f' and 'l' it
11984 is 32 bits. Where the constant is placed is based
11985 on how the MIPS assembler does things:
11988 f -- immediate value
11991 The .lit4 and .lit8 sections are only used if
11992 permitted by the -G argument.
11994 The code below needs to know whether the target register
11995 is 32 or 64 bits wide. It relies on the fact 'f' and
11996 'F' are used with GPR-based instructions and 'l' and
11997 'L' are used with FPR-based instructions. */
11999 f64
= *args
== 'F' || *args
== 'L';
12000 using_gprs
= *args
== 'F' || *args
== 'f';
12002 save_in
= input_line_pointer
;
12003 input_line_pointer
= s
;
12004 err
= md_atof (f64
? 'd' : 'f', (char *) temp
, &len
);
12006 s
= input_line_pointer
;
12007 input_line_pointer
= save_in
;
12008 if (err
!= NULL
&& *err
!= '\0')
12010 as_bad (_("Bad floating point constant: %s"), err
);
12011 memset (temp
, '\0', sizeof temp
);
12012 length
= f64
? 8 : 4;
12015 gas_assert (length
== (unsigned) (f64
? 8 : 4));
12019 && (g_switch_value
< 4
12020 || (temp
[0] == 0 && temp
[1] == 0)
12021 || (temp
[2] == 0 && temp
[3] == 0))))
12023 imm_expr
.X_op
= O_constant
;
12024 if (!target_big_endian
)
12025 imm_expr
.X_add_number
= bfd_getl32 (temp
);
12027 imm_expr
.X_add_number
= bfd_getb32 (temp
);
12029 else if (length
> 4
12030 && !mips_disable_float_construction
12031 /* Constants can only be constructed in GPRs and
12032 copied to FPRs if the GPRs are at least as wide
12033 as the FPRs. Force the constant into memory if
12034 we are using 64-bit FPRs but the GPRs are only
12037 || !(HAVE_64BIT_FPRS
&& HAVE_32BIT_GPRS
))
12038 && ((temp
[0] == 0 && temp
[1] == 0)
12039 || (temp
[2] == 0 && temp
[3] == 0))
12040 && ((temp
[4] == 0 && temp
[5] == 0)
12041 || (temp
[6] == 0 && temp
[7] == 0)))
12043 /* The value is simple enough to load with a couple of
12044 instructions. If using 32-bit registers, set
12045 imm_expr to the high order 32 bits and offset_expr to
12046 the low order 32 bits. Otherwise, set imm_expr to
12047 the entire 64 bit constant. */
12048 if (using_gprs
? HAVE_32BIT_GPRS
: HAVE_32BIT_FPRS
)
12050 imm_expr
.X_op
= O_constant
;
12051 offset_expr
.X_op
= O_constant
;
12052 if (!target_big_endian
)
12054 imm_expr
.X_add_number
= bfd_getl32 (temp
+ 4);
12055 offset_expr
.X_add_number
= bfd_getl32 (temp
);
12059 imm_expr
.X_add_number
= bfd_getb32 (temp
);
12060 offset_expr
.X_add_number
= bfd_getb32 (temp
+ 4);
12062 if (offset_expr
.X_add_number
== 0)
12063 offset_expr
.X_op
= O_absent
;
12067 imm_expr
.X_op
= O_constant
;
12068 if (!target_big_endian
)
12069 imm_expr
.X_add_number
= bfd_getl64 (temp
);
12071 imm_expr
.X_add_number
= bfd_getb64 (temp
);
12076 const char *newname
;
12079 /* Switch to the right section. */
12081 subseg
= now_subseg
;
12084 default: /* unused default case avoids warnings. */
12086 newname
= RDATA_SECTION_NAME
;
12087 if (g_switch_value
>= 8)
12091 newname
= RDATA_SECTION_NAME
;
12094 gas_assert (g_switch_value
>= 4);
12098 new_seg
= subseg_new (newname
, (subsegT
) 0);
12099 bfd_set_section_flags (stdoutput
, new_seg
,
12104 frag_align (*args
== 'l' ? 2 : 3, 0, 0);
12105 if (strncmp (TARGET_OS
, "elf", 3) != 0)
12106 record_alignment (new_seg
, 4);
12108 record_alignment (new_seg
, *args
== 'l' ? 2 : 3);
12109 if (seg
== now_seg
)
12110 as_bad (_("Can't use floating point insn in this section"));
12112 /* Set the argument to the current address in the
12114 offset_expr
.X_op
= O_symbol
;
12115 offset_expr
.X_add_symbol
= symbol_temp_new_now ();
12116 offset_expr
.X_add_number
= 0;
12118 /* Put the floating point number into the section. */
12119 p
= frag_more ((int) length
);
12120 memcpy (p
, temp
, length
);
12122 /* Switch back to the original section. */
12123 subseg_set (seg
, subseg
);
12128 /* ??? This is the traditional behavior, but is flaky if
12129 there are alternative versions of the same instruction
12130 for different subarchitectures. The next alternative
12131 might not be suitable. */
12133 /* For compatibility with older assemblers, we accept
12134 0x8000-0xffff as signed 16-bit numbers when only
12135 signed numbers are allowed. */
12136 arg
.lax_max
= !more_alts
;
12138 /* Only accept non-constant operands if this is the
12139 final alternative. Later alternatives might include
12140 a macro implementation. */
12141 arg
.allow_nonconst
= !more_alts
;
12145 /* There are no macro implementations for out-of-range values. */
12146 arg
.allow_nonconst
= TRUE
;
12150 /* There should always be a macro implementation. */
12151 arg
.allow_nonconst
= FALSE
;
12155 *offset_reloc
= BFD_RELOC_16_PCREL_S2
;
12159 *offset_reloc
= BFD_RELOC_MIPS_JMP
;
12163 gas_assert (mips_opts
.micromips
);
12170 /* We have already matched a comma by this point,
12171 so the register is only optional if there is another
12172 operand to come. */
12173 gas_assert (arg
.opnum
== 2);
12174 arg
.optional_reg
= (args
[2] == ',');
12179 if (!forced_insn_length
)
12180 *offset_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
12182 *offset_reloc
= BFD_RELOC_MICROMIPS_10_PCREL_S1
;
12184 *offset_reloc
= BFD_RELOC_MICROMIPS_7_PCREL_S1
;
12190 operand
= (mips_opts
.micromips
12191 ? decode_micromips_operand (args
)
12192 : decode_mips_operand (args
));
12196 s
= match_operand (&arg
, operand
, s
);
12197 if (!s
&& arg
.optional_reg
)
12199 /* Assume that the register has been elided and is the
12200 same as the first operand. */
12201 arg
.optional_reg
= FALSE
;
12204 SKIP_SPACE_TABS (s
);
12205 s
= match_operand (&arg
, operand
, s
);
12210 /* Skip prefixes. */
12211 if (*args
== '+' || *args
== 'm')
12216 /* Args don't match. */
12218 insn_error
= _("Illegal operands");
12224 if (wrong_delay_slot_insns
&& need_delay_slot_ok
)
12226 gas_assert (firstinsn
);
12227 need_delay_slot_ok
= FALSE
;
12236 /* As for mips_ip, but used when assembling MIPS16 code.
12237 Also set forced_insn_length to the resulting instruction size in
12238 bytes if the user explicitly requested a small or extended instruction. */
12241 mips16_ip (char *str
, struct mips_cl_insn
*ip
)
12245 struct mips_opcode
*insn
;
12248 const struct mips_operand
*operand
;
12249 const struct mips_operand
*ext_operand
;
12250 struct mips_arg_info arg
;
12254 forced_insn_length
= 0;
12256 for (s
= str
; ISLOWER (*s
); ++s
)
12268 if (s
[1] == 't' && s
[2] == ' ')
12271 forced_insn_length
= 2;
12275 else if (s
[1] == 'e' && s
[2] == ' ')
12278 forced_insn_length
= 4;
12282 /* Fall through. */
12284 insn_error
= _("unknown opcode");
12288 if (mips_opts
.noautoextend
&& !forced_insn_length
)
12289 forced_insn_length
= 2;
12291 if ((insn
= (struct mips_opcode
*) hash_find (mips16_op_hash
, str
)) == NULL
)
12293 insn_error
= _("unrecognized opcode");
12301 bfd_boolean more_alts
;
12304 gas_assert (strcmp (insn
->name
, str
) == 0);
12306 ok
= is_opcode_valid_16 (insn
);
12307 more_alts
= (insn
+ 1 < &mips16_opcodes
[bfd_mips16_num_opcodes
]
12308 && strcmp (insn
[0].name
, insn
[1].name
) == 0);
12320 static char buf
[100];
12322 _("Opcode not supported on this processor: %s (%s)"),
12323 mips_cpu_info_from_arch (mips_opts
.arch
)->name
,
12324 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
12331 create_insn (ip
, insn
);
12332 imm_expr
.X_op
= O_absent
;
12333 imm2_expr
.X_op
= O_absent
;
12334 offset_expr
.X_op
= O_absent
;
12335 offset_reloc
[0] = BFD_RELOC_UNUSED
;
12336 offset_reloc
[1] = BFD_RELOC_UNUSED
;
12337 offset_reloc
[2] = BFD_RELOC_UNUSED
;
12340 memset (&arg
, 0, sizeof (arg
));
12343 arg
.last_regno
= ILLEGAL_REG
;
12344 arg
.dest_regno
= ILLEGAL_REG
;
12345 arg
.soft_match
= more_alts
;
12347 for (args
= insn
->args
; 1; ++args
)
12351 SKIP_SPACE_TABS (s
);
12356 /* Handle unary instructions in which only one operand is given.
12357 The source is then the same as the destination. */
12358 if (arg
.opnum
== 1 && *args
== ',')
12368 /* Fail the match if there were too few operands. */
12372 /* Successful match. Stuff the immediate value in now, if
12374 if (insn
->pinfo
== INSN_MACRO
)
12376 gas_assert (relax_char
== 0);
12377 gas_assert (*offset_reloc
== BFD_RELOC_UNUSED
);
12379 else if (relax_char
12380 && offset_expr
.X_op
== O_constant
12381 && calculate_reloc (*offset_reloc
,
12382 offset_expr
.X_add_number
,
12385 mips16_immed (NULL
, 0, relax_char
, *offset_reloc
, value
,
12386 forced_insn_length
, &ip
->insn_opcode
);
12387 offset_expr
.X_op
= O_absent
;
12388 *offset_reloc
= BFD_RELOC_UNUSED
;
12390 else if (relax_char
&& *offset_reloc
!= BFD_RELOC_UNUSED
)
12392 if (forced_insn_length
== 2)
12393 as_bad (_("invalid unextended operand value"));
12394 forced_insn_length
= 4;
12395 ip
->insn_opcode
|= MIPS16_EXTEND
;
12397 else if (relax_char
)
12398 *offset_reloc
= (int) BFD_RELOC_UNUSED
+ relax_char
;
12400 check_completed_insn (&arg
);
12404 /* Fail the match if the line has too many operands. */
12408 /* Handle characters that need to match exactly. */
12409 if (*args
== '(' || *args
== ')' || *args
== ',')
12420 arg
.optional_reg
= FALSE
;
12426 arg
.optional_reg
= (args
[1] == ',');
12438 my_getExpression (&imm_expr
, s
);
12439 if (imm_expr
.X_op
!= O_big
12440 && imm_expr
.X_op
!= O_constant
)
12441 insn_error
= _("absolute expression required");
12442 if (HAVE_32BIT_GPRS
)
12443 normalize_constant_expr (&imm_expr
);
12449 *offset_reloc
= BFD_RELOC_MIPS16_JMP
;
12450 ip
->insn_opcode
<<= 16;
12454 operand
= decode_mips16_operand (c
, FALSE
);
12458 /* '6' is a special case. It is used for BREAK and SDBBP,
12459 whose operands are only meaningful to the software that decodes
12460 them. This means that there is no architectural reason why
12461 they cannot be prefixed by EXTEND, but in practice,
12462 exception handlers will only look at the instruction
12463 itself. We therefore allow '6' to be extended when
12464 disassembling but not when assembling. */
12465 if (operand
->type
!= OP_PCREL
&& c
!= '6')
12467 ext_operand
= decode_mips16_operand (c
, TRUE
);
12468 if (operand
!= ext_operand
)
12470 /* Parse the expression, allowing relocation operators. */
12471 i
= my_getSmallExpression (&offset_expr
, offset_reloc
, s
);
12474 if (offset_expr
.X_op
== O_register
)
12476 /* Handle elided offsets, which are equivalent to 0. */
12479 offset_expr
.X_op
= O_constant
;
12480 offset_expr
.X_add_number
= 0;
12484 /* Fail the match. */
12487 /* '8' is used for SLTI(U) and has traditionally not
12488 been allowed to take relocation operators. */
12489 if (i
> 0 && (ext_operand
->size
!= 16 || c
== '8'))
12496 s
= match_operand (&arg
, operand
, s
);
12497 if (!s
&& arg
.optional_reg
)
12499 /* Assume that the register has been elided and is the
12500 same as the first operand. */
12501 arg
.optional_reg
= FALSE
;
12504 SKIP_SPACE_TABS (s
);
12505 s
= match_operand (&arg
, operand
, s
);
12512 /* Args don't match. */
12520 insn_error
= _("illegal operands");
12526 /* This structure holds information we know about a mips16 immediate
12529 struct mips16_immed_operand
12531 /* The type code used in the argument string in the opcode table. */
12533 /* The number of bits in the short form of the opcode. */
12535 /* The number of bits in the extended form of the opcode. */
12537 /* The amount by which the short form is shifted when it is used;
12538 for example, the sw instruction has a shift count of 2. */
12540 /* The amount by which the short form is shifted when it is stored
12541 into the instruction code. */
12543 /* Non-zero if the short form is unsigned. */
12545 /* Non-zero if the extended form is unsigned. */
12547 /* Non-zero if the value is PC relative. */
12551 /* The mips16 immediate operand types. */
12553 static const struct mips16_immed_operand mips16_immed_operands
[] =
12555 { '<', 3, 5, 0, MIPS16OP_SH_RZ
, 1, 1, 0 },
12556 { '>', 3, 5, 0, MIPS16OP_SH_RX
, 1, 1, 0 },
12557 { '[', 3, 6, 0, MIPS16OP_SH_RZ
, 1, 1, 0 },
12558 { ']', 3, 6, 0, MIPS16OP_SH_RX
, 1, 1, 0 },
12559 { '4', 4, 15, 0, MIPS16OP_SH_IMM4
, 0, 0, 0 },
12560 { '5', 5, 16, 0, MIPS16OP_SH_IMM5
, 1, 0, 0 },
12561 { 'H', 5, 16, 1, MIPS16OP_SH_IMM5
, 1, 0, 0 },
12562 { 'W', 5, 16, 2, MIPS16OP_SH_IMM5
, 1, 0, 0 },
12563 { 'D', 5, 16, 3, MIPS16OP_SH_IMM5
, 1, 0, 0 },
12564 { 'j', 5, 16, 0, MIPS16OP_SH_IMM5
, 0, 0, 0 },
12565 { '8', 8, 16, 0, MIPS16OP_SH_IMM8
, 1, 0, 0 },
12566 { 'V', 8, 16, 2, MIPS16OP_SH_IMM8
, 1, 0, 0 },
12567 { 'C', 8, 16, 3, MIPS16OP_SH_IMM8
, 1, 0, 0 },
12568 { 'U', 8, 16, 0, MIPS16OP_SH_IMM8
, 1, 1, 0 },
12569 { 'k', 8, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 0 },
12570 { 'K', 8, 16, 3, MIPS16OP_SH_IMM8
, 0, 0, 0 },
12571 { 'p', 8, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 1 },
12572 { 'q', 11, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 1 },
12573 { 'A', 8, 16, 2, MIPS16OP_SH_IMM8
, 1, 0, 1 },
12574 { 'B', 5, 16, 3, MIPS16OP_SH_IMM5
, 1, 0, 1 },
12575 { 'E', 5, 16, 2, MIPS16OP_SH_IMM5
, 1, 0, 1 }
12578 #define MIPS16_NUM_IMMED \
12579 (sizeof mips16_immed_operands / sizeof mips16_immed_operands[0])
12581 /* Marshal immediate value VAL for an extended MIPS16 instruction.
12582 NBITS is the number of significant bits in VAL. */
12584 static unsigned long
12585 mips16_immed_extend (offsetT val
, unsigned int nbits
)
12590 extval
= ((val
>> 11) & 0x1f) | (val
& 0x7e0);
12593 else if (nbits
== 15)
12595 extval
= ((val
>> 11) & 0xf) | (val
& 0x7f0);
12600 extval
= ((val
& 0x1f) << 6) | (val
& 0x20);
12603 return (extval
<< 16) | val
;
12606 /* Install immediate value VAL into MIPS16 instruction *INSN,
12607 extending it if necessary. The instruction in *INSN may
12608 already be extended.
12610 RELOC is the relocation that produced VAL, or BFD_RELOC_UNUSED
12611 if none. In the former case, VAL is a 16-bit number with no
12612 defined signedness.
12614 TYPE is the type of the immediate field. USER_INSN_LENGTH
12615 is the length that the user requested, or 0 if none. */
12618 mips16_immed (char *file
, unsigned int line
, int type
,
12619 bfd_reloc_code_real_type reloc
, offsetT val
,
12620 unsigned int user_insn_length
, unsigned long *insn
)
12622 const struct mips16_immed_operand
*op
;
12623 int mintiny
, maxtiny
;
12625 op
= mips16_immed_operands
;
12626 while (op
->type
!= type
)
12629 gas_assert (op
< mips16_immed_operands
+ MIPS16_NUM_IMMED
);
12634 if (type
== '<' || type
== '>' || type
== '[' || type
== ']')
12637 maxtiny
= 1 << op
->nbits
;
12642 maxtiny
= (1 << op
->nbits
) - 1;
12644 if (reloc
!= BFD_RELOC_UNUSED
)
12649 mintiny
= - (1 << (op
->nbits
- 1));
12650 maxtiny
= (1 << (op
->nbits
- 1)) - 1;
12651 if (reloc
!= BFD_RELOC_UNUSED
)
12652 val
= SEXT_16BIT (val
);
12655 /* Branch offsets have an implicit 0 in the lowest bit. */
12656 if (type
== 'p' || type
== 'q')
12659 if ((val
& ((1 << op
->shift
) - 1)) != 0
12660 || val
< (mintiny
<< op
->shift
)
12661 || val
> (maxtiny
<< op
->shift
))
12663 /* We need an extended instruction. */
12664 if (user_insn_length
== 2)
12665 as_bad_where (file
, line
, _("invalid unextended operand value"));
12667 *insn
|= MIPS16_EXTEND
;
12669 else if (user_insn_length
== 4)
12671 /* The operand doesn't force an unextended instruction to be extended.
12672 Warn if the user wanted an extended instruction anyway. */
12673 *insn
|= MIPS16_EXTEND
;
12674 as_warn_where (file
, line
,
12675 _("extended operand requested but not required"));
12678 if (mips16_opcode_length (*insn
) == 2)
12682 insnval
= ((val
>> op
->shift
) & ((1 << op
->nbits
) - 1));
12683 insnval
<<= op
->op_shift
;
12688 long minext
, maxext
;
12690 if (reloc
== BFD_RELOC_UNUSED
)
12695 maxext
= (1 << op
->extbits
) - 1;
12699 minext
= - (1 << (op
->extbits
- 1));
12700 maxext
= (1 << (op
->extbits
- 1)) - 1;
12702 if (val
< minext
|| val
> maxext
)
12703 as_bad_where (file
, line
,
12704 _("operand value out of range for instruction"));
12707 *insn
|= mips16_immed_extend (val
, op
->extbits
);
12711 struct percent_op_match
12714 bfd_reloc_code_real_type reloc
;
12717 static const struct percent_op_match mips_percent_op
[] =
12719 {"%lo", BFD_RELOC_LO16
},
12720 {"%call_hi", BFD_RELOC_MIPS_CALL_HI16
},
12721 {"%call_lo", BFD_RELOC_MIPS_CALL_LO16
},
12722 {"%call16", BFD_RELOC_MIPS_CALL16
},
12723 {"%got_disp", BFD_RELOC_MIPS_GOT_DISP
},
12724 {"%got_page", BFD_RELOC_MIPS_GOT_PAGE
},
12725 {"%got_ofst", BFD_RELOC_MIPS_GOT_OFST
},
12726 {"%got_hi", BFD_RELOC_MIPS_GOT_HI16
},
12727 {"%got_lo", BFD_RELOC_MIPS_GOT_LO16
},
12728 {"%got", BFD_RELOC_MIPS_GOT16
},
12729 {"%gp_rel", BFD_RELOC_GPREL16
},
12730 {"%half", BFD_RELOC_16
},
12731 {"%highest", BFD_RELOC_MIPS_HIGHEST
},
12732 {"%higher", BFD_RELOC_MIPS_HIGHER
},
12733 {"%neg", BFD_RELOC_MIPS_SUB
},
12734 {"%tlsgd", BFD_RELOC_MIPS_TLS_GD
},
12735 {"%tlsldm", BFD_RELOC_MIPS_TLS_LDM
},
12736 {"%dtprel_hi", BFD_RELOC_MIPS_TLS_DTPREL_HI16
},
12737 {"%dtprel_lo", BFD_RELOC_MIPS_TLS_DTPREL_LO16
},
12738 {"%tprel_hi", BFD_RELOC_MIPS_TLS_TPREL_HI16
},
12739 {"%tprel_lo", BFD_RELOC_MIPS_TLS_TPREL_LO16
},
12740 {"%gottprel", BFD_RELOC_MIPS_TLS_GOTTPREL
},
12741 {"%hi", BFD_RELOC_HI16_S
}
12744 static const struct percent_op_match mips16_percent_op
[] =
12746 {"%lo", BFD_RELOC_MIPS16_LO16
},
12747 {"%gprel", BFD_RELOC_MIPS16_GPREL
},
12748 {"%got", BFD_RELOC_MIPS16_GOT16
},
12749 {"%call16", BFD_RELOC_MIPS16_CALL16
},
12750 {"%hi", BFD_RELOC_MIPS16_HI16_S
},
12751 {"%tlsgd", BFD_RELOC_MIPS16_TLS_GD
},
12752 {"%tlsldm", BFD_RELOC_MIPS16_TLS_LDM
},
12753 {"%dtprel_hi", BFD_RELOC_MIPS16_TLS_DTPREL_HI16
},
12754 {"%dtprel_lo", BFD_RELOC_MIPS16_TLS_DTPREL_LO16
},
12755 {"%tprel_hi", BFD_RELOC_MIPS16_TLS_TPREL_HI16
},
12756 {"%tprel_lo", BFD_RELOC_MIPS16_TLS_TPREL_LO16
},
12757 {"%gottprel", BFD_RELOC_MIPS16_TLS_GOTTPREL
}
12761 /* Return true if *STR points to a relocation operator. When returning true,
12762 move *STR over the operator and store its relocation code in *RELOC.
12763 Leave both *STR and *RELOC alone when returning false. */
12766 parse_relocation (char **str
, bfd_reloc_code_real_type
*reloc
)
12768 const struct percent_op_match
*percent_op
;
12771 if (mips_opts
.mips16
)
12773 percent_op
= mips16_percent_op
;
12774 limit
= ARRAY_SIZE (mips16_percent_op
);
12778 percent_op
= mips_percent_op
;
12779 limit
= ARRAY_SIZE (mips_percent_op
);
12782 for (i
= 0; i
< limit
; i
++)
12783 if (strncasecmp (*str
, percent_op
[i
].str
, strlen (percent_op
[i
].str
)) == 0)
12785 int len
= strlen (percent_op
[i
].str
);
12787 if (!ISSPACE ((*str
)[len
]) && (*str
)[len
] != '(')
12790 *str
+= strlen (percent_op
[i
].str
);
12791 *reloc
= percent_op
[i
].reloc
;
12793 /* Check whether the output BFD supports this relocation.
12794 If not, issue an error and fall back on something safe. */
12795 if (!bfd_reloc_type_lookup (stdoutput
, percent_op
[i
].reloc
))
12797 as_bad (_("relocation %s isn't supported by the current ABI"),
12798 percent_op
[i
].str
);
12799 *reloc
= BFD_RELOC_UNUSED
;
12807 /* Parse string STR as a 16-bit relocatable operand. Store the
12808 expression in *EP and the relocations in the array starting
12809 at RELOC. Return the number of relocation operators used.
12811 On exit, EXPR_END points to the first character after the expression. */
12814 my_getSmallExpression (expressionS
*ep
, bfd_reloc_code_real_type
*reloc
,
12817 bfd_reloc_code_real_type reversed_reloc
[3];
12818 size_t reloc_index
, i
;
12819 int crux_depth
, str_depth
;
12822 /* Search for the start of the main expression, recoding relocations
12823 in REVERSED_RELOC. End the loop with CRUX pointing to the start
12824 of the main expression and with CRUX_DEPTH containing the number
12825 of open brackets at that point. */
12832 crux_depth
= str_depth
;
12834 /* Skip over whitespace and brackets, keeping count of the number
12836 while (*str
== ' ' || *str
== '\t' || *str
== '(')
12841 && reloc_index
< (HAVE_NEWABI
? 3 : 1)
12842 && parse_relocation (&str
, &reversed_reloc
[reloc_index
]));
12844 my_getExpression (ep
, crux
);
12847 /* Match every open bracket. */
12848 while (crux_depth
> 0 && (*str
== ')' || *str
== ' ' || *str
== '\t'))
12852 if (crux_depth
> 0)
12853 as_bad (_("unclosed '('"));
12857 if (reloc_index
!= 0)
12859 prev_reloc_op_frag
= frag_now
;
12860 for (i
= 0; i
< reloc_index
; i
++)
12861 reloc
[i
] = reversed_reloc
[reloc_index
- 1 - i
];
12864 return reloc_index
;
12868 my_getExpression (expressionS
*ep
, char *str
)
12872 save_in
= input_line_pointer
;
12873 input_line_pointer
= str
;
12875 expr_end
= input_line_pointer
;
12876 input_line_pointer
= save_in
;
12880 md_atof (int type
, char *litP
, int *sizeP
)
12882 return ieee_md_atof (type
, litP
, sizeP
, target_big_endian
);
12886 md_number_to_chars (char *buf
, valueT val
, int n
)
12888 if (target_big_endian
)
12889 number_to_chars_bigendian (buf
, val
, n
);
12891 number_to_chars_littleendian (buf
, val
, n
);
12894 static int support_64bit_objects(void)
12896 const char **list
, **l
;
12899 list
= bfd_target_list ();
12900 for (l
= list
; *l
!= NULL
; l
++)
12901 if (strcmp (*l
, ELF_TARGET ("elf64-", "big")) == 0
12902 || strcmp (*l
, ELF_TARGET ("elf64-", "little")) == 0)
12904 yes
= (*l
!= NULL
);
12909 /* Set STRING_PTR (either &mips_arch_string or &mips_tune_string) to
12910 NEW_VALUE. Warn if another value was already specified. Note:
12911 we have to defer parsing the -march and -mtune arguments in order
12912 to handle 'from-abi' correctly, since the ABI might be specified
12913 in a later argument. */
12916 mips_set_option_string (const char **string_ptr
, const char *new_value
)
12918 if (*string_ptr
!= 0 && strcasecmp (*string_ptr
, new_value
) != 0)
12919 as_warn (_("A different %s was already specified, is now %s"),
12920 string_ptr
== &mips_arch_string
? "-march" : "-mtune",
12923 *string_ptr
= new_value
;
12927 md_parse_option (int c
, char *arg
)
12931 for (i
= 0; i
< ARRAY_SIZE (mips_ases
); i
++)
12932 if (c
== mips_ases
[i
].option_on
|| c
== mips_ases
[i
].option_off
)
12934 file_ase_explicit
|= mips_set_ase (&mips_ases
[i
],
12935 c
== mips_ases
[i
].option_on
);
12941 case OPTION_CONSTRUCT_FLOATS
:
12942 mips_disable_float_construction
= 0;
12945 case OPTION_NO_CONSTRUCT_FLOATS
:
12946 mips_disable_float_construction
= 1;
12958 target_big_endian
= 1;
12962 target_big_endian
= 0;
12968 else if (arg
[0] == '0')
12970 else if (arg
[0] == '1')
12980 mips_debug
= atoi (arg
);
12984 file_mips_isa
= ISA_MIPS1
;
12988 file_mips_isa
= ISA_MIPS2
;
12992 file_mips_isa
= ISA_MIPS3
;
12996 file_mips_isa
= ISA_MIPS4
;
13000 file_mips_isa
= ISA_MIPS5
;
13003 case OPTION_MIPS32
:
13004 file_mips_isa
= ISA_MIPS32
;
13007 case OPTION_MIPS32R2
:
13008 file_mips_isa
= ISA_MIPS32R2
;
13011 case OPTION_MIPS64R2
:
13012 file_mips_isa
= ISA_MIPS64R2
;
13015 case OPTION_MIPS64
:
13016 file_mips_isa
= ISA_MIPS64
;
13020 mips_set_option_string (&mips_tune_string
, arg
);
13024 mips_set_option_string (&mips_arch_string
, arg
);
13028 mips_set_option_string (&mips_arch_string
, "4650");
13029 mips_set_option_string (&mips_tune_string
, "4650");
13032 case OPTION_NO_M4650
:
13036 mips_set_option_string (&mips_arch_string
, "4010");
13037 mips_set_option_string (&mips_tune_string
, "4010");
13040 case OPTION_NO_M4010
:
13044 mips_set_option_string (&mips_arch_string
, "4100");
13045 mips_set_option_string (&mips_tune_string
, "4100");
13048 case OPTION_NO_M4100
:
13052 mips_set_option_string (&mips_arch_string
, "3900");
13053 mips_set_option_string (&mips_tune_string
, "3900");
13056 case OPTION_NO_M3900
:
13059 case OPTION_MICROMIPS
:
13060 if (mips_opts
.mips16
== 1)
13062 as_bad (_("-mmicromips cannot be used with -mips16"));
13065 mips_opts
.micromips
= 1;
13066 mips_no_prev_insn ();
13069 case OPTION_NO_MICROMIPS
:
13070 mips_opts
.micromips
= 0;
13071 mips_no_prev_insn ();
13074 case OPTION_MIPS16
:
13075 if (mips_opts
.micromips
== 1)
13077 as_bad (_("-mips16 cannot be used with -micromips"));
13080 mips_opts
.mips16
= 1;
13081 mips_no_prev_insn ();
13084 case OPTION_NO_MIPS16
:
13085 mips_opts
.mips16
= 0;
13086 mips_no_prev_insn ();
13089 case OPTION_FIX_24K
:
13093 case OPTION_NO_FIX_24K
:
13097 case OPTION_FIX_LOONGSON2F_JUMP
:
13098 mips_fix_loongson2f_jump
= TRUE
;
13101 case OPTION_NO_FIX_LOONGSON2F_JUMP
:
13102 mips_fix_loongson2f_jump
= FALSE
;
13105 case OPTION_FIX_LOONGSON2F_NOP
:
13106 mips_fix_loongson2f_nop
= TRUE
;
13109 case OPTION_NO_FIX_LOONGSON2F_NOP
:
13110 mips_fix_loongson2f_nop
= FALSE
;
13113 case OPTION_FIX_VR4120
:
13114 mips_fix_vr4120
= 1;
13117 case OPTION_NO_FIX_VR4120
:
13118 mips_fix_vr4120
= 0;
13121 case OPTION_FIX_VR4130
:
13122 mips_fix_vr4130
= 1;
13125 case OPTION_NO_FIX_VR4130
:
13126 mips_fix_vr4130
= 0;
13129 case OPTION_FIX_CN63XXP1
:
13130 mips_fix_cn63xxp1
= TRUE
;
13133 case OPTION_NO_FIX_CN63XXP1
:
13134 mips_fix_cn63xxp1
= FALSE
;
13137 case OPTION_RELAX_BRANCH
:
13138 mips_relax_branch
= 1;
13141 case OPTION_NO_RELAX_BRANCH
:
13142 mips_relax_branch
= 0;
13145 case OPTION_INSN32
:
13146 mips_opts
.insn32
= TRUE
;
13149 case OPTION_NO_INSN32
:
13150 mips_opts
.insn32
= FALSE
;
13153 case OPTION_MSHARED
:
13154 mips_in_shared
= TRUE
;
13157 case OPTION_MNO_SHARED
:
13158 mips_in_shared
= FALSE
;
13161 case OPTION_MSYM32
:
13162 mips_opts
.sym32
= TRUE
;
13165 case OPTION_MNO_SYM32
:
13166 mips_opts
.sym32
= FALSE
;
13169 /* When generating ELF code, we permit -KPIC and -call_shared to
13170 select SVR4_PIC, and -non_shared to select no PIC. This is
13171 intended to be compatible with Irix 5. */
13172 case OPTION_CALL_SHARED
:
13173 mips_pic
= SVR4_PIC
;
13174 mips_abicalls
= TRUE
;
13177 case OPTION_CALL_NONPIC
:
13179 mips_abicalls
= TRUE
;
13182 case OPTION_NON_SHARED
:
13184 mips_abicalls
= FALSE
;
13187 /* The -xgot option tells the assembler to use 32 bit offsets
13188 when accessing the got in SVR4_PIC mode. It is for Irix
13195 g_switch_value
= atoi (arg
);
13199 /* The -32, -n32 and -64 options are shortcuts for -mabi=32, -mabi=n32
13202 mips_abi
= O32_ABI
;
13206 mips_abi
= N32_ABI
;
13210 mips_abi
= N64_ABI
;
13211 if (!support_64bit_objects())
13212 as_fatal (_("No compiled in support for 64 bit object file format"));
13216 file_mips_gp32
= 1;
13220 file_mips_gp32
= 0;
13224 file_mips_fp32
= 1;
13228 file_mips_fp32
= 0;
13231 case OPTION_SINGLE_FLOAT
:
13232 file_mips_single_float
= 1;
13235 case OPTION_DOUBLE_FLOAT
:
13236 file_mips_single_float
= 0;
13239 case OPTION_SOFT_FLOAT
:
13240 file_mips_soft_float
= 1;
13243 case OPTION_HARD_FLOAT
:
13244 file_mips_soft_float
= 0;
13248 if (strcmp (arg
, "32") == 0)
13249 mips_abi
= O32_ABI
;
13250 else if (strcmp (arg
, "o64") == 0)
13251 mips_abi
= O64_ABI
;
13252 else if (strcmp (arg
, "n32") == 0)
13253 mips_abi
= N32_ABI
;
13254 else if (strcmp (arg
, "64") == 0)
13256 mips_abi
= N64_ABI
;
13257 if (! support_64bit_objects())
13258 as_fatal (_("No compiled in support for 64 bit object file "
13261 else if (strcmp (arg
, "eabi") == 0)
13262 mips_abi
= EABI_ABI
;
13265 as_fatal (_("invalid abi -mabi=%s"), arg
);
13270 case OPTION_M7000_HILO_FIX
:
13271 mips_7000_hilo_fix
= TRUE
;
13274 case OPTION_MNO_7000_HILO_FIX
:
13275 mips_7000_hilo_fix
= FALSE
;
13278 case OPTION_MDEBUG
:
13279 mips_flag_mdebug
= TRUE
;
13282 case OPTION_NO_MDEBUG
:
13283 mips_flag_mdebug
= FALSE
;
13287 mips_flag_pdr
= TRUE
;
13290 case OPTION_NO_PDR
:
13291 mips_flag_pdr
= FALSE
;
13294 case OPTION_MVXWORKS_PIC
:
13295 mips_pic
= VXWORKS_PIC
;
13299 if (strcmp (arg
, "2008") == 0)
13300 mips_flag_nan2008
= TRUE
;
13301 else if (strcmp (arg
, "legacy") == 0)
13302 mips_flag_nan2008
= FALSE
;
13305 as_fatal (_("Invalid NaN setting -mnan=%s"), arg
);
13314 mips_fix_loongson2f
= mips_fix_loongson2f_nop
|| mips_fix_loongson2f_jump
;
13319 /* Set up globals to generate code for the ISA or processor
13320 described by INFO. */
13323 mips_set_architecture (const struct mips_cpu_info
*info
)
13327 file_mips_arch
= info
->cpu
;
13328 mips_opts
.arch
= info
->cpu
;
13329 mips_opts
.isa
= info
->isa
;
13334 /* Likewise for tuning. */
13337 mips_set_tune (const struct mips_cpu_info
*info
)
13340 mips_tune
= info
->cpu
;
13345 mips_after_parse_args (void)
13347 const struct mips_cpu_info
*arch_info
= 0;
13348 const struct mips_cpu_info
*tune_info
= 0;
13350 /* GP relative stuff not working for PE */
13351 if (strncmp (TARGET_OS
, "pe", 2) == 0)
13353 if (g_switch_seen
&& g_switch_value
!= 0)
13354 as_bad (_("-G not supported in this configuration."));
13355 g_switch_value
= 0;
13358 if (mips_abi
== NO_ABI
)
13359 mips_abi
= MIPS_DEFAULT_ABI
;
13361 /* The following code determines the architecture and register size.
13362 Similar code was added to GCC 3.3 (see override_options() in
13363 config/mips/mips.c). The GAS and GCC code should be kept in sync
13364 as much as possible. */
13366 if (mips_arch_string
!= 0)
13367 arch_info
= mips_parse_cpu ("-march", mips_arch_string
);
13369 if (file_mips_isa
!= ISA_UNKNOWN
)
13371 /* Handle -mipsN. At this point, file_mips_isa contains the
13372 ISA level specified by -mipsN, while arch_info->isa contains
13373 the -march selection (if any). */
13374 if (arch_info
!= 0)
13376 /* -march takes precedence over -mipsN, since it is more descriptive.
13377 There's no harm in specifying both as long as the ISA levels
13379 if (file_mips_isa
!= arch_info
->isa
)
13380 as_bad (_("-%s conflicts with the other architecture options, which imply -%s"),
13381 mips_cpu_info_from_isa (file_mips_isa
)->name
,
13382 mips_cpu_info_from_isa (arch_info
->isa
)->name
);
13385 arch_info
= mips_cpu_info_from_isa (file_mips_isa
);
13388 if (arch_info
== 0)
13390 arch_info
= mips_parse_cpu ("default CPU", MIPS_CPU_STRING_DEFAULT
);
13391 gas_assert (arch_info
);
13394 if (ABI_NEEDS_64BIT_REGS (mips_abi
) && !ISA_HAS_64BIT_REGS (arch_info
->isa
))
13395 as_bad (_("-march=%s is not compatible with the selected ABI"),
13398 mips_set_architecture (arch_info
);
13400 /* Optimize for file_mips_arch, unless -mtune selects a different processor. */
13401 if (mips_tune_string
!= 0)
13402 tune_info
= mips_parse_cpu ("-mtune", mips_tune_string
);
13404 if (tune_info
== 0)
13405 mips_set_tune (arch_info
);
13407 mips_set_tune (tune_info
);
13409 if (file_mips_gp32
>= 0)
13411 /* The user specified the size of the integer registers. Make sure
13412 it agrees with the ABI and ISA. */
13413 if (file_mips_gp32
== 0 && !ISA_HAS_64BIT_REGS (mips_opts
.isa
))
13414 as_bad (_("-mgp64 used with a 32-bit processor"));
13415 else if (file_mips_gp32
== 1 && ABI_NEEDS_64BIT_REGS (mips_abi
))
13416 as_bad (_("-mgp32 used with a 64-bit ABI"));
13417 else if (file_mips_gp32
== 0 && ABI_NEEDS_32BIT_REGS (mips_abi
))
13418 as_bad (_("-mgp64 used with a 32-bit ABI"));
13422 /* Infer the integer register size from the ABI and processor.
13423 Restrict ourselves to 32-bit registers if that's all the
13424 processor has, or if the ABI cannot handle 64-bit registers. */
13425 file_mips_gp32
= (ABI_NEEDS_32BIT_REGS (mips_abi
)
13426 || !ISA_HAS_64BIT_REGS (mips_opts
.isa
));
13429 switch (file_mips_fp32
)
13433 /* No user specified float register size.
13434 ??? GAS treats single-float processors as though they had 64-bit
13435 float registers (although it complains when double-precision
13436 instructions are used). As things stand, saying they have 32-bit
13437 registers would lead to spurious "register must be even" messages.
13438 So here we assume float registers are never smaller than the
13440 if (file_mips_gp32
== 0)
13441 /* 64-bit integer registers implies 64-bit float registers. */
13442 file_mips_fp32
= 0;
13443 else if ((mips_opts
.ase
& FP64_ASES
)
13444 && ISA_HAS_64BIT_FPRS (mips_opts
.isa
))
13445 /* -mips3d and -mdmx imply 64-bit float registers, if possible. */
13446 file_mips_fp32
= 0;
13448 /* 32-bit float registers. */
13449 file_mips_fp32
= 1;
13452 /* The user specified the size of the float registers. Check if it
13453 agrees with the ABI and ISA. */
13455 if (!ISA_HAS_64BIT_FPRS (mips_opts
.isa
))
13456 as_bad (_("-mfp64 used with a 32-bit fpu"));
13457 else if (ABI_NEEDS_32BIT_REGS (mips_abi
)
13458 && !ISA_HAS_MXHC1 (mips_opts
.isa
))
13459 as_warn (_("-mfp64 used with a 32-bit ABI"));
13462 if (ABI_NEEDS_64BIT_REGS (mips_abi
))
13463 as_warn (_("-mfp32 used with a 64-bit ABI"));
13467 /* End of GCC-shared inference code. */
13469 /* This flag is set when we have a 64-bit capable CPU but use only
13470 32-bit wide registers. Note that EABI does not use it. */
13471 if (ISA_HAS_64BIT_REGS (mips_opts
.isa
)
13472 && ((mips_abi
== NO_ABI
&& file_mips_gp32
== 1)
13473 || mips_abi
== O32_ABI
))
13474 mips_32bitmode
= 1;
13476 if (mips_opts
.isa
== ISA_MIPS1
&& mips_trap
)
13477 as_bad (_("trap exception not supported at ISA 1"));
13479 /* If the selected architecture includes support for ASEs, enable
13480 generation of code for them. */
13481 if (mips_opts
.mips16
== -1)
13482 mips_opts
.mips16
= (CPU_HAS_MIPS16 (file_mips_arch
)) ? 1 : 0;
13483 if (mips_opts
.micromips
== -1)
13484 mips_opts
.micromips
= (CPU_HAS_MICROMIPS (file_mips_arch
)) ? 1 : 0;
13486 /* MIPS3D and MDMX require 64-bit FPRs, so -mfp32 should stop those
13487 ASEs from being selected implicitly. */
13488 if (file_mips_fp32
== 1)
13489 file_ase_explicit
|= ASE_MIPS3D
| ASE_MDMX
;
13491 /* If the user didn't explicitly select or deselect a particular ASE,
13492 use the default setting for the CPU. */
13493 mips_opts
.ase
|= (arch_info
->ase
& ~file_ase_explicit
);
13495 file_mips_isa
= mips_opts
.isa
;
13496 file_ase
= mips_opts
.ase
;
13497 mips_opts
.gp32
= file_mips_gp32
;
13498 mips_opts
.fp32
= file_mips_fp32
;
13499 mips_opts
.soft_float
= file_mips_soft_float
;
13500 mips_opts
.single_float
= file_mips_single_float
;
13502 mips_check_isa_supports_ases ();
13504 if (mips_flag_mdebug
< 0)
13505 mips_flag_mdebug
= 0;
13509 mips_init_after_args (void)
13511 /* initialize opcodes */
13512 bfd_mips_num_opcodes
= bfd_mips_num_builtin_opcodes
;
13513 mips_opcodes
= (struct mips_opcode
*) mips_builtin_opcodes
;
13517 md_pcrel_from (fixS
*fixP
)
13519 valueT addr
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
13520 switch (fixP
->fx_r_type
)
13522 case BFD_RELOC_MICROMIPS_7_PCREL_S1
:
13523 case BFD_RELOC_MICROMIPS_10_PCREL_S1
:
13524 /* Return the address of the delay slot. */
13527 case BFD_RELOC_MICROMIPS_16_PCREL_S1
:
13528 case BFD_RELOC_MICROMIPS_JMP
:
13529 case BFD_RELOC_16_PCREL_S2
:
13530 case BFD_RELOC_MIPS_JMP
:
13531 /* Return the address of the delay slot. */
13534 case BFD_RELOC_32_PCREL
:
13538 /* We have no relocation type for PC relative MIPS16 instructions. */
13539 if (fixP
->fx_addsy
&& S_GET_SEGMENT (fixP
->fx_addsy
) != now_seg
)
13540 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
13541 _("PC relative MIPS16 instruction references a different section"));
13546 /* This is called before the symbol table is processed. In order to
13547 work with gcc when using mips-tfile, we must keep all local labels.
13548 However, in other cases, we want to discard them. If we were
13549 called with -g, but we didn't see any debugging information, it may
13550 mean that gcc is smuggling debugging information through to
13551 mips-tfile, in which case we must generate all local labels. */
13554 mips_frob_file_before_adjust (void)
13556 #ifndef NO_ECOFF_DEBUGGING
13557 if (ECOFF_DEBUGGING
13559 && ! ecoff_debugging_seen
)
13560 flag_keep_locals
= 1;
13564 /* Sort any unmatched HI16 and GOT16 relocs so that they immediately precede
13565 the corresponding LO16 reloc. This is called before md_apply_fix and
13566 tc_gen_reloc. Unmatched relocs can only be generated by use of explicit
13567 relocation operators.
13569 For our purposes, a %lo() expression matches a %got() or %hi()
13572 (a) it refers to the same symbol; and
13573 (b) the offset applied in the %lo() expression is no lower than
13574 the offset applied in the %got() or %hi().
13576 (b) allows us to cope with code like:
13579 lh $4,%lo(foo+2)($4)
13581 ...which is legal on RELA targets, and has a well-defined behaviour
13582 if the user knows that adding 2 to "foo" will not induce a carry to
13585 When several %lo()s match a particular %got() or %hi(), we use the
13586 following rules to distinguish them:
13588 (1) %lo()s with smaller offsets are a better match than %lo()s with
13591 (2) %lo()s with no matching %got() or %hi() are better than those
13592 that already have a matching %got() or %hi().
13594 (3) later %lo()s are better than earlier %lo()s.
13596 These rules are applied in order.
13598 (1) means, among other things, that %lo()s with identical offsets are
13599 chosen if they exist.
13601 (2) means that we won't associate several high-part relocations with
13602 the same low-part relocation unless there's no alternative. Having
13603 several high parts for the same low part is a GNU extension; this rule
13604 allows careful users to avoid it.
13606 (3) is purely cosmetic. mips_hi_fixup_list is is in reverse order,
13607 with the last high-part relocation being at the front of the list.
13608 It therefore makes sense to choose the last matching low-part
13609 relocation, all other things being equal. It's also easier
13610 to code that way. */
13613 mips_frob_file (void)
13615 struct mips_hi_fixup
*l
;
13616 bfd_reloc_code_real_type looking_for_rtype
= BFD_RELOC_UNUSED
;
13618 for (l
= mips_hi_fixup_list
; l
!= NULL
; l
= l
->next
)
13620 segment_info_type
*seginfo
;
13621 bfd_boolean matched_lo_p
;
13622 fixS
**hi_pos
, **lo_pos
, **pos
;
13624 gas_assert (reloc_needs_lo_p (l
->fixp
->fx_r_type
));
13626 /* If a GOT16 relocation turns out to be against a global symbol,
13627 there isn't supposed to be a matching LO. Ignore %gots against
13628 constants; we'll report an error for those later. */
13629 if (got16_reloc_p (l
->fixp
->fx_r_type
)
13630 && !(l
->fixp
->fx_addsy
13631 && pic_need_relax (l
->fixp
->fx_addsy
, l
->seg
)))
13634 /* Check quickly whether the next fixup happens to be a matching %lo. */
13635 if (fixup_has_matching_lo_p (l
->fixp
))
13638 seginfo
= seg_info (l
->seg
);
13640 /* Set HI_POS to the position of this relocation in the chain.
13641 Set LO_POS to the position of the chosen low-part relocation.
13642 MATCHED_LO_P is true on entry to the loop if *POS is a low-part
13643 relocation that matches an immediately-preceding high-part
13647 matched_lo_p
= FALSE
;
13648 looking_for_rtype
= matching_lo_reloc (l
->fixp
->fx_r_type
);
13650 for (pos
= &seginfo
->fix_root
; *pos
!= NULL
; pos
= &(*pos
)->fx_next
)
13652 if (*pos
== l
->fixp
)
13655 if ((*pos
)->fx_r_type
== looking_for_rtype
13656 && symbol_same_p ((*pos
)->fx_addsy
, l
->fixp
->fx_addsy
)
13657 && (*pos
)->fx_offset
>= l
->fixp
->fx_offset
13659 || (*pos
)->fx_offset
< (*lo_pos
)->fx_offset
13661 && (*pos
)->fx_offset
== (*lo_pos
)->fx_offset
)))
13664 matched_lo_p
= (reloc_needs_lo_p ((*pos
)->fx_r_type
)
13665 && fixup_has_matching_lo_p (*pos
));
13668 /* If we found a match, remove the high-part relocation from its
13669 current position and insert it before the low-part relocation.
13670 Make the offsets match so that fixup_has_matching_lo_p()
13673 We don't warn about unmatched high-part relocations since some
13674 versions of gcc have been known to emit dead "lui ...%hi(...)"
13676 if (lo_pos
!= NULL
)
13678 l
->fixp
->fx_offset
= (*lo_pos
)->fx_offset
;
13679 if (l
->fixp
->fx_next
!= *lo_pos
)
13681 *hi_pos
= l
->fixp
->fx_next
;
13682 l
->fixp
->fx_next
= *lo_pos
;
13690 mips_force_relocation (fixS
*fixp
)
13692 if (generic_force_reloc (fixp
))
13695 /* We want to keep BFD_RELOC_MICROMIPS_*_PCREL_S1 relocation,
13696 so that the linker relaxation can update targets. */
13697 if (fixp
->fx_r_type
== BFD_RELOC_MICROMIPS_7_PCREL_S1
13698 || fixp
->fx_r_type
== BFD_RELOC_MICROMIPS_10_PCREL_S1
13699 || fixp
->fx_r_type
== BFD_RELOC_MICROMIPS_16_PCREL_S1
)
13705 /* Read the instruction associated with RELOC from BUF. */
13707 static unsigned int
13708 read_reloc_insn (char *buf
, bfd_reloc_code_real_type reloc
)
13710 if (mips16_reloc_p (reloc
) || micromips_reloc_p (reloc
))
13711 return read_compressed_insn (buf
, 4);
13713 return read_insn (buf
);
13716 /* Write instruction INSN to BUF, given that it has been relocated
13720 write_reloc_insn (char *buf
, bfd_reloc_code_real_type reloc
,
13721 unsigned long insn
)
13723 if (mips16_reloc_p (reloc
) || micromips_reloc_p (reloc
))
13724 write_compressed_insn (buf
, insn
, 4);
13726 write_insn (buf
, insn
);
13729 /* Apply a fixup to the object file. */
13732 md_apply_fix (fixS
*fixP
, valueT
*valP
, segT seg ATTRIBUTE_UNUSED
)
13735 unsigned long insn
;
13736 reloc_howto_type
*howto
;
13738 /* We ignore generic BFD relocations we don't know about. */
13739 howto
= bfd_reloc_type_lookup (stdoutput
, fixP
->fx_r_type
);
13743 gas_assert (fixP
->fx_size
== 2
13744 || fixP
->fx_size
== 4
13745 || fixP
->fx_r_type
== BFD_RELOC_16
13746 || fixP
->fx_r_type
== BFD_RELOC_64
13747 || fixP
->fx_r_type
== BFD_RELOC_CTOR
13748 || fixP
->fx_r_type
== BFD_RELOC_MIPS_SUB
13749 || fixP
->fx_r_type
== BFD_RELOC_MICROMIPS_SUB
13750 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
13751 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
13752 || fixP
->fx_r_type
== BFD_RELOC_MIPS_TLS_DTPREL64
);
13754 buf
= fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
13756 gas_assert (!fixP
->fx_pcrel
|| fixP
->fx_r_type
== BFD_RELOC_16_PCREL_S2
13757 || fixP
->fx_r_type
== BFD_RELOC_MICROMIPS_7_PCREL_S1
13758 || fixP
->fx_r_type
== BFD_RELOC_MICROMIPS_10_PCREL_S1
13759 || fixP
->fx_r_type
== BFD_RELOC_MICROMIPS_16_PCREL_S1
13760 || fixP
->fx_r_type
== BFD_RELOC_32_PCREL
);
13762 /* Don't treat parts of a composite relocation as done. There are two
13765 (1) The second and third parts will be against 0 (RSS_UNDEF) but
13766 should nevertheless be emitted if the first part is.
13768 (2) In normal usage, composite relocations are never assembly-time
13769 constants. The easiest way of dealing with the pathological
13770 exceptions is to generate a relocation against STN_UNDEF and
13771 leave everything up to the linker. */
13772 if (fixP
->fx_addsy
== NULL
&& !fixP
->fx_pcrel
&& fixP
->fx_tcbit
== 0)
13775 switch (fixP
->fx_r_type
)
13777 case BFD_RELOC_MIPS_TLS_GD
:
13778 case BFD_RELOC_MIPS_TLS_LDM
:
13779 case BFD_RELOC_MIPS_TLS_DTPREL32
:
13780 case BFD_RELOC_MIPS_TLS_DTPREL64
:
13781 case BFD_RELOC_MIPS_TLS_DTPREL_HI16
:
13782 case BFD_RELOC_MIPS_TLS_DTPREL_LO16
:
13783 case BFD_RELOC_MIPS_TLS_GOTTPREL
:
13784 case BFD_RELOC_MIPS_TLS_TPREL32
:
13785 case BFD_RELOC_MIPS_TLS_TPREL64
:
13786 case BFD_RELOC_MIPS_TLS_TPREL_HI16
:
13787 case BFD_RELOC_MIPS_TLS_TPREL_LO16
:
13788 case BFD_RELOC_MICROMIPS_TLS_GD
:
13789 case BFD_RELOC_MICROMIPS_TLS_LDM
:
13790 case BFD_RELOC_MICROMIPS_TLS_DTPREL_HI16
:
13791 case BFD_RELOC_MICROMIPS_TLS_DTPREL_LO16
:
13792 case BFD_RELOC_MICROMIPS_TLS_GOTTPREL
:
13793 case BFD_RELOC_MICROMIPS_TLS_TPREL_HI16
:
13794 case BFD_RELOC_MICROMIPS_TLS_TPREL_LO16
:
13795 case BFD_RELOC_MIPS16_TLS_GD
:
13796 case BFD_RELOC_MIPS16_TLS_LDM
:
13797 case BFD_RELOC_MIPS16_TLS_DTPREL_HI16
:
13798 case BFD_RELOC_MIPS16_TLS_DTPREL_LO16
:
13799 case BFD_RELOC_MIPS16_TLS_GOTTPREL
:
13800 case BFD_RELOC_MIPS16_TLS_TPREL_HI16
:
13801 case BFD_RELOC_MIPS16_TLS_TPREL_LO16
:
13802 if (!fixP
->fx_addsy
)
13804 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
13805 _("TLS relocation against a constant"));
13808 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
13811 case BFD_RELOC_MIPS_JMP
:
13812 case BFD_RELOC_MIPS_SHIFT5
:
13813 case BFD_RELOC_MIPS_SHIFT6
:
13814 case BFD_RELOC_MIPS_GOT_DISP
:
13815 case BFD_RELOC_MIPS_GOT_PAGE
:
13816 case BFD_RELOC_MIPS_GOT_OFST
:
13817 case BFD_RELOC_MIPS_SUB
:
13818 case BFD_RELOC_MIPS_INSERT_A
:
13819 case BFD_RELOC_MIPS_INSERT_B
:
13820 case BFD_RELOC_MIPS_DELETE
:
13821 case BFD_RELOC_MIPS_HIGHEST
:
13822 case BFD_RELOC_MIPS_HIGHER
:
13823 case BFD_RELOC_MIPS_SCN_DISP
:
13824 case BFD_RELOC_MIPS_REL16
:
13825 case BFD_RELOC_MIPS_RELGOT
:
13826 case BFD_RELOC_MIPS_JALR
:
13827 case BFD_RELOC_HI16
:
13828 case BFD_RELOC_HI16_S
:
13829 case BFD_RELOC_LO16
:
13830 case BFD_RELOC_GPREL16
:
13831 case BFD_RELOC_MIPS_LITERAL
:
13832 case BFD_RELOC_MIPS_CALL16
:
13833 case BFD_RELOC_MIPS_GOT16
:
13834 case BFD_RELOC_GPREL32
:
13835 case BFD_RELOC_MIPS_GOT_HI16
:
13836 case BFD_RELOC_MIPS_GOT_LO16
:
13837 case BFD_RELOC_MIPS_CALL_HI16
:
13838 case BFD_RELOC_MIPS_CALL_LO16
:
13839 case BFD_RELOC_MIPS16_GPREL
:
13840 case BFD_RELOC_MIPS16_GOT16
:
13841 case BFD_RELOC_MIPS16_CALL16
:
13842 case BFD_RELOC_MIPS16_HI16
:
13843 case BFD_RELOC_MIPS16_HI16_S
:
13844 case BFD_RELOC_MIPS16_LO16
:
13845 case BFD_RELOC_MIPS16_JMP
:
13846 case BFD_RELOC_MICROMIPS_JMP
:
13847 case BFD_RELOC_MICROMIPS_GOT_DISP
:
13848 case BFD_RELOC_MICROMIPS_GOT_PAGE
:
13849 case BFD_RELOC_MICROMIPS_GOT_OFST
:
13850 case BFD_RELOC_MICROMIPS_SUB
:
13851 case BFD_RELOC_MICROMIPS_HIGHEST
:
13852 case BFD_RELOC_MICROMIPS_HIGHER
:
13853 case BFD_RELOC_MICROMIPS_SCN_DISP
:
13854 case BFD_RELOC_MICROMIPS_JALR
:
13855 case BFD_RELOC_MICROMIPS_HI16
:
13856 case BFD_RELOC_MICROMIPS_HI16_S
:
13857 case BFD_RELOC_MICROMIPS_LO16
:
13858 case BFD_RELOC_MICROMIPS_GPREL16
:
13859 case BFD_RELOC_MICROMIPS_LITERAL
:
13860 case BFD_RELOC_MICROMIPS_CALL16
:
13861 case BFD_RELOC_MICROMIPS_GOT16
:
13862 case BFD_RELOC_MICROMIPS_GOT_HI16
:
13863 case BFD_RELOC_MICROMIPS_GOT_LO16
:
13864 case BFD_RELOC_MICROMIPS_CALL_HI16
:
13865 case BFD_RELOC_MICROMIPS_CALL_LO16
:
13866 case BFD_RELOC_MIPS_EH
:
13871 if (calculate_reloc (fixP
->fx_r_type
, *valP
, &value
))
13873 insn
= read_reloc_insn (buf
, fixP
->fx_r_type
);
13874 if (mips16_reloc_p (fixP
->fx_r_type
))
13875 insn
|= mips16_immed_extend (value
, 16);
13877 insn
|= (value
& 0xffff);
13878 write_reloc_insn (buf
, fixP
->fx_r_type
, insn
);
13881 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
13882 _("Unsupported constant in relocation"));
13887 /* This is handled like BFD_RELOC_32, but we output a sign
13888 extended value if we are only 32 bits. */
13891 if (8 <= sizeof (valueT
))
13892 md_number_to_chars (buf
, *valP
, 8);
13897 if ((*valP
& 0x80000000) != 0)
13901 md_number_to_chars (buf
+ (target_big_endian
? 4 : 0), *valP
, 4);
13902 md_number_to_chars (buf
+ (target_big_endian
? 0 : 4), hiv
, 4);
13907 case BFD_RELOC_RVA
:
13909 case BFD_RELOC_32_PCREL
:
13911 /* If we are deleting this reloc entry, we must fill in the
13912 value now. This can happen if we have a .word which is not
13913 resolved when it appears but is later defined. */
13915 md_number_to_chars (buf
, *valP
, fixP
->fx_size
);
13918 case BFD_RELOC_16_PCREL_S2
:
13919 if ((*valP
& 0x3) != 0)
13920 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
13921 _("Branch to misaligned address (%lx)"), (long) *valP
);
13923 /* We need to save the bits in the instruction since fixup_segment()
13924 might be deleting the relocation entry (i.e., a branch within
13925 the current segment). */
13926 if (! fixP
->fx_done
)
13929 /* Update old instruction data. */
13930 insn
= read_insn (buf
);
13932 if (*valP
+ 0x20000 <= 0x3ffff)
13934 insn
|= (*valP
>> 2) & 0xffff;
13935 write_insn (buf
, insn
);
13937 else if (mips_pic
== NO_PIC
13939 && fixP
->fx_frag
->fr_address
>= text_section
->vma
13940 && (fixP
->fx_frag
->fr_address
13941 < text_section
->vma
+ bfd_get_section_size (text_section
))
13942 && ((insn
& 0xffff0000) == 0x10000000 /* beq $0,$0 */
13943 || (insn
& 0xffff0000) == 0x04010000 /* bgez $0 */
13944 || (insn
& 0xffff0000) == 0x04110000)) /* bgezal $0 */
13946 /* The branch offset is too large. If this is an
13947 unconditional branch, and we are not generating PIC code,
13948 we can convert it to an absolute jump instruction. */
13949 if ((insn
& 0xffff0000) == 0x04110000) /* bgezal $0 */
13950 insn
= 0x0c000000; /* jal */
13952 insn
= 0x08000000; /* j */
13953 fixP
->fx_r_type
= BFD_RELOC_MIPS_JMP
;
13955 fixP
->fx_addsy
= section_symbol (text_section
);
13956 *valP
+= md_pcrel_from (fixP
);
13957 write_insn (buf
, insn
);
13961 /* If we got here, we have branch-relaxation disabled,
13962 and there's nothing we can do to fix this instruction
13963 without turning it into a longer sequence. */
13964 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
13965 _("Branch out of range"));
13969 case BFD_RELOC_MICROMIPS_7_PCREL_S1
:
13970 case BFD_RELOC_MICROMIPS_10_PCREL_S1
:
13971 case BFD_RELOC_MICROMIPS_16_PCREL_S1
:
13972 /* We adjust the offset back to even. */
13973 if ((*valP
& 0x1) != 0)
13976 if (! fixP
->fx_done
)
13979 /* Should never visit here, because we keep the relocation. */
13983 case BFD_RELOC_VTABLE_INHERIT
:
13986 && !S_IS_DEFINED (fixP
->fx_addsy
)
13987 && !S_IS_WEAK (fixP
->fx_addsy
))
13988 S_SET_WEAK (fixP
->fx_addsy
);
13991 case BFD_RELOC_VTABLE_ENTRY
:
13999 /* Remember value for tc_gen_reloc. */
14000 fixP
->fx_addnumber
= *valP
;
14010 name
= input_line_pointer
;
14011 c
= get_symbol_end ();
14012 p
= (symbolS
*) symbol_find_or_make (name
);
14013 *input_line_pointer
= c
;
14017 /* Align the current frag to a given power of two. If a particular
14018 fill byte should be used, FILL points to an integer that contains
14019 that byte, otherwise FILL is null.
14021 This function used to have the comment:
14023 The MIPS assembler also automatically adjusts any preceding label.
14025 The implementation therefore applied the adjustment to a maximum of
14026 one label. However, other label adjustments are applied to batches
14027 of labels, and adjusting just one caused problems when new labels
14028 were added for the sake of debugging or unwind information.
14029 We therefore adjust all preceding labels (given as LABELS) instead. */
14032 mips_align (int to
, int *fill
, struct insn_label_list
*labels
)
14034 mips_emit_delays ();
14035 mips_record_compressed_mode ();
14036 if (fill
== NULL
&& subseg_text_p (now_seg
))
14037 frag_align_code (to
, 0);
14039 frag_align (to
, fill
? *fill
: 0, 0);
14040 record_alignment (now_seg
, to
);
14041 mips_move_labels (labels
, FALSE
);
14044 /* Align to a given power of two. .align 0 turns off the automatic
14045 alignment used by the data creating pseudo-ops. */
14048 s_align (int x ATTRIBUTE_UNUSED
)
14050 int temp
, fill_value
, *fill_ptr
;
14051 long max_alignment
= 28;
14053 /* o Note that the assembler pulls down any immediately preceding label
14054 to the aligned address.
14055 o It's not documented but auto alignment is reinstated by
14056 a .align pseudo instruction.
14057 o Note also that after auto alignment is turned off the mips assembler
14058 issues an error on attempt to assemble an improperly aligned data item.
14061 temp
= get_absolute_expression ();
14062 if (temp
> max_alignment
)
14063 as_bad (_("Alignment too large: %d. assumed."), temp
= max_alignment
);
14066 as_warn (_("Alignment negative: 0 assumed."));
14069 if (*input_line_pointer
== ',')
14071 ++input_line_pointer
;
14072 fill_value
= get_absolute_expression ();
14073 fill_ptr
= &fill_value
;
14079 segment_info_type
*si
= seg_info (now_seg
);
14080 struct insn_label_list
*l
= si
->label_list
;
14081 /* Auto alignment should be switched on by next section change. */
14083 mips_align (temp
, fill_ptr
, l
);
14090 demand_empty_rest_of_line ();
14094 s_change_sec (int sec
)
14098 /* The ELF backend needs to know that we are changing sections, so
14099 that .previous works correctly. We could do something like check
14100 for an obj_section_change_hook macro, but that might be confusing
14101 as it would not be appropriate to use it in the section changing
14102 functions in read.c, since obj-elf.c intercepts those. FIXME:
14103 This should be cleaner, somehow. */
14104 obj_elf_section_change_hook ();
14106 mips_emit_delays ();
14117 subseg_set (bss_section
, (subsegT
) get_absolute_expression ());
14118 demand_empty_rest_of_line ();
14122 seg
= subseg_new (RDATA_SECTION_NAME
,
14123 (subsegT
) get_absolute_expression ());
14124 bfd_set_section_flags (stdoutput
, seg
, (SEC_ALLOC
| SEC_LOAD
14125 | SEC_READONLY
| SEC_RELOC
14127 if (strncmp (TARGET_OS
, "elf", 3) != 0)
14128 record_alignment (seg
, 4);
14129 demand_empty_rest_of_line ();
14133 seg
= subseg_new (".sdata", (subsegT
) get_absolute_expression ());
14134 bfd_set_section_flags (stdoutput
, seg
,
14135 SEC_ALLOC
| SEC_LOAD
| SEC_RELOC
| SEC_DATA
);
14136 if (strncmp (TARGET_OS
, "elf", 3) != 0)
14137 record_alignment (seg
, 4);
14138 demand_empty_rest_of_line ();
14142 seg
= subseg_new (".sbss", (subsegT
) get_absolute_expression ());
14143 bfd_set_section_flags (stdoutput
, seg
, SEC_ALLOC
);
14144 if (strncmp (TARGET_OS
, "elf", 3) != 0)
14145 record_alignment (seg
, 4);
14146 demand_empty_rest_of_line ();
14154 s_change_section (int ignore ATTRIBUTE_UNUSED
)
14156 char *section_name
;
14161 int section_entry_size
;
14162 int section_alignment
;
14164 section_name
= input_line_pointer
;
14165 c
= get_symbol_end ();
14167 next_c
= *(input_line_pointer
+ 1);
14169 /* Do we have .section Name<,"flags">? */
14170 if (c
!= ',' || (c
== ',' && next_c
== '"'))
14172 /* just after name is now '\0'. */
14173 *input_line_pointer
= c
;
14174 input_line_pointer
= section_name
;
14175 obj_elf_section (ignore
);
14178 input_line_pointer
++;
14180 /* Do we have .section Name<,type><,flag><,entry_size><,alignment> */
14182 section_type
= get_absolute_expression ();
14185 if (*input_line_pointer
++ == ',')
14186 section_flag
= get_absolute_expression ();
14189 if (*input_line_pointer
++ == ',')
14190 section_entry_size
= get_absolute_expression ();
14192 section_entry_size
= 0;
14193 if (*input_line_pointer
++ == ',')
14194 section_alignment
= get_absolute_expression ();
14196 section_alignment
= 0;
14197 /* FIXME: really ignore? */
14198 (void) section_alignment
;
14200 section_name
= xstrdup (section_name
);
14202 /* When using the generic form of .section (as implemented by obj-elf.c),
14203 there's no way to set the section type to SHT_MIPS_DWARF. Users have
14204 traditionally had to fall back on the more common @progbits instead.
14206 There's nothing really harmful in this, since bfd will correct
14207 SHT_PROGBITS to SHT_MIPS_DWARF before writing out the file. But it
14208 means that, for backwards compatibility, the special_section entries
14209 for dwarf sections must use SHT_PROGBITS rather than SHT_MIPS_DWARF.
14211 Even so, we shouldn't force users of the MIPS .section syntax to
14212 incorrectly label the sections as SHT_PROGBITS. The best compromise
14213 seems to be to map SHT_MIPS_DWARF to SHT_PROGBITS before calling the
14214 generic type-checking code. */
14215 if (section_type
== SHT_MIPS_DWARF
)
14216 section_type
= SHT_PROGBITS
;
14218 obj_elf_change_section (section_name
, section_type
, section_flag
,
14219 section_entry_size
, 0, 0, 0);
14221 if (now_seg
->name
!= section_name
)
14222 free (section_name
);
14226 mips_enable_auto_align (void)
14232 s_cons (int log_size
)
14234 segment_info_type
*si
= seg_info (now_seg
);
14235 struct insn_label_list
*l
= si
->label_list
;
14237 mips_emit_delays ();
14238 if (log_size
> 0 && auto_align
)
14239 mips_align (log_size
, 0, l
);
14240 cons (1 << log_size
);
14241 mips_clear_insn_labels ();
14245 s_float_cons (int type
)
14247 segment_info_type
*si
= seg_info (now_seg
);
14248 struct insn_label_list
*l
= si
->label_list
;
14250 mips_emit_delays ();
14255 mips_align (3, 0, l
);
14257 mips_align (2, 0, l
);
14261 mips_clear_insn_labels ();
14264 /* Handle .globl. We need to override it because on Irix 5 you are
14267 where foo is an undefined symbol, to mean that foo should be
14268 considered to be the address of a function. */
14271 s_mips_globl (int x ATTRIBUTE_UNUSED
)
14280 name
= input_line_pointer
;
14281 c
= get_symbol_end ();
14282 symbolP
= symbol_find_or_make (name
);
14283 S_SET_EXTERNAL (symbolP
);
14285 *input_line_pointer
= c
;
14286 SKIP_WHITESPACE ();
14288 /* On Irix 5, every global symbol that is not explicitly labelled as
14289 being a function is apparently labelled as being an object. */
14292 if (!is_end_of_line
[(unsigned char) *input_line_pointer
]
14293 && (*input_line_pointer
!= ','))
14298 secname
= input_line_pointer
;
14299 c
= get_symbol_end ();
14300 sec
= bfd_get_section_by_name (stdoutput
, secname
);
14302 as_bad (_("%s: no such section"), secname
);
14303 *input_line_pointer
= c
;
14305 if (sec
!= NULL
&& (sec
->flags
& SEC_CODE
) != 0)
14306 flag
= BSF_FUNCTION
;
14309 symbol_get_bfdsym (symbolP
)->flags
|= flag
;
14311 c
= *input_line_pointer
;
14314 input_line_pointer
++;
14315 SKIP_WHITESPACE ();
14316 if (is_end_of_line
[(unsigned char) *input_line_pointer
])
14322 demand_empty_rest_of_line ();
14326 s_option (int x ATTRIBUTE_UNUSED
)
14331 opt
= input_line_pointer
;
14332 c
= get_symbol_end ();
14336 /* FIXME: What does this mean? */
14338 else if (strncmp (opt
, "pic", 3) == 0)
14342 i
= atoi (opt
+ 3);
14347 mips_pic
= SVR4_PIC
;
14348 mips_abicalls
= TRUE
;
14351 as_bad (_(".option pic%d not supported"), i
);
14353 if (mips_pic
== SVR4_PIC
)
14355 if (g_switch_seen
&& g_switch_value
!= 0)
14356 as_warn (_("-G may not be used with SVR4 PIC code"));
14357 g_switch_value
= 0;
14358 bfd_set_gp_size (stdoutput
, 0);
14362 as_warn (_("Unrecognized option \"%s\""), opt
);
14364 *input_line_pointer
= c
;
14365 demand_empty_rest_of_line ();
14368 /* This structure is used to hold a stack of .set values. */
14370 struct mips_option_stack
14372 struct mips_option_stack
*next
;
14373 struct mips_set_options options
;
14376 static struct mips_option_stack
*mips_opts_stack
;
14378 /* Handle the .set pseudo-op. */
14381 s_mipsset (int x ATTRIBUTE_UNUSED
)
14383 char *name
= input_line_pointer
, ch
;
14384 const struct mips_ase
*ase
;
14386 while (!is_end_of_line
[(unsigned char) *input_line_pointer
])
14387 ++input_line_pointer
;
14388 ch
= *input_line_pointer
;
14389 *input_line_pointer
= '\0';
14391 if (strcmp (name
, "reorder") == 0)
14393 if (mips_opts
.noreorder
)
14396 else if (strcmp (name
, "noreorder") == 0)
14398 if (!mips_opts
.noreorder
)
14399 start_noreorder ();
14401 else if (strncmp (name
, "at=", 3) == 0)
14403 char *s
= name
+ 3;
14405 if (!reg_lookup (&s
, RTYPE_NUM
| RTYPE_GP
, &mips_opts
.at
))
14406 as_bad (_("Unrecognized register name `%s'"), s
);
14408 else if (strcmp (name
, "at") == 0)
14410 mips_opts
.at
= ATREG
;
14412 else if (strcmp (name
, "noat") == 0)
14414 mips_opts
.at
= ZERO
;
14416 else if (strcmp (name
, "macro") == 0)
14418 mips_opts
.warn_about_macros
= 0;
14420 else if (strcmp (name
, "nomacro") == 0)
14422 if (mips_opts
.noreorder
== 0)
14423 as_bad (_("`noreorder' must be set before `nomacro'"));
14424 mips_opts
.warn_about_macros
= 1;
14426 else if (strcmp (name
, "move") == 0 || strcmp (name
, "novolatile") == 0)
14428 mips_opts
.nomove
= 0;
14430 else if (strcmp (name
, "nomove") == 0 || strcmp (name
, "volatile") == 0)
14432 mips_opts
.nomove
= 1;
14434 else if (strcmp (name
, "bopt") == 0)
14436 mips_opts
.nobopt
= 0;
14438 else if (strcmp (name
, "nobopt") == 0)
14440 mips_opts
.nobopt
= 1;
14442 else if (strcmp (name
, "gp=default") == 0)
14443 mips_opts
.gp32
= file_mips_gp32
;
14444 else if (strcmp (name
, "gp=32") == 0)
14445 mips_opts
.gp32
= 1;
14446 else if (strcmp (name
, "gp=64") == 0)
14448 if (!ISA_HAS_64BIT_REGS (mips_opts
.isa
))
14449 as_warn (_("%s isa does not support 64-bit registers"),
14450 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
14451 mips_opts
.gp32
= 0;
14453 else if (strcmp (name
, "fp=default") == 0)
14454 mips_opts
.fp32
= file_mips_fp32
;
14455 else if (strcmp (name
, "fp=32") == 0)
14456 mips_opts
.fp32
= 1;
14457 else if (strcmp (name
, "fp=64") == 0)
14459 if (!ISA_HAS_64BIT_FPRS (mips_opts
.isa
))
14460 as_warn (_("%s isa does not support 64-bit floating point registers"),
14461 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
14462 mips_opts
.fp32
= 0;
14464 else if (strcmp (name
, "softfloat") == 0)
14465 mips_opts
.soft_float
= 1;
14466 else if (strcmp (name
, "hardfloat") == 0)
14467 mips_opts
.soft_float
= 0;
14468 else if (strcmp (name
, "singlefloat") == 0)
14469 mips_opts
.single_float
= 1;
14470 else if (strcmp (name
, "doublefloat") == 0)
14471 mips_opts
.single_float
= 0;
14472 else if (strcmp (name
, "mips16") == 0
14473 || strcmp (name
, "MIPS-16") == 0)
14475 if (mips_opts
.micromips
== 1)
14476 as_fatal (_("`mips16' cannot be used with `micromips'"));
14477 mips_opts
.mips16
= 1;
14479 else if (strcmp (name
, "nomips16") == 0
14480 || strcmp (name
, "noMIPS-16") == 0)
14481 mips_opts
.mips16
= 0;
14482 else if (strcmp (name
, "micromips") == 0)
14484 if (mips_opts
.mips16
== 1)
14485 as_fatal (_("`micromips' cannot be used with `mips16'"));
14486 mips_opts
.micromips
= 1;
14488 else if (strcmp (name
, "nomicromips") == 0)
14489 mips_opts
.micromips
= 0;
14490 else if (name
[0] == 'n'
14492 && (ase
= mips_lookup_ase (name
+ 2)))
14493 mips_set_ase (ase
, FALSE
);
14494 else if ((ase
= mips_lookup_ase (name
)))
14495 mips_set_ase (ase
, TRUE
);
14496 else if (strncmp (name
, "mips", 4) == 0 || strncmp (name
, "arch=", 5) == 0)
14500 /* Permit the user to change the ISA and architecture on the fly.
14501 Needless to say, misuse can cause serious problems. */
14502 if (strcmp (name
, "mips0") == 0 || strcmp (name
, "arch=default") == 0)
14505 mips_opts
.isa
= file_mips_isa
;
14506 mips_opts
.arch
= file_mips_arch
;
14508 else if (strncmp (name
, "arch=", 5) == 0)
14510 const struct mips_cpu_info
*p
;
14512 p
= mips_parse_cpu("internal use", name
+ 5);
14514 as_bad (_("unknown architecture %s"), name
+ 5);
14517 mips_opts
.arch
= p
->cpu
;
14518 mips_opts
.isa
= p
->isa
;
14521 else if (strncmp (name
, "mips", 4) == 0)
14523 const struct mips_cpu_info
*p
;
14525 p
= mips_parse_cpu("internal use", name
);
14527 as_bad (_("unknown ISA level %s"), name
+ 4);
14530 mips_opts
.arch
= p
->cpu
;
14531 mips_opts
.isa
= p
->isa
;
14535 as_bad (_("unknown ISA or architecture %s"), name
);
14537 switch (mips_opts
.isa
)
14545 mips_opts
.gp32
= 1;
14546 mips_opts
.fp32
= 1;
14553 mips_opts
.gp32
= 0;
14554 if (mips_opts
.arch
== CPU_R5900
)
14556 mips_opts
.fp32
= 1;
14560 mips_opts
.fp32
= 0;
14564 as_bad (_("unknown ISA level %s"), name
+ 4);
14569 mips_opts
.gp32
= file_mips_gp32
;
14570 mips_opts
.fp32
= file_mips_fp32
;
14573 else if (strcmp (name
, "autoextend") == 0)
14574 mips_opts
.noautoextend
= 0;
14575 else if (strcmp (name
, "noautoextend") == 0)
14576 mips_opts
.noautoextend
= 1;
14577 else if (strcmp (name
, "insn32") == 0)
14578 mips_opts
.insn32
= TRUE
;
14579 else if (strcmp (name
, "noinsn32") == 0)
14580 mips_opts
.insn32
= FALSE
;
14581 else if (strcmp (name
, "push") == 0)
14583 struct mips_option_stack
*s
;
14585 s
= (struct mips_option_stack
*) xmalloc (sizeof *s
);
14586 s
->next
= mips_opts_stack
;
14587 s
->options
= mips_opts
;
14588 mips_opts_stack
= s
;
14590 else if (strcmp (name
, "pop") == 0)
14592 struct mips_option_stack
*s
;
14594 s
= mips_opts_stack
;
14596 as_bad (_(".set pop with no .set push"));
14599 /* If we're changing the reorder mode we need to handle
14600 delay slots correctly. */
14601 if (s
->options
.noreorder
&& ! mips_opts
.noreorder
)
14602 start_noreorder ();
14603 else if (! s
->options
.noreorder
&& mips_opts
.noreorder
)
14606 mips_opts
= s
->options
;
14607 mips_opts_stack
= s
->next
;
14611 else if (strcmp (name
, "sym32") == 0)
14612 mips_opts
.sym32
= TRUE
;
14613 else if (strcmp (name
, "nosym32") == 0)
14614 mips_opts
.sym32
= FALSE
;
14615 else if (strchr (name
, ','))
14617 /* Generic ".set" directive; use the generic handler. */
14618 *input_line_pointer
= ch
;
14619 input_line_pointer
= name
;
14625 as_warn (_("Tried to set unrecognized symbol: %s\n"), name
);
14627 mips_check_isa_supports_ases ();
14628 *input_line_pointer
= ch
;
14629 demand_empty_rest_of_line ();
14632 /* Handle the .abicalls pseudo-op. I believe this is equivalent to
14633 .option pic2. It means to generate SVR4 PIC calls. */
14636 s_abicalls (int ignore ATTRIBUTE_UNUSED
)
14638 mips_pic
= SVR4_PIC
;
14639 mips_abicalls
= TRUE
;
14641 if (g_switch_seen
&& g_switch_value
!= 0)
14642 as_warn (_("-G may not be used with SVR4 PIC code"));
14643 g_switch_value
= 0;
14645 bfd_set_gp_size (stdoutput
, 0);
14646 demand_empty_rest_of_line ();
14649 /* Handle the .cpload pseudo-op. This is used when generating SVR4
14650 PIC code. It sets the $gp register for the function based on the
14651 function address, which is in the register named in the argument.
14652 This uses a relocation against _gp_disp, which is handled specially
14653 by the linker. The result is:
14654 lui $gp,%hi(_gp_disp)
14655 addiu $gp,$gp,%lo(_gp_disp)
14656 addu $gp,$gp,.cpload argument
14657 The .cpload argument is normally $25 == $t9.
14659 The -mno-shared option changes this to:
14660 lui $gp,%hi(__gnu_local_gp)
14661 addiu $gp,$gp,%lo(__gnu_local_gp)
14662 and the argument is ignored. This saves an instruction, but the
14663 resulting code is not position independent; it uses an absolute
14664 address for __gnu_local_gp. Thus code assembled with -mno-shared
14665 can go into an ordinary executable, but not into a shared library. */
14668 s_cpload (int ignore ATTRIBUTE_UNUSED
)
14674 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
14675 .cpload is ignored. */
14676 if (mips_pic
!= SVR4_PIC
|| HAVE_NEWABI
)
14682 if (mips_opts
.mips16
)
14684 as_bad (_("%s not supported in MIPS16 mode"), ".cpload");
14685 ignore_rest_of_line ();
14689 /* .cpload should be in a .set noreorder section. */
14690 if (mips_opts
.noreorder
== 0)
14691 as_warn (_(".cpload not in noreorder section"));
14693 reg
= tc_get_register (0);
14695 /* If we need to produce a 64-bit address, we are better off using
14696 the default instruction sequence. */
14697 in_shared
= mips_in_shared
|| HAVE_64BIT_SYMBOLS
;
14699 ex
.X_op
= O_symbol
;
14700 ex
.X_add_symbol
= symbol_find_or_make (in_shared
? "_gp_disp" :
14702 ex
.X_op_symbol
= NULL
;
14703 ex
.X_add_number
= 0;
14705 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
14706 symbol_get_bfdsym (ex
.X_add_symbol
)->flags
|= BSF_OBJECT
;
14708 mips_mark_labels ();
14709 mips_assembling_insn
= TRUE
;
14712 macro_build_lui (&ex
, mips_gp_register
);
14713 macro_build (&ex
, "addiu", "t,r,j", mips_gp_register
,
14714 mips_gp_register
, BFD_RELOC_LO16
);
14716 macro_build (NULL
, "addu", "d,v,t", mips_gp_register
,
14717 mips_gp_register
, reg
);
14720 mips_assembling_insn
= FALSE
;
14721 demand_empty_rest_of_line ();
14724 /* Handle the .cpsetup pseudo-op defined for NewABI PIC code. The syntax is:
14725 .cpsetup $reg1, offset|$reg2, label
14727 If offset is given, this results in:
14728 sd $gp, offset($sp)
14729 lui $gp, %hi(%neg(%gp_rel(label)))
14730 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
14731 daddu $gp, $gp, $reg1
14733 If $reg2 is given, this results in:
14734 daddu $reg2, $gp, $0
14735 lui $gp, %hi(%neg(%gp_rel(label)))
14736 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
14737 daddu $gp, $gp, $reg1
14738 $reg1 is normally $25 == $t9.
14740 The -mno-shared option replaces the last three instructions with
14742 addiu $gp,$gp,%lo(_gp) */
14745 s_cpsetup (int ignore ATTRIBUTE_UNUSED
)
14747 expressionS ex_off
;
14748 expressionS ex_sym
;
14751 /* If we are not generating SVR4 PIC code, .cpsetup is ignored.
14752 We also need NewABI support. */
14753 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
14759 if (mips_opts
.mips16
)
14761 as_bad (_("%s not supported in MIPS16 mode"), ".cpsetup");
14762 ignore_rest_of_line ();
14766 reg1
= tc_get_register (0);
14767 SKIP_WHITESPACE ();
14768 if (*input_line_pointer
!= ',')
14770 as_bad (_("missing argument separator ',' for .cpsetup"));
14774 ++input_line_pointer
;
14775 SKIP_WHITESPACE ();
14776 if (*input_line_pointer
== '$')
14778 mips_cpreturn_register
= tc_get_register (0);
14779 mips_cpreturn_offset
= -1;
14783 mips_cpreturn_offset
= get_absolute_expression ();
14784 mips_cpreturn_register
= -1;
14786 SKIP_WHITESPACE ();
14787 if (*input_line_pointer
!= ',')
14789 as_bad (_("missing argument separator ',' for .cpsetup"));
14793 ++input_line_pointer
;
14794 SKIP_WHITESPACE ();
14795 expression (&ex_sym
);
14797 mips_mark_labels ();
14798 mips_assembling_insn
= TRUE
;
14801 if (mips_cpreturn_register
== -1)
14803 ex_off
.X_op
= O_constant
;
14804 ex_off
.X_add_symbol
= NULL
;
14805 ex_off
.X_op_symbol
= NULL
;
14806 ex_off
.X_add_number
= mips_cpreturn_offset
;
14808 macro_build (&ex_off
, "sd", "t,o(b)", mips_gp_register
,
14809 BFD_RELOC_LO16
, SP
);
14812 macro_build (NULL
, "daddu", "d,v,t", mips_cpreturn_register
,
14813 mips_gp_register
, 0);
14815 if (mips_in_shared
|| HAVE_64BIT_SYMBOLS
)
14817 macro_build (&ex_sym
, "lui", LUI_FMT
, mips_gp_register
,
14818 -1, BFD_RELOC_GPREL16
, BFD_RELOC_MIPS_SUB
,
14821 macro_build (&ex_sym
, "addiu", "t,r,j", mips_gp_register
,
14822 mips_gp_register
, -1, BFD_RELOC_GPREL16
,
14823 BFD_RELOC_MIPS_SUB
, BFD_RELOC_LO16
);
14825 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", mips_gp_register
,
14826 mips_gp_register
, reg1
);
14832 ex
.X_op
= O_symbol
;
14833 ex
.X_add_symbol
= symbol_find_or_make ("__gnu_local_gp");
14834 ex
.X_op_symbol
= NULL
;
14835 ex
.X_add_number
= 0;
14837 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
14838 symbol_get_bfdsym (ex
.X_add_symbol
)->flags
|= BSF_OBJECT
;
14840 macro_build_lui (&ex
, mips_gp_register
);
14841 macro_build (&ex
, "addiu", "t,r,j", mips_gp_register
,
14842 mips_gp_register
, BFD_RELOC_LO16
);
14847 mips_assembling_insn
= FALSE
;
14848 demand_empty_rest_of_line ();
14852 s_cplocal (int ignore ATTRIBUTE_UNUSED
)
14854 /* If we are not generating SVR4 PIC code, or if this is not NewABI code,
14855 .cplocal is ignored. */
14856 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
14862 if (mips_opts
.mips16
)
14864 as_bad (_("%s not supported in MIPS16 mode"), ".cplocal");
14865 ignore_rest_of_line ();
14869 mips_gp_register
= tc_get_register (0);
14870 demand_empty_rest_of_line ();
14873 /* Handle the .cprestore pseudo-op. This stores $gp into a given
14874 offset from $sp. The offset is remembered, and after making a PIC
14875 call $gp is restored from that location. */
14878 s_cprestore (int ignore ATTRIBUTE_UNUSED
)
14882 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
14883 .cprestore is ignored. */
14884 if (mips_pic
!= SVR4_PIC
|| HAVE_NEWABI
)
14890 if (mips_opts
.mips16
)
14892 as_bad (_("%s not supported in MIPS16 mode"), ".cprestore");
14893 ignore_rest_of_line ();
14897 mips_cprestore_offset
= get_absolute_expression ();
14898 mips_cprestore_valid
= 1;
14900 ex
.X_op
= O_constant
;
14901 ex
.X_add_symbol
= NULL
;
14902 ex
.X_op_symbol
= NULL
;
14903 ex
.X_add_number
= mips_cprestore_offset
;
14905 mips_mark_labels ();
14906 mips_assembling_insn
= TRUE
;
14909 macro_build_ldst_constoffset (&ex
, ADDRESS_STORE_INSN
, mips_gp_register
,
14910 SP
, HAVE_64BIT_ADDRESSES
);
14913 mips_assembling_insn
= FALSE
;
14914 demand_empty_rest_of_line ();
14917 /* Handle the .cpreturn pseudo-op defined for NewABI PIC code. If an offset
14918 was given in the preceding .cpsetup, it results in:
14919 ld $gp, offset($sp)
14921 If a register $reg2 was given there, it results in:
14922 daddu $gp, $reg2, $0 */
14925 s_cpreturn (int ignore ATTRIBUTE_UNUSED
)
14929 /* If we are not generating SVR4 PIC code, .cpreturn is ignored.
14930 We also need NewABI support. */
14931 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
14937 if (mips_opts
.mips16
)
14939 as_bad (_("%s not supported in MIPS16 mode"), ".cpreturn");
14940 ignore_rest_of_line ();
14944 mips_mark_labels ();
14945 mips_assembling_insn
= TRUE
;
14948 if (mips_cpreturn_register
== -1)
14950 ex
.X_op
= O_constant
;
14951 ex
.X_add_symbol
= NULL
;
14952 ex
.X_op_symbol
= NULL
;
14953 ex
.X_add_number
= mips_cpreturn_offset
;
14955 macro_build (&ex
, "ld", "t,o(b)", mips_gp_register
, BFD_RELOC_LO16
, SP
);
14958 macro_build (NULL
, "daddu", "d,v,t", mips_gp_register
,
14959 mips_cpreturn_register
, 0);
14962 mips_assembling_insn
= FALSE
;
14963 demand_empty_rest_of_line ();
14966 /* Handle a .dtprelword, .dtpreldword, .tprelword, or .tpreldword
14967 pseudo-op; DIRSTR says which. The pseudo-op generates a BYTES-size
14968 DTP- or TP-relative relocation of type RTYPE, for use in either DWARF
14969 debug information or MIPS16 TLS. */
14972 s_tls_rel_directive (const size_t bytes
, const char *dirstr
,
14973 bfd_reloc_code_real_type rtype
)
14980 if (ex
.X_op
!= O_symbol
)
14982 as_bad (_("Unsupported use of %s"), dirstr
);
14983 ignore_rest_of_line ();
14986 p
= frag_more (bytes
);
14987 md_number_to_chars (p
, 0, bytes
);
14988 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, bytes
, &ex
, FALSE
, rtype
);
14989 demand_empty_rest_of_line ();
14990 mips_clear_insn_labels ();
14993 /* Handle .dtprelword. */
14996 s_dtprelword (int ignore ATTRIBUTE_UNUSED
)
14998 s_tls_rel_directive (4, ".dtprelword", BFD_RELOC_MIPS_TLS_DTPREL32
);
15001 /* Handle .dtpreldword. */
15004 s_dtpreldword (int ignore ATTRIBUTE_UNUSED
)
15006 s_tls_rel_directive (8, ".dtpreldword", BFD_RELOC_MIPS_TLS_DTPREL64
);
15009 /* Handle .tprelword. */
15012 s_tprelword (int ignore ATTRIBUTE_UNUSED
)
15014 s_tls_rel_directive (4, ".tprelword", BFD_RELOC_MIPS_TLS_TPREL32
);
15017 /* Handle .tpreldword. */
15020 s_tpreldword (int ignore ATTRIBUTE_UNUSED
)
15022 s_tls_rel_directive (8, ".tpreldword", BFD_RELOC_MIPS_TLS_TPREL64
);
15025 /* Handle the .gpvalue pseudo-op. This is used when generating NewABI PIC
15026 code. It sets the offset to use in gp_rel relocations. */
15029 s_gpvalue (int ignore ATTRIBUTE_UNUSED
)
15031 /* If we are not generating SVR4 PIC code, .gpvalue is ignored.
15032 We also need NewABI support. */
15033 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
15039 mips_gprel_offset
= get_absolute_expression ();
15041 demand_empty_rest_of_line ();
15044 /* Handle the .gpword pseudo-op. This is used when generating PIC
15045 code. It generates a 32 bit GP relative reloc. */
15048 s_gpword (int ignore ATTRIBUTE_UNUSED
)
15050 segment_info_type
*si
;
15051 struct insn_label_list
*l
;
15055 /* When not generating PIC code, this is treated as .word. */
15056 if (mips_pic
!= SVR4_PIC
)
15062 si
= seg_info (now_seg
);
15063 l
= si
->label_list
;
15064 mips_emit_delays ();
15066 mips_align (2, 0, l
);
15069 mips_clear_insn_labels ();
15071 if (ex
.X_op
!= O_symbol
|| ex
.X_add_number
!= 0)
15073 as_bad (_("Unsupported use of .gpword"));
15074 ignore_rest_of_line ();
15078 md_number_to_chars (p
, 0, 4);
15079 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 4, &ex
, FALSE
,
15080 BFD_RELOC_GPREL32
);
15082 demand_empty_rest_of_line ();
15086 s_gpdword (int ignore ATTRIBUTE_UNUSED
)
15088 segment_info_type
*si
;
15089 struct insn_label_list
*l
;
15093 /* When not generating PIC code, this is treated as .dword. */
15094 if (mips_pic
!= SVR4_PIC
)
15100 si
= seg_info (now_seg
);
15101 l
= si
->label_list
;
15102 mips_emit_delays ();
15104 mips_align (3, 0, l
);
15107 mips_clear_insn_labels ();
15109 if (ex
.X_op
!= O_symbol
|| ex
.X_add_number
!= 0)
15111 as_bad (_("Unsupported use of .gpdword"));
15112 ignore_rest_of_line ();
15116 md_number_to_chars (p
, 0, 8);
15117 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 4, &ex
, FALSE
,
15118 BFD_RELOC_GPREL32
)->fx_tcbit
= 1;
15120 /* GPREL32 composed with 64 gives a 64-bit GP offset. */
15121 fix_new (frag_now
, p
- frag_now
->fr_literal
, 8, NULL
, 0,
15122 FALSE
, BFD_RELOC_64
)->fx_tcbit
= 1;
15124 demand_empty_rest_of_line ();
15127 /* Handle the .ehword pseudo-op. This is used when generating unwinding
15128 tables. It generates a R_MIPS_EH reloc. */
15131 s_ehword (int ignore ATTRIBUTE_UNUSED
)
15136 mips_emit_delays ();
15139 mips_clear_insn_labels ();
15141 if (ex
.X_op
!= O_symbol
|| ex
.X_add_number
!= 0)
15143 as_bad (_("Unsupported use of .ehword"));
15144 ignore_rest_of_line ();
15148 md_number_to_chars (p
, 0, 4);
15149 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 4, &ex
, FALSE
,
15150 BFD_RELOC_MIPS_EH
);
15152 demand_empty_rest_of_line ();
15155 /* Handle the .cpadd pseudo-op. This is used when dealing with switch
15156 tables in SVR4 PIC code. */
15159 s_cpadd (int ignore ATTRIBUTE_UNUSED
)
15163 /* This is ignored when not generating SVR4 PIC code. */
15164 if (mips_pic
!= SVR4_PIC
)
15170 mips_mark_labels ();
15171 mips_assembling_insn
= TRUE
;
15173 /* Add $gp to the register named as an argument. */
15175 reg
= tc_get_register (0);
15176 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", reg
, reg
, mips_gp_register
);
15179 mips_assembling_insn
= FALSE
;
15180 demand_empty_rest_of_line ();
15183 /* Handle the .insn pseudo-op. This marks instruction labels in
15184 mips16/micromips mode. This permits the linker to handle them specially,
15185 such as generating jalx instructions when needed. We also make
15186 them odd for the duration of the assembly, in order to generate the
15187 right sort of code. We will make them even in the adjust_symtab
15188 routine, while leaving them marked. This is convenient for the
15189 debugger and the disassembler. The linker knows to make them odd
15193 s_insn (int ignore ATTRIBUTE_UNUSED
)
15195 mips_mark_labels ();
15197 demand_empty_rest_of_line ();
15200 /* Handle the .nan pseudo-op. */
15203 s_nan (int ignore ATTRIBUTE_UNUSED
)
15205 static const char str_legacy
[] = "legacy";
15206 static const char str_2008
[] = "2008";
15209 for (i
= 0; !is_end_of_line
[(unsigned char) input_line_pointer
[i
]]; i
++);
15211 if (i
== sizeof (str_2008
) - 1
15212 && memcmp (input_line_pointer
, str_2008
, i
) == 0)
15213 mips_flag_nan2008
= TRUE
;
15214 else if (i
== sizeof (str_legacy
) - 1
15215 && memcmp (input_line_pointer
, str_legacy
, i
) == 0)
15216 mips_flag_nan2008
= FALSE
;
15218 as_bad (_("Bad .nan directive"));
15220 input_line_pointer
+= i
;
15221 demand_empty_rest_of_line ();
15224 /* Handle a .stab[snd] directive. Ideally these directives would be
15225 implemented in a transparent way, so that removing them would not
15226 have any effect on the generated instructions. However, s_stab
15227 internally changes the section, so in practice we need to decide
15228 now whether the preceding label marks compressed code. We do not
15229 support changing the compression mode of a label after a .stab*
15230 directive, such as in:
15236 so the current mode wins. */
15239 s_mips_stab (int type
)
15241 mips_mark_labels ();
15245 /* Handle the .weakext pseudo-op as defined in Kane and Heinrich. */
15248 s_mips_weakext (int ignore ATTRIBUTE_UNUSED
)
15255 name
= input_line_pointer
;
15256 c
= get_symbol_end ();
15257 symbolP
= symbol_find_or_make (name
);
15258 S_SET_WEAK (symbolP
);
15259 *input_line_pointer
= c
;
15261 SKIP_WHITESPACE ();
15263 if (! is_end_of_line
[(unsigned char) *input_line_pointer
])
15265 if (S_IS_DEFINED (symbolP
))
15267 as_bad (_("ignoring attempt to redefine symbol %s"),
15268 S_GET_NAME (symbolP
));
15269 ignore_rest_of_line ();
15273 if (*input_line_pointer
== ',')
15275 ++input_line_pointer
;
15276 SKIP_WHITESPACE ();
15280 if (exp
.X_op
!= O_symbol
)
15282 as_bad (_("bad .weakext directive"));
15283 ignore_rest_of_line ();
15286 symbol_set_value_expression (symbolP
, &exp
);
15289 demand_empty_rest_of_line ();
15292 /* Parse a register string into a number. Called from the ECOFF code
15293 to parse .frame. The argument is non-zero if this is the frame
15294 register, so that we can record it in mips_frame_reg. */
15297 tc_get_register (int frame
)
15301 SKIP_WHITESPACE ();
15302 if (! reg_lookup (&input_line_pointer
, RWARN
| RTYPE_NUM
| RTYPE_GP
, ®
))
15306 mips_frame_reg
= reg
!= 0 ? reg
: SP
;
15307 mips_frame_reg_valid
= 1;
15308 mips_cprestore_valid
= 0;
15314 md_section_align (asection
*seg
, valueT addr
)
15316 int align
= bfd_get_section_alignment (stdoutput
, seg
);
15318 /* We don't need to align ELF sections to the full alignment.
15319 However, Irix 5 may prefer that we align them at least to a 16
15320 byte boundary. We don't bother to align the sections if we
15321 are targeted for an embedded system. */
15322 if (strncmp (TARGET_OS
, "elf", 3) == 0)
15327 return ((addr
+ (1 << align
) - 1) & (-1 << align
));
15330 /* Utility routine, called from above as well. If called while the
15331 input file is still being read, it's only an approximation. (For
15332 example, a symbol may later become defined which appeared to be
15333 undefined earlier.) */
15336 nopic_need_relax (symbolS
*sym
, int before_relaxing
)
15341 if (g_switch_value
> 0)
15343 const char *symname
;
15346 /* Find out whether this symbol can be referenced off the $gp
15347 register. It can be if it is smaller than the -G size or if
15348 it is in the .sdata or .sbss section. Certain symbols can
15349 not be referenced off the $gp, although it appears as though
15351 symname
= S_GET_NAME (sym
);
15352 if (symname
!= (const char *) NULL
15353 && (strcmp (symname
, "eprol") == 0
15354 || strcmp (symname
, "etext") == 0
15355 || strcmp (symname
, "_gp") == 0
15356 || strcmp (symname
, "edata") == 0
15357 || strcmp (symname
, "_fbss") == 0
15358 || strcmp (symname
, "_fdata") == 0
15359 || strcmp (symname
, "_ftext") == 0
15360 || strcmp (symname
, "end") == 0
15361 || strcmp (symname
, "_gp_disp") == 0))
15363 else if ((! S_IS_DEFINED (sym
) || S_IS_COMMON (sym
))
15365 #ifndef NO_ECOFF_DEBUGGING
15366 || (symbol_get_obj (sym
)->ecoff_extern_size
!= 0
15367 && (symbol_get_obj (sym
)->ecoff_extern_size
15368 <= g_switch_value
))
15370 /* We must defer this decision until after the whole
15371 file has been read, since there might be a .extern
15372 after the first use of this symbol. */
15373 || (before_relaxing
15374 #ifndef NO_ECOFF_DEBUGGING
15375 && symbol_get_obj (sym
)->ecoff_extern_size
== 0
15377 && S_GET_VALUE (sym
) == 0)
15378 || (S_GET_VALUE (sym
) != 0
15379 && S_GET_VALUE (sym
) <= g_switch_value
)))
15383 const char *segname
;
15385 segname
= segment_name (S_GET_SEGMENT (sym
));
15386 gas_assert (strcmp (segname
, ".lit8") != 0
15387 && strcmp (segname
, ".lit4") != 0);
15388 change
= (strcmp (segname
, ".sdata") != 0
15389 && strcmp (segname
, ".sbss") != 0
15390 && strncmp (segname
, ".sdata.", 7) != 0
15391 && strncmp (segname
, ".sbss.", 6) != 0
15392 && strncmp (segname
, ".gnu.linkonce.sb.", 17) != 0
15393 && strncmp (segname
, ".gnu.linkonce.s.", 16) != 0);
15398 /* We are not optimizing for the $gp register. */
15403 /* Return true if the given symbol should be considered local for SVR4 PIC. */
15406 pic_need_relax (symbolS
*sym
, asection
*segtype
)
15410 /* Handle the case of a symbol equated to another symbol. */
15411 while (symbol_equated_reloc_p (sym
))
15415 /* It's possible to get a loop here in a badly written program. */
15416 n
= symbol_get_value_expression (sym
)->X_add_symbol
;
15422 if (symbol_section_p (sym
))
15425 symsec
= S_GET_SEGMENT (sym
);
15427 /* This must duplicate the test in adjust_reloc_syms. */
15428 return (!bfd_is_und_section (symsec
)
15429 && !bfd_is_abs_section (symsec
)
15430 && !bfd_is_com_section (symsec
)
15431 && !s_is_linkonce (sym
, segtype
)
15432 /* A global or weak symbol is treated as external. */
15433 && (!S_IS_WEAK (sym
) && !S_IS_EXTERNAL (sym
)));
15437 /* Given a mips16 variant frag FRAGP, return non-zero if it needs an
15438 extended opcode. SEC is the section the frag is in. */
15441 mips16_extended_frag (fragS
*fragp
, asection
*sec
, long stretch
)
15444 const struct mips16_immed_operand
*op
;
15446 int mintiny
, maxtiny
;
15450 if (RELAX_MIPS16_USER_SMALL (fragp
->fr_subtype
))
15452 if (RELAX_MIPS16_USER_EXT (fragp
->fr_subtype
))
15455 type
= RELAX_MIPS16_TYPE (fragp
->fr_subtype
);
15456 op
= mips16_immed_operands
;
15457 while (op
->type
!= type
)
15460 gas_assert (op
< mips16_immed_operands
+ MIPS16_NUM_IMMED
);
15465 if (type
== '<' || type
== '>' || type
== '[' || type
== ']')
15468 maxtiny
= 1 << op
->nbits
;
15473 maxtiny
= (1 << op
->nbits
) - 1;
15478 mintiny
= - (1 << (op
->nbits
- 1));
15479 maxtiny
= (1 << (op
->nbits
- 1)) - 1;
15482 sym_frag
= symbol_get_frag (fragp
->fr_symbol
);
15483 val
= S_GET_VALUE (fragp
->fr_symbol
);
15484 symsec
= S_GET_SEGMENT (fragp
->fr_symbol
);
15490 /* We won't have the section when we are called from
15491 mips_relax_frag. However, we will always have been called
15492 from md_estimate_size_before_relax first. If this is a
15493 branch to a different section, we mark it as such. If SEC is
15494 NULL, and the frag is not marked, then it must be a branch to
15495 the same section. */
15498 if (RELAX_MIPS16_LONG_BRANCH (fragp
->fr_subtype
))
15503 /* Must have been called from md_estimate_size_before_relax. */
15506 fragp
->fr_subtype
=
15507 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
15509 /* FIXME: We should support this, and let the linker
15510 catch branches and loads that are out of range. */
15511 as_bad_where (fragp
->fr_file
, fragp
->fr_line
,
15512 _("unsupported PC relative reference to different section"));
15516 if (fragp
!= sym_frag
&& sym_frag
->fr_address
== 0)
15517 /* Assume non-extended on the first relaxation pass.
15518 The address we have calculated will be bogus if this is
15519 a forward branch to another frag, as the forward frag
15520 will have fr_address == 0. */
15524 /* In this case, we know for sure that the symbol fragment is in
15525 the same section. If the relax_marker of the symbol fragment
15526 differs from the relax_marker of this fragment, we have not
15527 yet adjusted the symbol fragment fr_address. We want to add
15528 in STRETCH in order to get a better estimate of the address.
15529 This particularly matters because of the shift bits. */
15531 && sym_frag
->relax_marker
!= fragp
->relax_marker
)
15535 /* Adjust stretch for any alignment frag. Note that if have
15536 been expanding the earlier code, the symbol may be
15537 defined in what appears to be an earlier frag. FIXME:
15538 This doesn't handle the fr_subtype field, which specifies
15539 a maximum number of bytes to skip when doing an
15541 for (f
= fragp
; f
!= NULL
&& f
!= sym_frag
; f
= f
->fr_next
)
15543 if (f
->fr_type
== rs_align
|| f
->fr_type
== rs_align_code
)
15546 stretch
= - ((- stretch
)
15547 & ~ ((1 << (int) f
->fr_offset
) - 1));
15549 stretch
&= ~ ((1 << (int) f
->fr_offset
) - 1);
15558 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
15560 /* The base address rules are complicated. The base address of
15561 a branch is the following instruction. The base address of a
15562 PC relative load or add is the instruction itself, but if it
15563 is in a delay slot (in which case it can not be extended) use
15564 the address of the instruction whose delay slot it is in. */
15565 if (type
== 'p' || type
== 'q')
15569 /* If we are currently assuming that this frag should be
15570 extended, then, the current address is two bytes
15572 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
15575 /* Ignore the low bit in the target, since it will be set
15576 for a text label. */
15577 if ((val
& 1) != 0)
15580 else if (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
))
15582 else if (RELAX_MIPS16_DSLOT (fragp
->fr_subtype
))
15585 val
-= addr
& ~ ((1 << op
->shift
) - 1);
15587 /* Branch offsets have an implicit 0 in the lowest bit. */
15588 if (type
== 'p' || type
== 'q')
15591 /* If any of the shifted bits are set, we must use an extended
15592 opcode. If the address depends on the size of this
15593 instruction, this can lead to a loop, so we arrange to always
15594 use an extended opcode. We only check this when we are in
15595 the main relaxation loop, when SEC is NULL. */
15596 if ((val
& ((1 << op
->shift
) - 1)) != 0 && sec
== NULL
)
15598 fragp
->fr_subtype
=
15599 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
15603 /* If we are about to mark a frag as extended because the value
15604 is precisely maxtiny + 1, then there is a chance of an
15605 infinite loop as in the following code:
15610 In this case when the la is extended, foo is 0x3fc bytes
15611 away, so the la can be shrunk, but then foo is 0x400 away, so
15612 the la must be extended. To avoid this loop, we mark the
15613 frag as extended if it was small, and is about to become
15614 extended with a value of maxtiny + 1. */
15615 if (val
== ((maxtiny
+ 1) << op
->shift
)
15616 && ! RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
)
15619 fragp
->fr_subtype
=
15620 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
15624 else if (symsec
!= absolute_section
&& sec
!= NULL
)
15625 as_bad_where (fragp
->fr_file
, fragp
->fr_line
, _("unsupported relocation"));
15627 if ((val
& ((1 << op
->shift
) - 1)) != 0
15628 || val
< (mintiny
<< op
->shift
)
15629 || val
> (maxtiny
<< op
->shift
))
15635 /* Compute the length of a branch sequence, and adjust the
15636 RELAX_BRANCH_TOOFAR bit accordingly. If FRAGP is NULL, the
15637 worst-case length is computed, with UPDATE being used to indicate
15638 whether an unconditional (-1), branch-likely (+1) or regular (0)
15639 branch is to be computed. */
15641 relaxed_branch_length (fragS
*fragp
, asection
*sec
, int update
)
15643 bfd_boolean toofar
;
15647 && S_IS_DEFINED (fragp
->fr_symbol
)
15648 && sec
== S_GET_SEGMENT (fragp
->fr_symbol
))
15653 val
= S_GET_VALUE (fragp
->fr_symbol
) + fragp
->fr_offset
;
15655 addr
= fragp
->fr_address
+ fragp
->fr_fix
+ 4;
15659 toofar
= val
< - (0x8000 << 2) || val
>= (0x8000 << 2);
15662 /* If the symbol is not defined or it's in a different segment,
15663 assume the user knows what's going on and emit a short
15669 if (fragp
&& update
&& toofar
!= RELAX_BRANCH_TOOFAR (fragp
->fr_subtype
))
15671 = RELAX_BRANCH_ENCODE (RELAX_BRANCH_AT (fragp
->fr_subtype
),
15672 RELAX_BRANCH_UNCOND (fragp
->fr_subtype
),
15673 RELAX_BRANCH_LIKELY (fragp
->fr_subtype
),
15674 RELAX_BRANCH_LINK (fragp
->fr_subtype
),
15680 if (fragp
? RELAX_BRANCH_LIKELY (fragp
->fr_subtype
) : (update
> 0))
15683 if (mips_pic
!= NO_PIC
)
15685 /* Additional space for PIC loading of target address. */
15687 if (mips_opts
.isa
== ISA_MIPS1
)
15688 /* Additional space for $at-stabilizing nop. */
15692 /* If branch is conditional. */
15693 if (fragp
? !RELAX_BRANCH_UNCOND (fragp
->fr_subtype
) : (update
>= 0))
15700 /* Compute the length of a branch sequence, and adjust the
15701 RELAX_MICROMIPS_TOOFAR32 bit accordingly. If FRAGP is NULL, the
15702 worst-case length is computed, with UPDATE being used to indicate
15703 whether an unconditional (-1), or regular (0) branch is to be
15707 relaxed_micromips_32bit_branch_length (fragS
*fragp
, asection
*sec
, int update
)
15709 bfd_boolean toofar
;
15713 && S_IS_DEFINED (fragp
->fr_symbol
)
15714 && sec
== S_GET_SEGMENT (fragp
->fr_symbol
))
15719 val
= S_GET_VALUE (fragp
->fr_symbol
) + fragp
->fr_offset
;
15720 /* Ignore the low bit in the target, since it will be set
15721 for a text label. */
15722 if ((val
& 1) != 0)
15725 addr
= fragp
->fr_address
+ fragp
->fr_fix
+ 4;
15729 toofar
= val
< - (0x8000 << 1) || val
>= (0x8000 << 1);
15732 /* If the symbol is not defined or it's in a different segment,
15733 assume the user knows what's going on and emit a short
15739 if (fragp
&& update
15740 && toofar
!= RELAX_MICROMIPS_TOOFAR32 (fragp
->fr_subtype
))
15741 fragp
->fr_subtype
= (toofar
15742 ? RELAX_MICROMIPS_MARK_TOOFAR32 (fragp
->fr_subtype
)
15743 : RELAX_MICROMIPS_CLEAR_TOOFAR32 (fragp
->fr_subtype
));
15748 bfd_boolean compact_known
= fragp
!= NULL
;
15749 bfd_boolean compact
= FALSE
;
15750 bfd_boolean uncond
;
15753 compact
= RELAX_MICROMIPS_COMPACT (fragp
->fr_subtype
);
15755 uncond
= RELAX_MICROMIPS_UNCOND (fragp
->fr_subtype
);
15757 uncond
= update
< 0;
15759 /* If label is out of range, we turn branch <br>:
15761 <br> label # 4 bytes
15767 nop # 2 bytes if compact && !PIC
15770 if (mips_pic
== NO_PIC
&& (!compact_known
|| compact
))
15773 /* If assembling PIC code, we further turn:
15779 lw/ld at, %got(label)(gp) # 4 bytes
15780 d/addiu at, %lo(label) # 4 bytes
15783 if (mips_pic
!= NO_PIC
)
15786 /* If branch <br> is conditional, we prepend negated branch <brneg>:
15788 <brneg> 0f # 4 bytes
15789 nop # 2 bytes if !compact
15792 length
+= (compact_known
&& compact
) ? 4 : 6;
15798 /* Compute the length of a branch, and adjust the RELAX_MICROMIPS_TOOFAR16
15799 bit accordingly. */
15802 relaxed_micromips_16bit_branch_length (fragS
*fragp
, asection
*sec
, int update
)
15804 bfd_boolean toofar
;
15807 && S_IS_DEFINED (fragp
->fr_symbol
)
15808 && sec
== S_GET_SEGMENT (fragp
->fr_symbol
))
15814 val
= S_GET_VALUE (fragp
->fr_symbol
) + fragp
->fr_offset
;
15815 /* Ignore the low bit in the target, since it will be set
15816 for a text label. */
15817 if ((val
& 1) != 0)
15820 /* Assume this is a 2-byte branch. */
15821 addr
= fragp
->fr_address
+ fragp
->fr_fix
+ 2;
15823 /* We try to avoid the infinite loop by not adding 2 more bytes for
15828 type
= RELAX_MICROMIPS_TYPE (fragp
->fr_subtype
);
15830 toofar
= val
< - (0x200 << 1) || val
>= (0x200 << 1);
15831 else if (type
== 'E')
15832 toofar
= val
< - (0x40 << 1) || val
>= (0x40 << 1);
15837 /* If the symbol is not defined or it's in a different segment,
15838 we emit a normal 32-bit branch. */
15841 if (fragp
&& update
15842 && toofar
!= RELAX_MICROMIPS_TOOFAR16 (fragp
->fr_subtype
))
15844 = toofar
? RELAX_MICROMIPS_MARK_TOOFAR16 (fragp
->fr_subtype
)
15845 : RELAX_MICROMIPS_CLEAR_TOOFAR16 (fragp
->fr_subtype
);
15853 /* Estimate the size of a frag before relaxing. Unless this is the
15854 mips16, we are not really relaxing here, and the final size is
15855 encoded in the subtype information. For the mips16, we have to
15856 decide whether we are using an extended opcode or not. */
15859 md_estimate_size_before_relax (fragS
*fragp
, asection
*segtype
)
15863 if (RELAX_BRANCH_P (fragp
->fr_subtype
))
15866 fragp
->fr_var
= relaxed_branch_length (fragp
, segtype
, FALSE
);
15868 return fragp
->fr_var
;
15871 if (RELAX_MIPS16_P (fragp
->fr_subtype
))
15872 /* We don't want to modify the EXTENDED bit here; it might get us
15873 into infinite loops. We change it only in mips_relax_frag(). */
15874 return (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
) ? 4 : 2);
15876 if (RELAX_MICROMIPS_P (fragp
->fr_subtype
))
15880 if (RELAX_MICROMIPS_TYPE (fragp
->fr_subtype
) != 0)
15881 length
= relaxed_micromips_16bit_branch_length (fragp
, segtype
, FALSE
);
15882 if (length
== 4 && RELAX_MICROMIPS_RELAX32 (fragp
->fr_subtype
))
15883 length
= relaxed_micromips_32bit_branch_length (fragp
, segtype
, FALSE
);
15884 fragp
->fr_var
= length
;
15889 if (mips_pic
== NO_PIC
)
15890 change
= nopic_need_relax (fragp
->fr_symbol
, 0);
15891 else if (mips_pic
== SVR4_PIC
)
15892 change
= pic_need_relax (fragp
->fr_symbol
, segtype
);
15893 else if (mips_pic
== VXWORKS_PIC
)
15894 /* For vxworks, GOT16 relocations never have a corresponding LO16. */
15901 fragp
->fr_subtype
|= RELAX_USE_SECOND
;
15902 return -RELAX_FIRST (fragp
->fr_subtype
);
15905 return -RELAX_SECOND (fragp
->fr_subtype
);
15908 /* This is called to see whether a reloc against a defined symbol
15909 should be converted into a reloc against a section. */
15912 mips_fix_adjustable (fixS
*fixp
)
15914 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
15915 || fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
15918 if (fixp
->fx_addsy
== NULL
)
15921 /* If symbol SYM is in a mergeable section, relocations of the form
15922 SYM + 0 can usually be made section-relative. The mergeable data
15923 is then identified by the section offset rather than by the symbol.
15925 However, if we're generating REL LO16 relocations, the offset is split
15926 between the LO16 and parterning high part relocation. The linker will
15927 need to recalculate the complete offset in order to correctly identify
15930 The linker has traditionally not looked for the parterning high part
15931 relocation, and has thus allowed orphaned R_MIPS_LO16 relocations to be
15932 placed anywhere. Rather than break backwards compatibility by changing
15933 this, it seems better not to force the issue, and instead keep the
15934 original symbol. This will work with either linker behavior. */
15935 if ((lo16_reloc_p (fixp
->fx_r_type
)
15936 || reloc_needs_lo_p (fixp
->fx_r_type
))
15937 && HAVE_IN_PLACE_ADDENDS
15938 && (S_GET_SEGMENT (fixp
->fx_addsy
)->flags
& SEC_MERGE
) != 0)
15941 /* There is no place to store an in-place offset for JALR relocations.
15942 Likewise an in-range offset of limited PC-relative relocations may
15943 overflow the in-place relocatable field if recalculated against the
15944 start address of the symbol's containing section. */
15945 if (HAVE_IN_PLACE_ADDENDS
15946 && (limited_pcrel_reloc_p (fixp
->fx_r_type
)
15947 || jalr_reloc_p (fixp
->fx_r_type
)))
15950 /* R_MIPS16_26 relocations against non-MIPS16 functions might resolve
15951 to a floating-point stub. The same is true for non-R_MIPS16_26
15952 relocations against MIPS16 functions; in this case, the stub becomes
15953 the function's canonical address.
15955 Floating-point stubs are stored in unique .mips16.call.* or
15956 .mips16.fn.* sections. If a stub T for function F is in section S,
15957 the first relocation in section S must be against F; this is how the
15958 linker determines the target function. All relocations that might
15959 resolve to T must also be against F. We therefore have the following
15960 restrictions, which are given in an intentionally-redundant way:
15962 1. We cannot reduce R_MIPS16_26 relocations against non-MIPS16
15965 2. We cannot reduce a stub's relocations against non-MIPS16 symbols
15966 if that stub might be used.
15968 3. We cannot reduce non-R_MIPS16_26 relocations against MIPS16
15971 4. We cannot reduce a stub's relocations against MIPS16 symbols if
15972 that stub might be used.
15974 There is a further restriction:
15976 5. We cannot reduce jump relocations (R_MIPS_26, R_MIPS16_26 or
15977 R_MICROMIPS_26_S1) against MIPS16 or microMIPS symbols on
15978 targets with in-place addends; the relocation field cannot
15979 encode the low bit.
15981 For simplicity, we deal with (3)-(4) by not reducing _any_ relocation
15982 against a MIPS16 symbol. We deal with (5) by by not reducing any
15983 such relocations on REL targets.
15985 We deal with (1)-(2) by saying that, if there's a R_MIPS16_26
15986 relocation against some symbol R, no relocation against R may be
15987 reduced. (Note that this deals with (2) as well as (1) because
15988 relocations against global symbols will never be reduced on ELF
15989 targets.) This approach is a little simpler than trying to detect
15990 stub sections, and gives the "all or nothing" per-symbol consistency
15991 that we have for MIPS16 symbols. */
15992 if (fixp
->fx_subsy
== NULL
15993 && (ELF_ST_IS_MIPS16 (S_GET_OTHER (fixp
->fx_addsy
))
15994 || *symbol_get_tc (fixp
->fx_addsy
)
15995 || (HAVE_IN_PLACE_ADDENDS
15996 && ELF_ST_IS_MICROMIPS (S_GET_OTHER (fixp
->fx_addsy
))
15997 && jmp_reloc_p (fixp
->fx_r_type
))))
16003 /* Translate internal representation of relocation info to BFD target
16007 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
, fixS
*fixp
)
16009 static arelent
*retval
[4];
16011 bfd_reloc_code_real_type code
;
16013 memset (retval
, 0, sizeof(retval
));
16014 reloc
= retval
[0] = (arelent
*) xcalloc (1, sizeof (arelent
));
16015 reloc
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
16016 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
16017 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
16019 if (fixp
->fx_pcrel
)
16021 gas_assert (fixp
->fx_r_type
== BFD_RELOC_16_PCREL_S2
16022 || fixp
->fx_r_type
== BFD_RELOC_MICROMIPS_7_PCREL_S1
16023 || fixp
->fx_r_type
== BFD_RELOC_MICROMIPS_10_PCREL_S1
16024 || fixp
->fx_r_type
== BFD_RELOC_MICROMIPS_16_PCREL_S1
16025 || fixp
->fx_r_type
== BFD_RELOC_32_PCREL
);
16027 /* At this point, fx_addnumber is "symbol offset - pcrel address".
16028 Relocations want only the symbol offset. */
16029 reloc
->addend
= fixp
->fx_addnumber
+ reloc
->address
;
16032 reloc
->addend
= fixp
->fx_addnumber
;
16034 /* Since the old MIPS ELF ABI uses Rel instead of Rela, encode the vtable
16035 entry to be used in the relocation's section offset. */
16036 if (! HAVE_NEWABI
&& fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
16038 reloc
->address
= reloc
->addend
;
16042 code
= fixp
->fx_r_type
;
16044 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
16045 if (reloc
->howto
== NULL
)
16047 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
16048 _("Can not represent %s relocation in this object file format"),
16049 bfd_get_reloc_code_name (code
));
16056 /* Relax a machine dependent frag. This returns the amount by which
16057 the current size of the frag should change. */
16060 mips_relax_frag (asection
*sec
, fragS
*fragp
, long stretch
)
16062 if (RELAX_BRANCH_P (fragp
->fr_subtype
))
16064 offsetT old_var
= fragp
->fr_var
;
16066 fragp
->fr_var
= relaxed_branch_length (fragp
, sec
, TRUE
);
16068 return fragp
->fr_var
- old_var
;
16071 if (RELAX_MICROMIPS_P (fragp
->fr_subtype
))
16073 offsetT old_var
= fragp
->fr_var
;
16074 offsetT new_var
= 4;
16076 if (RELAX_MICROMIPS_TYPE (fragp
->fr_subtype
) != 0)
16077 new_var
= relaxed_micromips_16bit_branch_length (fragp
, sec
, TRUE
);
16078 if (new_var
== 4 && RELAX_MICROMIPS_RELAX32 (fragp
->fr_subtype
))
16079 new_var
= relaxed_micromips_32bit_branch_length (fragp
, sec
, TRUE
);
16080 fragp
->fr_var
= new_var
;
16082 return new_var
- old_var
;
16085 if (! RELAX_MIPS16_P (fragp
->fr_subtype
))
16088 if (mips16_extended_frag (fragp
, NULL
, stretch
))
16090 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
16092 fragp
->fr_subtype
= RELAX_MIPS16_MARK_EXTENDED (fragp
->fr_subtype
);
16097 if (! RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
16099 fragp
->fr_subtype
= RELAX_MIPS16_CLEAR_EXTENDED (fragp
->fr_subtype
);
16106 /* Convert a machine dependent frag. */
16109 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
, segT asec
, fragS
*fragp
)
16111 if (RELAX_BRANCH_P (fragp
->fr_subtype
))
16114 unsigned long insn
;
16118 buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
16119 insn
= read_insn (buf
);
16121 if (!RELAX_BRANCH_TOOFAR (fragp
->fr_subtype
))
16123 /* We generate a fixup instead of applying it right now
16124 because, if there are linker relaxations, we're going to
16125 need the relocations. */
16126 exp
.X_op
= O_symbol
;
16127 exp
.X_add_symbol
= fragp
->fr_symbol
;
16128 exp
.X_add_number
= fragp
->fr_offset
;
16130 fixp
= fix_new_exp (fragp
, buf
- fragp
->fr_literal
, 4, &exp
, TRUE
,
16131 BFD_RELOC_16_PCREL_S2
);
16132 fixp
->fx_file
= fragp
->fr_file
;
16133 fixp
->fx_line
= fragp
->fr_line
;
16135 buf
= write_insn (buf
, insn
);
16141 as_warn_where (fragp
->fr_file
, fragp
->fr_line
,
16142 _("Relaxed out-of-range branch into a jump"));
16144 if (RELAX_BRANCH_UNCOND (fragp
->fr_subtype
))
16147 if (!RELAX_BRANCH_LIKELY (fragp
->fr_subtype
))
16149 /* Reverse the branch. */
16150 switch ((insn
>> 28) & 0xf)
16153 /* bc[0-3][tf]l? instructions can have the condition
16154 reversed by tweaking a single TF bit, and their
16155 opcodes all have 0x4???????. */
16156 gas_assert ((insn
& 0xf3e00000) == 0x41000000);
16157 insn
^= 0x00010000;
16161 /* bltz 0x04000000 bgez 0x04010000
16162 bltzal 0x04100000 bgezal 0x04110000 */
16163 gas_assert ((insn
& 0xfc0e0000) == 0x04000000);
16164 insn
^= 0x00010000;
16168 /* beq 0x10000000 bne 0x14000000
16169 blez 0x18000000 bgtz 0x1c000000 */
16170 insn
^= 0x04000000;
16178 if (RELAX_BRANCH_LINK (fragp
->fr_subtype
))
16180 /* Clear the and-link bit. */
16181 gas_assert ((insn
& 0xfc1c0000) == 0x04100000);
16183 /* bltzal 0x04100000 bgezal 0x04110000
16184 bltzall 0x04120000 bgezall 0x04130000 */
16185 insn
&= ~0x00100000;
16188 /* Branch over the branch (if the branch was likely) or the
16189 full jump (not likely case). Compute the offset from the
16190 current instruction to branch to. */
16191 if (RELAX_BRANCH_LIKELY (fragp
->fr_subtype
))
16195 /* How many bytes in instructions we've already emitted? */
16196 i
= buf
- fragp
->fr_literal
- fragp
->fr_fix
;
16197 /* How many bytes in instructions from here to the end? */
16198 i
= fragp
->fr_var
- i
;
16200 /* Convert to instruction count. */
16202 /* Branch counts from the next instruction. */
16205 /* Branch over the jump. */
16206 buf
= write_insn (buf
, insn
);
16209 buf
= write_insn (buf
, 0);
16211 if (RELAX_BRANCH_LIKELY (fragp
->fr_subtype
))
16213 /* beql $0, $0, 2f */
16215 /* Compute the PC offset from the current instruction to
16216 the end of the variable frag. */
16217 /* How many bytes in instructions we've already emitted? */
16218 i
= buf
- fragp
->fr_literal
- fragp
->fr_fix
;
16219 /* How many bytes in instructions from here to the end? */
16220 i
= fragp
->fr_var
- i
;
16221 /* Convert to instruction count. */
16223 /* Don't decrement i, because we want to branch over the
16227 buf
= write_insn (buf
, insn
);
16228 buf
= write_insn (buf
, 0);
16232 if (mips_pic
== NO_PIC
)
16235 insn
= (RELAX_BRANCH_LINK (fragp
->fr_subtype
)
16236 ? 0x0c000000 : 0x08000000);
16237 exp
.X_op
= O_symbol
;
16238 exp
.X_add_symbol
= fragp
->fr_symbol
;
16239 exp
.X_add_number
= fragp
->fr_offset
;
16241 fixp
= fix_new_exp (fragp
, buf
- fragp
->fr_literal
, 4, &exp
,
16242 FALSE
, BFD_RELOC_MIPS_JMP
);
16243 fixp
->fx_file
= fragp
->fr_file
;
16244 fixp
->fx_line
= fragp
->fr_line
;
16246 buf
= write_insn (buf
, insn
);
16250 unsigned long at
= RELAX_BRANCH_AT (fragp
->fr_subtype
);
16252 /* lw/ld $at, <sym>($gp) R_MIPS_GOT16 */
16253 insn
= HAVE_64BIT_ADDRESSES
? 0xdf800000 : 0x8f800000;
16254 insn
|= at
<< OP_SH_RT
;
16255 exp
.X_op
= O_symbol
;
16256 exp
.X_add_symbol
= fragp
->fr_symbol
;
16257 exp
.X_add_number
= fragp
->fr_offset
;
16259 if (fragp
->fr_offset
)
16261 exp
.X_add_symbol
= make_expr_symbol (&exp
);
16262 exp
.X_add_number
= 0;
16265 fixp
= fix_new_exp (fragp
, buf
- fragp
->fr_literal
, 4, &exp
,
16266 FALSE
, BFD_RELOC_MIPS_GOT16
);
16267 fixp
->fx_file
= fragp
->fr_file
;
16268 fixp
->fx_line
= fragp
->fr_line
;
16270 buf
= write_insn (buf
, insn
);
16272 if (mips_opts
.isa
== ISA_MIPS1
)
16274 buf
= write_insn (buf
, 0);
16276 /* d/addiu $at, $at, <sym> R_MIPS_LO16 */
16277 insn
= HAVE_64BIT_ADDRESSES
? 0x64000000 : 0x24000000;
16278 insn
|= at
<< OP_SH_RS
| at
<< OP_SH_RT
;
16280 fixp
= fix_new_exp (fragp
, buf
- fragp
->fr_literal
, 4, &exp
,
16281 FALSE
, BFD_RELOC_LO16
);
16282 fixp
->fx_file
= fragp
->fr_file
;
16283 fixp
->fx_line
= fragp
->fr_line
;
16285 buf
= write_insn (buf
, insn
);
16288 if (RELAX_BRANCH_LINK (fragp
->fr_subtype
))
16292 insn
|= at
<< OP_SH_RS
;
16294 buf
= write_insn (buf
, insn
);
16298 fragp
->fr_fix
+= fragp
->fr_var
;
16299 gas_assert (buf
== fragp
->fr_literal
+ fragp
->fr_fix
);
16303 /* Relax microMIPS branches. */
16304 if (RELAX_MICROMIPS_P (fragp
->fr_subtype
))
16306 char *buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
16307 bfd_boolean compact
= RELAX_MICROMIPS_COMPACT (fragp
->fr_subtype
);
16308 bfd_boolean al
= RELAX_MICROMIPS_LINK (fragp
->fr_subtype
);
16309 int type
= RELAX_MICROMIPS_TYPE (fragp
->fr_subtype
);
16310 bfd_boolean short_ds
;
16311 unsigned long insn
;
16315 exp
.X_op
= O_symbol
;
16316 exp
.X_add_symbol
= fragp
->fr_symbol
;
16317 exp
.X_add_number
= fragp
->fr_offset
;
16319 fragp
->fr_fix
+= fragp
->fr_var
;
16321 /* Handle 16-bit branches that fit or are forced to fit. */
16322 if (type
!= 0 && !RELAX_MICROMIPS_TOOFAR16 (fragp
->fr_subtype
))
16324 /* We generate a fixup instead of applying it right now,
16325 because if there is linker relaxation, we're going to
16326 need the relocations. */
16328 fixp
= fix_new_exp (fragp
, buf
- fragp
->fr_literal
, 2, &exp
, TRUE
,
16329 BFD_RELOC_MICROMIPS_10_PCREL_S1
);
16330 else if (type
== 'E')
16331 fixp
= fix_new_exp (fragp
, buf
- fragp
->fr_literal
, 2, &exp
, TRUE
,
16332 BFD_RELOC_MICROMIPS_7_PCREL_S1
);
16336 fixp
->fx_file
= fragp
->fr_file
;
16337 fixp
->fx_line
= fragp
->fr_line
;
16339 /* These relocations can have an addend that won't fit in
16341 fixp
->fx_no_overflow
= 1;
16346 /* Handle 32-bit branches that fit or are forced to fit. */
16347 if (!RELAX_MICROMIPS_RELAX32 (fragp
->fr_subtype
)
16348 || !RELAX_MICROMIPS_TOOFAR32 (fragp
->fr_subtype
))
16350 /* We generate a fixup instead of applying it right now,
16351 because if there is linker relaxation, we're going to
16352 need the relocations. */
16353 fixp
= fix_new_exp (fragp
, buf
- fragp
->fr_literal
, 4, &exp
, TRUE
,
16354 BFD_RELOC_MICROMIPS_16_PCREL_S1
);
16355 fixp
->fx_file
= fragp
->fr_file
;
16356 fixp
->fx_line
= fragp
->fr_line
;
16362 /* Relax 16-bit branches to 32-bit branches. */
16365 insn
= read_compressed_insn (buf
, 2);
16367 if ((insn
& 0xfc00) == 0xcc00) /* b16 */
16368 insn
= 0x94000000; /* beq */
16369 else if ((insn
& 0xdc00) == 0x8c00) /* beqz16/bnez16 */
16371 unsigned long regno
;
16373 regno
= (insn
>> MICROMIPSOP_SH_MD
) & MICROMIPSOP_MASK_MD
;
16374 regno
= micromips_to_32_reg_d_map
[regno
];
16375 insn
= ((insn
& 0x2000) << 16) | 0x94000000; /* beq/bne */
16376 insn
|= regno
<< MICROMIPSOP_SH_RS
;
16381 /* Nothing else to do, just write it out. */
16382 if (!RELAX_MICROMIPS_RELAX32 (fragp
->fr_subtype
)
16383 || !RELAX_MICROMIPS_TOOFAR32 (fragp
->fr_subtype
))
16385 buf
= write_compressed_insn (buf
, insn
, 4);
16386 gas_assert (buf
== fragp
->fr_literal
+ fragp
->fr_fix
);
16391 insn
= read_compressed_insn (buf
, 4);
16393 /* Relax 32-bit branches to a sequence of instructions. */
16394 as_warn_where (fragp
->fr_file
, fragp
->fr_line
,
16395 _("Relaxed out-of-range branch into a jump"));
16397 /* Set the short-delay-slot bit. */
16398 short_ds
= al
&& (insn
& 0x02000000) != 0;
16400 if (!RELAX_MICROMIPS_UNCOND (fragp
->fr_subtype
))
16404 /* Reverse the branch. */
16405 if ((insn
& 0xfc000000) == 0x94000000 /* beq */
16406 || (insn
& 0xfc000000) == 0xb4000000) /* bne */
16407 insn
^= 0x20000000;
16408 else if ((insn
& 0xffe00000) == 0x40000000 /* bltz */
16409 || (insn
& 0xffe00000) == 0x40400000 /* bgez */
16410 || (insn
& 0xffe00000) == 0x40800000 /* blez */
16411 || (insn
& 0xffe00000) == 0x40c00000 /* bgtz */
16412 || (insn
& 0xffe00000) == 0x40a00000 /* bnezc */
16413 || (insn
& 0xffe00000) == 0x40e00000 /* beqzc */
16414 || (insn
& 0xffe00000) == 0x40200000 /* bltzal */
16415 || (insn
& 0xffe00000) == 0x40600000 /* bgezal */
16416 || (insn
& 0xffe00000) == 0x42200000 /* bltzals */
16417 || (insn
& 0xffe00000) == 0x42600000) /* bgezals */
16418 insn
^= 0x00400000;
16419 else if ((insn
& 0xffe30000) == 0x43800000 /* bc1f */
16420 || (insn
& 0xffe30000) == 0x43a00000 /* bc1t */
16421 || (insn
& 0xffe30000) == 0x42800000 /* bc2f */
16422 || (insn
& 0xffe30000) == 0x42a00000) /* bc2t */
16423 insn
^= 0x00200000;
16429 /* Clear the and-link and short-delay-slot bits. */
16430 gas_assert ((insn
& 0xfda00000) == 0x40200000);
16432 /* bltzal 0x40200000 bgezal 0x40600000 */
16433 /* bltzals 0x42200000 bgezals 0x42600000 */
16434 insn
&= ~0x02200000;
16437 /* Make a label at the end for use with the branch. */
16438 l
= symbol_new (micromips_label_name (), asec
, fragp
->fr_fix
, fragp
);
16439 micromips_label_inc ();
16440 S_SET_OTHER (l
, ELF_ST_SET_MICROMIPS (S_GET_OTHER (l
)));
16443 fixp
= fix_new (fragp
, buf
- fragp
->fr_literal
, 4, l
, 0, TRUE
,
16444 BFD_RELOC_MICROMIPS_16_PCREL_S1
);
16445 fixp
->fx_file
= fragp
->fr_file
;
16446 fixp
->fx_line
= fragp
->fr_line
;
16448 /* Branch over the jump. */
16449 buf
= write_compressed_insn (buf
, insn
, 4);
16452 buf
= write_compressed_insn (buf
, 0x0c00, 2);
16455 if (mips_pic
== NO_PIC
)
16457 unsigned long jal
= short_ds
? 0x74000000 : 0xf4000000; /* jal/s */
16459 /* j/jal/jals <sym> R_MICROMIPS_26_S1 */
16460 insn
= al
? jal
: 0xd4000000;
16462 fixp
= fix_new_exp (fragp
, buf
- fragp
->fr_literal
, 4, &exp
, FALSE
,
16463 BFD_RELOC_MICROMIPS_JMP
);
16464 fixp
->fx_file
= fragp
->fr_file
;
16465 fixp
->fx_line
= fragp
->fr_line
;
16467 buf
= write_compressed_insn (buf
, insn
, 4);
16470 buf
= write_compressed_insn (buf
, 0x0c00, 2);
16474 unsigned long at
= RELAX_MICROMIPS_AT (fragp
->fr_subtype
);
16475 unsigned long jalr
= short_ds
? 0x45e0 : 0x45c0; /* jalr/s */
16476 unsigned long jr
= compact
? 0x45a0 : 0x4580; /* jr/c */
16478 /* lw/ld $at, <sym>($gp) R_MICROMIPS_GOT16 */
16479 insn
= HAVE_64BIT_ADDRESSES
? 0xdc1c0000 : 0xfc1c0000;
16480 insn
|= at
<< MICROMIPSOP_SH_RT
;
16482 if (exp
.X_add_number
)
16484 exp
.X_add_symbol
= make_expr_symbol (&exp
);
16485 exp
.X_add_number
= 0;
16488 fixp
= fix_new_exp (fragp
, buf
- fragp
->fr_literal
, 4, &exp
, FALSE
,
16489 BFD_RELOC_MICROMIPS_GOT16
);
16490 fixp
->fx_file
= fragp
->fr_file
;
16491 fixp
->fx_line
= fragp
->fr_line
;
16493 buf
= write_compressed_insn (buf
, insn
, 4);
16495 /* d/addiu $at, $at, <sym> R_MICROMIPS_LO16 */
16496 insn
= HAVE_64BIT_ADDRESSES
? 0x5c000000 : 0x30000000;
16497 insn
|= at
<< MICROMIPSOP_SH_RT
| at
<< MICROMIPSOP_SH_RS
;
16499 fixp
= fix_new_exp (fragp
, buf
- fragp
->fr_literal
, 4, &exp
, FALSE
,
16500 BFD_RELOC_MICROMIPS_LO16
);
16501 fixp
->fx_file
= fragp
->fr_file
;
16502 fixp
->fx_line
= fragp
->fr_line
;
16504 buf
= write_compressed_insn (buf
, insn
, 4);
16506 /* jr/jrc/jalr/jalrs $at */
16507 insn
= al
? jalr
: jr
;
16508 insn
|= at
<< MICROMIPSOP_SH_MJ
;
16510 buf
= write_compressed_insn (buf
, insn
, 2);
16513 gas_assert (buf
== fragp
->fr_literal
+ fragp
->fr_fix
);
16517 if (RELAX_MIPS16_P (fragp
->fr_subtype
))
16520 const struct mips16_immed_operand
*op
;
16523 unsigned int user_length
, length
;
16524 unsigned long insn
;
16527 type
= RELAX_MIPS16_TYPE (fragp
->fr_subtype
);
16528 op
= mips16_immed_operands
;
16529 while (op
->type
!= type
)
16532 ext
= RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
);
16533 val
= resolve_symbol_value (fragp
->fr_symbol
);
16538 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
16540 /* The rules for the base address of a PC relative reloc are
16541 complicated; see mips16_extended_frag. */
16542 if (type
== 'p' || type
== 'q')
16547 /* Ignore the low bit in the target, since it will be
16548 set for a text label. */
16549 if ((val
& 1) != 0)
16552 else if (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
))
16554 else if (RELAX_MIPS16_DSLOT (fragp
->fr_subtype
))
16557 addr
&= ~ (addressT
) ((1 << op
->shift
) - 1);
16560 /* Make sure the section winds up with the alignment we have
16563 record_alignment (asec
, op
->shift
);
16567 && (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
)
16568 || RELAX_MIPS16_DSLOT (fragp
->fr_subtype
)))
16569 as_warn_where (fragp
->fr_file
, fragp
->fr_line
,
16570 _("extended instruction in delay slot"));
16572 buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
16574 insn
= read_compressed_insn (buf
, 2);
16576 insn
|= MIPS16_EXTEND
;
16578 if (RELAX_MIPS16_USER_EXT (fragp
->fr_subtype
))
16580 else if (RELAX_MIPS16_USER_SMALL (fragp
->fr_subtype
))
16585 mips16_immed (fragp
->fr_file
, fragp
->fr_line
, type
,
16586 BFD_RELOC_UNUSED
, val
, user_length
, &insn
);
16588 length
= (ext
? 4 : 2);
16589 gas_assert (mips16_opcode_length (insn
) == length
);
16590 write_compressed_insn (buf
, insn
, length
);
16591 fragp
->fr_fix
+= length
;
16595 relax_substateT subtype
= fragp
->fr_subtype
;
16596 bfd_boolean second_longer
= (subtype
& RELAX_SECOND_LONGER
) != 0;
16597 bfd_boolean use_second
= (subtype
& RELAX_USE_SECOND
) != 0;
16601 first
= RELAX_FIRST (subtype
);
16602 second
= RELAX_SECOND (subtype
);
16603 fixp
= (fixS
*) fragp
->fr_opcode
;
16605 /* If the delay slot chosen does not match the size of the instruction,
16606 then emit a warning. */
16607 if ((!use_second
&& (subtype
& RELAX_DELAY_SLOT_SIZE_FIRST
) != 0)
16608 || (use_second
&& (subtype
& RELAX_DELAY_SLOT_SIZE_SECOND
) != 0))
16613 s
= subtype
& (RELAX_DELAY_SLOT_16BIT
16614 | RELAX_DELAY_SLOT_SIZE_FIRST
16615 | RELAX_DELAY_SLOT_SIZE_SECOND
);
16616 msg
= macro_warning (s
);
16618 as_warn_where (fragp
->fr_file
, fragp
->fr_line
, "%s", msg
);
16622 /* Possibly emit a warning if we've chosen the longer option. */
16623 if (use_second
== second_longer
)
16629 & (RELAX_SECOND_LONGER
| RELAX_NOMACRO
| RELAX_DELAY_SLOT
));
16630 msg
= macro_warning (s
);
16632 as_warn_where (fragp
->fr_file
, fragp
->fr_line
, "%s", msg
);
16636 /* Go through all the fixups for the first sequence. Disable them
16637 (by marking them as done) if we're going to use the second
16638 sequence instead. */
16640 && fixp
->fx_frag
== fragp
16641 && fixp
->fx_where
< fragp
->fr_fix
- second
)
16643 if (subtype
& RELAX_USE_SECOND
)
16645 fixp
= fixp
->fx_next
;
16648 /* Go through the fixups for the second sequence. Disable them if
16649 we're going to use the first sequence, otherwise adjust their
16650 addresses to account for the relaxation. */
16651 while (fixp
&& fixp
->fx_frag
== fragp
)
16653 if (subtype
& RELAX_USE_SECOND
)
16654 fixp
->fx_where
-= first
;
16657 fixp
= fixp
->fx_next
;
16660 /* Now modify the frag contents. */
16661 if (subtype
& RELAX_USE_SECOND
)
16665 start
= fragp
->fr_literal
+ fragp
->fr_fix
- first
- second
;
16666 memmove (start
, start
+ first
, second
);
16667 fragp
->fr_fix
-= first
;
16670 fragp
->fr_fix
-= second
;
16674 /* This function is called after the relocs have been generated.
16675 We've been storing mips16 text labels as odd. Here we convert them
16676 back to even for the convenience of the debugger. */
16679 mips_frob_file_after_relocs (void)
16682 unsigned int count
, i
;
16684 syms
= bfd_get_outsymbols (stdoutput
);
16685 count
= bfd_get_symcount (stdoutput
);
16686 for (i
= 0; i
< count
; i
++, syms
++)
16687 if (ELF_ST_IS_COMPRESSED (elf_symbol (*syms
)->internal_elf_sym
.st_other
)
16688 && ((*syms
)->value
& 1) != 0)
16690 (*syms
)->value
&= ~1;
16691 /* If the symbol has an odd size, it was probably computed
16692 incorrectly, so adjust that as well. */
16693 if ((elf_symbol (*syms
)->internal_elf_sym
.st_size
& 1) != 0)
16694 ++elf_symbol (*syms
)->internal_elf_sym
.st_size
;
16698 /* This function is called whenever a label is defined, including fake
16699 labels instantiated off the dot special symbol. It is used when
16700 handling branch delays; if a branch has a label, we assume we cannot
16701 move it. This also bumps the value of the symbol by 1 in compressed
16705 mips_record_label (symbolS
*sym
)
16707 segment_info_type
*si
= seg_info (now_seg
);
16708 struct insn_label_list
*l
;
16710 if (free_insn_labels
== NULL
)
16711 l
= (struct insn_label_list
*) xmalloc (sizeof *l
);
16714 l
= free_insn_labels
;
16715 free_insn_labels
= l
->next
;
16719 l
->next
= si
->label_list
;
16720 si
->label_list
= l
;
16723 /* This function is called as tc_frob_label() whenever a label is defined
16724 and adds a DWARF-2 record we only want for true labels. */
16727 mips_define_label (symbolS
*sym
)
16729 mips_record_label (sym
);
16730 dwarf2_emit_label (sym
);
16733 /* This function is called by tc_new_dot_label whenever a new dot symbol
16737 mips_add_dot_label (symbolS
*sym
)
16739 mips_record_label (sym
);
16740 if (mips_assembling_insn
&& HAVE_CODE_COMPRESSION
)
16741 mips_compressed_mark_label (sym
);
16744 /* Some special processing for a MIPS ELF file. */
16747 mips_elf_final_processing (void)
16749 /* Write out the register information. */
16750 if (mips_abi
!= N64_ABI
)
16754 s
.ri_gprmask
= mips_gprmask
;
16755 s
.ri_cprmask
[0] = mips_cprmask
[0];
16756 s
.ri_cprmask
[1] = mips_cprmask
[1];
16757 s
.ri_cprmask
[2] = mips_cprmask
[2];
16758 s
.ri_cprmask
[3] = mips_cprmask
[3];
16759 /* The gp_value field is set by the MIPS ELF backend. */
16761 bfd_mips_elf32_swap_reginfo_out (stdoutput
, &s
,
16762 ((Elf32_External_RegInfo
*)
16763 mips_regmask_frag
));
16767 Elf64_Internal_RegInfo s
;
16769 s
.ri_gprmask
= mips_gprmask
;
16771 s
.ri_cprmask
[0] = mips_cprmask
[0];
16772 s
.ri_cprmask
[1] = mips_cprmask
[1];
16773 s
.ri_cprmask
[2] = mips_cprmask
[2];
16774 s
.ri_cprmask
[3] = mips_cprmask
[3];
16775 /* The gp_value field is set by the MIPS ELF backend. */
16777 bfd_mips_elf64_swap_reginfo_out (stdoutput
, &s
,
16778 ((Elf64_External_RegInfo
*)
16779 mips_regmask_frag
));
16782 /* Set the MIPS ELF flag bits. FIXME: There should probably be some
16783 sort of BFD interface for this. */
16784 if (mips_any_noreorder
)
16785 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_NOREORDER
;
16786 if (mips_pic
!= NO_PIC
)
16788 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_PIC
;
16789 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_CPIC
;
16792 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_CPIC
;
16794 /* Set MIPS ELF flags for ASEs. Note that not all ASEs have flags
16795 defined at present; this might need to change in future. */
16796 if (file_ase_mips16
)
16797 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ARCH_ASE_M16
;
16798 if (file_ase_micromips
)
16799 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ARCH_ASE_MICROMIPS
;
16800 if (file_ase
& ASE_MDMX
)
16801 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ARCH_ASE_MDMX
;
16803 /* Set the MIPS ELF ABI flags. */
16804 if (mips_abi
== O32_ABI
&& USE_E_MIPS_ABI_O32
)
16805 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_O32
;
16806 else if (mips_abi
== O64_ABI
)
16807 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_O64
;
16808 else if (mips_abi
== EABI_ABI
)
16810 if (!file_mips_gp32
)
16811 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_EABI64
;
16813 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_EABI32
;
16815 else if (mips_abi
== N32_ABI
)
16816 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ABI2
;
16818 /* Nothing to do for N64_ABI. */
16820 if (mips_32bitmode
)
16821 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_32BITMODE
;
16823 if (mips_flag_nan2008
)
16824 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_NAN2008
;
16826 #if 0 /* XXX FIXME */
16827 /* 32 bit code with 64 bit FP registers. */
16828 if (!file_mips_fp32
&& ABI_NEEDS_32BIT_REGS (mips_abi
))
16829 elf_elfheader (stdoutput
)->e_flags
|= ???;
16833 typedef struct proc
{
16835 symbolS
*func_end_sym
;
16836 unsigned long reg_mask
;
16837 unsigned long reg_offset
;
16838 unsigned long fpreg_mask
;
16839 unsigned long fpreg_offset
;
16840 unsigned long frame_offset
;
16841 unsigned long frame_reg
;
16842 unsigned long pc_reg
;
16845 static procS cur_proc
;
16846 static procS
*cur_proc_ptr
;
16847 static int numprocs
;
16849 /* Implement NOP_OPCODE. We encode a MIPS16 nop as "1", a microMIPS nop
16850 as "2", and a normal nop as "0". */
16852 #define NOP_OPCODE_MIPS 0
16853 #define NOP_OPCODE_MIPS16 1
16854 #define NOP_OPCODE_MICROMIPS 2
16857 mips_nop_opcode (void)
16859 if (seg_info (now_seg
)->tc_segment_info_data
.micromips
)
16860 return NOP_OPCODE_MICROMIPS
;
16861 else if (seg_info (now_seg
)->tc_segment_info_data
.mips16
)
16862 return NOP_OPCODE_MIPS16
;
16864 return NOP_OPCODE_MIPS
;
16867 /* Fill in an rs_align_code fragment. Unlike elsewhere we want to use
16868 32-bit microMIPS NOPs here (if applicable). */
16871 mips_handle_align (fragS
*fragp
)
16875 int bytes
, size
, excess
;
16878 if (fragp
->fr_type
!= rs_align_code
)
16881 p
= fragp
->fr_literal
+ fragp
->fr_fix
;
16883 switch (nop_opcode
)
16885 case NOP_OPCODE_MICROMIPS
:
16886 opcode
= micromips_nop32_insn
.insn_opcode
;
16889 case NOP_OPCODE_MIPS16
:
16890 opcode
= mips16_nop_insn
.insn_opcode
;
16893 case NOP_OPCODE_MIPS
:
16895 opcode
= nop_insn
.insn_opcode
;
16900 bytes
= fragp
->fr_next
->fr_address
- fragp
->fr_address
- fragp
->fr_fix
;
16901 excess
= bytes
% size
;
16903 /* Handle the leading part if we're not inserting a whole number of
16904 instructions, and make it the end of the fixed part of the frag.
16905 Try to fit in a short microMIPS NOP if applicable and possible,
16906 and use zeroes otherwise. */
16907 gas_assert (excess
< 4);
16908 fragp
->fr_fix
+= excess
;
16913 /* Fall through. */
16915 if (nop_opcode
== NOP_OPCODE_MICROMIPS
&& !mips_opts
.insn32
)
16917 p
= write_compressed_insn (p
, micromips_nop16_insn
.insn_opcode
, 2);
16921 /* Fall through. */
16924 /* Fall through. */
16929 md_number_to_chars (p
, opcode
, size
);
16930 fragp
->fr_var
= size
;
16934 md_obj_begin (void)
16941 /* Check for premature end, nesting errors, etc. */
16943 as_warn (_("missing .end at end of assembly"));
16952 if (*input_line_pointer
== '-')
16954 ++input_line_pointer
;
16957 if (!ISDIGIT (*input_line_pointer
))
16958 as_bad (_("expected simple number"));
16959 if (input_line_pointer
[0] == '0')
16961 if (input_line_pointer
[1] == 'x')
16963 input_line_pointer
+= 2;
16964 while (ISXDIGIT (*input_line_pointer
))
16967 val
|= hex_value (*input_line_pointer
++);
16969 return negative
? -val
: val
;
16973 ++input_line_pointer
;
16974 while (ISDIGIT (*input_line_pointer
))
16977 val
|= *input_line_pointer
++ - '0';
16979 return negative
? -val
: val
;
16982 if (!ISDIGIT (*input_line_pointer
))
16984 printf (_(" *input_line_pointer == '%c' 0x%02x\n"),
16985 *input_line_pointer
, *input_line_pointer
);
16986 as_warn (_("invalid number"));
16989 while (ISDIGIT (*input_line_pointer
))
16992 val
+= *input_line_pointer
++ - '0';
16994 return negative
? -val
: val
;
16997 /* The .file directive; just like the usual .file directive, but there
16998 is an initial number which is the ECOFF file index. In the non-ECOFF
16999 case .file implies DWARF-2. */
17002 s_mips_file (int x ATTRIBUTE_UNUSED
)
17004 static int first_file_directive
= 0;
17006 if (ECOFF_DEBUGGING
)
17015 filename
= dwarf2_directive_file (0);
17017 /* Versions of GCC up to 3.1 start files with a ".file"
17018 directive even for stabs output. Make sure that this
17019 ".file" is handled. Note that you need a version of GCC
17020 after 3.1 in order to support DWARF-2 on MIPS. */
17021 if (filename
!= NULL
&& ! first_file_directive
)
17023 (void) new_logical_line (filename
, -1);
17024 s_app_file_string (filename
, 0);
17026 first_file_directive
= 1;
17030 /* The .loc directive, implying DWARF-2. */
17033 s_mips_loc (int x ATTRIBUTE_UNUSED
)
17035 if (!ECOFF_DEBUGGING
)
17036 dwarf2_directive_loc (0);
17039 /* The .end directive. */
17042 s_mips_end (int x ATTRIBUTE_UNUSED
)
17046 /* Following functions need their own .frame and .cprestore directives. */
17047 mips_frame_reg_valid
= 0;
17048 mips_cprestore_valid
= 0;
17050 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
17053 demand_empty_rest_of_line ();
17058 if ((bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) == 0)
17059 as_warn (_(".end not in text section"));
17063 as_warn (_(".end directive without a preceding .ent directive."));
17064 demand_empty_rest_of_line ();
17070 gas_assert (S_GET_NAME (p
));
17071 if (strcmp (S_GET_NAME (p
), S_GET_NAME (cur_proc_ptr
->func_sym
)))
17072 as_warn (_(".end symbol does not match .ent symbol."));
17074 if (debug_type
== DEBUG_STABS
)
17075 stabs_generate_asm_endfunc (S_GET_NAME (p
),
17079 as_warn (_(".end directive missing or unknown symbol"));
17081 /* Create an expression to calculate the size of the function. */
17082 if (p
&& cur_proc_ptr
)
17084 OBJ_SYMFIELD_TYPE
*obj
= symbol_get_obj (p
);
17085 expressionS
*exp
= xmalloc (sizeof (expressionS
));
17088 exp
->X_op
= O_subtract
;
17089 exp
->X_add_symbol
= symbol_temp_new_now ();
17090 exp
->X_op_symbol
= p
;
17091 exp
->X_add_number
= 0;
17093 cur_proc_ptr
->func_end_sym
= exp
->X_add_symbol
;
17096 /* Generate a .pdr section. */
17097 if (!ECOFF_DEBUGGING
&& mips_flag_pdr
)
17099 segT saved_seg
= now_seg
;
17100 subsegT saved_subseg
= now_subseg
;
17104 #ifdef md_flush_pending_output
17105 md_flush_pending_output ();
17108 gas_assert (pdr_seg
);
17109 subseg_set (pdr_seg
, 0);
17111 /* Write the symbol. */
17112 exp
.X_op
= O_symbol
;
17113 exp
.X_add_symbol
= p
;
17114 exp
.X_add_number
= 0;
17115 emit_expr (&exp
, 4);
17117 fragp
= frag_more (7 * 4);
17119 md_number_to_chars (fragp
, cur_proc_ptr
->reg_mask
, 4);
17120 md_number_to_chars (fragp
+ 4, cur_proc_ptr
->reg_offset
, 4);
17121 md_number_to_chars (fragp
+ 8, cur_proc_ptr
->fpreg_mask
, 4);
17122 md_number_to_chars (fragp
+ 12, cur_proc_ptr
->fpreg_offset
, 4);
17123 md_number_to_chars (fragp
+ 16, cur_proc_ptr
->frame_offset
, 4);
17124 md_number_to_chars (fragp
+ 20, cur_proc_ptr
->frame_reg
, 4);
17125 md_number_to_chars (fragp
+ 24, cur_proc_ptr
->pc_reg
, 4);
17127 subseg_set (saved_seg
, saved_subseg
);
17130 cur_proc_ptr
= NULL
;
17133 /* The .aent and .ent directives. */
17136 s_mips_ent (int aent
)
17140 symbolP
= get_symbol ();
17141 if (*input_line_pointer
== ',')
17142 ++input_line_pointer
;
17143 SKIP_WHITESPACE ();
17144 if (ISDIGIT (*input_line_pointer
)
17145 || *input_line_pointer
== '-')
17148 if ((bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) == 0)
17149 as_warn (_(".ent or .aent not in text section."));
17151 if (!aent
&& cur_proc_ptr
)
17152 as_warn (_("missing .end"));
17156 /* This function needs its own .frame and .cprestore directives. */
17157 mips_frame_reg_valid
= 0;
17158 mips_cprestore_valid
= 0;
17160 cur_proc_ptr
= &cur_proc
;
17161 memset (cur_proc_ptr
, '\0', sizeof (procS
));
17163 cur_proc_ptr
->func_sym
= symbolP
;
17167 if (debug_type
== DEBUG_STABS
)
17168 stabs_generate_asm_func (S_GET_NAME (symbolP
),
17169 S_GET_NAME (symbolP
));
17172 symbol_get_bfdsym (symbolP
)->flags
|= BSF_FUNCTION
;
17174 demand_empty_rest_of_line ();
17177 /* The .frame directive. If the mdebug section is present (IRIX 5 native)
17178 then ecoff.c (ecoff_directive_frame) is used. For embedded targets,
17179 s_mips_frame is used so that we can set the PDR information correctly.
17180 We can't use the ecoff routines because they make reference to the ecoff
17181 symbol table (in the mdebug section). */
17184 s_mips_frame (int ignore ATTRIBUTE_UNUSED
)
17186 if (ECOFF_DEBUGGING
)
17192 if (cur_proc_ptr
== (procS
*) NULL
)
17194 as_warn (_(".frame outside of .ent"));
17195 demand_empty_rest_of_line ();
17199 cur_proc_ptr
->frame_reg
= tc_get_register (1);
17201 SKIP_WHITESPACE ();
17202 if (*input_line_pointer
++ != ','
17203 || get_absolute_expression_and_terminator (&val
) != ',')
17205 as_warn (_("Bad .frame directive"));
17206 --input_line_pointer
;
17207 demand_empty_rest_of_line ();
17211 cur_proc_ptr
->frame_offset
= val
;
17212 cur_proc_ptr
->pc_reg
= tc_get_register (0);
17214 demand_empty_rest_of_line ();
17218 /* The .fmask and .mask directives. If the mdebug section is present
17219 (IRIX 5 native) then ecoff.c (ecoff_directive_mask) is used. For
17220 embedded targets, s_mips_mask is used so that we can set the PDR
17221 information correctly. We can't use the ecoff routines because they
17222 make reference to the ecoff symbol table (in the mdebug section). */
17225 s_mips_mask (int reg_type
)
17227 if (ECOFF_DEBUGGING
)
17228 s_ignore (reg_type
);
17233 if (cur_proc_ptr
== (procS
*) NULL
)
17235 as_warn (_(".mask/.fmask outside of .ent"));
17236 demand_empty_rest_of_line ();
17240 if (get_absolute_expression_and_terminator (&mask
) != ',')
17242 as_warn (_("Bad .mask/.fmask directive"));
17243 --input_line_pointer
;
17244 demand_empty_rest_of_line ();
17248 off
= get_absolute_expression ();
17250 if (reg_type
== 'F')
17252 cur_proc_ptr
->fpreg_mask
= mask
;
17253 cur_proc_ptr
->fpreg_offset
= off
;
17257 cur_proc_ptr
->reg_mask
= mask
;
17258 cur_proc_ptr
->reg_offset
= off
;
17261 demand_empty_rest_of_line ();
17265 /* A table describing all the processors gas knows about. Names are
17266 matched in the order listed.
17268 To ease comparison, please keep this table in the same order as
17269 gcc's mips_cpu_info_table[]. */
17270 static const struct mips_cpu_info mips_cpu_info_table
[] =
17272 /* Entries for generic ISAs */
17273 { "mips1", MIPS_CPU_IS_ISA
, 0, ISA_MIPS1
, CPU_R3000
},
17274 { "mips2", MIPS_CPU_IS_ISA
, 0, ISA_MIPS2
, CPU_R6000
},
17275 { "mips3", MIPS_CPU_IS_ISA
, 0, ISA_MIPS3
, CPU_R4000
},
17276 { "mips4", MIPS_CPU_IS_ISA
, 0, ISA_MIPS4
, CPU_R8000
},
17277 { "mips5", MIPS_CPU_IS_ISA
, 0, ISA_MIPS5
, CPU_MIPS5
},
17278 { "mips32", MIPS_CPU_IS_ISA
, 0, ISA_MIPS32
, CPU_MIPS32
},
17279 { "mips32r2", MIPS_CPU_IS_ISA
, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
17280 { "mips64", MIPS_CPU_IS_ISA
, 0, ISA_MIPS64
, CPU_MIPS64
},
17281 { "mips64r2", MIPS_CPU_IS_ISA
, 0, ISA_MIPS64R2
, CPU_MIPS64R2
},
17284 { "r3000", 0, 0, ISA_MIPS1
, CPU_R3000
},
17285 { "r2000", 0, 0, ISA_MIPS1
, CPU_R3000
},
17286 { "r3900", 0, 0, ISA_MIPS1
, CPU_R3900
},
17289 { "r6000", 0, 0, ISA_MIPS2
, CPU_R6000
},
17292 { "r4000", 0, 0, ISA_MIPS3
, CPU_R4000
},
17293 { "r4010", 0, 0, ISA_MIPS2
, CPU_R4010
},
17294 { "vr4100", 0, 0, ISA_MIPS3
, CPU_VR4100
},
17295 { "vr4111", 0, 0, ISA_MIPS3
, CPU_R4111
},
17296 { "vr4120", 0, 0, ISA_MIPS3
, CPU_VR4120
},
17297 { "vr4130", 0, 0, ISA_MIPS3
, CPU_VR4120
},
17298 { "vr4181", 0, 0, ISA_MIPS3
, CPU_R4111
},
17299 { "vr4300", 0, 0, ISA_MIPS3
, CPU_R4300
},
17300 { "r4400", 0, 0, ISA_MIPS3
, CPU_R4400
},
17301 { "r4600", 0, 0, ISA_MIPS3
, CPU_R4600
},
17302 { "orion", 0, 0, ISA_MIPS3
, CPU_R4600
},
17303 { "r4650", 0, 0, ISA_MIPS3
, CPU_R4650
},
17304 { "r5900", 0, 0, ISA_MIPS3
, CPU_R5900
},
17305 /* ST Microelectronics Loongson 2E and 2F cores */
17306 { "loongson2e", 0, 0, ISA_MIPS3
, CPU_LOONGSON_2E
},
17307 { "loongson2f", 0, 0, ISA_MIPS3
, CPU_LOONGSON_2F
},
17310 { "r8000", 0, 0, ISA_MIPS4
, CPU_R8000
},
17311 { "r10000", 0, 0, ISA_MIPS4
, CPU_R10000
},
17312 { "r12000", 0, 0, ISA_MIPS4
, CPU_R12000
},
17313 { "r14000", 0, 0, ISA_MIPS4
, CPU_R14000
},
17314 { "r16000", 0, 0, ISA_MIPS4
, CPU_R16000
},
17315 { "vr5000", 0, 0, ISA_MIPS4
, CPU_R5000
},
17316 { "vr5400", 0, 0, ISA_MIPS4
, CPU_VR5400
},
17317 { "vr5500", 0, 0, ISA_MIPS4
, CPU_VR5500
},
17318 { "rm5200", 0, 0, ISA_MIPS4
, CPU_R5000
},
17319 { "rm5230", 0, 0, ISA_MIPS4
, CPU_R5000
},
17320 { "rm5231", 0, 0, ISA_MIPS4
, CPU_R5000
},
17321 { "rm5261", 0, 0, ISA_MIPS4
, CPU_R5000
},
17322 { "rm5721", 0, 0, ISA_MIPS4
, CPU_R5000
},
17323 { "rm7000", 0, 0, ISA_MIPS4
, CPU_RM7000
},
17324 { "rm9000", 0, 0, ISA_MIPS4
, CPU_RM9000
},
17327 { "4kc", 0, 0, ISA_MIPS32
, CPU_MIPS32
},
17328 { "4km", 0, 0, ISA_MIPS32
, CPU_MIPS32
},
17329 { "4kp", 0, 0, ISA_MIPS32
, CPU_MIPS32
},
17330 { "4ksc", 0, ASE_SMARTMIPS
, ISA_MIPS32
, CPU_MIPS32
},
17332 /* MIPS 32 Release 2 */
17333 { "4kec", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
17334 { "4kem", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
17335 { "4kep", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
17336 { "4ksd", 0, ASE_SMARTMIPS
, ISA_MIPS32R2
, CPU_MIPS32R2
},
17337 { "m4k", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
17338 { "m4kp", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
17339 { "m14k", 0, ASE_MCU
, ISA_MIPS32R2
, CPU_MIPS32R2
},
17340 { "m14kc", 0, ASE_MCU
, ISA_MIPS32R2
, CPU_MIPS32R2
},
17341 { "m14ke", 0, ASE_DSP
| ASE_DSPR2
| ASE_MCU
,
17342 ISA_MIPS32R2
, CPU_MIPS32R2
},
17343 { "m14kec", 0, ASE_DSP
| ASE_DSPR2
| ASE_MCU
,
17344 ISA_MIPS32R2
, CPU_MIPS32R2
},
17345 { "24kc", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
17346 { "24kf2_1", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
17347 { "24kf", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
17348 { "24kf1_1", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
17349 /* Deprecated forms of the above. */
17350 { "24kfx", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
17351 { "24kx", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
17352 /* 24KE is a 24K with DSP ASE, other ASEs are optional. */
17353 { "24kec", 0, ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
17354 { "24kef2_1", 0, ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
17355 { "24kef", 0, ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
17356 { "24kef1_1", 0, ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
17357 /* Deprecated forms of the above. */
17358 { "24kefx", 0, ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
17359 { "24kex", 0, ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
17360 /* 34K is a 24K with DSP and MT ASE, other ASEs are optional. */
17361 { "34kc", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
17362 { "34kf2_1", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
17363 { "34kf", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
17364 { "34kf1_1", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
17365 /* Deprecated forms of the above. */
17366 { "34kfx", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
17367 { "34kx", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
17368 /* 34Kn is a 34kc without DSP. */
17369 { "34kn", 0, ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
17370 /* 74K with DSP and DSPR2 ASE, other ASEs are optional. */
17371 { "74kc", 0, ASE_DSP
| ASE_DSPR2
, ISA_MIPS32R2
, CPU_MIPS32R2
},
17372 { "74kf2_1", 0, ASE_DSP
| ASE_DSPR2
, ISA_MIPS32R2
, CPU_MIPS32R2
},
17373 { "74kf", 0, ASE_DSP
| ASE_DSPR2
, ISA_MIPS32R2
, CPU_MIPS32R2
},
17374 { "74kf1_1", 0, ASE_DSP
| ASE_DSPR2
, ISA_MIPS32R2
, CPU_MIPS32R2
},
17375 { "74kf3_2", 0, ASE_DSP
| ASE_DSPR2
, ISA_MIPS32R2
, CPU_MIPS32R2
},
17376 /* Deprecated forms of the above. */
17377 { "74kfx", 0, ASE_DSP
| ASE_DSPR2
, ISA_MIPS32R2
, CPU_MIPS32R2
},
17378 { "74kx", 0, ASE_DSP
| ASE_DSPR2
, ISA_MIPS32R2
, CPU_MIPS32R2
},
17379 /* 1004K cores are multiprocessor versions of the 34K. */
17380 { "1004kc", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
17381 { "1004kf2_1", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
17382 { "1004kf", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
17383 { "1004kf1_1", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
17386 { "5kc", 0, 0, ISA_MIPS64
, CPU_MIPS64
},
17387 { "5kf", 0, 0, ISA_MIPS64
, CPU_MIPS64
},
17388 { "20kc", 0, ASE_MIPS3D
, ISA_MIPS64
, CPU_MIPS64
},
17389 { "25kf", 0, ASE_MIPS3D
, ISA_MIPS64
, CPU_MIPS64
},
17391 /* Broadcom SB-1 CPU core */
17392 { "sb1", 0, ASE_MIPS3D
| ASE_MDMX
, ISA_MIPS64
, CPU_SB1
},
17393 /* Broadcom SB-1A CPU core */
17394 { "sb1a", 0, ASE_MIPS3D
| ASE_MDMX
, ISA_MIPS64
, CPU_SB1
},
17396 { "loongson3a", 0, 0, ISA_MIPS64
, CPU_LOONGSON_3A
},
17398 /* MIPS 64 Release 2 */
17400 /* Cavium Networks Octeon CPU core */
17401 { "octeon", 0, 0, ISA_MIPS64R2
, CPU_OCTEON
},
17402 { "octeon+", 0, 0, ISA_MIPS64R2
, CPU_OCTEONP
},
17403 { "octeon2", 0, 0, ISA_MIPS64R2
, CPU_OCTEON2
},
17406 { "xlr", 0, 0, ISA_MIPS64
, CPU_XLR
},
17409 XLP is mostly like XLR, with the prominent exception that it is
17410 MIPS64R2 rather than MIPS64. */
17411 { "xlp", 0, 0, ISA_MIPS64R2
, CPU_XLR
},
17414 { NULL
, 0, 0, 0, 0 }
17418 /* Return true if GIVEN is the same as CANONICAL, or if it is CANONICAL
17419 with a final "000" replaced by "k". Ignore case.
17421 Note: this function is shared between GCC and GAS. */
17424 mips_strict_matching_cpu_name_p (const char *canonical
, const char *given
)
17426 while (*given
!= 0 && TOLOWER (*given
) == TOLOWER (*canonical
))
17427 given
++, canonical
++;
17429 return ((*given
== 0 && *canonical
== 0)
17430 || (strcmp (canonical
, "000") == 0 && strcasecmp (given
, "k") == 0));
17434 /* Return true if GIVEN matches CANONICAL, where GIVEN is a user-supplied
17435 CPU name. We've traditionally allowed a lot of variation here.
17437 Note: this function is shared between GCC and GAS. */
17440 mips_matching_cpu_name_p (const char *canonical
, const char *given
)
17442 /* First see if the name matches exactly, or with a final "000"
17443 turned into "k". */
17444 if (mips_strict_matching_cpu_name_p (canonical
, given
))
17447 /* If not, try comparing based on numerical designation alone.
17448 See if GIVEN is an unadorned number, or 'r' followed by a number. */
17449 if (TOLOWER (*given
) == 'r')
17451 if (!ISDIGIT (*given
))
17454 /* Skip over some well-known prefixes in the canonical name,
17455 hoping to find a number there too. */
17456 if (TOLOWER (canonical
[0]) == 'v' && TOLOWER (canonical
[1]) == 'r')
17458 else if (TOLOWER (canonical
[0]) == 'r' && TOLOWER (canonical
[1]) == 'm')
17460 else if (TOLOWER (canonical
[0]) == 'r')
17463 return mips_strict_matching_cpu_name_p (canonical
, given
);
17467 /* Parse an option that takes the name of a processor as its argument.
17468 OPTION is the name of the option and CPU_STRING is the argument.
17469 Return the corresponding processor enumeration if the CPU_STRING is
17470 recognized, otherwise report an error and return null.
17472 A similar function exists in GCC. */
17474 static const struct mips_cpu_info
*
17475 mips_parse_cpu (const char *option
, const char *cpu_string
)
17477 const struct mips_cpu_info
*p
;
17479 /* 'from-abi' selects the most compatible architecture for the given
17480 ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit ABIs. For the
17481 EABIs, we have to decide whether we're using the 32-bit or 64-bit
17482 version. Look first at the -mgp options, if given, otherwise base
17483 the choice on MIPS_DEFAULT_64BIT.
17485 Treat NO_ABI like the EABIs. One reason to do this is that the
17486 plain 'mips' and 'mips64' configs have 'from-abi' as their default
17487 architecture. This code picks MIPS I for 'mips' and MIPS III for
17488 'mips64', just as we did in the days before 'from-abi'. */
17489 if (strcasecmp (cpu_string
, "from-abi") == 0)
17491 if (ABI_NEEDS_32BIT_REGS (mips_abi
))
17492 return mips_cpu_info_from_isa (ISA_MIPS1
);
17494 if (ABI_NEEDS_64BIT_REGS (mips_abi
))
17495 return mips_cpu_info_from_isa (ISA_MIPS3
);
17497 if (file_mips_gp32
>= 0)
17498 return mips_cpu_info_from_isa (file_mips_gp32
? ISA_MIPS1
: ISA_MIPS3
);
17500 return mips_cpu_info_from_isa (MIPS_DEFAULT_64BIT
17505 /* 'default' has traditionally been a no-op. Probably not very useful. */
17506 if (strcasecmp (cpu_string
, "default") == 0)
17509 for (p
= mips_cpu_info_table
; p
->name
!= 0; p
++)
17510 if (mips_matching_cpu_name_p (p
->name
, cpu_string
))
17513 as_bad (_("Bad value (%s) for %s"), cpu_string
, option
);
17517 /* Return the canonical processor information for ISA (a member of the
17518 ISA_MIPS* enumeration). */
17520 static const struct mips_cpu_info
*
17521 mips_cpu_info_from_isa (int isa
)
17525 for (i
= 0; mips_cpu_info_table
[i
].name
!= NULL
; i
++)
17526 if ((mips_cpu_info_table
[i
].flags
& MIPS_CPU_IS_ISA
)
17527 && isa
== mips_cpu_info_table
[i
].isa
)
17528 return (&mips_cpu_info_table
[i
]);
17533 static const struct mips_cpu_info
*
17534 mips_cpu_info_from_arch (int arch
)
17538 for (i
= 0; mips_cpu_info_table
[i
].name
!= NULL
; i
++)
17539 if (arch
== mips_cpu_info_table
[i
].cpu
)
17540 return (&mips_cpu_info_table
[i
]);
17546 show (FILE *stream
, const char *string
, int *col_p
, int *first_p
)
17550 fprintf (stream
, "%24s", "");
17555 fprintf (stream
, ", ");
17559 if (*col_p
+ strlen (string
) > 72)
17561 fprintf (stream
, "\n%24s", "");
17565 fprintf (stream
, "%s", string
);
17566 *col_p
+= strlen (string
);
17572 md_show_usage (FILE *stream
)
17577 fprintf (stream
, _("\
17579 -EB generate big endian output\n\
17580 -EL generate little endian output\n\
17581 -g, -g2 do not remove unneeded NOPs or swap branches\n\
17582 -G NUM allow referencing objects up to NUM bytes\n\
17583 implicitly with the gp register [default 8]\n"));
17584 fprintf (stream
, _("\
17585 -mips1 generate MIPS ISA I instructions\n\
17586 -mips2 generate MIPS ISA II instructions\n\
17587 -mips3 generate MIPS ISA III instructions\n\
17588 -mips4 generate MIPS ISA IV instructions\n\
17589 -mips5 generate MIPS ISA V instructions\n\
17590 -mips32 generate MIPS32 ISA instructions\n\
17591 -mips32r2 generate MIPS32 release 2 ISA instructions\n\
17592 -mips64 generate MIPS64 ISA instructions\n\
17593 -mips64r2 generate MIPS64 release 2 ISA instructions\n\
17594 -march=CPU/-mtune=CPU generate code/schedule for CPU, where CPU is one of:\n"));
17598 for (i
= 0; mips_cpu_info_table
[i
].name
!= NULL
; i
++)
17599 show (stream
, mips_cpu_info_table
[i
].name
, &column
, &first
);
17600 show (stream
, "from-abi", &column
, &first
);
17601 fputc ('\n', stream
);
17603 fprintf (stream
, _("\
17604 -mCPU equivalent to -march=CPU -mtune=CPU. Deprecated.\n\
17605 -no-mCPU don't generate code specific to CPU.\n\
17606 For -mCPU and -no-mCPU, CPU must be one of:\n"));
17610 show (stream
, "3900", &column
, &first
);
17611 show (stream
, "4010", &column
, &first
);
17612 show (stream
, "4100", &column
, &first
);
17613 show (stream
, "4650", &column
, &first
);
17614 fputc ('\n', stream
);
17616 fprintf (stream
, _("\
17617 -mips16 generate mips16 instructions\n\
17618 -no-mips16 do not generate mips16 instructions\n"));
17619 fprintf (stream
, _("\
17620 -mmicromips generate microMIPS instructions\n\
17621 -mno-micromips do not generate microMIPS instructions\n"));
17622 fprintf (stream
, _("\
17623 -msmartmips generate smartmips instructions\n\
17624 -mno-smartmips do not generate smartmips instructions\n"));
17625 fprintf (stream
, _("\
17626 -mdsp generate DSP instructions\n\
17627 -mno-dsp do not generate DSP instructions\n"));
17628 fprintf (stream
, _("\
17629 -mdspr2 generate DSP R2 instructions\n\
17630 -mno-dspr2 do not generate DSP R2 instructions\n"));
17631 fprintf (stream
, _("\
17632 -mmt generate MT instructions\n\
17633 -mno-mt do not generate MT instructions\n"));
17634 fprintf (stream
, _("\
17635 -mmcu generate MCU instructions\n\
17636 -mno-mcu do not generate MCU instructions\n"));
17637 fprintf (stream
, _("\
17638 -mvirt generate Virtualization instructions\n\
17639 -mno-virt do not generate Virtualization instructions\n"));
17640 fprintf (stream
, _("\
17641 -minsn32 only generate 32-bit microMIPS instructions\n\
17642 -mno-insn32 generate all microMIPS instructions\n"));
17643 fprintf (stream
, _("\
17644 -mfix-loongson2f-jump work around Loongson2F JUMP instructions\n\
17645 -mfix-loongson2f-nop work around Loongson2F NOP errata\n\
17646 -mfix-vr4120 work around certain VR4120 errata\n\
17647 -mfix-vr4130 work around VR4130 mflo/mfhi errata\n\
17648 -mfix-24k insert a nop after ERET and DERET instructions\n\
17649 -mfix-cn63xxp1 work around CN63XXP1 PREF errata\n\
17650 -mgp32 use 32-bit GPRs, regardless of the chosen ISA\n\
17651 -mfp32 use 32-bit FPRs, regardless of the chosen ISA\n\
17652 -msym32 assume all symbols have 32-bit values\n\
17653 -O0 remove unneeded NOPs, do not swap branches\n\
17654 -O remove unneeded NOPs and swap branches\n\
17655 --trap, --no-break trap exception on div by 0 and mult overflow\n\
17656 --break, --no-trap break exception on div by 0 and mult overflow\n"));
17657 fprintf (stream
, _("\
17658 -mhard-float allow floating-point instructions\n\
17659 -msoft-float do not allow floating-point instructions\n\
17660 -msingle-float only allow 32-bit floating-point operations\n\
17661 -mdouble-float allow 32-bit and 64-bit floating-point operations\n\
17662 --[no-]construct-floats [dis]allow floating point values to be constructed\n\
17663 --[no-]relax-branch [dis]allow out-of-range branches to be relaxed\n\
17664 -mnan=ENCODING select an IEEE 754 NaN encoding convention, either of:\n"));
17668 show (stream
, "legacy", &column
, &first
);
17669 show (stream
, "2008", &column
, &first
);
17671 fputc ('\n', stream
);
17673 fprintf (stream
, _("\
17674 -KPIC, -call_shared generate SVR4 position independent code\n\
17675 -call_nonpic generate non-PIC code that can operate with DSOs\n\
17676 -mvxworks-pic generate VxWorks position independent code\n\
17677 -non_shared do not generate code that can operate with DSOs\n\
17678 -xgot assume a 32 bit GOT\n\
17679 -mpdr, -mno-pdr enable/disable creation of .pdr sections\n\
17680 -mshared, -mno-shared disable/enable .cpload optimization for\n\
17681 position dependent (non shared) code\n\
17682 -mabi=ABI create ABI conformant object file for:\n"));
17686 show (stream
, "32", &column
, &first
);
17687 show (stream
, "o64", &column
, &first
);
17688 show (stream
, "n32", &column
, &first
);
17689 show (stream
, "64", &column
, &first
);
17690 show (stream
, "eabi", &column
, &first
);
17692 fputc ('\n', stream
);
17694 fprintf (stream
, _("\
17695 -32 create o32 ABI object file (default)\n\
17696 -n32 create n32 ABI object file\n\
17697 -64 create 64 ABI object file\n"));
17702 mips_dwarf2_format (asection
*sec ATTRIBUTE_UNUSED
)
17704 if (HAVE_64BIT_SYMBOLS
)
17705 return dwarf2_format_64bit_irix
;
17707 return dwarf2_format_32bit
;
17712 mips_dwarf2_addr_size (void)
17714 if (HAVE_64BIT_OBJECTS
)
17720 /* Standard calling conventions leave the CFA at SP on entry. */
17722 mips_cfi_frame_initial_instructions (void)
17724 cfi_add_CFA_def_cfa_register (SP
);
17728 tc_mips_regname_to_dw2regnum (char *regname
)
17730 unsigned int regnum
= -1;
17733 if (reg_lookup (®name
, RTYPE_GP
| RTYPE_NUM
, ®
))