1 /* tc-mips.c -- assemble code for a MIPS chip.
2 Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,
3 2003, 2004, 2005 Free Software Foundation, Inc.
4 Contributed by the OSF and Ralph Campbell.
5 Written by Keith Knowles and Ralph Campbell, working independently.
6 Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus
9 This file is part of GAS.
11 GAS is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 2, or (at your option)
16 GAS is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
21 You should have received a copy of the GNU General Public License
22 along with GAS; see the file COPYING. If not, write to the Free
23 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
29 #include "safe-ctype.h"
33 #include "opcode/mips.h"
35 #include "dwarf2dbg.h"
38 #define DBG(x) printf x
44 /* Clean up namespace so we can include obj-elf.h too. */
45 static int mips_output_flavor (void);
46 static int mips_output_flavor (void) { return OUTPUT_FLAVOR
; }
47 #undef OBJ_PROCESS_STAB
54 #undef obj_frob_file_after_relocs
55 #undef obj_frob_symbol
57 #undef obj_sec_sym_ok_for_reloc
58 #undef OBJ_COPY_SYMBOL_ATTRIBUTES
61 /* Fix any of them that we actually care about. */
63 #define OUTPUT_FLAVOR mips_output_flavor()
70 #ifndef ECOFF_DEBUGGING
71 #define NO_ECOFF_DEBUGGING
72 #define ECOFF_DEBUGGING 0
75 int mips_flag_mdebug
= -1;
77 /* Control generation of .pdr sections. Off by default on IRIX: the native
78 linker doesn't know about and discards them, but relocations against them
79 remain, leading to rld crashes. */
81 int mips_flag_pdr
= FALSE
;
83 int mips_flag_pdr
= TRUE
;
88 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
89 static char *mips_regmask_frag
;
95 #define PIC_CALL_REG 25
103 #define ILLEGAL_REG (32)
105 /* Allow override of standard little-endian ECOFF format. */
107 #ifndef ECOFF_LITTLE_FORMAT
108 #define ECOFF_LITTLE_FORMAT "ecoff-littlemips"
111 extern int target_big_endian
;
113 /* The name of the readonly data section. */
114 #define RDATA_SECTION_NAME (OUTPUT_FLAVOR == bfd_target_ecoff_flavour \
116 : OUTPUT_FLAVOR == bfd_target_coff_flavour \
118 : OUTPUT_FLAVOR == bfd_target_elf_flavour \
122 /* Information about an instruction, including its format, operands
126 /* The opcode's entry in mips_opcodes or mips16_opcodes. */
127 const struct mips_opcode
*insn_mo
;
129 /* True if this is a mips16 instruction and if we want the extended
131 bfd_boolean use_extend
;
133 /* The 16-bit extension instruction to use when USE_EXTEND is true. */
134 unsigned short extend
;
136 /* The 16-bit or 32-bit bitstring of the instruction itself. This is
137 a copy of INSN_MO->match with the operands filled in. */
138 unsigned long insn_opcode
;
140 /* The frag that contains the instruction. */
143 /* The offset into FRAG of the first instruction byte. */
146 /* The relocs associated with the instruction, if any. */
149 /* True if this entry cannot be moved from its current position. */
150 unsigned int fixed_p
: 1;
152 /* True if this instruction occured in a .set noreorder block. */
153 unsigned int noreorder_p
: 1;
155 /* True for mips16 instructions that jump to an absolute address. */
156 unsigned int mips16_absolute_jump_p
: 1;
159 /* The ABI to use. */
170 /* MIPS ABI we are using for this output file. */
171 static enum mips_abi_level mips_abi
= NO_ABI
;
173 /* Whether or not we have code that can call pic code. */
174 int mips_abicalls
= FALSE
;
176 /* Whether or not we have code which can be put into a shared
178 static bfd_boolean mips_in_shared
= TRUE
;
180 /* This is the set of options which may be modified by the .set
181 pseudo-op. We use a struct so that .set push and .set pop are more
184 struct mips_set_options
186 /* MIPS ISA (Instruction Set Architecture) level. This is set to -1
187 if it has not been initialized. Changed by `.set mipsN', and the
188 -mipsN command line option, and the default CPU. */
190 /* Enabled Application Specific Extensions (ASEs). These are set to -1
191 if they have not been initialized. Changed by `.set <asename>', by
192 command line options, and based on the default architecture. */
195 /* Whether we are assembling for the mips16 processor. 0 if we are
196 not, 1 if we are, and -1 if the value has not been initialized.
197 Changed by `.set mips16' and `.set nomips16', and the -mips16 and
198 -nomips16 command line options, and the default CPU. */
200 /* Non-zero if we should not reorder instructions. Changed by `.set
201 reorder' and `.set noreorder'. */
203 /* Non-zero if we should not permit the $at ($1) register to be used
204 in instructions. Changed by `.set at' and `.set noat'. */
206 /* Non-zero if we should warn when a macro instruction expands into
207 more than one machine instruction. Changed by `.set nomacro' and
209 int warn_about_macros
;
210 /* Non-zero if we should not move instructions. Changed by `.set
211 move', `.set volatile', `.set nomove', and `.set novolatile'. */
213 /* Non-zero if we should not optimize branches by moving the target
214 of the branch into the delay slot. Actually, we don't perform
215 this optimization anyhow. Changed by `.set bopt' and `.set
218 /* Non-zero if we should not autoextend mips16 instructions.
219 Changed by `.set autoextend' and `.set noautoextend'. */
221 /* Restrict general purpose registers and floating point registers
222 to 32 bit. This is initially determined when -mgp32 or -mfp32
223 is passed but can changed if the assembler code uses .set mipsN. */
226 /* MIPS architecture (CPU) type. Changed by .set arch=FOO, the -march
227 command line option, and the default CPU. */
229 /* True if ".set sym32" is in effect. */
233 /* True if -mgp32 was passed. */
234 static int file_mips_gp32
= -1;
236 /* True if -mfp32 was passed. */
237 static int file_mips_fp32
= -1;
239 /* This is the struct we use to hold the current set of options. Note
240 that we must set the isa field to ISA_UNKNOWN and the ASE fields to
241 -1 to indicate that they have not been initialized. */
243 static struct mips_set_options mips_opts
=
245 ISA_UNKNOWN
, -1, -1, -1, 0, 0, 0, 0, 0, 0, 0, 0, CPU_UNKNOWN
, FALSE
248 /* These variables are filled in with the masks of registers used.
249 The object format code reads them and puts them in the appropriate
251 unsigned long mips_gprmask
;
252 unsigned long mips_cprmask
[4];
254 /* MIPS ISA we are using for this output file. */
255 static int file_mips_isa
= ISA_UNKNOWN
;
257 /* True if -mips16 was passed or implied by arguments passed on the
258 command line (e.g., by -march). */
259 static int file_ase_mips16
;
261 /* True if -mips3d was passed or implied by arguments passed on the
262 command line (e.g., by -march). */
263 static int file_ase_mips3d
;
265 /* True if -mdmx was passed or implied by arguments passed on the
266 command line (e.g., by -march). */
267 static int file_ase_mdmx
;
269 /* The argument of the -march= flag. The architecture we are assembling. */
270 static int file_mips_arch
= CPU_UNKNOWN
;
271 static const char *mips_arch_string
;
273 /* The argument of the -mtune= flag. The architecture for which we
275 static int mips_tune
= CPU_UNKNOWN
;
276 static const char *mips_tune_string
;
278 /* True when generating 32-bit code for a 64-bit processor. */
279 static int mips_32bitmode
= 0;
281 /* True if the given ABI requires 32-bit registers. */
282 #define ABI_NEEDS_32BIT_REGS(ABI) ((ABI) == O32_ABI)
284 /* Likewise 64-bit registers. */
285 #define ABI_NEEDS_64BIT_REGS(ABI) \
287 || (ABI) == N64_ABI \
290 /* Return true if ISA supports 64 bit gp register instructions. */
291 #define ISA_HAS_64BIT_REGS(ISA) ( \
293 || (ISA) == ISA_MIPS4 \
294 || (ISA) == ISA_MIPS5 \
295 || (ISA) == ISA_MIPS64 \
296 || (ISA) == ISA_MIPS64R2 \
299 /* Return true if ISA supports 64-bit right rotate (dror et al.)
301 #define ISA_HAS_DROR(ISA) ( \
302 (ISA) == ISA_MIPS64R2 \
305 /* Return true if ISA supports 32-bit right rotate (ror et al.)
307 #define ISA_HAS_ROR(ISA) ( \
308 (ISA) == ISA_MIPS32R2 \
309 || (ISA) == ISA_MIPS64R2 \
312 #define HAVE_32BIT_GPRS \
313 (mips_opts.gp32 || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
315 #define HAVE_32BIT_FPRS \
316 (mips_opts.fp32 || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
318 #define HAVE_64BIT_GPRS (! HAVE_32BIT_GPRS)
319 #define HAVE_64BIT_FPRS (! HAVE_32BIT_FPRS)
321 #define HAVE_NEWABI (mips_abi == N32_ABI || mips_abi == N64_ABI)
323 #define HAVE_64BIT_OBJECTS (mips_abi == N64_ABI)
325 /* True if relocations are stored in-place. */
326 #define HAVE_IN_PLACE_ADDENDS (!HAVE_NEWABI)
328 /* The ABI-derived address size. */
329 #define HAVE_64BIT_ADDRESSES \
330 (HAVE_64BIT_GPRS && (mips_abi == EABI_ABI || mips_abi == N64_ABI))
331 #define HAVE_32BIT_ADDRESSES (!HAVE_64BIT_ADDRESSES)
333 /* The size of symbolic constants (i.e., expressions of the form
334 "SYMBOL" or "SYMBOL + OFFSET"). */
335 #define HAVE_32BIT_SYMBOLS \
336 (HAVE_32BIT_ADDRESSES || !HAVE_64BIT_OBJECTS || mips_opts.sym32)
337 #define HAVE_64BIT_SYMBOLS (!HAVE_32BIT_SYMBOLS)
339 /* Addresses are loaded in different ways, depending on the address size
340 in use. The n32 ABI Documentation also mandates the use of additions
341 with overflow checking, but existing implementations don't follow it. */
342 #define ADDRESS_ADD_INSN \
343 (HAVE_32BIT_ADDRESSES ? "addu" : "daddu")
345 #define ADDRESS_ADDI_INSN \
346 (HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu")
348 #define ADDRESS_LOAD_INSN \
349 (HAVE_32BIT_ADDRESSES ? "lw" : "ld")
351 #define ADDRESS_STORE_INSN \
352 (HAVE_32BIT_ADDRESSES ? "sw" : "sd")
354 /* Return true if the given CPU supports the MIPS16 ASE. */
355 #define CPU_HAS_MIPS16(cpu) \
356 (strncmp (TARGET_CPU, "mips16", sizeof ("mips16") - 1) == 0 \
357 || strncmp (TARGET_CANONICAL, "mips-lsi-elf", sizeof ("mips-lsi-elf") - 1) == 0)
359 /* Return true if the given CPU supports the MIPS3D ASE. */
360 #define CPU_HAS_MIPS3D(cpu) ((cpu) == CPU_SB1 \
363 /* Return true if the given CPU supports the MDMX ASE. */
364 #define CPU_HAS_MDMX(cpu) (FALSE \
367 /* True if CPU has a dror instruction. */
368 #define CPU_HAS_DROR(CPU) ((CPU) == CPU_VR5400 || (CPU) == CPU_VR5500)
370 /* True if CPU has a ror instruction. */
371 #define CPU_HAS_ROR(CPU) CPU_HAS_DROR (CPU)
373 /* True if mflo and mfhi can be immediately followed by instructions
374 which write to the HI and LO registers.
376 According to MIPS specifications, MIPS ISAs I, II, and III need
377 (at least) two instructions between the reads of HI/LO and
378 instructions which write them, and later ISAs do not. Contradicting
379 the MIPS specifications, some MIPS IV processor user manuals (e.g.
380 the UM for the NEC Vr5000) document needing the instructions between
381 HI/LO reads and writes, as well. Therefore, we declare only MIPS32,
382 MIPS64 and later ISAs to have the interlocks, plus any specific
383 earlier-ISA CPUs for which CPU documentation declares that the
384 instructions are really interlocked. */
385 #define hilo_interlocks \
386 (mips_opts.isa == ISA_MIPS32 \
387 || mips_opts.isa == ISA_MIPS32R2 \
388 || mips_opts.isa == ISA_MIPS64 \
389 || mips_opts.isa == ISA_MIPS64R2 \
390 || mips_opts.arch == CPU_R4010 \
391 || mips_opts.arch == CPU_R10000 \
392 || mips_opts.arch == CPU_R12000 \
393 || mips_opts.arch == CPU_RM7000 \
394 || mips_opts.arch == CPU_VR5500 \
397 /* Whether the processor uses hardware interlocks to protect reads
398 from the GPRs after they are loaded from memory, and thus does not
399 require nops to be inserted. This applies to instructions marked
400 INSN_LOAD_MEMORY_DELAY. These nops are only required at MIPS ISA
402 #define gpr_interlocks \
403 (mips_opts.isa != ISA_MIPS1 \
404 || mips_opts.arch == CPU_R3900)
406 /* Whether the processor uses hardware interlocks to avoid delays
407 required by coprocessor instructions, and thus does not require
408 nops to be inserted. This applies to instructions marked
409 INSN_LOAD_COPROC_DELAY, INSN_COPROC_MOVE_DELAY, and to delays
410 between instructions marked INSN_WRITE_COND_CODE and ones marked
411 INSN_READ_COND_CODE. These nops are only required at MIPS ISA
412 levels I, II, and III. */
413 /* Itbl support may require additional care here. */
414 #define cop_interlocks \
415 ((mips_opts.isa != ISA_MIPS1 \
416 && mips_opts.isa != ISA_MIPS2 \
417 && mips_opts.isa != ISA_MIPS3) \
418 || mips_opts.arch == CPU_R4300 \
421 /* Whether the processor uses hardware interlocks to protect reads
422 from coprocessor registers after they are loaded from memory, and
423 thus does not require nops to be inserted. This applies to
424 instructions marked INSN_COPROC_MEMORY_DELAY. These nops are only
425 requires at MIPS ISA level I. */
426 #define cop_mem_interlocks (mips_opts.isa != ISA_MIPS1)
428 /* Is this a mfhi or mflo instruction? */
429 #define MF_HILO_INSN(PINFO) \
430 ((PINFO & INSN_READ_HI) || (PINFO & INSN_READ_LO))
432 /* MIPS PIC level. */
434 enum mips_pic_level mips_pic
;
436 /* 1 if we should generate 32 bit offsets from the $gp register in
437 SVR4_PIC mode. Currently has no meaning in other modes. */
438 static int mips_big_got
= 0;
440 /* 1 if trap instructions should used for overflow rather than break
442 static int mips_trap
= 0;
444 /* 1 if double width floating point constants should not be constructed
445 by assembling two single width halves into two single width floating
446 point registers which just happen to alias the double width destination
447 register. On some architectures this aliasing can be disabled by a bit
448 in the status register, and the setting of this bit cannot be determined
449 automatically at assemble time. */
450 static int mips_disable_float_construction
;
452 /* Non-zero if any .set noreorder directives were used. */
454 static int mips_any_noreorder
;
456 /* Non-zero if nops should be inserted when the register referenced in
457 an mfhi/mflo instruction is read in the next two instructions. */
458 static int mips_7000_hilo_fix
;
460 /* The size of the small data section. */
461 static unsigned int g_switch_value
= 8;
462 /* Whether the -G option was used. */
463 static int g_switch_seen
= 0;
468 /* If we can determine in advance that GP optimization won't be
469 possible, we can skip the relaxation stuff that tries to produce
470 GP-relative references. This makes delay slot optimization work
473 This function can only provide a guess, but it seems to work for
474 gcc output. It needs to guess right for gcc, otherwise gcc
475 will put what it thinks is a GP-relative instruction in a branch
478 I don't know if a fix is needed for the SVR4_PIC mode. I've only
479 fixed it for the non-PIC mode. KR 95/04/07 */
480 static int nopic_need_relax (symbolS
*, int);
482 /* handle of the OPCODE hash table */
483 static struct hash_control
*op_hash
= NULL
;
485 /* The opcode hash table we use for the mips16. */
486 static struct hash_control
*mips16_op_hash
= NULL
;
488 /* This array holds the chars that always start a comment. If the
489 pre-processor is disabled, these aren't very useful */
490 const char comment_chars
[] = "#";
492 /* This array holds the chars that only start a comment at the beginning of
493 a line. If the line seems to have the form '# 123 filename'
494 .line and .file directives will appear in the pre-processed output */
495 /* Note that input_file.c hand checks for '#' at the beginning of the
496 first line of the input file. This is because the compiler outputs
497 #NO_APP at the beginning of its output. */
498 /* Also note that C style comments are always supported. */
499 const char line_comment_chars
[] = "#";
501 /* This array holds machine specific line separator characters. */
502 const char line_separator_chars
[] = ";";
504 /* Chars that can be used to separate mant from exp in floating point nums */
505 const char EXP_CHARS
[] = "eE";
507 /* Chars that mean this number is a floating point constant */
510 const char FLT_CHARS
[] = "rRsSfFdDxXpP";
512 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
513 changed in read.c . Ideally it shouldn't have to know about it at all,
514 but nothing is ideal around here.
517 static char *insn_error
;
519 static int auto_align
= 1;
521 /* When outputting SVR4 PIC code, the assembler needs to know the
522 offset in the stack frame from which to restore the $gp register.
523 This is set by the .cprestore pseudo-op, and saved in this
525 static offsetT mips_cprestore_offset
= -1;
527 /* Similar for NewABI PIC code, where $gp is callee-saved. NewABI has some
528 more optimizations, it can use a register value instead of a memory-saved
529 offset and even an other register than $gp as global pointer. */
530 static offsetT mips_cpreturn_offset
= -1;
531 static int mips_cpreturn_register
= -1;
532 static int mips_gp_register
= GP
;
533 static int mips_gprel_offset
= 0;
535 /* Whether mips_cprestore_offset has been set in the current function
536 (or whether it has already been warned about, if not). */
537 static int mips_cprestore_valid
= 0;
539 /* This is the register which holds the stack frame, as set by the
540 .frame pseudo-op. This is needed to implement .cprestore. */
541 static int mips_frame_reg
= SP
;
543 /* Whether mips_frame_reg has been set in the current function
544 (or whether it has already been warned about, if not). */
545 static int mips_frame_reg_valid
= 0;
547 /* To output NOP instructions correctly, we need to keep information
548 about the previous two instructions. */
550 /* Whether we are optimizing. The default value of 2 means to remove
551 unneeded NOPs and swap branch instructions when possible. A value
552 of 1 means to not swap branches. A value of 0 means to always
554 static int mips_optimize
= 2;
556 /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is
557 equivalent to seeing no -g option at all. */
558 static int mips_debug
= 0;
560 /* The maximum number of NOPs needed to avoid the VR4130 mflo/mfhi errata. */
561 #define MAX_VR4130_NOPS 4
563 /* The maximum number of NOPs needed to fill delay slots. */
564 #define MAX_DELAY_NOPS 2
566 /* The maximum number of NOPs needed for any purpose. */
569 /* A list of previous instructions, with index 0 being the most recent.
570 We need to look back MAX_NOPS instructions when filling delay slots
571 or working around processor errata. We need to look back one
572 instruction further if we're thinking about using history[0] to
573 fill a branch delay slot. */
574 static struct mips_cl_insn history
[1 + MAX_NOPS
];
576 /* Nop instructions used by emit_nop. */
577 static struct mips_cl_insn nop_insn
, mips16_nop_insn
;
579 /* The appropriate nop for the current mode. */
580 #define NOP_INSN (mips_opts.mips16 ? &mips16_nop_insn : &nop_insn)
582 /* If this is set, it points to a frag holding nop instructions which
583 were inserted before the start of a noreorder section. If those
584 nops turn out to be unnecessary, the size of the frag can be
586 static fragS
*prev_nop_frag
;
588 /* The number of nop instructions we created in prev_nop_frag. */
589 static int prev_nop_frag_holds
;
591 /* The number of nop instructions that we know we need in
593 static int prev_nop_frag_required
;
595 /* The number of instructions we've seen since prev_nop_frag. */
596 static int prev_nop_frag_since
;
598 /* For ECOFF and ELF, relocations against symbols are done in two
599 parts, with a HI relocation and a LO relocation. Each relocation
600 has only 16 bits of space to store an addend. This means that in
601 order for the linker to handle carries correctly, it must be able
602 to locate both the HI and the LO relocation. This means that the
603 relocations must appear in order in the relocation table.
605 In order to implement this, we keep track of each unmatched HI
606 relocation. We then sort them so that they immediately precede the
607 corresponding LO relocation. */
612 struct mips_hi_fixup
*next
;
615 /* The section this fixup is in. */
619 /* The list of unmatched HI relocs. */
621 static struct mips_hi_fixup
*mips_hi_fixup_list
;
623 /* The frag containing the last explicit relocation operator.
624 Null if explicit relocations have not been used. */
626 static fragS
*prev_reloc_op_frag
;
628 /* Map normal MIPS register numbers to mips16 register numbers. */
630 #define X ILLEGAL_REG
631 static const int mips32_to_16_reg_map
[] =
633 X
, X
, 2, 3, 4, 5, 6, 7,
634 X
, X
, X
, X
, X
, X
, X
, X
,
635 0, 1, X
, X
, X
, X
, X
, X
,
636 X
, X
, X
, X
, X
, X
, X
, X
640 /* Map mips16 register numbers to normal MIPS register numbers. */
642 static const unsigned int mips16_to_32_reg_map
[] =
644 16, 17, 2, 3, 4, 5, 6, 7
647 /* Classifies the kind of instructions we're interested in when
648 implementing -mfix-vr4120. */
649 enum fix_vr4120_class
{
656 NUM_FIX_VR4120_CLASSES
659 /* Given two FIX_VR4120_* values X and Y, bit Y of element X is set if
660 there must be at least one other instruction between an instruction
661 of type X and an instruction of type Y. */
662 static unsigned int vr4120_conflicts
[NUM_FIX_VR4120_CLASSES
];
664 /* True if -mfix-vr4120 is in force. */
665 static int mips_fix_vr4120
;
667 /* ...likewise -mfix-vr4130. */
668 static int mips_fix_vr4130
;
670 /* We don't relax branches by default, since this causes us to expand
671 `la .l2 - .l1' if there's a branch between .l1 and .l2, because we
672 fail to compute the offset before expanding the macro to the most
673 efficient expansion. */
675 static int mips_relax_branch
;
677 /* The expansion of many macros depends on the type of symbol that
678 they refer to. For example, when generating position-dependent code,
679 a macro that refers to a symbol may have two different expansions,
680 one which uses GP-relative addresses and one which uses absolute
681 addresses. When generating SVR4-style PIC, a macro may have
682 different expansions for local and global symbols.
684 We handle these situations by generating both sequences and putting
685 them in variant frags. In position-dependent code, the first sequence
686 will be the GP-relative one and the second sequence will be the
687 absolute one. In SVR4 PIC, the first sequence will be for global
688 symbols and the second will be for local symbols.
690 The frag's "subtype" is RELAX_ENCODE (FIRST, SECOND), where FIRST and
691 SECOND are the lengths of the two sequences in bytes. These fields
692 can be extracted using RELAX_FIRST() and RELAX_SECOND(). In addition,
693 the subtype has the following flags:
696 Set if it has been decided that we should use the second
697 sequence instead of the first.
700 Set in the first variant frag if the macro's second implementation
701 is longer than its first. This refers to the macro as a whole,
702 not an individual relaxation.
705 Set in the first variant frag if the macro appeared in a .set nomacro
706 block and if one alternative requires a warning but the other does not.
709 Like RELAX_NOMACRO, but indicates that the macro appears in a branch
712 The frag's "opcode" points to the first fixup for relaxable code.
714 Relaxable macros are generated using a sequence such as:
716 relax_start (SYMBOL);
717 ... generate first expansion ...
719 ... generate second expansion ...
722 The code and fixups for the unwanted alternative are discarded
723 by md_convert_frag. */
724 #define RELAX_ENCODE(FIRST, SECOND) (((FIRST) << 8) | (SECOND))
726 #define RELAX_FIRST(X) (((X) >> 8) & 0xff)
727 #define RELAX_SECOND(X) ((X) & 0xff)
728 #define RELAX_USE_SECOND 0x10000
729 #define RELAX_SECOND_LONGER 0x20000
730 #define RELAX_NOMACRO 0x40000
731 #define RELAX_DELAY_SLOT 0x80000
733 /* Branch without likely bit. If label is out of range, we turn:
735 beq reg1, reg2, label
745 with the following opcode replacements:
752 bltzal <-> bgezal (with jal label instead of j label)
754 Even though keeping the delay slot instruction in the delay slot of
755 the branch would be more efficient, it would be very tricky to do
756 correctly, because we'd have to introduce a variable frag *after*
757 the delay slot instruction, and expand that instead. Let's do it
758 the easy way for now, even if the branch-not-taken case now costs
759 one additional instruction. Out-of-range branches are not supposed
760 to be common, anyway.
762 Branch likely. If label is out of range, we turn:
764 beql reg1, reg2, label
765 delay slot (annulled if branch not taken)
774 delay slot (executed only if branch taken)
777 It would be possible to generate a shorter sequence by losing the
778 likely bit, generating something like:
783 delay slot (executed only if branch taken)
795 bltzall -> bgezal (with jal label instead of j label)
796 bgezall -> bltzal (ditto)
799 but it's not clear that it would actually improve performance. */
800 #define RELAX_BRANCH_ENCODE(uncond, likely, link, toofar) \
803 | ((toofar) ? 1 : 0) \
805 | ((likely) ? 4 : 0) \
806 | ((uncond) ? 8 : 0)))
807 #define RELAX_BRANCH_P(i) (((i) & 0xf0000000) == 0xc0000000)
808 #define RELAX_BRANCH_UNCOND(i) (((i) & 8) != 0)
809 #define RELAX_BRANCH_LIKELY(i) (((i) & 4) != 0)
810 #define RELAX_BRANCH_LINK(i) (((i) & 2) != 0)
811 #define RELAX_BRANCH_TOOFAR(i) (((i) & 1) != 0)
813 /* For mips16 code, we use an entirely different form of relaxation.
814 mips16 supports two versions of most instructions which take
815 immediate values: a small one which takes some small value, and a
816 larger one which takes a 16 bit value. Since branches also follow
817 this pattern, relaxing these values is required.
819 We can assemble both mips16 and normal MIPS code in a single
820 object. Therefore, we need to support this type of relaxation at
821 the same time that we support the relaxation described above. We
822 use the high bit of the subtype field to distinguish these cases.
824 The information we store for this type of relaxation is the
825 argument code found in the opcode file for this relocation, whether
826 the user explicitly requested a small or extended form, and whether
827 the relocation is in a jump or jal delay slot. That tells us the
828 size of the value, and how it should be stored. We also store
829 whether the fragment is considered to be extended or not. We also
830 store whether this is known to be a branch to a different section,
831 whether we have tried to relax this frag yet, and whether we have
832 ever extended a PC relative fragment because of a shift count. */
833 #define RELAX_MIPS16_ENCODE(type, small, ext, dslot, jal_dslot) \
836 | ((small) ? 0x100 : 0) \
837 | ((ext) ? 0x200 : 0) \
838 | ((dslot) ? 0x400 : 0) \
839 | ((jal_dslot) ? 0x800 : 0))
840 #define RELAX_MIPS16_P(i) (((i) & 0xc0000000) == 0x80000000)
841 #define RELAX_MIPS16_TYPE(i) ((i) & 0xff)
842 #define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x100) != 0)
843 #define RELAX_MIPS16_USER_EXT(i) (((i) & 0x200) != 0)
844 #define RELAX_MIPS16_DSLOT(i) (((i) & 0x400) != 0)
845 #define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x800) != 0)
846 #define RELAX_MIPS16_EXTENDED(i) (((i) & 0x1000) != 0)
847 #define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x1000)
848 #define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) &~ 0x1000)
849 #define RELAX_MIPS16_LONG_BRANCH(i) (((i) & 0x2000) != 0)
850 #define RELAX_MIPS16_MARK_LONG_BRANCH(i) ((i) | 0x2000)
851 #define RELAX_MIPS16_CLEAR_LONG_BRANCH(i) ((i) &~ 0x2000)
853 /* Is the given value a sign-extended 32-bit value? */
854 #define IS_SEXT_32BIT_NUM(x) \
855 (((x) &~ (offsetT) 0x7fffffff) == 0 \
856 || (((x) &~ (offsetT) 0x7fffffff) == ~ (offsetT) 0x7fffffff))
858 /* Is the given value a sign-extended 16-bit value? */
859 #define IS_SEXT_16BIT_NUM(x) \
860 (((x) &~ (offsetT) 0x7fff) == 0 \
861 || (((x) &~ (offsetT) 0x7fff) == ~ (offsetT) 0x7fff))
863 /* Replace bits MASK << SHIFT of STRUCT with the equivalent bits in
864 VALUE << SHIFT. VALUE is evaluated exactly once. */
865 #define INSERT_BITS(STRUCT, VALUE, MASK, SHIFT) \
866 (STRUCT) = (((STRUCT) & ~((MASK) << (SHIFT))) \
867 | (((VALUE) & (MASK)) << (SHIFT)))
869 /* Extract bits MASK << SHIFT from STRUCT and shift them right
871 #define EXTRACT_BITS(STRUCT, MASK, SHIFT) \
872 (((STRUCT) >> (SHIFT)) & (MASK))
874 /* Change INSN's opcode so that the operand given by FIELD has value VALUE.
875 INSN is a mips_cl_insn structure and VALUE is evaluated exactly once.
877 include/opcode/mips.h specifies operand fields using the macros
878 OP_MASK_<FIELD> and OP_SH_<FIELD>. The MIPS16 equivalents start
879 with "MIPS16OP" instead of "OP". */
880 #define INSERT_OPERAND(FIELD, INSN, VALUE) \
881 INSERT_BITS ((INSN).insn_opcode, VALUE, OP_MASK_##FIELD, OP_SH_##FIELD)
882 #define MIPS16_INSERT_OPERAND(FIELD, INSN, VALUE) \
883 INSERT_BITS ((INSN).insn_opcode, VALUE, \
884 MIPS16OP_MASK_##FIELD, MIPS16OP_SH_##FIELD)
886 /* Extract the operand given by FIELD from mips_cl_insn INSN. */
887 #define EXTRACT_OPERAND(FIELD, INSN) \
888 EXTRACT_BITS ((INSN).insn_opcode, OP_MASK_##FIELD, OP_SH_##FIELD)
889 #define MIPS16_EXTRACT_OPERAND(FIELD, INSN) \
890 EXTRACT_BITS ((INSN).insn_opcode, \
891 MIPS16OP_MASK_##FIELD, \
894 /* Global variables used when generating relaxable macros. See the
895 comment above RELAX_ENCODE for more details about how relaxation
898 /* 0 if we're not emitting a relaxable macro.
899 1 if we're emitting the first of the two relaxation alternatives.
900 2 if we're emitting the second alternative. */
903 /* The first relaxable fixup in the current frag. (In other words,
904 the first fixup that refers to relaxable code.) */
907 /* sizes[0] says how many bytes of the first alternative are stored in
908 the current frag. Likewise sizes[1] for the second alternative. */
909 unsigned int sizes
[2];
911 /* The symbol on which the choice of sequence depends. */
915 /* Global variables used to decide whether a macro needs a warning. */
917 /* True if the macro is in a branch delay slot. */
918 bfd_boolean delay_slot_p
;
920 /* For relaxable macros, sizes[0] is the length of the first alternative
921 in bytes and sizes[1] is the length of the second alternative.
922 For non-relaxable macros, both elements give the length of the
924 unsigned int sizes
[2];
926 /* The first variant frag for this macro. */
928 } mips_macro_warning
;
930 /* Prototypes for static functions. */
932 #define internalError() \
933 as_fatal (_("internal Error, line %d, %s"), __LINE__, __FILE__)
935 enum mips_regclass
{ MIPS_GR_REG
, MIPS_FP_REG
, MIPS16_REG
};
937 static void append_insn
938 (struct mips_cl_insn
*ip
, expressionS
*p
, bfd_reloc_code_real_type
*r
);
939 static void mips_no_prev_insn (void);
940 static void mips16_macro_build
941 (expressionS
*, const char *, const char *, va_list);
942 static void load_register (int, expressionS
*, int);
943 static void macro_start (void);
944 static void macro_end (void);
945 static void macro (struct mips_cl_insn
* ip
);
946 static void mips16_macro (struct mips_cl_insn
* ip
);
947 #ifdef LOSING_COMPILER
948 static void macro2 (struct mips_cl_insn
* ip
);
950 static void mips_ip (char *str
, struct mips_cl_insn
* ip
);
951 static void mips16_ip (char *str
, struct mips_cl_insn
* ip
);
952 static void mips16_immed
953 (char *, unsigned int, int, offsetT
, bfd_boolean
, bfd_boolean
, bfd_boolean
,
954 unsigned long *, bfd_boolean
*, unsigned short *);
955 static size_t my_getSmallExpression
956 (expressionS
*, bfd_reloc_code_real_type
*, char *);
957 static void my_getExpression (expressionS
*, char *);
958 static void s_align (int);
959 static void s_change_sec (int);
960 static void s_change_section (int);
961 static void s_cons (int);
962 static void s_float_cons (int);
963 static void s_mips_globl (int);
964 static void s_option (int);
965 static void s_mipsset (int);
966 static void s_abicalls (int);
967 static void s_cpload (int);
968 static void s_cpsetup (int);
969 static void s_cplocal (int);
970 static void s_cprestore (int);
971 static void s_cpreturn (int);
972 static void s_gpvalue (int);
973 static void s_gpword (int);
974 static void s_gpdword (int);
975 static void s_cpadd (int);
976 static void s_insn (int);
977 static void md_obj_begin (void);
978 static void md_obj_end (void);
979 static void s_mips_ent (int);
980 static void s_mips_end (int);
981 static void s_mips_frame (int);
982 static void s_mips_mask (int reg_type
);
983 static void s_mips_stab (int);
984 static void s_mips_weakext (int);
985 static void s_mips_file (int);
986 static void s_mips_loc (int);
987 static bfd_boolean
pic_need_relax (symbolS
*, asection
*);
988 static int relaxed_branch_length (fragS
*, asection
*, int);
989 static int validate_mips_insn (const struct mips_opcode
*);
991 /* Table and functions used to map between CPU/ISA names, and
992 ISA levels, and CPU numbers. */
996 const char *name
; /* CPU or ISA name. */
997 int is_isa
; /* Is this an ISA? (If 0, a CPU.) */
998 int isa
; /* ISA level. */
999 int cpu
; /* CPU number (default CPU if ISA). */
1002 static const struct mips_cpu_info
*mips_parse_cpu (const char *, const char *);
1003 static const struct mips_cpu_info
*mips_cpu_info_from_isa (int);
1004 static const struct mips_cpu_info
*mips_cpu_info_from_arch (int);
1008 The following pseudo-ops from the Kane and Heinrich MIPS book
1009 should be defined here, but are currently unsupported: .alias,
1010 .galive, .gjaldef, .gjrlive, .livereg, .noalias.
1012 The following pseudo-ops from the Kane and Heinrich MIPS book are
1013 specific to the type of debugging information being generated, and
1014 should be defined by the object format: .aent, .begin, .bend,
1015 .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp,
1018 The following pseudo-ops from the Kane and Heinrich MIPS book are
1019 not MIPS CPU specific, but are also not specific to the object file
1020 format. This file is probably the best place to define them, but
1021 they are not currently supported: .asm0, .endr, .lab, .repeat,
1024 static const pseudo_typeS mips_pseudo_table
[] =
1026 /* MIPS specific pseudo-ops. */
1027 {"option", s_option
, 0},
1028 {"set", s_mipsset
, 0},
1029 {"rdata", s_change_sec
, 'r'},
1030 {"sdata", s_change_sec
, 's'},
1031 {"livereg", s_ignore
, 0},
1032 {"abicalls", s_abicalls
, 0},
1033 {"cpload", s_cpload
, 0},
1034 {"cpsetup", s_cpsetup
, 0},
1035 {"cplocal", s_cplocal
, 0},
1036 {"cprestore", s_cprestore
, 0},
1037 {"cpreturn", s_cpreturn
, 0},
1038 {"gpvalue", s_gpvalue
, 0},
1039 {"gpword", s_gpword
, 0},
1040 {"gpdword", s_gpdword
, 0},
1041 {"cpadd", s_cpadd
, 0},
1042 {"insn", s_insn
, 0},
1044 /* Relatively generic pseudo-ops that happen to be used on MIPS
1046 {"asciiz", stringer
, 1},
1047 {"bss", s_change_sec
, 'b'},
1049 {"half", s_cons
, 1},
1050 {"dword", s_cons
, 3},
1051 {"weakext", s_mips_weakext
, 0},
1053 /* These pseudo-ops are defined in read.c, but must be overridden
1054 here for one reason or another. */
1055 {"align", s_align
, 0},
1056 {"byte", s_cons
, 0},
1057 {"data", s_change_sec
, 'd'},
1058 {"double", s_float_cons
, 'd'},
1059 {"float", s_float_cons
, 'f'},
1060 {"globl", s_mips_globl
, 0},
1061 {"global", s_mips_globl
, 0},
1062 {"hword", s_cons
, 1},
1064 {"long", s_cons
, 2},
1065 {"octa", s_cons
, 4},
1066 {"quad", s_cons
, 3},
1067 {"section", s_change_section
, 0},
1068 {"short", s_cons
, 1},
1069 {"single", s_float_cons
, 'f'},
1070 {"stabn", s_mips_stab
, 'n'},
1071 {"text", s_change_sec
, 't'},
1072 {"word", s_cons
, 2},
1074 { "extern", ecoff_directive_extern
, 0},
1079 static const pseudo_typeS mips_nonecoff_pseudo_table
[] =
1081 /* These pseudo-ops should be defined by the object file format.
1082 However, a.out doesn't support them, so we have versions here. */
1083 {"aent", s_mips_ent
, 1},
1084 {"bgnb", s_ignore
, 0},
1085 {"end", s_mips_end
, 0},
1086 {"endb", s_ignore
, 0},
1087 {"ent", s_mips_ent
, 0},
1088 {"file", s_mips_file
, 0},
1089 {"fmask", s_mips_mask
, 'F'},
1090 {"frame", s_mips_frame
, 0},
1091 {"loc", s_mips_loc
, 0},
1092 {"mask", s_mips_mask
, 'R'},
1093 {"verstamp", s_ignore
, 0},
1097 extern void pop_insert (const pseudo_typeS
*);
1100 mips_pop_insert (void)
1102 pop_insert (mips_pseudo_table
);
1103 if (! ECOFF_DEBUGGING
)
1104 pop_insert (mips_nonecoff_pseudo_table
);
1107 /* Symbols labelling the current insn. */
1109 struct insn_label_list
1111 struct insn_label_list
*next
;
1115 static struct insn_label_list
*insn_labels
;
1116 static struct insn_label_list
*free_insn_labels
;
1118 static void mips_clear_insn_labels (void);
1121 mips_clear_insn_labels (void)
1123 register struct insn_label_list
**pl
;
1125 for (pl
= &free_insn_labels
; *pl
!= NULL
; pl
= &(*pl
)->next
)
1131 static char *expr_end
;
1133 /* Expressions which appear in instructions. These are set by
1136 static expressionS imm_expr
;
1137 static expressionS imm2_expr
;
1138 static expressionS offset_expr
;
1140 /* Relocs associated with imm_expr and offset_expr. */
1142 static bfd_reloc_code_real_type imm_reloc
[3]
1143 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
1144 static bfd_reloc_code_real_type offset_reloc
[3]
1145 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
1147 /* These are set by mips16_ip if an explicit extension is used. */
1149 static bfd_boolean mips16_small
, mips16_ext
;
1152 /* The pdr segment for per procedure frame/regmask info. Not used for
1155 static segT pdr_seg
;
1158 /* The default target format to use. */
1161 mips_target_format (void)
1163 switch (OUTPUT_FLAVOR
)
1165 case bfd_target_ecoff_flavour
:
1166 return target_big_endian
? "ecoff-bigmips" : ECOFF_LITTLE_FORMAT
;
1167 case bfd_target_coff_flavour
:
1169 case bfd_target_elf_flavour
:
1171 /* This is traditional mips. */
1172 return (target_big_endian
1173 ? (HAVE_64BIT_OBJECTS
1174 ? "elf64-tradbigmips"
1176 ? "elf32-ntradbigmips" : "elf32-tradbigmips"))
1177 : (HAVE_64BIT_OBJECTS
1178 ? "elf64-tradlittlemips"
1180 ? "elf32-ntradlittlemips" : "elf32-tradlittlemips")));
1182 return (target_big_endian
1183 ? (HAVE_64BIT_OBJECTS
1186 ? "elf32-nbigmips" : "elf32-bigmips"))
1187 : (HAVE_64BIT_OBJECTS
1188 ? "elf64-littlemips"
1190 ? "elf32-nlittlemips" : "elf32-littlemips")));
1198 /* Return the length of instruction INSN. */
1200 static inline unsigned int
1201 insn_length (const struct mips_cl_insn
*insn
)
1203 if (!mips_opts
.mips16
)
1205 return insn
->mips16_absolute_jump_p
|| insn
->use_extend
? 4 : 2;
1208 /* Initialise INSN from opcode entry MO. Leave its position unspecified. */
1211 create_insn (struct mips_cl_insn
*insn
, const struct mips_opcode
*mo
)
1216 insn
->use_extend
= FALSE
;
1218 insn
->insn_opcode
= mo
->match
;
1221 for (i
= 0; i
< ARRAY_SIZE (insn
->fixp
); i
++)
1222 insn
->fixp
[i
] = NULL
;
1223 insn
->fixed_p
= (mips_opts
.noreorder
> 0);
1224 insn
->noreorder_p
= (mips_opts
.noreorder
> 0);
1225 insn
->mips16_absolute_jump_p
= 0;
1228 /* Install INSN at the location specified by its "frag" and "where" fields. */
1231 install_insn (const struct mips_cl_insn
*insn
)
1233 char *f
= insn
->frag
->fr_literal
+ insn
->where
;
1234 if (!mips_opts
.mips16
)
1235 md_number_to_chars (f
, insn
->insn_opcode
, 4);
1236 else if (insn
->mips16_absolute_jump_p
)
1238 md_number_to_chars (f
, insn
->insn_opcode
>> 16, 2);
1239 md_number_to_chars (f
+ 2, insn
->insn_opcode
& 0xffff, 2);
1243 if (insn
->use_extend
)
1245 md_number_to_chars (f
, 0xf000 | insn
->extend
, 2);
1248 md_number_to_chars (f
, insn
->insn_opcode
, 2);
1252 /* Move INSN to offset WHERE in FRAG. Adjust the fixups accordingly
1253 and install the opcode in the new location. */
1256 move_insn (struct mips_cl_insn
*insn
, fragS
*frag
, long where
)
1261 insn
->where
= where
;
1262 for (i
= 0; i
< ARRAY_SIZE (insn
->fixp
); i
++)
1263 if (insn
->fixp
[i
] != NULL
)
1265 insn
->fixp
[i
]->fx_frag
= frag
;
1266 insn
->fixp
[i
]->fx_where
= where
;
1268 install_insn (insn
);
1271 /* Add INSN to the end of the output. */
1274 add_fixed_insn (struct mips_cl_insn
*insn
)
1276 char *f
= frag_more (insn_length (insn
));
1277 move_insn (insn
, frag_now
, f
- frag_now
->fr_literal
);
1280 /* Start a variant frag and move INSN to the start of the variant part,
1281 marking it as fixed. The other arguments are as for frag_var. */
1284 add_relaxed_insn (struct mips_cl_insn
*insn
, int max_chars
, int var
,
1285 relax_substateT subtype
, symbolS
*symbol
, offsetT offset
)
1287 frag_grow (max_chars
);
1288 move_insn (insn
, frag_now
, frag_more (0) - frag_now
->fr_literal
);
1290 frag_var (rs_machine_dependent
, max_chars
, var
,
1291 subtype
, symbol
, offset
, NULL
);
1294 /* Insert N copies of INSN into the history buffer, starting at
1295 position FIRST. Neither FIRST nor N need to be clipped. */
1298 insert_into_history (unsigned int first
, unsigned int n
,
1299 const struct mips_cl_insn
*insn
)
1301 if (mips_relax
.sequence
!= 2)
1305 for (i
= ARRAY_SIZE (history
); i
-- > first
;)
1307 history
[i
] = history
[i
- n
];
1313 /* Emit a nop instruction, recording it in the history buffer. */
1318 add_fixed_insn (NOP_INSN
);
1319 insert_into_history (0, 1, NOP_INSN
);
1322 /* Initialize vr4120_conflicts. There is a bit of duplication here:
1323 the idea is to make it obvious at a glance that each errata is
1327 init_vr4120_conflicts (void)
1329 #define CONFLICT(FIRST, SECOND) \
1330 vr4120_conflicts[FIX_VR4120_##FIRST] |= 1 << FIX_VR4120_##SECOND
1332 /* Errata 21 - [D]DIV[U] after [D]MACC */
1333 CONFLICT (MACC
, DIV
);
1334 CONFLICT (DMACC
, DIV
);
1336 /* Errata 23 - Continuous DMULT[U]/DMACC instructions. */
1337 CONFLICT (DMULT
, DMULT
);
1338 CONFLICT (DMULT
, DMACC
);
1339 CONFLICT (DMACC
, DMULT
);
1340 CONFLICT (DMACC
, DMACC
);
1342 /* Errata 24 - MT{LO,HI} after [D]MACC */
1343 CONFLICT (MACC
, MTHILO
);
1344 CONFLICT (DMACC
, MTHILO
);
1346 /* VR4181A errata MD(1): "If a MULT, MULTU, DMULT or DMULTU
1347 instruction is executed immediately after a MACC or DMACC
1348 instruction, the result of [either instruction] is incorrect." */
1349 CONFLICT (MACC
, MULT
);
1350 CONFLICT (MACC
, DMULT
);
1351 CONFLICT (DMACC
, MULT
);
1352 CONFLICT (DMACC
, DMULT
);
1354 /* VR4181A errata MD(4): "If a MACC or DMACC instruction is
1355 executed immediately after a DMULT, DMULTU, DIV, DIVU,
1356 DDIV or DDIVU instruction, the result of the MACC or
1357 DMACC instruction is incorrect.". */
1358 CONFLICT (DMULT
, MACC
);
1359 CONFLICT (DMULT
, DMACC
);
1360 CONFLICT (DIV
, MACC
);
1361 CONFLICT (DIV
, DMACC
);
1366 /* This function is called once, at assembler startup time. It should
1367 set up all the tables, etc. that the MD part of the assembler will need. */
1372 register const char *retval
= NULL
;
1376 if (! bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, file_mips_arch
))
1377 as_warn (_("Could not set architecture and machine"));
1379 op_hash
= hash_new ();
1381 for (i
= 0; i
< NUMOPCODES
;)
1383 const char *name
= mips_opcodes
[i
].name
;
1385 retval
= hash_insert (op_hash
, name
, (void *) &mips_opcodes
[i
]);
1388 fprintf (stderr
, _("internal error: can't hash `%s': %s\n"),
1389 mips_opcodes
[i
].name
, retval
);
1390 /* Probably a memory allocation problem? Give up now. */
1391 as_fatal (_("Broken assembler. No assembly attempted."));
1395 if (mips_opcodes
[i
].pinfo
!= INSN_MACRO
)
1397 if (!validate_mips_insn (&mips_opcodes
[i
]))
1399 if (nop_insn
.insn_mo
== NULL
&& strcmp (name
, "nop") == 0)
1401 create_insn (&nop_insn
, mips_opcodes
+ i
);
1402 nop_insn
.fixed_p
= 1;
1407 while ((i
< NUMOPCODES
) && !strcmp (mips_opcodes
[i
].name
, name
));
1410 mips16_op_hash
= hash_new ();
1413 while (i
< bfd_mips16_num_opcodes
)
1415 const char *name
= mips16_opcodes
[i
].name
;
1417 retval
= hash_insert (mips16_op_hash
, name
, (void *) &mips16_opcodes
[i
]);
1419 as_fatal (_("internal: can't hash `%s': %s"),
1420 mips16_opcodes
[i
].name
, retval
);
1423 if (mips16_opcodes
[i
].pinfo
!= INSN_MACRO
1424 && ((mips16_opcodes
[i
].match
& mips16_opcodes
[i
].mask
)
1425 != mips16_opcodes
[i
].match
))
1427 fprintf (stderr
, _("internal error: bad mips16 opcode: %s %s\n"),
1428 mips16_opcodes
[i
].name
, mips16_opcodes
[i
].args
);
1431 if (mips16_nop_insn
.insn_mo
== NULL
&& strcmp (name
, "nop") == 0)
1433 create_insn (&mips16_nop_insn
, mips16_opcodes
+ i
);
1434 mips16_nop_insn
.fixed_p
= 1;
1438 while (i
< bfd_mips16_num_opcodes
1439 && strcmp (mips16_opcodes
[i
].name
, name
) == 0);
1443 as_fatal (_("Broken assembler. No assembly attempted."));
1445 /* We add all the general register names to the symbol table. This
1446 helps us detect invalid uses of them. */
1447 for (i
= 0; i
< 32; i
++)
1451 sprintf (buf
, "$%d", i
);
1452 symbol_table_insert (symbol_new (buf
, reg_section
, i
,
1453 &zero_address_frag
));
1455 symbol_table_insert (symbol_new ("$ra", reg_section
, RA
,
1456 &zero_address_frag
));
1457 symbol_table_insert (symbol_new ("$fp", reg_section
, FP
,
1458 &zero_address_frag
));
1459 symbol_table_insert (symbol_new ("$sp", reg_section
, SP
,
1460 &zero_address_frag
));
1461 symbol_table_insert (symbol_new ("$gp", reg_section
, GP
,
1462 &zero_address_frag
));
1463 symbol_table_insert (symbol_new ("$at", reg_section
, AT
,
1464 &zero_address_frag
));
1465 symbol_table_insert (symbol_new ("$kt0", reg_section
, KT0
,
1466 &zero_address_frag
));
1467 symbol_table_insert (symbol_new ("$kt1", reg_section
, KT1
,
1468 &zero_address_frag
));
1469 symbol_table_insert (symbol_new ("$zero", reg_section
, ZERO
,
1470 &zero_address_frag
));
1471 symbol_table_insert (symbol_new ("$pc", reg_section
, -1,
1472 &zero_address_frag
));
1474 /* If we don't add these register names to the symbol table, they
1475 may end up being added as regular symbols by operand(), and then
1476 make it to the object file as undefined in case they're not
1477 regarded as local symbols. They're local in o32, since `$' is a
1478 local symbol prefix, but not in n32 or n64. */
1479 for (i
= 0; i
< 8; i
++)
1483 sprintf (buf
, "$fcc%i", i
);
1484 symbol_table_insert (symbol_new (buf
, reg_section
, -1,
1485 &zero_address_frag
));
1488 mips_no_prev_insn ();
1491 mips_cprmask
[0] = 0;
1492 mips_cprmask
[1] = 0;
1493 mips_cprmask
[2] = 0;
1494 mips_cprmask
[3] = 0;
1496 /* set the default alignment for the text section (2**2) */
1497 record_alignment (text_section
, 2);
1499 bfd_set_gp_size (stdoutput
, g_switch_value
);
1501 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
1503 /* On a native system, sections must be aligned to 16 byte
1504 boundaries. When configured for an embedded ELF target, we
1506 if (strcmp (TARGET_OS
, "elf") != 0)
1508 (void) bfd_set_section_alignment (stdoutput
, text_section
, 4);
1509 (void) bfd_set_section_alignment (stdoutput
, data_section
, 4);
1510 (void) bfd_set_section_alignment (stdoutput
, bss_section
, 4);
1513 /* Create a .reginfo section for register masks and a .mdebug
1514 section for debugging information. */
1522 subseg
= now_subseg
;
1524 /* The ABI says this section should be loaded so that the
1525 running program can access it. However, we don't load it
1526 if we are configured for an embedded target */
1527 flags
= SEC_READONLY
| SEC_DATA
;
1528 if (strcmp (TARGET_OS
, "elf") != 0)
1529 flags
|= SEC_ALLOC
| SEC_LOAD
;
1531 if (mips_abi
!= N64_ABI
)
1533 sec
= subseg_new (".reginfo", (subsegT
) 0);
1535 bfd_set_section_flags (stdoutput
, sec
, flags
);
1536 bfd_set_section_alignment (stdoutput
, sec
, HAVE_NEWABI
? 3 : 2);
1539 mips_regmask_frag
= frag_more (sizeof (Elf32_External_RegInfo
));
1544 /* The 64-bit ABI uses a .MIPS.options section rather than
1545 .reginfo section. */
1546 sec
= subseg_new (".MIPS.options", (subsegT
) 0);
1547 bfd_set_section_flags (stdoutput
, sec
, flags
);
1548 bfd_set_section_alignment (stdoutput
, sec
, 3);
1551 /* Set up the option header. */
1553 Elf_Internal_Options opthdr
;
1556 opthdr
.kind
= ODK_REGINFO
;
1557 opthdr
.size
= (sizeof (Elf_External_Options
)
1558 + sizeof (Elf64_External_RegInfo
));
1561 f
= frag_more (sizeof (Elf_External_Options
));
1562 bfd_mips_elf_swap_options_out (stdoutput
, &opthdr
,
1563 (Elf_External_Options
*) f
);
1565 mips_regmask_frag
= frag_more (sizeof (Elf64_External_RegInfo
));
1570 if (ECOFF_DEBUGGING
)
1572 sec
= subseg_new (".mdebug", (subsegT
) 0);
1573 (void) bfd_set_section_flags (stdoutput
, sec
,
1574 SEC_HAS_CONTENTS
| SEC_READONLY
);
1575 (void) bfd_set_section_alignment (stdoutput
, sec
, 2);
1578 else if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
&& mips_flag_pdr
)
1580 pdr_seg
= subseg_new (".pdr", (subsegT
) 0);
1581 (void) bfd_set_section_flags (stdoutput
, pdr_seg
,
1582 SEC_READONLY
| SEC_RELOC
1584 (void) bfd_set_section_alignment (stdoutput
, pdr_seg
, 2);
1588 subseg_set (seg
, subseg
);
1592 if (! ECOFF_DEBUGGING
)
1595 if (mips_fix_vr4120
)
1596 init_vr4120_conflicts ();
1602 if (! ECOFF_DEBUGGING
)
1607 md_assemble (char *str
)
1609 struct mips_cl_insn insn
;
1610 bfd_reloc_code_real_type unused_reloc
[3]
1611 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
1613 imm_expr
.X_op
= O_absent
;
1614 imm2_expr
.X_op
= O_absent
;
1615 offset_expr
.X_op
= O_absent
;
1616 imm_reloc
[0] = BFD_RELOC_UNUSED
;
1617 imm_reloc
[1] = BFD_RELOC_UNUSED
;
1618 imm_reloc
[2] = BFD_RELOC_UNUSED
;
1619 offset_reloc
[0] = BFD_RELOC_UNUSED
;
1620 offset_reloc
[1] = BFD_RELOC_UNUSED
;
1621 offset_reloc
[2] = BFD_RELOC_UNUSED
;
1623 if (mips_opts
.mips16
)
1624 mips16_ip (str
, &insn
);
1627 mips_ip (str
, &insn
);
1628 DBG ((_("returned from mips_ip(%s) insn_opcode = 0x%x\n"),
1629 str
, insn
.insn_opcode
));
1634 as_bad ("%s `%s'", insn_error
, str
);
1638 if (insn
.insn_mo
->pinfo
== INSN_MACRO
)
1641 if (mips_opts
.mips16
)
1642 mips16_macro (&insn
);
1649 if (imm_expr
.X_op
!= O_absent
)
1650 append_insn (&insn
, &imm_expr
, imm_reloc
);
1651 else if (offset_expr
.X_op
!= O_absent
)
1652 append_insn (&insn
, &offset_expr
, offset_reloc
);
1654 append_insn (&insn
, NULL
, unused_reloc
);
1658 /* Return true if the given relocation might need a matching %lo().
1659 Note that R_MIPS_GOT16 relocations only need a matching %lo() when
1660 applied to local symbols. */
1662 static inline bfd_boolean
1663 reloc_needs_lo_p (bfd_reloc_code_real_type reloc
)
1665 return (HAVE_IN_PLACE_ADDENDS
1666 && (reloc
== BFD_RELOC_HI16_S
1667 || reloc
== BFD_RELOC_MIPS_GOT16
1668 || reloc
== BFD_RELOC_MIPS16_HI16_S
));
1671 /* Return true if the given fixup is followed by a matching R_MIPS_LO16
1674 static inline bfd_boolean
1675 fixup_has_matching_lo_p (fixS
*fixp
)
1677 return (fixp
->fx_next
!= NULL
1678 && (fixp
->fx_next
->fx_r_type
== BFD_RELOC_LO16
1679 || fixp
->fx_next
->fx_r_type
== BFD_RELOC_MIPS16_LO16
)
1680 && fixp
->fx_addsy
== fixp
->fx_next
->fx_addsy
1681 && fixp
->fx_offset
== fixp
->fx_next
->fx_offset
);
1684 /* See whether instruction IP reads register REG. CLASS is the type
1688 insn_uses_reg (const struct mips_cl_insn
*ip
, unsigned int reg
,
1689 enum mips_regclass
class)
1691 if (class == MIPS16_REG
)
1693 assert (mips_opts
.mips16
);
1694 reg
= mips16_to_32_reg_map
[reg
];
1695 class = MIPS_GR_REG
;
1698 /* Don't report on general register ZERO, since it never changes. */
1699 if (class == MIPS_GR_REG
&& reg
== ZERO
)
1702 if (class == MIPS_FP_REG
)
1704 assert (! mips_opts
.mips16
);
1705 /* If we are called with either $f0 or $f1, we must check $f0.
1706 This is not optimal, because it will introduce an unnecessary
1707 NOP between "lwc1 $f0" and "swc1 $f1". To fix this we would
1708 need to distinguish reading both $f0 and $f1 or just one of
1709 them. Note that we don't have to check the other way,
1710 because there is no instruction that sets both $f0 and $f1
1711 and requires a delay. */
1712 if ((ip
->insn_mo
->pinfo
& INSN_READ_FPR_S
)
1713 && ((EXTRACT_OPERAND (FS
, *ip
) & ~(unsigned) 1)
1714 == (reg
&~ (unsigned) 1)))
1716 if ((ip
->insn_mo
->pinfo
& INSN_READ_FPR_T
)
1717 && ((EXTRACT_OPERAND (FT
, *ip
) & ~(unsigned) 1)
1718 == (reg
&~ (unsigned) 1)))
1721 else if (! mips_opts
.mips16
)
1723 if ((ip
->insn_mo
->pinfo
& INSN_READ_GPR_S
)
1724 && EXTRACT_OPERAND (RS
, *ip
) == reg
)
1726 if ((ip
->insn_mo
->pinfo
& INSN_READ_GPR_T
)
1727 && EXTRACT_OPERAND (RT
, *ip
) == reg
)
1732 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_X
)
1733 && mips16_to_32_reg_map
[MIPS16_EXTRACT_OPERAND (RX
, *ip
)] == reg
)
1735 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_Y
)
1736 && mips16_to_32_reg_map
[MIPS16_EXTRACT_OPERAND (RY
, *ip
)] == reg
)
1738 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_Z
)
1739 && (mips16_to_32_reg_map
[MIPS16_EXTRACT_OPERAND (MOVE32Z
, *ip
)]
1742 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_T
) && reg
== TREG
)
1744 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_SP
) && reg
== SP
)
1746 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_31
) && reg
== RA
)
1748 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_GPR_X
)
1749 && MIPS16_EXTRACT_OPERAND (REGR32
, *ip
) == reg
)
1756 /* This function returns true if modifying a register requires a
1760 reg_needs_delay (unsigned int reg
)
1762 unsigned long prev_pinfo
;
1764 prev_pinfo
= history
[0].insn_mo
->pinfo
;
1765 if (! mips_opts
.noreorder
1766 && (((prev_pinfo
& INSN_LOAD_MEMORY_DELAY
)
1767 && ! gpr_interlocks
)
1768 || ((prev_pinfo
& INSN_LOAD_COPROC_DELAY
)
1769 && ! cop_interlocks
)))
1771 /* A load from a coprocessor or from memory. All load delays
1772 delay the use of general register rt for one instruction. */
1773 /* Itbl support may require additional care here. */
1774 know (prev_pinfo
& INSN_WRITE_GPR_T
);
1775 if (reg
== EXTRACT_OPERAND (RT
, history
[0]))
1782 /* Move all labels in insn_labels to the current insertion point. */
1785 mips_move_labels (void)
1787 struct insn_label_list
*l
;
1790 for (l
= insn_labels
; l
!= NULL
; l
= l
->next
)
1792 assert (S_GET_SEGMENT (l
->label
) == now_seg
);
1793 symbol_set_frag (l
->label
, frag_now
);
1794 val
= (valueT
) frag_now_fix ();
1795 /* mips16 text labels are stored as odd. */
1796 if (mips_opts
.mips16
)
1798 S_SET_VALUE (l
->label
, val
);
1802 /* Mark instruction labels in mips16 mode. This permits the linker to
1803 handle them specially, such as generating jalx instructions when
1804 needed. We also make them odd for the duration of the assembly, in
1805 order to generate the right sort of code. We will make them even
1806 in the adjust_symtab routine, while leaving them marked. This is
1807 convenient for the debugger and the disassembler. The linker knows
1808 to make them odd again. */
1811 mips16_mark_labels (void)
1813 if (mips_opts
.mips16
)
1815 struct insn_label_list
*l
;
1818 for (l
= insn_labels
; l
!= NULL
; l
= l
->next
)
1821 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
1822 S_SET_OTHER (l
->label
, STO_MIPS16
);
1824 val
= S_GET_VALUE (l
->label
);
1826 S_SET_VALUE (l
->label
, val
+ 1);
1831 /* End the current frag. Make it a variant frag and record the
1835 relax_close_frag (void)
1837 mips_macro_warning
.first_frag
= frag_now
;
1838 frag_var (rs_machine_dependent
, 0, 0,
1839 RELAX_ENCODE (mips_relax
.sizes
[0], mips_relax
.sizes
[1]),
1840 mips_relax
.symbol
, 0, (char *) mips_relax
.first_fixup
);
1842 memset (&mips_relax
.sizes
, 0, sizeof (mips_relax
.sizes
));
1843 mips_relax
.first_fixup
= 0;
1846 /* Start a new relaxation sequence whose expansion depends on SYMBOL.
1847 See the comment above RELAX_ENCODE for more details. */
1850 relax_start (symbolS
*symbol
)
1852 assert (mips_relax
.sequence
== 0);
1853 mips_relax
.sequence
= 1;
1854 mips_relax
.symbol
= symbol
;
1857 /* Start generating the second version of a relaxable sequence.
1858 See the comment above RELAX_ENCODE for more details. */
1863 assert (mips_relax
.sequence
== 1);
1864 mips_relax
.sequence
= 2;
1867 /* End the current relaxable sequence. */
1872 assert (mips_relax
.sequence
== 2);
1873 relax_close_frag ();
1874 mips_relax
.sequence
= 0;
1877 /* Classify an instruction according to the FIX_VR4120_* enumeration.
1878 Return NUM_FIX_VR4120_CLASSES if the instruction isn't affected
1879 by VR4120 errata. */
1882 classify_vr4120_insn (const char *name
)
1884 if (strncmp (name
, "macc", 4) == 0)
1885 return FIX_VR4120_MACC
;
1886 if (strncmp (name
, "dmacc", 5) == 0)
1887 return FIX_VR4120_DMACC
;
1888 if (strncmp (name
, "mult", 4) == 0)
1889 return FIX_VR4120_MULT
;
1890 if (strncmp (name
, "dmult", 5) == 0)
1891 return FIX_VR4120_DMULT
;
1892 if (strstr (name
, "div"))
1893 return FIX_VR4120_DIV
;
1894 if (strcmp (name
, "mtlo") == 0 || strcmp (name
, "mthi") == 0)
1895 return FIX_VR4120_MTHILO
;
1896 return NUM_FIX_VR4120_CLASSES
;
1899 /* Return the number of instructions that must separate INSN1 and INSN2,
1900 where INSN1 is the earlier instruction. Return the worst-case value
1901 for any INSN2 if INSN2 is null. */
1904 insns_between (const struct mips_cl_insn
*insn1
,
1905 const struct mips_cl_insn
*insn2
)
1907 unsigned long pinfo1
, pinfo2
;
1909 /* This function needs to know which pinfo flags are set for INSN2
1910 and which registers INSN2 uses. The former is stored in PINFO2 and
1911 the latter is tested via INSN2_USES_REG. If INSN2 is null, PINFO2
1912 will have every flag set and INSN2_USES_REG will always return true. */
1913 pinfo1
= insn1
->insn_mo
->pinfo
;
1914 pinfo2
= insn2
? insn2
->insn_mo
->pinfo
: ~0U;
1916 #define INSN2_USES_REG(REG, CLASS) \
1917 (insn2 == NULL || insn_uses_reg (insn2, REG, CLASS))
1919 /* For most targets, write-after-read dependencies on the HI and LO
1920 registers must be separated by at least two instructions. */
1921 if (!hilo_interlocks
)
1923 if ((pinfo1
& INSN_READ_LO
) && (pinfo2
& INSN_WRITE_LO
))
1925 if ((pinfo1
& INSN_READ_HI
) && (pinfo2
& INSN_WRITE_HI
))
1929 /* If we're working around r7000 errata, there must be two instructions
1930 between an mfhi or mflo and any instruction that uses the result. */
1931 if (mips_7000_hilo_fix
1932 && MF_HILO_INSN (pinfo1
)
1933 && INSN2_USES_REG (EXTRACT_OPERAND (RD
, *insn1
), MIPS_GR_REG
))
1936 /* If working around VR4120 errata, check for combinations that need
1937 a single intervening instruction. */
1938 if (mips_fix_vr4120
)
1940 unsigned int class1
, class2
;
1942 class1
= classify_vr4120_insn (insn1
->insn_mo
->name
);
1943 if (class1
!= NUM_FIX_VR4120_CLASSES
&& vr4120_conflicts
[class1
] != 0)
1947 class2
= classify_vr4120_insn (insn2
->insn_mo
->name
);
1948 if (vr4120_conflicts
[class1
] & (1 << class2
))
1953 if (!mips_opts
.mips16
)
1955 /* Check for GPR or coprocessor load delays. All such delays
1956 are on the RT register. */
1957 /* Itbl support may require additional care here. */
1958 if ((!gpr_interlocks
&& (pinfo1
& INSN_LOAD_MEMORY_DELAY
))
1959 || (!cop_interlocks
&& (pinfo1
& INSN_LOAD_COPROC_DELAY
)))
1961 know (pinfo1
& INSN_WRITE_GPR_T
);
1962 if (INSN2_USES_REG (EXTRACT_OPERAND (RT
, *insn1
), MIPS_GR_REG
))
1966 /* Check for generic coprocessor hazards.
1968 This case is not handled very well. There is no special
1969 knowledge of CP0 handling, and the coprocessors other than
1970 the floating point unit are not distinguished at all. */
1971 /* Itbl support may require additional care here. FIXME!
1972 Need to modify this to include knowledge about
1973 user specified delays! */
1974 else if ((!cop_interlocks
&& (pinfo1
& INSN_COPROC_MOVE_DELAY
))
1975 || (!cop_mem_interlocks
&& (pinfo1
& INSN_COPROC_MEMORY_DELAY
)))
1977 /* Handle cases where INSN1 writes to a known general coprocessor
1978 register. There must be a one instruction delay before INSN2
1979 if INSN2 reads that register, otherwise no delay is needed. */
1980 if (pinfo1
& INSN_WRITE_FPR_T
)
1982 if (INSN2_USES_REG (EXTRACT_OPERAND (FT
, *insn1
), MIPS_FP_REG
))
1985 else if (pinfo1
& INSN_WRITE_FPR_S
)
1987 if (INSN2_USES_REG (EXTRACT_OPERAND (FS
, *insn1
), MIPS_FP_REG
))
1992 /* Read-after-write dependencies on the control registers
1993 require a two-instruction gap. */
1994 if ((pinfo1
& INSN_WRITE_COND_CODE
)
1995 && (pinfo2
& INSN_READ_COND_CODE
))
1998 /* We don't know exactly what INSN1 does. If INSN2 is
1999 also a coprocessor instruction, assume there must be
2000 a one instruction gap. */
2001 if (pinfo2
& INSN_COP
)
2006 /* Check for read-after-write dependencies on the coprocessor
2007 control registers in cases where INSN1 does not need a general
2008 coprocessor delay. This means that INSN1 is a floating point
2009 comparison instruction. */
2010 /* Itbl support may require additional care here. */
2011 else if (!cop_interlocks
2012 && (pinfo1
& INSN_WRITE_COND_CODE
)
2013 && (pinfo2
& INSN_READ_COND_CODE
))
2017 #undef INSN2_USES_REG
2022 /* Return the number of nops that would be needed to work around the
2023 VR4130 mflo/mfhi errata if instruction INSN immediately followed
2024 the MAX_VR4130_NOPS instructions described by HISTORY. */
2027 nops_for_vr4130 (const struct mips_cl_insn
*history
,
2028 const struct mips_cl_insn
*insn
)
2032 /* Check if the instruction writes to HI or LO. MTHI and MTLO
2033 are not affected by the errata. */
2035 && ((insn
->insn_mo
->pinfo
& (INSN_WRITE_HI
| INSN_WRITE_LO
)) == 0
2036 || strcmp (insn
->insn_mo
->name
, "mtlo") == 0
2037 || strcmp (insn
->insn_mo
->name
, "mthi") == 0))
2040 /* Search for the first MFLO or MFHI. */
2041 for (i
= 0; i
< MAX_VR4130_NOPS
; i
++)
2042 if (!history
[i
].noreorder_p
&& MF_HILO_INSN (history
[i
].insn_mo
->pinfo
))
2044 /* Extract the destination register. */
2045 if (mips_opts
.mips16
)
2046 reg
= mips16_to_32_reg_map
[MIPS16_EXTRACT_OPERAND (RX
, history
[i
])];
2048 reg
= EXTRACT_OPERAND (RD
, history
[i
]);
2050 /* No nops are needed if INSN reads that register. */
2051 if (insn
!= NULL
&& insn_uses_reg (insn
, reg
, MIPS_GR_REG
))
2054 /* ...or if any of the intervening instructions do. */
2055 for (j
= 0; j
< i
; j
++)
2056 if (insn_uses_reg (&history
[j
], reg
, MIPS_GR_REG
))
2059 return MAX_VR4130_NOPS
- i
;
2064 /* Return the number of nops that would be needed if instruction INSN
2065 immediately followed the MAX_NOPS instructions given by HISTORY,
2066 where HISTORY[0] is the most recent instruction. If INSN is null,
2067 return the worse-case number of nops for any instruction. */
2070 nops_for_insn (const struct mips_cl_insn
*history
,
2071 const struct mips_cl_insn
*insn
)
2073 int i
, nops
, tmp_nops
;
2076 for (i
= 0; i
< MAX_DELAY_NOPS
; i
++)
2077 if (!history
[i
].noreorder_p
)
2079 tmp_nops
= insns_between (history
+ i
, insn
) - i
;
2080 if (tmp_nops
> nops
)
2084 if (mips_fix_vr4130
)
2086 tmp_nops
= nops_for_vr4130 (history
, insn
);
2087 if (tmp_nops
> nops
)
2094 /* The variable arguments provide NUM_INSNS extra instructions that
2095 might be added to HISTORY. Return the largest number of nops that
2096 would be needed after the extended sequence. */
2099 nops_for_sequence (int num_insns
, const struct mips_cl_insn
*history
, ...)
2102 struct mips_cl_insn buffer
[MAX_NOPS
];
2103 struct mips_cl_insn
*cursor
;
2106 va_start (args
, history
);
2107 cursor
= buffer
+ num_insns
;
2108 memcpy (cursor
, history
, (MAX_NOPS
- num_insns
) * sizeof (*cursor
));
2109 while (cursor
> buffer
)
2110 *--cursor
= *va_arg (args
, const struct mips_cl_insn
*);
2112 nops
= nops_for_insn (buffer
, NULL
);
2117 /* Like nops_for_insn, but if INSN is a branch, take into account the
2118 worst-case delay for the branch target. */
2121 nops_for_insn_or_target (const struct mips_cl_insn
*history
,
2122 const struct mips_cl_insn
*insn
)
2126 nops
= nops_for_insn (history
, insn
);
2127 if (insn
->insn_mo
->pinfo
& (INSN_UNCOND_BRANCH_DELAY
2128 | INSN_COND_BRANCH_DELAY
2129 | INSN_COND_BRANCH_LIKELY
))
2131 tmp_nops
= nops_for_sequence (2, history
, insn
, NOP_INSN
);
2132 if (tmp_nops
> nops
)
2135 else if (mips_opts
.mips16
&& (insn
->insn_mo
->pinfo
& MIPS16_INSN_BRANCH
))
2137 tmp_nops
= nops_for_sequence (1, history
, insn
);
2138 if (tmp_nops
> nops
)
2144 /* Output an instruction. IP is the instruction information.
2145 ADDRESS_EXPR is an operand of the instruction to be used with
2149 append_insn (struct mips_cl_insn
*ip
, expressionS
*address_expr
,
2150 bfd_reloc_code_real_type
*reloc_type
)
2152 register unsigned long prev_pinfo
, pinfo
;
2153 relax_stateT prev_insn_frag_type
= 0;
2154 bfd_boolean relaxed_branch
= FALSE
;
2156 /* Mark instruction labels in mips16 mode. */
2157 mips16_mark_labels ();
2159 prev_pinfo
= history
[0].insn_mo
->pinfo
;
2160 pinfo
= ip
->insn_mo
->pinfo
;
2162 if (mips_relax
.sequence
!= 2 && !mips_opts
.noreorder
)
2164 /* There are a lot of optimizations we could do that we don't.
2165 In particular, we do not, in general, reorder instructions.
2166 If you use gcc with optimization, it will reorder
2167 instructions and generally do much more optimization then we
2168 do here; repeating all that work in the assembler would only
2169 benefit hand written assembly code, and does not seem worth
2171 int nops
= (mips_optimize
== 0
2172 ? nops_for_insn (history
, NULL
)
2173 : nops_for_insn_or_target (history
, ip
));
2177 unsigned long old_frag_offset
;
2180 old_frag
= frag_now
;
2181 old_frag_offset
= frag_now_fix ();
2183 for (i
= 0; i
< nops
; i
++)
2188 listing_prev_line ();
2189 /* We may be at the start of a variant frag. In case we
2190 are, make sure there is enough space for the frag
2191 after the frags created by listing_prev_line. The
2192 argument to frag_grow here must be at least as large
2193 as the argument to all other calls to frag_grow in
2194 this file. We don't have to worry about being in the
2195 middle of a variant frag, because the variants insert
2196 all needed nop instructions themselves. */
2200 mips_move_labels ();
2202 #ifndef NO_ECOFF_DEBUGGING
2203 if (ECOFF_DEBUGGING
)
2204 ecoff_fix_loc (old_frag
, old_frag_offset
);
2208 else if (mips_relax
.sequence
!= 2 && prev_nop_frag
!= NULL
)
2210 /* Work out how many nops in prev_nop_frag are needed by IP. */
2211 int nops
= nops_for_insn_or_target (history
, ip
);
2212 assert (nops
<= prev_nop_frag_holds
);
2214 /* Enforce NOPS as a minimum. */
2215 if (nops
> prev_nop_frag_required
)
2216 prev_nop_frag_required
= nops
;
2218 if (prev_nop_frag_holds
== prev_nop_frag_required
)
2220 /* Settle for the current number of nops. Update the history
2221 accordingly (for the benefit of any future .set reorder code). */
2222 prev_nop_frag
= NULL
;
2223 insert_into_history (prev_nop_frag_since
,
2224 prev_nop_frag_holds
, NOP_INSN
);
2228 /* Allow this instruction to replace one of the nops that was
2229 tentatively added to prev_nop_frag. */
2230 prev_nop_frag
->fr_fix
-= mips_opts
.mips16
? 2 : 4;
2231 prev_nop_frag_holds
--;
2232 prev_nop_frag_since
++;
2237 /* The value passed to dwarf2_emit_insn is the distance between
2238 the beginning of the current instruction and the address that
2239 should be recorded in the debug tables. For MIPS16 debug info
2240 we want to use ISA-encoded addresses, so we pass -1 for an
2241 address higher by one than the current. */
2242 dwarf2_emit_insn (mips_opts
.mips16
? -1 : 0);
2245 /* Record the frag type before frag_var. */
2246 if (history
[0].frag
)
2247 prev_insn_frag_type
= history
[0].frag
->fr_type
;
2250 && *reloc_type
== BFD_RELOC_16_PCREL_S2
2251 && (pinfo
& INSN_UNCOND_BRANCH_DELAY
|| pinfo
& INSN_COND_BRANCH_DELAY
2252 || pinfo
& INSN_COND_BRANCH_LIKELY
)
2253 && mips_relax_branch
2254 /* Don't try branch relaxation within .set nomacro, or within
2255 .set noat if we use $at for PIC computations. If it turns
2256 out that the branch was out-of-range, we'll get an error. */
2257 && !mips_opts
.warn_about_macros
2258 && !(mips_opts
.noat
&& mips_pic
!= NO_PIC
)
2259 && !mips_opts
.mips16
)
2261 relaxed_branch
= TRUE
;
2262 add_relaxed_insn (ip
, (relaxed_branch_length
2264 (pinfo
& INSN_UNCOND_BRANCH_DELAY
) ? -1
2265 : (pinfo
& INSN_COND_BRANCH_LIKELY
) ? 1
2268 (pinfo
& INSN_UNCOND_BRANCH_DELAY
,
2269 pinfo
& INSN_COND_BRANCH_LIKELY
,
2270 pinfo
& INSN_WRITE_GPR_31
,
2272 address_expr
->X_add_symbol
,
2273 address_expr
->X_add_number
);
2274 *reloc_type
= BFD_RELOC_UNUSED
;
2276 else if (*reloc_type
> BFD_RELOC_UNUSED
)
2278 /* We need to set up a variant frag. */
2279 assert (mips_opts
.mips16
&& address_expr
!= NULL
);
2280 add_relaxed_insn (ip
, 4, 0,
2282 (*reloc_type
- BFD_RELOC_UNUSED
,
2283 mips16_small
, mips16_ext
,
2284 prev_pinfo
& INSN_UNCOND_BRANCH_DELAY
,
2285 history
[0].mips16_absolute_jump_p
),
2286 make_expr_symbol (address_expr
), 0);
2288 else if (mips_opts
.mips16
2290 && *reloc_type
!= BFD_RELOC_MIPS16_JMP
)
2292 /* Make sure there is enough room to swap this instruction with
2293 a following jump instruction. */
2295 add_fixed_insn (ip
);
2299 if (mips_opts
.mips16
2300 && mips_opts
.noreorder
2301 && (prev_pinfo
& INSN_UNCOND_BRANCH_DELAY
) != 0)
2302 as_warn (_("extended instruction in delay slot"));
2304 if (mips_relax
.sequence
)
2306 /* If we've reached the end of this frag, turn it into a variant
2307 frag and record the information for the instructions we've
2309 if (frag_room () < 4)
2310 relax_close_frag ();
2311 mips_relax
.sizes
[mips_relax
.sequence
- 1] += 4;
2314 if (mips_relax
.sequence
!= 2)
2315 mips_macro_warning
.sizes
[0] += 4;
2316 if (mips_relax
.sequence
!= 1)
2317 mips_macro_warning
.sizes
[1] += 4;
2319 if (mips_opts
.mips16
)
2322 ip
->mips16_absolute_jump_p
= (*reloc_type
== BFD_RELOC_MIPS16_JMP
);
2324 add_fixed_insn (ip
);
2327 if (address_expr
!= NULL
&& *reloc_type
<= BFD_RELOC_UNUSED
)
2329 if (address_expr
->X_op
== O_constant
)
2333 switch (*reloc_type
)
2336 ip
->insn_opcode
|= address_expr
->X_add_number
;
2339 case BFD_RELOC_MIPS_HIGHEST
:
2340 tmp
= (address_expr
->X_add_number
+ 0x800080008000ull
) >> 48;
2341 ip
->insn_opcode
|= tmp
& 0xffff;
2344 case BFD_RELOC_MIPS_HIGHER
:
2345 tmp
= (address_expr
->X_add_number
+ 0x80008000ull
) >> 32;
2346 ip
->insn_opcode
|= tmp
& 0xffff;
2349 case BFD_RELOC_HI16_S
:
2350 tmp
= (address_expr
->X_add_number
+ 0x8000) >> 16;
2351 ip
->insn_opcode
|= tmp
& 0xffff;
2354 case BFD_RELOC_HI16
:
2355 ip
->insn_opcode
|= (address_expr
->X_add_number
>> 16) & 0xffff;
2358 case BFD_RELOC_UNUSED
:
2359 case BFD_RELOC_LO16
:
2360 case BFD_RELOC_MIPS_GOT_DISP
:
2361 ip
->insn_opcode
|= address_expr
->X_add_number
& 0xffff;
2364 case BFD_RELOC_MIPS_JMP
:
2365 if ((address_expr
->X_add_number
& 3) != 0)
2366 as_bad (_("jump to misaligned address (0x%lx)"),
2367 (unsigned long) address_expr
->X_add_number
);
2368 if (address_expr
->X_add_number
& ~0xfffffff)
2369 as_bad (_("jump address range overflow (0x%lx)"),
2370 (unsigned long) address_expr
->X_add_number
);
2371 ip
->insn_opcode
|= (address_expr
->X_add_number
>> 2) & 0x3ffffff;
2374 case BFD_RELOC_MIPS16_JMP
:
2375 if ((address_expr
->X_add_number
& 3) != 0)
2376 as_bad (_("jump to misaligned address (0x%lx)"),
2377 (unsigned long) address_expr
->X_add_number
);
2378 if (address_expr
->X_add_number
& ~0xfffffff)
2379 as_bad (_("jump address range overflow (0x%lx)"),
2380 (unsigned long) address_expr
->X_add_number
);
2382 (((address_expr
->X_add_number
& 0x7c0000) << 3)
2383 | ((address_expr
->X_add_number
& 0xf800000) >> 7)
2384 | ((address_expr
->X_add_number
& 0x3fffc) >> 2));
2387 case BFD_RELOC_16_PCREL_S2
:
2394 else if (*reloc_type
< BFD_RELOC_UNUSED
)
2397 reloc_howto_type
*howto
;
2400 /* In a compound relocation, it is the final (outermost)
2401 operator that determines the relocated field. */
2402 for (i
= 1; i
< 3; i
++)
2403 if (reloc_type
[i
] == BFD_RELOC_UNUSED
)
2406 howto
= bfd_reloc_type_lookup (stdoutput
, reloc_type
[i
- 1]);
2407 ip
->fixp
[0] = fix_new_exp (ip
->frag
, ip
->where
,
2408 bfd_get_reloc_size (howto
),
2410 reloc_type
[0] == BFD_RELOC_16_PCREL_S2
,
2413 /* These relocations can have an addend that won't fit in
2414 4 octets for 64bit assembly. */
2416 && ! howto
->partial_inplace
2417 && (reloc_type
[0] == BFD_RELOC_16
2418 || reloc_type
[0] == BFD_RELOC_32
2419 || reloc_type
[0] == BFD_RELOC_MIPS_JMP
2420 || reloc_type
[0] == BFD_RELOC_HI16_S
2421 || reloc_type
[0] == BFD_RELOC_LO16
2422 || reloc_type
[0] == BFD_RELOC_GPREL16
2423 || reloc_type
[0] == BFD_RELOC_MIPS_LITERAL
2424 || reloc_type
[0] == BFD_RELOC_GPREL32
2425 || reloc_type
[0] == BFD_RELOC_64
2426 || reloc_type
[0] == BFD_RELOC_CTOR
2427 || reloc_type
[0] == BFD_RELOC_MIPS_SUB
2428 || reloc_type
[0] == BFD_RELOC_MIPS_HIGHEST
2429 || reloc_type
[0] == BFD_RELOC_MIPS_HIGHER
2430 || reloc_type
[0] == BFD_RELOC_MIPS_SCN_DISP
2431 || reloc_type
[0] == BFD_RELOC_MIPS_REL16
2432 || reloc_type
[0] == BFD_RELOC_MIPS_RELGOT
2433 || reloc_type
[0] == BFD_RELOC_MIPS16_GPREL
2434 || reloc_type
[0] == BFD_RELOC_MIPS16_HI16_S
2435 || reloc_type
[0] == BFD_RELOC_MIPS16_LO16
))
2436 ip
->fixp
[0]->fx_no_overflow
= 1;
2438 if (mips_relax
.sequence
)
2440 if (mips_relax
.first_fixup
== 0)
2441 mips_relax
.first_fixup
= ip
->fixp
[0];
2443 else if (reloc_needs_lo_p (*reloc_type
))
2445 struct mips_hi_fixup
*hi_fixup
;
2447 /* Reuse the last entry if it already has a matching %lo. */
2448 hi_fixup
= mips_hi_fixup_list
;
2450 || !fixup_has_matching_lo_p (hi_fixup
->fixp
))
2452 hi_fixup
= ((struct mips_hi_fixup
*)
2453 xmalloc (sizeof (struct mips_hi_fixup
)));
2454 hi_fixup
->next
= mips_hi_fixup_list
;
2455 mips_hi_fixup_list
= hi_fixup
;
2457 hi_fixup
->fixp
= ip
->fixp
[0];
2458 hi_fixup
->seg
= now_seg
;
2461 /* Add fixups for the second and third relocations, if given.
2462 Note that the ABI allows the second relocation to be
2463 against RSS_UNDEF, RSS_GP, RSS_GP0 or RSS_LOC. At the
2464 moment we only use RSS_UNDEF, but we could add support
2465 for the others if it ever becomes necessary. */
2466 for (i
= 1; i
< 3; i
++)
2467 if (reloc_type
[i
] != BFD_RELOC_UNUSED
)
2469 ip
->fixp
[i
] = fix_new (ip
->frag
, ip
->where
,
2470 ip
->fixp
[0]->fx_size
, NULL
, 0,
2471 FALSE
, reloc_type
[i
]);
2473 /* Use fx_tcbit to mark compound relocs. */
2474 ip
->fixp
[0]->fx_tcbit
= 1;
2475 ip
->fixp
[i
]->fx_tcbit
= 1;
2481 /* Update the register mask information. */
2482 if (! mips_opts
.mips16
)
2484 if (pinfo
& INSN_WRITE_GPR_D
)
2485 mips_gprmask
|= 1 << EXTRACT_OPERAND (RD
, *ip
);
2486 if ((pinfo
& (INSN_WRITE_GPR_T
| INSN_READ_GPR_T
)) != 0)
2487 mips_gprmask
|= 1 << EXTRACT_OPERAND (RT
, *ip
);
2488 if (pinfo
& INSN_READ_GPR_S
)
2489 mips_gprmask
|= 1 << EXTRACT_OPERAND (RS
, *ip
);
2490 if (pinfo
& INSN_WRITE_GPR_31
)
2491 mips_gprmask
|= 1 << RA
;
2492 if (pinfo
& INSN_WRITE_FPR_D
)
2493 mips_cprmask
[1] |= 1 << EXTRACT_OPERAND (FD
, *ip
);
2494 if ((pinfo
& (INSN_WRITE_FPR_S
| INSN_READ_FPR_S
)) != 0)
2495 mips_cprmask
[1] |= 1 << EXTRACT_OPERAND (FS
, *ip
);
2496 if ((pinfo
& (INSN_WRITE_FPR_T
| INSN_READ_FPR_T
)) != 0)
2497 mips_cprmask
[1] |= 1 << EXTRACT_OPERAND (FT
, *ip
);
2498 if ((pinfo
& INSN_READ_FPR_R
) != 0)
2499 mips_cprmask
[1] |= 1 << EXTRACT_OPERAND (FR
, *ip
);
2500 if (pinfo
& INSN_COP
)
2502 /* We don't keep enough information to sort these cases out.
2503 The itbl support does keep this information however, although
2504 we currently don't support itbl fprmats as part of the cop
2505 instruction. May want to add this support in the future. */
2507 /* Never set the bit for $0, which is always zero. */
2508 mips_gprmask
&= ~1 << 0;
2512 if (pinfo
& (MIPS16_INSN_WRITE_X
| MIPS16_INSN_READ_X
))
2513 mips_gprmask
|= 1 << MIPS16_EXTRACT_OPERAND (RX
, *ip
);
2514 if (pinfo
& (MIPS16_INSN_WRITE_Y
| MIPS16_INSN_READ_Y
))
2515 mips_gprmask
|= 1 << MIPS16_EXTRACT_OPERAND (RY
, *ip
);
2516 if (pinfo
& MIPS16_INSN_WRITE_Z
)
2517 mips_gprmask
|= 1 << MIPS16_EXTRACT_OPERAND (RZ
, *ip
);
2518 if (pinfo
& (MIPS16_INSN_WRITE_T
| MIPS16_INSN_READ_T
))
2519 mips_gprmask
|= 1 << TREG
;
2520 if (pinfo
& (MIPS16_INSN_WRITE_SP
| MIPS16_INSN_READ_SP
))
2521 mips_gprmask
|= 1 << SP
;
2522 if (pinfo
& (MIPS16_INSN_WRITE_31
| MIPS16_INSN_READ_31
))
2523 mips_gprmask
|= 1 << RA
;
2524 if (pinfo
& MIPS16_INSN_WRITE_GPR_Y
)
2525 mips_gprmask
|= 1 << MIPS16OP_EXTRACT_REG32R (ip
->insn_opcode
);
2526 if (pinfo
& MIPS16_INSN_READ_Z
)
2527 mips_gprmask
|= 1 << MIPS16_EXTRACT_OPERAND (MOVE32Z
, *ip
);
2528 if (pinfo
& MIPS16_INSN_READ_GPR_X
)
2529 mips_gprmask
|= 1 << MIPS16_EXTRACT_OPERAND (REGR32
, *ip
);
2532 if (mips_relax
.sequence
!= 2 && !mips_opts
.noreorder
)
2534 /* Filling the branch delay slot is more complex. We try to
2535 switch the branch with the previous instruction, which we can
2536 do if the previous instruction does not set up a condition
2537 that the branch tests and if the branch is not itself the
2538 target of any branch. */
2539 if ((pinfo
& INSN_UNCOND_BRANCH_DELAY
)
2540 || (pinfo
& INSN_COND_BRANCH_DELAY
))
2542 if (mips_optimize
< 2
2543 /* If we have seen .set volatile or .set nomove, don't
2545 || mips_opts
.nomove
!= 0
2546 /* We can't swap if the previous instruction's position
2548 || history
[0].fixed_p
2549 /* If the previous previous insn was in a .set
2550 noreorder, we can't swap. Actually, the MIPS
2551 assembler will swap in this situation. However, gcc
2552 configured -with-gnu-as will generate code like
2558 in which we can not swap the bne and INSN. If gcc is
2559 not configured -with-gnu-as, it does not output the
2561 || history
[1].noreorder_p
2562 /* If the branch is itself the target of a branch, we
2563 can not swap. We cheat on this; all we check for is
2564 whether there is a label on this instruction. If
2565 there are any branches to anything other than a
2566 label, users must use .set noreorder. */
2567 || insn_labels
!= NULL
2568 /* If the previous instruction is in a variant frag
2569 other than this branch's one, we cannot do the swap.
2570 This does not apply to the mips16, which uses variant
2571 frags for different purposes. */
2572 || (! mips_opts
.mips16
2573 && prev_insn_frag_type
== rs_machine_dependent
)
2574 /* Check for conflicts between the branch and the instructions
2575 before the candidate delay slot. */
2576 || nops_for_insn (history
+ 1, ip
) > 0
2577 /* Check for conflicts between the swapped sequence and the
2578 target of the branch. */
2579 || nops_for_sequence (2, history
+ 1, ip
, history
) > 0
2580 /* We do not swap with a trap instruction, since it
2581 complicates trap handlers to have the trap
2582 instruction be in a delay slot. */
2583 || (prev_pinfo
& INSN_TRAP
)
2584 /* If the branch reads a register that the previous
2585 instruction sets, we can not swap. */
2586 || (! mips_opts
.mips16
2587 && (prev_pinfo
& INSN_WRITE_GPR_T
)
2588 && insn_uses_reg (ip
, EXTRACT_OPERAND (RT
, history
[0]),
2590 || (! mips_opts
.mips16
2591 && (prev_pinfo
& INSN_WRITE_GPR_D
)
2592 && insn_uses_reg (ip
, EXTRACT_OPERAND (RD
, history
[0]),
2594 || (mips_opts
.mips16
2595 && (((prev_pinfo
& MIPS16_INSN_WRITE_X
)
2597 (ip
, MIPS16_EXTRACT_OPERAND (RX
, history
[0]),
2599 || ((prev_pinfo
& MIPS16_INSN_WRITE_Y
)
2601 (ip
, MIPS16_EXTRACT_OPERAND (RY
, history
[0]),
2603 || ((prev_pinfo
& MIPS16_INSN_WRITE_Z
)
2605 (ip
, MIPS16_EXTRACT_OPERAND (RZ
, history
[0]),
2607 || ((prev_pinfo
& MIPS16_INSN_WRITE_T
)
2608 && insn_uses_reg (ip
, TREG
, MIPS_GR_REG
))
2609 || ((prev_pinfo
& MIPS16_INSN_WRITE_31
)
2610 && insn_uses_reg (ip
, RA
, MIPS_GR_REG
))
2611 || ((prev_pinfo
& MIPS16_INSN_WRITE_GPR_Y
)
2612 && insn_uses_reg (ip
,
2613 MIPS16OP_EXTRACT_REG32R
2614 (history
[0].insn_opcode
),
2616 /* If the branch writes a register that the previous
2617 instruction sets, we can not swap (we know that
2618 branches write only to RD or to $31). */
2619 || (! mips_opts
.mips16
2620 && (prev_pinfo
& INSN_WRITE_GPR_T
)
2621 && (((pinfo
& INSN_WRITE_GPR_D
)
2622 && (EXTRACT_OPERAND (RT
, history
[0])
2623 == EXTRACT_OPERAND (RD
, *ip
)))
2624 || ((pinfo
& INSN_WRITE_GPR_31
)
2625 && EXTRACT_OPERAND (RT
, history
[0]) == RA
)))
2626 || (! mips_opts
.mips16
2627 && (prev_pinfo
& INSN_WRITE_GPR_D
)
2628 && (((pinfo
& INSN_WRITE_GPR_D
)
2629 && (EXTRACT_OPERAND (RD
, history
[0])
2630 == EXTRACT_OPERAND (RD
, *ip
)))
2631 || ((pinfo
& INSN_WRITE_GPR_31
)
2632 && EXTRACT_OPERAND (RD
, history
[0]) == RA
)))
2633 || (mips_opts
.mips16
2634 && (pinfo
& MIPS16_INSN_WRITE_31
)
2635 && ((prev_pinfo
& MIPS16_INSN_WRITE_31
)
2636 || ((prev_pinfo
& MIPS16_INSN_WRITE_GPR_Y
)
2637 && (MIPS16OP_EXTRACT_REG32R (history
[0].insn_opcode
)
2639 /* If the branch writes a register that the previous
2640 instruction reads, we can not swap (we know that
2641 branches only write to RD or to $31). */
2642 || (! mips_opts
.mips16
2643 && (pinfo
& INSN_WRITE_GPR_D
)
2644 && insn_uses_reg (&history
[0],
2645 EXTRACT_OPERAND (RD
, *ip
),
2647 || (! mips_opts
.mips16
2648 && (pinfo
& INSN_WRITE_GPR_31
)
2649 && insn_uses_reg (&history
[0], RA
, MIPS_GR_REG
))
2650 || (mips_opts
.mips16
2651 && (pinfo
& MIPS16_INSN_WRITE_31
)
2652 && insn_uses_reg (&history
[0], RA
, MIPS_GR_REG
))
2653 /* If one instruction sets a condition code and the
2654 other one uses a condition code, we can not swap. */
2655 || ((pinfo
& INSN_READ_COND_CODE
)
2656 && (prev_pinfo
& INSN_WRITE_COND_CODE
))
2657 || ((pinfo
& INSN_WRITE_COND_CODE
)
2658 && (prev_pinfo
& INSN_READ_COND_CODE
))
2659 /* If the previous instruction uses the PC, we can not
2661 || (mips_opts
.mips16
2662 && (prev_pinfo
& MIPS16_INSN_READ_PC
))
2663 /* If the previous instruction had a fixup in mips16
2664 mode, we can not swap. This normally means that the
2665 previous instruction was a 4 byte branch anyhow. */
2666 || (mips_opts
.mips16
&& history
[0].fixp
[0])
2667 /* If the previous instruction is a sync, sync.l, or
2668 sync.p, we can not swap. */
2669 || (prev_pinfo
& INSN_SYNC
))
2671 /* We could do even better for unconditional branches to
2672 portions of this object file; we could pick up the
2673 instruction at the destination, put it in the delay
2674 slot, and bump the destination address. */
2675 insert_into_history (0, 1, ip
);
2677 if (mips_relax
.sequence
)
2678 mips_relax
.sizes
[mips_relax
.sequence
- 1] += 4;
2682 /* It looks like we can actually do the swap. */
2683 struct mips_cl_insn delay
= history
[0];
2684 if (mips_opts
.mips16
)
2686 know (delay
.frag
== ip
->frag
);
2687 move_insn (ip
, delay
.frag
, delay
.where
);
2688 move_insn (&delay
, ip
->frag
, ip
->where
+ insn_length (ip
));
2690 else if (relaxed_branch
)
2692 /* Add the delay slot instruction to the end of the
2693 current frag and shrink the fixed part of the
2694 original frag. If the branch occupies the tail of
2695 the latter, move it backwards to cover the gap. */
2696 delay
.frag
->fr_fix
-= 4;
2697 if (delay
.frag
== ip
->frag
)
2698 move_insn (ip
, ip
->frag
, ip
->where
- 4);
2699 add_fixed_insn (&delay
);
2703 move_insn (&delay
, ip
->frag
, ip
->where
);
2704 move_insn (ip
, history
[0].frag
, history
[0].where
);
2708 insert_into_history (0, 1, &delay
);
2711 /* If that was an unconditional branch, forget the previous
2712 insn information. */
2713 if (pinfo
& INSN_UNCOND_BRANCH_DELAY
)
2714 mips_no_prev_insn ();
2716 else if (pinfo
& INSN_COND_BRANCH_LIKELY
)
2718 /* We don't yet optimize a branch likely. What we should do
2719 is look at the target, copy the instruction found there
2720 into the delay slot, and increment the branch to jump to
2721 the next instruction. */
2722 insert_into_history (0, 1, ip
);
2726 insert_into_history (0, 1, ip
);
2729 insert_into_history (0, 1, ip
);
2731 /* We just output an insn, so the next one doesn't have a label. */
2732 mips_clear_insn_labels ();
2735 /* Forget that there was any previous instruction or label. */
2738 mips_no_prev_insn (void)
2740 prev_nop_frag
= NULL
;
2741 insert_into_history (0, ARRAY_SIZE (history
), NOP_INSN
);
2742 mips_clear_insn_labels ();
2745 /* This function must be called before we emit something other than
2746 instructions. It is like mips_no_prev_insn except that it inserts
2747 any NOPS that might be needed by previous instructions. */
2750 mips_emit_delays (void)
2752 if (! mips_opts
.noreorder
)
2754 int nops
= nops_for_insn (history
, NULL
);
2758 add_fixed_insn (NOP_INSN
);
2759 mips_move_labels ();
2762 mips_no_prev_insn ();
2765 /* Start a (possibly nested) noreorder block. */
2768 start_noreorder (void)
2770 if (mips_opts
.noreorder
== 0)
2775 /* None of the instructions before the .set noreorder can be moved. */
2776 for (i
= 0; i
< ARRAY_SIZE (history
); i
++)
2777 history
[i
].fixed_p
= 1;
2779 /* Insert any nops that might be needed between the .set noreorder
2780 block and the previous instructions. We will later remove any
2781 nops that turn out not to be needed. */
2782 nops
= nops_for_insn (history
, NULL
);
2785 if (mips_optimize
!= 0)
2787 /* Record the frag which holds the nop instructions, so
2788 that we can remove them if we don't need them. */
2789 frag_grow (mips_opts
.mips16
? nops
* 2 : nops
* 4);
2790 prev_nop_frag
= frag_now
;
2791 prev_nop_frag_holds
= nops
;
2792 prev_nop_frag_required
= 0;
2793 prev_nop_frag_since
= 0;
2796 for (; nops
> 0; --nops
)
2797 add_fixed_insn (NOP_INSN
);
2799 /* Move on to a new frag, so that it is safe to simply
2800 decrease the size of prev_nop_frag. */
2801 frag_wane (frag_now
);
2803 mips_move_labels ();
2805 mips16_mark_labels ();
2806 mips_clear_insn_labels ();
2808 mips_opts
.noreorder
++;
2809 mips_any_noreorder
= 1;
2812 /* End a nested noreorder block. */
2815 end_noreorder (void)
2817 mips_opts
.noreorder
--;
2818 if (mips_opts
.noreorder
== 0 && prev_nop_frag
!= NULL
)
2820 /* Commit to inserting prev_nop_frag_required nops and go back to
2821 handling nop insertion the .set reorder way. */
2822 prev_nop_frag
->fr_fix
-= ((prev_nop_frag_holds
- prev_nop_frag_required
)
2823 * (mips_opts
.mips16
? 2 : 4));
2824 insert_into_history (prev_nop_frag_since
,
2825 prev_nop_frag_required
, NOP_INSN
);
2826 prev_nop_frag
= NULL
;
2830 /* Set up global variables for the start of a new macro. */
2835 memset (&mips_macro_warning
.sizes
, 0, sizeof (mips_macro_warning
.sizes
));
2836 mips_macro_warning
.delay_slot_p
= (mips_opts
.noreorder
2837 && (history
[0].insn_mo
->pinfo
2838 & (INSN_UNCOND_BRANCH_DELAY
2839 | INSN_COND_BRANCH_DELAY
2840 | INSN_COND_BRANCH_LIKELY
)) != 0);
2843 /* Given that a macro is longer than 4 bytes, return the appropriate warning
2844 for it. Return null if no warning is needed. SUBTYPE is a bitmask of
2845 RELAX_DELAY_SLOT and RELAX_NOMACRO. */
2848 macro_warning (relax_substateT subtype
)
2850 if (subtype
& RELAX_DELAY_SLOT
)
2851 return _("Macro instruction expanded into multiple instructions"
2852 " in a branch delay slot");
2853 else if (subtype
& RELAX_NOMACRO
)
2854 return _("Macro instruction expanded into multiple instructions");
2859 /* Finish up a macro. Emit warnings as appropriate. */
2864 if (mips_macro_warning
.sizes
[0] > 4 || mips_macro_warning
.sizes
[1] > 4)
2866 relax_substateT subtype
;
2868 /* Set up the relaxation warning flags. */
2870 if (mips_macro_warning
.sizes
[1] > mips_macro_warning
.sizes
[0])
2871 subtype
|= RELAX_SECOND_LONGER
;
2872 if (mips_opts
.warn_about_macros
)
2873 subtype
|= RELAX_NOMACRO
;
2874 if (mips_macro_warning
.delay_slot_p
)
2875 subtype
|= RELAX_DELAY_SLOT
;
2877 if (mips_macro_warning
.sizes
[0] > 4 && mips_macro_warning
.sizes
[1] > 4)
2879 /* Either the macro has a single implementation or both
2880 implementations are longer than 4 bytes. Emit the
2882 const char *msg
= macro_warning (subtype
);
2888 /* One implementation might need a warning but the other
2889 definitely doesn't. */
2890 mips_macro_warning
.first_frag
->fr_subtype
|= subtype
;
2895 /* Read a macro's relocation codes from *ARGS and store them in *R.
2896 The first argument in *ARGS will be either the code for a single
2897 relocation or -1 followed by the three codes that make up a
2898 composite relocation. */
2901 macro_read_relocs (va_list *args
, bfd_reloc_code_real_type
*r
)
2905 next
= va_arg (*args
, int);
2907 r
[0] = (bfd_reloc_code_real_type
) next
;
2909 for (i
= 0; i
< 3; i
++)
2910 r
[i
] = (bfd_reloc_code_real_type
) va_arg (*args
, int);
2913 /* Build an instruction created by a macro expansion. This is passed
2914 a pointer to the count of instructions created so far, an
2915 expression, the name of the instruction to build, an operand format
2916 string, and corresponding arguments. */
2919 macro_build (expressionS
*ep
, const char *name
, const char *fmt
, ...)
2921 const struct mips_opcode
*mo
;
2922 struct mips_cl_insn insn
;
2923 bfd_reloc_code_real_type r
[3];
2926 va_start (args
, fmt
);
2928 if (mips_opts
.mips16
)
2930 mips16_macro_build (ep
, name
, fmt
, args
);
2935 r
[0] = BFD_RELOC_UNUSED
;
2936 r
[1] = BFD_RELOC_UNUSED
;
2937 r
[2] = BFD_RELOC_UNUSED
;
2938 mo
= (struct mips_opcode
*) hash_find (op_hash
, name
);
2940 assert (strcmp (name
, mo
->name
) == 0);
2942 /* Search until we get a match for NAME. It is assumed here that
2943 macros will never generate MDMX or MIPS-3D instructions. */
2944 while (strcmp (fmt
, mo
->args
) != 0
2945 || mo
->pinfo
== INSN_MACRO
2946 || !OPCODE_IS_MEMBER (mo
,
2948 | (file_ase_mips16
? INSN_MIPS16
: 0)),
2950 || (mips_opts
.arch
== CPU_R4650
&& (mo
->pinfo
& FP_D
) != 0))
2954 assert (strcmp (name
, mo
->name
) == 0);
2957 create_insn (&insn
, mo
);
2975 INSERT_OPERAND (SHAMT
, insn
, va_arg (args
, int));
2980 /* Note that in the macro case, these arguments are already
2981 in MSB form. (When handling the instruction in the
2982 non-macro case, these arguments are sizes from which
2983 MSB values must be calculated.) */
2984 INSERT_OPERAND (INSMSB
, insn
, va_arg (args
, int));
2990 /* Note that in the macro case, these arguments are already
2991 in MSBD form. (When handling the instruction in the
2992 non-macro case, these arguments are sizes from which
2993 MSBD values must be calculated.) */
2994 INSERT_OPERAND (EXTMSBD
, insn
, va_arg (args
, int));
3005 INSERT_OPERAND (RT
, insn
, va_arg (args
, int));
3009 INSERT_OPERAND (CODE
, insn
, va_arg (args
, int));
3014 INSERT_OPERAND (FT
, insn
, va_arg (args
, int));
3020 INSERT_OPERAND (RD
, insn
, va_arg (args
, int));
3025 int tmp
= va_arg (args
, int);
3027 INSERT_OPERAND (RT
, insn
, tmp
);
3028 INSERT_OPERAND (RD
, insn
, tmp
);
3034 INSERT_OPERAND (FS
, insn
, va_arg (args
, int));
3041 INSERT_OPERAND (SHAMT
, insn
, va_arg (args
, int));
3045 INSERT_OPERAND (FD
, insn
, va_arg (args
, int));
3049 INSERT_OPERAND (CODE20
, insn
, va_arg (args
, int));
3053 INSERT_OPERAND (CODE19
, insn
, va_arg (args
, int));
3057 INSERT_OPERAND (CODE2
, insn
, va_arg (args
, int));
3064 INSERT_OPERAND (RS
, insn
, va_arg (args
, int));
3070 macro_read_relocs (&args
, r
);
3071 assert (*r
== BFD_RELOC_GPREL16
3072 || *r
== BFD_RELOC_MIPS_LITERAL
3073 || *r
== BFD_RELOC_MIPS_HIGHER
3074 || *r
== BFD_RELOC_HI16_S
3075 || *r
== BFD_RELOC_LO16
3076 || *r
== BFD_RELOC_MIPS_GOT16
3077 || *r
== BFD_RELOC_MIPS_CALL16
3078 || *r
== BFD_RELOC_MIPS_GOT_DISP
3079 || *r
== BFD_RELOC_MIPS_GOT_PAGE
3080 || *r
== BFD_RELOC_MIPS_GOT_OFST
3081 || *r
== BFD_RELOC_MIPS_GOT_LO16
3082 || *r
== BFD_RELOC_MIPS_CALL_LO16
);
3086 macro_read_relocs (&args
, r
);
3088 && (ep
->X_op
== O_constant
3089 || (ep
->X_op
== O_symbol
3090 && (*r
== BFD_RELOC_MIPS_HIGHEST
3091 || *r
== BFD_RELOC_HI16_S
3092 || *r
== BFD_RELOC_HI16
3093 || *r
== BFD_RELOC_GPREL16
3094 || *r
== BFD_RELOC_MIPS_GOT_HI16
3095 || *r
== BFD_RELOC_MIPS_CALL_HI16
))));
3099 assert (ep
!= NULL
);
3101 * This allows macro() to pass an immediate expression for
3102 * creating short branches without creating a symbol.
3103 * Note that the expression still might come from the assembly
3104 * input, in which case the value is not checked for range nor
3105 * is a relocation entry generated (yuck).
3107 if (ep
->X_op
== O_constant
)
3109 insn
.insn_opcode
|= (ep
->X_add_number
>> 2) & 0xffff;
3113 *r
= BFD_RELOC_16_PCREL_S2
;
3117 assert (ep
!= NULL
);
3118 *r
= BFD_RELOC_MIPS_JMP
;
3122 insn
.insn_opcode
|= va_arg (args
, unsigned long);
3131 assert (*r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
3133 append_insn (&insn
, ep
, r
);
3137 mips16_macro_build (expressionS
*ep
, const char *name
, const char *fmt
,
3140 struct mips_opcode
*mo
;
3141 struct mips_cl_insn insn
;
3142 bfd_reloc_code_real_type r
[3]
3143 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
3145 mo
= (struct mips_opcode
*) hash_find (mips16_op_hash
, name
);
3147 assert (strcmp (name
, mo
->name
) == 0);
3149 while (strcmp (fmt
, mo
->args
) != 0 || mo
->pinfo
== INSN_MACRO
)
3153 assert (strcmp (name
, mo
->name
) == 0);
3156 create_insn (&insn
, mo
);
3174 MIPS16_INSERT_OPERAND (RY
, insn
, va_arg (args
, int));
3179 MIPS16_INSERT_OPERAND (RX
, insn
, va_arg (args
, int));
3183 MIPS16_INSERT_OPERAND (RZ
, insn
, va_arg (args
, int));
3187 MIPS16_INSERT_OPERAND (MOVE32Z
, insn
, va_arg (args
, int));
3197 MIPS16_INSERT_OPERAND (REGR32
, insn
, va_arg (args
, int));
3204 regno
= va_arg (args
, int);
3205 regno
= ((regno
& 7) << 2) | ((regno
& 0x18) >> 3);
3206 insn
.insn_opcode
|= regno
<< MIPS16OP_SH_REG32R
;
3227 assert (ep
!= NULL
);
3229 if (ep
->X_op
!= O_constant
)
3230 *r
= (int) BFD_RELOC_UNUSED
+ c
;
3233 mips16_immed (NULL
, 0, c
, ep
->X_add_number
, FALSE
, FALSE
,
3234 FALSE
, &insn
.insn_opcode
, &insn
.use_extend
,
3237 *r
= BFD_RELOC_UNUSED
;
3243 MIPS16_INSERT_OPERAND (IMM6
, insn
, va_arg (args
, int));
3250 assert (*r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
3252 append_insn (&insn
, ep
, r
);
3256 * Generate a "jalr" instruction with a relocation hint to the called
3257 * function. This occurs in NewABI PIC code.
3260 macro_build_jalr (expressionS
*ep
)
3269 macro_build (NULL
, "jalr", "d,s", RA
, PIC_CALL_REG
);
3271 fix_new_exp (frag_now
, f
- frag_now
->fr_literal
,
3272 4, ep
, FALSE
, BFD_RELOC_MIPS_JALR
);
3276 * Generate a "lui" instruction.
3279 macro_build_lui (expressionS
*ep
, int regnum
)
3281 expressionS high_expr
;
3282 const struct mips_opcode
*mo
;
3283 struct mips_cl_insn insn
;
3284 bfd_reloc_code_real_type r
[3]
3285 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
3286 const char *name
= "lui";
3287 const char *fmt
= "t,u";
3289 assert (! mips_opts
.mips16
);
3293 if (high_expr
.X_op
== O_constant
)
3295 /* we can compute the instruction now without a relocation entry */
3296 high_expr
.X_add_number
= ((high_expr
.X_add_number
+ 0x8000)
3298 *r
= BFD_RELOC_UNUSED
;
3302 assert (ep
->X_op
== O_symbol
);
3303 /* _gp_disp is a special case, used from s_cpload.
3304 __gnu_local_gp is used if mips_no_shared. */
3305 assert (mips_pic
== NO_PIC
3307 && strcmp (S_GET_NAME (ep
->X_add_symbol
), "_gp_disp") == 0)
3308 || (! mips_in_shared
3309 && strcmp (S_GET_NAME (ep
->X_add_symbol
),
3310 "__gnu_local_gp") == 0));
3311 *r
= BFD_RELOC_HI16_S
;
3314 mo
= hash_find (op_hash
, name
);
3315 assert (strcmp (name
, mo
->name
) == 0);
3316 assert (strcmp (fmt
, mo
->args
) == 0);
3317 create_insn (&insn
, mo
);
3319 insn
.insn_opcode
= insn
.insn_mo
->match
;
3320 INSERT_OPERAND (RT
, insn
, regnum
);
3321 if (*r
== BFD_RELOC_UNUSED
)
3323 insn
.insn_opcode
|= high_expr
.X_add_number
;
3324 append_insn (&insn
, NULL
, r
);
3327 append_insn (&insn
, &high_expr
, r
);
3330 /* Generate a sequence of instructions to do a load or store from a constant
3331 offset off of a base register (breg) into/from a target register (treg),
3332 using AT if necessary. */
3334 macro_build_ldst_constoffset (expressionS
*ep
, const char *op
,
3335 int treg
, int breg
, int dbl
)
3337 assert (ep
->X_op
== O_constant
);
3339 /* Sign-extending 32-bit constants makes their handling easier. */
3340 if (! dbl
&& ! ((ep
->X_add_number
& ~((bfd_vma
) 0x7fffffff))
3341 == ~((bfd_vma
) 0x7fffffff)))
3343 if (ep
->X_add_number
& ~((bfd_vma
) 0xffffffff))
3344 as_bad (_("constant too large"));
3346 ep
->X_add_number
= (((ep
->X_add_number
& 0xffffffff) ^ 0x80000000)
3350 /* Right now, this routine can only handle signed 32-bit constants. */
3351 if (! IS_SEXT_32BIT_NUM(ep
->X_add_number
+ 0x8000))
3352 as_warn (_("operand overflow"));
3354 if (IS_SEXT_16BIT_NUM(ep
->X_add_number
))
3356 /* Signed 16-bit offset will fit in the op. Easy! */
3357 macro_build (ep
, op
, "t,o(b)", treg
, BFD_RELOC_LO16
, breg
);
3361 /* 32-bit offset, need multiple instructions and AT, like:
3362 lui $tempreg,const_hi (BFD_RELOC_HI16_S)
3363 addu $tempreg,$tempreg,$breg
3364 <op> $treg,const_lo($tempreg) (BFD_RELOC_LO16)
3365 to handle the complete offset. */
3366 macro_build_lui (ep
, AT
);
3367 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, AT
, breg
);
3368 macro_build (ep
, op
, "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
3371 as_bad (_("Macro used $at after \".set noat\""));
3376 * Generates code to set the $at register to true (one)
3377 * if reg is less than the immediate expression.
3380 set_at (int reg
, int unsignedp
)
3382 if (imm_expr
.X_op
== O_constant
3383 && imm_expr
.X_add_number
>= -0x8000
3384 && imm_expr
.X_add_number
< 0x8000)
3385 macro_build (&imm_expr
, unsignedp
? "sltiu" : "slti", "t,r,j",
3386 AT
, reg
, BFD_RELOC_LO16
);
3389 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
3390 macro_build (NULL
, unsignedp
? "sltu" : "slt", "d,v,t", AT
, reg
, AT
);
3395 normalize_constant_expr (expressionS
*ex
)
3397 if (ex
->X_op
== O_constant
&& HAVE_32BIT_GPRS
)
3398 ex
->X_add_number
= (((ex
->X_add_number
& 0xffffffff) ^ 0x80000000)
3402 /* Warn if an expression is not a constant. */
3405 check_absolute_expr (struct mips_cl_insn
*ip
, expressionS
*ex
)
3407 if (ex
->X_op
== O_big
)
3408 as_bad (_("unsupported large constant"));
3409 else if (ex
->X_op
!= O_constant
)
3410 as_bad (_("Instruction %s requires absolute expression"), ip
->insn_mo
->name
);
3412 normalize_constant_expr (ex
);
3415 /* Count the leading zeroes by performing a binary chop. This is a
3416 bulky bit of source, but performance is a LOT better for the
3417 majority of values than a simple loop to count the bits:
3418 for (lcnt = 0; (lcnt < 32); lcnt++)
3419 if ((v) & (1 << (31 - lcnt)))
3421 However it is not code size friendly, and the gain will drop a bit
3422 on certain cached systems.
3424 #define COUNT_TOP_ZEROES(v) \
3425 (((v) & ~0xffff) == 0 \
3426 ? ((v) & ~0xff) == 0 \
3427 ? ((v) & ~0xf) == 0 \
3428 ? ((v) & ~0x3) == 0 \
3429 ? ((v) & ~0x1) == 0 \
3434 : ((v) & ~0x7) == 0 \
3437 : ((v) & ~0x3f) == 0 \
3438 ? ((v) & ~0x1f) == 0 \
3441 : ((v) & ~0x7f) == 0 \
3444 : ((v) & ~0xfff) == 0 \
3445 ? ((v) & ~0x3ff) == 0 \
3446 ? ((v) & ~0x1ff) == 0 \
3449 : ((v) & ~0x7ff) == 0 \
3452 : ((v) & ~0x3fff) == 0 \
3453 ? ((v) & ~0x1fff) == 0 \
3456 : ((v) & ~0x7fff) == 0 \
3459 : ((v) & ~0xffffff) == 0 \
3460 ? ((v) & ~0xfffff) == 0 \
3461 ? ((v) & ~0x3ffff) == 0 \
3462 ? ((v) & ~0x1ffff) == 0 \
3465 : ((v) & ~0x7ffff) == 0 \
3468 : ((v) & ~0x3fffff) == 0 \
3469 ? ((v) & ~0x1fffff) == 0 \
3472 : ((v) & ~0x7fffff) == 0 \
3475 : ((v) & ~0xfffffff) == 0 \
3476 ? ((v) & ~0x3ffffff) == 0 \
3477 ? ((v) & ~0x1ffffff) == 0 \
3480 : ((v) & ~0x7ffffff) == 0 \
3483 : ((v) & ~0x3fffffff) == 0 \
3484 ? ((v) & ~0x1fffffff) == 0 \
3487 : ((v) & ~0x7fffffff) == 0 \
3492 * This routine generates the least number of instructions necessary to load
3493 * an absolute expression value into a register.
3496 load_register (int reg
, expressionS
*ep
, int dbl
)
3499 expressionS hi32
, lo32
;
3501 if (ep
->X_op
!= O_big
)
3503 assert (ep
->X_op
== O_constant
);
3505 /* Sign-extending 32-bit constants makes their handling easier. */
3506 if (! dbl
&& ! ((ep
->X_add_number
& ~((bfd_vma
) 0x7fffffff))
3507 == ~((bfd_vma
) 0x7fffffff)))
3509 if (ep
->X_add_number
& ~((bfd_vma
) 0xffffffff))
3510 as_bad (_("constant too large"));
3512 ep
->X_add_number
= (((ep
->X_add_number
& 0xffffffff) ^ 0x80000000)
3516 if (IS_SEXT_16BIT_NUM (ep
->X_add_number
))
3518 /* We can handle 16 bit signed values with an addiu to
3519 $zero. No need to ever use daddiu here, since $zero and
3520 the result are always correct in 32 bit mode. */
3521 macro_build (ep
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
3524 else if (ep
->X_add_number
>= 0 && ep
->X_add_number
< 0x10000)
3526 /* We can handle 16 bit unsigned values with an ori to
3528 macro_build (ep
, "ori", "t,r,i", reg
, 0, BFD_RELOC_LO16
);
3531 else if ((IS_SEXT_32BIT_NUM (ep
->X_add_number
)))
3533 /* 32 bit values require an lui. */
3534 macro_build (ep
, "lui", "t,u", reg
, BFD_RELOC_HI16
);
3535 if ((ep
->X_add_number
& 0xffff) != 0)
3536 macro_build (ep
, "ori", "t,r,i", reg
, reg
, BFD_RELOC_LO16
);
3541 /* The value is larger than 32 bits. */
3543 if (HAVE_32BIT_GPRS
)
3545 as_bad (_("Number (0x%lx) larger than 32 bits"),
3546 (unsigned long) ep
->X_add_number
);
3547 macro_build (ep
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
3551 if (ep
->X_op
!= O_big
)
3554 hi32
.X_add_number
= (valueT
) hi32
.X_add_number
>> 16;
3555 hi32
.X_add_number
= (valueT
) hi32
.X_add_number
>> 16;
3556 hi32
.X_add_number
&= 0xffffffff;
3558 lo32
.X_add_number
&= 0xffffffff;
3562 assert (ep
->X_add_number
> 2);
3563 if (ep
->X_add_number
== 3)
3564 generic_bignum
[3] = 0;
3565 else if (ep
->X_add_number
> 4)
3566 as_bad (_("Number larger than 64 bits"));
3567 lo32
.X_op
= O_constant
;
3568 lo32
.X_add_number
= generic_bignum
[0] + (generic_bignum
[1] << 16);
3569 hi32
.X_op
= O_constant
;
3570 hi32
.X_add_number
= generic_bignum
[2] + (generic_bignum
[3] << 16);
3573 if (hi32
.X_add_number
== 0)
3578 unsigned long hi
, lo
;
3580 if (hi32
.X_add_number
== (offsetT
) 0xffffffff)
3582 if ((lo32
.X_add_number
& 0xffff8000) == 0xffff8000)
3584 macro_build (&lo32
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
3587 if (lo32
.X_add_number
& 0x80000000)
3589 macro_build (&lo32
, "lui", "t,u", reg
, BFD_RELOC_HI16
);
3590 if (lo32
.X_add_number
& 0xffff)
3591 macro_build (&lo32
, "ori", "t,r,i", reg
, reg
, BFD_RELOC_LO16
);
3596 /* Check for 16bit shifted constant. We know that hi32 is
3597 non-zero, so start the mask on the first bit of the hi32
3602 unsigned long himask
, lomask
;
3606 himask
= 0xffff >> (32 - shift
);
3607 lomask
= (0xffff << shift
) & 0xffffffff;
3611 himask
= 0xffff << (shift
- 32);
3614 if ((hi32
.X_add_number
& ~(offsetT
) himask
) == 0
3615 && (lo32
.X_add_number
& ~(offsetT
) lomask
) == 0)
3619 tmp
.X_op
= O_constant
;
3621 tmp
.X_add_number
= ((hi32
.X_add_number
<< (32 - shift
))
3622 | (lo32
.X_add_number
>> shift
));
3624 tmp
.X_add_number
= hi32
.X_add_number
>> (shift
- 32);
3625 macro_build (&tmp
, "ori", "t,r,i", reg
, 0, BFD_RELOC_LO16
);
3626 macro_build (NULL
, (shift
>= 32) ? "dsll32" : "dsll", "d,w,<",
3627 reg
, reg
, (shift
>= 32) ? shift
- 32 : shift
);
3632 while (shift
<= (64 - 16));
3634 /* Find the bit number of the lowest one bit, and store the
3635 shifted value in hi/lo. */
3636 hi
= (unsigned long) (hi32
.X_add_number
& 0xffffffff);
3637 lo
= (unsigned long) (lo32
.X_add_number
& 0xffffffff);
3641 while ((lo
& 1) == 0)
3646 lo
|= (hi
& (((unsigned long) 1 << bit
) - 1)) << (32 - bit
);
3652 while ((hi
& 1) == 0)
3661 /* Optimize if the shifted value is a (power of 2) - 1. */
3662 if ((hi
== 0 && ((lo
+ 1) & lo
) == 0)
3663 || (lo
== 0xffffffff && ((hi
+ 1) & hi
) == 0))
3665 shift
= COUNT_TOP_ZEROES ((unsigned int) hi32
.X_add_number
);
3670 /* This instruction will set the register to be all
3672 tmp
.X_op
= O_constant
;
3673 tmp
.X_add_number
= (offsetT
) -1;
3674 macro_build (&tmp
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
3678 macro_build (NULL
, (bit
>= 32) ? "dsll32" : "dsll", "d,w,<",
3679 reg
, reg
, (bit
>= 32) ? bit
- 32 : bit
);
3681 macro_build (NULL
, (shift
>= 32) ? "dsrl32" : "dsrl", "d,w,<",
3682 reg
, reg
, (shift
>= 32) ? shift
- 32 : shift
);
3687 /* Sign extend hi32 before calling load_register, because we can
3688 generally get better code when we load a sign extended value. */
3689 if ((hi32
.X_add_number
& 0x80000000) != 0)
3690 hi32
.X_add_number
|= ~(offsetT
) 0xffffffff;
3691 load_register (reg
, &hi32
, 0);
3694 if ((lo32
.X_add_number
& 0xffff0000) == 0)
3698 macro_build (NULL
, "dsll32", "d,w,<", reg
, freg
, 0);
3706 if ((freg
== 0) && (lo32
.X_add_number
== (offsetT
) 0xffffffff))
3708 macro_build (&lo32
, "lui", "t,u", reg
, BFD_RELOC_HI16
);
3709 macro_build (NULL
, "dsrl32", "d,w,<", reg
, reg
, 0);
3715 macro_build (NULL
, "dsll", "d,w,<", reg
, freg
, 16);
3719 mid16
.X_add_number
>>= 16;
3720 macro_build (&mid16
, "ori", "t,r,i", reg
, freg
, BFD_RELOC_LO16
);
3721 macro_build (NULL
, "dsll", "d,w,<", reg
, reg
, 16);
3724 if ((lo32
.X_add_number
& 0xffff) != 0)
3725 macro_build (&lo32
, "ori", "t,r,i", reg
, freg
, BFD_RELOC_LO16
);
3729 load_delay_nop (void)
3731 if (!gpr_interlocks
)
3732 macro_build (NULL
, "nop", "");
3735 /* Load an address into a register. */
3738 load_address (int reg
, expressionS
*ep
, int *used_at
)
3740 if (ep
->X_op
!= O_constant
3741 && ep
->X_op
!= O_symbol
)
3743 as_bad (_("expression too complex"));
3744 ep
->X_op
= O_constant
;
3747 if (ep
->X_op
== O_constant
)
3749 load_register (reg
, ep
, HAVE_64BIT_ADDRESSES
);
3753 if (mips_pic
== NO_PIC
)
3755 /* If this is a reference to a GP relative symbol, we want
3756 addiu $reg,$gp,<sym> (BFD_RELOC_GPREL16)
3758 lui $reg,<sym> (BFD_RELOC_HI16_S)
3759 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
3760 If we have an addend, we always use the latter form.
3762 With 64bit address space and a usable $at we want
3763 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
3764 lui $at,<sym> (BFD_RELOC_HI16_S)
3765 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
3766 daddiu $at,<sym> (BFD_RELOC_LO16)
3770 If $at is already in use, we use a path which is suboptimal
3771 on superscalar processors.
3772 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
3773 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
3775 daddiu $reg,<sym> (BFD_RELOC_HI16_S)
3777 daddiu $reg,<sym> (BFD_RELOC_LO16)
3779 For GP relative symbols in 64bit address space we can use
3780 the same sequence as in 32bit address space. */
3781 if (HAVE_64BIT_SYMBOLS
)
3783 if ((valueT
) ep
->X_add_number
<= MAX_GPREL_OFFSET
3784 && !nopic_need_relax (ep
->X_add_symbol
, 1))
3786 relax_start (ep
->X_add_symbol
);
3787 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
,
3788 mips_gp_register
, BFD_RELOC_GPREL16
);
3792 if (*used_at
== 0 && !mips_opts
.noat
)
3794 macro_build (ep
, "lui", "t,u", reg
, BFD_RELOC_MIPS_HIGHEST
);
3795 macro_build (ep
, "lui", "t,u", AT
, BFD_RELOC_HI16_S
);
3796 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
,
3797 BFD_RELOC_MIPS_HIGHER
);
3798 macro_build (ep
, "daddiu", "t,r,j", AT
, AT
, BFD_RELOC_LO16
);
3799 macro_build (NULL
, "dsll32", "d,w,<", reg
, reg
, 0);
3800 macro_build (NULL
, "daddu", "d,v,t", reg
, reg
, AT
);
3805 macro_build (ep
, "lui", "t,u", reg
, BFD_RELOC_MIPS_HIGHEST
);
3806 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
,
3807 BFD_RELOC_MIPS_HIGHER
);
3808 macro_build (NULL
, "dsll", "d,w,<", reg
, reg
, 16);
3809 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
, BFD_RELOC_HI16_S
);
3810 macro_build (NULL
, "dsll", "d,w,<", reg
, reg
, 16);
3811 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
, BFD_RELOC_LO16
);
3814 if (mips_relax
.sequence
)
3819 if ((valueT
) ep
->X_add_number
<= MAX_GPREL_OFFSET
3820 && !nopic_need_relax (ep
->X_add_symbol
, 1))
3822 relax_start (ep
->X_add_symbol
);
3823 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
,
3824 mips_gp_register
, BFD_RELOC_GPREL16
);
3827 macro_build_lui (ep
, reg
);
3828 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j",
3829 reg
, reg
, BFD_RELOC_LO16
);
3830 if (mips_relax
.sequence
)
3834 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
3838 /* If this is a reference to an external symbol, we want
3839 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3841 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3843 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
3844 If there is a constant, it must be added in after.
3846 If we have NewABI, we want
3847 lw $reg,<sym+cst>($gp) (BFD_RELOC_MIPS_GOT_DISP)
3848 unless we're referencing a global symbol with a non-zero
3849 offset, in which case cst must be added separately. */
3852 if (ep
->X_add_number
)
3854 ex
.X_add_number
= ep
->X_add_number
;
3855 ep
->X_add_number
= 0;
3856 relax_start (ep
->X_add_symbol
);
3857 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
3858 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
3859 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
3860 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
3861 ex
.X_op
= O_constant
;
3862 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j",
3863 reg
, reg
, BFD_RELOC_LO16
);
3864 ep
->X_add_number
= ex
.X_add_number
;
3867 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
3868 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
3869 if (mips_relax
.sequence
)
3874 ex
.X_add_number
= ep
->X_add_number
;
3875 ep
->X_add_number
= 0;
3876 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
3877 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
3879 relax_start (ep
->X_add_symbol
);
3881 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
3885 if (ex
.X_add_number
!= 0)
3887 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
3888 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
3889 ex
.X_op
= O_constant
;
3890 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j",
3891 reg
, reg
, BFD_RELOC_LO16
);
3895 else if (mips_pic
== SVR4_PIC
)
3899 /* This is the large GOT case. If this is a reference to an
3900 external symbol, we want
3901 lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
3903 lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16)
3905 Otherwise, for a reference to a local symbol in old ABI, we want
3906 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3908 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
3909 If there is a constant, it must be added in after.
3911 In the NewABI, for local symbols, with or without offsets, we want:
3912 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
3913 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
3917 ex
.X_add_number
= ep
->X_add_number
;
3918 ep
->X_add_number
= 0;
3919 relax_start (ep
->X_add_symbol
);
3920 macro_build (ep
, "lui", "t,u", reg
, BFD_RELOC_MIPS_GOT_HI16
);
3921 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
3922 reg
, reg
, mips_gp_register
);
3923 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)",
3924 reg
, BFD_RELOC_MIPS_GOT_LO16
, reg
);
3925 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
3926 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
3927 else if (ex
.X_add_number
)
3929 ex
.X_op
= O_constant
;
3930 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
3934 ep
->X_add_number
= ex
.X_add_number
;
3936 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
3937 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
3938 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
3939 BFD_RELOC_MIPS_GOT_OFST
);
3944 ex
.X_add_number
= ep
->X_add_number
;
3945 ep
->X_add_number
= 0;
3946 relax_start (ep
->X_add_symbol
);
3947 macro_build (ep
, "lui", "t,u", reg
, BFD_RELOC_MIPS_GOT_HI16
);
3948 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
3949 reg
, reg
, mips_gp_register
);
3950 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)",
3951 reg
, BFD_RELOC_MIPS_GOT_LO16
, reg
);
3953 if (reg_needs_delay (mips_gp_register
))
3955 /* We need a nop before loading from $gp. This special
3956 check is required because the lui which starts the main
3957 instruction stream does not refer to $gp, and so will not
3958 insert the nop which may be required. */
3959 macro_build (NULL
, "nop", "");
3961 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
3962 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
3964 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
3968 if (ex
.X_add_number
!= 0)
3970 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
3971 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
3972 ex
.X_op
= O_constant
;
3973 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
3981 if (mips_opts
.noat
&& *used_at
== 1)
3982 as_bad (_("Macro used $at after \".set noat\""));
3985 /* Move the contents of register SOURCE into register DEST. */
3988 move_register (int dest
, int source
)
3990 macro_build (NULL
, HAVE_32BIT_GPRS
? "addu" : "daddu", "d,v,t",
3994 /* Emit an SVR4 PIC sequence to load address LOCAL into DEST, where
3995 LOCAL is the sum of a symbol and a 16-bit or 32-bit displacement.
3996 The two alternatives are:
3998 Global symbol Local sybmol
3999 ------------- ------------
4000 lw DEST,%got(SYMBOL) lw DEST,%got(SYMBOL + OFFSET)
4002 addiu DEST,DEST,OFFSET addiu DEST,DEST,%lo(SYMBOL + OFFSET)
4004 load_got_offset emits the first instruction and add_got_offset
4005 emits the second for a 16-bit offset or add_got_offset_hilo emits
4006 a sequence to add a 32-bit offset using a scratch register. */
4009 load_got_offset (int dest
, expressionS
*local
)
4014 global
.X_add_number
= 0;
4016 relax_start (local
->X_add_symbol
);
4017 macro_build (&global
, ADDRESS_LOAD_INSN
, "t,o(b)", dest
,
4018 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
4020 macro_build (local
, ADDRESS_LOAD_INSN
, "t,o(b)", dest
,
4021 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
4026 add_got_offset (int dest
, expressionS
*local
)
4030 global
.X_op
= O_constant
;
4031 global
.X_op_symbol
= NULL
;
4032 global
.X_add_symbol
= NULL
;
4033 global
.X_add_number
= local
->X_add_number
;
4035 relax_start (local
->X_add_symbol
);
4036 macro_build (&global
, ADDRESS_ADDI_INSN
, "t,r,j",
4037 dest
, dest
, BFD_RELOC_LO16
);
4039 macro_build (local
, ADDRESS_ADDI_INSN
, "t,r,j", dest
, dest
, BFD_RELOC_LO16
);
4044 add_got_offset_hilo (int dest
, expressionS
*local
, int tmp
)
4047 int hold_mips_optimize
;
4049 global
.X_op
= O_constant
;
4050 global
.X_op_symbol
= NULL
;
4051 global
.X_add_symbol
= NULL
;
4052 global
.X_add_number
= local
->X_add_number
;
4054 relax_start (local
->X_add_symbol
);
4055 load_register (tmp
, &global
, HAVE_64BIT_ADDRESSES
);
4057 /* Set mips_optimize around the lui instruction to avoid
4058 inserting an unnecessary nop after the lw. */
4059 hold_mips_optimize
= mips_optimize
;
4061 macro_build_lui (&global
, tmp
);
4062 mips_optimize
= hold_mips_optimize
;
4063 macro_build (local
, ADDRESS_ADDI_INSN
, "t,r,j", tmp
, tmp
, BFD_RELOC_LO16
);
4066 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", dest
, dest
, tmp
);
4071 * This routine implements the seemingly endless macro or synthesized
4072 * instructions and addressing modes in the mips assembly language. Many
4073 * of these macros are simple and are similar to each other. These could
4074 * probably be handled by some kind of table or grammar approach instead of
4075 * this verbose method. Others are not simple macros but are more like
4076 * optimizing code generation.
4077 * One interesting optimization is when several store macros appear
4078 * consecutively that would load AT with the upper half of the same address.
4079 * The ensuing load upper instructions are ommited. This implies some kind
4080 * of global optimization. We currently only optimize within a single macro.
4081 * For many of the load and store macros if the address is specified as a
4082 * constant expression in the first 64k of memory (ie ld $2,0x4000c) we
4083 * first load register 'at' with zero and use it as the base register. The
4084 * mips assembler simply uses register $zero. Just one tiny optimization
4088 macro (struct mips_cl_insn
*ip
)
4090 register int treg
, sreg
, dreg
, breg
;
4106 bfd_reloc_code_real_type r
;
4107 int hold_mips_optimize
;
4109 assert (! mips_opts
.mips16
);
4111 treg
= (ip
->insn_opcode
>> 16) & 0x1f;
4112 dreg
= (ip
->insn_opcode
>> 11) & 0x1f;
4113 sreg
= breg
= (ip
->insn_opcode
>> 21) & 0x1f;
4114 mask
= ip
->insn_mo
->mask
;
4116 expr1
.X_op
= O_constant
;
4117 expr1
.X_op_symbol
= NULL
;
4118 expr1
.X_add_symbol
= NULL
;
4119 expr1
.X_add_number
= 1;
4133 expr1
.X_add_number
= 8;
4134 macro_build (&expr1
, "bgez", "s,p", sreg
);
4136 macro_build (NULL
, "nop", "", 0);
4138 move_register (dreg
, sreg
);
4139 macro_build (NULL
, dbl
? "dsub" : "sub", "d,v,t", dreg
, 0, sreg
);
4162 if (imm_expr
.X_op
== O_constant
4163 && imm_expr
.X_add_number
>= -0x8000
4164 && imm_expr
.X_add_number
< 0x8000)
4166 macro_build (&imm_expr
, s
, "t,r,j", treg
, sreg
, BFD_RELOC_LO16
);
4170 load_register (AT
, &imm_expr
, dbl
);
4171 macro_build (NULL
, s2
, "d,v,t", treg
, sreg
, AT
);
4190 if (imm_expr
.X_op
== O_constant
4191 && imm_expr
.X_add_number
>= 0
4192 && imm_expr
.X_add_number
< 0x10000)
4194 if (mask
!= M_NOR_I
)
4195 macro_build (&imm_expr
, s
, "t,r,i", treg
, sreg
, BFD_RELOC_LO16
);
4198 macro_build (&imm_expr
, "ori", "t,r,i",
4199 treg
, sreg
, BFD_RELOC_LO16
);
4200 macro_build (NULL
, "nor", "d,v,t", treg
, treg
, 0);
4206 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
4207 macro_build (NULL
, s2
, "d,v,t", treg
, sreg
, AT
);
4224 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
4226 macro_build (&offset_expr
, s
, "s,t,p", sreg
, 0);
4230 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
4231 macro_build (&offset_expr
, s
, "s,t,p", sreg
, AT
);
4239 macro_build (&offset_expr
, likely
? "bgezl" : "bgez", "s,p", sreg
);
4244 macro_build (&offset_expr
, likely
? "blezl" : "blez", "s,p", treg
);
4248 macro_build (NULL
, "slt", "d,v,t", AT
, sreg
, treg
);
4249 macro_build (&offset_expr
, likely
? "beql" : "beq", "s,t,p", AT
, 0);
4255 /* check for > max integer */
4256 maxnum
= 0x7fffffff;
4257 if (HAVE_64BIT_GPRS
&& sizeof (maxnum
) > 4)
4264 if (imm_expr
.X_op
== O_constant
4265 && imm_expr
.X_add_number
>= maxnum
4266 && (HAVE_32BIT_GPRS
|| sizeof (maxnum
) > 4))
4269 /* result is always false */
4271 macro_build (NULL
, "nop", "", 0);
4273 macro_build (&offset_expr
, "bnel", "s,t,p", 0, 0);
4276 if (imm_expr
.X_op
!= O_constant
)
4277 as_bad (_("Unsupported large constant"));
4278 ++imm_expr
.X_add_number
;
4282 if (mask
== M_BGEL_I
)
4284 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
4286 macro_build (&offset_expr
, likely
? "bgezl" : "bgez", "s,p", sreg
);
4289 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
4291 macro_build (&offset_expr
, likely
? "bgtzl" : "bgtz", "s,p", sreg
);
4294 maxnum
= 0x7fffffff;
4295 if (HAVE_64BIT_GPRS
&& sizeof (maxnum
) > 4)
4302 maxnum
= - maxnum
- 1;
4303 if (imm_expr
.X_op
== O_constant
4304 && imm_expr
.X_add_number
<= maxnum
4305 && (HAVE_32BIT_GPRS
|| sizeof (maxnum
) > 4))
4308 /* result is always true */
4309 as_warn (_("Branch %s is always true"), ip
->insn_mo
->name
);
4310 macro_build (&offset_expr
, "b", "p");
4315 macro_build (&offset_expr
, likely
? "beql" : "beq", "s,t,p", AT
, 0);
4325 macro_build (&offset_expr
, likely
? "beql" : "beq",
4330 macro_build (NULL
, "sltu", "d,v,t", AT
, sreg
, treg
);
4331 macro_build (&offset_expr
, likely
? "beql" : "beq", "s,t,p", AT
, 0);
4339 && imm_expr
.X_op
== O_constant
4340 && imm_expr
.X_add_number
== (offsetT
) 0xffffffff))
4342 if (imm_expr
.X_op
!= O_constant
)
4343 as_bad (_("Unsupported large constant"));
4344 ++imm_expr
.X_add_number
;
4348 if (mask
== M_BGEUL_I
)
4350 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
4352 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
4354 macro_build (&offset_expr
, likely
? "bnel" : "bne",
4360 macro_build (&offset_expr
, likely
? "beql" : "beq", "s,t,p", AT
, 0);
4368 macro_build (&offset_expr
, likely
? "bgtzl" : "bgtz", "s,p", sreg
);
4373 macro_build (&offset_expr
, likely
? "bltzl" : "bltz", "s,p", treg
);
4377 macro_build (NULL
, "slt", "d,v,t", AT
, treg
, sreg
);
4378 macro_build (&offset_expr
, likely
? "bnel" : "bne", "s,t,p", AT
, 0);
4386 macro_build (&offset_expr
, likely
? "bnel" : "bne",
4393 macro_build (NULL
, "sltu", "d,v,t", AT
, treg
, sreg
);
4394 macro_build (&offset_expr
, likely
? "bnel" : "bne", "s,t,p", AT
, 0);
4402 macro_build (&offset_expr
, likely
? "blezl" : "blez", "s,p", sreg
);
4407 macro_build (&offset_expr
, likely
? "bgezl" : "bgez", "s,p", treg
);
4411 macro_build (NULL
, "slt", "d,v,t", AT
, treg
, sreg
);
4412 macro_build (&offset_expr
, likely
? "beql" : "beq", "s,t,p", AT
, 0);
4418 maxnum
= 0x7fffffff;
4419 if (HAVE_64BIT_GPRS
&& sizeof (maxnum
) > 4)
4426 if (imm_expr
.X_op
== O_constant
4427 && imm_expr
.X_add_number
>= maxnum
4428 && (HAVE_32BIT_GPRS
|| sizeof (maxnum
) > 4))
4430 if (imm_expr
.X_op
!= O_constant
)
4431 as_bad (_("Unsupported large constant"));
4432 ++imm_expr
.X_add_number
;
4436 if (mask
== M_BLTL_I
)
4438 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
4440 macro_build (&offset_expr
, likely
? "bltzl" : "bltz", "s,p", sreg
);
4443 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
4445 macro_build (&offset_expr
, likely
? "blezl" : "blez", "s,p", sreg
);
4450 macro_build (&offset_expr
, likely
? "bnel" : "bne", "s,t,p", AT
, 0);
4458 macro_build (&offset_expr
, likely
? "beql" : "beq",
4465 macro_build (NULL
, "sltu", "d,v,t", AT
, treg
, sreg
);
4466 macro_build (&offset_expr
, likely
? "beql" : "beq", "s,t,p", AT
, 0);
4474 && imm_expr
.X_op
== O_constant
4475 && imm_expr
.X_add_number
== (offsetT
) 0xffffffff))
4477 if (imm_expr
.X_op
!= O_constant
)
4478 as_bad (_("Unsupported large constant"));
4479 ++imm_expr
.X_add_number
;
4483 if (mask
== M_BLTUL_I
)
4485 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
4487 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
4489 macro_build (&offset_expr
, likely
? "beql" : "beq",
4495 macro_build (&offset_expr
, likely
? "bnel" : "bne", "s,t,p", AT
, 0);
4503 macro_build (&offset_expr
, likely
? "bltzl" : "bltz", "s,p", sreg
);
4508 macro_build (&offset_expr
, likely
? "bgtzl" : "bgtz", "s,p", treg
);
4512 macro_build (NULL
, "slt", "d,v,t", AT
, sreg
, treg
);
4513 macro_build (&offset_expr
, likely
? "bnel" : "bne", "s,t,p", AT
, 0);
4523 macro_build (&offset_expr
, likely
? "bnel" : "bne",
4528 macro_build (NULL
, "sltu", "d,v,t", AT
, sreg
, treg
);
4529 macro_build (&offset_expr
, likely
? "bnel" : "bne", "s,t,p", AT
, 0);
4537 if (imm_expr
.X_op
!= O_constant
|| imm2_expr
.X_op
!= O_constant
)
4539 as_bad (_("Unsupported large constant"));
4544 pos
= (unsigned long) imm_expr
.X_add_number
;
4545 size
= (unsigned long) imm2_expr
.X_add_number
;
4550 as_bad (_("Improper position (%lu)"), pos
);
4553 if (size
== 0 || size
> 64
4554 || (pos
+ size
- 1) > 63)
4556 as_bad (_("Improper extract size (%lu, position %lu)"),
4561 if (size
<= 32 && pos
< 32)
4566 else if (size
<= 32)
4576 macro_build ((expressionS
*) NULL
, s
, fmt
, treg
, sreg
, pos
, size
- 1);
4585 if (imm_expr
.X_op
!= O_constant
|| imm2_expr
.X_op
!= O_constant
)
4587 as_bad (_("Unsupported large constant"));
4592 pos
= (unsigned long) imm_expr
.X_add_number
;
4593 size
= (unsigned long) imm2_expr
.X_add_number
;
4598 as_bad (_("Improper position (%lu)"), pos
);
4601 if (size
== 0 || size
> 64
4602 || (pos
+ size
- 1) > 63)
4604 as_bad (_("Improper insert size (%lu, position %lu)"),
4609 if (pos
< 32 && (pos
+ size
- 1) < 32)
4624 macro_build ((expressionS
*) NULL
, s
, fmt
, treg
, sreg
, pos
,
4641 as_warn (_("Divide by zero."));
4643 macro_build (NULL
, "teq", "s,t,q", 0, 0, 7);
4645 macro_build (NULL
, "break", "c", 7);
4652 macro_build (NULL
, "teq", "s,t,q", treg
, 0, 7);
4653 macro_build (NULL
, dbl
? "ddiv" : "div", "z,s,t", sreg
, treg
);
4657 expr1
.X_add_number
= 8;
4658 macro_build (&expr1
, "bne", "s,t,p", treg
, 0);
4659 macro_build (NULL
, dbl
? "ddiv" : "div", "z,s,t", sreg
, treg
);
4660 macro_build (NULL
, "break", "c", 7);
4662 expr1
.X_add_number
= -1;
4664 load_register (AT
, &expr1
, dbl
);
4665 expr1
.X_add_number
= mips_trap
? (dbl
? 12 : 8) : (dbl
? 20 : 16);
4666 macro_build (&expr1
, "bne", "s,t,p", treg
, AT
);
4669 expr1
.X_add_number
= 1;
4670 load_register (AT
, &expr1
, dbl
);
4671 macro_build (NULL
, "dsll32", "d,w,<", AT
, AT
, 31);
4675 expr1
.X_add_number
= 0x80000000;
4676 macro_build (&expr1
, "lui", "t,u", AT
, BFD_RELOC_HI16
);
4680 macro_build (NULL
, "teq", "s,t,q", sreg
, AT
, 6);
4681 /* We want to close the noreorder block as soon as possible, so
4682 that later insns are available for delay slot filling. */
4687 expr1
.X_add_number
= 8;
4688 macro_build (&expr1
, "bne", "s,t,p", sreg
, AT
);
4689 macro_build (NULL
, "nop", "", 0);
4691 /* We want to close the noreorder block as soon as possible, so
4692 that later insns are available for delay slot filling. */
4695 macro_build (NULL
, "break", "c", 6);
4697 macro_build (NULL
, s
, "d", dreg
);
4736 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
4738 as_warn (_("Divide by zero."));
4740 macro_build (NULL
, "teq", "s,t,q", 0, 0, 7);
4742 macro_build (NULL
, "break", "c", 7);
4745 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
4747 if (strcmp (s2
, "mflo") == 0)
4748 move_register (dreg
, sreg
);
4750 move_register (dreg
, 0);
4753 if (imm_expr
.X_op
== O_constant
4754 && imm_expr
.X_add_number
== -1
4755 && s
[strlen (s
) - 1] != 'u')
4757 if (strcmp (s2
, "mflo") == 0)
4759 macro_build (NULL
, dbl
? "dneg" : "neg", "d,w", dreg
, sreg
);
4762 move_register (dreg
, 0);
4767 load_register (AT
, &imm_expr
, dbl
);
4768 macro_build (NULL
, s
, "z,s,t", sreg
, AT
);
4769 macro_build (NULL
, s2
, "d", dreg
);
4791 macro_build (NULL
, "teq", "s,t,q", treg
, 0, 7);
4792 macro_build (NULL
, s
, "z,s,t", sreg
, treg
);
4793 /* We want to close the noreorder block as soon as possible, so
4794 that later insns are available for delay slot filling. */
4799 expr1
.X_add_number
= 8;
4800 macro_build (&expr1
, "bne", "s,t,p", treg
, 0);
4801 macro_build (NULL
, s
, "z,s,t", sreg
, treg
);
4803 /* We want to close the noreorder block as soon as possible, so
4804 that later insns are available for delay slot filling. */
4806 macro_build (NULL
, "break", "c", 7);
4808 macro_build (NULL
, s2
, "d", dreg
);
4820 /* Load the address of a symbol into a register. If breg is not
4821 zero, we then add a base register to it. */
4823 if (dbl
&& HAVE_32BIT_GPRS
)
4824 as_warn (_("dla used to load 32-bit register"));
4826 if (! dbl
&& HAVE_64BIT_OBJECTS
)
4827 as_warn (_("la used to load 64-bit address"));
4829 if (offset_expr
.X_op
== O_constant
4830 && offset_expr
.X_add_number
>= -0x8000
4831 && offset_expr
.X_add_number
< 0x8000)
4833 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
,
4834 "t,r,j", treg
, sreg
, BFD_RELOC_LO16
);
4838 if (!mips_opts
.noat
&& (treg
== breg
))
4848 if (offset_expr
.X_op
!= O_symbol
4849 && offset_expr
.X_op
!= O_constant
)
4851 as_bad (_("expression too complex"));
4852 offset_expr
.X_op
= O_constant
;
4855 if (offset_expr
.X_op
== O_constant
)
4856 load_register (tempreg
, &offset_expr
, HAVE_64BIT_ADDRESSES
);
4857 else if (mips_pic
== NO_PIC
)
4859 /* If this is a reference to a GP relative symbol, we want
4860 addiu $tempreg,$gp,<sym> (BFD_RELOC_GPREL16)
4862 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
4863 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
4864 If we have a constant, we need two instructions anyhow,
4865 so we may as well always use the latter form.
4867 With 64bit address space and a usable $at we want
4868 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
4869 lui $at,<sym> (BFD_RELOC_HI16_S)
4870 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
4871 daddiu $at,<sym> (BFD_RELOC_LO16)
4873 daddu $tempreg,$tempreg,$at
4875 If $at is already in use, we use a path which is suboptimal
4876 on superscalar processors.
4877 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
4878 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
4880 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
4882 daddiu $tempreg,<sym> (BFD_RELOC_LO16)
4884 For GP relative symbols in 64bit address space we can use
4885 the same sequence as in 32bit address space. */
4886 if (HAVE_64BIT_SYMBOLS
)
4888 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
4889 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
4891 relax_start (offset_expr
.X_add_symbol
);
4892 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
4893 tempreg
, mips_gp_register
, BFD_RELOC_GPREL16
);
4897 if (used_at
== 0 && !mips_opts
.noat
)
4899 macro_build (&offset_expr
, "lui", "t,u",
4900 tempreg
, BFD_RELOC_MIPS_HIGHEST
);
4901 macro_build (&offset_expr
, "lui", "t,u",
4902 AT
, BFD_RELOC_HI16_S
);
4903 macro_build (&offset_expr
, "daddiu", "t,r,j",
4904 tempreg
, tempreg
, BFD_RELOC_MIPS_HIGHER
);
4905 macro_build (&offset_expr
, "daddiu", "t,r,j",
4906 AT
, AT
, BFD_RELOC_LO16
);
4907 macro_build (NULL
, "dsll32", "d,w,<", tempreg
, tempreg
, 0);
4908 macro_build (NULL
, "daddu", "d,v,t", tempreg
, tempreg
, AT
);
4913 macro_build (&offset_expr
, "lui", "t,u",
4914 tempreg
, BFD_RELOC_MIPS_HIGHEST
);
4915 macro_build (&offset_expr
, "daddiu", "t,r,j",
4916 tempreg
, tempreg
, BFD_RELOC_MIPS_HIGHER
);
4917 macro_build (NULL
, "dsll", "d,w,<", tempreg
, tempreg
, 16);
4918 macro_build (&offset_expr
, "daddiu", "t,r,j",
4919 tempreg
, tempreg
, BFD_RELOC_HI16_S
);
4920 macro_build (NULL
, "dsll", "d,w,<", tempreg
, tempreg
, 16);
4921 macro_build (&offset_expr
, "daddiu", "t,r,j",
4922 tempreg
, tempreg
, BFD_RELOC_LO16
);
4925 if (mips_relax
.sequence
)
4930 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
4931 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
4933 relax_start (offset_expr
.X_add_symbol
);
4934 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
4935 tempreg
, mips_gp_register
, BFD_RELOC_GPREL16
);
4938 if (!IS_SEXT_32BIT_NUM (offset_expr
.X_add_number
))
4939 as_bad (_("offset too large"));
4940 macro_build_lui (&offset_expr
, tempreg
);
4941 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
4942 tempreg
, tempreg
, BFD_RELOC_LO16
);
4943 if (mips_relax
.sequence
)
4947 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
&& ! HAVE_NEWABI
)
4949 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT16
;
4951 /* If this is a reference to an external symbol, and there
4952 is no constant, we want
4953 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4954 or for lca or if tempreg is PIC_CALL_REG
4955 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
4956 For a local symbol, we want
4957 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4959 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
4961 If we have a small constant, and this is a reference to
4962 an external symbol, we want
4963 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4965 addiu $tempreg,$tempreg,<constant>
4966 For a local symbol, we want the same instruction
4967 sequence, but we output a BFD_RELOC_LO16 reloc on the
4970 If we have a large constant, and this is a reference to
4971 an external symbol, we want
4972 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4973 lui $at,<hiconstant>
4974 addiu $at,$at,<loconstant>
4975 addu $tempreg,$tempreg,$at
4976 For a local symbol, we want the same instruction
4977 sequence, but we output a BFD_RELOC_LO16 reloc on the
4981 if (offset_expr
.X_add_number
== 0)
4983 if (breg
== 0 && (call
|| tempreg
== PIC_CALL_REG
))
4984 lw_reloc_type
= (int) BFD_RELOC_MIPS_CALL16
;
4986 relax_start (offset_expr
.X_add_symbol
);
4987 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
4988 lw_reloc_type
, mips_gp_register
);
4991 /* We're going to put in an addu instruction using
4992 tempreg, so we may as well insert the nop right
4997 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
4998 tempreg
, BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
5000 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
5001 tempreg
, tempreg
, BFD_RELOC_LO16
);
5003 /* FIXME: If breg == 0, and the next instruction uses
5004 $tempreg, then if this variant case is used an extra
5005 nop will be generated. */
5007 else if (offset_expr
.X_add_number
>= -0x8000
5008 && offset_expr
.X_add_number
< 0x8000)
5010 load_got_offset (tempreg
, &offset_expr
);
5012 add_got_offset (tempreg
, &offset_expr
);
5016 expr1
.X_add_number
= offset_expr
.X_add_number
;
5017 offset_expr
.X_add_number
=
5018 ((offset_expr
.X_add_number
+ 0x8000) & 0xffff) - 0x8000;
5019 load_got_offset (tempreg
, &offset_expr
);
5020 offset_expr
.X_add_number
= expr1
.X_add_number
;
5021 /* If we are going to add in a base register, and the
5022 target register and the base register are the same,
5023 then we are using AT as a temporary register. Since
5024 we want to load the constant into AT, we add our
5025 current AT (from the global offset table) and the
5026 register into the register now, and pretend we were
5027 not using a base register. */
5031 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5036 add_got_offset_hilo (tempreg
, &offset_expr
, AT
);
5040 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
&& HAVE_NEWABI
)
5042 int add_breg_early
= 0;
5044 /* If this is a reference to an external, and there is no
5045 constant, or local symbol (*), with or without a
5047 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
5048 or for lca or if tempreg is PIC_CALL_REG
5049 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
5051 If we have a small constant, and this is a reference to
5052 an external symbol, we want
5053 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
5054 addiu $tempreg,$tempreg,<constant>
5056 If we have a large constant, and this is a reference to
5057 an external symbol, we want
5058 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
5059 lui $at,<hiconstant>
5060 addiu $at,$at,<loconstant>
5061 addu $tempreg,$tempreg,$at
5063 (*) Other assemblers seem to prefer GOT_PAGE/GOT_OFST for
5064 local symbols, even though it introduces an additional
5067 if (offset_expr
.X_add_number
)
5069 expr1
.X_add_number
= offset_expr
.X_add_number
;
5070 offset_expr
.X_add_number
= 0;
5072 relax_start (offset_expr
.X_add_symbol
);
5073 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
5074 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
5076 if (expr1
.X_add_number
>= -0x8000
5077 && expr1
.X_add_number
< 0x8000)
5079 macro_build (&expr1
, ADDRESS_ADDI_INSN
, "t,r,j",
5080 tempreg
, tempreg
, BFD_RELOC_LO16
);
5082 else if (IS_SEXT_32BIT_NUM (expr1
.X_add_number
+ 0x8000))
5086 /* If we are going to add in a base register, and the
5087 target register and the base register are the same,
5088 then we are using AT as a temporary register. Since
5089 we want to load the constant into AT, we add our
5090 current AT (from the global offset table) and the
5091 register into the register now, and pretend we were
5092 not using a base register. */
5097 assert (tempreg
== AT
);
5098 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5104 load_register (AT
, &expr1
, HAVE_64BIT_ADDRESSES
);
5105 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5111 as_bad (_("PIC code offset overflow (max 32 signed bits)"));
5114 offset_expr
.X_add_number
= expr1
.X_add_number
;
5116 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
5117 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
5120 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5121 treg
, tempreg
, breg
);
5127 else if (breg
== 0 && (call
|| tempreg
== PIC_CALL_REG
))
5129 relax_start (offset_expr
.X_add_symbol
);
5130 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
5131 BFD_RELOC_MIPS_CALL16
, mips_gp_register
);
5133 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
5134 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
5139 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
5140 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
5143 else if (mips_pic
== SVR4_PIC
&& ! HAVE_NEWABI
)
5146 int lui_reloc_type
= (int) BFD_RELOC_MIPS_GOT_HI16
;
5147 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT_LO16
;
5148 int local_reloc_type
= (int) BFD_RELOC_MIPS_GOT16
;
5150 /* This is the large GOT case. If this is a reference to an
5151 external symbol, and there is no constant, we want
5152 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5153 addu $tempreg,$tempreg,$gp
5154 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5155 or for lca or if tempreg is PIC_CALL_REG
5156 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
5157 addu $tempreg,$tempreg,$gp
5158 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
5159 For a local symbol, we want
5160 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5162 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
5164 If we have a small constant, and this is a reference to
5165 an external symbol, we want
5166 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5167 addu $tempreg,$tempreg,$gp
5168 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5170 addiu $tempreg,$tempreg,<constant>
5171 For a local symbol, we want
5172 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5174 addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16)
5176 If we have a large constant, and this is a reference to
5177 an external symbol, we want
5178 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5179 addu $tempreg,$tempreg,$gp
5180 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5181 lui $at,<hiconstant>
5182 addiu $at,$at,<loconstant>
5183 addu $tempreg,$tempreg,$at
5184 For a local symbol, we want
5185 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5186 lui $at,<hiconstant>
5187 addiu $at,$at,<loconstant> (BFD_RELOC_LO16)
5188 addu $tempreg,$tempreg,$at
5191 expr1
.X_add_number
= offset_expr
.X_add_number
;
5192 offset_expr
.X_add_number
= 0;
5193 relax_start (offset_expr
.X_add_symbol
);
5194 gpdelay
= reg_needs_delay (mips_gp_register
);
5195 if (expr1
.X_add_number
== 0 && breg
== 0
5196 && (call
|| tempreg
== PIC_CALL_REG
))
5198 lui_reloc_type
= (int) BFD_RELOC_MIPS_CALL_HI16
;
5199 lw_reloc_type
= (int) BFD_RELOC_MIPS_CALL_LO16
;
5201 macro_build (&offset_expr
, "lui", "t,u", tempreg
, lui_reloc_type
);
5202 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5203 tempreg
, tempreg
, mips_gp_register
);
5204 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
5205 tempreg
, lw_reloc_type
, tempreg
);
5206 if (expr1
.X_add_number
== 0)
5210 /* We're going to put in an addu instruction using
5211 tempreg, so we may as well insert the nop right
5216 else if (expr1
.X_add_number
>= -0x8000
5217 && expr1
.X_add_number
< 0x8000)
5220 macro_build (&expr1
, ADDRESS_ADDI_INSN
, "t,r,j",
5221 tempreg
, tempreg
, BFD_RELOC_LO16
);
5227 /* If we are going to add in a base register, and the
5228 target register and the base register are the same,
5229 then we are using AT as a temporary register. Since
5230 we want to load the constant into AT, we add our
5231 current AT (from the global offset table) and the
5232 register into the register now, and pretend we were
5233 not using a base register. */
5238 assert (tempreg
== AT
);
5240 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5245 load_register (AT
, &expr1
, HAVE_64BIT_ADDRESSES
);
5246 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", dreg
, dreg
, AT
);
5250 offset_expr
.X_add_number
=
5251 ((expr1
.X_add_number
+ 0x8000) & 0xffff) - 0x8000;
5256 /* This is needed because this instruction uses $gp, but
5257 the first instruction on the main stream does not. */
5258 macro_build (NULL
, "nop", "");
5261 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
5262 local_reloc_type
, mips_gp_register
);
5263 if (expr1
.X_add_number
>= -0x8000
5264 && expr1
.X_add_number
< 0x8000)
5267 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
5268 tempreg
, tempreg
, BFD_RELOC_LO16
);
5269 /* FIXME: If add_number is 0, and there was no base
5270 register, the external symbol case ended with a load,
5271 so if the symbol turns out to not be external, and
5272 the next instruction uses tempreg, an unnecessary nop
5273 will be inserted. */
5279 /* We must add in the base register now, as in the
5280 external symbol case. */
5281 assert (tempreg
== AT
);
5283 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5286 /* We set breg to 0 because we have arranged to add
5287 it in in both cases. */
5291 macro_build_lui (&expr1
, AT
);
5292 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
5293 AT
, AT
, BFD_RELOC_LO16
);
5294 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5295 tempreg
, tempreg
, AT
);
5300 else if (mips_pic
== SVR4_PIC
&& HAVE_NEWABI
)
5302 int lui_reloc_type
= (int) BFD_RELOC_MIPS_GOT_HI16
;
5303 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT_LO16
;
5304 int add_breg_early
= 0;
5306 /* This is the large GOT case. If this is a reference to an
5307 external symbol, and there is no constant, we want
5308 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5309 add $tempreg,$tempreg,$gp
5310 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5311 or for lca or if tempreg is PIC_CALL_REG
5312 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
5313 add $tempreg,$tempreg,$gp
5314 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
5316 If we have a small constant, and this is a reference to
5317 an external symbol, we want
5318 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5319 add $tempreg,$tempreg,$gp
5320 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5321 addi $tempreg,$tempreg,<constant>
5323 If we have a large constant, and this is a reference to
5324 an external symbol, we want
5325 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5326 addu $tempreg,$tempreg,$gp
5327 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5328 lui $at,<hiconstant>
5329 addi $at,$at,<loconstant>
5330 add $tempreg,$tempreg,$at
5332 If we have NewABI, and we know it's a local symbol, we want
5333 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
5334 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
5335 otherwise we have to resort to GOT_HI16/GOT_LO16. */
5337 relax_start (offset_expr
.X_add_symbol
);
5339 expr1
.X_add_number
= offset_expr
.X_add_number
;
5340 offset_expr
.X_add_number
= 0;
5342 if (expr1
.X_add_number
== 0 && breg
== 0
5343 && (call
|| tempreg
== PIC_CALL_REG
))
5345 lui_reloc_type
= (int) BFD_RELOC_MIPS_CALL_HI16
;
5346 lw_reloc_type
= (int) BFD_RELOC_MIPS_CALL_LO16
;
5348 macro_build (&offset_expr
, "lui", "t,u", tempreg
, lui_reloc_type
);
5349 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5350 tempreg
, tempreg
, mips_gp_register
);
5351 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
5352 tempreg
, lw_reloc_type
, tempreg
);
5354 if (expr1
.X_add_number
== 0)
5356 else if (expr1
.X_add_number
>= -0x8000
5357 && expr1
.X_add_number
< 0x8000)
5359 macro_build (&expr1
, ADDRESS_ADDI_INSN
, "t,r,j",
5360 tempreg
, tempreg
, BFD_RELOC_LO16
);
5362 else if (IS_SEXT_32BIT_NUM (expr1
.X_add_number
+ 0x8000))
5366 /* If we are going to add in a base register, and the
5367 target register and the base register are the same,
5368 then we are using AT as a temporary register. Since
5369 we want to load the constant into AT, we add our
5370 current AT (from the global offset table) and the
5371 register into the register now, and pretend we were
5372 not using a base register. */
5377 assert (tempreg
== AT
);
5378 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5384 load_register (AT
, &expr1
, HAVE_64BIT_ADDRESSES
);
5385 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", dreg
, dreg
, AT
);
5390 as_bad (_("PIC code offset overflow (max 32 signed bits)"));
5393 offset_expr
.X_add_number
= expr1
.X_add_number
;
5394 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
5395 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
5396 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j", tempreg
,
5397 tempreg
, BFD_RELOC_MIPS_GOT_OFST
);
5400 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5401 treg
, tempreg
, breg
);
5411 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", treg
, tempreg
, breg
);
5415 /* The j instruction may not be used in PIC code, since it
5416 requires an absolute address. We convert it to a b
5418 if (mips_pic
== NO_PIC
)
5419 macro_build (&offset_expr
, "j", "a");
5421 macro_build (&offset_expr
, "b", "p");
5424 /* The jal instructions must be handled as macros because when
5425 generating PIC code they expand to multi-instruction
5426 sequences. Normally they are simple instructions. */
5431 if (mips_pic
== NO_PIC
)
5432 macro_build (NULL
, "jalr", "d,s", dreg
, sreg
);
5433 else if (mips_pic
== SVR4_PIC
)
5435 if (sreg
!= PIC_CALL_REG
)
5436 as_warn (_("MIPS PIC call to register other than $25"));
5438 macro_build (NULL
, "jalr", "d,s", dreg
, sreg
);
5441 if (mips_cprestore_offset
< 0)
5442 as_warn (_("No .cprestore pseudo-op used in PIC code"));
5445 if (! mips_frame_reg_valid
)
5447 as_warn (_("No .frame pseudo-op used in PIC code"));
5448 /* Quiet this warning. */
5449 mips_frame_reg_valid
= 1;
5451 if (! mips_cprestore_valid
)
5453 as_warn (_("No .cprestore pseudo-op used in PIC code"));
5454 /* Quiet this warning. */
5455 mips_cprestore_valid
= 1;
5457 expr1
.X_add_number
= mips_cprestore_offset
;
5458 macro_build_ldst_constoffset (&expr1
, ADDRESS_LOAD_INSN
,
5461 HAVE_64BIT_ADDRESSES
);
5471 if (mips_pic
== NO_PIC
)
5472 macro_build (&offset_expr
, "jal", "a");
5473 else if (mips_pic
== SVR4_PIC
)
5475 /* If this is a reference to an external symbol, and we are
5476 using a small GOT, we want
5477 lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
5481 lw $gp,cprestore($sp)
5482 The cprestore value is set using the .cprestore
5483 pseudo-op. If we are using a big GOT, we want
5484 lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16)
5486 lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16)
5490 lw $gp,cprestore($sp)
5491 If the symbol is not external, we want
5492 lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5494 addiu $25,$25,<sym> (BFD_RELOC_LO16)
5497 lw $gp,cprestore($sp)
5499 For NewABI, we use the same CALL16 or CALL_HI16/CALL_LO16
5500 sequences above, minus nops, unless the symbol is local,
5501 which enables us to use GOT_PAGE/GOT_OFST (big got) or
5507 relax_start (offset_expr
.X_add_symbol
);
5508 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
5509 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL16
,
5512 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
5513 PIC_CALL_REG
, BFD_RELOC_MIPS_GOT_DISP
,
5519 relax_start (offset_expr
.X_add_symbol
);
5520 macro_build (&offset_expr
, "lui", "t,u", PIC_CALL_REG
,
5521 BFD_RELOC_MIPS_CALL_HI16
);
5522 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", PIC_CALL_REG
,
5523 PIC_CALL_REG
, mips_gp_register
);
5524 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
5525 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL_LO16
,
5528 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
5529 PIC_CALL_REG
, BFD_RELOC_MIPS_GOT_PAGE
,
5531 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
5532 PIC_CALL_REG
, PIC_CALL_REG
,
5533 BFD_RELOC_MIPS_GOT_OFST
);
5537 macro_build_jalr (&offset_expr
);
5541 relax_start (offset_expr
.X_add_symbol
);
5544 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
5545 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL16
,
5554 gpdelay
= reg_needs_delay (mips_gp_register
);
5555 macro_build (&offset_expr
, "lui", "t,u", PIC_CALL_REG
,
5556 BFD_RELOC_MIPS_CALL_HI16
);
5557 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", PIC_CALL_REG
,
5558 PIC_CALL_REG
, mips_gp_register
);
5559 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
5560 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL_LO16
,
5565 macro_build (NULL
, "nop", "");
5567 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
5568 PIC_CALL_REG
, BFD_RELOC_MIPS_GOT16
,
5571 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
5572 PIC_CALL_REG
, PIC_CALL_REG
, BFD_RELOC_LO16
);
5574 macro_build_jalr (&offset_expr
);
5576 if (mips_cprestore_offset
< 0)
5577 as_warn (_("No .cprestore pseudo-op used in PIC code"));
5580 if (! mips_frame_reg_valid
)
5582 as_warn (_("No .frame pseudo-op used in PIC code"));
5583 /* Quiet this warning. */
5584 mips_frame_reg_valid
= 1;
5586 if (! mips_cprestore_valid
)
5588 as_warn (_("No .cprestore pseudo-op used in PIC code"));
5589 /* Quiet this warning. */
5590 mips_cprestore_valid
= 1;
5592 if (mips_opts
.noreorder
)
5593 macro_build (NULL
, "nop", "");
5594 expr1
.X_add_number
= mips_cprestore_offset
;
5595 macro_build_ldst_constoffset (&expr1
, ADDRESS_LOAD_INSN
,
5598 HAVE_64BIT_ADDRESSES
);
5624 /* Itbl support may require additional care here. */
5629 /* Itbl support may require additional care here. */
5634 /* Itbl support may require additional care here. */
5639 /* Itbl support may require additional care here. */
5651 if (mips_opts
.arch
== CPU_R4650
)
5653 as_bad (_("opcode not supported on this processor"));
5657 /* Itbl support may require additional care here. */
5662 /* Itbl support may require additional care here. */
5667 /* Itbl support may require additional care here. */
5687 if (breg
== treg
|| coproc
|| lr
)
5708 /* Itbl support may require additional care here. */
5713 /* Itbl support may require additional care here. */
5718 /* Itbl support may require additional care here. */
5723 /* Itbl support may require additional care here. */
5739 if (mips_opts
.arch
== CPU_R4650
)
5741 as_bad (_("opcode not supported on this processor"));
5746 /* Itbl support may require additional care here. */
5750 /* Itbl support may require additional care here. */
5755 /* Itbl support may require additional care here. */
5767 /* Itbl support may require additional care here. */
5768 if (mask
== M_LWC1_AB
5769 || mask
== M_SWC1_AB
5770 || mask
== M_LDC1_AB
5771 || mask
== M_SDC1_AB
5780 if (offset_expr
.X_op
!= O_constant
5781 && offset_expr
.X_op
!= O_symbol
)
5783 as_bad (_("expression too complex"));
5784 offset_expr
.X_op
= O_constant
;
5787 /* A constant expression in PIC code can be handled just as it
5788 is in non PIC code. */
5789 if (offset_expr
.X_op
== O_constant
)
5791 if (HAVE_32BIT_ADDRESSES
5792 && !IS_SEXT_32BIT_NUM (offset_expr
.X_add_number
))
5793 as_bad (_("constant too large"));
5795 expr1
.X_add_number
= ((offset_expr
.X_add_number
+ 0x8000)
5796 & ~(bfd_vma
) 0xffff);
5797 load_register (tempreg
, &expr1
, HAVE_64BIT_ADDRESSES
);
5799 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5800 tempreg
, tempreg
, breg
);
5801 macro_build (&offset_expr
, s
, fmt
, treg
, BFD_RELOC_LO16
, tempreg
);
5803 else if (mips_pic
== NO_PIC
)
5805 /* If this is a reference to a GP relative symbol, and there
5806 is no base register, we want
5807 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
5808 Otherwise, if there is no base register, we want
5809 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
5810 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5811 If we have a constant, we need two instructions anyhow,
5812 so we always use the latter form.
5814 If we have a base register, and this is a reference to a
5815 GP relative symbol, we want
5816 addu $tempreg,$breg,$gp
5817 <op> $treg,<sym>($tempreg) (BFD_RELOC_GPREL16)
5819 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
5820 addu $tempreg,$tempreg,$breg
5821 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5822 With a constant we always use the latter case.
5824 With 64bit address space and no base register and $at usable,
5826 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5827 lui $at,<sym> (BFD_RELOC_HI16_S)
5828 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
5831 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5832 If we have a base register, we want
5833 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5834 lui $at,<sym> (BFD_RELOC_HI16_S)
5835 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
5839 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5841 Without $at we can't generate the optimal path for superscalar
5842 processors here since this would require two temporary registers.
5843 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5844 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
5846 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
5848 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5849 If we have a base register, we want
5850 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5851 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
5853 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
5855 daddu $tempreg,$tempreg,$breg
5856 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5858 For GP relative symbols in 64bit address space we can use
5859 the same sequence as in 32bit address space. */
5860 if (HAVE_64BIT_SYMBOLS
)
5862 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
5863 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
5865 relax_start (offset_expr
.X_add_symbol
);
5868 macro_build (&offset_expr
, s
, fmt
, treg
,
5869 BFD_RELOC_GPREL16
, mips_gp_register
);
5873 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5874 tempreg
, breg
, mips_gp_register
);
5875 macro_build (&offset_expr
, s
, fmt
, treg
,
5876 BFD_RELOC_GPREL16
, tempreg
);
5881 if (used_at
== 0 && !mips_opts
.noat
)
5883 macro_build (&offset_expr
, "lui", "t,u", tempreg
,
5884 BFD_RELOC_MIPS_HIGHEST
);
5885 macro_build (&offset_expr
, "lui", "t,u", AT
,
5887 macro_build (&offset_expr
, "daddiu", "t,r,j", tempreg
,
5888 tempreg
, BFD_RELOC_MIPS_HIGHER
);
5890 macro_build (NULL
, "daddu", "d,v,t", AT
, AT
, breg
);
5891 macro_build (NULL
, "dsll32", "d,w,<", tempreg
, tempreg
, 0);
5892 macro_build (NULL
, "daddu", "d,v,t", tempreg
, tempreg
, AT
);
5893 macro_build (&offset_expr
, s
, fmt
, treg
, BFD_RELOC_LO16
,
5899 macro_build (&offset_expr
, "lui", "t,u", tempreg
,
5900 BFD_RELOC_MIPS_HIGHEST
);
5901 macro_build (&offset_expr
, "daddiu", "t,r,j", tempreg
,
5902 tempreg
, BFD_RELOC_MIPS_HIGHER
);
5903 macro_build (NULL
, "dsll", "d,w,<", tempreg
, tempreg
, 16);
5904 macro_build (&offset_expr
, "daddiu", "t,r,j", tempreg
,
5905 tempreg
, BFD_RELOC_HI16_S
);
5906 macro_build (NULL
, "dsll", "d,w,<", tempreg
, tempreg
, 16);
5908 macro_build (NULL
, "daddu", "d,v,t",
5909 tempreg
, tempreg
, breg
);
5910 macro_build (&offset_expr
, s
, fmt
, treg
,
5911 BFD_RELOC_LO16
, tempreg
);
5914 if (mips_relax
.sequence
)
5921 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
5922 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
5924 relax_start (offset_expr
.X_add_symbol
);
5925 macro_build (&offset_expr
, s
, fmt
, treg
, BFD_RELOC_GPREL16
,
5929 macro_build_lui (&offset_expr
, tempreg
);
5930 macro_build (&offset_expr
, s
, fmt
, treg
,
5931 BFD_RELOC_LO16
, tempreg
);
5932 if (mips_relax
.sequence
)
5937 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
5938 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
5940 relax_start (offset_expr
.X_add_symbol
);
5941 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5942 tempreg
, breg
, mips_gp_register
);
5943 macro_build (&offset_expr
, s
, fmt
, treg
,
5944 BFD_RELOC_GPREL16
, tempreg
);
5947 macro_build_lui (&offset_expr
, tempreg
);
5948 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5949 tempreg
, tempreg
, breg
);
5950 macro_build (&offset_expr
, s
, fmt
, treg
,
5951 BFD_RELOC_LO16
, tempreg
);
5952 if (mips_relax
.sequence
)
5956 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
5958 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT16
;
5960 /* If this is a reference to an external symbol, we want
5961 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5963 <op> $treg,0($tempreg)
5965 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5967 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
5968 <op> $treg,0($tempreg)
5971 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
5972 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST)
5974 If there is a base register, we add it to $tempreg before
5975 the <op>. If there is a constant, we stick it in the
5976 <op> instruction. We don't handle constants larger than
5977 16 bits, because we have no way to load the upper 16 bits
5978 (actually, we could handle them for the subset of cases
5979 in which we are not using $at). */
5980 assert (offset_expr
.X_op
== O_symbol
);
5983 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
5984 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
5986 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5987 tempreg
, tempreg
, breg
);
5988 macro_build (&offset_expr
, s
, fmt
, treg
,
5989 BFD_RELOC_MIPS_GOT_OFST
, tempreg
);
5992 expr1
.X_add_number
= offset_expr
.X_add_number
;
5993 offset_expr
.X_add_number
= 0;
5994 if (expr1
.X_add_number
< -0x8000
5995 || expr1
.X_add_number
>= 0x8000)
5996 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
5997 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
5998 lw_reloc_type
, mips_gp_register
);
6000 relax_start (offset_expr
.X_add_symbol
);
6002 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j", tempreg
,
6003 tempreg
, BFD_RELOC_LO16
);
6006 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6007 tempreg
, tempreg
, breg
);
6008 macro_build (&expr1
, s
, fmt
, treg
, BFD_RELOC_LO16
, tempreg
);
6010 else if (mips_pic
== SVR4_PIC
&& ! HAVE_NEWABI
)
6014 /* If this is a reference to an external symbol, we want
6015 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
6016 addu $tempreg,$tempreg,$gp
6017 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
6018 <op> $treg,0($tempreg)
6020 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6022 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
6023 <op> $treg,0($tempreg)
6024 If there is a base register, we add it to $tempreg before
6025 the <op>. If there is a constant, we stick it in the
6026 <op> instruction. We don't handle constants larger than
6027 16 bits, because we have no way to load the upper 16 bits
6028 (actually, we could handle them for the subset of cases
6029 in which we are not using $at). */
6030 assert (offset_expr
.X_op
== O_symbol
);
6031 expr1
.X_add_number
= offset_expr
.X_add_number
;
6032 offset_expr
.X_add_number
= 0;
6033 if (expr1
.X_add_number
< -0x8000
6034 || expr1
.X_add_number
>= 0x8000)
6035 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6036 gpdelay
= reg_needs_delay (mips_gp_register
);
6037 relax_start (offset_expr
.X_add_symbol
);
6038 macro_build (&offset_expr
, "lui", "t,u", tempreg
,
6039 BFD_RELOC_MIPS_GOT_HI16
);
6040 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", tempreg
, tempreg
,
6042 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
6043 BFD_RELOC_MIPS_GOT_LO16
, tempreg
);
6046 macro_build (NULL
, "nop", "");
6047 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
6048 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
6050 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j", tempreg
,
6051 tempreg
, BFD_RELOC_LO16
);
6055 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6056 tempreg
, tempreg
, breg
);
6057 macro_build (&expr1
, s
, fmt
, treg
, BFD_RELOC_LO16
, tempreg
);
6059 else if (mips_pic
== SVR4_PIC
&& HAVE_NEWABI
)
6061 /* If this is a reference to an external symbol, we want
6062 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
6063 add $tempreg,$tempreg,$gp
6064 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
6065 <op> $treg,<ofst>($tempreg)
6066 Otherwise, for local symbols, we want:
6067 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
6068 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST) */
6069 assert (offset_expr
.X_op
== O_symbol
);
6070 expr1
.X_add_number
= offset_expr
.X_add_number
;
6071 offset_expr
.X_add_number
= 0;
6072 if (expr1
.X_add_number
< -0x8000
6073 || expr1
.X_add_number
>= 0x8000)
6074 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6075 relax_start (offset_expr
.X_add_symbol
);
6076 macro_build (&offset_expr
, "lui", "t,u", tempreg
,
6077 BFD_RELOC_MIPS_GOT_HI16
);
6078 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", tempreg
, tempreg
,
6080 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
6081 BFD_RELOC_MIPS_GOT_LO16
, tempreg
);
6083 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6084 tempreg
, tempreg
, breg
);
6085 macro_build (&expr1
, s
, fmt
, treg
, BFD_RELOC_LO16
, tempreg
);
6088 offset_expr
.X_add_number
= expr1
.X_add_number
;
6089 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
6090 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
6092 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6093 tempreg
, tempreg
, breg
);
6094 macro_build (&offset_expr
, s
, fmt
, treg
,
6095 BFD_RELOC_MIPS_GOT_OFST
, tempreg
);
6105 load_register (treg
, &imm_expr
, 0);
6109 load_register (treg
, &imm_expr
, 1);
6113 if (imm_expr
.X_op
== O_constant
)
6116 load_register (AT
, &imm_expr
, 0);
6117 macro_build (NULL
, "mtc1", "t,G", AT
, treg
);
6122 assert (offset_expr
.X_op
== O_symbol
6123 && strcmp (segment_name (S_GET_SEGMENT
6124 (offset_expr
.X_add_symbol
)),
6126 && offset_expr
.X_add_number
== 0);
6127 macro_build (&offset_expr
, "lwc1", "T,o(b)", treg
,
6128 BFD_RELOC_MIPS_LITERAL
, mips_gp_register
);
6133 /* Check if we have a constant in IMM_EXPR. If the GPRs are 64 bits
6134 wide, IMM_EXPR is the entire value. Otherwise IMM_EXPR is the high
6135 order 32 bits of the value and the low order 32 bits are either
6136 zero or in OFFSET_EXPR. */
6137 if (imm_expr
.X_op
== O_constant
|| imm_expr
.X_op
== O_big
)
6139 if (HAVE_64BIT_GPRS
)
6140 load_register (treg
, &imm_expr
, 1);
6145 if (target_big_endian
)
6157 load_register (hreg
, &imm_expr
, 0);
6160 if (offset_expr
.X_op
== O_absent
)
6161 move_register (lreg
, 0);
6164 assert (offset_expr
.X_op
== O_constant
);
6165 load_register (lreg
, &offset_expr
, 0);
6172 /* We know that sym is in the .rdata section. First we get the
6173 upper 16 bits of the address. */
6174 if (mips_pic
== NO_PIC
)
6176 macro_build_lui (&offset_expr
, AT
);
6179 else if (mips_pic
== SVR4_PIC
)
6181 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", AT
,
6182 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
6188 /* Now we load the register(s). */
6189 if (HAVE_64BIT_GPRS
)
6192 macro_build (&offset_expr
, "ld", "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
6197 macro_build (&offset_expr
, "lw", "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
6200 /* FIXME: How in the world do we deal with the possible
6202 offset_expr
.X_add_number
+= 4;
6203 macro_build (&offset_expr
, "lw", "t,o(b)",
6204 treg
+ 1, BFD_RELOC_LO16
, AT
);
6210 /* Check if we have a constant in IMM_EXPR. If the FPRs are 64 bits
6211 wide, IMM_EXPR is the entire value and the GPRs are known to be 64
6212 bits wide as well. Otherwise IMM_EXPR is the high order 32 bits of
6213 the value and the low order 32 bits are either zero or in
6215 if (imm_expr
.X_op
== O_constant
|| imm_expr
.X_op
== O_big
)
6218 load_register (AT
, &imm_expr
, HAVE_64BIT_FPRS
);
6219 if (HAVE_64BIT_FPRS
)
6221 assert (HAVE_64BIT_GPRS
);
6222 macro_build (NULL
, "dmtc1", "t,S", AT
, treg
);
6226 macro_build (NULL
, "mtc1", "t,G", AT
, treg
+ 1);
6227 if (offset_expr
.X_op
== O_absent
)
6228 macro_build (NULL
, "mtc1", "t,G", 0, treg
);
6231 assert (offset_expr
.X_op
== O_constant
);
6232 load_register (AT
, &offset_expr
, 0);
6233 macro_build (NULL
, "mtc1", "t,G", AT
, treg
);
6239 assert (offset_expr
.X_op
== O_symbol
6240 && offset_expr
.X_add_number
== 0);
6241 s
= segment_name (S_GET_SEGMENT (offset_expr
.X_add_symbol
));
6242 if (strcmp (s
, ".lit8") == 0)
6244 if (mips_opts
.isa
!= ISA_MIPS1
)
6246 macro_build (&offset_expr
, "ldc1", "T,o(b)", treg
,
6247 BFD_RELOC_MIPS_LITERAL
, mips_gp_register
);
6250 breg
= mips_gp_register
;
6251 r
= BFD_RELOC_MIPS_LITERAL
;
6256 assert (strcmp (s
, RDATA_SECTION_NAME
) == 0);
6258 if (mips_pic
== SVR4_PIC
)
6259 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", AT
,
6260 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
6263 /* FIXME: This won't work for a 64 bit address. */
6264 macro_build_lui (&offset_expr
, AT
);
6267 if (mips_opts
.isa
!= ISA_MIPS1
)
6269 macro_build (&offset_expr
, "ldc1", "T,o(b)",
6270 treg
, BFD_RELOC_LO16
, AT
);
6279 if (mips_opts
.arch
== CPU_R4650
)
6281 as_bad (_("opcode not supported on this processor"));
6284 /* Even on a big endian machine $fn comes before $fn+1. We have
6285 to adjust when loading from memory. */
6288 assert (mips_opts
.isa
== ISA_MIPS1
);
6289 macro_build (&offset_expr
, "lwc1", "T,o(b)",
6290 target_big_endian
? treg
+ 1 : treg
, r
, breg
);
6291 /* FIXME: A possible overflow which I don't know how to deal
6293 offset_expr
.X_add_number
+= 4;
6294 macro_build (&offset_expr
, "lwc1", "T,o(b)",
6295 target_big_endian
? treg
: treg
+ 1, r
, breg
);
6300 * The MIPS assembler seems to check for X_add_number not
6301 * being double aligned and generating:
6304 * addiu at,at,%lo(foo+1)
6307 * But, the resulting address is the same after relocation so why
6308 * generate the extra instruction?
6310 if (mips_opts
.arch
== CPU_R4650
)
6312 as_bad (_("opcode not supported on this processor"));
6315 /* Itbl support may require additional care here. */
6317 if (mips_opts
.isa
!= ISA_MIPS1
)
6328 if (mips_opts
.arch
== CPU_R4650
)
6330 as_bad (_("opcode not supported on this processor"));
6334 if (mips_opts
.isa
!= ISA_MIPS1
)
6342 /* Itbl support may require additional care here. */
6347 if (HAVE_64BIT_GPRS
)
6358 if (HAVE_64BIT_GPRS
)
6368 if (offset_expr
.X_op
!= O_symbol
6369 && offset_expr
.X_op
!= O_constant
)
6371 as_bad (_("expression too complex"));
6372 offset_expr
.X_op
= O_constant
;
6375 /* Even on a big endian machine $fn comes before $fn+1. We have
6376 to adjust when loading from memory. We set coproc if we must
6377 load $fn+1 first. */
6378 /* Itbl support may require additional care here. */
6379 if (! target_big_endian
)
6382 if (mips_pic
== NO_PIC
6383 || offset_expr
.X_op
== O_constant
)
6385 /* If this is a reference to a GP relative symbol, we want
6386 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
6387 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_GPREL16)
6388 If we have a base register, we use this
6390 <op> $treg,<sym>($at) (BFD_RELOC_GPREL16)
6391 <op> $treg+1,<sym>+4($at) (BFD_RELOC_GPREL16)
6392 If this is not a GP relative symbol, we want
6393 lui $at,<sym> (BFD_RELOC_HI16_S)
6394 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
6395 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
6396 If there is a base register, we add it to $at after the
6397 lui instruction. If there is a constant, we always use
6399 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
6400 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
6402 relax_start (offset_expr
.X_add_symbol
);
6405 tempreg
= mips_gp_register
;
6409 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6410 AT
, breg
, mips_gp_register
);
6415 /* Itbl support may require additional care here. */
6416 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
+ 1 : treg
,
6417 BFD_RELOC_GPREL16
, tempreg
);
6418 offset_expr
.X_add_number
+= 4;
6420 /* Set mips_optimize to 2 to avoid inserting an
6422 hold_mips_optimize
= mips_optimize
;
6424 /* Itbl support may require additional care here. */
6425 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
: treg
+ 1,
6426 BFD_RELOC_GPREL16
, tempreg
);
6427 mips_optimize
= hold_mips_optimize
;
6431 /* We just generated two relocs. When tc_gen_reloc
6432 handles this case, it will skip the first reloc and
6433 handle the second. The second reloc already has an
6434 extra addend of 4, which we added above. We must
6435 subtract it out, and then subtract another 4 to make
6436 the first reloc come out right. The second reloc
6437 will come out right because we are going to add 4 to
6438 offset_expr when we build its instruction below.
6440 If we have a symbol, then we don't want to include
6441 the offset, because it will wind up being included
6442 when we generate the reloc. */
6444 if (offset_expr
.X_op
== O_constant
)
6445 offset_expr
.X_add_number
-= 8;
6448 offset_expr
.X_add_number
= -4;
6449 offset_expr
.X_op
= O_constant
;
6453 macro_build_lui (&offset_expr
, AT
);
6455 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
6456 /* Itbl support may require additional care here. */
6457 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
+ 1 : treg
,
6458 BFD_RELOC_LO16
, AT
);
6459 /* FIXME: How do we handle overflow here? */
6460 offset_expr
.X_add_number
+= 4;
6461 /* Itbl support may require additional care here. */
6462 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
: treg
+ 1,
6463 BFD_RELOC_LO16
, AT
);
6464 if (mips_relax
.sequence
)
6467 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
6469 /* If this is a reference to an external symbol, we want
6470 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6475 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6477 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
6478 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
6479 If there is a base register we add it to $at before the
6480 lwc1 instructions. If there is a constant we include it
6481 in the lwc1 instructions. */
6483 expr1
.X_add_number
= offset_expr
.X_add_number
;
6484 if (expr1
.X_add_number
< -0x8000
6485 || expr1
.X_add_number
>= 0x8000 - 4)
6486 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6487 load_got_offset (AT
, &offset_expr
);
6490 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
6492 /* Set mips_optimize to 2 to avoid inserting an undesired
6494 hold_mips_optimize
= mips_optimize
;
6497 /* Itbl support may require additional care here. */
6498 relax_start (offset_expr
.X_add_symbol
);
6499 macro_build (&expr1
, s
, fmt
, coproc
? treg
+ 1 : treg
,
6500 BFD_RELOC_LO16
, AT
);
6501 expr1
.X_add_number
+= 4;
6502 macro_build (&expr1
, s
, fmt
, coproc
? treg
: treg
+ 1,
6503 BFD_RELOC_LO16
, AT
);
6505 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
+ 1 : treg
,
6506 BFD_RELOC_LO16
, AT
);
6507 offset_expr
.X_add_number
+= 4;
6508 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
: treg
+ 1,
6509 BFD_RELOC_LO16
, AT
);
6512 mips_optimize
= hold_mips_optimize
;
6514 else if (mips_pic
== SVR4_PIC
)
6518 /* If this is a reference to an external symbol, we want
6519 lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16)
6521 lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16)
6526 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6528 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
6529 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
6530 If there is a base register we add it to $at before the
6531 lwc1 instructions. If there is a constant we include it
6532 in the lwc1 instructions. */
6534 expr1
.X_add_number
= offset_expr
.X_add_number
;
6535 offset_expr
.X_add_number
= 0;
6536 if (expr1
.X_add_number
< -0x8000
6537 || expr1
.X_add_number
>= 0x8000 - 4)
6538 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6539 gpdelay
= reg_needs_delay (mips_gp_register
);
6540 relax_start (offset_expr
.X_add_symbol
);
6541 macro_build (&offset_expr
, "lui", "t,u",
6542 AT
, BFD_RELOC_MIPS_GOT_HI16
);
6543 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6544 AT
, AT
, mips_gp_register
);
6545 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
6546 AT
, BFD_RELOC_MIPS_GOT_LO16
, AT
);
6549 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
6550 /* Itbl support may require additional care here. */
6551 macro_build (&expr1
, s
, fmt
, coproc
? treg
+ 1 : treg
,
6552 BFD_RELOC_LO16
, AT
);
6553 expr1
.X_add_number
+= 4;
6555 /* Set mips_optimize to 2 to avoid inserting an undesired
6557 hold_mips_optimize
= mips_optimize
;
6559 /* Itbl support may require additional care here. */
6560 macro_build (&expr1
, s
, fmt
, coproc
? treg
: treg
+ 1,
6561 BFD_RELOC_LO16
, AT
);
6562 mips_optimize
= hold_mips_optimize
;
6563 expr1
.X_add_number
-= 4;
6566 offset_expr
.X_add_number
= expr1
.X_add_number
;
6568 macro_build (NULL
, "nop", "");
6569 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", AT
,
6570 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
6573 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
6574 /* Itbl support may require additional care here. */
6575 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
+ 1 : treg
,
6576 BFD_RELOC_LO16
, AT
);
6577 offset_expr
.X_add_number
+= 4;
6579 /* Set mips_optimize to 2 to avoid inserting an undesired
6581 hold_mips_optimize
= mips_optimize
;
6583 /* Itbl support may require additional care here. */
6584 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
: treg
+ 1,
6585 BFD_RELOC_LO16
, AT
);
6586 mips_optimize
= hold_mips_optimize
;
6600 assert (HAVE_32BIT_ADDRESSES
);
6601 macro_build (&offset_expr
, s
, "t,o(b)", treg
, BFD_RELOC_LO16
, breg
);
6602 offset_expr
.X_add_number
+= 4;
6603 macro_build (&offset_expr
, s
, "t,o(b)", treg
+ 1, BFD_RELOC_LO16
, breg
);
6606 /* New code added to support COPZ instructions.
6607 This code builds table entries out of the macros in mip_opcodes.
6608 R4000 uses interlocks to handle coproc delays.
6609 Other chips (like the R3000) require nops to be inserted for delays.
6611 FIXME: Currently, we require that the user handle delays.
6612 In order to fill delay slots for non-interlocked chips,
6613 we must have a way to specify delays based on the coprocessor.
6614 Eg. 4 cycles if load coproc reg from memory, 1 if in cache, etc.
6615 What are the side-effects of the cop instruction?
6616 What cache support might we have and what are its effects?
6617 Both coprocessor & memory require delays. how long???
6618 What registers are read/set/modified?
6620 If an itbl is provided to interpret cop instructions,
6621 this knowledge can be encoded in the itbl spec. */
6635 /* For now we just do C (same as Cz). The parameter will be
6636 stored in insn_opcode by mips_ip. */
6637 macro_build (NULL
, s
, "C", ip
->insn_opcode
);
6641 move_register (dreg
, sreg
);
6644 #ifdef LOSING_COMPILER
6646 /* Try and see if this is a new itbl instruction.
6647 This code builds table entries out of the macros in mip_opcodes.
6648 FIXME: For now we just assemble the expression and pass it's
6649 value along as a 32-bit immediate.
6650 We may want to have the assembler assemble this value,
6651 so that we gain the assembler's knowledge of delay slots,
6653 Would it be more efficient to use mask (id) here? */
6654 if (itbl_have_entries
6655 && (immed_expr
= itbl_assemble (ip
->insn_mo
->name
, "")))
6657 s
= ip
->insn_mo
->name
;
6659 coproc
= ITBL_DECODE_PNUM (immed_expr
);;
6660 macro_build (&immed_expr
, s
, "C");
6666 if (mips_opts
.noat
&& used_at
)
6667 as_bad (_("Macro used $at after \".set noat\""));
6671 macro2 (struct mips_cl_insn
*ip
)
6673 register int treg
, sreg
, dreg
, breg
;
6688 bfd_reloc_code_real_type r
;
6690 treg
= (ip
->insn_opcode
>> 16) & 0x1f;
6691 dreg
= (ip
->insn_opcode
>> 11) & 0x1f;
6692 sreg
= breg
= (ip
->insn_opcode
>> 21) & 0x1f;
6693 mask
= ip
->insn_mo
->mask
;
6695 expr1
.X_op
= O_constant
;
6696 expr1
.X_op_symbol
= NULL
;
6697 expr1
.X_add_symbol
= NULL
;
6698 expr1
.X_add_number
= 1;
6702 #endif /* LOSING_COMPILER */
6707 macro_build (NULL
, dbl
? "dmultu" : "multu", "s,t", sreg
, treg
);
6708 macro_build (NULL
, "mflo", "d", dreg
);
6714 /* The MIPS assembler some times generates shifts and adds. I'm
6715 not trying to be that fancy. GCC should do this for us
6718 load_register (AT
, &imm_expr
, dbl
);
6719 macro_build (NULL
, dbl
? "dmult" : "mult", "s,t", sreg
, AT
);
6720 macro_build (NULL
, "mflo", "d", dreg
);
6736 load_register (AT
, &imm_expr
, dbl
);
6737 macro_build (NULL
, dbl
? "dmult" : "mult", "s,t", sreg
, imm
? AT
: treg
);
6738 macro_build (NULL
, "mflo", "d", dreg
);
6739 macro_build (NULL
, dbl
? "dsra32" : "sra", "d,w,<", dreg
, dreg
, RA
);
6740 macro_build (NULL
, "mfhi", "d", AT
);
6742 macro_build (NULL
, "tne", "s,t,q", dreg
, AT
, 6);
6745 expr1
.X_add_number
= 8;
6746 macro_build (&expr1
, "beq", "s,t,p", dreg
, AT
);
6747 macro_build (NULL
, "nop", "", 0);
6748 macro_build (NULL
, "break", "c", 6);
6751 macro_build (NULL
, "mflo", "d", dreg
);
6767 load_register (AT
, &imm_expr
, dbl
);
6768 macro_build (NULL
, dbl
? "dmultu" : "multu", "s,t",
6769 sreg
, imm
? AT
: treg
);
6770 macro_build (NULL
, "mfhi", "d", AT
);
6771 macro_build (NULL
, "mflo", "d", dreg
);
6773 macro_build (NULL
, "tne", "s,t,q", AT
, 0, 6);
6776 expr1
.X_add_number
= 8;
6777 macro_build (&expr1
, "beq", "s,t,p", AT
, 0);
6778 macro_build (NULL
, "nop", "", 0);
6779 macro_build (NULL
, "break", "c", 6);
6785 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
6796 macro_build (NULL
, "dnegu", "d,w", tempreg
, treg
);
6797 macro_build (NULL
, "drorv", "d,t,s", dreg
, sreg
, tempreg
);
6801 macro_build (NULL
, "dsubu", "d,v,t", AT
, 0, treg
);
6802 macro_build (NULL
, "dsrlv", "d,t,s", AT
, sreg
, AT
);
6803 macro_build (NULL
, "dsllv", "d,t,s", dreg
, sreg
, treg
);
6804 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
6808 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
6819 macro_build (NULL
, "negu", "d,w", tempreg
, treg
);
6820 macro_build (NULL
, "rorv", "d,t,s", dreg
, sreg
, tempreg
);
6824 macro_build (NULL
, "subu", "d,v,t", AT
, 0, treg
);
6825 macro_build (NULL
, "srlv", "d,t,s", AT
, sreg
, AT
);
6826 macro_build (NULL
, "sllv", "d,t,s", dreg
, sreg
, treg
);
6827 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
6835 if (imm_expr
.X_op
!= O_constant
)
6836 as_bad (_("Improper rotate count"));
6837 rot
= imm_expr
.X_add_number
& 0x3f;
6838 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
6840 rot
= (64 - rot
) & 0x3f;
6842 macro_build (NULL
, "dror32", "d,w,<", dreg
, sreg
, rot
- 32);
6844 macro_build (NULL
, "dror", "d,w,<", dreg
, sreg
, rot
);
6849 macro_build (NULL
, "dsrl", "d,w,<", dreg
, sreg
, 0);
6852 l
= (rot
< 0x20) ? "dsll" : "dsll32";
6853 r
= ((0x40 - rot
) < 0x20) ? "dsrl" : "dsrl32";
6856 macro_build (NULL
, l
, "d,w,<", AT
, sreg
, rot
);
6857 macro_build (NULL
, r
, "d,w,<", dreg
, sreg
, (0x20 - rot
) & 0x1f);
6858 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
6866 if (imm_expr
.X_op
!= O_constant
)
6867 as_bad (_("Improper rotate count"));
6868 rot
= imm_expr
.X_add_number
& 0x1f;
6869 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
6871 macro_build (NULL
, "ror", "d,w,<", dreg
, sreg
, (32 - rot
) & 0x1f);
6876 macro_build (NULL
, "srl", "d,w,<", dreg
, sreg
, 0);
6880 macro_build (NULL
, "sll", "d,w,<", AT
, sreg
, rot
);
6881 macro_build (NULL
, "srl", "d,w,<", dreg
, sreg
, (0x20 - rot
) & 0x1f);
6882 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
6887 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
6889 macro_build (NULL
, "drorv", "d,t,s", dreg
, sreg
, treg
);
6893 macro_build (NULL
, "dsubu", "d,v,t", AT
, 0, treg
);
6894 macro_build (NULL
, "dsllv", "d,t,s", AT
, sreg
, AT
);
6895 macro_build (NULL
, "dsrlv", "d,t,s", dreg
, sreg
, treg
);
6896 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
6900 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
6902 macro_build (NULL
, "rorv", "d,t,s", dreg
, sreg
, treg
);
6906 macro_build (NULL
, "subu", "d,v,t", AT
, 0, treg
);
6907 macro_build (NULL
, "sllv", "d,t,s", AT
, sreg
, AT
);
6908 macro_build (NULL
, "srlv", "d,t,s", dreg
, sreg
, treg
);
6909 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
6917 if (imm_expr
.X_op
!= O_constant
)
6918 as_bad (_("Improper rotate count"));
6919 rot
= imm_expr
.X_add_number
& 0x3f;
6920 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
6923 macro_build (NULL
, "dror32", "d,w,<", dreg
, sreg
, rot
- 32);
6925 macro_build (NULL
, "dror", "d,w,<", dreg
, sreg
, rot
);
6930 macro_build (NULL
, "dsrl", "d,w,<", dreg
, sreg
, 0);
6933 r
= (rot
< 0x20) ? "dsrl" : "dsrl32";
6934 l
= ((0x40 - rot
) < 0x20) ? "dsll" : "dsll32";
6937 macro_build (NULL
, r
, "d,w,<", AT
, sreg
, rot
);
6938 macro_build (NULL
, l
, "d,w,<", dreg
, sreg
, (0x20 - rot
) & 0x1f);
6939 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
6947 if (imm_expr
.X_op
!= O_constant
)
6948 as_bad (_("Improper rotate count"));
6949 rot
= imm_expr
.X_add_number
& 0x1f;
6950 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
6952 macro_build (NULL
, "ror", "d,w,<", dreg
, sreg
, rot
);
6957 macro_build (NULL
, "srl", "d,w,<", dreg
, sreg
, 0);
6961 macro_build (NULL
, "srl", "d,w,<", AT
, sreg
, rot
);
6962 macro_build (NULL
, "sll", "d,w,<", dreg
, sreg
, (0x20 - rot
) & 0x1f);
6963 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
6968 if (mips_opts
.arch
== CPU_R4650
)
6970 as_bad (_("opcode not supported on this processor"));
6973 assert (mips_opts
.isa
== ISA_MIPS1
);
6974 /* Even on a big endian machine $fn comes before $fn+1. We have
6975 to adjust when storing to memory. */
6976 macro_build (&offset_expr
, "swc1", "T,o(b)",
6977 target_big_endian
? treg
+ 1 : treg
, BFD_RELOC_LO16
, breg
);
6978 offset_expr
.X_add_number
+= 4;
6979 macro_build (&offset_expr
, "swc1", "T,o(b)",
6980 target_big_endian
? treg
: treg
+ 1, BFD_RELOC_LO16
, breg
);
6985 macro_build (&expr1
, "sltiu", "t,r,j", dreg
, treg
, BFD_RELOC_LO16
);
6987 macro_build (&expr1
, "sltiu", "t,r,j", dreg
, sreg
, BFD_RELOC_LO16
);
6990 macro_build (NULL
, "xor", "d,v,t", dreg
, sreg
, treg
);
6991 macro_build (&expr1
, "sltiu", "t,r,j", dreg
, dreg
, BFD_RELOC_LO16
);
6996 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
6998 macro_build (&expr1
, "sltiu", "t,r,j", dreg
, sreg
, BFD_RELOC_LO16
);
7003 as_warn (_("Instruction %s: result is always false"),
7005 move_register (dreg
, 0);
7008 if (imm_expr
.X_op
== O_constant
7009 && imm_expr
.X_add_number
>= 0
7010 && imm_expr
.X_add_number
< 0x10000)
7012 macro_build (&imm_expr
, "xori", "t,r,i", dreg
, sreg
, BFD_RELOC_LO16
);
7014 else if (imm_expr
.X_op
== O_constant
7015 && imm_expr
.X_add_number
> -0x8000
7016 && imm_expr
.X_add_number
< 0)
7018 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
7019 macro_build (&imm_expr
, HAVE_32BIT_GPRS
? "addiu" : "daddiu",
7020 "t,r,j", dreg
, sreg
, BFD_RELOC_LO16
);
7024 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7025 macro_build (NULL
, "xor", "d,v,t", dreg
, sreg
, AT
);
7028 macro_build (&expr1
, "sltiu", "t,r,j", dreg
, dreg
, BFD_RELOC_LO16
);
7031 case M_SGE
: /* sreg >= treg <==> not (sreg < treg) */
7037 macro_build (NULL
, s
, "d,v,t", dreg
, sreg
, treg
);
7038 macro_build (&expr1
, "xori", "t,r,i", dreg
, dreg
, BFD_RELOC_LO16
);
7041 case M_SGE_I
: /* sreg >= I <==> not (sreg < I) */
7043 if (imm_expr
.X_op
== O_constant
7044 && imm_expr
.X_add_number
>= -0x8000
7045 && imm_expr
.X_add_number
< 0x8000)
7047 macro_build (&imm_expr
, mask
== M_SGE_I
? "slti" : "sltiu", "t,r,j",
7048 dreg
, sreg
, BFD_RELOC_LO16
);
7052 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7053 macro_build (NULL
, mask
== M_SGE_I
? "slt" : "sltu", "d,v,t",
7057 macro_build (&expr1
, "xori", "t,r,i", dreg
, dreg
, BFD_RELOC_LO16
);
7060 case M_SGT
: /* sreg > treg <==> treg < sreg */
7066 macro_build (NULL
, s
, "d,v,t", dreg
, treg
, sreg
);
7069 case M_SGT_I
: /* sreg > I <==> I < sreg */
7076 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7077 macro_build (NULL
, s
, "d,v,t", dreg
, AT
, sreg
);
7080 case M_SLE
: /* sreg <= treg <==> treg >= sreg <==> not (treg < sreg) */
7086 macro_build (NULL
, s
, "d,v,t", dreg
, treg
, sreg
);
7087 macro_build (&expr1
, "xori", "t,r,i", dreg
, dreg
, BFD_RELOC_LO16
);
7090 case M_SLE_I
: /* sreg <= I <==> I >= sreg <==> not (I < sreg) */
7097 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7098 macro_build (NULL
, s
, "d,v,t", dreg
, AT
, sreg
);
7099 macro_build (&expr1
, "xori", "t,r,i", dreg
, dreg
, BFD_RELOC_LO16
);
7103 if (imm_expr
.X_op
== O_constant
7104 && imm_expr
.X_add_number
>= -0x8000
7105 && imm_expr
.X_add_number
< 0x8000)
7107 macro_build (&imm_expr
, "slti", "t,r,j", dreg
, sreg
, BFD_RELOC_LO16
);
7111 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7112 macro_build (NULL
, "slt", "d,v,t", dreg
, sreg
, AT
);
7116 if (imm_expr
.X_op
== O_constant
7117 && imm_expr
.X_add_number
>= -0x8000
7118 && imm_expr
.X_add_number
< 0x8000)
7120 macro_build (&imm_expr
, "sltiu", "t,r,j", dreg
, sreg
,
7125 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7126 macro_build (NULL
, "sltu", "d,v,t", dreg
, sreg
, AT
);
7131 macro_build (NULL
, "sltu", "d,v,t", dreg
, 0, treg
);
7133 macro_build (NULL
, "sltu", "d,v,t", dreg
, 0, sreg
);
7136 macro_build (NULL
, "xor", "d,v,t", dreg
, sreg
, treg
);
7137 macro_build (NULL
, "sltu", "d,v,t", dreg
, 0, dreg
);
7142 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
7144 macro_build (NULL
, "sltu", "d,v,t", dreg
, 0, sreg
);
7149 as_warn (_("Instruction %s: result is always true"),
7151 macro_build (&expr1
, HAVE_32BIT_GPRS
? "addiu" : "daddiu", "t,r,j",
7152 dreg
, 0, BFD_RELOC_LO16
);
7155 if (imm_expr
.X_op
== O_constant
7156 && imm_expr
.X_add_number
>= 0
7157 && imm_expr
.X_add_number
< 0x10000)
7159 macro_build (&imm_expr
, "xori", "t,r,i", dreg
, sreg
, BFD_RELOC_LO16
);
7161 else if (imm_expr
.X_op
== O_constant
7162 && imm_expr
.X_add_number
> -0x8000
7163 && imm_expr
.X_add_number
< 0)
7165 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
7166 macro_build (&imm_expr
, HAVE_32BIT_GPRS
? "addiu" : "daddiu",
7167 "t,r,j", dreg
, sreg
, BFD_RELOC_LO16
);
7171 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7172 macro_build (NULL
, "xor", "d,v,t", dreg
, sreg
, AT
);
7175 macro_build (NULL
, "sltu", "d,v,t", dreg
, 0, dreg
);
7181 if (imm_expr
.X_op
== O_constant
7182 && imm_expr
.X_add_number
> -0x8000
7183 && imm_expr
.X_add_number
<= 0x8000)
7185 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
7186 macro_build (&imm_expr
, dbl
? "daddi" : "addi", "t,r,j",
7187 dreg
, sreg
, BFD_RELOC_LO16
);
7191 load_register (AT
, &imm_expr
, dbl
);
7192 macro_build (NULL
, dbl
? "dsub" : "sub", "d,v,t", dreg
, sreg
, AT
);
7198 if (imm_expr
.X_op
== O_constant
7199 && imm_expr
.X_add_number
> -0x8000
7200 && imm_expr
.X_add_number
<= 0x8000)
7202 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
7203 macro_build (&imm_expr
, dbl
? "daddiu" : "addiu", "t,r,j",
7204 dreg
, sreg
, BFD_RELOC_LO16
);
7208 load_register (AT
, &imm_expr
, dbl
);
7209 macro_build (NULL
, dbl
? "dsubu" : "subu", "d,v,t", dreg
, sreg
, AT
);
7231 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7232 macro_build (NULL
, s
, "s,t", sreg
, AT
);
7237 assert (mips_opts
.isa
== ISA_MIPS1
);
7239 sreg
= (ip
->insn_opcode
>> 11) & 0x1f; /* floating reg */
7240 dreg
= (ip
->insn_opcode
>> 06) & 0x1f; /* floating reg */
7243 * Is the double cfc1 instruction a bug in the mips assembler;
7244 * or is there a reason for it?
7247 macro_build (NULL
, "cfc1", "t,G", treg
, RA
);
7248 macro_build (NULL
, "cfc1", "t,G", treg
, RA
);
7249 macro_build (NULL
, "nop", "");
7250 expr1
.X_add_number
= 3;
7251 macro_build (&expr1
, "ori", "t,r,i", AT
, treg
, BFD_RELOC_LO16
);
7252 expr1
.X_add_number
= 2;
7253 macro_build (&expr1
, "xori", "t,r,i", AT
, AT
, BFD_RELOC_LO16
);
7254 macro_build (NULL
, "ctc1", "t,G", AT
, RA
);
7255 macro_build (NULL
, "nop", "");
7256 macro_build (NULL
, mask
== M_TRUNCWD
? "cvt.w.d" : "cvt.w.s", "D,S",
7258 macro_build (NULL
, "ctc1", "t,G", treg
, RA
);
7259 macro_build (NULL
, "nop", "");
7270 if (offset_expr
.X_add_number
>= 0x7fff)
7271 as_bad (_("operand overflow"));
7272 if (! target_big_endian
)
7273 ++offset_expr
.X_add_number
;
7274 macro_build (&offset_expr
, s
, "t,o(b)", AT
, BFD_RELOC_LO16
, breg
);
7275 if (! target_big_endian
)
7276 --offset_expr
.X_add_number
;
7278 ++offset_expr
.X_add_number
;
7279 macro_build (&offset_expr
, "lbu", "t,o(b)", treg
, BFD_RELOC_LO16
, breg
);
7280 macro_build (NULL
, "sll", "d,w,<", AT
, AT
, 8);
7281 macro_build (NULL
, "or", "d,v,t", treg
, treg
, AT
);
7294 if (offset_expr
.X_add_number
>= 0x8000 - off
)
7295 as_bad (_("operand overflow"));
7303 if (! target_big_endian
)
7304 offset_expr
.X_add_number
+= off
;
7305 macro_build (&offset_expr
, s
, "t,o(b)", tempreg
, BFD_RELOC_LO16
, breg
);
7306 if (! target_big_endian
)
7307 offset_expr
.X_add_number
-= off
;
7309 offset_expr
.X_add_number
+= off
;
7310 macro_build (&offset_expr
, s2
, "t,o(b)", tempreg
, BFD_RELOC_LO16
, breg
);
7312 /* If necessary, move the result in tempreg the final destination. */
7313 if (treg
== tempreg
)
7315 /* Protect second load's delay slot. */
7317 move_register (treg
, tempreg
);
7331 load_address (AT
, &offset_expr
, &used_at
);
7333 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, AT
, breg
);
7334 if (! target_big_endian
)
7335 expr1
.X_add_number
= off
;
7337 expr1
.X_add_number
= 0;
7338 macro_build (&expr1
, s
, "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
7339 if (! target_big_endian
)
7340 expr1
.X_add_number
= 0;
7342 expr1
.X_add_number
= off
;
7343 macro_build (&expr1
, s2
, "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
7349 load_address (AT
, &offset_expr
, &used_at
);
7351 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, AT
, breg
);
7352 if (target_big_endian
)
7353 expr1
.X_add_number
= 0;
7354 macro_build (&expr1
, mask
== M_ULH_A
? "lb" : "lbu", "t,o(b)",
7355 treg
, BFD_RELOC_LO16
, AT
);
7356 if (target_big_endian
)
7357 expr1
.X_add_number
= 1;
7359 expr1
.X_add_number
= 0;
7360 macro_build (&expr1
, "lbu", "t,o(b)", AT
, BFD_RELOC_LO16
, AT
);
7361 macro_build (NULL
, "sll", "d,w,<", treg
, treg
, 8);
7362 macro_build (NULL
, "or", "d,v,t", treg
, treg
, AT
);
7367 if (offset_expr
.X_add_number
>= 0x7fff)
7368 as_bad (_("operand overflow"));
7369 if (target_big_endian
)
7370 ++offset_expr
.X_add_number
;
7371 macro_build (&offset_expr
, "sb", "t,o(b)", treg
, BFD_RELOC_LO16
, breg
);
7372 macro_build (NULL
, "srl", "d,w,<", AT
, treg
, 8);
7373 if (target_big_endian
)
7374 --offset_expr
.X_add_number
;
7376 ++offset_expr
.X_add_number
;
7377 macro_build (&offset_expr
, "sb", "t,o(b)", AT
, BFD_RELOC_LO16
, breg
);
7390 if (offset_expr
.X_add_number
>= 0x8000 - off
)
7391 as_bad (_("operand overflow"));
7392 if (! target_big_endian
)
7393 offset_expr
.X_add_number
+= off
;
7394 macro_build (&offset_expr
, s
, "t,o(b)", treg
, BFD_RELOC_LO16
, breg
);
7395 if (! target_big_endian
)
7396 offset_expr
.X_add_number
-= off
;
7398 offset_expr
.X_add_number
+= off
;
7399 macro_build (&offset_expr
, s2
, "t,o(b)", treg
, BFD_RELOC_LO16
, breg
);
7413 load_address (AT
, &offset_expr
, &used_at
);
7415 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, AT
, breg
);
7416 if (! target_big_endian
)
7417 expr1
.X_add_number
= off
;
7419 expr1
.X_add_number
= 0;
7420 macro_build (&expr1
, s
, "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
7421 if (! target_big_endian
)
7422 expr1
.X_add_number
= 0;
7424 expr1
.X_add_number
= off
;
7425 macro_build (&expr1
, s2
, "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
7430 load_address (AT
, &offset_expr
, &used_at
);
7432 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, AT
, breg
);
7433 if (! target_big_endian
)
7434 expr1
.X_add_number
= 0;
7435 macro_build (&expr1
, "sb", "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
7436 macro_build (NULL
, "srl", "d,w,<", treg
, treg
, 8);
7437 if (! target_big_endian
)
7438 expr1
.X_add_number
= 1;
7440 expr1
.X_add_number
= 0;
7441 macro_build (&expr1
, "sb", "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
7442 if (! target_big_endian
)
7443 expr1
.X_add_number
= 0;
7445 expr1
.X_add_number
= 1;
7446 macro_build (&expr1
, "lbu", "t,o(b)", AT
, BFD_RELOC_LO16
, AT
);
7447 macro_build (NULL
, "sll", "d,w,<", treg
, treg
, 8);
7448 macro_build (NULL
, "or", "d,v,t", treg
, treg
, AT
);
7452 /* FIXME: Check if this is one of the itbl macros, since they
7453 are added dynamically. */
7454 as_bad (_("Macro %s not implemented yet"), ip
->insn_mo
->name
);
7457 if (mips_opts
.noat
&& used_at
)
7458 as_bad (_("Macro used $at after \".set noat\""));
7461 /* Implement macros in mips16 mode. */
7464 mips16_macro (struct mips_cl_insn
*ip
)
7467 int xreg
, yreg
, zreg
, tmp
;
7470 const char *s
, *s2
, *s3
;
7472 mask
= ip
->insn_mo
->mask
;
7474 xreg
= MIPS16_EXTRACT_OPERAND (RX
, *ip
);
7475 yreg
= MIPS16_EXTRACT_OPERAND (RY
, *ip
);
7476 zreg
= MIPS16_EXTRACT_OPERAND (RZ
, *ip
);
7478 expr1
.X_op
= O_constant
;
7479 expr1
.X_op_symbol
= NULL
;
7480 expr1
.X_add_symbol
= NULL
;
7481 expr1
.X_add_number
= 1;
7501 macro_build (NULL
, dbl
? "ddiv" : "div", "0,x,y", xreg
, yreg
);
7502 expr1
.X_add_number
= 2;
7503 macro_build (&expr1
, "bnez", "x,p", yreg
);
7504 macro_build (NULL
, "break", "6", 7);
7506 /* FIXME: The normal code checks for of -1 / -0x80000000 here,
7507 since that causes an overflow. We should do that as well,
7508 but I don't see how to do the comparisons without a temporary
7511 macro_build (NULL
, s
, "x", zreg
);
7531 macro_build (NULL
, s
, "0,x,y", xreg
, yreg
);
7532 expr1
.X_add_number
= 2;
7533 macro_build (&expr1
, "bnez", "x,p", yreg
);
7534 macro_build (NULL
, "break", "6", 7);
7536 macro_build (NULL
, s2
, "x", zreg
);
7542 macro_build (NULL
, dbl
? "dmultu" : "multu", "x,y", xreg
, yreg
);
7543 macro_build (NULL
, "mflo", "x", zreg
);
7551 if (imm_expr
.X_op
!= O_constant
)
7552 as_bad (_("Unsupported large constant"));
7553 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
7554 macro_build (&imm_expr
, dbl
? "daddiu" : "addiu", "y,x,4", yreg
, xreg
);
7558 if (imm_expr
.X_op
!= O_constant
)
7559 as_bad (_("Unsupported large constant"));
7560 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
7561 macro_build (&imm_expr
, "addiu", "x,k", xreg
);
7565 if (imm_expr
.X_op
!= O_constant
)
7566 as_bad (_("Unsupported large constant"));
7567 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
7568 macro_build (&imm_expr
, "daddiu", "y,j", yreg
);
7590 goto do_reverse_branch
;
7594 goto do_reverse_branch
;
7606 goto do_reverse_branch
;
7617 macro_build (NULL
, s
, "x,y", xreg
, yreg
);
7618 macro_build (&offset_expr
, s2
, "p");
7645 goto do_addone_branch_i
;
7650 goto do_addone_branch_i
;
7665 goto do_addone_branch_i
;
7672 if (imm_expr
.X_op
!= O_constant
)
7673 as_bad (_("Unsupported large constant"));
7674 ++imm_expr
.X_add_number
;
7677 macro_build (&imm_expr
, s
, s3
, xreg
);
7678 macro_build (&offset_expr
, s2
, "p");
7682 expr1
.X_add_number
= 0;
7683 macro_build (&expr1
, "slti", "x,8", yreg
);
7685 move_register (xreg
, yreg
);
7686 expr1
.X_add_number
= 2;
7687 macro_build (&expr1
, "bteqz", "p");
7688 macro_build (NULL
, "neg", "x,w", xreg
, xreg
);
7692 /* For consistency checking, verify that all bits are specified either
7693 by the match/mask part of the instruction definition, or by the
7696 validate_mips_insn (const struct mips_opcode
*opc
)
7698 const char *p
= opc
->args
;
7700 unsigned long used_bits
= opc
->mask
;
7702 if ((used_bits
& opc
->match
) != opc
->match
)
7704 as_bad (_("internal: bad mips opcode (mask error): %s %s"),
7705 opc
->name
, opc
->args
);
7708 #define USE_BITS(mask,shift) (used_bits |= ((mask) << (shift)))
7718 case 'A': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
7719 case 'B': USE_BITS (OP_MASK_INSMSB
, OP_SH_INSMSB
); break;
7720 case 'C': USE_BITS (OP_MASK_EXTMSBD
, OP_SH_EXTMSBD
); break;
7721 case 'D': USE_BITS (OP_MASK_RD
, OP_SH_RD
);
7722 USE_BITS (OP_MASK_SEL
, OP_SH_SEL
); break;
7723 case 'E': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
7724 case 'F': USE_BITS (OP_MASK_INSMSB
, OP_SH_INSMSB
); break;
7725 case 'G': USE_BITS (OP_MASK_EXTMSBD
, OP_SH_EXTMSBD
); break;
7726 case 'H': USE_BITS (OP_MASK_EXTMSBD
, OP_SH_EXTMSBD
); break;
7729 as_bad (_("internal: bad mips opcode (unknown extension operand type `+%c'): %s %s"),
7730 c
, opc
->name
, opc
->args
);
7734 case '<': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
7735 case '>': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
7737 case 'B': USE_BITS (OP_MASK_CODE20
, OP_SH_CODE20
); break;
7738 case 'C': USE_BITS (OP_MASK_COPZ
, OP_SH_COPZ
); break;
7739 case 'D': USE_BITS (OP_MASK_FD
, OP_SH_FD
); break;
7740 case 'E': USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
7742 case 'G': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
7743 case 'H': USE_BITS (OP_MASK_SEL
, OP_SH_SEL
); break;
7745 case 'J': USE_BITS (OP_MASK_CODE19
, OP_SH_CODE19
); break;
7746 case 'K': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
7748 case 'M': USE_BITS (OP_MASK_CCC
, OP_SH_CCC
); break;
7749 case 'N': USE_BITS (OP_MASK_BCC
, OP_SH_BCC
); break;
7750 case 'O': USE_BITS (OP_MASK_ALN
, OP_SH_ALN
); break;
7751 case 'Q': USE_BITS (OP_MASK_VSEL
, OP_SH_VSEL
);
7752 USE_BITS (OP_MASK_FT
, OP_SH_FT
); break;
7753 case 'R': USE_BITS (OP_MASK_FR
, OP_SH_FR
); break;
7754 case 'S': USE_BITS (OP_MASK_FS
, OP_SH_FS
); break;
7755 case 'T': USE_BITS (OP_MASK_FT
, OP_SH_FT
); break;
7756 case 'V': USE_BITS (OP_MASK_FS
, OP_SH_FS
); break;
7757 case 'W': USE_BITS (OP_MASK_FT
, OP_SH_FT
); break;
7758 case 'X': USE_BITS (OP_MASK_FD
, OP_SH_FD
); break;
7759 case 'Y': USE_BITS (OP_MASK_FS
, OP_SH_FS
); break;
7760 case 'Z': USE_BITS (OP_MASK_FT
, OP_SH_FT
); break;
7761 case 'a': USE_BITS (OP_MASK_TARGET
, OP_SH_TARGET
); break;
7762 case 'b': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
7763 case 'c': USE_BITS (OP_MASK_CODE
, OP_SH_CODE
); break;
7764 case 'd': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
7766 case 'h': USE_BITS (OP_MASK_PREFX
, OP_SH_PREFX
); break;
7767 case 'i': USE_BITS (OP_MASK_IMMEDIATE
, OP_SH_IMMEDIATE
); break;
7768 case 'j': USE_BITS (OP_MASK_DELTA
, OP_SH_DELTA
); break;
7769 case 'k': USE_BITS (OP_MASK_CACHE
, OP_SH_CACHE
); break;
7771 case 'o': USE_BITS (OP_MASK_DELTA
, OP_SH_DELTA
); break;
7772 case 'p': USE_BITS (OP_MASK_DELTA
, OP_SH_DELTA
); break;
7773 case 'q': USE_BITS (OP_MASK_CODE2
, OP_SH_CODE2
); break;
7774 case 'r': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
7775 case 's': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
7776 case 't': USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
7777 case 'u': USE_BITS (OP_MASK_IMMEDIATE
, OP_SH_IMMEDIATE
); break;
7778 case 'v': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
7779 case 'w': USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
7782 case 'P': USE_BITS (OP_MASK_PERFREG
, OP_SH_PERFREG
); break;
7783 case 'U': USE_BITS (OP_MASK_RD
, OP_SH_RD
);
7784 USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
7785 case 'e': USE_BITS (OP_MASK_VECBYTE
, OP_SH_VECBYTE
); break;
7786 case '%': USE_BITS (OP_MASK_VECALIGN
, OP_SH_VECALIGN
); break;
7790 as_bad (_("internal: bad mips opcode (unknown operand type `%c'): %s %s"),
7791 c
, opc
->name
, opc
->args
);
7795 if (used_bits
!= 0xffffffff)
7797 as_bad (_("internal: bad mips opcode (bits 0x%lx undefined): %s %s"),
7798 ~used_bits
& 0xffffffff, opc
->name
, opc
->args
);
7804 /* This routine assembles an instruction into its binary format. As a
7805 side effect, it sets one of the global variables imm_reloc or
7806 offset_reloc to the type of relocation to do if one of the operands
7807 is an address expression. */
7810 mips_ip (char *str
, struct mips_cl_insn
*ip
)
7815 struct mips_opcode
*insn
;
7818 unsigned int lastregno
= 0;
7819 unsigned int lastpos
= 0;
7820 unsigned int limlo
, limhi
;
7826 /* If the instruction contains a '.', we first try to match an instruction
7827 including the '.'. Then we try again without the '.'. */
7829 for (s
= str
; *s
!= '\0' && !ISSPACE (*s
); ++s
)
7832 /* If we stopped on whitespace, then replace the whitespace with null for
7833 the call to hash_find. Save the character we replaced just in case we
7834 have to re-parse the instruction. */
7841 insn
= (struct mips_opcode
*) hash_find (op_hash
, str
);
7843 /* If we didn't find the instruction in the opcode table, try again, but
7844 this time with just the instruction up to, but not including the
7848 /* Restore the character we overwrite above (if any). */
7852 /* Scan up to the first '.' or whitespace. */
7854 *s
!= '\0' && *s
!= '.' && !ISSPACE (*s
);
7858 /* If we did not find a '.', then we can quit now. */
7861 insn_error
= "unrecognized opcode";
7865 /* Lookup the instruction in the hash table. */
7867 if ((insn
= (struct mips_opcode
*) hash_find (op_hash
, str
)) == NULL
)
7869 insn_error
= "unrecognized opcode";
7879 assert (strcmp (insn
->name
, str
) == 0);
7881 if (OPCODE_IS_MEMBER (insn
,
7883 | (file_ase_mips16
? INSN_MIPS16
: 0)
7884 | (mips_opts
.ase_mdmx
? INSN_MDMX
: 0)
7885 | (mips_opts
.ase_mips3d
? INSN_MIPS3D
: 0)),
7891 if (insn
->pinfo
!= INSN_MACRO
)
7893 if (mips_opts
.arch
== CPU_R4650
&& (insn
->pinfo
& FP_D
) != 0)
7899 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
]
7900 && strcmp (insn
->name
, insn
[1].name
) == 0)
7909 static char buf
[100];
7911 _("opcode not supported on this processor: %s (%s)"),
7912 mips_cpu_info_from_arch (mips_opts
.arch
)->name
,
7913 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
7922 create_insn (ip
, insn
);
7924 for (args
= insn
->args
;; ++args
)
7928 s
+= strspn (s
, " \t");
7932 case '\0': /* end of args */
7945 INSERT_OPERAND (RS
, *ip
, lastregno
);
7949 INSERT_OPERAND (RT
, *ip
, lastregno
);
7953 INSERT_OPERAND (FT
, *ip
, lastregno
);
7957 INSERT_OPERAND (FS
, *ip
, lastregno
);
7963 /* Handle optional base register.
7964 Either the base register is omitted or
7965 we must have a left paren. */
7966 /* This is dependent on the next operand specifier
7967 is a base register specification. */
7968 assert (args
[1] == 'b' || args
[1] == '5'
7969 || args
[1] == '-' || args
[1] == '4');
7973 case ')': /* these must match exactly */
7980 case '+': /* Opcode extension character. */
7983 case 'A': /* ins/ext position, becomes LSB. */
7992 my_getExpression (&imm_expr
, s
);
7993 check_absolute_expr (ip
, &imm_expr
);
7994 if ((unsigned long) imm_expr
.X_add_number
< limlo
7995 || (unsigned long) imm_expr
.X_add_number
> limhi
)
7997 as_bad (_("Improper position (%lu)"),
7998 (unsigned long) imm_expr
.X_add_number
);
7999 imm_expr
.X_add_number
= limlo
;
8001 lastpos
= imm_expr
.X_add_number
;
8002 INSERT_OPERAND (SHAMT
, *ip
, imm_expr
.X_add_number
);
8003 imm_expr
.X_op
= O_absent
;
8007 case 'B': /* ins size, becomes MSB. */
8016 my_getExpression (&imm_expr
, s
);
8017 check_absolute_expr (ip
, &imm_expr
);
8018 /* Check for negative input so that small negative numbers
8019 will not succeed incorrectly. The checks against
8020 (pos+size) transitively check "size" itself,
8021 assuming that "pos" is reasonable. */
8022 if ((long) imm_expr
.X_add_number
< 0
8023 || ((unsigned long) imm_expr
.X_add_number
8025 || ((unsigned long) imm_expr
.X_add_number
8028 as_bad (_("Improper insert size (%lu, position %lu)"),
8029 (unsigned long) imm_expr
.X_add_number
,
8030 (unsigned long) lastpos
);
8031 imm_expr
.X_add_number
= limlo
- lastpos
;
8033 INSERT_OPERAND (INSMSB
, *ip
,
8034 lastpos
+ imm_expr
.X_add_number
- 1);
8035 imm_expr
.X_op
= O_absent
;
8039 case 'C': /* ext size, becomes MSBD. */
8052 my_getExpression (&imm_expr
, s
);
8053 check_absolute_expr (ip
, &imm_expr
);
8054 /* Check for negative input so that small negative numbers
8055 will not succeed incorrectly. The checks against
8056 (pos+size) transitively check "size" itself,
8057 assuming that "pos" is reasonable. */
8058 if ((long) imm_expr
.X_add_number
< 0
8059 || ((unsigned long) imm_expr
.X_add_number
8061 || ((unsigned long) imm_expr
.X_add_number
8064 as_bad (_("Improper extract size (%lu, position %lu)"),
8065 (unsigned long) imm_expr
.X_add_number
,
8066 (unsigned long) lastpos
);
8067 imm_expr
.X_add_number
= limlo
- lastpos
;
8069 INSERT_OPERAND (EXTMSBD
, *ip
, imm_expr
.X_add_number
- 1);
8070 imm_expr
.X_op
= O_absent
;
8075 /* +D is for disassembly only; never match. */
8079 /* "+I" is like "I", except that imm2_expr is used. */
8080 my_getExpression (&imm2_expr
, s
);
8081 if (imm2_expr
.X_op
!= O_big
8082 && imm2_expr
.X_op
!= O_constant
)
8083 insn_error
= _("absolute expression required");
8084 normalize_constant_expr (&imm2_expr
);
8089 as_bad (_("internal: bad mips opcode (unknown extension operand type `+%c'): %s %s"),
8090 *args
, insn
->name
, insn
->args
);
8091 /* Further processing is fruitless. */
8096 case '<': /* must be at least one digit */
8098 * According to the manual, if the shift amount is greater
8099 * than 31 or less than 0, then the shift amount should be
8100 * mod 32. In reality the mips assembler issues an error.
8101 * We issue a warning and mask out all but the low 5 bits.
8103 my_getExpression (&imm_expr
, s
);
8104 check_absolute_expr (ip
, &imm_expr
);
8105 if ((unsigned long) imm_expr
.X_add_number
> 31)
8106 as_warn (_("Improper shift amount (%lu)"),
8107 (unsigned long) imm_expr
.X_add_number
);
8108 INSERT_OPERAND (SHAMT
, *ip
, imm_expr
.X_add_number
);
8109 imm_expr
.X_op
= O_absent
;
8113 case '>': /* shift amount minus 32 */
8114 my_getExpression (&imm_expr
, s
);
8115 check_absolute_expr (ip
, &imm_expr
);
8116 if ((unsigned long) imm_expr
.X_add_number
< 32
8117 || (unsigned long) imm_expr
.X_add_number
> 63)
8119 INSERT_OPERAND (SHAMT
, *ip
, imm_expr
.X_add_number
- 32);
8120 imm_expr
.X_op
= O_absent
;
8124 case 'k': /* cache code */
8125 case 'h': /* prefx code */
8126 my_getExpression (&imm_expr
, s
);
8127 check_absolute_expr (ip
, &imm_expr
);
8128 if ((unsigned long) imm_expr
.X_add_number
> 31)
8129 as_warn (_("Invalid value for `%s' (%lu)"),
8131 (unsigned long) imm_expr
.X_add_number
);
8133 INSERT_OPERAND (CACHE
, *ip
, imm_expr
.X_add_number
);
8135 INSERT_OPERAND (PREFX
, *ip
, imm_expr
.X_add_number
);
8136 imm_expr
.X_op
= O_absent
;
8140 case 'c': /* break code */
8141 my_getExpression (&imm_expr
, s
);
8142 check_absolute_expr (ip
, &imm_expr
);
8143 if ((unsigned long) imm_expr
.X_add_number
> 1023)
8144 as_warn (_("Illegal break code (%lu)"),
8145 (unsigned long) imm_expr
.X_add_number
);
8146 INSERT_OPERAND (CODE
, *ip
, imm_expr
.X_add_number
);
8147 imm_expr
.X_op
= O_absent
;
8151 case 'q': /* lower break code */
8152 my_getExpression (&imm_expr
, s
);
8153 check_absolute_expr (ip
, &imm_expr
);
8154 if ((unsigned long) imm_expr
.X_add_number
> 1023)
8155 as_warn (_("Illegal lower break code (%lu)"),
8156 (unsigned long) imm_expr
.X_add_number
);
8157 INSERT_OPERAND (CODE2
, *ip
, imm_expr
.X_add_number
);
8158 imm_expr
.X_op
= O_absent
;
8162 case 'B': /* 20-bit syscall/break code. */
8163 my_getExpression (&imm_expr
, s
);
8164 check_absolute_expr (ip
, &imm_expr
);
8165 if ((unsigned long) imm_expr
.X_add_number
> OP_MASK_CODE20
)
8166 as_warn (_("Illegal 20-bit code (%lu)"),
8167 (unsigned long) imm_expr
.X_add_number
);
8168 INSERT_OPERAND (CODE20
, *ip
, imm_expr
.X_add_number
);
8169 imm_expr
.X_op
= O_absent
;
8173 case 'C': /* Coprocessor code */
8174 my_getExpression (&imm_expr
, s
);
8175 check_absolute_expr (ip
, &imm_expr
);
8176 if ((unsigned long) imm_expr
.X_add_number
>= (1 << 25))
8178 as_warn (_("Coproccesor code > 25 bits (%lu)"),
8179 (unsigned long) imm_expr
.X_add_number
);
8180 imm_expr
.X_add_number
&= ((1 << 25) - 1);
8182 ip
->insn_opcode
|= imm_expr
.X_add_number
;
8183 imm_expr
.X_op
= O_absent
;
8187 case 'J': /* 19-bit wait code. */
8188 my_getExpression (&imm_expr
, s
);
8189 check_absolute_expr (ip
, &imm_expr
);
8190 if ((unsigned long) imm_expr
.X_add_number
> OP_MASK_CODE19
)
8191 as_warn (_("Illegal 19-bit code (%lu)"),
8192 (unsigned long) imm_expr
.X_add_number
);
8193 INSERT_OPERAND (CODE19
, *ip
, imm_expr
.X_add_number
);
8194 imm_expr
.X_op
= O_absent
;
8198 case 'P': /* Performance register */
8199 my_getExpression (&imm_expr
, s
);
8200 check_absolute_expr (ip
, &imm_expr
);
8201 if (imm_expr
.X_add_number
!= 0 && imm_expr
.X_add_number
!= 1)
8202 as_warn (_("Invalid performance register (%lu)"),
8203 (unsigned long) imm_expr
.X_add_number
);
8204 INSERT_OPERAND (PERFREG
, *ip
, imm_expr
.X_add_number
);
8205 imm_expr
.X_op
= O_absent
;
8209 case 'b': /* base register */
8210 case 'd': /* destination register */
8211 case 's': /* source register */
8212 case 't': /* target register */
8213 case 'r': /* both target and source */
8214 case 'v': /* both dest and source */
8215 case 'w': /* both dest and target */
8216 case 'E': /* coprocessor target register */
8217 case 'G': /* coprocessor destination register */
8218 case 'K': /* 'rdhwr' destination register */
8219 case 'x': /* ignore register name */
8220 case 'z': /* must be zero register */
8221 case 'U': /* destination register (clo/clz). */
8236 while (ISDIGIT (*s
));
8238 as_bad (_("Invalid register number (%d)"), regno
);
8240 else if (*args
== 'E' || *args
== 'G' || *args
== 'K')
8244 if (s
[1] == 'r' && s
[2] == 'a')
8249 else if (s
[1] == 'f' && s
[2] == 'p')
8254 else if (s
[1] == 's' && s
[2] == 'p')
8259 else if (s
[1] == 'g' && s
[2] == 'p')
8264 else if (s
[1] == 'a' && s
[2] == 't')
8269 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '0')
8274 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '1')
8279 else if (s
[1] == 'z' && s
[2] == 'e' && s
[3] == 'r' && s
[4] == 'o')
8284 else if (itbl_have_entries
)
8289 p
= s
+ 1; /* advance past '$' */
8290 n
= itbl_get_field (&p
); /* n is name */
8292 /* See if this is a register defined in an
8294 if (itbl_get_reg_val (n
, &r
))
8296 /* Get_field advances to the start of
8297 the next field, so we need to back
8298 rack to the end of the last field. */
8302 s
= strchr (s
, '\0');
8316 as_warn (_("Used $at without \".set noat\""));
8322 if (c
== 'r' || c
== 'v' || c
== 'w')
8329 /* 'z' only matches $0. */
8330 if (c
== 'z' && regno
!= 0)
8333 /* Now that we have assembled one operand, we use the args string
8334 * to figure out where it goes in the instruction. */
8341 INSERT_OPERAND (RS
, *ip
, regno
);
8346 INSERT_OPERAND (RD
, *ip
, regno
);
8349 INSERT_OPERAND (RD
, *ip
, regno
);
8350 INSERT_OPERAND (RT
, *ip
, regno
);
8355 INSERT_OPERAND (RT
, *ip
, regno
);
8358 /* This case exists because on the r3000 trunc
8359 expands into a macro which requires a gp
8360 register. On the r6000 or r4000 it is
8361 assembled into a single instruction which
8362 ignores the register. Thus the insn version
8363 is MIPS_ISA2 and uses 'x', and the macro
8364 version is MIPS_ISA1 and uses 't'. */
8367 /* This case is for the div instruction, which
8368 acts differently if the destination argument
8369 is $0. This only matches $0, and is checked
8370 outside the switch. */
8373 /* Itbl operand; not yet implemented. FIXME ?? */
8375 /* What about all other operands like 'i', which
8376 can be specified in the opcode table? */
8386 INSERT_OPERAND (RS
, *ip
, lastregno
);
8389 INSERT_OPERAND (RT
, *ip
, lastregno
);
8394 case 'O': /* MDMX alignment immediate constant. */
8395 my_getExpression (&imm_expr
, s
);
8396 check_absolute_expr (ip
, &imm_expr
);
8397 if ((unsigned long) imm_expr
.X_add_number
> OP_MASK_ALN
)
8398 as_warn ("Improper align amount (%ld), using low bits",
8399 (long) imm_expr
.X_add_number
);
8400 INSERT_OPERAND (ALN
, *ip
, imm_expr
.X_add_number
);
8401 imm_expr
.X_op
= O_absent
;
8405 case 'Q': /* MDMX vector, element sel, or const. */
8408 /* MDMX Immediate. */
8409 my_getExpression (&imm_expr
, s
);
8410 check_absolute_expr (ip
, &imm_expr
);
8411 if ((unsigned long) imm_expr
.X_add_number
> OP_MASK_FT
)
8412 as_warn (_("Invalid MDMX Immediate (%ld)"),
8413 (long) imm_expr
.X_add_number
);
8414 INSERT_OPERAND (FT
, *ip
, imm_expr
.X_add_number
);
8415 if (ip
->insn_opcode
& (OP_MASK_VSEL
<< OP_SH_VSEL
))
8416 ip
->insn_opcode
|= MDMX_FMTSEL_IMM_QH
<< OP_SH_VSEL
;
8418 ip
->insn_opcode
|= MDMX_FMTSEL_IMM_OB
<< OP_SH_VSEL
;
8419 imm_expr
.X_op
= O_absent
;
8423 /* Not MDMX Immediate. Fall through. */
8424 case 'X': /* MDMX destination register. */
8425 case 'Y': /* MDMX source register. */
8426 case 'Z': /* MDMX target register. */
8428 case 'D': /* floating point destination register */
8429 case 'S': /* floating point source register */
8430 case 'T': /* floating point target register */
8431 case 'R': /* floating point source register */
8435 /* Accept $fN for FP and MDMX register numbers, and in
8436 addition accept $vN for MDMX register numbers. */
8437 if ((s
[0] == '$' && s
[1] == 'f' && ISDIGIT (s
[2]))
8438 || (is_mdmx
!= 0 && s
[0] == '$' && s
[1] == 'v'
8449 while (ISDIGIT (*s
));
8452 as_bad (_("Invalid float register number (%d)"), regno
);
8454 if ((regno
& 1) != 0
8456 && ! (strcmp (str
, "mtc1") == 0
8457 || strcmp (str
, "mfc1") == 0
8458 || strcmp (str
, "lwc1") == 0
8459 || strcmp (str
, "swc1") == 0
8460 || strcmp (str
, "l.s") == 0
8461 || strcmp (str
, "s.s") == 0))
8462 as_warn (_("Float register should be even, was %d"),
8470 if (c
== 'V' || c
== 'W')
8481 INSERT_OPERAND (FD
, *ip
, regno
);
8486 INSERT_OPERAND (FS
, *ip
, regno
);
8489 /* This is like 'Z', but also needs to fix the MDMX
8490 vector/scalar select bits. Note that the
8491 scalar immediate case is handled above. */
8494 int is_qh
= (ip
->insn_opcode
& (1 << OP_SH_VSEL
));
8495 int max_el
= (is_qh
? 3 : 7);
8497 my_getExpression(&imm_expr
, s
);
8498 check_absolute_expr (ip
, &imm_expr
);
8500 if (imm_expr
.X_add_number
> max_el
)
8501 as_bad(_("Bad element selector %ld"),
8502 (long) imm_expr
.X_add_number
);
8503 imm_expr
.X_add_number
&= max_el
;
8504 ip
->insn_opcode
|= (imm_expr
.X_add_number
8507 imm_expr
.X_op
= O_absent
;
8509 as_warn(_("Expecting ']' found '%s'"), s
);
8515 if (ip
->insn_opcode
& (OP_MASK_VSEL
<< OP_SH_VSEL
))
8516 ip
->insn_opcode
|= (MDMX_FMTSEL_VEC_QH
8519 ip
->insn_opcode
|= (MDMX_FMTSEL_VEC_OB
<<
8526 INSERT_OPERAND (FT
, *ip
, regno
);
8529 INSERT_OPERAND (FR
, *ip
, regno
);
8539 INSERT_OPERAND (FS
, *ip
, lastregno
);
8542 INSERT_OPERAND (FT
, *ip
, lastregno
);
8548 my_getExpression (&imm_expr
, s
);
8549 if (imm_expr
.X_op
!= O_big
8550 && imm_expr
.X_op
!= O_constant
)
8551 insn_error
= _("absolute expression required");
8552 normalize_constant_expr (&imm_expr
);
8557 my_getExpression (&offset_expr
, s
);
8558 *imm_reloc
= BFD_RELOC_32
;
8571 unsigned char temp
[8];
8573 unsigned int length
;
8578 /* These only appear as the last operand in an
8579 instruction, and every instruction that accepts
8580 them in any variant accepts them in all variants.
8581 This means we don't have to worry about backing out
8582 any changes if the instruction does not match.
8584 The difference between them is the size of the
8585 floating point constant and where it goes. For 'F'
8586 and 'L' the constant is 64 bits; for 'f' and 'l' it
8587 is 32 bits. Where the constant is placed is based
8588 on how the MIPS assembler does things:
8591 f -- immediate value
8594 The .lit4 and .lit8 sections are only used if
8595 permitted by the -G argument.
8597 The code below needs to know whether the target register
8598 is 32 or 64 bits wide. It relies on the fact 'f' and
8599 'F' are used with GPR-based instructions and 'l' and
8600 'L' are used with FPR-based instructions. */
8602 f64
= *args
== 'F' || *args
== 'L';
8603 using_gprs
= *args
== 'F' || *args
== 'f';
8605 save_in
= input_line_pointer
;
8606 input_line_pointer
= s
;
8607 err
= md_atof (f64
? 'd' : 'f', (char *) temp
, &len
);
8609 s
= input_line_pointer
;
8610 input_line_pointer
= save_in
;
8611 if (err
!= NULL
&& *err
!= '\0')
8613 as_bad (_("Bad floating point constant: %s"), err
);
8614 memset (temp
, '\0', sizeof temp
);
8615 length
= f64
? 8 : 4;
8618 assert (length
== (unsigned) (f64
? 8 : 4));
8622 && (g_switch_value
< 4
8623 || (temp
[0] == 0 && temp
[1] == 0)
8624 || (temp
[2] == 0 && temp
[3] == 0))))
8626 imm_expr
.X_op
= O_constant
;
8627 if (! target_big_endian
)
8628 imm_expr
.X_add_number
= bfd_getl32 (temp
);
8630 imm_expr
.X_add_number
= bfd_getb32 (temp
);
8633 && ! mips_disable_float_construction
8634 /* Constants can only be constructed in GPRs and
8635 copied to FPRs if the GPRs are at least as wide
8636 as the FPRs. Force the constant into memory if
8637 we are using 64-bit FPRs but the GPRs are only
8640 || ! (HAVE_64BIT_FPRS
&& HAVE_32BIT_GPRS
))
8641 && ((temp
[0] == 0 && temp
[1] == 0)
8642 || (temp
[2] == 0 && temp
[3] == 0))
8643 && ((temp
[4] == 0 && temp
[5] == 0)
8644 || (temp
[6] == 0 && temp
[7] == 0)))
8646 /* The value is simple enough to load with a couple of
8647 instructions. If using 32-bit registers, set
8648 imm_expr to the high order 32 bits and offset_expr to
8649 the low order 32 bits. Otherwise, set imm_expr to
8650 the entire 64 bit constant. */
8651 if (using_gprs
? HAVE_32BIT_GPRS
: HAVE_32BIT_FPRS
)
8653 imm_expr
.X_op
= O_constant
;
8654 offset_expr
.X_op
= O_constant
;
8655 if (! target_big_endian
)
8657 imm_expr
.X_add_number
= bfd_getl32 (temp
+ 4);
8658 offset_expr
.X_add_number
= bfd_getl32 (temp
);
8662 imm_expr
.X_add_number
= bfd_getb32 (temp
);
8663 offset_expr
.X_add_number
= bfd_getb32 (temp
+ 4);
8665 if (offset_expr
.X_add_number
== 0)
8666 offset_expr
.X_op
= O_absent
;
8668 else if (sizeof (imm_expr
.X_add_number
) > 4)
8670 imm_expr
.X_op
= O_constant
;
8671 if (! target_big_endian
)
8672 imm_expr
.X_add_number
= bfd_getl64 (temp
);
8674 imm_expr
.X_add_number
= bfd_getb64 (temp
);
8678 imm_expr
.X_op
= O_big
;
8679 imm_expr
.X_add_number
= 4;
8680 if (! target_big_endian
)
8682 generic_bignum
[0] = bfd_getl16 (temp
);
8683 generic_bignum
[1] = bfd_getl16 (temp
+ 2);
8684 generic_bignum
[2] = bfd_getl16 (temp
+ 4);
8685 generic_bignum
[3] = bfd_getl16 (temp
+ 6);
8689 generic_bignum
[0] = bfd_getb16 (temp
+ 6);
8690 generic_bignum
[1] = bfd_getb16 (temp
+ 4);
8691 generic_bignum
[2] = bfd_getb16 (temp
+ 2);
8692 generic_bignum
[3] = bfd_getb16 (temp
);
8698 const char *newname
;
8701 /* Switch to the right section. */
8703 subseg
= now_subseg
;
8706 default: /* unused default case avoids warnings. */
8708 newname
= RDATA_SECTION_NAME
;
8709 if (g_switch_value
>= 8)
8713 newname
= RDATA_SECTION_NAME
;
8716 assert (g_switch_value
>= 4);
8720 new_seg
= subseg_new (newname
, (subsegT
) 0);
8721 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
8722 bfd_set_section_flags (stdoutput
, new_seg
,
8727 frag_align (*args
== 'l' ? 2 : 3, 0, 0);
8728 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
8729 && strcmp (TARGET_OS
, "elf") != 0)
8730 record_alignment (new_seg
, 4);
8732 record_alignment (new_seg
, *args
== 'l' ? 2 : 3);
8734 as_bad (_("Can't use floating point insn in this section"));
8736 /* Set the argument to the current address in the
8738 offset_expr
.X_op
= O_symbol
;
8739 offset_expr
.X_add_symbol
=
8740 symbol_new ("L0\001", now_seg
,
8741 (valueT
) frag_now_fix (), frag_now
);
8742 offset_expr
.X_add_number
= 0;
8744 /* Put the floating point number into the section. */
8745 p
= frag_more ((int) length
);
8746 memcpy (p
, temp
, length
);
8748 /* Switch back to the original section. */
8749 subseg_set (seg
, subseg
);
8754 case 'i': /* 16 bit unsigned immediate */
8755 case 'j': /* 16 bit signed immediate */
8756 *imm_reloc
= BFD_RELOC_LO16
;
8757 if (my_getSmallExpression (&imm_expr
, imm_reloc
, s
) == 0)
8760 offsetT minval
, maxval
;
8762 more
= (insn
+ 1 < &mips_opcodes
[NUMOPCODES
]
8763 && strcmp (insn
->name
, insn
[1].name
) == 0);
8765 /* If the expression was written as an unsigned number,
8766 only treat it as signed if there are no more
8770 && sizeof (imm_expr
.X_add_number
) <= 4
8771 && imm_expr
.X_op
== O_constant
8772 && imm_expr
.X_add_number
< 0
8773 && imm_expr
.X_unsigned
8777 /* For compatibility with older assemblers, we accept
8778 0x8000-0xffff as signed 16-bit numbers when only
8779 signed numbers are allowed. */
8781 minval
= 0, maxval
= 0xffff;
8783 minval
= -0x8000, maxval
= 0x7fff;
8785 minval
= -0x8000, maxval
= 0xffff;
8787 if (imm_expr
.X_op
!= O_constant
8788 || imm_expr
.X_add_number
< minval
8789 || imm_expr
.X_add_number
> maxval
)
8793 if (imm_expr
.X_op
== O_constant
8794 || imm_expr
.X_op
== O_big
)
8795 as_bad (_("expression out of range"));
8801 case 'o': /* 16 bit offset */
8802 /* Check whether there is only a single bracketed expression
8803 left. If so, it must be the base register and the
8804 constant must be zero. */
8805 if (*s
== '(' && strchr (s
+ 1, '(') == 0)
8807 offset_expr
.X_op
= O_constant
;
8808 offset_expr
.X_add_number
= 0;
8812 /* If this value won't fit into a 16 bit offset, then go
8813 find a macro that will generate the 32 bit offset
8815 if (my_getSmallExpression (&offset_expr
, offset_reloc
, s
) == 0
8816 && (offset_expr
.X_op
!= O_constant
8817 || offset_expr
.X_add_number
>= 0x8000
8818 || offset_expr
.X_add_number
< -0x8000))
8824 case 'p': /* pc relative offset */
8825 *offset_reloc
= BFD_RELOC_16_PCREL_S2
;
8826 my_getExpression (&offset_expr
, s
);
8830 case 'u': /* upper 16 bits */
8831 if (my_getSmallExpression (&imm_expr
, imm_reloc
, s
) == 0
8832 && imm_expr
.X_op
== O_constant
8833 && (imm_expr
.X_add_number
< 0
8834 || imm_expr
.X_add_number
>= 0x10000))
8835 as_bad (_("lui expression not in range 0..65535"));
8839 case 'a': /* 26 bit address */
8840 my_getExpression (&offset_expr
, s
);
8842 *offset_reloc
= BFD_RELOC_MIPS_JMP
;
8845 case 'N': /* 3 bit branch condition code */
8846 case 'M': /* 3 bit compare condition code */
8847 if (strncmp (s
, "$fcc", 4) != 0)
8857 while (ISDIGIT (*s
));
8859 as_bad (_("Invalid condition code register $fcc%d"), regno
);
8860 if ((strcmp(str
+ strlen(str
) - 3, ".ps") == 0
8861 || strcmp(str
+ strlen(str
) - 5, "any2f") == 0
8862 || strcmp(str
+ strlen(str
) - 5, "any2t") == 0)
8863 && (regno
& 1) != 0)
8864 as_warn(_("Condition code register should be even for %s, was %d"),
8866 if ((strcmp(str
+ strlen(str
) - 5, "any4f") == 0
8867 || strcmp(str
+ strlen(str
) - 5, "any4t") == 0)
8868 && (regno
& 3) != 0)
8869 as_warn(_("Condition code register should be 0 or 4 for %s, was %d"),
8872 INSERT_OPERAND (BCC
, *ip
, regno
);
8874 INSERT_OPERAND (CCC
, *ip
, regno
);
8878 if (s
[0] == '0' && (s
[1] == 'x' || s
[1] == 'X'))
8889 while (ISDIGIT (*s
));
8892 c
= 8; /* Invalid sel value. */
8895 as_bad (_("invalid coprocessor sub-selection value (0-7)"));
8896 ip
->insn_opcode
|= c
;
8900 /* Must be at least one digit. */
8901 my_getExpression (&imm_expr
, s
);
8902 check_absolute_expr (ip
, &imm_expr
);
8904 if ((unsigned long) imm_expr
.X_add_number
8905 > (unsigned long) OP_MASK_VECBYTE
)
8907 as_bad (_("bad byte vector index (%ld)"),
8908 (long) imm_expr
.X_add_number
);
8909 imm_expr
.X_add_number
= 0;
8912 INSERT_OPERAND (VECBYTE
, *ip
, imm_expr
.X_add_number
);
8913 imm_expr
.X_op
= O_absent
;
8918 my_getExpression (&imm_expr
, s
);
8919 check_absolute_expr (ip
, &imm_expr
);
8921 if ((unsigned long) imm_expr
.X_add_number
8922 > (unsigned long) OP_MASK_VECALIGN
)
8924 as_bad (_("bad byte vector index (%ld)"),
8925 (long) imm_expr
.X_add_number
);
8926 imm_expr
.X_add_number
= 0;
8929 INSERT_OPERAND (VECALIGN
, *ip
, imm_expr
.X_add_number
);
8930 imm_expr
.X_op
= O_absent
;
8935 as_bad (_("bad char = '%c'\n"), *args
);
8940 /* Args don't match. */
8941 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
8942 !strcmp (insn
->name
, insn
[1].name
))
8946 insn_error
= _("illegal operands");
8951 insn_error
= _("illegal operands");
8956 /* This routine assembles an instruction into its binary format when
8957 assembling for the mips16. As a side effect, it sets one of the
8958 global variables imm_reloc or offset_reloc to the type of
8959 relocation to do if one of the operands is an address expression.
8960 It also sets mips16_small and mips16_ext if the user explicitly
8961 requested a small or extended instruction. */
8964 mips16_ip (char *str
, struct mips_cl_insn
*ip
)
8968 struct mips_opcode
*insn
;
8971 unsigned int lastregno
= 0;
8977 mips16_small
= FALSE
;
8980 for (s
= str
; ISLOWER (*s
); ++s
)
8992 if (s
[1] == 't' && s
[2] == ' ')
8995 mips16_small
= TRUE
;
8999 else if (s
[1] == 'e' && s
[2] == ' ')
9008 insn_error
= _("unknown opcode");
9012 if (mips_opts
.noautoextend
&& ! mips16_ext
)
9013 mips16_small
= TRUE
;
9015 if ((insn
= (struct mips_opcode
*) hash_find (mips16_op_hash
, str
)) == NULL
)
9017 insn_error
= _("unrecognized opcode");
9024 assert (strcmp (insn
->name
, str
) == 0);
9026 create_insn (ip
, insn
);
9027 imm_expr
.X_op
= O_absent
;
9028 imm_reloc
[0] = BFD_RELOC_UNUSED
;
9029 imm_reloc
[1] = BFD_RELOC_UNUSED
;
9030 imm_reloc
[2] = BFD_RELOC_UNUSED
;
9031 imm2_expr
.X_op
= O_absent
;
9032 offset_expr
.X_op
= O_absent
;
9033 offset_reloc
[0] = BFD_RELOC_UNUSED
;
9034 offset_reloc
[1] = BFD_RELOC_UNUSED
;
9035 offset_reloc
[2] = BFD_RELOC_UNUSED
;
9036 for (args
= insn
->args
; 1; ++args
)
9043 /* In this switch statement we call break if we did not find
9044 a match, continue if we did find a match, or return if we
9053 /* Stuff the immediate value in now, if we can. */
9054 if (imm_expr
.X_op
== O_constant
9055 && *imm_reloc
> BFD_RELOC_UNUSED
9056 && insn
->pinfo
!= INSN_MACRO
)
9060 switch (*offset_reloc
)
9062 case BFD_RELOC_MIPS16_HI16_S
:
9063 tmp
= (imm_expr
.X_add_number
+ 0x8000) >> 16;
9066 case BFD_RELOC_MIPS16_HI16
:
9067 tmp
= imm_expr
.X_add_number
>> 16;
9070 case BFD_RELOC_MIPS16_LO16
:
9071 tmp
= ((imm_expr
.X_add_number
+ 0x8000) & 0xffff)
9075 case BFD_RELOC_UNUSED
:
9076 tmp
= imm_expr
.X_add_number
;
9082 *offset_reloc
= BFD_RELOC_UNUSED
;
9084 mips16_immed (NULL
, 0, *imm_reloc
- BFD_RELOC_UNUSED
,
9085 tmp
, TRUE
, mips16_small
,
9086 mips16_ext
, &ip
->insn_opcode
,
9087 &ip
->use_extend
, &ip
->extend
);
9088 imm_expr
.X_op
= O_absent
;
9089 *imm_reloc
= BFD_RELOC_UNUSED
;
9103 MIPS16_INSERT_OPERAND (RX
, *ip
, lastregno
);
9106 MIPS16_INSERT_OPERAND (RY
, *ip
, lastregno
);
9122 MIPS16_INSERT_OPERAND (RX
, *ip
, lastregno
);
9124 MIPS16_INSERT_OPERAND (RY
, *ip
, lastregno
);
9151 while (ISDIGIT (*s
));
9154 as_bad (_("invalid register number (%d)"), regno
);
9160 if (s
[1] == 'r' && s
[2] == 'a')
9165 else if (s
[1] == 'f' && s
[2] == 'p')
9170 else if (s
[1] == 's' && s
[2] == 'p')
9175 else if (s
[1] == 'g' && s
[2] == 'p')
9180 else if (s
[1] == 'a' && s
[2] == 't')
9185 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '0')
9190 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '1')
9195 else if (s
[1] == 'z' && s
[2] == 'e' && s
[3] == 'r' && s
[4] == 'o')
9208 if (c
== 'v' || c
== 'w')
9210 regno
= mips16_to_32_reg_map
[lastregno
];
9224 regno
= mips32_to_16_reg_map
[regno
];
9229 regno
= ILLEGAL_REG
;
9234 regno
= ILLEGAL_REG
;
9239 regno
= ILLEGAL_REG
;
9244 if (regno
== AT
&& ! mips_opts
.noat
)
9245 as_warn (_("used $at without \".set noat\""));
9252 if (regno
== ILLEGAL_REG
)
9259 MIPS16_INSERT_OPERAND (RX
, *ip
, regno
);
9263 MIPS16_INSERT_OPERAND (RY
, *ip
, regno
);
9266 MIPS16_INSERT_OPERAND (RZ
, *ip
, regno
);
9269 MIPS16_INSERT_OPERAND (MOVE32Z
, *ip
, regno
);
9275 MIPS16_INSERT_OPERAND (REGR32
, *ip
, regno
);
9278 regno
= ((regno
& 7) << 2) | ((regno
& 0x18) >> 3);
9279 MIPS16_INSERT_OPERAND (REG32R
, *ip
, regno
);
9289 if (strncmp (s
, "$pc", 3) == 0)
9306 i
= my_getSmallExpression (&imm_expr
, imm_reloc
, s
);
9309 if (imm_expr
.X_op
!= O_constant
)
9312 ip
->use_extend
= TRUE
;
9317 /* We need to relax this instruction. */
9318 *offset_reloc
= *imm_reloc
;
9319 *imm_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
9324 *imm_reloc
= BFD_RELOC_UNUSED
;
9332 my_getExpression (&imm_expr
, s
);
9333 if (imm_expr
.X_op
== O_register
)
9335 /* What we thought was an expression turned out to
9338 if (s
[0] == '(' && args
[1] == '(')
9340 /* It looks like the expression was omitted
9341 before a register indirection, which means
9342 that the expression is implicitly zero. We
9343 still set up imm_expr, so that we handle
9344 explicit extensions correctly. */
9345 imm_expr
.X_op
= O_constant
;
9346 imm_expr
.X_add_number
= 0;
9347 *imm_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
9354 /* We need to relax this instruction. */
9355 *imm_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
9364 /* We use offset_reloc rather than imm_reloc for the PC
9365 relative operands. This lets macros with both
9366 immediate and address operands work correctly. */
9367 my_getExpression (&offset_expr
, s
);
9369 if (offset_expr
.X_op
== O_register
)
9372 /* We need to relax this instruction. */
9373 *offset_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
9377 case '6': /* break code */
9378 my_getExpression (&imm_expr
, s
);
9379 check_absolute_expr (ip
, &imm_expr
);
9380 if ((unsigned long) imm_expr
.X_add_number
> 63)
9381 as_warn (_("Invalid value for `%s' (%lu)"),
9383 (unsigned long) imm_expr
.X_add_number
);
9384 MIPS16_INSERT_OPERAND (IMM6
, *ip
, imm_expr
.X_add_number
);
9385 imm_expr
.X_op
= O_absent
;
9389 case 'a': /* 26 bit address */
9390 my_getExpression (&offset_expr
, s
);
9392 *offset_reloc
= BFD_RELOC_MIPS16_JMP
;
9393 ip
->insn_opcode
<<= 16;
9396 case 'l': /* register list for entry macro */
9397 case 'L': /* register list for exit macro */
9407 int freg
, reg1
, reg2
;
9409 while (*s
== ' ' || *s
== ',')
9413 as_bad (_("can't parse register list"));
9425 while (ISDIGIT (*s
))
9447 as_bad (_("invalid register list"));
9452 while (ISDIGIT (*s
))
9459 if (freg
&& reg1
== 0 && reg2
== 0 && c
== 'L')
9464 else if (freg
&& reg1
== 0 && reg2
== 1 && c
== 'L')
9469 else if (reg1
== 4 && reg2
>= 4 && reg2
<= 7 && c
!= 'L')
9470 mask
|= (reg2
- 3) << 3;
9471 else if (reg1
== 16 && reg2
>= 16 && reg2
<= 17)
9472 mask
|= (reg2
- 15) << 1;
9473 else if (reg1
== RA
&& reg2
== RA
)
9477 as_bad (_("invalid register list"));
9481 /* The mask is filled in in the opcode table for the
9482 benefit of the disassembler. We remove it before
9483 applying the actual mask. */
9484 ip
->insn_opcode
&= ~ ((7 << 3) << MIPS16OP_SH_IMM6
);
9485 ip
->insn_opcode
|= mask
<< MIPS16OP_SH_IMM6
;
9489 case 'e': /* extend code */
9490 my_getExpression (&imm_expr
, s
);
9491 check_absolute_expr (ip
, &imm_expr
);
9492 if ((unsigned long) imm_expr
.X_add_number
> 0x7ff)
9494 as_warn (_("Invalid value for `%s' (%lu)"),
9496 (unsigned long) imm_expr
.X_add_number
);
9497 imm_expr
.X_add_number
&= 0x7ff;
9499 ip
->insn_opcode
|= imm_expr
.X_add_number
;
9500 imm_expr
.X_op
= O_absent
;
9510 /* Args don't match. */
9511 if (insn
+ 1 < &mips16_opcodes
[bfd_mips16_num_opcodes
] &&
9512 strcmp (insn
->name
, insn
[1].name
) == 0)
9519 insn_error
= _("illegal operands");
9525 /* This structure holds information we know about a mips16 immediate
9528 struct mips16_immed_operand
9530 /* The type code used in the argument string in the opcode table. */
9532 /* The number of bits in the short form of the opcode. */
9534 /* The number of bits in the extended form of the opcode. */
9536 /* The amount by which the short form is shifted when it is used;
9537 for example, the sw instruction has a shift count of 2. */
9539 /* The amount by which the short form is shifted when it is stored
9540 into the instruction code. */
9542 /* Non-zero if the short form is unsigned. */
9544 /* Non-zero if the extended form is unsigned. */
9546 /* Non-zero if the value is PC relative. */
9550 /* The mips16 immediate operand types. */
9552 static const struct mips16_immed_operand mips16_immed_operands
[] =
9554 { '<', 3, 5, 0, MIPS16OP_SH_RZ
, 1, 1, 0 },
9555 { '>', 3, 5, 0, MIPS16OP_SH_RX
, 1, 1, 0 },
9556 { '[', 3, 6, 0, MIPS16OP_SH_RZ
, 1, 1, 0 },
9557 { ']', 3, 6, 0, MIPS16OP_SH_RX
, 1, 1, 0 },
9558 { '4', 4, 15, 0, MIPS16OP_SH_IMM4
, 0, 0, 0 },
9559 { '5', 5, 16, 0, MIPS16OP_SH_IMM5
, 1, 0, 0 },
9560 { 'H', 5, 16, 1, MIPS16OP_SH_IMM5
, 1, 0, 0 },
9561 { 'W', 5, 16, 2, MIPS16OP_SH_IMM5
, 1, 0, 0 },
9562 { 'D', 5, 16, 3, MIPS16OP_SH_IMM5
, 1, 0, 0 },
9563 { 'j', 5, 16, 0, MIPS16OP_SH_IMM5
, 0, 0, 0 },
9564 { '8', 8, 16, 0, MIPS16OP_SH_IMM8
, 1, 0, 0 },
9565 { 'V', 8, 16, 2, MIPS16OP_SH_IMM8
, 1, 0, 0 },
9566 { 'C', 8, 16, 3, MIPS16OP_SH_IMM8
, 1, 0, 0 },
9567 { 'U', 8, 16, 0, MIPS16OP_SH_IMM8
, 1, 1, 0 },
9568 { 'k', 8, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 0 },
9569 { 'K', 8, 16, 3, MIPS16OP_SH_IMM8
, 0, 0, 0 },
9570 { 'p', 8, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 1 },
9571 { 'q', 11, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 1 },
9572 { 'A', 8, 16, 2, MIPS16OP_SH_IMM8
, 1, 0, 1 },
9573 { 'B', 5, 16, 3, MIPS16OP_SH_IMM5
, 1, 0, 1 },
9574 { 'E', 5, 16, 2, MIPS16OP_SH_IMM5
, 1, 0, 1 }
9577 #define MIPS16_NUM_IMMED \
9578 (sizeof mips16_immed_operands / sizeof mips16_immed_operands[0])
9580 /* Handle a mips16 instruction with an immediate value. This or's the
9581 small immediate value into *INSN. It sets *USE_EXTEND to indicate
9582 whether an extended value is needed; if one is needed, it sets
9583 *EXTEND to the value. The argument type is TYPE. The value is VAL.
9584 If SMALL is true, an unextended opcode was explicitly requested.
9585 If EXT is true, an extended opcode was explicitly requested. If
9586 WARN is true, warn if EXT does not match reality. */
9589 mips16_immed (char *file
, unsigned int line
, int type
, offsetT val
,
9590 bfd_boolean warn
, bfd_boolean small
, bfd_boolean ext
,
9591 unsigned long *insn
, bfd_boolean
*use_extend
,
9592 unsigned short *extend
)
9594 register const struct mips16_immed_operand
*op
;
9595 int mintiny
, maxtiny
;
9596 bfd_boolean needext
;
9598 op
= mips16_immed_operands
;
9599 while (op
->type
!= type
)
9602 assert (op
< mips16_immed_operands
+ MIPS16_NUM_IMMED
);
9607 if (type
== '<' || type
== '>' || type
== '[' || type
== ']')
9610 maxtiny
= 1 << op
->nbits
;
9615 maxtiny
= (1 << op
->nbits
) - 1;
9620 mintiny
= - (1 << (op
->nbits
- 1));
9621 maxtiny
= (1 << (op
->nbits
- 1)) - 1;
9624 /* Branch offsets have an implicit 0 in the lowest bit. */
9625 if (type
== 'p' || type
== 'q')
9628 if ((val
& ((1 << op
->shift
) - 1)) != 0
9629 || val
< (mintiny
<< op
->shift
)
9630 || val
> (maxtiny
<< op
->shift
))
9635 if (warn
&& ext
&& ! needext
)
9636 as_warn_where (file
, line
,
9637 _("extended operand requested but not required"));
9638 if (small
&& needext
)
9639 as_bad_where (file
, line
, _("invalid unextended operand value"));
9641 if (small
|| (! ext
&& ! needext
))
9645 *use_extend
= FALSE
;
9646 insnval
= ((val
>> op
->shift
) & ((1 << op
->nbits
) - 1));
9647 insnval
<<= op
->op_shift
;
9652 long minext
, maxext
;
9658 maxext
= (1 << op
->extbits
) - 1;
9662 minext
= - (1 << (op
->extbits
- 1));
9663 maxext
= (1 << (op
->extbits
- 1)) - 1;
9665 if (val
< minext
|| val
> maxext
)
9666 as_bad_where (file
, line
,
9667 _("operand value out of range for instruction"));
9670 if (op
->extbits
== 16)
9672 extval
= ((val
>> 11) & 0x1f) | (val
& 0x7e0);
9675 else if (op
->extbits
== 15)
9677 extval
= ((val
>> 11) & 0xf) | (val
& 0x7f0);
9682 extval
= ((val
& 0x1f) << 6) | (val
& 0x20);
9686 *extend
= (unsigned short) extval
;
9691 struct percent_op_match
9694 bfd_reloc_code_real_type reloc
;
9697 static const struct percent_op_match mips_percent_op
[] =
9699 {"%lo", BFD_RELOC_LO16
},
9701 {"%call_hi", BFD_RELOC_MIPS_CALL_HI16
},
9702 {"%call_lo", BFD_RELOC_MIPS_CALL_LO16
},
9703 {"%call16", BFD_RELOC_MIPS_CALL16
},
9704 {"%got_disp", BFD_RELOC_MIPS_GOT_DISP
},
9705 {"%got_page", BFD_RELOC_MIPS_GOT_PAGE
},
9706 {"%got_ofst", BFD_RELOC_MIPS_GOT_OFST
},
9707 {"%got_hi", BFD_RELOC_MIPS_GOT_HI16
},
9708 {"%got_lo", BFD_RELOC_MIPS_GOT_LO16
},
9709 {"%got", BFD_RELOC_MIPS_GOT16
},
9710 {"%gp_rel", BFD_RELOC_GPREL16
},
9711 {"%half", BFD_RELOC_16
},
9712 {"%highest", BFD_RELOC_MIPS_HIGHEST
},
9713 {"%higher", BFD_RELOC_MIPS_HIGHER
},
9714 {"%neg", BFD_RELOC_MIPS_SUB
},
9715 {"%tlsgd", BFD_RELOC_MIPS_TLS_GD
},
9716 {"%tlsldm", BFD_RELOC_MIPS_TLS_LDM
},
9717 {"%dtprel_hi", BFD_RELOC_MIPS_TLS_DTPREL_HI16
},
9718 {"%dtprel_lo", BFD_RELOC_MIPS_TLS_DTPREL_LO16
},
9719 {"%tprel_hi", BFD_RELOC_MIPS_TLS_TPREL_HI16
},
9720 {"%tprel_lo", BFD_RELOC_MIPS_TLS_TPREL_LO16
},
9721 {"%gottprel", BFD_RELOC_MIPS_TLS_GOTTPREL
},
9723 {"%hi", BFD_RELOC_HI16_S
}
9726 static const struct percent_op_match mips16_percent_op
[] =
9728 {"%lo", BFD_RELOC_MIPS16_LO16
},
9729 {"%gprel", BFD_RELOC_MIPS16_GPREL
},
9730 {"%hi", BFD_RELOC_MIPS16_HI16_S
}
9734 /* Return true if *STR points to a relocation operator. When returning true,
9735 move *STR over the operator and store its relocation code in *RELOC.
9736 Leave both *STR and *RELOC alone when returning false. */
9739 parse_relocation (char **str
, bfd_reloc_code_real_type
*reloc
)
9741 const struct percent_op_match
*percent_op
;
9744 if (mips_opts
.mips16
)
9746 percent_op
= mips16_percent_op
;
9747 limit
= ARRAY_SIZE (mips16_percent_op
);
9751 percent_op
= mips_percent_op
;
9752 limit
= ARRAY_SIZE (mips_percent_op
);
9755 for (i
= 0; i
< limit
; i
++)
9756 if (strncasecmp (*str
, percent_op
[i
].str
, strlen (percent_op
[i
].str
)) == 0)
9758 int len
= strlen (percent_op
[i
].str
);
9760 if (!ISSPACE ((*str
)[len
]) && (*str
)[len
] != '(')
9763 *str
+= strlen (percent_op
[i
].str
);
9764 *reloc
= percent_op
[i
].reloc
;
9766 /* Check whether the output BFD supports this relocation.
9767 If not, issue an error and fall back on something safe. */
9768 if (!bfd_reloc_type_lookup (stdoutput
, percent_op
[i
].reloc
))
9770 as_bad ("relocation %s isn't supported by the current ABI",
9772 *reloc
= BFD_RELOC_UNUSED
;
9780 /* Parse string STR as a 16-bit relocatable operand. Store the
9781 expression in *EP and the relocations in the array starting
9782 at RELOC. Return the number of relocation operators used.
9784 On exit, EXPR_END points to the first character after the expression. */
9787 my_getSmallExpression (expressionS
*ep
, bfd_reloc_code_real_type
*reloc
,
9790 bfd_reloc_code_real_type reversed_reloc
[3];
9791 size_t reloc_index
, i
;
9792 int crux_depth
, str_depth
;
9795 /* Search for the start of the main expression, recoding relocations
9796 in REVERSED_RELOC. End the loop with CRUX pointing to the start
9797 of the main expression and with CRUX_DEPTH containing the number
9798 of open brackets at that point. */
9805 crux_depth
= str_depth
;
9807 /* Skip over whitespace and brackets, keeping count of the number
9809 while (*str
== ' ' || *str
== '\t' || *str
== '(')
9814 && reloc_index
< (HAVE_NEWABI
? 3 : 1)
9815 && parse_relocation (&str
, &reversed_reloc
[reloc_index
]));
9817 my_getExpression (ep
, crux
);
9820 /* Match every open bracket. */
9821 while (crux_depth
> 0 && (*str
== ')' || *str
== ' ' || *str
== '\t'))
9826 as_bad ("unclosed '('");
9830 if (reloc_index
!= 0)
9832 prev_reloc_op_frag
= frag_now
;
9833 for (i
= 0; i
< reloc_index
; i
++)
9834 reloc
[i
] = reversed_reloc
[reloc_index
- 1 - i
];
9841 my_getExpression (expressionS
*ep
, char *str
)
9846 save_in
= input_line_pointer
;
9847 input_line_pointer
= str
;
9849 expr_end
= input_line_pointer
;
9850 input_line_pointer
= save_in
;
9852 /* If we are in mips16 mode, and this is an expression based on `.',
9853 then we bump the value of the symbol by 1 since that is how other
9854 text symbols are handled. We don't bother to handle complex
9855 expressions, just `.' plus or minus a constant. */
9856 if (mips_opts
.mips16
9857 && ep
->X_op
== O_symbol
9858 && strcmp (S_GET_NAME (ep
->X_add_symbol
), FAKE_LABEL_NAME
) == 0
9859 && S_GET_SEGMENT (ep
->X_add_symbol
) == now_seg
9860 && symbol_get_frag (ep
->X_add_symbol
) == frag_now
9861 && symbol_constant_p (ep
->X_add_symbol
)
9862 && (val
= S_GET_VALUE (ep
->X_add_symbol
)) == frag_now_fix ())
9863 S_SET_VALUE (ep
->X_add_symbol
, val
+ 1);
9866 /* Turn a string in input_line_pointer into a floating point constant
9867 of type TYPE, and store the appropriate bytes in *LITP. The number
9868 of LITTLENUMS emitted is stored in *SIZEP. An error message is
9869 returned, or NULL on OK. */
9872 md_atof (int type
, char *litP
, int *sizeP
)
9875 LITTLENUM_TYPE words
[4];
9891 return _("bad call to md_atof");
9894 t
= atof_ieee (input_line_pointer
, type
, words
);
9896 input_line_pointer
= t
;
9900 if (! target_big_endian
)
9902 for (i
= prec
- 1; i
>= 0; i
--)
9904 md_number_to_chars (litP
, words
[i
], 2);
9910 for (i
= 0; i
< prec
; i
++)
9912 md_number_to_chars (litP
, words
[i
], 2);
9921 md_number_to_chars (char *buf
, valueT val
, int n
)
9923 if (target_big_endian
)
9924 number_to_chars_bigendian (buf
, val
, n
);
9926 number_to_chars_littleendian (buf
, val
, n
);
9930 static int support_64bit_objects(void)
9932 const char **list
, **l
;
9935 list
= bfd_target_list ();
9936 for (l
= list
; *l
!= NULL
; l
++)
9938 /* This is traditional mips */
9939 if (strcmp (*l
, "elf64-tradbigmips") == 0
9940 || strcmp (*l
, "elf64-tradlittlemips") == 0)
9942 if (strcmp (*l
, "elf64-bigmips") == 0
9943 || strcmp (*l
, "elf64-littlemips") == 0)
9950 #endif /* OBJ_ELF */
9952 const char *md_shortopts
= "O::g::G:";
9954 struct option md_longopts
[] =
9956 /* Options which specify architecture. */
9957 #define OPTION_ARCH_BASE (OPTION_MD_BASE)
9958 #define OPTION_MARCH (OPTION_ARCH_BASE + 0)
9959 {"march", required_argument
, NULL
, OPTION_MARCH
},
9960 #define OPTION_MTUNE (OPTION_ARCH_BASE + 1)
9961 {"mtune", required_argument
, NULL
, OPTION_MTUNE
},
9962 #define OPTION_MIPS1 (OPTION_ARCH_BASE + 2)
9963 {"mips0", no_argument
, NULL
, OPTION_MIPS1
},
9964 {"mips1", no_argument
, NULL
, OPTION_MIPS1
},
9965 #define OPTION_MIPS2 (OPTION_ARCH_BASE + 3)
9966 {"mips2", no_argument
, NULL
, OPTION_MIPS2
},
9967 #define OPTION_MIPS3 (OPTION_ARCH_BASE + 4)
9968 {"mips3", no_argument
, NULL
, OPTION_MIPS3
},
9969 #define OPTION_MIPS4 (OPTION_ARCH_BASE + 5)
9970 {"mips4", no_argument
, NULL
, OPTION_MIPS4
},
9971 #define OPTION_MIPS5 (OPTION_ARCH_BASE + 6)
9972 {"mips5", no_argument
, NULL
, OPTION_MIPS5
},
9973 #define OPTION_MIPS32 (OPTION_ARCH_BASE + 7)
9974 {"mips32", no_argument
, NULL
, OPTION_MIPS32
},
9975 #define OPTION_MIPS64 (OPTION_ARCH_BASE + 8)
9976 {"mips64", no_argument
, NULL
, OPTION_MIPS64
},
9977 #define OPTION_MIPS32R2 (OPTION_ARCH_BASE + 9)
9978 {"mips32r2", no_argument
, NULL
, OPTION_MIPS32R2
},
9979 #define OPTION_MIPS64R2 (OPTION_ARCH_BASE + 10)
9980 {"mips64r2", no_argument
, NULL
, OPTION_MIPS64R2
},
9982 /* Options which specify Application Specific Extensions (ASEs). */
9983 #define OPTION_ASE_BASE (OPTION_ARCH_BASE + 11)
9984 #define OPTION_MIPS16 (OPTION_ASE_BASE + 0)
9985 {"mips16", no_argument
, NULL
, OPTION_MIPS16
},
9986 #define OPTION_NO_MIPS16 (OPTION_ASE_BASE + 1)
9987 {"no-mips16", no_argument
, NULL
, OPTION_NO_MIPS16
},
9988 #define OPTION_MIPS3D (OPTION_ASE_BASE + 2)
9989 {"mips3d", no_argument
, NULL
, OPTION_MIPS3D
},
9990 #define OPTION_NO_MIPS3D (OPTION_ASE_BASE + 3)
9991 {"no-mips3d", no_argument
, NULL
, OPTION_NO_MIPS3D
},
9992 #define OPTION_MDMX (OPTION_ASE_BASE + 4)
9993 {"mdmx", no_argument
, NULL
, OPTION_MDMX
},
9994 #define OPTION_NO_MDMX (OPTION_ASE_BASE + 5)
9995 {"no-mdmx", no_argument
, NULL
, OPTION_NO_MDMX
},
9997 /* Old-style architecture options. Don't add more of these. */
9998 #define OPTION_COMPAT_ARCH_BASE (OPTION_ASE_BASE + 6)
9999 #define OPTION_M4650 (OPTION_COMPAT_ARCH_BASE + 0)
10000 {"m4650", no_argument
, NULL
, OPTION_M4650
},
10001 #define OPTION_NO_M4650 (OPTION_COMPAT_ARCH_BASE + 1)
10002 {"no-m4650", no_argument
, NULL
, OPTION_NO_M4650
},
10003 #define OPTION_M4010 (OPTION_COMPAT_ARCH_BASE + 2)
10004 {"m4010", no_argument
, NULL
, OPTION_M4010
},
10005 #define OPTION_NO_M4010 (OPTION_COMPAT_ARCH_BASE + 3)
10006 {"no-m4010", no_argument
, NULL
, OPTION_NO_M4010
},
10007 #define OPTION_M4100 (OPTION_COMPAT_ARCH_BASE + 4)
10008 {"m4100", no_argument
, NULL
, OPTION_M4100
},
10009 #define OPTION_NO_M4100 (OPTION_COMPAT_ARCH_BASE + 5)
10010 {"no-m4100", no_argument
, NULL
, OPTION_NO_M4100
},
10011 #define OPTION_M3900 (OPTION_COMPAT_ARCH_BASE + 6)
10012 {"m3900", no_argument
, NULL
, OPTION_M3900
},
10013 #define OPTION_NO_M3900 (OPTION_COMPAT_ARCH_BASE + 7)
10014 {"no-m3900", no_argument
, NULL
, OPTION_NO_M3900
},
10016 /* Options which enable bug fixes. */
10017 #define OPTION_FIX_BASE (OPTION_COMPAT_ARCH_BASE + 8)
10018 #define OPTION_M7000_HILO_FIX (OPTION_FIX_BASE + 0)
10019 {"mfix7000", no_argument
, NULL
, OPTION_M7000_HILO_FIX
},
10020 #define OPTION_MNO_7000_HILO_FIX (OPTION_FIX_BASE + 1)
10021 {"no-fix-7000", no_argument
, NULL
, OPTION_MNO_7000_HILO_FIX
},
10022 {"mno-fix7000", no_argument
, NULL
, OPTION_MNO_7000_HILO_FIX
},
10023 #define OPTION_FIX_VR4120 (OPTION_FIX_BASE + 2)
10024 #define OPTION_NO_FIX_VR4120 (OPTION_FIX_BASE + 3)
10025 {"mfix-vr4120", no_argument
, NULL
, OPTION_FIX_VR4120
},
10026 {"mno-fix-vr4120", no_argument
, NULL
, OPTION_NO_FIX_VR4120
},
10027 #define OPTION_FIX_VR4130 (OPTION_FIX_BASE + 4)
10028 #define OPTION_NO_FIX_VR4130 (OPTION_FIX_BASE + 5)
10029 {"mfix-vr4130", no_argument
, NULL
, OPTION_FIX_VR4130
},
10030 {"mno-fix-vr4130", no_argument
, NULL
, OPTION_NO_FIX_VR4130
},
10032 /* Miscellaneous options. */
10033 #define OPTION_MISC_BASE (OPTION_FIX_BASE + 6)
10034 #define OPTION_TRAP (OPTION_MISC_BASE + 0)
10035 {"trap", no_argument
, NULL
, OPTION_TRAP
},
10036 {"no-break", no_argument
, NULL
, OPTION_TRAP
},
10037 #define OPTION_BREAK (OPTION_MISC_BASE + 1)
10038 {"break", no_argument
, NULL
, OPTION_BREAK
},
10039 {"no-trap", no_argument
, NULL
, OPTION_BREAK
},
10040 #define OPTION_EB (OPTION_MISC_BASE + 2)
10041 {"EB", no_argument
, NULL
, OPTION_EB
},
10042 #define OPTION_EL (OPTION_MISC_BASE + 3)
10043 {"EL", no_argument
, NULL
, OPTION_EL
},
10044 #define OPTION_FP32 (OPTION_MISC_BASE + 4)
10045 {"mfp32", no_argument
, NULL
, OPTION_FP32
},
10046 #define OPTION_GP32 (OPTION_MISC_BASE + 5)
10047 {"mgp32", no_argument
, NULL
, OPTION_GP32
},
10048 #define OPTION_CONSTRUCT_FLOATS (OPTION_MISC_BASE + 6)
10049 {"construct-floats", no_argument
, NULL
, OPTION_CONSTRUCT_FLOATS
},
10050 #define OPTION_NO_CONSTRUCT_FLOATS (OPTION_MISC_BASE + 7)
10051 {"no-construct-floats", no_argument
, NULL
, OPTION_NO_CONSTRUCT_FLOATS
},
10052 #define OPTION_FP64 (OPTION_MISC_BASE + 8)
10053 {"mfp64", no_argument
, NULL
, OPTION_FP64
},
10054 #define OPTION_GP64 (OPTION_MISC_BASE + 9)
10055 {"mgp64", no_argument
, NULL
, OPTION_GP64
},
10056 #define OPTION_RELAX_BRANCH (OPTION_MISC_BASE + 10)
10057 #define OPTION_NO_RELAX_BRANCH (OPTION_MISC_BASE + 11)
10058 {"relax-branch", no_argument
, NULL
, OPTION_RELAX_BRANCH
},
10059 {"no-relax-branch", no_argument
, NULL
, OPTION_NO_RELAX_BRANCH
},
10060 #define OPTION_MSHARED (OPTION_MISC_BASE + 12)
10061 #define OPTION_MNO_SHARED (OPTION_MISC_BASE + 13)
10062 {"mshared", no_argument
, NULL
, OPTION_MSHARED
},
10063 {"mno-shared", no_argument
, NULL
, OPTION_MNO_SHARED
},
10064 #define OPTION_MSYM32 (OPTION_MISC_BASE + 14)
10065 #define OPTION_MNO_SYM32 (OPTION_MISC_BASE + 15)
10066 {"msym32", no_argument
, NULL
, OPTION_MSYM32
},
10067 {"mno-sym32", no_argument
, NULL
, OPTION_MNO_SYM32
},
10069 /* ELF-specific options. */
10071 #define OPTION_ELF_BASE (OPTION_MISC_BASE + 16)
10072 #define OPTION_CALL_SHARED (OPTION_ELF_BASE + 0)
10073 {"KPIC", no_argument
, NULL
, OPTION_CALL_SHARED
},
10074 {"call_shared", no_argument
, NULL
, OPTION_CALL_SHARED
},
10075 #define OPTION_NON_SHARED (OPTION_ELF_BASE + 1)
10076 {"non_shared", no_argument
, NULL
, OPTION_NON_SHARED
},
10077 #define OPTION_XGOT (OPTION_ELF_BASE + 2)
10078 {"xgot", no_argument
, NULL
, OPTION_XGOT
},
10079 #define OPTION_MABI (OPTION_ELF_BASE + 3)
10080 {"mabi", required_argument
, NULL
, OPTION_MABI
},
10081 #define OPTION_32 (OPTION_ELF_BASE + 4)
10082 {"32", no_argument
, NULL
, OPTION_32
},
10083 #define OPTION_N32 (OPTION_ELF_BASE + 5)
10084 {"n32", no_argument
, NULL
, OPTION_N32
},
10085 #define OPTION_64 (OPTION_ELF_BASE + 6)
10086 {"64", no_argument
, NULL
, OPTION_64
},
10087 #define OPTION_MDEBUG (OPTION_ELF_BASE + 7)
10088 {"mdebug", no_argument
, NULL
, OPTION_MDEBUG
},
10089 #define OPTION_NO_MDEBUG (OPTION_ELF_BASE + 8)
10090 {"no-mdebug", no_argument
, NULL
, OPTION_NO_MDEBUG
},
10091 #define OPTION_PDR (OPTION_ELF_BASE + 9)
10092 {"mpdr", no_argument
, NULL
, OPTION_PDR
},
10093 #define OPTION_NO_PDR (OPTION_ELF_BASE + 10)
10094 {"mno-pdr", no_argument
, NULL
, OPTION_NO_PDR
},
10095 #endif /* OBJ_ELF */
10097 {NULL
, no_argument
, NULL
, 0}
10099 size_t md_longopts_size
= sizeof (md_longopts
);
10101 /* Set STRING_PTR (either &mips_arch_string or &mips_tune_string) to
10102 NEW_VALUE. Warn if another value was already specified. Note:
10103 we have to defer parsing the -march and -mtune arguments in order
10104 to handle 'from-abi' correctly, since the ABI might be specified
10105 in a later argument. */
10108 mips_set_option_string (const char **string_ptr
, const char *new_value
)
10110 if (*string_ptr
!= 0 && strcasecmp (*string_ptr
, new_value
) != 0)
10111 as_warn (_("A different %s was already specified, is now %s"),
10112 string_ptr
== &mips_arch_string
? "-march" : "-mtune",
10115 *string_ptr
= new_value
;
10119 md_parse_option (int c
, char *arg
)
10123 case OPTION_CONSTRUCT_FLOATS
:
10124 mips_disable_float_construction
= 0;
10127 case OPTION_NO_CONSTRUCT_FLOATS
:
10128 mips_disable_float_construction
= 1;
10140 target_big_endian
= 1;
10144 target_big_endian
= 0;
10148 if (arg
&& arg
[1] == '0')
10158 mips_debug
= atoi (arg
);
10159 /* When the MIPS assembler sees -g or -g2, it does not do
10160 optimizations which limit full symbolic debugging. We take
10161 that to be equivalent to -O0. */
10162 if (mips_debug
== 2)
10167 file_mips_isa
= ISA_MIPS1
;
10171 file_mips_isa
= ISA_MIPS2
;
10175 file_mips_isa
= ISA_MIPS3
;
10179 file_mips_isa
= ISA_MIPS4
;
10183 file_mips_isa
= ISA_MIPS5
;
10186 case OPTION_MIPS32
:
10187 file_mips_isa
= ISA_MIPS32
;
10190 case OPTION_MIPS32R2
:
10191 file_mips_isa
= ISA_MIPS32R2
;
10194 case OPTION_MIPS64R2
:
10195 file_mips_isa
= ISA_MIPS64R2
;
10198 case OPTION_MIPS64
:
10199 file_mips_isa
= ISA_MIPS64
;
10203 mips_set_option_string (&mips_tune_string
, arg
);
10207 mips_set_option_string (&mips_arch_string
, arg
);
10211 mips_set_option_string (&mips_arch_string
, "4650");
10212 mips_set_option_string (&mips_tune_string
, "4650");
10215 case OPTION_NO_M4650
:
10219 mips_set_option_string (&mips_arch_string
, "4010");
10220 mips_set_option_string (&mips_tune_string
, "4010");
10223 case OPTION_NO_M4010
:
10227 mips_set_option_string (&mips_arch_string
, "4100");
10228 mips_set_option_string (&mips_tune_string
, "4100");
10231 case OPTION_NO_M4100
:
10235 mips_set_option_string (&mips_arch_string
, "3900");
10236 mips_set_option_string (&mips_tune_string
, "3900");
10239 case OPTION_NO_M3900
:
10243 mips_opts
.ase_mdmx
= 1;
10246 case OPTION_NO_MDMX
:
10247 mips_opts
.ase_mdmx
= 0;
10250 case OPTION_MIPS16
:
10251 mips_opts
.mips16
= 1;
10252 mips_no_prev_insn ();
10255 case OPTION_NO_MIPS16
:
10256 mips_opts
.mips16
= 0;
10257 mips_no_prev_insn ();
10260 case OPTION_MIPS3D
:
10261 mips_opts
.ase_mips3d
= 1;
10264 case OPTION_NO_MIPS3D
:
10265 mips_opts
.ase_mips3d
= 0;
10268 case OPTION_FIX_VR4120
:
10269 mips_fix_vr4120
= 1;
10272 case OPTION_NO_FIX_VR4120
:
10273 mips_fix_vr4120
= 0;
10276 case OPTION_FIX_VR4130
:
10277 mips_fix_vr4130
= 1;
10280 case OPTION_NO_FIX_VR4130
:
10281 mips_fix_vr4130
= 0;
10284 case OPTION_RELAX_BRANCH
:
10285 mips_relax_branch
= 1;
10288 case OPTION_NO_RELAX_BRANCH
:
10289 mips_relax_branch
= 0;
10292 case OPTION_MSHARED
:
10293 mips_in_shared
= TRUE
;
10296 case OPTION_MNO_SHARED
:
10297 mips_in_shared
= FALSE
;
10300 case OPTION_MSYM32
:
10301 mips_opts
.sym32
= TRUE
;
10304 case OPTION_MNO_SYM32
:
10305 mips_opts
.sym32
= FALSE
;
10309 /* When generating ELF code, we permit -KPIC and -call_shared to
10310 select SVR4_PIC, and -non_shared to select no PIC. This is
10311 intended to be compatible with Irix 5. */
10312 case OPTION_CALL_SHARED
:
10313 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
10315 as_bad (_("-call_shared is supported only for ELF format"));
10318 mips_pic
= SVR4_PIC
;
10319 mips_abicalls
= TRUE
;
10320 if (g_switch_seen
&& g_switch_value
!= 0)
10322 as_bad (_("-G may not be used with SVR4 PIC code"));
10325 g_switch_value
= 0;
10328 case OPTION_NON_SHARED
:
10329 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
10331 as_bad (_("-non_shared is supported only for ELF format"));
10335 mips_abicalls
= FALSE
;
10338 /* The -xgot option tells the assembler to use 32 offsets when
10339 accessing the got in SVR4_PIC mode. It is for Irix
10344 #endif /* OBJ_ELF */
10347 g_switch_value
= atoi (arg
);
10349 if (mips_pic
== SVR4_PIC
&& g_switch_value
!= 0)
10351 as_bad (_("-G may not be used with SVR4 PIC code"));
10357 /* The -32, -n32 and -64 options are shortcuts for -mabi=32, -mabi=n32
10360 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
10362 as_bad (_("-32 is supported for ELF format only"));
10365 mips_abi
= O32_ABI
;
10369 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
10371 as_bad (_("-n32 is supported for ELF format only"));
10374 mips_abi
= N32_ABI
;
10378 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
10380 as_bad (_("-64 is supported for ELF format only"));
10383 mips_abi
= N64_ABI
;
10384 if (! support_64bit_objects())
10385 as_fatal (_("No compiled in support for 64 bit object file format"));
10387 #endif /* OBJ_ELF */
10390 file_mips_gp32
= 1;
10394 file_mips_gp32
= 0;
10398 file_mips_fp32
= 1;
10402 file_mips_fp32
= 0;
10407 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
10409 as_bad (_("-mabi is supported for ELF format only"));
10412 if (strcmp (arg
, "32") == 0)
10413 mips_abi
= O32_ABI
;
10414 else if (strcmp (arg
, "o64") == 0)
10415 mips_abi
= O64_ABI
;
10416 else if (strcmp (arg
, "n32") == 0)
10417 mips_abi
= N32_ABI
;
10418 else if (strcmp (arg
, "64") == 0)
10420 mips_abi
= N64_ABI
;
10421 if (! support_64bit_objects())
10422 as_fatal (_("No compiled in support for 64 bit object file "
10425 else if (strcmp (arg
, "eabi") == 0)
10426 mips_abi
= EABI_ABI
;
10429 as_fatal (_("invalid abi -mabi=%s"), arg
);
10433 #endif /* OBJ_ELF */
10435 case OPTION_M7000_HILO_FIX
:
10436 mips_7000_hilo_fix
= TRUE
;
10439 case OPTION_MNO_7000_HILO_FIX
:
10440 mips_7000_hilo_fix
= FALSE
;
10444 case OPTION_MDEBUG
:
10445 mips_flag_mdebug
= TRUE
;
10448 case OPTION_NO_MDEBUG
:
10449 mips_flag_mdebug
= FALSE
;
10453 mips_flag_pdr
= TRUE
;
10456 case OPTION_NO_PDR
:
10457 mips_flag_pdr
= FALSE
;
10459 #endif /* OBJ_ELF */
10468 /* Set up globals to generate code for the ISA or processor
10469 described by INFO. */
10472 mips_set_architecture (const struct mips_cpu_info
*info
)
10476 file_mips_arch
= info
->cpu
;
10477 mips_opts
.arch
= info
->cpu
;
10478 mips_opts
.isa
= info
->isa
;
10483 /* Likewise for tuning. */
10486 mips_set_tune (const struct mips_cpu_info
*info
)
10489 mips_tune
= info
->cpu
;
10494 mips_after_parse_args (void)
10496 const struct mips_cpu_info
*arch_info
= 0;
10497 const struct mips_cpu_info
*tune_info
= 0;
10499 /* GP relative stuff not working for PE */
10500 if (strncmp (TARGET_OS
, "pe", 2) == 0)
10502 if (g_switch_seen
&& g_switch_value
!= 0)
10503 as_bad (_("-G not supported in this configuration."));
10504 g_switch_value
= 0;
10507 if (mips_abi
== NO_ABI
)
10508 mips_abi
= MIPS_DEFAULT_ABI
;
10510 /* The following code determines the architecture and register size.
10511 Similar code was added to GCC 3.3 (see override_options() in
10512 config/mips/mips.c). The GAS and GCC code should be kept in sync
10513 as much as possible. */
10515 if (mips_arch_string
!= 0)
10516 arch_info
= mips_parse_cpu ("-march", mips_arch_string
);
10518 if (file_mips_isa
!= ISA_UNKNOWN
)
10520 /* Handle -mipsN. At this point, file_mips_isa contains the
10521 ISA level specified by -mipsN, while arch_info->isa contains
10522 the -march selection (if any). */
10523 if (arch_info
!= 0)
10525 /* -march takes precedence over -mipsN, since it is more descriptive.
10526 There's no harm in specifying both as long as the ISA levels
10528 if (file_mips_isa
!= arch_info
->isa
)
10529 as_bad (_("-%s conflicts with the other architecture options, which imply -%s"),
10530 mips_cpu_info_from_isa (file_mips_isa
)->name
,
10531 mips_cpu_info_from_isa (arch_info
->isa
)->name
);
10534 arch_info
= mips_cpu_info_from_isa (file_mips_isa
);
10537 if (arch_info
== 0)
10538 arch_info
= mips_parse_cpu ("default CPU", MIPS_CPU_STRING_DEFAULT
);
10540 if (ABI_NEEDS_64BIT_REGS (mips_abi
) && !ISA_HAS_64BIT_REGS (arch_info
->isa
))
10541 as_bad ("-march=%s is not compatible with the selected ABI",
10544 mips_set_architecture (arch_info
);
10546 /* Optimize for file_mips_arch, unless -mtune selects a different processor. */
10547 if (mips_tune_string
!= 0)
10548 tune_info
= mips_parse_cpu ("-mtune", mips_tune_string
);
10550 if (tune_info
== 0)
10551 mips_set_tune (arch_info
);
10553 mips_set_tune (tune_info
);
10555 if (file_mips_gp32
>= 0)
10557 /* The user specified the size of the integer registers. Make sure
10558 it agrees with the ABI and ISA. */
10559 if (file_mips_gp32
== 0 && !ISA_HAS_64BIT_REGS (mips_opts
.isa
))
10560 as_bad (_("-mgp64 used with a 32-bit processor"));
10561 else if (file_mips_gp32
== 1 && ABI_NEEDS_64BIT_REGS (mips_abi
))
10562 as_bad (_("-mgp32 used with a 64-bit ABI"));
10563 else if (file_mips_gp32
== 0 && ABI_NEEDS_32BIT_REGS (mips_abi
))
10564 as_bad (_("-mgp64 used with a 32-bit ABI"));
10568 /* Infer the integer register size from the ABI and processor.
10569 Restrict ourselves to 32-bit registers if that's all the
10570 processor has, or if the ABI cannot handle 64-bit registers. */
10571 file_mips_gp32
= (ABI_NEEDS_32BIT_REGS (mips_abi
)
10572 || !ISA_HAS_64BIT_REGS (mips_opts
.isa
));
10575 /* ??? GAS treats single-float processors as though they had 64-bit
10576 float registers (although it complains when double-precision
10577 instructions are used). As things stand, saying they have 32-bit
10578 registers would lead to spurious "register must be even" messages.
10579 So here we assume float registers are always the same size as
10580 integer ones, unless the user says otherwise. */
10581 if (file_mips_fp32
< 0)
10582 file_mips_fp32
= file_mips_gp32
;
10584 /* End of GCC-shared inference code. */
10586 /* This flag is set when we have a 64-bit capable CPU but use only
10587 32-bit wide registers. Note that EABI does not use it. */
10588 if (ISA_HAS_64BIT_REGS (mips_opts
.isa
)
10589 && ((mips_abi
== NO_ABI
&& file_mips_gp32
== 1)
10590 || mips_abi
== O32_ABI
))
10591 mips_32bitmode
= 1;
10593 if (mips_opts
.isa
== ISA_MIPS1
&& mips_trap
)
10594 as_bad (_("trap exception not supported at ISA 1"));
10596 /* If the selected architecture includes support for ASEs, enable
10597 generation of code for them. */
10598 if (mips_opts
.mips16
== -1)
10599 mips_opts
.mips16
= (CPU_HAS_MIPS16 (file_mips_arch
)) ? 1 : 0;
10600 if (mips_opts
.ase_mips3d
== -1)
10601 mips_opts
.ase_mips3d
= (CPU_HAS_MIPS3D (file_mips_arch
)) ? 1 : 0;
10602 if (mips_opts
.ase_mdmx
== -1)
10603 mips_opts
.ase_mdmx
= (CPU_HAS_MDMX (file_mips_arch
)) ? 1 : 0;
10605 file_mips_isa
= mips_opts
.isa
;
10606 file_ase_mips16
= mips_opts
.mips16
;
10607 file_ase_mips3d
= mips_opts
.ase_mips3d
;
10608 file_ase_mdmx
= mips_opts
.ase_mdmx
;
10609 mips_opts
.gp32
= file_mips_gp32
;
10610 mips_opts
.fp32
= file_mips_fp32
;
10612 if (mips_flag_mdebug
< 0)
10614 #ifdef OBJ_MAYBE_ECOFF
10615 if (OUTPUT_FLAVOR
== bfd_target_ecoff_flavour
)
10616 mips_flag_mdebug
= 1;
10618 #endif /* OBJ_MAYBE_ECOFF */
10619 mips_flag_mdebug
= 0;
10624 mips_init_after_args (void)
10626 /* initialize opcodes */
10627 bfd_mips_num_opcodes
= bfd_mips_num_builtin_opcodes
;
10628 mips_opcodes
= (struct mips_opcode
*) mips_builtin_opcodes
;
10632 md_pcrel_from (fixS
*fixP
)
10634 valueT addr
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
10635 switch (fixP
->fx_r_type
)
10637 case BFD_RELOC_16_PCREL_S2
:
10638 case BFD_RELOC_MIPS_JMP
:
10639 /* Return the address of the delay slot. */
10646 /* This is called before the symbol table is processed. In order to
10647 work with gcc when using mips-tfile, we must keep all local labels.
10648 However, in other cases, we want to discard them. If we were
10649 called with -g, but we didn't see any debugging information, it may
10650 mean that gcc is smuggling debugging information through to
10651 mips-tfile, in which case we must generate all local labels. */
10654 mips_frob_file_before_adjust (void)
10656 #ifndef NO_ECOFF_DEBUGGING
10657 if (ECOFF_DEBUGGING
10659 && ! ecoff_debugging_seen
)
10660 flag_keep_locals
= 1;
10664 /* Sort any unmatched HI16 and GOT16 relocs so that they immediately precede
10665 the corresponding LO16 reloc. This is called before md_apply_fix3 and
10666 tc_gen_reloc. Unmatched relocs can only be generated by use of explicit
10667 relocation operators.
10669 For our purposes, a %lo() expression matches a %got() or %hi()
10672 (a) it refers to the same symbol; and
10673 (b) the offset applied in the %lo() expression is no lower than
10674 the offset applied in the %got() or %hi().
10676 (b) allows us to cope with code like:
10679 lh $4,%lo(foo+2)($4)
10681 ...which is legal on RELA targets, and has a well-defined behaviour
10682 if the user knows that adding 2 to "foo" will not induce a carry to
10685 When several %lo()s match a particular %got() or %hi(), we use the
10686 following rules to distinguish them:
10688 (1) %lo()s with smaller offsets are a better match than %lo()s with
10691 (2) %lo()s with no matching %got() or %hi() are better than those
10692 that already have a matching %got() or %hi().
10694 (3) later %lo()s are better than earlier %lo()s.
10696 These rules are applied in order.
10698 (1) means, among other things, that %lo()s with identical offsets are
10699 chosen if they exist.
10701 (2) means that we won't associate several high-part relocations with
10702 the same low-part relocation unless there's no alternative. Having
10703 several high parts for the same low part is a GNU extension; this rule
10704 allows careful users to avoid it.
10706 (3) is purely cosmetic. mips_hi_fixup_list is is in reverse order,
10707 with the last high-part relocation being at the front of the list.
10708 It therefore makes sense to choose the last matching low-part
10709 relocation, all other things being equal. It's also easier
10710 to code that way. */
10713 mips_frob_file (void)
10715 struct mips_hi_fixup
*l
;
10717 for (l
= mips_hi_fixup_list
; l
!= NULL
; l
= l
->next
)
10719 segment_info_type
*seginfo
;
10720 bfd_boolean matched_lo_p
;
10721 fixS
**hi_pos
, **lo_pos
, **pos
;
10723 assert (reloc_needs_lo_p (l
->fixp
->fx_r_type
));
10725 /* If a GOT16 relocation turns out to be against a global symbol,
10726 there isn't supposed to be a matching LO. */
10727 if (l
->fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT16
10728 && !pic_need_relax (l
->fixp
->fx_addsy
, l
->seg
))
10731 /* Check quickly whether the next fixup happens to be a matching %lo. */
10732 if (fixup_has_matching_lo_p (l
->fixp
))
10735 seginfo
= seg_info (l
->seg
);
10737 /* Set HI_POS to the position of this relocation in the chain.
10738 Set LO_POS to the position of the chosen low-part relocation.
10739 MATCHED_LO_P is true on entry to the loop if *POS is a low-part
10740 relocation that matches an immediately-preceding high-part
10744 matched_lo_p
= FALSE
;
10745 for (pos
= &seginfo
->fix_root
; *pos
!= NULL
; pos
= &(*pos
)->fx_next
)
10747 if (*pos
== l
->fixp
)
10750 if ((*pos
)->fx_r_type
== BFD_RELOC_LO16
10751 && (*pos
)->fx_addsy
== l
->fixp
->fx_addsy
10752 && (*pos
)->fx_offset
>= l
->fixp
->fx_offset
10754 || (*pos
)->fx_offset
< (*lo_pos
)->fx_offset
10756 && (*pos
)->fx_offset
== (*lo_pos
)->fx_offset
)))
10759 matched_lo_p
= (reloc_needs_lo_p ((*pos
)->fx_r_type
)
10760 && fixup_has_matching_lo_p (*pos
));
10763 /* If we found a match, remove the high-part relocation from its
10764 current position and insert it before the low-part relocation.
10765 Make the offsets match so that fixup_has_matching_lo_p()
10768 We don't warn about unmatched high-part relocations since some
10769 versions of gcc have been known to emit dead "lui ...%hi(...)"
10771 if (lo_pos
!= NULL
)
10773 l
->fixp
->fx_offset
= (*lo_pos
)->fx_offset
;
10774 if (l
->fixp
->fx_next
!= *lo_pos
)
10776 *hi_pos
= l
->fixp
->fx_next
;
10777 l
->fixp
->fx_next
= *lo_pos
;
10784 /* We may have combined relocations without symbols in the N32/N64 ABI.
10785 We have to prevent gas from dropping them. */
10788 mips_force_relocation (fixS
*fixp
)
10790 if (generic_force_reloc (fixp
))
10794 && S_GET_SEGMENT (fixp
->fx_addsy
) == bfd_abs_section_ptr
10795 && (fixp
->fx_r_type
== BFD_RELOC_MIPS_SUB
10796 || fixp
->fx_r_type
== BFD_RELOC_HI16_S
10797 || fixp
->fx_r_type
== BFD_RELOC_LO16
))
10803 /* This hook is called before a fix is simplified. We don't really
10804 decide whether to skip a fix here. Rather, we turn global symbols
10805 used as branch targets into local symbols, such that they undergo
10806 simplification. We can only do this if the symbol is defined and
10807 it is in the same section as the branch. If this doesn't hold, we
10808 emit a better error message than just saying the relocation is not
10809 valid for the selected object format.
10811 FIXP is the fix-up we're going to try to simplify, SEG is the
10812 segment in which the fix up occurs. The return value should be
10813 non-zero to indicate the fix-up is valid for further
10814 simplifications. */
10817 mips_validate_fix (struct fix
*fixP
, asection
*seg
)
10819 /* There's a lot of discussion on whether it should be possible to
10820 use R_MIPS_PC16 to represent branch relocations. The outcome
10821 seems to be that it can, but gas/bfd are very broken in creating
10822 RELA relocations for this, so for now we only accept branches to
10823 symbols in the same section. Anything else is of dubious value,
10824 since there's no guarantee that at link time the symbol would be
10825 in range. Even for branches to local symbols this is arguably
10826 wrong, since it we assume the symbol is not going to be
10827 overridden, which should be possible per ELF library semantics,
10828 but then, there isn't a dynamic relocation that could be used to
10829 this effect, and the target would likely be out of range as well.
10831 Unfortunately, it seems that there is too much code out there
10832 that relies on branches to symbols that are global to be resolved
10833 as if they were local, like the IRIX tools do, so we do it as
10834 well, but with a warning so that people are reminded to fix their
10835 code. If we ever get back to using R_MIPS_PC16 for branch
10836 targets, this entire block should go away (and probably the
10837 whole function). */
10839 if (fixP
->fx_r_type
== BFD_RELOC_16_PCREL_S2
10840 && ((OUTPUT_FLAVOR
== bfd_target_ecoff_flavour
10841 || OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
10842 || bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_16_PCREL_S2
) == NULL
)
10845 if (! S_IS_DEFINED (fixP
->fx_addsy
))
10847 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
10848 _("Cannot branch to undefined symbol."));
10849 /* Avoid any further errors about this fixup. */
10852 else if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
10854 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
10855 _("Cannot branch to symbol in another section."));
10858 else if (S_IS_EXTERNAL (fixP
->fx_addsy
))
10860 symbolS
*sym
= fixP
->fx_addsy
;
10862 if (mips_pic
== SVR4_PIC
)
10863 as_warn_where (fixP
->fx_file
, fixP
->fx_line
,
10864 _("Pretending global symbol used as branch target is local."));
10866 fixP
->fx_addsy
= symbol_create (S_GET_NAME (sym
),
10867 S_GET_SEGMENT (sym
),
10869 symbol_get_frag (sym
));
10870 copy_symbol_attributes (fixP
->fx_addsy
, sym
);
10871 S_CLEAR_EXTERNAL (fixP
->fx_addsy
);
10872 assert (symbol_resolved_p (sym
));
10873 symbol_mark_resolved (fixP
->fx_addsy
);
10880 /* Apply a fixup to the object file. */
10883 md_apply_fix3 (fixS
*fixP
, valueT
*valP
, segT seg ATTRIBUTE_UNUSED
)
10887 reloc_howto_type
*howto
;
10889 /* We ignore generic BFD relocations we don't know about. */
10890 howto
= bfd_reloc_type_lookup (stdoutput
, fixP
->fx_r_type
);
10894 assert (fixP
->fx_size
== 4
10895 || fixP
->fx_r_type
== BFD_RELOC_16
10896 || fixP
->fx_r_type
== BFD_RELOC_64
10897 || fixP
->fx_r_type
== BFD_RELOC_CTOR
10898 || fixP
->fx_r_type
== BFD_RELOC_MIPS_SUB
10899 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
10900 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
);
10902 buf
= (bfd_byte
*) (fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
);
10904 assert (! fixP
->fx_pcrel
);
10906 /* Don't treat parts of a composite relocation as done. There are two
10909 (1) The second and third parts will be against 0 (RSS_UNDEF) but
10910 should nevertheless be emitted if the first part is.
10912 (2) In normal usage, composite relocations are never assembly-time
10913 constants. The easiest way of dealing with the pathological
10914 exceptions is to generate a relocation against STN_UNDEF and
10915 leave everything up to the linker. */
10916 if (fixP
->fx_addsy
== NULL
&& fixP
->fx_tcbit
== 0)
10919 switch (fixP
->fx_r_type
)
10921 case BFD_RELOC_MIPS_TLS_GD
:
10922 case BFD_RELOC_MIPS_TLS_LDM
:
10923 case BFD_RELOC_MIPS_TLS_DTPREL_HI16
:
10924 case BFD_RELOC_MIPS_TLS_DTPREL_LO16
:
10925 case BFD_RELOC_MIPS_TLS_GOTTPREL
:
10926 case BFD_RELOC_MIPS_TLS_TPREL_HI16
:
10927 case BFD_RELOC_MIPS_TLS_TPREL_LO16
:
10928 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
10931 case BFD_RELOC_MIPS_JMP
:
10932 case BFD_RELOC_MIPS_SHIFT5
:
10933 case BFD_RELOC_MIPS_SHIFT6
:
10934 case BFD_RELOC_MIPS_GOT_DISP
:
10935 case BFD_RELOC_MIPS_GOT_PAGE
:
10936 case BFD_RELOC_MIPS_GOT_OFST
:
10937 case BFD_RELOC_MIPS_SUB
:
10938 case BFD_RELOC_MIPS_INSERT_A
:
10939 case BFD_RELOC_MIPS_INSERT_B
:
10940 case BFD_RELOC_MIPS_DELETE
:
10941 case BFD_RELOC_MIPS_HIGHEST
:
10942 case BFD_RELOC_MIPS_HIGHER
:
10943 case BFD_RELOC_MIPS_SCN_DISP
:
10944 case BFD_RELOC_MIPS_REL16
:
10945 case BFD_RELOC_MIPS_RELGOT
:
10946 case BFD_RELOC_MIPS_JALR
:
10947 case BFD_RELOC_HI16
:
10948 case BFD_RELOC_HI16_S
:
10949 case BFD_RELOC_GPREL16
:
10950 case BFD_RELOC_MIPS_LITERAL
:
10951 case BFD_RELOC_MIPS_CALL16
:
10952 case BFD_RELOC_MIPS_GOT16
:
10953 case BFD_RELOC_GPREL32
:
10954 case BFD_RELOC_MIPS_GOT_HI16
:
10955 case BFD_RELOC_MIPS_GOT_LO16
:
10956 case BFD_RELOC_MIPS_CALL_HI16
:
10957 case BFD_RELOC_MIPS_CALL_LO16
:
10958 case BFD_RELOC_MIPS16_GPREL
:
10959 case BFD_RELOC_MIPS16_HI16
:
10960 case BFD_RELOC_MIPS16_HI16_S
:
10961 assert (! fixP
->fx_pcrel
);
10962 /* Nothing needed to do. The value comes from the reloc entry */
10965 case BFD_RELOC_MIPS16_JMP
:
10966 /* We currently always generate a reloc against a symbol, which
10967 means that we don't want an addend even if the symbol is
10973 /* This is handled like BFD_RELOC_32, but we output a sign
10974 extended value if we are only 32 bits. */
10977 if (8 <= sizeof (valueT
))
10978 md_number_to_chars ((char *) buf
, *valP
, 8);
10983 if ((*valP
& 0x80000000) != 0)
10987 md_number_to_chars ((char *)(buf
+ target_big_endian
? 4 : 0),
10989 md_number_to_chars ((char *)(buf
+ target_big_endian
? 0 : 4),
10995 case BFD_RELOC_RVA
:
10997 /* If we are deleting this reloc entry, we must fill in the
10998 value now. This can happen if we have a .word which is not
10999 resolved when it appears but is later defined. */
11001 md_number_to_chars ((char *) buf
, *valP
, 4);
11005 /* If we are deleting this reloc entry, we must fill in the
11008 md_number_to_chars ((char *) buf
, *valP
, 2);
11011 case BFD_RELOC_LO16
:
11012 case BFD_RELOC_MIPS16_LO16
:
11013 /* FIXME: Now that embedded-PIC is gone, some of this code/comment
11014 may be safe to remove, but if so it's not obvious. */
11015 /* When handling an embedded PIC switch statement, we can wind
11016 up deleting a LO16 reloc. See the 'o' case in mips_ip. */
11019 if (*valP
+ 0x8000 > 0xffff)
11020 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
11021 _("relocation overflow"));
11022 if (target_big_endian
)
11024 md_number_to_chars ((char *) buf
, *valP
, 2);
11028 case BFD_RELOC_16_PCREL_S2
:
11029 if ((*valP
& 0x3) != 0)
11030 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
11031 _("Branch to odd address (%lx)"), (long) *valP
);
11034 * We need to save the bits in the instruction since fixup_segment()
11035 * might be deleting the relocation entry (i.e., a branch within
11036 * the current segment).
11038 if (! fixP
->fx_done
)
11041 /* update old instruction data */
11042 if (target_big_endian
)
11043 insn
= (buf
[0] << 24) | (buf
[1] << 16) | (buf
[2] << 8) | buf
[3];
11045 insn
= (buf
[3] << 24) | (buf
[2] << 16) | (buf
[1] << 8) | buf
[0];
11047 if (*valP
+ 0x20000 <= 0x3ffff)
11049 insn
|= (*valP
>> 2) & 0xffff;
11050 md_number_to_chars ((char *) buf
, insn
, 4);
11052 else if (mips_pic
== NO_PIC
11054 && fixP
->fx_frag
->fr_address
>= text_section
->vma
11055 && (fixP
->fx_frag
->fr_address
11056 < text_section
->vma
+ bfd_get_section_size (text_section
))
11057 && ((insn
& 0xffff0000) == 0x10000000 /* beq $0,$0 */
11058 || (insn
& 0xffff0000) == 0x04010000 /* bgez $0 */
11059 || (insn
& 0xffff0000) == 0x04110000)) /* bgezal $0 */
11061 /* The branch offset is too large. If this is an
11062 unconditional branch, and we are not generating PIC code,
11063 we can convert it to an absolute jump instruction. */
11064 if ((insn
& 0xffff0000) == 0x04110000) /* bgezal $0 */
11065 insn
= 0x0c000000; /* jal */
11067 insn
= 0x08000000; /* j */
11068 fixP
->fx_r_type
= BFD_RELOC_MIPS_JMP
;
11070 fixP
->fx_addsy
= section_symbol (text_section
);
11071 *valP
+= md_pcrel_from (fixP
);
11072 md_number_to_chars ((char *) buf
, insn
, 4);
11076 /* If we got here, we have branch-relaxation disabled,
11077 and there's nothing we can do to fix this instruction
11078 without turning it into a longer sequence. */
11079 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
11080 _("Branch out of range"));
11084 case BFD_RELOC_VTABLE_INHERIT
:
11087 && !S_IS_DEFINED (fixP
->fx_addsy
)
11088 && !S_IS_WEAK (fixP
->fx_addsy
))
11089 S_SET_WEAK (fixP
->fx_addsy
);
11092 case BFD_RELOC_VTABLE_ENTRY
:
11100 /* Remember value for tc_gen_reloc. */
11101 fixP
->fx_addnumber
= *valP
;
11111 name
= input_line_pointer
;
11112 c
= get_symbol_end ();
11113 p
= (symbolS
*) symbol_find_or_make (name
);
11114 *input_line_pointer
= c
;
11118 /* Align the current frag to a given power of two. The MIPS assembler
11119 also automatically adjusts any preceding label. */
11122 mips_align (int to
, int fill
, symbolS
*label
)
11124 mips_emit_delays ();
11125 frag_align (to
, fill
, 0);
11126 record_alignment (now_seg
, to
);
11129 assert (S_GET_SEGMENT (label
) == now_seg
);
11130 symbol_set_frag (label
, frag_now
);
11131 S_SET_VALUE (label
, (valueT
) frag_now_fix ());
11135 /* Align to a given power of two. .align 0 turns off the automatic
11136 alignment used by the data creating pseudo-ops. */
11139 s_align (int x ATTRIBUTE_UNUSED
)
11142 register long temp_fill
;
11143 long max_alignment
= 15;
11147 o Note that the assembler pulls down any immediately preceding label
11148 to the aligned address.
11149 o It's not documented but auto alignment is reinstated by
11150 a .align pseudo instruction.
11151 o Note also that after auto alignment is turned off the mips assembler
11152 issues an error on attempt to assemble an improperly aligned data item.
11157 temp
= get_absolute_expression ();
11158 if (temp
> max_alignment
)
11159 as_bad (_("Alignment too large: %d. assumed."), temp
= max_alignment
);
11162 as_warn (_("Alignment negative: 0 assumed."));
11165 if (*input_line_pointer
== ',')
11167 ++input_line_pointer
;
11168 temp_fill
= get_absolute_expression ();
11175 mips_align (temp
, (int) temp_fill
,
11176 insn_labels
!= NULL
? insn_labels
->label
: NULL
);
11183 demand_empty_rest_of_line ();
11187 s_change_sec (int sec
)
11192 /* The ELF backend needs to know that we are changing sections, so
11193 that .previous works correctly. We could do something like check
11194 for an obj_section_change_hook macro, but that might be confusing
11195 as it would not be appropriate to use it in the section changing
11196 functions in read.c, since obj-elf.c intercepts those. FIXME:
11197 This should be cleaner, somehow. */
11198 obj_elf_section_change_hook ();
11201 mips_emit_delays ();
11211 subseg_set (bss_section
, (subsegT
) get_absolute_expression ());
11212 demand_empty_rest_of_line ();
11216 seg
= subseg_new (RDATA_SECTION_NAME
,
11217 (subsegT
) get_absolute_expression ());
11218 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
11220 bfd_set_section_flags (stdoutput
, seg
, (SEC_ALLOC
| SEC_LOAD
11221 | SEC_READONLY
| SEC_RELOC
11223 if (strcmp (TARGET_OS
, "elf") != 0)
11224 record_alignment (seg
, 4);
11226 demand_empty_rest_of_line ();
11230 seg
= subseg_new (".sdata", (subsegT
) get_absolute_expression ());
11231 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
11233 bfd_set_section_flags (stdoutput
, seg
,
11234 SEC_ALLOC
| SEC_LOAD
| SEC_RELOC
| SEC_DATA
);
11235 if (strcmp (TARGET_OS
, "elf") != 0)
11236 record_alignment (seg
, 4);
11238 demand_empty_rest_of_line ();
11246 s_change_section (int ignore ATTRIBUTE_UNUSED
)
11249 char *section_name
;
11254 int section_entry_size
;
11255 int section_alignment
;
11257 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
11260 section_name
= input_line_pointer
;
11261 c
= get_symbol_end ();
11263 next_c
= *(input_line_pointer
+ 1);
11265 /* Do we have .section Name<,"flags">? */
11266 if (c
!= ',' || (c
== ',' && next_c
== '"'))
11268 /* just after name is now '\0'. */
11269 *input_line_pointer
= c
;
11270 input_line_pointer
= section_name
;
11271 obj_elf_section (ignore
);
11274 input_line_pointer
++;
11276 /* Do we have .section Name<,type><,flag><,entry_size><,alignment> */
11278 section_type
= get_absolute_expression ();
11281 if (*input_line_pointer
++ == ',')
11282 section_flag
= get_absolute_expression ();
11285 if (*input_line_pointer
++ == ',')
11286 section_entry_size
= get_absolute_expression ();
11288 section_entry_size
= 0;
11289 if (*input_line_pointer
++ == ',')
11290 section_alignment
= get_absolute_expression ();
11292 section_alignment
= 0;
11294 section_name
= xstrdup (section_name
);
11296 /* When using the generic form of .section (as implemented by obj-elf.c),
11297 there's no way to set the section type to SHT_MIPS_DWARF. Users have
11298 traditionally had to fall back on the more common @progbits instead.
11300 There's nothing really harmful in this, since bfd will correct
11301 SHT_PROGBITS to SHT_MIPS_DWARF before writing out the file. But it
11302 means that, for backwards compatibiltiy, the special_section entries
11303 for dwarf sections must use SHT_PROGBITS rather than SHT_MIPS_DWARF.
11305 Even so, we shouldn't force users of the MIPS .section syntax to
11306 incorrectly label the sections as SHT_PROGBITS. The best compromise
11307 seems to be to map SHT_MIPS_DWARF to SHT_PROGBITS before calling the
11308 generic type-checking code. */
11309 if (section_type
== SHT_MIPS_DWARF
)
11310 section_type
= SHT_PROGBITS
;
11312 obj_elf_change_section (section_name
, section_type
, section_flag
,
11313 section_entry_size
, 0, 0, 0);
11315 if (now_seg
->name
!= section_name
)
11316 free (section_name
);
11317 #endif /* OBJ_ELF */
11321 mips_enable_auto_align (void)
11327 s_cons (int log_size
)
11331 label
= insn_labels
!= NULL
? insn_labels
->label
: NULL
;
11332 mips_emit_delays ();
11333 if (log_size
> 0 && auto_align
)
11334 mips_align (log_size
, 0, label
);
11335 mips_clear_insn_labels ();
11336 cons (1 << log_size
);
11340 s_float_cons (int type
)
11344 label
= insn_labels
!= NULL
? insn_labels
->label
: NULL
;
11346 mips_emit_delays ();
11351 mips_align (3, 0, label
);
11353 mips_align (2, 0, label
);
11356 mips_clear_insn_labels ();
11361 /* Handle .globl. We need to override it because on Irix 5 you are
11364 where foo is an undefined symbol, to mean that foo should be
11365 considered to be the address of a function. */
11368 s_mips_globl (int x ATTRIBUTE_UNUSED
)
11375 name
= input_line_pointer
;
11376 c
= get_symbol_end ();
11377 symbolP
= symbol_find_or_make (name
);
11378 *input_line_pointer
= c
;
11379 SKIP_WHITESPACE ();
11381 /* On Irix 5, every global symbol that is not explicitly labelled as
11382 being a function is apparently labelled as being an object. */
11385 if (! is_end_of_line
[(unsigned char) *input_line_pointer
])
11390 secname
= input_line_pointer
;
11391 c
= get_symbol_end ();
11392 sec
= bfd_get_section_by_name (stdoutput
, secname
);
11394 as_bad (_("%s: no such section"), secname
);
11395 *input_line_pointer
= c
;
11397 if (sec
!= NULL
&& (sec
->flags
& SEC_CODE
) != 0)
11398 flag
= BSF_FUNCTION
;
11401 symbol_get_bfdsym (symbolP
)->flags
|= flag
;
11403 S_SET_EXTERNAL (symbolP
);
11404 demand_empty_rest_of_line ();
11408 s_option (int x ATTRIBUTE_UNUSED
)
11413 opt
= input_line_pointer
;
11414 c
= get_symbol_end ();
11418 /* FIXME: What does this mean? */
11420 else if (strncmp (opt
, "pic", 3) == 0)
11424 i
= atoi (opt
+ 3);
11429 mips_pic
= SVR4_PIC
;
11430 mips_abicalls
= TRUE
;
11433 as_bad (_(".option pic%d not supported"), i
);
11435 if (mips_pic
== SVR4_PIC
)
11437 if (g_switch_seen
&& g_switch_value
!= 0)
11438 as_warn (_("-G may not be used with SVR4 PIC code"));
11439 g_switch_value
= 0;
11440 bfd_set_gp_size (stdoutput
, 0);
11444 as_warn (_("Unrecognized option \"%s\""), opt
);
11446 *input_line_pointer
= c
;
11447 demand_empty_rest_of_line ();
11450 /* This structure is used to hold a stack of .set values. */
11452 struct mips_option_stack
11454 struct mips_option_stack
*next
;
11455 struct mips_set_options options
;
11458 static struct mips_option_stack
*mips_opts_stack
;
11460 /* Handle the .set pseudo-op. */
11463 s_mipsset (int x ATTRIBUTE_UNUSED
)
11465 char *name
= input_line_pointer
, ch
;
11467 while (!is_end_of_line
[(unsigned char) *input_line_pointer
])
11468 ++input_line_pointer
;
11469 ch
= *input_line_pointer
;
11470 *input_line_pointer
= '\0';
11472 if (strcmp (name
, "reorder") == 0)
11474 if (mips_opts
.noreorder
)
11477 else if (strcmp (name
, "noreorder") == 0)
11479 if (!mips_opts
.noreorder
)
11480 start_noreorder ();
11482 else if (strcmp (name
, "at") == 0)
11484 mips_opts
.noat
= 0;
11486 else if (strcmp (name
, "noat") == 0)
11488 mips_opts
.noat
= 1;
11490 else if (strcmp (name
, "macro") == 0)
11492 mips_opts
.warn_about_macros
= 0;
11494 else if (strcmp (name
, "nomacro") == 0)
11496 if (mips_opts
.noreorder
== 0)
11497 as_bad (_("`noreorder' must be set before `nomacro'"));
11498 mips_opts
.warn_about_macros
= 1;
11500 else if (strcmp (name
, "move") == 0 || strcmp (name
, "novolatile") == 0)
11502 mips_opts
.nomove
= 0;
11504 else if (strcmp (name
, "nomove") == 0 || strcmp (name
, "volatile") == 0)
11506 mips_opts
.nomove
= 1;
11508 else if (strcmp (name
, "bopt") == 0)
11510 mips_opts
.nobopt
= 0;
11512 else if (strcmp (name
, "nobopt") == 0)
11514 mips_opts
.nobopt
= 1;
11516 else if (strcmp (name
, "mips16") == 0
11517 || strcmp (name
, "MIPS-16") == 0)
11518 mips_opts
.mips16
= 1;
11519 else if (strcmp (name
, "nomips16") == 0
11520 || strcmp (name
, "noMIPS-16") == 0)
11521 mips_opts
.mips16
= 0;
11522 else if (strcmp (name
, "mips3d") == 0)
11523 mips_opts
.ase_mips3d
= 1;
11524 else if (strcmp (name
, "nomips3d") == 0)
11525 mips_opts
.ase_mips3d
= 0;
11526 else if (strcmp (name
, "mdmx") == 0)
11527 mips_opts
.ase_mdmx
= 1;
11528 else if (strcmp (name
, "nomdmx") == 0)
11529 mips_opts
.ase_mdmx
= 0;
11530 else if (strncmp (name
, "mips", 4) == 0 || strncmp (name
, "arch=", 5) == 0)
11534 /* Permit the user to change the ISA and architecture on the fly.
11535 Needless to say, misuse can cause serious problems. */
11536 if (strcmp (name
, "mips0") == 0 || strcmp (name
, "arch=default") == 0)
11539 mips_opts
.isa
= file_mips_isa
;
11540 mips_opts
.arch
= file_mips_arch
;
11542 else if (strncmp (name
, "arch=", 5) == 0)
11544 const struct mips_cpu_info
*p
;
11546 p
= mips_parse_cpu("internal use", name
+ 5);
11548 as_bad (_("unknown architecture %s"), name
+ 5);
11551 mips_opts
.arch
= p
->cpu
;
11552 mips_opts
.isa
= p
->isa
;
11555 else if (strncmp (name
, "mips", 4) == 0)
11557 const struct mips_cpu_info
*p
;
11559 p
= mips_parse_cpu("internal use", name
);
11561 as_bad (_("unknown ISA level %s"), name
+ 4);
11564 mips_opts
.arch
= p
->cpu
;
11565 mips_opts
.isa
= p
->isa
;
11569 as_bad (_("unknown ISA or architecture %s"), name
);
11571 switch (mips_opts
.isa
)
11579 mips_opts
.gp32
= 1;
11580 mips_opts
.fp32
= 1;
11587 mips_opts
.gp32
= 0;
11588 mips_opts
.fp32
= 0;
11591 as_bad (_("unknown ISA level %s"), name
+ 4);
11596 mips_opts
.gp32
= file_mips_gp32
;
11597 mips_opts
.fp32
= file_mips_fp32
;
11600 else if (strcmp (name
, "autoextend") == 0)
11601 mips_opts
.noautoextend
= 0;
11602 else if (strcmp (name
, "noautoextend") == 0)
11603 mips_opts
.noautoextend
= 1;
11604 else if (strcmp (name
, "push") == 0)
11606 struct mips_option_stack
*s
;
11608 s
= (struct mips_option_stack
*) xmalloc (sizeof *s
);
11609 s
->next
= mips_opts_stack
;
11610 s
->options
= mips_opts
;
11611 mips_opts_stack
= s
;
11613 else if (strcmp (name
, "pop") == 0)
11615 struct mips_option_stack
*s
;
11617 s
= mips_opts_stack
;
11619 as_bad (_(".set pop with no .set push"));
11622 /* If we're changing the reorder mode we need to handle
11623 delay slots correctly. */
11624 if (s
->options
.noreorder
&& ! mips_opts
.noreorder
)
11625 start_noreorder ();
11626 else if (! s
->options
.noreorder
&& mips_opts
.noreorder
)
11629 mips_opts
= s
->options
;
11630 mips_opts_stack
= s
->next
;
11634 else if (strcmp (name
, "sym32") == 0)
11635 mips_opts
.sym32
= TRUE
;
11636 else if (strcmp (name
, "nosym32") == 0)
11637 mips_opts
.sym32
= FALSE
;
11640 as_warn (_("Tried to set unrecognized symbol: %s\n"), name
);
11642 *input_line_pointer
= ch
;
11643 demand_empty_rest_of_line ();
11646 /* Handle the .abicalls pseudo-op. I believe this is equivalent to
11647 .option pic2. It means to generate SVR4 PIC calls. */
11650 s_abicalls (int ignore ATTRIBUTE_UNUSED
)
11652 mips_pic
= SVR4_PIC
;
11653 mips_abicalls
= TRUE
;
11655 if (g_switch_seen
&& g_switch_value
!= 0)
11656 as_warn (_("-G may not be used with SVR4 PIC code"));
11657 g_switch_value
= 0;
11659 bfd_set_gp_size (stdoutput
, 0);
11660 demand_empty_rest_of_line ();
11663 /* Handle the .cpload pseudo-op. This is used when generating SVR4
11664 PIC code. It sets the $gp register for the function based on the
11665 function address, which is in the register named in the argument.
11666 This uses a relocation against _gp_disp, which is handled specially
11667 by the linker. The result is:
11668 lui $gp,%hi(_gp_disp)
11669 addiu $gp,$gp,%lo(_gp_disp)
11670 addu $gp,$gp,.cpload argument
11671 The .cpload argument is normally $25 == $t9.
11673 The -mno-shared option changes this to:
11674 lui $gp,%hi(__gnu_local_gp)
11675 addiu $gp,$gp,%lo(__gnu_local_gp)
11676 and the argument is ignored. This saves an instruction, but the
11677 resulting code is not position independent; it uses an absolute
11678 address for __gnu_local_gp. Thus code assembled with -mno-shared
11679 can go into an ordinary executable, but not into a shared library. */
11682 s_cpload (int ignore ATTRIBUTE_UNUSED
)
11688 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
11689 .cpload is ignored. */
11690 if (mips_pic
!= SVR4_PIC
|| HAVE_NEWABI
)
11696 /* .cpload should be in a .set noreorder section. */
11697 if (mips_opts
.noreorder
== 0)
11698 as_warn (_(".cpload not in noreorder section"));
11700 reg
= tc_get_register (0);
11702 /* If we need to produce a 64-bit address, we are better off using
11703 the default instruction sequence. */
11704 in_shared
= mips_in_shared
|| HAVE_64BIT_SYMBOLS
;
11706 ex
.X_op
= O_symbol
;
11707 ex
.X_add_symbol
= symbol_find_or_make (in_shared
? "_gp_disp" :
11709 ex
.X_op_symbol
= NULL
;
11710 ex
.X_add_number
= 0;
11712 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
11713 symbol_get_bfdsym (ex
.X_add_symbol
)->flags
|= BSF_OBJECT
;
11716 macro_build_lui (&ex
, mips_gp_register
);
11717 macro_build (&ex
, "addiu", "t,r,j", mips_gp_register
,
11718 mips_gp_register
, BFD_RELOC_LO16
);
11720 macro_build (NULL
, "addu", "d,v,t", mips_gp_register
,
11721 mips_gp_register
, reg
);
11724 demand_empty_rest_of_line ();
11727 /* Handle the .cpsetup pseudo-op defined for NewABI PIC code. The syntax is:
11728 .cpsetup $reg1, offset|$reg2, label
11730 If offset is given, this results in:
11731 sd $gp, offset($sp)
11732 lui $gp, %hi(%neg(%gp_rel(label)))
11733 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
11734 daddu $gp, $gp, $reg1
11736 If $reg2 is given, this results in:
11737 daddu $reg2, $gp, $0
11738 lui $gp, %hi(%neg(%gp_rel(label)))
11739 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
11740 daddu $gp, $gp, $reg1
11741 $reg1 is normally $25 == $t9.
11743 The -mno-shared option replaces the last three instructions with
11745 addiu $gp,$gp,%lo(_gp)
11749 s_cpsetup (int ignore ATTRIBUTE_UNUSED
)
11751 expressionS ex_off
;
11752 expressionS ex_sym
;
11755 /* If we are not generating SVR4 PIC code, .cpsetup is ignored.
11756 We also need NewABI support. */
11757 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
11763 reg1
= tc_get_register (0);
11764 SKIP_WHITESPACE ();
11765 if (*input_line_pointer
!= ',')
11767 as_bad (_("missing argument separator ',' for .cpsetup"));
11771 ++input_line_pointer
;
11772 SKIP_WHITESPACE ();
11773 if (*input_line_pointer
== '$')
11775 mips_cpreturn_register
= tc_get_register (0);
11776 mips_cpreturn_offset
= -1;
11780 mips_cpreturn_offset
= get_absolute_expression ();
11781 mips_cpreturn_register
= -1;
11783 SKIP_WHITESPACE ();
11784 if (*input_line_pointer
!= ',')
11786 as_bad (_("missing argument separator ',' for .cpsetup"));
11790 ++input_line_pointer
;
11791 SKIP_WHITESPACE ();
11792 expression (&ex_sym
);
11795 if (mips_cpreturn_register
== -1)
11797 ex_off
.X_op
= O_constant
;
11798 ex_off
.X_add_symbol
= NULL
;
11799 ex_off
.X_op_symbol
= NULL
;
11800 ex_off
.X_add_number
= mips_cpreturn_offset
;
11802 macro_build (&ex_off
, "sd", "t,o(b)", mips_gp_register
,
11803 BFD_RELOC_LO16
, SP
);
11806 macro_build (NULL
, "daddu", "d,v,t", mips_cpreturn_register
,
11807 mips_gp_register
, 0);
11809 if (mips_in_shared
|| HAVE_64BIT_SYMBOLS
)
11811 macro_build (&ex_sym
, "lui", "t,u", mips_gp_register
,
11812 -1, BFD_RELOC_GPREL16
, BFD_RELOC_MIPS_SUB
,
11815 macro_build (&ex_sym
, "addiu", "t,r,j", mips_gp_register
,
11816 mips_gp_register
, -1, BFD_RELOC_GPREL16
,
11817 BFD_RELOC_MIPS_SUB
, BFD_RELOC_LO16
);
11819 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", mips_gp_register
,
11820 mips_gp_register
, reg1
);
11826 ex
.X_op
= O_symbol
;
11827 ex
.X_add_symbol
= symbol_find_or_make ("__gnu_local_gp");
11828 ex
.X_op_symbol
= NULL
;
11829 ex
.X_add_number
= 0;
11831 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
11832 symbol_get_bfdsym (ex
.X_add_symbol
)->flags
|= BSF_OBJECT
;
11834 macro_build_lui (&ex
, mips_gp_register
);
11835 macro_build (&ex
, "addiu", "t,r,j", mips_gp_register
,
11836 mips_gp_register
, BFD_RELOC_LO16
);
11841 demand_empty_rest_of_line ();
11845 s_cplocal (int ignore ATTRIBUTE_UNUSED
)
11847 /* If we are not generating SVR4 PIC code, or if this is not NewABI code,
11848 .cplocal is ignored. */
11849 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
11855 mips_gp_register
= tc_get_register (0);
11856 demand_empty_rest_of_line ();
11859 /* Handle the .cprestore pseudo-op. This stores $gp into a given
11860 offset from $sp. The offset is remembered, and after making a PIC
11861 call $gp is restored from that location. */
11864 s_cprestore (int ignore ATTRIBUTE_UNUSED
)
11868 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
11869 .cprestore is ignored. */
11870 if (mips_pic
!= SVR4_PIC
|| HAVE_NEWABI
)
11876 mips_cprestore_offset
= get_absolute_expression ();
11877 mips_cprestore_valid
= 1;
11879 ex
.X_op
= O_constant
;
11880 ex
.X_add_symbol
= NULL
;
11881 ex
.X_op_symbol
= NULL
;
11882 ex
.X_add_number
= mips_cprestore_offset
;
11885 macro_build_ldst_constoffset (&ex
, ADDRESS_STORE_INSN
, mips_gp_register
,
11886 SP
, HAVE_64BIT_ADDRESSES
);
11889 demand_empty_rest_of_line ();
11892 /* Handle the .cpreturn pseudo-op defined for NewABI PIC code. If an offset
11893 was given in the preceding .cpsetup, it results in:
11894 ld $gp, offset($sp)
11896 If a register $reg2 was given there, it results in:
11897 daddu $gp, $reg2, $0
11900 s_cpreturn (int ignore ATTRIBUTE_UNUSED
)
11904 /* If we are not generating SVR4 PIC code, .cpreturn is ignored.
11905 We also need NewABI support. */
11906 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
11913 if (mips_cpreturn_register
== -1)
11915 ex
.X_op
= O_constant
;
11916 ex
.X_add_symbol
= NULL
;
11917 ex
.X_op_symbol
= NULL
;
11918 ex
.X_add_number
= mips_cpreturn_offset
;
11920 macro_build (&ex
, "ld", "t,o(b)", mips_gp_register
, BFD_RELOC_LO16
, SP
);
11923 macro_build (NULL
, "daddu", "d,v,t", mips_gp_register
,
11924 mips_cpreturn_register
, 0);
11927 demand_empty_rest_of_line ();
11930 /* Handle the .gpvalue pseudo-op. This is used when generating NewABI PIC
11931 code. It sets the offset to use in gp_rel relocations. */
11934 s_gpvalue (int ignore ATTRIBUTE_UNUSED
)
11936 /* If we are not generating SVR4 PIC code, .gpvalue is ignored.
11937 We also need NewABI support. */
11938 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
11944 mips_gprel_offset
= get_absolute_expression ();
11946 demand_empty_rest_of_line ();
11949 /* Handle the .gpword pseudo-op. This is used when generating PIC
11950 code. It generates a 32 bit GP relative reloc. */
11953 s_gpword (int ignore ATTRIBUTE_UNUSED
)
11959 /* When not generating PIC code, this is treated as .word. */
11960 if (mips_pic
!= SVR4_PIC
)
11966 label
= insn_labels
!= NULL
? insn_labels
->label
: NULL
;
11967 mips_emit_delays ();
11969 mips_align (2, 0, label
);
11970 mips_clear_insn_labels ();
11974 if (ex
.X_op
!= O_symbol
|| ex
.X_add_number
!= 0)
11976 as_bad (_("Unsupported use of .gpword"));
11977 ignore_rest_of_line ();
11981 md_number_to_chars (p
, 0, 4);
11982 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 4, &ex
, FALSE
,
11983 BFD_RELOC_GPREL32
);
11985 demand_empty_rest_of_line ();
11989 s_gpdword (int ignore ATTRIBUTE_UNUSED
)
11995 /* When not generating PIC code, this is treated as .dword. */
11996 if (mips_pic
!= SVR4_PIC
)
12002 label
= insn_labels
!= NULL
? insn_labels
->label
: NULL
;
12003 mips_emit_delays ();
12005 mips_align (3, 0, label
);
12006 mips_clear_insn_labels ();
12010 if (ex
.X_op
!= O_symbol
|| ex
.X_add_number
!= 0)
12012 as_bad (_("Unsupported use of .gpdword"));
12013 ignore_rest_of_line ();
12017 md_number_to_chars (p
, 0, 8);
12018 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 4, &ex
, FALSE
,
12019 BFD_RELOC_GPREL32
)->fx_tcbit
= 1;
12021 /* GPREL32 composed with 64 gives a 64-bit GP offset. */
12022 fix_new (frag_now
, p
- frag_now
->fr_literal
, 8, NULL
, 0,
12023 FALSE
, BFD_RELOC_64
)->fx_tcbit
= 1;
12025 demand_empty_rest_of_line ();
12028 /* Handle the .cpadd pseudo-op. This is used when dealing with switch
12029 tables in SVR4 PIC code. */
12032 s_cpadd (int ignore ATTRIBUTE_UNUSED
)
12036 /* This is ignored when not generating SVR4 PIC code. */
12037 if (mips_pic
!= SVR4_PIC
)
12043 /* Add $gp to the register named as an argument. */
12045 reg
= tc_get_register (0);
12046 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", reg
, reg
, mips_gp_register
);
12049 demand_empty_rest_of_line ();
12052 /* Handle the .insn pseudo-op. This marks instruction labels in
12053 mips16 mode. This permits the linker to handle them specially,
12054 such as generating jalx instructions when needed. We also make
12055 them odd for the duration of the assembly, in order to generate the
12056 right sort of code. We will make them even in the adjust_symtab
12057 routine, while leaving them marked. This is convenient for the
12058 debugger and the disassembler. The linker knows to make them odd
12062 s_insn (int ignore ATTRIBUTE_UNUSED
)
12064 mips16_mark_labels ();
12066 demand_empty_rest_of_line ();
12069 /* Handle a .stabn directive. We need these in order to mark a label
12070 as being a mips16 text label correctly. Sometimes the compiler
12071 will emit a label, followed by a .stabn, and then switch sections.
12072 If the label and .stabn are in mips16 mode, then the label is
12073 really a mips16 text label. */
12076 s_mips_stab (int type
)
12079 mips16_mark_labels ();
12084 /* Handle the .weakext pseudo-op as defined in Kane and Heinrich.
12088 s_mips_weakext (int ignore ATTRIBUTE_UNUSED
)
12095 name
= input_line_pointer
;
12096 c
= get_symbol_end ();
12097 symbolP
= symbol_find_or_make (name
);
12098 S_SET_WEAK (symbolP
);
12099 *input_line_pointer
= c
;
12101 SKIP_WHITESPACE ();
12103 if (! is_end_of_line
[(unsigned char) *input_line_pointer
])
12105 if (S_IS_DEFINED (symbolP
))
12107 as_bad ("ignoring attempt to redefine symbol %s",
12108 S_GET_NAME (symbolP
));
12109 ignore_rest_of_line ();
12113 if (*input_line_pointer
== ',')
12115 ++input_line_pointer
;
12116 SKIP_WHITESPACE ();
12120 if (exp
.X_op
!= O_symbol
)
12122 as_bad ("bad .weakext directive");
12123 ignore_rest_of_line ();
12126 symbol_set_value_expression (symbolP
, &exp
);
12129 demand_empty_rest_of_line ();
12132 /* Parse a register string into a number. Called from the ECOFF code
12133 to parse .frame. The argument is non-zero if this is the frame
12134 register, so that we can record it in mips_frame_reg. */
12137 tc_get_register (int frame
)
12141 SKIP_WHITESPACE ();
12142 if (*input_line_pointer
++ != '$')
12144 as_warn (_("expected `$'"));
12147 else if (ISDIGIT (*input_line_pointer
))
12149 reg
= get_absolute_expression ();
12150 if (reg
< 0 || reg
>= 32)
12152 as_warn (_("Bad register number"));
12158 if (strncmp (input_line_pointer
, "ra", 2) == 0)
12161 input_line_pointer
+= 2;
12163 else if (strncmp (input_line_pointer
, "fp", 2) == 0)
12166 input_line_pointer
+= 2;
12168 else if (strncmp (input_line_pointer
, "sp", 2) == 0)
12171 input_line_pointer
+= 2;
12173 else if (strncmp (input_line_pointer
, "gp", 2) == 0)
12176 input_line_pointer
+= 2;
12178 else if (strncmp (input_line_pointer
, "at", 2) == 0)
12181 input_line_pointer
+= 2;
12183 else if (strncmp (input_line_pointer
, "kt0", 3) == 0)
12186 input_line_pointer
+= 3;
12188 else if (strncmp (input_line_pointer
, "kt1", 3) == 0)
12191 input_line_pointer
+= 3;
12193 else if (strncmp (input_line_pointer
, "zero", 4) == 0)
12196 input_line_pointer
+= 4;
12200 as_warn (_("Unrecognized register name"));
12202 while (ISALNUM(*input_line_pointer
))
12203 input_line_pointer
++;
12208 mips_frame_reg
= reg
!= 0 ? reg
: SP
;
12209 mips_frame_reg_valid
= 1;
12210 mips_cprestore_valid
= 0;
12216 md_section_align (asection
*seg
, valueT addr
)
12218 int align
= bfd_get_section_alignment (stdoutput
, seg
);
12221 /* We don't need to align ELF sections to the full alignment.
12222 However, Irix 5 may prefer that we align them at least to a 16
12223 byte boundary. We don't bother to align the sections if we are
12224 targeted for an embedded system. */
12225 if (strcmp (TARGET_OS
, "elf") == 0)
12231 return ((addr
+ (1 << align
) - 1) & (-1 << align
));
12234 /* Utility routine, called from above as well. If called while the
12235 input file is still being read, it's only an approximation. (For
12236 example, a symbol may later become defined which appeared to be
12237 undefined earlier.) */
12240 nopic_need_relax (symbolS
*sym
, int before_relaxing
)
12245 if (g_switch_value
> 0)
12247 const char *symname
;
12250 /* Find out whether this symbol can be referenced off the $gp
12251 register. It can be if it is smaller than the -G size or if
12252 it is in the .sdata or .sbss section. Certain symbols can
12253 not be referenced off the $gp, although it appears as though
12255 symname
= S_GET_NAME (sym
);
12256 if (symname
!= (const char *) NULL
12257 && (strcmp (symname
, "eprol") == 0
12258 || strcmp (symname
, "etext") == 0
12259 || strcmp (symname
, "_gp") == 0
12260 || strcmp (symname
, "edata") == 0
12261 || strcmp (symname
, "_fbss") == 0
12262 || strcmp (symname
, "_fdata") == 0
12263 || strcmp (symname
, "_ftext") == 0
12264 || strcmp (symname
, "end") == 0
12265 || strcmp (symname
, "_gp_disp") == 0))
12267 else if ((! S_IS_DEFINED (sym
) || S_IS_COMMON (sym
))
12269 #ifndef NO_ECOFF_DEBUGGING
12270 || (symbol_get_obj (sym
)->ecoff_extern_size
!= 0
12271 && (symbol_get_obj (sym
)->ecoff_extern_size
12272 <= g_switch_value
))
12274 /* We must defer this decision until after the whole
12275 file has been read, since there might be a .extern
12276 after the first use of this symbol. */
12277 || (before_relaxing
12278 #ifndef NO_ECOFF_DEBUGGING
12279 && symbol_get_obj (sym
)->ecoff_extern_size
== 0
12281 && S_GET_VALUE (sym
) == 0)
12282 || (S_GET_VALUE (sym
) != 0
12283 && S_GET_VALUE (sym
) <= g_switch_value
)))
12287 const char *segname
;
12289 segname
= segment_name (S_GET_SEGMENT (sym
));
12290 assert (strcmp (segname
, ".lit8") != 0
12291 && strcmp (segname
, ".lit4") != 0);
12292 change
= (strcmp (segname
, ".sdata") != 0
12293 && strcmp (segname
, ".sbss") != 0
12294 && strncmp (segname
, ".sdata.", 7) != 0
12295 && strncmp (segname
, ".gnu.linkonce.s.", 16) != 0);
12300 /* We are not optimizing for the $gp register. */
12305 /* Return true if the given symbol should be considered local for SVR4 PIC. */
12308 pic_need_relax (symbolS
*sym
, asection
*segtype
)
12311 bfd_boolean linkonce
;
12313 /* Handle the case of a symbol equated to another symbol. */
12314 while (symbol_equated_reloc_p (sym
))
12318 /* It's possible to get a loop here in a badly written
12320 n
= symbol_get_value_expression (sym
)->X_add_symbol
;
12326 symsec
= S_GET_SEGMENT (sym
);
12328 /* duplicate the test for LINK_ONCE sections as in adjust_reloc_syms */
12330 if (symsec
!= segtype
&& ! S_IS_LOCAL (sym
))
12332 if ((bfd_get_section_flags (stdoutput
, symsec
) & SEC_LINK_ONCE
)
12336 /* The GNU toolchain uses an extension for ELF: a section
12337 beginning with the magic string .gnu.linkonce is a linkonce
12339 if (strncmp (segment_name (symsec
), ".gnu.linkonce",
12340 sizeof ".gnu.linkonce" - 1) == 0)
12344 /* This must duplicate the test in adjust_reloc_syms. */
12345 return (symsec
!= &bfd_und_section
12346 && symsec
!= &bfd_abs_section
12347 && ! bfd_is_com_section (symsec
)
12350 /* A global or weak symbol is treated as external. */
12351 && (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
12352 || (! S_IS_WEAK (sym
) && ! S_IS_EXTERNAL (sym
)))
12358 /* Given a mips16 variant frag FRAGP, return non-zero if it needs an
12359 extended opcode. SEC is the section the frag is in. */
12362 mips16_extended_frag (fragS
*fragp
, asection
*sec
, long stretch
)
12365 register const struct mips16_immed_operand
*op
;
12367 int mintiny
, maxtiny
;
12371 if (RELAX_MIPS16_USER_SMALL (fragp
->fr_subtype
))
12373 if (RELAX_MIPS16_USER_EXT (fragp
->fr_subtype
))
12376 type
= RELAX_MIPS16_TYPE (fragp
->fr_subtype
);
12377 op
= mips16_immed_operands
;
12378 while (op
->type
!= type
)
12381 assert (op
< mips16_immed_operands
+ MIPS16_NUM_IMMED
);
12386 if (type
== '<' || type
== '>' || type
== '[' || type
== ']')
12389 maxtiny
= 1 << op
->nbits
;
12394 maxtiny
= (1 << op
->nbits
) - 1;
12399 mintiny
= - (1 << (op
->nbits
- 1));
12400 maxtiny
= (1 << (op
->nbits
- 1)) - 1;
12403 sym_frag
= symbol_get_frag (fragp
->fr_symbol
);
12404 val
= S_GET_VALUE (fragp
->fr_symbol
);
12405 symsec
= S_GET_SEGMENT (fragp
->fr_symbol
);
12411 /* We won't have the section when we are called from
12412 mips_relax_frag. However, we will always have been called
12413 from md_estimate_size_before_relax first. If this is a
12414 branch to a different section, we mark it as such. If SEC is
12415 NULL, and the frag is not marked, then it must be a branch to
12416 the same section. */
12419 if (RELAX_MIPS16_LONG_BRANCH (fragp
->fr_subtype
))
12424 /* Must have been called from md_estimate_size_before_relax. */
12427 fragp
->fr_subtype
=
12428 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
12430 /* FIXME: We should support this, and let the linker
12431 catch branches and loads that are out of range. */
12432 as_bad_where (fragp
->fr_file
, fragp
->fr_line
,
12433 _("unsupported PC relative reference to different section"));
12437 if (fragp
!= sym_frag
&& sym_frag
->fr_address
== 0)
12438 /* Assume non-extended on the first relaxation pass.
12439 The address we have calculated will be bogus if this is
12440 a forward branch to another frag, as the forward frag
12441 will have fr_address == 0. */
12445 /* In this case, we know for sure that the symbol fragment is in
12446 the same section. If the relax_marker of the symbol fragment
12447 differs from the relax_marker of this fragment, we have not
12448 yet adjusted the symbol fragment fr_address. We want to add
12449 in STRETCH in order to get a better estimate of the address.
12450 This particularly matters because of the shift bits. */
12452 && sym_frag
->relax_marker
!= fragp
->relax_marker
)
12456 /* Adjust stretch for any alignment frag. Note that if have
12457 been expanding the earlier code, the symbol may be
12458 defined in what appears to be an earlier frag. FIXME:
12459 This doesn't handle the fr_subtype field, which specifies
12460 a maximum number of bytes to skip when doing an
12462 for (f
= fragp
; f
!= NULL
&& f
!= sym_frag
; f
= f
->fr_next
)
12464 if (f
->fr_type
== rs_align
|| f
->fr_type
== rs_align_code
)
12467 stretch
= - ((- stretch
)
12468 & ~ ((1 << (int) f
->fr_offset
) - 1));
12470 stretch
&= ~ ((1 << (int) f
->fr_offset
) - 1);
12479 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
12481 /* The base address rules are complicated. The base address of
12482 a branch is the following instruction. The base address of a
12483 PC relative load or add is the instruction itself, but if it
12484 is in a delay slot (in which case it can not be extended) use
12485 the address of the instruction whose delay slot it is in. */
12486 if (type
== 'p' || type
== 'q')
12490 /* If we are currently assuming that this frag should be
12491 extended, then, the current address is two bytes
12493 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
12496 /* Ignore the low bit in the target, since it will be set
12497 for a text label. */
12498 if ((val
& 1) != 0)
12501 else if (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
))
12503 else if (RELAX_MIPS16_DSLOT (fragp
->fr_subtype
))
12506 val
-= addr
& ~ ((1 << op
->shift
) - 1);
12508 /* Branch offsets have an implicit 0 in the lowest bit. */
12509 if (type
== 'p' || type
== 'q')
12512 /* If any of the shifted bits are set, we must use an extended
12513 opcode. If the address depends on the size of this
12514 instruction, this can lead to a loop, so we arrange to always
12515 use an extended opcode. We only check this when we are in
12516 the main relaxation loop, when SEC is NULL. */
12517 if ((val
& ((1 << op
->shift
) - 1)) != 0 && sec
== NULL
)
12519 fragp
->fr_subtype
=
12520 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
12524 /* If we are about to mark a frag as extended because the value
12525 is precisely maxtiny + 1, then there is a chance of an
12526 infinite loop as in the following code:
12531 In this case when the la is extended, foo is 0x3fc bytes
12532 away, so the la can be shrunk, but then foo is 0x400 away, so
12533 the la must be extended. To avoid this loop, we mark the
12534 frag as extended if it was small, and is about to become
12535 extended with a value of maxtiny + 1. */
12536 if (val
== ((maxtiny
+ 1) << op
->shift
)
12537 && ! RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
)
12540 fragp
->fr_subtype
=
12541 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
12545 else if (symsec
!= absolute_section
&& sec
!= NULL
)
12546 as_bad_where (fragp
->fr_file
, fragp
->fr_line
, _("unsupported relocation"));
12548 if ((val
& ((1 << op
->shift
) - 1)) != 0
12549 || val
< (mintiny
<< op
->shift
)
12550 || val
> (maxtiny
<< op
->shift
))
12556 /* Compute the length of a branch sequence, and adjust the
12557 RELAX_BRANCH_TOOFAR bit accordingly. If FRAGP is NULL, the
12558 worst-case length is computed, with UPDATE being used to indicate
12559 whether an unconditional (-1), branch-likely (+1) or regular (0)
12560 branch is to be computed. */
12562 relaxed_branch_length (fragS
*fragp
, asection
*sec
, int update
)
12564 bfd_boolean toofar
;
12568 && S_IS_DEFINED (fragp
->fr_symbol
)
12569 && sec
== S_GET_SEGMENT (fragp
->fr_symbol
))
12574 val
= S_GET_VALUE (fragp
->fr_symbol
) + fragp
->fr_offset
;
12576 addr
= fragp
->fr_address
+ fragp
->fr_fix
+ 4;
12580 toofar
= val
< - (0x8000 << 2) || val
>= (0x8000 << 2);
12583 /* If the symbol is not defined or it's in a different segment,
12584 assume the user knows what's going on and emit a short
12590 if (fragp
&& update
&& toofar
!= RELAX_BRANCH_TOOFAR (fragp
->fr_subtype
))
12592 = RELAX_BRANCH_ENCODE (RELAX_BRANCH_UNCOND (fragp
->fr_subtype
),
12593 RELAX_BRANCH_LIKELY (fragp
->fr_subtype
),
12594 RELAX_BRANCH_LINK (fragp
->fr_subtype
),
12600 if (fragp
? RELAX_BRANCH_LIKELY (fragp
->fr_subtype
) : (update
> 0))
12603 if (mips_pic
!= NO_PIC
)
12605 /* Additional space for PIC loading of target address. */
12607 if (mips_opts
.isa
== ISA_MIPS1
)
12608 /* Additional space for $at-stabilizing nop. */
12612 /* If branch is conditional. */
12613 if (fragp
? !RELAX_BRANCH_UNCOND (fragp
->fr_subtype
) : (update
>= 0))
12620 /* Estimate the size of a frag before relaxing. Unless this is the
12621 mips16, we are not really relaxing here, and the final size is
12622 encoded in the subtype information. For the mips16, we have to
12623 decide whether we are using an extended opcode or not. */
12626 md_estimate_size_before_relax (fragS
*fragp
, asection
*segtype
)
12630 if (RELAX_BRANCH_P (fragp
->fr_subtype
))
12633 fragp
->fr_var
= relaxed_branch_length (fragp
, segtype
, FALSE
);
12635 return fragp
->fr_var
;
12638 if (RELAX_MIPS16_P (fragp
->fr_subtype
))
12639 /* We don't want to modify the EXTENDED bit here; it might get us
12640 into infinite loops. We change it only in mips_relax_frag(). */
12641 return (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
) ? 4 : 2);
12643 if (mips_pic
== NO_PIC
)
12644 change
= nopic_need_relax (fragp
->fr_symbol
, 0);
12645 else if (mips_pic
== SVR4_PIC
)
12646 change
= pic_need_relax (fragp
->fr_symbol
, segtype
);
12652 fragp
->fr_subtype
|= RELAX_USE_SECOND
;
12653 return -RELAX_FIRST (fragp
->fr_subtype
);
12656 return -RELAX_SECOND (fragp
->fr_subtype
);
12659 /* This is called to see whether a reloc against a defined symbol
12660 should be converted into a reloc against a section. */
12663 mips_fix_adjustable (fixS
*fixp
)
12665 /* Don't adjust MIPS16 jump relocations, so we don't have to worry
12666 about the format of the offset in the .o file. */
12667 if (fixp
->fx_r_type
== BFD_RELOC_MIPS16_JMP
)
12670 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
12671 || fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
12674 if (fixp
->fx_addsy
== NULL
)
12677 /* If symbol SYM is in a mergeable section, relocations of the form
12678 SYM + 0 can usually be made section-relative. The mergeable data
12679 is then identified by the section offset rather than by the symbol.
12681 However, if we're generating REL LO16 relocations, the offset is split
12682 between the LO16 and parterning high part relocation. The linker will
12683 need to recalculate the complete offset in order to correctly identify
12686 The linker has traditionally not looked for the parterning high part
12687 relocation, and has thus allowed orphaned R_MIPS_LO16 relocations to be
12688 placed anywhere. Rather than break backwards compatibility by changing
12689 this, it seems better not to force the issue, and instead keep the
12690 original symbol. This will work with either linker behavior. */
12691 if ((fixp
->fx_r_type
== BFD_RELOC_LO16
|| reloc_needs_lo_p (fixp
->fx_r_type
))
12692 && HAVE_IN_PLACE_ADDENDS
12693 && (S_GET_SEGMENT (fixp
->fx_addsy
)->flags
& SEC_MERGE
) != 0)
12697 /* Don't adjust relocations against mips16 symbols, so that the linker
12698 can find them if it needs to set up a stub. */
12699 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
12700 && S_GET_OTHER (fixp
->fx_addsy
) == STO_MIPS16
12701 && fixp
->fx_subsy
== NULL
)
12708 /* Translate internal representation of relocation info to BFD target
12712 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
, fixS
*fixp
)
12714 static arelent
*retval
[4];
12716 bfd_reloc_code_real_type code
;
12718 memset (retval
, 0, sizeof(retval
));
12719 reloc
= retval
[0] = (arelent
*) xcalloc (1, sizeof (arelent
));
12720 reloc
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
12721 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
12722 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
12724 assert (! fixp
->fx_pcrel
);
12725 reloc
->addend
= fixp
->fx_addnumber
;
12727 /* Since the old MIPS ELF ABI uses Rel instead of Rela, encode the vtable
12728 entry to be used in the relocation's section offset. */
12729 if (! HAVE_NEWABI
&& fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
12731 reloc
->address
= reloc
->addend
;
12735 code
= fixp
->fx_r_type
;
12737 /* To support a PC relative reloc, we used a Cygnus extension.
12738 We check for that here to make sure that we don't let such a
12739 reloc escape normally. (FIXME: This was formerly used by
12740 embedded-PIC support, but is now used by branch handling in
12741 general. That probably should be fixed.) */
12742 if ((OUTPUT_FLAVOR
== bfd_target_ecoff_flavour
12743 || OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
12744 && code
== BFD_RELOC_16_PCREL_S2
)
12745 reloc
->howto
= NULL
;
12747 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
12749 if (reloc
->howto
== NULL
)
12751 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
12752 _("Can not represent %s relocation in this object file format"),
12753 bfd_get_reloc_code_name (code
));
12760 /* Relax a machine dependent frag. This returns the amount by which
12761 the current size of the frag should change. */
12764 mips_relax_frag (asection
*sec
, fragS
*fragp
, long stretch
)
12766 if (RELAX_BRANCH_P (fragp
->fr_subtype
))
12768 offsetT old_var
= fragp
->fr_var
;
12770 fragp
->fr_var
= relaxed_branch_length (fragp
, sec
, TRUE
);
12772 return fragp
->fr_var
- old_var
;
12775 if (! RELAX_MIPS16_P (fragp
->fr_subtype
))
12778 if (mips16_extended_frag (fragp
, NULL
, stretch
))
12780 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
12782 fragp
->fr_subtype
= RELAX_MIPS16_MARK_EXTENDED (fragp
->fr_subtype
);
12787 if (! RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
12789 fragp
->fr_subtype
= RELAX_MIPS16_CLEAR_EXTENDED (fragp
->fr_subtype
);
12796 /* Convert a machine dependent frag. */
12799 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
, segT asec
, fragS
*fragp
)
12801 if (RELAX_BRANCH_P (fragp
->fr_subtype
))
12804 unsigned long insn
;
12808 buf
= (bfd_byte
*)fragp
->fr_literal
+ fragp
->fr_fix
;
12810 if (target_big_endian
)
12811 insn
= bfd_getb32 (buf
);
12813 insn
= bfd_getl32 (buf
);
12815 if (!RELAX_BRANCH_TOOFAR (fragp
->fr_subtype
))
12817 /* We generate a fixup instead of applying it right now
12818 because, if there are linker relaxations, we're going to
12819 need the relocations. */
12820 exp
.X_op
= O_symbol
;
12821 exp
.X_add_symbol
= fragp
->fr_symbol
;
12822 exp
.X_add_number
= fragp
->fr_offset
;
12824 fixp
= fix_new_exp (fragp
, buf
- (bfd_byte
*)fragp
->fr_literal
,
12826 BFD_RELOC_16_PCREL_S2
);
12827 fixp
->fx_file
= fragp
->fr_file
;
12828 fixp
->fx_line
= fragp
->fr_line
;
12830 md_number_to_chars ((char *) buf
, insn
, 4);
12837 as_warn_where (fragp
->fr_file
, fragp
->fr_line
,
12838 _("relaxed out-of-range branch into a jump"));
12840 if (RELAX_BRANCH_UNCOND (fragp
->fr_subtype
))
12843 if (!RELAX_BRANCH_LIKELY (fragp
->fr_subtype
))
12845 /* Reverse the branch. */
12846 switch ((insn
>> 28) & 0xf)
12849 /* bc[0-3][tf]l? and bc1any[24][ft] instructions can
12850 have the condition reversed by tweaking a single
12851 bit, and their opcodes all have 0x4???????. */
12852 assert ((insn
& 0xf1000000) == 0x41000000);
12853 insn
^= 0x00010000;
12857 /* bltz 0x04000000 bgez 0x04010000
12858 bltzal 0x04100000 bgezal 0x04110000 */
12859 assert ((insn
& 0xfc0e0000) == 0x04000000);
12860 insn
^= 0x00010000;
12864 /* beq 0x10000000 bne 0x14000000
12865 blez 0x18000000 bgtz 0x1c000000 */
12866 insn
^= 0x04000000;
12874 if (RELAX_BRANCH_LINK (fragp
->fr_subtype
))
12876 /* Clear the and-link bit. */
12877 assert ((insn
& 0xfc1c0000) == 0x04100000);
12879 /* bltzal 0x04100000 bgezal 0x04110000
12880 bltzall 0x04120000 bgezall 0x04130000 */
12881 insn
&= ~0x00100000;
12884 /* Branch over the branch (if the branch was likely) or the
12885 full jump (not likely case). Compute the offset from the
12886 current instruction to branch to. */
12887 if (RELAX_BRANCH_LIKELY (fragp
->fr_subtype
))
12891 /* How many bytes in instructions we've already emitted? */
12892 i
= buf
- (bfd_byte
*)fragp
->fr_literal
- fragp
->fr_fix
;
12893 /* How many bytes in instructions from here to the end? */
12894 i
= fragp
->fr_var
- i
;
12896 /* Convert to instruction count. */
12898 /* Branch counts from the next instruction. */
12901 /* Branch over the jump. */
12902 md_number_to_chars ((char *) buf
, insn
, 4);
12906 md_number_to_chars ((char *) buf
, 0, 4);
12909 if (RELAX_BRANCH_LIKELY (fragp
->fr_subtype
))
12911 /* beql $0, $0, 2f */
12913 /* Compute the PC offset from the current instruction to
12914 the end of the variable frag. */
12915 /* How many bytes in instructions we've already emitted? */
12916 i
= buf
- (bfd_byte
*)fragp
->fr_literal
- fragp
->fr_fix
;
12917 /* How many bytes in instructions from here to the end? */
12918 i
= fragp
->fr_var
- i
;
12919 /* Convert to instruction count. */
12921 /* Don't decrement i, because we want to branch over the
12925 md_number_to_chars ((char *) buf
, insn
, 4);
12928 md_number_to_chars ((char *) buf
, 0, 4);
12933 if (mips_pic
== NO_PIC
)
12936 insn
= (RELAX_BRANCH_LINK (fragp
->fr_subtype
)
12937 ? 0x0c000000 : 0x08000000);
12938 exp
.X_op
= O_symbol
;
12939 exp
.X_add_symbol
= fragp
->fr_symbol
;
12940 exp
.X_add_number
= fragp
->fr_offset
;
12942 fixp
= fix_new_exp (fragp
, buf
- (bfd_byte
*)fragp
->fr_literal
,
12943 4, &exp
, 0, BFD_RELOC_MIPS_JMP
);
12944 fixp
->fx_file
= fragp
->fr_file
;
12945 fixp
->fx_line
= fragp
->fr_line
;
12947 md_number_to_chars ((char *) buf
, insn
, 4);
12952 /* lw/ld $at, <sym>($gp) R_MIPS_GOT16 */
12953 insn
= HAVE_64BIT_ADDRESSES
? 0xdf810000 : 0x8f810000;
12954 exp
.X_op
= O_symbol
;
12955 exp
.X_add_symbol
= fragp
->fr_symbol
;
12956 exp
.X_add_number
= fragp
->fr_offset
;
12958 if (fragp
->fr_offset
)
12960 exp
.X_add_symbol
= make_expr_symbol (&exp
);
12961 exp
.X_add_number
= 0;
12964 fixp
= fix_new_exp (fragp
, buf
- (bfd_byte
*)fragp
->fr_literal
,
12965 4, &exp
, 0, BFD_RELOC_MIPS_GOT16
);
12966 fixp
->fx_file
= fragp
->fr_file
;
12967 fixp
->fx_line
= fragp
->fr_line
;
12969 md_number_to_chars ((char *) buf
, insn
, 4);
12972 if (mips_opts
.isa
== ISA_MIPS1
)
12975 md_number_to_chars ((char *) buf
, 0, 4);
12979 /* d/addiu $at, $at, <sym> R_MIPS_LO16 */
12980 insn
= HAVE_64BIT_ADDRESSES
? 0x64210000 : 0x24210000;
12982 fixp
= fix_new_exp (fragp
, buf
- (bfd_byte
*)fragp
->fr_literal
,
12983 4, &exp
, 0, BFD_RELOC_LO16
);
12984 fixp
->fx_file
= fragp
->fr_file
;
12985 fixp
->fx_line
= fragp
->fr_line
;
12987 md_number_to_chars ((char *) buf
, insn
, 4);
12991 if (RELAX_BRANCH_LINK (fragp
->fr_subtype
))
12996 md_number_to_chars ((char *) buf
, insn
, 4);
13001 assert (buf
== (bfd_byte
*)fragp
->fr_literal
13002 + fragp
->fr_fix
+ fragp
->fr_var
);
13004 fragp
->fr_fix
+= fragp
->fr_var
;
13009 if (RELAX_MIPS16_P (fragp
->fr_subtype
))
13012 register const struct mips16_immed_operand
*op
;
13013 bfd_boolean small
, ext
;
13016 unsigned long insn
;
13017 bfd_boolean use_extend
;
13018 unsigned short extend
;
13020 type
= RELAX_MIPS16_TYPE (fragp
->fr_subtype
);
13021 op
= mips16_immed_operands
;
13022 while (op
->type
!= type
)
13025 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
13036 resolve_symbol_value (fragp
->fr_symbol
);
13037 val
= S_GET_VALUE (fragp
->fr_symbol
);
13042 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
13044 /* The rules for the base address of a PC relative reloc are
13045 complicated; see mips16_extended_frag. */
13046 if (type
== 'p' || type
== 'q')
13051 /* Ignore the low bit in the target, since it will be
13052 set for a text label. */
13053 if ((val
& 1) != 0)
13056 else if (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
))
13058 else if (RELAX_MIPS16_DSLOT (fragp
->fr_subtype
))
13061 addr
&= ~ (addressT
) ((1 << op
->shift
) - 1);
13064 /* Make sure the section winds up with the alignment we have
13067 record_alignment (asec
, op
->shift
);
13071 && (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
)
13072 || RELAX_MIPS16_DSLOT (fragp
->fr_subtype
)))
13073 as_warn_where (fragp
->fr_file
, fragp
->fr_line
,
13074 _("extended instruction in delay slot"));
13076 buf
= (bfd_byte
*) (fragp
->fr_literal
+ fragp
->fr_fix
);
13078 if (target_big_endian
)
13079 insn
= bfd_getb16 (buf
);
13081 insn
= bfd_getl16 (buf
);
13083 mips16_immed (fragp
->fr_file
, fragp
->fr_line
, type
, val
,
13084 RELAX_MIPS16_USER_EXT (fragp
->fr_subtype
),
13085 small
, ext
, &insn
, &use_extend
, &extend
);
13089 md_number_to_chars ((char *) buf
, 0xf000 | extend
, 2);
13090 fragp
->fr_fix
+= 2;
13094 md_number_to_chars ((char *) buf
, insn
, 2);
13095 fragp
->fr_fix
+= 2;
13103 first
= RELAX_FIRST (fragp
->fr_subtype
);
13104 second
= RELAX_SECOND (fragp
->fr_subtype
);
13105 fixp
= (fixS
*) fragp
->fr_opcode
;
13107 /* Possibly emit a warning if we've chosen the longer option. */
13108 if (((fragp
->fr_subtype
& RELAX_USE_SECOND
) != 0)
13109 == ((fragp
->fr_subtype
& RELAX_SECOND_LONGER
) != 0))
13111 const char *msg
= macro_warning (fragp
->fr_subtype
);
13113 as_warn_where (fragp
->fr_file
, fragp
->fr_line
, msg
);
13116 /* Go through all the fixups for the first sequence. Disable them
13117 (by marking them as done) if we're going to use the second
13118 sequence instead. */
13120 && fixp
->fx_frag
== fragp
13121 && fixp
->fx_where
< fragp
->fr_fix
- second
)
13123 if (fragp
->fr_subtype
& RELAX_USE_SECOND
)
13125 fixp
= fixp
->fx_next
;
13128 /* Go through the fixups for the second sequence. Disable them if
13129 we're going to use the first sequence, otherwise adjust their
13130 addresses to account for the relaxation. */
13131 while (fixp
&& fixp
->fx_frag
== fragp
)
13133 if (fragp
->fr_subtype
& RELAX_USE_SECOND
)
13134 fixp
->fx_where
-= first
;
13137 fixp
= fixp
->fx_next
;
13140 /* Now modify the frag contents. */
13141 if (fragp
->fr_subtype
& RELAX_USE_SECOND
)
13145 start
= fragp
->fr_literal
+ fragp
->fr_fix
- first
- second
;
13146 memmove (start
, start
+ first
, second
);
13147 fragp
->fr_fix
-= first
;
13150 fragp
->fr_fix
-= second
;
13156 /* This function is called after the relocs have been generated.
13157 We've been storing mips16 text labels as odd. Here we convert them
13158 back to even for the convenience of the debugger. */
13161 mips_frob_file_after_relocs (void)
13164 unsigned int count
, i
;
13166 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
13169 syms
= bfd_get_outsymbols (stdoutput
);
13170 count
= bfd_get_symcount (stdoutput
);
13171 for (i
= 0; i
< count
; i
++, syms
++)
13173 if (elf_symbol (*syms
)->internal_elf_sym
.st_other
== STO_MIPS16
13174 && ((*syms
)->value
& 1) != 0)
13176 (*syms
)->value
&= ~1;
13177 /* If the symbol has an odd size, it was probably computed
13178 incorrectly, so adjust that as well. */
13179 if ((elf_symbol (*syms
)->internal_elf_sym
.st_size
& 1) != 0)
13180 ++elf_symbol (*syms
)->internal_elf_sym
.st_size
;
13187 /* This function is called whenever a label is defined. It is used
13188 when handling branch delays; if a branch has a label, we assume we
13189 can not move it. */
13192 mips_define_label (symbolS
*sym
)
13194 struct insn_label_list
*l
;
13196 if (free_insn_labels
== NULL
)
13197 l
= (struct insn_label_list
*) xmalloc (sizeof *l
);
13200 l
= free_insn_labels
;
13201 free_insn_labels
= l
->next
;
13205 l
->next
= insn_labels
;
13209 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13211 /* Some special processing for a MIPS ELF file. */
13214 mips_elf_final_processing (void)
13216 /* Write out the register information. */
13217 if (mips_abi
!= N64_ABI
)
13221 s
.ri_gprmask
= mips_gprmask
;
13222 s
.ri_cprmask
[0] = mips_cprmask
[0];
13223 s
.ri_cprmask
[1] = mips_cprmask
[1];
13224 s
.ri_cprmask
[2] = mips_cprmask
[2];
13225 s
.ri_cprmask
[3] = mips_cprmask
[3];
13226 /* The gp_value field is set by the MIPS ELF backend. */
13228 bfd_mips_elf32_swap_reginfo_out (stdoutput
, &s
,
13229 ((Elf32_External_RegInfo
*)
13230 mips_regmask_frag
));
13234 Elf64_Internal_RegInfo s
;
13236 s
.ri_gprmask
= mips_gprmask
;
13238 s
.ri_cprmask
[0] = mips_cprmask
[0];
13239 s
.ri_cprmask
[1] = mips_cprmask
[1];
13240 s
.ri_cprmask
[2] = mips_cprmask
[2];
13241 s
.ri_cprmask
[3] = mips_cprmask
[3];
13242 /* The gp_value field is set by the MIPS ELF backend. */
13244 bfd_mips_elf64_swap_reginfo_out (stdoutput
, &s
,
13245 ((Elf64_External_RegInfo
*)
13246 mips_regmask_frag
));
13249 /* Set the MIPS ELF flag bits. FIXME: There should probably be some
13250 sort of BFD interface for this. */
13251 if (mips_any_noreorder
)
13252 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_NOREORDER
;
13253 if (mips_pic
!= NO_PIC
)
13255 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_PIC
;
13256 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_CPIC
;
13259 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_CPIC
;
13261 /* Set MIPS ELF flags for ASEs. */
13262 if (file_ase_mips16
)
13263 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ARCH_ASE_M16
;
13264 #if 0 /* XXX FIXME */
13265 if (file_ase_mips3d
)
13266 elf_elfheader (stdoutput
)->e_flags
|= ???;
13269 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ARCH_ASE_MDMX
;
13271 /* Set the MIPS ELF ABI flags. */
13272 if (mips_abi
== O32_ABI
&& USE_E_MIPS_ABI_O32
)
13273 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_O32
;
13274 else if (mips_abi
== O64_ABI
)
13275 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_O64
;
13276 else if (mips_abi
== EABI_ABI
)
13278 if (!file_mips_gp32
)
13279 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_EABI64
;
13281 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_EABI32
;
13283 else if (mips_abi
== N32_ABI
)
13284 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ABI2
;
13286 /* Nothing to do for N64_ABI. */
13288 if (mips_32bitmode
)
13289 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_32BITMODE
;
13292 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */
13294 typedef struct proc
{
13296 symbolS
*func_end_sym
;
13297 unsigned long reg_mask
;
13298 unsigned long reg_offset
;
13299 unsigned long fpreg_mask
;
13300 unsigned long fpreg_offset
;
13301 unsigned long frame_offset
;
13302 unsigned long frame_reg
;
13303 unsigned long pc_reg
;
13306 static procS cur_proc
;
13307 static procS
*cur_proc_ptr
;
13308 static int numprocs
;
13310 /* Fill in an rs_align_code fragment. */
13313 mips_handle_align (fragS
*fragp
)
13315 if (fragp
->fr_type
!= rs_align_code
)
13318 if (mips_opts
.mips16
)
13320 static const unsigned char be_nop
[] = { 0x65, 0x00 };
13321 static const unsigned char le_nop
[] = { 0x00, 0x65 };
13326 bytes
= fragp
->fr_next
->fr_address
- fragp
->fr_address
- fragp
->fr_fix
;
13327 p
= fragp
->fr_literal
+ fragp
->fr_fix
;
13335 memcpy (p
, (target_big_endian
? be_nop
: le_nop
), 2);
13339 /* For mips32, a nop is a zero, which we trivially get by doing nothing. */
13343 md_obj_begin (void)
13350 /* check for premature end, nesting errors, etc */
13352 as_warn (_("missing .end at end of assembly"));
13361 if (*input_line_pointer
== '-')
13363 ++input_line_pointer
;
13366 if (!ISDIGIT (*input_line_pointer
))
13367 as_bad (_("expected simple number"));
13368 if (input_line_pointer
[0] == '0')
13370 if (input_line_pointer
[1] == 'x')
13372 input_line_pointer
+= 2;
13373 while (ISXDIGIT (*input_line_pointer
))
13376 val
|= hex_value (*input_line_pointer
++);
13378 return negative
? -val
: val
;
13382 ++input_line_pointer
;
13383 while (ISDIGIT (*input_line_pointer
))
13386 val
|= *input_line_pointer
++ - '0';
13388 return negative
? -val
: val
;
13391 if (!ISDIGIT (*input_line_pointer
))
13393 printf (_(" *input_line_pointer == '%c' 0x%02x\n"),
13394 *input_line_pointer
, *input_line_pointer
);
13395 as_warn (_("invalid number"));
13398 while (ISDIGIT (*input_line_pointer
))
13401 val
+= *input_line_pointer
++ - '0';
13403 return negative
? -val
: val
;
13406 /* The .file directive; just like the usual .file directive, but there
13407 is an initial number which is the ECOFF file index. In the non-ECOFF
13408 case .file implies DWARF-2. */
13411 s_mips_file (int x ATTRIBUTE_UNUSED
)
13413 static int first_file_directive
= 0;
13415 if (ECOFF_DEBUGGING
)
13424 filename
= dwarf2_directive_file (0);
13426 /* Versions of GCC up to 3.1 start files with a ".file"
13427 directive even for stabs output. Make sure that this
13428 ".file" is handled. Note that you need a version of GCC
13429 after 3.1 in order to support DWARF-2 on MIPS. */
13430 if (filename
!= NULL
&& ! first_file_directive
)
13432 (void) new_logical_line (filename
, -1);
13433 s_app_file_string (filename
, 0);
13435 first_file_directive
= 1;
13439 /* The .loc directive, implying DWARF-2. */
13442 s_mips_loc (int x ATTRIBUTE_UNUSED
)
13444 if (!ECOFF_DEBUGGING
)
13445 dwarf2_directive_loc (0);
13448 /* The .end directive. */
13451 s_mips_end (int x ATTRIBUTE_UNUSED
)
13455 /* Following functions need their own .frame and .cprestore directives. */
13456 mips_frame_reg_valid
= 0;
13457 mips_cprestore_valid
= 0;
13459 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
13462 demand_empty_rest_of_line ();
13467 if ((bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) == 0)
13468 as_warn (_(".end not in text section"));
13472 as_warn (_(".end directive without a preceding .ent directive."));
13473 demand_empty_rest_of_line ();
13479 assert (S_GET_NAME (p
));
13480 if (strcmp (S_GET_NAME (p
), S_GET_NAME (cur_proc_ptr
->func_sym
)))
13481 as_warn (_(".end symbol does not match .ent symbol."));
13483 if (debug_type
== DEBUG_STABS
)
13484 stabs_generate_asm_endfunc (S_GET_NAME (p
),
13488 as_warn (_(".end directive missing or unknown symbol"));
13491 /* Create an expression to calculate the size of the function. */
13492 if (p
&& cur_proc_ptr
)
13494 OBJ_SYMFIELD_TYPE
*obj
= symbol_get_obj (p
);
13495 expressionS
*exp
= xmalloc (sizeof (expressionS
));
13498 exp
->X_op
= O_subtract
;
13499 exp
->X_add_symbol
= symbol_temp_new_now ();
13500 exp
->X_op_symbol
= p
;
13501 exp
->X_add_number
= 0;
13503 cur_proc_ptr
->func_end_sym
= exp
->X_add_symbol
;
13506 /* Generate a .pdr section. */
13507 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
&& ! ECOFF_DEBUGGING
13510 segT saved_seg
= now_seg
;
13511 subsegT saved_subseg
= now_subseg
;
13516 dot
= frag_now_fix ();
13518 #ifdef md_flush_pending_output
13519 md_flush_pending_output ();
13523 subseg_set (pdr_seg
, 0);
13525 /* Write the symbol. */
13526 exp
.X_op
= O_symbol
;
13527 exp
.X_add_symbol
= p
;
13528 exp
.X_add_number
= 0;
13529 emit_expr (&exp
, 4);
13531 fragp
= frag_more (7 * 4);
13533 md_number_to_chars (fragp
, cur_proc_ptr
->reg_mask
, 4);
13534 md_number_to_chars (fragp
+ 4, cur_proc_ptr
->reg_offset
, 4);
13535 md_number_to_chars (fragp
+ 8, cur_proc_ptr
->fpreg_mask
, 4);
13536 md_number_to_chars (fragp
+ 12, cur_proc_ptr
->fpreg_offset
, 4);
13537 md_number_to_chars (fragp
+ 16, cur_proc_ptr
->frame_offset
, 4);
13538 md_number_to_chars (fragp
+ 20, cur_proc_ptr
->frame_reg
, 4);
13539 md_number_to_chars (fragp
+ 24, cur_proc_ptr
->pc_reg
, 4);
13541 subseg_set (saved_seg
, saved_subseg
);
13543 #endif /* OBJ_ELF */
13545 cur_proc_ptr
= NULL
;
13548 /* The .aent and .ent directives. */
13551 s_mips_ent (int aent
)
13555 symbolP
= get_symbol ();
13556 if (*input_line_pointer
== ',')
13557 ++input_line_pointer
;
13558 SKIP_WHITESPACE ();
13559 if (ISDIGIT (*input_line_pointer
)
13560 || *input_line_pointer
== '-')
13563 if ((bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) == 0)
13564 as_warn (_(".ent or .aent not in text section."));
13566 if (!aent
&& cur_proc_ptr
)
13567 as_warn (_("missing .end"));
13571 /* This function needs its own .frame and .cprestore directives. */
13572 mips_frame_reg_valid
= 0;
13573 mips_cprestore_valid
= 0;
13575 cur_proc_ptr
= &cur_proc
;
13576 memset (cur_proc_ptr
, '\0', sizeof (procS
));
13578 cur_proc_ptr
->func_sym
= symbolP
;
13580 symbol_get_bfdsym (symbolP
)->flags
|= BSF_FUNCTION
;
13584 if (debug_type
== DEBUG_STABS
)
13585 stabs_generate_asm_func (S_GET_NAME (symbolP
),
13586 S_GET_NAME (symbolP
));
13589 demand_empty_rest_of_line ();
13592 /* The .frame directive. If the mdebug section is present (IRIX 5 native)
13593 then ecoff.c (ecoff_directive_frame) is used. For embedded targets,
13594 s_mips_frame is used so that we can set the PDR information correctly.
13595 We can't use the ecoff routines because they make reference to the ecoff
13596 symbol table (in the mdebug section). */
13599 s_mips_frame (int ignore ATTRIBUTE_UNUSED
)
13602 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
&& ! ECOFF_DEBUGGING
)
13606 if (cur_proc_ptr
== (procS
*) NULL
)
13608 as_warn (_(".frame outside of .ent"));
13609 demand_empty_rest_of_line ();
13613 cur_proc_ptr
->frame_reg
= tc_get_register (1);
13615 SKIP_WHITESPACE ();
13616 if (*input_line_pointer
++ != ','
13617 || get_absolute_expression_and_terminator (&val
) != ',')
13619 as_warn (_("Bad .frame directive"));
13620 --input_line_pointer
;
13621 demand_empty_rest_of_line ();
13625 cur_proc_ptr
->frame_offset
= val
;
13626 cur_proc_ptr
->pc_reg
= tc_get_register (0);
13628 demand_empty_rest_of_line ();
13631 #endif /* OBJ_ELF */
13635 /* The .fmask and .mask directives. If the mdebug section is present
13636 (IRIX 5 native) then ecoff.c (ecoff_directive_mask) is used. For
13637 embedded targets, s_mips_mask is used so that we can set the PDR
13638 information correctly. We can't use the ecoff routines because they
13639 make reference to the ecoff symbol table (in the mdebug section). */
13642 s_mips_mask (int reg_type
)
13645 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
&& ! ECOFF_DEBUGGING
)
13649 if (cur_proc_ptr
== (procS
*) NULL
)
13651 as_warn (_(".mask/.fmask outside of .ent"));
13652 demand_empty_rest_of_line ();
13656 if (get_absolute_expression_and_terminator (&mask
) != ',')
13658 as_warn (_("Bad .mask/.fmask directive"));
13659 --input_line_pointer
;
13660 demand_empty_rest_of_line ();
13664 off
= get_absolute_expression ();
13666 if (reg_type
== 'F')
13668 cur_proc_ptr
->fpreg_mask
= mask
;
13669 cur_proc_ptr
->fpreg_offset
= off
;
13673 cur_proc_ptr
->reg_mask
= mask
;
13674 cur_proc_ptr
->reg_offset
= off
;
13677 demand_empty_rest_of_line ();
13680 #endif /* OBJ_ELF */
13681 s_ignore (reg_type
);
13684 /* A table describing all the processors gas knows about. Names are
13685 matched in the order listed.
13687 To ease comparison, please keep this table in the same order as
13688 gcc's mips_cpu_info_table[]. */
13689 static const struct mips_cpu_info mips_cpu_info_table
[] =
13691 /* Entries for generic ISAs */
13692 { "mips1", 1, ISA_MIPS1
, CPU_R3000
},
13693 { "mips2", 1, ISA_MIPS2
, CPU_R6000
},
13694 { "mips3", 1, ISA_MIPS3
, CPU_R4000
},
13695 { "mips4", 1, ISA_MIPS4
, CPU_R8000
},
13696 { "mips5", 1, ISA_MIPS5
, CPU_MIPS5
},
13697 { "mips32", 1, ISA_MIPS32
, CPU_MIPS32
},
13698 { "mips32r2", 1, ISA_MIPS32R2
, CPU_MIPS32R2
},
13699 { "mips64", 1, ISA_MIPS64
, CPU_MIPS64
},
13700 { "mips64r2", 1, ISA_MIPS64R2
, CPU_MIPS64R2
},
13703 { "r3000", 0, ISA_MIPS1
, CPU_R3000
},
13704 { "r2000", 0, ISA_MIPS1
, CPU_R3000
},
13705 { "r3900", 0, ISA_MIPS1
, CPU_R3900
},
13708 { "r6000", 0, ISA_MIPS2
, CPU_R6000
},
13711 { "r4000", 0, ISA_MIPS3
, CPU_R4000
},
13712 { "r4010", 0, ISA_MIPS2
, CPU_R4010
},
13713 { "vr4100", 0, ISA_MIPS3
, CPU_VR4100
},
13714 { "vr4111", 0, ISA_MIPS3
, CPU_R4111
},
13715 { "vr4120", 0, ISA_MIPS3
, CPU_VR4120
},
13716 { "vr4130", 0, ISA_MIPS3
, CPU_VR4120
},
13717 { "vr4181", 0, ISA_MIPS3
, CPU_R4111
},
13718 { "vr4300", 0, ISA_MIPS3
, CPU_R4300
},
13719 { "r4400", 0, ISA_MIPS3
, CPU_R4400
},
13720 { "r4600", 0, ISA_MIPS3
, CPU_R4600
},
13721 { "orion", 0, ISA_MIPS3
, CPU_R4600
},
13722 { "r4650", 0, ISA_MIPS3
, CPU_R4650
},
13725 { "r8000", 0, ISA_MIPS4
, CPU_R8000
},
13726 { "r10000", 0, ISA_MIPS4
, CPU_R10000
},
13727 { "r12000", 0, ISA_MIPS4
, CPU_R12000
},
13728 { "vr5000", 0, ISA_MIPS4
, CPU_R5000
},
13729 { "vr5400", 0, ISA_MIPS4
, CPU_VR5400
},
13730 { "vr5500", 0, ISA_MIPS4
, CPU_VR5500
},
13731 { "rm5200", 0, ISA_MIPS4
, CPU_R5000
},
13732 { "rm5230", 0, ISA_MIPS4
, CPU_R5000
},
13733 { "rm5231", 0, ISA_MIPS4
, CPU_R5000
},
13734 { "rm5261", 0, ISA_MIPS4
, CPU_R5000
},
13735 { "rm5721", 0, ISA_MIPS4
, CPU_R5000
},
13736 { "rm7000", 0, ISA_MIPS4
, CPU_RM7000
},
13737 { "rm9000", 0, ISA_MIPS4
, CPU_RM9000
},
13740 { "4kc", 0, ISA_MIPS32
, CPU_MIPS32
},
13741 { "4km", 0, ISA_MIPS32
, CPU_MIPS32
},
13742 { "4kp", 0, ISA_MIPS32
, CPU_MIPS32
},
13745 { "5kc", 0, ISA_MIPS64
, CPU_MIPS64
},
13746 { "20kc", 0, ISA_MIPS64
, CPU_MIPS64
},
13748 /* Broadcom SB-1 CPU core */
13749 { "sb1", 0, ISA_MIPS64
, CPU_SB1
},
13756 /* Return true if GIVEN is the same as CANONICAL, or if it is CANONICAL
13757 with a final "000" replaced by "k". Ignore case.
13759 Note: this function is shared between GCC and GAS. */
13762 mips_strict_matching_cpu_name_p (const char *canonical
, const char *given
)
13764 while (*given
!= 0 && TOLOWER (*given
) == TOLOWER (*canonical
))
13765 given
++, canonical
++;
13767 return ((*given
== 0 && *canonical
== 0)
13768 || (strcmp (canonical
, "000") == 0 && strcasecmp (given
, "k") == 0));
13772 /* Return true if GIVEN matches CANONICAL, where GIVEN is a user-supplied
13773 CPU name. We've traditionally allowed a lot of variation here.
13775 Note: this function is shared between GCC and GAS. */
13778 mips_matching_cpu_name_p (const char *canonical
, const char *given
)
13780 /* First see if the name matches exactly, or with a final "000"
13781 turned into "k". */
13782 if (mips_strict_matching_cpu_name_p (canonical
, given
))
13785 /* If not, try comparing based on numerical designation alone.
13786 See if GIVEN is an unadorned number, or 'r' followed by a number. */
13787 if (TOLOWER (*given
) == 'r')
13789 if (!ISDIGIT (*given
))
13792 /* Skip over some well-known prefixes in the canonical name,
13793 hoping to find a number there too. */
13794 if (TOLOWER (canonical
[0]) == 'v' && TOLOWER (canonical
[1]) == 'r')
13796 else if (TOLOWER (canonical
[0]) == 'r' && TOLOWER (canonical
[1]) == 'm')
13798 else if (TOLOWER (canonical
[0]) == 'r')
13801 return mips_strict_matching_cpu_name_p (canonical
, given
);
13805 /* Parse an option that takes the name of a processor as its argument.
13806 OPTION is the name of the option and CPU_STRING is the argument.
13807 Return the corresponding processor enumeration if the CPU_STRING is
13808 recognized, otherwise report an error and return null.
13810 A similar function exists in GCC. */
13812 static const struct mips_cpu_info
*
13813 mips_parse_cpu (const char *option
, const char *cpu_string
)
13815 const struct mips_cpu_info
*p
;
13817 /* 'from-abi' selects the most compatible architecture for the given
13818 ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit ABIs. For the
13819 EABIs, we have to decide whether we're using the 32-bit or 64-bit
13820 version. Look first at the -mgp options, if given, otherwise base
13821 the choice on MIPS_DEFAULT_64BIT.
13823 Treat NO_ABI like the EABIs. One reason to do this is that the
13824 plain 'mips' and 'mips64' configs have 'from-abi' as their default
13825 architecture. This code picks MIPS I for 'mips' and MIPS III for
13826 'mips64', just as we did in the days before 'from-abi'. */
13827 if (strcasecmp (cpu_string
, "from-abi") == 0)
13829 if (ABI_NEEDS_32BIT_REGS (mips_abi
))
13830 return mips_cpu_info_from_isa (ISA_MIPS1
);
13832 if (ABI_NEEDS_64BIT_REGS (mips_abi
))
13833 return mips_cpu_info_from_isa (ISA_MIPS3
);
13835 if (file_mips_gp32
>= 0)
13836 return mips_cpu_info_from_isa (file_mips_gp32
? ISA_MIPS1
: ISA_MIPS3
);
13838 return mips_cpu_info_from_isa (MIPS_DEFAULT_64BIT
13843 /* 'default' has traditionally been a no-op. Probably not very useful. */
13844 if (strcasecmp (cpu_string
, "default") == 0)
13847 for (p
= mips_cpu_info_table
; p
->name
!= 0; p
++)
13848 if (mips_matching_cpu_name_p (p
->name
, cpu_string
))
13851 as_bad ("Bad value (%s) for %s", cpu_string
, option
);
13855 /* Return the canonical processor information for ISA (a member of the
13856 ISA_MIPS* enumeration). */
13858 static const struct mips_cpu_info
*
13859 mips_cpu_info_from_isa (int isa
)
13863 for (i
= 0; mips_cpu_info_table
[i
].name
!= NULL
; i
++)
13864 if (mips_cpu_info_table
[i
].is_isa
13865 && isa
== mips_cpu_info_table
[i
].isa
)
13866 return (&mips_cpu_info_table
[i
]);
13871 static const struct mips_cpu_info
*
13872 mips_cpu_info_from_arch (int arch
)
13876 for (i
= 0; mips_cpu_info_table
[i
].name
!= NULL
; i
++)
13877 if (arch
== mips_cpu_info_table
[i
].cpu
)
13878 return (&mips_cpu_info_table
[i
]);
13884 show (FILE *stream
, const char *string
, int *col_p
, int *first_p
)
13888 fprintf (stream
, "%24s", "");
13893 fprintf (stream
, ", ");
13897 if (*col_p
+ strlen (string
) > 72)
13899 fprintf (stream
, "\n%24s", "");
13903 fprintf (stream
, "%s", string
);
13904 *col_p
+= strlen (string
);
13910 md_show_usage (FILE *stream
)
13915 fprintf (stream
, _("\
13917 -EB generate big endian output\n\
13918 -EL generate little endian output\n\
13919 -g, -g2 do not remove unneeded NOPs or swap branches\n\
13920 -G NUM allow referencing objects up to NUM bytes\n\
13921 implicitly with the gp register [default 8]\n"));
13922 fprintf (stream
, _("\
13923 -mips1 generate MIPS ISA I instructions\n\
13924 -mips2 generate MIPS ISA II instructions\n\
13925 -mips3 generate MIPS ISA III instructions\n\
13926 -mips4 generate MIPS ISA IV instructions\n\
13927 -mips5 generate MIPS ISA V instructions\n\
13928 -mips32 generate MIPS32 ISA instructions\n\
13929 -mips32r2 generate MIPS32 release 2 ISA instructions\n\
13930 -mips64 generate MIPS64 ISA instructions\n\
13931 -mips64r2 generate MIPS64 release 2 ISA instructions\n\
13932 -march=CPU/-mtune=CPU generate code/schedule for CPU, where CPU is one of:\n"));
13936 for (i
= 0; mips_cpu_info_table
[i
].name
!= NULL
; i
++)
13937 show (stream
, mips_cpu_info_table
[i
].name
, &column
, &first
);
13938 show (stream
, "from-abi", &column
, &first
);
13939 fputc ('\n', stream
);
13941 fprintf (stream
, _("\
13942 -mCPU equivalent to -march=CPU -mtune=CPU. Deprecated.\n\
13943 -no-mCPU don't generate code specific to CPU.\n\
13944 For -mCPU and -no-mCPU, CPU must be one of:\n"));
13948 show (stream
, "3900", &column
, &first
);
13949 show (stream
, "4010", &column
, &first
);
13950 show (stream
, "4100", &column
, &first
);
13951 show (stream
, "4650", &column
, &first
);
13952 fputc ('\n', stream
);
13954 fprintf (stream
, _("\
13955 -mips16 generate mips16 instructions\n\
13956 -no-mips16 do not generate mips16 instructions\n"));
13957 fprintf (stream
, _("\
13958 -mfix-vr4120 work around certain VR4120 errata\n\
13959 -mfix-vr4130 work around VR4130 mflo/mfhi errata\n\
13960 -mgp32 use 32-bit GPRs, regardless of the chosen ISA\n\
13961 -mfp32 use 32-bit FPRs, regardless of the chosen ISA\n\
13962 -mno-shared optimize output for executables\n\
13963 -msym32 assume all symbols have 32-bit values\n\
13964 -O0 remove unneeded NOPs, do not swap branches\n\
13965 -O remove unneeded NOPs and swap branches\n\
13966 --[no-]construct-floats [dis]allow floating point values to be constructed\n\
13967 --trap, --no-break trap exception on div by 0 and mult overflow\n\
13968 --break, --no-trap break exception on div by 0 and mult overflow\n"));
13970 fprintf (stream
, _("\
13971 -KPIC, -call_shared generate SVR4 position independent code\n\
13972 -non_shared do not generate position independent code\n\
13973 -xgot assume a 32 bit GOT\n\
13974 -mpdr, -mno-pdr enable/disable creation of .pdr sections\n\
13975 -mshared, -mno-shared disable/enable .cpload optimization for\n\
13977 -mabi=ABI create ABI conformant object file for:\n"));
13981 show (stream
, "32", &column
, &first
);
13982 show (stream
, "o64", &column
, &first
);
13983 show (stream
, "n32", &column
, &first
);
13984 show (stream
, "64", &column
, &first
);
13985 show (stream
, "eabi", &column
, &first
);
13987 fputc ('\n', stream
);
13989 fprintf (stream
, _("\
13990 -32 create o32 ABI object file (default)\n\
13991 -n32 create n32 ABI object file\n\
13992 -64 create 64 ABI object file\n"));
13997 mips_dwarf2_format (void)
13999 if (mips_abi
== N64_ABI
)
14002 return dwarf2_format_64bit_irix
;
14004 return dwarf2_format_64bit
;
14008 return dwarf2_format_32bit
;
14012 mips_dwarf2_addr_size (void)
14014 if (mips_abi
== N64_ABI
)