1 /* tc-mips.c -- assemble code for a MIPS chip.
2 Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,
3 2003, 2004, 2005 Free Software Foundation, Inc.
4 Contributed by the OSF and Ralph Campbell.
5 Written by Keith Knowles and Ralph Campbell, working independently.
6 Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus
9 This file is part of GAS.
11 GAS is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 2, or (at your option)
16 GAS is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
21 You should have received a copy of the GNU General Public License
22 along with GAS; see the file COPYING. If not, write to the Free
23 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
29 #include "safe-ctype.h"
33 #include "opcode/mips.h"
35 #include "dwarf2dbg.h"
38 #define DBG(x) printf x
44 /* Clean up namespace so we can include obj-elf.h too. */
45 static int mips_output_flavor (void);
46 static int mips_output_flavor (void) { return OUTPUT_FLAVOR
; }
47 #undef OBJ_PROCESS_STAB
54 #undef obj_frob_file_after_relocs
55 #undef obj_frob_symbol
57 #undef obj_sec_sym_ok_for_reloc
58 #undef OBJ_COPY_SYMBOL_ATTRIBUTES
61 /* Fix any of them that we actually care about. */
63 #define OUTPUT_FLAVOR mips_output_flavor()
70 #ifndef ECOFF_DEBUGGING
71 #define NO_ECOFF_DEBUGGING
72 #define ECOFF_DEBUGGING 0
75 int mips_flag_mdebug
= -1;
77 /* Control generation of .pdr sections. Off by default on IRIX: the native
78 linker doesn't know about and discards them, but relocations against them
79 remain, leading to rld crashes. */
81 int mips_flag_pdr
= FALSE
;
83 int mips_flag_pdr
= TRUE
;
88 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
89 static char *mips_regmask_frag
;
95 #define PIC_CALL_REG 25
103 #define ILLEGAL_REG (32)
105 /* Allow override of standard little-endian ECOFF format. */
107 #ifndef ECOFF_LITTLE_FORMAT
108 #define ECOFF_LITTLE_FORMAT "ecoff-littlemips"
111 extern int target_big_endian
;
113 /* The name of the readonly data section. */
114 #define RDATA_SECTION_NAME (OUTPUT_FLAVOR == bfd_target_ecoff_flavour \
116 : OUTPUT_FLAVOR == bfd_target_coff_flavour \
118 : OUTPUT_FLAVOR == bfd_target_elf_flavour \
122 /* Information about an instruction, including its format, operands
126 /* The opcode's entry in mips_opcodes or mips16_opcodes. */
127 const struct mips_opcode
*insn_mo
;
129 /* True if this is a mips16 instruction and if we want the extended
131 bfd_boolean use_extend
;
133 /* The 16-bit extension instruction to use when USE_EXTEND is true. */
134 unsigned short extend
;
136 /* The 16-bit or 32-bit bitstring of the instruction itself. This is
137 a copy of INSN_MO->match with the operands filled in. */
138 unsigned long insn_opcode
;
140 /* The frag that contains the instruction. */
143 /* The offset into FRAG of the first instruction byte. */
146 /* The relocs associated with the instruction, if any. */
149 /* The reloc types associated with the instruction. */
150 bfd_reloc_code_real_type reloc_type
[3];
152 /* True if this entry describes a real instruction. */
153 unsigned int valid_p
: 1;
155 /* True if this instruction occured in a .set noreorder block. */
156 unsigned int noreorder_p
: 1;
158 /* True if this instruction corresponds to an assembler-filled
159 delay slot. Always false if noreorder_p. */
160 unsigned int delay_slot_p
: 1;
162 /* True for extended mips16 instructions. */
163 unsigned int extended_p
: 1;
166 /* The ABI to use. */
177 /* MIPS ABI we are using for this output file. */
178 static enum mips_abi_level mips_abi
= NO_ABI
;
180 /* Whether or not we have code that can call pic code. */
181 int mips_abicalls
= FALSE
;
183 /* Whether or not we have code which can be put into a shared
185 static bfd_boolean mips_in_shared
= TRUE
;
187 /* This is the set of options which may be modified by the .set
188 pseudo-op. We use a struct so that .set push and .set pop are more
191 struct mips_set_options
193 /* MIPS ISA (Instruction Set Architecture) level. This is set to -1
194 if it has not been initialized. Changed by `.set mipsN', and the
195 -mipsN command line option, and the default CPU. */
197 /* Enabled Application Specific Extensions (ASEs). These are set to -1
198 if they have not been initialized. Changed by `.set <asename>', by
199 command line options, and based on the default architecture. */
202 /* Whether we are assembling for the mips16 processor. 0 if we are
203 not, 1 if we are, and -1 if the value has not been initialized.
204 Changed by `.set mips16' and `.set nomips16', and the -mips16 and
205 -nomips16 command line options, and the default CPU. */
207 /* Non-zero if we should not reorder instructions. Changed by `.set
208 reorder' and `.set noreorder'. */
210 /* Non-zero if we should not permit the $at ($1) register to be used
211 in instructions. Changed by `.set at' and `.set noat'. */
213 /* Non-zero if we should warn when a macro instruction expands into
214 more than one machine instruction. Changed by `.set nomacro' and
216 int warn_about_macros
;
217 /* Non-zero if we should not move instructions. Changed by `.set
218 move', `.set volatile', `.set nomove', and `.set novolatile'. */
220 /* Non-zero if we should not optimize branches by moving the target
221 of the branch into the delay slot. Actually, we don't perform
222 this optimization anyhow. Changed by `.set bopt' and `.set
225 /* Non-zero if we should not autoextend mips16 instructions.
226 Changed by `.set autoextend' and `.set noautoextend'. */
228 /* Restrict general purpose registers and floating point registers
229 to 32 bit. This is initially determined when -mgp32 or -mfp32
230 is passed but can changed if the assembler code uses .set mipsN. */
233 /* MIPS architecture (CPU) type. Changed by .set arch=FOO, the -march
234 command line option, and the default CPU. */
236 /* True if ".set sym32" is in effect. */
240 /* True if -mgp32 was passed. */
241 static int file_mips_gp32
= -1;
243 /* True if -mfp32 was passed. */
244 static int file_mips_fp32
= -1;
246 /* This is the struct we use to hold the current set of options. Note
247 that we must set the isa field to ISA_UNKNOWN and the ASE fields to
248 -1 to indicate that they have not been initialized. */
250 static struct mips_set_options mips_opts
=
252 ISA_UNKNOWN
, -1, -1, -1, 0, 0, 0, 0, 0, 0, 0, 0, CPU_UNKNOWN
, FALSE
255 /* These variables are filled in with the masks of registers used.
256 The object format code reads them and puts them in the appropriate
258 unsigned long mips_gprmask
;
259 unsigned long mips_cprmask
[4];
261 /* MIPS ISA we are using for this output file. */
262 static int file_mips_isa
= ISA_UNKNOWN
;
264 /* True if -mips16 was passed or implied by arguments passed on the
265 command line (e.g., by -march). */
266 static int file_ase_mips16
;
268 /* True if -mips3d was passed or implied by arguments passed on the
269 command line (e.g., by -march). */
270 static int file_ase_mips3d
;
272 /* True if -mdmx was passed or implied by arguments passed on the
273 command line (e.g., by -march). */
274 static int file_ase_mdmx
;
276 /* The argument of the -march= flag. The architecture we are assembling. */
277 static int file_mips_arch
= CPU_UNKNOWN
;
278 static const char *mips_arch_string
;
280 /* The argument of the -mtune= flag. The architecture for which we
282 static int mips_tune
= CPU_UNKNOWN
;
283 static const char *mips_tune_string
;
285 /* True when generating 32-bit code for a 64-bit processor. */
286 static int mips_32bitmode
= 0;
288 /* True if the given ABI requires 32-bit registers. */
289 #define ABI_NEEDS_32BIT_REGS(ABI) ((ABI) == O32_ABI)
291 /* Likewise 64-bit registers. */
292 #define ABI_NEEDS_64BIT_REGS(ABI) \
294 || (ABI) == N64_ABI \
297 /* Return true if ISA supports 64 bit gp register instructions. */
298 #define ISA_HAS_64BIT_REGS(ISA) ( \
300 || (ISA) == ISA_MIPS4 \
301 || (ISA) == ISA_MIPS5 \
302 || (ISA) == ISA_MIPS64 \
303 || (ISA) == ISA_MIPS64R2 \
306 /* Return true if ISA supports 64-bit right rotate (dror et al.)
308 #define ISA_HAS_DROR(ISA) ( \
309 (ISA) == ISA_MIPS64R2 \
312 /* Return true if ISA supports 32-bit right rotate (ror et al.)
314 #define ISA_HAS_ROR(ISA) ( \
315 (ISA) == ISA_MIPS32R2 \
316 || (ISA) == ISA_MIPS64R2 \
319 #define HAVE_32BIT_GPRS \
320 (mips_opts.gp32 || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
322 #define HAVE_32BIT_FPRS \
323 (mips_opts.fp32 || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
325 #define HAVE_64BIT_GPRS (! HAVE_32BIT_GPRS)
326 #define HAVE_64BIT_FPRS (! HAVE_32BIT_FPRS)
328 #define HAVE_NEWABI (mips_abi == N32_ABI || mips_abi == N64_ABI)
330 #define HAVE_64BIT_OBJECTS (mips_abi == N64_ABI)
332 /* True if relocations are stored in-place. */
333 #define HAVE_IN_PLACE_ADDENDS (!HAVE_NEWABI)
335 /* The ABI-derived address size. */
336 #define HAVE_64BIT_ADDRESSES \
337 (HAVE_64BIT_GPRS && (mips_abi == EABI_ABI || mips_abi == N64_ABI))
338 #define HAVE_32BIT_ADDRESSES (!HAVE_64BIT_ADDRESSES)
340 /* The size of symbolic constants (i.e., expressions of the form
341 "SYMBOL" or "SYMBOL + OFFSET"). */
342 #define HAVE_32BIT_SYMBOLS \
343 (HAVE_32BIT_ADDRESSES || !HAVE_64BIT_OBJECTS || mips_opts.sym32)
344 #define HAVE_64BIT_SYMBOLS (!HAVE_32BIT_SYMBOLS)
346 /* Addresses are loaded in different ways, depending on the address size
347 in use. The n32 ABI Documentation also mandates the use of additions
348 with overflow checking, but existing implementations don't follow it. */
349 #define ADDRESS_ADD_INSN \
350 (HAVE_32BIT_ADDRESSES ? "addu" : "daddu")
352 #define ADDRESS_ADDI_INSN \
353 (HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu")
355 #define ADDRESS_LOAD_INSN \
356 (HAVE_32BIT_ADDRESSES ? "lw" : "ld")
358 #define ADDRESS_STORE_INSN \
359 (HAVE_32BIT_ADDRESSES ? "sw" : "sd")
361 /* Return true if the given CPU supports the MIPS16 ASE. */
362 #define CPU_HAS_MIPS16(cpu) \
363 (strncmp (TARGET_CPU, "mips16", sizeof ("mips16") - 1) == 0 \
364 || strncmp (TARGET_CANONICAL, "mips-lsi-elf", sizeof ("mips-lsi-elf") - 1) == 0)
366 /* Return true if the given CPU supports the MIPS3D ASE. */
367 #define CPU_HAS_MIPS3D(cpu) ((cpu) == CPU_SB1 \
370 /* Return true if the given CPU supports the MDMX ASE. */
371 #define CPU_HAS_MDMX(cpu) (FALSE \
374 /* True if CPU has a dror instruction. */
375 #define CPU_HAS_DROR(CPU) ((CPU) == CPU_VR5400 || (CPU) == CPU_VR5500)
377 /* True if CPU has a ror instruction. */
378 #define CPU_HAS_ROR(CPU) CPU_HAS_DROR (CPU)
380 /* True if mflo and mfhi can be immediately followed by instructions
381 which write to the HI and LO registers.
383 According to MIPS specifications, MIPS ISAs I, II, and III need
384 (at least) two instructions between the reads of HI/LO and
385 instructions which write them, and later ISAs do not. Contradicting
386 the MIPS specifications, some MIPS IV processor user manuals (e.g.
387 the UM for the NEC Vr5000) document needing the instructions between
388 HI/LO reads and writes, as well. Therefore, we declare only MIPS32,
389 MIPS64 and later ISAs to have the interlocks, plus any specific
390 earlier-ISA CPUs for which CPU documentation declares that the
391 instructions are really interlocked. */
392 #define hilo_interlocks \
393 (mips_opts.isa == ISA_MIPS32 \
394 || mips_opts.isa == ISA_MIPS32R2 \
395 || mips_opts.isa == ISA_MIPS64 \
396 || mips_opts.isa == ISA_MIPS64R2 \
397 || mips_opts.arch == CPU_R4010 \
398 || mips_opts.arch == CPU_R10000 \
399 || mips_opts.arch == CPU_R12000 \
400 || mips_opts.arch == CPU_RM7000 \
401 || mips_opts.arch == CPU_VR5500 \
404 /* Whether the processor uses hardware interlocks to protect reads
405 from the GPRs after they are loaded from memory, and thus does not
406 require nops to be inserted. This applies to instructions marked
407 INSN_LOAD_MEMORY_DELAY. These nops are only required at MIPS ISA
409 #define gpr_interlocks \
410 (mips_opts.isa != ISA_MIPS1 \
411 || mips_opts.arch == CPU_R3900)
413 /* Whether the processor uses hardware interlocks to avoid delays
414 required by coprocessor instructions, and thus does not require
415 nops to be inserted. This applies to instructions marked
416 INSN_LOAD_COPROC_DELAY, INSN_COPROC_MOVE_DELAY, and to delays
417 between instructions marked INSN_WRITE_COND_CODE and ones marked
418 INSN_READ_COND_CODE. These nops are only required at MIPS ISA
419 levels I, II, and III. */
420 /* Itbl support may require additional care here. */
421 #define cop_interlocks \
422 ((mips_opts.isa != ISA_MIPS1 \
423 && mips_opts.isa != ISA_MIPS2 \
424 && mips_opts.isa != ISA_MIPS3) \
425 || mips_opts.arch == CPU_R4300 \
428 /* Whether the processor uses hardware interlocks to protect reads
429 from coprocessor registers after they are loaded from memory, and
430 thus does not require nops to be inserted. This applies to
431 instructions marked INSN_COPROC_MEMORY_DELAY. These nops are only
432 requires at MIPS ISA level I. */
433 #define cop_mem_interlocks (mips_opts.isa != ISA_MIPS1)
435 /* Is this a mfhi or mflo instruction? */
436 #define MF_HILO_INSN(PINFO) \
437 ((PINFO & INSN_READ_HI) || (PINFO & INSN_READ_LO))
439 /* MIPS PIC level. */
441 enum mips_pic_level mips_pic
;
443 /* 1 if we should generate 32 bit offsets from the $gp register in
444 SVR4_PIC mode. Currently has no meaning in other modes. */
445 static int mips_big_got
= 0;
447 /* 1 if trap instructions should used for overflow rather than break
449 static int mips_trap
= 0;
451 /* 1 if double width floating point constants should not be constructed
452 by assembling two single width halves into two single width floating
453 point registers which just happen to alias the double width destination
454 register. On some architectures this aliasing can be disabled by a bit
455 in the status register, and the setting of this bit cannot be determined
456 automatically at assemble time. */
457 static int mips_disable_float_construction
;
459 /* Non-zero if any .set noreorder directives were used. */
461 static int mips_any_noreorder
;
463 /* Non-zero if nops should be inserted when the register referenced in
464 an mfhi/mflo instruction is read in the next two instructions. */
465 static int mips_7000_hilo_fix
;
467 /* The size of the small data section. */
468 static unsigned int g_switch_value
= 8;
469 /* Whether the -G option was used. */
470 static int g_switch_seen
= 0;
475 /* If we can determine in advance that GP optimization won't be
476 possible, we can skip the relaxation stuff that tries to produce
477 GP-relative references. This makes delay slot optimization work
480 This function can only provide a guess, but it seems to work for
481 gcc output. It needs to guess right for gcc, otherwise gcc
482 will put what it thinks is a GP-relative instruction in a branch
485 I don't know if a fix is needed for the SVR4_PIC mode. I've only
486 fixed it for the non-PIC mode. KR 95/04/07 */
487 static int nopic_need_relax (symbolS
*, int);
489 /* handle of the OPCODE hash table */
490 static struct hash_control
*op_hash
= NULL
;
492 /* The opcode hash table we use for the mips16. */
493 static struct hash_control
*mips16_op_hash
= NULL
;
495 /* This array holds the chars that always start a comment. If the
496 pre-processor is disabled, these aren't very useful */
497 const char comment_chars
[] = "#";
499 /* This array holds the chars that only start a comment at the beginning of
500 a line. If the line seems to have the form '# 123 filename'
501 .line and .file directives will appear in the pre-processed output */
502 /* Note that input_file.c hand checks for '#' at the beginning of the
503 first line of the input file. This is because the compiler outputs
504 #NO_APP at the beginning of its output. */
505 /* Also note that C style comments are always supported. */
506 const char line_comment_chars
[] = "#";
508 /* This array holds machine specific line separator characters. */
509 const char line_separator_chars
[] = ";";
511 /* Chars that can be used to separate mant from exp in floating point nums */
512 const char EXP_CHARS
[] = "eE";
514 /* Chars that mean this number is a floating point constant */
517 const char FLT_CHARS
[] = "rRsSfFdDxXpP";
519 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
520 changed in read.c . Ideally it shouldn't have to know about it at all,
521 but nothing is ideal around here.
524 static char *insn_error
;
526 static int auto_align
= 1;
528 /* When outputting SVR4 PIC code, the assembler needs to know the
529 offset in the stack frame from which to restore the $gp register.
530 This is set by the .cprestore pseudo-op, and saved in this
532 static offsetT mips_cprestore_offset
= -1;
534 /* Similar for NewABI PIC code, where $gp is callee-saved. NewABI has some
535 more optimizations, it can use a register value instead of a memory-saved
536 offset and even an other register than $gp as global pointer. */
537 static offsetT mips_cpreturn_offset
= -1;
538 static int mips_cpreturn_register
= -1;
539 static int mips_gp_register
= GP
;
540 static int mips_gprel_offset
= 0;
542 /* Whether mips_cprestore_offset has been set in the current function
543 (or whether it has already been warned about, if not). */
544 static int mips_cprestore_valid
= 0;
546 /* This is the register which holds the stack frame, as set by the
547 .frame pseudo-op. This is needed to implement .cprestore. */
548 static int mips_frame_reg
= SP
;
550 /* Whether mips_frame_reg has been set in the current function
551 (or whether it has already been warned about, if not). */
552 static int mips_frame_reg_valid
= 0;
554 /* To output NOP instructions correctly, we need to keep information
555 about the previous two instructions. */
557 /* Whether we are optimizing. The default value of 2 means to remove
558 unneeded NOPs and swap branch instructions when possible. A value
559 of 1 means to not swap branches. A value of 0 means to always
561 static int mips_optimize
= 2;
563 /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is
564 equivalent to seeing no -g option at all. */
565 static int mips_debug
= 0;
567 /* A list of previous instructions, with index 0 being the most recent. */
568 static struct mips_cl_insn history
[2];
570 /* If we don't want information for a history[] entry, we
571 point the insn_mo field at this dummy integer. */
572 static const struct mips_opcode dummy_opcode
= { NULL
, NULL
, 0, 0, 0, 0, 0 };
574 /* If this is set, it points to a frag holding nop instructions which
575 were inserted before the start of a noreorder section. If those
576 nops turn out to be unnecessary, the size of the frag can be
578 static fragS
*prev_nop_frag
;
580 /* The number of nop instructions we created in prev_nop_frag. */
581 static int prev_nop_frag_holds
;
583 /* The number of nop instructions that we know we need in
585 static int prev_nop_frag_required
;
587 /* The number of instructions we've seen since prev_nop_frag. */
588 static int prev_nop_frag_since
;
590 /* For ECOFF and ELF, relocations against symbols are done in two
591 parts, with a HI relocation and a LO relocation. Each relocation
592 has only 16 bits of space to store an addend. This means that in
593 order for the linker to handle carries correctly, it must be able
594 to locate both the HI and the LO relocation. This means that the
595 relocations must appear in order in the relocation table.
597 In order to implement this, we keep track of each unmatched HI
598 relocation. We then sort them so that they immediately precede the
599 corresponding LO relocation. */
604 struct mips_hi_fixup
*next
;
607 /* The section this fixup is in. */
611 /* The list of unmatched HI relocs. */
613 static struct mips_hi_fixup
*mips_hi_fixup_list
;
615 /* The frag containing the last explicit relocation operator.
616 Null if explicit relocations have not been used. */
618 static fragS
*prev_reloc_op_frag
;
620 /* Map normal MIPS register numbers to mips16 register numbers. */
622 #define X ILLEGAL_REG
623 static const int mips32_to_16_reg_map
[] =
625 X
, X
, 2, 3, 4, 5, 6, 7,
626 X
, X
, X
, X
, X
, X
, X
, X
,
627 0, 1, X
, X
, X
, X
, X
, X
,
628 X
, X
, X
, X
, X
, X
, X
, X
632 /* Map mips16 register numbers to normal MIPS register numbers. */
634 static const unsigned int mips16_to_32_reg_map
[] =
636 16, 17, 2, 3, 4, 5, 6, 7
639 static int mips_fix_vr4120
;
641 /* We don't relax branches by default, since this causes us to expand
642 `la .l2 - .l1' if there's a branch between .l1 and .l2, because we
643 fail to compute the offset before expanding the macro to the most
644 efficient expansion. */
646 static int mips_relax_branch
;
648 /* The expansion of many macros depends on the type of symbol that
649 they refer to. For example, when generating position-dependent code,
650 a macro that refers to a symbol may have two different expansions,
651 one which uses GP-relative addresses and one which uses absolute
652 addresses. When generating SVR4-style PIC, a macro may have
653 different expansions for local and global symbols.
655 We handle these situations by generating both sequences and putting
656 them in variant frags. In position-dependent code, the first sequence
657 will be the GP-relative one and the second sequence will be the
658 absolute one. In SVR4 PIC, the first sequence will be for global
659 symbols and the second will be for local symbols.
661 The frag's "subtype" is RELAX_ENCODE (FIRST, SECOND), where FIRST and
662 SECOND are the lengths of the two sequences in bytes. These fields
663 can be extracted using RELAX_FIRST() and RELAX_SECOND(). In addition,
664 the subtype has the following flags:
667 Set if it has been decided that we should use the second
668 sequence instead of the first.
671 Set in the first variant frag if the macro's second implementation
672 is longer than its first. This refers to the macro as a whole,
673 not an individual relaxation.
676 Set in the first variant frag if the macro appeared in a .set nomacro
677 block and if one alternative requires a warning but the other does not.
680 Like RELAX_NOMACRO, but indicates that the macro appears in a branch
683 The frag's "opcode" points to the first fixup for relaxable code.
685 Relaxable macros are generated using a sequence such as:
687 relax_start (SYMBOL);
688 ... generate first expansion ...
690 ... generate second expansion ...
693 The code and fixups for the unwanted alternative are discarded
694 by md_convert_frag. */
695 #define RELAX_ENCODE(FIRST, SECOND) (((FIRST) << 8) | (SECOND))
697 #define RELAX_FIRST(X) (((X) >> 8) & 0xff)
698 #define RELAX_SECOND(X) ((X) & 0xff)
699 #define RELAX_USE_SECOND 0x10000
700 #define RELAX_SECOND_LONGER 0x20000
701 #define RELAX_NOMACRO 0x40000
702 #define RELAX_DELAY_SLOT 0x80000
704 /* Branch without likely bit. If label is out of range, we turn:
706 beq reg1, reg2, label
716 with the following opcode replacements:
723 bltzal <-> bgezal (with jal label instead of j label)
725 Even though keeping the delay slot instruction in the delay slot of
726 the branch would be more efficient, it would be very tricky to do
727 correctly, because we'd have to introduce a variable frag *after*
728 the delay slot instruction, and expand that instead. Let's do it
729 the easy way for now, even if the branch-not-taken case now costs
730 one additional instruction. Out-of-range branches are not supposed
731 to be common, anyway.
733 Branch likely. If label is out of range, we turn:
735 beql reg1, reg2, label
736 delay slot (annulled if branch not taken)
745 delay slot (executed only if branch taken)
748 It would be possible to generate a shorter sequence by losing the
749 likely bit, generating something like:
754 delay slot (executed only if branch taken)
766 bltzall -> bgezal (with jal label instead of j label)
767 bgezall -> bltzal (ditto)
770 but it's not clear that it would actually improve performance. */
771 #define RELAX_BRANCH_ENCODE(uncond, likely, link, toofar) \
774 | ((toofar) ? 1 : 0) \
776 | ((likely) ? 4 : 0) \
777 | ((uncond) ? 8 : 0)))
778 #define RELAX_BRANCH_P(i) (((i) & 0xf0000000) == 0xc0000000)
779 #define RELAX_BRANCH_UNCOND(i) (((i) & 8) != 0)
780 #define RELAX_BRANCH_LIKELY(i) (((i) & 4) != 0)
781 #define RELAX_BRANCH_LINK(i) (((i) & 2) != 0)
782 #define RELAX_BRANCH_TOOFAR(i) (((i) & 1) != 0)
784 /* For mips16 code, we use an entirely different form of relaxation.
785 mips16 supports two versions of most instructions which take
786 immediate values: a small one which takes some small value, and a
787 larger one which takes a 16 bit value. Since branches also follow
788 this pattern, relaxing these values is required.
790 We can assemble both mips16 and normal MIPS code in a single
791 object. Therefore, we need to support this type of relaxation at
792 the same time that we support the relaxation described above. We
793 use the high bit of the subtype field to distinguish these cases.
795 The information we store for this type of relaxation is the
796 argument code found in the opcode file for this relocation, whether
797 the user explicitly requested a small or extended form, and whether
798 the relocation is in a jump or jal delay slot. That tells us the
799 size of the value, and how it should be stored. We also store
800 whether the fragment is considered to be extended or not. We also
801 store whether this is known to be a branch to a different section,
802 whether we have tried to relax this frag yet, and whether we have
803 ever extended a PC relative fragment because of a shift count. */
804 #define RELAX_MIPS16_ENCODE(type, small, ext, dslot, jal_dslot) \
807 | ((small) ? 0x100 : 0) \
808 | ((ext) ? 0x200 : 0) \
809 | ((dslot) ? 0x400 : 0) \
810 | ((jal_dslot) ? 0x800 : 0))
811 #define RELAX_MIPS16_P(i) (((i) & 0xc0000000) == 0x80000000)
812 #define RELAX_MIPS16_TYPE(i) ((i) & 0xff)
813 #define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x100) != 0)
814 #define RELAX_MIPS16_USER_EXT(i) (((i) & 0x200) != 0)
815 #define RELAX_MIPS16_DSLOT(i) (((i) & 0x400) != 0)
816 #define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x800) != 0)
817 #define RELAX_MIPS16_EXTENDED(i) (((i) & 0x1000) != 0)
818 #define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x1000)
819 #define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) &~ 0x1000)
820 #define RELAX_MIPS16_LONG_BRANCH(i) (((i) & 0x2000) != 0)
821 #define RELAX_MIPS16_MARK_LONG_BRANCH(i) ((i) | 0x2000)
822 #define RELAX_MIPS16_CLEAR_LONG_BRANCH(i) ((i) &~ 0x2000)
824 /* Is the given value a sign-extended 32-bit value? */
825 #define IS_SEXT_32BIT_NUM(x) \
826 (((x) &~ (offsetT) 0x7fffffff) == 0 \
827 || (((x) &~ (offsetT) 0x7fffffff) == ~ (offsetT) 0x7fffffff))
829 /* Is the given value a sign-extended 16-bit value? */
830 #define IS_SEXT_16BIT_NUM(x) \
831 (((x) &~ (offsetT) 0x7fff) == 0 \
832 || (((x) &~ (offsetT) 0x7fff) == ~ (offsetT) 0x7fff))
835 /* Global variables used when generating relaxable macros. See the
836 comment above RELAX_ENCODE for more details about how relaxation
839 /* 0 if we're not emitting a relaxable macro.
840 1 if we're emitting the first of the two relaxation alternatives.
841 2 if we're emitting the second alternative. */
844 /* The first relaxable fixup in the current frag. (In other words,
845 the first fixup that refers to relaxable code.) */
848 /* sizes[0] says how many bytes of the first alternative are stored in
849 the current frag. Likewise sizes[1] for the second alternative. */
850 unsigned int sizes
[2];
852 /* The symbol on which the choice of sequence depends. */
856 /* Global variables used to decide whether a macro needs a warning. */
858 /* True if the macro is in a branch delay slot. */
859 bfd_boolean delay_slot_p
;
861 /* For relaxable macros, sizes[0] is the length of the first alternative
862 in bytes and sizes[1] is the length of the second alternative.
863 For non-relaxable macros, both elements give the length of the
865 unsigned int sizes
[2];
867 /* The first variant frag for this macro. */
869 } mips_macro_warning
;
871 /* Prototypes for static functions. */
873 #define internalError() \
874 as_fatal (_("internal Error, line %d, %s"), __LINE__, __FILE__)
876 enum mips_regclass
{ MIPS_GR_REG
, MIPS_FP_REG
, MIPS16_REG
};
878 static void append_insn
879 (struct mips_cl_insn
*ip
, expressionS
*p
, bfd_reloc_code_real_type
*r
);
880 static void mips_no_prev_insn (int);
881 static void mips16_macro_build
882 (expressionS
*, const char *, const char *, va_list);
883 static void load_register (int, expressionS
*, int);
884 static void macro_start (void);
885 static void macro_end (void);
886 static void macro (struct mips_cl_insn
* ip
);
887 static void mips16_macro (struct mips_cl_insn
* ip
);
888 #ifdef LOSING_COMPILER
889 static void macro2 (struct mips_cl_insn
* ip
);
891 static void mips_ip (char *str
, struct mips_cl_insn
* ip
);
892 static void mips16_ip (char *str
, struct mips_cl_insn
* ip
);
893 static void mips16_immed
894 (char *, unsigned int, int, offsetT
, bfd_boolean
, bfd_boolean
, bfd_boolean
,
895 unsigned long *, bfd_boolean
*, unsigned short *);
896 static size_t my_getSmallExpression
897 (expressionS
*, bfd_reloc_code_real_type
*, char *);
898 static void my_getExpression (expressionS
*, char *);
899 static void s_align (int);
900 static void s_change_sec (int);
901 static void s_change_section (int);
902 static void s_cons (int);
903 static void s_float_cons (int);
904 static void s_mips_globl (int);
905 static void s_option (int);
906 static void s_mipsset (int);
907 static void s_abicalls (int);
908 static void s_cpload (int);
909 static void s_cpsetup (int);
910 static void s_cplocal (int);
911 static void s_cprestore (int);
912 static void s_cpreturn (int);
913 static void s_gpvalue (int);
914 static void s_gpword (int);
915 static void s_gpdword (int);
916 static void s_cpadd (int);
917 static void s_insn (int);
918 static void md_obj_begin (void);
919 static void md_obj_end (void);
920 static void s_mips_ent (int);
921 static void s_mips_end (int);
922 static void s_mips_frame (int);
923 static void s_mips_mask (int reg_type
);
924 static void s_mips_stab (int);
925 static void s_mips_weakext (int);
926 static void s_mips_file (int);
927 static void s_mips_loc (int);
928 static bfd_boolean
pic_need_relax (symbolS
*, asection
*);
929 static int relaxed_branch_length (fragS
*, asection
*, int);
930 static int validate_mips_insn (const struct mips_opcode
*);
932 /* Table and functions used to map between CPU/ISA names, and
933 ISA levels, and CPU numbers. */
937 const char *name
; /* CPU or ISA name. */
938 int is_isa
; /* Is this an ISA? (If 0, a CPU.) */
939 int isa
; /* ISA level. */
940 int cpu
; /* CPU number (default CPU if ISA). */
943 static const struct mips_cpu_info
*mips_parse_cpu (const char *, const char *);
944 static const struct mips_cpu_info
*mips_cpu_info_from_isa (int);
945 static const struct mips_cpu_info
*mips_cpu_info_from_arch (int);
949 The following pseudo-ops from the Kane and Heinrich MIPS book
950 should be defined here, but are currently unsupported: .alias,
951 .galive, .gjaldef, .gjrlive, .livereg, .noalias.
953 The following pseudo-ops from the Kane and Heinrich MIPS book are
954 specific to the type of debugging information being generated, and
955 should be defined by the object format: .aent, .begin, .bend,
956 .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp,
959 The following pseudo-ops from the Kane and Heinrich MIPS book are
960 not MIPS CPU specific, but are also not specific to the object file
961 format. This file is probably the best place to define them, but
962 they are not currently supported: .asm0, .endr, .lab, .repeat,
965 static const pseudo_typeS mips_pseudo_table
[] =
967 /* MIPS specific pseudo-ops. */
968 {"option", s_option
, 0},
969 {"set", s_mipsset
, 0},
970 {"rdata", s_change_sec
, 'r'},
971 {"sdata", s_change_sec
, 's'},
972 {"livereg", s_ignore
, 0},
973 {"abicalls", s_abicalls
, 0},
974 {"cpload", s_cpload
, 0},
975 {"cpsetup", s_cpsetup
, 0},
976 {"cplocal", s_cplocal
, 0},
977 {"cprestore", s_cprestore
, 0},
978 {"cpreturn", s_cpreturn
, 0},
979 {"gpvalue", s_gpvalue
, 0},
980 {"gpword", s_gpword
, 0},
981 {"gpdword", s_gpdword
, 0},
982 {"cpadd", s_cpadd
, 0},
985 /* Relatively generic pseudo-ops that happen to be used on MIPS
987 {"asciiz", stringer
, 1},
988 {"bss", s_change_sec
, 'b'},
991 {"dword", s_cons
, 3},
992 {"weakext", s_mips_weakext
, 0},
994 /* These pseudo-ops are defined in read.c, but must be overridden
995 here for one reason or another. */
996 {"align", s_align
, 0},
998 {"data", s_change_sec
, 'd'},
999 {"double", s_float_cons
, 'd'},
1000 {"float", s_float_cons
, 'f'},
1001 {"globl", s_mips_globl
, 0},
1002 {"global", s_mips_globl
, 0},
1003 {"hword", s_cons
, 1},
1005 {"long", s_cons
, 2},
1006 {"octa", s_cons
, 4},
1007 {"quad", s_cons
, 3},
1008 {"section", s_change_section
, 0},
1009 {"short", s_cons
, 1},
1010 {"single", s_float_cons
, 'f'},
1011 {"stabn", s_mips_stab
, 'n'},
1012 {"text", s_change_sec
, 't'},
1013 {"word", s_cons
, 2},
1015 { "extern", ecoff_directive_extern
, 0},
1020 static const pseudo_typeS mips_nonecoff_pseudo_table
[] =
1022 /* These pseudo-ops should be defined by the object file format.
1023 However, a.out doesn't support them, so we have versions here. */
1024 {"aent", s_mips_ent
, 1},
1025 {"bgnb", s_ignore
, 0},
1026 {"end", s_mips_end
, 0},
1027 {"endb", s_ignore
, 0},
1028 {"ent", s_mips_ent
, 0},
1029 {"file", s_mips_file
, 0},
1030 {"fmask", s_mips_mask
, 'F'},
1031 {"frame", s_mips_frame
, 0},
1032 {"loc", s_mips_loc
, 0},
1033 {"mask", s_mips_mask
, 'R'},
1034 {"verstamp", s_ignore
, 0},
1038 extern void pop_insert (const pseudo_typeS
*);
1041 mips_pop_insert (void)
1043 pop_insert (mips_pseudo_table
);
1044 if (! ECOFF_DEBUGGING
)
1045 pop_insert (mips_nonecoff_pseudo_table
);
1048 /* Symbols labelling the current insn. */
1050 struct insn_label_list
1052 struct insn_label_list
*next
;
1056 static struct insn_label_list
*insn_labels
;
1057 static struct insn_label_list
*free_insn_labels
;
1059 static void mips_clear_insn_labels (void);
1062 mips_clear_insn_labels (void)
1064 register struct insn_label_list
**pl
;
1066 for (pl
= &free_insn_labels
; *pl
!= NULL
; pl
= &(*pl
)->next
)
1072 static char *expr_end
;
1074 /* Expressions which appear in instructions. These are set by
1077 static expressionS imm_expr
;
1078 static expressionS imm2_expr
;
1079 static expressionS offset_expr
;
1081 /* Relocs associated with imm_expr and offset_expr. */
1083 static bfd_reloc_code_real_type imm_reloc
[3]
1084 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
1085 static bfd_reloc_code_real_type offset_reloc
[3]
1086 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
1088 /* These are set by mips16_ip if an explicit extension is used. */
1090 static bfd_boolean mips16_small
, mips16_ext
;
1093 /* The pdr segment for per procedure frame/regmask info. Not used for
1096 static segT pdr_seg
;
1099 /* The default target format to use. */
1102 mips_target_format (void)
1104 switch (OUTPUT_FLAVOR
)
1106 case bfd_target_ecoff_flavour
:
1107 return target_big_endian
? "ecoff-bigmips" : ECOFF_LITTLE_FORMAT
;
1108 case bfd_target_coff_flavour
:
1110 case bfd_target_elf_flavour
:
1112 /* This is traditional mips. */
1113 return (target_big_endian
1114 ? (HAVE_64BIT_OBJECTS
1115 ? "elf64-tradbigmips"
1117 ? "elf32-ntradbigmips" : "elf32-tradbigmips"))
1118 : (HAVE_64BIT_OBJECTS
1119 ? "elf64-tradlittlemips"
1121 ? "elf32-ntradlittlemips" : "elf32-tradlittlemips")));
1123 return (target_big_endian
1124 ? (HAVE_64BIT_OBJECTS
1127 ? "elf32-nbigmips" : "elf32-bigmips"))
1128 : (HAVE_64BIT_OBJECTS
1129 ? "elf64-littlemips"
1131 ? "elf32-nlittlemips" : "elf32-littlemips")));
1139 /* This function is called once, at assembler startup time. It should
1140 set up all the tables, etc. that the MD part of the assembler will need. */
1145 register const char *retval
= NULL
;
1149 if (! bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, file_mips_arch
))
1150 as_warn (_("Could not set architecture and machine"));
1152 op_hash
= hash_new ();
1154 for (i
= 0; i
< NUMOPCODES
;)
1156 const char *name
= mips_opcodes
[i
].name
;
1158 retval
= hash_insert (op_hash
, name
, (void *) &mips_opcodes
[i
]);
1161 fprintf (stderr
, _("internal error: can't hash `%s': %s\n"),
1162 mips_opcodes
[i
].name
, retval
);
1163 /* Probably a memory allocation problem? Give up now. */
1164 as_fatal (_("Broken assembler. No assembly attempted."));
1168 if (mips_opcodes
[i
].pinfo
!= INSN_MACRO
)
1170 if (!validate_mips_insn (&mips_opcodes
[i
]))
1175 while ((i
< NUMOPCODES
) && !strcmp (mips_opcodes
[i
].name
, name
));
1178 mips16_op_hash
= hash_new ();
1181 while (i
< bfd_mips16_num_opcodes
)
1183 const char *name
= mips16_opcodes
[i
].name
;
1185 retval
= hash_insert (mips16_op_hash
, name
, (void *) &mips16_opcodes
[i
]);
1187 as_fatal (_("internal: can't hash `%s': %s"),
1188 mips16_opcodes
[i
].name
, retval
);
1191 if (mips16_opcodes
[i
].pinfo
!= INSN_MACRO
1192 && ((mips16_opcodes
[i
].match
& mips16_opcodes
[i
].mask
)
1193 != mips16_opcodes
[i
].match
))
1195 fprintf (stderr
, _("internal error: bad mips16 opcode: %s %s\n"),
1196 mips16_opcodes
[i
].name
, mips16_opcodes
[i
].args
);
1201 while (i
< bfd_mips16_num_opcodes
1202 && strcmp (mips16_opcodes
[i
].name
, name
) == 0);
1206 as_fatal (_("Broken assembler. No assembly attempted."));
1208 /* We add all the general register names to the symbol table. This
1209 helps us detect invalid uses of them. */
1210 for (i
= 0; i
< 32; i
++)
1214 sprintf (buf
, "$%d", i
);
1215 symbol_table_insert (symbol_new (buf
, reg_section
, i
,
1216 &zero_address_frag
));
1218 symbol_table_insert (symbol_new ("$ra", reg_section
, RA
,
1219 &zero_address_frag
));
1220 symbol_table_insert (symbol_new ("$fp", reg_section
, FP
,
1221 &zero_address_frag
));
1222 symbol_table_insert (symbol_new ("$sp", reg_section
, SP
,
1223 &zero_address_frag
));
1224 symbol_table_insert (symbol_new ("$gp", reg_section
, GP
,
1225 &zero_address_frag
));
1226 symbol_table_insert (symbol_new ("$at", reg_section
, AT
,
1227 &zero_address_frag
));
1228 symbol_table_insert (symbol_new ("$kt0", reg_section
, KT0
,
1229 &zero_address_frag
));
1230 symbol_table_insert (symbol_new ("$kt1", reg_section
, KT1
,
1231 &zero_address_frag
));
1232 symbol_table_insert (symbol_new ("$zero", reg_section
, ZERO
,
1233 &zero_address_frag
));
1234 symbol_table_insert (symbol_new ("$pc", reg_section
, -1,
1235 &zero_address_frag
));
1237 /* If we don't add these register names to the symbol table, they
1238 may end up being added as regular symbols by operand(), and then
1239 make it to the object file as undefined in case they're not
1240 regarded as local symbols. They're local in o32, since `$' is a
1241 local symbol prefix, but not in n32 or n64. */
1242 for (i
= 0; i
< 8; i
++)
1246 sprintf (buf
, "$fcc%i", i
);
1247 symbol_table_insert (symbol_new (buf
, reg_section
, -1,
1248 &zero_address_frag
));
1251 mips_no_prev_insn (FALSE
);
1254 mips_cprmask
[0] = 0;
1255 mips_cprmask
[1] = 0;
1256 mips_cprmask
[2] = 0;
1257 mips_cprmask
[3] = 0;
1259 /* set the default alignment for the text section (2**2) */
1260 record_alignment (text_section
, 2);
1262 bfd_set_gp_size (stdoutput
, g_switch_value
);
1264 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
1266 /* On a native system, sections must be aligned to 16 byte
1267 boundaries. When configured for an embedded ELF target, we
1269 if (strcmp (TARGET_OS
, "elf") != 0)
1271 (void) bfd_set_section_alignment (stdoutput
, text_section
, 4);
1272 (void) bfd_set_section_alignment (stdoutput
, data_section
, 4);
1273 (void) bfd_set_section_alignment (stdoutput
, bss_section
, 4);
1276 /* Create a .reginfo section for register masks and a .mdebug
1277 section for debugging information. */
1285 subseg
= now_subseg
;
1287 /* The ABI says this section should be loaded so that the
1288 running program can access it. However, we don't load it
1289 if we are configured for an embedded target */
1290 flags
= SEC_READONLY
| SEC_DATA
;
1291 if (strcmp (TARGET_OS
, "elf") != 0)
1292 flags
|= SEC_ALLOC
| SEC_LOAD
;
1294 if (mips_abi
!= N64_ABI
)
1296 sec
= subseg_new (".reginfo", (subsegT
) 0);
1298 bfd_set_section_flags (stdoutput
, sec
, flags
);
1299 bfd_set_section_alignment (stdoutput
, sec
, HAVE_NEWABI
? 3 : 2);
1302 mips_regmask_frag
= frag_more (sizeof (Elf32_External_RegInfo
));
1307 /* The 64-bit ABI uses a .MIPS.options section rather than
1308 .reginfo section. */
1309 sec
= subseg_new (".MIPS.options", (subsegT
) 0);
1310 bfd_set_section_flags (stdoutput
, sec
, flags
);
1311 bfd_set_section_alignment (stdoutput
, sec
, 3);
1314 /* Set up the option header. */
1316 Elf_Internal_Options opthdr
;
1319 opthdr
.kind
= ODK_REGINFO
;
1320 opthdr
.size
= (sizeof (Elf_External_Options
)
1321 + sizeof (Elf64_External_RegInfo
));
1324 f
= frag_more (sizeof (Elf_External_Options
));
1325 bfd_mips_elf_swap_options_out (stdoutput
, &opthdr
,
1326 (Elf_External_Options
*) f
);
1328 mips_regmask_frag
= frag_more (sizeof (Elf64_External_RegInfo
));
1333 if (ECOFF_DEBUGGING
)
1335 sec
= subseg_new (".mdebug", (subsegT
) 0);
1336 (void) bfd_set_section_flags (stdoutput
, sec
,
1337 SEC_HAS_CONTENTS
| SEC_READONLY
);
1338 (void) bfd_set_section_alignment (stdoutput
, sec
, 2);
1341 else if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
&& mips_flag_pdr
)
1343 pdr_seg
= subseg_new (".pdr", (subsegT
) 0);
1344 (void) bfd_set_section_flags (stdoutput
, pdr_seg
,
1345 SEC_READONLY
| SEC_RELOC
1347 (void) bfd_set_section_alignment (stdoutput
, pdr_seg
, 2);
1351 subseg_set (seg
, subseg
);
1355 if (! ECOFF_DEBUGGING
)
1362 if (! ECOFF_DEBUGGING
)
1367 md_assemble (char *str
)
1369 struct mips_cl_insn insn
;
1370 bfd_reloc_code_real_type unused_reloc
[3]
1371 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
1373 imm_expr
.X_op
= O_absent
;
1374 imm2_expr
.X_op
= O_absent
;
1375 offset_expr
.X_op
= O_absent
;
1376 imm_reloc
[0] = BFD_RELOC_UNUSED
;
1377 imm_reloc
[1] = BFD_RELOC_UNUSED
;
1378 imm_reloc
[2] = BFD_RELOC_UNUSED
;
1379 offset_reloc
[0] = BFD_RELOC_UNUSED
;
1380 offset_reloc
[1] = BFD_RELOC_UNUSED
;
1381 offset_reloc
[2] = BFD_RELOC_UNUSED
;
1383 if (mips_opts
.mips16
)
1384 mips16_ip (str
, &insn
);
1387 mips_ip (str
, &insn
);
1388 DBG ((_("returned from mips_ip(%s) insn_opcode = 0x%x\n"),
1389 str
, insn
.insn_opcode
));
1394 as_bad ("%s `%s'", insn_error
, str
);
1398 if (insn
.insn_mo
->pinfo
== INSN_MACRO
)
1401 if (mips_opts
.mips16
)
1402 mips16_macro (&insn
);
1409 if (imm_expr
.X_op
!= O_absent
)
1410 append_insn (&insn
, &imm_expr
, imm_reloc
);
1411 else if (offset_expr
.X_op
!= O_absent
)
1412 append_insn (&insn
, &offset_expr
, offset_reloc
);
1414 append_insn (&insn
, NULL
, unused_reloc
);
1418 /* Return true if the given relocation might need a matching %lo().
1419 Note that R_MIPS_GOT16 relocations only need a matching %lo() when
1420 applied to local symbols. */
1422 static inline bfd_boolean
1423 reloc_needs_lo_p (bfd_reloc_code_real_type reloc
)
1425 return (HAVE_IN_PLACE_ADDENDS
1426 && (reloc
== BFD_RELOC_HI16_S
1427 || reloc
== BFD_RELOC_MIPS_GOT16
1428 || reloc
== BFD_RELOC_MIPS16_HI16_S
));
1431 /* Return true if the given fixup is followed by a matching R_MIPS_LO16
1434 static inline bfd_boolean
1435 fixup_has_matching_lo_p (fixS
*fixp
)
1437 return (fixp
->fx_next
!= NULL
1438 && (fixp
->fx_next
->fx_r_type
== BFD_RELOC_LO16
1439 || fixp
->fx_next
->fx_r_type
== BFD_RELOC_MIPS16_LO16
)
1440 && fixp
->fx_addsy
== fixp
->fx_next
->fx_addsy
1441 && fixp
->fx_offset
== fixp
->fx_next
->fx_offset
);
1444 /* See whether instruction IP reads register REG. CLASS is the type
1448 insn_uses_reg (struct mips_cl_insn
*ip
, unsigned int reg
,
1449 enum mips_regclass
class)
1451 if (class == MIPS16_REG
)
1453 assert (mips_opts
.mips16
);
1454 reg
= mips16_to_32_reg_map
[reg
];
1455 class = MIPS_GR_REG
;
1458 /* Don't report on general register ZERO, since it never changes. */
1459 if (class == MIPS_GR_REG
&& reg
== ZERO
)
1462 if (class == MIPS_FP_REG
)
1464 assert (! mips_opts
.mips16
);
1465 /* If we are called with either $f0 or $f1, we must check $f0.
1466 This is not optimal, because it will introduce an unnecessary
1467 NOP between "lwc1 $f0" and "swc1 $f1". To fix this we would
1468 need to distinguish reading both $f0 and $f1 or just one of
1469 them. Note that we don't have to check the other way,
1470 because there is no instruction that sets both $f0 and $f1
1471 and requires a delay. */
1472 if ((ip
->insn_mo
->pinfo
& INSN_READ_FPR_S
)
1473 && ((((ip
->insn_opcode
>> OP_SH_FS
) & OP_MASK_FS
) &~(unsigned)1)
1474 == (reg
&~ (unsigned) 1)))
1476 if ((ip
->insn_mo
->pinfo
& INSN_READ_FPR_T
)
1477 && ((((ip
->insn_opcode
>> OP_SH_FT
) & OP_MASK_FT
) &~(unsigned)1)
1478 == (reg
&~ (unsigned) 1)))
1481 else if (! mips_opts
.mips16
)
1483 if ((ip
->insn_mo
->pinfo
& INSN_READ_GPR_S
)
1484 && ((ip
->insn_opcode
>> OP_SH_RS
) & OP_MASK_RS
) == reg
)
1486 if ((ip
->insn_mo
->pinfo
& INSN_READ_GPR_T
)
1487 && ((ip
->insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
) == reg
)
1492 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_X
)
1493 && (mips16_to_32_reg_map
[((ip
->insn_opcode
>> MIPS16OP_SH_RX
)
1494 & MIPS16OP_MASK_RX
)]
1497 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_Y
)
1498 && (mips16_to_32_reg_map
[((ip
->insn_opcode
>> MIPS16OP_SH_RY
)
1499 & MIPS16OP_MASK_RY
)]
1502 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_Z
)
1503 && (mips16_to_32_reg_map
[((ip
->insn_opcode
>> MIPS16OP_SH_MOVE32Z
)
1504 & MIPS16OP_MASK_MOVE32Z
)]
1507 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_T
) && reg
== TREG
)
1509 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_SP
) && reg
== SP
)
1511 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_31
) && reg
== RA
)
1513 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_GPR_X
)
1514 && ((ip
->insn_opcode
>> MIPS16OP_SH_REGR32
)
1515 & MIPS16OP_MASK_REGR32
) == reg
)
1522 /* This function returns true if modifying a register requires a
1526 reg_needs_delay (unsigned int reg
)
1528 unsigned long prev_pinfo
;
1530 prev_pinfo
= history
[0].insn_mo
->pinfo
;
1531 if (! mips_opts
.noreorder
1532 && (((prev_pinfo
& INSN_LOAD_MEMORY_DELAY
)
1533 && ! gpr_interlocks
)
1534 || ((prev_pinfo
& INSN_LOAD_COPROC_DELAY
)
1535 && ! cop_interlocks
)))
1537 /* A load from a coprocessor or from memory. All load delays
1538 delay the use of general register rt for one instruction. */
1539 /* Itbl support may require additional care here. */
1540 know (prev_pinfo
& INSN_WRITE_GPR_T
);
1541 if (reg
== ((history
[0].insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
))
1548 /* Mark instruction labels in mips16 mode. This permits the linker to
1549 handle them specially, such as generating jalx instructions when
1550 needed. We also make them odd for the duration of the assembly, in
1551 order to generate the right sort of code. We will make them even
1552 in the adjust_symtab routine, while leaving them marked. This is
1553 convenient for the debugger and the disassembler. The linker knows
1554 to make them odd again. */
1557 mips16_mark_labels (void)
1559 if (mips_opts
.mips16
)
1561 struct insn_label_list
*l
;
1564 for (l
= insn_labels
; l
!= NULL
; l
= l
->next
)
1567 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
1568 S_SET_OTHER (l
->label
, STO_MIPS16
);
1570 val
= S_GET_VALUE (l
->label
);
1572 S_SET_VALUE (l
->label
, val
+ 1);
1577 /* End the current frag. Make it a variant frag and record the
1581 relax_close_frag (void)
1583 mips_macro_warning
.first_frag
= frag_now
;
1584 frag_var (rs_machine_dependent
, 0, 0,
1585 RELAX_ENCODE (mips_relax
.sizes
[0], mips_relax
.sizes
[1]),
1586 mips_relax
.symbol
, 0, (char *) mips_relax
.first_fixup
);
1588 memset (&mips_relax
.sizes
, 0, sizeof (mips_relax
.sizes
));
1589 mips_relax
.first_fixup
= 0;
1592 /* Start a new relaxation sequence whose expansion depends on SYMBOL.
1593 See the comment above RELAX_ENCODE for more details. */
1596 relax_start (symbolS
*symbol
)
1598 assert (mips_relax
.sequence
== 0);
1599 mips_relax
.sequence
= 1;
1600 mips_relax
.symbol
= symbol
;
1603 /* Start generating the second version of a relaxable sequence.
1604 See the comment above RELAX_ENCODE for more details. */
1609 assert (mips_relax
.sequence
== 1);
1610 mips_relax
.sequence
= 2;
1613 /* End the current relaxable sequence. */
1618 assert (mips_relax
.sequence
== 2);
1619 relax_close_frag ();
1620 mips_relax
.sequence
= 0;
1623 /* Output an instruction. IP is the instruction information.
1624 ADDRESS_EXPR is an operand of the instruction to be used with
1628 append_insn (struct mips_cl_insn
*ip
, expressionS
*address_expr
,
1629 bfd_reloc_code_real_type
*reloc_type
)
1631 register unsigned long prev_pinfo
, pinfo
;
1635 relax_stateT prev_insn_frag_type
= 0;
1636 bfd_boolean relaxed_branch
= FALSE
;
1637 bfd_boolean force_new_frag
= FALSE
;
1639 /* Mark instruction labels in mips16 mode. */
1640 mips16_mark_labels ();
1642 prev_pinfo
= history
[0].insn_mo
->pinfo
;
1643 pinfo
= ip
->insn_mo
->pinfo
;
1645 if (mips_relax
.sequence
!= 2
1646 && (!mips_opts
.noreorder
|| prev_nop_frag
!= NULL
))
1650 /* If the previous insn required any delay slots, see if we need
1651 to insert a NOP or two. There are eight kinds of possible
1652 hazards, of which an instruction can have at most one type.
1653 (1) a load from memory delay
1654 (2) a load from a coprocessor delay
1655 (3) an unconditional branch delay
1656 (4) a conditional branch delay
1657 (5) a move to coprocessor register delay
1658 (6) a load coprocessor register from memory delay
1659 (7) a coprocessor condition code delay
1660 (8) a HI/LO special register delay
1662 There are a lot of optimizations we could do that we don't.
1663 In particular, we do not, in general, reorder instructions.
1664 If you use gcc with optimization, it will reorder
1665 instructions and generally do much more optimization then we
1666 do here; repeating all that work in the assembler would only
1667 benefit hand written assembly code, and does not seem worth
1670 /* This is how a NOP is emitted. */
1671 #define emit_nop() \
1673 ? md_number_to_chars (frag_more (2), 0x6500, 2) \
1674 : md_number_to_chars (frag_more (4), 0, 4))
1676 /* The previous insn might require a delay slot, depending upon
1677 the contents of the current insn. */
1678 if (! mips_opts
.mips16
1679 && (((prev_pinfo
& INSN_LOAD_MEMORY_DELAY
)
1680 && ! gpr_interlocks
)
1681 || ((prev_pinfo
& INSN_LOAD_COPROC_DELAY
)
1682 && ! cop_interlocks
)))
1684 /* A load from a coprocessor or from memory. All load
1685 delays delay the use of general register rt for one
1687 /* Itbl support may require additional care here. */
1688 know (prev_pinfo
& INSN_WRITE_GPR_T
);
1689 if (mips_optimize
== 0
1690 || insn_uses_reg (ip
,
1691 ((history
[0].insn_opcode
>> OP_SH_RT
)
1696 else if (! mips_opts
.mips16
1697 && (((prev_pinfo
& INSN_COPROC_MOVE_DELAY
)
1698 && ! cop_interlocks
)
1699 || ((prev_pinfo
& INSN_COPROC_MEMORY_DELAY
)
1700 && ! cop_mem_interlocks
)))
1702 /* A generic coprocessor delay. The previous instruction
1703 modified a coprocessor general or control register. If
1704 it modified a control register, we need to avoid any
1705 coprocessor instruction (this is probably not always
1706 required, but it sometimes is). If it modified a general
1707 register, we avoid using that register.
1709 This case is not handled very well. There is no special
1710 knowledge of CP0 handling, and the coprocessors other
1711 than the floating point unit are not distinguished at
1713 /* Itbl support may require additional care here. FIXME!
1714 Need to modify this to include knowledge about
1715 user specified delays! */
1716 if (prev_pinfo
& INSN_WRITE_FPR_T
)
1718 if (mips_optimize
== 0
1719 || insn_uses_reg (ip
,
1720 ((history
[0].insn_opcode
>> OP_SH_FT
)
1725 else if (prev_pinfo
& INSN_WRITE_FPR_S
)
1727 if (mips_optimize
== 0
1728 || insn_uses_reg (ip
,
1729 ((history
[0].insn_opcode
>> OP_SH_FS
)
1736 /* We don't know exactly what the previous instruction
1737 does. If the current instruction uses a coprocessor
1738 register, we must insert a NOP. If previous
1739 instruction may set the condition codes, and the
1740 current instruction uses them, we must insert two
1742 /* Itbl support may require additional care here. */
1743 if (mips_optimize
== 0
1744 || ((prev_pinfo
& INSN_WRITE_COND_CODE
)
1745 && (pinfo
& INSN_READ_COND_CODE
)))
1747 else if (pinfo
& INSN_COP
)
1751 else if (! mips_opts
.mips16
1752 && (prev_pinfo
& INSN_WRITE_COND_CODE
)
1753 && ! cop_interlocks
)
1755 /* The previous instruction sets the coprocessor condition
1756 codes, but does not require a general coprocessor delay
1757 (this means it is a floating point comparison
1758 instruction). If this instruction uses the condition
1759 codes, we need to insert a single NOP. */
1760 /* Itbl support may require additional care here. */
1761 if (mips_optimize
== 0
1762 || (pinfo
& INSN_READ_COND_CODE
))
1766 /* If we're fixing up mfhi/mflo for the r7000 and the
1767 previous insn was an mfhi/mflo and the current insn
1768 reads the register that the mfhi/mflo wrote to, then
1771 else if (mips_7000_hilo_fix
1772 && MF_HILO_INSN (prev_pinfo
)
1773 && insn_uses_reg (ip
, ((history
[0].insn_opcode
>> OP_SH_RD
)
1780 /* If we're fixing up mfhi/mflo for the r7000 and the
1781 2nd previous insn was an mfhi/mflo and the current insn
1782 reads the register that the mfhi/mflo wrote to, then
1785 else if (mips_7000_hilo_fix
1786 && MF_HILO_INSN (history
[1].insn_opcode
)
1787 && insn_uses_reg (ip
, ((history
[1].insn_opcode
>> OP_SH_RD
)
1795 else if (prev_pinfo
& INSN_READ_LO
)
1797 /* The previous instruction reads the LO register; if the
1798 current instruction writes to the LO register, we must
1799 insert two NOPS. Some newer processors have interlocks.
1800 Also the tx39's multiply instructions can be executed
1801 immediately after a read from HI/LO (without the delay),
1802 though the tx39's divide insns still do require the
1804 if (! (hilo_interlocks
1805 || (mips_opts
.arch
== CPU_R3900
&& (pinfo
& INSN_MULT
)))
1806 && (mips_optimize
== 0
1807 || (pinfo
& INSN_WRITE_LO
)))
1809 /* Most mips16 branch insns don't have a delay slot.
1810 If a read from LO is immediately followed by a branch
1811 to a write to LO we have a read followed by a write
1812 less than 2 insns away. We assume the target of
1813 a branch might be a write to LO, and insert a nop
1814 between a read and an immediately following branch. */
1815 else if (mips_opts
.mips16
1816 && (mips_optimize
== 0
1817 || (pinfo
& MIPS16_INSN_BRANCH
)))
1820 else if (history
[0].insn_mo
->pinfo
& INSN_READ_HI
)
1822 /* The previous instruction reads the HI register; if the
1823 current instruction writes to the HI register, we must
1824 insert a NOP. Some newer processors have interlocks.
1825 Also the note tx39's multiply above. */
1826 if (! (hilo_interlocks
1827 || (mips_opts
.arch
== CPU_R3900
&& (pinfo
& INSN_MULT
)))
1828 && (mips_optimize
== 0
1829 || (pinfo
& INSN_WRITE_HI
)))
1831 /* Most mips16 branch insns don't have a delay slot.
1832 If a read from HI is immediately followed by a branch
1833 to a write to HI we have a read followed by a write
1834 less than 2 insns away. We assume the target of
1835 a branch might be a write to HI, and insert a nop
1836 between a read and an immediately following branch. */
1837 else if (mips_opts
.mips16
1838 && (mips_optimize
== 0
1839 || (pinfo
& MIPS16_INSN_BRANCH
)))
1843 /* If the previous instruction was in a noreorder section, then
1844 we don't want to insert the nop after all. */
1845 /* Itbl support may require additional care here. */
1846 if (history
[0].noreorder_p
)
1849 /* There are two cases which require two intervening
1850 instructions: 1) setting the condition codes using a move to
1851 coprocessor instruction which requires a general coprocessor
1852 delay and then reading the condition codes 2) reading the HI
1853 or LO register and then writing to it (except on processors
1854 which have interlocks). If we are not already emitting a NOP
1855 instruction, we must check for these cases compared to the
1856 instruction previous to the previous instruction. */
1857 if ((! mips_opts
.mips16
1858 && (history
[1].insn_mo
->pinfo
& INSN_COPROC_MOVE_DELAY
)
1859 && (history
[1].insn_mo
->pinfo
& INSN_WRITE_COND_CODE
)
1860 && (pinfo
& INSN_READ_COND_CODE
)
1861 && ! cop_interlocks
)
1862 || ((history
[1].insn_mo
->pinfo
& INSN_READ_LO
)
1863 && (pinfo
& INSN_WRITE_LO
)
1864 && ! (hilo_interlocks
1865 || (mips_opts
.arch
== CPU_R3900
&& (pinfo
& INSN_MULT
))))
1866 || ((history
[1].insn_mo
->pinfo
& INSN_READ_HI
)
1867 && (pinfo
& INSN_WRITE_HI
)
1868 && ! (hilo_interlocks
1869 || (mips_opts
.arch
== CPU_R3900
&& (pinfo
& INSN_MULT
)))))
1874 if (history
[1].noreorder_p
)
1877 if (prev_prev_nop
&& nops
== 0)
1880 if (mips_fix_vr4120
&& history
[0].insn_mo
->name
)
1882 /* We're out of bits in pinfo, so we must resort to string
1883 ops here. Shortcuts are selected based on opcodes being
1884 limited to the VR4120 instruction set. */
1886 const char *pn
= history
[0].insn_mo
->name
;
1887 const char *tn
= ip
->insn_mo
->name
;
1888 if (strncmp (pn
, "macc", 4) == 0
1889 || strncmp (pn
, "dmacc", 5) == 0)
1891 /* Errata 21 - [D]DIV[U] after [D]MACC */
1892 if (strstr (tn
, "div"))
1895 /* VR4181A errata MD(1): "If a MULT, MULTU, DMULT or DMULTU
1896 instruction is executed immediately after a MACC or
1897 DMACC instruction, the result of [either instruction]
1899 if (strncmp (tn
, "mult", 4) == 0
1900 || strncmp (tn
, "dmult", 5) == 0)
1903 /* Errata 23 - Continuous DMULT[U]/DMACC instructions.
1904 Applies on top of VR4181A MD(1) errata. */
1905 if (pn
[0] == 'd' && strncmp (tn
, "dmacc", 5) == 0)
1908 /* Errata 24 - MT{LO,HI} after [D]MACC */
1909 if (strcmp (tn
, "mtlo") == 0
1910 || strcmp (tn
, "mthi") == 0)
1913 else if (strncmp (pn
, "dmult", 5) == 0
1914 && (strncmp (tn
, "dmult", 5) == 0
1915 || strncmp (tn
, "dmacc", 5) == 0))
1917 /* Here is the rest of errata 23. */
1920 else if ((strncmp (pn
, "dmult", 5) == 0 || strstr (pn
, "div"))
1921 && (strncmp (tn
, "macc", 4) == 0
1922 || strncmp (tn
, "dmacc", 5) == 0))
1924 /* VR4181A errata MD(4): "If a MACC or DMACC instruction is
1925 executed immediately after a DMULT, DMULTU, DIV, DIVU,
1926 DDIV or DDIVU instruction, the result of the MACC or
1927 DMACC instruction is incorrect.". This partly overlaps
1928 the workaround for errata 23. */
1931 if (nops
< min_nops
)
1935 /* If we are being given a nop instruction, don't bother with
1936 one of the nops we would otherwise output. This will only
1937 happen when a nop instruction is used with mips_optimize set
1940 && ! mips_opts
.noreorder
1941 && ip
->insn_opcode
== (unsigned) (mips_opts
.mips16
? 0x6500 : 0))
1944 /* Now emit the right number of NOP instructions. */
1945 if (nops
> 0 && ! mips_opts
.noreorder
)
1948 unsigned long old_frag_offset
;
1950 struct insn_label_list
*l
;
1952 old_frag
= frag_now
;
1953 old_frag_offset
= frag_now_fix ();
1955 for (i
= 0; i
< nops
; i
++)
1960 listing_prev_line ();
1961 /* We may be at the start of a variant frag. In case we
1962 are, make sure there is enough space for the frag
1963 after the frags created by listing_prev_line. The
1964 argument to frag_grow here must be at least as large
1965 as the argument to all other calls to frag_grow in
1966 this file. We don't have to worry about being in the
1967 middle of a variant frag, because the variants insert
1968 all needed nop instructions themselves. */
1972 for (l
= insn_labels
; l
!= NULL
; l
= l
->next
)
1976 assert (S_GET_SEGMENT (l
->label
) == now_seg
);
1977 symbol_set_frag (l
->label
, frag_now
);
1978 val
= (valueT
) frag_now_fix ();
1979 /* mips16 text labels are stored as odd. */
1980 if (mips_opts
.mips16
)
1982 S_SET_VALUE (l
->label
, val
);
1985 #ifndef NO_ECOFF_DEBUGGING
1986 if (ECOFF_DEBUGGING
)
1987 ecoff_fix_loc (old_frag
, old_frag_offset
);
1990 else if (prev_nop_frag
!= NULL
)
1992 /* We have a frag holding nops we may be able to remove. If
1993 we don't need any nops, we can decrease the size of
1994 prev_nop_frag by the size of one instruction. If we do
1995 need some nops, we count them in prev_nops_required. */
1996 if (prev_nop_frag_since
== 0)
2000 prev_nop_frag
->fr_fix
-= mips_opts
.mips16
? 2 : 4;
2001 --prev_nop_frag_holds
;
2004 prev_nop_frag_required
+= nops
;
2008 if (prev_prev_nop
== 0)
2010 prev_nop_frag
->fr_fix
-= mips_opts
.mips16
? 2 : 4;
2011 --prev_nop_frag_holds
;
2014 ++prev_nop_frag_required
;
2017 if (prev_nop_frag_holds
<= prev_nop_frag_required
)
2018 prev_nop_frag
= NULL
;
2020 ++prev_nop_frag_since
;
2022 /* Sanity check: by the time we reach the second instruction
2023 after prev_nop_frag, we should have used up all the nops
2024 one way or another. */
2025 assert (prev_nop_frag_since
<= 1 || prev_nop_frag
== NULL
);
2030 /* The value passed to dwarf2_emit_insn is the distance between
2031 the beginning of the current instruction and the address that
2032 should be recorded in the debug tables. For MIPS16 debug info
2033 we want to use ISA-encoded addresses, so we pass -1 for an
2034 address higher by one than the current. */
2035 dwarf2_emit_insn (mips_opts
.mips16
? -1 : 0);
2038 /* Record the frag type before frag_var. */
2039 if (history
[0].frag
)
2040 prev_insn_frag_type
= history
[0].frag
->fr_type
;
2043 && *reloc_type
== BFD_RELOC_16_PCREL_S2
2044 && (pinfo
& INSN_UNCOND_BRANCH_DELAY
|| pinfo
& INSN_COND_BRANCH_DELAY
2045 || pinfo
& INSN_COND_BRANCH_LIKELY
)
2046 && mips_relax_branch
2047 /* Don't try branch relaxation within .set nomacro, or within
2048 .set noat if we use $at for PIC computations. If it turns
2049 out that the branch was out-of-range, we'll get an error. */
2050 && !mips_opts
.warn_about_macros
2051 && !(mips_opts
.noat
&& mips_pic
!= NO_PIC
)
2052 && !mips_opts
.mips16
)
2054 relaxed_branch
= TRUE
;
2055 f
= frag_var (rs_machine_dependent
,
2056 relaxed_branch_length
2058 (pinfo
& INSN_UNCOND_BRANCH_DELAY
) ? -1
2059 : (pinfo
& INSN_COND_BRANCH_LIKELY
) ? 1 : 0), 4,
2061 (pinfo
& INSN_UNCOND_BRANCH_DELAY
,
2062 pinfo
& INSN_COND_BRANCH_LIKELY
,
2063 pinfo
& INSN_WRITE_GPR_31
,
2065 address_expr
->X_add_symbol
,
2066 address_expr
->X_add_number
,
2068 *reloc_type
= BFD_RELOC_UNUSED
;
2070 else if (*reloc_type
> BFD_RELOC_UNUSED
)
2072 /* We need to set up a variant frag. */
2073 assert (mips_opts
.mips16
&& address_expr
!= NULL
);
2074 f
= frag_var (rs_machine_dependent
, 4, 0,
2075 RELAX_MIPS16_ENCODE (*reloc_type
- BFD_RELOC_UNUSED
,
2076 mips16_small
, mips16_ext
,
2078 & INSN_UNCOND_BRANCH_DELAY
),
2079 (*history
[0].reloc_type
2080 == BFD_RELOC_MIPS16_JMP
)),
2081 make_expr_symbol (address_expr
), 0, NULL
);
2083 else if (mips_opts
.mips16
2085 && *reloc_type
!= BFD_RELOC_MIPS16_JMP
)
2087 /* Make sure there is enough room to swap this instruction with
2088 a following jump instruction. */
2094 if (mips_opts
.mips16
2095 && mips_opts
.noreorder
2096 && (prev_pinfo
& INSN_UNCOND_BRANCH_DELAY
) != 0)
2097 as_warn (_("extended instruction in delay slot"));
2099 if (mips_relax
.sequence
)
2101 /* If we've reached the end of this frag, turn it into a variant
2102 frag and record the information for the instructions we've
2104 if (frag_room () < 4)
2105 relax_close_frag ();
2106 mips_relax
.sizes
[mips_relax
.sequence
- 1] += 4;
2109 if (mips_relax
.sequence
!= 2)
2110 mips_macro_warning
.sizes
[0] += 4;
2111 if (mips_relax
.sequence
!= 1)
2112 mips_macro_warning
.sizes
[1] += 4;
2117 fixp
[0] = fixp
[1] = fixp
[2] = NULL
;
2118 if (address_expr
!= NULL
&& *reloc_type
<= BFD_RELOC_UNUSED
)
2120 if (address_expr
->X_op
== O_constant
)
2124 switch (*reloc_type
)
2127 ip
->insn_opcode
|= address_expr
->X_add_number
;
2130 case BFD_RELOC_MIPS_HIGHEST
:
2131 tmp
= (address_expr
->X_add_number
+ 0x800080008000ull
) >> 48;
2132 ip
->insn_opcode
|= tmp
& 0xffff;
2135 case BFD_RELOC_MIPS_HIGHER
:
2136 tmp
= (address_expr
->X_add_number
+ 0x80008000ull
) >> 32;
2137 ip
->insn_opcode
|= tmp
& 0xffff;
2140 case BFD_RELOC_HI16_S
:
2141 tmp
= (address_expr
->X_add_number
+ 0x8000) >> 16;
2142 ip
->insn_opcode
|= tmp
& 0xffff;
2145 case BFD_RELOC_HI16
:
2146 ip
->insn_opcode
|= (address_expr
->X_add_number
>> 16) & 0xffff;
2149 case BFD_RELOC_UNUSED
:
2150 case BFD_RELOC_LO16
:
2151 case BFD_RELOC_MIPS_GOT_DISP
:
2152 ip
->insn_opcode
|= address_expr
->X_add_number
& 0xffff;
2155 case BFD_RELOC_MIPS_JMP
:
2156 if ((address_expr
->X_add_number
& 3) != 0)
2157 as_bad (_("jump to misaligned address (0x%lx)"),
2158 (unsigned long) address_expr
->X_add_number
);
2159 if (address_expr
->X_add_number
& ~0xfffffff)
2160 as_bad (_("jump address range overflow (0x%lx)"),
2161 (unsigned long) address_expr
->X_add_number
);
2162 ip
->insn_opcode
|= (address_expr
->X_add_number
>> 2) & 0x3ffffff;
2165 case BFD_RELOC_MIPS16_JMP
:
2166 if ((address_expr
->X_add_number
& 3) != 0)
2167 as_bad (_("jump to misaligned address (0x%lx)"),
2168 (unsigned long) address_expr
->X_add_number
);
2169 if (address_expr
->X_add_number
& ~0xfffffff)
2170 as_bad (_("jump address range overflow (0x%lx)"),
2171 (unsigned long) address_expr
->X_add_number
);
2173 (((address_expr
->X_add_number
& 0x7c0000) << 3)
2174 | ((address_expr
->X_add_number
& 0xf800000) >> 7)
2175 | ((address_expr
->X_add_number
& 0x3fffc) >> 2));
2178 case BFD_RELOC_16_PCREL_S2
:
2185 else if (*reloc_type
< BFD_RELOC_UNUSED
)
2188 reloc_howto_type
*howto
;
2191 /* In a compound relocation, it is the final (outermost)
2192 operator that determines the relocated field. */
2193 for (i
= 1; i
< 3; i
++)
2194 if (reloc_type
[i
] == BFD_RELOC_UNUSED
)
2197 howto
= bfd_reloc_type_lookup (stdoutput
, reloc_type
[i
- 1]);
2198 fixp
[0] = fix_new_exp (frag_now
, f
- frag_now
->fr_literal
,
2199 bfd_get_reloc_size(howto
),
2201 reloc_type
[0] == BFD_RELOC_16_PCREL_S2
,
2204 /* These relocations can have an addend that won't fit in
2205 4 octets for 64bit assembly. */
2207 && ! howto
->partial_inplace
2208 && (reloc_type
[0] == BFD_RELOC_16
2209 || reloc_type
[0] == BFD_RELOC_32
2210 || reloc_type
[0] == BFD_RELOC_MIPS_JMP
2211 || reloc_type
[0] == BFD_RELOC_HI16_S
2212 || reloc_type
[0] == BFD_RELOC_LO16
2213 || reloc_type
[0] == BFD_RELOC_GPREL16
2214 || reloc_type
[0] == BFD_RELOC_MIPS_LITERAL
2215 || reloc_type
[0] == BFD_RELOC_GPREL32
2216 || reloc_type
[0] == BFD_RELOC_64
2217 || reloc_type
[0] == BFD_RELOC_CTOR
2218 || reloc_type
[0] == BFD_RELOC_MIPS_SUB
2219 || reloc_type
[0] == BFD_RELOC_MIPS_HIGHEST
2220 || reloc_type
[0] == BFD_RELOC_MIPS_HIGHER
2221 || reloc_type
[0] == BFD_RELOC_MIPS_SCN_DISP
2222 || reloc_type
[0] == BFD_RELOC_MIPS_REL16
2223 || reloc_type
[0] == BFD_RELOC_MIPS_RELGOT
2224 || reloc_type
[0] == BFD_RELOC_MIPS16_GPREL
2225 || reloc_type
[0] == BFD_RELOC_MIPS16_HI16_S
2226 || reloc_type
[0] == BFD_RELOC_MIPS16_LO16
))
2227 fixp
[0]->fx_no_overflow
= 1;
2229 if (mips_relax
.sequence
)
2231 if (mips_relax
.first_fixup
== 0)
2232 mips_relax
.first_fixup
= fixp
[0];
2234 else if (reloc_needs_lo_p (*reloc_type
))
2236 struct mips_hi_fixup
*hi_fixup
;
2238 /* Reuse the last entry if it already has a matching %lo. */
2239 hi_fixup
= mips_hi_fixup_list
;
2241 || !fixup_has_matching_lo_p (hi_fixup
->fixp
))
2243 hi_fixup
= ((struct mips_hi_fixup
*)
2244 xmalloc (sizeof (struct mips_hi_fixup
)));
2245 hi_fixup
->next
= mips_hi_fixup_list
;
2246 mips_hi_fixup_list
= hi_fixup
;
2248 hi_fixup
->fixp
= fixp
[0];
2249 hi_fixup
->seg
= now_seg
;
2252 /* Add fixups for the second and third relocations, if given.
2253 Note that the ABI allows the second relocation to be
2254 against RSS_UNDEF, RSS_GP, RSS_GP0 or RSS_LOC. At the
2255 moment we only use RSS_UNDEF, but we could add support
2256 for the others if it ever becomes necessary. */
2257 for (i
= 1; i
< 3; i
++)
2258 if (reloc_type
[i
] != BFD_RELOC_UNUSED
)
2260 fixp
[i
] = fix_new (frag_now
, fixp
[0]->fx_where
,
2261 fixp
[0]->fx_size
, NULL
, 0,
2262 FALSE
, reloc_type
[i
]);
2264 /* Use fx_tcbit to mark compound relocs. */
2265 fixp
[0]->fx_tcbit
= 1;
2266 fixp
[i
]->fx_tcbit
= 1;
2271 if (! mips_opts
.mips16
)
2272 md_number_to_chars (f
, ip
->insn_opcode
, 4);
2273 else if (*reloc_type
== BFD_RELOC_MIPS16_JMP
)
2275 md_number_to_chars (f
, ip
->insn_opcode
>> 16, 2);
2276 md_number_to_chars (f
+ 2, ip
->insn_opcode
& 0xffff, 2);
2282 md_number_to_chars (f
, 0xf000 | ip
->extend
, 2);
2285 md_number_to_chars (f
, ip
->insn_opcode
, 2);
2288 /* Update the register mask information. */
2289 if (! mips_opts
.mips16
)
2291 if (pinfo
& INSN_WRITE_GPR_D
)
2292 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
);
2293 if ((pinfo
& (INSN_WRITE_GPR_T
| INSN_READ_GPR_T
)) != 0)
2294 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
);
2295 if (pinfo
& INSN_READ_GPR_S
)
2296 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> OP_SH_RS
) & OP_MASK_RS
);
2297 if (pinfo
& INSN_WRITE_GPR_31
)
2298 mips_gprmask
|= 1 << RA
;
2299 if (pinfo
& INSN_WRITE_FPR_D
)
2300 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FD
) & OP_MASK_FD
);
2301 if ((pinfo
& (INSN_WRITE_FPR_S
| INSN_READ_FPR_S
)) != 0)
2302 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FS
) & OP_MASK_FS
);
2303 if ((pinfo
& (INSN_WRITE_FPR_T
| INSN_READ_FPR_T
)) != 0)
2304 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FT
) & OP_MASK_FT
);
2305 if ((pinfo
& INSN_READ_FPR_R
) != 0)
2306 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FR
) & OP_MASK_FR
);
2307 if (pinfo
& INSN_COP
)
2309 /* We don't keep enough information to sort these cases out.
2310 The itbl support does keep this information however, although
2311 we currently don't support itbl fprmats as part of the cop
2312 instruction. May want to add this support in the future. */
2314 /* Never set the bit for $0, which is always zero. */
2315 mips_gprmask
&= ~1 << 0;
2319 if (pinfo
& (MIPS16_INSN_WRITE_X
| MIPS16_INSN_READ_X
))
2320 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_RX
)
2321 & MIPS16OP_MASK_RX
);
2322 if (pinfo
& (MIPS16_INSN_WRITE_Y
| MIPS16_INSN_READ_Y
))
2323 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_RY
)
2324 & MIPS16OP_MASK_RY
);
2325 if (pinfo
& MIPS16_INSN_WRITE_Z
)
2326 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_RZ
)
2327 & MIPS16OP_MASK_RZ
);
2328 if (pinfo
& (MIPS16_INSN_WRITE_T
| MIPS16_INSN_READ_T
))
2329 mips_gprmask
|= 1 << TREG
;
2330 if (pinfo
& (MIPS16_INSN_WRITE_SP
| MIPS16_INSN_READ_SP
))
2331 mips_gprmask
|= 1 << SP
;
2332 if (pinfo
& (MIPS16_INSN_WRITE_31
| MIPS16_INSN_READ_31
))
2333 mips_gprmask
|= 1 << RA
;
2334 if (pinfo
& MIPS16_INSN_WRITE_GPR_Y
)
2335 mips_gprmask
|= 1 << MIPS16OP_EXTRACT_REG32R (ip
->insn_opcode
);
2336 if (pinfo
& MIPS16_INSN_READ_Z
)
2337 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_MOVE32Z
)
2338 & MIPS16OP_MASK_MOVE32Z
);
2339 if (pinfo
& MIPS16_INSN_READ_GPR_X
)
2340 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_REGR32
)
2341 & MIPS16OP_MASK_REGR32
);
2344 if (mips_relax
.sequence
!= 2 && !mips_opts
.noreorder
)
2346 /* Filling the branch delay slot is more complex. We try to
2347 switch the branch with the previous instruction, which we can
2348 do if the previous instruction does not set up a condition
2349 that the branch tests and if the branch is not itself the
2350 target of any branch. */
2351 if ((pinfo
& INSN_UNCOND_BRANCH_DELAY
)
2352 || (pinfo
& INSN_COND_BRANCH_DELAY
))
2354 if (mips_optimize
< 2
2355 /* If we have seen .set volatile or .set nomove, don't
2357 || mips_opts
.nomove
!= 0
2358 /* If we had to emit any NOP instructions, then we
2359 already know we can not swap. */
2361 /* If we don't even know the previous insn, we can not
2363 || ! history
[0].valid_p
2364 /* If the previous insn is already in a branch delay
2365 slot, then we can not swap. */
2366 || history
[0].delay_slot_p
2367 /* If the previous previous insn was in a .set
2368 noreorder, we can't swap. Actually, the MIPS
2369 assembler will swap in this situation. However, gcc
2370 configured -with-gnu-as will generate code like
2376 in which we can not swap the bne and INSN. If gcc is
2377 not configured -with-gnu-as, it does not output the
2378 .set pseudo-ops. We don't have to check
2379 history[0].noreorder_p, because history[0].valid_p will
2380 be 0 in that case. We don't want to use
2381 history[1].valid_p, because we do want to be able
2382 to swap at the start of a function. */
2383 || history
[1].noreorder_p
2384 /* If the branch is itself the target of a branch, we
2385 can not swap. We cheat on this; all we check for is
2386 whether there is a label on this instruction. If
2387 there are any branches to anything other than a
2388 label, users must use .set noreorder. */
2389 || insn_labels
!= NULL
2390 /* If the previous instruction is in a variant frag
2391 other than this branch's one, we cannot do the swap.
2392 This does not apply to the mips16, which uses variant
2393 frags for different purposes. */
2394 || (! mips_opts
.mips16
2395 && prev_insn_frag_type
== rs_machine_dependent
)
2396 /* If the branch reads the condition codes, we don't
2397 even try to swap, because in the sequence
2402 we can not swap, and I don't feel like handling that
2404 || (! mips_opts
.mips16
2405 && (pinfo
& INSN_READ_COND_CODE
)
2406 && ! cop_interlocks
)
2407 /* We can not swap with an instruction that requires a
2408 delay slot, because the target of the branch might
2409 interfere with that instruction. */
2410 || (! mips_opts
.mips16
2412 /* Itbl support may require additional care here. */
2413 & (INSN_LOAD_COPROC_DELAY
2414 | INSN_COPROC_MOVE_DELAY
2415 | INSN_WRITE_COND_CODE
))
2416 && ! cop_interlocks
)
2417 || (! (hilo_interlocks
2418 || (mips_opts
.arch
== CPU_R3900
&& (pinfo
& INSN_MULT
)))
2422 || (! mips_opts
.mips16
2423 && (prev_pinfo
& INSN_LOAD_MEMORY_DELAY
)
2424 && ! gpr_interlocks
)
2425 || (! mips_opts
.mips16
2426 /* Itbl support may require additional care here. */
2427 && (prev_pinfo
& INSN_COPROC_MEMORY_DELAY
)
2428 && ! cop_mem_interlocks
)
2429 /* We can not swap with a branch instruction. */
2431 & (INSN_UNCOND_BRANCH_DELAY
2432 | INSN_COND_BRANCH_DELAY
2433 | INSN_COND_BRANCH_LIKELY
))
2434 /* We do not swap with a trap instruction, since it
2435 complicates trap handlers to have the trap
2436 instruction be in a delay slot. */
2437 || (prev_pinfo
& INSN_TRAP
)
2438 /* If the branch reads a register that the previous
2439 instruction sets, we can not swap. */
2440 || (! mips_opts
.mips16
2441 && (prev_pinfo
& INSN_WRITE_GPR_T
)
2442 && insn_uses_reg (ip
,
2443 ((history
[0].insn_opcode
>> OP_SH_RT
)
2446 || (! mips_opts
.mips16
2447 && (prev_pinfo
& INSN_WRITE_GPR_D
)
2448 && insn_uses_reg (ip
,
2449 ((history
[0].insn_opcode
>> OP_SH_RD
)
2452 || (mips_opts
.mips16
2453 && (((prev_pinfo
& MIPS16_INSN_WRITE_X
)
2454 && insn_uses_reg (ip
,
2455 ((history
[0].insn_opcode
2457 & MIPS16OP_MASK_RX
),
2459 || ((prev_pinfo
& MIPS16_INSN_WRITE_Y
)
2460 && insn_uses_reg (ip
,
2461 ((history
[0].insn_opcode
2463 & MIPS16OP_MASK_RY
),
2465 || ((prev_pinfo
& MIPS16_INSN_WRITE_Z
)
2466 && insn_uses_reg (ip
,
2467 ((history
[0].insn_opcode
2469 & MIPS16OP_MASK_RZ
),
2471 || ((prev_pinfo
& MIPS16_INSN_WRITE_T
)
2472 && insn_uses_reg (ip
, TREG
, MIPS_GR_REG
))
2473 || ((prev_pinfo
& MIPS16_INSN_WRITE_31
)
2474 && insn_uses_reg (ip
, RA
, MIPS_GR_REG
))
2475 || ((prev_pinfo
& MIPS16_INSN_WRITE_GPR_Y
)
2476 && insn_uses_reg (ip
,
2477 MIPS16OP_EXTRACT_REG32R
2478 (history
[0].insn_opcode
),
2480 /* If the branch writes a register that the previous
2481 instruction sets, we can not swap (we know that
2482 branches write only to RD or to $31). */
2483 || (! mips_opts
.mips16
2484 && (prev_pinfo
& INSN_WRITE_GPR_T
)
2485 && (((pinfo
& INSN_WRITE_GPR_D
)
2486 && (((history
[0].insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
)
2487 == ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)))
2488 || ((pinfo
& INSN_WRITE_GPR_31
)
2489 && (((history
[0].insn_opcode
>> OP_SH_RT
)
2492 || (! mips_opts
.mips16
2493 && (prev_pinfo
& INSN_WRITE_GPR_D
)
2494 && (((pinfo
& INSN_WRITE_GPR_D
)
2495 && (((history
[0].insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)
2496 == ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)))
2497 || ((pinfo
& INSN_WRITE_GPR_31
)
2498 && (((history
[0].insn_opcode
>> OP_SH_RD
)
2501 || (mips_opts
.mips16
2502 && (pinfo
& MIPS16_INSN_WRITE_31
)
2503 && ((prev_pinfo
& MIPS16_INSN_WRITE_31
)
2504 || ((prev_pinfo
& MIPS16_INSN_WRITE_GPR_Y
)
2505 && (MIPS16OP_EXTRACT_REG32R (history
[0].insn_opcode
)
2507 /* If the branch writes a register that the previous
2508 instruction reads, we can not swap (we know that
2509 branches only write to RD or to $31). */
2510 || (! mips_opts
.mips16
2511 && (pinfo
& INSN_WRITE_GPR_D
)
2512 && insn_uses_reg (&history
[0],
2513 ((ip
->insn_opcode
>> OP_SH_RD
)
2516 || (! mips_opts
.mips16
2517 && (pinfo
& INSN_WRITE_GPR_31
)
2518 && insn_uses_reg (&history
[0], RA
, MIPS_GR_REG
))
2519 || (mips_opts
.mips16
2520 && (pinfo
& MIPS16_INSN_WRITE_31
)
2521 && insn_uses_reg (&history
[0], RA
, MIPS_GR_REG
))
2522 /* If the previous previous instruction has a load
2523 delay, and sets a register that the branch reads, we
2525 || (! mips_opts
.mips16
2526 /* Itbl support may require additional care here. */
2527 && (((history
[1].insn_mo
->pinfo
& INSN_LOAD_COPROC_DELAY
)
2528 && ! cop_interlocks
)
2529 || ((history
[1].insn_mo
->pinfo
2530 & INSN_LOAD_MEMORY_DELAY
)
2531 && ! gpr_interlocks
))
2532 && insn_uses_reg (ip
,
2533 ((history
[1].insn_opcode
>> OP_SH_RT
)
2536 /* If one instruction sets a condition code and the
2537 other one uses a condition code, we can not swap. */
2538 || ((pinfo
& INSN_READ_COND_CODE
)
2539 && (prev_pinfo
& INSN_WRITE_COND_CODE
))
2540 || ((pinfo
& INSN_WRITE_COND_CODE
)
2541 && (prev_pinfo
& INSN_READ_COND_CODE
))
2542 /* If the previous instruction uses the PC, we can not
2544 || (mips_opts
.mips16
2545 && (prev_pinfo
& MIPS16_INSN_READ_PC
))
2546 /* If the previous instruction was extended, we can not
2548 || (mips_opts
.mips16
&& history
[0].extended_p
)
2549 /* If the previous instruction had a fixup in mips16
2550 mode, we can not swap. This normally means that the
2551 previous instruction was a 4 byte branch anyhow. */
2552 || (mips_opts
.mips16
&& history
[0].fixp
[0])
2553 /* If the previous instruction is a sync, sync.l, or
2554 sync.p, we can not swap. */
2555 || (prev_pinfo
& INSN_SYNC
))
2557 /* We could do even better for unconditional branches to
2558 portions of this object file; we could pick up the
2559 instruction at the destination, put it in the delay
2560 slot, and bump the destination address. */
2562 if (mips_relax
.sequence
)
2563 mips_relax
.sizes
[mips_relax
.sequence
- 1] += 4;
2564 /* Update the previous insn information. */
2565 history
[1].insn_mo
= ip
->insn_mo
;
2566 history
[1].use_extend
= ip
->use_extend
;
2567 history
[1].extend
= ip
->extend
;
2568 history
[1].insn_opcode
= ip
->insn_opcode
;
2569 history
[0].insn_mo
= &dummy_opcode
;
2573 /* It looks like we can actually do the swap. */
2574 if (! mips_opts
.mips16
)
2579 prev_f
= history
[0].frag
->fr_literal
+ history
[0].where
;
2580 if (!relaxed_branch
)
2582 /* If this is not a relaxed branch, then just
2583 swap the instructions. */
2584 memcpy (temp
, prev_f
, 4);
2585 memcpy (prev_f
, f
, 4);
2586 memcpy (f
, temp
, 4);
2590 /* If this is a relaxed branch, then we move the
2591 instruction to be placed in the delay slot to
2592 the current frag, shrinking the fixed part of
2593 the originating frag. If the branch occupies
2594 the tail of the latter, we move it backwards,
2595 into the space freed by the moved instruction. */
2597 memcpy (f
, prev_f
, 4);
2598 history
[0].frag
->fr_fix
-= 4;
2599 if (history
[0].frag
->fr_type
== rs_machine_dependent
)
2600 memmove (prev_f
, prev_f
+ 4, history
[0].frag
->fr_var
);
2603 if (history
[0].fixp
[0])
2605 history
[0].fixp
[0]->fx_frag
= frag_now
;
2606 history
[0].fixp
[0]->fx_where
= f
- frag_now
->fr_literal
;
2608 if (history
[0].fixp
[1])
2610 history
[0].fixp
[1]->fx_frag
= frag_now
;
2611 history
[0].fixp
[1]->fx_where
= f
- frag_now
->fr_literal
;
2613 if (history
[0].fixp
[2])
2615 history
[0].fixp
[2]->fx_frag
= frag_now
;
2616 history
[0].fixp
[2]->fx_where
= f
- frag_now
->fr_literal
;
2618 if (history
[0].fixp
[0] && HAVE_NEWABI
2619 && history
[0].frag
!= frag_now
2620 && (history
[0].fixp
[0]->fx_r_type
2621 == BFD_RELOC_MIPS_GOT_DISP
2622 || (history
[0].fixp
[0]->fx_r_type
2623 == BFD_RELOC_MIPS_CALL16
)))
2625 /* To avoid confusion in tc_gen_reloc, we must
2626 ensure that this does not become a variant
2628 force_new_frag
= TRUE
;
2631 if (!relaxed_branch
)
2635 fixp
[0]->fx_frag
= history
[0].frag
;
2636 fixp
[0]->fx_where
= history
[0].where
;
2640 fixp
[1]->fx_frag
= history
[0].frag
;
2641 fixp
[1]->fx_where
= history
[0].where
;
2645 fixp
[2]->fx_frag
= history
[0].frag
;
2646 fixp
[2]->fx_where
= history
[0].where
;
2649 else if (history
[0].frag
->fr_type
== rs_machine_dependent
)
2652 fixp
[0]->fx_where
-= 4;
2654 fixp
[1]->fx_where
-= 4;
2656 fixp
[2]->fx_where
-= 4;
2664 assert (history
[0].fixp
[0] == NULL
);
2665 assert (history
[0].fixp
[1] == NULL
);
2666 assert (history
[0].fixp
[2] == NULL
);
2667 prev_f
= history
[0].frag
->fr_literal
+ history
[0].where
;
2668 memcpy (temp
, prev_f
, 2);
2669 memcpy (prev_f
, f
, 2);
2670 if (*reloc_type
!= BFD_RELOC_MIPS16_JMP
)
2672 assert (*reloc_type
== BFD_RELOC_UNUSED
);
2673 memcpy (f
, temp
, 2);
2677 memcpy (f
, f
+ 2, 2);
2678 memcpy (f
+ 2, temp
, 2);
2682 fixp
[0]->fx_frag
= history
[0].frag
;
2683 fixp
[0]->fx_where
= history
[0].where
;
2687 fixp
[1]->fx_frag
= history
[0].frag
;
2688 fixp
[1]->fx_where
= history
[0].where
;
2692 fixp
[2]->fx_frag
= history
[0].frag
;
2693 fixp
[2]->fx_where
= history
[0].where
;
2697 /* Update the previous insn information; leave history[0]
2699 history
[1].insn_mo
= ip
->insn_mo
;
2700 history
[1].use_extend
= ip
->use_extend
;
2701 history
[1].extend
= ip
->extend
;
2702 history
[1].insn_opcode
= ip
->insn_opcode
;
2704 history
[0].delay_slot_p
= 1;
2706 /* If that was an unconditional branch, forget the previous
2707 insn information. */
2708 if (pinfo
& INSN_UNCOND_BRANCH_DELAY
)
2710 history
[1].insn_mo
= &dummy_opcode
;
2711 history
[0].insn_mo
= &dummy_opcode
;
2714 history
[0].fixp
[0] = NULL
;
2715 history
[0].fixp
[1] = NULL
;
2716 history
[0].fixp
[2] = NULL
;
2717 history
[0].reloc_type
[0] = BFD_RELOC_UNUSED
;
2718 history
[0].reloc_type
[1] = BFD_RELOC_UNUSED
;
2719 history
[0].reloc_type
[2] = BFD_RELOC_UNUSED
;
2720 history
[0].extended_p
= 0;
2722 else if (pinfo
& INSN_COND_BRANCH_LIKELY
)
2724 /* We don't yet optimize a branch likely. What we should do
2725 is look at the target, copy the instruction found there
2726 into the delay slot, and increment the branch to jump to
2727 the next instruction. */
2729 /* Update the previous insn information. */
2730 history
[1].insn_mo
= ip
->insn_mo
;
2731 history
[1].use_extend
= ip
->use_extend
;
2732 history
[1].extend
= ip
->extend
;
2733 history
[1].insn_opcode
= ip
->insn_opcode
;
2734 history
[0].insn_mo
= &dummy_opcode
;
2735 history
[0].fixp
[0] = NULL
;
2736 history
[0].fixp
[1] = NULL
;
2737 history
[0].fixp
[2] = NULL
;
2738 history
[0].reloc_type
[0] = BFD_RELOC_UNUSED
;
2739 history
[0].reloc_type
[1] = BFD_RELOC_UNUSED
;
2740 history
[0].reloc_type
[2] = BFD_RELOC_UNUSED
;
2741 history
[0].extended_p
= 0;
2742 history
[0].delay_slot_p
= 1;
2746 /* Update the previous insn information. */
2748 history
[1].insn_mo
= &dummy_opcode
;
2751 history
[1].insn_mo
= history
[0].insn_mo
;
2752 history
[1].use_extend
= history
[0].use_extend
;
2753 history
[1].extend
= history
[0].extend
;
2754 history
[1].insn_opcode
= history
[0].insn_opcode
;
2756 history
[0].insn_mo
= ip
->insn_mo
;
2757 history
[0].use_extend
= ip
->use_extend
;
2758 history
[0].extend
= ip
->extend
;
2759 history
[0].insn_opcode
= ip
->insn_opcode
;
2761 /* Any time we see a branch, we always fill the delay slot
2762 immediately; since this insn is not a branch, we know it
2763 is not in a delay slot. */
2764 history
[0].delay_slot_p
= 0;
2766 history
[0].fixp
[0] = fixp
[0];
2767 history
[0].fixp
[1] = fixp
[1];
2768 history
[0].fixp
[2] = fixp
[2];
2769 history
[0].reloc_type
[0] = reloc_type
[0];
2770 history
[0].reloc_type
[1] = reloc_type
[1];
2771 history
[0].reloc_type
[2] = reloc_type
[2];
2772 if (mips_opts
.mips16
)
2773 history
[0].extended_p
= (ip
->use_extend
2774 || *reloc_type
> BFD_RELOC_UNUSED
);
2777 history
[1].noreorder_p
= history
[0].noreorder_p
;
2778 history
[0].noreorder_p
= 0;
2779 history
[0].frag
= frag_now
;
2780 history
[0].where
= f
- frag_now
->fr_literal
;
2781 history
[0].valid_p
= 1;
2783 else if (mips_relax
.sequence
!= 2)
2785 /* We need to record a bit of information even when we are not
2786 reordering, in order to determine the base address for mips16
2787 PC relative relocs. */
2788 history
[1].insn_mo
= history
[0].insn_mo
;
2789 history
[1].use_extend
= history
[0].use_extend
;
2790 history
[1].extend
= history
[0].extend
;
2791 history
[1].insn_opcode
= history
[0].insn_opcode
;
2792 history
[0].insn_mo
= ip
->insn_mo
;
2793 history
[0].use_extend
= ip
->use_extend
;
2794 history
[0].extend
= ip
->extend
;
2795 history
[0].insn_opcode
= ip
->insn_opcode
;
2796 history
[0].reloc_type
[0] = reloc_type
[0];
2797 history
[0].reloc_type
[1] = reloc_type
[1];
2798 history
[0].reloc_type
[2] = reloc_type
[2];
2799 history
[1].noreorder_p
= history
[0].noreorder_p
;
2800 history
[0].noreorder_p
= 1;
2803 /* We just output an insn, so the next one doesn't have a label. */
2804 mips_clear_insn_labels ();
2807 /* This function forgets that there was any previous instruction or
2808 label. If PRESERVE is non-zero, it remembers enough information to
2809 know whether nops are needed before a noreorder section. */
2812 mips_no_prev_insn (int preserve
)
2816 history
[0].insn_mo
= &dummy_opcode
;
2817 history
[1].insn_mo
= &dummy_opcode
;
2818 prev_nop_frag
= NULL
;
2819 prev_nop_frag_holds
= 0;
2820 prev_nop_frag_required
= 0;
2821 prev_nop_frag_since
= 0;
2823 history
[0].valid_p
= 0;
2824 history
[0].delay_slot_p
= 0;
2825 history
[0].noreorder_p
= 0;
2826 history
[0].extended_p
= 0;
2827 history
[0].reloc_type
[0] = BFD_RELOC_UNUSED
;
2828 history
[0].reloc_type
[1] = BFD_RELOC_UNUSED
;
2829 history
[0].reloc_type
[2] = BFD_RELOC_UNUSED
;
2830 history
[1].noreorder_p
= 0;
2831 mips_clear_insn_labels ();
2834 /* This function must be called whenever we turn on noreorder or emit
2835 something other than instructions. It inserts any NOPS which might
2836 be needed by the previous instruction, and clears the information
2837 kept for the previous instructions. The INSNS parameter is true if
2838 instructions are to follow. */
2841 mips_emit_delays (bfd_boolean insns
)
2843 if (! mips_opts
.noreorder
)
2848 if ((! mips_opts
.mips16
2849 && ((history
[0].insn_mo
->pinfo
2850 & (INSN_LOAD_COPROC_DELAY
2851 | INSN_COPROC_MOVE_DELAY
2852 | INSN_WRITE_COND_CODE
))
2853 && ! cop_interlocks
))
2854 || (! hilo_interlocks
2855 && (history
[0].insn_mo
->pinfo
2858 || (! mips_opts
.mips16
2859 && (history
[0].insn_mo
->pinfo
& INSN_LOAD_MEMORY_DELAY
)
2860 && ! gpr_interlocks
)
2861 || (! mips_opts
.mips16
2862 && (history
[0].insn_mo
->pinfo
& INSN_COPROC_MEMORY_DELAY
)
2863 && ! cop_mem_interlocks
))
2865 /* Itbl support may require additional care here. */
2867 if ((! mips_opts
.mips16
2868 && ((history
[0].insn_mo
->pinfo
& INSN_WRITE_COND_CODE
)
2869 && ! cop_interlocks
))
2870 || (! hilo_interlocks
2871 && ((history
[0].insn_mo
->pinfo
& INSN_READ_HI
)
2872 || (history
[0].insn_mo
->pinfo
& INSN_READ_LO
))))
2875 if (history
[0].noreorder_p
)
2878 else if ((! mips_opts
.mips16
2879 && ((history
[1].insn_mo
->pinfo
& INSN_WRITE_COND_CODE
)
2880 && ! cop_interlocks
))
2881 || (! hilo_interlocks
2882 && ((history
[1].insn_mo
->pinfo
& INSN_READ_HI
)
2883 || (history
[1].insn_mo
->pinfo
& INSN_READ_LO
))))
2885 /* Itbl support may require additional care here. */
2886 if (! history
[1].noreorder_p
)
2890 if (mips_fix_vr4120
&& history
[0].insn_mo
->name
)
2893 const char *pn
= history
[0].insn_mo
->name
;
2894 if (strncmp (pn
, "macc", 4) == 0
2895 || strncmp (pn
, "dmacc", 5) == 0
2896 || strncmp (pn
, "dmult", 5) == 0
2897 || strstr (pn
, "div"))
2899 if (nops
< min_nops
)
2905 struct insn_label_list
*l
;
2909 /* Record the frag which holds the nop instructions, so
2910 that we can remove them if we don't need them. */
2911 frag_grow (mips_opts
.mips16
? nops
* 2 : nops
* 4);
2912 prev_nop_frag
= frag_now
;
2913 prev_nop_frag_holds
= nops
;
2914 prev_nop_frag_required
= 0;
2915 prev_nop_frag_since
= 0;
2918 for (; nops
> 0; --nops
)
2923 /* Move on to a new frag, so that it is safe to simply
2924 decrease the size of prev_nop_frag. */
2925 frag_wane (frag_now
);
2929 for (l
= insn_labels
; l
!= NULL
; l
= l
->next
)
2933 assert (S_GET_SEGMENT (l
->label
) == now_seg
);
2934 symbol_set_frag (l
->label
, frag_now
);
2935 val
= (valueT
) frag_now_fix ();
2936 /* mips16 text labels are stored as odd. */
2937 if (mips_opts
.mips16
)
2939 S_SET_VALUE (l
->label
, val
);
2944 /* Mark instruction labels in mips16 mode. */
2946 mips16_mark_labels ();
2948 mips_no_prev_insn (insns
);
2951 /* Set up global variables for the start of a new macro. */
2956 memset (&mips_macro_warning
.sizes
, 0, sizeof (mips_macro_warning
.sizes
));
2957 mips_macro_warning
.delay_slot_p
= (mips_opts
.noreorder
2958 && (history
[0].insn_mo
->pinfo
2959 & (INSN_UNCOND_BRANCH_DELAY
2960 | INSN_COND_BRANCH_DELAY
2961 | INSN_COND_BRANCH_LIKELY
)) != 0);
2964 /* Given that a macro is longer than 4 bytes, return the appropriate warning
2965 for it. Return null if no warning is needed. SUBTYPE is a bitmask of
2966 RELAX_DELAY_SLOT and RELAX_NOMACRO. */
2969 macro_warning (relax_substateT subtype
)
2971 if (subtype
& RELAX_DELAY_SLOT
)
2972 return _("Macro instruction expanded into multiple instructions"
2973 " in a branch delay slot");
2974 else if (subtype
& RELAX_NOMACRO
)
2975 return _("Macro instruction expanded into multiple instructions");
2980 /* Finish up a macro. Emit warnings as appropriate. */
2985 if (mips_macro_warning
.sizes
[0] > 4 || mips_macro_warning
.sizes
[1] > 4)
2987 relax_substateT subtype
;
2989 /* Set up the relaxation warning flags. */
2991 if (mips_macro_warning
.sizes
[1] > mips_macro_warning
.sizes
[0])
2992 subtype
|= RELAX_SECOND_LONGER
;
2993 if (mips_opts
.warn_about_macros
)
2994 subtype
|= RELAX_NOMACRO
;
2995 if (mips_macro_warning
.delay_slot_p
)
2996 subtype
|= RELAX_DELAY_SLOT
;
2998 if (mips_macro_warning
.sizes
[0] > 4 && mips_macro_warning
.sizes
[1] > 4)
3000 /* Either the macro has a single implementation or both
3001 implementations are longer than 4 bytes. Emit the
3003 const char *msg
= macro_warning (subtype
);
3009 /* One implementation might need a warning but the other
3010 definitely doesn't. */
3011 mips_macro_warning
.first_frag
->fr_subtype
|= subtype
;
3016 /* Read a macro's relocation codes from *ARGS and store them in *R.
3017 The first argument in *ARGS will be either the code for a single
3018 relocation or -1 followed by the three codes that make up a
3019 composite relocation. */
3022 macro_read_relocs (va_list *args
, bfd_reloc_code_real_type
*r
)
3026 next
= va_arg (*args
, int);
3028 r
[0] = (bfd_reloc_code_real_type
) next
;
3030 for (i
= 0; i
< 3; i
++)
3031 r
[i
] = (bfd_reloc_code_real_type
) va_arg (*args
, int);
3034 /* Build an instruction created by a macro expansion. This is passed
3035 a pointer to the count of instructions created so far, an
3036 expression, the name of the instruction to build, an operand format
3037 string, and corresponding arguments. */
3040 macro_build (expressionS
*ep
, const char *name
, const char *fmt
, ...)
3042 struct mips_cl_insn insn
;
3043 bfd_reloc_code_real_type r
[3];
3046 va_start (args
, fmt
);
3048 if (mips_opts
.mips16
)
3050 mips16_macro_build (ep
, name
, fmt
, args
);
3055 r
[0] = BFD_RELOC_UNUSED
;
3056 r
[1] = BFD_RELOC_UNUSED
;
3057 r
[2] = BFD_RELOC_UNUSED
;
3058 insn
.insn_mo
= (struct mips_opcode
*) hash_find (op_hash
, name
);
3059 assert (insn
.insn_mo
);
3060 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
3062 /* Search until we get a match for NAME. */
3065 /* It is assumed here that macros will never generate
3066 MDMX or MIPS-3D instructions. */
3067 if (strcmp (fmt
, insn
.insn_mo
->args
) == 0
3068 && insn
.insn_mo
->pinfo
!= INSN_MACRO
3069 && OPCODE_IS_MEMBER (insn
.insn_mo
,
3071 | (file_ase_mips16
? INSN_MIPS16
: 0)),
3073 && (mips_opts
.arch
!= CPU_R4650
|| (insn
.insn_mo
->pinfo
& FP_D
) == 0))
3077 assert (insn
.insn_mo
->name
);
3078 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
3081 insn
.insn_opcode
= insn
.insn_mo
->match
;
3099 insn
.insn_opcode
|= (va_arg (args
, int)
3100 & OP_MASK_SHAMT
) << OP_SH_SHAMT
;
3105 /* Note that in the macro case, these arguments are already
3106 in MSB form. (When handling the instruction in the
3107 non-macro case, these arguments are sizes from which
3108 MSB values must be calculated.) */
3109 insn
.insn_opcode
|= (va_arg (args
, int)
3110 & OP_MASK_INSMSB
) << OP_SH_INSMSB
;
3116 /* Note that in the macro case, these arguments are already
3117 in MSBD form. (When handling the instruction in the
3118 non-macro case, these arguments are sizes from which
3119 MSBD values must be calculated.) */
3120 insn
.insn_opcode
|= (va_arg (args
, int)
3121 & OP_MASK_EXTMSBD
) << OP_SH_EXTMSBD
;
3132 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_RT
;
3136 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_CODE
;
3141 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_FT
;
3147 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_RD
;
3152 int tmp
= va_arg (args
, int);
3154 insn
.insn_opcode
|= tmp
<< OP_SH_RT
;
3155 insn
.insn_opcode
|= tmp
<< OP_SH_RD
;
3161 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_FS
;
3168 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_SHAMT
;
3172 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_FD
;
3176 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_CODE20
;
3180 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_CODE19
;
3184 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_CODE2
;
3191 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_RS
;
3197 macro_read_relocs (&args
, r
);
3198 assert (*r
== BFD_RELOC_GPREL16
3199 || *r
== BFD_RELOC_MIPS_LITERAL
3200 || *r
== BFD_RELOC_MIPS_HIGHER
3201 || *r
== BFD_RELOC_HI16_S
3202 || *r
== BFD_RELOC_LO16
3203 || *r
== BFD_RELOC_MIPS_GOT16
3204 || *r
== BFD_RELOC_MIPS_CALL16
3205 || *r
== BFD_RELOC_MIPS_GOT_DISP
3206 || *r
== BFD_RELOC_MIPS_GOT_PAGE
3207 || *r
== BFD_RELOC_MIPS_GOT_OFST
3208 || *r
== BFD_RELOC_MIPS_GOT_LO16
3209 || *r
== BFD_RELOC_MIPS_CALL_LO16
);
3213 macro_read_relocs (&args
, r
);
3215 && (ep
->X_op
== O_constant
3216 || (ep
->X_op
== O_symbol
3217 && (*r
== BFD_RELOC_MIPS_HIGHEST
3218 || *r
== BFD_RELOC_HI16_S
3219 || *r
== BFD_RELOC_HI16
3220 || *r
== BFD_RELOC_GPREL16
3221 || *r
== BFD_RELOC_MIPS_GOT_HI16
3222 || *r
== BFD_RELOC_MIPS_CALL_HI16
))));
3226 assert (ep
!= NULL
);
3228 * This allows macro() to pass an immediate expression for
3229 * creating short branches without creating a symbol.
3230 * Note that the expression still might come from the assembly
3231 * input, in which case the value is not checked for range nor
3232 * is a relocation entry generated (yuck).
3234 if (ep
->X_op
== O_constant
)
3236 insn
.insn_opcode
|= (ep
->X_add_number
>> 2) & 0xffff;
3240 *r
= BFD_RELOC_16_PCREL_S2
;
3244 assert (ep
!= NULL
);
3245 *r
= BFD_RELOC_MIPS_JMP
;
3249 insn
.insn_opcode
|= va_arg (args
, unsigned long);
3258 assert (*r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
3260 append_insn (&insn
, ep
, r
);
3264 mips16_macro_build (expressionS
*ep
, const char *name
, const char *fmt
,
3267 struct mips_cl_insn insn
;
3268 bfd_reloc_code_real_type r
[3]
3269 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
3271 insn
.insn_mo
= (struct mips_opcode
*) hash_find (mips16_op_hash
, name
);
3272 assert (insn
.insn_mo
);
3273 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
3275 while (strcmp (fmt
, insn
.insn_mo
->args
) != 0
3276 || insn
.insn_mo
->pinfo
== INSN_MACRO
)
3279 assert (insn
.insn_mo
->name
);
3280 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
3283 insn
.insn_opcode
= insn
.insn_mo
->match
;
3284 insn
.use_extend
= FALSE
;
3303 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_RY
;
3308 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_RX
;
3312 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_RZ
;
3316 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_MOVE32Z
;
3326 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_REGR32
;
3333 regno
= va_arg (args
, int);
3334 regno
= ((regno
& 7) << 2) | ((regno
& 0x18) >> 3);
3335 insn
.insn_opcode
|= regno
<< MIPS16OP_SH_REG32R
;
3356 assert (ep
!= NULL
);
3358 if (ep
->X_op
!= O_constant
)
3359 *r
= (int) BFD_RELOC_UNUSED
+ c
;
3362 mips16_immed (NULL
, 0, c
, ep
->X_add_number
, FALSE
, FALSE
,
3363 FALSE
, &insn
.insn_opcode
, &insn
.use_extend
,
3366 *r
= BFD_RELOC_UNUSED
;
3372 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_IMM6
;
3379 assert (*r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
3381 append_insn (&insn
, ep
, r
);
3385 * Generate a "jalr" instruction with a relocation hint to the called
3386 * function. This occurs in NewABI PIC code.
3389 macro_build_jalr (expressionS
*ep
)
3398 macro_build (NULL
, "jalr", "d,s", RA
, PIC_CALL_REG
);
3400 fix_new_exp (frag_now
, f
- frag_now
->fr_literal
,
3401 4, ep
, FALSE
, BFD_RELOC_MIPS_JALR
);
3405 * Generate a "lui" instruction.
3408 macro_build_lui (expressionS
*ep
, int regnum
)
3410 expressionS high_expr
;
3411 struct mips_cl_insn insn
;
3412 bfd_reloc_code_real_type r
[3]
3413 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
3414 const char *name
= "lui";
3415 const char *fmt
= "t,u";
3417 assert (! mips_opts
.mips16
);
3421 if (high_expr
.X_op
== O_constant
)
3423 /* we can compute the instruction now without a relocation entry */
3424 high_expr
.X_add_number
= ((high_expr
.X_add_number
+ 0x8000)
3426 *r
= BFD_RELOC_UNUSED
;
3430 assert (ep
->X_op
== O_symbol
);
3431 /* _gp_disp is a special case, used from s_cpload.
3432 __gnu_local_gp is used if mips_no_shared. */
3433 assert (mips_pic
== NO_PIC
3435 && strcmp (S_GET_NAME (ep
->X_add_symbol
), "_gp_disp") == 0)
3436 || (! mips_in_shared
3437 && strcmp (S_GET_NAME (ep
->X_add_symbol
),
3438 "__gnu_local_gp") == 0));
3439 *r
= BFD_RELOC_HI16_S
;
3442 insn
.insn_mo
= (struct mips_opcode
*) hash_find (op_hash
, name
);
3443 assert (insn
.insn_mo
);
3444 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
3445 assert (strcmp (fmt
, insn
.insn_mo
->args
) == 0);
3447 insn
.insn_opcode
= insn
.insn_mo
->match
| (regnum
<< OP_SH_RT
);
3448 if (*r
== BFD_RELOC_UNUSED
)
3450 insn
.insn_opcode
|= high_expr
.X_add_number
;
3451 append_insn (&insn
, NULL
, r
);
3454 append_insn (&insn
, &high_expr
, r
);
3457 /* Generate a sequence of instructions to do a load or store from a constant
3458 offset off of a base register (breg) into/from a target register (treg),
3459 using AT if necessary. */
3461 macro_build_ldst_constoffset (expressionS
*ep
, const char *op
,
3462 int treg
, int breg
, int dbl
)
3464 assert (ep
->X_op
== O_constant
);
3466 /* Sign-extending 32-bit constants makes their handling easier. */
3467 if (! dbl
&& ! ((ep
->X_add_number
& ~((bfd_vma
) 0x7fffffff))
3468 == ~((bfd_vma
) 0x7fffffff)))
3470 if (ep
->X_add_number
& ~((bfd_vma
) 0xffffffff))
3471 as_bad (_("constant too large"));
3473 ep
->X_add_number
= (((ep
->X_add_number
& 0xffffffff) ^ 0x80000000)
3477 /* Right now, this routine can only handle signed 32-bit constants. */
3478 if (! IS_SEXT_32BIT_NUM(ep
->X_add_number
+ 0x8000))
3479 as_warn (_("operand overflow"));
3481 if (IS_SEXT_16BIT_NUM(ep
->X_add_number
))
3483 /* Signed 16-bit offset will fit in the op. Easy! */
3484 macro_build (ep
, op
, "t,o(b)", treg
, BFD_RELOC_LO16
, breg
);
3488 /* 32-bit offset, need multiple instructions and AT, like:
3489 lui $tempreg,const_hi (BFD_RELOC_HI16_S)
3490 addu $tempreg,$tempreg,$breg
3491 <op> $treg,const_lo($tempreg) (BFD_RELOC_LO16)
3492 to handle the complete offset. */
3493 macro_build_lui (ep
, AT
);
3494 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, AT
, breg
);
3495 macro_build (ep
, op
, "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
3498 as_bad (_("Macro used $at after \".set noat\""));
3503 * Generates code to set the $at register to true (one)
3504 * if reg is less than the immediate expression.
3507 set_at (int reg
, int unsignedp
)
3509 if (imm_expr
.X_op
== O_constant
3510 && imm_expr
.X_add_number
>= -0x8000
3511 && imm_expr
.X_add_number
< 0x8000)
3512 macro_build (&imm_expr
, unsignedp
? "sltiu" : "slti", "t,r,j",
3513 AT
, reg
, BFD_RELOC_LO16
);
3516 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
3517 macro_build (NULL
, unsignedp
? "sltu" : "slt", "d,v,t", AT
, reg
, AT
);
3522 normalize_constant_expr (expressionS
*ex
)
3524 if (ex
->X_op
== O_constant
&& HAVE_32BIT_GPRS
)
3525 ex
->X_add_number
= (((ex
->X_add_number
& 0xffffffff) ^ 0x80000000)
3529 /* Warn if an expression is not a constant. */
3532 check_absolute_expr (struct mips_cl_insn
*ip
, expressionS
*ex
)
3534 if (ex
->X_op
== O_big
)
3535 as_bad (_("unsupported large constant"));
3536 else if (ex
->X_op
!= O_constant
)
3537 as_bad (_("Instruction %s requires absolute expression"), ip
->insn_mo
->name
);
3539 normalize_constant_expr (ex
);
3542 /* Count the leading zeroes by performing a binary chop. This is a
3543 bulky bit of source, but performance is a LOT better for the
3544 majority of values than a simple loop to count the bits:
3545 for (lcnt = 0; (lcnt < 32); lcnt++)
3546 if ((v) & (1 << (31 - lcnt)))
3548 However it is not code size friendly, and the gain will drop a bit
3549 on certain cached systems.
3551 #define COUNT_TOP_ZEROES(v) \
3552 (((v) & ~0xffff) == 0 \
3553 ? ((v) & ~0xff) == 0 \
3554 ? ((v) & ~0xf) == 0 \
3555 ? ((v) & ~0x3) == 0 \
3556 ? ((v) & ~0x1) == 0 \
3561 : ((v) & ~0x7) == 0 \
3564 : ((v) & ~0x3f) == 0 \
3565 ? ((v) & ~0x1f) == 0 \
3568 : ((v) & ~0x7f) == 0 \
3571 : ((v) & ~0xfff) == 0 \
3572 ? ((v) & ~0x3ff) == 0 \
3573 ? ((v) & ~0x1ff) == 0 \
3576 : ((v) & ~0x7ff) == 0 \
3579 : ((v) & ~0x3fff) == 0 \
3580 ? ((v) & ~0x1fff) == 0 \
3583 : ((v) & ~0x7fff) == 0 \
3586 : ((v) & ~0xffffff) == 0 \
3587 ? ((v) & ~0xfffff) == 0 \
3588 ? ((v) & ~0x3ffff) == 0 \
3589 ? ((v) & ~0x1ffff) == 0 \
3592 : ((v) & ~0x7ffff) == 0 \
3595 : ((v) & ~0x3fffff) == 0 \
3596 ? ((v) & ~0x1fffff) == 0 \
3599 : ((v) & ~0x7fffff) == 0 \
3602 : ((v) & ~0xfffffff) == 0 \
3603 ? ((v) & ~0x3ffffff) == 0 \
3604 ? ((v) & ~0x1ffffff) == 0 \
3607 : ((v) & ~0x7ffffff) == 0 \
3610 : ((v) & ~0x3fffffff) == 0 \
3611 ? ((v) & ~0x1fffffff) == 0 \
3614 : ((v) & ~0x7fffffff) == 0 \
3619 * This routine generates the least number of instructions necessary to load
3620 * an absolute expression value into a register.
3623 load_register (int reg
, expressionS
*ep
, int dbl
)
3626 expressionS hi32
, lo32
;
3628 if (ep
->X_op
!= O_big
)
3630 assert (ep
->X_op
== O_constant
);
3632 /* Sign-extending 32-bit constants makes their handling easier. */
3633 if (! dbl
&& ! ((ep
->X_add_number
& ~((bfd_vma
) 0x7fffffff))
3634 == ~((bfd_vma
) 0x7fffffff)))
3636 if (ep
->X_add_number
& ~((bfd_vma
) 0xffffffff))
3637 as_bad (_("constant too large"));
3639 ep
->X_add_number
= (((ep
->X_add_number
& 0xffffffff) ^ 0x80000000)
3643 if (IS_SEXT_16BIT_NUM (ep
->X_add_number
))
3645 /* We can handle 16 bit signed values with an addiu to
3646 $zero. No need to ever use daddiu here, since $zero and
3647 the result are always correct in 32 bit mode. */
3648 macro_build (ep
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
3651 else if (ep
->X_add_number
>= 0 && ep
->X_add_number
< 0x10000)
3653 /* We can handle 16 bit unsigned values with an ori to
3655 macro_build (ep
, "ori", "t,r,i", reg
, 0, BFD_RELOC_LO16
);
3658 else if ((IS_SEXT_32BIT_NUM (ep
->X_add_number
)))
3660 /* 32 bit values require an lui. */
3661 macro_build (ep
, "lui", "t,u", reg
, BFD_RELOC_HI16
);
3662 if ((ep
->X_add_number
& 0xffff) != 0)
3663 macro_build (ep
, "ori", "t,r,i", reg
, reg
, BFD_RELOC_LO16
);
3668 /* The value is larger than 32 bits. */
3670 if (HAVE_32BIT_GPRS
)
3672 as_bad (_("Number (0x%lx) larger than 32 bits"),
3673 (unsigned long) ep
->X_add_number
);
3674 macro_build (ep
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
3678 if (ep
->X_op
!= O_big
)
3681 hi32
.X_add_number
= (valueT
) hi32
.X_add_number
>> 16;
3682 hi32
.X_add_number
= (valueT
) hi32
.X_add_number
>> 16;
3683 hi32
.X_add_number
&= 0xffffffff;
3685 lo32
.X_add_number
&= 0xffffffff;
3689 assert (ep
->X_add_number
> 2);
3690 if (ep
->X_add_number
== 3)
3691 generic_bignum
[3] = 0;
3692 else if (ep
->X_add_number
> 4)
3693 as_bad (_("Number larger than 64 bits"));
3694 lo32
.X_op
= O_constant
;
3695 lo32
.X_add_number
= generic_bignum
[0] + (generic_bignum
[1] << 16);
3696 hi32
.X_op
= O_constant
;
3697 hi32
.X_add_number
= generic_bignum
[2] + (generic_bignum
[3] << 16);
3700 if (hi32
.X_add_number
== 0)
3705 unsigned long hi
, lo
;
3707 if (hi32
.X_add_number
== (offsetT
) 0xffffffff)
3709 if ((lo32
.X_add_number
& 0xffff8000) == 0xffff8000)
3711 macro_build (&lo32
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
3714 if (lo32
.X_add_number
& 0x80000000)
3716 macro_build (&lo32
, "lui", "t,u", reg
, BFD_RELOC_HI16
);
3717 if (lo32
.X_add_number
& 0xffff)
3718 macro_build (&lo32
, "ori", "t,r,i", reg
, reg
, BFD_RELOC_LO16
);
3723 /* Check for 16bit shifted constant. We know that hi32 is
3724 non-zero, so start the mask on the first bit of the hi32
3729 unsigned long himask
, lomask
;
3733 himask
= 0xffff >> (32 - shift
);
3734 lomask
= (0xffff << shift
) & 0xffffffff;
3738 himask
= 0xffff << (shift
- 32);
3741 if ((hi32
.X_add_number
& ~(offsetT
) himask
) == 0
3742 && (lo32
.X_add_number
& ~(offsetT
) lomask
) == 0)
3746 tmp
.X_op
= O_constant
;
3748 tmp
.X_add_number
= ((hi32
.X_add_number
<< (32 - shift
))
3749 | (lo32
.X_add_number
>> shift
));
3751 tmp
.X_add_number
= hi32
.X_add_number
>> (shift
- 32);
3752 macro_build (&tmp
, "ori", "t,r,i", reg
, 0, BFD_RELOC_LO16
);
3753 macro_build (NULL
, (shift
>= 32) ? "dsll32" : "dsll", "d,w,<",
3754 reg
, reg
, (shift
>= 32) ? shift
- 32 : shift
);
3759 while (shift
<= (64 - 16));
3761 /* Find the bit number of the lowest one bit, and store the
3762 shifted value in hi/lo. */
3763 hi
= (unsigned long) (hi32
.X_add_number
& 0xffffffff);
3764 lo
= (unsigned long) (lo32
.X_add_number
& 0xffffffff);
3768 while ((lo
& 1) == 0)
3773 lo
|= (hi
& (((unsigned long) 1 << bit
) - 1)) << (32 - bit
);
3779 while ((hi
& 1) == 0)
3788 /* Optimize if the shifted value is a (power of 2) - 1. */
3789 if ((hi
== 0 && ((lo
+ 1) & lo
) == 0)
3790 || (lo
== 0xffffffff && ((hi
+ 1) & hi
) == 0))
3792 shift
= COUNT_TOP_ZEROES ((unsigned int) hi32
.X_add_number
);
3797 /* This instruction will set the register to be all
3799 tmp
.X_op
= O_constant
;
3800 tmp
.X_add_number
= (offsetT
) -1;
3801 macro_build (&tmp
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
3805 macro_build (NULL
, (bit
>= 32) ? "dsll32" : "dsll", "d,w,<",
3806 reg
, reg
, (bit
>= 32) ? bit
- 32 : bit
);
3808 macro_build (NULL
, (shift
>= 32) ? "dsrl32" : "dsrl", "d,w,<",
3809 reg
, reg
, (shift
>= 32) ? shift
- 32 : shift
);
3814 /* Sign extend hi32 before calling load_register, because we can
3815 generally get better code when we load a sign extended value. */
3816 if ((hi32
.X_add_number
& 0x80000000) != 0)
3817 hi32
.X_add_number
|= ~(offsetT
) 0xffffffff;
3818 load_register (reg
, &hi32
, 0);
3821 if ((lo32
.X_add_number
& 0xffff0000) == 0)
3825 macro_build (NULL
, "dsll32", "d,w,<", reg
, freg
, 0);
3833 if ((freg
== 0) && (lo32
.X_add_number
== (offsetT
) 0xffffffff))
3835 macro_build (&lo32
, "lui", "t,u", reg
, BFD_RELOC_HI16
);
3836 macro_build (NULL
, "dsrl32", "d,w,<", reg
, reg
, 0);
3842 macro_build (NULL
, "dsll", "d,w,<", reg
, freg
, 16);
3846 mid16
.X_add_number
>>= 16;
3847 macro_build (&mid16
, "ori", "t,r,i", reg
, freg
, BFD_RELOC_LO16
);
3848 macro_build (NULL
, "dsll", "d,w,<", reg
, reg
, 16);
3851 if ((lo32
.X_add_number
& 0xffff) != 0)
3852 macro_build (&lo32
, "ori", "t,r,i", reg
, freg
, BFD_RELOC_LO16
);
3856 load_delay_nop (void)
3858 if (!gpr_interlocks
)
3859 macro_build (NULL
, "nop", "");
3862 /* Load an address into a register. */
3865 load_address (int reg
, expressionS
*ep
, int *used_at
)
3867 if (ep
->X_op
!= O_constant
3868 && ep
->X_op
!= O_symbol
)
3870 as_bad (_("expression too complex"));
3871 ep
->X_op
= O_constant
;
3874 if (ep
->X_op
== O_constant
)
3876 load_register (reg
, ep
, HAVE_64BIT_ADDRESSES
);
3880 if (mips_pic
== NO_PIC
)
3882 /* If this is a reference to a GP relative symbol, we want
3883 addiu $reg,$gp,<sym> (BFD_RELOC_GPREL16)
3885 lui $reg,<sym> (BFD_RELOC_HI16_S)
3886 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
3887 If we have an addend, we always use the latter form.
3889 With 64bit address space and a usable $at we want
3890 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
3891 lui $at,<sym> (BFD_RELOC_HI16_S)
3892 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
3893 daddiu $at,<sym> (BFD_RELOC_LO16)
3897 If $at is already in use, we use a path which is suboptimal
3898 on superscalar processors.
3899 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
3900 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
3902 daddiu $reg,<sym> (BFD_RELOC_HI16_S)
3904 daddiu $reg,<sym> (BFD_RELOC_LO16)
3906 For GP relative symbols in 64bit address space we can use
3907 the same sequence as in 32bit address space. */
3908 if (HAVE_64BIT_SYMBOLS
)
3910 if ((valueT
) ep
->X_add_number
<= MAX_GPREL_OFFSET
3911 && !nopic_need_relax (ep
->X_add_symbol
, 1))
3913 relax_start (ep
->X_add_symbol
);
3914 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
,
3915 mips_gp_register
, BFD_RELOC_GPREL16
);
3919 if (*used_at
== 0 && !mips_opts
.noat
)
3921 macro_build (ep
, "lui", "t,u", reg
, BFD_RELOC_MIPS_HIGHEST
);
3922 macro_build (ep
, "lui", "t,u", AT
, BFD_RELOC_HI16_S
);
3923 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
,
3924 BFD_RELOC_MIPS_HIGHER
);
3925 macro_build (ep
, "daddiu", "t,r,j", AT
, AT
, BFD_RELOC_LO16
);
3926 macro_build (NULL
, "dsll32", "d,w,<", reg
, reg
, 0);
3927 macro_build (NULL
, "daddu", "d,v,t", reg
, reg
, AT
);
3932 macro_build (ep
, "lui", "t,u", reg
, BFD_RELOC_MIPS_HIGHEST
);
3933 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
,
3934 BFD_RELOC_MIPS_HIGHER
);
3935 macro_build (NULL
, "dsll", "d,w,<", reg
, reg
, 16);
3936 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
, BFD_RELOC_HI16_S
);
3937 macro_build (NULL
, "dsll", "d,w,<", reg
, reg
, 16);
3938 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
, BFD_RELOC_LO16
);
3941 if (mips_relax
.sequence
)
3946 if ((valueT
) ep
->X_add_number
<= MAX_GPREL_OFFSET
3947 && !nopic_need_relax (ep
->X_add_symbol
, 1))
3949 relax_start (ep
->X_add_symbol
);
3950 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
,
3951 mips_gp_register
, BFD_RELOC_GPREL16
);
3954 macro_build_lui (ep
, reg
);
3955 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j",
3956 reg
, reg
, BFD_RELOC_LO16
);
3957 if (mips_relax
.sequence
)
3961 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
3965 /* If this is a reference to an external symbol, we want
3966 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3968 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3970 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
3971 If there is a constant, it must be added in after.
3973 If we have NewABI, we want
3974 lw $reg,<sym+cst>($gp) (BFD_RELOC_MIPS_GOT_DISP)
3975 unless we're referencing a global symbol with a non-zero
3976 offset, in which case cst must be added separately. */
3979 if (ep
->X_add_number
)
3981 ex
.X_add_number
= ep
->X_add_number
;
3982 ep
->X_add_number
= 0;
3983 relax_start (ep
->X_add_symbol
);
3984 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
3985 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
3986 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
3987 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
3988 ex
.X_op
= O_constant
;
3989 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j",
3990 reg
, reg
, BFD_RELOC_LO16
);
3991 ep
->X_add_number
= ex
.X_add_number
;
3994 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
3995 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
3996 if (mips_relax
.sequence
)
4001 ex
.X_add_number
= ep
->X_add_number
;
4002 ep
->X_add_number
= 0;
4003 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
4004 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
4006 relax_start (ep
->X_add_symbol
);
4008 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
4012 if (ex
.X_add_number
!= 0)
4014 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
4015 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
4016 ex
.X_op
= O_constant
;
4017 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j",
4018 reg
, reg
, BFD_RELOC_LO16
);
4022 else if (mips_pic
== SVR4_PIC
)
4026 /* This is the large GOT case. If this is a reference to an
4027 external symbol, we want
4028 lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
4030 lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16)
4032 Otherwise, for a reference to a local symbol in old ABI, we want
4033 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4035 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
4036 If there is a constant, it must be added in after.
4038 In the NewABI, for local symbols, with or without offsets, we want:
4039 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
4040 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
4044 ex
.X_add_number
= ep
->X_add_number
;
4045 ep
->X_add_number
= 0;
4046 relax_start (ep
->X_add_symbol
);
4047 macro_build (ep
, "lui", "t,u", reg
, BFD_RELOC_MIPS_GOT_HI16
);
4048 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
4049 reg
, reg
, mips_gp_register
);
4050 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)",
4051 reg
, BFD_RELOC_MIPS_GOT_LO16
, reg
);
4052 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
4053 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
4054 else if (ex
.X_add_number
)
4056 ex
.X_op
= O_constant
;
4057 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
4061 ep
->X_add_number
= ex
.X_add_number
;
4063 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
4064 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
4065 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
4066 BFD_RELOC_MIPS_GOT_OFST
);
4071 ex
.X_add_number
= ep
->X_add_number
;
4072 ep
->X_add_number
= 0;
4073 relax_start (ep
->X_add_symbol
);
4074 macro_build (ep
, "lui", "t,u", reg
, BFD_RELOC_MIPS_GOT_HI16
);
4075 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
4076 reg
, reg
, mips_gp_register
);
4077 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)",
4078 reg
, BFD_RELOC_MIPS_GOT_LO16
, reg
);
4080 if (reg_needs_delay (mips_gp_register
))
4082 /* We need a nop before loading from $gp. This special
4083 check is required because the lui which starts the main
4084 instruction stream does not refer to $gp, and so will not
4085 insert the nop which may be required. */
4086 macro_build (NULL
, "nop", "");
4088 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
4089 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
4091 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
4095 if (ex
.X_add_number
!= 0)
4097 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
4098 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
4099 ex
.X_op
= O_constant
;
4100 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
4108 if (mips_opts
.noat
&& *used_at
== 1)
4109 as_bad (_("Macro used $at after \".set noat\""));
4112 /* Move the contents of register SOURCE into register DEST. */
4115 move_register (int dest
, int source
)
4117 macro_build (NULL
, HAVE_32BIT_GPRS
? "addu" : "daddu", "d,v,t",
4121 /* Emit an SVR4 PIC sequence to load address LOCAL into DEST, where
4122 LOCAL is the sum of a symbol and a 16-bit or 32-bit displacement.
4123 The two alternatives are:
4125 Global symbol Local sybmol
4126 ------------- ------------
4127 lw DEST,%got(SYMBOL) lw DEST,%got(SYMBOL + OFFSET)
4129 addiu DEST,DEST,OFFSET addiu DEST,DEST,%lo(SYMBOL + OFFSET)
4131 load_got_offset emits the first instruction and add_got_offset
4132 emits the second for a 16-bit offset or add_got_offset_hilo emits
4133 a sequence to add a 32-bit offset using a scratch register. */
4136 load_got_offset (int dest
, expressionS
*local
)
4141 global
.X_add_number
= 0;
4143 relax_start (local
->X_add_symbol
);
4144 macro_build (&global
, ADDRESS_LOAD_INSN
, "t,o(b)", dest
,
4145 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
4147 macro_build (local
, ADDRESS_LOAD_INSN
, "t,o(b)", dest
,
4148 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
4153 add_got_offset (int dest
, expressionS
*local
)
4157 global
.X_op
= O_constant
;
4158 global
.X_op_symbol
= NULL
;
4159 global
.X_add_symbol
= NULL
;
4160 global
.X_add_number
= local
->X_add_number
;
4162 relax_start (local
->X_add_symbol
);
4163 macro_build (&global
, ADDRESS_ADDI_INSN
, "t,r,j",
4164 dest
, dest
, BFD_RELOC_LO16
);
4166 macro_build (local
, ADDRESS_ADDI_INSN
, "t,r,j", dest
, dest
, BFD_RELOC_LO16
);
4171 add_got_offset_hilo (int dest
, expressionS
*local
, int tmp
)
4174 int hold_mips_optimize
;
4176 global
.X_op
= O_constant
;
4177 global
.X_op_symbol
= NULL
;
4178 global
.X_add_symbol
= NULL
;
4179 global
.X_add_number
= local
->X_add_number
;
4181 relax_start (local
->X_add_symbol
);
4182 load_register (tmp
, &global
, HAVE_64BIT_ADDRESSES
);
4184 /* Set mips_optimize around the lui instruction to avoid
4185 inserting an unnecessary nop after the lw. */
4186 hold_mips_optimize
= mips_optimize
;
4188 macro_build_lui (&global
, tmp
);
4189 mips_optimize
= hold_mips_optimize
;
4190 macro_build (local
, ADDRESS_ADDI_INSN
, "t,r,j", tmp
, tmp
, BFD_RELOC_LO16
);
4193 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", dest
, dest
, tmp
);
4198 * This routine implements the seemingly endless macro or synthesized
4199 * instructions and addressing modes in the mips assembly language. Many
4200 * of these macros are simple and are similar to each other. These could
4201 * probably be handled by some kind of table or grammar approach instead of
4202 * this verbose method. Others are not simple macros but are more like
4203 * optimizing code generation.
4204 * One interesting optimization is when several store macros appear
4205 * consecutively that would load AT with the upper half of the same address.
4206 * The ensuing load upper instructions are ommited. This implies some kind
4207 * of global optimization. We currently only optimize within a single macro.
4208 * For many of the load and store macros if the address is specified as a
4209 * constant expression in the first 64k of memory (ie ld $2,0x4000c) we
4210 * first load register 'at' with zero and use it as the base register. The
4211 * mips assembler simply uses register $zero. Just one tiny optimization
4215 macro (struct mips_cl_insn
*ip
)
4217 register int treg
, sreg
, dreg
, breg
;
4233 bfd_reloc_code_real_type r
;
4234 int hold_mips_optimize
;
4236 assert (! mips_opts
.mips16
);
4238 treg
= (ip
->insn_opcode
>> 16) & 0x1f;
4239 dreg
= (ip
->insn_opcode
>> 11) & 0x1f;
4240 sreg
= breg
= (ip
->insn_opcode
>> 21) & 0x1f;
4241 mask
= ip
->insn_mo
->mask
;
4243 expr1
.X_op
= O_constant
;
4244 expr1
.X_op_symbol
= NULL
;
4245 expr1
.X_add_symbol
= NULL
;
4246 expr1
.X_add_number
= 1;
4258 mips_emit_delays (TRUE
);
4259 ++mips_opts
.noreorder
;
4260 mips_any_noreorder
= 1;
4262 expr1
.X_add_number
= 8;
4263 macro_build (&expr1
, "bgez", "s,p", sreg
);
4265 macro_build (NULL
, "nop", "", 0);
4267 move_register (dreg
, sreg
);
4268 macro_build (NULL
, dbl
? "dsub" : "sub", "d,v,t", dreg
, 0, sreg
);
4270 --mips_opts
.noreorder
;
4291 if (imm_expr
.X_op
== O_constant
4292 && imm_expr
.X_add_number
>= -0x8000
4293 && imm_expr
.X_add_number
< 0x8000)
4295 macro_build (&imm_expr
, s
, "t,r,j", treg
, sreg
, BFD_RELOC_LO16
);
4299 load_register (AT
, &imm_expr
, dbl
);
4300 macro_build (NULL
, s2
, "d,v,t", treg
, sreg
, AT
);
4319 if (imm_expr
.X_op
== O_constant
4320 && imm_expr
.X_add_number
>= 0
4321 && imm_expr
.X_add_number
< 0x10000)
4323 if (mask
!= M_NOR_I
)
4324 macro_build (&imm_expr
, s
, "t,r,i", treg
, sreg
, BFD_RELOC_LO16
);
4327 macro_build (&imm_expr
, "ori", "t,r,i",
4328 treg
, sreg
, BFD_RELOC_LO16
);
4329 macro_build (NULL
, "nor", "d,v,t", treg
, treg
, 0);
4335 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
4336 macro_build (NULL
, s2
, "d,v,t", treg
, sreg
, AT
);
4353 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
4355 macro_build (&offset_expr
, s
, "s,t,p", sreg
, 0);
4359 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
4360 macro_build (&offset_expr
, s
, "s,t,p", sreg
, AT
);
4368 macro_build (&offset_expr
, likely
? "bgezl" : "bgez", "s,p", sreg
);
4373 macro_build (&offset_expr
, likely
? "blezl" : "blez", "s,p", treg
);
4377 macro_build (NULL
, "slt", "d,v,t", AT
, sreg
, treg
);
4378 macro_build (&offset_expr
, likely
? "beql" : "beq", "s,t,p", AT
, 0);
4384 /* check for > max integer */
4385 maxnum
= 0x7fffffff;
4386 if (HAVE_64BIT_GPRS
&& sizeof (maxnum
) > 4)
4393 if (imm_expr
.X_op
== O_constant
4394 && imm_expr
.X_add_number
>= maxnum
4395 && (HAVE_32BIT_GPRS
|| sizeof (maxnum
) > 4))
4398 /* result is always false */
4400 macro_build (NULL
, "nop", "", 0);
4402 macro_build (&offset_expr
, "bnel", "s,t,p", 0, 0);
4405 if (imm_expr
.X_op
!= O_constant
)
4406 as_bad (_("Unsupported large constant"));
4407 ++imm_expr
.X_add_number
;
4411 if (mask
== M_BGEL_I
)
4413 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
4415 macro_build (&offset_expr
, likely
? "bgezl" : "bgez", "s,p", sreg
);
4418 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
4420 macro_build (&offset_expr
, likely
? "bgtzl" : "bgtz", "s,p", sreg
);
4423 maxnum
= 0x7fffffff;
4424 if (HAVE_64BIT_GPRS
&& sizeof (maxnum
) > 4)
4431 maxnum
= - maxnum
- 1;
4432 if (imm_expr
.X_op
== O_constant
4433 && imm_expr
.X_add_number
<= maxnum
4434 && (HAVE_32BIT_GPRS
|| sizeof (maxnum
) > 4))
4437 /* result is always true */
4438 as_warn (_("Branch %s is always true"), ip
->insn_mo
->name
);
4439 macro_build (&offset_expr
, "b", "p");
4444 macro_build (&offset_expr
, likely
? "beql" : "beq", "s,t,p", AT
, 0);
4454 macro_build (&offset_expr
, likely
? "beql" : "beq",
4459 macro_build (NULL
, "sltu", "d,v,t", AT
, sreg
, treg
);
4460 macro_build (&offset_expr
, likely
? "beql" : "beq", "s,t,p", AT
, 0);
4468 && imm_expr
.X_op
== O_constant
4469 && imm_expr
.X_add_number
== (offsetT
) 0xffffffff))
4471 if (imm_expr
.X_op
!= O_constant
)
4472 as_bad (_("Unsupported large constant"));
4473 ++imm_expr
.X_add_number
;
4477 if (mask
== M_BGEUL_I
)
4479 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
4481 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
4483 macro_build (&offset_expr
, likely
? "bnel" : "bne",
4489 macro_build (&offset_expr
, likely
? "beql" : "beq", "s,t,p", AT
, 0);
4497 macro_build (&offset_expr
, likely
? "bgtzl" : "bgtz", "s,p", sreg
);
4502 macro_build (&offset_expr
, likely
? "bltzl" : "bltz", "s,p", treg
);
4506 macro_build (NULL
, "slt", "d,v,t", AT
, treg
, sreg
);
4507 macro_build (&offset_expr
, likely
? "bnel" : "bne", "s,t,p", AT
, 0);
4515 macro_build (&offset_expr
, likely
? "bnel" : "bne",
4522 macro_build (NULL
, "sltu", "d,v,t", AT
, treg
, sreg
);
4523 macro_build (&offset_expr
, likely
? "bnel" : "bne", "s,t,p", AT
, 0);
4531 macro_build (&offset_expr
, likely
? "blezl" : "blez", "s,p", sreg
);
4536 macro_build (&offset_expr
, likely
? "bgezl" : "bgez", "s,p", treg
);
4540 macro_build (NULL
, "slt", "d,v,t", AT
, treg
, sreg
);
4541 macro_build (&offset_expr
, likely
? "beql" : "beq", "s,t,p", AT
, 0);
4547 maxnum
= 0x7fffffff;
4548 if (HAVE_64BIT_GPRS
&& sizeof (maxnum
) > 4)
4555 if (imm_expr
.X_op
== O_constant
4556 && imm_expr
.X_add_number
>= maxnum
4557 && (HAVE_32BIT_GPRS
|| sizeof (maxnum
) > 4))
4559 if (imm_expr
.X_op
!= O_constant
)
4560 as_bad (_("Unsupported large constant"));
4561 ++imm_expr
.X_add_number
;
4565 if (mask
== M_BLTL_I
)
4567 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
4569 macro_build (&offset_expr
, likely
? "bltzl" : "bltz", "s,p", sreg
);
4572 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
4574 macro_build (&offset_expr
, likely
? "blezl" : "blez", "s,p", sreg
);
4579 macro_build (&offset_expr
, likely
? "bnel" : "bne", "s,t,p", AT
, 0);
4587 macro_build (&offset_expr
, likely
? "beql" : "beq",
4594 macro_build (NULL
, "sltu", "d,v,t", AT
, treg
, sreg
);
4595 macro_build (&offset_expr
, likely
? "beql" : "beq", "s,t,p", AT
, 0);
4603 && imm_expr
.X_op
== O_constant
4604 && imm_expr
.X_add_number
== (offsetT
) 0xffffffff))
4606 if (imm_expr
.X_op
!= O_constant
)
4607 as_bad (_("Unsupported large constant"));
4608 ++imm_expr
.X_add_number
;
4612 if (mask
== M_BLTUL_I
)
4614 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
4616 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
4618 macro_build (&offset_expr
, likely
? "beql" : "beq",
4624 macro_build (&offset_expr
, likely
? "bnel" : "bne", "s,t,p", AT
, 0);
4632 macro_build (&offset_expr
, likely
? "bltzl" : "bltz", "s,p", sreg
);
4637 macro_build (&offset_expr
, likely
? "bgtzl" : "bgtz", "s,p", treg
);
4641 macro_build (NULL
, "slt", "d,v,t", AT
, sreg
, treg
);
4642 macro_build (&offset_expr
, likely
? "bnel" : "bne", "s,t,p", AT
, 0);
4652 macro_build (&offset_expr
, likely
? "bnel" : "bne",
4657 macro_build (NULL
, "sltu", "d,v,t", AT
, sreg
, treg
);
4658 macro_build (&offset_expr
, likely
? "bnel" : "bne", "s,t,p", AT
, 0);
4666 if (imm_expr
.X_op
!= O_constant
|| imm2_expr
.X_op
!= O_constant
)
4668 as_bad (_("Unsupported large constant"));
4673 pos
= (unsigned long) imm_expr
.X_add_number
;
4674 size
= (unsigned long) imm2_expr
.X_add_number
;
4679 as_bad (_("Improper position (%lu)"), pos
);
4682 if (size
== 0 || size
> 64
4683 || (pos
+ size
- 1) > 63)
4685 as_bad (_("Improper extract size (%lu, position %lu)"),
4690 if (size
<= 32 && pos
< 32)
4695 else if (size
<= 32)
4705 macro_build ((expressionS
*) NULL
, s
, fmt
, treg
, sreg
, pos
, size
- 1);
4714 if (imm_expr
.X_op
!= O_constant
|| imm2_expr
.X_op
!= O_constant
)
4716 as_bad (_("Unsupported large constant"));
4721 pos
= (unsigned long) imm_expr
.X_add_number
;
4722 size
= (unsigned long) imm2_expr
.X_add_number
;
4727 as_bad (_("Improper position (%lu)"), pos
);
4730 if (size
== 0 || size
> 64
4731 || (pos
+ size
- 1) > 63)
4733 as_bad (_("Improper insert size (%lu, position %lu)"),
4738 if (pos
< 32 && (pos
+ size
- 1) < 32)
4753 macro_build ((expressionS
*) NULL
, s
, fmt
, treg
, sreg
, pos
,
4770 as_warn (_("Divide by zero."));
4772 macro_build (NULL
, "teq", "s,t,q", 0, 0, 7);
4774 macro_build (NULL
, "break", "c", 7);
4778 mips_emit_delays (TRUE
);
4779 ++mips_opts
.noreorder
;
4780 mips_any_noreorder
= 1;
4783 macro_build (NULL
, "teq", "s,t,q", treg
, 0, 7);
4784 macro_build (NULL
, dbl
? "ddiv" : "div", "z,s,t", sreg
, treg
);
4788 expr1
.X_add_number
= 8;
4789 macro_build (&expr1
, "bne", "s,t,p", treg
, 0);
4790 macro_build (NULL
, dbl
? "ddiv" : "div", "z,s,t", sreg
, treg
);
4791 macro_build (NULL
, "break", "c", 7);
4793 expr1
.X_add_number
= -1;
4795 load_register (AT
, &expr1
, dbl
);
4796 expr1
.X_add_number
= mips_trap
? (dbl
? 12 : 8) : (dbl
? 20 : 16);
4797 macro_build (&expr1
, "bne", "s,t,p", treg
, AT
);
4800 expr1
.X_add_number
= 1;
4801 load_register (AT
, &expr1
, dbl
);
4802 macro_build (NULL
, "dsll32", "d,w,<", AT
, AT
, 31);
4806 expr1
.X_add_number
= 0x80000000;
4807 macro_build (&expr1
, "lui", "t,u", AT
, BFD_RELOC_HI16
);
4811 macro_build (NULL
, "teq", "s,t,q", sreg
, AT
, 6);
4812 /* We want to close the noreorder block as soon as possible, so
4813 that later insns are available for delay slot filling. */
4814 --mips_opts
.noreorder
;
4818 expr1
.X_add_number
= 8;
4819 macro_build (&expr1
, "bne", "s,t,p", sreg
, AT
);
4820 macro_build (NULL
, "nop", "", 0);
4822 /* We want to close the noreorder block as soon as possible, so
4823 that later insns are available for delay slot filling. */
4824 --mips_opts
.noreorder
;
4826 macro_build (NULL
, "break", "c", 6);
4828 macro_build (NULL
, s
, "d", dreg
);
4867 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
4869 as_warn (_("Divide by zero."));
4871 macro_build (NULL
, "teq", "s,t,q", 0, 0, 7);
4873 macro_build (NULL
, "break", "c", 7);
4876 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
4878 if (strcmp (s2
, "mflo") == 0)
4879 move_register (dreg
, sreg
);
4881 move_register (dreg
, 0);
4884 if (imm_expr
.X_op
== O_constant
4885 && imm_expr
.X_add_number
== -1
4886 && s
[strlen (s
) - 1] != 'u')
4888 if (strcmp (s2
, "mflo") == 0)
4890 macro_build (NULL
, dbl
? "dneg" : "neg", "d,w", dreg
, sreg
);
4893 move_register (dreg
, 0);
4898 load_register (AT
, &imm_expr
, dbl
);
4899 macro_build (NULL
, s
, "z,s,t", sreg
, AT
);
4900 macro_build (NULL
, s2
, "d", dreg
);
4919 mips_emit_delays (TRUE
);
4920 ++mips_opts
.noreorder
;
4921 mips_any_noreorder
= 1;
4924 macro_build (NULL
, "teq", "s,t,q", treg
, 0, 7);
4925 macro_build (NULL
, s
, "z,s,t", sreg
, treg
);
4926 /* We want to close the noreorder block as soon as possible, so
4927 that later insns are available for delay slot filling. */
4928 --mips_opts
.noreorder
;
4932 expr1
.X_add_number
= 8;
4933 macro_build (&expr1
, "bne", "s,t,p", treg
, 0);
4934 macro_build (NULL
, s
, "z,s,t", sreg
, treg
);
4936 /* We want to close the noreorder block as soon as possible, so
4937 that later insns are available for delay slot filling. */
4938 --mips_opts
.noreorder
;
4939 macro_build (NULL
, "break", "c", 7);
4941 macro_build (NULL
, s2
, "d", dreg
);
4953 /* Load the address of a symbol into a register. If breg is not
4954 zero, we then add a base register to it. */
4956 if (dbl
&& HAVE_32BIT_GPRS
)
4957 as_warn (_("dla used to load 32-bit register"));
4959 if (! dbl
&& HAVE_64BIT_OBJECTS
)
4960 as_warn (_("la used to load 64-bit address"));
4962 if (offset_expr
.X_op
== O_constant
4963 && offset_expr
.X_add_number
>= -0x8000
4964 && offset_expr
.X_add_number
< 0x8000)
4966 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
,
4967 "t,r,j", treg
, sreg
, BFD_RELOC_LO16
);
4971 if (!mips_opts
.noat
&& (treg
== breg
))
4981 if (offset_expr
.X_op
!= O_symbol
4982 && offset_expr
.X_op
!= O_constant
)
4984 as_bad (_("expression too complex"));
4985 offset_expr
.X_op
= O_constant
;
4988 if (offset_expr
.X_op
== O_constant
)
4989 load_register (tempreg
, &offset_expr
, HAVE_64BIT_ADDRESSES
);
4990 else if (mips_pic
== NO_PIC
)
4992 /* If this is a reference to a GP relative symbol, we want
4993 addiu $tempreg,$gp,<sym> (BFD_RELOC_GPREL16)
4995 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
4996 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
4997 If we have a constant, we need two instructions anyhow,
4998 so we may as well always use the latter form.
5000 With 64bit address space and a usable $at we want
5001 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5002 lui $at,<sym> (BFD_RELOC_HI16_S)
5003 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
5004 daddiu $at,<sym> (BFD_RELOC_LO16)
5006 daddu $tempreg,$tempreg,$at
5008 If $at is already in use, we use a path which is suboptimal
5009 on superscalar processors.
5010 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5011 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
5013 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
5015 daddiu $tempreg,<sym> (BFD_RELOC_LO16)
5017 For GP relative symbols in 64bit address space we can use
5018 the same sequence as in 32bit address space. */
5019 if (HAVE_64BIT_SYMBOLS
)
5021 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
5022 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
5024 relax_start (offset_expr
.X_add_symbol
);
5025 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
5026 tempreg
, mips_gp_register
, BFD_RELOC_GPREL16
);
5030 if (used_at
== 0 && !mips_opts
.noat
)
5032 macro_build (&offset_expr
, "lui", "t,u",
5033 tempreg
, BFD_RELOC_MIPS_HIGHEST
);
5034 macro_build (&offset_expr
, "lui", "t,u",
5035 AT
, BFD_RELOC_HI16_S
);
5036 macro_build (&offset_expr
, "daddiu", "t,r,j",
5037 tempreg
, tempreg
, BFD_RELOC_MIPS_HIGHER
);
5038 macro_build (&offset_expr
, "daddiu", "t,r,j",
5039 AT
, AT
, BFD_RELOC_LO16
);
5040 macro_build (NULL
, "dsll32", "d,w,<", tempreg
, tempreg
, 0);
5041 macro_build (NULL
, "daddu", "d,v,t", tempreg
, tempreg
, AT
);
5046 macro_build (&offset_expr
, "lui", "t,u",
5047 tempreg
, BFD_RELOC_MIPS_HIGHEST
);
5048 macro_build (&offset_expr
, "daddiu", "t,r,j",
5049 tempreg
, tempreg
, BFD_RELOC_MIPS_HIGHER
);
5050 macro_build (NULL
, "dsll", "d,w,<", tempreg
, tempreg
, 16);
5051 macro_build (&offset_expr
, "daddiu", "t,r,j",
5052 tempreg
, tempreg
, BFD_RELOC_HI16_S
);
5053 macro_build (NULL
, "dsll", "d,w,<", tempreg
, tempreg
, 16);
5054 macro_build (&offset_expr
, "daddiu", "t,r,j",
5055 tempreg
, tempreg
, BFD_RELOC_LO16
);
5058 if (mips_relax
.sequence
)
5063 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
5064 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
5066 relax_start (offset_expr
.X_add_symbol
);
5067 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
5068 tempreg
, mips_gp_register
, BFD_RELOC_GPREL16
);
5071 if (!IS_SEXT_32BIT_NUM (offset_expr
.X_add_number
))
5072 as_bad (_("offset too large"));
5073 macro_build_lui (&offset_expr
, tempreg
);
5074 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
5075 tempreg
, tempreg
, BFD_RELOC_LO16
);
5076 if (mips_relax
.sequence
)
5080 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
&& ! HAVE_NEWABI
)
5082 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT16
;
5084 /* If this is a reference to an external symbol, and there
5085 is no constant, we want
5086 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5087 or for lca or if tempreg is PIC_CALL_REG
5088 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
5089 For a local symbol, we want
5090 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5092 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
5094 If we have a small constant, and this is a reference to
5095 an external symbol, we want
5096 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5098 addiu $tempreg,$tempreg,<constant>
5099 For a local symbol, we want the same instruction
5100 sequence, but we output a BFD_RELOC_LO16 reloc on the
5103 If we have a large constant, and this is a reference to
5104 an external symbol, we want
5105 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5106 lui $at,<hiconstant>
5107 addiu $at,$at,<loconstant>
5108 addu $tempreg,$tempreg,$at
5109 For a local symbol, we want the same instruction
5110 sequence, but we output a BFD_RELOC_LO16 reloc on the
5114 if (offset_expr
.X_add_number
== 0)
5116 if (breg
== 0 && (call
|| tempreg
== PIC_CALL_REG
))
5117 lw_reloc_type
= (int) BFD_RELOC_MIPS_CALL16
;
5119 relax_start (offset_expr
.X_add_symbol
);
5120 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
5121 lw_reloc_type
, mips_gp_register
);
5124 /* We're going to put in an addu instruction using
5125 tempreg, so we may as well insert the nop right
5130 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
5131 tempreg
, BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
5133 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
5134 tempreg
, tempreg
, BFD_RELOC_LO16
);
5136 /* FIXME: If breg == 0, and the next instruction uses
5137 $tempreg, then if this variant case is used an extra
5138 nop will be generated. */
5140 else if (offset_expr
.X_add_number
>= -0x8000
5141 && offset_expr
.X_add_number
< 0x8000)
5143 load_got_offset (tempreg
, &offset_expr
);
5145 add_got_offset (tempreg
, &offset_expr
);
5149 expr1
.X_add_number
= offset_expr
.X_add_number
;
5150 offset_expr
.X_add_number
=
5151 ((offset_expr
.X_add_number
+ 0x8000) & 0xffff) - 0x8000;
5152 load_got_offset (tempreg
, &offset_expr
);
5153 offset_expr
.X_add_number
= expr1
.X_add_number
;
5154 /* If we are going to add in a base register, and the
5155 target register and the base register are the same,
5156 then we are using AT as a temporary register. Since
5157 we want to load the constant into AT, we add our
5158 current AT (from the global offset table) and the
5159 register into the register now, and pretend we were
5160 not using a base register. */
5164 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5169 add_got_offset_hilo (tempreg
, &offset_expr
, AT
);
5173 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
&& HAVE_NEWABI
)
5175 int add_breg_early
= 0;
5177 /* If this is a reference to an external, and there is no
5178 constant, or local symbol (*), with or without a
5180 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
5181 or for lca or if tempreg is PIC_CALL_REG
5182 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
5184 If we have a small constant, and this is a reference to
5185 an external symbol, we want
5186 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
5187 addiu $tempreg,$tempreg,<constant>
5189 If we have a large constant, and this is a reference to
5190 an external symbol, we want
5191 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
5192 lui $at,<hiconstant>
5193 addiu $at,$at,<loconstant>
5194 addu $tempreg,$tempreg,$at
5196 (*) Other assemblers seem to prefer GOT_PAGE/GOT_OFST for
5197 local symbols, even though it introduces an additional
5200 if (offset_expr
.X_add_number
)
5202 expr1
.X_add_number
= offset_expr
.X_add_number
;
5203 offset_expr
.X_add_number
= 0;
5205 relax_start (offset_expr
.X_add_symbol
);
5206 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
5207 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
5209 if (expr1
.X_add_number
>= -0x8000
5210 && expr1
.X_add_number
< 0x8000)
5212 macro_build (&expr1
, ADDRESS_ADDI_INSN
, "t,r,j",
5213 tempreg
, tempreg
, BFD_RELOC_LO16
);
5215 else if (IS_SEXT_32BIT_NUM (expr1
.X_add_number
+ 0x8000))
5219 /* If we are going to add in a base register, and the
5220 target register and the base register are the same,
5221 then we are using AT as a temporary register. Since
5222 we want to load the constant into AT, we add our
5223 current AT (from the global offset table) and the
5224 register into the register now, and pretend we were
5225 not using a base register. */
5230 assert (tempreg
== AT
);
5231 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5237 load_register (AT
, &expr1
, HAVE_64BIT_ADDRESSES
);
5238 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5244 as_bad (_("PIC code offset overflow (max 32 signed bits)"));
5247 offset_expr
.X_add_number
= expr1
.X_add_number
;
5249 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
5250 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
5253 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5254 treg
, tempreg
, breg
);
5260 else if (breg
== 0 && (call
|| tempreg
== PIC_CALL_REG
))
5262 relax_start (offset_expr
.X_add_symbol
);
5263 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
5264 BFD_RELOC_MIPS_CALL16
, mips_gp_register
);
5266 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
5267 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
5272 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
5273 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
5276 else if (mips_pic
== SVR4_PIC
&& ! HAVE_NEWABI
)
5279 int lui_reloc_type
= (int) BFD_RELOC_MIPS_GOT_HI16
;
5280 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT_LO16
;
5281 int local_reloc_type
= (int) BFD_RELOC_MIPS_GOT16
;
5283 /* This is the large GOT case. If this is a reference to an
5284 external symbol, and there is no constant, we want
5285 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5286 addu $tempreg,$tempreg,$gp
5287 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5288 or for lca or if tempreg is PIC_CALL_REG
5289 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
5290 addu $tempreg,$tempreg,$gp
5291 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
5292 For a local symbol, we want
5293 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5295 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
5297 If we have a small constant, and this is a reference to
5298 an external symbol, we want
5299 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5300 addu $tempreg,$tempreg,$gp
5301 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5303 addiu $tempreg,$tempreg,<constant>
5304 For a local symbol, we want
5305 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5307 addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16)
5309 If we have a large constant, and this is a reference to
5310 an external symbol, we want
5311 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5312 addu $tempreg,$tempreg,$gp
5313 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5314 lui $at,<hiconstant>
5315 addiu $at,$at,<loconstant>
5316 addu $tempreg,$tempreg,$at
5317 For a local symbol, we want
5318 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5319 lui $at,<hiconstant>
5320 addiu $at,$at,<loconstant> (BFD_RELOC_LO16)
5321 addu $tempreg,$tempreg,$at
5324 expr1
.X_add_number
= offset_expr
.X_add_number
;
5325 offset_expr
.X_add_number
= 0;
5326 relax_start (offset_expr
.X_add_symbol
);
5327 gpdelay
= reg_needs_delay (mips_gp_register
);
5328 if (expr1
.X_add_number
== 0 && breg
== 0
5329 && (call
|| tempreg
== PIC_CALL_REG
))
5331 lui_reloc_type
= (int) BFD_RELOC_MIPS_CALL_HI16
;
5332 lw_reloc_type
= (int) BFD_RELOC_MIPS_CALL_LO16
;
5334 macro_build (&offset_expr
, "lui", "t,u", tempreg
, lui_reloc_type
);
5335 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5336 tempreg
, tempreg
, mips_gp_register
);
5337 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
5338 tempreg
, lw_reloc_type
, tempreg
);
5339 if (expr1
.X_add_number
== 0)
5343 /* We're going to put in an addu instruction using
5344 tempreg, so we may as well insert the nop right
5349 else if (expr1
.X_add_number
>= -0x8000
5350 && expr1
.X_add_number
< 0x8000)
5353 macro_build (&expr1
, ADDRESS_ADDI_INSN
, "t,r,j",
5354 tempreg
, tempreg
, BFD_RELOC_LO16
);
5360 /* If we are going to add in a base register, and the
5361 target register and the base register are the same,
5362 then we are using AT as a temporary register. Since
5363 we want to load the constant into AT, we add our
5364 current AT (from the global offset table) and the
5365 register into the register now, and pretend we were
5366 not using a base register. */
5371 assert (tempreg
== AT
);
5373 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5378 load_register (AT
, &expr1
, HAVE_64BIT_ADDRESSES
);
5379 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", dreg
, dreg
, AT
);
5383 offset_expr
.X_add_number
=
5384 ((expr1
.X_add_number
+ 0x8000) & 0xffff) - 0x8000;
5389 /* This is needed because this instruction uses $gp, but
5390 the first instruction on the main stream does not. */
5391 macro_build (NULL
, "nop", "");
5394 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
5395 local_reloc_type
, mips_gp_register
);
5396 if (expr1
.X_add_number
>= -0x8000
5397 && expr1
.X_add_number
< 0x8000)
5400 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
5401 tempreg
, tempreg
, BFD_RELOC_LO16
);
5402 /* FIXME: If add_number is 0, and there was no base
5403 register, the external symbol case ended with a load,
5404 so if the symbol turns out to not be external, and
5405 the next instruction uses tempreg, an unnecessary nop
5406 will be inserted. */
5412 /* We must add in the base register now, as in the
5413 external symbol case. */
5414 assert (tempreg
== AT
);
5416 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5419 /* We set breg to 0 because we have arranged to add
5420 it in in both cases. */
5424 macro_build_lui (&expr1
, AT
);
5425 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
5426 AT
, AT
, BFD_RELOC_LO16
);
5427 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5428 tempreg
, tempreg
, AT
);
5433 else if (mips_pic
== SVR4_PIC
&& HAVE_NEWABI
)
5435 int lui_reloc_type
= (int) BFD_RELOC_MIPS_GOT_HI16
;
5436 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT_LO16
;
5437 int add_breg_early
= 0;
5439 /* This is the large GOT case. If this is a reference to an
5440 external symbol, and there is no constant, we want
5441 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5442 add $tempreg,$tempreg,$gp
5443 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5444 or for lca or if tempreg is PIC_CALL_REG
5445 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
5446 add $tempreg,$tempreg,$gp
5447 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
5449 If we have a small constant, and this is a reference to
5450 an external symbol, we want
5451 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5452 add $tempreg,$tempreg,$gp
5453 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5454 addi $tempreg,$tempreg,<constant>
5456 If we have a large constant, and this is a reference to
5457 an external symbol, we want
5458 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5459 addu $tempreg,$tempreg,$gp
5460 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5461 lui $at,<hiconstant>
5462 addi $at,$at,<loconstant>
5463 add $tempreg,$tempreg,$at
5465 If we have NewABI, and we know it's a local symbol, we want
5466 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
5467 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
5468 otherwise we have to resort to GOT_HI16/GOT_LO16. */
5470 relax_start (offset_expr
.X_add_symbol
);
5472 expr1
.X_add_number
= offset_expr
.X_add_number
;
5473 offset_expr
.X_add_number
= 0;
5475 if (expr1
.X_add_number
== 0 && breg
== 0
5476 && (call
|| tempreg
== PIC_CALL_REG
))
5478 lui_reloc_type
= (int) BFD_RELOC_MIPS_CALL_HI16
;
5479 lw_reloc_type
= (int) BFD_RELOC_MIPS_CALL_LO16
;
5481 macro_build (&offset_expr
, "lui", "t,u", tempreg
, lui_reloc_type
);
5482 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5483 tempreg
, tempreg
, mips_gp_register
);
5484 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
5485 tempreg
, lw_reloc_type
, tempreg
);
5487 if (expr1
.X_add_number
== 0)
5489 else if (expr1
.X_add_number
>= -0x8000
5490 && expr1
.X_add_number
< 0x8000)
5492 macro_build (&expr1
, ADDRESS_ADDI_INSN
, "t,r,j",
5493 tempreg
, tempreg
, BFD_RELOC_LO16
);
5495 else if (IS_SEXT_32BIT_NUM (expr1
.X_add_number
+ 0x8000))
5499 /* If we are going to add in a base register, and the
5500 target register and the base register are the same,
5501 then we are using AT as a temporary register. Since
5502 we want to load the constant into AT, we add our
5503 current AT (from the global offset table) and the
5504 register into the register now, and pretend we were
5505 not using a base register. */
5510 assert (tempreg
== AT
);
5511 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5517 load_register (AT
, &expr1
, HAVE_64BIT_ADDRESSES
);
5518 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", dreg
, dreg
, AT
);
5523 as_bad (_("PIC code offset overflow (max 32 signed bits)"));
5526 offset_expr
.X_add_number
= expr1
.X_add_number
;
5527 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
5528 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
5529 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j", tempreg
,
5530 tempreg
, BFD_RELOC_MIPS_GOT_OFST
);
5533 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5534 treg
, tempreg
, breg
);
5544 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", treg
, tempreg
, breg
);
5548 /* The j instruction may not be used in PIC code, since it
5549 requires an absolute address. We convert it to a b
5551 if (mips_pic
== NO_PIC
)
5552 macro_build (&offset_expr
, "j", "a");
5554 macro_build (&offset_expr
, "b", "p");
5557 /* The jal instructions must be handled as macros because when
5558 generating PIC code they expand to multi-instruction
5559 sequences. Normally they are simple instructions. */
5564 if (mips_pic
== NO_PIC
)
5565 macro_build (NULL
, "jalr", "d,s", dreg
, sreg
);
5566 else if (mips_pic
== SVR4_PIC
)
5568 if (sreg
!= PIC_CALL_REG
)
5569 as_warn (_("MIPS PIC call to register other than $25"));
5571 macro_build (NULL
, "jalr", "d,s", dreg
, sreg
);
5574 if (mips_cprestore_offset
< 0)
5575 as_warn (_("No .cprestore pseudo-op used in PIC code"));
5578 if (! mips_frame_reg_valid
)
5580 as_warn (_("No .frame pseudo-op used in PIC code"));
5581 /* Quiet this warning. */
5582 mips_frame_reg_valid
= 1;
5584 if (! mips_cprestore_valid
)
5586 as_warn (_("No .cprestore pseudo-op used in PIC code"));
5587 /* Quiet this warning. */
5588 mips_cprestore_valid
= 1;
5590 expr1
.X_add_number
= mips_cprestore_offset
;
5591 macro_build_ldst_constoffset (&expr1
, ADDRESS_LOAD_INSN
,
5594 HAVE_64BIT_ADDRESSES
);
5604 if (mips_pic
== NO_PIC
)
5605 macro_build (&offset_expr
, "jal", "a");
5606 else if (mips_pic
== SVR4_PIC
)
5608 /* If this is a reference to an external symbol, and we are
5609 using a small GOT, we want
5610 lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
5614 lw $gp,cprestore($sp)
5615 The cprestore value is set using the .cprestore
5616 pseudo-op. If we are using a big GOT, we want
5617 lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16)
5619 lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16)
5623 lw $gp,cprestore($sp)
5624 If the symbol is not external, we want
5625 lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5627 addiu $25,$25,<sym> (BFD_RELOC_LO16)
5630 lw $gp,cprestore($sp)
5632 For NewABI, we use the same CALL16 or CALL_HI16/CALL_LO16
5633 sequences above, minus nops, unless the symbol is local,
5634 which enables us to use GOT_PAGE/GOT_OFST (big got) or
5640 relax_start (offset_expr
.X_add_symbol
);
5641 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
5642 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL16
,
5645 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
5646 PIC_CALL_REG
, BFD_RELOC_MIPS_GOT_DISP
,
5652 relax_start (offset_expr
.X_add_symbol
);
5653 macro_build (&offset_expr
, "lui", "t,u", PIC_CALL_REG
,
5654 BFD_RELOC_MIPS_CALL_HI16
);
5655 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", PIC_CALL_REG
,
5656 PIC_CALL_REG
, mips_gp_register
);
5657 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
5658 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL_LO16
,
5661 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
5662 PIC_CALL_REG
, BFD_RELOC_MIPS_GOT_PAGE
,
5664 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
5665 PIC_CALL_REG
, PIC_CALL_REG
,
5666 BFD_RELOC_MIPS_GOT_OFST
);
5670 macro_build_jalr (&offset_expr
);
5674 relax_start (offset_expr
.X_add_symbol
);
5677 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
5678 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL16
,
5687 gpdelay
= reg_needs_delay (mips_gp_register
);
5688 macro_build (&offset_expr
, "lui", "t,u", PIC_CALL_REG
,
5689 BFD_RELOC_MIPS_CALL_HI16
);
5690 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", PIC_CALL_REG
,
5691 PIC_CALL_REG
, mips_gp_register
);
5692 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
5693 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL_LO16
,
5698 macro_build (NULL
, "nop", "");
5700 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
5701 PIC_CALL_REG
, BFD_RELOC_MIPS_GOT16
,
5704 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
5705 PIC_CALL_REG
, PIC_CALL_REG
, BFD_RELOC_LO16
);
5707 macro_build_jalr (&offset_expr
);
5709 if (mips_cprestore_offset
< 0)
5710 as_warn (_("No .cprestore pseudo-op used in PIC code"));
5713 if (! mips_frame_reg_valid
)
5715 as_warn (_("No .frame pseudo-op used in PIC code"));
5716 /* Quiet this warning. */
5717 mips_frame_reg_valid
= 1;
5719 if (! mips_cprestore_valid
)
5721 as_warn (_("No .cprestore pseudo-op used in PIC code"));
5722 /* Quiet this warning. */
5723 mips_cprestore_valid
= 1;
5725 if (mips_opts
.noreorder
)
5726 macro_build (NULL
, "nop", "");
5727 expr1
.X_add_number
= mips_cprestore_offset
;
5728 macro_build_ldst_constoffset (&expr1
, ADDRESS_LOAD_INSN
,
5731 HAVE_64BIT_ADDRESSES
);
5757 /* Itbl support may require additional care here. */
5762 /* Itbl support may require additional care here. */
5767 /* Itbl support may require additional care here. */
5772 /* Itbl support may require additional care here. */
5784 if (mips_opts
.arch
== CPU_R4650
)
5786 as_bad (_("opcode not supported on this processor"));
5790 /* Itbl support may require additional care here. */
5795 /* Itbl support may require additional care here. */
5800 /* Itbl support may require additional care here. */
5820 if (breg
== treg
|| coproc
|| lr
)
5841 /* Itbl support may require additional care here. */
5846 /* Itbl support may require additional care here. */
5851 /* Itbl support may require additional care here. */
5856 /* Itbl support may require additional care here. */
5872 if (mips_opts
.arch
== CPU_R4650
)
5874 as_bad (_("opcode not supported on this processor"));
5879 /* Itbl support may require additional care here. */
5883 /* Itbl support may require additional care here. */
5888 /* Itbl support may require additional care here. */
5900 /* Itbl support may require additional care here. */
5901 if (mask
== M_LWC1_AB
5902 || mask
== M_SWC1_AB
5903 || mask
== M_LDC1_AB
5904 || mask
== M_SDC1_AB
5913 if (offset_expr
.X_op
!= O_constant
5914 && offset_expr
.X_op
!= O_symbol
)
5916 as_bad (_("expression too complex"));
5917 offset_expr
.X_op
= O_constant
;
5920 /* A constant expression in PIC code can be handled just as it
5921 is in non PIC code. */
5922 if (offset_expr
.X_op
== O_constant
)
5924 if (HAVE_32BIT_ADDRESSES
5925 && !IS_SEXT_32BIT_NUM (offset_expr
.X_add_number
))
5926 as_bad (_("constant too large"));
5928 expr1
.X_add_number
= ((offset_expr
.X_add_number
+ 0x8000)
5929 & ~(bfd_vma
) 0xffff);
5930 load_register (tempreg
, &expr1
, HAVE_64BIT_ADDRESSES
);
5932 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5933 tempreg
, tempreg
, breg
);
5934 macro_build (&offset_expr
, s
, fmt
, treg
, BFD_RELOC_LO16
, tempreg
);
5936 else if (mips_pic
== NO_PIC
)
5938 /* If this is a reference to a GP relative symbol, and there
5939 is no base register, we want
5940 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
5941 Otherwise, if there is no base register, we want
5942 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
5943 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5944 If we have a constant, we need two instructions anyhow,
5945 so we always use the latter form.
5947 If we have a base register, and this is a reference to a
5948 GP relative symbol, we want
5949 addu $tempreg,$breg,$gp
5950 <op> $treg,<sym>($tempreg) (BFD_RELOC_GPREL16)
5952 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
5953 addu $tempreg,$tempreg,$breg
5954 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5955 With a constant we always use the latter case.
5957 With 64bit address space and no base register and $at usable,
5959 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5960 lui $at,<sym> (BFD_RELOC_HI16_S)
5961 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
5964 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5965 If we have a base register, we want
5966 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5967 lui $at,<sym> (BFD_RELOC_HI16_S)
5968 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
5972 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5974 Without $at we can't generate the optimal path for superscalar
5975 processors here since this would require two temporary registers.
5976 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5977 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
5979 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
5981 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5982 If we have a base register, we want
5983 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5984 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
5986 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
5988 daddu $tempreg,$tempreg,$breg
5989 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5991 For GP relative symbols in 64bit address space we can use
5992 the same sequence as in 32bit address space. */
5993 if (HAVE_64BIT_SYMBOLS
)
5995 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
5996 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
5998 relax_start (offset_expr
.X_add_symbol
);
6001 macro_build (&offset_expr
, s
, fmt
, treg
,
6002 BFD_RELOC_GPREL16
, mips_gp_register
);
6006 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6007 tempreg
, breg
, mips_gp_register
);
6008 macro_build (&offset_expr
, s
, fmt
, treg
,
6009 BFD_RELOC_GPREL16
, tempreg
);
6014 if (used_at
== 0 && !mips_opts
.noat
)
6016 macro_build (&offset_expr
, "lui", "t,u", tempreg
,
6017 BFD_RELOC_MIPS_HIGHEST
);
6018 macro_build (&offset_expr
, "lui", "t,u", AT
,
6020 macro_build (&offset_expr
, "daddiu", "t,r,j", tempreg
,
6021 tempreg
, BFD_RELOC_MIPS_HIGHER
);
6023 macro_build (NULL
, "daddu", "d,v,t", AT
, AT
, breg
);
6024 macro_build (NULL
, "dsll32", "d,w,<", tempreg
, tempreg
, 0);
6025 macro_build (NULL
, "daddu", "d,v,t", tempreg
, tempreg
, AT
);
6026 macro_build (&offset_expr
, s
, fmt
, treg
, BFD_RELOC_LO16
,
6032 macro_build (&offset_expr
, "lui", "t,u", tempreg
,
6033 BFD_RELOC_MIPS_HIGHEST
);
6034 macro_build (&offset_expr
, "daddiu", "t,r,j", tempreg
,
6035 tempreg
, BFD_RELOC_MIPS_HIGHER
);
6036 macro_build (NULL
, "dsll", "d,w,<", tempreg
, tempreg
, 16);
6037 macro_build (&offset_expr
, "daddiu", "t,r,j", tempreg
,
6038 tempreg
, BFD_RELOC_HI16_S
);
6039 macro_build (NULL
, "dsll", "d,w,<", tempreg
, tempreg
, 16);
6041 macro_build (NULL
, "daddu", "d,v,t",
6042 tempreg
, tempreg
, breg
);
6043 macro_build (&offset_expr
, s
, fmt
, treg
,
6044 BFD_RELOC_LO16
, tempreg
);
6047 if (mips_relax
.sequence
)
6054 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
6055 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
6057 relax_start (offset_expr
.X_add_symbol
);
6058 macro_build (&offset_expr
, s
, fmt
, treg
, BFD_RELOC_GPREL16
,
6062 macro_build_lui (&offset_expr
, tempreg
);
6063 macro_build (&offset_expr
, s
, fmt
, treg
,
6064 BFD_RELOC_LO16
, tempreg
);
6065 if (mips_relax
.sequence
)
6070 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
6071 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
6073 relax_start (offset_expr
.X_add_symbol
);
6074 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6075 tempreg
, breg
, mips_gp_register
);
6076 macro_build (&offset_expr
, s
, fmt
, treg
,
6077 BFD_RELOC_GPREL16
, tempreg
);
6080 macro_build_lui (&offset_expr
, tempreg
);
6081 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6082 tempreg
, tempreg
, breg
);
6083 macro_build (&offset_expr
, s
, fmt
, treg
,
6084 BFD_RELOC_LO16
, tempreg
);
6085 if (mips_relax
.sequence
)
6089 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
6091 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT16
;
6093 /* If this is a reference to an external symbol, we want
6094 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6096 <op> $treg,0($tempreg)
6098 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6100 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
6101 <op> $treg,0($tempreg)
6104 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
6105 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST)
6107 If there is a base register, we add it to $tempreg before
6108 the <op>. If there is a constant, we stick it in the
6109 <op> instruction. We don't handle constants larger than
6110 16 bits, because we have no way to load the upper 16 bits
6111 (actually, we could handle them for the subset of cases
6112 in which we are not using $at). */
6113 assert (offset_expr
.X_op
== O_symbol
);
6116 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
6117 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
6119 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6120 tempreg
, tempreg
, breg
);
6121 macro_build (&offset_expr
, s
, fmt
, treg
,
6122 BFD_RELOC_MIPS_GOT_OFST
, tempreg
);
6125 expr1
.X_add_number
= offset_expr
.X_add_number
;
6126 offset_expr
.X_add_number
= 0;
6127 if (expr1
.X_add_number
< -0x8000
6128 || expr1
.X_add_number
>= 0x8000)
6129 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6130 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
6131 lw_reloc_type
, mips_gp_register
);
6133 relax_start (offset_expr
.X_add_symbol
);
6135 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j", tempreg
,
6136 tempreg
, BFD_RELOC_LO16
);
6139 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6140 tempreg
, tempreg
, breg
);
6141 macro_build (&expr1
, s
, fmt
, treg
, BFD_RELOC_LO16
, tempreg
);
6143 else if (mips_pic
== SVR4_PIC
&& ! HAVE_NEWABI
)
6147 /* If this is a reference to an external symbol, we want
6148 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
6149 addu $tempreg,$tempreg,$gp
6150 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
6151 <op> $treg,0($tempreg)
6153 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6155 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
6156 <op> $treg,0($tempreg)
6157 If there is a base register, we add it to $tempreg before
6158 the <op>. If there is a constant, we stick it in the
6159 <op> instruction. We don't handle constants larger than
6160 16 bits, because we have no way to load the upper 16 bits
6161 (actually, we could handle them for the subset of cases
6162 in which we are not using $at). */
6163 assert (offset_expr
.X_op
== O_symbol
);
6164 expr1
.X_add_number
= offset_expr
.X_add_number
;
6165 offset_expr
.X_add_number
= 0;
6166 if (expr1
.X_add_number
< -0x8000
6167 || expr1
.X_add_number
>= 0x8000)
6168 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6169 gpdelay
= reg_needs_delay (mips_gp_register
);
6170 relax_start (offset_expr
.X_add_symbol
);
6171 macro_build (&offset_expr
, "lui", "t,u", tempreg
,
6172 BFD_RELOC_MIPS_GOT_HI16
);
6173 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", tempreg
, tempreg
,
6175 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
6176 BFD_RELOC_MIPS_GOT_LO16
, tempreg
);
6179 macro_build (NULL
, "nop", "");
6180 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
6181 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
6183 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j", tempreg
,
6184 tempreg
, BFD_RELOC_LO16
);
6188 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6189 tempreg
, tempreg
, breg
);
6190 macro_build (&expr1
, s
, fmt
, treg
, BFD_RELOC_LO16
, tempreg
);
6192 else if (mips_pic
== SVR4_PIC
&& HAVE_NEWABI
)
6194 /* If this is a reference to an external symbol, we want
6195 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
6196 add $tempreg,$tempreg,$gp
6197 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
6198 <op> $treg,<ofst>($tempreg)
6199 Otherwise, for local symbols, we want:
6200 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
6201 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST) */
6202 assert (offset_expr
.X_op
== O_symbol
);
6203 expr1
.X_add_number
= offset_expr
.X_add_number
;
6204 offset_expr
.X_add_number
= 0;
6205 if (expr1
.X_add_number
< -0x8000
6206 || expr1
.X_add_number
>= 0x8000)
6207 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6208 relax_start (offset_expr
.X_add_symbol
);
6209 macro_build (&offset_expr
, "lui", "t,u", tempreg
,
6210 BFD_RELOC_MIPS_GOT_HI16
);
6211 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", tempreg
, tempreg
,
6213 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
6214 BFD_RELOC_MIPS_GOT_LO16
, tempreg
);
6216 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6217 tempreg
, tempreg
, breg
);
6218 macro_build (&expr1
, s
, fmt
, treg
, BFD_RELOC_LO16
, tempreg
);
6221 offset_expr
.X_add_number
= expr1
.X_add_number
;
6222 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
6223 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
6225 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6226 tempreg
, tempreg
, breg
);
6227 macro_build (&offset_expr
, s
, fmt
, treg
,
6228 BFD_RELOC_MIPS_GOT_OFST
, tempreg
);
6238 load_register (treg
, &imm_expr
, 0);
6242 load_register (treg
, &imm_expr
, 1);
6246 if (imm_expr
.X_op
== O_constant
)
6249 load_register (AT
, &imm_expr
, 0);
6250 macro_build (NULL
, "mtc1", "t,G", AT
, treg
);
6255 assert (offset_expr
.X_op
== O_symbol
6256 && strcmp (segment_name (S_GET_SEGMENT
6257 (offset_expr
.X_add_symbol
)),
6259 && offset_expr
.X_add_number
== 0);
6260 macro_build (&offset_expr
, "lwc1", "T,o(b)", treg
,
6261 BFD_RELOC_MIPS_LITERAL
, mips_gp_register
);
6266 /* Check if we have a constant in IMM_EXPR. If the GPRs are 64 bits
6267 wide, IMM_EXPR is the entire value. Otherwise IMM_EXPR is the high
6268 order 32 bits of the value and the low order 32 bits are either
6269 zero or in OFFSET_EXPR. */
6270 if (imm_expr
.X_op
== O_constant
|| imm_expr
.X_op
== O_big
)
6272 if (HAVE_64BIT_GPRS
)
6273 load_register (treg
, &imm_expr
, 1);
6278 if (target_big_endian
)
6290 load_register (hreg
, &imm_expr
, 0);
6293 if (offset_expr
.X_op
== O_absent
)
6294 move_register (lreg
, 0);
6297 assert (offset_expr
.X_op
== O_constant
);
6298 load_register (lreg
, &offset_expr
, 0);
6305 /* We know that sym is in the .rdata section. First we get the
6306 upper 16 bits of the address. */
6307 if (mips_pic
== NO_PIC
)
6309 macro_build_lui (&offset_expr
, AT
);
6312 else if (mips_pic
== SVR4_PIC
)
6314 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", AT
,
6315 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
6321 /* Now we load the register(s). */
6322 if (HAVE_64BIT_GPRS
)
6325 macro_build (&offset_expr
, "ld", "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
6330 macro_build (&offset_expr
, "lw", "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
6333 /* FIXME: How in the world do we deal with the possible
6335 offset_expr
.X_add_number
+= 4;
6336 macro_build (&offset_expr
, "lw", "t,o(b)",
6337 treg
+ 1, BFD_RELOC_LO16
, AT
);
6343 /* Check if we have a constant in IMM_EXPR. If the FPRs are 64 bits
6344 wide, IMM_EXPR is the entire value and the GPRs are known to be 64
6345 bits wide as well. Otherwise IMM_EXPR is the high order 32 bits of
6346 the value and the low order 32 bits are either zero or in
6348 if (imm_expr
.X_op
== O_constant
|| imm_expr
.X_op
== O_big
)
6351 load_register (AT
, &imm_expr
, HAVE_64BIT_FPRS
);
6352 if (HAVE_64BIT_FPRS
)
6354 assert (HAVE_64BIT_GPRS
);
6355 macro_build (NULL
, "dmtc1", "t,S", AT
, treg
);
6359 macro_build (NULL
, "mtc1", "t,G", AT
, treg
+ 1);
6360 if (offset_expr
.X_op
== O_absent
)
6361 macro_build (NULL
, "mtc1", "t,G", 0, treg
);
6364 assert (offset_expr
.X_op
== O_constant
);
6365 load_register (AT
, &offset_expr
, 0);
6366 macro_build (NULL
, "mtc1", "t,G", AT
, treg
);
6372 assert (offset_expr
.X_op
== O_symbol
6373 && offset_expr
.X_add_number
== 0);
6374 s
= segment_name (S_GET_SEGMENT (offset_expr
.X_add_symbol
));
6375 if (strcmp (s
, ".lit8") == 0)
6377 if (mips_opts
.isa
!= ISA_MIPS1
)
6379 macro_build (&offset_expr
, "ldc1", "T,o(b)", treg
,
6380 BFD_RELOC_MIPS_LITERAL
, mips_gp_register
);
6383 breg
= mips_gp_register
;
6384 r
= BFD_RELOC_MIPS_LITERAL
;
6389 assert (strcmp (s
, RDATA_SECTION_NAME
) == 0);
6391 if (mips_pic
== SVR4_PIC
)
6392 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", AT
,
6393 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
6396 /* FIXME: This won't work for a 64 bit address. */
6397 macro_build_lui (&offset_expr
, AT
);
6400 if (mips_opts
.isa
!= ISA_MIPS1
)
6402 macro_build (&offset_expr
, "ldc1", "T,o(b)",
6403 treg
, BFD_RELOC_LO16
, AT
);
6412 if (mips_opts
.arch
== CPU_R4650
)
6414 as_bad (_("opcode not supported on this processor"));
6417 /* Even on a big endian machine $fn comes before $fn+1. We have
6418 to adjust when loading from memory. */
6421 assert (mips_opts
.isa
== ISA_MIPS1
);
6422 macro_build (&offset_expr
, "lwc1", "T,o(b)",
6423 target_big_endian
? treg
+ 1 : treg
, r
, breg
);
6424 /* FIXME: A possible overflow which I don't know how to deal
6426 offset_expr
.X_add_number
+= 4;
6427 macro_build (&offset_expr
, "lwc1", "T,o(b)",
6428 target_big_endian
? treg
: treg
+ 1, r
, breg
);
6433 * The MIPS assembler seems to check for X_add_number not
6434 * being double aligned and generating:
6437 * addiu at,at,%lo(foo+1)
6440 * But, the resulting address is the same after relocation so why
6441 * generate the extra instruction?
6443 if (mips_opts
.arch
== CPU_R4650
)
6445 as_bad (_("opcode not supported on this processor"));
6448 /* Itbl support may require additional care here. */
6450 if (mips_opts
.isa
!= ISA_MIPS1
)
6461 if (mips_opts
.arch
== CPU_R4650
)
6463 as_bad (_("opcode not supported on this processor"));
6467 if (mips_opts
.isa
!= ISA_MIPS1
)
6475 /* Itbl support may require additional care here. */
6480 if (HAVE_64BIT_GPRS
)
6491 if (HAVE_64BIT_GPRS
)
6501 if (offset_expr
.X_op
!= O_symbol
6502 && offset_expr
.X_op
!= O_constant
)
6504 as_bad (_("expression too complex"));
6505 offset_expr
.X_op
= O_constant
;
6508 /* Even on a big endian machine $fn comes before $fn+1. We have
6509 to adjust when loading from memory. We set coproc if we must
6510 load $fn+1 first. */
6511 /* Itbl support may require additional care here. */
6512 if (! target_big_endian
)
6515 if (mips_pic
== NO_PIC
6516 || offset_expr
.X_op
== O_constant
)
6518 /* If this is a reference to a GP relative symbol, we want
6519 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
6520 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_GPREL16)
6521 If we have a base register, we use this
6523 <op> $treg,<sym>($at) (BFD_RELOC_GPREL16)
6524 <op> $treg+1,<sym>+4($at) (BFD_RELOC_GPREL16)
6525 If this is not a GP relative symbol, we want
6526 lui $at,<sym> (BFD_RELOC_HI16_S)
6527 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
6528 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
6529 If there is a base register, we add it to $at after the
6530 lui instruction. If there is a constant, we always use
6532 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
6533 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
6535 relax_start (offset_expr
.X_add_symbol
);
6538 tempreg
= mips_gp_register
;
6542 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6543 AT
, breg
, mips_gp_register
);
6548 /* Itbl support may require additional care here. */
6549 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
+ 1 : treg
,
6550 BFD_RELOC_GPREL16
, tempreg
);
6551 offset_expr
.X_add_number
+= 4;
6553 /* Set mips_optimize to 2 to avoid inserting an
6555 hold_mips_optimize
= mips_optimize
;
6557 /* Itbl support may require additional care here. */
6558 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
: treg
+ 1,
6559 BFD_RELOC_GPREL16
, tempreg
);
6560 mips_optimize
= hold_mips_optimize
;
6564 /* We just generated two relocs. When tc_gen_reloc
6565 handles this case, it will skip the first reloc and
6566 handle the second. The second reloc already has an
6567 extra addend of 4, which we added above. We must
6568 subtract it out, and then subtract another 4 to make
6569 the first reloc come out right. The second reloc
6570 will come out right because we are going to add 4 to
6571 offset_expr when we build its instruction below.
6573 If we have a symbol, then we don't want to include
6574 the offset, because it will wind up being included
6575 when we generate the reloc. */
6577 if (offset_expr
.X_op
== O_constant
)
6578 offset_expr
.X_add_number
-= 8;
6581 offset_expr
.X_add_number
= -4;
6582 offset_expr
.X_op
= O_constant
;
6586 macro_build_lui (&offset_expr
, AT
);
6588 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
6589 /* Itbl support may require additional care here. */
6590 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
+ 1 : treg
,
6591 BFD_RELOC_LO16
, AT
);
6592 /* FIXME: How do we handle overflow here? */
6593 offset_expr
.X_add_number
+= 4;
6594 /* Itbl support may require additional care here. */
6595 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
: treg
+ 1,
6596 BFD_RELOC_LO16
, AT
);
6597 if (mips_relax
.sequence
)
6600 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
6602 /* If this is a reference to an external symbol, we want
6603 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6608 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6610 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
6611 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
6612 If there is a base register we add it to $at before the
6613 lwc1 instructions. If there is a constant we include it
6614 in the lwc1 instructions. */
6616 expr1
.X_add_number
= offset_expr
.X_add_number
;
6617 if (expr1
.X_add_number
< -0x8000
6618 || expr1
.X_add_number
>= 0x8000 - 4)
6619 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6620 load_got_offset (AT
, &offset_expr
);
6623 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
6625 /* Set mips_optimize to 2 to avoid inserting an undesired
6627 hold_mips_optimize
= mips_optimize
;
6630 /* Itbl support may require additional care here. */
6631 relax_start (offset_expr
.X_add_symbol
);
6632 macro_build (&expr1
, s
, fmt
, coproc
? treg
+ 1 : treg
,
6633 BFD_RELOC_LO16
, AT
);
6634 expr1
.X_add_number
+= 4;
6635 macro_build (&expr1
, s
, fmt
, coproc
? treg
: treg
+ 1,
6636 BFD_RELOC_LO16
, AT
);
6638 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
+ 1 : treg
,
6639 BFD_RELOC_LO16
, AT
);
6640 offset_expr
.X_add_number
+= 4;
6641 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
: treg
+ 1,
6642 BFD_RELOC_LO16
, AT
);
6645 mips_optimize
= hold_mips_optimize
;
6647 else if (mips_pic
== SVR4_PIC
)
6651 /* If this is a reference to an external symbol, we want
6652 lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16)
6654 lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16)
6659 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6661 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
6662 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
6663 If there is a base register we add it to $at before the
6664 lwc1 instructions. If there is a constant we include it
6665 in the lwc1 instructions. */
6667 expr1
.X_add_number
= offset_expr
.X_add_number
;
6668 offset_expr
.X_add_number
= 0;
6669 if (expr1
.X_add_number
< -0x8000
6670 || expr1
.X_add_number
>= 0x8000 - 4)
6671 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6672 gpdelay
= reg_needs_delay (mips_gp_register
);
6673 relax_start (offset_expr
.X_add_symbol
);
6674 macro_build (&offset_expr
, "lui", "t,u",
6675 AT
, BFD_RELOC_MIPS_GOT_HI16
);
6676 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6677 AT
, AT
, mips_gp_register
);
6678 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
6679 AT
, BFD_RELOC_MIPS_GOT_LO16
, AT
);
6682 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
6683 /* Itbl support may require additional care here. */
6684 macro_build (&expr1
, s
, fmt
, coproc
? treg
+ 1 : treg
,
6685 BFD_RELOC_LO16
, AT
);
6686 expr1
.X_add_number
+= 4;
6688 /* Set mips_optimize to 2 to avoid inserting an undesired
6690 hold_mips_optimize
= mips_optimize
;
6692 /* Itbl support may require additional care here. */
6693 macro_build (&expr1
, s
, fmt
, coproc
? treg
: treg
+ 1,
6694 BFD_RELOC_LO16
, AT
);
6695 mips_optimize
= hold_mips_optimize
;
6696 expr1
.X_add_number
-= 4;
6699 offset_expr
.X_add_number
= expr1
.X_add_number
;
6701 macro_build (NULL
, "nop", "");
6702 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", AT
,
6703 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
6706 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
6707 /* Itbl support may require additional care here. */
6708 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
+ 1 : treg
,
6709 BFD_RELOC_LO16
, AT
);
6710 offset_expr
.X_add_number
+= 4;
6712 /* Set mips_optimize to 2 to avoid inserting an undesired
6714 hold_mips_optimize
= mips_optimize
;
6716 /* Itbl support may require additional care here. */
6717 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
: treg
+ 1,
6718 BFD_RELOC_LO16
, AT
);
6719 mips_optimize
= hold_mips_optimize
;
6733 assert (HAVE_32BIT_ADDRESSES
);
6734 macro_build (&offset_expr
, s
, "t,o(b)", treg
, BFD_RELOC_LO16
, breg
);
6735 offset_expr
.X_add_number
+= 4;
6736 macro_build (&offset_expr
, s
, "t,o(b)", treg
+ 1, BFD_RELOC_LO16
, breg
);
6739 /* New code added to support COPZ instructions.
6740 This code builds table entries out of the macros in mip_opcodes.
6741 R4000 uses interlocks to handle coproc delays.
6742 Other chips (like the R3000) require nops to be inserted for delays.
6744 FIXME: Currently, we require that the user handle delays.
6745 In order to fill delay slots for non-interlocked chips,
6746 we must have a way to specify delays based on the coprocessor.
6747 Eg. 4 cycles if load coproc reg from memory, 1 if in cache, etc.
6748 What are the side-effects of the cop instruction?
6749 What cache support might we have and what are its effects?
6750 Both coprocessor & memory require delays. how long???
6751 What registers are read/set/modified?
6753 If an itbl is provided to interpret cop instructions,
6754 this knowledge can be encoded in the itbl spec. */
6768 /* For now we just do C (same as Cz). The parameter will be
6769 stored in insn_opcode by mips_ip. */
6770 macro_build (NULL
, s
, "C", ip
->insn_opcode
);
6774 move_register (dreg
, sreg
);
6777 #ifdef LOSING_COMPILER
6779 /* Try and see if this is a new itbl instruction.
6780 This code builds table entries out of the macros in mip_opcodes.
6781 FIXME: For now we just assemble the expression and pass it's
6782 value along as a 32-bit immediate.
6783 We may want to have the assembler assemble this value,
6784 so that we gain the assembler's knowledge of delay slots,
6786 Would it be more efficient to use mask (id) here? */
6787 if (itbl_have_entries
6788 && (immed_expr
= itbl_assemble (ip
->insn_mo
->name
, "")))
6790 s
= ip
->insn_mo
->name
;
6792 coproc
= ITBL_DECODE_PNUM (immed_expr
);;
6793 macro_build (&immed_expr
, s
, "C");
6799 if (mips_opts
.noat
&& used_at
)
6800 as_bad (_("Macro used $at after \".set noat\""));
6804 macro2 (struct mips_cl_insn
*ip
)
6806 register int treg
, sreg
, dreg
, breg
;
6821 bfd_reloc_code_real_type r
;
6823 treg
= (ip
->insn_opcode
>> 16) & 0x1f;
6824 dreg
= (ip
->insn_opcode
>> 11) & 0x1f;
6825 sreg
= breg
= (ip
->insn_opcode
>> 21) & 0x1f;
6826 mask
= ip
->insn_mo
->mask
;
6828 expr1
.X_op
= O_constant
;
6829 expr1
.X_op_symbol
= NULL
;
6830 expr1
.X_add_symbol
= NULL
;
6831 expr1
.X_add_number
= 1;
6835 #endif /* LOSING_COMPILER */
6840 macro_build (NULL
, dbl
? "dmultu" : "multu", "s,t", sreg
, treg
);
6841 macro_build (NULL
, "mflo", "d", dreg
);
6847 /* The MIPS assembler some times generates shifts and adds. I'm
6848 not trying to be that fancy. GCC should do this for us
6851 load_register (AT
, &imm_expr
, dbl
);
6852 macro_build (NULL
, dbl
? "dmult" : "mult", "s,t", sreg
, AT
);
6853 macro_build (NULL
, "mflo", "d", dreg
);
6866 mips_emit_delays (TRUE
);
6867 ++mips_opts
.noreorder
;
6868 mips_any_noreorder
= 1;
6871 load_register (AT
, &imm_expr
, dbl
);
6872 macro_build (NULL
, dbl
? "dmult" : "mult", "s,t", sreg
, imm
? AT
: treg
);
6873 macro_build (NULL
, "mflo", "d", dreg
);
6874 macro_build (NULL
, dbl
? "dsra32" : "sra", "d,w,<", dreg
, dreg
, RA
);
6875 macro_build (NULL
, "mfhi", "d", AT
);
6877 macro_build (NULL
, "tne", "s,t,q", dreg
, AT
, 6);
6880 expr1
.X_add_number
= 8;
6881 macro_build (&expr1
, "beq", "s,t,p", dreg
, AT
);
6882 macro_build (NULL
, "nop", "", 0);
6883 macro_build (NULL
, "break", "c", 6);
6885 --mips_opts
.noreorder
;
6886 macro_build (NULL
, "mflo", "d", dreg
);
6899 mips_emit_delays (TRUE
);
6900 ++mips_opts
.noreorder
;
6901 mips_any_noreorder
= 1;
6904 load_register (AT
, &imm_expr
, dbl
);
6905 macro_build (NULL
, dbl
? "dmultu" : "multu", "s,t",
6906 sreg
, imm
? AT
: treg
);
6907 macro_build (NULL
, "mfhi", "d", AT
);
6908 macro_build (NULL
, "mflo", "d", dreg
);
6910 macro_build (NULL
, "tne", "s,t,q", AT
, 0, 6);
6913 expr1
.X_add_number
= 8;
6914 macro_build (&expr1
, "beq", "s,t,p", AT
, 0);
6915 macro_build (NULL
, "nop", "", 0);
6916 macro_build (NULL
, "break", "c", 6);
6918 --mips_opts
.noreorder
;
6922 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
6933 macro_build (NULL
, "dnegu", "d,w", tempreg
, treg
);
6934 macro_build (NULL
, "drorv", "d,t,s", dreg
, sreg
, tempreg
);
6938 macro_build (NULL
, "dsubu", "d,v,t", AT
, 0, treg
);
6939 macro_build (NULL
, "dsrlv", "d,t,s", AT
, sreg
, AT
);
6940 macro_build (NULL
, "dsllv", "d,t,s", dreg
, sreg
, treg
);
6941 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
6945 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
6956 macro_build (NULL
, "negu", "d,w", tempreg
, treg
);
6957 macro_build (NULL
, "rorv", "d,t,s", dreg
, sreg
, tempreg
);
6961 macro_build (NULL
, "subu", "d,v,t", AT
, 0, treg
);
6962 macro_build (NULL
, "srlv", "d,t,s", AT
, sreg
, AT
);
6963 macro_build (NULL
, "sllv", "d,t,s", dreg
, sreg
, treg
);
6964 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
6972 if (imm_expr
.X_op
!= O_constant
)
6973 as_bad (_("Improper rotate count"));
6974 rot
= imm_expr
.X_add_number
& 0x3f;
6975 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
6977 rot
= (64 - rot
) & 0x3f;
6979 macro_build (NULL
, "dror32", "d,w,<", dreg
, sreg
, rot
- 32);
6981 macro_build (NULL
, "dror", "d,w,<", dreg
, sreg
, rot
);
6986 macro_build (NULL
, "dsrl", "d,w,<", dreg
, sreg
, 0);
6989 l
= (rot
< 0x20) ? "dsll" : "dsll32";
6990 r
= ((0x40 - rot
) < 0x20) ? "dsrl" : "dsrl32";
6993 macro_build (NULL
, l
, "d,w,<", AT
, sreg
, rot
);
6994 macro_build (NULL
, r
, "d,w,<", dreg
, sreg
, (0x20 - rot
) & 0x1f);
6995 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
7003 if (imm_expr
.X_op
!= O_constant
)
7004 as_bad (_("Improper rotate count"));
7005 rot
= imm_expr
.X_add_number
& 0x1f;
7006 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
7008 macro_build (NULL
, "ror", "d,w,<", dreg
, sreg
, (32 - rot
) & 0x1f);
7013 macro_build (NULL
, "srl", "d,w,<", dreg
, sreg
, 0);
7017 macro_build (NULL
, "sll", "d,w,<", AT
, sreg
, rot
);
7018 macro_build (NULL
, "srl", "d,w,<", dreg
, sreg
, (0x20 - rot
) & 0x1f);
7019 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
7024 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
7026 macro_build (NULL
, "drorv", "d,t,s", dreg
, sreg
, treg
);
7030 macro_build (NULL
, "dsubu", "d,v,t", AT
, 0, treg
);
7031 macro_build (NULL
, "dsllv", "d,t,s", AT
, sreg
, AT
);
7032 macro_build (NULL
, "dsrlv", "d,t,s", dreg
, sreg
, treg
);
7033 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
7037 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
7039 macro_build (NULL
, "rorv", "d,t,s", dreg
, sreg
, treg
);
7043 macro_build (NULL
, "subu", "d,v,t", AT
, 0, treg
);
7044 macro_build (NULL
, "sllv", "d,t,s", AT
, sreg
, AT
);
7045 macro_build (NULL
, "srlv", "d,t,s", dreg
, sreg
, treg
);
7046 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
7054 if (imm_expr
.X_op
!= O_constant
)
7055 as_bad (_("Improper rotate count"));
7056 rot
= imm_expr
.X_add_number
& 0x3f;
7057 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
7060 macro_build (NULL
, "dror32", "d,w,<", dreg
, sreg
, rot
- 32);
7062 macro_build (NULL
, "dror", "d,w,<", dreg
, sreg
, rot
);
7067 macro_build (NULL
, "dsrl", "d,w,<", dreg
, sreg
, 0);
7070 r
= (rot
< 0x20) ? "dsrl" : "dsrl32";
7071 l
= ((0x40 - rot
) < 0x20) ? "dsll" : "dsll32";
7074 macro_build (NULL
, r
, "d,w,<", AT
, sreg
, rot
);
7075 macro_build (NULL
, l
, "d,w,<", dreg
, sreg
, (0x20 - rot
) & 0x1f);
7076 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
7084 if (imm_expr
.X_op
!= O_constant
)
7085 as_bad (_("Improper rotate count"));
7086 rot
= imm_expr
.X_add_number
& 0x1f;
7087 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
7089 macro_build (NULL
, "ror", "d,w,<", dreg
, sreg
, rot
);
7094 macro_build (NULL
, "srl", "d,w,<", dreg
, sreg
, 0);
7098 macro_build (NULL
, "srl", "d,w,<", AT
, sreg
, rot
);
7099 macro_build (NULL
, "sll", "d,w,<", dreg
, sreg
, (0x20 - rot
) & 0x1f);
7100 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
7105 if (mips_opts
.arch
== CPU_R4650
)
7107 as_bad (_("opcode not supported on this processor"));
7110 assert (mips_opts
.isa
== ISA_MIPS1
);
7111 /* Even on a big endian machine $fn comes before $fn+1. We have
7112 to adjust when storing to memory. */
7113 macro_build (&offset_expr
, "swc1", "T,o(b)",
7114 target_big_endian
? treg
+ 1 : treg
, BFD_RELOC_LO16
, breg
);
7115 offset_expr
.X_add_number
+= 4;
7116 macro_build (&offset_expr
, "swc1", "T,o(b)",
7117 target_big_endian
? treg
: treg
+ 1, BFD_RELOC_LO16
, breg
);
7122 macro_build (&expr1
, "sltiu", "t,r,j", dreg
, treg
, BFD_RELOC_LO16
);
7124 macro_build (&expr1
, "sltiu", "t,r,j", dreg
, sreg
, BFD_RELOC_LO16
);
7127 macro_build (NULL
, "xor", "d,v,t", dreg
, sreg
, treg
);
7128 macro_build (&expr1
, "sltiu", "t,r,j", dreg
, dreg
, BFD_RELOC_LO16
);
7133 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
7135 macro_build (&expr1
, "sltiu", "t,r,j", dreg
, sreg
, BFD_RELOC_LO16
);
7140 as_warn (_("Instruction %s: result is always false"),
7142 move_register (dreg
, 0);
7145 if (imm_expr
.X_op
== O_constant
7146 && imm_expr
.X_add_number
>= 0
7147 && imm_expr
.X_add_number
< 0x10000)
7149 macro_build (&imm_expr
, "xori", "t,r,i", dreg
, sreg
, BFD_RELOC_LO16
);
7151 else if (imm_expr
.X_op
== O_constant
7152 && imm_expr
.X_add_number
> -0x8000
7153 && imm_expr
.X_add_number
< 0)
7155 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
7156 macro_build (&imm_expr
, HAVE_32BIT_GPRS
? "addiu" : "daddiu",
7157 "t,r,j", dreg
, sreg
, BFD_RELOC_LO16
);
7161 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7162 macro_build (NULL
, "xor", "d,v,t", dreg
, sreg
, AT
);
7165 macro_build (&expr1
, "sltiu", "t,r,j", dreg
, dreg
, BFD_RELOC_LO16
);
7168 case M_SGE
: /* sreg >= treg <==> not (sreg < treg) */
7174 macro_build (NULL
, s
, "d,v,t", dreg
, sreg
, treg
);
7175 macro_build (&expr1
, "xori", "t,r,i", dreg
, dreg
, BFD_RELOC_LO16
);
7178 case M_SGE_I
: /* sreg >= I <==> not (sreg < I) */
7180 if (imm_expr
.X_op
== O_constant
7181 && imm_expr
.X_add_number
>= -0x8000
7182 && imm_expr
.X_add_number
< 0x8000)
7184 macro_build (&imm_expr
, mask
== M_SGE_I
? "slti" : "sltiu", "t,r,j",
7185 dreg
, sreg
, BFD_RELOC_LO16
);
7189 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7190 macro_build (NULL
, mask
== M_SGE_I
? "slt" : "sltu", "d,v,t",
7194 macro_build (&expr1
, "xori", "t,r,i", dreg
, dreg
, BFD_RELOC_LO16
);
7197 case M_SGT
: /* sreg > treg <==> treg < sreg */
7203 macro_build (NULL
, s
, "d,v,t", dreg
, treg
, sreg
);
7206 case M_SGT_I
: /* sreg > I <==> I < sreg */
7213 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7214 macro_build (NULL
, s
, "d,v,t", dreg
, AT
, sreg
);
7217 case M_SLE
: /* sreg <= treg <==> treg >= sreg <==> not (treg < sreg) */
7223 macro_build (NULL
, s
, "d,v,t", dreg
, treg
, sreg
);
7224 macro_build (&expr1
, "xori", "t,r,i", dreg
, dreg
, BFD_RELOC_LO16
);
7227 case M_SLE_I
: /* sreg <= I <==> I >= sreg <==> not (I < sreg) */
7234 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7235 macro_build (NULL
, s
, "d,v,t", dreg
, AT
, sreg
);
7236 macro_build (&expr1
, "xori", "t,r,i", dreg
, dreg
, BFD_RELOC_LO16
);
7240 if (imm_expr
.X_op
== O_constant
7241 && imm_expr
.X_add_number
>= -0x8000
7242 && imm_expr
.X_add_number
< 0x8000)
7244 macro_build (&imm_expr
, "slti", "t,r,j", dreg
, sreg
, BFD_RELOC_LO16
);
7248 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7249 macro_build (NULL
, "slt", "d,v,t", dreg
, sreg
, AT
);
7253 if (imm_expr
.X_op
== O_constant
7254 && imm_expr
.X_add_number
>= -0x8000
7255 && imm_expr
.X_add_number
< 0x8000)
7257 macro_build (&imm_expr
, "sltiu", "t,r,j", dreg
, sreg
,
7262 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7263 macro_build (NULL
, "sltu", "d,v,t", dreg
, sreg
, AT
);
7268 macro_build (NULL
, "sltu", "d,v,t", dreg
, 0, treg
);
7270 macro_build (NULL
, "sltu", "d,v,t", dreg
, 0, sreg
);
7273 macro_build (NULL
, "xor", "d,v,t", dreg
, sreg
, treg
);
7274 macro_build (NULL
, "sltu", "d,v,t", dreg
, 0, dreg
);
7279 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
7281 macro_build (NULL
, "sltu", "d,v,t", dreg
, 0, sreg
);
7286 as_warn (_("Instruction %s: result is always true"),
7288 macro_build (&expr1
, HAVE_32BIT_GPRS
? "addiu" : "daddiu", "t,r,j",
7289 dreg
, 0, BFD_RELOC_LO16
);
7292 if (imm_expr
.X_op
== O_constant
7293 && imm_expr
.X_add_number
>= 0
7294 && imm_expr
.X_add_number
< 0x10000)
7296 macro_build (&imm_expr
, "xori", "t,r,i", dreg
, sreg
, BFD_RELOC_LO16
);
7298 else if (imm_expr
.X_op
== O_constant
7299 && imm_expr
.X_add_number
> -0x8000
7300 && imm_expr
.X_add_number
< 0)
7302 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
7303 macro_build (&imm_expr
, HAVE_32BIT_GPRS
? "addiu" : "daddiu",
7304 "t,r,j", dreg
, sreg
, BFD_RELOC_LO16
);
7308 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7309 macro_build (NULL
, "xor", "d,v,t", dreg
, sreg
, AT
);
7312 macro_build (NULL
, "sltu", "d,v,t", dreg
, 0, dreg
);
7318 if (imm_expr
.X_op
== O_constant
7319 && imm_expr
.X_add_number
> -0x8000
7320 && imm_expr
.X_add_number
<= 0x8000)
7322 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
7323 macro_build (&imm_expr
, dbl
? "daddi" : "addi", "t,r,j",
7324 dreg
, sreg
, BFD_RELOC_LO16
);
7328 load_register (AT
, &imm_expr
, dbl
);
7329 macro_build (NULL
, dbl
? "dsub" : "sub", "d,v,t", dreg
, sreg
, AT
);
7335 if (imm_expr
.X_op
== O_constant
7336 && imm_expr
.X_add_number
> -0x8000
7337 && imm_expr
.X_add_number
<= 0x8000)
7339 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
7340 macro_build (&imm_expr
, dbl
? "daddiu" : "addiu", "t,r,j",
7341 dreg
, sreg
, BFD_RELOC_LO16
);
7345 load_register (AT
, &imm_expr
, dbl
);
7346 macro_build (NULL
, dbl
? "dsubu" : "subu", "d,v,t", dreg
, sreg
, AT
);
7368 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7369 macro_build (NULL
, s
, "s,t", sreg
, AT
);
7374 assert (mips_opts
.isa
== ISA_MIPS1
);
7376 sreg
= (ip
->insn_opcode
>> 11) & 0x1f; /* floating reg */
7377 dreg
= (ip
->insn_opcode
>> 06) & 0x1f; /* floating reg */
7380 * Is the double cfc1 instruction a bug in the mips assembler;
7381 * or is there a reason for it?
7383 mips_emit_delays (TRUE
);
7384 ++mips_opts
.noreorder
;
7385 mips_any_noreorder
= 1;
7386 macro_build (NULL
, "cfc1", "t,G", treg
, RA
);
7387 macro_build (NULL
, "cfc1", "t,G", treg
, RA
);
7388 macro_build (NULL
, "nop", "");
7389 expr1
.X_add_number
= 3;
7390 macro_build (&expr1
, "ori", "t,r,i", AT
, treg
, BFD_RELOC_LO16
);
7391 expr1
.X_add_number
= 2;
7392 macro_build (&expr1
, "xori", "t,r,i", AT
, AT
, BFD_RELOC_LO16
);
7393 macro_build (NULL
, "ctc1", "t,G", AT
, RA
);
7394 macro_build (NULL
, "nop", "");
7395 macro_build (NULL
, mask
== M_TRUNCWD
? "cvt.w.d" : "cvt.w.s", "D,S",
7397 macro_build (NULL
, "ctc1", "t,G", treg
, RA
);
7398 macro_build (NULL
, "nop", "");
7399 --mips_opts
.noreorder
;
7409 if (offset_expr
.X_add_number
>= 0x7fff)
7410 as_bad (_("operand overflow"));
7411 if (! target_big_endian
)
7412 ++offset_expr
.X_add_number
;
7413 macro_build (&offset_expr
, s
, "t,o(b)", AT
, BFD_RELOC_LO16
, breg
);
7414 if (! target_big_endian
)
7415 --offset_expr
.X_add_number
;
7417 ++offset_expr
.X_add_number
;
7418 macro_build (&offset_expr
, "lbu", "t,o(b)", treg
, BFD_RELOC_LO16
, breg
);
7419 macro_build (NULL
, "sll", "d,w,<", AT
, AT
, 8);
7420 macro_build (NULL
, "or", "d,v,t", treg
, treg
, AT
);
7433 if (offset_expr
.X_add_number
>= 0x8000 - off
)
7434 as_bad (_("operand overflow"));
7442 if (! target_big_endian
)
7443 offset_expr
.X_add_number
+= off
;
7444 macro_build (&offset_expr
, s
, "t,o(b)", tempreg
, BFD_RELOC_LO16
, breg
);
7445 if (! target_big_endian
)
7446 offset_expr
.X_add_number
-= off
;
7448 offset_expr
.X_add_number
+= off
;
7449 macro_build (&offset_expr
, s2
, "t,o(b)", tempreg
, BFD_RELOC_LO16
, breg
);
7451 /* If necessary, move the result in tempreg the final destination. */
7452 if (treg
== tempreg
)
7454 /* Protect second load's delay slot. */
7456 move_register (treg
, tempreg
);
7470 load_address (AT
, &offset_expr
, &used_at
);
7472 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, AT
, breg
);
7473 if (! target_big_endian
)
7474 expr1
.X_add_number
= off
;
7476 expr1
.X_add_number
= 0;
7477 macro_build (&expr1
, s
, "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
7478 if (! target_big_endian
)
7479 expr1
.X_add_number
= 0;
7481 expr1
.X_add_number
= off
;
7482 macro_build (&expr1
, s2
, "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
7488 load_address (AT
, &offset_expr
, &used_at
);
7490 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, AT
, breg
);
7491 if (target_big_endian
)
7492 expr1
.X_add_number
= 0;
7493 macro_build (&expr1
, mask
== M_ULH_A
? "lb" : "lbu", "t,o(b)",
7494 treg
, BFD_RELOC_LO16
, AT
);
7495 if (target_big_endian
)
7496 expr1
.X_add_number
= 1;
7498 expr1
.X_add_number
= 0;
7499 macro_build (&expr1
, "lbu", "t,o(b)", AT
, BFD_RELOC_LO16
, AT
);
7500 macro_build (NULL
, "sll", "d,w,<", treg
, treg
, 8);
7501 macro_build (NULL
, "or", "d,v,t", treg
, treg
, AT
);
7506 if (offset_expr
.X_add_number
>= 0x7fff)
7507 as_bad (_("operand overflow"));
7508 if (target_big_endian
)
7509 ++offset_expr
.X_add_number
;
7510 macro_build (&offset_expr
, "sb", "t,o(b)", treg
, BFD_RELOC_LO16
, breg
);
7511 macro_build (NULL
, "srl", "d,w,<", AT
, treg
, 8);
7512 if (target_big_endian
)
7513 --offset_expr
.X_add_number
;
7515 ++offset_expr
.X_add_number
;
7516 macro_build (&offset_expr
, "sb", "t,o(b)", AT
, BFD_RELOC_LO16
, breg
);
7529 if (offset_expr
.X_add_number
>= 0x8000 - off
)
7530 as_bad (_("operand overflow"));
7531 if (! target_big_endian
)
7532 offset_expr
.X_add_number
+= off
;
7533 macro_build (&offset_expr
, s
, "t,o(b)", treg
, BFD_RELOC_LO16
, breg
);
7534 if (! target_big_endian
)
7535 offset_expr
.X_add_number
-= off
;
7537 offset_expr
.X_add_number
+= off
;
7538 macro_build (&offset_expr
, s2
, "t,o(b)", treg
, BFD_RELOC_LO16
, breg
);
7552 load_address (AT
, &offset_expr
, &used_at
);
7554 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, AT
, breg
);
7555 if (! target_big_endian
)
7556 expr1
.X_add_number
= off
;
7558 expr1
.X_add_number
= 0;
7559 macro_build (&expr1
, s
, "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
7560 if (! target_big_endian
)
7561 expr1
.X_add_number
= 0;
7563 expr1
.X_add_number
= off
;
7564 macro_build (&expr1
, s2
, "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
7569 load_address (AT
, &offset_expr
, &used_at
);
7571 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, AT
, breg
);
7572 if (! target_big_endian
)
7573 expr1
.X_add_number
= 0;
7574 macro_build (&expr1
, "sb", "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
7575 macro_build (NULL
, "srl", "d,w,<", treg
, treg
, 8);
7576 if (! target_big_endian
)
7577 expr1
.X_add_number
= 1;
7579 expr1
.X_add_number
= 0;
7580 macro_build (&expr1
, "sb", "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
7581 if (! target_big_endian
)
7582 expr1
.X_add_number
= 0;
7584 expr1
.X_add_number
= 1;
7585 macro_build (&expr1
, "lbu", "t,o(b)", AT
, BFD_RELOC_LO16
, AT
);
7586 macro_build (NULL
, "sll", "d,w,<", treg
, treg
, 8);
7587 macro_build (NULL
, "or", "d,v,t", treg
, treg
, AT
);
7591 /* FIXME: Check if this is one of the itbl macros, since they
7592 are added dynamically. */
7593 as_bad (_("Macro %s not implemented yet"), ip
->insn_mo
->name
);
7596 if (mips_opts
.noat
&& used_at
)
7597 as_bad (_("Macro used $at after \".set noat\""));
7600 /* Implement macros in mips16 mode. */
7603 mips16_macro (struct mips_cl_insn
*ip
)
7606 int xreg
, yreg
, zreg
, tmp
;
7609 const char *s
, *s2
, *s3
;
7611 mask
= ip
->insn_mo
->mask
;
7613 xreg
= (ip
->insn_opcode
>> MIPS16OP_SH_RX
) & MIPS16OP_MASK_RX
;
7614 yreg
= (ip
->insn_opcode
>> MIPS16OP_SH_RY
) & MIPS16OP_MASK_RY
;
7615 zreg
= (ip
->insn_opcode
>> MIPS16OP_SH_RZ
) & MIPS16OP_MASK_RZ
;
7617 expr1
.X_op
= O_constant
;
7618 expr1
.X_op_symbol
= NULL
;
7619 expr1
.X_add_symbol
= NULL
;
7620 expr1
.X_add_number
= 1;
7639 mips_emit_delays (TRUE
);
7640 ++mips_opts
.noreorder
;
7641 mips_any_noreorder
= 1;
7642 macro_build (NULL
, dbl
? "ddiv" : "div", "0,x,y", xreg
, yreg
);
7643 expr1
.X_add_number
= 2;
7644 macro_build (&expr1
, "bnez", "x,p", yreg
);
7645 macro_build (NULL
, "break", "6", 7);
7647 /* FIXME: The normal code checks for of -1 / -0x80000000 here,
7648 since that causes an overflow. We should do that as well,
7649 but I don't see how to do the comparisons without a temporary
7651 --mips_opts
.noreorder
;
7652 macro_build (NULL
, s
, "x", zreg
);
7671 mips_emit_delays (TRUE
);
7672 ++mips_opts
.noreorder
;
7673 mips_any_noreorder
= 1;
7674 macro_build (NULL
, s
, "0,x,y", xreg
, yreg
);
7675 expr1
.X_add_number
= 2;
7676 macro_build (&expr1
, "bnez", "x,p", yreg
);
7677 macro_build (NULL
, "break", "6", 7);
7678 --mips_opts
.noreorder
;
7679 macro_build (NULL
, s2
, "x", zreg
);
7685 macro_build (NULL
, dbl
? "dmultu" : "multu", "x,y", xreg
, yreg
);
7686 macro_build (NULL
, "mflo", "x", zreg
);
7694 if (imm_expr
.X_op
!= O_constant
)
7695 as_bad (_("Unsupported large constant"));
7696 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
7697 macro_build (&imm_expr
, dbl
? "daddiu" : "addiu", "y,x,4", yreg
, xreg
);
7701 if (imm_expr
.X_op
!= O_constant
)
7702 as_bad (_("Unsupported large constant"));
7703 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
7704 macro_build (&imm_expr
, "addiu", "x,k", xreg
);
7708 if (imm_expr
.X_op
!= O_constant
)
7709 as_bad (_("Unsupported large constant"));
7710 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
7711 macro_build (&imm_expr
, "daddiu", "y,j", yreg
);
7733 goto do_reverse_branch
;
7737 goto do_reverse_branch
;
7749 goto do_reverse_branch
;
7760 macro_build (NULL
, s
, "x,y", xreg
, yreg
);
7761 macro_build (&offset_expr
, s2
, "p");
7788 goto do_addone_branch_i
;
7793 goto do_addone_branch_i
;
7808 goto do_addone_branch_i
;
7815 if (imm_expr
.X_op
!= O_constant
)
7816 as_bad (_("Unsupported large constant"));
7817 ++imm_expr
.X_add_number
;
7820 macro_build (&imm_expr
, s
, s3
, xreg
);
7821 macro_build (&offset_expr
, s2
, "p");
7825 expr1
.X_add_number
= 0;
7826 macro_build (&expr1
, "slti", "x,8", yreg
);
7828 move_register (xreg
, yreg
);
7829 expr1
.X_add_number
= 2;
7830 macro_build (&expr1
, "bteqz", "p");
7831 macro_build (NULL
, "neg", "x,w", xreg
, xreg
);
7835 /* For consistency checking, verify that all bits are specified either
7836 by the match/mask part of the instruction definition, or by the
7839 validate_mips_insn (const struct mips_opcode
*opc
)
7841 const char *p
= opc
->args
;
7843 unsigned long used_bits
= opc
->mask
;
7845 if ((used_bits
& opc
->match
) != opc
->match
)
7847 as_bad (_("internal: bad mips opcode (mask error): %s %s"),
7848 opc
->name
, opc
->args
);
7851 #define USE_BITS(mask,shift) (used_bits |= ((mask) << (shift)))
7861 case 'A': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
7862 case 'B': USE_BITS (OP_MASK_INSMSB
, OP_SH_INSMSB
); break;
7863 case 'C': USE_BITS (OP_MASK_EXTMSBD
, OP_SH_EXTMSBD
); break;
7864 case 'D': USE_BITS (OP_MASK_RD
, OP_SH_RD
);
7865 USE_BITS (OP_MASK_SEL
, OP_SH_SEL
); break;
7866 case 'E': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
7867 case 'F': USE_BITS (OP_MASK_INSMSB
, OP_SH_INSMSB
); break;
7868 case 'G': USE_BITS (OP_MASK_EXTMSBD
, OP_SH_EXTMSBD
); break;
7869 case 'H': USE_BITS (OP_MASK_EXTMSBD
, OP_SH_EXTMSBD
); break;
7872 as_bad (_("internal: bad mips opcode (unknown extension operand type `+%c'): %s %s"),
7873 c
, opc
->name
, opc
->args
);
7877 case '<': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
7878 case '>': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
7880 case 'B': USE_BITS (OP_MASK_CODE20
, OP_SH_CODE20
); break;
7881 case 'C': USE_BITS (OP_MASK_COPZ
, OP_SH_COPZ
); break;
7882 case 'D': USE_BITS (OP_MASK_FD
, OP_SH_FD
); break;
7883 case 'E': USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
7885 case 'G': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
7886 case 'H': USE_BITS (OP_MASK_SEL
, OP_SH_SEL
); break;
7888 case 'J': USE_BITS (OP_MASK_CODE19
, OP_SH_CODE19
); break;
7889 case 'K': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
7891 case 'M': USE_BITS (OP_MASK_CCC
, OP_SH_CCC
); break;
7892 case 'N': USE_BITS (OP_MASK_BCC
, OP_SH_BCC
); break;
7893 case 'O': USE_BITS (OP_MASK_ALN
, OP_SH_ALN
); break;
7894 case 'Q': USE_BITS (OP_MASK_VSEL
, OP_SH_VSEL
);
7895 USE_BITS (OP_MASK_FT
, OP_SH_FT
); break;
7896 case 'R': USE_BITS (OP_MASK_FR
, OP_SH_FR
); break;
7897 case 'S': USE_BITS (OP_MASK_FS
, OP_SH_FS
); break;
7898 case 'T': USE_BITS (OP_MASK_FT
, OP_SH_FT
); break;
7899 case 'V': USE_BITS (OP_MASK_FS
, OP_SH_FS
); break;
7900 case 'W': USE_BITS (OP_MASK_FT
, OP_SH_FT
); break;
7901 case 'X': USE_BITS (OP_MASK_FD
, OP_SH_FD
); break;
7902 case 'Y': USE_BITS (OP_MASK_FS
, OP_SH_FS
); break;
7903 case 'Z': USE_BITS (OP_MASK_FT
, OP_SH_FT
); break;
7904 case 'a': USE_BITS (OP_MASK_TARGET
, OP_SH_TARGET
); break;
7905 case 'b': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
7906 case 'c': USE_BITS (OP_MASK_CODE
, OP_SH_CODE
); break;
7907 case 'd': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
7909 case 'h': USE_BITS (OP_MASK_PREFX
, OP_SH_PREFX
); break;
7910 case 'i': USE_BITS (OP_MASK_IMMEDIATE
, OP_SH_IMMEDIATE
); break;
7911 case 'j': USE_BITS (OP_MASK_DELTA
, OP_SH_DELTA
); break;
7912 case 'k': USE_BITS (OP_MASK_CACHE
, OP_SH_CACHE
); break;
7914 case 'o': USE_BITS (OP_MASK_DELTA
, OP_SH_DELTA
); break;
7915 case 'p': USE_BITS (OP_MASK_DELTA
, OP_SH_DELTA
); break;
7916 case 'q': USE_BITS (OP_MASK_CODE2
, OP_SH_CODE2
); break;
7917 case 'r': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
7918 case 's': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
7919 case 't': USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
7920 case 'u': USE_BITS (OP_MASK_IMMEDIATE
, OP_SH_IMMEDIATE
); break;
7921 case 'v': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
7922 case 'w': USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
7925 case 'P': USE_BITS (OP_MASK_PERFREG
, OP_SH_PERFREG
); break;
7926 case 'U': USE_BITS (OP_MASK_RD
, OP_SH_RD
);
7927 USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
7928 case 'e': USE_BITS (OP_MASK_VECBYTE
, OP_SH_VECBYTE
); break;
7929 case '%': USE_BITS (OP_MASK_VECALIGN
, OP_SH_VECALIGN
); break;
7933 as_bad (_("internal: bad mips opcode (unknown operand type `%c'): %s %s"),
7934 c
, opc
->name
, opc
->args
);
7938 if (used_bits
!= 0xffffffff)
7940 as_bad (_("internal: bad mips opcode (bits 0x%lx undefined): %s %s"),
7941 ~used_bits
& 0xffffffff, opc
->name
, opc
->args
);
7947 /* This routine assembles an instruction into its binary format. As a
7948 side effect, it sets one of the global variables imm_reloc or
7949 offset_reloc to the type of relocation to do if one of the operands
7950 is an address expression. */
7953 mips_ip (char *str
, struct mips_cl_insn
*ip
)
7958 struct mips_opcode
*insn
;
7961 unsigned int lastregno
= 0;
7962 unsigned int lastpos
= 0;
7963 unsigned int limlo
, limhi
;
7969 /* If the instruction contains a '.', we first try to match an instruction
7970 including the '.'. Then we try again without the '.'. */
7972 for (s
= str
; *s
!= '\0' && !ISSPACE (*s
); ++s
)
7975 /* If we stopped on whitespace, then replace the whitespace with null for
7976 the call to hash_find. Save the character we replaced just in case we
7977 have to re-parse the instruction. */
7984 insn
= (struct mips_opcode
*) hash_find (op_hash
, str
);
7986 /* If we didn't find the instruction in the opcode table, try again, but
7987 this time with just the instruction up to, but not including the
7991 /* Restore the character we overwrite above (if any). */
7995 /* Scan up to the first '.' or whitespace. */
7997 *s
!= '\0' && *s
!= '.' && !ISSPACE (*s
);
8001 /* If we did not find a '.', then we can quit now. */
8004 insn_error
= "unrecognized opcode";
8008 /* Lookup the instruction in the hash table. */
8010 if ((insn
= (struct mips_opcode
*) hash_find (op_hash
, str
)) == NULL
)
8012 insn_error
= "unrecognized opcode";
8022 assert (strcmp (insn
->name
, str
) == 0);
8024 if (OPCODE_IS_MEMBER (insn
,
8026 | (file_ase_mips16
? INSN_MIPS16
: 0)
8027 | (mips_opts
.ase_mdmx
? INSN_MDMX
: 0)
8028 | (mips_opts
.ase_mips3d
? INSN_MIPS3D
: 0)),
8034 if (insn
->pinfo
!= INSN_MACRO
)
8036 if (mips_opts
.arch
== CPU_R4650
&& (insn
->pinfo
& FP_D
) != 0)
8042 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
]
8043 && strcmp (insn
->name
, insn
[1].name
) == 0)
8052 static char buf
[100];
8054 _("opcode not supported on this processor: %s (%s)"),
8055 mips_cpu_info_from_arch (mips_opts
.arch
)->name
,
8056 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
8066 ip
->insn_opcode
= insn
->match
;
8068 for (args
= insn
->args
;; ++args
)
8072 s
+= strspn (s
, " \t");
8076 case '\0': /* end of args */
8089 ip
->insn_opcode
|= lastregno
<< OP_SH_RS
;
8093 ip
->insn_opcode
|= lastregno
<< OP_SH_RT
;
8097 ip
->insn_opcode
|= lastregno
<< OP_SH_FT
;
8101 ip
->insn_opcode
|= lastregno
<< OP_SH_FS
;
8107 /* Handle optional base register.
8108 Either the base register is omitted or
8109 we must have a left paren. */
8110 /* This is dependent on the next operand specifier
8111 is a base register specification. */
8112 assert (args
[1] == 'b' || args
[1] == '5'
8113 || args
[1] == '-' || args
[1] == '4');
8117 case ')': /* these must match exactly */
8124 case '+': /* Opcode extension character. */
8127 case 'A': /* ins/ext position, becomes LSB. */
8136 my_getExpression (&imm_expr
, s
);
8137 check_absolute_expr (ip
, &imm_expr
);
8138 if ((unsigned long) imm_expr
.X_add_number
< limlo
8139 || (unsigned long) imm_expr
.X_add_number
> limhi
)
8141 as_bad (_("Improper position (%lu)"),
8142 (unsigned long) imm_expr
.X_add_number
);
8143 imm_expr
.X_add_number
= limlo
;
8145 lastpos
= imm_expr
.X_add_number
;
8146 ip
->insn_opcode
|= (imm_expr
.X_add_number
8147 & OP_MASK_SHAMT
) << OP_SH_SHAMT
;
8148 imm_expr
.X_op
= O_absent
;
8152 case 'B': /* ins size, becomes MSB. */
8161 my_getExpression (&imm_expr
, s
);
8162 check_absolute_expr (ip
, &imm_expr
);
8163 /* Check for negative input so that small negative numbers
8164 will not succeed incorrectly. The checks against
8165 (pos+size) transitively check "size" itself,
8166 assuming that "pos" is reasonable. */
8167 if ((long) imm_expr
.X_add_number
< 0
8168 || ((unsigned long) imm_expr
.X_add_number
8170 || ((unsigned long) imm_expr
.X_add_number
8173 as_bad (_("Improper insert size (%lu, position %lu)"),
8174 (unsigned long) imm_expr
.X_add_number
,
8175 (unsigned long) lastpos
);
8176 imm_expr
.X_add_number
= limlo
- lastpos
;
8178 ip
->insn_opcode
|= ((lastpos
+ imm_expr
.X_add_number
- 1)
8179 & OP_MASK_INSMSB
) << OP_SH_INSMSB
;
8180 imm_expr
.X_op
= O_absent
;
8184 case 'C': /* ext size, becomes MSBD. */
8197 my_getExpression (&imm_expr
, s
);
8198 check_absolute_expr (ip
, &imm_expr
);
8199 /* Check for negative input so that small negative numbers
8200 will not succeed incorrectly. The checks against
8201 (pos+size) transitively check "size" itself,
8202 assuming that "pos" is reasonable. */
8203 if ((long) imm_expr
.X_add_number
< 0
8204 || ((unsigned long) imm_expr
.X_add_number
8206 || ((unsigned long) imm_expr
.X_add_number
8209 as_bad (_("Improper extract size (%lu, position %lu)"),
8210 (unsigned long) imm_expr
.X_add_number
,
8211 (unsigned long) lastpos
);
8212 imm_expr
.X_add_number
= limlo
- lastpos
;
8214 ip
->insn_opcode
|= ((imm_expr
.X_add_number
- 1)
8215 & OP_MASK_EXTMSBD
) << OP_SH_EXTMSBD
;
8216 imm_expr
.X_op
= O_absent
;
8221 /* +D is for disassembly only; never match. */
8225 /* "+I" is like "I", except that imm2_expr is used. */
8226 my_getExpression (&imm2_expr
, s
);
8227 if (imm2_expr
.X_op
!= O_big
8228 && imm2_expr
.X_op
!= O_constant
)
8229 insn_error
= _("absolute expression required");
8230 normalize_constant_expr (&imm2_expr
);
8235 as_bad (_("internal: bad mips opcode (unknown extension operand type `+%c'): %s %s"),
8236 *args
, insn
->name
, insn
->args
);
8237 /* Further processing is fruitless. */
8242 case '<': /* must be at least one digit */
8244 * According to the manual, if the shift amount is greater
8245 * than 31 or less than 0, then the shift amount should be
8246 * mod 32. In reality the mips assembler issues an error.
8247 * We issue a warning and mask out all but the low 5 bits.
8249 my_getExpression (&imm_expr
, s
);
8250 check_absolute_expr (ip
, &imm_expr
);
8251 if ((unsigned long) imm_expr
.X_add_number
> 31)
8253 as_warn (_("Improper shift amount (%lu)"),
8254 (unsigned long) imm_expr
.X_add_number
);
8255 imm_expr
.X_add_number
&= OP_MASK_SHAMT
;
8257 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_SHAMT
;
8258 imm_expr
.X_op
= O_absent
;
8262 case '>': /* shift amount minus 32 */
8263 my_getExpression (&imm_expr
, s
);
8264 check_absolute_expr (ip
, &imm_expr
);
8265 if ((unsigned long) imm_expr
.X_add_number
< 32
8266 || (unsigned long) imm_expr
.X_add_number
> 63)
8268 ip
->insn_opcode
|= (imm_expr
.X_add_number
- 32) << OP_SH_SHAMT
;
8269 imm_expr
.X_op
= O_absent
;
8273 case 'k': /* cache code */
8274 case 'h': /* prefx code */
8275 my_getExpression (&imm_expr
, s
);
8276 check_absolute_expr (ip
, &imm_expr
);
8277 if ((unsigned long) imm_expr
.X_add_number
> 31)
8279 as_warn (_("Invalid value for `%s' (%lu)"),
8281 (unsigned long) imm_expr
.X_add_number
);
8282 imm_expr
.X_add_number
&= 0x1f;
8285 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_CACHE
;
8287 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_PREFX
;
8288 imm_expr
.X_op
= O_absent
;
8292 case 'c': /* break code */
8293 my_getExpression (&imm_expr
, s
);
8294 check_absolute_expr (ip
, &imm_expr
);
8295 if ((unsigned long) imm_expr
.X_add_number
> 1023)
8297 as_warn (_("Illegal break code (%lu)"),
8298 (unsigned long) imm_expr
.X_add_number
);
8299 imm_expr
.X_add_number
&= OP_MASK_CODE
;
8301 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_CODE
;
8302 imm_expr
.X_op
= O_absent
;
8306 case 'q': /* lower break code */
8307 my_getExpression (&imm_expr
, s
);
8308 check_absolute_expr (ip
, &imm_expr
);
8309 if ((unsigned long) imm_expr
.X_add_number
> 1023)
8311 as_warn (_("Illegal lower break code (%lu)"),
8312 (unsigned long) imm_expr
.X_add_number
);
8313 imm_expr
.X_add_number
&= OP_MASK_CODE2
;
8315 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_CODE2
;
8316 imm_expr
.X_op
= O_absent
;
8320 case 'B': /* 20-bit syscall/break code. */
8321 my_getExpression (&imm_expr
, s
);
8322 check_absolute_expr (ip
, &imm_expr
);
8323 if ((unsigned long) imm_expr
.X_add_number
> OP_MASK_CODE20
)
8324 as_warn (_("Illegal 20-bit code (%lu)"),
8325 (unsigned long) imm_expr
.X_add_number
);
8326 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_CODE20
;
8327 imm_expr
.X_op
= O_absent
;
8331 case 'C': /* Coprocessor code */
8332 my_getExpression (&imm_expr
, s
);
8333 check_absolute_expr (ip
, &imm_expr
);
8334 if ((unsigned long) imm_expr
.X_add_number
>= (1 << 25))
8336 as_warn (_("Coproccesor code > 25 bits (%lu)"),
8337 (unsigned long) imm_expr
.X_add_number
);
8338 imm_expr
.X_add_number
&= ((1 << 25) - 1);
8340 ip
->insn_opcode
|= imm_expr
.X_add_number
;
8341 imm_expr
.X_op
= O_absent
;
8345 case 'J': /* 19-bit wait code. */
8346 my_getExpression (&imm_expr
, s
);
8347 check_absolute_expr (ip
, &imm_expr
);
8348 if ((unsigned long) imm_expr
.X_add_number
> OP_MASK_CODE19
)
8349 as_warn (_("Illegal 19-bit code (%lu)"),
8350 (unsigned long) imm_expr
.X_add_number
);
8351 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_CODE19
;
8352 imm_expr
.X_op
= O_absent
;
8356 case 'P': /* Performance register */
8357 my_getExpression (&imm_expr
, s
);
8358 check_absolute_expr (ip
, &imm_expr
);
8359 if (imm_expr
.X_add_number
!= 0 && imm_expr
.X_add_number
!= 1)
8361 as_warn (_("Invalid performance register (%lu)"),
8362 (unsigned long) imm_expr
.X_add_number
);
8363 imm_expr
.X_add_number
&= OP_MASK_PERFREG
;
8365 ip
->insn_opcode
|= (imm_expr
.X_add_number
<< OP_SH_PERFREG
);
8366 imm_expr
.X_op
= O_absent
;
8370 case 'b': /* base register */
8371 case 'd': /* destination register */
8372 case 's': /* source register */
8373 case 't': /* target register */
8374 case 'r': /* both target and source */
8375 case 'v': /* both dest and source */
8376 case 'w': /* both dest and target */
8377 case 'E': /* coprocessor target register */
8378 case 'G': /* coprocessor destination register */
8379 case 'K': /* 'rdhwr' destination register */
8380 case 'x': /* ignore register name */
8381 case 'z': /* must be zero register */
8382 case 'U': /* destination register (clo/clz). */
8397 while (ISDIGIT (*s
));
8399 as_bad (_("Invalid register number (%d)"), regno
);
8401 else if (*args
== 'E' || *args
== 'G' || *args
== 'K')
8405 if (s
[1] == 'r' && s
[2] == 'a')
8410 else if (s
[1] == 'f' && s
[2] == 'p')
8415 else if (s
[1] == 's' && s
[2] == 'p')
8420 else if (s
[1] == 'g' && s
[2] == 'p')
8425 else if (s
[1] == 'a' && s
[2] == 't')
8430 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '0')
8435 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '1')
8440 else if (s
[1] == 'z' && s
[2] == 'e' && s
[3] == 'r' && s
[4] == 'o')
8445 else if (itbl_have_entries
)
8450 p
= s
+ 1; /* advance past '$' */
8451 n
= itbl_get_field (&p
); /* n is name */
8453 /* See if this is a register defined in an
8455 if (itbl_get_reg_val (n
, &r
))
8457 /* Get_field advances to the start of
8458 the next field, so we need to back
8459 rack to the end of the last field. */
8463 s
= strchr (s
, '\0');
8477 as_warn (_("Used $at without \".set noat\""));
8483 if (c
== 'r' || c
== 'v' || c
== 'w')
8490 /* 'z' only matches $0. */
8491 if (c
== 'z' && regno
!= 0)
8494 /* Now that we have assembled one operand, we use the args string
8495 * to figure out where it goes in the instruction. */
8502 ip
->insn_opcode
|= regno
<< OP_SH_RS
;
8507 ip
->insn_opcode
|= regno
<< OP_SH_RD
;
8510 ip
->insn_opcode
|= regno
<< OP_SH_RD
;
8511 ip
->insn_opcode
|= regno
<< OP_SH_RT
;
8516 ip
->insn_opcode
|= regno
<< OP_SH_RT
;
8519 /* This case exists because on the r3000 trunc
8520 expands into a macro which requires a gp
8521 register. On the r6000 or r4000 it is
8522 assembled into a single instruction which
8523 ignores the register. Thus the insn version
8524 is MIPS_ISA2 and uses 'x', and the macro
8525 version is MIPS_ISA1 and uses 't'. */
8528 /* This case is for the div instruction, which
8529 acts differently if the destination argument
8530 is $0. This only matches $0, and is checked
8531 outside the switch. */
8534 /* Itbl operand; not yet implemented. FIXME ?? */
8536 /* What about all other operands like 'i', which
8537 can be specified in the opcode table? */
8547 ip
->insn_opcode
|= lastregno
<< OP_SH_RS
;
8550 ip
->insn_opcode
|= lastregno
<< OP_SH_RT
;
8555 case 'O': /* MDMX alignment immediate constant. */
8556 my_getExpression (&imm_expr
, s
);
8557 check_absolute_expr (ip
, &imm_expr
);
8558 if ((unsigned long) imm_expr
.X_add_number
> OP_MASK_ALN
)
8560 as_warn ("Improper align amount (%ld), using low bits",
8561 (long) imm_expr
.X_add_number
);
8562 imm_expr
.X_add_number
&= OP_MASK_ALN
;
8564 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_ALN
;
8565 imm_expr
.X_op
= O_absent
;
8569 case 'Q': /* MDMX vector, element sel, or const. */
8572 /* MDMX Immediate. */
8573 my_getExpression (&imm_expr
, s
);
8574 check_absolute_expr (ip
, &imm_expr
);
8575 if ((unsigned long) imm_expr
.X_add_number
> OP_MASK_FT
)
8577 as_warn (_("Invalid MDMX Immediate (%ld)"),
8578 (long) imm_expr
.X_add_number
);
8579 imm_expr
.X_add_number
&= OP_MASK_FT
;
8581 imm_expr
.X_add_number
&= OP_MASK_FT
;
8582 if (ip
->insn_opcode
& (OP_MASK_VSEL
<< OP_SH_VSEL
))
8583 ip
->insn_opcode
|= MDMX_FMTSEL_IMM_QH
<< OP_SH_VSEL
;
8585 ip
->insn_opcode
|= MDMX_FMTSEL_IMM_OB
<< OP_SH_VSEL
;
8586 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_FT
;
8587 imm_expr
.X_op
= O_absent
;
8591 /* Not MDMX Immediate. Fall through. */
8592 case 'X': /* MDMX destination register. */
8593 case 'Y': /* MDMX source register. */
8594 case 'Z': /* MDMX target register. */
8596 case 'D': /* floating point destination register */
8597 case 'S': /* floating point source register */
8598 case 'T': /* floating point target register */
8599 case 'R': /* floating point source register */
8603 /* Accept $fN for FP and MDMX register numbers, and in
8604 addition accept $vN for MDMX register numbers. */
8605 if ((s
[0] == '$' && s
[1] == 'f' && ISDIGIT (s
[2]))
8606 || (is_mdmx
!= 0 && s
[0] == '$' && s
[1] == 'v'
8617 while (ISDIGIT (*s
));
8620 as_bad (_("Invalid float register number (%d)"), regno
);
8622 if ((regno
& 1) != 0
8624 && ! (strcmp (str
, "mtc1") == 0
8625 || strcmp (str
, "mfc1") == 0
8626 || strcmp (str
, "lwc1") == 0
8627 || strcmp (str
, "swc1") == 0
8628 || strcmp (str
, "l.s") == 0
8629 || strcmp (str
, "s.s") == 0))
8630 as_warn (_("Float register should be even, was %d"),
8638 if (c
== 'V' || c
== 'W')
8649 ip
->insn_opcode
|= regno
<< OP_SH_FD
;
8654 ip
->insn_opcode
|= regno
<< OP_SH_FS
;
8657 /* This is like 'Z', but also needs to fix the MDMX
8658 vector/scalar select bits. Note that the
8659 scalar immediate case is handled above. */
8662 int is_qh
= (ip
->insn_opcode
& (1 << OP_SH_VSEL
));
8663 int max_el
= (is_qh
? 3 : 7);
8665 my_getExpression(&imm_expr
, s
);
8666 check_absolute_expr (ip
, &imm_expr
);
8668 if (imm_expr
.X_add_number
> max_el
)
8669 as_bad(_("Bad element selector %ld"),
8670 (long) imm_expr
.X_add_number
);
8671 imm_expr
.X_add_number
&= max_el
;
8672 ip
->insn_opcode
|= (imm_expr
.X_add_number
8675 imm_expr
.X_op
= O_absent
;
8677 as_warn(_("Expecting ']' found '%s'"), s
);
8683 if (ip
->insn_opcode
& (OP_MASK_VSEL
<< OP_SH_VSEL
))
8684 ip
->insn_opcode
|= (MDMX_FMTSEL_VEC_QH
8687 ip
->insn_opcode
|= (MDMX_FMTSEL_VEC_OB
<<
8694 ip
->insn_opcode
|= regno
<< OP_SH_FT
;
8697 ip
->insn_opcode
|= regno
<< OP_SH_FR
;
8707 ip
->insn_opcode
|= lastregno
<< OP_SH_FS
;
8710 ip
->insn_opcode
|= lastregno
<< OP_SH_FT
;
8716 my_getExpression (&imm_expr
, s
);
8717 if (imm_expr
.X_op
!= O_big
8718 && imm_expr
.X_op
!= O_constant
)
8719 insn_error
= _("absolute expression required");
8720 normalize_constant_expr (&imm_expr
);
8725 my_getExpression (&offset_expr
, s
);
8726 *imm_reloc
= BFD_RELOC_32
;
8739 unsigned char temp
[8];
8741 unsigned int length
;
8746 /* These only appear as the last operand in an
8747 instruction, and every instruction that accepts
8748 them in any variant accepts them in all variants.
8749 This means we don't have to worry about backing out
8750 any changes if the instruction does not match.
8752 The difference between them is the size of the
8753 floating point constant and where it goes. For 'F'
8754 and 'L' the constant is 64 bits; for 'f' and 'l' it
8755 is 32 bits. Where the constant is placed is based
8756 on how the MIPS assembler does things:
8759 f -- immediate value
8762 The .lit4 and .lit8 sections are only used if
8763 permitted by the -G argument.
8765 The code below needs to know whether the target register
8766 is 32 or 64 bits wide. It relies on the fact 'f' and
8767 'F' are used with GPR-based instructions and 'l' and
8768 'L' are used with FPR-based instructions. */
8770 f64
= *args
== 'F' || *args
== 'L';
8771 using_gprs
= *args
== 'F' || *args
== 'f';
8773 save_in
= input_line_pointer
;
8774 input_line_pointer
= s
;
8775 err
= md_atof (f64
? 'd' : 'f', (char *) temp
, &len
);
8777 s
= input_line_pointer
;
8778 input_line_pointer
= save_in
;
8779 if (err
!= NULL
&& *err
!= '\0')
8781 as_bad (_("Bad floating point constant: %s"), err
);
8782 memset (temp
, '\0', sizeof temp
);
8783 length
= f64
? 8 : 4;
8786 assert (length
== (unsigned) (f64
? 8 : 4));
8790 && (g_switch_value
< 4
8791 || (temp
[0] == 0 && temp
[1] == 0)
8792 || (temp
[2] == 0 && temp
[3] == 0))))
8794 imm_expr
.X_op
= O_constant
;
8795 if (! target_big_endian
)
8796 imm_expr
.X_add_number
= bfd_getl32 (temp
);
8798 imm_expr
.X_add_number
= bfd_getb32 (temp
);
8801 && ! mips_disable_float_construction
8802 /* Constants can only be constructed in GPRs and
8803 copied to FPRs if the GPRs are at least as wide
8804 as the FPRs. Force the constant into memory if
8805 we are using 64-bit FPRs but the GPRs are only
8808 || ! (HAVE_64BIT_FPRS
&& HAVE_32BIT_GPRS
))
8809 && ((temp
[0] == 0 && temp
[1] == 0)
8810 || (temp
[2] == 0 && temp
[3] == 0))
8811 && ((temp
[4] == 0 && temp
[5] == 0)
8812 || (temp
[6] == 0 && temp
[7] == 0)))
8814 /* The value is simple enough to load with a couple of
8815 instructions. If using 32-bit registers, set
8816 imm_expr to the high order 32 bits and offset_expr to
8817 the low order 32 bits. Otherwise, set imm_expr to
8818 the entire 64 bit constant. */
8819 if (using_gprs
? HAVE_32BIT_GPRS
: HAVE_32BIT_FPRS
)
8821 imm_expr
.X_op
= O_constant
;
8822 offset_expr
.X_op
= O_constant
;
8823 if (! target_big_endian
)
8825 imm_expr
.X_add_number
= bfd_getl32 (temp
+ 4);
8826 offset_expr
.X_add_number
= bfd_getl32 (temp
);
8830 imm_expr
.X_add_number
= bfd_getb32 (temp
);
8831 offset_expr
.X_add_number
= bfd_getb32 (temp
+ 4);
8833 if (offset_expr
.X_add_number
== 0)
8834 offset_expr
.X_op
= O_absent
;
8836 else if (sizeof (imm_expr
.X_add_number
) > 4)
8838 imm_expr
.X_op
= O_constant
;
8839 if (! target_big_endian
)
8840 imm_expr
.X_add_number
= bfd_getl64 (temp
);
8842 imm_expr
.X_add_number
= bfd_getb64 (temp
);
8846 imm_expr
.X_op
= O_big
;
8847 imm_expr
.X_add_number
= 4;
8848 if (! target_big_endian
)
8850 generic_bignum
[0] = bfd_getl16 (temp
);
8851 generic_bignum
[1] = bfd_getl16 (temp
+ 2);
8852 generic_bignum
[2] = bfd_getl16 (temp
+ 4);
8853 generic_bignum
[3] = bfd_getl16 (temp
+ 6);
8857 generic_bignum
[0] = bfd_getb16 (temp
+ 6);
8858 generic_bignum
[1] = bfd_getb16 (temp
+ 4);
8859 generic_bignum
[2] = bfd_getb16 (temp
+ 2);
8860 generic_bignum
[3] = bfd_getb16 (temp
);
8866 const char *newname
;
8869 /* Switch to the right section. */
8871 subseg
= now_subseg
;
8874 default: /* unused default case avoids warnings. */
8876 newname
= RDATA_SECTION_NAME
;
8877 if (g_switch_value
>= 8)
8881 newname
= RDATA_SECTION_NAME
;
8884 assert (g_switch_value
>= 4);
8888 new_seg
= subseg_new (newname
, (subsegT
) 0);
8889 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
8890 bfd_set_section_flags (stdoutput
, new_seg
,
8895 frag_align (*args
== 'l' ? 2 : 3, 0, 0);
8896 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
8897 && strcmp (TARGET_OS
, "elf") != 0)
8898 record_alignment (new_seg
, 4);
8900 record_alignment (new_seg
, *args
== 'l' ? 2 : 3);
8902 as_bad (_("Can't use floating point insn in this section"));
8904 /* Set the argument to the current address in the
8906 offset_expr
.X_op
= O_symbol
;
8907 offset_expr
.X_add_symbol
=
8908 symbol_new ("L0\001", now_seg
,
8909 (valueT
) frag_now_fix (), frag_now
);
8910 offset_expr
.X_add_number
= 0;
8912 /* Put the floating point number into the section. */
8913 p
= frag_more ((int) length
);
8914 memcpy (p
, temp
, length
);
8916 /* Switch back to the original section. */
8917 subseg_set (seg
, subseg
);
8922 case 'i': /* 16 bit unsigned immediate */
8923 case 'j': /* 16 bit signed immediate */
8924 *imm_reloc
= BFD_RELOC_LO16
;
8925 if (my_getSmallExpression (&imm_expr
, imm_reloc
, s
) == 0)
8928 offsetT minval
, maxval
;
8930 more
= (insn
+ 1 < &mips_opcodes
[NUMOPCODES
]
8931 && strcmp (insn
->name
, insn
[1].name
) == 0);
8933 /* If the expression was written as an unsigned number,
8934 only treat it as signed if there are no more
8938 && sizeof (imm_expr
.X_add_number
) <= 4
8939 && imm_expr
.X_op
== O_constant
8940 && imm_expr
.X_add_number
< 0
8941 && imm_expr
.X_unsigned
8945 /* For compatibility with older assemblers, we accept
8946 0x8000-0xffff as signed 16-bit numbers when only
8947 signed numbers are allowed. */
8949 minval
= 0, maxval
= 0xffff;
8951 minval
= -0x8000, maxval
= 0x7fff;
8953 minval
= -0x8000, maxval
= 0xffff;
8955 if (imm_expr
.X_op
!= O_constant
8956 || imm_expr
.X_add_number
< minval
8957 || imm_expr
.X_add_number
> maxval
)
8961 if (imm_expr
.X_op
== O_constant
8962 || imm_expr
.X_op
== O_big
)
8963 as_bad (_("expression out of range"));
8969 case 'o': /* 16 bit offset */
8970 /* Check whether there is only a single bracketed expression
8971 left. If so, it must be the base register and the
8972 constant must be zero. */
8973 if (*s
== '(' && strchr (s
+ 1, '(') == 0)
8975 offset_expr
.X_op
= O_constant
;
8976 offset_expr
.X_add_number
= 0;
8980 /* If this value won't fit into a 16 bit offset, then go
8981 find a macro that will generate the 32 bit offset
8983 if (my_getSmallExpression (&offset_expr
, offset_reloc
, s
) == 0
8984 && (offset_expr
.X_op
!= O_constant
8985 || offset_expr
.X_add_number
>= 0x8000
8986 || offset_expr
.X_add_number
< -0x8000))
8992 case 'p': /* pc relative offset */
8993 *offset_reloc
= BFD_RELOC_16_PCREL_S2
;
8994 my_getExpression (&offset_expr
, s
);
8998 case 'u': /* upper 16 bits */
8999 if (my_getSmallExpression (&imm_expr
, imm_reloc
, s
) == 0
9000 && imm_expr
.X_op
== O_constant
9001 && (imm_expr
.X_add_number
< 0
9002 || imm_expr
.X_add_number
>= 0x10000))
9003 as_bad (_("lui expression not in range 0..65535"));
9007 case 'a': /* 26 bit address */
9008 my_getExpression (&offset_expr
, s
);
9010 *offset_reloc
= BFD_RELOC_MIPS_JMP
;
9013 case 'N': /* 3 bit branch condition code */
9014 case 'M': /* 3 bit compare condition code */
9015 if (strncmp (s
, "$fcc", 4) != 0)
9025 while (ISDIGIT (*s
));
9027 as_bad (_("Invalid condition code register $fcc%d"), regno
);
9028 if ((strcmp(str
+ strlen(str
) - 3, ".ps") == 0
9029 || strcmp(str
+ strlen(str
) - 5, "any2f") == 0
9030 || strcmp(str
+ strlen(str
) - 5, "any2t") == 0)
9031 && (regno
& 1) != 0)
9032 as_warn(_("Condition code register should be even for %s, was %d"),
9034 if ((strcmp(str
+ strlen(str
) - 5, "any4f") == 0
9035 || strcmp(str
+ strlen(str
) - 5, "any4t") == 0)
9036 && (regno
& 3) != 0)
9037 as_warn(_("Condition code register should be 0 or 4 for %s, was %d"),
9040 ip
->insn_opcode
|= regno
<< OP_SH_BCC
;
9042 ip
->insn_opcode
|= regno
<< OP_SH_CCC
;
9046 if (s
[0] == '0' && (s
[1] == 'x' || s
[1] == 'X'))
9057 while (ISDIGIT (*s
));
9060 c
= 8; /* Invalid sel value. */
9063 as_bad (_("invalid coprocessor sub-selection value (0-7)"));
9064 ip
->insn_opcode
|= c
;
9068 /* Must be at least one digit. */
9069 my_getExpression (&imm_expr
, s
);
9070 check_absolute_expr (ip
, &imm_expr
);
9072 if ((unsigned long) imm_expr
.X_add_number
9073 > (unsigned long) OP_MASK_VECBYTE
)
9075 as_bad (_("bad byte vector index (%ld)"),
9076 (long) imm_expr
.X_add_number
);
9077 imm_expr
.X_add_number
= 0;
9080 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_VECBYTE
;
9081 imm_expr
.X_op
= O_absent
;
9086 my_getExpression (&imm_expr
, s
);
9087 check_absolute_expr (ip
, &imm_expr
);
9089 if ((unsigned long) imm_expr
.X_add_number
9090 > (unsigned long) OP_MASK_VECALIGN
)
9092 as_bad (_("bad byte vector index (%ld)"),
9093 (long) imm_expr
.X_add_number
);
9094 imm_expr
.X_add_number
= 0;
9097 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_VECALIGN
;
9098 imm_expr
.X_op
= O_absent
;
9103 as_bad (_("bad char = '%c'\n"), *args
);
9108 /* Args don't match. */
9109 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
9110 !strcmp (insn
->name
, insn
[1].name
))
9114 insn_error
= _("illegal operands");
9119 insn_error
= _("illegal operands");
9124 /* This routine assembles an instruction into its binary format when
9125 assembling for the mips16. As a side effect, it sets one of the
9126 global variables imm_reloc or offset_reloc to the type of
9127 relocation to do if one of the operands is an address expression.
9128 It also sets mips16_small and mips16_ext if the user explicitly
9129 requested a small or extended instruction. */
9132 mips16_ip (char *str
, struct mips_cl_insn
*ip
)
9136 struct mips_opcode
*insn
;
9139 unsigned int lastregno
= 0;
9145 mips16_small
= FALSE
;
9148 for (s
= str
; ISLOWER (*s
); ++s
)
9160 if (s
[1] == 't' && s
[2] == ' ')
9163 mips16_small
= TRUE
;
9167 else if (s
[1] == 'e' && s
[2] == ' ')
9176 insn_error
= _("unknown opcode");
9180 if (mips_opts
.noautoextend
&& ! mips16_ext
)
9181 mips16_small
= TRUE
;
9183 if ((insn
= (struct mips_opcode
*) hash_find (mips16_op_hash
, str
)) == NULL
)
9185 insn_error
= _("unrecognized opcode");
9192 assert (strcmp (insn
->name
, str
) == 0);
9195 ip
->insn_opcode
= insn
->match
;
9196 ip
->use_extend
= FALSE
;
9197 imm_expr
.X_op
= O_absent
;
9198 imm_reloc
[0] = BFD_RELOC_UNUSED
;
9199 imm_reloc
[1] = BFD_RELOC_UNUSED
;
9200 imm_reloc
[2] = BFD_RELOC_UNUSED
;
9201 imm2_expr
.X_op
= O_absent
;
9202 offset_expr
.X_op
= O_absent
;
9203 offset_reloc
[0] = BFD_RELOC_UNUSED
;
9204 offset_reloc
[1] = BFD_RELOC_UNUSED
;
9205 offset_reloc
[2] = BFD_RELOC_UNUSED
;
9206 for (args
= insn
->args
; 1; ++args
)
9213 /* In this switch statement we call break if we did not find
9214 a match, continue if we did find a match, or return if we
9223 /* Stuff the immediate value in now, if we can. */
9224 if (imm_expr
.X_op
== O_constant
9225 && *imm_reloc
> BFD_RELOC_UNUSED
9226 && insn
->pinfo
!= INSN_MACRO
)
9230 switch (*offset_reloc
)
9232 case BFD_RELOC_MIPS16_HI16_S
:
9233 tmp
= (imm_expr
.X_add_number
+ 0x8000) >> 16;
9236 case BFD_RELOC_MIPS16_HI16
:
9237 tmp
= imm_expr
.X_add_number
>> 16;
9240 case BFD_RELOC_MIPS16_LO16
:
9241 tmp
= ((imm_expr
.X_add_number
+ 0x8000) & 0xffff)
9245 case BFD_RELOC_UNUSED
:
9246 tmp
= imm_expr
.X_add_number
;
9252 *offset_reloc
= BFD_RELOC_UNUSED
;
9254 mips16_immed (NULL
, 0, *imm_reloc
- BFD_RELOC_UNUSED
,
9255 tmp
, TRUE
, mips16_small
,
9256 mips16_ext
, &ip
->insn_opcode
,
9257 &ip
->use_extend
, &ip
->extend
);
9258 imm_expr
.X_op
= O_absent
;
9259 *imm_reloc
= BFD_RELOC_UNUSED
;
9273 ip
->insn_opcode
|= lastregno
<< MIPS16OP_SH_RX
;
9276 ip
->insn_opcode
|= lastregno
<< MIPS16OP_SH_RY
;
9292 ip
->insn_opcode
|= lastregno
<< MIPS16OP_SH_RX
;
9294 ip
->insn_opcode
|= lastregno
<< MIPS16OP_SH_RY
;
9321 while (ISDIGIT (*s
));
9324 as_bad (_("invalid register number (%d)"), regno
);
9330 if (s
[1] == 'r' && s
[2] == 'a')
9335 else if (s
[1] == 'f' && s
[2] == 'p')
9340 else if (s
[1] == 's' && s
[2] == 'p')
9345 else if (s
[1] == 'g' && s
[2] == 'p')
9350 else if (s
[1] == 'a' && s
[2] == 't')
9355 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '0')
9360 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '1')
9365 else if (s
[1] == 'z' && s
[2] == 'e' && s
[3] == 'r' && s
[4] == 'o')
9378 if (c
== 'v' || c
== 'w')
9380 regno
= mips16_to_32_reg_map
[lastregno
];
9394 regno
= mips32_to_16_reg_map
[regno
];
9399 regno
= ILLEGAL_REG
;
9404 regno
= ILLEGAL_REG
;
9409 regno
= ILLEGAL_REG
;
9414 if (regno
== AT
&& ! mips_opts
.noat
)
9415 as_warn (_("used $at without \".set noat\""));
9422 if (regno
== ILLEGAL_REG
)
9429 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_RX
;
9433 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_RY
;
9436 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_RZ
;
9439 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_MOVE32Z
;
9445 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_REGR32
;
9448 regno
= ((regno
& 7) << 2) | ((regno
& 0x18) >> 3);
9449 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_REG32R
;
9459 if (strncmp (s
, "$pc", 3) == 0)
9476 i
= my_getSmallExpression (&imm_expr
, imm_reloc
, s
);
9479 if (imm_expr
.X_op
!= O_constant
)
9482 ip
->use_extend
= TRUE
;
9487 /* We need to relax this instruction. */
9488 *offset_reloc
= *imm_reloc
;
9489 *imm_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
9494 *imm_reloc
= BFD_RELOC_UNUSED
;
9502 my_getExpression (&imm_expr
, s
);
9503 if (imm_expr
.X_op
== O_register
)
9505 /* What we thought was an expression turned out to
9508 if (s
[0] == '(' && args
[1] == '(')
9510 /* It looks like the expression was omitted
9511 before a register indirection, which means
9512 that the expression is implicitly zero. We
9513 still set up imm_expr, so that we handle
9514 explicit extensions correctly. */
9515 imm_expr
.X_op
= O_constant
;
9516 imm_expr
.X_add_number
= 0;
9517 *imm_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
9524 /* We need to relax this instruction. */
9525 *imm_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
9534 /* We use offset_reloc rather than imm_reloc for the PC
9535 relative operands. This lets macros with both
9536 immediate and address operands work correctly. */
9537 my_getExpression (&offset_expr
, s
);
9539 if (offset_expr
.X_op
== O_register
)
9542 /* We need to relax this instruction. */
9543 *offset_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
9547 case '6': /* break code */
9548 my_getExpression (&imm_expr
, s
);
9549 check_absolute_expr (ip
, &imm_expr
);
9550 if ((unsigned long) imm_expr
.X_add_number
> 63)
9552 as_warn (_("Invalid value for `%s' (%lu)"),
9554 (unsigned long) imm_expr
.X_add_number
);
9555 imm_expr
.X_add_number
&= 0x3f;
9557 ip
->insn_opcode
|= imm_expr
.X_add_number
<< MIPS16OP_SH_IMM6
;
9558 imm_expr
.X_op
= O_absent
;
9562 case 'a': /* 26 bit address */
9563 my_getExpression (&offset_expr
, s
);
9565 *offset_reloc
= BFD_RELOC_MIPS16_JMP
;
9566 ip
->insn_opcode
<<= 16;
9569 case 'l': /* register list for entry macro */
9570 case 'L': /* register list for exit macro */
9580 int freg
, reg1
, reg2
;
9582 while (*s
== ' ' || *s
== ',')
9586 as_bad (_("can't parse register list"));
9598 while (ISDIGIT (*s
))
9620 as_bad (_("invalid register list"));
9625 while (ISDIGIT (*s
))
9632 if (freg
&& reg1
== 0 && reg2
== 0 && c
== 'L')
9637 else if (freg
&& reg1
== 0 && reg2
== 1 && c
== 'L')
9642 else if (reg1
== 4 && reg2
>= 4 && reg2
<= 7 && c
!= 'L')
9643 mask
|= (reg2
- 3) << 3;
9644 else if (reg1
== 16 && reg2
>= 16 && reg2
<= 17)
9645 mask
|= (reg2
- 15) << 1;
9646 else if (reg1
== RA
&& reg2
== RA
)
9650 as_bad (_("invalid register list"));
9654 /* The mask is filled in in the opcode table for the
9655 benefit of the disassembler. We remove it before
9656 applying the actual mask. */
9657 ip
->insn_opcode
&= ~ ((7 << 3) << MIPS16OP_SH_IMM6
);
9658 ip
->insn_opcode
|= mask
<< MIPS16OP_SH_IMM6
;
9662 case 'e': /* extend code */
9663 my_getExpression (&imm_expr
, s
);
9664 check_absolute_expr (ip
, &imm_expr
);
9665 if ((unsigned long) imm_expr
.X_add_number
> 0x7ff)
9667 as_warn (_("Invalid value for `%s' (%lu)"),
9669 (unsigned long) imm_expr
.X_add_number
);
9670 imm_expr
.X_add_number
&= 0x7ff;
9672 ip
->insn_opcode
|= imm_expr
.X_add_number
;
9673 imm_expr
.X_op
= O_absent
;
9683 /* Args don't match. */
9684 if (insn
+ 1 < &mips16_opcodes
[bfd_mips16_num_opcodes
] &&
9685 strcmp (insn
->name
, insn
[1].name
) == 0)
9692 insn_error
= _("illegal operands");
9698 /* This structure holds information we know about a mips16 immediate
9701 struct mips16_immed_operand
9703 /* The type code used in the argument string in the opcode table. */
9705 /* The number of bits in the short form of the opcode. */
9707 /* The number of bits in the extended form of the opcode. */
9709 /* The amount by which the short form is shifted when it is used;
9710 for example, the sw instruction has a shift count of 2. */
9712 /* The amount by which the short form is shifted when it is stored
9713 into the instruction code. */
9715 /* Non-zero if the short form is unsigned. */
9717 /* Non-zero if the extended form is unsigned. */
9719 /* Non-zero if the value is PC relative. */
9723 /* The mips16 immediate operand types. */
9725 static const struct mips16_immed_operand mips16_immed_operands
[] =
9727 { '<', 3, 5, 0, MIPS16OP_SH_RZ
, 1, 1, 0 },
9728 { '>', 3, 5, 0, MIPS16OP_SH_RX
, 1, 1, 0 },
9729 { '[', 3, 6, 0, MIPS16OP_SH_RZ
, 1, 1, 0 },
9730 { ']', 3, 6, 0, MIPS16OP_SH_RX
, 1, 1, 0 },
9731 { '4', 4, 15, 0, MIPS16OP_SH_IMM4
, 0, 0, 0 },
9732 { '5', 5, 16, 0, MIPS16OP_SH_IMM5
, 1, 0, 0 },
9733 { 'H', 5, 16, 1, MIPS16OP_SH_IMM5
, 1, 0, 0 },
9734 { 'W', 5, 16, 2, MIPS16OP_SH_IMM5
, 1, 0, 0 },
9735 { 'D', 5, 16, 3, MIPS16OP_SH_IMM5
, 1, 0, 0 },
9736 { 'j', 5, 16, 0, MIPS16OP_SH_IMM5
, 0, 0, 0 },
9737 { '8', 8, 16, 0, MIPS16OP_SH_IMM8
, 1, 0, 0 },
9738 { 'V', 8, 16, 2, MIPS16OP_SH_IMM8
, 1, 0, 0 },
9739 { 'C', 8, 16, 3, MIPS16OP_SH_IMM8
, 1, 0, 0 },
9740 { 'U', 8, 16, 0, MIPS16OP_SH_IMM8
, 1, 1, 0 },
9741 { 'k', 8, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 0 },
9742 { 'K', 8, 16, 3, MIPS16OP_SH_IMM8
, 0, 0, 0 },
9743 { 'p', 8, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 1 },
9744 { 'q', 11, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 1 },
9745 { 'A', 8, 16, 2, MIPS16OP_SH_IMM8
, 1, 0, 1 },
9746 { 'B', 5, 16, 3, MIPS16OP_SH_IMM5
, 1, 0, 1 },
9747 { 'E', 5, 16, 2, MIPS16OP_SH_IMM5
, 1, 0, 1 }
9750 #define MIPS16_NUM_IMMED \
9751 (sizeof mips16_immed_operands / sizeof mips16_immed_operands[0])
9753 /* Handle a mips16 instruction with an immediate value. This or's the
9754 small immediate value into *INSN. It sets *USE_EXTEND to indicate
9755 whether an extended value is needed; if one is needed, it sets
9756 *EXTEND to the value. The argument type is TYPE. The value is VAL.
9757 If SMALL is true, an unextended opcode was explicitly requested.
9758 If EXT is true, an extended opcode was explicitly requested. If
9759 WARN is true, warn if EXT does not match reality. */
9762 mips16_immed (char *file
, unsigned int line
, int type
, offsetT val
,
9763 bfd_boolean warn
, bfd_boolean small
, bfd_boolean ext
,
9764 unsigned long *insn
, bfd_boolean
*use_extend
,
9765 unsigned short *extend
)
9767 register const struct mips16_immed_operand
*op
;
9768 int mintiny
, maxtiny
;
9769 bfd_boolean needext
;
9771 op
= mips16_immed_operands
;
9772 while (op
->type
!= type
)
9775 assert (op
< mips16_immed_operands
+ MIPS16_NUM_IMMED
);
9780 if (type
== '<' || type
== '>' || type
== '[' || type
== ']')
9783 maxtiny
= 1 << op
->nbits
;
9788 maxtiny
= (1 << op
->nbits
) - 1;
9793 mintiny
= - (1 << (op
->nbits
- 1));
9794 maxtiny
= (1 << (op
->nbits
- 1)) - 1;
9797 /* Branch offsets have an implicit 0 in the lowest bit. */
9798 if (type
== 'p' || type
== 'q')
9801 if ((val
& ((1 << op
->shift
) - 1)) != 0
9802 || val
< (mintiny
<< op
->shift
)
9803 || val
> (maxtiny
<< op
->shift
))
9808 if (warn
&& ext
&& ! needext
)
9809 as_warn_where (file
, line
,
9810 _("extended operand requested but not required"));
9811 if (small
&& needext
)
9812 as_bad_where (file
, line
, _("invalid unextended operand value"));
9814 if (small
|| (! ext
&& ! needext
))
9818 *use_extend
= FALSE
;
9819 insnval
= ((val
>> op
->shift
) & ((1 << op
->nbits
) - 1));
9820 insnval
<<= op
->op_shift
;
9825 long minext
, maxext
;
9831 maxext
= (1 << op
->extbits
) - 1;
9835 minext
= - (1 << (op
->extbits
- 1));
9836 maxext
= (1 << (op
->extbits
- 1)) - 1;
9838 if (val
< minext
|| val
> maxext
)
9839 as_bad_where (file
, line
,
9840 _("operand value out of range for instruction"));
9843 if (op
->extbits
== 16)
9845 extval
= ((val
>> 11) & 0x1f) | (val
& 0x7e0);
9848 else if (op
->extbits
== 15)
9850 extval
= ((val
>> 11) & 0xf) | (val
& 0x7f0);
9855 extval
= ((val
& 0x1f) << 6) | (val
& 0x20);
9859 *extend
= (unsigned short) extval
;
9864 struct percent_op_match
9867 bfd_reloc_code_real_type reloc
;
9870 static const struct percent_op_match mips_percent_op
[] =
9872 {"%lo", BFD_RELOC_LO16
},
9874 {"%call_hi", BFD_RELOC_MIPS_CALL_HI16
},
9875 {"%call_lo", BFD_RELOC_MIPS_CALL_LO16
},
9876 {"%call16", BFD_RELOC_MIPS_CALL16
},
9877 {"%got_disp", BFD_RELOC_MIPS_GOT_DISP
},
9878 {"%got_page", BFD_RELOC_MIPS_GOT_PAGE
},
9879 {"%got_ofst", BFD_RELOC_MIPS_GOT_OFST
},
9880 {"%got_hi", BFD_RELOC_MIPS_GOT_HI16
},
9881 {"%got_lo", BFD_RELOC_MIPS_GOT_LO16
},
9882 {"%got", BFD_RELOC_MIPS_GOT16
},
9883 {"%gp_rel", BFD_RELOC_GPREL16
},
9884 {"%half", BFD_RELOC_16
},
9885 {"%highest", BFD_RELOC_MIPS_HIGHEST
},
9886 {"%higher", BFD_RELOC_MIPS_HIGHER
},
9887 {"%neg", BFD_RELOC_MIPS_SUB
},
9888 {"%tlsgd", BFD_RELOC_MIPS_TLS_GD
},
9889 {"%tlsldm", BFD_RELOC_MIPS_TLS_LDM
},
9890 {"%dtprel_hi", BFD_RELOC_MIPS_TLS_DTPREL_HI16
},
9891 {"%dtprel_lo", BFD_RELOC_MIPS_TLS_DTPREL_LO16
},
9892 {"%tprel_hi", BFD_RELOC_MIPS_TLS_TPREL_HI16
},
9893 {"%tprel_lo", BFD_RELOC_MIPS_TLS_TPREL_LO16
},
9894 {"%gottprel", BFD_RELOC_MIPS_TLS_GOTTPREL
},
9896 {"%hi", BFD_RELOC_HI16_S
}
9899 static const struct percent_op_match mips16_percent_op
[] =
9901 {"%lo", BFD_RELOC_MIPS16_LO16
},
9902 {"%gprel", BFD_RELOC_MIPS16_GPREL
},
9903 {"%hi", BFD_RELOC_MIPS16_HI16_S
}
9907 /* Return true if *STR points to a relocation operator. When returning true,
9908 move *STR over the operator and store its relocation code in *RELOC.
9909 Leave both *STR and *RELOC alone when returning false. */
9912 parse_relocation (char **str
, bfd_reloc_code_real_type
*reloc
)
9914 const struct percent_op_match
*percent_op
;
9917 if (mips_opts
.mips16
)
9919 percent_op
= mips16_percent_op
;
9920 limit
= ARRAY_SIZE (mips16_percent_op
);
9924 percent_op
= mips_percent_op
;
9925 limit
= ARRAY_SIZE (mips_percent_op
);
9928 for (i
= 0; i
< limit
; i
++)
9929 if (strncasecmp (*str
, percent_op
[i
].str
, strlen (percent_op
[i
].str
)) == 0)
9931 int len
= strlen (percent_op
[i
].str
);
9933 if (!ISSPACE ((*str
)[len
]) && (*str
)[len
] != '(')
9936 *str
+= strlen (percent_op
[i
].str
);
9937 *reloc
= percent_op
[i
].reloc
;
9939 /* Check whether the output BFD supports this relocation.
9940 If not, issue an error and fall back on something safe. */
9941 if (!bfd_reloc_type_lookup (stdoutput
, percent_op
[i
].reloc
))
9943 as_bad ("relocation %s isn't supported by the current ABI",
9945 *reloc
= BFD_RELOC_UNUSED
;
9953 /* Parse string STR as a 16-bit relocatable operand. Store the
9954 expression in *EP and the relocations in the array starting
9955 at RELOC. Return the number of relocation operators used.
9957 On exit, EXPR_END points to the first character after the expression. */
9960 my_getSmallExpression (expressionS
*ep
, bfd_reloc_code_real_type
*reloc
,
9963 bfd_reloc_code_real_type reversed_reloc
[3];
9964 size_t reloc_index
, i
;
9965 int crux_depth
, str_depth
;
9968 /* Search for the start of the main expression, recoding relocations
9969 in REVERSED_RELOC. End the loop with CRUX pointing to the start
9970 of the main expression and with CRUX_DEPTH containing the number
9971 of open brackets at that point. */
9978 crux_depth
= str_depth
;
9980 /* Skip over whitespace and brackets, keeping count of the number
9982 while (*str
== ' ' || *str
== '\t' || *str
== '(')
9987 && reloc_index
< (HAVE_NEWABI
? 3 : 1)
9988 && parse_relocation (&str
, &reversed_reloc
[reloc_index
]));
9990 my_getExpression (ep
, crux
);
9993 /* Match every open bracket. */
9994 while (crux_depth
> 0 && (*str
== ')' || *str
== ' ' || *str
== '\t'))
9999 as_bad ("unclosed '('");
10003 if (reloc_index
!= 0)
10005 prev_reloc_op_frag
= frag_now
;
10006 for (i
= 0; i
< reloc_index
; i
++)
10007 reloc
[i
] = reversed_reloc
[reloc_index
- 1 - i
];
10010 return reloc_index
;
10014 my_getExpression (expressionS
*ep
, char *str
)
10019 save_in
= input_line_pointer
;
10020 input_line_pointer
= str
;
10022 expr_end
= input_line_pointer
;
10023 input_line_pointer
= save_in
;
10025 /* If we are in mips16 mode, and this is an expression based on `.',
10026 then we bump the value of the symbol by 1 since that is how other
10027 text symbols are handled. We don't bother to handle complex
10028 expressions, just `.' plus or minus a constant. */
10029 if (mips_opts
.mips16
10030 && ep
->X_op
== O_symbol
10031 && strcmp (S_GET_NAME (ep
->X_add_symbol
), FAKE_LABEL_NAME
) == 0
10032 && S_GET_SEGMENT (ep
->X_add_symbol
) == now_seg
10033 && symbol_get_frag (ep
->X_add_symbol
) == frag_now
10034 && symbol_constant_p (ep
->X_add_symbol
)
10035 && (val
= S_GET_VALUE (ep
->X_add_symbol
)) == frag_now_fix ())
10036 S_SET_VALUE (ep
->X_add_symbol
, val
+ 1);
10039 /* Turn a string in input_line_pointer into a floating point constant
10040 of type TYPE, and store the appropriate bytes in *LITP. The number
10041 of LITTLENUMS emitted is stored in *SIZEP. An error message is
10042 returned, or NULL on OK. */
10045 md_atof (int type
, char *litP
, int *sizeP
)
10048 LITTLENUM_TYPE words
[4];
10064 return _("bad call to md_atof");
10067 t
= atof_ieee (input_line_pointer
, type
, words
);
10069 input_line_pointer
= t
;
10073 if (! target_big_endian
)
10075 for (i
= prec
- 1; i
>= 0; i
--)
10077 md_number_to_chars (litP
, words
[i
], 2);
10083 for (i
= 0; i
< prec
; i
++)
10085 md_number_to_chars (litP
, words
[i
], 2);
10094 md_number_to_chars (char *buf
, valueT val
, int n
)
10096 if (target_big_endian
)
10097 number_to_chars_bigendian (buf
, val
, n
);
10099 number_to_chars_littleendian (buf
, val
, n
);
10103 static int support_64bit_objects(void)
10105 const char **list
, **l
;
10108 list
= bfd_target_list ();
10109 for (l
= list
; *l
!= NULL
; l
++)
10111 /* This is traditional mips */
10112 if (strcmp (*l
, "elf64-tradbigmips") == 0
10113 || strcmp (*l
, "elf64-tradlittlemips") == 0)
10115 if (strcmp (*l
, "elf64-bigmips") == 0
10116 || strcmp (*l
, "elf64-littlemips") == 0)
10119 yes
= (*l
!= NULL
);
10123 #endif /* OBJ_ELF */
10125 const char *md_shortopts
= "O::g::G:";
10127 struct option md_longopts
[] =
10129 /* Options which specify architecture. */
10130 #define OPTION_ARCH_BASE (OPTION_MD_BASE)
10131 #define OPTION_MARCH (OPTION_ARCH_BASE + 0)
10132 {"march", required_argument
, NULL
, OPTION_MARCH
},
10133 #define OPTION_MTUNE (OPTION_ARCH_BASE + 1)
10134 {"mtune", required_argument
, NULL
, OPTION_MTUNE
},
10135 #define OPTION_MIPS1 (OPTION_ARCH_BASE + 2)
10136 {"mips0", no_argument
, NULL
, OPTION_MIPS1
},
10137 {"mips1", no_argument
, NULL
, OPTION_MIPS1
},
10138 #define OPTION_MIPS2 (OPTION_ARCH_BASE + 3)
10139 {"mips2", no_argument
, NULL
, OPTION_MIPS2
},
10140 #define OPTION_MIPS3 (OPTION_ARCH_BASE + 4)
10141 {"mips3", no_argument
, NULL
, OPTION_MIPS3
},
10142 #define OPTION_MIPS4 (OPTION_ARCH_BASE + 5)
10143 {"mips4", no_argument
, NULL
, OPTION_MIPS4
},
10144 #define OPTION_MIPS5 (OPTION_ARCH_BASE + 6)
10145 {"mips5", no_argument
, NULL
, OPTION_MIPS5
},
10146 #define OPTION_MIPS32 (OPTION_ARCH_BASE + 7)
10147 {"mips32", no_argument
, NULL
, OPTION_MIPS32
},
10148 #define OPTION_MIPS64 (OPTION_ARCH_BASE + 8)
10149 {"mips64", no_argument
, NULL
, OPTION_MIPS64
},
10150 #define OPTION_MIPS32R2 (OPTION_ARCH_BASE + 9)
10151 {"mips32r2", no_argument
, NULL
, OPTION_MIPS32R2
},
10152 #define OPTION_MIPS64R2 (OPTION_ARCH_BASE + 10)
10153 {"mips64r2", no_argument
, NULL
, OPTION_MIPS64R2
},
10155 /* Options which specify Application Specific Extensions (ASEs). */
10156 #define OPTION_ASE_BASE (OPTION_ARCH_BASE + 11)
10157 #define OPTION_MIPS16 (OPTION_ASE_BASE + 0)
10158 {"mips16", no_argument
, NULL
, OPTION_MIPS16
},
10159 #define OPTION_NO_MIPS16 (OPTION_ASE_BASE + 1)
10160 {"no-mips16", no_argument
, NULL
, OPTION_NO_MIPS16
},
10161 #define OPTION_MIPS3D (OPTION_ASE_BASE + 2)
10162 {"mips3d", no_argument
, NULL
, OPTION_MIPS3D
},
10163 #define OPTION_NO_MIPS3D (OPTION_ASE_BASE + 3)
10164 {"no-mips3d", no_argument
, NULL
, OPTION_NO_MIPS3D
},
10165 #define OPTION_MDMX (OPTION_ASE_BASE + 4)
10166 {"mdmx", no_argument
, NULL
, OPTION_MDMX
},
10167 #define OPTION_NO_MDMX (OPTION_ASE_BASE + 5)
10168 {"no-mdmx", no_argument
, NULL
, OPTION_NO_MDMX
},
10170 /* Old-style architecture options. Don't add more of these. */
10171 #define OPTION_COMPAT_ARCH_BASE (OPTION_ASE_BASE + 6)
10172 #define OPTION_M4650 (OPTION_COMPAT_ARCH_BASE + 0)
10173 {"m4650", no_argument
, NULL
, OPTION_M4650
},
10174 #define OPTION_NO_M4650 (OPTION_COMPAT_ARCH_BASE + 1)
10175 {"no-m4650", no_argument
, NULL
, OPTION_NO_M4650
},
10176 #define OPTION_M4010 (OPTION_COMPAT_ARCH_BASE + 2)
10177 {"m4010", no_argument
, NULL
, OPTION_M4010
},
10178 #define OPTION_NO_M4010 (OPTION_COMPAT_ARCH_BASE + 3)
10179 {"no-m4010", no_argument
, NULL
, OPTION_NO_M4010
},
10180 #define OPTION_M4100 (OPTION_COMPAT_ARCH_BASE + 4)
10181 {"m4100", no_argument
, NULL
, OPTION_M4100
},
10182 #define OPTION_NO_M4100 (OPTION_COMPAT_ARCH_BASE + 5)
10183 {"no-m4100", no_argument
, NULL
, OPTION_NO_M4100
},
10184 #define OPTION_M3900 (OPTION_COMPAT_ARCH_BASE + 6)
10185 {"m3900", no_argument
, NULL
, OPTION_M3900
},
10186 #define OPTION_NO_M3900 (OPTION_COMPAT_ARCH_BASE + 7)
10187 {"no-m3900", no_argument
, NULL
, OPTION_NO_M3900
},
10189 /* Options which enable bug fixes. */
10190 #define OPTION_FIX_BASE (OPTION_COMPAT_ARCH_BASE + 8)
10191 #define OPTION_M7000_HILO_FIX (OPTION_FIX_BASE + 0)
10192 {"mfix7000", no_argument
, NULL
, OPTION_M7000_HILO_FIX
},
10193 #define OPTION_MNO_7000_HILO_FIX (OPTION_FIX_BASE + 1)
10194 {"no-fix-7000", no_argument
, NULL
, OPTION_MNO_7000_HILO_FIX
},
10195 {"mno-fix7000", no_argument
, NULL
, OPTION_MNO_7000_HILO_FIX
},
10196 #define OPTION_FIX_VR4120 (OPTION_FIX_BASE + 2)
10197 #define OPTION_NO_FIX_VR4120 (OPTION_FIX_BASE + 3)
10198 {"mfix-vr4120", no_argument
, NULL
, OPTION_FIX_VR4120
},
10199 {"mno-fix-vr4120", no_argument
, NULL
, OPTION_NO_FIX_VR4120
},
10201 /* Miscellaneous options. */
10202 #define OPTION_MISC_BASE (OPTION_FIX_BASE + 4)
10203 #define OPTION_TRAP (OPTION_MISC_BASE + 0)
10204 {"trap", no_argument
, NULL
, OPTION_TRAP
},
10205 {"no-break", no_argument
, NULL
, OPTION_TRAP
},
10206 #define OPTION_BREAK (OPTION_MISC_BASE + 1)
10207 {"break", no_argument
, NULL
, OPTION_BREAK
},
10208 {"no-trap", no_argument
, NULL
, OPTION_BREAK
},
10209 #define OPTION_EB (OPTION_MISC_BASE + 2)
10210 {"EB", no_argument
, NULL
, OPTION_EB
},
10211 #define OPTION_EL (OPTION_MISC_BASE + 3)
10212 {"EL", no_argument
, NULL
, OPTION_EL
},
10213 #define OPTION_FP32 (OPTION_MISC_BASE + 4)
10214 {"mfp32", no_argument
, NULL
, OPTION_FP32
},
10215 #define OPTION_GP32 (OPTION_MISC_BASE + 5)
10216 {"mgp32", no_argument
, NULL
, OPTION_GP32
},
10217 #define OPTION_CONSTRUCT_FLOATS (OPTION_MISC_BASE + 6)
10218 {"construct-floats", no_argument
, NULL
, OPTION_CONSTRUCT_FLOATS
},
10219 #define OPTION_NO_CONSTRUCT_FLOATS (OPTION_MISC_BASE + 7)
10220 {"no-construct-floats", no_argument
, NULL
, OPTION_NO_CONSTRUCT_FLOATS
},
10221 #define OPTION_FP64 (OPTION_MISC_BASE + 8)
10222 {"mfp64", no_argument
, NULL
, OPTION_FP64
},
10223 #define OPTION_GP64 (OPTION_MISC_BASE + 9)
10224 {"mgp64", no_argument
, NULL
, OPTION_GP64
},
10225 #define OPTION_RELAX_BRANCH (OPTION_MISC_BASE + 10)
10226 #define OPTION_NO_RELAX_BRANCH (OPTION_MISC_BASE + 11)
10227 {"relax-branch", no_argument
, NULL
, OPTION_RELAX_BRANCH
},
10228 {"no-relax-branch", no_argument
, NULL
, OPTION_NO_RELAX_BRANCH
},
10229 #define OPTION_MSHARED (OPTION_MISC_BASE + 12)
10230 #define OPTION_MNO_SHARED (OPTION_MISC_BASE + 13)
10231 {"mshared", no_argument
, NULL
, OPTION_MSHARED
},
10232 {"mno-shared", no_argument
, NULL
, OPTION_MNO_SHARED
},
10233 #define OPTION_MSYM32 (OPTION_MISC_BASE + 14)
10234 #define OPTION_MNO_SYM32 (OPTION_MISC_BASE + 15)
10235 {"msym32", no_argument
, NULL
, OPTION_MSYM32
},
10236 {"mno-sym32", no_argument
, NULL
, OPTION_MNO_SYM32
},
10238 /* ELF-specific options. */
10240 #define OPTION_ELF_BASE (OPTION_MISC_BASE + 16)
10241 #define OPTION_CALL_SHARED (OPTION_ELF_BASE + 0)
10242 {"KPIC", no_argument
, NULL
, OPTION_CALL_SHARED
},
10243 {"call_shared", no_argument
, NULL
, OPTION_CALL_SHARED
},
10244 #define OPTION_NON_SHARED (OPTION_ELF_BASE + 1)
10245 {"non_shared", no_argument
, NULL
, OPTION_NON_SHARED
},
10246 #define OPTION_XGOT (OPTION_ELF_BASE + 2)
10247 {"xgot", no_argument
, NULL
, OPTION_XGOT
},
10248 #define OPTION_MABI (OPTION_ELF_BASE + 3)
10249 {"mabi", required_argument
, NULL
, OPTION_MABI
},
10250 #define OPTION_32 (OPTION_ELF_BASE + 4)
10251 {"32", no_argument
, NULL
, OPTION_32
},
10252 #define OPTION_N32 (OPTION_ELF_BASE + 5)
10253 {"n32", no_argument
, NULL
, OPTION_N32
},
10254 #define OPTION_64 (OPTION_ELF_BASE + 6)
10255 {"64", no_argument
, NULL
, OPTION_64
},
10256 #define OPTION_MDEBUG (OPTION_ELF_BASE + 7)
10257 {"mdebug", no_argument
, NULL
, OPTION_MDEBUG
},
10258 #define OPTION_NO_MDEBUG (OPTION_ELF_BASE + 8)
10259 {"no-mdebug", no_argument
, NULL
, OPTION_NO_MDEBUG
},
10260 #define OPTION_PDR (OPTION_ELF_BASE + 9)
10261 {"mpdr", no_argument
, NULL
, OPTION_PDR
},
10262 #define OPTION_NO_PDR (OPTION_ELF_BASE + 10)
10263 {"mno-pdr", no_argument
, NULL
, OPTION_NO_PDR
},
10264 #endif /* OBJ_ELF */
10266 {NULL
, no_argument
, NULL
, 0}
10268 size_t md_longopts_size
= sizeof (md_longopts
);
10270 /* Set STRING_PTR (either &mips_arch_string or &mips_tune_string) to
10271 NEW_VALUE. Warn if another value was already specified. Note:
10272 we have to defer parsing the -march and -mtune arguments in order
10273 to handle 'from-abi' correctly, since the ABI might be specified
10274 in a later argument. */
10277 mips_set_option_string (const char **string_ptr
, const char *new_value
)
10279 if (*string_ptr
!= 0 && strcasecmp (*string_ptr
, new_value
) != 0)
10280 as_warn (_("A different %s was already specified, is now %s"),
10281 string_ptr
== &mips_arch_string
? "-march" : "-mtune",
10284 *string_ptr
= new_value
;
10288 md_parse_option (int c
, char *arg
)
10292 case OPTION_CONSTRUCT_FLOATS
:
10293 mips_disable_float_construction
= 0;
10296 case OPTION_NO_CONSTRUCT_FLOATS
:
10297 mips_disable_float_construction
= 1;
10309 target_big_endian
= 1;
10313 target_big_endian
= 0;
10317 if (arg
&& arg
[1] == '0')
10327 mips_debug
= atoi (arg
);
10328 /* When the MIPS assembler sees -g or -g2, it does not do
10329 optimizations which limit full symbolic debugging. We take
10330 that to be equivalent to -O0. */
10331 if (mips_debug
== 2)
10336 file_mips_isa
= ISA_MIPS1
;
10340 file_mips_isa
= ISA_MIPS2
;
10344 file_mips_isa
= ISA_MIPS3
;
10348 file_mips_isa
= ISA_MIPS4
;
10352 file_mips_isa
= ISA_MIPS5
;
10355 case OPTION_MIPS32
:
10356 file_mips_isa
= ISA_MIPS32
;
10359 case OPTION_MIPS32R2
:
10360 file_mips_isa
= ISA_MIPS32R2
;
10363 case OPTION_MIPS64R2
:
10364 file_mips_isa
= ISA_MIPS64R2
;
10367 case OPTION_MIPS64
:
10368 file_mips_isa
= ISA_MIPS64
;
10372 mips_set_option_string (&mips_tune_string
, arg
);
10376 mips_set_option_string (&mips_arch_string
, arg
);
10380 mips_set_option_string (&mips_arch_string
, "4650");
10381 mips_set_option_string (&mips_tune_string
, "4650");
10384 case OPTION_NO_M4650
:
10388 mips_set_option_string (&mips_arch_string
, "4010");
10389 mips_set_option_string (&mips_tune_string
, "4010");
10392 case OPTION_NO_M4010
:
10396 mips_set_option_string (&mips_arch_string
, "4100");
10397 mips_set_option_string (&mips_tune_string
, "4100");
10400 case OPTION_NO_M4100
:
10404 mips_set_option_string (&mips_arch_string
, "3900");
10405 mips_set_option_string (&mips_tune_string
, "3900");
10408 case OPTION_NO_M3900
:
10412 mips_opts
.ase_mdmx
= 1;
10415 case OPTION_NO_MDMX
:
10416 mips_opts
.ase_mdmx
= 0;
10419 case OPTION_MIPS16
:
10420 mips_opts
.mips16
= 1;
10421 mips_no_prev_insn (FALSE
);
10424 case OPTION_NO_MIPS16
:
10425 mips_opts
.mips16
= 0;
10426 mips_no_prev_insn (FALSE
);
10429 case OPTION_MIPS3D
:
10430 mips_opts
.ase_mips3d
= 1;
10433 case OPTION_NO_MIPS3D
:
10434 mips_opts
.ase_mips3d
= 0;
10437 case OPTION_FIX_VR4120
:
10438 mips_fix_vr4120
= 1;
10441 case OPTION_NO_FIX_VR4120
:
10442 mips_fix_vr4120
= 0;
10445 case OPTION_RELAX_BRANCH
:
10446 mips_relax_branch
= 1;
10449 case OPTION_NO_RELAX_BRANCH
:
10450 mips_relax_branch
= 0;
10453 case OPTION_MSHARED
:
10454 mips_in_shared
= TRUE
;
10457 case OPTION_MNO_SHARED
:
10458 mips_in_shared
= FALSE
;
10461 case OPTION_MSYM32
:
10462 mips_opts
.sym32
= TRUE
;
10465 case OPTION_MNO_SYM32
:
10466 mips_opts
.sym32
= FALSE
;
10470 /* When generating ELF code, we permit -KPIC and -call_shared to
10471 select SVR4_PIC, and -non_shared to select no PIC. This is
10472 intended to be compatible with Irix 5. */
10473 case OPTION_CALL_SHARED
:
10474 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
10476 as_bad (_("-call_shared is supported only for ELF format"));
10479 mips_pic
= SVR4_PIC
;
10480 mips_abicalls
= TRUE
;
10481 if (g_switch_seen
&& g_switch_value
!= 0)
10483 as_bad (_("-G may not be used with SVR4 PIC code"));
10486 g_switch_value
= 0;
10489 case OPTION_NON_SHARED
:
10490 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
10492 as_bad (_("-non_shared is supported only for ELF format"));
10496 mips_abicalls
= FALSE
;
10499 /* The -xgot option tells the assembler to use 32 offsets when
10500 accessing the got in SVR4_PIC mode. It is for Irix
10505 #endif /* OBJ_ELF */
10508 g_switch_value
= atoi (arg
);
10510 if (mips_pic
== SVR4_PIC
&& g_switch_value
!= 0)
10512 as_bad (_("-G may not be used with SVR4 PIC code"));
10518 /* The -32, -n32 and -64 options are shortcuts for -mabi=32, -mabi=n32
10521 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
10523 as_bad (_("-32 is supported for ELF format only"));
10526 mips_abi
= O32_ABI
;
10530 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
10532 as_bad (_("-n32 is supported for ELF format only"));
10535 mips_abi
= N32_ABI
;
10539 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
10541 as_bad (_("-64 is supported for ELF format only"));
10544 mips_abi
= N64_ABI
;
10545 if (! support_64bit_objects())
10546 as_fatal (_("No compiled in support for 64 bit object file format"));
10548 #endif /* OBJ_ELF */
10551 file_mips_gp32
= 1;
10555 file_mips_gp32
= 0;
10559 file_mips_fp32
= 1;
10563 file_mips_fp32
= 0;
10568 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
10570 as_bad (_("-mabi is supported for ELF format only"));
10573 if (strcmp (arg
, "32") == 0)
10574 mips_abi
= O32_ABI
;
10575 else if (strcmp (arg
, "o64") == 0)
10576 mips_abi
= O64_ABI
;
10577 else if (strcmp (arg
, "n32") == 0)
10578 mips_abi
= N32_ABI
;
10579 else if (strcmp (arg
, "64") == 0)
10581 mips_abi
= N64_ABI
;
10582 if (! support_64bit_objects())
10583 as_fatal (_("No compiled in support for 64 bit object file "
10586 else if (strcmp (arg
, "eabi") == 0)
10587 mips_abi
= EABI_ABI
;
10590 as_fatal (_("invalid abi -mabi=%s"), arg
);
10594 #endif /* OBJ_ELF */
10596 case OPTION_M7000_HILO_FIX
:
10597 mips_7000_hilo_fix
= TRUE
;
10600 case OPTION_MNO_7000_HILO_FIX
:
10601 mips_7000_hilo_fix
= FALSE
;
10605 case OPTION_MDEBUG
:
10606 mips_flag_mdebug
= TRUE
;
10609 case OPTION_NO_MDEBUG
:
10610 mips_flag_mdebug
= FALSE
;
10614 mips_flag_pdr
= TRUE
;
10617 case OPTION_NO_PDR
:
10618 mips_flag_pdr
= FALSE
;
10620 #endif /* OBJ_ELF */
10629 /* Set up globals to generate code for the ISA or processor
10630 described by INFO. */
10633 mips_set_architecture (const struct mips_cpu_info
*info
)
10637 file_mips_arch
= info
->cpu
;
10638 mips_opts
.arch
= info
->cpu
;
10639 mips_opts
.isa
= info
->isa
;
10644 /* Likewise for tuning. */
10647 mips_set_tune (const struct mips_cpu_info
*info
)
10650 mips_tune
= info
->cpu
;
10655 mips_after_parse_args (void)
10657 const struct mips_cpu_info
*arch_info
= 0;
10658 const struct mips_cpu_info
*tune_info
= 0;
10660 /* GP relative stuff not working for PE */
10661 if (strncmp (TARGET_OS
, "pe", 2) == 0)
10663 if (g_switch_seen
&& g_switch_value
!= 0)
10664 as_bad (_("-G not supported in this configuration."));
10665 g_switch_value
= 0;
10668 if (mips_abi
== NO_ABI
)
10669 mips_abi
= MIPS_DEFAULT_ABI
;
10671 /* The following code determines the architecture and register size.
10672 Similar code was added to GCC 3.3 (see override_options() in
10673 config/mips/mips.c). The GAS and GCC code should be kept in sync
10674 as much as possible. */
10676 if (mips_arch_string
!= 0)
10677 arch_info
= mips_parse_cpu ("-march", mips_arch_string
);
10679 if (file_mips_isa
!= ISA_UNKNOWN
)
10681 /* Handle -mipsN. At this point, file_mips_isa contains the
10682 ISA level specified by -mipsN, while arch_info->isa contains
10683 the -march selection (if any). */
10684 if (arch_info
!= 0)
10686 /* -march takes precedence over -mipsN, since it is more descriptive.
10687 There's no harm in specifying both as long as the ISA levels
10689 if (file_mips_isa
!= arch_info
->isa
)
10690 as_bad (_("-%s conflicts with the other architecture options, which imply -%s"),
10691 mips_cpu_info_from_isa (file_mips_isa
)->name
,
10692 mips_cpu_info_from_isa (arch_info
->isa
)->name
);
10695 arch_info
= mips_cpu_info_from_isa (file_mips_isa
);
10698 if (arch_info
== 0)
10699 arch_info
= mips_parse_cpu ("default CPU", MIPS_CPU_STRING_DEFAULT
);
10701 if (ABI_NEEDS_64BIT_REGS (mips_abi
) && !ISA_HAS_64BIT_REGS (arch_info
->isa
))
10702 as_bad ("-march=%s is not compatible with the selected ABI",
10705 mips_set_architecture (arch_info
);
10707 /* Optimize for file_mips_arch, unless -mtune selects a different processor. */
10708 if (mips_tune_string
!= 0)
10709 tune_info
= mips_parse_cpu ("-mtune", mips_tune_string
);
10711 if (tune_info
== 0)
10712 mips_set_tune (arch_info
);
10714 mips_set_tune (tune_info
);
10716 if (file_mips_gp32
>= 0)
10718 /* The user specified the size of the integer registers. Make sure
10719 it agrees with the ABI and ISA. */
10720 if (file_mips_gp32
== 0 && !ISA_HAS_64BIT_REGS (mips_opts
.isa
))
10721 as_bad (_("-mgp64 used with a 32-bit processor"));
10722 else if (file_mips_gp32
== 1 && ABI_NEEDS_64BIT_REGS (mips_abi
))
10723 as_bad (_("-mgp32 used with a 64-bit ABI"));
10724 else if (file_mips_gp32
== 0 && ABI_NEEDS_32BIT_REGS (mips_abi
))
10725 as_bad (_("-mgp64 used with a 32-bit ABI"));
10729 /* Infer the integer register size from the ABI and processor.
10730 Restrict ourselves to 32-bit registers if that's all the
10731 processor has, or if the ABI cannot handle 64-bit registers. */
10732 file_mips_gp32
= (ABI_NEEDS_32BIT_REGS (mips_abi
)
10733 || !ISA_HAS_64BIT_REGS (mips_opts
.isa
));
10736 /* ??? GAS treats single-float processors as though they had 64-bit
10737 float registers (although it complains when double-precision
10738 instructions are used). As things stand, saying they have 32-bit
10739 registers would lead to spurious "register must be even" messages.
10740 So here we assume float registers are always the same size as
10741 integer ones, unless the user says otherwise. */
10742 if (file_mips_fp32
< 0)
10743 file_mips_fp32
= file_mips_gp32
;
10745 /* End of GCC-shared inference code. */
10747 /* This flag is set when we have a 64-bit capable CPU but use only
10748 32-bit wide registers. Note that EABI does not use it. */
10749 if (ISA_HAS_64BIT_REGS (mips_opts
.isa
)
10750 && ((mips_abi
== NO_ABI
&& file_mips_gp32
== 1)
10751 || mips_abi
== O32_ABI
))
10752 mips_32bitmode
= 1;
10754 if (mips_opts
.isa
== ISA_MIPS1
&& mips_trap
)
10755 as_bad (_("trap exception not supported at ISA 1"));
10757 /* If the selected architecture includes support for ASEs, enable
10758 generation of code for them. */
10759 if (mips_opts
.mips16
== -1)
10760 mips_opts
.mips16
= (CPU_HAS_MIPS16 (file_mips_arch
)) ? 1 : 0;
10761 if (mips_opts
.ase_mips3d
== -1)
10762 mips_opts
.ase_mips3d
= (CPU_HAS_MIPS3D (file_mips_arch
)) ? 1 : 0;
10763 if (mips_opts
.ase_mdmx
== -1)
10764 mips_opts
.ase_mdmx
= (CPU_HAS_MDMX (file_mips_arch
)) ? 1 : 0;
10766 file_mips_isa
= mips_opts
.isa
;
10767 file_ase_mips16
= mips_opts
.mips16
;
10768 file_ase_mips3d
= mips_opts
.ase_mips3d
;
10769 file_ase_mdmx
= mips_opts
.ase_mdmx
;
10770 mips_opts
.gp32
= file_mips_gp32
;
10771 mips_opts
.fp32
= file_mips_fp32
;
10773 if (mips_flag_mdebug
< 0)
10775 #ifdef OBJ_MAYBE_ECOFF
10776 if (OUTPUT_FLAVOR
== bfd_target_ecoff_flavour
)
10777 mips_flag_mdebug
= 1;
10779 #endif /* OBJ_MAYBE_ECOFF */
10780 mips_flag_mdebug
= 0;
10785 mips_init_after_args (void)
10787 /* initialize opcodes */
10788 bfd_mips_num_opcodes
= bfd_mips_num_builtin_opcodes
;
10789 mips_opcodes
= (struct mips_opcode
*) mips_builtin_opcodes
;
10793 md_pcrel_from (fixS
*fixP
)
10795 valueT addr
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
10796 switch (fixP
->fx_r_type
)
10798 case BFD_RELOC_16_PCREL_S2
:
10799 case BFD_RELOC_MIPS_JMP
:
10800 /* Return the address of the delay slot. */
10807 /* This is called before the symbol table is processed. In order to
10808 work with gcc when using mips-tfile, we must keep all local labels.
10809 However, in other cases, we want to discard them. If we were
10810 called with -g, but we didn't see any debugging information, it may
10811 mean that gcc is smuggling debugging information through to
10812 mips-tfile, in which case we must generate all local labels. */
10815 mips_frob_file_before_adjust (void)
10817 #ifndef NO_ECOFF_DEBUGGING
10818 if (ECOFF_DEBUGGING
10820 && ! ecoff_debugging_seen
)
10821 flag_keep_locals
= 1;
10825 /* Sort any unmatched HI16 and GOT16 relocs so that they immediately precede
10826 the corresponding LO16 reloc. This is called before md_apply_fix3 and
10827 tc_gen_reloc. Unmatched relocs can only be generated by use of explicit
10828 relocation operators.
10830 For our purposes, a %lo() expression matches a %got() or %hi()
10833 (a) it refers to the same symbol; and
10834 (b) the offset applied in the %lo() expression is no lower than
10835 the offset applied in the %got() or %hi().
10837 (b) allows us to cope with code like:
10840 lh $4,%lo(foo+2)($4)
10842 ...which is legal on RELA targets, and has a well-defined behaviour
10843 if the user knows that adding 2 to "foo" will not induce a carry to
10846 When several %lo()s match a particular %got() or %hi(), we use the
10847 following rules to distinguish them:
10849 (1) %lo()s with smaller offsets are a better match than %lo()s with
10852 (2) %lo()s with no matching %got() or %hi() are better than those
10853 that already have a matching %got() or %hi().
10855 (3) later %lo()s are better than earlier %lo()s.
10857 These rules are applied in order.
10859 (1) means, among other things, that %lo()s with identical offsets are
10860 chosen if they exist.
10862 (2) means that we won't associate several high-part relocations with
10863 the same low-part relocation unless there's no alternative. Having
10864 several high parts for the same low part is a GNU extension; this rule
10865 allows careful users to avoid it.
10867 (3) is purely cosmetic. mips_hi_fixup_list is is in reverse order,
10868 with the last high-part relocation being at the front of the list.
10869 It therefore makes sense to choose the last matching low-part
10870 relocation, all other things being equal. It's also easier
10871 to code that way. */
10874 mips_frob_file (void)
10876 struct mips_hi_fixup
*l
;
10878 for (l
= mips_hi_fixup_list
; l
!= NULL
; l
= l
->next
)
10880 segment_info_type
*seginfo
;
10881 bfd_boolean matched_lo_p
;
10882 fixS
**hi_pos
, **lo_pos
, **pos
;
10884 assert (reloc_needs_lo_p (l
->fixp
->fx_r_type
));
10886 /* If a GOT16 relocation turns out to be against a global symbol,
10887 there isn't supposed to be a matching LO. */
10888 if (l
->fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT16
10889 && !pic_need_relax (l
->fixp
->fx_addsy
, l
->seg
))
10892 /* Check quickly whether the next fixup happens to be a matching %lo. */
10893 if (fixup_has_matching_lo_p (l
->fixp
))
10896 seginfo
= seg_info (l
->seg
);
10898 /* Set HI_POS to the position of this relocation in the chain.
10899 Set LO_POS to the position of the chosen low-part relocation.
10900 MATCHED_LO_P is true on entry to the loop if *POS is a low-part
10901 relocation that matches an immediately-preceding high-part
10905 matched_lo_p
= FALSE
;
10906 for (pos
= &seginfo
->fix_root
; *pos
!= NULL
; pos
= &(*pos
)->fx_next
)
10908 if (*pos
== l
->fixp
)
10911 if ((*pos
)->fx_r_type
== BFD_RELOC_LO16
10912 && (*pos
)->fx_addsy
== l
->fixp
->fx_addsy
10913 && (*pos
)->fx_offset
>= l
->fixp
->fx_offset
10915 || (*pos
)->fx_offset
< (*lo_pos
)->fx_offset
10917 && (*pos
)->fx_offset
== (*lo_pos
)->fx_offset
)))
10920 matched_lo_p
= (reloc_needs_lo_p ((*pos
)->fx_r_type
)
10921 && fixup_has_matching_lo_p (*pos
));
10924 /* If we found a match, remove the high-part relocation from its
10925 current position and insert it before the low-part relocation.
10926 Make the offsets match so that fixup_has_matching_lo_p()
10929 We don't warn about unmatched high-part relocations since some
10930 versions of gcc have been known to emit dead "lui ...%hi(...)"
10932 if (lo_pos
!= NULL
)
10934 l
->fixp
->fx_offset
= (*lo_pos
)->fx_offset
;
10935 if (l
->fixp
->fx_next
!= *lo_pos
)
10937 *hi_pos
= l
->fixp
->fx_next
;
10938 l
->fixp
->fx_next
= *lo_pos
;
10945 /* We may have combined relocations without symbols in the N32/N64 ABI.
10946 We have to prevent gas from dropping them. */
10949 mips_force_relocation (fixS
*fixp
)
10951 if (generic_force_reloc (fixp
))
10955 && S_GET_SEGMENT (fixp
->fx_addsy
) == bfd_abs_section_ptr
10956 && (fixp
->fx_r_type
== BFD_RELOC_MIPS_SUB
10957 || fixp
->fx_r_type
== BFD_RELOC_HI16_S
10958 || fixp
->fx_r_type
== BFD_RELOC_LO16
))
10964 /* This hook is called before a fix is simplified. We don't really
10965 decide whether to skip a fix here. Rather, we turn global symbols
10966 used as branch targets into local symbols, such that they undergo
10967 simplification. We can only do this if the symbol is defined and
10968 it is in the same section as the branch. If this doesn't hold, we
10969 emit a better error message than just saying the relocation is not
10970 valid for the selected object format.
10972 FIXP is the fix-up we're going to try to simplify, SEG is the
10973 segment in which the fix up occurs. The return value should be
10974 non-zero to indicate the fix-up is valid for further
10975 simplifications. */
10978 mips_validate_fix (struct fix
*fixP
, asection
*seg
)
10980 /* There's a lot of discussion on whether it should be possible to
10981 use R_MIPS_PC16 to represent branch relocations. The outcome
10982 seems to be that it can, but gas/bfd are very broken in creating
10983 RELA relocations for this, so for now we only accept branches to
10984 symbols in the same section. Anything else is of dubious value,
10985 since there's no guarantee that at link time the symbol would be
10986 in range. Even for branches to local symbols this is arguably
10987 wrong, since it we assume the symbol is not going to be
10988 overridden, which should be possible per ELF library semantics,
10989 but then, there isn't a dynamic relocation that could be used to
10990 this effect, and the target would likely be out of range as well.
10992 Unfortunately, it seems that there is too much code out there
10993 that relies on branches to symbols that are global to be resolved
10994 as if they were local, like the IRIX tools do, so we do it as
10995 well, but with a warning so that people are reminded to fix their
10996 code. If we ever get back to using R_MIPS_PC16 for branch
10997 targets, this entire block should go away (and probably the
10998 whole function). */
11000 if (fixP
->fx_r_type
== BFD_RELOC_16_PCREL_S2
11001 && ((OUTPUT_FLAVOR
== bfd_target_ecoff_flavour
11002 || OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
11003 || bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_16_PCREL_S2
) == NULL
)
11006 if (! S_IS_DEFINED (fixP
->fx_addsy
))
11008 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
11009 _("Cannot branch to undefined symbol."));
11010 /* Avoid any further errors about this fixup. */
11013 else if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
11015 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
11016 _("Cannot branch to symbol in another section."));
11019 else if (S_IS_EXTERNAL (fixP
->fx_addsy
))
11021 symbolS
*sym
= fixP
->fx_addsy
;
11023 if (mips_pic
== SVR4_PIC
)
11024 as_warn_where (fixP
->fx_file
, fixP
->fx_line
,
11025 _("Pretending global symbol used as branch target is local."));
11027 fixP
->fx_addsy
= symbol_create (S_GET_NAME (sym
),
11028 S_GET_SEGMENT (sym
),
11030 symbol_get_frag (sym
));
11031 copy_symbol_attributes (fixP
->fx_addsy
, sym
);
11032 S_CLEAR_EXTERNAL (fixP
->fx_addsy
);
11033 assert (symbol_resolved_p (sym
));
11034 symbol_mark_resolved (fixP
->fx_addsy
);
11041 /* Apply a fixup to the object file. */
11044 md_apply_fix3 (fixS
*fixP
, valueT
*valP
, segT seg ATTRIBUTE_UNUSED
)
11048 reloc_howto_type
*howto
;
11050 /* We ignore generic BFD relocations we don't know about. */
11051 howto
= bfd_reloc_type_lookup (stdoutput
, fixP
->fx_r_type
);
11055 assert (fixP
->fx_size
== 4
11056 || fixP
->fx_r_type
== BFD_RELOC_16
11057 || fixP
->fx_r_type
== BFD_RELOC_64
11058 || fixP
->fx_r_type
== BFD_RELOC_CTOR
11059 || fixP
->fx_r_type
== BFD_RELOC_MIPS_SUB
11060 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
11061 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
);
11063 buf
= (bfd_byte
*) (fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
);
11065 assert (! fixP
->fx_pcrel
);
11067 /* Don't treat parts of a composite relocation as done. There are two
11070 (1) The second and third parts will be against 0 (RSS_UNDEF) but
11071 should nevertheless be emitted if the first part is.
11073 (2) In normal usage, composite relocations are never assembly-time
11074 constants. The easiest way of dealing with the pathological
11075 exceptions is to generate a relocation against STN_UNDEF and
11076 leave everything up to the linker. */
11077 if (fixP
->fx_addsy
== NULL
&& fixP
->fx_tcbit
== 0)
11080 switch (fixP
->fx_r_type
)
11082 case BFD_RELOC_MIPS_TLS_GD
:
11083 case BFD_RELOC_MIPS_TLS_LDM
:
11084 case BFD_RELOC_MIPS_TLS_DTPREL_HI16
:
11085 case BFD_RELOC_MIPS_TLS_DTPREL_LO16
:
11086 case BFD_RELOC_MIPS_TLS_GOTTPREL
:
11087 case BFD_RELOC_MIPS_TLS_TPREL_HI16
:
11088 case BFD_RELOC_MIPS_TLS_TPREL_LO16
:
11089 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
11092 case BFD_RELOC_MIPS_JMP
:
11093 case BFD_RELOC_MIPS_SHIFT5
:
11094 case BFD_RELOC_MIPS_SHIFT6
:
11095 case BFD_RELOC_MIPS_GOT_DISP
:
11096 case BFD_RELOC_MIPS_GOT_PAGE
:
11097 case BFD_RELOC_MIPS_GOT_OFST
:
11098 case BFD_RELOC_MIPS_SUB
:
11099 case BFD_RELOC_MIPS_INSERT_A
:
11100 case BFD_RELOC_MIPS_INSERT_B
:
11101 case BFD_RELOC_MIPS_DELETE
:
11102 case BFD_RELOC_MIPS_HIGHEST
:
11103 case BFD_RELOC_MIPS_HIGHER
:
11104 case BFD_RELOC_MIPS_SCN_DISP
:
11105 case BFD_RELOC_MIPS_REL16
:
11106 case BFD_RELOC_MIPS_RELGOT
:
11107 case BFD_RELOC_MIPS_JALR
:
11108 case BFD_RELOC_HI16
:
11109 case BFD_RELOC_HI16_S
:
11110 case BFD_RELOC_GPREL16
:
11111 case BFD_RELOC_MIPS_LITERAL
:
11112 case BFD_RELOC_MIPS_CALL16
:
11113 case BFD_RELOC_MIPS_GOT16
:
11114 case BFD_RELOC_GPREL32
:
11115 case BFD_RELOC_MIPS_GOT_HI16
:
11116 case BFD_RELOC_MIPS_GOT_LO16
:
11117 case BFD_RELOC_MIPS_CALL_HI16
:
11118 case BFD_RELOC_MIPS_CALL_LO16
:
11119 case BFD_RELOC_MIPS16_GPREL
:
11120 case BFD_RELOC_MIPS16_HI16
:
11121 case BFD_RELOC_MIPS16_HI16_S
:
11122 assert (! fixP
->fx_pcrel
);
11123 /* Nothing needed to do. The value comes from the reloc entry */
11126 case BFD_RELOC_MIPS16_JMP
:
11127 /* We currently always generate a reloc against a symbol, which
11128 means that we don't want an addend even if the symbol is
11134 /* This is handled like BFD_RELOC_32, but we output a sign
11135 extended value if we are only 32 bits. */
11138 if (8 <= sizeof (valueT
))
11139 md_number_to_chars ((char *) buf
, *valP
, 8);
11144 if ((*valP
& 0x80000000) != 0)
11148 md_number_to_chars ((char *)(buf
+ target_big_endian
? 4 : 0),
11150 md_number_to_chars ((char *)(buf
+ target_big_endian
? 0 : 4),
11156 case BFD_RELOC_RVA
:
11158 /* If we are deleting this reloc entry, we must fill in the
11159 value now. This can happen if we have a .word which is not
11160 resolved when it appears but is later defined. */
11162 md_number_to_chars ((char *) buf
, *valP
, 4);
11166 /* If we are deleting this reloc entry, we must fill in the
11169 md_number_to_chars ((char *) buf
, *valP
, 2);
11172 case BFD_RELOC_LO16
:
11173 case BFD_RELOC_MIPS16_LO16
:
11174 /* FIXME: Now that embedded-PIC is gone, some of this code/comment
11175 may be safe to remove, but if so it's not obvious. */
11176 /* When handling an embedded PIC switch statement, we can wind
11177 up deleting a LO16 reloc. See the 'o' case in mips_ip. */
11180 if (*valP
+ 0x8000 > 0xffff)
11181 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
11182 _("relocation overflow"));
11183 if (target_big_endian
)
11185 md_number_to_chars ((char *) buf
, *valP
, 2);
11189 case BFD_RELOC_16_PCREL_S2
:
11190 if ((*valP
& 0x3) != 0)
11191 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
11192 _("Branch to odd address (%lx)"), (long) *valP
);
11195 * We need to save the bits in the instruction since fixup_segment()
11196 * might be deleting the relocation entry (i.e., a branch within
11197 * the current segment).
11199 if (! fixP
->fx_done
)
11202 /* update old instruction data */
11203 if (target_big_endian
)
11204 insn
= (buf
[0] << 24) | (buf
[1] << 16) | (buf
[2] << 8) | buf
[3];
11206 insn
= (buf
[3] << 24) | (buf
[2] << 16) | (buf
[1] << 8) | buf
[0];
11208 if (*valP
+ 0x20000 <= 0x3ffff)
11210 insn
|= (*valP
>> 2) & 0xffff;
11211 md_number_to_chars ((char *) buf
, insn
, 4);
11213 else if (mips_pic
== NO_PIC
11215 && fixP
->fx_frag
->fr_address
>= text_section
->vma
11216 && (fixP
->fx_frag
->fr_address
11217 < text_section
->vma
+ bfd_get_section_size (text_section
))
11218 && ((insn
& 0xffff0000) == 0x10000000 /* beq $0,$0 */
11219 || (insn
& 0xffff0000) == 0x04010000 /* bgez $0 */
11220 || (insn
& 0xffff0000) == 0x04110000)) /* bgezal $0 */
11222 /* The branch offset is too large. If this is an
11223 unconditional branch, and we are not generating PIC code,
11224 we can convert it to an absolute jump instruction. */
11225 if ((insn
& 0xffff0000) == 0x04110000) /* bgezal $0 */
11226 insn
= 0x0c000000; /* jal */
11228 insn
= 0x08000000; /* j */
11229 fixP
->fx_r_type
= BFD_RELOC_MIPS_JMP
;
11231 fixP
->fx_addsy
= section_symbol (text_section
);
11232 *valP
+= md_pcrel_from (fixP
);
11233 md_number_to_chars ((char *) buf
, insn
, 4);
11237 /* If we got here, we have branch-relaxation disabled,
11238 and there's nothing we can do to fix this instruction
11239 without turning it into a longer sequence. */
11240 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
11241 _("Branch out of range"));
11245 case BFD_RELOC_VTABLE_INHERIT
:
11248 && !S_IS_DEFINED (fixP
->fx_addsy
)
11249 && !S_IS_WEAK (fixP
->fx_addsy
))
11250 S_SET_WEAK (fixP
->fx_addsy
);
11253 case BFD_RELOC_VTABLE_ENTRY
:
11261 /* Remember value for tc_gen_reloc. */
11262 fixP
->fx_addnumber
= *valP
;
11272 name
= input_line_pointer
;
11273 c
= get_symbol_end ();
11274 p
= (symbolS
*) symbol_find_or_make (name
);
11275 *input_line_pointer
= c
;
11279 /* Align the current frag to a given power of two. The MIPS assembler
11280 also automatically adjusts any preceding label. */
11283 mips_align (int to
, int fill
, symbolS
*label
)
11285 mips_emit_delays (FALSE
);
11286 frag_align (to
, fill
, 0);
11287 record_alignment (now_seg
, to
);
11290 assert (S_GET_SEGMENT (label
) == now_seg
);
11291 symbol_set_frag (label
, frag_now
);
11292 S_SET_VALUE (label
, (valueT
) frag_now_fix ());
11296 /* Align to a given power of two. .align 0 turns off the automatic
11297 alignment used by the data creating pseudo-ops. */
11300 s_align (int x ATTRIBUTE_UNUSED
)
11303 register long temp_fill
;
11304 long max_alignment
= 15;
11308 o Note that the assembler pulls down any immediately preceding label
11309 to the aligned address.
11310 o It's not documented but auto alignment is reinstated by
11311 a .align pseudo instruction.
11312 o Note also that after auto alignment is turned off the mips assembler
11313 issues an error on attempt to assemble an improperly aligned data item.
11318 temp
= get_absolute_expression ();
11319 if (temp
> max_alignment
)
11320 as_bad (_("Alignment too large: %d. assumed."), temp
= max_alignment
);
11323 as_warn (_("Alignment negative: 0 assumed."));
11326 if (*input_line_pointer
== ',')
11328 ++input_line_pointer
;
11329 temp_fill
= get_absolute_expression ();
11336 mips_align (temp
, (int) temp_fill
,
11337 insn_labels
!= NULL
? insn_labels
->label
: NULL
);
11344 demand_empty_rest_of_line ();
11348 mips_flush_pending_output (void)
11350 mips_emit_delays (FALSE
);
11351 mips_clear_insn_labels ();
11355 s_change_sec (int sec
)
11360 /* The ELF backend needs to know that we are changing sections, so
11361 that .previous works correctly. We could do something like check
11362 for an obj_section_change_hook macro, but that might be confusing
11363 as it would not be appropriate to use it in the section changing
11364 functions in read.c, since obj-elf.c intercepts those. FIXME:
11365 This should be cleaner, somehow. */
11366 obj_elf_section_change_hook ();
11369 mips_emit_delays (FALSE
);
11379 subseg_set (bss_section
, (subsegT
) get_absolute_expression ());
11380 demand_empty_rest_of_line ();
11384 seg
= subseg_new (RDATA_SECTION_NAME
,
11385 (subsegT
) get_absolute_expression ());
11386 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
11388 bfd_set_section_flags (stdoutput
, seg
, (SEC_ALLOC
| SEC_LOAD
11389 | SEC_READONLY
| SEC_RELOC
11391 if (strcmp (TARGET_OS
, "elf") != 0)
11392 record_alignment (seg
, 4);
11394 demand_empty_rest_of_line ();
11398 seg
= subseg_new (".sdata", (subsegT
) get_absolute_expression ());
11399 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
11401 bfd_set_section_flags (stdoutput
, seg
,
11402 SEC_ALLOC
| SEC_LOAD
| SEC_RELOC
| SEC_DATA
);
11403 if (strcmp (TARGET_OS
, "elf") != 0)
11404 record_alignment (seg
, 4);
11406 demand_empty_rest_of_line ();
11414 s_change_section (int ignore ATTRIBUTE_UNUSED
)
11417 char *section_name
;
11422 int section_entry_size
;
11423 int section_alignment
;
11425 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
11428 section_name
= input_line_pointer
;
11429 c
= get_symbol_end ();
11431 next_c
= *(input_line_pointer
+ 1);
11433 /* Do we have .section Name<,"flags">? */
11434 if (c
!= ',' || (c
== ',' && next_c
== '"'))
11436 /* just after name is now '\0'. */
11437 *input_line_pointer
= c
;
11438 input_line_pointer
= section_name
;
11439 obj_elf_section (ignore
);
11442 input_line_pointer
++;
11444 /* Do we have .section Name<,type><,flag><,entry_size><,alignment> */
11446 section_type
= get_absolute_expression ();
11449 if (*input_line_pointer
++ == ',')
11450 section_flag
= get_absolute_expression ();
11453 if (*input_line_pointer
++ == ',')
11454 section_entry_size
= get_absolute_expression ();
11456 section_entry_size
= 0;
11457 if (*input_line_pointer
++ == ',')
11458 section_alignment
= get_absolute_expression ();
11460 section_alignment
= 0;
11462 section_name
= xstrdup (section_name
);
11464 /* When using the generic form of .section (as implemented by obj-elf.c),
11465 there's no way to set the section type to SHT_MIPS_DWARF. Users have
11466 traditionally had to fall back on the more common @progbits instead.
11468 There's nothing really harmful in this, since bfd will correct
11469 SHT_PROGBITS to SHT_MIPS_DWARF before writing out the file. But it
11470 means that, for backwards compatibiltiy, the special_section entries
11471 for dwarf sections must use SHT_PROGBITS rather than SHT_MIPS_DWARF.
11473 Even so, we shouldn't force users of the MIPS .section syntax to
11474 incorrectly label the sections as SHT_PROGBITS. The best compromise
11475 seems to be to map SHT_MIPS_DWARF to SHT_PROGBITS before calling the
11476 generic type-checking code. */
11477 if (section_type
== SHT_MIPS_DWARF
)
11478 section_type
= SHT_PROGBITS
;
11480 obj_elf_change_section (section_name
, section_type
, section_flag
,
11481 section_entry_size
, 0, 0, 0);
11483 if (now_seg
->name
!= section_name
)
11484 free (section_name
);
11485 #endif /* OBJ_ELF */
11489 mips_enable_auto_align (void)
11495 s_cons (int log_size
)
11499 label
= insn_labels
!= NULL
? insn_labels
->label
: NULL
;
11500 mips_emit_delays (FALSE
);
11501 if (log_size
> 0 && auto_align
)
11502 mips_align (log_size
, 0, label
);
11503 mips_clear_insn_labels ();
11504 cons (1 << log_size
);
11508 s_float_cons (int type
)
11512 label
= insn_labels
!= NULL
? insn_labels
->label
: NULL
;
11514 mips_emit_delays (FALSE
);
11519 mips_align (3, 0, label
);
11521 mips_align (2, 0, label
);
11524 mips_clear_insn_labels ();
11529 /* Handle .globl. We need to override it because on Irix 5 you are
11532 where foo is an undefined symbol, to mean that foo should be
11533 considered to be the address of a function. */
11536 s_mips_globl (int x ATTRIBUTE_UNUSED
)
11543 name
= input_line_pointer
;
11544 c
= get_symbol_end ();
11545 symbolP
= symbol_find_or_make (name
);
11546 *input_line_pointer
= c
;
11547 SKIP_WHITESPACE ();
11549 /* On Irix 5, every global symbol that is not explicitly labelled as
11550 being a function is apparently labelled as being an object. */
11553 if (! is_end_of_line
[(unsigned char) *input_line_pointer
])
11558 secname
= input_line_pointer
;
11559 c
= get_symbol_end ();
11560 sec
= bfd_get_section_by_name (stdoutput
, secname
);
11562 as_bad (_("%s: no such section"), secname
);
11563 *input_line_pointer
= c
;
11565 if (sec
!= NULL
&& (sec
->flags
& SEC_CODE
) != 0)
11566 flag
= BSF_FUNCTION
;
11569 symbol_get_bfdsym (symbolP
)->flags
|= flag
;
11571 S_SET_EXTERNAL (symbolP
);
11572 demand_empty_rest_of_line ();
11576 s_option (int x ATTRIBUTE_UNUSED
)
11581 opt
= input_line_pointer
;
11582 c
= get_symbol_end ();
11586 /* FIXME: What does this mean? */
11588 else if (strncmp (opt
, "pic", 3) == 0)
11592 i
= atoi (opt
+ 3);
11597 mips_pic
= SVR4_PIC
;
11598 mips_abicalls
= TRUE
;
11601 as_bad (_(".option pic%d not supported"), i
);
11603 if (mips_pic
== SVR4_PIC
)
11605 if (g_switch_seen
&& g_switch_value
!= 0)
11606 as_warn (_("-G may not be used with SVR4 PIC code"));
11607 g_switch_value
= 0;
11608 bfd_set_gp_size (stdoutput
, 0);
11612 as_warn (_("Unrecognized option \"%s\""), opt
);
11614 *input_line_pointer
= c
;
11615 demand_empty_rest_of_line ();
11618 /* This structure is used to hold a stack of .set values. */
11620 struct mips_option_stack
11622 struct mips_option_stack
*next
;
11623 struct mips_set_options options
;
11626 static struct mips_option_stack
*mips_opts_stack
;
11628 /* Handle the .set pseudo-op. */
11631 s_mipsset (int x ATTRIBUTE_UNUSED
)
11633 char *name
= input_line_pointer
, ch
;
11635 while (!is_end_of_line
[(unsigned char) *input_line_pointer
])
11636 ++input_line_pointer
;
11637 ch
= *input_line_pointer
;
11638 *input_line_pointer
= '\0';
11640 if (strcmp (name
, "reorder") == 0)
11642 if (mips_opts
.noreorder
&& prev_nop_frag
!= NULL
)
11644 /* If we still have pending nops, we can discard them. The
11645 usual nop handling will insert any that are still
11647 prev_nop_frag
->fr_fix
-= (prev_nop_frag_holds
11648 * (mips_opts
.mips16
? 2 : 4));
11649 prev_nop_frag
= NULL
;
11651 mips_opts
.noreorder
= 0;
11653 else if (strcmp (name
, "noreorder") == 0)
11655 mips_emit_delays (TRUE
);
11656 mips_opts
.noreorder
= 1;
11657 mips_any_noreorder
= 1;
11659 else if (strcmp (name
, "at") == 0)
11661 mips_opts
.noat
= 0;
11663 else if (strcmp (name
, "noat") == 0)
11665 mips_opts
.noat
= 1;
11667 else if (strcmp (name
, "macro") == 0)
11669 mips_opts
.warn_about_macros
= 0;
11671 else if (strcmp (name
, "nomacro") == 0)
11673 if (mips_opts
.noreorder
== 0)
11674 as_bad (_("`noreorder' must be set before `nomacro'"));
11675 mips_opts
.warn_about_macros
= 1;
11677 else if (strcmp (name
, "move") == 0 || strcmp (name
, "novolatile") == 0)
11679 mips_opts
.nomove
= 0;
11681 else if (strcmp (name
, "nomove") == 0 || strcmp (name
, "volatile") == 0)
11683 mips_opts
.nomove
= 1;
11685 else if (strcmp (name
, "bopt") == 0)
11687 mips_opts
.nobopt
= 0;
11689 else if (strcmp (name
, "nobopt") == 0)
11691 mips_opts
.nobopt
= 1;
11693 else if (strcmp (name
, "mips16") == 0
11694 || strcmp (name
, "MIPS-16") == 0)
11695 mips_opts
.mips16
= 1;
11696 else if (strcmp (name
, "nomips16") == 0
11697 || strcmp (name
, "noMIPS-16") == 0)
11698 mips_opts
.mips16
= 0;
11699 else if (strcmp (name
, "mips3d") == 0)
11700 mips_opts
.ase_mips3d
= 1;
11701 else if (strcmp (name
, "nomips3d") == 0)
11702 mips_opts
.ase_mips3d
= 0;
11703 else if (strcmp (name
, "mdmx") == 0)
11704 mips_opts
.ase_mdmx
= 1;
11705 else if (strcmp (name
, "nomdmx") == 0)
11706 mips_opts
.ase_mdmx
= 0;
11707 else if (strncmp (name
, "mips", 4) == 0 || strncmp (name
, "arch=", 5) == 0)
11711 /* Permit the user to change the ISA and architecture on the fly.
11712 Needless to say, misuse can cause serious problems. */
11713 if (strcmp (name
, "mips0") == 0 || strcmp (name
, "arch=default") == 0)
11716 mips_opts
.isa
= file_mips_isa
;
11717 mips_opts
.arch
= file_mips_arch
;
11719 else if (strncmp (name
, "arch=", 5) == 0)
11721 const struct mips_cpu_info
*p
;
11723 p
= mips_parse_cpu("internal use", name
+ 5);
11725 as_bad (_("unknown architecture %s"), name
+ 5);
11728 mips_opts
.arch
= p
->cpu
;
11729 mips_opts
.isa
= p
->isa
;
11732 else if (strncmp (name
, "mips", 4) == 0)
11734 const struct mips_cpu_info
*p
;
11736 p
= mips_parse_cpu("internal use", name
);
11738 as_bad (_("unknown ISA level %s"), name
+ 4);
11741 mips_opts
.arch
= p
->cpu
;
11742 mips_opts
.isa
= p
->isa
;
11746 as_bad (_("unknown ISA or architecture %s"), name
);
11748 switch (mips_opts
.isa
)
11756 mips_opts
.gp32
= 1;
11757 mips_opts
.fp32
= 1;
11764 mips_opts
.gp32
= 0;
11765 mips_opts
.fp32
= 0;
11768 as_bad (_("unknown ISA level %s"), name
+ 4);
11773 mips_opts
.gp32
= file_mips_gp32
;
11774 mips_opts
.fp32
= file_mips_fp32
;
11777 else if (strcmp (name
, "autoextend") == 0)
11778 mips_opts
.noautoextend
= 0;
11779 else if (strcmp (name
, "noautoextend") == 0)
11780 mips_opts
.noautoextend
= 1;
11781 else if (strcmp (name
, "push") == 0)
11783 struct mips_option_stack
*s
;
11785 s
= (struct mips_option_stack
*) xmalloc (sizeof *s
);
11786 s
->next
= mips_opts_stack
;
11787 s
->options
= mips_opts
;
11788 mips_opts_stack
= s
;
11790 else if (strcmp (name
, "pop") == 0)
11792 struct mips_option_stack
*s
;
11794 s
= mips_opts_stack
;
11796 as_bad (_(".set pop with no .set push"));
11799 /* If we're changing the reorder mode we need to handle
11800 delay slots correctly. */
11801 if (s
->options
.noreorder
&& ! mips_opts
.noreorder
)
11802 mips_emit_delays (TRUE
);
11803 else if (! s
->options
.noreorder
&& mips_opts
.noreorder
)
11805 if (prev_nop_frag
!= NULL
)
11807 prev_nop_frag
->fr_fix
-= (prev_nop_frag_holds
11808 * (mips_opts
.mips16
? 2 : 4));
11809 prev_nop_frag
= NULL
;
11813 mips_opts
= s
->options
;
11814 mips_opts_stack
= s
->next
;
11818 else if (strcmp (name
, "sym32") == 0)
11819 mips_opts
.sym32
= TRUE
;
11820 else if (strcmp (name
, "nosym32") == 0)
11821 mips_opts
.sym32
= FALSE
;
11824 as_warn (_("Tried to set unrecognized symbol: %s\n"), name
);
11826 *input_line_pointer
= ch
;
11827 demand_empty_rest_of_line ();
11830 /* Handle the .abicalls pseudo-op. I believe this is equivalent to
11831 .option pic2. It means to generate SVR4 PIC calls. */
11834 s_abicalls (int ignore ATTRIBUTE_UNUSED
)
11836 mips_pic
= SVR4_PIC
;
11837 mips_abicalls
= TRUE
;
11839 if (g_switch_seen
&& g_switch_value
!= 0)
11840 as_warn (_("-G may not be used with SVR4 PIC code"));
11841 g_switch_value
= 0;
11843 bfd_set_gp_size (stdoutput
, 0);
11844 demand_empty_rest_of_line ();
11847 /* Handle the .cpload pseudo-op. This is used when generating SVR4
11848 PIC code. It sets the $gp register for the function based on the
11849 function address, which is in the register named in the argument.
11850 This uses a relocation against _gp_disp, which is handled specially
11851 by the linker. The result is:
11852 lui $gp,%hi(_gp_disp)
11853 addiu $gp,$gp,%lo(_gp_disp)
11854 addu $gp,$gp,.cpload argument
11855 The .cpload argument is normally $25 == $t9.
11857 The -mno-shared option changes this to:
11858 lui $gp,%hi(__gnu_local_gp)
11859 addiu $gp,$gp,%lo(__gnu_local_gp)
11860 and the argument is ignored. This saves an instruction, but the
11861 resulting code is not position independent; it uses an absolute
11862 address for __gnu_local_gp. Thus code assembled with -mno-shared
11863 can go into an ordinary executable, but not into a shared library. */
11866 s_cpload (int ignore ATTRIBUTE_UNUSED
)
11872 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
11873 .cpload is ignored. */
11874 if (mips_pic
!= SVR4_PIC
|| HAVE_NEWABI
)
11880 /* .cpload should be in a .set noreorder section. */
11881 if (mips_opts
.noreorder
== 0)
11882 as_warn (_(".cpload not in noreorder section"));
11884 reg
= tc_get_register (0);
11886 /* If we need to produce a 64-bit address, we are better off using
11887 the default instruction sequence. */
11888 in_shared
= mips_in_shared
|| HAVE_64BIT_SYMBOLS
;
11890 ex
.X_op
= O_symbol
;
11891 ex
.X_add_symbol
= symbol_find_or_make (in_shared
? "_gp_disp" :
11893 ex
.X_op_symbol
= NULL
;
11894 ex
.X_add_number
= 0;
11896 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
11897 symbol_get_bfdsym (ex
.X_add_symbol
)->flags
|= BSF_OBJECT
;
11900 macro_build_lui (&ex
, mips_gp_register
);
11901 macro_build (&ex
, "addiu", "t,r,j", mips_gp_register
,
11902 mips_gp_register
, BFD_RELOC_LO16
);
11904 macro_build (NULL
, "addu", "d,v,t", mips_gp_register
,
11905 mips_gp_register
, reg
);
11908 demand_empty_rest_of_line ();
11911 /* Handle the .cpsetup pseudo-op defined for NewABI PIC code. The syntax is:
11912 .cpsetup $reg1, offset|$reg2, label
11914 If offset is given, this results in:
11915 sd $gp, offset($sp)
11916 lui $gp, %hi(%neg(%gp_rel(label)))
11917 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
11918 daddu $gp, $gp, $reg1
11920 If $reg2 is given, this results in:
11921 daddu $reg2, $gp, $0
11922 lui $gp, %hi(%neg(%gp_rel(label)))
11923 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
11924 daddu $gp, $gp, $reg1
11925 $reg1 is normally $25 == $t9.
11927 The -mno-shared option replaces the last three instructions with
11929 addiu $gp,$gp,%lo(_gp)
11933 s_cpsetup (int ignore ATTRIBUTE_UNUSED
)
11935 expressionS ex_off
;
11936 expressionS ex_sym
;
11939 /* If we are not generating SVR4 PIC code, .cpsetup is ignored.
11940 We also need NewABI support. */
11941 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
11947 reg1
= tc_get_register (0);
11948 SKIP_WHITESPACE ();
11949 if (*input_line_pointer
!= ',')
11951 as_bad (_("missing argument separator ',' for .cpsetup"));
11955 ++input_line_pointer
;
11956 SKIP_WHITESPACE ();
11957 if (*input_line_pointer
== '$')
11959 mips_cpreturn_register
= tc_get_register (0);
11960 mips_cpreturn_offset
= -1;
11964 mips_cpreturn_offset
= get_absolute_expression ();
11965 mips_cpreturn_register
= -1;
11967 SKIP_WHITESPACE ();
11968 if (*input_line_pointer
!= ',')
11970 as_bad (_("missing argument separator ',' for .cpsetup"));
11974 ++input_line_pointer
;
11975 SKIP_WHITESPACE ();
11976 expression (&ex_sym
);
11979 if (mips_cpreturn_register
== -1)
11981 ex_off
.X_op
= O_constant
;
11982 ex_off
.X_add_symbol
= NULL
;
11983 ex_off
.X_op_symbol
= NULL
;
11984 ex_off
.X_add_number
= mips_cpreturn_offset
;
11986 macro_build (&ex_off
, "sd", "t,o(b)", mips_gp_register
,
11987 BFD_RELOC_LO16
, SP
);
11990 macro_build (NULL
, "daddu", "d,v,t", mips_cpreturn_register
,
11991 mips_gp_register
, 0);
11993 if (mips_in_shared
|| HAVE_64BIT_SYMBOLS
)
11995 macro_build (&ex_sym
, "lui", "t,u", mips_gp_register
,
11996 -1, BFD_RELOC_GPREL16
, BFD_RELOC_MIPS_SUB
,
11999 macro_build (&ex_sym
, "addiu", "t,r,j", mips_gp_register
,
12000 mips_gp_register
, -1, BFD_RELOC_GPREL16
,
12001 BFD_RELOC_MIPS_SUB
, BFD_RELOC_LO16
);
12003 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", mips_gp_register
,
12004 mips_gp_register
, reg1
);
12010 ex
.X_op
= O_symbol
;
12011 ex
.X_add_symbol
= symbol_find_or_make ("_gp");
12012 ex
.X_op_symbol
= NULL
;
12013 ex
.X_add_number
= 0;
12015 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
12016 symbol_get_bfdsym (ex
.X_add_symbol
)->flags
|= BSF_OBJECT
;
12018 macro_build_lui (&ex
, mips_gp_register
);
12019 macro_build (&ex
, "addiu", "t,r,j", mips_gp_register
,
12020 mips_gp_register
, BFD_RELOC_LO16
);
12025 demand_empty_rest_of_line ();
12029 s_cplocal (int ignore ATTRIBUTE_UNUSED
)
12031 /* If we are not generating SVR4 PIC code, or if this is not NewABI code,
12032 .cplocal is ignored. */
12033 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
12039 mips_gp_register
= tc_get_register (0);
12040 demand_empty_rest_of_line ();
12043 /* Handle the .cprestore pseudo-op. This stores $gp into a given
12044 offset from $sp. The offset is remembered, and after making a PIC
12045 call $gp is restored from that location. */
12048 s_cprestore (int ignore ATTRIBUTE_UNUSED
)
12052 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
12053 .cprestore is ignored. */
12054 if (mips_pic
!= SVR4_PIC
|| HAVE_NEWABI
)
12060 mips_cprestore_offset
= get_absolute_expression ();
12061 mips_cprestore_valid
= 1;
12063 ex
.X_op
= O_constant
;
12064 ex
.X_add_symbol
= NULL
;
12065 ex
.X_op_symbol
= NULL
;
12066 ex
.X_add_number
= mips_cprestore_offset
;
12069 macro_build_ldst_constoffset (&ex
, ADDRESS_STORE_INSN
, mips_gp_register
,
12070 SP
, HAVE_64BIT_ADDRESSES
);
12073 demand_empty_rest_of_line ();
12076 /* Handle the .cpreturn pseudo-op defined for NewABI PIC code. If an offset
12077 was given in the preceding .cpsetup, it results in:
12078 ld $gp, offset($sp)
12080 If a register $reg2 was given there, it results in:
12081 daddu $gp, $reg2, $0
12084 s_cpreturn (int ignore ATTRIBUTE_UNUSED
)
12088 /* If we are not generating SVR4 PIC code, .cpreturn is ignored.
12089 We also need NewABI support. */
12090 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
12097 if (mips_cpreturn_register
== -1)
12099 ex
.X_op
= O_constant
;
12100 ex
.X_add_symbol
= NULL
;
12101 ex
.X_op_symbol
= NULL
;
12102 ex
.X_add_number
= mips_cpreturn_offset
;
12104 macro_build (&ex
, "ld", "t,o(b)", mips_gp_register
, BFD_RELOC_LO16
, SP
);
12107 macro_build (NULL
, "daddu", "d,v,t", mips_gp_register
,
12108 mips_cpreturn_register
, 0);
12111 demand_empty_rest_of_line ();
12114 /* Handle the .gpvalue pseudo-op. This is used when generating NewABI PIC
12115 code. It sets the offset to use in gp_rel relocations. */
12118 s_gpvalue (int ignore ATTRIBUTE_UNUSED
)
12120 /* If we are not generating SVR4 PIC code, .gpvalue is ignored.
12121 We also need NewABI support. */
12122 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
12128 mips_gprel_offset
= get_absolute_expression ();
12130 demand_empty_rest_of_line ();
12133 /* Handle the .gpword pseudo-op. This is used when generating PIC
12134 code. It generates a 32 bit GP relative reloc. */
12137 s_gpword (int ignore ATTRIBUTE_UNUSED
)
12143 /* When not generating PIC code, this is treated as .word. */
12144 if (mips_pic
!= SVR4_PIC
)
12150 label
= insn_labels
!= NULL
? insn_labels
->label
: NULL
;
12151 mips_emit_delays (TRUE
);
12153 mips_align (2, 0, label
);
12154 mips_clear_insn_labels ();
12158 if (ex
.X_op
!= O_symbol
|| ex
.X_add_number
!= 0)
12160 as_bad (_("Unsupported use of .gpword"));
12161 ignore_rest_of_line ();
12165 md_number_to_chars (p
, 0, 4);
12166 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 4, &ex
, FALSE
,
12167 BFD_RELOC_GPREL32
);
12169 demand_empty_rest_of_line ();
12173 s_gpdword (int ignore ATTRIBUTE_UNUSED
)
12179 /* When not generating PIC code, this is treated as .dword. */
12180 if (mips_pic
!= SVR4_PIC
)
12186 label
= insn_labels
!= NULL
? insn_labels
->label
: NULL
;
12187 mips_emit_delays (TRUE
);
12189 mips_align (3, 0, label
);
12190 mips_clear_insn_labels ();
12194 if (ex
.X_op
!= O_symbol
|| ex
.X_add_number
!= 0)
12196 as_bad (_("Unsupported use of .gpdword"));
12197 ignore_rest_of_line ();
12201 md_number_to_chars (p
, 0, 8);
12202 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 4, &ex
, FALSE
,
12203 BFD_RELOC_GPREL32
)->fx_tcbit
= 1;
12205 /* GPREL32 composed with 64 gives a 64-bit GP offset. */
12206 fix_new (frag_now
, p
- frag_now
->fr_literal
, 8, NULL
, 0,
12207 FALSE
, BFD_RELOC_64
)->fx_tcbit
= 1;
12209 demand_empty_rest_of_line ();
12212 /* Handle the .cpadd pseudo-op. This is used when dealing with switch
12213 tables in SVR4 PIC code. */
12216 s_cpadd (int ignore ATTRIBUTE_UNUSED
)
12220 /* This is ignored when not generating SVR4 PIC code. */
12221 if (mips_pic
!= SVR4_PIC
)
12227 /* Add $gp to the register named as an argument. */
12229 reg
= tc_get_register (0);
12230 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", reg
, reg
, mips_gp_register
);
12233 demand_empty_rest_of_line ();
12236 /* Handle the .insn pseudo-op. This marks instruction labels in
12237 mips16 mode. This permits the linker to handle them specially,
12238 such as generating jalx instructions when needed. We also make
12239 them odd for the duration of the assembly, in order to generate the
12240 right sort of code. We will make them even in the adjust_symtab
12241 routine, while leaving them marked. This is convenient for the
12242 debugger and the disassembler. The linker knows to make them odd
12246 s_insn (int ignore ATTRIBUTE_UNUSED
)
12248 mips16_mark_labels ();
12250 demand_empty_rest_of_line ();
12253 /* Handle a .stabn directive. We need these in order to mark a label
12254 as being a mips16 text label correctly. Sometimes the compiler
12255 will emit a label, followed by a .stabn, and then switch sections.
12256 If the label and .stabn are in mips16 mode, then the label is
12257 really a mips16 text label. */
12260 s_mips_stab (int type
)
12263 mips16_mark_labels ();
12268 /* Handle the .weakext pseudo-op as defined in Kane and Heinrich.
12272 s_mips_weakext (int ignore ATTRIBUTE_UNUSED
)
12279 name
= input_line_pointer
;
12280 c
= get_symbol_end ();
12281 symbolP
= symbol_find_or_make (name
);
12282 S_SET_WEAK (symbolP
);
12283 *input_line_pointer
= c
;
12285 SKIP_WHITESPACE ();
12287 if (! is_end_of_line
[(unsigned char) *input_line_pointer
])
12289 if (S_IS_DEFINED (symbolP
))
12291 as_bad ("ignoring attempt to redefine symbol %s",
12292 S_GET_NAME (symbolP
));
12293 ignore_rest_of_line ();
12297 if (*input_line_pointer
== ',')
12299 ++input_line_pointer
;
12300 SKIP_WHITESPACE ();
12304 if (exp
.X_op
!= O_symbol
)
12306 as_bad ("bad .weakext directive");
12307 ignore_rest_of_line ();
12310 symbol_set_value_expression (symbolP
, &exp
);
12313 demand_empty_rest_of_line ();
12316 /* Parse a register string into a number. Called from the ECOFF code
12317 to parse .frame. The argument is non-zero if this is the frame
12318 register, so that we can record it in mips_frame_reg. */
12321 tc_get_register (int frame
)
12325 SKIP_WHITESPACE ();
12326 if (*input_line_pointer
++ != '$')
12328 as_warn (_("expected `$'"));
12331 else if (ISDIGIT (*input_line_pointer
))
12333 reg
= get_absolute_expression ();
12334 if (reg
< 0 || reg
>= 32)
12336 as_warn (_("Bad register number"));
12342 if (strncmp (input_line_pointer
, "ra", 2) == 0)
12345 input_line_pointer
+= 2;
12347 else if (strncmp (input_line_pointer
, "fp", 2) == 0)
12350 input_line_pointer
+= 2;
12352 else if (strncmp (input_line_pointer
, "sp", 2) == 0)
12355 input_line_pointer
+= 2;
12357 else if (strncmp (input_line_pointer
, "gp", 2) == 0)
12360 input_line_pointer
+= 2;
12362 else if (strncmp (input_line_pointer
, "at", 2) == 0)
12365 input_line_pointer
+= 2;
12367 else if (strncmp (input_line_pointer
, "kt0", 3) == 0)
12370 input_line_pointer
+= 3;
12372 else if (strncmp (input_line_pointer
, "kt1", 3) == 0)
12375 input_line_pointer
+= 3;
12377 else if (strncmp (input_line_pointer
, "zero", 4) == 0)
12380 input_line_pointer
+= 4;
12384 as_warn (_("Unrecognized register name"));
12386 while (ISALNUM(*input_line_pointer
))
12387 input_line_pointer
++;
12392 mips_frame_reg
= reg
!= 0 ? reg
: SP
;
12393 mips_frame_reg_valid
= 1;
12394 mips_cprestore_valid
= 0;
12400 md_section_align (asection
*seg
, valueT addr
)
12402 int align
= bfd_get_section_alignment (stdoutput
, seg
);
12405 /* We don't need to align ELF sections to the full alignment.
12406 However, Irix 5 may prefer that we align them at least to a 16
12407 byte boundary. We don't bother to align the sections if we are
12408 targeted for an embedded system. */
12409 if (strcmp (TARGET_OS
, "elf") == 0)
12415 return ((addr
+ (1 << align
) - 1) & (-1 << align
));
12418 /* Utility routine, called from above as well. If called while the
12419 input file is still being read, it's only an approximation. (For
12420 example, a symbol may later become defined which appeared to be
12421 undefined earlier.) */
12424 nopic_need_relax (symbolS
*sym
, int before_relaxing
)
12429 if (g_switch_value
> 0)
12431 const char *symname
;
12434 /* Find out whether this symbol can be referenced off the $gp
12435 register. It can be if it is smaller than the -G size or if
12436 it is in the .sdata or .sbss section. Certain symbols can
12437 not be referenced off the $gp, although it appears as though
12439 symname
= S_GET_NAME (sym
);
12440 if (symname
!= (const char *) NULL
12441 && (strcmp (symname
, "eprol") == 0
12442 || strcmp (symname
, "etext") == 0
12443 || strcmp (symname
, "_gp") == 0
12444 || strcmp (symname
, "edata") == 0
12445 || strcmp (symname
, "_fbss") == 0
12446 || strcmp (symname
, "_fdata") == 0
12447 || strcmp (symname
, "_ftext") == 0
12448 || strcmp (symname
, "end") == 0
12449 || strcmp (symname
, "_gp_disp") == 0))
12451 else if ((! S_IS_DEFINED (sym
) || S_IS_COMMON (sym
))
12453 #ifndef NO_ECOFF_DEBUGGING
12454 || (symbol_get_obj (sym
)->ecoff_extern_size
!= 0
12455 && (symbol_get_obj (sym
)->ecoff_extern_size
12456 <= g_switch_value
))
12458 /* We must defer this decision until after the whole
12459 file has been read, since there might be a .extern
12460 after the first use of this symbol. */
12461 || (before_relaxing
12462 #ifndef NO_ECOFF_DEBUGGING
12463 && symbol_get_obj (sym
)->ecoff_extern_size
== 0
12465 && S_GET_VALUE (sym
) == 0)
12466 || (S_GET_VALUE (sym
) != 0
12467 && S_GET_VALUE (sym
) <= g_switch_value
)))
12471 const char *segname
;
12473 segname
= segment_name (S_GET_SEGMENT (sym
));
12474 assert (strcmp (segname
, ".lit8") != 0
12475 && strcmp (segname
, ".lit4") != 0);
12476 change
= (strcmp (segname
, ".sdata") != 0
12477 && strcmp (segname
, ".sbss") != 0
12478 && strncmp (segname
, ".sdata.", 7) != 0
12479 && strncmp (segname
, ".gnu.linkonce.s.", 16) != 0);
12484 /* We are not optimizing for the $gp register. */
12489 /* Return true if the given symbol should be considered local for SVR4 PIC. */
12492 pic_need_relax (symbolS
*sym
, asection
*segtype
)
12495 bfd_boolean linkonce
;
12497 /* Handle the case of a symbol equated to another symbol. */
12498 while (symbol_equated_reloc_p (sym
))
12502 /* It's possible to get a loop here in a badly written
12504 n
= symbol_get_value_expression (sym
)->X_add_symbol
;
12510 symsec
= S_GET_SEGMENT (sym
);
12512 /* duplicate the test for LINK_ONCE sections as in adjust_reloc_syms */
12514 if (symsec
!= segtype
&& ! S_IS_LOCAL (sym
))
12516 if ((bfd_get_section_flags (stdoutput
, symsec
) & SEC_LINK_ONCE
)
12520 /* The GNU toolchain uses an extension for ELF: a section
12521 beginning with the magic string .gnu.linkonce is a linkonce
12523 if (strncmp (segment_name (symsec
), ".gnu.linkonce",
12524 sizeof ".gnu.linkonce" - 1) == 0)
12528 /* This must duplicate the test in adjust_reloc_syms. */
12529 return (symsec
!= &bfd_und_section
12530 && symsec
!= &bfd_abs_section
12531 && ! bfd_is_com_section (symsec
)
12534 /* A global or weak symbol is treated as external. */
12535 && (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
12536 || (! S_IS_WEAK (sym
) && ! S_IS_EXTERNAL (sym
)))
12542 /* Given a mips16 variant frag FRAGP, return non-zero if it needs an
12543 extended opcode. SEC is the section the frag is in. */
12546 mips16_extended_frag (fragS
*fragp
, asection
*sec
, long stretch
)
12549 register const struct mips16_immed_operand
*op
;
12551 int mintiny
, maxtiny
;
12555 if (RELAX_MIPS16_USER_SMALL (fragp
->fr_subtype
))
12557 if (RELAX_MIPS16_USER_EXT (fragp
->fr_subtype
))
12560 type
= RELAX_MIPS16_TYPE (fragp
->fr_subtype
);
12561 op
= mips16_immed_operands
;
12562 while (op
->type
!= type
)
12565 assert (op
< mips16_immed_operands
+ MIPS16_NUM_IMMED
);
12570 if (type
== '<' || type
== '>' || type
== '[' || type
== ']')
12573 maxtiny
= 1 << op
->nbits
;
12578 maxtiny
= (1 << op
->nbits
) - 1;
12583 mintiny
= - (1 << (op
->nbits
- 1));
12584 maxtiny
= (1 << (op
->nbits
- 1)) - 1;
12587 sym_frag
= symbol_get_frag (fragp
->fr_symbol
);
12588 val
= S_GET_VALUE (fragp
->fr_symbol
);
12589 symsec
= S_GET_SEGMENT (fragp
->fr_symbol
);
12595 /* We won't have the section when we are called from
12596 mips_relax_frag. However, we will always have been called
12597 from md_estimate_size_before_relax first. If this is a
12598 branch to a different section, we mark it as such. If SEC is
12599 NULL, and the frag is not marked, then it must be a branch to
12600 the same section. */
12603 if (RELAX_MIPS16_LONG_BRANCH (fragp
->fr_subtype
))
12608 /* Must have been called from md_estimate_size_before_relax. */
12611 fragp
->fr_subtype
=
12612 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
12614 /* FIXME: We should support this, and let the linker
12615 catch branches and loads that are out of range. */
12616 as_bad_where (fragp
->fr_file
, fragp
->fr_line
,
12617 _("unsupported PC relative reference to different section"));
12621 if (fragp
!= sym_frag
&& sym_frag
->fr_address
== 0)
12622 /* Assume non-extended on the first relaxation pass.
12623 The address we have calculated will be bogus if this is
12624 a forward branch to another frag, as the forward frag
12625 will have fr_address == 0. */
12629 /* In this case, we know for sure that the symbol fragment is in
12630 the same section. If the relax_marker of the symbol fragment
12631 differs from the relax_marker of this fragment, we have not
12632 yet adjusted the symbol fragment fr_address. We want to add
12633 in STRETCH in order to get a better estimate of the address.
12634 This particularly matters because of the shift bits. */
12636 && sym_frag
->relax_marker
!= fragp
->relax_marker
)
12640 /* Adjust stretch for any alignment frag. Note that if have
12641 been expanding the earlier code, the symbol may be
12642 defined in what appears to be an earlier frag. FIXME:
12643 This doesn't handle the fr_subtype field, which specifies
12644 a maximum number of bytes to skip when doing an
12646 for (f
= fragp
; f
!= NULL
&& f
!= sym_frag
; f
= f
->fr_next
)
12648 if (f
->fr_type
== rs_align
|| f
->fr_type
== rs_align_code
)
12651 stretch
= - ((- stretch
)
12652 & ~ ((1 << (int) f
->fr_offset
) - 1));
12654 stretch
&= ~ ((1 << (int) f
->fr_offset
) - 1);
12663 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
12665 /* The base address rules are complicated. The base address of
12666 a branch is the following instruction. The base address of a
12667 PC relative load or add is the instruction itself, but if it
12668 is in a delay slot (in which case it can not be extended) use
12669 the address of the instruction whose delay slot it is in. */
12670 if (type
== 'p' || type
== 'q')
12674 /* If we are currently assuming that this frag should be
12675 extended, then, the current address is two bytes
12677 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
12680 /* Ignore the low bit in the target, since it will be set
12681 for a text label. */
12682 if ((val
& 1) != 0)
12685 else if (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
))
12687 else if (RELAX_MIPS16_DSLOT (fragp
->fr_subtype
))
12690 val
-= addr
& ~ ((1 << op
->shift
) - 1);
12692 /* Branch offsets have an implicit 0 in the lowest bit. */
12693 if (type
== 'p' || type
== 'q')
12696 /* If any of the shifted bits are set, we must use an extended
12697 opcode. If the address depends on the size of this
12698 instruction, this can lead to a loop, so we arrange to always
12699 use an extended opcode. We only check this when we are in
12700 the main relaxation loop, when SEC is NULL. */
12701 if ((val
& ((1 << op
->shift
) - 1)) != 0 && sec
== NULL
)
12703 fragp
->fr_subtype
=
12704 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
12708 /* If we are about to mark a frag as extended because the value
12709 is precisely maxtiny + 1, then there is a chance of an
12710 infinite loop as in the following code:
12715 In this case when the la is extended, foo is 0x3fc bytes
12716 away, so the la can be shrunk, but then foo is 0x400 away, so
12717 the la must be extended. To avoid this loop, we mark the
12718 frag as extended if it was small, and is about to become
12719 extended with a value of maxtiny + 1. */
12720 if (val
== ((maxtiny
+ 1) << op
->shift
)
12721 && ! RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
)
12724 fragp
->fr_subtype
=
12725 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
12729 else if (symsec
!= absolute_section
&& sec
!= NULL
)
12730 as_bad_where (fragp
->fr_file
, fragp
->fr_line
, _("unsupported relocation"));
12732 if ((val
& ((1 << op
->shift
) - 1)) != 0
12733 || val
< (mintiny
<< op
->shift
)
12734 || val
> (maxtiny
<< op
->shift
))
12740 /* Compute the length of a branch sequence, and adjust the
12741 RELAX_BRANCH_TOOFAR bit accordingly. If FRAGP is NULL, the
12742 worst-case length is computed, with UPDATE being used to indicate
12743 whether an unconditional (-1), branch-likely (+1) or regular (0)
12744 branch is to be computed. */
12746 relaxed_branch_length (fragS
*fragp
, asection
*sec
, int update
)
12748 bfd_boolean toofar
;
12752 && S_IS_DEFINED (fragp
->fr_symbol
)
12753 && sec
== S_GET_SEGMENT (fragp
->fr_symbol
))
12758 val
= S_GET_VALUE (fragp
->fr_symbol
) + fragp
->fr_offset
;
12760 addr
= fragp
->fr_address
+ fragp
->fr_fix
+ 4;
12764 toofar
= val
< - (0x8000 << 2) || val
>= (0x8000 << 2);
12767 /* If the symbol is not defined or it's in a different segment,
12768 assume the user knows what's going on and emit a short
12774 if (fragp
&& update
&& toofar
!= RELAX_BRANCH_TOOFAR (fragp
->fr_subtype
))
12776 = RELAX_BRANCH_ENCODE (RELAX_BRANCH_UNCOND (fragp
->fr_subtype
),
12777 RELAX_BRANCH_LIKELY (fragp
->fr_subtype
),
12778 RELAX_BRANCH_LINK (fragp
->fr_subtype
),
12784 if (fragp
? RELAX_BRANCH_LIKELY (fragp
->fr_subtype
) : (update
> 0))
12787 if (mips_pic
!= NO_PIC
)
12789 /* Additional space for PIC loading of target address. */
12791 if (mips_opts
.isa
== ISA_MIPS1
)
12792 /* Additional space for $at-stabilizing nop. */
12796 /* If branch is conditional. */
12797 if (fragp
? !RELAX_BRANCH_UNCOND (fragp
->fr_subtype
) : (update
>= 0))
12804 /* Estimate the size of a frag before relaxing. Unless this is the
12805 mips16, we are not really relaxing here, and the final size is
12806 encoded in the subtype information. For the mips16, we have to
12807 decide whether we are using an extended opcode or not. */
12810 md_estimate_size_before_relax (fragS
*fragp
, asection
*segtype
)
12814 if (RELAX_BRANCH_P (fragp
->fr_subtype
))
12817 fragp
->fr_var
= relaxed_branch_length (fragp
, segtype
, FALSE
);
12819 return fragp
->fr_var
;
12822 if (RELAX_MIPS16_P (fragp
->fr_subtype
))
12823 /* We don't want to modify the EXTENDED bit here; it might get us
12824 into infinite loops. We change it only in mips_relax_frag(). */
12825 return (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
) ? 4 : 2);
12827 if (mips_pic
== NO_PIC
)
12828 change
= nopic_need_relax (fragp
->fr_symbol
, 0);
12829 else if (mips_pic
== SVR4_PIC
)
12830 change
= pic_need_relax (fragp
->fr_symbol
, segtype
);
12836 fragp
->fr_subtype
|= RELAX_USE_SECOND
;
12837 return -RELAX_FIRST (fragp
->fr_subtype
);
12840 return -RELAX_SECOND (fragp
->fr_subtype
);
12843 /* This is called to see whether a reloc against a defined symbol
12844 should be converted into a reloc against a section. */
12847 mips_fix_adjustable (fixS
*fixp
)
12849 /* Don't adjust MIPS16 jump relocations, so we don't have to worry
12850 about the format of the offset in the .o file. */
12851 if (fixp
->fx_r_type
== BFD_RELOC_MIPS16_JMP
)
12854 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
12855 || fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
12858 if (fixp
->fx_addsy
== NULL
)
12861 /* If symbol SYM is in a mergeable section, relocations of the form
12862 SYM + 0 can usually be made section-relative. The mergeable data
12863 is then identified by the section offset rather than by the symbol.
12865 However, if we're generating REL LO16 relocations, the offset is split
12866 between the LO16 and parterning high part relocation. The linker will
12867 need to recalculate the complete offset in order to correctly identify
12870 The linker has traditionally not looked for the parterning high part
12871 relocation, and has thus allowed orphaned R_MIPS_LO16 relocations to be
12872 placed anywhere. Rather than break backwards compatibility by changing
12873 this, it seems better not to force the issue, and instead keep the
12874 original symbol. This will work with either linker behavior. */
12875 if ((fixp
->fx_r_type
== BFD_RELOC_LO16
|| reloc_needs_lo_p (fixp
->fx_r_type
))
12876 && HAVE_IN_PLACE_ADDENDS
12877 && (S_GET_SEGMENT (fixp
->fx_addsy
)->flags
& SEC_MERGE
) != 0)
12881 /* Don't adjust relocations against mips16 symbols, so that the linker
12882 can find them if it needs to set up a stub. */
12883 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
12884 && S_GET_OTHER (fixp
->fx_addsy
) == STO_MIPS16
12885 && fixp
->fx_subsy
== NULL
)
12892 /* Translate internal representation of relocation info to BFD target
12896 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
, fixS
*fixp
)
12898 static arelent
*retval
[4];
12900 bfd_reloc_code_real_type code
;
12902 memset (retval
, 0, sizeof(retval
));
12903 reloc
= retval
[0] = (arelent
*) xcalloc (1, sizeof (arelent
));
12904 reloc
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
12905 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
12906 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
12908 assert (! fixp
->fx_pcrel
);
12909 reloc
->addend
= fixp
->fx_addnumber
;
12911 /* Since the old MIPS ELF ABI uses Rel instead of Rela, encode the vtable
12912 entry to be used in the relocation's section offset. */
12913 if (! HAVE_NEWABI
&& fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
12915 reloc
->address
= reloc
->addend
;
12919 code
= fixp
->fx_r_type
;
12921 /* To support a PC relative reloc, we used a Cygnus extension.
12922 We check for that here to make sure that we don't let such a
12923 reloc escape normally. (FIXME: This was formerly used by
12924 embedded-PIC support, but is now used by branch handling in
12925 general. That probably should be fixed.) */
12926 if ((OUTPUT_FLAVOR
== bfd_target_ecoff_flavour
12927 || OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
12928 && code
== BFD_RELOC_16_PCREL_S2
)
12929 reloc
->howto
= NULL
;
12931 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
12933 if (reloc
->howto
== NULL
)
12935 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
12936 _("Can not represent %s relocation in this object file format"),
12937 bfd_get_reloc_code_name (code
));
12944 /* Relax a machine dependent frag. This returns the amount by which
12945 the current size of the frag should change. */
12948 mips_relax_frag (asection
*sec
, fragS
*fragp
, long stretch
)
12950 if (RELAX_BRANCH_P (fragp
->fr_subtype
))
12952 offsetT old_var
= fragp
->fr_var
;
12954 fragp
->fr_var
= relaxed_branch_length (fragp
, sec
, TRUE
);
12956 return fragp
->fr_var
- old_var
;
12959 if (! RELAX_MIPS16_P (fragp
->fr_subtype
))
12962 if (mips16_extended_frag (fragp
, NULL
, stretch
))
12964 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
12966 fragp
->fr_subtype
= RELAX_MIPS16_MARK_EXTENDED (fragp
->fr_subtype
);
12971 if (! RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
12973 fragp
->fr_subtype
= RELAX_MIPS16_CLEAR_EXTENDED (fragp
->fr_subtype
);
12980 /* Convert a machine dependent frag. */
12983 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
, segT asec
, fragS
*fragp
)
12985 if (RELAX_BRANCH_P (fragp
->fr_subtype
))
12988 unsigned long insn
;
12992 buf
= (bfd_byte
*)fragp
->fr_literal
+ fragp
->fr_fix
;
12994 if (target_big_endian
)
12995 insn
= bfd_getb32 (buf
);
12997 insn
= bfd_getl32 (buf
);
12999 if (!RELAX_BRANCH_TOOFAR (fragp
->fr_subtype
))
13001 /* We generate a fixup instead of applying it right now
13002 because, if there are linker relaxations, we're going to
13003 need the relocations. */
13004 exp
.X_op
= O_symbol
;
13005 exp
.X_add_symbol
= fragp
->fr_symbol
;
13006 exp
.X_add_number
= fragp
->fr_offset
;
13008 fixp
= fix_new_exp (fragp
, buf
- (bfd_byte
*)fragp
->fr_literal
,
13010 BFD_RELOC_16_PCREL_S2
);
13011 fixp
->fx_file
= fragp
->fr_file
;
13012 fixp
->fx_line
= fragp
->fr_line
;
13014 md_number_to_chars ((char *) buf
, insn
, 4);
13021 as_warn_where (fragp
->fr_file
, fragp
->fr_line
,
13022 _("relaxed out-of-range branch into a jump"));
13024 if (RELAX_BRANCH_UNCOND (fragp
->fr_subtype
))
13027 if (!RELAX_BRANCH_LIKELY (fragp
->fr_subtype
))
13029 /* Reverse the branch. */
13030 switch ((insn
>> 28) & 0xf)
13033 /* bc[0-3][tf]l? and bc1any[24][ft] instructions can
13034 have the condition reversed by tweaking a single
13035 bit, and their opcodes all have 0x4???????. */
13036 assert ((insn
& 0xf1000000) == 0x41000000);
13037 insn
^= 0x00010000;
13041 /* bltz 0x04000000 bgez 0x04010000
13042 bltzal 0x04100000 bgezal 0x04110000 */
13043 assert ((insn
& 0xfc0e0000) == 0x04000000);
13044 insn
^= 0x00010000;
13048 /* beq 0x10000000 bne 0x14000000
13049 blez 0x18000000 bgtz 0x1c000000 */
13050 insn
^= 0x04000000;
13058 if (RELAX_BRANCH_LINK (fragp
->fr_subtype
))
13060 /* Clear the and-link bit. */
13061 assert ((insn
& 0xfc1c0000) == 0x04100000);
13063 /* bltzal 0x04100000 bgezal 0x04110000
13064 bltzall 0x04120000 bgezall 0x04130000 */
13065 insn
&= ~0x00100000;
13068 /* Branch over the branch (if the branch was likely) or the
13069 full jump (not likely case). Compute the offset from the
13070 current instruction to branch to. */
13071 if (RELAX_BRANCH_LIKELY (fragp
->fr_subtype
))
13075 /* How many bytes in instructions we've already emitted? */
13076 i
= buf
- (bfd_byte
*)fragp
->fr_literal
- fragp
->fr_fix
;
13077 /* How many bytes in instructions from here to the end? */
13078 i
= fragp
->fr_var
- i
;
13080 /* Convert to instruction count. */
13082 /* Branch counts from the next instruction. */
13085 /* Branch over the jump. */
13086 md_number_to_chars ((char *) buf
, insn
, 4);
13090 md_number_to_chars ((char *) buf
, 0, 4);
13093 if (RELAX_BRANCH_LIKELY (fragp
->fr_subtype
))
13095 /* beql $0, $0, 2f */
13097 /* Compute the PC offset from the current instruction to
13098 the end of the variable frag. */
13099 /* How many bytes in instructions we've already emitted? */
13100 i
= buf
- (bfd_byte
*)fragp
->fr_literal
- fragp
->fr_fix
;
13101 /* How many bytes in instructions from here to the end? */
13102 i
= fragp
->fr_var
- i
;
13103 /* Convert to instruction count. */
13105 /* Don't decrement i, because we want to branch over the
13109 md_number_to_chars ((char *) buf
, insn
, 4);
13112 md_number_to_chars ((char *) buf
, 0, 4);
13117 if (mips_pic
== NO_PIC
)
13120 insn
= (RELAX_BRANCH_LINK (fragp
->fr_subtype
)
13121 ? 0x0c000000 : 0x08000000);
13122 exp
.X_op
= O_symbol
;
13123 exp
.X_add_symbol
= fragp
->fr_symbol
;
13124 exp
.X_add_number
= fragp
->fr_offset
;
13126 fixp
= fix_new_exp (fragp
, buf
- (bfd_byte
*)fragp
->fr_literal
,
13127 4, &exp
, 0, BFD_RELOC_MIPS_JMP
);
13128 fixp
->fx_file
= fragp
->fr_file
;
13129 fixp
->fx_line
= fragp
->fr_line
;
13131 md_number_to_chars ((char *) buf
, insn
, 4);
13136 /* lw/ld $at, <sym>($gp) R_MIPS_GOT16 */
13137 insn
= HAVE_64BIT_ADDRESSES
? 0xdf810000 : 0x8f810000;
13138 exp
.X_op
= O_symbol
;
13139 exp
.X_add_symbol
= fragp
->fr_symbol
;
13140 exp
.X_add_number
= fragp
->fr_offset
;
13142 if (fragp
->fr_offset
)
13144 exp
.X_add_symbol
= make_expr_symbol (&exp
);
13145 exp
.X_add_number
= 0;
13148 fixp
= fix_new_exp (fragp
, buf
- (bfd_byte
*)fragp
->fr_literal
,
13149 4, &exp
, 0, BFD_RELOC_MIPS_GOT16
);
13150 fixp
->fx_file
= fragp
->fr_file
;
13151 fixp
->fx_line
= fragp
->fr_line
;
13153 md_number_to_chars ((char *) buf
, insn
, 4);
13156 if (mips_opts
.isa
== ISA_MIPS1
)
13159 md_number_to_chars ((char *) buf
, 0, 4);
13163 /* d/addiu $at, $at, <sym> R_MIPS_LO16 */
13164 insn
= HAVE_64BIT_ADDRESSES
? 0x64210000 : 0x24210000;
13166 fixp
= fix_new_exp (fragp
, buf
- (bfd_byte
*)fragp
->fr_literal
,
13167 4, &exp
, 0, BFD_RELOC_LO16
);
13168 fixp
->fx_file
= fragp
->fr_file
;
13169 fixp
->fx_line
= fragp
->fr_line
;
13171 md_number_to_chars ((char *) buf
, insn
, 4);
13175 if (RELAX_BRANCH_LINK (fragp
->fr_subtype
))
13180 md_number_to_chars ((char *) buf
, insn
, 4);
13185 assert (buf
== (bfd_byte
*)fragp
->fr_literal
13186 + fragp
->fr_fix
+ fragp
->fr_var
);
13188 fragp
->fr_fix
+= fragp
->fr_var
;
13193 if (RELAX_MIPS16_P (fragp
->fr_subtype
))
13196 register const struct mips16_immed_operand
*op
;
13197 bfd_boolean small
, ext
;
13200 unsigned long insn
;
13201 bfd_boolean use_extend
;
13202 unsigned short extend
;
13204 type
= RELAX_MIPS16_TYPE (fragp
->fr_subtype
);
13205 op
= mips16_immed_operands
;
13206 while (op
->type
!= type
)
13209 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
13220 resolve_symbol_value (fragp
->fr_symbol
);
13221 val
= S_GET_VALUE (fragp
->fr_symbol
);
13226 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
13228 /* The rules for the base address of a PC relative reloc are
13229 complicated; see mips16_extended_frag. */
13230 if (type
== 'p' || type
== 'q')
13235 /* Ignore the low bit in the target, since it will be
13236 set for a text label. */
13237 if ((val
& 1) != 0)
13240 else if (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
))
13242 else if (RELAX_MIPS16_DSLOT (fragp
->fr_subtype
))
13245 addr
&= ~ (addressT
) ((1 << op
->shift
) - 1);
13248 /* Make sure the section winds up with the alignment we have
13251 record_alignment (asec
, op
->shift
);
13255 && (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
)
13256 || RELAX_MIPS16_DSLOT (fragp
->fr_subtype
)))
13257 as_warn_where (fragp
->fr_file
, fragp
->fr_line
,
13258 _("extended instruction in delay slot"));
13260 buf
= (bfd_byte
*) (fragp
->fr_literal
+ fragp
->fr_fix
);
13262 if (target_big_endian
)
13263 insn
= bfd_getb16 (buf
);
13265 insn
= bfd_getl16 (buf
);
13267 mips16_immed (fragp
->fr_file
, fragp
->fr_line
, type
, val
,
13268 RELAX_MIPS16_USER_EXT (fragp
->fr_subtype
),
13269 small
, ext
, &insn
, &use_extend
, &extend
);
13273 md_number_to_chars ((char *) buf
, 0xf000 | extend
, 2);
13274 fragp
->fr_fix
+= 2;
13278 md_number_to_chars ((char *) buf
, insn
, 2);
13279 fragp
->fr_fix
+= 2;
13287 first
= RELAX_FIRST (fragp
->fr_subtype
);
13288 second
= RELAX_SECOND (fragp
->fr_subtype
);
13289 fixp
= (fixS
*) fragp
->fr_opcode
;
13291 /* Possibly emit a warning if we've chosen the longer option. */
13292 if (((fragp
->fr_subtype
& RELAX_USE_SECOND
) != 0)
13293 == ((fragp
->fr_subtype
& RELAX_SECOND_LONGER
) != 0))
13295 const char *msg
= macro_warning (fragp
->fr_subtype
);
13297 as_warn_where (fragp
->fr_file
, fragp
->fr_line
, msg
);
13300 /* Go through all the fixups for the first sequence. Disable them
13301 (by marking them as done) if we're going to use the second
13302 sequence instead. */
13304 && fixp
->fx_frag
== fragp
13305 && fixp
->fx_where
< fragp
->fr_fix
- second
)
13307 if (fragp
->fr_subtype
& RELAX_USE_SECOND
)
13309 fixp
= fixp
->fx_next
;
13312 /* Go through the fixups for the second sequence. Disable them if
13313 we're going to use the first sequence, otherwise adjust their
13314 addresses to account for the relaxation. */
13315 while (fixp
&& fixp
->fx_frag
== fragp
)
13317 if (fragp
->fr_subtype
& RELAX_USE_SECOND
)
13318 fixp
->fx_where
-= first
;
13321 fixp
= fixp
->fx_next
;
13324 /* Now modify the frag contents. */
13325 if (fragp
->fr_subtype
& RELAX_USE_SECOND
)
13329 start
= fragp
->fr_literal
+ fragp
->fr_fix
- first
- second
;
13330 memmove (start
, start
+ first
, second
);
13331 fragp
->fr_fix
-= first
;
13334 fragp
->fr_fix
-= second
;
13340 /* This function is called after the relocs have been generated.
13341 We've been storing mips16 text labels as odd. Here we convert them
13342 back to even for the convenience of the debugger. */
13345 mips_frob_file_after_relocs (void)
13348 unsigned int count
, i
;
13350 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
13353 syms
= bfd_get_outsymbols (stdoutput
);
13354 count
= bfd_get_symcount (stdoutput
);
13355 for (i
= 0; i
< count
; i
++, syms
++)
13357 if (elf_symbol (*syms
)->internal_elf_sym
.st_other
== STO_MIPS16
13358 && ((*syms
)->value
& 1) != 0)
13360 (*syms
)->value
&= ~1;
13361 /* If the symbol has an odd size, it was probably computed
13362 incorrectly, so adjust that as well. */
13363 if ((elf_symbol (*syms
)->internal_elf_sym
.st_size
& 1) != 0)
13364 ++elf_symbol (*syms
)->internal_elf_sym
.st_size
;
13371 /* This function is called whenever a label is defined. It is used
13372 when handling branch delays; if a branch has a label, we assume we
13373 can not move it. */
13376 mips_define_label (symbolS
*sym
)
13378 struct insn_label_list
*l
;
13380 if (free_insn_labels
== NULL
)
13381 l
= (struct insn_label_list
*) xmalloc (sizeof *l
);
13384 l
= free_insn_labels
;
13385 free_insn_labels
= l
->next
;
13389 l
->next
= insn_labels
;
13393 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13395 /* Some special processing for a MIPS ELF file. */
13398 mips_elf_final_processing (void)
13400 /* Write out the register information. */
13401 if (mips_abi
!= N64_ABI
)
13405 s
.ri_gprmask
= mips_gprmask
;
13406 s
.ri_cprmask
[0] = mips_cprmask
[0];
13407 s
.ri_cprmask
[1] = mips_cprmask
[1];
13408 s
.ri_cprmask
[2] = mips_cprmask
[2];
13409 s
.ri_cprmask
[3] = mips_cprmask
[3];
13410 /* The gp_value field is set by the MIPS ELF backend. */
13412 bfd_mips_elf32_swap_reginfo_out (stdoutput
, &s
,
13413 ((Elf32_External_RegInfo
*)
13414 mips_regmask_frag
));
13418 Elf64_Internal_RegInfo s
;
13420 s
.ri_gprmask
= mips_gprmask
;
13422 s
.ri_cprmask
[0] = mips_cprmask
[0];
13423 s
.ri_cprmask
[1] = mips_cprmask
[1];
13424 s
.ri_cprmask
[2] = mips_cprmask
[2];
13425 s
.ri_cprmask
[3] = mips_cprmask
[3];
13426 /* The gp_value field is set by the MIPS ELF backend. */
13428 bfd_mips_elf64_swap_reginfo_out (stdoutput
, &s
,
13429 ((Elf64_External_RegInfo
*)
13430 mips_regmask_frag
));
13433 /* Set the MIPS ELF flag bits. FIXME: There should probably be some
13434 sort of BFD interface for this. */
13435 if (mips_any_noreorder
)
13436 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_NOREORDER
;
13437 if (mips_pic
!= NO_PIC
)
13439 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_PIC
;
13440 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_CPIC
;
13443 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_CPIC
;
13445 /* Set MIPS ELF flags for ASEs. */
13446 if (file_ase_mips16
)
13447 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ARCH_ASE_M16
;
13448 #if 0 /* XXX FIXME */
13449 if (file_ase_mips3d
)
13450 elf_elfheader (stdoutput
)->e_flags
|= ???;
13453 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ARCH_ASE_MDMX
;
13455 /* Set the MIPS ELF ABI flags. */
13456 if (mips_abi
== O32_ABI
&& USE_E_MIPS_ABI_O32
)
13457 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_O32
;
13458 else if (mips_abi
== O64_ABI
)
13459 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_O64
;
13460 else if (mips_abi
== EABI_ABI
)
13462 if (!file_mips_gp32
)
13463 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_EABI64
;
13465 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_EABI32
;
13467 else if (mips_abi
== N32_ABI
)
13468 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ABI2
;
13470 /* Nothing to do for N64_ABI. */
13472 if (mips_32bitmode
)
13473 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_32BITMODE
;
13476 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */
13478 typedef struct proc
{
13480 symbolS
*func_end_sym
;
13481 unsigned long reg_mask
;
13482 unsigned long reg_offset
;
13483 unsigned long fpreg_mask
;
13484 unsigned long fpreg_offset
;
13485 unsigned long frame_offset
;
13486 unsigned long frame_reg
;
13487 unsigned long pc_reg
;
13490 static procS cur_proc
;
13491 static procS
*cur_proc_ptr
;
13492 static int numprocs
;
13494 /* Fill in an rs_align_code fragment. */
13497 mips_handle_align (fragS
*fragp
)
13499 if (fragp
->fr_type
!= rs_align_code
)
13502 if (mips_opts
.mips16
)
13504 static const unsigned char be_nop
[] = { 0x65, 0x00 };
13505 static const unsigned char le_nop
[] = { 0x00, 0x65 };
13510 bytes
= fragp
->fr_next
->fr_address
- fragp
->fr_address
- fragp
->fr_fix
;
13511 p
= fragp
->fr_literal
+ fragp
->fr_fix
;
13519 memcpy (p
, (target_big_endian
? be_nop
: le_nop
), 2);
13523 /* For mips32, a nop is a zero, which we trivially get by doing nothing. */
13527 md_obj_begin (void)
13534 /* check for premature end, nesting errors, etc */
13536 as_warn (_("missing .end at end of assembly"));
13545 if (*input_line_pointer
== '-')
13547 ++input_line_pointer
;
13550 if (!ISDIGIT (*input_line_pointer
))
13551 as_bad (_("expected simple number"));
13552 if (input_line_pointer
[0] == '0')
13554 if (input_line_pointer
[1] == 'x')
13556 input_line_pointer
+= 2;
13557 while (ISXDIGIT (*input_line_pointer
))
13560 val
|= hex_value (*input_line_pointer
++);
13562 return negative
? -val
: val
;
13566 ++input_line_pointer
;
13567 while (ISDIGIT (*input_line_pointer
))
13570 val
|= *input_line_pointer
++ - '0';
13572 return negative
? -val
: val
;
13575 if (!ISDIGIT (*input_line_pointer
))
13577 printf (_(" *input_line_pointer == '%c' 0x%02x\n"),
13578 *input_line_pointer
, *input_line_pointer
);
13579 as_warn (_("invalid number"));
13582 while (ISDIGIT (*input_line_pointer
))
13585 val
+= *input_line_pointer
++ - '0';
13587 return negative
? -val
: val
;
13590 /* The .file directive; just like the usual .file directive, but there
13591 is an initial number which is the ECOFF file index. In the non-ECOFF
13592 case .file implies DWARF-2. */
13595 s_mips_file (int x ATTRIBUTE_UNUSED
)
13597 static int first_file_directive
= 0;
13599 if (ECOFF_DEBUGGING
)
13608 filename
= dwarf2_directive_file (0);
13610 /* Versions of GCC up to 3.1 start files with a ".file"
13611 directive even for stabs output. Make sure that this
13612 ".file" is handled. Note that you need a version of GCC
13613 after 3.1 in order to support DWARF-2 on MIPS. */
13614 if (filename
!= NULL
&& ! first_file_directive
)
13616 (void) new_logical_line (filename
, -1);
13617 s_app_file_string (filename
, 0);
13619 first_file_directive
= 1;
13623 /* The .loc directive, implying DWARF-2. */
13626 s_mips_loc (int x ATTRIBUTE_UNUSED
)
13628 if (!ECOFF_DEBUGGING
)
13629 dwarf2_directive_loc (0);
13632 /* The .end directive. */
13635 s_mips_end (int x ATTRIBUTE_UNUSED
)
13639 /* Following functions need their own .frame and .cprestore directives. */
13640 mips_frame_reg_valid
= 0;
13641 mips_cprestore_valid
= 0;
13643 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
13646 demand_empty_rest_of_line ();
13651 if ((bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) == 0)
13652 as_warn (_(".end not in text section"));
13656 as_warn (_(".end directive without a preceding .ent directive."));
13657 demand_empty_rest_of_line ();
13663 assert (S_GET_NAME (p
));
13664 if (strcmp (S_GET_NAME (p
), S_GET_NAME (cur_proc_ptr
->func_sym
)))
13665 as_warn (_(".end symbol does not match .ent symbol."));
13667 if (debug_type
== DEBUG_STABS
)
13668 stabs_generate_asm_endfunc (S_GET_NAME (p
),
13672 as_warn (_(".end directive missing or unknown symbol"));
13675 /* Create an expression to calculate the size of the function. */
13676 if (p
&& cur_proc_ptr
)
13678 OBJ_SYMFIELD_TYPE
*obj
= symbol_get_obj (p
);
13679 expressionS
*exp
= xmalloc (sizeof (expressionS
));
13682 exp
->X_op
= O_subtract
;
13683 exp
->X_add_symbol
= symbol_temp_new_now ();
13684 exp
->X_op_symbol
= p
;
13685 exp
->X_add_number
= 0;
13687 cur_proc_ptr
->func_end_sym
= exp
->X_add_symbol
;
13690 /* Generate a .pdr section. */
13691 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
&& ! ECOFF_DEBUGGING
13694 segT saved_seg
= now_seg
;
13695 subsegT saved_subseg
= now_subseg
;
13700 dot
= frag_now_fix ();
13702 #ifdef md_flush_pending_output
13703 md_flush_pending_output ();
13707 subseg_set (pdr_seg
, 0);
13709 /* Write the symbol. */
13710 exp
.X_op
= O_symbol
;
13711 exp
.X_add_symbol
= p
;
13712 exp
.X_add_number
= 0;
13713 emit_expr (&exp
, 4);
13715 fragp
= frag_more (7 * 4);
13717 md_number_to_chars (fragp
, cur_proc_ptr
->reg_mask
, 4);
13718 md_number_to_chars (fragp
+ 4, cur_proc_ptr
->reg_offset
, 4);
13719 md_number_to_chars (fragp
+ 8, cur_proc_ptr
->fpreg_mask
, 4);
13720 md_number_to_chars (fragp
+ 12, cur_proc_ptr
->fpreg_offset
, 4);
13721 md_number_to_chars (fragp
+ 16, cur_proc_ptr
->frame_offset
, 4);
13722 md_number_to_chars (fragp
+ 20, cur_proc_ptr
->frame_reg
, 4);
13723 md_number_to_chars (fragp
+ 24, cur_proc_ptr
->pc_reg
, 4);
13725 subseg_set (saved_seg
, saved_subseg
);
13727 #endif /* OBJ_ELF */
13729 cur_proc_ptr
= NULL
;
13732 /* The .aent and .ent directives. */
13735 s_mips_ent (int aent
)
13739 symbolP
= get_symbol ();
13740 if (*input_line_pointer
== ',')
13741 ++input_line_pointer
;
13742 SKIP_WHITESPACE ();
13743 if (ISDIGIT (*input_line_pointer
)
13744 || *input_line_pointer
== '-')
13747 if ((bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) == 0)
13748 as_warn (_(".ent or .aent not in text section."));
13750 if (!aent
&& cur_proc_ptr
)
13751 as_warn (_("missing .end"));
13755 /* This function needs its own .frame and .cprestore directives. */
13756 mips_frame_reg_valid
= 0;
13757 mips_cprestore_valid
= 0;
13759 cur_proc_ptr
= &cur_proc
;
13760 memset (cur_proc_ptr
, '\0', sizeof (procS
));
13762 cur_proc_ptr
->func_sym
= symbolP
;
13764 symbol_get_bfdsym (symbolP
)->flags
|= BSF_FUNCTION
;
13768 if (debug_type
== DEBUG_STABS
)
13769 stabs_generate_asm_func (S_GET_NAME (symbolP
),
13770 S_GET_NAME (symbolP
));
13773 demand_empty_rest_of_line ();
13776 /* The .frame directive. If the mdebug section is present (IRIX 5 native)
13777 then ecoff.c (ecoff_directive_frame) is used. For embedded targets,
13778 s_mips_frame is used so that we can set the PDR information correctly.
13779 We can't use the ecoff routines because they make reference to the ecoff
13780 symbol table (in the mdebug section). */
13783 s_mips_frame (int ignore ATTRIBUTE_UNUSED
)
13786 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
&& ! ECOFF_DEBUGGING
)
13790 if (cur_proc_ptr
== (procS
*) NULL
)
13792 as_warn (_(".frame outside of .ent"));
13793 demand_empty_rest_of_line ();
13797 cur_proc_ptr
->frame_reg
= tc_get_register (1);
13799 SKIP_WHITESPACE ();
13800 if (*input_line_pointer
++ != ','
13801 || get_absolute_expression_and_terminator (&val
) != ',')
13803 as_warn (_("Bad .frame directive"));
13804 --input_line_pointer
;
13805 demand_empty_rest_of_line ();
13809 cur_proc_ptr
->frame_offset
= val
;
13810 cur_proc_ptr
->pc_reg
= tc_get_register (0);
13812 demand_empty_rest_of_line ();
13815 #endif /* OBJ_ELF */
13819 /* The .fmask and .mask directives. If the mdebug section is present
13820 (IRIX 5 native) then ecoff.c (ecoff_directive_mask) is used. For
13821 embedded targets, s_mips_mask is used so that we can set the PDR
13822 information correctly. We can't use the ecoff routines because they
13823 make reference to the ecoff symbol table (in the mdebug section). */
13826 s_mips_mask (int reg_type
)
13829 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
&& ! ECOFF_DEBUGGING
)
13833 if (cur_proc_ptr
== (procS
*) NULL
)
13835 as_warn (_(".mask/.fmask outside of .ent"));
13836 demand_empty_rest_of_line ();
13840 if (get_absolute_expression_and_terminator (&mask
) != ',')
13842 as_warn (_("Bad .mask/.fmask directive"));
13843 --input_line_pointer
;
13844 demand_empty_rest_of_line ();
13848 off
= get_absolute_expression ();
13850 if (reg_type
== 'F')
13852 cur_proc_ptr
->fpreg_mask
= mask
;
13853 cur_proc_ptr
->fpreg_offset
= off
;
13857 cur_proc_ptr
->reg_mask
= mask
;
13858 cur_proc_ptr
->reg_offset
= off
;
13861 demand_empty_rest_of_line ();
13864 #endif /* OBJ_ELF */
13865 s_ignore (reg_type
);
13868 /* A table describing all the processors gas knows about. Names are
13869 matched in the order listed.
13871 To ease comparison, please keep this table in the same order as
13872 gcc's mips_cpu_info_table[]. */
13873 static const struct mips_cpu_info mips_cpu_info_table
[] =
13875 /* Entries for generic ISAs */
13876 { "mips1", 1, ISA_MIPS1
, CPU_R3000
},
13877 { "mips2", 1, ISA_MIPS2
, CPU_R6000
},
13878 { "mips3", 1, ISA_MIPS3
, CPU_R4000
},
13879 { "mips4", 1, ISA_MIPS4
, CPU_R8000
},
13880 { "mips5", 1, ISA_MIPS5
, CPU_MIPS5
},
13881 { "mips32", 1, ISA_MIPS32
, CPU_MIPS32
},
13882 { "mips32r2", 1, ISA_MIPS32R2
, CPU_MIPS32R2
},
13883 { "mips64", 1, ISA_MIPS64
, CPU_MIPS64
},
13884 { "mips64r2", 1, ISA_MIPS64R2
, CPU_MIPS64R2
},
13887 { "r3000", 0, ISA_MIPS1
, CPU_R3000
},
13888 { "r2000", 0, ISA_MIPS1
, CPU_R3000
},
13889 { "r3900", 0, ISA_MIPS1
, CPU_R3900
},
13892 { "r6000", 0, ISA_MIPS2
, CPU_R6000
},
13895 { "r4000", 0, ISA_MIPS3
, CPU_R4000
},
13896 { "r4010", 0, ISA_MIPS2
, CPU_R4010
},
13897 { "vr4100", 0, ISA_MIPS3
, CPU_VR4100
},
13898 { "vr4111", 0, ISA_MIPS3
, CPU_R4111
},
13899 { "vr4120", 0, ISA_MIPS3
, CPU_VR4120
},
13900 { "vr4130", 0, ISA_MIPS3
, CPU_VR4120
},
13901 { "vr4181", 0, ISA_MIPS3
, CPU_R4111
},
13902 { "vr4300", 0, ISA_MIPS3
, CPU_R4300
},
13903 { "r4400", 0, ISA_MIPS3
, CPU_R4400
},
13904 { "r4600", 0, ISA_MIPS3
, CPU_R4600
},
13905 { "orion", 0, ISA_MIPS3
, CPU_R4600
},
13906 { "r4650", 0, ISA_MIPS3
, CPU_R4650
},
13909 { "r8000", 0, ISA_MIPS4
, CPU_R8000
},
13910 { "r10000", 0, ISA_MIPS4
, CPU_R10000
},
13911 { "r12000", 0, ISA_MIPS4
, CPU_R12000
},
13912 { "vr5000", 0, ISA_MIPS4
, CPU_R5000
},
13913 { "vr5400", 0, ISA_MIPS4
, CPU_VR5400
},
13914 { "vr5500", 0, ISA_MIPS4
, CPU_VR5500
},
13915 { "rm5200", 0, ISA_MIPS4
, CPU_R5000
},
13916 { "rm5230", 0, ISA_MIPS4
, CPU_R5000
},
13917 { "rm5231", 0, ISA_MIPS4
, CPU_R5000
},
13918 { "rm5261", 0, ISA_MIPS4
, CPU_R5000
},
13919 { "rm5721", 0, ISA_MIPS4
, CPU_R5000
},
13920 { "rm7000", 0, ISA_MIPS4
, CPU_RM7000
},
13921 { "rm9000", 0, ISA_MIPS4
, CPU_RM9000
},
13924 { "4kc", 0, ISA_MIPS32
, CPU_MIPS32
},
13925 { "4km", 0, ISA_MIPS32
, CPU_MIPS32
},
13926 { "4kp", 0, ISA_MIPS32
, CPU_MIPS32
},
13929 { "5kc", 0, ISA_MIPS64
, CPU_MIPS64
},
13930 { "20kc", 0, ISA_MIPS64
, CPU_MIPS64
},
13932 /* Broadcom SB-1 CPU core */
13933 { "sb1", 0, ISA_MIPS64
, CPU_SB1
},
13940 /* Return true if GIVEN is the same as CANONICAL, or if it is CANONICAL
13941 with a final "000" replaced by "k". Ignore case.
13943 Note: this function is shared between GCC and GAS. */
13946 mips_strict_matching_cpu_name_p (const char *canonical
, const char *given
)
13948 while (*given
!= 0 && TOLOWER (*given
) == TOLOWER (*canonical
))
13949 given
++, canonical
++;
13951 return ((*given
== 0 && *canonical
== 0)
13952 || (strcmp (canonical
, "000") == 0 && strcasecmp (given
, "k") == 0));
13956 /* Return true if GIVEN matches CANONICAL, where GIVEN is a user-supplied
13957 CPU name. We've traditionally allowed a lot of variation here.
13959 Note: this function is shared between GCC and GAS. */
13962 mips_matching_cpu_name_p (const char *canonical
, const char *given
)
13964 /* First see if the name matches exactly, or with a final "000"
13965 turned into "k". */
13966 if (mips_strict_matching_cpu_name_p (canonical
, given
))
13969 /* If not, try comparing based on numerical designation alone.
13970 See if GIVEN is an unadorned number, or 'r' followed by a number. */
13971 if (TOLOWER (*given
) == 'r')
13973 if (!ISDIGIT (*given
))
13976 /* Skip over some well-known prefixes in the canonical name,
13977 hoping to find a number there too. */
13978 if (TOLOWER (canonical
[0]) == 'v' && TOLOWER (canonical
[1]) == 'r')
13980 else if (TOLOWER (canonical
[0]) == 'r' && TOLOWER (canonical
[1]) == 'm')
13982 else if (TOLOWER (canonical
[0]) == 'r')
13985 return mips_strict_matching_cpu_name_p (canonical
, given
);
13989 /* Parse an option that takes the name of a processor as its argument.
13990 OPTION is the name of the option and CPU_STRING is the argument.
13991 Return the corresponding processor enumeration if the CPU_STRING is
13992 recognized, otherwise report an error and return null.
13994 A similar function exists in GCC. */
13996 static const struct mips_cpu_info
*
13997 mips_parse_cpu (const char *option
, const char *cpu_string
)
13999 const struct mips_cpu_info
*p
;
14001 /* 'from-abi' selects the most compatible architecture for the given
14002 ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit ABIs. For the
14003 EABIs, we have to decide whether we're using the 32-bit or 64-bit
14004 version. Look first at the -mgp options, if given, otherwise base
14005 the choice on MIPS_DEFAULT_64BIT.
14007 Treat NO_ABI like the EABIs. One reason to do this is that the
14008 plain 'mips' and 'mips64' configs have 'from-abi' as their default
14009 architecture. This code picks MIPS I for 'mips' and MIPS III for
14010 'mips64', just as we did in the days before 'from-abi'. */
14011 if (strcasecmp (cpu_string
, "from-abi") == 0)
14013 if (ABI_NEEDS_32BIT_REGS (mips_abi
))
14014 return mips_cpu_info_from_isa (ISA_MIPS1
);
14016 if (ABI_NEEDS_64BIT_REGS (mips_abi
))
14017 return mips_cpu_info_from_isa (ISA_MIPS3
);
14019 if (file_mips_gp32
>= 0)
14020 return mips_cpu_info_from_isa (file_mips_gp32
? ISA_MIPS1
: ISA_MIPS3
);
14022 return mips_cpu_info_from_isa (MIPS_DEFAULT_64BIT
14027 /* 'default' has traditionally been a no-op. Probably not very useful. */
14028 if (strcasecmp (cpu_string
, "default") == 0)
14031 for (p
= mips_cpu_info_table
; p
->name
!= 0; p
++)
14032 if (mips_matching_cpu_name_p (p
->name
, cpu_string
))
14035 as_bad ("Bad value (%s) for %s", cpu_string
, option
);
14039 /* Return the canonical processor information for ISA (a member of the
14040 ISA_MIPS* enumeration). */
14042 static const struct mips_cpu_info
*
14043 mips_cpu_info_from_isa (int isa
)
14047 for (i
= 0; mips_cpu_info_table
[i
].name
!= NULL
; i
++)
14048 if (mips_cpu_info_table
[i
].is_isa
14049 && isa
== mips_cpu_info_table
[i
].isa
)
14050 return (&mips_cpu_info_table
[i
]);
14055 static const struct mips_cpu_info
*
14056 mips_cpu_info_from_arch (int arch
)
14060 for (i
= 0; mips_cpu_info_table
[i
].name
!= NULL
; i
++)
14061 if (arch
== mips_cpu_info_table
[i
].cpu
)
14062 return (&mips_cpu_info_table
[i
]);
14068 show (FILE *stream
, const char *string
, int *col_p
, int *first_p
)
14072 fprintf (stream
, "%24s", "");
14077 fprintf (stream
, ", ");
14081 if (*col_p
+ strlen (string
) > 72)
14083 fprintf (stream
, "\n%24s", "");
14087 fprintf (stream
, "%s", string
);
14088 *col_p
+= strlen (string
);
14094 md_show_usage (FILE *stream
)
14099 fprintf (stream
, _("\
14101 -EB generate big endian output\n\
14102 -EL generate little endian output\n\
14103 -g, -g2 do not remove unneeded NOPs or swap branches\n\
14104 -G NUM allow referencing objects up to NUM bytes\n\
14105 implicitly with the gp register [default 8]\n"));
14106 fprintf (stream
, _("\
14107 -mips1 generate MIPS ISA I instructions\n\
14108 -mips2 generate MIPS ISA II instructions\n\
14109 -mips3 generate MIPS ISA III instructions\n\
14110 -mips4 generate MIPS ISA IV instructions\n\
14111 -mips5 generate MIPS ISA V instructions\n\
14112 -mips32 generate MIPS32 ISA instructions\n\
14113 -mips32r2 generate MIPS32 release 2 ISA instructions\n\
14114 -mips64 generate MIPS64 ISA instructions\n\
14115 -mips64r2 generate MIPS64 release 2 ISA instructions\n\
14116 -march=CPU/-mtune=CPU generate code/schedule for CPU, where CPU is one of:\n"));
14120 for (i
= 0; mips_cpu_info_table
[i
].name
!= NULL
; i
++)
14121 show (stream
, mips_cpu_info_table
[i
].name
, &column
, &first
);
14122 show (stream
, "from-abi", &column
, &first
);
14123 fputc ('\n', stream
);
14125 fprintf (stream
, _("\
14126 -mCPU equivalent to -march=CPU -mtune=CPU. Deprecated.\n\
14127 -no-mCPU don't generate code specific to CPU.\n\
14128 For -mCPU and -no-mCPU, CPU must be one of:\n"));
14132 show (stream
, "3900", &column
, &first
);
14133 show (stream
, "4010", &column
, &first
);
14134 show (stream
, "4100", &column
, &first
);
14135 show (stream
, "4650", &column
, &first
);
14136 fputc ('\n', stream
);
14138 fprintf (stream
, _("\
14139 -mips16 generate mips16 instructions\n\
14140 -no-mips16 do not generate mips16 instructions\n"));
14141 fprintf (stream
, _("\
14142 -mfix-vr4120 work around certain VR4120 errata\n\
14143 -mgp32 use 32-bit GPRs, regardless of the chosen ISA\n\
14144 -mfp32 use 32-bit FPRs, regardless of the chosen ISA\n\
14145 -mno-shared optimize output for executables\n\
14146 -msym32 assume all symbols have 32-bit values\n\
14147 -O0 remove unneeded NOPs, do not swap branches\n\
14148 -O remove unneeded NOPs and swap branches\n\
14149 --[no-]construct-floats [dis]allow floating point values to be constructed\n\
14150 --trap, --no-break trap exception on div by 0 and mult overflow\n\
14151 --break, --no-trap break exception on div by 0 and mult overflow\n"));
14153 fprintf (stream
, _("\
14154 -KPIC, -call_shared generate SVR4 position independent code\n\
14155 -non_shared do not generate position independent code\n\
14156 -xgot assume a 32 bit GOT\n\
14157 -mpdr, -mno-pdr enable/disable creation of .pdr sections\n\
14158 -mshared, -mno-shared disable/enable .cpload optimization for\n\
14160 -mabi=ABI create ABI conformant object file for:\n"));
14164 show (stream
, "32", &column
, &first
);
14165 show (stream
, "o64", &column
, &first
);
14166 show (stream
, "n32", &column
, &first
);
14167 show (stream
, "64", &column
, &first
);
14168 show (stream
, "eabi", &column
, &first
);
14170 fputc ('\n', stream
);
14172 fprintf (stream
, _("\
14173 -32 create o32 ABI object file (default)\n\
14174 -n32 create n32 ABI object file\n\
14175 -64 create 64 ABI object file\n"));
14180 mips_dwarf2_format (void)
14182 if (mips_abi
== N64_ABI
)
14185 return dwarf2_format_64bit_irix
;
14187 return dwarf2_format_64bit
;
14191 return dwarf2_format_32bit
;
14195 mips_dwarf2_addr_size (void)
14197 if (mips_abi
== N64_ABI
)