1 /* tc-mips.c -- assemble code for a MIPS chip.
2 Copyright (C) 1993, 1995, 1996 Free Software Foundation, Inc.
3 Contributed by the OSF and Ralph Campbell.
4 Written by Keith Knowles and Ralph Campbell, working independently.
5 Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus
8 This file is part of GAS.
10 GAS is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 2, or (at your option)
15 GAS is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with GAS; see the file COPYING. If not, write to the Free
22 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
28 #include "libiberty.h"
39 #include "opcode/mips.h"
42 /* Clean up namespace so we can include obj-elf.h too. */
43 static int mips_output_flavor () { return OUTPUT_FLAVOR
; }
44 #undef OBJ_PROCESS_STAB
50 #undef TARGET_SYMBOL_FIELDS
52 #undef obj_frob_symbol
54 #undef obj_sec_sym_ok_for_reloc
57 /* Fix any of them that we actually care about. */
59 #define OUTPUT_FLAVOR mips_output_flavor()
66 #ifndef ECOFF_DEBUGGING
67 #define NO_ECOFF_DEBUGGING
68 #define ECOFF_DEBUGGING 0
73 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
74 static char *mips_regmask_frag
;
78 #define PIC_CALL_REG 25
86 extern int target_big_endian
;
88 /* 1 is we should use the 64 bit MIPS ELF ABI, 0 if we should use the
89 32 bit ABI. This has no meaning for ECOFF. */
92 /* The default target format to use. */
96 switch (OUTPUT_FLAVOR
)
98 case bfd_target_aout_flavour
:
99 return target_big_endian
? "a.out-mips-big" : "a.out-mips-little";
100 case bfd_target_ecoff_flavour
:
101 return target_big_endian
? "ecoff-bigmips" : "ecoff-littlemips";
102 case bfd_target_elf_flavour
:
103 return (target_big_endian
104 ? (mips_64
? "elf64-bigmips" : "elf32-bigmips")
105 : (mips_64
? "elf64-littlemips" : "elf32-littlemips"));
111 /* The name of the readonly data section. */
112 #define RDATA_SECTION_NAME (OUTPUT_FLAVOR == bfd_target_aout_flavour \
114 : OUTPUT_FLAVOR == bfd_target_ecoff_flavour \
116 : OUTPUT_FLAVOR == bfd_target_elf_flavour \
120 /* These variables are filled in with the masks of registers used.
121 The object format code reads them and puts them in the appropriate
123 unsigned long mips_gprmask
;
124 unsigned long mips_cprmask
[4];
126 /* MIPS ISA (Instruction Set Architecture) level (may be changed
127 temporarily using .set mipsN). */
128 static int mips_isa
= -1;
130 /* MIPS ISA we are using for this output file. */
131 static int file_mips_isa
;
133 /* The CPU type as a number: 2000, 3000, 4000, 4400, etc. */
134 static int mips_cpu
= -1;
136 /* Whether the 4650 instructions (mad/madu) are permitted. */
137 static int mips_4650
= -1;
139 /* Whether the 4010 instructions are permitted. */
140 static int mips_4010
= -1;
142 /* Whether the 4100 MADD16 and DMADD16 are permitted. */
143 static int mips_4100
= -1;
145 /* Whether the processor uses hardware interlocks, and thus does not
146 require nops to be inserted. */
147 static int interlocks
= -1;
149 /* As with "interlocks" this is used by hardware that has FP
150 (co-processor) interlocks. */
151 static int cop_interlocks
= -1;
153 /* MIPS PIC level. */
157 /* Do not generate PIC code. */
160 /* Generate PIC code as in Irix 4. This is not implemented, and I'm
161 not sure what it is supposed to do. */
164 /* Generate PIC code as in the SVR4 MIPS ABI. */
167 /* Generate PIC code without using a global offset table: the data
168 segment has a maximum size of 64K, all data references are off
169 the $gp register, and all text references are PC relative. This
170 is used on some embedded systems. */
174 static enum mips_pic_level mips_pic
;
176 /* 1 if we should generate 32 bit offsets from the GP register in
177 SVR4_PIC mode. Currently has no meaning in other modes. */
178 static int mips_big_got
;
180 /* 1 if trap instructions should used for overflow rather than break
182 static int mips_trap
;
184 static int mips_warn_about_macros
;
185 static int mips_noreorder
;
186 static int mips_any_noreorder
;
187 static int mips_nomove
;
188 static int mips_noat
;
189 static int mips_nobopt
;
191 /* The size of the small data section. */
192 static int g_switch_value
= 8;
193 /* Whether the -G option was used. */
194 static int g_switch_seen
= 0;
199 /* If we can determine in advance that GP optimization won't be
200 possible, we can skip the relaxation stuff that tries to produce
201 GP-relative references. This makes delay slot optimization work
204 This function can only provide a guess, but it seems to work for
205 gcc output. If it guesses wrong, the only loss should be in
206 efficiency; it shouldn't introduce any bugs.
208 I don't know if a fix is needed for the SVR4_PIC mode. I've only
209 fixed it for the non-PIC mode. KR 95/04/07 */
210 static int nopic_need_relax
PARAMS ((symbolS
*));
212 /* handle of the OPCODE hash table */
213 static struct hash_control
*op_hash
= NULL
;
215 /* This array holds the chars that always start a comment. If the
216 pre-processor is disabled, these aren't very useful */
217 const char comment_chars
[] = "#";
219 /* This array holds the chars that only start a comment at the beginning of
220 a line. If the line seems to have the form '# 123 filename'
221 .line and .file directives will appear in the pre-processed output */
222 /* Note that input_file.c hand checks for '#' at the beginning of the
223 first line of the input file. This is because the compiler outputs
224 #NO_APP at the beginning of its output. */
225 /* Also note that C style comments are always supported. */
226 const char line_comment_chars
[] = "#";
228 /* This array holds machine specific line separator characters. */
229 const char line_separator_chars
[] = "";
231 /* Chars that can be used to separate mant from exp in floating point nums */
232 const char EXP_CHARS
[] = "eE";
234 /* Chars that mean this number is a floating point constant */
237 const char FLT_CHARS
[] = "rRsSfFdDxXpP";
239 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
240 changed in read.c . Ideally it shouldn't have to know about it at all,
241 but nothing is ideal around here.
244 static char *insn_error
;
246 static int byte_order
;
248 static int auto_align
= 1;
250 /* Symbol labelling the current insn. */
251 static symbolS
*insn_label
;
253 /* When outputting SVR4 PIC code, the assembler needs to know the
254 offset in the stack frame from which to restore the $gp register.
255 This is set by the .cprestore pseudo-op, and saved in this
257 static offsetT mips_cprestore_offset
= -1;
259 /* This is the register which holds the stack frame, as set by the
260 .frame pseudo-op. This is needed to implement .cprestore. */
261 static int mips_frame_reg
= SP
;
263 /* To output NOP instructions correctly, we need to keep information
264 about the previous two instructions. */
266 /* Whether we are optimizing. The default value of 2 means to remove
267 unneeded NOPs and swap branch instructions when possible. A value
268 of 1 means to not swap branches. A value of 0 means to always
270 static int mips_optimize
= 2;
272 /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is
273 equivalent to seeing no -g option at all. */
274 static int mips_debug
= 0;
276 /* The previous instruction. */
277 static struct mips_cl_insn prev_insn
;
279 /* The instruction before prev_insn. */
280 static struct mips_cl_insn prev_prev_insn
;
282 /* If we don't want information for prev_insn or prev_prev_insn, we
283 point the insn_mo field at this dummy integer. */
284 static const struct mips_opcode dummy_opcode
= { 0 };
286 /* Non-zero if prev_insn is valid. */
287 static int prev_insn_valid
;
289 /* The frag for the previous instruction. */
290 static struct frag
*prev_insn_frag
;
292 /* The offset into prev_insn_frag for the previous instruction. */
293 static long prev_insn_where
;
295 /* The reloc for the previous instruction, if any. */
296 static fixS
*prev_insn_fixp
;
298 /* Non-zero if the previous instruction was in a delay slot. */
299 static int prev_insn_is_delay_slot
;
301 /* Non-zero if the previous instruction was in a .set noreorder. */
302 static int prev_insn_unreordered
;
304 /* Non-zero if the previous previous instruction was in a .set
306 static int prev_prev_insn_unreordered
;
308 /* For ECOFF and ELF, relocations against symbols are done in two
309 parts, with a HI relocation and a LO relocation. Each relocation
310 has only 16 bits of space to store an addend. This means that in
311 order for the linker to handle carries correctly, it must be able
312 to locate both the HI and the LO relocation. This means that the
313 relocations must appear in order in the relocation table.
315 In order to implement this, we keep track of each unmatched HI
316 relocation. We then sort them so that they immediately precede the
317 corresponding LO relocation. */
322 struct mips_hi_fixup
*next
;
325 /* The section this fixup is in. */
329 /* The list of unmatched HI relocs. */
331 static struct mips_hi_fixup
*mips_hi_fixup_list
;
333 /* Since the MIPS does not have multiple forms of PC relative
334 instructions, we do not have to do relaxing as is done on other
335 platforms. However, we do have to handle GP relative addressing
336 correctly, which turns out to be a similar problem.
338 Every macro that refers to a symbol can occur in (at least) two
339 forms, one with GP relative addressing and one without. For
340 example, loading a global variable into a register generally uses
341 a macro instruction like this:
343 If i can be addressed off the GP register (this is true if it is in
344 the .sbss or .sdata section, or if it is known to be smaller than
345 the -G argument) this will generate the following instruction:
347 This instruction will use a GPREL reloc. If i can not be addressed
348 off the GP register, the following instruction sequence will be used:
351 In this case the first instruction will have a HI16 reloc, and the
352 second reloc will have a LO16 reloc. Both relocs will be against
355 The issue here is that we may not know whether i is GP addressable
356 until after we see the instruction that uses it. Therefore, we
357 want to be able to choose the final instruction sequence only at
358 the end of the assembly. This is similar to the way other
359 platforms choose the size of a PC relative instruction only at the
362 When generating position independent code we do not use GP
363 addressing in quite the same way, but the issue still arises as
364 external symbols and local symbols must be handled differently.
366 We handle these issues by actually generating both possible
367 instruction sequences. The longer one is put in a frag_var with
368 type rs_machine_dependent. We encode what to do with the frag in
369 the subtype field. We encode (1) the number of existing bytes to
370 replace, (2) the number of new bytes to use, (3) the offset from
371 the start of the existing bytes to the first reloc we must generate
372 (that is, the offset is applied from the start of the existing
373 bytes after they are replaced by the new bytes, if any), (4) the
374 offset from the start of the existing bytes to the second reloc,
375 (5) whether a third reloc is needed (the third reloc is always four
376 bytes after the second reloc), and (6) whether to warn if this
377 variant is used (this is sometimes needed if .set nomacro or .set
378 noat is in effect). All these numbers are reasonably small.
380 Generating two instruction sequences must be handled carefully to
381 ensure that delay slots are handled correctly. Fortunately, there
382 are a limited number of cases. When the second instruction
383 sequence is generated, append_insn is directed to maintain the
384 existing delay slot information, so it continues to apply to any
385 code after the second instruction sequence. This means that the
386 second instruction sequence must not impose any requirements not
387 required by the first instruction sequence.
389 These variant frags are then handled in functions called by the
390 machine independent code. md_estimate_size_before_relax returns
391 the final size of the frag. md_convert_frag sets up the final form
392 of the frag. tc_gen_reloc adjust the first reloc and adds a second
394 #define RELAX_ENCODE(old, new, reloc1, reloc2, reloc3, warn) \
398 | (((reloc1) + 64) << 9) \
399 | (((reloc2) + 64) << 2) \
400 | ((reloc3) ? (1 << 1) : 0) \
402 #define RELAX_OLD(i) (((i) >> 24) & 0xff)
403 #define RELAX_NEW(i) (((i) >> 16) & 0xff)
404 #define RELAX_RELOC1(i) ((bfd_vma)(((i) >> 9) & 0x7f) - 64)
405 #define RELAX_RELOC2(i) ((bfd_vma)(((i) >> 2) & 0x7f) - 64)
406 #define RELAX_RELOC3(i) (((i) >> 1) & 1)
407 #define RELAX_WARN(i) ((i) & 1)
409 /* Prototypes for static functions. */
412 #define internalError() \
413 as_fatal ("internal Error, line %d, %s", __LINE__, __FILE__)
415 #define internalError() as_fatal ("MIPS internal Error");
418 static int insn_uses_reg
PARAMS ((struct mips_cl_insn
*ip
,
419 unsigned int reg
, int fpr
));
420 static int reg_needs_delay
PARAMS ((int));
421 static void append_insn
PARAMS ((char *place
,
422 struct mips_cl_insn
* ip
,
424 bfd_reloc_code_real_type r
,
426 static void mips_no_prev_insn
PARAMS ((void));
427 static void mips_emit_delays
PARAMS ((void));
429 static void macro_build
PARAMS ((char *place
, int *counter
, expressionS
* ep
,
430 const char *name
, const char *fmt
,
433 static void macro_build ();
435 static void macro_build_lui
PARAMS ((char *place
, int *counter
,
436 expressionS
* ep
, int regnum
));
437 static void set_at
PARAMS ((int *counter
, int reg
, int unsignedp
));
438 static void check_absolute_expr
PARAMS ((struct mips_cl_insn
* ip
,
440 static void load_register
PARAMS ((int *, int, expressionS
*, int));
441 static void load_address
PARAMS ((int *counter
, int reg
, expressionS
*ep
));
442 static void macro
PARAMS ((struct mips_cl_insn
* ip
));
443 #ifdef LOSING_COMPILER
444 static void macro2
PARAMS ((struct mips_cl_insn
* ip
));
446 static void mips_ip
PARAMS ((char *str
, struct mips_cl_insn
* ip
));
447 static int my_getSmallExpression
PARAMS ((expressionS
* ep
, char *str
));
448 static void my_getExpression
PARAMS ((expressionS
* ep
, char *str
));
449 static symbolS
*get_symbol
PARAMS ((void));
450 static void mips_align
PARAMS ((int to
, int fill
, symbolS
*label
));
451 static void s_align
PARAMS ((int));
452 static void s_change_sec
PARAMS ((int));
453 static void s_cons
PARAMS ((int));
454 static void s_float_cons
PARAMS ((int));
455 static void s_mips_globl
PARAMS ((int));
456 static void s_option
PARAMS ((int));
457 static void s_mipsset
PARAMS ((int));
458 static void s_abicalls
PARAMS ((int));
459 static void s_cpload
PARAMS ((int));
460 static void s_cprestore
PARAMS ((int));
461 static void s_gpword
PARAMS ((int));
462 static void s_cpadd
PARAMS ((int));
463 static void md_obj_begin
PARAMS ((void));
464 static void md_obj_end
PARAMS ((void));
465 static long get_number
PARAMS ((void));
466 static void s_ent
PARAMS ((int));
467 static void s_mipsend
PARAMS ((int));
468 static void s_file
PARAMS ((int));
472 The following pseudo-ops from the Kane and Heinrich MIPS book
473 should be defined here, but are currently unsupported: .alias,
474 .galive, .gjaldef, .gjrlive, .livereg, .noalias.
476 The following pseudo-ops from the Kane and Heinrich MIPS book are
477 specific to the type of debugging information being generated, and
478 should be defined by the object format: .aent, .begin, .bend,
479 .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp,
482 The following pseudo-ops from the Kane and Heinrich MIPS book are
483 not MIPS CPU specific, but are also not specific to the object file
484 format. This file is probably the best place to define them, but
485 they are not currently supported: .asm0, .endr, .lab, .repeat,
486 .struct, .weakext. */
488 static const pseudo_typeS mips_pseudo_table
[] =
490 /* MIPS specific pseudo-ops. */
491 {"option", s_option
, 0},
492 {"set", s_mipsset
, 0},
493 {"rdata", s_change_sec
, 'r'},
494 {"sdata", s_change_sec
, 's'},
495 {"livereg", s_ignore
, 0},
496 {"abicalls", s_abicalls
, 0},
497 {"cpload", s_cpload
, 0},
498 {"cprestore", s_cprestore
, 0},
499 {"gpword", s_gpword
, 0},
500 {"cpadd", s_cpadd
, 0},
502 /* Relatively generic pseudo-ops that happen to be used on MIPS
504 {"asciiz", stringer
, 1},
505 {"bss", s_change_sec
, 'b'},
508 {"dword", s_cons
, 3},
510 /* These pseudo-ops are defined in read.c, but must be overridden
511 here for one reason or another. */
512 {"align", s_align
, 0},
514 {"data", s_change_sec
, 'd'},
515 {"double", s_float_cons
, 'd'},
516 {"float", s_float_cons
, 'f'},
517 {"globl", s_mips_globl
, 0},
518 {"global", s_mips_globl
, 0},
519 {"hword", s_cons
, 1},
524 {"short", s_cons
, 1},
525 {"single", s_float_cons
, 'f'},
526 {"text", s_change_sec
, 't'},
531 static const pseudo_typeS mips_nonecoff_pseudo_table
[] = {
532 /* These pseudo-ops should be defined by the object file format.
533 However, a.out doesn't support them, so we have versions here. */
535 {"bgnb", s_ignore
, 0},
536 {"end", s_mipsend
, 0},
537 {"endb", s_ignore
, 0},
540 {"fmask", s_ignore
, 'F'},
541 {"frame", s_ignore
, 0},
542 {"loc", s_ignore
, 0},
543 {"mask", s_ignore
, 'R'},
544 {"verstamp", s_ignore
, 0},
548 extern void pop_insert
PARAMS ((const pseudo_typeS
*));
553 pop_insert (mips_pseudo_table
);
554 if (! ECOFF_DEBUGGING
)
555 pop_insert (mips_nonecoff_pseudo_table
);
558 static char *expr_end
;
560 /* Expressions which appear in instructions. These are set by
563 static expressionS imm_expr
;
564 static expressionS offset_expr
;
566 /* Relocs associated with imm_expr and offset_expr. */
568 static bfd_reloc_code_real_type imm_reloc
;
569 static bfd_reloc_code_real_type offset_reloc
;
571 /* This is set by mips_ip if imm_reloc is an unmatched HI16_S reloc. */
573 static boolean imm_unmatched_hi
;
576 * This function is called once, at assembler startup time. It should
577 * set up all the tables, etc. that the MD part of the assembler will need.
583 register const char *retval
= NULL
;
584 register unsigned int i
= 0;
592 if (strcmp (cpu
+ (sizeof TARGET_CPU
) - 3, "el") == 0)
594 a
= xmalloc (sizeof TARGET_CPU
);
595 strcpy (a
, TARGET_CPU
);
596 a
[(sizeof TARGET_CPU
) - 3] = '\0';
600 if (strcmp (cpu
, "mips") == 0)
606 else if (strcmp (cpu
, "r6000") == 0
607 || strcmp (cpu
, "mips2") == 0)
613 else if (strcmp (cpu
, "mips64") == 0
614 || strcmp (cpu
, "r4000") == 0
615 || strcmp (cpu
, "mips3") == 0)
621 else if (strcmp (cpu
, "r4400") == 0)
627 else if (strcmp (cpu
, "mips64orion") == 0
628 || strcmp (cpu
, "r4600") == 0)
634 else if (strcmp (cpu
, "r4650") == 0)
642 else if (strcmp (cpu
, "mips64vr4300") == 0)
648 else if (strcmp (cpu
, "mips64vr4100") == 0)
656 else if (strcmp (cpu
, "r4010") == 0)
664 else if (strcmp (cpu
, "r5000") == 0
665 || strcmp (cpu
, "mips64vr5000") == 0)
671 else if (strcmp (cpu
, "r8000") == 0
672 || strcmp (cpu
, "mips4") == 0)
678 else if (strcmp (cpu
, "r10000") == 0)
713 if (mips_cpu
== 4300 || mips_cpu
== 5000)
718 if (mips_isa
< 2 && mips_trap
)
719 as_bad ("trap exception not supported at ISA 1");
724 ok
= bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, 3000);
727 ok
= bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, 6000);
730 ok
= bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, 4000);
733 ok
= bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, 8000);
737 as_warn ("Could not set architecture and machine");
739 file_mips_isa
= mips_isa
;
741 op_hash
= hash_new ();
743 for (i
= 0; i
< NUMOPCODES
;)
745 const char *name
= mips_opcodes
[i
].name
;
747 retval
= hash_insert (op_hash
, name
, (PTR
) &mips_opcodes
[i
]);
750 fprintf (stderr
, "internal error: can't hash `%s': %s\n",
751 mips_opcodes
[i
].name
, retval
);
752 as_fatal ("Broken assembler. No assembly attempted.");
756 if (mips_opcodes
[i
].pinfo
!= INSN_MACRO
757 && ((mips_opcodes
[i
].match
& mips_opcodes
[i
].mask
)
758 != mips_opcodes
[i
].match
))
760 fprintf (stderr
, "internal error: bad opcode: `%s' \"%s\"\n",
761 mips_opcodes
[i
].name
, mips_opcodes
[i
].args
);
762 as_fatal ("Broken assembler. No assembly attempted.");
766 while ((i
< NUMOPCODES
) && !strcmp (mips_opcodes
[i
].name
, name
));
769 mips_no_prev_insn ();
777 /* set the default alignment for the text section (2**2) */
778 record_alignment (text_section
, 2);
780 if (USE_GLOBAL_POINTER_OPT
)
781 bfd_set_gp_size (stdoutput
, g_switch_value
);
783 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
785 /* Sections must be aligned to 16 byte boundaries. */
786 (void) bfd_set_section_alignment (stdoutput
, text_section
, 4);
787 (void) bfd_set_section_alignment (stdoutput
, data_section
, 4);
788 (void) bfd_set_section_alignment (stdoutput
, bss_section
, 4);
790 /* Create a .reginfo section for register masks and a .mdebug
791 section for debugging information. */
802 sec
= subseg_new (".reginfo", (subsegT
) 0);
804 /* The ABI says this section should be loaded so that the
805 running program can access it. */
806 (void) bfd_set_section_flags (stdoutput
, sec
,
807 (SEC_ALLOC
| SEC_LOAD
808 | SEC_READONLY
| SEC_DATA
));
809 (void) bfd_set_section_alignment (stdoutput
, sec
, 2);
812 mips_regmask_frag
= frag_more (sizeof (Elf32_External_RegInfo
));
817 /* The 64-bit ABI uses a .MIPS.options section rather than
819 sec
= subseg_new (".MIPS.options", (subsegT
) 0);
820 (void) bfd_set_section_flags (stdoutput
, sec
,
821 (SEC_ALLOC
| SEC_LOAD
822 | SEC_READONLY
| SEC_DATA
));
823 (void) bfd_set_section_alignment (stdoutput
, sec
, 3);
826 /* Set up the option header. */
828 Elf_Internal_Options opthdr
;
831 opthdr
.kind
= ODK_REGINFO
;
832 opthdr
.size
= (sizeof (Elf_External_Options
)
833 + sizeof (Elf64_External_RegInfo
));
836 f
= frag_more (sizeof (Elf_External_Options
));
837 bfd_mips_elf_swap_options_out (stdoutput
, &opthdr
,
838 (Elf_External_Options
*) f
);
840 mips_regmask_frag
= frag_more (sizeof (Elf64_External_RegInfo
));
847 sec
= subseg_new (".mdebug", (subsegT
) 0);
848 (void) bfd_set_section_flags (stdoutput
, sec
,
849 SEC_HAS_CONTENTS
| SEC_READONLY
);
850 (void) bfd_set_section_alignment (stdoutput
, sec
, 2);
853 subseg_set (seg
, subseg
);
857 if (! ECOFF_DEBUGGING
)
864 if (! ECOFF_DEBUGGING
)
872 struct mips_cl_insn insn
;
874 imm_expr
.X_op
= O_absent
;
875 imm_reloc
= BFD_RELOC_UNUSED
;
876 imm_unmatched_hi
= false;
877 offset_expr
.X_op
= O_absent
;
878 offset_reloc
= BFD_RELOC_UNUSED
;
880 mips_ip (str
, &insn
);
883 as_bad ("%s `%s'", insn_error
, str
);
886 if (insn
.insn_mo
->pinfo
== INSN_MACRO
)
892 if (imm_expr
.X_op
!= O_absent
)
893 append_insn ((char *) NULL
, &insn
, &imm_expr
, imm_reloc
,
895 else if (offset_expr
.X_op
!= O_absent
)
896 append_insn ((char *) NULL
, &insn
, &offset_expr
, offset_reloc
, false);
898 append_insn ((char *) NULL
, &insn
, NULL
, BFD_RELOC_UNUSED
, false);
902 /* See whether instruction IP reads register REG. If FPR is non-zero,
903 REG is a floating point register. */
906 insn_uses_reg (ip
, reg
, fpr
)
907 struct mips_cl_insn
*ip
;
911 /* Don't report on general register 0, since it never changes. */
912 if (! fpr
&& reg
== 0)
917 /* If we are called with either $f0 or $f1, we must check $f0.
918 This is not optimal, because it will introduce an unnecessary
919 NOP between "lwc1 $f0" and "swc1 $f1". To fix this we would
920 need to distinguish reading both $f0 and $f1 or just one of
921 them. Note that we don't have to check the other way,
922 because there is no instruction that sets both $f0 and $f1
923 and requires a delay. */
924 if ((ip
->insn_mo
->pinfo
& INSN_READ_FPR_S
)
925 && (((ip
->insn_opcode
>> OP_SH_FS
) & OP_MASK_FS
)
926 == (reg
&~ (unsigned) 1)))
928 if ((ip
->insn_mo
->pinfo
& INSN_READ_FPR_T
)
929 && (((ip
->insn_opcode
>> OP_SH_FT
) & OP_MASK_FT
)
930 == (reg
&~ (unsigned) 1)))
935 if ((ip
->insn_mo
->pinfo
& INSN_READ_GPR_S
)
936 && ((ip
->insn_opcode
>> OP_SH_RS
) & OP_MASK_RS
) == reg
)
938 if ((ip
->insn_mo
->pinfo
& INSN_READ_GPR_T
)
939 && ((ip
->insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
) == reg
)
946 /* This function returns true if modifying a register requires a
950 reg_needs_delay (reg
)
953 unsigned long prev_pinfo
;
955 prev_pinfo
= prev_insn
.insn_mo
->pinfo
;
958 && ((prev_pinfo
& INSN_LOAD_COPROC_DELAY
)
960 && (prev_pinfo
& INSN_LOAD_MEMORY_DELAY
))))
962 /* A load from a coprocessor or from memory. All load
963 delays delay the use of general register rt for one
964 instruction on the r3000. The r6000 and r4000 use
966 know (prev_pinfo
& INSN_WRITE_GPR_T
);
967 if (reg
== ((prev_insn
.insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
))
974 /* Output an instruction. PLACE is where to put the instruction; if
975 it is NULL, this uses frag_more to get room. IP is the instruction
976 information. ADDRESS_EXPR is an operand of the instruction to be
977 used with RELOC_TYPE. */
980 append_insn (place
, ip
, address_expr
, reloc_type
, unmatched_hi
)
982 struct mips_cl_insn
*ip
;
983 expressionS
*address_expr
;
984 bfd_reloc_code_real_type reloc_type
;
985 boolean unmatched_hi
;
987 register unsigned long prev_pinfo
, pinfo
;
992 prev_pinfo
= prev_insn
.insn_mo
->pinfo
;
993 pinfo
= ip
->insn_mo
->pinfo
;
995 if (place
== NULL
&& ! mips_noreorder
)
997 /* If the previous insn required any delay slots, see if we need
998 to insert a NOP or two. There are eight kinds of possible
999 hazards, of which an instruction can have at most one type.
1000 (1) a load from memory delay
1001 (2) a load from a coprocessor delay
1002 (3) an unconditional branch delay
1003 (4) a conditional branch delay
1004 (5) a move to coprocessor register delay
1005 (6) a load coprocessor register from memory delay
1006 (7) a coprocessor condition code delay
1007 (8) a HI/LO special register delay
1009 There are a lot of optimizations we could do that we don't.
1010 In particular, we do not, in general, reorder instructions.
1011 If you use gcc with optimization, it will reorder
1012 instructions and generally do much more optimization then we
1013 do here; repeating all that work in the assembler would only
1014 benefit hand written assembly code, and does not seem worth
1017 /* This is how a NOP is emitted. */
1018 #define emit_nop() md_number_to_chars (frag_more (4), 0, 4)
1020 /* The previous insn might require a delay slot, depending upon
1021 the contents of the current insn. */
1023 && (((prev_pinfo
& INSN_LOAD_COPROC_DELAY
)
1024 && ! cop_interlocks
)
1026 && (prev_pinfo
& INSN_LOAD_MEMORY_DELAY
))))
1028 /* A load from a coprocessor or from memory. All load
1029 delays delay the use of general register rt for one
1030 instruction on the r3000. The r6000 and r4000 use
1032 know (prev_pinfo
& INSN_WRITE_GPR_T
);
1033 if (mips_optimize
== 0
1034 || insn_uses_reg (ip
,
1035 ((prev_insn
.insn_opcode
>> OP_SH_RT
)
1040 else if (mips_isa
< 4
1041 && (((prev_pinfo
& INSN_COPROC_MOVE_DELAY
)
1042 && ! cop_interlocks
)
1044 && (prev_pinfo
& INSN_COPROC_MEMORY_DELAY
))))
1046 /* A generic coprocessor delay. The previous instruction
1047 modified a coprocessor general or control register. If
1048 it modified a control register, we need to avoid any
1049 coprocessor instruction (this is probably not always
1050 required, but it sometimes is). If it modified a general
1051 register, we avoid using that register.
1053 On the r6000 and r4000 loading a coprocessor register
1054 from memory is interlocked, and does not require a delay.
1056 This case is not handled very well. There is no special
1057 knowledge of CP0 handling, and the coprocessors other
1058 than the floating point unit are not distinguished at
1060 if (prev_pinfo
& INSN_WRITE_FPR_T
)
1062 if (mips_optimize
== 0
1063 || insn_uses_reg (ip
,
1064 ((prev_insn
.insn_opcode
>> OP_SH_FT
)
1069 else if (prev_pinfo
& INSN_WRITE_FPR_S
)
1071 if (mips_optimize
== 0
1072 || insn_uses_reg (ip
,
1073 ((prev_insn
.insn_opcode
>> OP_SH_FS
)
1080 /* We don't know exactly what the previous instruction
1081 does. If the current instruction uses a coprocessor
1082 register, we must insert a NOP. If previous
1083 instruction may set the condition codes, and the
1084 current instruction uses them, we must insert two
1086 if (mips_optimize
== 0
1087 || ((prev_pinfo
& INSN_WRITE_COND_CODE
)
1088 && (pinfo
& INSN_READ_COND_CODE
)))
1090 else if (pinfo
& INSN_COP
)
1094 else if (mips_isa
< 4
1095 && (prev_pinfo
& INSN_WRITE_COND_CODE
)
1096 && ! cop_interlocks
)
1098 /* The previous instruction sets the coprocessor condition
1099 codes, but does not require a general coprocessor delay
1100 (this means it is a floating point comparison
1101 instruction). If this instruction uses the condition
1102 codes, we need to insert a single NOP. */
1103 if (mips_optimize
== 0
1104 || (pinfo
& INSN_READ_COND_CODE
))
1107 else if (prev_pinfo
& INSN_READ_LO
)
1109 /* The previous instruction reads the LO register; if the
1110 current instruction writes to the LO register, we must
1111 insert two NOPS. Some newer processors have interlocks. */
1113 && (mips_optimize
== 0
1114 || (pinfo
& INSN_WRITE_LO
)))
1117 else if (prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
1119 /* The previous instruction reads the HI register; if the
1120 current instruction writes to the HI register, we must
1121 insert a NOP. Some newer processors have interlocks. */
1123 && (mips_optimize
== 0
1124 || (pinfo
& INSN_WRITE_HI
)))
1128 /* There are two cases which require two intervening
1129 instructions: 1) setting the condition codes using a move to
1130 coprocessor instruction which requires a general coprocessor
1131 delay and then reading the condition codes 2) reading the HI
1132 or LO register and then writing to it (except on processors
1133 which have interlocks). If we are not already emitting a NOP
1134 instruction, we must check for these cases compared to the
1135 instruction previous to the previous instruction. */
1138 && (prev_prev_insn
.insn_mo
->pinfo
& INSN_COPROC_MOVE_DELAY
)
1139 && (prev_prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
)
1140 && (pinfo
& INSN_READ_COND_CODE
)
1141 && ! cop_interlocks
)
1142 || ((prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
)
1143 && (pinfo
& INSN_WRITE_LO
)
1145 || ((prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
1146 && (pinfo
& INSN_WRITE_HI
)
1150 /* If we are being given a nop instruction, don't bother with
1151 one of the nops we would otherwise output. This will only
1152 happen when a nop instruction is used with mips_optimize set
1154 if (nops
> 0 && ip
->insn_opcode
== 0)
1157 /* Now emit the right number of NOP instructions. */
1161 unsigned long old_frag_offset
;
1164 old_frag
= frag_now
;
1165 old_frag_offset
= frag_now_fix ();
1167 for (i
= 0; i
< nops
; i
++)
1172 listing_prev_line ();
1173 /* We may be at the start of a variant frag. In case we
1174 are, make sure there is enough space for the frag
1175 after the frags created by listing_prev_line. The
1176 argument to frag_grow here must be at least as large
1177 as the argument to all other calls to frag_grow in
1178 this file. We don't have to worry about being in the
1179 middle of a variant frag, because the variants insert
1180 all needed nop instructions themselves. */
1184 if (insn_label
!= NULL
)
1186 assert (S_GET_SEGMENT (insn_label
) == now_seg
);
1187 insn_label
->sy_frag
= frag_now
;
1188 S_SET_VALUE (insn_label
, (valueT
) frag_now_fix ());
1191 #ifndef NO_ECOFF_DEBUGGING
1192 if (ECOFF_DEBUGGING
)
1193 ecoff_fix_loc (old_frag
, old_frag_offset
);
1203 if (address_expr
!= NULL
)
1205 if (address_expr
->X_op
== O_constant
)
1210 ip
->insn_opcode
|= address_expr
->X_add_number
;
1213 case BFD_RELOC_LO16
:
1214 ip
->insn_opcode
|= address_expr
->X_add_number
& 0xffff;
1217 case BFD_RELOC_MIPS_JMP
:
1218 case BFD_RELOC_16_PCREL_S2
:
1227 assert (reloc_type
!= BFD_RELOC_UNUSED
);
1229 /* Don't generate a reloc if we are writing into a variant
1233 fixp
= fix_new_exp (frag_now
, f
- frag_now
->fr_literal
, 4,
1235 reloc_type
== BFD_RELOC_16_PCREL_S2
,
1239 struct mips_hi_fixup
*hi_fixup
;
1241 assert (reloc_type
== BFD_RELOC_HI16_S
);
1242 hi_fixup
= ((struct mips_hi_fixup
*)
1243 xmalloc (sizeof (struct mips_hi_fixup
)));
1244 hi_fixup
->fixp
= fixp
;
1245 hi_fixup
->seg
= now_seg
;
1246 hi_fixup
->next
= mips_hi_fixup_list
;
1247 mips_hi_fixup_list
= hi_fixup
;
1253 md_number_to_chars (f
, ip
->insn_opcode
, 4);
1255 /* Update the register mask information. */
1256 if (pinfo
& INSN_WRITE_GPR_D
)
1257 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
);
1258 if ((pinfo
& (INSN_WRITE_GPR_T
| INSN_READ_GPR_T
)) != 0)
1259 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
);
1260 if (pinfo
& INSN_READ_GPR_S
)
1261 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> OP_SH_RS
) & OP_MASK_RS
);
1262 if (pinfo
& INSN_WRITE_GPR_31
)
1263 mips_gprmask
|= 1 << 31;
1264 if (pinfo
& INSN_WRITE_FPR_D
)
1265 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FD
) & OP_MASK_FD
);
1266 if ((pinfo
& (INSN_WRITE_FPR_S
| INSN_READ_FPR_S
)) != 0)
1267 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FS
) & OP_MASK_FS
);
1268 if ((pinfo
& (INSN_WRITE_FPR_T
| INSN_READ_FPR_T
)) != 0)
1269 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FT
) & OP_MASK_FT
);
1270 if ((pinfo
& INSN_READ_FPR_R
) != 0)
1271 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FR
) & OP_MASK_FR
);
1272 if (pinfo
& INSN_COP
)
1274 /* We don't keep enough information to sort these cases out. */
1276 /* Never set the bit for $0, which is always zero. */
1277 mips_gprmask
&=~ 1 << 0;
1279 if (place
== NULL
&& ! mips_noreorder
)
1281 /* Filling the branch delay slot is more complex. We try to
1282 switch the branch with the previous instruction, which we can
1283 do if the previous instruction does not set up a condition
1284 that the branch tests and if the branch is not itself the
1285 target of any branch. */
1286 if ((pinfo
& INSN_UNCOND_BRANCH_DELAY
)
1287 || (pinfo
& INSN_COND_BRANCH_DELAY
))
1289 if (mips_optimize
< 2
1290 /* If we have seen .set volatile or .set nomove, don't
1293 /* If we had to emit any NOP instructions, then we
1294 already know we can not swap. */
1296 /* If we don't even know the previous insn, we can not
1298 || ! prev_insn_valid
1299 /* If the previous insn is already in a branch delay
1300 slot, then we can not swap. */
1301 || prev_insn_is_delay_slot
1302 /* If the previous previous insn was in a .set
1303 noreorder, we can't swap. Actually, the MIPS
1304 assembler will swap in this situation. However, gcc
1305 configured -with-gnu-as will generate code like
1311 in which we can not swap the bne and INSN. If gcc is
1312 not configured -with-gnu-as, it does not output the
1313 .set pseudo-ops. We don't have to check
1314 prev_insn_unreordered, because prev_insn_valid will
1315 be 0 in that case. We don't want to use
1316 prev_prev_insn_valid, because we do want to be able
1317 to swap at the start of a function. */
1318 || prev_prev_insn_unreordered
1319 /* If the branch is itself the target of a branch, we
1320 can not swap. We cheat on this; all we check for is
1321 whether there is a label on this instruction. If
1322 there are any branches to anything other than a
1323 label, users must use .set noreorder. */
1324 || insn_label
!= NULL
1325 /* If the previous instruction is in a variant frag, we
1326 can not do the swap. */
1327 || prev_insn_frag
->fr_type
== rs_machine_dependent
1328 /* If the branch reads the condition codes, we don't
1329 even try to swap, because in the sequence
1334 we can not swap, and I don't feel like handling that
1337 && (pinfo
& INSN_READ_COND_CODE
))
1338 /* We can not swap with an instruction that requires a
1339 delay slot, becase the target of the branch might
1340 interfere with that instruction. */
1343 & (INSN_LOAD_COPROC_DELAY
1344 | INSN_COPROC_MOVE_DELAY
1345 | INSN_WRITE_COND_CODE
)))
1352 & (INSN_LOAD_MEMORY_DELAY
1353 | INSN_COPROC_MEMORY_DELAY
)))
1354 /* We can not swap with a branch instruction. */
1356 & (INSN_UNCOND_BRANCH_DELAY
1357 | INSN_COND_BRANCH_DELAY
1358 | INSN_COND_BRANCH_LIKELY
))
1359 /* We do not swap with a trap instruction, since it
1360 complicates trap handlers to have the trap
1361 instruction be in a delay slot. */
1362 || (prev_pinfo
& INSN_TRAP
)
1363 /* If the branch reads a register that the previous
1364 instruction sets, we can not swap. */
1365 || ((prev_pinfo
& INSN_WRITE_GPR_T
)
1366 && insn_uses_reg (ip
,
1367 ((prev_insn
.insn_opcode
>> OP_SH_RT
)
1370 || ((prev_pinfo
& INSN_WRITE_GPR_D
)
1371 && insn_uses_reg (ip
,
1372 ((prev_insn
.insn_opcode
>> OP_SH_RD
)
1375 /* If the branch writes a register that the previous
1376 instruction sets, we can not swap (we know that
1377 branches write only to RD or to $31). */
1378 || ((prev_pinfo
& INSN_WRITE_GPR_T
)
1379 && (((pinfo
& INSN_WRITE_GPR_D
)
1380 && (((prev_insn
.insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
)
1381 == ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)))
1382 || ((pinfo
& INSN_WRITE_GPR_31
)
1383 && (((prev_insn
.insn_opcode
>> OP_SH_RT
)
1386 || ((prev_pinfo
& INSN_WRITE_GPR_D
)
1387 && (((pinfo
& INSN_WRITE_GPR_D
)
1388 && (((prev_insn
.insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)
1389 == ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)))
1390 || ((pinfo
& INSN_WRITE_GPR_31
)
1391 && (((prev_insn
.insn_opcode
>> OP_SH_RD
)
1394 /* If the branch writes a register that the previous
1395 instruction reads, we can not swap (we know that
1396 branches only write to RD or to $31). */
1397 || ((pinfo
& INSN_WRITE_GPR_D
)
1398 && insn_uses_reg (&prev_insn
,
1399 ((ip
->insn_opcode
>> OP_SH_RD
)
1402 || ((pinfo
& INSN_WRITE_GPR_31
)
1403 && insn_uses_reg (&prev_insn
, 31, 0))
1404 /* If we are generating embedded PIC code, the branch
1405 might be expanded into a sequence which uses $at, so
1406 we can't swap with an instruction which reads it. */
1407 || (mips_pic
== EMBEDDED_PIC
1408 && insn_uses_reg (&prev_insn
, AT
, 0))
1409 /* If the previous previous instruction has a load
1410 delay, and sets a register that the branch reads, we
1413 && ((prev_prev_insn
.insn_mo
->pinfo
& INSN_LOAD_COPROC_DELAY
)
1415 && (prev_prev_insn
.insn_mo
->pinfo
1416 & INSN_LOAD_MEMORY_DELAY
)))
1417 && insn_uses_reg (ip
,
1418 ((prev_prev_insn
.insn_opcode
>> OP_SH_RT
)
1422 /* We could do even better for unconditional branches to
1423 portions of this object file; we could pick up the
1424 instruction at the destination, put it in the delay
1425 slot, and bump the destination address. */
1427 /* Update the previous insn information. */
1428 prev_prev_insn
= *ip
;
1429 prev_insn
.insn_mo
= &dummy_opcode
;
1436 /* It looks like we can actually do the swap. */
1437 prev_f
= prev_insn_frag
->fr_literal
+ prev_insn_where
;
1438 memcpy (temp
, prev_f
, 4);
1439 memcpy (prev_f
, f
, 4);
1440 memcpy (f
, temp
, 4);
1443 prev_insn_fixp
->fx_frag
= frag_now
;
1444 prev_insn_fixp
->fx_where
= f
- frag_now
->fr_literal
;
1448 fixp
->fx_frag
= prev_insn_frag
;
1449 fixp
->fx_where
= prev_insn_where
;
1451 /* Update the previous insn information; leave prev_insn
1453 prev_prev_insn
= *ip
;
1455 prev_insn_is_delay_slot
= 1;
1457 /* If that was an unconditional branch, forget the previous
1458 insn information. */
1459 if (pinfo
& INSN_UNCOND_BRANCH_DELAY
)
1461 prev_prev_insn
.insn_mo
= &dummy_opcode
;
1462 prev_insn
.insn_mo
= &dummy_opcode
;
1465 else if (pinfo
& INSN_COND_BRANCH_LIKELY
)
1467 /* We don't yet optimize a branch likely. What we should do
1468 is look at the target, copy the instruction found there
1469 into the delay slot, and increment the branch to jump to
1470 the next instruction. */
1472 /* Update the previous insn information. */
1473 prev_prev_insn
= *ip
;
1474 prev_insn
.insn_mo
= &dummy_opcode
;
1478 /* Update the previous insn information. */
1480 prev_prev_insn
.insn_mo
= &dummy_opcode
;
1482 prev_prev_insn
= prev_insn
;
1485 /* Any time we see a branch, we always fill the delay slot
1486 immediately; since this insn is not a branch, we know it
1487 is not in a delay slot. */
1488 prev_insn_is_delay_slot
= 0;
1491 prev_prev_insn_unreordered
= prev_insn_unreordered
;
1492 prev_insn_unreordered
= 0;
1493 prev_insn_frag
= frag_now
;
1494 prev_insn_where
= f
- frag_now
->fr_literal
;
1495 prev_insn_fixp
= fixp
;
1496 prev_insn_valid
= 1;
1499 /* We just output an insn, so the next one doesn't have a label. */
1503 /* This function forgets that there was any previous instruction or
1507 mips_no_prev_insn ()
1509 prev_insn
.insn_mo
= &dummy_opcode
;
1510 prev_prev_insn
.insn_mo
= &dummy_opcode
;
1511 prev_insn_valid
= 0;
1512 prev_insn_is_delay_slot
= 0;
1513 prev_insn_unreordered
= 0;
1514 prev_prev_insn_unreordered
= 0;
1518 /* This function must be called whenever we turn on noreorder or emit
1519 something other than instructions. It inserts any NOPS which might
1520 be needed by the previous instruction, and clears the information
1521 kept for the previous instructions. */
1526 if (! mips_noreorder
)
1532 && (! cop_interlocks
1533 && (prev_insn
.insn_mo
->pinfo
1534 & (INSN_LOAD_COPROC_DELAY
1535 | INSN_COPROC_MOVE_DELAY
1536 | INSN_WRITE_COND_CODE
))))
1538 && (prev_insn
.insn_mo
->pinfo
1542 && (prev_insn
.insn_mo
->pinfo
1543 & (INSN_LOAD_MEMORY_DELAY
1544 | INSN_COPROC_MEMORY_DELAY
))))
1548 && (! cop_interlocks
1549 && prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
))
1551 && ((prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
1552 || (prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
))))
1555 else if ((mips_isa
< 4
1556 && (! cop_interlocks
1557 && prev_prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
))
1559 && ((prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
1560 || (prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
))))
1565 if (insn_label
!= NULL
)
1567 assert (S_GET_SEGMENT (insn_label
) == now_seg
);
1568 insn_label
->sy_frag
= frag_now
;
1569 S_SET_VALUE (insn_label
, (valueT
) frag_now_fix ());
1574 mips_no_prev_insn ();
1577 /* Build an instruction created by a macro expansion. This is passed
1578 a pointer to the count of instructions created so far, an
1579 expression, the name of the instruction to build, an operand format
1580 string, and corresponding arguments. */
1584 macro_build (char *place
,
1592 macro_build (place
, counter
, ep
, name
, fmt
, va_alist
)
1601 struct mips_cl_insn insn
;
1602 bfd_reloc_code_real_type r
;
1606 va_start (args
, fmt
);
1612 * If the macro is about to expand into a second instruction,
1613 * print a warning if needed. We need to pass ip as a parameter
1614 * to generate a better warning message here...
1616 if (mips_warn_about_macros
&& place
== NULL
&& *counter
== 1)
1617 as_warn ("Macro instruction expanded into multiple instructions");
1620 *counter
+= 1; /* bump instruction counter */
1622 r
= BFD_RELOC_UNUSED
;
1623 insn
.insn_mo
= (struct mips_opcode
*) hash_find (op_hash
, name
);
1624 assert (insn
.insn_mo
);
1625 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
1627 while (strcmp (fmt
, insn
.insn_mo
->args
) != 0
1628 || insn
.insn_mo
->pinfo
== INSN_MACRO
1629 || ((insn
.insn_mo
->pinfo
& INSN_ISA
) == INSN_ISA2
1631 || ((insn
.insn_mo
->pinfo
& INSN_ISA
) == INSN_ISA3
1633 || ((insn
.insn_mo
->pinfo
& INSN_ISA
) == INSN_ISA4
1635 || ((insn
.insn_mo
->pinfo
& INSN_ISA
) == INSN_4650
1637 || ((insn
.insn_mo
->pinfo
& INSN_ISA
) == INSN_4010
1639 || ((insn
.insn_mo
->pinfo
& INSN_ISA
) == INSN_4100
1643 assert (insn
.insn_mo
->name
);
1644 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
1646 insn
.insn_opcode
= insn
.insn_mo
->match
;
1662 insn
.insn_opcode
|= va_arg (args
, int) << 16;
1668 insn
.insn_opcode
|= va_arg (args
, int) << 16;
1673 insn
.insn_opcode
|= va_arg (args
, int) << 11;
1678 insn
.insn_opcode
|= va_arg (args
, int) << 11;
1685 insn
.insn_opcode
|= va_arg (args
, int) << 6;
1689 insn
.insn_opcode
|= va_arg (args
, int) << 6;
1693 insn
.insn_opcode
|= va_arg (args
, int) << 6;
1700 insn
.insn_opcode
|= va_arg (args
, int) << 21;
1706 r
= (bfd_reloc_code_real_type
) va_arg (args
, int);
1707 assert (r
== BFD_RELOC_MIPS_GPREL
1708 || r
== BFD_RELOC_MIPS_LITERAL
1709 || r
== BFD_RELOC_LO16
1710 || r
== BFD_RELOC_MIPS_GOT16
1711 || r
== BFD_RELOC_MIPS_CALL16
1712 || r
== BFD_RELOC_MIPS_GOT_LO16
1713 || r
== BFD_RELOC_MIPS_CALL_LO16
1714 || (ep
->X_op
== O_subtract
1715 && now_seg
== text_section
1716 && r
== BFD_RELOC_PCREL_LO16
));
1720 r
= (bfd_reloc_code_real_type
) va_arg (args
, int);
1722 && (ep
->X_op
== O_constant
1723 || (ep
->X_op
== O_symbol
1724 && (r
== BFD_RELOC_HI16_S
1725 || r
== BFD_RELOC_HI16
1726 || r
== BFD_RELOC_MIPS_GOT_HI16
1727 || r
== BFD_RELOC_MIPS_CALL_HI16
))
1728 || (ep
->X_op
== O_subtract
1729 && now_seg
== text_section
1730 && r
== BFD_RELOC_PCREL_HI16_S
)));
1731 if (ep
->X_op
== O_constant
)
1733 insn
.insn_opcode
|= (ep
->X_add_number
>> 16) & 0xffff;
1735 r
= BFD_RELOC_UNUSED
;
1740 assert (ep
!= NULL
);
1742 * This allows macro() to pass an immediate expression for
1743 * creating short branches without creating a symbol.
1744 * Note that the expression still might come from the assembly
1745 * input, in which case the value is not checked for range nor
1746 * is a relocation entry generated (yuck).
1748 if (ep
->X_op
== O_constant
)
1750 insn
.insn_opcode
|= (ep
->X_add_number
>> 2) & 0xffff;
1754 r
= BFD_RELOC_16_PCREL_S2
;
1758 assert (ep
!= NULL
);
1759 r
= BFD_RELOC_MIPS_JMP
;
1768 assert (r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
1770 append_insn (place
, &insn
, ep
, r
, false);
1774 * Generate a "lui" instruction.
1777 macro_build_lui (place
, counter
, ep
, regnum
)
1783 expressionS high_expr
;
1784 struct mips_cl_insn insn
;
1785 bfd_reloc_code_real_type r
;
1786 CONST
char *name
= "lui";
1787 CONST
char *fmt
= "t,u";
1793 high_expr
.X_op
= O_constant
;
1794 high_expr
.X_add_number
= ep
->X_add_number
;
1797 if (high_expr
.X_op
== O_constant
)
1799 /* we can compute the instruction now without a relocation entry */
1800 if (high_expr
.X_add_number
& 0x8000)
1801 high_expr
.X_add_number
+= 0x10000;
1802 high_expr
.X_add_number
=
1803 ((unsigned long) high_expr
.X_add_number
>> 16) & 0xffff;
1804 r
= BFD_RELOC_UNUSED
;
1808 assert (ep
->X_op
== O_symbol
);
1809 /* _gp_disp is a special case, used from s_cpload. */
1810 assert (mips_pic
== NO_PIC
1811 || strcmp (S_GET_NAME (ep
->X_add_symbol
), "_gp_disp") == 0);
1812 r
= BFD_RELOC_HI16_S
;
1816 * If the macro is about to expand into a second instruction,
1817 * print a warning if needed. We need to pass ip as a parameter
1818 * to generate a better warning message here...
1820 if (mips_warn_about_macros
&& place
== NULL
&& *counter
== 1)
1821 as_warn ("Macro instruction expanded into multiple instructions");
1824 *counter
+= 1; /* bump instruction counter */
1826 insn
.insn_mo
= (struct mips_opcode
*) hash_find (op_hash
, name
);
1827 assert (insn
.insn_mo
);
1828 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
1829 assert (strcmp (fmt
, insn
.insn_mo
->args
) == 0);
1831 insn
.insn_opcode
= insn
.insn_mo
->match
| (regnum
<< OP_SH_RT
);
1832 if (r
== BFD_RELOC_UNUSED
)
1834 insn
.insn_opcode
|= high_expr
.X_add_number
;
1835 append_insn (place
, &insn
, NULL
, r
, false);
1838 append_insn (place
, &insn
, &high_expr
, r
, false);
1842 * Generates code to set the $at register to true (one)
1843 * if reg is less than the immediate expression.
1846 set_at (counter
, reg
, unsignedp
)
1851 if (imm_expr
.X_add_number
>= -0x8000 && imm_expr
.X_add_number
< 0x8000)
1852 macro_build ((char *) NULL
, counter
, &imm_expr
,
1853 unsignedp
? "sltiu" : "slti",
1854 "t,r,j", AT
, reg
, (int) BFD_RELOC_LO16
);
1857 load_register (counter
, AT
, &imm_expr
, 0);
1858 macro_build ((char *) NULL
, counter
, NULL
,
1859 unsignedp
? "sltu" : "slt",
1860 "d,v,t", AT
, reg
, AT
);
1864 /* Warn if an expression is not a constant. */
1867 check_absolute_expr (ip
, ex
)
1868 struct mips_cl_insn
*ip
;
1871 if (ex
->X_op
!= O_constant
)
1872 as_warn ("Instruction %s requires absolute expression", ip
->insn_mo
->name
);
1875 /* Count the leading zeroes by performing a binary chop. This is a
1876 bulky bit of source, but performance is a LOT better for the
1877 majority of values than a simple loop to count the bits:
1878 for (lcnt = 0; (lcnt < 32); lcnt++)
1879 if ((v) & (1 << (31 - lcnt)))
1881 However it is not code size friendly, and the gain will drop a bit
1882 on certain cached systems.
1884 #define COUNT_TOP_ZEROES(v) \
1885 (((v) & ~0xffff) == 0 \
1886 ? ((v) & ~0xff) == 0 \
1887 ? ((v) & ~0xf) == 0 \
1888 ? ((v) & ~0x3) == 0 \
1889 ? ((v) & ~0x1) == 0 \
1894 : ((v) & ~0x7) == 0 \
1897 : ((v) & ~0x3f) == 0 \
1898 ? ((v) & ~0x1f) == 0 \
1901 : ((v) & ~0x7f) == 0 \
1904 : ((v) & ~0xfff) == 0 \
1905 ? ((v) & ~0x3ff) == 0 \
1906 ? ((v) & ~0x1ff) == 0 \
1909 : ((v) & ~0x7ff) == 0 \
1912 : ((v) & ~0x3fff) == 0 \
1913 ? ((v) & ~0x1fff) == 0 \
1916 : ((v) & ~0x7fff) == 0 \
1919 : ((v) & ~0xffffff) == 0 \
1920 ? ((v) & ~0xfffff) == 0 \
1921 ? ((v) & ~0x3ffff) == 0 \
1922 ? ((v) & ~0x1ffff) == 0 \
1925 : ((v) & ~0x7ffff) == 0 \
1928 : ((v) & ~0x3fffff) == 0 \
1929 ? ((v) & ~0x1fffff) == 0 \
1932 : ((v) & ~0x7fffff) == 0 \
1935 : ((v) & ~0xfffffff) == 0 \
1936 ? ((v) & ~0x3ffffff) == 0 \
1937 ? ((v) & ~0x1ffffff) == 0 \
1940 : ((v) & ~0x7ffffff) == 0 \
1943 : ((v) & ~0x3fffffff) == 0 \
1944 ? ((v) & ~0x1fffffff) == 0 \
1947 : ((v) & ~0x7fffffff) == 0 \
1952 * This routine generates the least number of instructions neccessary to load
1953 * an absolute expression value into a register.
1956 load_register (counter
, reg
, ep
, dbl
)
1963 expressionS hi32
, lo32
, tmp
;
1965 if (ep
->X_op
!= O_big
)
1967 assert (ep
->X_op
== O_constant
);
1968 if (ep
->X_add_number
< 0x8000
1969 && (ep
->X_add_number
>= 0
1970 || (ep
->X_add_number
>= -0x8000
1973 || sizeof (ep
->X_add_number
) > 4))))
1975 /* We can handle 16 bit signed values with an addiu to
1976 $zero. No need to ever use daddiu here, since $zero and
1977 the result are always correct in 32 bit mode. */
1978 macro_build ((char *) NULL
, counter
, ep
, "addiu", "t,r,j", reg
, 0,
1979 (int) BFD_RELOC_LO16
);
1982 else if (ep
->X_add_number
>= 0 && ep
->X_add_number
< 0x10000)
1984 /* We can handle 16 bit unsigned values with an ori to
1986 macro_build ((char *) NULL
, counter
, ep
, "ori", "t,r,i", reg
, 0,
1987 (int) BFD_RELOC_LO16
);
1990 else if ((((ep
->X_add_number
&~ (offsetT
) 0x7fffffff) == 0
1991 || ((ep
->X_add_number
&~ (offsetT
) 0x7fffffff)
1992 == ~ (offsetT
) 0x7fffffff))
1995 || sizeof (ep
->X_add_number
) > 4
1996 || (ep
->X_add_number
& 0x80000000) == 0))
1997 || ((mips_isa
< 3 || !dbl
)
1998 && (ep
->X_add_number
&~ 0xffffffff) == 0))
2000 /* 32 bit values require an lui. */
2001 macro_build ((char *) NULL
, counter
, ep
, "lui", "t,u", reg
,
2002 (int) BFD_RELOC_HI16
);
2003 if ((ep
->X_add_number
& 0xffff) != 0)
2004 macro_build ((char *) NULL
, counter
, ep
, "ori", "t,r,i", reg
, reg
,
2005 (int) BFD_RELOC_LO16
);
2010 /* The value is larger than 32 bits. */
2014 as_bad ("Number larger than 32 bits");
2015 macro_build ((char *) NULL
, counter
, ep
, "addiu", "t,r,j", reg
, 0,
2016 (int) BFD_RELOC_LO16
);
2020 if (ep
->X_op
!= O_big
)
2024 hi32
.X_add_number
>>= shift
;
2025 hi32
.X_add_number
&= 0xffffffff;
2026 if ((hi32
.X_add_number
& 0x80000000) != 0)
2027 hi32
.X_add_number
|= ~ (offsetT
) 0xffffffff;
2029 lo32
.X_add_number
&= 0xffffffff;
2033 assert (ep
->X_add_number
> 2);
2034 if (ep
->X_add_number
== 3)
2035 generic_bignum
[3] = 0;
2036 else if (ep
->X_add_number
> 4)
2037 as_bad ("Number larger than 64 bits");
2038 lo32
.X_op
= O_constant
;
2039 lo32
.X_add_number
= generic_bignum
[0] + (generic_bignum
[1] << 16);
2040 hi32
.X_op
= O_constant
;
2041 hi32
.X_add_number
= generic_bignum
[2] + (generic_bignum
[3] << 16);
2044 if (hi32
.X_add_number
== 0)
2048 if (hi32
.X_add_number
== 0xffffffff)
2050 if ((lo32
.X_add_number
& 0xffff8000) == 0xffff8000)
2052 macro_build ((char *) NULL
, counter
, &lo32
, "addiu", "t,r,j", reg
, 0,
2053 (int) BFD_RELOC_LO16
);
2056 if (lo32
.X_add_number
& 0x80000000)
2058 macro_build ((char *) NULL
, counter
, &lo32
, "lui", "t,u", reg
,
2059 (int) BFD_RELOC_HI16
);
2060 macro_build ((char *) NULL
, counter
, &lo32
, "ori", "t,r,i", reg
, reg
,
2061 (int) BFD_RELOC_LO16
);
2066 /* Check for 16bit shifted constant: */
2068 tmp
.X_add_number
= hi32
.X_add_number
<< shift
| lo32
.X_add_number
;
2069 /* We know that hi32 is non-zero, so start the mask on the first
2070 bit of the hi32 value: */
2074 if ((tmp
.X_add_number
& ~((offsetT
)0xffff << shift
)) == 0)
2076 tmp
.X_op
= O_constant
;
2077 tmp
.X_add_number
>>= shift
;
2078 macro_build ((char *) NULL
, counter
, &tmp
, "ori", "t,r,i", reg
, 0,
2079 (int) BFD_RELOC_LO16
);
2080 macro_build ((char *) NULL
, counter
, NULL
,
2081 (shift
>= 32) ? "dsll32" : "dsll",
2082 "d,w,<", reg
, reg
, (shift
>= 32) ? shift
- 32 : shift
);
2086 } while (shift
<= (64 - 16));
2090 tmp
.X_add_number
= hi32
.X_add_number
<< shift
| lo32
.X_add_number
;
2091 while ((tmp
.X_add_number
& 1) == 0)
2093 tmp
.X_add_number
>>= 1;
2096 if (((tmp
.X_add_number
+ 1) & tmp
.X_add_number
) == 0) /* (power-of-2 - 1) */
2098 shift
= COUNT_TOP_ZEROES((unsigned int)hi32
.X_add_number
);
2101 tmp
.X_op
= O_constant
;
2102 tmp
.X_add_number
= (offsetT
)-1;
2103 macro_build ((char *) NULL
, counter
, &tmp
, "addiu", "t,r,j", reg
, 0,
2104 (int) BFD_RELOC_LO16
); /* set all ones */
2108 macro_build ((char *) NULL
, counter
, NULL
,
2109 (freg
>= 32) ? "dsll32" : "dsll",
2111 (freg
>= 32) ? freg
- 32 : freg
);
2113 macro_build ((char *) NULL
, counter
, NULL
, (shift
>= 32) ? "dsrl32" : "dsrl",
2114 "d,w,<", reg
, reg
, (shift
>= 32) ? shift
- 32 : shift
);
2118 load_register (counter
, reg
, &hi32
, 0);
2121 if ((lo32
.X_add_number
& 0xffff0000) == 0)
2125 macro_build ((char *) NULL
, counter
, NULL
, "dsll32", "d,w,<", reg
,
2134 if ((freg
== 0) && (lo32
.X_add_number
== 0xffffffff))
2136 macro_build ((char *) NULL
, counter
, &lo32
, "lui", "t,u", reg
,
2137 (int) BFD_RELOC_HI16
);
2138 macro_build ((char *) NULL
, counter
, NULL
, "dsrl32", "d,w,<", reg
,
2145 macro_build ((char *) NULL
, counter
, NULL
, "dsll", "d,w,<", reg
,
2150 mid16
.X_add_number
>>= 16;
2151 macro_build ((char *) NULL
, counter
, &mid16
, "ori", "t,r,i", reg
,
2152 freg
, (int) BFD_RELOC_LO16
);
2153 macro_build ((char *) NULL
, counter
, NULL
, "dsll", "d,w,<", reg
,
2157 if ((lo32
.X_add_number
& 0xffff) != 0)
2158 macro_build ((char *) NULL
, counter
, &lo32
, "ori", "t,r,i", reg
, freg
,
2159 (int) BFD_RELOC_LO16
);
2162 /* Load an address into a register. */
2165 load_address (counter
, reg
, ep
)
2172 if (ep
->X_op
!= O_constant
2173 && ep
->X_op
!= O_symbol
)
2175 as_bad ("expression too complex");
2176 ep
->X_op
= O_constant
;
2179 if (ep
->X_op
== O_constant
)
2181 load_register (counter
, reg
, ep
, 0);
2185 if (mips_pic
== NO_PIC
)
2187 /* If this is a reference to a GP relative symbol, we want
2188 addiu $reg,$gp,<sym> (BFD_RELOC_MIPS_GPREL)
2190 lui $reg,<sym> (BFD_RELOC_HI16_S)
2191 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
2192 If we have an addend, we always use the latter form. */
2193 if ((valueT
) ep
->X_add_number
>= MAX_GPREL_OFFSET
2194 || nopic_need_relax (ep
->X_add_symbol
))
2199 macro_build ((char *) NULL
, counter
, ep
,
2200 mips_isa
< 3 ? "addiu" : "daddiu",
2201 "t,r,j", reg
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
2202 p
= frag_var (rs_machine_dependent
, 8, 0,
2203 RELAX_ENCODE (4, 8, 0, 4, 0, mips_warn_about_macros
),
2204 ep
->X_add_symbol
, (long) 0, (char *) NULL
);
2206 macro_build_lui (p
, counter
, ep
, reg
);
2209 macro_build (p
, counter
, ep
,
2210 mips_isa
< 3 ? "addiu" : "daddiu",
2211 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
2213 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
2217 /* If this is a reference to an external symbol, we want
2218 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
2220 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
2222 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
2223 If there is a constant, it must be added in after. */
2224 ex
.X_add_number
= ep
->X_add_number
;
2225 ep
->X_add_number
= 0;
2227 macro_build ((char *) NULL
, counter
, ep
,
2228 mips_isa
< 3 ? "lw" : "ld",
2229 "t,o(b)", reg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
2230 macro_build ((char *) NULL
, counter
, (expressionS
*) NULL
, "nop", "");
2231 p
= frag_var (rs_machine_dependent
, 4, 0,
2232 RELAX_ENCODE (0, 4, -8, 0, 0, mips_warn_about_macros
),
2233 ep
->X_add_symbol
, (long) 0, (char *) NULL
);
2234 macro_build (p
, counter
, ep
,
2235 mips_isa
< 3 ? "addiu" : "daddiu",
2236 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
2237 if (ex
.X_add_number
!= 0)
2239 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
2240 as_bad ("PIC code offset overflow (max 16 signed bits)");
2241 ex
.X_op
= O_constant
;
2242 macro_build ((char *) NULL
, counter
, &ex
,
2243 mips_isa
< 3 ? "addiu" : "daddiu",
2244 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
2247 else if (mips_pic
== SVR4_PIC
)
2252 /* This is the large GOT case. If this is a reference to an
2253 external symbol, we want
2254 lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
2256 lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16)
2257 Otherwise, for a reference to a local symbol, we want
2258 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
2260 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
2261 If there is a constant, it must be added in after. */
2262 ex
.X_add_number
= ep
->X_add_number
;
2263 ep
->X_add_number
= 0;
2264 if (reg_needs_delay (GP
))
2269 macro_build ((char *) NULL
, counter
, ep
, "lui", "t,u", reg
,
2270 (int) BFD_RELOC_MIPS_GOT_HI16
);
2271 macro_build ((char *) NULL
, counter
, (expressionS
*) NULL
,
2272 mips_isa
< 3 ? "addu" : "daddu",
2273 "d,v,t", reg
, reg
, GP
);
2274 macro_build ((char *) NULL
, counter
, ep
,
2275 mips_isa
< 3 ? "lw" : "ld",
2276 "t,o(b)", reg
, (int) BFD_RELOC_MIPS_GOT_LO16
, reg
);
2277 p
= frag_var (rs_machine_dependent
, 12 + off
, 0,
2278 RELAX_ENCODE (12, 12 + off
, off
, 8 + off
, 0,
2279 mips_warn_about_macros
),
2280 ep
->X_add_symbol
, (long) 0, (char *) NULL
);
2283 /* We need a nop before loading from $gp. This special
2284 check is required because the lui which starts the main
2285 instruction stream does not refer to $gp, and so will not
2286 insert the nop which may be required. */
2287 macro_build (p
, counter
, (expressionS
*) NULL
, "nop", "");
2290 macro_build (p
, counter
, ep
,
2291 mips_isa
< 3 ? "lw" : "ld",
2292 "t,o(b)", reg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
2294 macro_build (p
, counter
, (expressionS
*) NULL
, "nop", "");
2296 macro_build (p
, counter
, ep
,
2297 mips_isa
< 3 ? "addiu" : "daddiu",
2298 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
2299 if (ex
.X_add_number
!= 0)
2301 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
2302 as_bad ("PIC code offset overflow (max 16 signed bits)");
2303 ex
.X_op
= O_constant
;
2304 macro_build ((char *) NULL
, counter
, &ex
,
2305 mips_isa
< 3 ? "addiu" : "daddiu",
2306 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
2309 else if (mips_pic
== EMBEDDED_PIC
)
2312 addiu $reg,$gp,<sym> (BFD_RELOC_MIPS_GPREL)
2314 macro_build ((char *) NULL
, counter
, ep
,
2315 mips_isa
< 3 ? "addiu" : "daddiu",
2316 "t,r,j", reg
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
2324 * This routine implements the seemingly endless macro or synthesized
2325 * instructions and addressing modes in the mips assembly language. Many
2326 * of these macros are simple and are similar to each other. These could
2327 * probably be handled by some kind of table or grammer aproach instead of
2328 * this verbose method. Others are not simple macros but are more like
2329 * optimizing code generation.
2330 * One interesting optimization is when several store macros appear
2331 * consecutivly that would load AT with the upper half of the same address.
2332 * The ensuing load upper instructions are ommited. This implies some kind
2333 * of global optimization. We currently only optimize within a single macro.
2334 * For many of the load and store macros if the address is specified as a
2335 * constant expression in the first 64k of memory (ie ld $2,0x4000c) we
2336 * first load register 'at' with zero and use it as the base register. The
2337 * mips assembler simply uses register $zero. Just one tiny optimization
2342 struct mips_cl_insn
*ip
;
2344 register int treg
, sreg
, dreg
, breg
;
2359 bfd_reloc_code_real_type r
;
2361 int hold_mips_optimize
;
2363 treg
= (ip
->insn_opcode
>> 16) & 0x1f;
2364 dreg
= (ip
->insn_opcode
>> 11) & 0x1f;
2365 sreg
= breg
= (ip
->insn_opcode
>> 21) & 0x1f;
2366 mask
= ip
->insn_mo
->mask
;
2368 expr1
.X_op
= O_constant
;
2369 expr1
.X_op_symbol
= NULL
;
2370 expr1
.X_add_symbol
= NULL
;
2371 expr1
.X_add_number
= 1;
2383 mips_emit_delays ();
2385 mips_any_noreorder
= 1;
2387 expr1
.X_add_number
= 8;
2388 macro_build ((char *) NULL
, &icnt
, &expr1
, "bgez", "s,p", sreg
);
2390 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
2392 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
, sreg
, 0);
2393 macro_build ((char *) NULL
, &icnt
, NULL
,
2394 dbl
? "dsub" : "sub",
2395 "d,v,t", dreg
, 0, sreg
);
2418 if (imm_expr
.X_add_number
>= -0x8000 && imm_expr
.X_add_number
< 0x8000)
2420 macro_build ((char *) NULL
, &icnt
, &imm_expr
, s
, "t,r,j", treg
, sreg
,
2421 (int) BFD_RELOC_LO16
);
2424 load_register (&icnt
, AT
, &imm_expr
, dbl
);
2425 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "d,v,t", treg
, sreg
, AT
);
2444 if (imm_expr
.X_add_number
>= 0 && imm_expr
.X_add_number
< 0x10000)
2446 if (mask
!= M_NOR_I
)
2447 macro_build ((char *) NULL
, &icnt
, &imm_expr
, s
, "t,r,i", treg
,
2448 sreg
, (int) BFD_RELOC_LO16
);
2451 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "ori", "t,r,i",
2452 treg
, sreg
, (int) BFD_RELOC_LO16
);
2453 macro_build ((char *) NULL
, &icnt
, NULL
, "nor", "d,v,t",
2459 load_register (&icnt
, AT
, &imm_expr
, 0);
2460 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "d,v,t", treg
, sreg
, AT
);
2477 if (imm_expr
.X_add_number
== 0)
2479 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "s,t,p", sreg
,
2483 load_register (&icnt
, AT
, &imm_expr
, 0);
2484 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "s,t,p", sreg
, AT
);
2492 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2493 likely
? "bgezl" : "bgez",
2499 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2500 likely
? "blezl" : "blez",
2504 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", AT
, sreg
, treg
);
2505 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2506 likely
? "beql" : "beq",
2513 /* check for > max integer */
2514 maxnum
= 0x7fffffff;
2522 if (imm_expr
.X_add_number
>= maxnum
2523 && (mips_isa
< 3 || sizeof (maxnum
) > 4))
2526 /* result is always false */
2529 as_warn ("Branch %s is always false (nop)", ip
->insn_mo
->name
);
2530 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
2534 as_warn ("Branch likely %s is always false", ip
->insn_mo
->name
);
2535 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "bnel",
2540 imm_expr
.X_add_number
++;
2544 if (mask
== M_BGEL_I
)
2546 if (imm_expr
.X_add_number
== 0)
2548 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2549 likely
? "bgezl" : "bgez",
2553 if (imm_expr
.X_add_number
== 1)
2555 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2556 likely
? "bgtzl" : "bgtz",
2560 maxnum
= 0x7fffffff;
2568 maxnum
= - maxnum
- 1;
2569 if (imm_expr
.X_add_number
<= maxnum
2570 && (mips_isa
< 3 || sizeof (maxnum
) > 4))
2573 /* result is always true */
2574 as_warn ("Branch %s is always true", ip
->insn_mo
->name
);
2575 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "b", "p");
2578 set_at (&icnt
, sreg
, 0);
2579 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2580 likely
? "beql" : "beq",
2591 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2592 likely
? "beql" : "beq",
2596 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", AT
, sreg
,
2598 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2599 likely
? "beql" : "beq",
2606 if (sreg
== 0 || imm_expr
.X_add_number
== -1)
2608 imm_expr
.X_add_number
++;
2612 if (mask
== M_BGEUL_I
)
2614 if (imm_expr
.X_add_number
== 0)
2616 if (imm_expr
.X_add_number
== 1)
2618 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2619 likely
? "bnel" : "bne",
2623 set_at (&icnt
, sreg
, 1);
2624 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2625 likely
? "beql" : "beq",
2634 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2635 likely
? "bgtzl" : "bgtz",
2641 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2642 likely
? "bltzl" : "bltz",
2646 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", AT
, treg
, sreg
);
2647 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2648 likely
? "bnel" : "bne",
2657 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2658 likely
? "bnel" : "bne",
2664 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", AT
, treg
,
2666 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2667 likely
? "bnel" : "bne",
2676 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2677 likely
? "blezl" : "blez",
2683 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2684 likely
? "bgezl" : "bgez",
2688 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", AT
, treg
, sreg
);
2689 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2690 likely
? "beql" : "beq",
2697 maxnum
= 0x7fffffff;
2705 if (imm_expr
.X_add_number
>= maxnum
2706 && (mips_isa
< 3 || sizeof (maxnum
) > 4))
2708 imm_expr
.X_add_number
++;
2712 if (mask
== M_BLTL_I
)
2714 if (imm_expr
.X_add_number
== 0)
2716 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2717 likely
? "bltzl" : "bltz",
2721 if (imm_expr
.X_add_number
== 1)
2723 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2724 likely
? "blezl" : "blez",
2728 set_at (&icnt
, sreg
, 0);
2729 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2730 likely
? "bnel" : "bne",
2739 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2740 likely
? "beql" : "beq",
2746 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", AT
, treg
,
2748 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2749 likely
? "beql" : "beq",
2756 if (sreg
== 0 || imm_expr
.X_add_number
== -1)
2758 imm_expr
.X_add_number
++;
2762 if (mask
== M_BLTUL_I
)
2764 if (imm_expr
.X_add_number
== 0)
2766 if (imm_expr
.X_add_number
== 1)
2768 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2769 likely
? "beql" : "beq",
2773 set_at (&icnt
, sreg
, 1);
2774 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2775 likely
? "bnel" : "bne",
2784 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2785 likely
? "bltzl" : "bltz",
2791 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2792 likely
? "bgtzl" : "bgtz",
2796 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", AT
, sreg
, treg
);
2797 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2798 likely
? "bnel" : "bne",
2809 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2810 likely
? "bnel" : "bne",
2814 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", AT
, sreg
,
2816 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2817 likely
? "bnel" : "bne",
2833 as_warn ("Divide by zero.");
2835 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", 0, 0);
2837 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 7);
2841 mips_emit_delays ();
2843 mips_any_noreorder
= 1;
2844 macro_build ((char *) NULL
, &icnt
, NULL
,
2845 dbl
? "ddiv" : "div",
2846 "z,s,t", sreg
, treg
);
2848 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", treg
, 0);
2851 expr1
.X_add_number
= 8;
2852 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", treg
, 0);
2853 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
2854 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 7);
2856 expr1
.X_add_number
= -1;
2857 macro_build ((char *) NULL
, &icnt
, &expr1
,
2858 dbl
? "daddiu" : "addiu",
2859 "t,r,j", AT
, 0, (int) BFD_RELOC_LO16
);
2860 expr1
.X_add_number
= mips_trap
? (dbl
? 12 : 8) : (dbl
? 20 : 16);
2861 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", treg
, AT
);
2864 expr1
.X_add_number
= 1;
2865 macro_build ((char *) NULL
, &icnt
, &expr1
, "daddiu", "t,r,j", AT
, 0,
2866 (int) BFD_RELOC_LO16
);
2867 macro_build ((char *) NULL
, &icnt
, NULL
, "dsll32", "d,w,<", AT
, AT
,
2872 expr1
.X_add_number
= 0x80000000;
2873 macro_build ((char *) NULL
, &icnt
, &expr1
, "lui", "t,u", AT
,
2874 (int) BFD_RELOC_HI16
);
2877 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", sreg
, AT
);
2880 expr1
.X_add_number
= 8;
2881 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", sreg
, AT
);
2882 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
2883 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 6);
2886 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d", dreg
);
2925 if (imm_expr
.X_add_number
== 0)
2927 as_warn ("Divide by zero.");
2929 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", 0, 0);
2931 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 7);
2934 if (imm_expr
.X_add_number
== 1)
2936 if (strcmp (s2
, "mflo") == 0)
2937 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
,
2940 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
, 0);
2943 if (imm_expr
.X_add_number
== -1
2944 && s
[strlen (s
) - 1] != 'u')
2946 if (strcmp (s2
, "mflo") == 0)
2949 macro_build ((char *) NULL
, &icnt
, NULL
, "dneg", "d,w", dreg
,
2952 macro_build ((char *) NULL
, &icnt
, NULL
, "neg", "d,w", dreg
,
2956 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
, 0);
2960 load_register (&icnt
, AT
, &imm_expr
, dbl
);
2961 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "z,s,t", sreg
, AT
);
2962 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "d", dreg
);
2981 mips_emit_delays ();
2983 mips_any_noreorder
= 1;
2984 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "z,s,t", sreg
, treg
);
2986 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", treg
, 0);
2989 expr1
.X_add_number
= 8;
2990 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", treg
, 0);
2991 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
2992 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 7);
2995 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "d", dreg
);
3001 /* Load the address of a symbol into a register. If breg is not
3002 zero, we then add a base register to it. */
3004 /* When generating embedded PIC code, we permit expressions of
3007 where bar is an address in the .text section. These are used
3008 when getting the addresses of functions. We don't permit
3009 X_add_number to be non-zero, because if the symbol is
3010 external the relaxing code needs to know that any addend is
3011 purely the offset to X_op_symbol. */
3012 if (mips_pic
== EMBEDDED_PIC
3013 && offset_expr
.X_op
== O_subtract
3014 && now_seg
== text_section
3015 && (offset_expr
.X_op_symbol
->sy_value
.X_op
== O_constant
3016 ? S_GET_SEGMENT (offset_expr
.X_op_symbol
) == text_section
3017 : (offset_expr
.X_op_symbol
->sy_value
.X_op
== O_symbol
3018 && (S_GET_SEGMENT (offset_expr
.X_op_symbol
3019 ->sy_value
.X_add_symbol
)
3022 && offset_expr
.X_add_number
== 0)
3024 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
3025 treg
, (int) BFD_RELOC_PCREL_HI16_S
);
3026 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3027 mips_isa
< 3 ? "addiu" : "daddiu",
3028 "t,r,j", treg
, treg
, (int) BFD_RELOC_PCREL_LO16
);
3032 if (offset_expr
.X_op
!= O_symbol
3033 && offset_expr
.X_op
!= O_constant
)
3035 as_bad ("expression too complex");
3036 offset_expr
.X_op
= O_constant
;
3050 if (offset_expr
.X_op
== O_constant
)
3051 load_register (&icnt
, tempreg
, &offset_expr
, dbl
);
3052 else if (mips_pic
== NO_PIC
)
3054 /* If this is a reference to an GP relative symbol, we want
3055 addiu $tempreg,$gp,<sym> (BFD_RELOC_MIPS_GPREL)
3057 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
3058 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
3059 If we have a constant, we need two instructions anyhow,
3060 so we may as well always use the latter form. */
3061 if ((valueT
) offset_expr
.X_add_number
>= MAX_GPREL_OFFSET
3062 || nopic_need_relax (offset_expr
.X_add_symbol
))
3067 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3068 mips_isa
< 3 ? "addiu" : "daddiu",
3069 "t,r,j", tempreg
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
3070 p
= frag_var (rs_machine_dependent
, 8, 0,
3071 RELAX_ENCODE (4, 8, 0, 4, 0,
3072 mips_warn_about_macros
),
3073 offset_expr
.X_add_symbol
, (long) 0,
3076 macro_build_lui (p
, &icnt
, &offset_expr
, tempreg
);
3079 macro_build (p
, &icnt
, &offset_expr
,
3080 mips_isa
< 3 ? "addiu" : "daddiu",
3081 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
3083 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
3085 /* If this is a reference to an external symbol, and there
3086 is no constant, we want
3087 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3088 For a local symbol, we want
3089 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3091 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
3093 If we have a small constant, and this is a reference to
3094 an external symbol, we want
3095 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3097 addiu $tempreg,$tempreg,<constant>
3098 For a local symbol, we want the same instruction
3099 sequence, but we output a BFD_RELOC_LO16 reloc on the
3102 If we have a large constant, and this is a reference to
3103 an external symbol, we want
3104 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3105 lui $at,<hiconstant>
3106 addiu $at,$at,<loconstant>
3107 addu $tempreg,$tempreg,$at
3108 For a local symbol, we want the same instruction
3109 sequence, but we output a BFD_RELOC_LO16 reloc on the
3110 addiu instruction. */
3111 expr1
.X_add_number
= offset_expr
.X_add_number
;
3112 offset_expr
.X_add_number
= 0;
3114 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3116 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
3117 if (expr1
.X_add_number
== 0)
3125 /* We're going to put in an addu instruction using
3126 tempreg, so we may as well insert the nop right
3128 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3132 p
= frag_var (rs_machine_dependent
, 8 - off
, 0,
3133 RELAX_ENCODE (0, 8 - off
, -4 - off
, 4 - off
, 0,
3135 ? mips_warn_about_macros
3137 offset_expr
.X_add_symbol
, (long) 0,
3141 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
3144 macro_build (p
, &icnt
, &expr1
,
3145 mips_isa
< 3 ? "addiu" : "daddiu",
3146 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
3147 /* FIXME: If breg == 0, and the next instruction uses
3148 $tempreg, then if this variant case is used an extra
3149 nop will be generated. */
3151 else if (expr1
.X_add_number
>= -0x8000
3152 && expr1
.X_add_number
< 0x8000)
3154 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3156 macro_build ((char *) NULL
, &icnt
, &expr1
,
3157 mips_isa
< 3 ? "addiu" : "daddiu",
3158 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
3159 (void) frag_var (rs_machine_dependent
, 0, 0,
3160 RELAX_ENCODE (0, 0, -12, -4, 0, 0),
3161 offset_expr
.X_add_symbol
, (long) 0,
3168 /* If we are going to add in a base register, and the
3169 target register and the base register are the same,
3170 then we are using AT as a temporary register. Since
3171 we want to load the constant into AT, we add our
3172 current AT (from the global offset table) and the
3173 register into the register now, and pretend we were
3174 not using a base register. */
3179 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3181 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3182 mips_isa
< 3 ? "addu" : "daddu",
3183 "d,v,t", treg
, AT
, breg
);
3189 /* Set mips_optimize around the lui instruction to avoid
3190 inserting an unnecessary nop after the lw. */
3191 hold_mips_optimize
= mips_optimize
;
3193 macro_build_lui ((char *) NULL
, &icnt
, &expr1
, AT
);
3194 mips_optimize
= hold_mips_optimize
;
3196 macro_build ((char *) NULL
, &icnt
, &expr1
,
3197 mips_isa
< 3 ? "addiu" : "daddiu",
3198 "t,r,j", AT
, AT
, (int) BFD_RELOC_LO16
);
3199 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3200 mips_isa
< 3 ? "addu" : "daddu",
3201 "d,v,t", tempreg
, tempreg
, AT
);
3202 (void) frag_var (rs_machine_dependent
, 0, 0,
3203 RELAX_ENCODE (0, 0, -16 + off1
, -8, 0, 0),
3204 offset_expr
.X_add_symbol
, (long) 0,
3209 else if (mips_pic
== SVR4_PIC
)
3213 /* This is the large GOT case. If this is a reference to an
3214 external symbol, and there is no constant, we want
3215 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
3216 addu $tempreg,$tempreg,$gp
3217 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
3218 For a local symbol, we want
3219 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3221 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
3223 If we have a small constant, and this is a reference to
3224 an external symbol, we want
3225 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
3226 addu $tempreg,$tempreg,$gp
3227 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
3229 addiu $tempreg,$tempreg,<constant>
3230 For a local symbol, we want
3231 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3233 addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16)
3235 If we have a large constant, and this is a reference to
3236 an external symbol, we want
3237 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
3238 addu $tempreg,$tempreg,$gp
3239 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
3240 lui $at,<hiconstant>
3241 addiu $at,$at,<loconstant>
3242 addu $tempreg,$tempreg,$at
3243 For a local symbol, we want
3244 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3245 lui $at,<hiconstant>
3246 addiu $at,$at,<loconstant> (BFD_RELOC_LO16)
3247 addu $tempreg,$tempreg,$at
3249 expr1
.X_add_number
= offset_expr
.X_add_number
;
3250 offset_expr
.X_add_number
= 0;
3252 if (reg_needs_delay (GP
))
3256 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
3257 tempreg
, (int) BFD_RELOC_MIPS_GOT_HI16
);
3258 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3259 mips_isa
< 3 ? "addu" : "daddu",
3260 "d,v,t", tempreg
, tempreg
, GP
);
3261 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3263 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT_LO16
,
3265 if (expr1
.X_add_number
== 0)
3273 /* We're going to put in an addu instruction using
3274 tempreg, so we may as well insert the nop right
3276 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3281 p
= frag_var (rs_machine_dependent
, 12 + gpdel
, 0,
3282 RELAX_ENCODE (12 + off
, 12 + gpdel
, gpdel
,
3285 ? mips_warn_about_macros
3287 offset_expr
.X_add_symbol
, (long) 0,
3290 else if (expr1
.X_add_number
>= -0x8000
3291 && expr1
.X_add_number
< 0x8000)
3293 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3295 macro_build ((char *) NULL
, &icnt
, &expr1
,
3296 mips_isa
< 3 ? "addiu" : "daddiu",
3297 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
3299 p
= frag_var (rs_machine_dependent
, 12 + gpdel
, 0,
3300 RELAX_ENCODE (20, 12 + gpdel
, gpdel
, 8 + gpdel
, 0,
3302 ? mips_warn_about_macros
3304 offset_expr
.X_add_symbol
, (long) 0,
3311 /* If we are going to add in a base register, and the
3312 target register and the base register are the same,
3313 then we are using AT as a temporary register. Since
3314 we want to load the constant into AT, we add our
3315 current AT (from the global offset table) and the
3316 register into the register now, and pretend we were
3317 not using a base register. */
3325 assert (tempreg
== AT
);
3326 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3328 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3329 mips_isa
< 3 ? "addu" : "daddu",
3330 "d,v,t", treg
, AT
, breg
);
3335 /* Set mips_optimize around the lui instruction to avoid
3336 inserting an unnecessary nop after the lw. */
3337 hold_mips_optimize
= mips_optimize
;
3339 macro_build_lui ((char *) NULL
, &icnt
, &expr1
, AT
);
3340 mips_optimize
= hold_mips_optimize
;
3342 macro_build ((char *) NULL
, &icnt
, &expr1
,
3343 mips_isa
< 3 ? "addiu" : "daddiu",
3344 "t,r,j", AT
, AT
, (int) BFD_RELOC_LO16
);
3345 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3346 mips_isa
< 3 ? "addu" : "daddu",
3347 "d,v,t", dreg
, dreg
, AT
);
3349 p
= frag_var (rs_machine_dependent
, 16 + gpdel
+ adj
, 0,
3350 RELAX_ENCODE (24 + adj
, 16 + gpdel
+ adj
, gpdel
,
3353 ? mips_warn_about_macros
3355 offset_expr
.X_add_symbol
, (long) 0,
3363 /* This is needed because this instruction uses $gp, but
3364 the first instruction on the main stream does not. */
3365 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
3368 macro_build (p
, &icnt
, &offset_expr
,
3370 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
3372 if (expr1
.X_add_number
>= -0x8000
3373 && expr1
.X_add_number
< 0x8000)
3375 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
3377 macro_build (p
, &icnt
, &expr1
,
3378 mips_isa
< 3 ? "addiu" : "daddiu",
3379 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
3380 /* FIXME: If add_number is 0, and there was no base
3381 register, the external symbol case ended with a load,
3382 so if the symbol turns out to not be external, and
3383 the next instruction uses tempreg, an unnecessary nop
3384 will be inserted. */
3390 /* We must add in the base register now, as in the
3391 external symbol case. */
3392 assert (tempreg
== AT
);
3393 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
3395 macro_build (p
, &icnt
, (expressionS
*) NULL
,
3396 mips_isa
< 3 ? "addu" : "daddu",
3397 "d,v,t", treg
, AT
, breg
);
3400 /* We set breg to 0 because we have arranged to add
3401 it in in both cases. */
3405 macro_build_lui (p
, &icnt
, &expr1
, AT
);
3407 macro_build (p
, &icnt
, &expr1
,
3408 mips_isa
< 3 ? "addiu" : "daddiu",
3409 "t,r,j", AT
, AT
, (int) BFD_RELOC_LO16
);
3411 macro_build (p
, &icnt
, (expressionS
*) NULL
,
3412 mips_isa
< 3 ? "addu" : "daddu",
3413 "d,v,t", tempreg
, tempreg
, AT
);
3417 else if (mips_pic
== EMBEDDED_PIC
)
3420 addiu $tempreg,$gp,<sym> (BFD_RELOC_MIPS_GPREL)
3422 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3423 mips_isa
< 3 ? "addiu" : "daddiu",
3424 "t,r,j", tempreg
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
3430 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3431 mips_isa
< 3 ? "addu" : "daddu",
3432 "d,v,t", treg
, tempreg
, breg
);
3440 /* The j instruction may not be used in PIC code, since it
3441 requires an absolute address. We convert it to a b
3443 if (mips_pic
== NO_PIC
)
3444 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "j", "a");
3446 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "b", "p");
3449 /* The jal instructions must be handled as macros because when
3450 generating PIC code they expand to multi-instruction
3451 sequences. Normally they are simple instructions. */
3456 if (mips_pic
== NO_PIC
3457 || mips_pic
== EMBEDDED_PIC
)
3458 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "jalr",
3460 else if (mips_pic
== SVR4_PIC
)
3462 if (sreg
!= PIC_CALL_REG
)
3463 as_warn ("MIPS PIC call to register other than $25");
3465 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "jalr",
3467 if (mips_cprestore_offset
< 0)
3468 as_warn ("No .cprestore pseudo-op used in PIC code");
3471 expr1
.X_add_number
= mips_cprestore_offset
;
3472 macro_build ((char *) NULL
, &icnt
, &expr1
,
3473 mips_isa
< 3 ? "lw" : "ld",
3474 "t,o(b)", GP
, (int) BFD_RELOC_LO16
, mips_frame_reg
);
3483 if (mips_pic
== NO_PIC
)
3484 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "jal", "a");
3485 else if (mips_pic
== SVR4_PIC
)
3487 /* If this is a reference to an external symbol, and we are
3488 using a small GOT, we want
3489 lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
3493 lw $gp,cprestore($sp)
3494 The cprestore value is set using the .cprestore
3495 pseudo-op. If we are using a big GOT, we want
3496 lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16)
3498 lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16)
3502 lw $gp,cprestore($sp)
3503 If the symbol is not external, we want
3504 lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3506 addiu $25,$25,<sym> (BFD_RELOC_LO16)
3509 lw $gp,cprestore($sp) */
3513 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3514 mips_isa
< 3 ? "lw" : "ld",
3515 "t,o(b)", PIC_CALL_REG
,
3516 (int) BFD_RELOC_MIPS_CALL16
, GP
);
3517 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3519 p
= frag_var (rs_machine_dependent
, 4, 0,
3520 RELAX_ENCODE (0, 4, -8, 0, 0, 0),
3521 offset_expr
.X_add_symbol
, (long) 0, (char *) NULL
);
3527 if (reg_needs_delay (GP
))
3531 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
3532 PIC_CALL_REG
, (int) BFD_RELOC_MIPS_CALL_HI16
);
3533 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3534 mips_isa
< 3 ? "addu" : "daddu",
3535 "d,v,t", PIC_CALL_REG
, PIC_CALL_REG
, GP
);
3536 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3537 mips_isa
< 3 ? "lw" : "ld",
3538 "t,o(b)", PIC_CALL_REG
,
3539 (int) BFD_RELOC_MIPS_CALL_LO16
, PIC_CALL_REG
);
3540 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3542 p
= frag_var (rs_machine_dependent
, 12 + gpdel
, 0,
3543 RELAX_ENCODE (16, 12 + gpdel
, gpdel
, 8 + gpdel
,
3545 offset_expr
.X_add_symbol
, (long) 0, (char *) NULL
);
3548 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
3551 macro_build (p
, &icnt
, &offset_expr
,
3552 mips_isa
< 3 ? "lw" : "ld",
3553 "t,o(b)", PIC_CALL_REG
,
3554 (int) BFD_RELOC_MIPS_GOT16
, GP
);
3556 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
3559 macro_build (p
, &icnt
, &offset_expr
,
3560 mips_isa
< 3 ? "addiu" : "daddiu",
3561 "t,r,j", PIC_CALL_REG
, PIC_CALL_REG
,
3562 (int) BFD_RELOC_LO16
);
3563 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3564 "jalr", "s", PIC_CALL_REG
);
3565 if (mips_cprestore_offset
< 0)
3566 as_warn ("No .cprestore pseudo-op used in PIC code");
3570 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3572 expr1
.X_add_number
= mips_cprestore_offset
;
3573 macro_build ((char *) NULL
, &icnt
, &expr1
,
3574 mips_isa
< 3 ? "lw" : "ld",
3575 "t,o(b)", GP
, (int) BFD_RELOC_LO16
,
3579 else if (mips_pic
== EMBEDDED_PIC
)
3581 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "bal", "p");
3582 /* The linker may expand the call to a longer sequence which
3583 uses $at, so we must break rather than return. */
3659 if (breg
== treg
|| coproc
|| lr
)
3728 if (mask
== M_LWC1_AB
3729 || mask
== M_SWC1_AB
3730 || mask
== M_LDC1_AB
3731 || mask
== M_SDC1_AB
3740 if (offset_expr
.X_op
!= O_constant
3741 && offset_expr
.X_op
!= O_symbol
)
3743 as_bad ("expression too complex");
3744 offset_expr
.X_op
= O_constant
;
3747 /* A constant expression in PIC code can be handled just as it
3748 is in non PIC code. */
3749 if (mips_pic
== NO_PIC
3750 || offset_expr
.X_op
== O_constant
)
3752 /* If this is a reference to a GP relative symbol, and there
3753 is no base register, we want
3754 <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL)
3755 Otherwise, if there is no base register, we want
3756 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
3757 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
3758 If we have a constant, we need two instructions anyhow,
3759 so we always use the latter form.
3761 If we have a base register, and this is a reference to a
3762 GP relative symbol, we want
3763 addu $tempreg,$breg,$gp
3764 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GPREL)
3766 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
3767 addu $tempreg,$tempreg,$breg
3768 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
3769 With a constant we always use the latter case. */
3772 if ((valueT
) offset_expr
.X_add_number
>= MAX_GPREL_OFFSET
3773 || nopic_need_relax (offset_expr
.X_add_symbol
))
3778 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
3779 treg
, (int) BFD_RELOC_MIPS_GPREL
, GP
);
3780 p
= frag_var (rs_machine_dependent
, 8, 0,
3781 RELAX_ENCODE (4, 8, 0, 4, 0,
3782 (mips_warn_about_macros
3783 || (used_at
&& mips_noat
))),
3784 offset_expr
.X_add_symbol
, (long) 0,
3788 macro_build_lui (p
, &icnt
, &offset_expr
, tempreg
);
3791 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
, treg
,
3792 (int) BFD_RELOC_LO16
, tempreg
);
3796 if ((valueT
) offset_expr
.X_add_number
>= MAX_GPREL_OFFSET
3797 || nopic_need_relax (offset_expr
.X_add_symbol
))
3802 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3803 mips_isa
< 3 ? "addu" : "daddu",
3804 "d,v,t", tempreg
, breg
, GP
);
3805 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
3806 treg
, (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
3807 p
= frag_var (rs_machine_dependent
, 12, 0,
3808 RELAX_ENCODE (8, 12, 0, 8, 0, 0),
3809 offset_expr
.X_add_symbol
, (long) 0,
3812 macro_build_lui (p
, &icnt
, &offset_expr
, tempreg
);
3815 macro_build (p
, &icnt
, (expressionS
*) NULL
,
3816 mips_isa
< 3 ? "addu" : "daddu",
3817 "d,v,t", tempreg
, tempreg
, breg
);
3820 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
, treg
,
3821 (int) BFD_RELOC_LO16
, tempreg
);
3824 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
3826 /* If this is a reference to an external symbol, we want
3827 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3829 <op> $treg,0($tempreg)
3831 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3833 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
3834 <op> $treg,0($tempreg)
3835 If there is a base register, we add it to $tempreg before
3836 the <op>. If there is a constant, we stick it in the
3837 <op> instruction. We don't handle constants larger than
3838 16 bits, because we have no way to load the upper 16 bits
3839 (actually, we could handle them for the subset of cases
3840 in which we are not using $at). */
3841 assert (offset_expr
.X_op
== O_symbol
);
3842 expr1
.X_add_number
= offset_expr
.X_add_number
;
3843 offset_expr
.X_add_number
= 0;
3844 if (expr1
.X_add_number
< -0x8000
3845 || expr1
.X_add_number
>= 0x8000)
3846 as_bad ("PIC code offset overflow (max 16 signed bits)");
3848 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3849 mips_isa
< 3 ? "lw" : "ld",
3850 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
3851 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
3852 p
= frag_var (rs_machine_dependent
, 4, 0,
3853 RELAX_ENCODE (0, 4, -8, 0, 0, 0),
3854 offset_expr
.X_add_symbol
, (long) 0,
3856 macro_build (p
, &icnt
, &offset_expr
,
3857 mips_isa
< 3 ? "addiu" : "daddiu",
3858 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
3860 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3861 mips_isa
< 3 ? "addu" : "daddu",
3862 "d,v,t", tempreg
, tempreg
, breg
);
3863 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
, treg
,
3864 (int) BFD_RELOC_LO16
, tempreg
);
3866 else if (mips_pic
== SVR4_PIC
)
3870 /* If this is a reference to an external symbol, we want
3871 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
3872 addu $tempreg,$tempreg,$gp
3873 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
3874 <op> $treg,0($tempreg)
3876 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3878 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
3879 <op> $treg,0($tempreg)
3880 If there is a base register, we add it to $tempreg before
3881 the <op>. If there is a constant, we stick it in the
3882 <op> instruction. We don't handle constants larger than
3883 16 bits, because we have no way to load the upper 16 bits
3884 (actually, we could handle them for the subset of cases
3885 in which we are not using $at). */
3886 assert (offset_expr
.X_op
== O_symbol
);
3887 expr1
.X_add_number
= offset_expr
.X_add_number
;
3888 offset_expr
.X_add_number
= 0;
3889 if (expr1
.X_add_number
< -0x8000
3890 || expr1
.X_add_number
>= 0x8000)
3891 as_bad ("PIC code offset overflow (max 16 signed bits)");
3892 if (reg_needs_delay (GP
))
3897 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
3898 tempreg
, (int) BFD_RELOC_MIPS_GOT_HI16
);
3899 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3900 mips_isa
< 3 ? "addu" : "daddu",
3901 "d,v,t", tempreg
, tempreg
, GP
);
3902 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3903 mips_isa
< 3 ? "lw" : "ld",
3904 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT_LO16
,
3906 p
= frag_var (rs_machine_dependent
, 12 + gpdel
, 0,
3907 RELAX_ENCODE (12, 12 + gpdel
, gpdel
, 8 + gpdel
, 0, 0),
3908 offset_expr
.X_add_symbol
, (long) 0, (char *) NULL
);
3911 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
3914 macro_build (p
, &icnt
, &offset_expr
,
3915 mips_isa
< 3 ? "lw" : "ld",
3916 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
3918 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
3920 macro_build (p
, &icnt
, &offset_expr
,
3921 mips_isa
< 3 ? "addiu" : "daddiu",
3922 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
3924 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3925 mips_isa
< 3 ? "addu" : "daddu",
3926 "d,v,t", tempreg
, tempreg
, breg
);
3927 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
, treg
,
3928 (int) BFD_RELOC_LO16
, tempreg
);
3930 else if (mips_pic
== EMBEDDED_PIC
)
3932 /* If there is no base register, we want
3933 <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL)
3934 If there is a base register, we want
3935 addu $tempreg,$breg,$gp
3936 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GPREL)
3938 assert (offset_expr
.X_op
== O_symbol
);
3941 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
3942 treg
, (int) BFD_RELOC_MIPS_GPREL
, GP
);
3947 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3948 mips_isa
< 3 ? "addu" : "daddu",
3949 "d,v,t", tempreg
, breg
, GP
);
3950 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
3951 treg
, (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
3964 load_register (&icnt
, treg
, &imm_expr
, 0);
3968 load_register (&icnt
, treg
, &imm_expr
, 1);
3972 if (imm_expr
.X_op
== O_constant
)
3974 load_register (&icnt
, AT
, &imm_expr
, 0);
3975 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3976 "mtc1", "t,G", AT
, treg
);
3981 assert (offset_expr
.X_op
== O_symbol
3982 && strcmp (segment_name (S_GET_SEGMENT
3983 (offset_expr
.X_add_symbol
)),
3985 && offset_expr
.X_add_number
== 0);
3986 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lwc1", "T,o(b)",
3987 treg
, (int) BFD_RELOC_MIPS_LITERAL
, GP
);
3992 /* We know that sym is in the .rdata section. First we get the
3993 upper 16 bits of the address. */
3994 if (mips_pic
== NO_PIC
)
3996 /* FIXME: This won't work for a 64 bit address. */
3997 macro_build_lui ((char *) NULL
, &icnt
, &offset_expr
, AT
);
3999 else if (mips_pic
== SVR4_PIC
)
4001 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4002 mips_isa
< 3 ? "lw" : "ld",
4003 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
4005 else if (mips_pic
== EMBEDDED_PIC
)
4007 /* For embedded PIC we pick up the entire address off $gp in
4008 a single instruction. */
4009 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4010 mips_isa
< 3 ? "addiu" : "daddiu",
4011 "t,r,j", AT
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
4012 offset_expr
.X_op
= O_constant
;
4013 offset_expr
.X_add_number
= 0;
4018 /* Now we load the register(s). */
4020 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "ld", "t,o(b)",
4021 treg
, (int) BFD_RELOC_LO16
, AT
);
4024 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lw", "t,o(b)",
4025 treg
, (int) BFD_RELOC_LO16
, AT
);
4028 /* FIXME: How in the world do we deal with the possible
4030 offset_expr
.X_add_number
+= 4;
4031 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lw", "t,o(b)",
4032 treg
+ 1, (int) BFD_RELOC_LO16
, AT
);
4036 /* To avoid confusion in tc_gen_reloc, we must ensure that this
4037 does not become a variant frag. */
4038 frag_wane (frag_now
);
4044 assert (offset_expr
.X_op
== O_symbol
4045 && offset_expr
.X_add_number
== 0);
4046 s
= segment_name (S_GET_SEGMENT (offset_expr
.X_add_symbol
));
4047 if (strcmp (s
, ".lit8") == 0)
4051 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "ldc1",
4052 "T,o(b)", treg
, (int) BFD_RELOC_MIPS_LITERAL
, GP
);
4056 r
= BFD_RELOC_MIPS_LITERAL
;
4061 assert (strcmp (s
, RDATA_SECTION_NAME
) == 0);
4062 if (mips_pic
== SVR4_PIC
)
4063 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4064 mips_isa
< 3 ? "lw" : "ld",
4065 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
4068 /* FIXME: This won't work for a 64 bit address. */
4069 macro_build_lui ((char *) NULL
, &icnt
, &offset_expr
, AT
);
4074 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "ldc1",
4075 "T,o(b)", treg
, (int) BFD_RELOC_LO16
, AT
);
4077 /* To avoid confusion in tc_gen_reloc, we must ensure
4078 that this does not become a variant frag. */
4079 frag_wane (frag_now
);
4090 /* Even on a big endian machine $fn comes before $fn+1. We have
4091 to adjust when loading from memory. */
4094 assert (mips_isa
< 2);
4095 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lwc1", "T,o(b)",
4096 byte_order
== LITTLE_ENDIAN
? treg
: treg
+ 1,
4098 /* FIXME: A possible overflow which I don't know how to deal
4100 offset_expr
.X_add_number
+= 4;
4101 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lwc1", "T,o(b)",
4102 byte_order
== LITTLE_ENDIAN
? treg
+ 1 : treg
,
4105 /* To avoid confusion in tc_gen_reloc, we must ensure that this
4106 does not become a variant frag. */
4107 frag_wane (frag_now
);
4116 * The MIPS assembler seems to check for X_add_number not
4117 * being double aligned and generating:
4120 * addiu at,at,%lo(foo+1)
4123 * But, the resulting address is the same after relocation so why
4124 * generate the extra instruction?
4171 if (offset_expr
.X_op
!= O_symbol
4172 && offset_expr
.X_op
!= O_constant
)
4174 as_bad ("expression too complex");
4175 offset_expr
.X_op
= O_constant
;
4178 /* Even on a big endian machine $fn comes before $fn+1. We have
4179 to adjust when loading from memory. We set coproc if we must
4180 load $fn+1 first. */
4181 if (byte_order
== LITTLE_ENDIAN
)
4184 if (mips_pic
== NO_PIC
4185 || offset_expr
.X_op
== O_constant
)
4187 /* If this is a reference to a GP relative symbol, we want
4188 <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL)
4189 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_MIPS_GPREL)
4190 If we have a base register, we use this
4192 <op> $treg,<sym>($at) (BFD_RELOC_MIPS_GPREL)
4193 <op> $treg+1,<sym>+4($at) (BFD_RELOC_MIPS_GPREL)
4194 If this is not a GP relative symbol, we want
4195 lui $at,<sym> (BFD_RELOC_HI16_S)
4196 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
4197 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
4198 If there is a base register, we add it to $at after the
4199 lui instruction. If there is a constant, we always use
4201 if ((valueT
) offset_expr
.X_add_number
>= MAX_GPREL_OFFSET
4202 || nopic_need_relax (offset_expr
.X_add_symbol
))
4221 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4222 mips_isa
< 3 ? "addu" : "daddu",
4223 "d,v,t", AT
, breg
, GP
);
4229 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
4230 coproc
? treg
+ 1 : treg
,
4231 (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
4232 offset_expr
.X_add_number
+= 4;
4234 /* Set mips_optimize to 2 to avoid inserting an
4236 hold_mips_optimize
= mips_optimize
;
4238 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
4239 coproc
? treg
: treg
+ 1,
4240 (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
4241 mips_optimize
= hold_mips_optimize
;
4243 p
= frag_var (rs_machine_dependent
, 12 + off
, 0,
4244 RELAX_ENCODE (8 + off
, 12 + off
, 0, 4 + off
, 1,
4245 used_at
&& mips_noat
),
4246 offset_expr
.X_add_symbol
, (long) 0,
4249 /* We just generated two relocs. When tc_gen_reloc
4250 handles this case, it will skip the first reloc and
4251 handle the second. The second reloc already has an
4252 extra addend of 4, which we added above. We must
4253 subtract it out, and then subtract another 4 to make
4254 the first reloc come out right. The second reloc
4255 will come out right because we are going to add 4 to
4256 offset_expr when we build its instruction below. */
4257 offset_expr
.X_add_number
-= 8;
4258 offset_expr
.X_op
= O_constant
;
4260 macro_build_lui (p
, &icnt
, &offset_expr
, AT
);
4265 macro_build (p
, &icnt
, (expressionS
*) NULL
,
4266 mips_isa
< 3 ? "addu" : "daddu",
4267 "d,v,t", AT
, breg
, AT
);
4271 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
,
4272 coproc
? treg
+ 1 : treg
,
4273 (int) BFD_RELOC_LO16
, AT
);
4276 /* FIXME: How do we handle overflow here? */
4277 offset_expr
.X_add_number
+= 4;
4278 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
,
4279 coproc
? treg
: treg
+ 1,
4280 (int) BFD_RELOC_LO16
, AT
);
4282 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
4286 /* If this is a reference to an external symbol, we want
4287 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4292 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4294 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
4295 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
4296 If there is a base register we add it to $at before the
4297 lwc1 instructions. If there is a constant we include it
4298 in the lwc1 instructions. */
4300 expr1
.X_add_number
= offset_expr
.X_add_number
;
4301 offset_expr
.X_add_number
= 0;
4302 if (expr1
.X_add_number
< -0x8000
4303 || expr1
.X_add_number
>= 0x8000 - 4)
4304 as_bad ("PIC code offset overflow (max 16 signed bits)");
4309 frag_grow (24 + off
);
4310 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4311 mips_isa
< 3 ? "lw" : "ld",
4312 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
4313 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
4315 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4316 mips_isa
< 3 ? "addu" : "daddu",
4317 "d,v,t", AT
, breg
, AT
);
4318 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
4319 coproc
? treg
+ 1 : treg
,
4320 (int) BFD_RELOC_LO16
, AT
);
4321 expr1
.X_add_number
+= 4;
4323 /* Set mips_optimize to 2 to avoid inserting an undesired
4325 hold_mips_optimize
= mips_optimize
;
4327 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
4328 coproc
? treg
: treg
+ 1,
4329 (int) BFD_RELOC_LO16
, AT
);
4330 mips_optimize
= hold_mips_optimize
;
4332 (void) frag_var (rs_machine_dependent
, 0, 0,
4333 RELAX_ENCODE (0, 0, -16 - off
, -8, 1, 0),
4334 offset_expr
.X_add_symbol
, (long) 0,
4337 else if (mips_pic
== SVR4_PIC
)
4341 /* If this is a reference to an external symbol, we want
4342 lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16)
4344 lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16)
4349 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4351 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
4352 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
4353 If there is a base register we add it to $at before the
4354 lwc1 instructions. If there is a constant we include it
4355 in the lwc1 instructions. */
4357 expr1
.X_add_number
= offset_expr
.X_add_number
;
4358 offset_expr
.X_add_number
= 0;
4359 if (expr1
.X_add_number
< -0x8000
4360 || expr1
.X_add_number
>= 0x8000 - 4)
4361 as_bad ("PIC code offset overflow (max 16 signed bits)");
4362 if (reg_needs_delay (GP
))
4371 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
4372 AT
, (int) BFD_RELOC_MIPS_GOT_HI16
);
4373 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4374 mips_isa
< 3 ? "addu" : "daddu",
4375 "d,v,t", AT
, AT
, GP
);
4376 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4377 mips_isa
< 3 ? "lw" : "ld",
4378 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT_LO16
, AT
);
4379 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
4381 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4382 mips_isa
< 3 ? "addu" : "daddu",
4383 "d,v,t", AT
, breg
, AT
);
4384 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
4385 coproc
? treg
+ 1 : treg
,
4386 (int) BFD_RELOC_LO16
, AT
);
4387 expr1
.X_add_number
+= 4;
4389 /* Set mips_optimize to 2 to avoid inserting an undesired
4391 hold_mips_optimize
= mips_optimize
;
4393 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
4394 coproc
? treg
: treg
+ 1,
4395 (int) BFD_RELOC_LO16
, AT
);
4396 mips_optimize
= hold_mips_optimize
;
4397 expr1
.X_add_number
-= 4;
4399 p
= frag_var (rs_machine_dependent
, 16 + gpdel
+ off
, 0,
4400 RELAX_ENCODE (24 + off
, 16 + gpdel
+ off
, gpdel
,
4401 8 + gpdel
+ off
, 1, 0),
4402 offset_expr
.X_add_symbol
, (long) 0,
4406 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4409 macro_build (p
, &icnt
, &offset_expr
,
4410 mips_isa
< 3 ? "lw" : "ld",
4411 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
4413 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4417 macro_build (p
, &icnt
, (expressionS
*) NULL
,
4418 mips_isa
< 3 ? "addu" : "daddu",
4419 "d,v,t", AT
, breg
, AT
);
4422 macro_build (p
, &icnt
, &expr1
, s
, fmt
,
4423 coproc
? treg
+ 1 : treg
,
4424 (int) BFD_RELOC_LO16
, AT
);
4426 expr1
.X_add_number
+= 4;
4428 /* Set mips_optimize to 2 to avoid inserting an undesired
4430 hold_mips_optimize
= mips_optimize
;
4432 macro_build (p
, &icnt
, &expr1
, s
, fmt
,
4433 coproc
? treg
: treg
+ 1,
4434 (int) BFD_RELOC_LO16
, AT
);
4435 mips_optimize
= hold_mips_optimize
;
4437 else if (mips_pic
== EMBEDDED_PIC
)
4439 /* If there is no base register, we use
4440 <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL)
4441 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_MIPS_GPREL)
4442 If we have a base register, we use
4444 <op> $treg,<sym>($at) (BFD_RELOC_MIPS_GPREL)
4445 <op> $treg+1,<sym>+4($at) (BFD_RELOC_MIPS_GPREL)
4454 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4455 mips_isa
< 3 ? "addu" : "daddu",
4456 "d,v,t", AT
, breg
, GP
);
4461 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
4462 coproc
? treg
+ 1 : treg
,
4463 (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
4464 offset_expr
.X_add_number
+= 4;
4465 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
4466 coproc
? treg
: treg
+ 1,
4467 (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
4483 assert (mips_isa
< 3);
4484 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
4485 (int) BFD_RELOC_LO16
, breg
);
4486 offset_expr
.X_add_number
+= 4;
4487 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
+ 1,
4488 (int) BFD_RELOC_LO16
, breg
);
4490 #ifdef LOSING_COMPILER
4496 as_warn ("Macro used $at after \".set noat\"");
4501 struct mips_cl_insn
*ip
;
4503 register int treg
, sreg
, dreg
, breg
;
4518 bfd_reloc_code_real_type r
;
4521 treg
= (ip
->insn_opcode
>> 16) & 0x1f;
4522 dreg
= (ip
->insn_opcode
>> 11) & 0x1f;
4523 sreg
= breg
= (ip
->insn_opcode
>> 21) & 0x1f;
4524 mask
= ip
->insn_mo
->mask
;
4526 expr1
.X_op
= O_constant
;
4527 expr1
.X_op_symbol
= NULL
;
4528 expr1
.X_add_symbol
= NULL
;
4529 expr1
.X_add_number
= 1;
4533 #endif /* LOSING_COMPILER */
4538 macro_build ((char *) NULL
, &icnt
, NULL
,
4539 dbl
? "dmultu" : "multu",
4541 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
4547 /* The MIPS assembler some times generates shifts and adds. I'm
4548 not trying to be that fancy. GCC should do this for us
4550 load_register (&icnt
, AT
, &imm_expr
, dbl
);
4551 macro_build ((char *) NULL
, &icnt
, NULL
,
4552 dbl
? "dmult" : "mult",
4554 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
4560 mips_emit_delays ();
4562 mips_any_noreorder
= 1;
4563 macro_build ((char *) NULL
, &icnt
, NULL
,
4564 dbl
? "dmult" : "mult",
4566 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
4567 macro_build ((char *) NULL
, &icnt
, NULL
,
4568 dbl
? "dsra32" : "sra",
4569 "d,w,<", dreg
, dreg
, 31);
4570 macro_build ((char *) NULL
, &icnt
, NULL
, "mfhi", "d", AT
);
4572 macro_build ((char *) NULL
, &icnt
, NULL
, "tne", "s,t", dreg
, AT
);
4575 expr1
.X_add_number
= 8;
4576 macro_build ((char *) NULL
, &icnt
, &expr1
, "beq", "s,t,p", dreg
, AT
);
4577 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
4578 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 6);
4581 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
4587 mips_emit_delays ();
4589 mips_any_noreorder
= 1;
4590 macro_build ((char *) NULL
, &icnt
, NULL
,
4591 dbl
? "dmultu" : "multu",
4593 macro_build ((char *) NULL
, &icnt
, NULL
, "mfhi", "d", AT
);
4594 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
4596 macro_build ((char *) NULL
, &icnt
, NULL
, "tne", "s,t", AT
, 0);
4599 expr1
.X_add_number
= 8;
4600 macro_build ((char *) NULL
, &icnt
, &expr1
, "beq", "s,t,p", AT
, 0);
4601 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
4602 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 6);
4608 macro_build ((char *) NULL
, &icnt
, NULL
, "subu", "d,v,t", AT
, 0, treg
);
4609 macro_build ((char *) NULL
, &icnt
, NULL
, "srlv", "d,t,s", AT
, sreg
, AT
);
4610 macro_build ((char *) NULL
, &icnt
, NULL
, "sllv", "d,t,s", dreg
, sreg
,
4612 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
4616 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", AT
, sreg
,
4617 (int) (imm_expr
.X_add_number
& 0x1f));
4618 macro_build ((char *) NULL
, &icnt
, NULL
, "srl", "d,w,<", dreg
, sreg
,
4619 (int) ((0 - imm_expr
.X_add_number
) & 0x1f));
4620 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
4624 macro_build ((char *) NULL
, &icnt
, NULL
, "subu", "d,v,t", AT
, 0, treg
);
4625 macro_build ((char *) NULL
, &icnt
, NULL
, "sllv", "d,t,s", AT
, sreg
, AT
);
4626 macro_build ((char *) NULL
, &icnt
, NULL
, "srlv", "d,t,s", dreg
, sreg
,
4628 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
4632 macro_build ((char *) NULL
, &icnt
, NULL
, "srl", "d,w,<", AT
, sreg
,
4633 (int) (imm_expr
.X_add_number
& 0x1f));
4634 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", dreg
, sreg
,
4635 (int) ((0 - imm_expr
.X_add_number
) & 0x1f));
4636 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
4640 assert (mips_isa
< 2);
4641 /* Even on a big endian machine $fn comes before $fn+1. We have
4642 to adjust when storing to memory. */
4643 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "swc1", "T,o(b)",
4644 byte_order
== LITTLE_ENDIAN
? treg
: treg
+ 1,
4645 (int) BFD_RELOC_LO16
, breg
);
4646 offset_expr
.X_add_number
+= 4;
4647 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "swc1", "T,o(b)",
4648 byte_order
== LITTLE_ENDIAN
? treg
+ 1 : treg
,
4649 (int) BFD_RELOC_LO16
, breg
);
4654 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
4655 treg
, (int) BFD_RELOC_LO16
);
4657 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
4658 sreg
, (int) BFD_RELOC_LO16
);
4661 macro_build ((char *) NULL
, &icnt
, NULL
, "xor", "d,v,t", dreg
,
4663 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
4664 dreg
, (int) BFD_RELOC_LO16
);
4669 if (imm_expr
.X_add_number
== 0)
4671 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
4672 sreg
, (int) BFD_RELOC_LO16
);
4677 as_warn ("Instruction %s: result is always false",
4679 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
, 0);
4682 if (imm_expr
.X_add_number
>= 0 && imm_expr
.X_add_number
< 0x10000)
4684 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "xori", "t,r,i", dreg
,
4685 sreg
, (int) BFD_RELOC_LO16
);
4688 else if (imm_expr
.X_add_number
> -0x8000 && imm_expr
.X_add_number
< 0)
4690 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
4691 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
4692 mips_isa
< 3 ? "addiu" : "daddiu",
4693 "t,r,j", dreg
, sreg
,
4694 (int) BFD_RELOC_LO16
);
4699 load_register (&icnt
, AT
, &imm_expr
, 0);
4700 macro_build ((char *) NULL
, &icnt
, NULL
, "xor", "d,v,t", dreg
,
4704 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
, dreg
,
4705 (int) BFD_RELOC_LO16
);
4710 case M_SGE
: /* sreg >= treg <==> not (sreg < treg) */
4716 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, sreg
, treg
);
4717 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
4718 (int) BFD_RELOC_LO16
);
4721 case M_SGE_I
: /* sreg >= I <==> not (sreg < I) */
4723 if (imm_expr
.X_add_number
>= -0x8000 && imm_expr
.X_add_number
< 0x8000)
4725 macro_build ((char *) NULL
, &icnt
, &expr1
,
4726 mask
== M_SGE_I
? "slti" : "sltiu",
4727 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
4732 load_register (&icnt
, AT
, &imm_expr
, 0);
4733 macro_build ((char *) NULL
, &icnt
, NULL
,
4734 mask
== M_SGE_I
? "slt" : "sltu",
4735 "d,v,t", dreg
, sreg
, AT
);
4738 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
4739 (int) BFD_RELOC_LO16
);
4744 case M_SGT
: /* sreg > treg <==> treg < sreg */
4750 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, treg
, sreg
);
4753 case M_SGT_I
: /* sreg > I <==> I < sreg */
4759 load_register (&icnt
, AT
, &imm_expr
, 0);
4760 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, AT
, sreg
);
4763 case M_SLE
: /* sreg <= treg <==> treg >= sreg <==> not (treg < sreg) */
4769 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, treg
, sreg
);
4770 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
4771 (int) BFD_RELOC_LO16
);
4774 case M_SLE_I
: /* sreg <= I <==> I >= sreg <==> not (I < sreg) */
4780 load_register (&icnt
, AT
, &imm_expr
, 0);
4781 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, AT
, sreg
);
4782 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
4783 (int) BFD_RELOC_LO16
);
4787 if (imm_expr
.X_add_number
>= -0x8000 && imm_expr
.X_add_number
< 0x8000)
4789 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "slti", "t,r,j",
4790 dreg
, sreg
, (int) BFD_RELOC_LO16
);
4793 load_register (&icnt
, AT
, &imm_expr
, 0);
4794 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", dreg
, sreg
, AT
);
4798 if (imm_expr
.X_add_number
>= -0x8000 && imm_expr
.X_add_number
< 0x8000)
4800 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "sltiu", "t,r,j",
4801 dreg
, sreg
, (int) BFD_RELOC_LO16
);
4804 load_register (&icnt
, AT
, &imm_expr
, 0);
4805 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, sreg
,
4811 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0,
4814 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0,
4818 macro_build ((char *) NULL
, &icnt
, NULL
, "xor", "d,v,t", dreg
,
4820 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0,
4826 if (imm_expr
.X_add_number
== 0)
4828 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0,
4834 as_warn ("Instruction %s: result is always true",
4836 macro_build ((char *) NULL
, &icnt
, &expr1
,
4837 mips_isa
< 3 ? "addiu" : "daddiu",
4838 "t,r,j", dreg
, 0, (int) BFD_RELOC_LO16
);
4841 if (imm_expr
.X_add_number
>= 0 && imm_expr
.X_add_number
< 0x10000)
4843 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "xori", "t,r,i",
4844 dreg
, sreg
, (int) BFD_RELOC_LO16
);
4847 else if (imm_expr
.X_add_number
> -0x8000 && imm_expr
.X_add_number
< 0)
4849 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
4850 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
4851 mips_isa
< 3 ? "addiu" : "daddiu",
4852 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
4857 load_register (&icnt
, AT
, &imm_expr
, 0);
4858 macro_build ((char *) NULL
, &icnt
, NULL
, "xor", "d,v,t", dreg
,
4862 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0, dreg
);
4870 if (imm_expr
.X_add_number
> -0x8000 && imm_expr
.X_add_number
<= 0x8000)
4872 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
4873 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
4874 dbl
? "daddi" : "addi",
4875 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
4878 load_register (&icnt
, AT
, &imm_expr
, dbl
);
4879 macro_build ((char *) NULL
, &icnt
, NULL
,
4880 dbl
? "dsub" : "sub",
4881 "d,v,t", dreg
, sreg
, AT
);
4887 if (imm_expr
.X_add_number
> -0x8000 && imm_expr
.X_add_number
<= 0x8000)
4889 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
4890 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
4891 dbl
? "daddiu" : "addiu",
4892 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
4895 load_register (&icnt
, AT
, &imm_expr
, dbl
);
4896 macro_build ((char *) NULL
, &icnt
, NULL
,
4897 dbl
? "dsubu" : "subu",
4898 "d,v,t", dreg
, sreg
, AT
);
4919 load_register (&icnt
, AT
, &imm_expr
, 0);
4920 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "s,t", sreg
, AT
);
4925 assert (mips_isa
< 2);
4926 sreg
= (ip
->insn_opcode
>> 11) & 0x1f; /* floating reg */
4927 dreg
= (ip
->insn_opcode
>> 06) & 0x1f; /* floating reg */
4930 * Is the double cfc1 instruction a bug in the mips assembler;
4931 * or is there a reason for it?
4933 mips_emit_delays ();
4935 mips_any_noreorder
= 1;
4936 macro_build ((char *) NULL
, &icnt
, NULL
, "cfc1", "t,G", treg
, 31);
4937 macro_build ((char *) NULL
, &icnt
, NULL
, "cfc1", "t,G", treg
, 31);
4938 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "");
4939 expr1
.X_add_number
= 3;
4940 macro_build ((char *) NULL
, &icnt
, &expr1
, "ori", "t,r,i", AT
, treg
,
4941 (int) BFD_RELOC_LO16
);
4942 expr1
.X_add_number
= 2;
4943 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", AT
, AT
,
4944 (int) BFD_RELOC_LO16
);
4945 macro_build ((char *) NULL
, &icnt
, NULL
, "ctc1", "t,G", AT
, 31);
4946 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "");
4947 macro_build ((char *) NULL
, &icnt
, NULL
,
4948 mask
== M_TRUNCWD
? "cvt.w.d" : "cvt.w.s", "D,S", dreg
, sreg
);
4949 macro_build ((char *) NULL
, &icnt
, NULL
, "ctc1", "t,G", treg
, 31);
4950 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "");
4960 if (offset_expr
.X_add_number
>= 0x7fff)
4961 as_bad ("operand overflow");
4962 /* avoid load delay */
4963 if (byte_order
== LITTLE_ENDIAN
)
4964 offset_expr
.X_add_number
+= 1;
4965 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
4966 (int) BFD_RELOC_LO16
, breg
);
4967 if (byte_order
== LITTLE_ENDIAN
)
4968 offset_expr
.X_add_number
-= 1;
4970 offset_expr
.X_add_number
+= 1;
4971 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lbu", "t,o(b)", AT
,
4972 (int) BFD_RELOC_LO16
, breg
);
4973 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", treg
, treg
, 8);
4974 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", treg
, treg
, AT
);
4987 if (offset_expr
.X_add_number
>= 0x8000 - off
)
4988 as_bad ("operand overflow");
4989 if (byte_order
== LITTLE_ENDIAN
)
4990 offset_expr
.X_add_number
+= off
;
4991 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
4992 (int) BFD_RELOC_LO16
, breg
);
4993 if (byte_order
== LITTLE_ENDIAN
)
4994 offset_expr
.X_add_number
-= off
;
4996 offset_expr
.X_add_number
+= off
;
4997 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s2
, "t,o(b)", treg
,
4998 (int) BFD_RELOC_LO16
, breg
);
5011 load_address (&icnt
, AT
, &offset_expr
);
5013 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5014 mips_isa
< 3 ? "addu" : "daddu",
5015 "d,v,t", AT
, AT
, breg
);
5016 if (byte_order
== LITTLE_ENDIAN
)
5017 expr1
.X_add_number
= off
;
5019 expr1
.X_add_number
= 0;
5020 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, "t,o(b)", treg
,
5021 (int) BFD_RELOC_LO16
, AT
);
5022 if (byte_order
== LITTLE_ENDIAN
)
5023 expr1
.X_add_number
= 0;
5025 expr1
.X_add_number
= off
;
5026 macro_build ((char *) NULL
, &icnt
, &expr1
, s2
, "t,o(b)", treg
,
5027 (int) BFD_RELOC_LO16
, AT
);
5032 load_address (&icnt
, AT
, &offset_expr
);
5034 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5035 mips_isa
< 3 ? "addu" : "daddu",
5036 "d,v,t", AT
, AT
, breg
);
5037 if (byte_order
== BIG_ENDIAN
)
5038 expr1
.X_add_number
= 0;
5039 macro_build ((char *) NULL
, &icnt
, &expr1
,
5040 mask
== M_ULH_A
? "lb" : "lbu", "t,o(b)", treg
,
5041 (int) BFD_RELOC_LO16
, AT
);
5042 if (byte_order
== BIG_ENDIAN
)
5043 expr1
.X_add_number
= 1;
5045 expr1
.X_add_number
= 0;
5046 macro_build ((char *) NULL
, &icnt
, &expr1
, "lbu", "t,o(b)", AT
,
5047 (int) BFD_RELOC_LO16
, AT
);
5048 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", treg
,
5050 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", treg
,
5055 if (offset_expr
.X_add_number
>= 0x7fff)
5056 as_bad ("operand overflow");
5057 if (byte_order
== BIG_ENDIAN
)
5058 offset_expr
.X_add_number
+= 1;
5059 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "sb", "t,o(b)", treg
,
5060 (int) BFD_RELOC_LO16
, breg
);
5061 macro_build ((char *) NULL
, &icnt
, NULL
, "srl", "d,w,<", AT
, treg
, 8);
5062 if (byte_order
== BIG_ENDIAN
)
5063 offset_expr
.X_add_number
-= 1;
5065 offset_expr
.X_add_number
+= 1;
5066 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "sb", "t,o(b)", AT
,
5067 (int) BFD_RELOC_LO16
, breg
);
5080 if (offset_expr
.X_add_number
>= 0x8000 - off
)
5081 as_bad ("operand overflow");
5082 if (byte_order
== LITTLE_ENDIAN
)
5083 offset_expr
.X_add_number
+= off
;
5084 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
5085 (int) BFD_RELOC_LO16
, breg
);
5086 if (byte_order
== LITTLE_ENDIAN
)
5087 offset_expr
.X_add_number
-= off
;
5089 offset_expr
.X_add_number
+= off
;
5090 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s2
, "t,o(b)", treg
,
5091 (int) BFD_RELOC_LO16
, breg
);
5104 load_address (&icnt
, AT
, &offset_expr
);
5106 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5107 mips_isa
< 3 ? "addu" : "daddu",
5108 "d,v,t", AT
, AT
, breg
);
5109 if (byte_order
== LITTLE_ENDIAN
)
5110 expr1
.X_add_number
= off
;
5112 expr1
.X_add_number
= 0;
5113 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, "t,o(b)", treg
,
5114 (int) BFD_RELOC_LO16
, AT
);
5115 if (byte_order
== LITTLE_ENDIAN
)
5116 expr1
.X_add_number
= 0;
5118 expr1
.X_add_number
= off
;
5119 macro_build ((char *) NULL
, &icnt
, &expr1
, s2
, "t,o(b)", treg
,
5120 (int) BFD_RELOC_LO16
, AT
);
5124 load_address (&icnt
, AT
, &offset_expr
);
5126 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5127 mips_isa
< 3 ? "addu" : "daddu",
5128 "d,v,t", AT
, AT
, breg
);
5129 if (byte_order
== LITTLE_ENDIAN
)
5130 expr1
.X_add_number
= 0;
5131 macro_build ((char *) NULL
, &icnt
, &expr1
, "sb", "t,o(b)", treg
,
5132 (int) BFD_RELOC_LO16
, AT
);
5133 macro_build ((char *) NULL
, &icnt
, NULL
, "srl", "d,w,<", treg
,
5135 if (byte_order
== LITTLE_ENDIAN
)
5136 expr1
.X_add_number
= 1;
5138 expr1
.X_add_number
= 0;
5139 macro_build ((char *) NULL
, &icnt
, &expr1
, "sb", "t,o(b)", treg
,
5140 (int) BFD_RELOC_LO16
, AT
);
5141 if (byte_order
== LITTLE_ENDIAN
)
5142 expr1
.X_add_number
= 0;
5144 expr1
.X_add_number
= 1;
5145 macro_build ((char *) NULL
, &icnt
, &expr1
, "lbu", "t,o(b)", AT
,
5146 (int) BFD_RELOC_LO16
, AT
);
5147 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", treg
,
5149 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", treg
,
5154 as_bad ("Macro %s not implemented yet", ip
->insn_mo
->name
);
5158 as_warn ("Macro used $at after \".set noat\"");
5161 /* This routine assembles an instruction into its binary format. As a
5162 side effect, it sets one of the global variables imm_reloc or
5163 offset_reloc to the type of relocation to do if one of the operands
5164 is an address expression. */
5169 struct mips_cl_insn
*ip
;
5174 struct mips_opcode
*insn
;
5177 unsigned int lastregno
= 0;
5182 for (s
= str
; islower (*s
) || (*s
>= '0' && *s
<= '3') || *s
== '6' || *s
== '.'; ++s
)
5194 as_fatal ("Unknown opcode: `%s'", str
);
5196 if ((insn
= (struct mips_opcode
*) hash_find (op_hash
, str
)) == NULL
)
5198 insn_error
= "unrecognized opcode";
5206 assert (strcmp (insn
->name
, str
) == 0);
5208 if (insn
->pinfo
== INSN_MACRO
)
5209 insn_isa
= insn
->match
;
5210 else if ((insn
->pinfo
& INSN_ISA
) == INSN_ISA2
)
5212 else if ((insn
->pinfo
& INSN_ISA
) == INSN_ISA3
)
5214 else if ((insn
->pinfo
& INSN_ISA
) == INSN_ISA4
)
5219 if (insn_isa
> mips_isa
5220 || ((insn
->pinfo
& INSN_ISA
) == INSN_4650
5222 || ((insn
->pinfo
& INSN_ISA
) == INSN_4010
5224 || ((insn
->pinfo
& INSN_ISA
) == INSN_4100
5227 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
]
5228 && strcmp (insn
->name
, insn
[1].name
) == 0)
5233 if (insn_isa
<= mips_isa
)
5234 insn_error
= "opcode not supported on this processor";
5237 static char buf
[100];
5239 sprintf (buf
, "opcode requires -mips%d or greater", insn_isa
);
5246 ip
->insn_opcode
= insn
->match
;
5247 for (args
= insn
->args
;; ++args
)
5253 case '\0': /* end of args */
5266 ip
->insn_opcode
|= lastregno
<< 21;
5271 ip
->insn_opcode
|= lastregno
<< 16;
5275 ip
->insn_opcode
|= lastregno
<< 11;
5281 /* handle optional base register.
5282 Either the base register is omitted or
5283 we must have a left paren. */
5284 /* this is dependent on the next operand specifier
5285 is a 'b' for base register */
5286 assert (args
[1] == 'b');
5290 case ')': /* these must match exactly */
5295 case '<': /* must be at least one digit */
5297 * According to the manual, if the shift amount is greater
5298 * than 31 or less than 0 the the shift amount should be
5299 * mod 32. In reality the mips assembler issues an error.
5300 * We issue a warning and mask out all but the low 5 bits.
5302 my_getExpression (&imm_expr
, s
);
5303 check_absolute_expr (ip
, &imm_expr
);
5304 if ((unsigned long) imm_expr
.X_add_number
> 31)
5306 as_warn ("Improper shift amount (%ld)",
5307 (long) imm_expr
.X_add_number
);
5308 imm_expr
.X_add_number
= imm_expr
.X_add_number
& 0x1f;
5310 ip
->insn_opcode
|= imm_expr
.X_add_number
<< 6;
5311 imm_expr
.X_op
= O_absent
;
5315 case '>': /* shift amount minus 32 */
5316 my_getExpression (&imm_expr
, s
);
5317 check_absolute_expr (ip
, &imm_expr
);
5318 if ((unsigned long) imm_expr
.X_add_number
< 32
5319 || (unsigned long) imm_expr
.X_add_number
> 63)
5321 ip
->insn_opcode
|= (imm_expr
.X_add_number
- 32) << 6;
5322 imm_expr
.X_op
= O_absent
;
5326 case 'k': /* cache code */
5327 case 'h': /* prefx code */
5328 my_getExpression (&imm_expr
, s
);
5329 check_absolute_expr (ip
, &imm_expr
);
5330 if ((unsigned long) imm_expr
.X_add_number
> 31)
5332 as_warn ("Invalid value for `%s' (%lu)",
5334 (unsigned long) imm_expr
.X_add_number
);
5335 imm_expr
.X_add_number
&= 0x1f;
5338 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_CACHE
;
5340 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_PREFX
;
5341 imm_expr
.X_op
= O_absent
;
5345 case 'c': /* break code */
5346 my_getExpression (&imm_expr
, s
);
5347 check_absolute_expr (ip
, &imm_expr
);
5348 if ((unsigned) imm_expr
.X_add_number
> 1023)
5349 as_warn ("Illegal break code (%ld)",
5350 (long) imm_expr
.X_add_number
);
5351 ip
->insn_opcode
|= imm_expr
.X_add_number
<< 16;
5352 imm_expr
.X_op
= O_absent
;
5356 case 'B': /* syscall code */
5357 my_getExpression (&imm_expr
, s
);
5358 check_absolute_expr (ip
, &imm_expr
);
5359 if ((unsigned) imm_expr
.X_add_number
> 0xfffff)
5360 as_warn ("Illegal syscall code (%ld)",
5361 (long) imm_expr
.X_add_number
);
5362 ip
->insn_opcode
|= imm_expr
.X_add_number
<< 6;
5363 imm_expr
.X_op
= O_absent
;
5367 case 'C': /* Coprocessor code */
5368 my_getExpression (&imm_expr
, s
);
5369 check_absolute_expr (ip
, &imm_expr
);
5370 if ((unsigned long) imm_expr
.X_add_number
>= (1<<25))
5372 as_warn ("Coproccesor code > 25 bits (%ld)",
5373 (long) imm_expr
.X_add_number
);
5374 imm_expr
.X_add_number
&= ((1<<25) - 1);
5376 ip
->insn_opcode
|= imm_expr
.X_add_number
;
5377 imm_expr
.X_op
= O_absent
;
5381 case 'b': /* base register */
5382 case 'd': /* destination register */
5383 case 's': /* source register */
5384 case 't': /* target register */
5385 case 'r': /* both target and source */
5386 case 'v': /* both dest and source */
5387 case 'w': /* both dest and target */
5388 case 'E': /* coprocessor target register */
5389 case 'G': /* coprocessor destination register */
5390 case 'x': /* ignore register name */
5391 case 'z': /* must be zero register */
5405 while (isdigit (*s
));
5407 as_bad ("Invalid register number (%d)", regno
);
5409 else if (*args
== 'E' || *args
== 'G')
5413 if (s
[1] == 'f' && s
[2] == 'p')
5418 else if (s
[1] == 's' && s
[2] == 'p')
5423 else if (s
[1] == 'g' && s
[2] == 'p')
5428 else if (s
[1] == 'a' && s
[2] == 't')
5433 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '0')
5438 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '1')
5450 as_warn ("Used $at without \".set noat\"");
5456 if (c
== 'r' || c
== 'v' || c
== 'w')
5463 /* 'z' only matches $0. */
5464 if (c
== 'z' && regno
!= 0)
5472 ip
->insn_opcode
|= regno
<< 21;
5476 ip
->insn_opcode
|= regno
<< 11;
5481 ip
->insn_opcode
|= regno
<< 16;
5484 /* This case exists because on the r3000 trunc
5485 expands into a macro which requires a gp
5486 register. On the r6000 or r4000 it is
5487 assembled into a single instruction which
5488 ignores the register. Thus the insn version
5489 is MIPS_ISA2 and uses 'x', and the macro
5490 version is MIPS_ISA1 and uses 't'. */
5493 /* This case is for the div instruction, which
5494 acts differently if the destination argument
5495 is $0. This only matches $0, and is checked
5496 outside the switch. */
5507 ip
->insn_opcode
|= lastregno
<< 21;
5510 ip
->insn_opcode
|= lastregno
<< 16;
5515 case 'D': /* floating point destination register */
5516 case 'S': /* floating point source register */
5517 case 'T': /* floating point target register */
5518 case 'R': /* floating point source register */
5522 if (s
[0] == '$' && s
[1] == 'f' && isdigit (s
[2]))
5532 while (isdigit (*s
));
5535 as_bad ("Invalid float register number (%d)", regno
);
5537 if ((regno
& 1) != 0
5539 && ! (strcmp (str
, "mtc1") == 0 ||
5540 strcmp (str
, "mfc1") == 0 ||
5541 strcmp (str
, "lwc1") == 0 ||
5542 strcmp (str
, "swc1") == 0))
5543 as_warn ("Float register should be even, was %d",
5551 if (c
== 'V' || c
== 'W')
5561 ip
->insn_opcode
|= regno
<< 6;
5565 ip
->insn_opcode
|= regno
<< 11;
5569 ip
->insn_opcode
|= regno
<< 16;
5572 ip
->insn_opcode
|= regno
<< 21;
5581 ip
->insn_opcode
|= lastregno
<< 11;
5584 ip
->insn_opcode
|= lastregno
<< 16;
5590 my_getExpression (&imm_expr
, s
);
5591 if (imm_expr
.X_op
!= O_big
5592 && imm_expr
.X_op
!= O_constant
)
5593 insn_error
= "absolute expression required";
5598 my_getExpression (&offset_expr
, s
);
5599 imm_reloc
= BFD_RELOC_32
;
5611 unsigned char temp
[8];
5613 unsigned int length
;
5618 /* These only appear as the last operand in an
5619 instruction, and every instruction that accepts
5620 them in any variant accepts them in all variants.
5621 This means we don't have to worry about backing out
5622 any changes if the instruction does not match.
5624 The difference between them is the size of the
5625 floating point constant and where it goes. For 'F'
5626 and 'L' the constant is 64 bits; for 'f' and 'l' it
5627 is 32 bits. Where the constant is placed is based
5628 on how the MIPS assembler does things:
5631 f -- immediate value
5634 The .lit4 and .lit8 sections are only used if
5635 permitted by the -G argument.
5637 When generating embedded PIC code, we use the
5638 .lit8 section but not the .lit4 section (we can do
5639 .lit4 inline easily; we need to put .lit8
5640 somewhere in the data segment, and using .lit8
5641 permits the linker to eventually combine identical
5644 f64
= *args
== 'F' || *args
== 'L';
5646 save_in
= input_line_pointer
;
5647 input_line_pointer
= s
;
5648 err
= md_atof (f64
? 'd' : 'f', (char *) temp
, &len
);
5650 s
= input_line_pointer
;
5651 input_line_pointer
= save_in
;
5652 if (err
!= NULL
&& *err
!= '\0')
5654 as_bad ("Bad floating point constant: %s", err
);
5655 memset (temp
, '\0', sizeof temp
);
5656 length
= f64
? 8 : 4;
5659 assert (length
== (f64
? 8 : 4));
5663 && (! USE_GLOBAL_POINTER_OPT
5664 || mips_pic
== EMBEDDED_PIC
5665 || g_switch_value
< 4)
5668 imm_expr
.X_op
= O_constant
;
5669 if (byte_order
== LITTLE_ENDIAN
)
5670 imm_expr
.X_add_number
=
5671 (((((((int) temp
[3] << 8)
5676 imm_expr
.X_add_number
=
5677 (((((((int) temp
[0] << 8)
5684 const char *newname
;
5687 /* Switch to the right section. */
5689 subseg
= now_subseg
;
5692 default: /* unused default case avoids warnings. */
5694 newname
= RDATA_SECTION_NAME
;
5695 if (USE_GLOBAL_POINTER_OPT
&& g_switch_value
>= 8)
5699 newname
= RDATA_SECTION_NAME
;
5702 assert (!USE_GLOBAL_POINTER_OPT
5703 || g_switch_value
>= 4);
5707 new_seg
= subseg_new (newname
, (subsegT
) 0);
5708 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
5709 bfd_set_section_flags (stdoutput
, new_seg
,
5714 frag_align (*args
== 'l' ? 2 : 3, 0);
5715 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
5716 record_alignment (new_seg
, 4);
5718 record_alignment (new_seg
, *args
== 'l' ? 2 : 3);
5720 as_bad ("Can't use floating point insn in this section");
5722 /* Set the argument to the current address in the
5724 offset_expr
.X_op
= O_symbol
;
5725 offset_expr
.X_add_symbol
=
5726 symbol_new ("L0\001", now_seg
,
5727 (valueT
) frag_now_fix (), frag_now
);
5728 offset_expr
.X_add_number
= 0;
5730 /* Put the floating point number into the section. */
5731 p
= frag_more ((int) length
);
5732 memcpy (p
, temp
, length
);
5734 /* Switch back to the original section. */
5735 subseg_set (seg
, subseg
);
5740 case 'i': /* 16 bit unsigned immediate */
5741 case 'j': /* 16 bit signed immediate */
5742 imm_reloc
= BFD_RELOC_LO16
;
5743 c
= my_getSmallExpression (&imm_expr
, s
);
5748 if (imm_expr
.X_op
== O_constant
)
5749 imm_expr
.X_add_number
=
5750 (imm_expr
.X_add_number
>> 16) & 0xffff;
5753 imm_reloc
= BFD_RELOC_HI16_S
;
5754 imm_unmatched_hi
= true;
5757 imm_reloc
= BFD_RELOC_HI16
;
5762 if ((c
== '\0' && imm_expr
.X_op
!= O_constant
)
5763 || ((imm_expr
.X_add_number
< 0
5764 || imm_expr
.X_add_number
>= 0x10000)
5765 && imm_expr
.X_op
== O_constant
))
5767 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
5768 !strcmp (insn
->name
, insn
[1].name
))
5770 if (imm_expr
.X_op
!= O_constant
5771 && imm_expr
.X_op
!= O_big
)
5772 insn_error
= "absolute expression required";
5774 as_bad ("16 bit expression not in range 0..65535");
5782 /* The upper bound should be 0x8000, but
5783 unfortunately the MIPS assembler accepts numbers
5784 from 0x8000 to 0xffff and sign extends them, and
5785 we want to be compatible. We only permit this
5786 extended range for an instruction which does not
5787 provide any further alternates, since those
5788 alternates may handle other cases. People should
5789 use the numbers they mean, rather than relying on
5790 a mysterious sign extension. */
5791 more
= (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
5792 strcmp (insn
->name
, insn
[1].name
) == 0);
5797 if ((c
== '\0' && imm_expr
.X_op
!= O_constant
)
5798 || ((imm_expr
.X_add_number
< -0x8000
5799 || imm_expr
.X_add_number
>= max
)
5800 && imm_expr
.X_op
== O_constant
)
5802 && imm_expr
.X_add_number
< 0
5804 && imm_expr
.X_unsigned
5805 && sizeof (imm_expr
.X_add_number
) <= 4))
5809 if (imm_expr
.X_op
!= O_constant
5810 && imm_expr
.X_op
!= O_big
)
5811 insn_error
= "absolute expression required";
5813 as_bad ("16 bit expression not in range -32768..32767");
5819 case 'o': /* 16 bit offset */
5820 c
= my_getSmallExpression (&offset_expr
, s
);
5822 /* If this value won't fit into a 16 bit offset, then go
5823 find a macro that will generate the 32 bit offset
5824 code pattern. As a special hack, we accept the
5825 difference of two local symbols as a constant. This
5826 is required to suppose embedded PIC switches, which
5827 use an instruction which looks like
5828 lw $4,$L12-$LS12($4)
5829 The problem with handling this in a more general
5830 fashion is that the macro function doesn't expect to
5831 see anything which can be handled in a single
5832 constant instruction. */
5834 && (offset_expr
.X_op
!= O_constant
5835 || offset_expr
.X_add_number
>= 0x8000
5836 || offset_expr
.X_add_number
< -0x8000)
5837 && (mips_pic
!= EMBEDDED_PIC
5838 || offset_expr
.X_op
!= O_subtract
5839 || now_seg
!= text_section
5840 || (S_GET_SEGMENT (offset_expr
.X_op_symbol
)
5844 offset_reloc
= BFD_RELOC_LO16
;
5845 if (c
== 'h' || c
== 'H')
5847 assert (offset_expr
.X_op
== O_constant
);
5848 offset_expr
.X_add_number
=
5849 (offset_expr
.X_add_number
>> 16) & 0xffff;
5854 case 'p': /* pc relative offset */
5855 offset_reloc
= BFD_RELOC_16_PCREL_S2
;
5856 my_getExpression (&offset_expr
, s
);
5860 case 'u': /* upper 16 bits */
5861 c
= my_getSmallExpression (&imm_expr
, s
);
5862 if (imm_expr
.X_op
== O_constant
5863 && (imm_expr
.X_add_number
< 0
5864 || imm_expr
.X_add_number
>= 0x10000))
5865 as_bad ("lui expression not in range 0..65535");
5866 imm_reloc
= BFD_RELOC_LO16
;
5871 if (imm_expr
.X_op
== O_constant
)
5872 imm_expr
.X_add_number
=
5873 (imm_expr
.X_add_number
>> 16) & 0xffff;
5876 imm_reloc
= BFD_RELOC_HI16_S
;
5877 imm_unmatched_hi
= true;
5880 imm_reloc
= BFD_RELOC_HI16
;
5886 case 'a': /* 26 bit address */
5887 my_getExpression (&offset_expr
, s
);
5889 offset_reloc
= BFD_RELOC_MIPS_JMP
;
5892 case 'N': /* 3 bit branch condition code */
5893 case 'M': /* 3 bit compare condition code */
5894 my_getExpression (&imm_expr
, s
);
5895 check_absolute_expr (ip
, &imm_expr
);
5896 if ((unsigned long) imm_expr
.X_add_number
> 7)
5898 as_warn ("Condition code > 7 (%ld)",
5899 (long) imm_expr
.X_add_number
);
5900 imm_expr
.X_add_number
&= 7;
5903 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_BCC
;
5905 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_CCC
;
5906 imm_expr
.X_op
= O_absent
;
5911 fprintf (stderr
, "bad char = '%c'\n", *args
);
5916 /* Args don't match. */
5917 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
5918 !strcmp (insn
->name
, insn
[1].name
))
5924 insn_error
= "illegal operands";
5933 my_getSmallExpression (ep
, str
)
5944 ((str
[1] == 'h' && str
[2] == 'i')
5945 || (str
[1] == 'H' && str
[2] == 'I')
5946 || (str
[1] == 'l' && str
[2] == 'o'))
5958 * A small expression may be followed by a base register.
5959 * Scan to the end of this operand, and then back over a possible
5960 * base register. Then scan the small expression up to that
5961 * point. (Based on code in sparc.c...)
5963 for (sp
= str
; *sp
&& *sp
!= ','; sp
++)
5965 if (sp
- 4 >= str
&& sp
[-1] == RP
)
5967 if (isdigit (sp
[-2]))
5969 for (sp
-= 3; sp
>= str
&& isdigit (*sp
); sp
--)
5971 if (*sp
== '$' && sp
> str
&& sp
[-1] == LP
)
5977 else if (sp
- 5 >= str
5980 && ((sp
[-3] == 'f' && sp
[-2] == 'p')
5981 || (sp
[-3] == 's' && sp
[-2] == 'p')
5982 || (sp
[-3] == 'g' && sp
[-2] == 'p')
5983 || (sp
[-3] == 'a' && sp
[-2] == 't')))
5989 /* no expression means zero offset */
5992 /* %xx(reg) is an error */
5993 ep
->X_op
= O_absent
;
5998 ep
->X_op
= O_constant
;
6001 ep
->X_add_symbol
= NULL
;
6002 ep
->X_op_symbol
= NULL
;
6003 ep
->X_add_number
= 0;
6008 my_getExpression (ep
, str
);
6015 my_getExpression (ep
, str
);
6016 return c
; /* => %hi or %lo encountered */
6020 my_getExpression (ep
, str
)
6026 save_in
= input_line_pointer
;
6027 input_line_pointer
= str
;
6029 expr_end
= input_line_pointer
;
6030 input_line_pointer
= save_in
;
6033 /* Turn a string in input_line_pointer into a floating point constant
6034 of type type, and store the appropriate bytes in *litP. The number
6035 of LITTLENUMS emitted is stored in *sizeP . An error message is
6036 returned, or NULL on OK. */
6039 md_atof (type
, litP
, sizeP
)
6045 LITTLENUM_TYPE words
[4];
6061 return "bad call to md_atof";
6064 t
= atof_ieee (input_line_pointer
, type
, words
);
6066 input_line_pointer
= t
;
6070 if (byte_order
== LITTLE_ENDIAN
)
6072 for (i
= prec
- 1; i
>= 0; i
--)
6074 md_number_to_chars (litP
, (valueT
) words
[i
], 2);
6080 for (i
= 0; i
< prec
; i
++)
6082 md_number_to_chars (litP
, (valueT
) words
[i
], 2);
6091 md_number_to_chars (buf
, val
, n
)
6099 number_to_chars_littleendian (buf
, val
, n
);
6103 number_to_chars_bigendian (buf
, val
, n
);
6111 CONST
char *md_shortopts
= "O::g::G:";
6113 struct option md_longopts
[] = {
6114 #define OPTION_MIPS1 (OPTION_MD_BASE + 1)
6115 {"mips0", no_argument
, NULL
, OPTION_MIPS1
},
6116 {"mips1", no_argument
, NULL
, OPTION_MIPS1
},
6117 #define OPTION_MIPS2 (OPTION_MD_BASE + 2)
6118 {"mips2", no_argument
, NULL
, OPTION_MIPS2
},
6119 #define OPTION_MIPS3 (OPTION_MD_BASE + 3)
6120 {"mips3", no_argument
, NULL
, OPTION_MIPS3
},
6121 #define OPTION_MIPS4 (OPTION_MD_BASE + 4)
6122 {"mips4", no_argument
, NULL
, OPTION_MIPS4
},
6123 #define OPTION_MCPU (OPTION_MD_BASE + 5)
6124 {"mcpu", required_argument
, NULL
, OPTION_MCPU
},
6125 #define OPTION_MEMBEDDED_PIC (OPTION_MD_BASE + 6)
6126 {"membedded-pic", no_argument
, NULL
, OPTION_MEMBEDDED_PIC
},
6127 #define OPTION_TRAP (OPTION_MD_BASE + 9)
6128 {"trap", no_argument
, NULL
, OPTION_TRAP
},
6129 {"no-break", no_argument
, NULL
, OPTION_TRAP
},
6130 #define OPTION_BREAK (OPTION_MD_BASE + 10)
6131 {"break", no_argument
, NULL
, OPTION_BREAK
},
6132 {"no-trap", no_argument
, NULL
, OPTION_BREAK
},
6133 #define OPTION_EB (OPTION_MD_BASE + 11)
6134 {"EB", no_argument
, NULL
, OPTION_EB
},
6135 #define OPTION_EL (OPTION_MD_BASE + 12)
6136 {"EL", no_argument
, NULL
, OPTION_EL
},
6137 #define OPTION_M4650 (OPTION_MD_BASE + 13)
6138 {"m4650", no_argument
, NULL
, OPTION_M4650
},
6139 #define OPTION_NO_M4650 (OPTION_MD_BASE + 14)
6140 {"no-m4650", no_argument
, NULL
, OPTION_NO_M4650
},
6141 #define OPTION_M4010 (OPTION_MD_BASE + 15)
6142 {"m4010", no_argument
, NULL
, OPTION_M4010
},
6143 #define OPTION_NO_M4010 (OPTION_MD_BASE + 16)
6144 {"no-m4010", no_argument
, NULL
, OPTION_NO_M4010
},
6145 #define OPTION_M4100 (OPTION_MD_BASE + 17)
6146 {"m4100", no_argument
, NULL
, OPTION_M4100
},
6147 #define OPTION_NO_M4100 (OPTION_MD_BASE + 18)
6148 {"no-m4100", no_argument
, NULL
, OPTION_NO_M4100
},
6150 #define OPTION_CALL_SHARED (OPTION_MD_BASE + 7)
6151 #define OPTION_NON_SHARED (OPTION_MD_BASE + 8)
6152 #define OPTION_XGOT (OPTION_MD_BASE + 19)
6153 #define OPTION_32 (OPTION_MD_BASE + 20)
6154 #define OPTION_64 (OPTION_MD_BASE + 21)
6156 {"KPIC", no_argument
, NULL
, OPTION_CALL_SHARED
},
6157 {"xgot", no_argument
, NULL
, OPTION_XGOT
},
6158 {"call_shared", no_argument
, NULL
, OPTION_CALL_SHARED
},
6159 {"non_shared", no_argument
, NULL
, OPTION_NON_SHARED
},
6160 {"32", no_argument
, NULL
, OPTION_32
},
6161 {"64", no_argument
, NULL
, OPTION_64
},
6164 {NULL
, no_argument
, NULL
, 0}
6166 size_t md_longopts_size
= sizeof(md_longopts
);
6169 md_parse_option (c
, arg
)
6184 target_big_endian
= 1;
6188 target_big_endian
= 0;
6192 if (arg
&& arg
[1] == '0')
6202 mips_debug
= atoi (arg
);
6203 /* When the MIPS assembler sees -g or -g2, it does not do
6204 optimizations which limit full symbolic debugging. We take
6205 that to be equivalent to -O0. */
6206 if (mips_debug
== 2)
6238 /* Identify the processor type */
6240 if (strcmp (p
, "default") == 0
6241 || strcmp (p
, "DEFAULT") == 0)
6247 /* We need to cope with the various "vr" prefixes for the 4300
6249 if (*p
== 'v' || *p
== 'V')
6255 if (*p
== 'r' || *p
== 'R')
6262 if (strcmp (p
, "10000") == 0
6263 || strcmp (p
, "10k") == 0
6264 || strcmp (p
, "10K") == 0)
6269 if (strcmp (p
, "2000") == 0
6270 || strcmp (p
, "2k") == 0
6271 || strcmp (p
, "2K") == 0)
6276 if (strcmp (p
, "3000") == 0
6277 || strcmp (p
, "3k") == 0
6278 || strcmp (p
, "3K") == 0)
6283 if (strcmp (p
, "4000") == 0
6284 || strcmp (p
, "4k") == 0
6285 || strcmp (p
, "4K") == 0)
6287 else if (strcmp (p
, "4100") == 0)
6293 else if (strcmp (p
, "4300") == 0)
6295 else if (strcmp (p
, "4400") == 0)
6297 else if (strcmp (p
, "4600") == 0)
6299 else if (strcmp (p
, "4650") == 0)
6305 else if (strcmp (p
, "4010") == 0)
6314 if (strcmp (p
, "5000") == 0
6315 || strcmp (p
, "5k") == 0
6316 || strcmp (p
, "5K") == 0)
6321 if (strcmp (p
, "6000") == 0
6322 || strcmp (p
, "6k") == 0
6323 || strcmp (p
, "6K") == 0)
6328 if (strcmp (p
, "8000") == 0
6329 || strcmp (p
, "8k") == 0
6330 || strcmp (p
, "8K") == 0)
6335 if (strcmp (p
, "orion") == 0)
6340 if (sv
&& mips_cpu
!= 4300 && mips_cpu
!= 4100 && mips_cpu
!= 5000)
6342 as_bad ("ignoring invalid leading 'v' in -mcpu=%s switch", arg
);
6348 as_bad ("invalid architecture -mcpu=%s", arg
);
6359 case OPTION_NO_M4650
:
6367 case OPTION_NO_M4010
:
6375 case OPTION_NO_M4100
:
6379 case OPTION_MEMBEDDED_PIC
:
6380 mips_pic
= EMBEDDED_PIC
;
6381 if (USE_GLOBAL_POINTER_OPT
&& g_switch_seen
)
6383 as_bad ("-G may not be used with embedded PIC code");
6386 g_switch_value
= 0x7fffffff;
6389 /* When generating ELF code, we permit -KPIC and -call_shared to
6390 select SVR4_PIC, and -non_shared to select no PIC. This is
6391 intended to be compatible with Irix 5. */
6392 case OPTION_CALL_SHARED
:
6393 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
6395 as_bad ("-call_shared is supported only for ELF format");
6398 mips_pic
= SVR4_PIC
;
6399 if (g_switch_seen
&& g_switch_value
!= 0)
6401 as_bad ("-G may not be used with SVR4 PIC code");
6407 case OPTION_NON_SHARED
:
6408 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
6410 as_bad ("-non_shared is supported only for ELF format");
6416 /* The -xgot option tells the assembler to use 32 offsets when
6417 accessing the got in SVR4_PIC mode. It is for Irix
6424 if (! USE_GLOBAL_POINTER_OPT
)
6426 as_bad ("-G is not supported for this configuration");
6429 else if (mips_pic
== SVR4_PIC
|| mips_pic
== EMBEDDED_PIC
)
6431 as_bad ("-G may not be used with SVR4 or embedded PIC code");
6435 g_switch_value
= atoi (arg
);
6439 /* The -32 and -64 options tell the assembler to output the 32
6440 bit or the 64 bit MIPS ELF format. */
6447 const char **list
, **l
;
6449 list
= bfd_target_list ();
6450 for (l
= list
; *l
!= NULL
; l
++)
6451 if (strcmp (*l
, "elf64-bigmips") == 0
6452 || strcmp (*l
, "elf64-littlemips") == 0)
6455 as_fatal ("No compiled in support for 64 bit object file format");
6469 md_show_usage (stream
)
6474 -membedded-pic generate embedded position independent code\n\
6475 -EB generate big endian output\n\
6476 -EL generate little endian output\n\
6477 -g, -g2 do not remove uneeded NOPs or swap branches\n\
6478 -G NUM allow referencing objects up to NUM bytes\n\
6479 implicitly with the gp register [default 8]\n");
6481 -mips1, -mcpu=r{2,3}000 generate code for r2000 and r3000\n\
6482 -mips2, -mcpu=r6000 generate code for r6000\n\
6483 -mips3, -mcpu=r4000 generate code for r4000\n\
6484 -mips4, -mcpu=r8000 generate code for r8000\n\
6485 -mcpu=vr4300 generate code for vr4300\n\
6486 -mcpu=vr4100 generate code for vr4100\n\
6487 -m4650 permit R4650 instructions\n\
6488 -no-m4650 do not permit R4650 instructions\n\
6489 -m4010 permit R4010 instructions\n\
6490 -no-m4010 do not permit R4010 instructions\n\
6491 -m4100 permit VR4100 instructions\n\
6492 -no-m4100 do not permit VR4100 instructions\n");
6494 -O0 remove unneeded NOPs, do not swap branches\n\
6495 -O remove unneeded NOPs and swap branches\n\
6496 --trap, --no-break trap exception on div by 0 and mult overflow\n\
6497 --break, --no-trap break exception on div by 0 and mult overflow\n");
6500 -KPIC, -call_shared generate SVR4 position independent code\n\
6501 -non_shared do not generate position independent code\n\
6502 -xgot assume a 32 bit GOT\n\
6503 -32 create 32 bit object file (default)\n\
6504 -64 create 64 bit object file\n");
6509 mips_init_after_args ()
6511 if (target_big_endian
)
6512 byte_order
= BIG_ENDIAN
;
6514 byte_order
= LITTLE_ENDIAN
;
6518 md_pcrel_from (fixP
)
6521 if (OUTPUT_FLAVOR
!= bfd_target_aout_flavour
6522 && fixP
->fx_addsy
!= (symbolS
*) NULL
6523 && ! S_IS_DEFINED (fixP
->fx_addsy
))
6525 /* This makes a branch to an undefined symbol be a branch to the
6526 current location. */
6530 /* return the address of the delay slot */
6531 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
6534 /* This is called by emit_expr via TC_CONS_FIX_NEW when creating a
6535 reloc for a cons. We could use the definition there, except that
6536 we want to handle 64 bit relocs specially. */
6539 cons_fix_new_mips (frag
, where
, nbytes
, exp
)
6542 unsigned int nbytes
;
6545 /* If we are assembling in 32 bit mode, turn an 8 byte reloc into a
6547 if (nbytes
== 8 && ! mips_64
)
6549 if (byte_order
== BIG_ENDIAN
)
6554 if (nbytes
!= 2 && nbytes
!= 4 && nbytes
!= 8)
6555 as_bad ("Unsupported reloc size %d", nbytes
);
6557 fix_new_exp (frag_now
, where
, (int) nbytes
, exp
, 0,
6560 : (nbytes
== 4 ? BFD_RELOC_32
: BFD_RELOC_64
)));
6563 /* Sort any unmatched HI16_S relocs so that they immediately precede
6564 the corresponding LO reloc. This is called before md_apply_fix and
6565 tc_gen_reloc. Unmatched HI16_S relocs can only be generated by
6566 explicit use of the %hi modifier. */
6571 struct mips_hi_fixup
*l
;
6573 for (l
= mips_hi_fixup_list
; l
!= NULL
; l
= l
->next
)
6575 segment_info_type
*seginfo
;
6578 assert (l
->fixp
->fx_r_type
== BFD_RELOC_HI16_S
);
6580 /* Check quickly whether the next fixup happens to be a matching
6582 if (l
->fixp
->fx_next
!= NULL
6583 && l
->fixp
->fx_next
->fx_r_type
== BFD_RELOC_LO16
6584 && l
->fixp
->fx_addsy
== l
->fixp
->fx_next
->fx_addsy
6585 && l
->fixp
->fx_offset
== l
->fixp
->fx_next
->fx_offset
)
6588 /* Look through the fixups for this segment for a matching %lo.
6589 When we find one, move the %hi just in front of it. We do
6590 this in two passes. In the first pass, we try to find a
6591 unique %lo. In the second pass, we permit multiple %hi
6592 relocs for a single %lo (this is a GNU extension). */
6593 seginfo
= seg_info (l
->seg
);
6594 for (pass
= 0; pass
< 2; pass
++)
6599 for (f
= seginfo
->fix_root
; f
!= NULL
; f
= f
->fx_next
)
6601 /* Check whether this is a %lo fixup which matches l->fixp. */
6602 if (f
->fx_r_type
== BFD_RELOC_LO16
6603 && f
->fx_addsy
== l
->fixp
->fx_addsy
6604 && f
->fx_offset
== l
->fixp
->fx_offset
6607 || prev
->fx_r_type
!= BFD_RELOC_HI16_S
6608 || prev
->fx_addsy
!= f
->fx_addsy
6609 || prev
->fx_offset
!= f
->fx_offset
))
6613 /* Move l->fixp before f. */
6614 for (pf
= &seginfo
->fix_root
;
6616 pf
= &(*pf
)->fx_next
)
6617 assert (*pf
!= NULL
);
6619 *pf
= l
->fixp
->fx_next
;
6621 l
->fixp
->fx_next
= f
;
6623 seginfo
->fix_root
= l
->fixp
;
6625 prev
->fx_next
= l
->fixp
;
6637 as_warn_where (l
->fixp
->fx_file
, l
->fixp
->fx_line
,
6638 "Unmatched %%hi reloc");
6643 /* When generating embedded PIC code we need to use a special
6644 relocation to represent the difference of two symbols in the .text
6645 section (switch tables use a difference of this sort). See
6646 include/coff/mips.h for details. This macro checks whether this
6647 fixup requires the special reloc. */
6648 #define SWITCH_TABLE(fixp) \
6649 ((fixp)->fx_r_type == BFD_RELOC_32 \
6650 && (fixp)->fx_addsy != NULL \
6651 && (fixp)->fx_subsy != NULL \
6652 && S_GET_SEGMENT ((fixp)->fx_addsy) == text_section \
6653 && S_GET_SEGMENT ((fixp)->fx_subsy) == text_section)
6655 /* When generating embedded PIC code we must keep all PC relative
6656 relocations, in case the linker has to relax a call. We also need
6657 to keep relocations for switch table entries. */
6661 mips_force_relocation (fixp
)
6664 return (mips_pic
== EMBEDDED_PIC
6666 || SWITCH_TABLE (fixp
)
6667 || fixp
->fx_r_type
== BFD_RELOC_PCREL_HI16_S
6668 || fixp
->fx_r_type
== BFD_RELOC_PCREL_LO16
));
6671 /* Apply a fixup to the object file. */
6674 md_apply_fix (fixP
, valueP
)
6681 assert (fixP
->fx_size
== 4 || fixP
->fx_r_type
== BFD_RELOC_16
);
6684 fixP
->fx_addnumber
= value
; /* Remember value for tc_gen_reloc */
6686 if (fixP
->fx_addsy
== NULL
&& ! fixP
->fx_pcrel
)
6689 switch (fixP
->fx_r_type
)
6691 case BFD_RELOC_MIPS_JMP
:
6692 case BFD_RELOC_HI16
:
6693 case BFD_RELOC_HI16_S
:
6694 case BFD_RELOC_MIPS_GPREL
:
6695 case BFD_RELOC_MIPS_LITERAL
:
6696 case BFD_RELOC_MIPS_CALL16
:
6697 case BFD_RELOC_MIPS_GOT16
:
6698 case BFD_RELOC_MIPS_GPREL32
:
6699 case BFD_RELOC_MIPS_GOT_HI16
:
6700 case BFD_RELOC_MIPS_GOT_LO16
:
6701 case BFD_RELOC_MIPS_CALL_HI16
:
6702 case BFD_RELOC_MIPS_CALL_LO16
:
6704 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
6705 "Invalid PC relative reloc");
6706 /* Nothing needed to do. The value comes from the reloc entry */
6709 case BFD_RELOC_PCREL_HI16_S
:
6710 /* The addend for this is tricky if it is internal, so we just
6711 do everything here rather than in bfd_perform_relocation. */
6712 if ((fixP
->fx_addsy
->bsym
->flags
& BSF_SECTION_SYM
) == 0)
6714 /* For an external symbol adjust by the address to make it
6715 pcrel_offset. We use the address of the RELLO reloc
6716 which follows this one. */
6717 value
+= (fixP
->fx_next
->fx_frag
->fr_address
6718 + fixP
->fx_next
->fx_where
);
6723 buf
= (unsigned char *) fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
6724 if (byte_order
== BIG_ENDIAN
)
6726 md_number_to_chars (buf
, value
, 2);
6729 case BFD_RELOC_PCREL_LO16
:
6730 /* The addend for this is tricky if it is internal, so we just
6731 do everything here rather than in bfd_perform_relocation. */
6732 if ((fixP
->fx_addsy
->bsym
->flags
& BSF_SECTION_SYM
) == 0)
6733 value
+= fixP
->fx_frag
->fr_address
+ fixP
->fx_where
;
6734 buf
= (unsigned char *) fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
6735 if (byte_order
== BIG_ENDIAN
)
6737 md_number_to_chars (buf
, value
, 2);
6741 /* If we are deleting this reloc entry, we must fill in the
6742 value now. This can happen if we have a .word which is not
6743 resolved when it appears but is later defined. We also need
6744 to fill in the value if this is an embedded PIC switch table
6747 || (mips_pic
== EMBEDDED_PIC
&& SWITCH_TABLE (fixP
)))
6748 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
,
6753 /* If we are deleting this reloc entry, we must fill in the
6755 assert (fixP
->fx_size
== 2);
6757 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
,
6761 case BFD_RELOC_LO16
:
6762 /* When handling an embedded PIC switch statement, we can wind
6763 up deleting a LO16 reloc. See the 'o' case in mips_ip. */
6766 if (value
< -0x8000 || value
> 0x7fff)
6767 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
6768 "relocation overflow");
6769 buf
= (unsigned char *) fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
6770 if (byte_order
== BIG_ENDIAN
)
6772 md_number_to_chars (buf
, value
, 2);
6776 case BFD_RELOC_16_PCREL_S2
:
6778 * We need to save the bits in the instruction since fixup_segment()
6779 * might be deleting the relocation entry (i.e., a branch within
6780 * the current segment).
6783 as_warn_where (fixP
->fx_file
, fixP
->fx_line
,
6784 "Branch to odd address (%lx)", value
);
6787 /* update old instruction data */
6788 buf
= (unsigned char *) (fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
);
6792 insn
= (buf
[3] << 24) | (buf
[2] << 16) | (buf
[1] << 8) | buf
[0];
6796 insn
= (buf
[0] << 24) | (buf
[1] << 16) | (buf
[2] << 8) | buf
[3];
6804 if (value
>= -0x8000 && value
< 0x8000)
6805 insn
|= value
& 0xffff;
6808 /* The branch offset is too large. If this is an
6809 unconditional branch, and we are not generating PIC code,
6810 we can convert it to an absolute jump instruction. */
6811 if (mips_pic
== NO_PIC
6813 && fixP
->fx_frag
->fr_address
>= text_section
->vma
6814 && (fixP
->fx_frag
->fr_address
6815 < text_section
->vma
+ text_section
->_raw_size
)
6816 && ((insn
& 0xffff0000) == 0x10000000 /* beq $0,$0 */
6817 || (insn
& 0xffff0000) == 0x04010000 /* bgez $0 */
6818 || (insn
& 0xffff0000) == 0x04110000)) /* bgezal $0 */
6820 if ((insn
& 0xffff0000) == 0x04110000) /* bgezal $0 */
6821 insn
= 0x0c000000; /* jal */
6823 insn
= 0x08000000; /* j */
6824 fixP
->fx_r_type
= BFD_RELOC_MIPS_JMP
;
6826 fixP
->fx_addsy
= section_symbol (text_section
);
6827 fixP
->fx_addnumber
= (value
<< 2) + md_pcrel_from (fixP
);
6831 /* FIXME. It would be possible in principle to handle
6832 conditional branches which overflow. They could be
6833 transformed into a branch around a jump. This would
6834 require setting up variant frags for each different
6835 branch type. The native MIPS assembler attempts to
6836 handle these cases, but it appears to do it
6838 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
6839 "Relocation overflow");
6843 md_number_to_chars ((char *) buf
, (valueT
) insn
, 4);
6858 const struct mips_opcode
*p
;
6859 int treg
, sreg
, dreg
, shamt
;
6864 for (i
= 0; i
< NUMOPCODES
; ++i
)
6866 p
= &mips_opcodes
[i
];
6867 if (((oc
& p
->mask
) == p
->match
) && (p
->pinfo
!= INSN_MACRO
))
6869 printf ("%08lx %s\t", oc
, p
->name
);
6870 treg
= (oc
>> 16) & 0x1f;
6871 sreg
= (oc
>> 21) & 0x1f;
6872 dreg
= (oc
>> 11) & 0x1f;
6873 shamt
= (oc
>> 6) & 0x1f;
6875 for (args
= p
->args
;; ++args
)
6886 printf ("%c", *args
);
6890 assert (treg
== sreg
);
6891 printf ("$%d,$%d", treg
, sreg
);
6896 printf ("$%d", dreg
);
6901 printf ("$%d", treg
);
6905 printf ("0x%x", treg
);
6910 printf ("$%d", sreg
);
6914 printf ("0x%08lx", oc
& 0x1ffffff);
6926 printf ("$%d", shamt
);
6937 printf ("%08lx UNDEFINED\n", oc
);
6948 name
= input_line_pointer
;
6949 c
= get_symbol_end ();
6950 p
= (symbolS
*) symbol_find_or_make (name
);
6951 *input_line_pointer
= c
;
6955 /* Align the current frag to a given power of two. The MIPS assembler
6956 also automatically adjusts any preceding label. */
6959 mips_align (to
, fill
, label
)
6964 mips_emit_delays ();
6965 frag_align (to
, fill
);
6966 record_alignment (now_seg
, to
);
6969 assert (S_GET_SEGMENT (label
) == now_seg
);
6970 label
->sy_frag
= frag_now
;
6971 S_SET_VALUE (label
, (valueT
) frag_now_fix ());
6975 /* Align to a given power of two. .align 0 turns off the automatic
6976 alignment used by the data creating pseudo-ops. */
6983 register long temp_fill
;
6984 long max_alignment
= 15;
6988 o Note that the assembler pulls down any immediately preceeding label
6989 to the aligned address.
6990 o It's not documented but auto alignment is reinstated by
6991 a .align pseudo instruction.
6992 o Note also that after auto alignment is turned off the mips assembler
6993 issues an error on attempt to assemble an improperly aligned data item.
6998 temp
= get_absolute_expression ();
6999 if (temp
> max_alignment
)
7000 as_bad ("Alignment too large: %d. assumed.", temp
= max_alignment
);
7003 as_warn ("Alignment negative: 0 assumed.");
7006 if (*input_line_pointer
== ',')
7008 input_line_pointer
++;
7009 temp_fill
= get_absolute_expression ();
7016 mips_align (temp
, (int) temp_fill
, insn_label
);
7023 demand_empty_rest_of_line ();
7027 mips_flush_pending_output ()
7029 mips_emit_delays ();
7039 /* When generating embedded PIC code, we only use the .text, .lit8,
7040 .sdata and .sbss sections. We change the .data and .rdata
7041 pseudo-ops to use .sdata. */
7042 if (mips_pic
== EMBEDDED_PIC
7043 && (sec
== 'd' || sec
== 'r'))
7046 mips_emit_delays ();
7056 subseg_set (bss_section
, (subsegT
) get_absolute_expression ());
7057 demand_empty_rest_of_line ();
7061 if (USE_GLOBAL_POINTER_OPT
)
7063 seg
= subseg_new (RDATA_SECTION_NAME
,
7064 (subsegT
) get_absolute_expression ());
7065 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
7067 bfd_set_section_flags (stdoutput
, seg
,
7073 bfd_set_section_alignment (stdoutput
, seg
, 4);
7075 demand_empty_rest_of_line ();
7079 as_bad ("No read only data section in this object file format");
7080 demand_empty_rest_of_line ();
7086 if (USE_GLOBAL_POINTER_OPT
)
7088 seg
= subseg_new (".sdata", (subsegT
) get_absolute_expression ());
7089 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
7091 bfd_set_section_flags (stdoutput
, seg
,
7092 SEC_ALLOC
| SEC_LOAD
| SEC_RELOC
7094 bfd_set_section_alignment (stdoutput
, seg
, 4);
7096 demand_empty_rest_of_line ();
7101 as_bad ("Global pointers not supported; recompile -G 0");
7102 demand_empty_rest_of_line ();
7111 mips_enable_auto_align ()
7123 mips_emit_delays ();
7124 if (log_size
> 0 && auto_align
)
7125 mips_align (log_size
, 0, label
);
7127 cons (1 << log_size
);
7138 mips_emit_delays ();
7142 mips_align (3, 0, label
);
7144 mips_align (2, 0, label
);
7151 /* Handle .globl. We need to override it because on Irix 5 you are
7154 where foo is an undefined symbol, to mean that foo should be
7155 considered to be the address of a function. */
7166 name
= input_line_pointer
;
7167 c
= get_symbol_end ();
7168 symbolP
= symbol_find_or_make (name
);
7169 *input_line_pointer
= c
;
7172 /* On Irix 5, every global symbol that is not explicitly labelled as
7173 being a function is apparently labelled as being an object. */
7176 if (! is_end_of_line
[(unsigned char) *input_line_pointer
])
7181 secname
= input_line_pointer
;
7182 c
= get_symbol_end ();
7183 sec
= bfd_get_section_by_name (stdoutput
, secname
);
7185 as_bad ("%s: no such section", secname
);
7186 *input_line_pointer
= c
;
7188 if (sec
!= NULL
&& (sec
->flags
& SEC_CODE
) != 0)
7189 flag
= BSF_FUNCTION
;
7192 symbolP
->bsym
->flags
|= flag
;
7194 S_SET_EXTERNAL (symbolP
);
7195 demand_empty_rest_of_line ();
7205 opt
= input_line_pointer
;
7206 c
= get_symbol_end ();
7210 /* FIXME: What does this mean? */
7212 else if (strncmp (opt
, "pic", 3) == 0)
7220 mips_pic
= SVR4_PIC
;
7222 as_bad (".option pic%d not supported", i
);
7224 if (USE_GLOBAL_POINTER_OPT
&& mips_pic
== SVR4_PIC
)
7226 if (g_switch_seen
&& g_switch_value
!= 0)
7227 as_warn ("-G may not be used with SVR4 PIC code");
7229 bfd_set_gp_size (stdoutput
, 0);
7233 as_warn ("Unrecognized option \"%s\"", opt
);
7235 *input_line_pointer
= c
;
7236 demand_empty_rest_of_line ();
7243 char *name
= input_line_pointer
, ch
;
7245 while (!is_end_of_line
[(unsigned char) *input_line_pointer
])
7246 input_line_pointer
++;
7247 ch
= *input_line_pointer
;
7248 *input_line_pointer
= '\0';
7250 if (strcmp (name
, "reorder") == 0)
7254 prev_insn_unreordered
= 1;
7255 prev_prev_insn_unreordered
= 1;
7259 else if (strcmp (name
, "noreorder") == 0)
7261 mips_emit_delays ();
7263 mips_any_noreorder
= 1;
7265 else if (strcmp (name
, "at") == 0)
7269 else if (strcmp (name
, "noat") == 0)
7273 else if (strcmp (name
, "macro") == 0)
7275 mips_warn_about_macros
= 0;
7277 else if (strcmp (name
, "nomacro") == 0)
7279 if (mips_noreorder
== 0)
7280 as_bad ("`noreorder' must be set before `nomacro'");
7281 mips_warn_about_macros
= 1;
7283 else if (strcmp (name
, "move") == 0 || strcmp (name
, "novolatile") == 0)
7287 else if (strcmp (name
, "nomove") == 0 || strcmp (name
, "volatile") == 0)
7291 else if (strcmp (name
, "bopt") == 0)
7295 else if (strcmp (name
, "nobopt") == 0)
7299 else if (strncmp (name
, "mips", 4) == 0)
7303 /* Permit the user to change the ISA on the fly. Needless to
7304 say, misuse can cause serious problems. */
7305 isa
= atoi (name
+ 4);
7307 mips_isa
= file_mips_isa
;
7308 else if (isa
< 1 || isa
> 4)
7309 as_bad ("unknown ISA level");
7315 as_warn ("Tried to set unrecognized symbol: %s\n", name
);
7317 *input_line_pointer
= ch
;
7318 demand_empty_rest_of_line ();
7321 /* Handle the .abicalls pseudo-op. I believe this is equivalent to
7322 .option pic2. It means to generate SVR4 PIC calls. */
7328 mips_pic
= SVR4_PIC
;
7329 if (USE_GLOBAL_POINTER_OPT
)
7331 if (g_switch_seen
&& g_switch_value
!= 0)
7332 as_warn ("-G may not be used with SVR4 PIC code");
7335 bfd_set_gp_size (stdoutput
, 0);
7336 demand_empty_rest_of_line ();
7339 /* Handle the .cpload pseudo-op. This is used when generating SVR4
7340 PIC code. It sets the $gp register for the function based on the
7341 function address, which is in the register named in the argument.
7342 This uses a relocation against _gp_disp, which is handled specially
7343 by the linker. The result is:
7344 lui $gp,%hi(_gp_disp)
7345 addiu $gp,$gp,%lo(_gp_disp)
7346 addu $gp,$gp,.cpload argument
7347 The .cpload argument is normally $25 == $t9. */
7356 /* If we are not generating SVR4 PIC code, .cpload is ignored. */
7357 if (mips_pic
!= SVR4_PIC
)
7363 /* .cpload should be a in .set noreorder section. */
7364 if (mips_noreorder
== 0)
7365 as_warn (".cpload not in noreorder section");
7368 ex
.X_add_symbol
= symbol_find_or_make ("_gp_disp");
7369 ex
.X_op_symbol
= NULL
;
7370 ex
.X_add_number
= 0;
7372 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
7373 ex
.X_add_symbol
->bsym
->flags
|= BSF_OBJECT
;
7375 macro_build_lui ((char *) NULL
, &icnt
, &ex
, GP
);
7376 macro_build ((char *) NULL
, &icnt
, &ex
, "addiu", "t,r,j", GP
, GP
,
7377 (int) BFD_RELOC_LO16
);
7379 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "addu", "d,v,t",
7380 GP
, GP
, tc_get_register (0));
7382 demand_empty_rest_of_line ();
7385 /* Handle the .cprestore pseudo-op. This stores $gp into a given
7386 offset from $sp. The offset is remembered, and after making a PIC
7387 call $gp is restored from that location. */
7390 s_cprestore (ignore
)
7396 /* If we are not generating SVR4 PIC code, .cprestore is ignored. */
7397 if (mips_pic
!= SVR4_PIC
)
7403 mips_cprestore_offset
= get_absolute_expression ();
7405 ex
.X_op
= O_constant
;
7406 ex
.X_add_symbol
= NULL
;
7407 ex
.X_op_symbol
= NULL
;
7408 ex
.X_add_number
= mips_cprestore_offset
;
7410 macro_build ((char *) NULL
, &icnt
, &ex
,
7411 mips_isa
< 3 ? "sw" : "sd",
7412 "t,o(b)", GP
, (int) BFD_RELOC_LO16
, SP
);
7414 demand_empty_rest_of_line ();
7417 /* Handle the .gpword pseudo-op. This is used when generating PIC
7418 code. It generates a 32 bit GP relative reloc. */
7428 /* When not generating PIC code, this is treated as .word. */
7429 if (mips_pic
!= SVR4_PIC
)
7436 mips_emit_delays ();
7438 mips_align (2, 0, label
);
7443 if (ex
.X_op
!= O_symbol
|| ex
.X_add_number
!= 0)
7445 as_bad ("Unsupported use of .gpword");
7446 ignore_rest_of_line ();
7450 md_number_to_chars (p
, (valueT
) 0, 4);
7451 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 4, &ex
, 0,
7452 BFD_RELOC_MIPS_GPREL32
);
7454 demand_empty_rest_of_line ();
7457 /* Handle the .cpadd pseudo-op. This is used when dealing with switch
7458 tables in SVR4 PIC code. */
7467 /* This is ignored when not generating SVR4 PIC code. */
7468 if (mips_pic
!= SVR4_PIC
)
7474 /* Add $gp to the register named as an argument. */
7475 reg
= tc_get_register (0);
7476 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
7477 mips_isa
< 3 ? "addu" : "daddu",
7478 "d,v,t", reg
, reg
, GP
);
7480 demand_empty_rest_of_line ();
7483 /* Parse a register string into a number. Called from the ECOFF code
7484 to parse .frame. The argument is non-zero if this is the frame
7485 register, so that we can record it in mips_frame_reg. */
7488 tc_get_register (frame
)
7494 if (*input_line_pointer
++ != '$')
7496 as_warn ("expected `$'");
7499 else if (isdigit ((unsigned char) *input_line_pointer
))
7501 reg
= get_absolute_expression ();
7502 if (reg
< 0 || reg
>= 32)
7504 as_warn ("Bad register number");
7510 if (strncmp (input_line_pointer
, "fp", 2) == 0)
7512 else if (strncmp (input_line_pointer
, "sp", 2) == 0)
7514 else if (strncmp (input_line_pointer
, "gp", 2) == 0)
7516 else if (strncmp (input_line_pointer
, "at", 2) == 0)
7520 as_warn ("Unrecognized register name");
7523 input_line_pointer
+= 2;
7526 mips_frame_reg
= reg
!= 0 ? reg
: SP
;
7531 md_section_align (seg
, addr
)
7535 int align
= bfd_get_section_alignment (stdoutput
, seg
);
7538 /* We don't need to align ELF sections to the full alignment.
7539 However, Irix 5 may prefer that we align them at least to a 16
7545 return ((addr
+ (1 << align
) - 1) & (-1 << align
));
7548 /* Utility routine, called from above as well. If called while the
7549 input file is still being read, it's only an approximation. (For
7550 example, a symbol may later become defined which appeared to be
7551 undefined earlier.) */
7554 nopic_need_relax (sym
)
7560 if (USE_GLOBAL_POINTER_OPT
)
7562 const char *symname
;
7565 /* Find out whether this symbol can be referenced off the GP
7566 register. It can be if it is smaller than the -G size or if
7567 it is in the .sdata or .sbss section. Certain symbols can
7568 not be referenced off the GP, although it appears as though
7570 symname
= S_GET_NAME (sym
);
7571 if (symname
!= (const char *) NULL
7572 && (strcmp (symname
, "eprol") == 0
7573 || strcmp (symname
, "etext") == 0
7574 || strcmp (symname
, "_gp") == 0
7575 || strcmp (symname
, "edata") == 0
7576 || strcmp (symname
, "_fbss") == 0
7577 || strcmp (symname
, "_fdata") == 0
7578 || strcmp (symname
, "_ftext") == 0
7579 || strcmp (symname
, "end") == 0
7580 || strcmp (symname
, "_gp_disp") == 0))
7582 else if (! S_IS_DEFINED (sym
)
7584 #ifndef NO_ECOFF_DEBUGGING
7585 || (sym
->ecoff_extern_size
!= 0
7586 && sym
->ecoff_extern_size
<= g_switch_value
)
7588 || (S_GET_VALUE (sym
) != 0
7589 && S_GET_VALUE (sym
) <= g_switch_value
)))
7593 const char *segname
;
7595 segname
= segment_name (S_GET_SEGMENT (sym
));
7596 assert (strcmp (segname
, ".lit8") != 0
7597 && strcmp (segname
, ".lit4") != 0);
7598 change
= (strcmp (segname
, ".sdata") != 0
7599 && strcmp (segname
, ".sbss") != 0);
7604 /* We are not optimizing for the GP register. */
7608 /* Estimate the size of a frag before relaxing. We are not really
7609 relaxing here, and the final size is encoded in the subtype
7614 md_estimate_size_before_relax (fragp
, segtype
)
7620 if (mips_pic
== NO_PIC
)
7622 change
= nopic_need_relax (fragp
->fr_symbol
);
7624 else if (mips_pic
== SVR4_PIC
)
7626 asection
*symsec
= fragp
->fr_symbol
->bsym
->section
;
7628 /* This must duplicate the test in adjust_reloc_syms. */
7629 change
= (symsec
!= &bfd_und_section
7630 && symsec
!= &bfd_abs_section
7631 && ! bfd_is_com_section (symsec
));
7638 /* Record the offset to the first reloc in the fr_opcode field.
7639 This lets md_convert_frag and tc_gen_reloc know that the code
7640 must be expanded. */
7641 fragp
->fr_opcode
= (fragp
->fr_literal
7643 - RELAX_OLD (fragp
->fr_subtype
)
7644 + RELAX_RELOC1 (fragp
->fr_subtype
));
7645 /* FIXME: This really needs as_warn_where. */
7646 if (RELAX_WARN (fragp
->fr_subtype
))
7647 as_warn ("AT used after \".set noat\" or macro used after \".set nomacro\"");
7653 return RELAX_NEW (fragp
->fr_subtype
) - RELAX_OLD (fragp
->fr_subtype
);
7656 /* Translate internal representation of relocation info to BFD target
7660 tc_gen_reloc (section
, fixp
)
7664 static arelent
*retval
[4];
7666 bfd_reloc_code_real_type code
;
7668 reloc
= retval
[0] = (arelent
*) xmalloc (sizeof (arelent
));
7671 reloc
->sym_ptr_ptr
= &fixp
->fx_addsy
->bsym
;
7672 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
7674 if (mips_pic
== EMBEDDED_PIC
7675 && SWITCH_TABLE (fixp
))
7677 /* For a switch table entry we use a special reloc. The addend
7678 is actually the difference between the reloc address and the
7680 reloc
->addend
= reloc
->address
- S_GET_VALUE (fixp
->fx_subsy
);
7681 if (OUTPUT_FLAVOR
!= bfd_target_ecoff_flavour
)
7682 as_fatal ("Double check fx_r_type in tc-mips.c:tc_gen_reloc");
7683 fixp
->fx_r_type
= BFD_RELOC_GPREL32
;
7685 else if (fixp
->fx_r_type
== BFD_RELOC_PCREL_LO16
)
7687 /* We use a special addend for an internal RELLO reloc. */
7688 if (fixp
->fx_addsy
->bsym
->flags
& BSF_SECTION_SYM
)
7689 reloc
->addend
= reloc
->address
- S_GET_VALUE (fixp
->fx_subsy
);
7691 reloc
->addend
= fixp
->fx_addnumber
+ reloc
->address
;
7693 else if (fixp
->fx_r_type
== BFD_RELOC_PCREL_HI16_S
)
7695 assert (fixp
->fx_next
!= NULL
7696 && fixp
->fx_next
->fx_r_type
== BFD_RELOC_PCREL_LO16
);
7697 /* We use a special addend for an internal RELHI reloc. The
7698 reloc is relative to the RELLO; adjust the addend
7700 if (fixp
->fx_addsy
->bsym
->flags
& BSF_SECTION_SYM
)
7701 reloc
->addend
= (fixp
->fx_next
->fx_frag
->fr_address
7702 + fixp
->fx_next
->fx_where
7703 - S_GET_VALUE (fixp
->fx_subsy
));
7705 reloc
->addend
= (fixp
->fx_addnumber
7706 + fixp
->fx_next
->fx_frag
->fr_address
7707 + fixp
->fx_next
->fx_where
);
7709 else if (fixp
->fx_pcrel
== 0)
7710 reloc
->addend
= fixp
->fx_addnumber
;
7713 if (OUTPUT_FLAVOR
!= bfd_target_aout_flavour
)
7714 /* A gruesome hack which is a result of the gruesome gas reloc
7716 reloc
->addend
= reloc
->address
;
7718 reloc
->addend
= -reloc
->address
;
7721 /* If this is a variant frag, we may need to adjust the existing
7722 reloc and generate a new one. */
7723 if (fixp
->fx_frag
->fr_opcode
!= NULL
7724 && (fixp
->fx_r_type
== BFD_RELOC_MIPS_GPREL
7725 || fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT16
7726 || fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL16
7727 || fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT_HI16
7728 || fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT_LO16
7729 || fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL_HI16
7730 || fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL_LO16
))
7734 /* If this is not the last reloc in this frag, then we have two
7735 GPREL relocs, or a GOT_HI16/GOT_LO16 pair, or a
7736 CALL_HI16/CALL_LO16, both of which are being replaced. Let
7737 the second one handle all of them. */
7738 if (fixp
->fx_next
!= NULL
7739 && fixp
->fx_frag
== fixp
->fx_next
->fx_frag
)
7741 assert ((fixp
->fx_r_type
== BFD_RELOC_MIPS_GPREL
7742 && fixp
->fx_next
->fx_r_type
== BFD_RELOC_MIPS_GPREL
)
7743 || (fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT_HI16
7744 && (fixp
->fx_next
->fx_r_type
7745 == BFD_RELOC_MIPS_GOT_LO16
))
7746 || (fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL_HI16
7747 && (fixp
->fx_next
->fx_r_type
7748 == BFD_RELOC_MIPS_CALL_LO16
)));
7753 fixp
->fx_where
= fixp
->fx_frag
->fr_opcode
- fixp
->fx_frag
->fr_literal
;
7754 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
7755 reloc2
= retval
[1] = (arelent
*) xmalloc (sizeof (arelent
));
7757 reloc2
->sym_ptr_ptr
= &fixp
->fx_addsy
->bsym
;
7758 reloc2
->address
= (reloc
->address
7759 + (RELAX_RELOC2 (fixp
->fx_frag
->fr_subtype
)
7760 - RELAX_RELOC1 (fixp
->fx_frag
->fr_subtype
)));
7761 reloc2
->addend
= fixp
->fx_addnumber
;
7762 reloc2
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_LO16
);
7763 assert (reloc2
->howto
!= NULL
);
7765 if (RELAX_RELOC3 (fixp
->fx_frag
->fr_subtype
))
7769 reloc3
= retval
[2] = (arelent
*) xmalloc (sizeof (arelent
));
7772 reloc3
->address
+= 4;
7775 if (mips_pic
== NO_PIC
)
7777 assert (fixp
->fx_r_type
== BFD_RELOC_MIPS_GPREL
);
7778 fixp
->fx_r_type
= BFD_RELOC_HI16_S
;
7780 else if (mips_pic
== SVR4_PIC
)
7782 switch (fixp
->fx_r_type
)
7786 case BFD_RELOC_MIPS_GOT16
:
7788 case BFD_RELOC_MIPS_CALL16
:
7789 case BFD_RELOC_MIPS_GOT_LO16
:
7790 case BFD_RELOC_MIPS_CALL_LO16
:
7791 fixp
->fx_r_type
= BFD_RELOC_MIPS_GOT16
;
7799 /* Since DIFF_EXPR_OK is defined in tc-mips.h, it is possible that
7800 fixup_segment converted a non-PC relative reloc into a PC
7801 relative reloc. In such a case, we need to convert the reloc
7803 code
= fixp
->fx_r_type
;
7809 code
= BFD_RELOC_8_PCREL
;
7812 code
= BFD_RELOC_16_PCREL
;
7815 code
= BFD_RELOC_32_PCREL
;
7817 case BFD_RELOC_8_PCREL
:
7818 case BFD_RELOC_16_PCREL
:
7819 case BFD_RELOC_32_PCREL
:
7820 case BFD_RELOC_16_PCREL_S2
:
7821 case BFD_RELOC_PCREL_HI16_S
:
7822 case BFD_RELOC_PCREL_LO16
:
7825 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
7826 "Cannot make %s relocation PC relative",
7827 bfd_get_reloc_code_name (code
));
7831 /* To support a PC relative reloc when generating embedded PIC code
7832 for ECOFF, we use a Cygnus extension. We check for that here to
7833 make sure that we don't let such a reloc escape normally. */
7834 if (OUTPUT_FLAVOR
== bfd_target_ecoff_flavour
7835 && code
== BFD_RELOC_16_PCREL_S2
7836 && mips_pic
!= EMBEDDED_PIC
)
7837 reloc
->howto
= NULL
;
7839 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
7841 if (reloc
->howto
== NULL
)
7843 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
7844 "Can not represent %s relocation in this object file format",
7845 bfd_get_reloc_code_name (code
));
7852 /* Convert a machine dependent frag. */
7855 md_convert_frag (abfd
, asec
, fragp
)
7863 if (fragp
->fr_opcode
== NULL
)
7866 old
= RELAX_OLD (fragp
->fr_subtype
);
7867 new = RELAX_NEW (fragp
->fr_subtype
);
7868 fixptr
= fragp
->fr_literal
+ fragp
->fr_fix
;
7871 memcpy (fixptr
- old
, fixptr
, new);
7873 fragp
->fr_fix
+= new - old
;
7876 /* This function is called whenever a label is defined. It is used
7877 when handling branch delays; if a branch has a label, we assume we
7881 mips_define_label (sym
)
7887 /* Decide whether a label is local. This is called by LOCAL_LABEL.
7888 In order to work with gcc when using mips-tfile, we must keep all
7889 local labels. However, in other cases, we want to discard them,
7890 since they are useless. */
7893 mips_local_label (name
)
7896 #ifndef NO_ECOFF_DEBUGGING
7899 && ! ecoff_debugging_seen
)
7901 /* We were called with -g, but we didn't see any debugging
7902 information. That may mean that gcc is smuggling debugging
7903 information through to mips-tfile, in which case we must
7904 generate all local labels. */
7909 /* Here it's OK to discard local labels. */
7911 return name
[0] == '$';
7914 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7916 /* Some special processing for a MIPS ELF file. */
7919 mips_elf_final_processing ()
7921 /* Write out the register information. */
7926 s
.ri_gprmask
= mips_gprmask
;
7927 s
.ri_cprmask
[0] = mips_cprmask
[0];
7928 s
.ri_cprmask
[1] = mips_cprmask
[1];
7929 s
.ri_cprmask
[2] = mips_cprmask
[2];
7930 s
.ri_cprmask
[3] = mips_cprmask
[3];
7931 /* The gp_value field is set by the MIPS ELF backend. */
7933 bfd_mips_elf32_swap_reginfo_out (stdoutput
, &s
,
7934 ((Elf32_External_RegInfo
*)
7935 mips_regmask_frag
));
7939 Elf64_Internal_RegInfo s
;
7941 s
.ri_gprmask
= mips_gprmask
;
7943 s
.ri_cprmask
[0] = mips_cprmask
[0];
7944 s
.ri_cprmask
[1] = mips_cprmask
[1];
7945 s
.ri_cprmask
[2] = mips_cprmask
[2];
7946 s
.ri_cprmask
[3] = mips_cprmask
[3];
7947 /* The gp_value field is set by the MIPS ELF backend. */
7949 bfd_mips_elf64_swap_reginfo_out (stdoutput
, &s
,
7950 ((Elf64_External_RegInfo
*)
7951 mips_regmask_frag
));
7954 /* Set the MIPS ELF flag bits. FIXME: There should probably be some
7955 sort of BFD interface for this. */
7956 if (mips_any_noreorder
)
7957 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_NOREORDER
;
7958 if (mips_pic
!= NO_PIC
)
7959 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_PIC
;
7962 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */
7964 /* These functions should really be defined by the object file format,
7965 since they are related to debugging information. However, this
7966 code has to work for the a.out format, which does not define them,
7967 so we provide simple versions here. These don't actually generate
7968 any debugging information, but they do simple checking and someday
7969 somebody may make them useful. */
7973 struct loc
*loc_next
;
7974 unsigned long loc_fileno
;
7975 unsigned long loc_lineno
;
7976 unsigned long loc_offset
;
7977 unsigned short loc_delta
;
7978 unsigned short loc_count
;
7987 struct proc
*proc_next
;
7988 struct symbol
*proc_isym
;
7989 struct symbol
*proc_end
;
7990 unsigned long proc_reg_mask
;
7991 unsigned long proc_reg_offset
;
7992 unsigned long proc_fpreg_mask
;
7993 unsigned long proc_fpreg_offset
;
7994 unsigned long proc_frameoffset
;
7995 unsigned long proc_framereg
;
7996 unsigned long proc_pcreg
;
7998 struct file
*proc_file
;
8005 struct file
*file_next
;
8006 unsigned long file_fileno
;
8007 struct symbol
*file_symbol
;
8008 struct symbol
*file_end
;
8009 struct proc
*file_proc
;
8014 static struct obstack proc_frags
;
8015 static procS
*proc_lastP
;
8016 static procS
*proc_rootP
;
8017 static int numprocs
;
8022 obstack_begin (&proc_frags
, 0x2000);
8028 /* check for premature end, nesting errors, etc */
8029 if (proc_lastP
&& proc_lastP
->proc_end
== NULL
)
8030 as_warn ("missing `.end' at end of assembly");
8039 if (*input_line_pointer
== '-')
8041 ++input_line_pointer
;
8044 if (!isdigit (*input_line_pointer
))
8045 as_bad ("Expected simple number.");
8046 if (input_line_pointer
[0] == '0')
8048 if (input_line_pointer
[1] == 'x')
8050 input_line_pointer
+= 2;
8051 while (isxdigit (*input_line_pointer
))
8054 val
|= hex_value (*input_line_pointer
++);
8056 return negative
? -val
: val
;
8060 ++input_line_pointer
;
8061 while (isdigit (*input_line_pointer
))
8064 val
|= *input_line_pointer
++ - '0';
8066 return negative
? -val
: val
;
8069 if (!isdigit (*input_line_pointer
))
8071 printf (" *input_line_pointer == '%c' 0x%02x\n",
8072 *input_line_pointer
, *input_line_pointer
);
8073 as_warn ("Invalid number");
8076 while (isdigit (*input_line_pointer
))
8079 val
+= *input_line_pointer
++ - '0';
8081 return negative
? -val
: val
;
8084 /* The .file directive; just like the usual .file directive, but there
8085 is an initial number which is the ECOFF file index. */
8093 line
= get_number ();
8098 /* The .end directive. */
8106 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
8109 demand_empty_rest_of_line ();
8113 if (now_seg
!= text_section
)
8114 as_warn (".end not in text section");
8117 as_warn (".end and no .ent seen yet.");
8123 assert (S_GET_NAME (p
));
8124 if (strcmp (S_GET_NAME (p
), S_GET_NAME (proc_lastP
->proc_isym
)))
8125 as_warn (".end symbol does not match .ent symbol.");
8128 proc_lastP
->proc_end
= (symbolS
*) 1;
8131 /* The .aent and .ent directives. */
8141 symbolP
= get_symbol ();
8142 if (*input_line_pointer
== ',')
8143 input_line_pointer
++;
8145 if (isdigit (*input_line_pointer
) || *input_line_pointer
== '-')
8146 number
= get_number ();
8147 if (now_seg
!= text_section
)
8148 as_warn (".ent or .aent not in text section.");
8150 if (!aent
&& proc_lastP
&& proc_lastP
->proc_end
== NULL
)
8151 as_warn ("missing `.end'");
8155 procP
= (procS
*) obstack_alloc (&proc_frags
, sizeof (*procP
));
8156 procP
->proc_isym
= symbolP
;
8157 procP
->proc_reg_mask
= 0;
8158 procP
->proc_reg_offset
= 0;
8159 procP
->proc_fpreg_mask
= 0;
8160 procP
->proc_fpreg_offset
= 0;
8161 procP
->proc_frameoffset
= 0;
8162 procP
->proc_framereg
= 0;
8163 procP
->proc_pcreg
= 0;
8164 procP
->proc_end
= NULL
;
8165 procP
->proc_next
= NULL
;
8167 proc_lastP
->proc_next
= procP
;
8173 demand_empty_rest_of_line ();
8176 /* The .frame directive. */
8189 frame_reg
= tc_get_register (1);
8190 if (*input_line_pointer
== ',')
8191 input_line_pointer
++;
8192 frame_off
= get_absolute_expression ();
8193 if (*input_line_pointer
== ',')
8194 input_line_pointer
++;
8195 pcreg
= tc_get_register (0);
8198 assert (proc_rootP
);
8199 proc_rootP
->proc_framereg
= frame_reg
;
8200 proc_rootP
->proc_frameoffset
= frame_off
;
8201 proc_rootP
->proc_pcreg
= pcreg
;
8202 /* bob macho .frame */
8204 /* We don't have to write out a frame stab for unoptimized code. */
8205 if (!(frame_reg
== FP
&& frame_off
== 0))
8208 as_warn ("No .ent for .frame to use.");
8209 (void) sprintf (str
, "R%d;%d", frame_reg
, frame_off
);
8210 symP
= symbol_new (str
, N_VFP
, 0, frag_now
);
8211 S_SET_TYPE (symP
, N_RMASK
);
8212 S_SET_OTHER (symP
, 0);
8213 S_SET_DESC (symP
, 0);
8214 symP
->sy_forward
= proc_lastP
->proc_isym
;
8215 /* bob perhaps I should have used pseudo set */
8217 demand_empty_rest_of_line ();
8221 /* The .fmask and .mask directives. */
8228 char str
[100], *strP
;
8234 mask
= get_number ();
8235 if (*input_line_pointer
== ',')
8236 input_line_pointer
++;
8237 off
= get_absolute_expression ();
8239 /* bob only for coff */
8240 assert (proc_rootP
);
8241 if (reg_type
== 'F')
8243 proc_rootP
->proc_fpreg_mask
= mask
;
8244 proc_rootP
->proc_fpreg_offset
= off
;
8248 proc_rootP
->proc_reg_mask
= mask
;
8249 proc_rootP
->proc_reg_offset
= off
;
8252 /* bob macho .mask + .fmask */
8254 /* We don't have to write out a mask stab if no saved regs. */
8258 as_warn ("No .ent for .mask to use.");
8260 for (i
= 0; i
< 32; i
++)
8264 sprintf (strP
, "%c%d,", reg_type
, i
);
8265 strP
+= strlen (strP
);
8269 sprintf (strP
, ";%d,", off
);
8270 symP
= symbol_new (str
, N_RMASK
, 0, frag_now
);
8271 S_SET_TYPE (symP
, N_RMASK
);
8272 S_SET_OTHER (symP
, 0);
8273 S_SET_DESC (symP
, 0);
8274 symP
->sy_forward
= proc_lastP
->proc_isym
;
8275 /* bob perhaps I should have used pseudo set */
8280 /* The .loc directive. */
8291 assert (now_seg
== text_section
);
8293 lineno
= get_number ();
8294 addroff
= frag_now_fix ();
8296 symbolP
= symbol_new ("", N_SLINE
, addroff
, frag_now
);
8297 S_SET_TYPE (symbolP
, N_SLINE
);
8298 S_SET_OTHER (symbolP
, 0);
8299 S_SET_DESC (symbolP
, lineno
);
8300 symbolP
->sy_segment
= now_seg
;