1 /* tc-mips.c -- assemble code for a MIPS chip.
2 Copyright (C) 1993, 1995, 1996 Free Software Foundation, Inc.
3 Contributed by the OSF and Ralph Campbell.
4 Written by Keith Knowles and Ralph Campbell, working independently.
5 Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus
8 This file is part of GAS.
10 GAS is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 2, or (at your option)
15 GAS is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with GAS; see the file COPYING. If not, write to the Free
22 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
38 #include "opcode/mips.h"
41 /* Clean up namespace so we can include obj-elf.h too. */
42 static int mips_output_flavor () { return OUTPUT_FLAVOR
; }
43 #undef OBJ_PROCESS_STAB
49 #undef TARGET_SYMBOL_FIELDS
51 #undef obj_frob_file_after_relocs
52 #undef obj_frob_symbol
54 #undef obj_sec_sym_ok_for_reloc
57 /* Fix any of them that we actually care about. */
59 #define OUTPUT_FLAVOR mips_output_flavor()
66 #ifndef ECOFF_DEBUGGING
67 #define NO_ECOFF_DEBUGGING
68 #define ECOFF_DEBUGGING 0
73 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
74 static char *mips_regmask_frag
;
79 #define PIC_CALL_REG 25
87 #define ILLEGAL_REG (32)
89 extern int target_big_endian
;
91 /* 1 is we should use the 64 bit MIPS ELF ABI, 0 if we should use the
92 32 bit ABI. This has no meaning for ECOFF. */
95 /* The default target format to use. */
99 switch (OUTPUT_FLAVOR
)
101 case bfd_target_aout_flavour
:
102 return target_big_endian
? "a.out-mips-big" : "a.out-mips-little";
103 case bfd_target_ecoff_flavour
:
104 return target_big_endian
? "ecoff-bigmips" : "ecoff-littlemips";
105 case bfd_target_elf_flavour
:
106 return (target_big_endian
107 ? (mips_64
? "elf64-bigmips" : "elf32-bigmips")
108 : (mips_64
? "elf64-littlemips" : "elf32-littlemips"));
114 /* The name of the readonly data section. */
115 #define RDATA_SECTION_NAME (OUTPUT_FLAVOR == bfd_target_aout_flavour \
117 : OUTPUT_FLAVOR == bfd_target_ecoff_flavour \
119 : OUTPUT_FLAVOR == bfd_target_elf_flavour \
123 /* These variables are filled in with the masks of registers used.
124 The object format code reads them and puts them in the appropriate
126 unsigned long mips_gprmask
;
127 unsigned long mips_cprmask
[4];
129 /* MIPS ISA (Instruction Set Architecture) level (may be changed
130 temporarily using .set mipsN). */
131 static int mips_isa
= -1;
133 /* MIPS ISA we are using for this output file. */
134 static int file_mips_isa
;
136 /* Whether we are assembling for the mips16 processor. */
137 static int mips16
= -1;
139 /* The CPU type as a number: 2000, 3000, 4000, 4400, etc. */
140 static int mips_cpu
= -1;
142 /* Whether the 4650 instructions (mad/madu) are permitted. */
143 static int mips_4650
= -1;
145 /* Whether the 4010 instructions are permitted. */
146 static int mips_4010
= -1;
148 /* Whether the 4100 MADD16 and DMADD16 are permitted. */
149 static int mips_4100
= -1;
151 /* Whether the processor uses hardware interlocks, and thus does not
152 require nops to be inserted. */
153 static int interlocks
= -1;
155 /* As with "interlocks" this is used by hardware that has FP
156 (co-processor) interlocks. */
157 static int cop_interlocks
= -1;
159 /* MIPS PIC level. */
163 /* Do not generate PIC code. */
166 /* Generate PIC code as in Irix 4. This is not implemented, and I'm
167 not sure what it is supposed to do. */
170 /* Generate PIC code as in the SVR4 MIPS ABI. */
173 /* Generate PIC code without using a global offset table: the data
174 segment has a maximum size of 64K, all data references are off
175 the $gp register, and all text references are PC relative. This
176 is used on some embedded systems. */
180 static enum mips_pic_level mips_pic
;
182 /* 1 if we should generate 32 bit offsets from the GP register in
183 SVR4_PIC mode. Currently has no meaning in other modes. */
184 static int mips_big_got
;
186 /* 1 if trap instructions should used for overflow rather than break
188 static int mips_trap
;
190 /* 1 if we should autoextend mips16 instructions. */
191 static int mips16_autoextend
= 1;
193 static int mips_warn_about_macros
;
194 static int mips_noreorder
;
195 static int mips_any_noreorder
;
196 static int mips_nomove
;
197 static int mips_noat
;
198 static int mips_nobopt
;
200 /* The size of the small data section. */
201 static int g_switch_value
= 8;
202 /* Whether the -G option was used. */
203 static int g_switch_seen
= 0;
208 /* If we can determine in advance that GP optimization won't be
209 possible, we can skip the relaxation stuff that tries to produce
210 GP-relative references. This makes delay slot optimization work
213 This function can only provide a guess, but it seems to work for
214 gcc output. If it guesses wrong, the only loss should be in
215 efficiency; it shouldn't introduce any bugs.
217 I don't know if a fix is needed for the SVR4_PIC mode. I've only
218 fixed it for the non-PIC mode. KR 95/04/07 */
219 static int nopic_need_relax
PARAMS ((symbolS
*));
221 /* handle of the OPCODE hash table */
222 static struct hash_control
*op_hash
= NULL
;
224 /* The opcode hash table we use for the mips16. */
225 static struct hash_control
*mips16_op_hash
= NULL
;
227 /* This array holds the chars that always start a comment. If the
228 pre-processor is disabled, these aren't very useful */
229 const char comment_chars
[] = "#";
231 /* This array holds the chars that only start a comment at the beginning of
232 a line. If the line seems to have the form '# 123 filename'
233 .line and .file directives will appear in the pre-processed output */
234 /* Note that input_file.c hand checks for '#' at the beginning of the
235 first line of the input file. This is because the compiler outputs
236 #NO_APP at the beginning of its output. */
237 /* Also note that C style comments are always supported. */
238 const char line_comment_chars
[] = "#";
240 /* This array holds machine specific line separator characters. */
241 const char line_separator_chars
[] = "";
243 /* Chars that can be used to separate mant from exp in floating point nums */
244 const char EXP_CHARS
[] = "eE";
246 /* Chars that mean this number is a floating point constant */
249 const char FLT_CHARS
[] = "rRsSfFdDxXpP";
251 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
252 changed in read.c . Ideally it shouldn't have to know about it at all,
253 but nothing is ideal around here.
256 static char *insn_error
;
258 static int byte_order
;
260 static int auto_align
= 1;
262 /* Symbol labelling the current insn. */
263 static symbolS
*insn_label
;
265 /* When outputting SVR4 PIC code, the assembler needs to know the
266 offset in the stack frame from which to restore the $gp register.
267 This is set by the .cprestore pseudo-op, and saved in this
269 static offsetT mips_cprestore_offset
= -1;
271 /* This is the register which holds the stack frame, as set by the
272 .frame pseudo-op. This is needed to implement .cprestore. */
273 static int mips_frame_reg
= SP
;
275 /* To output NOP instructions correctly, we need to keep information
276 about the previous two instructions. */
278 /* Whether we are optimizing. The default value of 2 means to remove
279 unneeded NOPs and swap branch instructions when possible. A value
280 of 1 means to not swap branches. A value of 0 means to always
282 static int mips_optimize
= 2;
284 /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is
285 equivalent to seeing no -g option at all. */
286 static int mips_debug
= 0;
288 /* The previous instruction. */
289 static struct mips_cl_insn prev_insn
;
291 /* The instruction before prev_insn. */
292 static struct mips_cl_insn prev_prev_insn
;
294 /* If we don't want information for prev_insn or prev_prev_insn, we
295 point the insn_mo field at this dummy integer. */
296 static const struct mips_opcode dummy_opcode
= { 0 };
298 /* Non-zero if prev_insn is valid. */
299 static int prev_insn_valid
;
301 /* The frag for the previous instruction. */
302 static struct frag
*prev_insn_frag
;
304 /* The offset into prev_insn_frag for the previous instruction. */
305 static long prev_insn_where
;
307 /* The reloc for the previous instruction, if any. */
308 static fixS
*prev_insn_fixp
;
310 /* Non-zero if the previous instruction was in a delay slot. */
311 static int prev_insn_is_delay_slot
;
313 /* Non-zero if the previous instruction was in a .set noreorder. */
314 static int prev_insn_unreordered
;
316 /* Non-zero if the previous instruction uses an extend opcode (if
318 static int prev_insn_extended
;
320 /* Non-zero if the previous previous instruction was in a .set
322 static int prev_prev_insn_unreordered
;
324 /* For ECOFF and ELF, relocations against symbols are done in two
325 parts, with a HI relocation and a LO relocation. Each relocation
326 has only 16 bits of space to store an addend. This means that in
327 order for the linker to handle carries correctly, it must be able
328 to locate both the HI and the LO relocation. This means that the
329 relocations must appear in order in the relocation table.
331 In order to implement this, we keep track of each unmatched HI
332 relocation. We then sort them so that they immediately precede the
333 corresponding LO relocation. */
338 struct mips_hi_fixup
*next
;
341 /* The section this fixup is in. */
345 /* The list of unmatched HI relocs. */
347 static struct mips_hi_fixup
*mips_hi_fixup_list
;
349 /* Map normal MIPS register numbers to mips16 register numbers. */
351 #define X ILLEGAL_REG
352 static const int mips32_to_16_reg_map
[] =
354 X
, X
, 2, 3, 4, 5, 6, 7,
355 X
, X
, X
, X
, X
, X
, X
, X
,
356 0, 1, X
, X
, X
, X
, X
, X
,
357 X
, X
, X
, X
, X
, X
, X
, X
361 /* Map mips16 register numbers to normal MIPS register numbers. */
363 static const int mips16_to_32_reg_map
[] =
365 16, 17, 2, 3, 4, 5, 6, 7
368 /* Since the MIPS does not have multiple forms of PC relative
369 instructions, we do not have to do relaxing as is done on other
370 platforms. However, we do have to handle GP relative addressing
371 correctly, which turns out to be a similar problem.
373 Every macro that refers to a symbol can occur in (at least) two
374 forms, one with GP relative addressing and one without. For
375 example, loading a global variable into a register generally uses
376 a macro instruction like this:
378 If i can be addressed off the GP register (this is true if it is in
379 the .sbss or .sdata section, or if it is known to be smaller than
380 the -G argument) this will generate the following instruction:
382 This instruction will use a GPREL reloc. If i can not be addressed
383 off the GP register, the following instruction sequence will be used:
386 In this case the first instruction will have a HI16 reloc, and the
387 second reloc will have a LO16 reloc. Both relocs will be against
390 The issue here is that we may not know whether i is GP addressable
391 until after we see the instruction that uses it. Therefore, we
392 want to be able to choose the final instruction sequence only at
393 the end of the assembly. This is similar to the way other
394 platforms choose the size of a PC relative instruction only at the
397 When generating position independent code we do not use GP
398 addressing in quite the same way, but the issue still arises as
399 external symbols and local symbols must be handled differently.
401 We handle these issues by actually generating both possible
402 instruction sequences. The longer one is put in a frag_var with
403 type rs_machine_dependent. We encode what to do with the frag in
404 the subtype field. We encode (1) the number of existing bytes to
405 replace, (2) the number of new bytes to use, (3) the offset from
406 the start of the existing bytes to the first reloc we must generate
407 (that is, the offset is applied from the start of the existing
408 bytes after they are replaced by the new bytes, if any), (4) the
409 offset from the start of the existing bytes to the second reloc,
410 (5) whether a third reloc is needed (the third reloc is always four
411 bytes after the second reloc), and (6) whether to warn if this
412 variant is used (this is sometimes needed if .set nomacro or .set
413 noat is in effect). All these numbers are reasonably small.
415 Generating two instruction sequences must be handled carefully to
416 ensure that delay slots are handled correctly. Fortunately, there
417 are a limited number of cases. When the second instruction
418 sequence is generated, append_insn is directed to maintain the
419 existing delay slot information, so it continues to apply to any
420 code after the second instruction sequence. This means that the
421 second instruction sequence must not impose any requirements not
422 required by the first instruction sequence.
424 These variant frags are then handled in functions called by the
425 machine independent code. md_estimate_size_before_relax returns
426 the final size of the frag. md_convert_frag sets up the final form
427 of the frag. tc_gen_reloc adjust the first reloc and adds a second
429 #define RELAX_ENCODE(old, new, reloc1, reloc2, reloc3, warn) \
433 | (((reloc1) + 64) << 9) \
434 | (((reloc2) + 64) << 2) \
435 | ((reloc3) ? (1 << 1) : 0) \
437 #define RELAX_OLD(i) (((i) >> 23) & 0x7f)
438 #define RELAX_NEW(i) (((i) >> 16) & 0x7f)
439 #define RELAX_RELOC1(i) ((bfd_vma)(((i) >> 9) & 0x7f) - 64)
440 #define RELAX_RELOC2(i) ((bfd_vma)(((i) >> 2) & 0x7f) - 64)
441 #define RELAX_RELOC3(i) (((i) >> 1) & 1)
442 #define RELAX_WARN(i) ((i) & 1)
444 /* For mips16 code, we use an entirely different form of relaxation.
445 mips16 supports two versions of most instructions which take
446 immediate values: a small one which takes some small value, and a
447 larger one which takes a 16 bit value. Since branches also follow
448 this pattern, relaxing these values is required.
450 We can assemble both mips16 and normal MIPS code in a single
451 object. Therefore, we need to support this type of relaxation at
452 the same time that we support the relaxation described above. We
453 use the high bit of the subtype field to distinguish these cases.
455 The information we store for this type of relaxation is simply the
456 argument code found in the opcode file for this relocation, and
457 whether the user explicitly requested a small or extended form.
458 That tells us the size of the value, and how it should be stored.
459 We also store whether the fragment is considered to be extended or
460 not. We also store whether this is known to be a branch to a
461 different section, whether we have tried to relax this frag yet,
462 and whether we have ever extended a PC relative fragment because of
464 #define RELAX_MIPS16_ENCODE(type, small, ext) \
467 | ((small) ? 0x100 : 0) \
468 | ((ext) ? 0x200 : 0))
469 #define RELAX_MIPS16_P(i) (((i) & 0x80000000) != 0)
470 #define RELAX_MIPS16_TYPE(i) ((i) & 0xff)
471 #define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x100) != 0)
472 #define RELAX_MIPS16_USER_EXT(i) (((i) & 0x200) != 0)
473 #define RELAX_MIPS16_EXTENDED(i) (((i) & 0x400) != 0)
474 #define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x400)
475 #define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) &~ 0x400)
476 #define RELAX_MIPS16_LONG_BRANCH(i) (((i) & 0x800) != 0)
477 #define RELAX_MIPS16_MARK_LONG_BRANCH(i) ((i) | 0x800)
478 #define RELAX_MIPS16_CLEAR_LONG_BRANCH(i) ((i) &~ 0x800)
480 /* Prototypes for static functions. */
483 #define internalError() \
484 as_fatal ("internal Error, line %d, %s", __LINE__, __FILE__)
486 #define internalError() as_fatal ("MIPS internal Error");
489 enum mips_regclass
{ MIPS_GR_REG
, MIPS_FP_REG
, MIPS16_REG
};
491 static int insn_uses_reg
PARAMS ((struct mips_cl_insn
*ip
,
492 unsigned int reg
, enum mips_regclass
class));
493 static int reg_needs_delay
PARAMS ((int));
494 static void append_insn
PARAMS ((char *place
,
495 struct mips_cl_insn
* ip
,
497 bfd_reloc_code_real_type r
,
499 static void mips_no_prev_insn
PARAMS ((void));
500 static void mips_emit_delays
PARAMS ((void));
502 static void macro_build
PARAMS ((char *place
, int *counter
, expressionS
* ep
,
503 const char *name
, const char *fmt
,
506 static void macro_build ();
508 static void mips16_macro_build
PARAMS ((char *, int *, expressionS
*,
509 const char *, const char *,
511 static void macro_build_lui
PARAMS ((char *place
, int *counter
,
512 expressionS
* ep
, int regnum
));
513 static void set_at
PARAMS ((int *counter
, int reg
, int unsignedp
));
514 static void check_absolute_expr
PARAMS ((struct mips_cl_insn
* ip
,
516 static void load_register
PARAMS ((int *, int, expressionS
*, int));
517 static void load_address
PARAMS ((int *counter
, int reg
, expressionS
*ep
));
518 static void macro
PARAMS ((struct mips_cl_insn
* ip
));
519 static void mips16_macro
PARAMS ((struct mips_cl_insn
* ip
));
520 #ifdef LOSING_COMPILER
521 static void macro2
PARAMS ((struct mips_cl_insn
* ip
));
523 static void mips_ip
PARAMS ((char *str
, struct mips_cl_insn
* ip
));
524 static void mips16_ip
PARAMS ((char *str
, struct mips_cl_insn
* ip
));
525 static void mips16_immed
PARAMS ((char *, unsigned int, int, offsetT
, boolean
,
526 boolean
, boolean
, unsigned long *,
527 boolean
*, unsigned short *));
528 static int my_getSmallExpression
PARAMS ((expressionS
* ep
, char *str
));
529 static void my_getExpression
PARAMS ((expressionS
* ep
, char *str
));
530 static symbolS
*get_symbol
PARAMS ((void));
531 static void mips_align
PARAMS ((int to
, int fill
, symbolS
*label
));
532 static void s_align
PARAMS ((int));
533 static void s_change_sec
PARAMS ((int));
534 static void s_cons
PARAMS ((int));
535 static void s_float_cons
PARAMS ((int));
536 static void s_mips_globl
PARAMS ((int));
537 static void s_option
PARAMS ((int));
538 static void s_mipsset
PARAMS ((int));
539 static void s_abicalls
PARAMS ((int));
540 static void s_cpload
PARAMS ((int));
541 static void s_cprestore
PARAMS ((int));
542 static void s_gpword
PARAMS ((int));
543 static void s_cpadd
PARAMS ((int));
544 static void md_obj_begin
PARAMS ((void));
545 static void md_obj_end
PARAMS ((void));
546 static long get_number
PARAMS ((void));
547 static void s_ent
PARAMS ((int));
548 static void s_mipsend
PARAMS ((int));
549 static void s_file
PARAMS ((int));
550 static int mips16_extended_frag
PARAMS ((fragS
*, asection
*, long));
554 The following pseudo-ops from the Kane and Heinrich MIPS book
555 should be defined here, but are currently unsupported: .alias,
556 .galive, .gjaldef, .gjrlive, .livereg, .noalias.
558 The following pseudo-ops from the Kane and Heinrich MIPS book are
559 specific to the type of debugging information being generated, and
560 should be defined by the object format: .aent, .begin, .bend,
561 .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp,
564 The following pseudo-ops from the Kane and Heinrich MIPS book are
565 not MIPS CPU specific, but are also not specific to the object file
566 format. This file is probably the best place to define them, but
567 they are not currently supported: .asm0, .endr, .lab, .repeat,
568 .struct, .weakext. */
570 static const pseudo_typeS mips_pseudo_table
[] =
572 /* MIPS specific pseudo-ops. */
573 {"option", s_option
, 0},
574 {"set", s_mipsset
, 0},
575 {"rdata", s_change_sec
, 'r'},
576 {"sdata", s_change_sec
, 's'},
577 {"livereg", s_ignore
, 0},
578 {"abicalls", s_abicalls
, 0},
579 {"cpload", s_cpload
, 0},
580 {"cprestore", s_cprestore
, 0},
581 {"gpword", s_gpword
, 0},
582 {"cpadd", s_cpadd
, 0},
584 /* Relatively generic pseudo-ops that happen to be used on MIPS
586 {"asciiz", stringer
, 1},
587 {"bss", s_change_sec
, 'b'},
590 {"dword", s_cons
, 3},
592 /* These pseudo-ops are defined in read.c, but must be overridden
593 here for one reason or another. */
594 {"align", s_align
, 0},
596 {"data", s_change_sec
, 'd'},
597 {"double", s_float_cons
, 'd'},
598 {"float", s_float_cons
, 'f'},
599 {"globl", s_mips_globl
, 0},
600 {"global", s_mips_globl
, 0},
601 {"hword", s_cons
, 1},
606 {"short", s_cons
, 1},
607 {"single", s_float_cons
, 'f'},
608 {"text", s_change_sec
, 't'},
613 static const pseudo_typeS mips_nonecoff_pseudo_table
[] = {
614 /* These pseudo-ops should be defined by the object file format.
615 However, a.out doesn't support them, so we have versions here. */
617 {"bgnb", s_ignore
, 0},
618 {"end", s_mipsend
, 0},
619 {"endb", s_ignore
, 0},
622 {"fmask", s_ignore
, 'F'},
623 {"frame", s_ignore
, 0},
624 {"loc", s_ignore
, 0},
625 {"mask", s_ignore
, 'R'},
626 {"verstamp", s_ignore
, 0},
630 extern void pop_insert
PARAMS ((const pseudo_typeS
*));
635 pop_insert (mips_pseudo_table
);
636 if (! ECOFF_DEBUGGING
)
637 pop_insert (mips_nonecoff_pseudo_table
);
640 static char *expr_end
;
642 /* Expressions which appear in instructions. These are set by
645 static expressionS imm_expr
;
646 static expressionS offset_expr
;
648 /* Relocs associated with imm_expr and offset_expr. */
650 static bfd_reloc_code_real_type imm_reloc
;
651 static bfd_reloc_code_real_type offset_reloc
;
653 /* This is set by mips_ip if imm_reloc is an unmatched HI16_S reloc. */
655 static boolean imm_unmatched_hi
;
657 /* These are set by mips16_ip if an explicit extension is used. */
659 static boolean mips16_small
, mips16_ext
;
662 * This function is called once, at assembler startup time. It should
663 * set up all the tables, etc. that the MD part of the assembler will need.
669 register const char *retval
= NULL
;
670 register unsigned int i
= 0;
678 if (strcmp (cpu
+ (sizeof TARGET_CPU
) - 3, "el") == 0)
680 a
= xmalloc (sizeof TARGET_CPU
);
681 strcpy (a
, TARGET_CPU
);
682 a
[(sizeof TARGET_CPU
) - 3] = '\0';
686 if (strcmp (cpu
, "mips") == 0)
692 else if (strcmp (cpu
, "r6000") == 0
693 || strcmp (cpu
, "mips2") == 0)
699 else if (strcmp (cpu
, "mips64") == 0
700 || strcmp (cpu
, "r4000") == 0
701 || strcmp (cpu
, "mips3") == 0)
707 else if (strcmp (cpu
, "r4400") == 0)
713 else if (strcmp (cpu
, "mips64orion") == 0
714 || strcmp (cpu
, "r4600") == 0)
720 else if (strcmp (cpu
, "r4650") == 0)
728 else if (strcmp (cpu
, "mips64vr4300") == 0)
734 else if (strcmp (cpu
, "mips64vr4100") == 0)
742 else if (strcmp (cpu
, "r4010") == 0)
750 else if (strcmp (cpu
, "r5000") == 0
751 || strcmp (cpu
, "mips64vr5000") == 0)
757 else if (strcmp (cpu
, "r8000") == 0
758 || strcmp (cpu
, "mips4") == 0)
764 else if (strcmp (cpu
, "r10000") == 0)
770 else if (strcmp (cpu
, "mips16") == 0)
774 mips_cpu
= 0; /* FIXME */
789 if (strncmp (TARGET_CPU
, "mips16", sizeof "mips16" - 1) == 0)
804 if (mips_4650
|| mips_4010
|| mips_4100
|| mips_cpu
== 4300)
809 if (mips_cpu
== 4300)
814 if (mips_isa
< 2 && mips_trap
)
815 as_bad ("trap exception not supported at ISA 1");
820 ok
= bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, 3000);
823 ok
= bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, 6000);
826 ok
= bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, 4000);
829 ok
= bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, 8000);
833 as_warn ("Could not set architecture and machine");
835 file_mips_isa
= mips_isa
;
837 op_hash
= hash_new ();
839 for (i
= 0; i
< NUMOPCODES
;)
841 const char *name
= mips_opcodes
[i
].name
;
843 retval
= hash_insert (op_hash
, name
, (PTR
) &mips_opcodes
[i
]);
846 fprintf (stderr
, "internal error: can't hash `%s': %s\n",
847 mips_opcodes
[i
].name
, retval
);
848 as_fatal ("Broken assembler. No assembly attempted.");
852 if (mips_opcodes
[i
].pinfo
!= INSN_MACRO
853 && ((mips_opcodes
[i
].match
& mips_opcodes
[i
].mask
)
854 != mips_opcodes
[i
].match
))
856 fprintf (stderr
, "internal error: bad opcode: `%s' \"%s\"\n",
857 mips_opcodes
[i
].name
, mips_opcodes
[i
].args
);
858 as_fatal ("Broken assembler. No assembly attempted.");
862 while ((i
< NUMOPCODES
) && !strcmp (mips_opcodes
[i
].name
, name
));
865 mips16_op_hash
= hash_new ();
868 while (i
< bfd_mips16_num_opcodes
)
870 const char *name
= mips16_opcodes
[i
].name
;
872 retval
= hash_insert (mips16_op_hash
, name
, (PTR
) &mips16_opcodes
[i
]);
874 as_fatal ("internal error: can't hash `%s': %s\n",
875 mips16_opcodes
[i
].name
, retval
);
878 if (mips16_opcodes
[i
].pinfo
!= INSN_MACRO
879 && ((mips16_opcodes
[i
].match
& mips16_opcodes
[i
].mask
)
880 != mips16_opcodes
[i
].match
))
881 as_fatal ("internal error: bad opcode: `%s' \"%s\"\n",
882 mips16_opcodes
[i
].name
, mips16_opcodes
[i
].args
);
885 while (i
< bfd_mips16_num_opcodes
886 && strcmp (mips16_opcodes
[i
].name
, name
) == 0);
889 mips_no_prev_insn ();
897 /* set the default alignment for the text section (2**2) */
898 record_alignment (text_section
, 2);
900 if (USE_GLOBAL_POINTER_OPT
)
901 bfd_set_gp_size (stdoutput
, g_switch_value
);
903 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
905 /* Sections must be aligned to 16 byte boundaries. */
906 (void) bfd_set_section_alignment (stdoutput
, text_section
, 4);
907 (void) bfd_set_section_alignment (stdoutput
, data_section
, 4);
908 (void) bfd_set_section_alignment (stdoutput
, bss_section
, 4);
910 /* Create a .reginfo section for register masks and a .mdebug
911 section for debugging information. */
922 sec
= subseg_new (".reginfo", (subsegT
) 0);
924 /* The ABI says this section should be loaded so that the
925 running program can access it. */
926 (void) bfd_set_section_flags (stdoutput
, sec
,
927 (SEC_ALLOC
| SEC_LOAD
928 | SEC_READONLY
| SEC_DATA
));
929 (void) bfd_set_section_alignment (stdoutput
, sec
, 2);
932 mips_regmask_frag
= frag_more (sizeof (Elf32_External_RegInfo
));
937 /* The 64-bit ABI uses a .MIPS.options section rather than
939 sec
= subseg_new (".MIPS.options", (subsegT
) 0);
940 (void) bfd_set_section_flags (stdoutput
, sec
,
941 (SEC_ALLOC
| SEC_LOAD
942 | SEC_READONLY
| SEC_DATA
));
943 (void) bfd_set_section_alignment (stdoutput
, sec
, 3);
946 /* Set up the option header. */
948 Elf_Internal_Options opthdr
;
951 opthdr
.kind
= ODK_REGINFO
;
952 opthdr
.size
= (sizeof (Elf_External_Options
)
953 + sizeof (Elf64_External_RegInfo
));
956 f
= frag_more (sizeof (Elf_External_Options
));
957 bfd_mips_elf_swap_options_out (stdoutput
, &opthdr
,
958 (Elf_External_Options
*) f
);
960 mips_regmask_frag
= frag_more (sizeof (Elf64_External_RegInfo
));
967 sec
= subseg_new (".mdebug", (subsegT
) 0);
968 (void) bfd_set_section_flags (stdoutput
, sec
,
969 SEC_HAS_CONTENTS
| SEC_READONLY
);
970 (void) bfd_set_section_alignment (stdoutput
, sec
, 2);
973 subseg_set (seg
, subseg
);
977 if (! ECOFF_DEBUGGING
)
984 if (! ECOFF_DEBUGGING
)
992 struct mips_cl_insn insn
;
994 imm_expr
.X_op
= O_absent
;
995 imm_reloc
= BFD_RELOC_UNUSED
;
996 imm_unmatched_hi
= false;
997 offset_expr
.X_op
= O_absent
;
998 offset_reloc
= BFD_RELOC_UNUSED
;
1001 mips16_ip (str
, &insn
);
1003 mips_ip (str
, &insn
);
1007 as_bad ("%s `%s'", insn_error
, str
);
1011 if (insn
.insn_mo
->pinfo
== INSN_MACRO
)
1014 mips16_macro (&insn
);
1020 if (imm_expr
.X_op
!= O_absent
)
1021 append_insn ((char *) NULL
, &insn
, &imm_expr
, imm_reloc
,
1023 else if (offset_expr
.X_op
!= O_absent
)
1024 append_insn ((char *) NULL
, &insn
, &offset_expr
, offset_reloc
, false);
1026 append_insn ((char *) NULL
, &insn
, NULL
, BFD_RELOC_UNUSED
, false);
1030 /* See whether instruction IP reads register REG. CLASS is the type
1034 insn_uses_reg (ip
, reg
, class)
1035 struct mips_cl_insn
*ip
;
1037 enum mips_regclass
class;
1039 if (class == MIPS16_REG
)
1042 reg
= mips16_to_32_reg_map
[reg
];
1043 class = MIPS_GR_REG
;
1046 /* Don't report on general register 0, since it never changes. */
1047 if (class == MIPS_GR_REG
&& reg
== 0)
1050 if (class == MIPS_FP_REG
)
1053 /* If we are called with either $f0 or $f1, we must check $f0.
1054 This is not optimal, because it will introduce an unnecessary
1055 NOP between "lwc1 $f0" and "swc1 $f1". To fix this we would
1056 need to distinguish reading both $f0 and $f1 or just one of
1057 them. Note that we don't have to check the other way,
1058 because there is no instruction that sets both $f0 and $f1
1059 and requires a delay. */
1060 if ((ip
->insn_mo
->pinfo
& INSN_READ_FPR_S
)
1061 && (((ip
->insn_opcode
>> OP_SH_FS
) & OP_MASK_FS
)
1062 == (reg
&~ (unsigned) 1)))
1064 if ((ip
->insn_mo
->pinfo
& INSN_READ_FPR_T
)
1065 && (((ip
->insn_opcode
>> OP_SH_FT
) & OP_MASK_FT
)
1066 == (reg
&~ (unsigned) 1)))
1071 if ((ip
->insn_mo
->pinfo
& INSN_READ_GPR_S
)
1072 && ((ip
->insn_opcode
>> OP_SH_RS
) & OP_MASK_RS
) == reg
)
1074 if ((ip
->insn_mo
->pinfo
& INSN_READ_GPR_T
)
1075 && ((ip
->insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
) == reg
)
1080 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_X
)
1081 && ((ip
->insn_opcode
>> MIPS16OP_SH_RX
) & MIPS16OP_MASK_RX
) == reg
)
1083 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_Y
)
1084 && ((ip
->insn_opcode
>> MIPS16OP_SH_RY
) & MIPS16OP_MASK_RY
) == reg
)
1086 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_Z
)
1087 && ((ip
->insn_opcode
>> MIPS16OP_SH_MOVE32Z
)
1088 & MIPS16OP_MASK_MOVE32Z
) == reg
)
1090 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_T
) && reg
== TREG
)
1092 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_SP
) && reg
== SP
)
1094 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_31
) && reg
== RA
)
1096 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_GPR_X
)
1097 && ((ip
->insn_opcode
>> MIPS16OP_SH_REGR32
)
1098 & MIPS16OP_MASK_REGR32
) == reg
)
1105 /* This function returns true if modifying a register requires a
1109 reg_needs_delay (reg
)
1112 unsigned long prev_pinfo
;
1114 prev_pinfo
= prev_insn
.insn_mo
->pinfo
;
1115 if (! mips_noreorder
1117 && ((prev_pinfo
& INSN_LOAD_COPROC_DELAY
)
1119 && (prev_pinfo
& INSN_LOAD_MEMORY_DELAY
))))
1121 /* A load from a coprocessor or from memory. All load
1122 delays delay the use of general register rt for one
1123 instruction on the r3000. The r6000 and r4000 use
1125 know (prev_pinfo
& INSN_WRITE_GPR_T
);
1126 if (reg
== ((prev_insn
.insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
))
1133 /* Output an instruction. PLACE is where to put the instruction; if
1134 it is NULL, this uses frag_more to get room. IP is the instruction
1135 information. ADDRESS_EXPR is an operand of the instruction to be
1136 used with RELOC_TYPE. */
1139 append_insn (place
, ip
, address_expr
, reloc_type
, unmatched_hi
)
1141 struct mips_cl_insn
*ip
;
1142 expressionS
*address_expr
;
1143 bfd_reloc_code_real_type reloc_type
;
1144 boolean unmatched_hi
;
1146 register unsigned long prev_pinfo
, pinfo
;
1151 prev_pinfo
= prev_insn
.insn_mo
->pinfo
;
1152 pinfo
= ip
->insn_mo
->pinfo
;
1154 if (place
== NULL
&& ! mips_noreorder
)
1156 /* If the previous insn required any delay slots, see if we need
1157 to insert a NOP or two. There are eight kinds of possible
1158 hazards, of which an instruction can have at most one type.
1159 (1) a load from memory delay
1160 (2) a load from a coprocessor delay
1161 (3) an unconditional branch delay
1162 (4) a conditional branch delay
1163 (5) a move to coprocessor register delay
1164 (6) a load coprocessor register from memory delay
1165 (7) a coprocessor condition code delay
1166 (8) a HI/LO special register delay
1168 There are a lot of optimizations we could do that we don't.
1169 In particular, we do not, in general, reorder instructions.
1170 If you use gcc with optimization, it will reorder
1171 instructions and generally do much more optimization then we
1172 do here; repeating all that work in the assembler would only
1173 benefit hand written assembly code, and does not seem worth
1176 /* This is how a NOP is emitted. */
1177 #define emit_nop() \
1179 ? md_number_to_chars (frag_more (2), 0x6500, 2) \
1180 : md_number_to_chars (frag_more (4), 0, 4))
1182 /* The previous insn might require a delay slot, depending upon
1183 the contents of the current insn. */
1186 && (((prev_pinfo
& INSN_LOAD_COPROC_DELAY
)
1187 && ! cop_interlocks
)
1189 && (prev_pinfo
& INSN_LOAD_MEMORY_DELAY
))))
1191 /* A load from a coprocessor or from memory. All load
1192 delays delay the use of general register rt for one
1193 instruction on the r3000. The r6000 and r4000 use
1195 know (prev_pinfo
& INSN_WRITE_GPR_T
);
1196 if (mips_optimize
== 0
1197 || insn_uses_reg (ip
,
1198 ((prev_insn
.insn_opcode
>> OP_SH_RT
)
1205 && (((prev_pinfo
& INSN_COPROC_MOVE_DELAY
)
1206 && ! cop_interlocks
)
1208 && (prev_pinfo
& INSN_COPROC_MEMORY_DELAY
))))
1210 /* A generic coprocessor delay. The previous instruction
1211 modified a coprocessor general or control register. If
1212 it modified a control register, we need to avoid any
1213 coprocessor instruction (this is probably not always
1214 required, but it sometimes is). If it modified a general
1215 register, we avoid using that register.
1217 On the r6000 and r4000 loading a coprocessor register
1218 from memory is interlocked, and does not require a delay.
1220 This case is not handled very well. There is no special
1221 knowledge of CP0 handling, and the coprocessors other
1222 than the floating point unit are not distinguished at
1224 if (prev_pinfo
& INSN_WRITE_FPR_T
)
1226 if (mips_optimize
== 0
1227 || insn_uses_reg (ip
,
1228 ((prev_insn
.insn_opcode
>> OP_SH_FT
)
1233 else if (prev_pinfo
& INSN_WRITE_FPR_S
)
1235 if (mips_optimize
== 0
1236 || insn_uses_reg (ip
,
1237 ((prev_insn
.insn_opcode
>> OP_SH_FS
)
1244 /* We don't know exactly what the previous instruction
1245 does. If the current instruction uses a coprocessor
1246 register, we must insert a NOP. If previous
1247 instruction may set the condition codes, and the
1248 current instruction uses them, we must insert two
1250 if (mips_optimize
== 0
1251 || ((prev_pinfo
& INSN_WRITE_COND_CODE
)
1252 && (pinfo
& INSN_READ_COND_CODE
)))
1254 else if (pinfo
& INSN_COP
)
1260 && (prev_pinfo
& INSN_WRITE_COND_CODE
)
1261 && ! cop_interlocks
)
1263 /* The previous instruction sets the coprocessor condition
1264 codes, but does not require a general coprocessor delay
1265 (this means it is a floating point comparison
1266 instruction). If this instruction uses the condition
1267 codes, we need to insert a single NOP. */
1268 if (mips_optimize
== 0
1269 || (pinfo
& INSN_READ_COND_CODE
))
1272 else if (prev_pinfo
& INSN_READ_LO
)
1274 /* The previous instruction reads the LO register; if the
1275 current instruction writes to the LO register, we must
1276 insert two NOPS. Some newer processors have interlocks. */
1278 && (mips_optimize
== 0
1279 || (pinfo
& INSN_WRITE_LO
)))
1282 else if (prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
1284 /* The previous instruction reads the HI register; if the
1285 current instruction writes to the HI register, we must
1286 insert a NOP. Some newer processors have interlocks. */
1288 && (mips_optimize
== 0
1289 || (pinfo
& INSN_WRITE_HI
)))
1293 /* There are two cases which require two intervening
1294 instructions: 1) setting the condition codes using a move to
1295 coprocessor instruction which requires a general coprocessor
1296 delay and then reading the condition codes 2) reading the HI
1297 or LO register and then writing to it (except on processors
1298 which have interlocks). If we are not already emitting a NOP
1299 instruction, we must check for these cases compared to the
1300 instruction previous to the previous instruction. */
1304 && (prev_prev_insn
.insn_mo
->pinfo
& INSN_COPROC_MOVE_DELAY
)
1305 && (prev_prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
)
1306 && (pinfo
& INSN_READ_COND_CODE
)
1307 && ! cop_interlocks
)
1308 || ((prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
)
1309 && (pinfo
& INSN_WRITE_LO
)
1311 || ((prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
1312 && (pinfo
& INSN_WRITE_HI
)
1316 /* If we are being given a nop instruction, don't bother with
1317 one of the nops we would otherwise output. This will only
1318 happen when a nop instruction is used with mips_optimize set
1320 if (nops
> 0 && ip
->insn_opcode
== (mips16
? 0x6500 : 0))
1323 /* Now emit the right number of NOP instructions. */
1327 unsigned long old_frag_offset
;
1330 old_frag
= frag_now
;
1331 old_frag_offset
= frag_now_fix ();
1333 for (i
= 0; i
< nops
; i
++)
1338 listing_prev_line ();
1339 /* We may be at the start of a variant frag. In case we
1340 are, make sure there is enough space for the frag
1341 after the frags created by listing_prev_line. The
1342 argument to frag_grow here must be at least as large
1343 as the argument to all other calls to frag_grow in
1344 this file. We don't have to worry about being in the
1345 middle of a variant frag, because the variants insert
1346 all needed nop instructions themselves. */
1350 if (insn_label
!= NULL
)
1352 assert (S_GET_SEGMENT (insn_label
) == now_seg
);
1353 insn_label
->sy_frag
= frag_now
;
1354 S_SET_VALUE (insn_label
, (valueT
) frag_now_fix ());
1357 #ifndef NO_ECOFF_DEBUGGING
1358 if (ECOFF_DEBUGGING
)
1359 ecoff_fix_loc (old_frag
, old_frag_offset
);
1364 if (reloc_type
> BFD_RELOC_UNUSED
)
1366 /* We need to set up a variant frag. */
1367 assert (mips16
&& address_expr
!= NULL
);
1368 f
= frag_var (rs_machine_dependent
, 4, 0,
1369 RELAX_MIPS16_ENCODE (reloc_type
- BFD_RELOC_UNUSED
,
1370 mips16_small
, mips16_ext
),
1371 make_expr_symbol (address_expr
), (long) 0,
1374 else if (place
!= NULL
)
1376 else if (mips16
&& ! ip
->use_extend
&& reloc_type
!= BFD_RELOC_MIPS16_JMP
)
1381 if (address_expr
!= NULL
&& reloc_type
< BFD_RELOC_UNUSED
)
1383 if (address_expr
->X_op
== O_constant
)
1388 ip
->insn_opcode
|= address_expr
->X_add_number
;
1391 case BFD_RELOC_LO16
:
1392 ip
->insn_opcode
|= address_expr
->X_add_number
& 0xffff;
1395 case BFD_RELOC_MIPS_JMP
:
1396 ip
->insn_opcode
|= (address_expr
->X_add_number
>> 2) & 0x3ffffff;
1399 case BFD_RELOC_MIPS16_JMP
:
1401 (((address_expr
->X_add_number
& 0x7c0000) << 3)
1402 | ((address_expr
->X_add_number
& 0xf800000) >> 7)
1403 | ((address_expr
->X_add_number
& 0x3fffc) >> 2));
1406 case BFD_RELOC_16_PCREL_S2
:
1416 /* Don't generate a reloc if we are writing into a variant
1420 fixp
= fix_new_exp (frag_now
, f
- frag_now
->fr_literal
, 4,
1422 reloc_type
== BFD_RELOC_16_PCREL_S2
,
1426 struct mips_hi_fixup
*hi_fixup
;
1428 assert (reloc_type
== BFD_RELOC_HI16_S
);
1429 hi_fixup
= ((struct mips_hi_fixup
*)
1430 xmalloc (sizeof (struct mips_hi_fixup
)));
1431 hi_fixup
->fixp
= fixp
;
1432 hi_fixup
->seg
= now_seg
;
1433 hi_fixup
->next
= mips_hi_fixup_list
;
1434 mips_hi_fixup_list
= hi_fixup
;
1440 if (! mips16
|| reloc_type
== BFD_RELOC_MIPS16_JMP
)
1441 md_number_to_chars (f
, ip
->insn_opcode
, 4);
1446 md_number_to_chars (f
, 0xf000 | ip
->extend
, 2);
1449 md_number_to_chars (f
, ip
->insn_opcode
, 2);
1452 /* Update the register mask information. */
1455 if (pinfo
& INSN_WRITE_GPR_D
)
1456 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
);
1457 if ((pinfo
& (INSN_WRITE_GPR_T
| INSN_READ_GPR_T
)) != 0)
1458 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
);
1459 if (pinfo
& INSN_READ_GPR_S
)
1460 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> OP_SH_RS
) & OP_MASK_RS
);
1461 if (pinfo
& INSN_WRITE_GPR_31
)
1462 mips_gprmask
|= 1 << 31;
1463 if (pinfo
& INSN_WRITE_FPR_D
)
1464 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FD
) & OP_MASK_FD
);
1465 if ((pinfo
& (INSN_WRITE_FPR_S
| INSN_READ_FPR_S
)) != 0)
1466 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FS
) & OP_MASK_FS
);
1467 if ((pinfo
& (INSN_WRITE_FPR_T
| INSN_READ_FPR_T
)) != 0)
1468 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FT
) & OP_MASK_FT
);
1469 if ((pinfo
& INSN_READ_FPR_R
) != 0)
1470 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FR
) & OP_MASK_FR
);
1471 if (pinfo
& INSN_COP
)
1473 /* We don't keep enough information to sort these cases out. */
1475 /* Never set the bit for $0, which is always zero. */
1476 mips_gprmask
&=~ 1 << 0;
1480 if (pinfo
& (MIPS16_INSN_WRITE_X
| MIPS16_INSN_READ_X
))
1481 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_RX
)
1482 & MIPS16OP_MASK_RX
);
1483 if (pinfo
& (MIPS16_INSN_WRITE_Y
| MIPS16_INSN_READ_Y
))
1484 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_RY
)
1485 & MIPS16OP_MASK_RY
);
1486 if (pinfo
& MIPS16_INSN_WRITE_Z
)
1487 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_RZ
)
1488 & MIPS16OP_MASK_RZ
);
1489 if (pinfo
& (MIPS16_INSN_WRITE_T
| MIPS16_INSN_READ_T
))
1490 mips_gprmask
|= 1 << TREG
;
1491 if (pinfo
& (MIPS16_INSN_WRITE_SP
| MIPS16_INSN_READ_SP
))
1492 mips_gprmask
|= 1 << SP
;
1493 if (pinfo
& (MIPS16_INSN_WRITE_31
| MIPS16_INSN_READ_31
))
1494 mips_gprmask
|= 1 << RA
;
1495 if (pinfo
& MIPS16_INSN_WRITE_GPR_Y
)
1496 mips_gprmask
|= 1 << MIPS16OP_EXTRACT_REG32R (ip
->insn_opcode
);
1497 if (pinfo
& MIPS16_INSN_READ_Z
)
1498 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_MOVE32Z
)
1499 & MIPS16OP_MASK_MOVE32Z
);
1500 if (pinfo
& MIPS16_INSN_READ_GPR_X
)
1501 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_REGR32
)
1502 & MIPS16OP_MASK_REGR32
);
1505 if (place
== NULL
&& ! mips_noreorder
)
1507 /* Filling the branch delay slot is more complex. We try to
1508 switch the branch with the previous instruction, which we can
1509 do if the previous instruction does not set up a condition
1510 that the branch tests and if the branch is not itself the
1511 target of any branch. */
1512 if ((pinfo
& INSN_UNCOND_BRANCH_DELAY
)
1513 || (pinfo
& INSN_COND_BRANCH_DELAY
))
1515 if (mips_optimize
< 2
1516 /* If we have seen .set volatile or .set nomove, don't
1519 /* If we had to emit any NOP instructions, then we
1520 already know we can not swap. */
1522 /* If we don't even know the previous insn, we can not
1524 || ! prev_insn_valid
1525 /* If the previous insn is already in a branch delay
1526 slot, then we can not swap. */
1527 || prev_insn_is_delay_slot
1528 /* If the previous previous insn was in a .set
1529 noreorder, we can't swap. Actually, the MIPS
1530 assembler will swap in this situation. However, gcc
1531 configured -with-gnu-as will generate code like
1537 in which we can not swap the bne and INSN. If gcc is
1538 not configured -with-gnu-as, it does not output the
1539 .set pseudo-ops. We don't have to check
1540 prev_insn_unreordered, because prev_insn_valid will
1541 be 0 in that case. We don't want to use
1542 prev_prev_insn_valid, because we do want to be able
1543 to swap at the start of a function. */
1544 || prev_prev_insn_unreordered
1545 /* If the branch is itself the target of a branch, we
1546 can not swap. We cheat on this; all we check for is
1547 whether there is a label on this instruction. If
1548 there are any branches to anything other than a
1549 label, users must use .set noreorder. */
1550 || insn_label
!= NULL
1551 /* If the previous instruction is in a variant frag, we
1552 can not do the swap. This does not apply to the
1553 mips16, which uses variant frags for different
1556 && prev_insn_frag
->fr_type
== rs_machine_dependent
)
1557 /* If the branch reads the condition codes, we don't
1558 even try to swap, because in the sequence
1563 we can not swap, and I don't feel like handling that
1567 && (pinfo
& INSN_READ_COND_CODE
))
1568 /* We can not swap with an instruction that requires a
1569 delay slot, becase the target of the branch might
1570 interfere with that instruction. */
1574 & (INSN_LOAD_COPROC_DELAY
1575 | INSN_COPROC_MOVE_DELAY
1576 | INSN_WRITE_COND_CODE
)))
1584 & (INSN_LOAD_MEMORY_DELAY
1585 | INSN_COPROC_MEMORY_DELAY
)))
1586 /* We can not swap with a branch instruction. */
1588 & (INSN_UNCOND_BRANCH_DELAY
1589 | INSN_COND_BRANCH_DELAY
1590 | INSN_COND_BRANCH_LIKELY
))
1591 /* We do not swap with a trap instruction, since it
1592 complicates trap handlers to have the trap
1593 instruction be in a delay slot. */
1594 || (prev_pinfo
& INSN_TRAP
)
1595 /* If the branch reads a register that the previous
1596 instruction sets, we can not swap. */
1598 && (prev_pinfo
& INSN_WRITE_GPR_T
)
1599 && insn_uses_reg (ip
,
1600 ((prev_insn
.insn_opcode
>> OP_SH_RT
)
1604 && (prev_pinfo
& INSN_WRITE_GPR_D
)
1605 && insn_uses_reg (ip
,
1606 ((prev_insn
.insn_opcode
>> OP_SH_RD
)
1610 && (((prev_pinfo
& MIPS16_INSN_WRITE_X
)
1611 && insn_uses_reg (ip
,
1612 ((prev_insn
.insn_opcode
1614 & MIPS16OP_MASK_RX
),
1616 || ((prev_pinfo
& MIPS16_INSN_WRITE_Y
)
1617 && insn_uses_reg (ip
,
1618 ((prev_insn
.insn_opcode
1620 & MIPS16OP_MASK_RY
),
1622 || ((prev_pinfo
& MIPS16_INSN_WRITE_Z
)
1623 && insn_uses_reg (ip
,
1624 ((prev_insn
.insn_opcode
1626 & MIPS16OP_MASK_RZ
),
1628 || ((prev_pinfo
& MIPS16_INSN_WRITE_T
)
1629 && insn_uses_reg (ip
, TREG
, MIPS_GR_REG
))
1630 || ((prev_pinfo
& MIPS16_INSN_WRITE_31
)
1631 && insn_uses_reg (ip
, RA
, MIPS_GR_REG
))
1632 || ((prev_pinfo
& MIPS16_INSN_WRITE_GPR_Y
)
1633 && insn_uses_reg (ip
,
1634 MIPS16OP_EXTRACT_REG32R (prev_insn
.
1637 /* If the branch writes a register that the previous
1638 instruction sets, we can not swap (we know that
1639 branches write only to RD or to $31). */
1641 && (prev_pinfo
& INSN_WRITE_GPR_T
)
1642 && (((pinfo
& INSN_WRITE_GPR_D
)
1643 && (((prev_insn
.insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
)
1644 == ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)))
1645 || ((pinfo
& INSN_WRITE_GPR_31
)
1646 && (((prev_insn
.insn_opcode
>> OP_SH_RT
)
1650 && (prev_pinfo
& INSN_WRITE_GPR_D
)
1651 && (((pinfo
& INSN_WRITE_GPR_D
)
1652 && (((prev_insn
.insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)
1653 == ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)))
1654 || ((pinfo
& INSN_WRITE_GPR_31
)
1655 && (((prev_insn
.insn_opcode
>> OP_SH_RD
)
1659 && (pinfo
& MIPS16_INSN_WRITE_31
)
1660 && ((prev_pinfo
& MIPS16_INSN_WRITE_31
)
1661 || ((prev_pinfo
& MIPS16_INSN_WRITE_GPR_Y
)
1662 && (MIPS16OP_EXTRACT_REG32R (prev_insn
.insn_opcode
)
1664 /* If the branch writes a register that the previous
1665 instruction reads, we can not swap (we know that
1666 branches only write to RD or to $31). */
1668 && (pinfo
& INSN_WRITE_GPR_D
)
1669 && insn_uses_reg (&prev_insn
,
1670 ((ip
->insn_opcode
>> OP_SH_RD
)
1674 && (pinfo
& INSN_WRITE_GPR_31
)
1675 && insn_uses_reg (&prev_insn
, 31, MIPS_GR_REG
))
1677 && (pinfo
& MIPS16_INSN_WRITE_31
)
1678 && insn_uses_reg (&prev_insn
, RA
, MIPS_GR_REG
))
1679 /* If we are generating embedded PIC code, the branch
1680 might be expanded into a sequence which uses $at, so
1681 we can't swap with an instruction which reads it. */
1682 || (mips_pic
== EMBEDDED_PIC
1683 && insn_uses_reg (&prev_insn
, AT
, MIPS_GR_REG
))
1684 /* If the previous previous instruction has a load
1685 delay, and sets a register that the branch reads, we
1689 && ((prev_prev_insn
.insn_mo
->pinfo
& INSN_LOAD_COPROC_DELAY
)
1691 && (prev_prev_insn
.insn_mo
->pinfo
1692 & INSN_LOAD_MEMORY_DELAY
)))
1693 && insn_uses_reg (ip
,
1694 ((prev_prev_insn
.insn_opcode
>> OP_SH_RT
)
1697 /* If one instruction sets a condition code and the
1698 other one uses a condition code, we can not swap. */
1699 || ((pinfo
& INSN_READ_COND_CODE
)
1700 && (prev_pinfo
& INSN_WRITE_COND_CODE
))
1701 || ((pinfo
& INSN_WRITE_COND_CODE
)
1702 && (prev_pinfo
& INSN_READ_COND_CODE
))
1703 /* If the previous instruction uses the PC, we can not
1706 && (prev_pinfo
& MIPS16_INSN_READ_PC
))
1707 /* If the previous instruction was extended, we can not
1709 || (mips16
&& prev_insn_extended
)
1710 /* If the previous instruction had a fixup in mips16
1711 mode, we can not swap. This normally means that the
1712 previous instruction was a 4 byte branch anyhow. */
1713 || (mips16
&& prev_insn_fixp
))
1715 /* We could do even better for unconditional branches to
1716 portions of this object file; we could pick up the
1717 instruction at the destination, put it in the delay
1718 slot, and bump the destination address. */
1720 /* Update the previous insn information. */
1721 prev_prev_insn
= *ip
;
1722 prev_insn
.insn_mo
= &dummy_opcode
;
1726 /* It looks like we can actually do the swap. */
1732 prev_f
= prev_insn_frag
->fr_literal
+ prev_insn_where
;
1733 memcpy (temp
, prev_f
, 4);
1734 memcpy (prev_f
, f
, 4);
1735 memcpy (f
, temp
, 4);
1738 prev_insn_fixp
->fx_frag
= frag_now
;
1739 prev_insn_fixp
->fx_where
= f
- frag_now
->fr_literal
;
1743 fixp
->fx_frag
= prev_insn_frag
;
1744 fixp
->fx_where
= prev_insn_where
;
1747 else if (reloc_type
> BFD_RELOC_UNUSED
)
1752 /* We are in mips16 mode, and we have just created a
1753 variant frag. We need to extract the old
1754 instruction from the end of the previous frag,
1755 and add it to a new frag. */
1756 prev_f
= prev_insn_frag
->fr_literal
+ prev_insn_where
;
1757 memcpy (temp
, prev_f
, 2);
1758 prev_insn_frag
->fr_fix
-= 2;
1759 if (prev_insn_frag
->fr_type
== rs_machine_dependent
)
1761 assert (prev_insn_where
== prev_insn_frag
->fr_fix
);
1762 memcpy (prev_f
, prev_f
+ 2, 2);
1764 memcpy (frag_more (2), temp
, 2);
1771 assert (prev_insn_fixp
== NULL
);
1772 prev_f
= prev_insn_frag
->fr_literal
+ prev_insn_where
;
1773 memcpy (temp
, prev_f
, 2);
1774 memcpy (prev_f
, f
, 2);
1775 if (reloc_type
!= BFD_RELOC_MIPS16_JMP
)
1776 memcpy (f
, temp
, 2);
1779 memcpy (f
, f
+ 2, 2);
1780 memcpy (f
+ 2, temp
, 2);
1784 fixp
->fx_frag
= prev_insn_frag
;
1785 fixp
->fx_where
= prev_insn_where
;
1789 /* Update the previous insn information; leave prev_insn
1791 prev_prev_insn
= *ip
;
1793 prev_insn_is_delay_slot
= 1;
1795 /* If that was an unconditional branch, forget the previous
1796 insn information. */
1797 if (pinfo
& INSN_UNCOND_BRANCH_DELAY
)
1799 prev_prev_insn
.insn_mo
= &dummy_opcode
;
1800 prev_insn
.insn_mo
= &dummy_opcode
;
1803 else if (pinfo
& INSN_COND_BRANCH_LIKELY
)
1805 /* We don't yet optimize a branch likely. What we should do
1806 is look at the target, copy the instruction found there
1807 into the delay slot, and increment the branch to jump to
1808 the next instruction. */
1810 /* Update the previous insn information. */
1811 prev_prev_insn
= *ip
;
1812 prev_insn
.insn_mo
= &dummy_opcode
;
1816 /* Update the previous insn information. */
1818 prev_prev_insn
.insn_mo
= &dummy_opcode
;
1820 prev_prev_insn
= prev_insn
;
1823 /* Any time we see a branch, we always fill the delay slot
1824 immediately; since this insn is not a branch, we know it
1825 is not in a delay slot. */
1826 prev_insn_is_delay_slot
= 0;
1829 prev_prev_insn_unreordered
= prev_insn_unreordered
;
1830 prev_insn_unreordered
= 0;
1831 prev_insn_frag
= frag_now
;
1832 prev_insn_where
= f
- frag_now
->fr_literal
;
1833 prev_insn_fixp
= fixp
;
1835 prev_insn_extended
= ip
->use_extend
|| reloc_type
> BFD_RELOC_UNUSED
;
1836 prev_insn_valid
= 1;
1839 /* We just output an insn, so the next one doesn't have a label. */
1843 /* This function forgets that there was any previous instruction or
1847 mips_no_prev_insn ()
1849 prev_insn
.insn_mo
= &dummy_opcode
;
1850 prev_prev_insn
.insn_mo
= &dummy_opcode
;
1851 prev_insn_valid
= 0;
1852 prev_insn_is_delay_slot
= 0;
1853 prev_insn_unreordered
= 0;
1854 prev_insn_extended
= 0;
1855 prev_prev_insn_unreordered
= 0;
1859 /* This function must be called whenever we turn on noreorder or emit
1860 something other than instructions. It inserts any NOPS which might
1861 be needed by the previous instruction, and clears the information
1862 kept for the previous instructions. */
1867 if (! mips_noreorder
)
1874 && (! cop_interlocks
1875 && (prev_insn
.insn_mo
->pinfo
1876 & (INSN_LOAD_COPROC_DELAY
1877 | INSN_COPROC_MOVE_DELAY
1878 | INSN_WRITE_COND_CODE
))))
1880 && (prev_insn
.insn_mo
->pinfo
1885 && (prev_insn
.insn_mo
->pinfo
1886 & (INSN_LOAD_MEMORY_DELAY
1887 | INSN_COPROC_MEMORY_DELAY
))))
1892 && (! cop_interlocks
1893 && prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
))
1895 && ((prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
1896 || (prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
))))
1901 && (! cop_interlocks
1902 && prev_prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
))
1904 && ((prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
1905 || (prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
))))
1910 if (insn_label
!= NULL
)
1912 assert (S_GET_SEGMENT (insn_label
) == now_seg
);
1913 insn_label
->sy_frag
= frag_now
;
1914 S_SET_VALUE (insn_label
, (valueT
) frag_now_fix ());
1919 mips_no_prev_insn ();
1922 /* Build an instruction created by a macro expansion. This is passed
1923 a pointer to the count of instructions created so far, an
1924 expression, the name of the instruction to build, an operand format
1925 string, and corresponding arguments. */
1929 macro_build (char *place
,
1937 macro_build (place
, counter
, ep
, name
, fmt
, va_alist
)
1946 struct mips_cl_insn insn
;
1947 bfd_reloc_code_real_type r
;
1951 va_start (args
, fmt
);
1957 * If the macro is about to expand into a second instruction,
1958 * print a warning if needed. We need to pass ip as a parameter
1959 * to generate a better warning message here...
1961 if (mips_warn_about_macros
&& place
== NULL
&& *counter
== 1)
1962 as_warn ("Macro instruction expanded into multiple instructions");
1965 *counter
+= 1; /* bump instruction counter */
1969 mips16_macro_build (place
, counter
, ep
, name
, fmt
, args
);
1974 r
= BFD_RELOC_UNUSED
;
1975 insn
.insn_mo
= (struct mips_opcode
*) hash_find (op_hash
, name
);
1976 assert (insn
.insn_mo
);
1977 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
1979 while (strcmp (fmt
, insn
.insn_mo
->args
) != 0
1980 || insn
.insn_mo
->pinfo
== INSN_MACRO
1981 || ((insn
.insn_mo
->pinfo
& INSN_ISA
) == INSN_ISA2
1983 || ((insn
.insn_mo
->pinfo
& INSN_ISA
) == INSN_ISA3
1985 || ((insn
.insn_mo
->pinfo
& INSN_ISA
) == INSN_ISA4
1987 || ((insn
.insn_mo
->pinfo
& INSN_ISA
) == INSN_4650
1989 || ((insn
.insn_mo
->pinfo
& INSN_ISA
) == INSN_4010
1991 || ((insn
.insn_mo
->pinfo
& INSN_ISA
) == INSN_4100
1995 assert (insn
.insn_mo
->name
);
1996 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
1998 insn
.insn_opcode
= insn
.insn_mo
->match
;
2014 insn
.insn_opcode
|= va_arg (args
, int) << 16;
2020 insn
.insn_opcode
|= va_arg (args
, int) << 16;
2025 insn
.insn_opcode
|= va_arg (args
, int) << 11;
2030 insn
.insn_opcode
|= va_arg (args
, int) << 11;
2037 insn
.insn_opcode
|= va_arg (args
, int) << 6;
2041 insn
.insn_opcode
|= va_arg (args
, int) << 6;
2045 insn
.insn_opcode
|= va_arg (args
, int) << 6;
2052 insn
.insn_opcode
|= va_arg (args
, int) << 21;
2058 r
= (bfd_reloc_code_real_type
) va_arg (args
, int);
2059 assert (r
== BFD_RELOC_MIPS_GPREL
2060 || r
== BFD_RELOC_MIPS_LITERAL
2061 || r
== BFD_RELOC_LO16
2062 || r
== BFD_RELOC_MIPS_GOT16
2063 || r
== BFD_RELOC_MIPS_CALL16
2064 || r
== BFD_RELOC_MIPS_GOT_LO16
2065 || r
== BFD_RELOC_MIPS_CALL_LO16
2066 || (ep
->X_op
== O_subtract
2067 && now_seg
== text_section
2068 && r
== BFD_RELOC_PCREL_LO16
));
2072 r
= (bfd_reloc_code_real_type
) va_arg (args
, int);
2074 && (ep
->X_op
== O_constant
2075 || (ep
->X_op
== O_symbol
2076 && (r
== BFD_RELOC_HI16_S
2077 || r
== BFD_RELOC_HI16
2078 || r
== BFD_RELOC_MIPS_GOT_HI16
2079 || r
== BFD_RELOC_MIPS_CALL_HI16
))
2080 || (ep
->X_op
== O_subtract
2081 && now_seg
== text_section
2082 && r
== BFD_RELOC_PCREL_HI16_S
)));
2083 if (ep
->X_op
== O_constant
)
2085 insn
.insn_opcode
|= (ep
->X_add_number
>> 16) & 0xffff;
2087 r
= BFD_RELOC_UNUSED
;
2092 assert (ep
!= NULL
);
2094 * This allows macro() to pass an immediate expression for
2095 * creating short branches without creating a symbol.
2096 * Note that the expression still might come from the assembly
2097 * input, in which case the value is not checked for range nor
2098 * is a relocation entry generated (yuck).
2100 if (ep
->X_op
== O_constant
)
2102 insn
.insn_opcode
|= (ep
->X_add_number
>> 2) & 0xffff;
2106 r
= BFD_RELOC_16_PCREL_S2
;
2110 assert (ep
!= NULL
);
2111 r
= BFD_RELOC_MIPS_JMP
;
2120 assert (r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
2122 append_insn (place
, &insn
, ep
, r
, false);
2126 mips16_macro_build (place
, counter
, ep
, name
, fmt
, args
)
2134 struct mips_cl_insn insn
;
2135 bfd_reloc_code_real_type r
;
2137 r
= BFD_RELOC_UNUSED
;
2138 insn
.insn_mo
= (struct mips_opcode
*) hash_find (mips16_op_hash
, name
);
2139 assert (insn
.insn_mo
);
2140 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
2142 while (strcmp (fmt
, insn
.insn_mo
->args
) != 0
2143 || insn
.insn_mo
->pinfo
== INSN_MACRO
)
2146 assert (insn
.insn_mo
->name
);
2147 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
2150 insn
.insn_opcode
= insn
.insn_mo
->match
;
2151 insn
.use_extend
= false;
2170 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_RY
;
2175 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_RX
;
2179 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_RZ
;
2183 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_MOVE32Z
;
2193 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_REGR32
;
2200 regno
= va_arg (args
, int);
2201 regno
= ((regno
& 7) << 2) | ((regno
& 0x18) >> 3);
2202 insn
.insn_opcode
|= regno
<< MIPS16OP_SH_REG32R
;
2223 assert (ep
!= NULL
);
2225 if (ep
->X_op
!= O_constant
)
2226 r
= BFD_RELOC_UNUSED
+ c
;
2229 mips16_immed ((char *) NULL
, 0, c
, ep
->X_add_number
, false,
2230 false, false, &insn
.insn_opcode
,
2231 &insn
.use_extend
, &insn
.extend
);
2233 r
= BFD_RELOC_UNUSED
;
2239 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_IMM6
;
2246 assert (r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
2248 append_insn (place
, &insn
, ep
, r
, false);
2252 * Generate a "lui" instruction.
2255 macro_build_lui (place
, counter
, ep
, regnum
)
2261 expressionS high_expr
;
2262 struct mips_cl_insn insn
;
2263 bfd_reloc_code_real_type r
;
2264 CONST
char *name
= "lui";
2265 CONST
char *fmt
= "t,u";
2273 high_expr
.X_op
= O_constant
;
2274 high_expr
.X_add_number
= ep
->X_add_number
;
2277 if (high_expr
.X_op
== O_constant
)
2279 /* we can compute the instruction now without a relocation entry */
2280 if (high_expr
.X_add_number
& 0x8000)
2281 high_expr
.X_add_number
+= 0x10000;
2282 high_expr
.X_add_number
=
2283 ((unsigned long) high_expr
.X_add_number
>> 16) & 0xffff;
2284 r
= BFD_RELOC_UNUSED
;
2288 assert (ep
->X_op
== O_symbol
);
2289 /* _gp_disp is a special case, used from s_cpload. */
2290 assert (mips_pic
== NO_PIC
2291 || strcmp (S_GET_NAME (ep
->X_add_symbol
), "_gp_disp") == 0);
2292 r
= BFD_RELOC_HI16_S
;
2296 * If the macro is about to expand into a second instruction,
2297 * print a warning if needed. We need to pass ip as a parameter
2298 * to generate a better warning message here...
2300 if (mips_warn_about_macros
&& place
== NULL
&& *counter
== 1)
2301 as_warn ("Macro instruction expanded into multiple instructions");
2304 *counter
+= 1; /* bump instruction counter */
2306 insn
.insn_mo
= (struct mips_opcode
*) hash_find (op_hash
, name
);
2307 assert (insn
.insn_mo
);
2308 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
2309 assert (strcmp (fmt
, insn
.insn_mo
->args
) == 0);
2311 insn
.insn_opcode
= insn
.insn_mo
->match
| (regnum
<< OP_SH_RT
);
2312 if (r
== BFD_RELOC_UNUSED
)
2314 insn
.insn_opcode
|= high_expr
.X_add_number
;
2315 append_insn (place
, &insn
, NULL
, r
, false);
2318 append_insn (place
, &insn
, &high_expr
, r
, false);
2322 * Generates code to set the $at register to true (one)
2323 * if reg is less than the immediate expression.
2326 set_at (counter
, reg
, unsignedp
)
2331 if (imm_expr
.X_add_number
>= -0x8000 && imm_expr
.X_add_number
< 0x8000)
2332 macro_build ((char *) NULL
, counter
, &imm_expr
,
2333 unsignedp
? "sltiu" : "slti",
2334 "t,r,j", AT
, reg
, (int) BFD_RELOC_LO16
);
2337 load_register (counter
, AT
, &imm_expr
, 0);
2338 macro_build ((char *) NULL
, counter
, NULL
,
2339 unsignedp
? "sltu" : "slt",
2340 "d,v,t", AT
, reg
, AT
);
2344 /* Warn if an expression is not a constant. */
2347 check_absolute_expr (ip
, ex
)
2348 struct mips_cl_insn
*ip
;
2351 if (ex
->X_op
!= O_constant
)
2352 as_warn ("Instruction %s requires absolute expression", ip
->insn_mo
->name
);
2355 /* Count the leading zeroes by performing a binary chop. This is a
2356 bulky bit of source, but performance is a LOT better for the
2357 majority of values than a simple loop to count the bits:
2358 for (lcnt = 0; (lcnt < 32); lcnt++)
2359 if ((v) & (1 << (31 - lcnt)))
2361 However it is not code size friendly, and the gain will drop a bit
2362 on certain cached systems.
2364 #define COUNT_TOP_ZEROES(v) \
2365 (((v) & ~0xffff) == 0 \
2366 ? ((v) & ~0xff) == 0 \
2367 ? ((v) & ~0xf) == 0 \
2368 ? ((v) & ~0x3) == 0 \
2369 ? ((v) & ~0x1) == 0 \
2374 : ((v) & ~0x7) == 0 \
2377 : ((v) & ~0x3f) == 0 \
2378 ? ((v) & ~0x1f) == 0 \
2381 : ((v) & ~0x7f) == 0 \
2384 : ((v) & ~0xfff) == 0 \
2385 ? ((v) & ~0x3ff) == 0 \
2386 ? ((v) & ~0x1ff) == 0 \
2389 : ((v) & ~0x7ff) == 0 \
2392 : ((v) & ~0x3fff) == 0 \
2393 ? ((v) & ~0x1fff) == 0 \
2396 : ((v) & ~0x7fff) == 0 \
2399 : ((v) & ~0xffffff) == 0 \
2400 ? ((v) & ~0xfffff) == 0 \
2401 ? ((v) & ~0x3ffff) == 0 \
2402 ? ((v) & ~0x1ffff) == 0 \
2405 : ((v) & ~0x7ffff) == 0 \
2408 : ((v) & ~0x3fffff) == 0 \
2409 ? ((v) & ~0x1fffff) == 0 \
2412 : ((v) & ~0x7fffff) == 0 \
2415 : ((v) & ~0xfffffff) == 0 \
2416 ? ((v) & ~0x3ffffff) == 0 \
2417 ? ((v) & ~0x1ffffff) == 0 \
2420 : ((v) & ~0x7ffffff) == 0 \
2423 : ((v) & ~0x3fffffff) == 0 \
2424 ? ((v) & ~0x1fffffff) == 0 \
2427 : ((v) & ~0x7fffffff) == 0 \
2432 * This routine generates the least number of instructions neccessary to load
2433 * an absolute expression value into a register.
2436 load_register (counter
, reg
, ep
, dbl
)
2443 expressionS hi32
, lo32
, tmp
;
2445 if (ep
->X_op
!= O_big
)
2447 assert (ep
->X_op
== O_constant
);
2448 if (ep
->X_add_number
< 0x8000
2449 && (ep
->X_add_number
>= 0
2450 || (ep
->X_add_number
>= -0x8000
2453 || sizeof (ep
->X_add_number
) > 4))))
2455 /* We can handle 16 bit signed values with an addiu to
2456 $zero. No need to ever use daddiu here, since $zero and
2457 the result are always correct in 32 bit mode. */
2458 macro_build ((char *) NULL
, counter
, ep
, "addiu", "t,r,j", reg
, 0,
2459 (int) BFD_RELOC_LO16
);
2462 else if (ep
->X_add_number
>= 0 && ep
->X_add_number
< 0x10000)
2464 /* We can handle 16 bit unsigned values with an ori to
2466 macro_build ((char *) NULL
, counter
, ep
, "ori", "t,r,i", reg
, 0,
2467 (int) BFD_RELOC_LO16
);
2470 else if ((((ep
->X_add_number
&~ (offsetT
) 0x7fffffff) == 0
2471 || ((ep
->X_add_number
&~ (offsetT
) 0x7fffffff)
2472 == ~ (offsetT
) 0x7fffffff))
2475 || sizeof (ep
->X_add_number
) > 4
2476 || (ep
->X_add_number
& 0x80000000) == 0))
2477 || ((mips_isa
< 3 || !dbl
)
2478 && (ep
->X_add_number
&~ (offsetT
) 0xffffffff) == 0))
2480 /* 32 bit values require an lui. */
2481 macro_build ((char *) NULL
, counter
, ep
, "lui", "t,u", reg
,
2482 (int) BFD_RELOC_HI16
);
2483 if ((ep
->X_add_number
& 0xffff) != 0)
2484 macro_build ((char *) NULL
, counter
, ep
, "ori", "t,r,i", reg
, reg
,
2485 (int) BFD_RELOC_LO16
);
2490 /* The value is larger than 32 bits. */
2494 as_bad ("Number larger than 32 bits");
2495 macro_build ((char *) NULL
, counter
, ep
, "addiu", "t,r,j", reg
, 0,
2496 (int) BFD_RELOC_LO16
);
2500 if (ep
->X_op
!= O_big
)
2504 hi32
.X_add_number
>>= shift
;
2505 hi32
.X_add_number
&= 0xffffffff;
2506 if ((hi32
.X_add_number
& 0x80000000) != 0)
2507 hi32
.X_add_number
|= ~ (offsetT
) 0xffffffff;
2509 lo32
.X_add_number
&= 0xffffffff;
2513 assert (ep
->X_add_number
> 2);
2514 if (ep
->X_add_number
== 3)
2515 generic_bignum
[3] = 0;
2516 else if (ep
->X_add_number
> 4)
2517 as_bad ("Number larger than 64 bits");
2518 lo32
.X_op
= O_constant
;
2519 lo32
.X_add_number
= generic_bignum
[0] + (generic_bignum
[1] << 16);
2520 hi32
.X_op
= O_constant
;
2521 hi32
.X_add_number
= generic_bignum
[2] + (generic_bignum
[3] << 16);
2524 if (hi32
.X_add_number
== 0)
2528 if (hi32
.X_add_number
== 0xffffffff)
2530 if ((lo32
.X_add_number
& 0xffff8000) == 0xffff8000)
2532 macro_build ((char *) NULL
, counter
, &lo32
, "addiu", "t,r,j", reg
, 0,
2533 (int) BFD_RELOC_LO16
);
2536 if (lo32
.X_add_number
& 0x80000000)
2538 macro_build ((char *) NULL
, counter
, &lo32
, "lui", "t,u", reg
,
2539 (int) BFD_RELOC_HI16
);
2540 macro_build ((char *) NULL
, counter
, &lo32
, "ori", "t,r,i", reg
, reg
,
2541 (int) BFD_RELOC_LO16
);
2546 /* Check for 16bit shifted constant: */
2548 tmp
.X_add_number
= hi32
.X_add_number
<< shift
| lo32
.X_add_number
;
2549 /* We know that hi32 is non-zero, so start the mask on the first
2550 bit of the hi32 value: */
2554 if ((tmp
.X_add_number
& ~((offsetT
)0xffff << shift
)) == 0)
2556 tmp
.X_op
= O_constant
;
2557 tmp
.X_add_number
>>= shift
;
2558 macro_build ((char *) NULL
, counter
, &tmp
, "ori", "t,r,i", reg
, 0,
2559 (int) BFD_RELOC_LO16
);
2560 macro_build ((char *) NULL
, counter
, NULL
,
2561 (shift
>= 32) ? "dsll32" : "dsll",
2562 "d,w,<", reg
, reg
, (shift
>= 32) ? shift
- 32 : shift
);
2566 } while (shift
<= (64 - 16));
2570 tmp
.X_add_number
= hi32
.X_add_number
<< shift
| lo32
.X_add_number
;
2571 while ((tmp
.X_add_number
& 1) == 0)
2573 tmp
.X_add_number
>>= 1;
2576 if (((tmp
.X_add_number
+ 1) & tmp
.X_add_number
) == 0) /* (power-of-2 - 1) */
2578 shift
= COUNT_TOP_ZEROES((unsigned int)hi32
.X_add_number
);
2581 tmp
.X_op
= O_constant
;
2582 tmp
.X_add_number
= (offsetT
)-1;
2583 macro_build ((char *) NULL
, counter
, &tmp
, "addiu", "t,r,j", reg
, 0,
2584 (int) BFD_RELOC_LO16
); /* set all ones */
2588 macro_build ((char *) NULL
, counter
, NULL
,
2589 (freg
>= 32) ? "dsll32" : "dsll",
2591 (freg
>= 32) ? freg
- 32 : freg
);
2593 macro_build ((char *) NULL
, counter
, NULL
, (shift
>= 32) ? "dsrl32" : "dsrl",
2594 "d,w,<", reg
, reg
, (shift
>= 32) ? shift
- 32 : shift
);
2598 load_register (counter
, reg
, &hi32
, 0);
2601 if ((lo32
.X_add_number
& 0xffff0000) == 0)
2605 macro_build ((char *) NULL
, counter
, NULL
, "dsll32", "d,w,<", reg
,
2614 if ((freg
== 0) && (lo32
.X_add_number
== 0xffffffff))
2616 macro_build ((char *) NULL
, counter
, &lo32
, "lui", "t,u", reg
,
2617 (int) BFD_RELOC_HI16
);
2618 macro_build ((char *) NULL
, counter
, NULL
, "dsrl32", "d,w,<", reg
,
2625 macro_build ((char *) NULL
, counter
, NULL
, "dsll", "d,w,<", reg
,
2630 mid16
.X_add_number
>>= 16;
2631 macro_build ((char *) NULL
, counter
, &mid16
, "ori", "t,r,i", reg
,
2632 freg
, (int) BFD_RELOC_LO16
);
2633 macro_build ((char *) NULL
, counter
, NULL
, "dsll", "d,w,<", reg
,
2637 if ((lo32
.X_add_number
& 0xffff) != 0)
2638 macro_build ((char *) NULL
, counter
, &lo32
, "ori", "t,r,i", reg
, freg
,
2639 (int) BFD_RELOC_LO16
);
2642 /* Load an address into a register. */
2645 load_address (counter
, reg
, ep
)
2652 if (ep
->X_op
!= O_constant
2653 && ep
->X_op
!= O_symbol
)
2655 as_bad ("expression too complex");
2656 ep
->X_op
= O_constant
;
2659 if (ep
->X_op
== O_constant
)
2661 load_register (counter
, reg
, ep
, 0);
2665 if (mips_pic
== NO_PIC
)
2667 /* If this is a reference to a GP relative symbol, we want
2668 addiu $reg,$gp,<sym> (BFD_RELOC_MIPS_GPREL)
2670 lui $reg,<sym> (BFD_RELOC_HI16_S)
2671 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
2672 If we have an addend, we always use the latter form. */
2673 if ((valueT
) ep
->X_add_number
>= MAX_GPREL_OFFSET
2674 || nopic_need_relax (ep
->X_add_symbol
))
2679 macro_build ((char *) NULL
, counter
, ep
,
2680 mips_isa
< 3 ? "addiu" : "daddiu",
2681 "t,r,j", reg
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
2682 p
= frag_var (rs_machine_dependent
, 8, 0,
2683 RELAX_ENCODE (4, 8, 0, 4, 0, mips_warn_about_macros
),
2684 ep
->X_add_symbol
, (long) 0, (char *) NULL
);
2686 macro_build_lui (p
, counter
, ep
, reg
);
2689 macro_build (p
, counter
, ep
,
2690 mips_isa
< 3 ? "addiu" : "daddiu",
2691 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
2693 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
2697 /* If this is a reference to an external symbol, we want
2698 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
2700 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
2702 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
2703 If there is a constant, it must be added in after. */
2704 ex
.X_add_number
= ep
->X_add_number
;
2705 ep
->X_add_number
= 0;
2707 macro_build ((char *) NULL
, counter
, ep
,
2708 mips_isa
< 3 ? "lw" : "ld",
2709 "t,o(b)", reg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
2710 macro_build ((char *) NULL
, counter
, (expressionS
*) NULL
, "nop", "");
2711 p
= frag_var (rs_machine_dependent
, 4, 0,
2712 RELAX_ENCODE (0, 4, -8, 0, 0, mips_warn_about_macros
),
2713 ep
->X_add_symbol
, (long) 0, (char *) NULL
);
2714 macro_build (p
, counter
, ep
,
2715 mips_isa
< 3 ? "addiu" : "daddiu",
2716 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
2717 if (ex
.X_add_number
!= 0)
2719 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
2720 as_bad ("PIC code offset overflow (max 16 signed bits)");
2721 ex
.X_op
= O_constant
;
2722 macro_build ((char *) NULL
, counter
, &ex
,
2723 mips_isa
< 3 ? "addiu" : "daddiu",
2724 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
2727 else if (mips_pic
== SVR4_PIC
)
2732 /* This is the large GOT case. If this is a reference to an
2733 external symbol, we want
2734 lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
2736 lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16)
2737 Otherwise, for a reference to a local symbol, we want
2738 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
2740 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
2741 If there is a constant, it must be added in after. */
2742 ex
.X_add_number
= ep
->X_add_number
;
2743 ep
->X_add_number
= 0;
2744 if (reg_needs_delay (GP
))
2749 macro_build ((char *) NULL
, counter
, ep
, "lui", "t,u", reg
,
2750 (int) BFD_RELOC_MIPS_GOT_HI16
);
2751 macro_build ((char *) NULL
, counter
, (expressionS
*) NULL
,
2752 mips_isa
< 3 ? "addu" : "daddu",
2753 "d,v,t", reg
, reg
, GP
);
2754 macro_build ((char *) NULL
, counter
, ep
,
2755 mips_isa
< 3 ? "lw" : "ld",
2756 "t,o(b)", reg
, (int) BFD_RELOC_MIPS_GOT_LO16
, reg
);
2757 p
= frag_var (rs_machine_dependent
, 12 + off
, 0,
2758 RELAX_ENCODE (12, 12 + off
, off
, 8 + off
, 0,
2759 mips_warn_about_macros
),
2760 ep
->X_add_symbol
, (long) 0, (char *) NULL
);
2763 /* We need a nop before loading from $gp. This special
2764 check is required because the lui which starts the main
2765 instruction stream does not refer to $gp, and so will not
2766 insert the nop which may be required. */
2767 macro_build (p
, counter
, (expressionS
*) NULL
, "nop", "");
2770 macro_build (p
, counter
, ep
,
2771 mips_isa
< 3 ? "lw" : "ld",
2772 "t,o(b)", reg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
2774 macro_build (p
, counter
, (expressionS
*) NULL
, "nop", "");
2776 macro_build (p
, counter
, ep
,
2777 mips_isa
< 3 ? "addiu" : "daddiu",
2778 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
2779 if (ex
.X_add_number
!= 0)
2781 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
2782 as_bad ("PIC code offset overflow (max 16 signed bits)");
2783 ex
.X_op
= O_constant
;
2784 macro_build ((char *) NULL
, counter
, &ex
,
2785 mips_isa
< 3 ? "addiu" : "daddiu",
2786 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
2789 else if (mips_pic
== EMBEDDED_PIC
)
2792 addiu $reg,$gp,<sym> (BFD_RELOC_MIPS_GPREL)
2794 macro_build ((char *) NULL
, counter
, ep
,
2795 mips_isa
< 3 ? "addiu" : "daddiu",
2796 "t,r,j", reg
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
2804 * This routine implements the seemingly endless macro or synthesized
2805 * instructions and addressing modes in the mips assembly language. Many
2806 * of these macros are simple and are similar to each other. These could
2807 * probably be handled by some kind of table or grammer aproach instead of
2808 * this verbose method. Others are not simple macros but are more like
2809 * optimizing code generation.
2810 * One interesting optimization is when several store macros appear
2811 * consecutivly that would load AT with the upper half of the same address.
2812 * The ensuing load upper instructions are ommited. This implies some kind
2813 * of global optimization. We currently only optimize within a single macro.
2814 * For many of the load and store macros if the address is specified as a
2815 * constant expression in the first 64k of memory (ie ld $2,0x4000c) we
2816 * first load register 'at' with zero and use it as the base register. The
2817 * mips assembler simply uses register $zero. Just one tiny optimization
2822 struct mips_cl_insn
*ip
;
2824 register int treg
, sreg
, dreg
, breg
;
2839 bfd_reloc_code_real_type r
;
2841 int hold_mips_optimize
;
2845 treg
= (ip
->insn_opcode
>> 16) & 0x1f;
2846 dreg
= (ip
->insn_opcode
>> 11) & 0x1f;
2847 sreg
= breg
= (ip
->insn_opcode
>> 21) & 0x1f;
2848 mask
= ip
->insn_mo
->mask
;
2850 expr1
.X_op
= O_constant
;
2851 expr1
.X_op_symbol
= NULL
;
2852 expr1
.X_add_symbol
= NULL
;
2853 expr1
.X_add_number
= 1;
2865 mips_emit_delays ();
2867 mips_any_noreorder
= 1;
2869 expr1
.X_add_number
= 8;
2870 macro_build ((char *) NULL
, &icnt
, &expr1
, "bgez", "s,p", sreg
);
2872 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
2874 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
, sreg
, 0);
2875 macro_build ((char *) NULL
, &icnt
, NULL
,
2876 dbl
? "dsub" : "sub",
2877 "d,v,t", dreg
, 0, sreg
);
2900 if (imm_expr
.X_add_number
>= -0x8000 && imm_expr
.X_add_number
< 0x8000)
2902 macro_build ((char *) NULL
, &icnt
, &imm_expr
, s
, "t,r,j", treg
, sreg
,
2903 (int) BFD_RELOC_LO16
);
2906 load_register (&icnt
, AT
, &imm_expr
, dbl
);
2907 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "d,v,t", treg
, sreg
, AT
);
2926 if (imm_expr
.X_add_number
>= 0 && imm_expr
.X_add_number
< 0x10000)
2928 if (mask
!= M_NOR_I
)
2929 macro_build ((char *) NULL
, &icnt
, &imm_expr
, s
, "t,r,i", treg
,
2930 sreg
, (int) BFD_RELOC_LO16
);
2933 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "ori", "t,r,i",
2934 treg
, sreg
, (int) BFD_RELOC_LO16
);
2935 macro_build ((char *) NULL
, &icnt
, NULL
, "nor", "d,v,t",
2941 load_register (&icnt
, AT
, &imm_expr
, 0);
2942 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "d,v,t", treg
, sreg
, AT
);
2959 if (imm_expr
.X_add_number
== 0)
2961 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "s,t,p", sreg
,
2965 load_register (&icnt
, AT
, &imm_expr
, 0);
2966 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "s,t,p", sreg
, AT
);
2974 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2975 likely
? "bgezl" : "bgez",
2981 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2982 likely
? "blezl" : "blez",
2986 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", AT
, sreg
, treg
);
2987 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2988 likely
? "beql" : "beq",
2995 /* check for > max integer */
2996 maxnum
= 0x7fffffff;
3004 if (imm_expr
.X_add_number
>= maxnum
3005 && (mips_isa
< 3 || sizeof (maxnum
) > 4))
3008 /* result is always false */
3011 as_warn ("Branch %s is always false (nop)", ip
->insn_mo
->name
);
3012 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
3016 as_warn ("Branch likely %s is always false", ip
->insn_mo
->name
);
3017 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "bnel",
3022 imm_expr
.X_add_number
++;
3026 if (mask
== M_BGEL_I
)
3028 if (imm_expr
.X_add_number
== 0)
3030 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3031 likely
? "bgezl" : "bgez",
3035 if (imm_expr
.X_add_number
== 1)
3037 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3038 likely
? "bgtzl" : "bgtz",
3042 maxnum
= 0x7fffffff;
3050 maxnum
= - maxnum
- 1;
3051 if (imm_expr
.X_add_number
<= maxnum
3052 && (mips_isa
< 3 || sizeof (maxnum
) > 4))
3055 /* result is always true */
3056 as_warn ("Branch %s is always true", ip
->insn_mo
->name
);
3057 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "b", "p");
3060 set_at (&icnt
, sreg
, 0);
3061 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3062 likely
? "beql" : "beq",
3073 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3074 likely
? "beql" : "beq",
3078 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", AT
, sreg
,
3080 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3081 likely
? "beql" : "beq",
3088 if (sreg
== 0 || imm_expr
.X_add_number
== -1)
3090 imm_expr
.X_add_number
++;
3094 if (mask
== M_BGEUL_I
)
3096 if (imm_expr
.X_add_number
== 0)
3098 if (imm_expr
.X_add_number
== 1)
3100 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3101 likely
? "bnel" : "bne",
3105 set_at (&icnt
, sreg
, 1);
3106 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3107 likely
? "beql" : "beq",
3116 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3117 likely
? "bgtzl" : "bgtz",
3123 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3124 likely
? "bltzl" : "bltz",
3128 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", AT
, treg
, sreg
);
3129 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3130 likely
? "bnel" : "bne",
3139 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3140 likely
? "bnel" : "bne",
3146 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", AT
, treg
,
3148 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3149 likely
? "bnel" : "bne",
3158 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3159 likely
? "blezl" : "blez",
3165 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3166 likely
? "bgezl" : "bgez",
3170 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", AT
, treg
, sreg
);
3171 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3172 likely
? "beql" : "beq",
3179 maxnum
= 0x7fffffff;
3187 if (imm_expr
.X_add_number
>= maxnum
3188 && (mips_isa
< 3 || sizeof (maxnum
) > 4))
3190 imm_expr
.X_add_number
++;
3194 if (mask
== M_BLTL_I
)
3196 if (imm_expr
.X_add_number
== 0)
3198 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3199 likely
? "bltzl" : "bltz",
3203 if (imm_expr
.X_add_number
== 1)
3205 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3206 likely
? "blezl" : "blez",
3210 set_at (&icnt
, sreg
, 0);
3211 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3212 likely
? "bnel" : "bne",
3221 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3222 likely
? "beql" : "beq",
3228 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", AT
, treg
,
3230 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3231 likely
? "beql" : "beq",
3238 if (sreg
== 0 || imm_expr
.X_add_number
== -1)
3240 imm_expr
.X_add_number
++;
3244 if (mask
== M_BLTUL_I
)
3246 if (imm_expr
.X_add_number
== 0)
3248 if (imm_expr
.X_add_number
== 1)
3250 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3251 likely
? "beql" : "beq",
3255 set_at (&icnt
, sreg
, 1);
3256 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3257 likely
? "bnel" : "bne",
3266 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3267 likely
? "bltzl" : "bltz",
3273 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3274 likely
? "bgtzl" : "bgtz",
3278 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", AT
, sreg
, treg
);
3279 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3280 likely
? "bnel" : "bne",
3291 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3292 likely
? "bnel" : "bne",
3296 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", AT
, sreg
,
3298 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3299 likely
? "bnel" : "bne",
3315 as_warn ("Divide by zero.");
3317 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", 0, 0);
3319 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 7);
3323 mips_emit_delays ();
3325 mips_any_noreorder
= 1;
3326 macro_build ((char *) NULL
, &icnt
, NULL
,
3327 dbl
? "ddiv" : "div",
3328 "z,s,t", sreg
, treg
);
3330 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", treg
, 0);
3333 expr1
.X_add_number
= 8;
3334 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", treg
, 0);
3335 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
3336 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 7);
3338 expr1
.X_add_number
= -1;
3339 macro_build ((char *) NULL
, &icnt
, &expr1
,
3340 dbl
? "daddiu" : "addiu",
3341 "t,r,j", AT
, 0, (int) BFD_RELOC_LO16
);
3342 expr1
.X_add_number
= mips_trap
? (dbl
? 12 : 8) : (dbl
? 20 : 16);
3343 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", treg
, AT
);
3346 expr1
.X_add_number
= 1;
3347 macro_build ((char *) NULL
, &icnt
, &expr1
, "daddiu", "t,r,j", AT
, 0,
3348 (int) BFD_RELOC_LO16
);
3349 macro_build ((char *) NULL
, &icnt
, NULL
, "dsll32", "d,w,<", AT
, AT
,
3354 expr1
.X_add_number
= 0x80000000;
3355 macro_build ((char *) NULL
, &icnt
, &expr1
, "lui", "t,u", AT
,
3356 (int) BFD_RELOC_HI16
);
3359 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", sreg
, AT
);
3362 expr1
.X_add_number
= 8;
3363 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", sreg
, AT
);
3364 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
3365 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 6);
3368 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d", dreg
);
3407 if (imm_expr
.X_add_number
== 0)
3409 as_warn ("Divide by zero.");
3411 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", 0, 0);
3413 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 7);
3416 if (imm_expr
.X_add_number
== 1)
3418 if (strcmp (s2
, "mflo") == 0)
3419 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
,
3422 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
, 0);
3425 if (imm_expr
.X_add_number
== -1
3426 && s
[strlen (s
) - 1] != 'u')
3428 if (strcmp (s2
, "mflo") == 0)
3431 macro_build ((char *) NULL
, &icnt
, NULL
, "dneg", "d,w", dreg
,
3434 macro_build ((char *) NULL
, &icnt
, NULL
, "neg", "d,w", dreg
,
3438 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
, 0);
3442 load_register (&icnt
, AT
, &imm_expr
, dbl
);
3443 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "z,s,t", sreg
, AT
);
3444 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "d", dreg
);
3463 mips_emit_delays ();
3465 mips_any_noreorder
= 1;
3466 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "z,s,t", sreg
, treg
);
3468 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", treg
, 0);
3471 expr1
.X_add_number
= 8;
3472 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", treg
, 0);
3473 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
3474 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 7);
3477 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "d", dreg
);
3483 /* Load the address of a symbol into a register. If breg is not
3484 zero, we then add a base register to it. */
3486 /* When generating embedded PIC code, we permit expressions of
3489 where bar is an address in the .text section. These are used
3490 when getting the addresses of functions. We don't permit
3491 X_add_number to be non-zero, because if the symbol is
3492 external the relaxing code needs to know that any addend is
3493 purely the offset to X_op_symbol. */
3494 if (mips_pic
== EMBEDDED_PIC
3495 && offset_expr
.X_op
== O_subtract
3496 && now_seg
== text_section
3497 && (offset_expr
.X_op_symbol
->sy_value
.X_op
== O_constant
3498 ? S_GET_SEGMENT (offset_expr
.X_op_symbol
) == text_section
3499 : (offset_expr
.X_op_symbol
->sy_value
.X_op
== O_symbol
3500 && (S_GET_SEGMENT (offset_expr
.X_op_symbol
3501 ->sy_value
.X_add_symbol
)
3504 && offset_expr
.X_add_number
== 0)
3506 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
3507 treg
, (int) BFD_RELOC_PCREL_HI16_S
);
3508 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3509 mips_isa
< 3 ? "addiu" : "daddiu",
3510 "t,r,j", treg
, treg
, (int) BFD_RELOC_PCREL_LO16
);
3514 if (offset_expr
.X_op
!= O_symbol
3515 && offset_expr
.X_op
!= O_constant
)
3517 as_bad ("expression too complex");
3518 offset_expr
.X_op
= O_constant
;
3532 if (offset_expr
.X_op
== O_constant
)
3533 load_register (&icnt
, tempreg
, &offset_expr
, dbl
);
3534 else if (mips_pic
== NO_PIC
)
3536 /* If this is a reference to an GP relative symbol, we want
3537 addiu $tempreg,$gp,<sym> (BFD_RELOC_MIPS_GPREL)
3539 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
3540 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
3541 If we have a constant, we need two instructions anyhow,
3542 so we may as well always use the latter form. */
3543 if ((valueT
) offset_expr
.X_add_number
>= MAX_GPREL_OFFSET
3544 || nopic_need_relax (offset_expr
.X_add_symbol
))
3549 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3550 mips_isa
< 3 ? "addiu" : "daddiu",
3551 "t,r,j", tempreg
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
3552 p
= frag_var (rs_machine_dependent
, 8, 0,
3553 RELAX_ENCODE (4, 8, 0, 4, 0,
3554 mips_warn_about_macros
),
3555 offset_expr
.X_add_symbol
, (long) 0,
3558 macro_build_lui (p
, &icnt
, &offset_expr
, tempreg
);
3561 macro_build (p
, &icnt
, &offset_expr
,
3562 mips_isa
< 3 ? "addiu" : "daddiu",
3563 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
3565 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
3567 /* If this is a reference to an external symbol, and there
3568 is no constant, we want
3569 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3570 For a local symbol, we want
3571 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3573 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
3575 If we have a small constant, and this is a reference to
3576 an external symbol, we want
3577 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3579 addiu $tempreg,$tempreg,<constant>
3580 For a local symbol, we want the same instruction
3581 sequence, but we output a BFD_RELOC_LO16 reloc on the
3584 If we have a large constant, and this is a reference to
3585 an external symbol, we want
3586 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3587 lui $at,<hiconstant>
3588 addiu $at,$at,<loconstant>
3589 addu $tempreg,$tempreg,$at
3590 For a local symbol, we want the same instruction
3591 sequence, but we output a BFD_RELOC_LO16 reloc on the
3592 addiu instruction. */
3593 expr1
.X_add_number
= offset_expr
.X_add_number
;
3594 offset_expr
.X_add_number
= 0;
3596 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3598 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
3599 if (expr1
.X_add_number
== 0)
3607 /* We're going to put in an addu instruction using
3608 tempreg, so we may as well insert the nop right
3610 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3614 p
= frag_var (rs_machine_dependent
, 8 - off
, 0,
3615 RELAX_ENCODE (0, 8 - off
, -4 - off
, 4 - off
, 0,
3617 ? mips_warn_about_macros
3619 offset_expr
.X_add_symbol
, (long) 0,
3623 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
3626 macro_build (p
, &icnt
, &expr1
,
3627 mips_isa
< 3 ? "addiu" : "daddiu",
3628 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
3629 /* FIXME: If breg == 0, and the next instruction uses
3630 $tempreg, then if this variant case is used an extra
3631 nop will be generated. */
3633 else if (expr1
.X_add_number
>= -0x8000
3634 && expr1
.X_add_number
< 0x8000)
3636 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3638 macro_build ((char *) NULL
, &icnt
, &expr1
,
3639 mips_isa
< 3 ? "addiu" : "daddiu",
3640 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
3641 (void) frag_var (rs_machine_dependent
, 0, 0,
3642 RELAX_ENCODE (0, 0, -12, -4, 0, 0),
3643 offset_expr
.X_add_symbol
, (long) 0,
3650 /* If we are going to add in a base register, and the
3651 target register and the base register are the same,
3652 then we are using AT as a temporary register. Since
3653 we want to load the constant into AT, we add our
3654 current AT (from the global offset table) and the
3655 register into the register now, and pretend we were
3656 not using a base register. */
3661 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3663 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3664 mips_isa
< 3 ? "addu" : "daddu",
3665 "d,v,t", treg
, AT
, breg
);
3671 /* Set mips_optimize around the lui instruction to avoid
3672 inserting an unnecessary nop after the lw. */
3673 hold_mips_optimize
= mips_optimize
;
3675 macro_build_lui ((char *) NULL
, &icnt
, &expr1
, AT
);
3676 mips_optimize
= hold_mips_optimize
;
3678 macro_build ((char *) NULL
, &icnt
, &expr1
,
3679 mips_isa
< 3 ? "addiu" : "daddiu",
3680 "t,r,j", AT
, AT
, (int) BFD_RELOC_LO16
);
3681 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3682 mips_isa
< 3 ? "addu" : "daddu",
3683 "d,v,t", tempreg
, tempreg
, AT
);
3684 (void) frag_var (rs_machine_dependent
, 0, 0,
3685 RELAX_ENCODE (0, 0, -16 + off1
, -8, 0, 0),
3686 offset_expr
.X_add_symbol
, (long) 0,
3691 else if (mips_pic
== SVR4_PIC
)
3695 /* This is the large GOT case. If this is a reference to an
3696 external symbol, and there is no constant, we want
3697 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
3698 addu $tempreg,$tempreg,$gp
3699 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
3700 For a local symbol, we want
3701 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3703 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
3705 If we have a small constant, and this is a reference to
3706 an external symbol, we want
3707 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
3708 addu $tempreg,$tempreg,$gp
3709 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
3711 addiu $tempreg,$tempreg,<constant>
3712 For a local symbol, we want
3713 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3715 addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16)
3717 If we have a large constant, and this is a reference to
3718 an external symbol, we want
3719 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
3720 addu $tempreg,$tempreg,$gp
3721 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
3722 lui $at,<hiconstant>
3723 addiu $at,$at,<loconstant>
3724 addu $tempreg,$tempreg,$at
3725 For a local symbol, we want
3726 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3727 lui $at,<hiconstant>
3728 addiu $at,$at,<loconstant> (BFD_RELOC_LO16)
3729 addu $tempreg,$tempreg,$at
3731 expr1
.X_add_number
= offset_expr
.X_add_number
;
3732 offset_expr
.X_add_number
= 0;
3734 if (reg_needs_delay (GP
))
3738 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
3739 tempreg
, (int) BFD_RELOC_MIPS_GOT_HI16
);
3740 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3741 mips_isa
< 3 ? "addu" : "daddu",
3742 "d,v,t", tempreg
, tempreg
, GP
);
3743 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3745 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT_LO16
,
3747 if (expr1
.X_add_number
== 0)
3755 /* We're going to put in an addu instruction using
3756 tempreg, so we may as well insert the nop right
3758 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3763 p
= frag_var (rs_machine_dependent
, 12 + gpdel
, 0,
3764 RELAX_ENCODE (12 + off
, 12 + gpdel
, gpdel
,
3767 ? mips_warn_about_macros
3769 offset_expr
.X_add_symbol
, (long) 0,
3772 else if (expr1
.X_add_number
>= -0x8000
3773 && expr1
.X_add_number
< 0x8000)
3775 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3777 macro_build ((char *) NULL
, &icnt
, &expr1
,
3778 mips_isa
< 3 ? "addiu" : "daddiu",
3779 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
3781 p
= frag_var (rs_machine_dependent
, 12 + gpdel
, 0,
3782 RELAX_ENCODE (20, 12 + gpdel
, gpdel
, 8 + gpdel
, 0,
3784 ? mips_warn_about_macros
3786 offset_expr
.X_add_symbol
, (long) 0,
3793 /* If we are going to add in a base register, and the
3794 target register and the base register are the same,
3795 then we are using AT as a temporary register. Since
3796 we want to load the constant into AT, we add our
3797 current AT (from the global offset table) and the
3798 register into the register now, and pretend we were
3799 not using a base register. */
3807 assert (tempreg
== AT
);
3808 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3810 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3811 mips_isa
< 3 ? "addu" : "daddu",
3812 "d,v,t", treg
, AT
, breg
);
3817 /* Set mips_optimize around the lui instruction to avoid
3818 inserting an unnecessary nop after the lw. */
3819 hold_mips_optimize
= mips_optimize
;
3821 macro_build_lui ((char *) NULL
, &icnt
, &expr1
, AT
);
3822 mips_optimize
= hold_mips_optimize
;
3824 macro_build ((char *) NULL
, &icnt
, &expr1
,
3825 mips_isa
< 3 ? "addiu" : "daddiu",
3826 "t,r,j", AT
, AT
, (int) BFD_RELOC_LO16
);
3827 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3828 mips_isa
< 3 ? "addu" : "daddu",
3829 "d,v,t", dreg
, dreg
, AT
);
3831 p
= frag_var (rs_machine_dependent
, 16 + gpdel
+ adj
, 0,
3832 RELAX_ENCODE (24 + adj
, 16 + gpdel
+ adj
, gpdel
,
3835 ? mips_warn_about_macros
3837 offset_expr
.X_add_symbol
, (long) 0,
3845 /* This is needed because this instruction uses $gp, but
3846 the first instruction on the main stream does not. */
3847 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
3850 macro_build (p
, &icnt
, &offset_expr
,
3852 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
3854 if (expr1
.X_add_number
>= -0x8000
3855 && expr1
.X_add_number
< 0x8000)
3857 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
3859 macro_build (p
, &icnt
, &expr1
,
3860 mips_isa
< 3 ? "addiu" : "daddiu",
3861 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
3862 /* FIXME: If add_number is 0, and there was no base
3863 register, the external symbol case ended with a load,
3864 so if the symbol turns out to not be external, and
3865 the next instruction uses tempreg, an unnecessary nop
3866 will be inserted. */
3872 /* We must add in the base register now, as in the
3873 external symbol case. */
3874 assert (tempreg
== AT
);
3875 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
3877 macro_build (p
, &icnt
, (expressionS
*) NULL
,
3878 mips_isa
< 3 ? "addu" : "daddu",
3879 "d,v,t", treg
, AT
, breg
);
3882 /* We set breg to 0 because we have arranged to add
3883 it in in both cases. */
3887 macro_build_lui (p
, &icnt
, &expr1
, AT
);
3889 macro_build (p
, &icnt
, &expr1
,
3890 mips_isa
< 3 ? "addiu" : "daddiu",
3891 "t,r,j", AT
, AT
, (int) BFD_RELOC_LO16
);
3893 macro_build (p
, &icnt
, (expressionS
*) NULL
,
3894 mips_isa
< 3 ? "addu" : "daddu",
3895 "d,v,t", tempreg
, tempreg
, AT
);
3899 else if (mips_pic
== EMBEDDED_PIC
)
3902 addiu $tempreg,$gp,<sym> (BFD_RELOC_MIPS_GPREL)
3904 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3905 mips_isa
< 3 ? "addiu" : "daddiu",
3906 "t,r,j", tempreg
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
3912 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3913 mips_isa
< 3 ? "addu" : "daddu",
3914 "d,v,t", treg
, tempreg
, breg
);
3922 /* The j instruction may not be used in PIC code, since it
3923 requires an absolute address. We convert it to a b
3925 if (mips_pic
== NO_PIC
)
3926 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "j", "a");
3928 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "b", "p");
3931 /* The jal instructions must be handled as macros because when
3932 generating PIC code they expand to multi-instruction
3933 sequences. Normally they are simple instructions. */
3938 if (mips_pic
== NO_PIC
3939 || mips_pic
== EMBEDDED_PIC
)
3940 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "jalr",
3942 else if (mips_pic
== SVR4_PIC
)
3944 if (sreg
!= PIC_CALL_REG
)
3945 as_warn ("MIPS PIC call to register other than $25");
3947 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "jalr",
3949 if (mips_cprestore_offset
< 0)
3950 as_warn ("No .cprestore pseudo-op used in PIC code");
3953 expr1
.X_add_number
= mips_cprestore_offset
;
3954 macro_build ((char *) NULL
, &icnt
, &expr1
,
3955 mips_isa
< 3 ? "lw" : "ld",
3956 "t,o(b)", GP
, (int) BFD_RELOC_LO16
, mips_frame_reg
);
3965 if (mips_pic
== NO_PIC
)
3966 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "jal", "a");
3967 else if (mips_pic
== SVR4_PIC
)
3969 /* If this is a reference to an external symbol, and we are
3970 using a small GOT, we want
3971 lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
3975 lw $gp,cprestore($sp)
3976 The cprestore value is set using the .cprestore
3977 pseudo-op. If we are using a big GOT, we want
3978 lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16)
3980 lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16)
3984 lw $gp,cprestore($sp)
3985 If the symbol is not external, we want
3986 lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3988 addiu $25,$25,<sym> (BFD_RELOC_LO16)
3991 lw $gp,cprestore($sp) */
3995 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3996 mips_isa
< 3 ? "lw" : "ld",
3997 "t,o(b)", PIC_CALL_REG
,
3998 (int) BFD_RELOC_MIPS_CALL16
, GP
);
3999 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4001 p
= frag_var (rs_machine_dependent
, 4, 0,
4002 RELAX_ENCODE (0, 4, -8, 0, 0, 0),
4003 offset_expr
.X_add_symbol
, (long) 0, (char *) NULL
);
4009 if (reg_needs_delay (GP
))
4013 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
4014 PIC_CALL_REG
, (int) BFD_RELOC_MIPS_CALL_HI16
);
4015 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4016 mips_isa
< 3 ? "addu" : "daddu",
4017 "d,v,t", PIC_CALL_REG
, PIC_CALL_REG
, GP
);
4018 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4019 mips_isa
< 3 ? "lw" : "ld",
4020 "t,o(b)", PIC_CALL_REG
,
4021 (int) BFD_RELOC_MIPS_CALL_LO16
, PIC_CALL_REG
);
4022 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4024 p
= frag_var (rs_machine_dependent
, 12 + gpdel
, 0,
4025 RELAX_ENCODE (16, 12 + gpdel
, gpdel
, 8 + gpdel
,
4027 offset_expr
.X_add_symbol
, (long) 0, (char *) NULL
);
4030 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4033 macro_build (p
, &icnt
, &offset_expr
,
4034 mips_isa
< 3 ? "lw" : "ld",
4035 "t,o(b)", PIC_CALL_REG
,
4036 (int) BFD_RELOC_MIPS_GOT16
, GP
);
4038 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4041 macro_build (p
, &icnt
, &offset_expr
,
4042 mips_isa
< 3 ? "addiu" : "daddiu",
4043 "t,r,j", PIC_CALL_REG
, PIC_CALL_REG
,
4044 (int) BFD_RELOC_LO16
);
4045 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4046 "jalr", "s", PIC_CALL_REG
);
4047 if (mips_cprestore_offset
< 0)
4048 as_warn ("No .cprestore pseudo-op used in PIC code");
4052 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4054 expr1
.X_add_number
= mips_cprestore_offset
;
4055 macro_build ((char *) NULL
, &icnt
, &expr1
,
4056 mips_isa
< 3 ? "lw" : "ld",
4057 "t,o(b)", GP
, (int) BFD_RELOC_LO16
,
4061 else if (mips_pic
== EMBEDDED_PIC
)
4063 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "bal", "p");
4064 /* The linker may expand the call to a longer sequence which
4065 uses $at, so we must break rather than return. */
4141 if (breg
== treg
|| coproc
|| lr
)
4210 if (mask
== M_LWC1_AB
4211 || mask
== M_SWC1_AB
4212 || mask
== M_LDC1_AB
4213 || mask
== M_SDC1_AB
4222 if (offset_expr
.X_op
!= O_constant
4223 && offset_expr
.X_op
!= O_symbol
)
4225 as_bad ("expression too complex");
4226 offset_expr
.X_op
= O_constant
;
4229 /* A constant expression in PIC code can be handled just as it
4230 is in non PIC code. */
4231 if (mips_pic
== NO_PIC
4232 || offset_expr
.X_op
== O_constant
)
4234 /* If this is a reference to a GP relative symbol, and there
4235 is no base register, we want
4236 <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL)
4237 Otherwise, if there is no base register, we want
4238 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
4239 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
4240 If we have a constant, we need two instructions anyhow,
4241 so we always use the latter form.
4243 If we have a base register, and this is a reference to a
4244 GP relative symbol, we want
4245 addu $tempreg,$breg,$gp
4246 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GPREL)
4248 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
4249 addu $tempreg,$tempreg,$breg
4250 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
4251 With a constant we always use the latter case. */
4254 if ((valueT
) offset_expr
.X_add_number
>= MAX_GPREL_OFFSET
4255 || nopic_need_relax (offset_expr
.X_add_symbol
))
4260 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
4261 treg
, (int) BFD_RELOC_MIPS_GPREL
, GP
);
4262 p
= frag_var (rs_machine_dependent
, 8, 0,
4263 RELAX_ENCODE (4, 8, 0, 4, 0,
4264 (mips_warn_about_macros
4265 || (used_at
&& mips_noat
))),
4266 offset_expr
.X_add_symbol
, (long) 0,
4270 macro_build_lui (p
, &icnt
, &offset_expr
, tempreg
);
4273 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
, treg
,
4274 (int) BFD_RELOC_LO16
, tempreg
);
4278 if ((valueT
) offset_expr
.X_add_number
>= MAX_GPREL_OFFSET
4279 || nopic_need_relax (offset_expr
.X_add_symbol
))
4284 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4285 mips_isa
< 3 ? "addu" : "daddu",
4286 "d,v,t", tempreg
, breg
, GP
);
4287 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
4288 treg
, (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
4289 p
= frag_var (rs_machine_dependent
, 12, 0,
4290 RELAX_ENCODE (8, 12, 0, 8, 0, 0),
4291 offset_expr
.X_add_symbol
, (long) 0,
4294 macro_build_lui (p
, &icnt
, &offset_expr
, tempreg
);
4297 macro_build (p
, &icnt
, (expressionS
*) NULL
,
4298 mips_isa
< 3 ? "addu" : "daddu",
4299 "d,v,t", tempreg
, tempreg
, breg
);
4302 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
, treg
,
4303 (int) BFD_RELOC_LO16
, tempreg
);
4306 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
4308 /* If this is a reference to an external symbol, we want
4309 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4311 <op> $treg,0($tempreg)
4313 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4315 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
4316 <op> $treg,0($tempreg)
4317 If there is a base register, we add it to $tempreg before
4318 the <op>. If there is a constant, we stick it in the
4319 <op> instruction. We don't handle constants larger than
4320 16 bits, because we have no way to load the upper 16 bits
4321 (actually, we could handle them for the subset of cases
4322 in which we are not using $at). */
4323 assert (offset_expr
.X_op
== O_symbol
);
4324 expr1
.X_add_number
= offset_expr
.X_add_number
;
4325 offset_expr
.X_add_number
= 0;
4326 if (expr1
.X_add_number
< -0x8000
4327 || expr1
.X_add_number
>= 0x8000)
4328 as_bad ("PIC code offset overflow (max 16 signed bits)");
4330 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4331 mips_isa
< 3 ? "lw" : "ld",
4332 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
4333 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
4334 p
= frag_var (rs_machine_dependent
, 4, 0,
4335 RELAX_ENCODE (0, 4, -8, 0, 0, 0),
4336 offset_expr
.X_add_symbol
, (long) 0,
4338 macro_build (p
, &icnt
, &offset_expr
,
4339 mips_isa
< 3 ? "addiu" : "daddiu",
4340 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
4342 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4343 mips_isa
< 3 ? "addu" : "daddu",
4344 "d,v,t", tempreg
, tempreg
, breg
);
4345 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
, treg
,
4346 (int) BFD_RELOC_LO16
, tempreg
);
4348 else if (mips_pic
== SVR4_PIC
)
4352 /* If this is a reference to an external symbol, we want
4353 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
4354 addu $tempreg,$tempreg,$gp
4355 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
4356 <op> $treg,0($tempreg)
4358 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4360 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
4361 <op> $treg,0($tempreg)
4362 If there is a base register, we add it to $tempreg before
4363 the <op>. If there is a constant, we stick it in the
4364 <op> instruction. We don't handle constants larger than
4365 16 bits, because we have no way to load the upper 16 bits
4366 (actually, we could handle them for the subset of cases
4367 in which we are not using $at). */
4368 assert (offset_expr
.X_op
== O_symbol
);
4369 expr1
.X_add_number
= offset_expr
.X_add_number
;
4370 offset_expr
.X_add_number
= 0;
4371 if (expr1
.X_add_number
< -0x8000
4372 || expr1
.X_add_number
>= 0x8000)
4373 as_bad ("PIC code offset overflow (max 16 signed bits)");
4374 if (reg_needs_delay (GP
))
4379 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
4380 tempreg
, (int) BFD_RELOC_MIPS_GOT_HI16
);
4381 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4382 mips_isa
< 3 ? "addu" : "daddu",
4383 "d,v,t", tempreg
, tempreg
, GP
);
4384 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4385 mips_isa
< 3 ? "lw" : "ld",
4386 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT_LO16
,
4388 p
= frag_var (rs_machine_dependent
, 12 + gpdel
, 0,
4389 RELAX_ENCODE (12, 12 + gpdel
, gpdel
, 8 + gpdel
, 0, 0),
4390 offset_expr
.X_add_symbol
, (long) 0, (char *) NULL
);
4393 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4396 macro_build (p
, &icnt
, &offset_expr
,
4397 mips_isa
< 3 ? "lw" : "ld",
4398 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
4400 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4402 macro_build (p
, &icnt
, &offset_expr
,
4403 mips_isa
< 3 ? "addiu" : "daddiu",
4404 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
4406 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4407 mips_isa
< 3 ? "addu" : "daddu",
4408 "d,v,t", tempreg
, tempreg
, breg
);
4409 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
, treg
,
4410 (int) BFD_RELOC_LO16
, tempreg
);
4412 else if (mips_pic
== EMBEDDED_PIC
)
4414 /* If there is no base register, we want
4415 <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL)
4416 If there is a base register, we want
4417 addu $tempreg,$breg,$gp
4418 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GPREL)
4420 assert (offset_expr
.X_op
== O_symbol
);
4423 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
4424 treg
, (int) BFD_RELOC_MIPS_GPREL
, GP
);
4429 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4430 mips_isa
< 3 ? "addu" : "daddu",
4431 "d,v,t", tempreg
, breg
, GP
);
4432 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
4433 treg
, (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
4446 load_register (&icnt
, treg
, &imm_expr
, 0);
4450 load_register (&icnt
, treg
, &imm_expr
, 1);
4454 if (imm_expr
.X_op
== O_constant
)
4456 load_register (&icnt
, AT
, &imm_expr
, 0);
4457 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4458 "mtc1", "t,G", AT
, treg
);
4463 assert (offset_expr
.X_op
== O_symbol
4464 && strcmp (segment_name (S_GET_SEGMENT
4465 (offset_expr
.X_add_symbol
)),
4467 && offset_expr
.X_add_number
== 0);
4468 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lwc1", "T,o(b)",
4469 treg
, (int) BFD_RELOC_MIPS_LITERAL
, GP
);
4474 /* We know that sym is in the .rdata section. First we get the
4475 upper 16 bits of the address. */
4476 if (mips_pic
== NO_PIC
)
4478 /* FIXME: This won't work for a 64 bit address. */
4479 macro_build_lui ((char *) NULL
, &icnt
, &offset_expr
, AT
);
4481 else if (mips_pic
== SVR4_PIC
)
4483 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4484 mips_isa
< 3 ? "lw" : "ld",
4485 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
4487 else if (mips_pic
== EMBEDDED_PIC
)
4489 /* For embedded PIC we pick up the entire address off $gp in
4490 a single instruction. */
4491 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4492 mips_isa
< 3 ? "addiu" : "daddiu",
4493 "t,r,j", AT
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
4494 offset_expr
.X_op
= O_constant
;
4495 offset_expr
.X_add_number
= 0;
4500 /* Now we load the register(s). */
4502 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "ld", "t,o(b)",
4503 treg
, (int) BFD_RELOC_LO16
, AT
);
4506 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lw", "t,o(b)",
4507 treg
, (int) BFD_RELOC_LO16
, AT
);
4510 /* FIXME: How in the world do we deal with the possible
4512 offset_expr
.X_add_number
+= 4;
4513 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lw", "t,o(b)",
4514 treg
+ 1, (int) BFD_RELOC_LO16
, AT
);
4518 /* To avoid confusion in tc_gen_reloc, we must ensure that this
4519 does not become a variant frag. */
4520 frag_wane (frag_now
);
4526 assert (offset_expr
.X_op
== O_symbol
4527 && offset_expr
.X_add_number
== 0);
4528 s
= segment_name (S_GET_SEGMENT (offset_expr
.X_add_symbol
));
4529 if (strcmp (s
, ".lit8") == 0)
4533 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "ldc1",
4534 "T,o(b)", treg
, (int) BFD_RELOC_MIPS_LITERAL
, GP
);
4538 r
= BFD_RELOC_MIPS_LITERAL
;
4543 assert (strcmp (s
, RDATA_SECTION_NAME
) == 0);
4544 if (mips_pic
== SVR4_PIC
)
4545 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4546 mips_isa
< 3 ? "lw" : "ld",
4547 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
4550 /* FIXME: This won't work for a 64 bit address. */
4551 macro_build_lui ((char *) NULL
, &icnt
, &offset_expr
, AT
);
4556 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "ldc1",
4557 "T,o(b)", treg
, (int) BFD_RELOC_LO16
, AT
);
4559 /* To avoid confusion in tc_gen_reloc, we must ensure
4560 that this does not become a variant frag. */
4561 frag_wane (frag_now
);
4572 /* Even on a big endian machine $fn comes before $fn+1. We have
4573 to adjust when loading from memory. */
4576 assert (mips_isa
< 2);
4577 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lwc1", "T,o(b)",
4578 byte_order
== LITTLE_ENDIAN
? treg
: treg
+ 1,
4580 /* FIXME: A possible overflow which I don't know how to deal
4582 offset_expr
.X_add_number
+= 4;
4583 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lwc1", "T,o(b)",
4584 byte_order
== LITTLE_ENDIAN
? treg
+ 1 : treg
,
4587 /* To avoid confusion in tc_gen_reloc, we must ensure that this
4588 does not become a variant frag. */
4589 frag_wane (frag_now
);
4598 * The MIPS assembler seems to check for X_add_number not
4599 * being double aligned and generating:
4602 * addiu at,at,%lo(foo+1)
4605 * But, the resulting address is the same after relocation so why
4606 * generate the extra instruction?
4653 if (offset_expr
.X_op
!= O_symbol
4654 && offset_expr
.X_op
!= O_constant
)
4656 as_bad ("expression too complex");
4657 offset_expr
.X_op
= O_constant
;
4660 /* Even on a big endian machine $fn comes before $fn+1. We have
4661 to adjust when loading from memory. We set coproc if we must
4662 load $fn+1 first. */
4663 if (byte_order
== LITTLE_ENDIAN
)
4666 if (mips_pic
== NO_PIC
4667 || offset_expr
.X_op
== O_constant
)
4669 /* If this is a reference to a GP relative symbol, we want
4670 <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL)
4671 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_MIPS_GPREL)
4672 If we have a base register, we use this
4674 <op> $treg,<sym>($at) (BFD_RELOC_MIPS_GPREL)
4675 <op> $treg+1,<sym>+4($at) (BFD_RELOC_MIPS_GPREL)
4676 If this is not a GP relative symbol, we want
4677 lui $at,<sym> (BFD_RELOC_HI16_S)
4678 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
4679 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
4680 If there is a base register, we add it to $at after the
4681 lui instruction. If there is a constant, we always use
4683 if ((valueT
) offset_expr
.X_add_number
>= MAX_GPREL_OFFSET
4684 || nopic_need_relax (offset_expr
.X_add_symbol
))
4703 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4704 mips_isa
< 3 ? "addu" : "daddu",
4705 "d,v,t", AT
, breg
, GP
);
4711 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
4712 coproc
? treg
+ 1 : treg
,
4713 (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
4714 offset_expr
.X_add_number
+= 4;
4716 /* Set mips_optimize to 2 to avoid inserting an
4718 hold_mips_optimize
= mips_optimize
;
4720 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
4721 coproc
? treg
: treg
+ 1,
4722 (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
4723 mips_optimize
= hold_mips_optimize
;
4725 p
= frag_var (rs_machine_dependent
, 12 + off
, 0,
4726 RELAX_ENCODE (8 + off
, 12 + off
, 0, 4 + off
, 1,
4727 used_at
&& mips_noat
),
4728 offset_expr
.X_add_symbol
, (long) 0,
4731 /* We just generated two relocs. When tc_gen_reloc
4732 handles this case, it will skip the first reloc and
4733 handle the second. The second reloc already has an
4734 extra addend of 4, which we added above. We must
4735 subtract it out, and then subtract another 4 to make
4736 the first reloc come out right. The second reloc
4737 will come out right because we are going to add 4 to
4738 offset_expr when we build its instruction below. */
4739 offset_expr
.X_add_number
-= 8;
4740 offset_expr
.X_op
= O_constant
;
4742 macro_build_lui (p
, &icnt
, &offset_expr
, AT
);
4747 macro_build (p
, &icnt
, (expressionS
*) NULL
,
4748 mips_isa
< 3 ? "addu" : "daddu",
4749 "d,v,t", AT
, breg
, AT
);
4753 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
,
4754 coproc
? treg
+ 1 : treg
,
4755 (int) BFD_RELOC_LO16
, AT
);
4758 /* FIXME: How do we handle overflow here? */
4759 offset_expr
.X_add_number
+= 4;
4760 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
,
4761 coproc
? treg
: treg
+ 1,
4762 (int) BFD_RELOC_LO16
, AT
);
4764 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
4768 /* If this is a reference to an external symbol, we want
4769 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4774 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4776 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
4777 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
4778 If there is a base register we add it to $at before the
4779 lwc1 instructions. If there is a constant we include it
4780 in the lwc1 instructions. */
4782 expr1
.X_add_number
= offset_expr
.X_add_number
;
4783 offset_expr
.X_add_number
= 0;
4784 if (expr1
.X_add_number
< -0x8000
4785 || expr1
.X_add_number
>= 0x8000 - 4)
4786 as_bad ("PIC code offset overflow (max 16 signed bits)");
4791 frag_grow (24 + off
);
4792 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4793 mips_isa
< 3 ? "lw" : "ld",
4794 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
4795 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
4797 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4798 mips_isa
< 3 ? "addu" : "daddu",
4799 "d,v,t", AT
, breg
, AT
);
4800 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
4801 coproc
? treg
+ 1 : treg
,
4802 (int) BFD_RELOC_LO16
, AT
);
4803 expr1
.X_add_number
+= 4;
4805 /* Set mips_optimize to 2 to avoid inserting an undesired
4807 hold_mips_optimize
= mips_optimize
;
4809 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
4810 coproc
? treg
: treg
+ 1,
4811 (int) BFD_RELOC_LO16
, AT
);
4812 mips_optimize
= hold_mips_optimize
;
4814 (void) frag_var (rs_machine_dependent
, 0, 0,
4815 RELAX_ENCODE (0, 0, -16 - off
, -8, 1, 0),
4816 offset_expr
.X_add_symbol
, (long) 0,
4819 else if (mips_pic
== SVR4_PIC
)
4823 /* If this is a reference to an external symbol, we want
4824 lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16)
4826 lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16)
4831 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4833 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
4834 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
4835 If there is a base register we add it to $at before the
4836 lwc1 instructions. If there is a constant we include it
4837 in the lwc1 instructions. */
4839 expr1
.X_add_number
= offset_expr
.X_add_number
;
4840 offset_expr
.X_add_number
= 0;
4841 if (expr1
.X_add_number
< -0x8000
4842 || expr1
.X_add_number
>= 0x8000 - 4)
4843 as_bad ("PIC code offset overflow (max 16 signed bits)");
4844 if (reg_needs_delay (GP
))
4853 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
4854 AT
, (int) BFD_RELOC_MIPS_GOT_HI16
);
4855 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4856 mips_isa
< 3 ? "addu" : "daddu",
4857 "d,v,t", AT
, AT
, GP
);
4858 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4859 mips_isa
< 3 ? "lw" : "ld",
4860 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT_LO16
, AT
);
4861 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
4863 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4864 mips_isa
< 3 ? "addu" : "daddu",
4865 "d,v,t", AT
, breg
, AT
);
4866 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
4867 coproc
? treg
+ 1 : treg
,
4868 (int) BFD_RELOC_LO16
, AT
);
4869 expr1
.X_add_number
+= 4;
4871 /* Set mips_optimize to 2 to avoid inserting an undesired
4873 hold_mips_optimize
= mips_optimize
;
4875 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
4876 coproc
? treg
: treg
+ 1,
4877 (int) BFD_RELOC_LO16
, AT
);
4878 mips_optimize
= hold_mips_optimize
;
4879 expr1
.X_add_number
-= 4;
4881 p
= frag_var (rs_machine_dependent
, 16 + gpdel
+ off
, 0,
4882 RELAX_ENCODE (24 + off
, 16 + gpdel
+ off
, gpdel
,
4883 8 + gpdel
+ off
, 1, 0),
4884 offset_expr
.X_add_symbol
, (long) 0,
4888 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4891 macro_build (p
, &icnt
, &offset_expr
,
4892 mips_isa
< 3 ? "lw" : "ld",
4893 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
4895 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4899 macro_build (p
, &icnt
, (expressionS
*) NULL
,
4900 mips_isa
< 3 ? "addu" : "daddu",
4901 "d,v,t", AT
, breg
, AT
);
4904 macro_build (p
, &icnt
, &expr1
, s
, fmt
,
4905 coproc
? treg
+ 1 : treg
,
4906 (int) BFD_RELOC_LO16
, AT
);
4908 expr1
.X_add_number
+= 4;
4910 /* Set mips_optimize to 2 to avoid inserting an undesired
4912 hold_mips_optimize
= mips_optimize
;
4914 macro_build (p
, &icnt
, &expr1
, s
, fmt
,
4915 coproc
? treg
: treg
+ 1,
4916 (int) BFD_RELOC_LO16
, AT
);
4917 mips_optimize
= hold_mips_optimize
;
4919 else if (mips_pic
== EMBEDDED_PIC
)
4921 /* If there is no base register, we use
4922 <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL)
4923 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_MIPS_GPREL)
4924 If we have a base register, we use
4926 <op> $treg,<sym>($at) (BFD_RELOC_MIPS_GPREL)
4927 <op> $treg+1,<sym>+4($at) (BFD_RELOC_MIPS_GPREL)
4936 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4937 mips_isa
< 3 ? "addu" : "daddu",
4938 "d,v,t", AT
, breg
, GP
);
4943 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
4944 coproc
? treg
+ 1 : treg
,
4945 (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
4946 offset_expr
.X_add_number
+= 4;
4947 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
4948 coproc
? treg
: treg
+ 1,
4949 (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
4965 assert (mips_isa
< 3);
4966 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
4967 (int) BFD_RELOC_LO16
, breg
);
4968 offset_expr
.X_add_number
+= 4;
4969 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
+ 1,
4970 (int) BFD_RELOC_LO16
, breg
);
4972 #ifdef LOSING_COMPILER
4978 as_warn ("Macro used $at after \".set noat\"");
4983 struct mips_cl_insn
*ip
;
4985 register int treg
, sreg
, dreg
, breg
;
5000 bfd_reloc_code_real_type r
;
5003 treg
= (ip
->insn_opcode
>> 16) & 0x1f;
5004 dreg
= (ip
->insn_opcode
>> 11) & 0x1f;
5005 sreg
= breg
= (ip
->insn_opcode
>> 21) & 0x1f;
5006 mask
= ip
->insn_mo
->mask
;
5008 expr1
.X_op
= O_constant
;
5009 expr1
.X_op_symbol
= NULL
;
5010 expr1
.X_add_symbol
= NULL
;
5011 expr1
.X_add_number
= 1;
5015 #endif /* LOSING_COMPILER */
5020 macro_build ((char *) NULL
, &icnt
, NULL
,
5021 dbl
? "dmultu" : "multu",
5023 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
5029 /* The MIPS assembler some times generates shifts and adds. I'm
5030 not trying to be that fancy. GCC should do this for us
5032 load_register (&icnt
, AT
, &imm_expr
, dbl
);
5033 macro_build ((char *) NULL
, &icnt
, NULL
,
5034 dbl
? "dmult" : "mult",
5036 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
5042 mips_emit_delays ();
5044 mips_any_noreorder
= 1;
5045 macro_build ((char *) NULL
, &icnt
, NULL
,
5046 dbl
? "dmult" : "mult",
5048 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
5049 macro_build ((char *) NULL
, &icnt
, NULL
,
5050 dbl
? "dsra32" : "sra",
5051 "d,w,<", dreg
, dreg
, 31);
5052 macro_build ((char *) NULL
, &icnt
, NULL
, "mfhi", "d", AT
);
5054 macro_build ((char *) NULL
, &icnt
, NULL
, "tne", "s,t", dreg
, AT
);
5057 expr1
.X_add_number
= 8;
5058 macro_build ((char *) NULL
, &icnt
, &expr1
, "beq", "s,t,p", dreg
, AT
);
5059 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
5060 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 6);
5063 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
5069 mips_emit_delays ();
5071 mips_any_noreorder
= 1;
5072 macro_build ((char *) NULL
, &icnt
, NULL
,
5073 dbl
? "dmultu" : "multu",
5075 macro_build ((char *) NULL
, &icnt
, NULL
, "mfhi", "d", AT
);
5076 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
5078 macro_build ((char *) NULL
, &icnt
, NULL
, "tne", "s,t", AT
, 0);
5081 expr1
.X_add_number
= 8;
5082 macro_build ((char *) NULL
, &icnt
, &expr1
, "beq", "s,t,p", AT
, 0);
5083 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
5084 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 6);
5090 macro_build ((char *) NULL
, &icnt
, NULL
, "subu", "d,v,t", AT
, 0, treg
);
5091 macro_build ((char *) NULL
, &icnt
, NULL
, "srlv", "d,t,s", AT
, sreg
, AT
);
5092 macro_build ((char *) NULL
, &icnt
, NULL
, "sllv", "d,t,s", dreg
, sreg
,
5094 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
5098 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", AT
, sreg
,
5099 (int) (imm_expr
.X_add_number
& 0x1f));
5100 macro_build ((char *) NULL
, &icnt
, NULL
, "srl", "d,w,<", dreg
, sreg
,
5101 (int) ((0 - imm_expr
.X_add_number
) & 0x1f));
5102 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
5106 macro_build ((char *) NULL
, &icnt
, NULL
, "subu", "d,v,t", AT
, 0, treg
);
5107 macro_build ((char *) NULL
, &icnt
, NULL
, "sllv", "d,t,s", AT
, sreg
, AT
);
5108 macro_build ((char *) NULL
, &icnt
, NULL
, "srlv", "d,t,s", dreg
, sreg
,
5110 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
5114 macro_build ((char *) NULL
, &icnt
, NULL
, "srl", "d,w,<", AT
, sreg
,
5115 (int) (imm_expr
.X_add_number
& 0x1f));
5116 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", dreg
, sreg
,
5117 (int) ((0 - imm_expr
.X_add_number
) & 0x1f));
5118 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
5122 assert (mips_isa
< 2);
5123 /* Even on a big endian machine $fn comes before $fn+1. We have
5124 to adjust when storing to memory. */
5125 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "swc1", "T,o(b)",
5126 byte_order
== LITTLE_ENDIAN
? treg
: treg
+ 1,
5127 (int) BFD_RELOC_LO16
, breg
);
5128 offset_expr
.X_add_number
+= 4;
5129 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "swc1", "T,o(b)",
5130 byte_order
== LITTLE_ENDIAN
? treg
+ 1 : treg
,
5131 (int) BFD_RELOC_LO16
, breg
);
5136 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
5137 treg
, (int) BFD_RELOC_LO16
);
5139 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
5140 sreg
, (int) BFD_RELOC_LO16
);
5143 macro_build ((char *) NULL
, &icnt
, NULL
, "xor", "d,v,t", dreg
,
5145 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
5146 dreg
, (int) BFD_RELOC_LO16
);
5151 if (imm_expr
.X_add_number
== 0)
5153 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
5154 sreg
, (int) BFD_RELOC_LO16
);
5159 as_warn ("Instruction %s: result is always false",
5161 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
, 0);
5164 if (imm_expr
.X_add_number
>= 0 && imm_expr
.X_add_number
< 0x10000)
5166 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "xori", "t,r,i", dreg
,
5167 sreg
, (int) BFD_RELOC_LO16
);
5170 else if (imm_expr
.X_add_number
> -0x8000 && imm_expr
.X_add_number
< 0)
5172 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
5173 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
5174 mips_isa
< 3 ? "addiu" : "daddiu",
5175 "t,r,j", dreg
, sreg
,
5176 (int) BFD_RELOC_LO16
);
5181 load_register (&icnt
, AT
, &imm_expr
, 0);
5182 macro_build ((char *) NULL
, &icnt
, NULL
, "xor", "d,v,t", dreg
,
5186 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
, dreg
,
5187 (int) BFD_RELOC_LO16
);
5192 case M_SGE
: /* sreg >= treg <==> not (sreg < treg) */
5198 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, sreg
, treg
);
5199 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
5200 (int) BFD_RELOC_LO16
);
5203 case M_SGE_I
: /* sreg >= I <==> not (sreg < I) */
5205 if (imm_expr
.X_add_number
>= -0x8000 && imm_expr
.X_add_number
< 0x8000)
5207 macro_build ((char *) NULL
, &icnt
, &expr1
,
5208 mask
== M_SGE_I
? "slti" : "sltiu",
5209 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
5214 load_register (&icnt
, AT
, &imm_expr
, 0);
5215 macro_build ((char *) NULL
, &icnt
, NULL
,
5216 mask
== M_SGE_I
? "slt" : "sltu",
5217 "d,v,t", dreg
, sreg
, AT
);
5220 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
5221 (int) BFD_RELOC_LO16
);
5226 case M_SGT
: /* sreg > treg <==> treg < sreg */
5232 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, treg
, sreg
);
5235 case M_SGT_I
: /* sreg > I <==> I < sreg */
5241 load_register (&icnt
, AT
, &imm_expr
, 0);
5242 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, AT
, sreg
);
5245 case M_SLE
: /* sreg <= treg <==> treg >= sreg <==> not (treg < sreg) */
5251 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, treg
, sreg
);
5252 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
5253 (int) BFD_RELOC_LO16
);
5256 case M_SLE_I
: /* sreg <= I <==> I >= sreg <==> not (I < sreg) */
5262 load_register (&icnt
, AT
, &imm_expr
, 0);
5263 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, AT
, sreg
);
5264 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
5265 (int) BFD_RELOC_LO16
);
5269 if (imm_expr
.X_add_number
>= -0x8000 && imm_expr
.X_add_number
< 0x8000)
5271 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "slti", "t,r,j",
5272 dreg
, sreg
, (int) BFD_RELOC_LO16
);
5275 load_register (&icnt
, AT
, &imm_expr
, 0);
5276 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", dreg
, sreg
, AT
);
5280 if (imm_expr
.X_add_number
>= -0x8000 && imm_expr
.X_add_number
< 0x8000)
5282 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "sltiu", "t,r,j",
5283 dreg
, sreg
, (int) BFD_RELOC_LO16
);
5286 load_register (&icnt
, AT
, &imm_expr
, 0);
5287 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, sreg
,
5293 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0,
5296 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0,
5300 macro_build ((char *) NULL
, &icnt
, NULL
, "xor", "d,v,t", dreg
,
5302 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0,
5308 if (imm_expr
.X_add_number
== 0)
5310 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0,
5316 as_warn ("Instruction %s: result is always true",
5318 macro_build ((char *) NULL
, &icnt
, &expr1
,
5319 mips_isa
< 3 ? "addiu" : "daddiu",
5320 "t,r,j", dreg
, 0, (int) BFD_RELOC_LO16
);
5323 if (imm_expr
.X_add_number
>= 0 && imm_expr
.X_add_number
< 0x10000)
5325 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "xori", "t,r,i",
5326 dreg
, sreg
, (int) BFD_RELOC_LO16
);
5329 else if (imm_expr
.X_add_number
> -0x8000 && imm_expr
.X_add_number
< 0)
5331 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
5332 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
5333 mips_isa
< 3 ? "addiu" : "daddiu",
5334 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
5339 load_register (&icnt
, AT
, &imm_expr
, 0);
5340 macro_build ((char *) NULL
, &icnt
, NULL
, "xor", "d,v,t", dreg
,
5344 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0, dreg
);
5352 if (imm_expr
.X_add_number
> -0x8000 && imm_expr
.X_add_number
<= 0x8000)
5354 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
5355 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
5356 dbl
? "daddi" : "addi",
5357 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
5360 load_register (&icnt
, AT
, &imm_expr
, dbl
);
5361 macro_build ((char *) NULL
, &icnt
, NULL
,
5362 dbl
? "dsub" : "sub",
5363 "d,v,t", dreg
, sreg
, AT
);
5369 if (imm_expr
.X_add_number
> -0x8000 && imm_expr
.X_add_number
<= 0x8000)
5371 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
5372 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
5373 dbl
? "daddiu" : "addiu",
5374 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
5377 load_register (&icnt
, AT
, &imm_expr
, dbl
);
5378 macro_build ((char *) NULL
, &icnt
, NULL
,
5379 dbl
? "dsubu" : "subu",
5380 "d,v,t", dreg
, sreg
, AT
);
5401 load_register (&icnt
, AT
, &imm_expr
, 0);
5402 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "s,t", sreg
, AT
);
5407 assert (mips_isa
< 2);
5408 sreg
= (ip
->insn_opcode
>> 11) & 0x1f; /* floating reg */
5409 dreg
= (ip
->insn_opcode
>> 06) & 0x1f; /* floating reg */
5412 * Is the double cfc1 instruction a bug in the mips assembler;
5413 * or is there a reason for it?
5415 mips_emit_delays ();
5417 mips_any_noreorder
= 1;
5418 macro_build ((char *) NULL
, &icnt
, NULL
, "cfc1", "t,G", treg
, 31);
5419 macro_build ((char *) NULL
, &icnt
, NULL
, "cfc1", "t,G", treg
, 31);
5420 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "");
5421 expr1
.X_add_number
= 3;
5422 macro_build ((char *) NULL
, &icnt
, &expr1
, "ori", "t,r,i", AT
, treg
,
5423 (int) BFD_RELOC_LO16
);
5424 expr1
.X_add_number
= 2;
5425 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", AT
, AT
,
5426 (int) BFD_RELOC_LO16
);
5427 macro_build ((char *) NULL
, &icnt
, NULL
, "ctc1", "t,G", AT
, 31);
5428 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "");
5429 macro_build ((char *) NULL
, &icnt
, NULL
,
5430 mask
== M_TRUNCWD
? "cvt.w.d" : "cvt.w.s", "D,S", dreg
, sreg
);
5431 macro_build ((char *) NULL
, &icnt
, NULL
, "ctc1", "t,G", treg
, 31);
5432 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "");
5442 if (offset_expr
.X_add_number
>= 0x7fff)
5443 as_bad ("operand overflow");
5444 /* avoid load delay */
5445 if (byte_order
== LITTLE_ENDIAN
)
5446 offset_expr
.X_add_number
+= 1;
5447 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
5448 (int) BFD_RELOC_LO16
, breg
);
5449 if (byte_order
== LITTLE_ENDIAN
)
5450 offset_expr
.X_add_number
-= 1;
5452 offset_expr
.X_add_number
+= 1;
5453 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lbu", "t,o(b)", AT
,
5454 (int) BFD_RELOC_LO16
, breg
);
5455 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", treg
, treg
, 8);
5456 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", treg
, treg
, AT
);
5469 if (offset_expr
.X_add_number
>= 0x8000 - off
)
5470 as_bad ("operand overflow");
5471 if (byte_order
== LITTLE_ENDIAN
)
5472 offset_expr
.X_add_number
+= off
;
5473 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
5474 (int) BFD_RELOC_LO16
, breg
);
5475 if (byte_order
== LITTLE_ENDIAN
)
5476 offset_expr
.X_add_number
-= off
;
5478 offset_expr
.X_add_number
+= off
;
5479 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s2
, "t,o(b)", treg
,
5480 (int) BFD_RELOC_LO16
, breg
);
5493 load_address (&icnt
, AT
, &offset_expr
);
5495 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5496 mips_isa
< 3 ? "addu" : "daddu",
5497 "d,v,t", AT
, AT
, breg
);
5498 if (byte_order
== LITTLE_ENDIAN
)
5499 expr1
.X_add_number
= off
;
5501 expr1
.X_add_number
= 0;
5502 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, "t,o(b)", treg
,
5503 (int) BFD_RELOC_LO16
, AT
);
5504 if (byte_order
== LITTLE_ENDIAN
)
5505 expr1
.X_add_number
= 0;
5507 expr1
.X_add_number
= off
;
5508 macro_build ((char *) NULL
, &icnt
, &expr1
, s2
, "t,o(b)", treg
,
5509 (int) BFD_RELOC_LO16
, AT
);
5514 load_address (&icnt
, AT
, &offset_expr
);
5516 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5517 mips_isa
< 3 ? "addu" : "daddu",
5518 "d,v,t", AT
, AT
, breg
);
5519 if (byte_order
== BIG_ENDIAN
)
5520 expr1
.X_add_number
= 0;
5521 macro_build ((char *) NULL
, &icnt
, &expr1
,
5522 mask
== M_ULH_A
? "lb" : "lbu", "t,o(b)", treg
,
5523 (int) BFD_RELOC_LO16
, AT
);
5524 if (byte_order
== BIG_ENDIAN
)
5525 expr1
.X_add_number
= 1;
5527 expr1
.X_add_number
= 0;
5528 macro_build ((char *) NULL
, &icnt
, &expr1
, "lbu", "t,o(b)", AT
,
5529 (int) BFD_RELOC_LO16
, AT
);
5530 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", treg
,
5532 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", treg
,
5537 if (offset_expr
.X_add_number
>= 0x7fff)
5538 as_bad ("operand overflow");
5539 if (byte_order
== BIG_ENDIAN
)
5540 offset_expr
.X_add_number
+= 1;
5541 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "sb", "t,o(b)", treg
,
5542 (int) BFD_RELOC_LO16
, breg
);
5543 macro_build ((char *) NULL
, &icnt
, NULL
, "srl", "d,w,<", AT
, treg
, 8);
5544 if (byte_order
== BIG_ENDIAN
)
5545 offset_expr
.X_add_number
-= 1;
5547 offset_expr
.X_add_number
+= 1;
5548 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "sb", "t,o(b)", AT
,
5549 (int) BFD_RELOC_LO16
, breg
);
5562 if (offset_expr
.X_add_number
>= 0x8000 - off
)
5563 as_bad ("operand overflow");
5564 if (byte_order
== LITTLE_ENDIAN
)
5565 offset_expr
.X_add_number
+= off
;
5566 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
5567 (int) BFD_RELOC_LO16
, breg
);
5568 if (byte_order
== LITTLE_ENDIAN
)
5569 offset_expr
.X_add_number
-= off
;
5571 offset_expr
.X_add_number
+= off
;
5572 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s2
, "t,o(b)", treg
,
5573 (int) BFD_RELOC_LO16
, breg
);
5586 load_address (&icnt
, AT
, &offset_expr
);
5588 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5589 mips_isa
< 3 ? "addu" : "daddu",
5590 "d,v,t", AT
, AT
, breg
);
5591 if (byte_order
== LITTLE_ENDIAN
)
5592 expr1
.X_add_number
= off
;
5594 expr1
.X_add_number
= 0;
5595 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, "t,o(b)", treg
,
5596 (int) BFD_RELOC_LO16
, AT
);
5597 if (byte_order
== LITTLE_ENDIAN
)
5598 expr1
.X_add_number
= 0;
5600 expr1
.X_add_number
= off
;
5601 macro_build ((char *) NULL
, &icnt
, &expr1
, s2
, "t,o(b)", treg
,
5602 (int) BFD_RELOC_LO16
, AT
);
5606 load_address (&icnt
, AT
, &offset_expr
);
5608 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5609 mips_isa
< 3 ? "addu" : "daddu",
5610 "d,v,t", AT
, AT
, breg
);
5611 if (byte_order
== LITTLE_ENDIAN
)
5612 expr1
.X_add_number
= 0;
5613 macro_build ((char *) NULL
, &icnt
, &expr1
, "sb", "t,o(b)", treg
,
5614 (int) BFD_RELOC_LO16
, AT
);
5615 macro_build ((char *) NULL
, &icnt
, NULL
, "srl", "d,w,<", treg
,
5617 if (byte_order
== LITTLE_ENDIAN
)
5618 expr1
.X_add_number
= 1;
5620 expr1
.X_add_number
= 0;
5621 macro_build ((char *) NULL
, &icnt
, &expr1
, "sb", "t,o(b)", treg
,
5622 (int) BFD_RELOC_LO16
, AT
);
5623 if (byte_order
== LITTLE_ENDIAN
)
5624 expr1
.X_add_number
= 0;
5626 expr1
.X_add_number
= 1;
5627 macro_build ((char *) NULL
, &icnt
, &expr1
, "lbu", "t,o(b)", AT
,
5628 (int) BFD_RELOC_LO16
, AT
);
5629 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", treg
,
5631 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", treg
,
5636 as_bad ("Macro %s not implemented yet", ip
->insn_mo
->name
);
5640 as_warn ("Macro used $at after \".set noat\"");
5643 /* Implement macros in mips16 mode. */
5647 struct mips_cl_insn
*ip
;
5650 int xreg
, yreg
, zreg
, tmp
;
5654 const char *s
, *s2
, *s3
;
5656 mask
= ip
->insn_mo
->mask
;
5658 xreg
= (ip
->insn_opcode
>> MIPS16OP_SH_RX
) & MIPS16OP_MASK_RX
;
5659 yreg
= (ip
->insn_opcode
>> MIPS16OP_SH_RY
) & MIPS16OP_MASK_RY
;
5660 zreg
= (ip
->insn_opcode
>> MIPS16OP_SH_RZ
) & MIPS16OP_MASK_RZ
;
5664 expr1
.X_op
= O_constant
;
5665 expr1
.X_op_symbol
= NULL
;
5666 expr1
.X_add_symbol
= NULL
;
5667 expr1
.X_add_number
= 1;
5686 mips_emit_delays ();
5688 mips_any_noreorder
= 1;
5689 macro_build ((char *) NULL
, &icnt
, NULL
,
5690 dbl
? "ddiv" : "div",
5691 "0,x,y", xreg
, yreg
);
5692 expr1
.X_add_number
= 4;
5693 macro_build ((char *) NULL
, &icnt
, &expr1
, "bnez", "x,p", yreg
);
5694 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "");
5695 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "6", 7);
5696 /* FIXME: The normal code checks for of -1 / -0x80000000 here,
5697 since that causes an overflow. We should do that as well,
5698 but I don't see how to do the comparisons without a temporary
5701 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "x", zreg
);
5720 mips_emit_delays ();
5722 mips_any_noreorder
= 1;
5723 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "0,x,y", xreg
, yreg
);
5724 expr1
.X_add_number
= 4;
5725 macro_build ((char *) NULL
, &icnt
, &expr1
, "bnez", "x,p", yreg
);
5726 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
5727 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "6", 7);
5729 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "x", zreg
);
5737 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
5738 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
5739 dbl
? "daddiu" : "addiu",
5740 "y,x,4", yreg
, xreg
);
5744 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
5745 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "addiu",
5750 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
5751 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "daddiu",
5774 goto do_reverse_branch
;
5778 goto do_reverse_branch
;
5790 goto do_reverse_branch
;
5801 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s
, "x,y",
5803 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s2
, "p");
5830 goto do_addone_branch_i
;
5835 goto do_addone_branch_i
;
5850 goto do_addone_branch_i
;
5857 ++imm_expr
.X_add_number
;
5860 macro_build ((char *) NULL
, &icnt
, &imm_expr
, s
, s3
, xreg
);
5861 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s2
, "p");
5866 /* This routine assembles an instruction into its binary format. As a
5867 side effect, it sets one of the global variables imm_reloc or
5868 offset_reloc to the type of relocation to do if one of the operands
5869 is an address expression. */
5874 struct mips_cl_insn
*ip
;
5879 struct mips_opcode
*insn
;
5882 unsigned int lastregno
= 0;
5887 for (s
= str
; islower (*s
) || (*s
>= '0' && *s
<= '3') || *s
== '6' || *s
== '.'; ++s
)
5899 as_fatal ("Unknown opcode: `%s'", str
);
5901 if ((insn
= (struct mips_opcode
*) hash_find (op_hash
, str
)) == NULL
)
5903 insn_error
= "unrecognized opcode";
5911 assert (strcmp (insn
->name
, str
) == 0);
5913 if (insn
->pinfo
== INSN_MACRO
)
5914 insn_isa
= insn
->match
;
5915 else if ((insn
->pinfo
& INSN_ISA
) == INSN_ISA2
)
5917 else if ((insn
->pinfo
& INSN_ISA
) == INSN_ISA3
)
5919 else if ((insn
->pinfo
& INSN_ISA
) == INSN_ISA4
)
5924 if (insn_isa
> mips_isa
5925 || ((insn
->pinfo
& INSN_ISA
) == INSN_4650
5927 || ((insn
->pinfo
& INSN_ISA
) == INSN_4010
5929 || ((insn
->pinfo
& INSN_ISA
) == INSN_4100
5932 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
]
5933 && strcmp (insn
->name
, insn
[1].name
) == 0)
5938 if (insn_isa
<= mips_isa
)
5939 insn_error
= "opcode not supported on this processor";
5942 static char buf
[100];
5944 sprintf (buf
, "opcode requires -mips%d or greater", insn_isa
);
5951 ip
->insn_opcode
= insn
->match
;
5952 for (args
= insn
->args
;; ++args
)
5958 case '\0': /* end of args */
5971 ip
->insn_opcode
|= lastregno
<< 21;
5976 ip
->insn_opcode
|= lastregno
<< 16;
5980 ip
->insn_opcode
|= lastregno
<< 11;
5986 /* handle optional base register.
5987 Either the base register is omitted or
5988 we must have a left paren. */
5989 /* this is dependent on the next operand specifier
5990 is a 'b' for base register */
5991 assert (args
[1] == 'b');
5995 case ')': /* these must match exactly */
6000 case '<': /* must be at least one digit */
6002 * According to the manual, if the shift amount is greater
6003 * than 31 or less than 0 the the shift amount should be
6004 * mod 32. In reality the mips assembler issues an error.
6005 * We issue a warning and mask out all but the low 5 bits.
6007 my_getExpression (&imm_expr
, s
);
6008 check_absolute_expr (ip
, &imm_expr
);
6009 if ((unsigned long) imm_expr
.X_add_number
> 31)
6011 as_warn ("Improper shift amount (%ld)",
6012 (long) imm_expr
.X_add_number
);
6013 imm_expr
.X_add_number
= imm_expr
.X_add_number
& 0x1f;
6015 ip
->insn_opcode
|= imm_expr
.X_add_number
<< 6;
6016 imm_expr
.X_op
= O_absent
;
6020 case '>': /* shift amount minus 32 */
6021 my_getExpression (&imm_expr
, s
);
6022 check_absolute_expr (ip
, &imm_expr
);
6023 if ((unsigned long) imm_expr
.X_add_number
< 32
6024 || (unsigned long) imm_expr
.X_add_number
> 63)
6026 ip
->insn_opcode
|= (imm_expr
.X_add_number
- 32) << 6;
6027 imm_expr
.X_op
= O_absent
;
6031 case 'k': /* cache code */
6032 case 'h': /* prefx code */
6033 my_getExpression (&imm_expr
, s
);
6034 check_absolute_expr (ip
, &imm_expr
);
6035 if ((unsigned long) imm_expr
.X_add_number
> 31)
6037 as_warn ("Invalid value for `%s' (%lu)",
6039 (unsigned long) imm_expr
.X_add_number
);
6040 imm_expr
.X_add_number
&= 0x1f;
6043 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_CACHE
;
6045 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_PREFX
;
6046 imm_expr
.X_op
= O_absent
;
6050 case 'c': /* break code */
6051 my_getExpression (&imm_expr
, s
);
6052 check_absolute_expr (ip
, &imm_expr
);
6053 if ((unsigned) imm_expr
.X_add_number
> 1023)
6054 as_warn ("Illegal break code (%ld)",
6055 (long) imm_expr
.X_add_number
);
6056 ip
->insn_opcode
|= imm_expr
.X_add_number
<< 16;
6057 imm_expr
.X_op
= O_absent
;
6061 case 'B': /* syscall code */
6062 my_getExpression (&imm_expr
, s
);
6063 check_absolute_expr (ip
, &imm_expr
);
6064 if ((unsigned) imm_expr
.X_add_number
> 0xfffff)
6065 as_warn ("Illegal syscall code (%ld)",
6066 (long) imm_expr
.X_add_number
);
6067 ip
->insn_opcode
|= imm_expr
.X_add_number
<< 6;
6068 imm_expr
.X_op
= O_absent
;
6072 case 'C': /* Coprocessor code */
6073 my_getExpression (&imm_expr
, s
);
6074 check_absolute_expr (ip
, &imm_expr
);
6075 if ((unsigned long) imm_expr
.X_add_number
>= (1<<25))
6077 as_warn ("Coproccesor code > 25 bits (%ld)",
6078 (long) imm_expr
.X_add_number
);
6079 imm_expr
.X_add_number
&= ((1<<25) - 1);
6081 ip
->insn_opcode
|= imm_expr
.X_add_number
;
6082 imm_expr
.X_op
= O_absent
;
6086 case 'b': /* base register */
6087 case 'd': /* destination register */
6088 case 's': /* source register */
6089 case 't': /* target register */
6090 case 'r': /* both target and source */
6091 case 'v': /* both dest and source */
6092 case 'w': /* both dest and target */
6093 case 'E': /* coprocessor target register */
6094 case 'G': /* coprocessor destination register */
6095 case 'x': /* ignore register name */
6096 case 'z': /* must be zero register */
6110 while (isdigit (*s
));
6112 as_bad ("Invalid register number (%d)", regno
);
6114 else if (*args
== 'E' || *args
== 'G')
6118 if (s
[1] == 'f' && s
[2] == 'p')
6123 else if (s
[1] == 's' && s
[2] == 'p')
6128 else if (s
[1] == 'g' && s
[2] == 'p')
6133 else if (s
[1] == 'a' && s
[2] == 't')
6138 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '0')
6143 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '1')
6155 as_warn ("Used $at without \".set noat\"");
6161 if (c
== 'r' || c
== 'v' || c
== 'w')
6168 /* 'z' only matches $0. */
6169 if (c
== 'z' && regno
!= 0)
6177 ip
->insn_opcode
|= regno
<< 21;
6181 ip
->insn_opcode
|= regno
<< 11;
6186 ip
->insn_opcode
|= regno
<< 16;
6189 /* This case exists because on the r3000 trunc
6190 expands into a macro which requires a gp
6191 register. On the r6000 or r4000 it is
6192 assembled into a single instruction which
6193 ignores the register. Thus the insn version
6194 is MIPS_ISA2 and uses 'x', and the macro
6195 version is MIPS_ISA1 and uses 't'. */
6198 /* This case is for the div instruction, which
6199 acts differently if the destination argument
6200 is $0. This only matches $0, and is checked
6201 outside the switch. */
6212 ip
->insn_opcode
|= lastregno
<< 21;
6215 ip
->insn_opcode
|= lastregno
<< 16;
6220 case 'D': /* floating point destination register */
6221 case 'S': /* floating point source register */
6222 case 'T': /* floating point target register */
6223 case 'R': /* floating point source register */
6227 if (s
[0] == '$' && s
[1] == 'f' && isdigit (s
[2]))
6237 while (isdigit (*s
));
6240 as_bad ("Invalid float register number (%d)", regno
);
6242 if ((regno
& 1) != 0
6244 && ! (strcmp (str
, "mtc1") == 0
6245 || strcmp (str
, "mfc1") == 0
6246 || strcmp (str
, "lwc1") == 0
6247 || strcmp (str
, "swc1") == 0
6248 || strcmp (str
, "l.s") == 0
6249 || strcmp (str
, "s.s") == 0))
6250 as_warn ("Float register should be even, was %d",
6258 if (c
== 'V' || c
== 'W')
6268 ip
->insn_opcode
|= regno
<< 6;
6272 ip
->insn_opcode
|= regno
<< 11;
6276 ip
->insn_opcode
|= regno
<< 16;
6279 ip
->insn_opcode
|= regno
<< 21;
6288 ip
->insn_opcode
|= lastregno
<< 11;
6291 ip
->insn_opcode
|= lastregno
<< 16;
6297 my_getExpression (&imm_expr
, s
);
6298 if (imm_expr
.X_op
!= O_big
6299 && imm_expr
.X_op
!= O_constant
)
6300 insn_error
= "absolute expression required";
6305 my_getExpression (&offset_expr
, s
);
6306 imm_reloc
= BFD_RELOC_32
;
6318 unsigned char temp
[8];
6320 unsigned int length
;
6325 /* These only appear as the last operand in an
6326 instruction, and every instruction that accepts
6327 them in any variant accepts them in all variants.
6328 This means we don't have to worry about backing out
6329 any changes if the instruction does not match.
6331 The difference between them is the size of the
6332 floating point constant and where it goes. For 'F'
6333 and 'L' the constant is 64 bits; for 'f' and 'l' it
6334 is 32 bits. Where the constant is placed is based
6335 on how the MIPS assembler does things:
6338 f -- immediate value
6341 The .lit4 and .lit8 sections are only used if
6342 permitted by the -G argument.
6344 When generating embedded PIC code, we use the
6345 .lit8 section but not the .lit4 section (we can do
6346 .lit4 inline easily; we need to put .lit8
6347 somewhere in the data segment, and using .lit8
6348 permits the linker to eventually combine identical
6351 f64
= *args
== 'F' || *args
== 'L';
6353 save_in
= input_line_pointer
;
6354 input_line_pointer
= s
;
6355 err
= md_atof (f64
? 'd' : 'f', (char *) temp
, &len
);
6357 s
= input_line_pointer
;
6358 input_line_pointer
= save_in
;
6359 if (err
!= NULL
&& *err
!= '\0')
6361 as_bad ("Bad floating point constant: %s", err
);
6362 memset (temp
, '\0', sizeof temp
);
6363 length
= f64
? 8 : 4;
6366 assert (length
== (f64
? 8 : 4));
6370 && (! USE_GLOBAL_POINTER_OPT
6371 || mips_pic
== EMBEDDED_PIC
6372 || g_switch_value
< 4)
6375 imm_expr
.X_op
= O_constant
;
6376 if (byte_order
== LITTLE_ENDIAN
)
6377 imm_expr
.X_add_number
=
6378 (((((((int) temp
[3] << 8)
6383 imm_expr
.X_add_number
=
6384 (((((((int) temp
[0] << 8)
6391 const char *newname
;
6394 /* Switch to the right section. */
6396 subseg
= now_subseg
;
6399 default: /* unused default case avoids warnings. */
6401 newname
= RDATA_SECTION_NAME
;
6402 if (USE_GLOBAL_POINTER_OPT
&& g_switch_value
>= 8)
6406 newname
= RDATA_SECTION_NAME
;
6409 assert (!USE_GLOBAL_POINTER_OPT
6410 || g_switch_value
>= 4);
6414 new_seg
= subseg_new (newname
, (subsegT
) 0);
6415 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
6416 bfd_set_section_flags (stdoutput
, new_seg
,
6421 frag_align (*args
== 'l' ? 2 : 3, 0);
6422 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
6423 record_alignment (new_seg
, 4);
6425 record_alignment (new_seg
, *args
== 'l' ? 2 : 3);
6427 as_bad ("Can't use floating point insn in this section");
6429 /* Set the argument to the current address in the
6431 offset_expr
.X_op
= O_symbol
;
6432 offset_expr
.X_add_symbol
=
6433 symbol_new ("L0\001", now_seg
,
6434 (valueT
) frag_now_fix (), frag_now
);
6435 offset_expr
.X_add_number
= 0;
6437 /* Put the floating point number into the section. */
6438 p
= frag_more ((int) length
);
6439 memcpy (p
, temp
, length
);
6441 /* Switch back to the original section. */
6442 subseg_set (seg
, subseg
);
6447 case 'i': /* 16 bit unsigned immediate */
6448 case 'j': /* 16 bit signed immediate */
6449 imm_reloc
= BFD_RELOC_LO16
;
6450 c
= my_getSmallExpression (&imm_expr
, s
);
6455 if (imm_expr
.X_op
== O_constant
)
6456 imm_expr
.X_add_number
=
6457 (imm_expr
.X_add_number
>> 16) & 0xffff;
6460 imm_reloc
= BFD_RELOC_HI16_S
;
6461 imm_unmatched_hi
= true;
6464 imm_reloc
= BFD_RELOC_HI16
;
6469 if ((c
== '\0' && imm_expr
.X_op
!= O_constant
)
6470 || ((imm_expr
.X_add_number
< 0
6471 || imm_expr
.X_add_number
>= 0x10000)
6472 && imm_expr
.X_op
== O_constant
))
6474 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
6475 !strcmp (insn
->name
, insn
[1].name
))
6477 if (imm_expr
.X_op
!= O_constant
6478 && imm_expr
.X_op
!= O_big
)
6479 insn_error
= "absolute expression required";
6481 as_bad ("16 bit expression not in range 0..65535");
6489 /* The upper bound should be 0x8000, but
6490 unfortunately the MIPS assembler accepts numbers
6491 from 0x8000 to 0xffff and sign extends them, and
6492 we want to be compatible. We only permit this
6493 extended range for an instruction which does not
6494 provide any further alternates, since those
6495 alternates may handle other cases. People should
6496 use the numbers they mean, rather than relying on
6497 a mysterious sign extension. */
6498 more
= (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
6499 strcmp (insn
->name
, insn
[1].name
) == 0);
6504 if ((c
== '\0' && imm_expr
.X_op
!= O_constant
)
6505 || ((imm_expr
.X_add_number
< -0x8000
6506 || imm_expr
.X_add_number
>= max
)
6507 && imm_expr
.X_op
== O_constant
)
6509 && imm_expr
.X_add_number
< 0
6511 && imm_expr
.X_unsigned
6512 && sizeof (imm_expr
.X_add_number
) <= 4))
6516 if (imm_expr
.X_op
!= O_constant
6517 && imm_expr
.X_op
!= O_big
)
6518 insn_error
= "absolute expression required";
6520 as_bad ("16 bit expression not in range -32768..32767");
6526 case 'o': /* 16 bit offset */
6527 c
= my_getSmallExpression (&offset_expr
, s
);
6529 /* If this value won't fit into a 16 bit offset, then go
6530 find a macro that will generate the 32 bit offset
6531 code pattern. As a special hack, we accept the
6532 difference of two local symbols as a constant. This
6533 is required to suppose embedded PIC switches, which
6534 use an instruction which looks like
6535 lw $4,$L12-$LS12($4)
6536 The problem with handling this in a more general
6537 fashion is that the macro function doesn't expect to
6538 see anything which can be handled in a single
6539 constant instruction. */
6541 && (offset_expr
.X_op
!= O_constant
6542 || offset_expr
.X_add_number
>= 0x8000
6543 || offset_expr
.X_add_number
< -0x8000)
6544 && (mips_pic
!= EMBEDDED_PIC
6545 || offset_expr
.X_op
!= O_subtract
6546 || now_seg
!= text_section
6547 || (S_GET_SEGMENT (offset_expr
.X_op_symbol
)
6551 offset_reloc
= BFD_RELOC_LO16
;
6552 if (c
== 'h' || c
== 'H')
6554 assert (offset_expr
.X_op
== O_constant
);
6555 offset_expr
.X_add_number
=
6556 (offset_expr
.X_add_number
>> 16) & 0xffff;
6561 case 'p': /* pc relative offset */
6562 offset_reloc
= BFD_RELOC_16_PCREL_S2
;
6563 my_getExpression (&offset_expr
, s
);
6567 case 'u': /* upper 16 bits */
6568 c
= my_getSmallExpression (&imm_expr
, s
);
6569 if (imm_expr
.X_op
== O_constant
6570 && (imm_expr
.X_add_number
< 0
6571 || imm_expr
.X_add_number
>= 0x10000))
6572 as_bad ("lui expression not in range 0..65535");
6573 imm_reloc
= BFD_RELOC_LO16
;
6578 if (imm_expr
.X_op
== O_constant
)
6579 imm_expr
.X_add_number
=
6580 (imm_expr
.X_add_number
>> 16) & 0xffff;
6583 imm_reloc
= BFD_RELOC_HI16_S
;
6584 imm_unmatched_hi
= true;
6587 imm_reloc
= BFD_RELOC_HI16
;
6593 case 'a': /* 26 bit address */
6594 my_getExpression (&offset_expr
, s
);
6596 offset_reloc
= BFD_RELOC_MIPS_JMP
;
6599 case 'N': /* 3 bit branch condition code */
6600 case 'M': /* 3 bit compare condition code */
6601 if (strncmp (s
, "$fcc", 4) != 0)
6611 while (isdigit (*s
));
6613 as_bad ("invalid condition code register $fcc%d", regno
);
6615 ip
->insn_opcode
|= regno
<< OP_SH_BCC
;
6617 ip
->insn_opcode
|= regno
<< OP_SH_CCC
;
6621 fprintf (stderr
, "bad char = '%c'\n", *args
);
6626 /* Args don't match. */
6627 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
6628 !strcmp (insn
->name
, insn
[1].name
))
6634 insn_error
= "illegal operands";
6639 /* This routine assembles an instruction into its binary format when
6640 assembling for the mips16. As a side effect, it sets one of the
6641 global variables imm_reloc or offset_reloc to the type of
6642 relocation to do if one of the operands is an address expression.
6643 It also sets mips16_small and mips16_ext if the user explicitly
6644 requested a small or extended instruction. */
6649 struct mips_cl_insn
*ip
;
6653 struct mips_opcode
*insn
;
6656 unsigned int lastregno
= 0;
6661 mips16_small
= false;
6664 for (s
= str
; islower (*s
); ++s
)
6676 if (s
[1] == 't' && s
[2] == ' ')
6679 mips16_small
= true;
6683 else if (s
[1] == 'e' && s
[2] == ' ')
6692 insn_error
= "unknown opcode";
6696 if (! mips16_autoextend
&& ! mips16_ext
)
6697 mips16_small
= true;
6699 if ((insn
= (struct mips_opcode
*) hash_find (mips16_op_hash
, str
)) == NULL
)
6701 insn_error
= "unrecognized opcode";
6708 assert (strcmp (insn
->name
, str
) == 0);
6711 ip
->insn_opcode
= insn
->match
;
6712 ip
->use_extend
= false;
6713 imm_expr
.X_op
= O_absent
;
6714 imm_reloc
= BFD_RELOC_UNUSED
;
6715 offset_expr
.X_op
= O_absent
;
6716 offset_reloc
= BFD_RELOC_UNUSED
;
6717 for (args
= insn
->args
; 1; ++args
)
6724 /* In this switch statement we call break if we did not find
6725 a match, continue if we did find a match, or return if we
6734 /* Stuff the immediate value in now, if we can. */
6735 if (imm_expr
.X_op
== O_constant
6736 && imm_reloc
> BFD_RELOC_UNUSED
6737 && insn
->pinfo
!= INSN_MACRO
)
6739 mips16_immed ((char *) NULL
, 0,
6740 imm_reloc
- BFD_RELOC_UNUSED
,
6741 imm_expr
.X_add_number
, true, mips16_small
,
6742 mips16_ext
, &ip
->insn_opcode
,
6743 &ip
->use_extend
, &ip
->extend
);
6744 imm_expr
.X_op
= O_absent
;
6745 imm_reloc
= BFD_RELOC_UNUSED
;
6759 ip
->insn_opcode
|= lastregno
<< MIPS16OP_SH_RX
;
6762 ip
->insn_opcode
|= lastregno
<< MIPS16OP_SH_RY
;
6778 ip
->insn_opcode
|= lastregno
<< MIPS16OP_SH_RX
;
6780 ip
->insn_opcode
|= lastregno
<< MIPS16OP_SH_RY
;
6807 while (isdigit (*s
));
6810 as_bad ("invalid register number (%d)", regno
);
6816 if (s
[1] == 'f' && s
[2] == 'p')
6821 else if (s
[1] == 's' && s
[2] == 'p')
6826 else if (s
[1] == 'g' && s
[2] == 'p')
6831 else if (s
[1] == 'a' && s
[2] == 't')
6836 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '0')
6841 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '1')
6854 if (c
== 'v' || c
== 'w')
6856 regno
= mips16_to_32_reg_map
[lastregno
];
6870 regno
= mips32_to_16_reg_map
[regno
];
6875 regno
= ILLEGAL_REG
;
6880 regno
= ILLEGAL_REG
;
6885 regno
= ILLEGAL_REG
;
6890 if (regno
== AT
&& ! mips_noat
)
6891 as_warn ("used $at without \".set noat\"");
6898 if (regno
== ILLEGAL_REG
)
6905 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_RX
;
6909 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_RY
;
6912 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_RZ
;
6915 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_MOVE32Z
;
6921 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_REGR32
;
6924 regno
= ((regno
& 7) << 2) | ((regno
& 0x18) >> 3);
6925 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_REG32R
;
6935 if (strncmp (s
, "$pc", 3) == 0)
6958 if (s
[0] == '$' && isdigit (s
[1]))
6960 /* Looks like a register name. */
6963 my_getExpression (&imm_expr
, s
);
6964 /* We need to relax this instruction. */
6965 imm_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
6974 /* We use offset_reloc rather than imm_reloc for the PC
6975 relative operands. This lets macros with both
6976 immediate and address operands work correctly. */
6977 if (s
[0] == '$' && isdigit (s
[1]))
6979 /* Looks like a register name. */
6982 my_getExpression (&offset_expr
, s
);
6983 /* We need to relax this instruction. */
6984 offset_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
6988 case '6': /* break code */
6989 my_getExpression (&imm_expr
, s
);
6990 check_absolute_expr (ip
, &imm_expr
);
6991 if ((unsigned long) imm_expr
.X_add_number
> 63)
6993 as_warn ("Invalid value for `%s' (%lu)",
6995 (unsigned long) imm_expr
.X_add_number
);
6996 imm_expr
.X_add_number
&= 0x3f;
6998 ip
->insn_opcode
|= imm_expr
.X_add_number
<< MIPS16OP_SH_IMM6
;
6999 imm_expr
.X_op
= O_absent
;
7003 case 'a': /* 26 bit address */
7004 my_getExpression (&offset_expr
, s
);
7006 offset_reloc
= BFD_RELOC_MIPS16_JMP
;
7007 ip
->insn_opcode
<<= 16;
7010 case 'l': /* register list for entry macro */
7011 case 'L': /* register list for exit macro */
7023 while (*s
== ' ' || *s
== ',')
7027 as_bad ("can't parse register list");
7032 while (isdigit (*s
))
7049 while (isdigit (*s
))
7056 if (reg1
== 4 && reg2
>= 4 && reg2
<= 7 && c
!= 'L')
7057 mask
|= (reg2
- 3) << 3;
7058 else if (reg1
== 16 && reg2
>= 16 && reg2
<= 17)
7059 mask
|= (reg2
- 15) << 1;
7060 else if (reg1
== 31 && reg2
== 31)
7063 as_bad ("invalid register list");
7065 ip
->insn_opcode
|= mask
<< MIPS16OP_SH_IMM6
;
7075 /* Args don't match. */
7076 if (insn
+ 1 < &mips16_opcodes
[bfd_mips16_num_opcodes
] &&
7077 strcmp (insn
->name
, insn
[1].name
) == 0)
7084 insn_error
= "illegal operands";
7090 /* This structure holds information we know about a mips16 immediate
7093 struct mips16_immed_operand
7095 /* The type code used in the argument string in the opcode table. */
7097 /* The number of bits in the short form of the opcode. */
7099 /* The number of bits in the extended form of the opcode. */
7101 /* The amount by which the short form is shifted when it is used;
7102 for example, the sw instruction has a shift count of 2. */
7104 /* The amount by which the short form is shifted when it is stored
7105 into the instruction code. */
7107 /* Non-zero if the short form is unsigned. */
7109 /* Non-zero if the extended form is unsigned. */
7111 /* Non-zero if the value is PC relative. */
7115 /* The mips16 immediate operand types. */
7117 static const struct mips16_immed_operand mips16_immed_operands
[] =
7119 { '<', 3, 5, 0, MIPS16OP_SH_RZ
, 1, 1, 0 },
7120 { '>', 3, 5, 0, MIPS16OP_SH_RX
, 1, 1, 0 },
7121 { '[', 3, 6, 0, MIPS16OP_SH_RZ
, 1, 1, 0 },
7122 { ']', 3, 6, 0, MIPS16OP_SH_RX
, 1, 1, 0 },
7123 { '4', 4, 15, 0, MIPS16OP_SH_IMM4
, 0, 0, 0 },
7124 { '5', 5, 16, 0, MIPS16OP_SH_IMM5
, 1, 0, 0 },
7125 { 'H', 5, 16, 1, MIPS16OP_SH_IMM5
, 1, 0, 0 },
7126 { 'W', 5, 16, 2, MIPS16OP_SH_IMM5
, 1, 0, 0 },
7127 { 'D', 5, 16, 3, MIPS16OP_SH_IMM5
, 1, 0, 0 },
7128 { 'j', 5, 16, 0, MIPS16OP_SH_IMM5
, 0, 0, 0 },
7129 { '8', 8, 16, 0, MIPS16OP_SH_IMM8
, 1, 0, 0 },
7130 { 'V', 8, 16, 2, MIPS16OP_SH_IMM8
, 1, 0, 0 },
7131 { 'C', 8, 16, 3, MIPS16OP_SH_IMM8
, 1, 0, 0 },
7132 { 'U', 8, 16, 0, MIPS16OP_SH_IMM8
, 1, 1, 0 },
7133 { 'k', 8, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 0 },
7134 { 'K', 8, 16, 3, MIPS16OP_SH_IMM8
, 0, 0, 0 },
7135 { 'p', 8, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 1 },
7136 { 'q', 11, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 1 },
7137 { 'A', 8, 16, 2, MIPS16OP_SH_IMM8
, 1, 0, 1 },
7138 { 'B', 5, 16, 3, MIPS16OP_SH_IMM5
, 1, 0, 1 },
7139 { 'E', 5, 16, 2, MIPS16OP_SH_IMM5
, 1, 0, 1 }
7142 #define MIPS16_NUM_IMMED \
7143 (sizeof mips16_immed_operands / sizeof mips16_immed_operands[0])
7145 /* Handle a mips16 instruction with an immediate value. This or's the
7146 small immediate value into *INSN. It sets *USE_EXTEND to indicate
7147 whether an extended value is needed; if one is needed, it sets
7148 *EXTEND to the value. The argument type is TYPE. The value is VAL.
7149 If SMALL is true, an unextended opcode was explicitly requested.
7150 If EXT is true, an extended opcode was explicitly requested. If
7151 WARN is true, warn if EXT does not match reality. */
7154 mips16_immed (file
, line
, type
, val
, warn
, small
, ext
, insn
, use_extend
,
7163 unsigned long *insn
;
7164 boolean
*use_extend
;
7165 unsigned short *extend
;
7167 register const struct mips16_immed_operand
*op
;
7168 int mintiny
, maxtiny
;
7171 op
= mips16_immed_operands
;
7172 while (op
->type
!= type
)
7175 assert (op
< mips16_immed_operands
+ MIPS16_NUM_IMMED
);
7180 if (type
== '<' || type
== '>' || type
== '[' || type
== ']')
7183 maxtiny
= 1 << op
->nbits
;
7188 maxtiny
= (1 << op
->nbits
) - 1;
7193 mintiny
= - (1 << (op
->nbits
- 1));
7194 maxtiny
= (1 << (op
->nbits
- 1)) - 1;
7197 /* Branch offsets have an implicit 0 in the lowest bit. */
7198 if (type
== 'p' || type
== 'q')
7201 as_bad_where (file
, line
, "branch to odd address");
7205 if ((val
& ((1 << op
->shift
) - 1)) != 0
7206 || val
< (mintiny
<< op
->shift
)
7207 || val
> (maxtiny
<< op
->shift
))
7212 if (warn
&& ext
&& ! needext
)
7213 as_warn_where (file
, line
, "extended operand requested but not required");
7214 if (small
&& needext
)
7215 as_bad_where (file
, line
, "invalid unextended operand value");
7217 if (small
|| (! ext
&& ! needext
))
7221 *use_extend
= false;
7222 insnval
= ((val
>> op
->shift
) & ((1 << op
->nbits
) - 1));
7223 insnval
<<= op
->op_shift
;
7228 long minext
, maxext
;
7234 maxext
= (1 << op
->extbits
) - 1;
7238 minext
= - (1 << (op
->extbits
- 1));
7239 maxext
= (1 << (op
->extbits
- 1)) - 1;
7241 if (val
< minext
|| val
> maxext
)
7242 as_bad_where (file
, line
,
7243 "operand value out of range for instruction");
7246 if (op
->extbits
== 16)
7248 extval
= ((val
>> 11) & 0x1f) | (val
& 0x7e0);
7251 else if (op
->extbits
== 15)
7253 extval
= ((val
>> 11) & 0xf) | (val
& 0x7f0);
7258 extval
= ((val
& 0x1f) << 6) | (val
& 0x20);
7262 *extend
= (unsigned short) extval
;
7271 my_getSmallExpression (ep
, str
)
7282 ((str
[1] == 'h' && str
[2] == 'i')
7283 || (str
[1] == 'H' && str
[2] == 'I')
7284 || (str
[1] == 'l' && str
[2] == 'o'))
7296 * A small expression may be followed by a base register.
7297 * Scan to the end of this operand, and then back over a possible
7298 * base register. Then scan the small expression up to that
7299 * point. (Based on code in sparc.c...)
7301 for (sp
= str
; *sp
&& *sp
!= ','; sp
++)
7303 if (sp
- 4 >= str
&& sp
[-1] == RP
)
7305 if (isdigit (sp
[-2]))
7307 for (sp
-= 3; sp
>= str
&& isdigit (*sp
); sp
--)
7309 if (*sp
== '$' && sp
> str
&& sp
[-1] == LP
)
7315 else if (sp
- 5 >= str
7318 && ((sp
[-3] == 'f' && sp
[-2] == 'p')
7319 || (sp
[-3] == 's' && sp
[-2] == 'p')
7320 || (sp
[-3] == 'g' && sp
[-2] == 'p')
7321 || (sp
[-3] == 'a' && sp
[-2] == 't')))
7327 /* no expression means zero offset */
7330 /* %xx(reg) is an error */
7331 ep
->X_op
= O_absent
;
7336 ep
->X_op
= O_constant
;
7339 ep
->X_add_symbol
= NULL
;
7340 ep
->X_op_symbol
= NULL
;
7341 ep
->X_add_number
= 0;
7346 my_getExpression (ep
, str
);
7353 my_getExpression (ep
, str
);
7354 return c
; /* => %hi or %lo encountered */
7358 my_getExpression (ep
, str
)
7364 save_in
= input_line_pointer
;
7365 input_line_pointer
= str
;
7367 expr_end
= input_line_pointer
;
7368 input_line_pointer
= save_in
;
7371 /* Turn a string in input_line_pointer into a floating point constant
7372 of type type, and store the appropriate bytes in *litP. The number
7373 of LITTLENUMS emitted is stored in *sizeP . An error message is
7374 returned, or NULL on OK. */
7377 md_atof (type
, litP
, sizeP
)
7383 LITTLENUM_TYPE words
[4];
7399 return "bad call to md_atof";
7402 t
= atof_ieee (input_line_pointer
, type
, words
);
7404 input_line_pointer
= t
;
7408 if (byte_order
== LITTLE_ENDIAN
)
7410 for (i
= prec
- 1; i
>= 0; i
--)
7412 md_number_to_chars (litP
, (valueT
) words
[i
], 2);
7418 for (i
= 0; i
< prec
; i
++)
7420 md_number_to_chars (litP
, (valueT
) words
[i
], 2);
7429 md_number_to_chars (buf
, val
, n
)
7437 number_to_chars_littleendian (buf
, val
, n
);
7441 number_to_chars_bigendian (buf
, val
, n
);
7449 CONST
char *md_shortopts
= "O::g::G:";
7451 struct option md_longopts
[] = {
7452 #define OPTION_MIPS1 (OPTION_MD_BASE + 1)
7453 {"mips0", no_argument
, NULL
, OPTION_MIPS1
},
7454 {"mips1", no_argument
, NULL
, OPTION_MIPS1
},
7455 #define OPTION_MIPS2 (OPTION_MD_BASE + 2)
7456 {"mips2", no_argument
, NULL
, OPTION_MIPS2
},
7457 #define OPTION_MIPS3 (OPTION_MD_BASE + 3)
7458 {"mips3", no_argument
, NULL
, OPTION_MIPS3
},
7459 #define OPTION_MIPS4 (OPTION_MD_BASE + 4)
7460 {"mips4", no_argument
, NULL
, OPTION_MIPS4
},
7461 #define OPTION_MCPU (OPTION_MD_BASE + 5)
7462 {"mcpu", required_argument
, NULL
, OPTION_MCPU
},
7463 #define OPTION_MEMBEDDED_PIC (OPTION_MD_BASE + 6)
7464 {"membedded-pic", no_argument
, NULL
, OPTION_MEMBEDDED_PIC
},
7465 #define OPTION_TRAP (OPTION_MD_BASE + 9)
7466 {"trap", no_argument
, NULL
, OPTION_TRAP
},
7467 {"no-break", no_argument
, NULL
, OPTION_TRAP
},
7468 #define OPTION_BREAK (OPTION_MD_BASE + 10)
7469 {"break", no_argument
, NULL
, OPTION_BREAK
},
7470 {"no-trap", no_argument
, NULL
, OPTION_BREAK
},
7471 #define OPTION_EB (OPTION_MD_BASE + 11)
7472 {"EB", no_argument
, NULL
, OPTION_EB
},
7473 #define OPTION_EL (OPTION_MD_BASE + 12)
7474 {"EL", no_argument
, NULL
, OPTION_EL
},
7475 #define OPTION_M4650 (OPTION_MD_BASE + 13)
7476 {"m4650", no_argument
, NULL
, OPTION_M4650
},
7477 #define OPTION_NO_M4650 (OPTION_MD_BASE + 14)
7478 {"no-m4650", no_argument
, NULL
, OPTION_NO_M4650
},
7479 #define OPTION_M4010 (OPTION_MD_BASE + 15)
7480 {"m4010", no_argument
, NULL
, OPTION_M4010
},
7481 #define OPTION_NO_M4010 (OPTION_MD_BASE + 16)
7482 {"no-m4010", no_argument
, NULL
, OPTION_NO_M4010
},
7483 #define OPTION_M4100 (OPTION_MD_BASE + 17)
7484 {"m4100", no_argument
, NULL
, OPTION_M4100
},
7485 #define OPTION_NO_M4100 (OPTION_MD_BASE + 18)
7486 {"no-m4100", no_argument
, NULL
, OPTION_NO_M4100
},
7487 #define OPTION_MIPS16 (OPTION_MD_BASE + 22)
7488 {"mips16", no_argument
, NULL
, OPTION_MIPS16
},
7489 #define OPTION_NO_MIPS16 (OPTION_MD_BASE + 23)
7490 {"no-mips16", no_argument
, NULL
, OPTION_NO_MIPS16
},
7492 #define OPTION_CALL_SHARED (OPTION_MD_BASE + 7)
7493 #define OPTION_NON_SHARED (OPTION_MD_BASE + 8)
7494 #define OPTION_XGOT (OPTION_MD_BASE + 19)
7495 #define OPTION_32 (OPTION_MD_BASE + 20)
7496 #define OPTION_64 (OPTION_MD_BASE + 21)
7498 {"KPIC", no_argument
, NULL
, OPTION_CALL_SHARED
},
7499 {"xgot", no_argument
, NULL
, OPTION_XGOT
},
7500 {"call_shared", no_argument
, NULL
, OPTION_CALL_SHARED
},
7501 {"non_shared", no_argument
, NULL
, OPTION_NON_SHARED
},
7502 {"32", no_argument
, NULL
, OPTION_32
},
7503 {"64", no_argument
, NULL
, OPTION_64
},
7506 {NULL
, no_argument
, NULL
, 0}
7508 size_t md_longopts_size
= sizeof(md_longopts
);
7511 md_parse_option (c
, arg
)
7526 target_big_endian
= 1;
7530 target_big_endian
= 0;
7534 if (arg
&& arg
[1] == '0')
7544 mips_debug
= atoi (arg
);
7545 /* When the MIPS assembler sees -g or -g2, it does not do
7546 optimizations which limit full symbolic debugging. We take
7547 that to be equivalent to -O0. */
7548 if (mips_debug
== 2)
7580 /* Identify the processor type */
7582 if (strcmp (p
, "default") == 0
7583 || strcmp (p
, "DEFAULT") == 0)
7589 /* We need to cope with the various "vr" prefixes for the 4300
7591 if (*p
== 'v' || *p
== 'V')
7597 if (*p
== 'r' || *p
== 'R')
7604 if (strcmp (p
, "10000") == 0
7605 || strcmp (p
, "10k") == 0
7606 || strcmp (p
, "10K") == 0)
7611 if (strcmp (p
, "2000") == 0
7612 || strcmp (p
, "2k") == 0
7613 || strcmp (p
, "2K") == 0)
7618 if (strcmp (p
, "3000") == 0
7619 || strcmp (p
, "3k") == 0
7620 || strcmp (p
, "3K") == 0)
7625 if (strcmp (p
, "4000") == 0
7626 || strcmp (p
, "4k") == 0
7627 || strcmp (p
, "4K") == 0)
7629 else if (strcmp (p
, "4100") == 0)
7635 else if (strcmp (p
, "4300") == 0)
7637 else if (strcmp (p
, "4400") == 0)
7639 else if (strcmp (p
, "4600") == 0)
7641 else if (strcmp (p
, "4650") == 0)
7647 else if (strcmp (p
, "4010") == 0)
7656 if (strcmp (p
, "5000") == 0
7657 || strcmp (p
, "5k") == 0
7658 || strcmp (p
, "5K") == 0)
7663 if (strcmp (p
, "6000") == 0
7664 || strcmp (p
, "6k") == 0
7665 || strcmp (p
, "6K") == 0)
7670 if (strcmp (p
, "8000") == 0
7671 || strcmp (p
, "8k") == 0
7672 || strcmp (p
, "8K") == 0)
7677 if (strcmp (p
, "orion") == 0)
7682 if (sv
&& mips_cpu
!= 4300 && mips_cpu
!= 4100 && mips_cpu
!= 5000)
7684 as_bad ("ignoring invalid leading 'v' in -mcpu=%s switch", arg
);
7690 as_bad ("invalid architecture -mcpu=%s", arg
);
7701 case OPTION_NO_M4650
:
7709 case OPTION_NO_M4010
:
7717 case OPTION_NO_M4100
:
7723 mips_no_prev_insn ();
7726 case OPTION_NO_MIPS16
:
7728 mips_no_prev_insn ();
7731 case OPTION_MEMBEDDED_PIC
:
7732 mips_pic
= EMBEDDED_PIC
;
7733 if (USE_GLOBAL_POINTER_OPT
&& g_switch_seen
)
7735 as_bad ("-G may not be used with embedded PIC code");
7738 g_switch_value
= 0x7fffffff;
7741 /* When generating ELF code, we permit -KPIC and -call_shared to
7742 select SVR4_PIC, and -non_shared to select no PIC. This is
7743 intended to be compatible with Irix 5. */
7744 case OPTION_CALL_SHARED
:
7745 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
7747 as_bad ("-call_shared is supported only for ELF format");
7750 mips_pic
= SVR4_PIC
;
7751 if (g_switch_seen
&& g_switch_value
!= 0)
7753 as_bad ("-G may not be used with SVR4 PIC code");
7759 case OPTION_NON_SHARED
:
7760 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
7762 as_bad ("-non_shared is supported only for ELF format");
7768 /* The -xgot option tells the assembler to use 32 offsets when
7769 accessing the got in SVR4_PIC mode. It is for Irix
7776 if (! USE_GLOBAL_POINTER_OPT
)
7778 as_bad ("-G is not supported for this configuration");
7781 else if (mips_pic
== SVR4_PIC
|| mips_pic
== EMBEDDED_PIC
)
7783 as_bad ("-G may not be used with SVR4 or embedded PIC code");
7787 g_switch_value
= atoi (arg
);
7791 /* The -32 and -64 options tell the assembler to output the 32
7792 bit or the 64 bit MIPS ELF format. */
7799 const char **list
, **l
;
7801 list
= bfd_target_list ();
7802 for (l
= list
; *l
!= NULL
; l
++)
7803 if (strcmp (*l
, "elf64-bigmips") == 0
7804 || strcmp (*l
, "elf64-littlemips") == 0)
7807 as_fatal ("No compiled in support for 64 bit object file format");
7821 md_show_usage (stream
)
7826 -membedded-pic generate embedded position independent code\n\
7827 -EB generate big endian output\n\
7828 -EL generate little endian output\n\
7829 -g, -g2 do not remove uneeded NOPs or swap branches\n\
7830 -G NUM allow referencing objects up to NUM bytes\n\
7831 implicitly with the gp register [default 8]\n");
7833 -mips1, -mcpu=r{2,3}000 generate code for r2000 and r3000\n\
7834 -mips2, -mcpu=r6000 generate code for r6000\n\
7835 -mips3, -mcpu=r4000 generate code for r4000\n\
7836 -mips4, -mcpu=r8000 generate code for r8000\n\
7837 -mcpu=vr4300 generate code for vr4300\n\
7838 -mcpu=vr4100 generate code for vr4100\n\
7839 -m4650 permit R4650 instructions\n\
7840 -no-m4650 do not permit R4650 instructions\n\
7841 -m4010 permit R4010 instructions\n\
7842 -no-m4010 do not permit R4010 instructions\n\
7843 -m4100 permit VR4100 instructions\n\
7844 -no-m4100 do not permit VR4100 instructions\n");
7846 -mips16 generate mips16 instructions\n\
7847 -no-mips16 do not generate mips16 instructions\n");
7849 -O0 remove unneeded NOPs, do not swap branches\n\
7850 -O remove unneeded NOPs and swap branches\n\
7851 --trap, --no-break trap exception on div by 0 and mult overflow\n\
7852 --break, --no-trap break exception on div by 0 and mult overflow\n");
7855 -KPIC, -call_shared generate SVR4 position independent code\n\
7856 -non_shared do not generate position independent code\n\
7857 -xgot assume a 32 bit GOT\n\
7858 -32 create 32 bit object file (default)\n\
7859 -64 create 64 bit object file\n");
7864 mips_init_after_args ()
7866 if (target_big_endian
)
7867 byte_order
= BIG_ENDIAN
;
7869 byte_order
= LITTLE_ENDIAN
;
7873 md_pcrel_from (fixP
)
7876 if (OUTPUT_FLAVOR
!= bfd_target_aout_flavour
7877 && fixP
->fx_addsy
!= (symbolS
*) NULL
7878 && ! S_IS_DEFINED (fixP
->fx_addsy
))
7880 /* This makes a branch to an undefined symbol be a branch to the
7881 current location. */
7885 /* return the address of the delay slot */
7886 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
7889 /* This is called by emit_expr via TC_CONS_FIX_NEW when creating a
7890 reloc for a cons. We could use the definition there, except that
7891 we want to handle 64 bit relocs specially. */
7894 cons_fix_new_mips (frag
, where
, nbytes
, exp
)
7897 unsigned int nbytes
;
7901 /* If we are assembling in 32 bit mode, turn an 8 byte reloc into a
7903 if (nbytes
== 8 && ! mips_64
)
7905 if (byte_order
== BIG_ENDIAN
)
7911 if (nbytes
!= 2 && nbytes
!= 4 && nbytes
!= 8)
7912 as_bad ("Unsupported reloc size %d", nbytes
);
7914 fix_new_exp (frag_now
, where
, (int) nbytes
, exp
, 0,
7917 : (nbytes
== 4 ? BFD_RELOC_32
: BFD_RELOC_64
)));
7920 /* Sort any unmatched HI16_S relocs so that they immediately precede
7921 the corresponding LO reloc. This is called before md_apply_fix and
7922 tc_gen_reloc. Unmatched HI16_S relocs can only be generated by
7923 explicit use of the %hi modifier. */
7928 struct mips_hi_fixup
*l
;
7930 for (l
= mips_hi_fixup_list
; l
!= NULL
; l
= l
->next
)
7932 segment_info_type
*seginfo
;
7935 assert (l
->fixp
->fx_r_type
== BFD_RELOC_HI16_S
);
7937 /* Check quickly whether the next fixup happens to be a matching
7939 if (l
->fixp
->fx_next
!= NULL
7940 && l
->fixp
->fx_next
->fx_r_type
== BFD_RELOC_LO16
7941 && l
->fixp
->fx_addsy
== l
->fixp
->fx_next
->fx_addsy
7942 && l
->fixp
->fx_offset
== l
->fixp
->fx_next
->fx_offset
)
7945 /* Look through the fixups for this segment for a matching %lo.
7946 When we find one, move the %hi just in front of it. We do
7947 this in two passes. In the first pass, we try to find a
7948 unique %lo. In the second pass, we permit multiple %hi
7949 relocs for a single %lo (this is a GNU extension). */
7950 seginfo
= seg_info (l
->seg
);
7951 for (pass
= 0; pass
< 2; pass
++)
7956 for (f
= seginfo
->fix_root
; f
!= NULL
; f
= f
->fx_next
)
7958 /* Check whether this is a %lo fixup which matches l->fixp. */
7959 if (f
->fx_r_type
== BFD_RELOC_LO16
7960 && f
->fx_addsy
== l
->fixp
->fx_addsy
7961 && f
->fx_offset
== l
->fixp
->fx_offset
7964 || prev
->fx_r_type
!= BFD_RELOC_HI16_S
7965 || prev
->fx_addsy
!= f
->fx_addsy
7966 || prev
->fx_offset
!= f
->fx_offset
))
7970 /* Move l->fixp before f. */
7971 for (pf
= &seginfo
->fix_root
;
7973 pf
= &(*pf
)->fx_next
)
7974 assert (*pf
!= NULL
);
7976 *pf
= l
->fixp
->fx_next
;
7978 l
->fixp
->fx_next
= f
;
7980 seginfo
->fix_root
= l
->fixp
;
7982 prev
->fx_next
= l
->fixp
;
7994 as_warn_where (l
->fixp
->fx_file
, l
->fixp
->fx_line
,
7995 "Unmatched %%hi reloc");
8000 /* When generating embedded PIC code we need to use a special
8001 relocation to represent the difference of two symbols in the .text
8002 section (switch tables use a difference of this sort). See
8003 include/coff/mips.h for details. This macro checks whether this
8004 fixup requires the special reloc. */
8005 #define SWITCH_TABLE(fixp) \
8006 ((fixp)->fx_r_type == BFD_RELOC_32 \
8007 && (fixp)->fx_addsy != NULL \
8008 && (fixp)->fx_subsy != NULL \
8009 && S_GET_SEGMENT ((fixp)->fx_addsy) == text_section \
8010 && S_GET_SEGMENT ((fixp)->fx_subsy) == text_section)
8012 /* When generating embedded PIC code we must keep all PC relative
8013 relocations, in case the linker has to relax a call. We also need
8014 to keep relocations for switch table entries. */
8018 mips_force_relocation (fixp
)
8021 return (mips_pic
== EMBEDDED_PIC
8023 || SWITCH_TABLE (fixp
)
8024 || fixp
->fx_r_type
== BFD_RELOC_PCREL_HI16_S
8025 || fixp
->fx_r_type
== BFD_RELOC_PCREL_LO16
));
8028 /* Apply a fixup to the object file. */
8031 md_apply_fix (fixP
, valueP
)
8038 assert (fixP
->fx_size
== 4
8039 || fixP
->fx_r_type
== BFD_RELOC_16
8040 || fixP
->fx_r_type
== BFD_RELOC_64
);
8043 fixP
->fx_addnumber
= value
; /* Remember value for tc_gen_reloc */
8045 if (fixP
->fx_addsy
== NULL
&& ! fixP
->fx_pcrel
)
8048 switch (fixP
->fx_r_type
)
8050 case BFD_RELOC_MIPS_JMP
:
8051 case BFD_RELOC_HI16
:
8052 case BFD_RELOC_HI16_S
:
8053 case BFD_RELOC_MIPS_GPREL
:
8054 case BFD_RELOC_MIPS_LITERAL
:
8055 case BFD_RELOC_MIPS_CALL16
:
8056 case BFD_RELOC_MIPS_GOT16
:
8057 case BFD_RELOC_MIPS_GPREL32
:
8058 case BFD_RELOC_MIPS_GOT_HI16
:
8059 case BFD_RELOC_MIPS_GOT_LO16
:
8060 case BFD_RELOC_MIPS_CALL_HI16
:
8061 case BFD_RELOC_MIPS_CALL_LO16
:
8063 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
8064 "Invalid PC relative reloc");
8065 /* Nothing needed to do. The value comes from the reloc entry */
8068 case BFD_RELOC_MIPS16_JMP
:
8069 /* We currently always generate a reloc against a symbol, which
8070 means that we don't want an addend even if the symbol is
8072 fixP
->fx_addnumber
= 0;
8075 case BFD_RELOC_PCREL_HI16_S
:
8076 /* The addend for this is tricky if it is internal, so we just
8077 do everything here rather than in bfd_perform_relocation. */
8078 if ((fixP
->fx_addsy
->bsym
->flags
& BSF_SECTION_SYM
) == 0)
8080 /* For an external symbol adjust by the address to make it
8081 pcrel_offset. We use the address of the RELLO reloc
8082 which follows this one. */
8083 value
+= (fixP
->fx_next
->fx_frag
->fr_address
8084 + fixP
->fx_next
->fx_where
);
8089 buf
= (unsigned char *) fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
8090 if (byte_order
== BIG_ENDIAN
)
8092 md_number_to_chars (buf
, value
, 2);
8095 case BFD_RELOC_PCREL_LO16
:
8096 /* The addend for this is tricky if it is internal, so we just
8097 do everything here rather than in bfd_perform_relocation. */
8098 if ((fixP
->fx_addsy
->bsym
->flags
& BSF_SECTION_SYM
) == 0)
8099 value
+= fixP
->fx_frag
->fr_address
+ fixP
->fx_where
;
8100 buf
= (unsigned char *) fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
8101 if (byte_order
== BIG_ENDIAN
)
8103 md_number_to_chars (buf
, value
, 2);
8107 /* This is handled like BFD_RELOC_32, but we output a sign
8108 extended value if we are only 32 bits. */
8110 || (mips_pic
== EMBEDDED_PIC
&& SWITCH_TABLE (fixP
)))
8112 if (8 <= sizeof (valueT
))
8113 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
,
8120 w1
= w2
= fixP
->fx_where
;
8121 if (byte_order
== BIG_ENDIAN
)
8125 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ w1
, value
, 4);
8126 if ((value
& 0x80000000) != 0)
8130 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ w2
, hiv
, 4);
8136 /* If we are deleting this reloc entry, we must fill in the
8137 value now. This can happen if we have a .word which is not
8138 resolved when it appears but is later defined. We also need
8139 to fill in the value if this is an embedded PIC switch table
8142 || (mips_pic
== EMBEDDED_PIC
&& SWITCH_TABLE (fixP
)))
8143 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
,
8148 /* If we are deleting this reloc entry, we must fill in the
8150 assert (fixP
->fx_size
== 2);
8152 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
,
8156 case BFD_RELOC_LO16
:
8157 /* When handling an embedded PIC switch statement, we can wind
8158 up deleting a LO16 reloc. See the 'o' case in mips_ip. */
8161 if (value
< -0x8000 || value
> 0x7fff)
8162 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
8163 "relocation overflow");
8164 buf
= (unsigned char *) fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
8165 if (byte_order
== BIG_ENDIAN
)
8167 md_number_to_chars (buf
, value
, 2);
8171 case BFD_RELOC_16_PCREL_S2
:
8173 * We need to save the bits in the instruction since fixup_segment()
8174 * might be deleting the relocation entry (i.e., a branch within
8175 * the current segment).
8177 /* TinyRISC can branch to odd addresses */
8178 if ((value
& (mips16
? 0x1 : 0x3)) != 0)
8179 as_warn_where (fixP
->fx_file
, fixP
->fx_line
,
8180 "Branch to odd address (%lx)", value
);
8183 /* update old instruction data */
8184 buf
= (unsigned char *) (fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
);
8188 insn
= (buf
[3] << 24) | (buf
[2] << 16) | (buf
[1] << 8) | buf
[0];
8192 insn
= (buf
[0] << 24) | (buf
[1] << 16) | (buf
[2] << 8) | buf
[3];
8200 if (value
>= -0x8000 && value
< 0x8000)
8201 insn
|= value
& 0xffff;
8204 /* The branch offset is too large. If this is an
8205 unconditional branch, and we are not generating PIC code,
8206 we can convert it to an absolute jump instruction. */
8207 if (mips_pic
== NO_PIC
8209 && fixP
->fx_frag
->fr_address
>= text_section
->vma
8210 && (fixP
->fx_frag
->fr_address
8211 < text_section
->vma
+ text_section
->_raw_size
)
8212 && ((insn
& 0xffff0000) == 0x10000000 /* beq $0,$0 */
8213 || (insn
& 0xffff0000) == 0x04010000 /* bgez $0 */
8214 || (insn
& 0xffff0000) == 0x04110000)) /* bgezal $0 */
8216 if ((insn
& 0xffff0000) == 0x04110000) /* bgezal $0 */
8217 insn
= 0x0c000000; /* jal */
8219 insn
= 0x08000000; /* j */
8220 fixP
->fx_r_type
= BFD_RELOC_MIPS_JMP
;
8222 fixP
->fx_addsy
= section_symbol (text_section
);
8223 fixP
->fx_addnumber
= (value
<< 2) + md_pcrel_from (fixP
);
8227 /* FIXME. It would be possible in principle to handle
8228 conditional branches which overflow. They could be
8229 transformed into a branch around a jump. This would
8230 require setting up variant frags for each different
8231 branch type. The native MIPS assembler attempts to
8232 handle these cases, but it appears to do it
8234 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
8235 "Relocation overflow");
8239 md_number_to_chars ((char *) buf
, (valueT
) insn
, 4);
8254 const struct mips_opcode
*p
;
8255 int treg
, sreg
, dreg
, shamt
;
8260 for (i
= 0; i
< NUMOPCODES
; ++i
)
8262 p
= &mips_opcodes
[i
];
8263 if (((oc
& p
->mask
) == p
->match
) && (p
->pinfo
!= INSN_MACRO
))
8265 printf ("%08lx %s\t", oc
, p
->name
);
8266 treg
= (oc
>> 16) & 0x1f;
8267 sreg
= (oc
>> 21) & 0x1f;
8268 dreg
= (oc
>> 11) & 0x1f;
8269 shamt
= (oc
>> 6) & 0x1f;
8271 for (args
= p
->args
;; ++args
)
8282 printf ("%c", *args
);
8286 assert (treg
== sreg
);
8287 printf ("$%d,$%d", treg
, sreg
);
8292 printf ("$%d", dreg
);
8297 printf ("$%d", treg
);
8301 printf ("0x%x", treg
);
8306 printf ("$%d", sreg
);
8310 printf ("0x%08lx", oc
& 0x1ffffff);
8322 printf ("$%d", shamt
);
8333 printf ("%08lx UNDEFINED\n", oc
);
8344 name
= input_line_pointer
;
8345 c
= get_symbol_end ();
8346 p
= (symbolS
*) symbol_find_or_make (name
);
8347 *input_line_pointer
= c
;
8351 /* Align the current frag to a given power of two. The MIPS assembler
8352 also automatically adjusts any preceding label. */
8355 mips_align (to
, fill
, label
)
8360 mips_emit_delays ();
8361 frag_align (to
, fill
);
8362 record_alignment (now_seg
, to
);
8365 assert (S_GET_SEGMENT (label
) == now_seg
);
8366 label
->sy_frag
= frag_now
;
8367 S_SET_VALUE (label
, (valueT
) frag_now_fix ());
8371 /* Align to a given power of two. .align 0 turns off the automatic
8372 alignment used by the data creating pseudo-ops. */
8379 register long temp_fill
;
8380 long max_alignment
= 15;
8384 o Note that the assembler pulls down any immediately preceeding label
8385 to the aligned address.
8386 o It's not documented but auto alignment is reinstated by
8387 a .align pseudo instruction.
8388 o Note also that after auto alignment is turned off the mips assembler
8389 issues an error on attempt to assemble an improperly aligned data item.
8394 temp
= get_absolute_expression ();
8395 if (temp
> max_alignment
)
8396 as_bad ("Alignment too large: %d. assumed.", temp
= max_alignment
);
8399 as_warn ("Alignment negative: 0 assumed.");
8402 if (*input_line_pointer
== ',')
8404 input_line_pointer
++;
8405 temp_fill
= get_absolute_expression ();
8412 mips_align (temp
, (int) temp_fill
, insn_label
);
8419 demand_empty_rest_of_line ();
8423 mips_flush_pending_output ()
8425 mips_emit_delays ();
8435 /* When generating embedded PIC code, we only use the .text, .lit8,
8436 .sdata and .sbss sections. We change the .data and .rdata
8437 pseudo-ops to use .sdata. */
8438 if (mips_pic
== EMBEDDED_PIC
8439 && (sec
== 'd' || sec
== 'r'))
8442 mips_emit_delays ();
8452 subseg_set (bss_section
, (subsegT
) get_absolute_expression ());
8453 demand_empty_rest_of_line ();
8457 if (USE_GLOBAL_POINTER_OPT
)
8459 seg
= subseg_new (RDATA_SECTION_NAME
,
8460 (subsegT
) get_absolute_expression ());
8461 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
8463 bfd_set_section_flags (stdoutput
, seg
,
8469 bfd_set_section_alignment (stdoutput
, seg
, 4);
8471 demand_empty_rest_of_line ();
8475 as_bad ("No read only data section in this object file format");
8476 demand_empty_rest_of_line ();
8482 if (USE_GLOBAL_POINTER_OPT
)
8484 seg
= subseg_new (".sdata", (subsegT
) get_absolute_expression ());
8485 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
8487 bfd_set_section_flags (stdoutput
, seg
,
8488 SEC_ALLOC
| SEC_LOAD
| SEC_RELOC
8490 bfd_set_section_alignment (stdoutput
, seg
, 4);
8492 demand_empty_rest_of_line ();
8497 as_bad ("Global pointers not supported; recompile -G 0");
8498 demand_empty_rest_of_line ();
8507 mips_enable_auto_align ()
8519 mips_emit_delays ();
8520 if (log_size
> 0 && auto_align
)
8521 mips_align (log_size
, 0, label
);
8523 cons (1 << log_size
);
8534 mips_emit_delays ();
8538 mips_align (3, 0, label
);
8540 mips_align (2, 0, label
);
8547 /* Handle .globl. We need to override it because on Irix 5 you are
8550 where foo is an undefined symbol, to mean that foo should be
8551 considered to be the address of a function. */
8562 name
= input_line_pointer
;
8563 c
= get_symbol_end ();
8564 symbolP
= symbol_find_or_make (name
);
8565 *input_line_pointer
= c
;
8568 /* On Irix 5, every global symbol that is not explicitly labelled as
8569 being a function is apparently labelled as being an object. */
8572 if (! is_end_of_line
[(unsigned char) *input_line_pointer
])
8577 secname
= input_line_pointer
;
8578 c
= get_symbol_end ();
8579 sec
= bfd_get_section_by_name (stdoutput
, secname
);
8581 as_bad ("%s: no such section", secname
);
8582 *input_line_pointer
= c
;
8584 if (sec
!= NULL
&& (sec
->flags
& SEC_CODE
) != 0)
8585 flag
= BSF_FUNCTION
;
8588 symbolP
->bsym
->flags
|= flag
;
8590 S_SET_EXTERNAL (symbolP
);
8591 demand_empty_rest_of_line ();
8601 opt
= input_line_pointer
;
8602 c
= get_symbol_end ();
8606 /* FIXME: What does this mean? */
8608 else if (strncmp (opt
, "pic", 3) == 0)
8616 mips_pic
= SVR4_PIC
;
8618 as_bad (".option pic%d not supported", i
);
8620 if (USE_GLOBAL_POINTER_OPT
&& mips_pic
== SVR4_PIC
)
8622 if (g_switch_seen
&& g_switch_value
!= 0)
8623 as_warn ("-G may not be used with SVR4 PIC code");
8625 bfd_set_gp_size (stdoutput
, 0);
8629 as_warn ("Unrecognized option \"%s\"", opt
);
8631 *input_line_pointer
= c
;
8632 demand_empty_rest_of_line ();
8639 char *name
= input_line_pointer
, ch
;
8641 while (!is_end_of_line
[(unsigned char) *input_line_pointer
])
8642 input_line_pointer
++;
8643 ch
= *input_line_pointer
;
8644 *input_line_pointer
= '\0';
8646 if (strcmp (name
, "reorder") == 0)
8650 prev_insn_unreordered
= 1;
8651 prev_prev_insn_unreordered
= 1;
8655 else if (strcmp (name
, "noreorder") == 0)
8657 mips_emit_delays ();
8659 mips_any_noreorder
= 1;
8661 else if (strcmp (name
, "at") == 0)
8665 else if (strcmp (name
, "noat") == 0)
8669 else if (strcmp (name
, "macro") == 0)
8671 mips_warn_about_macros
= 0;
8673 else if (strcmp (name
, "nomacro") == 0)
8675 if (mips_noreorder
== 0)
8676 as_bad ("`noreorder' must be set before `nomacro'");
8677 mips_warn_about_macros
= 1;
8679 else if (strcmp (name
, "move") == 0 || strcmp (name
, "novolatile") == 0)
8683 else if (strcmp (name
, "nomove") == 0 || strcmp (name
, "volatile") == 0)
8687 else if (strcmp (name
, "bopt") == 0)
8691 else if (strcmp (name
, "nobopt") == 0)
8695 else if (strcmp (name
, "mips16") == 0
8696 || strcmp (name
, "MIPS-16") == 0)
8698 else if (strcmp (name
, "nomips16") == 0
8699 || strcmp (name
, "noMIPS-16") == 0)
8701 else if (strncmp (name
, "mips", 4) == 0)
8705 /* Permit the user to change the ISA on the fly. Needless to
8706 say, misuse can cause serious problems. */
8707 isa
= atoi (name
+ 4);
8709 mips_isa
= file_mips_isa
;
8710 else if (isa
< 1 || isa
> 4)
8711 as_bad ("unknown ISA level");
8715 else if (strcmp (name
, "autoextend") == 0)
8716 mips16_autoextend
= 1;
8717 else if (strcmp (name
, "noautoextend") == 0)
8718 mips16_autoextend
= 0;
8721 as_warn ("Tried to set unrecognized symbol: %s\n", name
);
8723 *input_line_pointer
= ch
;
8724 demand_empty_rest_of_line ();
8727 /* Handle the .abicalls pseudo-op. I believe this is equivalent to
8728 .option pic2. It means to generate SVR4 PIC calls. */
8734 mips_pic
= SVR4_PIC
;
8735 if (USE_GLOBAL_POINTER_OPT
)
8737 if (g_switch_seen
&& g_switch_value
!= 0)
8738 as_warn ("-G may not be used with SVR4 PIC code");
8741 bfd_set_gp_size (stdoutput
, 0);
8742 demand_empty_rest_of_line ();
8745 /* Handle the .cpload pseudo-op. This is used when generating SVR4
8746 PIC code. It sets the $gp register for the function based on the
8747 function address, which is in the register named in the argument.
8748 This uses a relocation against _gp_disp, which is handled specially
8749 by the linker. The result is:
8750 lui $gp,%hi(_gp_disp)
8751 addiu $gp,$gp,%lo(_gp_disp)
8752 addu $gp,$gp,.cpload argument
8753 The .cpload argument is normally $25 == $t9. */
8762 /* If we are not generating SVR4 PIC code, .cpload is ignored. */
8763 if (mips_pic
!= SVR4_PIC
)
8769 /* .cpload should be a in .set noreorder section. */
8770 if (mips_noreorder
== 0)
8771 as_warn (".cpload not in noreorder section");
8774 ex
.X_add_symbol
= symbol_find_or_make ("_gp_disp");
8775 ex
.X_op_symbol
= NULL
;
8776 ex
.X_add_number
= 0;
8778 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
8779 ex
.X_add_symbol
->bsym
->flags
|= BSF_OBJECT
;
8781 macro_build_lui ((char *) NULL
, &icnt
, &ex
, GP
);
8782 macro_build ((char *) NULL
, &icnt
, &ex
, "addiu", "t,r,j", GP
, GP
,
8783 (int) BFD_RELOC_LO16
);
8785 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "addu", "d,v,t",
8786 GP
, GP
, tc_get_register (0));
8788 demand_empty_rest_of_line ();
8791 /* Handle the .cprestore pseudo-op. This stores $gp into a given
8792 offset from $sp. The offset is remembered, and after making a PIC
8793 call $gp is restored from that location. */
8796 s_cprestore (ignore
)
8802 /* If we are not generating SVR4 PIC code, .cprestore is ignored. */
8803 if (mips_pic
!= SVR4_PIC
)
8809 mips_cprestore_offset
= get_absolute_expression ();
8811 ex
.X_op
= O_constant
;
8812 ex
.X_add_symbol
= NULL
;
8813 ex
.X_op_symbol
= NULL
;
8814 ex
.X_add_number
= mips_cprestore_offset
;
8816 macro_build ((char *) NULL
, &icnt
, &ex
,
8817 mips_isa
< 3 ? "sw" : "sd",
8818 "t,o(b)", GP
, (int) BFD_RELOC_LO16
, SP
);
8820 demand_empty_rest_of_line ();
8823 /* Handle the .gpword pseudo-op. This is used when generating PIC
8824 code. It generates a 32 bit GP relative reloc. */
8834 /* When not generating PIC code, this is treated as .word. */
8835 if (mips_pic
!= SVR4_PIC
)
8842 mips_emit_delays ();
8844 mips_align (2, 0, label
);
8849 if (ex
.X_op
!= O_symbol
|| ex
.X_add_number
!= 0)
8851 as_bad ("Unsupported use of .gpword");
8852 ignore_rest_of_line ();
8856 md_number_to_chars (p
, (valueT
) 0, 4);
8857 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 4, &ex
, 0,
8858 BFD_RELOC_MIPS_GPREL32
);
8860 demand_empty_rest_of_line ();
8863 /* Handle the .cpadd pseudo-op. This is used when dealing with switch
8864 tables in SVR4 PIC code. */
8873 /* This is ignored when not generating SVR4 PIC code. */
8874 if (mips_pic
!= SVR4_PIC
)
8880 /* Add $gp to the register named as an argument. */
8881 reg
= tc_get_register (0);
8882 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
8883 mips_isa
< 3 ? "addu" : "daddu",
8884 "d,v,t", reg
, reg
, GP
);
8886 demand_empty_rest_of_line ();
8889 /* Parse a register string into a number. Called from the ECOFF code
8890 to parse .frame. The argument is non-zero if this is the frame
8891 register, so that we can record it in mips_frame_reg. */
8894 tc_get_register (frame
)
8900 if (*input_line_pointer
++ != '$')
8902 as_warn ("expected `$'");
8905 else if (isdigit ((unsigned char) *input_line_pointer
))
8907 reg
= get_absolute_expression ();
8908 if (reg
< 0 || reg
>= 32)
8910 as_warn ("Bad register number");
8916 if (strncmp (input_line_pointer
, "fp", 2) == 0)
8918 else if (strncmp (input_line_pointer
, "sp", 2) == 0)
8920 else if (strncmp (input_line_pointer
, "gp", 2) == 0)
8922 else if (strncmp (input_line_pointer
, "at", 2) == 0)
8926 as_warn ("Unrecognized register name");
8929 input_line_pointer
+= 2;
8932 mips_frame_reg
= reg
!= 0 ? reg
: SP
;
8937 md_section_align (seg
, addr
)
8941 int align
= bfd_get_section_alignment (stdoutput
, seg
);
8944 /* We don't need to align ELF sections to the full alignment.
8945 However, Irix 5 may prefer that we align them at least to a 16
8951 return ((addr
+ (1 << align
) - 1) & (-1 << align
));
8954 /* Utility routine, called from above as well. If called while the
8955 input file is still being read, it's only an approximation. (For
8956 example, a symbol may later become defined which appeared to be
8957 undefined earlier.) */
8960 nopic_need_relax (sym
)
8966 if (USE_GLOBAL_POINTER_OPT
)
8968 const char *symname
;
8971 /* Find out whether this symbol can be referenced off the GP
8972 register. It can be if it is smaller than the -G size or if
8973 it is in the .sdata or .sbss section. Certain symbols can
8974 not be referenced off the GP, although it appears as though
8976 symname
= S_GET_NAME (sym
);
8977 if (symname
!= (const char *) NULL
8978 && (strcmp (symname
, "eprol") == 0
8979 || strcmp (symname
, "etext") == 0
8980 || strcmp (symname
, "_gp") == 0
8981 || strcmp (symname
, "edata") == 0
8982 || strcmp (symname
, "_fbss") == 0
8983 || strcmp (symname
, "_fdata") == 0
8984 || strcmp (symname
, "_ftext") == 0
8985 || strcmp (symname
, "end") == 0
8986 || strcmp (symname
, "_gp_disp") == 0))
8988 else if (! S_IS_DEFINED (sym
)
8990 #ifndef NO_ECOFF_DEBUGGING
8991 || (sym
->ecoff_extern_size
!= 0
8992 && sym
->ecoff_extern_size
<= g_switch_value
)
8994 || (S_GET_VALUE (sym
) != 0
8995 && S_GET_VALUE (sym
) <= g_switch_value
)))
8999 const char *segname
;
9001 segname
= segment_name (S_GET_SEGMENT (sym
));
9002 assert (strcmp (segname
, ".lit8") != 0
9003 && strcmp (segname
, ".lit4") != 0);
9004 change
= (strcmp (segname
, ".sdata") != 0
9005 && strcmp (segname
, ".sbss") != 0);
9010 /* We are not optimizing for the GP register. */
9014 /* Given a mips16 variant frag FRAGP, return non-zero if it needs an
9015 extended opcode. SEC is the section the frag is in. */
9018 mips16_extended_frag (fragp
, sec
, stretch
)
9024 register const struct mips16_immed_operand
*op
;
9026 int mintiny
, maxtiny
;
9029 if (RELAX_MIPS16_USER_SMALL (fragp
->fr_subtype
))
9031 if (RELAX_MIPS16_USER_EXT (fragp
->fr_subtype
))
9034 type
= RELAX_MIPS16_TYPE (fragp
->fr_subtype
);
9035 op
= mips16_immed_operands
;
9036 while (op
->type
!= type
)
9039 assert (op
< mips16_immed_operands
+ MIPS16_NUM_IMMED
);
9044 if (type
== '<' || type
== '>' || type
== '[' || type
== ']')
9047 maxtiny
= 1 << op
->nbits
;
9052 maxtiny
= (1 << op
->nbits
) - 1;
9057 mintiny
= - (1 << (op
->nbits
- 1));
9058 maxtiny
= (1 << (op
->nbits
- 1)) - 1;
9061 /* We can't call S_GET_VALUE here, because we don't want to lock in
9062 a particular frag address. */
9063 if (fragp
->fr_symbol
->sy_value
.X_op
== O_constant
)
9065 val
= (fragp
->fr_symbol
->sy_value
.X_add_number
9066 + fragp
->fr_symbol
->sy_frag
->fr_address
);
9067 symsec
= S_GET_SEGMENT (fragp
->fr_symbol
);
9069 else if (fragp
->fr_symbol
->sy_value
.X_op
== O_symbol
9070 && (fragp
->fr_symbol
->sy_value
.X_add_symbol
->sy_value
.X_op
9073 val
= (fragp
->fr_symbol
->sy_value
.X_add_symbol
->sy_value
.X_add_number
9074 + fragp
->fr_symbol
->sy_value
.X_add_symbol
->sy_frag
->fr_address
9075 + fragp
->fr_symbol
->sy_value
.X_add_number
9076 + fragp
->fr_symbol
->sy_frag
->fr_address
);
9077 symsec
= S_GET_SEGMENT (fragp
->fr_symbol
->sy_value
.X_add_symbol
);
9086 /* We won't have the section when we are called from
9087 mips_relax_frag. However, we will always have been called
9088 from md_estimate_size_before_relax first. If this is a
9089 branch to a different section, we mark it as such. If SEC is
9090 NULL, and the frag is not marked, then it must be a branch to
9091 the same section. */
9094 if (RELAX_MIPS16_LONG_BRANCH (fragp
->fr_subtype
))
9102 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
9104 /* FIXME: We should support this, and let the linker
9105 catch branches and loads that are out of range. */
9106 as_bad_where (fragp
->fr_file
, fragp
->fr_line
,
9107 "unsupported PC relative reference to different section");
9113 /* In this case, we know for sure that the symbol fragment is in
9114 the same section. If the fr_address of the symbol fragment
9115 is greater then the address of this fragment we want to add
9116 in STRETCH in order to get a better estimate of the address.
9117 This particularly matters because of the shift bits. */
9119 && fragp
->fr_symbol
->sy_frag
->fr_address
>= fragp
->fr_address
)
9123 /* Adjust stretch for any alignment frag. */
9124 for (f
= fragp
; f
!= fragp
->fr_symbol
->sy_frag
; f
= f
->fr_next
)
9127 if (f
->fr_type
== rs_align
|| f
->fr_type
== rs_align_code
)
9130 stretch
= - ((- stretch
)
9131 & ~ ((1 << (int) f
->fr_offset
) - 1));
9133 stretch
&= ~ ((1 << (int) f
->fr_offset
) - 1);
9141 addr
= fragp
->fr_address
+ fragp
->fr_fix
+ 2;
9143 /* If we are currently assuming that this frag should be
9144 extended, then the current address is two bytes higher. */
9145 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
9148 val
-= addr
& ~ ((1 << op
->shift
) - 1);
9150 /* Branch offsets have an implicit 0 in the lowest bit. */
9151 if (type
== 'p' || type
== 'q')
9154 /* If any of the shifted bits are set, we must use an extended
9155 opcode. If the address depends on the size of this
9156 instruction, this can lead to a loop, so we arrange to always
9157 use an extended opcode. We only check this when we are in
9158 the main relaxation loop, when SEC is NULL. */
9159 if ((val
& ((1 << op
->shift
) - 1)) != 0 && sec
== NULL
)
9162 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
9166 /* If we are about to mark a frag as extended because the value
9167 is precisely maxtiny + 1, then there is a chance of an
9168 infinite loop as in the following code:
9173 In this case when the la is extended, foo is 0x3fc bytes
9174 away, so the la can be shrunk, but then foo is 0x400 away, so
9175 the la must be extended. To avoid this loop, we mark the
9176 frag as extended if it was small, and is about to become
9177 extended with a value of maxtiny + 1. */
9178 if (val
== ((maxtiny
+ 1) << op
->shift
)
9179 && ! RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
)
9183 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
9188 if ((val
& ((1 << op
->shift
) - 1)) != 0
9189 || val
< (mintiny
<< op
->shift
)
9190 || val
> (maxtiny
<< op
->shift
))
9196 /* Estimate the size of a frag before relaxing. Unless this is the
9197 mips16, we are not really relaxing here, and the final size is
9198 encoded in the subtype information. For the mips16, we have to
9199 decide whether we are using an extended opcode or not. */
9203 md_estimate_size_before_relax (fragp
, segtype
)
9209 if (RELAX_MIPS16_P (fragp
->fr_subtype
))
9211 if (mips16_extended_frag (fragp
, segtype
, 0))
9213 fragp
->fr_subtype
= RELAX_MIPS16_MARK_EXTENDED (fragp
->fr_subtype
);
9218 fragp
->fr_subtype
= RELAX_MIPS16_CLEAR_EXTENDED (fragp
->fr_subtype
);
9223 if (mips_pic
== NO_PIC
)
9225 change
= nopic_need_relax (fragp
->fr_symbol
);
9227 else if (mips_pic
== SVR4_PIC
)
9229 asection
*symsec
= fragp
->fr_symbol
->bsym
->section
;
9231 /* This must duplicate the test in adjust_reloc_syms. */
9232 change
= (symsec
!= &bfd_und_section
9233 && symsec
!= &bfd_abs_section
9234 && ! bfd_is_com_section (symsec
));
9241 /* Record the offset to the first reloc in the fr_opcode field.
9242 This lets md_convert_frag and tc_gen_reloc know that the code
9243 must be expanded. */
9244 fragp
->fr_opcode
= (fragp
->fr_literal
9246 - RELAX_OLD (fragp
->fr_subtype
)
9247 + RELAX_RELOC1 (fragp
->fr_subtype
));
9248 /* FIXME: This really needs as_warn_where. */
9249 if (RELAX_WARN (fragp
->fr_subtype
))
9250 as_warn ("AT used after \".set noat\" or macro used after \".set nomacro\"");
9256 return RELAX_NEW (fragp
->fr_subtype
) - RELAX_OLD (fragp
->fr_subtype
);
9259 /* Translate internal representation of relocation info to BFD target
9263 tc_gen_reloc (section
, fixp
)
9267 static arelent
*retval
[4];
9269 bfd_reloc_code_real_type code
;
9271 reloc
= retval
[0] = (arelent
*) xmalloc (sizeof (arelent
));
9274 reloc
->sym_ptr_ptr
= &fixp
->fx_addsy
->bsym
;
9275 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
9277 if (mips_pic
== EMBEDDED_PIC
9278 && SWITCH_TABLE (fixp
))
9280 /* For a switch table entry we use a special reloc. The addend
9281 is actually the difference between the reloc address and the
9283 reloc
->addend
= reloc
->address
- S_GET_VALUE (fixp
->fx_subsy
);
9284 if (OUTPUT_FLAVOR
!= bfd_target_ecoff_flavour
)
9285 as_fatal ("Double check fx_r_type in tc-mips.c:tc_gen_reloc");
9286 fixp
->fx_r_type
= BFD_RELOC_GPREL32
;
9288 else if (fixp
->fx_r_type
== BFD_RELOC_PCREL_LO16
)
9290 /* We use a special addend for an internal RELLO reloc. */
9291 if (fixp
->fx_addsy
->bsym
->flags
& BSF_SECTION_SYM
)
9292 reloc
->addend
= reloc
->address
- S_GET_VALUE (fixp
->fx_subsy
);
9294 reloc
->addend
= fixp
->fx_addnumber
+ reloc
->address
;
9296 else if (fixp
->fx_r_type
== BFD_RELOC_PCREL_HI16_S
)
9298 assert (fixp
->fx_next
!= NULL
9299 && fixp
->fx_next
->fx_r_type
== BFD_RELOC_PCREL_LO16
);
9300 /* We use a special addend for an internal RELHI reloc. The
9301 reloc is relative to the RELLO; adjust the addend
9303 if (fixp
->fx_addsy
->bsym
->flags
& BSF_SECTION_SYM
)
9304 reloc
->addend
= (fixp
->fx_next
->fx_frag
->fr_address
9305 + fixp
->fx_next
->fx_where
9306 - S_GET_VALUE (fixp
->fx_subsy
));
9308 reloc
->addend
= (fixp
->fx_addnumber
9309 + fixp
->fx_next
->fx_frag
->fr_address
9310 + fixp
->fx_next
->fx_where
);
9312 else if (fixp
->fx_pcrel
== 0)
9313 reloc
->addend
= fixp
->fx_addnumber
;
9316 if (OUTPUT_FLAVOR
!= bfd_target_aout_flavour
)
9317 /* A gruesome hack which is a result of the gruesome gas reloc
9319 reloc
->addend
= reloc
->address
;
9321 reloc
->addend
= -reloc
->address
;
9324 /* If this is a variant frag, we may need to adjust the existing
9325 reloc and generate a new one. */
9326 if (fixp
->fx_frag
->fr_opcode
!= NULL
9327 && (fixp
->fx_r_type
== BFD_RELOC_MIPS_GPREL
9328 || fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT16
9329 || fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL16
9330 || fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT_HI16
9331 || fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT_LO16
9332 || fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL_HI16
9333 || fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL_LO16
))
9337 assert (! RELAX_MIPS16_P (fixp
->fx_frag
->fr_subtype
));
9339 /* If this is not the last reloc in this frag, then we have two
9340 GPREL relocs, or a GOT_HI16/GOT_LO16 pair, or a
9341 CALL_HI16/CALL_LO16, both of which are being replaced. Let
9342 the second one handle all of them. */
9343 if (fixp
->fx_next
!= NULL
9344 && fixp
->fx_frag
== fixp
->fx_next
->fx_frag
)
9346 assert ((fixp
->fx_r_type
== BFD_RELOC_MIPS_GPREL
9347 && fixp
->fx_next
->fx_r_type
== BFD_RELOC_MIPS_GPREL
)
9348 || (fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT_HI16
9349 && (fixp
->fx_next
->fx_r_type
9350 == BFD_RELOC_MIPS_GOT_LO16
))
9351 || (fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL_HI16
9352 && (fixp
->fx_next
->fx_r_type
9353 == BFD_RELOC_MIPS_CALL_LO16
)));
9358 fixp
->fx_where
= fixp
->fx_frag
->fr_opcode
- fixp
->fx_frag
->fr_literal
;
9359 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
9360 reloc2
= retval
[1] = (arelent
*) xmalloc (sizeof (arelent
));
9362 reloc2
->sym_ptr_ptr
= &fixp
->fx_addsy
->bsym
;
9363 reloc2
->address
= (reloc
->address
9364 + (RELAX_RELOC2 (fixp
->fx_frag
->fr_subtype
)
9365 - RELAX_RELOC1 (fixp
->fx_frag
->fr_subtype
)));
9366 reloc2
->addend
= fixp
->fx_addnumber
;
9367 reloc2
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_LO16
);
9368 assert (reloc2
->howto
!= NULL
);
9370 if (RELAX_RELOC3 (fixp
->fx_frag
->fr_subtype
))
9374 reloc3
= retval
[2] = (arelent
*) xmalloc (sizeof (arelent
));
9377 reloc3
->address
+= 4;
9380 if (mips_pic
== NO_PIC
)
9382 assert (fixp
->fx_r_type
== BFD_RELOC_MIPS_GPREL
);
9383 fixp
->fx_r_type
= BFD_RELOC_HI16_S
;
9385 else if (mips_pic
== SVR4_PIC
)
9387 switch (fixp
->fx_r_type
)
9391 case BFD_RELOC_MIPS_GOT16
:
9393 case BFD_RELOC_MIPS_CALL16
:
9394 case BFD_RELOC_MIPS_GOT_LO16
:
9395 case BFD_RELOC_MIPS_CALL_LO16
:
9396 fixp
->fx_r_type
= BFD_RELOC_MIPS_GOT16
;
9404 /* Since DIFF_EXPR_OK is defined in tc-mips.h, it is possible that
9405 fixup_segment converted a non-PC relative reloc into a PC
9406 relative reloc. In such a case, we need to convert the reloc
9408 code
= fixp
->fx_r_type
;
9414 code
= BFD_RELOC_8_PCREL
;
9417 code
= BFD_RELOC_16_PCREL
;
9420 code
= BFD_RELOC_32_PCREL
;
9423 code
= BFD_RELOC_64_PCREL
;
9425 case BFD_RELOC_8_PCREL
:
9426 case BFD_RELOC_16_PCREL
:
9427 case BFD_RELOC_32_PCREL
:
9428 case BFD_RELOC_64_PCREL
:
9429 case BFD_RELOC_16_PCREL_S2
:
9430 case BFD_RELOC_PCREL_HI16_S
:
9431 case BFD_RELOC_PCREL_LO16
:
9434 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
9435 "Cannot make %s relocation PC relative",
9436 bfd_get_reloc_code_name (code
));
9440 /* To support a PC relative reloc when generating embedded PIC code
9441 for ECOFF, we use a Cygnus extension. We check for that here to
9442 make sure that we don't let such a reloc escape normally. */
9443 if (OUTPUT_FLAVOR
== bfd_target_ecoff_flavour
9444 && code
== BFD_RELOC_16_PCREL_S2
9445 && mips_pic
!= EMBEDDED_PIC
)
9446 reloc
->howto
= NULL
;
9448 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
9450 if (reloc
->howto
== NULL
)
9452 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
9453 "Can not represent %s relocation in this object file format",
9454 bfd_get_reloc_code_name (code
));
9461 /* Relax a machine dependent frag. This returns the amount by which
9462 the current size of the frag should change. */
9465 mips_relax_frag (fragp
, stretch
)
9469 if (! RELAX_MIPS16_P (fragp
->fr_subtype
))
9472 if (mips16_extended_frag (fragp
, (asection
*) NULL
, stretch
))
9474 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
9476 fragp
->fr_subtype
= RELAX_MIPS16_MARK_EXTENDED (fragp
->fr_subtype
);
9481 if (! RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
9483 fragp
->fr_subtype
= RELAX_MIPS16_CLEAR_EXTENDED (fragp
->fr_subtype
);
9490 /* Convert a machine dependent frag. */
9493 md_convert_frag (abfd
, asec
, fragp
)
9501 if (RELAX_MIPS16_P (fragp
->fr_subtype
))
9504 register const struct mips16_immed_operand
*op
;
9510 unsigned short extend
;
9512 type
= RELAX_MIPS16_TYPE (fragp
->fr_subtype
);
9513 op
= mips16_immed_operands
;
9514 while (op
->type
!= type
)
9517 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
9528 resolve_symbol_value (fragp
->fr_symbol
);
9529 val
= S_GET_VALUE (fragp
->fr_symbol
);
9534 addr
= fragp
->fr_address
+ fragp
->fr_fix
+ 2;
9537 addr
&= ~ (addressT
) ((1 << op
->shift
) - 1);
9541 buf
= (bfd_byte
*) (fragp
->fr_literal
+ fragp
->fr_fix
);
9548 insn
= bfd_getl16 (buf
);
9551 insn
= bfd_getb16 (buf
);
9555 mips16_immed (fragp
->fr_file
, fragp
->fr_line
, type
, val
, false, small
,
9556 ext
, &insn
, &use_extend
, &extend
);
9560 md_number_to_chars (buf
, 0xf000 | extend
, 2);
9565 md_number_to_chars (buf
, insn
, 2);
9571 if (fragp
->fr_opcode
== NULL
)
9574 old
= RELAX_OLD (fragp
->fr_subtype
);
9575 new = RELAX_NEW (fragp
->fr_subtype
);
9576 fixptr
= fragp
->fr_literal
+ fragp
->fr_fix
;
9579 memcpy (fixptr
- old
, fixptr
, new);
9581 fragp
->fr_fix
+= new - old
;
9585 /* This function is called whenever a label is defined. It is used
9586 when handling branch delays; if a branch has a label, we assume we
9590 mips_define_label (sym
)
9596 S_SET_OTHER (insn_label
, STO_MIPS16
);
9600 /* Decide whether a label is local. This is called by LOCAL_LABEL.
9601 In order to work with gcc when using mips-tfile, we must keep all
9602 local labels. However, in other cases, we want to discard them,
9603 since they are useless. */
9606 mips_local_label (name
)
9609 #ifndef NO_ECOFF_DEBUGGING
9612 && ! ecoff_debugging_seen
)
9614 /* We were called with -g, but we didn't see any debugging
9615 information. That may mean that gcc is smuggling debugging
9616 information through to mips-tfile, in which case we must
9617 generate all local labels. */
9622 /* Here it's OK to discard local labels. */
9624 return name
[0] == '$';
9627 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9629 /* Some special processing for a MIPS ELF file. */
9632 mips_elf_final_processing ()
9634 /* Write out the register information. */
9639 s
.ri_gprmask
= mips_gprmask
;
9640 s
.ri_cprmask
[0] = mips_cprmask
[0];
9641 s
.ri_cprmask
[1] = mips_cprmask
[1];
9642 s
.ri_cprmask
[2] = mips_cprmask
[2];
9643 s
.ri_cprmask
[3] = mips_cprmask
[3];
9644 /* The gp_value field is set by the MIPS ELF backend. */
9646 bfd_mips_elf32_swap_reginfo_out (stdoutput
, &s
,
9647 ((Elf32_External_RegInfo
*)
9648 mips_regmask_frag
));
9652 Elf64_Internal_RegInfo s
;
9654 s
.ri_gprmask
= mips_gprmask
;
9656 s
.ri_cprmask
[0] = mips_cprmask
[0];
9657 s
.ri_cprmask
[1] = mips_cprmask
[1];
9658 s
.ri_cprmask
[2] = mips_cprmask
[2];
9659 s
.ri_cprmask
[3] = mips_cprmask
[3];
9660 /* The gp_value field is set by the MIPS ELF backend. */
9662 bfd_mips_elf64_swap_reginfo_out (stdoutput
, &s
,
9663 ((Elf64_External_RegInfo
*)
9664 mips_regmask_frag
));
9667 /* Set the MIPS ELF flag bits. FIXME: There should probably be some
9668 sort of BFD interface for this. */
9669 if (mips_any_noreorder
)
9670 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_NOREORDER
;
9671 if (mips_pic
!= NO_PIC
)
9672 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_PIC
;
9675 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */
9677 /* These functions should really be defined by the object file format,
9678 since they are related to debugging information. However, this
9679 code has to work for the a.out format, which does not define them,
9680 so we provide simple versions here. These don't actually generate
9681 any debugging information, but they do simple checking and someday
9682 somebody may make them useful. */
9686 struct loc
*loc_next
;
9687 unsigned long loc_fileno
;
9688 unsigned long loc_lineno
;
9689 unsigned long loc_offset
;
9690 unsigned short loc_delta
;
9691 unsigned short loc_count
;
9700 struct proc
*proc_next
;
9701 struct symbol
*proc_isym
;
9702 struct symbol
*proc_end
;
9703 unsigned long proc_reg_mask
;
9704 unsigned long proc_reg_offset
;
9705 unsigned long proc_fpreg_mask
;
9706 unsigned long proc_fpreg_offset
;
9707 unsigned long proc_frameoffset
;
9708 unsigned long proc_framereg
;
9709 unsigned long proc_pcreg
;
9711 struct file
*proc_file
;
9718 struct file
*file_next
;
9719 unsigned long file_fileno
;
9720 struct symbol
*file_symbol
;
9721 struct symbol
*file_end
;
9722 struct proc
*file_proc
;
9727 static struct obstack proc_frags
;
9728 static procS
*proc_lastP
;
9729 static procS
*proc_rootP
;
9730 static int numprocs
;
9735 obstack_begin (&proc_frags
, 0x2000);
9741 /* check for premature end, nesting errors, etc */
9742 if (proc_lastP
&& proc_lastP
->proc_end
== NULL
)
9743 as_warn ("missing `.end' at end of assembly");
9752 if (*input_line_pointer
== '-')
9754 ++input_line_pointer
;
9757 if (!isdigit (*input_line_pointer
))
9758 as_bad ("Expected simple number.");
9759 if (input_line_pointer
[0] == '0')
9761 if (input_line_pointer
[1] == 'x')
9763 input_line_pointer
+= 2;
9764 while (isxdigit (*input_line_pointer
))
9767 val
|= hex_value (*input_line_pointer
++);
9769 return negative
? -val
: val
;
9773 ++input_line_pointer
;
9774 while (isdigit (*input_line_pointer
))
9777 val
|= *input_line_pointer
++ - '0';
9779 return negative
? -val
: val
;
9782 if (!isdigit (*input_line_pointer
))
9784 printf (" *input_line_pointer == '%c' 0x%02x\n",
9785 *input_line_pointer
, *input_line_pointer
);
9786 as_warn ("Invalid number");
9789 while (isdigit (*input_line_pointer
))
9792 val
+= *input_line_pointer
++ - '0';
9794 return negative
? -val
: val
;
9797 /* The .file directive; just like the usual .file directive, but there
9798 is an initial number which is the ECOFF file index. */
9806 line
= get_number ();
9811 /* The .end directive. */
9819 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
9822 demand_empty_rest_of_line ();
9826 if (now_seg
!= text_section
)
9827 as_warn (".end not in text section");
9830 as_warn (".end and no .ent seen yet.");
9836 assert (S_GET_NAME (p
));
9837 if (strcmp (S_GET_NAME (p
), S_GET_NAME (proc_lastP
->proc_isym
)))
9838 as_warn (".end symbol does not match .ent symbol.");
9841 proc_lastP
->proc_end
= (symbolS
*) 1;
9844 /* The .aent and .ent directives. */
9854 symbolP
= get_symbol ();
9855 if (*input_line_pointer
== ',')
9856 input_line_pointer
++;
9858 if (isdigit (*input_line_pointer
) || *input_line_pointer
== '-')
9859 number
= get_number ();
9860 if (now_seg
!= text_section
)
9861 as_warn (".ent or .aent not in text section.");
9863 if (!aent
&& proc_lastP
&& proc_lastP
->proc_end
== NULL
)
9864 as_warn ("missing `.end'");
9868 procP
= (procS
*) obstack_alloc (&proc_frags
, sizeof (*procP
));
9869 procP
->proc_isym
= symbolP
;
9870 procP
->proc_reg_mask
= 0;
9871 procP
->proc_reg_offset
= 0;
9872 procP
->proc_fpreg_mask
= 0;
9873 procP
->proc_fpreg_offset
= 0;
9874 procP
->proc_frameoffset
= 0;
9875 procP
->proc_framereg
= 0;
9876 procP
->proc_pcreg
= 0;
9877 procP
->proc_end
= NULL
;
9878 procP
->proc_next
= NULL
;
9880 proc_lastP
->proc_next
= procP
;
9886 demand_empty_rest_of_line ();
9889 /* The .frame directive. */
9902 frame_reg
= tc_get_register (1);
9903 if (*input_line_pointer
== ',')
9904 input_line_pointer
++;
9905 frame_off
= get_absolute_expression ();
9906 if (*input_line_pointer
== ',')
9907 input_line_pointer
++;
9908 pcreg
= tc_get_register (0);
9911 assert (proc_rootP
);
9912 proc_rootP
->proc_framereg
= frame_reg
;
9913 proc_rootP
->proc_frameoffset
= frame_off
;
9914 proc_rootP
->proc_pcreg
= pcreg
;
9915 /* bob macho .frame */
9917 /* We don't have to write out a frame stab for unoptimized code. */
9918 if (!(frame_reg
== FP
&& frame_off
== 0))
9921 as_warn ("No .ent for .frame to use.");
9922 (void) sprintf (str
, "R%d;%d", frame_reg
, frame_off
);
9923 symP
= symbol_new (str
, N_VFP
, 0, frag_now
);
9924 S_SET_TYPE (symP
, N_RMASK
);
9925 S_SET_OTHER (symP
, 0);
9926 S_SET_DESC (symP
, 0);
9927 symP
->sy_forward
= proc_lastP
->proc_isym
;
9928 /* bob perhaps I should have used pseudo set */
9930 demand_empty_rest_of_line ();
9934 /* The .fmask and .mask directives. */
9941 char str
[100], *strP
;
9947 mask
= get_number ();
9948 if (*input_line_pointer
== ',')
9949 input_line_pointer
++;
9950 off
= get_absolute_expression ();
9952 /* bob only for coff */
9953 assert (proc_rootP
);
9954 if (reg_type
== 'F')
9956 proc_rootP
->proc_fpreg_mask
= mask
;
9957 proc_rootP
->proc_fpreg_offset
= off
;
9961 proc_rootP
->proc_reg_mask
= mask
;
9962 proc_rootP
->proc_reg_offset
= off
;
9965 /* bob macho .mask + .fmask */
9967 /* We don't have to write out a mask stab if no saved regs. */
9971 as_warn ("No .ent for .mask to use.");
9973 for (i
= 0; i
< 32; i
++)
9977 sprintf (strP
, "%c%d,", reg_type
, i
);
9978 strP
+= strlen (strP
);
9982 sprintf (strP
, ";%d,", off
);
9983 symP
= symbol_new (str
, N_RMASK
, 0, frag_now
);
9984 S_SET_TYPE (symP
, N_RMASK
);
9985 S_SET_OTHER (symP
, 0);
9986 S_SET_DESC (symP
, 0);
9987 symP
->sy_forward
= proc_lastP
->proc_isym
;
9988 /* bob perhaps I should have used pseudo set */
9993 /* The .loc directive. */
10004 assert (now_seg
== text_section
);
10006 lineno
= get_number ();
10007 addroff
= frag_now_fix ();
10009 symbolP
= symbol_new ("", N_SLINE
, addroff
, frag_now
);
10010 S_SET_TYPE (symbolP
, N_SLINE
);
10011 S_SET_OTHER (symbolP
, 0);
10012 S_SET_DESC (symbolP
, lineno
);
10013 symbolP
->sy_segment
= now_seg
;