1 /* tc-mips.c -- assemble code for a MIPS chip.
2 Copyright (C) 1993, 1994, 1995, 1996, 1997 Free Software Foundation, Inc.
3 Contributed by the OSF and Ralph Campbell.
4 Written by Keith Knowles and Ralph Campbell, working independently.
5 Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus
8 This file is part of GAS.
10 GAS is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 2, or (at your option)
15 GAS is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with GAS; see the file COPYING. If not, write to the Free
22 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
38 #include "opcode/mips.h"
41 /* Clean up namespace so we can include obj-elf.h too. */
42 static int mips_output_flavor () { return OUTPUT_FLAVOR
; }
43 #undef OBJ_PROCESS_STAB
49 #undef TARGET_SYMBOL_FIELDS
51 #undef obj_frob_file_after_relocs
52 #undef obj_frob_symbol
54 #undef obj_sec_sym_ok_for_reloc
57 /* Fix any of them that we actually care about. */
59 #define OUTPUT_FLAVOR mips_output_flavor()
66 #ifndef ECOFF_DEBUGGING
67 #define NO_ECOFF_DEBUGGING
68 #define ECOFF_DEBUGGING 0
73 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
74 static char *mips_regmask_frag
;
79 #define PIC_CALL_REG 25
87 #define ILLEGAL_REG (32)
89 extern int target_big_endian
;
91 /* 1 is we should use the 64 bit MIPS ELF ABI, 0 if we should use the
92 32 bit ABI. This has no meaning for ECOFF. */
95 /* The default target format to use. */
99 switch (OUTPUT_FLAVOR
)
101 case bfd_target_aout_flavour
:
102 return target_big_endian
? "a.out-mips-big" : "a.out-mips-little";
103 case bfd_target_ecoff_flavour
:
104 return target_big_endian
? "ecoff-bigmips" : "ecoff-littlemips";
105 case bfd_target_elf_flavour
:
106 return (target_big_endian
107 ? (mips_64
? "elf64-bigmips" : "elf32-bigmips")
108 : (mips_64
? "elf64-littlemips" : "elf32-littlemips"));
114 /* The name of the readonly data section. */
115 #define RDATA_SECTION_NAME (OUTPUT_FLAVOR == bfd_target_aout_flavour \
117 : OUTPUT_FLAVOR == bfd_target_ecoff_flavour \
119 : OUTPUT_FLAVOR == bfd_target_elf_flavour \
123 /* These variables are filled in with the masks of registers used.
124 The object format code reads them and puts them in the appropriate
126 unsigned long mips_gprmask
;
127 unsigned long mips_cprmask
[4];
129 /* MIPS ISA (Instruction Set Architecture) level (may be changed
130 temporarily using .set mipsN). */
131 static int mips_isa
= -1;
133 /* MIPS ISA we are using for this output file. */
134 static int file_mips_isa
;
136 /* Whether we are assembling for the mips16 processor. */
137 static int mips16
= -1;
139 /* The CPU type as a number: 2000, 3000, 4000, 4400, etc. */
140 static int mips_cpu
= -1;
142 /* Whether the 4650 instructions (mad/madu) are permitted. */
143 static int mips_4650
= -1;
145 /* Whether the 4010 instructions are permitted. */
146 static int mips_4010
= -1;
148 /* Whether the 4100 MADD16 and DMADD16 are permitted. */
149 static int mips_4100
= -1;
151 /* start-sanitize-r5900 */
152 /* Whether Toshiba r5900 instructions are permitted. */
153 static int mips_5900
= -1;
154 /* end-sanitize-r5900 */
156 /* Whether the processor uses hardware interlocks, and thus does not
157 require nops to be inserted. */
158 static int interlocks
= -1;
160 /* As with "interlocks" this is used by hardware that has FP
161 (co-processor) interlocks. */
162 static int cop_interlocks
= -1;
164 /* MIPS PIC level. */
168 /* Do not generate PIC code. */
171 /* Generate PIC code as in Irix 4. This is not implemented, and I'm
172 not sure what it is supposed to do. */
175 /* Generate PIC code as in the SVR4 MIPS ABI. */
178 /* Generate PIC code without using a global offset table: the data
179 segment has a maximum size of 64K, all data references are off
180 the $gp register, and all text references are PC relative. This
181 is used on some embedded systems. */
185 static enum mips_pic_level mips_pic
;
187 /* 1 if we should generate 32 bit offsets from the GP register in
188 SVR4_PIC mode. Currently has no meaning in other modes. */
189 static int mips_big_got
;
191 /* 1 if trap instructions should used for overflow rather than break
193 static int mips_trap
;
195 /* 1 if we should autoextend mips16 instructions. */
196 static int mips16_autoextend
= 1;
198 static int mips_warn_about_macros
;
199 static int mips_noreorder
;
200 static int mips_any_noreorder
;
201 static int mips_nomove
;
202 static int mips_noat
;
203 static int mips_nobopt
;
205 /* The size of the small data section. */
206 static int g_switch_value
= 8;
207 /* Whether the -G option was used. */
208 static int g_switch_seen
= 0;
213 /* If we can determine in advance that GP optimization won't be
214 possible, we can skip the relaxation stuff that tries to produce
215 GP-relative references. This makes delay slot optimization work
218 This function can only provide a guess, but it seems to work for
219 gcc output. If it guesses wrong, the only loss should be in
220 efficiency; it shouldn't introduce any bugs.
222 I don't know if a fix is needed for the SVR4_PIC mode. I've only
223 fixed it for the non-PIC mode. KR 95/04/07 */
224 static int nopic_need_relax
PARAMS ((symbolS
*));
226 /* handle of the OPCODE hash table */
227 static struct hash_control
*op_hash
= NULL
;
229 /* The opcode hash table we use for the mips16. */
230 static struct hash_control
*mips16_op_hash
= NULL
;
232 /* This array holds the chars that always start a comment. If the
233 pre-processor is disabled, these aren't very useful */
234 const char comment_chars
[] = "#";
236 /* This array holds the chars that only start a comment at the beginning of
237 a line. If the line seems to have the form '# 123 filename'
238 .line and .file directives will appear in the pre-processed output */
239 /* Note that input_file.c hand checks for '#' at the beginning of the
240 first line of the input file. This is because the compiler outputs
241 #NO_APP at the beginning of its output. */
242 /* Also note that C style comments are always supported. */
243 const char line_comment_chars
[] = "#";
245 /* This array holds machine specific line separator characters. */
246 const char line_separator_chars
[] = "";
248 /* Chars that can be used to separate mant from exp in floating point nums */
249 const char EXP_CHARS
[] = "eE";
251 /* Chars that mean this number is a floating point constant */
254 const char FLT_CHARS
[] = "rRsSfFdDxXpP";
256 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
257 changed in read.c . Ideally it shouldn't have to know about it at all,
258 but nothing is ideal around here.
261 static char *insn_error
;
263 static int auto_align
= 1;
265 /* When outputting SVR4 PIC code, the assembler needs to know the
266 offset in the stack frame from which to restore the $gp register.
267 This is set by the .cprestore pseudo-op, and saved in this
269 static offsetT mips_cprestore_offset
= -1;
271 /* This is the register which holds the stack frame, as set by the
272 .frame pseudo-op. This is needed to implement .cprestore. */
273 static int mips_frame_reg
= SP
;
275 /* To output NOP instructions correctly, we need to keep information
276 about the previous two instructions. */
278 /* Whether we are optimizing. The default value of 2 means to remove
279 unneeded NOPs and swap branch instructions when possible. A value
280 of 1 means to not swap branches. A value of 0 means to always
282 static int mips_optimize
= 2;
284 /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is
285 equivalent to seeing no -g option at all. */
286 static int mips_debug
= 0;
288 /* The previous instruction. */
289 static struct mips_cl_insn prev_insn
;
291 /* The instruction before prev_insn. */
292 static struct mips_cl_insn prev_prev_insn
;
294 /* If we don't want information for prev_insn or prev_prev_insn, we
295 point the insn_mo field at this dummy integer. */
296 static const struct mips_opcode dummy_opcode
= { 0 };
298 /* Non-zero if prev_insn is valid. */
299 static int prev_insn_valid
;
301 /* The frag for the previous instruction. */
302 static struct frag
*prev_insn_frag
;
304 /* The offset into prev_insn_frag for the previous instruction. */
305 static long prev_insn_where
;
307 /* The reloc type for the previous instruction, if any. */
308 static bfd_reloc_code_real_type prev_insn_reloc_type
;
310 /* The reloc for the previous instruction, if any. */
311 static fixS
*prev_insn_fixp
;
313 /* Non-zero if the previous instruction was in a delay slot. */
314 static int prev_insn_is_delay_slot
;
316 /* Non-zero if the previous instruction was in a .set noreorder. */
317 static int prev_insn_unreordered
;
319 /* Non-zero if the previous instruction uses an extend opcode (if
321 static int prev_insn_extended
;
323 /* Non-zero if the previous previous instruction was in a .set
325 static int prev_prev_insn_unreordered
;
327 /* For ECOFF and ELF, relocations against symbols are done in two
328 parts, with a HI relocation and a LO relocation. Each relocation
329 has only 16 bits of space to store an addend. This means that in
330 order for the linker to handle carries correctly, it must be able
331 to locate both the HI and the LO relocation. This means that the
332 relocations must appear in order in the relocation table.
334 In order to implement this, we keep track of each unmatched HI
335 relocation. We then sort them so that they immediately precede the
336 corresponding LO relocation. */
341 struct mips_hi_fixup
*next
;
344 /* The section this fixup is in. */
348 /* The list of unmatched HI relocs. */
350 static struct mips_hi_fixup
*mips_hi_fixup_list
;
352 /* Map normal MIPS register numbers to mips16 register numbers. */
354 #define X ILLEGAL_REG
355 static const int mips32_to_16_reg_map
[] =
357 X
, X
, 2, 3, 4, 5, 6, 7,
358 X
, X
, X
, X
, X
, X
, X
, X
,
359 0, 1, X
, X
, X
, X
, X
, X
,
360 X
, X
, X
, X
, X
, X
, X
, X
364 /* Map mips16 register numbers to normal MIPS register numbers. */
366 static const int mips16_to_32_reg_map
[] =
368 16, 17, 2, 3, 4, 5, 6, 7
371 /* Since the MIPS does not have multiple forms of PC relative
372 instructions, we do not have to do relaxing as is done on other
373 platforms. However, we do have to handle GP relative addressing
374 correctly, which turns out to be a similar problem.
376 Every macro that refers to a symbol can occur in (at least) two
377 forms, one with GP relative addressing and one without. For
378 example, loading a global variable into a register generally uses
379 a macro instruction like this:
381 If i can be addressed off the GP register (this is true if it is in
382 the .sbss or .sdata section, or if it is known to be smaller than
383 the -G argument) this will generate the following instruction:
385 This instruction will use a GPREL reloc. If i can not be addressed
386 off the GP register, the following instruction sequence will be used:
389 In this case the first instruction will have a HI16 reloc, and the
390 second reloc will have a LO16 reloc. Both relocs will be against
393 The issue here is that we may not know whether i is GP addressable
394 until after we see the instruction that uses it. Therefore, we
395 want to be able to choose the final instruction sequence only at
396 the end of the assembly. This is similar to the way other
397 platforms choose the size of a PC relative instruction only at the
400 When generating position independent code we do not use GP
401 addressing in quite the same way, but the issue still arises as
402 external symbols and local symbols must be handled differently.
404 We handle these issues by actually generating both possible
405 instruction sequences. The longer one is put in a frag_var with
406 type rs_machine_dependent. We encode what to do with the frag in
407 the subtype field. We encode (1) the number of existing bytes to
408 replace, (2) the number of new bytes to use, (3) the offset from
409 the start of the existing bytes to the first reloc we must generate
410 (that is, the offset is applied from the start of the existing
411 bytes after they are replaced by the new bytes, if any), (4) the
412 offset from the start of the existing bytes to the second reloc,
413 (5) whether a third reloc is needed (the third reloc is always four
414 bytes after the second reloc), and (6) whether to warn if this
415 variant is used (this is sometimes needed if .set nomacro or .set
416 noat is in effect). All these numbers are reasonably small.
418 Generating two instruction sequences must be handled carefully to
419 ensure that delay slots are handled correctly. Fortunately, there
420 are a limited number of cases. When the second instruction
421 sequence is generated, append_insn is directed to maintain the
422 existing delay slot information, so it continues to apply to any
423 code after the second instruction sequence. This means that the
424 second instruction sequence must not impose any requirements not
425 required by the first instruction sequence.
427 These variant frags are then handled in functions called by the
428 machine independent code. md_estimate_size_before_relax returns
429 the final size of the frag. md_convert_frag sets up the final form
430 of the frag. tc_gen_reloc adjust the first reloc and adds a second
432 #define RELAX_ENCODE(old, new, reloc1, reloc2, reloc3, warn) \
436 | (((reloc1) + 64) << 9) \
437 | (((reloc2) + 64) << 2) \
438 | ((reloc3) ? (1 << 1) : 0) \
440 #define RELAX_OLD(i) (((i) >> 23) & 0x7f)
441 #define RELAX_NEW(i) (((i) >> 16) & 0x7f)
442 #define RELAX_RELOC1(i) ((bfd_vma)(((i) >> 9) & 0x7f) - 64)
443 #define RELAX_RELOC2(i) ((bfd_vma)(((i) >> 2) & 0x7f) - 64)
444 #define RELAX_RELOC3(i) (((i) >> 1) & 1)
445 #define RELAX_WARN(i) ((i) & 1)
447 /* For mips16 code, we use an entirely different form of relaxation.
448 mips16 supports two versions of most instructions which take
449 immediate values: a small one which takes some small value, and a
450 larger one which takes a 16 bit value. Since branches also follow
451 this pattern, relaxing these values is required.
453 We can assemble both mips16 and normal MIPS code in a single
454 object. Therefore, we need to support this type of relaxation at
455 the same time that we support the relaxation described above. We
456 use the high bit of the subtype field to distinguish these cases.
458 The information we store for this type of relaxation is the
459 argument code found in the opcode file for this relocation, whether
460 the user explicitly requested a small or extended form, and whether
461 the relocation is in a jump or jal delay slot. That tells us the
462 size of the value, and how it should be stored. We also store
463 whether the fragment is considered to be extended or not. We also
464 store whether this is known to be a branch to a different section,
465 whether we have tried to relax this frag yet, and whether we have
466 ever extended a PC relative fragment because of a shift count. */
467 #define RELAX_MIPS16_ENCODE(type, small, ext, dslot, jal_dslot) \
470 | ((small) ? 0x100 : 0) \
471 | ((ext) ? 0x200 : 0) \
472 | ((dslot) ? 0x400 : 0) \
473 | ((jal_dslot) ? 0x800 : 0))
474 #define RELAX_MIPS16_P(i) (((i) & 0x80000000) != 0)
475 #define RELAX_MIPS16_TYPE(i) ((i) & 0xff)
476 #define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x100) != 0)
477 #define RELAX_MIPS16_USER_EXT(i) (((i) & 0x200) != 0)
478 #define RELAX_MIPS16_DSLOT(i) (((i) & 0x400) != 0)
479 #define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x800) != 0)
480 #define RELAX_MIPS16_EXTENDED(i) (((i) & 0x1000) != 0)
481 #define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x1000)
482 #define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) &~ 0x1000)
483 #define RELAX_MIPS16_LONG_BRANCH(i) (((i) & 0x2000) != 0)
484 #define RELAX_MIPS16_MARK_LONG_BRANCH(i) ((i) | 0x2000)
485 #define RELAX_MIPS16_CLEAR_LONG_BRANCH(i) ((i) &~ 0x2000)
487 /* Prototypes for static functions. */
490 #define internalError() \
491 as_fatal ("internal Error, line %d, %s", __LINE__, __FILE__)
493 #define internalError() as_fatal ("MIPS internal Error");
496 enum mips_regclass
{ MIPS_GR_REG
, MIPS_FP_REG
, MIPS16_REG
};
498 static int insn_uses_reg
PARAMS ((struct mips_cl_insn
*ip
,
499 unsigned int reg
, enum mips_regclass
class));
500 static int reg_needs_delay
PARAMS ((int));
501 static void append_insn
PARAMS ((char *place
,
502 struct mips_cl_insn
* ip
,
504 bfd_reloc_code_real_type r
,
506 static void mips_no_prev_insn
PARAMS ((void));
507 static void mips_emit_delays
PARAMS ((boolean
));
509 static void macro_build
PARAMS ((char *place
, int *counter
, expressionS
* ep
,
510 const char *name
, const char *fmt
,
513 static void macro_build ();
515 static void mips16_macro_build
PARAMS ((char *, int *, expressionS
*,
516 const char *, const char *,
518 static void macro_build_lui
PARAMS ((char *place
, int *counter
,
519 expressionS
* ep
, int regnum
));
520 static void set_at
PARAMS ((int *counter
, int reg
, int unsignedp
));
521 static void check_absolute_expr
PARAMS ((struct mips_cl_insn
* ip
,
523 static void load_register
PARAMS ((int *, int, expressionS
*, int));
524 static void load_address
PARAMS ((int *counter
, int reg
, expressionS
*ep
));
525 static void macro
PARAMS ((struct mips_cl_insn
* ip
));
526 static void mips16_macro
PARAMS ((struct mips_cl_insn
* ip
));
527 #ifdef LOSING_COMPILER
528 static void macro2
PARAMS ((struct mips_cl_insn
* ip
));
530 static void mips_ip
PARAMS ((char *str
, struct mips_cl_insn
* ip
));
531 static void mips16_ip
PARAMS ((char *str
, struct mips_cl_insn
* ip
));
532 static void mips16_immed
PARAMS ((char *, unsigned int, int, offsetT
, boolean
,
533 boolean
, boolean
, unsigned long *,
534 boolean
*, unsigned short *));
535 static int my_getSmallExpression
PARAMS ((expressionS
* ep
, char *str
));
536 static void my_getExpression
PARAMS ((expressionS
* ep
, char *str
));
537 static symbolS
*get_symbol
PARAMS ((void));
538 static void mips_align
PARAMS ((int to
, int fill
, symbolS
*label
));
539 static void s_align
PARAMS ((int));
540 static void s_change_sec
PARAMS ((int));
541 static void s_cons
PARAMS ((int));
542 static void s_float_cons
PARAMS ((int));
543 static void s_mips_globl
PARAMS ((int));
544 static void s_option
PARAMS ((int));
545 static void s_mipsset
PARAMS ((int));
546 static void s_abicalls
PARAMS ((int));
547 static void s_cpload
PARAMS ((int));
548 static void s_cprestore
PARAMS ((int));
549 static void s_gpword
PARAMS ((int));
550 static void s_cpadd
PARAMS ((int));
551 static void s_insn
PARAMS ((int));
552 static void md_obj_begin
PARAMS ((void));
553 static void md_obj_end
PARAMS ((void));
554 static long get_number
PARAMS ((void));
555 static void s_ent
PARAMS ((int));
556 static void s_mipsend
PARAMS ((int));
557 static void s_file
PARAMS ((int));
558 static int mips16_extended_frag
PARAMS ((fragS
*, asection
*, long));
562 The following pseudo-ops from the Kane and Heinrich MIPS book
563 should be defined here, but are currently unsupported: .alias,
564 .galive, .gjaldef, .gjrlive, .livereg, .noalias.
566 The following pseudo-ops from the Kane and Heinrich MIPS book are
567 specific to the type of debugging information being generated, and
568 should be defined by the object format: .aent, .begin, .bend,
569 .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp,
572 The following pseudo-ops from the Kane and Heinrich MIPS book are
573 not MIPS CPU specific, but are also not specific to the object file
574 format. This file is probably the best place to define them, but
575 they are not currently supported: .asm0, .endr, .lab, .repeat,
576 .struct, .weakext. */
578 static const pseudo_typeS mips_pseudo_table
[] =
580 /* MIPS specific pseudo-ops. */
581 {"option", s_option
, 0},
582 {"set", s_mipsset
, 0},
583 {"rdata", s_change_sec
, 'r'},
584 {"sdata", s_change_sec
, 's'},
585 {"livereg", s_ignore
, 0},
586 {"abicalls", s_abicalls
, 0},
587 {"cpload", s_cpload
, 0},
588 {"cprestore", s_cprestore
, 0},
589 {"gpword", s_gpword
, 0},
590 {"cpadd", s_cpadd
, 0},
593 /* Relatively generic pseudo-ops that happen to be used on MIPS
595 {"asciiz", stringer
, 1},
596 {"bss", s_change_sec
, 'b'},
599 {"dword", s_cons
, 3},
601 /* These pseudo-ops are defined in read.c, but must be overridden
602 here for one reason or another. */
603 {"align", s_align
, 0},
605 {"data", s_change_sec
, 'd'},
606 {"double", s_float_cons
, 'd'},
607 {"float", s_float_cons
, 'f'},
608 {"globl", s_mips_globl
, 0},
609 {"global", s_mips_globl
, 0},
610 {"hword", s_cons
, 1},
615 {"short", s_cons
, 1},
616 {"single", s_float_cons
, 'f'},
617 {"text", s_change_sec
, 't'},
622 static const pseudo_typeS mips_nonecoff_pseudo_table
[] = {
623 /* These pseudo-ops should be defined by the object file format.
624 However, a.out doesn't support them, so we have versions here. */
626 {"bgnb", s_ignore
, 0},
627 {"end", s_mipsend
, 0},
628 {"endb", s_ignore
, 0},
631 {"fmask", s_ignore
, 'F'},
632 {"frame", s_ignore
, 0},
633 {"loc", s_ignore
, 0},
634 {"mask", s_ignore
, 'R'},
635 {"verstamp", s_ignore
, 0},
639 extern void pop_insert
PARAMS ((const pseudo_typeS
*));
644 pop_insert (mips_pseudo_table
);
645 if (! ECOFF_DEBUGGING
)
646 pop_insert (mips_nonecoff_pseudo_table
);
649 /* Symbols labelling the current insn. */
651 struct insn_label_list
653 struct insn_label_list
*next
;
657 static struct insn_label_list
*insn_labels
;
658 static struct insn_label_list
*free_insn_labels
;
660 static void mips_clear_insn_labels
PARAMS ((void));
663 mips_clear_insn_labels ()
665 register struct insn_label_list
**pl
;
667 for (pl
= &free_insn_labels
; *pl
!= NULL
; pl
= &(*pl
)->next
)
673 static char *expr_end
;
675 /* Expressions which appear in instructions. These are set by
678 static expressionS imm_expr
;
679 static expressionS offset_expr
;
681 /* Relocs associated with imm_expr and offset_expr. */
683 static bfd_reloc_code_real_type imm_reloc
;
684 static bfd_reloc_code_real_type offset_reloc
;
686 /* This is set by mips_ip if imm_reloc is an unmatched HI16_S reloc. */
688 static boolean imm_unmatched_hi
;
690 /* These are set by mips16_ip if an explicit extension is used. */
692 static boolean mips16_small
, mips16_ext
;
695 * This function is called once, at assembler startup time. It should
696 * set up all the tables, etc. that the MD part of the assembler will need.
702 register const char *retval
= NULL
;
703 register unsigned int i
= 0;
711 if (strcmp (cpu
+ (sizeof TARGET_CPU
) - 3, "el") == 0)
713 a
= xmalloc (sizeof TARGET_CPU
);
714 strcpy (a
, TARGET_CPU
);
715 a
[(sizeof TARGET_CPU
) - 3] = '\0';
719 if (strcmp (cpu
, "mips") == 0)
725 else if (strcmp (cpu
, "r6000") == 0
726 || strcmp (cpu
, "mips2") == 0)
732 else if (strcmp (cpu
, "mips64") == 0
733 || strcmp (cpu
, "r4000") == 0
734 || strcmp (cpu
, "mips3") == 0)
740 else if (strcmp (cpu
, "r4400") == 0)
746 else if (strcmp (cpu
, "mips64orion") == 0
747 || strcmp (cpu
, "r4600") == 0)
753 else if (strcmp (cpu
, "r4650") == 0)
761 else if (strcmp (cpu
, "mips64vr4300") == 0)
767 else if (strcmp (cpu
, "mips64vr4100") == 0)
775 else if (strcmp (cpu
, "r4010") == 0)
783 else if (strcmp (cpu
, "r5000") == 0
784 || strcmp (cpu
, "mips64vr5000") == 0)
790 /* start-sanitize-r5900 */
791 else if (strcmp (cpu
, "r5900") == 0
792 || strcmp (cpu
, "mips64vr5900") == 0
793 || strcmp (cpu
, "mips64vr5900el") == 0)
801 /* end-sanitize-r5900 */
802 else if (strcmp (cpu
, "r8000") == 0
803 || strcmp (cpu
, "mips4") == 0)
809 else if (strcmp (cpu
, "r10000") == 0)
815 else if (strcmp (cpu
, "mips16") == 0)
819 mips_cpu
= 0; /* FIXME */
834 if (strncmp (TARGET_CPU
, "mips16", sizeof "mips16" - 1) == 0)
849 /* start-sanitize-r5900 */
852 /* end-sanitize-r5900 */
854 if (mips_4010
|| mips_4100
|| mips_cpu
== 4300)
859 if (mips_cpu
== 4300)
864 if (mips_isa
< 2 && mips_trap
)
865 as_bad ("trap exception not supported at ISA 1");
870 ok
= bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, 3000);
873 ok
= bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, 6000);
876 ok
= bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, 4000);
879 ok
= bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, 8000);
883 as_warn ("Could not set architecture and machine");
885 file_mips_isa
= mips_isa
;
887 op_hash
= hash_new ();
889 for (i
= 0; i
< NUMOPCODES
;)
891 const char *name
= mips_opcodes
[i
].name
;
893 retval
= hash_insert (op_hash
, name
, (PTR
) &mips_opcodes
[i
]);
896 fprintf (stderr
, "internal error: can't hash `%s': %s\n",
897 mips_opcodes
[i
].name
, retval
);
898 as_fatal ("Broken assembler. No assembly attempted.");
902 if (mips_opcodes
[i
].pinfo
!= INSN_MACRO
903 && ((mips_opcodes
[i
].match
& mips_opcodes
[i
].mask
)
904 != mips_opcodes
[i
].match
))
906 fprintf (stderr
, "internal error: bad opcode: `%s' \"%s\"\n",
907 mips_opcodes
[i
].name
, mips_opcodes
[i
].args
);
908 as_fatal ("Broken assembler. No assembly attempted.");
912 while ((i
< NUMOPCODES
) && !strcmp (mips_opcodes
[i
].name
, name
));
915 mips16_op_hash
= hash_new ();
918 while (i
< bfd_mips16_num_opcodes
)
920 const char *name
= mips16_opcodes
[i
].name
;
922 retval
= hash_insert (mips16_op_hash
, name
, (PTR
) &mips16_opcodes
[i
]);
924 as_fatal ("internal error: can't hash `%s': %s\n",
925 mips16_opcodes
[i
].name
, retval
);
928 if (mips16_opcodes
[i
].pinfo
!= INSN_MACRO
929 && ((mips16_opcodes
[i
].match
& mips16_opcodes
[i
].mask
)
930 != mips16_opcodes
[i
].match
))
931 as_fatal ("internal error: bad opcode: `%s' \"%s\"\n",
932 mips16_opcodes
[i
].name
, mips16_opcodes
[i
].args
);
935 while (i
< bfd_mips16_num_opcodes
936 && strcmp (mips16_opcodes
[i
].name
, name
) == 0);
939 /* We add all the general register names to the symbol table. This
940 helps us detect invalid uses of them. */
941 for (i
= 0; i
< 32; i
++)
945 sprintf (buf
, "$%d", i
);
946 symbol_table_insert (symbol_new (buf
, reg_section
, i
,
947 &zero_address_frag
));
949 symbol_table_insert (symbol_new ("$fp", reg_section
, FP
,
950 &zero_address_frag
));
951 symbol_table_insert (symbol_new ("$sp", reg_section
, SP
,
952 &zero_address_frag
));
953 symbol_table_insert (symbol_new ("$gp", reg_section
, GP
,
954 &zero_address_frag
));
955 symbol_table_insert (symbol_new ("$at", reg_section
, AT
,
956 &zero_address_frag
));
957 symbol_table_insert (symbol_new ("$kt0", reg_section
, KT0
,
958 &zero_address_frag
));
959 symbol_table_insert (symbol_new ("$kt1", reg_section
, KT1
,
960 &zero_address_frag
));
961 symbol_table_insert (symbol_new ("$pc", reg_section
, -1,
962 &zero_address_frag
));
964 mips_no_prev_insn ();
972 /* set the default alignment for the text section (2**2) */
973 record_alignment (text_section
, 2);
975 if (USE_GLOBAL_POINTER_OPT
)
976 bfd_set_gp_size (stdoutput
, g_switch_value
);
978 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
980 /* On a native system, sections must be aligned to 16 byte
981 boundaries. When configured for an embedded ELF target, we
983 if (strcmp (TARGET_OS
, "elf") != 0)
985 (void) bfd_set_section_alignment (stdoutput
, text_section
, 4);
986 (void) bfd_set_section_alignment (stdoutput
, data_section
, 4);
987 (void) bfd_set_section_alignment (stdoutput
, bss_section
, 4);
990 /* Create a .reginfo section for register masks and a .mdebug
991 section for debugging information. */
1001 /* The ABI says this section should be loaded so that the
1002 running program can access it. However, we don't load it
1003 if we are configured for an embedded target */
1004 flags
= SEC_READONLY
| SEC_DATA
;
1005 if (strcmp (TARGET_OS
, "elf") != 0)
1006 flags
|= SEC_ALLOC
| SEC_LOAD
;
1010 sec
= subseg_new (".reginfo", (subsegT
) 0);
1013 (void) bfd_set_section_flags (stdoutput
, sec
, flags
);
1014 (void) bfd_set_section_alignment (stdoutput
, sec
, 2);
1017 mips_regmask_frag
= frag_more (sizeof (Elf32_External_RegInfo
));
1022 /* The 64-bit ABI uses a .MIPS.options section rather than
1023 .reginfo section. */
1024 sec
= subseg_new (".MIPS.options", (subsegT
) 0);
1025 (void) bfd_set_section_flags (stdoutput
, sec
, flags
);
1026 (void) bfd_set_section_alignment (stdoutput
, sec
, 3);
1029 /* Set up the option header. */
1031 Elf_Internal_Options opthdr
;
1034 opthdr
.kind
= ODK_REGINFO
;
1035 opthdr
.size
= (sizeof (Elf_External_Options
)
1036 + sizeof (Elf64_External_RegInfo
));
1039 f
= frag_more (sizeof (Elf_External_Options
));
1040 bfd_mips_elf_swap_options_out (stdoutput
, &opthdr
,
1041 (Elf_External_Options
*) f
);
1043 mips_regmask_frag
= frag_more (sizeof (Elf64_External_RegInfo
));
1048 if (ECOFF_DEBUGGING
)
1050 sec
= subseg_new (".mdebug", (subsegT
) 0);
1051 (void) bfd_set_section_flags (stdoutput
, sec
,
1052 SEC_HAS_CONTENTS
| SEC_READONLY
);
1053 (void) bfd_set_section_alignment (stdoutput
, sec
, 2);
1056 subseg_set (seg
, subseg
);
1060 if (! ECOFF_DEBUGGING
)
1067 if (! ECOFF_DEBUGGING
)
1075 struct mips_cl_insn insn
;
1077 imm_expr
.X_op
= O_absent
;
1078 imm_reloc
= BFD_RELOC_UNUSED
;
1079 imm_unmatched_hi
= false;
1080 offset_expr
.X_op
= O_absent
;
1081 offset_reloc
= BFD_RELOC_UNUSED
;
1084 mips16_ip (str
, &insn
);
1086 mips_ip (str
, &insn
);
1090 as_bad ("%s `%s'", insn_error
, str
);
1094 if (insn
.insn_mo
->pinfo
== INSN_MACRO
)
1097 mips16_macro (&insn
);
1103 if (imm_expr
.X_op
!= O_absent
)
1104 append_insn ((char *) NULL
, &insn
, &imm_expr
, imm_reloc
,
1106 else if (offset_expr
.X_op
!= O_absent
)
1107 append_insn ((char *) NULL
, &insn
, &offset_expr
, offset_reloc
, false);
1109 append_insn ((char *) NULL
, &insn
, NULL
, BFD_RELOC_UNUSED
, false);
1113 /* See whether instruction IP reads register REG. CLASS is the type
1117 insn_uses_reg (ip
, reg
, class)
1118 struct mips_cl_insn
*ip
;
1120 enum mips_regclass
class;
1122 if (class == MIPS16_REG
)
1125 reg
= mips16_to_32_reg_map
[reg
];
1126 class = MIPS_GR_REG
;
1129 /* Don't report on general register 0, since it never changes. */
1130 if (class == MIPS_GR_REG
&& reg
== 0)
1133 if (class == MIPS_FP_REG
)
1136 /* If we are called with either $f0 or $f1, we must check $f0.
1137 This is not optimal, because it will introduce an unnecessary
1138 NOP between "lwc1 $f0" and "swc1 $f1". To fix this we would
1139 need to distinguish reading both $f0 and $f1 or just one of
1140 them. Note that we don't have to check the other way,
1141 because there is no instruction that sets both $f0 and $f1
1142 and requires a delay. */
1143 if ((ip
->insn_mo
->pinfo
& INSN_READ_FPR_S
)
1144 && (((ip
->insn_opcode
>> OP_SH_FS
) & OP_MASK_FS
)
1145 == (reg
&~ (unsigned) 1)))
1147 if ((ip
->insn_mo
->pinfo
& INSN_READ_FPR_T
)
1148 && (((ip
->insn_opcode
>> OP_SH_FT
) & OP_MASK_FT
)
1149 == (reg
&~ (unsigned) 1)))
1154 if ((ip
->insn_mo
->pinfo
& INSN_READ_GPR_S
)
1155 && ((ip
->insn_opcode
>> OP_SH_RS
) & OP_MASK_RS
) == reg
)
1157 if ((ip
->insn_mo
->pinfo
& INSN_READ_GPR_T
)
1158 && ((ip
->insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
) == reg
)
1163 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_X
)
1164 && ((ip
->insn_opcode
>> MIPS16OP_SH_RX
) & MIPS16OP_MASK_RX
) == reg
)
1166 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_Y
)
1167 && ((ip
->insn_opcode
>> MIPS16OP_SH_RY
) & MIPS16OP_MASK_RY
) == reg
)
1169 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_Z
)
1170 && ((ip
->insn_opcode
>> MIPS16OP_SH_MOVE32Z
)
1171 & MIPS16OP_MASK_MOVE32Z
) == reg
)
1173 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_T
) && reg
== TREG
)
1175 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_SP
) && reg
== SP
)
1177 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_31
) && reg
== RA
)
1179 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_GPR_X
)
1180 && ((ip
->insn_opcode
>> MIPS16OP_SH_REGR32
)
1181 & MIPS16OP_MASK_REGR32
) == reg
)
1188 /* This function returns true if modifying a register requires a
1192 reg_needs_delay (reg
)
1195 unsigned long prev_pinfo
;
1197 prev_pinfo
= prev_insn
.insn_mo
->pinfo
;
1198 if (! mips_noreorder
1200 && ((prev_pinfo
& INSN_LOAD_COPROC_DELAY
)
1202 && (prev_pinfo
& INSN_LOAD_MEMORY_DELAY
))))
1204 /* A load from a coprocessor or from memory. All load
1205 delays delay the use of general register rt for one
1206 instruction on the r3000. The r6000 and r4000 use
1208 know (prev_pinfo
& INSN_WRITE_GPR_T
);
1209 if (reg
== ((prev_insn
.insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
))
1216 /* Output an instruction. PLACE is where to put the instruction; if
1217 it is NULL, this uses frag_more to get room. IP is the instruction
1218 information. ADDRESS_EXPR is an operand of the instruction to be
1219 used with RELOC_TYPE. */
1222 append_insn (place
, ip
, address_expr
, reloc_type
, unmatched_hi
)
1224 struct mips_cl_insn
*ip
;
1225 expressionS
*address_expr
;
1226 bfd_reloc_code_real_type reloc_type
;
1227 boolean unmatched_hi
;
1229 register unsigned long prev_pinfo
, pinfo
;
1234 /* Mark instruction labels in mips16 mode. This permits the linker
1235 to handle them specially, such as generating jalx instructions
1236 when needed. We also make them odd for the duration of the
1237 assembly, in order to generate the right sort of code. We will
1238 make them even in the adjust_symtab routine, while leaving them
1239 marked. This is convenient for the debugger and the
1240 disassembler. The linker knows to make them odd again. */
1243 struct insn_label_list
*l
;
1245 for (l
= insn_labels
; l
!= NULL
; l
= l
->next
)
1248 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
1249 S_SET_OTHER (l
->label
, STO_MIPS16
);
1251 ++l
->label
->sy_value
.X_add_number
;
1255 prev_pinfo
= prev_insn
.insn_mo
->pinfo
;
1256 pinfo
= ip
->insn_mo
->pinfo
;
1258 if (place
== NULL
&& ! mips_noreorder
)
1260 /* If the previous insn required any delay slots, see if we need
1261 to insert a NOP or two. There are eight kinds of possible
1262 hazards, of which an instruction can have at most one type.
1263 (1) a load from memory delay
1264 (2) a load from a coprocessor delay
1265 (3) an unconditional branch delay
1266 (4) a conditional branch delay
1267 (5) a move to coprocessor register delay
1268 (6) a load coprocessor register from memory delay
1269 (7) a coprocessor condition code delay
1270 (8) a HI/LO special register delay
1272 There are a lot of optimizations we could do that we don't.
1273 In particular, we do not, in general, reorder instructions.
1274 If you use gcc with optimization, it will reorder
1275 instructions and generally do much more optimization then we
1276 do here; repeating all that work in the assembler would only
1277 benefit hand written assembly code, and does not seem worth
1280 /* This is how a NOP is emitted. */
1281 #define emit_nop() \
1283 ? md_number_to_chars (frag_more (2), 0x6500, 2) \
1284 : md_number_to_chars (frag_more (4), 0, 4))
1286 /* The previous insn might require a delay slot, depending upon
1287 the contents of the current insn. */
1290 && (((prev_pinfo
& INSN_LOAD_COPROC_DELAY
)
1291 && ! cop_interlocks
)
1293 && (prev_pinfo
& INSN_LOAD_MEMORY_DELAY
))))
1295 /* A load from a coprocessor or from memory. All load
1296 delays delay the use of general register rt for one
1297 instruction on the r3000. The r6000 and r4000 use
1299 know (prev_pinfo
& INSN_WRITE_GPR_T
);
1300 if (mips_optimize
== 0
1301 || insn_uses_reg (ip
,
1302 ((prev_insn
.insn_opcode
>> OP_SH_RT
)
1309 && (((prev_pinfo
& INSN_COPROC_MOVE_DELAY
)
1310 && ! cop_interlocks
)
1312 && (prev_pinfo
& INSN_COPROC_MEMORY_DELAY
))))
1314 /* A generic coprocessor delay. The previous instruction
1315 modified a coprocessor general or control register. If
1316 it modified a control register, we need to avoid any
1317 coprocessor instruction (this is probably not always
1318 required, but it sometimes is). If it modified a general
1319 register, we avoid using that register.
1321 On the r6000 and r4000 loading a coprocessor register
1322 from memory is interlocked, and does not require a delay.
1324 This case is not handled very well. There is no special
1325 knowledge of CP0 handling, and the coprocessors other
1326 than the floating point unit are not distinguished at
1328 if (prev_pinfo
& INSN_WRITE_FPR_T
)
1330 if (mips_optimize
== 0
1331 || insn_uses_reg (ip
,
1332 ((prev_insn
.insn_opcode
>> OP_SH_FT
)
1337 else if (prev_pinfo
& INSN_WRITE_FPR_S
)
1339 if (mips_optimize
== 0
1340 || insn_uses_reg (ip
,
1341 ((prev_insn
.insn_opcode
>> OP_SH_FS
)
1348 /* We don't know exactly what the previous instruction
1349 does. If the current instruction uses a coprocessor
1350 register, we must insert a NOP. If previous
1351 instruction may set the condition codes, and the
1352 current instruction uses them, we must insert two
1354 if (mips_optimize
== 0
1355 || ((prev_pinfo
& INSN_WRITE_COND_CODE
)
1356 && (pinfo
& INSN_READ_COND_CODE
)))
1358 else if (pinfo
& INSN_COP
)
1364 && (prev_pinfo
& INSN_WRITE_COND_CODE
)
1365 && ! cop_interlocks
)
1367 /* The previous instruction sets the coprocessor condition
1368 codes, but does not require a general coprocessor delay
1369 (this means it is a floating point comparison
1370 instruction). If this instruction uses the condition
1371 codes, we need to insert a single NOP. */
1372 if (mips_optimize
== 0
1373 || (pinfo
& INSN_READ_COND_CODE
))
1376 else if (prev_pinfo
& INSN_READ_LO
)
1378 /* The previous instruction reads the LO register; if the
1379 current instruction writes to the LO register, we must
1380 insert two NOPS. Some newer processors have interlocks. */
1382 && (mips_optimize
== 0
1383 || (pinfo
& INSN_WRITE_LO
)))
1386 else if (prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
1388 /* The previous instruction reads the HI register; if the
1389 current instruction writes to the HI register, we must
1390 insert a NOP. Some newer processors have interlocks. */
1392 && (mips_optimize
== 0
1393 || (pinfo
& INSN_WRITE_HI
)))
1397 /* There are two cases which require two intervening
1398 instructions: 1) setting the condition codes using a move to
1399 coprocessor instruction which requires a general coprocessor
1400 delay and then reading the condition codes 2) reading the HI
1401 or LO register and then writing to it (except on processors
1402 which have interlocks). If we are not already emitting a NOP
1403 instruction, we must check for these cases compared to the
1404 instruction previous to the previous instruction. */
1408 && (prev_prev_insn
.insn_mo
->pinfo
& INSN_COPROC_MOVE_DELAY
)
1409 && (prev_prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
)
1410 && (pinfo
& INSN_READ_COND_CODE
)
1411 && ! cop_interlocks
)
1412 || ((prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
)
1413 && (pinfo
& INSN_WRITE_LO
)
1415 || ((prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
1416 && (pinfo
& INSN_WRITE_HI
)
1420 /* If we are being given a nop instruction, don't bother with
1421 one of the nops we would otherwise output. This will only
1422 happen when a nop instruction is used with mips_optimize set
1424 if (nops
> 0 && ip
->insn_opcode
== (mips16
? 0x6500 : 0))
1427 /* Now emit the right number of NOP instructions. */
1431 unsigned long old_frag_offset
;
1433 struct insn_label_list
*l
;
1435 old_frag
= frag_now
;
1436 old_frag_offset
= frag_now_fix ();
1438 for (i
= 0; i
< nops
; i
++)
1443 listing_prev_line ();
1444 /* We may be at the start of a variant frag. In case we
1445 are, make sure there is enough space for the frag
1446 after the frags created by listing_prev_line. The
1447 argument to frag_grow here must be at least as large
1448 as the argument to all other calls to frag_grow in
1449 this file. We don't have to worry about being in the
1450 middle of a variant frag, because the variants insert
1451 all needed nop instructions themselves. */
1455 for (l
= insn_labels
; l
!= NULL
; l
= l
->next
)
1457 assert (S_GET_SEGMENT (l
->label
) == now_seg
);
1458 l
->label
->sy_frag
= frag_now
;
1459 S_SET_VALUE (l
->label
, (valueT
) frag_now_fix ());
1460 /* mips16 text labels are stored as odd. */
1462 ++l
->label
->sy_value
.X_add_number
;
1465 #ifndef NO_ECOFF_DEBUGGING
1466 if (ECOFF_DEBUGGING
)
1467 ecoff_fix_loc (old_frag
, old_frag_offset
);
1472 if (reloc_type
> BFD_RELOC_UNUSED
)
1474 /* We need to set up a variant frag. */
1475 assert (mips16
&& address_expr
!= NULL
);
1476 f
= frag_var (rs_machine_dependent
, 4, 0,
1477 RELAX_MIPS16_ENCODE (reloc_type
- BFD_RELOC_UNUSED
,
1478 mips16_small
, mips16_ext
,
1480 & INSN_UNCOND_BRANCH_DELAY
),
1481 (prev_insn_reloc_type
1482 == BFD_RELOC_MIPS16_JMP
)),
1483 make_expr_symbol (address_expr
), (long) 0,
1486 else if (place
!= NULL
)
1488 else if (mips16
&& ! ip
->use_extend
&& reloc_type
!= BFD_RELOC_MIPS16_JMP
)
1490 /* Make sure there is enough room to swap this instruction with
1491 a following jump instruction. */
1499 && (prev_pinfo
& INSN_UNCOND_BRANCH_DELAY
) != 0)
1500 as_warn ("extended instruction in delay slot");
1506 if (address_expr
!= NULL
&& reloc_type
< BFD_RELOC_UNUSED
)
1508 if (address_expr
->X_op
== O_constant
)
1513 ip
->insn_opcode
|= address_expr
->X_add_number
;
1516 case BFD_RELOC_LO16
:
1517 ip
->insn_opcode
|= address_expr
->X_add_number
& 0xffff;
1520 case BFD_RELOC_MIPS_JMP
:
1521 if ((address_expr
->X_add_number
& 3) != 0)
1522 as_bad ("jump to misaligned address (0x%lx)",
1523 (unsigned long) address_expr
->X_add_number
);
1524 ip
->insn_opcode
|= (address_expr
->X_add_number
>> 2) & 0x3ffffff;
1527 case BFD_RELOC_MIPS16_JMP
:
1528 if ((address_expr
->X_add_number
& 3) != 0)
1529 as_bad ("jump to misaligned address (0x%lx)",
1530 (unsigned long) address_expr
->X_add_number
);
1532 (((address_expr
->X_add_number
& 0x7c0000) << 3)
1533 | ((address_expr
->X_add_number
& 0xf800000) >> 7)
1534 | ((address_expr
->X_add_number
& 0x3fffc) >> 2));
1537 case BFD_RELOC_16_PCREL_S2
:
1547 /* Don't generate a reloc if we are writing into a variant
1551 fixp
= fix_new_exp (frag_now
, f
- frag_now
->fr_literal
, 4,
1553 reloc_type
== BFD_RELOC_16_PCREL_S2
,
1557 struct mips_hi_fixup
*hi_fixup
;
1559 assert (reloc_type
== BFD_RELOC_HI16_S
);
1560 hi_fixup
= ((struct mips_hi_fixup
*)
1561 xmalloc (sizeof (struct mips_hi_fixup
)));
1562 hi_fixup
->fixp
= fixp
;
1563 hi_fixup
->seg
= now_seg
;
1564 hi_fixup
->next
= mips_hi_fixup_list
;
1565 mips_hi_fixup_list
= hi_fixup
;
1572 md_number_to_chars (f
, ip
->insn_opcode
, 4);
1573 else if (reloc_type
== BFD_RELOC_MIPS16_JMP
)
1575 md_number_to_chars (f
, ip
->insn_opcode
>> 16, 2);
1576 md_number_to_chars (f
+ 2, ip
->insn_opcode
& 0xffff, 2);
1582 md_number_to_chars (f
, 0xf000 | ip
->extend
, 2);
1585 md_number_to_chars (f
, ip
->insn_opcode
, 2);
1588 /* Update the register mask information. */
1591 if (pinfo
& INSN_WRITE_GPR_D
)
1592 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
);
1593 if ((pinfo
& (INSN_WRITE_GPR_T
| INSN_READ_GPR_T
)) != 0)
1594 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
);
1595 if (pinfo
& INSN_READ_GPR_S
)
1596 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> OP_SH_RS
) & OP_MASK_RS
);
1597 if (pinfo
& INSN_WRITE_GPR_31
)
1598 mips_gprmask
|= 1 << 31;
1599 if (pinfo
& INSN_WRITE_FPR_D
)
1600 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FD
) & OP_MASK_FD
);
1601 if ((pinfo
& (INSN_WRITE_FPR_S
| INSN_READ_FPR_S
)) != 0)
1602 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FS
) & OP_MASK_FS
);
1603 if ((pinfo
& (INSN_WRITE_FPR_T
| INSN_READ_FPR_T
)) != 0)
1604 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FT
) & OP_MASK_FT
);
1605 if ((pinfo
& INSN_READ_FPR_R
) != 0)
1606 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FR
) & OP_MASK_FR
);
1607 if (pinfo
& INSN_COP
)
1609 /* We don't keep enough information to sort these cases out. */
1611 /* Never set the bit for $0, which is always zero. */
1612 mips_gprmask
&=~ 1 << 0;
1616 if (pinfo
& (MIPS16_INSN_WRITE_X
| MIPS16_INSN_READ_X
))
1617 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_RX
)
1618 & MIPS16OP_MASK_RX
);
1619 if (pinfo
& (MIPS16_INSN_WRITE_Y
| MIPS16_INSN_READ_Y
))
1620 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_RY
)
1621 & MIPS16OP_MASK_RY
);
1622 if (pinfo
& MIPS16_INSN_WRITE_Z
)
1623 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_RZ
)
1624 & MIPS16OP_MASK_RZ
);
1625 if (pinfo
& (MIPS16_INSN_WRITE_T
| MIPS16_INSN_READ_T
))
1626 mips_gprmask
|= 1 << TREG
;
1627 if (pinfo
& (MIPS16_INSN_WRITE_SP
| MIPS16_INSN_READ_SP
))
1628 mips_gprmask
|= 1 << SP
;
1629 if (pinfo
& (MIPS16_INSN_WRITE_31
| MIPS16_INSN_READ_31
))
1630 mips_gprmask
|= 1 << RA
;
1631 if (pinfo
& MIPS16_INSN_WRITE_GPR_Y
)
1632 mips_gprmask
|= 1 << MIPS16OP_EXTRACT_REG32R (ip
->insn_opcode
);
1633 if (pinfo
& MIPS16_INSN_READ_Z
)
1634 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_MOVE32Z
)
1635 & MIPS16OP_MASK_MOVE32Z
);
1636 if (pinfo
& MIPS16_INSN_READ_GPR_X
)
1637 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_REGR32
)
1638 & MIPS16OP_MASK_REGR32
);
1641 if (place
== NULL
&& ! mips_noreorder
)
1643 /* Filling the branch delay slot is more complex. We try to
1644 switch the branch with the previous instruction, which we can
1645 do if the previous instruction does not set up a condition
1646 that the branch tests and if the branch is not itself the
1647 target of any branch. */
1648 if ((pinfo
& INSN_UNCOND_BRANCH_DELAY
)
1649 || (pinfo
& INSN_COND_BRANCH_DELAY
))
1651 if (mips_optimize
< 2
1652 /* If we have seen .set volatile or .set nomove, don't
1655 /* If we had to emit any NOP instructions, then we
1656 already know we can not swap. */
1658 /* If we don't even know the previous insn, we can not
1660 || ! prev_insn_valid
1661 /* If the previous insn is already in a branch delay
1662 slot, then we can not swap. */
1663 || prev_insn_is_delay_slot
1664 /* If the previous previous insn was in a .set
1665 noreorder, we can't swap. Actually, the MIPS
1666 assembler will swap in this situation. However, gcc
1667 configured -with-gnu-as will generate code like
1673 in which we can not swap the bne and INSN. If gcc is
1674 not configured -with-gnu-as, it does not output the
1675 .set pseudo-ops. We don't have to check
1676 prev_insn_unreordered, because prev_insn_valid will
1677 be 0 in that case. We don't want to use
1678 prev_prev_insn_valid, because we do want to be able
1679 to swap at the start of a function. */
1680 || prev_prev_insn_unreordered
1681 /* If the branch is itself the target of a branch, we
1682 can not swap. We cheat on this; all we check for is
1683 whether there is a label on this instruction. If
1684 there are any branches to anything other than a
1685 label, users must use .set noreorder. */
1686 || insn_labels
!= NULL
1687 /* If the previous instruction is in a variant frag, we
1688 can not do the swap. This does not apply to the
1689 mips16, which uses variant frags for different
1692 && prev_insn_frag
->fr_type
== rs_machine_dependent
)
1693 /* If the branch reads the condition codes, we don't
1694 even try to swap, because in the sequence
1699 we can not swap, and I don't feel like handling that
1703 && (pinfo
& INSN_READ_COND_CODE
))
1704 /* We can not swap with an instruction that requires a
1705 delay slot, becase the target of the branch might
1706 interfere with that instruction. */
1710 & (INSN_LOAD_COPROC_DELAY
1711 | INSN_COPROC_MOVE_DELAY
1712 | INSN_WRITE_COND_CODE
)))
1720 & (INSN_LOAD_MEMORY_DELAY
1721 | INSN_COPROC_MEMORY_DELAY
)))
1722 /* We can not swap with a branch instruction. */
1724 & (INSN_UNCOND_BRANCH_DELAY
1725 | INSN_COND_BRANCH_DELAY
1726 | INSN_COND_BRANCH_LIKELY
))
1727 /* We do not swap with a trap instruction, since it
1728 complicates trap handlers to have the trap
1729 instruction be in a delay slot. */
1730 || (prev_pinfo
& INSN_TRAP
)
1731 /* If the branch reads a register that the previous
1732 instruction sets, we can not swap. */
1734 && (prev_pinfo
& INSN_WRITE_GPR_T
)
1735 && insn_uses_reg (ip
,
1736 ((prev_insn
.insn_opcode
>> OP_SH_RT
)
1740 && (prev_pinfo
& INSN_WRITE_GPR_D
)
1741 && insn_uses_reg (ip
,
1742 ((prev_insn
.insn_opcode
>> OP_SH_RD
)
1746 && (((prev_pinfo
& MIPS16_INSN_WRITE_X
)
1747 && insn_uses_reg (ip
,
1748 ((prev_insn
.insn_opcode
1750 & MIPS16OP_MASK_RX
),
1752 || ((prev_pinfo
& MIPS16_INSN_WRITE_Y
)
1753 && insn_uses_reg (ip
,
1754 ((prev_insn
.insn_opcode
1756 & MIPS16OP_MASK_RY
),
1758 || ((prev_pinfo
& MIPS16_INSN_WRITE_Z
)
1759 && insn_uses_reg (ip
,
1760 ((prev_insn
.insn_opcode
1762 & MIPS16OP_MASK_RZ
),
1764 || ((prev_pinfo
& MIPS16_INSN_WRITE_T
)
1765 && insn_uses_reg (ip
, TREG
, MIPS_GR_REG
))
1766 || ((prev_pinfo
& MIPS16_INSN_WRITE_31
)
1767 && insn_uses_reg (ip
, RA
, MIPS_GR_REG
))
1768 || ((prev_pinfo
& MIPS16_INSN_WRITE_GPR_Y
)
1769 && insn_uses_reg (ip
,
1770 MIPS16OP_EXTRACT_REG32R (prev_insn
.
1773 /* If the branch writes a register that the previous
1774 instruction sets, we can not swap (we know that
1775 branches write only to RD or to $31). */
1777 && (prev_pinfo
& INSN_WRITE_GPR_T
)
1778 && (((pinfo
& INSN_WRITE_GPR_D
)
1779 && (((prev_insn
.insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
)
1780 == ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)))
1781 || ((pinfo
& INSN_WRITE_GPR_31
)
1782 && (((prev_insn
.insn_opcode
>> OP_SH_RT
)
1786 && (prev_pinfo
& INSN_WRITE_GPR_D
)
1787 && (((pinfo
& INSN_WRITE_GPR_D
)
1788 && (((prev_insn
.insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)
1789 == ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)))
1790 || ((pinfo
& INSN_WRITE_GPR_31
)
1791 && (((prev_insn
.insn_opcode
>> OP_SH_RD
)
1795 && (pinfo
& MIPS16_INSN_WRITE_31
)
1796 && ((prev_pinfo
& MIPS16_INSN_WRITE_31
)
1797 || ((prev_pinfo
& MIPS16_INSN_WRITE_GPR_Y
)
1798 && (MIPS16OP_EXTRACT_REG32R (prev_insn
.insn_opcode
)
1800 /* If the branch writes a register that the previous
1801 instruction reads, we can not swap (we know that
1802 branches only write to RD or to $31). */
1804 && (pinfo
& INSN_WRITE_GPR_D
)
1805 && insn_uses_reg (&prev_insn
,
1806 ((ip
->insn_opcode
>> OP_SH_RD
)
1810 && (pinfo
& INSN_WRITE_GPR_31
)
1811 && insn_uses_reg (&prev_insn
, 31, MIPS_GR_REG
))
1813 && (pinfo
& MIPS16_INSN_WRITE_31
)
1814 && insn_uses_reg (&prev_insn
, RA
, MIPS_GR_REG
))
1815 /* If we are generating embedded PIC code, the branch
1816 might be expanded into a sequence which uses $at, so
1817 we can't swap with an instruction which reads it. */
1818 || (mips_pic
== EMBEDDED_PIC
1819 && insn_uses_reg (&prev_insn
, AT
, MIPS_GR_REG
))
1820 /* If the previous previous instruction has a load
1821 delay, and sets a register that the branch reads, we
1825 && ((prev_prev_insn
.insn_mo
->pinfo
& INSN_LOAD_COPROC_DELAY
)
1827 && (prev_prev_insn
.insn_mo
->pinfo
1828 & INSN_LOAD_MEMORY_DELAY
)))
1829 && insn_uses_reg (ip
,
1830 ((prev_prev_insn
.insn_opcode
>> OP_SH_RT
)
1833 /* If one instruction sets a condition code and the
1834 other one uses a condition code, we can not swap. */
1835 || ((pinfo
& INSN_READ_COND_CODE
)
1836 && (prev_pinfo
& INSN_WRITE_COND_CODE
))
1837 || ((pinfo
& INSN_WRITE_COND_CODE
)
1838 && (prev_pinfo
& INSN_READ_COND_CODE
))
1839 /* If the previous instruction uses the PC, we can not
1842 && (prev_pinfo
& MIPS16_INSN_READ_PC
))
1843 /* If the previous instruction was extended, we can not
1845 || (mips16
&& prev_insn_extended
)
1846 /* If the previous instruction had a fixup in mips16
1847 mode, we can not swap. This normally means that the
1848 previous instruction was a 4 byte branch anyhow. */
1849 || (mips16
&& prev_insn_fixp
))
1851 /* We could do even better for unconditional branches to
1852 portions of this object file; we could pick up the
1853 instruction at the destination, put it in the delay
1854 slot, and bump the destination address. */
1856 /* Update the previous insn information. */
1857 prev_prev_insn
= *ip
;
1858 prev_insn
.insn_mo
= &dummy_opcode
;
1862 /* It looks like we can actually do the swap. */
1868 prev_f
= prev_insn_frag
->fr_literal
+ prev_insn_where
;
1869 memcpy (temp
, prev_f
, 4);
1870 memcpy (prev_f
, f
, 4);
1871 memcpy (f
, temp
, 4);
1874 prev_insn_fixp
->fx_frag
= frag_now
;
1875 prev_insn_fixp
->fx_where
= f
- frag_now
->fr_literal
;
1879 fixp
->fx_frag
= prev_insn_frag
;
1880 fixp
->fx_where
= prev_insn_where
;
1883 else if (reloc_type
> BFD_RELOC_UNUSED
)
1888 /* We are in mips16 mode, and we have just created a
1889 variant frag. We need to extract the old
1890 instruction from the end of the previous frag,
1891 and add it to a new frag. */
1892 prev_f
= prev_insn_frag
->fr_literal
+ prev_insn_where
;
1893 memcpy (temp
, prev_f
, 2);
1894 prev_insn_frag
->fr_fix
-= 2;
1895 if (prev_insn_frag
->fr_type
== rs_machine_dependent
)
1897 assert (prev_insn_where
== prev_insn_frag
->fr_fix
);
1898 memcpy (prev_f
, prev_f
+ 2, 2);
1900 memcpy (frag_more (2), temp
, 2);
1907 assert (prev_insn_fixp
== NULL
);
1908 prev_f
= prev_insn_frag
->fr_literal
+ prev_insn_where
;
1909 memcpy (temp
, prev_f
, 2);
1910 memcpy (prev_f
, f
, 2);
1911 if (reloc_type
!= BFD_RELOC_MIPS16_JMP
)
1912 memcpy (f
, temp
, 2);
1915 memcpy (f
, f
+ 2, 2);
1916 memcpy (f
+ 2, temp
, 2);
1920 fixp
->fx_frag
= prev_insn_frag
;
1921 fixp
->fx_where
= prev_insn_where
;
1925 /* Update the previous insn information; leave prev_insn
1927 prev_prev_insn
= *ip
;
1929 prev_insn_is_delay_slot
= 1;
1931 /* If that was an unconditional branch, forget the previous
1932 insn information. */
1933 if (pinfo
& INSN_UNCOND_BRANCH_DELAY
)
1935 prev_prev_insn
.insn_mo
= &dummy_opcode
;
1936 prev_insn
.insn_mo
= &dummy_opcode
;
1939 prev_insn_fixp
= NULL
;
1940 prev_insn_reloc_type
= BFD_RELOC_UNUSED
;
1941 prev_insn_extended
= 0;
1943 else if (pinfo
& INSN_COND_BRANCH_LIKELY
)
1945 /* We don't yet optimize a branch likely. What we should do
1946 is look at the target, copy the instruction found there
1947 into the delay slot, and increment the branch to jump to
1948 the next instruction. */
1950 /* Update the previous insn information. */
1951 prev_prev_insn
= *ip
;
1952 prev_insn
.insn_mo
= &dummy_opcode
;
1953 prev_insn_fixp
= NULL
;
1954 prev_insn_reloc_type
= BFD_RELOC_UNUSED
;
1955 prev_insn_extended
= 0;
1959 /* Update the previous insn information. */
1961 prev_prev_insn
.insn_mo
= &dummy_opcode
;
1963 prev_prev_insn
= prev_insn
;
1966 /* Any time we see a branch, we always fill the delay slot
1967 immediately; since this insn is not a branch, we know it
1968 is not in a delay slot. */
1969 prev_insn_is_delay_slot
= 0;
1971 prev_insn_fixp
= fixp
;
1972 prev_insn_reloc_type
= reloc_type
;
1974 prev_insn_extended
= (ip
->use_extend
1975 || reloc_type
> BFD_RELOC_UNUSED
);
1978 prev_prev_insn_unreordered
= prev_insn_unreordered
;
1979 prev_insn_unreordered
= 0;
1980 prev_insn_frag
= frag_now
;
1981 prev_insn_where
= f
- frag_now
->fr_literal
;
1982 prev_insn_valid
= 1;
1984 else if (place
== NULL
)
1986 /* We need to record a bit of information even when we are not
1987 reordering, in order to determine the base address for mips16
1988 PC relative relocs. */
1990 prev_insn_reloc_type
= reloc_type
;
1991 prev_insn_valid
= 1;
1994 /* We just output an insn, so the next one doesn't have a label. */
1995 mips_clear_insn_labels ();
1998 /* This function forgets that there was any previous instruction or
2002 mips_no_prev_insn ()
2004 prev_insn
.insn_mo
= &dummy_opcode
;
2005 prev_prev_insn
.insn_mo
= &dummy_opcode
;
2006 prev_insn_valid
= 0;
2007 prev_insn_is_delay_slot
= 0;
2008 prev_insn_unreordered
= 0;
2009 prev_insn_extended
= 0;
2010 prev_insn_reloc_type
= BFD_RELOC_UNUSED
;
2011 prev_prev_insn_unreordered
= 0;
2012 mips_clear_insn_labels ();
2015 /* This function must be called whenever we turn on noreorder or emit
2016 something other than instructions. It inserts any NOPS which might
2017 be needed by the previous instruction, and clears the information
2018 kept for the previous instructions. The INSNS parameter is true if
2019 instructions are to follow. */
2022 mips_emit_delays (insns
)
2025 if (! mips_noreorder
)
2032 && (! cop_interlocks
2033 && (prev_insn
.insn_mo
->pinfo
2034 & (INSN_LOAD_COPROC_DELAY
2035 | INSN_COPROC_MOVE_DELAY
2036 | INSN_WRITE_COND_CODE
))))
2038 && (prev_insn
.insn_mo
->pinfo
2043 && (prev_insn
.insn_mo
->pinfo
2044 & (INSN_LOAD_MEMORY_DELAY
2045 | INSN_COPROC_MEMORY_DELAY
))))
2050 && (! cop_interlocks
2051 && prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
))
2053 && ((prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
2054 || (prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
))))
2059 && (! cop_interlocks
2060 && prev_prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
))
2062 && ((prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
2063 || (prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
))))
2067 struct insn_label_list
*l
;
2070 for (l
= insn_labels
; l
!= NULL
; l
= l
->next
)
2072 assert (S_GET_SEGMENT (l
->label
) == now_seg
);
2073 l
->label
->sy_frag
= frag_now
;
2074 S_SET_VALUE (l
->label
, (valueT
) frag_now_fix ());
2075 /* mips16 text labels are stored as odd. */
2077 ++l
->label
->sy_value
.X_add_number
;
2082 /* Mark instruction labels in mips16 mode. This permits the linker
2083 to handle them specially, such as generating jalx instructions
2084 when needed. We also make them odd for the duration of the
2085 assembly, in order to generate the right sort of code. We will
2086 make them even in the adjust_symtab routine, while leaving them
2087 marked. This is convenient for the debugger and the
2088 disassembler. The linker knows to make them odd again. */
2089 if (mips16
&& insns
)
2091 struct insn_label_list
*l
;
2093 for (l
= insn_labels
; l
!= NULL
; l
= l
->next
)
2096 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
2097 S_SET_OTHER (l
->label
, STO_MIPS16
);
2099 if ((l
->label
->sy_value
.X_add_number
& 1) == 0)
2100 ++l
->label
->sy_value
.X_add_number
;
2104 mips_no_prev_insn ();
2107 /* Build an instruction created by a macro expansion. This is passed
2108 a pointer to the count of instructions created so far, an
2109 expression, the name of the instruction to build, an operand format
2110 string, and corresponding arguments. */
2114 macro_build (char *place
,
2122 macro_build (place
, counter
, ep
, name
, fmt
, va_alist
)
2131 struct mips_cl_insn insn
;
2132 bfd_reloc_code_real_type r
;
2136 va_start (args
, fmt
);
2142 * If the macro is about to expand into a second instruction,
2143 * print a warning if needed. We need to pass ip as a parameter
2144 * to generate a better warning message here...
2146 if (mips_warn_about_macros
&& place
== NULL
&& *counter
== 1)
2147 as_warn ("Macro instruction expanded into multiple instructions");
2150 *counter
+= 1; /* bump instruction counter */
2154 mips16_macro_build (place
, counter
, ep
, name
, fmt
, args
);
2159 r
= BFD_RELOC_UNUSED
;
2160 insn
.insn_mo
= (struct mips_opcode
*) hash_find (op_hash
, name
);
2161 assert (insn
.insn_mo
);
2162 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
2164 while (strcmp (fmt
, insn
.insn_mo
->args
) != 0
2165 || insn
.insn_mo
->pinfo
== INSN_MACRO
2166 || ((insn
.insn_mo
->pinfo
& INSN_ISA
) == INSN_ISA2
2168 || ((insn
.insn_mo
->pinfo
& INSN_ISA
) == INSN_ISA3
2170 || ((insn
.insn_mo
->pinfo
& INSN_ISA
) == INSN_ISA4
2172 || ((insn
.insn_mo
->pinfo
& INSN_ISA
) == INSN_4650
2174 || ((insn
.insn_mo
->pinfo
& INSN_ISA
) == INSN_4010
2176 || ((insn
.insn_mo
->pinfo
& INSN_ISA
) == INSN_4100
2178 /* start-sanitize-r5900 */
2179 || ((insn
.insn_mo
->pinfo
& INSN_ISA
) == INSN_5900
2181 /* end-sanitize-r5900 */
2185 assert (insn
.insn_mo
->name
);
2186 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
2188 insn
.insn_opcode
= insn
.insn_mo
->match
;
2204 insn
.insn_opcode
|= va_arg (args
, int) << 16;
2210 insn
.insn_opcode
|= va_arg (args
, int) << 16;
2215 insn
.insn_opcode
|= va_arg (args
, int) << 11;
2220 insn
.insn_opcode
|= va_arg (args
, int) << 11;
2227 insn
.insn_opcode
|= va_arg (args
, int) << 6;
2231 insn
.insn_opcode
|= va_arg (args
, int) << 6;
2235 insn
.insn_opcode
|= va_arg (args
, int) << 6;
2242 insn
.insn_opcode
|= va_arg (args
, int) << 21;
2248 r
= (bfd_reloc_code_real_type
) va_arg (args
, int);
2249 assert (r
== BFD_RELOC_MIPS_GPREL
2250 || r
== BFD_RELOC_MIPS_LITERAL
2251 || r
== BFD_RELOC_LO16
2252 || r
== BFD_RELOC_MIPS_GOT16
2253 || r
== BFD_RELOC_MIPS_CALL16
2254 || r
== BFD_RELOC_MIPS_GOT_LO16
2255 || r
== BFD_RELOC_MIPS_CALL_LO16
2256 || (ep
->X_op
== O_subtract
2257 && now_seg
== text_section
2258 && r
== BFD_RELOC_PCREL_LO16
));
2262 r
= (bfd_reloc_code_real_type
) va_arg (args
, int);
2264 && (ep
->X_op
== O_constant
2265 || (ep
->X_op
== O_symbol
2266 && (r
== BFD_RELOC_HI16_S
2267 || r
== BFD_RELOC_HI16
2268 || r
== BFD_RELOC_MIPS_GOT_HI16
2269 || r
== BFD_RELOC_MIPS_CALL_HI16
))
2270 || (ep
->X_op
== O_subtract
2271 && now_seg
== text_section
2272 && r
== BFD_RELOC_PCREL_HI16_S
)));
2273 if (ep
->X_op
== O_constant
)
2275 insn
.insn_opcode
|= (ep
->X_add_number
>> 16) & 0xffff;
2277 r
= BFD_RELOC_UNUSED
;
2282 assert (ep
!= NULL
);
2284 * This allows macro() to pass an immediate expression for
2285 * creating short branches without creating a symbol.
2286 * Note that the expression still might come from the assembly
2287 * input, in which case the value is not checked for range nor
2288 * is a relocation entry generated (yuck).
2290 if (ep
->X_op
== O_constant
)
2292 insn
.insn_opcode
|= (ep
->X_add_number
>> 2) & 0xffff;
2296 r
= BFD_RELOC_16_PCREL_S2
;
2300 assert (ep
!= NULL
);
2301 r
= BFD_RELOC_MIPS_JMP
;
2310 assert (r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
2312 append_insn (place
, &insn
, ep
, r
, false);
2316 mips16_macro_build (place
, counter
, ep
, name
, fmt
, args
)
2324 struct mips_cl_insn insn
;
2325 bfd_reloc_code_real_type r
;
2327 r
= BFD_RELOC_UNUSED
;
2328 insn
.insn_mo
= (struct mips_opcode
*) hash_find (mips16_op_hash
, name
);
2329 assert (insn
.insn_mo
);
2330 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
2332 while (strcmp (fmt
, insn
.insn_mo
->args
) != 0
2333 || insn
.insn_mo
->pinfo
== INSN_MACRO
)
2336 assert (insn
.insn_mo
->name
);
2337 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
2340 insn
.insn_opcode
= insn
.insn_mo
->match
;
2341 insn
.use_extend
= false;
2360 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_RY
;
2365 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_RX
;
2369 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_RZ
;
2373 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_MOVE32Z
;
2383 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_REGR32
;
2390 regno
= va_arg (args
, int);
2391 regno
= ((regno
& 7) << 2) | ((regno
& 0x18) >> 3);
2392 insn
.insn_opcode
|= regno
<< MIPS16OP_SH_REG32R
;
2413 assert (ep
!= NULL
);
2415 if (ep
->X_op
!= O_constant
)
2416 r
= BFD_RELOC_UNUSED
+ c
;
2419 mips16_immed ((char *) NULL
, 0, c
, ep
->X_add_number
, false,
2420 false, false, &insn
.insn_opcode
,
2421 &insn
.use_extend
, &insn
.extend
);
2423 r
= BFD_RELOC_UNUSED
;
2429 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_IMM6
;
2436 assert (r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
2438 append_insn (place
, &insn
, ep
, r
, false);
2442 * Generate a "lui" instruction.
2445 macro_build_lui (place
, counter
, ep
, regnum
)
2451 expressionS high_expr
;
2452 struct mips_cl_insn insn
;
2453 bfd_reloc_code_real_type r
;
2454 CONST
char *name
= "lui";
2455 CONST
char *fmt
= "t,u";
2463 high_expr
.X_op
= O_constant
;
2464 high_expr
.X_add_number
= ep
->X_add_number
;
2467 if (high_expr
.X_op
== O_constant
)
2469 /* we can compute the instruction now without a relocation entry */
2470 if (high_expr
.X_add_number
& 0x8000)
2471 high_expr
.X_add_number
+= 0x10000;
2472 high_expr
.X_add_number
=
2473 ((unsigned long) high_expr
.X_add_number
>> 16) & 0xffff;
2474 r
= BFD_RELOC_UNUSED
;
2478 assert (ep
->X_op
== O_symbol
);
2479 /* _gp_disp is a special case, used from s_cpload. */
2480 assert (mips_pic
== NO_PIC
2481 || strcmp (S_GET_NAME (ep
->X_add_symbol
), "_gp_disp") == 0);
2482 r
= BFD_RELOC_HI16_S
;
2486 * If the macro is about to expand into a second instruction,
2487 * print a warning if needed. We need to pass ip as a parameter
2488 * to generate a better warning message here...
2490 if (mips_warn_about_macros
&& place
== NULL
&& *counter
== 1)
2491 as_warn ("Macro instruction expanded into multiple instructions");
2494 *counter
+= 1; /* bump instruction counter */
2496 insn
.insn_mo
= (struct mips_opcode
*) hash_find (op_hash
, name
);
2497 assert (insn
.insn_mo
);
2498 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
2499 assert (strcmp (fmt
, insn
.insn_mo
->args
) == 0);
2501 insn
.insn_opcode
= insn
.insn_mo
->match
| (regnum
<< OP_SH_RT
);
2502 if (r
== BFD_RELOC_UNUSED
)
2504 insn
.insn_opcode
|= high_expr
.X_add_number
;
2505 append_insn (place
, &insn
, NULL
, r
, false);
2508 append_insn (place
, &insn
, &high_expr
, r
, false);
2512 * Generates code to set the $at register to true (one)
2513 * if reg is less than the immediate expression.
2516 set_at (counter
, reg
, unsignedp
)
2521 if (imm_expr
.X_add_number
>= -0x8000 && imm_expr
.X_add_number
< 0x8000)
2522 macro_build ((char *) NULL
, counter
, &imm_expr
,
2523 unsignedp
? "sltiu" : "slti",
2524 "t,r,j", AT
, reg
, (int) BFD_RELOC_LO16
);
2527 load_register (counter
, AT
, &imm_expr
, 0);
2528 macro_build ((char *) NULL
, counter
, NULL
,
2529 unsignedp
? "sltu" : "slt",
2530 "d,v,t", AT
, reg
, AT
);
2534 /* Warn if an expression is not a constant. */
2537 check_absolute_expr (ip
, ex
)
2538 struct mips_cl_insn
*ip
;
2541 if (ex
->X_op
!= O_constant
)
2542 as_warn ("Instruction %s requires absolute expression", ip
->insn_mo
->name
);
2545 /* Count the leading zeroes by performing a binary chop. This is a
2546 bulky bit of source, but performance is a LOT better for the
2547 majority of values than a simple loop to count the bits:
2548 for (lcnt = 0; (lcnt < 32); lcnt++)
2549 if ((v) & (1 << (31 - lcnt)))
2551 However it is not code size friendly, and the gain will drop a bit
2552 on certain cached systems.
2554 #define COUNT_TOP_ZEROES(v) \
2555 (((v) & ~0xffff) == 0 \
2556 ? ((v) & ~0xff) == 0 \
2557 ? ((v) & ~0xf) == 0 \
2558 ? ((v) & ~0x3) == 0 \
2559 ? ((v) & ~0x1) == 0 \
2564 : ((v) & ~0x7) == 0 \
2567 : ((v) & ~0x3f) == 0 \
2568 ? ((v) & ~0x1f) == 0 \
2571 : ((v) & ~0x7f) == 0 \
2574 : ((v) & ~0xfff) == 0 \
2575 ? ((v) & ~0x3ff) == 0 \
2576 ? ((v) & ~0x1ff) == 0 \
2579 : ((v) & ~0x7ff) == 0 \
2582 : ((v) & ~0x3fff) == 0 \
2583 ? ((v) & ~0x1fff) == 0 \
2586 : ((v) & ~0x7fff) == 0 \
2589 : ((v) & ~0xffffff) == 0 \
2590 ? ((v) & ~0xfffff) == 0 \
2591 ? ((v) & ~0x3ffff) == 0 \
2592 ? ((v) & ~0x1ffff) == 0 \
2595 : ((v) & ~0x7ffff) == 0 \
2598 : ((v) & ~0x3fffff) == 0 \
2599 ? ((v) & ~0x1fffff) == 0 \
2602 : ((v) & ~0x7fffff) == 0 \
2605 : ((v) & ~0xfffffff) == 0 \
2606 ? ((v) & ~0x3ffffff) == 0 \
2607 ? ((v) & ~0x1ffffff) == 0 \
2610 : ((v) & ~0x7ffffff) == 0 \
2613 : ((v) & ~0x3fffffff) == 0 \
2614 ? ((v) & ~0x1fffffff) == 0 \
2617 : ((v) & ~0x7fffffff) == 0 \
2622 * This routine generates the least number of instructions neccessary to load
2623 * an absolute expression value into a register.
2626 load_register (counter
, reg
, ep
, dbl
)
2633 expressionS hi32
, lo32
;
2635 if (ep
->X_op
!= O_big
)
2637 assert (ep
->X_op
== O_constant
);
2638 if (ep
->X_add_number
< 0x8000
2639 && (ep
->X_add_number
>= 0
2640 || (ep
->X_add_number
>= -0x8000
2643 || sizeof (ep
->X_add_number
) > 4))))
2645 /* We can handle 16 bit signed values with an addiu to
2646 $zero. No need to ever use daddiu here, since $zero and
2647 the result are always correct in 32 bit mode. */
2648 macro_build ((char *) NULL
, counter
, ep
, "addiu", "t,r,j", reg
, 0,
2649 (int) BFD_RELOC_LO16
);
2652 else if (ep
->X_add_number
>= 0 && ep
->X_add_number
< 0x10000)
2654 /* We can handle 16 bit unsigned values with an ori to
2656 macro_build ((char *) NULL
, counter
, ep
, "ori", "t,r,i", reg
, 0,
2657 (int) BFD_RELOC_LO16
);
2660 else if ((((ep
->X_add_number
&~ (offsetT
) 0x7fffffff) == 0
2661 || ((ep
->X_add_number
&~ (offsetT
) 0x7fffffff)
2662 == ~ (offsetT
) 0x7fffffff))
2665 || sizeof (ep
->X_add_number
) > 4
2666 || (ep
->X_add_number
& 0x80000000) == 0))
2667 || ((mips_isa
< 3 || !dbl
)
2668 && (ep
->X_add_number
&~ (offsetT
) 0xffffffff) == 0))
2670 /* 32 bit values require an lui. */
2671 macro_build ((char *) NULL
, counter
, ep
, "lui", "t,u", reg
,
2672 (int) BFD_RELOC_HI16
);
2673 if ((ep
->X_add_number
& 0xffff) != 0)
2674 macro_build ((char *) NULL
, counter
, ep
, "ori", "t,r,i", reg
, reg
,
2675 (int) BFD_RELOC_LO16
);
2680 /* The value is larger than 32 bits. */
2684 as_bad ("Number larger than 32 bits");
2685 macro_build ((char *) NULL
, counter
, ep
, "addiu", "t,r,j", reg
, 0,
2686 (int) BFD_RELOC_LO16
);
2690 if (ep
->X_op
!= O_big
)
2693 hi32
.X_add_number
= (valueT
) hi32
.X_add_number
>> 16;
2694 hi32
.X_add_number
= (valueT
) hi32
.X_add_number
>> 16;
2695 hi32
.X_add_number
&= 0xffffffff;
2697 lo32
.X_add_number
&= 0xffffffff;
2701 assert (ep
->X_add_number
> 2);
2702 if (ep
->X_add_number
== 3)
2703 generic_bignum
[3] = 0;
2704 else if (ep
->X_add_number
> 4)
2705 as_bad ("Number larger than 64 bits");
2706 lo32
.X_op
= O_constant
;
2707 lo32
.X_add_number
= generic_bignum
[0] + (generic_bignum
[1] << 16);
2708 hi32
.X_op
= O_constant
;
2709 hi32
.X_add_number
= generic_bignum
[2] + (generic_bignum
[3] << 16);
2712 if (hi32
.X_add_number
== 0)
2717 unsigned long hi
, lo
;
2719 if (hi32
.X_add_number
== 0xffffffff)
2721 if ((lo32
.X_add_number
& 0xffff8000) == 0xffff8000)
2723 macro_build ((char *) NULL
, counter
, &lo32
, "addiu", "t,r,j",
2724 reg
, 0, (int) BFD_RELOC_LO16
);
2727 if (lo32
.X_add_number
& 0x80000000)
2729 macro_build ((char *) NULL
, counter
, &lo32
, "lui", "t,u", reg
,
2730 (int) BFD_RELOC_HI16
);
2731 if (lo32
.X_add_number
& 0xffff)
2732 macro_build ((char *) NULL
, counter
, &lo32
, "ori", "t,r,i",
2733 reg
, reg
, (int) BFD_RELOC_LO16
);
2738 /* Check for 16bit shifted constant. We know that hi32 is
2739 non-zero, so start the mask on the first bit of the hi32
2744 unsigned long himask
, lomask
;
2748 himask
= 0xffff >> (32 - shift
);
2749 lomask
= (0xffff << shift
) & 0xffffffff;
2753 himask
= 0xffff << (shift
- 32);
2756 if ((hi32
.X_add_number
& ~ (offsetT
) himask
) == 0
2757 && (lo32
.X_add_number
& ~ (offsetT
) lomask
) == 0)
2761 tmp
.X_op
= O_constant
;
2763 tmp
.X_add_number
= ((hi32
.X_add_number
<< (32 - shift
))
2764 | (lo32
.X_add_number
>> shift
));
2766 tmp
.X_add_number
= hi32
.X_add_number
>> (shift
- 32);
2767 macro_build ((char *) NULL
, counter
, &tmp
, "ori", "t,r,i", reg
, 0,
2768 (int) BFD_RELOC_LO16
);
2769 macro_build ((char *) NULL
, counter
, NULL
,
2770 (shift
>= 32) ? "dsll32" : "dsll",
2772 (shift
>= 32) ? shift
- 32 : shift
);
2776 } while (shift
<= (64 - 16));
2778 /* Find the bit number of the lowest one bit, and store the
2779 shifted value in hi/lo. */
2780 hi
= (unsigned long) (hi32
.X_add_number
& 0xffffffff);
2781 lo
= (unsigned long) (lo32
.X_add_number
& 0xffffffff);
2785 while ((lo
& 1) == 0)
2790 lo
|= (hi
& (((unsigned long) 1 << bit
) - 1)) << (32 - bit
);
2796 while ((hi
& 1) == 0)
2805 /* Optimize if the shifted value is a (power of 2) - 1. */
2806 if ((hi
== 0 && ((lo
+ 1) & lo
) == 0)
2807 || (lo
== 0xffffffff && ((hi
+ 1) & hi
) == 0))
2809 shift
= COUNT_TOP_ZEROES ((unsigned int) hi32
.X_add_number
);
2814 /* This instruction will set the register to be all
2816 tmp
.X_op
= O_constant
;
2817 tmp
.X_add_number
= (offsetT
) -1;
2818 macro_build ((char *) NULL
, counter
, &tmp
, "addiu", "t,r,j",
2819 reg
, 0, (int) BFD_RELOC_LO16
);
2823 macro_build ((char *) NULL
, counter
, NULL
,
2824 (bit
>= 32) ? "dsll32" : "dsll",
2826 (bit
>= 32) ? bit
- 32 : bit
);
2828 macro_build ((char *) NULL
, counter
, NULL
,
2829 (shift
>= 32) ? "dsrl32" : "dsrl",
2831 (shift
>= 32) ? shift
- 32 : shift
);
2836 /* Sign extend hi32 before calling load_register, because we can
2837 generally get better code when we load a sign extended value. */
2838 if ((hi32
.X_add_number
& 0x80000000) != 0)
2839 hi32
.X_add_number
|= ~ (offsetT
) 0xffffffff;
2840 load_register (counter
, reg
, &hi32
, 0);
2843 if ((lo32
.X_add_number
& 0xffff0000) == 0)
2847 macro_build ((char *) NULL
, counter
, NULL
, "dsll32", "d,w,<", reg
,
2856 if ((freg
== 0) && (lo32
.X_add_number
== 0xffffffff))
2858 macro_build ((char *) NULL
, counter
, &lo32
, "lui", "t,u", reg
,
2859 (int) BFD_RELOC_HI16
);
2860 macro_build ((char *) NULL
, counter
, NULL
, "dsrl32", "d,w,<", reg
,
2867 macro_build ((char *) NULL
, counter
, NULL
, "dsll", "d,w,<", reg
,
2872 mid16
.X_add_number
>>= 16;
2873 macro_build ((char *) NULL
, counter
, &mid16
, "ori", "t,r,i", reg
,
2874 freg
, (int) BFD_RELOC_LO16
);
2875 macro_build ((char *) NULL
, counter
, NULL
, "dsll", "d,w,<", reg
,
2879 if ((lo32
.X_add_number
& 0xffff) != 0)
2880 macro_build ((char *) NULL
, counter
, &lo32
, "ori", "t,r,i", reg
, freg
,
2881 (int) BFD_RELOC_LO16
);
2884 /* Load an address into a register. */
2887 load_address (counter
, reg
, ep
)
2894 if (ep
->X_op
!= O_constant
2895 && ep
->X_op
!= O_symbol
)
2897 as_bad ("expression too complex");
2898 ep
->X_op
= O_constant
;
2901 if (ep
->X_op
== O_constant
)
2903 load_register (counter
, reg
, ep
, 0);
2907 if (mips_pic
== NO_PIC
)
2909 /* If this is a reference to a GP relative symbol, we want
2910 addiu $reg,$gp,<sym> (BFD_RELOC_MIPS_GPREL)
2912 lui $reg,<sym> (BFD_RELOC_HI16_S)
2913 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
2914 If we have an addend, we always use the latter form. */
2915 if ((valueT
) ep
->X_add_number
>= MAX_GPREL_OFFSET
2916 || nopic_need_relax (ep
->X_add_symbol
))
2921 macro_build ((char *) NULL
, counter
, ep
,
2922 mips_isa
< 3 ? "addiu" : "daddiu",
2923 "t,r,j", reg
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
2924 p
= frag_var (rs_machine_dependent
, 8, 0,
2925 RELAX_ENCODE (4, 8, 0, 4, 0, mips_warn_about_macros
),
2926 ep
->X_add_symbol
, (long) 0, (char *) NULL
);
2928 macro_build_lui (p
, counter
, ep
, reg
);
2931 macro_build (p
, counter
, ep
,
2932 mips_isa
< 3 ? "addiu" : "daddiu",
2933 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
2935 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
2939 /* If this is a reference to an external symbol, we want
2940 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
2942 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
2944 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
2945 If there is a constant, it must be added in after. */
2946 ex
.X_add_number
= ep
->X_add_number
;
2947 ep
->X_add_number
= 0;
2949 macro_build ((char *) NULL
, counter
, ep
,
2950 mips_isa
< 3 ? "lw" : "ld",
2951 "t,o(b)", reg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
2952 macro_build ((char *) NULL
, counter
, (expressionS
*) NULL
, "nop", "");
2953 p
= frag_var (rs_machine_dependent
, 4, 0,
2954 RELAX_ENCODE (0, 4, -8, 0, 0, mips_warn_about_macros
),
2955 ep
->X_add_symbol
, (long) 0, (char *) NULL
);
2956 macro_build (p
, counter
, ep
,
2957 mips_isa
< 3 ? "addiu" : "daddiu",
2958 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
2959 if (ex
.X_add_number
!= 0)
2961 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
2962 as_bad ("PIC code offset overflow (max 16 signed bits)");
2963 ex
.X_op
= O_constant
;
2964 macro_build ((char *) NULL
, counter
, &ex
,
2965 mips_isa
< 3 ? "addiu" : "daddiu",
2966 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
2969 else if (mips_pic
== SVR4_PIC
)
2974 /* This is the large GOT case. If this is a reference to an
2975 external symbol, we want
2976 lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
2978 lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16)
2979 Otherwise, for a reference to a local symbol, we want
2980 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
2982 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
2983 If there is a constant, it must be added in after. */
2984 ex
.X_add_number
= ep
->X_add_number
;
2985 ep
->X_add_number
= 0;
2986 if (reg_needs_delay (GP
))
2991 macro_build ((char *) NULL
, counter
, ep
, "lui", "t,u", reg
,
2992 (int) BFD_RELOC_MIPS_GOT_HI16
);
2993 macro_build ((char *) NULL
, counter
, (expressionS
*) NULL
,
2994 mips_isa
< 3 ? "addu" : "daddu",
2995 "d,v,t", reg
, reg
, GP
);
2996 macro_build ((char *) NULL
, counter
, ep
,
2997 mips_isa
< 3 ? "lw" : "ld",
2998 "t,o(b)", reg
, (int) BFD_RELOC_MIPS_GOT_LO16
, reg
);
2999 p
= frag_var (rs_machine_dependent
, 12 + off
, 0,
3000 RELAX_ENCODE (12, 12 + off
, off
, 8 + off
, 0,
3001 mips_warn_about_macros
),
3002 ep
->X_add_symbol
, (long) 0, (char *) NULL
);
3005 /* We need a nop before loading from $gp. This special
3006 check is required because the lui which starts the main
3007 instruction stream does not refer to $gp, and so will not
3008 insert the nop which may be required. */
3009 macro_build (p
, counter
, (expressionS
*) NULL
, "nop", "");
3012 macro_build (p
, counter
, ep
,
3013 mips_isa
< 3 ? "lw" : "ld",
3014 "t,o(b)", reg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
3016 macro_build (p
, counter
, (expressionS
*) NULL
, "nop", "");
3018 macro_build (p
, counter
, ep
,
3019 mips_isa
< 3 ? "addiu" : "daddiu",
3020 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
3021 if (ex
.X_add_number
!= 0)
3023 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
3024 as_bad ("PIC code offset overflow (max 16 signed bits)");
3025 ex
.X_op
= O_constant
;
3026 macro_build ((char *) NULL
, counter
, &ex
,
3027 mips_isa
< 3 ? "addiu" : "daddiu",
3028 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
3031 else if (mips_pic
== EMBEDDED_PIC
)
3034 addiu $reg,$gp,<sym> (BFD_RELOC_MIPS_GPREL)
3036 macro_build ((char *) NULL
, counter
, ep
,
3037 mips_isa
< 3 ? "addiu" : "daddiu",
3038 "t,r,j", reg
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
3046 * This routine implements the seemingly endless macro or synthesized
3047 * instructions and addressing modes in the mips assembly language. Many
3048 * of these macros are simple and are similar to each other. These could
3049 * probably be handled by some kind of table or grammer aproach instead of
3050 * this verbose method. Others are not simple macros but are more like
3051 * optimizing code generation.
3052 * One interesting optimization is when several store macros appear
3053 * consecutivly that would load AT with the upper half of the same address.
3054 * The ensuing load upper instructions are ommited. This implies some kind
3055 * of global optimization. We currently only optimize within a single macro.
3056 * For many of the load and store macros if the address is specified as a
3057 * constant expression in the first 64k of memory (ie ld $2,0x4000c) we
3058 * first load register 'at' with zero and use it as the base register. The
3059 * mips assembler simply uses register $zero. Just one tiny optimization
3064 struct mips_cl_insn
*ip
;
3066 register int treg
, sreg
, dreg
, breg
;
3081 bfd_reloc_code_real_type r
;
3083 int hold_mips_optimize
;
3087 treg
= (ip
->insn_opcode
>> 16) & 0x1f;
3088 dreg
= (ip
->insn_opcode
>> 11) & 0x1f;
3089 sreg
= breg
= (ip
->insn_opcode
>> 21) & 0x1f;
3090 mask
= ip
->insn_mo
->mask
;
3092 expr1
.X_op
= O_constant
;
3093 expr1
.X_op_symbol
= NULL
;
3094 expr1
.X_add_symbol
= NULL
;
3095 expr1
.X_add_number
= 1;
3107 mips_emit_delays (true);
3109 mips_any_noreorder
= 1;
3111 expr1
.X_add_number
= 8;
3112 macro_build ((char *) NULL
, &icnt
, &expr1
, "bgez", "s,p", sreg
);
3114 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
3116 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
, sreg
, 0);
3117 macro_build ((char *) NULL
, &icnt
, NULL
,
3118 dbl
? "dsub" : "sub",
3119 "d,v,t", dreg
, 0, sreg
);
3142 if (imm_expr
.X_add_number
>= -0x8000 && imm_expr
.X_add_number
< 0x8000)
3144 macro_build ((char *) NULL
, &icnt
, &imm_expr
, s
, "t,r,j", treg
, sreg
,
3145 (int) BFD_RELOC_LO16
);
3148 load_register (&icnt
, AT
, &imm_expr
, dbl
);
3149 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "d,v,t", treg
, sreg
, AT
);
3168 if (imm_expr
.X_add_number
>= 0 && imm_expr
.X_add_number
< 0x10000)
3170 if (mask
!= M_NOR_I
)
3171 macro_build ((char *) NULL
, &icnt
, &imm_expr
, s
, "t,r,i", treg
,
3172 sreg
, (int) BFD_RELOC_LO16
);
3175 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "ori", "t,r,i",
3176 treg
, sreg
, (int) BFD_RELOC_LO16
);
3177 macro_build ((char *) NULL
, &icnt
, NULL
, "nor", "d,v,t",
3183 load_register (&icnt
, AT
, &imm_expr
, 0);
3184 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "d,v,t", treg
, sreg
, AT
);
3201 if (imm_expr
.X_add_number
== 0)
3203 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "s,t,p", sreg
,
3207 load_register (&icnt
, AT
, &imm_expr
, 0);
3208 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "s,t,p", sreg
, AT
);
3216 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3217 likely
? "bgezl" : "bgez",
3223 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3224 likely
? "blezl" : "blez",
3228 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", AT
, sreg
, treg
);
3229 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3230 likely
? "beql" : "beq",
3237 /* check for > max integer */
3238 maxnum
= 0x7fffffff;
3246 if (imm_expr
.X_add_number
>= maxnum
3247 && (mips_isa
< 3 || sizeof (maxnum
) > 4))
3250 /* result is always false */
3253 as_warn ("Branch %s is always false (nop)", ip
->insn_mo
->name
);
3254 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
3258 as_warn ("Branch likely %s is always false", ip
->insn_mo
->name
);
3259 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "bnel",
3264 imm_expr
.X_add_number
++;
3268 if (mask
== M_BGEL_I
)
3270 if (imm_expr
.X_add_number
== 0)
3272 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3273 likely
? "bgezl" : "bgez",
3277 if (imm_expr
.X_add_number
== 1)
3279 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3280 likely
? "bgtzl" : "bgtz",
3284 maxnum
= 0x7fffffff;
3292 maxnum
= - maxnum
- 1;
3293 if (imm_expr
.X_add_number
<= maxnum
3294 && (mips_isa
< 3 || sizeof (maxnum
) > 4))
3297 /* result is always true */
3298 as_warn ("Branch %s is always true", ip
->insn_mo
->name
);
3299 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "b", "p");
3302 set_at (&icnt
, sreg
, 0);
3303 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3304 likely
? "beql" : "beq",
3315 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3316 likely
? "beql" : "beq",
3320 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", AT
, sreg
,
3322 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3323 likely
? "beql" : "beq",
3330 if (sreg
== 0 || imm_expr
.X_add_number
== -1)
3332 imm_expr
.X_add_number
++;
3336 if (mask
== M_BGEUL_I
)
3338 if (imm_expr
.X_add_number
== 0)
3340 if (imm_expr
.X_add_number
== 1)
3342 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3343 likely
? "bnel" : "bne",
3347 set_at (&icnt
, sreg
, 1);
3348 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3349 likely
? "beql" : "beq",
3358 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3359 likely
? "bgtzl" : "bgtz",
3365 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3366 likely
? "bltzl" : "bltz",
3370 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", AT
, treg
, sreg
);
3371 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3372 likely
? "bnel" : "bne",
3381 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3382 likely
? "bnel" : "bne",
3388 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", AT
, treg
,
3390 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3391 likely
? "bnel" : "bne",
3400 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3401 likely
? "blezl" : "blez",
3407 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3408 likely
? "bgezl" : "bgez",
3412 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", AT
, treg
, sreg
);
3413 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3414 likely
? "beql" : "beq",
3421 maxnum
= 0x7fffffff;
3429 if (imm_expr
.X_add_number
>= maxnum
3430 && (mips_isa
< 3 || sizeof (maxnum
) > 4))
3432 imm_expr
.X_add_number
++;
3436 if (mask
== M_BLTL_I
)
3438 if (imm_expr
.X_add_number
== 0)
3440 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3441 likely
? "bltzl" : "bltz",
3445 if (imm_expr
.X_add_number
== 1)
3447 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3448 likely
? "blezl" : "blez",
3452 set_at (&icnt
, sreg
, 0);
3453 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3454 likely
? "bnel" : "bne",
3463 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3464 likely
? "beql" : "beq",
3470 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", AT
, treg
,
3472 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3473 likely
? "beql" : "beq",
3480 if (sreg
== 0 || imm_expr
.X_add_number
== -1)
3482 imm_expr
.X_add_number
++;
3486 if (mask
== M_BLTUL_I
)
3488 if (imm_expr
.X_add_number
== 0)
3490 if (imm_expr
.X_add_number
== 1)
3492 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3493 likely
? "beql" : "beq",
3497 set_at (&icnt
, sreg
, 1);
3498 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3499 likely
? "bnel" : "bne",
3508 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3509 likely
? "bltzl" : "bltz",
3515 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3516 likely
? "bgtzl" : "bgtz",
3520 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", AT
, sreg
, treg
);
3521 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3522 likely
? "bnel" : "bne",
3533 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3534 likely
? "bnel" : "bne",
3538 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", AT
, sreg
,
3540 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3541 likely
? "bnel" : "bne",
3557 as_warn ("Divide by zero.");
3559 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", 0, 0);
3561 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 7);
3565 mips_emit_delays (true);
3567 mips_any_noreorder
= 1;
3568 macro_build ((char *) NULL
, &icnt
, NULL
,
3569 dbl
? "ddiv" : "div",
3570 "z,s,t", sreg
, treg
);
3572 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", treg
, 0);
3575 expr1
.X_add_number
= 8;
3576 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", treg
, 0);
3577 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
3578 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 7);
3580 expr1
.X_add_number
= -1;
3581 macro_build ((char *) NULL
, &icnt
, &expr1
,
3582 dbl
? "daddiu" : "addiu",
3583 "t,r,j", AT
, 0, (int) BFD_RELOC_LO16
);
3584 expr1
.X_add_number
= mips_trap
? (dbl
? 12 : 8) : (dbl
? 20 : 16);
3585 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", treg
, AT
);
3588 expr1
.X_add_number
= 1;
3589 macro_build ((char *) NULL
, &icnt
, &expr1
, "daddiu", "t,r,j", AT
, 0,
3590 (int) BFD_RELOC_LO16
);
3591 macro_build ((char *) NULL
, &icnt
, NULL
, "dsll32", "d,w,<", AT
, AT
,
3596 expr1
.X_add_number
= 0x80000000;
3597 macro_build ((char *) NULL
, &icnt
, &expr1
, "lui", "t,u", AT
,
3598 (int) BFD_RELOC_HI16
);
3601 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", sreg
, AT
);
3604 expr1
.X_add_number
= 8;
3605 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", sreg
, AT
);
3606 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
3607 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 6);
3610 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d", dreg
);
3649 if (imm_expr
.X_add_number
== 0)
3651 as_warn ("Divide by zero.");
3653 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", 0, 0);
3655 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 7);
3658 if (imm_expr
.X_add_number
== 1)
3660 if (strcmp (s2
, "mflo") == 0)
3661 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
,
3664 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
, 0);
3667 if (imm_expr
.X_add_number
== -1
3668 && s
[strlen (s
) - 1] != 'u')
3670 if (strcmp (s2
, "mflo") == 0)
3673 macro_build ((char *) NULL
, &icnt
, NULL
, "dneg", "d,w", dreg
,
3676 macro_build ((char *) NULL
, &icnt
, NULL
, "neg", "d,w", dreg
,
3680 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
, 0);
3684 load_register (&icnt
, AT
, &imm_expr
, dbl
);
3685 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "z,s,t", sreg
, AT
);
3686 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "d", dreg
);
3705 mips_emit_delays (true);
3707 mips_any_noreorder
= 1;
3708 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "z,s,t", sreg
, treg
);
3710 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", treg
, 0);
3713 expr1
.X_add_number
= 8;
3714 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", treg
, 0);
3715 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
3716 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 7);
3719 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "d", dreg
);
3725 /* Load the address of a symbol into a register. If breg is not
3726 zero, we then add a base register to it. */
3728 /* When generating embedded PIC code, we permit expressions of
3731 where bar is an address in the .text section. These are used
3732 when getting the addresses of functions. We don't permit
3733 X_add_number to be non-zero, because if the symbol is
3734 external the relaxing code needs to know that any addend is
3735 purely the offset to X_op_symbol. */
3736 if (mips_pic
== EMBEDDED_PIC
3737 && offset_expr
.X_op
== O_subtract
3738 && now_seg
== text_section
3739 && (offset_expr
.X_op_symbol
->sy_value
.X_op
== O_constant
3740 ? S_GET_SEGMENT (offset_expr
.X_op_symbol
) == text_section
3741 : (offset_expr
.X_op_symbol
->sy_value
.X_op
== O_symbol
3742 && (S_GET_SEGMENT (offset_expr
.X_op_symbol
3743 ->sy_value
.X_add_symbol
)
3746 && offset_expr
.X_add_number
== 0)
3748 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
3749 treg
, (int) BFD_RELOC_PCREL_HI16_S
);
3750 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3751 mips_isa
< 3 ? "addiu" : "daddiu",
3752 "t,r,j", treg
, treg
, (int) BFD_RELOC_PCREL_LO16
);
3756 if (offset_expr
.X_op
!= O_symbol
3757 && offset_expr
.X_op
!= O_constant
)
3759 as_bad ("expression too complex");
3760 offset_expr
.X_op
= O_constant
;
3774 if (offset_expr
.X_op
== O_constant
)
3775 load_register (&icnt
, tempreg
, &offset_expr
, dbl
);
3776 else if (mips_pic
== NO_PIC
)
3778 /* If this is a reference to an GP relative symbol, we want
3779 addiu $tempreg,$gp,<sym> (BFD_RELOC_MIPS_GPREL)
3781 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
3782 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
3783 If we have a constant, we need two instructions anyhow,
3784 so we may as well always use the latter form. */
3785 if ((valueT
) offset_expr
.X_add_number
>= MAX_GPREL_OFFSET
3786 || nopic_need_relax (offset_expr
.X_add_symbol
))
3791 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3792 mips_isa
< 3 ? "addiu" : "daddiu",
3793 "t,r,j", tempreg
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
3794 p
= frag_var (rs_machine_dependent
, 8, 0,
3795 RELAX_ENCODE (4, 8, 0, 4, 0,
3796 mips_warn_about_macros
),
3797 offset_expr
.X_add_symbol
, (long) 0,
3800 macro_build_lui (p
, &icnt
, &offset_expr
, tempreg
);
3803 macro_build (p
, &icnt
, &offset_expr
,
3804 mips_isa
< 3 ? "addiu" : "daddiu",
3805 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
3807 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
3809 /* If this is a reference to an external symbol, and there
3810 is no constant, we want
3811 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3812 For a local symbol, we want
3813 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3815 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
3817 If we have a small constant, and this is a reference to
3818 an external symbol, we want
3819 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3821 addiu $tempreg,$tempreg,<constant>
3822 For a local symbol, we want the same instruction
3823 sequence, but we output a BFD_RELOC_LO16 reloc on the
3826 If we have a large constant, and this is a reference to
3827 an external symbol, we want
3828 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3829 lui $at,<hiconstant>
3830 addiu $at,$at,<loconstant>
3831 addu $tempreg,$tempreg,$at
3832 For a local symbol, we want the same instruction
3833 sequence, but we output a BFD_RELOC_LO16 reloc on the
3834 addiu instruction. */
3835 expr1
.X_add_number
= offset_expr
.X_add_number
;
3836 offset_expr
.X_add_number
= 0;
3838 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3840 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
3841 if (expr1
.X_add_number
== 0)
3849 /* We're going to put in an addu instruction using
3850 tempreg, so we may as well insert the nop right
3852 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3856 p
= frag_var (rs_machine_dependent
, 8 - off
, 0,
3857 RELAX_ENCODE (0, 8 - off
, -4 - off
, 4 - off
, 0,
3859 ? mips_warn_about_macros
3861 offset_expr
.X_add_symbol
, (long) 0,
3865 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
3868 macro_build (p
, &icnt
, &expr1
,
3869 mips_isa
< 3 ? "addiu" : "daddiu",
3870 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
3871 /* FIXME: If breg == 0, and the next instruction uses
3872 $tempreg, then if this variant case is used an extra
3873 nop will be generated. */
3875 else if (expr1
.X_add_number
>= -0x8000
3876 && expr1
.X_add_number
< 0x8000)
3878 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3880 macro_build ((char *) NULL
, &icnt
, &expr1
,
3881 mips_isa
< 3 ? "addiu" : "daddiu",
3882 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
3883 (void) frag_var (rs_machine_dependent
, 0, 0,
3884 RELAX_ENCODE (0, 0, -12, -4, 0, 0),
3885 offset_expr
.X_add_symbol
, (long) 0,
3892 /* If we are going to add in a base register, and the
3893 target register and the base register are the same,
3894 then we are using AT as a temporary register. Since
3895 we want to load the constant into AT, we add our
3896 current AT (from the global offset table) and the
3897 register into the register now, and pretend we were
3898 not using a base register. */
3903 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3905 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3906 mips_isa
< 3 ? "addu" : "daddu",
3907 "d,v,t", treg
, AT
, breg
);
3913 /* Set mips_optimize around the lui instruction to avoid
3914 inserting an unnecessary nop after the lw. */
3915 hold_mips_optimize
= mips_optimize
;
3917 macro_build_lui ((char *) NULL
, &icnt
, &expr1
, AT
);
3918 mips_optimize
= hold_mips_optimize
;
3920 macro_build ((char *) NULL
, &icnt
, &expr1
,
3921 mips_isa
< 3 ? "addiu" : "daddiu",
3922 "t,r,j", AT
, AT
, (int) BFD_RELOC_LO16
);
3923 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3924 mips_isa
< 3 ? "addu" : "daddu",
3925 "d,v,t", tempreg
, tempreg
, AT
);
3926 (void) frag_var (rs_machine_dependent
, 0, 0,
3927 RELAX_ENCODE (0, 0, -16 + off1
, -8, 0, 0),
3928 offset_expr
.X_add_symbol
, (long) 0,
3933 else if (mips_pic
== SVR4_PIC
)
3937 /* This is the large GOT case. If this is a reference to an
3938 external symbol, and there is no constant, we want
3939 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
3940 addu $tempreg,$tempreg,$gp
3941 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
3942 For a local symbol, we want
3943 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3945 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
3947 If we have a small constant, and this is a reference to
3948 an external symbol, we want
3949 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
3950 addu $tempreg,$tempreg,$gp
3951 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
3953 addiu $tempreg,$tempreg,<constant>
3954 For a local symbol, we want
3955 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3957 addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16)
3959 If we have a large constant, and this is a reference to
3960 an external symbol, we want
3961 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
3962 addu $tempreg,$tempreg,$gp
3963 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
3964 lui $at,<hiconstant>
3965 addiu $at,$at,<loconstant>
3966 addu $tempreg,$tempreg,$at
3967 For a local symbol, we want
3968 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3969 lui $at,<hiconstant>
3970 addiu $at,$at,<loconstant> (BFD_RELOC_LO16)
3971 addu $tempreg,$tempreg,$at
3973 expr1
.X_add_number
= offset_expr
.X_add_number
;
3974 offset_expr
.X_add_number
= 0;
3976 if (reg_needs_delay (GP
))
3980 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
3981 tempreg
, (int) BFD_RELOC_MIPS_GOT_HI16
);
3982 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3983 mips_isa
< 3 ? "addu" : "daddu",
3984 "d,v,t", tempreg
, tempreg
, GP
);
3985 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3987 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT_LO16
,
3989 if (expr1
.X_add_number
== 0)
3997 /* We're going to put in an addu instruction using
3998 tempreg, so we may as well insert the nop right
4000 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4005 p
= frag_var (rs_machine_dependent
, 12 + gpdel
, 0,
4006 RELAX_ENCODE (12 + off
, 12 + gpdel
, gpdel
,
4009 ? mips_warn_about_macros
4011 offset_expr
.X_add_symbol
, (long) 0,
4014 else if (expr1
.X_add_number
>= -0x8000
4015 && expr1
.X_add_number
< 0x8000)
4017 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4019 macro_build ((char *) NULL
, &icnt
, &expr1
,
4020 mips_isa
< 3 ? "addiu" : "daddiu",
4021 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
4023 p
= frag_var (rs_machine_dependent
, 12 + gpdel
, 0,
4024 RELAX_ENCODE (20, 12 + gpdel
, gpdel
, 8 + gpdel
, 0,
4026 ? mips_warn_about_macros
4028 offset_expr
.X_add_symbol
, (long) 0,
4035 /* If we are going to add in a base register, and the
4036 target register and the base register are the same,
4037 then we are using AT as a temporary register. Since
4038 we want to load the constant into AT, we add our
4039 current AT (from the global offset table) and the
4040 register into the register now, and pretend we were
4041 not using a base register. */
4049 assert (tempreg
== AT
);
4050 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4052 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4053 mips_isa
< 3 ? "addu" : "daddu",
4054 "d,v,t", treg
, AT
, breg
);
4059 /* Set mips_optimize around the lui instruction to avoid
4060 inserting an unnecessary nop after the lw. */
4061 hold_mips_optimize
= mips_optimize
;
4063 macro_build_lui ((char *) NULL
, &icnt
, &expr1
, AT
);
4064 mips_optimize
= hold_mips_optimize
;
4066 macro_build ((char *) NULL
, &icnt
, &expr1
,
4067 mips_isa
< 3 ? "addiu" : "daddiu",
4068 "t,r,j", AT
, AT
, (int) BFD_RELOC_LO16
);
4069 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4070 mips_isa
< 3 ? "addu" : "daddu",
4071 "d,v,t", dreg
, dreg
, AT
);
4073 p
= frag_var (rs_machine_dependent
, 16 + gpdel
+ adj
, 0,
4074 RELAX_ENCODE (24 + adj
, 16 + gpdel
+ adj
, gpdel
,
4077 ? mips_warn_about_macros
4079 offset_expr
.X_add_symbol
, (long) 0,
4087 /* This is needed because this instruction uses $gp, but
4088 the first instruction on the main stream does not. */
4089 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4092 macro_build (p
, &icnt
, &offset_expr
,
4094 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
4096 if (expr1
.X_add_number
>= -0x8000
4097 && expr1
.X_add_number
< 0x8000)
4099 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4101 macro_build (p
, &icnt
, &expr1
,
4102 mips_isa
< 3 ? "addiu" : "daddiu",
4103 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
4104 /* FIXME: If add_number is 0, and there was no base
4105 register, the external symbol case ended with a load,
4106 so if the symbol turns out to not be external, and
4107 the next instruction uses tempreg, an unnecessary nop
4108 will be inserted. */
4114 /* We must add in the base register now, as in the
4115 external symbol case. */
4116 assert (tempreg
== AT
);
4117 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4119 macro_build (p
, &icnt
, (expressionS
*) NULL
,
4120 mips_isa
< 3 ? "addu" : "daddu",
4121 "d,v,t", treg
, AT
, breg
);
4124 /* We set breg to 0 because we have arranged to add
4125 it in in both cases. */
4129 macro_build_lui (p
, &icnt
, &expr1
, AT
);
4131 macro_build (p
, &icnt
, &expr1
,
4132 mips_isa
< 3 ? "addiu" : "daddiu",
4133 "t,r,j", AT
, AT
, (int) BFD_RELOC_LO16
);
4135 macro_build (p
, &icnt
, (expressionS
*) NULL
,
4136 mips_isa
< 3 ? "addu" : "daddu",
4137 "d,v,t", tempreg
, tempreg
, AT
);
4141 else if (mips_pic
== EMBEDDED_PIC
)
4144 addiu $tempreg,$gp,<sym> (BFD_RELOC_MIPS_GPREL)
4146 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4147 mips_isa
< 3 ? "addiu" : "daddiu",
4148 "t,r,j", tempreg
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
4154 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4155 mips_isa
< 3 ? "addu" : "daddu",
4156 "d,v,t", treg
, tempreg
, breg
);
4164 /* The j instruction may not be used in PIC code, since it
4165 requires an absolute address. We convert it to a b
4167 if (mips_pic
== NO_PIC
)
4168 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "j", "a");
4170 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "b", "p");
4173 /* The jal instructions must be handled as macros because when
4174 generating PIC code they expand to multi-instruction
4175 sequences. Normally they are simple instructions. */
4180 if (mips_pic
== NO_PIC
4181 || mips_pic
== EMBEDDED_PIC
)
4182 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "jalr",
4184 else if (mips_pic
== SVR4_PIC
)
4186 if (sreg
!= PIC_CALL_REG
)
4187 as_warn ("MIPS PIC call to register other than $25");
4189 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "jalr",
4191 if (mips_cprestore_offset
< 0)
4192 as_warn ("No .cprestore pseudo-op used in PIC code");
4195 expr1
.X_add_number
= mips_cprestore_offset
;
4196 macro_build ((char *) NULL
, &icnt
, &expr1
,
4197 mips_isa
< 3 ? "lw" : "ld",
4198 "t,o(b)", GP
, (int) BFD_RELOC_LO16
, mips_frame_reg
);
4207 if (mips_pic
== NO_PIC
)
4208 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "jal", "a");
4209 else if (mips_pic
== SVR4_PIC
)
4211 /* If this is a reference to an external symbol, and we are
4212 using a small GOT, we want
4213 lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
4217 lw $gp,cprestore($sp)
4218 The cprestore value is set using the .cprestore
4219 pseudo-op. If we are using a big GOT, we want
4220 lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16)
4222 lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16)
4226 lw $gp,cprestore($sp)
4227 If the symbol is not external, we want
4228 lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4230 addiu $25,$25,<sym> (BFD_RELOC_LO16)
4233 lw $gp,cprestore($sp) */
4237 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4238 mips_isa
< 3 ? "lw" : "ld",
4239 "t,o(b)", PIC_CALL_REG
,
4240 (int) BFD_RELOC_MIPS_CALL16
, GP
);
4241 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4243 p
= frag_var (rs_machine_dependent
, 4, 0,
4244 RELAX_ENCODE (0, 4, -8, 0, 0, 0),
4245 offset_expr
.X_add_symbol
, (long) 0, (char *) NULL
);
4251 if (reg_needs_delay (GP
))
4255 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
4256 PIC_CALL_REG
, (int) BFD_RELOC_MIPS_CALL_HI16
);
4257 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4258 mips_isa
< 3 ? "addu" : "daddu",
4259 "d,v,t", PIC_CALL_REG
, PIC_CALL_REG
, GP
);
4260 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4261 mips_isa
< 3 ? "lw" : "ld",
4262 "t,o(b)", PIC_CALL_REG
,
4263 (int) BFD_RELOC_MIPS_CALL_LO16
, PIC_CALL_REG
);
4264 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4266 p
= frag_var (rs_machine_dependent
, 12 + gpdel
, 0,
4267 RELAX_ENCODE (16, 12 + gpdel
, gpdel
, 8 + gpdel
,
4269 offset_expr
.X_add_symbol
, (long) 0, (char *) NULL
);
4272 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4275 macro_build (p
, &icnt
, &offset_expr
,
4276 mips_isa
< 3 ? "lw" : "ld",
4277 "t,o(b)", PIC_CALL_REG
,
4278 (int) BFD_RELOC_MIPS_GOT16
, GP
);
4280 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4283 macro_build (p
, &icnt
, &offset_expr
,
4284 mips_isa
< 3 ? "addiu" : "daddiu",
4285 "t,r,j", PIC_CALL_REG
, PIC_CALL_REG
,
4286 (int) BFD_RELOC_LO16
);
4287 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4288 "jalr", "s", PIC_CALL_REG
);
4289 if (mips_cprestore_offset
< 0)
4290 as_warn ("No .cprestore pseudo-op used in PIC code");
4294 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4296 expr1
.X_add_number
= mips_cprestore_offset
;
4297 macro_build ((char *) NULL
, &icnt
, &expr1
,
4298 mips_isa
< 3 ? "lw" : "ld",
4299 "t,o(b)", GP
, (int) BFD_RELOC_LO16
,
4303 else if (mips_pic
== EMBEDDED_PIC
)
4305 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "bal", "p");
4306 /* The linker may expand the call to a longer sequence which
4307 uses $at, so we must break rather than return. */
4383 if (breg
== treg
|| coproc
|| lr
)
4452 if (mask
== M_LWC1_AB
4453 || mask
== M_SWC1_AB
4454 || mask
== M_LDC1_AB
4455 || mask
== M_SDC1_AB
4464 if (offset_expr
.X_op
!= O_constant
4465 && offset_expr
.X_op
!= O_symbol
)
4467 as_bad ("expression too complex");
4468 offset_expr
.X_op
= O_constant
;
4471 /* A constant expression in PIC code can be handled just as it
4472 is in non PIC code. */
4473 if (mips_pic
== NO_PIC
4474 || offset_expr
.X_op
== O_constant
)
4476 /* If this is a reference to a GP relative symbol, and there
4477 is no base register, we want
4478 <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL)
4479 Otherwise, if there is no base register, we want
4480 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
4481 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
4482 If we have a constant, we need two instructions anyhow,
4483 so we always use the latter form.
4485 If we have a base register, and this is a reference to a
4486 GP relative symbol, we want
4487 addu $tempreg,$breg,$gp
4488 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GPREL)
4490 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
4491 addu $tempreg,$tempreg,$breg
4492 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
4493 With a constant we always use the latter case. */
4496 if ((valueT
) offset_expr
.X_add_number
>= MAX_GPREL_OFFSET
4497 || nopic_need_relax (offset_expr
.X_add_symbol
))
4502 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
4503 treg
, (int) BFD_RELOC_MIPS_GPREL
, GP
);
4504 p
= frag_var (rs_machine_dependent
, 8, 0,
4505 RELAX_ENCODE (4, 8, 0, 4, 0,
4506 (mips_warn_about_macros
4507 || (used_at
&& mips_noat
))),
4508 offset_expr
.X_add_symbol
, (long) 0,
4512 macro_build_lui (p
, &icnt
, &offset_expr
, tempreg
);
4515 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
, treg
,
4516 (int) BFD_RELOC_LO16
, tempreg
);
4520 if ((valueT
) offset_expr
.X_add_number
>= MAX_GPREL_OFFSET
4521 || nopic_need_relax (offset_expr
.X_add_symbol
))
4526 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4527 mips_isa
< 3 ? "addu" : "daddu",
4528 "d,v,t", tempreg
, breg
, GP
);
4529 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
4530 treg
, (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
4531 p
= frag_var (rs_machine_dependent
, 12, 0,
4532 RELAX_ENCODE (8, 12, 0, 8, 0, 0),
4533 offset_expr
.X_add_symbol
, (long) 0,
4536 macro_build_lui (p
, &icnt
, &offset_expr
, tempreg
);
4539 macro_build (p
, &icnt
, (expressionS
*) NULL
,
4540 mips_isa
< 3 ? "addu" : "daddu",
4541 "d,v,t", tempreg
, tempreg
, breg
);
4544 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
, treg
,
4545 (int) BFD_RELOC_LO16
, tempreg
);
4548 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
4550 /* If this is a reference to an external symbol, we want
4551 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4553 <op> $treg,0($tempreg)
4555 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4557 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
4558 <op> $treg,0($tempreg)
4559 If there is a base register, we add it to $tempreg before
4560 the <op>. If there is a constant, we stick it in the
4561 <op> instruction. We don't handle constants larger than
4562 16 bits, because we have no way to load the upper 16 bits
4563 (actually, we could handle them for the subset of cases
4564 in which we are not using $at). */
4565 assert (offset_expr
.X_op
== O_symbol
);
4566 expr1
.X_add_number
= offset_expr
.X_add_number
;
4567 offset_expr
.X_add_number
= 0;
4568 if (expr1
.X_add_number
< -0x8000
4569 || expr1
.X_add_number
>= 0x8000)
4570 as_bad ("PIC code offset overflow (max 16 signed bits)");
4572 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4573 mips_isa
< 3 ? "lw" : "ld",
4574 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
4575 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
4576 p
= frag_var (rs_machine_dependent
, 4, 0,
4577 RELAX_ENCODE (0, 4, -8, 0, 0, 0),
4578 offset_expr
.X_add_symbol
, (long) 0,
4580 macro_build (p
, &icnt
, &offset_expr
,
4581 mips_isa
< 3 ? "addiu" : "daddiu",
4582 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
4584 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4585 mips_isa
< 3 ? "addu" : "daddu",
4586 "d,v,t", tempreg
, tempreg
, breg
);
4587 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
, treg
,
4588 (int) BFD_RELOC_LO16
, tempreg
);
4590 else if (mips_pic
== SVR4_PIC
)
4594 /* If this is a reference to an external symbol, we want
4595 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
4596 addu $tempreg,$tempreg,$gp
4597 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
4598 <op> $treg,0($tempreg)
4600 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4602 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
4603 <op> $treg,0($tempreg)
4604 If there is a base register, we add it to $tempreg before
4605 the <op>. If there is a constant, we stick it in the
4606 <op> instruction. We don't handle constants larger than
4607 16 bits, because we have no way to load the upper 16 bits
4608 (actually, we could handle them for the subset of cases
4609 in which we are not using $at). */
4610 assert (offset_expr
.X_op
== O_symbol
);
4611 expr1
.X_add_number
= offset_expr
.X_add_number
;
4612 offset_expr
.X_add_number
= 0;
4613 if (expr1
.X_add_number
< -0x8000
4614 || expr1
.X_add_number
>= 0x8000)
4615 as_bad ("PIC code offset overflow (max 16 signed bits)");
4616 if (reg_needs_delay (GP
))
4621 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
4622 tempreg
, (int) BFD_RELOC_MIPS_GOT_HI16
);
4623 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4624 mips_isa
< 3 ? "addu" : "daddu",
4625 "d,v,t", tempreg
, tempreg
, GP
);
4626 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4627 mips_isa
< 3 ? "lw" : "ld",
4628 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT_LO16
,
4630 p
= frag_var (rs_machine_dependent
, 12 + gpdel
, 0,
4631 RELAX_ENCODE (12, 12 + gpdel
, gpdel
, 8 + gpdel
, 0, 0),
4632 offset_expr
.X_add_symbol
, (long) 0, (char *) NULL
);
4635 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4638 macro_build (p
, &icnt
, &offset_expr
,
4639 mips_isa
< 3 ? "lw" : "ld",
4640 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
4642 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4644 macro_build (p
, &icnt
, &offset_expr
,
4645 mips_isa
< 3 ? "addiu" : "daddiu",
4646 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
4648 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4649 mips_isa
< 3 ? "addu" : "daddu",
4650 "d,v,t", tempreg
, tempreg
, breg
);
4651 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
, treg
,
4652 (int) BFD_RELOC_LO16
, tempreg
);
4654 else if (mips_pic
== EMBEDDED_PIC
)
4656 /* If there is no base register, we want
4657 <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL)
4658 If there is a base register, we want
4659 addu $tempreg,$breg,$gp
4660 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GPREL)
4662 assert (offset_expr
.X_op
== O_symbol
);
4665 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
4666 treg
, (int) BFD_RELOC_MIPS_GPREL
, GP
);
4671 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4672 mips_isa
< 3 ? "addu" : "daddu",
4673 "d,v,t", tempreg
, breg
, GP
);
4674 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
4675 treg
, (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
4688 load_register (&icnt
, treg
, &imm_expr
, 0);
4692 load_register (&icnt
, treg
, &imm_expr
, 1);
4696 if (imm_expr
.X_op
== O_constant
)
4698 load_register (&icnt
, AT
, &imm_expr
, 0);
4699 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4700 "mtc1", "t,G", AT
, treg
);
4705 assert (offset_expr
.X_op
== O_symbol
4706 && strcmp (segment_name (S_GET_SEGMENT
4707 (offset_expr
.X_add_symbol
)),
4709 && offset_expr
.X_add_number
== 0);
4710 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lwc1", "T,o(b)",
4711 treg
, (int) BFD_RELOC_MIPS_LITERAL
, GP
);
4716 /* We know that sym is in the .rdata section. First we get the
4717 upper 16 bits of the address. */
4718 if (mips_pic
== NO_PIC
)
4720 /* FIXME: This won't work for a 64 bit address. */
4721 macro_build_lui ((char *) NULL
, &icnt
, &offset_expr
, AT
);
4723 else if (mips_pic
== SVR4_PIC
)
4725 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4726 mips_isa
< 3 ? "lw" : "ld",
4727 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
4729 else if (mips_pic
== EMBEDDED_PIC
)
4731 /* For embedded PIC we pick up the entire address off $gp in
4732 a single instruction. */
4733 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4734 mips_isa
< 3 ? "addiu" : "daddiu",
4735 "t,r,j", AT
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
4736 offset_expr
.X_op
= O_constant
;
4737 offset_expr
.X_add_number
= 0;
4742 /* Now we load the register(s). */
4744 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "ld", "t,o(b)",
4745 treg
, (int) BFD_RELOC_LO16
, AT
);
4748 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lw", "t,o(b)",
4749 treg
, (int) BFD_RELOC_LO16
, AT
);
4752 /* FIXME: How in the world do we deal with the possible
4754 offset_expr
.X_add_number
+= 4;
4755 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lw", "t,o(b)",
4756 treg
+ 1, (int) BFD_RELOC_LO16
, AT
);
4760 /* To avoid confusion in tc_gen_reloc, we must ensure that this
4761 does not become a variant frag. */
4762 frag_wane (frag_now
);
4768 assert (offset_expr
.X_op
== O_symbol
4769 && offset_expr
.X_add_number
== 0);
4770 s
= segment_name (S_GET_SEGMENT (offset_expr
.X_add_symbol
));
4771 if (strcmp (s
, ".lit8") == 0)
4775 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "ldc1",
4776 "T,o(b)", treg
, (int) BFD_RELOC_MIPS_LITERAL
, GP
);
4780 r
= BFD_RELOC_MIPS_LITERAL
;
4785 assert (strcmp (s
, RDATA_SECTION_NAME
) == 0);
4786 if (mips_pic
== SVR4_PIC
)
4787 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4788 mips_isa
< 3 ? "lw" : "ld",
4789 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
4792 /* FIXME: This won't work for a 64 bit address. */
4793 macro_build_lui ((char *) NULL
, &icnt
, &offset_expr
, AT
);
4798 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "ldc1",
4799 "T,o(b)", treg
, (int) BFD_RELOC_LO16
, AT
);
4801 /* To avoid confusion in tc_gen_reloc, we must ensure
4802 that this does not become a variant frag. */
4803 frag_wane (frag_now
);
4814 /* Even on a big endian machine $fn comes before $fn+1. We have
4815 to adjust when loading from memory. */
4818 assert (mips_isa
< 2);
4819 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lwc1", "T,o(b)",
4820 target_big_endian
? treg
+ 1 : treg
,
4822 /* FIXME: A possible overflow which I don't know how to deal
4824 offset_expr
.X_add_number
+= 4;
4825 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lwc1", "T,o(b)",
4826 target_big_endian
? treg
: treg
+ 1,
4829 /* To avoid confusion in tc_gen_reloc, we must ensure that this
4830 does not become a variant frag. */
4831 frag_wane (frag_now
);
4840 * The MIPS assembler seems to check for X_add_number not
4841 * being double aligned and generating:
4844 * addiu at,at,%lo(foo+1)
4847 * But, the resulting address is the same after relocation so why
4848 * generate the extra instruction?
4895 if (offset_expr
.X_op
!= O_symbol
4896 && offset_expr
.X_op
!= O_constant
)
4898 as_bad ("expression too complex");
4899 offset_expr
.X_op
= O_constant
;
4902 /* Even on a big endian machine $fn comes before $fn+1. We have
4903 to adjust when loading from memory. We set coproc if we must
4904 load $fn+1 first. */
4905 if (! target_big_endian
)
4908 if (mips_pic
== NO_PIC
4909 || offset_expr
.X_op
== O_constant
)
4911 /* If this is a reference to a GP relative symbol, we want
4912 <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL)
4913 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_MIPS_GPREL)
4914 If we have a base register, we use this
4916 <op> $treg,<sym>($at) (BFD_RELOC_MIPS_GPREL)
4917 <op> $treg+1,<sym>+4($at) (BFD_RELOC_MIPS_GPREL)
4918 If this is not a GP relative symbol, we want
4919 lui $at,<sym> (BFD_RELOC_HI16_S)
4920 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
4921 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
4922 If there is a base register, we add it to $at after the
4923 lui instruction. If there is a constant, we always use
4925 if ((valueT
) offset_expr
.X_add_number
>= MAX_GPREL_OFFSET
4926 || nopic_need_relax (offset_expr
.X_add_symbol
))
4945 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4946 mips_isa
< 3 ? "addu" : "daddu",
4947 "d,v,t", AT
, breg
, GP
);
4953 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
4954 coproc
? treg
+ 1 : treg
,
4955 (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
4956 offset_expr
.X_add_number
+= 4;
4958 /* Set mips_optimize to 2 to avoid inserting an
4960 hold_mips_optimize
= mips_optimize
;
4962 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
4963 coproc
? treg
: treg
+ 1,
4964 (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
4965 mips_optimize
= hold_mips_optimize
;
4967 p
= frag_var (rs_machine_dependent
, 12 + off
, 0,
4968 RELAX_ENCODE (8 + off
, 12 + off
, 0, 4 + off
, 1,
4969 used_at
&& mips_noat
),
4970 offset_expr
.X_add_symbol
, (long) 0,
4973 /* We just generated two relocs. When tc_gen_reloc
4974 handles this case, it will skip the first reloc and
4975 handle the second. The second reloc already has an
4976 extra addend of 4, which we added above. We must
4977 subtract it out, and then subtract another 4 to make
4978 the first reloc come out right. The second reloc
4979 will come out right because we are going to add 4 to
4980 offset_expr when we build its instruction below. */
4981 offset_expr
.X_add_number
-= 8;
4982 offset_expr
.X_op
= O_constant
;
4984 macro_build_lui (p
, &icnt
, &offset_expr
, AT
);
4989 macro_build (p
, &icnt
, (expressionS
*) NULL
,
4990 mips_isa
< 3 ? "addu" : "daddu",
4991 "d,v,t", AT
, breg
, AT
);
4995 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
,
4996 coproc
? treg
+ 1 : treg
,
4997 (int) BFD_RELOC_LO16
, AT
);
5000 /* FIXME: How do we handle overflow here? */
5001 offset_expr
.X_add_number
+= 4;
5002 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
,
5003 coproc
? treg
: treg
+ 1,
5004 (int) BFD_RELOC_LO16
, AT
);
5006 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
5010 /* If this is a reference to an external symbol, we want
5011 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5016 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5018 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
5019 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
5020 If there is a base register we add it to $at before the
5021 lwc1 instructions. If there is a constant we include it
5022 in the lwc1 instructions. */
5024 expr1
.X_add_number
= offset_expr
.X_add_number
;
5025 offset_expr
.X_add_number
= 0;
5026 if (expr1
.X_add_number
< -0x8000
5027 || expr1
.X_add_number
>= 0x8000 - 4)
5028 as_bad ("PIC code offset overflow (max 16 signed bits)");
5033 frag_grow (24 + off
);
5034 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5035 mips_isa
< 3 ? "lw" : "ld",
5036 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
5037 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
5039 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5040 mips_isa
< 3 ? "addu" : "daddu",
5041 "d,v,t", AT
, breg
, AT
);
5042 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
5043 coproc
? treg
+ 1 : treg
,
5044 (int) BFD_RELOC_LO16
, AT
);
5045 expr1
.X_add_number
+= 4;
5047 /* Set mips_optimize to 2 to avoid inserting an undesired
5049 hold_mips_optimize
= mips_optimize
;
5051 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
5052 coproc
? treg
: treg
+ 1,
5053 (int) BFD_RELOC_LO16
, AT
);
5054 mips_optimize
= hold_mips_optimize
;
5056 (void) frag_var (rs_machine_dependent
, 0, 0,
5057 RELAX_ENCODE (0, 0, -16 - off
, -8, 1, 0),
5058 offset_expr
.X_add_symbol
, (long) 0,
5061 else if (mips_pic
== SVR4_PIC
)
5065 /* If this is a reference to an external symbol, we want
5066 lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5068 lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16)
5073 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5075 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
5076 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
5077 If there is a base register we add it to $at before the
5078 lwc1 instructions. If there is a constant we include it
5079 in the lwc1 instructions. */
5081 expr1
.X_add_number
= offset_expr
.X_add_number
;
5082 offset_expr
.X_add_number
= 0;
5083 if (expr1
.X_add_number
< -0x8000
5084 || expr1
.X_add_number
>= 0x8000 - 4)
5085 as_bad ("PIC code offset overflow (max 16 signed bits)");
5086 if (reg_needs_delay (GP
))
5095 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
5096 AT
, (int) BFD_RELOC_MIPS_GOT_HI16
);
5097 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5098 mips_isa
< 3 ? "addu" : "daddu",
5099 "d,v,t", AT
, AT
, GP
);
5100 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5101 mips_isa
< 3 ? "lw" : "ld",
5102 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT_LO16
, AT
);
5103 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
5105 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5106 mips_isa
< 3 ? "addu" : "daddu",
5107 "d,v,t", AT
, breg
, AT
);
5108 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
5109 coproc
? treg
+ 1 : treg
,
5110 (int) BFD_RELOC_LO16
, AT
);
5111 expr1
.X_add_number
+= 4;
5113 /* Set mips_optimize to 2 to avoid inserting an undesired
5115 hold_mips_optimize
= mips_optimize
;
5117 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
5118 coproc
? treg
: treg
+ 1,
5119 (int) BFD_RELOC_LO16
, AT
);
5120 mips_optimize
= hold_mips_optimize
;
5121 expr1
.X_add_number
-= 4;
5123 p
= frag_var (rs_machine_dependent
, 16 + gpdel
+ off
, 0,
5124 RELAX_ENCODE (24 + off
, 16 + gpdel
+ off
, gpdel
,
5125 8 + gpdel
+ off
, 1, 0),
5126 offset_expr
.X_add_symbol
, (long) 0,
5130 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
5133 macro_build (p
, &icnt
, &offset_expr
,
5134 mips_isa
< 3 ? "lw" : "ld",
5135 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
5137 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
5141 macro_build (p
, &icnt
, (expressionS
*) NULL
,
5142 mips_isa
< 3 ? "addu" : "daddu",
5143 "d,v,t", AT
, breg
, AT
);
5146 macro_build (p
, &icnt
, &expr1
, s
, fmt
,
5147 coproc
? treg
+ 1 : treg
,
5148 (int) BFD_RELOC_LO16
, AT
);
5150 expr1
.X_add_number
+= 4;
5152 /* Set mips_optimize to 2 to avoid inserting an undesired
5154 hold_mips_optimize
= mips_optimize
;
5156 macro_build (p
, &icnt
, &expr1
, s
, fmt
,
5157 coproc
? treg
: treg
+ 1,
5158 (int) BFD_RELOC_LO16
, AT
);
5159 mips_optimize
= hold_mips_optimize
;
5161 else if (mips_pic
== EMBEDDED_PIC
)
5163 /* If there is no base register, we use
5164 <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL)
5165 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_MIPS_GPREL)
5166 If we have a base register, we use
5168 <op> $treg,<sym>($at) (BFD_RELOC_MIPS_GPREL)
5169 <op> $treg+1,<sym>+4($at) (BFD_RELOC_MIPS_GPREL)
5178 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5179 mips_isa
< 3 ? "addu" : "daddu",
5180 "d,v,t", AT
, breg
, GP
);
5185 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
5186 coproc
? treg
+ 1 : treg
,
5187 (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
5188 offset_expr
.X_add_number
+= 4;
5189 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
5190 coproc
? treg
: treg
+ 1,
5191 (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
5207 assert (mips_isa
< 3);
5208 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
5209 (int) BFD_RELOC_LO16
, breg
);
5210 offset_expr
.X_add_number
+= 4;
5211 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
+ 1,
5212 (int) BFD_RELOC_LO16
, breg
);
5214 #ifdef LOSING_COMPILER
5220 as_warn ("Macro used $at after \".set noat\"");
5225 struct mips_cl_insn
*ip
;
5227 register int treg
, sreg
, dreg
, breg
;
5242 bfd_reloc_code_real_type r
;
5245 treg
= (ip
->insn_opcode
>> 16) & 0x1f;
5246 dreg
= (ip
->insn_opcode
>> 11) & 0x1f;
5247 sreg
= breg
= (ip
->insn_opcode
>> 21) & 0x1f;
5248 mask
= ip
->insn_mo
->mask
;
5250 expr1
.X_op
= O_constant
;
5251 expr1
.X_op_symbol
= NULL
;
5252 expr1
.X_add_symbol
= NULL
;
5253 expr1
.X_add_number
= 1;
5257 #endif /* LOSING_COMPILER */
5262 macro_build ((char *) NULL
, &icnt
, NULL
,
5263 dbl
? "dmultu" : "multu",
5265 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
5271 /* The MIPS assembler some times generates shifts and adds. I'm
5272 not trying to be that fancy. GCC should do this for us
5274 load_register (&icnt
, AT
, &imm_expr
, dbl
);
5275 macro_build ((char *) NULL
, &icnt
, NULL
,
5276 dbl
? "dmult" : "mult",
5278 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
5284 mips_emit_delays (true);
5286 mips_any_noreorder
= 1;
5287 macro_build ((char *) NULL
, &icnt
, NULL
,
5288 dbl
? "dmult" : "mult",
5290 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
5291 macro_build ((char *) NULL
, &icnt
, NULL
,
5292 dbl
? "dsra32" : "sra",
5293 "d,w,<", dreg
, dreg
, 31);
5294 macro_build ((char *) NULL
, &icnt
, NULL
, "mfhi", "d", AT
);
5296 macro_build ((char *) NULL
, &icnt
, NULL
, "tne", "s,t", dreg
, AT
);
5299 expr1
.X_add_number
= 8;
5300 macro_build ((char *) NULL
, &icnt
, &expr1
, "beq", "s,t,p", dreg
, AT
);
5301 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
5302 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 6);
5305 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
5311 mips_emit_delays (true);
5313 mips_any_noreorder
= 1;
5314 macro_build ((char *) NULL
, &icnt
, NULL
,
5315 dbl
? "dmultu" : "multu",
5317 macro_build ((char *) NULL
, &icnt
, NULL
, "mfhi", "d", AT
);
5318 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
5320 macro_build ((char *) NULL
, &icnt
, NULL
, "tne", "s,t", AT
, 0);
5323 expr1
.X_add_number
= 8;
5324 macro_build ((char *) NULL
, &icnt
, &expr1
, "beq", "s,t,p", AT
, 0);
5325 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
5326 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 6);
5332 macro_build ((char *) NULL
, &icnt
, NULL
, "subu", "d,v,t", AT
, 0, treg
);
5333 macro_build ((char *) NULL
, &icnt
, NULL
, "srlv", "d,t,s", AT
, sreg
, AT
);
5334 macro_build ((char *) NULL
, &icnt
, NULL
, "sllv", "d,t,s", dreg
, sreg
,
5336 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
5340 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", AT
, sreg
,
5341 (int) (imm_expr
.X_add_number
& 0x1f));
5342 macro_build ((char *) NULL
, &icnt
, NULL
, "srl", "d,w,<", dreg
, sreg
,
5343 (int) ((0 - imm_expr
.X_add_number
) & 0x1f));
5344 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
5348 macro_build ((char *) NULL
, &icnt
, NULL
, "subu", "d,v,t", AT
, 0, treg
);
5349 macro_build ((char *) NULL
, &icnt
, NULL
, "sllv", "d,t,s", AT
, sreg
, AT
);
5350 macro_build ((char *) NULL
, &icnt
, NULL
, "srlv", "d,t,s", dreg
, sreg
,
5352 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
5356 macro_build ((char *) NULL
, &icnt
, NULL
, "srl", "d,w,<", AT
, sreg
,
5357 (int) (imm_expr
.X_add_number
& 0x1f));
5358 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", dreg
, sreg
,
5359 (int) ((0 - imm_expr
.X_add_number
) & 0x1f));
5360 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
5364 assert (mips_isa
< 2);
5365 /* Even on a big endian machine $fn comes before $fn+1. We have
5366 to adjust when storing to memory. */
5367 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "swc1", "T,o(b)",
5368 target_big_endian
? treg
+ 1 : treg
,
5369 (int) BFD_RELOC_LO16
, breg
);
5370 offset_expr
.X_add_number
+= 4;
5371 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "swc1", "T,o(b)",
5372 target_big_endian
? treg
: treg
+ 1,
5373 (int) BFD_RELOC_LO16
, breg
);
5378 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
5379 treg
, (int) BFD_RELOC_LO16
);
5381 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
5382 sreg
, (int) BFD_RELOC_LO16
);
5385 macro_build ((char *) NULL
, &icnt
, NULL
, "xor", "d,v,t", dreg
,
5387 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
5388 dreg
, (int) BFD_RELOC_LO16
);
5393 if (imm_expr
.X_add_number
== 0)
5395 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
5396 sreg
, (int) BFD_RELOC_LO16
);
5401 as_warn ("Instruction %s: result is always false",
5403 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
, 0);
5406 if (imm_expr
.X_add_number
>= 0 && imm_expr
.X_add_number
< 0x10000)
5408 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "xori", "t,r,i", dreg
,
5409 sreg
, (int) BFD_RELOC_LO16
);
5412 else if (imm_expr
.X_add_number
> -0x8000 && imm_expr
.X_add_number
< 0)
5414 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
5415 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
5416 mips_isa
< 3 ? "addiu" : "daddiu",
5417 "t,r,j", dreg
, sreg
,
5418 (int) BFD_RELOC_LO16
);
5423 load_register (&icnt
, AT
, &imm_expr
, 0);
5424 macro_build ((char *) NULL
, &icnt
, NULL
, "xor", "d,v,t", dreg
,
5428 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
, dreg
,
5429 (int) BFD_RELOC_LO16
);
5434 case M_SGE
: /* sreg >= treg <==> not (sreg < treg) */
5440 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, sreg
, treg
);
5441 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
5442 (int) BFD_RELOC_LO16
);
5445 case M_SGE_I
: /* sreg >= I <==> not (sreg < I) */
5447 if (imm_expr
.X_add_number
>= -0x8000 && imm_expr
.X_add_number
< 0x8000)
5449 macro_build ((char *) NULL
, &icnt
, &expr1
,
5450 mask
== M_SGE_I
? "slti" : "sltiu",
5451 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
5456 load_register (&icnt
, AT
, &imm_expr
, 0);
5457 macro_build ((char *) NULL
, &icnt
, NULL
,
5458 mask
== M_SGE_I
? "slt" : "sltu",
5459 "d,v,t", dreg
, sreg
, AT
);
5462 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
5463 (int) BFD_RELOC_LO16
);
5468 case M_SGT
: /* sreg > treg <==> treg < sreg */
5474 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, treg
, sreg
);
5477 case M_SGT_I
: /* sreg > I <==> I < sreg */
5483 load_register (&icnt
, AT
, &imm_expr
, 0);
5484 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, AT
, sreg
);
5487 case M_SLE
: /* sreg <= treg <==> treg >= sreg <==> not (treg < sreg) */
5493 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, treg
, sreg
);
5494 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
5495 (int) BFD_RELOC_LO16
);
5498 case M_SLE_I
: /* sreg <= I <==> I >= sreg <==> not (I < sreg) */
5504 load_register (&icnt
, AT
, &imm_expr
, 0);
5505 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, AT
, sreg
);
5506 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
5507 (int) BFD_RELOC_LO16
);
5511 if (imm_expr
.X_add_number
>= -0x8000 && imm_expr
.X_add_number
< 0x8000)
5513 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "slti", "t,r,j",
5514 dreg
, sreg
, (int) BFD_RELOC_LO16
);
5517 load_register (&icnt
, AT
, &imm_expr
, 0);
5518 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", dreg
, sreg
, AT
);
5522 if (imm_expr
.X_add_number
>= -0x8000 && imm_expr
.X_add_number
< 0x8000)
5524 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "sltiu", "t,r,j",
5525 dreg
, sreg
, (int) BFD_RELOC_LO16
);
5528 load_register (&icnt
, AT
, &imm_expr
, 0);
5529 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, sreg
,
5535 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0,
5538 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0,
5542 macro_build ((char *) NULL
, &icnt
, NULL
, "xor", "d,v,t", dreg
,
5544 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0,
5550 if (imm_expr
.X_add_number
== 0)
5552 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0,
5558 as_warn ("Instruction %s: result is always true",
5560 macro_build ((char *) NULL
, &icnt
, &expr1
,
5561 mips_isa
< 3 ? "addiu" : "daddiu",
5562 "t,r,j", dreg
, 0, (int) BFD_RELOC_LO16
);
5565 if (imm_expr
.X_add_number
>= 0 && imm_expr
.X_add_number
< 0x10000)
5567 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "xori", "t,r,i",
5568 dreg
, sreg
, (int) BFD_RELOC_LO16
);
5571 else if (imm_expr
.X_add_number
> -0x8000 && imm_expr
.X_add_number
< 0)
5573 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
5574 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
5575 mips_isa
< 3 ? "addiu" : "daddiu",
5576 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
5581 load_register (&icnt
, AT
, &imm_expr
, 0);
5582 macro_build ((char *) NULL
, &icnt
, NULL
, "xor", "d,v,t", dreg
,
5586 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0, dreg
);
5594 if (imm_expr
.X_add_number
> -0x8000 && imm_expr
.X_add_number
<= 0x8000)
5596 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
5597 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
5598 dbl
? "daddi" : "addi",
5599 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
5602 load_register (&icnt
, AT
, &imm_expr
, dbl
);
5603 macro_build ((char *) NULL
, &icnt
, NULL
,
5604 dbl
? "dsub" : "sub",
5605 "d,v,t", dreg
, sreg
, AT
);
5611 if (imm_expr
.X_add_number
> -0x8000 && imm_expr
.X_add_number
<= 0x8000)
5613 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
5614 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
5615 dbl
? "daddiu" : "addiu",
5616 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
5619 load_register (&icnt
, AT
, &imm_expr
, dbl
);
5620 macro_build ((char *) NULL
, &icnt
, NULL
,
5621 dbl
? "dsubu" : "subu",
5622 "d,v,t", dreg
, sreg
, AT
);
5643 load_register (&icnt
, AT
, &imm_expr
, 0);
5644 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "s,t", sreg
, AT
);
5649 assert (mips_isa
< 2);
5650 sreg
= (ip
->insn_opcode
>> 11) & 0x1f; /* floating reg */
5651 dreg
= (ip
->insn_opcode
>> 06) & 0x1f; /* floating reg */
5654 * Is the double cfc1 instruction a bug in the mips assembler;
5655 * or is there a reason for it?
5657 mips_emit_delays (true);
5659 mips_any_noreorder
= 1;
5660 macro_build ((char *) NULL
, &icnt
, NULL
, "cfc1", "t,G", treg
, 31);
5661 macro_build ((char *) NULL
, &icnt
, NULL
, "cfc1", "t,G", treg
, 31);
5662 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "");
5663 expr1
.X_add_number
= 3;
5664 macro_build ((char *) NULL
, &icnt
, &expr1
, "ori", "t,r,i", AT
, treg
,
5665 (int) BFD_RELOC_LO16
);
5666 expr1
.X_add_number
= 2;
5667 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", AT
, AT
,
5668 (int) BFD_RELOC_LO16
);
5669 macro_build ((char *) NULL
, &icnt
, NULL
, "ctc1", "t,G", AT
, 31);
5670 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "");
5671 macro_build ((char *) NULL
, &icnt
, NULL
,
5672 mask
== M_TRUNCWD
? "cvt.w.d" : "cvt.w.s", "D,S", dreg
, sreg
);
5673 macro_build ((char *) NULL
, &icnt
, NULL
, "ctc1", "t,G", treg
, 31);
5674 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "");
5684 if (offset_expr
.X_add_number
>= 0x7fff)
5685 as_bad ("operand overflow");
5686 /* avoid load delay */
5687 if (! target_big_endian
)
5688 offset_expr
.X_add_number
+= 1;
5689 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
5690 (int) BFD_RELOC_LO16
, breg
);
5691 if (! target_big_endian
)
5692 offset_expr
.X_add_number
-= 1;
5694 offset_expr
.X_add_number
+= 1;
5695 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lbu", "t,o(b)", AT
,
5696 (int) BFD_RELOC_LO16
, breg
);
5697 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", treg
, treg
, 8);
5698 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", treg
, treg
, AT
);
5711 if (offset_expr
.X_add_number
>= 0x8000 - off
)
5712 as_bad ("operand overflow");
5713 if (! target_big_endian
)
5714 offset_expr
.X_add_number
+= off
;
5715 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
5716 (int) BFD_RELOC_LO16
, breg
);
5717 if (! target_big_endian
)
5718 offset_expr
.X_add_number
-= off
;
5720 offset_expr
.X_add_number
+= off
;
5721 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s2
, "t,o(b)", treg
,
5722 (int) BFD_RELOC_LO16
, breg
);
5735 load_address (&icnt
, AT
, &offset_expr
);
5737 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5738 mips_isa
< 3 ? "addu" : "daddu",
5739 "d,v,t", AT
, AT
, breg
);
5740 if (! target_big_endian
)
5741 expr1
.X_add_number
= off
;
5743 expr1
.X_add_number
= 0;
5744 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, "t,o(b)", treg
,
5745 (int) BFD_RELOC_LO16
, AT
);
5746 if (! target_big_endian
)
5747 expr1
.X_add_number
= 0;
5749 expr1
.X_add_number
= off
;
5750 macro_build ((char *) NULL
, &icnt
, &expr1
, s2
, "t,o(b)", treg
,
5751 (int) BFD_RELOC_LO16
, AT
);
5756 load_address (&icnt
, AT
, &offset_expr
);
5758 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5759 mips_isa
< 3 ? "addu" : "daddu",
5760 "d,v,t", AT
, AT
, breg
);
5761 if (target_big_endian
)
5762 expr1
.X_add_number
= 0;
5763 macro_build ((char *) NULL
, &icnt
, &expr1
,
5764 mask
== M_ULH_A
? "lb" : "lbu", "t,o(b)", treg
,
5765 (int) BFD_RELOC_LO16
, AT
);
5766 if (target_big_endian
)
5767 expr1
.X_add_number
= 1;
5769 expr1
.X_add_number
= 0;
5770 macro_build ((char *) NULL
, &icnt
, &expr1
, "lbu", "t,o(b)", AT
,
5771 (int) BFD_RELOC_LO16
, AT
);
5772 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", treg
,
5774 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", treg
,
5779 if (offset_expr
.X_add_number
>= 0x7fff)
5780 as_bad ("operand overflow");
5781 if (target_big_endian
)
5782 offset_expr
.X_add_number
+= 1;
5783 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "sb", "t,o(b)", treg
,
5784 (int) BFD_RELOC_LO16
, breg
);
5785 macro_build ((char *) NULL
, &icnt
, NULL
, "srl", "d,w,<", AT
, treg
, 8);
5786 if (target_big_endian
)
5787 offset_expr
.X_add_number
-= 1;
5789 offset_expr
.X_add_number
+= 1;
5790 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "sb", "t,o(b)", AT
,
5791 (int) BFD_RELOC_LO16
, breg
);
5804 if (offset_expr
.X_add_number
>= 0x8000 - off
)
5805 as_bad ("operand overflow");
5806 if (! target_big_endian
)
5807 offset_expr
.X_add_number
+= off
;
5808 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
5809 (int) BFD_RELOC_LO16
, breg
);
5810 if (! target_big_endian
)
5811 offset_expr
.X_add_number
-= off
;
5813 offset_expr
.X_add_number
+= off
;
5814 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s2
, "t,o(b)", treg
,
5815 (int) BFD_RELOC_LO16
, breg
);
5828 load_address (&icnt
, AT
, &offset_expr
);
5830 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5831 mips_isa
< 3 ? "addu" : "daddu",
5832 "d,v,t", AT
, AT
, breg
);
5833 if (! target_big_endian
)
5834 expr1
.X_add_number
= off
;
5836 expr1
.X_add_number
= 0;
5837 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, "t,o(b)", treg
,
5838 (int) BFD_RELOC_LO16
, AT
);
5839 if (! target_big_endian
)
5840 expr1
.X_add_number
= 0;
5842 expr1
.X_add_number
= off
;
5843 macro_build ((char *) NULL
, &icnt
, &expr1
, s2
, "t,o(b)", treg
,
5844 (int) BFD_RELOC_LO16
, AT
);
5848 load_address (&icnt
, AT
, &offset_expr
);
5850 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5851 mips_isa
< 3 ? "addu" : "daddu",
5852 "d,v,t", AT
, AT
, breg
);
5853 if (! target_big_endian
)
5854 expr1
.X_add_number
= 0;
5855 macro_build ((char *) NULL
, &icnt
, &expr1
, "sb", "t,o(b)", treg
,
5856 (int) BFD_RELOC_LO16
, AT
);
5857 macro_build ((char *) NULL
, &icnt
, NULL
, "srl", "d,w,<", treg
,
5859 if (! target_big_endian
)
5860 expr1
.X_add_number
= 1;
5862 expr1
.X_add_number
= 0;
5863 macro_build ((char *) NULL
, &icnt
, &expr1
, "sb", "t,o(b)", treg
,
5864 (int) BFD_RELOC_LO16
, AT
);
5865 if (! target_big_endian
)
5866 expr1
.X_add_number
= 0;
5868 expr1
.X_add_number
= 1;
5869 macro_build ((char *) NULL
, &icnt
, &expr1
, "lbu", "t,o(b)", AT
,
5870 (int) BFD_RELOC_LO16
, AT
);
5871 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", treg
,
5873 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", treg
,
5878 as_bad ("Macro %s not implemented yet", ip
->insn_mo
->name
);
5882 as_warn ("Macro used $at after \".set noat\"");
5885 /* Implement macros in mips16 mode. */
5889 struct mips_cl_insn
*ip
;
5892 int xreg
, yreg
, zreg
, tmp
;
5896 const char *s
, *s2
, *s3
;
5898 mask
= ip
->insn_mo
->mask
;
5900 xreg
= (ip
->insn_opcode
>> MIPS16OP_SH_RX
) & MIPS16OP_MASK_RX
;
5901 yreg
= (ip
->insn_opcode
>> MIPS16OP_SH_RY
) & MIPS16OP_MASK_RY
;
5902 zreg
= (ip
->insn_opcode
>> MIPS16OP_SH_RZ
) & MIPS16OP_MASK_RZ
;
5906 expr1
.X_op
= O_constant
;
5907 expr1
.X_op_symbol
= NULL
;
5908 expr1
.X_add_symbol
= NULL
;
5909 expr1
.X_add_number
= 1;
5928 mips_emit_delays (true);
5930 mips_any_noreorder
= 1;
5931 macro_build ((char *) NULL
, &icnt
, NULL
,
5932 dbl
? "ddiv" : "div",
5933 "0,x,y", xreg
, yreg
);
5934 expr1
.X_add_number
= 2;
5935 macro_build ((char *) NULL
, &icnt
, &expr1
, "bnez", "x,p", yreg
);
5936 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "6", 7);
5937 /* FIXME: The normal code checks for of -1 / -0x80000000 here,
5938 since that causes an overflow. We should do that as well,
5939 but I don't see how to do the comparisons without a temporary
5942 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "x", zreg
);
5961 mips_emit_delays (true);
5963 mips_any_noreorder
= 1;
5964 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "0,x,y", xreg
, yreg
);
5965 expr1
.X_add_number
= 2;
5966 macro_build ((char *) NULL
, &icnt
, &expr1
, "bnez", "x,p", yreg
);
5967 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "6", 7);
5969 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "x", zreg
);
5977 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
5978 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
5979 dbl
? "daddiu" : "addiu",
5980 "y,x,4", yreg
, xreg
);
5984 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
5985 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "addiu",
5990 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
5991 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "daddiu",
6014 goto do_reverse_branch
;
6018 goto do_reverse_branch
;
6030 goto do_reverse_branch
;
6041 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s
, "x,y",
6043 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s2
, "p");
6070 goto do_addone_branch_i
;
6075 goto do_addone_branch_i
;
6090 goto do_addone_branch_i
;
6097 ++imm_expr
.X_add_number
;
6100 macro_build ((char *) NULL
, &icnt
, &imm_expr
, s
, s3
, xreg
);
6101 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s2
, "p");
6105 expr1
.X_add_number
= 0;
6106 macro_build ((char *) NULL
, &icnt
, &expr1
, "slti", "x,8", yreg
);
6108 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6109 "move", "y,X", xreg
, yreg
);
6110 expr1
.X_add_number
= 2;
6111 macro_build ((char *) NULL
, &icnt
, &expr1
, "bteqz", "p");
6112 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6113 "neg", "x,w", xreg
, xreg
);
6117 /* This routine assembles an instruction into its binary format. As a
6118 side effect, it sets one of the global variables imm_reloc or
6119 offset_reloc to the type of relocation to do if one of the operands
6120 is an address expression. */
6125 struct mips_cl_insn
*ip
;
6130 struct mips_opcode
*insn
;
6133 unsigned int lastregno
= 0;
6138 for (s
= str
; islower (*s
) || (*s
>= '0' && *s
<= '3') || *s
== '6' || *s
== '.'; ++s
)
6150 as_fatal ("Unknown opcode: `%s'", str
);
6152 if ((insn
= (struct mips_opcode
*) hash_find (op_hash
, str
)) == NULL
)
6154 insn_error
= "unrecognized opcode";
6162 assert (strcmp (insn
->name
, str
) == 0);
6164 if (insn
->pinfo
== INSN_MACRO
)
6165 insn_isa
= insn
->match
;
6166 else if ((insn
->pinfo
& INSN_ISA
) == INSN_ISA2
)
6168 else if ((insn
->pinfo
& INSN_ISA
) == INSN_ISA3
)
6170 else if ((insn
->pinfo
& INSN_ISA
) == INSN_ISA4
)
6175 if (insn_isa
> mips_isa
6176 || (insn
->pinfo
!= INSN_MACRO
6177 && (((insn
->pinfo
& INSN_ISA
) == INSN_4650
6179 || ((insn
->pinfo
& INSN_ISA
) == INSN_4010
6181 || ((insn
->pinfo
& INSN_ISA
) == INSN_4100
6183 /* start-sanitize-r5900 */
6184 || ((insn
->pinfo
& INSN_ISA
) == INSN_5900
6186 /* end-sanitize-r5900 */
6189 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
]
6190 && strcmp (insn
->name
, insn
[1].name
) == 0)
6195 if (insn_isa
<= mips_isa
)
6196 insn_error
= "opcode not supported on this processor";
6199 static char buf
[100];
6201 sprintf (buf
, "opcode requires -mips%d or greater", insn_isa
);
6208 ip
->insn_opcode
= insn
->match
;
6209 for (args
= insn
->args
;; ++args
)
6215 case '\0': /* end of args */
6228 ip
->insn_opcode
|= lastregno
<< 21;
6233 ip
->insn_opcode
|= lastregno
<< 16;
6237 ip
->insn_opcode
|= lastregno
<< 11;
6243 /* handle optional base register.
6244 Either the base register is omitted or
6245 we must have a left paren. */
6246 /* this is dependent on the next operand specifier
6247 is a 'b' for base register */
6248 assert (args
[1] == 'b');
6252 case ')': /* these must match exactly */
6257 case '<': /* must be at least one digit */
6259 * According to the manual, if the shift amount is greater
6260 * than 31 or less than 0 the the shift amount should be
6261 * mod 32. In reality the mips assembler issues an error.
6262 * We issue a warning and mask out all but the low 5 bits.
6264 my_getExpression (&imm_expr
, s
);
6265 check_absolute_expr (ip
, &imm_expr
);
6266 if ((unsigned long) imm_expr
.X_add_number
> 31)
6268 as_warn ("Improper shift amount (%ld)",
6269 (long) imm_expr
.X_add_number
);
6270 imm_expr
.X_add_number
= imm_expr
.X_add_number
& 0x1f;
6272 ip
->insn_opcode
|= imm_expr
.X_add_number
<< 6;
6273 imm_expr
.X_op
= O_absent
;
6277 case '>': /* shift amount minus 32 */
6278 my_getExpression (&imm_expr
, s
);
6279 check_absolute_expr (ip
, &imm_expr
);
6280 if ((unsigned long) imm_expr
.X_add_number
< 32
6281 || (unsigned long) imm_expr
.X_add_number
> 63)
6283 ip
->insn_opcode
|= (imm_expr
.X_add_number
- 32) << 6;
6284 imm_expr
.X_op
= O_absent
;
6288 case 'k': /* cache code */
6289 case 'h': /* prefx code */
6290 my_getExpression (&imm_expr
, s
);
6291 check_absolute_expr (ip
, &imm_expr
);
6292 if ((unsigned long) imm_expr
.X_add_number
> 31)
6294 as_warn ("Invalid value for `%s' (%lu)",
6296 (unsigned long) imm_expr
.X_add_number
);
6297 imm_expr
.X_add_number
&= 0x1f;
6300 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_CACHE
;
6302 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_PREFX
;
6303 imm_expr
.X_op
= O_absent
;
6307 case 'c': /* break code */
6308 my_getExpression (&imm_expr
, s
);
6309 check_absolute_expr (ip
, &imm_expr
);
6310 if ((unsigned) imm_expr
.X_add_number
> 1023)
6311 as_warn ("Illegal break code (%ld)",
6312 (long) imm_expr
.X_add_number
);
6313 ip
->insn_opcode
|= imm_expr
.X_add_number
<< 16;
6314 imm_expr
.X_op
= O_absent
;
6318 case 'B': /* syscall code */
6319 my_getExpression (&imm_expr
, s
);
6320 check_absolute_expr (ip
, &imm_expr
);
6321 if ((unsigned) imm_expr
.X_add_number
> 0xfffff)
6322 as_warn ("Illegal syscall code (%ld)",
6323 (long) imm_expr
.X_add_number
);
6324 ip
->insn_opcode
|= imm_expr
.X_add_number
<< 6;
6325 imm_expr
.X_op
= O_absent
;
6329 case 'C': /* Coprocessor code */
6330 my_getExpression (&imm_expr
, s
);
6331 check_absolute_expr (ip
, &imm_expr
);
6332 if ((unsigned long) imm_expr
.X_add_number
>= (1<<25))
6334 as_warn ("Coproccesor code > 25 bits (%ld)",
6335 (long) imm_expr
.X_add_number
);
6336 imm_expr
.X_add_number
&= ((1<<25) - 1);
6338 ip
->insn_opcode
|= imm_expr
.X_add_number
;
6339 imm_expr
.X_op
= O_absent
;
6343 case 'b': /* base register */
6344 case 'd': /* destination register */
6345 case 's': /* source register */
6346 case 't': /* target register */
6347 case 'r': /* both target and source */
6348 case 'v': /* both dest and source */
6349 case 'w': /* both dest and target */
6350 case 'E': /* coprocessor target register */
6351 case 'G': /* coprocessor destination register */
6352 case 'x': /* ignore register name */
6353 case 'z': /* must be zero register */
6367 while (isdigit (*s
));
6369 as_bad ("Invalid register number (%d)", regno
);
6371 else if (*args
== 'E' || *args
== 'G')
6375 if (s
[1] == 'f' && s
[2] == 'p')
6380 else if (s
[1] == 's' && s
[2] == 'p')
6385 else if (s
[1] == 'g' && s
[2] == 'p')
6390 else if (s
[1] == 'a' && s
[2] == 't')
6395 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '0')
6400 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '1')
6412 as_warn ("Used $at without \".set noat\"");
6418 if (c
== 'r' || c
== 'v' || c
== 'w')
6425 /* 'z' only matches $0. */
6426 if (c
== 'z' && regno
!= 0)
6434 ip
->insn_opcode
|= regno
<< 21;
6438 ip
->insn_opcode
|= regno
<< 11;
6443 ip
->insn_opcode
|= regno
<< 16;
6446 /* This case exists because on the r3000 trunc
6447 expands into a macro which requires a gp
6448 register. On the r6000 or r4000 it is
6449 assembled into a single instruction which
6450 ignores the register. Thus the insn version
6451 is MIPS_ISA2 and uses 'x', and the macro
6452 version is MIPS_ISA1 and uses 't'. */
6455 /* This case is for the div instruction, which
6456 acts differently if the destination argument
6457 is $0. This only matches $0, and is checked
6458 outside the switch. */
6469 ip
->insn_opcode
|= lastregno
<< 21;
6472 ip
->insn_opcode
|= lastregno
<< 16;
6477 case 'D': /* floating point destination register */
6478 case 'S': /* floating point source register */
6479 case 'T': /* floating point target register */
6480 case 'R': /* floating point source register */
6484 if (s
[0] == '$' && s
[1] == 'f' && isdigit (s
[2]))
6494 while (isdigit (*s
));
6497 as_bad ("Invalid float register number (%d)", regno
);
6499 if ((regno
& 1) != 0
6501 && ! (strcmp (str
, "mtc1") == 0
6502 || strcmp (str
, "mfc1") == 0
6503 || strcmp (str
, "lwc1") == 0
6504 || strcmp (str
, "swc1") == 0
6505 || strcmp (str
, "l.s") == 0
6506 || strcmp (str
, "s.s") == 0))
6507 as_warn ("Float register should be even, was %d",
6515 if (c
== 'V' || c
== 'W')
6525 ip
->insn_opcode
|= regno
<< 6;
6529 ip
->insn_opcode
|= regno
<< 11;
6533 ip
->insn_opcode
|= regno
<< 16;
6536 ip
->insn_opcode
|= regno
<< 21;
6545 ip
->insn_opcode
|= lastregno
<< 11;
6548 ip
->insn_opcode
|= lastregno
<< 16;
6554 my_getExpression (&imm_expr
, s
);
6555 if (imm_expr
.X_op
!= O_big
6556 && imm_expr
.X_op
!= O_constant
)
6557 insn_error
= "absolute expression required";
6562 my_getExpression (&offset_expr
, s
);
6563 imm_reloc
= BFD_RELOC_32
;
6575 unsigned char temp
[8];
6577 unsigned int length
;
6582 /* These only appear as the last operand in an
6583 instruction, and every instruction that accepts
6584 them in any variant accepts them in all variants.
6585 This means we don't have to worry about backing out
6586 any changes if the instruction does not match.
6588 The difference between them is the size of the
6589 floating point constant and where it goes. For 'F'
6590 and 'L' the constant is 64 bits; for 'f' and 'l' it
6591 is 32 bits. Where the constant is placed is based
6592 on how the MIPS assembler does things:
6595 f -- immediate value
6598 The .lit4 and .lit8 sections are only used if
6599 permitted by the -G argument.
6601 When generating embedded PIC code, we use the
6602 .lit8 section but not the .lit4 section (we can do
6603 .lit4 inline easily; we need to put .lit8
6604 somewhere in the data segment, and using .lit8
6605 permits the linker to eventually combine identical
6608 f64
= *args
== 'F' || *args
== 'L';
6610 save_in
= input_line_pointer
;
6611 input_line_pointer
= s
;
6612 err
= md_atof (f64
? 'd' : 'f', (char *) temp
, &len
);
6614 s
= input_line_pointer
;
6615 input_line_pointer
= save_in
;
6616 if (err
!= NULL
&& *err
!= '\0')
6618 as_bad ("Bad floating point constant: %s", err
);
6619 memset (temp
, '\0', sizeof temp
);
6620 length
= f64
? 8 : 4;
6623 assert (length
== (f64
? 8 : 4));
6627 && (! USE_GLOBAL_POINTER_OPT
6628 || mips_pic
== EMBEDDED_PIC
6629 || g_switch_value
< 4)
6632 imm_expr
.X_op
= O_constant
;
6633 if (! target_big_endian
)
6634 imm_expr
.X_add_number
=
6635 (((((((int) temp
[3] << 8)
6640 imm_expr
.X_add_number
=
6641 (((((((int) temp
[0] << 8)
6648 const char *newname
;
6651 /* Switch to the right section. */
6653 subseg
= now_subseg
;
6656 default: /* unused default case avoids warnings. */
6658 newname
= RDATA_SECTION_NAME
;
6659 if (USE_GLOBAL_POINTER_OPT
&& g_switch_value
>= 8)
6663 newname
= RDATA_SECTION_NAME
;
6666 assert (!USE_GLOBAL_POINTER_OPT
6667 || g_switch_value
>= 4);
6671 new_seg
= subseg_new (newname
, (subsegT
) 0);
6672 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
6673 bfd_set_section_flags (stdoutput
, new_seg
,
6678 frag_align (*args
== 'l' ? 2 : 3, 0);
6679 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
6680 record_alignment (new_seg
, 4);
6682 record_alignment (new_seg
, *args
== 'l' ? 2 : 3);
6684 as_bad ("Can't use floating point insn in this section");
6686 /* Set the argument to the current address in the
6688 offset_expr
.X_op
= O_symbol
;
6689 offset_expr
.X_add_symbol
=
6690 symbol_new ("L0\001", now_seg
,
6691 (valueT
) frag_now_fix (), frag_now
);
6692 offset_expr
.X_add_number
= 0;
6694 /* Put the floating point number into the section. */
6695 p
= frag_more ((int) length
);
6696 memcpy (p
, temp
, length
);
6698 /* Switch back to the original section. */
6699 subseg_set (seg
, subseg
);
6704 case 'i': /* 16 bit unsigned immediate */
6705 case 'j': /* 16 bit signed immediate */
6706 imm_reloc
= BFD_RELOC_LO16
;
6707 c
= my_getSmallExpression (&imm_expr
, s
);
6712 if (imm_expr
.X_op
== O_constant
)
6713 imm_expr
.X_add_number
=
6714 (imm_expr
.X_add_number
>> 16) & 0xffff;
6717 imm_reloc
= BFD_RELOC_HI16_S
;
6718 imm_unmatched_hi
= true;
6721 imm_reloc
= BFD_RELOC_HI16
;
6726 if ((c
== '\0' && imm_expr
.X_op
!= O_constant
)
6727 || ((imm_expr
.X_add_number
< 0
6728 || imm_expr
.X_add_number
>= 0x10000)
6729 && imm_expr
.X_op
== O_constant
))
6731 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
6732 !strcmp (insn
->name
, insn
[1].name
))
6734 if (imm_expr
.X_op
!= O_constant
6735 && imm_expr
.X_op
!= O_big
)
6736 insn_error
= "absolute expression required";
6738 as_bad ("16 bit expression not in range 0..65535");
6746 /* The upper bound should be 0x8000, but
6747 unfortunately the MIPS assembler accepts numbers
6748 from 0x8000 to 0xffff and sign extends them, and
6749 we want to be compatible. We only permit this
6750 extended range for an instruction which does not
6751 provide any further alternates, since those
6752 alternates may handle other cases. People should
6753 use the numbers they mean, rather than relying on
6754 a mysterious sign extension. */
6755 more
= (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
6756 strcmp (insn
->name
, insn
[1].name
) == 0);
6761 if ((c
== '\0' && imm_expr
.X_op
!= O_constant
)
6762 || ((imm_expr
.X_add_number
< -0x8000
6763 || imm_expr
.X_add_number
>= max
)
6764 && imm_expr
.X_op
== O_constant
)
6766 && imm_expr
.X_add_number
< 0
6768 && imm_expr
.X_unsigned
6769 && sizeof (imm_expr
.X_add_number
) <= 4))
6773 if (imm_expr
.X_op
!= O_constant
6774 && imm_expr
.X_op
!= O_big
)
6775 insn_error
= "absolute expression required";
6777 as_bad ("16 bit expression not in range -32768..32767");
6783 case 'o': /* 16 bit offset */
6784 c
= my_getSmallExpression (&offset_expr
, s
);
6786 /* If this value won't fit into a 16 bit offset, then go
6787 find a macro that will generate the 32 bit offset
6788 code pattern. As a special hack, we accept the
6789 difference of two local symbols as a constant. This
6790 is required to suppose embedded PIC switches, which
6791 use an instruction which looks like
6792 lw $4,$L12-$LS12($4)
6793 The problem with handling this in a more general
6794 fashion is that the macro function doesn't expect to
6795 see anything which can be handled in a single
6796 constant instruction. */
6798 && (offset_expr
.X_op
!= O_constant
6799 || offset_expr
.X_add_number
>= 0x8000
6800 || offset_expr
.X_add_number
< -0x8000)
6801 && (mips_pic
!= EMBEDDED_PIC
6802 || offset_expr
.X_op
!= O_subtract
6803 || now_seg
!= text_section
6804 || (S_GET_SEGMENT (offset_expr
.X_op_symbol
)
6808 offset_reloc
= BFD_RELOC_LO16
;
6809 if (c
== 'h' || c
== 'H')
6811 assert (offset_expr
.X_op
== O_constant
);
6812 offset_expr
.X_add_number
=
6813 (offset_expr
.X_add_number
>> 16) & 0xffff;
6818 case 'p': /* pc relative offset */
6819 offset_reloc
= BFD_RELOC_16_PCREL_S2
;
6820 my_getExpression (&offset_expr
, s
);
6824 case 'u': /* upper 16 bits */
6825 c
= my_getSmallExpression (&imm_expr
, s
);
6826 if (imm_expr
.X_op
== O_constant
6827 && (imm_expr
.X_add_number
< 0
6828 || imm_expr
.X_add_number
>= 0x10000))
6829 as_bad ("lui expression not in range 0..65535");
6830 imm_reloc
= BFD_RELOC_LO16
;
6835 if (imm_expr
.X_op
== O_constant
)
6836 imm_expr
.X_add_number
=
6837 (imm_expr
.X_add_number
>> 16) & 0xffff;
6840 imm_reloc
= BFD_RELOC_HI16_S
;
6841 imm_unmatched_hi
= true;
6844 imm_reloc
= BFD_RELOC_HI16
;
6850 case 'a': /* 26 bit address */
6851 my_getExpression (&offset_expr
, s
);
6853 offset_reloc
= BFD_RELOC_MIPS_JMP
;
6856 case 'N': /* 3 bit branch condition code */
6857 case 'M': /* 3 bit compare condition code */
6858 if (strncmp (s
, "$fcc", 4) != 0)
6868 while (isdigit (*s
));
6870 as_bad ("invalid condition code register $fcc%d", regno
);
6872 ip
->insn_opcode
|= regno
<< OP_SH_BCC
;
6874 ip
->insn_opcode
|= regno
<< OP_SH_CCC
;
6878 fprintf (stderr
, "bad char = '%c'\n", *args
);
6883 /* Args don't match. */
6884 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
6885 !strcmp (insn
->name
, insn
[1].name
))
6891 insn_error
= "illegal operands";
6896 /* This routine assembles an instruction into its binary format when
6897 assembling for the mips16. As a side effect, it sets one of the
6898 global variables imm_reloc or offset_reloc to the type of
6899 relocation to do if one of the operands is an address expression.
6900 It also sets mips16_small and mips16_ext if the user explicitly
6901 requested a small or extended instruction. */
6906 struct mips_cl_insn
*ip
;
6910 struct mips_opcode
*insn
;
6913 unsigned int lastregno
= 0;
6918 mips16_small
= false;
6921 for (s
= str
; islower (*s
); ++s
)
6933 if (s
[1] == 't' && s
[2] == ' ')
6936 mips16_small
= true;
6940 else if (s
[1] == 'e' && s
[2] == ' ')
6949 insn_error
= "unknown opcode";
6953 if (! mips16_autoextend
&& ! mips16_ext
)
6954 mips16_small
= true;
6956 if ((insn
= (struct mips_opcode
*) hash_find (mips16_op_hash
, str
)) == NULL
)
6958 insn_error
= "unrecognized opcode";
6965 assert (strcmp (insn
->name
, str
) == 0);
6968 ip
->insn_opcode
= insn
->match
;
6969 ip
->use_extend
= false;
6970 imm_expr
.X_op
= O_absent
;
6971 imm_reloc
= BFD_RELOC_UNUSED
;
6972 offset_expr
.X_op
= O_absent
;
6973 offset_reloc
= BFD_RELOC_UNUSED
;
6974 for (args
= insn
->args
; 1; ++args
)
6981 /* In this switch statement we call break if we did not find
6982 a match, continue if we did find a match, or return if we
6991 /* Stuff the immediate value in now, if we can. */
6992 if (imm_expr
.X_op
== O_constant
6993 && imm_reloc
> BFD_RELOC_UNUSED
6994 && insn
->pinfo
!= INSN_MACRO
)
6996 mips16_immed ((char *) NULL
, 0,
6997 imm_reloc
- BFD_RELOC_UNUSED
,
6998 imm_expr
.X_add_number
, true, mips16_small
,
6999 mips16_ext
, &ip
->insn_opcode
,
7000 &ip
->use_extend
, &ip
->extend
);
7001 imm_expr
.X_op
= O_absent
;
7002 imm_reloc
= BFD_RELOC_UNUSED
;
7016 ip
->insn_opcode
|= lastregno
<< MIPS16OP_SH_RX
;
7019 ip
->insn_opcode
|= lastregno
<< MIPS16OP_SH_RY
;
7035 ip
->insn_opcode
|= lastregno
<< MIPS16OP_SH_RX
;
7037 ip
->insn_opcode
|= lastregno
<< MIPS16OP_SH_RY
;
7064 while (isdigit (*s
));
7067 as_bad ("invalid register number (%d)", regno
);
7073 if (s
[1] == 'f' && s
[2] == 'p')
7078 else if (s
[1] == 's' && s
[2] == 'p')
7083 else if (s
[1] == 'g' && s
[2] == 'p')
7088 else if (s
[1] == 'a' && s
[2] == 't')
7093 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '0')
7098 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '1')
7111 if (c
== 'v' || c
== 'w')
7113 regno
= mips16_to_32_reg_map
[lastregno
];
7127 regno
= mips32_to_16_reg_map
[regno
];
7132 regno
= ILLEGAL_REG
;
7137 regno
= ILLEGAL_REG
;
7142 regno
= ILLEGAL_REG
;
7147 if (regno
== AT
&& ! mips_noat
)
7148 as_warn ("used $at without \".set noat\"");
7155 if (regno
== ILLEGAL_REG
)
7162 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_RX
;
7166 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_RY
;
7169 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_RZ
;
7172 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_MOVE32Z
;
7178 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_REGR32
;
7181 regno
= ((regno
& 7) << 2) | ((regno
& 0x18) >> 3);
7182 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_REG32R
;
7192 if (strncmp (s
, "$pc", 3) == 0)
7216 && strncmp (s
+ 1, "gprel(", sizeof "gprel(" - 1) == 0)
7218 /* This is %gprel(SYMBOL). We need to read SYMBOL,
7219 and generate the appropriate reloc. If the text
7220 inside %gprel is not a symbol name with an
7221 optional offset, then we generate a normal reloc
7222 and will probably fail later. */
7223 my_getExpression (&imm_expr
, s
+ sizeof "%gprel" - 1);
7224 if (imm_expr
.X_op
== O_symbol
)
7227 imm_reloc
= BFD_RELOC_MIPS16_GPREL
;
7229 ip
->use_extend
= true;
7236 /* Just pick up a normal expression. */
7237 my_getExpression (&imm_expr
, s
);
7240 if (imm_expr
.X_op
== O_register
)
7242 /* What we thought was an expression turned out to
7245 if (s
[0] == '(' && args
[1] == '(')
7247 /* It looks like the expression was omitted
7248 before a register indirection, which means
7249 that the expression is implicitly zero. We
7250 still set up imm_expr, so that we handle
7251 explicit extensions correctly. */
7252 imm_expr
.X_op
= O_constant
;
7253 imm_expr
.X_add_number
= 0;
7254 imm_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
7261 /* We need to relax this instruction. */
7262 imm_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
7271 /* We use offset_reloc rather than imm_reloc for the PC
7272 relative operands. This lets macros with both
7273 immediate and address operands work correctly. */
7274 my_getExpression (&offset_expr
, s
);
7276 if (offset_expr
.X_op
== O_register
)
7279 /* We need to relax this instruction. */
7280 offset_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
7284 case '6': /* break code */
7285 my_getExpression (&imm_expr
, s
);
7286 check_absolute_expr (ip
, &imm_expr
);
7287 if ((unsigned long) imm_expr
.X_add_number
> 63)
7289 as_warn ("Invalid value for `%s' (%lu)",
7291 (unsigned long) imm_expr
.X_add_number
);
7292 imm_expr
.X_add_number
&= 0x3f;
7294 ip
->insn_opcode
|= imm_expr
.X_add_number
<< MIPS16OP_SH_IMM6
;
7295 imm_expr
.X_op
= O_absent
;
7299 case 'a': /* 26 bit address */
7300 my_getExpression (&offset_expr
, s
);
7302 offset_reloc
= BFD_RELOC_MIPS16_JMP
;
7303 ip
->insn_opcode
<<= 16;
7306 case 'l': /* register list for entry macro */
7307 case 'L': /* register list for exit macro */
7317 int freg
, reg1
, reg2
;
7319 while (*s
== ' ' || *s
== ',')
7323 as_bad ("can't parse register list");
7335 while (isdigit (*s
))
7357 as_bad ("invalid register list");
7362 while (isdigit (*s
))
7369 if (freg
&& reg1
== 0 && reg2
== 0 && c
== 'L')
7374 else if (freg
&& reg1
== 0 && reg2
== 1 && c
== 'L')
7379 else if (reg1
== 4 && reg2
>= 4 && reg2
<= 7 && c
!= 'L')
7380 mask
|= (reg2
- 3) << 3;
7381 else if (reg1
== 16 && reg2
>= 16 && reg2
<= 17)
7382 mask
|= (reg2
- 15) << 1;
7383 else if (reg1
== 31 && reg2
== 31)
7387 as_bad ("invalid register list");
7391 /* The mask is filled in in the opcode table for the
7392 benefit of the disassembler. We remove it before
7393 applying the actual mask. */
7394 ip
->insn_opcode
&= ~ ((7 << 3) << MIPS16OP_SH_IMM6
);
7395 ip
->insn_opcode
|= mask
<< MIPS16OP_SH_IMM6
;
7399 case 'e': /* extend code */
7400 my_getExpression (&imm_expr
, s
);
7401 check_absolute_expr (ip
, &imm_expr
);
7402 if ((unsigned long) imm_expr
.X_add_number
> 0x7ff)
7404 as_warn ("Invalid value for `%s' (%lu)",
7406 (unsigned long) imm_expr
.X_add_number
);
7407 imm_expr
.X_add_number
&= 0x7ff;
7409 ip
->insn_opcode
|= imm_expr
.X_add_number
;
7410 imm_expr
.X_op
= O_absent
;
7420 /* Args don't match. */
7421 if (insn
+ 1 < &mips16_opcodes
[bfd_mips16_num_opcodes
] &&
7422 strcmp (insn
->name
, insn
[1].name
) == 0)
7429 insn_error
= "illegal operands";
7435 /* This structure holds information we know about a mips16 immediate
7438 struct mips16_immed_operand
7440 /* The type code used in the argument string in the opcode table. */
7442 /* The number of bits in the short form of the opcode. */
7444 /* The number of bits in the extended form of the opcode. */
7446 /* The amount by which the short form is shifted when it is used;
7447 for example, the sw instruction has a shift count of 2. */
7449 /* The amount by which the short form is shifted when it is stored
7450 into the instruction code. */
7452 /* Non-zero if the short form is unsigned. */
7454 /* Non-zero if the extended form is unsigned. */
7456 /* Non-zero if the value is PC relative. */
7460 /* The mips16 immediate operand types. */
7462 static const struct mips16_immed_operand mips16_immed_operands
[] =
7464 { '<', 3, 5, 0, MIPS16OP_SH_RZ
, 1, 1, 0 },
7465 { '>', 3, 5, 0, MIPS16OP_SH_RX
, 1, 1, 0 },
7466 { '[', 3, 6, 0, MIPS16OP_SH_RZ
, 1, 1, 0 },
7467 { ']', 3, 6, 0, MIPS16OP_SH_RX
, 1, 1, 0 },
7468 { '4', 4, 15, 0, MIPS16OP_SH_IMM4
, 0, 0, 0 },
7469 { '5', 5, 16, 0, MIPS16OP_SH_IMM5
, 1, 0, 0 },
7470 { 'H', 5, 16, 1, MIPS16OP_SH_IMM5
, 1, 0, 0 },
7471 { 'W', 5, 16, 2, MIPS16OP_SH_IMM5
, 1, 0, 0 },
7472 { 'D', 5, 16, 3, MIPS16OP_SH_IMM5
, 1, 0, 0 },
7473 { 'j', 5, 16, 0, MIPS16OP_SH_IMM5
, 0, 0, 0 },
7474 { '8', 8, 16, 0, MIPS16OP_SH_IMM8
, 1, 0, 0 },
7475 { 'V', 8, 16, 2, MIPS16OP_SH_IMM8
, 1, 0, 0 },
7476 { 'C', 8, 16, 3, MIPS16OP_SH_IMM8
, 1, 0, 0 },
7477 { 'U', 8, 16, 0, MIPS16OP_SH_IMM8
, 1, 1, 0 },
7478 { 'k', 8, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 0 },
7479 { 'K', 8, 16, 3, MIPS16OP_SH_IMM8
, 0, 0, 0 },
7480 { 'p', 8, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 1 },
7481 { 'q', 11, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 1 },
7482 { 'A', 8, 16, 2, MIPS16OP_SH_IMM8
, 1, 0, 1 },
7483 { 'B', 5, 16, 3, MIPS16OP_SH_IMM5
, 1, 0, 1 },
7484 { 'E', 5, 16, 2, MIPS16OP_SH_IMM5
, 1, 0, 1 }
7487 #define MIPS16_NUM_IMMED \
7488 (sizeof mips16_immed_operands / sizeof mips16_immed_operands[0])
7490 /* Handle a mips16 instruction with an immediate value. This or's the
7491 small immediate value into *INSN. It sets *USE_EXTEND to indicate
7492 whether an extended value is needed; if one is needed, it sets
7493 *EXTEND to the value. The argument type is TYPE. The value is VAL.
7494 If SMALL is true, an unextended opcode was explicitly requested.
7495 If EXT is true, an extended opcode was explicitly requested. If
7496 WARN is true, warn if EXT does not match reality. */
7499 mips16_immed (file
, line
, type
, val
, warn
, small
, ext
, insn
, use_extend
,
7508 unsigned long *insn
;
7509 boolean
*use_extend
;
7510 unsigned short *extend
;
7512 register const struct mips16_immed_operand
*op
;
7513 int mintiny
, maxtiny
;
7516 op
= mips16_immed_operands
;
7517 while (op
->type
!= type
)
7520 assert (op
< mips16_immed_operands
+ MIPS16_NUM_IMMED
);
7525 if (type
== '<' || type
== '>' || type
== '[' || type
== ']')
7528 maxtiny
= 1 << op
->nbits
;
7533 maxtiny
= (1 << op
->nbits
) - 1;
7538 mintiny
= - (1 << (op
->nbits
- 1));
7539 maxtiny
= (1 << (op
->nbits
- 1)) - 1;
7542 /* Branch offsets have an implicit 0 in the lowest bit. */
7543 if (type
== 'p' || type
== 'q')
7546 if ((val
& ((1 << op
->shift
) - 1)) != 0
7547 || val
< (mintiny
<< op
->shift
)
7548 || val
> (maxtiny
<< op
->shift
))
7553 if (warn
&& ext
&& ! needext
)
7554 as_warn_where (file
, line
, "extended operand requested but not required");
7555 if (small
&& needext
)
7556 as_bad_where (file
, line
, "invalid unextended operand value");
7558 if (small
|| (! ext
&& ! needext
))
7562 *use_extend
= false;
7563 insnval
= ((val
>> op
->shift
) & ((1 << op
->nbits
) - 1));
7564 insnval
<<= op
->op_shift
;
7569 long minext
, maxext
;
7575 maxext
= (1 << op
->extbits
) - 1;
7579 minext
= - (1 << (op
->extbits
- 1));
7580 maxext
= (1 << (op
->extbits
- 1)) - 1;
7582 if (val
< minext
|| val
> maxext
)
7583 as_bad_where (file
, line
,
7584 "operand value out of range for instruction");
7587 if (op
->extbits
== 16)
7589 extval
= ((val
>> 11) & 0x1f) | (val
& 0x7e0);
7592 else if (op
->extbits
== 15)
7594 extval
= ((val
>> 11) & 0xf) | (val
& 0x7f0);
7599 extval
= ((val
& 0x1f) << 6) | (val
& 0x20);
7603 *extend
= (unsigned short) extval
;
7612 my_getSmallExpression (ep
, str
)
7623 ((str
[1] == 'h' && str
[2] == 'i')
7624 || (str
[1] == 'H' && str
[2] == 'I')
7625 || (str
[1] == 'l' && str
[2] == 'o'))
7637 * A small expression may be followed by a base register.
7638 * Scan to the end of this operand, and then back over a possible
7639 * base register. Then scan the small expression up to that
7640 * point. (Based on code in sparc.c...)
7642 for (sp
= str
; *sp
&& *sp
!= ','; sp
++)
7644 if (sp
- 4 >= str
&& sp
[-1] == RP
)
7646 if (isdigit (sp
[-2]))
7648 for (sp
-= 3; sp
>= str
&& isdigit (*sp
); sp
--)
7650 if (*sp
== '$' && sp
> str
&& sp
[-1] == LP
)
7656 else if (sp
- 5 >= str
7659 && ((sp
[-3] == 'f' && sp
[-2] == 'p')
7660 || (sp
[-3] == 's' && sp
[-2] == 'p')
7661 || (sp
[-3] == 'g' && sp
[-2] == 'p')
7662 || (sp
[-3] == 'a' && sp
[-2] == 't')))
7668 /* no expression means zero offset */
7671 /* %xx(reg) is an error */
7672 ep
->X_op
= O_absent
;
7677 ep
->X_op
= O_constant
;
7680 ep
->X_add_symbol
= NULL
;
7681 ep
->X_op_symbol
= NULL
;
7682 ep
->X_add_number
= 0;
7687 my_getExpression (ep
, str
);
7694 my_getExpression (ep
, str
);
7695 return c
; /* => %hi or %lo encountered */
7699 my_getExpression (ep
, str
)
7705 save_in
= input_line_pointer
;
7706 input_line_pointer
= str
;
7708 expr_end
= input_line_pointer
;
7709 input_line_pointer
= save_in
;
7711 /* If we are in mips16 mode, and this is an expression based on `.',
7712 then we bump the value of the symbol by 1 since that is how other
7713 text symbols are handled. We don't bother to handle complex
7714 expressions, just `.' plus or minus a constant. */
7716 && ep
->X_op
== O_symbol
7717 && strcmp (S_GET_NAME (ep
->X_add_symbol
), FAKE_LABEL_NAME
) == 0
7718 && S_GET_SEGMENT (ep
->X_add_symbol
) == now_seg
7719 && ep
->X_add_symbol
->sy_frag
== frag_now
7720 && ep
->X_add_symbol
->sy_value
.X_op
== O_constant
7721 && ep
->X_add_symbol
->sy_value
.X_add_number
== frag_now_fix ())
7722 ++ep
->X_add_symbol
->sy_value
.X_add_number
;
7725 /* Turn a string in input_line_pointer into a floating point constant
7726 of type type, and store the appropriate bytes in *litP. The number
7727 of LITTLENUMS emitted is stored in *sizeP . An error message is
7728 returned, or NULL on OK. */
7731 md_atof (type
, litP
, sizeP
)
7737 LITTLENUM_TYPE words
[4];
7753 return "bad call to md_atof";
7756 t
= atof_ieee (input_line_pointer
, type
, words
);
7758 input_line_pointer
= t
;
7762 if (! target_big_endian
)
7764 for (i
= prec
- 1; i
>= 0; i
--)
7766 md_number_to_chars (litP
, (valueT
) words
[i
], 2);
7772 for (i
= 0; i
< prec
; i
++)
7774 md_number_to_chars (litP
, (valueT
) words
[i
], 2);
7783 md_number_to_chars (buf
, val
, n
)
7788 if (target_big_endian
)
7789 number_to_chars_bigendian (buf
, val
, n
);
7791 number_to_chars_littleendian (buf
, val
, n
);
7794 CONST
char *md_shortopts
= "O::g::G:";
7796 struct option md_longopts
[] = {
7797 #define OPTION_MIPS1 (OPTION_MD_BASE + 1)
7798 {"mips0", no_argument
, NULL
, OPTION_MIPS1
},
7799 {"mips1", no_argument
, NULL
, OPTION_MIPS1
},
7800 #define OPTION_MIPS2 (OPTION_MD_BASE + 2)
7801 {"mips2", no_argument
, NULL
, OPTION_MIPS2
},
7802 #define OPTION_MIPS3 (OPTION_MD_BASE + 3)
7803 {"mips3", no_argument
, NULL
, OPTION_MIPS3
},
7804 #define OPTION_MIPS4 (OPTION_MD_BASE + 4)
7805 {"mips4", no_argument
, NULL
, OPTION_MIPS4
},
7806 #define OPTION_MCPU (OPTION_MD_BASE + 5)
7807 {"mcpu", required_argument
, NULL
, OPTION_MCPU
},
7808 #define OPTION_MEMBEDDED_PIC (OPTION_MD_BASE + 6)
7809 {"membedded-pic", no_argument
, NULL
, OPTION_MEMBEDDED_PIC
},
7810 #define OPTION_TRAP (OPTION_MD_BASE + 9)
7811 {"trap", no_argument
, NULL
, OPTION_TRAP
},
7812 {"no-break", no_argument
, NULL
, OPTION_TRAP
},
7813 #define OPTION_BREAK (OPTION_MD_BASE + 10)
7814 {"break", no_argument
, NULL
, OPTION_BREAK
},
7815 {"no-trap", no_argument
, NULL
, OPTION_BREAK
},
7816 #define OPTION_EB (OPTION_MD_BASE + 11)
7817 {"EB", no_argument
, NULL
, OPTION_EB
},
7818 #define OPTION_EL (OPTION_MD_BASE + 12)
7819 {"EL", no_argument
, NULL
, OPTION_EL
},
7820 #define OPTION_M4650 (OPTION_MD_BASE + 13)
7821 {"m4650", no_argument
, NULL
, OPTION_M4650
},
7822 #define OPTION_NO_M4650 (OPTION_MD_BASE + 14)
7823 {"no-m4650", no_argument
, NULL
, OPTION_NO_M4650
},
7824 #define OPTION_M4010 (OPTION_MD_BASE + 15)
7825 {"m4010", no_argument
, NULL
, OPTION_M4010
},
7826 #define OPTION_NO_M4010 (OPTION_MD_BASE + 16)
7827 {"no-m4010", no_argument
, NULL
, OPTION_NO_M4010
},
7828 #define OPTION_M4100 (OPTION_MD_BASE + 17)
7829 {"m4100", no_argument
, NULL
, OPTION_M4100
},
7830 #define OPTION_NO_M4100 (OPTION_MD_BASE + 18)
7831 {"no-m4100", no_argument
, NULL
, OPTION_NO_M4100
},
7832 #define OPTION_MIPS16 (OPTION_MD_BASE + 22)
7833 {"mips16", no_argument
, NULL
, OPTION_MIPS16
},
7834 #define OPTION_NO_MIPS16 (OPTION_MD_BASE + 23)
7835 {"no-mips16", no_argument
, NULL
, OPTION_NO_MIPS16
},
7836 /* start-sanitize-5900 */
7837 #define OPTION_M5900 (OPTION_MD_BASE + 24)
7838 {"m5900", no_argument
, NULL
, OPTION_M5900
},
7839 #define OPTION_NO_M5900 (OPTION_MD_BASE + 25)
7840 {"no-m5900", no_argument
, NULL
, OPTION_NO_M5900
},
7841 /* end-sanitize-5900 */
7843 #define OPTION_CALL_SHARED (OPTION_MD_BASE + 7)
7844 #define OPTION_NON_SHARED (OPTION_MD_BASE + 8)
7845 #define OPTION_XGOT (OPTION_MD_BASE + 19)
7846 #define OPTION_32 (OPTION_MD_BASE + 20)
7847 #define OPTION_64 (OPTION_MD_BASE + 21)
7849 {"KPIC", no_argument
, NULL
, OPTION_CALL_SHARED
},
7850 {"xgot", no_argument
, NULL
, OPTION_XGOT
},
7851 {"call_shared", no_argument
, NULL
, OPTION_CALL_SHARED
},
7852 {"non_shared", no_argument
, NULL
, OPTION_NON_SHARED
},
7853 {"32", no_argument
, NULL
, OPTION_32
},
7854 {"64", no_argument
, NULL
, OPTION_64
},
7857 {NULL
, no_argument
, NULL
, 0}
7859 size_t md_longopts_size
= sizeof(md_longopts
);
7862 md_parse_option (c
, arg
)
7877 target_big_endian
= 1;
7881 target_big_endian
= 0;
7885 if (arg
&& arg
[1] == '0')
7895 mips_debug
= atoi (arg
);
7896 /* When the MIPS assembler sees -g or -g2, it does not do
7897 optimizations which limit full symbolic debugging. We take
7898 that to be equivalent to -O0. */
7899 if (mips_debug
== 2)
7931 /* Identify the processor type */
7933 if (strcmp (p
, "default") == 0
7934 || strcmp (p
, "DEFAULT") == 0)
7940 /* We need to cope with the various "vr" prefixes for the 4300
7942 if (*p
== 'v' || *p
== 'V')
7948 if (*p
== 'r' || *p
== 'R')
7955 if (strcmp (p
, "10000") == 0
7956 || strcmp (p
, "10k") == 0
7957 || strcmp (p
, "10K") == 0)
7962 if (strcmp (p
, "2000") == 0
7963 || strcmp (p
, "2k") == 0
7964 || strcmp (p
, "2K") == 0)
7969 if (strcmp (p
, "3000") == 0
7970 || strcmp (p
, "3k") == 0
7971 || strcmp (p
, "3K") == 0)
7976 if (strcmp (p
, "4000") == 0
7977 || strcmp (p
, "4k") == 0
7978 || strcmp (p
, "4K") == 0)
7980 else if (strcmp (p
, "4100") == 0)
7986 else if (strcmp (p
, "4300") == 0)
7988 else if (strcmp (p
, "4400") == 0)
7990 else if (strcmp (p
, "4600") == 0)
7992 else if (strcmp (p
, "4650") == 0)
7998 else if (strcmp (p
, "4010") == 0)
8007 if (strcmp (p
, "5000") == 0
8008 || strcmp (p
, "5k") == 0
8009 || strcmp (p
, "5K") == 0)
8011 /* start-sanitize-r5900 */
8012 else if (strcmp (p
, "5900") == 0)
8014 /* end-sanitize-r5900 */
8018 if (strcmp (p
, "6000") == 0
8019 || strcmp (p
, "6k") == 0
8020 || strcmp (p
, "6K") == 0)
8025 if (strcmp (p
, "8000") == 0
8026 || strcmp (p
, "8k") == 0
8027 || strcmp (p
, "8K") == 0)
8032 if (strcmp (p
, "orion") == 0)
8037 if (sv
&& mips_cpu
!= 4300 && mips_cpu
!= 4100 && mips_cpu
!= 5000)
8039 as_bad ("ignoring invalid leading 'v' in -mcpu=%s switch", arg
);
8045 as_bad ("invalid architecture -mcpu=%s", arg
);
8056 case OPTION_NO_M4650
:
8064 case OPTION_NO_M4010
:
8072 case OPTION_NO_M4100
:
8076 /* start-sanitize-r5900 */
8081 case OPTION_NO_M5900
:
8084 /* end-sanitize-r5900 */
8088 mips_no_prev_insn ();
8091 case OPTION_NO_MIPS16
:
8093 mips_no_prev_insn ();
8096 case OPTION_MEMBEDDED_PIC
:
8097 mips_pic
= EMBEDDED_PIC
;
8098 if (USE_GLOBAL_POINTER_OPT
&& g_switch_seen
)
8100 as_bad ("-G may not be used with embedded PIC code");
8103 g_switch_value
= 0x7fffffff;
8106 /* When generating ELF code, we permit -KPIC and -call_shared to
8107 select SVR4_PIC, and -non_shared to select no PIC. This is
8108 intended to be compatible with Irix 5. */
8109 case OPTION_CALL_SHARED
:
8110 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
8112 as_bad ("-call_shared is supported only for ELF format");
8115 mips_pic
= SVR4_PIC
;
8116 if (g_switch_seen
&& g_switch_value
!= 0)
8118 as_bad ("-G may not be used with SVR4 PIC code");
8124 case OPTION_NON_SHARED
:
8125 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
8127 as_bad ("-non_shared is supported only for ELF format");
8133 /* The -xgot option tells the assembler to use 32 offsets when
8134 accessing the got in SVR4_PIC mode. It is for Irix
8141 if (! USE_GLOBAL_POINTER_OPT
)
8143 as_bad ("-G is not supported for this configuration");
8146 else if (mips_pic
== SVR4_PIC
|| mips_pic
== EMBEDDED_PIC
)
8148 as_bad ("-G may not be used with SVR4 or embedded PIC code");
8152 g_switch_value
= atoi (arg
);
8156 /* The -32 and -64 options tell the assembler to output the 32
8157 bit or the 64 bit MIPS ELF format. */
8164 const char **list
, **l
;
8166 list
= bfd_target_list ();
8167 for (l
= list
; *l
!= NULL
; l
++)
8168 if (strcmp (*l
, "elf64-bigmips") == 0
8169 || strcmp (*l
, "elf64-littlemips") == 0)
8172 as_fatal ("No compiled in support for 64 bit object file format");
8186 md_show_usage (stream
)
8191 -membedded-pic generate embedded position independent code\n\
8192 -EB generate big endian output\n\
8193 -EL generate little endian output\n\
8194 -g, -g2 do not remove uneeded NOPs or swap branches\n\
8195 -G NUM allow referencing objects up to NUM bytes\n\
8196 implicitly with the gp register [default 8]\n");
8198 -mips1, -mcpu=r{2,3}000 generate code for r2000 and r3000\n\
8199 -mips2, -mcpu=r6000 generate code for r6000\n\
8200 -mips3, -mcpu=r4000 generate code for r4000\n\
8201 -mips4, -mcpu=r8000 generate code for r8000\n\
8202 -mcpu=vr4300 generate code for vr4300\n\
8203 -mcpu=vr4100 generate code for vr4100\n\
8204 -m4650 permit R4650 instructions\n\
8205 -no-m4650 do not permit R4650 instructions\n\
8206 -m4010 permit R4010 instructions\n\
8207 -no-m4010 do not permit R4010 instructions\n\
8208 -m4100 permit VR4100 instructions\n\
8209 -no-m4100 do not permit VR4100 instructions\n");
8211 -mips16 generate mips16 instructions\n\
8212 -no-mips16 do not generate mips16 instructions\n");
8214 -O0 remove unneeded NOPs, do not swap branches\n\
8215 -O remove unneeded NOPs and swap branches\n\
8216 --trap, --no-break trap exception on div by 0 and mult overflow\n\
8217 --break, --no-trap break exception on div by 0 and mult overflow\n");
8220 -KPIC, -call_shared generate SVR4 position independent code\n\
8221 -non_shared do not generate position independent code\n\
8222 -xgot assume a 32 bit GOT\n\
8223 -32 create 32 bit object file (default)\n\
8224 -64 create 64 bit object file\n");
8229 md_pcrel_from (fixP
)
8232 if (OUTPUT_FLAVOR
!= bfd_target_aout_flavour
8233 && fixP
->fx_addsy
!= (symbolS
*) NULL
8234 && ! S_IS_DEFINED (fixP
->fx_addsy
))
8236 /* This makes a branch to an undefined symbol be a branch to the
8237 current location. */
8241 /* return the address of the delay slot */
8242 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
8245 /* This is called by emit_expr via TC_CONS_FIX_NEW when creating a
8246 reloc for a cons. We could use the definition there, except that
8247 we want to handle 64 bit relocs specially. */
8250 cons_fix_new_mips (frag
, where
, nbytes
, exp
)
8253 unsigned int nbytes
;
8257 /* If we are assembling in 32 bit mode, turn an 8 byte reloc into a
8259 if (nbytes
== 8 && ! mips_64
)
8261 if (target_big_endian
)
8267 if (nbytes
!= 2 && nbytes
!= 4 && nbytes
!= 8)
8268 as_bad ("Unsupported reloc size %d", nbytes
);
8270 fix_new_exp (frag_now
, where
, (int) nbytes
, exp
, 0,
8273 : (nbytes
== 4 ? BFD_RELOC_32
: BFD_RELOC_64
)));
8276 /* Sort any unmatched HI16_S relocs so that they immediately precede
8277 the corresponding LO reloc. This is called before md_apply_fix and
8278 tc_gen_reloc. Unmatched HI16_S relocs can only be generated by
8279 explicit use of the %hi modifier. */
8284 struct mips_hi_fixup
*l
;
8286 for (l
= mips_hi_fixup_list
; l
!= NULL
; l
= l
->next
)
8288 segment_info_type
*seginfo
;
8291 assert (l
->fixp
->fx_r_type
== BFD_RELOC_HI16_S
);
8293 /* Check quickly whether the next fixup happens to be a matching
8295 if (l
->fixp
->fx_next
!= NULL
8296 && l
->fixp
->fx_next
->fx_r_type
== BFD_RELOC_LO16
8297 && l
->fixp
->fx_addsy
== l
->fixp
->fx_next
->fx_addsy
8298 && l
->fixp
->fx_offset
== l
->fixp
->fx_next
->fx_offset
)
8301 /* Look through the fixups for this segment for a matching %lo.
8302 When we find one, move the %hi just in front of it. We do
8303 this in two passes. In the first pass, we try to find a
8304 unique %lo. In the second pass, we permit multiple %hi
8305 relocs for a single %lo (this is a GNU extension). */
8306 seginfo
= seg_info (l
->seg
);
8307 for (pass
= 0; pass
< 2; pass
++)
8312 for (f
= seginfo
->fix_root
; f
!= NULL
; f
= f
->fx_next
)
8314 /* Check whether this is a %lo fixup which matches l->fixp. */
8315 if (f
->fx_r_type
== BFD_RELOC_LO16
8316 && f
->fx_addsy
== l
->fixp
->fx_addsy
8317 && f
->fx_offset
== l
->fixp
->fx_offset
8320 || prev
->fx_r_type
!= BFD_RELOC_HI16_S
8321 || prev
->fx_addsy
!= f
->fx_addsy
8322 || prev
->fx_offset
!= f
->fx_offset
))
8326 /* Move l->fixp before f. */
8327 for (pf
= &seginfo
->fix_root
;
8329 pf
= &(*pf
)->fx_next
)
8330 assert (*pf
!= NULL
);
8332 *pf
= l
->fixp
->fx_next
;
8334 l
->fixp
->fx_next
= f
;
8336 seginfo
->fix_root
= l
->fixp
;
8338 prev
->fx_next
= l
->fixp
;
8350 as_warn_where (l
->fixp
->fx_file
, l
->fixp
->fx_line
,
8351 "Unmatched %%hi reloc");
8356 /* When generating embedded PIC code we need to use a special
8357 relocation to represent the difference of two symbols in the .text
8358 section (switch tables use a difference of this sort). See
8359 include/coff/mips.h for details. This macro checks whether this
8360 fixup requires the special reloc. */
8361 #define SWITCH_TABLE(fixp) \
8362 ((fixp)->fx_r_type == BFD_RELOC_32 \
8363 && (fixp)->fx_addsy != NULL \
8364 && (fixp)->fx_subsy != NULL \
8365 && S_GET_SEGMENT ((fixp)->fx_addsy) == text_section \
8366 && S_GET_SEGMENT ((fixp)->fx_subsy) == text_section)
8368 /* When generating embedded PIC code we must keep all PC relative
8369 relocations, in case the linker has to relax a call. We also need
8370 to keep relocations for switch table entries. */
8374 mips_force_relocation (fixp
)
8377 return (mips_pic
== EMBEDDED_PIC
8379 || SWITCH_TABLE (fixp
)
8380 || fixp
->fx_r_type
== BFD_RELOC_PCREL_HI16_S
8381 || fixp
->fx_r_type
== BFD_RELOC_PCREL_LO16
));
8384 /* Apply a fixup to the object file. */
8387 md_apply_fix (fixP
, valueP
)
8394 assert (fixP
->fx_size
== 4
8395 || fixP
->fx_r_type
== BFD_RELOC_16
8396 || fixP
->fx_r_type
== BFD_RELOC_64
);
8400 /* If we aren't adjusting this fixup to be against the section
8401 symbol, we need to adjust the value. */
8403 if (fixP
->fx_addsy
!= NULL
8404 && OUTPUT_FLAVOR
== bfd_target_elf_flavour
8405 && S_GET_OTHER (fixP
->fx_addsy
) == STO_MIPS16
)
8407 value
-= S_GET_VALUE (fixP
->fx_addsy
);
8408 if (value
!= 0 && ! fixP
->fx_pcrel
)
8410 /* In this case, the bfd_install_relocation routine will
8411 incorrectly add the symbol value back in. We just want
8412 the addend to appear in the object file. */
8413 value
-= S_GET_VALUE (fixP
->fx_addsy
);
8418 fixP
->fx_addnumber
= value
; /* Remember value for tc_gen_reloc */
8420 if (fixP
->fx_addsy
== NULL
&& ! fixP
->fx_pcrel
)
8423 switch (fixP
->fx_r_type
)
8425 case BFD_RELOC_MIPS_JMP
:
8426 case BFD_RELOC_HI16
:
8427 case BFD_RELOC_HI16_S
:
8428 case BFD_RELOC_MIPS_GPREL
:
8429 case BFD_RELOC_MIPS_LITERAL
:
8430 case BFD_RELOC_MIPS_CALL16
:
8431 case BFD_RELOC_MIPS_GOT16
:
8432 case BFD_RELOC_MIPS_GPREL32
:
8433 case BFD_RELOC_MIPS_GOT_HI16
:
8434 case BFD_RELOC_MIPS_GOT_LO16
:
8435 case BFD_RELOC_MIPS_CALL_HI16
:
8436 case BFD_RELOC_MIPS_CALL_LO16
:
8437 case BFD_RELOC_MIPS16_GPREL
:
8439 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
8440 "Invalid PC relative reloc");
8441 /* Nothing needed to do. The value comes from the reloc entry */
8444 case BFD_RELOC_MIPS16_JMP
:
8445 /* We currently always generate a reloc against a symbol, which
8446 means that we don't want an addend even if the symbol is
8448 fixP
->fx_addnumber
= 0;
8451 case BFD_RELOC_PCREL_HI16_S
:
8452 /* The addend for this is tricky if it is internal, so we just
8453 do everything here rather than in bfd_perform_relocation. */
8454 if ((fixP
->fx_addsy
->bsym
->flags
& BSF_SECTION_SYM
) == 0)
8456 /* For an external symbol adjust by the address to make it
8457 pcrel_offset. We use the address of the RELLO reloc
8458 which follows this one. */
8459 value
+= (fixP
->fx_next
->fx_frag
->fr_address
8460 + fixP
->fx_next
->fx_where
);
8465 buf
= (unsigned char *) fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
8466 if (target_big_endian
)
8468 md_number_to_chars (buf
, value
, 2);
8471 case BFD_RELOC_PCREL_LO16
:
8472 /* The addend for this is tricky if it is internal, so we just
8473 do everything here rather than in bfd_perform_relocation. */
8474 if ((fixP
->fx_addsy
->bsym
->flags
& BSF_SECTION_SYM
) == 0)
8475 value
+= fixP
->fx_frag
->fr_address
+ fixP
->fx_where
;
8476 buf
= (unsigned char *) fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
8477 if (target_big_endian
)
8479 md_number_to_chars (buf
, value
, 2);
8483 /* This is handled like BFD_RELOC_32, but we output a sign
8484 extended value if we are only 32 bits. */
8486 || (mips_pic
== EMBEDDED_PIC
&& SWITCH_TABLE (fixP
)))
8488 if (8 <= sizeof (valueT
))
8489 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
,
8496 w1
= w2
= fixP
->fx_where
;
8497 if (target_big_endian
)
8501 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ w1
, value
, 4);
8502 if ((value
& 0x80000000) != 0)
8506 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ w2
, hiv
, 4);
8512 /* If we are deleting this reloc entry, we must fill in the
8513 value now. This can happen if we have a .word which is not
8514 resolved when it appears but is later defined. We also need
8515 to fill in the value if this is an embedded PIC switch table
8518 || (mips_pic
== EMBEDDED_PIC
&& SWITCH_TABLE (fixP
)))
8519 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
,
8524 /* If we are deleting this reloc entry, we must fill in the
8526 assert (fixP
->fx_size
== 2);
8528 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
,
8532 case BFD_RELOC_LO16
:
8533 /* When handling an embedded PIC switch statement, we can wind
8534 up deleting a LO16 reloc. See the 'o' case in mips_ip. */
8537 if (value
< -0x8000 || value
> 0x7fff)
8538 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
8539 "relocation overflow");
8540 buf
= (unsigned char *) fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
8541 if (target_big_endian
)
8543 md_number_to_chars (buf
, value
, 2);
8547 case BFD_RELOC_16_PCREL_S2
:
8549 * We need to save the bits in the instruction since fixup_segment()
8550 * might be deleting the relocation entry (i.e., a branch within
8551 * the current segment).
8553 if ((value
& 0x3) != 0)
8554 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
8555 "Branch to odd address (%lx)", value
);
8558 /* update old instruction data */
8559 buf
= (unsigned char *) (fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
);
8560 if (target_big_endian
)
8561 insn
= (buf
[0] << 24) | (buf
[1] << 16) | (buf
[2] << 8) | buf
[3];
8563 insn
= (buf
[3] << 24) | (buf
[2] << 16) | (buf
[1] << 8) | buf
[0];
8565 if (value
>= -0x8000 && value
< 0x8000)
8566 insn
|= value
& 0xffff;
8569 /* The branch offset is too large. If this is an
8570 unconditional branch, and we are not generating PIC code,
8571 we can convert it to an absolute jump instruction. */
8572 if (mips_pic
== NO_PIC
8574 && fixP
->fx_frag
->fr_address
>= text_section
->vma
8575 && (fixP
->fx_frag
->fr_address
8576 < text_section
->vma
+ text_section
->_raw_size
)
8577 && ((insn
& 0xffff0000) == 0x10000000 /* beq $0,$0 */
8578 || (insn
& 0xffff0000) == 0x04010000 /* bgez $0 */
8579 || (insn
& 0xffff0000) == 0x04110000)) /* bgezal $0 */
8581 if ((insn
& 0xffff0000) == 0x04110000) /* bgezal $0 */
8582 insn
= 0x0c000000; /* jal */
8584 insn
= 0x08000000; /* j */
8585 fixP
->fx_r_type
= BFD_RELOC_MIPS_JMP
;
8587 fixP
->fx_addsy
= section_symbol (text_section
);
8588 fixP
->fx_addnumber
= (value
<< 2) + md_pcrel_from (fixP
);
8592 /* FIXME. It would be possible in principle to handle
8593 conditional branches which overflow. They could be
8594 transformed into a branch around a jump. This would
8595 require setting up variant frags for each different
8596 branch type. The native MIPS assembler attempts to
8597 handle these cases, but it appears to do it
8599 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
8600 "Relocation overflow");
8604 md_number_to_chars ((char *) buf
, (valueT
) insn
, 4);
8619 const struct mips_opcode
*p
;
8620 int treg
, sreg
, dreg
, shamt
;
8625 for (i
= 0; i
< NUMOPCODES
; ++i
)
8627 p
= &mips_opcodes
[i
];
8628 if (((oc
& p
->mask
) == p
->match
) && (p
->pinfo
!= INSN_MACRO
))
8630 printf ("%08lx %s\t", oc
, p
->name
);
8631 treg
= (oc
>> 16) & 0x1f;
8632 sreg
= (oc
>> 21) & 0x1f;
8633 dreg
= (oc
>> 11) & 0x1f;
8634 shamt
= (oc
>> 6) & 0x1f;
8636 for (args
= p
->args
;; ++args
)
8647 printf ("%c", *args
);
8651 assert (treg
== sreg
);
8652 printf ("$%d,$%d", treg
, sreg
);
8657 printf ("$%d", dreg
);
8662 printf ("$%d", treg
);
8666 printf ("0x%x", treg
);
8671 printf ("$%d", sreg
);
8675 printf ("0x%08lx", oc
& 0x1ffffff);
8687 printf ("$%d", shamt
);
8698 printf ("%08lx UNDEFINED\n", oc
);
8709 name
= input_line_pointer
;
8710 c
= get_symbol_end ();
8711 p
= (symbolS
*) symbol_find_or_make (name
);
8712 *input_line_pointer
= c
;
8716 /* Align the current frag to a given power of two. The MIPS assembler
8717 also automatically adjusts any preceding label. */
8720 mips_align (to
, fill
, label
)
8725 mips_emit_delays (false);
8726 frag_align (to
, fill
);
8727 record_alignment (now_seg
, to
);
8730 assert (S_GET_SEGMENT (label
) == now_seg
);
8731 label
->sy_frag
= frag_now
;
8732 S_SET_VALUE (label
, (valueT
) frag_now_fix ());
8736 /* Align to a given power of two. .align 0 turns off the automatic
8737 alignment used by the data creating pseudo-ops. */
8744 register long temp_fill
;
8745 long max_alignment
= 15;
8749 o Note that the assembler pulls down any immediately preceeding label
8750 to the aligned address.
8751 o It's not documented but auto alignment is reinstated by
8752 a .align pseudo instruction.
8753 o Note also that after auto alignment is turned off the mips assembler
8754 issues an error on attempt to assemble an improperly aligned data item.
8759 temp
= get_absolute_expression ();
8760 if (temp
> max_alignment
)
8761 as_bad ("Alignment too large: %d. assumed.", temp
= max_alignment
);
8764 as_warn ("Alignment negative: 0 assumed.");
8767 if (*input_line_pointer
== ',')
8769 input_line_pointer
++;
8770 temp_fill
= get_absolute_expression ();
8777 mips_align (temp
, (int) temp_fill
,
8778 insn_labels
!= NULL
? insn_labels
->label
: NULL
);
8785 demand_empty_rest_of_line ();
8789 mips_flush_pending_output ()
8791 mips_emit_delays (false);
8792 mips_clear_insn_labels ();
8801 /* When generating embedded PIC code, we only use the .text, .lit8,
8802 .sdata and .sbss sections. We change the .data and .rdata
8803 pseudo-ops to use .sdata. */
8804 if (mips_pic
== EMBEDDED_PIC
8805 && (sec
== 'd' || sec
== 'r'))
8808 mips_emit_delays (false);
8818 subseg_set (bss_section
, (subsegT
) get_absolute_expression ());
8819 demand_empty_rest_of_line ();
8823 if (USE_GLOBAL_POINTER_OPT
)
8825 seg
= subseg_new (RDATA_SECTION_NAME
,
8826 (subsegT
) get_absolute_expression ());
8827 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
8829 bfd_set_section_flags (stdoutput
, seg
,
8835 if (strcmp (TARGET_OS
, "elf") != 0)
8836 bfd_set_section_alignment (stdoutput
, seg
, 4);
8838 demand_empty_rest_of_line ();
8842 as_bad ("No read only data section in this object file format");
8843 demand_empty_rest_of_line ();
8849 if (USE_GLOBAL_POINTER_OPT
)
8851 seg
= subseg_new (".sdata", (subsegT
) get_absolute_expression ());
8852 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
8854 bfd_set_section_flags (stdoutput
, seg
,
8855 SEC_ALLOC
| SEC_LOAD
| SEC_RELOC
8857 if (strcmp (TARGET_OS
, "elf") != 0)
8858 bfd_set_section_alignment (stdoutput
, seg
, 4);
8860 demand_empty_rest_of_line ();
8865 as_bad ("Global pointers not supported; recompile -G 0");
8866 demand_empty_rest_of_line ();
8875 mips_enable_auto_align ()
8886 label
= insn_labels
!= NULL
? insn_labels
->label
: NULL
;
8887 mips_emit_delays (false);
8888 if (log_size
> 0 && auto_align
)
8889 mips_align (log_size
, 0, label
);
8890 mips_clear_insn_labels ();
8891 cons (1 << log_size
);
8900 label
= insn_labels
!= NULL
? insn_labels
->label
: NULL
;
8902 mips_emit_delays (false);
8906 mips_align (3, 0, label
);
8908 mips_align (2, 0, label
);
8910 mips_clear_insn_labels ();
8915 /* Handle .globl. We need to override it because on Irix 5 you are
8918 where foo is an undefined symbol, to mean that foo should be
8919 considered to be the address of a function. */
8930 name
= input_line_pointer
;
8931 c
= get_symbol_end ();
8932 symbolP
= symbol_find_or_make (name
);
8933 *input_line_pointer
= c
;
8936 /* On Irix 5, every global symbol that is not explicitly labelled as
8937 being a function is apparently labelled as being an object. */
8940 if (! is_end_of_line
[(unsigned char) *input_line_pointer
])
8945 secname
= input_line_pointer
;
8946 c
= get_symbol_end ();
8947 sec
= bfd_get_section_by_name (stdoutput
, secname
);
8949 as_bad ("%s: no such section", secname
);
8950 *input_line_pointer
= c
;
8952 if (sec
!= NULL
&& (sec
->flags
& SEC_CODE
) != 0)
8953 flag
= BSF_FUNCTION
;
8956 symbolP
->bsym
->flags
|= flag
;
8958 S_SET_EXTERNAL (symbolP
);
8959 demand_empty_rest_of_line ();
8969 opt
= input_line_pointer
;
8970 c
= get_symbol_end ();
8974 /* FIXME: What does this mean? */
8976 else if (strncmp (opt
, "pic", 3) == 0)
8984 mips_pic
= SVR4_PIC
;
8986 as_bad (".option pic%d not supported", i
);
8988 if (USE_GLOBAL_POINTER_OPT
&& mips_pic
== SVR4_PIC
)
8990 if (g_switch_seen
&& g_switch_value
!= 0)
8991 as_warn ("-G may not be used with SVR4 PIC code");
8993 bfd_set_gp_size (stdoutput
, 0);
8997 as_warn ("Unrecognized option \"%s\"", opt
);
8999 *input_line_pointer
= c
;
9000 demand_empty_rest_of_line ();
9007 char *name
= input_line_pointer
, ch
;
9009 while (!is_end_of_line
[(unsigned char) *input_line_pointer
])
9010 input_line_pointer
++;
9011 ch
= *input_line_pointer
;
9012 *input_line_pointer
= '\0';
9014 if (strcmp (name
, "reorder") == 0)
9018 prev_insn_unreordered
= 1;
9019 prev_prev_insn_unreordered
= 1;
9023 else if (strcmp (name
, "noreorder") == 0)
9025 mips_emit_delays (true);
9027 mips_any_noreorder
= 1;
9029 else if (strcmp (name
, "at") == 0)
9033 else if (strcmp (name
, "noat") == 0)
9037 else if (strcmp (name
, "macro") == 0)
9039 mips_warn_about_macros
= 0;
9041 else if (strcmp (name
, "nomacro") == 0)
9043 if (mips_noreorder
== 0)
9044 as_bad ("`noreorder' must be set before `nomacro'");
9045 mips_warn_about_macros
= 1;
9047 else if (strcmp (name
, "move") == 0 || strcmp (name
, "novolatile") == 0)
9051 else if (strcmp (name
, "nomove") == 0 || strcmp (name
, "volatile") == 0)
9055 else if (strcmp (name
, "bopt") == 0)
9059 else if (strcmp (name
, "nobopt") == 0)
9063 else if (strcmp (name
, "mips16") == 0
9064 || strcmp (name
, "MIPS-16") == 0)
9066 else if (strcmp (name
, "nomips16") == 0
9067 || strcmp (name
, "noMIPS-16") == 0)
9069 else if (strncmp (name
, "mips", 4) == 0)
9073 /* Permit the user to change the ISA on the fly. Needless to
9074 say, misuse can cause serious problems. */
9075 isa
= atoi (name
+ 4);
9077 mips_isa
= file_mips_isa
;
9078 else if (isa
< 1 || isa
> 4)
9079 as_bad ("unknown ISA level");
9083 else if (strcmp (name
, "autoextend") == 0)
9084 mips16_autoextend
= 1;
9085 else if (strcmp (name
, "noautoextend") == 0)
9086 mips16_autoextend
= 0;
9089 as_warn ("Tried to set unrecognized symbol: %s\n", name
);
9091 *input_line_pointer
= ch
;
9092 demand_empty_rest_of_line ();
9095 /* Handle the .abicalls pseudo-op. I believe this is equivalent to
9096 .option pic2. It means to generate SVR4 PIC calls. */
9102 mips_pic
= SVR4_PIC
;
9103 if (USE_GLOBAL_POINTER_OPT
)
9105 if (g_switch_seen
&& g_switch_value
!= 0)
9106 as_warn ("-G may not be used with SVR4 PIC code");
9109 bfd_set_gp_size (stdoutput
, 0);
9110 demand_empty_rest_of_line ();
9113 /* Handle the .cpload pseudo-op. This is used when generating SVR4
9114 PIC code. It sets the $gp register for the function based on the
9115 function address, which is in the register named in the argument.
9116 This uses a relocation against _gp_disp, which is handled specially
9117 by the linker. The result is:
9118 lui $gp,%hi(_gp_disp)
9119 addiu $gp,$gp,%lo(_gp_disp)
9120 addu $gp,$gp,.cpload argument
9121 The .cpload argument is normally $25 == $t9. */
9130 /* If we are not generating SVR4 PIC code, .cpload is ignored. */
9131 if (mips_pic
!= SVR4_PIC
)
9137 /* .cpload should be a in .set noreorder section. */
9138 if (mips_noreorder
== 0)
9139 as_warn (".cpload not in noreorder section");
9142 ex
.X_add_symbol
= symbol_find_or_make ("_gp_disp");
9143 ex
.X_op_symbol
= NULL
;
9144 ex
.X_add_number
= 0;
9146 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
9147 ex
.X_add_symbol
->bsym
->flags
|= BSF_OBJECT
;
9149 macro_build_lui ((char *) NULL
, &icnt
, &ex
, GP
);
9150 macro_build ((char *) NULL
, &icnt
, &ex
, "addiu", "t,r,j", GP
, GP
,
9151 (int) BFD_RELOC_LO16
);
9153 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "addu", "d,v,t",
9154 GP
, GP
, tc_get_register (0));
9156 demand_empty_rest_of_line ();
9159 /* Handle the .cprestore pseudo-op. This stores $gp into a given
9160 offset from $sp. The offset is remembered, and after making a PIC
9161 call $gp is restored from that location. */
9164 s_cprestore (ignore
)
9170 /* If we are not generating SVR4 PIC code, .cprestore is ignored. */
9171 if (mips_pic
!= SVR4_PIC
)
9177 mips_cprestore_offset
= get_absolute_expression ();
9179 ex
.X_op
= O_constant
;
9180 ex
.X_add_symbol
= NULL
;
9181 ex
.X_op_symbol
= NULL
;
9182 ex
.X_add_number
= mips_cprestore_offset
;
9184 macro_build ((char *) NULL
, &icnt
, &ex
,
9185 mips_isa
< 3 ? "sw" : "sd",
9186 "t,o(b)", GP
, (int) BFD_RELOC_LO16
, SP
);
9188 demand_empty_rest_of_line ();
9191 /* Handle the .gpword pseudo-op. This is used when generating PIC
9192 code. It generates a 32 bit GP relative reloc. */
9202 /* When not generating PIC code, this is treated as .word. */
9203 if (mips_pic
!= SVR4_PIC
)
9209 label
= insn_labels
!= NULL
? insn_labels
->label
: NULL
;
9210 mips_emit_delays (true);
9212 mips_align (2, 0, label
);
9213 mips_clear_insn_labels ();
9217 if (ex
.X_op
!= O_symbol
|| ex
.X_add_number
!= 0)
9219 as_bad ("Unsupported use of .gpword");
9220 ignore_rest_of_line ();
9224 md_number_to_chars (p
, (valueT
) 0, 4);
9225 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 4, &ex
, 0,
9226 BFD_RELOC_MIPS_GPREL32
);
9228 demand_empty_rest_of_line ();
9231 /* Handle the .cpadd pseudo-op. This is used when dealing with switch
9232 tables in SVR4 PIC code. */
9241 /* This is ignored when not generating SVR4 PIC code. */
9242 if (mips_pic
!= SVR4_PIC
)
9248 /* Add $gp to the register named as an argument. */
9249 reg
= tc_get_register (0);
9250 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
9251 mips_isa
< 3 ? "addu" : "daddu",
9252 "d,v,t", reg
, reg
, GP
);
9254 demand_empty_rest_of_line ();
9257 /* Handle the .insn pseudo-op. This marks instruction labels in
9258 mips16 mode. This permits the linker to handle them specially,
9259 such as generating jalx instructions when needed. We also make
9260 them odd for the duration of the assembly, in order to generate the
9261 right sort of code. We will make them even in the adjust_symtab
9262 routine, while leaving them marked. This is convenient for the
9263 debugger and the disassembler. The linker knows to make them odd
9272 struct insn_label_list
*l
;
9274 for (l
= insn_labels
; l
!= NULL
; l
= l
->next
)
9277 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
9278 S_SET_OTHER (l
->label
, STO_MIPS16
);
9280 ++l
->label
->sy_value
.X_add_number
;
9283 mips_clear_insn_labels ();
9286 demand_empty_rest_of_line ();
9289 /* Parse a register string into a number. Called from the ECOFF code
9290 to parse .frame. The argument is non-zero if this is the frame
9291 register, so that we can record it in mips_frame_reg. */
9294 tc_get_register (frame
)
9300 if (*input_line_pointer
++ != '$')
9302 as_warn ("expected `$'");
9305 else if (isdigit ((unsigned char) *input_line_pointer
))
9307 reg
= get_absolute_expression ();
9308 if (reg
< 0 || reg
>= 32)
9310 as_warn ("Bad register number");
9316 if (strncmp (input_line_pointer
, "fp", 2) == 0)
9318 else if (strncmp (input_line_pointer
, "sp", 2) == 0)
9320 else if (strncmp (input_line_pointer
, "gp", 2) == 0)
9322 else if (strncmp (input_line_pointer
, "at", 2) == 0)
9326 as_warn ("Unrecognized register name");
9329 input_line_pointer
+= 2;
9332 mips_frame_reg
= reg
!= 0 ? reg
: SP
;
9337 md_section_align (seg
, addr
)
9341 int align
= bfd_get_section_alignment (stdoutput
, seg
);
9344 /* We don't need to align ELF sections to the full alignment.
9345 However, Irix 5 may prefer that we align them at least to a 16
9346 byte boundary. We don't bother to align the sections if we are
9347 targeted for an embedded system. */
9348 if (strcmp (TARGET_OS
, "elf") == 0)
9354 return ((addr
+ (1 << align
) - 1) & (-1 << align
));
9357 /* Utility routine, called from above as well. If called while the
9358 input file is still being read, it's only an approximation. (For
9359 example, a symbol may later become defined which appeared to be
9360 undefined earlier.) */
9363 nopic_need_relax (sym
)
9369 if (USE_GLOBAL_POINTER_OPT
)
9371 const char *symname
;
9374 /* Find out whether this symbol can be referenced off the GP
9375 register. It can be if it is smaller than the -G size or if
9376 it is in the .sdata or .sbss section. Certain symbols can
9377 not be referenced off the GP, although it appears as though
9379 symname
= S_GET_NAME (sym
);
9380 if (symname
!= (const char *) NULL
9381 && (strcmp (symname
, "eprol") == 0
9382 || strcmp (symname
, "etext") == 0
9383 || strcmp (symname
, "_gp") == 0
9384 || strcmp (symname
, "edata") == 0
9385 || strcmp (symname
, "_fbss") == 0
9386 || strcmp (symname
, "_fdata") == 0
9387 || strcmp (symname
, "_ftext") == 0
9388 || strcmp (symname
, "end") == 0
9389 || strcmp (symname
, "_gp_disp") == 0))
9391 else if (! S_IS_DEFINED (sym
)
9393 #ifndef NO_ECOFF_DEBUGGING
9394 || (sym
->ecoff_extern_size
!= 0
9395 && sym
->ecoff_extern_size
<= g_switch_value
)
9397 || (S_GET_VALUE (sym
) != 0
9398 && S_GET_VALUE (sym
) <= g_switch_value
)))
9402 const char *segname
;
9404 segname
= segment_name (S_GET_SEGMENT (sym
));
9405 assert (strcmp (segname
, ".lit8") != 0
9406 && strcmp (segname
, ".lit4") != 0);
9407 change
= (strcmp (segname
, ".sdata") != 0
9408 && strcmp (segname
, ".sbss") != 0);
9413 /* We are not optimizing for the GP register. */
9417 /* Given a mips16 variant frag FRAGP, return non-zero if it needs an
9418 extended opcode. SEC is the section the frag is in. */
9421 mips16_extended_frag (fragp
, sec
, stretch
)
9427 register const struct mips16_immed_operand
*op
;
9429 int mintiny
, maxtiny
;
9432 if (RELAX_MIPS16_USER_SMALL (fragp
->fr_subtype
))
9434 if (RELAX_MIPS16_USER_EXT (fragp
->fr_subtype
))
9437 type
= RELAX_MIPS16_TYPE (fragp
->fr_subtype
);
9438 op
= mips16_immed_operands
;
9439 while (op
->type
!= type
)
9442 assert (op
< mips16_immed_operands
+ MIPS16_NUM_IMMED
);
9447 if (type
== '<' || type
== '>' || type
== '[' || type
== ']')
9450 maxtiny
= 1 << op
->nbits
;
9455 maxtiny
= (1 << op
->nbits
) - 1;
9460 mintiny
= - (1 << (op
->nbits
- 1));
9461 maxtiny
= (1 << (op
->nbits
- 1)) - 1;
9464 /* We can't call S_GET_VALUE here, because we don't want to lock in
9465 a particular frag address. */
9466 if (fragp
->fr_symbol
->sy_value
.X_op
== O_constant
)
9468 val
= (fragp
->fr_symbol
->sy_value
.X_add_number
9469 + fragp
->fr_symbol
->sy_frag
->fr_address
);
9470 symsec
= S_GET_SEGMENT (fragp
->fr_symbol
);
9472 else if (fragp
->fr_symbol
->sy_value
.X_op
== O_symbol
9473 && (fragp
->fr_symbol
->sy_value
.X_add_symbol
->sy_value
.X_op
9476 val
= (fragp
->fr_symbol
->sy_value
.X_add_symbol
->sy_value
.X_add_number
9477 + fragp
->fr_symbol
->sy_value
.X_add_symbol
->sy_frag
->fr_address
9478 + fragp
->fr_symbol
->sy_value
.X_add_number
9479 + fragp
->fr_symbol
->sy_frag
->fr_address
);
9480 symsec
= S_GET_SEGMENT (fragp
->fr_symbol
->sy_value
.X_add_symbol
);
9489 /* We won't have the section when we are called from
9490 mips_relax_frag. However, we will always have been called
9491 from md_estimate_size_before_relax first. If this is a
9492 branch to a different section, we mark it as such. If SEC is
9493 NULL, and the frag is not marked, then it must be a branch to
9494 the same section. */
9497 if (RELAX_MIPS16_LONG_BRANCH (fragp
->fr_subtype
))
9505 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
9507 /* FIXME: We should support this, and let the linker
9508 catch branches and loads that are out of range. */
9509 as_bad_where (fragp
->fr_file
, fragp
->fr_line
,
9510 "unsupported PC relative reference to different section");
9516 /* In this case, we know for sure that the symbol fragment is in
9517 the same section. If the fr_address of the symbol fragment
9518 is greater then the address of this fragment we want to add
9519 in STRETCH in order to get a better estimate of the address.
9520 This particularly matters because of the shift bits. */
9522 && fragp
->fr_symbol
->sy_frag
->fr_address
>= fragp
->fr_address
)
9526 /* Adjust stretch for any alignment frag. */
9527 for (f
= fragp
; f
!= fragp
->fr_symbol
->sy_frag
; f
= f
->fr_next
)
9530 if (f
->fr_type
== rs_align
|| f
->fr_type
== rs_align_code
)
9533 stretch
= - ((- stretch
)
9534 & ~ ((1 << (int) f
->fr_offset
) - 1));
9536 stretch
&= ~ ((1 << (int) f
->fr_offset
) - 1);
9544 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
9546 /* The base address rules are complicated. The base address of
9547 a branch is the following instruction. The base address of a
9548 PC relative load or add is the instruction itself, but if it
9549 is extended add 2, and if it is in a delay slot (in which
9550 case it can not be extended) use the address of the
9551 instruction whose delay slot it is in. */
9552 if (type
== 'p' || type
== 'q')
9555 /* Ignore the low bit in the target, since it will be set
9556 for a text label. */
9560 else if (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
))
9562 else if (RELAX_MIPS16_DSLOT (fragp
->fr_subtype
))
9565 /* If we are currently assuming that this frag should be
9566 extended, then the current address is two bytes higher. */
9567 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
9570 val
-= addr
& ~ ((1 << op
->shift
) - 1);
9572 /* Branch offsets have an implicit 0 in the lowest bit. */
9573 if (type
== 'p' || type
== 'q')
9576 /* If any of the shifted bits are set, we must use an extended
9577 opcode. If the address depends on the size of this
9578 instruction, this can lead to a loop, so we arrange to always
9579 use an extended opcode. We only check this when we are in
9580 the main relaxation loop, when SEC is NULL. */
9581 if ((val
& ((1 << op
->shift
) - 1)) != 0 && sec
== NULL
)
9584 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
9588 /* If we are about to mark a frag as extended because the value
9589 is precisely maxtiny + 1, then there is a chance of an
9590 infinite loop as in the following code:
9595 In this case when the la is extended, foo is 0x3fc bytes
9596 away, so the la can be shrunk, but then foo is 0x400 away, so
9597 the la must be extended. To avoid this loop, we mark the
9598 frag as extended if it was small, and is about to become
9599 extended with a value of maxtiny + 1. */
9600 if (val
== ((maxtiny
+ 1) << op
->shift
)
9601 && ! RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
)
9605 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
9609 else if (symsec
!= absolute_section
&& sec
!= NULL
)
9610 as_bad_where (fragp
->fr_file
, fragp
->fr_line
, "unsupported relocation");
9612 if ((val
& ((1 << op
->shift
) - 1)) != 0
9613 || val
< (mintiny
<< op
->shift
)
9614 || val
> (maxtiny
<< op
->shift
))
9620 /* Estimate the size of a frag before relaxing. Unless this is the
9621 mips16, we are not really relaxing here, and the final size is
9622 encoded in the subtype information. For the mips16, we have to
9623 decide whether we are using an extended opcode or not. */
9627 md_estimate_size_before_relax (fragp
, segtype
)
9633 if (RELAX_MIPS16_P (fragp
->fr_subtype
))
9635 if (mips16_extended_frag (fragp
, segtype
, 0))
9637 fragp
->fr_subtype
= RELAX_MIPS16_MARK_EXTENDED (fragp
->fr_subtype
);
9642 fragp
->fr_subtype
= RELAX_MIPS16_CLEAR_EXTENDED (fragp
->fr_subtype
);
9647 if (mips_pic
== NO_PIC
)
9649 change
= nopic_need_relax (fragp
->fr_symbol
);
9651 else if (mips_pic
== SVR4_PIC
)
9653 asection
*symsec
= fragp
->fr_symbol
->bsym
->section
;
9655 /* This must duplicate the test in adjust_reloc_syms. */
9656 change
= (symsec
!= &bfd_und_section
9657 && symsec
!= &bfd_abs_section
9658 && ! bfd_is_com_section (symsec
));
9665 /* Record the offset to the first reloc in the fr_opcode field.
9666 This lets md_convert_frag and tc_gen_reloc know that the code
9667 must be expanded. */
9668 fragp
->fr_opcode
= (fragp
->fr_literal
9670 - RELAX_OLD (fragp
->fr_subtype
)
9671 + RELAX_RELOC1 (fragp
->fr_subtype
));
9672 /* FIXME: This really needs as_warn_where. */
9673 if (RELAX_WARN (fragp
->fr_subtype
))
9674 as_warn ("AT used after \".set noat\" or macro used after \".set nomacro\"");
9680 return RELAX_NEW (fragp
->fr_subtype
) - RELAX_OLD (fragp
->fr_subtype
);
9683 /* This is called to see whether a reloc against a defined symbol
9684 should be converted into a reloc against a section. Don't adjust
9685 MIPS16 jump relocations, so we don't have to worry about the format
9686 of the offset in the .o file. Don't adjust relocations against
9687 mips16 symbols, so that the linker can find them if it needs to set
9691 mips_fix_adjustable (fixp
)
9694 if (fixp
->fx_r_type
== BFD_RELOC_MIPS16_JMP
)
9696 if (fixp
->fx_addsy
== NULL
)
9699 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
9700 && S_GET_OTHER (fixp
->fx_addsy
) == STO_MIPS16
)
9706 /* Translate internal representation of relocation info to BFD target
9710 tc_gen_reloc (section
, fixp
)
9714 static arelent
*retval
[4];
9716 bfd_reloc_code_real_type code
;
9718 reloc
= retval
[0] = (arelent
*) xmalloc (sizeof (arelent
));
9721 reloc
->sym_ptr_ptr
= &fixp
->fx_addsy
->bsym
;
9722 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
9724 if (mips_pic
== EMBEDDED_PIC
9725 && SWITCH_TABLE (fixp
))
9727 /* For a switch table entry we use a special reloc. The addend
9728 is actually the difference between the reloc address and the
9730 reloc
->addend
= reloc
->address
- S_GET_VALUE (fixp
->fx_subsy
);
9731 if (OUTPUT_FLAVOR
!= bfd_target_ecoff_flavour
)
9732 as_fatal ("Double check fx_r_type in tc-mips.c:tc_gen_reloc");
9733 fixp
->fx_r_type
= BFD_RELOC_GPREL32
;
9735 else if (fixp
->fx_r_type
== BFD_RELOC_PCREL_LO16
)
9737 /* We use a special addend for an internal RELLO reloc. */
9738 if (fixp
->fx_addsy
->bsym
->flags
& BSF_SECTION_SYM
)
9739 reloc
->addend
= reloc
->address
- S_GET_VALUE (fixp
->fx_subsy
);
9741 reloc
->addend
= fixp
->fx_addnumber
+ reloc
->address
;
9743 else if (fixp
->fx_r_type
== BFD_RELOC_PCREL_HI16_S
)
9745 assert (fixp
->fx_next
!= NULL
9746 && fixp
->fx_next
->fx_r_type
== BFD_RELOC_PCREL_LO16
);
9747 /* We use a special addend for an internal RELHI reloc. The
9748 reloc is relative to the RELLO; adjust the addend
9750 if (fixp
->fx_addsy
->bsym
->flags
& BSF_SECTION_SYM
)
9751 reloc
->addend
= (fixp
->fx_next
->fx_frag
->fr_address
9752 + fixp
->fx_next
->fx_where
9753 - S_GET_VALUE (fixp
->fx_subsy
));
9755 reloc
->addend
= (fixp
->fx_addnumber
9756 + fixp
->fx_next
->fx_frag
->fr_address
9757 + fixp
->fx_next
->fx_where
);
9759 else if (fixp
->fx_pcrel
== 0)
9760 reloc
->addend
= fixp
->fx_addnumber
;
9763 if (OUTPUT_FLAVOR
!= bfd_target_aout_flavour
)
9764 /* A gruesome hack which is a result of the gruesome gas reloc
9766 reloc
->addend
= reloc
->address
;
9768 reloc
->addend
= -reloc
->address
;
9771 /* If this is a variant frag, we may need to adjust the existing
9772 reloc and generate a new one. */
9773 if (fixp
->fx_frag
->fr_opcode
!= NULL
9774 && (fixp
->fx_r_type
== BFD_RELOC_MIPS_GPREL
9775 || fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT16
9776 || fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL16
9777 || fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT_HI16
9778 || fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT_LO16
9779 || fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL_HI16
9780 || fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL_LO16
))
9784 assert (! RELAX_MIPS16_P (fixp
->fx_frag
->fr_subtype
));
9786 /* If this is not the last reloc in this frag, then we have two
9787 GPREL relocs, or a GOT_HI16/GOT_LO16 pair, or a
9788 CALL_HI16/CALL_LO16, both of which are being replaced. Let
9789 the second one handle all of them. */
9790 if (fixp
->fx_next
!= NULL
9791 && fixp
->fx_frag
== fixp
->fx_next
->fx_frag
)
9793 assert ((fixp
->fx_r_type
== BFD_RELOC_MIPS_GPREL
9794 && fixp
->fx_next
->fx_r_type
== BFD_RELOC_MIPS_GPREL
)
9795 || (fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT_HI16
9796 && (fixp
->fx_next
->fx_r_type
9797 == BFD_RELOC_MIPS_GOT_LO16
))
9798 || (fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL_HI16
9799 && (fixp
->fx_next
->fx_r_type
9800 == BFD_RELOC_MIPS_CALL_LO16
)));
9805 fixp
->fx_where
= fixp
->fx_frag
->fr_opcode
- fixp
->fx_frag
->fr_literal
;
9806 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
9807 reloc2
= retval
[1] = (arelent
*) xmalloc (sizeof (arelent
));
9809 reloc2
->sym_ptr_ptr
= &fixp
->fx_addsy
->bsym
;
9810 reloc2
->address
= (reloc
->address
9811 + (RELAX_RELOC2 (fixp
->fx_frag
->fr_subtype
)
9812 - RELAX_RELOC1 (fixp
->fx_frag
->fr_subtype
)));
9813 reloc2
->addend
= fixp
->fx_addnumber
;
9814 reloc2
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_LO16
);
9815 assert (reloc2
->howto
!= NULL
);
9817 if (RELAX_RELOC3 (fixp
->fx_frag
->fr_subtype
))
9821 reloc3
= retval
[2] = (arelent
*) xmalloc (sizeof (arelent
));
9824 reloc3
->address
+= 4;
9827 if (mips_pic
== NO_PIC
)
9829 assert (fixp
->fx_r_type
== BFD_RELOC_MIPS_GPREL
);
9830 fixp
->fx_r_type
= BFD_RELOC_HI16_S
;
9832 else if (mips_pic
== SVR4_PIC
)
9834 switch (fixp
->fx_r_type
)
9838 case BFD_RELOC_MIPS_GOT16
:
9840 case BFD_RELOC_MIPS_CALL16
:
9841 case BFD_RELOC_MIPS_GOT_LO16
:
9842 case BFD_RELOC_MIPS_CALL_LO16
:
9843 fixp
->fx_r_type
= BFD_RELOC_MIPS_GOT16
;
9851 /* Since DIFF_EXPR_OK is defined in tc-mips.h, it is possible that
9852 fixup_segment converted a non-PC relative reloc into a PC
9853 relative reloc. In such a case, we need to convert the reloc
9855 code
= fixp
->fx_r_type
;
9861 code
= BFD_RELOC_8_PCREL
;
9864 code
= BFD_RELOC_16_PCREL
;
9867 code
= BFD_RELOC_32_PCREL
;
9870 code
= BFD_RELOC_64_PCREL
;
9872 case BFD_RELOC_8_PCREL
:
9873 case BFD_RELOC_16_PCREL
:
9874 case BFD_RELOC_32_PCREL
:
9875 case BFD_RELOC_64_PCREL
:
9876 case BFD_RELOC_16_PCREL_S2
:
9877 case BFD_RELOC_PCREL_HI16_S
:
9878 case BFD_RELOC_PCREL_LO16
:
9881 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
9882 "Cannot make %s relocation PC relative",
9883 bfd_get_reloc_code_name (code
));
9887 /* To support a PC relative reloc when generating embedded PIC code
9888 for ECOFF, we use a Cygnus extension. We check for that here to
9889 make sure that we don't let such a reloc escape normally. */
9890 if (OUTPUT_FLAVOR
== bfd_target_ecoff_flavour
9891 && code
== BFD_RELOC_16_PCREL_S2
9892 && mips_pic
!= EMBEDDED_PIC
)
9893 reloc
->howto
= NULL
;
9895 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
9897 if (reloc
->howto
== NULL
)
9899 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
9900 "Can not represent %s relocation in this object file format",
9901 bfd_get_reloc_code_name (code
));
9908 /* Relax a machine dependent frag. This returns the amount by which
9909 the current size of the frag should change. */
9912 mips_relax_frag (fragp
, stretch
)
9916 if (! RELAX_MIPS16_P (fragp
->fr_subtype
))
9919 if (mips16_extended_frag (fragp
, (asection
*) NULL
, stretch
))
9921 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
9923 fragp
->fr_subtype
= RELAX_MIPS16_MARK_EXTENDED (fragp
->fr_subtype
);
9928 if (! RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
9930 fragp
->fr_subtype
= RELAX_MIPS16_CLEAR_EXTENDED (fragp
->fr_subtype
);
9937 /* Convert a machine dependent frag. */
9940 md_convert_frag (abfd
, asec
, fragp
)
9948 if (RELAX_MIPS16_P (fragp
->fr_subtype
))
9951 register const struct mips16_immed_operand
*op
;
9957 unsigned short extend
;
9959 type
= RELAX_MIPS16_TYPE (fragp
->fr_subtype
);
9960 op
= mips16_immed_operands
;
9961 while (op
->type
!= type
)
9964 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
9975 resolve_symbol_value (fragp
->fr_symbol
);
9976 val
= S_GET_VALUE (fragp
->fr_symbol
);
9981 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
9983 /* The rules for the base address of a PC relative reloc are
9984 complicated; see mips16_extended_frag. */
9985 if (type
== 'p' || type
== 'q')
9988 /* Ignore the low bit in the target, since it will be
9989 set for a text label. */
9993 else if (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
))
9995 else if (RELAX_MIPS16_DSLOT (fragp
->fr_subtype
))
10000 addr
&= ~ (addressT
) ((1 << op
->shift
) - 1);
10003 /* Make sure the section winds up with the alignment we have
10006 record_alignment (asec
, op
->shift
);
10010 && (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
)
10011 || RELAX_MIPS16_DSLOT (fragp
->fr_subtype
)))
10012 as_warn_where (fragp
->fr_file
, fragp
->fr_line
,
10013 "extended instruction in delay slot");
10015 buf
= (bfd_byte
*) (fragp
->fr_literal
+ fragp
->fr_fix
);
10017 if (target_big_endian
)
10018 insn
= bfd_getb16 (buf
);
10020 insn
= bfd_getl16 (buf
);
10022 mips16_immed (fragp
->fr_file
, fragp
->fr_line
, type
, val
,
10023 RELAX_MIPS16_USER_EXT (fragp
->fr_subtype
),
10024 small
, ext
, &insn
, &use_extend
, &extend
);
10028 md_number_to_chars (buf
, 0xf000 | extend
, 2);
10029 fragp
->fr_fix
+= 2;
10033 md_number_to_chars (buf
, insn
, 2);
10034 fragp
->fr_fix
+= 2;
10039 if (fragp
->fr_opcode
== NULL
)
10042 old
= RELAX_OLD (fragp
->fr_subtype
);
10043 new = RELAX_NEW (fragp
->fr_subtype
);
10044 fixptr
= fragp
->fr_literal
+ fragp
->fr_fix
;
10047 memcpy (fixptr
- old
, fixptr
, new);
10049 fragp
->fr_fix
+= new - old
;
10055 /* This function is called after the relocs have been generated.
10056 We've been storing mips16 text labels as odd. Here we convert them
10057 back to even for the convenience of the debugger. */
10060 mips_frob_file_after_relocs ()
10063 unsigned int count
, i
;
10065 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
10068 syms
= bfd_get_outsymbols (stdoutput
);
10069 count
= bfd_get_symcount (stdoutput
);
10070 for (i
= 0; i
< count
; i
++, syms
++)
10072 if (elf_symbol (*syms
)->internal_elf_sym
.st_other
== STO_MIPS16
10073 && ((*syms
)->value
& 1) != 0)
10075 (*syms
)->value
&= ~1;
10076 /* If the symbol has an odd size, it was probably computed
10077 incorrectly, so adjust that as well. */
10078 if ((elf_symbol (*syms
)->internal_elf_sym
.st_size
& 1) != 0)
10079 ++elf_symbol (*syms
)->internal_elf_sym
.st_size
;
10086 /* This function is called whenever a label is defined. It is used
10087 when handling branch delays; if a branch has a label, we assume we
10088 can not move it. */
10091 mips_define_label (sym
)
10094 struct insn_label_list
*l
;
10096 if (free_insn_labels
== NULL
)
10097 l
= (struct insn_label_list
*) xmalloc (sizeof *l
);
10100 l
= free_insn_labels
;
10101 free_insn_labels
= l
->next
;
10105 l
->next
= insn_labels
;
10109 /* Decide whether a label is local. This is called by LOCAL_LABEL.
10110 In order to work with gcc when using mips-tfile, we must keep all
10111 local labels. However, in other cases, we want to discard them,
10112 since they are useless. */
10115 mips_local_label (name
)
10118 #ifndef NO_ECOFF_DEBUGGING
10119 if (ECOFF_DEBUGGING
10121 && ! ecoff_debugging_seen
)
10123 /* We were called with -g, but we didn't see any debugging
10124 information. That may mean that gcc is smuggling debugging
10125 information through to mips-tfile, in which case we must
10126 generate all local labels. */
10131 /* Here it's OK to discard local labels. */
10133 return name
[0] == '$';
10136 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10138 /* Some special processing for a MIPS ELF file. */
10141 mips_elf_final_processing ()
10143 /* Write out the register information. */
10148 s
.ri_gprmask
= mips_gprmask
;
10149 s
.ri_cprmask
[0] = mips_cprmask
[0];
10150 s
.ri_cprmask
[1] = mips_cprmask
[1];
10151 s
.ri_cprmask
[2] = mips_cprmask
[2];
10152 s
.ri_cprmask
[3] = mips_cprmask
[3];
10153 /* The gp_value field is set by the MIPS ELF backend. */
10155 bfd_mips_elf32_swap_reginfo_out (stdoutput
, &s
,
10156 ((Elf32_External_RegInfo
*)
10157 mips_regmask_frag
));
10161 Elf64_Internal_RegInfo s
;
10163 s
.ri_gprmask
= mips_gprmask
;
10165 s
.ri_cprmask
[0] = mips_cprmask
[0];
10166 s
.ri_cprmask
[1] = mips_cprmask
[1];
10167 s
.ri_cprmask
[2] = mips_cprmask
[2];
10168 s
.ri_cprmask
[3] = mips_cprmask
[3];
10169 /* The gp_value field is set by the MIPS ELF backend. */
10171 bfd_mips_elf64_swap_reginfo_out (stdoutput
, &s
,
10172 ((Elf64_External_RegInfo
*)
10173 mips_regmask_frag
));
10176 /* Set the MIPS ELF flag bits. FIXME: There should probably be some
10177 sort of BFD interface for this. */
10178 if (mips_any_noreorder
)
10179 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_NOREORDER
;
10180 if (mips_pic
!= NO_PIC
)
10181 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_PIC
;
10184 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */
10186 /* These functions should really be defined by the object file format,
10187 since they are related to debugging information. However, this
10188 code has to work for the a.out format, which does not define them,
10189 so we provide simple versions here. These don't actually generate
10190 any debugging information, but they do simple checking and someday
10191 somebody may make them useful. */
10195 struct loc
*loc_next
;
10196 unsigned long loc_fileno
;
10197 unsigned long loc_lineno
;
10198 unsigned long loc_offset
;
10199 unsigned short loc_delta
;
10200 unsigned short loc_count
;
10207 typedef struct proc
10209 struct proc
*proc_next
;
10210 struct symbol
*proc_isym
;
10211 struct symbol
*proc_end
;
10212 unsigned long proc_reg_mask
;
10213 unsigned long proc_reg_offset
;
10214 unsigned long proc_fpreg_mask
;
10215 unsigned long proc_fpreg_offset
;
10216 unsigned long proc_frameoffset
;
10217 unsigned long proc_framereg
;
10218 unsigned long proc_pcreg
;
10220 struct file
*proc_file
;
10225 typedef struct file
10227 struct file
*file_next
;
10228 unsigned long file_fileno
;
10229 struct symbol
*file_symbol
;
10230 struct symbol
*file_end
;
10231 struct proc
*file_proc
;
10236 static struct obstack proc_frags
;
10237 static procS
*proc_lastP
;
10238 static procS
*proc_rootP
;
10239 static int numprocs
;
10244 obstack_begin (&proc_frags
, 0x2000);
10250 /* check for premature end, nesting errors, etc */
10251 if (proc_lastP
&& proc_lastP
->proc_end
== NULL
)
10252 as_warn ("missing `.end' at end of assembly");
10261 if (*input_line_pointer
== '-')
10263 ++input_line_pointer
;
10266 if (!isdigit (*input_line_pointer
))
10267 as_bad ("Expected simple number.");
10268 if (input_line_pointer
[0] == '0')
10270 if (input_line_pointer
[1] == 'x')
10272 input_line_pointer
+= 2;
10273 while (isxdigit (*input_line_pointer
))
10276 val
|= hex_value (*input_line_pointer
++);
10278 return negative
? -val
: val
;
10282 ++input_line_pointer
;
10283 while (isdigit (*input_line_pointer
))
10286 val
|= *input_line_pointer
++ - '0';
10288 return negative
? -val
: val
;
10291 if (!isdigit (*input_line_pointer
))
10293 printf (" *input_line_pointer == '%c' 0x%02x\n",
10294 *input_line_pointer
, *input_line_pointer
);
10295 as_warn ("Invalid number");
10298 while (isdigit (*input_line_pointer
))
10301 val
+= *input_line_pointer
++ - '0';
10303 return negative
? -val
: val
;
10306 /* The .file directive; just like the usual .file directive, but there
10307 is an initial number which is the ECOFF file index. */
10315 line
= get_number ();
10320 /* The .end directive. */
10328 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
10331 demand_empty_rest_of_line ();
10335 if (now_seg
!= text_section
)
10336 as_warn (".end not in text section");
10339 as_warn (".end and no .ent seen yet.");
10345 assert (S_GET_NAME (p
));
10346 if (strcmp (S_GET_NAME (p
), S_GET_NAME (proc_lastP
->proc_isym
)))
10347 as_warn (".end symbol does not match .ent symbol.");
10350 proc_lastP
->proc_end
= (symbolS
*) 1;
10353 /* The .aent and .ent directives. */
10363 symbolP
= get_symbol ();
10364 if (*input_line_pointer
== ',')
10365 input_line_pointer
++;
10366 SKIP_WHITESPACE ();
10367 if (isdigit (*input_line_pointer
) || *input_line_pointer
== '-')
10368 number
= get_number ();
10369 if (now_seg
!= text_section
)
10370 as_warn (".ent or .aent not in text section.");
10372 if (!aent
&& proc_lastP
&& proc_lastP
->proc_end
== NULL
)
10373 as_warn ("missing `.end'");
10377 procP
= (procS
*) obstack_alloc (&proc_frags
, sizeof (*procP
));
10378 procP
->proc_isym
= symbolP
;
10379 procP
->proc_reg_mask
= 0;
10380 procP
->proc_reg_offset
= 0;
10381 procP
->proc_fpreg_mask
= 0;
10382 procP
->proc_fpreg_offset
= 0;
10383 procP
->proc_frameoffset
= 0;
10384 procP
->proc_framereg
= 0;
10385 procP
->proc_pcreg
= 0;
10386 procP
->proc_end
= NULL
;
10387 procP
->proc_next
= NULL
;
10389 proc_lastP
->proc_next
= procP
;
10391 proc_rootP
= procP
;
10392 proc_lastP
= procP
;
10395 demand_empty_rest_of_line ();
10398 /* The .frame directive. */
10411 frame_reg
= tc_get_register (1);
10412 if (*input_line_pointer
== ',')
10413 input_line_pointer
++;
10414 frame_off
= get_absolute_expression ();
10415 if (*input_line_pointer
== ',')
10416 input_line_pointer
++;
10417 pcreg
= tc_get_register (0);
10419 /* bob third eye */
10420 assert (proc_rootP
);
10421 proc_rootP
->proc_framereg
= frame_reg
;
10422 proc_rootP
->proc_frameoffset
= frame_off
;
10423 proc_rootP
->proc_pcreg
= pcreg
;
10424 /* bob macho .frame */
10426 /* We don't have to write out a frame stab for unoptimized code. */
10427 if (!(frame_reg
== FP
&& frame_off
== 0))
10430 as_warn ("No .ent for .frame to use.");
10431 (void) sprintf (str
, "R%d;%d", frame_reg
, frame_off
);
10432 symP
= symbol_new (str
, N_VFP
, 0, frag_now
);
10433 S_SET_TYPE (symP
, N_RMASK
);
10434 S_SET_OTHER (symP
, 0);
10435 S_SET_DESC (symP
, 0);
10436 symP
->sy_forward
= proc_lastP
->proc_isym
;
10437 /* bob perhaps I should have used pseudo set */
10439 demand_empty_rest_of_line ();
10443 /* The .fmask and .mask directives. */
10450 char str
[100], *strP
;
10456 mask
= get_number ();
10457 if (*input_line_pointer
== ',')
10458 input_line_pointer
++;
10459 off
= get_absolute_expression ();
10461 /* bob only for coff */
10462 assert (proc_rootP
);
10463 if (reg_type
== 'F')
10465 proc_rootP
->proc_fpreg_mask
= mask
;
10466 proc_rootP
->proc_fpreg_offset
= off
;
10470 proc_rootP
->proc_reg_mask
= mask
;
10471 proc_rootP
->proc_reg_offset
= off
;
10474 /* bob macho .mask + .fmask */
10476 /* We don't have to write out a mask stab if no saved regs. */
10480 as_warn ("No .ent for .mask to use.");
10482 for (i
= 0; i
< 32; i
++)
10486 sprintf (strP
, "%c%d,", reg_type
, i
);
10487 strP
+= strlen (strP
);
10491 sprintf (strP
, ";%d,", off
);
10492 symP
= symbol_new (str
, N_RMASK
, 0, frag_now
);
10493 S_SET_TYPE (symP
, N_RMASK
);
10494 S_SET_OTHER (symP
, 0);
10495 S_SET_DESC (symP
, 0);
10496 symP
->sy_forward
= proc_lastP
->proc_isym
;
10497 /* bob perhaps I should have used pseudo set */
10502 /* The .loc directive. */
10513 assert (now_seg
== text_section
);
10515 lineno
= get_number ();
10516 addroff
= frag_now_fix ();
10518 symbolP
= symbol_new ("", N_SLINE
, addroff
, frag_now
);
10519 S_SET_TYPE (symbolP
, N_SLINE
);
10520 S_SET_OTHER (symbolP
, 0);
10521 S_SET_DESC (symbolP
, lineno
);
10522 symbolP
->sy_segment
= now_seg
;