1 /* tc-mips.c -- assemble code for a MIPS chip.
2 Copyright (C) 1993 Free Software Foundation, Inc.
3 Contributed by the OSF and Ralph Campbell.
4 Written by Keith Knowles and Ralph Campbell, working independently.
5 Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus
8 This file is part of GAS.
10 GAS is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 2, or (at your option)
15 GAS is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with GAS; see the file COPYING. If not, write to
22 the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */
40 #endif /* NO_VARARGS */
41 #endif /* NO_STDARG */
43 #include "opcode/mips.h"
48 static char *mips_regmask_frag
;
55 /* Decide whether to do GP reference optimizations based on the object
65 /* These variables are filled in with the masks of registers used.
66 The object format code reads them and puts them in the appropriate
68 unsigned long mips_gprmask
;
69 unsigned long mips_cprmask
[4];
71 /* MIPS ISA (Instruction Set Architecture) level. */
72 static int mips_isa
= -1;
74 static int mips_warn_about_macros
;
75 static int mips_noreorder
;
76 static int mips_nomove
;
78 static int mips_nobopt
;
81 /* The size of the small data section. */
82 static int g_switch_value
= 8;
88 /* handle of the OPCODE hash table */
89 static struct hash_control
*op_hash
= NULL
;
91 /* This array holds the chars that always start a comment. If the
92 pre-processor is disabled, these aren't very useful */
93 const char comment_chars
[] = "#";
95 /* This array holds the chars that only start a comment at the beginning of
96 a line. If the line seems to have the form '# 123 filename'
97 .line and .file directives will appear in the pre-processed output */
98 /* Note that input_file.c hand checks for '#' at the beginning of the
99 first line of the input file. This is because the compiler outputs
100 #NO_APP at the beginning of its output. */
101 /* Also note that C style comments are always supported. */
102 const char line_comment_chars
[] = "#";
104 /* This array holds machine specific line separator characters. */
105 const char line_separator_chars
[] = "";
107 /* Chars that can be used to separate mant from exp in floating point nums */
108 const char EXP_CHARS
[] = "eE";
110 /* Chars that mean this number is a floating point constant */
113 const char FLT_CHARS
[] = "rRsSfFdDxXpP";
115 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
116 changed in read.c . Ideally it shouldn't have to know about it at all,
117 but nothing is ideal around here.
120 static char *insn_error
;
122 static int byte_order
= BYTE_ORDER
;
124 static int auto_align
= 1;
126 /* Symbol labelling the current insn. */
127 static symbolS
*insn_label
;
129 /* To output NOP instructions correctly, we need to keep information
130 about the previous two instructions. */
132 /* Whether we are optimizing. The default value of 2 means to remove
133 unneeded NOPs and swap branch instructions when possible. A value
134 of 1 means to not swap branches. A value of 0 means to always
136 static int mips_optimize
= 2;
138 /* The previous instruction. */
139 static struct mips_cl_insn prev_insn
;
141 /* The instruction before prev_insn. */
142 static struct mips_cl_insn prev_prev_insn
;
144 /* If we don't want information for prev_insn or prev_prev_insn, we
145 point the insn_mo field at this dummy integer. */
146 static const struct mips_opcode dummy_opcode
= { 0 };
148 /* Non-zero if prev_insn is valid. */
149 static int prev_insn_valid
;
151 /* The frag for the previous instruction. */
152 static struct frag
*prev_insn_frag
;
154 /* The offset into prev_insn_frag for the previous instruction. */
155 static long prev_insn_where
;
157 /* The reloc for the previous instruction, if any. */
158 static fixS
*prev_insn_fixp
;
160 /* Non-zero if the previous instruction was in a delay slot. */
161 static int prev_insn_is_delay_slot
;
163 /* Non-zero if the previous instruction was in a .set noreorder. */
164 static int prev_insn_unreordered
;
166 /* Non-zero if the previous previous instruction was in a .set
168 static int prev_prev_insn_unreordered
;
170 /* Prototypes for static functions. */
173 #define internalError() \
174 as_fatal ("internal Error, line %d, %s", __LINE__, __FILE__)
176 #define internalError() as_fatal ("MIPS internal Error");
179 static int insn_uses_reg
PARAMS ((struct mips_cl_insn
*ip
,
180 unsigned int reg
, int fpr
));
181 static void append_insn
PARAMS ((struct mips_cl_insn
* ip
,
183 bfd_reloc_code_real_type r
));
184 static void mips_no_prev_insn
PARAMS ((void));
185 static void mips_emit_delays
PARAMS ((void));
186 static int gp_reference
PARAMS ((expressionS
* ep
));
187 static void macro_build
PARAMS ((int *counter
, expressionS
* ep
,
188 const char *name
, const char *fmt
,
190 static void macro_build_lui
PARAMS ((int *counter
, expressionS
* ep
,
192 static void set_at
PARAMS ((int *counter
, int reg
, int unsignedp
));
193 static void check_absolute_expr
PARAMS ((struct mips_cl_insn
* ip
,
195 static void load_register
PARAMS ((int *counter
,
196 int reg
, expressionS
* ep
));
197 static void macro
PARAMS ((struct mips_cl_insn
* ip
));
198 static void mips_ip
PARAMS ((char *str
, struct mips_cl_insn
* ip
));
199 static int my_getSmallExpression
PARAMS ((expressionS
* ep
, char *str
));
200 static void my_getExpression
PARAMS ((expressionS
* ep
, char *str
));
201 static symbolS
*get_symbol
PARAMS ((void));
202 static void mips_align
PARAMS ((int to
, int fill
));
203 static void s_align
PARAMS ((int));
204 static void s_stringer
PARAMS ((int));
205 static void s_change_sec
PARAMS ((int));
206 static void s_cons
PARAMS ((int));
207 static void s_err
PARAMS ((int));
208 static void s_extern
PARAMS ((int));
209 static void s_float_cons
PARAMS ((int));
210 static void s_option
PARAMS ((int));
211 static void s_mipsset
PARAMS ((int));
212 static void s_mips_space
PARAMS ((int));
214 static void md_obj_begin
PARAMS ((void));
215 static void md_obj_end
PARAMS ((void));
216 static long get_number
PARAMS ((void));
217 static void s_ent
PARAMS ((int));
218 static void s_mipsend
PARAMS ((int));
219 static void s_file
PARAMS ((int));
221 static void s_frame
PARAMS ((int));
222 static void s_loc
PARAMS ((int));
223 static void s_mask
PARAMS ((char));
229 The following pseudo-ops from the Kane and Heinrich MIPS book
230 should be defined here, but are currently unsupported: .alias,
231 .galive, .gjaldef, .gjrlive, .livereg, .noalias.
233 The following pseudo-ops from the Kane and Heinrich MIPS book are
234 specific to the type of debugging information being generated, and
235 should be defined by the object format: .aent, .begin, .bend,
236 .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp,
239 The following pseudo-ops from the Kane and Heinrich MIPS book are
240 not MIPS CPU specific, but are also not specific to the object file
241 format. This file is probably the best place to define them, but
242 they are not currently supported: .asm0, .endr, .lab, .repeat,
243 .struct, .weakext. */
245 const pseudo_typeS md_pseudo_table
[] =
247 /* MIPS specific pseudo-ops. */
248 {"option", s_option
, 0},
249 {"set", s_mipsset
, 0},
250 {"rdata", s_change_sec
, 'r'},
251 {"sdata", s_change_sec
, 's'},
252 {"livereg", s_ignore
, 0},
254 /* Relatively generic pseudo-ops that happen to be used on MIPS
256 {"asciiz", s_stringer
, 1},
257 {"bss", s_change_sec
, 'b'},
260 {"dword", s_cons
, 3},
262 /* These pseudo-ops are defined in read.c, but must be overridden
263 here for one reason or another. */
264 {"align", s_align
, 0},
265 {"ascii", s_stringer
, 0},
266 {"asciz", s_stringer
, 1},
268 {"data", s_change_sec
, 'd'},
269 {"double", s_float_cons
, 'd'},
270 {"extern", s_extern
, 0},
271 {"float", s_float_cons
, 'f'},
272 {"space", s_mips_space
, 0},
273 {"text", s_change_sec
, 't'},
277 /* These pseudo-ops should be defined by the object file format.
278 However, ECOFF is the only format which currently defines them,
279 so we have versions here for a.out. */
281 {"end", s_mipsend
, 0},
284 {"fmask", s_ignore
, 'F'},
285 {"frame", s_ignore
, 0},
286 {"loc", s_ignore
, 0},
287 {"mask", s_ignore
, 'R'},
288 {"verstamp", s_ignore
, 0},
295 const relax_typeS md_relax_table
[] =
301 static char *expr_end
;
303 static expressionS imm_expr
;
304 static expressionS offset_expr
;
305 static bfd_reloc_code_real_type imm_reloc
;
306 static bfd_reloc_code_real_type offset_reloc
;
308 /* FIXME: This should be handled in a different way. */
309 extern int target_big_endian
;
312 * This function is called once, at assembler startup time. It should
313 * set up all the tables, etc. that the MD part of the assembler will need.
319 register const char *retval
= NULL
;
320 register unsigned int i
= 0;
324 if (strcmp (TARGET_CPU
, "mips") == 0)
326 else if (strcmp (TARGET_CPU
, "r6000") == 0
327 || strcmp (TARGET_CPU
, "mips2") == 0)
329 else if (strcmp (TARGET_CPU
, "mips64") == 0
330 || strcmp (TARGET_CPU
, "r4000") == 0
331 || strcmp (TARGET_CPU
, "mips3") == 0)
340 ok
= bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, 3000);
343 ok
= bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, 6000);
346 ok
= bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, 4000);
350 as_warn ("Could not set architecture and machine");
352 if ((op_hash
= hash_new ()) == NULL
)
354 as_fatal ("Virtual memory exhausted");
356 for (i
= 0; i
< NUMOPCODES
;)
358 const char *name
= mips_opcodes
[i
].name
;
360 retval
= hash_insert (op_hash
, name
, (PTR
) &mips_opcodes
[i
]);
363 fprintf (stderr
, "internal error: can't hash `%s': %s\n",
364 mips_opcodes
[i
].name
, retval
);
365 as_fatal ("Broken assembler. No assembly attempted.");
369 if (mips_opcodes
[i
].pinfo
!= INSN_MACRO
370 && ((mips_opcodes
[i
].match
& mips_opcodes
[i
].mask
)
371 != mips_opcodes
[i
].match
))
373 fprintf (stderr
, "internal error: bad opcode: `%s' \"%s\"\n",
374 mips_opcodes
[i
].name
, mips_opcodes
[i
].args
);
375 as_fatal ("Broken assembler. No assembly attempted.");
379 while ((i
< NUMOPCODES
) && !strcmp (mips_opcodes
[i
].name
, name
));
382 mips_no_prev_insn ();
390 /* set the default alignment for the text section (2**2) */
391 record_alignment (text_section
, 2);
393 /* FIXME: This should be handled in a different way. */
394 target_big_endian
= byte_order
== BIG_ENDIAN
;
397 bfd_set_gp_size (stdoutput
, g_switch_value
);
401 /* Create a .reginfo section for register masks. */
409 regsec
= subseg_new (".reginfo", (subsegT
) 0);
411 /* I don't know why this section should be loaded, but the ABI
412 says that SHF_ALLOC should be set. */
413 bfd_set_section_flags (stdoutput
, regsec
,
414 SEC_ALLOC
| SEC_LOAD
| SEC_READONLY
| SEC_DATA
);
416 mips_regmask_frag
= frag_more (sizeof (Elf32_External_RegInfo
));
418 subseg_set (seg
, subseg
);
439 struct mips_cl_insn insn
;
441 imm_expr
.X_op
= O_absent
;
442 offset_expr
.X_op
= O_absent
;
444 mips_ip (str
, &insn
);
447 as_bad ("%s `%s'", insn_error
, str
);
450 if (insn
.insn_mo
->pinfo
== INSN_MACRO
)
456 if (imm_expr
.X_op
!= O_absent
)
457 append_insn (&insn
, &imm_expr
, imm_reloc
);
458 else if (offset_expr
.X_op
!= O_absent
)
459 append_insn (&insn
, &offset_expr
, offset_reloc
);
461 append_insn (&insn
, NULL
, BFD_RELOC_UNUSED
);
465 /* See whether instruction IP reads register REG. If FPR is non-zero,
466 REG is a floating point register. */
469 insn_uses_reg (ip
, reg
, fpr
)
470 struct mips_cl_insn
*ip
;
474 /* Don't report on general register 0, since it never changes. */
475 if (! fpr
&& reg
== 0)
480 /* If we are called with either $f0 or $f1, we must check $f0.
481 This is not optimal, because it will introduce an unnecessary
482 NOP between "lwc1 $f0" and "swc1 $f1". To fix this we would
483 need to distinguish reading both $f0 and $f1 or just one of
484 them. Note that we don't have to check the other way,
485 because there is no instruction that sets both $f0 and $f1
486 and requires a delay. */
487 if ((ip
->insn_mo
->pinfo
& INSN_READ_FPR_S
)
488 && (((ip
->insn_opcode
>> OP_SH_FS
) & OP_MASK_FS
)
489 == (reg
&~ (unsigned) 1)))
491 if ((ip
->insn_mo
->pinfo
& INSN_READ_FPR_T
)
492 && (((ip
->insn_opcode
>> OP_SH_FT
) & OP_MASK_FT
)
493 == (reg
&~ (unsigned) 1)))
498 if ((ip
->insn_mo
->pinfo
& INSN_READ_GPR_S
)
499 && ((ip
->insn_opcode
>> OP_SH_RS
) & OP_MASK_RS
) == reg
)
501 if ((ip
->insn_mo
->pinfo
& INSN_READ_GPR_T
)
502 && ((ip
->insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
) == reg
)
509 #define ALIGN_ERR "Attempt to assemble instruction onto non word boundary."
510 #define ALIGN_ERR2 "GAS doesn't do implicit alignment; use .align directive."
514 * Output an instruction.
517 append_insn (ip
, address_expr
, reloc_type
)
518 struct mips_cl_insn
*ip
;
519 expressionS
*address_expr
;
520 bfd_reloc_code_real_type reloc_type
;
522 register unsigned long prev_pinfo
, pinfo
;
527 prev_pinfo
= prev_insn
.insn_mo
->pinfo
;
528 pinfo
= ip
->insn_mo
->pinfo
;
530 if (! mips_noreorder
)
532 /* If the previous insn required any delay slots, see if we need
533 to insert a NOP or two. There are eight kinds of possible
534 hazards, of which an instruction can have at most one type.
535 (1) a load from memory delay
536 (2) a load from a coprocessor delay
537 (3) an unconditional branch delay
538 (4) a conditional branch delay
539 (5) a move to coprocessor register delay
540 (6) a load coprocessor register from memory delay
541 (7) a coprocessor condition code delay
542 (8) a HI/LO special register delay
544 There are a lot of optimizations we could do that we don't.
545 In particular, we do not, in general, reorder instructions.
546 If you use gcc with optimization, it will reorder
547 instructions and generally do much more optimization then we
548 do here; repeating all that work in the assembler would only
549 benefit hand written assembly code, and does not seem worth
552 /* This is how a NOP is emitted. */
553 #define emit_nop() md_number_to_chars (frag_more (4), 0, 4)
555 /* The previous insn might require a delay slot, depending upon
556 the contents of the current insn. */
557 if ((prev_pinfo
& INSN_LOAD_COPROC_DELAY
)
559 && (prev_pinfo
& INSN_LOAD_MEMORY_DELAY
)))
561 /* A load from a coprocessor or from memory. All load
562 delays delay the use of general register rt for one
563 instruction on the r3000. The r6000 and r4000 use
565 know (prev_pinfo
& INSN_WRITE_GPR_T
);
566 if (mips_optimize
== 0
567 || insn_uses_reg (ip
,
568 ((prev_insn
.insn_opcode
>> OP_SH_RT
)
573 else if ((prev_pinfo
& INSN_COPROC_MOVE_DELAY
)
575 && (prev_pinfo
& INSN_COPROC_MEMORY_DELAY
)))
577 /* A generic coprocessor delay. The previous instruction
578 modified a coprocessor general or control register. If
579 it modified a control register, we need to avoid any
580 coprocessor instruction (this is probably not always
581 required, but it sometimes is). If it modified a general
582 register, we avoid using that register.
584 On the r6000 and r4000 loading a coprocessor register
585 from memory is interlocked, and does not require a delay.
587 This case is not handled very well. There is no special
588 knowledge of CP0 handling, and the coprocessors other
589 than the floating point unit are not distinguished at
591 if (prev_pinfo
& INSN_WRITE_FPR_T
)
593 if (mips_optimize
== 0
594 || insn_uses_reg (ip
,
595 ((prev_insn
.insn_opcode
>> OP_SH_FT
)
600 else if (prev_pinfo
& INSN_WRITE_FPR_S
)
602 if (mips_optimize
== 0
603 || insn_uses_reg (ip
,
604 ((prev_insn
.insn_opcode
>> OP_SH_FS
)
611 /* We don't know exactly what the previous instruction
612 does. If the current instruction uses a coprocessor
613 register, we must insert a NOP. If previous
614 instruction may set the condition codes, and the
615 current instruction uses them, we must insert two
617 if (mips_optimize
== 0
618 || ((prev_pinfo
& INSN_WRITE_COND_CODE
)
619 && (pinfo
& INSN_READ_COND_CODE
)))
621 else if (pinfo
& INSN_COP
)
625 else if (prev_pinfo
& INSN_WRITE_COND_CODE
)
627 /* The previous instruction sets the coprocessor condition
628 codes, but does not require a general coprocessor delay
629 (this means it is a floating point comparison
630 instruction). If this instruction uses the condition
631 codes, we need to insert a single NOP. */
632 if (mips_optimize
== 0
633 || (pinfo
& INSN_READ_COND_CODE
))
636 else if (prev_pinfo
& INSN_READ_LO
)
638 /* The previous instruction reads the LO register; if the
639 current instruction writes to the LO register, we must
641 if (mips_optimize
== 0
642 || (pinfo
& INSN_WRITE_LO
))
645 else if (prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
647 /* The previous instruction reads the HI register; if the
648 current instruction writes to the HI register, we must
650 if (mips_optimize
== 0
651 || (pinfo
& INSN_WRITE_HI
))
655 /* There are two cases which require two intervening
656 instructions: 1) setting the condition codes using a move to
657 coprocessor instruction which requires a general coprocessor
658 delay and then reading the condition codes 2) reading the HI
659 or LO register and then writing to it. If we are not already
660 emitting a NOP instruction, we must check for these cases
661 compared to the instruction previous to the previous
664 && (((prev_prev_insn
.insn_mo
->pinfo
& INSN_COPROC_MOVE_DELAY
)
665 && (prev_prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
)
666 && (pinfo
& INSN_READ_COND_CODE
))
667 || ((prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
)
668 && (pinfo
& INSN_WRITE_LO
))
669 || ((prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
670 && (pinfo
& INSN_WRITE_HI
))))
673 /* Now emit the right number of NOP instructions. */
679 if (insn_label
!= NULL
)
681 assert (S_GET_SEGMENT (insn_label
) == now_seg
);
682 insn_label
->sy_frag
= frag_now
;
683 S_SET_VALUE (insn_label
, (valueT
) frag_now_fix ());
690 /* This is testing the address of the frag, not the alignment of
691 the instruction in the current section. */
699 if (address_expr
!= NULL
)
701 if (address_expr
->X_op
== O_constant
)
706 ip
->insn_opcode
|= address_expr
->X_add_number
;
710 ip
->insn_opcode
|= address_expr
->X_add_number
& 0xffff;
713 case BFD_RELOC_MIPS_JMP
:
714 case BFD_RELOC_16_PCREL_S2
:
723 assert (reloc_type
!= BFD_RELOC_UNUSED
);
725 fixp
= fix_new_exp (frag_now
, f
- frag_now
->fr_literal
, 4,
727 reloc_type
== BFD_RELOC_16_PCREL_S2
,
732 md_number_to_chars (f
, ip
->insn_opcode
, 4);
734 /* Update the register mask information. */
735 if (pinfo
& INSN_WRITE_GPR_D
)
736 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
);
737 if ((pinfo
& (INSN_WRITE_GPR_T
| INSN_READ_GPR_T
)) != 0)
738 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
);
739 if (pinfo
& INSN_READ_GPR_S
)
740 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> OP_SH_RS
) & OP_MASK_RS
);
741 if (pinfo
& INSN_WRITE_GPR_31
)
742 mips_gprmask
|= 1 << 31;
743 if (pinfo
& INSN_WRITE_FPR_D
)
744 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FD
) & OP_MASK_FD
);
745 if ((pinfo
& (INSN_WRITE_FPR_S
| INSN_READ_FPR_S
)) != 0)
746 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FS
) & OP_MASK_FS
);
747 if ((pinfo
& (INSN_WRITE_FPR_T
| INSN_READ_FPR_T
)) != 0)
748 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FT
) & OP_MASK_FT
);
749 if (pinfo
& INSN_COP
)
751 /* We don't keep enough information to sort these cases out. */
753 /* Never set the bit for $0, which is always zero. */
754 mips_gprmask
&=~ 1 << 0;
756 if (! mips_noreorder
)
758 /* Filling the branch delay slot is more complex. We try to
759 switch the branch with the previous instruction, which we can
760 do if the previous instruction does not set up a condition
761 that the branch tests and if the branch is not itself the
762 target of any branch. */
763 if ((pinfo
& INSN_UNCOND_BRANCH_DELAY
)
764 || (pinfo
& INSN_COND_BRANCH_DELAY
))
766 if (mips_optimize
< 2
767 /* If we have seen .set nobopt, don't optimize. */
769 /* If we have seen .set volatile or .set nomove, don't
772 /* If we had to emit any NOP instructions, then we
773 already know we can not swap. */
775 /* If we don't even know the previous insn, we can not
778 /* If the previous insn is already in a branch delay
779 slot, then we can not swap. */
780 || prev_insn_is_delay_slot
781 /* If the previous previous insn was in a .set
782 noreorder, we can't swap. Actually, the MIPS
783 assembler will swap in this situation. However, gcc
784 configured -with-gnu-as will generate code like
790 in which we can not swap the bne and INSN. If gcc is
791 not configured -with-gnu-as, it does not output the
792 .set pseudo-ops. We don't have to check
793 prev_insn_unreordered, because prev_insn_valid will
794 be 0 in that case. We don't want to use
795 prev_prev_insn_valid, because we do want to be able
796 to swap at the start of a function. */
797 || prev_prev_insn_unreordered
798 /* If the branch is itself the target of a branch, we
799 can not swap. We cheat on this; all we check for is
800 whether there is a label on this instruction. If
801 there are any branches to anything other than a
802 label, users must use .set noreorder. */
803 || insn_label
!= NULL
804 /* If the branch reads the condition codes, we don't
805 even try to swap, because in the sequence
810 we can not swap, and I don't feel like handling that
812 || (pinfo
& INSN_READ_COND_CODE
)
813 /* We can not swap with an instruction that requires a
814 delay slot, becase the target of the branch might
815 interfere with that instruction. */
817 & (INSN_LOAD_COPROC_DELAY
818 | INSN_COPROC_MOVE_DELAY
819 | INSN_WRITE_COND_CODE
824 & (INSN_LOAD_MEMORY_DELAY
825 | INSN_COPROC_MEMORY_DELAY
)))
826 /* We can not swap with a branch instruction. */
828 & (INSN_UNCOND_BRANCH_DELAY
829 | INSN_COND_BRANCH_DELAY
830 | INSN_COND_BRANCH_LIKELY
))
831 /* We do not swap with a trap instruction, since it
832 complicates trap handlers to have the trap
833 instruction be in a delay slot. */
834 || (prev_pinfo
& INSN_TRAP
)
835 /* If the branch reads a register that the previous
836 instruction sets, we can not swap. */
837 || ((prev_pinfo
& INSN_WRITE_GPR_T
)
838 && insn_uses_reg (ip
,
839 ((prev_insn
.insn_opcode
>> OP_SH_RT
)
842 || ((prev_pinfo
& INSN_WRITE_GPR_D
)
843 && insn_uses_reg (ip
,
844 ((prev_insn
.insn_opcode
>> OP_SH_RD
)
847 /* If the branch writes a register that the previous
848 instruction sets, we can not swap (we know that
849 branches write only to RD or to $31). */
850 || ((prev_pinfo
& INSN_WRITE_GPR_T
)
851 && (((pinfo
& INSN_WRITE_GPR_D
)
852 && (((prev_insn
.insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
)
853 == ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)))
854 || ((pinfo
& INSN_WRITE_GPR_31
)
855 && (((prev_insn
.insn_opcode
>> OP_SH_RT
)
858 || ((prev_pinfo
& INSN_WRITE_GPR_D
)
859 && (((pinfo
& INSN_WRITE_GPR_D
)
860 && (((prev_insn
.insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)
861 == ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)))
862 || ((pinfo
& INSN_WRITE_GPR_31
)
863 && (((prev_insn
.insn_opcode
>> OP_SH_RD
)
866 /* If the branch writes a register that the previous
867 instruction reads, we can not swap (we know that
868 branches only write to RD or to $31). */
869 || ((pinfo
& INSN_WRITE_GPR_D
)
870 && insn_uses_reg (&prev_insn
,
871 ((ip
->insn_opcode
>> OP_SH_RD
)
874 || ((pinfo
& INSN_WRITE_GPR_31
)
875 && insn_uses_reg (&prev_insn
, 31, 0))
876 /* If the previous previous instruction has a load
877 delay, and sets a register that the branch reads, we
879 || (((prev_prev_insn
.insn_mo
->pinfo
& INSN_LOAD_COPROC_DELAY
)
881 && (prev_prev_insn
.insn_mo
->pinfo
882 & INSN_LOAD_MEMORY_DELAY
)))
883 && insn_uses_reg (ip
,
884 ((prev_prev_insn
.insn_opcode
>> OP_SH_RT
)
888 /* We could do even better for unconditional branches to
889 portions of this object file; we could pick up the
890 instruction at the destination, put it in the delay
891 slot, and bump the destination address. */
893 /* Update the previous insn information. */
894 prev_prev_insn
= *ip
;
895 prev_insn
.insn_mo
= &dummy_opcode
;
902 /* It looks like we can actually do the swap. */
903 prev_f
= prev_insn_frag
->fr_literal
+ prev_insn_where
;
904 memcpy (temp
, prev_f
, 4);
905 memcpy (prev_f
, f
, 4);
909 prev_insn_fixp
->fx_frag
= frag_now
;
910 prev_insn_fixp
->fx_where
= f
- frag_now
->fr_literal
;
914 fixp
->fx_frag
= prev_insn_frag
;
915 fixp
->fx_where
= prev_insn_where
;
917 /* Update the previous insn information; leave prev_insn
919 prev_prev_insn
= *ip
;
921 prev_insn_is_delay_slot
= 1;
923 /* If that was an unconditional branch, forget the previous
925 if (pinfo
& INSN_UNCOND_BRANCH_DELAY
)
927 prev_prev_insn
.insn_mo
= &dummy_opcode
;
928 prev_insn
.insn_mo
= &dummy_opcode
;
931 else if (pinfo
& INSN_COND_BRANCH_LIKELY
)
933 /* We don't yet optimize a branch likely. What we should do
934 is look at the target, copy the instruction found there
935 into the delay slot, and increment the branch to jump to
936 the next instruction. */
938 /* Update the previous insn information. */
939 prev_prev_insn
= *ip
;
940 prev_insn
.insn_mo
= &dummy_opcode
;
944 /* Update the previous insn information. */
946 prev_prev_insn
.insn_mo
= &dummy_opcode
;
948 prev_prev_insn
= prev_insn
;
951 /* Any time we see a branch, we always fill the delay slot
952 immediately; since this insn is not a branch, we know it
953 is not in a delay slot. */
954 prev_insn_is_delay_slot
= 0;
957 prev_prev_insn_unreordered
= prev_insn_unreordered
;
958 prev_insn_unreordered
= 0;
959 prev_insn_frag
= frag_now
;
960 prev_insn_where
= f
- frag_now
->fr_literal
;
961 prev_insn_fixp
= fixp
;
965 /* We just output an insn, so the next one doesn't have a label. */
969 /* This function forgets that there was any previous instruction or
975 prev_insn
.insn_mo
= &dummy_opcode
;
976 prev_prev_insn
.insn_mo
= &dummy_opcode
;
978 prev_insn_is_delay_slot
= 0;
979 prev_insn_unreordered
= 0;
980 prev_prev_insn_unreordered
= 0;
984 /* This function must be called whenever we turn on noreorder or emit
985 something other than instructions. It inserts any NOPS which might
986 be needed by the previous instruction, and clears the information
987 kept for the previous instructions. */
992 if (! mips_noreorder
)
997 if ((prev_insn
.insn_mo
->pinfo
998 & (INSN_LOAD_COPROC_DELAY
999 | INSN_COPROC_MOVE_DELAY
1000 | INSN_WRITE_COND_CODE
1004 && (prev_insn
.insn_mo
->pinfo
1005 & (INSN_LOAD_MEMORY_DELAY
1006 | INSN_COPROC_MEMORY_DELAY
))))
1009 if ((prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
)
1010 || (prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
1011 || (prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
))
1014 else if ((prev_prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
)
1015 || (prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
1016 || (prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
))
1021 if (insn_label
!= NULL
)
1023 assert (S_GET_SEGMENT (insn_label
) == now_seg
);
1024 insn_label
->sy_frag
= frag_now
;
1025 S_SET_VALUE (insn_label
, (valueT
) frag_now_fix ());
1028 mips_no_prev_insn ();
1032 /* Return 1 if an expression can be accessed via the GP register. */
1040 const char *symname
;
1041 const char *segname
;
1043 sym
= ep
->X_add_symbol
;
1044 if (sym
== (symbolS
*) NULL
1045 || ep
->X_op_symbol
!= (symbolS
*) NULL
)
1048 /* Certain symbols can not be referenced off the GP, although it
1049 appears as though they can. */
1050 symname
= S_GET_NAME (sym
);
1051 if (symname
!= (const char *) NULL
1052 && (strcmp (symname
, "eprol") == 0
1053 || strcmp (symname
, "etext") == 0
1054 || strcmp (symname
, "_gp") == 0
1055 || strcmp (symname
, "edata") == 0
1056 || strcmp (symname
, "_fbss") == 0
1057 || strcmp (symname
, "_fdata") == 0
1058 || strcmp (symname
, "_ftext") == 0
1059 || strcmp (symname
, "end") == 0))
1061 if (! S_IS_DEFINED (sym
)
1062 && S_GET_VALUE (sym
) != 0
1063 && S_GET_VALUE (sym
) <= g_switch_value
)
1065 segname
= segment_name (S_GET_SEGMENT (ep
->X_add_symbol
));
1066 return (strcmp (segname
, ".sdata") == 0
1067 || strcmp (segname
, ".sbss") == 0
1068 || strcmp (segname
, ".lit8") == 0
1069 || strcmp (segname
, ".lit4") == 0);
1070 #else /* ! defined (GPOPT) */
1071 /* We are not optimizing for the GP register. */
1073 #endif /* ! defined (GPOPT) */
1076 /* Build an instruction created by a macro expansion. This is passed
1077 a pointer to the count of instructions created so far, an
1078 expression, the name of the instruction to build, an operand format
1079 string, and corresponding arguments. */
1083 macro_build (int *counter
,
1088 #else /* ! defined (NO_STDARG) */
1090 macro_build (counter
, ep
, name
, fmt
, va_alist
)
1096 #endif /* ! defined (NO_STDARG) */
1098 struct mips_cl_insn insn
;
1099 bfd_reloc_code_real_type r
;
1103 va_start (args
, fmt
);
1109 * If the macro is about to expand into a second instruction,
1110 * print a warning if needed. We need to pass ip as a parameter
1111 * to generate a better warning message here...
1113 if (mips_warn_about_macros
&& *counter
== 1)
1114 as_warn ("Macro instruction expanded into multiple instructions");
1116 *counter
+= 1; /* bump instruction counter */
1118 r
= BFD_RELOC_UNUSED
;
1119 insn
.insn_mo
= (struct mips_opcode
*) hash_find (op_hash
, name
);
1120 assert (insn
.insn_mo
);
1121 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
1123 while (strcmp (fmt
, insn
.insn_mo
->args
) != 0)
1126 assert (insn
.insn_mo
->name
);
1127 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
1129 assert (insn
.insn_mo
->pinfo
!= INSN_MACRO
);
1130 insn
.insn_opcode
= insn
.insn_mo
->match
;
1146 insn
.insn_opcode
|= va_arg (args
, int) << 16;
1152 insn
.insn_opcode
|= va_arg (args
, int) << 16;
1157 insn
.insn_opcode
|= va_arg (args
, int) << 11;
1162 insn
.insn_opcode
|= va_arg (args
, int) << 11;
1170 insn
.insn_opcode
|= va_arg (args
, int) << 6;
1174 insn
.insn_opcode
|= va_arg (args
, int) << 6;
1178 insn
.insn_opcode
|= va_arg (args
, int) << 6;
1185 insn
.insn_opcode
|= va_arg (args
, int) << 21;
1195 assert (ep
!= NULL
&& ep
->X_op
== O_constant
);
1196 insn
.insn_opcode
|= (ep
->X_add_number
>> 16) & 0xffff;
1201 assert (ep
!= NULL
);
1203 * This allows macro() to pass an immediate expression for
1204 * creating short branches without creating a symbol.
1205 * Note that the expression still might come from the assembly
1206 * input, in which case the value is not checked for range nor
1207 * is a relocation entry generated (yuck).
1209 if (ep
->X_op
== O_constant
)
1211 insn
.insn_opcode
|= (ep
->X_add_number
>> 2) & 0xffff;
1215 r
= BFD_RELOC_16_PCREL_S2
;
1224 assert (r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
1226 /* Use GP relative addressing if possible. */
1227 if (r
== BFD_RELOC_LO16
1228 && gp_reference (ep
))
1229 r
= BFD_RELOC_MIPS_GPREL
;
1231 append_insn (&insn
, ep
, r
);
1235 * Generate a "lui" instruction.
1238 macro_build_lui (counter
, ep
, regnum
)
1243 expressionS high_expr
;
1244 struct mips_cl_insn insn
;
1245 bfd_reloc_code_real_type r
;
1246 CONST
char *name
= "lui";
1247 CONST
char *fmt
= "t,u";
1251 if (high_expr
.X_op
== O_constant
)
1253 /* we can compute the instruction now without a relocation entry */
1254 if (high_expr
.X_add_number
& 0x8000)
1255 high_expr
.X_add_number
+= 0x10000;
1256 high_expr
.X_add_number
=
1257 ((unsigned long) high_expr
.X_add_number
>> 16) & 0xffff;
1258 r
= BFD_RELOC_UNUSED
;
1261 r
= BFD_RELOC_HI16_S
;
1264 * If the macro is about to expand into a second instruction,
1265 * print a warning if needed. We need to pass ip as a parameter
1266 * to generate a better warning message here...
1268 if (mips_warn_about_macros
&& *counter
== 1)
1269 as_warn ("Macro instruction expanded into multiple instructions");
1271 *counter
+= 1; /* bump instruction counter */
1273 insn
.insn_mo
= (struct mips_opcode
*) hash_find (op_hash
, name
);
1274 assert (insn
.insn_mo
);
1275 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
1276 assert (strcmp (fmt
, insn
.insn_mo
->args
) == 0);
1278 insn
.insn_opcode
= insn
.insn_mo
->match
| (regnum
<< 16);
1279 if (r
== BFD_RELOC_UNUSED
)
1281 insn
.insn_opcode
|= high_expr
.X_add_number
;
1282 append_insn (&insn
, NULL
, r
);
1285 append_insn (&insn
, &high_expr
, r
);
1289 * Generates code to set the $at register to true (one)
1290 * if reg is less than the immediate expression.
1293 set_at (counter
, reg
, unsignedp
)
1298 if (imm_expr
.X_add_number
>= -0x8000 && imm_expr
.X_add_number
< 0x8000)
1299 macro_build (counter
, &imm_expr
,
1300 unsignedp
? "sltiu" : "slti",
1304 load_register (counter
, AT
, &imm_expr
);
1305 macro_build (counter
, NULL
,
1306 unsignedp
? "sltu" : "slt",
1307 "d,v,t", AT
, reg
, AT
);
1311 /* Warn if an expression is not a constant. */
1314 check_absolute_expr (ip
, ex
)
1315 struct mips_cl_insn
*ip
;
1318 if (ex
->X_op
!= O_constant
)
1319 as_warn ("Instruction %s requires absolute expression", ip
->insn_mo
->name
);
1323 * This routine generates the least number of instructions neccessary to load
1324 * an absolute expression value into a register.
1327 load_register (counter
, reg
, ep
)
1332 assert (ep
->X_op
== O_constant
);
1333 if (ep
->X_add_number
>= -0x8000 && ep
->X_add_number
< 0x8000)
1334 macro_build (counter
, ep
,
1335 mips_isa
< 3 ? "addiu" : "daddiu",
1337 else if (ep
->X_add_number
>= 0 && ep
->X_add_number
< 0x10000)
1338 macro_build (counter
, ep
, "ori", "t,r,i", reg
, 0);
1339 else if ((ep
->X_add_number
&~ (offsetT
) 0x7fffffff) == 0
1340 || ((ep
->X_add_number
&~ (offsetT
) 0x7fffffff)
1341 == ~ (offsetT
) 0x7fffffff))
1343 macro_build (counter
, ep
, "lui", "t,u", reg
);
1344 if ((ep
->X_add_number
& 0xffff) != 0)
1345 macro_build (counter
, ep
, "ori", "t,r,i", reg
, reg
);
1347 else if (mips_isa
< 3)
1349 as_bad ("Number larger than 32 bits");
1350 macro_build (counter
, ep
, "addiu", "t,r,j", reg
, 0);
1355 expressionS hi32
, lo32
;
1359 hi32
.X_add_number
>>= shift
;
1360 hi32
.X_add_number
&= 0xffffffff;
1361 if ((hi32
.X_add_number
& 0x80000000) != 0)
1362 hi32
.X_add_number
|= ~ (offsetT
) 0xffffffff;
1363 load_register (counter
, reg
, &hi32
);
1365 lo32
.X_add_number
&= 0xffffffff;
1366 if ((lo32
.X_add_number
& 0xffff0000) == 0)
1367 macro_build (counter
, NULL
, "dsll32", "d,w,<", reg
, reg
, 0);
1372 macro_build (counter
, NULL
, "dsll", "d,w,<", reg
, reg
, 16);
1374 mid16
.X_add_number
>>= 16;
1375 macro_build (counter
, &mid16
, "ori", "t,r,i", reg
, reg
);
1376 macro_build (counter
, NULL
, "dsll", "d,w,<", reg
, reg
, 16);
1378 if ((lo32
.X_add_number
& 0xffff) != 0)
1379 macro_build (counter
, &lo32
, "ori", "t,r,i", reg
, reg
);
1385 * This routine implements the seemingly endless macro or synthesized
1386 * instructions and addressing modes in the mips assembly language. Many
1387 * of these macros are simple and are similar to each other. These could
1388 * probably be handled by some kind of table or grammer aproach instead of
1389 * this verbose method. Others are not simple macros but are more like
1390 * optimizing code generation.
1391 * One interesting optimization is when several store macros appear
1392 * consecutivly that would load AT with the upper half of the same address.
1393 * The ensuing load upper instructions are ommited. This implies some kind
1394 * of global optimization. We currently only optimize within a single macro.
1395 * For many of the load and store macros if the address is specified as a
1396 * constant expression in the first 64k of memory (ie ld $2,0x4000c) we
1397 * first load register 'at' with zero and use it as the base register. The
1398 * mips assembler simply uses register $zero. Just one tiny optimization
1403 struct mips_cl_insn
*ip
;
1405 register int treg
, sreg
, dreg
, breg
;
1419 treg
= (ip
->insn_opcode
>> 16) & 0x1f;
1420 dreg
= (ip
->insn_opcode
>> 11) & 0x1f;
1421 sreg
= breg
= (ip
->insn_opcode
>> 21) & 0x1f;
1422 mask
= ip
->insn_mo
->mask
;
1424 expr1
.X_op
= O_constant
;
1425 expr1
.X_op_symbol
= NULL
;
1426 expr1
.X_add_symbol
= NULL
;
1427 expr1
.X_add_number
= 1;
1439 mips_emit_delays ();
1442 expr1
.X_add_number
= 8;
1443 macro_build (&icnt
, &expr1
, "bgez", "s,p", sreg
);
1445 macro_build (&icnt
, NULL
, "nop", "", 0);
1447 macro_build (&icnt
, NULL
, "move", "d,s", dreg
, sreg
, 0);
1448 macro_build (&icnt
, NULL
,
1449 dbl
? "dsub" : "sub",
1450 "d,v,t", dreg
, 0, sreg
);
1473 if (imm_expr
.X_add_number
>= -0x8000 && imm_expr
.X_add_number
< 0x8000)
1475 macro_build (&icnt
, &imm_expr
, s
, "t,r,j", treg
, sreg
);
1478 load_register (&icnt
, AT
, &imm_expr
);
1479 macro_build (&icnt
, NULL
, s2
, "d,v,t", treg
, sreg
, AT
);
1498 if (imm_expr
.X_add_number
>= 0 && imm_expr
.X_add_number
< 0x10000)
1500 if (mask
!= M_NOR_I
)
1501 macro_build (&icnt
, &imm_expr
, s
, "t,r,i", treg
, sreg
);
1504 macro_build (&icnt
, &imm_expr
, "ori", "t,r,i", treg
, sreg
);
1505 macro_build (&icnt
, &imm_expr
, "nor", "d,v,t", treg
, treg
, 0);
1510 load_register (&icnt
, AT
, &imm_expr
);
1511 macro_build (&icnt
, NULL
, s2
, "d,v,t", treg
, sreg
, AT
);
1528 if (imm_expr
.X_add_number
== 0)
1530 macro_build (&icnt
, &offset_expr
, s
, "s,t,p", sreg
, 0);
1533 load_register (&icnt
, AT
, &imm_expr
);
1534 macro_build (&icnt
, &offset_expr
, s
, "s,t,p", sreg
, AT
);
1542 macro_build (&icnt
, &offset_expr
,
1543 likely
? "bgezl" : "bgez",
1549 macro_build (&icnt
, &offset_expr
,
1550 likely
? "blezl" : "blez",
1554 macro_build (&icnt
, NULL
, "slt", "d,v,t", AT
, sreg
, treg
);
1555 macro_build (&icnt
, &offset_expr
,
1556 likely
? "beql" : "beq",
1563 /* check for > max integer */
1564 maxnum
= 0x7fffffff;
1572 if (imm_expr
.X_add_number
>= maxnum
)
1575 /* result is always false */
1578 as_warn ("Branch %s is always false (nop)", ip
->insn_mo
->name
);
1579 macro_build (&icnt
, NULL
, "nop", "", 0);
1583 as_warn ("Branch likely %s is always false", ip
->insn_mo
->name
);
1584 macro_build (&icnt
, &offset_expr
, "bnel", "s,t,p", 0, 0);
1588 imm_expr
.X_add_number
++;
1592 if (mask
== M_BGEL_I
)
1594 if (imm_expr
.X_add_number
== 0)
1596 macro_build (&icnt
, &offset_expr
,
1597 likely
? "bgezl" : "bgez",
1601 if (imm_expr
.X_add_number
== 1)
1603 macro_build (&icnt
, &offset_expr
,
1604 likely
? "bgtzl" : "bgtz",
1608 maxnum
= 0x7fffffff;
1616 maxnum
= - maxnum
- 1;
1617 if (imm_expr
.X_add_number
<= maxnum
)
1620 /* result is always true */
1621 as_warn ("Branch %s is always true", ip
->insn_mo
->name
);
1622 macro_build (&icnt
, &offset_expr
, "b", "p");
1625 set_at (&icnt
, sreg
, 0);
1626 macro_build (&icnt
, &offset_expr
,
1627 likely
? "beql" : "beq",
1638 macro_build (&icnt
, &offset_expr
,
1639 likely
? "beql" : "beq",
1643 macro_build (&icnt
, NULL
, "sltu", "d,v,t", AT
, sreg
, treg
);
1644 macro_build (&icnt
, &offset_expr
,
1645 likely
? "beql" : "beq",
1652 if (sreg
== 0 || imm_expr
.X_add_number
== -1)
1654 imm_expr
.X_add_number
++;
1658 if (mask
== M_BGEUL_I
)
1660 if (imm_expr
.X_add_number
== 0)
1662 if (imm_expr
.X_add_number
== 1)
1664 macro_build (&icnt
, &offset_expr
,
1665 likely
? "bnel" : "bne",
1669 set_at (&icnt
, sreg
, 1);
1670 macro_build (&icnt
, &offset_expr
,
1671 likely
? "beql" : "beq",
1680 macro_build (&icnt
, &offset_expr
,
1681 likely
? "bgtzl" : "bgtz",
1687 macro_build (&icnt
, &offset_expr
,
1688 likely
? "bltzl" : "bltz",
1692 macro_build (&icnt
, NULL
, "slt", "d,v,t", AT
, treg
, sreg
);
1693 macro_build (&icnt
, &offset_expr
,
1694 likely
? "bnel" : "bne",
1703 macro_build (&icnt
, &offset_expr
,
1704 likely
? "bnel" : "bne",
1710 macro_build (&icnt
, NULL
, "sltu", "d,v,t", AT
, treg
, sreg
);
1711 macro_build (&icnt
, &offset_expr
,
1712 likely
? "bnel" : "bne",
1721 macro_build (&icnt
, &offset_expr
,
1722 likely
? "blezl" : "blez",
1728 macro_build (&icnt
, &offset_expr
,
1729 likely
? "bgezl" : "bgez",
1733 macro_build (&icnt
, NULL
, "slt", "d,v,t", AT
, treg
, sreg
);
1734 macro_build (&icnt
, &offset_expr
,
1735 likely
? "beql" : "beq",
1742 maxnum
= 0x7fffffff;
1750 if (imm_expr
.X_add_number
>= maxnum
)
1752 imm_expr
.X_add_number
++;
1756 if (mask
== M_BLTL_I
)
1758 if (imm_expr
.X_add_number
== 0)
1760 macro_build (&icnt
, &offset_expr
,
1761 likely
? "bltzl" : "bltz",
1765 if (imm_expr
.X_add_number
== 1)
1767 macro_build (&icnt
, &offset_expr
,
1768 likely
? "blezl" : "blez",
1772 set_at (&icnt
, sreg
, 0);
1773 macro_build (&icnt
, &offset_expr
,
1774 likely
? "bnel" : "bne",
1783 macro_build (&icnt
, &offset_expr
,
1784 likely
? "beql" : "beq",
1790 macro_build (&icnt
, NULL
, "sltu", "d,v,t", AT
, treg
, sreg
);
1791 macro_build (&icnt
, &offset_expr
,
1792 likely
? "beql" : "beq",
1799 if (sreg
== 0 || imm_expr
.X_add_number
== -1)
1801 imm_expr
.X_add_number
++;
1805 if (mask
== M_BLTUL_I
)
1807 if (imm_expr
.X_add_number
== 0)
1809 if (imm_expr
.X_add_number
== 1)
1811 macro_build (&icnt
, &offset_expr
,
1812 likely
? "beql" : "beq",
1816 set_at (&icnt
, sreg
, 1);
1817 macro_build (&icnt
, &offset_expr
,
1818 likely
? "bnel" : "bne",
1827 macro_build (&icnt
, &offset_expr
,
1828 likely
? "bltzl" : "bltz",
1834 macro_build (&icnt
, &offset_expr
,
1835 likely
? "bgtzl" : "bgtz",
1839 macro_build (&icnt
, NULL
, "slt", "d,v,t", AT
, sreg
, treg
);
1840 macro_build (&icnt
, &offset_expr
,
1841 likely
? "bnel" : "bne",
1852 macro_build (&icnt
, &offset_expr
,
1853 likely
? "bnel" : "bne",
1857 macro_build (&icnt
, NULL
, "sltu", "d,v,t", AT
, sreg
, treg
);
1858 macro_build (&icnt
, &offset_expr
,
1859 likely
? "bnel" : "bne",
1875 as_warn ("Divide by zero.");
1876 macro_build (&icnt
, NULL
, "break", "c", 7);
1880 mips_emit_delays ();
1882 macro_build (&icnt
, NULL
,
1883 dbl
? "ddiv" : "div",
1884 "z,s,t", sreg
, treg
);
1885 expr1
.X_add_number
= 8;
1886 macro_build (&icnt
, &expr1
, "bne", "s,t,p", treg
, 0);
1887 macro_build (&icnt
, NULL
, "nop", "", 0);
1888 macro_build (&icnt
, NULL
, "break", "c", 7);
1889 expr1
.X_add_number
= -1;
1890 macro_build (&icnt
, &expr1
,
1891 dbl
? "daddiu" : "addiu",
1893 expr1
.X_add_number
= dbl
? 20 : 16;
1894 macro_build (&icnt
, &expr1
, "bne", "s,t,p", treg
, AT
);
1897 expr1
.X_add_number
= 1;
1898 macro_build (&icnt
, &expr1
, "daddiu", "t,r,j", AT
, 0);
1899 macro_build (&icnt
, NULL
, "dsll32", "d,w,<", AT
, AT
, 31);
1903 expr1
.X_add_number
= 0x80000000;
1904 macro_build (&icnt
, &expr1
, "lui", "t,u", AT
);
1906 expr1
.X_add_number
= 8;
1907 macro_build (&icnt
, &expr1
, "bne", "s,t,p", sreg
, AT
);
1908 macro_build (&icnt
, NULL
, "nop", "", 0);
1909 macro_build (&icnt
, NULL
, "break", "c", 6);
1911 macro_build (&icnt
, NULL
, s
, "d", dreg
);
1950 if (imm_expr
.X_add_number
== 0)
1952 as_warn ("Divide by zero.");
1953 macro_build (&icnt
, NULL
, "break", "c", 7);
1956 if (imm_expr
.X_add_number
== 1)
1958 if (strcmp (s2
, "mflo") == 0)
1959 macro_build (&icnt
, NULL
, "move", "d,s", dreg
, sreg
);
1961 macro_build (&icnt
, NULL
, "move", "d,s", dreg
, 0);
1964 if (imm_expr
.X_add_number
== -1
1965 && s
[strlen (s
) - 1] != 'u')
1967 if (strcmp (s2
, "mflo") == 0)
1970 macro_build (&icnt
, NULL
, "dneg", "d,w", dreg
, sreg
);
1972 macro_build (&icnt
, NULL
, "neg", "d,w", dreg
, sreg
);
1975 macro_build (&icnt
, NULL
, "move", "d,s", dreg
, 0);
1979 load_register (&icnt
, AT
, &imm_expr
);
1980 macro_build (&icnt
, NULL
, s
, "z,s,t", sreg
, AT
);
1981 macro_build (&icnt
, NULL
, s2
, "d", dreg
);
2000 mips_emit_delays ();
2002 macro_build (&icnt
, NULL
, s
, "z,s,t", sreg
, treg
);
2003 expr1
.X_add_number
= 8;
2004 macro_build (&icnt
, &expr1
, "bne", "s,t,p", treg
, 0);
2005 macro_build (&icnt
, NULL
, "nop", "", 0);
2006 macro_build (&icnt
, NULL
, "break", "c", 7);
2008 macro_build (&icnt
, NULL
, s2
, "d", dreg
);
2012 if (offset_expr
.X_op
== O_constant
)
2014 load_register (&icnt
, treg
, &offset_expr
);
2017 if (gp_reference (&offset_expr
))
2018 macro_build (&icnt
, &offset_expr
,
2019 mips_isa
< 3 ? "addiu" : "daddiu",
2023 /* FIXME: This won't work for a 64 bit address. */
2024 macro_build_lui (&icnt
, &offset_expr
, treg
);
2025 macro_build (&icnt
, &offset_expr
,
2026 mips_isa
< 3 ? "addiu" : "daddiu",
2027 "t,r,j", treg
, treg
);
2032 tempreg
= (breg
== treg
) ? AT
: treg
;
2033 if (offset_expr
.X_op
== O_constant
)
2034 load_register (&icnt
, tempreg
, &offset_expr
);
2035 else if (gp_reference (&offset_expr
))
2036 macro_build (&icnt
, &offset_expr
,
2037 mips_isa
< 3 ? "addiu" : "daddiu",
2038 "t,r,j", tempreg
, GP
);
2041 /* FIXME: This won't work for a 64 bit address. */
2042 macro_build_lui (&icnt
, &offset_expr
, tempreg
);
2043 macro_build (&icnt
, &offset_expr
,
2044 mips_isa
< 3 ? "addiu" : "daddiu",
2045 "t,r,j", tempreg
, tempreg
);
2048 macro_build (&icnt
, NULL
, "addu", "d,v,t", treg
, tempreg
, breg
);
2118 if (breg
== treg
|| coproc
)
2187 if (mask
== M_LWC1_AB
2188 || mask
== M_SWC1_AB
2190 || mask
== M_LDC1_AB
2191 || mask
== M_SDC1_AB
)
2197 if (gp_reference (&offset_expr
))
2201 macro_build (&icnt
, &offset_expr
, s
, fmt
, treg
, GP
);
2204 macro_build (&icnt
, (expressionS
*) NULL
,
2205 mips_isa
< 3 ? "addu" : "daddu",
2206 "d,v,t", tempreg
, breg
, GP
);
2210 /* FIXME: This won't work for a 64 bit address. */
2211 macro_build_lui (&icnt
, &offset_expr
, tempreg
);
2213 macro_build (&icnt
, NULL
,
2214 mips_isa
< 3 ? "addu" : "daddu",
2215 "d,v,t", tempreg
, tempreg
, breg
);
2217 macro_build (&icnt
, &offset_expr
, s
, fmt
, treg
, tempreg
);
2224 load_register (&icnt
, treg
, &imm_expr
);
2229 lw $v0,%lo(foo)($at)
2230 lw $v1,%lo(foo+4)($at)
2235 /* FIXME: This won't work for a 64 bit address. */
2236 macro_build_lui (&icnt
, &offset_expr
, AT
);
2238 macro_build (&icnt
, &offset_expr
, "ld", "t,o(b)", treg
, AT
);
2241 macro_build (&icnt
, &offset_expr
, "lw", "t,o(b)", treg
, AT
);
2242 offset_expr
.X_add_number
+= 4;
2243 macro_build (&icnt
, &offset_expr
, "lw", "t,o(b)", treg
+ 1, AT
);
2248 /* Load a floating point number from the .lit8 section. */
2251 macro_build (&icnt
, &offset_expr
, "ldc1", "T,o(b)", treg
, GP
);
2257 /* Even on a big endian machine $fn comes before $fn+1. We have
2258 to adjust when loading from memory. */
2259 assert (mips_isa
< 2);
2260 macro_build (&icnt
, &offset_expr
, "lwc1", "T,o(b)",
2261 byte_order
== LITTLE_ENDIAN
? treg
: treg
+ 1,
2263 offset_expr
.X_add_number
+= 4;
2264 macro_build (&icnt
, &offset_expr
, "lwc1", "T,o(b)",
2265 byte_order
== LITTLE_ENDIAN
? treg
+ 1 : treg
,
2271 * The MIPS assembler seems to check for X_add_number not
2272 * being double aligned and generating:
2275 * addiu at,at,%lo(foo+1)
2278 * But, the resulting address is the same after relocation so why
2279 * generate the extra instruction?
2281 if (gp_reference (&offset_expr
))
2287 macro_build (&icnt
, &offset_expr
,
2288 mips_isa
< 3 ? "addu" : "daddu",
2289 "d,v,t", AT
, breg
, GP
);
2295 /* FIXME: This won't work for a 64 bit address. */
2296 macro_build_lui (&icnt
, &offset_expr
, AT
);
2298 macro_build (&icnt
, NULL
,
2299 mips_isa
< 3 ? "addu" : "daddu",
2300 "d,v,t", AT
, AT
, breg
);
2304 macro_build (&icnt
, &offset_expr
, "ldc1", "T,o(b)", treg
, tempreg
);
2307 /* Even on a big endian machine $fn comes before $fn+1. We
2308 have to adjust when loading from memory. */
2309 macro_build (&icnt
, &offset_expr
, "lwc1", "T,o(b)",
2310 byte_order
== LITTLE_ENDIAN
? treg
: treg
+ 1,
2312 offset_expr
.X_add_number
+= 4;
2313 macro_build (&icnt
, &offset_expr
, "lwc1", "T,o(b)",
2314 byte_order
== LITTLE_ENDIAN
? treg
+ 1 : treg
,
2327 assert (mips_isa
< 3);
2328 macro_build (&icnt
, &offset_expr
, s
, "t,o(b)", treg
, breg
);
2329 offset_expr
.X_add_number
+= 4;
2330 macro_build (&icnt
, &offset_expr
, s
, "t,o(b)", treg
+ 1, breg
);
2353 if (gp_reference (&offset_expr
))
2361 macro_build (&icnt
, (expressionS
*) NULL
,
2362 mips_isa
< 3 ? "addu" : "daddu",
2363 "d,v,t", tempreg
, breg
, GP
);
2367 /* FIXME: This won't work for a 64 bit address. */
2368 macro_build_lui (&icnt
, &offset_expr
, tempreg
);
2370 macro_build (&icnt
, NULL
,
2371 mips_isa
< 3 ? "addu" : "daddu",
2372 "d,v,t", tempreg
, tempreg
, breg
);
2375 macro_build (&icnt
, &offset_expr
, s2
, "t,o(b)", treg
, tempreg
);
2378 macro_build (&icnt
, &offset_expr
, s
, "t,o(b)", treg
, tempreg
);
2379 offset_expr
.X_add_number
+= 4;
2380 macro_build (&icnt
, &offset_expr
, s
, "t,o(b)", treg
+ 1, tempreg
);
2389 macro_build (&icnt
, NULL
,
2390 dbl
? "dmultu" : "multu",
2392 macro_build (&icnt
, NULL
, "mflo", "d", dreg
);
2398 /* The MIPS assembler some times generates shifts and adds. I'm
2399 not trying to be that fancy. GCC should do this for us
2401 load_register (&icnt
, AT
, &imm_expr
);
2402 macro_build (&icnt
, NULL
,
2403 dbl
? "dmult" : "mult",
2405 macro_build (&icnt
, NULL
, "mflo", "d", dreg
);
2411 mips_emit_delays ();
2413 macro_build (&icnt
, NULL
,
2414 dbl
? "dmult" : "mult",
2416 macro_build (&icnt
, NULL
, "mflo", "d", dreg
);
2417 macro_build (&icnt
, NULL
,
2418 dbl
? "dsra32" : "sra",
2419 "d,w,<", dreg
, dreg
, 31);
2420 macro_build (&icnt
, NULL
, "mfhi", "d", AT
);
2421 expr1
.X_add_number
= 8;
2422 macro_build (&icnt
, &expr1
, "beq", "s,t,p", dreg
, AT
);
2423 macro_build (&icnt
, NULL
, "nop", "", 0);
2424 macro_build (&icnt
, NULL
, "break", "c", 6);
2426 macro_build (&icnt
, NULL
, "mflo", "d", dreg
);
2432 mips_emit_delays ();
2434 macro_build (&icnt
, NULL
,
2435 dbl
? "dmultu" : "multu",
2437 macro_build (&icnt
, NULL
, "mfhi", "d", AT
);
2438 macro_build (&icnt
, NULL
, "mflo", "d", dreg
);
2439 expr1
.X_add_number
= 8;
2440 macro_build (&icnt
, &expr1
, "beq", "s,t,p", AT
, 0);
2441 macro_build (&icnt
, NULL
, "nop", "", 0);
2442 macro_build (&icnt
, NULL
, "break", "c", 6);
2447 macro_build (&icnt
, NULL
, "subu", "d,v,t", AT
, 0, treg
);
2448 macro_build (&icnt
, NULL
, "srlv", "d,t,s", AT
, sreg
, AT
);
2449 macro_build (&icnt
, NULL
, "sllv", "d,t,s", dreg
, sreg
, treg
);
2450 macro_build (&icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
2454 macro_build (&icnt
, NULL
, "sll", "d,w,<", AT
, sreg
,
2455 imm_expr
.X_add_number
& 0x1f);
2456 macro_build (&icnt
, NULL
, "srl", "d,w,<", dreg
, sreg
,
2457 (0 - imm_expr
.X_add_number
) & 0x1f);
2458 macro_build (&icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
2462 macro_build (&icnt
, NULL
, "subu", "d,v,t", AT
, 0, treg
);
2463 macro_build (&icnt
, NULL
, "sllv", "d,t,s", AT
, sreg
, AT
);
2464 macro_build (&icnt
, NULL
, "srlv", "d,t,s", dreg
, sreg
, treg
);
2465 macro_build (&icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
2469 macro_build (&icnt
, NULL
, "srl", "d,w,<", AT
, sreg
,
2470 imm_expr
.X_add_number
& 0x1f);
2471 macro_build (&icnt
, NULL
, "sll", "d,w,<", dreg
, sreg
,
2472 (0 - imm_expr
.X_add_number
) & 0x1f);
2473 macro_build (&icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
2477 assert (mips_isa
< 2);
2478 /* Even on a big endian machine $fn comes before $fn+1. We have
2479 to adjust when storing to memory. */
2480 macro_build (&icnt
, &offset_expr
, "swc1", "T,o(b)",
2481 byte_order
== LITTLE_ENDIAN
? treg
: treg
+ 1,
2483 offset_expr
.X_add_number
+= 4;
2484 macro_build (&icnt
, &offset_expr
, "swc1", "T,o(b)",
2485 byte_order
== LITTLE_ENDIAN
? treg
+ 1 : treg
,
2490 if (gp_reference (&offset_expr
))
2496 macro_build (&icnt
, (expressionS
*) NULL
,
2497 mips_isa
< 3 ? "addu" : "daddu",
2498 "d,v,t", AT
, breg
, GP
);
2504 /* FIXME: This won't work for a 64 bit address. */
2505 macro_build_lui (&icnt
, &offset_expr
, AT
);
2507 macro_build (&icnt
, NULL
,
2508 mips_isa
< 3 ? "addu" : "daddu",
2509 "d,v,t", AT
, AT
, breg
);
2513 macro_build (&icnt
, &offset_expr
, "sdc1", "T,o(b)", treg
, tempreg
);
2516 /* Even on a big endian machine $fn comes before $fn+1. We
2517 have to adjust when storing to memory. */
2518 macro_build (&icnt
, &offset_expr
, "swc1", "T,o(b)",
2519 byte_order
== LITTLE_ENDIAN
? treg
: treg
+ 1,
2521 offset_expr
.X_add_number
+= 4;
2522 macro_build (&icnt
, &offset_expr
, "swc1", "T,o(b)",
2523 byte_order
== LITTLE_ENDIAN
? treg
+ 1 : treg
,
2532 macro_build (&icnt
, &expr1
, "sltiu", "t,r,j", dreg
, treg
);
2534 macro_build (&icnt
, &expr1
, "sltiu", "t,r,j", dreg
, sreg
);
2537 macro_build (&icnt
, NULL
, "xor", "d,v,t", dreg
, sreg
, treg
);
2538 macro_build (&icnt
, &expr1
, "sltiu", "t,r,j", dreg
, dreg
);
2543 if (imm_expr
.X_add_number
== 0)
2545 macro_build (&icnt
, &expr1
, "sltiu", "t,r,j", dreg
, sreg
);
2550 as_warn ("Instruction %s: result is always false",
2552 macro_build (&icnt
, NULL
, "move", "d,s", dreg
, 0);
2555 if (imm_expr
.X_add_number
>= 0 && imm_expr
.X_add_number
< 0x10000)
2557 macro_build (&icnt
, &imm_expr
, "xori", "t,r,i", dreg
, sreg
);
2560 else if (imm_expr
.X_add_number
> -0x8000 && imm_expr
.X_add_number
< 0)
2562 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
2563 macro_build (&icnt
, &imm_expr
,
2564 mips_isa
< 3 ? "addiu" : "daddiu",
2565 "t,r,j", dreg
, sreg
);
2570 load_register (&icnt
, AT
, &imm_expr
);
2571 macro_build (&icnt
, NULL
, "xor", "d,v,t", dreg
, sreg
, AT
);
2574 macro_build (&icnt
, &expr1
, "sltiu", "t,r,j", dreg
, dreg
);
2579 case M_SGE
: /* sreg >= treg <==> not (sreg < treg) */
2585 macro_build (&icnt
, NULL
, s
, "d,v,t", dreg
, sreg
, treg
);
2586 macro_build (&icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
);
2589 case M_SGE_I
: /* sreg >= I <==> not (sreg < I) */
2591 if (imm_expr
.X_add_number
>= -0x8000 && imm_expr
.X_add_number
< 0x8000)
2593 macro_build (&icnt
, &expr1
,
2594 mask
== M_SGE_I
? "slti" : "sltiu",
2595 "t,r,j", dreg
, sreg
);
2600 load_register (&icnt
, AT
, &imm_expr
);
2601 macro_build (&icnt
, NULL
,
2602 mask
== M_SGE_I
? "slt" : "sltu",
2603 "d,v,t", dreg
, sreg
, AT
);
2606 macro_build (&icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
);
2611 case M_SGT
: /* sreg > treg <==> treg < sreg */
2617 macro_build (&icnt
, NULL
, s
, "d,v,t", dreg
, treg
, sreg
);
2620 case M_SGT_I
: /* sreg > I <==> I < sreg */
2626 load_register (&icnt
, AT
, &imm_expr
);
2627 macro_build (&icnt
, NULL
, s
, "d,v,t", dreg
, AT
, sreg
);
2630 case M_SLE
: /* sreg <= treg <==> treg >= sreg <==> not (treg < sreg) */
2636 macro_build (&icnt
, NULL
, s
, "d,v,t", dreg
, treg
, sreg
);
2637 macro_build (&icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
);
2640 case M_SLE_I
: /* sreg <= I <==> I >= sreg <==> not (I < sreg) */
2646 load_register (&icnt
, AT
, &imm_expr
);
2647 macro_build (&icnt
, NULL
, s
, "d,v,t", dreg
, AT
, sreg
);
2648 macro_build (&icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
);
2652 if (imm_expr
.X_add_number
>= -0x8000 && imm_expr
.X_add_number
< 0x8000)
2654 macro_build (&icnt
, &imm_expr
, "slti", "t,r,j", dreg
, sreg
);
2657 load_register (&icnt
, AT
, &imm_expr
);
2658 macro_build (&icnt
, NULL
, "slt", "d,v,t", dreg
, sreg
, AT
);
2662 if (imm_expr
.X_add_number
>= -0x8000 && imm_expr
.X_add_number
< 0x8000)
2664 macro_build (&icnt
, &imm_expr
, "sltiu", "t,r,j", dreg
, sreg
);
2667 load_register (&icnt
, AT
, &imm_expr
);
2668 macro_build (&icnt
, NULL
, "sltu", "d,v,t", dreg
, sreg
, AT
);
2673 macro_build (&icnt
, NULL
, "sltu", "d,v,t", dreg
, 0, treg
);
2675 macro_build (&icnt
, NULL
, "sltu", "d,v,t", dreg
, 0, sreg
);
2678 macro_build (&icnt
, NULL
, "xor", "d,v,t", dreg
, sreg
, treg
);
2679 macro_build (&icnt
, NULL
, "sltu", "d,v,t", dreg
, 0, dreg
);
2684 if (imm_expr
.X_add_number
== 0)
2686 macro_build (&icnt
, NULL
, "sltu", "d,v,t", dreg
, 0, sreg
);
2691 as_warn ("Instruction %s: result is always true",
2693 macro_build (&icnt
, &expr1
,
2694 mips_isa
< 3 ? "addiu" : "daddiu",
2698 if (imm_expr
.X_add_number
>= 0 && imm_expr
.X_add_number
< 0x10000)
2700 macro_build (&icnt
, &imm_expr
, "xori", "t,r,i", dreg
, sreg
);
2703 else if (imm_expr
.X_add_number
> -0x8000 && imm_expr
.X_add_number
< 0)
2705 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
2706 macro_build (&icnt
, &imm_expr
,
2707 mips_isa
< 3 ? "addiu" : "daddiu",
2708 "t,r,j", dreg
, sreg
);
2713 load_register (&icnt
, AT
, &imm_expr
);
2714 macro_build (&icnt
, NULL
, "xor", "d,v,t", dreg
, sreg
, AT
);
2717 macro_build (&icnt
, NULL
, "sltu", "d,v,t", dreg
, 0, dreg
);
2725 if (imm_expr
.X_add_number
> -0x8000 && imm_expr
.X_add_number
<= 0x8000)
2727 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
2728 macro_build (&icnt
, &imm_expr
,
2729 dbl
? "daddi" : "addi",
2730 "t,r,j", dreg
, sreg
);
2733 load_register (&icnt
, AT
, &imm_expr
);
2734 macro_build (&icnt
, NULL
,
2735 dbl
? "dsub" : "sub",
2736 "d,v,t", dreg
, sreg
, AT
);
2742 if (imm_expr
.X_add_number
> -0x8000 && imm_expr
.X_add_number
<= 0x8000)
2744 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
2745 macro_build (&icnt
, &imm_expr
,
2746 dbl
? "daddiu" : "addiu",
2747 "t,r,j", dreg
, sreg
);
2750 load_register (&icnt
, AT
, &imm_expr
);
2751 macro_build (&icnt
, NULL
,
2752 dbl
? "dsubu" : "subu",
2753 "d,v,t", dreg
, sreg
, AT
);
2774 load_register (&icnt
, AT
, &imm_expr
);
2775 macro_build (&icnt
, NULL
, s
, "s,t", sreg
, AT
);
2780 assert (mips_isa
< 2);
2781 sreg
= (ip
->insn_opcode
>> 11) & 0x1f; /* floating reg */
2782 dreg
= (ip
->insn_opcode
>> 06) & 0x1f; /* floating reg */
2785 * Is the double cfc1 instruction a bug in the mips assembler;
2786 * or is there a reason for it?
2788 mips_emit_delays ();
2790 macro_build (&icnt
, NULL
, "cfc1", "t,G", treg
, 31);
2791 macro_build (&icnt
, NULL
, "cfc1", "t,G", treg
, 31);
2792 macro_build (&icnt
, NULL
, "nop", "");
2793 expr1
.X_add_number
= 3;
2794 macro_build (&icnt
, &expr1
, "ori", "t,r,i", AT
, treg
);
2795 expr1
.X_add_number
= 2;
2796 macro_build (&icnt
, &expr1
, "xori", "t,r,i", AT
, AT
);
2797 macro_build (&icnt
, NULL
, "ctc1", "t,G", AT
, 31);
2798 macro_build (&icnt
, NULL
, "nop", "");
2799 macro_build (&icnt
, NULL
,
2800 mask
== M_TRUNCWD
? "cvt.w.d" : "cvt.w.s", "D,S", dreg
, sreg
);
2801 macro_build (&icnt
, NULL
, "ctc1", "t,G", treg
, 31);
2802 macro_build (&icnt
, NULL
, "nop", "");
2812 /* avoid load delay */
2813 offset_expr
.X_add_number
+= 1;
2814 macro_build (&icnt
, &offset_expr
, s
, "t,o(b)", treg
, breg
);
2815 offset_expr
.X_add_number
-= 1;
2816 macro_build (&icnt
, &offset_expr
, "lbu", "t,o(b)", AT
, breg
);
2817 macro_build (&icnt
, NULL
, "sll", "d,w,<", treg
, treg
, 8);
2818 macro_build (&icnt
, NULL
, "or", "d,v,t", treg
, treg
, AT
);
2822 /* does this work on a big endian machine? */
2823 offset_expr
.X_add_number
+= 3;
2824 macro_build (&icnt
, &offset_expr
, "lwl", "t,o(b)", treg
, breg
);
2825 offset_expr
.X_add_number
-= 3;
2826 macro_build (&icnt
, &offset_expr
, "lwr", "t,o(b)", treg
, breg
);
2832 if (offset_expr
.X_op
== O_constant
)
2833 load_register (&icnt
, AT
, &offset_expr
);
2834 else if (gp_reference (&offset_expr
))
2835 macro_build (&icnt
, &offset_expr
,
2836 mips_isa
< 3 ? "addiu" : "daddiu",
2840 /* FIXME: This won't work for a 64 bit address. */
2841 macro_build_lui (&icnt
, &offset_expr
, AT
);
2842 macro_build (&icnt
, &offset_expr
,
2843 mips_isa
< 3 ? "addiu" : "daddiu",
2846 if (mask
== M_ULW_A
)
2848 expr1
.X_add_number
= 3;
2849 macro_build (&icnt
, &expr1
, "lwl", "t,o(b)", treg
, AT
);
2850 imm_expr
.X_add_number
= 0;
2851 macro_build (&icnt
, &expr1
, "lwr", "t,o(b)", treg
, AT
);
2855 macro_build (&icnt
, &expr1
,
2856 mask
== M_ULH_A
? "lb" : "lbu", "t,o(b)", treg
, AT
);
2857 imm_expr
.X_add_number
= 0;
2858 macro_build (&icnt
, &expr1
, "lbu", "t,o(b)", AT
, AT
);
2859 macro_build (&icnt
, NULL
, "sll", "d,w,<", treg
, treg
, 8);
2860 macro_build (&icnt
, NULL
, "or", "d,v,t", treg
, treg
, AT
);
2865 macro_build (&icnt
, &offset_expr
, "sb", "t,o(b)", treg
, breg
);
2866 macro_build (&icnt
, NULL
, "srl", "d,w,<", AT
, treg
, 8);
2867 offset_expr
.X_add_number
+= 1;
2868 macro_build (&icnt
, &offset_expr
, "sb", "t,o(b)", AT
, breg
);
2872 offset_expr
.X_add_number
+= 3;
2873 macro_build (&icnt
, &offset_expr
, "swl", "t,o(b)", treg
, breg
);
2874 offset_expr
.X_add_number
-= 3;
2875 macro_build (&icnt
, &offset_expr
, "swr", "t,o(b)", treg
, breg
);
2880 if (offset_expr
.X_op
== O_constant
)
2881 load_register (&icnt
, AT
, &offset_expr
);
2882 else if (gp_reference (&offset_expr
))
2883 macro_build (&icnt
, &offset_expr
,
2884 mips_isa
< 3 ? "addiu" : "daddiu",
2888 /* FIXME: This won't work for a 64 bit address. */
2889 macro_build_lui (&icnt
, &offset_expr
, AT
);
2890 macro_build (&icnt
, &offset_expr
,
2891 mips_isa
< 3 ? "addiu" : "daddiu",
2894 if (mask
== M_USW_A
)
2896 expr1
.X_add_number
= 3;
2897 macro_build (&icnt
, &expr1
, "swl", "t,o(b)", treg
, AT
);
2898 expr1
.X_add_number
= 0;
2899 macro_build (&icnt
, &expr1
, "swr", "t,o(b)", treg
, AT
);
2903 expr1
.X_add_number
= 0;
2904 macro_build (&icnt
, &expr1
, "sb", "t,o(b)", treg
, AT
);
2905 macro_build (&icnt
, NULL
, "srl", "d,w,<", treg
, treg
, 8);
2906 expr1
.X_add_number
= 1;
2907 macro_build (&icnt
, &expr1
, "sb", "t,o(b)", treg
, AT
);
2908 expr1
.X_add_number
= 0;
2909 macro_build (&icnt
, &expr1
, "lbu", "t,o(b)", AT
, AT
);
2910 macro_build (&icnt
, NULL
, "sll", "d,w,<", treg
, treg
, 8);
2911 macro_build (&icnt
, NULL
, "or", "d,v,t", treg
, treg
, AT
);
2916 as_bad ("Macro %s not implemented yet", ip
->insn_mo
->name
);
2920 as_warn ("Macro used $at after \".set noat\"");
2925 This routine assembles an instruction into its binary format. As a side
2926 effect it sets one of the global variables imm_reloc or offset_reloc to the
2927 type of relocation to do if one of the operands is an address expression.
2932 struct mips_cl_insn
*ip
;
2937 struct mips_opcode
*insn
;
2940 unsigned int lastregno
= 0;
2945 for (s
= str
; islower (*s
) || (*s
>= '0' && *s
<= '3') || *s
== '.'; ++s
)
2957 as_warn ("Unknown opcode: `%s'", str
);
2960 if ((insn
= (struct mips_opcode
*) hash_find (op_hash
, str
)) == NULL
)
2962 as_warn ("`%s' not in hash table.", str
);
2963 insn_error
= "ERROR: Unrecognized opcode";
2971 assert (strcmp (insn
->name
, str
) == 0);
2973 if (insn
->pinfo
== INSN_MACRO
)
2974 insn_isa
= insn
->match
;
2975 else if (insn
->pinfo
& INSN_ISA2
)
2977 else if (insn
->pinfo
& INSN_ISA3
)
2982 if (insn_isa
> mips_isa
)
2984 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
]
2985 && strcmp (insn
->name
, insn
[1].name
) == 0)
2990 insn_error
= "ERROR: instruction not supported on this processor";
2995 ip
->insn_opcode
= insn
->match
;
2996 for (args
= insn
->args
;; ++args
)
3002 case '\0': /* end of args */
3015 ip
->insn_opcode
|= lastregno
<< 21;
3020 ip
->insn_opcode
|= lastregno
<< 16;
3024 ip
->insn_opcode
|= lastregno
<< 11;
3030 /* handle optional base register.
3031 Either the base register is omitted or
3032 we must have a left paren. */
3033 /* this is dependent on the next operand specifier
3034 is a 'b' for base register */
3035 assert (args
[1] == 'b');
3039 case ')': /* these must match exactly */
3044 case '<': /* must be at least one digit */
3046 * According to the manual, if the shift amount is greater
3047 * than 31 or less than 0 the the shift amount should be
3048 * mod 32. In reality the mips assembler issues an error.
3049 * We issue a warning and do the mod.
3051 my_getExpression (&imm_expr
, s
);
3052 check_absolute_expr (ip
, &imm_expr
);
3053 if ((unsigned long) imm_expr
.X_add_number
> 31)
3055 as_warn ("Improper shift amount (%ld)",
3056 (long) imm_expr
.X_add_number
);
3057 imm_expr
.X_add_number
= imm_expr
.X_add_number
% 32;
3059 ip
->insn_opcode
|= imm_expr
.X_add_number
<< 6;
3060 imm_expr
.X_op
= O_absent
;
3064 case '>': /* shift amount minus 32 */
3065 my_getExpression (&imm_expr
, s
);
3066 check_absolute_expr (ip
, &imm_expr
);
3067 if ((unsigned long) imm_expr
.X_add_number
< 32
3068 || (unsigned long) imm_expr
.X_add_number
> 63)
3070 ip
->insn_opcode
|= (imm_expr
.X_add_number
- 32) << 6;
3071 imm_expr
.X_op
= O_absent
;
3075 case 'c': /* break code */
3076 my_getExpression (&imm_expr
, s
);
3077 check_absolute_expr (ip
, &imm_expr
);
3078 if ((unsigned) imm_expr
.X_add_number
> 1023)
3079 as_warn ("Illegal break code (%ld)",
3080 (long) imm_expr
.X_add_number
);
3081 ip
->insn_opcode
|= imm_expr
.X_add_number
<< 16;
3082 imm_expr
.X_op
= O_absent
;
3086 case 'B': /* syscall code */
3087 my_getExpression (&imm_expr
, s
);
3088 check_absolute_expr (ip
, &imm_expr
);
3089 if ((unsigned) imm_expr
.X_add_number
> 0xfffff)
3090 as_warn ("Illegal syscall code (%ld)",
3091 (long) imm_expr
.X_add_number
);
3092 ip
->insn_opcode
|= imm_expr
.X_add_number
<< 6;
3093 imm_expr
.X_op
= O_absent
;
3097 case 'C': /* Coprocessor code */
3098 my_getExpression (&imm_expr
, s
);
3099 check_absolute_expr (ip
, &imm_expr
);
3100 if ((unsigned long) imm_expr
.X_add_number
>= (1<<25))
3102 as_warn ("Coproccesor code > 25 bits (%ld)",
3103 (long) imm_expr
.X_add_number
);
3104 imm_expr
.X_add_number
&= ((1<<25) - 1);
3106 ip
->insn_opcode
|= imm_expr
.X_add_number
;
3107 imm_expr
.X_op
= O_absent
;
3111 case 'b': /* base register */
3112 case 'd': /* destination register */
3113 case 's': /* source register */
3114 case 't': /* target register */
3115 case 'r': /* both target and source */
3116 case 'v': /* both dest and source */
3117 case 'w': /* both dest and target */
3118 case 'E': /* coprocessor target register */
3119 case 'G': /* coprocessor destination register */
3120 case 'x': /* ignore register name */
3121 case 'z': /* must be zero register */
3135 while (isdigit (*s
));
3137 as_bad ("Invalid register number (%d)", regno
);
3139 else if (*args
!= 'E' && *args
!= 'G')
3141 if (s
[1] == 'f' && s
[2] == 'p')
3146 else if (s
[1] == 's' && s
[2] == 'p')
3151 else if (s
[1] == 'g' && s
[2] == 'p')
3156 else if (s
[1] == 'a' && s
[2] == 't')
3163 if (regno
== AT
&& ! mips_noat
)
3164 as_warn ("Used $at without \".set noat\"");
3171 if (c
== 'r' || c
== 'v' || c
== 'w')
3178 /* 'z' only matches $0. */
3179 if (c
== 'z' && regno
!= 0)
3187 ip
->insn_opcode
|= regno
<< 21;
3191 ip
->insn_opcode
|= regno
<< 11;
3196 ip
->insn_opcode
|= regno
<< 16;
3199 /* This case exists because on the r3000 trunc
3200 expands into a macro which requires a gp
3201 register. On the r6000 or r4000 it is
3202 assembled into a single instruction which
3203 ignores the register. Thus the insn version
3204 is MIPS_ISA2 and uses 'x', and the macro
3205 version is MIPS_ISA1 and uses 't'. */
3208 /* This case is for the div instruction, which
3209 acts differently if the destination argument
3210 is $0. This only matches $0, and is checked
3211 outside the switch. */
3222 ip
->insn_opcode
|= lastregno
<< 21;
3225 ip
->insn_opcode
|= lastregno
<< 16;
3230 case 'D': /* floating point destination register */
3231 case 'S': /* floating point source register */
3232 case 'T': /* floating point target register */
3236 if (s
[0] == '$' && s
[1] == 'f' && isdigit (s
[2]))
3246 while (isdigit (*s
));
3249 as_bad ("Invalid float register number (%d)", regno
);
3252 !(strcmp (str
, "mtc1") == 0 ||
3253 strcmp (str
, "mfc1") == 0 ||
3254 strcmp (str
, "lwc1") == 0 ||
3255 strcmp (str
, "swc1") == 0))
3256 as_warn ("Float register should be even, was %d",
3264 if (c
== 'V' || c
== 'W')
3274 ip
->insn_opcode
|= regno
<< 6;
3278 ip
->insn_opcode
|= regno
<< 11;
3282 ip
->insn_opcode
|= regno
<< 16;
3290 ip
->insn_opcode
|= lastregno
<< 11;
3293 ip
->insn_opcode
|= lastregno
<< 16;
3299 my_getExpression (&imm_expr
, s
);
3300 check_absolute_expr (ip
, &imm_expr
);
3305 my_getExpression (&offset_expr
, s
);
3306 imm_reloc
= BFD_RELOC_32
;
3318 unsigned char temp
[8];
3320 unsigned int length
;
3325 /* These only appear as the last operand in an
3326 instruction, and every instruction that accepts
3327 them in any variant accepts them in all variants.
3328 This means we don't have to worry about backing out
3329 any changes if the instruction does not match.
3331 The difference between them is the size of the
3332 floating point constant and where it goes. For 'F'
3333 and 'L' the constant is 64 bits; for 'f' and 'l' it
3334 is 32 bits. Where the constant is placed is based
3335 on how the MIPS assembler does things:
3338 f -- immediate value
3342 f64
= *args
== 'F' || *args
== 'L';
3344 save_in
= input_line_pointer
;
3345 input_line_pointer
= s
;
3346 err
= md_atof (f64
? 'd' : 'f', (char *) temp
, &len
);
3348 s
= input_line_pointer
;
3349 input_line_pointer
= save_in
;
3350 if (err
!= NULL
&& *err
!= '\0')
3352 as_bad ("Bad floating point constant: %s", err
);
3353 memset (temp
, '\0', sizeof temp
);
3354 length
= f64
? 8 : 4;
3357 assert (length
== (f64
? 8 : 4));
3361 imm_expr
.X_op
= O_constant
;
3362 if (byte_order
== LITTLE_ENDIAN
)
3363 imm_expr
.X_add_number
=
3364 (((((((int) temp
[3] << 8)
3369 imm_expr
.X_add_number
=
3370 (((((((int) temp
[0] << 8)
3377 /* Switch to the right section. */
3379 subseg
= now_subseg
;
3383 subseg_new (".rdata", (subsegT
) 0);
3386 subseg_new (".lit8", (subsegT
) 0);
3389 subseg_new (".lit4", (subsegT
) 0);
3393 as_bad ("Can't use floating point insn in this section");
3395 /* Set the argument to the current address in the
3397 offset_expr
.X_op
= O_symbol
;
3398 offset_expr
.X_add_symbol
=
3399 symbol_new ("L0\001", now_seg
,
3400 (valueT
) frag_now_fix (), frag_now
);
3401 offset_expr
.X_add_number
= 0;
3403 /* Put the floating point number into the section. */
3404 p
= frag_more ((int) length
);
3405 memcpy (p
, temp
, length
);
3407 /* Switch back to the original section. */
3408 subseg_set (seg
, subseg
);
3413 case 'i': /* 16 bit unsigned immediate */
3414 case 'j': /* 16 bit signed immediate */
3415 imm_reloc
= BFD_RELOC_LO16
;
3416 c
= my_getSmallExpression (&imm_expr
, s
);
3421 if (imm_expr
.X_op
== O_constant
)
3422 imm_expr
.X_add_number
=
3423 (imm_expr
.X_add_number
>> 16) & 0xffff;
3425 imm_reloc
= BFD_RELOC_HI16_S
;
3427 imm_reloc
= BFD_RELOC_HI16
;
3431 check_absolute_expr (ip
, &imm_expr
);
3434 if (imm_expr
.X_add_number
< 0
3435 || imm_expr
.X_add_number
>= 0x10000)
3437 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
3438 !strcmp (insn
->name
, insn
[1].name
))
3440 as_bad ("16 bit expression not in range 0..65535");
3445 if (imm_expr
.X_add_number
< -0x8000 ||
3446 imm_expr
.X_add_number
>= 0x8000)
3448 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
3449 !strcmp (insn
->name
, insn
[1].name
))
3451 as_bad ("16 bit expression not in range -32768..32767");
3457 case 'o': /* 16 bit offset */
3458 c
= my_getSmallExpression (&offset_expr
, s
);
3460 * If this value won't fit into a 16 bit offset, then
3461 * go find a macro that will generate the 32 bit offset
3464 if (offset_expr
.X_op
!= O_constant
3465 || offset_expr
.X_add_number
>= 0x8000
3466 || offset_expr
.X_add_number
< -0x8000)
3469 offset_reloc
= BFD_RELOC_LO16
;
3470 if (c
== 'h' || c
== 'H')
3472 assert (offset_expr
.X_op
== O_constant
);
3473 offset_expr
.X_add_number
=
3474 (offset_expr
.X_add_number
>> 16) & 0xffff;
3479 case 'p': /* pc relative offset */
3480 offset_reloc
= BFD_RELOC_16_PCREL_S2
;
3481 my_getExpression (&offset_expr
, s
);
3485 case 'u': /* upper 16 bits */
3486 c
= my_getSmallExpression (&imm_expr
, s
);
3487 if (imm_expr
.X_op
!= O_constant
3488 || imm_expr
.X_add_number
< 0
3489 || imm_expr
.X_add_number
>= 0x10000)
3490 as_bad ("lui expression not in range 0..65535");
3491 imm_reloc
= BFD_RELOC_LO16
;
3496 if (imm_expr
.X_op
== O_constant
)
3497 imm_expr
.X_add_number
=
3498 (imm_expr
.X_add_number
>> 16) & 0xffff;
3500 imm_reloc
= BFD_RELOC_HI16_S
;
3502 imm_reloc
= BFD_RELOC_HI16
;
3508 case 'a': /* 26 bit address */
3509 my_getExpression (&offset_expr
, s
);
3511 offset_reloc
= BFD_RELOC_MIPS_JMP
;
3515 fprintf (stderr
, "bad char = '%c'\n", *args
);
3520 /* Args don't match. */
3521 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
3522 !strcmp (insn
->name
, insn
[1].name
))
3528 insn_error
= "ERROR: Illegal operands";
3537 my_getSmallExpression (ep
, str
)
3548 ((str
[1] == 'h' && str
[2] == 'i')
3549 || (str
[1] == 'H' && str
[2] == 'I')
3550 || (str
[1] == 'l' && str
[2] == 'o'))
3562 * A small expression may be followed by a base register.
3563 * Scan to the end of this operand, and then back over a possible
3564 * base register. Then scan the small expression up to that
3565 * point. (Based on code in sparc.c...)
3567 for (sp
= str
; *sp
&& *sp
!= ','; sp
++)
3569 if (sp
- 4 >= str
&& sp
[-1] == RP
)
3571 if (isdigit (sp
[-2]))
3573 for (sp
-= 3; sp
>= str
&& isdigit (*sp
); sp
--)
3575 if (*sp
== '$' && sp
> str
&& sp
[-1] == LP
)
3581 else if (sp
- 5 >= str
3584 && ((sp
[-3] == 'f' && sp
[-2] == 'p')
3585 || (sp
[-3] == 's' && sp
[-2] == 'p')
3586 || (sp
[-3] == 'g' && sp
[-2] == 'p')
3587 || (sp
[-3] == 'a' && sp
[-2] == 't')))
3593 /* no expression means zero offset */
3596 /* %xx(reg) is an error */
3597 ep
->X_op
= O_absent
;
3602 ep
->X_op
= O_constant
;
3605 ep
->X_add_symbol
= NULL
;
3606 ep
->X_op_symbol
= NULL
;
3607 ep
->X_add_number
= 0;
3612 my_getExpression (ep
, str
);
3619 my_getExpression (ep
, str
);
3620 return c
; /* => %hi or %lo encountered */
3624 my_getExpression (ep
, str
)
3630 save_in
= input_line_pointer
;
3631 input_line_pointer
= str
;
3633 expr_end
= input_line_pointer
;
3634 input_line_pointer
= save_in
;
3637 /* Turn a string in input_line_pointer into a floating point constant
3638 of type type, and store the appropriate bytes in *litP. The number
3639 of LITTLENUMS emitted is stored in *sizeP . An error message is
3640 returned, or NULL on OK. */
3643 md_atof (type
, litP
, sizeP
)
3649 LITTLENUM_TYPE words
[4];
3665 return "bad call to md_atof";
3668 t
= atof_ieee (input_line_pointer
, type
, words
);
3670 input_line_pointer
= t
;
3674 if (byte_order
== LITTLE_ENDIAN
)
3676 for (i
= prec
- 1; i
>= 0; i
--)
3678 md_number_to_chars (litP
, (valueT
) words
[i
], 2);
3684 for (i
= 0; i
< prec
; i
++)
3686 md_number_to_chars (litP
, (valueT
) words
[i
], 2);
3695 md_number_to_chars (buf
, val
, n
)
3743 md_number_to_chars (buf
, hi
, 4);
3768 md_parse_option (argP
, cntP
, vecP
)
3773 /* Accept -nocpp but ignore it. */
3774 if (strcmp (*argP
, "nocpp") == 0)
3780 if (strcmp (*argP
, "EL") == 0
3781 || strcmp (*argP
, "EB") == 0)
3783 /* FIXME: This breaks -L -EL. */
3791 if ((*argP
)[1] == '0')
3800 if ((*argP
)[1] == '\0' || (*argP
)[1] == '2')
3805 if (strncmp (*argP
, "mips", 4) == 0)
3807 mips_isa
= atol (*argP
+ 4);
3810 else if (mips_isa
< 1 || mips_isa
> 3)
3812 as_bad ("-mips%d not supported", mips_isa
);
3819 if (strncmp (*argP
, "mcpu=", 5) == 0)
3823 /* Identify the processor type */
3825 if (strcmp (p
, "default") == 0
3826 || strcmp (p
, "DEFAULT") == 0)
3830 if (*p
== 'r' || *p
== 'R')
3837 if (strcmp (p
, "2000") == 0
3838 || strcmp (p
, "2k") == 0
3839 || strcmp (p
, "2K") == 0)
3844 if (strcmp (p
, "3000") == 0
3845 || strcmp (p
, "3k") == 0
3846 || strcmp (p
, "3K") == 0)
3851 if (strcmp (p
, "4000") == 0
3852 || strcmp (p
, "4k") == 0
3853 || strcmp (p
, "4K") == 0)
3858 if (strcmp (p
, "6000") == 0
3859 || strcmp (p
, "6k") == 0
3860 || strcmp (p
, "6K") == 0)
3867 as_bad ("bad value (%s) for -mcpu= switch", *argP
+ 5);
3880 if ((*argP
)[1] != '\0')
3881 g_switch_value
= atoi (*argP
+ 1);
3884 **vecP
= (char *) NULL
;
3887 g_switch_value
= atoi (**vecP
);
3890 as_warn ("Number expected after -G");
3896 return 1; /* pretend you parsed the character */
3900 md_pcrel_from (fixP
)
3903 /* return the address of the delay slot */
3904 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
3907 /* This is called by emit_expr via TC_CONS_FIX_NEW when creating a
3908 reloc for a cons. We could use the definition there, except that
3909 we want to handle 64 bit relocs specially. */
3912 cons_fix_new_mips (frag
, where
, nbytes
, exp
)
3915 unsigned int nbytes
;
3918 /* If we are assembling in 32 bit mode, turn an 8 byte reloc into a
3920 FIXME: There is no way to select anything but 32 bit mode right
3924 if (byte_order
== BIG_ENDIAN
)
3929 if (nbytes
!= 2 && nbytes
!= 4)
3930 as_bad ("Unsupported reloc size %d", nbytes
);
3932 fix_new_exp (frag_now
, where
, (int) nbytes
, exp
, 0,
3933 nbytes
== 2 ? BFD_RELOC_16
: BFD_RELOC_32
);
3937 md_apply_fix (fixP
, valueP
)
3944 assert (fixP
->fx_size
== 4);
3947 fixP
->fx_addnumber
= value
; /* Remember value for tc_gen_reloc */
3949 switch (fixP
->fx_r_type
)
3952 case BFD_RELOC_MIPS_JMP
:
3953 case BFD_RELOC_HI16
:
3954 case BFD_RELOC_HI16_S
:
3955 case BFD_RELOC_LO16
:
3956 case BFD_RELOC_MIPS_GPREL
:
3957 /* Nothing needed to do. The value comes from the reloc entry */
3960 case BFD_RELOC_16_PCREL_S2
:
3962 * We need to save the bits in the instruction since fixup_segment()
3963 * might be deleting the relocation entry (i.e., a branch within
3964 * the current segment).
3967 as_warn ("Branch to odd address (%lx)", value
);
3969 if ((value
& ~0xFFFF) && (value
& ~0xFFFF) != (-1 & ~0xFFFF))
3970 as_bad ("Relocation overflow");
3972 /* update old instruction data */
3973 buf
= (unsigned char *) (fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
);
3977 insn
= (buf
[3] << 24) | (buf
[2] << 16) | (buf
[1] << 8) | buf
[0];
3981 insn
= (buf
[0] << 24) | (buf
[1] << 16) | (buf
[2] << 8) | buf
[3];
3988 insn
|= value
& 0xFFFF;
3989 md_number_to_chars ((char *) buf
, (valueT
) insn
, 4);
4003 const struct mips_opcode
*p
;
4004 int treg
, sreg
, dreg
, shamt
;
4009 for (i
= 0; i
< NUMOPCODES
; ++i
)
4011 p
= &mips_opcodes
[i
];
4012 if (((oc
& p
->mask
) == p
->match
) && (p
->pinfo
!= INSN_MACRO
))
4014 printf ("%08lx %s\t", oc
, p
->name
);
4015 treg
= (oc
>> 16) & 0x1f;
4016 sreg
= (oc
>> 21) & 0x1f;
4017 dreg
= (oc
>> 11) & 0x1f;
4018 shamt
= (oc
>> 6) & 0x1f;
4020 for (args
= p
->args
;; ++args
)
4031 printf ("%c", *args
);
4035 assert (treg
== sreg
);
4036 printf ("$%d,$%d", treg
, sreg
);
4041 printf ("$%d", dreg
);
4046 printf ("$%d", treg
);
4051 printf ("$%d", sreg
);
4055 printf ("0x%08lx", oc
& 0x1ffffff);
4067 printf ("$%d", shamt
);
4078 printf ("%08lx UNDEFINED\n", oc
);
4089 name
= input_line_pointer
;
4090 c
= get_symbol_end ();
4091 p
= (symbolS
*) symbol_find_or_make (name
);
4092 *input_line_pointer
= c
;
4096 /* Align the current frag to a given power of two. The MIPS assembler
4097 also automatically adjusts any preceding label. */
4100 mips_align (to
, fill
)
4104 mips_emit_delays ();
4105 frag_align (to
, fill
);
4106 record_alignment (now_seg
, to
);
4107 if (insn_label
!= NULL
)
4109 assert (S_GET_SEGMENT (insn_label
) == now_seg
);
4110 insn_label
->sy_frag
= frag_now
;
4111 S_SET_VALUE (insn_label
, (valueT
) frag_now_fix ());
4116 /* Align to a given power of two. .align 0 turns off the automatic
4117 alignment used by the data creating pseudo-ops. */
4124 register long temp_fill
;
4125 long max_alignment
= 15;
4129 o Note that the assembler pulls down any immediately preceeding label
4130 to the aligned address.
4131 o It's not documented but auto alignment is reinstated by
4132 a .align pseudo instruction.
4133 o Note also that after auto alignment is turned off the mips assembler
4134 issues an error on attempt to assemble an improperly aligned data item.
4139 temp
= get_absolute_expression ();
4140 if (temp
> max_alignment
)
4141 as_bad ("Alignment too large: %d. assumed.", temp
= max_alignment
);
4144 as_warn ("Alignment negative: 0 assumed.");
4147 if (*input_line_pointer
== ',')
4149 input_line_pointer
++;
4150 temp_fill
= get_absolute_expression ();
4157 mips_align (temp
, (int) temp_fill
);
4164 demand_empty_rest_of_line ();
4167 /* Handle .ascii and .asciiz. This just calls stringer and forgets
4168 that there was a previous instruction. */
4171 s_stringer (append_zero
)
4174 mips_emit_delays ();
4176 stringer (append_zero
);
4187 mips_emit_delays ();
4197 subseg_set (bss_section
, (subsegT
) get_absolute_expression ());
4198 demand_empty_rest_of_line ();
4203 subseg_new (".rdata", (subsegT
) get_absolute_expression ());
4204 demand_empty_rest_of_line ();
4206 #else /* ! defined (OBJ_ECOFF) */
4208 seg
= subseg_new (".rodata", (subsegT
) get_absolute_expression ());
4209 bfd_set_section_flags (stdoutput
, seg
,
4215 demand_empty_rest_of_line ();
4217 #else /* ! defined (OBJ_ELF) */
4220 #endif /* ! defined (OBJ_ELF) */
4221 #endif /* ! defined (OBJ_ECOFF) */
4225 seg
= subseg_new (".sdata", (subsegT
) get_absolute_expression ());
4227 bfd_set_section_flags (stdoutput
, seg
,
4228 SEC_ALLOC
| SEC_LOAD
| SEC_RELOC
| SEC_DATA
);
4230 demand_empty_rest_of_line ();
4232 #else /* ! defined (GPOPT) */
4233 as_bad ("Global pointers not supported; recompile -G 0");
4234 demand_empty_rest_of_line ();
4236 #endif /* ! defined (GPOPT) */
4246 mips_emit_delays ();
4247 if (log_size
> 0 && auto_align
)
4248 mips_align (log_size
, 0);
4250 cons (1 << log_size
);
4257 as_fatal ("Encountered `.err', aborting assembly");
4267 symbolP
= get_symbol ();
4268 if (*input_line_pointer
== ',')
4269 input_line_pointer
++;
4270 size
= get_absolute_expression ();
4271 S_SET_VALUE (symbolP
, size
);
4272 S_SET_EXTERNAL (symbolP
);
4275 /* ECOFF needs to distinguish a .comm symbol from a .extern symbol,
4276 so we use an additional ECOFF specific field. */
4277 symbolP
->ecoff_undefined
= 1;
4285 mips_emit_delays ();
4305 opt
= input_line_pointer
;
4306 c
= get_symbol_end ();
4308 /* FIXME: What do these options mean? */
4311 else if (strncmp (opt
, "pic", 3) == 0)
4314 as_warn ("Unrecognized option \"%s\"", opt
);
4316 *input_line_pointer
= c
;
4317 demand_empty_rest_of_line ();
4324 char *name
= input_line_pointer
, ch
;
4326 while (!is_end_of_line
[(unsigned char) *input_line_pointer
])
4327 input_line_pointer
++;
4328 ch
= *input_line_pointer
;
4329 *input_line_pointer
= '\0';
4331 if (strcmp (name
, "reorder") == 0)
4335 prev_insn_unreordered
= 1;
4336 prev_prev_insn_unreordered
= 1;
4340 else if (strcmp (name
, "noreorder") == 0)
4342 mips_emit_delays ();
4345 else if (strcmp (name
, "at") == 0)
4349 else if (strcmp (name
, "noat") == 0)
4353 else if (strcmp (name
, "macro") == 0)
4355 mips_warn_about_macros
= 0;
4357 else if (strcmp (name
, "nomacro") == 0)
4359 if (mips_noreorder
== 0)
4360 as_bad ("`noreorder' must be set before `nomacro'");
4361 mips_warn_about_macros
= 1;
4363 else if (strcmp (name
, "move") == 0 || strcmp (name
, "novolatile") == 0)
4367 else if (strcmp (name
, "nomove") == 0 || strcmp (name
, "volatile") == 0)
4371 else if (strcmp (name
, "bopt") == 0)
4375 else if (strcmp (name
, "nobopt") == 0)
4381 as_warn ("Tried to set unrecognized symbol: %s\n", name
);
4383 *input_line_pointer
= ch
;
4384 demand_empty_rest_of_line ();
4387 /* The same as the usual .space directive, except that we have to
4388 forget about any previous instruction. */
4391 s_mips_space (param
)
4394 mips_emit_delays ();
4405 if (*input_line_pointer
++ != '$')
4407 as_warn ("expected `$'");
4410 if (isdigit ((unsigned char) *input_line_pointer
))
4412 reg
= get_absolute_expression ();
4413 if (reg
< 0 || reg
>= 32)
4415 as_warn ("Bad register number");
4421 if (strncmp (input_line_pointer
, "fp", 2) == 0)
4423 else if (strncmp (input_line_pointer
, "sp", 2) == 0)
4425 else if (strncmp (input_line_pointer
, "gp", 2) == 0)
4427 else if (strncmp (input_line_pointer
, "at", 2) == 0)
4431 as_warn ("Unrecognized register name");
4434 input_line_pointer
+= 2;
4440 * Translate internal representation of relocation info to BFD target format.
4443 tc_gen_reloc (section
, fixp
)
4449 reloc
= (arelent
*) xmalloc (sizeof (arelent
));
4450 assert (reloc
!= 0);
4452 reloc
->sym_ptr_ptr
= &fixp
->fx_addsy
->bsym
;
4453 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
4454 if (fixp
->fx_pcrel
== 0)
4455 reloc
->addend
= fixp
->fx_addnumber
;
4460 reloc
->addend
= -reloc
->address
;
4462 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, fixp
->fx_r_type
);
4463 if (reloc
->howto
== NULL
)
4465 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
4466 "Can not represent relocation in this object file format");
4473 /* should never be called */
4475 md_section_align (seg
, addr
)
4479 int align
= bfd_get_section_alignment (stdoutput
, seg
);
4481 return ((addr
+ (1 << align
) - 1) & (-1 << align
));
4485 md_estimate_size_before_relax (fragP
, segtype
)
4489 as_fatal ("md_estimate_size_before_relax");
4491 } /* md_estimate_size_before_relax() */
4493 /* This function is called whenever a label is defined. It is used
4494 when handling branch delays; if a branch has a label, we assume we
4498 mips_define_label (sym
)
4506 /* Write out the .reginfo section for a MIPS ELF file. */
4509 mips_elf_final_processing ()
4513 s
.ri_gprmask
= mips_gprmask
;
4514 s
.ri_cprmask
[0] = mips_cprmask
[0];
4515 s
.ri_cprmask
[1] = mips_cprmask
[1];
4516 s
.ri_cprmask
[2] = mips_cprmask
[2];
4517 s
.ri_cprmask
[3] = mips_cprmask
[3];
4518 /* The gp_value field is set by the MIPS ELF backend. */
4520 bfd_mips_elf32_swap_reginfo_out (stdoutput
, &s
,
4521 ((Elf32_External_RegInfo
*)
4522 mips_regmask_frag
));
4525 #endif /* OBJ_ELF */
4529 /* These functions should really be defined by the object file format,
4530 since they are related to debugging information. However, this
4531 code has to work for the a.out format, which does not define them,
4532 so we provide simple versions here. These don't actually generate
4533 any debugging information, but they do simple checking and someday
4534 somebody may make them useful. */
4538 struct loc
*loc_next
;
4539 unsigned long loc_fileno
;
4540 unsigned long loc_lineno
;
4541 unsigned long loc_offset
;
4542 unsigned short loc_delta
;
4543 unsigned short loc_count
;
4552 struct proc
*proc_next
;
4553 struct symbol
*proc_isym
;
4554 struct symbol
*proc_end
;
4555 unsigned long proc_reg_mask
;
4556 unsigned long proc_reg_offset
;
4557 unsigned long proc_fpreg_mask
;
4558 unsigned long proc_fpreg_offset
;
4559 unsigned long proc_frameoffset
;
4560 unsigned long proc_framereg
;
4561 unsigned long proc_pcreg
;
4563 struct file
*proc_file
;
4570 struct file
*file_next
;
4571 unsigned long file_fileno
;
4572 struct symbol
*file_symbol
;
4573 struct symbol
*file_end
;
4574 struct proc
*file_proc
;
4579 static struct obstack proc_frags
;
4580 static procS
*proc_lastP
;
4581 static procS
*proc_rootP
;
4582 static int numprocs
;
4587 obstack_begin (&proc_frags
, 0x2000);
4593 /* check for premature end, nesting errors, etc */
4594 if (proc_lastP
&& proc_lastP
->proc_end
== NULL
)
4595 as_warn ("missing `.end' at end of assembly");
4598 extern char hex_value
[];
4606 if (*input_line_pointer
== '-')
4608 ++input_line_pointer
;
4611 if (!isdigit (*input_line_pointer
))
4612 as_bad ("Expected simple number.");
4613 if (input_line_pointer
[0] == '0')
4615 if (input_line_pointer
[1] == 'x')
4617 input_line_pointer
+= 2;
4618 while (isxdigit (*input_line_pointer
))
4621 val
|= hex_value
[(int) *input_line_pointer
++];
4623 return negative
? -val
: val
;
4627 ++input_line_pointer
;
4628 while (isdigit (*input_line_pointer
))
4631 val
|= *input_line_pointer
++ - '0';
4633 return negative
? -val
: val
;
4636 if (!isdigit (*input_line_pointer
))
4638 printf (" *input_line_pointer == '%c' 0x%02x\n",
4639 *input_line_pointer
, *input_line_pointer
);
4640 as_warn ("Invalid number");
4643 while (isdigit (*input_line_pointer
))
4646 val
+= *input_line_pointer
++ - '0';
4648 return negative
? -val
: val
;
4651 /* The .file directive; just like the usual .file directive, but there
4652 is an initial number which is the ECOFF file index. */
4660 line
= get_number ();
4665 /* The .end directive. */
4673 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
4676 demand_empty_rest_of_line ();
4680 if (now_seg
!= text_section
)
4681 as_warn (".end not in text section");
4684 as_warn (".end and no .ent seen yet.");
4690 assert (S_GET_NAME (p
));
4691 if (strcmp (S_GET_NAME (p
), S_GET_NAME (proc_lastP
->proc_isym
)))
4692 as_warn (".end symbol does not match .ent symbol.");
4695 proc_lastP
->proc_end
= (symbolS
*) 1;
4698 /* The .aent and .ent directives. */
4708 symbolP
= get_symbol ();
4709 if (*input_line_pointer
== ',')
4710 input_line_pointer
++;
4712 if (isdigit (*input_line_pointer
) || *input_line_pointer
== '-')
4713 number
= get_number ();
4714 if (now_seg
!= text_section
)
4715 as_warn (".ent or .aent not in text section.");
4717 if (!aent
&& proc_lastP
&& proc_lastP
->proc_end
== NULL
)
4718 as_warn ("missing `.end'");
4722 procP
= (procS
*) obstack_alloc (&proc_frags
, sizeof (*procP
));
4723 procP
->proc_isym
= symbolP
;
4724 procP
->proc_reg_mask
= 0;
4725 procP
->proc_reg_offset
= 0;
4726 procP
->proc_fpreg_mask
= 0;
4727 procP
->proc_fpreg_offset
= 0;
4728 procP
->proc_frameoffset
= 0;
4729 procP
->proc_framereg
= 0;
4730 procP
->proc_pcreg
= 0;
4731 procP
->proc_end
= NULL
;
4732 procP
->proc_next
= NULL
;
4734 proc_lastP
->proc_next
= procP
;
4740 demand_empty_rest_of_line ();
4743 /* The .frame directive. */
4756 frame_reg
= tc_get_register ();
4757 if (*input_line_pointer
== ',')
4758 input_line_pointer
++;
4759 frame_off
= get_absolute_expression ();
4760 if (*input_line_pointer
== ',')
4761 input_line_pointer
++;
4762 pcreg
= tc_get_register ();
4765 assert (proc_rootP
);
4766 proc_rootP
->proc_framereg
= frame_reg
;
4767 proc_rootP
->proc_frameoffset
= frame_off
;
4768 proc_rootP
->proc_pcreg
= pcreg
;
4769 /* bob macho .frame */
4771 /* We don't have to write out a frame stab for unoptimized code. */
4772 if (!(frame_reg
== 30 && frame_off
== 0))
4775 as_warn ("No .ent for .frame to use.");
4776 (void) sprintf (str
, "R%d;%d", frame_reg
, frame_off
);
4777 symP
= symbol_new (str
, N_VFP
, 0, frag_now
);
4778 S_SET_TYPE (symP
, N_RMASK
);
4779 S_SET_OTHER (symP
, 0);
4780 S_SET_DESC (symP
, 0);
4781 symP
->sy_forward
= proc_lastP
->proc_isym
;
4782 /* bob perhaps I should have used pseudo set */
4784 demand_empty_rest_of_line ();
4788 /* The .fmask and .mask directives. */
4795 char str
[100], *strP
;
4801 mask
= get_number ();
4802 if (*input_line_pointer
== ',')
4803 input_line_pointer
++;
4804 off
= get_absolute_expression ();
4806 /* bob only for coff */
4807 assert (proc_rootP
);
4808 if (reg_type
== 'F')
4810 proc_rootP
->proc_fpreg_mask
= mask
;
4811 proc_rootP
->proc_fpreg_offset
= off
;
4815 proc_rootP
->proc_reg_mask
= mask
;
4816 proc_rootP
->proc_reg_offset
= off
;
4819 /* bob macho .mask + .fmask */
4821 /* We don't have to write out a mask stab if no saved regs. */
4825 as_warn ("No .ent for .mask to use.");
4827 for (i
= 0; i
< 32; i
++)
4831 sprintf (strP
, "%c%d,", reg_type
, i
);
4832 strP
+= strlen (strP
);
4836 sprintf (strP
, ";%d,", off
);
4837 symP
= symbol_new (str
, N_RMASK
, 0, frag_now
);
4838 S_SET_TYPE (symP
, N_RMASK
);
4839 S_SET_OTHER (symP
, 0);
4840 S_SET_DESC (symP
, 0);
4841 symP
->sy_forward
= proc_lastP
->proc_isym
;
4842 /* bob perhaps I should have used pseudo set */
4847 /* The .loc directive. */
4858 assert (now_seg
== text_section
);
4860 lineno
= get_number ();
4861 addroff
= obstack_next_free (&frags
) - frag_now
->fr_literal
;
4863 symbolP
= symbol_new ("", N_SLINE
, addroff
, frag_now
);
4864 S_SET_TYPE (symbolP
, N_SLINE
);
4865 S_SET_OTHER (symbolP
, 0);
4866 S_SET_DESC (symbolP
, lineno
);
4867 symbolP
->sy_segment
= now_seg
;
4871 #endif /* ! defined (OBJ_ECOFF) */