1 /* tc-mips.c -- assemble code for a MIPS chip.
2 Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,
3 2003, 2004 Free Software Foundation, Inc.
4 Contributed by the OSF and Ralph Campbell.
5 Written by Keith Knowles and Ralph Campbell, working independently.
6 Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus
9 This file is part of GAS.
11 GAS is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 2, or (at your option)
16 GAS is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
21 You should have received a copy of the GNU General Public License
22 along with GAS; see the file COPYING. If not, write to the Free
23 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
29 #include "safe-ctype.h"
33 #include "opcode/mips.h"
35 #include "dwarf2dbg.h"
38 #define DBG(x) printf x
44 /* Clean up namespace so we can include obj-elf.h too. */
45 static int mips_output_flavor (void);
46 static int mips_output_flavor (void) { return OUTPUT_FLAVOR
; }
47 #undef OBJ_PROCESS_STAB
54 #undef obj_frob_file_after_relocs
55 #undef obj_frob_symbol
57 #undef obj_sec_sym_ok_for_reloc
58 #undef OBJ_COPY_SYMBOL_ATTRIBUTES
61 /* Fix any of them that we actually care about. */
63 #define OUTPUT_FLAVOR mips_output_flavor()
70 #ifndef ECOFF_DEBUGGING
71 #define NO_ECOFF_DEBUGGING
72 #define ECOFF_DEBUGGING 0
75 int mips_flag_mdebug
= -1;
77 /* Control generation of .pdr sections. Off by default on IRIX: the native
78 linker doesn't know about and discards them, but relocations against them
79 remain, leading to rld crashes. */
81 int mips_flag_pdr
= FALSE
;
83 int mips_flag_pdr
= TRUE
;
88 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
89 static char *mips_regmask_frag
;
95 #define PIC_CALL_REG 25
103 #define ILLEGAL_REG (32)
105 /* Allow override of standard little-endian ECOFF format. */
107 #ifndef ECOFF_LITTLE_FORMAT
108 #define ECOFF_LITTLE_FORMAT "ecoff-littlemips"
111 extern int target_big_endian
;
113 /* The name of the readonly data section. */
114 #define RDATA_SECTION_NAME (OUTPUT_FLAVOR == bfd_target_ecoff_flavour \
116 : OUTPUT_FLAVOR == bfd_target_coff_flavour \
118 : OUTPUT_FLAVOR == bfd_target_elf_flavour \
122 /* The ABI to use. */
133 /* MIPS ABI we are using for this output file. */
134 static enum mips_abi_level mips_abi
= NO_ABI
;
136 /* Whether or not we have code that can call pic code. */
137 int mips_abicalls
= FALSE
;
139 /* This is the set of options which may be modified by the .set
140 pseudo-op. We use a struct so that .set push and .set pop are more
143 struct mips_set_options
145 /* MIPS ISA (Instruction Set Architecture) level. This is set to -1
146 if it has not been initialized. Changed by `.set mipsN', and the
147 -mipsN command line option, and the default CPU. */
149 /* Enabled Application Specific Extensions (ASEs). These are set to -1
150 if they have not been initialized. Changed by `.set <asename>', by
151 command line options, and based on the default architecture. */
154 /* Whether we are assembling for the mips16 processor. 0 if we are
155 not, 1 if we are, and -1 if the value has not been initialized.
156 Changed by `.set mips16' and `.set nomips16', and the -mips16 and
157 -nomips16 command line options, and the default CPU. */
159 /* Non-zero if we should not reorder instructions. Changed by `.set
160 reorder' and `.set noreorder'. */
162 /* Non-zero if we should not permit the $at ($1) register to be used
163 in instructions. Changed by `.set at' and `.set noat'. */
165 /* Non-zero if we should warn when a macro instruction expands into
166 more than one machine instruction. Changed by `.set nomacro' and
168 int warn_about_macros
;
169 /* Non-zero if we should not move instructions. Changed by `.set
170 move', `.set volatile', `.set nomove', and `.set novolatile'. */
172 /* Non-zero if we should not optimize branches by moving the target
173 of the branch into the delay slot. Actually, we don't perform
174 this optimization anyhow. Changed by `.set bopt' and `.set
177 /* Non-zero if we should not autoextend mips16 instructions.
178 Changed by `.set autoextend' and `.set noautoextend'. */
180 /* Restrict general purpose registers and floating point registers
181 to 32 bit. This is initially determined when -mgp32 or -mfp32
182 is passed but can changed if the assembler code uses .set mipsN. */
185 /* MIPS architecture (CPU) type. Changed by .set arch=FOO, the -march
186 command line option, and the default CPU. */
190 /* True if -mgp32 was passed. */
191 static int file_mips_gp32
= -1;
193 /* True if -mfp32 was passed. */
194 static int file_mips_fp32
= -1;
196 /* This is the struct we use to hold the current set of options. Note
197 that we must set the isa field to ISA_UNKNOWN and the ASE fields to
198 -1 to indicate that they have not been initialized. */
200 static struct mips_set_options mips_opts
=
202 ISA_UNKNOWN
, -1, -1, -1, 0, 0, 0, 0, 0, 0, 0, 0, CPU_UNKNOWN
205 /* These variables are filled in with the masks of registers used.
206 The object format code reads them and puts them in the appropriate
208 unsigned long mips_gprmask
;
209 unsigned long mips_cprmask
[4];
211 /* MIPS ISA we are using for this output file. */
212 static int file_mips_isa
= ISA_UNKNOWN
;
214 /* True if -mips16 was passed or implied by arguments passed on the
215 command line (e.g., by -march). */
216 static int file_ase_mips16
;
218 /* True if -mips3d was passed or implied by arguments passed on the
219 command line (e.g., by -march). */
220 static int file_ase_mips3d
;
222 /* True if -mdmx was passed or implied by arguments passed on the
223 command line (e.g., by -march). */
224 static int file_ase_mdmx
;
226 /* The argument of the -march= flag. The architecture we are assembling. */
227 static int file_mips_arch
= CPU_UNKNOWN
;
228 static const char *mips_arch_string
;
230 /* The argument of the -mtune= flag. The architecture for which we
232 static int mips_tune
= CPU_UNKNOWN
;
233 static const char *mips_tune_string
;
235 /* True when generating 32-bit code for a 64-bit processor. */
236 static int mips_32bitmode
= 0;
238 /* True if the given ABI requires 32-bit registers. */
239 #define ABI_NEEDS_32BIT_REGS(ABI) ((ABI) == O32_ABI)
241 /* Likewise 64-bit registers. */
242 #define ABI_NEEDS_64BIT_REGS(ABI) \
244 || (ABI) == N64_ABI \
247 /* Return true if ISA supports 64 bit gp register instructions. */
248 #define ISA_HAS_64BIT_REGS(ISA) ( \
250 || (ISA) == ISA_MIPS4 \
251 || (ISA) == ISA_MIPS5 \
252 || (ISA) == ISA_MIPS64 \
253 || (ISA) == ISA_MIPS64R2 \
256 /* Return true if ISA supports 64-bit right rotate (dror et al.)
258 #define ISA_HAS_DROR(ISA) ( \
259 (ISA) == ISA_MIPS64R2 \
262 /* Return true if ISA supports 32-bit right rotate (ror et al.)
264 #define ISA_HAS_ROR(ISA) ( \
265 (ISA) == ISA_MIPS32R2 \
266 || (ISA) == ISA_MIPS64R2 \
269 #define HAVE_32BIT_GPRS \
270 (mips_opts.gp32 || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
272 #define HAVE_32BIT_FPRS \
273 (mips_opts.fp32 || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
275 #define HAVE_64BIT_GPRS (! HAVE_32BIT_GPRS)
276 #define HAVE_64BIT_FPRS (! HAVE_32BIT_FPRS)
278 #define HAVE_NEWABI (mips_abi == N32_ABI || mips_abi == N64_ABI)
280 #define HAVE_64BIT_OBJECTS (mips_abi == N64_ABI)
282 /* We can only have 64bit addresses if the object file format supports it. */
283 #define HAVE_32BIT_ADDRESSES \
285 || (bfd_arch_bits_per_address (stdoutput) == 32 \
286 || ! HAVE_64BIT_OBJECTS)) \
288 #define HAVE_64BIT_ADDRESSES (! HAVE_32BIT_ADDRESSES)
290 /* Addresses are loaded in different ways, depending on the address size
291 in use. The n32 ABI Documentation also mandates the use of additions
292 with overflow checking, but existing implementations don't follow it. */
293 #define ADDRESS_ADD_INSN \
294 (HAVE_32BIT_ADDRESSES ? "addu" : "daddu")
296 #define ADDRESS_ADDI_INSN \
297 (HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu")
299 #define ADDRESS_LOAD_INSN \
300 (HAVE_32BIT_ADDRESSES ? "lw" : "ld")
302 #define ADDRESS_STORE_INSN \
303 (HAVE_32BIT_ADDRESSES ? "sw" : "sd")
305 /* Return true if the given CPU supports the MIPS16 ASE. */
306 #define CPU_HAS_MIPS16(cpu) \
307 (strncmp (TARGET_CPU, "mips16", sizeof ("mips16") - 1) == 0 \
308 || strncmp (TARGET_CANONICAL, "mips-lsi-elf", sizeof ("mips-lsi-elf") - 1) == 0)
310 /* Return true if the given CPU supports the MIPS3D ASE. */
311 #define CPU_HAS_MIPS3D(cpu) ((cpu) == CPU_SB1 \
314 /* Return true if the given CPU supports the MDMX ASE. */
315 #define CPU_HAS_MDMX(cpu) (FALSE \
318 /* True if CPU has a dror instruction. */
319 #define CPU_HAS_DROR(CPU) ((CPU) == CPU_VR5400 || (CPU) == CPU_VR5500)
321 /* True if CPU has a ror instruction. */
322 #define CPU_HAS_ROR(CPU) CPU_HAS_DROR (CPU)
324 /* True if mflo and mfhi can be immediately followed by instructions
325 which write to the HI and LO registers.
327 According to MIPS specifications, MIPS ISAs I, II, and III need
328 (at least) two instructions between the reads of HI/LO and
329 instructions which write them, and later ISAs do not. Contradicting
330 the MIPS specifications, some MIPS IV processor user manuals (e.g.
331 the UM for the NEC Vr5000) document needing the instructions between
332 HI/LO reads and writes, as well. Therefore, we declare only MIPS32,
333 MIPS64 and later ISAs to have the interlocks, plus any specific
334 earlier-ISA CPUs for which CPU documentation declares that the
335 instructions are really interlocked. */
336 #define hilo_interlocks \
337 (mips_opts.isa == ISA_MIPS32 \
338 || mips_opts.isa == ISA_MIPS32R2 \
339 || mips_opts.isa == ISA_MIPS64 \
340 || mips_opts.isa == ISA_MIPS64R2 \
341 || mips_opts.arch == CPU_R4010 \
342 || mips_opts.arch == CPU_R10000 \
343 || mips_opts.arch == CPU_R12000 \
344 || mips_opts.arch == CPU_RM7000 \
345 || mips_opts.arch == CPU_VR5500 \
348 /* Whether the processor uses hardware interlocks to protect reads
349 from the GPRs after they are loaded from memory, and thus does not
350 require nops to be inserted. This applies to instructions marked
351 INSN_LOAD_MEMORY_DELAY. These nops are only required at MIPS ISA
353 #define gpr_interlocks \
354 (mips_opts.isa != ISA_MIPS1 \
355 || mips_opts.arch == CPU_R3900)
357 /* Whether the processor uses hardware interlocks to avoid delays
358 required by coprocessor instructions, and thus does not require
359 nops to be inserted. This applies to instructions marked
360 INSN_LOAD_COPROC_DELAY, INSN_COPROC_MOVE_DELAY, and to delays
361 between instructions marked INSN_WRITE_COND_CODE and ones marked
362 INSN_READ_COND_CODE. These nops are only required at MIPS ISA
363 levels I, II, and III. */
364 /* Itbl support may require additional care here. */
365 #define cop_interlocks \
366 ((mips_opts.isa != ISA_MIPS1 \
367 && mips_opts.isa != ISA_MIPS2 \
368 && mips_opts.isa != ISA_MIPS3) \
369 || mips_opts.arch == CPU_R4300 \
372 /* Whether the processor uses hardware interlocks to protect reads
373 from coprocessor registers after they are loaded from memory, and
374 thus does not require nops to be inserted. This applies to
375 instructions marked INSN_COPROC_MEMORY_DELAY. These nops are only
376 requires at MIPS ISA level I. */
377 #define cop_mem_interlocks (mips_opts.isa != ISA_MIPS1)
379 /* Is this a mfhi or mflo instruction? */
380 #define MF_HILO_INSN(PINFO) \
381 ((PINFO & INSN_READ_HI) || (PINFO & INSN_READ_LO))
383 /* MIPS PIC level. */
385 enum mips_pic_level mips_pic
;
387 /* 1 if we should generate 32 bit offsets from the $gp register in
388 SVR4_PIC mode. Currently has no meaning in other modes. */
389 static int mips_big_got
= 0;
391 /* 1 if trap instructions should used for overflow rather than break
393 static int mips_trap
= 0;
395 /* 1 if double width floating point constants should not be constructed
396 by assembling two single width halves into two single width floating
397 point registers which just happen to alias the double width destination
398 register. On some architectures this aliasing can be disabled by a bit
399 in the status register, and the setting of this bit cannot be determined
400 automatically at assemble time. */
401 static int mips_disable_float_construction
;
403 /* Non-zero if any .set noreorder directives were used. */
405 static int mips_any_noreorder
;
407 /* Non-zero if nops should be inserted when the register referenced in
408 an mfhi/mflo instruction is read in the next two instructions. */
409 static int mips_7000_hilo_fix
;
411 /* The size of the small data section. */
412 static unsigned int g_switch_value
= 8;
413 /* Whether the -G option was used. */
414 static int g_switch_seen
= 0;
419 /* If we can determine in advance that GP optimization won't be
420 possible, we can skip the relaxation stuff that tries to produce
421 GP-relative references. This makes delay slot optimization work
424 This function can only provide a guess, but it seems to work for
425 gcc output. It needs to guess right for gcc, otherwise gcc
426 will put what it thinks is a GP-relative instruction in a branch
429 I don't know if a fix is needed for the SVR4_PIC mode. I've only
430 fixed it for the non-PIC mode. KR 95/04/07 */
431 static int nopic_need_relax (symbolS
*, int);
433 /* handle of the OPCODE hash table */
434 static struct hash_control
*op_hash
= NULL
;
436 /* The opcode hash table we use for the mips16. */
437 static struct hash_control
*mips16_op_hash
= NULL
;
439 /* This array holds the chars that always start a comment. If the
440 pre-processor is disabled, these aren't very useful */
441 const char comment_chars
[] = "#";
443 /* This array holds the chars that only start a comment at the beginning of
444 a line. If the line seems to have the form '# 123 filename'
445 .line and .file directives will appear in the pre-processed output */
446 /* Note that input_file.c hand checks for '#' at the beginning of the
447 first line of the input file. This is because the compiler outputs
448 #NO_APP at the beginning of its output. */
449 /* Also note that C style comments are always supported. */
450 const char line_comment_chars
[] = "#";
452 /* This array holds machine specific line separator characters. */
453 const char line_separator_chars
[] = ";";
455 /* Chars that can be used to separate mant from exp in floating point nums */
456 const char EXP_CHARS
[] = "eE";
458 /* Chars that mean this number is a floating point constant */
461 const char FLT_CHARS
[] = "rRsSfFdDxXpP";
463 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
464 changed in read.c . Ideally it shouldn't have to know about it at all,
465 but nothing is ideal around here.
468 static char *insn_error
;
470 static int auto_align
= 1;
472 /* When outputting SVR4 PIC code, the assembler needs to know the
473 offset in the stack frame from which to restore the $gp register.
474 This is set by the .cprestore pseudo-op, and saved in this
476 static offsetT mips_cprestore_offset
= -1;
478 /* Similar for NewABI PIC code, where $gp is callee-saved. NewABI has some
479 more optimizations, it can use a register value instead of a memory-saved
480 offset and even an other register than $gp as global pointer. */
481 static offsetT mips_cpreturn_offset
= -1;
482 static int mips_cpreturn_register
= -1;
483 static int mips_gp_register
= GP
;
484 static int mips_gprel_offset
= 0;
486 /* Whether mips_cprestore_offset has been set in the current function
487 (or whether it has already been warned about, if not). */
488 static int mips_cprestore_valid
= 0;
490 /* This is the register which holds the stack frame, as set by the
491 .frame pseudo-op. This is needed to implement .cprestore. */
492 static int mips_frame_reg
= SP
;
494 /* Whether mips_frame_reg has been set in the current function
495 (or whether it has already been warned about, if not). */
496 static int mips_frame_reg_valid
= 0;
498 /* To output NOP instructions correctly, we need to keep information
499 about the previous two instructions. */
501 /* Whether we are optimizing. The default value of 2 means to remove
502 unneeded NOPs and swap branch instructions when possible. A value
503 of 1 means to not swap branches. A value of 0 means to always
505 static int mips_optimize
= 2;
507 /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is
508 equivalent to seeing no -g option at all. */
509 static int mips_debug
= 0;
511 /* The previous instruction. */
512 static struct mips_cl_insn prev_insn
;
514 /* The instruction before prev_insn. */
515 static struct mips_cl_insn prev_prev_insn
;
517 /* If we don't want information for prev_insn or prev_prev_insn, we
518 point the insn_mo field at this dummy integer. */
519 static const struct mips_opcode dummy_opcode
= { NULL
, NULL
, 0, 0, 0, 0 };
521 /* Non-zero if prev_insn is valid. */
522 static int prev_insn_valid
;
524 /* The frag for the previous instruction. */
525 static struct frag
*prev_insn_frag
;
527 /* The offset into prev_insn_frag for the previous instruction. */
528 static long prev_insn_where
;
530 /* The reloc type for the previous instruction, if any. */
531 static bfd_reloc_code_real_type prev_insn_reloc_type
[3];
533 /* The reloc for the previous instruction, if any. */
534 static fixS
*prev_insn_fixp
[3];
536 /* Non-zero if the previous instruction was in a delay slot. */
537 static int prev_insn_is_delay_slot
;
539 /* Non-zero if the previous instruction was in a .set noreorder. */
540 static int prev_insn_unreordered
;
542 /* Non-zero if the previous instruction uses an extend opcode (if
544 static int prev_insn_extended
;
546 /* Non-zero if the previous previous instruction was in a .set
548 static int prev_prev_insn_unreordered
;
550 /* If this is set, it points to a frag holding nop instructions which
551 were inserted before the start of a noreorder section. If those
552 nops turn out to be unnecessary, the size of the frag can be
554 static fragS
*prev_nop_frag
;
556 /* The number of nop instructions we created in prev_nop_frag. */
557 static int prev_nop_frag_holds
;
559 /* The number of nop instructions that we know we need in
561 static int prev_nop_frag_required
;
563 /* The number of instructions we've seen since prev_nop_frag. */
564 static int prev_nop_frag_since
;
566 /* For ECOFF and ELF, relocations against symbols are done in two
567 parts, with a HI relocation and a LO relocation. Each relocation
568 has only 16 bits of space to store an addend. This means that in
569 order for the linker to handle carries correctly, it must be able
570 to locate both the HI and the LO relocation. This means that the
571 relocations must appear in order in the relocation table.
573 In order to implement this, we keep track of each unmatched HI
574 relocation. We then sort them so that they immediately precede the
575 corresponding LO relocation. */
580 struct mips_hi_fixup
*next
;
583 /* The section this fixup is in. */
587 /* The list of unmatched HI relocs. */
589 static struct mips_hi_fixup
*mips_hi_fixup_list
;
591 /* The frag containing the last explicit relocation operator.
592 Null if explicit relocations have not been used. */
594 static fragS
*prev_reloc_op_frag
;
596 /* Map normal MIPS register numbers to mips16 register numbers. */
598 #define X ILLEGAL_REG
599 static const int mips32_to_16_reg_map
[] =
601 X
, X
, 2, 3, 4, 5, 6, 7,
602 X
, X
, X
, X
, X
, X
, X
, X
,
603 0, 1, X
, X
, X
, X
, X
, X
,
604 X
, X
, X
, X
, X
, X
, X
, X
608 /* Map mips16 register numbers to normal MIPS register numbers. */
610 static const unsigned int mips16_to_32_reg_map
[] =
612 16, 17, 2, 3, 4, 5, 6, 7
615 static int mips_fix_vr4120
;
617 /* We don't relax branches by default, since this causes us to expand
618 `la .l2 - .l1' if there's a branch between .l1 and .l2, because we
619 fail to compute the offset before expanding the macro to the most
620 efficient expansion. */
622 static int mips_relax_branch
;
624 /* The expansion of many macros depends on the type of symbol that
625 they refer to. For example, when generating position-dependent code,
626 a macro that refers to a symbol may have two different expansions,
627 one which uses GP-relative addresses and one which uses absolute
628 addresses. When generating SVR4-style PIC, a macro may have
629 different expansions for local and global symbols.
631 We handle these situations by generating both sequences and putting
632 them in variant frags. In position-dependent code, the first sequence
633 will be the GP-relative one and the second sequence will be the
634 absolute one. In SVR4 PIC, the first sequence will be for global
635 symbols and the second will be for local symbols.
637 The frag's "subtype" is RELAX_ENCODE (FIRST, SECOND), where FIRST and
638 SECOND are the lengths of the two sequences in bytes. These fields
639 can be extracted using RELAX_FIRST() and RELAX_SECOND(). In addition,
640 the subtype has the following flags:
643 Set if it has been decided that we should use the second
644 sequence instead of the first.
647 Set in the first variant frag if the macro's second implementation
648 is longer than its first. This refers to the macro as a whole,
649 not an individual relaxation.
652 Set in the first variant frag if the macro appeared in a .set nomacro
653 block and if one alternative requires a warning but the other does not.
656 Like RELAX_NOMACRO, but indicates that the macro appears in a branch
659 The frag's "opcode" points to the first fixup for relaxable code.
661 Relaxable macros are generated using a sequence such as:
663 relax_start (SYMBOL);
664 ... generate first expansion ...
666 ... generate second expansion ...
669 The code and fixups for the unwanted alternative are discarded
670 by md_convert_frag. */
671 #define RELAX_ENCODE(FIRST, SECOND) (((FIRST) << 8) | (SECOND))
673 #define RELAX_FIRST(X) (((X) >> 8) & 0xff)
674 #define RELAX_SECOND(X) ((X) & 0xff)
675 #define RELAX_USE_SECOND 0x10000
676 #define RELAX_SECOND_LONGER 0x20000
677 #define RELAX_NOMACRO 0x40000
678 #define RELAX_DELAY_SLOT 0x80000
680 /* Branch without likely bit. If label is out of range, we turn:
682 beq reg1, reg2, label
692 with the following opcode replacements:
699 bltzal <-> bgezal (with jal label instead of j label)
701 Even though keeping the delay slot instruction in the delay slot of
702 the branch would be more efficient, it would be very tricky to do
703 correctly, because we'd have to introduce a variable frag *after*
704 the delay slot instruction, and expand that instead. Let's do it
705 the easy way for now, even if the branch-not-taken case now costs
706 one additional instruction. Out-of-range branches are not supposed
707 to be common, anyway.
709 Branch likely. If label is out of range, we turn:
711 beql reg1, reg2, label
712 delay slot (annulled if branch not taken)
721 delay slot (executed only if branch taken)
724 It would be possible to generate a shorter sequence by losing the
725 likely bit, generating something like:
730 delay slot (executed only if branch taken)
742 bltzall -> bgezal (with jal label instead of j label)
743 bgezall -> bltzal (ditto)
746 but it's not clear that it would actually improve performance. */
747 #define RELAX_BRANCH_ENCODE(uncond, likely, link, toofar) \
750 | ((toofar) ? 1 : 0) \
752 | ((likely) ? 4 : 0) \
753 | ((uncond) ? 8 : 0)))
754 #define RELAX_BRANCH_P(i) (((i) & 0xf0000000) == 0xc0000000)
755 #define RELAX_BRANCH_UNCOND(i) (((i) & 8) != 0)
756 #define RELAX_BRANCH_LIKELY(i) (((i) & 4) != 0)
757 #define RELAX_BRANCH_LINK(i) (((i) & 2) != 0)
758 #define RELAX_BRANCH_TOOFAR(i) (((i) & 1) != 0)
760 /* For mips16 code, we use an entirely different form of relaxation.
761 mips16 supports two versions of most instructions which take
762 immediate values: a small one which takes some small value, and a
763 larger one which takes a 16 bit value. Since branches also follow
764 this pattern, relaxing these values is required.
766 We can assemble both mips16 and normal MIPS code in a single
767 object. Therefore, we need to support this type of relaxation at
768 the same time that we support the relaxation described above. We
769 use the high bit of the subtype field to distinguish these cases.
771 The information we store for this type of relaxation is the
772 argument code found in the opcode file for this relocation, whether
773 the user explicitly requested a small or extended form, and whether
774 the relocation is in a jump or jal delay slot. That tells us the
775 size of the value, and how it should be stored. We also store
776 whether the fragment is considered to be extended or not. We also
777 store whether this is known to be a branch to a different section,
778 whether we have tried to relax this frag yet, and whether we have
779 ever extended a PC relative fragment because of a shift count. */
780 #define RELAX_MIPS16_ENCODE(type, small, ext, dslot, jal_dslot) \
783 | ((small) ? 0x100 : 0) \
784 | ((ext) ? 0x200 : 0) \
785 | ((dslot) ? 0x400 : 0) \
786 | ((jal_dslot) ? 0x800 : 0))
787 #define RELAX_MIPS16_P(i) (((i) & 0xc0000000) == 0x80000000)
788 #define RELAX_MIPS16_TYPE(i) ((i) & 0xff)
789 #define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x100) != 0)
790 #define RELAX_MIPS16_USER_EXT(i) (((i) & 0x200) != 0)
791 #define RELAX_MIPS16_DSLOT(i) (((i) & 0x400) != 0)
792 #define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x800) != 0)
793 #define RELAX_MIPS16_EXTENDED(i) (((i) & 0x1000) != 0)
794 #define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x1000)
795 #define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) &~ 0x1000)
796 #define RELAX_MIPS16_LONG_BRANCH(i) (((i) & 0x2000) != 0)
797 #define RELAX_MIPS16_MARK_LONG_BRANCH(i) ((i) | 0x2000)
798 #define RELAX_MIPS16_CLEAR_LONG_BRANCH(i) ((i) &~ 0x2000)
800 /* Is the given value a sign-extended 32-bit value? */
801 #define IS_SEXT_32BIT_NUM(x) \
802 (((x) &~ (offsetT) 0x7fffffff) == 0 \
803 || (((x) &~ (offsetT) 0x7fffffff) == ~ (offsetT) 0x7fffffff))
805 /* Is the given value a sign-extended 16-bit value? */
806 #define IS_SEXT_16BIT_NUM(x) \
807 (((x) &~ (offsetT) 0x7fff) == 0 \
808 || (((x) &~ (offsetT) 0x7fff) == ~ (offsetT) 0x7fff))
811 /* Global variables used when generating relaxable macros. See the
812 comment above RELAX_ENCODE for more details about how relaxation
815 /* 0 if we're not emitting a relaxable macro.
816 1 if we're emitting the first of the two relaxation alternatives.
817 2 if we're emitting the second alternative. */
820 /* The first relaxable fixup in the current frag. (In other words,
821 the first fixup that refers to relaxable code.) */
824 /* sizes[0] says how many bytes of the first alternative are stored in
825 the current frag. Likewise sizes[1] for the second alternative. */
826 unsigned int sizes
[2];
828 /* The symbol on which the choice of sequence depends. */
832 /* Global variables used to decide whether a macro needs a warning. */
834 /* True if the macro is in a branch delay slot. */
835 bfd_boolean delay_slot_p
;
837 /* For relaxable macros, sizes[0] is the length of the first alternative
838 in bytes and sizes[1] is the length of the second alternative.
839 For non-relaxable macros, both elements give the length of the
841 unsigned int sizes
[2];
843 /* The first variant frag for this macro. */
845 } mips_macro_warning
;
847 /* Prototypes for static functions. */
849 #define internalError() \
850 as_fatal (_("internal Error, line %d, %s"), __LINE__, __FILE__)
852 enum mips_regclass
{ MIPS_GR_REG
, MIPS_FP_REG
, MIPS16_REG
};
854 static void append_insn
855 (struct mips_cl_insn
*ip
, expressionS
*p
, bfd_reloc_code_real_type
*r
);
856 static void mips_no_prev_insn (int);
857 static void mips16_macro_build
858 (expressionS
*, const char *, const char *, va_list);
859 static void load_register (int, expressionS
*, int);
860 static void macro_start (void);
861 static void macro_end (void);
862 static void macro (struct mips_cl_insn
* ip
);
863 static void mips16_macro (struct mips_cl_insn
* ip
);
864 #ifdef LOSING_COMPILER
865 static void macro2 (struct mips_cl_insn
* ip
);
867 static void mips_ip (char *str
, struct mips_cl_insn
* ip
);
868 static void mips16_ip (char *str
, struct mips_cl_insn
* ip
);
869 static void mips16_immed
870 (char *, unsigned int, int, offsetT
, bfd_boolean
, bfd_boolean
, bfd_boolean
,
871 unsigned long *, bfd_boolean
*, unsigned short *);
872 static size_t my_getSmallExpression
873 (expressionS
*, bfd_reloc_code_real_type
*, char *);
874 static void my_getExpression (expressionS
*, char *);
875 static void s_align (int);
876 static void s_change_sec (int);
877 static void s_change_section (int);
878 static void s_cons (int);
879 static void s_float_cons (int);
880 static void s_mips_globl (int);
881 static void s_option (int);
882 static void s_mipsset (int);
883 static void s_abicalls (int);
884 static void s_cpload (int);
885 static void s_cpsetup (int);
886 static void s_cplocal (int);
887 static void s_cprestore (int);
888 static void s_cpreturn (int);
889 static void s_gpvalue (int);
890 static void s_gpword (int);
891 static void s_gpdword (int);
892 static void s_cpadd (int);
893 static void s_insn (int);
894 static void md_obj_begin (void);
895 static void md_obj_end (void);
896 static void s_mips_ent (int);
897 static void s_mips_end (int);
898 static void s_mips_frame (int);
899 static void s_mips_mask (int reg_type
);
900 static void s_mips_stab (int);
901 static void s_mips_weakext (int);
902 static void s_mips_file (int);
903 static void s_mips_loc (int);
904 static bfd_boolean
pic_need_relax (symbolS
*, asection
*);
905 static int relaxed_branch_length (fragS
*, asection
*, int);
906 static int validate_mips_insn (const struct mips_opcode
*);
908 /* Table and functions used to map between CPU/ISA names, and
909 ISA levels, and CPU numbers. */
913 const char *name
; /* CPU or ISA name. */
914 int is_isa
; /* Is this an ISA? (If 0, a CPU.) */
915 int isa
; /* ISA level. */
916 int cpu
; /* CPU number (default CPU if ISA). */
919 static const struct mips_cpu_info
*mips_parse_cpu (const char *, const char *);
920 static const struct mips_cpu_info
*mips_cpu_info_from_isa (int);
921 static const struct mips_cpu_info
*mips_cpu_info_from_arch (int);
925 The following pseudo-ops from the Kane and Heinrich MIPS book
926 should be defined here, but are currently unsupported: .alias,
927 .galive, .gjaldef, .gjrlive, .livereg, .noalias.
929 The following pseudo-ops from the Kane and Heinrich MIPS book are
930 specific to the type of debugging information being generated, and
931 should be defined by the object format: .aent, .begin, .bend,
932 .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp,
935 The following pseudo-ops from the Kane and Heinrich MIPS book are
936 not MIPS CPU specific, but are also not specific to the object file
937 format. This file is probably the best place to define them, but
938 they are not currently supported: .asm0, .endr, .lab, .repeat,
941 static const pseudo_typeS mips_pseudo_table
[] =
943 /* MIPS specific pseudo-ops. */
944 {"option", s_option
, 0},
945 {"set", s_mipsset
, 0},
946 {"rdata", s_change_sec
, 'r'},
947 {"sdata", s_change_sec
, 's'},
948 {"livereg", s_ignore
, 0},
949 {"abicalls", s_abicalls
, 0},
950 {"cpload", s_cpload
, 0},
951 {"cpsetup", s_cpsetup
, 0},
952 {"cplocal", s_cplocal
, 0},
953 {"cprestore", s_cprestore
, 0},
954 {"cpreturn", s_cpreturn
, 0},
955 {"gpvalue", s_gpvalue
, 0},
956 {"gpword", s_gpword
, 0},
957 {"gpdword", s_gpdword
, 0},
958 {"cpadd", s_cpadd
, 0},
961 /* Relatively generic pseudo-ops that happen to be used on MIPS
963 {"asciiz", stringer
, 1},
964 {"bss", s_change_sec
, 'b'},
967 {"dword", s_cons
, 3},
968 {"weakext", s_mips_weakext
, 0},
970 /* These pseudo-ops are defined in read.c, but must be overridden
971 here for one reason or another. */
972 {"align", s_align
, 0},
974 {"data", s_change_sec
, 'd'},
975 {"double", s_float_cons
, 'd'},
976 {"float", s_float_cons
, 'f'},
977 {"globl", s_mips_globl
, 0},
978 {"global", s_mips_globl
, 0},
979 {"hword", s_cons
, 1},
984 {"section", s_change_section
, 0},
985 {"short", s_cons
, 1},
986 {"single", s_float_cons
, 'f'},
987 {"stabn", s_mips_stab
, 'n'},
988 {"text", s_change_sec
, 't'},
991 { "extern", ecoff_directive_extern
, 0},
996 static const pseudo_typeS mips_nonecoff_pseudo_table
[] =
998 /* These pseudo-ops should be defined by the object file format.
999 However, a.out doesn't support them, so we have versions here. */
1000 {"aent", s_mips_ent
, 1},
1001 {"bgnb", s_ignore
, 0},
1002 {"end", s_mips_end
, 0},
1003 {"endb", s_ignore
, 0},
1004 {"ent", s_mips_ent
, 0},
1005 {"file", s_mips_file
, 0},
1006 {"fmask", s_mips_mask
, 'F'},
1007 {"frame", s_mips_frame
, 0},
1008 {"loc", s_mips_loc
, 0},
1009 {"mask", s_mips_mask
, 'R'},
1010 {"verstamp", s_ignore
, 0},
1014 extern void pop_insert (const pseudo_typeS
*);
1017 mips_pop_insert (void)
1019 pop_insert (mips_pseudo_table
);
1020 if (! ECOFF_DEBUGGING
)
1021 pop_insert (mips_nonecoff_pseudo_table
);
1024 /* Symbols labelling the current insn. */
1026 struct insn_label_list
1028 struct insn_label_list
*next
;
1032 static struct insn_label_list
*insn_labels
;
1033 static struct insn_label_list
*free_insn_labels
;
1035 static void mips_clear_insn_labels (void);
1038 mips_clear_insn_labels (void)
1040 register struct insn_label_list
**pl
;
1042 for (pl
= &free_insn_labels
; *pl
!= NULL
; pl
= &(*pl
)->next
)
1048 static char *expr_end
;
1050 /* Expressions which appear in instructions. These are set by
1053 static expressionS imm_expr
;
1054 static expressionS imm2_expr
;
1055 static expressionS offset_expr
;
1057 /* Relocs associated with imm_expr and offset_expr. */
1059 static bfd_reloc_code_real_type imm_reloc
[3]
1060 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
1061 static bfd_reloc_code_real_type offset_reloc
[3]
1062 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
1064 /* These are set by mips16_ip if an explicit extension is used. */
1066 static bfd_boolean mips16_small
, mips16_ext
;
1069 /* The pdr segment for per procedure frame/regmask info. Not used for
1072 static segT pdr_seg
;
1075 /* The default target format to use. */
1078 mips_target_format (void)
1080 switch (OUTPUT_FLAVOR
)
1082 case bfd_target_ecoff_flavour
:
1083 return target_big_endian
? "ecoff-bigmips" : ECOFF_LITTLE_FORMAT
;
1084 case bfd_target_coff_flavour
:
1086 case bfd_target_elf_flavour
:
1088 /* This is traditional mips. */
1089 return (target_big_endian
1090 ? (HAVE_64BIT_OBJECTS
1091 ? "elf64-tradbigmips"
1093 ? "elf32-ntradbigmips" : "elf32-tradbigmips"))
1094 : (HAVE_64BIT_OBJECTS
1095 ? "elf64-tradlittlemips"
1097 ? "elf32-ntradlittlemips" : "elf32-tradlittlemips")));
1099 return (target_big_endian
1100 ? (HAVE_64BIT_OBJECTS
1103 ? "elf32-nbigmips" : "elf32-bigmips"))
1104 : (HAVE_64BIT_OBJECTS
1105 ? "elf64-littlemips"
1107 ? "elf32-nlittlemips" : "elf32-littlemips")));
1115 /* This function is called once, at assembler startup time. It should
1116 set up all the tables, etc. that the MD part of the assembler will need. */
1121 register const char *retval
= NULL
;
1125 if (! bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, file_mips_arch
))
1126 as_warn (_("Could not set architecture and machine"));
1128 op_hash
= hash_new ();
1130 for (i
= 0; i
< NUMOPCODES
;)
1132 const char *name
= mips_opcodes
[i
].name
;
1134 retval
= hash_insert (op_hash
, name
, (void *) &mips_opcodes
[i
]);
1137 fprintf (stderr
, _("internal error: can't hash `%s': %s\n"),
1138 mips_opcodes
[i
].name
, retval
);
1139 /* Probably a memory allocation problem? Give up now. */
1140 as_fatal (_("Broken assembler. No assembly attempted."));
1144 if (mips_opcodes
[i
].pinfo
!= INSN_MACRO
)
1146 if (!validate_mips_insn (&mips_opcodes
[i
]))
1151 while ((i
< NUMOPCODES
) && !strcmp (mips_opcodes
[i
].name
, name
));
1154 mips16_op_hash
= hash_new ();
1157 while (i
< bfd_mips16_num_opcodes
)
1159 const char *name
= mips16_opcodes
[i
].name
;
1161 retval
= hash_insert (mips16_op_hash
, name
, (void *) &mips16_opcodes
[i
]);
1163 as_fatal (_("internal: can't hash `%s': %s"),
1164 mips16_opcodes
[i
].name
, retval
);
1167 if (mips16_opcodes
[i
].pinfo
!= INSN_MACRO
1168 && ((mips16_opcodes
[i
].match
& mips16_opcodes
[i
].mask
)
1169 != mips16_opcodes
[i
].match
))
1171 fprintf (stderr
, _("internal error: bad mips16 opcode: %s %s\n"),
1172 mips16_opcodes
[i
].name
, mips16_opcodes
[i
].args
);
1177 while (i
< bfd_mips16_num_opcodes
1178 && strcmp (mips16_opcodes
[i
].name
, name
) == 0);
1182 as_fatal (_("Broken assembler. No assembly attempted."));
1184 /* We add all the general register names to the symbol table. This
1185 helps us detect invalid uses of them. */
1186 for (i
= 0; i
< 32; i
++)
1190 sprintf (buf
, "$%d", i
);
1191 symbol_table_insert (symbol_new (buf
, reg_section
, i
,
1192 &zero_address_frag
));
1194 symbol_table_insert (symbol_new ("$ra", reg_section
, RA
,
1195 &zero_address_frag
));
1196 symbol_table_insert (symbol_new ("$fp", reg_section
, FP
,
1197 &zero_address_frag
));
1198 symbol_table_insert (symbol_new ("$sp", reg_section
, SP
,
1199 &zero_address_frag
));
1200 symbol_table_insert (symbol_new ("$gp", reg_section
, GP
,
1201 &zero_address_frag
));
1202 symbol_table_insert (symbol_new ("$at", reg_section
, AT
,
1203 &zero_address_frag
));
1204 symbol_table_insert (symbol_new ("$kt0", reg_section
, KT0
,
1205 &zero_address_frag
));
1206 symbol_table_insert (symbol_new ("$kt1", reg_section
, KT1
,
1207 &zero_address_frag
));
1208 symbol_table_insert (symbol_new ("$zero", reg_section
, ZERO
,
1209 &zero_address_frag
));
1210 symbol_table_insert (symbol_new ("$pc", reg_section
, -1,
1211 &zero_address_frag
));
1213 /* If we don't add these register names to the symbol table, they
1214 may end up being added as regular symbols by operand(), and then
1215 make it to the object file as undefined in case they're not
1216 regarded as local symbols. They're local in o32, since `$' is a
1217 local symbol prefix, but not in n32 or n64. */
1218 for (i
= 0; i
< 8; i
++)
1222 sprintf (buf
, "$fcc%i", i
);
1223 symbol_table_insert (symbol_new (buf
, reg_section
, -1,
1224 &zero_address_frag
));
1227 mips_no_prev_insn (FALSE
);
1230 mips_cprmask
[0] = 0;
1231 mips_cprmask
[1] = 0;
1232 mips_cprmask
[2] = 0;
1233 mips_cprmask
[3] = 0;
1235 /* set the default alignment for the text section (2**2) */
1236 record_alignment (text_section
, 2);
1238 bfd_set_gp_size (stdoutput
, g_switch_value
);
1240 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
1242 /* On a native system, sections must be aligned to 16 byte
1243 boundaries. When configured for an embedded ELF target, we
1245 if (strcmp (TARGET_OS
, "elf") != 0)
1247 (void) bfd_set_section_alignment (stdoutput
, text_section
, 4);
1248 (void) bfd_set_section_alignment (stdoutput
, data_section
, 4);
1249 (void) bfd_set_section_alignment (stdoutput
, bss_section
, 4);
1252 /* Create a .reginfo section for register masks and a .mdebug
1253 section for debugging information. */
1261 subseg
= now_subseg
;
1263 /* The ABI says this section should be loaded so that the
1264 running program can access it. However, we don't load it
1265 if we are configured for an embedded target */
1266 flags
= SEC_READONLY
| SEC_DATA
;
1267 if (strcmp (TARGET_OS
, "elf") != 0)
1268 flags
|= SEC_ALLOC
| SEC_LOAD
;
1270 if (mips_abi
!= N64_ABI
)
1272 sec
= subseg_new (".reginfo", (subsegT
) 0);
1274 bfd_set_section_flags (stdoutput
, sec
, flags
);
1275 bfd_set_section_alignment (stdoutput
, sec
, HAVE_NEWABI
? 3 : 2);
1278 mips_regmask_frag
= frag_more (sizeof (Elf32_External_RegInfo
));
1283 /* The 64-bit ABI uses a .MIPS.options section rather than
1284 .reginfo section. */
1285 sec
= subseg_new (".MIPS.options", (subsegT
) 0);
1286 bfd_set_section_flags (stdoutput
, sec
, flags
);
1287 bfd_set_section_alignment (stdoutput
, sec
, 3);
1290 /* Set up the option header. */
1292 Elf_Internal_Options opthdr
;
1295 opthdr
.kind
= ODK_REGINFO
;
1296 opthdr
.size
= (sizeof (Elf_External_Options
)
1297 + sizeof (Elf64_External_RegInfo
));
1300 f
= frag_more (sizeof (Elf_External_Options
));
1301 bfd_mips_elf_swap_options_out (stdoutput
, &opthdr
,
1302 (Elf_External_Options
*) f
);
1304 mips_regmask_frag
= frag_more (sizeof (Elf64_External_RegInfo
));
1309 if (ECOFF_DEBUGGING
)
1311 sec
= subseg_new (".mdebug", (subsegT
) 0);
1312 (void) bfd_set_section_flags (stdoutput
, sec
,
1313 SEC_HAS_CONTENTS
| SEC_READONLY
);
1314 (void) bfd_set_section_alignment (stdoutput
, sec
, 2);
1317 else if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
&& mips_flag_pdr
)
1319 pdr_seg
= subseg_new (".pdr", (subsegT
) 0);
1320 (void) bfd_set_section_flags (stdoutput
, pdr_seg
,
1321 SEC_READONLY
| SEC_RELOC
1323 (void) bfd_set_section_alignment (stdoutput
, pdr_seg
, 2);
1327 subseg_set (seg
, subseg
);
1331 if (! ECOFF_DEBUGGING
)
1338 if (! ECOFF_DEBUGGING
)
1343 md_assemble (char *str
)
1345 struct mips_cl_insn insn
;
1346 bfd_reloc_code_real_type unused_reloc
[3]
1347 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
1349 imm_expr
.X_op
= O_absent
;
1350 imm2_expr
.X_op
= O_absent
;
1351 offset_expr
.X_op
= O_absent
;
1352 imm_reloc
[0] = BFD_RELOC_UNUSED
;
1353 imm_reloc
[1] = BFD_RELOC_UNUSED
;
1354 imm_reloc
[2] = BFD_RELOC_UNUSED
;
1355 offset_reloc
[0] = BFD_RELOC_UNUSED
;
1356 offset_reloc
[1] = BFD_RELOC_UNUSED
;
1357 offset_reloc
[2] = BFD_RELOC_UNUSED
;
1359 if (mips_opts
.mips16
)
1360 mips16_ip (str
, &insn
);
1363 mips_ip (str
, &insn
);
1364 DBG ((_("returned from mips_ip(%s) insn_opcode = 0x%x\n"),
1365 str
, insn
.insn_opcode
));
1370 as_bad ("%s `%s'", insn_error
, str
);
1374 if (insn
.insn_mo
->pinfo
== INSN_MACRO
)
1377 if (mips_opts
.mips16
)
1378 mips16_macro (&insn
);
1385 if (imm_expr
.X_op
!= O_absent
)
1386 append_insn (&insn
, &imm_expr
, imm_reloc
);
1387 else if (offset_expr
.X_op
!= O_absent
)
1388 append_insn (&insn
, &offset_expr
, offset_reloc
);
1390 append_insn (&insn
, NULL
, unused_reloc
);
1394 /* Return true if the given relocation might need a matching %lo().
1395 Note that R_MIPS_GOT16 relocations only need a matching %lo() when
1396 applied to local symbols. */
1398 static inline bfd_boolean
1399 reloc_needs_lo_p (bfd_reloc_code_real_type reloc
)
1401 return (reloc
== BFD_RELOC_HI16_S
1402 || reloc
== BFD_RELOC_MIPS_GOT16
);
1405 /* Return true if the given fixup is followed by a matching R_MIPS_LO16
1408 static inline bfd_boolean
1409 fixup_has_matching_lo_p (fixS
*fixp
)
1411 return (fixp
->fx_next
!= NULL
1412 && fixp
->fx_next
->fx_r_type
== BFD_RELOC_LO16
1413 && fixp
->fx_addsy
== fixp
->fx_next
->fx_addsy
1414 && fixp
->fx_offset
== fixp
->fx_next
->fx_offset
);
1417 /* See whether instruction IP reads register REG. CLASS is the type
1421 insn_uses_reg (struct mips_cl_insn
*ip
, unsigned int reg
,
1422 enum mips_regclass
class)
1424 if (class == MIPS16_REG
)
1426 assert (mips_opts
.mips16
);
1427 reg
= mips16_to_32_reg_map
[reg
];
1428 class = MIPS_GR_REG
;
1431 /* Don't report on general register ZERO, since it never changes. */
1432 if (class == MIPS_GR_REG
&& reg
== ZERO
)
1435 if (class == MIPS_FP_REG
)
1437 assert (! mips_opts
.mips16
);
1438 /* If we are called with either $f0 or $f1, we must check $f0.
1439 This is not optimal, because it will introduce an unnecessary
1440 NOP between "lwc1 $f0" and "swc1 $f1". To fix this we would
1441 need to distinguish reading both $f0 and $f1 or just one of
1442 them. Note that we don't have to check the other way,
1443 because there is no instruction that sets both $f0 and $f1
1444 and requires a delay. */
1445 if ((ip
->insn_mo
->pinfo
& INSN_READ_FPR_S
)
1446 && ((((ip
->insn_opcode
>> OP_SH_FS
) & OP_MASK_FS
) &~(unsigned)1)
1447 == (reg
&~ (unsigned) 1)))
1449 if ((ip
->insn_mo
->pinfo
& INSN_READ_FPR_T
)
1450 && ((((ip
->insn_opcode
>> OP_SH_FT
) & OP_MASK_FT
) &~(unsigned)1)
1451 == (reg
&~ (unsigned) 1)))
1454 else if (! mips_opts
.mips16
)
1456 if ((ip
->insn_mo
->pinfo
& INSN_READ_GPR_S
)
1457 && ((ip
->insn_opcode
>> OP_SH_RS
) & OP_MASK_RS
) == reg
)
1459 if ((ip
->insn_mo
->pinfo
& INSN_READ_GPR_T
)
1460 && ((ip
->insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
) == reg
)
1465 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_X
)
1466 && (mips16_to_32_reg_map
[((ip
->insn_opcode
>> MIPS16OP_SH_RX
)
1467 & MIPS16OP_MASK_RX
)]
1470 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_Y
)
1471 && (mips16_to_32_reg_map
[((ip
->insn_opcode
>> MIPS16OP_SH_RY
)
1472 & MIPS16OP_MASK_RY
)]
1475 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_Z
)
1476 && (mips16_to_32_reg_map
[((ip
->insn_opcode
>> MIPS16OP_SH_MOVE32Z
)
1477 & MIPS16OP_MASK_MOVE32Z
)]
1480 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_T
) && reg
== TREG
)
1482 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_SP
) && reg
== SP
)
1484 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_31
) && reg
== RA
)
1486 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_GPR_X
)
1487 && ((ip
->insn_opcode
>> MIPS16OP_SH_REGR32
)
1488 & MIPS16OP_MASK_REGR32
) == reg
)
1495 /* This function returns true if modifying a register requires a
1499 reg_needs_delay (unsigned int reg
)
1501 unsigned long prev_pinfo
;
1503 prev_pinfo
= prev_insn
.insn_mo
->pinfo
;
1504 if (! mips_opts
.noreorder
1505 && (((prev_pinfo
& INSN_LOAD_MEMORY_DELAY
)
1506 && ! gpr_interlocks
)
1507 || ((prev_pinfo
& INSN_LOAD_COPROC_DELAY
)
1508 && ! cop_interlocks
)))
1510 /* A load from a coprocessor or from memory. All load delays
1511 delay the use of general register rt for one instruction. */
1512 /* Itbl support may require additional care here. */
1513 know (prev_pinfo
& INSN_WRITE_GPR_T
);
1514 if (reg
== ((prev_insn
.insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
))
1521 /* Mark instruction labels in mips16 mode. This permits the linker to
1522 handle them specially, such as generating jalx instructions when
1523 needed. We also make them odd for the duration of the assembly, in
1524 order to generate the right sort of code. We will make them even
1525 in the adjust_symtab routine, while leaving them marked. This is
1526 convenient for the debugger and the disassembler. The linker knows
1527 to make them odd again. */
1530 mips16_mark_labels (void)
1532 if (mips_opts
.mips16
)
1534 struct insn_label_list
*l
;
1537 for (l
= insn_labels
; l
!= NULL
; l
= l
->next
)
1540 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
1541 S_SET_OTHER (l
->label
, STO_MIPS16
);
1543 val
= S_GET_VALUE (l
->label
);
1545 S_SET_VALUE (l
->label
, val
+ 1);
1550 /* End the current frag. Make it a variant frag and record the
1554 relax_close_frag (void)
1556 mips_macro_warning
.first_frag
= frag_now
;
1557 frag_var (rs_machine_dependent
, 0, 0,
1558 RELAX_ENCODE (mips_relax
.sizes
[0], mips_relax
.sizes
[1]),
1559 mips_relax
.symbol
, 0, (char *) mips_relax
.first_fixup
);
1561 memset (&mips_relax
.sizes
, 0, sizeof (mips_relax
.sizes
));
1562 mips_relax
.first_fixup
= 0;
1565 /* Start a new relaxation sequence whose expansion depends on SYMBOL.
1566 See the comment above RELAX_ENCODE for more details. */
1569 relax_start (symbolS
*symbol
)
1571 assert (mips_relax
.sequence
== 0);
1572 mips_relax
.sequence
= 1;
1573 mips_relax
.symbol
= symbol
;
1576 /* Start generating the second version of a relaxable sequence.
1577 See the comment above RELAX_ENCODE for more details. */
1582 assert (mips_relax
.sequence
== 1);
1583 mips_relax
.sequence
= 2;
1586 /* End the current relaxable sequence. */
1591 assert (mips_relax
.sequence
== 2);
1592 relax_close_frag ();
1593 mips_relax
.sequence
= 0;
1596 /* Output an instruction. IP is the instruction information.
1597 ADDRESS_EXPR is an operand of the instruction to be used with
1601 append_insn (struct mips_cl_insn
*ip
, expressionS
*address_expr
,
1602 bfd_reloc_code_real_type
*reloc_type
)
1604 register unsigned long prev_pinfo
, pinfo
;
1608 relax_stateT prev_insn_frag_type
= 0;
1609 bfd_boolean relaxed_branch
= FALSE
;
1610 bfd_boolean force_new_frag
= FALSE
;
1612 /* Mark instruction labels in mips16 mode. */
1613 mips16_mark_labels ();
1615 prev_pinfo
= prev_insn
.insn_mo
->pinfo
;
1616 pinfo
= ip
->insn_mo
->pinfo
;
1618 if (mips_relax
.sequence
!= 2
1619 && (!mips_opts
.noreorder
|| prev_nop_frag
!= NULL
))
1623 /* If the previous insn required any delay slots, see if we need
1624 to insert a NOP or two. There are eight kinds of possible
1625 hazards, of which an instruction can have at most one type.
1626 (1) a load from memory delay
1627 (2) a load from a coprocessor delay
1628 (3) an unconditional branch delay
1629 (4) a conditional branch delay
1630 (5) a move to coprocessor register delay
1631 (6) a load coprocessor register from memory delay
1632 (7) a coprocessor condition code delay
1633 (8) a HI/LO special register delay
1635 There are a lot of optimizations we could do that we don't.
1636 In particular, we do not, in general, reorder instructions.
1637 If you use gcc with optimization, it will reorder
1638 instructions and generally do much more optimization then we
1639 do here; repeating all that work in the assembler would only
1640 benefit hand written assembly code, and does not seem worth
1643 /* This is how a NOP is emitted. */
1644 #define emit_nop() \
1646 ? md_number_to_chars (frag_more (2), 0x6500, 2) \
1647 : md_number_to_chars (frag_more (4), 0, 4))
1649 /* The previous insn might require a delay slot, depending upon
1650 the contents of the current insn. */
1651 if (! mips_opts
.mips16
1652 && (((prev_pinfo
& INSN_LOAD_MEMORY_DELAY
)
1653 && ! gpr_interlocks
)
1654 || ((prev_pinfo
& INSN_LOAD_COPROC_DELAY
)
1655 && ! cop_interlocks
)))
1657 /* A load from a coprocessor or from memory. All load
1658 delays delay the use of general register rt for one
1660 /* Itbl support may require additional care here. */
1661 know (prev_pinfo
& INSN_WRITE_GPR_T
);
1662 if (mips_optimize
== 0
1663 || insn_uses_reg (ip
,
1664 ((prev_insn
.insn_opcode
>> OP_SH_RT
)
1669 else if (! mips_opts
.mips16
1670 && (((prev_pinfo
& INSN_COPROC_MOVE_DELAY
)
1671 && ! cop_interlocks
)
1672 || ((prev_pinfo
& INSN_COPROC_MEMORY_DELAY
)
1673 && ! cop_mem_interlocks
)))
1675 /* A generic coprocessor delay. The previous instruction
1676 modified a coprocessor general or control register. If
1677 it modified a control register, we need to avoid any
1678 coprocessor instruction (this is probably not always
1679 required, but it sometimes is). If it modified a general
1680 register, we avoid using that register.
1682 This case is not handled very well. There is no special
1683 knowledge of CP0 handling, and the coprocessors other
1684 than the floating point unit are not distinguished at
1686 /* Itbl support may require additional care here. FIXME!
1687 Need to modify this to include knowledge about
1688 user specified delays! */
1689 if (prev_pinfo
& INSN_WRITE_FPR_T
)
1691 if (mips_optimize
== 0
1692 || insn_uses_reg (ip
,
1693 ((prev_insn
.insn_opcode
>> OP_SH_FT
)
1698 else if (prev_pinfo
& INSN_WRITE_FPR_S
)
1700 if (mips_optimize
== 0
1701 || insn_uses_reg (ip
,
1702 ((prev_insn
.insn_opcode
>> OP_SH_FS
)
1709 /* We don't know exactly what the previous instruction
1710 does. If the current instruction uses a coprocessor
1711 register, we must insert a NOP. If previous
1712 instruction may set the condition codes, and the
1713 current instruction uses them, we must insert two
1715 /* Itbl support may require additional care here. */
1716 if (mips_optimize
== 0
1717 || ((prev_pinfo
& INSN_WRITE_COND_CODE
)
1718 && (pinfo
& INSN_READ_COND_CODE
)))
1720 else if (pinfo
& INSN_COP
)
1724 else if (! mips_opts
.mips16
1725 && (prev_pinfo
& INSN_WRITE_COND_CODE
)
1726 && ! cop_interlocks
)
1728 /* The previous instruction sets the coprocessor condition
1729 codes, but does not require a general coprocessor delay
1730 (this means it is a floating point comparison
1731 instruction). If this instruction uses the condition
1732 codes, we need to insert a single NOP. */
1733 /* Itbl support may require additional care here. */
1734 if (mips_optimize
== 0
1735 || (pinfo
& INSN_READ_COND_CODE
))
1739 /* If we're fixing up mfhi/mflo for the r7000 and the
1740 previous insn was an mfhi/mflo and the current insn
1741 reads the register that the mfhi/mflo wrote to, then
1744 else if (mips_7000_hilo_fix
1745 && MF_HILO_INSN (prev_pinfo
)
1746 && insn_uses_reg (ip
, ((prev_insn
.insn_opcode
>> OP_SH_RD
)
1753 /* If we're fixing up mfhi/mflo for the r7000 and the
1754 2nd previous insn was an mfhi/mflo and the current insn
1755 reads the register that the mfhi/mflo wrote to, then
1758 else if (mips_7000_hilo_fix
1759 && MF_HILO_INSN (prev_prev_insn
.insn_opcode
)
1760 && insn_uses_reg (ip
, ((prev_prev_insn
.insn_opcode
>> OP_SH_RD
)
1768 else if (prev_pinfo
& INSN_READ_LO
)
1770 /* The previous instruction reads the LO register; if the
1771 current instruction writes to the LO register, we must
1772 insert two NOPS. Some newer processors have interlocks.
1773 Also the tx39's multiply instructions can be executed
1774 immediately after a read from HI/LO (without the delay),
1775 though the tx39's divide insns still do require the
1777 if (! (hilo_interlocks
1778 || (mips_opts
.arch
== CPU_R3900
&& (pinfo
& INSN_MULT
)))
1779 && (mips_optimize
== 0
1780 || (pinfo
& INSN_WRITE_LO
)))
1782 /* Most mips16 branch insns don't have a delay slot.
1783 If a read from LO is immediately followed by a branch
1784 to a write to LO we have a read followed by a write
1785 less than 2 insns away. We assume the target of
1786 a branch might be a write to LO, and insert a nop
1787 between a read and an immediately following branch. */
1788 else if (mips_opts
.mips16
1789 && (mips_optimize
== 0
1790 || (pinfo
& MIPS16_INSN_BRANCH
)))
1793 else if (prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
1795 /* The previous instruction reads the HI register; if the
1796 current instruction writes to the HI register, we must
1797 insert a NOP. Some newer processors have interlocks.
1798 Also the note tx39's multiply above. */
1799 if (! (hilo_interlocks
1800 || (mips_opts
.arch
== CPU_R3900
&& (pinfo
& INSN_MULT
)))
1801 && (mips_optimize
== 0
1802 || (pinfo
& INSN_WRITE_HI
)))
1804 /* Most mips16 branch insns don't have a delay slot.
1805 If a read from HI is immediately followed by a branch
1806 to a write to HI we have a read followed by a write
1807 less than 2 insns away. We assume the target of
1808 a branch might be a write to HI, and insert a nop
1809 between a read and an immediately following branch. */
1810 else if (mips_opts
.mips16
1811 && (mips_optimize
== 0
1812 || (pinfo
& MIPS16_INSN_BRANCH
)))
1816 /* If the previous instruction was in a noreorder section, then
1817 we don't want to insert the nop after all. */
1818 /* Itbl support may require additional care here. */
1819 if (prev_insn_unreordered
)
1822 /* There are two cases which require two intervening
1823 instructions: 1) setting the condition codes using a move to
1824 coprocessor instruction which requires a general coprocessor
1825 delay and then reading the condition codes 2) reading the HI
1826 or LO register and then writing to it (except on processors
1827 which have interlocks). If we are not already emitting a NOP
1828 instruction, we must check for these cases compared to the
1829 instruction previous to the previous instruction. */
1830 if ((! mips_opts
.mips16
1831 && (prev_prev_insn
.insn_mo
->pinfo
& INSN_COPROC_MOVE_DELAY
)
1832 && (prev_prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
)
1833 && (pinfo
& INSN_READ_COND_CODE
)
1834 && ! cop_interlocks
)
1835 || ((prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
)
1836 && (pinfo
& INSN_WRITE_LO
)
1837 && ! (hilo_interlocks
1838 || (mips_opts
.arch
== CPU_R3900
&& (pinfo
& INSN_MULT
))))
1839 || ((prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
1840 && (pinfo
& INSN_WRITE_HI
)
1841 && ! (hilo_interlocks
1842 || (mips_opts
.arch
== CPU_R3900
&& (pinfo
& INSN_MULT
)))))
1847 if (prev_prev_insn_unreordered
)
1850 if (prev_prev_nop
&& nops
== 0)
1853 if (mips_fix_vr4120
&& prev_insn
.insn_mo
->name
)
1855 /* We're out of bits in pinfo, so we must resort to string
1856 ops here. Shortcuts are selected based on opcodes being
1857 limited to the VR4120 instruction set. */
1859 const char *pn
= prev_insn
.insn_mo
->name
;
1860 const char *tn
= ip
->insn_mo
->name
;
1861 if (strncmp (pn
, "macc", 4) == 0
1862 || strncmp (pn
, "dmacc", 5) == 0)
1864 /* Errata 21 - [D]DIV[U] after [D]MACC */
1865 if (strstr (tn
, "div"))
1868 /* VR4181A errata MD(1): "If a MULT, MULTU, DMULT or DMULTU
1869 instruction is executed immediately after a MACC or
1870 DMACC instruction, the result of [either instruction]
1872 if (strncmp (tn
, "mult", 4) == 0
1873 || strncmp (tn
, "dmult", 5) == 0)
1876 /* Errata 23 - Continuous DMULT[U]/DMACC instructions.
1877 Applies on top of VR4181A MD(1) errata. */
1878 if (pn
[0] == 'd' && strncmp (tn
, "dmacc", 5) == 0)
1881 /* Errata 24 - MT{LO,HI} after [D]MACC */
1882 if (strcmp (tn
, "mtlo") == 0
1883 || strcmp (tn
, "mthi") == 0)
1886 else if (strncmp (pn
, "dmult", 5) == 0
1887 && (strncmp (tn
, "dmult", 5) == 0
1888 || strncmp (tn
, "dmacc", 5) == 0))
1890 /* Here is the rest of errata 23. */
1893 else if ((strncmp (pn
, "dmult", 5) == 0 || strstr (pn
, "div"))
1894 && (strncmp (tn
, "macc", 4) == 0
1895 || strncmp (tn
, "dmacc", 5) == 0))
1897 /* VR4181A errata MD(4): "If a MACC or DMACC instruction is
1898 executed immediately after a DMULT, DMULTU, DIV, DIVU,
1899 DDIV or DDIVU instruction, the result of the MACC or
1900 DMACC instruction is incorrect.". This partly overlaps
1901 the workaround for errata 23. */
1904 if (nops
< min_nops
)
1908 /* If we are being given a nop instruction, don't bother with
1909 one of the nops we would otherwise output. This will only
1910 happen when a nop instruction is used with mips_optimize set
1913 && ! mips_opts
.noreorder
1914 && ip
->insn_opcode
== (unsigned) (mips_opts
.mips16
? 0x6500 : 0))
1917 /* Now emit the right number of NOP instructions. */
1918 if (nops
> 0 && ! mips_opts
.noreorder
)
1921 unsigned long old_frag_offset
;
1923 struct insn_label_list
*l
;
1925 old_frag
= frag_now
;
1926 old_frag_offset
= frag_now_fix ();
1928 for (i
= 0; i
< nops
; i
++)
1933 listing_prev_line ();
1934 /* We may be at the start of a variant frag. In case we
1935 are, make sure there is enough space for the frag
1936 after the frags created by listing_prev_line. The
1937 argument to frag_grow here must be at least as large
1938 as the argument to all other calls to frag_grow in
1939 this file. We don't have to worry about being in the
1940 middle of a variant frag, because the variants insert
1941 all needed nop instructions themselves. */
1945 for (l
= insn_labels
; l
!= NULL
; l
= l
->next
)
1949 assert (S_GET_SEGMENT (l
->label
) == now_seg
);
1950 symbol_set_frag (l
->label
, frag_now
);
1951 val
= (valueT
) frag_now_fix ();
1952 /* mips16 text labels are stored as odd. */
1953 if (mips_opts
.mips16
)
1955 S_SET_VALUE (l
->label
, val
);
1958 #ifndef NO_ECOFF_DEBUGGING
1959 if (ECOFF_DEBUGGING
)
1960 ecoff_fix_loc (old_frag
, old_frag_offset
);
1963 else if (prev_nop_frag
!= NULL
)
1965 /* We have a frag holding nops we may be able to remove. If
1966 we don't need any nops, we can decrease the size of
1967 prev_nop_frag by the size of one instruction. If we do
1968 need some nops, we count them in prev_nops_required. */
1969 if (prev_nop_frag_since
== 0)
1973 prev_nop_frag
->fr_fix
-= mips_opts
.mips16
? 2 : 4;
1974 --prev_nop_frag_holds
;
1977 prev_nop_frag_required
+= nops
;
1981 if (prev_prev_nop
== 0)
1983 prev_nop_frag
->fr_fix
-= mips_opts
.mips16
? 2 : 4;
1984 --prev_nop_frag_holds
;
1987 ++prev_nop_frag_required
;
1990 if (prev_nop_frag_holds
<= prev_nop_frag_required
)
1991 prev_nop_frag
= NULL
;
1993 ++prev_nop_frag_since
;
1995 /* Sanity check: by the time we reach the second instruction
1996 after prev_nop_frag, we should have used up all the nops
1997 one way or another. */
1998 assert (prev_nop_frag_since
<= 1 || prev_nop_frag
== NULL
);
2002 /* Record the frag type before frag_var. */
2004 prev_insn_frag_type
= prev_insn_frag
->fr_type
;
2007 && *reloc_type
== BFD_RELOC_16_PCREL_S2
2008 && (pinfo
& INSN_UNCOND_BRANCH_DELAY
|| pinfo
& INSN_COND_BRANCH_DELAY
2009 || pinfo
& INSN_COND_BRANCH_LIKELY
)
2010 && mips_relax_branch
2011 /* Don't try branch relaxation within .set nomacro, or within
2012 .set noat if we use $at for PIC computations. If it turns
2013 out that the branch was out-of-range, we'll get an error. */
2014 && !mips_opts
.warn_about_macros
2015 && !(mips_opts
.noat
&& mips_pic
!= NO_PIC
)
2016 && !mips_opts
.mips16
)
2018 relaxed_branch
= TRUE
;
2019 f
= frag_var (rs_machine_dependent
,
2020 relaxed_branch_length
2022 (pinfo
& INSN_UNCOND_BRANCH_DELAY
) ? -1
2023 : (pinfo
& INSN_COND_BRANCH_LIKELY
) ? 1 : 0), 4,
2025 (pinfo
& INSN_UNCOND_BRANCH_DELAY
,
2026 pinfo
& INSN_COND_BRANCH_LIKELY
,
2027 pinfo
& INSN_WRITE_GPR_31
,
2029 address_expr
->X_add_symbol
,
2030 address_expr
->X_add_number
,
2032 *reloc_type
= BFD_RELOC_UNUSED
;
2034 else if (*reloc_type
> BFD_RELOC_UNUSED
)
2036 /* We need to set up a variant frag. */
2037 assert (mips_opts
.mips16
&& address_expr
!= NULL
);
2038 f
= frag_var (rs_machine_dependent
, 4, 0,
2039 RELAX_MIPS16_ENCODE (*reloc_type
- BFD_RELOC_UNUSED
,
2040 mips16_small
, mips16_ext
,
2042 & INSN_UNCOND_BRANCH_DELAY
),
2043 (*prev_insn_reloc_type
2044 == BFD_RELOC_MIPS16_JMP
)),
2045 make_expr_symbol (address_expr
), 0, NULL
);
2047 else if (mips_opts
.mips16
2049 && *reloc_type
!= BFD_RELOC_MIPS16_JMP
)
2051 /* Make sure there is enough room to swap this instruction with
2052 a following jump instruction. */
2058 if (mips_opts
.mips16
2059 && mips_opts
.noreorder
2060 && (prev_pinfo
& INSN_UNCOND_BRANCH_DELAY
) != 0)
2061 as_warn (_("extended instruction in delay slot"));
2063 if (mips_relax
.sequence
)
2065 /* If we've reached the end of this frag, turn it into a variant
2066 frag and record the information for the instructions we've
2068 if (frag_room () < 4)
2069 relax_close_frag ();
2070 mips_relax
.sizes
[mips_relax
.sequence
- 1] += 4;
2073 if (mips_relax
.sequence
!= 2)
2074 mips_macro_warning
.sizes
[0] += 4;
2075 if (mips_relax
.sequence
!= 1)
2076 mips_macro_warning
.sizes
[1] += 4;
2081 fixp
[0] = fixp
[1] = fixp
[2] = NULL
;
2082 if (address_expr
!= NULL
&& *reloc_type
< BFD_RELOC_UNUSED
)
2084 if (address_expr
->X_op
== O_constant
)
2088 switch (*reloc_type
)
2091 ip
->insn_opcode
|= address_expr
->X_add_number
;
2094 case BFD_RELOC_MIPS_HIGHEST
:
2095 tmp
= (address_expr
->X_add_number
2096 + ((valueT
) 0x8000 << 32) + 0x80008000) >> 16;
2098 ip
->insn_opcode
|= (tmp
>> 16) & 0xffff;
2101 case BFD_RELOC_MIPS_HIGHER
:
2102 tmp
= (address_expr
->X_add_number
+ 0x80008000) >> 16;
2103 ip
->insn_opcode
|= (tmp
>> 16) & 0xffff;
2106 case BFD_RELOC_HI16_S
:
2107 ip
->insn_opcode
|= ((address_expr
->X_add_number
+ 0x8000)
2111 case BFD_RELOC_HI16
:
2112 ip
->insn_opcode
|= (address_expr
->X_add_number
>> 16) & 0xffff;
2115 case BFD_RELOC_LO16
:
2116 case BFD_RELOC_MIPS_GOT_DISP
:
2117 ip
->insn_opcode
|= address_expr
->X_add_number
& 0xffff;
2120 case BFD_RELOC_MIPS_JMP
:
2121 if ((address_expr
->X_add_number
& 3) != 0)
2122 as_bad (_("jump to misaligned address (0x%lx)"),
2123 (unsigned long) address_expr
->X_add_number
);
2124 if (address_expr
->X_add_number
& ~0xfffffff)
2125 as_bad (_("jump address range overflow (0x%lx)"),
2126 (unsigned long) address_expr
->X_add_number
);
2127 ip
->insn_opcode
|= (address_expr
->X_add_number
>> 2) & 0x3ffffff;
2130 case BFD_RELOC_MIPS16_JMP
:
2131 if ((address_expr
->X_add_number
& 3) != 0)
2132 as_bad (_("jump to misaligned address (0x%lx)"),
2133 (unsigned long) address_expr
->X_add_number
);
2134 if (address_expr
->X_add_number
& ~0xfffffff)
2135 as_bad (_("jump address range overflow (0x%lx)"),
2136 (unsigned long) address_expr
->X_add_number
);
2138 (((address_expr
->X_add_number
& 0x7c0000) << 3)
2139 | ((address_expr
->X_add_number
& 0xf800000) >> 7)
2140 | ((address_expr
->X_add_number
& 0x3fffc) >> 2));
2143 case BFD_RELOC_16_PCREL_S2
:
2153 reloc_howto_type
*howto
;
2156 /* In a compound relocation, it is the final (outermost)
2157 operator that determines the relocated field. */
2158 for (i
= 1; i
< 3; i
++)
2159 if (reloc_type
[i
] == BFD_RELOC_UNUSED
)
2162 howto
= bfd_reloc_type_lookup (stdoutput
, reloc_type
[i
- 1]);
2163 fixp
[0] = fix_new_exp (frag_now
, f
- frag_now
->fr_literal
,
2164 bfd_get_reloc_size(howto
),
2166 reloc_type
[0] == BFD_RELOC_16_PCREL_S2
,
2169 /* These relocations can have an addend that won't fit in
2170 4 octets for 64bit assembly. */
2172 && ! howto
->partial_inplace
2173 && (reloc_type
[0] == BFD_RELOC_16
2174 || reloc_type
[0] == BFD_RELOC_32
2175 || reloc_type
[0] == BFD_RELOC_MIPS_JMP
2176 || reloc_type
[0] == BFD_RELOC_HI16_S
2177 || reloc_type
[0] == BFD_RELOC_LO16
2178 || reloc_type
[0] == BFD_RELOC_GPREL16
2179 || reloc_type
[0] == BFD_RELOC_MIPS_LITERAL
2180 || reloc_type
[0] == BFD_RELOC_GPREL32
2181 || reloc_type
[0] == BFD_RELOC_64
2182 || reloc_type
[0] == BFD_RELOC_CTOR
2183 || reloc_type
[0] == BFD_RELOC_MIPS_SUB
2184 || reloc_type
[0] == BFD_RELOC_MIPS_HIGHEST
2185 || reloc_type
[0] == BFD_RELOC_MIPS_HIGHER
2186 || reloc_type
[0] == BFD_RELOC_MIPS_SCN_DISP
2187 || reloc_type
[0] == BFD_RELOC_MIPS_REL16
2188 || reloc_type
[0] == BFD_RELOC_MIPS_RELGOT
))
2189 fixp
[0]->fx_no_overflow
= 1;
2191 if (mips_relax
.sequence
)
2193 if (mips_relax
.first_fixup
== 0)
2194 mips_relax
.first_fixup
= fixp
[0];
2196 else if (reloc_needs_lo_p (*reloc_type
))
2198 struct mips_hi_fixup
*hi_fixup
;
2200 /* Reuse the last entry if it already has a matching %lo. */
2201 hi_fixup
= mips_hi_fixup_list
;
2203 || !fixup_has_matching_lo_p (hi_fixup
->fixp
))
2205 hi_fixup
= ((struct mips_hi_fixup
*)
2206 xmalloc (sizeof (struct mips_hi_fixup
)));
2207 hi_fixup
->next
= mips_hi_fixup_list
;
2208 mips_hi_fixup_list
= hi_fixup
;
2210 hi_fixup
->fixp
= fixp
[0];
2211 hi_fixup
->seg
= now_seg
;
2214 /* Add fixups for the second and third relocations, if given.
2215 Note that the ABI allows the second relocation to be
2216 against RSS_UNDEF, RSS_GP, RSS_GP0 or RSS_LOC. At the
2217 moment we only use RSS_UNDEF, but we could add support
2218 for the others if it ever becomes necessary. */
2219 for (i
= 1; i
< 3; i
++)
2220 if (reloc_type
[i
] != BFD_RELOC_UNUSED
)
2222 address_expr
->X_op
= O_absent
;
2223 address_expr
->X_add_symbol
= 0;
2224 address_expr
->X_add_number
= 0;
2226 fixp
[i
] = fix_new_exp (frag_now
, fixp
[0]->fx_where
,
2227 fixp
[0]->fx_size
, address_expr
,
2228 FALSE
, reloc_type
[i
]);
2233 if (! mips_opts
.mips16
)
2235 md_number_to_chars (f
, ip
->insn_opcode
, 4);
2237 dwarf2_emit_insn (4);
2240 else if (*reloc_type
== BFD_RELOC_MIPS16_JMP
)
2242 md_number_to_chars (f
, ip
->insn_opcode
>> 16, 2);
2243 md_number_to_chars (f
+ 2, ip
->insn_opcode
& 0xffff, 2);
2245 /* The value passed to dwarf2_emit_insn is the distance between
2246 the end of the current instruction and the address that should
2247 be recorded in the debug tables. Since we want to use ISA-encoded
2248 addresses in MIPS16 debug info, the value is one byte less than
2249 the real instruction length. */
2250 dwarf2_emit_insn (3);
2257 md_number_to_chars (f
, 0xf000 | ip
->extend
, 2);
2260 md_number_to_chars (f
, ip
->insn_opcode
, 2);
2262 dwarf2_emit_insn (ip
->use_extend
? 3 : 1);
2266 /* Update the register mask information. */
2267 if (! mips_opts
.mips16
)
2269 if (pinfo
& INSN_WRITE_GPR_D
)
2270 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
);
2271 if ((pinfo
& (INSN_WRITE_GPR_T
| INSN_READ_GPR_T
)) != 0)
2272 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
);
2273 if (pinfo
& INSN_READ_GPR_S
)
2274 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> OP_SH_RS
) & OP_MASK_RS
);
2275 if (pinfo
& INSN_WRITE_GPR_31
)
2276 mips_gprmask
|= 1 << RA
;
2277 if (pinfo
& INSN_WRITE_FPR_D
)
2278 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FD
) & OP_MASK_FD
);
2279 if ((pinfo
& (INSN_WRITE_FPR_S
| INSN_READ_FPR_S
)) != 0)
2280 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FS
) & OP_MASK_FS
);
2281 if ((pinfo
& (INSN_WRITE_FPR_T
| INSN_READ_FPR_T
)) != 0)
2282 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FT
) & OP_MASK_FT
);
2283 if ((pinfo
& INSN_READ_FPR_R
) != 0)
2284 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FR
) & OP_MASK_FR
);
2285 if (pinfo
& INSN_COP
)
2287 /* We don't keep enough information to sort these cases out.
2288 The itbl support does keep this information however, although
2289 we currently don't support itbl fprmats as part of the cop
2290 instruction. May want to add this support in the future. */
2292 /* Never set the bit for $0, which is always zero. */
2293 mips_gprmask
&= ~1 << 0;
2297 if (pinfo
& (MIPS16_INSN_WRITE_X
| MIPS16_INSN_READ_X
))
2298 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_RX
)
2299 & MIPS16OP_MASK_RX
);
2300 if (pinfo
& (MIPS16_INSN_WRITE_Y
| MIPS16_INSN_READ_Y
))
2301 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_RY
)
2302 & MIPS16OP_MASK_RY
);
2303 if (pinfo
& MIPS16_INSN_WRITE_Z
)
2304 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_RZ
)
2305 & MIPS16OP_MASK_RZ
);
2306 if (pinfo
& (MIPS16_INSN_WRITE_T
| MIPS16_INSN_READ_T
))
2307 mips_gprmask
|= 1 << TREG
;
2308 if (pinfo
& (MIPS16_INSN_WRITE_SP
| MIPS16_INSN_READ_SP
))
2309 mips_gprmask
|= 1 << SP
;
2310 if (pinfo
& (MIPS16_INSN_WRITE_31
| MIPS16_INSN_READ_31
))
2311 mips_gprmask
|= 1 << RA
;
2312 if (pinfo
& MIPS16_INSN_WRITE_GPR_Y
)
2313 mips_gprmask
|= 1 << MIPS16OP_EXTRACT_REG32R (ip
->insn_opcode
);
2314 if (pinfo
& MIPS16_INSN_READ_Z
)
2315 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_MOVE32Z
)
2316 & MIPS16OP_MASK_MOVE32Z
);
2317 if (pinfo
& MIPS16_INSN_READ_GPR_X
)
2318 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_REGR32
)
2319 & MIPS16OP_MASK_REGR32
);
2322 if (mips_relax
.sequence
!= 2 && !mips_opts
.noreorder
)
2324 /* Filling the branch delay slot is more complex. We try to
2325 switch the branch with the previous instruction, which we can
2326 do if the previous instruction does not set up a condition
2327 that the branch tests and if the branch is not itself the
2328 target of any branch. */
2329 if ((pinfo
& INSN_UNCOND_BRANCH_DELAY
)
2330 || (pinfo
& INSN_COND_BRANCH_DELAY
))
2332 if (mips_optimize
< 2
2333 /* If we have seen .set volatile or .set nomove, don't
2335 || mips_opts
.nomove
!= 0
2336 /* If we had to emit any NOP instructions, then we
2337 already know we can not swap. */
2339 /* If we don't even know the previous insn, we can not
2341 || ! prev_insn_valid
2342 /* If the previous insn is already in a branch delay
2343 slot, then we can not swap. */
2344 || prev_insn_is_delay_slot
2345 /* If the previous previous insn was in a .set
2346 noreorder, we can't swap. Actually, the MIPS
2347 assembler will swap in this situation. However, gcc
2348 configured -with-gnu-as will generate code like
2354 in which we can not swap the bne and INSN. If gcc is
2355 not configured -with-gnu-as, it does not output the
2356 .set pseudo-ops. We don't have to check
2357 prev_insn_unreordered, because prev_insn_valid will
2358 be 0 in that case. We don't want to use
2359 prev_prev_insn_valid, because we do want to be able
2360 to swap at the start of a function. */
2361 || prev_prev_insn_unreordered
2362 /* If the branch is itself the target of a branch, we
2363 can not swap. We cheat on this; all we check for is
2364 whether there is a label on this instruction. If
2365 there are any branches to anything other than a
2366 label, users must use .set noreorder. */
2367 || insn_labels
!= NULL
2368 /* If the previous instruction is in a variant frag
2369 other than this branch's one, we cannot do the swap.
2370 This does not apply to the mips16, which uses variant
2371 frags for different purposes. */
2372 || (! mips_opts
.mips16
2373 && prev_insn_frag_type
== rs_machine_dependent
)
2374 /* If the branch reads the condition codes, we don't
2375 even try to swap, because in the sequence
2380 we can not swap, and I don't feel like handling that
2382 || (! mips_opts
.mips16
2383 && (pinfo
& INSN_READ_COND_CODE
)
2384 && ! cop_interlocks
)
2385 /* We can not swap with an instruction that requires a
2386 delay slot, because the target of the branch might
2387 interfere with that instruction. */
2388 || (! mips_opts
.mips16
2390 /* Itbl support may require additional care here. */
2391 & (INSN_LOAD_COPROC_DELAY
2392 | INSN_COPROC_MOVE_DELAY
2393 | INSN_WRITE_COND_CODE
))
2394 && ! cop_interlocks
)
2395 || (! (hilo_interlocks
2396 || (mips_opts
.arch
== CPU_R3900
&& (pinfo
& INSN_MULT
)))
2400 || (! mips_opts
.mips16
2401 && (prev_pinfo
& INSN_LOAD_MEMORY_DELAY
)
2402 && ! gpr_interlocks
)
2403 || (! mips_opts
.mips16
2404 /* Itbl support may require additional care here. */
2405 && (prev_pinfo
& INSN_COPROC_MEMORY_DELAY
)
2406 && ! cop_mem_interlocks
)
2407 /* We can not swap with a branch instruction. */
2409 & (INSN_UNCOND_BRANCH_DELAY
2410 | INSN_COND_BRANCH_DELAY
2411 | INSN_COND_BRANCH_LIKELY
))
2412 /* We do not swap with a trap instruction, since it
2413 complicates trap handlers to have the trap
2414 instruction be in a delay slot. */
2415 || (prev_pinfo
& INSN_TRAP
)
2416 /* If the branch reads a register that the previous
2417 instruction sets, we can not swap. */
2418 || (! mips_opts
.mips16
2419 && (prev_pinfo
& INSN_WRITE_GPR_T
)
2420 && insn_uses_reg (ip
,
2421 ((prev_insn
.insn_opcode
>> OP_SH_RT
)
2424 || (! mips_opts
.mips16
2425 && (prev_pinfo
& INSN_WRITE_GPR_D
)
2426 && insn_uses_reg (ip
,
2427 ((prev_insn
.insn_opcode
>> OP_SH_RD
)
2430 || (mips_opts
.mips16
2431 && (((prev_pinfo
& MIPS16_INSN_WRITE_X
)
2432 && insn_uses_reg (ip
,
2433 ((prev_insn
.insn_opcode
2435 & MIPS16OP_MASK_RX
),
2437 || ((prev_pinfo
& MIPS16_INSN_WRITE_Y
)
2438 && insn_uses_reg (ip
,
2439 ((prev_insn
.insn_opcode
2441 & MIPS16OP_MASK_RY
),
2443 || ((prev_pinfo
& MIPS16_INSN_WRITE_Z
)
2444 && insn_uses_reg (ip
,
2445 ((prev_insn
.insn_opcode
2447 & MIPS16OP_MASK_RZ
),
2449 || ((prev_pinfo
& MIPS16_INSN_WRITE_T
)
2450 && insn_uses_reg (ip
, TREG
, MIPS_GR_REG
))
2451 || ((prev_pinfo
& MIPS16_INSN_WRITE_31
)
2452 && insn_uses_reg (ip
, RA
, MIPS_GR_REG
))
2453 || ((prev_pinfo
& MIPS16_INSN_WRITE_GPR_Y
)
2454 && insn_uses_reg (ip
,
2455 MIPS16OP_EXTRACT_REG32R (prev_insn
.
2458 /* If the branch writes a register that the previous
2459 instruction sets, we can not swap (we know that
2460 branches write only to RD or to $31). */
2461 || (! mips_opts
.mips16
2462 && (prev_pinfo
& INSN_WRITE_GPR_T
)
2463 && (((pinfo
& INSN_WRITE_GPR_D
)
2464 && (((prev_insn
.insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
)
2465 == ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)))
2466 || ((pinfo
& INSN_WRITE_GPR_31
)
2467 && (((prev_insn
.insn_opcode
>> OP_SH_RT
)
2470 || (! mips_opts
.mips16
2471 && (prev_pinfo
& INSN_WRITE_GPR_D
)
2472 && (((pinfo
& INSN_WRITE_GPR_D
)
2473 && (((prev_insn
.insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)
2474 == ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)))
2475 || ((pinfo
& INSN_WRITE_GPR_31
)
2476 && (((prev_insn
.insn_opcode
>> OP_SH_RD
)
2479 || (mips_opts
.mips16
2480 && (pinfo
& MIPS16_INSN_WRITE_31
)
2481 && ((prev_pinfo
& MIPS16_INSN_WRITE_31
)
2482 || ((prev_pinfo
& MIPS16_INSN_WRITE_GPR_Y
)
2483 && (MIPS16OP_EXTRACT_REG32R (prev_insn
.insn_opcode
)
2485 /* If the branch writes a register that the previous
2486 instruction reads, we can not swap (we know that
2487 branches only write to RD or to $31). */
2488 || (! mips_opts
.mips16
2489 && (pinfo
& INSN_WRITE_GPR_D
)
2490 && insn_uses_reg (&prev_insn
,
2491 ((ip
->insn_opcode
>> OP_SH_RD
)
2494 || (! mips_opts
.mips16
2495 && (pinfo
& INSN_WRITE_GPR_31
)
2496 && insn_uses_reg (&prev_insn
, RA
, MIPS_GR_REG
))
2497 || (mips_opts
.mips16
2498 && (pinfo
& MIPS16_INSN_WRITE_31
)
2499 && insn_uses_reg (&prev_insn
, RA
, MIPS_GR_REG
))
2500 /* If the previous previous instruction has a load
2501 delay, and sets a register that the branch reads, we
2503 || (! mips_opts
.mips16
2504 /* Itbl support may require additional care here. */
2505 && (((prev_prev_insn
.insn_mo
->pinfo
& INSN_LOAD_COPROC_DELAY
)
2506 && ! cop_interlocks
)
2507 || ((prev_prev_insn
.insn_mo
->pinfo
2508 & INSN_LOAD_MEMORY_DELAY
)
2509 && ! gpr_interlocks
))
2510 && insn_uses_reg (ip
,
2511 ((prev_prev_insn
.insn_opcode
>> OP_SH_RT
)
2514 /* If one instruction sets a condition code and the
2515 other one uses a condition code, we can not swap. */
2516 || ((pinfo
& INSN_READ_COND_CODE
)
2517 && (prev_pinfo
& INSN_WRITE_COND_CODE
))
2518 || ((pinfo
& INSN_WRITE_COND_CODE
)
2519 && (prev_pinfo
& INSN_READ_COND_CODE
))
2520 /* If the previous instruction uses the PC, we can not
2522 || (mips_opts
.mips16
2523 && (prev_pinfo
& MIPS16_INSN_READ_PC
))
2524 /* If the previous instruction was extended, we can not
2526 || (mips_opts
.mips16
&& prev_insn_extended
)
2527 /* If the previous instruction had a fixup in mips16
2528 mode, we can not swap. This normally means that the
2529 previous instruction was a 4 byte branch anyhow. */
2530 || (mips_opts
.mips16
&& prev_insn_fixp
[0])
2531 /* If the previous instruction is a sync, sync.l, or
2532 sync.p, we can not swap. */
2533 || (prev_pinfo
& INSN_SYNC
))
2535 /* We could do even better for unconditional branches to
2536 portions of this object file; we could pick up the
2537 instruction at the destination, put it in the delay
2538 slot, and bump the destination address. */
2540 /* Update the previous insn information. */
2541 prev_prev_insn
= *ip
;
2542 prev_insn
.insn_mo
= &dummy_opcode
;
2546 /* It looks like we can actually do the swap. */
2547 if (! mips_opts
.mips16
)
2552 prev_f
= prev_insn_frag
->fr_literal
+ prev_insn_where
;
2553 if (!relaxed_branch
)
2555 /* If this is not a relaxed branch, then just
2556 swap the instructions. */
2557 memcpy (temp
, prev_f
, 4);
2558 memcpy (prev_f
, f
, 4);
2559 memcpy (f
, temp
, 4);
2563 /* If this is a relaxed branch, then we move the
2564 instruction to be placed in the delay slot to
2565 the current frag, shrinking the fixed part of
2566 the originating frag. If the branch occupies
2567 the tail of the latter, we move it backwards,
2568 into the space freed by the moved instruction. */
2570 memcpy (f
, prev_f
, 4);
2571 prev_insn_frag
->fr_fix
-= 4;
2572 if (prev_insn_frag
->fr_type
== rs_machine_dependent
)
2573 memmove (prev_f
, prev_f
+ 4, prev_insn_frag
->fr_var
);
2576 if (prev_insn_fixp
[0])
2578 prev_insn_fixp
[0]->fx_frag
= frag_now
;
2579 prev_insn_fixp
[0]->fx_where
= f
- frag_now
->fr_literal
;
2581 if (prev_insn_fixp
[1])
2583 prev_insn_fixp
[1]->fx_frag
= frag_now
;
2584 prev_insn_fixp
[1]->fx_where
= f
- frag_now
->fr_literal
;
2586 if (prev_insn_fixp
[2])
2588 prev_insn_fixp
[2]->fx_frag
= frag_now
;
2589 prev_insn_fixp
[2]->fx_where
= f
- frag_now
->fr_literal
;
2591 if (prev_insn_fixp
[0] && HAVE_NEWABI
2592 && prev_insn_frag
!= frag_now
2593 && (prev_insn_fixp
[0]->fx_r_type
2594 == BFD_RELOC_MIPS_GOT_DISP
2595 || (prev_insn_fixp
[0]->fx_r_type
2596 == BFD_RELOC_MIPS_CALL16
)))
2598 /* To avoid confusion in tc_gen_reloc, we must
2599 ensure that this does not become a variant
2601 force_new_frag
= TRUE
;
2604 if (!relaxed_branch
)
2608 fixp
[0]->fx_frag
= prev_insn_frag
;
2609 fixp
[0]->fx_where
= prev_insn_where
;
2613 fixp
[1]->fx_frag
= prev_insn_frag
;
2614 fixp
[1]->fx_where
= prev_insn_where
;
2618 fixp
[2]->fx_frag
= prev_insn_frag
;
2619 fixp
[2]->fx_where
= prev_insn_where
;
2622 else if (prev_insn_frag
->fr_type
== rs_machine_dependent
)
2625 fixp
[0]->fx_where
-= 4;
2627 fixp
[1]->fx_where
-= 4;
2629 fixp
[2]->fx_where
-= 4;
2637 assert (prev_insn_fixp
[0] == NULL
);
2638 assert (prev_insn_fixp
[1] == NULL
);
2639 assert (prev_insn_fixp
[2] == NULL
);
2640 prev_f
= prev_insn_frag
->fr_literal
+ prev_insn_where
;
2641 memcpy (temp
, prev_f
, 2);
2642 memcpy (prev_f
, f
, 2);
2643 if (*reloc_type
!= BFD_RELOC_MIPS16_JMP
)
2645 assert (*reloc_type
== BFD_RELOC_UNUSED
);
2646 memcpy (f
, temp
, 2);
2650 memcpy (f
, f
+ 2, 2);
2651 memcpy (f
+ 2, temp
, 2);
2655 fixp
[0]->fx_frag
= prev_insn_frag
;
2656 fixp
[0]->fx_where
= prev_insn_where
;
2660 fixp
[1]->fx_frag
= prev_insn_frag
;
2661 fixp
[1]->fx_where
= prev_insn_where
;
2665 fixp
[2]->fx_frag
= prev_insn_frag
;
2666 fixp
[2]->fx_where
= prev_insn_where
;
2670 /* Update the previous insn information; leave prev_insn
2672 prev_prev_insn
= *ip
;
2674 prev_insn_is_delay_slot
= 1;
2676 /* If that was an unconditional branch, forget the previous
2677 insn information. */
2678 if (pinfo
& INSN_UNCOND_BRANCH_DELAY
)
2680 prev_prev_insn
.insn_mo
= &dummy_opcode
;
2681 prev_insn
.insn_mo
= &dummy_opcode
;
2684 prev_insn_fixp
[0] = NULL
;
2685 prev_insn_fixp
[1] = NULL
;
2686 prev_insn_fixp
[2] = NULL
;
2687 prev_insn_reloc_type
[0] = BFD_RELOC_UNUSED
;
2688 prev_insn_reloc_type
[1] = BFD_RELOC_UNUSED
;
2689 prev_insn_reloc_type
[2] = BFD_RELOC_UNUSED
;
2690 prev_insn_extended
= 0;
2692 else if (pinfo
& INSN_COND_BRANCH_LIKELY
)
2694 /* We don't yet optimize a branch likely. What we should do
2695 is look at the target, copy the instruction found there
2696 into the delay slot, and increment the branch to jump to
2697 the next instruction. */
2699 /* Update the previous insn information. */
2700 prev_prev_insn
= *ip
;
2701 prev_insn
.insn_mo
= &dummy_opcode
;
2702 prev_insn_fixp
[0] = NULL
;
2703 prev_insn_fixp
[1] = NULL
;
2704 prev_insn_fixp
[2] = NULL
;
2705 prev_insn_reloc_type
[0] = BFD_RELOC_UNUSED
;
2706 prev_insn_reloc_type
[1] = BFD_RELOC_UNUSED
;
2707 prev_insn_reloc_type
[2] = BFD_RELOC_UNUSED
;
2708 prev_insn_extended
= 0;
2712 /* Update the previous insn information. */
2714 prev_prev_insn
.insn_mo
= &dummy_opcode
;
2716 prev_prev_insn
= prev_insn
;
2719 /* Any time we see a branch, we always fill the delay slot
2720 immediately; since this insn is not a branch, we know it
2721 is not in a delay slot. */
2722 prev_insn_is_delay_slot
= 0;
2724 prev_insn_fixp
[0] = fixp
[0];
2725 prev_insn_fixp
[1] = fixp
[1];
2726 prev_insn_fixp
[2] = fixp
[2];
2727 prev_insn_reloc_type
[0] = reloc_type
[0];
2728 prev_insn_reloc_type
[1] = reloc_type
[1];
2729 prev_insn_reloc_type
[2] = reloc_type
[2];
2730 if (mips_opts
.mips16
)
2731 prev_insn_extended
= (ip
->use_extend
2732 || *reloc_type
> BFD_RELOC_UNUSED
);
2735 prev_prev_insn_unreordered
= prev_insn_unreordered
;
2736 prev_insn_unreordered
= 0;
2737 prev_insn_frag
= frag_now
;
2738 prev_insn_where
= f
- frag_now
->fr_literal
;
2739 prev_insn_valid
= 1;
2741 else if (mips_relax
.sequence
!= 2)
2743 /* We need to record a bit of information even when we are not
2744 reordering, in order to determine the base address for mips16
2745 PC relative relocs. */
2746 prev_prev_insn
= prev_insn
;
2748 prev_insn_reloc_type
[0] = reloc_type
[0];
2749 prev_insn_reloc_type
[1] = reloc_type
[1];
2750 prev_insn_reloc_type
[2] = reloc_type
[2];
2751 prev_prev_insn_unreordered
= prev_insn_unreordered
;
2752 prev_insn_unreordered
= 1;
2755 /* We just output an insn, so the next one doesn't have a label. */
2756 mips_clear_insn_labels ();
2759 /* This function forgets that there was any previous instruction or
2760 label. If PRESERVE is non-zero, it remembers enough information to
2761 know whether nops are needed before a noreorder section. */
2764 mips_no_prev_insn (int preserve
)
2768 prev_insn
.insn_mo
= &dummy_opcode
;
2769 prev_prev_insn
.insn_mo
= &dummy_opcode
;
2770 prev_nop_frag
= NULL
;
2771 prev_nop_frag_holds
= 0;
2772 prev_nop_frag_required
= 0;
2773 prev_nop_frag_since
= 0;
2775 prev_insn_valid
= 0;
2776 prev_insn_is_delay_slot
= 0;
2777 prev_insn_unreordered
= 0;
2778 prev_insn_extended
= 0;
2779 prev_insn_reloc_type
[0] = BFD_RELOC_UNUSED
;
2780 prev_insn_reloc_type
[1] = BFD_RELOC_UNUSED
;
2781 prev_insn_reloc_type
[2] = BFD_RELOC_UNUSED
;
2782 prev_prev_insn_unreordered
= 0;
2783 mips_clear_insn_labels ();
2786 /* This function must be called whenever we turn on noreorder or emit
2787 something other than instructions. It inserts any NOPS which might
2788 be needed by the previous instruction, and clears the information
2789 kept for the previous instructions. The INSNS parameter is true if
2790 instructions are to follow. */
2793 mips_emit_delays (bfd_boolean insns
)
2795 if (! mips_opts
.noreorder
)
2800 if ((! mips_opts
.mips16
2801 && ((prev_insn
.insn_mo
->pinfo
2802 & (INSN_LOAD_COPROC_DELAY
2803 | INSN_COPROC_MOVE_DELAY
2804 | INSN_WRITE_COND_CODE
))
2805 && ! cop_interlocks
))
2806 || (! hilo_interlocks
2807 && (prev_insn
.insn_mo
->pinfo
2810 || (! mips_opts
.mips16
2811 && (prev_insn
.insn_mo
->pinfo
& INSN_LOAD_MEMORY_DELAY
)
2812 && ! gpr_interlocks
)
2813 || (! mips_opts
.mips16
2814 && (prev_insn
.insn_mo
->pinfo
& INSN_COPROC_MEMORY_DELAY
)
2815 && ! cop_mem_interlocks
))
2817 /* Itbl support may require additional care here. */
2819 if ((! mips_opts
.mips16
2820 && ((prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
)
2821 && ! cop_interlocks
))
2822 || (! hilo_interlocks
2823 && ((prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
2824 || (prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
))))
2827 if (prev_insn_unreordered
)
2830 else if ((! mips_opts
.mips16
2831 && ((prev_prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
)
2832 && ! cop_interlocks
))
2833 || (! hilo_interlocks
2834 && ((prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
2835 || (prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
))))
2837 /* Itbl support may require additional care here. */
2838 if (! prev_prev_insn_unreordered
)
2842 if (mips_fix_vr4120
&& prev_insn
.insn_mo
->name
)
2845 const char *pn
= prev_insn
.insn_mo
->name
;
2846 if (strncmp (pn
, "macc", 4) == 0
2847 || strncmp (pn
, "dmacc", 5) == 0
2848 || strncmp (pn
, "dmult", 5) == 0
2849 || strstr (pn
, "div"))
2851 if (nops
< min_nops
)
2857 struct insn_label_list
*l
;
2861 /* Record the frag which holds the nop instructions, so
2862 that we can remove them if we don't need them. */
2863 frag_grow (mips_opts
.mips16
? nops
* 2 : nops
* 4);
2864 prev_nop_frag
= frag_now
;
2865 prev_nop_frag_holds
= nops
;
2866 prev_nop_frag_required
= 0;
2867 prev_nop_frag_since
= 0;
2870 for (; nops
> 0; --nops
)
2875 /* Move on to a new frag, so that it is safe to simply
2876 decrease the size of prev_nop_frag. */
2877 frag_wane (frag_now
);
2881 for (l
= insn_labels
; l
!= NULL
; l
= l
->next
)
2885 assert (S_GET_SEGMENT (l
->label
) == now_seg
);
2886 symbol_set_frag (l
->label
, frag_now
);
2887 val
= (valueT
) frag_now_fix ();
2888 /* mips16 text labels are stored as odd. */
2889 if (mips_opts
.mips16
)
2891 S_SET_VALUE (l
->label
, val
);
2896 /* Mark instruction labels in mips16 mode. */
2898 mips16_mark_labels ();
2900 mips_no_prev_insn (insns
);
2903 /* Set up global variables for the start of a new macro. */
2908 memset (&mips_macro_warning
.sizes
, 0, sizeof (mips_macro_warning
.sizes
));
2909 mips_macro_warning
.delay_slot_p
= (mips_opts
.noreorder
2910 && (prev_insn
.insn_mo
->pinfo
2911 & (INSN_UNCOND_BRANCH_DELAY
2912 | INSN_COND_BRANCH_DELAY
2913 | INSN_COND_BRANCH_LIKELY
)) != 0);
2916 /* Given that a macro is longer than 4 bytes, return the appropriate warning
2917 for it. Return null if no warning is needed. SUBTYPE is a bitmask of
2918 RELAX_DELAY_SLOT and RELAX_NOMACRO. */
2921 macro_warning (relax_substateT subtype
)
2923 if (subtype
& RELAX_DELAY_SLOT
)
2924 return _("Macro instruction expanded into multiple instructions"
2925 " in a branch delay slot");
2926 else if (subtype
& RELAX_NOMACRO
)
2927 return _("Macro instruction expanded into multiple instructions");
2932 /* Finish up a macro. Emit warnings as appropriate. */
2937 if (mips_macro_warning
.sizes
[0] > 4 || mips_macro_warning
.sizes
[1] > 4)
2939 relax_substateT subtype
;
2941 /* Set up the relaxation warning flags. */
2943 if (mips_macro_warning
.sizes
[1] > mips_macro_warning
.sizes
[0])
2944 subtype
|= RELAX_SECOND_LONGER
;
2945 if (mips_opts
.warn_about_macros
)
2946 subtype
|= RELAX_NOMACRO
;
2947 if (mips_macro_warning
.delay_slot_p
)
2948 subtype
|= RELAX_DELAY_SLOT
;
2950 if (mips_macro_warning
.sizes
[0] > 4 && mips_macro_warning
.sizes
[1] > 4)
2952 /* Either the macro has a single implementation or both
2953 implementations are longer than 4 bytes. Emit the
2955 const char *msg
= macro_warning (subtype
);
2961 /* One implementation might need a warning but the other
2962 definitely doesn't. */
2963 mips_macro_warning
.first_frag
->fr_subtype
|= subtype
;
2968 /* Build an instruction created by a macro expansion. This is passed
2969 a pointer to the count of instructions created so far, an
2970 expression, the name of the instruction to build, an operand format
2971 string, and corresponding arguments. */
2974 macro_build (expressionS
*ep
, const char *name
, const char *fmt
, ...)
2976 struct mips_cl_insn insn
;
2977 bfd_reloc_code_real_type r
[3];
2980 va_start (args
, fmt
);
2982 if (mips_opts
.mips16
)
2984 mips16_macro_build (ep
, name
, fmt
, args
);
2989 r
[0] = BFD_RELOC_UNUSED
;
2990 r
[1] = BFD_RELOC_UNUSED
;
2991 r
[2] = BFD_RELOC_UNUSED
;
2992 insn
.insn_mo
= (struct mips_opcode
*) hash_find (op_hash
, name
);
2993 assert (insn
.insn_mo
);
2994 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
2996 /* Search until we get a match for NAME. */
2999 /* It is assumed here that macros will never generate
3000 MDMX or MIPS-3D instructions. */
3001 if (strcmp (fmt
, insn
.insn_mo
->args
) == 0
3002 && insn
.insn_mo
->pinfo
!= INSN_MACRO
3003 && OPCODE_IS_MEMBER (insn
.insn_mo
,
3005 | (file_ase_mips16
? INSN_MIPS16
: 0)),
3007 && (mips_opts
.arch
!= CPU_R4650
|| (insn
.insn_mo
->pinfo
& FP_D
) == 0))
3011 assert (insn
.insn_mo
->name
);
3012 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
3015 insn
.insn_opcode
= insn
.insn_mo
->match
;
3033 insn
.insn_opcode
|= (va_arg (args
, int)
3034 & OP_MASK_SHAMT
) << OP_SH_SHAMT
;
3039 /* Note that in the macro case, these arguments are already
3040 in MSB form. (When handling the instruction in the
3041 non-macro case, these arguments are sizes from which
3042 MSB values must be calculated.) */
3043 insn
.insn_opcode
|= (va_arg (args
, int)
3044 & OP_MASK_INSMSB
) << OP_SH_INSMSB
;
3050 /* Note that in the macro case, these arguments are already
3051 in MSBD form. (When handling the instruction in the
3052 non-macro case, these arguments are sizes from which
3053 MSBD values must be calculated.) */
3054 insn
.insn_opcode
|= (va_arg (args
, int)
3055 & OP_MASK_EXTMSBD
) << OP_SH_EXTMSBD
;
3066 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_RT
;
3070 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_CODE
;
3075 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_FT
;
3081 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_RD
;
3086 int tmp
= va_arg (args
, int);
3088 insn
.insn_opcode
|= tmp
<< OP_SH_RT
;
3089 insn
.insn_opcode
|= tmp
<< OP_SH_RD
;
3095 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_FS
;
3102 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_SHAMT
;
3106 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_FD
;
3110 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_CODE20
;
3114 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_CODE19
;
3118 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_CODE2
;
3125 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_RS
;
3131 *r
= (bfd_reloc_code_real_type
) va_arg (args
, int);
3132 assert (*r
== BFD_RELOC_GPREL16
3133 || *r
== BFD_RELOC_MIPS_LITERAL
3134 || *r
== BFD_RELOC_MIPS_HIGHER
3135 || *r
== BFD_RELOC_HI16_S
3136 || *r
== BFD_RELOC_LO16
3137 || *r
== BFD_RELOC_MIPS_GOT16
3138 || *r
== BFD_RELOC_MIPS_CALL16
3139 || *r
== BFD_RELOC_MIPS_GOT_DISP
3140 || *r
== BFD_RELOC_MIPS_GOT_PAGE
3141 || *r
== BFD_RELOC_MIPS_GOT_OFST
3142 || *r
== BFD_RELOC_MIPS_GOT_LO16
3143 || *r
== BFD_RELOC_MIPS_CALL_LO16
);
3147 *r
= (bfd_reloc_code_real_type
) va_arg (args
, int);
3149 && (ep
->X_op
== O_constant
3150 || (ep
->X_op
== O_symbol
3151 && (*r
== BFD_RELOC_MIPS_HIGHEST
3152 || *r
== BFD_RELOC_HI16_S
3153 || *r
== BFD_RELOC_HI16
3154 || *r
== BFD_RELOC_GPREL16
3155 || *r
== BFD_RELOC_MIPS_GOT_HI16
3156 || *r
== BFD_RELOC_MIPS_CALL_HI16
))));
3160 assert (ep
!= NULL
);
3162 * This allows macro() to pass an immediate expression for
3163 * creating short branches without creating a symbol.
3164 * Note that the expression still might come from the assembly
3165 * input, in which case the value is not checked for range nor
3166 * is a relocation entry generated (yuck).
3168 if (ep
->X_op
== O_constant
)
3170 insn
.insn_opcode
|= (ep
->X_add_number
>> 2) & 0xffff;
3174 *r
= BFD_RELOC_16_PCREL_S2
;
3178 assert (ep
!= NULL
);
3179 *r
= BFD_RELOC_MIPS_JMP
;
3183 insn
.insn_opcode
|= va_arg (args
, unsigned long);
3192 assert (*r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
3194 append_insn (&insn
, ep
, r
);
3198 mips16_macro_build (expressionS
*ep
, const char *name
, const char *fmt
,
3201 struct mips_cl_insn insn
;
3202 bfd_reloc_code_real_type r
[3]
3203 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
3205 insn
.insn_mo
= (struct mips_opcode
*) hash_find (mips16_op_hash
, name
);
3206 assert (insn
.insn_mo
);
3207 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
3209 while (strcmp (fmt
, insn
.insn_mo
->args
) != 0
3210 || insn
.insn_mo
->pinfo
== INSN_MACRO
)
3213 assert (insn
.insn_mo
->name
);
3214 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
3217 insn
.insn_opcode
= insn
.insn_mo
->match
;
3218 insn
.use_extend
= FALSE
;
3237 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_RY
;
3242 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_RX
;
3246 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_RZ
;
3250 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_MOVE32Z
;
3260 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_REGR32
;
3267 regno
= va_arg (args
, int);
3268 regno
= ((regno
& 7) << 2) | ((regno
& 0x18) >> 3);
3269 insn
.insn_opcode
|= regno
<< MIPS16OP_SH_REG32R
;
3290 assert (ep
!= NULL
);
3292 if (ep
->X_op
!= O_constant
)
3293 *r
= (int) BFD_RELOC_UNUSED
+ c
;
3296 mips16_immed (NULL
, 0, c
, ep
->X_add_number
, FALSE
, FALSE
,
3297 FALSE
, &insn
.insn_opcode
, &insn
.use_extend
,
3300 *r
= BFD_RELOC_UNUSED
;
3306 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_IMM6
;
3313 assert (*r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
3315 append_insn (&insn
, ep
, r
);
3319 * Generate a "jalr" instruction with a relocation hint to the called
3320 * function. This occurs in NewABI PIC code.
3323 macro_build_jalr (expressionS
*ep
)
3332 macro_build (NULL
, "jalr", "d,s", RA
, PIC_CALL_REG
);
3334 fix_new_exp (frag_now
, f
- frag_now
->fr_literal
,
3335 4, ep
, FALSE
, BFD_RELOC_MIPS_JALR
);
3339 * Generate a "lui" instruction.
3342 macro_build_lui (expressionS
*ep
, int regnum
)
3344 expressionS high_expr
;
3345 struct mips_cl_insn insn
;
3346 bfd_reloc_code_real_type r
[3]
3347 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
3348 const char *name
= "lui";
3349 const char *fmt
= "t,u";
3351 assert (! mips_opts
.mips16
);
3355 if (high_expr
.X_op
== O_constant
)
3357 /* we can compute the instruction now without a relocation entry */
3358 high_expr
.X_add_number
= ((high_expr
.X_add_number
+ 0x8000)
3360 *r
= BFD_RELOC_UNUSED
;
3364 assert (ep
->X_op
== O_symbol
);
3365 /* _gp_disp is a special case, used from s_cpload. */
3366 assert (mips_pic
== NO_PIC
3368 && strcmp (S_GET_NAME (ep
->X_add_symbol
), "_gp_disp") == 0));
3369 *r
= BFD_RELOC_HI16_S
;
3372 insn
.insn_mo
= (struct mips_opcode
*) hash_find (op_hash
, name
);
3373 assert (insn
.insn_mo
);
3374 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
3375 assert (strcmp (fmt
, insn
.insn_mo
->args
) == 0);
3377 insn
.insn_opcode
= insn
.insn_mo
->match
| (regnum
<< OP_SH_RT
);
3378 if (*r
== BFD_RELOC_UNUSED
)
3380 insn
.insn_opcode
|= high_expr
.X_add_number
;
3381 append_insn (&insn
, NULL
, r
);
3384 append_insn (&insn
, &high_expr
, r
);
3387 /* Generate a sequence of instructions to do a load or store from a constant
3388 offset off of a base register (breg) into/from a target register (treg),
3389 using AT if necessary. */
3391 macro_build_ldst_constoffset (expressionS
*ep
, const char *op
,
3392 int treg
, int breg
, int dbl
)
3394 assert (ep
->X_op
== O_constant
);
3396 /* Sign-extending 32-bit constants makes their handling easier. */
3397 if (! dbl
&& ! ((ep
->X_add_number
& ~((bfd_vma
) 0x7fffffff))
3398 == ~((bfd_vma
) 0x7fffffff)))
3400 if (ep
->X_add_number
& ~((bfd_vma
) 0xffffffff))
3401 as_bad (_("constant too large"));
3403 ep
->X_add_number
= (((ep
->X_add_number
& 0xffffffff) ^ 0x80000000)
3407 /* Right now, this routine can only handle signed 32-bit constants. */
3408 if (! IS_SEXT_32BIT_NUM(ep
->X_add_number
+ 0x8000))
3409 as_warn (_("operand overflow"));
3411 if (IS_SEXT_16BIT_NUM(ep
->X_add_number
))
3413 /* Signed 16-bit offset will fit in the op. Easy! */
3414 macro_build (ep
, op
, "t,o(b)", treg
, BFD_RELOC_LO16
, breg
);
3418 /* 32-bit offset, need multiple instructions and AT, like:
3419 lui $tempreg,const_hi (BFD_RELOC_HI16_S)
3420 addu $tempreg,$tempreg,$breg
3421 <op> $treg,const_lo($tempreg) (BFD_RELOC_LO16)
3422 to handle the complete offset. */
3423 macro_build_lui (ep
, AT
);
3424 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, AT
, breg
);
3425 macro_build (ep
, op
, "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
3428 as_warn (_("Macro used $at after \".set noat\""));
3433 * Generates code to set the $at register to true (one)
3434 * if reg is less than the immediate expression.
3437 set_at (int reg
, int unsignedp
)
3439 if (imm_expr
.X_op
== O_constant
3440 && imm_expr
.X_add_number
>= -0x8000
3441 && imm_expr
.X_add_number
< 0x8000)
3442 macro_build (&imm_expr
, unsignedp
? "sltiu" : "slti", "t,r,j",
3443 AT
, reg
, BFD_RELOC_LO16
);
3446 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
3447 macro_build (NULL
, unsignedp
? "sltu" : "slt", "d,v,t", AT
, reg
, AT
);
3452 normalize_constant_expr (expressionS
*ex
)
3454 if (ex
->X_op
== O_constant
&& HAVE_32BIT_GPRS
)
3455 ex
->X_add_number
= (((ex
->X_add_number
& 0xffffffff) ^ 0x80000000)
3459 /* Warn if an expression is not a constant. */
3462 check_absolute_expr (struct mips_cl_insn
*ip
, expressionS
*ex
)
3464 if (ex
->X_op
== O_big
)
3465 as_bad (_("unsupported large constant"));
3466 else if (ex
->X_op
!= O_constant
)
3467 as_bad (_("Instruction %s requires absolute expression"), ip
->insn_mo
->name
);
3469 normalize_constant_expr (ex
);
3472 /* Count the leading zeroes by performing a binary chop. This is a
3473 bulky bit of source, but performance is a LOT better for the
3474 majority of values than a simple loop to count the bits:
3475 for (lcnt = 0; (lcnt < 32); lcnt++)
3476 if ((v) & (1 << (31 - lcnt)))
3478 However it is not code size friendly, and the gain will drop a bit
3479 on certain cached systems.
3481 #define COUNT_TOP_ZEROES(v) \
3482 (((v) & ~0xffff) == 0 \
3483 ? ((v) & ~0xff) == 0 \
3484 ? ((v) & ~0xf) == 0 \
3485 ? ((v) & ~0x3) == 0 \
3486 ? ((v) & ~0x1) == 0 \
3491 : ((v) & ~0x7) == 0 \
3494 : ((v) & ~0x3f) == 0 \
3495 ? ((v) & ~0x1f) == 0 \
3498 : ((v) & ~0x7f) == 0 \
3501 : ((v) & ~0xfff) == 0 \
3502 ? ((v) & ~0x3ff) == 0 \
3503 ? ((v) & ~0x1ff) == 0 \
3506 : ((v) & ~0x7ff) == 0 \
3509 : ((v) & ~0x3fff) == 0 \
3510 ? ((v) & ~0x1fff) == 0 \
3513 : ((v) & ~0x7fff) == 0 \
3516 : ((v) & ~0xffffff) == 0 \
3517 ? ((v) & ~0xfffff) == 0 \
3518 ? ((v) & ~0x3ffff) == 0 \
3519 ? ((v) & ~0x1ffff) == 0 \
3522 : ((v) & ~0x7ffff) == 0 \
3525 : ((v) & ~0x3fffff) == 0 \
3526 ? ((v) & ~0x1fffff) == 0 \
3529 : ((v) & ~0x7fffff) == 0 \
3532 : ((v) & ~0xfffffff) == 0 \
3533 ? ((v) & ~0x3ffffff) == 0 \
3534 ? ((v) & ~0x1ffffff) == 0 \
3537 : ((v) & ~0x7ffffff) == 0 \
3540 : ((v) & ~0x3fffffff) == 0 \
3541 ? ((v) & ~0x1fffffff) == 0 \
3544 : ((v) & ~0x7fffffff) == 0 \
3549 * This routine generates the least number of instructions necessary to load
3550 * an absolute expression value into a register.
3553 load_register (int reg
, expressionS
*ep
, int dbl
)
3556 expressionS hi32
, lo32
;
3558 if (ep
->X_op
!= O_big
)
3560 assert (ep
->X_op
== O_constant
);
3562 /* Sign-extending 32-bit constants makes their handling easier. */
3563 if (! dbl
&& ! ((ep
->X_add_number
& ~((bfd_vma
) 0x7fffffff))
3564 == ~((bfd_vma
) 0x7fffffff)))
3566 if (ep
->X_add_number
& ~((bfd_vma
) 0xffffffff))
3567 as_bad (_("constant too large"));
3569 ep
->X_add_number
= (((ep
->X_add_number
& 0xffffffff) ^ 0x80000000)
3573 if (IS_SEXT_16BIT_NUM (ep
->X_add_number
))
3575 /* We can handle 16 bit signed values with an addiu to
3576 $zero. No need to ever use daddiu here, since $zero and
3577 the result are always correct in 32 bit mode. */
3578 macro_build (ep
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
3581 else if (ep
->X_add_number
>= 0 && ep
->X_add_number
< 0x10000)
3583 /* We can handle 16 bit unsigned values with an ori to
3585 macro_build (ep
, "ori", "t,r,i", reg
, 0, BFD_RELOC_LO16
);
3588 else if ((IS_SEXT_32BIT_NUM (ep
->X_add_number
)))
3590 /* 32 bit values require an lui. */
3591 macro_build (ep
, "lui", "t,u", reg
, BFD_RELOC_HI16
);
3592 if ((ep
->X_add_number
& 0xffff) != 0)
3593 macro_build (ep
, "ori", "t,r,i", reg
, reg
, BFD_RELOC_LO16
);
3598 /* The value is larger than 32 bits. */
3600 if (HAVE_32BIT_GPRS
)
3602 as_bad (_("Number (0x%lx) larger than 32 bits"),
3603 (unsigned long) ep
->X_add_number
);
3604 macro_build (ep
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
3608 if (ep
->X_op
!= O_big
)
3611 hi32
.X_add_number
= (valueT
) hi32
.X_add_number
>> 16;
3612 hi32
.X_add_number
= (valueT
) hi32
.X_add_number
>> 16;
3613 hi32
.X_add_number
&= 0xffffffff;
3615 lo32
.X_add_number
&= 0xffffffff;
3619 assert (ep
->X_add_number
> 2);
3620 if (ep
->X_add_number
== 3)
3621 generic_bignum
[3] = 0;
3622 else if (ep
->X_add_number
> 4)
3623 as_bad (_("Number larger than 64 bits"));
3624 lo32
.X_op
= O_constant
;
3625 lo32
.X_add_number
= generic_bignum
[0] + (generic_bignum
[1] << 16);
3626 hi32
.X_op
= O_constant
;
3627 hi32
.X_add_number
= generic_bignum
[2] + (generic_bignum
[3] << 16);
3630 if (hi32
.X_add_number
== 0)
3635 unsigned long hi
, lo
;
3637 if (hi32
.X_add_number
== (offsetT
) 0xffffffff)
3639 if ((lo32
.X_add_number
& 0xffff8000) == 0xffff8000)
3641 macro_build (&lo32
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
3644 if (lo32
.X_add_number
& 0x80000000)
3646 macro_build (&lo32
, "lui", "t,u", reg
, BFD_RELOC_HI16
);
3647 if (lo32
.X_add_number
& 0xffff)
3648 macro_build (&lo32
, "ori", "t,r,i", reg
, reg
, BFD_RELOC_LO16
);
3653 /* Check for 16bit shifted constant. We know that hi32 is
3654 non-zero, so start the mask on the first bit of the hi32
3659 unsigned long himask
, lomask
;
3663 himask
= 0xffff >> (32 - shift
);
3664 lomask
= (0xffff << shift
) & 0xffffffff;
3668 himask
= 0xffff << (shift
- 32);
3671 if ((hi32
.X_add_number
& ~(offsetT
) himask
) == 0
3672 && (lo32
.X_add_number
& ~(offsetT
) lomask
) == 0)
3676 tmp
.X_op
= O_constant
;
3678 tmp
.X_add_number
= ((hi32
.X_add_number
<< (32 - shift
))
3679 | (lo32
.X_add_number
>> shift
));
3681 tmp
.X_add_number
= hi32
.X_add_number
>> (shift
- 32);
3682 macro_build (&tmp
, "ori", "t,r,i", reg
, 0, BFD_RELOC_LO16
);
3683 macro_build (NULL
, (shift
>= 32) ? "dsll32" : "dsll", "d,w,<",
3684 reg
, reg
, (shift
>= 32) ? shift
- 32 : shift
);
3689 while (shift
<= (64 - 16));
3691 /* Find the bit number of the lowest one bit, and store the
3692 shifted value in hi/lo. */
3693 hi
= (unsigned long) (hi32
.X_add_number
& 0xffffffff);
3694 lo
= (unsigned long) (lo32
.X_add_number
& 0xffffffff);
3698 while ((lo
& 1) == 0)
3703 lo
|= (hi
& (((unsigned long) 1 << bit
) - 1)) << (32 - bit
);
3709 while ((hi
& 1) == 0)
3718 /* Optimize if the shifted value is a (power of 2) - 1. */
3719 if ((hi
== 0 && ((lo
+ 1) & lo
) == 0)
3720 || (lo
== 0xffffffff && ((hi
+ 1) & hi
) == 0))
3722 shift
= COUNT_TOP_ZEROES ((unsigned int) hi32
.X_add_number
);
3727 /* This instruction will set the register to be all
3729 tmp
.X_op
= O_constant
;
3730 tmp
.X_add_number
= (offsetT
) -1;
3731 macro_build (&tmp
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
3735 macro_build (NULL
, (bit
>= 32) ? "dsll32" : "dsll", "d,w,<",
3736 reg
, reg
, (bit
>= 32) ? bit
- 32 : bit
);
3738 macro_build (NULL
, (shift
>= 32) ? "dsrl32" : "dsrl", "d,w,<",
3739 reg
, reg
, (shift
>= 32) ? shift
- 32 : shift
);
3744 /* Sign extend hi32 before calling load_register, because we can
3745 generally get better code when we load a sign extended value. */
3746 if ((hi32
.X_add_number
& 0x80000000) != 0)
3747 hi32
.X_add_number
|= ~(offsetT
) 0xffffffff;
3748 load_register (reg
, &hi32
, 0);
3751 if ((lo32
.X_add_number
& 0xffff0000) == 0)
3755 macro_build (NULL
, "dsll32", "d,w,<", reg
, freg
, 0);
3763 if ((freg
== 0) && (lo32
.X_add_number
== (offsetT
) 0xffffffff))
3765 macro_build (&lo32
, "lui", "t,u", reg
, BFD_RELOC_HI16
);
3766 macro_build (NULL
, "dsrl32", "d,w,<", reg
, reg
, 0);
3772 macro_build (NULL
, "dsll", "d,w,<", reg
, freg
, 16);
3776 mid16
.X_add_number
>>= 16;
3777 macro_build (&mid16
, "ori", "t,r,i", reg
, freg
, BFD_RELOC_LO16
);
3778 macro_build (NULL
, "dsll", "d,w,<", reg
, reg
, 16);
3781 if ((lo32
.X_add_number
& 0xffff) != 0)
3782 macro_build (&lo32
, "ori", "t,r,i", reg
, freg
, BFD_RELOC_LO16
);
3786 load_delay_nop (void)
3788 if (!gpr_interlocks
)
3789 macro_build (NULL
, "nop", "");
3792 /* Load an address into a register. */
3795 load_address (int reg
, expressionS
*ep
, int *used_at
)
3797 if (ep
->X_op
!= O_constant
3798 && ep
->X_op
!= O_symbol
)
3800 as_bad (_("expression too complex"));
3801 ep
->X_op
= O_constant
;
3804 if (ep
->X_op
== O_constant
)
3806 load_register (reg
, ep
, HAVE_64BIT_ADDRESSES
);
3810 if (mips_pic
== NO_PIC
)
3812 /* If this is a reference to a GP relative symbol, we want
3813 addiu $reg,$gp,<sym> (BFD_RELOC_GPREL16)
3815 lui $reg,<sym> (BFD_RELOC_HI16_S)
3816 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
3817 If we have an addend, we always use the latter form.
3819 With 64bit address space and a usable $at we want
3820 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
3821 lui $at,<sym> (BFD_RELOC_HI16_S)
3822 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
3823 daddiu $at,<sym> (BFD_RELOC_LO16)
3827 If $at is already in use, we use a path which is suboptimal
3828 on superscalar processors.
3829 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
3830 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
3832 daddiu $reg,<sym> (BFD_RELOC_HI16_S)
3834 daddiu $reg,<sym> (BFD_RELOC_LO16)
3836 if (HAVE_64BIT_ADDRESSES
)
3838 /* ??? We don't provide a GP-relative alternative for these macros.
3839 It used not to be possible with the original relaxation code,
3840 but it could be done now. */
3842 if (*used_at
== 0 && ! mips_opts
.noat
)
3844 macro_build (ep
, "lui", "t,u", reg
, BFD_RELOC_MIPS_HIGHEST
);
3845 macro_build (ep
, "lui", "t,u", AT
, BFD_RELOC_HI16_S
);
3846 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
,
3847 BFD_RELOC_MIPS_HIGHER
);
3848 macro_build (ep
, "daddiu", "t,r,j", AT
, AT
, BFD_RELOC_LO16
);
3849 macro_build (NULL
, "dsll32", "d,w,<", reg
, reg
, 0);
3850 macro_build (NULL
, "daddu", "d,v,t", reg
, reg
, AT
);
3855 macro_build (ep
, "lui", "t,u", reg
, BFD_RELOC_MIPS_HIGHEST
);
3856 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
,
3857 BFD_RELOC_MIPS_HIGHER
);
3858 macro_build (NULL
, "dsll", "d,w,<", reg
, reg
, 16);
3859 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
, BFD_RELOC_HI16_S
);
3860 macro_build (NULL
, "dsll", "d,w,<", reg
, reg
, 16);
3861 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
, BFD_RELOC_LO16
);
3866 if ((valueT
) ep
->X_add_number
<= MAX_GPREL_OFFSET
3867 && ! nopic_need_relax (ep
->X_add_symbol
, 1))
3869 relax_start (ep
->X_add_symbol
);
3870 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
,
3871 mips_gp_register
, BFD_RELOC_GPREL16
);
3874 macro_build_lui (ep
, reg
);
3875 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j",
3876 reg
, reg
, BFD_RELOC_LO16
);
3877 if (mips_relax
.sequence
)
3881 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
3885 /* If this is a reference to an external symbol, we want
3886 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3888 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3890 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
3891 If there is a constant, it must be added in after.
3893 If we have NewABI, we want
3894 lw $reg,<sym+cst>($gp) (BFD_RELOC_MIPS_GOT_DISP)
3895 unless we're referencing a global symbol with a non-zero
3896 offset, in which case cst must be added separately. */
3899 if (ep
->X_add_number
)
3901 ex
.X_add_number
= ep
->X_add_number
;
3902 ep
->X_add_number
= 0;
3903 relax_start (ep
->X_add_symbol
);
3904 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
3905 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
3906 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
3907 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
3908 ex
.X_op
= O_constant
;
3909 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j",
3910 reg
, reg
, BFD_RELOC_LO16
);
3911 ep
->X_add_number
= ex
.X_add_number
;
3914 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
3915 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
3916 if (mips_relax
.sequence
)
3921 ex
.X_add_number
= ep
->X_add_number
;
3922 ep
->X_add_number
= 0;
3923 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
3924 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
3926 relax_start (ep
->X_add_symbol
);
3928 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
3932 if (ex
.X_add_number
!= 0)
3934 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
3935 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
3936 ex
.X_op
= O_constant
;
3937 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j",
3938 reg
, reg
, BFD_RELOC_LO16
);
3942 else if (mips_pic
== SVR4_PIC
)
3946 /* This is the large GOT case. If this is a reference to an
3947 external symbol, we want
3948 lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
3950 lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16)
3952 Otherwise, for a reference to a local symbol in old ABI, we want
3953 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3955 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
3956 If there is a constant, it must be added in after.
3958 In the NewABI, for local symbols, with or without offsets, we want:
3959 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
3960 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
3964 ex
.X_add_number
= ep
->X_add_number
;
3965 ep
->X_add_number
= 0;
3966 relax_start (ep
->X_add_symbol
);
3967 macro_build (ep
, "lui", "t,u", reg
, BFD_RELOC_MIPS_GOT_HI16
);
3968 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
3969 reg
, reg
, mips_gp_register
);
3970 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)",
3971 reg
, BFD_RELOC_MIPS_GOT_LO16
, reg
);
3972 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
3973 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
3974 else if (ex
.X_add_number
)
3976 ex
.X_op
= O_constant
;
3977 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
3981 ep
->X_add_number
= ex
.X_add_number
;
3983 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
3984 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
3985 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
3986 BFD_RELOC_MIPS_GOT_OFST
);
3991 ex
.X_add_number
= ep
->X_add_number
;
3992 ep
->X_add_number
= 0;
3993 relax_start (ep
->X_add_symbol
);
3994 macro_build (ep
, "lui", "t,u", reg
, BFD_RELOC_MIPS_GOT_HI16
);
3995 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
3996 reg
, reg
, mips_gp_register
);
3997 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)",
3998 reg
, BFD_RELOC_MIPS_GOT_LO16
, reg
);
4000 if (reg_needs_delay (mips_gp_register
))
4002 /* We need a nop before loading from $gp. This special
4003 check is required because the lui which starts the main
4004 instruction stream does not refer to $gp, and so will not
4005 insert the nop which may be required. */
4006 macro_build (NULL
, "nop", "");
4008 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
4009 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
4011 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
4015 if (ex
.X_add_number
!= 0)
4017 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
4018 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
4019 ex
.X_op
= O_constant
;
4020 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
4029 /* Move the contents of register SOURCE into register DEST. */
4032 move_register (int dest
, int source
)
4034 macro_build (NULL
, HAVE_32BIT_GPRS
? "addu" : "daddu", "d,v,t",
4038 /* Emit an SVR4 PIC sequence to load address LOCAL into DEST, where
4039 LOCAL is the sum of a symbol and a 16-bit or 32-bit displacement.
4040 The two alternatives are:
4042 Global symbol Local sybmol
4043 ------------- ------------
4044 lw DEST,%got(SYMBOL) lw DEST,%got(SYMBOL + OFFSET)
4046 addiu DEST,DEST,OFFSET addiu DEST,DEST,%lo(SYMBOL + OFFSET)
4048 load_got_offset emits the first instruction and add_got_offset
4049 emits the second for a 16-bit offset or add_got_offset_hilo emits
4050 a sequence to add a 32-bit offset using a scratch register. */
4053 load_got_offset (int dest
, expressionS
*local
)
4058 global
.X_add_number
= 0;
4060 relax_start (local
->X_add_symbol
);
4061 macro_build (&global
, ADDRESS_LOAD_INSN
, "t,o(b)", dest
,
4062 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
4064 macro_build (local
, ADDRESS_LOAD_INSN
, "t,o(b)", dest
,
4065 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
4070 add_got_offset (int dest
, expressionS
*local
)
4074 global
.X_op
= O_constant
;
4075 global
.X_op_symbol
= NULL
;
4076 global
.X_add_symbol
= NULL
;
4077 global
.X_add_number
= local
->X_add_number
;
4079 relax_start (local
->X_add_symbol
);
4080 macro_build (&global
, ADDRESS_ADDI_INSN
, "t,r,j",
4081 dest
, dest
, BFD_RELOC_LO16
);
4083 macro_build (local
, ADDRESS_ADDI_INSN
, "t,r,j", dest
, dest
, BFD_RELOC_LO16
);
4088 add_got_offset_hilo (int dest
, expressionS
*local
, int tmp
)
4091 int hold_mips_optimize
;
4093 global
.X_op
= O_constant
;
4094 global
.X_op_symbol
= NULL
;
4095 global
.X_add_symbol
= NULL
;
4096 global
.X_add_number
= local
->X_add_number
;
4098 relax_start (local
->X_add_symbol
);
4099 load_register (tmp
, &global
, HAVE_64BIT_ADDRESSES
);
4101 /* Set mips_optimize around the lui instruction to avoid
4102 inserting an unnecessary nop after the lw. */
4103 hold_mips_optimize
= mips_optimize
;
4105 macro_build_lui (&global
, tmp
);
4106 mips_optimize
= hold_mips_optimize
;
4107 macro_build (local
, ADDRESS_ADDI_INSN
, "t,r,j", tmp
, tmp
, BFD_RELOC_LO16
);
4110 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", dest
, dest
, tmp
);
4115 * This routine implements the seemingly endless macro or synthesized
4116 * instructions and addressing modes in the mips assembly language. Many
4117 * of these macros are simple and are similar to each other. These could
4118 * probably be handled by some kind of table or grammar approach instead of
4119 * this verbose method. Others are not simple macros but are more like
4120 * optimizing code generation.
4121 * One interesting optimization is when several store macros appear
4122 * consecutively that would load AT with the upper half of the same address.
4123 * The ensuing load upper instructions are ommited. This implies some kind
4124 * of global optimization. We currently only optimize within a single macro.
4125 * For many of the load and store macros if the address is specified as a
4126 * constant expression in the first 64k of memory (ie ld $2,0x4000c) we
4127 * first load register 'at' with zero and use it as the base register. The
4128 * mips assembler simply uses register $zero. Just one tiny optimization
4132 macro (struct mips_cl_insn
*ip
)
4134 register int treg
, sreg
, dreg
, breg
;
4150 bfd_reloc_code_real_type r
;
4151 int hold_mips_optimize
;
4153 assert (! mips_opts
.mips16
);
4155 treg
= (ip
->insn_opcode
>> 16) & 0x1f;
4156 dreg
= (ip
->insn_opcode
>> 11) & 0x1f;
4157 sreg
= breg
= (ip
->insn_opcode
>> 21) & 0x1f;
4158 mask
= ip
->insn_mo
->mask
;
4160 expr1
.X_op
= O_constant
;
4161 expr1
.X_op_symbol
= NULL
;
4162 expr1
.X_add_symbol
= NULL
;
4163 expr1
.X_add_number
= 1;
4175 mips_emit_delays (TRUE
);
4176 ++mips_opts
.noreorder
;
4177 mips_any_noreorder
= 1;
4179 expr1
.X_add_number
= 8;
4180 macro_build (&expr1
, "bgez", "s,p", sreg
);
4182 macro_build (NULL
, "nop", "", 0);
4184 move_register (dreg
, sreg
);
4185 macro_build (NULL
, dbl
? "dsub" : "sub", "d,v,t", dreg
, 0, sreg
);
4187 --mips_opts
.noreorder
;
4208 if (imm_expr
.X_op
== O_constant
4209 && imm_expr
.X_add_number
>= -0x8000
4210 && imm_expr
.X_add_number
< 0x8000)
4212 macro_build (&imm_expr
, s
, "t,r,j", treg
, sreg
, BFD_RELOC_LO16
);
4215 load_register (AT
, &imm_expr
, dbl
);
4216 macro_build (NULL
, s2
, "d,v,t", treg
, sreg
, AT
);
4235 if (imm_expr
.X_op
== O_constant
4236 && imm_expr
.X_add_number
>= 0
4237 && imm_expr
.X_add_number
< 0x10000)
4239 if (mask
!= M_NOR_I
)
4240 macro_build (&imm_expr
, s
, "t,r,i", treg
, sreg
, BFD_RELOC_LO16
);
4243 macro_build (&imm_expr
, "ori", "t,r,i",
4244 treg
, sreg
, BFD_RELOC_LO16
);
4245 macro_build (NULL
, "nor", "d,v,t", treg
, treg
, 0);
4250 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
4251 macro_build (NULL
, s2
, "d,v,t", treg
, sreg
, AT
);
4268 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
4270 macro_build (&offset_expr
, s
, "s,t,p", sreg
, 0);
4273 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
4274 macro_build (&offset_expr
, s
, "s,t,p", sreg
, AT
);
4282 macro_build (&offset_expr
, likely
? "bgezl" : "bgez", "s,p", sreg
);
4287 macro_build (&offset_expr
, likely
? "blezl" : "blez", "s,p", treg
);
4290 macro_build (NULL
, "slt", "d,v,t", AT
, sreg
, treg
);
4291 macro_build (&offset_expr
, likely
? "beql" : "beq", "s,t,p", AT
, 0);
4297 /* check for > max integer */
4298 maxnum
= 0x7fffffff;
4299 if (HAVE_64BIT_GPRS
&& sizeof (maxnum
) > 4)
4306 if (imm_expr
.X_op
== O_constant
4307 && imm_expr
.X_add_number
>= maxnum
4308 && (HAVE_32BIT_GPRS
|| sizeof (maxnum
) > 4))
4311 /* result is always false */
4313 macro_build (NULL
, "nop", "", 0);
4315 macro_build (&offset_expr
, "bnel", "s,t,p", 0, 0);
4318 if (imm_expr
.X_op
!= O_constant
)
4319 as_bad (_("Unsupported large constant"));
4320 ++imm_expr
.X_add_number
;
4324 if (mask
== M_BGEL_I
)
4326 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
4328 macro_build (&offset_expr
, likely
? "bgezl" : "bgez", "s,p", sreg
);
4331 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
4333 macro_build (&offset_expr
, likely
? "bgtzl" : "bgtz", "s,p", sreg
);
4336 maxnum
= 0x7fffffff;
4337 if (HAVE_64BIT_GPRS
&& sizeof (maxnum
) > 4)
4344 maxnum
= - maxnum
- 1;
4345 if (imm_expr
.X_op
== O_constant
4346 && imm_expr
.X_add_number
<= maxnum
4347 && (HAVE_32BIT_GPRS
|| sizeof (maxnum
) > 4))
4350 /* result is always true */
4351 as_warn (_("Branch %s is always true"), ip
->insn_mo
->name
);
4352 macro_build (&offset_expr
, "b", "p");
4356 macro_build (&offset_expr
, likely
? "beql" : "beq", "s,t,p", AT
, 0);
4366 macro_build (&offset_expr
, likely
? "beql" : "beq",
4370 macro_build (NULL
, "sltu", "d,v,t", AT
, sreg
, treg
);
4371 macro_build (&offset_expr
, likely
? "beql" : "beq", "s,t,p", AT
, 0);
4379 && imm_expr
.X_op
== O_constant
4380 && imm_expr
.X_add_number
== (offsetT
) 0xffffffff))
4382 if (imm_expr
.X_op
!= O_constant
)
4383 as_bad (_("Unsupported large constant"));
4384 ++imm_expr
.X_add_number
;
4388 if (mask
== M_BGEUL_I
)
4390 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
4392 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
4394 macro_build (&offset_expr
, likely
? "bnel" : "bne",
4399 macro_build (&offset_expr
, likely
? "beql" : "beq", "s,t,p", AT
, 0);
4407 macro_build (&offset_expr
, likely
? "bgtzl" : "bgtz", "s,p", sreg
);
4412 macro_build (&offset_expr
, likely
? "bltzl" : "bltz", "s,p", treg
);
4415 macro_build (NULL
, "slt", "d,v,t", AT
, treg
, sreg
);
4416 macro_build (&offset_expr
, likely
? "bnel" : "bne", "s,t,p", AT
, 0);
4424 macro_build (&offset_expr
, likely
? "bnel" : "bne",
4430 macro_build (NULL
, "sltu", "d,v,t", AT
, treg
, sreg
);
4431 macro_build (&offset_expr
, likely
? "bnel" : "bne", "s,t,p", AT
, 0);
4439 macro_build (&offset_expr
, likely
? "blezl" : "blez", "s,p", sreg
);
4444 macro_build (&offset_expr
, likely
? "bgezl" : "bgez", "s,p", treg
);
4447 macro_build (NULL
, "slt", "d,v,t", AT
, treg
, sreg
);
4448 macro_build (&offset_expr
, likely
? "beql" : "beq", "s,t,p", AT
, 0);
4454 maxnum
= 0x7fffffff;
4455 if (HAVE_64BIT_GPRS
&& sizeof (maxnum
) > 4)
4462 if (imm_expr
.X_op
== O_constant
4463 && imm_expr
.X_add_number
>= maxnum
4464 && (HAVE_32BIT_GPRS
|| sizeof (maxnum
) > 4))
4466 if (imm_expr
.X_op
!= O_constant
)
4467 as_bad (_("Unsupported large constant"));
4468 ++imm_expr
.X_add_number
;
4472 if (mask
== M_BLTL_I
)
4474 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
4476 macro_build (&offset_expr
, likely
? "bltzl" : "bltz", "s,p", sreg
);
4479 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
4481 macro_build (&offset_expr
, likely
? "blezl" : "blez", "s,p", sreg
);
4485 macro_build (&offset_expr
, likely
? "bnel" : "bne", "s,t,p", AT
, 0);
4493 macro_build (&offset_expr
, likely
? "beql" : "beq",
4499 macro_build (NULL
, "sltu", "d,v,t", AT
, treg
, sreg
);
4500 macro_build (&offset_expr
, likely
? "beql" : "beq", "s,t,p", AT
, 0);
4508 && imm_expr
.X_op
== O_constant
4509 && imm_expr
.X_add_number
== (offsetT
) 0xffffffff))
4511 if (imm_expr
.X_op
!= O_constant
)
4512 as_bad (_("Unsupported large constant"));
4513 ++imm_expr
.X_add_number
;
4517 if (mask
== M_BLTUL_I
)
4519 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
4521 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
4523 macro_build (&offset_expr
, likely
? "beql" : "beq",
4528 macro_build (&offset_expr
, likely
? "bnel" : "bne", "s,t,p", AT
, 0);
4536 macro_build (&offset_expr
, likely
? "bltzl" : "bltz", "s,p", sreg
);
4541 macro_build (&offset_expr
, likely
? "bgtzl" : "bgtz", "s,p", treg
);
4544 macro_build (NULL
, "slt", "d,v,t", AT
, sreg
, treg
);
4545 macro_build (&offset_expr
, likely
? "bnel" : "bne", "s,t,p", AT
, 0);
4555 macro_build (&offset_expr
, likely
? "bnel" : "bne",
4559 macro_build (NULL
, "sltu", "d,v,t", AT
, sreg
, treg
);
4560 macro_build (&offset_expr
, likely
? "bnel" : "bne", "s,t,p", AT
, 0);
4568 if (imm_expr
.X_op
!= O_constant
|| imm2_expr
.X_op
!= O_constant
)
4570 as_bad (_("Unsupported large constant"));
4575 pos
= (unsigned long) imm_expr
.X_add_number
;
4576 size
= (unsigned long) imm2_expr
.X_add_number
;
4581 as_bad (_("Improper position (%lu)"), pos
);
4584 if (size
== 0 || size
> 64
4585 || (pos
+ size
- 1) > 63)
4587 as_bad (_("Improper extract size (%lu, position %lu)"),
4592 if (size
<= 32 && pos
< 32)
4597 else if (size
<= 32)
4607 macro_build ((expressionS
*) NULL
, s
, fmt
, treg
, sreg
, pos
, size
- 1);
4616 if (imm_expr
.X_op
!= O_constant
|| imm2_expr
.X_op
!= O_constant
)
4618 as_bad (_("Unsupported large constant"));
4623 pos
= (unsigned long) imm_expr
.X_add_number
;
4624 size
= (unsigned long) imm2_expr
.X_add_number
;
4629 as_bad (_("Improper position (%lu)"), pos
);
4632 if (size
== 0 || size
> 64
4633 || (pos
+ size
- 1) > 63)
4635 as_bad (_("Improper insert size (%lu, position %lu)"),
4640 if (pos
< 32 && (pos
+ size
- 1) < 32)
4655 macro_build ((expressionS
*) NULL
, s
, fmt
, treg
, sreg
, pos
,
4672 as_warn (_("Divide by zero."));
4674 macro_build (NULL
, "teq", "s,t,q", 0, 0, 7);
4676 macro_build (NULL
, "break", "c", 7);
4680 mips_emit_delays (TRUE
);
4681 ++mips_opts
.noreorder
;
4682 mips_any_noreorder
= 1;
4685 macro_build (NULL
, "teq", "s,t,q", treg
, 0, 7);
4686 macro_build (NULL
, dbl
? "ddiv" : "div", "z,s,t", sreg
, treg
);
4690 expr1
.X_add_number
= 8;
4691 macro_build (&expr1
, "bne", "s,t,p", treg
, 0);
4692 macro_build (NULL
, dbl
? "ddiv" : "div", "z,s,t", sreg
, treg
);
4693 macro_build (NULL
, "break", "c", 7);
4695 expr1
.X_add_number
= -1;
4696 load_register (AT
, &expr1
, dbl
);
4697 expr1
.X_add_number
= mips_trap
? (dbl
? 12 : 8) : (dbl
? 20 : 16);
4698 macro_build (&expr1
, "bne", "s,t,p", treg
, AT
);
4701 expr1
.X_add_number
= 1;
4702 load_register (AT
, &expr1
, dbl
);
4703 macro_build (NULL
, "dsll32", "d,w,<", AT
, AT
, 31);
4707 expr1
.X_add_number
= 0x80000000;
4708 macro_build (&expr1
, "lui", "t,u", AT
, BFD_RELOC_HI16
);
4712 macro_build (NULL
, "teq", "s,t,q", sreg
, AT
, 6);
4713 /* We want to close the noreorder block as soon as possible, so
4714 that later insns are available for delay slot filling. */
4715 --mips_opts
.noreorder
;
4719 expr1
.X_add_number
= 8;
4720 macro_build (&expr1
, "bne", "s,t,p", sreg
, AT
);
4721 macro_build (NULL
, "nop", "", 0);
4723 /* We want to close the noreorder block as soon as possible, so
4724 that later insns are available for delay slot filling. */
4725 --mips_opts
.noreorder
;
4727 macro_build (NULL
, "break", "c", 6);
4729 macro_build (NULL
, s
, "d", dreg
);
4768 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
4770 as_warn (_("Divide by zero."));
4772 macro_build (NULL
, "teq", "s,t,q", 0, 0, 7);
4774 macro_build (NULL
, "break", "c", 7);
4777 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
4779 if (strcmp (s2
, "mflo") == 0)
4780 move_register (dreg
, sreg
);
4782 move_register (dreg
, 0);
4785 if (imm_expr
.X_op
== O_constant
4786 && imm_expr
.X_add_number
== -1
4787 && s
[strlen (s
) - 1] != 'u')
4789 if (strcmp (s2
, "mflo") == 0)
4791 macro_build (NULL
, dbl
? "dneg" : "neg", "d,w", dreg
, sreg
);
4794 move_register (dreg
, 0);
4798 load_register (AT
, &imm_expr
, dbl
);
4799 macro_build (NULL
, s
, "z,s,t", sreg
, AT
);
4800 macro_build (NULL
, s2
, "d", dreg
);
4819 mips_emit_delays (TRUE
);
4820 ++mips_opts
.noreorder
;
4821 mips_any_noreorder
= 1;
4824 macro_build (NULL
, "teq", "s,t,q", treg
, 0, 7);
4825 macro_build (NULL
, s
, "z,s,t", sreg
, treg
);
4826 /* We want to close the noreorder block as soon as possible, so
4827 that later insns are available for delay slot filling. */
4828 --mips_opts
.noreorder
;
4832 expr1
.X_add_number
= 8;
4833 macro_build (&expr1
, "bne", "s,t,p", treg
, 0);
4834 macro_build (NULL
, s
, "z,s,t", sreg
, treg
);
4836 /* We want to close the noreorder block as soon as possible, so
4837 that later insns are available for delay slot filling. */
4838 --mips_opts
.noreorder
;
4839 macro_build (NULL
, "break", "c", 7);
4841 macro_build (NULL
, s2
, "d", dreg
);
4853 /* Load the address of a symbol into a register. If breg is not
4854 zero, we then add a base register to it. */
4856 if (dbl
&& HAVE_32BIT_GPRS
)
4857 as_warn (_("dla used to load 32-bit register"));
4859 if (! dbl
&& HAVE_64BIT_OBJECTS
)
4860 as_warn (_("la used to load 64-bit address"));
4862 if (offset_expr
.X_op
== O_constant
4863 && offset_expr
.X_add_number
>= -0x8000
4864 && offset_expr
.X_add_number
< 0x8000)
4866 macro_build (&offset_expr
,
4867 (dbl
|| HAVE_64BIT_ADDRESSES
) ? "daddiu" : "addiu",
4868 "t,r,j", treg
, sreg
, BFD_RELOC_LO16
);
4883 if (offset_expr
.X_op
!= O_symbol
4884 && offset_expr
.X_op
!= O_constant
)
4886 as_bad (_("expression too complex"));
4887 offset_expr
.X_op
= O_constant
;
4890 if (offset_expr
.X_op
== O_constant
)
4891 load_register (tempreg
, &offset_expr
,
4893 ? (dbl
|| HAVE_64BIT_ADDRESSES
)
4894 : HAVE_64BIT_ADDRESSES
));
4895 else if (mips_pic
== NO_PIC
)
4897 /* If this is a reference to a GP relative symbol, we want
4898 addiu $tempreg,$gp,<sym> (BFD_RELOC_GPREL16)
4900 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
4901 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
4902 If we have a constant, we need two instructions anyhow,
4903 so we may as well always use the latter form.
4905 With 64bit address space and a usable $at we want
4906 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
4907 lui $at,<sym> (BFD_RELOC_HI16_S)
4908 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
4909 daddiu $at,<sym> (BFD_RELOC_LO16)
4911 daddu $tempreg,$tempreg,$at
4913 If $at is already in use, we use a path which is suboptimal
4914 on superscalar processors.
4915 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
4916 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
4918 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
4920 daddiu $tempreg,<sym> (BFD_RELOC_LO16)
4922 if (HAVE_64BIT_ADDRESSES
)
4924 /* ??? We don't provide a GP-relative alternative for
4925 these macros. It used not to be possible with the
4926 original relaxation code, but it could be done now. */
4928 if (used_at
== 0 && ! mips_opts
.noat
)
4930 macro_build (&offset_expr
, "lui", "t,u",
4931 tempreg
, BFD_RELOC_MIPS_HIGHEST
);
4932 macro_build (&offset_expr
, "lui", "t,u",
4933 AT
, BFD_RELOC_HI16_S
);
4934 macro_build (&offset_expr
, "daddiu", "t,r,j",
4935 tempreg
, tempreg
, BFD_RELOC_MIPS_HIGHER
);
4936 macro_build (&offset_expr
, "daddiu", "t,r,j",
4937 AT
, AT
, BFD_RELOC_LO16
);
4938 macro_build (NULL
, "dsll32", "d,w,<", tempreg
, tempreg
, 0);
4939 macro_build (NULL
, "daddu", "d,v,t", tempreg
, tempreg
, AT
);
4944 macro_build (&offset_expr
, "lui", "t,u",
4945 tempreg
, BFD_RELOC_MIPS_HIGHEST
);
4946 macro_build (&offset_expr
, "daddiu", "t,r,j",
4947 tempreg
, tempreg
, BFD_RELOC_MIPS_HIGHER
);
4948 macro_build (NULL
, "dsll", "d,w,<", tempreg
, tempreg
, 16);
4949 macro_build (&offset_expr
, "daddiu", "t,r,j",
4950 tempreg
, tempreg
, BFD_RELOC_HI16_S
);
4951 macro_build (NULL
, "dsll", "d,w,<", tempreg
, tempreg
, 16);
4952 macro_build (&offset_expr
, "daddiu", "t,r,j",
4953 tempreg
, tempreg
, BFD_RELOC_LO16
);
4958 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
4959 && ! nopic_need_relax (offset_expr
.X_add_symbol
, 1))
4961 relax_start (offset_expr
.X_add_symbol
);
4962 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
4963 tempreg
, mips_gp_register
, BFD_RELOC_GPREL16
);
4966 macro_build_lui (&offset_expr
, tempreg
);
4967 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
4968 tempreg
, tempreg
, BFD_RELOC_LO16
);
4969 if (mips_relax
.sequence
)
4973 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
&& ! HAVE_NEWABI
)
4975 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT16
;
4977 /* If this is a reference to an external symbol, and there
4978 is no constant, we want
4979 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4980 or for lca or if tempreg is PIC_CALL_REG
4981 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
4982 For a local symbol, we want
4983 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4985 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
4987 If we have a small constant, and this is a reference to
4988 an external symbol, we want
4989 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4991 addiu $tempreg,$tempreg,<constant>
4992 For a local symbol, we want the same instruction
4993 sequence, but we output a BFD_RELOC_LO16 reloc on the
4996 If we have a large constant, and this is a reference to
4997 an external symbol, we want
4998 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4999 lui $at,<hiconstant>
5000 addiu $at,$at,<loconstant>
5001 addu $tempreg,$tempreg,$at
5002 For a local symbol, we want the same instruction
5003 sequence, but we output a BFD_RELOC_LO16 reloc on the
5007 if (offset_expr
.X_add_number
== 0)
5009 if (breg
== 0 && (call
|| tempreg
== PIC_CALL_REG
))
5010 lw_reloc_type
= (int) BFD_RELOC_MIPS_CALL16
;
5012 relax_start (offset_expr
.X_add_symbol
);
5013 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
5014 lw_reloc_type
, mips_gp_register
);
5017 /* We're going to put in an addu instruction using
5018 tempreg, so we may as well insert the nop right
5023 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
5024 tempreg
, BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
5026 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
5027 tempreg
, tempreg
, BFD_RELOC_LO16
);
5029 /* FIXME: If breg == 0, and the next instruction uses
5030 $tempreg, then if this variant case is used an extra
5031 nop will be generated. */
5033 else if (offset_expr
.X_add_number
>= -0x8000
5034 && offset_expr
.X_add_number
< 0x8000)
5036 load_got_offset (tempreg
, &offset_expr
);
5038 add_got_offset (tempreg
, &offset_expr
);
5042 expr1
.X_add_number
= offset_expr
.X_add_number
;
5043 offset_expr
.X_add_number
=
5044 ((offset_expr
.X_add_number
+ 0x8000) & 0xffff) - 0x8000;
5045 load_got_offset (tempreg
, &offset_expr
);
5046 offset_expr
.X_add_number
= expr1
.X_add_number
;
5047 /* If we are going to add in a base register, and the
5048 target register and the base register are the same,
5049 then we are using AT as a temporary register. Since
5050 we want to load the constant into AT, we add our
5051 current AT (from the global offset table) and the
5052 register into the register now, and pretend we were
5053 not using a base register. */
5057 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5062 add_got_offset_hilo (tempreg
, &offset_expr
, AT
);
5066 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
&& HAVE_NEWABI
)
5068 int add_breg_early
= 0;
5070 /* If this is a reference to an external, and there is no
5071 constant, or local symbol (*), with or without a
5073 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
5074 or for lca or if tempreg is PIC_CALL_REG
5075 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
5077 If we have a small constant, and this is a reference to
5078 an external symbol, we want
5079 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
5080 addiu $tempreg,$tempreg,<constant>
5082 If we have a large constant, and this is a reference to
5083 an external symbol, we want
5084 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
5085 lui $at,<hiconstant>
5086 addiu $at,$at,<loconstant>
5087 addu $tempreg,$tempreg,$at
5089 (*) Other assemblers seem to prefer GOT_PAGE/GOT_OFST for
5090 local symbols, even though it introduces an additional
5093 if (offset_expr
.X_add_number
)
5095 expr1
.X_add_number
= offset_expr
.X_add_number
;
5096 offset_expr
.X_add_number
= 0;
5098 relax_start (offset_expr
.X_add_symbol
);
5099 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
5100 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
5102 if (expr1
.X_add_number
>= -0x8000
5103 && expr1
.X_add_number
< 0x8000)
5105 macro_build (&expr1
, ADDRESS_ADDI_INSN
, "t,r,j",
5106 tempreg
, tempreg
, BFD_RELOC_LO16
);
5108 else if (IS_SEXT_32BIT_NUM (expr1
.X_add_number
+ 0x8000))
5112 /* If we are going to add in a base register, and the
5113 target register and the base register are the same,
5114 then we are using AT as a temporary register. Since
5115 we want to load the constant into AT, we add our
5116 current AT (from the global offset table) and the
5117 register into the register now, and pretend we were
5118 not using a base register. */
5123 assert (tempreg
== AT
);
5124 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5130 load_register (AT
, &expr1
, HAVE_64BIT_ADDRESSES
);
5131 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5137 as_bad (_("PIC code offset overflow (max 32 signed bits)"));
5140 offset_expr
.X_add_number
= expr1
.X_add_number
;
5142 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
5143 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
5146 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5147 treg
, tempreg
, breg
);
5153 else if (breg
== 0 && (call
|| tempreg
== PIC_CALL_REG
))
5155 relax_start (offset_expr
.X_add_symbol
);
5156 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
5157 BFD_RELOC_MIPS_CALL16
, mips_gp_register
);
5159 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
5160 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
5165 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
5166 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
5169 else if (mips_pic
== SVR4_PIC
&& ! HAVE_NEWABI
)
5172 int lui_reloc_type
= (int) BFD_RELOC_MIPS_GOT_HI16
;
5173 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT_LO16
;
5174 int local_reloc_type
= (int) BFD_RELOC_MIPS_GOT16
;
5176 /* This is the large GOT case. If this is a reference to an
5177 external symbol, and there is no constant, we want
5178 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5179 addu $tempreg,$tempreg,$gp
5180 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5181 or for lca or if tempreg is PIC_CALL_REG
5182 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
5183 addu $tempreg,$tempreg,$gp
5184 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
5185 For a local symbol, we want
5186 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5188 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
5190 If we have a small constant, and this is a reference to
5191 an external symbol, we want
5192 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5193 addu $tempreg,$tempreg,$gp
5194 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5196 addiu $tempreg,$tempreg,<constant>
5197 For a local symbol, we want
5198 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5200 addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16)
5202 If we have a large constant, and this is a reference to
5203 an external symbol, we want
5204 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5205 addu $tempreg,$tempreg,$gp
5206 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5207 lui $at,<hiconstant>
5208 addiu $at,$at,<loconstant>
5209 addu $tempreg,$tempreg,$at
5210 For a local symbol, we want
5211 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5212 lui $at,<hiconstant>
5213 addiu $at,$at,<loconstant> (BFD_RELOC_LO16)
5214 addu $tempreg,$tempreg,$at
5217 expr1
.X_add_number
= offset_expr
.X_add_number
;
5218 offset_expr
.X_add_number
= 0;
5219 relax_start (offset_expr
.X_add_symbol
);
5220 gpdelay
= reg_needs_delay (mips_gp_register
);
5221 if (expr1
.X_add_number
== 0 && breg
== 0
5222 && (call
|| tempreg
== PIC_CALL_REG
))
5224 lui_reloc_type
= (int) BFD_RELOC_MIPS_CALL_HI16
;
5225 lw_reloc_type
= (int) BFD_RELOC_MIPS_CALL_LO16
;
5227 macro_build (&offset_expr
, "lui", "t,u", tempreg
, lui_reloc_type
);
5228 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5229 tempreg
, tempreg
, mips_gp_register
);
5230 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
5231 tempreg
, lw_reloc_type
, tempreg
);
5232 if (expr1
.X_add_number
== 0)
5236 /* We're going to put in an addu instruction using
5237 tempreg, so we may as well insert the nop right
5242 else if (expr1
.X_add_number
>= -0x8000
5243 && expr1
.X_add_number
< 0x8000)
5246 macro_build (&expr1
, ADDRESS_ADDI_INSN
, "t,r,j",
5247 tempreg
, tempreg
, BFD_RELOC_LO16
);
5253 /* If we are going to add in a base register, and the
5254 target register and the base register are the same,
5255 then we are using AT as a temporary register. Since
5256 we want to load the constant into AT, we add our
5257 current AT (from the global offset table) and the
5258 register into the register now, and pretend we were
5259 not using a base register. */
5264 assert (tempreg
== AT
);
5266 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5271 load_register (AT
, &expr1
, HAVE_64BIT_ADDRESSES
);
5272 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", dreg
, dreg
, AT
);
5276 offset_expr
.X_add_number
=
5277 ((expr1
.X_add_number
+ 0x8000) & 0xffff) - 0x8000;
5282 /* This is needed because this instruction uses $gp, but
5283 the first instruction on the main stream does not. */
5284 macro_build (NULL
, "nop", "");
5287 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
5288 local_reloc_type
, mips_gp_register
);
5289 if (expr1
.X_add_number
>= -0x8000
5290 && expr1
.X_add_number
< 0x8000)
5293 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
5294 tempreg
, tempreg
, BFD_RELOC_LO16
);
5295 /* FIXME: If add_number is 0, and there was no base
5296 register, the external symbol case ended with a load,
5297 so if the symbol turns out to not be external, and
5298 the next instruction uses tempreg, an unnecessary nop
5299 will be inserted. */
5305 /* We must add in the base register now, as in the
5306 external symbol case. */
5307 assert (tempreg
== AT
);
5309 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5312 /* We set breg to 0 because we have arranged to add
5313 it in in both cases. */
5317 macro_build_lui (&expr1
, AT
);
5318 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
5319 AT
, AT
, BFD_RELOC_LO16
);
5320 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5321 tempreg
, tempreg
, AT
);
5325 else if (mips_pic
== SVR4_PIC
&& HAVE_NEWABI
)
5327 int lui_reloc_type
= (int) BFD_RELOC_MIPS_GOT_HI16
;
5328 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT_LO16
;
5329 int add_breg_early
= 0;
5331 /* This is the large GOT case. If this is a reference to an
5332 external symbol, and there is no constant, we want
5333 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5334 add $tempreg,$tempreg,$gp
5335 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5336 or for lca or if tempreg is PIC_CALL_REG
5337 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
5338 add $tempreg,$tempreg,$gp
5339 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
5341 If we have a small constant, and this is a reference to
5342 an external symbol, we want
5343 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5344 add $tempreg,$tempreg,$gp
5345 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5346 addi $tempreg,$tempreg,<constant>
5348 If we have a large constant, and this is a reference to
5349 an external symbol, we want
5350 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5351 addu $tempreg,$tempreg,$gp
5352 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5353 lui $at,<hiconstant>
5354 addi $at,$at,<loconstant>
5355 add $tempreg,$tempreg,$at
5357 If we have NewABI, and we know it's a local symbol, we want
5358 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
5359 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
5360 otherwise we have to resort to GOT_HI16/GOT_LO16. */
5362 relax_start (offset_expr
.X_add_symbol
);
5364 expr1
.X_add_number
= offset_expr
.X_add_number
;
5365 offset_expr
.X_add_number
= 0;
5367 if (expr1
.X_add_number
== 0 && breg
== 0
5368 && (call
|| tempreg
== PIC_CALL_REG
))
5370 lui_reloc_type
= (int) BFD_RELOC_MIPS_CALL_HI16
;
5371 lw_reloc_type
= (int) BFD_RELOC_MIPS_CALL_LO16
;
5373 macro_build (&offset_expr
, "lui", "t,u", tempreg
, lui_reloc_type
);
5374 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5375 tempreg
, tempreg
, mips_gp_register
);
5376 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
5377 tempreg
, lw_reloc_type
, tempreg
);
5379 if (expr1
.X_add_number
== 0)
5381 else if (expr1
.X_add_number
>= -0x8000
5382 && expr1
.X_add_number
< 0x8000)
5384 macro_build (&expr1
, ADDRESS_ADDI_INSN
, "t,r,j",
5385 tempreg
, tempreg
, BFD_RELOC_LO16
);
5387 else if (IS_SEXT_32BIT_NUM (expr1
.X_add_number
+ 0x8000))
5391 /* If we are going to add in a base register, and the
5392 target register and the base register are the same,
5393 then we are using AT as a temporary register. Since
5394 we want to load the constant into AT, we add our
5395 current AT (from the global offset table) and the
5396 register into the register now, and pretend we were
5397 not using a base register. */
5402 assert (tempreg
== AT
);
5403 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5409 load_register (AT
, &expr1
, HAVE_64BIT_ADDRESSES
);
5410 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", dreg
, dreg
, AT
);
5415 as_bad (_("PIC code offset overflow (max 32 signed bits)"));
5418 offset_expr
.X_add_number
= expr1
.X_add_number
;
5419 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
5420 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
5421 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j", tempreg
,
5422 tempreg
, BFD_RELOC_MIPS_GOT_OFST
);
5425 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5426 treg
, tempreg
, breg
);
5439 if (mips_pic
== NO_PIC
)
5440 s
= (dbl
|| HAVE_64BIT_ADDRESSES
) ? "daddu" : "addu";
5442 s
= ADDRESS_ADD_INSN
;
5444 macro_build (NULL
, s
, "d,v,t", treg
, tempreg
, breg
);
5453 /* The j instruction may not be used in PIC code, since it
5454 requires an absolute address. We convert it to a b
5456 if (mips_pic
== NO_PIC
)
5457 macro_build (&offset_expr
, "j", "a");
5459 macro_build (&offset_expr
, "b", "p");
5462 /* The jal instructions must be handled as macros because when
5463 generating PIC code they expand to multi-instruction
5464 sequences. Normally they are simple instructions. */
5469 if (mips_pic
== NO_PIC
)
5470 macro_build (NULL
, "jalr", "d,s", dreg
, sreg
);
5471 else if (mips_pic
== SVR4_PIC
)
5473 if (sreg
!= PIC_CALL_REG
)
5474 as_warn (_("MIPS PIC call to register other than $25"));
5476 macro_build (NULL
, "jalr", "d,s", dreg
, sreg
);
5479 if (mips_cprestore_offset
< 0)
5480 as_warn (_("No .cprestore pseudo-op used in PIC code"));
5483 if (! mips_frame_reg_valid
)
5485 as_warn (_("No .frame pseudo-op used in PIC code"));
5486 /* Quiet this warning. */
5487 mips_frame_reg_valid
= 1;
5489 if (! mips_cprestore_valid
)
5491 as_warn (_("No .cprestore pseudo-op used in PIC code"));
5492 /* Quiet this warning. */
5493 mips_cprestore_valid
= 1;
5495 expr1
.X_add_number
= mips_cprestore_offset
;
5496 macro_build_ldst_constoffset (&expr1
, ADDRESS_LOAD_INSN
,
5499 HAVE_64BIT_ADDRESSES
);
5509 if (mips_pic
== NO_PIC
)
5510 macro_build (&offset_expr
, "jal", "a");
5511 else if (mips_pic
== SVR4_PIC
)
5513 /* If this is a reference to an external symbol, and we are
5514 using a small GOT, we want
5515 lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
5519 lw $gp,cprestore($sp)
5520 The cprestore value is set using the .cprestore
5521 pseudo-op. If we are using a big GOT, we want
5522 lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16)
5524 lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16)
5528 lw $gp,cprestore($sp)
5529 If the symbol is not external, we want
5530 lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5532 addiu $25,$25,<sym> (BFD_RELOC_LO16)
5535 lw $gp,cprestore($sp)
5537 For NewABI, we use the same CALL16 or CALL_HI16/CALL_LO16
5538 sequences above, minus nops, unless the symbol is local,
5539 which enables us to use GOT_PAGE/GOT_OFST (big got) or
5545 relax_start (offset_expr
.X_add_symbol
);
5546 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
5547 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL16
,
5550 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
5551 PIC_CALL_REG
, BFD_RELOC_MIPS_GOT_DISP
,
5557 relax_start (offset_expr
.X_add_symbol
);
5558 macro_build (&offset_expr
, "lui", "t,u", PIC_CALL_REG
,
5559 BFD_RELOC_MIPS_CALL_HI16
);
5560 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", PIC_CALL_REG
,
5561 PIC_CALL_REG
, mips_gp_register
);
5562 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
5563 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL_LO16
,
5566 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
5567 PIC_CALL_REG
, BFD_RELOC_MIPS_GOT_PAGE
,
5569 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
5570 PIC_CALL_REG
, PIC_CALL_REG
,
5571 BFD_RELOC_MIPS_GOT_OFST
);
5575 macro_build_jalr (&offset_expr
);
5579 relax_start (offset_expr
.X_add_symbol
);
5582 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
5583 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL16
,
5592 gpdelay
= reg_needs_delay (mips_gp_register
);
5593 macro_build (&offset_expr
, "lui", "t,u", PIC_CALL_REG
,
5594 BFD_RELOC_MIPS_CALL_HI16
);
5595 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", PIC_CALL_REG
,
5596 PIC_CALL_REG
, mips_gp_register
);
5597 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
5598 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL_LO16
,
5603 macro_build (NULL
, "nop", "");
5605 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
5606 PIC_CALL_REG
, BFD_RELOC_MIPS_GOT16
,
5609 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
5610 PIC_CALL_REG
, PIC_CALL_REG
, BFD_RELOC_LO16
);
5612 macro_build_jalr (&offset_expr
);
5614 if (mips_cprestore_offset
< 0)
5615 as_warn (_("No .cprestore pseudo-op used in PIC code"));
5618 if (! mips_frame_reg_valid
)
5620 as_warn (_("No .frame pseudo-op used in PIC code"));
5621 /* Quiet this warning. */
5622 mips_frame_reg_valid
= 1;
5624 if (! mips_cprestore_valid
)
5626 as_warn (_("No .cprestore pseudo-op used in PIC code"));
5627 /* Quiet this warning. */
5628 mips_cprestore_valid
= 1;
5630 if (mips_opts
.noreorder
)
5631 macro_build (NULL
, "nop", "");
5632 expr1
.X_add_number
= mips_cprestore_offset
;
5633 macro_build_ldst_constoffset (&expr1
, ADDRESS_LOAD_INSN
,
5636 HAVE_64BIT_ADDRESSES
);
5662 /* Itbl support may require additional care here. */
5667 /* Itbl support may require additional care here. */
5672 /* Itbl support may require additional care here. */
5677 /* Itbl support may require additional care here. */
5689 if (mips_opts
.arch
== CPU_R4650
)
5691 as_bad (_("opcode not supported on this processor"));
5695 /* Itbl support may require additional care here. */
5700 /* Itbl support may require additional care here. */
5705 /* Itbl support may require additional care here. */
5725 if (breg
== treg
|| coproc
|| lr
)
5747 /* Itbl support may require additional care here. */
5752 /* Itbl support may require additional care here. */
5757 /* Itbl support may require additional care here. */
5762 /* Itbl support may require additional care here. */
5778 if (mips_opts
.arch
== CPU_R4650
)
5780 as_bad (_("opcode not supported on this processor"));
5785 /* Itbl support may require additional care here. */
5789 /* Itbl support may require additional care here. */
5794 /* Itbl support may require additional care here. */
5806 /* Itbl support may require additional care here. */
5807 if (mask
== M_LWC1_AB
5808 || mask
== M_SWC1_AB
5809 || mask
== M_LDC1_AB
5810 || mask
== M_SDC1_AB
5819 /* Sign-extending 32-bit constants makes their handling easier.
5820 The HAVE_64BIT_GPRS... part is due to the linux kernel hack
5822 if ((! HAVE_64BIT_ADDRESSES
5823 && (! HAVE_64BIT_GPRS
&& offset_expr
.X_op
== O_constant
))
5824 && (offset_expr
.X_op
== O_constant
)
5825 && ! ((offset_expr
.X_add_number
& ~((bfd_vma
) 0x7fffffff))
5826 == ~((bfd_vma
) 0x7fffffff)))
5828 if (offset_expr
.X_add_number
& ~((bfd_vma
) 0xffffffff))
5829 as_bad (_("constant too large"));
5831 offset_expr
.X_add_number
= (((offset_expr
.X_add_number
& 0xffffffff)
5832 ^ 0x80000000) - 0x80000000);
5835 if (offset_expr
.X_op
!= O_constant
5836 && offset_expr
.X_op
!= O_symbol
)
5838 as_bad (_("expression too complex"));
5839 offset_expr
.X_op
= O_constant
;
5842 /* A constant expression in PIC code can be handled just as it
5843 is in non PIC code. */
5844 if (mips_pic
== NO_PIC
5845 || offset_expr
.X_op
== O_constant
)
5847 /* If this is a reference to a GP relative symbol, and there
5848 is no base register, we want
5849 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
5850 Otherwise, if there is no base register, we want
5851 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
5852 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5853 If we have a constant, we need two instructions anyhow,
5854 so we always use the latter form.
5856 If we have a base register, and this is a reference to a
5857 GP relative symbol, we want
5858 addu $tempreg,$breg,$gp
5859 <op> $treg,<sym>($tempreg) (BFD_RELOC_GPREL16)
5861 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
5862 addu $tempreg,$tempreg,$breg
5863 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5864 With a constant we always use the latter case.
5866 With 64bit address space and no base register and $at usable,
5868 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5869 lui $at,<sym> (BFD_RELOC_HI16_S)
5870 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
5873 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5874 If we have a base register, we want
5875 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5876 lui $at,<sym> (BFD_RELOC_HI16_S)
5877 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
5881 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5883 Without $at we can't generate the optimal path for superscalar
5884 processors here since this would require two temporary registers.
5885 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5886 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
5888 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
5890 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5891 If we have a base register, we want
5892 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5893 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
5895 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
5897 daddu $tempreg,$tempreg,$breg
5898 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5900 If we have 64-bit addresses, as an optimization, for
5901 addresses which are 32-bit constants (e.g. kseg0/kseg1
5902 addresses) we fall back to the 32-bit address generation
5903 mechanism since it is more efficient. Note that due to
5904 the signed offset used by memory operations, the 32-bit
5905 range is shifted down by 32768 here. This code should
5906 probably attempt to generate 64-bit constants more
5907 efficiently in general.
5909 As an extension for architectures with 64-bit registers,
5910 we don't truncate 64-bit addresses given as literal
5911 constants down to 32 bits, to support existing practice
5912 in the mips64 Linux (the kernel), that compiles source
5913 files with -mabi=64, assembling them as o32 or n32 (with
5914 -Wa,-32 or -Wa,-n32). This is not beautiful, but since
5915 the whole kernel is loaded into a memory region that is
5916 addressable with sign-extended 32-bit addresses, it is
5917 wasteful to compute the upper 32 bits of every
5918 non-literal address, that takes more space and time.
5919 Some day this should probably be implemented as an
5920 assembler option, such that the kernel doesn't have to
5921 use such ugly hacks, even though it will still have to
5922 end up converting the binary to ELF32 for a number of
5923 platforms whose boot loaders don't support ELF64
5925 if ((HAVE_64BIT_ADDRESSES
5926 && ! (offset_expr
.X_op
== O_constant
5927 && IS_SEXT_32BIT_NUM (offset_expr
.X_add_number
+ 0x8000)))
5929 && offset_expr
.X_op
== O_constant
5930 && ! IS_SEXT_32BIT_NUM (offset_expr
.X_add_number
+ 0x8000)))
5932 /* ??? We don't provide a GP-relative alternative for
5933 these macros. It used not to be possible with the
5934 original relaxation code, but it could be done now. */
5936 if (used_at
== 0 && ! mips_opts
.noat
)
5938 macro_build (&offset_expr
, "lui", "t,u", tempreg
,
5939 BFD_RELOC_MIPS_HIGHEST
);
5940 macro_build (&offset_expr
, "lui", "t,u", AT
,
5942 macro_build (&offset_expr
, "daddiu", "t,r,j", tempreg
,
5943 tempreg
, BFD_RELOC_MIPS_HIGHER
);
5945 macro_build (NULL
, "daddu", "d,v,t", AT
, AT
, breg
);
5946 macro_build (NULL
, "dsll32", "d,w,<", tempreg
, tempreg
, 0);
5947 macro_build (NULL
, "daddu", "d,v,t", tempreg
, tempreg
, AT
);
5948 macro_build (&offset_expr
, s
, fmt
, treg
, BFD_RELOC_LO16
,
5954 macro_build (&offset_expr
, "lui", "t,u", tempreg
,
5955 BFD_RELOC_MIPS_HIGHEST
);
5956 macro_build (&offset_expr
, "daddiu", "t,r,j", tempreg
,
5957 tempreg
, BFD_RELOC_MIPS_HIGHER
);
5958 macro_build (NULL
, "dsll", "d,w,<", tempreg
, tempreg
, 16);
5959 macro_build (&offset_expr
, "daddiu", "t,r,j", tempreg
,
5960 tempreg
, BFD_RELOC_HI16_S
);
5961 macro_build (NULL
, "dsll", "d,w,<", tempreg
, tempreg
, 16);
5963 macro_build (NULL
, "daddu", "d,v,t",
5964 tempreg
, tempreg
, breg
);
5965 macro_build (&offset_expr
, s
, fmt
, treg
,
5966 BFD_RELOC_LO16
, tempreg
);
5972 if (offset_expr
.X_op
== O_constant
5973 && ! IS_SEXT_32BIT_NUM (offset_expr
.X_add_number
+ 0x8000))
5974 as_bad (_("load/store address overflow (max 32 bits)"));
5978 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
5979 && ! nopic_need_relax (offset_expr
.X_add_symbol
, 1))
5981 relax_start (offset_expr
.X_add_symbol
);
5982 macro_build (&offset_expr
, s
, fmt
, treg
, BFD_RELOC_GPREL16
,
5987 macro_build_lui (&offset_expr
, tempreg
);
5988 macro_build (&offset_expr
, s
, fmt
, treg
,
5989 BFD_RELOC_LO16
, tempreg
);
5990 if (mips_relax
.sequence
)
5995 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
5996 && ! nopic_need_relax (offset_expr
.X_add_symbol
, 1))
5998 relax_start (offset_expr
.X_add_symbol
);
5999 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6000 tempreg
, breg
, mips_gp_register
);
6001 macro_build (&offset_expr
, s
, fmt
, treg
,
6002 BFD_RELOC_GPREL16
, tempreg
);
6005 macro_build_lui (&offset_expr
, tempreg
);
6006 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6007 tempreg
, tempreg
, breg
);
6008 macro_build (&offset_expr
, s
, fmt
, treg
,
6009 BFD_RELOC_LO16
, tempreg
);
6010 if (mips_relax
.sequence
)
6014 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
6016 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT16
;
6018 /* If this is a reference to an external symbol, we want
6019 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6021 <op> $treg,0($tempreg)
6023 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6025 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
6026 <op> $treg,0($tempreg)
6029 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
6030 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST)
6032 If there is a base register, we add it to $tempreg before
6033 the <op>. If there is a constant, we stick it in the
6034 <op> instruction. We don't handle constants larger than
6035 16 bits, because we have no way to load the upper 16 bits
6036 (actually, we could handle them for the subset of cases
6037 in which we are not using $at). */
6038 assert (offset_expr
.X_op
== O_symbol
);
6041 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
6042 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
6044 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6045 tempreg
, tempreg
, breg
);
6046 macro_build (&offset_expr
, s
, fmt
, treg
,
6047 BFD_RELOC_MIPS_GOT_OFST
, tempreg
);
6054 expr1
.X_add_number
= offset_expr
.X_add_number
;
6055 offset_expr
.X_add_number
= 0;
6056 if (expr1
.X_add_number
< -0x8000
6057 || expr1
.X_add_number
>= 0x8000)
6058 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6059 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
6060 lw_reloc_type
, mips_gp_register
);
6062 relax_start (offset_expr
.X_add_symbol
);
6064 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j", tempreg
,
6065 tempreg
, BFD_RELOC_LO16
);
6068 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6069 tempreg
, tempreg
, breg
);
6070 macro_build (&expr1
, s
, fmt
, treg
, BFD_RELOC_LO16
, tempreg
);
6072 else if (mips_pic
== SVR4_PIC
&& ! HAVE_NEWABI
)
6076 /* If this is a reference to an external symbol, we want
6077 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
6078 addu $tempreg,$tempreg,$gp
6079 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
6080 <op> $treg,0($tempreg)
6082 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6084 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
6085 <op> $treg,0($tempreg)
6086 If there is a base register, we add it to $tempreg before
6087 the <op>. If there is a constant, we stick it in the
6088 <op> instruction. We don't handle constants larger than
6089 16 bits, because we have no way to load the upper 16 bits
6090 (actually, we could handle them for the subset of cases
6091 in which we are not using $at). */
6092 assert (offset_expr
.X_op
== O_symbol
);
6093 expr1
.X_add_number
= offset_expr
.X_add_number
;
6094 offset_expr
.X_add_number
= 0;
6095 if (expr1
.X_add_number
< -0x8000
6096 || expr1
.X_add_number
>= 0x8000)
6097 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6098 gpdelay
= reg_needs_delay (mips_gp_register
);
6099 relax_start (offset_expr
.X_add_symbol
);
6100 macro_build (&offset_expr
, "lui", "t,u", tempreg
,
6101 BFD_RELOC_MIPS_GOT_HI16
);
6102 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", tempreg
, tempreg
,
6104 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
6105 BFD_RELOC_MIPS_GOT_LO16
, tempreg
);
6108 macro_build (NULL
, "nop", "");
6109 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
6110 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
6112 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j", tempreg
,
6113 tempreg
, BFD_RELOC_LO16
);
6117 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6118 tempreg
, tempreg
, breg
);
6119 macro_build (&expr1
, s
, fmt
, treg
, BFD_RELOC_LO16
, tempreg
);
6121 else if (mips_pic
== SVR4_PIC
&& HAVE_NEWABI
)
6123 /* If this is a reference to an external symbol, we want
6124 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
6125 add $tempreg,$tempreg,$gp
6126 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
6127 <op> $treg,<ofst>($tempreg)
6128 Otherwise, for local symbols, we want:
6129 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
6130 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST) */
6131 assert (offset_expr
.X_op
== O_symbol
);
6132 expr1
.X_add_number
= offset_expr
.X_add_number
;
6133 offset_expr
.X_add_number
= 0;
6134 if (expr1
.X_add_number
< -0x8000
6135 || expr1
.X_add_number
>= 0x8000)
6136 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6137 relax_start (offset_expr
.X_add_symbol
);
6138 macro_build (&offset_expr
, "lui", "t,u", tempreg
,
6139 BFD_RELOC_MIPS_GOT_HI16
);
6140 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", tempreg
, tempreg
,
6142 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
6143 BFD_RELOC_MIPS_GOT_LO16
, tempreg
);
6145 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6146 tempreg
, tempreg
, breg
);
6147 macro_build (&expr1
, s
, fmt
, treg
, BFD_RELOC_LO16
, tempreg
);
6150 offset_expr
.X_add_number
= expr1
.X_add_number
;
6151 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
6152 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
6154 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6155 tempreg
, tempreg
, breg
);
6156 macro_build (&offset_expr
, s
, fmt
, treg
,
6157 BFD_RELOC_MIPS_GOT_OFST
, tempreg
);
6170 load_register (treg
, &imm_expr
, 0);
6174 load_register (treg
, &imm_expr
, 1);
6178 if (imm_expr
.X_op
== O_constant
)
6180 load_register (AT
, &imm_expr
, 0);
6181 macro_build (NULL
, "mtc1", "t,G", AT
, treg
);
6186 assert (offset_expr
.X_op
== O_symbol
6187 && strcmp (segment_name (S_GET_SEGMENT
6188 (offset_expr
.X_add_symbol
)),
6190 && offset_expr
.X_add_number
== 0);
6191 macro_build (&offset_expr
, "lwc1", "T,o(b)", treg
,
6192 BFD_RELOC_MIPS_LITERAL
, mips_gp_register
);
6197 /* Check if we have a constant in IMM_EXPR. If the GPRs are 64 bits
6198 wide, IMM_EXPR is the entire value. Otherwise IMM_EXPR is the high
6199 order 32 bits of the value and the low order 32 bits are either
6200 zero or in OFFSET_EXPR. */
6201 if (imm_expr
.X_op
== O_constant
|| imm_expr
.X_op
== O_big
)
6203 if (HAVE_64BIT_GPRS
)
6204 load_register (treg
, &imm_expr
, 1);
6209 if (target_big_endian
)
6221 load_register (hreg
, &imm_expr
, 0);
6224 if (offset_expr
.X_op
== O_absent
)
6225 move_register (lreg
, 0);
6228 assert (offset_expr
.X_op
== O_constant
);
6229 load_register (lreg
, &offset_expr
, 0);
6236 /* We know that sym is in the .rdata section. First we get the
6237 upper 16 bits of the address. */
6238 if (mips_pic
== NO_PIC
)
6240 macro_build_lui (&offset_expr
, AT
);
6242 else if (mips_pic
== SVR4_PIC
)
6244 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", AT
,
6245 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
6250 /* Now we load the register(s). */
6251 if (HAVE_64BIT_GPRS
)
6252 macro_build (&offset_expr
, "ld", "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
6255 macro_build (&offset_expr
, "lw", "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
6258 /* FIXME: How in the world do we deal with the possible
6260 offset_expr
.X_add_number
+= 4;
6261 macro_build (&offset_expr
, "lw", "t,o(b)",
6262 treg
+ 1, BFD_RELOC_LO16
, AT
);
6268 /* Check if we have a constant in IMM_EXPR. If the FPRs are 64 bits
6269 wide, IMM_EXPR is the entire value and the GPRs are known to be 64
6270 bits wide as well. Otherwise IMM_EXPR is the high order 32 bits of
6271 the value and the low order 32 bits are either zero or in
6273 if (imm_expr
.X_op
== O_constant
|| imm_expr
.X_op
== O_big
)
6275 load_register (AT
, &imm_expr
, HAVE_64BIT_FPRS
);
6276 if (HAVE_64BIT_FPRS
)
6278 assert (HAVE_64BIT_GPRS
);
6279 macro_build (NULL
, "dmtc1", "t,S", AT
, treg
);
6283 macro_build (NULL
, "mtc1", "t,G", AT
, treg
+ 1);
6284 if (offset_expr
.X_op
== O_absent
)
6285 macro_build (NULL
, "mtc1", "t,G", 0, treg
);
6288 assert (offset_expr
.X_op
== O_constant
);
6289 load_register (AT
, &offset_expr
, 0);
6290 macro_build (NULL
, "mtc1", "t,G", AT
, treg
);
6296 assert (offset_expr
.X_op
== O_symbol
6297 && offset_expr
.X_add_number
== 0);
6298 s
= segment_name (S_GET_SEGMENT (offset_expr
.X_add_symbol
));
6299 if (strcmp (s
, ".lit8") == 0)
6301 if (mips_opts
.isa
!= ISA_MIPS1
)
6303 macro_build (&offset_expr
, "ldc1", "T,o(b)", treg
,
6304 BFD_RELOC_MIPS_LITERAL
, mips_gp_register
);
6307 breg
= mips_gp_register
;
6308 r
= BFD_RELOC_MIPS_LITERAL
;
6313 assert (strcmp (s
, RDATA_SECTION_NAME
) == 0);
6314 if (mips_pic
== SVR4_PIC
)
6315 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", AT
,
6316 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
6319 /* FIXME: This won't work for a 64 bit address. */
6320 macro_build_lui (&offset_expr
, AT
);
6323 if (mips_opts
.isa
!= ISA_MIPS1
)
6325 macro_build (&offset_expr
, "ldc1", "T,o(b)",
6326 treg
, BFD_RELOC_LO16
, AT
);
6335 if (mips_opts
.arch
== CPU_R4650
)
6337 as_bad (_("opcode not supported on this processor"));
6340 /* Even on a big endian machine $fn comes before $fn+1. We have
6341 to adjust when loading from memory. */
6344 assert (mips_opts
.isa
== ISA_MIPS1
);
6345 macro_build (&offset_expr
, "lwc1", "T,o(b)",
6346 target_big_endian
? treg
+ 1 : treg
, r
, breg
);
6347 /* FIXME: A possible overflow which I don't know how to deal
6349 offset_expr
.X_add_number
+= 4;
6350 macro_build (&offset_expr
, "lwc1", "T,o(b)",
6351 target_big_endian
? treg
: treg
+ 1, r
, breg
);
6359 * The MIPS assembler seems to check for X_add_number not
6360 * being double aligned and generating:
6363 * addiu at,at,%lo(foo+1)
6366 * But, the resulting address is the same after relocation so why
6367 * generate the extra instruction?
6369 if (mips_opts
.arch
== CPU_R4650
)
6371 as_bad (_("opcode not supported on this processor"));
6374 /* Itbl support may require additional care here. */
6376 if (mips_opts
.isa
!= ISA_MIPS1
)
6387 if (mips_opts
.arch
== CPU_R4650
)
6389 as_bad (_("opcode not supported on this processor"));
6393 if (mips_opts
.isa
!= ISA_MIPS1
)
6401 /* Itbl support may require additional care here. */
6406 if (HAVE_64BIT_GPRS
)
6417 if (HAVE_64BIT_GPRS
)
6427 if (offset_expr
.X_op
!= O_symbol
6428 && offset_expr
.X_op
!= O_constant
)
6430 as_bad (_("expression too complex"));
6431 offset_expr
.X_op
= O_constant
;
6434 /* Even on a big endian machine $fn comes before $fn+1. We have
6435 to adjust when loading from memory. We set coproc if we must
6436 load $fn+1 first. */
6437 /* Itbl support may require additional care here. */
6438 if (! target_big_endian
)
6441 if (mips_pic
== NO_PIC
6442 || offset_expr
.X_op
== O_constant
)
6444 /* If this is a reference to a GP relative symbol, we want
6445 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
6446 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_GPREL16)
6447 If we have a base register, we use this
6449 <op> $treg,<sym>($at) (BFD_RELOC_GPREL16)
6450 <op> $treg+1,<sym>+4($at) (BFD_RELOC_GPREL16)
6451 If this is not a GP relative symbol, we want
6452 lui $at,<sym> (BFD_RELOC_HI16_S)
6453 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
6454 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
6455 If there is a base register, we add it to $at after the
6456 lui instruction. If there is a constant, we always use
6458 if ((valueT
) offset_expr
.X_add_number
> MAX_GPREL_OFFSET
6459 || nopic_need_relax (offset_expr
.X_add_symbol
, 1))
6463 relax_start (offset_expr
.X_add_symbol
);
6466 tempreg
= mips_gp_register
;
6471 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6472 AT
, breg
, mips_gp_register
);
6477 /* Itbl support may require additional care here. */
6478 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
+ 1 : treg
,
6479 BFD_RELOC_GPREL16
, tempreg
);
6480 offset_expr
.X_add_number
+= 4;
6482 /* Set mips_optimize to 2 to avoid inserting an
6484 hold_mips_optimize
= mips_optimize
;
6486 /* Itbl support may require additional care here. */
6487 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
: treg
+ 1,
6488 BFD_RELOC_GPREL16
, tempreg
);
6489 mips_optimize
= hold_mips_optimize
;
6493 /* We just generated two relocs. When tc_gen_reloc
6494 handles this case, it will skip the first reloc and
6495 handle the second. The second reloc already has an
6496 extra addend of 4, which we added above. We must
6497 subtract it out, and then subtract another 4 to make
6498 the first reloc come out right. The second reloc
6499 will come out right because we are going to add 4 to
6500 offset_expr when we build its instruction below.
6502 If we have a symbol, then we don't want to include
6503 the offset, because it will wind up being included
6504 when we generate the reloc. */
6506 if (offset_expr
.X_op
== O_constant
)
6507 offset_expr
.X_add_number
-= 8;
6510 offset_expr
.X_add_number
= -4;
6511 offset_expr
.X_op
= O_constant
;
6514 macro_build_lui (&offset_expr
, AT
);
6516 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
6517 /* Itbl support may require additional care here. */
6518 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
+ 1 : treg
,
6519 BFD_RELOC_LO16
, AT
);
6520 /* FIXME: How do we handle overflow here? */
6521 offset_expr
.X_add_number
+= 4;
6522 /* Itbl support may require additional care here. */
6523 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
: treg
+ 1,
6524 BFD_RELOC_LO16
, AT
);
6525 if (mips_relax
.sequence
)
6528 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
6530 /* If this is a reference to an external symbol, we want
6531 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6536 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6538 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
6539 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
6540 If there is a base register we add it to $at before the
6541 lwc1 instructions. If there is a constant we include it
6542 in the lwc1 instructions. */
6544 expr1
.X_add_number
= offset_expr
.X_add_number
;
6545 if (expr1
.X_add_number
< -0x8000
6546 || expr1
.X_add_number
>= 0x8000 - 4)
6547 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6548 load_got_offset (AT
, &offset_expr
);
6551 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
6553 /* Set mips_optimize to 2 to avoid inserting an undesired
6555 hold_mips_optimize
= mips_optimize
;
6558 /* Itbl support may require additional care here. */
6559 relax_start (offset_expr
.X_add_symbol
);
6560 macro_build (&expr1
, s
, fmt
, coproc
? treg
+ 1 : treg
,
6561 BFD_RELOC_LO16
, AT
);
6562 expr1
.X_add_number
+= 4;
6563 macro_build (&expr1
, s
, fmt
, coproc
? treg
: treg
+ 1,
6564 BFD_RELOC_LO16
, AT
);
6566 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
+ 1 : treg
,
6567 BFD_RELOC_LO16
, AT
);
6568 offset_expr
.X_add_number
+= 4;
6569 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
: treg
+ 1,
6570 BFD_RELOC_LO16
, AT
);
6573 mips_optimize
= hold_mips_optimize
;
6575 else if (mips_pic
== SVR4_PIC
)
6579 /* If this is a reference to an external symbol, we want
6580 lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16)
6582 lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16)
6587 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6589 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
6590 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
6591 If there is a base register we add it to $at before the
6592 lwc1 instructions. If there is a constant we include it
6593 in the lwc1 instructions. */
6595 expr1
.X_add_number
= offset_expr
.X_add_number
;
6596 offset_expr
.X_add_number
= 0;
6597 if (expr1
.X_add_number
< -0x8000
6598 || expr1
.X_add_number
>= 0x8000 - 4)
6599 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6600 gpdelay
= reg_needs_delay (mips_gp_register
);
6601 relax_start (offset_expr
.X_add_symbol
);
6602 macro_build (&offset_expr
, "lui", "t,u",
6603 AT
, BFD_RELOC_MIPS_GOT_HI16
);
6604 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6605 AT
, AT
, mips_gp_register
);
6606 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
6607 AT
, BFD_RELOC_MIPS_GOT_LO16
, AT
);
6610 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
6611 /* Itbl support may require additional care here. */
6612 macro_build (&expr1
, s
, fmt
, coproc
? treg
+ 1 : treg
,
6613 BFD_RELOC_LO16
, AT
);
6614 expr1
.X_add_number
+= 4;
6616 /* Set mips_optimize to 2 to avoid inserting an undesired
6618 hold_mips_optimize
= mips_optimize
;
6620 /* Itbl support may require additional care here. */
6621 macro_build (&expr1
, s
, fmt
, coproc
? treg
: treg
+ 1,
6622 BFD_RELOC_LO16
, AT
);
6623 mips_optimize
= hold_mips_optimize
;
6624 expr1
.X_add_number
-= 4;
6627 offset_expr
.X_add_number
= expr1
.X_add_number
;
6629 macro_build (NULL
, "nop", "");
6630 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", AT
,
6631 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
6634 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
6635 /* Itbl support may require additional care here. */
6636 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
+ 1 : treg
,
6637 BFD_RELOC_LO16
, AT
);
6638 offset_expr
.X_add_number
+= 4;
6640 /* Set mips_optimize to 2 to avoid inserting an undesired
6642 hold_mips_optimize
= mips_optimize
;
6644 /* Itbl support may require additional care here. */
6645 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
: treg
+ 1,
6646 BFD_RELOC_LO16
, AT
);
6647 mips_optimize
= hold_mips_optimize
;
6664 assert (HAVE_32BIT_ADDRESSES
);
6665 macro_build (&offset_expr
, s
, "t,o(b)", treg
, BFD_RELOC_LO16
, breg
);
6666 offset_expr
.X_add_number
+= 4;
6667 macro_build (&offset_expr
, s
, "t,o(b)", treg
+ 1, BFD_RELOC_LO16
, breg
);
6670 /* New code added to support COPZ instructions.
6671 This code builds table entries out of the macros in mip_opcodes.
6672 R4000 uses interlocks to handle coproc delays.
6673 Other chips (like the R3000) require nops to be inserted for delays.
6675 FIXME: Currently, we require that the user handle delays.
6676 In order to fill delay slots for non-interlocked chips,
6677 we must have a way to specify delays based on the coprocessor.
6678 Eg. 4 cycles if load coproc reg from memory, 1 if in cache, etc.
6679 What are the side-effects of the cop instruction?
6680 What cache support might we have and what are its effects?
6681 Both coprocessor & memory require delays. how long???
6682 What registers are read/set/modified?
6684 If an itbl is provided to interpret cop instructions,
6685 this knowledge can be encoded in the itbl spec. */
6699 /* For now we just do C (same as Cz). The parameter will be
6700 stored in insn_opcode by mips_ip. */
6701 macro_build (NULL
, s
, "C", ip
->insn_opcode
);
6705 move_register (dreg
, sreg
);
6708 #ifdef LOSING_COMPILER
6710 /* Try and see if this is a new itbl instruction.
6711 This code builds table entries out of the macros in mip_opcodes.
6712 FIXME: For now we just assemble the expression and pass it's
6713 value along as a 32-bit immediate.
6714 We may want to have the assembler assemble this value,
6715 so that we gain the assembler's knowledge of delay slots,
6717 Would it be more efficient to use mask (id) here? */
6718 if (itbl_have_entries
6719 && (immed_expr
= itbl_assemble (ip
->insn_mo
->name
, "")))
6721 s
= ip
->insn_mo
->name
;
6723 coproc
= ITBL_DECODE_PNUM (immed_expr
);;
6724 macro_build (&immed_expr
, s
, "C");
6731 as_warn (_("Macro used $at after \".set noat\""));
6735 macro2 (struct mips_cl_insn
*ip
)
6737 register int treg
, sreg
, dreg
, breg
;
6752 bfd_reloc_code_real_type r
;
6754 treg
= (ip
->insn_opcode
>> 16) & 0x1f;
6755 dreg
= (ip
->insn_opcode
>> 11) & 0x1f;
6756 sreg
= breg
= (ip
->insn_opcode
>> 21) & 0x1f;
6757 mask
= ip
->insn_mo
->mask
;
6759 expr1
.X_op
= O_constant
;
6760 expr1
.X_op_symbol
= NULL
;
6761 expr1
.X_add_symbol
= NULL
;
6762 expr1
.X_add_number
= 1;
6766 #endif /* LOSING_COMPILER */
6771 macro_build (NULL
, dbl
? "dmultu" : "multu", "s,t", sreg
, treg
);
6772 macro_build (NULL
, "mflo", "d", dreg
);
6778 /* The MIPS assembler some times generates shifts and adds. I'm
6779 not trying to be that fancy. GCC should do this for us
6781 load_register (AT
, &imm_expr
, dbl
);
6782 macro_build (NULL
, dbl
? "dmult" : "mult", "s,t", sreg
, AT
);
6783 macro_build (NULL
, "mflo", "d", dreg
);
6796 mips_emit_delays (TRUE
);
6797 ++mips_opts
.noreorder
;
6798 mips_any_noreorder
= 1;
6800 load_register (AT
, &imm_expr
, dbl
);
6801 macro_build (NULL
, dbl
? "dmult" : "mult", "s,t", sreg
, imm
? AT
: treg
);
6802 macro_build (NULL
, "mflo", "d", dreg
);
6803 macro_build (NULL
, dbl
? "dsra32" : "sra", "d,w,<", dreg
, dreg
, RA
);
6804 macro_build (NULL
, "mfhi", "d", AT
);
6806 macro_build (NULL
, "tne", "s,t,q", dreg
, AT
, 6);
6809 expr1
.X_add_number
= 8;
6810 macro_build (&expr1
, "beq", "s,t,p", dreg
, AT
);
6811 macro_build (NULL
, "nop", "", 0);
6812 macro_build (NULL
, "break", "c", 6);
6814 --mips_opts
.noreorder
;
6815 macro_build (NULL
, "mflo", "d", dreg
);
6828 mips_emit_delays (TRUE
);
6829 ++mips_opts
.noreorder
;
6830 mips_any_noreorder
= 1;
6832 load_register (AT
, &imm_expr
, dbl
);
6833 macro_build (NULL
, dbl
? "dmultu" : "multu", "s,t",
6834 sreg
, imm
? AT
: treg
);
6835 macro_build (NULL
, "mfhi", "d", AT
);
6836 macro_build (NULL
, "mflo", "d", dreg
);
6838 macro_build (NULL
, "tne", "s,t,q", AT
, 0, 6);
6841 expr1
.X_add_number
= 8;
6842 macro_build (&expr1
, "beq", "s,t,p", AT
, 0);
6843 macro_build (NULL
, "nop", "", 0);
6844 macro_build (NULL
, "break", "c", 6);
6846 --mips_opts
.noreorder
;
6850 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
6862 macro_build (NULL
, "dnegu", "d,w", tempreg
, treg
);
6863 macro_build (NULL
, "drorv", "d,t,s", dreg
, sreg
, tempreg
);
6868 macro_build (NULL
, "dsubu", "d,v,t", AT
, 0, treg
);
6869 macro_build (NULL
, "dsrlv", "d,t,s", AT
, sreg
, AT
);
6870 macro_build (NULL
, "dsllv", "d,t,s", dreg
, sreg
, treg
);
6871 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
6875 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
6887 macro_build (NULL
, "negu", "d,w", tempreg
, treg
);
6888 macro_build (NULL
, "rorv", "d,t,s", dreg
, sreg
, tempreg
);
6893 macro_build (NULL
, "subu", "d,v,t", AT
, 0, treg
);
6894 macro_build (NULL
, "srlv", "d,t,s", AT
, sreg
, AT
);
6895 macro_build (NULL
, "sllv", "d,t,s", dreg
, sreg
, treg
);
6896 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
6904 if (imm_expr
.X_op
!= O_constant
)
6905 as_bad (_("Improper rotate count"));
6906 rot
= imm_expr
.X_add_number
& 0x3f;
6907 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
6909 rot
= (64 - rot
) & 0x3f;
6911 macro_build (NULL
, "dror32", "d,w,<", dreg
, sreg
, rot
- 32);
6913 macro_build (NULL
, "dror", "d,w,<", dreg
, sreg
, rot
);
6918 macro_build (NULL
, "dsrl", "d,w,<", dreg
, sreg
, 0);
6921 l
= (rot
< 0x20) ? "dsll" : "dsll32";
6922 r
= ((0x40 - rot
) < 0x20) ? "dsrl" : "dsrl32";
6924 macro_build (NULL
, l
, "d,w,<", AT
, sreg
, rot
);
6925 macro_build (NULL
, r
, "d,w,<", dreg
, sreg
, (0x20 - rot
) & 0x1f);
6926 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
6934 if (imm_expr
.X_op
!= O_constant
)
6935 as_bad (_("Improper rotate count"));
6936 rot
= imm_expr
.X_add_number
& 0x1f;
6937 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
6939 macro_build (NULL
, "ror", "d,w,<", dreg
, sreg
, (32 - rot
) & 0x1f);
6944 macro_build (NULL
, "srl", "d,w,<", dreg
, sreg
, 0);
6947 macro_build (NULL
, "sll", "d,w,<", AT
, sreg
, rot
);
6948 macro_build (NULL
, "srl", "d,w,<", dreg
, sreg
, (0x20 - rot
) & 0x1f);
6949 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
6954 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
6956 macro_build (NULL
, "drorv", "d,t,s", dreg
, sreg
, treg
);
6959 macro_build (NULL
, "dsubu", "d,v,t", AT
, 0, treg
);
6960 macro_build (NULL
, "dsllv", "d,t,s", AT
, sreg
, AT
);
6961 macro_build (NULL
, "dsrlv", "d,t,s", dreg
, sreg
, treg
);
6962 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
6966 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
6968 macro_build (NULL
, "rorv", "d,t,s", dreg
, sreg
, treg
);
6971 macro_build (NULL
, "subu", "d,v,t", AT
, 0, treg
);
6972 macro_build (NULL
, "sllv", "d,t,s", AT
, sreg
, AT
);
6973 macro_build (NULL
, "srlv", "d,t,s", dreg
, sreg
, treg
);
6974 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
6982 if (imm_expr
.X_op
!= O_constant
)
6983 as_bad (_("Improper rotate count"));
6984 rot
= imm_expr
.X_add_number
& 0x3f;
6985 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
6988 macro_build (NULL
, "dror32", "d,w,<", dreg
, sreg
, rot
- 32);
6990 macro_build (NULL
, "dror", "d,w,<", dreg
, sreg
, rot
);
6995 macro_build (NULL
, "dsrl", "d,w,<", dreg
, sreg
, 0);
6998 r
= (rot
< 0x20) ? "dsrl" : "dsrl32";
6999 l
= ((0x40 - rot
) < 0x20) ? "dsll" : "dsll32";
7001 macro_build (NULL
, r
, "d,w,<", AT
, sreg
, rot
);
7002 macro_build (NULL
, l
, "d,w,<", dreg
, sreg
, (0x20 - rot
) & 0x1f);
7003 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
7011 if (imm_expr
.X_op
!= O_constant
)
7012 as_bad (_("Improper rotate count"));
7013 rot
= imm_expr
.X_add_number
& 0x1f;
7014 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
7016 macro_build (NULL
, "ror", "d,w,<", dreg
, sreg
, rot
);
7021 macro_build (NULL
, "srl", "d,w,<", dreg
, sreg
, 0);
7024 macro_build (NULL
, "srl", "d,w,<", AT
, sreg
, rot
);
7025 macro_build (NULL
, "sll", "d,w,<", dreg
, sreg
, (0x20 - rot
) & 0x1f);
7026 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
7031 if (mips_opts
.arch
== CPU_R4650
)
7033 as_bad (_("opcode not supported on this processor"));
7036 assert (mips_opts
.isa
== ISA_MIPS1
);
7037 /* Even on a big endian machine $fn comes before $fn+1. We have
7038 to adjust when storing to memory. */
7039 macro_build (&offset_expr
, "swc1", "T,o(b)",
7040 target_big_endian
? treg
+ 1 : treg
, BFD_RELOC_LO16
, breg
);
7041 offset_expr
.X_add_number
+= 4;
7042 macro_build (&offset_expr
, "swc1", "T,o(b)",
7043 target_big_endian
? treg
: treg
+ 1, BFD_RELOC_LO16
, breg
);
7048 macro_build (&expr1
, "sltiu", "t,r,j", dreg
, treg
, BFD_RELOC_LO16
);
7050 macro_build (&expr1
, "sltiu", "t,r,j", dreg
, sreg
, BFD_RELOC_LO16
);
7053 macro_build (NULL
, "xor", "d,v,t", dreg
, sreg
, treg
);
7054 macro_build (&expr1
, "sltiu", "t,r,j", dreg
, dreg
, BFD_RELOC_LO16
);
7059 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
7061 macro_build (&expr1
, "sltiu", "t,r,j", dreg
, sreg
, BFD_RELOC_LO16
);
7066 as_warn (_("Instruction %s: result is always false"),
7068 move_register (dreg
, 0);
7071 if (imm_expr
.X_op
== O_constant
7072 && imm_expr
.X_add_number
>= 0
7073 && imm_expr
.X_add_number
< 0x10000)
7075 macro_build (&imm_expr
, "xori", "t,r,i", dreg
, sreg
, BFD_RELOC_LO16
);
7078 else if (imm_expr
.X_op
== O_constant
7079 && imm_expr
.X_add_number
> -0x8000
7080 && imm_expr
.X_add_number
< 0)
7082 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
7083 macro_build (&imm_expr
, HAVE_32BIT_GPRS
? "addiu" : "daddiu",
7084 "t,r,j", dreg
, sreg
, BFD_RELOC_LO16
);
7089 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7090 macro_build (NULL
, "xor", "d,v,t", dreg
, sreg
, AT
);
7093 macro_build (&expr1
, "sltiu", "t,r,j", dreg
, dreg
, BFD_RELOC_LO16
);
7098 case M_SGE
: /* sreg >= treg <==> not (sreg < treg) */
7104 macro_build (NULL
, s
, "d,v,t", dreg
, sreg
, treg
);
7105 macro_build (&expr1
, "xori", "t,r,i", dreg
, dreg
, BFD_RELOC_LO16
);
7108 case M_SGE_I
: /* sreg >= I <==> not (sreg < I) */
7110 if (imm_expr
.X_op
== O_constant
7111 && imm_expr
.X_add_number
>= -0x8000
7112 && imm_expr
.X_add_number
< 0x8000)
7114 macro_build (&imm_expr
, mask
== M_SGE_I
? "slti" : "sltiu", "t,r,j",
7115 dreg
, sreg
, BFD_RELOC_LO16
);
7120 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7121 macro_build (NULL
, mask
== M_SGE_I
? "slt" : "sltu", "d,v,t",
7125 macro_build (&expr1
, "xori", "t,r,i", dreg
, dreg
, BFD_RELOC_LO16
);
7130 case M_SGT
: /* sreg > treg <==> treg < sreg */
7136 macro_build (NULL
, s
, "d,v,t", dreg
, treg
, sreg
);
7139 case M_SGT_I
: /* sreg > I <==> I < sreg */
7145 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7146 macro_build (NULL
, s
, "d,v,t", dreg
, AT
, sreg
);
7149 case M_SLE
: /* sreg <= treg <==> treg >= sreg <==> not (treg < sreg) */
7155 macro_build (NULL
, s
, "d,v,t", dreg
, treg
, sreg
);
7156 macro_build (&expr1
, "xori", "t,r,i", dreg
, dreg
, BFD_RELOC_LO16
);
7159 case M_SLE_I
: /* sreg <= I <==> I >= sreg <==> not (I < sreg) */
7165 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7166 macro_build (NULL
, s
, "d,v,t", dreg
, AT
, sreg
);
7167 macro_build (&expr1
, "xori", "t,r,i", dreg
, dreg
, BFD_RELOC_LO16
);
7171 if (imm_expr
.X_op
== O_constant
7172 && imm_expr
.X_add_number
>= -0x8000
7173 && imm_expr
.X_add_number
< 0x8000)
7175 macro_build (&imm_expr
, "slti", "t,r,j", dreg
, sreg
, BFD_RELOC_LO16
);
7178 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7179 macro_build (NULL
, "slt", "d,v,t", dreg
, sreg
, AT
);
7183 if (imm_expr
.X_op
== O_constant
7184 && imm_expr
.X_add_number
>= -0x8000
7185 && imm_expr
.X_add_number
< 0x8000)
7187 macro_build (&imm_expr
, "sltiu", "t,r,j", dreg
, sreg
,
7191 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7192 macro_build (NULL
, "sltu", "d,v,t", dreg
, sreg
, AT
);
7197 macro_build (NULL
, "sltu", "d,v,t", dreg
, 0, treg
);
7199 macro_build (NULL
, "sltu", "d,v,t", dreg
, 0, sreg
);
7202 macro_build (NULL
, "xor", "d,v,t", dreg
, sreg
, treg
);
7203 macro_build (NULL
, "sltu", "d,v,t", dreg
, 0, dreg
);
7208 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
7210 macro_build (NULL
, "sltu", "d,v,t", dreg
, 0, sreg
);
7215 as_warn (_("Instruction %s: result is always true"),
7217 macro_build (&expr1
, HAVE_32BIT_GPRS
? "addiu" : "daddiu", "t,r,j",
7218 dreg
, 0, BFD_RELOC_LO16
);
7221 if (imm_expr
.X_op
== O_constant
7222 && imm_expr
.X_add_number
>= 0
7223 && imm_expr
.X_add_number
< 0x10000)
7225 macro_build (&imm_expr
, "xori", "t,r,i", dreg
, sreg
, BFD_RELOC_LO16
);
7228 else if (imm_expr
.X_op
== O_constant
7229 && imm_expr
.X_add_number
> -0x8000
7230 && imm_expr
.X_add_number
< 0)
7232 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
7233 macro_build (&imm_expr
, HAVE_32BIT_GPRS
? "addiu" : "daddiu",
7234 "t,r,j", dreg
, sreg
, BFD_RELOC_LO16
);
7239 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7240 macro_build (NULL
, "xor", "d,v,t", dreg
, sreg
, AT
);
7243 macro_build (NULL
, "sltu", "d,v,t", dreg
, 0, dreg
);
7251 if (imm_expr
.X_op
== O_constant
7252 && imm_expr
.X_add_number
> -0x8000
7253 && imm_expr
.X_add_number
<= 0x8000)
7255 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
7256 macro_build (&imm_expr
, dbl
? "daddi" : "addi", "t,r,j",
7257 dreg
, sreg
, BFD_RELOC_LO16
);
7260 load_register (AT
, &imm_expr
, dbl
);
7261 macro_build (NULL
, dbl
? "dsub" : "sub", "d,v,t", dreg
, sreg
, AT
);
7267 if (imm_expr
.X_op
== O_constant
7268 && imm_expr
.X_add_number
> -0x8000
7269 && imm_expr
.X_add_number
<= 0x8000)
7271 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
7272 macro_build (&imm_expr
, dbl
? "daddiu" : "addiu", "t,r,j",
7273 dreg
, sreg
, BFD_RELOC_LO16
);
7276 load_register (AT
, &imm_expr
, dbl
);
7277 macro_build (NULL
, dbl
? "dsubu" : "subu", "d,v,t", dreg
, sreg
, AT
);
7298 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7299 macro_build (NULL
, s
, "s,t", sreg
, AT
);
7304 assert (mips_opts
.isa
== ISA_MIPS1
);
7305 sreg
= (ip
->insn_opcode
>> 11) & 0x1f; /* floating reg */
7306 dreg
= (ip
->insn_opcode
>> 06) & 0x1f; /* floating reg */
7309 * Is the double cfc1 instruction a bug in the mips assembler;
7310 * or is there a reason for it?
7312 mips_emit_delays (TRUE
);
7313 ++mips_opts
.noreorder
;
7314 mips_any_noreorder
= 1;
7315 macro_build (NULL
, "cfc1", "t,G", treg
, RA
);
7316 macro_build (NULL
, "cfc1", "t,G", treg
, RA
);
7317 macro_build (NULL
, "nop", "");
7318 expr1
.X_add_number
= 3;
7319 macro_build (&expr1
, "ori", "t,r,i", AT
, treg
, BFD_RELOC_LO16
);
7320 expr1
.X_add_number
= 2;
7321 macro_build (&expr1
, "xori", "t,r,i", AT
, AT
, BFD_RELOC_LO16
);
7322 macro_build (NULL
, "ctc1", "t,G", AT
, RA
);
7323 macro_build (NULL
, "nop", "");
7324 macro_build (NULL
, mask
== M_TRUNCWD
? "cvt.w.d" : "cvt.w.s", "D,S",
7326 macro_build (NULL
, "ctc1", "t,G", treg
, RA
);
7327 macro_build (NULL
, "nop", "");
7328 --mips_opts
.noreorder
;
7337 if (offset_expr
.X_add_number
>= 0x7fff)
7338 as_bad (_("operand overflow"));
7339 if (! target_big_endian
)
7340 ++offset_expr
.X_add_number
;
7341 macro_build (&offset_expr
, s
, "t,o(b)", AT
, BFD_RELOC_LO16
, breg
);
7342 if (! target_big_endian
)
7343 --offset_expr
.X_add_number
;
7345 ++offset_expr
.X_add_number
;
7346 macro_build (&offset_expr
, "lbu", "t,o(b)", treg
, BFD_RELOC_LO16
, breg
);
7347 macro_build (NULL
, "sll", "d,w,<", AT
, AT
, 8);
7348 macro_build (NULL
, "or", "d,v,t", treg
, treg
, AT
);
7361 if (offset_expr
.X_add_number
>= 0x8000 - off
)
7362 as_bad (_("operand overflow"));
7367 if (! target_big_endian
)
7368 offset_expr
.X_add_number
+= off
;
7369 macro_build (&offset_expr
, s
, "t,o(b)", tempreg
, BFD_RELOC_LO16
, breg
);
7370 if (! target_big_endian
)
7371 offset_expr
.X_add_number
-= off
;
7373 offset_expr
.X_add_number
+= off
;
7374 macro_build (&offset_expr
, s2
, "t,o(b)", tempreg
, BFD_RELOC_LO16
, breg
);
7376 /* If necessary, move the result in tempreg the final destination. */
7377 if (treg
== tempreg
)
7379 /* Protect second load's delay slot. */
7381 move_register (treg
, tempreg
);
7395 load_address (AT
, &offset_expr
, &used_at
);
7397 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, AT
, breg
);
7398 if (! target_big_endian
)
7399 expr1
.X_add_number
= off
;
7401 expr1
.X_add_number
= 0;
7402 macro_build (&expr1
, s
, "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
7403 if (! target_big_endian
)
7404 expr1
.X_add_number
= 0;
7406 expr1
.X_add_number
= off
;
7407 macro_build (&expr1
, s2
, "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
7413 load_address (AT
, &offset_expr
, &used_at
);
7415 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, AT
, breg
);
7416 if (target_big_endian
)
7417 expr1
.X_add_number
= 0;
7418 macro_build (&expr1
, mask
== M_ULH_A
? "lb" : "lbu", "t,o(b)",
7419 treg
, BFD_RELOC_LO16
, AT
);
7420 if (target_big_endian
)
7421 expr1
.X_add_number
= 1;
7423 expr1
.X_add_number
= 0;
7424 macro_build (&expr1
, "lbu", "t,o(b)", AT
, BFD_RELOC_LO16
, AT
);
7425 macro_build (NULL
, "sll", "d,w,<", treg
, treg
, 8);
7426 macro_build (NULL
, "or", "d,v,t", treg
, treg
, AT
);
7430 if (offset_expr
.X_add_number
>= 0x7fff)
7431 as_bad (_("operand overflow"));
7432 if (target_big_endian
)
7433 ++offset_expr
.X_add_number
;
7434 macro_build (&offset_expr
, "sb", "t,o(b)", treg
, BFD_RELOC_LO16
, breg
);
7435 macro_build (NULL
, "srl", "d,w,<", AT
, treg
, 8);
7436 if (target_big_endian
)
7437 --offset_expr
.X_add_number
;
7439 ++offset_expr
.X_add_number
;
7440 macro_build (&offset_expr
, "sb", "t,o(b)", AT
, BFD_RELOC_LO16
, breg
);
7453 if (offset_expr
.X_add_number
>= 0x8000 - off
)
7454 as_bad (_("operand overflow"));
7455 if (! target_big_endian
)
7456 offset_expr
.X_add_number
+= off
;
7457 macro_build (&offset_expr
, s
, "t,o(b)", treg
, BFD_RELOC_LO16
, breg
);
7458 if (! target_big_endian
)
7459 offset_expr
.X_add_number
-= off
;
7461 offset_expr
.X_add_number
+= off
;
7462 macro_build (&offset_expr
, s2
, "t,o(b)", treg
, BFD_RELOC_LO16
, breg
);
7476 load_address (AT
, &offset_expr
, &used_at
);
7478 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, AT
, breg
);
7479 if (! target_big_endian
)
7480 expr1
.X_add_number
= off
;
7482 expr1
.X_add_number
= 0;
7483 macro_build (&expr1
, s
, "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
7484 if (! target_big_endian
)
7485 expr1
.X_add_number
= 0;
7487 expr1
.X_add_number
= off
;
7488 macro_build (&expr1
, s2
, "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
7493 load_address (AT
, &offset_expr
, &used_at
);
7495 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, AT
, breg
);
7496 if (! target_big_endian
)
7497 expr1
.X_add_number
= 0;
7498 macro_build (&expr1
, "sb", "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
7499 macro_build (NULL
, "srl", "d,w,<", treg
, treg
, 8);
7500 if (! target_big_endian
)
7501 expr1
.X_add_number
= 1;
7503 expr1
.X_add_number
= 0;
7504 macro_build (&expr1
, "sb", "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
7505 if (! target_big_endian
)
7506 expr1
.X_add_number
= 0;
7508 expr1
.X_add_number
= 1;
7509 macro_build (&expr1
, "lbu", "t,o(b)", AT
, BFD_RELOC_LO16
, AT
);
7510 macro_build (NULL
, "sll", "d,w,<", treg
, treg
, 8);
7511 macro_build (NULL
, "or", "d,v,t", treg
, treg
, AT
);
7515 /* FIXME: Check if this is one of the itbl macros, since they
7516 are added dynamically. */
7517 as_bad (_("Macro %s not implemented yet"), ip
->insn_mo
->name
);
7521 as_warn (_("Macro used $at after \".set noat\""));
7524 /* Implement macros in mips16 mode. */
7527 mips16_macro (struct mips_cl_insn
*ip
)
7530 int xreg
, yreg
, zreg
, tmp
;
7533 const char *s
, *s2
, *s3
;
7535 mask
= ip
->insn_mo
->mask
;
7537 xreg
= (ip
->insn_opcode
>> MIPS16OP_SH_RX
) & MIPS16OP_MASK_RX
;
7538 yreg
= (ip
->insn_opcode
>> MIPS16OP_SH_RY
) & MIPS16OP_MASK_RY
;
7539 zreg
= (ip
->insn_opcode
>> MIPS16OP_SH_RZ
) & MIPS16OP_MASK_RZ
;
7541 expr1
.X_op
= O_constant
;
7542 expr1
.X_op_symbol
= NULL
;
7543 expr1
.X_add_symbol
= NULL
;
7544 expr1
.X_add_number
= 1;
7563 mips_emit_delays (TRUE
);
7564 ++mips_opts
.noreorder
;
7565 mips_any_noreorder
= 1;
7566 macro_build (NULL
, dbl
? "ddiv" : "div", "0,x,y", xreg
, yreg
);
7567 expr1
.X_add_number
= 2;
7568 macro_build (&expr1
, "bnez", "x,p", yreg
);
7569 macro_build (NULL
, "break", "6", 7);
7571 /* FIXME: The normal code checks for of -1 / -0x80000000 here,
7572 since that causes an overflow. We should do that as well,
7573 but I don't see how to do the comparisons without a temporary
7575 --mips_opts
.noreorder
;
7576 macro_build (NULL
, s
, "x", zreg
);
7595 mips_emit_delays (TRUE
);
7596 ++mips_opts
.noreorder
;
7597 mips_any_noreorder
= 1;
7598 macro_build (NULL
, s
, "0,x,y", xreg
, yreg
);
7599 expr1
.X_add_number
= 2;
7600 macro_build (&expr1
, "bnez", "x,p", yreg
);
7601 macro_build (NULL
, "break", "6", 7);
7602 --mips_opts
.noreorder
;
7603 macro_build (NULL
, s2
, "x", zreg
);
7609 macro_build (NULL
, dbl
? "dmultu" : "multu", "x,y", xreg
, yreg
);
7610 macro_build (NULL
, "mflo", "x", zreg
);
7618 if (imm_expr
.X_op
!= O_constant
)
7619 as_bad (_("Unsupported large constant"));
7620 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
7621 macro_build (&imm_expr
, dbl
? "daddiu" : "addiu", "y,x,4", yreg
, xreg
);
7625 if (imm_expr
.X_op
!= O_constant
)
7626 as_bad (_("Unsupported large constant"));
7627 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
7628 macro_build (&imm_expr
, "addiu", "x,k", xreg
);
7632 if (imm_expr
.X_op
!= O_constant
)
7633 as_bad (_("Unsupported large constant"));
7634 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
7635 macro_build (&imm_expr
, "daddiu", "y,j", yreg
);
7657 goto do_reverse_branch
;
7661 goto do_reverse_branch
;
7673 goto do_reverse_branch
;
7684 macro_build (NULL
, s
, "x,y", xreg
, yreg
);
7685 macro_build (&offset_expr
, s2
, "p");
7712 goto do_addone_branch_i
;
7717 goto do_addone_branch_i
;
7732 goto do_addone_branch_i
;
7739 if (imm_expr
.X_op
!= O_constant
)
7740 as_bad (_("Unsupported large constant"));
7741 ++imm_expr
.X_add_number
;
7744 macro_build (&imm_expr
, s
, s3
, xreg
);
7745 macro_build (&offset_expr
, s2
, "p");
7749 expr1
.X_add_number
= 0;
7750 macro_build (&expr1
, "slti", "x,8", yreg
);
7752 move_register (xreg
, yreg
);
7753 expr1
.X_add_number
= 2;
7754 macro_build (&expr1
, "bteqz", "p");
7755 macro_build (NULL
, "neg", "x,w", xreg
, xreg
);
7759 /* For consistency checking, verify that all bits are specified either
7760 by the match/mask part of the instruction definition, or by the
7763 validate_mips_insn (const struct mips_opcode
*opc
)
7765 const char *p
= opc
->args
;
7767 unsigned long used_bits
= opc
->mask
;
7769 if ((used_bits
& opc
->match
) != opc
->match
)
7771 as_bad (_("internal: bad mips opcode (mask error): %s %s"),
7772 opc
->name
, opc
->args
);
7775 #define USE_BITS(mask,shift) (used_bits |= ((mask) << (shift)))
7785 case 'A': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
7786 case 'B': USE_BITS (OP_MASK_INSMSB
, OP_SH_INSMSB
); break;
7787 case 'C': USE_BITS (OP_MASK_EXTMSBD
, OP_SH_EXTMSBD
); break;
7788 case 'D': USE_BITS (OP_MASK_RD
, OP_SH_RD
);
7789 USE_BITS (OP_MASK_SEL
, OP_SH_SEL
); break;
7790 case 'E': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
7791 case 'F': USE_BITS (OP_MASK_INSMSB
, OP_SH_INSMSB
); break;
7792 case 'G': USE_BITS (OP_MASK_EXTMSBD
, OP_SH_EXTMSBD
); break;
7793 case 'H': USE_BITS (OP_MASK_EXTMSBD
, OP_SH_EXTMSBD
); break;
7796 as_bad (_("internal: bad mips opcode (unknown extension operand type `+%c'): %s %s"),
7797 c
, opc
->name
, opc
->args
);
7801 case '<': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
7802 case '>': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
7804 case 'B': USE_BITS (OP_MASK_CODE20
, OP_SH_CODE20
); break;
7805 case 'C': USE_BITS (OP_MASK_COPZ
, OP_SH_COPZ
); break;
7806 case 'D': USE_BITS (OP_MASK_FD
, OP_SH_FD
); break;
7807 case 'E': USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
7809 case 'G': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
7810 case 'H': USE_BITS (OP_MASK_SEL
, OP_SH_SEL
); break;
7812 case 'J': USE_BITS (OP_MASK_CODE19
, OP_SH_CODE19
); break;
7813 case 'K': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
7815 case 'M': USE_BITS (OP_MASK_CCC
, OP_SH_CCC
); break;
7816 case 'N': USE_BITS (OP_MASK_BCC
, OP_SH_BCC
); break;
7817 case 'O': USE_BITS (OP_MASK_ALN
, OP_SH_ALN
); break;
7818 case 'Q': USE_BITS (OP_MASK_VSEL
, OP_SH_VSEL
);
7819 USE_BITS (OP_MASK_FT
, OP_SH_FT
); break;
7820 case 'R': USE_BITS (OP_MASK_FR
, OP_SH_FR
); break;
7821 case 'S': USE_BITS (OP_MASK_FS
, OP_SH_FS
); break;
7822 case 'T': USE_BITS (OP_MASK_FT
, OP_SH_FT
); break;
7823 case 'V': USE_BITS (OP_MASK_FS
, OP_SH_FS
); break;
7824 case 'W': USE_BITS (OP_MASK_FT
, OP_SH_FT
); break;
7825 case 'X': USE_BITS (OP_MASK_FD
, OP_SH_FD
); break;
7826 case 'Y': USE_BITS (OP_MASK_FS
, OP_SH_FS
); break;
7827 case 'Z': USE_BITS (OP_MASK_FT
, OP_SH_FT
); break;
7828 case 'a': USE_BITS (OP_MASK_TARGET
, OP_SH_TARGET
); break;
7829 case 'b': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
7830 case 'c': USE_BITS (OP_MASK_CODE
, OP_SH_CODE
); break;
7831 case 'd': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
7833 case 'h': USE_BITS (OP_MASK_PREFX
, OP_SH_PREFX
); break;
7834 case 'i': USE_BITS (OP_MASK_IMMEDIATE
, OP_SH_IMMEDIATE
); break;
7835 case 'j': USE_BITS (OP_MASK_DELTA
, OP_SH_DELTA
); break;
7836 case 'k': USE_BITS (OP_MASK_CACHE
, OP_SH_CACHE
); break;
7838 case 'o': USE_BITS (OP_MASK_DELTA
, OP_SH_DELTA
); break;
7839 case 'p': USE_BITS (OP_MASK_DELTA
, OP_SH_DELTA
); break;
7840 case 'q': USE_BITS (OP_MASK_CODE2
, OP_SH_CODE2
); break;
7841 case 'r': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
7842 case 's': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
7843 case 't': USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
7844 case 'u': USE_BITS (OP_MASK_IMMEDIATE
, OP_SH_IMMEDIATE
); break;
7845 case 'v': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
7846 case 'w': USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
7849 case 'P': USE_BITS (OP_MASK_PERFREG
, OP_SH_PERFREG
); break;
7850 case 'U': USE_BITS (OP_MASK_RD
, OP_SH_RD
);
7851 USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
7852 case 'e': USE_BITS (OP_MASK_VECBYTE
, OP_SH_VECBYTE
); break;
7853 case '%': USE_BITS (OP_MASK_VECALIGN
, OP_SH_VECALIGN
); break;
7857 as_bad (_("internal: bad mips opcode (unknown operand type `%c'): %s %s"),
7858 c
, opc
->name
, opc
->args
);
7862 if (used_bits
!= 0xffffffff)
7864 as_bad (_("internal: bad mips opcode (bits 0x%lx undefined): %s %s"),
7865 ~used_bits
& 0xffffffff, opc
->name
, opc
->args
);
7871 /* This routine assembles an instruction into its binary format. As a
7872 side effect, it sets one of the global variables imm_reloc or
7873 offset_reloc to the type of relocation to do if one of the operands
7874 is an address expression. */
7877 mips_ip (char *str
, struct mips_cl_insn
*ip
)
7882 struct mips_opcode
*insn
;
7885 unsigned int lastregno
= 0;
7886 unsigned int lastpos
= 0;
7887 unsigned int limlo
, limhi
;
7893 /* If the instruction contains a '.', we first try to match an instruction
7894 including the '.'. Then we try again without the '.'. */
7896 for (s
= str
; *s
!= '\0' && !ISSPACE (*s
); ++s
)
7899 /* If we stopped on whitespace, then replace the whitespace with null for
7900 the call to hash_find. Save the character we replaced just in case we
7901 have to re-parse the instruction. */
7908 insn
= (struct mips_opcode
*) hash_find (op_hash
, str
);
7910 /* If we didn't find the instruction in the opcode table, try again, but
7911 this time with just the instruction up to, but not including the
7915 /* Restore the character we overwrite above (if any). */
7919 /* Scan up to the first '.' or whitespace. */
7921 *s
!= '\0' && *s
!= '.' && !ISSPACE (*s
);
7925 /* If we did not find a '.', then we can quit now. */
7928 insn_error
= "unrecognized opcode";
7932 /* Lookup the instruction in the hash table. */
7934 if ((insn
= (struct mips_opcode
*) hash_find (op_hash
, str
)) == NULL
)
7936 insn_error
= "unrecognized opcode";
7946 assert (strcmp (insn
->name
, str
) == 0);
7948 if (OPCODE_IS_MEMBER (insn
,
7950 | (file_ase_mips16
? INSN_MIPS16
: 0)
7951 | (mips_opts
.ase_mdmx
? INSN_MDMX
: 0)
7952 | (mips_opts
.ase_mips3d
? INSN_MIPS3D
: 0)),
7958 if (insn
->pinfo
!= INSN_MACRO
)
7960 if (mips_opts
.arch
== CPU_R4650
&& (insn
->pinfo
& FP_D
) != 0)
7966 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
]
7967 && strcmp (insn
->name
, insn
[1].name
) == 0)
7976 static char buf
[100];
7978 _("opcode not supported on this processor: %s (%s)"),
7979 mips_cpu_info_from_arch (mips_opts
.arch
)->name
,
7980 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
7990 ip
->insn_opcode
= insn
->match
;
7992 for (args
= insn
->args
;; ++args
)
7996 s
+= strspn (s
, " \t");
8000 case '\0': /* end of args */
8013 ip
->insn_opcode
|= lastregno
<< OP_SH_RS
;
8017 ip
->insn_opcode
|= lastregno
<< OP_SH_RT
;
8021 ip
->insn_opcode
|= lastregno
<< OP_SH_FT
;
8025 ip
->insn_opcode
|= lastregno
<< OP_SH_FS
;
8031 /* Handle optional base register.
8032 Either the base register is omitted or
8033 we must have a left paren. */
8034 /* This is dependent on the next operand specifier
8035 is a base register specification. */
8036 assert (args
[1] == 'b' || args
[1] == '5'
8037 || args
[1] == '-' || args
[1] == '4');
8041 case ')': /* these must match exactly */
8048 case '+': /* Opcode extension character. */
8051 case 'A': /* ins/ext position, becomes LSB. */
8060 my_getExpression (&imm_expr
, s
);
8061 check_absolute_expr (ip
, &imm_expr
);
8062 if ((unsigned long) imm_expr
.X_add_number
< limlo
8063 || (unsigned long) imm_expr
.X_add_number
> limhi
)
8065 as_bad (_("Improper position (%lu)"),
8066 (unsigned long) imm_expr
.X_add_number
);
8067 imm_expr
.X_add_number
= limlo
;
8069 lastpos
= imm_expr
.X_add_number
;
8070 ip
->insn_opcode
|= (imm_expr
.X_add_number
8071 & OP_MASK_SHAMT
) << OP_SH_SHAMT
;
8072 imm_expr
.X_op
= O_absent
;
8076 case 'B': /* ins size, becomes MSB. */
8085 my_getExpression (&imm_expr
, s
);
8086 check_absolute_expr (ip
, &imm_expr
);
8087 /* Check for negative input so that small negative numbers
8088 will not succeed incorrectly. The checks against
8089 (pos+size) transitively check "size" itself,
8090 assuming that "pos" is reasonable. */
8091 if ((long) imm_expr
.X_add_number
< 0
8092 || ((unsigned long) imm_expr
.X_add_number
8094 || ((unsigned long) imm_expr
.X_add_number
8097 as_bad (_("Improper insert size (%lu, position %lu)"),
8098 (unsigned long) imm_expr
.X_add_number
,
8099 (unsigned long) lastpos
);
8100 imm_expr
.X_add_number
= limlo
- lastpos
;
8102 ip
->insn_opcode
|= ((lastpos
+ imm_expr
.X_add_number
- 1)
8103 & OP_MASK_INSMSB
) << OP_SH_INSMSB
;
8104 imm_expr
.X_op
= O_absent
;
8108 case 'C': /* ext size, becomes MSBD. */
8121 my_getExpression (&imm_expr
, s
);
8122 check_absolute_expr (ip
, &imm_expr
);
8123 /* Check for negative input so that small negative numbers
8124 will not succeed incorrectly. The checks against
8125 (pos+size) transitively check "size" itself,
8126 assuming that "pos" is reasonable. */
8127 if ((long) imm_expr
.X_add_number
< 0
8128 || ((unsigned long) imm_expr
.X_add_number
8130 || ((unsigned long) imm_expr
.X_add_number
8133 as_bad (_("Improper extract size (%lu, position %lu)"),
8134 (unsigned long) imm_expr
.X_add_number
,
8135 (unsigned long) lastpos
);
8136 imm_expr
.X_add_number
= limlo
- lastpos
;
8138 ip
->insn_opcode
|= ((imm_expr
.X_add_number
- 1)
8139 & OP_MASK_EXTMSBD
) << OP_SH_EXTMSBD
;
8140 imm_expr
.X_op
= O_absent
;
8145 /* +D is for disassembly only; never match. */
8149 /* "+I" is like "I", except that imm2_expr is used. */
8150 my_getExpression (&imm2_expr
, s
);
8151 if (imm2_expr
.X_op
!= O_big
8152 && imm2_expr
.X_op
!= O_constant
)
8153 insn_error
= _("absolute expression required");
8154 normalize_constant_expr (&imm2_expr
);
8159 as_bad (_("internal: bad mips opcode (unknown extension operand type `+%c'): %s %s"),
8160 *args
, insn
->name
, insn
->args
);
8161 /* Further processing is fruitless. */
8166 case '<': /* must be at least one digit */
8168 * According to the manual, if the shift amount is greater
8169 * than 31 or less than 0, then the shift amount should be
8170 * mod 32. In reality the mips assembler issues an error.
8171 * We issue a warning and mask out all but the low 5 bits.
8173 my_getExpression (&imm_expr
, s
);
8174 check_absolute_expr (ip
, &imm_expr
);
8175 if ((unsigned long) imm_expr
.X_add_number
> 31)
8177 as_warn (_("Improper shift amount (%lu)"),
8178 (unsigned long) imm_expr
.X_add_number
);
8179 imm_expr
.X_add_number
&= OP_MASK_SHAMT
;
8181 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_SHAMT
;
8182 imm_expr
.X_op
= O_absent
;
8186 case '>': /* shift amount minus 32 */
8187 my_getExpression (&imm_expr
, s
);
8188 check_absolute_expr (ip
, &imm_expr
);
8189 if ((unsigned long) imm_expr
.X_add_number
< 32
8190 || (unsigned long) imm_expr
.X_add_number
> 63)
8192 ip
->insn_opcode
|= (imm_expr
.X_add_number
- 32) << OP_SH_SHAMT
;
8193 imm_expr
.X_op
= O_absent
;
8197 case 'k': /* cache code */
8198 case 'h': /* prefx code */
8199 my_getExpression (&imm_expr
, s
);
8200 check_absolute_expr (ip
, &imm_expr
);
8201 if ((unsigned long) imm_expr
.X_add_number
> 31)
8203 as_warn (_("Invalid value for `%s' (%lu)"),
8205 (unsigned long) imm_expr
.X_add_number
);
8206 imm_expr
.X_add_number
&= 0x1f;
8209 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_CACHE
;
8211 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_PREFX
;
8212 imm_expr
.X_op
= O_absent
;
8216 case 'c': /* break code */
8217 my_getExpression (&imm_expr
, s
);
8218 check_absolute_expr (ip
, &imm_expr
);
8219 if ((unsigned long) imm_expr
.X_add_number
> 1023)
8221 as_warn (_("Illegal break code (%lu)"),
8222 (unsigned long) imm_expr
.X_add_number
);
8223 imm_expr
.X_add_number
&= OP_MASK_CODE
;
8225 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_CODE
;
8226 imm_expr
.X_op
= O_absent
;
8230 case 'q': /* lower break code */
8231 my_getExpression (&imm_expr
, s
);
8232 check_absolute_expr (ip
, &imm_expr
);
8233 if ((unsigned long) imm_expr
.X_add_number
> 1023)
8235 as_warn (_("Illegal lower break code (%lu)"),
8236 (unsigned long) imm_expr
.X_add_number
);
8237 imm_expr
.X_add_number
&= OP_MASK_CODE2
;
8239 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_CODE2
;
8240 imm_expr
.X_op
= O_absent
;
8244 case 'B': /* 20-bit syscall/break code. */
8245 my_getExpression (&imm_expr
, s
);
8246 check_absolute_expr (ip
, &imm_expr
);
8247 if ((unsigned long) imm_expr
.X_add_number
> OP_MASK_CODE20
)
8248 as_warn (_("Illegal 20-bit code (%lu)"),
8249 (unsigned long) imm_expr
.X_add_number
);
8250 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_CODE20
;
8251 imm_expr
.X_op
= O_absent
;
8255 case 'C': /* Coprocessor code */
8256 my_getExpression (&imm_expr
, s
);
8257 check_absolute_expr (ip
, &imm_expr
);
8258 if ((unsigned long) imm_expr
.X_add_number
>= (1 << 25))
8260 as_warn (_("Coproccesor code > 25 bits (%lu)"),
8261 (unsigned long) imm_expr
.X_add_number
);
8262 imm_expr
.X_add_number
&= ((1 << 25) - 1);
8264 ip
->insn_opcode
|= imm_expr
.X_add_number
;
8265 imm_expr
.X_op
= O_absent
;
8269 case 'J': /* 19-bit wait code. */
8270 my_getExpression (&imm_expr
, s
);
8271 check_absolute_expr (ip
, &imm_expr
);
8272 if ((unsigned long) imm_expr
.X_add_number
> OP_MASK_CODE19
)
8273 as_warn (_("Illegal 19-bit code (%lu)"),
8274 (unsigned long) imm_expr
.X_add_number
);
8275 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_CODE19
;
8276 imm_expr
.X_op
= O_absent
;
8280 case 'P': /* Performance register */
8281 my_getExpression (&imm_expr
, s
);
8282 check_absolute_expr (ip
, &imm_expr
);
8283 if (imm_expr
.X_add_number
!= 0 && imm_expr
.X_add_number
!= 1)
8285 as_warn (_("Invalid performance register (%lu)"),
8286 (unsigned long) imm_expr
.X_add_number
);
8287 imm_expr
.X_add_number
&= OP_MASK_PERFREG
;
8289 ip
->insn_opcode
|= (imm_expr
.X_add_number
<< OP_SH_PERFREG
);
8290 imm_expr
.X_op
= O_absent
;
8294 case 'b': /* base register */
8295 case 'd': /* destination register */
8296 case 's': /* source register */
8297 case 't': /* target register */
8298 case 'r': /* both target and source */
8299 case 'v': /* both dest and source */
8300 case 'w': /* both dest and target */
8301 case 'E': /* coprocessor target register */
8302 case 'G': /* coprocessor destination register */
8303 case 'K': /* 'rdhwr' destination register */
8304 case 'x': /* ignore register name */
8305 case 'z': /* must be zero register */
8306 case 'U': /* destination register (clo/clz). */
8321 while (ISDIGIT (*s
));
8323 as_bad (_("Invalid register number (%d)"), regno
);
8325 else if (*args
== 'E' || *args
== 'G' || *args
== 'K')
8329 if (s
[1] == 'r' && s
[2] == 'a')
8334 else if (s
[1] == 'f' && s
[2] == 'p')
8339 else if (s
[1] == 's' && s
[2] == 'p')
8344 else if (s
[1] == 'g' && s
[2] == 'p')
8349 else if (s
[1] == 'a' && s
[2] == 't')
8354 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '0')
8359 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '1')
8364 else if (s
[1] == 'z' && s
[2] == 'e' && s
[3] == 'r' && s
[4] == 'o')
8369 else if (itbl_have_entries
)
8374 p
= s
+ 1; /* advance past '$' */
8375 n
= itbl_get_field (&p
); /* n is name */
8377 /* See if this is a register defined in an
8379 if (itbl_get_reg_val (n
, &r
))
8381 /* Get_field advances to the start of
8382 the next field, so we need to back
8383 rack to the end of the last field. */
8387 s
= strchr (s
, '\0');
8401 as_warn (_("Used $at without \".set noat\""));
8407 if (c
== 'r' || c
== 'v' || c
== 'w')
8414 /* 'z' only matches $0. */
8415 if (c
== 'z' && regno
!= 0)
8418 /* Now that we have assembled one operand, we use the args string
8419 * to figure out where it goes in the instruction. */
8426 ip
->insn_opcode
|= regno
<< OP_SH_RS
;
8431 ip
->insn_opcode
|= regno
<< OP_SH_RD
;
8434 ip
->insn_opcode
|= regno
<< OP_SH_RD
;
8435 ip
->insn_opcode
|= regno
<< OP_SH_RT
;
8440 ip
->insn_opcode
|= regno
<< OP_SH_RT
;
8443 /* This case exists because on the r3000 trunc
8444 expands into a macro which requires a gp
8445 register. On the r6000 or r4000 it is
8446 assembled into a single instruction which
8447 ignores the register. Thus the insn version
8448 is MIPS_ISA2 and uses 'x', and the macro
8449 version is MIPS_ISA1 and uses 't'. */
8452 /* This case is for the div instruction, which
8453 acts differently if the destination argument
8454 is $0. This only matches $0, and is checked
8455 outside the switch. */
8458 /* Itbl operand; not yet implemented. FIXME ?? */
8460 /* What about all other operands like 'i', which
8461 can be specified in the opcode table? */
8471 ip
->insn_opcode
|= lastregno
<< OP_SH_RS
;
8474 ip
->insn_opcode
|= lastregno
<< OP_SH_RT
;
8479 case 'O': /* MDMX alignment immediate constant. */
8480 my_getExpression (&imm_expr
, s
);
8481 check_absolute_expr (ip
, &imm_expr
);
8482 if ((unsigned long) imm_expr
.X_add_number
> OP_MASK_ALN
)
8484 as_warn ("Improper align amount (%ld), using low bits",
8485 (long) imm_expr
.X_add_number
);
8486 imm_expr
.X_add_number
&= OP_MASK_ALN
;
8488 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_ALN
;
8489 imm_expr
.X_op
= O_absent
;
8493 case 'Q': /* MDMX vector, element sel, or const. */
8496 /* MDMX Immediate. */
8497 my_getExpression (&imm_expr
, s
);
8498 check_absolute_expr (ip
, &imm_expr
);
8499 if ((unsigned long) imm_expr
.X_add_number
> OP_MASK_FT
)
8501 as_warn (_("Invalid MDMX Immediate (%ld)"),
8502 (long) imm_expr
.X_add_number
);
8503 imm_expr
.X_add_number
&= OP_MASK_FT
;
8505 imm_expr
.X_add_number
&= OP_MASK_FT
;
8506 if (ip
->insn_opcode
& (OP_MASK_VSEL
<< OP_SH_VSEL
))
8507 ip
->insn_opcode
|= MDMX_FMTSEL_IMM_QH
<< OP_SH_VSEL
;
8509 ip
->insn_opcode
|= MDMX_FMTSEL_IMM_OB
<< OP_SH_VSEL
;
8510 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_FT
;
8511 imm_expr
.X_op
= O_absent
;
8515 /* Not MDMX Immediate. Fall through. */
8516 case 'X': /* MDMX destination register. */
8517 case 'Y': /* MDMX source register. */
8518 case 'Z': /* MDMX target register. */
8520 case 'D': /* floating point destination register */
8521 case 'S': /* floating point source register */
8522 case 'T': /* floating point target register */
8523 case 'R': /* floating point source register */
8527 /* Accept $fN for FP and MDMX register numbers, and in
8528 addition accept $vN for MDMX register numbers. */
8529 if ((s
[0] == '$' && s
[1] == 'f' && ISDIGIT (s
[2]))
8530 || (is_mdmx
!= 0 && s
[0] == '$' && s
[1] == 'v'
8541 while (ISDIGIT (*s
));
8544 as_bad (_("Invalid float register number (%d)"), regno
);
8546 if ((regno
& 1) != 0
8548 && ! (strcmp (str
, "mtc1") == 0
8549 || strcmp (str
, "mfc1") == 0
8550 || strcmp (str
, "lwc1") == 0
8551 || strcmp (str
, "swc1") == 0
8552 || strcmp (str
, "l.s") == 0
8553 || strcmp (str
, "s.s") == 0))
8554 as_warn (_("Float register should be even, was %d"),
8562 if (c
== 'V' || c
== 'W')
8573 ip
->insn_opcode
|= regno
<< OP_SH_FD
;
8578 ip
->insn_opcode
|= regno
<< OP_SH_FS
;
8581 /* This is like 'Z', but also needs to fix the MDMX
8582 vector/scalar select bits. Note that the
8583 scalar immediate case is handled above. */
8586 int is_qh
= (ip
->insn_opcode
& (1 << OP_SH_VSEL
));
8587 int max_el
= (is_qh
? 3 : 7);
8589 my_getExpression(&imm_expr
, s
);
8590 check_absolute_expr (ip
, &imm_expr
);
8592 if (imm_expr
.X_add_number
> max_el
)
8593 as_bad(_("Bad element selector %ld"),
8594 (long) imm_expr
.X_add_number
);
8595 imm_expr
.X_add_number
&= max_el
;
8596 ip
->insn_opcode
|= (imm_expr
.X_add_number
8600 as_warn(_("Expecting ']' found '%s'"), s
);
8606 if (ip
->insn_opcode
& (OP_MASK_VSEL
<< OP_SH_VSEL
))
8607 ip
->insn_opcode
|= (MDMX_FMTSEL_VEC_QH
8610 ip
->insn_opcode
|= (MDMX_FMTSEL_VEC_OB
<<
8617 ip
->insn_opcode
|= regno
<< OP_SH_FT
;
8620 ip
->insn_opcode
|= regno
<< OP_SH_FR
;
8630 ip
->insn_opcode
|= lastregno
<< OP_SH_FS
;
8633 ip
->insn_opcode
|= lastregno
<< OP_SH_FT
;
8639 my_getExpression (&imm_expr
, s
);
8640 if (imm_expr
.X_op
!= O_big
8641 && imm_expr
.X_op
!= O_constant
)
8642 insn_error
= _("absolute expression required");
8643 normalize_constant_expr (&imm_expr
);
8648 my_getExpression (&offset_expr
, s
);
8649 *imm_reloc
= BFD_RELOC_32
;
8662 unsigned char temp
[8];
8664 unsigned int length
;
8669 /* These only appear as the last operand in an
8670 instruction, and every instruction that accepts
8671 them in any variant accepts them in all variants.
8672 This means we don't have to worry about backing out
8673 any changes if the instruction does not match.
8675 The difference between them is the size of the
8676 floating point constant and where it goes. For 'F'
8677 and 'L' the constant is 64 bits; for 'f' and 'l' it
8678 is 32 bits. Where the constant is placed is based
8679 on how the MIPS assembler does things:
8682 f -- immediate value
8685 The .lit4 and .lit8 sections are only used if
8686 permitted by the -G argument.
8688 The code below needs to know whether the target register
8689 is 32 or 64 bits wide. It relies on the fact 'f' and
8690 'F' are used with GPR-based instructions and 'l' and
8691 'L' are used with FPR-based instructions. */
8693 f64
= *args
== 'F' || *args
== 'L';
8694 using_gprs
= *args
== 'F' || *args
== 'f';
8696 save_in
= input_line_pointer
;
8697 input_line_pointer
= s
;
8698 err
= md_atof (f64
? 'd' : 'f', (char *) temp
, &len
);
8700 s
= input_line_pointer
;
8701 input_line_pointer
= save_in
;
8702 if (err
!= NULL
&& *err
!= '\0')
8704 as_bad (_("Bad floating point constant: %s"), err
);
8705 memset (temp
, '\0', sizeof temp
);
8706 length
= f64
? 8 : 4;
8709 assert (length
== (unsigned) (f64
? 8 : 4));
8713 && (g_switch_value
< 4
8714 || (temp
[0] == 0 && temp
[1] == 0)
8715 || (temp
[2] == 0 && temp
[3] == 0))))
8717 imm_expr
.X_op
= O_constant
;
8718 if (! target_big_endian
)
8719 imm_expr
.X_add_number
= bfd_getl32 (temp
);
8721 imm_expr
.X_add_number
= bfd_getb32 (temp
);
8724 && ! mips_disable_float_construction
8725 /* Constants can only be constructed in GPRs and
8726 copied to FPRs if the GPRs are at least as wide
8727 as the FPRs. Force the constant into memory if
8728 we are using 64-bit FPRs but the GPRs are only
8731 || ! (HAVE_64BIT_FPRS
&& HAVE_32BIT_GPRS
))
8732 && ((temp
[0] == 0 && temp
[1] == 0)
8733 || (temp
[2] == 0 && temp
[3] == 0))
8734 && ((temp
[4] == 0 && temp
[5] == 0)
8735 || (temp
[6] == 0 && temp
[7] == 0)))
8737 /* The value is simple enough to load with a couple of
8738 instructions. If using 32-bit registers, set
8739 imm_expr to the high order 32 bits and offset_expr to
8740 the low order 32 bits. Otherwise, set imm_expr to
8741 the entire 64 bit constant. */
8742 if (using_gprs
? HAVE_32BIT_GPRS
: HAVE_32BIT_FPRS
)
8744 imm_expr
.X_op
= O_constant
;
8745 offset_expr
.X_op
= O_constant
;
8746 if (! target_big_endian
)
8748 imm_expr
.X_add_number
= bfd_getl32 (temp
+ 4);
8749 offset_expr
.X_add_number
= bfd_getl32 (temp
);
8753 imm_expr
.X_add_number
= bfd_getb32 (temp
);
8754 offset_expr
.X_add_number
= bfd_getb32 (temp
+ 4);
8756 if (offset_expr
.X_add_number
== 0)
8757 offset_expr
.X_op
= O_absent
;
8759 else if (sizeof (imm_expr
.X_add_number
) > 4)
8761 imm_expr
.X_op
= O_constant
;
8762 if (! target_big_endian
)
8763 imm_expr
.X_add_number
= bfd_getl64 (temp
);
8765 imm_expr
.X_add_number
= bfd_getb64 (temp
);
8769 imm_expr
.X_op
= O_big
;
8770 imm_expr
.X_add_number
= 4;
8771 if (! target_big_endian
)
8773 generic_bignum
[0] = bfd_getl16 (temp
);
8774 generic_bignum
[1] = bfd_getl16 (temp
+ 2);
8775 generic_bignum
[2] = bfd_getl16 (temp
+ 4);
8776 generic_bignum
[3] = bfd_getl16 (temp
+ 6);
8780 generic_bignum
[0] = bfd_getb16 (temp
+ 6);
8781 generic_bignum
[1] = bfd_getb16 (temp
+ 4);
8782 generic_bignum
[2] = bfd_getb16 (temp
+ 2);
8783 generic_bignum
[3] = bfd_getb16 (temp
);
8789 const char *newname
;
8792 /* Switch to the right section. */
8794 subseg
= now_subseg
;
8797 default: /* unused default case avoids warnings. */
8799 newname
= RDATA_SECTION_NAME
;
8800 if (g_switch_value
>= 8)
8804 newname
= RDATA_SECTION_NAME
;
8807 assert (g_switch_value
>= 4);
8811 new_seg
= subseg_new (newname
, (subsegT
) 0);
8812 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
8813 bfd_set_section_flags (stdoutput
, new_seg
,
8818 frag_align (*args
== 'l' ? 2 : 3, 0, 0);
8819 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
8820 && strcmp (TARGET_OS
, "elf") != 0)
8821 record_alignment (new_seg
, 4);
8823 record_alignment (new_seg
, *args
== 'l' ? 2 : 3);
8825 as_bad (_("Can't use floating point insn in this section"));
8827 /* Set the argument to the current address in the
8829 offset_expr
.X_op
= O_symbol
;
8830 offset_expr
.X_add_symbol
=
8831 symbol_new ("L0\001", now_seg
,
8832 (valueT
) frag_now_fix (), frag_now
);
8833 offset_expr
.X_add_number
= 0;
8835 /* Put the floating point number into the section. */
8836 p
= frag_more ((int) length
);
8837 memcpy (p
, temp
, length
);
8839 /* Switch back to the original section. */
8840 subseg_set (seg
, subseg
);
8845 case 'i': /* 16 bit unsigned immediate */
8846 case 'j': /* 16 bit signed immediate */
8847 *imm_reloc
= BFD_RELOC_LO16
;
8848 if (my_getSmallExpression (&imm_expr
, imm_reloc
, s
) == 0)
8851 offsetT minval
, maxval
;
8853 more
= (insn
+ 1 < &mips_opcodes
[NUMOPCODES
]
8854 && strcmp (insn
->name
, insn
[1].name
) == 0);
8856 /* If the expression was written as an unsigned number,
8857 only treat it as signed if there are no more
8861 && sizeof (imm_expr
.X_add_number
) <= 4
8862 && imm_expr
.X_op
== O_constant
8863 && imm_expr
.X_add_number
< 0
8864 && imm_expr
.X_unsigned
8868 /* For compatibility with older assemblers, we accept
8869 0x8000-0xffff as signed 16-bit numbers when only
8870 signed numbers are allowed. */
8872 minval
= 0, maxval
= 0xffff;
8874 minval
= -0x8000, maxval
= 0x7fff;
8876 minval
= -0x8000, maxval
= 0xffff;
8878 if (imm_expr
.X_op
!= O_constant
8879 || imm_expr
.X_add_number
< minval
8880 || imm_expr
.X_add_number
> maxval
)
8884 if (imm_expr
.X_op
== O_constant
8885 || imm_expr
.X_op
== O_big
)
8886 as_bad (_("expression out of range"));
8892 case 'o': /* 16 bit offset */
8893 /* Check whether there is only a single bracketed expression
8894 left. If so, it must be the base register and the
8895 constant must be zero. */
8896 if (*s
== '(' && strchr (s
+ 1, '(') == 0)
8898 offset_expr
.X_op
= O_constant
;
8899 offset_expr
.X_add_number
= 0;
8903 /* If this value won't fit into a 16 bit offset, then go
8904 find a macro that will generate the 32 bit offset
8906 if (my_getSmallExpression (&offset_expr
, offset_reloc
, s
) == 0
8907 && (offset_expr
.X_op
!= O_constant
8908 || offset_expr
.X_add_number
>= 0x8000
8909 || offset_expr
.X_add_number
< -0x8000))
8915 case 'p': /* pc relative offset */
8916 *offset_reloc
= BFD_RELOC_16_PCREL_S2
;
8917 my_getExpression (&offset_expr
, s
);
8921 case 'u': /* upper 16 bits */
8922 if (my_getSmallExpression (&imm_expr
, imm_reloc
, s
) == 0
8923 && imm_expr
.X_op
== O_constant
8924 && (imm_expr
.X_add_number
< 0
8925 || imm_expr
.X_add_number
>= 0x10000))
8926 as_bad (_("lui expression not in range 0..65535"));
8930 case 'a': /* 26 bit address */
8931 my_getExpression (&offset_expr
, s
);
8933 *offset_reloc
= BFD_RELOC_MIPS_JMP
;
8936 case 'N': /* 3 bit branch condition code */
8937 case 'M': /* 3 bit compare condition code */
8938 if (strncmp (s
, "$fcc", 4) != 0)
8948 while (ISDIGIT (*s
));
8950 as_bad (_("Invalid condition code register $fcc%d"), regno
);
8951 if ((strcmp(str
+ strlen(str
) - 3, ".ps") == 0
8952 || strcmp(str
+ strlen(str
) - 5, "any2f") == 0
8953 || strcmp(str
+ strlen(str
) - 5, "any2t") == 0)
8954 && (regno
& 1) != 0)
8955 as_warn(_("Condition code register should be even for %s, was %d"),
8957 if ((strcmp(str
+ strlen(str
) - 5, "any4f") == 0
8958 || strcmp(str
+ strlen(str
) - 5, "any4t") == 0)
8959 && (regno
& 3) != 0)
8960 as_warn(_("Condition code register should be 0 or 4 for %s, was %d"),
8963 ip
->insn_opcode
|= regno
<< OP_SH_BCC
;
8965 ip
->insn_opcode
|= regno
<< OP_SH_CCC
;
8969 if (s
[0] == '0' && (s
[1] == 'x' || s
[1] == 'X'))
8980 while (ISDIGIT (*s
));
8983 c
= 8; /* Invalid sel value. */
8986 as_bad (_("invalid coprocessor sub-selection value (0-7)"));
8987 ip
->insn_opcode
|= c
;
8991 /* Must be at least one digit. */
8992 my_getExpression (&imm_expr
, s
);
8993 check_absolute_expr (ip
, &imm_expr
);
8995 if ((unsigned long) imm_expr
.X_add_number
8996 > (unsigned long) OP_MASK_VECBYTE
)
8998 as_bad (_("bad byte vector index (%ld)"),
8999 (long) imm_expr
.X_add_number
);
9000 imm_expr
.X_add_number
= 0;
9003 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_VECBYTE
;
9004 imm_expr
.X_op
= O_absent
;
9009 my_getExpression (&imm_expr
, s
);
9010 check_absolute_expr (ip
, &imm_expr
);
9012 if ((unsigned long) imm_expr
.X_add_number
9013 > (unsigned long) OP_MASK_VECALIGN
)
9015 as_bad (_("bad byte vector index (%ld)"),
9016 (long) imm_expr
.X_add_number
);
9017 imm_expr
.X_add_number
= 0;
9020 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_VECALIGN
;
9021 imm_expr
.X_op
= O_absent
;
9026 as_bad (_("bad char = '%c'\n"), *args
);
9031 /* Args don't match. */
9032 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
9033 !strcmp (insn
->name
, insn
[1].name
))
9037 insn_error
= _("illegal operands");
9042 insn_error
= _("illegal operands");
9047 /* This routine assembles an instruction into its binary format when
9048 assembling for the mips16. As a side effect, it sets one of the
9049 global variables imm_reloc or offset_reloc to the type of
9050 relocation to do if one of the operands is an address expression.
9051 It also sets mips16_small and mips16_ext if the user explicitly
9052 requested a small or extended instruction. */
9055 mips16_ip (char *str
, struct mips_cl_insn
*ip
)
9059 struct mips_opcode
*insn
;
9062 unsigned int lastregno
= 0;
9067 mips16_small
= FALSE
;
9070 for (s
= str
; ISLOWER (*s
); ++s
)
9082 if (s
[1] == 't' && s
[2] == ' ')
9085 mips16_small
= TRUE
;
9089 else if (s
[1] == 'e' && s
[2] == ' ')
9098 insn_error
= _("unknown opcode");
9102 if (mips_opts
.noautoextend
&& ! mips16_ext
)
9103 mips16_small
= TRUE
;
9105 if ((insn
= (struct mips_opcode
*) hash_find (mips16_op_hash
, str
)) == NULL
)
9107 insn_error
= _("unrecognized opcode");
9114 assert (strcmp (insn
->name
, str
) == 0);
9117 ip
->insn_opcode
= insn
->match
;
9118 ip
->use_extend
= FALSE
;
9119 imm_expr
.X_op
= O_absent
;
9120 imm_reloc
[0] = BFD_RELOC_UNUSED
;
9121 imm_reloc
[1] = BFD_RELOC_UNUSED
;
9122 imm_reloc
[2] = BFD_RELOC_UNUSED
;
9123 imm2_expr
.X_op
= O_absent
;
9124 offset_expr
.X_op
= O_absent
;
9125 offset_reloc
[0] = BFD_RELOC_UNUSED
;
9126 offset_reloc
[1] = BFD_RELOC_UNUSED
;
9127 offset_reloc
[2] = BFD_RELOC_UNUSED
;
9128 for (args
= insn
->args
; 1; ++args
)
9135 /* In this switch statement we call break if we did not find
9136 a match, continue if we did find a match, or return if we
9145 /* Stuff the immediate value in now, if we can. */
9146 if (imm_expr
.X_op
== O_constant
9147 && *imm_reloc
> BFD_RELOC_UNUSED
9148 && insn
->pinfo
!= INSN_MACRO
)
9150 mips16_immed (NULL
, 0, *imm_reloc
- BFD_RELOC_UNUSED
,
9151 imm_expr
.X_add_number
, TRUE
, mips16_small
,
9152 mips16_ext
, &ip
->insn_opcode
,
9153 &ip
->use_extend
, &ip
->extend
);
9154 imm_expr
.X_op
= O_absent
;
9155 *imm_reloc
= BFD_RELOC_UNUSED
;
9169 ip
->insn_opcode
|= lastregno
<< MIPS16OP_SH_RX
;
9172 ip
->insn_opcode
|= lastregno
<< MIPS16OP_SH_RY
;
9188 ip
->insn_opcode
|= lastregno
<< MIPS16OP_SH_RX
;
9190 ip
->insn_opcode
|= lastregno
<< MIPS16OP_SH_RY
;
9217 while (ISDIGIT (*s
));
9220 as_bad (_("invalid register number (%d)"), regno
);
9226 if (s
[1] == 'r' && s
[2] == 'a')
9231 else if (s
[1] == 'f' && s
[2] == 'p')
9236 else if (s
[1] == 's' && s
[2] == 'p')
9241 else if (s
[1] == 'g' && s
[2] == 'p')
9246 else if (s
[1] == 'a' && s
[2] == 't')
9251 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '0')
9256 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '1')
9261 else if (s
[1] == 'z' && s
[2] == 'e' && s
[3] == 'r' && s
[4] == 'o')
9274 if (c
== 'v' || c
== 'w')
9276 regno
= mips16_to_32_reg_map
[lastregno
];
9290 regno
= mips32_to_16_reg_map
[regno
];
9295 regno
= ILLEGAL_REG
;
9300 regno
= ILLEGAL_REG
;
9305 regno
= ILLEGAL_REG
;
9310 if (regno
== AT
&& ! mips_opts
.noat
)
9311 as_warn (_("used $at without \".set noat\""));
9318 if (regno
== ILLEGAL_REG
)
9325 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_RX
;
9329 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_RY
;
9332 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_RZ
;
9335 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_MOVE32Z
;
9341 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_REGR32
;
9344 regno
= ((regno
& 7) << 2) | ((regno
& 0x18) >> 3);
9345 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_REG32R
;
9355 if (strncmp (s
, "$pc", 3) == 0)
9379 && strncmp (s
+ 1, "gprel(", sizeof "gprel(" - 1) == 0)
9381 /* This is %gprel(SYMBOL). We need to read SYMBOL,
9382 and generate the appropriate reloc. If the text
9383 inside %gprel is not a symbol name with an
9384 optional offset, then we generate a normal reloc
9385 and will probably fail later. */
9386 my_getExpression (&imm_expr
, s
+ sizeof "%gprel" - 1);
9387 if (imm_expr
.X_op
== O_symbol
)
9390 *imm_reloc
= BFD_RELOC_MIPS16_GPREL
;
9392 ip
->use_extend
= TRUE
;
9399 /* Just pick up a normal expression. */
9400 my_getExpression (&imm_expr
, s
);
9403 if (imm_expr
.X_op
== O_register
)
9405 /* What we thought was an expression turned out to
9408 if (s
[0] == '(' && args
[1] == '(')
9410 /* It looks like the expression was omitted
9411 before a register indirection, which means
9412 that the expression is implicitly zero. We
9413 still set up imm_expr, so that we handle
9414 explicit extensions correctly. */
9415 imm_expr
.X_op
= O_constant
;
9416 imm_expr
.X_add_number
= 0;
9417 *imm_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
9424 /* We need to relax this instruction. */
9425 *imm_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
9434 /* We use offset_reloc rather than imm_reloc for the PC
9435 relative operands. This lets macros with both
9436 immediate and address operands work correctly. */
9437 my_getExpression (&offset_expr
, s
);
9439 if (offset_expr
.X_op
== O_register
)
9442 /* We need to relax this instruction. */
9443 *offset_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
9447 case '6': /* break code */
9448 my_getExpression (&imm_expr
, s
);
9449 check_absolute_expr (ip
, &imm_expr
);
9450 if ((unsigned long) imm_expr
.X_add_number
> 63)
9452 as_warn (_("Invalid value for `%s' (%lu)"),
9454 (unsigned long) imm_expr
.X_add_number
);
9455 imm_expr
.X_add_number
&= 0x3f;
9457 ip
->insn_opcode
|= imm_expr
.X_add_number
<< MIPS16OP_SH_IMM6
;
9458 imm_expr
.X_op
= O_absent
;
9462 case 'a': /* 26 bit address */
9463 my_getExpression (&offset_expr
, s
);
9465 *offset_reloc
= BFD_RELOC_MIPS16_JMP
;
9466 ip
->insn_opcode
<<= 16;
9469 case 'l': /* register list for entry macro */
9470 case 'L': /* register list for exit macro */
9480 int freg
, reg1
, reg2
;
9482 while (*s
== ' ' || *s
== ',')
9486 as_bad (_("can't parse register list"));
9498 while (ISDIGIT (*s
))
9520 as_bad (_("invalid register list"));
9525 while (ISDIGIT (*s
))
9532 if (freg
&& reg1
== 0 && reg2
== 0 && c
== 'L')
9537 else if (freg
&& reg1
== 0 && reg2
== 1 && c
== 'L')
9542 else if (reg1
== 4 && reg2
>= 4 && reg2
<= 7 && c
!= 'L')
9543 mask
|= (reg2
- 3) << 3;
9544 else if (reg1
== 16 && reg2
>= 16 && reg2
<= 17)
9545 mask
|= (reg2
- 15) << 1;
9546 else if (reg1
== RA
&& reg2
== RA
)
9550 as_bad (_("invalid register list"));
9554 /* The mask is filled in in the opcode table for the
9555 benefit of the disassembler. We remove it before
9556 applying the actual mask. */
9557 ip
->insn_opcode
&= ~ ((7 << 3) << MIPS16OP_SH_IMM6
);
9558 ip
->insn_opcode
|= mask
<< MIPS16OP_SH_IMM6
;
9562 case 'e': /* extend code */
9563 my_getExpression (&imm_expr
, s
);
9564 check_absolute_expr (ip
, &imm_expr
);
9565 if ((unsigned long) imm_expr
.X_add_number
> 0x7ff)
9567 as_warn (_("Invalid value for `%s' (%lu)"),
9569 (unsigned long) imm_expr
.X_add_number
);
9570 imm_expr
.X_add_number
&= 0x7ff;
9572 ip
->insn_opcode
|= imm_expr
.X_add_number
;
9573 imm_expr
.X_op
= O_absent
;
9583 /* Args don't match. */
9584 if (insn
+ 1 < &mips16_opcodes
[bfd_mips16_num_opcodes
] &&
9585 strcmp (insn
->name
, insn
[1].name
) == 0)
9592 insn_error
= _("illegal operands");
9598 /* This structure holds information we know about a mips16 immediate
9601 struct mips16_immed_operand
9603 /* The type code used in the argument string in the opcode table. */
9605 /* The number of bits in the short form of the opcode. */
9607 /* The number of bits in the extended form of the opcode. */
9609 /* The amount by which the short form is shifted when it is used;
9610 for example, the sw instruction has a shift count of 2. */
9612 /* The amount by which the short form is shifted when it is stored
9613 into the instruction code. */
9615 /* Non-zero if the short form is unsigned. */
9617 /* Non-zero if the extended form is unsigned. */
9619 /* Non-zero if the value is PC relative. */
9623 /* The mips16 immediate operand types. */
9625 static const struct mips16_immed_operand mips16_immed_operands
[] =
9627 { '<', 3, 5, 0, MIPS16OP_SH_RZ
, 1, 1, 0 },
9628 { '>', 3, 5, 0, MIPS16OP_SH_RX
, 1, 1, 0 },
9629 { '[', 3, 6, 0, MIPS16OP_SH_RZ
, 1, 1, 0 },
9630 { ']', 3, 6, 0, MIPS16OP_SH_RX
, 1, 1, 0 },
9631 { '4', 4, 15, 0, MIPS16OP_SH_IMM4
, 0, 0, 0 },
9632 { '5', 5, 16, 0, MIPS16OP_SH_IMM5
, 1, 0, 0 },
9633 { 'H', 5, 16, 1, MIPS16OP_SH_IMM5
, 1, 0, 0 },
9634 { 'W', 5, 16, 2, MIPS16OP_SH_IMM5
, 1, 0, 0 },
9635 { 'D', 5, 16, 3, MIPS16OP_SH_IMM5
, 1, 0, 0 },
9636 { 'j', 5, 16, 0, MIPS16OP_SH_IMM5
, 0, 0, 0 },
9637 { '8', 8, 16, 0, MIPS16OP_SH_IMM8
, 1, 0, 0 },
9638 { 'V', 8, 16, 2, MIPS16OP_SH_IMM8
, 1, 0, 0 },
9639 { 'C', 8, 16, 3, MIPS16OP_SH_IMM8
, 1, 0, 0 },
9640 { 'U', 8, 16, 0, MIPS16OP_SH_IMM8
, 1, 1, 0 },
9641 { 'k', 8, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 0 },
9642 { 'K', 8, 16, 3, MIPS16OP_SH_IMM8
, 0, 0, 0 },
9643 { 'p', 8, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 1 },
9644 { 'q', 11, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 1 },
9645 { 'A', 8, 16, 2, MIPS16OP_SH_IMM8
, 1, 0, 1 },
9646 { 'B', 5, 16, 3, MIPS16OP_SH_IMM5
, 1, 0, 1 },
9647 { 'E', 5, 16, 2, MIPS16OP_SH_IMM5
, 1, 0, 1 }
9650 #define MIPS16_NUM_IMMED \
9651 (sizeof mips16_immed_operands / sizeof mips16_immed_operands[0])
9653 /* Handle a mips16 instruction with an immediate value. This or's the
9654 small immediate value into *INSN. It sets *USE_EXTEND to indicate
9655 whether an extended value is needed; if one is needed, it sets
9656 *EXTEND to the value. The argument type is TYPE. The value is VAL.
9657 If SMALL is true, an unextended opcode was explicitly requested.
9658 If EXT is true, an extended opcode was explicitly requested. If
9659 WARN is true, warn if EXT does not match reality. */
9662 mips16_immed (char *file
, unsigned int line
, int type
, offsetT val
,
9663 bfd_boolean warn
, bfd_boolean small
, bfd_boolean ext
,
9664 unsigned long *insn
, bfd_boolean
*use_extend
,
9665 unsigned short *extend
)
9667 register const struct mips16_immed_operand
*op
;
9668 int mintiny
, maxtiny
;
9669 bfd_boolean needext
;
9671 op
= mips16_immed_operands
;
9672 while (op
->type
!= type
)
9675 assert (op
< mips16_immed_operands
+ MIPS16_NUM_IMMED
);
9680 if (type
== '<' || type
== '>' || type
== '[' || type
== ']')
9683 maxtiny
= 1 << op
->nbits
;
9688 maxtiny
= (1 << op
->nbits
) - 1;
9693 mintiny
= - (1 << (op
->nbits
- 1));
9694 maxtiny
= (1 << (op
->nbits
- 1)) - 1;
9697 /* Branch offsets have an implicit 0 in the lowest bit. */
9698 if (type
== 'p' || type
== 'q')
9701 if ((val
& ((1 << op
->shift
) - 1)) != 0
9702 || val
< (mintiny
<< op
->shift
)
9703 || val
> (maxtiny
<< op
->shift
))
9708 if (warn
&& ext
&& ! needext
)
9709 as_warn_where (file
, line
,
9710 _("extended operand requested but not required"));
9711 if (small
&& needext
)
9712 as_bad_where (file
, line
, _("invalid unextended operand value"));
9714 if (small
|| (! ext
&& ! needext
))
9718 *use_extend
= FALSE
;
9719 insnval
= ((val
>> op
->shift
) & ((1 << op
->nbits
) - 1));
9720 insnval
<<= op
->op_shift
;
9725 long minext
, maxext
;
9731 maxext
= (1 << op
->extbits
) - 1;
9735 minext
= - (1 << (op
->extbits
- 1));
9736 maxext
= (1 << (op
->extbits
- 1)) - 1;
9738 if (val
< minext
|| val
> maxext
)
9739 as_bad_where (file
, line
,
9740 _("operand value out of range for instruction"));
9743 if (op
->extbits
== 16)
9745 extval
= ((val
>> 11) & 0x1f) | (val
& 0x7e0);
9748 else if (op
->extbits
== 15)
9750 extval
= ((val
>> 11) & 0xf) | (val
& 0x7f0);
9755 extval
= ((val
& 0x1f) << 6) | (val
& 0x20);
9759 *extend
= (unsigned short) extval
;
9764 static const struct percent_op_match
9767 bfd_reloc_code_real_type reloc
;
9770 {"%lo", BFD_RELOC_LO16
},
9772 {"%call_hi", BFD_RELOC_MIPS_CALL_HI16
},
9773 {"%call_lo", BFD_RELOC_MIPS_CALL_LO16
},
9774 {"%call16", BFD_RELOC_MIPS_CALL16
},
9775 {"%got_disp", BFD_RELOC_MIPS_GOT_DISP
},
9776 {"%got_page", BFD_RELOC_MIPS_GOT_PAGE
},
9777 {"%got_ofst", BFD_RELOC_MIPS_GOT_OFST
},
9778 {"%got_hi", BFD_RELOC_MIPS_GOT_HI16
},
9779 {"%got_lo", BFD_RELOC_MIPS_GOT_LO16
},
9780 {"%got", BFD_RELOC_MIPS_GOT16
},
9781 {"%gp_rel", BFD_RELOC_GPREL16
},
9782 {"%half", BFD_RELOC_16
},
9783 {"%highest", BFD_RELOC_MIPS_HIGHEST
},
9784 {"%higher", BFD_RELOC_MIPS_HIGHER
},
9785 {"%neg", BFD_RELOC_MIPS_SUB
},
9787 {"%hi", BFD_RELOC_HI16_S
}
9791 /* Return true if *STR points to a relocation operator. When returning true,
9792 move *STR over the operator and store its relocation code in *RELOC.
9793 Leave both *STR and *RELOC alone when returning false. */
9796 parse_relocation (char **str
, bfd_reloc_code_real_type
*reloc
)
9800 for (i
= 0; i
< ARRAY_SIZE (percent_op
); i
++)
9801 if (strncasecmp (*str
, percent_op
[i
].str
, strlen (percent_op
[i
].str
)) == 0)
9803 *str
+= strlen (percent_op
[i
].str
);
9804 *reloc
= percent_op
[i
].reloc
;
9806 /* Check whether the output BFD supports this relocation.
9807 If not, issue an error and fall back on something safe. */
9808 if (!bfd_reloc_type_lookup (stdoutput
, percent_op
[i
].reloc
))
9810 as_bad ("relocation %s isn't supported by the current ABI",
9812 *reloc
= BFD_RELOC_LO16
;
9820 /* Parse string STR as a 16-bit relocatable operand. Store the
9821 expression in *EP and the relocations in the array starting
9822 at RELOC. Return the number of relocation operators used.
9824 On exit, EXPR_END points to the first character after the expression.
9825 If no relocation operators are used, RELOC[0] is set to BFD_RELOC_LO16. */
9828 my_getSmallExpression (expressionS
*ep
, bfd_reloc_code_real_type
*reloc
,
9831 bfd_reloc_code_real_type reversed_reloc
[3];
9832 size_t reloc_index
, i
;
9833 int crux_depth
, str_depth
;
9836 /* Search for the start of the main expression, recoding relocations
9837 in REVERSED_RELOC. End the loop with CRUX pointing to the start
9838 of the main expression and with CRUX_DEPTH containing the number
9839 of open brackets at that point. */
9846 crux_depth
= str_depth
;
9848 /* Skip over whitespace and brackets, keeping count of the number
9850 while (*str
== ' ' || *str
== '\t' || *str
== '(')
9855 && reloc_index
< (HAVE_NEWABI
? 3 : 1)
9856 && parse_relocation (&str
, &reversed_reloc
[reloc_index
]));
9858 my_getExpression (ep
, crux
);
9861 /* Match every open bracket. */
9862 while (crux_depth
> 0 && (*str
== ')' || *str
== ' ' || *str
== '\t'))
9867 as_bad ("unclosed '('");
9871 if (reloc_index
== 0)
9872 reloc
[0] = BFD_RELOC_LO16
;
9875 prev_reloc_op_frag
= frag_now
;
9876 for (i
= 0; i
< reloc_index
; i
++)
9877 reloc
[i
] = reversed_reloc
[reloc_index
- 1 - i
];
9884 my_getExpression (expressionS
*ep
, char *str
)
9889 save_in
= input_line_pointer
;
9890 input_line_pointer
= str
;
9892 expr_end
= input_line_pointer
;
9893 input_line_pointer
= save_in
;
9895 /* If we are in mips16 mode, and this is an expression based on `.',
9896 then we bump the value of the symbol by 1 since that is how other
9897 text symbols are handled. We don't bother to handle complex
9898 expressions, just `.' plus or minus a constant. */
9899 if (mips_opts
.mips16
9900 && ep
->X_op
== O_symbol
9901 && strcmp (S_GET_NAME (ep
->X_add_symbol
), FAKE_LABEL_NAME
) == 0
9902 && S_GET_SEGMENT (ep
->X_add_symbol
) == now_seg
9903 && symbol_get_frag (ep
->X_add_symbol
) == frag_now
9904 && symbol_constant_p (ep
->X_add_symbol
)
9905 && (val
= S_GET_VALUE (ep
->X_add_symbol
)) == frag_now_fix ())
9906 S_SET_VALUE (ep
->X_add_symbol
, val
+ 1);
9909 /* Turn a string in input_line_pointer into a floating point constant
9910 of type TYPE, and store the appropriate bytes in *LITP. The number
9911 of LITTLENUMS emitted is stored in *SIZEP. An error message is
9912 returned, or NULL on OK. */
9915 md_atof (int type
, char *litP
, int *sizeP
)
9918 LITTLENUM_TYPE words
[4];
9934 return _("bad call to md_atof");
9937 t
= atof_ieee (input_line_pointer
, type
, words
);
9939 input_line_pointer
= t
;
9943 if (! target_big_endian
)
9945 for (i
= prec
- 1; i
>= 0; i
--)
9947 md_number_to_chars (litP
, words
[i
], 2);
9953 for (i
= 0; i
< prec
; i
++)
9955 md_number_to_chars (litP
, words
[i
], 2);
9964 md_number_to_chars (char *buf
, valueT val
, int n
)
9966 if (target_big_endian
)
9967 number_to_chars_bigendian (buf
, val
, n
);
9969 number_to_chars_littleendian (buf
, val
, n
);
9973 static int support_64bit_objects(void)
9975 const char **list
, **l
;
9978 list
= bfd_target_list ();
9979 for (l
= list
; *l
!= NULL
; l
++)
9981 /* This is traditional mips */
9982 if (strcmp (*l
, "elf64-tradbigmips") == 0
9983 || strcmp (*l
, "elf64-tradlittlemips") == 0)
9985 if (strcmp (*l
, "elf64-bigmips") == 0
9986 || strcmp (*l
, "elf64-littlemips") == 0)
9993 #endif /* OBJ_ELF */
9995 const char *md_shortopts
= "O::g::G:";
9997 struct option md_longopts
[] =
9999 /* Options which specify architecture. */
10000 #define OPTION_ARCH_BASE (OPTION_MD_BASE)
10001 #define OPTION_MARCH (OPTION_ARCH_BASE + 0)
10002 {"march", required_argument
, NULL
, OPTION_MARCH
},
10003 #define OPTION_MTUNE (OPTION_ARCH_BASE + 1)
10004 {"mtune", required_argument
, NULL
, OPTION_MTUNE
},
10005 #define OPTION_MIPS1 (OPTION_ARCH_BASE + 2)
10006 {"mips0", no_argument
, NULL
, OPTION_MIPS1
},
10007 {"mips1", no_argument
, NULL
, OPTION_MIPS1
},
10008 #define OPTION_MIPS2 (OPTION_ARCH_BASE + 3)
10009 {"mips2", no_argument
, NULL
, OPTION_MIPS2
},
10010 #define OPTION_MIPS3 (OPTION_ARCH_BASE + 4)
10011 {"mips3", no_argument
, NULL
, OPTION_MIPS3
},
10012 #define OPTION_MIPS4 (OPTION_ARCH_BASE + 5)
10013 {"mips4", no_argument
, NULL
, OPTION_MIPS4
},
10014 #define OPTION_MIPS5 (OPTION_ARCH_BASE + 6)
10015 {"mips5", no_argument
, NULL
, OPTION_MIPS5
},
10016 #define OPTION_MIPS32 (OPTION_ARCH_BASE + 7)
10017 {"mips32", no_argument
, NULL
, OPTION_MIPS32
},
10018 #define OPTION_MIPS64 (OPTION_ARCH_BASE + 8)
10019 {"mips64", no_argument
, NULL
, OPTION_MIPS64
},
10020 #define OPTION_MIPS32R2 (OPTION_ARCH_BASE + 9)
10021 {"mips32r2", no_argument
, NULL
, OPTION_MIPS32R2
},
10022 #define OPTION_MIPS64R2 (OPTION_ARCH_BASE + 10)
10023 {"mips64r2", no_argument
, NULL
, OPTION_MIPS64R2
},
10025 /* Options which specify Application Specific Extensions (ASEs). */
10026 #define OPTION_ASE_BASE (OPTION_ARCH_BASE + 11)
10027 #define OPTION_MIPS16 (OPTION_ASE_BASE + 0)
10028 {"mips16", no_argument
, NULL
, OPTION_MIPS16
},
10029 #define OPTION_NO_MIPS16 (OPTION_ASE_BASE + 1)
10030 {"no-mips16", no_argument
, NULL
, OPTION_NO_MIPS16
},
10031 #define OPTION_MIPS3D (OPTION_ASE_BASE + 2)
10032 {"mips3d", no_argument
, NULL
, OPTION_MIPS3D
},
10033 #define OPTION_NO_MIPS3D (OPTION_ASE_BASE + 3)
10034 {"no-mips3d", no_argument
, NULL
, OPTION_NO_MIPS3D
},
10035 #define OPTION_MDMX (OPTION_ASE_BASE + 4)
10036 {"mdmx", no_argument
, NULL
, OPTION_MDMX
},
10037 #define OPTION_NO_MDMX (OPTION_ASE_BASE + 5)
10038 {"no-mdmx", no_argument
, NULL
, OPTION_NO_MDMX
},
10040 /* Old-style architecture options. Don't add more of these. */
10041 #define OPTION_COMPAT_ARCH_BASE (OPTION_ASE_BASE + 6)
10042 #define OPTION_M4650 (OPTION_COMPAT_ARCH_BASE + 0)
10043 {"m4650", no_argument
, NULL
, OPTION_M4650
},
10044 #define OPTION_NO_M4650 (OPTION_COMPAT_ARCH_BASE + 1)
10045 {"no-m4650", no_argument
, NULL
, OPTION_NO_M4650
},
10046 #define OPTION_M4010 (OPTION_COMPAT_ARCH_BASE + 2)
10047 {"m4010", no_argument
, NULL
, OPTION_M4010
},
10048 #define OPTION_NO_M4010 (OPTION_COMPAT_ARCH_BASE + 3)
10049 {"no-m4010", no_argument
, NULL
, OPTION_NO_M4010
},
10050 #define OPTION_M4100 (OPTION_COMPAT_ARCH_BASE + 4)
10051 {"m4100", no_argument
, NULL
, OPTION_M4100
},
10052 #define OPTION_NO_M4100 (OPTION_COMPAT_ARCH_BASE + 5)
10053 {"no-m4100", no_argument
, NULL
, OPTION_NO_M4100
},
10054 #define OPTION_M3900 (OPTION_COMPAT_ARCH_BASE + 6)
10055 {"m3900", no_argument
, NULL
, OPTION_M3900
},
10056 #define OPTION_NO_M3900 (OPTION_COMPAT_ARCH_BASE + 7)
10057 {"no-m3900", no_argument
, NULL
, OPTION_NO_M3900
},
10059 /* Options which enable bug fixes. */
10060 #define OPTION_FIX_BASE (OPTION_COMPAT_ARCH_BASE + 8)
10061 #define OPTION_M7000_HILO_FIX (OPTION_FIX_BASE + 0)
10062 {"mfix7000", no_argument
, NULL
, OPTION_M7000_HILO_FIX
},
10063 #define OPTION_MNO_7000_HILO_FIX (OPTION_FIX_BASE + 1)
10064 {"no-fix-7000", no_argument
, NULL
, OPTION_MNO_7000_HILO_FIX
},
10065 {"mno-fix7000", no_argument
, NULL
, OPTION_MNO_7000_HILO_FIX
},
10066 #define OPTION_FIX_VR4120 (OPTION_FIX_BASE + 2)
10067 #define OPTION_NO_FIX_VR4120 (OPTION_FIX_BASE + 3)
10068 {"mfix-vr4120", no_argument
, NULL
, OPTION_FIX_VR4120
},
10069 {"mno-fix-vr4120", no_argument
, NULL
, OPTION_NO_FIX_VR4120
},
10071 /* Miscellaneous options. */
10072 #define OPTION_MISC_BASE (OPTION_FIX_BASE + 4)
10073 #define OPTION_TRAP (OPTION_MISC_BASE + 0)
10074 {"trap", no_argument
, NULL
, OPTION_TRAP
},
10075 {"no-break", no_argument
, NULL
, OPTION_TRAP
},
10076 #define OPTION_BREAK (OPTION_MISC_BASE + 1)
10077 {"break", no_argument
, NULL
, OPTION_BREAK
},
10078 {"no-trap", no_argument
, NULL
, OPTION_BREAK
},
10079 #define OPTION_EB (OPTION_MISC_BASE + 2)
10080 {"EB", no_argument
, NULL
, OPTION_EB
},
10081 #define OPTION_EL (OPTION_MISC_BASE + 3)
10082 {"EL", no_argument
, NULL
, OPTION_EL
},
10083 #define OPTION_FP32 (OPTION_MISC_BASE + 4)
10084 {"mfp32", no_argument
, NULL
, OPTION_FP32
},
10085 #define OPTION_GP32 (OPTION_MISC_BASE + 5)
10086 {"mgp32", no_argument
, NULL
, OPTION_GP32
},
10087 #define OPTION_CONSTRUCT_FLOATS (OPTION_MISC_BASE + 6)
10088 {"construct-floats", no_argument
, NULL
, OPTION_CONSTRUCT_FLOATS
},
10089 #define OPTION_NO_CONSTRUCT_FLOATS (OPTION_MISC_BASE + 7)
10090 {"no-construct-floats", no_argument
, NULL
, OPTION_NO_CONSTRUCT_FLOATS
},
10091 #define OPTION_FP64 (OPTION_MISC_BASE + 8)
10092 {"mfp64", no_argument
, NULL
, OPTION_FP64
},
10093 #define OPTION_GP64 (OPTION_MISC_BASE + 9)
10094 {"mgp64", no_argument
, NULL
, OPTION_GP64
},
10095 #define OPTION_RELAX_BRANCH (OPTION_MISC_BASE + 10)
10096 #define OPTION_NO_RELAX_BRANCH (OPTION_MISC_BASE + 11)
10097 {"relax-branch", no_argument
, NULL
, OPTION_RELAX_BRANCH
},
10098 {"no-relax-branch", no_argument
, NULL
, OPTION_NO_RELAX_BRANCH
},
10100 /* ELF-specific options. */
10102 #define OPTION_ELF_BASE (OPTION_MISC_BASE + 12)
10103 #define OPTION_CALL_SHARED (OPTION_ELF_BASE + 0)
10104 {"KPIC", no_argument
, NULL
, OPTION_CALL_SHARED
},
10105 {"call_shared", no_argument
, NULL
, OPTION_CALL_SHARED
},
10106 #define OPTION_NON_SHARED (OPTION_ELF_BASE + 1)
10107 {"non_shared", no_argument
, NULL
, OPTION_NON_SHARED
},
10108 #define OPTION_XGOT (OPTION_ELF_BASE + 2)
10109 {"xgot", no_argument
, NULL
, OPTION_XGOT
},
10110 #define OPTION_MABI (OPTION_ELF_BASE + 3)
10111 {"mabi", required_argument
, NULL
, OPTION_MABI
},
10112 #define OPTION_32 (OPTION_ELF_BASE + 4)
10113 {"32", no_argument
, NULL
, OPTION_32
},
10114 #define OPTION_N32 (OPTION_ELF_BASE + 5)
10115 {"n32", no_argument
, NULL
, OPTION_N32
},
10116 #define OPTION_64 (OPTION_ELF_BASE + 6)
10117 {"64", no_argument
, NULL
, OPTION_64
},
10118 #define OPTION_MDEBUG (OPTION_ELF_BASE + 7)
10119 {"mdebug", no_argument
, NULL
, OPTION_MDEBUG
},
10120 #define OPTION_NO_MDEBUG (OPTION_ELF_BASE + 8)
10121 {"no-mdebug", no_argument
, NULL
, OPTION_NO_MDEBUG
},
10122 #define OPTION_PDR (OPTION_ELF_BASE + 9)
10123 {"mpdr", no_argument
, NULL
, OPTION_PDR
},
10124 #define OPTION_NO_PDR (OPTION_ELF_BASE + 10)
10125 {"mno-pdr", no_argument
, NULL
, OPTION_NO_PDR
},
10126 #endif /* OBJ_ELF */
10128 {NULL
, no_argument
, NULL
, 0}
10130 size_t md_longopts_size
= sizeof (md_longopts
);
10132 /* Set STRING_PTR (either &mips_arch_string or &mips_tune_string) to
10133 NEW_VALUE. Warn if another value was already specified. Note:
10134 we have to defer parsing the -march and -mtune arguments in order
10135 to handle 'from-abi' correctly, since the ABI might be specified
10136 in a later argument. */
10139 mips_set_option_string (const char **string_ptr
, const char *new_value
)
10141 if (*string_ptr
!= 0 && strcasecmp (*string_ptr
, new_value
) != 0)
10142 as_warn (_("A different %s was already specified, is now %s"),
10143 string_ptr
== &mips_arch_string
? "-march" : "-mtune",
10146 *string_ptr
= new_value
;
10150 md_parse_option (int c
, char *arg
)
10154 case OPTION_CONSTRUCT_FLOATS
:
10155 mips_disable_float_construction
= 0;
10158 case OPTION_NO_CONSTRUCT_FLOATS
:
10159 mips_disable_float_construction
= 1;
10171 target_big_endian
= 1;
10175 target_big_endian
= 0;
10179 if (arg
&& arg
[1] == '0')
10189 mips_debug
= atoi (arg
);
10190 /* When the MIPS assembler sees -g or -g2, it does not do
10191 optimizations which limit full symbolic debugging. We take
10192 that to be equivalent to -O0. */
10193 if (mips_debug
== 2)
10198 file_mips_isa
= ISA_MIPS1
;
10202 file_mips_isa
= ISA_MIPS2
;
10206 file_mips_isa
= ISA_MIPS3
;
10210 file_mips_isa
= ISA_MIPS4
;
10214 file_mips_isa
= ISA_MIPS5
;
10217 case OPTION_MIPS32
:
10218 file_mips_isa
= ISA_MIPS32
;
10221 case OPTION_MIPS32R2
:
10222 file_mips_isa
= ISA_MIPS32R2
;
10225 case OPTION_MIPS64R2
:
10226 file_mips_isa
= ISA_MIPS64R2
;
10229 case OPTION_MIPS64
:
10230 file_mips_isa
= ISA_MIPS64
;
10234 mips_set_option_string (&mips_tune_string
, arg
);
10238 mips_set_option_string (&mips_arch_string
, arg
);
10242 mips_set_option_string (&mips_arch_string
, "4650");
10243 mips_set_option_string (&mips_tune_string
, "4650");
10246 case OPTION_NO_M4650
:
10250 mips_set_option_string (&mips_arch_string
, "4010");
10251 mips_set_option_string (&mips_tune_string
, "4010");
10254 case OPTION_NO_M4010
:
10258 mips_set_option_string (&mips_arch_string
, "4100");
10259 mips_set_option_string (&mips_tune_string
, "4100");
10262 case OPTION_NO_M4100
:
10266 mips_set_option_string (&mips_arch_string
, "3900");
10267 mips_set_option_string (&mips_tune_string
, "3900");
10270 case OPTION_NO_M3900
:
10274 mips_opts
.ase_mdmx
= 1;
10277 case OPTION_NO_MDMX
:
10278 mips_opts
.ase_mdmx
= 0;
10281 case OPTION_MIPS16
:
10282 mips_opts
.mips16
= 1;
10283 mips_no_prev_insn (FALSE
);
10286 case OPTION_NO_MIPS16
:
10287 mips_opts
.mips16
= 0;
10288 mips_no_prev_insn (FALSE
);
10291 case OPTION_MIPS3D
:
10292 mips_opts
.ase_mips3d
= 1;
10295 case OPTION_NO_MIPS3D
:
10296 mips_opts
.ase_mips3d
= 0;
10299 case OPTION_FIX_VR4120
:
10300 mips_fix_vr4120
= 1;
10303 case OPTION_NO_FIX_VR4120
:
10304 mips_fix_vr4120
= 0;
10307 case OPTION_RELAX_BRANCH
:
10308 mips_relax_branch
= 1;
10311 case OPTION_NO_RELAX_BRANCH
:
10312 mips_relax_branch
= 0;
10316 /* When generating ELF code, we permit -KPIC and -call_shared to
10317 select SVR4_PIC, and -non_shared to select no PIC. This is
10318 intended to be compatible with Irix 5. */
10319 case OPTION_CALL_SHARED
:
10320 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
10322 as_bad (_("-call_shared is supported only for ELF format"));
10325 mips_pic
= SVR4_PIC
;
10326 mips_abicalls
= TRUE
;
10327 if (g_switch_seen
&& g_switch_value
!= 0)
10329 as_bad (_("-G may not be used with SVR4 PIC code"));
10332 g_switch_value
= 0;
10335 case OPTION_NON_SHARED
:
10336 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
10338 as_bad (_("-non_shared is supported only for ELF format"));
10342 mips_abicalls
= FALSE
;
10345 /* The -xgot option tells the assembler to use 32 offsets when
10346 accessing the got in SVR4_PIC mode. It is for Irix
10351 #endif /* OBJ_ELF */
10354 if (mips_pic
== SVR4_PIC
)
10356 as_bad (_("-G may not be used with SVR4 PIC code"));
10360 g_switch_value
= atoi (arg
);
10365 /* The -32, -n32 and -64 options are shortcuts for -mabi=32, -mabi=n32
10368 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
10370 as_bad (_("-32 is supported for ELF format only"));
10373 mips_abi
= O32_ABI
;
10377 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
10379 as_bad (_("-n32 is supported for ELF format only"));
10382 mips_abi
= N32_ABI
;
10386 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
10388 as_bad (_("-64 is supported for ELF format only"));
10391 mips_abi
= N64_ABI
;
10392 if (! support_64bit_objects())
10393 as_fatal (_("No compiled in support for 64 bit object file format"));
10395 #endif /* OBJ_ELF */
10398 file_mips_gp32
= 1;
10402 file_mips_gp32
= 0;
10406 file_mips_fp32
= 1;
10410 file_mips_fp32
= 0;
10415 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
10417 as_bad (_("-mabi is supported for ELF format only"));
10420 if (strcmp (arg
, "32") == 0)
10421 mips_abi
= O32_ABI
;
10422 else if (strcmp (arg
, "o64") == 0)
10423 mips_abi
= O64_ABI
;
10424 else if (strcmp (arg
, "n32") == 0)
10425 mips_abi
= N32_ABI
;
10426 else if (strcmp (arg
, "64") == 0)
10428 mips_abi
= N64_ABI
;
10429 if (! support_64bit_objects())
10430 as_fatal (_("No compiled in support for 64 bit object file "
10433 else if (strcmp (arg
, "eabi") == 0)
10434 mips_abi
= EABI_ABI
;
10437 as_fatal (_("invalid abi -mabi=%s"), arg
);
10441 #endif /* OBJ_ELF */
10443 case OPTION_M7000_HILO_FIX
:
10444 mips_7000_hilo_fix
= TRUE
;
10447 case OPTION_MNO_7000_HILO_FIX
:
10448 mips_7000_hilo_fix
= FALSE
;
10452 case OPTION_MDEBUG
:
10453 mips_flag_mdebug
= TRUE
;
10456 case OPTION_NO_MDEBUG
:
10457 mips_flag_mdebug
= FALSE
;
10461 mips_flag_pdr
= TRUE
;
10464 case OPTION_NO_PDR
:
10465 mips_flag_pdr
= FALSE
;
10467 #endif /* OBJ_ELF */
10476 /* Set up globals to generate code for the ISA or processor
10477 described by INFO. */
10480 mips_set_architecture (const struct mips_cpu_info
*info
)
10484 file_mips_arch
= info
->cpu
;
10485 mips_opts
.arch
= info
->cpu
;
10486 mips_opts
.isa
= info
->isa
;
10491 /* Likewise for tuning. */
10494 mips_set_tune (const struct mips_cpu_info
*info
)
10497 mips_tune
= info
->cpu
;
10502 mips_after_parse_args (void)
10504 const struct mips_cpu_info
*arch_info
= 0;
10505 const struct mips_cpu_info
*tune_info
= 0;
10507 /* GP relative stuff not working for PE */
10508 if (strncmp (TARGET_OS
, "pe", 2) == 0
10509 && g_switch_value
!= 0)
10512 as_bad (_("-G not supported in this configuration."));
10513 g_switch_value
= 0;
10516 if (mips_abi
== NO_ABI
)
10517 mips_abi
= MIPS_DEFAULT_ABI
;
10519 /* The following code determines the architecture and register size.
10520 Similar code was added to GCC 3.3 (see override_options() in
10521 config/mips/mips.c). The GAS and GCC code should be kept in sync
10522 as much as possible. */
10524 if (mips_arch_string
!= 0)
10525 arch_info
= mips_parse_cpu ("-march", mips_arch_string
);
10527 if (file_mips_isa
!= ISA_UNKNOWN
)
10529 /* Handle -mipsN. At this point, file_mips_isa contains the
10530 ISA level specified by -mipsN, while arch_info->isa contains
10531 the -march selection (if any). */
10532 if (arch_info
!= 0)
10534 /* -march takes precedence over -mipsN, since it is more descriptive.
10535 There's no harm in specifying both as long as the ISA levels
10537 if (file_mips_isa
!= arch_info
->isa
)
10538 as_bad (_("-%s conflicts with the other architecture options, which imply -%s"),
10539 mips_cpu_info_from_isa (file_mips_isa
)->name
,
10540 mips_cpu_info_from_isa (arch_info
->isa
)->name
);
10543 arch_info
= mips_cpu_info_from_isa (file_mips_isa
);
10546 if (arch_info
== 0)
10547 arch_info
= mips_parse_cpu ("default CPU", MIPS_CPU_STRING_DEFAULT
);
10549 if (ABI_NEEDS_64BIT_REGS (mips_abi
) && !ISA_HAS_64BIT_REGS (arch_info
->isa
))
10550 as_bad ("-march=%s is not compatible with the selected ABI",
10553 mips_set_architecture (arch_info
);
10555 /* Optimize for file_mips_arch, unless -mtune selects a different processor. */
10556 if (mips_tune_string
!= 0)
10557 tune_info
= mips_parse_cpu ("-mtune", mips_tune_string
);
10559 if (tune_info
== 0)
10560 mips_set_tune (arch_info
);
10562 mips_set_tune (tune_info
);
10564 if (file_mips_gp32
>= 0)
10566 /* The user specified the size of the integer registers. Make sure
10567 it agrees with the ABI and ISA. */
10568 if (file_mips_gp32
== 0 && !ISA_HAS_64BIT_REGS (mips_opts
.isa
))
10569 as_bad (_("-mgp64 used with a 32-bit processor"));
10570 else if (file_mips_gp32
== 1 && ABI_NEEDS_64BIT_REGS (mips_abi
))
10571 as_bad (_("-mgp32 used with a 64-bit ABI"));
10572 else if (file_mips_gp32
== 0 && ABI_NEEDS_32BIT_REGS (mips_abi
))
10573 as_bad (_("-mgp64 used with a 32-bit ABI"));
10577 /* Infer the integer register size from the ABI and processor.
10578 Restrict ourselves to 32-bit registers if that's all the
10579 processor has, or if the ABI cannot handle 64-bit registers. */
10580 file_mips_gp32
= (ABI_NEEDS_32BIT_REGS (mips_abi
)
10581 || !ISA_HAS_64BIT_REGS (mips_opts
.isa
));
10584 /* ??? GAS treats single-float processors as though they had 64-bit
10585 float registers (although it complains when double-precision
10586 instructions are used). As things stand, saying they have 32-bit
10587 registers would lead to spurious "register must be even" messages.
10588 So here we assume float registers are always the same size as
10589 integer ones, unless the user says otherwise. */
10590 if (file_mips_fp32
< 0)
10591 file_mips_fp32
= file_mips_gp32
;
10593 /* End of GCC-shared inference code. */
10595 /* This flag is set when we have a 64-bit capable CPU but use only
10596 32-bit wide registers. Note that EABI does not use it. */
10597 if (ISA_HAS_64BIT_REGS (mips_opts
.isa
)
10598 && ((mips_abi
== NO_ABI
&& file_mips_gp32
== 1)
10599 || mips_abi
== O32_ABI
))
10600 mips_32bitmode
= 1;
10602 if (mips_opts
.isa
== ISA_MIPS1
&& mips_trap
)
10603 as_bad (_("trap exception not supported at ISA 1"));
10605 /* If the selected architecture includes support for ASEs, enable
10606 generation of code for them. */
10607 if (mips_opts
.mips16
== -1)
10608 mips_opts
.mips16
= (CPU_HAS_MIPS16 (file_mips_arch
)) ? 1 : 0;
10609 if (mips_opts
.ase_mips3d
== -1)
10610 mips_opts
.ase_mips3d
= (CPU_HAS_MIPS3D (file_mips_arch
)) ? 1 : 0;
10611 if (mips_opts
.ase_mdmx
== -1)
10612 mips_opts
.ase_mdmx
= (CPU_HAS_MDMX (file_mips_arch
)) ? 1 : 0;
10614 file_mips_isa
= mips_opts
.isa
;
10615 file_ase_mips16
= mips_opts
.mips16
;
10616 file_ase_mips3d
= mips_opts
.ase_mips3d
;
10617 file_ase_mdmx
= mips_opts
.ase_mdmx
;
10618 mips_opts
.gp32
= file_mips_gp32
;
10619 mips_opts
.fp32
= file_mips_fp32
;
10621 if (mips_flag_mdebug
< 0)
10623 #ifdef OBJ_MAYBE_ECOFF
10624 if (OUTPUT_FLAVOR
== bfd_target_ecoff_flavour
)
10625 mips_flag_mdebug
= 1;
10627 #endif /* OBJ_MAYBE_ECOFF */
10628 mips_flag_mdebug
= 0;
10633 mips_init_after_args (void)
10635 /* initialize opcodes */
10636 bfd_mips_num_opcodes
= bfd_mips_num_builtin_opcodes
;
10637 mips_opcodes
= (struct mips_opcode
*) mips_builtin_opcodes
;
10641 md_pcrel_from (fixS
*fixP
)
10643 valueT addr
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
10644 switch (fixP
->fx_r_type
)
10646 case BFD_RELOC_16_PCREL_S2
:
10647 case BFD_RELOC_MIPS_JMP
:
10648 /* Return the address of the delay slot. */
10655 /* This is called before the symbol table is processed. In order to
10656 work with gcc when using mips-tfile, we must keep all local labels.
10657 However, in other cases, we want to discard them. If we were
10658 called with -g, but we didn't see any debugging information, it may
10659 mean that gcc is smuggling debugging information through to
10660 mips-tfile, in which case we must generate all local labels. */
10663 mips_frob_file_before_adjust (void)
10665 #ifndef NO_ECOFF_DEBUGGING
10666 if (ECOFF_DEBUGGING
10668 && ! ecoff_debugging_seen
)
10669 flag_keep_locals
= 1;
10673 /* Sort any unmatched HI16_S relocs so that they immediately precede
10674 the corresponding LO reloc. This is called before md_apply_fix3 and
10675 tc_gen_reloc. Unmatched HI16_S relocs can only be generated by
10676 explicit use of the %hi modifier. */
10679 mips_frob_file (void)
10681 struct mips_hi_fixup
*l
;
10683 for (l
= mips_hi_fixup_list
; l
!= NULL
; l
= l
->next
)
10685 segment_info_type
*seginfo
;
10688 assert (reloc_needs_lo_p (l
->fixp
->fx_r_type
));
10690 /* If a GOT16 relocation turns out to be against a global symbol,
10691 there isn't supposed to be a matching LO. */
10692 if (l
->fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT16
10693 && !pic_need_relax (l
->fixp
->fx_addsy
, l
->seg
))
10696 /* Check quickly whether the next fixup happens to be a matching %lo. */
10697 if (fixup_has_matching_lo_p (l
->fixp
))
10700 /* Look through the fixups for this segment for a matching %lo.
10701 When we find one, move the %hi just in front of it. We do
10702 this in two passes. In the first pass, we try to find a
10703 unique %lo. In the second pass, we permit multiple %hi
10704 relocs for a single %lo (this is a GNU extension). */
10705 seginfo
= seg_info (l
->seg
);
10706 for (pass
= 0; pass
< 2; pass
++)
10711 for (f
= seginfo
->fix_root
; f
!= NULL
; f
= f
->fx_next
)
10713 /* Check whether this is a %lo fixup which matches l->fixp. */
10714 if (f
->fx_r_type
== BFD_RELOC_LO16
10715 && f
->fx_addsy
== l
->fixp
->fx_addsy
10716 && f
->fx_offset
== l
->fixp
->fx_offset
10719 || !reloc_needs_lo_p (prev
->fx_r_type
)
10720 || !fixup_has_matching_lo_p (prev
)))
10724 /* Move l->fixp before f. */
10725 for (pf
= &seginfo
->fix_root
;
10727 pf
= &(*pf
)->fx_next
)
10728 assert (*pf
!= NULL
);
10730 *pf
= l
->fixp
->fx_next
;
10732 l
->fixp
->fx_next
= f
;
10734 seginfo
->fix_root
= l
->fixp
;
10736 prev
->fx_next
= l
->fixp
;
10747 #if 0 /* GCC code motion plus incomplete dead code elimination
10748 can leave a %hi without a %lo. */
10750 as_warn_where (l
->fixp
->fx_file
, l
->fixp
->fx_line
,
10751 _("Unmatched %%hi reloc"));
10757 /* We may have combined relocations without symbols in the N32/N64 ABI.
10758 We have to prevent gas from dropping them. */
10761 mips_force_relocation (fixS
*fixp
)
10763 if (generic_force_reloc (fixp
))
10767 && S_GET_SEGMENT (fixp
->fx_addsy
) == bfd_abs_section_ptr
10768 && (fixp
->fx_r_type
== BFD_RELOC_MIPS_SUB
10769 || fixp
->fx_r_type
== BFD_RELOC_HI16_S
10770 || fixp
->fx_r_type
== BFD_RELOC_LO16
))
10776 /* This hook is called before a fix is simplified. We don't really
10777 decide whether to skip a fix here. Rather, we turn global symbols
10778 used as branch targets into local symbols, such that they undergo
10779 simplification. We can only do this if the symbol is defined and
10780 it is in the same section as the branch. If this doesn't hold, we
10781 emit a better error message than just saying the relocation is not
10782 valid for the selected object format.
10784 FIXP is the fix-up we're going to try to simplify, SEG is the
10785 segment in which the fix up occurs. The return value should be
10786 non-zero to indicate the fix-up is valid for further
10787 simplifications. */
10790 mips_validate_fix (struct fix
*fixP
, asection
*seg
)
10792 /* There's a lot of discussion on whether it should be possible to
10793 use R_MIPS_PC16 to represent branch relocations. The outcome
10794 seems to be that it can, but gas/bfd are very broken in creating
10795 RELA relocations for this, so for now we only accept branches to
10796 symbols in the same section. Anything else is of dubious value,
10797 since there's no guarantee that at link time the symbol would be
10798 in range. Even for branches to local symbols this is arguably
10799 wrong, since it we assume the symbol is not going to be
10800 overridden, which should be possible per ELF library semantics,
10801 but then, there isn't a dynamic relocation that could be used to
10802 this effect, and the target would likely be out of range as well.
10804 Unfortunately, it seems that there is too much code out there
10805 that relies on branches to symbols that are global to be resolved
10806 as if they were local, like the IRIX tools do, so we do it as
10807 well, but with a warning so that people are reminded to fix their
10808 code. If we ever get back to using R_MIPS_PC16 for branch
10809 targets, this entire block should go away (and probably the
10810 whole function). */
10812 if (fixP
->fx_r_type
== BFD_RELOC_16_PCREL_S2
10813 && ((OUTPUT_FLAVOR
== bfd_target_ecoff_flavour
10814 || OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
10815 || bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_16_PCREL_S2
) == NULL
)
10818 if (! S_IS_DEFINED (fixP
->fx_addsy
))
10820 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
10821 _("Cannot branch to undefined symbol."));
10822 /* Avoid any further errors about this fixup. */
10825 else if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
10827 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
10828 _("Cannot branch to symbol in another section."));
10831 else if (S_IS_EXTERNAL (fixP
->fx_addsy
))
10833 symbolS
*sym
= fixP
->fx_addsy
;
10835 if (mips_pic
== SVR4_PIC
)
10836 as_warn_where (fixP
->fx_file
, fixP
->fx_line
,
10837 _("Pretending global symbol used as branch target is local."));
10839 fixP
->fx_addsy
= symbol_create (S_GET_NAME (sym
),
10840 S_GET_SEGMENT (sym
),
10842 symbol_get_frag (sym
));
10843 copy_symbol_attributes (fixP
->fx_addsy
, sym
);
10844 S_CLEAR_EXTERNAL (fixP
->fx_addsy
);
10845 assert (symbol_resolved_p (sym
));
10846 symbol_mark_resolved (fixP
->fx_addsy
);
10853 /* Apply a fixup to the object file. */
10856 md_apply_fix3 (fixS
*fixP
, valueT
*valP
, segT seg ATTRIBUTE_UNUSED
)
10860 static int previous_fx_r_type
= 0;
10861 reloc_howto_type
*howto
;
10863 /* We ignore generic BFD relocations we don't know about. */
10864 howto
= bfd_reloc_type_lookup (stdoutput
, fixP
->fx_r_type
);
10868 assert (fixP
->fx_size
== 4
10869 || fixP
->fx_r_type
== BFD_RELOC_16
10870 || fixP
->fx_r_type
== BFD_RELOC_64
10871 || fixP
->fx_r_type
== BFD_RELOC_CTOR
10872 || fixP
->fx_r_type
== BFD_RELOC_MIPS_SUB
10873 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
10874 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
);
10876 buf
= (bfd_byte
*) (fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
);
10878 /* We are not done if this is a composite relocation to set up gp. */
10879 assert (! fixP
->fx_pcrel
);
10880 if (fixP
->fx_addsy
== NULL
10881 && !(fixP
->fx_r_type
== BFD_RELOC_MIPS_SUB
10882 || (fixP
->fx_r_type
== BFD_RELOC_64
10883 && (previous_fx_r_type
== BFD_RELOC_GPREL32
10884 || previous_fx_r_type
== BFD_RELOC_GPREL16
))
10885 || (previous_fx_r_type
== BFD_RELOC_MIPS_SUB
10886 && (fixP
->fx_r_type
== BFD_RELOC_HI16_S
10887 || fixP
->fx_r_type
== BFD_RELOC_LO16
))))
10889 previous_fx_r_type
= fixP
->fx_r_type
;
10891 switch (fixP
->fx_r_type
)
10893 case BFD_RELOC_MIPS_JMP
:
10894 case BFD_RELOC_MIPS_SHIFT5
:
10895 case BFD_RELOC_MIPS_SHIFT6
:
10896 case BFD_RELOC_MIPS_GOT_DISP
:
10897 case BFD_RELOC_MIPS_GOT_PAGE
:
10898 case BFD_RELOC_MIPS_GOT_OFST
:
10899 case BFD_RELOC_MIPS_SUB
:
10900 case BFD_RELOC_MIPS_INSERT_A
:
10901 case BFD_RELOC_MIPS_INSERT_B
:
10902 case BFD_RELOC_MIPS_DELETE
:
10903 case BFD_RELOC_MIPS_HIGHEST
:
10904 case BFD_RELOC_MIPS_HIGHER
:
10905 case BFD_RELOC_MIPS_SCN_DISP
:
10906 case BFD_RELOC_MIPS_REL16
:
10907 case BFD_RELOC_MIPS_RELGOT
:
10908 case BFD_RELOC_MIPS_JALR
:
10909 case BFD_RELOC_HI16
:
10910 case BFD_RELOC_HI16_S
:
10911 case BFD_RELOC_GPREL16
:
10912 case BFD_RELOC_MIPS_LITERAL
:
10913 case BFD_RELOC_MIPS_CALL16
:
10914 case BFD_RELOC_MIPS_GOT16
:
10915 case BFD_RELOC_GPREL32
:
10916 case BFD_RELOC_MIPS_GOT_HI16
:
10917 case BFD_RELOC_MIPS_GOT_LO16
:
10918 case BFD_RELOC_MIPS_CALL_HI16
:
10919 case BFD_RELOC_MIPS_CALL_LO16
:
10920 case BFD_RELOC_MIPS16_GPREL
:
10921 assert (! fixP
->fx_pcrel
);
10922 /* Nothing needed to do. The value comes from the reloc entry */
10925 case BFD_RELOC_MIPS16_JMP
:
10926 /* We currently always generate a reloc against a symbol, which
10927 means that we don't want an addend even if the symbol is
10933 /* This is handled like BFD_RELOC_32, but we output a sign
10934 extended value if we are only 32 bits. */
10937 if (8 <= sizeof (valueT
))
10938 md_number_to_chars (buf
, *valP
, 8);
10943 if ((*valP
& 0x80000000) != 0)
10947 md_number_to_chars ((char *)(buf
+ target_big_endian
? 4 : 0),
10949 md_number_to_chars ((char *)(buf
+ target_big_endian
? 0 : 4),
10955 case BFD_RELOC_RVA
:
10957 /* If we are deleting this reloc entry, we must fill in the
10958 value now. This can happen if we have a .word which is not
10959 resolved when it appears but is later defined. */
10961 md_number_to_chars (buf
, *valP
, 4);
10965 /* If we are deleting this reloc entry, we must fill in the
10967 assert (fixP
->fx_size
== 2);
10969 md_number_to_chars (buf
, *valP
, 2);
10972 case BFD_RELOC_LO16
:
10973 /* FIXME: Now that embedded-PIC is gone, some of this code/comment
10974 may be safe to remove, but if so it's not obvious. */
10975 /* When handling an embedded PIC switch statement, we can wind
10976 up deleting a LO16 reloc. See the 'o' case in mips_ip. */
10979 if (*valP
+ 0x8000 > 0xffff)
10980 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
10981 _("relocation overflow"));
10982 if (target_big_endian
)
10984 md_number_to_chars (buf
, *valP
, 2);
10988 case BFD_RELOC_16_PCREL_S2
:
10989 if ((*valP
& 0x3) != 0)
10990 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
10991 _("Branch to odd address (%lx)"), (long) *valP
);
10994 * We need to save the bits in the instruction since fixup_segment()
10995 * might be deleting the relocation entry (i.e., a branch within
10996 * the current segment).
10998 if (! fixP
->fx_done
)
11001 /* update old instruction data */
11002 if (target_big_endian
)
11003 insn
= (buf
[0] << 24) | (buf
[1] << 16) | (buf
[2] << 8) | buf
[3];
11005 insn
= (buf
[3] << 24) | (buf
[2] << 16) | (buf
[1] << 8) | buf
[0];
11007 if (*valP
+ 0x20000 <= 0x3ffff)
11009 insn
|= (*valP
>> 2) & 0xffff;
11010 md_number_to_chars (buf
, insn
, 4);
11012 else if (mips_pic
== NO_PIC
11014 && fixP
->fx_frag
->fr_address
>= text_section
->vma
11015 && (fixP
->fx_frag
->fr_address
11016 < text_section
->vma
+ bfd_get_section_size (text_section
))
11017 && ((insn
& 0xffff0000) == 0x10000000 /* beq $0,$0 */
11018 || (insn
& 0xffff0000) == 0x04010000 /* bgez $0 */
11019 || (insn
& 0xffff0000) == 0x04110000)) /* bgezal $0 */
11021 /* The branch offset is too large. If this is an
11022 unconditional branch, and we are not generating PIC code,
11023 we can convert it to an absolute jump instruction. */
11024 if ((insn
& 0xffff0000) == 0x04110000) /* bgezal $0 */
11025 insn
= 0x0c000000; /* jal */
11027 insn
= 0x08000000; /* j */
11028 fixP
->fx_r_type
= BFD_RELOC_MIPS_JMP
;
11030 fixP
->fx_addsy
= section_symbol (text_section
);
11031 *valP
+= md_pcrel_from (fixP
);
11032 md_number_to_chars (buf
, insn
, 4);
11036 /* If we got here, we have branch-relaxation disabled,
11037 and there's nothing we can do to fix this instruction
11038 without turning it into a longer sequence. */
11039 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
11040 _("Branch out of range"));
11044 case BFD_RELOC_VTABLE_INHERIT
:
11047 && !S_IS_DEFINED (fixP
->fx_addsy
)
11048 && !S_IS_WEAK (fixP
->fx_addsy
))
11049 S_SET_WEAK (fixP
->fx_addsy
);
11052 case BFD_RELOC_VTABLE_ENTRY
:
11060 /* Remember value for tc_gen_reloc. */
11061 fixP
->fx_addnumber
= *valP
;
11066 printInsn (unsigned long oc
)
11068 const struct mips_opcode
*p
;
11069 int treg
, sreg
, dreg
, shamt
;
11074 for (i
= 0; i
< NUMOPCODES
; ++i
)
11076 p
= &mips_opcodes
[i
];
11077 if (((oc
& p
->mask
) == p
->match
) && (p
->pinfo
!= INSN_MACRO
))
11079 printf ("%08lx %s\t", oc
, p
->name
);
11080 treg
= (oc
>> 16) & 0x1f;
11081 sreg
= (oc
>> 21) & 0x1f;
11082 dreg
= (oc
>> 11) & 0x1f;
11083 shamt
= (oc
>> 6) & 0x1f;
11085 for (args
= p
->args
;; ++args
)
11096 printf ("%c", *args
);
11100 assert (treg
== sreg
);
11101 printf ("$%d,$%d", treg
, sreg
);
11106 printf ("$%d", dreg
);
11111 printf ("$%d", treg
);
11115 printf ("0x%x", treg
);
11120 printf ("$%d", sreg
);
11124 printf ("0x%08lx", oc
& 0x1ffffff);
11131 printf ("%d", imm
);
11136 printf ("$%d", shamt
);
11147 printf (_("%08lx UNDEFINED\n"), oc
);
11158 name
= input_line_pointer
;
11159 c
= get_symbol_end ();
11160 p
= (symbolS
*) symbol_find_or_make (name
);
11161 *input_line_pointer
= c
;
11165 /* Align the current frag to a given power of two. The MIPS assembler
11166 also automatically adjusts any preceding label. */
11169 mips_align (int to
, int fill
, symbolS
*label
)
11171 mips_emit_delays (FALSE
);
11172 frag_align (to
, fill
, 0);
11173 record_alignment (now_seg
, to
);
11176 assert (S_GET_SEGMENT (label
) == now_seg
);
11177 symbol_set_frag (label
, frag_now
);
11178 S_SET_VALUE (label
, (valueT
) frag_now_fix ());
11182 /* Align to a given power of two. .align 0 turns off the automatic
11183 alignment used by the data creating pseudo-ops. */
11186 s_align (int x ATTRIBUTE_UNUSED
)
11189 register long temp_fill
;
11190 long max_alignment
= 15;
11194 o Note that the assembler pulls down any immediately preceding label
11195 to the aligned address.
11196 o It's not documented but auto alignment is reinstated by
11197 a .align pseudo instruction.
11198 o Note also that after auto alignment is turned off the mips assembler
11199 issues an error on attempt to assemble an improperly aligned data item.
11204 temp
= get_absolute_expression ();
11205 if (temp
> max_alignment
)
11206 as_bad (_("Alignment too large: %d. assumed."), temp
= max_alignment
);
11209 as_warn (_("Alignment negative: 0 assumed."));
11212 if (*input_line_pointer
== ',')
11214 ++input_line_pointer
;
11215 temp_fill
= get_absolute_expression ();
11222 mips_align (temp
, (int) temp_fill
,
11223 insn_labels
!= NULL
? insn_labels
->label
: NULL
);
11230 demand_empty_rest_of_line ();
11234 mips_flush_pending_output (void)
11236 mips_emit_delays (FALSE
);
11237 mips_clear_insn_labels ();
11241 s_change_sec (int sec
)
11246 /* The ELF backend needs to know that we are changing sections, so
11247 that .previous works correctly. We could do something like check
11248 for an obj_section_change_hook macro, but that might be confusing
11249 as it would not be appropriate to use it in the section changing
11250 functions in read.c, since obj-elf.c intercepts those. FIXME:
11251 This should be cleaner, somehow. */
11252 obj_elf_section_change_hook ();
11255 mips_emit_delays (FALSE
);
11265 subseg_set (bss_section
, (subsegT
) get_absolute_expression ());
11266 demand_empty_rest_of_line ();
11270 seg
= subseg_new (RDATA_SECTION_NAME
,
11271 (subsegT
) get_absolute_expression ());
11272 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
11274 bfd_set_section_flags (stdoutput
, seg
, (SEC_ALLOC
| SEC_LOAD
11275 | SEC_READONLY
| SEC_RELOC
11277 if (strcmp (TARGET_OS
, "elf") != 0)
11278 record_alignment (seg
, 4);
11280 demand_empty_rest_of_line ();
11284 seg
= subseg_new (".sdata", (subsegT
) get_absolute_expression ());
11285 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
11287 bfd_set_section_flags (stdoutput
, seg
,
11288 SEC_ALLOC
| SEC_LOAD
| SEC_RELOC
| SEC_DATA
);
11289 if (strcmp (TARGET_OS
, "elf") != 0)
11290 record_alignment (seg
, 4);
11292 demand_empty_rest_of_line ();
11300 s_change_section (int ignore ATTRIBUTE_UNUSED
)
11303 char *section_name
;
11308 int section_entry_size
;
11309 int section_alignment
;
11311 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
11314 section_name
= input_line_pointer
;
11315 c
= get_symbol_end ();
11317 next_c
= *(input_line_pointer
+ 1);
11319 /* Do we have .section Name<,"flags">? */
11320 if (c
!= ',' || (c
== ',' && next_c
== '"'))
11322 /* just after name is now '\0'. */
11323 *input_line_pointer
= c
;
11324 input_line_pointer
= section_name
;
11325 obj_elf_section (ignore
);
11328 input_line_pointer
++;
11330 /* Do we have .section Name<,type><,flag><,entry_size><,alignment> */
11332 section_type
= get_absolute_expression ();
11335 if (*input_line_pointer
++ == ',')
11336 section_flag
= get_absolute_expression ();
11339 if (*input_line_pointer
++ == ',')
11340 section_entry_size
= get_absolute_expression ();
11342 section_entry_size
= 0;
11343 if (*input_line_pointer
++ == ',')
11344 section_alignment
= get_absolute_expression ();
11346 section_alignment
= 0;
11348 section_name
= xstrdup (section_name
);
11350 /* When using the generic form of .section (as implemented by obj-elf.c),
11351 there's no way to set the section type to SHT_MIPS_DWARF. Users have
11352 traditionally had to fall back on the more common @progbits instead.
11354 There's nothing really harmful in this, since bfd will correct
11355 SHT_PROGBITS to SHT_MIPS_DWARF before writing out the file. But it
11356 means that, for backwards compatibiltiy, the special_section entries
11357 for dwarf sections must use SHT_PROGBITS rather than SHT_MIPS_DWARF.
11359 Even so, we shouldn't force users of the MIPS .section syntax to
11360 incorrectly label the sections as SHT_PROGBITS. The best compromise
11361 seems to be to map SHT_MIPS_DWARF to SHT_PROGBITS before calling the
11362 generic type-checking code. */
11363 if (section_type
== SHT_MIPS_DWARF
)
11364 section_type
= SHT_PROGBITS
;
11366 obj_elf_change_section (section_name
, section_type
, section_flag
,
11367 section_entry_size
, 0, 0, 0);
11369 if (now_seg
->name
!= section_name
)
11370 free (section_name
);
11371 #endif /* OBJ_ELF */
11375 mips_enable_auto_align (void)
11381 s_cons (int log_size
)
11385 label
= insn_labels
!= NULL
? insn_labels
->label
: NULL
;
11386 mips_emit_delays (FALSE
);
11387 if (log_size
> 0 && auto_align
)
11388 mips_align (log_size
, 0, label
);
11389 mips_clear_insn_labels ();
11390 cons (1 << log_size
);
11394 s_float_cons (int type
)
11398 label
= insn_labels
!= NULL
? insn_labels
->label
: NULL
;
11400 mips_emit_delays (FALSE
);
11405 mips_align (3, 0, label
);
11407 mips_align (2, 0, label
);
11410 mips_clear_insn_labels ();
11415 /* Handle .globl. We need to override it because on Irix 5 you are
11418 where foo is an undefined symbol, to mean that foo should be
11419 considered to be the address of a function. */
11422 s_mips_globl (int x ATTRIBUTE_UNUSED
)
11429 name
= input_line_pointer
;
11430 c
= get_symbol_end ();
11431 symbolP
= symbol_find_or_make (name
);
11432 *input_line_pointer
= c
;
11433 SKIP_WHITESPACE ();
11435 /* On Irix 5, every global symbol that is not explicitly labelled as
11436 being a function is apparently labelled as being an object. */
11439 if (! is_end_of_line
[(unsigned char) *input_line_pointer
])
11444 secname
= input_line_pointer
;
11445 c
= get_symbol_end ();
11446 sec
= bfd_get_section_by_name (stdoutput
, secname
);
11448 as_bad (_("%s: no such section"), secname
);
11449 *input_line_pointer
= c
;
11451 if (sec
!= NULL
&& (sec
->flags
& SEC_CODE
) != 0)
11452 flag
= BSF_FUNCTION
;
11455 symbol_get_bfdsym (symbolP
)->flags
|= flag
;
11457 S_SET_EXTERNAL (symbolP
);
11458 demand_empty_rest_of_line ();
11462 s_option (int x ATTRIBUTE_UNUSED
)
11467 opt
= input_line_pointer
;
11468 c
= get_symbol_end ();
11472 /* FIXME: What does this mean? */
11474 else if (strncmp (opt
, "pic", 3) == 0)
11478 i
= atoi (opt
+ 3);
11483 mips_pic
= SVR4_PIC
;
11484 mips_abicalls
= TRUE
;
11487 as_bad (_(".option pic%d not supported"), i
);
11489 if (mips_pic
== SVR4_PIC
)
11491 if (g_switch_seen
&& g_switch_value
!= 0)
11492 as_warn (_("-G may not be used with SVR4 PIC code"));
11493 g_switch_value
= 0;
11494 bfd_set_gp_size (stdoutput
, 0);
11498 as_warn (_("Unrecognized option \"%s\""), opt
);
11500 *input_line_pointer
= c
;
11501 demand_empty_rest_of_line ();
11504 /* This structure is used to hold a stack of .set values. */
11506 struct mips_option_stack
11508 struct mips_option_stack
*next
;
11509 struct mips_set_options options
;
11512 static struct mips_option_stack
*mips_opts_stack
;
11514 /* Handle the .set pseudo-op. */
11517 s_mipsset (int x ATTRIBUTE_UNUSED
)
11519 char *name
= input_line_pointer
, ch
;
11521 while (!is_end_of_line
[(unsigned char) *input_line_pointer
])
11522 ++input_line_pointer
;
11523 ch
= *input_line_pointer
;
11524 *input_line_pointer
= '\0';
11526 if (strcmp (name
, "reorder") == 0)
11528 if (mips_opts
.noreorder
&& prev_nop_frag
!= NULL
)
11530 /* If we still have pending nops, we can discard them. The
11531 usual nop handling will insert any that are still
11533 prev_nop_frag
->fr_fix
-= (prev_nop_frag_holds
11534 * (mips_opts
.mips16
? 2 : 4));
11535 prev_nop_frag
= NULL
;
11537 mips_opts
.noreorder
= 0;
11539 else if (strcmp (name
, "noreorder") == 0)
11541 mips_emit_delays (TRUE
);
11542 mips_opts
.noreorder
= 1;
11543 mips_any_noreorder
= 1;
11545 else if (strcmp (name
, "at") == 0)
11547 mips_opts
.noat
= 0;
11549 else if (strcmp (name
, "noat") == 0)
11551 mips_opts
.noat
= 1;
11553 else if (strcmp (name
, "macro") == 0)
11555 mips_opts
.warn_about_macros
= 0;
11557 else if (strcmp (name
, "nomacro") == 0)
11559 if (mips_opts
.noreorder
== 0)
11560 as_bad (_("`noreorder' must be set before `nomacro'"));
11561 mips_opts
.warn_about_macros
= 1;
11563 else if (strcmp (name
, "move") == 0 || strcmp (name
, "novolatile") == 0)
11565 mips_opts
.nomove
= 0;
11567 else if (strcmp (name
, "nomove") == 0 || strcmp (name
, "volatile") == 0)
11569 mips_opts
.nomove
= 1;
11571 else if (strcmp (name
, "bopt") == 0)
11573 mips_opts
.nobopt
= 0;
11575 else if (strcmp (name
, "nobopt") == 0)
11577 mips_opts
.nobopt
= 1;
11579 else if (strcmp (name
, "mips16") == 0
11580 || strcmp (name
, "MIPS-16") == 0)
11581 mips_opts
.mips16
= 1;
11582 else if (strcmp (name
, "nomips16") == 0
11583 || strcmp (name
, "noMIPS-16") == 0)
11584 mips_opts
.mips16
= 0;
11585 else if (strcmp (name
, "mips3d") == 0)
11586 mips_opts
.ase_mips3d
= 1;
11587 else if (strcmp (name
, "nomips3d") == 0)
11588 mips_opts
.ase_mips3d
= 0;
11589 else if (strcmp (name
, "mdmx") == 0)
11590 mips_opts
.ase_mdmx
= 1;
11591 else if (strcmp (name
, "nomdmx") == 0)
11592 mips_opts
.ase_mdmx
= 0;
11593 else if (strncmp (name
, "mips", 4) == 0 || strncmp (name
, "arch=", 5) == 0)
11597 /* Permit the user to change the ISA and architecture on the fly.
11598 Needless to say, misuse can cause serious problems. */
11599 if (strcmp (name
, "mips0") == 0 || strcmp (name
, "arch=default") == 0)
11602 mips_opts
.isa
= file_mips_isa
;
11603 mips_opts
.arch
= file_mips_arch
;
11605 else if (strncmp (name
, "arch=", 5) == 0)
11607 const struct mips_cpu_info
*p
;
11609 p
= mips_parse_cpu("internal use", name
+ 5);
11611 as_bad (_("unknown architecture %s"), name
+ 5);
11614 mips_opts
.arch
= p
->cpu
;
11615 mips_opts
.isa
= p
->isa
;
11618 else if (strncmp (name
, "mips", 4) == 0)
11620 const struct mips_cpu_info
*p
;
11622 p
= mips_parse_cpu("internal use", name
);
11624 as_bad (_("unknown ISA level %s"), name
+ 4);
11627 mips_opts
.arch
= p
->cpu
;
11628 mips_opts
.isa
= p
->isa
;
11632 as_bad (_("unknown ISA or architecture %s"), name
);
11634 switch (mips_opts
.isa
)
11642 mips_opts
.gp32
= 1;
11643 mips_opts
.fp32
= 1;
11650 mips_opts
.gp32
= 0;
11651 mips_opts
.fp32
= 0;
11654 as_bad (_("unknown ISA level %s"), name
+ 4);
11659 mips_opts
.gp32
= file_mips_gp32
;
11660 mips_opts
.fp32
= file_mips_fp32
;
11663 else if (strcmp (name
, "autoextend") == 0)
11664 mips_opts
.noautoextend
= 0;
11665 else if (strcmp (name
, "noautoextend") == 0)
11666 mips_opts
.noautoextend
= 1;
11667 else if (strcmp (name
, "push") == 0)
11669 struct mips_option_stack
*s
;
11671 s
= (struct mips_option_stack
*) xmalloc (sizeof *s
);
11672 s
->next
= mips_opts_stack
;
11673 s
->options
= mips_opts
;
11674 mips_opts_stack
= s
;
11676 else if (strcmp (name
, "pop") == 0)
11678 struct mips_option_stack
*s
;
11680 s
= mips_opts_stack
;
11682 as_bad (_(".set pop with no .set push"));
11685 /* If we're changing the reorder mode we need to handle
11686 delay slots correctly. */
11687 if (s
->options
.noreorder
&& ! mips_opts
.noreorder
)
11688 mips_emit_delays (TRUE
);
11689 else if (! s
->options
.noreorder
&& mips_opts
.noreorder
)
11691 if (prev_nop_frag
!= NULL
)
11693 prev_nop_frag
->fr_fix
-= (prev_nop_frag_holds
11694 * (mips_opts
.mips16
? 2 : 4));
11695 prev_nop_frag
= NULL
;
11699 mips_opts
= s
->options
;
11700 mips_opts_stack
= s
->next
;
11706 as_warn (_("Tried to set unrecognized symbol: %s\n"), name
);
11708 *input_line_pointer
= ch
;
11709 demand_empty_rest_of_line ();
11712 /* Handle the .abicalls pseudo-op. I believe this is equivalent to
11713 .option pic2. It means to generate SVR4 PIC calls. */
11716 s_abicalls (int ignore ATTRIBUTE_UNUSED
)
11718 mips_pic
= SVR4_PIC
;
11719 mips_abicalls
= TRUE
;
11721 if (g_switch_seen
&& g_switch_value
!= 0)
11722 as_warn (_("-G may not be used with SVR4 PIC code"));
11723 g_switch_value
= 0;
11725 bfd_set_gp_size (stdoutput
, 0);
11726 demand_empty_rest_of_line ();
11729 /* Handle the .cpload pseudo-op. This is used when generating SVR4
11730 PIC code. It sets the $gp register for the function based on the
11731 function address, which is in the register named in the argument.
11732 This uses a relocation against _gp_disp, which is handled specially
11733 by the linker. The result is:
11734 lui $gp,%hi(_gp_disp)
11735 addiu $gp,$gp,%lo(_gp_disp)
11736 addu $gp,$gp,.cpload argument
11737 The .cpload argument is normally $25 == $t9. */
11740 s_cpload (int ignore ATTRIBUTE_UNUSED
)
11744 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
11745 .cpload is ignored. */
11746 if (mips_pic
!= SVR4_PIC
|| HAVE_NEWABI
)
11752 /* .cpload should be in a .set noreorder section. */
11753 if (mips_opts
.noreorder
== 0)
11754 as_warn (_(".cpload not in noreorder section"));
11756 ex
.X_op
= O_symbol
;
11757 ex
.X_add_symbol
= symbol_find_or_make ("_gp_disp");
11758 ex
.X_op_symbol
= NULL
;
11759 ex
.X_add_number
= 0;
11761 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
11762 symbol_get_bfdsym (ex
.X_add_symbol
)->flags
|= BSF_OBJECT
;
11765 macro_build_lui (&ex
, mips_gp_register
);
11766 macro_build (&ex
, "addiu", "t,r,j", mips_gp_register
,
11767 mips_gp_register
, BFD_RELOC_LO16
);
11768 macro_build (NULL
, "addu", "d,v,t", mips_gp_register
,
11769 mips_gp_register
, tc_get_register (0));
11772 demand_empty_rest_of_line ();
11775 /* Handle the .cpsetup pseudo-op defined for NewABI PIC code. The syntax is:
11776 .cpsetup $reg1, offset|$reg2, label
11778 If offset is given, this results in:
11779 sd $gp, offset($sp)
11780 lui $gp, %hi(%neg(%gp_rel(label)))
11781 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
11782 daddu $gp, $gp, $reg1
11784 If $reg2 is given, this results in:
11785 daddu $reg2, $gp, $0
11786 lui $gp, %hi(%neg(%gp_rel(label)))
11787 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
11788 daddu $gp, $gp, $reg1
11789 $reg1 is normally $25 == $t9. */
11791 s_cpsetup (int ignore ATTRIBUTE_UNUSED
)
11793 expressionS ex_off
;
11794 expressionS ex_sym
;
11798 /* If we are not generating SVR4 PIC code, .cpsetup is ignored.
11799 We also need NewABI support. */
11800 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
11806 reg1
= tc_get_register (0);
11807 SKIP_WHITESPACE ();
11808 if (*input_line_pointer
!= ',')
11810 as_bad (_("missing argument separator ',' for .cpsetup"));
11814 ++input_line_pointer
;
11815 SKIP_WHITESPACE ();
11816 if (*input_line_pointer
== '$')
11818 mips_cpreturn_register
= tc_get_register (0);
11819 mips_cpreturn_offset
= -1;
11823 mips_cpreturn_offset
= get_absolute_expression ();
11824 mips_cpreturn_register
= -1;
11826 SKIP_WHITESPACE ();
11827 if (*input_line_pointer
!= ',')
11829 as_bad (_("missing argument separator ',' for .cpsetup"));
11833 ++input_line_pointer
;
11834 SKIP_WHITESPACE ();
11835 expression (&ex_sym
);
11838 if (mips_cpreturn_register
== -1)
11840 ex_off
.X_op
= O_constant
;
11841 ex_off
.X_add_symbol
= NULL
;
11842 ex_off
.X_op_symbol
= NULL
;
11843 ex_off
.X_add_number
= mips_cpreturn_offset
;
11845 macro_build (&ex_off
, "sd", "t,o(b)", mips_gp_register
,
11846 BFD_RELOC_LO16
, SP
);
11849 macro_build (NULL
, "daddu", "d,v,t", mips_cpreturn_register
,
11850 mips_gp_register
, 0);
11852 /* Ensure there's room for the next two instructions, so that `f'
11853 doesn't end up with an address in the wrong frag. */
11856 macro_build (&ex_sym
, "lui", "t,u", mips_gp_register
, BFD_RELOC_GPREL16
);
11857 fix_new (frag_now
, f
- frag_now
->fr_literal
,
11858 8, NULL
, 0, 0, BFD_RELOC_MIPS_SUB
);
11859 fix_new (frag_now
, f
- frag_now
->fr_literal
,
11860 4, NULL
, 0, 0, BFD_RELOC_HI16_S
);
11863 macro_build (&ex_sym
, "addiu", "t,r,j", mips_gp_register
,
11864 mips_gp_register
, BFD_RELOC_GPREL16
);
11865 fix_new (frag_now
, f
- frag_now
->fr_literal
,
11866 8, NULL
, 0, 0, BFD_RELOC_MIPS_SUB
);
11867 fix_new (frag_now
, f
- frag_now
->fr_literal
,
11868 4, NULL
, 0, 0, BFD_RELOC_LO16
);
11870 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", mips_gp_register
,
11871 mips_gp_register
, reg1
);
11874 demand_empty_rest_of_line ();
11878 s_cplocal (int ignore ATTRIBUTE_UNUSED
)
11880 /* If we are not generating SVR4 PIC code, or if this is not NewABI code,
11881 .cplocal is ignored. */
11882 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
11888 mips_gp_register
= tc_get_register (0);
11889 demand_empty_rest_of_line ();
11892 /* Handle the .cprestore pseudo-op. This stores $gp into a given
11893 offset from $sp. The offset is remembered, and after making a PIC
11894 call $gp is restored from that location. */
11897 s_cprestore (int ignore ATTRIBUTE_UNUSED
)
11901 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
11902 .cprestore is ignored. */
11903 if (mips_pic
!= SVR4_PIC
|| HAVE_NEWABI
)
11909 mips_cprestore_offset
= get_absolute_expression ();
11910 mips_cprestore_valid
= 1;
11912 ex
.X_op
= O_constant
;
11913 ex
.X_add_symbol
= NULL
;
11914 ex
.X_op_symbol
= NULL
;
11915 ex
.X_add_number
= mips_cprestore_offset
;
11918 macro_build_ldst_constoffset (&ex
, ADDRESS_STORE_INSN
, mips_gp_register
,
11919 SP
, HAVE_64BIT_ADDRESSES
);
11922 demand_empty_rest_of_line ();
11925 /* Handle the .cpreturn pseudo-op defined for NewABI PIC code. If an offset
11926 was given in the preceding .cpsetup, it results in:
11927 ld $gp, offset($sp)
11929 If a register $reg2 was given there, it results in:
11930 daddu $gp, $reg2, $0
11933 s_cpreturn (int ignore ATTRIBUTE_UNUSED
)
11937 /* If we are not generating SVR4 PIC code, .cpreturn is ignored.
11938 We also need NewABI support. */
11939 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
11946 if (mips_cpreturn_register
== -1)
11948 ex
.X_op
= O_constant
;
11949 ex
.X_add_symbol
= NULL
;
11950 ex
.X_op_symbol
= NULL
;
11951 ex
.X_add_number
= mips_cpreturn_offset
;
11953 macro_build (&ex
, "ld", "t,o(b)", mips_gp_register
, BFD_RELOC_LO16
, SP
);
11956 macro_build (NULL
, "daddu", "d,v,t", mips_gp_register
,
11957 mips_cpreturn_register
, 0);
11960 demand_empty_rest_of_line ();
11963 /* Handle the .gpvalue pseudo-op. This is used when generating NewABI PIC
11964 code. It sets the offset to use in gp_rel relocations. */
11967 s_gpvalue (int ignore ATTRIBUTE_UNUSED
)
11969 /* If we are not generating SVR4 PIC code, .gpvalue is ignored.
11970 We also need NewABI support. */
11971 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
11977 mips_gprel_offset
= get_absolute_expression ();
11979 demand_empty_rest_of_line ();
11982 /* Handle the .gpword pseudo-op. This is used when generating PIC
11983 code. It generates a 32 bit GP relative reloc. */
11986 s_gpword (int ignore ATTRIBUTE_UNUSED
)
11992 /* When not generating PIC code, this is treated as .word. */
11993 if (mips_pic
!= SVR4_PIC
)
11999 label
= insn_labels
!= NULL
? insn_labels
->label
: NULL
;
12000 mips_emit_delays (TRUE
);
12002 mips_align (2, 0, label
);
12003 mips_clear_insn_labels ();
12007 if (ex
.X_op
!= O_symbol
|| ex
.X_add_number
!= 0)
12009 as_bad (_("Unsupported use of .gpword"));
12010 ignore_rest_of_line ();
12014 md_number_to_chars (p
, 0, 4);
12015 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 4, &ex
, FALSE
,
12016 BFD_RELOC_GPREL32
);
12018 demand_empty_rest_of_line ();
12022 s_gpdword (int ignore ATTRIBUTE_UNUSED
)
12028 /* When not generating PIC code, this is treated as .dword. */
12029 if (mips_pic
!= SVR4_PIC
)
12035 label
= insn_labels
!= NULL
? insn_labels
->label
: NULL
;
12036 mips_emit_delays (TRUE
);
12038 mips_align (3, 0, label
);
12039 mips_clear_insn_labels ();
12043 if (ex
.X_op
!= O_symbol
|| ex
.X_add_number
!= 0)
12045 as_bad (_("Unsupported use of .gpdword"));
12046 ignore_rest_of_line ();
12050 md_number_to_chars (p
, 0, 8);
12051 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 4, &ex
, FALSE
,
12052 BFD_RELOC_GPREL32
);
12054 /* GPREL32 composed with 64 gives a 64-bit GP offset. */
12055 ex
.X_op
= O_absent
;
12056 ex
.X_add_symbol
= 0;
12057 ex
.X_add_number
= 0;
12058 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 8, &ex
, FALSE
,
12061 demand_empty_rest_of_line ();
12064 /* Handle the .cpadd pseudo-op. This is used when dealing with switch
12065 tables in SVR4 PIC code. */
12068 s_cpadd (int ignore ATTRIBUTE_UNUSED
)
12072 /* This is ignored when not generating SVR4 PIC code. */
12073 if (mips_pic
!= SVR4_PIC
)
12079 /* Add $gp to the register named as an argument. */
12081 reg
= tc_get_register (0);
12082 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", reg
, reg
, mips_gp_register
);
12085 demand_empty_rest_of_line ();
12088 /* Handle the .insn pseudo-op. This marks instruction labels in
12089 mips16 mode. This permits the linker to handle them specially,
12090 such as generating jalx instructions when needed. We also make
12091 them odd for the duration of the assembly, in order to generate the
12092 right sort of code. We will make them even in the adjust_symtab
12093 routine, while leaving them marked. This is convenient for the
12094 debugger and the disassembler. The linker knows to make them odd
12098 s_insn (int ignore ATTRIBUTE_UNUSED
)
12100 mips16_mark_labels ();
12102 demand_empty_rest_of_line ();
12105 /* Handle a .stabn directive. We need these in order to mark a label
12106 as being a mips16 text label correctly. Sometimes the compiler
12107 will emit a label, followed by a .stabn, and then switch sections.
12108 If the label and .stabn are in mips16 mode, then the label is
12109 really a mips16 text label. */
12112 s_mips_stab (int type
)
12115 mips16_mark_labels ();
12120 /* Handle the .weakext pseudo-op as defined in Kane and Heinrich.
12124 s_mips_weakext (int ignore ATTRIBUTE_UNUSED
)
12131 name
= input_line_pointer
;
12132 c
= get_symbol_end ();
12133 symbolP
= symbol_find_or_make (name
);
12134 S_SET_WEAK (symbolP
);
12135 *input_line_pointer
= c
;
12137 SKIP_WHITESPACE ();
12139 if (! is_end_of_line
[(unsigned char) *input_line_pointer
])
12141 if (S_IS_DEFINED (symbolP
))
12143 as_bad ("ignoring attempt to redefine symbol %s",
12144 S_GET_NAME (symbolP
));
12145 ignore_rest_of_line ();
12149 if (*input_line_pointer
== ',')
12151 ++input_line_pointer
;
12152 SKIP_WHITESPACE ();
12156 if (exp
.X_op
!= O_symbol
)
12158 as_bad ("bad .weakext directive");
12159 ignore_rest_of_line ();
12162 symbol_set_value_expression (symbolP
, &exp
);
12165 demand_empty_rest_of_line ();
12168 /* Parse a register string into a number. Called from the ECOFF code
12169 to parse .frame. The argument is non-zero if this is the frame
12170 register, so that we can record it in mips_frame_reg. */
12173 tc_get_register (int frame
)
12177 SKIP_WHITESPACE ();
12178 if (*input_line_pointer
++ != '$')
12180 as_warn (_("expected `$'"));
12183 else if (ISDIGIT (*input_line_pointer
))
12185 reg
= get_absolute_expression ();
12186 if (reg
< 0 || reg
>= 32)
12188 as_warn (_("Bad register number"));
12194 if (strncmp (input_line_pointer
, "ra", 2) == 0)
12197 input_line_pointer
+= 2;
12199 else if (strncmp (input_line_pointer
, "fp", 2) == 0)
12202 input_line_pointer
+= 2;
12204 else if (strncmp (input_line_pointer
, "sp", 2) == 0)
12207 input_line_pointer
+= 2;
12209 else if (strncmp (input_line_pointer
, "gp", 2) == 0)
12212 input_line_pointer
+= 2;
12214 else if (strncmp (input_line_pointer
, "at", 2) == 0)
12217 input_line_pointer
+= 2;
12219 else if (strncmp (input_line_pointer
, "kt0", 3) == 0)
12222 input_line_pointer
+= 3;
12224 else if (strncmp (input_line_pointer
, "kt1", 3) == 0)
12227 input_line_pointer
+= 3;
12229 else if (strncmp (input_line_pointer
, "zero", 4) == 0)
12232 input_line_pointer
+= 4;
12236 as_warn (_("Unrecognized register name"));
12238 while (ISALNUM(*input_line_pointer
))
12239 input_line_pointer
++;
12244 mips_frame_reg
= reg
!= 0 ? reg
: SP
;
12245 mips_frame_reg_valid
= 1;
12246 mips_cprestore_valid
= 0;
12252 md_section_align (asection
*seg
, valueT addr
)
12254 int align
= bfd_get_section_alignment (stdoutput
, seg
);
12257 /* We don't need to align ELF sections to the full alignment.
12258 However, Irix 5 may prefer that we align them at least to a 16
12259 byte boundary. We don't bother to align the sections if we are
12260 targeted for an embedded system. */
12261 if (strcmp (TARGET_OS
, "elf") == 0)
12267 return ((addr
+ (1 << align
) - 1) & (-1 << align
));
12270 /* Utility routine, called from above as well. If called while the
12271 input file is still being read, it's only an approximation. (For
12272 example, a symbol may later become defined which appeared to be
12273 undefined earlier.) */
12276 nopic_need_relax (symbolS
*sym
, int before_relaxing
)
12281 if (g_switch_value
> 0)
12283 const char *symname
;
12286 /* Find out whether this symbol can be referenced off the $gp
12287 register. It can be if it is smaller than the -G size or if
12288 it is in the .sdata or .sbss section. Certain symbols can
12289 not be referenced off the $gp, although it appears as though
12291 symname
= S_GET_NAME (sym
);
12292 if (symname
!= (const char *) NULL
12293 && (strcmp (symname
, "eprol") == 0
12294 || strcmp (symname
, "etext") == 0
12295 || strcmp (symname
, "_gp") == 0
12296 || strcmp (symname
, "edata") == 0
12297 || strcmp (symname
, "_fbss") == 0
12298 || strcmp (symname
, "_fdata") == 0
12299 || strcmp (symname
, "_ftext") == 0
12300 || strcmp (symname
, "end") == 0
12301 || strcmp (symname
, "_gp_disp") == 0))
12303 else if ((! S_IS_DEFINED (sym
) || S_IS_COMMON (sym
))
12305 #ifndef NO_ECOFF_DEBUGGING
12306 || (symbol_get_obj (sym
)->ecoff_extern_size
!= 0
12307 && (symbol_get_obj (sym
)->ecoff_extern_size
12308 <= g_switch_value
))
12310 /* We must defer this decision until after the whole
12311 file has been read, since there might be a .extern
12312 after the first use of this symbol. */
12313 || (before_relaxing
12314 #ifndef NO_ECOFF_DEBUGGING
12315 && symbol_get_obj (sym
)->ecoff_extern_size
== 0
12317 && S_GET_VALUE (sym
) == 0)
12318 || (S_GET_VALUE (sym
) != 0
12319 && S_GET_VALUE (sym
) <= g_switch_value
)))
12323 const char *segname
;
12325 segname
= segment_name (S_GET_SEGMENT (sym
));
12326 assert (strcmp (segname
, ".lit8") != 0
12327 && strcmp (segname
, ".lit4") != 0);
12328 change
= (strcmp (segname
, ".sdata") != 0
12329 && strcmp (segname
, ".sbss") != 0
12330 && strncmp (segname
, ".sdata.", 7) != 0
12331 && strncmp (segname
, ".gnu.linkonce.s.", 16) != 0);
12336 /* We are not optimizing for the $gp register. */
12341 /* Return true if the given symbol should be considered local for SVR4 PIC. */
12344 pic_need_relax (symbolS
*sym
, asection
*segtype
)
12347 bfd_boolean linkonce
;
12349 /* Handle the case of a symbol equated to another symbol. */
12350 while (symbol_equated_reloc_p (sym
))
12354 /* It's possible to get a loop here in a badly written
12356 n
= symbol_get_value_expression (sym
)->X_add_symbol
;
12362 symsec
= S_GET_SEGMENT (sym
);
12364 /* duplicate the test for LINK_ONCE sections as in adjust_reloc_syms */
12366 if (symsec
!= segtype
&& ! S_IS_LOCAL (sym
))
12368 if ((bfd_get_section_flags (stdoutput
, symsec
) & SEC_LINK_ONCE
)
12372 /* The GNU toolchain uses an extension for ELF: a section
12373 beginning with the magic string .gnu.linkonce is a linkonce
12375 if (strncmp (segment_name (symsec
), ".gnu.linkonce",
12376 sizeof ".gnu.linkonce" - 1) == 0)
12380 /* This must duplicate the test in adjust_reloc_syms. */
12381 return (symsec
!= &bfd_und_section
12382 && symsec
!= &bfd_abs_section
12383 && ! bfd_is_com_section (symsec
)
12386 /* A global or weak symbol is treated as external. */
12387 && (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
12388 || (! S_IS_WEAK (sym
) && ! S_IS_EXTERNAL (sym
)))
12394 /* Given a mips16 variant frag FRAGP, return non-zero if it needs an
12395 extended opcode. SEC is the section the frag is in. */
12398 mips16_extended_frag (fragS
*fragp
, asection
*sec
, long stretch
)
12401 register const struct mips16_immed_operand
*op
;
12403 int mintiny
, maxtiny
;
12407 if (RELAX_MIPS16_USER_SMALL (fragp
->fr_subtype
))
12409 if (RELAX_MIPS16_USER_EXT (fragp
->fr_subtype
))
12412 type
= RELAX_MIPS16_TYPE (fragp
->fr_subtype
);
12413 op
= mips16_immed_operands
;
12414 while (op
->type
!= type
)
12417 assert (op
< mips16_immed_operands
+ MIPS16_NUM_IMMED
);
12422 if (type
== '<' || type
== '>' || type
== '[' || type
== ']')
12425 maxtiny
= 1 << op
->nbits
;
12430 maxtiny
= (1 << op
->nbits
) - 1;
12435 mintiny
= - (1 << (op
->nbits
- 1));
12436 maxtiny
= (1 << (op
->nbits
- 1)) - 1;
12439 sym_frag
= symbol_get_frag (fragp
->fr_symbol
);
12440 val
= S_GET_VALUE (fragp
->fr_symbol
);
12441 symsec
= S_GET_SEGMENT (fragp
->fr_symbol
);
12447 /* We won't have the section when we are called from
12448 mips_relax_frag. However, we will always have been called
12449 from md_estimate_size_before_relax first. If this is a
12450 branch to a different section, we mark it as such. If SEC is
12451 NULL, and the frag is not marked, then it must be a branch to
12452 the same section. */
12455 if (RELAX_MIPS16_LONG_BRANCH (fragp
->fr_subtype
))
12460 /* Must have been called from md_estimate_size_before_relax. */
12463 fragp
->fr_subtype
=
12464 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
12466 /* FIXME: We should support this, and let the linker
12467 catch branches and loads that are out of range. */
12468 as_bad_where (fragp
->fr_file
, fragp
->fr_line
,
12469 _("unsupported PC relative reference to different section"));
12473 if (fragp
!= sym_frag
&& sym_frag
->fr_address
== 0)
12474 /* Assume non-extended on the first relaxation pass.
12475 The address we have calculated will be bogus if this is
12476 a forward branch to another frag, as the forward frag
12477 will have fr_address == 0. */
12481 /* In this case, we know for sure that the symbol fragment is in
12482 the same section. If the relax_marker of the symbol fragment
12483 differs from the relax_marker of this fragment, we have not
12484 yet adjusted the symbol fragment fr_address. We want to add
12485 in STRETCH in order to get a better estimate of the address.
12486 This particularly matters because of the shift bits. */
12488 && sym_frag
->relax_marker
!= fragp
->relax_marker
)
12492 /* Adjust stretch for any alignment frag. Note that if have
12493 been expanding the earlier code, the symbol may be
12494 defined in what appears to be an earlier frag. FIXME:
12495 This doesn't handle the fr_subtype field, which specifies
12496 a maximum number of bytes to skip when doing an
12498 for (f
= fragp
; f
!= NULL
&& f
!= sym_frag
; f
= f
->fr_next
)
12500 if (f
->fr_type
== rs_align
|| f
->fr_type
== rs_align_code
)
12503 stretch
= - ((- stretch
)
12504 & ~ ((1 << (int) f
->fr_offset
) - 1));
12506 stretch
&= ~ ((1 << (int) f
->fr_offset
) - 1);
12515 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
12517 /* The base address rules are complicated. The base address of
12518 a branch is the following instruction. The base address of a
12519 PC relative load or add is the instruction itself, but if it
12520 is in a delay slot (in which case it can not be extended) use
12521 the address of the instruction whose delay slot it is in. */
12522 if (type
== 'p' || type
== 'q')
12526 /* If we are currently assuming that this frag should be
12527 extended, then, the current address is two bytes
12529 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
12532 /* Ignore the low bit in the target, since it will be set
12533 for a text label. */
12534 if ((val
& 1) != 0)
12537 else if (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
))
12539 else if (RELAX_MIPS16_DSLOT (fragp
->fr_subtype
))
12542 val
-= addr
& ~ ((1 << op
->shift
) - 1);
12544 /* Branch offsets have an implicit 0 in the lowest bit. */
12545 if (type
== 'p' || type
== 'q')
12548 /* If any of the shifted bits are set, we must use an extended
12549 opcode. If the address depends on the size of this
12550 instruction, this can lead to a loop, so we arrange to always
12551 use an extended opcode. We only check this when we are in
12552 the main relaxation loop, when SEC is NULL. */
12553 if ((val
& ((1 << op
->shift
) - 1)) != 0 && sec
== NULL
)
12555 fragp
->fr_subtype
=
12556 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
12560 /* If we are about to mark a frag as extended because the value
12561 is precisely maxtiny + 1, then there is a chance of an
12562 infinite loop as in the following code:
12567 In this case when the la is extended, foo is 0x3fc bytes
12568 away, so the la can be shrunk, but then foo is 0x400 away, so
12569 the la must be extended. To avoid this loop, we mark the
12570 frag as extended if it was small, and is about to become
12571 extended with a value of maxtiny + 1. */
12572 if (val
== ((maxtiny
+ 1) << op
->shift
)
12573 && ! RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
)
12576 fragp
->fr_subtype
=
12577 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
12581 else if (symsec
!= absolute_section
&& sec
!= NULL
)
12582 as_bad_where (fragp
->fr_file
, fragp
->fr_line
, _("unsupported relocation"));
12584 if ((val
& ((1 << op
->shift
) - 1)) != 0
12585 || val
< (mintiny
<< op
->shift
)
12586 || val
> (maxtiny
<< op
->shift
))
12592 /* Compute the length of a branch sequence, and adjust the
12593 RELAX_BRANCH_TOOFAR bit accordingly. If FRAGP is NULL, the
12594 worst-case length is computed, with UPDATE being used to indicate
12595 whether an unconditional (-1), branch-likely (+1) or regular (0)
12596 branch is to be computed. */
12598 relaxed_branch_length (fragS
*fragp
, asection
*sec
, int update
)
12600 bfd_boolean toofar
;
12604 && S_IS_DEFINED (fragp
->fr_symbol
)
12605 && sec
== S_GET_SEGMENT (fragp
->fr_symbol
))
12610 val
= S_GET_VALUE (fragp
->fr_symbol
) + fragp
->fr_offset
;
12612 addr
= fragp
->fr_address
+ fragp
->fr_fix
+ 4;
12616 toofar
= val
< - (0x8000 << 2) || val
>= (0x8000 << 2);
12619 /* If the symbol is not defined or it's in a different segment,
12620 assume the user knows what's going on and emit a short
12626 if (fragp
&& update
&& toofar
!= RELAX_BRANCH_TOOFAR (fragp
->fr_subtype
))
12628 = RELAX_BRANCH_ENCODE (RELAX_BRANCH_UNCOND (fragp
->fr_subtype
),
12629 RELAX_BRANCH_LIKELY (fragp
->fr_subtype
),
12630 RELAX_BRANCH_LINK (fragp
->fr_subtype
),
12636 if (fragp
? RELAX_BRANCH_LIKELY (fragp
->fr_subtype
) : (update
> 0))
12639 if (mips_pic
!= NO_PIC
)
12641 /* Additional space for PIC loading of target address. */
12643 if (mips_opts
.isa
== ISA_MIPS1
)
12644 /* Additional space for $at-stabilizing nop. */
12648 /* If branch is conditional. */
12649 if (fragp
? !RELAX_BRANCH_UNCOND (fragp
->fr_subtype
) : (update
>= 0))
12656 /* Estimate the size of a frag before relaxing. Unless this is the
12657 mips16, we are not really relaxing here, and the final size is
12658 encoded in the subtype information. For the mips16, we have to
12659 decide whether we are using an extended opcode or not. */
12662 md_estimate_size_before_relax (fragS
*fragp
, asection
*segtype
)
12666 if (RELAX_BRANCH_P (fragp
->fr_subtype
))
12669 fragp
->fr_var
= relaxed_branch_length (fragp
, segtype
, FALSE
);
12671 return fragp
->fr_var
;
12674 if (RELAX_MIPS16_P (fragp
->fr_subtype
))
12675 /* We don't want to modify the EXTENDED bit here; it might get us
12676 into infinite loops. We change it only in mips_relax_frag(). */
12677 return (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
) ? 4 : 2);
12679 if (mips_pic
== NO_PIC
)
12680 change
= nopic_need_relax (fragp
->fr_symbol
, 0);
12681 else if (mips_pic
== SVR4_PIC
)
12682 change
= pic_need_relax (fragp
->fr_symbol
, segtype
);
12688 fragp
->fr_subtype
|= RELAX_USE_SECOND
;
12689 return -RELAX_FIRST (fragp
->fr_subtype
);
12692 return -RELAX_SECOND (fragp
->fr_subtype
);
12695 /* This is called to see whether a reloc against a defined symbol
12696 should be converted into a reloc against a section. Don't adjust
12697 MIPS16 jump relocations, so we don't have to worry about the format
12698 of the offset in the .o file. Don't adjust relocations against
12699 mips16 symbols, so that the linker can find them if it needs to set
12703 mips_fix_adjustable (fixS
*fixp
)
12705 if (fixp
->fx_r_type
== BFD_RELOC_MIPS16_JMP
)
12708 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
12709 || fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
12712 if (fixp
->fx_addsy
== NULL
)
12716 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
12717 && S_GET_OTHER (fixp
->fx_addsy
) == STO_MIPS16
12718 && fixp
->fx_subsy
== NULL
)
12725 /* Translate internal representation of relocation info to BFD target
12729 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
, fixS
*fixp
)
12731 static arelent
*retval
[4];
12733 bfd_reloc_code_real_type code
;
12735 memset (retval
, 0, sizeof(retval
));
12736 reloc
= retval
[0] = (arelent
*) xcalloc (1, sizeof (arelent
));
12737 reloc
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
12738 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
12739 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
12741 assert (! fixp
->fx_pcrel
);
12742 reloc
->addend
= fixp
->fx_addnumber
;
12744 /* Since the old MIPS ELF ABI uses Rel instead of Rela, encode the vtable
12745 entry to be used in the relocation's section offset. */
12746 if (! HAVE_NEWABI
&& fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
12748 reloc
->address
= reloc
->addend
;
12752 code
= fixp
->fx_r_type
;
12754 /* To support a PC relative reloc, we used a Cygnus extension.
12755 We check for that here to make sure that we don't let such a
12756 reloc escape normally. (FIXME: This was formerly used by
12757 embedded-PIC support, but is now used by branch handling in
12758 general. That probably should be fixed.) */
12759 if ((OUTPUT_FLAVOR
== bfd_target_ecoff_flavour
12760 || OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
12761 && code
== BFD_RELOC_16_PCREL_S2
)
12762 reloc
->howto
= NULL
;
12764 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
12766 if (reloc
->howto
== NULL
)
12768 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
12769 _("Can not represent %s relocation in this object file format"),
12770 bfd_get_reloc_code_name (code
));
12777 /* Relax a machine dependent frag. This returns the amount by which
12778 the current size of the frag should change. */
12781 mips_relax_frag (asection
*sec
, fragS
*fragp
, long stretch
)
12783 if (RELAX_BRANCH_P (fragp
->fr_subtype
))
12785 offsetT old_var
= fragp
->fr_var
;
12787 fragp
->fr_var
= relaxed_branch_length (fragp
, sec
, TRUE
);
12789 return fragp
->fr_var
- old_var
;
12792 if (! RELAX_MIPS16_P (fragp
->fr_subtype
))
12795 if (mips16_extended_frag (fragp
, NULL
, stretch
))
12797 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
12799 fragp
->fr_subtype
= RELAX_MIPS16_MARK_EXTENDED (fragp
->fr_subtype
);
12804 if (! RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
12806 fragp
->fr_subtype
= RELAX_MIPS16_CLEAR_EXTENDED (fragp
->fr_subtype
);
12813 /* Convert a machine dependent frag. */
12816 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
, segT asec
, fragS
*fragp
)
12818 if (RELAX_BRANCH_P (fragp
->fr_subtype
))
12821 unsigned long insn
;
12825 buf
= (bfd_byte
*)fragp
->fr_literal
+ fragp
->fr_fix
;
12827 if (target_big_endian
)
12828 insn
= bfd_getb32 (buf
);
12830 insn
= bfd_getl32 (buf
);
12832 if (!RELAX_BRANCH_TOOFAR (fragp
->fr_subtype
))
12834 /* We generate a fixup instead of applying it right now
12835 because, if there are linker relaxations, we're going to
12836 need the relocations. */
12837 exp
.X_op
= O_symbol
;
12838 exp
.X_add_symbol
= fragp
->fr_symbol
;
12839 exp
.X_add_number
= fragp
->fr_offset
;
12841 fixp
= fix_new_exp (fragp
, buf
- (bfd_byte
*)fragp
->fr_literal
,
12843 BFD_RELOC_16_PCREL_S2
);
12844 fixp
->fx_file
= fragp
->fr_file
;
12845 fixp
->fx_line
= fragp
->fr_line
;
12847 md_number_to_chars (buf
, insn
, 4);
12854 as_warn_where (fragp
->fr_file
, fragp
->fr_line
,
12855 _("relaxed out-of-range branch into a jump"));
12857 if (RELAX_BRANCH_UNCOND (fragp
->fr_subtype
))
12860 if (!RELAX_BRANCH_LIKELY (fragp
->fr_subtype
))
12862 /* Reverse the branch. */
12863 switch ((insn
>> 28) & 0xf)
12866 /* bc[0-3][tf]l? and bc1any[24][ft] instructions can
12867 have the condition reversed by tweaking a single
12868 bit, and their opcodes all have 0x4???????. */
12869 assert ((insn
& 0xf1000000) == 0x41000000);
12870 insn
^= 0x00010000;
12874 /* bltz 0x04000000 bgez 0x04010000
12875 bltzal 0x04100000 bgezal 0x04110000 */
12876 assert ((insn
& 0xfc0e0000) == 0x04000000);
12877 insn
^= 0x00010000;
12881 /* beq 0x10000000 bne 0x14000000
12882 blez 0x18000000 bgtz 0x1c000000 */
12883 insn
^= 0x04000000;
12891 if (RELAX_BRANCH_LINK (fragp
->fr_subtype
))
12893 /* Clear the and-link bit. */
12894 assert ((insn
& 0xfc1c0000) == 0x04100000);
12896 /* bltzal 0x04100000 bgezal 0x04110000
12897 bltzall 0x04120000 bgezall 0x04130000 */
12898 insn
&= ~0x00100000;
12901 /* Branch over the branch (if the branch was likely) or the
12902 full jump (not likely case). Compute the offset from the
12903 current instruction to branch to. */
12904 if (RELAX_BRANCH_LIKELY (fragp
->fr_subtype
))
12908 /* How many bytes in instructions we've already emitted? */
12909 i
= buf
- (bfd_byte
*)fragp
->fr_literal
- fragp
->fr_fix
;
12910 /* How many bytes in instructions from here to the end? */
12911 i
= fragp
->fr_var
- i
;
12913 /* Convert to instruction count. */
12915 /* Branch counts from the next instruction. */
12918 /* Branch over the jump. */
12919 md_number_to_chars (buf
, insn
, 4);
12923 md_number_to_chars (buf
, 0, 4);
12926 if (RELAX_BRANCH_LIKELY (fragp
->fr_subtype
))
12928 /* beql $0, $0, 2f */
12930 /* Compute the PC offset from the current instruction to
12931 the end of the variable frag. */
12932 /* How many bytes in instructions we've already emitted? */
12933 i
= buf
- (bfd_byte
*)fragp
->fr_literal
- fragp
->fr_fix
;
12934 /* How many bytes in instructions from here to the end? */
12935 i
= fragp
->fr_var
- i
;
12936 /* Convert to instruction count. */
12938 /* Don't decrement i, because we want to branch over the
12942 md_number_to_chars (buf
, insn
, 4);
12945 md_number_to_chars (buf
, 0, 4);
12950 if (mips_pic
== NO_PIC
)
12953 insn
= (RELAX_BRANCH_LINK (fragp
->fr_subtype
)
12954 ? 0x0c000000 : 0x08000000);
12955 exp
.X_op
= O_symbol
;
12956 exp
.X_add_symbol
= fragp
->fr_symbol
;
12957 exp
.X_add_number
= fragp
->fr_offset
;
12959 fixp
= fix_new_exp (fragp
, buf
- (bfd_byte
*)fragp
->fr_literal
,
12960 4, &exp
, 0, BFD_RELOC_MIPS_JMP
);
12961 fixp
->fx_file
= fragp
->fr_file
;
12962 fixp
->fx_line
= fragp
->fr_line
;
12964 md_number_to_chars (buf
, insn
, 4);
12969 /* lw/ld $at, <sym>($gp) R_MIPS_GOT16 */
12970 insn
= HAVE_64BIT_ADDRESSES
? 0xdf810000 : 0x8f810000;
12971 exp
.X_op
= O_symbol
;
12972 exp
.X_add_symbol
= fragp
->fr_symbol
;
12973 exp
.X_add_number
= fragp
->fr_offset
;
12975 if (fragp
->fr_offset
)
12977 exp
.X_add_symbol
= make_expr_symbol (&exp
);
12978 exp
.X_add_number
= 0;
12981 fixp
= fix_new_exp (fragp
, buf
- (bfd_byte
*)fragp
->fr_literal
,
12982 4, &exp
, 0, BFD_RELOC_MIPS_GOT16
);
12983 fixp
->fx_file
= fragp
->fr_file
;
12984 fixp
->fx_line
= fragp
->fr_line
;
12986 md_number_to_chars (buf
, insn
, 4);
12989 if (mips_opts
.isa
== ISA_MIPS1
)
12992 md_number_to_chars (buf
, 0, 4);
12996 /* d/addiu $at, $at, <sym> R_MIPS_LO16 */
12997 insn
= HAVE_64BIT_ADDRESSES
? 0x64210000 : 0x24210000;
12999 fixp
= fix_new_exp (fragp
, buf
- (bfd_byte
*)fragp
->fr_literal
,
13000 4, &exp
, 0, BFD_RELOC_LO16
);
13001 fixp
->fx_file
= fragp
->fr_file
;
13002 fixp
->fx_line
= fragp
->fr_line
;
13004 md_number_to_chars (buf
, insn
, 4);
13008 if (RELAX_BRANCH_LINK (fragp
->fr_subtype
))
13013 md_number_to_chars (buf
, insn
, 4);
13018 assert (buf
== (bfd_byte
*)fragp
->fr_literal
13019 + fragp
->fr_fix
+ fragp
->fr_var
);
13021 fragp
->fr_fix
+= fragp
->fr_var
;
13026 if (RELAX_MIPS16_P (fragp
->fr_subtype
))
13029 register const struct mips16_immed_operand
*op
;
13030 bfd_boolean small
, ext
;
13033 unsigned long insn
;
13034 bfd_boolean use_extend
;
13035 unsigned short extend
;
13037 type
= RELAX_MIPS16_TYPE (fragp
->fr_subtype
);
13038 op
= mips16_immed_operands
;
13039 while (op
->type
!= type
)
13042 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
13053 resolve_symbol_value (fragp
->fr_symbol
);
13054 val
= S_GET_VALUE (fragp
->fr_symbol
);
13059 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
13061 /* The rules for the base address of a PC relative reloc are
13062 complicated; see mips16_extended_frag. */
13063 if (type
== 'p' || type
== 'q')
13068 /* Ignore the low bit in the target, since it will be
13069 set for a text label. */
13070 if ((val
& 1) != 0)
13073 else if (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
))
13075 else if (RELAX_MIPS16_DSLOT (fragp
->fr_subtype
))
13078 addr
&= ~ (addressT
) ((1 << op
->shift
) - 1);
13081 /* Make sure the section winds up with the alignment we have
13084 record_alignment (asec
, op
->shift
);
13088 && (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
)
13089 || RELAX_MIPS16_DSLOT (fragp
->fr_subtype
)))
13090 as_warn_where (fragp
->fr_file
, fragp
->fr_line
,
13091 _("extended instruction in delay slot"));
13093 buf
= (bfd_byte
*) (fragp
->fr_literal
+ fragp
->fr_fix
);
13095 if (target_big_endian
)
13096 insn
= bfd_getb16 (buf
);
13098 insn
= bfd_getl16 (buf
);
13100 mips16_immed (fragp
->fr_file
, fragp
->fr_line
, type
, val
,
13101 RELAX_MIPS16_USER_EXT (fragp
->fr_subtype
),
13102 small
, ext
, &insn
, &use_extend
, &extend
);
13106 md_number_to_chars (buf
, 0xf000 | extend
, 2);
13107 fragp
->fr_fix
+= 2;
13111 md_number_to_chars (buf
, insn
, 2);
13112 fragp
->fr_fix
+= 2;
13120 first
= RELAX_FIRST (fragp
->fr_subtype
);
13121 second
= RELAX_SECOND (fragp
->fr_subtype
);
13122 fixp
= (fixS
*) fragp
->fr_opcode
;
13124 /* Possibly emit a warning if we've chosen the longer option. */
13125 if (((fragp
->fr_subtype
& RELAX_USE_SECOND
) != 0)
13126 == ((fragp
->fr_subtype
& RELAX_SECOND_LONGER
) != 0))
13128 const char *msg
= macro_warning (fragp
->fr_subtype
);
13130 as_warn_where (fragp
->fr_file
, fragp
->fr_line
, msg
);
13133 /* Go through all the fixups for the first sequence. Disable them
13134 (by marking them as done) if we're going to use the second
13135 sequence instead. */
13137 && fixp
->fx_frag
== fragp
13138 && fixp
->fx_where
< fragp
->fr_fix
- second
)
13140 if (fragp
->fr_subtype
& RELAX_USE_SECOND
)
13142 fixp
= fixp
->fx_next
;
13145 /* Go through the fixups for the second sequence. Disable them if
13146 we're going to use the first sequence, otherwise adjust their
13147 addresses to account for the relaxation. */
13148 while (fixp
&& fixp
->fx_frag
== fragp
)
13150 if (fragp
->fr_subtype
& RELAX_USE_SECOND
)
13151 fixp
->fx_where
-= first
;
13154 fixp
= fixp
->fx_next
;
13157 /* Now modify the frag contents. */
13158 if (fragp
->fr_subtype
& RELAX_USE_SECOND
)
13162 start
= fragp
->fr_literal
+ fragp
->fr_fix
- first
- second
;
13163 memmove (start
, start
+ first
, second
);
13164 fragp
->fr_fix
-= first
;
13167 fragp
->fr_fix
-= second
;
13173 /* This function is called after the relocs have been generated.
13174 We've been storing mips16 text labels as odd. Here we convert them
13175 back to even for the convenience of the debugger. */
13178 mips_frob_file_after_relocs (void)
13181 unsigned int count
, i
;
13183 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
13186 syms
= bfd_get_outsymbols (stdoutput
);
13187 count
= bfd_get_symcount (stdoutput
);
13188 for (i
= 0; i
< count
; i
++, syms
++)
13190 if (elf_symbol (*syms
)->internal_elf_sym
.st_other
== STO_MIPS16
13191 && ((*syms
)->value
& 1) != 0)
13193 (*syms
)->value
&= ~1;
13194 /* If the symbol has an odd size, it was probably computed
13195 incorrectly, so adjust that as well. */
13196 if ((elf_symbol (*syms
)->internal_elf_sym
.st_size
& 1) != 0)
13197 ++elf_symbol (*syms
)->internal_elf_sym
.st_size
;
13204 /* This function is called whenever a label is defined. It is used
13205 when handling branch delays; if a branch has a label, we assume we
13206 can not move it. */
13209 mips_define_label (symbolS
*sym
)
13211 struct insn_label_list
*l
;
13213 if (free_insn_labels
== NULL
)
13214 l
= (struct insn_label_list
*) xmalloc (sizeof *l
);
13217 l
= free_insn_labels
;
13218 free_insn_labels
= l
->next
;
13222 l
->next
= insn_labels
;
13226 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13228 /* Some special processing for a MIPS ELF file. */
13231 mips_elf_final_processing (void)
13233 /* Write out the register information. */
13234 if (mips_abi
!= N64_ABI
)
13238 s
.ri_gprmask
= mips_gprmask
;
13239 s
.ri_cprmask
[0] = mips_cprmask
[0];
13240 s
.ri_cprmask
[1] = mips_cprmask
[1];
13241 s
.ri_cprmask
[2] = mips_cprmask
[2];
13242 s
.ri_cprmask
[3] = mips_cprmask
[3];
13243 /* The gp_value field is set by the MIPS ELF backend. */
13245 bfd_mips_elf32_swap_reginfo_out (stdoutput
, &s
,
13246 ((Elf32_External_RegInfo
*)
13247 mips_regmask_frag
));
13251 Elf64_Internal_RegInfo s
;
13253 s
.ri_gprmask
= mips_gprmask
;
13255 s
.ri_cprmask
[0] = mips_cprmask
[0];
13256 s
.ri_cprmask
[1] = mips_cprmask
[1];
13257 s
.ri_cprmask
[2] = mips_cprmask
[2];
13258 s
.ri_cprmask
[3] = mips_cprmask
[3];
13259 /* The gp_value field is set by the MIPS ELF backend. */
13261 bfd_mips_elf64_swap_reginfo_out (stdoutput
, &s
,
13262 ((Elf64_External_RegInfo
*)
13263 mips_regmask_frag
));
13266 /* Set the MIPS ELF flag bits. FIXME: There should probably be some
13267 sort of BFD interface for this. */
13268 if (mips_any_noreorder
)
13269 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_NOREORDER
;
13270 if (mips_pic
!= NO_PIC
)
13272 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_PIC
;
13273 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_CPIC
;
13276 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_CPIC
;
13278 /* Set MIPS ELF flags for ASEs. */
13279 if (file_ase_mips16
)
13280 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ARCH_ASE_M16
;
13281 #if 0 /* XXX FIXME */
13282 if (file_ase_mips3d
)
13283 elf_elfheader (stdoutput
)->e_flags
|= ???;
13286 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ARCH_ASE_MDMX
;
13288 /* Set the MIPS ELF ABI flags. */
13289 if (mips_abi
== O32_ABI
&& USE_E_MIPS_ABI_O32
)
13290 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_O32
;
13291 else if (mips_abi
== O64_ABI
)
13292 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_O64
;
13293 else if (mips_abi
== EABI_ABI
)
13295 if (!file_mips_gp32
)
13296 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_EABI64
;
13298 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_EABI32
;
13300 else if (mips_abi
== N32_ABI
)
13301 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ABI2
;
13303 /* Nothing to do for N64_ABI. */
13305 if (mips_32bitmode
)
13306 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_32BITMODE
;
13309 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */
13311 typedef struct proc
{
13313 unsigned long reg_mask
;
13314 unsigned long reg_offset
;
13315 unsigned long fpreg_mask
;
13316 unsigned long fpreg_offset
;
13317 unsigned long frame_offset
;
13318 unsigned long frame_reg
;
13319 unsigned long pc_reg
;
13322 static procS cur_proc
;
13323 static procS
*cur_proc_ptr
;
13324 static int numprocs
;
13326 /* Fill in an rs_align_code fragment. */
13329 mips_handle_align (fragS
*fragp
)
13331 if (fragp
->fr_type
!= rs_align_code
)
13334 if (mips_opts
.mips16
)
13336 static const unsigned char be_nop
[] = { 0x65, 0x00 };
13337 static const unsigned char le_nop
[] = { 0x00, 0x65 };
13342 bytes
= fragp
->fr_next
->fr_address
- fragp
->fr_address
- fragp
->fr_fix
;
13343 p
= fragp
->fr_literal
+ fragp
->fr_fix
;
13351 memcpy (p
, (target_big_endian
? be_nop
: le_nop
), 2);
13355 /* For mips32, a nop is a zero, which we trivially get by doing nothing. */
13359 md_obj_begin (void)
13366 /* check for premature end, nesting errors, etc */
13368 as_warn (_("missing .end at end of assembly"));
13377 if (*input_line_pointer
== '-')
13379 ++input_line_pointer
;
13382 if (!ISDIGIT (*input_line_pointer
))
13383 as_bad (_("expected simple number"));
13384 if (input_line_pointer
[0] == '0')
13386 if (input_line_pointer
[1] == 'x')
13388 input_line_pointer
+= 2;
13389 while (ISXDIGIT (*input_line_pointer
))
13392 val
|= hex_value (*input_line_pointer
++);
13394 return negative
? -val
: val
;
13398 ++input_line_pointer
;
13399 while (ISDIGIT (*input_line_pointer
))
13402 val
|= *input_line_pointer
++ - '0';
13404 return negative
? -val
: val
;
13407 if (!ISDIGIT (*input_line_pointer
))
13409 printf (_(" *input_line_pointer == '%c' 0x%02x\n"),
13410 *input_line_pointer
, *input_line_pointer
);
13411 as_warn (_("invalid number"));
13414 while (ISDIGIT (*input_line_pointer
))
13417 val
+= *input_line_pointer
++ - '0';
13419 return negative
? -val
: val
;
13422 /* The .file directive; just like the usual .file directive, but there
13423 is an initial number which is the ECOFF file index. In the non-ECOFF
13424 case .file implies DWARF-2. */
13427 s_mips_file (int x ATTRIBUTE_UNUSED
)
13429 static int first_file_directive
= 0;
13431 if (ECOFF_DEBUGGING
)
13440 filename
= dwarf2_directive_file (0);
13442 /* Versions of GCC up to 3.1 start files with a ".file"
13443 directive even for stabs output. Make sure that this
13444 ".file" is handled. Note that you need a version of GCC
13445 after 3.1 in order to support DWARF-2 on MIPS. */
13446 if (filename
!= NULL
&& ! first_file_directive
)
13448 (void) new_logical_line (filename
, -1);
13449 s_app_file_string (filename
);
13451 first_file_directive
= 1;
13455 /* The .loc directive, implying DWARF-2. */
13458 s_mips_loc (int x ATTRIBUTE_UNUSED
)
13460 if (!ECOFF_DEBUGGING
)
13461 dwarf2_directive_loc (0);
13464 /* The .end directive. */
13467 s_mips_end (int x ATTRIBUTE_UNUSED
)
13471 /* Following functions need their own .frame and .cprestore directives. */
13472 mips_frame_reg_valid
= 0;
13473 mips_cprestore_valid
= 0;
13475 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
13478 demand_empty_rest_of_line ();
13483 if ((bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) == 0)
13484 as_warn (_(".end not in text section"));
13488 as_warn (_(".end directive without a preceding .ent directive."));
13489 demand_empty_rest_of_line ();
13495 assert (S_GET_NAME (p
));
13496 if (strcmp (S_GET_NAME (p
), S_GET_NAME (cur_proc_ptr
->isym
)))
13497 as_warn (_(".end symbol does not match .ent symbol."));
13499 if (debug_type
== DEBUG_STABS
)
13500 stabs_generate_asm_endfunc (S_GET_NAME (p
),
13504 as_warn (_(".end directive missing or unknown symbol"));
13507 /* Generate a .pdr section. */
13508 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
&& ! ECOFF_DEBUGGING
13511 segT saved_seg
= now_seg
;
13512 subsegT saved_subseg
= now_subseg
;
13517 dot
= frag_now_fix ();
13519 #ifdef md_flush_pending_output
13520 md_flush_pending_output ();
13524 subseg_set (pdr_seg
, 0);
13526 /* Write the symbol. */
13527 exp
.X_op
= O_symbol
;
13528 exp
.X_add_symbol
= p
;
13529 exp
.X_add_number
= 0;
13530 emit_expr (&exp
, 4);
13532 fragp
= frag_more (7 * 4);
13534 md_number_to_chars (fragp
, cur_proc_ptr
->reg_mask
, 4);
13535 md_number_to_chars (fragp
+ 4, cur_proc_ptr
->reg_offset
, 4);
13536 md_number_to_chars (fragp
+ 8, cur_proc_ptr
->fpreg_mask
, 4);
13537 md_number_to_chars (fragp
+ 12, cur_proc_ptr
->fpreg_offset
, 4);
13538 md_number_to_chars (fragp
+ 16, cur_proc_ptr
->frame_offset
, 4);
13539 md_number_to_chars (fragp
+ 20, cur_proc_ptr
->frame_reg
, 4);
13540 md_number_to_chars (fragp
+ 24, cur_proc_ptr
->pc_reg
, 4);
13542 subseg_set (saved_seg
, saved_subseg
);
13544 #endif /* OBJ_ELF */
13546 cur_proc_ptr
= NULL
;
13549 /* The .aent and .ent directives. */
13552 s_mips_ent (int aent
)
13556 symbolP
= get_symbol ();
13557 if (*input_line_pointer
== ',')
13558 ++input_line_pointer
;
13559 SKIP_WHITESPACE ();
13560 if (ISDIGIT (*input_line_pointer
)
13561 || *input_line_pointer
== '-')
13564 if ((bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) == 0)
13565 as_warn (_(".ent or .aent not in text section."));
13567 if (!aent
&& cur_proc_ptr
)
13568 as_warn (_("missing .end"));
13572 /* This function needs its own .frame and .cprestore directives. */
13573 mips_frame_reg_valid
= 0;
13574 mips_cprestore_valid
= 0;
13576 cur_proc_ptr
= &cur_proc
;
13577 memset (cur_proc_ptr
, '\0', sizeof (procS
));
13579 cur_proc_ptr
->isym
= symbolP
;
13581 symbol_get_bfdsym (symbolP
)->flags
|= BSF_FUNCTION
;
13585 if (debug_type
== DEBUG_STABS
)
13586 stabs_generate_asm_func (S_GET_NAME (symbolP
),
13587 S_GET_NAME (symbolP
));
13590 demand_empty_rest_of_line ();
13593 /* The .frame directive. If the mdebug section is present (IRIX 5 native)
13594 then ecoff.c (ecoff_directive_frame) is used. For embedded targets,
13595 s_mips_frame is used so that we can set the PDR information correctly.
13596 We can't use the ecoff routines because they make reference to the ecoff
13597 symbol table (in the mdebug section). */
13600 s_mips_frame (int ignore ATTRIBUTE_UNUSED
)
13603 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
&& ! ECOFF_DEBUGGING
)
13607 if (cur_proc_ptr
== (procS
*) NULL
)
13609 as_warn (_(".frame outside of .ent"));
13610 demand_empty_rest_of_line ();
13614 cur_proc_ptr
->frame_reg
= tc_get_register (1);
13616 SKIP_WHITESPACE ();
13617 if (*input_line_pointer
++ != ','
13618 || get_absolute_expression_and_terminator (&val
) != ',')
13620 as_warn (_("Bad .frame directive"));
13621 --input_line_pointer
;
13622 demand_empty_rest_of_line ();
13626 cur_proc_ptr
->frame_offset
= val
;
13627 cur_proc_ptr
->pc_reg
= tc_get_register (0);
13629 demand_empty_rest_of_line ();
13632 #endif /* OBJ_ELF */
13636 /* The .fmask and .mask directives. If the mdebug section is present
13637 (IRIX 5 native) then ecoff.c (ecoff_directive_mask) is used. For
13638 embedded targets, s_mips_mask is used so that we can set the PDR
13639 information correctly. We can't use the ecoff routines because they
13640 make reference to the ecoff symbol table (in the mdebug section). */
13643 s_mips_mask (int reg_type
)
13646 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
&& ! ECOFF_DEBUGGING
)
13650 if (cur_proc_ptr
== (procS
*) NULL
)
13652 as_warn (_(".mask/.fmask outside of .ent"));
13653 demand_empty_rest_of_line ();
13657 if (get_absolute_expression_and_terminator (&mask
) != ',')
13659 as_warn (_("Bad .mask/.fmask directive"));
13660 --input_line_pointer
;
13661 demand_empty_rest_of_line ();
13665 off
= get_absolute_expression ();
13667 if (reg_type
== 'F')
13669 cur_proc_ptr
->fpreg_mask
= mask
;
13670 cur_proc_ptr
->fpreg_offset
= off
;
13674 cur_proc_ptr
->reg_mask
= mask
;
13675 cur_proc_ptr
->reg_offset
= off
;
13678 demand_empty_rest_of_line ();
13681 #endif /* OBJ_ELF */
13682 s_ignore (reg_type
);
13685 /* The .loc directive. */
13695 assert (now_seg
== text_section
);
13697 lineno
= get_number ();
13698 addroff
= frag_now_fix ();
13700 symbolP
= symbol_new ("", N_SLINE
, addroff
, frag_now
);
13701 S_SET_TYPE (symbolP
, N_SLINE
);
13702 S_SET_OTHER (symbolP
, 0);
13703 S_SET_DESC (symbolP
, lineno
);
13704 symbolP
->sy_segment
= now_seg
;
13708 /* A table describing all the processors gas knows about. Names are
13709 matched in the order listed.
13711 To ease comparison, please keep this table in the same order as
13712 gcc's mips_cpu_info_table[]. */
13713 static const struct mips_cpu_info mips_cpu_info_table
[] =
13715 /* Entries for generic ISAs */
13716 { "mips1", 1, ISA_MIPS1
, CPU_R3000
},
13717 { "mips2", 1, ISA_MIPS2
, CPU_R6000
},
13718 { "mips3", 1, ISA_MIPS3
, CPU_R4000
},
13719 { "mips4", 1, ISA_MIPS4
, CPU_R8000
},
13720 { "mips5", 1, ISA_MIPS5
, CPU_MIPS5
},
13721 { "mips32", 1, ISA_MIPS32
, CPU_MIPS32
},
13722 { "mips32r2", 1, ISA_MIPS32R2
, CPU_MIPS32R2
},
13723 { "mips64", 1, ISA_MIPS64
, CPU_MIPS64
},
13724 { "mips64r2", 1, ISA_MIPS64R2
, CPU_MIPS64R2
},
13727 { "r3000", 0, ISA_MIPS1
, CPU_R3000
},
13728 { "r2000", 0, ISA_MIPS1
, CPU_R3000
},
13729 { "r3900", 0, ISA_MIPS1
, CPU_R3900
},
13732 { "r6000", 0, ISA_MIPS2
, CPU_R6000
},
13735 { "r4000", 0, ISA_MIPS3
, CPU_R4000
},
13736 { "r4010", 0, ISA_MIPS2
, CPU_R4010
},
13737 { "vr4100", 0, ISA_MIPS3
, CPU_VR4100
},
13738 { "vr4111", 0, ISA_MIPS3
, CPU_R4111
},
13739 { "vr4120", 0, ISA_MIPS3
, CPU_VR4120
},
13740 { "vr4130", 0, ISA_MIPS3
, CPU_VR4120
},
13741 { "vr4181", 0, ISA_MIPS3
, CPU_R4111
},
13742 { "vr4300", 0, ISA_MIPS3
, CPU_R4300
},
13743 { "r4400", 0, ISA_MIPS3
, CPU_R4400
},
13744 { "r4600", 0, ISA_MIPS3
, CPU_R4600
},
13745 { "orion", 0, ISA_MIPS3
, CPU_R4600
},
13746 { "r4650", 0, ISA_MIPS3
, CPU_R4650
},
13749 { "r8000", 0, ISA_MIPS4
, CPU_R8000
},
13750 { "r10000", 0, ISA_MIPS4
, CPU_R10000
},
13751 { "r12000", 0, ISA_MIPS4
, CPU_R12000
},
13752 { "vr5000", 0, ISA_MIPS4
, CPU_R5000
},
13753 { "vr5400", 0, ISA_MIPS4
, CPU_VR5400
},
13754 { "vr5500", 0, ISA_MIPS4
, CPU_VR5500
},
13755 { "rm5200", 0, ISA_MIPS4
, CPU_R5000
},
13756 { "rm5230", 0, ISA_MIPS4
, CPU_R5000
},
13757 { "rm5231", 0, ISA_MIPS4
, CPU_R5000
},
13758 { "rm5261", 0, ISA_MIPS4
, CPU_R5000
},
13759 { "rm5721", 0, ISA_MIPS4
, CPU_R5000
},
13760 { "rm7000", 0, ISA_MIPS4
, CPU_RM7000
},
13761 { "rm9000", 0, ISA_MIPS4
, CPU_RM7000
},
13764 { "4kc", 0, ISA_MIPS32
, CPU_MIPS32
},
13765 { "4km", 0, ISA_MIPS32
, CPU_MIPS32
},
13766 { "4kp", 0, ISA_MIPS32
, CPU_MIPS32
},
13769 { "5kc", 0, ISA_MIPS64
, CPU_MIPS64
},
13770 { "20kc", 0, ISA_MIPS64
, CPU_MIPS64
},
13772 /* Broadcom SB-1 CPU core */
13773 { "sb1", 0, ISA_MIPS64
, CPU_SB1
},
13780 /* Return true if GIVEN is the same as CANONICAL, or if it is CANONICAL
13781 with a final "000" replaced by "k". Ignore case.
13783 Note: this function is shared between GCC and GAS. */
13786 mips_strict_matching_cpu_name_p (const char *canonical
, const char *given
)
13788 while (*given
!= 0 && TOLOWER (*given
) == TOLOWER (*canonical
))
13789 given
++, canonical
++;
13791 return ((*given
== 0 && *canonical
== 0)
13792 || (strcmp (canonical
, "000") == 0 && strcasecmp (given
, "k") == 0));
13796 /* Return true if GIVEN matches CANONICAL, where GIVEN is a user-supplied
13797 CPU name. We've traditionally allowed a lot of variation here.
13799 Note: this function is shared between GCC and GAS. */
13802 mips_matching_cpu_name_p (const char *canonical
, const char *given
)
13804 /* First see if the name matches exactly, or with a final "000"
13805 turned into "k". */
13806 if (mips_strict_matching_cpu_name_p (canonical
, given
))
13809 /* If not, try comparing based on numerical designation alone.
13810 See if GIVEN is an unadorned number, or 'r' followed by a number. */
13811 if (TOLOWER (*given
) == 'r')
13813 if (!ISDIGIT (*given
))
13816 /* Skip over some well-known prefixes in the canonical name,
13817 hoping to find a number there too. */
13818 if (TOLOWER (canonical
[0]) == 'v' && TOLOWER (canonical
[1]) == 'r')
13820 else if (TOLOWER (canonical
[0]) == 'r' && TOLOWER (canonical
[1]) == 'm')
13822 else if (TOLOWER (canonical
[0]) == 'r')
13825 return mips_strict_matching_cpu_name_p (canonical
, given
);
13829 /* Parse an option that takes the name of a processor as its argument.
13830 OPTION is the name of the option and CPU_STRING is the argument.
13831 Return the corresponding processor enumeration if the CPU_STRING is
13832 recognized, otherwise report an error and return null.
13834 A similar function exists in GCC. */
13836 static const struct mips_cpu_info
*
13837 mips_parse_cpu (const char *option
, const char *cpu_string
)
13839 const struct mips_cpu_info
*p
;
13841 /* 'from-abi' selects the most compatible architecture for the given
13842 ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit ABIs. For the
13843 EABIs, we have to decide whether we're using the 32-bit or 64-bit
13844 version. Look first at the -mgp options, if given, otherwise base
13845 the choice on MIPS_DEFAULT_64BIT.
13847 Treat NO_ABI like the EABIs. One reason to do this is that the
13848 plain 'mips' and 'mips64' configs have 'from-abi' as their default
13849 architecture. This code picks MIPS I for 'mips' and MIPS III for
13850 'mips64', just as we did in the days before 'from-abi'. */
13851 if (strcasecmp (cpu_string
, "from-abi") == 0)
13853 if (ABI_NEEDS_32BIT_REGS (mips_abi
))
13854 return mips_cpu_info_from_isa (ISA_MIPS1
);
13856 if (ABI_NEEDS_64BIT_REGS (mips_abi
))
13857 return mips_cpu_info_from_isa (ISA_MIPS3
);
13859 if (file_mips_gp32
>= 0)
13860 return mips_cpu_info_from_isa (file_mips_gp32
? ISA_MIPS1
: ISA_MIPS3
);
13862 return mips_cpu_info_from_isa (MIPS_DEFAULT_64BIT
13867 /* 'default' has traditionally been a no-op. Probably not very useful. */
13868 if (strcasecmp (cpu_string
, "default") == 0)
13871 for (p
= mips_cpu_info_table
; p
->name
!= 0; p
++)
13872 if (mips_matching_cpu_name_p (p
->name
, cpu_string
))
13875 as_bad ("Bad value (%s) for %s", cpu_string
, option
);
13879 /* Return the canonical processor information for ISA (a member of the
13880 ISA_MIPS* enumeration). */
13882 static const struct mips_cpu_info
*
13883 mips_cpu_info_from_isa (int isa
)
13887 for (i
= 0; mips_cpu_info_table
[i
].name
!= NULL
; i
++)
13888 if (mips_cpu_info_table
[i
].is_isa
13889 && isa
== mips_cpu_info_table
[i
].isa
)
13890 return (&mips_cpu_info_table
[i
]);
13895 static const struct mips_cpu_info
*
13896 mips_cpu_info_from_arch (int arch
)
13900 for (i
= 0; mips_cpu_info_table
[i
].name
!= NULL
; i
++)
13901 if (arch
== mips_cpu_info_table
[i
].cpu
)
13902 return (&mips_cpu_info_table
[i
]);
13908 show (FILE *stream
, const char *string
, int *col_p
, int *first_p
)
13912 fprintf (stream
, "%24s", "");
13917 fprintf (stream
, ", ");
13921 if (*col_p
+ strlen (string
) > 72)
13923 fprintf (stream
, "\n%24s", "");
13927 fprintf (stream
, "%s", string
);
13928 *col_p
+= strlen (string
);
13934 md_show_usage (FILE *stream
)
13939 fprintf (stream
, _("\
13941 -EB generate big endian output\n\
13942 -EL generate little endian output\n\
13943 -g, -g2 do not remove unneeded NOPs or swap branches\n\
13944 -G NUM allow referencing objects up to NUM bytes\n\
13945 implicitly with the gp register [default 8]\n"));
13946 fprintf (stream
, _("\
13947 -mips1 generate MIPS ISA I instructions\n\
13948 -mips2 generate MIPS ISA II instructions\n\
13949 -mips3 generate MIPS ISA III instructions\n\
13950 -mips4 generate MIPS ISA IV instructions\n\
13951 -mips5 generate MIPS ISA V instructions\n\
13952 -mips32 generate MIPS32 ISA instructions\n\
13953 -mips32r2 generate MIPS32 release 2 ISA instructions\n\
13954 -mips64 generate MIPS64 ISA instructions\n\
13955 -mips64r2 generate MIPS64 release 2 ISA instructions\n\
13956 -march=CPU/-mtune=CPU generate code/schedule for CPU, where CPU is one of:\n"));
13960 for (i
= 0; mips_cpu_info_table
[i
].name
!= NULL
; i
++)
13961 show (stream
, mips_cpu_info_table
[i
].name
, &column
, &first
);
13962 show (stream
, "from-abi", &column
, &first
);
13963 fputc ('\n', stream
);
13965 fprintf (stream
, _("\
13966 -mCPU equivalent to -march=CPU -mtune=CPU. Deprecated.\n\
13967 -no-mCPU don't generate code specific to CPU.\n\
13968 For -mCPU and -no-mCPU, CPU must be one of:\n"));
13972 show (stream
, "3900", &column
, &first
);
13973 show (stream
, "4010", &column
, &first
);
13974 show (stream
, "4100", &column
, &first
);
13975 show (stream
, "4650", &column
, &first
);
13976 fputc ('\n', stream
);
13978 fprintf (stream
, _("\
13979 -mips16 generate mips16 instructions\n\
13980 -no-mips16 do not generate mips16 instructions\n"));
13981 fprintf (stream
, _("\
13982 -mfix-vr4120 work around certain VR4120 errata\n\
13983 -mgp32 use 32-bit GPRs, regardless of the chosen ISA\n\
13984 -mfp32 use 32-bit FPRs, regardless of the chosen ISA\n\
13985 -O0 remove unneeded NOPs, do not swap branches\n\
13986 -O remove unneeded NOPs and swap branches\n\
13987 --[no-]construct-floats [dis]allow floating point values to be constructed\n\
13988 --trap, --no-break trap exception on div by 0 and mult overflow\n\
13989 --break, --no-trap break exception on div by 0 and mult overflow\n"));
13991 fprintf (stream
, _("\
13992 -KPIC, -call_shared generate SVR4 position independent code\n\
13993 -non_shared do not generate position independent code\n\
13994 -xgot assume a 32 bit GOT\n\
13995 -mpdr, -mno-pdr enable/disable creation of .pdr sections\n\
13996 -mabi=ABI create ABI conformant object file for:\n"));
14000 show (stream
, "32", &column
, &first
);
14001 show (stream
, "o64", &column
, &first
);
14002 show (stream
, "n32", &column
, &first
);
14003 show (stream
, "64", &column
, &first
);
14004 show (stream
, "eabi", &column
, &first
);
14006 fputc ('\n', stream
);
14008 fprintf (stream
, _("\
14009 -32 create o32 ABI object file (default)\n\
14010 -n32 create n32 ABI object file\n\
14011 -64 create 64 ABI object file\n"));
14016 mips_dwarf2_format (void)
14018 if (mips_abi
== N64_ABI
)
14021 return dwarf2_format_64bit_irix
;
14023 return dwarf2_format_64bit
;
14027 return dwarf2_format_32bit
;
14031 mips_dwarf2_addr_size (void)
14033 if (mips_abi
== N64_ABI
)