1 /* tc-mips.c -- assemble code for a MIPS chip.
2 Copyright (C) 1993 Free Software Foundation, Inc.
3 Contributed by the OSF and Ralph Campbell.
4 Written by Keith Knowles and Ralph Campbell, working independently.
5 Modified for ECOFF support by Ian Lance Taylor of Cygnus Support.
7 This file is part of GAS.
9 GAS is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2, or (at your option)
14 GAS is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with GAS; see the file COPYING. If not, write to
21 the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */
38 #endif /* NO_VARARGS */
39 #endif /* NO_STDARG */
41 #include "opcode/mips.h"
47 static int mips_warn_about_macros
;
48 static int mips_noreorder
;
49 static int mips_nomove
;
51 static int mips_nobopt
;
54 /* The size of the small data section. */
55 static int g_switch_value
= 8;
61 /* handle of the OPCODE hash table */
62 static struct hash_control
*op_hash
= NULL
;
64 /* This array holds the chars that always start a comment. If the
65 pre-processor is disabled, these aren't very useful */
66 const char comment_chars
[] = "#";
68 /* This array holds the chars that only start a comment at the beginning of
69 a line. If the line seems to have the form '# 123 filename'
70 .line and .file directives will appear in the pre-processed output */
71 /* Note that input_file.c hand checks for '#' at the beginning of the
72 first line of the input file. This is because the compiler outputs
73 #NO_APP at the beginning of its output. */
74 /* Also note that C style comments are always supported. */
75 const char line_comment_chars
[] = "#";
77 /* This array holds machine specific line separator characters. */
78 const char line_separator_chars
[] = "";
80 /* Chars that can be used to separate mant from exp in floating point nums */
81 const char EXP_CHARS
[] = "eE";
83 /* Chars that mean this number is a floating point constant */
86 const char FLT_CHARS
[] = "rRsSfFdDxXpP";
88 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
89 changed in read.c . Ideally it shouldn't have to know about it at all,
90 but nothing is ideal around here.
93 static char *insn_error
;
95 static int byte_order
= BYTE_ORDER
;
97 static int auto_align
= 1;
99 /* Symbol labelling the current insn. */
100 static symbolS
*insn_label
;
102 /* To output NOP instructions correctly, we need to keep information
103 about the previous two instructions. */
105 /* The previous instruction. */
106 static struct mips_cl_insn prev_insn
;
108 /* The instruction before prev_insn. */
109 static struct mips_cl_insn prev_prev_insn
;
111 /* If we don't want information for prev_insn or prev_prev_insn, we
112 point the insn_mo field at this dummy integer. */
113 static const struct mips_opcode dummy_opcode
= { 0 };
115 /* Non-zero if prev_insn is valid. */
116 static int prev_insn_valid
;
118 /* The frag for the previous instruction. */
119 static struct frag
*prev_insn_frag
;
121 /* The offset into prev_insn_frag for the previous instruction. */
122 static long prev_insn_where
;
124 /* The reloc for the previous instruction, if any. */
125 static fixS
*prev_insn_fixp
;
127 /* Non-zero if the previous instruction was in a delay slot. */
128 static int prev_insn_is_delay_slot
;
130 /* Prototypes for static functions. */
133 #define internalError() \
134 as_fatal ("internal Error, line %d, %s", __LINE__, __FILE__)
136 #define internalError() as_fatal ("MIPS internal Error");
139 static int insn_uses_reg
PARAMS ((struct mips_cl_insn
*ip
,
141 static void append_insn
PARAMS ((struct mips_cl_insn
* ip
,
143 bfd_reloc_code_real_type r
));
144 static void mips_no_prev_insn
PARAMS ((void));
145 static void mips_emit_delays
PARAMS ((void));
146 static int gp_reference
PARAMS ((expressionS
* ep
));
147 static void macro_build
PARAMS ((int *counter
, expressionS
* ep
,
148 const char *name
, const char *fmt
,
150 static void macro_build_lui
PARAMS ((int *counter
, expressionS
* ep
,
152 static void set_at
PARAMS ((int *counter
, int reg
));
153 static void set_at_unsigned
PARAMS ((int *counter
, int reg
));
154 static void check_absolute_expr
PARAMS ((struct mips_cl_insn
* ip
,
155 expressionS
* expr
));
156 static void load_register
PARAMS ((int *counter
,
157 struct mips_cl_insn
* ip
,
158 int reg
, expressionS
* ep
));
159 static void macro
PARAMS ((struct mips_cl_insn
* ip
));
160 static void mips_ip
PARAMS ((char *str
, struct mips_cl_insn
* ip
));
161 static int my_getSmallExpression
PARAMS ((expressionS
* ep
, char *str
));
162 static void my_getExpression
PARAMS ((expressionS
* ep
, char *str
));
163 static symbolS
*get_symbol
PARAMS ((void));
164 static void mips_align
PARAMS ((int to
, int fill
));
165 static void s_align
PARAMS ((int));
166 static void s_stringer
PARAMS ((int));
167 static void s_change_sec
PARAMS ((int));
168 static void s_cons
PARAMS ((int));
169 static void s_err
PARAMS ((int));
170 static void s_extern
PARAMS ((int));
171 static void s_float_cons
PARAMS ((int));
172 static void s_option
PARAMS ((int));
173 static void s_mipsset
PARAMS ((int));
174 static void s_mips_space
PARAMS ((int));
176 static void md_obj_begin
PARAMS ((void));
177 static void md_obj_end
PARAMS ((void));
178 static long get_number
PARAMS ((void));
179 static void s_ent
PARAMS ((int));
180 static void s_mipsend
PARAMS ((int));
181 static void s_file
PARAMS ((int));
182 static void s_frame
PARAMS ((int));
183 static void s_loc
PARAMS ((int));
184 static void s_mask
PARAMS ((char));
189 The following pseudo-ops from the Kane and Heinrich MIPS book
190 should be defined here, but are currently unsupported: .alias,
191 .galive, .gjaldef, .gjrlive, .livereg, .noalias.
193 The following pseudo-ops from the Kane and Heinrich MIPS book are
194 specific to the type of debugging information being generated, and
195 should be defined by the object format: .aent, .begin, .bend,
196 .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp,
199 The following pseudo-ops from the Kane and Heinrich MIPS book are
200 not MIPS CPU specific, but are also not specific to the object file
201 format. This file is probably the best place to define them, but
202 they are not currently supported: .asm0, .endr, .lab, .repeat,
203 .struct, .weakext. */
205 const pseudo_typeS md_pseudo_table
[] =
207 /* MIPS specific pseudo-ops. */
208 {"option", s_option
, 0},
209 {"set", s_mipsset
, 0},
210 {"rdata", s_change_sec
, 'r',},
211 {"sdata", s_change_sec
, 's',},
213 /* Relatively generic pseudo-ops that happen to be used on MIPS
215 {"asciiz", s_stringer
, 1},
216 {"bss", s_change_sec
, 'b'},
220 /* These pseudo-ops are defined in read.c, but must be overridden
221 here for one reason or another. */
222 {"align", s_align
, 0},
223 {"ascii", s_stringer
, 0},
224 {"asciz", s_stringer
, 1},
226 {"data", s_change_sec
, 'd'},
227 {"double", s_float_cons
, 'd'},
228 {"extern", s_extern
, 0},
229 {"float", s_float_cons
, 'f'},
230 {"space", s_mips_space
, 0},
231 {"text", s_change_sec
, 't'},
235 /* These pseudo-ops should be defined by the object file format.
236 However, ECOFF is the only format which currently defines them,
237 so we have versions here for a.out. */
239 {"end", s_mipsend
, 0},
242 {"fmask", s_ignore
, 'F'},
243 {"frame", s_ignore
, 0},
244 {"loc", s_ignore
, 0},
245 {"mask", s_ignore
, 'R'},
246 {"verstamp", s_ignore
, 0},
253 const relax_typeS md_relax_table
[] =
259 static char *expr_end
;
261 static expressionS imm_expr
;
262 static expressionS offset_expr
;
263 static bfd_reloc_code_real_type imm_reloc
;
264 static bfd_reloc_code_real_type offset_reloc
;
267 * This function is called once, at assembler startup time. It should
268 * set up all the tables, etc. that the MD part of the assembler will need.
273 register char *retval
= NULL
;
274 register unsigned int i
= 0;
276 if ((op_hash
= hash_new ()) == NULL
)
278 as_fatal ("Virtual memory exhausted");
280 for (i
= 0; i
< NUMOPCODES
;)
282 const char *name
= mips_opcodes
[i
].name
;
284 retval
= hash_insert (op_hash
, name
, &mips_opcodes
[i
]);
285 if (retval
!= NULL
&& *retval
!= '\0')
287 fprintf (stderr
, "internal error: can't hash `%s': %s\n",
288 mips_opcodes
[i
].name
, retval
);
289 as_fatal ("Broken assembler. No assembly attempted.");
293 if ((mips_opcodes
[i
].match
& mips_opcodes
[i
].mask
) !=
294 mips_opcodes
[i
].match
)
296 fprintf (stderr
, "internal error: bad opcode: `%s' \"%s\"\n",
297 mips_opcodes
[i
].name
, mips_opcodes
[i
].args
);
298 as_fatal ("Broken assembler. No assembly attempted.");
302 while ((i
< NUMOPCODES
) && !strcmp (mips_opcodes
[i
].name
, name
));
305 mips_no_prev_insn ();
324 struct mips_cl_insn insn
;
329 /* set the default alignment for the text section (2**2) */
330 /* This should go in md_begin but text_section isn't initialized then */
331 record_alignment (text_section
, 2);
333 bfd_set_gp_size (stdoutput
, g_switch_value
);
338 imm_expr
.X_op
= O_absent
;
339 offset_expr
.X_op
= O_absent
;
341 mips_ip (str
, &insn
);
344 as_bad ("%s `%s'", insn_error
, str
);
347 if (insn
.insn_mo
->pinfo
== INSN_MACRO
)
353 if (imm_expr
.X_op
!= O_absent
)
354 append_insn (&insn
, &imm_expr
, imm_reloc
);
355 else if (offset_expr
.X_op
!= O_absent
)
356 append_insn (&insn
, &offset_expr
, offset_reloc
);
358 append_insn (&insn
, NULL
, BFD_RELOC_UNUSED
);
362 /* See whether instruction IP reads register REG. If FPR is non-zero,
363 REG is a floating point register. */
366 insn_uses_reg (ip
, reg
, fpr
)
367 struct mips_cl_insn
*ip
;
371 /* Don't report on general register 0, since it never changes. */
372 if (! fpr
&& reg
== 0)
377 /* If we are called with either $f0 or $f1, we must check $f0.
378 This is not optimal, because it will introduce an unnecessary
379 NOP between "lwc1 $f0" and "swc1 $f1". To fix this we would
380 need to distinguish reading both $f0 and $f1 or just one of
381 them. Note that we don't have to check the other way,
382 because there is no instruction that sets both $f0 and $f1
383 and requires a delay. */
384 if ((ip
->insn_mo
->pinfo
& INSN_READ_FPR_S
)
385 && ((ip
->insn_opcode
>> OP_SH_FS
) & OP_MASK_FS
) == (reg
&~ 1))
387 if ((ip
->insn_mo
->pinfo
& INSN_READ_FPR_T
)
388 && ((ip
->insn_opcode
>> OP_SH_FT
) & OP_MASK_FT
) == (reg
&~ 1))
393 if ((ip
->insn_mo
->pinfo
& INSN_READ_GPR_S
)
394 && ((ip
->insn_opcode
>> OP_SH_RS
) & OP_MASK_RS
) == reg
)
396 if ((ip
->insn_mo
->pinfo
& INSN_READ_GPR_T
)
397 && ((ip
->insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
) == reg
)
404 #define ALIGN_ERR "Attempt to assemble instruction onto non word boundary."
405 #define ALIGN_ERR2 "GAS doesn't do implicit alignment; use .align directive."
409 * Output an instruction.
412 append_insn (ip
, address_expr
, reloc_type
)
413 struct mips_cl_insn
*ip
;
414 expressionS
*address_expr
;
415 bfd_reloc_code_real_type reloc_type
;
421 if (! mips_noreorder
)
423 /* If the previous insn required any delay slots, see if we need
424 to insert a NOP or two. There are six kinds of possible
425 hazards, of which an instruction can have at most one type.
427 (2) an unconditional branch delay
428 (3) a conditional branch delay
429 (4) a generic coprocessor delay
430 (5) a coprocessor condition code delay
431 (6) a HI/LO special register delay
433 There are a lot of optimizations we could do that we don't.
434 In particular, we do not, in general, reorder instructions.
435 If you use gcc with optimization, it will reorder
436 instructions and generally do much more optimization then we
437 do here; repeating all that work in the assembler would only
438 benefit hand written assembly code, and does not seem worth
441 /* This is how a NOP is emitted. */
442 #define emit_nop() md_number_to_chars (frag_more (4), 0, 4)
444 /* The previous insn might require a delay slot, depending upon
445 the contents of the current insn. */
446 if (prev_insn
.insn_mo
->pinfo
& INSN_LOAD_DELAY
)
448 /* A load delay. All load delays delay the use of general
449 register rt for one instruction. */
450 know (prev_insn
.insn_mo
->pinfo
& INSN_WRITE_GPR_T
);
451 if (insn_uses_reg (ip
,
452 (prev_insn
.insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
,
456 else if (prev_insn
.insn_mo
->pinfo
& INSN_COPROC_DELAY
)
458 /* A generic coprocessor delay. The previous instruction
459 modified a coprocessor general or control register. If
460 it modified a control register, we need to avoid any
461 coprocessor instruction (this is probably not always
462 required, but it sometimes is). If it modified a general
463 register, we avoid using that register.
465 This case is not handled very well. There is no special
466 knowledge of CP0 handling, and the coprocessors other
467 than the floating point unit are not distinguished at
469 if (prev_insn
.insn_mo
->pinfo
& INSN_WRITE_FPR_T
)
471 if (insn_uses_reg (ip
,
472 ((prev_insn
.insn_opcode
>> OP_SH_RT
)
477 else if (prev_insn
.insn_mo
->pinfo
& INSN_WRITE_FPR_D
)
479 if (insn_uses_reg (ip
,
480 ((prev_insn
.insn_opcode
>> OP_SH_RD
)
487 /* We don't know exactly what the previous instruction
488 does. If the current instruction uses a coprocessor
489 register, we must insert a NOP. If previous
490 instruction may set the condition codes, and the
491 current instruction uses them, we must insert two
493 if ((prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
)
494 && (ip
->insn_mo
->pinfo
& INSN_READ_COND_CODE
))
496 else if (ip
->insn_mo
->pinfo
& INSN_COP
)
500 else if (prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
)
502 /* The previous instruction sets the coprocessor condition
503 codes, but does not require a general coprocessor delay
504 (this means it is a floating point comparison
505 instruction). If this instruction uses the condition
506 codes, we need to insert a single NOP. */
507 if (ip
->insn_mo
->pinfo
& INSN_READ_COND_CODE
)
510 else if (prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
)
512 /* The previous instruction reads the LO register; if the
513 current instruction writes to the LO register, we must
515 if (ip
->insn_mo
->pinfo
& INSN_WRITE_LO
)
518 else if (prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
520 /* The previous instruction reads the HI register; if the
521 current instruction writes to the HI register, we must
523 if (ip
->insn_mo
->pinfo
& INSN_WRITE_HI
)
527 /* There are two cases which require two intervening
528 instructions: 1) setting the condition codes using a move to
529 coprocessor instruction which requires a general coprocessor
530 delay and then reading the condition codes 2) reading the HI
531 or LO register and then writing to it. If we are not already
532 emitting a NOP instruction, we must check for these cases
533 compared to the instruction previous to the previous
536 && (((prev_prev_insn
.insn_mo
->pinfo
& INSN_COPROC_DELAY
)
537 && (prev_prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
)
538 && (ip
->insn_mo
->pinfo
& INSN_READ_COND_CODE
))
539 || ((prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
)
540 && (ip
->insn_mo
->pinfo
& INSN_WRITE_LO
))
541 || ((prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
542 && (ip
->insn_mo
->pinfo
& INSN_WRITE_HI
))))
545 /* Now emit the right number of NOP instructions. */
551 if (insn_label
!= NULL
)
553 assert (S_GET_SEGMENT (insn_label
) == now_seg
);
554 insn_label
->sy_frag
= frag_now
;
555 S_SET_VALUE (insn_label
, frag_now_fix ());
562 /* This is testing the address of the frag, not the alignment of
563 the instruction in the current section. */
571 if (address_expr
!= NULL
)
573 if (address_expr
->X_op
== O_constant
)
578 ip
->insn_opcode
|= address_expr
->X_add_number
;
582 ip
->insn_opcode
|= address_expr
->X_add_number
& 0xffff;
585 case BFD_RELOC_MIPS_JMP
:
586 case BFD_RELOC_16_PCREL_S2
:
595 assert (reloc_type
!= BFD_RELOC_UNUSED
);
597 fixp
= fix_new_exp (frag_now
, f
- frag_now
->fr_literal
, 4,
599 reloc_type
== BFD_RELOC_16_PCREL_S2
,
604 md_number_to_chars (f
, ip
->insn_opcode
, 4);
606 if (! mips_noreorder
)
608 /* Filling the branch delay slot is more complex. We try to
609 switch the branch with the previous instruction, which we can
610 do if the previous instruction does not set up a condition
611 that the branch tests and if the branch is not itself the
612 target of any branch. */
613 if ((ip
->insn_mo
->pinfo
& INSN_UNCOND_BRANCH_DELAY
)
614 || (ip
->insn_mo
->pinfo
& INSN_COND_BRANCH_DELAY
))
616 /* If we had to emit any NOP instructions, then we already
617 know we can not swap. */
619 /* If we don't even know the previous insn, we can not
622 /* If the previous insn is already in a branch delay
623 slot, then we can not swap. */
624 || prev_insn_is_delay_slot
625 /* If the branch is itself the target of a branch, we
626 can not swap. We cheat on this; all we check for is
627 whether there is a label on this instruction. If
628 there are any branches to anything other than a
629 label, users must use .set noreorder. */
630 || insn_label
!= NULL
631 /* If the branch reads the condition codes, we don't
632 even try to swap, because in the sequence
637 we can not swap, and I don't feel like handling that
639 || (ip
->insn_mo
->pinfo
& INSN_READ_COND_CODE
)
640 /* We can not swap with an instruction that requires a
641 delay slot, becase the target of the branch might
642 interfere with that instruction. */
643 || (prev_insn
.insn_mo
->pinfo
646 | INSN_WRITE_COND_CODE
649 /* We can not swap with a branch instruction. */
650 || (prev_insn
.insn_mo
->pinfo
651 & (INSN_UNCOND_BRANCH_DELAY
| INSN_COND_BRANCH_DELAY
))
652 /* If the branch reads a register that the previous
653 instruction sets, we can not swap. */
654 || ((prev_insn
.insn_mo
->pinfo
& INSN_WRITE_GPR_T
)
655 && insn_uses_reg (ip
,
656 ((prev_insn
.insn_opcode
>> OP_SH_RT
)
659 || ((prev_insn
.insn_mo
->pinfo
& INSN_WRITE_GPR_D
)
660 && insn_uses_reg (ip
,
661 ((prev_insn
.insn_opcode
>> OP_SH_RD
)
664 /* If the branch writes a register that the previous
665 instruction reads, we can not swap (we know that
666 branches only write to RD or to $31). */
667 || ((ip
->insn_mo
->pinfo
& INSN_WRITE_GPR_D
)
668 && insn_uses_reg (&prev_insn
,
669 ((ip
->insn_opcode
>> OP_SH_RD
)
672 || ((ip
->insn_mo
->pinfo
& INSN_WRITE_GPR_31
)
673 && insn_uses_reg (&prev_insn
, 31, 0))
674 /* If the previous previous instruction has a load
675 delay, and sets a register that the branch reads, we
677 || ((prev_prev_insn
.insn_mo
->pinfo
& INSN_LOAD_DELAY
)
678 && insn_uses_reg (ip
,
679 ((prev_prev_insn
.insn_opcode
>> OP_SH_RT
)
683 /* We could do even better for unconditional branches to
684 portions of this object file; we could pick up the
685 instruction at the destination, put it in the delay
686 slot, and bump the destination address. */
688 /* Update the previous insn information. */
689 prev_prev_insn
= *ip
;
690 prev_insn
.insn_mo
= &dummy_opcode
;
697 /* It looks like we can actually do the swap. */
698 prev_f
= prev_insn_frag
->fr_literal
+ prev_insn_where
;
699 memcpy (temp
, prev_f
, 4);
700 memcpy (prev_f
, f
, 4);
704 prev_insn_fixp
->fx_frag
= frag_now
;
705 prev_insn_fixp
->fx_where
= f
- frag_now
->fr_literal
;
709 fixp
->fx_frag
= prev_insn_frag
;
710 fixp
->fx_where
= prev_insn_where
;
712 /* Update the previous insn information; leave prev_insn
714 prev_prev_insn
= *ip
;
716 prev_insn_is_delay_slot
= 1;
718 /* If that was an unconditional branch, forget the previous
720 if (ip
->insn_mo
->pinfo
& INSN_UNCOND_BRANCH_DELAY
)
722 prev_prev_insn
.insn_mo
= &dummy_opcode
;
723 prev_insn
.insn_mo
= &dummy_opcode
;
728 /* Update the previous insn information. */
730 prev_prev_insn
.insn_mo
= &dummy_opcode
;
732 prev_prev_insn
= prev_insn
;
735 /* Any time we see a branch, we always fill the delay slot
736 immediately; since this insn is not a branch, we know it
737 is not in a delay slot. */
738 prev_insn_is_delay_slot
= 0;
741 prev_insn_frag
= frag_now
;
742 prev_insn_where
= f
- frag_now
->fr_literal
;
743 prev_insn_fixp
= fixp
;
747 /* We just output an insn, so the next one doesn't have a label. */
751 /* This function forgets that there was any previous instruction or
757 prev_insn
.insn_mo
= &dummy_opcode
;
758 prev_prev_insn
.insn_mo
= &dummy_opcode
;
760 prev_insn_is_delay_slot
= 0;
764 /* This function must be called whenever we turn on noreorder or emit
765 something other than instructions. It inserts any NOPS which might
766 be needed by the previous instruction, and clears the information
767 kept for the previous instructions. */
772 if (! mips_noreorder
)
777 if (prev_insn
.insn_mo
->pinfo
& ANY_DELAY
)
780 if ((prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
)
781 || (prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
782 || (prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
))
785 else if ((prev_prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
)
786 || (prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
787 || (prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
))
792 if (insn_label
!= NULL
)
794 assert (S_GET_SEGMENT (insn_label
) == now_seg
);
795 insn_label
->sy_frag
= frag_now
;
796 S_SET_VALUE (insn_label
, frag_now_fix ());
799 mips_no_prev_insn ();
803 /* Return 1 if an expression can be accessed via the GP register. */
814 sym
= ep
->X_add_symbol
;
815 if (sym
== (symbolS
*) NULL
816 || ep
->X_op_symbol
!= (symbolS
*) NULL
)
819 /* Certain symbols can not be referenced off the GP, although it
820 appears as though they can. */
821 symname
= S_GET_NAME (sym
);
822 if (symname
!= (const char *) NULL
823 && (strcmp (symname
, "eprol") == 0
824 || strcmp (symname
, "etext") == 0
825 || strcmp (symname
, "_gp") == 0
826 || strcmp (symname
, "edata") == 0
827 || strcmp (symname
, "_fbss") == 0
828 || strcmp (symname
, "_fdata") == 0
829 || strcmp (symname
, "_ftext") == 0
830 || strcmp (symname
, "end") == 0))
832 if (! S_IS_DEFINED (sym
)
833 && S_GET_VALUE (sym
) != 0
834 && S_GET_VALUE (sym
) <= g_switch_value
)
836 segname
= segment_name (S_GET_SEGMENT (ep
->X_add_symbol
));
837 return (strcmp (segname
, ".sdata") == 0
838 || strcmp (segname
, ".sbss") == 0);
839 #else /* ! defined (OBJ_ECOFF) */
840 /* The GP register is only used for ECOFF. */
842 #endif /* ! defined (OBJ_ECOFF) */
845 /* Build an instruction created by a macro expansion. This is passed
846 a pointer to the count of instructions created so far, an
847 expression, the name of the instruction to build, an operand format
848 string, and corresponding arguments. */
852 macro_build (int *counter
,
857 #else /* ! defined (NO_STDARG) */
859 macro_build (counter
, ep
, name
, fmt
, va_alist
)
865 #endif /* ! defined (NO_STDARG) */
867 struct mips_cl_insn insn
;
868 bfd_reloc_code_real_type r
;
872 va_start (args
, fmt
);
878 * If the macro is about to expand into a second instruction,
879 * print a warning if needed. We need to pass ip as a parameter
880 * to generate a better warning message here...
882 if (mips_warn_about_macros
&& *counter
== 1)
883 as_warn ("Macro instruction expanded into multiple instructions");
885 *counter
+= 1; /* bump instruction counter */
887 r
= BFD_RELOC_UNUSED
;
888 insn
.insn_mo
= (struct mips_opcode
*) hash_find (op_hash
, name
);
889 assert (insn
.insn_mo
);
890 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
892 while (strcmp (fmt
, insn
.insn_mo
->args
) != 0)
895 assert (insn
.insn_mo
->name
);
896 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
898 assert (insn
.insn_mo
->pinfo
!= INSN_MACRO
);
899 insn
.insn_opcode
= insn
.insn_mo
->match
;
915 insn
.insn_opcode
|= va_arg (args
, int) << 16;
921 insn
.insn_opcode
|= va_arg (args
, int) << 16;
926 insn
.insn_opcode
|= va_arg (args
, int) << 11;
931 insn
.insn_opcode
|= va_arg (args
, int) << 11;
935 insn
.insn_opcode
|= va_arg (args
, int) << 6;
939 insn
.insn_opcode
|= va_arg (args
, int) << 6;
943 insn
.insn_opcode
|= va_arg (args
, int) << 6;
950 insn
.insn_opcode
|= va_arg (args
, int) << 21;
962 * This allows macro() to pass an immediate expression for
963 * creating short branches without creating a symbol.
964 * Note that the expression still might come from the assembly
965 * input, in which case the value is not checked for range nor
966 * is a relocation entry generated (yuck).
968 if (ep
->X_op
== O_constant
)
970 insn
.insn_opcode
|= (ep
->X_add_number
>> 2) & 0xffff;
974 r
= BFD_RELOC_16_PCREL_S2
;
983 assert (r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
985 /* Use GP relative addressing if possible. */
986 if (r
== BFD_RELOC_LO16
987 && gp_reference (ep
))
988 r
= BFD_RELOC_MIPS_GPREL
;
990 append_insn (&insn
, ep
, r
);
994 * Generate a "lui" instruction.
997 macro_build_lui (counter
, ep
, regnum
)
1002 expressionS high_expr
;
1003 struct mips_cl_insn insn
;
1004 bfd_reloc_code_real_type r
;
1005 CONST
char *name
= "lui";
1006 CONST
char *fmt
= "t,u";
1010 if (high_expr
.X_op
== O_constant
)
1012 /* we can compute the instruction now without a relocation entry */
1013 if (high_expr
.X_add_number
& 0x8000)
1014 high_expr
.X_add_number
+= 0x10000;
1015 high_expr
.X_add_number
=
1016 ((unsigned long) high_expr
.X_add_number
>> 16) & 0xffff;
1017 r
= BFD_RELOC_UNUSED
;
1020 r
= BFD_RELOC_HI16_S
;
1023 * If the macro is about to expand into a second instruction,
1024 * print a warning if needed. We need to pass ip as a parameter
1025 * to generate a better warning message here...
1027 if (mips_warn_about_macros
&& *counter
== 1)
1028 as_warn ("Macro instruction expanded into multiple instructions");
1030 *counter
+= 1; /* bump instruction counter */
1032 insn
.insn_mo
= (struct mips_opcode
*) hash_find (op_hash
, name
);
1033 assert (insn
.insn_mo
);
1034 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
1035 assert (strcmp (fmt
, insn
.insn_mo
->args
) == 0);
1037 insn
.insn_opcode
= insn
.insn_mo
->match
| (regnum
<< 16);
1038 if (r
== BFD_RELOC_UNUSED
)
1040 insn
.insn_opcode
|= high_expr
.X_add_number
;
1041 append_insn (&insn
, NULL
, r
);
1044 append_insn (&insn
, &high_expr
, r
);
1048 * Generates code to set the $at register to true (one)
1049 * if reg is less than the immediate expression.
1052 set_at (counter
, reg
)
1057 switch (imm_expr
.X_add_number
& 0xffff8000)
1061 macro_build (counter
, &imm_expr
, "slti", "t,r,j", AT
, reg
);
1065 macro_build (counter
, &imm_expr
, "ori", "t,r,i", AT
, 0);
1069 macro_build_lui (counter
, &imm_expr
, AT
);
1070 if (imm_expr
.X_add_number
& 0xffff)
1071 macro_build (counter
, &imm_expr
, "addiu", "t,r,j", AT
, AT
);
1073 macro_build (counter
, NULL
, "slt", "d,v,t", AT
, reg
, AT
);
1076 /* set_at_unsigned()
1077 * Generates code to set the $at register to true (one)
1078 * if reg is less than the immediate expression.
1079 * Unsigned comparison is perfomed.
1082 set_at_unsigned (counter
, reg
)
1087 switch (imm_expr
.X_add_number
& 0xffff8000)
1091 macro_build (counter
, &imm_expr
, "sltiu", "t,r,j", AT
, reg
);
1095 macro_build (counter
, &imm_expr
, "ori", "t,r,i", AT
, 0);
1099 macro_build_lui (counter
, &imm_expr
, AT
);
1100 if (imm_expr
.X_add_number
& 0xffff)
1101 macro_build (counter
, &imm_expr
, "addiu", "t,r,j", AT
, AT
);
1103 macro_build (counter
, NULL
, "sltu", "d,v,t", AT
, reg
, AT
);
1107 check_absolute_expr (ip
, expr
)
1108 struct mips_cl_insn
*ip
;
1112 if (expr
->X_op
!= O_constant
)
1113 as_warn ("Instruction %s requires absolute expression", ip
->insn_mo
->name
);
1117 * This routine generates the least number of instructions neccessary to load
1118 * an absolute expression value into a register.
1121 load_register (counter
, ip
, reg
, ep
)
1123 struct mips_cl_insn
*ip
;
1127 switch (ep
->X_add_number
& 0xffff8000)
1131 macro_build (counter
, ep
, "addiu", "t,r,j", reg
, 0);
1135 macro_build (counter
, ep
, "ori", "t,r,i", reg
, 0);
1139 macro_build_lui (counter
, ep
, reg
);
1140 if (ep
->X_add_number
& 0xffff)
1141 macro_build (counter
, ep
, "addiu", "t,r,j", reg
, reg
);
1148 * This routine implements the seemingly endless macro or synthesized
1149 * instructions and addressing modes in the mips assembly language. Many
1150 * of these macros are simple and are similar to each other. These could
1151 * probably be handled by some kind of table or grammer aproach instead of
1152 * this verbose method. Others are not simple macros but are more like
1153 * optimizing code generation.
1154 * One interesting optimization is when several store macros appear
1155 * consecutivly that would load AT with the upper half of the same address.
1156 * The ensuing load upper instructions are ommited. This implies some kind
1157 * of global optimization. We currently only optimize within a single macro.
1158 * For many of the load and store macros if the address is specified as a
1159 * constant expression in the first 64k of memory (ie ld $2,0x4000c) we
1160 * first load register 'at' with zero and use it as the base register. The
1161 * mips assembler simply uses register $zero. Just one tiny optimization
1166 struct mips_cl_insn
*ip
;
1168 register int treg
, sreg
, dreg
, breg
;
1177 treg
= (ip
->insn_opcode
>> 16) & 0x1f;
1178 dreg
= (ip
->insn_opcode
>> 11) & 0x1f;
1179 sreg
= breg
= (ip
->insn_opcode
>> 21) & 0x1f;
1180 mask
= ip
->insn_mo
->mask
;
1182 expr1
.X_op
= O_constant
;
1183 expr1
.X_op_symbol
= NULL
;
1184 expr1
.X_add_symbol
= NULL
;
1185 expr1
.X_add_number
= 1;
1192 Note: mips algorithm requires the move in the delay slot.
1193 <main>: bgez $a0,0x4001bc <main+12>
1194 <main+4>: move v0,$a0
1195 <main+8>: sub v0,$zero,$a0
1199 mips_emit_delays ();
1202 expr1
.X_add_number
= 8;
1203 macro_build (&icnt
, &expr1
, "bgez", "s,p", sreg
);
1204 macro_build (&icnt
, NULL
, "move", "d,s", dreg
, sreg
, 0);
1205 macro_build (&icnt
, NULL
, mask
== M_ABS
? "sub" : "subu", "d,v,t",
1213 switch (imm_expr
.X_add_number
& 0xffff8000)
1217 macro_build (&icnt
, &imm_expr
,
1218 mask
== M_ADD_I
? "addi" : "addiu", "t,r,j", treg
, sreg
);
1222 macro_build (&icnt
, &imm_expr
, "ori", "t,r,i", AT
, 0);
1226 macro_build_lui (&icnt
, &imm_expr
, AT
);
1227 if (imm_expr
.X_add_number
& 0xffff)
1228 macro_build (&icnt
, &imm_expr
, "addiu", "t,r,j", AT
, AT
);
1231 macro_build (&icnt
, NULL
,
1232 mask
== M_ADD_I
? "add" : "addu", "d,v,t", treg
, sreg
, AT
);
1239 switch (imm_expr
.X_add_number
& 0xffff8000)
1246 macro_build (&icnt
, &imm_expr
, "andi", "t,r,i", treg
, sreg
);
1249 macro_build (&icnt
, &imm_expr
, "ori", "t,r,i", treg
, sreg
);
1252 macro_build (&icnt
, &imm_expr
, "ori", "t,r,i", treg
, sreg
);
1253 macro_build (&icnt
, &imm_expr
, "nor", "d,v,t", treg
, treg
, 0);
1256 macro_build (&icnt
, &imm_expr
, "xori", "t,r,i", treg
, sreg
);
1263 macro_build (&icnt
, &imm_expr
, "addiu", "t,r,j", AT
, 0);
1267 macro_build_lui (&icnt
, &imm_expr
, AT
);
1268 if (imm_expr
.X_add_number
& 0xffff)
1269 macro_build (&icnt
, &imm_expr
, "addiu", "t,r,j", AT
, AT
);
1274 macro_build (&icnt
, NULL
, "and", "d,v,t", treg
, sreg
, AT
);
1277 macro_build (&icnt
, NULL
, "or", "d,v,t", treg
, sreg
, AT
);
1280 macro_build (&icnt
, NULL
, "nor", "d,v,t", treg
, sreg
, AT
);
1283 macro_build (&icnt
, NULL
, "xor", "d,v,t", treg
, sreg
, AT
);
1292 if (imm_expr
.X_add_number
== 0)
1294 macro_build (&icnt
, &offset_expr
, mask
== M_BEQ_I
? "beq" : "bne",
1298 load_register (&icnt
, ip
, AT
, &imm_expr
);
1299 macro_build (&icnt
, &offset_expr
, mask
== M_BEQ_I
? "beq" : "bne",
1306 macro_build (&icnt
, &offset_expr
, "bgez", "s,p", sreg
);
1311 macro_build (&icnt
, &offset_expr
, "blez", "s,p", treg
);
1314 macro_build (&icnt
, NULL
, "slt", "d,v,t", AT
, sreg
, treg
);
1315 macro_build (&icnt
, &offset_expr
, "beq", "s,t,p", AT
, 0);
1319 /* check for > max integer */
1320 if (imm_expr
.X_add_number
== 0x7fffffff)
1323 /* result is always false */
1324 as_warn ("Branch %s is always false (nop)", ip
->insn_mo
->name
);
1325 macro_build (&icnt
, NULL
, "nop", "", 0);
1328 imm_expr
.X_add_number
++;
1332 if (imm_expr
.X_add_number
== 0)
1334 macro_build (&icnt
, &offset_expr
, "bgez", "s,p", sreg
);
1337 if (imm_expr
.X_add_number
== 1)
1339 macro_build (&icnt
, &offset_expr
, "bgtz", "s,p", sreg
);
1342 if (imm_expr
.X_add_number
== 0x80000000)
1345 /* result is always true */
1346 as_warn ("Branch %s is always true", ip
->insn_mo
->name
);
1347 macro_build (&icnt
, &offset_expr
, "b", "p");
1350 set_at (&icnt
, sreg
);
1351 macro_build (&icnt
, &offset_expr
, "beq", "s,t,p", AT
, 0);
1359 macro_build (&icnt
, &offset_expr
, "beq", "s,t,p", 0, treg
);
1362 macro_build (&icnt
, NULL
, "sltu", "d,v,t", AT
, sreg
, treg
);
1363 macro_build (&icnt
, &offset_expr
, "beq", "s,t,p", AT
, 0);
1367 if (sreg
== 0 || imm_expr
.X_add_number
== 0xffffffff)
1369 imm_expr
.X_add_number
++;
1373 if (imm_expr
.X_add_number
== 0)
1375 if (imm_expr
.X_add_number
== 1)
1377 macro_build (&icnt
, &offset_expr
, "bne", "s,t,p", sreg
, 0);
1380 set_at_unsigned (&icnt
, sreg
);
1381 macro_build (&icnt
, &offset_expr
, "beq", "s,t,p", AT
, 0);
1387 macro_build (&icnt
, &offset_expr
, "bgtz", "s,p", sreg
);
1392 macro_build (&icnt
, &offset_expr
, "bltz", "s,p", treg
);
1395 macro_build (&icnt
, NULL
, "slt", "d,v,t", AT
, treg
, sreg
);
1396 macro_build (&icnt
, &offset_expr
, "bne", "s,t,p", AT
, 0);
1402 macro_build (&icnt
, &offset_expr
, "bne", "s,t,p", sreg
, 0);
1407 macro_build (&icnt
, NULL
, "sltu", "d,v,t", AT
, treg
, sreg
);
1408 macro_build (&icnt
, &offset_expr
, "bne", "s,t,p", AT
, 0);
1414 macro_build (&icnt
, &offset_expr
, "blez", "s,p", sreg
);
1419 macro_build (&icnt
, &offset_expr
, "bgez", "s,p", treg
);
1422 macro_build (&icnt
, NULL
, "slt", "d,v,t", AT
, treg
, sreg
);
1423 macro_build (&icnt
, &offset_expr
, "beq", "s,t,p", AT
, 0);
1427 if (imm_expr
.X_add_number
== 0x7fffffff)
1429 imm_expr
.X_add_number
++;
1433 if (imm_expr
.X_add_number
== 0)
1435 macro_build (&icnt
, &offset_expr
, "bltz", "s,p", sreg
);
1438 if (imm_expr
.X_add_number
== 1)
1440 macro_build (&icnt
, &offset_expr
, "blez", "s,p", sreg
);
1443 set_at (&icnt
, sreg
);
1444 macro_build (&icnt
, &offset_expr
, "bne", "s,t,p", AT
, 0);
1450 macro_build (&icnt
, &offset_expr
, "beq", "s,t,p", sreg
, 0);
1455 macro_build (&icnt
, NULL
, "sltu", "d,v,t", AT
, treg
, sreg
);
1456 macro_build (&icnt
, &offset_expr
, "beq", "s,t,p", AT
, 0);
1460 if (sreg
== 0 || imm_expr
.X_add_number
== 0xffffffff)
1462 imm_expr
.X_add_number
++;
1466 if (imm_expr
.X_add_number
== 0)
1468 if (imm_expr
.X_add_number
== 1)
1470 macro_build (&icnt
, &offset_expr
, "beq", "s,t,p", sreg
, 0);
1473 set_at_unsigned (&icnt
, sreg
);
1474 macro_build (&icnt
, &offset_expr
, "bne", "s,t,p", AT
, 0);
1480 macro_build (&icnt
, &offset_expr
, "bltz", "s,p", sreg
);
1485 macro_build (&icnt
, &offset_expr
, "bgtz", "s,p", treg
);
1488 macro_build (&icnt
, NULL
, "slt", "d,v,t", AT
, sreg
, treg
);
1489 macro_build (&icnt
, &offset_expr
, "bne", "s,t,p", AT
, 0);
1497 macro_build (&icnt
, &offset_expr
, "bne", "s,t,p", 0, treg
);
1500 macro_build (&icnt
, NULL
, "sltu", "d,v,t", AT
, sreg
, treg
);
1501 macro_build (&icnt
, &offset_expr
, "bne", "s,t,p", AT
, 0);
1508 as_warn ("Divide by zero.");
1509 macro_build (&icnt
, NULL
, "break", "c", 7);
1513 mips_emit_delays ();
1515 macro_build (&icnt
, NULL
, "div", "s,t", sreg
, treg
);
1516 expr1
.X_add_number
= 8;
1517 macro_build (&icnt
, &expr1
, "bne", "s,t,p", treg
, 0);
1518 macro_build (&icnt
, NULL
, "nop", "", 0);
1519 macro_build (&icnt
, NULL
, "break", "c", 7);
1520 expr1
.X_add_number
= -1;
1521 macro_build (&icnt
, &expr1
, "addiu", "t,r,j", AT
, 0);
1522 expr1
.X_add_number
= 16;
1523 macro_build (&icnt
, &expr1
, "bne", "s,t,p", treg
, AT
);
1524 expr1
.X_add_number
= 0x80000000;
1525 macro_build_lui (&icnt
, &expr1
, AT
);
1526 expr1
.X_add_number
= 8;
1527 macro_build (&icnt
, &expr1
, "bne", "s,t,p", sreg
, AT
);
1528 macro_build (&icnt
, NULL
, "nop", "", 0);
1529 macro_build (&icnt
, NULL
, "break", "c", 6);
1531 macro_build (&icnt
, NULL
, mask
== M_DIV_3
? "mflo" : "mfhi", "d", dreg
);
1532 /* with reorder on there will be two implicit nop instructions here. */
1539 if (imm_expr
.X_add_number
== 0)
1541 as_warn ("Divide by zero.");
1542 macro_build (&icnt
, NULL
, "break", "c", 7);
1545 if (imm_expr
.X_add_number
== 1)
1547 if (mask
== (int) M_DIV_3I
|| mask
== (int) M_DIVU_3I
)
1548 macro_build (&icnt
, NULL
, "move", "d,s", dreg
, sreg
);
1550 macro_build (&icnt
, NULL
, "move", "d,s", dreg
, 0);
1554 load_register (&icnt
, ip
, AT
, &imm_expr
);
1555 if (mask
== (int) M_DIV_3I
|| mask
== (int) M_REM_3I
)
1556 macro_build (&icnt
, NULL
, "div", "s,t", sreg
, AT
);
1558 macro_build (&icnt
, NULL
, "divu", "s,t", sreg
, AT
);
1560 if (mask
== (int) M_DIV_3I
|| mask
== (int) M_DIVU_3I
)
1561 macro_build (&icnt
, NULL
, "mflo", "d", dreg
);
1563 macro_build (&icnt
, NULL
, "mfhi", "d", dreg
);
1564 /* two implicit nop's required for mflo or mfhi */
1569 mips_emit_delays ();
1571 macro_build (&icnt
, NULL
, "divu", "s,t", sreg
, treg
);
1572 expr1
.X_add_number
= 8;
1573 macro_build (&icnt
, &expr1
, "bne", "s,t,p", treg
, 0);
1574 macro_build (&icnt
, NULL
, "nop", "", 0);
1575 macro_build (&icnt
, NULL
, "break", "c", 7);
1577 macro_build (&icnt
, NULL
, mask
== M_DIVU_3
? "mflo" : "mfhi", "d", dreg
);
1578 /* with reorder on there will be two implicit nop instructions here. */
1582 if (offset_expr
.X_op
== O_constant
)
1584 load_register (&icnt
, ip
, treg
, &offset_expr
);
1587 if (gp_reference (&offset_expr
))
1588 macro_build (&icnt
, &offset_expr
, "addiu", "t,r,j", treg
, GP
);
1591 macro_build_lui (&icnt
, &offset_expr
, treg
);
1592 macro_build (&icnt
, &offset_expr
, "addiu", "t,r,j", treg
, treg
);
1597 tempreg
= (breg
== treg
) ? AT
: treg
;
1598 if (offset_expr
.X_op
== O_constant
)
1599 load_register (&icnt
, ip
, tempreg
, &offset_expr
);
1600 else if (gp_reference (&offset_expr
))
1601 macro_build (&icnt
, &offset_expr
, "addiu", "t,r,j", tempreg
, GP
);
1604 macro_build_lui (&icnt
, &offset_expr
, tempreg
);
1605 macro_build (&icnt
, &offset_expr
, "addiu", "t,r,j", tempreg
, tempreg
);
1608 macro_build (&icnt
, NULL
, "addu", "d,v,t", treg
, tempreg
, breg
);
1646 if (breg
== treg
|| mask
== M_LWC1_AB
)
1687 if (mask
== M_LWC1_AB
|| mask
== M_SWC1_AB
)
1691 if (gp_reference (&offset_expr
))
1695 macro_build (&icnt
, &offset_expr
, s
, fmt
, treg
, GP
);
1698 macro_build (&icnt
, (expressionS
*) NULL
, "addu", "d,v,t",
1703 macro_build_lui (&icnt
, &offset_expr
, tempreg
);
1705 macro_build (&icnt
, NULL
, "addu", "d,v,t", tempreg
, tempreg
, breg
);
1707 macro_build (&icnt
, &offset_expr
, s
, fmt
, treg
, tempreg
);
1713 load_register (&icnt
, ip
, treg
, &imm_expr
);
1718 0x400370 <main>: lui $at,%hi(foo)
1719 0x400374 <main+4>: lw $v0,%lo(foo)($at)
1720 0x400378 <main+8>: lw $v1,%lo(foo+4)($at)
1725 /* FIXME: I don't think this is used at present, because the 'F'
1726 format character is not supported. When this is supported,
1727 it should use the GP register. */
1728 macro_build_lui (&icnt
, &offset_expr
, AT
);
1729 macro_build (&icnt
, &offset_expr
, "lw", "t,o(b)", treg
, AT
);
1730 offset_expr
.X_add_number
= 4;
1731 macro_build (&icnt
, &offset_expr
, "lw", "t,o(b)", treg
+ 1, AT
);
1736 0x4003a0 <main>: lwc1 $f0,-32752($gp)
1737 0x4003a4 <main+4>: lwc1 $f1,-32748($gp)
1738 0x4003a8 <main+8>: nop
1740 /* FIXME: This is nonsense. It isn't used anyhow. */
1741 sreg
= (ip
->insn_opcode
>> 11) & 0x1f; /* Fs reg */
1742 macro_build (&icnt
, &offset_expr
, "lwc1", "T,o(b)", treg
, AT
);
1743 offset_expr
.X_add_number
= 4;
1744 macro_build (&icnt
, &offset_expr
, "lwc1", "T,o(b)", treg
+ 1, AT
);
1748 /* Even on a big endian machine $fn comes before $fn+1. We have
1749 to adjust when loading from memory. */
1750 macro_build (&icnt
, &offset_expr
, "lwc1", "T,o(b)",
1751 byte_order
== LITTLE_ENDIAN
? treg
: treg
+ 1,
1753 offset_expr
.X_add_number
+= 4;
1754 macro_build (&icnt
, &offset_expr
, "lwc1", "T,o(b)",
1755 byte_order
== LITTLE_ENDIAN
? treg
+ 1 : treg
,
1761 * The MIPS assembler seems to check for X_add_number not
1762 * being double aligned and generating:
1765 * addiu at,at,%lo(foo+1)
1768 * But, the resulting address is the same after relocation so why
1769 * generate the extra instruction?
1771 if (gp_reference (&offset_expr
))
1777 macro_build (&icnt
, &offset_expr
, "addu", "d,v,t", AT
, breg
, GP
);
1783 macro_build_lui (&icnt
, &offset_expr
, AT
);
1785 macro_build (&icnt
, NULL
, "addu", "d,v,t", AT
, AT
, breg
);
1788 /* Even on a big endian machine $fn comes before $fn+1. We have
1789 to adjust when loading from memory. */
1790 macro_build (&icnt
, &offset_expr
, "lwc1", "T,o(b)",
1791 byte_order
== LITTLE_ENDIAN
? treg
: treg
+ 1,
1793 offset_expr
.X_add_number
+= 4;
1794 macro_build (&icnt
, &offset_expr
, "lwc1", "T,o(b)",
1795 byte_order
== LITTLE_ENDIAN
? treg
+ 1 : treg
,
1807 macro_build (&icnt
, &offset_expr
, s
, "t,o(b)", treg
, breg
);
1808 offset_expr
.X_add_number
= 4;
1809 macro_build (&icnt
, &offset_expr
, s
, "t,o(b)", treg
+ 1, breg
);
1830 if (gp_reference (&offset_expr
))
1838 macro_build (&icnt
, (expressionS
*) NULL
, "addu", "d,v,t",
1843 macro_build_lui (&icnt
, &offset_expr
, tempreg
);
1845 macro_build (&icnt
, NULL
, "addu", "d,v,t", tempreg
, tempreg
, breg
);
1847 macro_build (&icnt
, &offset_expr
, s
, "t,o(b)", treg
, tempreg
);
1848 offset_expr
.X_add_number
+= 4;
1849 macro_build (&icnt
, &offset_expr
, s
, "t,o(b)", treg
+ 1, tempreg
);
1855 macro_build (&icnt
, NULL
, "multu", "s,t", sreg
, treg
);
1856 macro_build (&icnt
, NULL
, "mflo", "d", dreg
);
1857 /* two implicit nop's required for mflo */
1862 * The mips assembler some times generates shifts and adds.
1863 * Im not trying to be that fancy. GCC should do this for us
1866 load_register (&icnt
, ip
, AT
, &imm_expr
);
1867 macro_build (&icnt
, NULL
, "mult", "s,t", sreg
, AT
);
1868 macro_build (&icnt
, NULL
, "mflo", "d", dreg
);
1869 /* two implicit nop's required for mflo */
1873 macro_build (&icnt
, NULL
, "subu", "d,v,t", AT
, 0, treg
);
1874 macro_build (&icnt
, NULL
, "srlv", "d,t,s", AT
, sreg
, AT
);
1875 macro_build (&icnt
, NULL
, "sllv", "d,t,s", dreg
, sreg
, treg
);
1876 macro_build (&icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
1880 macro_build (&icnt
, NULL
, "sll", "d,w,<", AT
, sreg
,
1881 imm_expr
.X_add_number
& 0x1f);
1882 macro_build (&icnt
, NULL
, "srl", "d,w,<", dreg
, sreg
,
1883 (0 - imm_expr
.X_add_number
) & 0x1f);
1884 macro_build (&icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
1888 macro_build (&icnt
, NULL
, "subu", "d,v,t", AT
, 0, treg
);
1889 macro_build (&icnt
, NULL
, "sllv", "d,t,s", AT
, sreg
, AT
);
1890 macro_build (&icnt
, NULL
, "srlv", "d,t,s", dreg
, sreg
, treg
);
1891 macro_build (&icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
1895 macro_build (&icnt
, NULL
, "srl", "d,w,<", AT
, sreg
,
1896 imm_expr
.X_add_number
& 0x1f);
1897 macro_build (&icnt
, NULL
, "sll", "d,w,<", dreg
, sreg
,
1898 (0 - imm_expr
.X_add_number
) & 0x1f);
1899 macro_build (&icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
1903 /* Even on a big endian machine $fn comes before $fn+1. We have
1904 to adjust when storing to memory. */
1905 macro_build (&icnt
, &offset_expr
, "swc1", "T,o(b)",
1906 byte_order
== LITTLE_ENDIAN
? treg
: treg
+ 1,
1908 offset_expr
.X_add_number
+= 4;
1909 macro_build (&icnt
, &offset_expr
, "swc1", "T,o(b)",
1910 byte_order
== LITTLE_ENDIAN
? treg
+ 1 : treg
,
1915 if (gp_reference (&offset_expr
))
1921 macro_build (&icnt
, (expressionS
*) NULL
, "addu", "d,v,t",
1928 macro_build_lui (&icnt
, &offset_expr
, AT
);
1930 macro_build (&icnt
, NULL
, "addu", "d,v,t", AT
, AT
, breg
);
1933 /* Even on a big endian machine $fn comes before $fn+1. We have
1934 to adjust when storing to memory. */
1935 macro_build (&icnt
, &offset_expr
, "swc1", "T,o(b)",
1936 byte_order
== LITTLE_ENDIAN
? treg
: treg
+ 1,
1938 offset_expr
.X_add_number
+= 4;
1939 macro_build (&icnt
, &offset_expr
, "swc1", "T,o(b)",
1940 byte_order
== LITTLE_ENDIAN
? treg
+ 1 : treg
,
1948 macro_build (&icnt
, &expr1
, "sltiu", "t,r,j", dreg
, treg
);
1950 macro_build (&icnt
, &expr1
, "sltiu", "t,r,j", dreg
, sreg
);
1953 macro_build (&icnt
, NULL
, "xor", "d,v,t", dreg
, sreg
, treg
);
1954 macro_build (&icnt
, &expr1
, "sltiu", "t,r,j", dreg
, dreg
);
1959 if (imm_expr
.X_add_number
== 0)
1961 macro_build (&icnt
, &expr1
, "sltiu", "t,r,j", dreg
, sreg
);
1966 as_warn ("Instruction %s: result is always false",
1968 macro_build (&icnt
, NULL
, "move", "d,s", dreg
, 0);
1971 switch (imm_expr
.X_add_number
& 0xffff8000)
1975 macro_build (&icnt
, &imm_expr
, "xori", "t,r,i", dreg
, sreg
);
1980 if (imm_expr
.X_add_number
!= -32768)
1982 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
1983 macro_build (&icnt
, &imm_expr
, "addiu", "t,r,j", dreg
, sreg
);
1990 macro_build_lui (&icnt
, &imm_expr
, AT
);
1991 if (imm_expr
.X_add_number
& 0xffff)
1992 macro_build (&icnt
, &imm_expr
, "addiu", "t,r,j", AT
, AT
);
1993 macro_build (&icnt
, NULL
, "xor", "d,v,t", dreg
, sreg
, AT
);
1996 macro_build (&icnt
, &expr1
, "sltiu", "t,r,j", dreg
, dreg
);
2001 case M_SGE
: /* sreg >= treg <==> not (sreg < treg) */
2007 macro_build (&icnt
, NULL
, s
, "d,v,t", dreg
, sreg
, treg
);
2008 macro_build (&icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
);
2011 case M_SGE_I
: /* sreg >= I <==> not (sreg < I) */
2013 if (imm_expr
.X_add_number
< 32768 && imm_expr
.X_add_number
> -32769)
2015 macro_build (&icnt
, &expr1
,
2016 mask
== M_SGE_I
? "slti" : "sltiu", "t,r,j", dreg
, sreg
);
2021 load_register (&icnt
, ip
, AT
, &imm_expr
);
2022 macro_build (&icnt
, NULL
,
2023 mask
== M_SGE_I
? "slt" : "sltu", "d,v,t", dreg
, sreg
, AT
);
2026 macro_build (&icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
);
2031 case M_SGT
: /* sreg > treg <==> treg < sreg */
2037 macro_build (&icnt
, NULL
, s
, "d,v,t", dreg
, treg
, sreg
);
2040 case M_SGT_I
: /* sreg > I <==> I < sreg */
2046 load_register (&icnt
, ip
, AT
, &imm_expr
);
2047 macro_build (&icnt
, NULL
, s
, "d,v,t", dreg
, AT
, sreg
);
2050 case M_SLE
: /* sreg <= treg <==> treg >= sreg <==> not (treg < sreg) */
2056 macro_build (&icnt
, NULL
, s
, "d,v,t", dreg
, treg
, sreg
);
2057 macro_build (&icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
);
2060 case M_SLE_I
: /* sreg <= I <==> I >= sreg <==> not (I < sreg) */
2066 load_register (&icnt
, ip
, AT
, &imm_expr
);
2067 macro_build (&icnt
, NULL
, s
, "d,v,t", dreg
, AT
, sreg
);
2068 macro_build (&icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
);
2072 if (imm_expr
.X_add_number
< 32768 && imm_expr
.X_add_number
> -32769)
2074 macro_build (&icnt
, &imm_expr
, "slti", "t,r,j", dreg
, sreg
);
2077 load_register (&icnt
, ip
, AT
, &imm_expr
);
2078 macro_build (&icnt
, NULL
, "slt", "d,v,t", dreg
, sreg
, AT
);
2082 if (imm_expr
.X_add_number
< 32768 && imm_expr
.X_add_number
> -32769)
2084 macro_build (&icnt
, &imm_expr
, "sltiu", "t,r,j", dreg
, sreg
);
2087 load_register (&icnt
, ip
, AT
, &imm_expr
);
2088 macro_build (&icnt
, NULL
, "sltu", "d,v,t", dreg
, sreg
, AT
);
2093 macro_build (&icnt
, NULL
, "sltu", "d,v,t", dreg
, 0, treg
);
2095 macro_build (&icnt
, NULL
, "sltu", "d,v,t", dreg
, 0, sreg
);
2098 macro_build (&icnt
, NULL
, "xor", "d,v,t", dreg
, sreg
, treg
);
2099 macro_build (&icnt
, NULL
, "sltu", "d,v,t", dreg
, 0, dreg
);
2104 if (imm_expr
.X_add_number
== 0)
2106 macro_build (&icnt
, NULL
, "sltu", "d,v,t", dreg
, 0, sreg
);
2111 as_warn ("Instruction %s: result is always true",
2113 macro_build (&icnt
, &expr1
, "addiu", "t,r,j", dreg
, 0);
2116 switch (imm_expr
.X_add_number
& 0xffff8000)
2120 macro_build (&icnt
, &imm_expr
, "xori", "t,r,i", dreg
, sreg
);
2125 if (imm_expr
.X_add_number
!= -32768)
2127 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
2128 macro_build (&icnt
, &imm_expr
, "addiu", "t,r,j", dreg
, sreg
);
2135 macro_build_lui (&icnt
, &imm_expr
, AT
);
2136 if (imm_expr
.X_add_number
& 0xffff)
2137 macro_build (&icnt
, &imm_expr
, "addiu", "t,r,j", AT
, AT
);
2138 macro_build (&icnt
, NULL
, "xor", "d,v,t", dreg
, sreg
, AT
);
2141 macro_build (&icnt
, NULL
, "sltu", "d,v,t", dreg
, 0, dreg
);
2147 if (imm_expr
.X_add_number
< 32768 && imm_expr
.X_add_number
> -32768)
2149 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
2150 macro_build (&icnt
, &imm_expr
, "addi", "t,r,j", dreg
, sreg
);
2153 load_register (&icnt
, ip
, AT
, &imm_expr
);
2154 macro_build (&icnt
, NULL
, "sub", "d,v,t", dreg
, sreg
, AT
);
2158 if (imm_expr
.X_add_number
< 32768 && imm_expr
.X_add_number
> -32768)
2160 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
2161 macro_build (&icnt
, &imm_expr
, "addiu", "t,r,j", dreg
, sreg
);
2164 load_register (&icnt
, ip
, AT
, &imm_expr
);
2165 macro_build (&icnt
, NULL
, "subu", "d,v,t", dreg
, sreg
, AT
);
2170 sreg
= (ip
->insn_opcode
>> 11) & 0x1f; /* floating reg */
2171 dreg
= (ip
->insn_opcode
>> 06) & 0x1f; /* floating reg */
2174 * Is the double cfc1 instruction a bug in the mips assembler;
2175 * or is there a reason for it?
2177 mips_emit_delays ();
2179 macro_build (&icnt
, NULL
, "cfc1", "t,G", treg
, 31);
2180 macro_build (&icnt
, NULL
, "cfc1", "t,G", treg
, 31);
2181 macro_build (&icnt
, NULL
, "nop", "");
2182 expr1
.X_add_number
= 3;
2183 macro_build (&icnt
, &expr1
, "ori", "t,r,i", AT
, treg
);
2184 expr1
.X_add_number
= 2;
2185 macro_build (&icnt
, &expr1
, "xori", "t,r,i", AT
, AT
);
2186 macro_build (&icnt
, NULL
, "ctc1", "t,G", AT
, 31);
2187 macro_build (&icnt
, NULL
, "nop", "");
2188 macro_build (&icnt
, NULL
,
2189 mask
== M_TRUNCWD
? "cvt.w.d" : "cvt.w.s", "D,S", dreg
, sreg
);
2190 macro_build (&icnt
, NULL
, "ctc1", "t,G", treg
, 31);
2191 macro_build (&icnt
, NULL
, "nop", "");
2201 /* avoid load delay */
2202 offset_expr
.X_add_number
+= 1;
2203 macro_build (&icnt
, &offset_expr
, s
, "t,o(b)", treg
, breg
);
2204 offset_expr
.X_add_number
-= 1;
2205 macro_build (&icnt
, &offset_expr
, "lbu", "t,o(b)", AT
, breg
);
2206 macro_build (&icnt
, NULL
, "sll", "d,w,<", treg
, treg
, 8);
2207 macro_build (&icnt
, NULL
, "or", "d,v,t", treg
, treg
, AT
);
2211 /* does this work on a big endian machine? */
2212 offset_expr
.X_add_number
+= 3;
2213 macro_build (&icnt
, &offset_expr
, "lwl", "t,o(b)", treg
, breg
);
2214 offset_expr
.X_add_number
-= 3;
2215 macro_build (&icnt
, &offset_expr
, "lwr", "t,o(b)", treg
, breg
);
2221 if (offset_expr
.X_op
== O_constant
)
2222 load_register (&icnt
, ip
, AT
, &offset_expr
);
2223 else if (gp_reference (&offset_expr
))
2224 macro_build (&icnt
, &offset_expr
, "addiu", "t,r,j", AT
, GP
);
2227 macro_build_lui (&icnt
, &offset_expr
, AT
);
2228 macro_build (&icnt
, &offset_expr
, "addiu", "t,r,j", AT
, AT
);
2230 if (mask
== M_ULW_A
)
2232 expr1
.X_add_number
= 3;
2233 macro_build (&icnt
, &expr1
, "lwl", "t,o(b)", treg
, AT
);
2234 imm_expr
.X_add_number
= 0;
2235 macro_build (&icnt
, &expr1
, "lwr", "t,o(b)", treg
, AT
);
2239 macro_build (&icnt
, &expr1
,
2240 mask
== M_ULH_A
? "lb" : "lbu", "t,o(b)", treg
, AT
);
2241 imm_expr
.X_add_number
= 0;
2242 macro_build (&icnt
, &expr1
, "lbu", "t,o(b)", AT
, AT
);
2243 macro_build (&icnt
, NULL
, "sll", "d,w,<", treg
, treg
, 8);
2244 macro_build (&icnt
, NULL
, "or", "d,v,t", treg
, treg
, AT
);
2249 macro_build (&icnt
, &offset_expr
, "sb", "t,o(b)", treg
, breg
);
2250 macro_build (&icnt
, NULL
, "srl", "d,w,<", AT
, treg
, 8);
2251 offset_expr
.X_add_number
+= 1;
2252 macro_build (&icnt
, &offset_expr
, "sb", "t,o(b)", AT
, breg
);
2256 offset_expr
.X_add_number
+= 3;
2257 macro_build (&icnt
, &offset_expr
, "swl", "t,o(b)", treg
, breg
);
2258 offset_expr
.X_add_number
-= 3;
2259 macro_build (&icnt
, &offset_expr
, "swr", "t,o(b)", treg
, breg
);
2264 if (offset_expr
.X_op
== O_constant
)
2265 load_register (&icnt
, ip
, AT
, &offset_expr
);
2266 else if (gp_reference (&offset_expr
))
2267 macro_build (&icnt
, &offset_expr
, "addiu", "t,r,j", AT
, GP
);
2270 macro_build_lui (&icnt
, &offset_expr
, AT
);
2271 macro_build (&icnt
, &offset_expr
, "addiu", "t,r,j", AT
, AT
);
2273 if (mask
== M_USW_A
)
2275 expr1
.X_add_number
= 3;
2276 macro_build (&icnt
, &expr1
, "swl", "t,o(b)", treg
, AT
);
2277 expr1
.X_add_number
= 0;
2278 macro_build (&icnt
, &expr1
, "swr", "t,o(b)", treg
, AT
);
2282 expr1
.X_add_number
= 0;
2283 macro_build (&icnt
, &expr1
, "sb", "t,o(b)", treg
, AT
);
2284 macro_build (&icnt
, NULL
, "srl", "d,w,<", treg
, treg
, 8);
2285 expr1
.X_add_number
= 1;
2286 macro_build (&icnt
, &expr1
, "sb", "t,o(b)", treg
, AT
);
2287 expr1
.X_add_number
= 0;
2288 macro_build (&icnt
, &expr1
, "lbu", "t,o(b)", AT
, AT
);
2289 macro_build (&icnt
, NULL
, "sll", "d,w,<", treg
, treg
, 8);
2290 macro_build (&icnt
, NULL
, "or", "d,v,t", treg
, treg
, AT
);
2295 as_bad ("Macro %s not implemented yet", ip
->insn_mo
->name
);
2298 as_warn ("Macro used $at after \".set noat\"");
2303 This routine assembles an instruction into its binary format. As a side
2304 effect it sets one of the global variables imm_reloc or offset_reloc to the
2305 type of relocation to do if one of the operands is an address expression.
2310 struct mips_cl_insn
*ip
;
2315 struct mips_opcode
*insn
;
2318 unsigned int lastregno
= 0;
2323 for (s
= str
; islower (*s
) || (*s
>= '0' && *s
<= '3') || *s
== '.'; ++s
)
2335 as_warn ("Unknown opcode: `%s'", str
);
2338 if ((insn
= (struct mips_opcode
*) hash_find (op_hash
, str
)) == NULL
)
2340 as_warn ("`%s' not in hash table.", str
);
2341 insn_error
= "ERROR: Unrecognized opcode";
2347 assert (strcmp (insn
->name
, str
) == 0);
2349 ip
->insn_opcode
= insn
->match
;
2350 for (args
= insn
->args
;; ++args
)
2356 case '\0': /* end of args */
2369 ip
->insn_opcode
|= lastregno
<< 21;
2374 ip
->insn_opcode
|= lastregno
<< 16;
2378 ip
->insn_opcode
|= lastregno
<< 11;
2384 /* handle optional base register.
2385 Either the base register is omitted or
2386 we must have a left paren. */
2387 /* this is dependent on the next operand specifier
2388 is a 'b' for base register */
2389 assert (args
[1] == 'b');
2393 case ')': /* these must match exactly */
2398 case '<': /* must be at least one digit */
2400 * According to the manual, if the shift amount is greater
2401 * than 31 or less than 0 the the shift amount should be
2402 * mod 32. In reality the mips assembler issues an error.
2403 * We issue a warning and do the mod.
2405 my_getExpression (&imm_expr
, s
);
2406 check_absolute_expr (ip
, &imm_expr
);
2407 if ((unsigned long) imm_expr
.X_add_number
> 31)
2409 as_warn ("Improper shift amount (%d)",
2410 imm_expr
.X_add_number
);
2411 imm_expr
.X_add_number
= imm_expr
.X_add_number
% 32;
2413 ip
->insn_opcode
|= imm_expr
.X_add_number
<< 6;
2414 imm_expr
.X_op
= O_absent
;
2418 case 'c': /* break code */
2419 my_getExpression (&imm_expr
, s
);
2420 check_absolute_expr (ip
, &imm_expr
);
2421 if ((unsigned) imm_expr
.X_add_number
> 1023)
2422 as_warn ("Illegal break code (%d)", imm_expr
.X_add_number
);
2423 ip
->insn_opcode
|= imm_expr
.X_add_number
<< 16;
2424 imm_expr
.X_op
= O_absent
;
2428 case 'B': /* syscall code */
2429 my_getExpression (&imm_expr
, s
);
2430 check_absolute_expr (ip
, &imm_expr
);
2431 if ((unsigned) imm_expr
.X_add_number
> 0xfffff)
2432 as_warn ("Illegal syscall code (%d)", imm_expr
.X_add_number
);
2433 ip
->insn_opcode
|= imm_expr
.X_add_number
<< 6;
2434 imm_expr
.X_op
= O_absent
;
2438 case 'b': /* base register */
2439 case 'd': /* destination register */
2440 case 's': /* source register */
2441 case 't': /* target register */
2442 case 'r': /* both target and source */
2443 case 'v': /* both dest and source */
2444 case 'w': /* both dest and target */
2445 case 'E': /* coprocessor target register */
2446 case 'G': /* coprocessor destination register */
2460 while (isdigit (*s
));
2462 else if (s
[1] == 'f' && s
[2] == 'p')
2467 else if (s
[1] == 's' && s
[2] == 'p')
2472 else if (s
[1] == 'g' && s
[2] == 'p')
2477 else if (s
[1] == 'a' && s
[2] == 't')
2485 as_bad ("Invalid register number (%d)", regno
);
2486 if (regno
== AT
&& !mips_noat
)
2487 as_warn ("Used $at without \".set noat\"");
2493 if (c
== 'r' || c
== 'v' || c
== 'w')
2506 ip
->insn_opcode
|= regno
<< 21;
2510 ip
->insn_opcode
|= regno
<< 11;
2515 ip
->insn_opcode
|= regno
<< 16;
2525 ip
->insn_opcode
|= lastregno
<< 21;
2528 ip
->insn_opcode
|= lastregno
<< 16;
2533 case 'D': /* floating point destination register */
2534 case 'S': /* floating point source register */
2535 case 'T': /* floating point target register */
2539 if (s
[0] == '$' && s
[1] == 'f' && isdigit (s
[2]))
2549 while (isdigit (*s
));
2552 as_bad ("Invalid float register number (%d)", regno
);
2555 !(strcmp (str
, "mtc1") == 0 ||
2556 strcmp (str
, "mfc1") == 0 ||
2557 strcmp (str
, "lwc1") == 0 ||
2558 strcmp (str
, "swc1") == 0))
2559 as_warn ("Float register should be even, was %d",
2567 if (c
== 'V' || c
== 'W')
2577 ip
->insn_opcode
|= regno
<< 6;
2581 ip
->insn_opcode
|= regno
<< 11;
2585 ip
->insn_opcode
|= regno
<< 16;
2593 ip
->insn_opcode
|= lastregno
<< 11;
2596 ip
->insn_opcode
|= lastregno
<< 16;
2602 my_getExpression (&imm_expr
, s
);
2603 check_absolute_expr (ip
, &imm_expr
);
2608 my_getExpression (&offset_expr
, s
);
2609 imm_reloc
= BFD_RELOC_32
;
2614 as_bad ("Floating point constants only implemented for pseudo ops.");
2617 case 'i': /* 16 bit unsigned immediate */
2618 case 'j': /* 16 bit signed immediate */
2619 imm_reloc
= BFD_RELOC_LO16
;
2620 c
= my_getSmallExpression (&imm_expr
, s
);
2625 if (imm_expr
.X_op
== O_constant
)
2626 imm_expr
.X_add_number
=
2627 (imm_expr
.X_add_number
>> 16) & 0xffff;
2629 imm_reloc
= BFD_RELOC_HI16_S
;
2631 imm_reloc
= BFD_RELOC_HI16
;
2635 check_absolute_expr (ip
, &imm_expr
);
2638 if ((unsigned long) imm_expr
.X_add_number
> 65535)
2640 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
2641 !strcmp (insn
->name
, insn
[1].name
))
2643 as_bad ("16 bit expression not in range 0..65535");
2648 if (imm_expr
.X_add_number
< -32768 ||
2649 imm_expr
.X_add_number
> 32767)
2651 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
2652 !strcmp (insn
->name
, insn
[1].name
))
2654 as_bad ("16 bit expression not in range -32768..32767");
2660 case 'o': /* 16 bit offset */
2661 c
= my_getSmallExpression (&offset_expr
, s
);
2663 * If this value won't fit into a 16 bit offset, then
2664 * go find a macro that will generate the 32 bit offset
2667 if ((offset_expr
.X_add_symbol
2668 && offset_expr
.X_op
!= O_constant
)
2669 || offset_expr
.X_op_symbol
2670 || offset_expr
.X_add_number
> 32767
2671 || offset_expr
.X_add_number
< -32768)
2674 offset_reloc
= BFD_RELOC_LO16
;
2675 if (c
== 'h' || c
== 'H')
2676 offset_expr
.X_add_number
=
2677 (offset_expr
.X_add_number
>> 16) & 0xffff;
2681 case 'p': /* pc relative offset */
2682 offset_reloc
= BFD_RELOC_16_PCREL_S2
;
2683 my_getExpression (&offset_expr
, s
);
2687 case 'u': /* upper 16 bits */
2688 c
= my_getSmallExpression (&imm_expr
, s
);
2689 if ((unsigned long) imm_expr
.X_add_number
> 65535)
2690 as_bad ("lui expression not in range 0..65535");
2691 imm_reloc
= BFD_RELOC_LO16
;
2696 if (imm_expr
.X_op
== O_constant
)
2697 imm_expr
.X_add_number
=
2698 (imm_expr
.X_add_number
>> 16) & 0xffff;
2700 imm_reloc
= BFD_RELOC_HI16_S
;
2702 imm_reloc
= BFD_RELOC_HI16
;
2708 case 'a': /* 26 bit address */
2709 my_getExpression (&offset_expr
, s
);
2711 offset_reloc
= BFD_RELOC_MIPS_JMP
;
2715 fprintf (stderr
, "bad char = '%c'\n", *args
);
2720 /* Args don't match. */
2721 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
2722 !strcmp (insn
->name
, insn
[1].name
))
2728 insn_error
= "ERROR: Illegal operands";
2737 my_getSmallExpression (ep
, str
)
2748 ((str
[1] == 'h' && str
[2] == 'i')
2749 || (str
[1] == 'H' && str
[2] == 'I')
2750 || (str
[1] == 'l' && str
[2] == 'o'))
2762 * A small expression may be followed by a base register.
2763 * Scan to the end of this operand, and then back over a possible
2764 * base register. Then scan the small expression up to that
2765 * point. (Based on code in sparc.c...)
2767 for (sp
= str
; *sp
&& *sp
!= ','; sp
++)
2769 if (sp
- 4 >= str
&& sp
[-1] == RP
)
2771 if (isdigit (sp
[-2]))
2773 for (sp
-= 3; sp
>= str
&& isdigit (*sp
); sp
--)
2775 if (*sp
== '$' && sp
> str
&& sp
[-1] == LP
)
2781 else if (sp
- 5 >= str
2784 && ((sp
[-3] == 'f' && sp
[-2] == 'p')
2785 || (sp
[-3] == 's' && sp
[-2] == 'p')
2786 || (sp
[-3] == 'g' && sp
[-2] == 'p')
2787 || (sp
[-3] == 'a' && sp
[-2] == 't')))
2793 /* no expression means zero offset */
2796 /* %xx(reg) is an error */
2797 ep
->X_op
= O_absent
;
2802 ep
->X_op
= O_absent
;
2805 ep
->X_add_symbol
= NULL
;
2806 ep
->X_op_symbol
= NULL
;
2807 ep
->X_add_number
= 0;
2812 my_getExpression (ep
, str
);
2819 my_getExpression (ep
, str
);
2820 return c
; /* => %hi or %lo encountered */
2824 my_getExpression (ep
, str
)
2830 save_in
= input_line_pointer
;
2831 input_line_pointer
= str
;
2833 expr_end
= input_line_pointer
;
2834 input_line_pointer
= save_in
;
2837 /* Turn a string in input_line_pointer into a floating point constant
2838 of type type, and store the appropriate bytes in *litP. The number
2839 of LITTLENUMS emitted is stored in *sizeP . An error message is
2840 returned, or NULL on OK. */
2843 md_atof (type
, litP
, sizeP
)
2849 LITTLENUM_TYPE words
[4];
2865 return "bad call to md_atof";
2868 t
= atof_ieee (input_line_pointer
, type
, words
);
2870 input_line_pointer
= t
;
2874 if (byte_order
== LITTLE_ENDIAN
)
2876 for (i
= prec
- 1; i
>= 0; i
--)
2878 md_number_to_chars (litP
, (valueT
) words
[i
], 2);
2884 for (i
= 0; i
< prec
; i
++)
2886 md_number_to_chars (litP
, (valueT
) words
[i
], 2);
2895 md_number_to_chars (buf
, val
, n
)
2947 md_parse_option (argP
, cntP
, vecP
)
2952 /* Accept -nocpp but ignore it. */
2953 if (!strcmp (*argP
, "nocpp"))
2959 if (strcmp (*argP
, "EL") == 0
2960 || strcmp (*argP
, "EB") == 0)
2962 /* FIXME: This breaks -L -EL. */
2971 if ((*argP
)[1] != '\0')
2972 g_switch_value
= atoi (*argP
+ 1);
2975 **vecP
= (char *) NULL
;
2978 g_switch_value
= atoi (**vecP
);
2981 as_warn ("Number expected after -G");
2986 return 1; /* pretend you parsed the character */
2990 md_pcrel_from (fixP
)
2993 /* return the address of the delay slot */
2994 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
2998 md_apply_fix (fixP
, valueP
)
3005 assert (fixP
->fx_size
== 4);
3008 fixP
->fx_addnumber
= value
; /* Remember value for tc_gen_reloc */
3010 switch (fixP
->fx_r_type
)
3013 case BFD_RELOC_MIPS_JMP
:
3014 case BFD_RELOC_HI16
:
3015 case BFD_RELOC_HI16_S
:
3016 case BFD_RELOC_LO16
:
3017 case BFD_RELOC_MIPS_GPREL
:
3018 /* Nothing needed to do. The value comes from the reloc entry */
3021 case BFD_RELOC_16_PCREL_S2
:
3023 * We need to save the bits in the instruction since fixup_segment()
3024 * might be deleting the relocation entry (i.e., a branch within
3025 * the current segment).
3028 as_warn ("Branch to odd address (%x)", value
);
3030 if ((value
& ~0xFFFF) && (value
& ~0xFFFF) != (-1 & ~0xFFFF))
3031 as_bad ("Relocation overflow");
3033 /* update old instruction data */
3034 buf
= (unsigned char *) (fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
);
3038 insn
= (buf
[3] << 24) | (buf
[2] << 16) | (buf
[1] << 8) | buf
[0];
3042 insn
= (buf
[0] << 24) | (buf
[1] << 16) | (buf
[2] << 8) | buf
[3];
3049 insn
|= value
& 0xFFFF;
3050 md_number_to_chars ((char *) buf
, insn
, 4);
3064 const struct mips_opcode
*p
;
3065 int treg
, sreg
, dreg
, shamt
;
3070 for (i
= 0; i
< NUMOPCODES
; ++i
)
3072 p
= &mips_opcodes
[i
];
3073 if (((oc
& p
->mask
) == p
->match
) && (p
->pinfo
!= INSN_MACRO
))
3075 printf ("%08lx %s\t", oc
, p
->name
);
3076 treg
= (oc
>> 16) & 0x1f;
3077 sreg
= (oc
>> 21) & 0x1f;
3078 dreg
= (oc
>> 11) & 0x1f;
3079 shamt
= (oc
>> 6) & 0x1f;
3081 for (args
= p
->args
;; ++args
)
3092 printf ("%c", *args
);
3096 assert (treg
== sreg
);
3097 printf ("$%d,$%d", treg
, sreg
);
3102 printf ("$%d", dreg
);
3107 printf ("$%d", treg
);
3112 printf ("$%d", sreg
);
3116 printf ("0x%08lx", oc
& 0x1ffffff);
3127 printf ("$%d", shamt
);
3138 printf ("%08lx UNDEFINED\n", oc
);
3149 name
= input_line_pointer
;
3150 c
= get_symbol_end ();
3151 p
= (symbolS
*) symbol_find_or_make (name
);
3152 *input_line_pointer
= c
;
3156 /* Align the current frag to a given power of two. The MIPS assembler
3157 also automatically adjusts any preceding label. */
3160 mips_align (to
, fill
)
3164 mips_emit_delays ();
3165 frag_align (to
, fill
);
3166 record_alignment (now_seg
, to
);
3167 if (insn_label
!= NULL
)
3169 assert (S_GET_SEGMENT (insn_label
) == now_seg
);
3170 insn_label
->sy_frag
= frag_now
;
3171 S_SET_VALUE (insn_label
, frag_now_fix ());
3175 /* Align to a given power of two. .align 0 turns off the automatic
3176 alignment used by the data creating pseudo-ops. */
3183 register long temp_fill
;
3184 long max_alignment
= 15;
3188 o Note that the assembler pulls down any immediately preceeding label
3189 to the aligned address.
3190 o It's not documented but auto alignment is reinstated by
3191 a .align pseudo instruction.
3192 o Note also that after auto alignment is turned off the mips assembler
3193 issues an error on attempt to assemble an improperly aligned data item.
3198 temp
= get_absolute_expression ();
3199 if (temp
> max_alignment
)
3200 as_bad ("Alignment too large: %d. assumed.", temp
= max_alignment
);
3203 as_warn ("Alignment negative: 0 assumed.");
3206 if (*input_line_pointer
== ',')
3208 input_line_pointer
++;
3209 temp_fill
= get_absolute_expression ();
3216 mips_align (temp
, (int) temp_fill
);
3223 demand_empty_rest_of_line ();
3226 /* Handle .ascii and .asciiz. This just calls stringer and forgets
3227 that there was a previous instruction. */
3230 s_stringer (append_zero
)
3233 mips_emit_delays ();
3234 stringer (append_zero
);
3243 mips_emit_delays ();
3252 subseg_new (".rdata", (subsegT
) get_absolute_expression ());
3253 demand_empty_rest_of_line ();
3262 #ifdef BFD_ASSEMBLER
3263 subseg_set (bss_section
, (subsegT
) get_absolute_expression ());
3265 subseg_new (bss_section
, (subsegT
) get_absolute_expression ());
3267 demand_empty_rest_of_line ();
3271 subseg_new (".sdata", (subsegT
) get_absolute_expression ());
3272 demand_empty_rest_of_line ();
3275 as_bad ("Global pointers not supported; recompile -G 0");
3276 demand_empty_rest_of_line ();
3287 mips_emit_delays ();
3288 if (log_size
> 0 && auto_align
)
3289 mips_align (log_size
, 0);
3290 cons (1 << log_size
);
3297 as_fatal ("Encountered `.err', aborting assembly");
3307 symbolP
= get_symbol ();
3308 if (*input_line_pointer
== ',')
3309 input_line_pointer
++;
3310 size
= get_absolute_expression ();
3311 S_SET_VALUE (symbolP
, size
);
3312 S_SET_EXTERNAL (symbolP
);
3315 /* ECOFF needs to distinguish a .comm symbol from a .extern symbol,
3316 so we use an additional ECOFF specific field. */
3317 symbolP
->ecoff_undefined
= 1;
3325 mips_emit_delays ();
3340 if (strcmp (input_line_pointer
, "O1") != 0
3341 && strcmp (input_line_pointer
, "O2") != 0)
3342 as_warn ("Unrecognized option");
3343 demand_empty_rest_of_line ();
3350 char *name
= input_line_pointer
, ch
;
3352 while (!is_end_of_line
[(unsigned char) *input_line_pointer
])
3353 input_line_pointer
++;
3354 ch
= *input_line_pointer
;
3355 *input_line_pointer
= '\0';
3357 if (strcmp (name
, "reorder") == 0)
3361 else if (strcmp (name
, "noreorder") == 0)
3363 mips_emit_delays ();
3366 else if (strcmp (name
, "at") == 0)
3370 else if (strcmp (name
, "noat") == 0)
3374 else if (strcmp (name
, "macro") == 0)
3376 mips_warn_about_macros
= 0;
3378 else if (strcmp (name
, "nomacro") == 0)
3380 if (mips_noreorder
== 0)
3381 as_bad ("`noreorder' must be set before `nomacro'");
3382 mips_warn_about_macros
= 1;
3384 else if (strcmp (name
, "move") == 0 || strcmp (name
, "novolatile") == 0)
3388 else if (strcmp (name
, "nomove") == 0 || strcmp (name
, "volatile") == 0)
3392 else if (strcmp (name
, "bopt") == 0)
3396 else if (strcmp (name
, "nobopt") == 0)
3402 as_warn ("Tried to set unrecognized symbol: %s\n", name
);
3404 *input_line_pointer
= ch
;
3405 demand_empty_rest_of_line ();
3408 /* The same as the usual .space directive, except that we have to
3409 forget about any previous instruction. */
3412 s_mips_space (param
)
3415 mips_emit_delays ();
3425 if (*input_line_pointer
++ != '$')
3427 as_warn ("expected `$'");
3430 if (isdigit ((unsigned char) *input_line_pointer
))
3432 reg
= get_absolute_expression ();
3433 if (reg
< 0 || reg
>= 32)
3435 as_warn ("Bad register number");
3441 if (strncmp (input_line_pointer
, "fp", 2) == 0)
3443 else if (strncmp (input_line_pointer
, "sp", 2) == 0)
3445 else if (strncmp (input_line_pointer
, "gp", 2) == 0)
3447 else if (strncmp (input_line_pointer
, "at", 2) == 0)
3451 as_warn ("Unrecognized register name");
3454 input_line_pointer
+= 2;
3460 * Translate internal representation of relocation info to BFD target format.
3463 tc_gen_reloc (section
, fixp
)
3469 reloc
= (arelent
*) xmalloc (sizeof (arelent
));
3470 assert (reloc
!= 0);
3472 reloc
->sym_ptr_ptr
= &fixp
->fx_addsy
->bsym
;
3473 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
3474 if (fixp
->fx_pcrel
== 0)
3475 reloc
->addend
= fixp
->fx_addnumber
;
3480 reloc
->addend
= -reloc
->address
;
3482 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, fixp
->fx_r_type
);
3483 assert (reloc
->howto
!= 0);
3488 /* should never be called */
3490 md_section_align (seg
, addr
)
3494 int align
= bfd_get_section_alignment (stdoutput
, seg
);
3496 return ((addr
+ (1 << align
) - 1) & (-1 << align
));
3500 md_estimate_size_before_relax (fragP
, segtype
)
3504 as_fatal ("md_estimate_size_before_relax");
3506 } /* md_estimate_size_before_relax() */
3508 /* This function is called whenever a label is defined. It is used
3509 when handling branch delays; if a branch has a label, we assume we
3513 mips_define_label (sym
)
3521 /* These functions should really be defined by the object file format,
3522 since they are related to debugging information. However, this
3523 code has to work for the a.out format, which does not define them,
3524 so we provide simple versions here. These don't actually generate
3525 any debugging information, but they do simple checking and someday
3526 somebody may make them useful. */
3530 struct loc
*loc_next
;
3531 unsigned long loc_fileno
;
3532 unsigned long loc_lineno
;
3533 unsigned long loc_offset
;
3534 unsigned short loc_delta
;
3535 unsigned short loc_count
;
3544 struct proc
*proc_next
;
3545 struct symbol
*proc_isym
;
3546 struct symbol
*proc_end
;
3547 unsigned long proc_reg_mask
;
3548 unsigned long proc_reg_offset
;
3549 unsigned long proc_fpreg_mask
;
3550 unsigned long proc_fpreg_offset
;
3551 unsigned long proc_frameoffset
;
3552 unsigned long proc_framereg
;
3553 unsigned long proc_pcreg
;
3555 struct file
*proc_file
;
3562 struct file
*file_next
;
3563 unsigned long file_fileno
;
3564 struct symbol
*file_symbol
;
3565 struct symbol
*file_end
;
3566 struct proc
*file_proc
;
3571 static struct obstack proc_frags
;
3572 static procS
*proc_lastP
;
3573 static procS
*proc_rootP
;
3574 static int numprocs
;
3579 obstack_begin (&proc_frags
, 0x2000);
3585 /* check for premature end, nesting errors, etc */
3586 if (proc_lastP
&& proc_lastP
->proc_end
== NULL
)
3587 as_warn ("missing `.end' at end of assembly");
3590 extern char hex_value
[];
3598 if (*input_line_pointer
== '-')
3600 ++input_line_pointer
;
3603 if (!isdigit (*input_line_pointer
))
3604 as_bad ("Expected simple number.");
3605 if (input_line_pointer
[0] == '0')
3607 if (input_line_pointer
[1] == 'x')
3609 input_line_pointer
+= 2;
3610 while (isxdigit (*input_line_pointer
))
3613 val
|= hex_value
[(int) *input_line_pointer
++];
3615 return negative
? -val
: val
;
3619 ++input_line_pointer
;
3620 while (isdigit (*input_line_pointer
))
3623 val
|= *input_line_pointer
++ - '0';
3625 return negative
? -val
: val
;
3628 if (!isdigit (*input_line_pointer
))
3630 printf (" *input_line_pointer == '%c' 0x%02x\n",
3631 *input_line_pointer
, *input_line_pointer
);
3632 as_warn ("Invalid number");
3635 while (isdigit (*input_line_pointer
))
3638 val
+= *input_line_pointer
++ - '0';
3640 return negative
? -val
: val
;
3643 /* The .file directive; just like the usual .file directive, but there
3644 is an initial number which is the ECOFF file index. */
3652 line
= get_number ();
3657 /* The .end directive. */
3665 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
3668 demand_empty_rest_of_line ();
3672 if (now_seg
!= text_section
)
3673 as_warn (".end not in text section");
3676 as_warn (".end and no .ent seen yet.");
3682 assert (S_GET_NAME (p
));
3683 if (strcmp (S_GET_NAME (p
), S_GET_NAME (proc_lastP
->proc_isym
)))
3684 as_warn (".end symbol does not match .ent symbol.");
3687 proc_lastP
->proc_end
= (symbolS
*) 1;
3690 /* The .aent and .ent directives. */
3700 symbolP
= get_symbol ();
3701 if (*input_line_pointer
== ',')
3702 input_line_pointer
++;
3703 if (isdigit (*input_line_pointer
) || *input_line_pointer
== '-')
3704 number
= get_number ();
3705 if (now_seg
!= text_section
)
3706 as_warn (".ent or .aent not in text section.");
3708 if (!aent
&& proc_lastP
&& proc_lastP
->proc_end
== NULL
)
3709 as_warn ("missing `.end'");
3713 procP
= (procS
*) obstack_alloc (&proc_frags
, sizeof (*procP
));
3714 procP
->proc_isym
= symbolP
;
3715 procP
->proc_reg_mask
= 0;
3716 procP
->proc_reg_offset
= 0;
3717 procP
->proc_fpreg_mask
= 0;
3718 procP
->proc_fpreg_offset
= 0;
3719 procP
->proc_frameoffset
= 0;
3720 procP
->proc_framereg
= 0;
3721 procP
->proc_pcreg
= 0;
3722 procP
->proc_end
= NULL
;
3723 procP
->proc_next
= NULL
;
3725 proc_lastP
->proc_next
= procP
;
3731 demand_empty_rest_of_line ();
3734 /* The .frame directive. */
3747 frame_reg
= tc_get_register ();
3748 if (*input_line_pointer
== ',')
3749 input_line_pointer
++;
3750 frame_off
= get_absolute_expression ();
3751 if (*input_line_pointer
== ',')
3752 input_line_pointer
++;
3753 pcreg
= tc_get_register ();
3756 assert (proc_rootP
);
3757 proc_rootP
->proc_framereg
= frame_reg
;
3758 proc_rootP
->proc_frameoffset
= frame_off
;
3759 proc_rootP
->proc_pcreg
= pcreg
;
3760 /* bob macho .frame */
3762 /* We don't have to write out a frame stab for unoptimized code. */
3763 if (!(frame_reg
== 30 && frame_off
== 0))
3766 as_warn ("No .ent for .frame to use.");
3767 (void) sprintf (str
, "R%d;%d", frame_reg
, frame_off
);
3768 symP
= symbol_new (str
, N_VFP
, 0, frag_now
);
3769 S_SET_TYPE (symP
, N_RMASK
);
3770 S_SET_OTHER (symP
, 0);
3771 S_SET_DESC (symP
, 0);
3772 symP
->sy_forward
= proc_lastP
->proc_isym
;
3773 /* bob perhaps I should have used pseudo set */
3775 demand_empty_rest_of_line ();
3779 /* The .fmask and .mask directives. */
3786 char str
[100], *strP
;
3792 mask
= get_number ();
3793 if (*input_line_pointer
== ',')
3794 input_line_pointer
++;
3795 off
= get_absolute_expression ();
3797 /* bob only for coff */
3798 assert (proc_rootP
);
3799 if (reg_type
== 'F')
3801 proc_rootP
->proc_fpreg_mask
= mask
;
3802 proc_rootP
->proc_fpreg_offset
= off
;
3806 proc_rootP
->proc_reg_mask
= mask
;
3807 proc_rootP
->proc_reg_offset
= off
;
3810 /* bob macho .mask + .fmask */
3812 /* We don't have to write out a mask stab if no saved regs. */
3816 as_warn ("No .ent for .mask to use.");
3818 for (i
= 0; i
< 32; i
++)
3822 sprintf (strP
, "%c%d,", reg_type
, i
);
3823 strP
+= strlen (strP
);
3827 sprintf (strP
, ";%d,", off
);
3828 symP
= symbol_new (str
, N_RMASK
, 0, frag_now
);
3829 S_SET_TYPE (symP
, N_RMASK
);
3830 S_SET_OTHER (symP
, 0);
3831 S_SET_DESC (symP
, 0);
3832 symP
->sy_forward
= proc_lastP
->proc_isym
;
3833 /* bob perhaps I should have used pseudo set */
3838 /* The .loc directive. */
3849 assert (now_seg
== text_section
);
3851 lineno
= get_number ();
3852 addroff
= obstack_next_free (&frags
) - frag_now
->fr_literal
;
3854 symbolP
= symbol_new ("", N_SLINE
, addroff
, frag_now
);
3855 S_SET_TYPE (symbolP
, N_SLINE
);
3856 S_SET_OTHER (symbolP
, 0);
3857 S_SET_DESC (symbolP
, lineno
);
3858 symbolP
->sy_segment
= now_seg
;
3862 #endif /* ! defined (OBJ_ECOFF) */