1 /* tc-mips.c -- assemble code for a MIPS chip.
2 Copyright (C) 1993, 1995, 1996 Free Software Foundation, Inc.
3 Contributed by the OSF and Ralph Campbell.
4 Written by Keith Knowles and Ralph Campbell, working independently.
5 Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus
8 This file is part of GAS.
10 GAS is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 2, or (at your option)
15 GAS is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with GAS; see the file COPYING. If not, write to the Free
22 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
28 #include "libiberty.h"
39 #include "opcode/mips.h"
42 /* Clean up namespace so we can include obj-elf.h too. */
43 static int mips_output_flavor () { return OUTPUT_FLAVOR
; }
44 #undef OBJ_PROCESS_STAB
50 #undef TARGET_SYMBOL_FIELDS
52 #undef obj_frob_symbol
54 #undef obj_sec_sym_ok_for_reloc
57 /* Fix any of them that we actually care about. */
59 #define OUTPUT_FLAVOR mips_output_flavor()
66 #ifndef ECOFF_DEBUGGING
67 #define NO_ECOFF_DEBUGGING
68 #define ECOFF_DEBUGGING 0
73 static char *mips_regmask_frag
;
76 #define PIC_CALL_REG 25
84 extern int target_big_endian
;
86 /* 1 is we should use the 64 bit MIPS ELF ABI, 0 if we should use the
87 32 bit ABI. This has no meaning for ECOFF. */
90 /* The default target format to use. */
94 switch (OUTPUT_FLAVOR
)
96 case bfd_target_aout_flavour
:
97 return target_big_endian
? "a.out-mips-big" : "a.out-mips-little";
98 case bfd_target_ecoff_flavour
:
99 return target_big_endian
? "ecoff-bigmips" : "ecoff-littlemips";
100 case bfd_target_elf_flavour
:
101 return (target_big_endian
102 ? (mips_64
? "elf64-bigmips" : "elf32-bigmips")
103 : (mips_64
? "elf64-littlemips" : "elf32-littlemips"));
109 /* The name of the readonly data section. */
110 #define RDATA_SECTION_NAME (OUTPUT_FLAVOR == bfd_target_aout_flavour \
112 : OUTPUT_FLAVOR == bfd_target_ecoff_flavour \
114 : OUTPUT_FLAVOR == bfd_target_elf_flavour \
118 /* These variables are filled in with the masks of registers used.
119 The object format code reads them and puts them in the appropriate
121 unsigned long mips_gprmask
;
122 unsigned long mips_cprmask
[4];
124 /* MIPS ISA (Instruction Set Architecture) level (may be changed
125 temporarily using .set mipsN). */
126 static int mips_isa
= -1;
128 /* MIPS ISA we are using for this output file. */
129 static int file_mips_isa
;
131 /* The CPU type as a number: 2000, 3000, 4000, 4400, etc. */
132 static int mips_cpu
= -1;
134 /* Whether the 4650 instructions (mad/madu) are permitted. */
135 static int mips_4650
= -1;
137 /* Whether the 4010 instructions are permitted. */
138 static int mips_4010
= -1;
140 /* Whether the 4100 MADD16 and DMADD16 are permitted. */
141 static int mips_4100
= -1;
143 /* Whether the processor uses hardware interlocks, and thus does not
144 require nops to be inserted. */
145 static int interlocks
= -1;
147 /* As with "interlocks" this is used by hardware that has FP
148 (co-processor) interlocks. */
149 static int cop_interlocks
= -1;
151 /* MIPS PIC level. */
155 /* Do not generate PIC code. */
158 /* Generate PIC code as in Irix 4. This is not implemented, and I'm
159 not sure what it is supposed to do. */
162 /* Generate PIC code as in the SVR4 MIPS ABI. */
165 /* Generate PIC code without using a global offset table: the data
166 segment has a maximum size of 64K, all data references are off
167 the $gp register, and all text references are PC relative. This
168 is used on some embedded systems. */
172 static enum mips_pic_level mips_pic
;
174 /* 1 if we should generate 32 bit offsets from the GP register in
175 SVR4_PIC mode. Currently has no meaning in other modes. */
176 static int mips_big_got
;
178 /* 1 if trap instructions should used for overflow rather than break
180 static int mips_trap
;
182 static int mips_warn_about_macros
;
183 static int mips_noreorder
;
184 static int mips_any_noreorder
;
185 static int mips_nomove
;
186 static int mips_noat
;
187 static int mips_nobopt
;
189 /* The size of the small data section. */
190 static int g_switch_value
= 8;
191 /* Whether the -G option was used. */
192 static int g_switch_seen
= 0;
197 /* If we can determine in advance that GP optimization won't be
198 possible, we can skip the relaxation stuff that tries to produce
199 GP-relative references. This makes delay slot optimization work
202 This function can only provide a guess, but it seems to work for
203 gcc output. If it guesses wrong, the only loss should be in
204 efficiency; it shouldn't introduce any bugs.
206 I don't know if a fix is needed for the SVR4_PIC mode. I've only
207 fixed it for the non-PIC mode. KR 95/04/07 */
208 static int nopic_need_relax
PARAMS ((symbolS
*));
210 /* handle of the OPCODE hash table */
211 static struct hash_control
*op_hash
= NULL
;
213 /* This array holds the chars that always start a comment. If the
214 pre-processor is disabled, these aren't very useful */
215 const char comment_chars
[] = "#";
217 /* This array holds the chars that only start a comment at the beginning of
218 a line. If the line seems to have the form '# 123 filename'
219 .line and .file directives will appear in the pre-processed output */
220 /* Note that input_file.c hand checks for '#' at the beginning of the
221 first line of the input file. This is because the compiler outputs
222 #NO_APP at the beginning of its output. */
223 /* Also note that C style comments are always supported. */
224 const char line_comment_chars
[] = "#";
226 /* This array holds machine specific line separator characters. */
227 const char line_separator_chars
[] = "";
229 /* Chars that can be used to separate mant from exp in floating point nums */
230 const char EXP_CHARS
[] = "eE";
232 /* Chars that mean this number is a floating point constant */
235 const char FLT_CHARS
[] = "rRsSfFdDxXpP";
237 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
238 changed in read.c . Ideally it shouldn't have to know about it at all,
239 but nothing is ideal around here.
242 static char *insn_error
;
244 static int byte_order
;
246 static int auto_align
= 1;
248 /* Symbol labelling the current insn. */
249 static symbolS
*insn_label
;
251 /* When outputting SVR4 PIC code, the assembler needs to know the
252 offset in the stack frame from which to restore the $gp register.
253 This is set by the .cprestore pseudo-op, and saved in this
255 static offsetT mips_cprestore_offset
= -1;
257 /* This is the register which holds the stack frame, as set by the
258 .frame pseudo-op. This is needed to implement .cprestore. */
259 static int mips_frame_reg
= SP
;
261 /* To output NOP instructions correctly, we need to keep information
262 about the previous two instructions. */
264 /* Whether we are optimizing. The default value of 2 means to remove
265 unneeded NOPs and swap branch instructions when possible. A value
266 of 1 means to not swap branches. A value of 0 means to always
268 static int mips_optimize
= 2;
270 /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is
271 equivalent to seeing no -g option at all. */
272 static int mips_debug
= 0;
274 /* The previous instruction. */
275 static struct mips_cl_insn prev_insn
;
277 /* The instruction before prev_insn. */
278 static struct mips_cl_insn prev_prev_insn
;
280 /* If we don't want information for prev_insn or prev_prev_insn, we
281 point the insn_mo field at this dummy integer. */
282 static const struct mips_opcode dummy_opcode
= { 0 };
284 /* Non-zero if prev_insn is valid. */
285 static int prev_insn_valid
;
287 /* The frag for the previous instruction. */
288 static struct frag
*prev_insn_frag
;
290 /* The offset into prev_insn_frag for the previous instruction. */
291 static long prev_insn_where
;
293 /* The reloc for the previous instruction, if any. */
294 static fixS
*prev_insn_fixp
;
296 /* Non-zero if the previous instruction was in a delay slot. */
297 static int prev_insn_is_delay_slot
;
299 /* Non-zero if the previous instruction was in a .set noreorder. */
300 static int prev_insn_unreordered
;
302 /* Non-zero if the previous previous instruction was in a .set
304 static int prev_prev_insn_unreordered
;
306 /* For ECOFF and ELF, relocations against symbols are done in two
307 parts, with a HI relocation and a LO relocation. Each relocation
308 has only 16 bits of space to store an addend. This means that in
309 order for the linker to handle carries correctly, it must be able
310 to locate both the HI and the LO relocation. This means that the
311 relocations must appear in order in the relocation table.
313 In order to implement this, we keep track of each unmatched HI
314 relocation. We then sort them so that they immediately precede the
315 corresponding LO relocation. */
320 struct mips_hi_fixup
*next
;
323 /* The section this fixup is in. */
327 /* The list of unmatched HI relocs. */
329 static struct mips_hi_fixup
*mips_hi_fixup_list
;
331 /* Since the MIPS does not have multiple forms of PC relative
332 instructions, we do not have to do relaxing as is done on other
333 platforms. However, we do have to handle GP relative addressing
334 correctly, which turns out to be a similar problem.
336 Every macro that refers to a symbol can occur in (at least) two
337 forms, one with GP relative addressing and one without. For
338 example, loading a global variable into a register generally uses
339 a macro instruction like this:
341 If i can be addressed off the GP register (this is true if it is in
342 the .sbss or .sdata section, or if it is known to be smaller than
343 the -G argument) this will generate the following instruction:
345 This instruction will use a GPREL reloc. If i can not be addressed
346 off the GP register, the following instruction sequence will be used:
349 In this case the first instruction will have a HI16 reloc, and the
350 second reloc will have a LO16 reloc. Both relocs will be against
353 The issue here is that we may not know whether i is GP addressable
354 until after we see the instruction that uses it. Therefore, we
355 want to be able to choose the final instruction sequence only at
356 the end of the assembly. This is similar to the way other
357 platforms choose the size of a PC relative instruction only at the
360 When generating position independent code we do not use GP
361 addressing in quite the same way, but the issue still arises as
362 external symbols and local symbols must be handled differently.
364 We handle these issues by actually generating both possible
365 instruction sequences. The longer one is put in a frag_var with
366 type rs_machine_dependent. We encode what to do with the frag in
367 the subtype field. We encode (1) the number of existing bytes to
368 replace, (2) the number of new bytes to use, (3) the offset from
369 the start of the existing bytes to the first reloc we must generate
370 (that is, the offset is applied from the start of the existing
371 bytes after they are replaced by the new bytes, if any), (4) the
372 offset from the start of the existing bytes to the second reloc,
373 (5) whether a third reloc is needed (the third reloc is always four
374 bytes after the second reloc), and (6) whether to warn if this
375 variant is used (this is sometimes needed if .set nomacro or .set
376 noat is in effect). All these numbers are reasonably small.
378 Generating two instruction sequences must be handled carefully to
379 ensure that delay slots are handled correctly. Fortunately, there
380 are a limited number of cases. When the second instruction
381 sequence is generated, append_insn is directed to maintain the
382 existing delay slot information, so it continues to apply to any
383 code after the second instruction sequence. This means that the
384 second instruction sequence must not impose any requirements not
385 required by the first instruction sequence.
387 These variant frags are then handled in functions called by the
388 machine independent code. md_estimate_size_before_relax returns
389 the final size of the frag. md_convert_frag sets up the final form
390 of the frag. tc_gen_reloc adjust the first reloc and adds a second
392 #define RELAX_ENCODE(old, new, reloc1, reloc2, reloc3, warn) \
396 | (((reloc1) + 64) << 9) \
397 | (((reloc2) + 64) << 2) \
398 | ((reloc3) ? (1 << 1) : 0) \
400 #define RELAX_OLD(i) (((i) >> 24) & 0xff)
401 #define RELAX_NEW(i) (((i) >> 16) & 0xff)
402 #define RELAX_RELOC1(i) ((bfd_vma)(((i) >> 9) & 0x7f) - 64)
403 #define RELAX_RELOC2(i) ((bfd_vma)(((i) >> 2) & 0x7f) - 64)
404 #define RELAX_RELOC3(i) (((i) >> 1) & 1)
405 #define RELAX_WARN(i) ((i) & 1)
407 /* Prototypes for static functions. */
410 #define internalError() \
411 as_fatal ("internal Error, line %d, %s", __LINE__, __FILE__)
413 #define internalError() as_fatal ("MIPS internal Error");
416 static int insn_uses_reg
PARAMS ((struct mips_cl_insn
*ip
,
417 unsigned int reg
, int fpr
));
418 static int reg_needs_delay
PARAMS ((int));
419 static void append_insn
PARAMS ((char *place
,
420 struct mips_cl_insn
* ip
,
422 bfd_reloc_code_real_type r
,
424 static void mips_no_prev_insn
PARAMS ((void));
425 static void mips_emit_delays
PARAMS ((void));
427 static void macro_build
PARAMS ((char *place
, int *counter
, expressionS
* ep
,
428 const char *name
, const char *fmt
,
431 static void macro_build ();
433 static void macro_build_lui
PARAMS ((char *place
, int *counter
,
434 expressionS
* ep
, int regnum
));
435 static void set_at
PARAMS ((int *counter
, int reg
, int unsignedp
));
436 static void check_absolute_expr
PARAMS ((struct mips_cl_insn
* ip
,
438 static void load_register
PARAMS ((int *, int, expressionS
*, int));
439 static void load_address
PARAMS ((int *counter
, int reg
, expressionS
*ep
));
440 static void macro
PARAMS ((struct mips_cl_insn
* ip
));
441 #ifdef LOSING_COMPILER
442 static void macro2
PARAMS ((struct mips_cl_insn
* ip
));
444 static void mips_ip
PARAMS ((char *str
, struct mips_cl_insn
* ip
));
445 static int my_getSmallExpression
PARAMS ((expressionS
* ep
, char *str
));
446 static void my_getExpression
PARAMS ((expressionS
* ep
, char *str
));
447 static symbolS
*get_symbol
PARAMS ((void));
448 static void mips_align
PARAMS ((int to
, int fill
, symbolS
*label
));
449 static void s_align
PARAMS ((int));
450 static void s_change_sec
PARAMS ((int));
451 static void s_cons
PARAMS ((int));
452 static void s_float_cons
PARAMS ((int));
453 static void s_mips_globl
PARAMS ((int));
454 static void s_option
PARAMS ((int));
455 static void s_mipsset
PARAMS ((int));
456 static void s_abicalls
PARAMS ((int));
457 static void s_cpload
PARAMS ((int));
458 static void s_cprestore
PARAMS ((int));
459 static void s_gpword
PARAMS ((int));
460 static void s_cpadd
PARAMS ((int));
461 static void md_obj_begin
PARAMS ((void));
462 static void md_obj_end
PARAMS ((void));
463 static long get_number
PARAMS ((void));
464 static void s_ent
PARAMS ((int));
465 static void s_mipsend
PARAMS ((int));
466 static void s_file
PARAMS ((int));
470 The following pseudo-ops from the Kane and Heinrich MIPS book
471 should be defined here, but are currently unsupported: .alias,
472 .galive, .gjaldef, .gjrlive, .livereg, .noalias.
474 The following pseudo-ops from the Kane and Heinrich MIPS book are
475 specific to the type of debugging information being generated, and
476 should be defined by the object format: .aent, .begin, .bend,
477 .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp,
480 The following pseudo-ops from the Kane and Heinrich MIPS book are
481 not MIPS CPU specific, but are also not specific to the object file
482 format. This file is probably the best place to define them, but
483 they are not currently supported: .asm0, .endr, .lab, .repeat,
484 .struct, .weakext. */
486 static const pseudo_typeS mips_pseudo_table
[] =
488 /* MIPS specific pseudo-ops. */
489 {"option", s_option
, 0},
490 {"set", s_mipsset
, 0},
491 {"rdata", s_change_sec
, 'r'},
492 {"sdata", s_change_sec
, 's'},
493 {"livereg", s_ignore
, 0},
494 {"abicalls", s_abicalls
, 0},
495 {"cpload", s_cpload
, 0},
496 {"cprestore", s_cprestore
, 0},
497 {"gpword", s_gpword
, 0},
498 {"cpadd", s_cpadd
, 0},
500 /* Relatively generic pseudo-ops that happen to be used on MIPS
502 {"asciiz", stringer
, 1},
503 {"bss", s_change_sec
, 'b'},
506 {"dword", s_cons
, 3},
508 /* These pseudo-ops are defined in read.c, but must be overridden
509 here for one reason or another. */
510 {"align", s_align
, 0},
512 {"data", s_change_sec
, 'd'},
513 {"double", s_float_cons
, 'd'},
514 {"float", s_float_cons
, 'f'},
515 {"globl", s_mips_globl
, 0},
516 {"global", s_mips_globl
, 0},
517 {"hword", s_cons
, 1},
522 {"short", s_cons
, 1},
523 {"single", s_float_cons
, 'f'},
524 {"text", s_change_sec
, 't'},
529 static const pseudo_typeS mips_nonecoff_pseudo_table
[] = {
530 /* These pseudo-ops should be defined by the object file format.
531 However, a.out doesn't support them, so we have versions here. */
533 {"bgnb", s_ignore
, 0},
534 {"end", s_mipsend
, 0},
535 {"endb", s_ignore
, 0},
538 {"fmask", s_ignore
, 'F'},
539 {"frame", s_ignore
, 0},
540 {"loc", s_ignore
, 0},
541 {"mask", s_ignore
, 'R'},
542 {"verstamp", s_ignore
, 0},
546 extern void pop_insert
PARAMS ((const pseudo_typeS
*));
551 pop_insert (mips_pseudo_table
);
552 if (! ECOFF_DEBUGGING
)
553 pop_insert (mips_nonecoff_pseudo_table
);
556 static char *expr_end
;
558 /* Expressions which appear in instructions. These are set by
561 static expressionS imm_expr
;
562 static expressionS offset_expr
;
564 /* Relocs associated with imm_expr and offset_expr. */
566 static bfd_reloc_code_real_type imm_reloc
;
567 static bfd_reloc_code_real_type offset_reloc
;
569 /* This is set by mips_ip if imm_reloc is an unmatched HI16_S reloc. */
571 static boolean imm_unmatched_hi
;
574 * This function is called once, at assembler startup time. It should
575 * set up all the tables, etc. that the MD part of the assembler will need.
581 register const char *retval
= NULL
;
582 register unsigned int i
= 0;
590 if (strcmp (cpu
+ (sizeof TARGET_CPU
) - 3, "el") == 0)
592 a
= xmalloc (sizeof TARGET_CPU
);
593 strcpy (a
, TARGET_CPU
);
594 a
[(sizeof TARGET_CPU
) - 3] = '\0';
598 if (strcmp (cpu
, "mips") == 0)
604 else if (strcmp (cpu
, "r6000") == 0
605 || strcmp (cpu
, "mips2") == 0)
611 else if (strcmp (cpu
, "mips64") == 0
612 || strcmp (cpu
, "r4000") == 0
613 || strcmp (cpu
, "mips3") == 0)
619 else if (strcmp (cpu
, "r4400") == 0)
625 else if (strcmp (cpu
, "mips64orion") == 0
626 || strcmp (cpu
, "r4600") == 0)
632 else if (strcmp (cpu
, "r4650") == 0)
640 else if (strcmp (cpu
, "mips64vr4300") == 0)
646 else if (strcmp (cpu
, "mips64vr4100") == 0)
654 else if (strcmp (cpu
, "r4010") == 0)
662 else if (strcmp (cpu
, "r8000") == 0
663 || strcmp (cpu
, "mips4") == 0)
669 else if (strcmp (cpu
, "r10000") == 0)
695 if (mips_4650
|| mips_4010
|| mips_4100
|| mips_cpu
== 4300)
700 if (mips_cpu
== 4300)
705 if (mips_isa
< 2 && mips_trap
)
706 as_bad ("trap exception not supported at ISA 1");
711 ok
= bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, 3000);
714 ok
= bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, 6000);
717 ok
= bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, 4000);
720 ok
= bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, 8000);
724 as_warn ("Could not set architecture and machine");
726 file_mips_isa
= mips_isa
;
728 op_hash
= hash_new ();
730 for (i
= 0; i
< NUMOPCODES
;)
732 const char *name
= mips_opcodes
[i
].name
;
734 retval
= hash_insert (op_hash
, name
, (PTR
) &mips_opcodes
[i
]);
737 fprintf (stderr
, "internal error: can't hash `%s': %s\n",
738 mips_opcodes
[i
].name
, retval
);
739 as_fatal ("Broken assembler. No assembly attempted.");
743 if (mips_opcodes
[i
].pinfo
!= INSN_MACRO
744 && ((mips_opcodes
[i
].match
& mips_opcodes
[i
].mask
)
745 != mips_opcodes
[i
].match
))
747 fprintf (stderr
, "internal error: bad opcode: `%s' \"%s\"\n",
748 mips_opcodes
[i
].name
, mips_opcodes
[i
].args
);
749 as_fatal ("Broken assembler. No assembly attempted.");
753 while ((i
< NUMOPCODES
) && !strcmp (mips_opcodes
[i
].name
, name
));
756 mips_no_prev_insn ();
764 /* set the default alignment for the text section (2**2) */
765 record_alignment (text_section
, 2);
767 if (USE_GLOBAL_POINTER_OPT
)
768 bfd_set_gp_size (stdoutput
, g_switch_value
);
770 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
772 /* Sections must be aligned to 16 byte boundaries. */
773 (void) bfd_set_section_alignment (stdoutput
, text_section
, 4);
774 (void) bfd_set_section_alignment (stdoutput
, data_section
, 4);
775 (void) bfd_set_section_alignment (stdoutput
, bss_section
, 4);
777 /* Create a .reginfo section for register masks and a .mdebug
778 section for debugging information. */
789 sec
= subseg_new (".reginfo", (subsegT
) 0);
791 /* The ABI says this section should be loaded so that the
792 running program can access it. */
793 (void) bfd_set_section_flags (stdoutput
, sec
,
794 (SEC_ALLOC
| SEC_LOAD
795 | SEC_READONLY
| SEC_DATA
));
796 (void) bfd_set_section_alignment (stdoutput
, sec
, 2);
799 mips_regmask_frag
= frag_more (sizeof (Elf32_External_RegInfo
));
804 /* The 64-bit ABI uses a .MIPS.options section rather than
806 sec
= subseg_new (".MIPS.options", (subsegT
) 0);
807 (void) bfd_set_section_flags (stdoutput
, sec
,
808 (SEC_ALLOC
| SEC_LOAD
809 | SEC_READONLY
| SEC_DATA
));
810 (void) bfd_set_section_alignment (stdoutput
, sec
, 3);
813 /* Set up the option header. */
815 Elf_Internal_Options opthdr
;
818 opthdr
.kind
= ODK_REGINFO
;
819 opthdr
.size
= (sizeof (Elf_External_Options
)
820 + sizeof (Elf64_External_RegInfo
));
823 f
= frag_more (sizeof (Elf_External_Options
));
824 bfd_mips_elf_swap_options_out (stdoutput
, &opthdr
,
825 (Elf_External_Options
*) f
);
827 mips_regmask_frag
= frag_more (sizeof (Elf64_External_RegInfo
));
834 sec
= subseg_new (".mdebug", (subsegT
) 0);
835 (void) bfd_set_section_flags (stdoutput
, sec
,
836 SEC_HAS_CONTENTS
| SEC_READONLY
);
837 (void) bfd_set_section_alignment (stdoutput
, sec
, 2);
840 subseg_set (seg
, subseg
);
844 if (! ECOFF_DEBUGGING
)
851 if (! ECOFF_DEBUGGING
)
859 struct mips_cl_insn insn
;
861 imm_expr
.X_op
= O_absent
;
862 imm_reloc
= BFD_RELOC_UNUSED
;
863 imm_unmatched_hi
= false;
864 offset_expr
.X_op
= O_absent
;
865 offset_reloc
= BFD_RELOC_UNUSED
;
867 mips_ip (str
, &insn
);
870 as_bad ("%s `%s'", insn_error
, str
);
873 if (insn
.insn_mo
->pinfo
== INSN_MACRO
)
879 if (imm_expr
.X_op
!= O_absent
)
880 append_insn ((char *) NULL
, &insn
, &imm_expr
, imm_reloc
,
882 else if (offset_expr
.X_op
!= O_absent
)
883 append_insn ((char *) NULL
, &insn
, &offset_expr
, offset_reloc
, false);
885 append_insn ((char *) NULL
, &insn
, NULL
, BFD_RELOC_UNUSED
, false);
889 /* See whether instruction IP reads register REG. If FPR is non-zero,
890 REG is a floating point register. */
893 insn_uses_reg (ip
, reg
, fpr
)
894 struct mips_cl_insn
*ip
;
898 /* Don't report on general register 0, since it never changes. */
899 if (! fpr
&& reg
== 0)
904 /* If we are called with either $f0 or $f1, we must check $f0.
905 This is not optimal, because it will introduce an unnecessary
906 NOP between "lwc1 $f0" and "swc1 $f1". To fix this we would
907 need to distinguish reading both $f0 and $f1 or just one of
908 them. Note that we don't have to check the other way,
909 because there is no instruction that sets both $f0 and $f1
910 and requires a delay. */
911 if ((ip
->insn_mo
->pinfo
& INSN_READ_FPR_S
)
912 && (((ip
->insn_opcode
>> OP_SH_FS
) & OP_MASK_FS
)
913 == (reg
&~ (unsigned) 1)))
915 if ((ip
->insn_mo
->pinfo
& INSN_READ_FPR_T
)
916 && (((ip
->insn_opcode
>> OP_SH_FT
) & OP_MASK_FT
)
917 == (reg
&~ (unsigned) 1)))
922 if ((ip
->insn_mo
->pinfo
& INSN_READ_GPR_S
)
923 && ((ip
->insn_opcode
>> OP_SH_RS
) & OP_MASK_RS
) == reg
)
925 if ((ip
->insn_mo
->pinfo
& INSN_READ_GPR_T
)
926 && ((ip
->insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
) == reg
)
933 /* This function returns true if modifying a register requires a
937 reg_needs_delay (reg
)
940 unsigned long prev_pinfo
;
942 prev_pinfo
= prev_insn
.insn_mo
->pinfo
;
945 && ((prev_pinfo
& INSN_LOAD_COPROC_DELAY
)
947 && (prev_pinfo
& INSN_LOAD_MEMORY_DELAY
))))
949 /* A load from a coprocessor or from memory. All load
950 delays delay the use of general register rt for one
951 instruction on the r3000. The r6000 and r4000 use
953 know (prev_pinfo
& INSN_WRITE_GPR_T
);
954 if (reg
== ((prev_insn
.insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
))
961 /* Output an instruction. PLACE is where to put the instruction; if
962 it is NULL, this uses frag_more to get room. IP is the instruction
963 information. ADDRESS_EXPR is an operand of the instruction to be
964 used with RELOC_TYPE. */
967 append_insn (place
, ip
, address_expr
, reloc_type
, unmatched_hi
)
969 struct mips_cl_insn
*ip
;
970 expressionS
*address_expr
;
971 bfd_reloc_code_real_type reloc_type
;
972 boolean unmatched_hi
;
974 register unsigned long prev_pinfo
, pinfo
;
979 prev_pinfo
= prev_insn
.insn_mo
->pinfo
;
980 pinfo
= ip
->insn_mo
->pinfo
;
982 if (place
== NULL
&& ! mips_noreorder
)
984 /* If the previous insn required any delay slots, see if we need
985 to insert a NOP or two. There are eight kinds of possible
986 hazards, of which an instruction can have at most one type.
987 (1) a load from memory delay
988 (2) a load from a coprocessor delay
989 (3) an unconditional branch delay
990 (4) a conditional branch delay
991 (5) a move to coprocessor register delay
992 (6) a load coprocessor register from memory delay
993 (7) a coprocessor condition code delay
994 (8) a HI/LO special register delay
996 There are a lot of optimizations we could do that we don't.
997 In particular, we do not, in general, reorder instructions.
998 If you use gcc with optimization, it will reorder
999 instructions and generally do much more optimization then we
1000 do here; repeating all that work in the assembler would only
1001 benefit hand written assembly code, and does not seem worth
1004 /* This is how a NOP is emitted. */
1005 #define emit_nop() md_number_to_chars (frag_more (4), 0, 4)
1007 /* The previous insn might require a delay slot, depending upon
1008 the contents of the current insn. */
1010 && (((prev_pinfo
& INSN_LOAD_COPROC_DELAY
)
1011 && ! cop_interlocks
)
1013 && (prev_pinfo
& INSN_LOAD_MEMORY_DELAY
))))
1015 /* A load from a coprocessor or from memory. All load
1016 delays delay the use of general register rt for one
1017 instruction on the r3000. The r6000 and r4000 use
1019 know (prev_pinfo
& INSN_WRITE_GPR_T
);
1020 if (mips_optimize
== 0
1021 || insn_uses_reg (ip
,
1022 ((prev_insn
.insn_opcode
>> OP_SH_RT
)
1027 else if (mips_isa
< 4
1028 && (((prev_pinfo
& INSN_COPROC_MOVE_DELAY
)
1029 && ! cop_interlocks
)
1031 && (prev_pinfo
& INSN_COPROC_MEMORY_DELAY
))))
1033 /* A generic coprocessor delay. The previous instruction
1034 modified a coprocessor general or control register. If
1035 it modified a control register, we need to avoid any
1036 coprocessor instruction (this is probably not always
1037 required, but it sometimes is). If it modified a general
1038 register, we avoid using that register.
1040 On the r6000 and r4000 loading a coprocessor register
1041 from memory is interlocked, and does not require a delay.
1043 This case is not handled very well. There is no special
1044 knowledge of CP0 handling, and the coprocessors other
1045 than the floating point unit are not distinguished at
1047 if (prev_pinfo
& INSN_WRITE_FPR_T
)
1049 if (mips_optimize
== 0
1050 || insn_uses_reg (ip
,
1051 ((prev_insn
.insn_opcode
>> OP_SH_FT
)
1056 else if (prev_pinfo
& INSN_WRITE_FPR_S
)
1058 if (mips_optimize
== 0
1059 || insn_uses_reg (ip
,
1060 ((prev_insn
.insn_opcode
>> OP_SH_FS
)
1067 /* We don't know exactly what the previous instruction
1068 does. If the current instruction uses a coprocessor
1069 register, we must insert a NOP. If previous
1070 instruction may set the condition codes, and the
1071 current instruction uses them, we must insert two
1073 if (mips_optimize
== 0
1074 || ((prev_pinfo
& INSN_WRITE_COND_CODE
)
1075 && (pinfo
& INSN_READ_COND_CODE
)))
1077 else if (pinfo
& INSN_COP
)
1081 else if (mips_isa
< 4
1082 && (prev_pinfo
& INSN_WRITE_COND_CODE
)
1083 && ! cop_interlocks
)
1085 /* The previous instruction sets the coprocessor condition
1086 codes, but does not require a general coprocessor delay
1087 (this means it is a floating point comparison
1088 instruction). If this instruction uses the condition
1089 codes, we need to insert a single NOP. */
1090 if (mips_optimize
== 0
1091 || (pinfo
& INSN_READ_COND_CODE
))
1094 else if (prev_pinfo
& INSN_READ_LO
)
1096 /* The previous instruction reads the LO register; if the
1097 current instruction writes to the LO register, we must
1098 insert two NOPS. The R4650, VR4100 and VR4300 have
1101 && (mips_optimize
== 0
1102 || (pinfo
& INSN_WRITE_LO
)))
1105 else if (prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
1107 /* The previous instruction reads the HI register; if the
1108 current instruction writes to the HI register, we must
1109 insert a NOP. The R4650, VR4100 and VR4300 have
1112 && (mips_optimize
== 0
1113 || (pinfo
& INSN_WRITE_HI
)))
1117 /* There are two cases which require two intervening
1118 instructions: 1) setting the condition codes using a move to
1119 coprocessor instruction which requires a general coprocessor
1120 delay and then reading the condition codes 2) reading the HI
1121 or LO register and then writing to it (except on the R4650,
1122 VR4100, and VR4300 which have interlocks). If we are not
1123 already emitting a NOP instruction, we must check for these
1124 cases compared to the instruction previous to the previous
1128 && (prev_prev_insn
.insn_mo
->pinfo
& INSN_COPROC_MOVE_DELAY
)
1129 && (prev_prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
)
1130 && (pinfo
& INSN_READ_COND_CODE
)
1131 && ! cop_interlocks
)
1132 || ((prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
)
1133 && (pinfo
& INSN_WRITE_LO
)
1135 || ((prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
1136 && (pinfo
& INSN_WRITE_HI
)
1140 /* If we are being given a nop instruction, don't bother with
1141 one of the nops we would otherwise output. This will only
1142 happen when a nop instruction is used with mips_optimize set
1144 if (nops
> 0 && ip
->insn_opcode
== 0)
1147 /* Now emit the right number of NOP instructions. */
1151 unsigned long old_frag_offset
;
1154 old_frag
= frag_now
;
1155 old_frag_offset
= frag_now_fix ();
1157 for (i
= 0; i
< nops
; i
++)
1162 listing_prev_line ();
1163 /* We may be at the start of a variant frag. In case we
1164 are, make sure there is enough space for the frag
1165 after the frags created by listing_prev_line. The
1166 argument to frag_grow here must be at least as large
1167 as the argument to all other calls to frag_grow in
1168 this file. We don't have to worry about being in the
1169 middle of a variant frag, because the variants insert
1170 all needed nop instructions themselves. */
1174 if (insn_label
!= NULL
)
1176 assert (S_GET_SEGMENT (insn_label
) == now_seg
);
1177 insn_label
->sy_frag
= frag_now
;
1178 S_SET_VALUE (insn_label
, (valueT
) frag_now_fix ());
1181 #ifndef NO_ECOFF_DEBUGGING
1182 if (ECOFF_DEBUGGING
)
1183 ecoff_fix_loc (old_frag
, old_frag_offset
);
1193 if (address_expr
!= NULL
)
1195 if (address_expr
->X_op
== O_constant
)
1200 ip
->insn_opcode
|= address_expr
->X_add_number
;
1203 case BFD_RELOC_LO16
:
1204 ip
->insn_opcode
|= address_expr
->X_add_number
& 0xffff;
1207 case BFD_RELOC_MIPS_JMP
:
1208 case BFD_RELOC_16_PCREL_S2
:
1217 assert (reloc_type
!= BFD_RELOC_UNUSED
);
1219 /* Don't generate a reloc if we are writing into a variant
1223 fixp
= fix_new_exp (frag_now
, f
- frag_now
->fr_literal
, 4,
1225 reloc_type
== BFD_RELOC_16_PCREL_S2
,
1229 struct mips_hi_fixup
*hi_fixup
;
1231 assert (reloc_type
== BFD_RELOC_HI16_S
);
1232 hi_fixup
= ((struct mips_hi_fixup
*)
1233 xmalloc (sizeof (struct mips_hi_fixup
)));
1234 hi_fixup
->fixp
= fixp
;
1235 hi_fixup
->seg
= now_seg
;
1236 hi_fixup
->next
= mips_hi_fixup_list
;
1237 mips_hi_fixup_list
= hi_fixup
;
1243 md_number_to_chars (f
, ip
->insn_opcode
, 4);
1245 /* Update the register mask information. */
1246 if (pinfo
& INSN_WRITE_GPR_D
)
1247 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
);
1248 if ((pinfo
& (INSN_WRITE_GPR_T
| INSN_READ_GPR_T
)) != 0)
1249 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
);
1250 if (pinfo
& INSN_READ_GPR_S
)
1251 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> OP_SH_RS
) & OP_MASK_RS
);
1252 if (pinfo
& INSN_WRITE_GPR_31
)
1253 mips_gprmask
|= 1 << 31;
1254 if (pinfo
& INSN_WRITE_FPR_D
)
1255 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FD
) & OP_MASK_FD
);
1256 if ((pinfo
& (INSN_WRITE_FPR_S
| INSN_READ_FPR_S
)) != 0)
1257 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FS
) & OP_MASK_FS
);
1258 if ((pinfo
& (INSN_WRITE_FPR_T
| INSN_READ_FPR_T
)) != 0)
1259 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FT
) & OP_MASK_FT
);
1260 if ((pinfo
& INSN_READ_FPR_R
) != 0)
1261 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FR
) & OP_MASK_FR
);
1262 if (pinfo
& INSN_COP
)
1264 /* We don't keep enough information to sort these cases out. */
1266 /* Never set the bit for $0, which is always zero. */
1267 mips_gprmask
&=~ 1 << 0;
1269 if (place
== NULL
&& ! mips_noreorder
)
1271 /* Filling the branch delay slot is more complex. We try to
1272 switch the branch with the previous instruction, which we can
1273 do if the previous instruction does not set up a condition
1274 that the branch tests and if the branch is not itself the
1275 target of any branch. */
1276 if ((pinfo
& INSN_UNCOND_BRANCH_DELAY
)
1277 || (pinfo
& INSN_COND_BRANCH_DELAY
))
1279 if (mips_optimize
< 2
1280 /* If we have seen .set volatile or .set nomove, don't
1283 /* If we had to emit any NOP instructions, then we
1284 already know we can not swap. */
1286 /* If we don't even know the previous insn, we can not
1288 || ! prev_insn_valid
1289 /* If the previous insn is already in a branch delay
1290 slot, then we can not swap. */
1291 || prev_insn_is_delay_slot
1292 /* If the previous previous insn was in a .set
1293 noreorder, we can't swap. Actually, the MIPS
1294 assembler will swap in this situation. However, gcc
1295 configured -with-gnu-as will generate code like
1301 in which we can not swap the bne and INSN. If gcc is
1302 not configured -with-gnu-as, it does not output the
1303 .set pseudo-ops. We don't have to check
1304 prev_insn_unreordered, because prev_insn_valid will
1305 be 0 in that case. We don't want to use
1306 prev_prev_insn_valid, because we do want to be able
1307 to swap at the start of a function. */
1308 || prev_prev_insn_unreordered
1309 /* If the branch is itself the target of a branch, we
1310 can not swap. We cheat on this; all we check for is
1311 whether there is a label on this instruction. If
1312 there are any branches to anything other than a
1313 label, users must use .set noreorder. */
1314 || insn_label
!= NULL
1315 /* If the previous instruction is in a variant frag, we
1316 can not do the swap. */
1317 || prev_insn_frag
->fr_type
== rs_machine_dependent
1318 /* If the branch reads the condition codes, we don't
1319 even try to swap, because in the sequence
1324 we can not swap, and I don't feel like handling that
1327 && (pinfo
& INSN_READ_COND_CODE
))
1328 /* We can not swap with an instruction that requires a
1329 delay slot, becase the target of the branch might
1330 interfere with that instruction. */
1333 & (INSN_LOAD_COPROC_DELAY
1334 | INSN_COPROC_MOVE_DELAY
1335 | INSN_WRITE_COND_CODE
)))
1342 & (INSN_LOAD_MEMORY_DELAY
1343 | INSN_COPROC_MEMORY_DELAY
)))
1344 /* We can not swap with a branch instruction. */
1346 & (INSN_UNCOND_BRANCH_DELAY
1347 | INSN_COND_BRANCH_DELAY
1348 | INSN_COND_BRANCH_LIKELY
))
1349 /* We do not swap with a trap instruction, since it
1350 complicates trap handlers to have the trap
1351 instruction be in a delay slot. */
1352 || (prev_pinfo
& INSN_TRAP
)
1353 /* If the branch reads a register that the previous
1354 instruction sets, we can not swap. */
1355 || ((prev_pinfo
& INSN_WRITE_GPR_T
)
1356 && insn_uses_reg (ip
,
1357 ((prev_insn
.insn_opcode
>> OP_SH_RT
)
1360 || ((prev_pinfo
& INSN_WRITE_GPR_D
)
1361 && insn_uses_reg (ip
,
1362 ((prev_insn
.insn_opcode
>> OP_SH_RD
)
1365 /* If the branch writes a register that the previous
1366 instruction sets, we can not swap (we know that
1367 branches write only to RD or to $31). */
1368 || ((prev_pinfo
& INSN_WRITE_GPR_T
)
1369 && (((pinfo
& INSN_WRITE_GPR_D
)
1370 && (((prev_insn
.insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
)
1371 == ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)))
1372 || ((pinfo
& INSN_WRITE_GPR_31
)
1373 && (((prev_insn
.insn_opcode
>> OP_SH_RT
)
1376 || ((prev_pinfo
& INSN_WRITE_GPR_D
)
1377 && (((pinfo
& INSN_WRITE_GPR_D
)
1378 && (((prev_insn
.insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)
1379 == ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)))
1380 || ((pinfo
& INSN_WRITE_GPR_31
)
1381 && (((prev_insn
.insn_opcode
>> OP_SH_RD
)
1384 /* If the branch writes a register that the previous
1385 instruction reads, we can not swap (we know that
1386 branches only write to RD or to $31). */
1387 || ((pinfo
& INSN_WRITE_GPR_D
)
1388 && insn_uses_reg (&prev_insn
,
1389 ((ip
->insn_opcode
>> OP_SH_RD
)
1392 || ((pinfo
& INSN_WRITE_GPR_31
)
1393 && insn_uses_reg (&prev_insn
, 31, 0))
1394 /* If we are generating embedded PIC code, the branch
1395 might be expanded into a sequence which uses $at, so
1396 we can't swap with an instruction which reads it. */
1397 || (mips_pic
== EMBEDDED_PIC
1398 && insn_uses_reg (&prev_insn
, AT
, 0))
1399 /* If the previous previous instruction has a load
1400 delay, and sets a register that the branch reads, we
1403 && ((prev_prev_insn
.insn_mo
->pinfo
& INSN_LOAD_COPROC_DELAY
)
1405 && (prev_prev_insn
.insn_mo
->pinfo
1406 & INSN_LOAD_MEMORY_DELAY
)))
1407 && insn_uses_reg (ip
,
1408 ((prev_prev_insn
.insn_opcode
>> OP_SH_RT
)
1412 /* We could do even better for unconditional branches to
1413 portions of this object file; we could pick up the
1414 instruction at the destination, put it in the delay
1415 slot, and bump the destination address. */
1417 /* Update the previous insn information. */
1418 prev_prev_insn
= *ip
;
1419 prev_insn
.insn_mo
= &dummy_opcode
;
1426 /* It looks like we can actually do the swap. */
1427 prev_f
= prev_insn_frag
->fr_literal
+ prev_insn_where
;
1428 memcpy (temp
, prev_f
, 4);
1429 memcpy (prev_f
, f
, 4);
1430 memcpy (f
, temp
, 4);
1433 prev_insn_fixp
->fx_frag
= frag_now
;
1434 prev_insn_fixp
->fx_where
= f
- frag_now
->fr_literal
;
1438 fixp
->fx_frag
= prev_insn_frag
;
1439 fixp
->fx_where
= prev_insn_where
;
1441 /* Update the previous insn information; leave prev_insn
1443 prev_prev_insn
= *ip
;
1445 prev_insn_is_delay_slot
= 1;
1447 /* If that was an unconditional branch, forget the previous
1448 insn information. */
1449 if (pinfo
& INSN_UNCOND_BRANCH_DELAY
)
1451 prev_prev_insn
.insn_mo
= &dummy_opcode
;
1452 prev_insn
.insn_mo
= &dummy_opcode
;
1455 else if (pinfo
& INSN_COND_BRANCH_LIKELY
)
1457 /* We don't yet optimize a branch likely. What we should do
1458 is look at the target, copy the instruction found there
1459 into the delay slot, and increment the branch to jump to
1460 the next instruction. */
1462 /* Update the previous insn information. */
1463 prev_prev_insn
= *ip
;
1464 prev_insn
.insn_mo
= &dummy_opcode
;
1468 /* Update the previous insn information. */
1470 prev_prev_insn
.insn_mo
= &dummy_opcode
;
1472 prev_prev_insn
= prev_insn
;
1475 /* Any time we see a branch, we always fill the delay slot
1476 immediately; since this insn is not a branch, we know it
1477 is not in a delay slot. */
1478 prev_insn_is_delay_slot
= 0;
1481 prev_prev_insn_unreordered
= prev_insn_unreordered
;
1482 prev_insn_unreordered
= 0;
1483 prev_insn_frag
= frag_now
;
1484 prev_insn_where
= f
- frag_now
->fr_literal
;
1485 prev_insn_fixp
= fixp
;
1486 prev_insn_valid
= 1;
1489 /* We just output an insn, so the next one doesn't have a label. */
1493 /* This function forgets that there was any previous instruction or
1497 mips_no_prev_insn ()
1499 prev_insn
.insn_mo
= &dummy_opcode
;
1500 prev_prev_insn
.insn_mo
= &dummy_opcode
;
1501 prev_insn_valid
= 0;
1502 prev_insn_is_delay_slot
= 0;
1503 prev_insn_unreordered
= 0;
1504 prev_prev_insn_unreordered
= 0;
1508 /* This function must be called whenever we turn on noreorder or emit
1509 something other than instructions. It inserts any NOPS which might
1510 be needed by the previous instruction, and clears the information
1511 kept for the previous instructions. */
1516 if (! mips_noreorder
)
1522 && (! cop_interlocks
1523 && (prev_insn
.insn_mo
->pinfo
1524 & (INSN_LOAD_COPROC_DELAY
1525 | INSN_COPROC_MOVE_DELAY
1526 | INSN_WRITE_COND_CODE
))))
1528 && (prev_insn
.insn_mo
->pinfo
1532 && (prev_insn
.insn_mo
->pinfo
1533 & (INSN_LOAD_MEMORY_DELAY
1534 | INSN_COPROC_MEMORY_DELAY
))))
1538 && (! cop_interlocks
1539 && prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
))
1541 && ((prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
1542 || (prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
))))
1545 else if ((mips_isa
< 4
1546 && (! cop_interlocks
1547 && prev_prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
))
1549 && ((prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
1550 || (prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
))))
1555 if (insn_label
!= NULL
)
1557 assert (S_GET_SEGMENT (insn_label
) == now_seg
);
1558 insn_label
->sy_frag
= frag_now
;
1559 S_SET_VALUE (insn_label
, (valueT
) frag_now_fix ());
1564 mips_no_prev_insn ();
1567 /* Build an instruction created by a macro expansion. This is passed
1568 a pointer to the count of instructions created so far, an
1569 expression, the name of the instruction to build, an operand format
1570 string, and corresponding arguments. */
1574 macro_build (char *place
,
1582 macro_build (place
, counter
, ep
, name
, fmt
, va_alist
)
1591 struct mips_cl_insn insn
;
1592 bfd_reloc_code_real_type r
;
1596 va_start (args
, fmt
);
1602 * If the macro is about to expand into a second instruction,
1603 * print a warning if needed. We need to pass ip as a parameter
1604 * to generate a better warning message here...
1606 if (mips_warn_about_macros
&& place
== NULL
&& *counter
== 1)
1607 as_warn ("Macro instruction expanded into multiple instructions");
1610 *counter
+= 1; /* bump instruction counter */
1612 r
= BFD_RELOC_UNUSED
;
1613 insn
.insn_mo
= (struct mips_opcode
*) hash_find (op_hash
, name
);
1614 assert (insn
.insn_mo
);
1615 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
1617 while (strcmp (fmt
, insn
.insn_mo
->args
) != 0
1618 || insn
.insn_mo
->pinfo
== INSN_MACRO
1619 || ((insn
.insn_mo
->pinfo
& INSN_ISA
) == INSN_ISA2
1621 || ((insn
.insn_mo
->pinfo
& INSN_ISA
) == INSN_ISA3
1623 || ((insn
.insn_mo
->pinfo
& INSN_ISA
) == INSN_ISA4
1625 || ((insn
.insn_mo
->pinfo
& INSN_ISA
) == INSN_4650
1627 || ((insn
.insn_mo
->pinfo
& INSN_ISA
) == INSN_4010
1629 || ((insn
.insn_mo
->pinfo
& INSN_ISA
) == INSN_4100
1633 assert (insn
.insn_mo
->name
);
1634 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
1636 insn
.insn_opcode
= insn
.insn_mo
->match
;
1652 insn
.insn_opcode
|= va_arg (args
, int) << 16;
1658 insn
.insn_opcode
|= va_arg (args
, int) << 16;
1663 insn
.insn_opcode
|= va_arg (args
, int) << 11;
1668 insn
.insn_opcode
|= va_arg (args
, int) << 11;
1675 insn
.insn_opcode
|= va_arg (args
, int) << 6;
1679 insn
.insn_opcode
|= va_arg (args
, int) << 6;
1683 insn
.insn_opcode
|= va_arg (args
, int) << 6;
1690 insn
.insn_opcode
|= va_arg (args
, int) << 21;
1696 r
= (bfd_reloc_code_real_type
) va_arg (args
, int);
1697 assert (r
== BFD_RELOC_MIPS_GPREL
1698 || r
== BFD_RELOC_MIPS_LITERAL
1699 || r
== BFD_RELOC_LO16
1700 || r
== BFD_RELOC_MIPS_GOT16
1701 || r
== BFD_RELOC_MIPS_CALL16
1702 || r
== BFD_RELOC_MIPS_GOT_LO16
1703 || r
== BFD_RELOC_MIPS_CALL_LO16
1704 || (ep
->X_op
== O_subtract
1705 && now_seg
== text_section
1706 && r
== BFD_RELOC_PCREL_LO16
));
1710 r
= (bfd_reloc_code_real_type
) va_arg (args
, int);
1712 && (ep
->X_op
== O_constant
1713 || (ep
->X_op
== O_symbol
1714 && (r
== BFD_RELOC_HI16_S
1715 || r
== BFD_RELOC_HI16
1716 || r
== BFD_RELOC_MIPS_GOT_HI16
1717 || r
== BFD_RELOC_MIPS_CALL_HI16
))
1718 || (ep
->X_op
== O_subtract
1719 && now_seg
== text_section
1720 && r
== BFD_RELOC_PCREL_HI16_S
)));
1721 if (ep
->X_op
== O_constant
)
1723 insn
.insn_opcode
|= (ep
->X_add_number
>> 16) & 0xffff;
1725 r
= BFD_RELOC_UNUSED
;
1730 assert (ep
!= NULL
);
1732 * This allows macro() to pass an immediate expression for
1733 * creating short branches without creating a symbol.
1734 * Note that the expression still might come from the assembly
1735 * input, in which case the value is not checked for range nor
1736 * is a relocation entry generated (yuck).
1738 if (ep
->X_op
== O_constant
)
1740 insn
.insn_opcode
|= (ep
->X_add_number
>> 2) & 0xffff;
1744 r
= BFD_RELOC_16_PCREL_S2
;
1748 assert (ep
!= NULL
);
1749 r
= BFD_RELOC_MIPS_JMP
;
1758 assert (r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
1760 append_insn (place
, &insn
, ep
, r
, false);
1764 * Generate a "lui" instruction.
1767 macro_build_lui (place
, counter
, ep
, regnum
)
1773 expressionS high_expr
;
1774 struct mips_cl_insn insn
;
1775 bfd_reloc_code_real_type r
;
1776 CONST
char *name
= "lui";
1777 CONST
char *fmt
= "t,u";
1783 high_expr
.X_op
= O_constant
;
1784 high_expr
.X_add_number
= ep
->X_add_number
;
1787 if (high_expr
.X_op
== O_constant
)
1789 /* we can compute the instruction now without a relocation entry */
1790 if (high_expr
.X_add_number
& 0x8000)
1791 high_expr
.X_add_number
+= 0x10000;
1792 high_expr
.X_add_number
=
1793 ((unsigned long) high_expr
.X_add_number
>> 16) & 0xffff;
1794 r
= BFD_RELOC_UNUSED
;
1798 assert (ep
->X_op
== O_symbol
);
1799 /* _gp_disp is a special case, used from s_cpload. */
1800 assert (mips_pic
== NO_PIC
1801 || strcmp (S_GET_NAME (ep
->X_add_symbol
), "_gp_disp") == 0);
1802 r
= BFD_RELOC_HI16_S
;
1806 * If the macro is about to expand into a second instruction,
1807 * print a warning if needed. We need to pass ip as a parameter
1808 * to generate a better warning message here...
1810 if (mips_warn_about_macros
&& place
== NULL
&& *counter
== 1)
1811 as_warn ("Macro instruction expanded into multiple instructions");
1814 *counter
+= 1; /* bump instruction counter */
1816 insn
.insn_mo
= (struct mips_opcode
*) hash_find (op_hash
, name
);
1817 assert (insn
.insn_mo
);
1818 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
1819 assert (strcmp (fmt
, insn
.insn_mo
->args
) == 0);
1821 insn
.insn_opcode
= insn
.insn_mo
->match
| (regnum
<< OP_SH_RT
);
1822 if (r
== BFD_RELOC_UNUSED
)
1824 insn
.insn_opcode
|= high_expr
.X_add_number
;
1825 append_insn (place
, &insn
, NULL
, r
, false);
1828 append_insn (place
, &insn
, &high_expr
, r
, false);
1832 * Generates code to set the $at register to true (one)
1833 * if reg is less than the immediate expression.
1836 set_at (counter
, reg
, unsignedp
)
1841 if (imm_expr
.X_add_number
>= -0x8000 && imm_expr
.X_add_number
< 0x8000)
1842 macro_build ((char *) NULL
, counter
, &imm_expr
,
1843 unsignedp
? "sltiu" : "slti",
1844 "t,r,j", AT
, reg
, (int) BFD_RELOC_LO16
);
1847 load_register (counter
, AT
, &imm_expr
, 0);
1848 macro_build ((char *) NULL
, counter
, NULL
,
1849 unsignedp
? "sltu" : "slt",
1850 "d,v,t", AT
, reg
, AT
);
1854 /* Warn if an expression is not a constant. */
1857 check_absolute_expr (ip
, ex
)
1858 struct mips_cl_insn
*ip
;
1861 if (ex
->X_op
!= O_constant
)
1862 as_warn ("Instruction %s requires absolute expression", ip
->insn_mo
->name
);
1866 * This routine generates the least number of instructions neccessary to load
1867 * an absolute expression value into a register.
1870 load_register (counter
, reg
, ep
, dbl
)
1877 expressionS hi32
, lo32
, tmp
;
1879 if (ep
->X_op
!= O_big
)
1881 assert (ep
->X_op
== O_constant
);
1882 if (ep
->X_add_number
< 0x8000
1883 && (ep
->X_add_number
>= 0
1884 || (ep
->X_add_number
>= -0x8000
1887 || sizeof (ep
->X_add_number
) > 4))))
1889 /* We can handle 16 bit signed values with an addiu to
1890 $zero. No need to ever use daddiu here, since $zero and
1891 the result are always correct in 32 bit mode. */
1892 macro_build ((char *) NULL
, counter
, ep
, "addiu", "t,r,j", reg
, 0,
1893 (int) BFD_RELOC_LO16
);
1896 else if (ep
->X_add_number
>= 0 && ep
->X_add_number
< 0x10000)
1898 /* We can handle 16 bit unsigned values with an ori to
1900 macro_build ((char *) NULL
, counter
, ep
, "ori", "t,r,i", reg
, 0,
1901 (int) BFD_RELOC_LO16
);
1904 else if ((((ep
->X_add_number
&~ (offsetT
) 0x7fffffff) == 0
1905 || ((ep
->X_add_number
&~ (offsetT
) 0x7fffffff)
1906 == ~ (offsetT
) 0x7fffffff))
1909 || sizeof (ep
->X_add_number
) > 4
1910 || (ep
->X_add_number
& 0x80000000) == 0))
1912 && (ep
->X_add_number
&~ 0xffffffff) == 0))
1914 /* 32 bit values require an lui. */
1915 macro_build ((char *) NULL
, counter
, ep
, "lui", "t,u", reg
,
1916 (int) BFD_RELOC_HI16
);
1917 if ((ep
->X_add_number
& 0xffff) != 0)
1918 macro_build ((char *) NULL
, counter
, ep
, "ori", "t,r,i", reg
, reg
,
1919 (int) BFD_RELOC_LO16
);
1924 /* 32 bit value with high bit set being loaded into a 64 bit
1925 register. We can't use lui, because that would
1926 incorrectly set the 32 high bits. */
1927 generic_bignum
[3] = 0;
1928 generic_bignum
[2] = 0;
1929 generic_bignum
[1] = (ep
->X_add_number
>> 16) & 0xffff;
1930 generic_bignum
[0] = ep
->X_add_number
& 0xffff;
1932 tmp
.X_add_number
= 4;
1937 /* The value is larger than 32 bits. */
1941 as_bad ("Number larger than 32 bits");
1942 macro_build ((char *) NULL
, counter
, ep
, "addiu", "t,r,j", reg
, 0,
1943 (int) BFD_RELOC_LO16
);
1947 if (ep
->X_op
!= O_big
)
1951 hi32
.X_add_number
>>= shift
;
1952 hi32
.X_add_number
&= 0xffffffff;
1953 if ((hi32
.X_add_number
& 0x80000000) != 0)
1954 hi32
.X_add_number
|= ~ (offsetT
) 0xffffffff;
1956 lo32
.X_add_number
&= 0xffffffff;
1960 assert (ep
->X_add_number
> 2);
1961 if (ep
->X_add_number
== 3)
1962 generic_bignum
[3] = 0;
1963 else if (ep
->X_add_number
> 4)
1964 as_bad ("Number larger than 64 bits");
1965 lo32
.X_op
= O_constant
;
1966 lo32
.X_add_number
= generic_bignum
[0] + (generic_bignum
[1] << 16);
1967 hi32
.X_op
= O_constant
;
1968 hi32
.X_add_number
= generic_bignum
[2] + (generic_bignum
[3] << 16);
1971 if (hi32
.X_add_number
== 0)
1975 if (hi32
.X_add_number
== 0xffffffff)
1977 if ((lo32
.X_add_number
& 0xffff8000) == 0xffff8000)
1979 macro_build ((char *) NULL
, counter
, &lo32
, "addiu", "t,r,j", reg
, 0,
1980 (int) BFD_RELOC_LO16
);
1983 if (lo32
.X_add_number
& 0x80000000)
1985 macro_build ((char *) NULL
, counter
, &lo32
, "lui", "t,u", reg
,
1986 (int) BFD_RELOC_HI16
);
1987 macro_build ((char *) NULL
, counter
, &lo32
, "ori", "t,r,i", reg
, reg
,
1988 (int) BFD_RELOC_LO16
);
1992 load_register (counter
, reg
, &hi32
, 0);
1995 if ((lo32
.X_add_number
& 0xffff0000) == 0)
1999 macro_build ((char *) NULL
, counter
, NULL
, "dsll32", "d,w,<", reg
,
2008 if ((freg
== 0) && (lo32
.X_add_number
== 0xffffffff))
2010 macro_build ((char *) NULL
, counter
, &lo32
, "lui", "t,u", reg
,
2011 (int) BFD_RELOC_HI16
);
2012 macro_build ((char *) NULL
, counter
, NULL
, "dsrl32", "d,w,<", reg
,
2019 macro_build ((char *) NULL
, counter
, NULL
, "dsll", "d,w,<", reg
,
2024 mid16
.X_add_number
>>= 16;
2025 macro_build ((char *) NULL
, counter
, &mid16
, "ori", "t,r,i", reg
,
2026 freg
, (int) BFD_RELOC_LO16
);
2027 macro_build ((char *) NULL
, counter
, NULL
, "dsll", "d,w,<", reg
,
2031 if ((lo32
.X_add_number
& 0xffff) != 0)
2032 macro_build ((char *) NULL
, counter
, &lo32
, "ori", "t,r,i", reg
, freg
,
2033 (int) BFD_RELOC_LO16
);
2036 /* Load an address into a register. */
2039 load_address (counter
, reg
, ep
)
2046 if (ep
->X_op
!= O_constant
2047 && ep
->X_op
!= O_symbol
)
2049 as_bad ("expression too complex");
2050 ep
->X_op
= O_constant
;
2053 if (ep
->X_op
== O_constant
)
2055 load_register (counter
, reg
, ep
, 0);
2059 if (mips_pic
== NO_PIC
)
2061 /* If this is a reference to a GP relative symbol, we want
2062 addiu $reg,$gp,<sym> (BFD_RELOC_MIPS_GPREL)
2064 lui $reg,<sym> (BFD_RELOC_HI16_S)
2065 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
2066 If we have an addend, we always use the latter form. */
2067 if ((valueT
) ep
->X_add_number
>= MAX_GPREL_OFFSET
2068 || nopic_need_relax (ep
->X_add_symbol
))
2073 macro_build ((char *) NULL
, counter
, ep
,
2074 mips_isa
< 3 ? "addiu" : "daddiu",
2075 "t,r,j", reg
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
2076 p
= frag_var (rs_machine_dependent
, 8, 0,
2077 RELAX_ENCODE (4, 8, 0, 4, 0, mips_warn_about_macros
),
2078 ep
->X_add_symbol
, (long) 0, (char *) NULL
);
2080 macro_build_lui (p
, counter
, ep
, reg
);
2083 macro_build (p
, counter
, ep
,
2084 mips_isa
< 3 ? "addiu" : "daddiu",
2085 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
2087 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
2091 /* If this is a reference to an external symbol, we want
2092 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
2094 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
2096 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
2097 If there is a constant, it must be added in after. */
2098 ex
.X_add_number
= ep
->X_add_number
;
2099 ep
->X_add_number
= 0;
2101 macro_build ((char *) NULL
, counter
, ep
,
2102 mips_isa
< 3 ? "lw" : "ld",
2103 "t,o(b)", reg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
2104 macro_build ((char *) NULL
, counter
, (expressionS
*) NULL
, "nop", "");
2105 p
= frag_var (rs_machine_dependent
, 4, 0,
2106 RELAX_ENCODE (0, 4, -8, 0, 0, mips_warn_about_macros
),
2107 ep
->X_add_symbol
, (long) 0, (char *) NULL
);
2108 macro_build (p
, counter
, ep
,
2109 mips_isa
< 3 ? "addiu" : "daddiu",
2110 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
2111 if (ex
.X_add_number
!= 0)
2113 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
2114 as_bad ("PIC code offset overflow (max 16 signed bits)");
2115 ex
.X_op
= O_constant
;
2116 macro_build ((char *) NULL
, counter
, &ex
,
2117 mips_isa
< 3 ? "addiu" : "daddiu",
2118 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
2121 else if (mips_pic
== SVR4_PIC
)
2126 /* This is the large GOT case. If this is a reference to an
2127 external symbol, we want
2128 lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
2130 lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16)
2131 Otherwise, for a reference to a local symbol, we want
2132 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
2134 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
2135 If there is a constant, it must be added in after. */
2136 ex
.X_add_number
= ep
->X_add_number
;
2137 ep
->X_add_number
= 0;
2138 if (reg_needs_delay (GP
))
2143 macro_build ((char *) NULL
, counter
, ep
, "lui", "t,u", reg
,
2144 (int) BFD_RELOC_MIPS_GOT_HI16
);
2145 macro_build ((char *) NULL
, counter
, (expressionS
*) NULL
,
2146 mips_isa
< 3 ? "addu" : "daddu",
2147 "d,v,t", reg
, reg
, GP
);
2148 macro_build ((char *) NULL
, counter
, ep
,
2149 mips_isa
< 3 ? "lw" : "ld",
2150 "t,o(b)", reg
, (int) BFD_RELOC_MIPS_GOT_LO16
, reg
);
2151 p
= frag_var (rs_machine_dependent
, 12 + off
, 0,
2152 RELAX_ENCODE (12, 12 + off
, off
, 8 + off
, 0,
2153 mips_warn_about_macros
),
2154 ep
->X_add_symbol
, (long) 0, (char *) NULL
);
2157 /* We need a nop before loading from $gp. This special
2158 check is required because the lui which starts the main
2159 instruction stream does not refer to $gp, and so will not
2160 insert the nop which may be required. */
2161 macro_build (p
, counter
, (expressionS
*) NULL
, "nop", "");
2164 macro_build (p
, counter
, ep
,
2165 mips_isa
< 3 ? "lw" : "ld",
2166 "t,o(b)", reg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
2168 macro_build (p
, counter
, (expressionS
*) NULL
, "nop", "");
2170 macro_build (p
, counter
, ep
,
2171 mips_isa
< 3 ? "addiu" : "daddiu",
2172 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
2173 if (ex
.X_add_number
!= 0)
2175 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
2176 as_bad ("PIC code offset overflow (max 16 signed bits)");
2177 ex
.X_op
= O_constant
;
2178 macro_build ((char *) NULL
, counter
, &ex
,
2179 mips_isa
< 3 ? "addiu" : "daddiu",
2180 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
2183 else if (mips_pic
== EMBEDDED_PIC
)
2186 addiu $reg,$gp,<sym> (BFD_RELOC_MIPS_GPREL)
2188 macro_build ((char *) NULL
, counter
, ep
,
2189 mips_isa
< 3 ? "addiu" : "daddiu",
2190 "t,r,j", reg
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
2198 * This routine implements the seemingly endless macro or synthesized
2199 * instructions and addressing modes in the mips assembly language. Many
2200 * of these macros are simple and are similar to each other. These could
2201 * probably be handled by some kind of table or grammer aproach instead of
2202 * this verbose method. Others are not simple macros but are more like
2203 * optimizing code generation.
2204 * One interesting optimization is when several store macros appear
2205 * consecutivly that would load AT with the upper half of the same address.
2206 * The ensuing load upper instructions are ommited. This implies some kind
2207 * of global optimization. We currently only optimize within a single macro.
2208 * For many of the load and store macros if the address is specified as a
2209 * constant expression in the first 64k of memory (ie ld $2,0x4000c) we
2210 * first load register 'at' with zero and use it as the base register. The
2211 * mips assembler simply uses register $zero. Just one tiny optimization
2216 struct mips_cl_insn
*ip
;
2218 register int treg
, sreg
, dreg
, breg
;
2233 bfd_reloc_code_real_type r
;
2235 int hold_mips_optimize
;
2237 treg
= (ip
->insn_opcode
>> 16) & 0x1f;
2238 dreg
= (ip
->insn_opcode
>> 11) & 0x1f;
2239 sreg
= breg
= (ip
->insn_opcode
>> 21) & 0x1f;
2240 mask
= ip
->insn_mo
->mask
;
2242 expr1
.X_op
= O_constant
;
2243 expr1
.X_op_symbol
= NULL
;
2244 expr1
.X_add_symbol
= NULL
;
2245 expr1
.X_add_number
= 1;
2257 mips_emit_delays ();
2259 mips_any_noreorder
= 1;
2261 expr1
.X_add_number
= 8;
2262 macro_build ((char *) NULL
, &icnt
, &expr1
, "bgez", "s,p", sreg
);
2264 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
2266 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
, sreg
, 0);
2267 macro_build ((char *) NULL
, &icnt
, NULL
,
2268 dbl
? "dsub" : "sub",
2269 "d,v,t", dreg
, 0, sreg
);
2292 if (imm_expr
.X_add_number
>= -0x8000 && imm_expr
.X_add_number
< 0x8000)
2294 macro_build ((char *) NULL
, &icnt
, &imm_expr
, s
, "t,r,j", treg
, sreg
,
2295 (int) BFD_RELOC_LO16
);
2298 load_register (&icnt
, AT
, &imm_expr
, dbl
);
2299 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "d,v,t", treg
, sreg
, AT
);
2318 if (imm_expr
.X_add_number
>= 0 && imm_expr
.X_add_number
< 0x10000)
2320 if (mask
!= M_NOR_I
)
2321 macro_build ((char *) NULL
, &icnt
, &imm_expr
, s
, "t,r,i", treg
,
2322 sreg
, (int) BFD_RELOC_LO16
);
2325 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "ori", "t,r,i",
2326 treg
, sreg
, (int) BFD_RELOC_LO16
);
2327 macro_build ((char *) NULL
, &icnt
, NULL
, "nor", "d,v,t",
2333 load_register (&icnt
, AT
, &imm_expr
, 0);
2334 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "d,v,t", treg
, sreg
, AT
);
2351 if (imm_expr
.X_add_number
== 0)
2353 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "s,t,p", sreg
,
2357 load_register (&icnt
, AT
, &imm_expr
, 0);
2358 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "s,t,p", sreg
, AT
);
2366 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2367 likely
? "bgezl" : "bgez",
2373 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2374 likely
? "blezl" : "blez",
2378 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", AT
, sreg
, treg
);
2379 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2380 likely
? "beql" : "beq",
2387 /* check for > max integer */
2388 maxnum
= 0x7fffffff;
2396 if (imm_expr
.X_add_number
>= maxnum
2397 && (mips_isa
< 3 || sizeof (maxnum
) > 4))
2400 /* result is always false */
2403 as_warn ("Branch %s is always false (nop)", ip
->insn_mo
->name
);
2404 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
2408 as_warn ("Branch likely %s is always false", ip
->insn_mo
->name
);
2409 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "bnel",
2414 imm_expr
.X_add_number
++;
2418 if (mask
== M_BGEL_I
)
2420 if (imm_expr
.X_add_number
== 0)
2422 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2423 likely
? "bgezl" : "bgez",
2427 if (imm_expr
.X_add_number
== 1)
2429 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2430 likely
? "bgtzl" : "bgtz",
2434 maxnum
= 0x7fffffff;
2442 maxnum
= - maxnum
- 1;
2443 if (imm_expr
.X_add_number
<= maxnum
2444 && (mips_isa
< 3 || sizeof (maxnum
) > 4))
2447 /* result is always true */
2448 as_warn ("Branch %s is always true", ip
->insn_mo
->name
);
2449 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "b", "p");
2452 set_at (&icnt
, sreg
, 0);
2453 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2454 likely
? "beql" : "beq",
2465 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2466 likely
? "beql" : "beq",
2470 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", AT
, sreg
,
2472 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2473 likely
? "beql" : "beq",
2480 if (sreg
== 0 || imm_expr
.X_add_number
== -1)
2482 imm_expr
.X_add_number
++;
2486 if (mask
== M_BGEUL_I
)
2488 if (imm_expr
.X_add_number
== 0)
2490 if (imm_expr
.X_add_number
== 1)
2492 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2493 likely
? "bnel" : "bne",
2497 set_at (&icnt
, sreg
, 1);
2498 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2499 likely
? "beql" : "beq",
2508 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2509 likely
? "bgtzl" : "bgtz",
2515 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2516 likely
? "bltzl" : "bltz",
2520 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", AT
, treg
, sreg
);
2521 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2522 likely
? "bnel" : "bne",
2531 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2532 likely
? "bnel" : "bne",
2538 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", AT
, treg
,
2540 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2541 likely
? "bnel" : "bne",
2550 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2551 likely
? "blezl" : "blez",
2557 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2558 likely
? "bgezl" : "bgez",
2562 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", AT
, treg
, sreg
);
2563 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2564 likely
? "beql" : "beq",
2571 maxnum
= 0x7fffffff;
2579 if (imm_expr
.X_add_number
>= maxnum
2580 && (mips_isa
< 3 || sizeof (maxnum
) > 4))
2582 imm_expr
.X_add_number
++;
2586 if (mask
== M_BLTL_I
)
2588 if (imm_expr
.X_add_number
== 0)
2590 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2591 likely
? "bltzl" : "bltz",
2595 if (imm_expr
.X_add_number
== 1)
2597 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2598 likely
? "blezl" : "blez",
2602 set_at (&icnt
, sreg
, 0);
2603 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2604 likely
? "bnel" : "bne",
2613 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2614 likely
? "beql" : "beq",
2620 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", AT
, treg
,
2622 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2623 likely
? "beql" : "beq",
2630 if (sreg
== 0 || imm_expr
.X_add_number
== -1)
2632 imm_expr
.X_add_number
++;
2636 if (mask
== M_BLTUL_I
)
2638 if (imm_expr
.X_add_number
== 0)
2640 if (imm_expr
.X_add_number
== 1)
2642 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2643 likely
? "beql" : "beq",
2647 set_at (&icnt
, sreg
, 1);
2648 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2649 likely
? "bnel" : "bne",
2658 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2659 likely
? "bltzl" : "bltz",
2665 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2666 likely
? "bgtzl" : "bgtz",
2670 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", AT
, sreg
, treg
);
2671 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2672 likely
? "bnel" : "bne",
2683 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2684 likely
? "bnel" : "bne",
2688 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", AT
, sreg
,
2690 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2691 likely
? "bnel" : "bne",
2707 as_warn ("Divide by zero.");
2709 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", 0, 0);
2711 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 7);
2715 mips_emit_delays ();
2717 mips_any_noreorder
= 1;
2718 macro_build ((char *) NULL
, &icnt
, NULL
,
2719 dbl
? "ddiv" : "div",
2720 "z,s,t", sreg
, treg
);
2722 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", treg
, 0);
2725 expr1
.X_add_number
= 8;
2726 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", treg
, 0);
2727 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
2728 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 7);
2730 expr1
.X_add_number
= -1;
2731 macro_build ((char *) NULL
, &icnt
, &expr1
,
2732 dbl
? "daddiu" : "addiu",
2733 "t,r,j", AT
, 0, (int) BFD_RELOC_LO16
);
2734 expr1
.X_add_number
= mips_trap
? (dbl
? 12 : 8) : (dbl
? 20 : 16);
2735 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", treg
, AT
);
2738 expr1
.X_add_number
= 1;
2739 macro_build ((char *) NULL
, &icnt
, &expr1
, "daddiu", "t,r,j", AT
, 0,
2740 (int) BFD_RELOC_LO16
);
2741 macro_build ((char *) NULL
, &icnt
, NULL
, "dsll32", "d,w,<", AT
, AT
,
2746 expr1
.X_add_number
= 0x80000000;
2747 macro_build ((char *) NULL
, &icnt
, &expr1
, "lui", "t,u", AT
,
2748 (int) BFD_RELOC_HI16
);
2751 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", sreg
, AT
);
2754 expr1
.X_add_number
= 8;
2755 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", sreg
, AT
);
2756 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
2757 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 6);
2760 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d", dreg
);
2799 if (imm_expr
.X_add_number
== 0)
2801 as_warn ("Divide by zero.");
2803 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", 0, 0);
2805 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 7);
2808 if (imm_expr
.X_add_number
== 1)
2810 if (strcmp (s2
, "mflo") == 0)
2811 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
,
2814 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
, 0);
2817 if (imm_expr
.X_add_number
== -1
2818 && s
[strlen (s
) - 1] != 'u')
2820 if (strcmp (s2
, "mflo") == 0)
2823 macro_build ((char *) NULL
, &icnt
, NULL
, "dneg", "d,w", dreg
,
2826 macro_build ((char *) NULL
, &icnt
, NULL
, "neg", "d,w", dreg
,
2830 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
, 0);
2834 load_register (&icnt
, AT
, &imm_expr
, dbl
);
2835 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "z,s,t", sreg
, AT
);
2836 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "d", dreg
);
2855 mips_emit_delays ();
2857 mips_any_noreorder
= 1;
2858 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "z,s,t", sreg
, treg
);
2860 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", treg
, 0);
2863 expr1
.X_add_number
= 8;
2864 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", treg
, 0);
2865 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
2866 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 7);
2869 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "d", dreg
);
2875 /* Load the address of a symbol into a register. If breg is not
2876 zero, we then add a base register to it. */
2878 /* When generating embedded PIC code, we permit expressions of
2881 where bar is an address in the .text section. These are used
2882 when getting the addresses of functions. We don't permit
2883 X_add_number to be non-zero, because if the symbol is
2884 external the relaxing code needs to know that any addend is
2885 purely the offset to X_op_symbol. */
2886 if (mips_pic
== EMBEDDED_PIC
2887 && offset_expr
.X_op
== O_subtract
2888 && now_seg
== text_section
2889 && (offset_expr
.X_op_symbol
->sy_value
.X_op
== O_constant
2890 ? S_GET_SEGMENT (offset_expr
.X_op_symbol
) == text_section
2891 : (offset_expr
.X_op_symbol
->sy_value
.X_op
== O_symbol
2892 && (S_GET_SEGMENT (offset_expr
.X_op_symbol
2893 ->sy_value
.X_add_symbol
)
2896 && offset_expr
.X_add_number
== 0)
2898 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
2899 treg
, (int) BFD_RELOC_PCREL_HI16_S
);
2900 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2901 mips_isa
< 3 ? "addiu" : "daddiu",
2902 "t,r,j", treg
, treg
, (int) BFD_RELOC_PCREL_LO16
);
2906 if (offset_expr
.X_op
!= O_symbol
2907 && offset_expr
.X_op
!= O_constant
)
2909 as_bad ("expression too complex");
2910 offset_expr
.X_op
= O_constant
;
2924 if (offset_expr
.X_op
== O_constant
)
2925 load_register (&icnt
, tempreg
, &offset_expr
, dbl
);
2926 else if (mips_pic
== NO_PIC
)
2928 /* If this is a reference to an GP relative symbol, we want
2929 addiu $tempreg,$gp,<sym> (BFD_RELOC_MIPS_GPREL)
2931 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
2932 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
2933 If we have a constant, we need two instructions anyhow,
2934 so we may as well always use the latter form. */
2935 if ((valueT
) offset_expr
.X_add_number
>= MAX_GPREL_OFFSET
2936 || nopic_need_relax (offset_expr
.X_add_symbol
))
2941 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2942 mips_isa
< 3 ? "addiu" : "daddiu",
2943 "t,r,j", tempreg
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
2944 p
= frag_var (rs_machine_dependent
, 8, 0,
2945 RELAX_ENCODE (4, 8, 0, 4, 0,
2946 mips_warn_about_macros
),
2947 offset_expr
.X_add_symbol
, (long) 0,
2950 macro_build_lui (p
, &icnt
, &offset_expr
, tempreg
);
2953 macro_build (p
, &icnt
, &offset_expr
,
2954 mips_isa
< 3 ? "addiu" : "daddiu",
2955 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
2957 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
2959 /* If this is a reference to an external symbol, and there
2960 is no constant, we want
2961 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
2962 For a local symbol, we want
2963 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
2965 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
2967 If we have a small constant, and this is a reference to
2968 an external symbol, we want
2969 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
2971 addiu $tempreg,$tempreg,<constant>
2972 For a local symbol, we want the same instruction
2973 sequence, but we output a BFD_RELOC_LO16 reloc on the
2976 If we have a large constant, and this is a reference to
2977 an external symbol, we want
2978 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
2979 lui $at,<hiconstant>
2980 addiu $at,$at,<loconstant>
2981 addu $tempreg,$tempreg,$at
2982 For a local symbol, we want the same instruction
2983 sequence, but we output a BFD_RELOC_LO16 reloc on the
2984 addiu instruction. */
2985 expr1
.X_add_number
= offset_expr
.X_add_number
;
2986 offset_expr
.X_add_number
= 0;
2988 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2990 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
2991 if (expr1
.X_add_number
== 0)
2999 /* We're going to put in an addu instruction using
3000 tempreg, so we may as well insert the nop right
3002 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3006 p
= frag_var (rs_machine_dependent
, 8 - off
, 0,
3007 RELAX_ENCODE (0, 8 - off
, -4 - off
, 4 - off
, 0,
3009 ? mips_warn_about_macros
3011 offset_expr
.X_add_symbol
, (long) 0,
3015 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
3018 macro_build (p
, &icnt
, &expr1
,
3019 mips_isa
< 3 ? "addiu" : "daddiu",
3020 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
3021 /* FIXME: If breg == 0, and the next instruction uses
3022 $tempreg, then if this variant case is used an extra
3023 nop will be generated. */
3025 else if (expr1
.X_add_number
>= -0x8000
3026 && expr1
.X_add_number
< 0x8000)
3028 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3030 macro_build ((char *) NULL
, &icnt
, &expr1
,
3031 mips_isa
< 3 ? "addiu" : "daddiu",
3032 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
3033 (void) frag_var (rs_machine_dependent
, 0, 0,
3034 RELAX_ENCODE (0, 0, -12, -4, 0, 0),
3035 offset_expr
.X_add_symbol
, (long) 0,
3042 /* If we are going to add in a base register, and the
3043 target register and the base register are the same,
3044 then we are using AT as a temporary register. Since
3045 we want to load the constant into AT, we add our
3046 current AT (from the global offset table) and the
3047 register into the register now, and pretend we were
3048 not using a base register. */
3053 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3055 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3056 mips_isa
< 3 ? "addu" : "daddu",
3057 "d,v,t", treg
, AT
, breg
);
3063 /* Set mips_optimize around the lui instruction to avoid
3064 inserting an unnecessary nop after the lw. */
3065 hold_mips_optimize
= mips_optimize
;
3067 macro_build_lui ((char *) NULL
, &icnt
, &expr1
, AT
);
3068 mips_optimize
= hold_mips_optimize
;
3070 macro_build ((char *) NULL
, &icnt
, &expr1
,
3071 mips_isa
< 3 ? "addiu" : "daddiu",
3072 "t,r,j", AT
, AT
, (int) BFD_RELOC_LO16
);
3073 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3074 mips_isa
< 3 ? "addu" : "daddu",
3075 "d,v,t", tempreg
, tempreg
, AT
);
3076 (void) frag_var (rs_machine_dependent
, 0, 0,
3077 RELAX_ENCODE (0, 0, -16 + off1
, -8, 0, 0),
3078 offset_expr
.X_add_symbol
, (long) 0,
3083 else if (mips_pic
== SVR4_PIC
)
3087 /* This is the large GOT case. If this is a reference to an
3088 external symbol, and there is no constant, we want
3089 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
3090 addu $tempreg,$tempreg,$gp
3091 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
3092 For a local symbol, we want
3093 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3095 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
3097 If we have a small constant, and this is a reference to
3098 an external symbol, we want
3099 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
3100 addu $tempreg,$tempreg,$gp
3101 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
3103 addiu $tempreg,$tempreg,<constant>
3104 For a local symbol, we want
3105 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3107 addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16)
3109 If we have a large constant, and this is a reference to
3110 an external symbol, we want
3111 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
3112 addu $tempreg,$tempreg,$gp
3113 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
3114 lui $at,<hiconstant>
3115 addiu $at,$at,<loconstant>
3116 addu $tempreg,$tempreg,$at
3117 For a local symbol, we want
3118 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3119 lui $at,<hiconstant>
3120 addiu $at,$at,<loconstant> (BFD_RELOC_LO16)
3121 addu $tempreg,$tempreg,$at
3123 expr1
.X_add_number
= offset_expr
.X_add_number
;
3124 offset_expr
.X_add_number
= 0;
3126 if (reg_needs_delay (GP
))
3130 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
3131 tempreg
, (int) BFD_RELOC_MIPS_GOT_HI16
);
3132 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3133 mips_isa
< 3 ? "addu" : "daddu",
3134 "d,v,t", tempreg
, tempreg
, GP
);
3135 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3137 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT_LO16
,
3139 if (expr1
.X_add_number
== 0)
3147 /* We're going to put in an addu instruction using
3148 tempreg, so we may as well insert the nop right
3150 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3155 p
= frag_var (rs_machine_dependent
, 12 + gpdel
, 0,
3156 RELAX_ENCODE (12 + off
, 12 + gpdel
, gpdel
,
3159 ? mips_warn_about_macros
3161 offset_expr
.X_add_symbol
, (long) 0,
3164 else if (expr1
.X_add_number
>= -0x8000
3165 && expr1
.X_add_number
< 0x8000)
3167 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3169 macro_build ((char *) NULL
, &icnt
, &expr1
,
3170 mips_isa
< 3 ? "addiu" : "daddiu",
3171 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
3173 p
= frag_var (rs_machine_dependent
, 12 + gpdel
, 0,
3174 RELAX_ENCODE (20, 12 + gpdel
, gpdel
, 8 + gpdel
, 0,
3176 ? mips_warn_about_macros
3178 offset_expr
.X_add_symbol
, (long) 0,
3185 /* If we are going to add in a base register, and the
3186 target register and the base register are the same,
3187 then we are using AT as a temporary register. Since
3188 we want to load the constant into AT, we add our
3189 current AT (from the global offset table) and the
3190 register into the register now, and pretend we were
3191 not using a base register. */
3199 assert (tempreg
== AT
);
3200 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3202 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3203 mips_isa
< 3 ? "addu" : "daddu",
3204 "d,v,t", treg
, AT
, breg
);
3209 /* Set mips_optimize around the lui instruction to avoid
3210 inserting an unnecessary nop after the lw. */
3211 hold_mips_optimize
= mips_optimize
;
3213 macro_build_lui ((char *) NULL
, &icnt
, &expr1
, AT
);
3214 mips_optimize
= hold_mips_optimize
;
3216 macro_build ((char *) NULL
, &icnt
, &expr1
,
3217 mips_isa
< 3 ? "addiu" : "daddiu",
3218 "t,r,j", AT
, AT
, (int) BFD_RELOC_LO16
);
3219 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3220 mips_isa
< 3 ? "addu" : "daddu",
3221 "d,v,t", dreg
, dreg
, AT
);
3223 p
= frag_var (rs_machine_dependent
, 16 + gpdel
+ adj
, 0,
3224 RELAX_ENCODE (24 + adj
, 16 + gpdel
+ adj
, gpdel
,
3227 ? mips_warn_about_macros
3229 offset_expr
.X_add_symbol
, (long) 0,
3237 /* This is needed because this instruction uses $gp, but
3238 the first instruction on the main stream does not. */
3239 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
3242 macro_build (p
, &icnt
, &offset_expr
,
3244 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
3246 if (expr1
.X_add_number
>= -0x8000
3247 && expr1
.X_add_number
< 0x8000)
3249 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
3251 macro_build (p
, &icnt
, &expr1
,
3252 mips_isa
< 3 ? "addiu" : "daddiu",
3253 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
3254 /* FIXME: If add_number is 0, and there was no base
3255 register, the external symbol case ended with a load,
3256 so if the symbol turns out to not be external, and
3257 the next instruction uses tempreg, an unnecessary nop
3258 will be inserted. */
3264 /* We must add in the base register now, as in the
3265 external symbol case. */
3266 assert (tempreg
== AT
);
3267 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
3269 macro_build (p
, &icnt
, (expressionS
*) NULL
,
3270 mips_isa
< 3 ? "addu" : "daddu",
3271 "d,v,t", treg
, AT
, breg
);
3274 /* We set breg to 0 because we have arranged to add
3275 it in in both cases. */
3279 macro_build_lui (p
, &icnt
, &expr1
, AT
);
3281 macro_build (p
, &icnt
, &expr1
,
3282 mips_isa
< 3 ? "addiu" : "daddiu",
3283 "t,r,j", AT
, AT
, (int) BFD_RELOC_LO16
);
3285 macro_build (p
, &icnt
, (expressionS
*) NULL
,
3286 mips_isa
< 3 ? "addu" : "daddu",
3287 "d,v,t", tempreg
, tempreg
, AT
);
3291 else if (mips_pic
== EMBEDDED_PIC
)
3294 addiu $tempreg,$gp,<sym> (BFD_RELOC_MIPS_GPREL)
3296 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3297 mips_isa
< 3 ? "addiu" : "daddiu",
3298 "t,r,j", tempreg
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
3304 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3305 mips_isa
< 3 ? "addu" : "daddu",
3306 "d,v,t", treg
, tempreg
, breg
);
3314 /* The j instruction may not be used in PIC code, since it
3315 requires an absolute address. We convert it to a b
3317 if (mips_pic
== NO_PIC
)
3318 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "j", "a");
3320 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "b", "p");
3323 /* The jal instructions must be handled as macros because when
3324 generating PIC code they expand to multi-instruction
3325 sequences. Normally they are simple instructions. */
3330 if (mips_pic
== NO_PIC
3331 || mips_pic
== EMBEDDED_PIC
)
3332 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "jalr",
3334 else if (mips_pic
== SVR4_PIC
)
3336 if (sreg
!= PIC_CALL_REG
)
3337 as_warn ("MIPS PIC call to register other than $25");
3339 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "jalr",
3341 if (mips_cprestore_offset
< 0)
3342 as_warn ("No .cprestore pseudo-op used in PIC code");
3345 expr1
.X_add_number
= mips_cprestore_offset
;
3346 macro_build ((char *) NULL
, &icnt
, &expr1
,
3347 mips_isa
< 3 ? "lw" : "ld",
3348 "t,o(b)", GP
, (int) BFD_RELOC_LO16
, mips_frame_reg
);
3357 if (mips_pic
== NO_PIC
)
3358 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "jal", "a");
3359 else if (mips_pic
== SVR4_PIC
)
3361 /* If this is a reference to an external symbol, and we are
3362 using a small GOT, we want
3363 lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
3367 lw $gp,cprestore($sp)
3368 The cprestore value is set using the .cprestore
3369 pseudo-op. If we are using a big GOT, we want
3370 lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16)
3372 lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16)
3376 lw $gp,cprestore($sp)
3377 If the symbol is not external, we want
3378 lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3380 addiu $25,$25,<sym> (BFD_RELOC_LO16)
3383 lw $gp,cprestore($sp) */
3387 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3388 mips_isa
< 3 ? "lw" : "ld",
3389 "t,o(b)", PIC_CALL_REG
,
3390 (int) BFD_RELOC_MIPS_CALL16
, GP
);
3391 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3393 p
= frag_var (rs_machine_dependent
, 4, 0,
3394 RELAX_ENCODE (0, 4, -8, 0, 0, 0),
3395 offset_expr
.X_add_symbol
, (long) 0, (char *) NULL
);
3401 if (reg_needs_delay (GP
))
3405 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
3406 PIC_CALL_REG
, (int) BFD_RELOC_MIPS_CALL_HI16
);
3407 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3408 mips_isa
< 3 ? "addu" : "daddu",
3409 "d,v,t", PIC_CALL_REG
, PIC_CALL_REG
, GP
);
3410 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3411 mips_isa
< 3 ? "lw" : "ld",
3412 "t,o(b)", PIC_CALL_REG
,
3413 (int) BFD_RELOC_MIPS_CALL_LO16
, PIC_CALL_REG
);
3414 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3416 p
= frag_var (rs_machine_dependent
, 12 + gpdel
, 0,
3417 RELAX_ENCODE (16, 12 + gpdel
, gpdel
, 8 + gpdel
,
3419 offset_expr
.X_add_symbol
, (long) 0, (char *) NULL
);
3422 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
3425 macro_build (p
, &icnt
, &offset_expr
,
3426 mips_isa
< 3 ? "lw" : "ld",
3427 "t,o(b)", PIC_CALL_REG
,
3428 (int) BFD_RELOC_MIPS_GOT16
, GP
);
3430 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
3433 macro_build (p
, &icnt
, &offset_expr
,
3434 mips_isa
< 3 ? "addiu" : "daddiu",
3435 "t,r,j", PIC_CALL_REG
, PIC_CALL_REG
,
3436 (int) BFD_RELOC_LO16
);
3437 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3438 "jalr", "s", PIC_CALL_REG
);
3439 if (mips_cprestore_offset
< 0)
3440 as_warn ("No .cprestore pseudo-op used in PIC code");
3444 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3446 expr1
.X_add_number
= mips_cprestore_offset
;
3447 macro_build ((char *) NULL
, &icnt
, &expr1
,
3448 mips_isa
< 3 ? "lw" : "ld",
3449 "t,o(b)", GP
, (int) BFD_RELOC_LO16
,
3453 else if (mips_pic
== EMBEDDED_PIC
)
3455 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "bal", "p");
3456 /* The linker may expand the call to a longer sequence which
3457 uses $at, so we must break rather than return. */
3533 if (breg
== treg
|| coproc
|| lr
)
3602 if (mask
== M_LWC1_AB
3603 || mask
== M_SWC1_AB
3604 || mask
== M_LDC1_AB
3605 || mask
== M_SDC1_AB
3614 if (offset_expr
.X_op
!= O_constant
3615 && offset_expr
.X_op
!= O_symbol
)
3617 as_bad ("expression too complex");
3618 offset_expr
.X_op
= O_constant
;
3621 /* A constant expression in PIC code can be handled just as it
3622 is in non PIC code. */
3623 if (mips_pic
== NO_PIC
3624 || offset_expr
.X_op
== O_constant
)
3626 /* If this is a reference to a GP relative symbol, and there
3627 is no base register, we want
3628 <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL)
3629 Otherwise, if there is no base register, we want
3630 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
3631 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
3632 If we have a constant, we need two instructions anyhow,
3633 so we always use the latter form.
3635 If we have a base register, and this is a reference to a
3636 GP relative symbol, we want
3637 addu $tempreg,$breg,$gp
3638 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GPREL)
3640 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
3641 addu $tempreg,$tempreg,$breg
3642 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
3643 With a constant we always use the latter case. */
3646 if ((valueT
) offset_expr
.X_add_number
>= MAX_GPREL_OFFSET
3647 || nopic_need_relax (offset_expr
.X_add_symbol
))
3652 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
3653 treg
, (int) BFD_RELOC_MIPS_GPREL
, GP
);
3654 p
= frag_var (rs_machine_dependent
, 8, 0,
3655 RELAX_ENCODE (4, 8, 0, 4, 0,
3656 (mips_warn_about_macros
3657 || (used_at
&& mips_noat
))),
3658 offset_expr
.X_add_symbol
, (long) 0,
3662 macro_build_lui (p
, &icnt
, &offset_expr
, tempreg
);
3665 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
, treg
,
3666 (int) BFD_RELOC_LO16
, tempreg
);
3670 if ((valueT
) offset_expr
.X_add_number
>= MAX_GPREL_OFFSET
3671 || nopic_need_relax (offset_expr
.X_add_symbol
))
3676 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3677 mips_isa
< 3 ? "addu" : "daddu",
3678 "d,v,t", tempreg
, breg
, GP
);
3679 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
3680 treg
, (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
3681 p
= frag_var (rs_machine_dependent
, 12, 0,
3682 RELAX_ENCODE (8, 12, 0, 8, 0, 0),
3683 offset_expr
.X_add_symbol
, (long) 0,
3686 macro_build_lui (p
, &icnt
, &offset_expr
, tempreg
);
3689 macro_build (p
, &icnt
, (expressionS
*) NULL
,
3690 mips_isa
< 3 ? "addu" : "daddu",
3691 "d,v,t", tempreg
, tempreg
, breg
);
3694 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
, treg
,
3695 (int) BFD_RELOC_LO16
, tempreg
);
3698 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
3700 /* If this is a reference to an external symbol, we want
3701 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3703 <op> $treg,0($tempreg)
3705 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3707 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
3708 <op> $treg,0($tempreg)
3709 If there is a base register, we add it to $tempreg before
3710 the <op>. If there is a constant, we stick it in the
3711 <op> instruction. We don't handle constants larger than
3712 16 bits, because we have no way to load the upper 16 bits
3713 (actually, we could handle them for the subset of cases
3714 in which we are not using $at). */
3715 assert (offset_expr
.X_op
== O_symbol
);
3716 expr1
.X_add_number
= offset_expr
.X_add_number
;
3717 offset_expr
.X_add_number
= 0;
3718 if (expr1
.X_add_number
< -0x8000
3719 || expr1
.X_add_number
>= 0x8000)
3720 as_bad ("PIC code offset overflow (max 16 signed bits)");
3722 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3723 mips_isa
< 3 ? "lw" : "ld",
3724 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
3725 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
3726 p
= frag_var (rs_machine_dependent
, 4, 0,
3727 RELAX_ENCODE (0, 4, -8, 0, 0, 0),
3728 offset_expr
.X_add_symbol
, (long) 0,
3730 macro_build (p
, &icnt
, &offset_expr
,
3731 mips_isa
< 3 ? "addiu" : "daddiu",
3732 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
3734 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3735 mips_isa
< 3 ? "addu" : "daddu",
3736 "d,v,t", tempreg
, tempreg
, breg
);
3737 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
, treg
,
3738 (int) BFD_RELOC_LO16
, tempreg
);
3740 else if (mips_pic
== SVR4_PIC
)
3744 /* If this is a reference to an external symbol, we want
3745 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
3746 addu $tempreg,$tempreg,$gp
3747 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
3748 <op> $treg,0($tempreg)
3750 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3752 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
3753 <op> $treg,0($tempreg)
3754 If there is a base register, we add it to $tempreg before
3755 the <op>. If there is a constant, we stick it in the
3756 <op> instruction. We don't handle constants larger than
3757 16 bits, because we have no way to load the upper 16 bits
3758 (actually, we could handle them for the subset of cases
3759 in which we are not using $at). */
3760 assert (offset_expr
.X_op
== O_symbol
);
3761 expr1
.X_add_number
= offset_expr
.X_add_number
;
3762 offset_expr
.X_add_number
= 0;
3763 if (expr1
.X_add_number
< -0x8000
3764 || expr1
.X_add_number
>= 0x8000)
3765 as_bad ("PIC code offset overflow (max 16 signed bits)");
3766 if (reg_needs_delay (GP
))
3771 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
3772 tempreg
, (int) BFD_RELOC_MIPS_GOT_HI16
);
3773 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3774 mips_isa
< 3 ? "addu" : "daddu",
3775 "d,v,t", tempreg
, tempreg
, GP
);
3776 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3777 mips_isa
< 3 ? "lw" : "ld",
3778 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT_LO16
,
3780 p
= frag_var (rs_machine_dependent
, 12 + gpdel
, 0,
3781 RELAX_ENCODE (12, 12 + gpdel
, gpdel
, 8 + gpdel
, 0, 0),
3782 offset_expr
.X_add_symbol
, (long) 0, (char *) NULL
);
3785 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
3788 macro_build (p
, &icnt
, &offset_expr
,
3789 mips_isa
< 3 ? "lw" : "ld",
3790 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
3792 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
3794 macro_build (p
, &icnt
, &offset_expr
,
3795 mips_isa
< 3 ? "addiu" : "daddiu",
3796 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
3798 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3799 mips_isa
< 3 ? "addu" : "daddu",
3800 "d,v,t", tempreg
, tempreg
, breg
);
3801 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
, treg
,
3802 (int) BFD_RELOC_LO16
, tempreg
);
3804 else if (mips_pic
== EMBEDDED_PIC
)
3806 /* If there is no base register, we want
3807 <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL)
3808 If there is a base register, we want
3809 addu $tempreg,$breg,$gp
3810 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GPREL)
3812 assert (offset_expr
.X_op
== O_symbol
);
3815 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
3816 treg
, (int) BFD_RELOC_MIPS_GPREL
, GP
);
3821 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3822 mips_isa
< 3 ? "addu" : "daddu",
3823 "d,v,t", tempreg
, breg
, GP
);
3824 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
3825 treg
, (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
3838 load_register (&icnt
, treg
, &imm_expr
, 0);
3842 load_register (&icnt
, treg
, &imm_expr
, 1);
3846 if (imm_expr
.X_op
== O_constant
)
3848 load_register (&icnt
, AT
, &imm_expr
, 0);
3849 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3850 "mtc1", "t,G", AT
, treg
);
3855 assert (offset_expr
.X_op
== O_symbol
3856 && strcmp (segment_name (S_GET_SEGMENT
3857 (offset_expr
.X_add_symbol
)),
3859 && offset_expr
.X_add_number
== 0);
3860 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lwc1", "T,o(b)",
3861 treg
, (int) BFD_RELOC_MIPS_LITERAL
, GP
);
3866 /* We know that sym is in the .rdata section. First we get the
3867 upper 16 bits of the address. */
3868 if (mips_pic
== NO_PIC
)
3870 /* FIXME: This won't work for a 64 bit address. */
3871 macro_build_lui ((char *) NULL
, &icnt
, &offset_expr
, AT
);
3873 else if (mips_pic
== SVR4_PIC
)
3875 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3876 mips_isa
< 3 ? "lw" : "ld",
3877 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
3879 else if (mips_pic
== EMBEDDED_PIC
)
3881 /* For embedded PIC we pick up the entire address off $gp in
3882 a single instruction. */
3883 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3884 mips_isa
< 3 ? "addiu" : "daddiu",
3885 "t,r,j", AT
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
3886 offset_expr
.X_op
= O_constant
;
3887 offset_expr
.X_add_number
= 0;
3892 /* Now we load the register(s). */
3894 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "ld", "t,o(b)",
3895 treg
, (int) BFD_RELOC_LO16
, AT
);
3898 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lw", "t,o(b)",
3899 treg
, (int) BFD_RELOC_LO16
, AT
);
3902 /* FIXME: How in the world do we deal with the possible
3904 offset_expr
.X_add_number
+= 4;
3905 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lw", "t,o(b)",
3906 treg
+ 1, (int) BFD_RELOC_LO16
, AT
);
3910 /* To avoid confusion in tc_gen_reloc, we must ensure that this
3911 does not become a variant frag. */
3912 frag_wane (frag_now
);
3918 assert (offset_expr
.X_op
== O_symbol
3919 && offset_expr
.X_add_number
== 0);
3920 s
= segment_name (S_GET_SEGMENT (offset_expr
.X_add_symbol
));
3921 if (strcmp (s
, ".lit8") == 0)
3925 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "ldc1",
3926 "T,o(b)", treg
, (int) BFD_RELOC_MIPS_LITERAL
, GP
);
3930 r
= BFD_RELOC_MIPS_LITERAL
;
3935 assert (strcmp (s
, RDATA_SECTION_NAME
) == 0);
3936 if (mips_pic
== SVR4_PIC
)
3937 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3938 mips_isa
< 3 ? "lw" : "ld",
3939 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
3942 /* FIXME: This won't work for a 64 bit address. */
3943 macro_build_lui ((char *) NULL
, &icnt
, &offset_expr
, AT
);
3948 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "ldc1",
3949 "T,o(b)", treg
, (int) BFD_RELOC_LO16
, AT
);
3951 /* To avoid confusion in tc_gen_reloc, we must ensure
3952 that this does not become a variant frag. */
3953 frag_wane (frag_now
);
3964 /* Even on a big endian machine $fn comes before $fn+1. We have
3965 to adjust when loading from memory. */
3968 assert (mips_isa
< 2);
3969 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lwc1", "T,o(b)",
3970 byte_order
== LITTLE_ENDIAN
? treg
: treg
+ 1,
3972 /* FIXME: A possible overflow which I don't know how to deal
3974 offset_expr
.X_add_number
+= 4;
3975 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lwc1", "T,o(b)",
3976 byte_order
== LITTLE_ENDIAN
? treg
+ 1 : treg
,
3979 /* To avoid confusion in tc_gen_reloc, we must ensure that this
3980 does not become a variant frag. */
3981 frag_wane (frag_now
);
3990 * The MIPS assembler seems to check for X_add_number not
3991 * being double aligned and generating:
3994 * addiu at,at,%lo(foo+1)
3997 * But, the resulting address is the same after relocation so why
3998 * generate the extra instruction?
4045 if (offset_expr
.X_op
!= O_symbol
4046 && offset_expr
.X_op
!= O_constant
)
4048 as_bad ("expression too complex");
4049 offset_expr
.X_op
= O_constant
;
4052 /* Even on a big endian machine $fn comes before $fn+1. We have
4053 to adjust when loading from memory. We set coproc if we must
4054 load $fn+1 first. */
4055 if (byte_order
== LITTLE_ENDIAN
)
4058 if (mips_pic
== NO_PIC
4059 || offset_expr
.X_op
== O_constant
)
4061 /* If this is a reference to a GP relative symbol, we want
4062 <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL)
4063 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_MIPS_GPREL)
4064 If we have a base register, we use this
4066 <op> $treg,<sym>($at) (BFD_RELOC_MIPS_GPREL)
4067 <op> $treg+1,<sym>+4($at) (BFD_RELOC_MIPS_GPREL)
4068 If this is not a GP relative symbol, we want
4069 lui $at,<sym> (BFD_RELOC_HI16_S)
4070 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
4071 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
4072 If there is a base register, we add it to $at after the
4073 lui instruction. If there is a constant, we always use
4075 if ((valueT
) offset_expr
.X_add_number
>= MAX_GPREL_OFFSET
4076 || nopic_need_relax (offset_expr
.X_add_symbol
))
4095 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4096 mips_isa
< 3 ? "addu" : "daddu",
4097 "d,v,t", AT
, breg
, GP
);
4103 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
4104 coproc
? treg
+ 1 : treg
,
4105 (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
4106 offset_expr
.X_add_number
+= 4;
4108 /* Set mips_optimize to 2 to avoid inserting an
4110 hold_mips_optimize
= mips_optimize
;
4112 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
4113 coproc
? treg
: treg
+ 1,
4114 (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
4115 mips_optimize
= hold_mips_optimize
;
4117 p
= frag_var (rs_machine_dependent
, 12 + off
, 0,
4118 RELAX_ENCODE (8 + off
, 12 + off
, 0, 4 + off
, 1,
4119 used_at
&& mips_noat
),
4120 offset_expr
.X_add_symbol
, (long) 0,
4123 /* We just generated two relocs. When tc_gen_reloc
4124 handles this case, it will skip the first reloc and
4125 handle the second. The second reloc already has an
4126 extra addend of 4, which we added above. We must
4127 subtract it out, and then subtract another 4 to make
4128 the first reloc come out right. The second reloc
4129 will come out right because we are going to add 4 to
4130 offset_expr when we build its instruction below. */
4131 offset_expr
.X_add_number
-= 8;
4132 offset_expr
.X_op
= O_constant
;
4134 macro_build_lui (p
, &icnt
, &offset_expr
, AT
);
4139 macro_build (p
, &icnt
, (expressionS
*) NULL
,
4140 mips_isa
< 3 ? "addu" : "daddu",
4141 "d,v,t", AT
, breg
, AT
);
4145 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
,
4146 coproc
? treg
+ 1 : treg
,
4147 (int) BFD_RELOC_LO16
, AT
);
4150 /* FIXME: How do we handle overflow here? */
4151 offset_expr
.X_add_number
+= 4;
4152 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
,
4153 coproc
? treg
: treg
+ 1,
4154 (int) BFD_RELOC_LO16
, AT
);
4156 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
4160 /* If this is a reference to an external symbol, we want
4161 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4166 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4168 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
4169 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
4170 If there is a base register we add it to $at before the
4171 lwc1 instructions. If there is a constant we include it
4172 in the lwc1 instructions. */
4174 expr1
.X_add_number
= offset_expr
.X_add_number
;
4175 offset_expr
.X_add_number
= 0;
4176 if (expr1
.X_add_number
< -0x8000
4177 || expr1
.X_add_number
>= 0x8000 - 4)
4178 as_bad ("PIC code offset overflow (max 16 signed bits)");
4183 frag_grow (24 + off
);
4184 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4185 mips_isa
< 3 ? "lw" : "ld",
4186 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
4187 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
4189 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4190 mips_isa
< 3 ? "addu" : "daddu",
4191 "d,v,t", AT
, breg
, AT
);
4192 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
4193 coproc
? treg
+ 1 : treg
,
4194 (int) BFD_RELOC_LO16
, AT
);
4195 expr1
.X_add_number
+= 4;
4197 /* Set mips_optimize to 2 to avoid inserting an undesired
4199 hold_mips_optimize
= mips_optimize
;
4201 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
4202 coproc
? treg
: treg
+ 1,
4203 (int) BFD_RELOC_LO16
, AT
);
4204 mips_optimize
= hold_mips_optimize
;
4206 (void) frag_var (rs_machine_dependent
, 0, 0,
4207 RELAX_ENCODE (0, 0, -16 - off
, -8, 1, 0),
4208 offset_expr
.X_add_symbol
, (long) 0,
4211 else if (mips_pic
== SVR4_PIC
)
4215 /* If this is a reference to an external symbol, we want
4216 lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16)
4218 lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16)
4223 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4225 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
4226 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
4227 If there is a base register we add it to $at before the
4228 lwc1 instructions. If there is a constant we include it
4229 in the lwc1 instructions. */
4231 expr1
.X_add_number
= offset_expr
.X_add_number
;
4232 offset_expr
.X_add_number
= 0;
4233 if (expr1
.X_add_number
< -0x8000
4234 || expr1
.X_add_number
>= 0x8000 - 4)
4235 as_bad ("PIC code offset overflow (max 16 signed bits)");
4236 if (reg_needs_delay (GP
))
4245 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
4246 AT
, (int) BFD_RELOC_MIPS_GOT_HI16
);
4247 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4248 mips_isa
< 3 ? "addu" : "daddu",
4249 "d,v,t", AT
, AT
, GP
);
4250 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4251 mips_isa
< 3 ? "lw" : "ld",
4252 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT_LO16
, AT
);
4253 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
4255 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4256 mips_isa
< 3 ? "addu" : "daddu",
4257 "d,v,t", AT
, breg
, AT
);
4258 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
4259 coproc
? treg
+ 1 : treg
,
4260 (int) BFD_RELOC_LO16
, AT
);
4261 expr1
.X_add_number
+= 4;
4263 /* Set mips_optimize to 2 to avoid inserting an undesired
4265 hold_mips_optimize
= mips_optimize
;
4267 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
4268 coproc
? treg
: treg
+ 1,
4269 (int) BFD_RELOC_LO16
, AT
);
4270 mips_optimize
= hold_mips_optimize
;
4271 expr1
.X_add_number
-= 4;
4273 p
= frag_var (rs_machine_dependent
, 16 + gpdel
+ off
, 0,
4274 RELAX_ENCODE (24 + off
, 16 + gpdel
+ off
, gpdel
,
4275 8 + gpdel
+ off
, 1, 0),
4276 offset_expr
.X_add_symbol
, (long) 0,
4280 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4283 macro_build (p
, &icnt
, &offset_expr
,
4284 mips_isa
< 3 ? "lw" : "ld",
4285 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
4287 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4291 macro_build (p
, &icnt
, (expressionS
*) NULL
,
4292 mips_isa
< 3 ? "addu" : "daddu",
4293 "d,v,t", AT
, breg
, AT
);
4296 macro_build (p
, &icnt
, &expr1
, s
, fmt
,
4297 coproc
? treg
+ 1 : treg
,
4298 (int) BFD_RELOC_LO16
, AT
);
4300 expr1
.X_add_number
+= 4;
4302 /* Set mips_optimize to 2 to avoid inserting an undesired
4304 hold_mips_optimize
= mips_optimize
;
4306 macro_build (p
, &icnt
, &expr1
, s
, fmt
,
4307 coproc
? treg
: treg
+ 1,
4308 (int) BFD_RELOC_LO16
, AT
);
4309 mips_optimize
= hold_mips_optimize
;
4311 else if (mips_pic
== EMBEDDED_PIC
)
4313 /* If there is no base register, we use
4314 <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL)
4315 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_MIPS_GPREL)
4316 If we have a base register, we use
4318 <op> $treg,<sym>($at) (BFD_RELOC_MIPS_GPREL)
4319 <op> $treg+1,<sym>+4($at) (BFD_RELOC_MIPS_GPREL)
4328 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4329 mips_isa
< 3 ? "addu" : "daddu",
4330 "d,v,t", AT
, breg
, GP
);
4335 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
4336 coproc
? treg
+ 1 : treg
,
4337 (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
4338 offset_expr
.X_add_number
+= 4;
4339 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
4340 coproc
? treg
: treg
+ 1,
4341 (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
4357 assert (mips_isa
< 3);
4358 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
4359 (int) BFD_RELOC_LO16
, breg
);
4360 offset_expr
.X_add_number
+= 4;
4361 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
+ 1,
4362 (int) BFD_RELOC_LO16
, breg
);
4364 #ifdef LOSING_COMPILER
4370 as_warn ("Macro used $at after \".set noat\"");
4375 struct mips_cl_insn
*ip
;
4377 register int treg
, sreg
, dreg
, breg
;
4392 bfd_reloc_code_real_type r
;
4395 treg
= (ip
->insn_opcode
>> 16) & 0x1f;
4396 dreg
= (ip
->insn_opcode
>> 11) & 0x1f;
4397 sreg
= breg
= (ip
->insn_opcode
>> 21) & 0x1f;
4398 mask
= ip
->insn_mo
->mask
;
4400 expr1
.X_op
= O_constant
;
4401 expr1
.X_op_symbol
= NULL
;
4402 expr1
.X_add_symbol
= NULL
;
4403 expr1
.X_add_number
= 1;
4407 #endif /* LOSING_COMPILER */
4412 macro_build ((char *) NULL
, &icnt
, NULL
,
4413 dbl
? "dmultu" : "multu",
4415 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
4421 /* The MIPS assembler some times generates shifts and adds. I'm
4422 not trying to be that fancy. GCC should do this for us
4424 load_register (&icnt
, AT
, &imm_expr
, dbl
);
4425 macro_build ((char *) NULL
, &icnt
, NULL
,
4426 dbl
? "dmult" : "mult",
4428 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
4434 mips_emit_delays ();
4436 mips_any_noreorder
= 1;
4437 macro_build ((char *) NULL
, &icnt
, NULL
,
4438 dbl
? "dmult" : "mult",
4440 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
4441 macro_build ((char *) NULL
, &icnt
, NULL
,
4442 dbl
? "dsra32" : "sra",
4443 "d,w,<", dreg
, dreg
, 31);
4444 macro_build ((char *) NULL
, &icnt
, NULL
, "mfhi", "d", AT
);
4446 macro_build ((char *) NULL
, &icnt
, NULL
, "tne", "s,t", dreg
, AT
);
4449 expr1
.X_add_number
= 8;
4450 macro_build ((char *) NULL
, &icnt
, &expr1
, "beq", "s,t,p", dreg
, AT
);
4451 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
4452 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 6);
4455 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
4461 mips_emit_delays ();
4463 mips_any_noreorder
= 1;
4464 macro_build ((char *) NULL
, &icnt
, NULL
,
4465 dbl
? "dmultu" : "multu",
4467 macro_build ((char *) NULL
, &icnt
, NULL
, "mfhi", "d", AT
);
4468 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
4470 macro_build ((char *) NULL
, &icnt
, NULL
, "tne", "s,t", AT
, 0);
4473 expr1
.X_add_number
= 8;
4474 macro_build ((char *) NULL
, &icnt
, &expr1
, "beq", "s,t,p", AT
, 0);
4475 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
4476 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 6);
4482 macro_build ((char *) NULL
, &icnt
, NULL
, "subu", "d,v,t", AT
, 0, treg
);
4483 macro_build ((char *) NULL
, &icnt
, NULL
, "srlv", "d,t,s", AT
, sreg
, AT
);
4484 macro_build ((char *) NULL
, &icnt
, NULL
, "sllv", "d,t,s", dreg
, sreg
,
4486 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
4490 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", AT
, sreg
,
4491 (int) (imm_expr
.X_add_number
& 0x1f));
4492 macro_build ((char *) NULL
, &icnt
, NULL
, "srl", "d,w,<", dreg
, sreg
,
4493 (int) ((0 - imm_expr
.X_add_number
) & 0x1f));
4494 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
4498 macro_build ((char *) NULL
, &icnt
, NULL
, "subu", "d,v,t", AT
, 0, treg
);
4499 macro_build ((char *) NULL
, &icnt
, NULL
, "sllv", "d,t,s", AT
, sreg
, AT
);
4500 macro_build ((char *) NULL
, &icnt
, NULL
, "srlv", "d,t,s", dreg
, sreg
,
4502 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
4506 macro_build ((char *) NULL
, &icnt
, NULL
, "srl", "d,w,<", AT
, sreg
,
4507 (int) (imm_expr
.X_add_number
& 0x1f));
4508 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", dreg
, sreg
,
4509 (int) ((0 - imm_expr
.X_add_number
) & 0x1f));
4510 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
4514 assert (mips_isa
< 2);
4515 /* Even on a big endian machine $fn comes before $fn+1. We have
4516 to adjust when storing to memory. */
4517 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "swc1", "T,o(b)",
4518 byte_order
== LITTLE_ENDIAN
? treg
: treg
+ 1,
4519 (int) BFD_RELOC_LO16
, breg
);
4520 offset_expr
.X_add_number
+= 4;
4521 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "swc1", "T,o(b)",
4522 byte_order
== LITTLE_ENDIAN
? treg
+ 1 : treg
,
4523 (int) BFD_RELOC_LO16
, breg
);
4528 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
4529 treg
, (int) BFD_RELOC_LO16
);
4531 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
4532 sreg
, (int) BFD_RELOC_LO16
);
4535 macro_build ((char *) NULL
, &icnt
, NULL
, "xor", "d,v,t", dreg
,
4537 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
4538 dreg
, (int) BFD_RELOC_LO16
);
4543 if (imm_expr
.X_add_number
== 0)
4545 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
4546 sreg
, (int) BFD_RELOC_LO16
);
4551 as_warn ("Instruction %s: result is always false",
4553 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
, 0);
4556 if (imm_expr
.X_add_number
>= 0 && imm_expr
.X_add_number
< 0x10000)
4558 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "xori", "t,r,i", dreg
,
4559 sreg
, (int) BFD_RELOC_LO16
);
4562 else if (imm_expr
.X_add_number
> -0x8000 && imm_expr
.X_add_number
< 0)
4564 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
4565 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
4566 mips_isa
< 3 ? "addiu" : "daddiu",
4567 "t,r,j", dreg
, sreg
,
4568 (int) BFD_RELOC_LO16
);
4573 load_register (&icnt
, AT
, &imm_expr
, 0);
4574 macro_build ((char *) NULL
, &icnt
, NULL
, "xor", "d,v,t", dreg
,
4578 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
, dreg
,
4579 (int) BFD_RELOC_LO16
);
4584 case M_SGE
: /* sreg >= treg <==> not (sreg < treg) */
4590 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, sreg
, treg
);
4591 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
4592 (int) BFD_RELOC_LO16
);
4595 case M_SGE_I
: /* sreg >= I <==> not (sreg < I) */
4597 if (imm_expr
.X_add_number
>= -0x8000 && imm_expr
.X_add_number
< 0x8000)
4599 macro_build ((char *) NULL
, &icnt
, &expr1
,
4600 mask
== M_SGE_I
? "slti" : "sltiu",
4601 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
4606 load_register (&icnt
, AT
, &imm_expr
, 0);
4607 macro_build ((char *) NULL
, &icnt
, NULL
,
4608 mask
== M_SGE_I
? "slt" : "sltu",
4609 "d,v,t", dreg
, sreg
, AT
);
4612 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
4613 (int) BFD_RELOC_LO16
);
4618 case M_SGT
: /* sreg > treg <==> treg < sreg */
4624 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, treg
, sreg
);
4627 case M_SGT_I
: /* sreg > I <==> I < sreg */
4633 load_register (&icnt
, AT
, &imm_expr
, 0);
4634 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, AT
, sreg
);
4637 case M_SLE
: /* sreg <= treg <==> treg >= sreg <==> not (treg < sreg) */
4643 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, treg
, sreg
);
4644 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
4645 (int) BFD_RELOC_LO16
);
4648 case M_SLE_I
: /* sreg <= I <==> I >= sreg <==> not (I < sreg) */
4654 load_register (&icnt
, AT
, &imm_expr
, 0);
4655 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, AT
, sreg
);
4656 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
4657 (int) BFD_RELOC_LO16
);
4661 if (imm_expr
.X_add_number
>= -0x8000 && imm_expr
.X_add_number
< 0x8000)
4663 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "slti", "t,r,j",
4664 dreg
, sreg
, (int) BFD_RELOC_LO16
);
4667 load_register (&icnt
, AT
, &imm_expr
, 0);
4668 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", dreg
, sreg
, AT
);
4672 if (imm_expr
.X_add_number
>= -0x8000 && imm_expr
.X_add_number
< 0x8000)
4674 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "sltiu", "t,r,j",
4675 dreg
, sreg
, (int) BFD_RELOC_LO16
);
4678 load_register (&icnt
, AT
, &imm_expr
, 0);
4679 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, sreg
,
4685 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0,
4688 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0,
4692 macro_build ((char *) NULL
, &icnt
, NULL
, "xor", "d,v,t", dreg
,
4694 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0,
4700 if (imm_expr
.X_add_number
== 0)
4702 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0,
4708 as_warn ("Instruction %s: result is always true",
4710 macro_build ((char *) NULL
, &icnt
, &expr1
,
4711 mips_isa
< 3 ? "addiu" : "daddiu",
4712 "t,r,j", dreg
, 0, (int) BFD_RELOC_LO16
);
4715 if (imm_expr
.X_add_number
>= 0 && imm_expr
.X_add_number
< 0x10000)
4717 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "xori", "t,r,i",
4718 dreg
, sreg
, (int) BFD_RELOC_LO16
);
4721 else if (imm_expr
.X_add_number
> -0x8000 && imm_expr
.X_add_number
< 0)
4723 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
4724 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
4725 mips_isa
< 3 ? "addiu" : "daddiu",
4726 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
4731 load_register (&icnt
, AT
, &imm_expr
, 0);
4732 macro_build ((char *) NULL
, &icnt
, NULL
, "xor", "d,v,t", dreg
,
4736 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0, dreg
);
4744 if (imm_expr
.X_add_number
> -0x8000 && imm_expr
.X_add_number
<= 0x8000)
4746 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
4747 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
4748 dbl
? "daddi" : "addi",
4749 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
4752 load_register (&icnt
, AT
, &imm_expr
, dbl
);
4753 macro_build ((char *) NULL
, &icnt
, NULL
,
4754 dbl
? "dsub" : "sub",
4755 "d,v,t", dreg
, sreg
, AT
);
4761 if (imm_expr
.X_add_number
> -0x8000 && imm_expr
.X_add_number
<= 0x8000)
4763 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
4764 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
4765 dbl
? "daddiu" : "addiu",
4766 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
4769 load_register (&icnt
, AT
, &imm_expr
, dbl
);
4770 macro_build ((char *) NULL
, &icnt
, NULL
,
4771 dbl
? "dsubu" : "subu",
4772 "d,v,t", dreg
, sreg
, AT
);
4793 load_register (&icnt
, AT
, &imm_expr
, 0);
4794 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "s,t", sreg
, AT
);
4799 assert (mips_isa
< 2);
4800 sreg
= (ip
->insn_opcode
>> 11) & 0x1f; /* floating reg */
4801 dreg
= (ip
->insn_opcode
>> 06) & 0x1f; /* floating reg */
4804 * Is the double cfc1 instruction a bug in the mips assembler;
4805 * or is there a reason for it?
4807 mips_emit_delays ();
4809 mips_any_noreorder
= 1;
4810 macro_build ((char *) NULL
, &icnt
, NULL
, "cfc1", "t,G", treg
, 31);
4811 macro_build ((char *) NULL
, &icnt
, NULL
, "cfc1", "t,G", treg
, 31);
4812 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "");
4813 expr1
.X_add_number
= 3;
4814 macro_build ((char *) NULL
, &icnt
, &expr1
, "ori", "t,r,i", AT
, treg
,
4815 (int) BFD_RELOC_LO16
);
4816 expr1
.X_add_number
= 2;
4817 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", AT
, AT
,
4818 (int) BFD_RELOC_LO16
);
4819 macro_build ((char *) NULL
, &icnt
, NULL
, "ctc1", "t,G", AT
, 31);
4820 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "");
4821 macro_build ((char *) NULL
, &icnt
, NULL
,
4822 mask
== M_TRUNCWD
? "cvt.w.d" : "cvt.w.s", "D,S", dreg
, sreg
);
4823 macro_build ((char *) NULL
, &icnt
, NULL
, "ctc1", "t,G", treg
, 31);
4824 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "");
4834 if (offset_expr
.X_add_number
>= 0x7fff)
4835 as_bad ("operand overflow");
4836 /* avoid load delay */
4837 if (byte_order
== LITTLE_ENDIAN
)
4838 offset_expr
.X_add_number
+= 1;
4839 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
4840 (int) BFD_RELOC_LO16
, breg
);
4841 if (byte_order
== LITTLE_ENDIAN
)
4842 offset_expr
.X_add_number
-= 1;
4844 offset_expr
.X_add_number
+= 1;
4845 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lbu", "t,o(b)", AT
,
4846 (int) BFD_RELOC_LO16
, breg
);
4847 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", treg
, treg
, 8);
4848 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", treg
, treg
, AT
);
4861 if (offset_expr
.X_add_number
>= 0x8000 - off
)
4862 as_bad ("operand overflow");
4863 if (byte_order
== LITTLE_ENDIAN
)
4864 offset_expr
.X_add_number
+= off
;
4865 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
4866 (int) BFD_RELOC_LO16
, breg
);
4867 if (byte_order
== LITTLE_ENDIAN
)
4868 offset_expr
.X_add_number
-= off
;
4870 offset_expr
.X_add_number
+= off
;
4871 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s2
, "t,o(b)", treg
,
4872 (int) BFD_RELOC_LO16
, breg
);
4885 load_address (&icnt
, AT
, &offset_expr
);
4887 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4888 mips_isa
< 3 ? "addu" : "daddu",
4889 "d,v,t", AT
, AT
, breg
);
4890 if (byte_order
== LITTLE_ENDIAN
)
4891 expr1
.X_add_number
= off
;
4893 expr1
.X_add_number
= 0;
4894 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, "t,o(b)", treg
,
4895 (int) BFD_RELOC_LO16
, AT
);
4896 if (byte_order
== LITTLE_ENDIAN
)
4897 expr1
.X_add_number
= 0;
4899 expr1
.X_add_number
= off
;
4900 macro_build ((char *) NULL
, &icnt
, &expr1
, s2
, "t,o(b)", treg
,
4901 (int) BFD_RELOC_LO16
, AT
);
4906 load_address (&icnt
, AT
, &offset_expr
);
4908 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4909 mips_isa
< 3 ? "addu" : "daddu",
4910 "d,v,t", AT
, AT
, breg
);
4911 if (byte_order
== BIG_ENDIAN
)
4912 expr1
.X_add_number
= 0;
4913 macro_build ((char *) NULL
, &icnt
, &expr1
,
4914 mask
== M_ULH_A
? "lb" : "lbu", "t,o(b)", treg
,
4915 (int) BFD_RELOC_LO16
, AT
);
4916 if (byte_order
== BIG_ENDIAN
)
4917 expr1
.X_add_number
= 1;
4919 expr1
.X_add_number
= 0;
4920 macro_build ((char *) NULL
, &icnt
, &expr1
, "lbu", "t,o(b)", AT
,
4921 (int) BFD_RELOC_LO16
, AT
);
4922 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", treg
,
4924 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", treg
,
4929 if (offset_expr
.X_add_number
>= 0x7fff)
4930 as_bad ("operand overflow");
4931 if (byte_order
== BIG_ENDIAN
)
4932 offset_expr
.X_add_number
+= 1;
4933 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "sb", "t,o(b)", treg
,
4934 (int) BFD_RELOC_LO16
, breg
);
4935 macro_build ((char *) NULL
, &icnt
, NULL
, "srl", "d,w,<", AT
, treg
, 8);
4936 if (byte_order
== BIG_ENDIAN
)
4937 offset_expr
.X_add_number
-= 1;
4939 offset_expr
.X_add_number
+= 1;
4940 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "sb", "t,o(b)", AT
,
4941 (int) BFD_RELOC_LO16
, breg
);
4954 if (offset_expr
.X_add_number
>= 0x8000 - off
)
4955 as_bad ("operand overflow");
4956 if (byte_order
== LITTLE_ENDIAN
)
4957 offset_expr
.X_add_number
+= off
;
4958 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
4959 (int) BFD_RELOC_LO16
, breg
);
4960 if (byte_order
== LITTLE_ENDIAN
)
4961 offset_expr
.X_add_number
-= off
;
4963 offset_expr
.X_add_number
+= off
;
4964 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s2
, "t,o(b)", treg
,
4965 (int) BFD_RELOC_LO16
, breg
);
4978 load_address (&icnt
, AT
, &offset_expr
);
4980 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4981 mips_isa
< 3 ? "addu" : "daddu",
4982 "d,v,t", AT
, AT
, breg
);
4983 if (byte_order
== LITTLE_ENDIAN
)
4984 expr1
.X_add_number
= off
;
4986 expr1
.X_add_number
= 0;
4987 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, "t,o(b)", treg
,
4988 (int) BFD_RELOC_LO16
, AT
);
4989 if (byte_order
== LITTLE_ENDIAN
)
4990 expr1
.X_add_number
= 0;
4992 expr1
.X_add_number
= off
;
4993 macro_build ((char *) NULL
, &icnt
, &expr1
, s2
, "t,o(b)", treg
,
4994 (int) BFD_RELOC_LO16
, AT
);
4998 load_address (&icnt
, AT
, &offset_expr
);
5000 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5001 mips_isa
< 3 ? "addu" : "daddu",
5002 "d,v,t", AT
, AT
, breg
);
5003 if (byte_order
== LITTLE_ENDIAN
)
5004 expr1
.X_add_number
= 0;
5005 macro_build ((char *) NULL
, &icnt
, &expr1
, "sb", "t,o(b)", treg
,
5006 (int) BFD_RELOC_LO16
, AT
);
5007 macro_build ((char *) NULL
, &icnt
, NULL
, "srl", "d,w,<", treg
,
5009 if (byte_order
== LITTLE_ENDIAN
)
5010 expr1
.X_add_number
= 1;
5012 expr1
.X_add_number
= 0;
5013 macro_build ((char *) NULL
, &icnt
, &expr1
, "sb", "t,o(b)", treg
,
5014 (int) BFD_RELOC_LO16
, AT
);
5015 if (byte_order
== LITTLE_ENDIAN
)
5016 expr1
.X_add_number
= 0;
5018 expr1
.X_add_number
= 1;
5019 macro_build ((char *) NULL
, &icnt
, &expr1
, "lbu", "t,o(b)", AT
,
5020 (int) BFD_RELOC_LO16
, AT
);
5021 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", treg
,
5023 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", treg
,
5028 as_bad ("Macro %s not implemented yet", ip
->insn_mo
->name
);
5032 as_warn ("Macro used $at after \".set noat\"");
5035 /* This routine assembles an instruction into its binary format. As a
5036 side effect, it sets one of the global variables imm_reloc or
5037 offset_reloc to the type of relocation to do if one of the operands
5038 is an address expression. */
5043 struct mips_cl_insn
*ip
;
5048 struct mips_opcode
*insn
;
5051 unsigned int lastregno
= 0;
5056 for (s
= str
; islower (*s
) || (*s
>= '0' && *s
<= '3') || *s
== '6' || *s
== '.'; ++s
)
5068 as_fatal ("Unknown opcode: `%s'", str
);
5070 if ((insn
= (struct mips_opcode
*) hash_find (op_hash
, str
)) == NULL
)
5072 insn_error
= "unrecognized opcode";
5080 assert (strcmp (insn
->name
, str
) == 0);
5082 if (insn
->pinfo
== INSN_MACRO
)
5083 insn_isa
= insn
->match
;
5084 else if ((insn
->pinfo
& INSN_ISA
) == INSN_ISA2
)
5086 else if ((insn
->pinfo
& INSN_ISA
) == INSN_ISA3
)
5088 else if ((insn
->pinfo
& INSN_ISA
) == INSN_ISA4
)
5093 if (insn_isa
> mips_isa
5094 || ((insn
->pinfo
& INSN_ISA
) == INSN_4650
5096 || ((insn
->pinfo
& INSN_ISA
) == INSN_4010
5098 || ((insn
->pinfo
& INSN_ISA
) == INSN_4100
5101 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
]
5102 && strcmp (insn
->name
, insn
[1].name
) == 0)
5107 insn_error
= "opcode not supported on this processor";
5112 ip
->insn_opcode
= insn
->match
;
5113 for (args
= insn
->args
;; ++args
)
5119 case '\0': /* end of args */
5132 ip
->insn_opcode
|= lastregno
<< 21;
5137 ip
->insn_opcode
|= lastregno
<< 16;
5141 ip
->insn_opcode
|= lastregno
<< 11;
5147 /* handle optional base register.
5148 Either the base register is omitted or
5149 we must have a left paren. */
5150 /* this is dependent on the next operand specifier
5151 is a 'b' for base register */
5152 assert (args
[1] == 'b');
5156 case ')': /* these must match exactly */
5161 case '<': /* must be at least one digit */
5163 * According to the manual, if the shift amount is greater
5164 * than 31 or less than 0 the the shift amount should be
5165 * mod 32. In reality the mips assembler issues an error.
5166 * We issue a warning and mask out all but the low 5 bits.
5168 my_getExpression (&imm_expr
, s
);
5169 check_absolute_expr (ip
, &imm_expr
);
5170 if ((unsigned long) imm_expr
.X_add_number
> 31)
5172 as_warn ("Improper shift amount (%ld)",
5173 (long) imm_expr
.X_add_number
);
5174 imm_expr
.X_add_number
= imm_expr
.X_add_number
& 0x1f;
5176 ip
->insn_opcode
|= imm_expr
.X_add_number
<< 6;
5177 imm_expr
.X_op
= O_absent
;
5181 case '>': /* shift amount minus 32 */
5182 my_getExpression (&imm_expr
, s
);
5183 check_absolute_expr (ip
, &imm_expr
);
5184 if ((unsigned long) imm_expr
.X_add_number
< 32
5185 || (unsigned long) imm_expr
.X_add_number
> 63)
5187 ip
->insn_opcode
|= (imm_expr
.X_add_number
- 32) << 6;
5188 imm_expr
.X_op
= O_absent
;
5192 case 'k': /* cache code */
5193 case 'h': /* prefx code */
5194 my_getExpression (&imm_expr
, s
);
5195 check_absolute_expr (ip
, &imm_expr
);
5196 if ((unsigned long) imm_expr
.X_add_number
> 31)
5198 as_warn ("Invalid value for `%s' (%lu)",
5200 (unsigned long) imm_expr
.X_add_number
);
5201 imm_expr
.X_add_number
&= 0x1f;
5204 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_CACHE
;
5206 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_PREFX
;
5207 imm_expr
.X_op
= O_absent
;
5211 case 'c': /* break code */
5212 my_getExpression (&imm_expr
, s
);
5213 check_absolute_expr (ip
, &imm_expr
);
5214 if ((unsigned) imm_expr
.X_add_number
> 1023)
5215 as_warn ("Illegal break code (%ld)",
5216 (long) imm_expr
.X_add_number
);
5217 ip
->insn_opcode
|= imm_expr
.X_add_number
<< 16;
5218 imm_expr
.X_op
= O_absent
;
5222 case 'B': /* syscall code */
5223 my_getExpression (&imm_expr
, s
);
5224 check_absolute_expr (ip
, &imm_expr
);
5225 if ((unsigned) imm_expr
.X_add_number
> 0xfffff)
5226 as_warn ("Illegal syscall code (%ld)",
5227 (long) imm_expr
.X_add_number
);
5228 ip
->insn_opcode
|= imm_expr
.X_add_number
<< 6;
5229 imm_expr
.X_op
= O_absent
;
5233 case 'C': /* Coprocessor code */
5234 my_getExpression (&imm_expr
, s
);
5235 check_absolute_expr (ip
, &imm_expr
);
5236 if ((unsigned long) imm_expr
.X_add_number
>= (1<<25))
5238 as_warn ("Coproccesor code > 25 bits (%ld)",
5239 (long) imm_expr
.X_add_number
);
5240 imm_expr
.X_add_number
&= ((1<<25) - 1);
5242 ip
->insn_opcode
|= imm_expr
.X_add_number
;
5243 imm_expr
.X_op
= O_absent
;
5247 case 'b': /* base register */
5248 case 'd': /* destination register */
5249 case 's': /* source register */
5250 case 't': /* target register */
5251 case 'r': /* both target and source */
5252 case 'v': /* both dest and source */
5253 case 'w': /* both dest and target */
5254 case 'E': /* coprocessor target register */
5255 case 'G': /* coprocessor destination register */
5256 case 'x': /* ignore register name */
5257 case 'z': /* must be zero register */
5271 while (isdigit (*s
));
5273 as_bad ("Invalid register number (%d)", regno
);
5275 else if (*args
== 'E' || *args
== 'G')
5279 if (s
[1] == 'f' && s
[2] == 'p')
5284 else if (s
[1] == 's' && s
[2] == 'p')
5289 else if (s
[1] == 'g' && s
[2] == 'p')
5294 else if (s
[1] == 'a' && s
[2] == 't')
5299 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '0')
5304 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '1')
5316 as_warn ("Used $at without \".set noat\"");
5322 if (c
== 'r' || c
== 'v' || c
== 'w')
5329 /* 'z' only matches $0. */
5330 if (c
== 'z' && regno
!= 0)
5338 ip
->insn_opcode
|= regno
<< 21;
5342 ip
->insn_opcode
|= regno
<< 11;
5347 ip
->insn_opcode
|= regno
<< 16;
5350 /* This case exists because on the r3000 trunc
5351 expands into a macro which requires a gp
5352 register. On the r6000 or r4000 it is
5353 assembled into a single instruction which
5354 ignores the register. Thus the insn version
5355 is MIPS_ISA2 and uses 'x', and the macro
5356 version is MIPS_ISA1 and uses 't'. */
5359 /* This case is for the div instruction, which
5360 acts differently if the destination argument
5361 is $0. This only matches $0, and is checked
5362 outside the switch. */
5373 ip
->insn_opcode
|= lastregno
<< 21;
5376 ip
->insn_opcode
|= lastregno
<< 16;
5381 case 'D': /* floating point destination register */
5382 case 'S': /* floating point source register */
5383 case 'T': /* floating point target register */
5384 case 'R': /* floating point source register */
5388 if (s
[0] == '$' && s
[1] == 'f' && isdigit (s
[2]))
5398 while (isdigit (*s
));
5401 as_bad ("Invalid float register number (%d)", regno
);
5403 if ((regno
& 1) != 0
5405 && ! (strcmp (str
, "mtc1") == 0 ||
5406 strcmp (str
, "mfc1") == 0 ||
5407 strcmp (str
, "lwc1") == 0 ||
5408 strcmp (str
, "swc1") == 0))
5409 as_warn ("Float register should be even, was %d",
5417 if (c
== 'V' || c
== 'W')
5427 ip
->insn_opcode
|= regno
<< 6;
5431 ip
->insn_opcode
|= regno
<< 11;
5435 ip
->insn_opcode
|= regno
<< 16;
5438 ip
->insn_opcode
|= regno
<< 21;
5447 ip
->insn_opcode
|= lastregno
<< 11;
5450 ip
->insn_opcode
|= lastregno
<< 16;
5456 my_getExpression (&imm_expr
, s
);
5457 if (imm_expr
.X_op
!= O_big
5458 && imm_expr
.X_op
!= O_constant
)
5459 insn_error
= "absolute expression required";
5464 my_getExpression (&offset_expr
, s
);
5465 imm_reloc
= BFD_RELOC_32
;
5477 unsigned char temp
[8];
5479 unsigned int length
;
5484 /* These only appear as the last operand in an
5485 instruction, and every instruction that accepts
5486 them in any variant accepts them in all variants.
5487 This means we don't have to worry about backing out
5488 any changes if the instruction does not match.
5490 The difference between them is the size of the
5491 floating point constant and where it goes. For 'F'
5492 and 'L' the constant is 64 bits; for 'f' and 'l' it
5493 is 32 bits. Where the constant is placed is based
5494 on how the MIPS assembler does things:
5497 f -- immediate value
5500 The .lit4 and .lit8 sections are only used if
5501 permitted by the -G argument.
5503 When generating embedded PIC code, we use the
5504 .lit8 section but not the .lit4 section (we can do
5505 .lit4 inline easily; we need to put .lit8
5506 somewhere in the data segment, and using .lit8
5507 permits the linker to eventually combine identical
5510 f64
= *args
== 'F' || *args
== 'L';
5512 save_in
= input_line_pointer
;
5513 input_line_pointer
= s
;
5514 err
= md_atof (f64
? 'd' : 'f', (char *) temp
, &len
);
5516 s
= input_line_pointer
;
5517 input_line_pointer
= save_in
;
5518 if (err
!= NULL
&& *err
!= '\0')
5520 as_bad ("Bad floating point constant: %s", err
);
5521 memset (temp
, '\0', sizeof temp
);
5522 length
= f64
? 8 : 4;
5525 assert (length
== (f64
? 8 : 4));
5529 && (! USE_GLOBAL_POINTER_OPT
5530 || mips_pic
== EMBEDDED_PIC
5531 || g_switch_value
< 4)
5534 imm_expr
.X_op
= O_constant
;
5535 if (byte_order
== LITTLE_ENDIAN
)
5536 imm_expr
.X_add_number
=
5537 (((((((int) temp
[3] << 8)
5542 imm_expr
.X_add_number
=
5543 (((((((int) temp
[0] << 8)
5550 const char *newname
;
5553 /* Switch to the right section. */
5555 subseg
= now_subseg
;
5558 default: /* unused default case avoids warnings. */
5560 newname
= RDATA_SECTION_NAME
;
5561 if (USE_GLOBAL_POINTER_OPT
&& g_switch_value
>= 8)
5565 newname
= RDATA_SECTION_NAME
;
5568 assert (!USE_GLOBAL_POINTER_OPT
5569 || g_switch_value
>= 4);
5573 new_seg
= subseg_new (newname
, (subsegT
) 0);
5574 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
5575 bfd_set_section_flags (stdoutput
, new_seg
,
5580 frag_align (*args
== 'l' ? 2 : 3, 0);
5581 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
5582 record_alignment (new_seg
, 4);
5584 record_alignment (new_seg
, *args
== 'l' ? 2 : 3);
5586 as_bad ("Can't use floating point insn in this section");
5588 /* Set the argument to the current address in the
5590 offset_expr
.X_op
= O_symbol
;
5591 offset_expr
.X_add_symbol
=
5592 symbol_new ("L0\001", now_seg
,
5593 (valueT
) frag_now_fix (), frag_now
);
5594 offset_expr
.X_add_number
= 0;
5596 /* Put the floating point number into the section. */
5597 p
= frag_more ((int) length
);
5598 memcpy (p
, temp
, length
);
5600 /* Switch back to the original section. */
5601 subseg_set (seg
, subseg
);
5606 case 'i': /* 16 bit unsigned immediate */
5607 case 'j': /* 16 bit signed immediate */
5608 imm_reloc
= BFD_RELOC_LO16
;
5609 c
= my_getSmallExpression (&imm_expr
, s
);
5614 if (imm_expr
.X_op
== O_constant
)
5615 imm_expr
.X_add_number
=
5616 (imm_expr
.X_add_number
>> 16) & 0xffff;
5619 imm_reloc
= BFD_RELOC_HI16_S
;
5620 imm_unmatched_hi
= true;
5623 imm_reloc
= BFD_RELOC_HI16
;
5628 if ((c
== '\0' && imm_expr
.X_op
!= O_constant
)
5629 || imm_expr
.X_add_number
< 0
5630 || imm_expr
.X_add_number
>= 0x10000)
5632 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
5633 !strcmp (insn
->name
, insn
[1].name
))
5635 if (imm_expr
.X_op
!= O_constant
5636 && imm_expr
.X_op
!= O_big
)
5637 insn_error
= "absolute expression required";
5639 as_bad ("16 bit expression not in range 0..65535");
5647 /* The upper bound should be 0x8000, but
5648 unfortunately the MIPS assembler accepts numbers
5649 from 0x8000 to 0xffff and sign extends them, and
5650 we want to be compatible. We only permit this
5651 extended range for an instruction which does not
5652 provide any further alternates, since those
5653 alternates may handle other cases. People should
5654 use the numbers they mean, rather than relying on
5655 a mysterious sign extension. */
5656 more
= (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
5657 strcmp (insn
->name
, insn
[1].name
) == 0);
5662 if ((c
== '\0' && imm_expr
.X_op
!= O_constant
)
5663 || imm_expr
.X_add_number
< -0x8000
5664 || imm_expr
.X_add_number
>= max
5666 && imm_expr
.X_add_number
< 0
5668 && imm_expr
.X_unsigned
5669 && sizeof (imm_expr
.X_add_number
) <= 4))
5673 if (imm_expr
.X_op
!= O_constant
5674 && imm_expr
.X_op
!= O_big
)
5675 insn_error
= "absolute expression required";
5677 as_bad ("16 bit expression not in range -32768..32767");
5683 case 'o': /* 16 bit offset */
5684 c
= my_getSmallExpression (&offset_expr
, s
);
5686 /* If this value won't fit into a 16 bit offset, then go
5687 find a macro that will generate the 32 bit offset
5688 code pattern. As a special hack, we accept the
5689 difference of two local symbols as a constant. This
5690 is required to suppose embedded PIC switches, which
5691 use an instruction which looks like
5692 lw $4,$L12-$LS12($4)
5693 The problem with handling this in a more general
5694 fashion is that the macro function doesn't expect to
5695 see anything which can be handled in a single
5696 constant instruction. */
5698 && (offset_expr
.X_op
!= O_constant
5699 || offset_expr
.X_add_number
>= 0x8000
5700 || offset_expr
.X_add_number
< -0x8000)
5701 && (mips_pic
!= EMBEDDED_PIC
5702 || offset_expr
.X_op
!= O_subtract
5703 || now_seg
!= text_section
5704 || (S_GET_SEGMENT (offset_expr
.X_op_symbol
)
5708 offset_reloc
= BFD_RELOC_LO16
;
5709 if (c
== 'h' || c
== 'H')
5711 assert (offset_expr
.X_op
== O_constant
);
5712 offset_expr
.X_add_number
=
5713 (offset_expr
.X_add_number
>> 16) & 0xffff;
5718 case 'p': /* pc relative offset */
5719 offset_reloc
= BFD_RELOC_16_PCREL_S2
;
5720 my_getExpression (&offset_expr
, s
);
5724 case 'u': /* upper 16 bits */
5725 c
= my_getSmallExpression (&imm_expr
, s
);
5726 if (imm_expr
.X_op
== O_constant
5727 && (imm_expr
.X_add_number
< 0
5728 || imm_expr
.X_add_number
>= 0x10000))
5729 as_bad ("lui expression not in range 0..65535");
5730 imm_reloc
= BFD_RELOC_LO16
;
5735 if (imm_expr
.X_op
== O_constant
)
5736 imm_expr
.X_add_number
=
5737 (imm_expr
.X_add_number
>> 16) & 0xffff;
5740 imm_reloc
= BFD_RELOC_HI16_S
;
5741 imm_unmatched_hi
= true;
5744 imm_reloc
= BFD_RELOC_HI16
;
5750 case 'a': /* 26 bit address */
5751 my_getExpression (&offset_expr
, s
);
5753 offset_reloc
= BFD_RELOC_MIPS_JMP
;
5756 case 'N': /* 3 bit branch condition code */
5757 case 'M': /* 3 bit compare condition code */
5758 my_getExpression (&imm_expr
, s
);
5759 check_absolute_expr (ip
, &imm_expr
);
5760 if ((unsigned long) imm_expr
.X_add_number
> 7)
5762 as_warn ("Condition code > 7 (%ld)",
5763 (long) imm_expr
.X_add_number
);
5764 imm_expr
.X_add_number
&= 7;
5767 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_BCC
;
5769 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_CCC
;
5770 imm_expr
.X_op
= O_absent
;
5775 fprintf (stderr
, "bad char = '%c'\n", *args
);
5780 /* Args don't match. */
5781 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
5782 !strcmp (insn
->name
, insn
[1].name
))
5788 insn_error
= "illegal operands";
5797 my_getSmallExpression (ep
, str
)
5808 ((str
[1] == 'h' && str
[2] == 'i')
5809 || (str
[1] == 'H' && str
[2] == 'I')
5810 || (str
[1] == 'l' && str
[2] == 'o'))
5822 * A small expression may be followed by a base register.
5823 * Scan to the end of this operand, and then back over a possible
5824 * base register. Then scan the small expression up to that
5825 * point. (Based on code in sparc.c...)
5827 for (sp
= str
; *sp
&& *sp
!= ','; sp
++)
5829 if (sp
- 4 >= str
&& sp
[-1] == RP
)
5831 if (isdigit (sp
[-2]))
5833 for (sp
-= 3; sp
>= str
&& isdigit (*sp
); sp
--)
5835 if (*sp
== '$' && sp
> str
&& sp
[-1] == LP
)
5841 else if (sp
- 5 >= str
5844 && ((sp
[-3] == 'f' && sp
[-2] == 'p')
5845 || (sp
[-3] == 's' && sp
[-2] == 'p')
5846 || (sp
[-3] == 'g' && sp
[-2] == 'p')
5847 || (sp
[-3] == 'a' && sp
[-2] == 't')))
5853 /* no expression means zero offset */
5856 /* %xx(reg) is an error */
5857 ep
->X_op
= O_absent
;
5862 ep
->X_op
= O_constant
;
5865 ep
->X_add_symbol
= NULL
;
5866 ep
->X_op_symbol
= NULL
;
5867 ep
->X_add_number
= 0;
5872 my_getExpression (ep
, str
);
5879 my_getExpression (ep
, str
);
5880 return c
; /* => %hi or %lo encountered */
5884 my_getExpression (ep
, str
)
5890 save_in
= input_line_pointer
;
5891 input_line_pointer
= str
;
5893 expr_end
= input_line_pointer
;
5894 input_line_pointer
= save_in
;
5897 /* Turn a string in input_line_pointer into a floating point constant
5898 of type type, and store the appropriate bytes in *litP. The number
5899 of LITTLENUMS emitted is stored in *sizeP . An error message is
5900 returned, or NULL on OK. */
5903 md_atof (type
, litP
, sizeP
)
5909 LITTLENUM_TYPE words
[4];
5925 return "bad call to md_atof";
5928 t
= atof_ieee (input_line_pointer
, type
, words
);
5930 input_line_pointer
= t
;
5934 if (byte_order
== LITTLE_ENDIAN
)
5936 for (i
= prec
- 1; i
>= 0; i
--)
5938 md_number_to_chars (litP
, (valueT
) words
[i
], 2);
5944 for (i
= 0; i
< prec
; i
++)
5946 md_number_to_chars (litP
, (valueT
) words
[i
], 2);
5955 md_number_to_chars (buf
, val
, n
)
5963 number_to_chars_littleendian (buf
, val
, n
);
5967 number_to_chars_bigendian (buf
, val
, n
);
5975 CONST
char *md_shortopts
= "O::g::G:";
5977 struct option md_longopts
[] = {
5978 #define OPTION_MIPS1 (OPTION_MD_BASE + 1)
5979 {"mips0", no_argument
, NULL
, OPTION_MIPS1
},
5980 {"mips1", no_argument
, NULL
, OPTION_MIPS1
},
5981 #define OPTION_MIPS2 (OPTION_MD_BASE + 2)
5982 {"mips2", no_argument
, NULL
, OPTION_MIPS2
},
5983 #define OPTION_MIPS3 (OPTION_MD_BASE + 3)
5984 {"mips3", no_argument
, NULL
, OPTION_MIPS3
},
5985 #define OPTION_MIPS4 (OPTION_MD_BASE + 4)
5986 {"mips4", no_argument
, NULL
, OPTION_MIPS4
},
5987 #define OPTION_MCPU (OPTION_MD_BASE + 5)
5988 {"mcpu", required_argument
, NULL
, OPTION_MCPU
},
5989 #define OPTION_MEMBEDDED_PIC (OPTION_MD_BASE + 6)
5990 {"membedded-pic", no_argument
, NULL
, OPTION_MEMBEDDED_PIC
},
5991 #define OPTION_TRAP (OPTION_MD_BASE + 9)
5992 {"trap", no_argument
, NULL
, OPTION_TRAP
},
5993 {"no-break", no_argument
, NULL
, OPTION_TRAP
},
5994 #define OPTION_BREAK (OPTION_MD_BASE + 10)
5995 {"break", no_argument
, NULL
, OPTION_BREAK
},
5996 {"no-trap", no_argument
, NULL
, OPTION_BREAK
},
5997 #define OPTION_EB (OPTION_MD_BASE + 11)
5998 {"EB", no_argument
, NULL
, OPTION_EB
},
5999 #define OPTION_EL (OPTION_MD_BASE + 12)
6000 {"EL", no_argument
, NULL
, OPTION_EL
},
6001 #define OPTION_M4650 (OPTION_MD_BASE + 13)
6002 {"m4650", no_argument
, NULL
, OPTION_M4650
},
6003 #define OPTION_NO_M4650 (OPTION_MD_BASE + 14)
6004 {"no-m4650", no_argument
, NULL
, OPTION_NO_M4650
},
6005 #define OPTION_M4010 (OPTION_MD_BASE + 15)
6006 {"m4010", no_argument
, NULL
, OPTION_M4010
},
6007 #define OPTION_NO_M4010 (OPTION_MD_BASE + 16)
6008 {"no-m4010", no_argument
, NULL
, OPTION_NO_M4010
},
6009 #define OPTION_M4100 (OPTION_MD_BASE + 17)
6010 {"m4100", no_argument
, NULL
, OPTION_M4100
},
6011 #define OPTION_NO_M4100 (OPTION_MD_BASE + 18)
6012 {"no-m4100", no_argument
, NULL
, OPTION_NO_M4100
},
6014 #define OPTION_CALL_SHARED (OPTION_MD_BASE + 7)
6015 #define OPTION_NON_SHARED (OPTION_MD_BASE + 8)
6016 #define OPTION_XGOT (OPTION_MD_BASE + 19)
6017 #define OPTION_32 (OPTION_MD_BASE + 20)
6018 #define OPTION_64 (OPTION_MD_BASE + 21)
6020 {"KPIC", no_argument
, NULL
, OPTION_CALL_SHARED
},
6021 {"xgot", no_argument
, NULL
, OPTION_XGOT
},
6022 {"call_shared", no_argument
, NULL
, OPTION_CALL_SHARED
},
6023 {"non_shared", no_argument
, NULL
, OPTION_NON_SHARED
},
6024 {"32", no_argument
, NULL
, OPTION_32
},
6025 {"64", no_argument
, NULL
, OPTION_64
},
6028 {NULL
, no_argument
, NULL
, 0}
6030 size_t md_longopts_size
= sizeof(md_longopts
);
6033 md_parse_option (c
, arg
)
6048 target_big_endian
= 1;
6052 target_big_endian
= 0;
6056 if (arg
&& arg
[1] == '0')
6066 mips_debug
= atoi (arg
);
6067 /* When the MIPS assembler sees -g or -g2, it does not do
6068 optimizations which limit full symbolic debugging. We take
6069 that to be equivalent to -O0. */
6070 if (mips_debug
== 2)
6102 /* Identify the processor type */
6104 if (strcmp (p
, "default") == 0
6105 || strcmp (p
, "DEFAULT") == 0)
6111 /* We need to cope with the various "vr" prefixes for the 4300
6113 if (*p
== 'v' || *p
== 'V')
6119 if (*p
== 'r' || *p
== 'R')
6126 if (strcmp (p
, "10000") == 0
6127 || strcmp (p
, "10k") == 0
6128 || strcmp (p
, "10K") == 0)
6133 if (strcmp (p
, "2000") == 0
6134 || strcmp (p
, "2k") == 0
6135 || strcmp (p
, "2K") == 0)
6140 if (strcmp (p
, "3000") == 0
6141 || strcmp (p
, "3k") == 0
6142 || strcmp (p
, "3K") == 0)
6147 if (strcmp (p
, "4000") == 0
6148 || strcmp (p
, "4k") == 0
6149 || strcmp (p
, "4K") == 0)
6151 else if (strcmp (p
, "4100") == 0)
6157 else if (strcmp (p
, "4300") == 0)
6159 else if (strcmp (p
, "4400") == 0)
6161 else if (strcmp (p
, "4600") == 0)
6163 else if (strcmp (p
, "4650") == 0)
6169 else if (strcmp (p
, "4010") == 0)
6178 if (strcmp (p
, "6000") == 0
6179 || strcmp (p
, "6k") == 0
6180 || strcmp (p
, "6K") == 0)
6185 if (strcmp (p
, "8000") == 0
6186 || strcmp (p
, "8k") == 0
6187 || strcmp (p
, "8K") == 0)
6192 if (strcmp (p
, "orion") == 0)
6197 if (sv
&& mips_cpu
!= 4300 && mips_cpu
!= 4100)
6199 as_bad ("ignoring invalid leading 'v' in -mcpu=%s switch", arg
);
6205 as_bad ("invalid architecture -mcpu=%s", arg
);
6216 case OPTION_NO_M4650
:
6224 case OPTION_NO_M4010
:
6232 case OPTION_NO_M4100
:
6236 case OPTION_MEMBEDDED_PIC
:
6237 mips_pic
= EMBEDDED_PIC
;
6238 if (USE_GLOBAL_POINTER_OPT
&& g_switch_seen
)
6240 as_bad ("-G may not be used with embedded PIC code");
6243 g_switch_value
= 0x7fffffff;
6246 /* When generating ELF code, we permit -KPIC and -call_shared to
6247 select SVR4_PIC, and -non_shared to select no PIC. This is
6248 intended to be compatible with Irix 5. */
6249 case OPTION_CALL_SHARED
:
6250 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
6252 as_bad ("-call_shared is supported only for ELF format");
6255 mips_pic
= SVR4_PIC
;
6256 if (g_switch_seen
&& g_switch_value
!= 0)
6258 as_bad ("-G may not be used with SVR4 PIC code");
6264 case OPTION_NON_SHARED
:
6265 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
6267 as_bad ("-non_shared is supported only for ELF format");
6273 /* The -xgot option tells the assembler to use 32 offsets when
6274 accessing the got in SVR4_PIC mode. It is for Irix
6281 if (! USE_GLOBAL_POINTER_OPT
)
6283 as_bad ("-G is not supported for this configuration");
6286 else if (mips_pic
== SVR4_PIC
|| mips_pic
== EMBEDDED_PIC
)
6288 as_bad ("-G may not be used with SVR4 or embedded PIC code");
6292 g_switch_value
= atoi (arg
);
6296 /* The -32 and -64 options tell the assembler to output the 32
6297 bit or the 64 bit MIPS ELF format. */
6304 const char **list
, **l
;
6306 list
= bfd_target_list ();
6307 for (l
= list
; *l
!= NULL
; l
++)
6308 if (strcmp (*l
, "elf64-bigmips") == 0
6309 || strcmp (*l
, "elf64-littlemips") == 0)
6312 as_fatal ("No compiled in support for 64 bit object file format");
6326 md_show_usage (stream
)
6331 -membedded-pic generate embedded position independent code\n\
6332 -EB generate big endian output\n\
6333 -EL generate little endian output\n\
6334 -g, -g2 do not remove uneeded NOPs or swap branches\n\
6335 -G NUM allow referencing objects up to NUM bytes\n\
6336 implicitly with the gp register [default 8]\n");
6338 -mips1, -mcpu=r{2,3}000 generate code for r2000 and r3000\n\
6339 -mips2, -mcpu=r6000 generate code for r6000\n\
6340 -mips3, -mcpu=r4000 generate code for r4000\n\
6341 -mips4, -mcpu=r8000 generate code for r8000\n\
6342 -mcpu=vr4300 generate code for vr4300\n\
6343 -mcpu=vr4100 generate code for vr4100\n\
6344 -m4650 permit R4650 instructions\n\
6345 -no-m4650 do not permit R4650 instructions\n\
6346 -m4010 permit R4010 instructions\n\
6347 -no-m4010 do not permit R4010 instructions\n\
6348 -m4100 permit VR4100 instructions\n\
6349 -no-m4100 do not permit VR4100 instructions\n");
6351 -O0 remove unneeded NOPs, do not swap branches\n\
6352 -O remove unneeded NOPs and swap branches\n\
6353 --trap, --no-break trap exception on div by 0 and mult overflow\n\
6354 --break, --no-trap break exception on div by 0 and mult overflow\n");
6357 -KPIC, -call_shared generate SVR4 position independent code\n\
6358 -non_shared do not generate position independent code\n\
6359 -xgot assume a 32 bit GOT\n\
6360 -32 create 32 bit object file (default)\n\
6361 -64 create 64 bit object file\n");
6366 mips_init_after_args ()
6368 if (target_big_endian
)
6369 byte_order
= BIG_ENDIAN
;
6371 byte_order
= LITTLE_ENDIAN
;
6375 md_pcrel_from (fixP
)
6378 if (OUTPUT_FLAVOR
!= bfd_target_aout_flavour
6379 && fixP
->fx_addsy
!= (symbolS
*) NULL
6380 && ! S_IS_DEFINED (fixP
->fx_addsy
))
6382 /* This makes a branch to an undefined symbol be a branch to the
6383 current location. */
6387 /* return the address of the delay slot */
6388 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
6391 /* This is called by emit_expr via TC_CONS_FIX_NEW when creating a
6392 reloc for a cons. We could use the definition there, except that
6393 we want to handle 64 bit relocs specially. */
6396 cons_fix_new_mips (frag
, where
, nbytes
, exp
)
6399 unsigned int nbytes
;
6402 /* If we are assembling in 32 bit mode, turn an 8 byte reloc into a
6404 if (nbytes
== 8 && ! mips_64
)
6406 if (byte_order
== BIG_ENDIAN
)
6411 if (nbytes
!= 2 && nbytes
!= 4 && nbytes
!= 8)
6412 as_bad ("Unsupported reloc size %d", nbytes
);
6414 fix_new_exp (frag_now
, where
, (int) nbytes
, exp
, 0,
6417 : (nbytes
== 4 ? BFD_RELOC_32
: BFD_RELOC_64
)));
6420 /* Sort any unmatched HI16_S relocs so that they immediately precede
6421 the corresponding LO reloc. This is called before md_apply_fix and
6422 tc_gen_reloc. Unmatched HI16_S relocs can only be generated by
6423 explicit use of the %hi modifier. */
6428 struct mips_hi_fixup
*l
;
6430 for (l
= mips_hi_fixup_list
; l
!= NULL
; l
= l
->next
)
6432 segment_info_type
*seginfo
;
6435 assert (l
->fixp
->fx_r_type
== BFD_RELOC_HI16_S
);
6437 /* Check quickly whether the next fixup happens to be a matching
6439 if (l
->fixp
->fx_next
!= NULL
6440 && l
->fixp
->fx_next
->fx_r_type
== BFD_RELOC_LO16
6441 && l
->fixp
->fx_addsy
== l
->fixp
->fx_next
->fx_addsy
6442 && l
->fixp
->fx_offset
== l
->fixp
->fx_next
->fx_offset
)
6445 /* Look through the fixups for this segment for a matching %lo.
6446 When we find one, move the %hi just in front of it. We do
6447 this in two passes. In the first pass, we try to find a
6448 unique %lo. In the second pass, we permit multiple %hi
6449 relocs for a single %lo (this is a GNU extension). */
6450 seginfo
= seg_info (l
->seg
);
6451 for (pass
= 0; pass
< 2; pass
++)
6456 for (f
= seginfo
->fix_root
; f
!= NULL
; f
= f
->fx_next
)
6458 /* Check whether this is a %lo fixup which matches l->fixp. */
6459 if (f
->fx_r_type
== BFD_RELOC_LO16
6460 && f
->fx_addsy
== l
->fixp
->fx_addsy
6461 && f
->fx_offset
== l
->fixp
->fx_offset
6464 || prev
->fx_r_type
!= BFD_RELOC_HI16_S
6465 || prev
->fx_addsy
!= f
->fx_addsy
6466 || prev
->fx_offset
!= f
->fx_offset
))
6470 /* Move l->fixp before f. */
6471 for (pf
= &seginfo
->fix_root
;
6473 pf
= &(*pf
)->fx_next
)
6474 assert (*pf
!= NULL
);
6476 *pf
= l
->fixp
->fx_next
;
6478 l
->fixp
->fx_next
= f
;
6480 seginfo
->fix_root
= l
->fixp
;
6482 prev
->fx_next
= l
->fixp
;
6494 as_warn_where (l
->fixp
->fx_file
, l
->fixp
->fx_line
,
6495 "Unmatched %%hi reloc");
6500 /* When generating embedded PIC code we need to use a special
6501 relocation to represent the difference of two symbols in the .text
6502 section (switch tables use a difference of this sort). See
6503 include/coff/mips.h for details. This macro checks whether this
6504 fixup requires the special reloc. */
6505 #define SWITCH_TABLE(fixp) \
6506 ((fixp)->fx_r_type == BFD_RELOC_32 \
6507 && (fixp)->fx_addsy != NULL \
6508 && (fixp)->fx_subsy != NULL \
6509 && S_GET_SEGMENT ((fixp)->fx_addsy) == text_section \
6510 && S_GET_SEGMENT ((fixp)->fx_subsy) == text_section)
6512 /* When generating embedded PIC code we must keep all PC relative
6513 relocations, in case the linker has to relax a call. We also need
6514 to keep relocations for switch table entries. */
6518 mips_force_relocation (fixp
)
6521 return (mips_pic
== EMBEDDED_PIC
6523 || SWITCH_TABLE (fixp
)
6524 || fixp
->fx_r_type
== BFD_RELOC_PCREL_HI16_S
6525 || fixp
->fx_r_type
== BFD_RELOC_PCREL_LO16
));
6528 /* Apply a fixup to the object file. */
6531 md_apply_fix (fixP
, valueP
)
6538 assert (fixP
->fx_size
== 4 || fixP
->fx_r_type
== BFD_RELOC_16
);
6541 fixP
->fx_addnumber
= value
; /* Remember value for tc_gen_reloc */
6543 if (fixP
->fx_addsy
== NULL
&& ! fixP
->fx_pcrel
)
6546 switch (fixP
->fx_r_type
)
6548 case BFD_RELOC_MIPS_JMP
:
6549 case BFD_RELOC_HI16
:
6550 case BFD_RELOC_HI16_S
:
6551 case BFD_RELOC_MIPS_GPREL
:
6552 case BFD_RELOC_MIPS_LITERAL
:
6553 case BFD_RELOC_MIPS_CALL16
:
6554 case BFD_RELOC_MIPS_GOT16
:
6555 case BFD_RELOC_MIPS_GPREL32
:
6556 case BFD_RELOC_MIPS_GOT_HI16
:
6557 case BFD_RELOC_MIPS_GOT_LO16
:
6558 case BFD_RELOC_MIPS_CALL_HI16
:
6559 case BFD_RELOC_MIPS_CALL_LO16
:
6561 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
6562 "Invalid PC relative reloc");
6563 /* Nothing needed to do. The value comes from the reloc entry */
6566 case BFD_RELOC_PCREL_HI16_S
:
6567 /* The addend for this is tricky if it is internal, so we just
6568 do everything here rather than in bfd_perform_relocation. */
6569 if ((fixP
->fx_addsy
->bsym
->flags
& BSF_SECTION_SYM
) == 0)
6571 /* For an external symbol adjust by the address to make it
6572 pcrel_offset. We use the address of the RELLO reloc
6573 which follows this one. */
6574 value
+= (fixP
->fx_next
->fx_frag
->fr_address
6575 + fixP
->fx_next
->fx_where
);
6580 buf
= (unsigned char *) fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
6581 if (byte_order
== BIG_ENDIAN
)
6583 md_number_to_chars (buf
, value
, 2);
6586 case BFD_RELOC_PCREL_LO16
:
6587 /* The addend for this is tricky if it is internal, so we just
6588 do everything here rather than in bfd_perform_relocation. */
6589 if ((fixP
->fx_addsy
->bsym
->flags
& BSF_SECTION_SYM
) == 0)
6590 value
+= fixP
->fx_frag
->fr_address
+ fixP
->fx_where
;
6591 buf
= (unsigned char *) fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
6592 if (byte_order
== BIG_ENDIAN
)
6594 md_number_to_chars (buf
, value
, 2);
6598 /* If we are deleting this reloc entry, we must fill in the
6599 value now. This can happen if we have a .word which is not
6600 resolved when it appears but is later defined. We also need
6601 to fill in the value if this is an embedded PIC switch table
6604 || (mips_pic
== EMBEDDED_PIC
&& SWITCH_TABLE (fixP
)))
6605 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
,
6610 /* If we are deleting this reloc entry, we must fill in the
6612 assert (fixP
->fx_size
== 2);
6614 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
,
6618 case BFD_RELOC_LO16
:
6619 /* When handling an embedded PIC switch statement, we can wind
6620 up deleting a LO16 reloc. See the 'o' case in mips_ip. */
6623 if (value
< -0x8000 || value
> 0x7fff)
6624 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
6625 "relocation overflow");
6626 buf
= (unsigned char *) fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
6627 if (byte_order
== BIG_ENDIAN
)
6629 md_number_to_chars (buf
, value
, 2);
6633 case BFD_RELOC_16_PCREL_S2
:
6635 * We need to save the bits in the instruction since fixup_segment()
6636 * might be deleting the relocation entry (i.e., a branch within
6637 * the current segment).
6640 as_warn_where (fixP
->fx_file
, fixP
->fx_line
,
6641 "Branch to odd address (%lx)", value
);
6644 /* update old instruction data */
6645 buf
= (unsigned char *) (fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
);
6649 insn
= (buf
[3] << 24) | (buf
[2] << 16) | (buf
[1] << 8) | buf
[0];
6653 insn
= (buf
[0] << 24) | (buf
[1] << 16) | (buf
[2] << 8) | buf
[3];
6661 if (value
>= -0x8000 && value
< 0x8000)
6662 insn
|= value
& 0xffff;
6665 /* The branch offset is too large. If this is an
6666 unconditional branch, and we are not generating PIC code,
6667 we can convert it to an absolute jump instruction. */
6668 if (mips_pic
== NO_PIC
6670 && fixP
->fx_frag
->fr_address
>= text_section
->vma
6671 && (fixP
->fx_frag
->fr_address
6672 < text_section
->vma
+ text_section
->_raw_size
)
6673 && ((insn
& 0xffff0000) == 0x10000000 /* beq $0,$0 */
6674 || (insn
& 0xffff0000) == 0x04010000 /* bgez $0 */
6675 || (insn
& 0xffff0000) == 0x04110000)) /* bgezal $0 */
6677 if ((insn
& 0xffff0000) == 0x04110000) /* bgezal $0 */
6678 insn
= 0x0c000000; /* jal */
6680 insn
= 0x08000000; /* j */
6681 fixP
->fx_r_type
= BFD_RELOC_MIPS_JMP
;
6683 fixP
->fx_addsy
= section_symbol (text_section
);
6684 fixP
->fx_addnumber
= (value
<< 2) + md_pcrel_from (fixP
);
6688 /* FIXME. It would be possible in principle to handle
6689 conditional branches which overflow. They could be
6690 transformed into a branch around a jump. This would
6691 require setting up variant frags for each different
6692 branch type. The native MIPS assembler attempts to
6693 handle these cases, but it appears to do it
6695 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
6696 "Relocation overflow");
6700 md_number_to_chars ((char *) buf
, (valueT
) insn
, 4);
6715 const struct mips_opcode
*p
;
6716 int treg
, sreg
, dreg
, shamt
;
6721 for (i
= 0; i
< NUMOPCODES
; ++i
)
6723 p
= &mips_opcodes
[i
];
6724 if (((oc
& p
->mask
) == p
->match
) && (p
->pinfo
!= INSN_MACRO
))
6726 printf ("%08lx %s\t", oc
, p
->name
);
6727 treg
= (oc
>> 16) & 0x1f;
6728 sreg
= (oc
>> 21) & 0x1f;
6729 dreg
= (oc
>> 11) & 0x1f;
6730 shamt
= (oc
>> 6) & 0x1f;
6732 for (args
= p
->args
;; ++args
)
6743 printf ("%c", *args
);
6747 assert (treg
== sreg
);
6748 printf ("$%d,$%d", treg
, sreg
);
6753 printf ("$%d", dreg
);
6758 printf ("$%d", treg
);
6762 printf ("0x%x", treg
);
6767 printf ("$%d", sreg
);
6771 printf ("0x%08lx", oc
& 0x1ffffff);
6783 printf ("$%d", shamt
);
6794 printf ("%08lx UNDEFINED\n", oc
);
6805 name
= input_line_pointer
;
6806 c
= get_symbol_end ();
6807 p
= (symbolS
*) symbol_find_or_make (name
);
6808 *input_line_pointer
= c
;
6812 /* Align the current frag to a given power of two. The MIPS assembler
6813 also automatically adjusts any preceding label. */
6816 mips_align (to
, fill
, label
)
6821 mips_emit_delays ();
6822 frag_align (to
, fill
);
6823 record_alignment (now_seg
, to
);
6826 assert (S_GET_SEGMENT (label
) == now_seg
);
6827 label
->sy_frag
= frag_now
;
6828 S_SET_VALUE (label
, (valueT
) frag_now_fix ());
6832 /* Align to a given power of two. .align 0 turns off the automatic
6833 alignment used by the data creating pseudo-ops. */
6840 register long temp_fill
;
6841 long max_alignment
= 15;
6845 o Note that the assembler pulls down any immediately preceeding label
6846 to the aligned address.
6847 o It's not documented but auto alignment is reinstated by
6848 a .align pseudo instruction.
6849 o Note also that after auto alignment is turned off the mips assembler
6850 issues an error on attempt to assemble an improperly aligned data item.
6855 temp
= get_absolute_expression ();
6856 if (temp
> max_alignment
)
6857 as_bad ("Alignment too large: %d. assumed.", temp
= max_alignment
);
6860 as_warn ("Alignment negative: 0 assumed.");
6863 if (*input_line_pointer
== ',')
6865 input_line_pointer
++;
6866 temp_fill
= get_absolute_expression ();
6873 mips_align (temp
, (int) temp_fill
, insn_label
);
6880 demand_empty_rest_of_line ();
6884 mips_flush_pending_output ()
6886 mips_emit_delays ();
6896 /* When generating embedded PIC code, we only use the .text, .lit8,
6897 .sdata and .sbss sections. We change the .data and .rdata
6898 pseudo-ops to use .sdata. */
6899 if (mips_pic
== EMBEDDED_PIC
6900 && (sec
== 'd' || sec
== 'r'))
6903 mips_emit_delays ();
6913 subseg_set (bss_section
, (subsegT
) get_absolute_expression ());
6914 demand_empty_rest_of_line ();
6918 if (USE_GLOBAL_POINTER_OPT
)
6920 seg
= subseg_new (RDATA_SECTION_NAME
,
6921 (subsegT
) get_absolute_expression ());
6922 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
6924 bfd_set_section_flags (stdoutput
, seg
,
6930 bfd_set_section_alignment (stdoutput
, seg
, 4);
6932 demand_empty_rest_of_line ();
6936 as_bad ("No read only data section in this object file format");
6937 demand_empty_rest_of_line ();
6943 if (USE_GLOBAL_POINTER_OPT
)
6945 seg
= subseg_new (".sdata", (subsegT
) get_absolute_expression ());
6946 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
6948 bfd_set_section_flags (stdoutput
, seg
,
6949 SEC_ALLOC
| SEC_LOAD
| SEC_RELOC
6951 bfd_set_section_alignment (stdoutput
, seg
, 4);
6953 demand_empty_rest_of_line ();
6958 as_bad ("Global pointers not supported; recompile -G 0");
6959 demand_empty_rest_of_line ();
6968 mips_enable_auto_align ()
6980 mips_emit_delays ();
6981 if (log_size
> 0 && auto_align
)
6982 mips_align (log_size
, 0, label
);
6984 cons (1 << log_size
);
6995 mips_emit_delays ();
6999 mips_align (3, 0, label
);
7001 mips_align (2, 0, label
);
7008 /* Handle .globl. We need to override it because on Irix 5 you are
7011 where foo is an undefined symbol, to mean that foo should be
7012 considered to be the address of a function. */
7023 name
= input_line_pointer
;
7024 c
= get_symbol_end ();
7025 symbolP
= symbol_find_or_make (name
);
7026 *input_line_pointer
= c
;
7029 /* On Irix 5, every global symbol that is not explicitly labelled as
7030 being a function is apparently labelled as being an object. */
7033 if (! is_end_of_line
[(unsigned char) *input_line_pointer
])
7038 secname
= input_line_pointer
;
7039 c
= get_symbol_end ();
7040 sec
= bfd_get_section_by_name (stdoutput
, secname
);
7042 as_bad ("%s: no such section", secname
);
7043 *input_line_pointer
= c
;
7045 if (sec
!= NULL
&& (sec
->flags
& SEC_CODE
) != 0)
7046 flag
= BSF_FUNCTION
;
7049 symbolP
->bsym
->flags
|= flag
;
7051 S_SET_EXTERNAL (symbolP
);
7052 demand_empty_rest_of_line ();
7062 opt
= input_line_pointer
;
7063 c
= get_symbol_end ();
7067 /* FIXME: What does this mean? */
7069 else if (strncmp (opt
, "pic", 3) == 0)
7077 mips_pic
= SVR4_PIC
;
7079 as_bad (".option pic%d not supported", i
);
7081 if (USE_GLOBAL_POINTER_OPT
&& mips_pic
== SVR4_PIC
)
7083 if (g_switch_seen
&& g_switch_value
!= 0)
7084 as_warn ("-G may not be used with SVR4 PIC code");
7086 bfd_set_gp_size (stdoutput
, 0);
7090 as_warn ("Unrecognized option \"%s\"", opt
);
7092 *input_line_pointer
= c
;
7093 demand_empty_rest_of_line ();
7100 char *name
= input_line_pointer
, ch
;
7102 while (!is_end_of_line
[(unsigned char) *input_line_pointer
])
7103 input_line_pointer
++;
7104 ch
= *input_line_pointer
;
7105 *input_line_pointer
= '\0';
7107 if (strcmp (name
, "reorder") == 0)
7111 prev_insn_unreordered
= 1;
7112 prev_prev_insn_unreordered
= 1;
7116 else if (strcmp (name
, "noreorder") == 0)
7118 mips_emit_delays ();
7120 mips_any_noreorder
= 1;
7122 else if (strcmp (name
, "at") == 0)
7126 else if (strcmp (name
, "noat") == 0)
7130 else if (strcmp (name
, "macro") == 0)
7132 mips_warn_about_macros
= 0;
7134 else if (strcmp (name
, "nomacro") == 0)
7136 if (mips_noreorder
== 0)
7137 as_bad ("`noreorder' must be set before `nomacro'");
7138 mips_warn_about_macros
= 1;
7140 else if (strcmp (name
, "move") == 0 || strcmp (name
, "novolatile") == 0)
7144 else if (strcmp (name
, "nomove") == 0 || strcmp (name
, "volatile") == 0)
7148 else if (strcmp (name
, "bopt") == 0)
7152 else if (strcmp (name
, "nobopt") == 0)
7156 else if (strncmp (name
, "mips", 4) == 0)
7160 /* Permit the user to change the ISA on the fly. Needless to
7161 say, misuse can cause serious problems. */
7162 isa
= atoi (name
+ 4);
7164 mips_isa
= file_mips_isa
;
7165 else if (isa
< 1 || isa
> 4)
7166 as_bad ("unknown ISA level");
7172 as_warn ("Tried to set unrecognized symbol: %s\n", name
);
7174 *input_line_pointer
= ch
;
7175 demand_empty_rest_of_line ();
7178 /* Handle the .abicalls pseudo-op. I believe this is equivalent to
7179 .option pic2. It means to generate SVR4 PIC calls. */
7185 mips_pic
= SVR4_PIC
;
7186 if (USE_GLOBAL_POINTER_OPT
)
7188 if (g_switch_seen
&& g_switch_value
!= 0)
7189 as_warn ("-G may not be used with SVR4 PIC code");
7192 bfd_set_gp_size (stdoutput
, 0);
7193 demand_empty_rest_of_line ();
7196 /* Handle the .cpload pseudo-op. This is used when generating SVR4
7197 PIC code. It sets the $gp register for the function based on the
7198 function address, which is in the register named in the argument.
7199 This uses a relocation against _gp_disp, which is handled specially
7200 by the linker. The result is:
7201 lui $gp,%hi(_gp_disp)
7202 addiu $gp,$gp,%lo(_gp_disp)
7203 addu $gp,$gp,.cpload argument
7204 The .cpload argument is normally $25 == $t9. */
7213 /* If we are not generating SVR4 PIC code, .cpload is ignored. */
7214 if (mips_pic
!= SVR4_PIC
)
7220 /* .cpload should be a in .set noreorder section. */
7221 if (mips_noreorder
== 0)
7222 as_warn (".cpload not in noreorder section");
7225 ex
.X_add_symbol
= symbol_find_or_make ("_gp_disp");
7226 ex
.X_op_symbol
= NULL
;
7227 ex
.X_add_number
= 0;
7229 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
7230 ex
.X_add_symbol
->bsym
->flags
|= BSF_OBJECT
;
7232 macro_build_lui ((char *) NULL
, &icnt
, &ex
, GP
);
7233 macro_build ((char *) NULL
, &icnt
, &ex
, "addiu", "t,r,j", GP
, GP
,
7234 (int) BFD_RELOC_LO16
);
7236 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "addu", "d,v,t",
7237 GP
, GP
, tc_get_register (0));
7239 demand_empty_rest_of_line ();
7242 /* Handle the .cprestore pseudo-op. This stores $gp into a given
7243 offset from $sp. The offset is remembered, and after making a PIC
7244 call $gp is restored from that location. */
7247 s_cprestore (ignore
)
7253 /* If we are not generating SVR4 PIC code, .cprestore is ignored. */
7254 if (mips_pic
!= SVR4_PIC
)
7260 mips_cprestore_offset
= get_absolute_expression ();
7262 ex
.X_op
= O_constant
;
7263 ex
.X_add_symbol
= NULL
;
7264 ex
.X_op_symbol
= NULL
;
7265 ex
.X_add_number
= mips_cprestore_offset
;
7267 macro_build ((char *) NULL
, &icnt
, &ex
,
7268 mips_isa
< 3 ? "sw" : "sd",
7269 "t,o(b)", GP
, (int) BFD_RELOC_LO16
, SP
);
7271 demand_empty_rest_of_line ();
7274 /* Handle the .gpword pseudo-op. This is used when generating PIC
7275 code. It generates a 32 bit GP relative reloc. */
7285 /* When not generating PIC code, this is treated as .word. */
7286 if (mips_pic
!= SVR4_PIC
)
7293 mips_emit_delays ();
7295 mips_align (2, 0, label
);
7300 if (ex
.X_op
!= O_symbol
|| ex
.X_add_number
!= 0)
7302 as_bad ("Unsupported use of .gpword");
7303 ignore_rest_of_line ();
7307 md_number_to_chars (p
, (valueT
) 0, 4);
7308 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 4, &ex
, 0,
7309 BFD_RELOC_MIPS_GPREL32
);
7311 demand_empty_rest_of_line ();
7314 /* Handle the .cpadd pseudo-op. This is used when dealing with switch
7315 tables in SVR4 PIC code. */
7324 /* This is ignored when not generating SVR4 PIC code. */
7325 if (mips_pic
!= SVR4_PIC
)
7331 /* Add $gp to the register named as an argument. */
7332 reg
= tc_get_register (0);
7333 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
7334 mips_isa
< 3 ? "addu" : "daddu",
7335 "d,v,t", reg
, reg
, GP
);
7337 demand_empty_rest_of_line ();
7340 /* Parse a register string into a number. Called from the ECOFF code
7341 to parse .frame. The argument is non-zero if this is the frame
7342 register, so that we can record it in mips_frame_reg. */
7345 tc_get_register (frame
)
7351 if (*input_line_pointer
++ != '$')
7353 as_warn ("expected `$'");
7356 else if (isdigit ((unsigned char) *input_line_pointer
))
7358 reg
= get_absolute_expression ();
7359 if (reg
< 0 || reg
>= 32)
7361 as_warn ("Bad register number");
7367 if (strncmp (input_line_pointer
, "fp", 2) == 0)
7369 else if (strncmp (input_line_pointer
, "sp", 2) == 0)
7371 else if (strncmp (input_line_pointer
, "gp", 2) == 0)
7373 else if (strncmp (input_line_pointer
, "at", 2) == 0)
7377 as_warn ("Unrecognized register name");
7380 input_line_pointer
+= 2;
7383 mips_frame_reg
= reg
!= 0 ? reg
: SP
;
7388 md_section_align (seg
, addr
)
7392 int align
= bfd_get_section_alignment (stdoutput
, seg
);
7394 return ((addr
+ (1 << align
) - 1) & (-1 << align
));
7397 /* Utility routine, called from above as well. If called while the
7398 input file is still being read, it's only an approximation. (For
7399 example, a symbol may later become defined which appeared to be
7400 undefined earlier.) */
7403 nopic_need_relax (sym
)
7409 if (USE_GLOBAL_POINTER_OPT
)
7411 const char *symname
;
7414 /* Find out whether this symbol can be referenced off the GP
7415 register. It can be if it is smaller than the -G size or if
7416 it is in the .sdata or .sbss section. Certain symbols can
7417 not be referenced off the GP, although it appears as though
7419 symname
= S_GET_NAME (sym
);
7420 if (symname
!= (const char *) NULL
7421 && (strcmp (symname
, "eprol") == 0
7422 || strcmp (symname
, "etext") == 0
7423 || strcmp (symname
, "_gp") == 0
7424 || strcmp (symname
, "edata") == 0
7425 || strcmp (symname
, "_fbss") == 0
7426 || strcmp (symname
, "_fdata") == 0
7427 || strcmp (symname
, "_ftext") == 0
7428 || strcmp (symname
, "end") == 0
7429 || strcmp (symname
, "_gp_disp") == 0))
7431 else if (! S_IS_DEFINED (sym
)
7433 #ifndef NO_ECOFF_DEBUGGING
7434 || (sym
->ecoff_extern_size
!= 0
7435 && sym
->ecoff_extern_size
<= g_switch_value
)
7437 || (S_GET_VALUE (sym
) != 0
7438 && S_GET_VALUE (sym
) <= g_switch_value
)))
7442 const char *segname
;
7444 segname
= segment_name (S_GET_SEGMENT (sym
));
7445 assert (strcmp (segname
, ".lit8") != 0
7446 && strcmp (segname
, ".lit4") != 0);
7447 change
= (strcmp (segname
, ".sdata") != 0
7448 && strcmp (segname
, ".sbss") != 0);
7453 /* We are not optimizing for the GP register. */
7457 /* Estimate the size of a frag before relaxing. We are not really
7458 relaxing here, and the final size is encoded in the subtype
7463 md_estimate_size_before_relax (fragp
, segtype
)
7469 if (mips_pic
== NO_PIC
)
7471 change
= nopic_need_relax (fragp
->fr_symbol
);
7473 else if (mips_pic
== SVR4_PIC
)
7475 asection
*symsec
= fragp
->fr_symbol
->bsym
->section
;
7477 /* This must duplicate the test in adjust_reloc_syms. */
7478 change
= (symsec
!= &bfd_und_section
7479 && symsec
!= &bfd_abs_section
7480 && ! bfd_is_com_section (symsec
));
7487 /* Record the offset to the first reloc in the fr_opcode field.
7488 This lets md_convert_frag and tc_gen_reloc know that the code
7489 must be expanded. */
7490 fragp
->fr_opcode
= (fragp
->fr_literal
7492 - RELAX_OLD (fragp
->fr_subtype
)
7493 + RELAX_RELOC1 (fragp
->fr_subtype
));
7494 /* FIXME: This really needs as_warn_where. */
7495 if (RELAX_WARN (fragp
->fr_subtype
))
7496 as_warn ("AT used after \".set noat\" or macro used after \".set nomacro\"");
7502 return RELAX_NEW (fragp
->fr_subtype
) - RELAX_OLD (fragp
->fr_subtype
);
7505 /* Translate internal representation of relocation info to BFD target
7509 tc_gen_reloc (section
, fixp
)
7513 static arelent
*retval
[4];
7516 reloc
= retval
[0] = (arelent
*) xmalloc (sizeof (arelent
));
7519 reloc
->sym_ptr_ptr
= &fixp
->fx_addsy
->bsym
;
7520 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
7522 if (mips_pic
== EMBEDDED_PIC
7523 && SWITCH_TABLE (fixp
))
7525 /* For a switch table entry we use a special reloc. The addend
7526 is actually the difference between the reloc address and the
7528 reloc
->addend
= reloc
->address
- S_GET_VALUE (fixp
->fx_subsy
);
7529 if (OUTPUT_FLAVOR
!= bfd_target_ecoff_flavour
)
7530 as_fatal ("Double check fx_r_type in tc-mips.c:tc_gen_reloc");
7531 fixp
->fx_r_type
= BFD_RELOC_GPREL32
;
7533 else if (fixp
->fx_r_type
== BFD_RELOC_PCREL_LO16
)
7535 /* We use a special addend for an internal RELLO reloc. */
7536 if (fixp
->fx_addsy
->bsym
->flags
& BSF_SECTION_SYM
)
7537 reloc
->addend
= reloc
->address
- S_GET_VALUE (fixp
->fx_subsy
);
7539 reloc
->addend
= fixp
->fx_addnumber
+ reloc
->address
;
7541 else if (fixp
->fx_r_type
== BFD_RELOC_PCREL_HI16_S
)
7543 assert (fixp
->fx_next
!= NULL
7544 && fixp
->fx_next
->fx_r_type
== BFD_RELOC_PCREL_LO16
);
7545 /* We use a special addend for an internal RELHI reloc. The
7546 reloc is relative to the RELLO; adjust the addend
7548 if (fixp
->fx_addsy
->bsym
->flags
& BSF_SECTION_SYM
)
7549 reloc
->addend
= (fixp
->fx_next
->fx_frag
->fr_address
7550 + fixp
->fx_next
->fx_where
7551 - S_GET_VALUE (fixp
->fx_subsy
));
7553 reloc
->addend
= (fixp
->fx_addnumber
7554 + fixp
->fx_next
->fx_frag
->fr_address
7555 + fixp
->fx_next
->fx_where
);
7557 else if (fixp
->fx_pcrel
== 0)
7558 reloc
->addend
= fixp
->fx_addnumber
;
7561 if (OUTPUT_FLAVOR
!= bfd_target_aout_flavour
)
7562 /* A gruesome hack which is a result of the gruesome gas reloc
7564 reloc
->addend
= reloc
->address
;
7566 reloc
->addend
= -reloc
->address
;
7569 /* If this is a variant frag, we may need to adjust the existing
7570 reloc and generate a new one. */
7571 if (fixp
->fx_frag
->fr_opcode
!= NULL
7572 && (fixp
->fx_r_type
== BFD_RELOC_MIPS_GPREL
7573 || fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT16
7574 || fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL16
7575 || fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT_HI16
7576 || fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT_LO16
7577 || fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL_HI16
7578 || fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL_LO16
))
7582 /* If this is not the last reloc in this frag, then we have two
7583 GPREL relocs, or a GOT_HI16/GOT_LO16 pair, or a
7584 CALL_HI16/CALL_LO16, both of which are being replaced. Let
7585 the second one handle all of them. */
7586 if (fixp
->fx_next
!= NULL
7587 && fixp
->fx_frag
== fixp
->fx_next
->fx_frag
)
7589 assert ((fixp
->fx_r_type
== BFD_RELOC_MIPS_GPREL
7590 && fixp
->fx_next
->fx_r_type
== BFD_RELOC_MIPS_GPREL
)
7591 || (fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT_HI16
7592 && (fixp
->fx_next
->fx_r_type
7593 == BFD_RELOC_MIPS_GOT_LO16
))
7594 || (fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL_HI16
7595 && (fixp
->fx_next
->fx_r_type
7596 == BFD_RELOC_MIPS_CALL_LO16
)));
7601 fixp
->fx_where
= fixp
->fx_frag
->fr_opcode
- fixp
->fx_frag
->fr_literal
;
7602 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
7603 reloc2
= retval
[1] = (arelent
*) xmalloc (sizeof (arelent
));
7605 reloc2
->sym_ptr_ptr
= &fixp
->fx_addsy
->bsym
;
7606 reloc2
->address
= (reloc
->address
7607 + (RELAX_RELOC2 (fixp
->fx_frag
->fr_subtype
)
7608 - RELAX_RELOC1 (fixp
->fx_frag
->fr_subtype
)));
7609 reloc2
->addend
= fixp
->fx_addnumber
;
7610 reloc2
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_LO16
);
7611 assert (reloc2
->howto
!= NULL
);
7613 if (RELAX_RELOC3 (fixp
->fx_frag
->fr_subtype
))
7617 reloc3
= retval
[2] = (arelent
*) xmalloc (sizeof (arelent
));
7620 reloc3
->address
+= 4;
7623 if (mips_pic
== NO_PIC
)
7625 assert (fixp
->fx_r_type
== BFD_RELOC_MIPS_GPREL
);
7626 fixp
->fx_r_type
= BFD_RELOC_HI16_S
;
7628 else if (mips_pic
== SVR4_PIC
)
7630 switch (fixp
->fx_r_type
)
7634 case BFD_RELOC_MIPS_GOT16
:
7636 case BFD_RELOC_MIPS_CALL16
:
7637 case BFD_RELOC_MIPS_GOT_LO16
:
7638 case BFD_RELOC_MIPS_CALL_LO16
:
7639 fixp
->fx_r_type
= BFD_RELOC_MIPS_GOT16
;
7647 /* To support a PC relative reloc when generating embedded PIC code
7648 for ECOFF, we use a Cygnus extension. We check for that here to
7649 make sure that we don't let such a reloc escape normally. */
7650 if (OUTPUT_FLAVOR
== bfd_target_ecoff_flavour
7651 && fixp
->fx_r_type
== BFD_RELOC_16_PCREL_S2
7652 && mips_pic
!= EMBEDDED_PIC
)
7653 reloc
->howto
= NULL
;
7655 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, fixp
->fx_r_type
);
7657 if (reloc
->howto
== NULL
)
7659 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
7660 "Can not represent relocation in this object file format");
7667 /* Convert a machine dependent frag. */
7670 md_convert_frag (abfd
, asec
, fragp
)
7678 if (fragp
->fr_opcode
== NULL
)
7681 old
= RELAX_OLD (fragp
->fr_subtype
);
7682 new = RELAX_NEW (fragp
->fr_subtype
);
7683 fixptr
= fragp
->fr_literal
+ fragp
->fr_fix
;
7686 memcpy (fixptr
- old
, fixptr
, new);
7688 fragp
->fr_fix
+= new - old
;
7691 /* This function is called whenever a label is defined. It is used
7692 when handling branch delays; if a branch has a label, we assume we
7696 mips_define_label (sym
)
7702 /* Decide whether a label is local. This is called by LOCAL_LABEL.
7703 In order to work with gcc when using mips-tfile, we must keep all
7704 local labels. However, in other cases, we want to discard them,
7705 since they are useless. */
7708 mips_local_label (name
)
7711 #ifndef NO_ECOFF_DEBUGGING
7714 && ! ecoff_debugging_seen
)
7716 /* We were called with -g, but we didn't see any debugging
7717 information. That may mean that gcc is smuggling debugging
7718 information through to mips-tfile, in which case we must
7719 generate all local labels. */
7724 /* Here it's OK to discard local labels. */
7726 return name
[0] == '$';
7729 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7731 /* Some special processing for a MIPS ELF file. */
7734 mips_elf_final_processing ()
7736 /* Write out the register information. */
7741 s
.ri_gprmask
= mips_gprmask
;
7742 s
.ri_cprmask
[0] = mips_cprmask
[0];
7743 s
.ri_cprmask
[1] = mips_cprmask
[1];
7744 s
.ri_cprmask
[2] = mips_cprmask
[2];
7745 s
.ri_cprmask
[3] = mips_cprmask
[3];
7746 /* The gp_value field is set by the MIPS ELF backend. */
7748 bfd_mips_elf32_swap_reginfo_out (stdoutput
, &s
,
7749 ((Elf32_External_RegInfo
*)
7750 mips_regmask_frag
));
7754 Elf64_Internal_RegInfo s
;
7756 s
.ri_gprmask
= mips_gprmask
;
7758 s
.ri_cprmask
[0] = mips_cprmask
[0];
7759 s
.ri_cprmask
[1] = mips_cprmask
[1];
7760 s
.ri_cprmask
[2] = mips_cprmask
[2];
7761 s
.ri_cprmask
[3] = mips_cprmask
[3];
7762 /* The gp_value field is set by the MIPS ELF backend. */
7764 bfd_mips_elf64_swap_reginfo_out (stdoutput
, &s
,
7765 ((Elf64_External_RegInfo
*)
7766 mips_regmask_frag
));
7769 /* Set the MIPS ELF flag bits. FIXME: There should probably be some
7770 sort of BFD interface for this. */
7771 if (mips_any_noreorder
)
7772 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_NOREORDER
;
7773 if (mips_pic
!= NO_PIC
)
7774 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_PIC
;
7777 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */
7779 /* These functions should really be defined by the object file format,
7780 since they are related to debugging information. However, this
7781 code has to work for the a.out format, which does not define them,
7782 so we provide simple versions here. These don't actually generate
7783 any debugging information, but they do simple checking and someday
7784 somebody may make them useful. */
7788 struct loc
*loc_next
;
7789 unsigned long loc_fileno
;
7790 unsigned long loc_lineno
;
7791 unsigned long loc_offset
;
7792 unsigned short loc_delta
;
7793 unsigned short loc_count
;
7802 struct proc
*proc_next
;
7803 struct symbol
*proc_isym
;
7804 struct symbol
*proc_end
;
7805 unsigned long proc_reg_mask
;
7806 unsigned long proc_reg_offset
;
7807 unsigned long proc_fpreg_mask
;
7808 unsigned long proc_fpreg_offset
;
7809 unsigned long proc_frameoffset
;
7810 unsigned long proc_framereg
;
7811 unsigned long proc_pcreg
;
7813 struct file
*proc_file
;
7820 struct file
*file_next
;
7821 unsigned long file_fileno
;
7822 struct symbol
*file_symbol
;
7823 struct symbol
*file_end
;
7824 struct proc
*file_proc
;
7829 static struct obstack proc_frags
;
7830 static procS
*proc_lastP
;
7831 static procS
*proc_rootP
;
7832 static int numprocs
;
7837 obstack_begin (&proc_frags
, 0x2000);
7843 /* check for premature end, nesting errors, etc */
7844 if (proc_lastP
&& proc_lastP
->proc_end
== NULL
)
7845 as_warn ("missing `.end' at end of assembly");
7854 if (*input_line_pointer
== '-')
7856 ++input_line_pointer
;
7859 if (!isdigit (*input_line_pointer
))
7860 as_bad ("Expected simple number.");
7861 if (input_line_pointer
[0] == '0')
7863 if (input_line_pointer
[1] == 'x')
7865 input_line_pointer
+= 2;
7866 while (isxdigit (*input_line_pointer
))
7869 val
|= hex_value (*input_line_pointer
++);
7871 return negative
? -val
: val
;
7875 ++input_line_pointer
;
7876 while (isdigit (*input_line_pointer
))
7879 val
|= *input_line_pointer
++ - '0';
7881 return negative
? -val
: val
;
7884 if (!isdigit (*input_line_pointer
))
7886 printf (" *input_line_pointer == '%c' 0x%02x\n",
7887 *input_line_pointer
, *input_line_pointer
);
7888 as_warn ("Invalid number");
7891 while (isdigit (*input_line_pointer
))
7894 val
+= *input_line_pointer
++ - '0';
7896 return negative
? -val
: val
;
7899 /* The .file directive; just like the usual .file directive, but there
7900 is an initial number which is the ECOFF file index. */
7908 line
= get_number ();
7913 /* The .end directive. */
7921 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
7924 demand_empty_rest_of_line ();
7928 if (now_seg
!= text_section
)
7929 as_warn (".end not in text section");
7932 as_warn (".end and no .ent seen yet.");
7938 assert (S_GET_NAME (p
));
7939 if (strcmp (S_GET_NAME (p
), S_GET_NAME (proc_lastP
->proc_isym
)))
7940 as_warn (".end symbol does not match .ent symbol.");
7943 proc_lastP
->proc_end
= (symbolS
*) 1;
7946 /* The .aent and .ent directives. */
7956 symbolP
= get_symbol ();
7957 if (*input_line_pointer
== ',')
7958 input_line_pointer
++;
7960 if (isdigit (*input_line_pointer
) || *input_line_pointer
== '-')
7961 number
= get_number ();
7962 if (now_seg
!= text_section
)
7963 as_warn (".ent or .aent not in text section.");
7965 if (!aent
&& proc_lastP
&& proc_lastP
->proc_end
== NULL
)
7966 as_warn ("missing `.end'");
7970 procP
= (procS
*) obstack_alloc (&proc_frags
, sizeof (*procP
));
7971 procP
->proc_isym
= symbolP
;
7972 procP
->proc_reg_mask
= 0;
7973 procP
->proc_reg_offset
= 0;
7974 procP
->proc_fpreg_mask
= 0;
7975 procP
->proc_fpreg_offset
= 0;
7976 procP
->proc_frameoffset
= 0;
7977 procP
->proc_framereg
= 0;
7978 procP
->proc_pcreg
= 0;
7979 procP
->proc_end
= NULL
;
7980 procP
->proc_next
= NULL
;
7982 proc_lastP
->proc_next
= procP
;
7988 demand_empty_rest_of_line ();
7991 /* The .frame directive. */
8004 frame_reg
= tc_get_register (1);
8005 if (*input_line_pointer
== ',')
8006 input_line_pointer
++;
8007 frame_off
= get_absolute_expression ();
8008 if (*input_line_pointer
== ',')
8009 input_line_pointer
++;
8010 pcreg
= tc_get_register (0);
8013 assert (proc_rootP
);
8014 proc_rootP
->proc_framereg
= frame_reg
;
8015 proc_rootP
->proc_frameoffset
= frame_off
;
8016 proc_rootP
->proc_pcreg
= pcreg
;
8017 /* bob macho .frame */
8019 /* We don't have to write out a frame stab for unoptimized code. */
8020 if (!(frame_reg
== FP
&& frame_off
== 0))
8023 as_warn ("No .ent for .frame to use.");
8024 (void) sprintf (str
, "R%d;%d", frame_reg
, frame_off
);
8025 symP
= symbol_new (str
, N_VFP
, 0, frag_now
);
8026 S_SET_TYPE (symP
, N_RMASK
);
8027 S_SET_OTHER (symP
, 0);
8028 S_SET_DESC (symP
, 0);
8029 symP
->sy_forward
= proc_lastP
->proc_isym
;
8030 /* bob perhaps I should have used pseudo set */
8032 demand_empty_rest_of_line ();
8036 /* The .fmask and .mask directives. */
8043 char str
[100], *strP
;
8049 mask
= get_number ();
8050 if (*input_line_pointer
== ',')
8051 input_line_pointer
++;
8052 off
= get_absolute_expression ();
8054 /* bob only for coff */
8055 assert (proc_rootP
);
8056 if (reg_type
== 'F')
8058 proc_rootP
->proc_fpreg_mask
= mask
;
8059 proc_rootP
->proc_fpreg_offset
= off
;
8063 proc_rootP
->proc_reg_mask
= mask
;
8064 proc_rootP
->proc_reg_offset
= off
;
8067 /* bob macho .mask + .fmask */
8069 /* We don't have to write out a mask stab if no saved regs. */
8073 as_warn ("No .ent for .mask to use.");
8075 for (i
= 0; i
< 32; i
++)
8079 sprintf (strP
, "%c%d,", reg_type
, i
);
8080 strP
+= strlen (strP
);
8084 sprintf (strP
, ";%d,", off
);
8085 symP
= symbol_new (str
, N_RMASK
, 0, frag_now
);
8086 S_SET_TYPE (symP
, N_RMASK
);
8087 S_SET_OTHER (symP
, 0);
8088 S_SET_DESC (symP
, 0);
8089 symP
->sy_forward
= proc_lastP
->proc_isym
;
8090 /* bob perhaps I should have used pseudo set */
8095 /* The .loc directive. */
8106 assert (now_seg
== text_section
);
8108 lineno
= get_number ();
8109 addroff
= frag_now_fix ();
8111 symbolP
= symbol_new ("", N_SLINE
, addroff
, frag_now
);
8112 S_SET_TYPE (symbolP
, N_SLINE
);
8113 S_SET_OTHER (symbolP
, 0);
8114 S_SET_DESC (symbolP
, lineno
);
8115 symbolP
->sy_segment
= now_seg
;