1 /* tc-mips.c -- assemble code for a MIPS chip.
2 Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002
3 Free Software Foundation, Inc.
4 Contributed by the OSF and Ralph Campbell.
5 Written by Keith Knowles and Ralph Campbell, working independently.
6 Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus
9 This file is part of GAS.
11 GAS is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 2, or (at your option)
16 GAS is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
21 You should have received a copy of the GNU General Public License
22 along with GAS; see the file COPYING. If not, write to the Free
23 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
29 #include "safe-ctype.h"
38 #include "opcode/mips.h"
40 #include "dwarf2dbg.h"
43 #define DBG(x) printf x
49 /* Clean up namespace so we can include obj-elf.h too. */
50 static int mips_output_flavor
PARAMS ((void));
51 static int mips_output_flavor () { return OUTPUT_FLAVOR
; }
52 #undef OBJ_PROCESS_STAB
59 #undef obj_frob_file_after_relocs
60 #undef obj_frob_symbol
62 #undef obj_sec_sym_ok_for_reloc
63 #undef OBJ_COPY_SYMBOL_ATTRIBUTES
66 /* Fix any of them that we actually care about. */
68 #define OUTPUT_FLAVOR mips_output_flavor()
75 #ifndef ECOFF_DEBUGGING
76 #define NO_ECOFF_DEBUGGING
77 #define ECOFF_DEBUGGING 0
80 int mips_flag_mdebug
= -1;
84 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
85 static char *mips_regmask_frag
;
91 #define PIC_CALL_REG 25
99 #define ILLEGAL_REG (32)
101 /* Allow override of standard little-endian ECOFF format. */
103 #ifndef ECOFF_LITTLE_FORMAT
104 #define ECOFF_LITTLE_FORMAT "ecoff-littlemips"
107 extern int target_big_endian
;
109 /* The name of the readonly data section. */
110 #define RDATA_SECTION_NAME (OUTPUT_FLAVOR == bfd_target_aout_flavour \
112 : OUTPUT_FLAVOR == bfd_target_ecoff_flavour \
114 : OUTPUT_FLAVOR == bfd_target_coff_flavour \
116 : OUTPUT_FLAVOR == bfd_target_elf_flavour \
120 /* The ABI to use. */
131 /* MIPS ABI we are using for this output file. */
132 static enum mips_abi_level mips_abi
= NO_ABI
;
134 /* This is the set of options which may be modified by the .set
135 pseudo-op. We use a struct so that .set push and .set pop are more
138 struct mips_set_options
140 /* MIPS ISA (Instruction Set Architecture) level. This is set to -1
141 if it has not been initialized. Changed by `.set mipsN', and the
142 -mipsN command line option, and the default CPU. */
144 /* Enabled Application Specific Extensions (ASEs). These are set to -1
145 if they have not been initialized. Changed by `.set <asename>', by
146 command line options, and based on the default architecture. */
149 /* Whether we are assembling for the mips16 processor. 0 if we are
150 not, 1 if we are, and -1 if the value has not been initialized.
151 Changed by `.set mips16' and `.set nomips16', and the -mips16 and
152 -nomips16 command line options, and the default CPU. */
154 /* Non-zero if we should not reorder instructions. Changed by `.set
155 reorder' and `.set noreorder'. */
157 /* Non-zero if we should not permit the $at ($1) register to be used
158 in instructions. Changed by `.set at' and `.set noat'. */
160 /* Non-zero if we should warn when a macro instruction expands into
161 more than one machine instruction. Changed by `.set nomacro' and
163 int warn_about_macros
;
164 /* Non-zero if we should not move instructions. Changed by `.set
165 move', `.set volatile', `.set nomove', and `.set novolatile'. */
167 /* Non-zero if we should not optimize branches by moving the target
168 of the branch into the delay slot. Actually, we don't perform
169 this optimization anyhow. Changed by `.set bopt' and `.set
172 /* Non-zero if we should not autoextend mips16 instructions.
173 Changed by `.set autoextend' and `.set noautoextend'. */
175 /* Restrict general purpose registers and floating point registers
176 to 32 bit. This is initially determined when -mgp32 or -mfp32
177 is passed but can changed if the assembler code uses .set mipsN. */
182 /* True if -mgp32 was passed. */
183 static int file_mips_gp32
= -1;
185 /* True if -mfp32 was passed. */
186 static int file_mips_fp32
= -1;
188 /* This is the struct we use to hold the current set of options. Note
189 that we must set the isa field to ISA_UNKNOWN and the ASE fields to
190 -1 to indicate that they have not been initialized. */
192 static struct mips_set_options mips_opts
=
194 ISA_UNKNOWN
, -1, -1, -1, 0, 0, 0, 0, 0, 0, 0, 0
197 /* These variables are filled in with the masks of registers used.
198 The object format code reads them and puts them in the appropriate
200 unsigned long mips_gprmask
;
201 unsigned long mips_cprmask
[4];
203 /* MIPS ISA we are using for this output file. */
204 static int file_mips_isa
= ISA_UNKNOWN
;
206 /* True if -mips16 was passed or implied by arguments passed on the
207 command line (e.g., by -march). */
208 static int file_ase_mips16
;
210 /* True if -mips3d was passed or implied by arguments passed on the
211 command line (e.g., by -march). */
212 static int file_ase_mips3d
;
214 /* True if -mdmx was passed or implied by arguments passed on the
215 command line (e.g., by -march). */
216 static int file_ase_mdmx
;
218 /* The argument of the -march= flag. The architecture we are assembling. */
219 static int mips_arch
= CPU_UNKNOWN
;
220 static const char *mips_arch_string
;
221 static const struct mips_cpu_info
*mips_arch_info
;
223 /* The argument of the -mtune= flag. The architecture for which we
225 static int mips_tune
= CPU_UNKNOWN
;
226 static const char *mips_tune_string
;
227 static const struct mips_cpu_info
*mips_tune_info
;
229 /* True when generating 32-bit code for a 64-bit processor. */
230 static int mips_32bitmode
= 0;
232 /* Some ISA's have delay slots for instructions which read or write
233 from a coprocessor (eg. mips1-mips3); some don't (eg mips4).
234 Return true if instructions marked INSN_LOAD_COPROC_DELAY,
235 INSN_COPROC_MOVE_DELAY, or INSN_WRITE_COND_CODE actually have a
236 delay slot in this ISA. The uses of this macro assume that any
237 ISA that has delay slots for one of these, has them for all. They
238 also assume that ISAs which don't have delays for these insns, don't
239 have delays for the INSN_LOAD_MEMORY_DELAY instructions either. */
240 #define ISA_HAS_COPROC_DELAYS(ISA) ( \
242 || (ISA) == ISA_MIPS2 \
243 || (ISA) == ISA_MIPS3 \
246 /* True if the given ABI requires 32-bit registers. */
247 #define ABI_NEEDS_32BIT_REGS(ABI) ((ABI) == O32_ABI)
249 /* Likewise 64-bit registers. */
250 #define ABI_NEEDS_64BIT_REGS(ABI) \
252 || (ABI) == N64_ABI \
255 /* Return true if ISA supports 64 bit gp register instructions. */
256 #define ISA_HAS_64BIT_REGS(ISA) ( \
258 || (ISA) == ISA_MIPS4 \
259 || (ISA) == ISA_MIPS5 \
260 || (ISA) == ISA_MIPS64 \
263 #define HAVE_32BIT_GPRS \
264 (mips_opts.gp32 || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
266 #define HAVE_32BIT_FPRS \
267 (mips_opts.fp32 || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
269 #define HAVE_64BIT_GPRS (! HAVE_32BIT_GPRS)
270 #define HAVE_64BIT_FPRS (! HAVE_32BIT_FPRS)
272 #define HAVE_NEWABI (mips_abi == N32_ABI || mips_abi == N64_ABI)
274 #define HAVE_64BIT_OBJECTS (mips_abi == N64_ABI)
276 /* We can only have 64bit addresses if the object file format
278 #define HAVE_32BIT_ADDRESSES \
280 || ((bfd_arch_bits_per_address (stdoutput) == 32 \
281 || ! HAVE_64BIT_OBJECTS) \
282 && mips_pic != EMBEDDED_PIC))
284 #define HAVE_64BIT_ADDRESSES (! HAVE_32BIT_ADDRESSES)
286 /* Return true if the given CPU supports the MIPS16 ASE. */
287 #define CPU_HAS_MIPS16(cpu) \
288 (strncmp (TARGET_CPU, "mips16", sizeof ("mips16") - 1) == 0 \
289 || strncmp (TARGET_CANONICAL, "mips-lsi-elf", sizeof ("mips-lsi-elf") - 1) == 0)
291 /* Return true if the given CPU supports the MIPS3D ASE. */
292 #define CPU_HAS_MIPS3D(cpu) ((cpu) == CPU_SB1 \
295 /* Return true if the given CPU supports the MDMX ASE. */
296 #define CPU_HAS_MDMX(cpu) (false \
299 /* True if CPU has a dror instruction. */
300 #define CPU_HAS_DROR(CPU) ((CPU) == CPU_VR5400 || (CPU) == CPU_VR5500)
302 /* True if CPU has a ror instruction. */
303 #define CPU_HAS_ROR(CPU) CPU_HAS_DROR (CPU)
305 /* Whether the processor uses hardware interlocks to protect
306 reads from the HI and LO registers, and thus does not
307 require nops to be inserted. */
309 #define hilo_interlocks (mips_arch == CPU_R4010 \
310 || mips_arch == CPU_VR5500 \
311 || mips_arch == CPU_SB1 \
314 /* Whether the processor uses hardware interlocks to protect reads
315 from the GPRs, and thus does not require nops to be inserted. */
316 #define gpr_interlocks \
317 (mips_opts.isa != ISA_MIPS1 \
318 || mips_arch == CPU_VR5400 \
319 || mips_arch == CPU_VR5500 \
320 || mips_arch == CPU_R3900)
322 /* As with other "interlocks" this is used by hardware that has FP
323 (co-processor) interlocks. */
324 /* Itbl support may require additional care here. */
325 #define cop_interlocks (mips_arch == CPU_R4300 \
326 || mips_arch == CPU_VR5400 \
327 || mips_arch == CPU_VR5500 \
328 || mips_arch == CPU_SB1 \
331 /* Is this a mfhi or mflo instruction? */
332 #define MF_HILO_INSN(PINFO) \
333 ((PINFO & INSN_READ_HI) || (PINFO & INSN_READ_LO))
335 /* MIPS PIC level. */
337 enum mips_pic_level mips_pic
;
339 /* Warn about all NOPS that the assembler generates. */
340 static int warn_nops
= 0;
342 /* 1 if we should generate 32 bit offsets from the $gp register in
343 SVR4_PIC mode. Currently has no meaning in other modes. */
344 static int mips_big_got
= 0;
346 /* 1 if trap instructions should used for overflow rather than break
348 static int mips_trap
= 0;
350 /* 1 if double width floating point constants should not be constructed
351 by assembling two single width halves into two single width floating
352 point registers which just happen to alias the double width destination
353 register. On some architectures this aliasing can be disabled by a bit
354 in the status register, and the setting of this bit cannot be determined
355 automatically at assemble time. */
356 static int mips_disable_float_construction
;
358 /* Non-zero if any .set noreorder directives were used. */
360 static int mips_any_noreorder
;
362 /* Non-zero if nops should be inserted when the register referenced in
363 an mfhi/mflo instruction is read in the next two instructions. */
364 static int mips_7000_hilo_fix
;
366 /* The size of the small data section. */
367 static unsigned int g_switch_value
= 8;
368 /* Whether the -G option was used. */
369 static int g_switch_seen
= 0;
374 /* If we can determine in advance that GP optimization won't be
375 possible, we can skip the relaxation stuff that tries to produce
376 GP-relative references. This makes delay slot optimization work
379 This function can only provide a guess, but it seems to work for
380 gcc output. It needs to guess right for gcc, otherwise gcc
381 will put what it thinks is a GP-relative instruction in a branch
384 I don't know if a fix is needed for the SVR4_PIC mode. I've only
385 fixed it for the non-PIC mode. KR 95/04/07 */
386 static int nopic_need_relax
PARAMS ((symbolS
*, int));
388 /* handle of the OPCODE hash table */
389 static struct hash_control
*op_hash
= NULL
;
391 /* The opcode hash table we use for the mips16. */
392 static struct hash_control
*mips16_op_hash
= NULL
;
394 /* This array holds the chars that always start a comment. If the
395 pre-processor is disabled, these aren't very useful */
396 const char comment_chars
[] = "#";
398 /* This array holds the chars that only start a comment at the beginning of
399 a line. If the line seems to have the form '# 123 filename'
400 .line and .file directives will appear in the pre-processed output */
401 /* Note that input_file.c hand checks for '#' at the beginning of the
402 first line of the input file. This is because the compiler outputs
403 #NO_APP at the beginning of its output. */
404 /* Also note that C style comments are always supported. */
405 const char line_comment_chars
[] = "#";
407 /* This array holds machine specific line separator characters. */
408 const char line_separator_chars
[] = ";";
410 /* Chars that can be used to separate mant from exp in floating point nums */
411 const char EXP_CHARS
[] = "eE";
413 /* Chars that mean this number is a floating point constant */
416 const char FLT_CHARS
[] = "rRsSfFdDxXpP";
418 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
419 changed in read.c . Ideally it shouldn't have to know about it at all,
420 but nothing is ideal around here.
423 static char *insn_error
;
425 static int auto_align
= 1;
427 /* When outputting SVR4 PIC code, the assembler needs to know the
428 offset in the stack frame from which to restore the $gp register.
429 This is set by the .cprestore pseudo-op, and saved in this
431 static offsetT mips_cprestore_offset
= -1;
433 /* Similiar for NewABI PIC code, where $gp is callee-saved. NewABI has some
434 more optimizations, it can use a register value instead of a memory-saved
435 offset and even an other register than $gp as global pointer. */
436 static offsetT mips_cpreturn_offset
= -1;
437 static int mips_cpreturn_register
= -1;
438 static int mips_gp_register
= GP
;
439 static int mips_gprel_offset
= 0;
441 /* Whether mips_cprestore_offset has been set in the current function
442 (or whether it has already been warned about, if not). */
443 static int mips_cprestore_valid
= 0;
445 /* This is the register which holds the stack frame, as set by the
446 .frame pseudo-op. This is needed to implement .cprestore. */
447 static int mips_frame_reg
= SP
;
449 /* Whether mips_frame_reg has been set in the current function
450 (or whether it has already been warned about, if not). */
451 static int mips_frame_reg_valid
= 0;
453 /* To output NOP instructions correctly, we need to keep information
454 about the previous two instructions. */
456 /* Whether we are optimizing. The default value of 2 means to remove
457 unneeded NOPs and swap branch instructions when possible. A value
458 of 1 means to not swap branches. A value of 0 means to always
460 static int mips_optimize
= 2;
462 /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is
463 equivalent to seeing no -g option at all. */
464 static int mips_debug
= 0;
466 /* The previous instruction. */
467 static struct mips_cl_insn prev_insn
;
469 /* The instruction before prev_insn. */
470 static struct mips_cl_insn prev_prev_insn
;
472 /* If we don't want information for prev_insn or prev_prev_insn, we
473 point the insn_mo field at this dummy integer. */
474 static const struct mips_opcode dummy_opcode
= { NULL
, NULL
, 0, 0, 0, 0 };
476 /* Non-zero if prev_insn is valid. */
477 static int prev_insn_valid
;
479 /* The frag for the previous instruction. */
480 static struct frag
*prev_insn_frag
;
482 /* The offset into prev_insn_frag for the previous instruction. */
483 static long prev_insn_where
;
485 /* The reloc type for the previous instruction, if any. */
486 static bfd_reloc_code_real_type prev_insn_reloc_type
[3];
488 /* The reloc for the previous instruction, if any. */
489 static fixS
*prev_insn_fixp
[3];
491 /* Non-zero if the previous instruction was in a delay slot. */
492 static int prev_insn_is_delay_slot
;
494 /* Non-zero if the previous instruction was in a .set noreorder. */
495 static int prev_insn_unreordered
;
497 /* Non-zero if the previous instruction uses an extend opcode (if
499 static int prev_insn_extended
;
501 /* Non-zero if the previous previous instruction was in a .set
503 static int prev_prev_insn_unreordered
;
505 /* If this is set, it points to a frag holding nop instructions which
506 were inserted before the start of a noreorder section. If those
507 nops turn out to be unnecessary, the size of the frag can be
509 static fragS
*prev_nop_frag
;
511 /* The number of nop instructions we created in prev_nop_frag. */
512 static int prev_nop_frag_holds
;
514 /* The number of nop instructions that we know we need in
516 static int prev_nop_frag_required
;
518 /* The number of instructions we've seen since prev_nop_frag. */
519 static int prev_nop_frag_since
;
521 /* For ECOFF and ELF, relocations against symbols are done in two
522 parts, with a HI relocation and a LO relocation. Each relocation
523 has only 16 bits of space to store an addend. This means that in
524 order for the linker to handle carries correctly, it must be able
525 to locate both the HI and the LO relocation. This means that the
526 relocations must appear in order in the relocation table.
528 In order to implement this, we keep track of each unmatched HI
529 relocation. We then sort them so that they immediately precede the
530 corresponding LO relocation. */
535 struct mips_hi_fixup
*next
;
538 /* The section this fixup is in. */
542 /* The list of unmatched HI relocs. */
544 static struct mips_hi_fixup
*mips_hi_fixup_list
;
546 /* Map normal MIPS register numbers to mips16 register numbers. */
548 #define X ILLEGAL_REG
549 static const int mips32_to_16_reg_map
[] =
551 X
, X
, 2, 3, 4, 5, 6, 7,
552 X
, X
, X
, X
, X
, X
, X
, X
,
553 0, 1, X
, X
, X
, X
, X
, X
,
554 X
, X
, X
, X
, X
, X
, X
, X
558 /* Map mips16 register numbers to normal MIPS register numbers. */
560 static const unsigned int mips16_to_32_reg_map
[] =
562 16, 17, 2, 3, 4, 5, 6, 7
565 static int mips_fix_4122_bugs
;
567 /* Since the MIPS does not have multiple forms of PC relative
568 instructions, we do not have to do relaxing as is done on other
569 platforms. However, we do have to handle GP relative addressing
570 correctly, which turns out to be a similar problem.
572 Every macro that refers to a symbol can occur in (at least) two
573 forms, one with GP relative addressing and one without. For
574 example, loading a global variable into a register generally uses
575 a macro instruction like this:
577 If i can be addressed off the GP register (this is true if it is in
578 the .sbss or .sdata section, or if it is known to be smaller than
579 the -G argument) this will generate the following instruction:
581 This instruction will use a GPREL reloc. If i can not be addressed
582 off the GP register, the following instruction sequence will be used:
585 In this case the first instruction will have a HI16 reloc, and the
586 second reloc will have a LO16 reloc. Both relocs will be against
589 The issue here is that we may not know whether i is GP addressable
590 until after we see the instruction that uses it. Therefore, we
591 want to be able to choose the final instruction sequence only at
592 the end of the assembly. This is similar to the way other
593 platforms choose the size of a PC relative instruction only at the
596 When generating position independent code we do not use GP
597 addressing in quite the same way, but the issue still arises as
598 external symbols and local symbols must be handled differently.
600 We handle these issues by actually generating both possible
601 instruction sequences. The longer one is put in a frag_var with
602 type rs_machine_dependent. We encode what to do with the frag in
603 the subtype field. We encode (1) the number of existing bytes to
604 replace, (2) the number of new bytes to use, (3) the offset from
605 the start of the existing bytes to the first reloc we must generate
606 (that is, the offset is applied from the start of the existing
607 bytes after they are replaced by the new bytes, if any), (4) the
608 offset from the start of the existing bytes to the second reloc,
609 (5) whether a third reloc is needed (the third reloc is always four
610 bytes after the second reloc), and (6) whether to warn if this
611 variant is used (this is sometimes needed if .set nomacro or .set
612 noat is in effect). All these numbers are reasonably small.
614 Generating two instruction sequences must be handled carefully to
615 ensure that delay slots are handled correctly. Fortunately, there
616 are a limited number of cases. When the second instruction
617 sequence is generated, append_insn is directed to maintain the
618 existing delay slot information, so it continues to apply to any
619 code after the second instruction sequence. This means that the
620 second instruction sequence must not impose any requirements not
621 required by the first instruction sequence.
623 These variant frags are then handled in functions called by the
624 machine independent code. md_estimate_size_before_relax returns
625 the final size of the frag. md_convert_frag sets up the final form
626 of the frag. tc_gen_reloc adjust the first reloc and adds a second
628 #define RELAX_ENCODE(old, new, reloc1, reloc2, reloc3, warn) \
632 | (((reloc1) + 64) << 9) \
633 | (((reloc2) + 64) << 2) \
634 | ((reloc3) ? (1 << 1) : 0) \
636 #define RELAX_OLD(i) (((i) >> 23) & 0x7f)
637 #define RELAX_NEW(i) (((i) >> 16) & 0x7f)
638 #define RELAX_RELOC1(i) ((valueT) (((i) >> 9) & 0x7f) - 64)
639 #define RELAX_RELOC2(i) ((valueT) (((i) >> 2) & 0x7f) - 64)
640 #define RELAX_RELOC3(i) (((i) >> 1) & 1)
641 #define RELAX_WARN(i) ((i) & 1)
643 /* For mips16 code, we use an entirely different form of relaxation.
644 mips16 supports two versions of most instructions which take
645 immediate values: a small one which takes some small value, and a
646 larger one which takes a 16 bit value. Since branches also follow
647 this pattern, relaxing these values is required.
649 We can assemble both mips16 and normal MIPS code in a single
650 object. Therefore, we need to support this type of relaxation at
651 the same time that we support the relaxation described above. We
652 use the high bit of the subtype field to distinguish these cases.
654 The information we store for this type of relaxation is the
655 argument code found in the opcode file for this relocation, whether
656 the user explicitly requested a small or extended form, and whether
657 the relocation is in a jump or jal delay slot. That tells us the
658 size of the value, and how it should be stored. We also store
659 whether the fragment is considered to be extended or not. We also
660 store whether this is known to be a branch to a different section,
661 whether we have tried to relax this frag yet, and whether we have
662 ever extended a PC relative fragment because of a shift count. */
663 #define RELAX_MIPS16_ENCODE(type, small, ext, dslot, jal_dslot) \
666 | ((small) ? 0x100 : 0) \
667 | ((ext) ? 0x200 : 0) \
668 | ((dslot) ? 0x400 : 0) \
669 | ((jal_dslot) ? 0x800 : 0))
670 #define RELAX_MIPS16_P(i) (((i) & 0x80000000) != 0)
671 #define RELAX_MIPS16_TYPE(i) ((i) & 0xff)
672 #define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x100) != 0)
673 #define RELAX_MIPS16_USER_EXT(i) (((i) & 0x200) != 0)
674 #define RELAX_MIPS16_DSLOT(i) (((i) & 0x400) != 0)
675 #define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x800) != 0)
676 #define RELAX_MIPS16_EXTENDED(i) (((i) & 0x1000) != 0)
677 #define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x1000)
678 #define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) &~ 0x1000)
679 #define RELAX_MIPS16_LONG_BRANCH(i) (((i) & 0x2000) != 0)
680 #define RELAX_MIPS16_MARK_LONG_BRANCH(i) ((i) | 0x2000)
681 #define RELAX_MIPS16_CLEAR_LONG_BRANCH(i) ((i) &~ 0x2000)
683 /* Is the given value a sign-extended 32-bit value? */
684 #define IS_SEXT_32BIT_NUM(x) \
685 (((x) &~ (offsetT) 0x7fffffff) == 0 \
686 || (((x) &~ (offsetT) 0x7fffffff) == ~ (offsetT) 0x7fffffff))
688 /* Is the given value a sign-extended 16-bit value? */
689 #define IS_SEXT_16BIT_NUM(x) \
690 (((x) &~ (offsetT) 0x7fff) == 0 \
691 || (((x) &~ (offsetT) 0x7fff) == ~ (offsetT) 0x7fff))
694 /* Prototypes for static functions. */
697 #define internalError() \
698 as_fatal (_("internal Error, line %d, %s"), __LINE__, __FILE__)
700 #define internalError() as_fatal (_("MIPS internal Error"));
703 enum mips_regclass
{ MIPS_GR_REG
, MIPS_FP_REG
, MIPS16_REG
};
705 static int insn_uses_reg
PARAMS ((struct mips_cl_insn
*ip
,
706 unsigned int reg
, enum mips_regclass
class));
707 static int reg_needs_delay
PARAMS ((unsigned int));
708 static void mips16_mark_labels
PARAMS ((void));
709 static void append_insn
PARAMS ((char *place
,
710 struct mips_cl_insn
* ip
,
712 bfd_reloc_code_real_type
*r
,
714 static void mips_no_prev_insn
PARAMS ((int));
715 static void mips_emit_delays
PARAMS ((boolean
));
717 static void macro_build
PARAMS ((char *place
, int *counter
, expressionS
* ep
,
718 const char *name
, const char *fmt
,
721 static void macro_build ();
723 static void mips16_macro_build
PARAMS ((char *, int *, expressionS
*,
724 const char *, const char *,
726 static void macro_build_jalr
PARAMS ((int, expressionS
*));
727 static void macro_build_lui
PARAMS ((char *place
, int *counter
,
728 expressionS
* ep
, int regnum
));
729 static void macro_build_ldst_constoffset
PARAMS ((char *place
, int *counter
,
730 expressionS
* ep
, const char *op
,
731 int valreg
, int breg
));
732 static void set_at
PARAMS ((int *counter
, int reg
, int unsignedp
));
733 static void check_absolute_expr
PARAMS ((struct mips_cl_insn
* ip
,
735 static void load_register
PARAMS ((int *, int, expressionS
*, int));
736 static void load_address
PARAMS ((int *, int, expressionS
*, int *));
737 static void move_register
PARAMS ((int *, int, int));
738 static void macro
PARAMS ((struct mips_cl_insn
* ip
));
739 static void mips16_macro
PARAMS ((struct mips_cl_insn
* ip
));
740 #ifdef LOSING_COMPILER
741 static void macro2
PARAMS ((struct mips_cl_insn
* ip
));
743 static void mips_ip
PARAMS ((char *str
, struct mips_cl_insn
* ip
));
744 static void mips16_ip
PARAMS ((char *str
, struct mips_cl_insn
* ip
));
745 static void mips16_immed
PARAMS ((char *, unsigned int, int, offsetT
, boolean
,
746 boolean
, boolean
, unsigned long *,
747 boolean
*, unsigned short *));
748 static int my_getPercentOp
PARAMS ((char **, unsigned int *, int *));
749 static int my_getSmallParser
PARAMS ((char **, unsigned int *, int *));
750 static int my_getSmallExpression
PARAMS ((expressionS
*, char *));
751 static void my_getExpression
PARAMS ((expressionS
*, char *));
753 static int support_64bit_objects
PARAMS((void));
755 static void mips_set_option_string
PARAMS ((const char **, const char *));
756 static symbolS
*get_symbol
PARAMS ((void));
757 static void mips_align
PARAMS ((int to
, int fill
, symbolS
*label
));
758 static void s_align
PARAMS ((int));
759 static void s_change_sec
PARAMS ((int));
760 static void s_change_section
PARAMS ((int));
761 static void s_cons
PARAMS ((int));
762 static void s_float_cons
PARAMS ((int));
763 static void s_mips_globl
PARAMS ((int));
764 static void s_option
PARAMS ((int));
765 static void s_mipsset
PARAMS ((int));
766 static void s_abicalls
PARAMS ((int));
767 static void s_cpload
PARAMS ((int));
768 static void s_cpsetup
PARAMS ((int));
769 static void s_cplocal
PARAMS ((int));
770 static void s_cprestore
PARAMS ((int));
771 static void s_cpreturn
PARAMS ((int));
772 static void s_gpvalue
PARAMS ((int));
773 static void s_gpword
PARAMS ((int));
774 static void s_cpadd
PARAMS ((int));
775 static void s_insn
PARAMS ((int));
776 static void md_obj_begin
PARAMS ((void));
777 static void md_obj_end
PARAMS ((void));
778 static long get_number
PARAMS ((void));
779 static void s_mips_ent
PARAMS ((int));
780 static void s_mips_end
PARAMS ((int));
781 static void s_mips_frame
PARAMS ((int));
782 static void s_mips_mask
PARAMS ((int));
783 static void s_mips_stab
PARAMS ((int));
784 static void s_mips_weakext
PARAMS ((int));
785 static void s_mips_file
PARAMS ((int));
786 static void s_mips_loc
PARAMS ((int));
787 static int mips16_extended_frag
PARAMS ((fragS
*, asection
*, long));
788 static int validate_mips_insn
PARAMS ((const struct mips_opcode
*));
789 static void show
PARAMS ((FILE *, const char *, int *, int *));
791 static int mips_need_elf_addend_fixup
PARAMS ((fixS
*));
794 /* Return values of my_getSmallExpression(). */
801 /* Direct relocation creation by %percent_op(). */
820 /* Table and functions used to map between CPU/ISA names, and
821 ISA levels, and CPU numbers. */
825 const char *name
; /* CPU or ISA name. */
826 int is_isa
; /* Is this an ISA? (If 0, a CPU.) */
827 int isa
; /* ISA level. */
828 int cpu
; /* CPU number (default CPU if ISA). */
831 static void mips_set_architecture
PARAMS ((const struct mips_cpu_info
*));
832 static void mips_set_tune
PARAMS ((const struct mips_cpu_info
*));
833 static boolean mips_strict_matching_cpu_name_p
PARAMS ((const char *,
835 static boolean mips_matching_cpu_name_p
PARAMS ((const char *, const char *));
836 static const struct mips_cpu_info
*mips_parse_cpu
PARAMS ((const char *,
838 static const struct mips_cpu_info
*mips_cpu_info_from_isa
PARAMS ((int));
842 The following pseudo-ops from the Kane and Heinrich MIPS book
843 should be defined here, but are currently unsupported: .alias,
844 .galive, .gjaldef, .gjrlive, .livereg, .noalias.
846 The following pseudo-ops from the Kane and Heinrich MIPS book are
847 specific to the type of debugging information being generated, and
848 should be defined by the object format: .aent, .begin, .bend,
849 .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp,
852 The following pseudo-ops from the Kane and Heinrich MIPS book are
853 not MIPS CPU specific, but are also not specific to the object file
854 format. This file is probably the best place to define them, but
855 they are not currently supported: .asm0, .endr, .lab, .repeat,
858 static const pseudo_typeS mips_pseudo_table
[] =
860 /* MIPS specific pseudo-ops. */
861 {"option", s_option
, 0},
862 {"set", s_mipsset
, 0},
863 {"rdata", s_change_sec
, 'r'},
864 {"sdata", s_change_sec
, 's'},
865 {"livereg", s_ignore
, 0},
866 {"abicalls", s_abicalls
, 0},
867 {"cpload", s_cpload
, 0},
868 {"cpsetup", s_cpsetup
, 0},
869 {"cplocal", s_cplocal
, 0},
870 {"cprestore", s_cprestore
, 0},
871 {"cpreturn", s_cpreturn
, 0},
872 {"gpvalue", s_gpvalue
, 0},
873 {"gpword", s_gpword
, 0},
874 {"cpadd", s_cpadd
, 0},
877 /* Relatively generic pseudo-ops that happen to be used on MIPS
879 {"asciiz", stringer
, 1},
880 {"bss", s_change_sec
, 'b'},
883 {"dword", s_cons
, 3},
884 {"weakext", s_mips_weakext
, 0},
886 /* These pseudo-ops are defined in read.c, but must be overridden
887 here for one reason or another. */
888 {"align", s_align
, 0},
890 {"data", s_change_sec
, 'd'},
891 {"double", s_float_cons
, 'd'},
892 {"float", s_float_cons
, 'f'},
893 {"globl", s_mips_globl
, 0},
894 {"global", s_mips_globl
, 0},
895 {"hword", s_cons
, 1},
900 {"section", s_change_section
, 0},
901 {"short", s_cons
, 1},
902 {"single", s_float_cons
, 'f'},
903 {"stabn", s_mips_stab
, 'n'},
904 {"text", s_change_sec
, 't'},
907 { "extern", ecoff_directive_extern
, 0},
912 static const pseudo_typeS mips_nonecoff_pseudo_table
[] =
914 /* These pseudo-ops should be defined by the object file format.
915 However, a.out doesn't support them, so we have versions here. */
916 {"aent", s_mips_ent
, 1},
917 {"bgnb", s_ignore
, 0},
918 {"end", s_mips_end
, 0},
919 {"endb", s_ignore
, 0},
920 {"ent", s_mips_ent
, 0},
921 {"file", s_mips_file
, 0},
922 {"fmask", s_mips_mask
, 'F'},
923 {"frame", s_mips_frame
, 0},
924 {"loc", s_mips_loc
, 0},
925 {"mask", s_mips_mask
, 'R'},
926 {"verstamp", s_ignore
, 0},
930 extern void pop_insert
PARAMS ((const pseudo_typeS
*));
935 pop_insert (mips_pseudo_table
);
936 if (! ECOFF_DEBUGGING
)
937 pop_insert (mips_nonecoff_pseudo_table
);
940 /* Symbols labelling the current insn. */
942 struct insn_label_list
944 struct insn_label_list
*next
;
948 static struct insn_label_list
*insn_labels
;
949 static struct insn_label_list
*free_insn_labels
;
951 static void mips_clear_insn_labels
PARAMS ((void));
954 mips_clear_insn_labels ()
956 register struct insn_label_list
**pl
;
958 for (pl
= &free_insn_labels
; *pl
!= NULL
; pl
= &(*pl
)->next
)
964 static char *expr_end
;
966 /* Expressions which appear in instructions. These are set by
969 static expressionS imm_expr
;
970 static expressionS offset_expr
;
972 /* Relocs associated with imm_expr and offset_expr. */
974 static bfd_reloc_code_real_type imm_reloc
[3]
975 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
976 static bfd_reloc_code_real_type offset_reloc
[3]
977 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
979 /* This is set by mips_ip if imm_reloc is an unmatched HI16_S reloc. */
981 static boolean imm_unmatched_hi
;
983 /* These are set by mips16_ip if an explicit extension is used. */
985 static boolean mips16_small
, mips16_ext
;
988 /* The pdr segment for per procedure frame/regmask info. Not used for
994 /* The default target format to use. */
997 mips_target_format ()
999 switch (OUTPUT_FLAVOR
)
1001 case bfd_target_aout_flavour
:
1002 return target_big_endian
? "a.out-mips-big" : "a.out-mips-little";
1003 case bfd_target_ecoff_flavour
:
1004 return target_big_endian
? "ecoff-bigmips" : ECOFF_LITTLE_FORMAT
;
1005 case bfd_target_coff_flavour
:
1007 case bfd_target_elf_flavour
:
1009 /* This is traditional mips. */
1010 return (target_big_endian
1011 ? (HAVE_64BIT_OBJECTS
1012 ? "elf64-tradbigmips"
1014 ? "elf32-ntradbigmips" : "elf32-tradbigmips"))
1015 : (HAVE_64BIT_OBJECTS
1016 ? "elf64-tradlittlemips"
1018 ? "elf32-ntradlittlemips" : "elf32-tradlittlemips")));
1020 return (target_big_endian
1021 ? (HAVE_64BIT_OBJECTS
1024 ? "elf32-nbigmips" : "elf32-bigmips"))
1025 : (HAVE_64BIT_OBJECTS
1026 ? "elf64-littlemips"
1028 ? "elf32-nlittlemips" : "elf32-littlemips")));
1036 /* This function is called once, at assembler startup time. It should
1037 set up all the tables, etc. that the MD part of the assembler will need. */
1042 register const char *retval
= NULL
;
1046 if (! bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, mips_arch
))
1047 as_warn (_("Could not set architecture and machine"));
1049 op_hash
= hash_new ();
1051 for (i
= 0; i
< NUMOPCODES
;)
1053 const char *name
= mips_opcodes
[i
].name
;
1055 retval
= hash_insert (op_hash
, name
, (PTR
) &mips_opcodes
[i
]);
1058 fprintf (stderr
, _("internal error: can't hash `%s': %s\n"),
1059 mips_opcodes
[i
].name
, retval
);
1060 /* Probably a memory allocation problem? Give up now. */
1061 as_fatal (_("Broken assembler. No assembly attempted."));
1065 if (mips_opcodes
[i
].pinfo
!= INSN_MACRO
)
1067 if (!validate_mips_insn (&mips_opcodes
[i
]))
1072 while ((i
< NUMOPCODES
) && !strcmp (mips_opcodes
[i
].name
, name
));
1075 mips16_op_hash
= hash_new ();
1078 while (i
< bfd_mips16_num_opcodes
)
1080 const char *name
= mips16_opcodes
[i
].name
;
1082 retval
= hash_insert (mips16_op_hash
, name
, (PTR
) &mips16_opcodes
[i
]);
1084 as_fatal (_("internal: can't hash `%s': %s"),
1085 mips16_opcodes
[i
].name
, retval
);
1088 if (mips16_opcodes
[i
].pinfo
!= INSN_MACRO
1089 && ((mips16_opcodes
[i
].match
& mips16_opcodes
[i
].mask
)
1090 != mips16_opcodes
[i
].match
))
1092 fprintf (stderr
, _("internal error: bad mips16 opcode: %s %s\n"),
1093 mips16_opcodes
[i
].name
, mips16_opcodes
[i
].args
);
1098 while (i
< bfd_mips16_num_opcodes
1099 && strcmp (mips16_opcodes
[i
].name
, name
) == 0);
1103 as_fatal (_("Broken assembler. No assembly attempted."));
1105 /* We add all the general register names to the symbol table. This
1106 helps us detect invalid uses of them. */
1107 for (i
= 0; i
< 32; i
++)
1111 sprintf (buf
, "$%d", i
);
1112 symbol_table_insert (symbol_new (buf
, reg_section
, i
,
1113 &zero_address_frag
));
1115 symbol_table_insert (symbol_new ("$ra", reg_section
, RA
,
1116 &zero_address_frag
));
1117 symbol_table_insert (symbol_new ("$fp", reg_section
, FP
,
1118 &zero_address_frag
));
1119 symbol_table_insert (symbol_new ("$sp", reg_section
, SP
,
1120 &zero_address_frag
));
1121 symbol_table_insert (symbol_new ("$gp", reg_section
, GP
,
1122 &zero_address_frag
));
1123 symbol_table_insert (symbol_new ("$at", reg_section
, AT
,
1124 &zero_address_frag
));
1125 symbol_table_insert (symbol_new ("$kt0", reg_section
, KT0
,
1126 &zero_address_frag
));
1127 symbol_table_insert (symbol_new ("$kt1", reg_section
, KT1
,
1128 &zero_address_frag
));
1129 symbol_table_insert (symbol_new ("$zero", reg_section
, ZERO
,
1130 &zero_address_frag
));
1131 symbol_table_insert (symbol_new ("$pc", reg_section
, -1,
1132 &zero_address_frag
));
1134 mips_no_prev_insn (false);
1137 mips_cprmask
[0] = 0;
1138 mips_cprmask
[1] = 0;
1139 mips_cprmask
[2] = 0;
1140 mips_cprmask
[3] = 0;
1142 /* set the default alignment for the text section (2**2) */
1143 record_alignment (text_section
, 2);
1145 if (USE_GLOBAL_POINTER_OPT
)
1146 bfd_set_gp_size (stdoutput
, g_switch_value
);
1148 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
1150 /* On a native system, sections must be aligned to 16 byte
1151 boundaries. When configured for an embedded ELF target, we
1153 if (strcmp (TARGET_OS
, "elf") != 0)
1155 (void) bfd_set_section_alignment (stdoutput
, text_section
, 4);
1156 (void) bfd_set_section_alignment (stdoutput
, data_section
, 4);
1157 (void) bfd_set_section_alignment (stdoutput
, bss_section
, 4);
1160 /* Create a .reginfo section for register masks and a .mdebug
1161 section for debugging information. */
1169 subseg
= now_subseg
;
1171 /* The ABI says this section should be loaded so that the
1172 running program can access it. However, we don't load it
1173 if we are configured for an embedded target */
1174 flags
= SEC_READONLY
| SEC_DATA
;
1175 if (strcmp (TARGET_OS
, "elf") != 0)
1176 flags
|= SEC_ALLOC
| SEC_LOAD
;
1178 if (mips_abi
!= N64_ABI
)
1180 sec
= subseg_new (".reginfo", (subsegT
) 0);
1182 bfd_set_section_flags (stdoutput
, sec
, flags
);
1183 bfd_set_section_alignment (stdoutput
, sec
, HAVE_NEWABI
? 3 : 2);
1186 mips_regmask_frag
= frag_more (sizeof (Elf32_External_RegInfo
));
1191 /* The 64-bit ABI uses a .MIPS.options section rather than
1192 .reginfo section. */
1193 sec
= subseg_new (".MIPS.options", (subsegT
) 0);
1194 bfd_set_section_flags (stdoutput
, sec
, flags
);
1195 bfd_set_section_alignment (stdoutput
, sec
, 3);
1198 /* Set up the option header. */
1200 Elf_Internal_Options opthdr
;
1203 opthdr
.kind
= ODK_REGINFO
;
1204 opthdr
.size
= (sizeof (Elf_External_Options
)
1205 + sizeof (Elf64_External_RegInfo
));
1208 f
= frag_more (sizeof (Elf_External_Options
));
1209 bfd_mips_elf_swap_options_out (stdoutput
, &opthdr
,
1210 (Elf_External_Options
*) f
);
1212 mips_regmask_frag
= frag_more (sizeof (Elf64_External_RegInfo
));
1217 if (ECOFF_DEBUGGING
)
1219 sec
= subseg_new (".mdebug", (subsegT
) 0);
1220 (void) bfd_set_section_flags (stdoutput
, sec
,
1221 SEC_HAS_CONTENTS
| SEC_READONLY
);
1222 (void) bfd_set_section_alignment (stdoutput
, sec
, 2);
1225 else if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
1227 pdr_seg
= subseg_new (".pdr", (subsegT
) 0);
1228 (void) bfd_set_section_flags (stdoutput
, pdr_seg
,
1229 SEC_READONLY
| SEC_RELOC
1231 (void) bfd_set_section_alignment (stdoutput
, pdr_seg
, 2);
1235 subseg_set (seg
, subseg
);
1239 if (! ECOFF_DEBUGGING
)
1246 if (! ECOFF_DEBUGGING
)
1254 struct mips_cl_insn insn
;
1255 bfd_reloc_code_real_type unused_reloc
[3]
1256 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
1258 imm_expr
.X_op
= O_absent
;
1259 imm_unmatched_hi
= false;
1260 offset_expr
.X_op
= O_absent
;
1261 imm_reloc
[0] = BFD_RELOC_UNUSED
;
1262 imm_reloc
[1] = BFD_RELOC_UNUSED
;
1263 imm_reloc
[2] = BFD_RELOC_UNUSED
;
1264 offset_reloc
[0] = BFD_RELOC_UNUSED
;
1265 offset_reloc
[1] = BFD_RELOC_UNUSED
;
1266 offset_reloc
[2] = BFD_RELOC_UNUSED
;
1268 if (mips_opts
.mips16
)
1269 mips16_ip (str
, &insn
);
1272 mips_ip (str
, &insn
);
1273 DBG ((_("returned from mips_ip(%s) insn_opcode = 0x%x\n"),
1274 str
, insn
.insn_opcode
));
1279 as_bad ("%s `%s'", insn_error
, str
);
1283 if (insn
.insn_mo
->pinfo
== INSN_MACRO
)
1285 if (mips_opts
.mips16
)
1286 mips16_macro (&insn
);
1292 if (imm_expr
.X_op
!= O_absent
)
1293 append_insn (NULL
, &insn
, &imm_expr
, imm_reloc
, imm_unmatched_hi
);
1294 else if (offset_expr
.X_op
!= O_absent
)
1295 append_insn (NULL
, &insn
, &offset_expr
, offset_reloc
, false);
1297 append_insn (NULL
, &insn
, NULL
, unused_reloc
, false);
1301 /* See whether instruction IP reads register REG. CLASS is the type
1305 insn_uses_reg (ip
, reg
, class)
1306 struct mips_cl_insn
*ip
;
1308 enum mips_regclass
class;
1310 if (class == MIPS16_REG
)
1312 assert (mips_opts
.mips16
);
1313 reg
= mips16_to_32_reg_map
[reg
];
1314 class = MIPS_GR_REG
;
1317 /* Don't report on general register ZERO, since it never changes. */
1318 if (class == MIPS_GR_REG
&& reg
== ZERO
)
1321 if (class == MIPS_FP_REG
)
1323 assert (! mips_opts
.mips16
);
1324 /* If we are called with either $f0 or $f1, we must check $f0.
1325 This is not optimal, because it will introduce an unnecessary
1326 NOP between "lwc1 $f0" and "swc1 $f1". To fix this we would
1327 need to distinguish reading both $f0 and $f1 or just one of
1328 them. Note that we don't have to check the other way,
1329 because there is no instruction that sets both $f0 and $f1
1330 and requires a delay. */
1331 if ((ip
->insn_mo
->pinfo
& INSN_READ_FPR_S
)
1332 && ((((ip
->insn_opcode
>> OP_SH_FS
) & OP_MASK_FS
) &~(unsigned)1)
1333 == (reg
&~ (unsigned) 1)))
1335 if ((ip
->insn_mo
->pinfo
& INSN_READ_FPR_T
)
1336 && ((((ip
->insn_opcode
>> OP_SH_FT
) & OP_MASK_FT
) &~(unsigned)1)
1337 == (reg
&~ (unsigned) 1)))
1340 else if (! mips_opts
.mips16
)
1342 if ((ip
->insn_mo
->pinfo
& INSN_READ_GPR_S
)
1343 && ((ip
->insn_opcode
>> OP_SH_RS
) & OP_MASK_RS
) == reg
)
1345 if ((ip
->insn_mo
->pinfo
& INSN_READ_GPR_T
)
1346 && ((ip
->insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
) == reg
)
1351 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_X
)
1352 && (mips16_to_32_reg_map
[((ip
->insn_opcode
>> MIPS16OP_SH_RX
)
1353 & MIPS16OP_MASK_RX
)]
1356 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_Y
)
1357 && (mips16_to_32_reg_map
[((ip
->insn_opcode
>> MIPS16OP_SH_RY
)
1358 & MIPS16OP_MASK_RY
)]
1361 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_Z
)
1362 && (mips16_to_32_reg_map
[((ip
->insn_opcode
>> MIPS16OP_SH_MOVE32Z
)
1363 & MIPS16OP_MASK_MOVE32Z
)]
1366 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_T
) && reg
== TREG
)
1368 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_SP
) && reg
== SP
)
1370 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_31
) && reg
== RA
)
1372 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_GPR_X
)
1373 && ((ip
->insn_opcode
>> MIPS16OP_SH_REGR32
)
1374 & MIPS16OP_MASK_REGR32
) == reg
)
1381 /* This function returns true if modifying a register requires a
1385 reg_needs_delay (reg
)
1388 unsigned long prev_pinfo
;
1390 prev_pinfo
= prev_insn
.insn_mo
->pinfo
;
1391 if (! mips_opts
.noreorder
1392 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
1393 && ((prev_pinfo
& INSN_LOAD_COPROC_DELAY
)
1394 || (! gpr_interlocks
1395 && (prev_pinfo
& INSN_LOAD_MEMORY_DELAY
))))
1397 /* A load from a coprocessor or from memory. All load
1398 delays delay the use of general register rt for one
1399 instruction on the r3000. The r6000 and r4000 use
1401 /* Itbl support may require additional care here. */
1402 know (prev_pinfo
& INSN_WRITE_GPR_T
);
1403 if (reg
== ((prev_insn
.insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
))
1410 /* Mark instruction labels in mips16 mode. This permits the linker to
1411 handle them specially, such as generating jalx instructions when
1412 needed. We also make them odd for the duration of the assembly, in
1413 order to generate the right sort of code. We will make them even
1414 in the adjust_symtab routine, while leaving them marked. This is
1415 convenient for the debugger and the disassembler. The linker knows
1416 to make them odd again. */
1419 mips16_mark_labels ()
1421 if (mips_opts
.mips16
)
1423 struct insn_label_list
*l
;
1426 for (l
= insn_labels
; l
!= NULL
; l
= l
->next
)
1429 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
1430 S_SET_OTHER (l
->label
, STO_MIPS16
);
1432 val
= S_GET_VALUE (l
->label
);
1434 S_SET_VALUE (l
->label
, val
+ 1);
1439 /* Output an instruction. PLACE is where to put the instruction; if
1440 it is NULL, this uses frag_more to get room. IP is the instruction
1441 information. ADDRESS_EXPR is an operand of the instruction to be
1442 used with RELOC_TYPE. */
1445 append_insn (place
, ip
, address_expr
, reloc_type
, unmatched_hi
)
1447 struct mips_cl_insn
*ip
;
1448 expressionS
*address_expr
;
1449 bfd_reloc_code_real_type
*reloc_type
;
1450 boolean unmatched_hi
;
1452 register unsigned long prev_pinfo
, pinfo
;
1457 /* Mark instruction labels in mips16 mode. */
1458 mips16_mark_labels ();
1460 prev_pinfo
= prev_insn
.insn_mo
->pinfo
;
1461 pinfo
= ip
->insn_mo
->pinfo
;
1463 if (place
== NULL
&& (! mips_opts
.noreorder
|| prev_nop_frag
!= NULL
))
1467 /* If the previous insn required any delay slots, see if we need
1468 to insert a NOP or two. There are eight kinds of possible
1469 hazards, of which an instruction can have at most one type.
1470 (1) a load from memory delay
1471 (2) a load from a coprocessor delay
1472 (3) an unconditional branch delay
1473 (4) a conditional branch delay
1474 (5) a move to coprocessor register delay
1475 (6) a load coprocessor register from memory delay
1476 (7) a coprocessor condition code delay
1477 (8) a HI/LO special register delay
1479 There are a lot of optimizations we could do that we don't.
1480 In particular, we do not, in general, reorder instructions.
1481 If you use gcc with optimization, it will reorder
1482 instructions and generally do much more optimization then we
1483 do here; repeating all that work in the assembler would only
1484 benefit hand written assembly code, and does not seem worth
1487 /* This is how a NOP is emitted. */
1488 #define emit_nop() \
1490 ? md_number_to_chars (frag_more (2), 0x6500, 2) \
1491 : md_number_to_chars (frag_more (4), 0, 4))
1493 /* The previous insn might require a delay slot, depending upon
1494 the contents of the current insn. */
1495 if (! mips_opts
.mips16
1496 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
1497 && (((prev_pinfo
& INSN_LOAD_COPROC_DELAY
)
1498 && ! cop_interlocks
)
1499 || (! gpr_interlocks
1500 && (prev_pinfo
& INSN_LOAD_MEMORY_DELAY
))))
1502 /* A load from a coprocessor or from memory. All load
1503 delays delay the use of general register rt for one
1504 instruction on the r3000. The r6000 and r4000 use
1506 /* Itbl support may require additional care here. */
1507 know (prev_pinfo
& INSN_WRITE_GPR_T
);
1508 if (mips_optimize
== 0
1509 || insn_uses_reg (ip
,
1510 ((prev_insn
.insn_opcode
>> OP_SH_RT
)
1515 else if (! mips_opts
.mips16
1516 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
1517 && (((prev_pinfo
& INSN_COPROC_MOVE_DELAY
)
1518 && ! cop_interlocks
)
1519 || (mips_opts
.isa
== ISA_MIPS1
1520 && (prev_pinfo
& INSN_COPROC_MEMORY_DELAY
))))
1522 /* A generic coprocessor delay. The previous instruction
1523 modified a coprocessor general or control register. If
1524 it modified a control register, we need to avoid any
1525 coprocessor instruction (this is probably not always
1526 required, but it sometimes is). If it modified a general
1527 register, we avoid using that register.
1529 On the r6000 and r4000 loading a coprocessor register
1530 from memory is interlocked, and does not require a delay.
1532 This case is not handled very well. There is no special
1533 knowledge of CP0 handling, and the coprocessors other
1534 than the floating point unit are not distinguished at
1536 /* Itbl support may require additional care here. FIXME!
1537 Need to modify this to include knowledge about
1538 user specified delays! */
1539 if (prev_pinfo
& INSN_WRITE_FPR_T
)
1541 if (mips_optimize
== 0
1542 || insn_uses_reg (ip
,
1543 ((prev_insn
.insn_opcode
>> OP_SH_FT
)
1548 else if (prev_pinfo
& INSN_WRITE_FPR_S
)
1550 if (mips_optimize
== 0
1551 || insn_uses_reg (ip
,
1552 ((prev_insn
.insn_opcode
>> OP_SH_FS
)
1559 /* We don't know exactly what the previous instruction
1560 does. If the current instruction uses a coprocessor
1561 register, we must insert a NOP. If previous
1562 instruction may set the condition codes, and the
1563 current instruction uses them, we must insert two
1565 /* Itbl support may require additional care here. */
1566 if (mips_optimize
== 0
1567 || ((prev_pinfo
& INSN_WRITE_COND_CODE
)
1568 && (pinfo
& INSN_READ_COND_CODE
)))
1570 else if (pinfo
& INSN_COP
)
1574 else if (! mips_opts
.mips16
1575 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
1576 && (prev_pinfo
& INSN_WRITE_COND_CODE
)
1577 && ! cop_interlocks
)
1579 /* The previous instruction sets the coprocessor condition
1580 codes, but does not require a general coprocessor delay
1581 (this means it is a floating point comparison
1582 instruction). If this instruction uses the condition
1583 codes, we need to insert a single NOP. */
1584 /* Itbl support may require additional care here. */
1585 if (mips_optimize
== 0
1586 || (pinfo
& INSN_READ_COND_CODE
))
1590 /* If we're fixing up mfhi/mflo for the r7000 and the
1591 previous insn was an mfhi/mflo and the current insn
1592 reads the register that the mfhi/mflo wrote to, then
1595 else if (mips_7000_hilo_fix
1596 && MF_HILO_INSN (prev_pinfo
)
1597 && insn_uses_reg (ip
, ((prev_insn
.insn_opcode
>> OP_SH_RD
)
1604 /* If we're fixing up mfhi/mflo for the r7000 and the
1605 2nd previous insn was an mfhi/mflo and the current insn
1606 reads the register that the mfhi/mflo wrote to, then
1609 else if (mips_7000_hilo_fix
1610 && MF_HILO_INSN (prev_prev_insn
.insn_opcode
)
1611 && insn_uses_reg (ip
, ((prev_prev_insn
.insn_opcode
>> OP_SH_RD
)
1619 else if (prev_pinfo
& INSN_READ_LO
)
1621 /* The previous instruction reads the LO register; if the
1622 current instruction writes to the LO register, we must
1623 insert two NOPS. Some newer processors have interlocks.
1624 Also the tx39's multiply instructions can be exectuted
1625 immediatly after a read from HI/LO (without the delay),
1626 though the tx39's divide insns still do require the
1628 if (! (hilo_interlocks
1629 || (mips_tune
== CPU_R3900
&& (pinfo
& INSN_MULT
)))
1630 && (mips_optimize
== 0
1631 || (pinfo
& INSN_WRITE_LO
)))
1633 /* Most mips16 branch insns don't have a delay slot.
1634 If a read from LO is immediately followed by a branch
1635 to a write to LO we have a read followed by a write
1636 less than 2 insns away. We assume the target of
1637 a branch might be a write to LO, and insert a nop
1638 between a read and an immediately following branch. */
1639 else if (mips_opts
.mips16
1640 && (mips_optimize
== 0
1641 || (pinfo
& MIPS16_INSN_BRANCH
)))
1644 else if (prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
1646 /* The previous instruction reads the HI register; if the
1647 current instruction writes to the HI register, we must
1648 insert a NOP. Some newer processors have interlocks.
1649 Also the note tx39's multiply above. */
1650 if (! (hilo_interlocks
1651 || (mips_tune
== CPU_R3900
&& (pinfo
& INSN_MULT
)))
1652 && (mips_optimize
== 0
1653 || (pinfo
& INSN_WRITE_HI
)))
1655 /* Most mips16 branch insns don't have a delay slot.
1656 If a read from HI is immediately followed by a branch
1657 to a write to HI we have a read followed by a write
1658 less than 2 insns away. We assume the target of
1659 a branch might be a write to HI, and insert a nop
1660 between a read and an immediately following branch. */
1661 else if (mips_opts
.mips16
1662 && (mips_optimize
== 0
1663 || (pinfo
& MIPS16_INSN_BRANCH
)))
1667 /* If the previous instruction was in a noreorder section, then
1668 we don't want to insert the nop after all. */
1669 /* Itbl support may require additional care here. */
1670 if (prev_insn_unreordered
)
1673 /* There are two cases which require two intervening
1674 instructions: 1) setting the condition codes using a move to
1675 coprocessor instruction which requires a general coprocessor
1676 delay and then reading the condition codes 2) reading the HI
1677 or LO register and then writing to it (except on processors
1678 which have interlocks). If we are not already emitting a NOP
1679 instruction, we must check for these cases compared to the
1680 instruction previous to the previous instruction. */
1681 if ((! mips_opts
.mips16
1682 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
1683 && (prev_prev_insn
.insn_mo
->pinfo
& INSN_COPROC_MOVE_DELAY
)
1684 && (prev_prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
)
1685 && (pinfo
& INSN_READ_COND_CODE
)
1686 && ! cop_interlocks
)
1687 || ((prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
)
1688 && (pinfo
& INSN_WRITE_LO
)
1689 && ! (hilo_interlocks
1690 || (mips_tune
== CPU_R3900
&& (pinfo
& INSN_MULT
))))
1691 || ((prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
1692 && (pinfo
& INSN_WRITE_HI
)
1693 && ! (hilo_interlocks
1694 || (mips_tune
== CPU_R3900
&& (pinfo
& INSN_MULT
)))))
1699 if (prev_prev_insn_unreordered
)
1702 if (prev_prev_nop
&& nops
== 0)
1705 if (mips_fix_4122_bugs
&& prev_insn
.insn_mo
->name
)
1707 /* We're out of bits in pinfo, so we must resort to string
1708 ops here. Shortcuts are selected based on opcodes being
1709 limited to the VR4122 instruction set. */
1711 const char *pn
= prev_insn
.insn_mo
->name
;
1712 const char *tn
= ip
->insn_mo
->name
;
1713 if (strncmp(pn
, "macc", 4) == 0
1714 || strncmp(pn
, "dmacc", 5) == 0)
1716 /* Errata 21 - [D]DIV[U] after [D]MACC */
1717 if (strstr (tn
, "div"))
1722 /* Errata 23 - Continuous DMULT[U]/DMACC instructions */
1723 if (pn
[0] == 'd' /* dmacc */
1724 && (strncmp(tn
, "dmult", 5) == 0
1725 || strncmp(tn
, "dmacc", 5) == 0))
1730 /* Errata 24 - MT{LO,HI} after [D]MACC */
1731 if (strcmp (tn
, "mtlo") == 0
1732 || strcmp (tn
, "mthi") == 0)
1738 else if (strncmp(pn
, "dmult", 5) == 0
1739 && (strncmp(tn
, "dmult", 5) == 0
1740 || strncmp(tn
, "dmacc", 5) == 0))
1742 /* Here is the rest of errata 23. */
1745 if (nops
< min_nops
)
1749 /* If we are being given a nop instruction, don't bother with
1750 one of the nops we would otherwise output. This will only
1751 happen when a nop instruction is used with mips_optimize set
1754 && ! mips_opts
.noreorder
1755 && ip
->insn_opcode
== (unsigned) (mips_opts
.mips16
? 0x6500 : 0))
1758 /* Now emit the right number of NOP instructions. */
1759 if (nops
> 0 && ! mips_opts
.noreorder
)
1762 unsigned long old_frag_offset
;
1764 struct insn_label_list
*l
;
1766 old_frag
= frag_now
;
1767 old_frag_offset
= frag_now_fix ();
1769 for (i
= 0; i
< nops
; i
++)
1774 listing_prev_line ();
1775 /* We may be at the start of a variant frag. In case we
1776 are, make sure there is enough space for the frag
1777 after the frags created by listing_prev_line. The
1778 argument to frag_grow here must be at least as large
1779 as the argument to all other calls to frag_grow in
1780 this file. We don't have to worry about being in the
1781 middle of a variant frag, because the variants insert
1782 all needed nop instructions themselves. */
1786 for (l
= insn_labels
; l
!= NULL
; l
= l
->next
)
1790 assert (S_GET_SEGMENT (l
->label
) == now_seg
);
1791 symbol_set_frag (l
->label
, frag_now
);
1792 val
= (valueT
) frag_now_fix ();
1793 /* mips16 text labels are stored as odd. */
1794 if (mips_opts
.mips16
)
1796 S_SET_VALUE (l
->label
, val
);
1799 #ifndef NO_ECOFF_DEBUGGING
1800 if (ECOFF_DEBUGGING
)
1801 ecoff_fix_loc (old_frag
, old_frag_offset
);
1804 else if (prev_nop_frag
!= NULL
)
1806 /* We have a frag holding nops we may be able to remove. If
1807 we don't need any nops, we can decrease the size of
1808 prev_nop_frag by the size of one instruction. If we do
1809 need some nops, we count them in prev_nops_required. */
1810 if (prev_nop_frag_since
== 0)
1814 prev_nop_frag
->fr_fix
-= mips_opts
.mips16
? 2 : 4;
1815 --prev_nop_frag_holds
;
1818 prev_nop_frag_required
+= nops
;
1822 if (prev_prev_nop
== 0)
1824 prev_nop_frag
->fr_fix
-= mips_opts
.mips16
? 2 : 4;
1825 --prev_nop_frag_holds
;
1828 ++prev_nop_frag_required
;
1831 if (prev_nop_frag_holds
<= prev_nop_frag_required
)
1832 prev_nop_frag
= NULL
;
1834 ++prev_nop_frag_since
;
1836 /* Sanity check: by the time we reach the second instruction
1837 after prev_nop_frag, we should have used up all the nops
1838 one way or another. */
1839 assert (prev_nop_frag_since
<= 1 || prev_nop_frag
== NULL
);
1843 if (*reloc_type
> BFD_RELOC_UNUSED
)
1845 /* We need to set up a variant frag. */
1846 assert (mips_opts
.mips16
&& address_expr
!= NULL
);
1847 f
= frag_var (rs_machine_dependent
, 4, 0,
1848 RELAX_MIPS16_ENCODE (*reloc_type
- BFD_RELOC_UNUSED
,
1849 mips16_small
, mips16_ext
,
1851 & INSN_UNCOND_BRANCH_DELAY
),
1852 (*prev_insn_reloc_type
1853 == BFD_RELOC_MIPS16_JMP
)),
1854 make_expr_symbol (address_expr
), 0, NULL
);
1856 else if (place
!= NULL
)
1858 else if (mips_opts
.mips16
1860 && *reloc_type
!= BFD_RELOC_MIPS16_JMP
)
1862 /* Make sure there is enough room to swap this instruction with
1863 a following jump instruction. */
1869 if (mips_opts
.mips16
1870 && mips_opts
.noreorder
1871 && (prev_pinfo
& INSN_UNCOND_BRANCH_DELAY
) != 0)
1872 as_warn (_("extended instruction in delay slot"));
1877 fixp
[0] = fixp
[1] = fixp
[2] = NULL
;
1878 if (address_expr
!= NULL
&& *reloc_type
< BFD_RELOC_UNUSED
)
1880 if (address_expr
->X_op
== O_constant
)
1884 switch (*reloc_type
)
1887 ip
->insn_opcode
|= address_expr
->X_add_number
;
1890 case BFD_RELOC_MIPS_HIGHEST
:
1891 tmp
= (address_expr
->X_add_number
+ 0x800080008000) >> 16;
1893 ip
->insn_opcode
|= (tmp
>> 16) & 0xffff;
1896 case BFD_RELOC_MIPS_HIGHER
:
1897 tmp
= (address_expr
->X_add_number
+ 0x80008000) >> 16;
1898 ip
->insn_opcode
|= (tmp
>> 16) & 0xffff;
1901 case BFD_RELOC_HI16_S
:
1902 ip
->insn_opcode
|= ((address_expr
->X_add_number
+ 0x8000)
1906 case BFD_RELOC_HI16
:
1907 ip
->insn_opcode
|= (address_expr
->X_add_number
>> 16) & 0xffff;
1910 case BFD_RELOC_LO16
:
1911 case BFD_RELOC_MIPS_GOT_DISP
:
1912 ip
->insn_opcode
|= address_expr
->X_add_number
& 0xffff;
1915 case BFD_RELOC_MIPS_JMP
:
1916 if ((address_expr
->X_add_number
& 3) != 0)
1917 as_bad (_("jump to misaligned address (0x%lx)"),
1918 (unsigned long) address_expr
->X_add_number
);
1919 if (address_expr
->X_add_number
& ~0xfffffff)
1920 as_bad (_("jump address range overflow (0x%lx)"),
1921 (unsigned long) address_expr
->X_add_number
);
1922 ip
->insn_opcode
|= (address_expr
->X_add_number
>> 2) & 0x3ffffff;
1925 case BFD_RELOC_MIPS16_JMP
:
1926 if ((address_expr
->X_add_number
& 3) != 0)
1927 as_bad (_("jump to misaligned address (0x%lx)"),
1928 (unsigned long) address_expr
->X_add_number
);
1929 if (address_expr
->X_add_number
& ~0xfffffff)
1930 as_bad (_("jump address range overflow (0x%lx)"),
1931 (unsigned long) address_expr
->X_add_number
);
1933 (((address_expr
->X_add_number
& 0x7c0000) << 3)
1934 | ((address_expr
->X_add_number
& 0xf800000) >> 7)
1935 | ((address_expr
->X_add_number
& 0x3fffc) >> 2));
1938 case BFD_RELOC_16_PCREL
:
1939 ip
->insn_opcode
|= address_expr
->X_add_number
& 0xffff;
1942 case BFD_RELOC_16_PCREL_S2
:
1952 /* Don't generate a reloc if we are writing into a variant frag. */
1955 fixp
[0] = fix_new_exp (frag_now
, f
- frag_now
->fr_literal
, 4,
1957 (*reloc_type
== BFD_RELOC_16_PCREL
1958 || *reloc_type
== BFD_RELOC_16_PCREL_S2
),
1961 /* These relocations can have an addend that won't fit in
1962 4 octets for 64bit assembly. */
1963 if (HAVE_64BIT_GPRS
&&
1964 (*reloc_type
== BFD_RELOC_16
1965 || *reloc_type
== BFD_RELOC_32
1966 || *reloc_type
== BFD_RELOC_MIPS_JMP
1967 || *reloc_type
== BFD_RELOC_HI16_S
1968 || *reloc_type
== BFD_RELOC_LO16
1969 || *reloc_type
== BFD_RELOC_GPREL16
1970 || *reloc_type
== BFD_RELOC_MIPS_LITERAL
1971 || *reloc_type
== BFD_RELOC_GPREL32
1972 || *reloc_type
== BFD_RELOC_64
1973 || *reloc_type
== BFD_RELOC_CTOR
1974 || *reloc_type
== BFD_RELOC_MIPS_SUB
1975 || *reloc_type
== BFD_RELOC_MIPS_HIGHEST
1976 || *reloc_type
== BFD_RELOC_MIPS_HIGHER
1977 || *reloc_type
== BFD_RELOC_MIPS_SCN_DISP
1978 || *reloc_type
== BFD_RELOC_MIPS_REL16
1979 || *reloc_type
== BFD_RELOC_MIPS_RELGOT
))
1980 fixp
[0]->fx_no_overflow
= 1;
1984 struct mips_hi_fixup
*hi_fixup
;
1986 assert (*reloc_type
== BFD_RELOC_HI16_S
);
1987 hi_fixup
= ((struct mips_hi_fixup
*)
1988 xmalloc (sizeof (struct mips_hi_fixup
)));
1989 hi_fixup
->fixp
= fixp
[0];
1990 hi_fixup
->seg
= now_seg
;
1991 hi_fixup
->next
= mips_hi_fixup_list
;
1992 mips_hi_fixup_list
= hi_fixup
;
1995 if (reloc_type
[1] != BFD_RELOC_UNUSED
)
1997 /* FIXME: This symbol can be one of
1998 RSS_UNDEF, RSS_GP, RSS_GP0, RSS_LOC. */
1999 address_expr
->X_op
= O_absent
;
2000 address_expr
->X_add_symbol
= 0;
2001 address_expr
->X_add_number
= 0;
2003 fixp
[1] = fix_new_exp (frag_now
, f
- frag_now
->fr_literal
,
2004 4, address_expr
, false,
2007 /* These relocations can have an addend that won't fit in
2008 4 octets for 64bit assembly. */
2009 if (HAVE_64BIT_GPRS
&&
2010 (*reloc_type
== BFD_RELOC_16
2011 || *reloc_type
== BFD_RELOC_32
2012 || *reloc_type
== BFD_RELOC_MIPS_JMP
2013 || *reloc_type
== BFD_RELOC_HI16_S
2014 || *reloc_type
== BFD_RELOC_LO16
2015 || *reloc_type
== BFD_RELOC_GPREL16
2016 || *reloc_type
== BFD_RELOC_MIPS_LITERAL
2017 || *reloc_type
== BFD_RELOC_GPREL32
2018 || *reloc_type
== BFD_RELOC_64
2019 || *reloc_type
== BFD_RELOC_CTOR
2020 || *reloc_type
== BFD_RELOC_MIPS_SUB
2021 || *reloc_type
== BFD_RELOC_MIPS_HIGHEST
2022 || *reloc_type
== BFD_RELOC_MIPS_HIGHER
2023 || *reloc_type
== BFD_RELOC_MIPS_SCN_DISP
2024 || *reloc_type
== BFD_RELOC_MIPS_REL16
2025 || *reloc_type
== BFD_RELOC_MIPS_RELGOT
))
2026 fixp
[1]->fx_no_overflow
= 1;
2028 if (reloc_type
[2] != BFD_RELOC_UNUSED
)
2030 address_expr
->X_op
= O_absent
;
2031 address_expr
->X_add_symbol
= 0;
2032 address_expr
->X_add_number
= 0;
2034 fixp
[2] = fix_new_exp (frag_now
,
2035 f
- frag_now
->fr_literal
, 4,
2036 address_expr
, false,
2039 /* These relocations can have an addend that won't fit in
2040 4 octets for 64bit assembly. */
2041 if (HAVE_64BIT_GPRS
&&
2042 (*reloc_type
== BFD_RELOC_16
2043 || *reloc_type
== BFD_RELOC_32
2044 || *reloc_type
== BFD_RELOC_MIPS_JMP
2045 || *reloc_type
== BFD_RELOC_HI16_S
2046 || *reloc_type
== BFD_RELOC_LO16
2047 || *reloc_type
== BFD_RELOC_GPREL16
2048 || *reloc_type
== BFD_RELOC_MIPS_LITERAL
2049 || *reloc_type
== BFD_RELOC_GPREL32
2050 || *reloc_type
== BFD_RELOC_64
2051 || *reloc_type
== BFD_RELOC_CTOR
2052 || *reloc_type
== BFD_RELOC_MIPS_SUB
2053 || *reloc_type
== BFD_RELOC_MIPS_HIGHEST
2054 || *reloc_type
== BFD_RELOC_MIPS_HIGHER
2055 || *reloc_type
== BFD_RELOC_MIPS_SCN_DISP
2056 || *reloc_type
== BFD_RELOC_MIPS_REL16
2057 || *reloc_type
== BFD_RELOC_MIPS_RELGOT
))
2058 fixp
[2]->fx_no_overflow
= 1;
2065 if (! mips_opts
.mips16
)
2067 md_number_to_chars (f
, ip
->insn_opcode
, 4);
2069 dwarf2_emit_insn (4);
2072 else if (*reloc_type
== BFD_RELOC_MIPS16_JMP
)
2074 md_number_to_chars (f
, ip
->insn_opcode
>> 16, 2);
2075 md_number_to_chars (f
+ 2, ip
->insn_opcode
& 0xffff, 2);
2077 dwarf2_emit_insn (4);
2084 md_number_to_chars (f
, 0xf000 | ip
->extend
, 2);
2087 md_number_to_chars (f
, ip
->insn_opcode
, 2);
2089 dwarf2_emit_insn (ip
->use_extend
? 4 : 2);
2093 /* Update the register mask information. */
2094 if (! mips_opts
.mips16
)
2096 if (pinfo
& INSN_WRITE_GPR_D
)
2097 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
);
2098 if ((pinfo
& (INSN_WRITE_GPR_T
| INSN_READ_GPR_T
)) != 0)
2099 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
);
2100 if (pinfo
& INSN_READ_GPR_S
)
2101 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> OP_SH_RS
) & OP_MASK_RS
);
2102 if (pinfo
& INSN_WRITE_GPR_31
)
2103 mips_gprmask
|= 1 << RA
;
2104 if (pinfo
& INSN_WRITE_FPR_D
)
2105 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FD
) & OP_MASK_FD
);
2106 if ((pinfo
& (INSN_WRITE_FPR_S
| INSN_READ_FPR_S
)) != 0)
2107 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FS
) & OP_MASK_FS
);
2108 if ((pinfo
& (INSN_WRITE_FPR_T
| INSN_READ_FPR_T
)) != 0)
2109 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FT
) & OP_MASK_FT
);
2110 if ((pinfo
& INSN_READ_FPR_R
) != 0)
2111 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FR
) & OP_MASK_FR
);
2112 if (pinfo
& INSN_COP
)
2114 /* We don't keep enough information to sort these cases out.
2115 The itbl support does keep this information however, although
2116 we currently don't support itbl fprmats as part of the cop
2117 instruction. May want to add this support in the future. */
2119 /* Never set the bit for $0, which is always zero. */
2120 mips_gprmask
&= ~1 << 0;
2124 if (pinfo
& (MIPS16_INSN_WRITE_X
| MIPS16_INSN_READ_X
))
2125 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_RX
)
2126 & MIPS16OP_MASK_RX
);
2127 if (pinfo
& (MIPS16_INSN_WRITE_Y
| MIPS16_INSN_READ_Y
))
2128 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_RY
)
2129 & MIPS16OP_MASK_RY
);
2130 if (pinfo
& MIPS16_INSN_WRITE_Z
)
2131 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_RZ
)
2132 & MIPS16OP_MASK_RZ
);
2133 if (pinfo
& (MIPS16_INSN_WRITE_T
| MIPS16_INSN_READ_T
))
2134 mips_gprmask
|= 1 << TREG
;
2135 if (pinfo
& (MIPS16_INSN_WRITE_SP
| MIPS16_INSN_READ_SP
))
2136 mips_gprmask
|= 1 << SP
;
2137 if (pinfo
& (MIPS16_INSN_WRITE_31
| MIPS16_INSN_READ_31
))
2138 mips_gprmask
|= 1 << RA
;
2139 if (pinfo
& MIPS16_INSN_WRITE_GPR_Y
)
2140 mips_gprmask
|= 1 << MIPS16OP_EXTRACT_REG32R (ip
->insn_opcode
);
2141 if (pinfo
& MIPS16_INSN_READ_Z
)
2142 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_MOVE32Z
)
2143 & MIPS16OP_MASK_MOVE32Z
);
2144 if (pinfo
& MIPS16_INSN_READ_GPR_X
)
2145 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_REGR32
)
2146 & MIPS16OP_MASK_REGR32
);
2149 if (place
== NULL
&& ! mips_opts
.noreorder
)
2151 /* Filling the branch delay slot is more complex. We try to
2152 switch the branch with the previous instruction, which we can
2153 do if the previous instruction does not set up a condition
2154 that the branch tests and if the branch is not itself the
2155 target of any branch. */
2156 if ((pinfo
& INSN_UNCOND_BRANCH_DELAY
)
2157 || (pinfo
& INSN_COND_BRANCH_DELAY
))
2159 if (mips_optimize
< 2
2160 /* If we have seen .set volatile or .set nomove, don't
2162 || mips_opts
.nomove
!= 0
2163 /* If we had to emit any NOP instructions, then we
2164 already know we can not swap. */
2166 /* If we don't even know the previous insn, we can not
2168 || ! prev_insn_valid
2169 /* If the previous insn is already in a branch delay
2170 slot, then we can not swap. */
2171 || prev_insn_is_delay_slot
2172 /* If the previous previous insn was in a .set
2173 noreorder, we can't swap. Actually, the MIPS
2174 assembler will swap in this situation. However, gcc
2175 configured -with-gnu-as will generate code like
2181 in which we can not swap the bne and INSN. If gcc is
2182 not configured -with-gnu-as, it does not output the
2183 .set pseudo-ops. We don't have to check
2184 prev_insn_unreordered, because prev_insn_valid will
2185 be 0 in that case. We don't want to use
2186 prev_prev_insn_valid, because we do want to be able
2187 to swap at the start of a function. */
2188 || prev_prev_insn_unreordered
2189 /* If the branch is itself the target of a branch, we
2190 can not swap. We cheat on this; all we check for is
2191 whether there is a label on this instruction. If
2192 there are any branches to anything other than a
2193 label, users must use .set noreorder. */
2194 || insn_labels
!= NULL
2195 /* If the previous instruction is in a variant frag, we
2196 can not do the swap. This does not apply to the
2197 mips16, which uses variant frags for different
2199 || (! mips_opts
.mips16
2200 && prev_insn_frag
->fr_type
== rs_machine_dependent
)
2201 /* If the branch reads the condition codes, we don't
2202 even try to swap, because in the sequence
2207 we can not swap, and I don't feel like handling that
2209 || (! mips_opts
.mips16
2210 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
2211 && (pinfo
& INSN_READ_COND_CODE
))
2212 /* We can not swap with an instruction that requires a
2213 delay slot, becase the target of the branch might
2214 interfere with that instruction. */
2215 || (! mips_opts
.mips16
2216 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
2218 /* Itbl support may require additional care here. */
2219 & (INSN_LOAD_COPROC_DELAY
2220 | INSN_COPROC_MOVE_DELAY
2221 | INSN_WRITE_COND_CODE
)))
2222 || (! (hilo_interlocks
2223 || (mips_tune
== CPU_R3900
&& (pinfo
& INSN_MULT
)))
2227 || (! mips_opts
.mips16
2229 && (prev_pinfo
& INSN_LOAD_MEMORY_DELAY
))
2230 || (! mips_opts
.mips16
2231 && mips_opts
.isa
== ISA_MIPS1
2232 /* Itbl support may require additional care here. */
2233 && (prev_pinfo
& INSN_COPROC_MEMORY_DELAY
))
2234 /* We can not swap with a branch instruction. */
2236 & (INSN_UNCOND_BRANCH_DELAY
2237 | INSN_COND_BRANCH_DELAY
2238 | INSN_COND_BRANCH_LIKELY
))
2239 /* We do not swap with a trap instruction, since it
2240 complicates trap handlers to have the trap
2241 instruction be in a delay slot. */
2242 || (prev_pinfo
& INSN_TRAP
)
2243 /* If the branch reads a register that the previous
2244 instruction sets, we can not swap. */
2245 || (! mips_opts
.mips16
2246 && (prev_pinfo
& INSN_WRITE_GPR_T
)
2247 && insn_uses_reg (ip
,
2248 ((prev_insn
.insn_opcode
>> OP_SH_RT
)
2251 || (! mips_opts
.mips16
2252 && (prev_pinfo
& INSN_WRITE_GPR_D
)
2253 && insn_uses_reg (ip
,
2254 ((prev_insn
.insn_opcode
>> OP_SH_RD
)
2257 || (mips_opts
.mips16
2258 && (((prev_pinfo
& MIPS16_INSN_WRITE_X
)
2259 && insn_uses_reg (ip
,
2260 ((prev_insn
.insn_opcode
2262 & MIPS16OP_MASK_RX
),
2264 || ((prev_pinfo
& MIPS16_INSN_WRITE_Y
)
2265 && insn_uses_reg (ip
,
2266 ((prev_insn
.insn_opcode
2268 & MIPS16OP_MASK_RY
),
2270 || ((prev_pinfo
& MIPS16_INSN_WRITE_Z
)
2271 && insn_uses_reg (ip
,
2272 ((prev_insn
.insn_opcode
2274 & MIPS16OP_MASK_RZ
),
2276 || ((prev_pinfo
& MIPS16_INSN_WRITE_T
)
2277 && insn_uses_reg (ip
, TREG
, MIPS_GR_REG
))
2278 || ((prev_pinfo
& MIPS16_INSN_WRITE_31
)
2279 && insn_uses_reg (ip
, RA
, MIPS_GR_REG
))
2280 || ((prev_pinfo
& MIPS16_INSN_WRITE_GPR_Y
)
2281 && insn_uses_reg (ip
,
2282 MIPS16OP_EXTRACT_REG32R (prev_insn
.
2285 /* If the branch writes a register that the previous
2286 instruction sets, we can not swap (we know that
2287 branches write only to RD or to $31). */
2288 || (! mips_opts
.mips16
2289 && (prev_pinfo
& INSN_WRITE_GPR_T
)
2290 && (((pinfo
& INSN_WRITE_GPR_D
)
2291 && (((prev_insn
.insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
)
2292 == ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)))
2293 || ((pinfo
& INSN_WRITE_GPR_31
)
2294 && (((prev_insn
.insn_opcode
>> OP_SH_RT
)
2297 || (! mips_opts
.mips16
2298 && (prev_pinfo
& INSN_WRITE_GPR_D
)
2299 && (((pinfo
& INSN_WRITE_GPR_D
)
2300 && (((prev_insn
.insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)
2301 == ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)))
2302 || ((pinfo
& INSN_WRITE_GPR_31
)
2303 && (((prev_insn
.insn_opcode
>> OP_SH_RD
)
2306 || (mips_opts
.mips16
2307 && (pinfo
& MIPS16_INSN_WRITE_31
)
2308 && ((prev_pinfo
& MIPS16_INSN_WRITE_31
)
2309 || ((prev_pinfo
& MIPS16_INSN_WRITE_GPR_Y
)
2310 && (MIPS16OP_EXTRACT_REG32R (prev_insn
.insn_opcode
)
2312 /* If the branch writes a register that the previous
2313 instruction reads, we can not swap (we know that
2314 branches only write to RD or to $31). */
2315 || (! mips_opts
.mips16
2316 && (pinfo
& INSN_WRITE_GPR_D
)
2317 && insn_uses_reg (&prev_insn
,
2318 ((ip
->insn_opcode
>> OP_SH_RD
)
2321 || (! mips_opts
.mips16
2322 && (pinfo
& INSN_WRITE_GPR_31
)
2323 && insn_uses_reg (&prev_insn
, RA
, MIPS_GR_REG
))
2324 || (mips_opts
.mips16
2325 && (pinfo
& MIPS16_INSN_WRITE_31
)
2326 && insn_uses_reg (&prev_insn
, RA
, MIPS_GR_REG
))
2327 /* If we are generating embedded PIC code, the branch
2328 might be expanded into a sequence which uses $at, so
2329 we can't swap with an instruction which reads it. */
2330 || (mips_pic
== EMBEDDED_PIC
2331 && insn_uses_reg (&prev_insn
, AT
, MIPS_GR_REG
))
2332 /* If the previous previous instruction has a load
2333 delay, and sets a register that the branch reads, we
2335 || (! mips_opts
.mips16
2336 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
2337 /* Itbl support may require additional care here. */
2338 && ((prev_prev_insn
.insn_mo
->pinfo
& INSN_LOAD_COPROC_DELAY
)
2339 || (! gpr_interlocks
2340 && (prev_prev_insn
.insn_mo
->pinfo
2341 & INSN_LOAD_MEMORY_DELAY
)))
2342 && insn_uses_reg (ip
,
2343 ((prev_prev_insn
.insn_opcode
>> OP_SH_RT
)
2346 /* If one instruction sets a condition code and the
2347 other one uses a condition code, we can not swap. */
2348 || ((pinfo
& INSN_READ_COND_CODE
)
2349 && (prev_pinfo
& INSN_WRITE_COND_CODE
))
2350 || ((pinfo
& INSN_WRITE_COND_CODE
)
2351 && (prev_pinfo
& INSN_READ_COND_CODE
))
2352 /* If the previous instruction uses the PC, we can not
2354 || (mips_opts
.mips16
2355 && (prev_pinfo
& MIPS16_INSN_READ_PC
))
2356 /* If the previous instruction was extended, we can not
2358 || (mips_opts
.mips16
&& prev_insn_extended
)
2359 /* If the previous instruction had a fixup in mips16
2360 mode, we can not swap. This normally means that the
2361 previous instruction was a 4 byte branch anyhow. */
2362 || (mips_opts
.mips16
&& prev_insn_fixp
[0])
2363 /* If the previous instruction is a sync, sync.l, or
2364 sync.p, we can not swap. */
2365 || (prev_pinfo
& INSN_SYNC
))
2367 /* We could do even better for unconditional branches to
2368 portions of this object file; we could pick up the
2369 instruction at the destination, put it in the delay
2370 slot, and bump the destination address. */
2372 /* Update the previous insn information. */
2373 prev_prev_insn
= *ip
;
2374 prev_insn
.insn_mo
= &dummy_opcode
;
2378 /* It looks like we can actually do the swap. */
2379 if (! mips_opts
.mips16
)
2384 prev_f
= prev_insn_frag
->fr_literal
+ prev_insn_where
;
2385 memcpy (temp
, prev_f
, 4);
2386 memcpy (prev_f
, f
, 4);
2387 memcpy (f
, temp
, 4);
2388 if (prev_insn_fixp
[0])
2390 prev_insn_fixp
[0]->fx_frag
= frag_now
;
2391 prev_insn_fixp
[0]->fx_where
= f
- frag_now
->fr_literal
;
2393 if (prev_insn_fixp
[1])
2395 prev_insn_fixp
[1]->fx_frag
= frag_now
;
2396 prev_insn_fixp
[1]->fx_where
= f
- frag_now
->fr_literal
;
2398 if (prev_insn_fixp
[2])
2400 prev_insn_fixp
[2]->fx_frag
= frag_now
;
2401 prev_insn_fixp
[2]->fx_where
= f
- frag_now
->fr_literal
;
2405 fixp
[0]->fx_frag
= prev_insn_frag
;
2406 fixp
[0]->fx_where
= prev_insn_where
;
2410 fixp
[1]->fx_frag
= prev_insn_frag
;
2411 fixp
[1]->fx_where
= prev_insn_where
;
2415 fixp
[2]->fx_frag
= prev_insn_frag
;
2416 fixp
[2]->fx_where
= prev_insn_where
;
2424 assert (prev_insn_fixp
[0] == NULL
);
2425 assert (prev_insn_fixp
[1] == NULL
);
2426 assert (prev_insn_fixp
[2] == NULL
);
2427 prev_f
= prev_insn_frag
->fr_literal
+ prev_insn_where
;
2428 memcpy (temp
, prev_f
, 2);
2429 memcpy (prev_f
, f
, 2);
2430 if (*reloc_type
!= BFD_RELOC_MIPS16_JMP
)
2432 assert (*reloc_type
== BFD_RELOC_UNUSED
);
2433 memcpy (f
, temp
, 2);
2437 memcpy (f
, f
+ 2, 2);
2438 memcpy (f
+ 2, temp
, 2);
2442 fixp
[0]->fx_frag
= prev_insn_frag
;
2443 fixp
[0]->fx_where
= prev_insn_where
;
2447 fixp
[1]->fx_frag
= prev_insn_frag
;
2448 fixp
[1]->fx_where
= prev_insn_where
;
2452 fixp
[2]->fx_frag
= prev_insn_frag
;
2453 fixp
[2]->fx_where
= prev_insn_where
;
2457 /* Update the previous insn information; leave prev_insn
2459 prev_prev_insn
= *ip
;
2461 prev_insn_is_delay_slot
= 1;
2463 /* If that was an unconditional branch, forget the previous
2464 insn information. */
2465 if (pinfo
& INSN_UNCOND_BRANCH_DELAY
)
2467 prev_prev_insn
.insn_mo
= &dummy_opcode
;
2468 prev_insn
.insn_mo
= &dummy_opcode
;
2471 prev_insn_fixp
[0] = NULL
;
2472 prev_insn_fixp
[1] = NULL
;
2473 prev_insn_fixp
[2] = NULL
;
2474 prev_insn_reloc_type
[0] = BFD_RELOC_UNUSED
;
2475 prev_insn_reloc_type
[1] = BFD_RELOC_UNUSED
;
2476 prev_insn_reloc_type
[2] = BFD_RELOC_UNUSED
;
2477 prev_insn_extended
= 0;
2479 else if (pinfo
& INSN_COND_BRANCH_LIKELY
)
2481 /* We don't yet optimize a branch likely. What we should do
2482 is look at the target, copy the instruction found there
2483 into the delay slot, and increment the branch to jump to
2484 the next instruction. */
2486 /* Update the previous insn information. */
2487 prev_prev_insn
= *ip
;
2488 prev_insn
.insn_mo
= &dummy_opcode
;
2489 prev_insn_fixp
[0] = NULL
;
2490 prev_insn_fixp
[1] = NULL
;
2491 prev_insn_fixp
[2] = NULL
;
2492 prev_insn_reloc_type
[0] = BFD_RELOC_UNUSED
;
2493 prev_insn_reloc_type
[1] = BFD_RELOC_UNUSED
;
2494 prev_insn_reloc_type
[2] = BFD_RELOC_UNUSED
;
2495 prev_insn_extended
= 0;
2499 /* Update the previous insn information. */
2501 prev_prev_insn
.insn_mo
= &dummy_opcode
;
2503 prev_prev_insn
= prev_insn
;
2506 /* Any time we see a branch, we always fill the delay slot
2507 immediately; since this insn is not a branch, we know it
2508 is not in a delay slot. */
2509 prev_insn_is_delay_slot
= 0;
2511 prev_insn_fixp
[0] = fixp
[0];
2512 prev_insn_fixp
[1] = fixp
[1];
2513 prev_insn_fixp
[2] = fixp
[2];
2514 prev_insn_reloc_type
[0] = reloc_type
[0];
2515 prev_insn_reloc_type
[1] = reloc_type
[1];
2516 prev_insn_reloc_type
[2] = reloc_type
[2];
2517 if (mips_opts
.mips16
)
2518 prev_insn_extended
= (ip
->use_extend
2519 || *reloc_type
> BFD_RELOC_UNUSED
);
2522 prev_prev_insn_unreordered
= prev_insn_unreordered
;
2523 prev_insn_unreordered
= 0;
2524 prev_insn_frag
= frag_now
;
2525 prev_insn_where
= f
- frag_now
->fr_literal
;
2526 prev_insn_valid
= 1;
2528 else if (place
== NULL
)
2530 /* We need to record a bit of information even when we are not
2531 reordering, in order to determine the base address for mips16
2532 PC relative relocs. */
2533 prev_prev_insn
= prev_insn
;
2535 prev_insn_reloc_type
[0] = reloc_type
[0];
2536 prev_insn_reloc_type
[1] = reloc_type
[1];
2537 prev_insn_reloc_type
[2] = reloc_type
[2];
2538 prev_prev_insn_unreordered
= prev_insn_unreordered
;
2539 prev_insn_unreordered
= 1;
2542 /* We just output an insn, so the next one doesn't have a label. */
2543 mips_clear_insn_labels ();
2545 /* We must ensure that a fixup associated with an unmatched %hi
2546 reloc does not become a variant frag. Otherwise, the
2547 rearrangement of %hi relocs in frob_file may confuse
2551 frag_wane (frag_now
);
2556 /* This function forgets that there was any previous instruction or
2557 label. If PRESERVE is non-zero, it remembers enough information to
2558 know whether nops are needed before a noreorder section. */
2561 mips_no_prev_insn (preserve
)
2566 prev_insn
.insn_mo
= &dummy_opcode
;
2567 prev_prev_insn
.insn_mo
= &dummy_opcode
;
2568 prev_nop_frag
= NULL
;
2569 prev_nop_frag_holds
= 0;
2570 prev_nop_frag_required
= 0;
2571 prev_nop_frag_since
= 0;
2573 prev_insn_valid
= 0;
2574 prev_insn_is_delay_slot
= 0;
2575 prev_insn_unreordered
= 0;
2576 prev_insn_extended
= 0;
2577 prev_insn_reloc_type
[0] = BFD_RELOC_UNUSED
;
2578 prev_insn_reloc_type
[1] = BFD_RELOC_UNUSED
;
2579 prev_insn_reloc_type
[2] = BFD_RELOC_UNUSED
;
2580 prev_prev_insn_unreordered
= 0;
2581 mips_clear_insn_labels ();
2584 /* This function must be called whenever we turn on noreorder or emit
2585 something other than instructions. It inserts any NOPS which might
2586 be needed by the previous instruction, and clears the information
2587 kept for the previous instructions. The INSNS parameter is true if
2588 instructions are to follow. */
2591 mips_emit_delays (insns
)
2594 if (! mips_opts
.noreorder
)
2599 if ((! mips_opts
.mips16
2600 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
2601 && (! cop_interlocks
2602 && (prev_insn
.insn_mo
->pinfo
2603 & (INSN_LOAD_COPROC_DELAY
2604 | INSN_COPROC_MOVE_DELAY
2605 | INSN_WRITE_COND_CODE
))))
2606 || (! hilo_interlocks
2607 && (prev_insn
.insn_mo
->pinfo
2610 || (! mips_opts
.mips16
2612 && (prev_insn
.insn_mo
->pinfo
2613 & INSN_LOAD_MEMORY_DELAY
))
2614 || (! mips_opts
.mips16
2615 && mips_opts
.isa
== ISA_MIPS1
2616 && (prev_insn
.insn_mo
->pinfo
2617 & INSN_COPROC_MEMORY_DELAY
)))
2619 /* Itbl support may require additional care here. */
2621 if ((! mips_opts
.mips16
2622 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
2623 && (! cop_interlocks
2624 && prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
))
2625 || (! hilo_interlocks
2626 && ((prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
2627 || (prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
))))
2630 if (prev_insn_unreordered
)
2633 else if ((! mips_opts
.mips16
2634 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
2635 && (! cop_interlocks
2636 && prev_prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
))
2637 || (! hilo_interlocks
2638 && ((prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
2639 || (prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
))))
2641 /* Itbl support may require additional care here. */
2642 if (! prev_prev_insn_unreordered
)
2646 if (mips_fix_4122_bugs
&& prev_insn
.insn_mo
->name
)
2649 const char *pn
= prev_insn
.insn_mo
->name
;
2650 if (strncmp(pn
, "macc", 4) == 0
2651 || strncmp(pn
, "dmacc", 5) == 0
2652 || strncmp(pn
, "dmult", 5) == 0)
2656 if (nops
< min_nops
)
2662 struct insn_label_list
*l
;
2666 /* Record the frag which holds the nop instructions, so
2667 that we can remove them if we don't need them. */
2668 frag_grow (mips_opts
.mips16
? nops
* 2 : nops
* 4);
2669 prev_nop_frag
= frag_now
;
2670 prev_nop_frag_holds
= nops
;
2671 prev_nop_frag_required
= 0;
2672 prev_nop_frag_since
= 0;
2675 for (; nops
> 0; --nops
)
2680 /* Move on to a new frag, so that it is safe to simply
2681 decrease the size of prev_nop_frag. */
2682 frag_wane (frag_now
);
2686 for (l
= insn_labels
; l
!= NULL
; l
= l
->next
)
2690 assert (S_GET_SEGMENT (l
->label
) == now_seg
);
2691 symbol_set_frag (l
->label
, frag_now
);
2692 val
= (valueT
) frag_now_fix ();
2693 /* mips16 text labels are stored as odd. */
2694 if (mips_opts
.mips16
)
2696 S_SET_VALUE (l
->label
, val
);
2701 /* Mark instruction labels in mips16 mode. */
2703 mips16_mark_labels ();
2705 mips_no_prev_insn (insns
);
2708 /* Build an instruction created by a macro expansion. This is passed
2709 a pointer to the count of instructions created so far, an
2710 expression, the name of the instruction to build, an operand format
2711 string, and corresponding arguments. */
2715 macro_build (char *place
,
2723 macro_build (place
, counter
, ep
, name
, fmt
, va_alist
)
2732 struct mips_cl_insn insn
;
2733 bfd_reloc_code_real_type r
[3];
2737 va_start (args
, fmt
);
2743 * If the macro is about to expand into a second instruction,
2744 * print a warning if needed. We need to pass ip as a parameter
2745 * to generate a better warning message here...
2747 if (mips_opts
.warn_about_macros
&& place
== NULL
&& *counter
== 1)
2748 as_warn (_("Macro instruction expanded into multiple instructions"));
2751 * If the macro is about to expand into a second instruction,
2752 * and it is in a delay slot, print a warning.
2756 && mips_opts
.noreorder
2757 && (prev_prev_insn
.insn_mo
->pinfo
2758 & (INSN_UNCOND_BRANCH_DELAY
| INSN_COND_BRANCH_DELAY
2759 | INSN_COND_BRANCH_LIKELY
)) != 0)
2760 as_warn (_("Macro instruction expanded into multiple instructions in a branch delay slot"));
2763 ++*counter
; /* bump instruction counter */
2765 if (mips_opts
.mips16
)
2767 mips16_macro_build (place
, counter
, ep
, name
, fmt
, args
);
2772 r
[0] = BFD_RELOC_UNUSED
;
2773 r
[1] = BFD_RELOC_UNUSED
;
2774 r
[2] = BFD_RELOC_UNUSED
;
2775 insn
.insn_mo
= (struct mips_opcode
*) hash_find (op_hash
, name
);
2776 assert (insn
.insn_mo
);
2777 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
2779 /* Search until we get a match for NAME. */
2782 /* It is assumed here that macros will never generate
2783 MDMX or MIPS-3D instructions. */
2784 if (strcmp (fmt
, insn
.insn_mo
->args
) == 0
2785 && insn
.insn_mo
->pinfo
!= INSN_MACRO
2786 && OPCODE_IS_MEMBER (insn
.insn_mo
,
2788 | (file_ase_mips16
? INSN_MIPS16
: 0)),
2790 && (mips_arch
!= CPU_R4650
|| (insn
.insn_mo
->pinfo
& FP_D
) == 0))
2794 assert (insn
.insn_mo
->name
);
2795 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
2798 insn
.insn_opcode
= insn
.insn_mo
->match
;
2814 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_RT
;
2818 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_CODE
;
2823 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_FT
;
2828 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_RD
;
2833 int tmp
= va_arg (args
, int);
2835 insn
.insn_opcode
|= tmp
<< OP_SH_RT
;
2836 insn
.insn_opcode
|= tmp
<< OP_SH_RD
;
2842 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_FS
;
2849 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_SHAMT
;
2853 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_FD
;
2857 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_CODE20
;
2861 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_CODE19
;
2865 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_CODE2
;
2872 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_RS
;
2878 *r
= (bfd_reloc_code_real_type
) va_arg (args
, int);
2879 assert (*r
== BFD_RELOC_GPREL16
2880 || *r
== BFD_RELOC_MIPS_LITERAL
2881 || *r
== BFD_RELOC_MIPS_HIGHER
2882 || *r
== BFD_RELOC_HI16_S
2883 || *r
== BFD_RELOC_LO16
2884 || *r
== BFD_RELOC_MIPS_GOT16
2885 || *r
== BFD_RELOC_MIPS_CALL16
2886 || *r
== BFD_RELOC_MIPS_GOT_DISP
2887 || *r
== BFD_RELOC_MIPS_GOT_PAGE
2888 || *r
== BFD_RELOC_MIPS_GOT_OFST
2889 || *r
== BFD_RELOC_MIPS_GOT_LO16
2890 || *r
== BFD_RELOC_MIPS_CALL_LO16
2891 || (ep
->X_op
== O_subtract
2892 && *r
== BFD_RELOC_PCREL_LO16
));
2896 *r
= (bfd_reloc_code_real_type
) va_arg (args
, int);
2898 && (ep
->X_op
== O_constant
2899 || (ep
->X_op
== O_symbol
2900 && (*r
== BFD_RELOC_MIPS_HIGHEST
2901 || *r
== BFD_RELOC_HI16_S
2902 || *r
== BFD_RELOC_HI16
2903 || *r
== BFD_RELOC_GPREL16
2904 || *r
== BFD_RELOC_MIPS_GOT_HI16
2905 || *r
== BFD_RELOC_MIPS_CALL_HI16
))
2906 || (ep
->X_op
== O_subtract
2907 && *r
== BFD_RELOC_PCREL_HI16_S
)));
2911 assert (ep
!= NULL
);
2913 * This allows macro() to pass an immediate expression for
2914 * creating short branches without creating a symbol.
2915 * Note that the expression still might come from the assembly
2916 * input, in which case the value is not checked for range nor
2917 * is a relocation entry generated (yuck).
2919 if (ep
->X_op
== O_constant
)
2921 insn
.insn_opcode
|= (ep
->X_add_number
>> 2) & 0xffff;
2925 if (mips_pic
== EMBEDDED_PIC
)
2926 *r
= BFD_RELOC_16_PCREL_S2
;
2928 *r
= BFD_RELOC_16_PCREL
;
2932 assert (ep
!= NULL
);
2933 *r
= BFD_RELOC_MIPS_JMP
;
2937 insn
.insn_opcode
|= va_arg (args
, unsigned long);
2946 assert (*r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
2948 append_insn (place
, &insn
, ep
, r
, false);
2952 mips16_macro_build (place
, counter
, ep
, name
, fmt
, args
)
2954 int *counter ATTRIBUTE_UNUSED
;
2960 struct mips_cl_insn insn
;
2961 bfd_reloc_code_real_type r
[3]
2962 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
2964 insn
.insn_mo
= (struct mips_opcode
*) hash_find (mips16_op_hash
, name
);
2965 assert (insn
.insn_mo
);
2966 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
2968 while (strcmp (fmt
, insn
.insn_mo
->args
) != 0
2969 || insn
.insn_mo
->pinfo
== INSN_MACRO
)
2972 assert (insn
.insn_mo
->name
);
2973 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
2976 insn
.insn_opcode
= insn
.insn_mo
->match
;
2977 insn
.use_extend
= false;
2996 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_RY
;
3001 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_RX
;
3005 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_RZ
;
3009 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_MOVE32Z
;
3019 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_REGR32
;
3026 regno
= va_arg (args
, int);
3027 regno
= ((regno
& 7) << 2) | ((regno
& 0x18) >> 3);
3028 insn
.insn_opcode
|= regno
<< MIPS16OP_SH_REG32R
;
3049 assert (ep
!= NULL
);
3051 if (ep
->X_op
!= O_constant
)
3052 *r
= (int) BFD_RELOC_UNUSED
+ c
;
3055 mips16_immed (NULL
, 0, c
, ep
->X_add_number
, false, false,
3056 false, &insn
.insn_opcode
, &insn
.use_extend
,
3059 *r
= BFD_RELOC_UNUSED
;
3065 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_IMM6
;
3072 assert (*r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
3074 append_insn (place
, &insn
, ep
, r
, false);
3078 * Generate a "jalr" instruction with a relocation hint to the called
3079 * function. This occurs in NewABI PIC code.
3082 macro_build_jalr (icnt
, ep
)
3093 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "jalr", "d,s",
3096 fix_new_exp (frag_now
, f
- frag_now
->fr_literal
,
3097 0, ep
, false, BFD_RELOC_MIPS_JALR
);
3101 * Generate a "lui" instruction.
3104 macro_build_lui (place
, counter
, ep
, regnum
)
3110 expressionS high_expr
;
3111 struct mips_cl_insn insn
;
3112 bfd_reloc_code_real_type r
[3]
3113 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
3114 const char *name
= "lui";
3115 const char *fmt
= "t,u";
3117 assert (! mips_opts
.mips16
);
3123 high_expr
.X_op
= O_constant
;
3124 high_expr
.X_add_number
= ep
->X_add_number
;
3127 if (high_expr
.X_op
== O_constant
)
3129 /* we can compute the instruction now without a relocation entry */
3130 high_expr
.X_add_number
= ((high_expr
.X_add_number
+ 0x8000)
3132 *r
= BFD_RELOC_UNUSED
;
3134 else if (! HAVE_NEWABI
)
3136 assert (ep
->X_op
== O_symbol
);
3137 /* _gp_disp is a special case, used from s_cpload. */
3138 assert (mips_pic
== NO_PIC
3139 || strcmp (S_GET_NAME (ep
->X_add_symbol
), "_gp_disp") == 0);
3140 *r
= BFD_RELOC_HI16_S
;
3144 * If the macro is about to expand into a second instruction,
3145 * print a warning if needed. We need to pass ip as a parameter
3146 * to generate a better warning message here...
3148 if (mips_opts
.warn_about_macros
&& place
== NULL
&& *counter
== 1)
3149 as_warn (_("Macro instruction expanded into multiple instructions"));
3152 ++*counter
; /* bump instruction counter */
3154 insn
.insn_mo
= (struct mips_opcode
*) hash_find (op_hash
, name
);
3155 assert (insn
.insn_mo
);
3156 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
3157 assert (strcmp (fmt
, insn
.insn_mo
->args
) == 0);
3159 insn
.insn_opcode
= insn
.insn_mo
->match
| (regnum
<< OP_SH_RT
);
3160 if (*r
== BFD_RELOC_UNUSED
)
3162 insn
.insn_opcode
|= high_expr
.X_add_number
;
3163 append_insn (place
, &insn
, NULL
, r
, false);
3166 append_insn (place
, &insn
, &high_expr
, r
, false);
3169 /* Generate a sequence of instructions to do a load or store from a constant
3170 offset off of a base register (breg) into/from a target register (treg),
3171 using AT if necessary. */
3173 macro_build_ldst_constoffset (place
, counter
, ep
, op
, treg
, breg
)
3180 assert (ep
->X_op
== O_constant
);
3182 /* Right now, this routine can only handle signed 32-bit contants. */
3183 if (! IS_SEXT_32BIT_NUM(ep
->X_add_number
))
3184 as_warn (_("operand overflow"));
3186 if (IS_SEXT_16BIT_NUM(ep
->X_add_number
))
3188 /* Signed 16-bit offset will fit in the op. Easy! */
3189 macro_build (place
, counter
, ep
, op
, "t,o(b)", treg
,
3190 (int) BFD_RELOC_LO16
, breg
);
3194 /* 32-bit offset, need multiple instructions and AT, like:
3195 lui $tempreg,const_hi (BFD_RELOC_HI16_S)
3196 addu $tempreg,$tempreg,$breg
3197 <op> $treg,const_lo($tempreg) (BFD_RELOC_LO16)
3198 to handle the complete offset. */
3199 macro_build_lui (place
, counter
, ep
, AT
);
3202 macro_build (place
, counter
, (expressionS
*) NULL
,
3203 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
3204 "d,v,t", AT
, AT
, breg
);
3207 macro_build (place
, counter
, ep
, op
, "t,o(b)", treg
,
3208 (int) BFD_RELOC_LO16
, AT
);
3211 as_warn (_("Macro used $at after \".set noat\""));
3216 * Generates code to set the $at register to true (one)
3217 * if reg is less than the immediate expression.
3220 set_at (counter
, reg
, unsignedp
)
3225 if (imm_expr
.X_op
== O_constant
3226 && imm_expr
.X_add_number
>= -0x8000
3227 && imm_expr
.X_add_number
< 0x8000)
3228 macro_build ((char *) NULL
, counter
, &imm_expr
,
3229 unsignedp
? "sltiu" : "slti",
3230 "t,r,j", AT
, reg
, (int) BFD_RELOC_LO16
);
3233 load_register (counter
, AT
, &imm_expr
, HAVE_64BIT_GPRS
);
3234 macro_build ((char *) NULL
, counter
, (expressionS
*) NULL
,
3235 unsignedp
? "sltu" : "slt",
3236 "d,v,t", AT
, reg
, AT
);
3240 /* Warn if an expression is not a constant. */
3243 check_absolute_expr (ip
, ex
)
3244 struct mips_cl_insn
*ip
;
3247 if (ex
->X_op
== O_big
)
3248 as_bad (_("unsupported large constant"));
3249 else if (ex
->X_op
!= O_constant
)
3250 as_bad (_("Instruction %s requires absolute expression"), ip
->insn_mo
->name
);
3253 /* Count the leading zeroes by performing a binary chop. This is a
3254 bulky bit of source, but performance is a LOT better for the
3255 majority of values than a simple loop to count the bits:
3256 for (lcnt = 0; (lcnt < 32); lcnt++)
3257 if ((v) & (1 << (31 - lcnt)))
3259 However it is not code size friendly, and the gain will drop a bit
3260 on certain cached systems.
3262 #define COUNT_TOP_ZEROES(v) \
3263 (((v) & ~0xffff) == 0 \
3264 ? ((v) & ~0xff) == 0 \
3265 ? ((v) & ~0xf) == 0 \
3266 ? ((v) & ~0x3) == 0 \
3267 ? ((v) & ~0x1) == 0 \
3272 : ((v) & ~0x7) == 0 \
3275 : ((v) & ~0x3f) == 0 \
3276 ? ((v) & ~0x1f) == 0 \
3279 : ((v) & ~0x7f) == 0 \
3282 : ((v) & ~0xfff) == 0 \
3283 ? ((v) & ~0x3ff) == 0 \
3284 ? ((v) & ~0x1ff) == 0 \
3287 : ((v) & ~0x7ff) == 0 \
3290 : ((v) & ~0x3fff) == 0 \
3291 ? ((v) & ~0x1fff) == 0 \
3294 : ((v) & ~0x7fff) == 0 \
3297 : ((v) & ~0xffffff) == 0 \
3298 ? ((v) & ~0xfffff) == 0 \
3299 ? ((v) & ~0x3ffff) == 0 \
3300 ? ((v) & ~0x1ffff) == 0 \
3303 : ((v) & ~0x7ffff) == 0 \
3306 : ((v) & ~0x3fffff) == 0 \
3307 ? ((v) & ~0x1fffff) == 0 \
3310 : ((v) & ~0x7fffff) == 0 \
3313 : ((v) & ~0xfffffff) == 0 \
3314 ? ((v) & ~0x3ffffff) == 0 \
3315 ? ((v) & ~0x1ffffff) == 0 \
3318 : ((v) & ~0x7ffffff) == 0 \
3321 : ((v) & ~0x3fffffff) == 0 \
3322 ? ((v) & ~0x1fffffff) == 0 \
3325 : ((v) & ~0x7fffffff) == 0 \
3330 * This routine generates the least number of instructions neccessary to load
3331 * an absolute expression value into a register.
3334 load_register (counter
, reg
, ep
, dbl
)
3341 expressionS hi32
, lo32
;
3343 if (ep
->X_op
!= O_big
)
3345 assert (ep
->X_op
== O_constant
);
3346 if (ep
->X_add_number
< 0x8000
3347 && (ep
->X_add_number
>= 0
3348 || (ep
->X_add_number
>= -0x8000
3351 || sizeof (ep
->X_add_number
) > 4))))
3353 /* We can handle 16 bit signed values with an addiu to
3354 $zero. No need to ever use daddiu here, since $zero and
3355 the result are always correct in 32 bit mode. */
3356 macro_build ((char *) NULL
, counter
, ep
, "addiu", "t,r,j", reg
, 0,
3357 (int) BFD_RELOC_LO16
);
3360 else if (ep
->X_add_number
>= 0 && ep
->X_add_number
< 0x10000)
3362 /* We can handle 16 bit unsigned values with an ori to
3364 macro_build ((char *) NULL
, counter
, ep
, "ori", "t,r,i", reg
, 0,
3365 (int) BFD_RELOC_LO16
);
3368 else if ((IS_SEXT_32BIT_NUM (ep
->X_add_number
)
3371 || sizeof (ep
->X_add_number
) > 4
3372 || (ep
->X_add_number
& 0x80000000) == 0))
3373 || ((HAVE_32BIT_GPRS
|| ! dbl
)
3374 && (ep
->X_add_number
&~ (offsetT
) 0xffffffff) == 0)
3377 && ((ep
->X_add_number
&~ (offsetT
) 0xffffffff)
3378 == ~ (offsetT
) 0xffffffff)))
3380 /* 32 bit values require an lui. */
3381 macro_build ((char *) NULL
, counter
, ep
, "lui", "t,u", reg
,
3382 (int) BFD_RELOC_HI16
);
3383 if ((ep
->X_add_number
& 0xffff) != 0)
3384 macro_build ((char *) NULL
, counter
, ep
, "ori", "t,r,i", reg
, reg
,
3385 (int) BFD_RELOC_LO16
);
3390 /* The value is larger than 32 bits. */
3392 if (HAVE_32BIT_GPRS
)
3394 as_bad (_("Number (0x%lx) larger than 32 bits"),
3395 (unsigned long) ep
->X_add_number
);
3396 macro_build ((char *) NULL
, counter
, ep
, "addiu", "t,r,j", reg
, 0,
3397 (int) BFD_RELOC_LO16
);
3401 if (ep
->X_op
!= O_big
)
3404 hi32
.X_add_number
= (valueT
) hi32
.X_add_number
>> 16;
3405 hi32
.X_add_number
= (valueT
) hi32
.X_add_number
>> 16;
3406 hi32
.X_add_number
&= 0xffffffff;
3408 lo32
.X_add_number
&= 0xffffffff;
3412 assert (ep
->X_add_number
> 2);
3413 if (ep
->X_add_number
== 3)
3414 generic_bignum
[3] = 0;
3415 else if (ep
->X_add_number
> 4)
3416 as_bad (_("Number larger than 64 bits"));
3417 lo32
.X_op
= O_constant
;
3418 lo32
.X_add_number
= generic_bignum
[0] + (generic_bignum
[1] << 16);
3419 hi32
.X_op
= O_constant
;
3420 hi32
.X_add_number
= generic_bignum
[2] + (generic_bignum
[3] << 16);
3423 if (hi32
.X_add_number
== 0)
3428 unsigned long hi
, lo
;
3430 if (hi32
.X_add_number
== (offsetT
) 0xffffffff)
3432 if ((lo32
.X_add_number
& 0xffff8000) == 0xffff8000)
3434 macro_build ((char *) NULL
, counter
, &lo32
, "addiu", "t,r,j",
3435 reg
, 0, (int) BFD_RELOC_LO16
);
3438 if (lo32
.X_add_number
& 0x80000000)
3440 macro_build ((char *) NULL
, counter
, &lo32
, "lui", "t,u", reg
,
3441 (int) BFD_RELOC_HI16
);
3442 if (lo32
.X_add_number
& 0xffff)
3443 macro_build ((char *) NULL
, counter
, &lo32
, "ori", "t,r,i",
3444 reg
, reg
, (int) BFD_RELOC_LO16
);
3449 /* Check for 16bit shifted constant. We know that hi32 is
3450 non-zero, so start the mask on the first bit of the hi32
3455 unsigned long himask
, lomask
;
3459 himask
= 0xffff >> (32 - shift
);
3460 lomask
= (0xffff << shift
) & 0xffffffff;
3464 himask
= 0xffff << (shift
- 32);
3467 if ((hi32
.X_add_number
& ~(offsetT
) himask
) == 0
3468 && (lo32
.X_add_number
& ~(offsetT
) lomask
) == 0)
3472 tmp
.X_op
= O_constant
;
3474 tmp
.X_add_number
= ((hi32
.X_add_number
<< (32 - shift
))
3475 | (lo32
.X_add_number
>> shift
));
3477 tmp
.X_add_number
= hi32
.X_add_number
>> (shift
- 32);
3478 macro_build ((char *) NULL
, counter
, &tmp
,
3479 "ori", "t,r,i", reg
, 0,
3480 (int) BFD_RELOC_LO16
);
3481 macro_build ((char *) NULL
, counter
, (expressionS
*) NULL
,
3482 (shift
>= 32) ? "dsll32" : "dsll",
3484 (shift
>= 32) ? shift
- 32 : shift
);
3489 while (shift
<= (64 - 16));
3491 /* Find the bit number of the lowest one bit, and store the
3492 shifted value in hi/lo. */
3493 hi
= (unsigned long) (hi32
.X_add_number
& 0xffffffff);
3494 lo
= (unsigned long) (lo32
.X_add_number
& 0xffffffff);
3498 while ((lo
& 1) == 0)
3503 lo
|= (hi
& (((unsigned long) 1 << bit
) - 1)) << (32 - bit
);
3509 while ((hi
& 1) == 0)
3518 /* Optimize if the shifted value is a (power of 2) - 1. */
3519 if ((hi
== 0 && ((lo
+ 1) & lo
) == 0)
3520 || (lo
== 0xffffffff && ((hi
+ 1) & hi
) == 0))
3522 shift
= COUNT_TOP_ZEROES ((unsigned int) hi32
.X_add_number
);
3527 /* This instruction will set the register to be all
3529 tmp
.X_op
= O_constant
;
3530 tmp
.X_add_number
= (offsetT
) -1;
3531 macro_build ((char *) NULL
, counter
, &tmp
, "addiu", "t,r,j",
3532 reg
, 0, (int) BFD_RELOC_LO16
);
3536 macro_build ((char *) NULL
, counter
, (expressionS
*) NULL
,
3537 (bit
>= 32) ? "dsll32" : "dsll",
3539 (bit
>= 32) ? bit
- 32 : bit
);
3541 macro_build ((char *) NULL
, counter
, (expressionS
*) NULL
,
3542 (shift
>= 32) ? "dsrl32" : "dsrl",
3544 (shift
>= 32) ? shift
- 32 : shift
);
3549 /* Sign extend hi32 before calling load_register, because we can
3550 generally get better code when we load a sign extended value. */
3551 if ((hi32
.X_add_number
& 0x80000000) != 0)
3552 hi32
.X_add_number
|= ~(offsetT
) 0xffffffff;
3553 load_register (counter
, reg
, &hi32
, 0);
3556 if ((lo32
.X_add_number
& 0xffff0000) == 0)
3560 macro_build ((char *) NULL
, counter
, (expressionS
*) NULL
,
3561 "dsll32", "d,w,<", reg
, freg
, 0);
3569 if ((freg
== 0) && (lo32
.X_add_number
== (offsetT
) 0xffffffff))
3571 macro_build ((char *) NULL
, counter
, &lo32
, "lui", "t,u", reg
,
3572 (int) BFD_RELOC_HI16
);
3573 macro_build ((char *) NULL
, counter
, (expressionS
*) NULL
,
3574 "dsrl32", "d,w,<", reg
, reg
, 0);
3580 macro_build ((char *) NULL
, counter
, (expressionS
*) NULL
, "dsll",
3581 "d,w,<", reg
, freg
, 16);
3585 mid16
.X_add_number
>>= 16;
3586 macro_build ((char *) NULL
, counter
, &mid16
, "ori", "t,r,i", reg
,
3587 freg
, (int) BFD_RELOC_LO16
);
3588 macro_build ((char *) NULL
, counter
, (expressionS
*) NULL
, "dsll",
3589 "d,w,<", reg
, reg
, 16);
3592 if ((lo32
.X_add_number
& 0xffff) != 0)
3593 macro_build ((char *) NULL
, counter
, &lo32
, "ori", "t,r,i", reg
, freg
,
3594 (int) BFD_RELOC_LO16
);
3597 /* Load an address into a register. */
3600 load_address (counter
, reg
, ep
, used_at
)
3608 if (ep
->X_op
!= O_constant
3609 && ep
->X_op
!= O_symbol
)
3611 as_bad (_("expression too complex"));
3612 ep
->X_op
= O_constant
;
3615 if (ep
->X_op
== O_constant
)
3617 load_register (counter
, reg
, ep
, HAVE_64BIT_ADDRESSES
);
3621 if (mips_pic
== NO_PIC
)
3623 /* If this is a reference to a GP relative symbol, we want
3624 addiu $reg,$gp,<sym> (BFD_RELOC_GPREL16)
3626 lui $reg,<sym> (BFD_RELOC_HI16_S)
3627 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
3628 If we have an addend, we always use the latter form.
3630 With 64bit address space and a usable $at we want
3631 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
3632 lui $at,<sym> (BFD_RELOC_HI16_S)
3633 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
3634 daddiu $at,<sym> (BFD_RELOC_LO16)
3638 If $at is already in use, we use an path which is suboptimal
3639 on superscalar processors.
3640 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
3641 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
3643 daddiu $reg,<sym> (BFD_RELOC_HI16_S)
3645 daddiu $reg,<sym> (BFD_RELOC_LO16)
3647 if (HAVE_64BIT_ADDRESSES
)
3649 /* We don't do GP optimization for now because RELAX_ENCODE can't
3650 hold the data for such large chunks. */
3652 if (*used_at
== 0 && ! mips_opts
.noat
)
3654 macro_build (p
, counter
, ep
, "lui", "t,u",
3655 reg
, (int) BFD_RELOC_MIPS_HIGHEST
);
3656 macro_build (p
, counter
, ep
, "lui", "t,u",
3657 AT
, (int) BFD_RELOC_HI16_S
);
3658 macro_build (p
, counter
, ep
, "daddiu", "t,r,j",
3659 reg
, reg
, (int) BFD_RELOC_MIPS_HIGHER
);
3660 macro_build (p
, counter
, ep
, "daddiu", "t,r,j",
3661 AT
, AT
, (int) BFD_RELOC_LO16
);
3662 macro_build (p
, counter
, (expressionS
*) NULL
, "dsll32",
3663 "d,w,<", reg
, reg
, 0);
3664 macro_build (p
, counter
, (expressionS
*) NULL
, "daddu",
3665 "d,v,t", reg
, reg
, AT
);
3670 macro_build (p
, counter
, ep
, "lui", "t,u",
3671 reg
, (int) BFD_RELOC_MIPS_HIGHEST
);
3672 macro_build (p
, counter
, ep
, "daddiu", "t,r,j",
3673 reg
, reg
, (int) BFD_RELOC_MIPS_HIGHER
);
3674 macro_build (p
, counter
, (expressionS
*) NULL
, "dsll",
3675 "d,w,<", reg
, reg
, 16);
3676 macro_build (p
, counter
, ep
, "daddiu", "t,r,j",
3677 reg
, reg
, (int) BFD_RELOC_HI16_S
);
3678 macro_build (p
, counter
, (expressionS
*) NULL
, "dsll",
3679 "d,w,<", reg
, reg
, 16);
3680 macro_build (p
, counter
, ep
, "daddiu", "t,r,j",
3681 reg
, reg
, (int) BFD_RELOC_LO16
);
3686 if ((valueT
) ep
->X_add_number
<= MAX_GPREL_OFFSET
3687 && ! nopic_need_relax (ep
->X_add_symbol
, 1))
3690 macro_build ((char *) NULL
, counter
, ep
,
3691 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu", "t,r,j",
3692 reg
, mips_gp_register
, (int) BFD_RELOC_GPREL16
);
3693 p
= frag_var (rs_machine_dependent
, 8, 0,
3694 RELAX_ENCODE (4, 8, 0, 4, 0,
3695 mips_opts
.warn_about_macros
),
3696 ep
->X_add_symbol
, 0, NULL
);
3698 macro_build_lui (p
, counter
, ep
, reg
);
3701 macro_build (p
, counter
, ep
,
3702 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
3703 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
3706 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
3710 /* If this is a reference to an external symbol, we want
3711 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3713 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3715 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
3716 If we have NewABI, we want
3717 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
3718 If there is a constant, it must be added in after. */
3719 ex
.X_add_number
= ep
->X_add_number
;
3720 ep
->X_add_number
= 0;
3724 macro_build ((char *) NULL
, counter
, ep
,
3725 HAVE_32BIT_ADDRESSES
? "lw" : "ld", "t,o(b)", reg
,
3726 (int) BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
3730 macro_build ((char *) NULL
, counter
, ep
,
3731 HAVE_32BIT_ADDRESSES
? "lw" : "ld", "t,o(b)",
3732 reg
, (int) BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
3733 macro_build ((char *) NULL
, counter
, (expressionS
*) NULL
, "nop", "");
3734 p
= frag_var (rs_machine_dependent
, 4, 0,
3735 RELAX_ENCODE (0, 4, -8, 0, 0, mips_opts
.warn_about_macros
),
3736 ep
->X_add_symbol
, (offsetT
) 0, (char *) NULL
);
3737 macro_build (p
, counter
, ep
,
3738 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
3739 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
3742 if (ex
.X_add_number
!= 0)
3744 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
3745 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
3746 ex
.X_op
= O_constant
;
3747 macro_build ((char *) NULL
, counter
, &ex
,
3748 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
3749 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
3752 else if (mips_pic
== SVR4_PIC
)
3757 /* This is the large GOT case. If this is a reference to an
3758 external symbol, we want
3759 lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
3761 lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16)
3762 Otherwise, for a reference to a local symbol, we want
3763 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3765 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
3766 If we have NewABI, we want
3767 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
3768 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
3769 If there is a constant, it must be added in after. */
3770 ex
.X_add_number
= ep
->X_add_number
;
3771 ep
->X_add_number
= 0;
3774 macro_build ((char *) NULL
, counter
, ep
,
3775 HAVE_32BIT_ADDRESSES
? "lw" : "ld", "t,o(b)", reg
,
3776 (int) BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
3777 macro_build (p
, counter
, ep
,
3778 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu", "t,r,j",
3779 reg
, reg
, (int) BFD_RELOC_MIPS_GOT_OFST
);
3783 if (reg_needs_delay (mips_gp_register
))
3788 macro_build ((char *) NULL
, counter
, ep
, "lui", "t,u", reg
,
3789 (int) BFD_RELOC_MIPS_GOT_HI16
);
3790 macro_build ((char *) NULL
, counter
, (expressionS
*) NULL
,
3791 HAVE_32BIT_ADDRESSES
? "addu" : "daddu", "d,v,t", reg
,
3792 reg
, mips_gp_register
);
3793 macro_build ((char *) NULL
, counter
, ep
,
3794 HAVE_32BIT_ADDRESSES
? "lw" : "ld",
3795 "t,o(b)", reg
, (int) BFD_RELOC_MIPS_GOT_LO16
, reg
);
3796 p
= frag_var (rs_machine_dependent
, 12 + off
, 0,
3797 RELAX_ENCODE (12, 12 + off
, off
, 8 + off
, 0,
3798 mips_opts
.warn_about_macros
),
3799 ep
->X_add_symbol
, 0, NULL
);
3802 /* We need a nop before loading from $gp. This special
3803 check is required because the lui which starts the main
3804 instruction stream does not refer to $gp, and so will not
3805 insert the nop which may be required. */
3806 macro_build (p
, counter
, (expressionS
*) NULL
, "nop", "");
3809 macro_build (p
, counter
, ep
,
3810 HAVE_32BIT_ADDRESSES
? "lw" : "ld", "t,o(b)", reg
,
3811 (int) BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
3813 macro_build (p
, counter
, (expressionS
*) NULL
, "nop", "");
3815 macro_build (p
, counter
, ep
,
3816 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
3817 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
3820 if (ex
.X_add_number
!= 0)
3822 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
3823 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
3824 ex
.X_op
= O_constant
;
3825 macro_build ((char *) NULL
, counter
, &ex
,
3826 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
3827 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
3830 else if (mips_pic
== EMBEDDED_PIC
)
3833 addiu $reg,$gp,<sym> (BFD_RELOC_GPREL16)
3835 macro_build ((char *) NULL
, counter
, ep
,
3836 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
3837 "t,r,j", reg
, mips_gp_register
, (int) BFD_RELOC_GPREL16
);
3843 /* Move the contents of register SOURCE into register DEST. */
3846 move_register (counter
, dest
, source
)
3851 macro_build ((char *) NULL
, counter
, (expressionS
*) NULL
,
3852 HAVE_32BIT_GPRS
? "addu" : "daddu",
3853 "d,v,t", dest
, source
, 0);
3858 * This routine implements the seemingly endless macro or synthesized
3859 * instructions and addressing modes in the mips assembly language. Many
3860 * of these macros are simple and are similar to each other. These could
3861 * probably be handled by some kind of table or grammer aproach instead of
3862 * this verbose method. Others are not simple macros but are more like
3863 * optimizing code generation.
3864 * One interesting optimization is when several store macros appear
3865 * consecutivly that would load AT with the upper half of the same address.
3866 * The ensuing load upper instructions are ommited. This implies some kind
3867 * of global optimization. We currently only optimize within a single macro.
3868 * For many of the load and store macros if the address is specified as a
3869 * constant expression in the first 64k of memory (ie ld $2,0x4000c) we
3870 * first load register 'at' with zero and use it as the base register. The
3871 * mips assembler simply uses register $zero. Just one tiny optimization
3876 struct mips_cl_insn
*ip
;
3878 register int treg
, sreg
, dreg
, breg
;
3894 bfd_reloc_code_real_type r
;
3895 int hold_mips_optimize
;
3897 assert (! mips_opts
.mips16
);
3899 treg
= (ip
->insn_opcode
>> 16) & 0x1f;
3900 dreg
= (ip
->insn_opcode
>> 11) & 0x1f;
3901 sreg
= breg
= (ip
->insn_opcode
>> 21) & 0x1f;
3902 mask
= ip
->insn_mo
->mask
;
3904 expr1
.X_op
= O_constant
;
3905 expr1
.X_op_symbol
= NULL
;
3906 expr1
.X_add_symbol
= NULL
;
3907 expr1
.X_add_number
= 1;
3919 mips_emit_delays (true);
3920 ++mips_opts
.noreorder
;
3921 mips_any_noreorder
= 1;
3923 expr1
.X_add_number
= 8;
3924 macro_build ((char *) NULL
, &icnt
, &expr1
, "bgez", "s,p", sreg
);
3926 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "",
3929 move_register (&icnt
, dreg
, sreg
);
3930 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3931 dbl
? "dsub" : "sub", "d,v,t", dreg
, 0, sreg
);
3933 --mips_opts
.noreorder
;
3954 if (imm_expr
.X_op
== O_constant
3955 && imm_expr
.X_add_number
>= -0x8000
3956 && imm_expr
.X_add_number
< 0x8000)
3958 macro_build ((char *) NULL
, &icnt
, &imm_expr
, s
, "t,r,j", treg
, sreg
,
3959 (int) BFD_RELOC_LO16
);
3962 load_register (&icnt
, AT
, &imm_expr
, dbl
);
3963 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s2
, "d,v,t",
3983 if (imm_expr
.X_op
== O_constant
3984 && imm_expr
.X_add_number
>= 0
3985 && imm_expr
.X_add_number
< 0x10000)
3987 if (mask
!= M_NOR_I
)
3988 macro_build ((char *) NULL
, &icnt
, &imm_expr
, s
, "t,r,i", treg
,
3989 sreg
, (int) BFD_RELOC_LO16
);
3992 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "ori", "t,r,i",
3993 treg
, sreg
, (int) BFD_RELOC_LO16
);
3994 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nor",
3995 "d,v,t", treg
, treg
, 0);
4000 load_register (&icnt
, AT
, &imm_expr
, HAVE_64BIT_GPRS
);
4001 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s2
, "d,v,t",
4019 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
4021 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "s,t,p", sreg
,
4025 load_register (&icnt
, AT
, &imm_expr
, HAVE_64BIT_GPRS
);
4026 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "s,t,p", sreg
, AT
);
4034 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4035 likely
? "bgezl" : "bgez", "s,p", sreg
);
4040 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4041 likely
? "blezl" : "blez", "s,p", treg
);
4044 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "slt", "d,v,t",
4046 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4047 likely
? "beql" : "beq", "s,t,p", AT
, 0);
4053 /* check for > max integer */
4054 maxnum
= 0x7fffffff;
4055 if (HAVE_64BIT_GPRS
&& sizeof (maxnum
) > 4)
4062 if (imm_expr
.X_op
== O_constant
4063 && imm_expr
.X_add_number
>= maxnum
4064 && (HAVE_32BIT_GPRS
|| sizeof (maxnum
) > 4))
4067 /* result is always false */
4071 as_warn (_("Branch %s is always false (nop)"),
4073 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop",
4079 as_warn (_("Branch likely %s is always false"),
4081 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "bnel",
4086 if (imm_expr
.X_op
!= O_constant
)
4087 as_bad (_("Unsupported large constant"));
4088 ++imm_expr
.X_add_number
;
4092 if (mask
== M_BGEL_I
)
4094 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
4096 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4097 likely
? "bgezl" : "bgez", "s,p", sreg
);
4100 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
4102 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4103 likely
? "bgtzl" : "bgtz", "s,p", sreg
);
4106 maxnum
= 0x7fffffff;
4107 if (HAVE_64BIT_GPRS
&& sizeof (maxnum
) > 4)
4114 maxnum
= - maxnum
- 1;
4115 if (imm_expr
.X_op
== O_constant
4116 && imm_expr
.X_add_number
<= maxnum
4117 && (HAVE_32BIT_GPRS
|| sizeof (maxnum
) > 4))
4120 /* result is always true */
4121 as_warn (_("Branch %s is always true"), ip
->insn_mo
->name
);
4122 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "b", "p");
4125 set_at (&icnt
, sreg
, 0);
4126 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4127 likely
? "beql" : "beq", "s,t,p", AT
, 0);
4137 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4138 likely
? "beql" : "beq", "s,t,p", 0, treg
);
4141 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "sltu",
4142 "d,v,t", AT
, sreg
, treg
);
4143 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4144 likely
? "beql" : "beq", "s,t,p", AT
, 0);
4152 && imm_expr
.X_op
== O_constant
4153 && imm_expr
.X_add_number
== (offsetT
) 0xffffffff))
4155 if (imm_expr
.X_op
!= O_constant
)
4156 as_bad (_("Unsupported large constant"));
4157 ++imm_expr
.X_add_number
;
4161 if (mask
== M_BGEUL_I
)
4163 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
4165 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
4167 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4168 likely
? "bnel" : "bne", "s,t,p", sreg
, 0);
4171 set_at (&icnt
, sreg
, 1);
4172 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4173 likely
? "beql" : "beq", "s,t,p", AT
, 0);
4181 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4182 likely
? "bgtzl" : "bgtz", "s,p", sreg
);
4187 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4188 likely
? "bltzl" : "bltz", "s,p", treg
);
4191 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "slt", "d,v,t",
4193 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4194 likely
? "bnel" : "bne", "s,t,p", AT
, 0);
4202 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4203 likely
? "bnel" : "bne", "s,t,p", sreg
, 0);
4208 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "sltu",
4209 "d,v,t", AT
, treg
, sreg
);
4210 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4211 likely
? "bnel" : "bne", "s,t,p", AT
, 0);
4219 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4220 likely
? "blezl" : "blez", "s,p", sreg
);
4225 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4226 likely
? "bgezl" : "bgez", "s,p", treg
);
4229 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "slt", "d,v,t",
4231 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4232 likely
? "beql" : "beq", "s,t,p", AT
, 0);
4238 maxnum
= 0x7fffffff;
4239 if (HAVE_64BIT_GPRS
&& sizeof (maxnum
) > 4)
4246 if (imm_expr
.X_op
== O_constant
4247 && imm_expr
.X_add_number
>= maxnum
4248 && (HAVE_32BIT_GPRS
|| sizeof (maxnum
) > 4))
4250 if (imm_expr
.X_op
!= O_constant
)
4251 as_bad (_("Unsupported large constant"));
4252 ++imm_expr
.X_add_number
;
4256 if (mask
== M_BLTL_I
)
4258 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
4260 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4261 likely
? "bltzl" : "bltz", "s,p", sreg
);
4264 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
4266 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4267 likely
? "blezl" : "blez", "s,p", sreg
);
4270 set_at (&icnt
, sreg
, 0);
4271 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4272 likely
? "bnel" : "bne", "s,t,p", AT
, 0);
4280 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4281 likely
? "beql" : "beq", "s,t,p", sreg
, 0);
4286 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "sltu",
4287 "d,v,t", AT
, treg
, sreg
);
4288 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4289 likely
? "beql" : "beq", "s,t,p", AT
, 0);
4297 && imm_expr
.X_op
== O_constant
4298 && imm_expr
.X_add_number
== (offsetT
) 0xffffffff))
4300 if (imm_expr
.X_op
!= O_constant
)
4301 as_bad (_("Unsupported large constant"));
4302 ++imm_expr
.X_add_number
;
4306 if (mask
== M_BLTUL_I
)
4308 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
4310 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
4312 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4313 likely
? "beql" : "beq",
4317 set_at (&icnt
, sreg
, 1);
4318 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4319 likely
? "bnel" : "bne", "s,t,p", AT
, 0);
4327 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4328 likely
? "bltzl" : "bltz", "s,p", sreg
);
4333 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4334 likely
? "bgtzl" : "bgtz", "s,p", treg
);
4337 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "slt", "d,v,t",
4339 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4340 likely
? "bnel" : "bne", "s,t,p", AT
, 0);
4350 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4351 likely
? "bnel" : "bne", "s,t,p", 0, treg
);
4354 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "sltu",
4357 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4358 likely
? "bnel" : "bne", "s,t,p", AT
, 0);
4373 as_warn (_("Divide by zero."));
4375 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "teq",
4378 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "break",
4383 mips_emit_delays (true);
4384 ++mips_opts
.noreorder
;
4385 mips_any_noreorder
= 1;
4388 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "teq",
4389 "s,t,q", treg
, 0, 7);
4390 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4391 dbl
? "ddiv" : "div", "z,s,t", sreg
, treg
);
4395 expr1
.X_add_number
= 8;
4396 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", treg
, 0);
4397 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4398 dbl
? "ddiv" : "div", "z,s,t", sreg
, treg
);
4399 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "break",
4402 expr1
.X_add_number
= -1;
4403 macro_build ((char *) NULL
, &icnt
, &expr1
,
4404 dbl
? "daddiu" : "addiu",
4405 "t,r,j", AT
, 0, (int) BFD_RELOC_LO16
);
4406 expr1
.X_add_number
= mips_trap
? (dbl
? 12 : 8) : (dbl
? 20 : 16);
4407 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", treg
, AT
);
4410 expr1
.X_add_number
= 1;
4411 macro_build ((char *) NULL
, &icnt
, &expr1
, "daddiu", "t,r,j", AT
, 0,
4412 (int) BFD_RELOC_LO16
);
4413 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "dsll32",
4414 "d,w,<", AT
, AT
, 31);
4418 expr1
.X_add_number
= 0x80000000;
4419 macro_build ((char *) NULL
, &icnt
, &expr1
, "lui", "t,u", AT
,
4420 (int) BFD_RELOC_HI16
);
4424 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "teq",
4425 "s,t,q", sreg
, AT
, 6);
4426 /* We want to close the noreorder block as soon as possible, so
4427 that later insns are available for delay slot filling. */
4428 --mips_opts
.noreorder
;
4432 expr1
.X_add_number
= 8;
4433 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", sreg
, AT
);
4434 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "",
4437 /* We want to close the noreorder block as soon as possible, so
4438 that later insns are available for delay slot filling. */
4439 --mips_opts
.noreorder
;
4441 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "break",
4444 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s
, "d", dreg
);
4483 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
4485 as_warn (_("Divide by zero."));
4487 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "teq",
4490 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "break",
4494 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
4496 if (strcmp (s2
, "mflo") == 0)
4497 move_register (&icnt
, dreg
, sreg
);
4499 move_register (&icnt
, dreg
, 0);
4502 if (imm_expr
.X_op
== O_constant
4503 && imm_expr
.X_add_number
== -1
4504 && s
[strlen (s
) - 1] != 'u')
4506 if (strcmp (s2
, "mflo") == 0)
4508 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4509 dbl
? "dneg" : "neg", "d,w", dreg
, sreg
);
4512 move_register (&icnt
, dreg
, 0);
4516 load_register (&icnt
, AT
, &imm_expr
, dbl
);
4517 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s
, "z,s,t",
4519 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s2
, "d", dreg
);
4538 mips_emit_delays (true);
4539 ++mips_opts
.noreorder
;
4540 mips_any_noreorder
= 1;
4543 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "teq",
4544 "s,t,q", treg
, 0, 7);
4545 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s
, "z,s,t",
4547 /* We want to close the noreorder block as soon as possible, so
4548 that later insns are available for delay slot filling. */
4549 --mips_opts
.noreorder
;
4553 expr1
.X_add_number
= 8;
4554 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", treg
, 0);
4555 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s
, "z,s,t",
4558 /* We want to close the noreorder block as soon as possible, so
4559 that later insns are available for delay slot filling. */
4560 --mips_opts
.noreorder
;
4561 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "break",
4564 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s2
, "d", dreg
);
4570 /* Load the address of a symbol into a register. If breg is not
4571 zero, we then add a base register to it. */
4573 if (dbl
&& HAVE_32BIT_GPRS
)
4574 as_warn (_("dla used to load 32-bit register"));
4576 if (! dbl
&& HAVE_64BIT_OBJECTS
)
4577 as_warn (_("la used to load 64-bit address"));
4579 if (offset_expr
.X_op
== O_constant
4580 && offset_expr
.X_add_number
>= -0x8000
4581 && offset_expr
.X_add_number
< 0x8000)
4583 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4584 (dbl
|| HAVE_64BIT_ADDRESSES
) ? "daddiu" : "addiu",
4585 "t,r,j", treg
, sreg
, (int) BFD_RELOC_LO16
);
4600 /* When generating embedded PIC code, we permit expressions of
4603 la $treg,foo-bar($breg)
4604 where bar is an address in the current section. These are used
4605 when getting the addresses of functions. We don't permit
4606 X_add_number to be non-zero, because if the symbol is
4607 external the relaxing code needs to know that any addend is
4608 purely the offset to X_op_symbol. */
4609 if (mips_pic
== EMBEDDED_PIC
4610 && offset_expr
.X_op
== O_subtract
4611 && (symbol_constant_p (offset_expr
.X_op_symbol
)
4612 ? S_GET_SEGMENT (offset_expr
.X_op_symbol
) == now_seg
4613 : (symbol_equated_p (offset_expr
.X_op_symbol
)
4615 (symbol_get_value_expression (offset_expr
.X_op_symbol
)
4618 && (offset_expr
.X_add_number
== 0
4619 || OUTPUT_FLAVOR
== bfd_target_elf_flavour
))
4625 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
4626 tempreg
, (int) BFD_RELOC_PCREL_HI16_S
);
4630 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
4631 tempreg
, (int) BFD_RELOC_PCREL_HI16_S
);
4632 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4633 (dbl
|| HAVE_64BIT_ADDRESSES
) ? "daddu" : "addu",
4634 "d,v,t", tempreg
, tempreg
, breg
);
4636 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4637 (dbl
|| HAVE_64BIT_ADDRESSES
) ? "daddiu" : "addiu",
4638 "t,r,j", treg
, tempreg
, (int) BFD_RELOC_PCREL_LO16
);
4644 if (offset_expr
.X_op
!= O_symbol
4645 && offset_expr
.X_op
!= O_constant
)
4647 as_bad (_("expression too complex"));
4648 offset_expr
.X_op
= O_constant
;
4651 if (offset_expr
.X_op
== O_constant
)
4652 load_register (&icnt
, tempreg
, &offset_expr
,
4653 ((mips_pic
== EMBEDDED_PIC
|| mips_pic
== NO_PIC
)
4654 ? (dbl
|| HAVE_64BIT_ADDRESSES
)
4655 : HAVE_64BIT_ADDRESSES
));
4656 else if (mips_pic
== NO_PIC
)
4658 /* If this is a reference to a GP relative symbol, we want
4659 addiu $tempreg,$gp,<sym> (BFD_RELOC_GPREL16)
4661 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
4662 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
4663 If we have a constant, we need two instructions anyhow,
4664 so we may as well always use the latter form.
4666 With 64bit address space and a usable $at we want
4667 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
4668 lui $at,<sym> (BFD_RELOC_HI16_S)
4669 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
4670 daddiu $at,<sym> (BFD_RELOC_LO16)
4672 daddu $tempreg,$tempreg,$at
4674 If $at is already in use, we use an path which is suboptimal
4675 on superscalar processors.
4676 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
4677 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
4679 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
4681 daddiu $tempreg,<sym> (BFD_RELOC_LO16)
4684 if (HAVE_64BIT_ADDRESSES
)
4686 /* We don't do GP optimization for now because RELAX_ENCODE can't
4687 hold the data for such large chunks. */
4689 if (used_at
== 0 && ! mips_opts
.noat
)
4691 macro_build (p
, &icnt
, &offset_expr
, "lui", "t,u",
4692 tempreg
, (int) BFD_RELOC_MIPS_HIGHEST
);
4693 macro_build (p
, &icnt
, &offset_expr
, "lui", "t,u",
4694 AT
, (int) BFD_RELOC_HI16_S
);
4695 macro_build (p
, &icnt
, &offset_expr
, "daddiu", "t,r,j",
4696 tempreg
, tempreg
, (int) BFD_RELOC_MIPS_HIGHER
);
4697 macro_build (p
, &icnt
, &offset_expr
, "daddiu", "t,r,j",
4698 AT
, AT
, (int) BFD_RELOC_LO16
);
4699 macro_build (p
, &icnt
, (expressionS
*) NULL
, "dsll32",
4700 "d,w,<", tempreg
, tempreg
, 0);
4701 macro_build (p
, &icnt
, (expressionS
*) NULL
, "daddu",
4702 "d,v,t", tempreg
, tempreg
, AT
);
4707 macro_build (p
, &icnt
, &offset_expr
, "lui", "t,u",
4708 tempreg
, (int) BFD_RELOC_MIPS_HIGHEST
);
4709 macro_build (p
, &icnt
, &offset_expr
, "daddiu", "t,r,j",
4710 tempreg
, tempreg
, (int) BFD_RELOC_MIPS_HIGHER
);
4711 macro_build (p
, &icnt
, (expressionS
*) NULL
, "dsll", "d,w,<",
4712 tempreg
, tempreg
, 16);
4713 macro_build (p
, &icnt
, &offset_expr
, "daddiu", "t,r,j",
4714 tempreg
, tempreg
, (int) BFD_RELOC_HI16_S
);
4715 macro_build (p
, &icnt
, (expressionS
*) NULL
, "dsll", "d,w,<",
4716 tempreg
, tempreg
, 16);
4717 macro_build (p
, &icnt
, &offset_expr
, "daddiu", "t,r,j",
4718 tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
4723 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
4724 && ! nopic_need_relax (offset_expr
.X_add_symbol
, 1))
4727 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "addiu",
4728 "t,r,j", tempreg
, mips_gp_register
,
4729 (int) BFD_RELOC_GPREL16
);
4730 p
= frag_var (rs_machine_dependent
, 8, 0,
4731 RELAX_ENCODE (4, 8, 0, 4, 0,
4732 mips_opts
.warn_about_macros
),
4733 offset_expr
.X_add_symbol
, 0, NULL
);
4735 macro_build_lui (p
, &icnt
, &offset_expr
, tempreg
);
4738 macro_build (p
, &icnt
, &offset_expr
, "addiu",
4739 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
4742 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
4744 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT16
;
4746 /* If this is a reference to an external symbol, and there
4747 is no constant, we want
4748 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4749 or if tempreg is PIC_CALL_REG
4750 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
4751 For a local symbol, we want
4752 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4754 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
4756 If we have a small constant, and this is a reference to
4757 an external symbol, we want
4758 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4760 addiu $tempreg,$tempreg,<constant>
4761 For a local symbol, we want the same instruction
4762 sequence, but we output a BFD_RELOC_LO16 reloc on the
4765 If we have a large constant, and this is a reference to
4766 an external symbol, we want
4767 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4768 lui $at,<hiconstant>
4769 addiu $at,$at,<loconstant>
4770 addu $tempreg,$tempreg,$at
4771 For a local symbol, we want the same instruction
4772 sequence, but we output a BFD_RELOC_LO16 reloc on the
4775 For NewABI, we want for local or external data addresses
4776 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
4777 For a local function symbol, we want
4778 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
4780 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
4783 expr1
.X_add_number
= offset_expr
.X_add_number
;
4784 offset_expr
.X_add_number
= 0;
4786 if (expr1
.X_add_number
== 0 && tempreg
== PIC_CALL_REG
)
4787 lw_reloc_type
= (int) BFD_RELOC_MIPS_CALL16
;
4788 else if (HAVE_NEWABI
)
4789 lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT_DISP
;
4790 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4791 HAVE_32BIT_ADDRESSES
? "lw" : "ld",
4792 "t,o(b)", tempreg
, lw_reloc_type
, mips_gp_register
);
4793 if (expr1
.X_add_number
== 0)
4802 /* We're going to put in an addu instruction using
4803 tempreg, so we may as well insert the nop right
4805 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4809 p
= frag_var (rs_machine_dependent
, 8 - off
, 0,
4810 RELAX_ENCODE (0, 8 - off
, -4 - off
, 4 - off
, 0,
4812 ? mips_opts
.warn_about_macros
4814 offset_expr
.X_add_symbol
, 0, NULL
);
4817 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4820 macro_build (p
, &icnt
, &expr1
,
4821 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
4822 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
4823 /* FIXME: If breg == 0, and the next instruction uses
4824 $tempreg, then if this variant case is used an extra
4825 nop will be generated. */
4827 else if (expr1
.X_add_number
>= -0x8000
4828 && expr1
.X_add_number
< 0x8000)
4830 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4832 macro_build ((char *) NULL
, &icnt
, &expr1
,
4833 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
4834 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
4835 frag_var (rs_machine_dependent
, 0, 0,
4836 RELAX_ENCODE (0, 0, -12, -4, 0, 0),
4837 offset_expr
.X_add_symbol
, 0, NULL
);
4843 /* If we are going to add in a base register, and the
4844 target register and the base register are the same,
4845 then we are using AT as a temporary register. Since
4846 we want to load the constant into AT, we add our
4847 current AT (from the global offset table) and the
4848 register into the register now, and pretend we were
4849 not using a base register. */
4854 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4856 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4857 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
4858 "d,v,t", treg
, AT
, breg
);
4864 /* Set mips_optimize around the lui instruction to avoid
4865 inserting an unnecessary nop after the lw. */
4866 hold_mips_optimize
= mips_optimize
;
4868 macro_build_lui (NULL
, &icnt
, &expr1
, AT
);
4869 mips_optimize
= hold_mips_optimize
;
4871 macro_build ((char *) NULL
, &icnt
, &expr1
,
4872 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
4873 "t,r,j", AT
, AT
, (int) BFD_RELOC_LO16
);
4874 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4875 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
4876 "d,v,t", tempreg
, tempreg
, AT
);
4877 frag_var (rs_machine_dependent
, 0, 0,
4878 RELAX_ENCODE (0, 0, -16 + off1
, -8, 0, 0),
4879 offset_expr
.X_add_symbol
, 0, NULL
);
4883 else if (mips_pic
== SVR4_PIC
)
4887 int lui_reloc_type
= (int) BFD_RELOC_MIPS_GOT_HI16
;
4888 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT_LO16
;
4889 int local_reloc_type
= (int) BFD_RELOC_MIPS_GOT16
;
4891 /* This is the large GOT case. If this is a reference to an
4892 external symbol, and there is no constant, we want
4893 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
4894 addu $tempreg,$tempreg,$gp
4895 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
4896 or if tempreg is PIC_CALL_REG
4897 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
4898 addu $tempreg,$tempreg,$gp
4899 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
4900 For a local symbol, we want
4901 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4903 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
4905 If we have a small constant, and this is a reference to
4906 an external symbol, we want
4907 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
4908 addu $tempreg,$tempreg,$gp
4909 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
4911 addiu $tempreg,$tempreg,<constant>
4912 For a local symbol, we want
4913 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4915 addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16)
4917 If we have a large constant, and this is a reference to
4918 an external symbol, we want
4919 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
4920 addu $tempreg,$tempreg,$gp
4921 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
4922 lui $at,<hiconstant>
4923 addiu $at,$at,<loconstant>
4924 addu $tempreg,$tempreg,$at
4925 For a local symbol, we want
4926 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4927 lui $at,<hiconstant>
4928 addiu $at,$at,<loconstant> (BFD_RELOC_LO16)
4929 addu $tempreg,$tempreg,$at
4931 For NewABI, we want for local data addresses
4932 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
4935 expr1
.X_add_number
= offset_expr
.X_add_number
;
4936 offset_expr
.X_add_number
= 0;
4938 if (reg_needs_delay (mips_gp_register
))
4942 if (expr1
.X_add_number
== 0 && tempreg
== PIC_CALL_REG
)
4944 lui_reloc_type
= (int) BFD_RELOC_MIPS_CALL_HI16
;
4945 lw_reloc_type
= (int) BFD_RELOC_MIPS_CALL_LO16
;
4947 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
4948 tempreg
, lui_reloc_type
);
4949 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4950 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
4951 "d,v,t", tempreg
, tempreg
, mips_gp_register
);
4952 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4953 HAVE_32BIT_ADDRESSES
? "lw" : "ld",
4954 "t,o(b)", tempreg
, lw_reloc_type
, tempreg
);
4955 if (expr1
.X_add_number
== 0)
4963 /* We're going to put in an addu instruction using
4964 tempreg, so we may as well insert the nop right
4966 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4971 p
= frag_var (rs_machine_dependent
, 12 + gpdel
, 0,
4972 RELAX_ENCODE (12 + off
, 12 + gpdel
, gpdel
,
4975 ? mips_opts
.warn_about_macros
4977 offset_expr
.X_add_symbol
, 0, NULL
);
4979 else if (expr1
.X_add_number
>= -0x8000
4980 && expr1
.X_add_number
< 0x8000)
4982 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4984 macro_build ((char *) NULL
, &icnt
, &expr1
,
4985 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
4986 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
4988 p
= frag_var (rs_machine_dependent
, 12 + gpdel
, 0,
4989 RELAX_ENCODE (20, 12 + gpdel
, gpdel
, 8 + gpdel
, 0,
4991 ? mips_opts
.warn_about_macros
4993 offset_expr
.X_add_symbol
, 0, NULL
);
4999 /* If we are going to add in a base register, and the
5000 target register and the base register are the same,
5001 then we are using AT as a temporary register. Since
5002 we want to load the constant into AT, we add our
5003 current AT (from the global offset table) and the
5004 register into the register now, and pretend we were
5005 not using a base register. */
5013 assert (tempreg
== AT
);
5014 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5016 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5017 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
5018 "d,v,t", treg
, AT
, breg
);
5023 /* Set mips_optimize around the lui instruction to avoid
5024 inserting an unnecessary nop after the lw. */
5025 hold_mips_optimize
= mips_optimize
;
5027 macro_build_lui (NULL
, &icnt
, &expr1
, AT
);
5028 mips_optimize
= hold_mips_optimize
;
5030 macro_build ((char *) NULL
, &icnt
, &expr1
,
5031 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
5032 "t,r,j", AT
, AT
, (int) BFD_RELOC_LO16
);
5033 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5034 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
5035 "d,v,t", dreg
, dreg
, AT
);
5037 p
= frag_var (rs_machine_dependent
, 16 + gpdel
+ adj
, 0,
5038 RELAX_ENCODE (24 + adj
, 16 + gpdel
+ adj
, gpdel
,
5041 ? mips_opts
.warn_about_macros
5043 offset_expr
.X_add_symbol
, 0, NULL
);
5050 /* This is needed because this instruction uses $gp, but
5051 the first instruction on the main stream does not. */
5052 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
5057 local_reloc_type
= (int) BFD_RELOC_MIPS_GOT_DISP
;
5058 macro_build (p
, &icnt
, &offset_expr
,
5059 HAVE_32BIT_ADDRESSES
? "lw" : "ld",
5064 if (expr1
.X_add_number
== 0 && HAVE_NEWABI
)
5066 /* BFD_RELOC_MIPS_GOT_DISP is sufficient for newabi */
5069 if (expr1
.X_add_number
>= -0x8000
5070 && expr1
.X_add_number
< 0x8000)
5072 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
5074 macro_build (p
, &icnt
, &expr1
,
5075 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
5076 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
5077 /* FIXME: If add_number is 0, and there was no base
5078 register, the external symbol case ended with a load,
5079 so if the symbol turns out to not be external, and
5080 the next instruction uses tempreg, an unnecessary nop
5081 will be inserted. */
5087 /* We must add in the base register now, as in the
5088 external symbol case. */
5089 assert (tempreg
== AT
);
5090 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
5092 macro_build (p
, &icnt
, (expressionS
*) NULL
,
5093 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
5094 "d,v,t", treg
, AT
, breg
);
5097 /* We set breg to 0 because we have arranged to add
5098 it in in both cases. */
5102 macro_build_lui (p
, &icnt
, &expr1
, AT
);
5104 macro_build (p
, &icnt
, &expr1
,
5105 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
5106 "t,r,j", AT
, AT
, (int) BFD_RELOC_LO16
);
5108 macro_build (p
, &icnt
, (expressionS
*) NULL
,
5109 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
5110 "d,v,t", tempreg
, tempreg
, AT
);
5114 else if (mips_pic
== EMBEDDED_PIC
)
5117 addiu $tempreg,$gp,<sym> (BFD_RELOC_GPREL16)
5119 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5120 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu", "t,r,j",
5121 tempreg
, mips_gp_register
, (int) BFD_RELOC_GPREL16
);
5130 if (mips_pic
== EMBEDDED_PIC
|| mips_pic
== NO_PIC
)
5131 s
= (dbl
|| HAVE_64BIT_ADDRESSES
) ? "daddu" : "addu";
5133 s
= HAVE_64BIT_ADDRESSES
? "daddu" : "addu";
5135 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s
,
5136 "d,v,t", treg
, tempreg
, breg
);
5145 /* The j instruction may not be used in PIC code, since it
5146 requires an absolute address. We convert it to a b
5148 if (mips_pic
== NO_PIC
)
5149 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "j", "a");
5151 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "b", "p");
5154 /* The jal instructions must be handled as macros because when
5155 generating PIC code they expand to multi-instruction
5156 sequences. Normally they are simple instructions. */
5161 if (mips_pic
== NO_PIC
5162 || mips_pic
== EMBEDDED_PIC
)
5163 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "jalr",
5165 else if (mips_pic
== SVR4_PIC
)
5167 if (sreg
!= PIC_CALL_REG
)
5168 as_warn (_("MIPS PIC call to register other than $25"));
5170 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "jalr",
5174 if (mips_cprestore_offset
< 0)
5175 as_warn (_("No .cprestore pseudo-op used in PIC code"));
5178 if (! mips_frame_reg_valid
)
5180 as_warn (_("No .frame pseudo-op used in PIC code"));
5181 /* Quiet this warning. */
5182 mips_frame_reg_valid
= 1;
5184 if (! mips_cprestore_valid
)
5186 as_warn (_("No .cprestore pseudo-op used in PIC code"));
5187 /* Quiet this warning. */
5188 mips_cprestore_valid
= 1;
5190 expr1
.X_add_number
= mips_cprestore_offset
;
5191 macro_build_ldst_constoffset ((char *) NULL
, &icnt
, &expr1
,
5192 HAVE_32BIT_ADDRESSES
? "lw" : "ld",
5193 mips_gp_register
, mips_frame_reg
);
5203 if (mips_pic
== NO_PIC
)
5204 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "jal", "a");
5205 else if (mips_pic
== SVR4_PIC
)
5209 /* If this is a reference to an external symbol, and we are
5210 using a small GOT, we want
5211 lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
5215 lw $gp,cprestore($sp)
5216 The cprestore value is set using the .cprestore
5217 pseudo-op. If we are using a big GOT, we want
5218 lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16)
5220 lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16)
5224 lw $gp,cprestore($sp)
5225 If the symbol is not external, we want
5226 lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5228 addiu $25,$25,<sym> (BFD_RELOC_LO16)
5231 lw $gp,cprestore($sp)
5233 lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
5234 jalr $ra,$25 (BFD_RELOC_MIPS_JALR)
5238 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5239 HAVE_32BIT_ADDRESSES
? "lw" : "ld",
5240 "t,o(b)", PIC_CALL_REG
,
5241 (int) BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
5242 macro_build_jalr (icnt
, &offset_expr
);
5249 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5250 HAVE_32BIT_ADDRESSES
? "lw" : "ld",
5251 "t,o(b)", PIC_CALL_REG
,
5252 (int) BFD_RELOC_MIPS_CALL16
, mips_gp_register
);
5253 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5255 p
= frag_var (rs_machine_dependent
, 4, 0,
5256 RELAX_ENCODE (0, 4, -8, 0, 0, 0),
5257 offset_expr
.X_add_symbol
, 0, NULL
);
5263 if (reg_needs_delay (mips_gp_register
))
5267 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui",
5268 "t,u", PIC_CALL_REG
,
5269 (int) BFD_RELOC_MIPS_CALL_HI16
);
5270 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5271 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
5272 "d,v,t", PIC_CALL_REG
, PIC_CALL_REG
,
5274 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5275 HAVE_32BIT_ADDRESSES
? "lw" : "ld",
5276 "t,o(b)", PIC_CALL_REG
,
5277 (int) BFD_RELOC_MIPS_CALL_LO16
, PIC_CALL_REG
);
5278 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5280 p
= frag_var (rs_machine_dependent
, 12 + gpdel
, 0,
5281 RELAX_ENCODE (16, 12 + gpdel
, gpdel
,
5283 offset_expr
.X_add_symbol
, 0, NULL
);
5286 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
5289 macro_build (p
, &icnt
, &offset_expr
,
5290 HAVE_32BIT_ADDRESSES
? "lw" : "ld",
5291 "t,o(b)", PIC_CALL_REG
,
5292 (int) BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
5294 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
5297 macro_build (p
, &icnt
, &offset_expr
,
5298 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
5299 "t,r,j", PIC_CALL_REG
, PIC_CALL_REG
,
5300 (int) BFD_RELOC_LO16
);
5301 macro_build_jalr (icnt
, &offset_expr
);
5303 if (mips_cprestore_offset
< 0)
5304 as_warn (_("No .cprestore pseudo-op used in PIC code"));
5307 if (! mips_frame_reg_valid
)
5309 as_warn (_("No .frame pseudo-op used in PIC code"));
5310 /* Quiet this warning. */
5311 mips_frame_reg_valid
= 1;
5313 if (! mips_cprestore_valid
)
5315 as_warn (_("No .cprestore pseudo-op used in PIC code"));
5316 /* Quiet this warning. */
5317 mips_cprestore_valid
= 1;
5319 if (mips_opts
.noreorder
)
5320 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5322 expr1
.X_add_number
= mips_cprestore_offset
;
5323 macro_build_ldst_constoffset ((char *) NULL
, &icnt
, &expr1
,
5324 HAVE_32BIT_ADDRESSES
? "lw" : "ld",
5325 mips_gp_register
, mips_frame_reg
);
5329 else if (mips_pic
== EMBEDDED_PIC
)
5331 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "bal", "p");
5332 /* The linker may expand the call to a longer sequence which
5333 uses $at, so we must break rather than return. */
5358 /* Itbl support may require additional care here. */
5363 /* Itbl support may require additional care here. */
5368 /* Itbl support may require additional care here. */
5373 /* Itbl support may require additional care here. */
5385 if (mips_arch
== CPU_R4650
)
5387 as_bad (_("opcode not supported on this processor"));
5391 /* Itbl support may require additional care here. */
5396 /* Itbl support may require additional care here. */
5401 /* Itbl support may require additional care here. */
5421 if (breg
== treg
|| coproc
|| lr
)
5443 /* Itbl support may require additional care here. */
5448 /* Itbl support may require additional care here. */
5453 /* Itbl support may require additional care here. */
5458 /* Itbl support may require additional care here. */
5474 if (mips_arch
== CPU_R4650
)
5476 as_bad (_("opcode not supported on this processor"));
5481 /* Itbl support may require additional care here. */
5485 /* Itbl support may require additional care here. */
5490 /* Itbl support may require additional care here. */
5502 /* Itbl support may require additional care here. */
5503 if (mask
== M_LWC1_AB
5504 || mask
== M_SWC1_AB
5505 || mask
== M_LDC1_AB
5506 || mask
== M_SDC1_AB
5515 /* For embedded PIC, we allow loads where the offset is calculated
5516 by subtracting a symbol in the current segment from an unknown
5517 symbol, relative to a base register, e.g.:
5518 <op> $treg, <sym>-<localsym>($breg)
5519 This is used by the compiler for switch statements. */
5520 if (mips_pic
== EMBEDDED_PIC
5521 && offset_expr
.X_op
== O_subtract
5522 && (symbol_constant_p (offset_expr
.X_op_symbol
)
5523 ? S_GET_SEGMENT (offset_expr
.X_op_symbol
) == now_seg
5524 : (symbol_equated_p (offset_expr
.X_op_symbol
)
5526 (symbol_get_value_expression (offset_expr
.X_op_symbol
)
5530 && (offset_expr
.X_add_number
== 0
5531 || OUTPUT_FLAVOR
== bfd_target_elf_flavour
))
5533 /* For this case, we output the instructions:
5534 lui $tempreg,<sym> (BFD_RELOC_PCREL_HI16_S)
5535 addiu $tempreg,$tempreg,$breg
5536 <op> $treg,<sym>($tempreg) (BFD_RELOC_PCREL_LO16)
5537 If the relocation would fit entirely in 16 bits, it would be
5539 <op> $treg,<sym>($breg) (BFD_RELOC_PCREL_LO16)
5540 instead, but that seems quite difficult. */
5541 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
5542 tempreg
, (int) BFD_RELOC_PCREL_HI16_S
);
5543 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5544 ((bfd_arch_bits_per_address (stdoutput
) == 32
5545 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5546 ? "addu" : "daddu"),
5547 "d,v,t", tempreg
, tempreg
, breg
);
5548 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
, treg
,
5549 (int) BFD_RELOC_PCREL_LO16
, tempreg
);
5555 if (offset_expr
.X_op
!= O_constant
5556 && offset_expr
.X_op
!= O_symbol
)
5558 as_bad (_("expression too complex"));
5559 offset_expr
.X_op
= O_constant
;
5562 /* A constant expression in PIC code can be handled just as it
5563 is in non PIC code. */
5564 if (mips_pic
== NO_PIC
5565 || offset_expr
.X_op
== O_constant
)
5569 /* If this is a reference to a GP relative symbol, and there
5570 is no base register, we want
5571 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
5572 Otherwise, if there is no base register, we want
5573 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
5574 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5575 If we have a constant, we need two instructions anyhow,
5576 so we always use the latter form.
5578 If we have a base register, and this is a reference to a
5579 GP relative symbol, we want
5580 addu $tempreg,$breg,$gp
5581 <op> $treg,<sym>($tempreg) (BFD_RELOC_GPREL16)
5583 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
5584 addu $tempreg,$tempreg,$breg
5585 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5586 With a constant we always use the latter case.
5588 With 64bit address space and no base register and $at usable,
5590 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5591 lui $at,<sym> (BFD_RELOC_HI16_S)
5592 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
5595 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5596 If we have a base register, we want
5597 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5598 lui $at,<sym> (BFD_RELOC_HI16_S)
5599 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
5603 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5605 Without $at we can't generate the optimal path for superscalar
5606 processors here since this would require two temporary registers.
5607 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5608 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
5610 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
5612 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5613 If we have a base register, we want
5614 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5615 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
5617 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
5619 daddu $tempreg,$tempreg,$breg
5620 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5622 If we have 64-bit addresses, as an optimization, for
5623 addresses which are 32-bit constants (e.g. kseg0/kseg1
5624 addresses) we fall back to the 32-bit address generation
5625 mechanism since it is more efficient. Note that due to
5626 the signed offset used by memory operations, the 32-bit
5627 range is shifted down by 32768 here. This code should
5628 probably attempt to generate 64-bit constants more
5629 efficiently in general.
5631 if (HAVE_64BIT_ADDRESSES
5632 && !(offset_expr
.X_op
== O_constant
5633 && IS_SEXT_32BIT_NUM (offset_expr
.X_add_number
+ 0x8000)))
5637 /* We don't do GP optimization for now because RELAX_ENCODE can't
5638 hold the data for such large chunks. */
5640 if (used_at
== 0 && ! mips_opts
.noat
)
5642 macro_build (p
, &icnt
, &offset_expr
, "lui", "t,u",
5643 tempreg
, (int) BFD_RELOC_MIPS_HIGHEST
);
5644 macro_build (p
, &icnt
, &offset_expr
, "lui", "t,u",
5645 AT
, (int) BFD_RELOC_HI16_S
);
5646 macro_build (p
, &icnt
, &offset_expr
, "daddiu", "t,r,j",
5647 tempreg
, tempreg
, (int) BFD_RELOC_MIPS_HIGHER
);
5649 macro_build (p
, &icnt
, (expressionS
*) NULL
, "daddu",
5650 "d,v,t", AT
, AT
, breg
);
5651 macro_build (p
, &icnt
, (expressionS
*) NULL
, "dsll32",
5652 "d,w,<", tempreg
, tempreg
, 0);
5653 macro_build (p
, &icnt
, (expressionS
*) NULL
, "daddu",
5654 "d,v,t", tempreg
, tempreg
, AT
);
5655 macro_build (p
, &icnt
, &offset_expr
, s
,
5656 fmt
, treg
, (int) BFD_RELOC_LO16
, tempreg
);
5661 macro_build (p
, &icnt
, &offset_expr
, "lui", "t,u",
5662 tempreg
, (int) BFD_RELOC_MIPS_HIGHEST
);
5663 macro_build (p
, &icnt
, &offset_expr
, "daddiu", "t,r,j",
5664 tempreg
, tempreg
, (int) BFD_RELOC_MIPS_HIGHER
);
5665 macro_build (p
, &icnt
, (expressionS
*) NULL
, "dsll",
5666 "d,w,<", tempreg
, tempreg
, 16);
5667 macro_build (p
, &icnt
, &offset_expr
, "daddiu", "t,r,j",
5668 tempreg
, tempreg
, (int) BFD_RELOC_HI16_S
);
5669 macro_build (p
, &icnt
, (expressionS
*) NULL
, "dsll",
5670 "d,w,<", tempreg
, tempreg
, 16);
5672 macro_build (p
, &icnt
, (expressionS
*) NULL
, "daddu",
5673 "d,v,t", tempreg
, tempreg
, breg
);
5674 macro_build (p
, &icnt
, &offset_expr
, s
,
5675 fmt
, treg
, (int) BFD_RELOC_LO16
, tempreg
);
5683 if ((valueT
) offset_expr
.X_add_number
> MAX_GPREL_OFFSET
5684 || nopic_need_relax (offset_expr
.X_add_symbol
, 1))
5689 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
5690 treg
, (int) BFD_RELOC_GPREL16
,
5692 p
= frag_var (rs_machine_dependent
, 8, 0,
5693 RELAX_ENCODE (4, 8, 0, 4, 0,
5694 (mips_opts
.warn_about_macros
5696 && mips_opts
.noat
))),
5697 offset_expr
.X_add_symbol
, 0, NULL
);
5700 macro_build_lui (p
, &icnt
, &offset_expr
, tempreg
);
5703 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
, treg
,
5704 (int) BFD_RELOC_LO16
, tempreg
);
5708 if ((valueT
) offset_expr
.X_add_number
> MAX_GPREL_OFFSET
5709 || nopic_need_relax (offset_expr
.X_add_symbol
, 1))
5714 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5715 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
5716 "d,v,t", tempreg
, breg
, mips_gp_register
);
5717 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
5718 treg
, (int) BFD_RELOC_GPREL16
, tempreg
);
5719 p
= frag_var (rs_machine_dependent
, 12, 0,
5720 RELAX_ENCODE (8, 12, 0, 8, 0, 0),
5721 offset_expr
.X_add_symbol
, 0, NULL
);
5723 macro_build_lui (p
, &icnt
, &offset_expr
, tempreg
);
5726 macro_build (p
, &icnt
, (expressionS
*) NULL
,
5727 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
5728 "d,v,t", tempreg
, tempreg
, breg
);
5731 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
, treg
,
5732 (int) BFD_RELOC_LO16
, tempreg
);
5735 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
5738 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT16
;
5740 /* If this is a reference to an external symbol, we want
5741 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5743 <op> $treg,0($tempreg)
5745 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5747 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
5748 <op> $treg,0($tempreg)
5749 If we have NewABI, we want
5750 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
5751 If there is a base register, we add it to $tempreg before
5752 the <op>. If there is a constant, we stick it in the
5753 <op> instruction. We don't handle constants larger than
5754 16 bits, because we have no way to load the upper 16 bits
5755 (actually, we could handle them for the subset of cases
5756 in which we are not using $at). */
5757 assert (offset_expr
.X_op
== O_symbol
);
5758 expr1
.X_add_number
= offset_expr
.X_add_number
;
5759 offset_expr
.X_add_number
= 0;
5761 lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT_DISP
;
5762 if (expr1
.X_add_number
< -0x8000
5763 || expr1
.X_add_number
>= 0x8000)
5764 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
5766 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5767 HAVE_32BIT_ADDRESSES
? "lw" : "ld", "t,o(b)", tempreg
,
5768 (int) lw_reloc_type
, mips_gp_register
);
5769 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
5770 p
= frag_var (rs_machine_dependent
, 4, 0,
5771 RELAX_ENCODE (0, 4, -8, 0, 0, 0),
5772 offset_expr
.X_add_symbol
, 0, NULL
);
5773 macro_build (p
, &icnt
, &offset_expr
,
5774 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
5775 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
5777 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5778 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
5779 "d,v,t", tempreg
, tempreg
, breg
);
5780 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
, treg
,
5781 (int) BFD_RELOC_LO16
, tempreg
);
5783 else if (mips_pic
== SVR4_PIC
)
5788 /* If this is a reference to an external symbol, we want
5789 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5790 addu $tempreg,$tempreg,$gp
5791 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5792 <op> $treg,0($tempreg)
5794 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5796 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
5797 <op> $treg,0($tempreg)
5798 If there is a base register, we add it to $tempreg before
5799 the <op>. If there is a constant, we stick it in the
5800 <op> instruction. We don't handle constants larger than
5801 16 bits, because we have no way to load the upper 16 bits
5802 (actually, we could handle them for the subset of cases
5803 in which we are not using $at).
5806 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
5807 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
5808 <op> $treg,0($tempreg)
5810 assert (offset_expr
.X_op
== O_symbol
);
5811 expr1
.X_add_number
= offset_expr
.X_add_number
;
5812 offset_expr
.X_add_number
= 0;
5813 if (expr1
.X_add_number
< -0x8000
5814 || expr1
.X_add_number
>= 0x8000)
5815 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
5818 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5819 HAVE_32BIT_ADDRESSES
? "lw" : "ld",
5820 "t,o(b)", tempreg
, BFD_RELOC_MIPS_GOT_PAGE
,
5822 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5823 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
5824 "t,r,j", tempreg
, tempreg
,
5825 BFD_RELOC_MIPS_GOT_OFST
);
5827 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5828 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
5829 "d,v,t", tempreg
, tempreg
, breg
);
5830 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
, treg
,
5831 (int) BFD_RELOC_LO16
, tempreg
);
5838 if (reg_needs_delay (mips_gp_register
))
5843 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
5844 tempreg
, (int) BFD_RELOC_MIPS_GOT_HI16
);
5845 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5846 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
5847 "d,v,t", tempreg
, tempreg
, mips_gp_register
);
5848 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5849 HAVE_32BIT_ADDRESSES
? "lw" : "ld",
5850 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT_LO16
,
5852 p
= frag_var (rs_machine_dependent
, 12 + gpdel
, 0,
5853 RELAX_ENCODE (12, 12 + gpdel
, gpdel
, 8 + gpdel
, 0, 0),
5854 offset_expr
.X_add_symbol
, 0, NULL
);
5857 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
5860 macro_build (p
, &icnt
, &offset_expr
,
5861 HAVE_32BIT_ADDRESSES
? "lw" : "ld",
5862 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT16
,
5865 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
5867 macro_build (p
, &icnt
, &offset_expr
,
5868 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
5869 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
5871 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5872 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
5873 "d,v,t", tempreg
, tempreg
, breg
);
5874 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
, treg
,
5875 (int) BFD_RELOC_LO16
, tempreg
);
5877 else if (mips_pic
== EMBEDDED_PIC
)
5879 /* If there is no base register, we want
5880 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
5881 If there is a base register, we want
5882 addu $tempreg,$breg,$gp
5883 <op> $treg,<sym>($tempreg) (BFD_RELOC_GPREL16)
5885 assert (offset_expr
.X_op
== O_symbol
);
5888 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
5889 treg
, (int) BFD_RELOC_GPREL16
, mips_gp_register
);
5894 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5895 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
5896 "d,v,t", tempreg
, breg
, mips_gp_register
);
5897 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
5898 treg
, (int) BFD_RELOC_GPREL16
, tempreg
);
5911 load_register (&icnt
, treg
, &imm_expr
, 0);
5915 load_register (&icnt
, treg
, &imm_expr
, 1);
5919 if (imm_expr
.X_op
== O_constant
)
5921 load_register (&icnt
, AT
, &imm_expr
, 0);
5922 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5923 "mtc1", "t,G", AT
, treg
);
5928 assert (offset_expr
.X_op
== O_symbol
5929 && strcmp (segment_name (S_GET_SEGMENT
5930 (offset_expr
.X_add_symbol
)),
5932 && offset_expr
.X_add_number
== 0);
5933 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lwc1", "T,o(b)",
5934 treg
, (int) BFD_RELOC_MIPS_LITERAL
, mips_gp_register
);
5939 /* Check if we have a constant in IMM_EXPR. If the GPRs are 64 bits
5940 wide, IMM_EXPR is the entire value. Otherwise IMM_EXPR is the high
5941 order 32 bits of the value and the low order 32 bits are either
5942 zero or in OFFSET_EXPR. */
5943 if (imm_expr
.X_op
== O_constant
|| imm_expr
.X_op
== O_big
)
5945 if (HAVE_64BIT_GPRS
)
5946 load_register (&icnt
, treg
, &imm_expr
, 1);
5951 if (target_big_endian
)
5963 load_register (&icnt
, hreg
, &imm_expr
, 0);
5966 if (offset_expr
.X_op
== O_absent
)
5967 move_register (&icnt
, lreg
, 0);
5970 assert (offset_expr
.X_op
== O_constant
);
5971 load_register (&icnt
, lreg
, &offset_expr
, 0);
5978 /* We know that sym is in the .rdata section. First we get the
5979 upper 16 bits of the address. */
5980 if (mips_pic
== NO_PIC
)
5982 macro_build_lui (NULL
, &icnt
, &offset_expr
, AT
);
5984 else if (mips_pic
== SVR4_PIC
)
5986 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5987 HAVE_32BIT_ADDRESSES
? "lw" : "ld",
5988 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
,
5991 else if (mips_pic
== EMBEDDED_PIC
)
5993 /* For embedded PIC we pick up the entire address off $gp in
5994 a single instruction. */
5995 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5996 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu", "t,r,j", AT
,
5997 mips_gp_register
, (int) BFD_RELOC_GPREL16
);
5998 offset_expr
.X_op
= O_constant
;
5999 offset_expr
.X_add_number
= 0;
6004 /* Now we load the register(s). */
6005 if (HAVE_64BIT_GPRS
)
6006 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "ld", "t,o(b)",
6007 treg
, (int) BFD_RELOC_LO16
, AT
);
6010 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lw", "t,o(b)",
6011 treg
, (int) BFD_RELOC_LO16
, AT
);
6014 /* FIXME: How in the world do we deal with the possible
6016 offset_expr
.X_add_number
+= 4;
6017 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lw", "t,o(b)",
6018 treg
+ 1, (int) BFD_RELOC_LO16
, AT
);
6022 /* To avoid confusion in tc_gen_reloc, we must ensure that this
6023 does not become a variant frag. */
6024 frag_wane (frag_now
);
6030 /* Check if we have a constant in IMM_EXPR. If the FPRs are 64 bits
6031 wide, IMM_EXPR is the entire value and the GPRs are known to be 64
6032 bits wide as well. Otherwise IMM_EXPR is the high order 32 bits of
6033 the value and the low order 32 bits are either zero or in
6035 if (imm_expr
.X_op
== O_constant
|| imm_expr
.X_op
== O_big
)
6037 load_register (&icnt
, AT
, &imm_expr
, HAVE_64BIT_FPRS
);
6038 if (HAVE_64BIT_FPRS
)
6040 assert (HAVE_64BIT_GPRS
);
6041 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6042 "dmtc1", "t,S", AT
, treg
);
6046 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6047 "mtc1", "t,G", AT
, treg
+ 1);
6048 if (offset_expr
.X_op
== O_absent
)
6049 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6050 "mtc1", "t,G", 0, treg
);
6053 assert (offset_expr
.X_op
== O_constant
);
6054 load_register (&icnt
, AT
, &offset_expr
, 0);
6055 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6056 "mtc1", "t,G", AT
, treg
);
6062 assert (offset_expr
.X_op
== O_symbol
6063 && offset_expr
.X_add_number
== 0);
6064 s
= segment_name (S_GET_SEGMENT (offset_expr
.X_add_symbol
));
6065 if (strcmp (s
, ".lit8") == 0)
6067 if (mips_opts
.isa
!= ISA_MIPS1
)
6069 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "ldc1",
6070 "T,o(b)", treg
, (int) BFD_RELOC_MIPS_LITERAL
,
6074 breg
= mips_gp_register
;
6075 r
= BFD_RELOC_MIPS_LITERAL
;
6080 assert (strcmp (s
, RDATA_SECTION_NAME
) == 0);
6081 if (mips_pic
== SVR4_PIC
)
6082 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
6083 HAVE_32BIT_ADDRESSES
? "lw" : "ld",
6084 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
,
6088 /* FIXME: This won't work for a 64 bit address. */
6089 macro_build_lui (NULL
, &icnt
, &offset_expr
, AT
);
6092 if (mips_opts
.isa
!= ISA_MIPS1
)
6094 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "ldc1",
6095 "T,o(b)", treg
, (int) BFD_RELOC_LO16
, AT
);
6097 /* To avoid confusion in tc_gen_reloc, we must ensure
6098 that this does not become a variant frag. */
6099 frag_wane (frag_now
);
6110 if (mips_arch
== CPU_R4650
)
6112 as_bad (_("opcode not supported on this processor"));
6115 /* Even on a big endian machine $fn comes before $fn+1. We have
6116 to adjust when loading from memory. */
6119 assert (mips_opts
.isa
== ISA_MIPS1
);
6120 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lwc1", "T,o(b)",
6121 target_big_endian
? treg
+ 1 : treg
,
6123 /* FIXME: A possible overflow which I don't know how to deal
6125 offset_expr
.X_add_number
+= 4;
6126 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lwc1", "T,o(b)",
6127 target_big_endian
? treg
: treg
+ 1,
6130 /* To avoid confusion in tc_gen_reloc, we must ensure that this
6131 does not become a variant frag. */
6132 frag_wane (frag_now
);
6141 * The MIPS assembler seems to check for X_add_number not
6142 * being double aligned and generating:
6145 * addiu at,at,%lo(foo+1)
6148 * But, the resulting address is the same after relocation so why
6149 * generate the extra instruction?
6151 if (mips_arch
== CPU_R4650
)
6153 as_bad (_("opcode not supported on this processor"));
6156 /* Itbl support may require additional care here. */
6158 if (mips_opts
.isa
!= ISA_MIPS1
)
6169 if (mips_arch
== CPU_R4650
)
6171 as_bad (_("opcode not supported on this processor"));
6175 if (mips_opts
.isa
!= ISA_MIPS1
)
6183 /* Itbl support may require additional care here. */
6188 if (HAVE_64BIT_GPRS
)
6199 if (HAVE_64BIT_GPRS
)
6209 /* We do _not_ bother to allow embedded PIC (symbol-local_symbol)
6210 loads for the case of doing a pair of loads to simulate an 'ld'.
6211 This is not currently done by the compiler, and assembly coders
6212 writing embedded-pic code can cope. */
6214 if (offset_expr
.X_op
!= O_symbol
6215 && offset_expr
.X_op
!= O_constant
)
6217 as_bad (_("expression too complex"));
6218 offset_expr
.X_op
= O_constant
;
6221 /* Even on a big endian machine $fn comes before $fn+1. We have
6222 to adjust when loading from memory. We set coproc if we must
6223 load $fn+1 first. */
6224 /* Itbl support may require additional care here. */
6225 if (! target_big_endian
)
6228 if (mips_pic
== NO_PIC
6229 || offset_expr
.X_op
== O_constant
)
6233 /* If this is a reference to a GP relative symbol, we want
6234 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
6235 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_GPREL16)
6236 If we have a base register, we use this
6238 <op> $treg,<sym>($at) (BFD_RELOC_GPREL16)
6239 <op> $treg+1,<sym>+4($at) (BFD_RELOC_GPREL16)
6240 If this is not a GP relative symbol, we want
6241 lui $at,<sym> (BFD_RELOC_HI16_S)
6242 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
6243 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
6244 If there is a base register, we add it to $at after the
6245 lui instruction. If there is a constant, we always use
6247 if ((valueT
) offset_expr
.X_add_number
> MAX_GPREL_OFFSET
6248 || nopic_need_relax (offset_expr
.X_add_symbol
, 1))
6260 tempreg
= mips_gp_register
;
6267 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6268 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
6269 "d,v,t", AT
, breg
, mips_gp_register
);
6275 /* Itbl support may require additional care here. */
6276 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
6277 coproc
? treg
+ 1 : treg
,
6278 (int) BFD_RELOC_GPREL16
, tempreg
);
6279 offset_expr
.X_add_number
+= 4;
6281 /* Set mips_optimize to 2 to avoid inserting an
6283 hold_mips_optimize
= mips_optimize
;
6285 /* Itbl support may require additional care here. */
6286 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
6287 coproc
? treg
: treg
+ 1,
6288 (int) BFD_RELOC_GPREL16
, tempreg
);
6289 mips_optimize
= hold_mips_optimize
;
6291 p
= frag_var (rs_machine_dependent
, 12 + off
, 0,
6292 RELAX_ENCODE (8 + off
, 12 + off
, 0, 4 + off
, 1,
6293 used_at
&& mips_opts
.noat
),
6294 offset_expr
.X_add_symbol
, 0, NULL
);
6296 /* We just generated two relocs. When tc_gen_reloc
6297 handles this case, it will skip the first reloc and
6298 handle the second. The second reloc already has an
6299 extra addend of 4, which we added above. We must
6300 subtract it out, and then subtract another 4 to make
6301 the first reloc come out right. The second reloc
6302 will come out right because we are going to add 4 to
6303 offset_expr when we build its instruction below.
6305 If we have a symbol, then we don't want to include
6306 the offset, because it will wind up being included
6307 when we generate the reloc. */
6309 if (offset_expr
.X_op
== O_constant
)
6310 offset_expr
.X_add_number
-= 8;
6313 offset_expr
.X_add_number
= -4;
6314 offset_expr
.X_op
= O_constant
;
6317 macro_build_lui (p
, &icnt
, &offset_expr
, AT
);
6322 macro_build (p
, &icnt
, (expressionS
*) NULL
,
6323 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
6324 "d,v,t", AT
, breg
, AT
);
6328 /* Itbl support may require additional care here. */
6329 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
,
6330 coproc
? treg
+ 1 : treg
,
6331 (int) BFD_RELOC_LO16
, AT
);
6334 /* FIXME: How do we handle overflow here? */
6335 offset_expr
.X_add_number
+= 4;
6336 /* Itbl support may require additional care here. */
6337 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
,
6338 coproc
? treg
: treg
+ 1,
6339 (int) BFD_RELOC_LO16
, AT
);
6341 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
6345 /* If this is a reference to an external symbol, we want
6346 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6351 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6353 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
6354 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
6355 If there is a base register we add it to $at before the
6356 lwc1 instructions. If there is a constant we include it
6357 in the lwc1 instructions. */
6359 expr1
.X_add_number
= offset_expr
.X_add_number
;
6360 offset_expr
.X_add_number
= 0;
6361 if (expr1
.X_add_number
< -0x8000
6362 || expr1
.X_add_number
>= 0x8000 - 4)
6363 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6368 frag_grow (24 + off
);
6369 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
6370 HAVE_32BIT_ADDRESSES
? "lw" : "ld", "t,o(b)", AT
,
6371 (int) BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
6372 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
6374 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6375 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
6376 "d,v,t", AT
, breg
, AT
);
6377 /* Itbl support may require additional care here. */
6378 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
6379 coproc
? treg
+ 1 : treg
,
6380 (int) BFD_RELOC_LO16
, AT
);
6381 expr1
.X_add_number
+= 4;
6383 /* Set mips_optimize to 2 to avoid inserting an undesired
6385 hold_mips_optimize
= mips_optimize
;
6387 /* Itbl support may require additional care here. */
6388 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
6389 coproc
? treg
: treg
+ 1,
6390 (int) BFD_RELOC_LO16
, AT
);
6391 mips_optimize
= hold_mips_optimize
;
6393 (void) frag_var (rs_machine_dependent
, 0, 0,
6394 RELAX_ENCODE (0, 0, -16 - off
, -8, 1, 0),
6395 offset_expr
.X_add_symbol
, 0, NULL
);
6397 else if (mips_pic
== SVR4_PIC
)
6402 /* If this is a reference to an external symbol, we want
6403 lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16)
6405 lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16)
6410 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6412 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
6413 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
6414 If there is a base register we add it to $at before the
6415 lwc1 instructions. If there is a constant we include it
6416 in the lwc1 instructions. */
6418 expr1
.X_add_number
= offset_expr
.X_add_number
;
6419 offset_expr
.X_add_number
= 0;
6420 if (expr1
.X_add_number
< -0x8000
6421 || expr1
.X_add_number
>= 0x8000 - 4)
6422 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6423 if (reg_needs_delay (mips_gp_register
))
6432 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
6433 AT
, (int) BFD_RELOC_MIPS_GOT_HI16
);
6434 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6435 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
6436 "d,v,t", AT
, AT
, mips_gp_register
);
6437 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
6438 HAVE_32BIT_ADDRESSES
? "lw" : "ld",
6439 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT_LO16
, AT
);
6440 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
6442 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6443 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
6444 "d,v,t", AT
, breg
, AT
);
6445 /* Itbl support may require additional care here. */
6446 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
6447 coproc
? treg
+ 1 : treg
,
6448 (int) BFD_RELOC_LO16
, AT
);
6449 expr1
.X_add_number
+= 4;
6451 /* Set mips_optimize to 2 to avoid inserting an undesired
6453 hold_mips_optimize
= mips_optimize
;
6455 /* Itbl support may require additional care here. */
6456 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
6457 coproc
? treg
: treg
+ 1,
6458 (int) BFD_RELOC_LO16
, AT
);
6459 mips_optimize
= hold_mips_optimize
;
6460 expr1
.X_add_number
-= 4;
6462 p
= frag_var (rs_machine_dependent
, 16 + gpdel
+ off
, 0,
6463 RELAX_ENCODE (24 + off
, 16 + gpdel
+ off
, gpdel
,
6464 8 + gpdel
+ off
, 1, 0),
6465 offset_expr
.X_add_symbol
, 0, NULL
);
6468 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
6471 macro_build (p
, &icnt
, &offset_expr
,
6472 HAVE_32BIT_ADDRESSES
? "lw" : "ld",
6473 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
,
6476 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
6480 macro_build (p
, &icnt
, (expressionS
*) NULL
,
6481 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
6482 "d,v,t", AT
, breg
, AT
);
6485 /* Itbl support may require additional care here. */
6486 macro_build (p
, &icnt
, &expr1
, s
, fmt
,
6487 coproc
? treg
+ 1 : treg
,
6488 (int) BFD_RELOC_LO16
, AT
);
6490 expr1
.X_add_number
+= 4;
6492 /* Set mips_optimize to 2 to avoid inserting an undesired
6494 hold_mips_optimize
= mips_optimize
;
6496 /* Itbl support may require additional care here. */
6497 macro_build (p
, &icnt
, &expr1
, s
, fmt
,
6498 coproc
? treg
: treg
+ 1,
6499 (int) BFD_RELOC_LO16
, AT
);
6500 mips_optimize
= hold_mips_optimize
;
6502 else if (mips_pic
== EMBEDDED_PIC
)
6504 /* If there is no base register, we use
6505 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
6506 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_GPREL16)
6507 If we have a base register, we use
6509 <op> $treg,<sym>($at) (BFD_RELOC_GPREL16)
6510 <op> $treg+1,<sym>+4($at) (BFD_RELOC_GPREL16)
6514 tempreg
= mips_gp_register
;
6519 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6520 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
6521 "d,v,t", AT
, breg
, mips_gp_register
);
6526 /* Itbl support may require additional care here. */
6527 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
6528 coproc
? treg
+ 1 : treg
,
6529 (int) BFD_RELOC_GPREL16
, tempreg
);
6530 offset_expr
.X_add_number
+= 4;
6531 /* Itbl support may require additional care here. */
6532 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
6533 coproc
? treg
: treg
+ 1,
6534 (int) BFD_RELOC_GPREL16
, tempreg
);
6550 assert (HAVE_32BIT_ADDRESSES
);
6551 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
6552 (int) BFD_RELOC_LO16
, breg
);
6553 offset_expr
.X_add_number
+= 4;
6554 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
+ 1,
6555 (int) BFD_RELOC_LO16
, breg
);
6558 /* New code added to support COPZ instructions.
6559 This code builds table entries out of the macros in mip_opcodes.
6560 R4000 uses interlocks to handle coproc delays.
6561 Other chips (like the R3000) require nops to be inserted for delays.
6563 FIXME: Currently, we require that the user handle delays.
6564 In order to fill delay slots for non-interlocked chips,
6565 we must have a way to specify delays based on the coprocessor.
6566 Eg. 4 cycles if load coproc reg from memory, 1 if in cache, etc.
6567 What are the side-effects of the cop instruction?
6568 What cache support might we have and what are its effects?
6569 Both coprocessor & memory require delays. how long???
6570 What registers are read/set/modified?
6572 If an itbl is provided to interpret cop instructions,
6573 this knowledge can be encoded in the itbl spec. */
6587 /* For now we just do C (same as Cz). The parameter will be
6588 stored in insn_opcode by mips_ip. */
6589 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s
, "C",
6594 move_register (&icnt
, dreg
, sreg
);
6597 #ifdef LOSING_COMPILER
6599 /* Try and see if this is a new itbl instruction.
6600 This code builds table entries out of the macros in mip_opcodes.
6601 FIXME: For now we just assemble the expression and pass it's
6602 value along as a 32-bit immediate.
6603 We may want to have the assembler assemble this value,
6604 so that we gain the assembler's knowledge of delay slots,
6606 Would it be more efficient to use mask (id) here? */
6607 if (itbl_have_entries
6608 && (immed_expr
= itbl_assemble (ip
->insn_mo
->name
, "")))
6610 s
= ip
->insn_mo
->name
;
6612 coproc
= ITBL_DECODE_PNUM (immed_expr
);;
6613 macro_build ((char *) NULL
, &icnt
, &immed_expr
, s
, "C");
6620 as_warn (_("Macro used $at after \".set noat\""));
6625 struct mips_cl_insn
*ip
;
6627 register int treg
, sreg
, dreg
, breg
;
6643 bfd_reloc_code_real_type r
;
6646 treg
= (ip
->insn_opcode
>> 16) & 0x1f;
6647 dreg
= (ip
->insn_opcode
>> 11) & 0x1f;
6648 sreg
= breg
= (ip
->insn_opcode
>> 21) & 0x1f;
6649 mask
= ip
->insn_mo
->mask
;
6651 expr1
.X_op
= O_constant
;
6652 expr1
.X_op_symbol
= NULL
;
6653 expr1
.X_add_symbol
= NULL
;
6654 expr1
.X_add_number
= 1;
6658 #endif /* LOSING_COMPILER */
6663 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6664 dbl
? "dmultu" : "multu", "s,t", sreg
, treg
);
6665 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "mflo", "d",
6672 /* The MIPS assembler some times generates shifts and adds. I'm
6673 not trying to be that fancy. GCC should do this for us
6675 load_register (&icnt
, AT
, &imm_expr
, dbl
);
6676 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6677 dbl
? "dmult" : "mult", "s,t", sreg
, AT
);
6678 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "mflo", "d",
6692 mips_emit_delays (true);
6693 ++mips_opts
.noreorder
;
6694 mips_any_noreorder
= 1;
6696 load_register (&icnt
, AT
, &imm_expr
, dbl
);
6697 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6698 dbl
? "dmult" : "mult", "s,t", sreg
, imm
? AT
: treg
);
6699 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "mflo", "d",
6701 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6702 dbl
? "dsra32" : "sra", "d,w,<", dreg
, dreg
, RA
);
6703 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "mfhi", "d",
6706 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "tne",
6707 "s,t,q", dreg
, AT
, 6);
6710 expr1
.X_add_number
= 8;
6711 macro_build ((char *) NULL
, &icnt
, &expr1
, "beq", "s,t,p", dreg
,
6713 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "",
6715 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "break",
6718 --mips_opts
.noreorder
;
6719 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "mflo", "d", dreg
);
6732 mips_emit_delays (true);
6733 ++mips_opts
.noreorder
;
6734 mips_any_noreorder
= 1;
6736 load_register (&icnt
, AT
, &imm_expr
, dbl
);
6737 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6738 dbl
? "dmultu" : "multu",
6739 "s,t", sreg
, imm
? AT
: treg
);
6740 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "mfhi", "d",
6742 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "mflo", "d",
6745 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "tne",
6749 expr1
.X_add_number
= 8;
6750 macro_build ((char *) NULL
, &icnt
, &expr1
, "beq", "s,t,p", AT
, 0);
6751 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "",
6753 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "break",
6756 --mips_opts
.noreorder
;
6760 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "dsubu",
6761 "d,v,t", AT
, 0, treg
);
6762 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "dsrlv",
6763 "d,t,s", AT
, sreg
, AT
);
6764 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "dsllv",
6765 "d,t,s", dreg
, sreg
, treg
);
6766 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "or",
6767 "d,v,t", dreg
, dreg
, AT
);
6771 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "subu",
6772 "d,v,t", AT
, 0, treg
);
6773 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "srlv",
6774 "d,t,s", AT
, sreg
, AT
);
6775 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "sllv",
6776 "d,t,s", dreg
, sreg
, treg
);
6777 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "or",
6778 "d,v,t", dreg
, dreg
, AT
);
6785 if (imm_expr
.X_op
!= O_constant
)
6786 as_bad (_("rotate count too large"));
6787 rot
= imm_expr
.X_add_number
& 0x3f;
6788 if (CPU_HAS_DROR (mips_arch
))
6790 rot
= (64 - rot
) & 0x3f;
6792 macro_build ((char *) NULL
, &icnt
, NULL
, "dror32",
6793 "d,w,<", dreg
, sreg
, rot
- 32);
6795 macro_build ((char *) NULL
, &icnt
, NULL
, "dror",
6796 "d,w,<", dreg
, sreg
, rot
);
6800 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "dsrl",
6801 "d,w,<", dreg
, sreg
, 0);
6806 l
= (rot
< 0x20) ? "dsll" : "dsll32";
6807 r
= ((0x40 - rot
) < 0x20) ? "dsrl" : "dsrl32";
6809 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, l
,
6810 "d,w,<", AT
, sreg
, rot
);
6811 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, r
,
6812 "d,w,<", dreg
, sreg
, (0x20 - rot
) & 0x1f);
6813 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "or",
6814 "d,v,t", dreg
, dreg
, AT
);
6823 if (imm_expr
.X_op
!= O_constant
)
6824 as_bad (_("rotate count too large"));
6825 rot
= imm_expr
.X_add_number
& 0x1f;
6826 if (CPU_HAS_ROR (mips_arch
))
6828 macro_build ((char *) NULL
, &icnt
, NULL
, "ror",
6829 "d,w,<", dreg
, sreg
, (32 - rot
) & 0x1f);
6833 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "srl",
6834 "d,w,<", dreg
, sreg
, 0);
6837 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "sll",
6838 "d,w,<", AT
, sreg
, rot
);
6839 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "srl",
6840 "d,w,<", dreg
, sreg
, (0x20 - rot
) & 0x1f);
6841 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "or",
6842 "d,v,t", dreg
, dreg
, AT
);
6848 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "dsubu",
6849 "d,v,t", AT
, 0, treg
);
6850 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "dsllv",
6851 "d,t,s", AT
, sreg
, AT
);
6852 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "dsrlv",
6853 "d,t,s", dreg
, sreg
, treg
);
6854 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "or",
6855 "d,v,t", dreg
, dreg
, AT
);
6859 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "subu",
6860 "d,v,t", AT
, 0, treg
);
6861 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "sllv",
6862 "d,t,s", AT
, sreg
, AT
);
6863 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "srlv",
6864 "d,t,s", dreg
, sreg
, treg
);
6865 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "or",
6866 "d,v,t", dreg
, dreg
, AT
);
6873 if (imm_expr
.X_op
!= O_constant
)
6874 as_bad (_("rotate count too large"));
6875 rot
= imm_expr
.X_add_number
& 0x3f;
6877 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "dsrl",
6878 "d,w,<", dreg
, sreg
, 0);
6883 r
= (rot
< 0x20) ? "dsrl" : "dsrl32";
6884 l
= ((0x40 - rot
) < 0x20) ? "dsll" : "dsll32";
6886 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, r
,
6887 "d,w,<", AT
, sreg
, rot
);
6888 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, l
,
6889 "d,w,<", dreg
, sreg
, (0x20 - rot
) & 0x1f);
6890 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "or",
6891 "d,v,t", dreg
, dreg
, AT
);
6900 if (imm_expr
.X_op
!= O_constant
)
6901 as_bad (_("rotate count too large"));
6902 rot
= imm_expr
.X_add_number
& 0x1f;
6904 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "srl",
6905 "d,w,<", dreg
, sreg
, 0);
6908 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "srl",
6909 "d,w,<", AT
, sreg
, rot
);
6910 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "sll",
6911 "d,w,<", dreg
, sreg
, (0x20 - rot
) & 0x1f);
6912 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "or",
6913 "d,v,t", dreg
, dreg
, AT
);
6919 if (mips_arch
== CPU_R4650
)
6921 as_bad (_("opcode not supported on this processor"));
6924 assert (mips_opts
.isa
== ISA_MIPS1
);
6925 /* Even on a big endian machine $fn comes before $fn+1. We have
6926 to adjust when storing to memory. */
6927 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "swc1", "T,o(b)",
6928 target_big_endian
? treg
+ 1 : treg
,
6929 (int) BFD_RELOC_LO16
, breg
);
6930 offset_expr
.X_add_number
+= 4;
6931 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "swc1", "T,o(b)",
6932 target_big_endian
? treg
: treg
+ 1,
6933 (int) BFD_RELOC_LO16
, breg
);
6938 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
6939 treg
, (int) BFD_RELOC_LO16
);
6941 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
6942 sreg
, (int) BFD_RELOC_LO16
);
6945 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "xor",
6946 "d,v,t", dreg
, sreg
, treg
);
6947 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
6948 dreg
, (int) BFD_RELOC_LO16
);
6953 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
6955 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
6956 sreg
, (int) BFD_RELOC_LO16
);
6961 as_warn (_("Instruction %s: result is always false"),
6963 move_register (&icnt
, dreg
, 0);
6966 if (imm_expr
.X_op
== O_constant
6967 && imm_expr
.X_add_number
>= 0
6968 && imm_expr
.X_add_number
< 0x10000)
6970 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "xori", "t,r,i", dreg
,
6971 sreg
, (int) BFD_RELOC_LO16
);
6974 else if (imm_expr
.X_op
== O_constant
6975 && imm_expr
.X_add_number
> -0x8000
6976 && imm_expr
.X_add_number
< 0)
6978 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
6979 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
6980 HAVE_32BIT_GPRS
? "addiu" : "daddiu",
6981 "t,r,j", dreg
, sreg
,
6982 (int) BFD_RELOC_LO16
);
6987 load_register (&icnt
, AT
, &imm_expr
, HAVE_64BIT_GPRS
);
6988 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "xor",
6989 "d,v,t", dreg
, sreg
, AT
);
6992 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
, dreg
,
6993 (int) BFD_RELOC_LO16
);
6998 case M_SGE
: /* sreg >= treg <==> not (sreg < treg) */
7004 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s
, "d,v,t",
7006 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
7007 (int) BFD_RELOC_LO16
);
7010 case M_SGE_I
: /* sreg >= I <==> not (sreg < I) */
7012 if (imm_expr
.X_op
== O_constant
7013 && imm_expr
.X_add_number
>= -0x8000
7014 && imm_expr
.X_add_number
< 0x8000)
7016 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
7017 mask
== M_SGE_I
? "slti" : "sltiu",
7018 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
7023 load_register (&icnt
, AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7024 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
7025 mask
== M_SGE_I
? "slt" : "sltu", "d,v,t", dreg
, sreg
,
7029 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
7030 (int) BFD_RELOC_LO16
);
7035 case M_SGT
: /* sreg > treg <==> treg < sreg */
7041 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s
, "d,v,t",
7045 case M_SGT_I
: /* sreg > I <==> I < sreg */
7051 load_register (&icnt
, AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7052 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s
, "d,v,t",
7056 case M_SLE
: /* sreg <= treg <==> treg >= sreg <==> not (treg < sreg) */
7062 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s
, "d,v,t",
7064 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
7065 (int) BFD_RELOC_LO16
);
7068 case M_SLE_I
: /* sreg <= I <==> I >= sreg <==> not (I < sreg) */
7074 load_register (&icnt
, AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7075 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s
, "d,v,t",
7077 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
7078 (int) BFD_RELOC_LO16
);
7082 if (imm_expr
.X_op
== O_constant
7083 && imm_expr
.X_add_number
>= -0x8000
7084 && imm_expr
.X_add_number
< 0x8000)
7086 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "slti", "t,r,j",
7087 dreg
, sreg
, (int) BFD_RELOC_LO16
);
7090 load_register (&icnt
, AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7091 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "slt", "d,v,t",
7096 if (imm_expr
.X_op
== O_constant
7097 && imm_expr
.X_add_number
>= -0x8000
7098 && imm_expr
.X_add_number
< 0x8000)
7100 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "sltiu", "t,r,j",
7101 dreg
, sreg
, (int) BFD_RELOC_LO16
);
7104 load_register (&icnt
, AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7105 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "sltu",
7106 "d,v,t", dreg
, sreg
, AT
);
7111 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "sltu",
7112 "d,v,t", dreg
, 0, treg
);
7114 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "sltu",
7115 "d,v,t", dreg
, 0, sreg
);
7118 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "xor",
7119 "d,v,t", dreg
, sreg
, treg
);
7120 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "sltu",
7121 "d,v,t", dreg
, 0, dreg
);
7126 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
7128 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "sltu",
7129 "d,v,t", dreg
, 0, sreg
);
7134 as_warn (_("Instruction %s: result is always true"),
7136 macro_build ((char *) NULL
, &icnt
, &expr1
,
7137 HAVE_32BIT_GPRS
? "addiu" : "daddiu",
7138 "t,r,j", dreg
, 0, (int) BFD_RELOC_LO16
);
7141 if (imm_expr
.X_op
== O_constant
7142 && imm_expr
.X_add_number
>= 0
7143 && imm_expr
.X_add_number
< 0x10000)
7145 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "xori", "t,r,i",
7146 dreg
, sreg
, (int) BFD_RELOC_LO16
);
7149 else if (imm_expr
.X_op
== O_constant
7150 && imm_expr
.X_add_number
> -0x8000
7151 && imm_expr
.X_add_number
< 0)
7153 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
7154 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
7155 HAVE_32BIT_GPRS
? "addiu" : "daddiu",
7156 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
7161 load_register (&icnt
, AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7162 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "xor",
7163 "d,v,t", dreg
, sreg
, AT
);
7166 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "sltu",
7167 "d,v,t", dreg
, 0, dreg
);
7175 if (imm_expr
.X_op
== O_constant
7176 && imm_expr
.X_add_number
> -0x8000
7177 && imm_expr
.X_add_number
<= 0x8000)
7179 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
7180 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
7181 dbl
? "daddi" : "addi",
7182 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
7185 load_register (&icnt
, AT
, &imm_expr
, dbl
);
7186 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
7187 dbl
? "dsub" : "sub", "d,v,t", dreg
, sreg
, AT
);
7193 if (imm_expr
.X_op
== O_constant
7194 && imm_expr
.X_add_number
> -0x8000
7195 && imm_expr
.X_add_number
<= 0x8000)
7197 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
7198 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
7199 dbl
? "daddiu" : "addiu",
7200 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
7203 load_register (&icnt
, AT
, &imm_expr
, dbl
);
7204 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
7205 dbl
? "dsubu" : "subu", "d,v,t", dreg
, sreg
, AT
);
7226 load_register (&icnt
, AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7227 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s
, "s,t", sreg
,
7233 assert (mips_opts
.isa
== ISA_MIPS1
);
7234 sreg
= (ip
->insn_opcode
>> 11) & 0x1f; /* floating reg */
7235 dreg
= (ip
->insn_opcode
>> 06) & 0x1f; /* floating reg */
7238 * Is the double cfc1 instruction a bug in the mips assembler;
7239 * or is there a reason for it?
7241 mips_emit_delays (true);
7242 ++mips_opts
.noreorder
;
7243 mips_any_noreorder
= 1;
7244 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "cfc1", "t,G",
7246 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "cfc1", "t,G",
7248 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
7249 expr1
.X_add_number
= 3;
7250 macro_build ((char *) NULL
, &icnt
, &expr1
, "ori", "t,r,i", AT
, treg
,
7251 (int) BFD_RELOC_LO16
);
7252 expr1
.X_add_number
= 2;
7253 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", AT
, AT
,
7254 (int) BFD_RELOC_LO16
);
7255 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "ctc1", "t,G",
7257 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
7258 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
7259 mask
== M_TRUNCWD
? "cvt.w.d" : "cvt.w.s", "D,S", dreg
, sreg
);
7260 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "ctc1", "t,G",
7262 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
7263 --mips_opts
.noreorder
;
7272 if (offset_expr
.X_add_number
>= 0x7fff)
7273 as_bad (_("operand overflow"));
7274 /* avoid load delay */
7275 if (! target_big_endian
)
7276 ++offset_expr
.X_add_number
;
7277 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
7278 (int) BFD_RELOC_LO16
, breg
);
7279 if (! target_big_endian
)
7280 --offset_expr
.X_add_number
;
7282 ++offset_expr
.X_add_number
;
7283 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lbu", "t,o(b)", AT
,
7284 (int) BFD_RELOC_LO16
, breg
);
7285 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "sll", "d,w,<",
7287 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "or", "d,v,t",
7301 if (offset_expr
.X_add_number
>= 0x8000 - off
)
7302 as_bad (_("operand overflow"));
7303 if (! target_big_endian
)
7304 offset_expr
.X_add_number
+= off
;
7305 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
7306 (int) BFD_RELOC_LO16
, breg
);
7307 if (! target_big_endian
)
7308 offset_expr
.X_add_number
-= off
;
7310 offset_expr
.X_add_number
+= off
;
7311 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s2
, "t,o(b)", treg
,
7312 (int) BFD_RELOC_LO16
, breg
);
7326 load_address (&icnt
, AT
, &offset_expr
, &used_at
);
7328 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
7329 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
7330 "d,v,t", AT
, AT
, breg
);
7331 if (! target_big_endian
)
7332 expr1
.X_add_number
= off
;
7334 expr1
.X_add_number
= 0;
7335 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, "t,o(b)", treg
,
7336 (int) BFD_RELOC_LO16
, AT
);
7337 if (! target_big_endian
)
7338 expr1
.X_add_number
= 0;
7340 expr1
.X_add_number
= off
;
7341 macro_build ((char *) NULL
, &icnt
, &expr1
, s2
, "t,o(b)", treg
,
7342 (int) BFD_RELOC_LO16
, AT
);
7348 load_address (&icnt
, AT
, &offset_expr
, &used_at
);
7350 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
7351 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
7352 "d,v,t", AT
, AT
, breg
);
7353 if (target_big_endian
)
7354 expr1
.X_add_number
= 0;
7355 macro_build ((char *) NULL
, &icnt
, &expr1
,
7356 mask
== M_ULH_A
? "lb" : "lbu", "t,o(b)", treg
,
7357 (int) BFD_RELOC_LO16
, AT
);
7358 if (target_big_endian
)
7359 expr1
.X_add_number
= 1;
7361 expr1
.X_add_number
= 0;
7362 macro_build ((char *) NULL
, &icnt
, &expr1
, "lbu", "t,o(b)", AT
,
7363 (int) BFD_RELOC_LO16
, AT
);
7364 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "sll", "d,w,<",
7366 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "or", "d,v,t",
7371 if (offset_expr
.X_add_number
>= 0x7fff)
7372 as_bad (_("operand overflow"));
7373 if (target_big_endian
)
7374 ++offset_expr
.X_add_number
;
7375 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "sb", "t,o(b)", treg
,
7376 (int) BFD_RELOC_LO16
, breg
);
7377 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "srl", "d,w,<",
7379 if (target_big_endian
)
7380 --offset_expr
.X_add_number
;
7382 ++offset_expr
.X_add_number
;
7383 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "sb", "t,o(b)", AT
,
7384 (int) BFD_RELOC_LO16
, breg
);
7397 if (offset_expr
.X_add_number
>= 0x8000 - off
)
7398 as_bad (_("operand overflow"));
7399 if (! target_big_endian
)
7400 offset_expr
.X_add_number
+= off
;
7401 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
7402 (int) BFD_RELOC_LO16
, breg
);
7403 if (! target_big_endian
)
7404 offset_expr
.X_add_number
-= off
;
7406 offset_expr
.X_add_number
+= off
;
7407 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s2
, "t,o(b)", treg
,
7408 (int) BFD_RELOC_LO16
, breg
);
7422 load_address (&icnt
, AT
, &offset_expr
, &used_at
);
7424 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
7425 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
7426 "d,v,t", AT
, AT
, breg
);
7427 if (! target_big_endian
)
7428 expr1
.X_add_number
= off
;
7430 expr1
.X_add_number
= 0;
7431 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, "t,o(b)", treg
,
7432 (int) BFD_RELOC_LO16
, AT
);
7433 if (! target_big_endian
)
7434 expr1
.X_add_number
= 0;
7436 expr1
.X_add_number
= off
;
7437 macro_build ((char *) NULL
, &icnt
, &expr1
, s2
, "t,o(b)", treg
,
7438 (int) BFD_RELOC_LO16
, AT
);
7443 load_address (&icnt
, AT
, &offset_expr
, &used_at
);
7445 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
7446 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
7447 "d,v,t", AT
, AT
, breg
);
7448 if (! target_big_endian
)
7449 expr1
.X_add_number
= 0;
7450 macro_build ((char *) NULL
, &icnt
, &expr1
, "sb", "t,o(b)", treg
,
7451 (int) BFD_RELOC_LO16
, AT
);
7452 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "srl", "d,w,<",
7454 if (! target_big_endian
)
7455 expr1
.X_add_number
= 1;
7457 expr1
.X_add_number
= 0;
7458 macro_build ((char *) NULL
, &icnt
, &expr1
, "sb", "t,o(b)", treg
,
7459 (int) BFD_RELOC_LO16
, AT
);
7460 if (! target_big_endian
)
7461 expr1
.X_add_number
= 0;
7463 expr1
.X_add_number
= 1;
7464 macro_build ((char *) NULL
, &icnt
, &expr1
, "lbu", "t,o(b)", AT
,
7465 (int) BFD_RELOC_LO16
, AT
);
7466 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "sll", "d,w,<",
7468 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "or", "d,v,t",
7473 /* FIXME: Check if this is one of the itbl macros, since they
7474 are added dynamically. */
7475 as_bad (_("Macro %s not implemented yet"), ip
->insn_mo
->name
);
7479 as_warn (_("Macro used $at after \".set noat\""));
7482 /* Implement macros in mips16 mode. */
7486 struct mips_cl_insn
*ip
;
7489 int xreg
, yreg
, zreg
, tmp
;
7493 const char *s
, *s2
, *s3
;
7495 mask
= ip
->insn_mo
->mask
;
7497 xreg
= (ip
->insn_opcode
>> MIPS16OP_SH_RX
) & MIPS16OP_MASK_RX
;
7498 yreg
= (ip
->insn_opcode
>> MIPS16OP_SH_RY
) & MIPS16OP_MASK_RY
;
7499 zreg
= (ip
->insn_opcode
>> MIPS16OP_SH_RZ
) & MIPS16OP_MASK_RZ
;
7503 expr1
.X_op
= O_constant
;
7504 expr1
.X_op_symbol
= NULL
;
7505 expr1
.X_add_symbol
= NULL
;
7506 expr1
.X_add_number
= 1;
7525 mips_emit_delays (true);
7526 ++mips_opts
.noreorder
;
7527 mips_any_noreorder
= 1;
7528 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
7529 dbl
? "ddiv" : "div",
7530 "0,x,y", xreg
, yreg
);
7531 expr1
.X_add_number
= 2;
7532 macro_build ((char *) NULL
, &icnt
, &expr1
, "bnez", "x,p", yreg
);
7533 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "break", "6",
7536 /* FIXME: The normal code checks for of -1 / -0x80000000 here,
7537 since that causes an overflow. We should do that as well,
7538 but I don't see how to do the comparisons without a temporary
7540 --mips_opts
.noreorder
;
7541 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s
, "x", zreg
);
7560 mips_emit_delays (true);
7561 ++mips_opts
.noreorder
;
7562 mips_any_noreorder
= 1;
7563 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s
, "0,x,y",
7565 expr1
.X_add_number
= 2;
7566 macro_build ((char *) NULL
, &icnt
, &expr1
, "bnez", "x,p", yreg
);
7567 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "break",
7569 --mips_opts
.noreorder
;
7570 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s2
, "x", zreg
);
7576 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
7577 dbl
? "dmultu" : "multu", "x,y", xreg
, yreg
);
7578 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "mflo", "x",
7587 if (imm_expr
.X_op
!= O_constant
)
7588 as_bad (_("Unsupported large constant"));
7589 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
7590 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
7591 dbl
? "daddiu" : "addiu", "y,x,4", yreg
, xreg
);
7595 if (imm_expr
.X_op
!= O_constant
)
7596 as_bad (_("Unsupported large constant"));
7597 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
7598 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "addiu",
7603 if (imm_expr
.X_op
!= O_constant
)
7604 as_bad (_("Unsupported large constant"));
7605 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
7606 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "daddiu",
7629 goto do_reverse_branch
;
7633 goto do_reverse_branch
;
7645 goto do_reverse_branch
;
7656 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s
, "x,y",
7658 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s2
, "p");
7685 goto do_addone_branch_i
;
7690 goto do_addone_branch_i
;
7705 goto do_addone_branch_i
;
7712 if (imm_expr
.X_op
!= O_constant
)
7713 as_bad (_("Unsupported large constant"));
7714 ++imm_expr
.X_add_number
;
7717 macro_build ((char *) NULL
, &icnt
, &imm_expr
, s
, s3
, xreg
);
7718 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s2
, "p");
7722 expr1
.X_add_number
= 0;
7723 macro_build ((char *) NULL
, &icnt
, &expr1
, "slti", "x,8", yreg
);
7725 move_register (&icnt
, xreg
, yreg
);
7726 expr1
.X_add_number
= 2;
7727 macro_build ((char *) NULL
, &icnt
, &expr1
, "bteqz", "p");
7728 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
7729 "neg", "x,w", xreg
, xreg
);
7733 /* For consistency checking, verify that all bits are specified either
7734 by the match/mask part of the instruction definition, or by the
7737 validate_mips_insn (opc
)
7738 const struct mips_opcode
*opc
;
7740 const char *p
= opc
->args
;
7742 unsigned long used_bits
= opc
->mask
;
7744 if ((used_bits
& opc
->match
) != opc
->match
)
7746 as_bad (_("internal: bad mips opcode (mask error): %s %s"),
7747 opc
->name
, opc
->args
);
7750 #define USE_BITS(mask,shift) (used_bits |= ((mask) << (shift)))
7757 case '<': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
7758 case '>': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
7760 case 'B': USE_BITS (OP_MASK_CODE20
, OP_SH_CODE20
); break;
7761 case 'C': USE_BITS (OP_MASK_COPZ
, OP_SH_COPZ
); break;
7762 case 'D': USE_BITS (OP_MASK_FD
, OP_SH_FD
); break;
7763 case 'E': USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
7765 case 'G': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
7766 case 'H': USE_BITS (OP_MASK_SEL
, OP_SH_SEL
); break;
7768 case 'J': USE_BITS (OP_MASK_CODE19
, OP_SH_CODE19
); break;
7770 case 'M': USE_BITS (OP_MASK_CCC
, OP_SH_CCC
); break;
7771 case 'N': USE_BITS (OP_MASK_BCC
, OP_SH_BCC
); break;
7772 case 'O': USE_BITS (OP_MASK_ALN
, OP_SH_ALN
); break;
7773 case 'Q': USE_BITS (OP_MASK_VSEL
, OP_SH_VSEL
);
7774 USE_BITS (OP_MASK_FT
, OP_SH_FT
); break;
7775 case 'R': USE_BITS (OP_MASK_FR
, OP_SH_FR
); break;
7776 case 'S': USE_BITS (OP_MASK_FS
, OP_SH_FS
); break;
7777 case 'T': USE_BITS (OP_MASK_FT
, OP_SH_FT
); break;
7778 case 'V': USE_BITS (OP_MASK_FS
, OP_SH_FS
); break;
7779 case 'W': USE_BITS (OP_MASK_FT
, OP_SH_FT
); break;
7780 case 'X': USE_BITS (OP_MASK_FD
, OP_SH_FD
); break;
7781 case 'Y': USE_BITS (OP_MASK_FS
, OP_SH_FS
); break;
7782 case 'Z': USE_BITS (OP_MASK_FT
, OP_SH_FT
); break;
7783 case 'a': USE_BITS (OP_MASK_TARGET
, OP_SH_TARGET
); break;
7784 case 'b': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
7785 case 'c': USE_BITS (OP_MASK_CODE
, OP_SH_CODE
); break;
7786 case 'd': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
7788 case 'h': USE_BITS (OP_MASK_PREFX
, OP_SH_PREFX
); break;
7789 case 'i': USE_BITS (OP_MASK_IMMEDIATE
, OP_SH_IMMEDIATE
); break;
7790 case 'j': USE_BITS (OP_MASK_DELTA
, OP_SH_DELTA
); break;
7791 case 'k': USE_BITS (OP_MASK_CACHE
, OP_SH_CACHE
); break;
7793 case 'o': USE_BITS (OP_MASK_DELTA
, OP_SH_DELTA
); break;
7794 case 'p': USE_BITS (OP_MASK_DELTA
, OP_SH_DELTA
); break;
7795 case 'q': USE_BITS (OP_MASK_CODE2
, OP_SH_CODE2
); break;
7796 case 'r': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
7797 case 's': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
7798 case 't': USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
7799 case 'u': USE_BITS (OP_MASK_IMMEDIATE
, OP_SH_IMMEDIATE
); break;
7800 case 'v': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
7801 case 'w': USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
7804 case 'P': USE_BITS (OP_MASK_PERFREG
, OP_SH_PERFREG
); break;
7805 case 'U': USE_BITS (OP_MASK_RD
, OP_SH_RD
);
7806 USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
7807 case 'e': USE_BITS (OP_MASK_VECBYTE
, OP_SH_VECBYTE
); break;
7808 case '%': USE_BITS (OP_MASK_VECALIGN
, OP_SH_VECALIGN
); break;
7812 as_bad (_("internal: bad mips opcode (unknown operand type `%c'): %s %s"),
7813 c
, opc
->name
, opc
->args
);
7817 if (used_bits
!= 0xffffffff)
7819 as_bad (_("internal: bad mips opcode (bits 0x%lx undefined): %s %s"),
7820 ~used_bits
& 0xffffffff, opc
->name
, opc
->args
);
7826 /* This routine assembles an instruction into its binary format. As a
7827 side effect, it sets one of the global variables imm_reloc or
7828 offset_reloc to the type of relocation to do if one of the operands
7829 is an address expression. */
7834 struct mips_cl_insn
*ip
;
7839 struct mips_opcode
*insn
;
7842 unsigned int lastregno
= 0;
7848 /* If the instruction contains a '.', we first try to match an instruction
7849 including the '.'. Then we try again without the '.'. */
7851 for (s
= str
; *s
!= '\0' && !ISSPACE (*s
); ++s
)
7854 /* If we stopped on whitespace, then replace the whitespace with null for
7855 the call to hash_find. Save the character we replaced just in case we
7856 have to re-parse the instruction. */
7863 insn
= (struct mips_opcode
*) hash_find (op_hash
, str
);
7865 /* If we didn't find the instruction in the opcode table, try again, but
7866 this time with just the instruction up to, but not including the
7870 /* Restore the character we overwrite above (if any). */
7874 /* Scan up to the first '.' or whitespace. */
7876 *s
!= '\0' && *s
!= '.' && !ISSPACE (*s
);
7880 /* If we did not find a '.', then we can quit now. */
7883 insn_error
= "unrecognized opcode";
7887 /* Lookup the instruction in the hash table. */
7889 if ((insn
= (struct mips_opcode
*) hash_find (op_hash
, str
)) == NULL
)
7891 insn_error
= "unrecognized opcode";
7901 assert (strcmp (insn
->name
, str
) == 0);
7903 if (OPCODE_IS_MEMBER (insn
,
7905 | (file_ase_mips16
? INSN_MIPS16
: 0)
7906 | (mips_opts
.ase_mdmx
? INSN_MDMX
: 0)
7907 | (mips_opts
.ase_mips3d
? INSN_MIPS3D
: 0)),
7913 if (insn
->pinfo
!= INSN_MACRO
)
7915 if (mips_arch
== CPU_R4650
&& (insn
->pinfo
& FP_D
) != 0)
7921 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
]
7922 && strcmp (insn
->name
, insn
[1].name
) == 0)
7931 static char buf
[100];
7932 if (mips_arch_info
->is_isa
)
7934 _("opcode not supported at this ISA level (%s)"),
7935 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
7938 _("opcode not supported on this processor: %s (%s)"),
7939 mips_arch_info
->name
,
7940 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
7950 ip
->insn_opcode
= insn
->match
;
7952 for (args
= insn
->args
;; ++args
)
7956 s
+= strspn (s
, " \t");
7960 case '\0': /* end of args */
7973 ip
->insn_opcode
|= lastregno
<< OP_SH_RS
;
7977 ip
->insn_opcode
|= lastregno
<< OP_SH_RT
;
7981 ip
->insn_opcode
|= lastregno
<< OP_SH_FT
;
7985 ip
->insn_opcode
|= lastregno
<< OP_SH_FS
;
7991 /* Handle optional base register.
7992 Either the base register is omitted or
7993 we must have a left paren. */
7994 /* This is dependent on the next operand specifier
7995 is a base register specification. */
7996 assert (args
[1] == 'b' || args
[1] == '5'
7997 || args
[1] == '-' || args
[1] == '4');
8001 case ')': /* these must match exactly */
8008 case '<': /* must be at least one digit */
8010 * According to the manual, if the shift amount is greater
8011 * than 31 or less than 0, then the shift amount should be
8012 * mod 32. In reality the mips assembler issues an error.
8013 * We issue a warning and mask out all but the low 5 bits.
8015 my_getExpression (&imm_expr
, s
);
8016 check_absolute_expr (ip
, &imm_expr
);
8017 if ((unsigned long) imm_expr
.X_add_number
> 31)
8019 as_warn (_("Improper shift amount (%lu)"),
8020 (unsigned long) imm_expr
.X_add_number
);
8021 imm_expr
.X_add_number
&= OP_MASK_SHAMT
;
8023 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_SHAMT
;
8024 imm_expr
.X_op
= O_absent
;
8028 case '>': /* shift amount minus 32 */
8029 my_getExpression (&imm_expr
, s
);
8030 check_absolute_expr (ip
, &imm_expr
);
8031 if ((unsigned long) imm_expr
.X_add_number
< 32
8032 || (unsigned long) imm_expr
.X_add_number
> 63)
8034 ip
->insn_opcode
|= (imm_expr
.X_add_number
- 32) << OP_SH_SHAMT
;
8035 imm_expr
.X_op
= O_absent
;
8039 case 'k': /* cache code */
8040 case 'h': /* prefx code */
8041 my_getExpression (&imm_expr
, s
);
8042 check_absolute_expr (ip
, &imm_expr
);
8043 if ((unsigned long) imm_expr
.X_add_number
> 31)
8045 as_warn (_("Invalid value for `%s' (%lu)"),
8047 (unsigned long) imm_expr
.X_add_number
);
8048 imm_expr
.X_add_number
&= 0x1f;
8051 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_CACHE
;
8053 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_PREFX
;
8054 imm_expr
.X_op
= O_absent
;
8058 case 'c': /* break code */
8059 my_getExpression (&imm_expr
, s
);
8060 check_absolute_expr (ip
, &imm_expr
);
8061 if ((unsigned long) imm_expr
.X_add_number
> 1023)
8063 as_warn (_("Illegal break code (%lu)"),
8064 (unsigned long) imm_expr
.X_add_number
);
8065 imm_expr
.X_add_number
&= OP_MASK_CODE
;
8067 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_CODE
;
8068 imm_expr
.X_op
= O_absent
;
8072 case 'q': /* lower break code */
8073 my_getExpression (&imm_expr
, s
);
8074 check_absolute_expr (ip
, &imm_expr
);
8075 if ((unsigned long) imm_expr
.X_add_number
> 1023)
8077 as_warn (_("Illegal lower break code (%lu)"),
8078 (unsigned long) imm_expr
.X_add_number
);
8079 imm_expr
.X_add_number
&= OP_MASK_CODE2
;
8081 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_CODE2
;
8082 imm_expr
.X_op
= O_absent
;
8086 case 'B': /* 20-bit syscall/break code. */
8087 my_getExpression (&imm_expr
, s
);
8088 check_absolute_expr (ip
, &imm_expr
);
8089 if ((unsigned long) imm_expr
.X_add_number
> OP_MASK_CODE20
)
8090 as_warn (_("Illegal 20-bit code (%lu)"),
8091 (unsigned long) imm_expr
.X_add_number
);
8092 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_CODE20
;
8093 imm_expr
.X_op
= O_absent
;
8097 case 'C': /* Coprocessor code */
8098 my_getExpression (&imm_expr
, s
);
8099 check_absolute_expr (ip
, &imm_expr
);
8100 if ((unsigned long) imm_expr
.X_add_number
>= (1 << 25))
8102 as_warn (_("Coproccesor code > 25 bits (%lu)"),
8103 (unsigned long) imm_expr
.X_add_number
);
8104 imm_expr
.X_add_number
&= ((1 << 25) - 1);
8106 ip
->insn_opcode
|= imm_expr
.X_add_number
;
8107 imm_expr
.X_op
= O_absent
;
8111 case 'J': /* 19-bit wait code. */
8112 my_getExpression (&imm_expr
, s
);
8113 check_absolute_expr (ip
, &imm_expr
);
8114 if ((unsigned long) imm_expr
.X_add_number
> OP_MASK_CODE19
)
8115 as_warn (_("Illegal 19-bit code (%lu)"),
8116 (unsigned long) imm_expr
.X_add_number
);
8117 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_CODE19
;
8118 imm_expr
.X_op
= O_absent
;
8122 case 'P': /* Performance register */
8123 my_getExpression (&imm_expr
, s
);
8124 check_absolute_expr (ip
, &imm_expr
);
8125 if (imm_expr
.X_add_number
!= 0 && imm_expr
.X_add_number
!= 1)
8127 as_warn (_("Invalid performance register (%lu)"),
8128 (unsigned long) imm_expr
.X_add_number
);
8129 imm_expr
.X_add_number
&= OP_MASK_PERFREG
;
8131 ip
->insn_opcode
|= (imm_expr
.X_add_number
<< OP_SH_PERFREG
);
8132 imm_expr
.X_op
= O_absent
;
8136 case 'b': /* base register */
8137 case 'd': /* destination register */
8138 case 's': /* source register */
8139 case 't': /* target register */
8140 case 'r': /* both target and source */
8141 case 'v': /* both dest and source */
8142 case 'w': /* both dest and target */
8143 case 'E': /* coprocessor target register */
8144 case 'G': /* coprocessor destination register */
8145 case 'x': /* ignore register name */
8146 case 'z': /* must be zero register */
8147 case 'U': /* destination register (clo/clz). */
8162 while (ISDIGIT (*s
));
8164 as_bad (_("Invalid register number (%d)"), regno
);
8166 else if (*args
== 'E' || *args
== 'G')
8170 if (s
[1] == 'r' && s
[2] == 'a')
8175 else if (s
[1] == 'f' && s
[2] == 'p')
8180 else if (s
[1] == 's' && s
[2] == 'p')
8185 else if (s
[1] == 'g' && s
[2] == 'p')
8190 else if (s
[1] == 'a' && s
[2] == 't')
8195 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '0')
8200 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '1')
8205 else if (s
[1] == 'z' && s
[2] == 'e' && s
[3] == 'r' && s
[4] == 'o')
8210 else if (itbl_have_entries
)
8215 p
= s
+ 1; /* advance past '$' */
8216 n
= itbl_get_field (&p
); /* n is name */
8218 /* See if this is a register defined in an
8220 if (itbl_get_reg_val (n
, &r
))
8222 /* Get_field advances to the start of
8223 the next field, so we need to back
8224 rack to the end of the last field. */
8228 s
= strchr (s
, '\0');
8241 as_warn (_("Used $at without \".set noat\""));
8247 if (c
== 'r' || c
== 'v' || c
== 'w')
8254 /* 'z' only matches $0. */
8255 if (c
== 'z' && regno
!= 0)
8258 /* Now that we have assembled one operand, we use the args string
8259 * to figure out where it goes in the instruction. */
8266 ip
->insn_opcode
|= regno
<< OP_SH_RS
;
8270 ip
->insn_opcode
|= regno
<< OP_SH_RD
;
8273 ip
->insn_opcode
|= regno
<< OP_SH_RD
;
8274 ip
->insn_opcode
|= regno
<< OP_SH_RT
;
8279 ip
->insn_opcode
|= regno
<< OP_SH_RT
;
8282 /* This case exists because on the r3000 trunc
8283 expands into a macro which requires a gp
8284 register. On the r6000 or r4000 it is
8285 assembled into a single instruction which
8286 ignores the register. Thus the insn version
8287 is MIPS_ISA2 and uses 'x', and the macro
8288 version is MIPS_ISA1 and uses 't'. */
8291 /* This case is for the div instruction, which
8292 acts differently if the destination argument
8293 is $0. This only matches $0, and is checked
8294 outside the switch. */
8297 /* Itbl operand; not yet implemented. FIXME ?? */
8299 /* What about all other operands like 'i', which
8300 can be specified in the opcode table? */
8310 ip
->insn_opcode
|= lastregno
<< OP_SH_RS
;
8313 ip
->insn_opcode
|= lastregno
<< OP_SH_RT
;
8318 case 'O': /* MDMX alignment immediate constant. */
8319 my_getExpression (&imm_expr
, s
);
8320 check_absolute_expr (ip
, &imm_expr
);
8321 if ((unsigned long) imm_expr
.X_add_number
> OP_MASK_ALN
)
8323 as_warn ("Improper align amount (%ld), using low bits",
8324 (long) imm_expr
.X_add_number
);
8325 imm_expr
.X_add_number
&= OP_MASK_ALN
;
8327 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_ALN
;
8328 imm_expr
.X_op
= O_absent
;
8332 case 'Q': /* MDMX vector, element sel, or const. */
8335 /* MDMX Immediate. */
8336 my_getExpression (&imm_expr
, s
);
8337 check_absolute_expr (ip
, &imm_expr
);
8338 if ((unsigned long) imm_expr
.X_add_number
> OP_MASK_FT
)
8340 as_warn (_("Invalid MDMX Immediate (%ld)"),
8341 (long) imm_expr
.X_add_number
);
8342 imm_expr
.X_add_number
&= OP_MASK_FT
;
8344 imm_expr
.X_add_number
&= OP_MASK_FT
;
8345 if (ip
->insn_opcode
& (OP_MASK_VSEL
<< OP_SH_VSEL
))
8346 ip
->insn_opcode
|= MDMX_FMTSEL_IMM_QH
<< OP_SH_VSEL
;
8348 ip
->insn_opcode
|= MDMX_FMTSEL_IMM_OB
<< OP_SH_VSEL
;
8349 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_FT
;
8350 imm_expr
.X_op
= O_absent
;
8354 /* Not MDMX Immediate. Fall through. */
8355 case 'X': /* MDMX destination register. */
8356 case 'Y': /* MDMX source register. */
8357 case 'Z': /* MDMX target register. */
8359 case 'D': /* floating point destination register */
8360 case 'S': /* floating point source register */
8361 case 'T': /* floating point target register */
8362 case 'R': /* floating point source register */
8366 /* Accept $fN for FP and MDMX register numbers, and in
8367 addition accept $vN for MDMX register numbers. */
8368 if ((s
[0] == '$' && s
[1] == 'f' && ISDIGIT (s
[2]))
8369 || (is_mdmx
!= 0 && s
[0] == '$' && s
[1] == 'v'
8380 while (ISDIGIT (*s
));
8383 as_bad (_("Invalid float register number (%d)"), regno
);
8385 if ((regno
& 1) != 0
8387 && ! (strcmp (str
, "mtc1") == 0
8388 || strcmp (str
, "mfc1") == 0
8389 || strcmp (str
, "lwc1") == 0
8390 || strcmp (str
, "swc1") == 0
8391 || strcmp (str
, "l.s") == 0
8392 || strcmp (str
, "s.s") == 0))
8393 as_warn (_("Float register should be even, was %d"),
8401 if (c
== 'V' || c
== 'W')
8412 ip
->insn_opcode
|= regno
<< OP_SH_FD
;
8417 ip
->insn_opcode
|= regno
<< OP_SH_FS
;
8420 /* This is like 'Z', but also needs to fix the MDMX
8421 vector/scalar select bits. Note that the
8422 scalar immediate case is handled above. */
8425 int is_qh
= (ip
->insn_opcode
& (1 << OP_SH_VSEL
));
8426 int max_el
= (is_qh
? 3 : 7);
8428 my_getExpression(&imm_expr
, s
);
8429 check_absolute_expr (ip
, &imm_expr
);
8431 if (imm_expr
.X_add_number
> max_el
)
8432 as_bad(_("Bad element selector %ld"),
8433 (long) imm_expr
.X_add_number
);
8434 imm_expr
.X_add_number
&= max_el
;
8435 ip
->insn_opcode
|= (imm_expr
.X_add_number
8439 as_warn(_("Expecting ']' found '%s'"), s
);
8445 if (ip
->insn_opcode
& (OP_MASK_VSEL
<< OP_SH_VSEL
))
8446 ip
->insn_opcode
|= (MDMX_FMTSEL_VEC_QH
8449 ip
->insn_opcode
|= (MDMX_FMTSEL_VEC_OB
<<
8456 ip
->insn_opcode
|= regno
<< OP_SH_FT
;
8459 ip
->insn_opcode
|= regno
<< OP_SH_FR
;
8469 ip
->insn_opcode
|= lastregno
<< OP_SH_FS
;
8472 ip
->insn_opcode
|= lastregno
<< OP_SH_FT
;
8478 my_getExpression (&imm_expr
, s
);
8479 if (imm_expr
.X_op
!= O_big
8480 && imm_expr
.X_op
!= O_constant
)
8481 insn_error
= _("absolute expression required");
8486 my_getExpression (&offset_expr
, s
);
8487 *imm_reloc
= BFD_RELOC_32
;
8500 unsigned char temp
[8];
8502 unsigned int length
;
8507 /* These only appear as the last operand in an
8508 instruction, and every instruction that accepts
8509 them in any variant accepts them in all variants.
8510 This means we don't have to worry about backing out
8511 any changes if the instruction does not match.
8513 The difference between them is the size of the
8514 floating point constant and where it goes. For 'F'
8515 and 'L' the constant is 64 bits; for 'f' and 'l' it
8516 is 32 bits. Where the constant is placed is based
8517 on how the MIPS assembler does things:
8520 f -- immediate value
8523 The .lit4 and .lit8 sections are only used if
8524 permitted by the -G argument.
8526 When generating embedded PIC code, we use the
8527 .lit8 section but not the .lit4 section (we can do
8528 .lit4 inline easily; we need to put .lit8
8529 somewhere in the data segment, and using .lit8
8530 permits the linker to eventually combine identical
8533 The code below needs to know whether the target register
8534 is 32 or 64 bits wide. It relies on the fact 'f' and
8535 'F' are used with GPR-based instructions and 'l' and
8536 'L' are used with FPR-based instructions. */
8538 f64
= *args
== 'F' || *args
== 'L';
8539 using_gprs
= *args
== 'F' || *args
== 'f';
8541 save_in
= input_line_pointer
;
8542 input_line_pointer
= s
;
8543 err
= md_atof (f64
? 'd' : 'f', (char *) temp
, &len
);
8545 s
= input_line_pointer
;
8546 input_line_pointer
= save_in
;
8547 if (err
!= NULL
&& *err
!= '\0')
8549 as_bad (_("Bad floating point constant: %s"), err
);
8550 memset (temp
, '\0', sizeof temp
);
8551 length
= f64
? 8 : 4;
8554 assert (length
== (unsigned) (f64
? 8 : 4));
8558 && (! USE_GLOBAL_POINTER_OPT
8559 || mips_pic
== EMBEDDED_PIC
8560 || g_switch_value
< 4
8561 || (temp
[0] == 0 && temp
[1] == 0)
8562 || (temp
[2] == 0 && temp
[3] == 0))))
8564 imm_expr
.X_op
= O_constant
;
8565 if (! target_big_endian
)
8566 imm_expr
.X_add_number
= bfd_getl32 (temp
);
8568 imm_expr
.X_add_number
= bfd_getb32 (temp
);
8571 && ! mips_disable_float_construction
8572 /* Constants can only be constructed in GPRs and
8573 copied to FPRs if the GPRs are at least as wide
8574 as the FPRs. Force the constant into memory if
8575 we are using 64-bit FPRs but the GPRs are only
8578 || ! (HAVE_64BIT_FPRS
&& HAVE_32BIT_GPRS
))
8579 && ((temp
[0] == 0 && temp
[1] == 0)
8580 || (temp
[2] == 0 && temp
[3] == 0))
8581 && ((temp
[4] == 0 && temp
[5] == 0)
8582 || (temp
[6] == 0 && temp
[7] == 0)))
8584 /* The value is simple enough to load with a couple of
8585 instructions. If using 32-bit registers, set
8586 imm_expr to the high order 32 bits and offset_expr to
8587 the low order 32 bits. Otherwise, set imm_expr to
8588 the entire 64 bit constant. */
8589 if (using_gprs
? HAVE_32BIT_GPRS
: HAVE_32BIT_FPRS
)
8591 imm_expr
.X_op
= O_constant
;
8592 offset_expr
.X_op
= O_constant
;
8593 if (! target_big_endian
)
8595 imm_expr
.X_add_number
= bfd_getl32 (temp
+ 4);
8596 offset_expr
.X_add_number
= bfd_getl32 (temp
);
8600 imm_expr
.X_add_number
= bfd_getb32 (temp
);
8601 offset_expr
.X_add_number
= bfd_getb32 (temp
+ 4);
8603 if (offset_expr
.X_add_number
== 0)
8604 offset_expr
.X_op
= O_absent
;
8606 else if (sizeof (imm_expr
.X_add_number
) > 4)
8608 imm_expr
.X_op
= O_constant
;
8609 if (! target_big_endian
)
8610 imm_expr
.X_add_number
= bfd_getl64 (temp
);
8612 imm_expr
.X_add_number
= bfd_getb64 (temp
);
8616 imm_expr
.X_op
= O_big
;
8617 imm_expr
.X_add_number
= 4;
8618 if (! target_big_endian
)
8620 generic_bignum
[0] = bfd_getl16 (temp
);
8621 generic_bignum
[1] = bfd_getl16 (temp
+ 2);
8622 generic_bignum
[2] = bfd_getl16 (temp
+ 4);
8623 generic_bignum
[3] = bfd_getl16 (temp
+ 6);
8627 generic_bignum
[0] = bfd_getb16 (temp
+ 6);
8628 generic_bignum
[1] = bfd_getb16 (temp
+ 4);
8629 generic_bignum
[2] = bfd_getb16 (temp
+ 2);
8630 generic_bignum
[3] = bfd_getb16 (temp
);
8636 const char *newname
;
8639 /* Switch to the right section. */
8641 subseg
= now_subseg
;
8644 default: /* unused default case avoids warnings. */
8646 newname
= RDATA_SECTION_NAME
;
8647 if ((USE_GLOBAL_POINTER_OPT
&& g_switch_value
>= 8)
8648 || mips_pic
== EMBEDDED_PIC
)
8652 if (mips_pic
== EMBEDDED_PIC
)
8655 newname
= RDATA_SECTION_NAME
;
8658 assert (!USE_GLOBAL_POINTER_OPT
8659 || g_switch_value
>= 4);
8663 new_seg
= subseg_new (newname
, (subsegT
) 0);
8664 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
8665 bfd_set_section_flags (stdoutput
, new_seg
,
8670 frag_align (*args
== 'l' ? 2 : 3, 0, 0);
8671 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
8672 && strcmp (TARGET_OS
, "elf") != 0)
8673 record_alignment (new_seg
, 4);
8675 record_alignment (new_seg
, *args
== 'l' ? 2 : 3);
8677 as_bad (_("Can't use floating point insn in this section"));
8679 /* Set the argument to the current address in the
8681 offset_expr
.X_op
= O_symbol
;
8682 offset_expr
.X_add_symbol
=
8683 symbol_new ("L0\001", now_seg
,
8684 (valueT
) frag_now_fix (), frag_now
);
8685 offset_expr
.X_add_number
= 0;
8687 /* Put the floating point number into the section. */
8688 p
= frag_more ((int) length
);
8689 memcpy (p
, temp
, length
);
8691 /* Switch back to the original section. */
8692 subseg_set (seg
, subseg
);
8697 case 'i': /* 16 bit unsigned immediate */
8698 case 'j': /* 16 bit signed immediate */
8699 *imm_reloc
= BFD_RELOC_LO16
;
8700 c
= my_getSmallExpression (&imm_expr
, s
);
8707 *imm_reloc
= BFD_RELOC_HI16_S
;
8708 imm_unmatched_hi
= true;
8711 else if (c
== S_EX_HIGHEST
)
8712 *imm_reloc
= BFD_RELOC_MIPS_HIGHEST
;
8713 else if (c
== S_EX_HIGHER
)
8714 *imm_reloc
= BFD_RELOC_MIPS_HIGHER
;
8715 else if (c
== S_EX_GP_REL
)
8717 /* This occurs in NewABI only. */
8718 c
= my_getSmallExpression (&imm_expr
, s
);
8720 as_bad (_("bad composition of relocations"));
8723 c
= my_getSmallExpression (&imm_expr
, s
);
8725 as_bad (_("bad composition of relocations"));
8728 imm_reloc
[0] = BFD_RELOC_GPREL16
;
8729 imm_reloc
[1] = BFD_RELOC_MIPS_SUB
;
8730 imm_reloc
[2] = BFD_RELOC_LO16
;
8736 *imm_reloc
= BFD_RELOC_HI16
;
8738 else if (imm_expr
.X_op
== O_constant
)
8739 imm_expr
.X_add_number
&= 0xffff;
8743 if ((c
== S_EX_NONE
&& imm_expr
.X_op
!= O_constant
)
8744 || ((imm_expr
.X_add_number
< 0
8745 || imm_expr
.X_add_number
>= 0x10000)
8746 && imm_expr
.X_op
== O_constant
))
8748 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
8749 !strcmp (insn
->name
, insn
[1].name
))
8751 if (imm_expr
.X_op
== O_constant
8752 || imm_expr
.X_op
== O_big
)
8753 as_bad (_("16 bit expression not in range 0..65535"));
8761 /* The upper bound should be 0x8000, but
8762 unfortunately the MIPS assembler accepts numbers
8763 from 0x8000 to 0xffff and sign extends them, and
8764 we want to be compatible. We only permit this
8765 extended range for an instruction which does not
8766 provide any further alternates, since those
8767 alternates may handle other cases. People should
8768 use the numbers they mean, rather than relying on
8769 a mysterious sign extension. */
8770 more
= (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
8771 strcmp (insn
->name
, insn
[1].name
) == 0);
8776 if ((c
== S_EX_NONE
&& imm_expr
.X_op
!= O_constant
)
8777 || ((imm_expr
.X_add_number
< -0x8000
8778 || imm_expr
.X_add_number
>= max
)
8779 && imm_expr
.X_op
== O_constant
)
8781 && imm_expr
.X_add_number
< 0
8783 && imm_expr
.X_unsigned
8784 && sizeof (imm_expr
.X_add_number
) <= 4))
8788 if (imm_expr
.X_op
== O_constant
8789 || imm_expr
.X_op
== O_big
)
8790 as_bad (_("16 bit expression not in range -32768..32767"));
8796 case 'o': /* 16 bit offset */
8797 c
= my_getSmallExpression (&offset_expr
, s
);
8799 /* If this value won't fit into a 16 bit offset, then go
8800 find a macro that will generate the 32 bit offset
8803 && (offset_expr
.X_op
!= O_constant
8804 || offset_expr
.X_add_number
>= 0x8000
8805 || offset_expr
.X_add_number
< -0x8000))
8810 if (offset_expr
.X_op
!= O_constant
)
8812 offset_expr
.X_add_number
=
8813 (offset_expr
.X_add_number
>> 16) & 0xffff;
8815 *offset_reloc
= BFD_RELOC_LO16
;
8819 case 'p': /* pc relative offset */
8820 if (mips_pic
== EMBEDDED_PIC
)
8821 *offset_reloc
= BFD_RELOC_16_PCREL_S2
;
8823 *offset_reloc
= BFD_RELOC_16_PCREL
;
8824 my_getExpression (&offset_expr
, s
);
8828 case 'u': /* upper 16 bits */
8829 c
= my_getSmallExpression (&imm_expr
, s
);
8830 *imm_reloc
= BFD_RELOC_LO16
;
8837 *imm_reloc
= BFD_RELOC_HI16_S
;
8838 imm_unmatched_hi
= true;
8841 else if (c
== S_EX_HIGHEST
)
8842 *imm_reloc
= BFD_RELOC_MIPS_HIGHEST
;
8843 else if (c
== S_EX_GP_REL
)
8845 /* This occurs in NewABI only. */
8846 c
= my_getSmallExpression (&imm_expr
, s
);
8848 as_bad (_("bad composition of relocations"));
8851 c
= my_getSmallExpression (&imm_expr
, s
);
8853 as_bad (_("bad composition of relocations"));
8856 imm_reloc
[0] = BFD_RELOC_GPREL16
;
8857 imm_reloc
[1] = BFD_RELOC_MIPS_SUB
;
8858 imm_reloc
[2] = BFD_RELOC_HI16_S
;
8864 *imm_reloc
= BFD_RELOC_HI16
;
8866 else if (imm_expr
.X_op
== O_constant
)
8867 imm_expr
.X_add_number
&= 0xffff;
8869 else if (imm_expr
.X_op
== O_constant
8870 && (imm_expr
.X_add_number
< 0
8871 || imm_expr
.X_add_number
>= 0x10000))
8872 as_bad (_("lui expression not in range 0..65535"));
8876 case 'a': /* 26 bit address */
8877 my_getExpression (&offset_expr
, s
);
8879 *offset_reloc
= BFD_RELOC_MIPS_JMP
;
8882 case 'N': /* 3 bit branch condition code */
8883 case 'M': /* 3 bit compare condition code */
8884 if (strncmp (s
, "$fcc", 4) != 0)
8894 while (ISDIGIT (*s
));
8896 as_bad (_("invalid condition code register $fcc%d"), regno
);
8898 ip
->insn_opcode
|= regno
<< OP_SH_BCC
;
8900 ip
->insn_opcode
|= regno
<< OP_SH_CCC
;
8904 if (s
[0] == '0' && (s
[1] == 'x' || s
[1] == 'X'))
8915 while (ISDIGIT (*s
));
8918 c
= 8; /* Invalid sel value. */
8921 as_bad (_("invalid coprocessor sub-selection value (0-7)"));
8922 ip
->insn_opcode
|= c
;
8926 /* Must be at least one digit. */
8927 my_getExpression (&imm_expr
, s
);
8928 check_absolute_expr (ip
, &imm_expr
);
8930 if ((unsigned long) imm_expr
.X_add_number
8931 > (unsigned long) OP_MASK_VECBYTE
)
8933 as_bad (_("bad byte vector index (%ld)"),
8934 (long) imm_expr
.X_add_number
);
8935 imm_expr
.X_add_number
= 0;
8938 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_VECBYTE
;
8939 imm_expr
.X_op
= O_absent
;
8944 my_getExpression (&imm_expr
, s
);
8945 check_absolute_expr (ip
, &imm_expr
);
8947 if ((unsigned long) imm_expr
.X_add_number
8948 > (unsigned long) OP_MASK_VECALIGN
)
8950 as_bad (_("bad byte vector index (%ld)"),
8951 (long) imm_expr
.X_add_number
);
8952 imm_expr
.X_add_number
= 0;
8955 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_VECALIGN
;
8956 imm_expr
.X_op
= O_absent
;
8961 as_bad (_("bad char = '%c'\n"), *args
);
8966 /* Args don't match. */
8967 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
8968 !strcmp (insn
->name
, insn
[1].name
))
8972 insn_error
= _("illegal operands");
8977 insn_error
= _("illegal operands");
8982 /* This routine assembles an instruction into its binary format when
8983 assembling for the mips16. As a side effect, it sets one of the
8984 global variables imm_reloc or offset_reloc to the type of
8985 relocation to do if one of the operands is an address expression.
8986 It also sets mips16_small and mips16_ext if the user explicitly
8987 requested a small or extended instruction. */
8992 struct mips_cl_insn
*ip
;
8996 struct mips_opcode
*insn
;
8999 unsigned int lastregno
= 0;
9004 mips16_small
= false;
9007 for (s
= str
; ISLOWER (*s
); ++s
)
9019 if (s
[1] == 't' && s
[2] == ' ')
9022 mips16_small
= true;
9026 else if (s
[1] == 'e' && s
[2] == ' ')
9035 insn_error
= _("unknown opcode");
9039 if (mips_opts
.noautoextend
&& ! mips16_ext
)
9040 mips16_small
= true;
9042 if ((insn
= (struct mips_opcode
*) hash_find (mips16_op_hash
, str
)) == NULL
)
9044 insn_error
= _("unrecognized opcode");
9051 assert (strcmp (insn
->name
, str
) == 0);
9054 ip
->insn_opcode
= insn
->match
;
9055 ip
->use_extend
= false;
9056 imm_expr
.X_op
= O_absent
;
9057 imm_reloc
[0] = BFD_RELOC_UNUSED
;
9058 imm_reloc
[1] = BFD_RELOC_UNUSED
;
9059 imm_reloc
[2] = BFD_RELOC_UNUSED
;
9060 offset_expr
.X_op
= O_absent
;
9061 offset_reloc
[0] = BFD_RELOC_UNUSED
;
9062 offset_reloc
[1] = BFD_RELOC_UNUSED
;
9063 offset_reloc
[2] = BFD_RELOC_UNUSED
;
9064 for (args
= insn
->args
; 1; ++args
)
9071 /* In this switch statement we call break if we did not find
9072 a match, continue if we did find a match, or return if we
9081 /* Stuff the immediate value in now, if we can. */
9082 if (imm_expr
.X_op
== O_constant
9083 && *imm_reloc
> BFD_RELOC_UNUSED
9084 && insn
->pinfo
!= INSN_MACRO
)
9086 mips16_immed (NULL
, 0, *imm_reloc
- BFD_RELOC_UNUSED
,
9087 imm_expr
.X_add_number
, true, mips16_small
,
9088 mips16_ext
, &ip
->insn_opcode
,
9089 &ip
->use_extend
, &ip
->extend
);
9090 imm_expr
.X_op
= O_absent
;
9091 *imm_reloc
= BFD_RELOC_UNUSED
;
9105 ip
->insn_opcode
|= lastregno
<< MIPS16OP_SH_RX
;
9108 ip
->insn_opcode
|= lastregno
<< MIPS16OP_SH_RY
;
9124 ip
->insn_opcode
|= lastregno
<< MIPS16OP_SH_RX
;
9126 ip
->insn_opcode
|= lastregno
<< MIPS16OP_SH_RY
;
9153 while (ISDIGIT (*s
));
9156 as_bad (_("invalid register number (%d)"), regno
);
9162 if (s
[1] == 'r' && s
[2] == 'a')
9167 else if (s
[1] == 'f' && s
[2] == 'p')
9172 else if (s
[1] == 's' && s
[2] == 'p')
9177 else if (s
[1] == 'g' && s
[2] == 'p')
9182 else if (s
[1] == 'a' && s
[2] == 't')
9187 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '0')
9192 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '1')
9197 else if (s
[1] == 'z' && s
[2] == 'e' && s
[3] == 'r' && s
[4] == 'o')
9210 if (c
== 'v' || c
== 'w')
9212 regno
= mips16_to_32_reg_map
[lastregno
];
9226 regno
= mips32_to_16_reg_map
[regno
];
9231 regno
= ILLEGAL_REG
;
9236 regno
= ILLEGAL_REG
;
9241 regno
= ILLEGAL_REG
;
9246 if (regno
== AT
&& ! mips_opts
.noat
)
9247 as_warn (_("used $at without \".set noat\""));
9254 if (regno
== ILLEGAL_REG
)
9261 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_RX
;
9265 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_RY
;
9268 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_RZ
;
9271 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_MOVE32Z
;
9277 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_REGR32
;
9280 regno
= ((regno
& 7) << 2) | ((regno
& 0x18) >> 3);
9281 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_REG32R
;
9291 if (strncmp (s
, "$pc", 3) == 0)
9315 && strncmp (s
+ 1, "gprel(", sizeof "gprel(" - 1) == 0)
9317 /* This is %gprel(SYMBOL). We need to read SYMBOL,
9318 and generate the appropriate reloc. If the text
9319 inside %gprel is not a symbol name with an
9320 optional offset, then we generate a normal reloc
9321 and will probably fail later. */
9322 my_getExpression (&imm_expr
, s
+ sizeof "%gprel" - 1);
9323 if (imm_expr
.X_op
== O_symbol
)
9326 *imm_reloc
= BFD_RELOC_MIPS16_GPREL
;
9328 ip
->use_extend
= true;
9335 /* Just pick up a normal expression. */
9336 my_getExpression (&imm_expr
, s
);
9339 if (imm_expr
.X_op
== O_register
)
9341 /* What we thought was an expression turned out to
9344 if (s
[0] == '(' && args
[1] == '(')
9346 /* It looks like the expression was omitted
9347 before a register indirection, which means
9348 that the expression is implicitly zero. We
9349 still set up imm_expr, so that we handle
9350 explicit extensions correctly. */
9351 imm_expr
.X_op
= O_constant
;
9352 imm_expr
.X_add_number
= 0;
9353 *imm_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
9360 /* We need to relax this instruction. */
9361 *imm_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
9370 /* We use offset_reloc rather than imm_reloc for the PC
9371 relative operands. This lets macros with both
9372 immediate and address operands work correctly. */
9373 my_getExpression (&offset_expr
, s
);
9375 if (offset_expr
.X_op
== O_register
)
9378 /* We need to relax this instruction. */
9379 *offset_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
9383 case '6': /* break code */
9384 my_getExpression (&imm_expr
, s
);
9385 check_absolute_expr (ip
, &imm_expr
);
9386 if ((unsigned long) imm_expr
.X_add_number
> 63)
9388 as_warn (_("Invalid value for `%s' (%lu)"),
9390 (unsigned long) imm_expr
.X_add_number
);
9391 imm_expr
.X_add_number
&= 0x3f;
9393 ip
->insn_opcode
|= imm_expr
.X_add_number
<< MIPS16OP_SH_IMM6
;
9394 imm_expr
.X_op
= O_absent
;
9398 case 'a': /* 26 bit address */
9399 my_getExpression (&offset_expr
, s
);
9401 *offset_reloc
= BFD_RELOC_MIPS16_JMP
;
9402 ip
->insn_opcode
<<= 16;
9405 case 'l': /* register list for entry macro */
9406 case 'L': /* register list for exit macro */
9416 int freg
, reg1
, reg2
;
9418 while (*s
== ' ' || *s
== ',')
9422 as_bad (_("can't parse register list"));
9434 while (ISDIGIT (*s
))
9456 as_bad (_("invalid register list"));
9461 while (ISDIGIT (*s
))
9468 if (freg
&& reg1
== 0 && reg2
== 0 && c
== 'L')
9473 else if (freg
&& reg1
== 0 && reg2
== 1 && c
== 'L')
9478 else if (reg1
== 4 && reg2
>= 4 && reg2
<= 7 && c
!= 'L')
9479 mask
|= (reg2
- 3) << 3;
9480 else if (reg1
== 16 && reg2
>= 16 && reg2
<= 17)
9481 mask
|= (reg2
- 15) << 1;
9482 else if (reg1
== RA
&& reg2
== RA
)
9486 as_bad (_("invalid register list"));
9490 /* The mask is filled in in the opcode table for the
9491 benefit of the disassembler. We remove it before
9492 applying the actual mask. */
9493 ip
->insn_opcode
&= ~ ((7 << 3) << MIPS16OP_SH_IMM6
);
9494 ip
->insn_opcode
|= mask
<< MIPS16OP_SH_IMM6
;
9498 case 'e': /* extend code */
9499 my_getExpression (&imm_expr
, s
);
9500 check_absolute_expr (ip
, &imm_expr
);
9501 if ((unsigned long) imm_expr
.X_add_number
> 0x7ff)
9503 as_warn (_("Invalid value for `%s' (%lu)"),
9505 (unsigned long) imm_expr
.X_add_number
);
9506 imm_expr
.X_add_number
&= 0x7ff;
9508 ip
->insn_opcode
|= imm_expr
.X_add_number
;
9509 imm_expr
.X_op
= O_absent
;
9519 /* Args don't match. */
9520 if (insn
+ 1 < &mips16_opcodes
[bfd_mips16_num_opcodes
] &&
9521 strcmp (insn
->name
, insn
[1].name
) == 0)
9528 insn_error
= _("illegal operands");
9534 /* This structure holds information we know about a mips16 immediate
9537 struct mips16_immed_operand
9539 /* The type code used in the argument string in the opcode table. */
9541 /* The number of bits in the short form of the opcode. */
9543 /* The number of bits in the extended form of the opcode. */
9545 /* The amount by which the short form is shifted when it is used;
9546 for example, the sw instruction has a shift count of 2. */
9548 /* The amount by which the short form is shifted when it is stored
9549 into the instruction code. */
9551 /* Non-zero if the short form is unsigned. */
9553 /* Non-zero if the extended form is unsigned. */
9555 /* Non-zero if the value is PC relative. */
9559 /* The mips16 immediate operand types. */
9561 static const struct mips16_immed_operand mips16_immed_operands
[] =
9563 { '<', 3, 5, 0, MIPS16OP_SH_RZ
, 1, 1, 0 },
9564 { '>', 3, 5, 0, MIPS16OP_SH_RX
, 1, 1, 0 },
9565 { '[', 3, 6, 0, MIPS16OP_SH_RZ
, 1, 1, 0 },
9566 { ']', 3, 6, 0, MIPS16OP_SH_RX
, 1, 1, 0 },
9567 { '4', 4, 15, 0, MIPS16OP_SH_IMM4
, 0, 0, 0 },
9568 { '5', 5, 16, 0, MIPS16OP_SH_IMM5
, 1, 0, 0 },
9569 { 'H', 5, 16, 1, MIPS16OP_SH_IMM5
, 1, 0, 0 },
9570 { 'W', 5, 16, 2, MIPS16OP_SH_IMM5
, 1, 0, 0 },
9571 { 'D', 5, 16, 3, MIPS16OP_SH_IMM5
, 1, 0, 0 },
9572 { 'j', 5, 16, 0, MIPS16OP_SH_IMM5
, 0, 0, 0 },
9573 { '8', 8, 16, 0, MIPS16OP_SH_IMM8
, 1, 0, 0 },
9574 { 'V', 8, 16, 2, MIPS16OP_SH_IMM8
, 1, 0, 0 },
9575 { 'C', 8, 16, 3, MIPS16OP_SH_IMM8
, 1, 0, 0 },
9576 { 'U', 8, 16, 0, MIPS16OP_SH_IMM8
, 1, 1, 0 },
9577 { 'k', 8, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 0 },
9578 { 'K', 8, 16, 3, MIPS16OP_SH_IMM8
, 0, 0, 0 },
9579 { 'p', 8, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 1 },
9580 { 'q', 11, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 1 },
9581 { 'A', 8, 16, 2, MIPS16OP_SH_IMM8
, 1, 0, 1 },
9582 { 'B', 5, 16, 3, MIPS16OP_SH_IMM5
, 1, 0, 1 },
9583 { 'E', 5, 16, 2, MIPS16OP_SH_IMM5
, 1, 0, 1 }
9586 #define MIPS16_NUM_IMMED \
9587 (sizeof mips16_immed_operands / sizeof mips16_immed_operands[0])
9589 /* Handle a mips16 instruction with an immediate value. This or's the
9590 small immediate value into *INSN. It sets *USE_EXTEND to indicate
9591 whether an extended value is needed; if one is needed, it sets
9592 *EXTEND to the value. The argument type is TYPE. The value is VAL.
9593 If SMALL is true, an unextended opcode was explicitly requested.
9594 If EXT is true, an extended opcode was explicitly requested. If
9595 WARN is true, warn if EXT does not match reality. */
9598 mips16_immed (file
, line
, type
, val
, warn
, small
, ext
, insn
, use_extend
,
9607 unsigned long *insn
;
9608 boolean
*use_extend
;
9609 unsigned short *extend
;
9611 register const struct mips16_immed_operand
*op
;
9612 int mintiny
, maxtiny
;
9615 op
= mips16_immed_operands
;
9616 while (op
->type
!= type
)
9619 assert (op
< mips16_immed_operands
+ MIPS16_NUM_IMMED
);
9624 if (type
== '<' || type
== '>' || type
== '[' || type
== ']')
9627 maxtiny
= 1 << op
->nbits
;
9632 maxtiny
= (1 << op
->nbits
) - 1;
9637 mintiny
= - (1 << (op
->nbits
- 1));
9638 maxtiny
= (1 << (op
->nbits
- 1)) - 1;
9641 /* Branch offsets have an implicit 0 in the lowest bit. */
9642 if (type
== 'p' || type
== 'q')
9645 if ((val
& ((1 << op
->shift
) - 1)) != 0
9646 || val
< (mintiny
<< op
->shift
)
9647 || val
> (maxtiny
<< op
->shift
))
9652 if (warn
&& ext
&& ! needext
)
9653 as_warn_where (file
, line
,
9654 _("extended operand requested but not required"));
9655 if (small
&& needext
)
9656 as_bad_where (file
, line
, _("invalid unextended operand value"));
9658 if (small
|| (! ext
&& ! needext
))
9662 *use_extend
= false;
9663 insnval
= ((val
>> op
->shift
) & ((1 << op
->nbits
) - 1));
9664 insnval
<<= op
->op_shift
;
9669 long minext
, maxext
;
9675 maxext
= (1 << op
->extbits
) - 1;
9679 minext
= - (1 << (op
->extbits
- 1));
9680 maxext
= (1 << (op
->extbits
- 1)) - 1;
9682 if (val
< minext
|| val
> maxext
)
9683 as_bad_where (file
, line
,
9684 _("operand value out of range for instruction"));
9687 if (op
->extbits
== 16)
9689 extval
= ((val
>> 11) & 0x1f) | (val
& 0x7e0);
9692 else if (op
->extbits
== 15)
9694 extval
= ((val
>> 11) & 0xf) | (val
& 0x7f0);
9699 extval
= ((val
& 0x1f) << 6) | (val
& 0x20);
9703 *extend
= (unsigned short) extval
;
9708 static struct percent_op_match
9711 const enum small_ex_type type
;
9716 {"%call_hi", S_EX_CALL_HI
},
9717 {"%call_lo", S_EX_CALL_LO
},
9718 {"%call16", S_EX_CALL16
},
9719 {"%got_disp", S_EX_GOT_DISP
},
9720 {"%got_page", S_EX_GOT_PAGE
},
9721 {"%got_ofst", S_EX_GOT_OFST
},
9722 {"%got_hi", S_EX_GOT_HI
},
9723 {"%got_lo", S_EX_GOT_LO
},
9725 {"%gp_rel", S_EX_GP_REL
},
9726 {"%half", S_EX_HALF
},
9727 {"%highest", S_EX_HIGHEST
},
9728 {"%higher", S_EX_HIGHER
},
9734 /* Parse small expression input. STR gets adjusted to eat up whitespace.
9735 It detects valid "%percent_op(...)" and "($reg)" strings. Percent_op's
9736 can be nested, this is handled by blanking the innermost, parsing the
9737 rest by subsequent calls. */
9740 my_getSmallParser (str
, len
, nestlevel
)
9746 *str
+= strspn (*str
, " \t");
9747 /* Check for expression in parentheses. */
9750 char *b
= *str
+ 1 + strspn (*str
+ 1, " \t");
9753 /* Check for base register. */
9757 && (e
= b
+ strcspn (b
, ") \t"))
9758 && e
- b
> 1 && e
- b
< 4)
9761 && ((b
[1] == 'f' && b
[2] == 'p')
9762 || (b
[1] == 's' && b
[2] == 'p')
9763 || (b
[1] == 'g' && b
[2] == 'p')
9764 || (b
[1] == 'a' && b
[2] == 't')
9766 && ISDIGIT (b
[2]))))
9767 || (ISDIGIT (b
[1])))
9769 *len
= strcspn (*str
, ")") + 1;
9770 return S_EX_REGISTER
;
9774 /* Check for percent_op (in parentheses). */
9775 else if (b
[0] == '%')
9778 return my_getPercentOp (str
, len
, nestlevel
);
9781 /* Some other expression in the parentheses, which can contain
9782 parentheses itself. Attempt to find the matching one. */
9788 for (s
= *str
+ 1; *s
&& pcnt
; s
++, (*len
)++)
9797 /* Check for percent_op (outside of parentheses). */
9798 else if (*str
[0] == '%')
9799 return my_getPercentOp (str
, len
, nestlevel
);
9801 /* Any other expression. */
9806 my_getPercentOp (str
, len
, nestlevel
)
9811 char *tmp
= *str
+ 1;
9814 while (ISALPHA (*tmp
) || *tmp
== '_')
9816 *tmp
= TOLOWER (*tmp
);
9819 while (i
< (sizeof (percent_op
) / sizeof (struct percent_op_match
)))
9821 if (strncmp (*str
, percent_op
[i
].str
, strlen (percent_op
[i
].str
)))
9825 int type
= percent_op
[i
].type
;
9827 /* Only %hi and %lo are allowed for OldABI. */
9828 if (! HAVE_NEWABI
&& type
!= S_EX_HI
&& type
!= S_EX_LO
)
9831 *len
= strlen (percent_op
[i
].str
);
9840 my_getSmallExpression (ep
, str
)
9844 static char *oldstr
= NULL
;
9850 /* Don't update oldstr if the last call had nested percent_op's. We need
9851 it to parse the outer ones later. */
9858 c
= my_getSmallParser (&str
, &len
, &nestlevel
);
9859 if (c
!= S_EX_NONE
&& c
!= S_EX_REGISTER
)
9862 while (c
!= S_EX_NONE
&& c
!= S_EX_REGISTER
);
9866 /* A percent_op was encountered. Don't try to get an expression if
9867 it is already blanked out. */
9868 if (*(str
+ strspn (str
+ 1, " )")) != ')')
9872 /* Let my_getExpression() stop at the closing parenthesis. */
9873 save
= *(str
+ len
);
9874 *(str
+ len
) = '\0';
9875 my_getExpression (ep
, str
);
9876 *(str
+ len
) = save
;
9880 /* Blank out including the % sign and the proper matching
9883 char *s
= strrchr (oldstr
, '%');
9886 for (end
= strchr (s
, '(') + 1; *end
&& pcnt
; end
++)
9890 else if (*end
== ')')
9894 memset (s
, ' ', end
- s
);
9898 expr_end
= str
+ len
;
9902 else if (c
== S_EX_NONE
)
9904 my_getExpression (ep
, str
);
9906 else if (c
== S_EX_REGISTER
)
9908 ep
->X_op
= O_constant
;
9910 ep
->X_add_symbol
= NULL
;
9911 ep
->X_op_symbol
= NULL
;
9912 ep
->X_add_number
= 0;
9916 as_fatal (_("internal error"));
9920 /* All percent_op's have been handled. */
9927 my_getExpression (ep
, str
)
9934 save_in
= input_line_pointer
;
9935 input_line_pointer
= str
;
9937 expr_end
= input_line_pointer
;
9938 input_line_pointer
= save_in
;
9940 /* If we are in mips16 mode, and this is an expression based on `.',
9941 then we bump the value of the symbol by 1 since that is how other
9942 text symbols are handled. We don't bother to handle complex
9943 expressions, just `.' plus or minus a constant. */
9944 if (mips_opts
.mips16
9945 && ep
->X_op
== O_symbol
9946 && strcmp (S_GET_NAME (ep
->X_add_symbol
), FAKE_LABEL_NAME
) == 0
9947 && S_GET_SEGMENT (ep
->X_add_symbol
) == now_seg
9948 && symbol_get_frag (ep
->X_add_symbol
) == frag_now
9949 && symbol_constant_p (ep
->X_add_symbol
)
9950 && (val
= S_GET_VALUE (ep
->X_add_symbol
)) == frag_now_fix ())
9951 S_SET_VALUE (ep
->X_add_symbol
, val
+ 1);
9954 /* Turn a string in input_line_pointer into a floating point constant
9955 of type TYPE, and store the appropriate bytes in *LITP. The number
9956 of LITTLENUMS emitted is stored in *SIZEP. An error message is
9957 returned, or NULL on OK. */
9960 md_atof (type
, litP
, sizeP
)
9966 LITTLENUM_TYPE words
[4];
9982 return _("bad call to md_atof");
9985 t
= atof_ieee (input_line_pointer
, type
, words
);
9987 input_line_pointer
= t
;
9991 if (! target_big_endian
)
9993 for (i
= prec
- 1; i
>= 0; i
--)
9995 md_number_to_chars (litP
, (valueT
) words
[i
], 2);
10001 for (i
= 0; i
< prec
; i
++)
10003 md_number_to_chars (litP
, (valueT
) words
[i
], 2);
10012 md_number_to_chars (buf
, val
, n
)
10017 if (target_big_endian
)
10018 number_to_chars_bigendian (buf
, val
, n
);
10020 number_to_chars_littleendian (buf
, val
, n
);
10024 static int support_64bit_objects(void)
10026 const char **list
, **l
;
10028 list
= bfd_target_list ();
10029 for (l
= list
; *l
!= NULL
; l
++)
10031 /* This is traditional mips */
10032 if (strcmp (*l
, "elf64-tradbigmips") == 0
10033 || strcmp (*l
, "elf64-tradlittlemips") == 0)
10035 if (strcmp (*l
, "elf64-bigmips") == 0
10036 || strcmp (*l
, "elf64-littlemips") == 0)
10040 return (*l
!= NULL
);
10042 #endif /* OBJ_ELF */
10044 const char *md_shortopts
= "nO::g::G:";
10046 struct option md_longopts
[] =
10048 #define OPTION_MIPS1 (OPTION_MD_BASE + 1)
10049 {"mips0", no_argument
, NULL
, OPTION_MIPS1
},
10050 {"mips1", no_argument
, NULL
, OPTION_MIPS1
},
10051 #define OPTION_MIPS2 (OPTION_MD_BASE + 2)
10052 {"mips2", no_argument
, NULL
, OPTION_MIPS2
},
10053 #define OPTION_MIPS3 (OPTION_MD_BASE + 3)
10054 {"mips3", no_argument
, NULL
, OPTION_MIPS3
},
10055 #define OPTION_MIPS4 (OPTION_MD_BASE + 4)
10056 {"mips4", no_argument
, NULL
, OPTION_MIPS4
},
10057 #define OPTION_MIPS5 (OPTION_MD_BASE + 5)
10058 {"mips5", no_argument
, NULL
, OPTION_MIPS5
},
10059 #define OPTION_MIPS32 (OPTION_MD_BASE + 6)
10060 {"mips32", no_argument
, NULL
, OPTION_MIPS32
},
10061 #define OPTION_MIPS64 (OPTION_MD_BASE + 7)
10062 {"mips64", no_argument
, NULL
, OPTION_MIPS64
},
10063 #define OPTION_MEMBEDDED_PIC (OPTION_MD_BASE + 8)
10064 {"membedded-pic", no_argument
, NULL
, OPTION_MEMBEDDED_PIC
},
10065 #define OPTION_TRAP (OPTION_MD_BASE + 9)
10066 {"trap", no_argument
, NULL
, OPTION_TRAP
},
10067 {"no-break", no_argument
, NULL
, OPTION_TRAP
},
10068 #define OPTION_BREAK (OPTION_MD_BASE + 10)
10069 {"break", no_argument
, NULL
, OPTION_BREAK
},
10070 {"no-trap", no_argument
, NULL
, OPTION_BREAK
},
10071 #define OPTION_EB (OPTION_MD_BASE + 11)
10072 {"EB", no_argument
, NULL
, OPTION_EB
},
10073 #define OPTION_EL (OPTION_MD_BASE + 12)
10074 {"EL", no_argument
, NULL
, OPTION_EL
},
10075 #define OPTION_MIPS16 (OPTION_MD_BASE + 13)
10076 {"mips16", no_argument
, NULL
, OPTION_MIPS16
},
10077 #define OPTION_NO_MIPS16 (OPTION_MD_BASE + 14)
10078 {"no-mips16", no_argument
, NULL
, OPTION_NO_MIPS16
},
10079 #define OPTION_M7000_HILO_FIX (OPTION_MD_BASE + 15)
10080 {"mfix7000", no_argument
, NULL
, OPTION_M7000_HILO_FIX
},
10081 #define OPTION_MNO_7000_HILO_FIX (OPTION_MD_BASE + 16)
10082 {"no-fix-7000", no_argument
, NULL
, OPTION_MNO_7000_HILO_FIX
},
10083 {"mno-fix7000", no_argument
, NULL
, OPTION_MNO_7000_HILO_FIX
},
10084 #define OPTION_FP32 (OPTION_MD_BASE + 17)
10085 {"mfp32", no_argument
, NULL
, OPTION_FP32
},
10086 #define OPTION_GP32 (OPTION_MD_BASE + 18)
10087 {"mgp32", no_argument
, NULL
, OPTION_GP32
},
10088 #define OPTION_CONSTRUCT_FLOATS (OPTION_MD_BASE + 19)
10089 {"construct-floats", no_argument
, NULL
, OPTION_CONSTRUCT_FLOATS
},
10090 #define OPTION_NO_CONSTRUCT_FLOATS (OPTION_MD_BASE + 20)
10091 {"no-construct-floats", no_argument
, NULL
, OPTION_NO_CONSTRUCT_FLOATS
},
10092 #define OPTION_MARCH (OPTION_MD_BASE + 21)
10093 {"march", required_argument
, NULL
, OPTION_MARCH
},
10094 #define OPTION_MTUNE (OPTION_MD_BASE + 22)
10095 {"mtune", required_argument
, NULL
, OPTION_MTUNE
},
10096 #define OPTION_FP64 (OPTION_MD_BASE + 23)
10097 {"mfp64", no_argument
, NULL
, OPTION_FP64
},
10098 #define OPTION_M4650 (OPTION_MD_BASE + 24)
10099 {"m4650", no_argument
, NULL
, OPTION_M4650
},
10100 #define OPTION_NO_M4650 (OPTION_MD_BASE + 25)
10101 {"no-m4650", no_argument
, NULL
, OPTION_NO_M4650
},
10102 #define OPTION_M4010 (OPTION_MD_BASE + 26)
10103 {"m4010", no_argument
, NULL
, OPTION_M4010
},
10104 #define OPTION_NO_M4010 (OPTION_MD_BASE + 27)
10105 {"no-m4010", no_argument
, NULL
, OPTION_NO_M4010
},
10106 #define OPTION_M4100 (OPTION_MD_BASE + 28)
10107 {"m4100", no_argument
, NULL
, OPTION_M4100
},
10108 #define OPTION_NO_M4100 (OPTION_MD_BASE + 29)
10109 {"no-m4100", no_argument
, NULL
, OPTION_NO_M4100
},
10110 #define OPTION_M3900 (OPTION_MD_BASE + 30)
10111 {"m3900", no_argument
, NULL
, OPTION_M3900
},
10112 #define OPTION_NO_M3900 (OPTION_MD_BASE + 31)
10113 {"no-m3900", no_argument
, NULL
, OPTION_NO_M3900
},
10114 #define OPTION_GP64 (OPTION_MD_BASE + 32)
10115 {"mgp64", no_argument
, NULL
, OPTION_GP64
},
10116 #define OPTION_MIPS3D (OPTION_MD_BASE + 33)
10117 {"mips3d", no_argument
, NULL
, OPTION_MIPS3D
},
10118 #define OPTION_NO_MIPS3D (OPTION_MD_BASE + 34)
10119 {"no-mips3d", no_argument
, NULL
, OPTION_NO_MIPS3D
},
10120 #define OPTION_MDMX (OPTION_MD_BASE + 35)
10121 {"mdmx", no_argument
, NULL
, OPTION_MDMX
},
10122 #define OPTION_NO_MDMX (OPTION_MD_BASE + 36)
10123 {"no-mdmx", no_argument
, NULL
, OPTION_NO_MDMX
},
10124 #define OPTION_FIX_VR4122 (OPTION_MD_BASE + 37)
10125 #define OPTION_NO_FIX_VR4122 (OPTION_MD_BASE + 38)
10126 {"mfix-vr4122-bugs", no_argument
, NULL
, OPTION_FIX_VR4122
},
10127 {"no-mfix-vr4122-bugs", no_argument
, NULL
, OPTION_NO_FIX_VR4122
},
10129 #define OPTION_ELF_BASE (OPTION_MD_BASE + 39)
10130 #define OPTION_CALL_SHARED (OPTION_ELF_BASE + 0)
10131 {"KPIC", no_argument
, NULL
, OPTION_CALL_SHARED
},
10132 {"call_shared", no_argument
, NULL
, OPTION_CALL_SHARED
},
10133 #define OPTION_NON_SHARED (OPTION_ELF_BASE + 1)
10134 {"non_shared", no_argument
, NULL
, OPTION_NON_SHARED
},
10135 #define OPTION_XGOT (OPTION_ELF_BASE + 2)
10136 {"xgot", no_argument
, NULL
, OPTION_XGOT
},
10137 #define OPTION_MABI (OPTION_ELF_BASE + 3)
10138 {"mabi", required_argument
, NULL
, OPTION_MABI
},
10139 #define OPTION_32 (OPTION_ELF_BASE + 4)
10140 {"32", no_argument
, NULL
, OPTION_32
},
10141 #define OPTION_N32 (OPTION_ELF_BASE + 5)
10142 {"n32", no_argument
, NULL
, OPTION_N32
},
10143 #define OPTION_64 (OPTION_ELF_BASE + 6)
10144 {"64", no_argument
, NULL
, OPTION_64
},
10145 #define OPTION_MDEBUG (OPTION_ELF_BASE + 7)
10146 {"mdebug", no_argument
, NULL
, OPTION_MDEBUG
},
10147 #define OPTION_NO_MDEBUG (OPTION_ELF_BASE + 8)
10148 {"no-mdebug", no_argument
, NULL
, OPTION_NO_MDEBUG
},
10149 #endif /* OBJ_ELF */
10150 {NULL
, no_argument
, NULL
, 0}
10152 size_t md_longopts_size
= sizeof (md_longopts
);
10154 /* Set STRING_PTR (either &mips_arch_string or &mips_tune_string) to
10155 NEW_VALUE. Warn if another value was already specified. Note:
10156 we have to defer parsing the -march and -mtune arguments in order
10157 to handle 'from-abi' correctly, since the ABI might be specified
10158 in a later argument. */
10161 mips_set_option_string (string_ptr
, new_value
)
10162 const char **string_ptr
, *new_value
;
10164 if (*string_ptr
!= 0 && strcasecmp (*string_ptr
, new_value
) != 0)
10165 as_warn (_("A different %s was already specified, is now %s"),
10166 string_ptr
== &mips_arch_string
? "-march" : "-mtune",
10169 *string_ptr
= new_value
;
10173 md_parse_option (c
, arg
)
10179 case OPTION_CONSTRUCT_FLOATS
:
10180 mips_disable_float_construction
= 0;
10183 case OPTION_NO_CONSTRUCT_FLOATS
:
10184 mips_disable_float_construction
= 1;
10196 target_big_endian
= 1;
10200 target_big_endian
= 0;
10208 if (arg
&& arg
[1] == '0')
10218 mips_debug
= atoi (arg
);
10219 /* When the MIPS assembler sees -g or -g2, it does not do
10220 optimizations which limit full symbolic debugging. We take
10221 that to be equivalent to -O0. */
10222 if (mips_debug
== 2)
10227 file_mips_isa
= ISA_MIPS1
;
10231 file_mips_isa
= ISA_MIPS2
;
10235 file_mips_isa
= ISA_MIPS3
;
10239 file_mips_isa
= ISA_MIPS4
;
10243 file_mips_isa
= ISA_MIPS5
;
10246 case OPTION_MIPS32
:
10247 file_mips_isa
= ISA_MIPS32
;
10250 case OPTION_MIPS64
:
10251 file_mips_isa
= ISA_MIPS64
;
10255 mips_set_option_string (&mips_tune_string
, arg
);
10259 mips_set_option_string (&mips_arch_string
, arg
);
10263 mips_set_option_string (&mips_arch_string
, "4650");
10264 mips_set_option_string (&mips_tune_string
, "4650");
10267 case OPTION_NO_M4650
:
10271 mips_set_option_string (&mips_arch_string
, "4010");
10272 mips_set_option_string (&mips_tune_string
, "4010");
10275 case OPTION_NO_M4010
:
10279 mips_set_option_string (&mips_arch_string
, "4100");
10280 mips_set_option_string (&mips_tune_string
, "4100");
10283 case OPTION_NO_M4100
:
10287 mips_set_option_string (&mips_arch_string
, "3900");
10288 mips_set_option_string (&mips_tune_string
, "3900");
10291 case OPTION_NO_M3900
:
10295 mips_opts
.ase_mdmx
= 1;
10298 case OPTION_NO_MDMX
:
10299 mips_opts
.ase_mdmx
= 0;
10302 case OPTION_MIPS16
:
10303 mips_opts
.mips16
= 1;
10304 mips_no_prev_insn (false);
10307 case OPTION_NO_MIPS16
:
10308 mips_opts
.mips16
= 0;
10309 mips_no_prev_insn (false);
10312 case OPTION_MIPS3D
:
10313 mips_opts
.ase_mips3d
= 1;
10316 case OPTION_NO_MIPS3D
:
10317 mips_opts
.ase_mips3d
= 0;
10320 case OPTION_MEMBEDDED_PIC
:
10321 mips_pic
= EMBEDDED_PIC
;
10322 if (USE_GLOBAL_POINTER_OPT
&& g_switch_seen
)
10324 as_bad (_("-G may not be used with embedded PIC code"));
10327 g_switch_value
= 0x7fffffff;
10330 case OPTION_FIX_VR4122
:
10331 mips_fix_4122_bugs
= 1;
10334 case OPTION_NO_FIX_VR4122
:
10335 mips_fix_4122_bugs
= 0;
10339 /* When generating ELF code, we permit -KPIC and -call_shared to
10340 select SVR4_PIC, and -non_shared to select no PIC. This is
10341 intended to be compatible with Irix 5. */
10342 case OPTION_CALL_SHARED
:
10343 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
10345 as_bad (_("-call_shared is supported only for ELF format"));
10348 mips_pic
= SVR4_PIC
;
10349 if (g_switch_seen
&& g_switch_value
!= 0)
10351 as_bad (_("-G may not be used with SVR4 PIC code"));
10354 g_switch_value
= 0;
10357 case OPTION_NON_SHARED
:
10358 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
10360 as_bad (_("-non_shared is supported only for ELF format"));
10366 /* The -xgot option tells the assembler to use 32 offsets when
10367 accessing the got in SVR4_PIC mode. It is for Irix
10372 #endif /* OBJ_ELF */
10375 if (! USE_GLOBAL_POINTER_OPT
)
10377 as_bad (_("-G is not supported for this configuration"));
10380 else if (mips_pic
== SVR4_PIC
|| mips_pic
== EMBEDDED_PIC
)
10382 as_bad (_("-G may not be used with SVR4 or embedded PIC code"));
10386 g_switch_value
= atoi (arg
);
10391 /* The -32, -n32 and -64 options are shortcuts for -mabi=32, -mabi=n32
10394 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
10396 as_bad (_("-32 is supported for ELF format only"));
10399 mips_abi
= O32_ABI
;
10403 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
10405 as_bad (_("-n32 is supported for ELF format only"));
10408 mips_abi
= N32_ABI
;
10412 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
10414 as_bad (_("-64 is supported for ELF format only"));
10417 mips_abi
= N64_ABI
;
10418 if (! support_64bit_objects())
10419 as_fatal (_("No compiled in support for 64 bit object file format"));
10421 #endif /* OBJ_ELF */
10424 file_mips_gp32
= 1;
10428 file_mips_gp32
= 0;
10432 file_mips_fp32
= 1;
10436 file_mips_fp32
= 0;
10441 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
10443 as_bad (_("-mabi is supported for ELF format only"));
10446 if (strcmp (arg
, "32") == 0)
10447 mips_abi
= O32_ABI
;
10448 else if (strcmp (arg
, "o64") == 0)
10449 mips_abi
= O64_ABI
;
10450 else if (strcmp (arg
, "n32") == 0)
10451 mips_abi
= N32_ABI
;
10452 else if (strcmp (arg
, "64") == 0)
10454 mips_abi
= N64_ABI
;
10455 if (! support_64bit_objects())
10456 as_fatal (_("No compiled in support for 64 bit object file "
10459 else if (strcmp (arg
, "eabi") == 0)
10460 mips_abi
= EABI_ABI
;
10463 as_fatal (_("invalid abi -mabi=%s"), arg
);
10467 #endif /* OBJ_ELF */
10469 case OPTION_M7000_HILO_FIX
:
10470 mips_7000_hilo_fix
= true;
10473 case OPTION_MNO_7000_HILO_FIX
:
10474 mips_7000_hilo_fix
= false;
10478 case OPTION_MDEBUG
:
10479 mips_flag_mdebug
= true;
10482 case OPTION_NO_MDEBUG
:
10483 mips_flag_mdebug
= false;
10485 #endif /* OBJ_ELF */
10494 /* Set up globals to generate code for the ISA or processor
10495 described by INFO. */
10498 mips_set_architecture (info
)
10499 const struct mips_cpu_info
*info
;
10503 mips_arch_info
= info
;
10504 mips_arch
= info
->cpu
;
10505 mips_opts
.isa
= info
->isa
;
10510 /* Likewise for tuning. */
10513 mips_set_tune (info
)
10514 const struct mips_cpu_info
*info
;
10518 mips_tune_info
= info
;
10519 mips_tune
= info
->cpu
;
10525 mips_after_parse_args ()
10527 /* GP relative stuff not working for PE */
10528 if (strncmp (TARGET_OS
, "pe", 2) == 0
10529 && g_switch_value
!= 0)
10532 as_bad (_("-G not supported in this configuration."));
10533 g_switch_value
= 0;
10536 /* The following code determines the architecture and register size.
10537 Similar code was added to GCC 3.3 (see override_options() in
10538 config/mips/mips.c). The GAS and GCC code should be kept in sync
10539 as much as possible. */
10541 if (mips_arch_string
!= 0)
10542 mips_set_architecture (mips_parse_cpu ("-march", mips_arch_string
));
10544 if (mips_tune_string
!= 0)
10545 mips_set_tune (mips_parse_cpu ("-mtune", mips_tune_string
));
10547 if (file_mips_isa
!= ISA_UNKNOWN
)
10549 /* Handle -mipsN. At this point, file_mips_isa contains the
10550 ISA level specified by -mipsN, while mips_opts.isa contains
10551 the -march selection (if any). */
10552 if (mips_arch_info
!= 0)
10554 /* -march takes precedence over -mipsN, since it is more descriptive.
10555 There's no harm in specifying both as long as the ISA levels
10557 if (file_mips_isa
!= mips_opts
.isa
)
10558 as_bad (_("-%s conflicts with the other architecture options, which imply -%s"),
10559 mips_cpu_info_from_isa (file_mips_isa
)->name
,
10560 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
10563 mips_set_architecture (mips_cpu_info_from_isa (file_mips_isa
));
10566 if (mips_arch_info
== 0)
10567 mips_set_architecture (mips_parse_cpu ("default CPU",
10568 MIPS_CPU_STRING_DEFAULT
));
10570 if (ABI_NEEDS_64BIT_REGS (mips_abi
) && !ISA_HAS_64BIT_REGS (mips_opts
.isa
))
10571 as_bad ("-march=%s is not compatible with the selected ABI",
10572 mips_arch_info
->name
);
10574 /* Optimize for mips_arch, unless -mtune selects a different processor. */
10575 if (mips_tune_info
== 0)
10576 mips_set_tune (mips_arch_info
);
10578 if (file_mips_gp32
>= 0)
10580 /* The user specified the size of the integer registers. Make sure
10581 it agrees with the ABI and ISA. */
10582 if (file_mips_gp32
== 0 && !ISA_HAS_64BIT_REGS (mips_opts
.isa
))
10583 as_bad (_("-mgp64 used with a 32-bit processor"));
10584 else if (file_mips_gp32
== 1 && ABI_NEEDS_64BIT_REGS (mips_abi
))
10585 as_bad (_("-mgp32 used with a 64-bit ABI"));
10586 else if (file_mips_gp32
== 0 && ABI_NEEDS_32BIT_REGS (mips_abi
))
10587 as_bad (_("-mgp64 used with a 32-bit ABI"));
10591 /* Infer the integer register size from the ABI and processor.
10592 Restrict ourselves to 32-bit registers if that's all the
10593 processor has, or if the ABI cannot handle 64-bit registers. */
10594 file_mips_gp32
= (ABI_NEEDS_32BIT_REGS (mips_abi
)
10595 || !ISA_HAS_64BIT_REGS (mips_opts
.isa
));
10598 /* ??? GAS treats single-float processors as though they had 64-bit
10599 float registers (although it complains when double-precision
10600 instructions are used). As things stand, saying they have 32-bit
10601 registers would lead to spurious "register must be even" messages.
10602 So here we assume float registers are always the same size as
10603 integer ones, unless the user says otherwise. */
10604 if (file_mips_fp32
< 0)
10605 file_mips_fp32
= file_mips_gp32
;
10607 /* End of GCC-shared inference code. */
10609 /* ??? When do we want this flag to be set? Who uses it? */
10610 if (file_mips_gp32
== 1
10611 && mips_abi
== NO_ABI
10612 && ISA_HAS_64BIT_REGS (mips_opts
.isa
))
10613 mips_32bitmode
= 1;
10615 if (mips_opts
.isa
== ISA_MIPS1
&& mips_trap
)
10616 as_bad (_("trap exception not supported at ISA 1"));
10618 /* If the selected architecture includes support for ASEs, enable
10619 generation of code for them. */
10620 if (mips_opts
.mips16
== -1)
10621 mips_opts
.mips16
= (CPU_HAS_MIPS16 (mips_arch
)) ? 1 : 0;
10622 if (mips_opts
.ase_mips3d
== -1)
10623 mips_opts
.ase_mips3d
= (CPU_HAS_MIPS3D (mips_arch
)) ? 1 : 0;
10624 if (mips_opts
.ase_mdmx
== -1)
10625 mips_opts
.ase_mdmx
= (CPU_HAS_MDMX (mips_arch
)) ? 1 : 0;
10627 file_mips_isa
= mips_opts
.isa
;
10628 file_ase_mips16
= mips_opts
.mips16
;
10629 file_ase_mips3d
= mips_opts
.ase_mips3d
;
10630 file_ase_mdmx
= mips_opts
.ase_mdmx
;
10631 mips_opts
.gp32
= file_mips_gp32
;
10632 mips_opts
.fp32
= file_mips_fp32
;
10634 if (mips_flag_mdebug
< 0)
10636 #ifdef OBJ_MAYBE_ECOFF
10637 if (OUTPUT_FLAVOR
== bfd_target_ecoff_flavour
)
10638 mips_flag_mdebug
= 1;
10640 #endif /* OBJ_MAYBE_ECOFF */
10641 mips_flag_mdebug
= 0;
10646 mips_init_after_args ()
10648 /* initialize opcodes */
10649 bfd_mips_num_opcodes
= bfd_mips_num_builtin_opcodes
;
10650 mips_opcodes
= (struct mips_opcode
*) mips_builtin_opcodes
;
10654 md_pcrel_from (fixP
)
10657 if (OUTPUT_FLAVOR
!= bfd_target_aout_flavour
10658 && fixP
->fx_addsy
!= (symbolS
*) NULL
10659 && ! S_IS_DEFINED (fixP
->fx_addsy
))
10661 /* This makes a branch to an undefined symbol be a branch to the
10662 current location. */
10663 if (mips_pic
== EMBEDDED_PIC
)
10669 /* Return the address of the delay slot. */
10670 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
10673 /* This is called before the symbol table is processed. In order to
10674 work with gcc when using mips-tfile, we must keep all local labels.
10675 However, in other cases, we want to discard them. If we were
10676 called with -g, but we didn't see any debugging information, it may
10677 mean that gcc is smuggling debugging information through to
10678 mips-tfile, in which case we must generate all local labels. */
10681 mips_frob_file_before_adjust ()
10683 #ifndef NO_ECOFF_DEBUGGING
10684 if (ECOFF_DEBUGGING
10686 && ! ecoff_debugging_seen
)
10687 flag_keep_locals
= 1;
10691 /* Sort any unmatched HI16_S relocs so that they immediately precede
10692 the corresponding LO reloc. This is called before md_apply_fix3 and
10693 tc_gen_reloc. Unmatched HI16_S relocs can only be generated by
10694 explicit use of the %hi modifier. */
10699 struct mips_hi_fixup
*l
;
10701 for (l
= mips_hi_fixup_list
; l
!= NULL
; l
= l
->next
)
10703 segment_info_type
*seginfo
;
10706 assert (l
->fixp
->fx_r_type
== BFD_RELOC_HI16_S
);
10708 /* Check quickly whether the next fixup happens to be a matching
10710 if (l
->fixp
->fx_next
!= NULL
10711 && l
->fixp
->fx_next
->fx_r_type
== BFD_RELOC_LO16
10712 && l
->fixp
->fx_addsy
== l
->fixp
->fx_next
->fx_addsy
10713 && l
->fixp
->fx_offset
== l
->fixp
->fx_next
->fx_offset
)
10716 /* Look through the fixups for this segment for a matching %lo.
10717 When we find one, move the %hi just in front of it. We do
10718 this in two passes. In the first pass, we try to find a
10719 unique %lo. In the second pass, we permit multiple %hi
10720 relocs for a single %lo (this is a GNU extension). */
10721 seginfo
= seg_info (l
->seg
);
10722 for (pass
= 0; pass
< 2; pass
++)
10727 for (f
= seginfo
->fix_root
; f
!= NULL
; f
= f
->fx_next
)
10729 /* Check whether this is a %lo fixup which matches l->fixp. */
10730 if (f
->fx_r_type
== BFD_RELOC_LO16
10731 && f
->fx_addsy
== l
->fixp
->fx_addsy
10732 && f
->fx_offset
== l
->fixp
->fx_offset
10735 || prev
->fx_r_type
!= BFD_RELOC_HI16_S
10736 || prev
->fx_addsy
!= f
->fx_addsy
10737 || prev
->fx_offset
!= f
->fx_offset
))
10741 /* Move l->fixp before f. */
10742 for (pf
= &seginfo
->fix_root
;
10744 pf
= &(*pf
)->fx_next
)
10745 assert (*pf
!= NULL
);
10747 *pf
= l
->fixp
->fx_next
;
10749 l
->fixp
->fx_next
= f
;
10751 seginfo
->fix_root
= l
->fixp
;
10753 prev
->fx_next
= l
->fixp
;
10764 #if 0 /* GCC code motion plus incomplete dead code elimination
10765 can leave a %hi without a %lo. */
10767 as_warn_where (l
->fixp
->fx_file
, l
->fixp
->fx_line
,
10768 _("Unmatched %%hi reloc"));
10774 /* When generating embedded PIC code we need to use a special
10775 relocation to represent the difference of two symbols in the .text
10776 section (switch tables use a difference of this sort). See
10777 include/coff/mips.h for details. This macro checks whether this
10778 fixup requires the special reloc. */
10779 #define SWITCH_TABLE(fixp) \
10780 ((fixp)->fx_r_type == BFD_RELOC_32 \
10781 && OUTPUT_FLAVOR != bfd_target_elf_flavour \
10782 && (fixp)->fx_addsy != NULL \
10783 && (fixp)->fx_subsy != NULL \
10784 && S_GET_SEGMENT ((fixp)->fx_addsy) == text_section \
10785 && S_GET_SEGMENT ((fixp)->fx_subsy) == text_section)
10787 /* When generating embedded PIC code we must keep all PC relative
10788 relocations, in case the linker has to relax a call. We also need
10789 to keep relocations for switch table entries.
10791 We may have combined relocations without symbols in the N32/N64 ABI.
10792 We have to prevent gas from dropping them. */
10795 mips_force_relocation (fixp
)
10798 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
10799 || fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
10800 || S_FORCE_RELOC (fixp
->fx_addsy
))
10804 && S_GET_SEGMENT (fixp
->fx_addsy
) == bfd_abs_section_ptr
10805 && (fixp
->fx_r_type
== BFD_RELOC_MIPS_SUB
10806 || fixp
->fx_r_type
== BFD_RELOC_HI16_S
10807 || fixp
->fx_r_type
== BFD_RELOC_LO16
))
10810 return (mips_pic
== EMBEDDED_PIC
10812 || SWITCH_TABLE (fixp
)
10813 || fixp
->fx_r_type
== BFD_RELOC_PCREL_HI16_S
10814 || fixp
->fx_r_type
== BFD_RELOC_PCREL_LO16
));
10819 mips_need_elf_addend_fixup (fixP
)
10822 if (S_GET_OTHER (fixP
->fx_addsy
) == STO_MIPS16
)
10824 if (mips_pic
== EMBEDDED_PIC
10825 && S_IS_WEAK (fixP
->fx_addsy
))
10827 if (mips_pic
!= EMBEDDED_PIC
10828 && (S_IS_WEAK (fixP
->fx_addsy
)
10829 || S_IS_EXTERNAL (fixP
->fx_addsy
))
10830 && !S_IS_COMMON (fixP
->fx_addsy
))
10832 if (symbol_used_in_reloc_p (fixP
->fx_addsy
)
10833 && (((bfd_get_section_flags (stdoutput
,
10834 S_GET_SEGMENT (fixP
->fx_addsy
))
10835 & SEC_LINK_ONCE
) != 0)
10836 || !strncmp (segment_name (S_GET_SEGMENT (fixP
->fx_addsy
)),
10838 sizeof (".gnu.linkonce") - 1)))
10844 /* Apply a fixup to the object file. */
10847 md_apply_fix3 (fixP
, valP
, seg
)
10850 segT seg ATTRIBUTE_UNUSED
;
10855 static int previous_fx_r_type
= 0;
10857 /* FIXME: Maybe just return for all reloc types not listed below?
10858 Eric Christopher says: "This is stupid, please rewrite md_apply_fix3. */
10859 if (fixP
->fx_r_type
== BFD_RELOC_8
)
10862 assert (fixP
->fx_size
== 4
10863 || fixP
->fx_r_type
== BFD_RELOC_16
10864 || fixP
->fx_r_type
== BFD_RELOC_32
10865 || fixP
->fx_r_type
== BFD_RELOC_MIPS_JMP
10866 || fixP
->fx_r_type
== BFD_RELOC_HI16_S
10867 || fixP
->fx_r_type
== BFD_RELOC_LO16
10868 || fixP
->fx_r_type
== BFD_RELOC_GPREL16
10869 || fixP
->fx_r_type
== BFD_RELOC_MIPS_LITERAL
10870 || fixP
->fx_r_type
== BFD_RELOC_GPREL32
10871 || fixP
->fx_r_type
== BFD_RELOC_64
10872 || fixP
->fx_r_type
== BFD_RELOC_CTOR
10873 || fixP
->fx_r_type
== BFD_RELOC_MIPS_SUB
10874 || fixP
->fx_r_type
== BFD_RELOC_MIPS_HIGHEST
10875 || fixP
->fx_r_type
== BFD_RELOC_MIPS_HIGHER
10876 || fixP
->fx_r_type
== BFD_RELOC_MIPS_SCN_DISP
10877 || fixP
->fx_r_type
== BFD_RELOC_MIPS_REL16
10878 || fixP
->fx_r_type
== BFD_RELOC_MIPS_RELGOT
10879 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
10880 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
10881 || fixP
->fx_r_type
== BFD_RELOC_MIPS_JALR
);
10885 /* If we aren't adjusting this fixup to be against the section
10886 symbol, we need to adjust the value. */
10888 if (fixP
->fx_addsy
!= NULL
&& OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
10890 if (mips_need_elf_addend_fixup (fixP
))
10892 reloc_howto_type
*howto
;
10893 valueT symval
= S_GET_VALUE (fixP
->fx_addsy
);
10897 howto
= bfd_reloc_type_lookup (stdoutput
, fixP
->fx_r_type
);
10898 if (value
!= 0 && howto
->partial_inplace
10899 && (! fixP
->fx_pcrel
|| howto
->pcrel_offset
))
10901 /* In this case, the bfd_install_relocation routine will
10902 incorrectly add the symbol value back in. We just want
10903 the addend to appear in the object file.
10905 howto->pcrel_offset is added for R_MIPS_PC16, which is
10906 generated for code like
10917 /* Make sure the addend is still non-zero. If it became zero
10918 after the last operation, set it to a spurious value and
10919 subtract the same value from the object file's contents. */
10924 /* The in-place addends for LO16 relocations are signed;
10925 leave the matching HI16 in-place addends as zero. */
10926 if (fixP
->fx_r_type
!= BFD_RELOC_HI16_S
)
10928 bfd_vma contents
, mask
, field
;
10930 contents
= bfd_get_bits (fixP
->fx_frag
->fr_literal
10933 target_big_endian
);
10935 /* MASK has bits set where the relocation should go.
10936 FIELD is -value, shifted into the appropriate place
10937 for this relocation. */
10938 mask
= 1 << (howto
->bitsize
- 1);
10939 mask
= (((mask
- 1) << 1) | 1) << howto
->bitpos
;
10940 field
= (-value
>> howto
->rightshift
) << howto
->bitpos
;
10942 bfd_put_bits ((field
& mask
) | (contents
& ~mask
),
10943 fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
,
10945 target_big_endian
);
10951 /* This code was generated using trial and error and so is
10952 fragile and not trustworthy. If you change it, you should
10953 rerun the elf-rel, elf-rel2, and empic testcases and ensure
10954 they still pass. */
10955 if (fixP
->fx_pcrel
|| fixP
->fx_subsy
!= NULL
)
10957 value
+= fixP
->fx_frag
->fr_address
+ fixP
->fx_where
;
10959 /* BFD's REL handling, for MIPS, is _very_ weird.
10960 This gives the right results, but it can't possibly
10961 be the way things are supposed to work. */
10962 if ((fixP
->fx_r_type
!= BFD_RELOC_16_PCREL
10963 && fixP
->fx_r_type
!= BFD_RELOC_16_PCREL_S2
)
10964 || S_GET_SEGMENT (fixP
->fx_addsy
) != undefined_section
)
10965 value
+= fixP
->fx_frag
->fr_address
+ fixP
->fx_where
;
10970 fixP
->fx_addnumber
= value
; /* Remember value for tc_gen_reloc. */
10972 /* We are not done if this is a composite relocation to set up gp. */
10973 if (fixP
->fx_addsy
== NULL
&& ! fixP
->fx_pcrel
10974 && !(fixP
->fx_r_type
== BFD_RELOC_MIPS_SUB
10975 || (previous_fx_r_type
== BFD_RELOC_MIPS_SUB
10976 && (fixP
->fx_r_type
== BFD_RELOC_HI16_S
10977 || fixP
->fx_r_type
== BFD_RELOC_LO16
))))
10979 previous_fx_r_type
= fixP
->fx_r_type
;
10981 switch (fixP
->fx_r_type
)
10983 case BFD_RELOC_MIPS_JMP
:
10984 case BFD_RELOC_MIPS_SHIFT5
:
10985 case BFD_RELOC_MIPS_SHIFT6
:
10986 case BFD_RELOC_MIPS_GOT_DISP
:
10987 case BFD_RELOC_MIPS_GOT_PAGE
:
10988 case BFD_RELOC_MIPS_GOT_OFST
:
10989 case BFD_RELOC_MIPS_SUB
:
10990 case BFD_RELOC_MIPS_INSERT_A
:
10991 case BFD_RELOC_MIPS_INSERT_B
:
10992 case BFD_RELOC_MIPS_DELETE
:
10993 case BFD_RELOC_MIPS_HIGHEST
:
10994 case BFD_RELOC_MIPS_HIGHER
:
10995 case BFD_RELOC_MIPS_SCN_DISP
:
10996 case BFD_RELOC_MIPS_REL16
:
10997 case BFD_RELOC_MIPS_RELGOT
:
10998 case BFD_RELOC_MIPS_JALR
:
10999 case BFD_RELOC_HI16
:
11000 case BFD_RELOC_HI16_S
:
11001 case BFD_RELOC_GPREL16
:
11002 case BFD_RELOC_MIPS_LITERAL
:
11003 case BFD_RELOC_MIPS_CALL16
:
11004 case BFD_RELOC_MIPS_GOT16
:
11005 case BFD_RELOC_GPREL32
:
11006 case BFD_RELOC_MIPS_GOT_HI16
:
11007 case BFD_RELOC_MIPS_GOT_LO16
:
11008 case BFD_RELOC_MIPS_CALL_HI16
:
11009 case BFD_RELOC_MIPS_CALL_LO16
:
11010 case BFD_RELOC_MIPS16_GPREL
:
11011 if (fixP
->fx_pcrel
)
11012 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
11013 _("Invalid PC relative reloc"));
11014 /* Nothing needed to do. The value comes from the reloc entry */
11017 case BFD_RELOC_MIPS16_JMP
:
11018 /* We currently always generate a reloc against a symbol, which
11019 means that we don't want an addend even if the symbol is
11021 fixP
->fx_addnumber
= 0;
11024 case BFD_RELOC_PCREL_HI16_S
:
11025 /* The addend for this is tricky if it is internal, so we just
11026 do everything here rather than in bfd_install_relocation. */
11027 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
11032 && (symbol_get_bfdsym (fixP
->fx_addsy
)->flags
& BSF_SECTION_SYM
) == 0)
11034 /* For an external symbol adjust by the address to make it
11035 pcrel_offset. We use the address of the RELLO reloc
11036 which follows this one. */
11037 value
+= (fixP
->fx_next
->fx_frag
->fr_address
11038 + fixP
->fx_next
->fx_where
);
11040 value
= ((value
+ 0x8000) >> 16) & 0xffff;
11041 buf
= (bfd_byte
*) fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
11042 if (target_big_endian
)
11044 md_number_to_chars ((char *) buf
, value
, 2);
11047 case BFD_RELOC_PCREL_LO16
:
11048 /* The addend for this is tricky if it is internal, so we just
11049 do everything here rather than in bfd_install_relocation. */
11050 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
11055 && (symbol_get_bfdsym (fixP
->fx_addsy
)->flags
& BSF_SECTION_SYM
) == 0)
11056 value
+= fixP
->fx_frag
->fr_address
+ fixP
->fx_where
;
11057 buf
= (bfd_byte
*) fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
11058 if (target_big_endian
)
11060 md_number_to_chars ((char *) buf
, value
, 2);
11064 /* This is handled like BFD_RELOC_32, but we output a sign
11065 extended value if we are only 32 bits. */
11067 || (mips_pic
== EMBEDDED_PIC
&& SWITCH_TABLE (fixP
)))
11069 if (8 <= sizeof (valueT
))
11070 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
,
11077 w1
= w2
= fixP
->fx_where
;
11078 if (target_big_endian
)
11082 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ w1
, value
, 4);
11083 if ((value
& 0x80000000) != 0)
11087 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ w2
, hiv
, 4);
11092 case BFD_RELOC_RVA
:
11094 /* If we are deleting this reloc entry, we must fill in the
11095 value now. This can happen if we have a .word which is not
11096 resolved when it appears but is later defined. We also need
11097 to fill in the value if this is an embedded PIC switch table
11100 || (mips_pic
== EMBEDDED_PIC
&& SWITCH_TABLE (fixP
)))
11101 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
,
11106 /* If we are deleting this reloc entry, we must fill in the
11108 assert (fixP
->fx_size
== 2);
11110 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
,
11114 case BFD_RELOC_LO16
:
11115 /* When handling an embedded PIC switch statement, we can wind
11116 up deleting a LO16 reloc. See the 'o' case in mips_ip. */
11119 if (value
+ 0x8000 > 0xffff)
11120 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
11121 _("relocation overflow"));
11122 buf
= (bfd_byte
*) fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
11123 if (target_big_endian
)
11125 md_number_to_chars ((char *) buf
, value
, 2);
11129 case BFD_RELOC_16_PCREL_S2
:
11130 if ((value
& 0x3) != 0)
11131 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
11132 _("Branch to odd address (%lx)"), (long) value
);
11134 /* Fall through. */
11136 case BFD_RELOC_16_PCREL
:
11138 * We need to save the bits in the instruction since fixup_segment()
11139 * might be deleting the relocation entry (i.e., a branch within
11140 * the current segment).
11142 if (!fixP
->fx_done
&& value
!= 0)
11144 /* If 'value' is zero, the remaining reloc code won't actually
11145 do the store, so it must be done here. This is probably
11146 a bug somewhere. */
11148 && (fixP
->fx_r_type
!= BFD_RELOC_16_PCREL_S2
11149 || fixP
->fx_addsy
== NULL
/* ??? */
11150 || ! S_IS_DEFINED (fixP
->fx_addsy
)))
11151 value
-= fixP
->fx_frag
->fr_address
+ fixP
->fx_where
;
11153 value
= (offsetT
) value
>> 2;
11155 /* update old instruction data */
11156 buf
= (bfd_byte
*) (fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
);
11157 if (target_big_endian
)
11158 insn
= (buf
[0] << 24) | (buf
[1] << 16) | (buf
[2] << 8) | buf
[3];
11160 insn
= (buf
[3] << 24) | (buf
[2] << 16) | (buf
[1] << 8) | buf
[0];
11162 if (value
+ 0x8000 <= 0xffff)
11163 insn
|= value
& 0xffff;
11166 /* The branch offset is too large. If this is an
11167 unconditional branch, and we are not generating PIC code,
11168 we can convert it to an absolute jump instruction. */
11169 if (mips_pic
== NO_PIC
11171 && fixP
->fx_frag
->fr_address
>= text_section
->vma
11172 && (fixP
->fx_frag
->fr_address
11173 < text_section
->vma
+ text_section
->_raw_size
)
11174 && ((insn
& 0xffff0000) == 0x10000000 /* beq $0,$0 */
11175 || (insn
& 0xffff0000) == 0x04010000 /* bgez $0 */
11176 || (insn
& 0xffff0000) == 0x04110000)) /* bgezal $0 */
11178 if ((insn
& 0xffff0000) == 0x04110000) /* bgezal $0 */
11179 insn
= 0x0c000000; /* jal */
11181 insn
= 0x08000000; /* j */
11182 fixP
->fx_r_type
= BFD_RELOC_MIPS_JMP
;
11184 fixP
->fx_addsy
= section_symbol (text_section
);
11185 fixP
->fx_addnumber
= (value
<< 2) + md_pcrel_from (fixP
);
11189 /* FIXME. It would be possible in principle to handle
11190 conditional branches which overflow. They could be
11191 transformed into a branch around a jump. This would
11192 require setting up variant frags for each different
11193 branch type. The native MIPS assembler attempts to
11194 handle these cases, but it appears to do it
11196 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
11197 _("Branch out of range"));
11201 md_number_to_chars ((char *) buf
, (valueT
) insn
, 4);
11204 case BFD_RELOC_VTABLE_INHERIT
:
11207 && !S_IS_DEFINED (fixP
->fx_addsy
)
11208 && !S_IS_WEAK (fixP
->fx_addsy
))
11209 S_SET_WEAK (fixP
->fx_addsy
);
11212 case BFD_RELOC_VTABLE_ENTRY
:
11226 const struct mips_opcode
*p
;
11227 int treg
, sreg
, dreg
, shamt
;
11232 for (i
= 0; i
< NUMOPCODES
; ++i
)
11234 p
= &mips_opcodes
[i
];
11235 if (((oc
& p
->mask
) == p
->match
) && (p
->pinfo
!= INSN_MACRO
))
11237 printf ("%08lx %s\t", oc
, p
->name
);
11238 treg
= (oc
>> 16) & 0x1f;
11239 sreg
= (oc
>> 21) & 0x1f;
11240 dreg
= (oc
>> 11) & 0x1f;
11241 shamt
= (oc
>> 6) & 0x1f;
11243 for (args
= p
->args
;; ++args
)
11254 printf ("%c", *args
);
11258 assert (treg
== sreg
);
11259 printf ("$%d,$%d", treg
, sreg
);
11264 printf ("$%d", dreg
);
11269 printf ("$%d", treg
);
11273 printf ("0x%x", treg
);
11278 printf ("$%d", sreg
);
11282 printf ("0x%08lx", oc
& 0x1ffffff);
11289 printf ("%d", imm
);
11294 printf ("$%d", shamt
);
11305 printf (_("%08lx UNDEFINED\n"), oc
);
11316 name
= input_line_pointer
;
11317 c
= get_symbol_end ();
11318 p
= (symbolS
*) symbol_find_or_make (name
);
11319 *input_line_pointer
= c
;
11323 /* Align the current frag to a given power of two. The MIPS assembler
11324 also automatically adjusts any preceding label. */
11327 mips_align (to
, fill
, label
)
11332 mips_emit_delays (false);
11333 frag_align (to
, fill
, 0);
11334 record_alignment (now_seg
, to
);
11337 assert (S_GET_SEGMENT (label
) == now_seg
);
11338 symbol_set_frag (label
, frag_now
);
11339 S_SET_VALUE (label
, (valueT
) frag_now_fix ());
11343 /* Align to a given power of two. .align 0 turns off the automatic
11344 alignment used by the data creating pseudo-ops. */
11348 int x ATTRIBUTE_UNUSED
;
11351 register long temp_fill
;
11352 long max_alignment
= 15;
11356 o Note that the assembler pulls down any immediately preceeding label
11357 to the aligned address.
11358 o It's not documented but auto alignment is reinstated by
11359 a .align pseudo instruction.
11360 o Note also that after auto alignment is turned off the mips assembler
11361 issues an error on attempt to assemble an improperly aligned data item.
11366 temp
= get_absolute_expression ();
11367 if (temp
> max_alignment
)
11368 as_bad (_("Alignment too large: %d. assumed."), temp
= max_alignment
);
11371 as_warn (_("Alignment negative: 0 assumed."));
11374 if (*input_line_pointer
== ',')
11376 ++input_line_pointer
;
11377 temp_fill
= get_absolute_expression ();
11384 mips_align (temp
, (int) temp_fill
,
11385 insn_labels
!= NULL
? insn_labels
->label
: NULL
);
11392 demand_empty_rest_of_line ();
11396 mips_flush_pending_output ()
11398 mips_emit_delays (false);
11399 mips_clear_insn_labels ();
11408 /* When generating embedded PIC code, we only use the .text, .lit8,
11409 .sdata and .sbss sections. We change the .data and .rdata
11410 pseudo-ops to use .sdata. */
11411 if (mips_pic
== EMBEDDED_PIC
11412 && (sec
== 'd' || sec
== 'r'))
11416 /* The ELF backend needs to know that we are changing sections, so
11417 that .previous works correctly. We could do something like check
11418 for an obj_section_change_hook macro, but that might be confusing
11419 as it would not be appropriate to use it in the section changing
11420 functions in read.c, since obj-elf.c intercepts those. FIXME:
11421 This should be cleaner, somehow. */
11422 obj_elf_section_change_hook ();
11425 mips_emit_delays (false);
11435 subseg_set (bss_section
, (subsegT
) get_absolute_expression ());
11436 demand_empty_rest_of_line ();
11440 if (USE_GLOBAL_POINTER_OPT
)
11442 seg
= subseg_new (RDATA_SECTION_NAME
,
11443 (subsegT
) get_absolute_expression ());
11444 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
11446 bfd_set_section_flags (stdoutput
, seg
,
11452 if (strcmp (TARGET_OS
, "elf") != 0)
11453 record_alignment (seg
, 4);
11455 demand_empty_rest_of_line ();
11459 as_bad (_("No read only data section in this object file format"));
11460 demand_empty_rest_of_line ();
11466 if (USE_GLOBAL_POINTER_OPT
)
11468 seg
= subseg_new (".sdata", (subsegT
) get_absolute_expression ());
11469 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
11471 bfd_set_section_flags (stdoutput
, seg
,
11472 SEC_ALLOC
| SEC_LOAD
| SEC_RELOC
11474 if (strcmp (TARGET_OS
, "elf") != 0)
11475 record_alignment (seg
, 4);
11477 demand_empty_rest_of_line ();
11482 as_bad (_("Global pointers not supported; recompile -G 0"));
11483 demand_empty_rest_of_line ();
11492 s_change_section (ignore
)
11493 int ignore ATTRIBUTE_UNUSED
;
11496 char *section_name
;
11501 int section_entry_size
;
11502 int section_alignment
;
11504 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
11507 section_name
= input_line_pointer
;
11508 c
= get_symbol_end ();
11509 next_c
= *(input_line_pointer
+ 1);
11511 /* Do we have .section Name<,"flags">? */
11512 if (c
!= ',' || (c
== ',' && next_c
== '"'))
11514 /* just after name is now '\0'. */
11515 *input_line_pointer
= c
;
11516 input_line_pointer
= section_name
;
11517 obj_elf_section (ignore
);
11520 input_line_pointer
++;
11522 /* Do we have .section Name<,type><,flag><,entry_size><,alignment> */
11524 section_type
= get_absolute_expression ();
11527 if (*input_line_pointer
++ == ',')
11528 section_flag
= get_absolute_expression ();
11531 if (*input_line_pointer
++ == ',')
11532 section_entry_size
= get_absolute_expression ();
11534 section_entry_size
= 0;
11535 if (*input_line_pointer
++ == ',')
11536 section_alignment
= get_absolute_expression ();
11538 section_alignment
= 0;
11540 obj_elf_change_section (section_name
, section_type
, section_flag
,
11541 section_entry_size
, 0, 0, 0);
11542 #endif /* OBJ_ELF */
11546 mips_enable_auto_align ()
11557 label
= insn_labels
!= NULL
? insn_labels
->label
: NULL
;
11558 mips_emit_delays (false);
11559 if (log_size
> 0 && auto_align
)
11560 mips_align (log_size
, 0, label
);
11561 mips_clear_insn_labels ();
11562 cons (1 << log_size
);
11566 s_float_cons (type
)
11571 label
= insn_labels
!= NULL
? insn_labels
->label
: NULL
;
11573 mips_emit_delays (false);
11578 mips_align (3, 0, label
);
11580 mips_align (2, 0, label
);
11583 mips_clear_insn_labels ();
11588 /* Handle .globl. We need to override it because on Irix 5 you are
11591 where foo is an undefined symbol, to mean that foo should be
11592 considered to be the address of a function. */
11596 int x ATTRIBUTE_UNUSED
;
11603 name
= input_line_pointer
;
11604 c
= get_symbol_end ();
11605 symbolP
= symbol_find_or_make (name
);
11606 *input_line_pointer
= c
;
11607 SKIP_WHITESPACE ();
11609 /* On Irix 5, every global symbol that is not explicitly labelled as
11610 being a function is apparently labelled as being an object. */
11613 if (! is_end_of_line
[(unsigned char) *input_line_pointer
])
11618 secname
= input_line_pointer
;
11619 c
= get_symbol_end ();
11620 sec
= bfd_get_section_by_name (stdoutput
, secname
);
11622 as_bad (_("%s: no such section"), secname
);
11623 *input_line_pointer
= c
;
11625 if (sec
!= NULL
&& (sec
->flags
& SEC_CODE
) != 0)
11626 flag
= BSF_FUNCTION
;
11629 symbol_get_bfdsym (symbolP
)->flags
|= flag
;
11631 S_SET_EXTERNAL (symbolP
);
11632 demand_empty_rest_of_line ();
11637 int x ATTRIBUTE_UNUSED
;
11642 opt
= input_line_pointer
;
11643 c
= get_symbol_end ();
11647 /* FIXME: What does this mean? */
11649 else if (strncmp (opt
, "pic", 3) == 0)
11653 i
= atoi (opt
+ 3);
11657 mips_pic
= SVR4_PIC
;
11659 as_bad (_(".option pic%d not supported"), i
);
11661 if (USE_GLOBAL_POINTER_OPT
&& mips_pic
== SVR4_PIC
)
11663 if (g_switch_seen
&& g_switch_value
!= 0)
11664 as_warn (_("-G may not be used with SVR4 PIC code"));
11665 g_switch_value
= 0;
11666 bfd_set_gp_size (stdoutput
, 0);
11670 as_warn (_("Unrecognized option \"%s\""), opt
);
11672 *input_line_pointer
= c
;
11673 demand_empty_rest_of_line ();
11676 /* This structure is used to hold a stack of .set values. */
11678 struct mips_option_stack
11680 struct mips_option_stack
*next
;
11681 struct mips_set_options options
;
11684 static struct mips_option_stack
*mips_opts_stack
;
11686 /* Handle the .set pseudo-op. */
11690 int x ATTRIBUTE_UNUSED
;
11692 char *name
= input_line_pointer
, ch
;
11694 while (!is_end_of_line
[(unsigned char) *input_line_pointer
])
11695 ++input_line_pointer
;
11696 ch
= *input_line_pointer
;
11697 *input_line_pointer
= '\0';
11699 if (strcmp (name
, "reorder") == 0)
11701 if (mips_opts
.noreorder
&& prev_nop_frag
!= NULL
)
11703 /* If we still have pending nops, we can discard them. The
11704 usual nop handling will insert any that are still
11706 prev_nop_frag
->fr_fix
-= (prev_nop_frag_holds
11707 * (mips_opts
.mips16
? 2 : 4));
11708 prev_nop_frag
= NULL
;
11710 mips_opts
.noreorder
= 0;
11712 else if (strcmp (name
, "noreorder") == 0)
11714 mips_emit_delays (true);
11715 mips_opts
.noreorder
= 1;
11716 mips_any_noreorder
= 1;
11718 else if (strcmp (name
, "at") == 0)
11720 mips_opts
.noat
= 0;
11722 else if (strcmp (name
, "noat") == 0)
11724 mips_opts
.noat
= 1;
11726 else if (strcmp (name
, "macro") == 0)
11728 mips_opts
.warn_about_macros
= 0;
11730 else if (strcmp (name
, "nomacro") == 0)
11732 if (mips_opts
.noreorder
== 0)
11733 as_bad (_("`noreorder' must be set before `nomacro'"));
11734 mips_opts
.warn_about_macros
= 1;
11736 else if (strcmp (name
, "move") == 0 || strcmp (name
, "novolatile") == 0)
11738 mips_opts
.nomove
= 0;
11740 else if (strcmp (name
, "nomove") == 0 || strcmp (name
, "volatile") == 0)
11742 mips_opts
.nomove
= 1;
11744 else if (strcmp (name
, "bopt") == 0)
11746 mips_opts
.nobopt
= 0;
11748 else if (strcmp (name
, "nobopt") == 0)
11750 mips_opts
.nobopt
= 1;
11752 else if (strcmp (name
, "mips16") == 0
11753 || strcmp (name
, "MIPS-16") == 0)
11754 mips_opts
.mips16
= 1;
11755 else if (strcmp (name
, "nomips16") == 0
11756 || strcmp (name
, "noMIPS-16") == 0)
11757 mips_opts
.mips16
= 0;
11758 else if (strcmp (name
, "mips3d") == 0)
11759 mips_opts
.ase_mips3d
= 1;
11760 else if (strcmp (name
, "nomips3d") == 0)
11761 mips_opts
.ase_mips3d
= 0;
11762 else if (strcmp (name
, "mdmx") == 0)
11763 mips_opts
.ase_mdmx
= 1;
11764 else if (strcmp (name
, "nomdmx") == 0)
11765 mips_opts
.ase_mdmx
= 0;
11766 else if (strncmp (name
, "mips", 4) == 0)
11770 /* Permit the user to change the ISA on the fly. Needless to
11771 say, misuse can cause serious problems. */
11772 isa
= atoi (name
+ 4);
11776 mips_opts
.gp32
= file_mips_gp32
;
11777 mips_opts
.fp32
= file_mips_fp32
;
11782 mips_opts
.gp32
= 1;
11783 mips_opts
.fp32
= 1;
11789 mips_opts
.gp32
= 0;
11790 mips_opts
.fp32
= 0;
11793 as_bad (_("unknown ISA level %s"), name
+ 4);
11799 case 0: mips_opts
.isa
= file_mips_isa
; break;
11800 case 1: mips_opts
.isa
= ISA_MIPS1
; break;
11801 case 2: mips_opts
.isa
= ISA_MIPS2
; break;
11802 case 3: mips_opts
.isa
= ISA_MIPS3
; break;
11803 case 4: mips_opts
.isa
= ISA_MIPS4
; break;
11804 case 5: mips_opts
.isa
= ISA_MIPS5
; break;
11805 case 32: mips_opts
.isa
= ISA_MIPS32
; break;
11806 case 64: mips_opts
.isa
= ISA_MIPS64
; break;
11807 default: as_bad (_("unknown ISA level %s"), name
+ 4); break;
11810 else if (strcmp (name
, "autoextend") == 0)
11811 mips_opts
.noautoextend
= 0;
11812 else if (strcmp (name
, "noautoextend") == 0)
11813 mips_opts
.noautoextend
= 1;
11814 else if (strcmp (name
, "push") == 0)
11816 struct mips_option_stack
*s
;
11818 s
= (struct mips_option_stack
*) xmalloc (sizeof *s
);
11819 s
->next
= mips_opts_stack
;
11820 s
->options
= mips_opts
;
11821 mips_opts_stack
= s
;
11823 else if (strcmp (name
, "pop") == 0)
11825 struct mips_option_stack
*s
;
11827 s
= mips_opts_stack
;
11829 as_bad (_(".set pop with no .set push"));
11832 /* If we're changing the reorder mode we need to handle
11833 delay slots correctly. */
11834 if (s
->options
.noreorder
&& ! mips_opts
.noreorder
)
11835 mips_emit_delays (true);
11836 else if (! s
->options
.noreorder
&& mips_opts
.noreorder
)
11838 if (prev_nop_frag
!= NULL
)
11840 prev_nop_frag
->fr_fix
-= (prev_nop_frag_holds
11841 * (mips_opts
.mips16
? 2 : 4));
11842 prev_nop_frag
= NULL
;
11846 mips_opts
= s
->options
;
11847 mips_opts_stack
= s
->next
;
11853 as_warn (_("Tried to set unrecognized symbol: %s\n"), name
);
11855 *input_line_pointer
= ch
;
11856 demand_empty_rest_of_line ();
11859 /* Handle the .abicalls pseudo-op. I believe this is equivalent to
11860 .option pic2. It means to generate SVR4 PIC calls. */
11863 s_abicalls (ignore
)
11864 int ignore ATTRIBUTE_UNUSED
;
11866 mips_pic
= SVR4_PIC
;
11867 if (USE_GLOBAL_POINTER_OPT
)
11869 if (g_switch_seen
&& g_switch_value
!= 0)
11870 as_warn (_("-G may not be used with SVR4 PIC code"));
11871 g_switch_value
= 0;
11873 bfd_set_gp_size (stdoutput
, 0);
11874 demand_empty_rest_of_line ();
11877 /* Handle the .cpload pseudo-op. This is used when generating SVR4
11878 PIC code. It sets the $gp register for the function based on the
11879 function address, which is in the register named in the argument.
11880 This uses a relocation against _gp_disp, which is handled specially
11881 by the linker. The result is:
11882 lui $gp,%hi(_gp_disp)
11883 addiu $gp,$gp,%lo(_gp_disp)
11884 addu $gp,$gp,.cpload argument
11885 The .cpload argument is normally $25 == $t9. */
11889 int ignore ATTRIBUTE_UNUSED
;
11894 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
11895 .cpload is ignored. */
11896 if (mips_pic
!= SVR4_PIC
|| HAVE_NEWABI
)
11902 /* .cpload should be in a .set noreorder section. */
11903 if (mips_opts
.noreorder
== 0)
11904 as_warn (_(".cpload not in noreorder section"));
11906 ex
.X_op
= O_symbol
;
11907 ex
.X_add_symbol
= symbol_find_or_make ("_gp_disp");
11908 ex
.X_op_symbol
= NULL
;
11909 ex
.X_add_number
= 0;
11911 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
11912 symbol_get_bfdsym (ex
.X_add_symbol
)->flags
|= BSF_OBJECT
;
11914 macro_build_lui (NULL
, &icnt
, &ex
, mips_gp_register
);
11915 macro_build ((char *) NULL
, &icnt
, &ex
, "addiu", "t,r,j",
11916 mips_gp_register
, mips_gp_register
, (int) BFD_RELOC_LO16
);
11918 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "addu", "d,v,t",
11919 mips_gp_register
, mips_gp_register
, tc_get_register (0));
11921 demand_empty_rest_of_line ();
11924 /* Handle the .cpsetup pseudo-op defined for NewABI PIC code. The syntax is:
11925 .cpsetup $reg1, offset|$reg2, label
11927 If offset is given, this results in:
11928 sd $gp, offset($sp)
11929 lui $gp, %hi(%neg(%gp_rel(label)))
11930 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
11931 daddu $gp, $gp, $reg1
11933 If $reg2 is given, this results in:
11934 daddu $reg2, $gp, $0
11935 lui $gp, %hi(%neg(%gp_rel(label)))
11936 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
11937 daddu $gp, $gp, $reg1
11938 $reg1 is normally $25 == $t9. */
11941 int ignore ATTRIBUTE_UNUSED
;
11943 expressionS ex_off
;
11944 expressionS ex_sym
;
11949 /* If we are not generating SVR4 PIC code, .cpsetup is ignored.
11950 We also need NewABI support. */
11951 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
11957 reg1
= tc_get_register (0);
11958 SKIP_WHITESPACE ();
11959 if (*input_line_pointer
!= ',')
11961 as_bad (_("missing argument separator ',' for .cpsetup"));
11965 ++input_line_pointer
;
11966 SKIP_WHITESPACE ();
11967 if (*input_line_pointer
== '$')
11969 mips_cpreturn_register
= tc_get_register (0);
11970 mips_cpreturn_offset
= -1;
11974 mips_cpreturn_offset
= get_absolute_expression ();
11975 mips_cpreturn_register
= -1;
11977 SKIP_WHITESPACE ();
11978 if (*input_line_pointer
!= ',')
11980 as_bad (_("missing argument separator ',' for .cpsetup"));
11984 ++input_line_pointer
;
11985 SKIP_WHITESPACE ();
11986 expression (&ex_sym
);
11988 if (mips_cpreturn_register
== -1)
11990 ex_off
.X_op
= O_constant
;
11991 ex_off
.X_add_symbol
= NULL
;
11992 ex_off
.X_op_symbol
= NULL
;
11993 ex_off
.X_add_number
= mips_cpreturn_offset
;
11995 macro_build ((char *) NULL
, &icnt
, &ex_off
, "sd", "t,o(b)",
11996 mips_gp_register
, (int) BFD_RELOC_LO16
, SP
);
11999 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "daddu",
12000 "d,v,t", mips_cpreturn_register
, mips_gp_register
, 0);
12002 /* Ensure there's room for the next two instructions, so that `f'
12003 doesn't end up with an address in the wrong frag. */
12006 macro_build ((char *) NULL
, &icnt
, &ex_sym
, "lui", "t,u", mips_gp_register
,
12007 (int) BFD_RELOC_GPREL16
);
12008 fix_new (frag_now
, f
- frag_now
->fr_literal
,
12009 0, NULL
, 0, 0, BFD_RELOC_MIPS_SUB
);
12010 fix_new (frag_now
, f
- frag_now
->fr_literal
,
12011 0, NULL
, 0, 0, BFD_RELOC_HI16_S
);
12014 macro_build ((char *) NULL
, &icnt
, &ex_sym
, "addiu", "t,r,j",
12015 mips_gp_register
, mips_gp_register
, (int) BFD_RELOC_GPREL16
);
12016 fix_new (frag_now
, f
- frag_now
->fr_literal
,
12017 0, NULL
, 0, 0, BFD_RELOC_MIPS_SUB
);
12018 fix_new (frag_now
, f
- frag_now
->fr_literal
,
12019 0, NULL
, 0, 0, BFD_RELOC_LO16
);
12021 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
12022 HAVE_64BIT_ADDRESSES
? "daddu" : "addu", "d,v,t",
12023 mips_gp_register
, mips_gp_register
, reg1
);
12025 demand_empty_rest_of_line ();
12030 int ignore ATTRIBUTE_UNUSED
;
12032 /* If we are not generating SVR4 PIC code, or if this is not NewABI code,
12033 .cplocal is ignored. */
12034 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
12040 mips_gp_register
= tc_get_register (0);
12041 demand_empty_rest_of_line ();
12044 /* Handle the .cprestore pseudo-op. This stores $gp into a given
12045 offset from $sp. The offset is remembered, and after making a PIC
12046 call $gp is restored from that location. */
12049 s_cprestore (ignore
)
12050 int ignore ATTRIBUTE_UNUSED
;
12055 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
12056 .cprestore is ignored. */
12057 if (mips_pic
!= SVR4_PIC
|| HAVE_NEWABI
)
12063 mips_cprestore_offset
= get_absolute_expression ();
12064 mips_cprestore_valid
= 1;
12066 ex
.X_op
= O_constant
;
12067 ex
.X_add_symbol
= NULL
;
12068 ex
.X_op_symbol
= NULL
;
12069 ex
.X_add_number
= mips_cprestore_offset
;
12071 macro_build_ldst_constoffset ((char *) NULL
, &icnt
, &ex
,
12072 HAVE_32BIT_ADDRESSES
? "sw" : "sd",
12073 mips_gp_register
, SP
);
12075 demand_empty_rest_of_line ();
12078 /* Handle the .cpreturn pseudo-op defined for NewABI PIC code. If an offset
12079 was given in the preceeding .gpsetup, it results in:
12080 ld $gp, offset($sp)
12082 If a register $reg2 was given there, it results in:
12083 daddiu $gp, $gp, $reg2
12086 s_cpreturn (ignore
)
12087 int ignore ATTRIBUTE_UNUSED
;
12092 /* If we are not generating SVR4 PIC code, .cpreturn is ignored.
12093 We also need NewABI support. */
12094 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
12100 if (mips_cpreturn_register
== -1)
12102 ex
.X_op
= O_constant
;
12103 ex
.X_add_symbol
= NULL
;
12104 ex
.X_op_symbol
= NULL
;
12105 ex
.X_add_number
= mips_cpreturn_offset
;
12107 macro_build ((char *) NULL
, &icnt
, &ex
, "ld", "t,o(b)",
12108 mips_gp_register
, (int) BFD_RELOC_LO16
, SP
);
12111 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "daddu",
12112 "d,v,t", mips_gp_register
, mips_cpreturn_register
, 0);
12114 demand_empty_rest_of_line ();
12117 /* Handle the .gpvalue pseudo-op. This is used when generating NewABI PIC
12118 code. It sets the offset to use in gp_rel relocations. */
12122 int ignore ATTRIBUTE_UNUSED
;
12124 /* If we are not generating SVR4 PIC code, .gpvalue is ignored.
12125 We also need NewABI support. */
12126 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
12132 mips_gprel_offset
= get_absolute_expression ();
12134 demand_empty_rest_of_line ();
12137 /* Handle the .gpword pseudo-op. This is used when generating PIC
12138 code. It generates a 32 bit GP relative reloc. */
12142 int ignore ATTRIBUTE_UNUSED
;
12148 /* When not generating PIC code, this is treated as .word. */
12149 if (mips_pic
!= SVR4_PIC
)
12155 label
= insn_labels
!= NULL
? insn_labels
->label
: NULL
;
12156 mips_emit_delays (true);
12158 mips_align (2, 0, label
);
12159 mips_clear_insn_labels ();
12163 if (ex
.X_op
!= O_symbol
|| ex
.X_add_number
!= 0)
12165 as_bad (_("Unsupported use of .gpword"));
12166 ignore_rest_of_line ();
12170 md_number_to_chars (p
, (valueT
) 0, 4);
12171 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 4, &ex
, false,
12172 BFD_RELOC_GPREL32
);
12174 demand_empty_rest_of_line ();
12177 /* Handle the .cpadd pseudo-op. This is used when dealing with switch
12178 tables in SVR4 PIC code. */
12182 int ignore ATTRIBUTE_UNUSED
;
12187 /* This is ignored when not generating SVR4 PIC code or if this is NewABI
12189 if (mips_pic
!= SVR4_PIC
|| HAVE_NEWABI
)
12195 /* Add $gp to the register named as an argument. */
12196 reg
= tc_get_register (0);
12197 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
12198 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
12199 "d,v,t", reg
, reg
, mips_gp_register
);
12201 demand_empty_rest_of_line ();
12204 /* Handle the .insn pseudo-op. This marks instruction labels in
12205 mips16 mode. This permits the linker to handle them specially,
12206 such as generating jalx instructions when needed. We also make
12207 them odd for the duration of the assembly, in order to generate the
12208 right sort of code. We will make them even in the adjust_symtab
12209 routine, while leaving them marked. This is convenient for the
12210 debugger and the disassembler. The linker knows to make them odd
12215 int ignore ATTRIBUTE_UNUSED
;
12217 mips16_mark_labels ();
12219 demand_empty_rest_of_line ();
12222 /* Handle a .stabn directive. We need these in order to mark a label
12223 as being a mips16 text label correctly. Sometimes the compiler
12224 will emit a label, followed by a .stabn, and then switch sections.
12225 If the label and .stabn are in mips16 mode, then the label is
12226 really a mips16 text label. */
12233 mips16_mark_labels ();
12238 /* Handle the .weakext pseudo-op as defined in Kane and Heinrich.
12242 s_mips_weakext (ignore
)
12243 int ignore ATTRIBUTE_UNUSED
;
12250 name
= input_line_pointer
;
12251 c
= get_symbol_end ();
12252 symbolP
= symbol_find_or_make (name
);
12253 S_SET_WEAK (symbolP
);
12254 *input_line_pointer
= c
;
12256 SKIP_WHITESPACE ();
12258 if (! is_end_of_line
[(unsigned char) *input_line_pointer
])
12260 if (S_IS_DEFINED (symbolP
))
12262 as_bad ("ignoring attempt to redefine symbol %s",
12263 S_GET_NAME (symbolP
));
12264 ignore_rest_of_line ();
12268 if (*input_line_pointer
== ',')
12270 ++input_line_pointer
;
12271 SKIP_WHITESPACE ();
12275 if (exp
.X_op
!= O_symbol
)
12277 as_bad ("bad .weakext directive");
12278 ignore_rest_of_line ();
12281 symbol_set_value_expression (symbolP
, &exp
);
12284 demand_empty_rest_of_line ();
12287 /* Parse a register string into a number. Called from the ECOFF code
12288 to parse .frame. The argument is non-zero if this is the frame
12289 register, so that we can record it in mips_frame_reg. */
12292 tc_get_register (frame
)
12297 SKIP_WHITESPACE ();
12298 if (*input_line_pointer
++ != '$')
12300 as_warn (_("expected `$'"));
12303 else if (ISDIGIT (*input_line_pointer
))
12305 reg
= get_absolute_expression ();
12306 if (reg
< 0 || reg
>= 32)
12308 as_warn (_("Bad register number"));
12314 if (strncmp (input_line_pointer
, "ra", 2) == 0)
12317 input_line_pointer
+= 2;
12319 else if (strncmp (input_line_pointer
, "fp", 2) == 0)
12322 input_line_pointer
+= 2;
12324 else if (strncmp (input_line_pointer
, "sp", 2) == 0)
12327 input_line_pointer
+= 2;
12329 else if (strncmp (input_line_pointer
, "gp", 2) == 0)
12332 input_line_pointer
+= 2;
12334 else if (strncmp (input_line_pointer
, "at", 2) == 0)
12337 input_line_pointer
+= 2;
12339 else if (strncmp (input_line_pointer
, "kt0", 3) == 0)
12342 input_line_pointer
+= 3;
12344 else if (strncmp (input_line_pointer
, "kt1", 3) == 0)
12347 input_line_pointer
+= 3;
12349 else if (strncmp (input_line_pointer
, "zero", 4) == 0)
12352 input_line_pointer
+= 4;
12356 as_warn (_("Unrecognized register name"));
12358 while (ISALNUM(*input_line_pointer
))
12359 input_line_pointer
++;
12364 mips_frame_reg
= reg
!= 0 ? reg
: SP
;
12365 mips_frame_reg_valid
= 1;
12366 mips_cprestore_valid
= 0;
12372 md_section_align (seg
, addr
)
12376 int align
= bfd_get_section_alignment (stdoutput
, seg
);
12379 /* We don't need to align ELF sections to the full alignment.
12380 However, Irix 5 may prefer that we align them at least to a 16
12381 byte boundary. We don't bother to align the sections if we are
12382 targeted for an embedded system. */
12383 if (strcmp (TARGET_OS
, "elf") == 0)
12389 return ((addr
+ (1 << align
) - 1) & (-1 << align
));
12392 /* Utility routine, called from above as well. If called while the
12393 input file is still being read, it's only an approximation. (For
12394 example, a symbol may later become defined which appeared to be
12395 undefined earlier.) */
12398 nopic_need_relax (sym
, before_relaxing
)
12400 int before_relaxing
;
12405 if (USE_GLOBAL_POINTER_OPT
&& g_switch_value
> 0)
12407 const char *symname
;
12410 /* Find out whether this symbol can be referenced off the $gp
12411 register. It can be if it is smaller than the -G size or if
12412 it is in the .sdata or .sbss section. Certain symbols can
12413 not be referenced off the $gp, although it appears as though
12415 symname
= S_GET_NAME (sym
);
12416 if (symname
!= (const char *) NULL
12417 && (strcmp (symname
, "eprol") == 0
12418 || strcmp (symname
, "etext") == 0
12419 || strcmp (symname
, "_gp") == 0
12420 || strcmp (symname
, "edata") == 0
12421 || strcmp (symname
, "_fbss") == 0
12422 || strcmp (symname
, "_fdata") == 0
12423 || strcmp (symname
, "_ftext") == 0
12424 || strcmp (symname
, "end") == 0
12425 || strcmp (symname
, "_gp_disp") == 0))
12427 else if ((! S_IS_DEFINED (sym
) || S_IS_COMMON (sym
))
12429 #ifndef NO_ECOFF_DEBUGGING
12430 || (symbol_get_obj (sym
)->ecoff_extern_size
!= 0
12431 && (symbol_get_obj (sym
)->ecoff_extern_size
12432 <= g_switch_value
))
12434 /* We must defer this decision until after the whole
12435 file has been read, since there might be a .extern
12436 after the first use of this symbol. */
12437 || (before_relaxing
12438 #ifndef NO_ECOFF_DEBUGGING
12439 && symbol_get_obj (sym
)->ecoff_extern_size
== 0
12441 && S_GET_VALUE (sym
) == 0)
12442 || (S_GET_VALUE (sym
) != 0
12443 && S_GET_VALUE (sym
) <= g_switch_value
)))
12447 const char *segname
;
12449 segname
= segment_name (S_GET_SEGMENT (sym
));
12450 assert (strcmp (segname
, ".lit8") != 0
12451 && strcmp (segname
, ".lit4") != 0);
12452 change
= (strcmp (segname
, ".sdata") != 0
12453 && strcmp (segname
, ".sbss") != 0
12454 && strncmp (segname
, ".sdata.", 7) != 0
12455 && strncmp (segname
, ".gnu.linkonce.s.", 16) != 0);
12460 /* We are not optimizing for the $gp register. */
12464 /* Given a mips16 variant frag FRAGP, return non-zero if it needs an
12465 extended opcode. SEC is the section the frag is in. */
12468 mips16_extended_frag (fragp
, sec
, stretch
)
12474 register const struct mips16_immed_operand
*op
;
12476 int mintiny
, maxtiny
;
12480 if (RELAX_MIPS16_USER_SMALL (fragp
->fr_subtype
))
12482 if (RELAX_MIPS16_USER_EXT (fragp
->fr_subtype
))
12485 type
= RELAX_MIPS16_TYPE (fragp
->fr_subtype
);
12486 op
= mips16_immed_operands
;
12487 while (op
->type
!= type
)
12490 assert (op
< mips16_immed_operands
+ MIPS16_NUM_IMMED
);
12495 if (type
== '<' || type
== '>' || type
== '[' || type
== ']')
12498 maxtiny
= 1 << op
->nbits
;
12503 maxtiny
= (1 << op
->nbits
) - 1;
12508 mintiny
= - (1 << (op
->nbits
- 1));
12509 maxtiny
= (1 << (op
->nbits
- 1)) - 1;
12512 sym_frag
= symbol_get_frag (fragp
->fr_symbol
);
12513 val
= S_GET_VALUE (fragp
->fr_symbol
);
12514 symsec
= S_GET_SEGMENT (fragp
->fr_symbol
);
12520 /* We won't have the section when we are called from
12521 mips_relax_frag. However, we will always have been called
12522 from md_estimate_size_before_relax first. If this is a
12523 branch to a different section, we mark it as such. If SEC is
12524 NULL, and the frag is not marked, then it must be a branch to
12525 the same section. */
12528 if (RELAX_MIPS16_LONG_BRANCH (fragp
->fr_subtype
))
12533 /* Must have been called from md_estimate_size_before_relax. */
12536 fragp
->fr_subtype
=
12537 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
12539 /* FIXME: We should support this, and let the linker
12540 catch branches and loads that are out of range. */
12541 as_bad_where (fragp
->fr_file
, fragp
->fr_line
,
12542 _("unsupported PC relative reference to different section"));
12546 if (fragp
!= sym_frag
&& sym_frag
->fr_address
== 0)
12547 /* Assume non-extended on the first relaxation pass.
12548 The address we have calculated will be bogus if this is
12549 a forward branch to another frag, as the forward frag
12550 will have fr_address == 0. */
12554 /* In this case, we know for sure that the symbol fragment is in
12555 the same section. If the relax_marker of the symbol fragment
12556 differs from the relax_marker of this fragment, we have not
12557 yet adjusted the symbol fragment fr_address. We want to add
12558 in STRETCH in order to get a better estimate of the address.
12559 This particularly matters because of the shift bits. */
12561 && sym_frag
->relax_marker
!= fragp
->relax_marker
)
12565 /* Adjust stretch for any alignment frag. Note that if have
12566 been expanding the earlier code, the symbol may be
12567 defined in what appears to be an earlier frag. FIXME:
12568 This doesn't handle the fr_subtype field, which specifies
12569 a maximum number of bytes to skip when doing an
12571 for (f
= fragp
; f
!= NULL
&& f
!= sym_frag
; f
= f
->fr_next
)
12573 if (f
->fr_type
== rs_align
|| f
->fr_type
== rs_align_code
)
12576 stretch
= - ((- stretch
)
12577 & ~ ((1 << (int) f
->fr_offset
) - 1));
12579 stretch
&= ~ ((1 << (int) f
->fr_offset
) - 1);
12588 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
12590 /* The base address rules are complicated. The base address of
12591 a branch is the following instruction. The base address of a
12592 PC relative load or add is the instruction itself, but if it
12593 is in a delay slot (in which case it can not be extended) use
12594 the address of the instruction whose delay slot it is in. */
12595 if (type
== 'p' || type
== 'q')
12599 /* If we are currently assuming that this frag should be
12600 extended, then, the current address is two bytes
12602 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
12605 /* Ignore the low bit in the target, since it will be set
12606 for a text label. */
12607 if ((val
& 1) != 0)
12610 else if (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
))
12612 else if (RELAX_MIPS16_DSLOT (fragp
->fr_subtype
))
12615 val
-= addr
& ~ ((1 << op
->shift
) - 1);
12617 /* Branch offsets have an implicit 0 in the lowest bit. */
12618 if (type
== 'p' || type
== 'q')
12621 /* If any of the shifted bits are set, we must use an extended
12622 opcode. If the address depends on the size of this
12623 instruction, this can lead to a loop, so we arrange to always
12624 use an extended opcode. We only check this when we are in
12625 the main relaxation loop, when SEC is NULL. */
12626 if ((val
& ((1 << op
->shift
) - 1)) != 0 && sec
== NULL
)
12628 fragp
->fr_subtype
=
12629 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
12633 /* If we are about to mark a frag as extended because the value
12634 is precisely maxtiny + 1, then there is a chance of an
12635 infinite loop as in the following code:
12640 In this case when the la is extended, foo is 0x3fc bytes
12641 away, so the la can be shrunk, but then foo is 0x400 away, so
12642 the la must be extended. To avoid this loop, we mark the
12643 frag as extended if it was small, and is about to become
12644 extended with a value of maxtiny + 1. */
12645 if (val
== ((maxtiny
+ 1) << op
->shift
)
12646 && ! RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
)
12649 fragp
->fr_subtype
=
12650 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
12654 else if (symsec
!= absolute_section
&& sec
!= NULL
)
12655 as_bad_where (fragp
->fr_file
, fragp
->fr_line
, _("unsupported relocation"));
12657 if ((val
& ((1 << op
->shift
) - 1)) != 0
12658 || val
< (mintiny
<< op
->shift
)
12659 || val
> (maxtiny
<< op
->shift
))
12665 /* Estimate the size of a frag before relaxing. Unless this is the
12666 mips16, we are not really relaxing here, and the final size is
12667 encoded in the subtype information. For the mips16, we have to
12668 decide whether we are using an extended opcode or not. */
12671 md_estimate_size_before_relax (fragp
, segtype
)
12676 boolean linkonce
= false;
12678 if (RELAX_MIPS16_P (fragp
->fr_subtype
))
12679 /* We don't want to modify the EXTENDED bit here; it might get us
12680 into infinite loops. We change it only in mips_relax_frag(). */
12681 return (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
) ? 4 : 2);
12683 if (mips_pic
== NO_PIC
)
12685 change
= nopic_need_relax (fragp
->fr_symbol
, 0);
12687 else if (mips_pic
== SVR4_PIC
)
12692 sym
= fragp
->fr_symbol
;
12694 /* Handle the case of a symbol equated to another symbol. */
12695 while (symbol_equated_reloc_p (sym
))
12699 /* It's possible to get a loop here in a badly written
12701 n
= symbol_get_value_expression (sym
)->X_add_symbol
;
12707 symsec
= S_GET_SEGMENT (sym
);
12709 /* duplicate the test for LINK_ONCE sections as in adjust_reloc_syms */
12710 if (symsec
!= segtype
&& ! S_IS_LOCAL (sym
))
12712 if ((bfd_get_section_flags (stdoutput
, symsec
) & SEC_LINK_ONCE
)
12716 /* The GNU toolchain uses an extension for ELF: a section
12717 beginning with the magic string .gnu.linkonce is a linkonce
12719 if (strncmp (segment_name (symsec
), ".gnu.linkonce",
12720 sizeof ".gnu.linkonce" - 1) == 0)
12724 /* This must duplicate the test in adjust_reloc_syms. */
12725 change
= (symsec
!= &bfd_und_section
12726 && symsec
!= &bfd_abs_section
12727 && ! bfd_is_com_section (symsec
)
12730 /* A global or weak symbol is treated as external. */
12731 && (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
12732 || (! S_IS_WEAK (sym
)
12733 && (! S_IS_EXTERNAL (sym
)
12734 || mips_pic
== EMBEDDED_PIC
)))
12743 /* Record the offset to the first reloc in the fr_opcode field.
12744 This lets md_convert_frag and tc_gen_reloc know that the code
12745 must be expanded. */
12746 fragp
->fr_opcode
= (fragp
->fr_literal
12748 - RELAX_OLD (fragp
->fr_subtype
)
12749 + RELAX_RELOC1 (fragp
->fr_subtype
));
12750 /* FIXME: This really needs as_warn_where. */
12751 if (RELAX_WARN (fragp
->fr_subtype
))
12752 as_warn (_("AT used after \".set noat\" or macro used after "
12753 "\".set nomacro\""));
12755 return RELAX_NEW (fragp
->fr_subtype
) - RELAX_OLD (fragp
->fr_subtype
);
12761 /* This is called to see whether a reloc against a defined symbol
12762 should be converted into a reloc against a section. Don't adjust
12763 MIPS16 jump relocations, so we don't have to worry about the format
12764 of the offset in the .o file. Don't adjust relocations against
12765 mips16 symbols, so that the linker can find them if it needs to set
12769 mips_fix_adjustable (fixp
)
12772 if (fixp
->fx_r_type
== BFD_RELOC_MIPS16_JMP
)
12775 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
12776 || fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
12779 if (fixp
->fx_addsy
== NULL
)
12783 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
12784 && S_GET_OTHER (fixp
->fx_addsy
) == STO_MIPS16
12785 && fixp
->fx_subsy
== NULL
)
12792 /* Translate internal representation of relocation info to BFD target
12796 tc_gen_reloc (section
, fixp
)
12797 asection
*section ATTRIBUTE_UNUSED
;
12800 static arelent
*retval
[4];
12802 bfd_reloc_code_real_type code
;
12804 reloc
= retval
[0] = (arelent
*) xmalloc (sizeof (arelent
));
12807 reloc
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
12808 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
12809 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
12811 if (mips_pic
== EMBEDDED_PIC
12812 && SWITCH_TABLE (fixp
))
12814 /* For a switch table entry we use a special reloc. The addend
12815 is actually the difference between the reloc address and the
12817 reloc
->addend
= reloc
->address
- S_GET_VALUE (fixp
->fx_subsy
);
12818 if (OUTPUT_FLAVOR
!= bfd_target_ecoff_flavour
)
12819 as_fatal (_("Double check fx_r_type in tc-mips.c:tc_gen_reloc"));
12820 fixp
->fx_r_type
= BFD_RELOC_GPREL32
;
12822 else if (fixp
->fx_r_type
== BFD_RELOC_PCREL_LO16
)
12824 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
12825 reloc
->addend
= fixp
->fx_addnumber
;
12828 /* We use a special addend for an internal RELLO reloc. */
12829 if (symbol_section_p (fixp
->fx_addsy
))
12830 reloc
->addend
= reloc
->address
- S_GET_VALUE (fixp
->fx_subsy
);
12832 reloc
->addend
= fixp
->fx_addnumber
+ reloc
->address
;
12835 else if (fixp
->fx_r_type
== BFD_RELOC_PCREL_HI16_S
)
12837 assert (fixp
->fx_next
!= NULL
12838 && fixp
->fx_next
->fx_r_type
== BFD_RELOC_PCREL_LO16
);
12840 /* The reloc is relative to the RELLO; adjust the addend
12842 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
12843 reloc
->addend
= fixp
->fx_next
->fx_addnumber
;
12846 /* We use a special addend for an internal RELHI reloc. */
12847 if (symbol_section_p (fixp
->fx_addsy
))
12848 reloc
->addend
= (fixp
->fx_next
->fx_frag
->fr_address
12849 + fixp
->fx_next
->fx_where
12850 - S_GET_VALUE (fixp
->fx_subsy
));
12852 reloc
->addend
= (fixp
->fx_addnumber
12853 + fixp
->fx_next
->fx_frag
->fr_address
12854 + fixp
->fx_next
->fx_where
);
12857 else if (fixp
->fx_pcrel
== 0 || OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
12858 reloc
->addend
= fixp
->fx_addnumber
;
12861 if (OUTPUT_FLAVOR
!= bfd_target_aout_flavour
)
12862 /* A gruesome hack which is a result of the gruesome gas reloc
12864 reloc
->addend
= reloc
->address
;
12866 reloc
->addend
= -reloc
->address
;
12869 /* If this is a variant frag, we may need to adjust the existing
12870 reloc and generate a new one. */
12871 if (fixp
->fx_frag
->fr_opcode
!= NULL
12872 && ((fixp
->fx_r_type
== BFD_RELOC_GPREL16
12874 || fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT16
12875 || fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL16
12876 || fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT_HI16
12877 || fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT_LO16
12878 || fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL_HI16
12879 || fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL_LO16
)
12884 assert (! RELAX_MIPS16_P (fixp
->fx_frag
->fr_subtype
));
12886 /* If this is not the last reloc in this frag, then we have two
12887 GPREL relocs, or a GOT_HI16/GOT_LO16 pair, or a
12888 CALL_HI16/CALL_LO16, both of which are being replaced. Let
12889 the second one handle all of them. */
12890 if (fixp
->fx_next
!= NULL
12891 && fixp
->fx_frag
== fixp
->fx_next
->fx_frag
)
12893 assert ((fixp
->fx_r_type
== BFD_RELOC_GPREL16
12894 && fixp
->fx_next
->fx_r_type
== BFD_RELOC_GPREL16
)
12895 || (fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT_HI16
12896 && (fixp
->fx_next
->fx_r_type
12897 == BFD_RELOC_MIPS_GOT_LO16
))
12898 || (fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL_HI16
12899 && (fixp
->fx_next
->fx_r_type
12900 == BFD_RELOC_MIPS_CALL_LO16
)));
12905 fixp
->fx_where
= fixp
->fx_frag
->fr_opcode
- fixp
->fx_frag
->fr_literal
;
12906 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
12907 reloc2
= retval
[1] = (arelent
*) xmalloc (sizeof (arelent
));
12909 reloc2
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
12910 *reloc2
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
12911 reloc2
->address
= (reloc
->address
12912 + (RELAX_RELOC2 (fixp
->fx_frag
->fr_subtype
)
12913 - RELAX_RELOC1 (fixp
->fx_frag
->fr_subtype
)));
12914 reloc2
->addend
= fixp
->fx_addnumber
;
12915 reloc2
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_LO16
);
12916 assert (reloc2
->howto
!= NULL
);
12918 if (RELAX_RELOC3 (fixp
->fx_frag
->fr_subtype
))
12922 reloc3
= retval
[2] = (arelent
*) xmalloc (sizeof (arelent
));
12925 reloc3
->address
+= 4;
12928 if (mips_pic
== NO_PIC
)
12930 assert (fixp
->fx_r_type
== BFD_RELOC_GPREL16
);
12931 fixp
->fx_r_type
= BFD_RELOC_HI16_S
;
12933 else if (mips_pic
== SVR4_PIC
)
12935 switch (fixp
->fx_r_type
)
12939 case BFD_RELOC_MIPS_GOT16
:
12941 case BFD_RELOC_MIPS_GOT_LO16
:
12942 case BFD_RELOC_MIPS_CALL_LO16
:
12943 fixp
->fx_r_type
= BFD_RELOC_MIPS_GOT16
;
12945 case BFD_RELOC_MIPS_CALL16
:
12948 /* BFD_RELOC_MIPS_GOT16;*/
12949 fixp
->fx_r_type
= BFD_RELOC_MIPS_GOT_PAGE
;
12950 reloc2
->howto
= bfd_reloc_type_lookup
12951 (stdoutput
, BFD_RELOC_MIPS_GOT_OFST
);
12954 fixp
->fx_r_type
= BFD_RELOC_MIPS_GOT16
;
12961 /* newabi uses R_MIPS_GOT_DISP for local symbols */
12962 if (HAVE_NEWABI
&& BFD_RELOC_MIPS_GOT_LO16
)
12964 fixp
->fx_r_type
= BFD_RELOC_MIPS_GOT_DISP
;
12969 /* Since the old MIPS ELF ABI uses Rel instead of Rela, encode the vtable
12970 entry to be used in the relocation's section offset. */
12971 if (! HAVE_NEWABI
&& fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
12973 reloc
->address
= reloc
->addend
;
12977 /* Since DIFF_EXPR_OK is defined in tc-mips.h, it is possible that
12978 fixup_segment converted a non-PC relative reloc into a PC
12979 relative reloc. In such a case, we need to convert the reloc
12981 code
= fixp
->fx_r_type
;
12982 if (fixp
->fx_pcrel
)
12987 code
= BFD_RELOC_8_PCREL
;
12990 code
= BFD_RELOC_16_PCREL
;
12993 code
= BFD_RELOC_32_PCREL
;
12996 code
= BFD_RELOC_64_PCREL
;
12998 case BFD_RELOC_8_PCREL
:
12999 case BFD_RELOC_16_PCREL
:
13000 case BFD_RELOC_32_PCREL
:
13001 case BFD_RELOC_64_PCREL
:
13002 case BFD_RELOC_16_PCREL_S2
:
13003 case BFD_RELOC_PCREL_HI16_S
:
13004 case BFD_RELOC_PCREL_LO16
:
13007 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
13008 _("Cannot make %s relocation PC relative"),
13009 bfd_get_reloc_code_name (code
));
13014 /* md_apply_fix3 has a double-subtraction hack to get
13015 bfd_install_relocation to behave nicely. GPREL relocations are
13016 handled correctly without this hack, so undo it here. We can't
13017 stop md_apply_fix3 from subtracting twice in the first place since
13018 the fake addend is required for variant frags above. */
13019 if (fixp
->fx_addsy
!= NULL
&& OUTPUT_FLAVOR
== bfd_target_elf_flavour
13020 && (code
== BFD_RELOC_GPREL16
|| code
== BFD_RELOC_MIPS16_GPREL
)
13021 && reloc
->addend
!= 0
13022 && mips_need_elf_addend_fixup (fixp
))
13023 reloc
->addend
+= S_GET_VALUE (fixp
->fx_addsy
);
13026 /* To support a PC relative reloc when generating embedded PIC code
13027 for ECOFF, we use a Cygnus extension. We check for that here to
13028 make sure that we don't let such a reloc escape normally. */
13029 if ((OUTPUT_FLAVOR
== bfd_target_ecoff_flavour
13030 || OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
13031 && code
== BFD_RELOC_16_PCREL_S2
13032 && mips_pic
!= EMBEDDED_PIC
)
13033 reloc
->howto
= NULL
;
13035 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
13037 if (reloc
->howto
== NULL
)
13039 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
13040 _("Can not represent %s relocation in this object file format"),
13041 bfd_get_reloc_code_name (code
));
13048 /* Relax a machine dependent frag. This returns the amount by which
13049 the current size of the frag should change. */
13052 mips_relax_frag (fragp
, stretch
)
13056 if (! RELAX_MIPS16_P (fragp
->fr_subtype
))
13059 if (mips16_extended_frag (fragp
, NULL
, stretch
))
13061 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
13063 fragp
->fr_subtype
= RELAX_MIPS16_MARK_EXTENDED (fragp
->fr_subtype
);
13068 if (! RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
13070 fragp
->fr_subtype
= RELAX_MIPS16_CLEAR_EXTENDED (fragp
->fr_subtype
);
13077 /* Convert a machine dependent frag. */
13080 md_convert_frag (abfd
, asec
, fragp
)
13081 bfd
*abfd ATTRIBUTE_UNUSED
;
13088 if (RELAX_MIPS16_P (fragp
->fr_subtype
))
13091 register const struct mips16_immed_operand
*op
;
13092 boolean small
, ext
;
13095 unsigned long insn
;
13096 boolean use_extend
;
13097 unsigned short extend
;
13099 type
= RELAX_MIPS16_TYPE (fragp
->fr_subtype
);
13100 op
= mips16_immed_operands
;
13101 while (op
->type
!= type
)
13104 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
13115 resolve_symbol_value (fragp
->fr_symbol
);
13116 val
= S_GET_VALUE (fragp
->fr_symbol
);
13121 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
13123 /* The rules for the base address of a PC relative reloc are
13124 complicated; see mips16_extended_frag. */
13125 if (type
== 'p' || type
== 'q')
13130 /* Ignore the low bit in the target, since it will be
13131 set for a text label. */
13132 if ((val
& 1) != 0)
13135 else if (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
))
13137 else if (RELAX_MIPS16_DSLOT (fragp
->fr_subtype
))
13140 addr
&= ~ (addressT
) ((1 << op
->shift
) - 1);
13143 /* Make sure the section winds up with the alignment we have
13146 record_alignment (asec
, op
->shift
);
13150 && (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
)
13151 || RELAX_MIPS16_DSLOT (fragp
->fr_subtype
)))
13152 as_warn_where (fragp
->fr_file
, fragp
->fr_line
,
13153 _("extended instruction in delay slot"));
13155 buf
= (bfd_byte
*) (fragp
->fr_literal
+ fragp
->fr_fix
);
13157 if (target_big_endian
)
13158 insn
= bfd_getb16 (buf
);
13160 insn
= bfd_getl16 (buf
);
13162 mips16_immed (fragp
->fr_file
, fragp
->fr_line
, type
, val
,
13163 RELAX_MIPS16_USER_EXT (fragp
->fr_subtype
),
13164 small
, ext
, &insn
, &use_extend
, &extend
);
13168 md_number_to_chars ((char *) buf
, 0xf000 | extend
, 2);
13169 fragp
->fr_fix
+= 2;
13173 md_number_to_chars ((char *) buf
, insn
, 2);
13174 fragp
->fr_fix
+= 2;
13179 if (fragp
->fr_opcode
== NULL
)
13182 old
= RELAX_OLD (fragp
->fr_subtype
);
13183 new = RELAX_NEW (fragp
->fr_subtype
);
13184 fixptr
= fragp
->fr_literal
+ fragp
->fr_fix
;
13187 memcpy (fixptr
- old
, fixptr
, new);
13189 fragp
->fr_fix
+= new - old
;
13195 /* This function is called after the relocs have been generated.
13196 We've been storing mips16 text labels as odd. Here we convert them
13197 back to even for the convenience of the debugger. */
13200 mips_frob_file_after_relocs ()
13203 unsigned int count
, i
;
13205 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
13208 syms
= bfd_get_outsymbols (stdoutput
);
13209 count
= bfd_get_symcount (stdoutput
);
13210 for (i
= 0; i
< count
; i
++, syms
++)
13212 if (elf_symbol (*syms
)->internal_elf_sym
.st_other
== STO_MIPS16
13213 && ((*syms
)->value
& 1) != 0)
13215 (*syms
)->value
&= ~1;
13216 /* If the symbol has an odd size, it was probably computed
13217 incorrectly, so adjust that as well. */
13218 if ((elf_symbol (*syms
)->internal_elf_sym
.st_size
& 1) != 0)
13219 ++elf_symbol (*syms
)->internal_elf_sym
.st_size
;
13226 /* This function is called whenever a label is defined. It is used
13227 when handling branch delays; if a branch has a label, we assume we
13228 can not move it. */
13231 mips_define_label (sym
)
13234 struct insn_label_list
*l
;
13236 if (free_insn_labels
== NULL
)
13237 l
= (struct insn_label_list
*) xmalloc (sizeof *l
);
13240 l
= free_insn_labels
;
13241 free_insn_labels
= l
->next
;
13245 l
->next
= insn_labels
;
13249 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13251 /* Some special processing for a MIPS ELF file. */
13254 mips_elf_final_processing ()
13256 /* Write out the register information. */
13257 if (mips_abi
!= N64_ABI
)
13261 s
.ri_gprmask
= mips_gprmask
;
13262 s
.ri_cprmask
[0] = mips_cprmask
[0];
13263 s
.ri_cprmask
[1] = mips_cprmask
[1];
13264 s
.ri_cprmask
[2] = mips_cprmask
[2];
13265 s
.ri_cprmask
[3] = mips_cprmask
[3];
13266 /* The gp_value field is set by the MIPS ELF backend. */
13268 bfd_mips_elf32_swap_reginfo_out (stdoutput
, &s
,
13269 ((Elf32_External_RegInfo
*)
13270 mips_regmask_frag
));
13274 Elf64_Internal_RegInfo s
;
13276 s
.ri_gprmask
= mips_gprmask
;
13278 s
.ri_cprmask
[0] = mips_cprmask
[0];
13279 s
.ri_cprmask
[1] = mips_cprmask
[1];
13280 s
.ri_cprmask
[2] = mips_cprmask
[2];
13281 s
.ri_cprmask
[3] = mips_cprmask
[3];
13282 /* The gp_value field is set by the MIPS ELF backend. */
13284 bfd_mips_elf64_swap_reginfo_out (stdoutput
, &s
,
13285 ((Elf64_External_RegInfo
*)
13286 mips_regmask_frag
));
13289 /* Set the MIPS ELF flag bits. FIXME: There should probably be some
13290 sort of BFD interface for this. */
13291 if (mips_any_noreorder
)
13292 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_NOREORDER
;
13293 if (mips_pic
!= NO_PIC
)
13294 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_PIC
;
13296 /* Set MIPS ELF flags for ASEs. */
13297 if (file_ase_mips16
)
13298 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ARCH_ASE_M16
;
13299 #if 0 /* XXX FIXME */
13300 if (file_ase_mips3d
)
13301 elf_elfheader (stdoutput
)->e_flags
|= ???;
13304 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ARCH_ASE_MDMX
;
13306 /* Set the MIPS ELF ABI flags. */
13307 if (mips_abi
== O32_ABI
&& USE_E_MIPS_ABI_O32
)
13308 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_O32
;
13309 else if (mips_abi
== O64_ABI
)
13310 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_O64
;
13311 else if (mips_abi
== EABI_ABI
)
13313 if (!file_mips_gp32
)
13314 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_EABI64
;
13316 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_EABI32
;
13318 else if (mips_abi
== N32_ABI
)
13319 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ABI2
;
13321 /* Nothing to do for N64_ABI. */
13323 if (mips_32bitmode
)
13324 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_32BITMODE
;
13327 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */
13329 typedef struct proc
{
13331 unsigned long reg_mask
;
13332 unsigned long reg_offset
;
13333 unsigned long fpreg_mask
;
13334 unsigned long fpreg_offset
;
13335 unsigned long frame_offset
;
13336 unsigned long frame_reg
;
13337 unsigned long pc_reg
;
13340 static procS cur_proc
;
13341 static procS
*cur_proc_ptr
;
13342 static int numprocs
;
13344 /* Fill in an rs_align_code fragment. */
13347 mips_handle_align (fragp
)
13350 if (fragp
->fr_type
!= rs_align_code
)
13353 if (mips_opts
.mips16
)
13355 static const unsigned char be_nop
[] = { 0x65, 0x00 };
13356 static const unsigned char le_nop
[] = { 0x00, 0x65 };
13361 bytes
= fragp
->fr_next
->fr_address
- fragp
->fr_address
- fragp
->fr_fix
;
13362 p
= fragp
->fr_literal
+ fragp
->fr_fix
;
13370 memcpy (p
, (target_big_endian
? be_nop
: le_nop
), 2);
13374 /* For mips32, a nop is a zero, which we trivially get by doing nothing. */
13385 /* check for premature end, nesting errors, etc */
13387 as_warn (_("missing .end at end of assembly"));
13396 if (*input_line_pointer
== '-')
13398 ++input_line_pointer
;
13401 if (!ISDIGIT (*input_line_pointer
))
13402 as_bad (_("expected simple number"));
13403 if (input_line_pointer
[0] == '0')
13405 if (input_line_pointer
[1] == 'x')
13407 input_line_pointer
+= 2;
13408 while (ISXDIGIT (*input_line_pointer
))
13411 val
|= hex_value (*input_line_pointer
++);
13413 return negative
? -val
: val
;
13417 ++input_line_pointer
;
13418 while (ISDIGIT (*input_line_pointer
))
13421 val
|= *input_line_pointer
++ - '0';
13423 return negative
? -val
: val
;
13426 if (!ISDIGIT (*input_line_pointer
))
13428 printf (_(" *input_line_pointer == '%c' 0x%02x\n"),
13429 *input_line_pointer
, *input_line_pointer
);
13430 as_warn (_("invalid number"));
13433 while (ISDIGIT (*input_line_pointer
))
13436 val
+= *input_line_pointer
++ - '0';
13438 return negative
? -val
: val
;
13441 /* The .file directive; just like the usual .file directive, but there
13442 is an initial number which is the ECOFF file index. In the non-ECOFF
13443 case .file implies DWARF-2. */
13447 int x ATTRIBUTE_UNUSED
;
13449 static int first_file_directive
= 0;
13451 if (ECOFF_DEBUGGING
)
13460 filename
= dwarf2_directive_file (0);
13462 /* Versions of GCC up to 3.1 start files with a ".file"
13463 directive even for stabs output. Make sure that this
13464 ".file" is handled. Note that you need a version of GCC
13465 after 3.1 in order to support DWARF-2 on MIPS. */
13466 if (filename
!= NULL
&& ! first_file_directive
)
13468 (void) new_logical_line (filename
, -1);
13469 s_app_file_string (filename
);
13471 first_file_directive
= 1;
13475 /* The .loc directive, implying DWARF-2. */
13479 int x ATTRIBUTE_UNUSED
;
13481 if (!ECOFF_DEBUGGING
)
13482 dwarf2_directive_loc (0);
13485 /* The .end directive. */
13489 int x ATTRIBUTE_UNUSED
;
13494 /* Following functions need their own .frame and .cprestore directives. */
13495 mips_frame_reg_valid
= 0;
13496 mips_cprestore_valid
= 0;
13498 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
13501 demand_empty_rest_of_line ();
13506 #ifdef BFD_ASSEMBLER
13507 if ((bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) != 0)
13512 if (now_seg
!= data_section
&& now_seg
!= bss_section
)
13519 as_warn (_(".end not in text section"));
13523 as_warn (_(".end directive without a preceding .ent directive."));
13524 demand_empty_rest_of_line ();
13530 assert (S_GET_NAME (p
));
13531 if (strcmp (S_GET_NAME (p
), S_GET_NAME (cur_proc_ptr
->isym
)))
13532 as_warn (_(".end symbol does not match .ent symbol."));
13534 if (debug_type
== DEBUG_STABS
)
13535 stabs_generate_asm_endfunc (S_GET_NAME (p
),
13539 as_warn (_(".end directive missing or unknown symbol"));
13542 /* Generate a .pdr section. */
13543 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
&& ! ECOFF_DEBUGGING
)
13545 segT saved_seg
= now_seg
;
13546 subsegT saved_subseg
= now_subseg
;
13551 dot
= frag_now_fix ();
13553 #ifdef md_flush_pending_output
13554 md_flush_pending_output ();
13558 subseg_set (pdr_seg
, 0);
13560 /* Write the symbol. */
13561 exp
.X_op
= O_symbol
;
13562 exp
.X_add_symbol
= p
;
13563 exp
.X_add_number
= 0;
13564 emit_expr (&exp
, 4);
13566 fragp
= frag_more (7 * 4);
13568 md_number_to_chars (fragp
, (valueT
) cur_proc_ptr
->reg_mask
, 4);
13569 md_number_to_chars (fragp
+ 4, (valueT
) cur_proc_ptr
->reg_offset
, 4);
13570 md_number_to_chars (fragp
+ 8, (valueT
) cur_proc_ptr
->fpreg_mask
, 4);
13571 md_number_to_chars (fragp
+ 12, (valueT
) cur_proc_ptr
->fpreg_offset
, 4);
13572 md_number_to_chars (fragp
+ 16, (valueT
) cur_proc_ptr
->frame_offset
, 4);
13573 md_number_to_chars (fragp
+ 20, (valueT
) cur_proc_ptr
->frame_reg
, 4);
13574 md_number_to_chars (fragp
+ 24, (valueT
) cur_proc_ptr
->pc_reg
, 4);
13576 subseg_set (saved_seg
, saved_subseg
);
13578 #endif /* OBJ_ELF */
13580 cur_proc_ptr
= NULL
;
13583 /* The .aent and .ent directives. */
13592 symbolP
= get_symbol ();
13593 if (*input_line_pointer
== ',')
13594 ++input_line_pointer
;
13595 SKIP_WHITESPACE ();
13596 if (ISDIGIT (*input_line_pointer
)
13597 || *input_line_pointer
== '-')
13600 #ifdef BFD_ASSEMBLER
13601 if ((bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) != 0)
13606 if (now_seg
!= data_section
&& now_seg
!= bss_section
)
13613 as_warn (_(".ent or .aent not in text section."));
13615 if (!aent
&& cur_proc_ptr
)
13616 as_warn (_("missing .end"));
13620 /* This function needs its own .frame and .cprestore directives. */
13621 mips_frame_reg_valid
= 0;
13622 mips_cprestore_valid
= 0;
13624 cur_proc_ptr
= &cur_proc
;
13625 memset (cur_proc_ptr
, '\0', sizeof (procS
));
13627 cur_proc_ptr
->isym
= symbolP
;
13629 symbol_get_bfdsym (symbolP
)->flags
|= BSF_FUNCTION
;
13633 if (debug_type
== DEBUG_STABS
)
13634 stabs_generate_asm_func (S_GET_NAME (symbolP
),
13635 S_GET_NAME (symbolP
));
13638 demand_empty_rest_of_line ();
13641 /* The .frame directive. If the mdebug section is present (IRIX 5 native)
13642 then ecoff.c (ecoff_directive_frame) is used. For embedded targets,
13643 s_mips_frame is used so that we can set the PDR information correctly.
13644 We can't use the ecoff routines because they make reference to the ecoff
13645 symbol table (in the mdebug section). */
13648 s_mips_frame (ignore
)
13649 int ignore ATTRIBUTE_UNUSED
;
13652 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
&& ! ECOFF_DEBUGGING
)
13656 if (cur_proc_ptr
== (procS
*) NULL
)
13658 as_warn (_(".frame outside of .ent"));
13659 demand_empty_rest_of_line ();
13663 cur_proc_ptr
->frame_reg
= tc_get_register (1);
13665 SKIP_WHITESPACE ();
13666 if (*input_line_pointer
++ != ','
13667 || get_absolute_expression_and_terminator (&val
) != ',')
13669 as_warn (_("Bad .frame directive"));
13670 --input_line_pointer
;
13671 demand_empty_rest_of_line ();
13675 cur_proc_ptr
->frame_offset
= val
;
13676 cur_proc_ptr
->pc_reg
= tc_get_register (0);
13678 demand_empty_rest_of_line ();
13681 #endif /* OBJ_ELF */
13685 /* The .fmask and .mask directives. If the mdebug section is present
13686 (IRIX 5 native) then ecoff.c (ecoff_directive_mask) is used. For
13687 embedded targets, s_mips_mask is used so that we can set the PDR
13688 information correctly. We can't use the ecoff routines because they
13689 make reference to the ecoff symbol table (in the mdebug section). */
13692 s_mips_mask (reg_type
)
13696 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
&& ! ECOFF_DEBUGGING
)
13700 if (cur_proc_ptr
== (procS
*) NULL
)
13702 as_warn (_(".mask/.fmask outside of .ent"));
13703 demand_empty_rest_of_line ();
13707 if (get_absolute_expression_and_terminator (&mask
) != ',')
13709 as_warn (_("Bad .mask/.fmask directive"));
13710 --input_line_pointer
;
13711 demand_empty_rest_of_line ();
13715 off
= get_absolute_expression ();
13717 if (reg_type
== 'F')
13719 cur_proc_ptr
->fpreg_mask
= mask
;
13720 cur_proc_ptr
->fpreg_offset
= off
;
13724 cur_proc_ptr
->reg_mask
= mask
;
13725 cur_proc_ptr
->reg_offset
= off
;
13728 demand_empty_rest_of_line ();
13731 #endif /* OBJ_ELF */
13732 s_ignore (reg_type
);
13735 /* The .loc directive. */
13746 assert (now_seg
== text_section
);
13748 lineno
= get_number ();
13749 addroff
= frag_now_fix ();
13751 symbolP
= symbol_new ("", N_SLINE
, addroff
, frag_now
);
13752 S_SET_TYPE (symbolP
, N_SLINE
);
13753 S_SET_OTHER (symbolP
, 0);
13754 S_SET_DESC (symbolP
, lineno
);
13755 symbolP
->sy_segment
= now_seg
;
13759 /* A table describing all the processors gas knows about. Names are
13760 matched in the order listed.
13762 To ease comparison, please keep this table in the same order as
13763 gcc's mips_cpu_info_table[]. */
13764 static const struct mips_cpu_info mips_cpu_info_table
[] =
13766 /* Entries for generic ISAs */
13767 { "mips1", 1, ISA_MIPS1
, CPU_R3000
},
13768 { "mips2", 1, ISA_MIPS2
, CPU_R6000
},
13769 { "mips3", 1, ISA_MIPS3
, CPU_R4000
},
13770 { "mips4", 1, ISA_MIPS4
, CPU_R8000
},
13771 { "mips5", 1, ISA_MIPS5
, CPU_MIPS5
},
13772 { "mips32", 1, ISA_MIPS32
, CPU_MIPS32
},
13773 { "mips64", 1, ISA_MIPS64
, CPU_MIPS64
},
13776 { "r3000", 0, ISA_MIPS1
, CPU_R3000
},
13777 { "r2000", 0, ISA_MIPS1
, CPU_R3000
},
13778 { "r3900", 0, ISA_MIPS1
, CPU_R3900
},
13781 { "r6000", 0, ISA_MIPS2
, CPU_R6000
},
13784 { "r4000", 0, ISA_MIPS3
, CPU_R4000
},
13785 { "r4010", 0, ISA_MIPS2
, CPU_R4010
},
13786 { "vr4100", 0, ISA_MIPS3
, CPU_VR4100
},
13787 { "vr4111", 0, ISA_MIPS3
, CPU_R4111
},
13788 { "vr4120", 0, ISA_MIPS3
, CPU_VR4120
},
13789 { "vr4130", 0, ISA_MIPS3
, CPU_VR4120
},
13790 { "vr4181", 0, ISA_MIPS3
, CPU_R4111
},
13791 { "vr4300", 0, ISA_MIPS3
, CPU_R4300
},
13792 { "r4400", 0, ISA_MIPS3
, CPU_R4400
},
13793 { "r4600", 0, ISA_MIPS3
, CPU_R4600
},
13794 { "orion", 0, ISA_MIPS3
, CPU_R4600
},
13795 { "r4650", 0, ISA_MIPS3
, CPU_R4650
},
13798 { "r8000", 0, ISA_MIPS4
, CPU_R8000
},
13799 { "r10000", 0, ISA_MIPS4
, CPU_R10000
},
13800 { "r12000", 0, ISA_MIPS4
, CPU_R12000
},
13801 { "vr5000", 0, ISA_MIPS4
, CPU_R5000
},
13802 { "vr5400", 0, ISA_MIPS4
, CPU_VR5400
},
13803 { "vr5500", 0, ISA_MIPS4
, CPU_VR5500
},
13804 { "rm5200", 0, ISA_MIPS4
, CPU_R5000
},
13805 { "rm5230", 0, ISA_MIPS4
, CPU_R5000
},
13806 { "rm5231", 0, ISA_MIPS4
, CPU_R5000
},
13807 { "rm5261", 0, ISA_MIPS4
, CPU_R5000
},
13808 { "rm5721", 0, ISA_MIPS4
, CPU_R5000
},
13809 { "r7000", 0, ISA_MIPS4
, CPU_R5000
},
13812 { "4kc", 0, ISA_MIPS32
, CPU_MIPS32
, },
13813 { "4km", 0, ISA_MIPS32
, CPU_MIPS32
},
13814 { "4kp", 0, ISA_MIPS32
, CPU_MIPS32
},
13817 { "5kc", 0, ISA_MIPS64
, CPU_MIPS64
},
13818 { "20kc", 0, ISA_MIPS64
, CPU_MIPS64
},
13820 /* Broadcom SB-1 CPU core */
13821 { "sb1", 0, ISA_MIPS64
, CPU_SB1
},
13828 /* Return true if GIVEN is the same as CANONICAL, or if it is CANONICAL
13829 with a final "000" replaced by "k". Ignore case.
13831 Note: this function is shared between GCC and GAS. */
13834 mips_strict_matching_cpu_name_p (canonical
, given
)
13835 const char *canonical
, *given
;
13837 while (*given
!= 0 && TOLOWER (*given
) == TOLOWER (*canonical
))
13838 given
++, canonical
++;
13840 return ((*given
== 0 && *canonical
== 0)
13841 || (strcmp (canonical
, "000") == 0 && strcasecmp (given
, "k") == 0));
13845 /* Return true if GIVEN matches CANONICAL, where GIVEN is a user-supplied
13846 CPU name. We've traditionally allowed a lot of variation here.
13848 Note: this function is shared between GCC and GAS. */
13851 mips_matching_cpu_name_p (canonical
, given
)
13852 const char *canonical
, *given
;
13854 /* First see if the name matches exactly, or with a final "000"
13855 turned into "k". */
13856 if (mips_strict_matching_cpu_name_p (canonical
, given
))
13859 /* If not, try comparing based on numerical designation alone.
13860 See if GIVEN is an unadorned number, or 'r' followed by a number. */
13861 if (TOLOWER (*given
) == 'r')
13863 if (!ISDIGIT (*given
))
13866 /* Skip over some well-known prefixes in the canonical name,
13867 hoping to find a number there too. */
13868 if (TOLOWER (canonical
[0]) == 'v' && TOLOWER (canonical
[1]) == 'r')
13870 else if (TOLOWER (canonical
[0]) == 'r' && TOLOWER (canonical
[1]) == 'm')
13872 else if (TOLOWER (canonical
[0]) == 'r')
13875 return mips_strict_matching_cpu_name_p (canonical
, given
);
13879 /* Parse an option that takes the name of a processor as its argument.
13880 OPTION is the name of the option and CPU_STRING is the argument.
13881 Return the corresponding processor enumeration if the CPU_STRING is
13882 recognized, otherwise report an error and return null.
13884 A similar function exists in GCC. */
13886 static const struct mips_cpu_info
*
13887 mips_parse_cpu (option
, cpu_string
)
13888 const char *option
, *cpu_string
;
13890 const struct mips_cpu_info
*p
;
13892 /* 'from-abi' selects the most compatible architecture for the given
13893 ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit ABIs. For the
13894 EABIs, we have to decide whether we're using the 32-bit or 64-bit
13895 version. Look first at the -mgp options, if given, otherwise base
13896 the choice on MIPS_DEFAULT_64BIT.
13898 Treat NO_ABI like the EABIs. One reason to do this is that the
13899 plain 'mips' and 'mips64' configs have 'from-abi' as their default
13900 architecture. This code picks MIPS I for 'mips' and MIPS III for
13901 'mips64', just as we did in the days before 'from-abi'. */
13902 if (strcasecmp (cpu_string
, "from-abi") == 0)
13904 if (ABI_NEEDS_32BIT_REGS (mips_abi
))
13905 return mips_cpu_info_from_isa (ISA_MIPS1
);
13907 if (ABI_NEEDS_64BIT_REGS (mips_abi
))
13908 return mips_cpu_info_from_isa (ISA_MIPS3
);
13910 if (file_mips_gp32
>= 0)
13911 return mips_cpu_info_from_isa (file_mips_gp32
? ISA_MIPS1
: ISA_MIPS3
);
13913 return mips_cpu_info_from_isa (MIPS_DEFAULT_64BIT
13918 /* 'default' has traditionally been a no-op. Probably not very useful. */
13919 if (strcasecmp (cpu_string
, "default") == 0)
13922 for (p
= mips_cpu_info_table
; p
->name
!= 0; p
++)
13923 if (mips_matching_cpu_name_p (p
->name
, cpu_string
))
13926 as_bad ("Bad value (%s) for %s", cpu_string
, option
);
13930 /* Return the canonical processor information for ISA (a member of the
13931 ISA_MIPS* enumeration). */
13933 static const struct mips_cpu_info
*
13934 mips_cpu_info_from_isa (isa
)
13939 for (i
= 0; mips_cpu_info_table
[i
].name
!= NULL
; i
++)
13940 if (mips_cpu_info_table
[i
].is_isa
13941 && isa
== mips_cpu_info_table
[i
].isa
)
13942 return (&mips_cpu_info_table
[i
]);
13948 show (stream
, string
, col_p
, first_p
)
13950 const char *string
;
13956 fprintf (stream
, "%24s", "");
13961 fprintf (stream
, ", ");
13965 if (*col_p
+ strlen (string
) > 72)
13967 fprintf (stream
, "\n%24s", "");
13971 fprintf (stream
, "%s", string
);
13972 *col_p
+= strlen (string
);
13978 md_show_usage (stream
)
13984 fprintf (stream
, _("\
13986 -membedded-pic generate embedded position independent code\n\
13987 -EB generate big endian output\n\
13988 -EL generate little endian output\n\
13989 -g, -g2 do not remove unneeded NOPs or swap branches\n\
13990 -G NUM allow referencing objects up to NUM bytes\n\
13991 implicitly with the gp register [default 8]\n"));
13992 fprintf (stream
, _("\
13993 -mips1 generate MIPS ISA I instructions\n\
13994 -mips2 generate MIPS ISA II instructions\n\
13995 -mips3 generate MIPS ISA III instructions\n\
13996 -mips4 generate MIPS ISA IV instructions\n\
13997 -mips5 generate MIPS ISA V instructions\n\
13998 -mips32 generate MIPS32 ISA instructions\n\
13999 -mips64 generate MIPS64 ISA instructions\n\
14000 -march=CPU/-mtune=CPU generate code/schedule for CPU, where CPU is one of:\n"));
14004 for (i
= 0; mips_cpu_info_table
[i
].name
!= NULL
; i
++)
14005 show (stream
, mips_cpu_info_table
[i
].name
, &column
, &first
);
14006 show (stream
, "from-abi", &column
, &first
);
14007 fputc ('\n', stream
);
14009 fprintf (stream
, _("\
14010 -mCPU equivalent to -march=CPU -mtune=CPU. Deprecated.\n\
14011 -no-mCPU don't generate code specific to CPU.\n\
14012 For -mCPU and -no-mCPU, CPU must be one of:\n"));
14016 show (stream
, "3900", &column
, &first
);
14017 show (stream
, "4010", &column
, &first
);
14018 show (stream
, "4100", &column
, &first
);
14019 show (stream
, "4650", &column
, &first
);
14020 fputc ('\n', stream
);
14022 fprintf (stream
, _("\
14023 -mips16 generate mips16 instructions\n\
14024 -no-mips16 do not generate mips16 instructions\n"));
14025 fprintf (stream
, _("\
14026 -mgp32 use 32-bit GPRs, regardless of the chosen ISA\n\
14027 -mfp32 use 32-bit FPRs, regardless of the chosen ISA\n\
14028 -O0 remove unneeded NOPs, do not swap branches\n\
14029 -O remove unneeded NOPs and swap branches\n\
14030 -n warn about NOPs generated from macros\n\
14031 --[no-]construct-floats [dis]allow floating point values to be constructed\n\
14032 --trap, --no-break trap exception on div by 0 and mult overflow\n\
14033 --break, --no-trap break exception on div by 0 and mult overflow\n"));
14035 fprintf (stream
, _("\
14036 -KPIC, -call_shared generate SVR4 position independent code\n\
14037 -non_shared do not generate position independent code\n\
14038 -xgot assume a 32 bit GOT\n\
14039 -mabi=ABI create ABI conformant object file for:\n"));
14043 show (stream
, "32", &column
, &first
);
14044 show (stream
, "o64", &column
, &first
);
14045 show (stream
, "n32", &column
, &first
);
14046 show (stream
, "64", &column
, &first
);
14047 show (stream
, "eabi", &column
, &first
);
14049 fputc ('\n', stream
);
14051 fprintf (stream
, _("\
14052 -32 create o32 ABI object file (default)\n\
14053 -n32 create n32 ABI object file\n\
14054 -64 create 64 ABI object file\n"));