1 /* tc-mips.c -- assemble code for a MIPS chip.
2 Copyright (C) 1993 Free Software Foundation, Inc.
3 Contributed by the OSF and Ralph Campbell.
4 Written by Keith Knowles and Ralph Campbell, working independently.
5 Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus
8 This file is part of GAS.
10 GAS is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 2, or (at your option)
15 GAS is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with GAS; see the file COPYING. If not, write to
22 the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */
27 #include "libiberty.h"
42 #endif /* NO_VARARGS */
43 #endif /* NO_STDARG */
45 #include "opcode/mips.h"
50 static char *mips_regmask_frag
;
54 #define PIC_CALL_REG 25
62 /* Decide whether to do GP reference optimizations based on the object
72 /* The default target format to use. */
74 #ifdef TARGET_BYTES_BIG_ENDIAN
75 #define DEFAULT_TARGET_FORMAT "a.out-mips-big"
77 #define DEFAULT_TARGET_FORMAT "a.out-mips-little"
81 #ifdef TARGET_BYTES_BIG_ENDIAN
82 #define DEFAULT_TARGET_FORMAT "ecoff-bigmips"
84 #define DEFAULT_TARGET_FORMAT "ecoff-littlemips"
86 #endif /* OBJ_ECOFF */
88 #ifdef TARGET_BYTES_BIG_ENDIAN
89 #define DEFAULT_TARGET_FORMAT "elf32-bigmips"
91 #define DEFAULT_TARGET_FORMAT "elf32-littlemips"
95 const char *mips_target_format
= DEFAULT_TARGET_FORMAT
;
97 /* The name of the readonly data section. */
99 #define RDATA_SECTION_NAME ".data"
102 #define RDATA_SECTION_NAME ".rdata"
105 #define RDATA_SECTION_NAME ".rodata"
108 /* These variables are filled in with the masks of registers used.
109 The object format code reads them and puts them in the appropriate
111 unsigned long mips_gprmask
;
112 unsigned long mips_cprmask
[4];
114 /* MIPS ISA (Instruction Set Architecture) level (may be changed
115 temporarily using .set mipsN). */
116 static int mips_isa
= -1;
118 /* MIPS ISA we are using for this output file. */
119 static int file_mips_isa
;
121 /* The CPU type as a number: 2000, 3000, 4000, 4400, etc. */
122 static int mips_cpu
= -1;
124 /* Whether the 4650 instructions (mad/madu) are permitted. */
125 static int mips_4650
= -1;
127 /* MIPS PIC level. */
131 /* Do not generate PIC code. */
134 /* Generate PIC code as in Irix 4. This is not implemented, and I'm
135 not sure what it is supposed to do. */
138 /* Generate PIC code as in the SVR4 MIPS ABI. */
141 /* Generate PIC code without using a global offset table: the data
142 segment has a maximum size of 64K, all data references are off
143 the $gp register, and all text references are PC relative. This
144 is used on some embedded systems. */
148 static enum mips_pic_level mips_pic
;
150 /* 1 if trap instructions should used for overflow rather than break
152 static int mips_trap
;
154 static int mips_warn_about_macros
;
155 static int mips_noreorder
;
156 static int mips_any_noreorder
;
157 static int mips_nomove
;
158 static int mips_noat
;
159 static int mips_nobopt
;
162 /* The size of the small data section. */
163 static int g_switch_value
= 8;
164 /* Whether the -G option was used. */
165 static int g_switch_seen
= 0;
171 /* handle of the OPCODE hash table */
172 static struct hash_control
*op_hash
= NULL
;
174 /* This array holds the chars that always start a comment. If the
175 pre-processor is disabled, these aren't very useful */
176 const char comment_chars
[] = "#";
178 /* This array holds the chars that only start a comment at the beginning of
179 a line. If the line seems to have the form '# 123 filename'
180 .line and .file directives will appear in the pre-processed output */
181 /* Note that input_file.c hand checks for '#' at the beginning of the
182 first line of the input file. This is because the compiler outputs
183 #NO_APP at the beginning of its output. */
184 /* Also note that C style comments are always supported. */
185 const char line_comment_chars
[] = "#";
187 /* This array holds machine specific line separator characters. */
188 const char line_separator_chars
[] = "";
190 /* Chars that can be used to separate mant from exp in floating point nums */
191 const char EXP_CHARS
[] = "eE";
193 /* Chars that mean this number is a floating point constant */
196 const char FLT_CHARS
[] = "rRsSfFdDxXpP";
198 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
199 changed in read.c . Ideally it shouldn't have to know about it at all,
200 but nothing is ideal around here.
203 static char *insn_error
;
205 static int byte_order
= BYTE_ORDER
;
207 static int auto_align
= 1;
209 /* Symbol labelling the current insn. */
210 static symbolS
*insn_label
;
212 /* When outputting SVR4 PIC code, the assembler needs to know the
213 offset in the stack frame from which to restore the $gp register.
214 This is set by the .cprestore pseudo-op, and saved in this
216 static offsetT mips_cprestore_offset
= -1;
218 /* This is the register which holds the stack frame, as set by the
219 .frame pseudo-op. This is needed to implement .cprestore. */
220 static int mips_frame_reg
= SP
;
222 /* To output NOP instructions correctly, we need to keep information
223 about the previous two instructions. */
225 /* Whether we are optimizing. The default value of 2 means to remove
226 unneeded NOPs and swap branch instructions when possible. A value
227 of 1 means to not swap branches. A value of 0 means to always
229 static int mips_optimize
= 2;
231 /* The previous instruction. */
232 static struct mips_cl_insn prev_insn
;
234 /* The instruction before prev_insn. */
235 static struct mips_cl_insn prev_prev_insn
;
237 /* If we don't want information for prev_insn or prev_prev_insn, we
238 point the insn_mo field at this dummy integer. */
239 static const struct mips_opcode dummy_opcode
= { 0 };
241 /* Non-zero if prev_insn is valid. */
242 static int prev_insn_valid
;
244 /* The frag for the previous instruction. */
245 static struct frag
*prev_insn_frag
;
247 /* The offset into prev_insn_frag for the previous instruction. */
248 static long prev_insn_where
;
250 /* The reloc for the previous instruction, if any. */
251 static fixS
*prev_insn_fixp
;
253 /* Non-zero if the previous instruction was in a delay slot. */
254 static int prev_insn_is_delay_slot
;
256 /* Non-zero if the previous instruction was in a .set noreorder. */
257 static int prev_insn_unreordered
;
259 /* Non-zero if the previous previous instruction was in a .set
261 static int prev_prev_insn_unreordered
;
263 /* Since the MIPS does not have multiple forms of PC relative
264 instructions, we do not have to do relaxing as is done on other
265 platforms. However, we do have to handle GP relative addressing
266 correctly, which turns out to be a similar problem.
268 Every macro that refers to a symbol can occur in (at least) two
269 forms, one with GP relative addressing and one without. For
270 example, loading a global variable into a register generally uses
271 a macro instruction like this:
273 If i can be addressed off the GP register (this is true if it is in
274 the .sbss or .sdata section, or if it is known to be smaller than
275 the -G argument) this will generate the following instruction:
277 This instruction will use a GPREL reloc. If i can not be addressed
278 off the GP register, the following instruction sequence will be used:
281 In this case the first instruction will have a HI16 reloc, and the
282 second reloc will have a LO16 reloc. Both relocs will be against
285 The issue here is that we may not know whether i is GP addressable
286 until after we see the instruction that uses it. Therefore, we
287 want to be able to choose the final instruction sequence only at
288 the end of the assembly. This is similar to the way other
289 platforms choose the size of a PC relative instruction only at the
292 When generating position independent code we do not use GP
293 addressing in quite the same way, but the issue still arises as
294 external symbols and local symbols must be handled differently.
296 We handle these issues by actually generating both possible
297 instruction sequences. The longer one is put in a frag_var with
298 type rs_machine_dependent. We encode what to do with the frag in
299 the subtype field. We encode (1) the number of existing bytes to
300 replace, (2) the number of new bytes to use, (3) the offset from
301 the start of the existing bytes to the first reloc we must generate
302 (that is, the offset is applied from the start of the existing
303 bytes after they are replaced by the new bytes, if any), (4) the
304 offset from the start of the existing bytes to the second reloc,
305 (5) whether a third reloc is needed (the third reloc is always four
306 bytes after the second reloc), and (6) whether to warn if this
307 variant is used (this is sometimes needed if .set nomacro or .set
308 noat is in effect). All these numbers are reasonably small.
310 Generating two instruction sequences must be handled carefully to
311 ensure that delay slots are handled correctly. Fortunately, there
312 are a limited number of cases. When the second instruction
313 sequence is generated, append_insn is directed to maintain the
314 existing delay slot information, so it continues to apply to any
315 code after the second instruction sequence. This means that the
316 second instruction sequence must not impose any requirements not
317 required by the first instruction sequence.
319 These variant frags are then handled in functions called by the
320 machine independent code. md_estimate_size_before_relax returns
321 the final size of the frag. md_convert_frag sets up the final form
322 of the frag. tc_gen_reloc adjust the first reloc and adds a second
324 #define RELAX_ENCODE(old, new, reloc1, reloc2, reloc3, warn) \
328 | (((reloc1) + 64) << 9) \
329 | (((reloc2) + 64) << 2) \
330 | ((reloc3) ? (1 << 1) : 0) \
332 #define RELAX_OLD(i) (((i) >> 24) & 0xff)
333 #define RELAX_NEW(i) (((i) >> 16) & 0xff)
334 #define RELAX_RELOC1(i) ((bfd_vma)(((i) >> 9) & 0x7f) - 64)
335 #define RELAX_RELOC2(i) ((bfd_vma)(((i) >> 2) & 0x7f) - 64)
336 #define RELAX_RELOC3(i) (((i) >> 1) & 1)
337 #define RELAX_WARN(i) ((i) & 1)
339 /* Prototypes for static functions. */
342 #define internalError() \
343 as_fatal ("internal Error, line %d, %s", __LINE__, __FILE__)
345 #define internalError() as_fatal ("MIPS internal Error");
348 static int insn_uses_reg
PARAMS ((struct mips_cl_insn
*ip
,
349 unsigned int reg
, int fpr
));
350 static void append_insn
PARAMS ((char *place
,
351 struct mips_cl_insn
* ip
,
353 bfd_reloc_code_real_type r
));
354 static void mips_no_prev_insn
PARAMS ((void));
355 static void mips_emit_delays
PARAMS ((void));
356 static void macro_build
PARAMS ((char *place
, int *counter
, expressionS
* ep
,
357 const char *name
, const char *fmt
,
359 static void macro_build_lui
PARAMS ((char *place
, int *counter
,
360 expressionS
* ep
, int regnum
));
361 static void set_at
PARAMS ((int *counter
, int reg
, int unsignedp
));
362 static void check_absolute_expr
PARAMS ((struct mips_cl_insn
* ip
,
364 static void load_register
PARAMS ((int *counter
, int reg
, expressionS
* ep
));
365 static void load_address
PARAMS ((int *counter
, int reg
, expressionS
*ep
));
366 static void macro
PARAMS ((struct mips_cl_insn
* ip
));
367 #ifdef LOSING_COMPILER
368 static void macro2
PARAMS ((struct mips_cl_insn
* ip
));
370 static void mips_ip
PARAMS ((char *str
, struct mips_cl_insn
* ip
));
371 static int my_getSmallExpression
PARAMS ((expressionS
* ep
, char *str
));
372 static void my_getExpression
PARAMS ((expressionS
* ep
, char *str
));
373 static symbolS
*get_symbol
PARAMS ((void));
374 static void mips_align
PARAMS ((int to
, int fill
, symbolS
*label
));
375 static void s_align
PARAMS ((int));
376 static void s_stringer
PARAMS ((int));
377 static void s_change_sec
PARAMS ((int));
378 static void s_cons
PARAMS ((int));
379 static void s_err
PARAMS ((int));
380 static void s_extern
PARAMS ((int));
381 static void s_float_cons
PARAMS ((int));
382 static void s_mips_globl
PARAMS ((int));
383 static void s_option
PARAMS ((int));
384 static void s_mipsset
PARAMS ((int));
385 static void s_mips_space
PARAMS ((int));
386 static void s_abicalls
PARAMS ((int));
387 static void s_cpload
PARAMS ((int));
388 static void s_cprestore
PARAMS ((int));
389 static void s_gpword
PARAMS ((int));
390 static void s_cpadd
PARAMS ((int));
391 #ifndef ECOFF_DEBUGGING
392 static void md_obj_begin
PARAMS ((void));
393 static void md_obj_end
PARAMS ((void));
394 static long get_number
PARAMS ((void));
395 static void s_ent
PARAMS ((int));
396 static void s_mipsend
PARAMS ((int));
397 static void s_file
PARAMS ((int));
399 static void s_frame
PARAMS ((int));
400 static void s_loc
PARAMS ((int));
401 static void s_mask
PARAMS ((char));
405 static void s_elf_section
PARAMS ((int));
410 The following pseudo-ops from the Kane and Heinrich MIPS book
411 should be defined here, but are currently unsupported: .alias,
412 .galive, .gjaldef, .gjrlive, .livereg, .noalias.
414 The following pseudo-ops from the Kane and Heinrich MIPS book are
415 specific to the type of debugging information being generated, and
416 should be defined by the object format: .aent, .begin, .bend,
417 .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp,
420 The following pseudo-ops from the Kane and Heinrich MIPS book are
421 not MIPS CPU specific, but are also not specific to the object file
422 format. This file is probably the best place to define them, but
423 they are not currently supported: .asm0, .endr, .lab, .repeat,
424 .struct, .weakext. */
426 const pseudo_typeS md_pseudo_table
[] =
428 /* MIPS specific pseudo-ops. */
429 {"option", s_option
, 0},
430 {"set", s_mipsset
, 0},
431 {"rdata", s_change_sec
, 'r'},
432 {"sdata", s_change_sec
, 's'},
433 {"livereg", s_ignore
, 0},
434 { "abicalls", s_abicalls
, 0},
435 { "cpload", s_cpload
, 0},
436 { "cprestore", s_cprestore
, 0},
437 { "gpword", s_gpword
, 0},
438 { "cpadd", s_cpadd
, 0},
440 /* Relatively generic pseudo-ops that happen to be used on MIPS
442 {"asciiz", s_stringer
, 1},
443 {"bss", s_change_sec
, 'b'},
446 {"dword", s_cons
, 3},
448 /* These pseudo-ops are defined in read.c, but must be overridden
449 here for one reason or another. */
450 {"align", s_align
, 0},
451 {"ascii", s_stringer
, 0},
452 {"asciz", s_stringer
, 1},
454 {"data", s_change_sec
, 'd'},
455 {"double", s_float_cons
, 'd'},
456 {"extern", s_extern
, 0},
457 {"float", s_float_cons
, 'f'},
458 {"globl", s_mips_globl
, 0},
459 {"global", s_mips_globl
, 0},
460 {"hword", s_cons
, 1},
465 {"short", s_cons
, 1},
466 {"single", s_float_cons
, 'f'},
467 {"space", s_mips_space
, 0},
468 {"text", s_change_sec
, 't'},
471 #ifndef ECOFF_DEBUGGING
472 /* These pseudo-ops should be defined by the object file format.
473 However, a.out doesn't support them, so we have versions here. */
475 {"bgnb", s_ignore
, 0},
476 {"end", s_mipsend
, 0},
477 {"endb", s_ignore
, 0},
480 {"fmask", s_ignore
, 'F'},
481 {"frame", s_ignore
, 0},
482 {"loc", s_ignore
, 0},
483 {"mask", s_ignore
, 'R'},
484 {"verstamp", s_ignore
, 0},
488 /* We need to tweak the ELF ".section" pseudo-op a bit. */
489 {"section", s_elf_section
, 0},
491 /* Redirect additional ELF data allocation pseudo-ops. */
492 {"2byte", s_cons
, 2},
493 {"4byte", s_cons
, 4},
494 {"8byte", s_cons
, 8},
501 const relax_typeS md_relax_table
[] =
506 static char *expr_end
;
508 static expressionS imm_expr
;
509 static expressionS offset_expr
;
510 static bfd_reloc_code_real_type imm_reloc
;
511 static bfd_reloc_code_real_type offset_reloc
;
513 /* FIXME: This should be handled in a different way. */
514 extern int target_big_endian
;
517 * This function is called once, at assembler startup time. It should
518 * set up all the tables, etc. that the MD part of the assembler will need.
524 register const char *retval
= NULL
;
525 register unsigned int i
= 0;
533 if (strcmp (cpu
+ (sizeof TARGET_CPU
) - 3, "el") == 0)
535 a
= xmalloc (sizeof TARGET_CPU
);
536 strcpy (a
, TARGET_CPU
);
537 a
[(sizeof TARGET_CPU
) - 3] = '\0';
541 if (strcmp (cpu
, "mips") == 0)
547 else if (strcmp (cpu
, "r6000") == 0
548 || strcmp (cpu
, "mips2") == 0)
554 else if (strcmp (cpu
, "mips64") == 0
555 || strcmp (cpu
, "r4000") == 0
556 || strcmp (cpu
, "mips3") == 0)
562 else if (strcmp (cpu
, "r4400") == 0)
568 else if (strcmp (cpu
, "mips64orion") == 0
569 || strcmp (cpu
, "r4600") == 0)
575 else if (strcmp (cpu
, "r4650") == 0)
597 if (mips_isa
< 2 && mips_trap
)
598 as_bad ("trap exception not supported at ISA 1");
603 ok
= bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, 3000);
606 ok
= bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, 6000);
609 ok
= bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, 4000);
613 as_warn ("Could not set architecture and machine");
615 file_mips_isa
= mips_isa
;
617 op_hash
= hash_new ();
619 for (i
= 0; i
< NUMOPCODES
;)
621 const char *name
= mips_opcodes
[i
].name
;
623 retval
= hash_insert (op_hash
, name
, (PTR
) &mips_opcodes
[i
]);
626 fprintf (stderr
, "internal error: can't hash `%s': %s\n",
627 mips_opcodes
[i
].name
, retval
);
628 as_fatal ("Broken assembler. No assembly attempted.");
632 if (mips_opcodes
[i
].pinfo
!= INSN_MACRO
633 && ((mips_opcodes
[i
].match
& mips_opcodes
[i
].mask
)
634 != mips_opcodes
[i
].match
))
636 fprintf (stderr
, "internal error: bad opcode: `%s' \"%s\"\n",
637 mips_opcodes
[i
].name
, mips_opcodes
[i
].args
);
638 as_fatal ("Broken assembler. No assembly attempted.");
642 while ((i
< NUMOPCODES
) && !strcmp (mips_opcodes
[i
].name
, name
));
645 mips_no_prev_insn ();
653 /* set the default alignment for the text section (2**2) */
654 record_alignment (text_section
, 2);
656 /* FIXME: This should be handled in a different way. */
657 target_big_endian
= byte_order
== BIG_ENDIAN
;
660 bfd_set_gp_size (stdoutput
, g_switch_value
);
664 /* Sections must be aligned to 16 byte boundaries. */
665 (void) bfd_set_section_alignment (stdoutput
, text_section
, 4);
666 (void) bfd_set_section_alignment (stdoutput
, data_section
, 4);
667 (void) bfd_set_section_alignment (stdoutput
, bss_section
, 4);
669 /* Create a .reginfo section for register masks and a .mdebug
670 section for debugging information. */
678 sec
= subseg_new (".reginfo", (subsegT
) 0);
680 /* The ABI says this section should be loaded so that the running
681 program can access it. */
682 (void) bfd_set_section_flags (stdoutput
, sec
,
683 (SEC_ALLOC
| SEC_LOAD
684 | SEC_READONLY
| SEC_DATA
));
685 (void) bfd_set_section_alignment (stdoutput
, sec
, 2);
687 mips_regmask_frag
= frag_more (sizeof (Elf32_External_RegInfo
));
689 #ifdef ECOFF_DEBUGGING
690 sec
= subseg_new (".mdebug", (subsegT
) 0);
691 (void) bfd_set_section_flags (stdoutput
, sec
,
692 SEC_HAS_CONTENTS
| SEC_READONLY
);
693 (void) bfd_set_section_alignment (stdoutput
, sec
, 2);
696 subseg_set (seg
, subseg
);
700 #ifndef ECOFF_DEBUGGING
708 #ifndef ECOFF_DEBUGGING
717 struct mips_cl_insn insn
;
719 imm_expr
.X_op
= O_absent
;
720 offset_expr
.X_op
= O_absent
;
722 mips_ip (str
, &insn
);
725 as_bad ("%s `%s'", insn_error
, str
);
728 if (insn
.insn_mo
->pinfo
== INSN_MACRO
)
734 if (imm_expr
.X_op
!= O_absent
)
735 append_insn ((char *) NULL
, &insn
, &imm_expr
, imm_reloc
);
736 else if (offset_expr
.X_op
!= O_absent
)
737 append_insn ((char *) NULL
, &insn
, &offset_expr
, offset_reloc
);
739 append_insn ((char *) NULL
, &insn
, NULL
, BFD_RELOC_UNUSED
);
743 /* See whether instruction IP reads register REG. If FPR is non-zero,
744 REG is a floating point register. */
747 insn_uses_reg (ip
, reg
, fpr
)
748 struct mips_cl_insn
*ip
;
752 /* Don't report on general register 0, since it never changes. */
753 if (! fpr
&& reg
== 0)
758 /* If we are called with either $f0 or $f1, we must check $f0.
759 This is not optimal, because it will introduce an unnecessary
760 NOP between "lwc1 $f0" and "swc1 $f1". To fix this we would
761 need to distinguish reading both $f0 and $f1 or just one of
762 them. Note that we don't have to check the other way,
763 because there is no instruction that sets both $f0 and $f1
764 and requires a delay. */
765 if ((ip
->insn_mo
->pinfo
& INSN_READ_FPR_S
)
766 && (((ip
->insn_opcode
>> OP_SH_FS
) & OP_MASK_FS
)
767 == (reg
&~ (unsigned) 1)))
769 if ((ip
->insn_mo
->pinfo
& INSN_READ_FPR_T
)
770 && (((ip
->insn_opcode
>> OP_SH_FT
) & OP_MASK_FT
)
771 == (reg
&~ (unsigned) 1)))
776 if ((ip
->insn_mo
->pinfo
& INSN_READ_GPR_S
)
777 && ((ip
->insn_opcode
>> OP_SH_RS
) & OP_MASK_RS
) == reg
)
779 if ((ip
->insn_mo
->pinfo
& INSN_READ_GPR_T
)
780 && ((ip
->insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
) == reg
)
787 /* Output an instruction. PLACE is where to put the instruction; if
788 it is NULL, this uses frag_more to get room. IP is the instruction
789 information. ADDRESS_EXPR is an operand of the instruction to be
790 used with RELOC_TYPE. */
793 append_insn (place
, ip
, address_expr
, reloc_type
)
795 struct mips_cl_insn
*ip
;
796 expressionS
*address_expr
;
797 bfd_reloc_code_real_type reloc_type
;
799 register unsigned long prev_pinfo
, pinfo
;
804 prev_pinfo
= prev_insn
.insn_mo
->pinfo
;
805 pinfo
= ip
->insn_mo
->pinfo
;
807 if (place
== NULL
&& ! mips_noreorder
)
809 /* If the previous insn required any delay slots, see if we need
810 to insert a NOP or two. There are eight kinds of possible
811 hazards, of which an instruction can have at most one type.
812 (1) a load from memory delay
813 (2) a load from a coprocessor delay
814 (3) an unconditional branch delay
815 (4) a conditional branch delay
816 (5) a move to coprocessor register delay
817 (6) a load coprocessor register from memory delay
818 (7) a coprocessor condition code delay
819 (8) a HI/LO special register delay
821 There are a lot of optimizations we could do that we don't.
822 In particular, we do not, in general, reorder instructions.
823 If you use gcc with optimization, it will reorder
824 instructions and generally do much more optimization then we
825 do here; repeating all that work in the assembler would only
826 benefit hand written assembly code, and does not seem worth
829 /* This is how a NOP is emitted. */
830 #define emit_nop() md_number_to_chars (frag_more (4), 0, 4)
832 /* The previous insn might require a delay slot, depending upon
833 the contents of the current insn. */
834 if ((prev_pinfo
& INSN_LOAD_COPROC_DELAY
)
836 && (prev_pinfo
& INSN_LOAD_MEMORY_DELAY
)))
838 /* A load from a coprocessor or from memory. All load
839 delays delay the use of general register rt for one
840 instruction on the r3000. The r6000 and r4000 use
842 know (prev_pinfo
& INSN_WRITE_GPR_T
);
843 if (mips_optimize
== 0
844 || insn_uses_reg (ip
,
845 ((prev_insn
.insn_opcode
>> OP_SH_RT
)
850 else if ((prev_pinfo
& INSN_COPROC_MOVE_DELAY
)
852 && (prev_pinfo
& INSN_COPROC_MEMORY_DELAY
)))
854 /* A generic coprocessor delay. The previous instruction
855 modified a coprocessor general or control register. If
856 it modified a control register, we need to avoid any
857 coprocessor instruction (this is probably not always
858 required, but it sometimes is). If it modified a general
859 register, we avoid using that register.
861 On the r6000 and r4000 loading a coprocessor register
862 from memory is interlocked, and does not require a delay.
864 This case is not handled very well. There is no special
865 knowledge of CP0 handling, and the coprocessors other
866 than the floating point unit are not distinguished at
868 if (prev_pinfo
& INSN_WRITE_FPR_T
)
870 if (mips_optimize
== 0
871 || insn_uses_reg (ip
,
872 ((prev_insn
.insn_opcode
>> OP_SH_FT
)
877 else if (prev_pinfo
& INSN_WRITE_FPR_S
)
879 if (mips_optimize
== 0
880 || insn_uses_reg (ip
,
881 ((prev_insn
.insn_opcode
>> OP_SH_FS
)
888 /* We don't know exactly what the previous instruction
889 does. If the current instruction uses a coprocessor
890 register, we must insert a NOP. If previous
891 instruction may set the condition codes, and the
892 current instruction uses them, we must insert two
894 if (mips_optimize
== 0
895 || ((prev_pinfo
& INSN_WRITE_COND_CODE
)
896 && (pinfo
& INSN_READ_COND_CODE
)))
898 else if (pinfo
& INSN_COP
)
902 else if (prev_pinfo
& INSN_WRITE_COND_CODE
)
904 /* The previous instruction sets the coprocessor condition
905 codes, but does not require a general coprocessor delay
906 (this means it is a floating point comparison
907 instruction). If this instruction uses the condition
908 codes, we need to insert a single NOP. */
909 if (mips_optimize
== 0
910 || (pinfo
& INSN_READ_COND_CODE
))
913 else if (prev_pinfo
& INSN_READ_LO
)
915 /* The previous instruction reads the LO register; if the
916 current instruction writes to the LO register, we must
917 insert two NOPS. The R4650 has interlocks. */
919 && (mips_optimize
== 0
920 || (pinfo
& INSN_WRITE_LO
)))
923 else if (prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
925 /* The previous instruction reads the HI register; if the
926 current instruction writes to the HI register, we must
927 insert a NOP. The R4650 has interlocks. */
929 && (mips_optimize
== 0
930 || (pinfo
& INSN_WRITE_HI
)))
934 /* There are two cases which require two intervening
935 instructions: 1) setting the condition codes using a move to
936 coprocessor instruction which requires a general coprocessor
937 delay and then reading the condition codes 2) reading the HI
938 or LO register and then writing to it (except on the R4650,
939 which has interlocks). If we are not already emitting a NOP
940 instruction, we must check for these cases compared to the
941 instruction previous to the previous instruction. */
943 && (((prev_prev_insn
.insn_mo
->pinfo
& INSN_COPROC_MOVE_DELAY
)
944 && (prev_prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
)
945 && (pinfo
& INSN_READ_COND_CODE
))
946 || ((prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
)
947 && (pinfo
& INSN_WRITE_LO
)
949 || ((prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
950 && (pinfo
& INSN_WRITE_HI
)
954 /* If we are being given a nop instruction, don't bother with
955 one of the nops we would otherwise output. This will only
956 happen when a nop instruction is used with mips_optimize set
958 if (nops
> 0 && ip
->insn_opcode
== 0)
961 /* Now emit the right number of NOP instructions. */
966 for (i
= 0; i
< nops
; i
++)
969 listing_prev_line ();
970 if (insn_label
!= NULL
)
972 assert (S_GET_SEGMENT (insn_label
) == now_seg
);
973 insn_label
->sy_frag
= frag_now
;
974 S_SET_VALUE (insn_label
, (valueT
) frag_now_fix ());
984 if (address_expr
!= NULL
)
986 if (address_expr
->X_op
== O_constant
)
991 ip
->insn_opcode
|= address_expr
->X_add_number
;
995 ip
->insn_opcode
|= address_expr
->X_add_number
& 0xffff;
998 case BFD_RELOC_MIPS_JMP
:
999 case BFD_RELOC_16_PCREL_S2
:
1008 assert (reloc_type
!= BFD_RELOC_UNUSED
);
1010 /* Don't generate a reloc if we are writing into a variant
1013 fixp
= fix_new_exp (frag_now
, f
- frag_now
->fr_literal
, 4,
1015 reloc_type
== BFD_RELOC_16_PCREL_S2
,
1020 md_number_to_chars (f
, ip
->insn_opcode
, 4);
1022 /* Update the register mask information. */
1023 if (pinfo
& INSN_WRITE_GPR_D
)
1024 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
);
1025 if ((pinfo
& (INSN_WRITE_GPR_T
| INSN_READ_GPR_T
)) != 0)
1026 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
);
1027 if (pinfo
& INSN_READ_GPR_S
)
1028 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> OP_SH_RS
) & OP_MASK_RS
);
1029 if (pinfo
& INSN_WRITE_GPR_31
)
1030 mips_gprmask
|= 1 << 31;
1031 if (pinfo
& INSN_WRITE_FPR_D
)
1032 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FD
) & OP_MASK_FD
);
1033 if ((pinfo
& (INSN_WRITE_FPR_S
| INSN_READ_FPR_S
)) != 0)
1034 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FS
) & OP_MASK_FS
);
1035 if ((pinfo
& (INSN_WRITE_FPR_T
| INSN_READ_FPR_T
)) != 0)
1036 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FT
) & OP_MASK_FT
);
1037 if (pinfo
& INSN_COP
)
1039 /* We don't keep enough information to sort these cases out. */
1041 /* Never set the bit for $0, which is always zero. */
1042 mips_gprmask
&=~ 1 << 0;
1044 if (place
== NULL
&& ! mips_noreorder
)
1046 /* Filling the branch delay slot is more complex. We try to
1047 switch the branch with the previous instruction, which we can
1048 do if the previous instruction does not set up a condition
1049 that the branch tests and if the branch is not itself the
1050 target of any branch. */
1051 if ((pinfo
& INSN_UNCOND_BRANCH_DELAY
)
1052 || (pinfo
& INSN_COND_BRANCH_DELAY
))
1054 if (mips_optimize
< 2
1055 /* If we have seen .set volatile or .set nomove, don't
1058 /* If we had to emit any NOP instructions, then we
1059 already know we can not swap. */
1061 /* If we don't even know the previous insn, we can not
1063 || ! prev_insn_valid
1064 /* If the previous insn is already in a branch delay
1065 slot, then we can not swap. */
1066 || prev_insn_is_delay_slot
1067 /* If the previous previous insn was in a .set
1068 noreorder, we can't swap. Actually, the MIPS
1069 assembler will swap in this situation. However, gcc
1070 configured -with-gnu-as will generate code like
1076 in which we can not swap the bne and INSN. If gcc is
1077 not configured -with-gnu-as, it does not output the
1078 .set pseudo-ops. We don't have to check
1079 prev_insn_unreordered, because prev_insn_valid will
1080 be 0 in that case. We don't want to use
1081 prev_prev_insn_valid, because we do want to be able
1082 to swap at the start of a function. */
1083 || prev_prev_insn_unreordered
1084 /* If the branch is itself the target of a branch, we
1085 can not swap. We cheat on this; all we check for is
1086 whether there is a label on this instruction. If
1087 there are any branches to anything other than a
1088 label, users must use .set noreorder. */
1089 || insn_label
!= NULL
1090 /* If the previous instruction is in a variant frag, we
1091 can not do the swap. */
1092 || prev_insn_frag
->fr_type
== rs_machine_dependent
1093 /* If the branch reads the condition codes, we don't
1094 even try to swap, because in the sequence
1099 we can not swap, and I don't feel like handling that
1101 || (pinfo
& INSN_READ_COND_CODE
)
1102 /* We can not swap with an instruction that requires a
1103 delay slot, becase the target of the branch might
1104 interfere with that instruction. */
1106 & (INSN_LOAD_COPROC_DELAY
1107 | INSN_COPROC_MOVE_DELAY
1108 | INSN_WRITE_COND_CODE
))
1115 & (INSN_LOAD_MEMORY_DELAY
1116 | INSN_COPROC_MEMORY_DELAY
)))
1117 /* We can not swap with a branch instruction. */
1119 & (INSN_UNCOND_BRANCH_DELAY
1120 | INSN_COND_BRANCH_DELAY
1121 | INSN_COND_BRANCH_LIKELY
))
1122 /* We do not swap with a trap instruction, since it
1123 complicates trap handlers to have the trap
1124 instruction be in a delay slot. */
1125 || (prev_pinfo
& INSN_TRAP
)
1126 /* If the branch reads a register that the previous
1127 instruction sets, we can not swap. */
1128 || ((prev_pinfo
& INSN_WRITE_GPR_T
)
1129 && insn_uses_reg (ip
,
1130 ((prev_insn
.insn_opcode
>> OP_SH_RT
)
1133 || ((prev_pinfo
& INSN_WRITE_GPR_D
)
1134 && insn_uses_reg (ip
,
1135 ((prev_insn
.insn_opcode
>> OP_SH_RD
)
1138 /* If the branch writes a register that the previous
1139 instruction sets, we can not swap (we know that
1140 branches write only to RD or to $31). */
1141 || ((prev_pinfo
& INSN_WRITE_GPR_T
)
1142 && (((pinfo
& INSN_WRITE_GPR_D
)
1143 && (((prev_insn
.insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
)
1144 == ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)))
1145 || ((pinfo
& INSN_WRITE_GPR_31
)
1146 && (((prev_insn
.insn_opcode
>> OP_SH_RT
)
1149 || ((prev_pinfo
& INSN_WRITE_GPR_D
)
1150 && (((pinfo
& INSN_WRITE_GPR_D
)
1151 && (((prev_insn
.insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)
1152 == ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)))
1153 || ((pinfo
& INSN_WRITE_GPR_31
)
1154 && (((prev_insn
.insn_opcode
>> OP_SH_RD
)
1157 /* If the branch writes a register that the previous
1158 instruction reads, we can not swap (we know that
1159 branches only write to RD or to $31). */
1160 || ((pinfo
& INSN_WRITE_GPR_D
)
1161 && insn_uses_reg (&prev_insn
,
1162 ((ip
->insn_opcode
>> OP_SH_RD
)
1165 || ((pinfo
& INSN_WRITE_GPR_31
)
1166 && insn_uses_reg (&prev_insn
, 31, 0))
1167 /* If we are generating embedded PIC code, the branch
1168 might be expanded into a sequence which uses $at, so
1169 we can't swap with an instruction which reads it. */
1170 || (mips_pic
== EMBEDDED_PIC
1171 && insn_uses_reg (&prev_insn
, AT
, 0))
1172 /* If the previous previous instruction has a load
1173 delay, and sets a register that the branch reads, we
1175 || (((prev_prev_insn
.insn_mo
->pinfo
& INSN_LOAD_COPROC_DELAY
)
1177 && (prev_prev_insn
.insn_mo
->pinfo
1178 & INSN_LOAD_MEMORY_DELAY
)))
1179 && insn_uses_reg (ip
,
1180 ((prev_prev_insn
.insn_opcode
>> OP_SH_RT
)
1184 /* We could do even better for unconditional branches to
1185 portions of this object file; we could pick up the
1186 instruction at the destination, put it in the delay
1187 slot, and bump the destination address. */
1189 /* Update the previous insn information. */
1190 prev_prev_insn
= *ip
;
1191 prev_insn
.insn_mo
= &dummy_opcode
;
1198 /* It looks like we can actually do the swap. */
1199 prev_f
= prev_insn_frag
->fr_literal
+ prev_insn_where
;
1200 memcpy (temp
, prev_f
, 4);
1201 memcpy (prev_f
, f
, 4);
1202 memcpy (f
, temp
, 4);
1205 prev_insn_fixp
->fx_frag
= frag_now
;
1206 prev_insn_fixp
->fx_where
= f
- frag_now
->fr_literal
;
1210 fixp
->fx_frag
= prev_insn_frag
;
1211 fixp
->fx_where
= prev_insn_where
;
1213 /* Update the previous insn information; leave prev_insn
1215 prev_prev_insn
= *ip
;
1217 prev_insn_is_delay_slot
= 1;
1219 /* If that was an unconditional branch, forget the previous
1220 insn information. */
1221 if (pinfo
& INSN_UNCOND_BRANCH_DELAY
)
1223 prev_prev_insn
.insn_mo
= &dummy_opcode
;
1224 prev_insn
.insn_mo
= &dummy_opcode
;
1227 else if (pinfo
& INSN_COND_BRANCH_LIKELY
)
1229 /* We don't yet optimize a branch likely. What we should do
1230 is look at the target, copy the instruction found there
1231 into the delay slot, and increment the branch to jump to
1232 the next instruction. */
1234 /* Update the previous insn information. */
1235 prev_prev_insn
= *ip
;
1236 prev_insn
.insn_mo
= &dummy_opcode
;
1240 /* Update the previous insn information. */
1242 prev_prev_insn
.insn_mo
= &dummy_opcode
;
1244 prev_prev_insn
= prev_insn
;
1247 /* Any time we see a branch, we always fill the delay slot
1248 immediately; since this insn is not a branch, we know it
1249 is not in a delay slot. */
1250 prev_insn_is_delay_slot
= 0;
1253 prev_prev_insn_unreordered
= prev_insn_unreordered
;
1254 prev_insn_unreordered
= 0;
1255 prev_insn_frag
= frag_now
;
1256 prev_insn_where
= f
- frag_now
->fr_literal
;
1257 prev_insn_fixp
= fixp
;
1258 prev_insn_valid
= 1;
1261 /* We just output an insn, so the next one doesn't have a label. */
1265 /* This function forgets that there was any previous instruction or
1269 mips_no_prev_insn ()
1271 prev_insn
.insn_mo
= &dummy_opcode
;
1272 prev_prev_insn
.insn_mo
= &dummy_opcode
;
1273 prev_insn_valid
= 0;
1274 prev_insn_is_delay_slot
= 0;
1275 prev_insn_unreordered
= 0;
1276 prev_prev_insn_unreordered
= 0;
1280 /* This function must be called whenever we turn on noreorder or emit
1281 something other than instructions. It inserts any NOPS which might
1282 be needed by the previous instruction, and clears the information
1283 kept for the previous instructions. */
1288 if (! mips_noreorder
)
1293 if ((prev_insn
.insn_mo
->pinfo
1294 & (INSN_LOAD_COPROC_DELAY
1295 | INSN_COPROC_MOVE_DELAY
1296 | INSN_WRITE_COND_CODE
))
1298 && (prev_insn
.insn_mo
->pinfo
1302 && (prev_insn
.insn_mo
->pinfo
1303 & (INSN_LOAD_MEMORY_DELAY
1304 | INSN_COPROC_MEMORY_DELAY
))))
1307 if ((prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
)
1309 && ((prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
1310 || (prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
))))
1313 else if ((prev_prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
)
1315 && ((prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
1316 || (prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
))))
1321 if (insn_label
!= NULL
)
1323 assert (S_GET_SEGMENT (insn_label
) == now_seg
);
1324 insn_label
->sy_frag
= frag_now
;
1325 S_SET_VALUE (insn_label
, (valueT
) frag_now_fix ());
1330 mips_no_prev_insn ();
1333 /* Build an instruction created by a macro expansion. This is passed
1334 a pointer to the count of instructions created so far, an
1335 expression, the name of the instruction to build, an operand format
1336 string, and corresponding arguments. */
1340 macro_build (char *place
,
1346 #else /* ! defined (NO_STDARG) */
1348 macro_build (place
, counter
, ep
, name
, fmt
, va_alist
)
1355 #endif /* ! defined (NO_STDARG) */
1357 struct mips_cl_insn insn
;
1358 bfd_reloc_code_real_type r
;
1362 va_start (args
, fmt
);
1368 * If the macro is about to expand into a second instruction,
1369 * print a warning if needed. We need to pass ip as a parameter
1370 * to generate a better warning message here...
1372 if (mips_warn_about_macros
&& place
== NULL
&& *counter
== 1)
1373 as_warn ("Macro instruction expanded into multiple instructions");
1376 *counter
+= 1; /* bump instruction counter */
1378 r
= BFD_RELOC_UNUSED
;
1379 insn
.insn_mo
= (struct mips_opcode
*) hash_find (op_hash
, name
);
1380 assert (insn
.insn_mo
);
1381 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
1383 while (strcmp (fmt
, insn
.insn_mo
->args
) != 0
1384 || insn
.insn_mo
->pinfo
== INSN_MACRO
)
1387 assert (insn
.insn_mo
->name
);
1388 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
1390 insn
.insn_opcode
= insn
.insn_mo
->match
;
1406 insn
.insn_opcode
|= va_arg (args
, int) << 16;
1412 insn
.insn_opcode
|= va_arg (args
, int) << 16;
1417 insn
.insn_opcode
|= va_arg (args
, int) << 11;
1422 insn
.insn_opcode
|= va_arg (args
, int) << 11;
1429 insn
.insn_opcode
|= va_arg (args
, int) << 6;
1433 insn
.insn_opcode
|= va_arg (args
, int) << 6;
1437 insn
.insn_opcode
|= va_arg (args
, int) << 6;
1444 insn
.insn_opcode
|= va_arg (args
, int) << 21;
1450 r
= (bfd_reloc_code_real_type
) va_arg (args
, int);
1451 assert (r
== BFD_RELOC_MIPS_GPREL
1452 || r
== BFD_RELOC_MIPS_LITERAL
1453 || r
== BFD_RELOC_LO16
1454 || r
== BFD_RELOC_MIPS_GOT16
1455 || r
== BFD_RELOC_MIPS_CALL16
1456 || (ep
->X_op
== O_subtract
1457 && now_seg
== text_section
1458 && r
== BFD_RELOC_PCREL_LO16
));
1462 r
= (bfd_reloc_code_real_type
) va_arg (args
, int);
1464 && (ep
->X_op
== O_constant
1465 || (ep
->X_op
== O_symbol
1466 && (r
== BFD_RELOC_HI16_S
1467 || r
== BFD_RELOC_HI16
))
1468 || (ep
->X_op
== O_subtract
1469 && now_seg
== text_section
1470 && r
== BFD_RELOC_PCREL_HI16_S
)));
1471 if (ep
->X_op
== O_constant
)
1473 insn
.insn_opcode
|= (ep
->X_add_number
>> 16) & 0xffff;
1475 r
= BFD_RELOC_UNUSED
;
1480 assert (ep
!= NULL
);
1482 * This allows macro() to pass an immediate expression for
1483 * creating short branches without creating a symbol.
1484 * Note that the expression still might come from the assembly
1485 * input, in which case the value is not checked for range nor
1486 * is a relocation entry generated (yuck).
1488 if (ep
->X_op
== O_constant
)
1490 insn
.insn_opcode
|= (ep
->X_add_number
>> 2) & 0xffff;
1494 r
= BFD_RELOC_16_PCREL_S2
;
1498 assert (ep
!= NULL
);
1499 r
= BFD_RELOC_MIPS_JMP
;
1508 assert (r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
1510 append_insn (place
, &insn
, ep
, r
);
1514 * Generate a "lui" instruction.
1517 macro_build_lui (place
, counter
, ep
, regnum
)
1523 expressionS high_expr
;
1524 struct mips_cl_insn insn
;
1525 bfd_reloc_code_real_type r
;
1526 CONST
char *name
= "lui";
1527 CONST
char *fmt
= "t,u";
1533 high_expr
.X_op
= O_constant
;
1534 high_expr
.X_add_number
= 0;
1537 if (high_expr
.X_op
== O_constant
)
1539 /* we can compute the instruction now without a relocation entry */
1540 if (high_expr
.X_add_number
& 0x8000)
1541 high_expr
.X_add_number
+= 0x10000;
1542 high_expr
.X_add_number
=
1543 ((unsigned long) high_expr
.X_add_number
>> 16) & 0xffff;
1544 r
= BFD_RELOC_UNUSED
;
1548 assert (ep
->X_op
== O_symbol
);
1549 /* _gp_disp is a special case, used from s_cpload. */
1550 assert (mips_pic
== NO_PIC
1551 || strcmp (S_GET_NAME (ep
->X_add_symbol
), "_gp_disp") == 0);
1552 r
= BFD_RELOC_HI16_S
;
1556 * If the macro is about to expand into a second instruction,
1557 * print a warning if needed. We need to pass ip as a parameter
1558 * to generate a better warning message here...
1560 if (mips_warn_about_macros
&& place
== NULL
&& *counter
== 1)
1561 as_warn ("Macro instruction expanded into multiple instructions");
1564 *counter
+= 1; /* bump instruction counter */
1566 insn
.insn_mo
= (struct mips_opcode
*) hash_find (op_hash
, name
);
1567 assert (insn
.insn_mo
);
1568 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
1569 assert (strcmp (fmt
, insn
.insn_mo
->args
) == 0);
1571 insn
.insn_opcode
= insn
.insn_mo
->match
| (regnum
<< OP_SH_RT
);
1572 if (r
== BFD_RELOC_UNUSED
)
1574 insn
.insn_opcode
|= high_expr
.X_add_number
;
1575 append_insn (place
, &insn
, NULL
, r
);
1578 append_insn (place
, &insn
, &high_expr
, r
);
1582 * Generates code to set the $at register to true (one)
1583 * if reg is less than the immediate expression.
1586 set_at (counter
, reg
, unsignedp
)
1591 if (imm_expr
.X_add_number
>= -0x8000 && imm_expr
.X_add_number
< 0x8000)
1592 macro_build ((char *) NULL
, counter
, &imm_expr
,
1593 unsignedp
? "sltiu" : "slti",
1594 "t,r,j", AT
, reg
, (int) BFD_RELOC_LO16
);
1597 load_register (counter
, AT
, &imm_expr
);
1598 macro_build ((char *) NULL
, counter
, NULL
,
1599 unsignedp
? "sltu" : "slt",
1600 "d,v,t", AT
, reg
, AT
);
1604 /* Warn if an expression is not a constant. */
1607 check_absolute_expr (ip
, ex
)
1608 struct mips_cl_insn
*ip
;
1611 if (ex
->X_op
!= O_constant
)
1612 as_warn ("Instruction %s requires absolute expression", ip
->insn_mo
->name
);
1616 * This routine generates the least number of instructions neccessary to load
1617 * an absolute expression value into a register.
1620 load_register (counter
, reg
, ep
)
1626 expressionS hi32
, lo32
;
1628 if (ep
->X_op
!= O_big
)
1630 assert (ep
->X_op
== O_constant
);
1631 if (ep
->X_add_number
>= -0x8000 && ep
->X_add_number
< 0x8000)
1633 /* We can handle 16 bit signed values with an addiu to
1634 $zero. No need to ever use daddiu here, since $zero and
1635 the result are always correct in 32 bit mode. */
1636 macro_build ((char *) NULL
, counter
, ep
, "addiu", "t,r,j", reg
, 0,
1637 (int) BFD_RELOC_LO16
);
1640 else if (ep
->X_add_number
>= 0 && ep
->X_add_number
< 0x10000)
1642 /* We can handle 16 bit unsigned values with an ori to
1644 macro_build ((char *) NULL
, counter
, ep
, "ori", "t,r,i", reg
, 0,
1645 (int) BFD_RELOC_LO16
);
1648 else if ((ep
->X_add_number
&~ (offsetT
) 0x7fffffff) == 0
1649 || ((ep
->X_add_number
&~ (offsetT
) 0x7fffffff)
1650 == ~ (offsetT
) 0x7fffffff))
1652 /* 32 bit values require an lui. */
1653 macro_build ((char *) NULL
, counter
, ep
, "lui", "t,u", reg
,
1654 (int) BFD_RELOC_HI16
);
1655 if ((ep
->X_add_number
& 0xffff) != 0)
1656 macro_build ((char *) NULL
, counter
, ep
, "ori", "t,r,i", reg
, reg
,
1657 (int) BFD_RELOC_LO16
);
1662 /* The value is larger than 32 bits. */
1666 as_bad ("Number larger than 32 bits");
1667 macro_build ((char *) NULL
, counter
, ep
, "addiu", "t,r,j", reg
, 0,
1668 (int) BFD_RELOC_LO16
);
1672 if (ep
->X_op
!= O_big
)
1676 hi32
.X_add_number
>>= shift
;
1677 hi32
.X_add_number
&= 0xffffffff;
1678 if ((hi32
.X_add_number
& 0x80000000) != 0)
1679 hi32
.X_add_number
|= ~ (offsetT
) 0xffffffff;
1681 lo32
.X_add_number
&= 0xffffffff;
1685 assert (ep
->X_add_number
> 2);
1686 if (ep
->X_add_number
== 3)
1687 generic_bignum
[3] = 0;
1688 else if (ep
->X_add_number
> 4)
1689 as_bad ("Number larger than 64 bits");
1690 lo32
.X_op
= O_constant
;
1691 lo32
.X_add_number
= generic_bignum
[0] + (generic_bignum
[1] << 16);
1692 hi32
.X_op
= O_constant
;
1693 hi32
.X_add_number
= generic_bignum
[2] + (generic_bignum
[3] << 16);
1696 load_register (counter
, reg
, &hi32
);
1697 if ((lo32
.X_add_number
& 0xffff0000) == 0)
1698 macro_build ((char *) NULL
, counter
, NULL
, "dsll32", "d,w,<", reg
,
1704 macro_build ((char *) NULL
, counter
, NULL
, "dsll", "d,w,<", reg
,
1707 mid16
.X_add_number
>>= 16;
1708 macro_build ((char *) NULL
, counter
, &mid16
, "ori", "t,r,i", reg
,
1709 reg
, (int) BFD_RELOC_LO16
);
1710 macro_build ((char *) NULL
, counter
, NULL
, "dsll", "d,w,<", reg
,
1713 if ((lo32
.X_add_number
& 0xffff) != 0)
1714 macro_build ((char *) NULL
, counter
, &lo32
, "ori", "t,r,i", reg
, reg
,
1715 (int) BFD_RELOC_LO16
);
1718 /* Load an address into a register. */
1721 load_address (counter
, reg
, ep
)
1728 if (ep
->X_op
!= O_constant
1729 && ep
->X_op
!= O_symbol
)
1731 as_bad ("expression too complex");
1732 ep
->X_op
= O_constant
;
1735 if (ep
->X_op
== O_constant
)
1737 load_register (counter
, reg
, ep
);
1741 if (mips_pic
== NO_PIC
)
1743 /* If this is a reference to a GP relative symbol, we want
1744 addiu $reg,$gp,<sym> (BFD_RELOC_MIPS_GPREL)
1746 lui $reg,<sym> (BFD_RELOC_HI16_S)
1747 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
1748 If we have an addend, we always use the latter form. */
1749 if (ep
->X_add_number
!= 0)
1754 macro_build ((char *) NULL
, counter
, ep
,
1755 mips_isa
< 3 ? "addiu" : "daddiu",
1756 "t,r,j", reg
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
1757 p
= frag_var (rs_machine_dependent
, 8, 0,
1758 RELAX_ENCODE (4, 8, 0, 4, 0, mips_warn_about_macros
),
1759 ep
->X_add_symbol
, (long) 0, (char *) NULL
);
1761 macro_build_lui (p
, counter
, ep
, reg
);
1764 macro_build (p
, counter
, ep
,
1765 mips_isa
< 3 ? "addiu" : "daddiu",
1766 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
1768 else if (mips_pic
== SVR4_PIC
)
1772 /* If this is a reference to an external symbol, we want
1773 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
1775 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
1777 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
1778 If there is a constant, it must be added in after. */
1779 ex
.X_add_number
= ep
->X_add_number
;
1780 ep
->X_add_number
= 0;
1782 macro_build ((char *) NULL
, counter
, ep
,
1783 mips_isa
< 3 ? "lw" : "ld",
1784 "t,o(b)", reg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
1785 macro_build ((char *) NULL
, counter
, (expressionS
*) NULL
, "nop", "");
1786 p
= frag_var (rs_machine_dependent
, 4, 0,
1787 RELAX_ENCODE (0, 4, -8, 0, 0, mips_warn_about_macros
),
1788 ep
->X_add_symbol
, (long) 0, (char *) NULL
);
1789 macro_build (p
, counter
, ep
,
1790 mips_isa
< 3 ? "addiu" : "daddiu",
1791 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
1792 if (ex
.X_add_number
!= 0)
1794 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
1795 as_bad ("PIC code offset overflow (max 16 signed bits)");
1796 ex
.X_op
= O_constant
;
1797 macro_build (p
, counter
, &ex
,
1798 mips_isa
< 3 ? "addiu" : "daddiu",
1799 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
1802 else if (mips_pic
== EMBEDDED_PIC
)
1805 addiu $reg,$gp,<sym> (BFD_RELOC_MIPS_GPREL)
1807 macro_build ((char *) NULL
, counter
, ep
,
1808 mips_isa
< 3 ? "addiu" : "daddiu",
1809 "t,r,j", reg
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
1817 * This routine implements the seemingly endless macro or synthesized
1818 * instructions and addressing modes in the mips assembly language. Many
1819 * of these macros are simple and are similar to each other. These could
1820 * probably be handled by some kind of table or grammer aproach instead of
1821 * this verbose method. Others are not simple macros but are more like
1822 * optimizing code generation.
1823 * One interesting optimization is when several store macros appear
1824 * consecutivly that would load AT with the upper half of the same address.
1825 * The ensuing load upper instructions are ommited. This implies some kind
1826 * of global optimization. We currently only optimize within a single macro.
1827 * For many of the load and store macros if the address is specified as a
1828 * constant expression in the first 64k of memory (ie ld $2,0x4000c) we
1829 * first load register 'at' with zero and use it as the base register. The
1830 * mips assembler simply uses register $zero. Just one tiny optimization
1835 struct mips_cl_insn
*ip
;
1837 register int treg
, sreg
, dreg
, breg
;
1852 bfd_reloc_code_real_type r
;
1854 int hold_mips_optimize
;
1856 treg
= (ip
->insn_opcode
>> 16) & 0x1f;
1857 dreg
= (ip
->insn_opcode
>> 11) & 0x1f;
1858 sreg
= breg
= (ip
->insn_opcode
>> 21) & 0x1f;
1859 mask
= ip
->insn_mo
->mask
;
1861 expr1
.X_op
= O_constant
;
1862 expr1
.X_op_symbol
= NULL
;
1863 expr1
.X_add_symbol
= NULL
;
1864 expr1
.X_add_number
= 1;
1876 mips_emit_delays ();
1878 mips_any_noreorder
= 1;
1880 expr1
.X_add_number
= 8;
1881 macro_build ((char *) NULL
, &icnt
, &expr1
, "bgez", "s,p", sreg
);
1883 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
1885 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
, sreg
, 0);
1886 macro_build ((char *) NULL
, &icnt
, NULL
,
1887 dbl
? "dsub" : "sub",
1888 "d,v,t", dreg
, 0, sreg
);
1911 if (imm_expr
.X_add_number
>= -0x8000 && imm_expr
.X_add_number
< 0x8000)
1913 macro_build ((char *) NULL
, &icnt
, &imm_expr
, s
, "t,r,j", treg
, sreg
,
1914 (int) BFD_RELOC_LO16
);
1917 load_register (&icnt
, AT
, &imm_expr
);
1918 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "d,v,t", treg
, sreg
, AT
);
1937 if (imm_expr
.X_add_number
>= 0 && imm_expr
.X_add_number
< 0x10000)
1939 if (mask
!= M_NOR_I
)
1940 macro_build ((char *) NULL
, &icnt
, &imm_expr
, s
, "t,r,i", treg
,
1941 sreg
, (int) BFD_RELOC_LO16
);
1944 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "ori", "t,r,i",
1945 treg
, sreg
, (int) BFD_RELOC_LO16
);
1946 macro_build ((char *) NULL
, &icnt
, NULL
, "nor", "d,v,t",
1952 load_register (&icnt
, AT
, &imm_expr
);
1953 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "d,v,t", treg
, sreg
, AT
);
1970 if (imm_expr
.X_add_number
== 0)
1972 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "s,t,p", sreg
,
1976 load_register (&icnt
, AT
, &imm_expr
);
1977 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "s,t,p", sreg
, AT
);
1985 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
1986 likely
? "bgezl" : "bgez",
1992 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
1993 likely
? "blezl" : "blez",
1997 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", AT
, sreg
, treg
);
1998 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
1999 likely
? "beql" : "beq",
2006 /* check for > max integer */
2007 maxnum
= 0x7fffffff;
2015 if (imm_expr
.X_add_number
>= maxnum
2016 && (mips_isa
< 3 || sizeof (maxnum
) > 4))
2019 /* result is always false */
2022 as_warn ("Branch %s is always false (nop)", ip
->insn_mo
->name
);
2023 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
2027 as_warn ("Branch likely %s is always false", ip
->insn_mo
->name
);
2028 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "bnel",
2033 imm_expr
.X_add_number
++;
2037 if (mask
== M_BGEL_I
)
2039 if (imm_expr
.X_add_number
== 0)
2041 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2042 likely
? "bgezl" : "bgez",
2046 if (imm_expr
.X_add_number
== 1)
2048 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2049 likely
? "bgtzl" : "bgtz",
2053 maxnum
= 0x7fffffff;
2061 maxnum
= - maxnum
- 1;
2062 if (imm_expr
.X_add_number
<= maxnum
2063 && (mips_isa
< 3 || sizeof (maxnum
) > 4))
2066 /* result is always true */
2067 as_warn ("Branch %s is always true", ip
->insn_mo
->name
);
2068 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "b", "p");
2071 set_at (&icnt
, sreg
, 0);
2072 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2073 likely
? "beql" : "beq",
2084 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2085 likely
? "beql" : "beq",
2089 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", AT
, sreg
,
2091 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2092 likely
? "beql" : "beq",
2099 if (sreg
== 0 || imm_expr
.X_add_number
== -1)
2101 imm_expr
.X_add_number
++;
2105 if (mask
== M_BGEUL_I
)
2107 if (imm_expr
.X_add_number
== 0)
2109 if (imm_expr
.X_add_number
== 1)
2111 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2112 likely
? "bnel" : "bne",
2116 set_at (&icnt
, sreg
, 1);
2117 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2118 likely
? "beql" : "beq",
2127 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2128 likely
? "bgtzl" : "bgtz",
2134 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2135 likely
? "bltzl" : "bltz",
2139 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", AT
, treg
, sreg
);
2140 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2141 likely
? "bnel" : "bne",
2150 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2151 likely
? "bnel" : "bne",
2157 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", AT
, treg
,
2159 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2160 likely
? "bnel" : "bne",
2169 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2170 likely
? "blezl" : "blez",
2176 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2177 likely
? "bgezl" : "bgez",
2181 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", AT
, treg
, sreg
);
2182 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2183 likely
? "beql" : "beq",
2190 maxnum
= 0x7fffffff;
2198 if (imm_expr
.X_add_number
>= maxnum
2199 && (mips_isa
< 3 || sizeof (maxnum
) > 4))
2201 imm_expr
.X_add_number
++;
2205 if (mask
== M_BLTL_I
)
2207 if (imm_expr
.X_add_number
== 0)
2209 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2210 likely
? "bltzl" : "bltz",
2214 if (imm_expr
.X_add_number
== 1)
2216 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2217 likely
? "blezl" : "blez",
2221 set_at (&icnt
, sreg
, 0);
2222 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2223 likely
? "bnel" : "bne",
2232 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2233 likely
? "beql" : "beq",
2239 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", AT
, treg
,
2241 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2242 likely
? "beql" : "beq",
2249 if (sreg
== 0 || imm_expr
.X_add_number
== -1)
2251 imm_expr
.X_add_number
++;
2255 if (mask
== M_BLTUL_I
)
2257 if (imm_expr
.X_add_number
== 0)
2259 if (imm_expr
.X_add_number
== 1)
2261 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2262 likely
? "beql" : "beq",
2266 set_at (&icnt
, sreg
, 1);
2267 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2268 likely
? "bnel" : "bne",
2277 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2278 likely
? "bltzl" : "bltz",
2284 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2285 likely
? "bgtzl" : "bgtz",
2289 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", AT
, sreg
, treg
);
2290 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2291 likely
? "bnel" : "bne",
2302 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2303 likely
? "bnel" : "bne",
2307 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", AT
, sreg
,
2309 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2310 likely
? "bnel" : "bne",
2326 as_warn ("Divide by zero.");
2328 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", 0, 0);
2330 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 7);
2334 mips_emit_delays ();
2336 mips_any_noreorder
= 1;
2337 macro_build ((char *) NULL
, &icnt
, NULL
,
2338 dbl
? "ddiv" : "div",
2339 "z,s,t", sreg
, treg
);
2341 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", treg
, 0);
2344 expr1
.X_add_number
= 8;
2345 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", treg
, 0);
2346 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
2347 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 7);
2349 expr1
.X_add_number
= -1;
2350 macro_build ((char *) NULL
, &icnt
, &expr1
,
2351 dbl
? "daddiu" : "addiu",
2352 "t,r,j", AT
, 0, (int) BFD_RELOC_LO16
);
2353 expr1
.X_add_number
= mips_trap
? (dbl
? 12 : 8) : (dbl
? 20 : 16);
2354 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", treg
, AT
);
2357 expr1
.X_add_number
= 1;
2358 macro_build ((char *) NULL
, &icnt
, &expr1
, "daddiu", "t,r,j", AT
, 0,
2359 (int) BFD_RELOC_LO16
);
2360 macro_build ((char *) NULL
, &icnt
, NULL
, "dsll32", "d,w,<", AT
, AT
,
2365 expr1
.X_add_number
= 0x80000000;
2366 macro_build ((char *) NULL
, &icnt
, &expr1
, "lui", "t,u", AT
,
2367 (int) BFD_RELOC_HI16
);
2370 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", sreg
, AT
);
2373 expr1
.X_add_number
= 8;
2374 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", sreg
, AT
);
2375 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
2376 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 6);
2379 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d", dreg
);
2418 if (imm_expr
.X_add_number
== 0)
2420 as_warn ("Divide by zero.");
2422 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", 0, 0);
2424 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 7);
2427 if (imm_expr
.X_add_number
== 1)
2429 if (strcmp (s2
, "mflo") == 0)
2430 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
,
2433 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
, 0);
2436 if (imm_expr
.X_add_number
== -1
2437 && s
[strlen (s
) - 1] != 'u')
2439 if (strcmp (s2
, "mflo") == 0)
2442 macro_build ((char *) NULL
, &icnt
, NULL
, "dneg", "d,w", dreg
,
2445 macro_build ((char *) NULL
, &icnt
, NULL
, "neg", "d,w", dreg
,
2449 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
, 0);
2453 load_register (&icnt
, AT
, &imm_expr
);
2454 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "z,s,t", sreg
, AT
);
2455 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "d", dreg
);
2474 mips_emit_delays ();
2476 mips_any_noreorder
= 1;
2477 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "z,s,t", sreg
, treg
);
2479 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", treg
, 0);
2482 expr1
.X_add_number
= 8;
2483 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", treg
, 0);
2484 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
2485 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 7);
2488 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "d", dreg
);
2492 /* Load the address of a symbol into a register. If breg is not
2493 zero, we then add a base register to it. */
2495 /* When generating embedded PIC code, we permit expressions of
2498 where bar is an address in the .text section. These are used
2499 when getting the addresses of functions. We don't permit
2500 X_add_number to be non-zero, because if the symbol is
2501 external the relaxing code needs to know that any addend is
2502 purely the offset to X_op_symbol. */
2503 if (mips_pic
== EMBEDDED_PIC
2504 && offset_expr
.X_op
== O_subtract
2505 && now_seg
== text_section
2506 && (offset_expr
.X_op_symbol
->sy_value
.X_op
== O_constant
2507 ? S_GET_SEGMENT (offset_expr
.X_op_symbol
) == text_section
2508 : (offset_expr
.X_op_symbol
->sy_value
.X_op
== O_symbol
2509 && (S_GET_SEGMENT (offset_expr
.X_op_symbol
2510 ->sy_value
.X_add_symbol
)
2513 && offset_expr
.X_add_number
== 0)
2515 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
2516 treg
, (int) BFD_RELOC_PCREL_HI16_S
);
2517 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2518 mips_isa
< 3 ? "addiu" : "daddiu",
2519 "t,r,j", treg
, treg
, (int) BFD_RELOC_PCREL_LO16
);
2523 if (offset_expr
.X_op
!= O_symbol
2524 && offset_expr
.X_op
!= O_constant
)
2526 as_bad ("expression too complex");
2527 offset_expr
.X_op
= O_constant
;
2541 if (offset_expr
.X_op
== O_constant
)
2542 load_register (&icnt
, tempreg
, &offset_expr
);
2543 else if (mips_pic
== NO_PIC
)
2545 /* If this is a reference to an GP relative symbol, we want
2546 addiu $tempreg,$gp,<sym> (BFD_RELOC_MIPS_GPREL)
2548 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
2549 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
2550 If we have a constant, we need two instructions anyhow,
2551 so we may as well always use the latter form. */
2552 if (offset_expr
.X_add_number
!= 0)
2557 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2558 mips_isa
< 3 ? "addiu" : "daddiu",
2559 "t,r,j", tempreg
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
2560 p
= frag_var (rs_machine_dependent
, 8, 0,
2561 RELAX_ENCODE (4, 8, 0, 4, 0,
2562 mips_warn_about_macros
),
2563 offset_expr
.X_add_symbol
, (long) 0,
2566 macro_build_lui (p
, &icnt
, &offset_expr
, tempreg
);
2569 macro_build (p
, &icnt
, &offset_expr
,
2570 mips_isa
< 3 ? "addiu" : "daddiu",
2571 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
2573 else if (mips_pic
== SVR4_PIC
)
2575 /* If this is a reference to an external symbol, and there
2576 is no constant, we want
2577 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
2578 For a local symbol, we want
2579 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
2581 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
2583 If we have a small constant, and this is a reference to
2584 an external symbol, we want
2585 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
2587 addiu $tempreg,$tempreg,<constant>
2588 For a local symbol, we want the same instruction
2589 sequence, but we output a BFD_RELOC_LO16 reloc on the
2592 If we have a large constant, and this is a reference to
2593 an external symbol, we want
2594 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
2595 lui $at,<hiconstant>
2596 addiu $at,$at,<loconstant>
2597 addu $tempreg,$tempreg,$at
2598 For a local symbol, we want the same instruction
2599 sequence, but we output a BFD_RELOC_LO16 reloc on the
2600 addiu instruction. */
2601 expr1
.X_add_number
= offset_expr
.X_add_number
;
2602 offset_expr
.X_add_number
= 0;
2604 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2605 mips_isa
< 3 ? "lw" : "ld",
2606 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
2607 if (expr1
.X_add_number
== 0)
2615 /* We're going to put in an addu instruction using
2616 tempreg, so we may as well insert the nop right
2618 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
2622 p
= frag_var (rs_machine_dependent
, 8 - off
, 0,
2623 RELAX_ENCODE (0, 8 - off
, -4 - off
, 4 - off
, 0,
2625 ? mips_warn_about_macros
2627 offset_expr
.X_add_symbol
, (long) 0,
2631 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
2634 macro_build (p
, &icnt
, &expr1
,
2635 mips_isa
< 3 ? "addiu" : "daddiu",
2636 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
2637 /* FIXME: If breg == 0, and the next instruction uses
2638 $tempreg, then if this variant case is used an extra
2639 nop will be generated. */
2641 else if (expr1
.X_add_number
>= -0x8000
2642 && expr1
.X_add_number
< 0x8000)
2644 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
2646 macro_build ((char *) NULL
, &icnt
, &expr1
,
2647 mips_isa
< 3 ? "addiu" : "daddiu",
2648 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
2649 (void) frag_var (rs_machine_dependent
, 0, 0,
2650 RELAX_ENCODE (0, 0, -12, -4, 0, 0),
2651 offset_expr
.X_add_symbol
, (long) 0,
2658 /* If we are going to add in a base register, and the
2659 target register and the base register are the same,
2660 then we are using AT as a temporary register. Since
2661 we want to load the constant into AT, we add our
2662 current AT (from the global offset table) and the
2663 register into the register now, and pretend we were
2664 not using a base register. */
2669 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
2671 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
2672 mips_isa
< 3 ? "addu" : "daddu",
2673 "d,v,t", treg
, AT
, breg
);
2679 /* Set mips_optimize around the lui instruction to avoid
2680 inserting an unnecessary nop after the lw. */
2681 hold_mips_optimize
= mips_optimize
;
2683 macro_build_lui ((char *) NULL
, &icnt
, &expr1
, AT
);
2684 mips_optimize
= hold_mips_optimize
;
2686 macro_build ((char *) NULL
, &icnt
, &expr1
,
2687 mips_isa
< 3 ? "addiu" : "daddiu",
2688 "t,r,j", AT
, AT
, (int) BFD_RELOC_LO16
);
2689 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
2690 mips_isa
< 3 ? "addu" : "daddu",
2691 "d,v,t", tempreg
, tempreg
, AT
);
2692 (void) frag_var (rs_machine_dependent
, 0, 0,
2693 RELAX_ENCODE (0, 0, -16 + off1
, -8, 0, 0),
2694 offset_expr
.X_add_symbol
, (long) 0,
2699 else if (mips_pic
== EMBEDDED_PIC
)
2702 addiu $tempreg,$gp,<sym> (BFD_RELOC_MIPS_GPREL)
2704 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2705 mips_isa
< 3 ? "addiu" : "daddiu",
2706 "t,r,j", tempreg
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
2712 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
2713 mips_isa
< 3 ? "addu" : "daddu",
2714 "d,v,t", treg
, tempreg
, breg
);
2722 /* The j instruction may not be used in PIC code, since it
2723 requires an absolute address. We convert it to a b
2725 if (mips_pic
== NO_PIC
)
2726 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "j", "a");
2728 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "b", "p");
2731 /* The jal instructions must be handled as macros because when
2732 generating PIC code they expand to multi-instruction
2733 sequences. Normally they are simple instructions. */
2738 if (mips_pic
== NO_PIC
2739 || mips_pic
== EMBEDDED_PIC
)
2740 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "jalr",
2742 else if (mips_pic
== SVR4_PIC
)
2744 if (sreg
!= PIC_CALL_REG
)
2745 as_warn ("MIPS PIC call to register other than $25");
2747 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "jalr",
2749 if (mips_cprestore_offset
< 0)
2750 as_warn ("No .cprestore pseudo-op used in PIC code");
2753 expr1
.X_add_number
= mips_cprestore_offset
;
2754 macro_build ((char *) NULL
, &icnt
, &expr1
,
2755 mips_isa
< 3 ? "lw" : "ld",
2756 "t,o(b)", GP
, (int) BFD_RELOC_LO16
, mips_frame_reg
);
2765 if (mips_pic
== NO_PIC
)
2766 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "jal", "a");
2767 else if (mips_pic
== SVR4_PIC
)
2769 /* If this is a reference to an external symbol, we want
2770 lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
2774 lw $gp,cprestore($sp)
2775 The cprestore value is set using the .cprestore
2776 pseudo-op. If the symbol is not external, we want
2777 lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
2779 addiu $25,$25,<sym> (BFD_RELOC_LO16)
2782 lw $gp,cprestore($sp)
2785 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2786 mips_isa
< 3 ? "lw" : "ld",
2787 "t,o(b)", PIC_CALL_REG
,
2788 (int) BFD_RELOC_MIPS_CALL16
, GP
);
2789 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
2790 p
= frag_var (rs_machine_dependent
, 4, 0,
2791 RELAX_ENCODE (0, 4, -8, 0, 0, 0),
2792 offset_expr
.X_add_symbol
, (long) 0, (char *) NULL
);
2793 macro_build (p
, &icnt
, &offset_expr
,
2794 mips_isa
< 3 ? "addiu" : "daddiu",
2795 "t,r,j", PIC_CALL_REG
, PIC_CALL_REG
,
2796 (int) BFD_RELOC_LO16
);
2797 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
2798 "jalr", "s", PIC_CALL_REG
);
2799 if (mips_cprestore_offset
< 0)
2800 as_warn ("No .cprestore pseudo-op used in PIC code");
2804 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
2806 expr1
.X_add_number
= mips_cprestore_offset
;
2807 macro_build ((char *) NULL
, &icnt
, &expr1
,
2808 mips_isa
< 3 ? "lw" : "ld",
2809 "t,o(b)", GP
, (int) BFD_RELOC_LO16
,
2813 else if (mips_pic
== EMBEDDED_PIC
)
2815 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "bal", "p");
2816 /* The linker may expand the call to a longer sequence which
2817 uses $at, so we must break rather than return. */
2893 if (breg
== treg
|| coproc
|| lr
)
2962 if (mask
== M_LWC1_AB
2963 || mask
== M_SWC1_AB
2964 || mask
== M_LDC1_AB
2965 || mask
== M_SDC1_AB
2974 if (offset_expr
.X_op
!= O_constant
2975 && offset_expr
.X_op
!= O_symbol
)
2977 as_bad ("expression too complex");
2978 offset_expr
.X_op
= O_constant
;
2981 /* A constant expression in PIC code can be handled just as it
2982 is in non PIC code. */
2983 if (mips_pic
== NO_PIC
2984 || offset_expr
.X_op
== O_constant
)
2986 /* If this is a reference to a GP relative symbol, and there
2987 is no base register, we want
2988 <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL)
2989 Otherwise, if there is no base register, we want
2990 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
2991 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
2992 If we have a constant, we need two instructions anyhow,
2993 so we always use the latter form.
2995 If we have a base register, and this is a reference to a
2996 GP relative symbol, we want
2997 addu $tempreg,$breg,$gp
2998 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GPREL)
3000 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
3001 addu $tempreg,$tempreg,$breg
3002 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
3003 With a constant we always use the latter case. */
3006 if (offset_expr
.X_add_number
!= 0)
3011 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
3012 treg
, (int) BFD_RELOC_MIPS_GPREL
, GP
);
3013 p
= frag_var (rs_machine_dependent
, 8, 0,
3014 RELAX_ENCODE (4, 8, 0, 4, 0,
3015 (mips_warn_about_macros
3016 || (used_at
&& mips_noat
))),
3017 offset_expr
.X_add_symbol
, (long) 0,
3021 macro_build_lui (p
, &icnt
, &offset_expr
, tempreg
);
3024 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
, treg
,
3025 (int) BFD_RELOC_LO16
, tempreg
);
3029 if (offset_expr
.X_add_number
!= 0)
3034 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3035 mips_isa
< 3 ? "addu" : "daddu",
3036 "d,v,t", tempreg
, breg
, GP
);
3037 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
3038 treg
, (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
3039 p
= frag_var (rs_machine_dependent
, 12, 0,
3040 RELAX_ENCODE (8, 12, 0, 8, 0, 0),
3041 offset_expr
.X_add_symbol
, (long) 0,
3044 macro_build_lui (p
, &icnt
, &offset_expr
, tempreg
);
3047 macro_build (p
, &icnt
, (expressionS
*) NULL
,
3048 mips_isa
< 3 ? "addu" : "daddu",
3049 "d,v,t", tempreg
, tempreg
, breg
);
3052 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
, treg
,
3053 (int) BFD_RELOC_LO16
, tempreg
);
3056 else if (mips_pic
== SVR4_PIC
)
3058 /* If this is a reference to an external symbol, we want
3059 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3061 <op> $treg,0($tempreg)
3063 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3065 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
3066 <op> $treg,0($tempreg)
3067 If there is a base register, we add it to $tempreg before
3068 the <op>. If there is a constant, we stick it in the
3069 <op> instruction. We don't handle constants larger than
3070 16 bits, because we have no way to load the upper 16 bits
3071 (actually, we could handle them for the subset of cases
3072 in which we are not using $at). */
3073 assert (offset_expr
.X_op
== O_symbol
);
3074 expr1
.X_add_number
= offset_expr
.X_add_number
;
3075 offset_expr
.X_add_number
= 0;
3076 if (expr1
.X_add_number
< -0x8000
3077 || expr1
.X_add_number
>= 0x8000)
3078 as_bad ("PIC code offset overflow (max 16 signed bits)");
3080 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3081 mips_isa
< 3 ? "lw" : "ld",
3082 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
3083 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
3084 p
= frag_var (rs_machine_dependent
, 4, 0,
3085 RELAX_ENCODE (0, 4, -8, 0, 0, 0),
3086 offset_expr
.X_add_symbol
, (long) 0,
3088 macro_build (p
, &icnt
, &offset_expr
,
3089 mips_isa
< 3 ? "addiu" : "daddiu",
3090 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
3092 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3093 mips_isa
< 3 ? "addu" : "daddu",
3094 "d,v,t", tempreg
, tempreg
, breg
);
3095 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
, treg
,
3096 (int) BFD_RELOC_LO16
, tempreg
);
3098 else if (mips_pic
== EMBEDDED_PIC
)
3100 /* If there is no base register, we want
3101 <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL)
3102 If there is a base register, we want
3103 addu $tempreg,$breg,$gp
3104 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GPREL)
3106 assert (offset_expr
.X_op
== O_symbol
);
3109 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
3110 treg
, (int) BFD_RELOC_MIPS_GPREL
, GP
);
3115 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3116 mips_isa
< 3 ? "addu" : "daddu",
3117 "d,v,t", tempreg
, breg
, GP
);
3118 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
3119 treg
, (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
3132 load_register (&icnt
, treg
, &imm_expr
);
3136 if (imm_expr
.X_op
== O_constant
)
3138 load_register (&icnt
, AT
, &imm_expr
);
3139 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3140 "mtc1", "t,G", AT
, treg
);
3145 assert (offset_expr
.X_op
== O_symbol
3146 && strcmp (segment_name (S_GET_SEGMENT
3147 (offset_expr
.X_add_symbol
)),
3149 && offset_expr
.X_add_number
== 0);
3150 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lwc1", "T,o(b)",
3151 treg
, (int) BFD_RELOC_MIPS_LITERAL
, GP
);
3156 /* We know that sym is in the .rdata section. First we get the
3157 upper 16 bits of the address. */
3158 if (mips_pic
== NO_PIC
)
3160 /* FIXME: This won't work for a 64 bit address. */
3161 macro_build_lui ((char *) NULL
, &icnt
, &offset_expr
, AT
);
3163 else if (mips_pic
== SVR4_PIC
)
3165 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3166 mips_isa
< 3 ? "lw" : "ld",
3167 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
3169 else if (mips_pic
== EMBEDDED_PIC
)
3171 /* For embedded PIC we pick up the entire address off $gp in
3172 a single instruction. */
3173 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3174 mips_isa
< 3 ? "addiu" : "daddiu",
3175 "t,r,j", AT
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
3176 offset_expr
.X_op
= O_constant
;
3177 offset_expr
.X_add_number
= 0;
3182 /* Now we load the register(s). */
3184 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "ld", "t,o(b)",
3185 treg
, (int) BFD_RELOC_LO16
, AT
);
3188 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lw", "t,o(b)",
3189 treg
, (int) BFD_RELOC_LO16
, AT
);
3192 /* FIXME: How in the world do we deal with the possible
3194 offset_expr
.X_add_number
+= 4;
3195 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lw", "t,o(b)",
3196 treg
+ 1, (int) BFD_RELOC_LO16
, AT
);
3200 /* To avoid confusion in tc_gen_reloc, we must ensure that this
3201 does not become a variant frag. */
3202 frag_wane (frag_now
);
3208 assert (offset_expr
.X_op
== O_symbol
3209 && offset_expr
.X_add_number
== 0);
3210 s
= segment_name (S_GET_SEGMENT (offset_expr
.X_add_symbol
));
3211 if (strcmp (s
, ".lit8") == 0)
3215 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "ldc1",
3216 "T,o(b)", treg
, (int) BFD_RELOC_MIPS_LITERAL
, GP
);
3220 r
= BFD_RELOC_MIPS_LITERAL
;
3225 assert (strcmp (s
, RDATA_SECTION_NAME
) == 0);
3226 if (mips_pic
== SVR4_PIC
)
3227 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3228 mips_isa
< 3 ? "lw" : "ld",
3229 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
3232 /* FIXME: This won't work for a 64 bit address. */
3233 macro_build_lui ((char *) NULL
, &icnt
, &offset_expr
, AT
);
3238 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "ldc1",
3239 "T,o(b)", treg
, (int) BFD_RELOC_LO16
, AT
);
3241 /* To avoid confusion in tc_gen_reloc, we must ensure
3242 that this does not become a variant frag. */
3243 frag_wane (frag_now
);
3254 /* Even on a big endian machine $fn comes before $fn+1. We have
3255 to adjust when loading from memory. */
3258 assert (mips_isa
< 2);
3259 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lwc1", "T,o(b)",
3260 byte_order
== LITTLE_ENDIAN
? treg
: treg
+ 1,
3262 /* FIXME: A possible overflow which I don't know how to deal
3264 offset_expr
.X_add_number
+= 4;
3265 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lwc1", "T,o(b)",
3266 byte_order
== LITTLE_ENDIAN
? treg
+ 1 : treg
,
3269 /* To avoid confusion in tc_gen_reloc, we must ensure that this
3270 does not become a variant frag. */
3271 frag_wane (frag_now
);
3280 * The MIPS assembler seems to check for X_add_number not
3281 * being double aligned and generating:
3284 * addiu at,at,%lo(foo+1)
3287 * But, the resulting address is the same after relocation so why
3288 * generate the extra instruction?
3335 if (offset_expr
.X_op
!= O_symbol
3336 && offset_expr
.X_op
!= O_constant
)
3338 as_bad ("expression too complex");
3339 offset_expr
.X_op
= O_constant
;
3342 /* Even on a big endian machine $fn comes before $fn+1. We have
3343 to adjust when loading from memory. We set coproc if we must
3344 load $fn+1 first. */
3345 if (byte_order
== LITTLE_ENDIAN
)
3348 if (mips_pic
== NO_PIC
3349 || offset_expr
.X_op
== O_constant
)
3351 /* If this is a reference to a GP relative symbol, we want
3352 <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL)
3353 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_MIPS_GPREL)
3354 If we have a base register, we use this
3356 <op> $treg,<sym>($at) (BFD_RELOC_MIPS_GPREL)
3357 <op> $treg+1,<sym>+4($at) (BFD_RELOC_MIPS_GPREL)
3358 If this is not a GP relative symbol, we want
3359 lui $at,<sym> (BFD_RELOC_HI16_S)
3360 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
3361 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
3362 If there is a base register, we add it to $at after the
3363 lui instruction. If there is a constant, we always use
3365 if (offset_expr
.X_add_number
!= 0)
3384 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3385 mips_isa
< 3 ? "addu" : "daddu",
3386 "d,v,t", AT
, breg
, GP
);
3392 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
3393 coproc
? treg
+ 1 : treg
,
3394 (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
3395 offset_expr
.X_add_number
+= 4;
3397 /* Set mips_optimize to 2 to avoid inserting an
3399 hold_mips_optimize
= mips_optimize
;
3401 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
3402 coproc
? treg
: treg
+ 1,
3403 (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
3404 mips_optimize
= hold_mips_optimize
;
3406 p
= frag_var (rs_machine_dependent
, 12 + off
, 0,
3407 RELAX_ENCODE (8 + off
, 12 + off
, 0, 4 + off
, 1,
3408 used_at
&& mips_noat
),
3409 offset_expr
.X_add_symbol
, (long) 0,
3412 /* We just generated two relocs. When tc_gen_reloc
3413 handles this case, it will skip the first reloc and
3414 handle the second. The second reloc already has an
3415 extra addend of 4, which we added above. We must
3416 subtract it out, and then subtract another 4 to make
3417 the first reloc come out right. The second reloc
3418 will come out right because we are going to add 4 to
3419 offset_expr when we build its instruction below. */
3420 offset_expr
.X_add_number
-= 8;
3421 offset_expr
.X_op
= O_constant
;
3423 macro_build_lui (p
, &icnt
, &offset_expr
, AT
);
3428 macro_build (p
, &icnt
, (expressionS
*) NULL
,
3429 mips_isa
< 3 ? "addu" : "daddu",
3430 "d,v,t", AT
, breg
, AT
);
3434 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
,
3435 coproc
? treg
+ 1 : treg
,
3436 (int) BFD_RELOC_LO16
, AT
);
3439 /* FIXME: How do we handle overflow here? */
3440 offset_expr
.X_add_number
+= 4;
3441 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
,
3442 coproc
? treg
: treg
+ 1,
3443 (int) BFD_RELOC_LO16
, AT
);
3445 else if (mips_pic
== SVR4_PIC
)
3449 /* If this is a reference to an external symbol, we want
3450 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3455 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3457 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
3458 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
3459 If there is a base register we add it to $at before the
3460 lwc1 instructions. If there is a constant we include it
3461 in the lwc1 instructions. */
3463 expr1
.X_add_number
= offset_expr
.X_add_number
;
3464 offset_expr
.X_add_number
= 0;
3465 if (expr1
.X_add_number
< -0x8000
3466 || expr1
.X_add_number
>= 0x8000 - 4)
3467 as_bad ("PIC code offset overflow (max 16 signed bits)");
3472 frag_grow (24 + off
);
3473 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3474 mips_isa
< 3 ? "lw" : "ld",
3475 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
3476 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
3478 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3479 mips_isa
< 3 ? "addu" : "daddu",
3480 "d,v,t", AT
, breg
, AT
);
3481 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
3482 coproc
? treg
+ 1 : treg
,
3483 (int) BFD_RELOC_LO16
, AT
);
3484 expr1
.X_add_number
+= 4;
3486 /* Set mips_optimize to 2 to avoid inserting an undesired
3488 hold_mips_optimize
= mips_optimize
;
3490 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
3491 coproc
? treg
: treg
+ 1,
3492 (int) BFD_RELOC_LO16
, AT
);
3493 mips_optimize
= hold_mips_optimize
;
3495 (void) frag_var (rs_machine_dependent
, 0, 0,
3496 RELAX_ENCODE (0, 0, -16 - off
, -8, 1, 0),
3497 offset_expr
.X_add_symbol
, (long) 0,
3500 else if (mips_pic
== EMBEDDED_PIC
)
3502 /* If there is no base register, we use
3503 <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL)
3504 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_MIPS_GPREL)
3505 If we have a base register, we use
3507 <op> $treg,<sym>($at) (BFD_RELOC_MIPS_GPREL)
3508 <op> $treg+1,<sym>+4($at) (BFD_RELOC_MIPS_GPREL)
3517 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3518 mips_isa
< 3 ? "addu" : "daddu",
3519 "d,v,t", AT
, breg
, GP
);
3524 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
3525 coproc
? treg
+ 1 : treg
,
3526 (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
3527 offset_expr
.X_add_number
+= 4;
3528 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
3529 coproc
? treg
: treg
+ 1,
3530 (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
3546 assert (mips_isa
< 3);
3547 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
3548 (int) BFD_RELOC_LO16
, breg
);
3549 offset_expr
.X_add_number
+= 4;
3550 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
+ 1,
3551 (int) BFD_RELOC_LO16
, breg
);
3553 #ifdef LOSING_COMPILER
3559 as_warn ("Macro used $at after \".set noat\"");
3564 struct mips_cl_insn
*ip
;
3566 register int treg
, sreg
, dreg
, breg
;
3581 bfd_reloc_code_real_type r
;
3584 treg
= (ip
->insn_opcode
>> 16) & 0x1f;
3585 dreg
= (ip
->insn_opcode
>> 11) & 0x1f;
3586 sreg
= breg
= (ip
->insn_opcode
>> 21) & 0x1f;
3587 mask
= ip
->insn_mo
->mask
;
3589 expr1
.X_op
= O_constant
;
3590 expr1
.X_op_symbol
= NULL
;
3591 expr1
.X_add_symbol
= NULL
;
3592 expr1
.X_add_number
= 1;
3596 #endif /* LOSING_COMPILER */
3601 macro_build ((char *) NULL
, &icnt
, NULL
,
3602 dbl
? "dmultu" : "multu",
3604 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
3610 /* The MIPS assembler some times generates shifts and adds. I'm
3611 not trying to be that fancy. GCC should do this for us
3613 load_register (&icnt
, AT
, &imm_expr
);
3614 macro_build ((char *) NULL
, &icnt
, NULL
,
3615 dbl
? "dmult" : "mult",
3617 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
3623 mips_emit_delays ();
3625 mips_any_noreorder
= 1;
3626 macro_build ((char *) NULL
, &icnt
, NULL
,
3627 dbl
? "dmult" : "mult",
3629 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
3630 macro_build ((char *) NULL
, &icnt
, NULL
,
3631 dbl
? "dsra32" : "sra",
3632 "d,w,<", dreg
, dreg
, 31);
3633 macro_build ((char *) NULL
, &icnt
, NULL
, "mfhi", "d", AT
);
3635 macro_build ((char *) NULL
, &icnt
, NULL
, "tne", "s,t", dreg
, AT
);
3638 expr1
.X_add_number
= 8;
3639 macro_build ((char *) NULL
, &icnt
, &expr1
, "beq", "s,t,p", dreg
, AT
);
3640 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
3641 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 6);
3644 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
3650 mips_emit_delays ();
3652 mips_any_noreorder
= 1;
3653 macro_build ((char *) NULL
, &icnt
, NULL
,
3654 dbl
? "dmultu" : "multu",
3656 macro_build ((char *) NULL
, &icnt
, NULL
, "mfhi", "d", AT
);
3657 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
3659 macro_build ((char *) NULL
, &icnt
, NULL
, "tne", "s,t", AT
, 0);
3662 expr1
.X_add_number
= 8;
3663 macro_build ((char *) NULL
, &icnt
, &expr1
, "beq", "s,t,p", AT
, 0);
3664 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
3665 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 6);
3671 macro_build ((char *) NULL
, &icnt
, NULL
, "subu", "d,v,t", AT
, 0, treg
);
3672 macro_build ((char *) NULL
, &icnt
, NULL
, "srlv", "d,t,s", AT
, sreg
, AT
);
3673 macro_build ((char *) NULL
, &icnt
, NULL
, "sllv", "d,t,s", dreg
, sreg
,
3675 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
3679 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", AT
, sreg
,
3680 imm_expr
.X_add_number
& 0x1f);
3681 macro_build ((char *) NULL
, &icnt
, NULL
, "srl", "d,w,<", dreg
, sreg
,
3682 (0 - imm_expr
.X_add_number
) & 0x1f);
3683 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
3687 macro_build ((char *) NULL
, &icnt
, NULL
, "subu", "d,v,t", AT
, 0, treg
);
3688 macro_build ((char *) NULL
, &icnt
, NULL
, "sllv", "d,t,s", AT
, sreg
, AT
);
3689 macro_build ((char *) NULL
, &icnt
, NULL
, "srlv", "d,t,s", dreg
, sreg
,
3691 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
3695 macro_build ((char *) NULL
, &icnt
, NULL
, "srl", "d,w,<", AT
, sreg
,
3696 imm_expr
.X_add_number
& 0x1f);
3697 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", dreg
, sreg
,
3698 (0 - imm_expr
.X_add_number
) & 0x1f);
3699 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
3703 assert (mips_isa
< 2);
3704 /* Even on a big endian machine $fn comes before $fn+1. We have
3705 to adjust when storing to memory. */
3706 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "swc1", "T,o(b)",
3707 byte_order
== LITTLE_ENDIAN
? treg
: treg
+ 1,
3708 (int) BFD_RELOC_LO16
, breg
);
3709 offset_expr
.X_add_number
+= 4;
3710 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "swc1", "T,o(b)",
3711 byte_order
== LITTLE_ENDIAN
? treg
+ 1 : treg
,
3712 (int) BFD_RELOC_LO16
, breg
);
3717 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
3718 treg
, (int) BFD_RELOC_LO16
);
3720 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
3721 sreg
, (int) BFD_RELOC_LO16
);
3724 macro_build ((char *) NULL
, &icnt
, NULL
, "xor", "d,v,t", dreg
,
3726 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
3727 dreg
, (int) BFD_RELOC_LO16
);
3732 if (imm_expr
.X_add_number
== 0)
3734 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
3735 sreg
, (int) BFD_RELOC_LO16
);
3740 as_warn ("Instruction %s: result is always false",
3742 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
, 0);
3745 if (imm_expr
.X_add_number
>= 0 && imm_expr
.X_add_number
< 0x10000)
3747 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "xori", "t,r,i", dreg
,
3748 sreg
, (int) BFD_RELOC_LO16
);
3751 else if (imm_expr
.X_add_number
> -0x8000 && imm_expr
.X_add_number
< 0)
3753 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
3754 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
3755 mips_isa
< 3 ? "addiu" : "daddiu",
3756 "t,r,j", dreg
, sreg
,
3757 (int) BFD_RELOC_LO16
);
3762 load_register (&icnt
, AT
, &imm_expr
);
3763 macro_build ((char *) NULL
, &icnt
, NULL
, "xor", "d,v,t", dreg
,
3767 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
, dreg
,
3768 (int) BFD_RELOC_LO16
);
3773 case M_SGE
: /* sreg >= treg <==> not (sreg < treg) */
3779 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, sreg
, treg
);
3780 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
3781 (int) BFD_RELOC_LO16
);
3784 case M_SGE_I
: /* sreg >= I <==> not (sreg < I) */
3786 if (imm_expr
.X_add_number
>= -0x8000 && imm_expr
.X_add_number
< 0x8000)
3788 macro_build ((char *) NULL
, &icnt
, &expr1
,
3789 mask
== M_SGE_I
? "slti" : "sltiu",
3790 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
3795 load_register (&icnt
, AT
, &imm_expr
);
3796 macro_build ((char *) NULL
, &icnt
, NULL
,
3797 mask
== M_SGE_I
? "slt" : "sltu",
3798 "d,v,t", dreg
, sreg
, AT
);
3801 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
3802 (int) BFD_RELOC_LO16
);
3807 case M_SGT
: /* sreg > treg <==> treg < sreg */
3813 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, treg
, sreg
);
3816 case M_SGT_I
: /* sreg > I <==> I < sreg */
3822 load_register (&icnt
, AT
, &imm_expr
);
3823 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, AT
, sreg
);
3826 case M_SLE
: /* sreg <= treg <==> treg >= sreg <==> not (treg < sreg) */
3832 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, treg
, sreg
);
3833 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
3834 (int) BFD_RELOC_LO16
);
3837 case M_SLE_I
: /* sreg <= I <==> I >= sreg <==> not (I < sreg) */
3843 load_register (&icnt
, AT
, &imm_expr
);
3844 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, AT
, sreg
);
3845 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
3846 (int) BFD_RELOC_LO16
);
3850 if (imm_expr
.X_add_number
>= -0x8000 && imm_expr
.X_add_number
< 0x8000)
3852 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "slti", "t,r,j",
3853 dreg
, sreg
, (int) BFD_RELOC_LO16
);
3856 load_register (&icnt
, AT
, &imm_expr
);
3857 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", dreg
, sreg
, AT
);
3861 if (imm_expr
.X_add_number
>= -0x8000 && imm_expr
.X_add_number
< 0x8000)
3863 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "sltiu", "t,r,j",
3864 dreg
, sreg
, (int) BFD_RELOC_LO16
);
3867 load_register (&icnt
, AT
, &imm_expr
);
3868 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, sreg
,
3874 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0,
3877 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0,
3881 macro_build ((char *) NULL
, &icnt
, NULL
, "xor", "d,v,t", dreg
,
3883 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0,
3889 if (imm_expr
.X_add_number
== 0)
3891 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0,
3897 as_warn ("Instruction %s: result is always true",
3899 macro_build ((char *) NULL
, &icnt
, &expr1
,
3900 mips_isa
< 3 ? "addiu" : "daddiu",
3901 "t,r,j", dreg
, 0, (int) BFD_RELOC_LO16
);
3904 if (imm_expr
.X_add_number
>= 0 && imm_expr
.X_add_number
< 0x10000)
3906 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "xori", "t,r,i",
3907 dreg
, sreg
, (int) BFD_RELOC_LO16
);
3910 else if (imm_expr
.X_add_number
> -0x8000 && imm_expr
.X_add_number
< 0)
3912 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
3913 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
3914 mips_isa
< 3 ? "addiu" : "daddiu",
3915 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
3920 load_register (&icnt
, AT
, &imm_expr
);
3921 macro_build ((char *) NULL
, &icnt
, NULL
, "xor", "d,v,t", dreg
,
3925 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0, dreg
);
3933 if (imm_expr
.X_add_number
> -0x8000 && imm_expr
.X_add_number
<= 0x8000)
3935 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
3936 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
3937 dbl
? "daddi" : "addi",
3938 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
3941 load_register (&icnt
, AT
, &imm_expr
);
3942 macro_build ((char *) NULL
, &icnt
, NULL
,
3943 dbl
? "dsub" : "sub",
3944 "d,v,t", dreg
, sreg
, AT
);
3950 if (imm_expr
.X_add_number
> -0x8000 && imm_expr
.X_add_number
<= 0x8000)
3952 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
3953 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
3954 dbl
? "daddiu" : "addiu",
3955 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
3958 load_register (&icnt
, AT
, &imm_expr
);
3959 macro_build ((char *) NULL
, &icnt
, NULL
,
3960 dbl
? "dsubu" : "subu",
3961 "d,v,t", dreg
, sreg
, AT
);
3982 load_register (&icnt
, AT
, &imm_expr
);
3983 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "s,t", sreg
, AT
);
3988 assert (mips_isa
< 2);
3989 sreg
= (ip
->insn_opcode
>> 11) & 0x1f; /* floating reg */
3990 dreg
= (ip
->insn_opcode
>> 06) & 0x1f; /* floating reg */
3993 * Is the double cfc1 instruction a bug in the mips assembler;
3994 * or is there a reason for it?
3996 mips_emit_delays ();
3998 mips_any_noreorder
= 1;
3999 macro_build ((char *) NULL
, &icnt
, NULL
, "cfc1", "t,G", treg
, 31);
4000 macro_build ((char *) NULL
, &icnt
, NULL
, "cfc1", "t,G", treg
, 31);
4001 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "");
4002 expr1
.X_add_number
= 3;
4003 macro_build ((char *) NULL
, &icnt
, &expr1
, "ori", "t,r,i", AT
, treg
,
4004 (int) BFD_RELOC_LO16
);
4005 expr1
.X_add_number
= 2;
4006 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", AT
, AT
,
4007 (int) BFD_RELOC_LO16
);
4008 macro_build ((char *) NULL
, &icnt
, NULL
, "ctc1", "t,G", AT
, 31);
4009 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "");
4010 macro_build ((char *) NULL
, &icnt
, NULL
,
4011 mask
== M_TRUNCWD
? "cvt.w.d" : "cvt.w.s", "D,S", dreg
, sreg
);
4012 macro_build ((char *) NULL
, &icnt
, NULL
, "ctc1", "t,G", treg
, 31);
4013 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "");
4023 if (offset_expr
.X_add_number
>= 0x7fff)
4024 as_bad ("operand overflow");
4025 /* avoid load delay */
4026 if (byte_order
== LITTLE_ENDIAN
)
4027 offset_expr
.X_add_number
+= 1;
4028 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
4029 (int) BFD_RELOC_LO16
, breg
);
4030 if (byte_order
== LITTLE_ENDIAN
)
4031 offset_expr
.X_add_number
-= 1;
4033 offset_expr
.X_add_number
+= 1;
4034 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lbu", "t,o(b)", AT
,
4035 (int) BFD_RELOC_LO16
, breg
);
4036 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", treg
, treg
, 8);
4037 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", treg
, treg
, AT
);
4050 if (offset_expr
.X_add_number
>= 0x8000 - off
)
4051 as_bad ("operand overflow");
4052 if (byte_order
== LITTLE_ENDIAN
)
4053 offset_expr
.X_add_number
+= off
;
4054 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
4055 (int) BFD_RELOC_LO16
, breg
);
4056 if (byte_order
== LITTLE_ENDIAN
)
4057 offset_expr
.X_add_number
-= off
;
4059 offset_expr
.X_add_number
+= off
;
4060 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s2
, "t,o(b)", treg
,
4061 (int) BFD_RELOC_LO16
, breg
);
4074 load_address (&icnt
, AT
, &offset_expr
);
4075 if (byte_order
== LITTLE_ENDIAN
)
4076 expr1
.X_add_number
= off
;
4078 expr1
.X_add_number
= 0;
4079 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, "t,o(b)", treg
,
4080 (int) BFD_RELOC_LO16
, AT
);
4081 if (byte_order
== LITTLE_ENDIAN
)
4082 expr1
.X_add_number
= 0;
4084 expr1
.X_add_number
= off
;
4085 macro_build ((char *) NULL
, &icnt
, &expr1
, s2
, "t,o(b)", treg
,
4086 (int) BFD_RELOC_LO16
, AT
);
4091 load_address (&icnt
, AT
, &offset_expr
);
4092 if (byte_order
== BIG_ENDIAN
)
4093 expr1
.X_add_number
= 0;
4094 macro_build ((char *) NULL
, &icnt
, &expr1
,
4095 mask
== M_ULH_A
? "lb" : "lbu", "t,o(b)", treg
,
4096 (int) BFD_RELOC_LO16
, AT
);
4097 if (byte_order
== BIG_ENDIAN
)
4098 expr1
.X_add_number
= 1;
4100 expr1
.X_add_number
= 0;
4101 macro_build ((char *) NULL
, &icnt
, &expr1
, "lbu", "t,o(b)", AT
,
4102 (int) BFD_RELOC_LO16
, AT
);
4103 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", treg
,
4105 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", treg
,
4110 if (offset_expr
.X_add_number
>= 0x7fff)
4111 as_bad ("operand overflow");
4112 if (byte_order
== BIG_ENDIAN
)
4113 offset_expr
.X_add_number
+= 1;
4114 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "sb", "t,o(b)", treg
,
4115 (int) BFD_RELOC_LO16
, breg
);
4116 macro_build ((char *) NULL
, &icnt
, NULL
, "srl", "d,w,<", AT
, treg
, 8);
4117 if (byte_order
== BIG_ENDIAN
)
4118 offset_expr
.X_add_number
-= 1;
4120 offset_expr
.X_add_number
+= 1;
4121 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "sb", "t,o(b)", AT
,
4122 (int) BFD_RELOC_LO16
, breg
);
4135 if (offset_expr
.X_add_number
>= 0x8000 - off
)
4136 as_bad ("operand overflow");
4137 if (byte_order
== LITTLE_ENDIAN
)
4138 offset_expr
.X_add_number
+= off
;
4139 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
4140 (int) BFD_RELOC_LO16
, breg
);
4141 if (byte_order
== LITTLE_ENDIAN
)
4142 offset_expr
.X_add_number
-= off
;
4144 offset_expr
.X_add_number
+= off
;
4145 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s2
, "t,o(b)", treg
,
4146 (int) BFD_RELOC_LO16
, breg
);
4159 load_address (&icnt
, AT
, &offset_expr
);
4160 if (byte_order
== LITTLE_ENDIAN
)
4161 expr1
.X_add_number
= off
;
4163 expr1
.X_add_number
= 0;
4164 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, "t,o(b)", treg
,
4165 (int) BFD_RELOC_LO16
, AT
);
4166 if (byte_order
== LITTLE_ENDIAN
)
4167 expr1
.X_add_number
= 0;
4169 expr1
.X_add_number
= off
;
4170 macro_build ((char *) NULL
, &icnt
, &expr1
, s2
, "t,o(b)", treg
,
4171 (int) BFD_RELOC_LO16
, AT
);
4175 load_address (&icnt
, AT
, &offset_expr
);
4176 if (byte_order
== LITTLE_ENDIAN
)
4177 expr1
.X_add_number
= 0;
4178 macro_build ((char *) NULL
, &icnt
, &expr1
, "sb", "t,o(b)", treg
,
4179 (int) BFD_RELOC_LO16
, AT
);
4180 macro_build ((char *) NULL
, &icnt
, NULL
, "srl", "d,w,<", treg
,
4182 if (byte_order
== LITTLE_ENDIAN
)
4183 expr1
.X_add_number
= 1;
4185 expr1
.X_add_number
= 0;
4186 macro_build ((char *) NULL
, &icnt
, &expr1
, "sb", "t,o(b)", treg
,
4187 (int) BFD_RELOC_LO16
, AT
);
4188 if (byte_order
== LITTLE_ENDIAN
)
4189 expr1
.X_add_number
= 0;
4191 expr1
.X_add_number
= 1;
4192 macro_build ((char *) NULL
, &icnt
, &expr1
, "lbu", "t,o(b)", AT
,
4193 (int) BFD_RELOC_LO16
, AT
);
4194 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", treg
,
4196 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", treg
,
4201 as_bad ("Macro %s not implemented yet", ip
->insn_mo
->name
);
4205 as_warn ("Macro used $at after \".set noat\"");
4210 This routine assembles an instruction into its binary format. As a side
4211 effect it sets one of the global variables imm_reloc or offset_reloc to the
4212 type of relocation to do if one of the operands is an address expression.
4217 struct mips_cl_insn
*ip
;
4222 struct mips_opcode
*insn
;
4225 unsigned int lastregno
= 0;
4230 for (s
= str
; islower (*s
) || (*s
>= '0' && *s
<= '3') || *s
== '.'; ++s
)
4242 as_fatal ("Unknown opcode: `%s'", str
);
4244 if ((insn
= (struct mips_opcode
*) hash_find (op_hash
, str
)) == NULL
)
4246 as_warn ("`%s' not in hash table.", str
);
4247 insn_error
= "ERROR: Unrecognized opcode";
4255 assert (strcmp (insn
->name
, str
) == 0);
4257 if (insn
->pinfo
== INSN_MACRO
)
4258 insn_isa
= insn
->match
;
4259 else if ((insn
->pinfo
& INSN_ISA
) == INSN_ISA2
)
4261 else if ((insn
->pinfo
& INSN_ISA
) == INSN_ISA3
)
4266 if (insn_isa
> mips_isa
4267 || ((insn
->pinfo
& INSN_ISA
) == INSN_4650
4270 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
]
4271 && strcmp (insn
->name
, insn
[1].name
) == 0)
4276 as_warn ("Instruction not supported on this processor");
4280 ip
->insn_opcode
= insn
->match
;
4281 for (args
= insn
->args
;; ++args
)
4287 case '\0': /* end of args */
4300 ip
->insn_opcode
|= lastregno
<< 21;
4305 ip
->insn_opcode
|= lastregno
<< 16;
4309 ip
->insn_opcode
|= lastregno
<< 11;
4315 /* handle optional base register.
4316 Either the base register is omitted or
4317 we must have a left paren. */
4318 /* this is dependent on the next operand specifier
4319 is a 'b' for base register */
4320 assert (args
[1] == 'b');
4324 case ')': /* these must match exactly */
4329 case '<': /* must be at least one digit */
4331 * According to the manual, if the shift amount is greater
4332 * than 31 or less than 0 the the shift amount should be
4333 * mod 32. In reality the mips assembler issues an error.
4334 * We issue a warning and mask out all but the low 5 bits.
4336 my_getExpression (&imm_expr
, s
);
4337 check_absolute_expr (ip
, &imm_expr
);
4338 if ((unsigned long) imm_expr
.X_add_number
> 31)
4340 as_warn ("Improper shift amount (%ld)",
4341 (long) imm_expr
.X_add_number
);
4342 imm_expr
.X_add_number
= imm_expr
.X_add_number
& 0x1f;
4344 ip
->insn_opcode
|= imm_expr
.X_add_number
<< 6;
4345 imm_expr
.X_op
= O_absent
;
4349 case '>': /* shift amount minus 32 */
4350 my_getExpression (&imm_expr
, s
);
4351 check_absolute_expr (ip
, &imm_expr
);
4352 if ((unsigned long) imm_expr
.X_add_number
< 32
4353 || (unsigned long) imm_expr
.X_add_number
> 63)
4355 ip
->insn_opcode
|= (imm_expr
.X_add_number
- 32) << 6;
4356 imm_expr
.X_op
= O_absent
;
4360 case 'k': /* cache code */
4361 my_getExpression (&imm_expr
, s
);
4362 check_absolute_expr (ip
, &imm_expr
);
4363 if ((unsigned long) imm_expr
.X_add_number
> 31)
4365 as_warn ("Invalid cahce opcode (%lu)",
4366 (unsigned long) imm_expr
.X_add_number
);
4367 imm_expr
.X_add_number
&= 0x1f;
4369 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_CACHE
;
4370 imm_expr
.X_op
= O_absent
;
4374 case 'c': /* break code */
4375 my_getExpression (&imm_expr
, s
);
4376 check_absolute_expr (ip
, &imm_expr
);
4377 if ((unsigned) imm_expr
.X_add_number
> 1023)
4378 as_warn ("Illegal break code (%ld)",
4379 (long) imm_expr
.X_add_number
);
4380 ip
->insn_opcode
|= imm_expr
.X_add_number
<< 16;
4381 imm_expr
.X_op
= O_absent
;
4385 case 'B': /* syscall code */
4386 my_getExpression (&imm_expr
, s
);
4387 check_absolute_expr (ip
, &imm_expr
);
4388 if ((unsigned) imm_expr
.X_add_number
> 0xfffff)
4389 as_warn ("Illegal syscall code (%ld)",
4390 (long) imm_expr
.X_add_number
);
4391 ip
->insn_opcode
|= imm_expr
.X_add_number
<< 6;
4392 imm_expr
.X_op
= O_absent
;
4396 case 'C': /* Coprocessor code */
4397 my_getExpression (&imm_expr
, s
);
4398 check_absolute_expr (ip
, &imm_expr
);
4399 if ((unsigned long) imm_expr
.X_add_number
>= (1<<25))
4401 as_warn ("Coproccesor code > 25 bits (%ld)",
4402 (long) imm_expr
.X_add_number
);
4403 imm_expr
.X_add_number
&= ((1<<25) - 1);
4405 ip
->insn_opcode
|= imm_expr
.X_add_number
;
4406 imm_expr
.X_op
= O_absent
;
4410 case 'b': /* base register */
4411 case 'd': /* destination register */
4412 case 's': /* source register */
4413 case 't': /* target register */
4414 case 'r': /* both target and source */
4415 case 'v': /* both dest and source */
4416 case 'w': /* both dest and target */
4417 case 'E': /* coprocessor target register */
4418 case 'G': /* coprocessor destination register */
4419 case 'x': /* ignore register name */
4420 case 'z': /* must be zero register */
4434 while (isdigit (*s
));
4436 as_bad ("Invalid register number (%d)", regno
);
4438 else if (*args
== 'E' || *args
== 'G')
4442 if (s
[1] == 'f' && s
[2] == 'p')
4447 else if (s
[1] == 's' && s
[2] == 'p')
4452 else if (s
[1] == 'g' && s
[2] == 'p')
4457 else if (s
[1] == 'a' && s
[2] == 't')
4462 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '0')
4467 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '1')
4475 if (regno
== AT
&& ! mips_noat
)
4476 as_warn ("Used $at without \".set noat\"");
4482 if (c
== 'r' || c
== 'v' || c
== 'w')
4489 /* 'z' only matches $0. */
4490 if (c
== 'z' && regno
!= 0)
4498 ip
->insn_opcode
|= regno
<< 21;
4502 ip
->insn_opcode
|= regno
<< 11;
4507 ip
->insn_opcode
|= regno
<< 16;
4510 /* This case exists because on the r3000 trunc
4511 expands into a macro which requires a gp
4512 register. On the r6000 or r4000 it is
4513 assembled into a single instruction which
4514 ignores the register. Thus the insn version
4515 is MIPS_ISA2 and uses 'x', and the macro
4516 version is MIPS_ISA1 and uses 't'. */
4519 /* This case is for the div instruction, which
4520 acts differently if the destination argument
4521 is $0. This only matches $0, and is checked
4522 outside the switch. */
4533 ip
->insn_opcode
|= lastregno
<< 21;
4536 ip
->insn_opcode
|= lastregno
<< 16;
4541 case 'D': /* floating point destination register */
4542 case 'S': /* floating point source register */
4543 case 'T': /* floating point target register */
4547 if (s
[0] == '$' && s
[1] == 'f' && isdigit (s
[2]))
4557 while (isdigit (*s
));
4560 as_bad ("Invalid float register number (%d)", regno
);
4562 if ((regno
& 1) != 0
4564 && ! (strcmp (str
, "mtc1") == 0 ||
4565 strcmp (str
, "mfc1") == 0 ||
4566 strcmp (str
, "lwc1") == 0 ||
4567 strcmp (str
, "swc1") == 0))
4568 as_warn ("Float register should be even, was %d",
4576 if (c
== 'V' || c
== 'W')
4586 ip
->insn_opcode
|= regno
<< 6;
4590 ip
->insn_opcode
|= regno
<< 11;
4594 ip
->insn_opcode
|= regno
<< 16;
4602 ip
->insn_opcode
|= lastregno
<< 11;
4605 ip
->insn_opcode
|= lastregno
<< 16;
4611 my_getExpression (&imm_expr
, s
);
4612 if (imm_expr
.X_op
!= O_big
)
4613 check_absolute_expr (ip
, &imm_expr
);
4618 my_getExpression (&offset_expr
, s
);
4619 imm_reloc
= BFD_RELOC_32
;
4631 unsigned char temp
[8];
4633 unsigned int length
;
4638 /* These only appear as the last operand in an
4639 instruction, and every instruction that accepts
4640 them in any variant accepts them in all variants.
4641 This means we don't have to worry about backing out
4642 any changes if the instruction does not match.
4644 The difference between them is the size of the
4645 floating point constant and where it goes. For 'F'
4646 and 'L' the constant is 64 bits; for 'f' and 'l' it
4647 is 32 bits. Where the constant is placed is based
4648 on how the MIPS assembler does things:
4651 f -- immediate value
4654 The .lit4 and .lit8 sections are only used if
4655 permitted by the -G argument.
4657 When generating embedded PIC code, we use the
4658 .lit8 section but not the .lit4 section (we can do
4659 .lit4 inline easily; we need to put .lit8
4660 somewhere in the data segment, and using .lit8
4661 permits the linker to eventually combine identical
4664 f64
= *args
== 'F' || *args
== 'L';
4666 save_in
= input_line_pointer
;
4667 input_line_pointer
= s
;
4668 err
= md_atof (f64
? 'd' : 'f', (char *) temp
, &len
);
4670 s
= input_line_pointer
;
4671 input_line_pointer
= save_in
;
4672 if (err
!= NULL
&& *err
!= '\0')
4674 as_bad ("Bad floating point constant: %s", err
);
4675 memset (temp
, '\0', sizeof temp
);
4676 length
= f64
? 8 : 4;
4679 assert (length
== (f64
? 8 : 4));
4684 && (mips_pic
== EMBEDDED_PIC
4685 || g_switch_value
< 4)
4689 imm_expr
.X_op
= O_constant
;
4690 if (byte_order
== LITTLE_ENDIAN
)
4691 imm_expr
.X_add_number
=
4692 (((((((int) temp
[3] << 8)
4697 imm_expr
.X_add_number
=
4698 (((((((int) temp
[0] << 8)
4705 const char *newname
;
4708 /* Switch to the right section. */
4710 subseg
= now_subseg
;
4713 default: /* unused default case avoids warnings. */
4715 newname
= RDATA_SECTION_NAME
;
4717 if (g_switch_value
>= 8)
4722 newname
= RDATA_SECTION_NAME
;
4726 assert (g_switch_value
>= 4);
4731 new_seg
= subseg_new (newname
, (subsegT
) 0);
4732 frag_align (*args
== 'l' ? 2 : 3, 0);
4734 record_alignment (new_seg
, 4);
4736 record_alignment (new_seg
, *args
== 'l' ? 2 : 3);
4739 as_bad ("Can't use floating point insn in this section");
4741 /* Set the argument to the current address in the
4743 offset_expr
.X_op
= O_symbol
;
4744 offset_expr
.X_add_symbol
=
4745 symbol_new ("L0\001", now_seg
,
4746 (valueT
) frag_now_fix (), frag_now
);
4747 offset_expr
.X_add_number
= 0;
4749 /* Put the floating point number into the section. */
4750 p
= frag_more ((int) length
);
4751 memcpy (p
, temp
, length
);
4753 /* Switch back to the original section. */
4754 subseg_set (seg
, subseg
);
4759 case 'i': /* 16 bit unsigned immediate */
4760 case 'j': /* 16 bit signed immediate */
4761 imm_reloc
= BFD_RELOC_LO16
;
4762 c
= my_getSmallExpression (&imm_expr
, s
);
4767 if (imm_expr
.X_op
== O_constant
)
4768 imm_expr
.X_add_number
=
4769 (imm_expr
.X_add_number
>> 16) & 0xffff;
4771 imm_reloc
= BFD_RELOC_HI16_S
;
4773 imm_reloc
= BFD_RELOC_HI16
;
4776 else if (imm_expr
.X_op
!= O_big
)
4777 check_absolute_expr (ip
, &imm_expr
);
4780 if (imm_expr
.X_op
== O_big
4781 || imm_expr
.X_add_number
< 0
4782 || imm_expr
.X_add_number
>= 0x10000)
4784 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
4785 !strcmp (insn
->name
, insn
[1].name
))
4787 as_bad ("16 bit expression not in range 0..65535");
4795 /* The upper bound should be 0x8000, but
4796 unfortunately the MIPS assembler accepts numbers
4797 from 0x8000 to 0xffff and sign extends them, and
4798 we want to be compatible. We only permit this
4799 extended range for an instruction which does not
4800 provide any further alternates, since those
4801 alternates may handle other cases. People should
4802 use the numbers they mean, rather than relying on
4803 a mysterious sign extension. */
4804 more
= (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
4805 strcmp (insn
->name
, insn
[1].name
) == 0);
4810 if (imm_expr
.X_op
== O_big
4811 || imm_expr
.X_add_number
< -0x8000
4812 || imm_expr
.X_add_number
>= max
)
4816 as_bad ("16 bit expression not in range -32768..32767");
4822 case 'o': /* 16 bit offset */
4823 c
= my_getSmallExpression (&offset_expr
, s
);
4825 /* If this value won't fit into a 16 bit offset, then go
4826 find a macro that will generate the 32 bit offset
4827 code pattern. As a special hack, we accept the
4828 difference of two local symbols as a constant. This
4829 is required to suppose embedded PIC switches, which
4830 use an instruction which looks like
4831 lw $4,$L12-$LS12($4)
4832 The problem with handling this in a more general
4833 fashion is that the macro function doesn't expect to
4834 see anything which can be handled in a single
4835 constant instruction. */
4837 && (offset_expr
.X_op
!= O_constant
4838 || offset_expr
.X_add_number
>= 0x8000
4839 || offset_expr
.X_add_number
< -0x8000)
4840 && (mips_pic
!= EMBEDDED_PIC
4841 || offset_expr
.X_op
!= O_subtract
4842 || now_seg
!= text_section
4843 || (S_GET_SEGMENT (offset_expr
.X_op_symbol
)
4847 offset_reloc
= BFD_RELOC_LO16
;
4848 if (c
== 'h' || c
== 'H')
4850 assert (offset_expr
.X_op
== O_constant
);
4851 offset_expr
.X_add_number
=
4852 (offset_expr
.X_add_number
>> 16) & 0xffff;
4857 case 'p': /* pc relative offset */
4858 offset_reloc
= BFD_RELOC_16_PCREL_S2
;
4859 my_getExpression (&offset_expr
, s
);
4863 case 'u': /* upper 16 bits */
4864 c
= my_getSmallExpression (&imm_expr
, s
);
4865 if (imm_expr
.X_op
== O_constant
4866 && (imm_expr
.X_add_number
< 0
4867 || imm_expr
.X_add_number
>= 0x10000))
4868 as_bad ("lui expression not in range 0..65535");
4869 imm_reloc
= BFD_RELOC_LO16
;
4874 if (imm_expr
.X_op
== O_constant
)
4875 imm_expr
.X_add_number
=
4876 (imm_expr
.X_add_number
>> 16) & 0xffff;
4878 imm_reloc
= BFD_RELOC_HI16_S
;
4880 imm_reloc
= BFD_RELOC_HI16
;
4886 case 'a': /* 26 bit address */
4887 my_getExpression (&offset_expr
, s
);
4889 offset_reloc
= BFD_RELOC_MIPS_JMP
;
4893 fprintf (stderr
, "bad char = '%c'\n", *args
);
4898 /* Args don't match. */
4899 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
4900 !strcmp (insn
->name
, insn
[1].name
))
4906 insn_error
= "ERROR: Illegal operands";
4915 my_getSmallExpression (ep
, str
)
4926 ((str
[1] == 'h' && str
[2] == 'i')
4927 || (str
[1] == 'H' && str
[2] == 'I')
4928 || (str
[1] == 'l' && str
[2] == 'o'))
4940 * A small expression may be followed by a base register.
4941 * Scan to the end of this operand, and then back over a possible
4942 * base register. Then scan the small expression up to that
4943 * point. (Based on code in sparc.c...)
4945 for (sp
= str
; *sp
&& *sp
!= ','; sp
++)
4947 if (sp
- 4 >= str
&& sp
[-1] == RP
)
4949 if (isdigit (sp
[-2]))
4951 for (sp
-= 3; sp
>= str
&& isdigit (*sp
); sp
--)
4953 if (*sp
== '$' && sp
> str
&& sp
[-1] == LP
)
4959 else if (sp
- 5 >= str
4962 && ((sp
[-3] == 'f' && sp
[-2] == 'p')
4963 || (sp
[-3] == 's' && sp
[-2] == 'p')
4964 || (sp
[-3] == 'g' && sp
[-2] == 'p')
4965 || (sp
[-3] == 'a' && sp
[-2] == 't')))
4971 /* no expression means zero offset */
4974 /* %xx(reg) is an error */
4975 ep
->X_op
= O_absent
;
4980 ep
->X_op
= O_constant
;
4983 ep
->X_add_symbol
= NULL
;
4984 ep
->X_op_symbol
= NULL
;
4985 ep
->X_add_number
= 0;
4990 my_getExpression (ep
, str
);
4997 my_getExpression (ep
, str
);
4998 return c
; /* => %hi or %lo encountered */
5002 my_getExpression (ep
, str
)
5008 save_in
= input_line_pointer
;
5009 input_line_pointer
= str
;
5011 expr_end
= input_line_pointer
;
5012 input_line_pointer
= save_in
;
5015 /* Turn a string in input_line_pointer into a floating point constant
5016 of type type, and store the appropriate bytes in *litP. The number
5017 of LITTLENUMS emitted is stored in *sizeP . An error message is
5018 returned, or NULL on OK. */
5021 md_atof (type
, litP
, sizeP
)
5027 LITTLENUM_TYPE words
[4];
5043 return "bad call to md_atof";
5046 t
= atof_ieee (input_line_pointer
, type
, words
);
5048 input_line_pointer
= t
;
5052 if (byte_order
== LITTLE_ENDIAN
)
5054 for (i
= prec
- 1; i
>= 0; i
--)
5056 md_number_to_chars (litP
, (valueT
) words
[i
], 2);
5062 for (i
= 0; i
< prec
; i
++)
5064 md_number_to_chars (litP
, (valueT
) words
[i
], 2);
5073 md_number_to_chars (buf
, val
, n
)
5081 number_to_chars_littleendian (buf
, val
, n
);
5085 number_to_chars_bigendian (buf
, val
, n
);
5094 CONST
char *md_shortopts
= "O::g::G:";
5096 CONST
char *md_shortopts
= "O::g::";
5098 struct option md_longopts
[] = {
5099 #define OPTION_MIPS1 (OPTION_MD_BASE + 1)
5100 {"mips0", no_argument
, NULL
, OPTION_MIPS1
},
5101 {"mips1", no_argument
, NULL
, OPTION_MIPS1
},
5102 #define OPTION_MIPS2 (OPTION_MD_BASE + 2)
5103 {"mips2", no_argument
, NULL
, OPTION_MIPS2
},
5104 #define OPTION_MIPS3 (OPTION_MD_BASE + 3)
5105 {"mips3", no_argument
, NULL
, OPTION_MIPS3
},
5106 #define OPTION_MCPU (OPTION_MD_BASE + 4)
5107 {"mcpu", required_argument
, NULL
, OPTION_MCPU
},
5108 #define OPTION_MEMBEDDED_PIC (OPTION_MD_BASE + 5)
5109 {"membedded-pic", no_argument
, NULL
, OPTION_MEMBEDDED_PIC
},
5110 #define OPTION_TRAP (OPTION_MD_BASE + 8)
5111 {"trap", no_argument
, NULL
, OPTION_TRAP
},
5112 {"no-break", no_argument
, NULL
, OPTION_TRAP
},
5113 #define OPTION_BREAK (OPTION_MD_BASE + 9)
5114 {"break", no_argument
, NULL
, OPTION_BREAK
},
5115 {"no-trap", no_argument
, NULL
, OPTION_BREAK
},
5116 #define OPTION_EB (OPTION_MD_BASE + 10)
5117 {"EB", no_argument
, NULL
, OPTION_EB
},
5118 #define OPTION_EL (OPTION_MD_BASE + 11)
5119 {"EL", no_argument
, NULL
, OPTION_EL
},
5120 #define OPTION_M4650 (OPTION_MD_BASE + 12)
5121 {"m4650", no_argument
, NULL
, OPTION_M4650
},
5122 #define OPTION_NO_M4650 (OPTION_MD_BASE + 13)
5123 {"no-m4650", no_argument
, NULL
, OPTION_NO_M4650
},
5126 #define OPTION_CALL_SHARED (OPTION_MD_BASE + 6)
5127 {"KPIC", no_argument
, NULL
, OPTION_CALL_SHARED
},
5128 {"call_shared", no_argument
, NULL
, OPTION_CALL_SHARED
},
5129 #define OPTION_NON_SHARED (OPTION_MD_BASE + 7)
5130 {"non_shared", no_argument
, NULL
, OPTION_NON_SHARED
},
5133 {NULL
, no_argument
, NULL
, 0}
5135 size_t md_longopts_size
= sizeof(md_longopts
);
5138 md_parse_option (c
, arg
)
5153 byte_order
= BIG_ENDIAN
;
5155 mips_target_format
= "a.out-mips-big";
5158 mips_target_format
= "ecoff-bigmips";
5161 mips_target_format
= "elf32-bigmips";
5166 byte_order
= LITTLE_ENDIAN
;
5168 mips_target_format
= "a.out-mips-little";
5171 mips_target_format
= "ecoff-littlemips";
5174 mips_target_format
= "elf32-littlemips";
5179 if (arg
&& arg
[1] == '0')
5186 if (arg
== NULL
|| arg
[1] == '2')
5212 /* Identify the processor type */
5214 if (strcmp (p
, "default") == 0
5215 || strcmp (p
, "DEFAULT") == 0)
5219 if (*p
== 'r' || *p
== 'R')
5226 if (strcmp (p
, "2000") == 0
5227 || strcmp (p
, "2k") == 0
5228 || strcmp (p
, "2K") == 0)
5233 if (strcmp (p
, "3000") == 0
5234 || strcmp (p
, "3k") == 0
5235 || strcmp (p
, "3K") == 0)
5240 if (strcmp (p
, "4000") == 0
5241 || strcmp (p
, "4k") == 0
5242 || strcmp (p
, "4K") == 0)
5244 else if (strcmp (p
, "4400") == 0)
5246 else if (strcmp (p
, "4600") == 0)
5248 else if (strcmp (p
, "4650") == 0)
5257 if (strcmp (p
, "6000") == 0
5258 || strcmp (p
, "6k") == 0
5259 || strcmp (p
, "6K") == 0)
5264 if (strcmp (p
, "orion") == 0)
5271 as_bad ("invalid architecture -mcpu=%s", arg
);
5282 case OPTION_NO_M4650
:
5286 case OPTION_MEMBEDDED_PIC
:
5287 mips_pic
= EMBEDDED_PIC
;
5291 as_bad ("-G may not be used with embedded PIC code");
5294 g_switch_value
= 0x7fffffff;
5299 /* When generating ELF code, we permit -KPIC and -call_shared to
5300 select SVR4_PIC, and -non_shared to select no PIC. This is
5301 intended to be compatible with Irix 5. */
5302 case OPTION_CALL_SHARED
:
5303 mips_pic
= SVR4_PIC
;
5304 if (g_switch_seen
&& g_switch_value
!= 0)
5306 as_bad ("-G may not be used with SVR4 PIC code");
5312 case OPTION_NON_SHARED
:
5315 #endif /* OBJ_ELF */
5319 if (mips_pic
== SVR4_PIC
|| mips_pic
== EMBEDDED_PIC
)
5321 as_bad ("-G may not be used with SVR4 or embedded PIC code");
5325 g_switch_value
= atoi (arg
);
5338 md_show_usage (stream
)
5343 -membedded-pic generate embedded position independent code\n\
5344 -EB generate big endian output\n\
5345 -EL generate little endian output\n\
5346 -g, -g2 do not remove uneeded NOPs or swap branches\n\
5347 -G NUM allow referencing objects up to NUM bytes\n\
5348 implicitly with the gp register [default 8]\n");
5350 -mips1, -mcpu=r{2,3}000 generate code for r2000 and r3000\n\
5351 -mips2, -mcpu=r6000 generate code for r6000\n\
5352 -mips3, -mcpu=r4000 generate code for r4000\n\
5353 -O0 remove unneeded NOPs, do not swap branches\n\
5354 -O remove unneeded NOPs and swap branches\n\
5355 --trap, --no-break trap exception on div by 0 and mult overflow\n\
5356 --break, --no-trap break exception on div by 0 and mult overflow\n");
5359 -KPIC, -call_shared generate SVR4 position independent code\n\
5360 -non_shared do not generate position independent code\n");
5365 md_pcrel_from (fixP
)
5369 if (fixP
->fx_addsy
!= (symbolS
*) NULL
5370 && ! S_IS_DEFINED (fixP
->fx_addsy
))
5372 /* This makes a branch to an undefined symbol be a branch to the
5373 current location. */
5378 /* return the address of the delay slot */
5379 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
5382 /* This is called by emit_expr via TC_CONS_FIX_NEW when creating a
5383 reloc for a cons. We could use the definition there, except that
5384 we want to handle 64 bit relocs specially. */
5387 cons_fix_new_mips (frag
, where
, nbytes
, exp
)
5390 unsigned int nbytes
;
5393 /* If we are assembling in 32 bit mode, turn an 8 byte reloc into a
5395 FIXME: There is no way to select anything but 32 bit mode right
5399 if (byte_order
== BIG_ENDIAN
)
5404 if (nbytes
!= 2 && nbytes
!= 4)
5405 as_bad ("Unsupported reloc size %d", nbytes
);
5407 fix_new_exp (frag_now
, where
, (int) nbytes
, exp
, 0,
5408 nbytes
== 2 ? BFD_RELOC_16
: BFD_RELOC_32
);
5411 /* When generating embedded PIC code we need to use a special
5412 relocation to represent the difference of two symbols in the .text
5413 section (switch tables use a difference of this sort). See
5414 include/coff/mips.h for details. This macro checks whether this
5415 fixup requires the special reloc. */
5416 #define SWITCH_TABLE(fixp) \
5417 ((fixp)->fx_r_type == BFD_RELOC_32 \
5418 && (fixp)->fx_addsy != NULL \
5419 && (fixp)->fx_subsy != NULL \
5420 && S_GET_SEGMENT ((fixp)->fx_addsy) == text_section \
5421 && S_GET_SEGMENT ((fixp)->fx_subsy) == text_section)
5423 /* When generating embedded PIC code we must keep all PC relative
5424 relocations, in case the linker has to relax a call. We also need
5425 to keep relocations for switch table entries. */
5429 mips_force_relocation (fixp
)
5432 return (mips_pic
== EMBEDDED_PIC
5434 || SWITCH_TABLE (fixp
)
5435 || fixp
->fx_r_type
== BFD_RELOC_PCREL_HI16_S
5436 || fixp
->fx_r_type
== BFD_RELOC_PCREL_LO16
));
5439 /* Apply a fixup to the object file. */
5442 md_apply_fix (fixP
, valueP
)
5449 assert (fixP
->fx_size
== 4 || fixP
->fx_r_type
== BFD_RELOC_16
);
5452 fixP
->fx_addnumber
= value
; /* Remember value for tc_gen_reloc */
5454 if (fixP
->fx_addsy
== NULL
&& ! fixP
->fx_pcrel
)
5457 switch (fixP
->fx_r_type
)
5459 case BFD_RELOC_MIPS_JMP
:
5460 case BFD_RELOC_HI16
:
5461 case BFD_RELOC_HI16_S
:
5462 case BFD_RELOC_MIPS_GPREL
:
5463 case BFD_RELOC_MIPS_LITERAL
:
5464 case BFD_RELOC_MIPS_CALL16
:
5465 case BFD_RELOC_MIPS_GOT16
:
5466 case BFD_RELOC_MIPS_GPREL32
:
5468 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
5469 "Invalid PC relative reloc");
5470 /* Nothing needed to do. The value comes from the reloc entry */
5473 case BFD_RELOC_PCREL_HI16_S
:
5474 /* The addend for this is tricky if it is internal, so we just
5475 do everything here rather than in bfd_perform_relocation. */
5476 if ((fixP
->fx_addsy
->bsym
->flags
& BSF_SECTION_SYM
) == 0)
5478 /* For an external symbol adjust by the address to make it
5479 pcrel_offset. We use the address of the RELLO reloc
5480 which follows this one. */
5481 value
+= (fixP
->fx_next
->fx_frag
->fr_address
5482 + fixP
->fx_next
->fx_where
);
5487 buf
= (unsigned char *) fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
5488 if (byte_order
== BIG_ENDIAN
)
5490 md_number_to_chars (buf
, value
, 2);
5493 case BFD_RELOC_PCREL_LO16
:
5494 /* The addend for this is tricky if it is internal, so we just
5495 do everything here rather than in bfd_perform_relocation. */
5496 if ((fixP
->fx_addsy
->bsym
->flags
& BSF_SECTION_SYM
) == 0)
5497 value
+= fixP
->fx_frag
->fr_address
+ fixP
->fx_where
;
5498 buf
= (unsigned char *) fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
5499 if (byte_order
== BIG_ENDIAN
)
5501 md_number_to_chars (buf
, value
, 2);
5505 /* If we are deleting this reloc entry, we must fill in the
5506 value now. This can happen if we have a .word which is not
5507 resolved when it appears but is later defined. We also need
5508 to fill in the value if this is an embedded PIC switch table
5511 || (mips_pic
== EMBEDDED_PIC
&& SWITCH_TABLE (fixP
)))
5512 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
,
5517 /* If we are deleting this reloc entry, we must fill in the
5519 assert (fixP
->fx_size
== 2);
5521 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
,
5525 case BFD_RELOC_LO16
:
5526 /* When handling an embedded PIC switch statement, we can wind
5527 up deleting a LO16 reloc. See the 'o' case in mips_ip. */
5530 if (value
< -0x8000 || value
> 0x7fff)
5531 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
5532 "relocation overflow");
5533 buf
= (unsigned char *) fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
5534 if (byte_order
== BIG_ENDIAN
)
5536 md_number_to_chars (buf
, value
, 2);
5540 case BFD_RELOC_16_PCREL_S2
:
5542 * We need to save the bits in the instruction since fixup_segment()
5543 * might be deleting the relocation entry (i.e., a branch within
5544 * the current segment).
5547 as_warn_where (fixP
->fx_file
, fixP
->fx_line
,
5548 "Branch to odd address (%lx)", value
);
5551 /* update old instruction data */
5552 buf
= (unsigned char *) (fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
);
5556 insn
= (buf
[3] << 24) | (buf
[2] << 16) | (buf
[1] << 8) | buf
[0];
5560 insn
= (buf
[0] << 24) | (buf
[1] << 16) | (buf
[2] << 8) | buf
[3];
5568 if (value
>= -0x8000 && value
< 0x8000)
5569 insn
|= value
& 0xffff;
5572 /* The branch offset is too large. If this is an
5573 unconditional branch, and we are not generating PIC code,
5574 we can convert it to an absolute jump instruction. */
5575 if (mips_pic
== NO_PIC
5577 && fixP
->fx_frag
->fr_address
>= text_section
->vma
5578 && (fixP
->fx_frag
->fr_address
5579 < text_section
->vma
+ text_section
->_raw_size
)
5580 && ((insn
& 0xffff0000) == 0x10000000 /* beq $0,$0 */
5581 || (insn
& 0xffff0000) == 0x04010000 /* bgez $0 */
5582 || (insn
& 0xffff0000) == 0x04110000)) /* bgezal $0 */
5584 if ((insn
& 0xffff0000) == 0x04110000) /* bgezal $0 */
5585 insn
= 0x0c000000; /* jal */
5587 insn
= 0x08000000; /* j */
5588 fixP
->fx_r_type
= BFD_RELOC_MIPS_JMP
;
5590 fixP
->fx_addsy
= section_symbol (text_section
);
5591 fixP
->fx_addnumber
= (value
<< 2) + md_pcrel_from (fixP
);
5595 /* FIXME. It would be possible in principle to handle
5596 conditional branches which overflow. They could be
5597 transformed into a branch around a jump. This would
5598 require setting up variant frags for each different
5599 branch type. The native MIPS assembler attempts to
5600 handle these cases, but it appears to do it
5602 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
5603 "Relocation overflow");
5607 md_number_to_chars ((char *) buf
, (valueT
) insn
, 4);
5622 const struct mips_opcode
*p
;
5623 int treg
, sreg
, dreg
, shamt
;
5628 for (i
= 0; i
< NUMOPCODES
; ++i
)
5630 p
= &mips_opcodes
[i
];
5631 if (((oc
& p
->mask
) == p
->match
) && (p
->pinfo
!= INSN_MACRO
))
5633 printf ("%08lx %s\t", oc
, p
->name
);
5634 treg
= (oc
>> 16) & 0x1f;
5635 sreg
= (oc
>> 21) & 0x1f;
5636 dreg
= (oc
>> 11) & 0x1f;
5637 shamt
= (oc
>> 6) & 0x1f;
5639 for (args
= p
->args
;; ++args
)
5650 printf ("%c", *args
);
5654 assert (treg
== sreg
);
5655 printf ("$%d,$%d", treg
, sreg
);
5660 printf ("$%d", dreg
);
5665 printf ("$%d", treg
);
5669 printf ("0x%x", treg
);
5674 printf ("$%d", sreg
);
5678 printf ("0x%08lx", oc
& 0x1ffffff);
5690 printf ("$%d", shamt
);
5701 printf ("%08lx UNDEFINED\n", oc
);
5712 name
= input_line_pointer
;
5713 c
= get_symbol_end ();
5714 p
= (symbolS
*) symbol_find_or_make (name
);
5715 *input_line_pointer
= c
;
5719 /* Align the current frag to a given power of two. The MIPS assembler
5720 also automatically adjusts any preceding label. */
5723 mips_align (to
, fill
, label
)
5728 mips_emit_delays ();
5729 frag_align (to
, fill
);
5730 record_alignment (now_seg
, to
);
5733 assert (S_GET_SEGMENT (label
) == now_seg
);
5734 label
->sy_frag
= frag_now
;
5735 S_SET_VALUE (label
, (valueT
) frag_now_fix ());
5739 /* Align to a given power of two. .align 0 turns off the automatic
5740 alignment used by the data creating pseudo-ops. */
5747 register long temp_fill
;
5748 long max_alignment
= 15;
5752 o Note that the assembler pulls down any immediately preceeding label
5753 to the aligned address.
5754 o It's not documented but auto alignment is reinstated by
5755 a .align pseudo instruction.
5756 o Note also that after auto alignment is turned off the mips assembler
5757 issues an error on attempt to assemble an improperly aligned data item.
5762 temp
= get_absolute_expression ();
5763 if (temp
> max_alignment
)
5764 as_bad ("Alignment too large: %d. assumed.", temp
= max_alignment
);
5767 as_warn ("Alignment negative: 0 assumed.");
5770 if (*input_line_pointer
== ',')
5772 input_line_pointer
++;
5773 temp_fill
= get_absolute_expression ();
5780 mips_align (temp
, (int) temp_fill
, insn_label
);
5787 demand_empty_rest_of_line ();
5790 /* Handle .ascii and .asciiz. This just calls stringer and forgets
5791 that there was a previous instruction. */
5794 s_stringer (append_zero
)
5797 mips_emit_delays ();
5799 stringer (append_zero
);
5810 /* When generating embedded PIC code, we only use the .text, .lit8,
5811 .sdata and .sbss sections. We change the .data and .rdata
5812 pseudo-ops to use .sdata. */
5813 if (mips_pic
== EMBEDDED_PIC
5814 && (sec
== 'd' || sec
== 'r'))
5817 mips_emit_delays ();
5827 subseg_set (bss_section
, (subsegT
) get_absolute_expression ());
5828 demand_empty_rest_of_line ();
5833 seg
= subseg_new (RDATA_SECTION_NAME
,
5834 (subsegT
) get_absolute_expression ());
5836 bfd_set_section_flags (stdoutput
, seg
,
5842 bfd_set_section_alignment (stdoutput
, seg
, 4);
5844 demand_empty_rest_of_line ();
5845 #else /* ! defined (GPOPT) */
5846 as_bad ("No read only data section in this object file format");
5847 demand_empty_rest_of_line ();
5849 #endif /* ! defined (GPOPT) */
5854 seg
= subseg_new (".sdata", (subsegT
) get_absolute_expression ());
5856 bfd_set_section_flags (stdoutput
, seg
,
5857 SEC_ALLOC
| SEC_LOAD
| SEC_RELOC
| SEC_DATA
);
5858 bfd_set_section_alignment (stdoutput
, seg
, 4);
5860 demand_empty_rest_of_line ();
5862 #else /* ! defined (GPOPT) */
5863 as_bad ("Global pointers not supported; recompile -G 0");
5864 demand_empty_rest_of_line ();
5866 #endif /* ! defined (GPOPT) */
5874 /* Handle the ELF .section pseudo-op. This is a wrapper around
5881 mips_emit_delays ();
5882 obj_elf_section (x
);
5886 #endif /* OBJ_ELF */
5895 mips_emit_delays ();
5896 if (log_size
> 0 && auto_align
)
5897 mips_align (log_size
, 0, label
);
5899 cons (1 << log_size
);
5906 as_fatal ("Encountered `.err', aborting assembly");
5916 symbolP
= get_symbol ();
5917 if (*input_line_pointer
== ',')
5918 input_line_pointer
++;
5919 size
= get_absolute_expression ();
5920 S_SET_EXTERNAL (symbolP
);
5922 #ifdef ECOFF_DEBUGGING
5923 symbolP
->ecoff_extern_size
= size
;
5935 mips_emit_delays ();
5939 mips_align (3, 0, label
);
5941 mips_align (2, 0, label
);
5948 /* Handle .globl. We need to override it because on Irix 5 you are
5951 where foo is an undefined symbol, to mean that foo should be
5952 considered to be the address of a function. */
5962 name
= input_line_pointer
;
5963 c
= get_symbol_end ();
5964 symbolP
= symbol_find_or_make (name
);
5965 *input_line_pointer
= c
;
5967 if (! is_end_of_line
[(unsigned char) *input_line_pointer
])
5972 secname
= input_line_pointer
;
5973 c
= get_symbol_end ();
5974 sec
= bfd_get_section_by_name (stdoutput
, secname
);
5976 as_bad ("%s: no such section", secname
);
5977 *input_line_pointer
= c
;
5979 if (sec
!= NULL
&& (sec
->flags
& SEC_CODE
) != 0)
5980 symbolP
->bsym
->flags
|= BSF_FUNCTION
;
5983 S_SET_EXTERNAL (symbolP
);
5984 demand_empty_rest_of_line ();
5994 opt
= input_line_pointer
;
5995 c
= get_symbol_end ();
5999 /* FIXME: What does this mean? */
6001 else if (strncmp (opt
, "pic", 3) == 0)
6009 mips_pic
= SVR4_PIC
;
6011 as_bad (".option pic%d not supported", i
);
6014 if (mips_pic
== SVR4_PIC
)
6016 if (g_switch_seen
&& g_switch_value
!= 0)
6017 as_warn ("-G may not be used with SVR4 PIC code");
6019 bfd_set_gp_size (stdoutput
, 0);
6024 as_warn ("Unrecognized option \"%s\"", opt
);
6026 *input_line_pointer
= c
;
6027 demand_empty_rest_of_line ();
6034 char *name
= input_line_pointer
, ch
;
6036 while (!is_end_of_line
[(unsigned char) *input_line_pointer
])
6037 input_line_pointer
++;
6038 ch
= *input_line_pointer
;
6039 *input_line_pointer
= '\0';
6041 if (strcmp (name
, "reorder") == 0)
6045 prev_insn_unreordered
= 1;
6046 prev_prev_insn_unreordered
= 1;
6050 else if (strcmp (name
, "noreorder") == 0)
6052 mips_emit_delays ();
6054 mips_any_noreorder
= 1;
6056 else if (strcmp (name
, "at") == 0)
6060 else if (strcmp (name
, "noat") == 0)
6064 else if (strcmp (name
, "macro") == 0)
6066 mips_warn_about_macros
= 0;
6068 else if (strcmp (name
, "nomacro") == 0)
6070 if (mips_noreorder
== 0)
6071 as_bad ("`noreorder' must be set before `nomacro'");
6072 mips_warn_about_macros
= 1;
6074 else if (strcmp (name
, "move") == 0 || strcmp (name
, "novolatile") == 0)
6078 else if (strcmp (name
, "nomove") == 0 || strcmp (name
, "volatile") == 0)
6082 else if (strcmp (name
, "bopt") == 0)
6086 else if (strcmp (name
, "nobopt") == 0)
6090 else if (strncmp (name
, "mips", 4) == 0)
6094 /* Permit the user to change the ISA on the fly. Needless to
6095 say, misuse can cause serious problems. */
6096 isa
= atoi (name
+ 4);
6098 mips_isa
= file_mips_isa
;
6099 else if (isa
< 1 || isa
> 3)
6100 as_bad ("unknown ISA level");
6106 as_warn ("Tried to set unrecognized symbol: %s\n", name
);
6108 *input_line_pointer
= ch
;
6109 demand_empty_rest_of_line ();
6112 /* The same as the usual .space directive, except that we have to
6113 forget about any previous instruction. */
6116 s_mips_space (param
)
6119 mips_emit_delays ();
6124 /* Handle the .abicalls pseudo-op. I believe this is equivalent to
6125 .option pic2. It means to generate SVR4 PIC calls. */
6131 mips_pic
= SVR4_PIC
;
6133 if (g_switch_seen
&& g_switch_value
!= 0)
6134 as_warn ("-G may not be used with SVR4 PIC code");
6137 bfd_set_gp_size (stdoutput
, 0);
6138 demand_empty_rest_of_line ();
6141 /* Handle the .cpload pseudo-op. This is used when generating SVR4
6142 PIC code. It sets the $gp register for the function based on the
6143 function address, which is in the register named in the argument.
6144 This uses a relocation against _gp_disp, which is handled specially
6145 by the linker. The result is:
6146 lui $gp,%hi(_gp_disp)
6147 addiu $gp,$gp,%lo(_gp_disp)
6148 addu $gp,$gp,.cpload argument
6149 The .cpload argument is normally $25 == $t9. */
6158 /* If we are not generating SVR4 PIC code, .cpload is ignored. */
6159 if (mips_pic
!= SVR4_PIC
)
6165 /* .cpload should be a in .set noreorder section. */
6166 if (mips_noreorder
== 0)
6167 as_warn (".cpload not in noreorder section");
6170 ex
.X_add_symbol
= symbol_find_or_make ("_gp_disp");
6171 ex
.X_op_symbol
= NULL
;
6172 ex
.X_add_number
= 0;
6174 macro_build_lui ((char *) NULL
, &icnt
, &ex
, GP
);
6175 macro_build ((char *) NULL
, &icnt
, &ex
, "addiu", "t,r,j", GP
, GP
,
6176 (int) BFD_RELOC_LO16
);
6178 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "addu", "d,v,t",
6179 GP
, GP
, tc_get_register (0));
6181 demand_empty_rest_of_line ();
6184 /* Handle the .cprestore pseudo-op. This stores $gp into a given
6185 offset from $sp. The offset is remembered, and after making a PIC
6186 call $gp is restored from that location. */
6189 s_cprestore (ignore
)
6195 /* If we are not generating SVR4 PIC code, .cprestore is ignored. */
6196 if (mips_pic
!= SVR4_PIC
)
6202 mips_cprestore_offset
= get_absolute_expression ();
6204 ex
.X_op
= O_constant
;
6205 ex
.X_add_symbol
= NULL
;
6206 ex
.X_op_symbol
= NULL
;
6207 ex
.X_add_number
= mips_cprestore_offset
;
6209 macro_build ((char *) NULL
, &icnt
, &ex
,
6210 mips_isa
< 3 ? "sw" : "sd",
6211 "t,o(b)", GP
, (int) BFD_RELOC_LO16
, SP
);
6213 demand_empty_rest_of_line ();
6216 /* Handle the .gpword pseudo-op. This is used when generating PIC
6217 code. It generates a 32 bit GP relative reloc. */
6227 /* When not generating PIC code, this is treated as .word. */
6228 if (mips_pic
!= SVR4_PIC
)
6235 mips_emit_delays ();
6237 mips_align (2, 0, label
);
6242 if (ex
.X_op
!= O_symbol
|| ex
.X_add_number
!= 0)
6244 as_bad ("Unsupported use of .gpword");
6245 ignore_rest_of_line ();
6249 md_number_to_chars (p
, (valueT
) 0, 4);
6250 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 4, &ex
, 0,
6251 BFD_RELOC_MIPS_GPREL32
);
6253 demand_empty_rest_of_line ();
6256 /* Handle the .cpadd pseudo-op. This is used when dealing with switch
6257 tables in SVR4 PIC code. */
6266 /* This is ignored when not generating SVR4 PIC code. */
6267 if (mips_pic
!= SVR4_PIC
)
6273 /* Add $gp to the register named as an argument. */
6274 reg
= tc_get_register (0);
6275 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6276 mips_isa
< 3 ? "addu" : "daddu",
6277 "d,v,t", reg
, reg
, GP
);
6279 demand_empty_rest_of_line ();
6282 /* Parse a register string into a number. Called from the ECOFF code
6283 to parse .frame. The argument is non-zero if this is the frame
6284 register, so that we can record it in mips_frame_reg. */
6287 tc_get_register (frame
)
6293 if (*input_line_pointer
++ != '$')
6295 as_warn ("expected `$'");
6298 else if (isdigit ((unsigned char) *input_line_pointer
))
6300 reg
= get_absolute_expression ();
6301 if (reg
< 0 || reg
>= 32)
6303 as_warn ("Bad register number");
6309 if (strncmp (input_line_pointer
, "fp", 2) == 0)
6311 else if (strncmp (input_line_pointer
, "sp", 2) == 0)
6313 else if (strncmp (input_line_pointer
, "gp", 2) == 0)
6315 else if (strncmp (input_line_pointer
, "at", 2) == 0)
6319 as_warn ("Unrecognized register name");
6322 input_line_pointer
+= 2;
6325 mips_frame_reg
= reg
!= 0 ? reg
: SP
;
6330 md_section_align (seg
, addr
)
6334 int align
= bfd_get_section_alignment (stdoutput
, seg
);
6336 return ((addr
+ (1 << align
) - 1) & (-1 << align
));
6339 /* Estimate the size of a frag before relaxing. We are not really
6340 relaxing here, and the final size is encoded in the subtype
6345 md_estimate_size_before_relax (fragp
, segtype
)
6351 if (mips_pic
== NO_PIC
)
6354 const char *symname
;
6356 /* Find out whether this symbol can be referenced off the GP
6357 register. It can be if it is smaller than the -G size or if
6358 it is in the .sdata or .sbss section. Certain symbols can
6359 not be referenced off the GP, although it appears as though
6361 symname
= S_GET_NAME (fragp
->fr_symbol
);
6362 if (symname
!= (const char *) NULL
6363 && (strcmp (symname
, "eprol") == 0
6364 || strcmp (symname
, "etext") == 0
6365 || strcmp (symname
, "_gp") == 0
6366 || strcmp (symname
, "edata") == 0
6367 || strcmp (symname
, "_fbss") == 0
6368 || strcmp (symname
, "_fdata") == 0
6369 || strcmp (symname
, "_ftext") == 0
6370 || strcmp (symname
, "end") == 0
6371 || strcmp (symname
, "_gp_disp") == 0))
6373 else if (! S_IS_DEFINED (fragp
->fr_symbol
)
6374 && ((fragp
->fr_symbol
->ecoff_extern_size
!= 0
6375 && fragp
->fr_symbol
->ecoff_extern_size
<= g_switch_value
)
6376 || (S_GET_VALUE (fragp
->fr_symbol
) != 0
6377 && S_GET_VALUE (fragp
->fr_symbol
) <= g_switch_value
)))
6381 const char *segname
;
6383 segname
= segment_name (S_GET_SEGMENT (fragp
->fr_symbol
));
6384 assert (strcmp (segname
, ".lit8") != 0
6385 && strcmp (segname
, ".lit4") != 0);
6386 change
= (strcmp (segname
, ".sdata") != 0
6387 && strcmp (segname
, ".sbss") != 0);
6389 #else /* ! defined (GPOPT) */
6390 /* We are not optimizing for the GP register. */
6392 #endif /* ! defined (GPOPT) */
6394 else if (mips_pic
== SVR4_PIC
)
6396 asection
*symsec
= fragp
->fr_symbol
->bsym
->section
;
6398 /* This must duplicate the test in adjust_reloc_syms. */
6399 change
= (symsec
!= &bfd_und_section
6400 && symsec
!= &bfd_abs_section
6401 && ! bfd_is_com_section (symsec
));
6408 /* Record the offset to the first reloc in the fr_opcode field.
6409 This lets md_convert_frag and tc_gen_reloc know that the code
6410 must be expanded. */
6411 fragp
->fr_opcode
= (fragp
->fr_literal
6413 - RELAX_OLD (fragp
->fr_subtype
)
6414 + RELAX_RELOC1 (fragp
->fr_subtype
));
6415 /* FIXME: This really needs as_warn_where. */
6416 if (RELAX_WARN (fragp
->fr_subtype
))
6417 as_warn ("AT used after \".set noat\" or macro used after \".set nomacro\"");
6423 return RELAX_NEW (fragp
->fr_subtype
) - RELAX_OLD (fragp
->fr_subtype
);
6426 /* Translate internal representation of relocation info to BFD target
6430 tc_gen_reloc (section
, fixp
)
6434 static arelent
*retval
[4];
6437 reloc
= retval
[0] = (arelent
*) xmalloc (sizeof (arelent
));
6440 reloc
->sym_ptr_ptr
= &fixp
->fx_addsy
->bsym
;
6441 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
6443 if (mips_pic
== EMBEDDED_PIC
6444 && SWITCH_TABLE (fixp
))
6446 /* For a switch table entry we use a special reloc. The addend
6447 is actually the difference between the reloc address and the
6449 reloc
->addend
= reloc
->address
- S_GET_VALUE (fixp
->fx_subsy
);
6451 as_fatal ("Double check fx_r_type in tc-mips.c:tc_gen_reloc");
6453 fixp
->fx_r_type
= BFD_RELOC_GPREL32
;
6455 else if (fixp
->fx_r_type
== BFD_RELOC_PCREL_LO16
)
6457 /* We use a special addend for an internal RELLO reloc. */
6458 if (fixp
->fx_addsy
->bsym
->flags
& BSF_SECTION_SYM
)
6459 reloc
->addend
= reloc
->address
- S_GET_VALUE (fixp
->fx_subsy
);
6461 reloc
->addend
= fixp
->fx_addnumber
+ reloc
->address
;
6463 else if (fixp
->fx_r_type
== BFD_RELOC_PCREL_HI16_S
)
6465 assert (fixp
->fx_next
!= NULL
6466 && fixp
->fx_next
->fx_r_type
== BFD_RELOC_PCREL_LO16
);
6467 /* We use a special addend for an internal RELHI reloc. The
6468 reloc is relative to the RELLO; adjust the addend
6470 if (fixp
->fx_addsy
->bsym
->flags
& BSF_SECTION_SYM
)
6471 reloc
->addend
= (fixp
->fx_next
->fx_frag
->fr_address
6472 + fixp
->fx_next
->fx_where
6473 - S_GET_VALUE (fixp
->fx_subsy
));
6475 reloc
->addend
= (fixp
->fx_addnumber
6476 + fixp
->fx_next
->fx_frag
->fr_address
6477 + fixp
->fx_next
->fx_where
);
6479 else if (fixp
->fx_pcrel
== 0)
6480 reloc
->addend
= fixp
->fx_addnumber
;
6484 /* A gruesome hack which is a result of the gruesome gas reloc
6486 reloc
->addend
= reloc
->address
;
6488 reloc
->addend
= -reloc
->address
;
6492 /* If this is a variant frag, we may need to adjust the existing
6493 reloc and generate a new one. */
6494 if (fixp
->fx_frag
->fr_opcode
!= NULL
6495 && (fixp
->fx_r_type
== BFD_RELOC_MIPS_GPREL
6496 || fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT16
6497 || fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL16
))
6501 /* If this is not the last reloc in this frag, then we have two
6502 GPREL relocs, both of which are being replaced. Let the
6503 second one handle all of them. */
6504 if (fixp
->fx_next
!= NULL
6505 && fixp
->fx_frag
== fixp
->fx_next
->fx_frag
)
6507 assert (fixp
->fx_r_type
== BFD_RELOC_MIPS_GPREL
6508 && fixp
->fx_next
->fx_r_type
== BFD_RELOC_MIPS_GPREL
);
6513 fixp
->fx_where
= fixp
->fx_frag
->fr_opcode
- fixp
->fx_frag
->fr_literal
;
6514 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
6515 reloc2
= retval
[1] = (arelent
*) xmalloc (sizeof (arelent
));
6517 reloc2
->sym_ptr_ptr
= &fixp
->fx_addsy
->bsym
;
6518 reloc2
->address
= (reloc
->address
6519 + (RELAX_RELOC2 (fixp
->fx_frag
->fr_subtype
)
6520 - RELAX_RELOC1 (fixp
->fx_frag
->fr_subtype
)));
6521 reloc2
->addend
= fixp
->fx_addnumber
;
6522 reloc2
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_LO16
);
6523 assert (reloc2
->howto
!= NULL
);
6525 if (RELAX_RELOC3 (fixp
->fx_frag
->fr_subtype
))
6529 reloc3
= retval
[2] = (arelent
*) xmalloc (sizeof (arelent
));
6532 reloc3
->address
+= 4;
6535 if (mips_pic
== NO_PIC
)
6537 assert (fixp
->fx_r_type
== BFD_RELOC_MIPS_GPREL
);
6538 fixp
->fx_r_type
= BFD_RELOC_HI16_S
;
6540 else if (mips_pic
== SVR4_PIC
)
6542 if (fixp
->fx_r_type
!= BFD_RELOC_MIPS_GOT16
)
6544 assert (fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL16
);
6545 fixp
->fx_r_type
= BFD_RELOC_MIPS_GOT16
;
6552 /* To support a PC relative reloc when generating embedded PIC code
6553 for ECOFF, we use a Cygnus extension. We check for that here to
6554 make sure that we don't let such a reloc escape normally. */
6556 if (fixp
->fx_r_type
== BFD_RELOC_16_PCREL_S2
6557 && mips_pic
!= EMBEDDED_PIC
)
6558 reloc
->howto
= NULL
;
6561 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, fixp
->fx_r_type
);
6563 if (reloc
->howto
== NULL
)
6565 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
6566 "Can not represent relocation in this object file format");
6573 /* Convert a machine dependent frag. */
6576 md_convert_frag (abfd
, asec
, fragp
)
6584 if (fragp
->fr_opcode
== NULL
)
6587 old
= RELAX_OLD (fragp
->fr_subtype
);
6588 new = RELAX_NEW (fragp
->fr_subtype
);
6589 fixptr
= fragp
->fr_literal
+ fragp
->fr_fix
;
6592 memcpy (fixptr
- old
, fixptr
, new);
6594 fragp
->fr_fix
+= new - old
;
6597 /* This function is called whenever a label is defined. It is used
6598 when handling branch delays; if a branch has a label, we assume we
6602 mips_define_label (sym
)
6610 /* Some special processing for a MIPS ELF file. */
6613 mips_elf_final_processing ()
6617 /* Write out the .reginfo section. */
6618 s
.ri_gprmask
= mips_gprmask
;
6619 s
.ri_cprmask
[0] = mips_cprmask
[0];
6620 s
.ri_cprmask
[1] = mips_cprmask
[1];
6621 s
.ri_cprmask
[2] = mips_cprmask
[2];
6622 s
.ri_cprmask
[3] = mips_cprmask
[3];
6623 /* The gp_value field is set by the MIPS ELF backend. */
6625 bfd_mips_elf32_swap_reginfo_out (stdoutput
, &s
,
6626 ((Elf32_External_RegInfo
*)
6627 mips_regmask_frag
));
6629 /* Set the MIPS ELF flag bits. FIXME: There should probably be some
6630 sort of BFD interface for this. */
6631 if (mips_any_noreorder
)
6632 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_NOREORDER
;
6633 if (mips_pic
!= NO_PIC
)
6634 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_PIC
;
6637 #endif /* OBJ_ELF */
6639 #ifndef ECOFF_DEBUGGING
6641 /* These functions should really be defined by the object file format,
6642 since they are related to debugging information. However, this
6643 code has to work for the a.out format, which does not define them,
6644 so we provide simple versions here. These don't actually generate
6645 any debugging information, but they do simple checking and someday
6646 somebody may make them useful. */
6650 struct loc
*loc_next
;
6651 unsigned long loc_fileno
;
6652 unsigned long loc_lineno
;
6653 unsigned long loc_offset
;
6654 unsigned short loc_delta
;
6655 unsigned short loc_count
;
6664 struct proc
*proc_next
;
6665 struct symbol
*proc_isym
;
6666 struct symbol
*proc_end
;
6667 unsigned long proc_reg_mask
;
6668 unsigned long proc_reg_offset
;
6669 unsigned long proc_fpreg_mask
;
6670 unsigned long proc_fpreg_offset
;
6671 unsigned long proc_frameoffset
;
6672 unsigned long proc_framereg
;
6673 unsigned long proc_pcreg
;
6675 struct file
*proc_file
;
6682 struct file
*file_next
;
6683 unsigned long file_fileno
;
6684 struct symbol
*file_symbol
;
6685 struct symbol
*file_end
;
6686 struct proc
*file_proc
;
6691 static struct obstack proc_frags
;
6692 static procS
*proc_lastP
;
6693 static procS
*proc_rootP
;
6694 static int numprocs
;
6699 obstack_begin (&proc_frags
, 0x2000);
6705 /* check for premature end, nesting errors, etc */
6706 if (proc_lastP
&& proc_lastP
->proc_end
== NULL
)
6707 as_warn ("missing `.end' at end of assembly");
6716 if (*input_line_pointer
== '-')
6718 ++input_line_pointer
;
6721 if (!isdigit (*input_line_pointer
))
6722 as_bad ("Expected simple number.");
6723 if (input_line_pointer
[0] == '0')
6725 if (input_line_pointer
[1] == 'x')
6727 input_line_pointer
+= 2;
6728 while (isxdigit (*input_line_pointer
))
6731 val
|= hex_value (*input_line_pointer
++);
6733 return negative
? -val
: val
;
6737 ++input_line_pointer
;
6738 while (isdigit (*input_line_pointer
))
6741 val
|= *input_line_pointer
++ - '0';
6743 return negative
? -val
: val
;
6746 if (!isdigit (*input_line_pointer
))
6748 printf (" *input_line_pointer == '%c' 0x%02x\n",
6749 *input_line_pointer
, *input_line_pointer
);
6750 as_warn ("Invalid number");
6753 while (isdigit (*input_line_pointer
))
6756 val
+= *input_line_pointer
++ - '0';
6758 return negative
? -val
: val
;
6761 /* The .file directive; just like the usual .file directive, but there
6762 is an initial number which is the ECOFF file index. */
6770 line
= get_number ();
6775 /* The .end directive. */
6783 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
6786 demand_empty_rest_of_line ();
6790 if (now_seg
!= text_section
)
6791 as_warn (".end not in text section");
6794 as_warn (".end and no .ent seen yet.");
6800 assert (S_GET_NAME (p
));
6801 if (strcmp (S_GET_NAME (p
), S_GET_NAME (proc_lastP
->proc_isym
)))
6802 as_warn (".end symbol does not match .ent symbol.");
6805 proc_lastP
->proc_end
= (symbolS
*) 1;
6808 /* The .aent and .ent directives. */
6818 symbolP
= get_symbol ();
6819 if (*input_line_pointer
== ',')
6820 input_line_pointer
++;
6822 if (isdigit (*input_line_pointer
) || *input_line_pointer
== '-')
6823 number
= get_number ();
6824 if (now_seg
!= text_section
)
6825 as_warn (".ent or .aent not in text section.");
6827 if (!aent
&& proc_lastP
&& proc_lastP
->proc_end
== NULL
)
6828 as_warn ("missing `.end'");
6832 procP
= (procS
*) obstack_alloc (&proc_frags
, sizeof (*procP
));
6833 procP
->proc_isym
= symbolP
;
6834 procP
->proc_reg_mask
= 0;
6835 procP
->proc_reg_offset
= 0;
6836 procP
->proc_fpreg_mask
= 0;
6837 procP
->proc_fpreg_offset
= 0;
6838 procP
->proc_frameoffset
= 0;
6839 procP
->proc_framereg
= 0;
6840 procP
->proc_pcreg
= 0;
6841 procP
->proc_end
= NULL
;
6842 procP
->proc_next
= NULL
;
6844 proc_lastP
->proc_next
= procP
;
6850 demand_empty_rest_of_line ();
6853 /* The .frame directive. */
6866 frame_reg
= tc_get_register (1);
6867 if (*input_line_pointer
== ',')
6868 input_line_pointer
++;
6869 frame_off
= get_absolute_expression ();
6870 if (*input_line_pointer
== ',')
6871 input_line_pointer
++;
6872 pcreg
= tc_get_register (0);
6875 assert (proc_rootP
);
6876 proc_rootP
->proc_framereg
= frame_reg
;
6877 proc_rootP
->proc_frameoffset
= frame_off
;
6878 proc_rootP
->proc_pcreg
= pcreg
;
6879 /* bob macho .frame */
6881 /* We don't have to write out a frame stab for unoptimized code. */
6882 if (!(frame_reg
== FP
&& frame_off
== 0))
6885 as_warn ("No .ent for .frame to use.");
6886 (void) sprintf (str
, "R%d;%d", frame_reg
, frame_off
);
6887 symP
= symbol_new (str
, N_VFP
, 0, frag_now
);
6888 S_SET_TYPE (symP
, N_RMASK
);
6889 S_SET_OTHER (symP
, 0);
6890 S_SET_DESC (symP
, 0);
6891 symP
->sy_forward
= proc_lastP
->proc_isym
;
6892 /* bob perhaps I should have used pseudo set */
6894 demand_empty_rest_of_line ();
6898 /* The .fmask and .mask directives. */
6905 char str
[100], *strP
;
6911 mask
= get_number ();
6912 if (*input_line_pointer
== ',')
6913 input_line_pointer
++;
6914 off
= get_absolute_expression ();
6916 /* bob only for coff */
6917 assert (proc_rootP
);
6918 if (reg_type
== 'F')
6920 proc_rootP
->proc_fpreg_mask
= mask
;
6921 proc_rootP
->proc_fpreg_offset
= off
;
6925 proc_rootP
->proc_reg_mask
= mask
;
6926 proc_rootP
->proc_reg_offset
= off
;
6929 /* bob macho .mask + .fmask */
6931 /* We don't have to write out a mask stab if no saved regs. */
6935 as_warn ("No .ent for .mask to use.");
6937 for (i
= 0; i
< 32; i
++)
6941 sprintf (strP
, "%c%d,", reg_type
, i
);
6942 strP
+= strlen (strP
);
6946 sprintf (strP
, ";%d,", off
);
6947 symP
= symbol_new (str
, N_RMASK
, 0, frag_now
);
6948 S_SET_TYPE (symP
, N_RMASK
);
6949 S_SET_OTHER (symP
, 0);
6950 S_SET_DESC (symP
, 0);
6951 symP
->sy_forward
= proc_lastP
->proc_isym
;
6952 /* bob perhaps I should have used pseudo set */
6957 /* The .loc directive. */
6968 assert (now_seg
== text_section
);
6970 lineno
= get_number ();
6971 addroff
= frag_now_fix ();
6973 symbolP
= symbol_new ("", N_SLINE
, addroff
, frag_now
);
6974 S_SET_TYPE (symbolP
, N_SLINE
);
6975 S_SET_OTHER (symbolP
, 0);
6976 S_SET_DESC (symbolP
, lineno
);
6977 symbolP
->sy_segment
= now_seg
;
6981 #endif /* ! defined (ECOFF_DEBUGGING) */