1 /* tc-mips.c -- assemble code for a MIPS chip.
2 Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001
3 Free Software Foundation, Inc.
4 Contributed by the OSF and Ralph Campbell.
5 Written by Keith Knowles and Ralph Campbell, working independently.
6 Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus
9 This file is part of GAS.
11 GAS is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 2, or (at your option)
16 GAS is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
21 You should have received a copy of the GNU General Public License
22 along with GAS; see the file COPYING. If not, write to the Free
23 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
29 #include "safe-ctype.h"
38 #include "opcode/mips.h"
42 #define DBG(x) printf x
48 /* Clean up namespace so we can include obj-elf.h too. */
49 static int mips_output_flavor
PARAMS ((void));
50 static int mips_output_flavor () { return OUTPUT_FLAVOR
; }
51 #undef OBJ_PROCESS_STAB
58 #undef obj_frob_file_after_relocs
59 #undef obj_frob_symbol
61 #undef obj_sec_sym_ok_for_reloc
62 #undef OBJ_COPY_SYMBOL_ATTRIBUTES
65 /* Fix any of them that we actually care about. */
67 #define OUTPUT_FLAVOR mips_output_flavor()
74 #ifndef ECOFF_DEBUGGING
75 #define NO_ECOFF_DEBUGGING
76 #define ECOFF_DEBUGGING 0
81 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
82 static char *mips_regmask_frag
;
87 #define PIC_CALL_REG 25
95 #define ILLEGAL_REG (32)
97 /* Allow override of standard little-endian ECOFF format. */
99 #ifndef ECOFF_LITTLE_FORMAT
100 #define ECOFF_LITTLE_FORMAT "ecoff-littlemips"
103 extern int target_big_endian
;
105 /* The name of the readonly data section. */
106 #define RDATA_SECTION_NAME (OUTPUT_FLAVOR == bfd_target_aout_flavour \
108 : OUTPUT_FLAVOR == bfd_target_ecoff_flavour \
110 : OUTPUT_FLAVOR == bfd_target_coff_flavour \
112 : OUTPUT_FLAVOR == bfd_target_elf_flavour \
116 /* The ABI to use. */
127 /* MIPS ABI we are using for this output file. */
128 static enum mips_abi_level file_mips_abi
= NO_ABI
;
130 /* This is the set of options which may be modified by the .set
131 pseudo-op. We use a struct so that .set push and .set pop are more
134 struct mips_set_options
136 /* MIPS ISA (Instruction Set Architecture) level. This is set to -1
137 if it has not been initialized. Changed by `.set mipsN', and the
138 -mipsN command line option, and the default CPU. */
140 /* Whether we are assembling for the mips16 processor. 0 if we are
141 not, 1 if we are, and -1 if the value has not been initialized.
142 Changed by `.set mips16' and `.set nomips16', and the -mips16 and
143 -nomips16 command line options, and the default CPU. */
145 /* Non-zero if we should not reorder instructions. Changed by `.set
146 reorder' and `.set noreorder'. */
148 /* Non-zero if we should not permit the $at ($1) register to be used
149 in instructions. Changed by `.set at' and `.set noat'. */
151 /* Non-zero if we should warn when a macro instruction expands into
152 more than one machine instruction. Changed by `.set nomacro' and
154 int warn_about_macros
;
155 /* Non-zero if we should not move instructions. Changed by `.set
156 move', `.set volatile', `.set nomove', and `.set novolatile'. */
158 /* Non-zero if we should not optimize branches by moving the target
159 of the branch into the delay slot. Actually, we don't perform
160 this optimization anyhow. Changed by `.set bopt' and `.set
163 /* Non-zero if we should not autoextend mips16 instructions.
164 Changed by `.set autoextend' and `.set noautoextend'. */
166 /* Restrict general purpose registers and floating point registers
167 to 32 bit. This is initially determined when -mgp32 or -mfp32
168 is passed but can changed if the assembler code uses .set mipsN. */
171 /* The ABI currently in use. This is changed by .set mipsN to loosen
172 restrictions and doesn't affect the whole file. */
173 enum mips_abi_level abi
;
176 /* True if -mgp32 was passed. */
177 static int file_mips_gp32
= 0;
179 /* True if -mfp32 was passed. */
180 static int file_mips_fp32
= 0;
182 /* This is the struct we use to hold the current set of options. Note
183 that we must set the isa field to ISA_UNKNOWN and the mips16 field to
184 -1 to indicate that they have not been initialized. */
186 static struct mips_set_options mips_opts
=
188 ISA_UNKNOWN
, -1, 0, 0, 0, 0, 0, 0, 0, 0, NO_ABI
191 /* These variables are filled in with the masks of registers used.
192 The object format code reads them and puts them in the appropriate
194 unsigned long mips_gprmask
;
195 unsigned long mips_cprmask
[4];
197 /* MIPS ISA we are using for this output file. */
198 static int file_mips_isa
= ISA_UNKNOWN
;
200 /* The argument of the -mcpu= flag. Historical for code generation. */
201 static int mips_cpu
= CPU_UNKNOWN
;
203 /* The argument of the -march= flag. The architecture we are assembling. */
204 static int mips_arch
= CPU_UNKNOWN
;
206 /* The argument of the -mtune= flag. The architecture for which we
208 static int mips_tune
= CPU_UNKNOWN
;
210 /* Whether we should mark the file EABI64 or EABI32. */
211 static int mips_eabi64
= 0;
213 /* If they asked for mips1 or mips2 and a cpu that is
214 mips3 or greater, then mark the object file 32BITMODE. */
215 static int mips_32bitmode
= 0;
217 /* Some ISA's have delay slots for instructions which read or write
218 from a coprocessor (eg. mips1-mips3); some don't (eg mips4).
219 Return true if instructions marked INSN_LOAD_COPROC_DELAY,
220 INSN_COPROC_MOVE_DELAY, or INSN_WRITE_COND_CODE actually have a
221 delay slot in this ISA. The uses of this macro assume that any
222 ISA that has delay slots for one of these, has them for all. They
223 also assume that ISAs which don't have delays for these insns, don't
224 have delays for the INSN_LOAD_MEMORY_DELAY instructions either. */
225 #define ISA_HAS_COPROC_DELAYS(ISA) ( \
227 || (ISA) == ISA_MIPS2 \
228 || (ISA) == ISA_MIPS3 \
231 /* Return true if ISA supports 64 bit gp register instructions. */
232 #define ISA_HAS_64BIT_REGS(ISA) ( \
234 || (ISA) == ISA_MIPS4 \
235 || (ISA) == ISA_MIPS5 \
236 || (ISA) == ISA_MIPS64 \
239 #define HAVE_32BIT_GPRS \
241 || mips_opts.abi == O32_ABI \
242 || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
244 #define HAVE_32BIT_FPRS \
246 || mips_opts.abi == O32_ABI \
247 || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
249 #define HAVE_64BIT_GPRS (! HAVE_32BIT_GPRS)
250 #define HAVE_64BIT_FPRS (! HAVE_32BIT_FPRS)
252 #define HAVE_NEWABI (mips_opts.abi == N32_ABI || mips_opts.abi == N64_ABI)
254 #define HAVE_64BIT_OBJECTS (mips_opts.abi == N64_ABI)
256 /* We can only have 64bit addresses if the object file format
258 #define HAVE_32BIT_ADDRESSES \
260 || ((bfd_arch_bits_per_address (stdoutput) == 32 \
261 || ! HAVE_64BIT_OBJECTS) \
262 && mips_pic != EMBEDDED_PIC))
264 #define HAVE_64BIT_ADDRESSES (! HAVE_32BIT_ADDRESSES)
266 /* Whether the processor uses hardware interlocks to protect
267 reads from the HI and LO registers, and thus does not
268 require nops to be inserted. */
270 #define hilo_interlocks (mips_arch == CPU_R4010 \
271 || mips_arch == CPU_SB1 \
274 /* Whether the processor uses hardware interlocks to protect reads
275 from the GPRs, and thus does not require nops to be inserted. */
276 #define gpr_interlocks \
277 (mips_opts.isa != ISA_MIPS1 \
278 || mips_arch == CPU_R3900)
280 /* As with other "interlocks" this is used by hardware that has FP
281 (co-processor) interlocks. */
282 /* Itbl support may require additional care here. */
283 #define cop_interlocks (mips_arch == CPU_R4300 \
284 || mips_arch == CPU_SB1 \
287 /* Is this a mfhi or mflo instruction? */
288 #define MF_HILO_INSN(PINFO) \
289 ((PINFO & INSN_READ_HI) || (PINFO & INSN_READ_LO))
291 /* MIPS PIC level. */
295 /* Do not generate PIC code. */
298 /* Generate PIC code as in Irix 4. This is not implemented, and I'm
299 not sure what it is supposed to do. */
302 /* Generate PIC code as in the SVR4 MIPS ABI. */
305 /* Generate PIC code without using a global offset table: the data
306 segment has a maximum size of 64K, all data references are off
307 the $gp register, and all text references are PC relative. This
308 is used on some embedded systems. */
312 static enum mips_pic_level mips_pic
;
314 /* Warn about all NOPS that the assembler generates. */
315 static int warn_nops
= 0;
317 /* 1 if we should generate 32 bit offsets from the GP register in
318 SVR4_PIC mode. Currently has no meaning in other modes. */
319 static int mips_big_got
;
321 /* 1 if trap instructions should used for overflow rather than break
323 static int mips_trap
;
325 /* 1 if double width floating point constants should not be constructed
326 by assembling two single width halves into two single width floating
327 point registers which just happen to alias the double width destination
328 register. On some architectures this aliasing can be disabled by a bit
329 in the status register, and the setting of this bit cannot be determined
330 automatically at assemble time. */
331 static int mips_disable_float_construction
;
333 /* Non-zero if any .set noreorder directives were used. */
335 static int mips_any_noreorder
;
337 /* Non-zero if nops should be inserted when the register referenced in
338 an mfhi/mflo instruction is read in the next two instructions. */
339 static int mips_7000_hilo_fix
;
341 /* The size of the small data section. */
342 static unsigned int g_switch_value
= 8;
343 /* Whether the -G option was used. */
344 static int g_switch_seen
= 0;
349 /* If we can determine in advance that GP optimization won't be
350 possible, we can skip the relaxation stuff that tries to produce
351 GP-relative references. This makes delay slot optimization work
354 This function can only provide a guess, but it seems to work for
355 gcc output. It needs to guess right for gcc, otherwise gcc
356 will put what it thinks is a GP-relative instruction in a branch
359 I don't know if a fix is needed for the SVR4_PIC mode. I've only
360 fixed it for the non-PIC mode. KR 95/04/07 */
361 static int nopic_need_relax
PARAMS ((symbolS
*, int));
363 /* handle of the OPCODE hash table */
364 static struct hash_control
*op_hash
= NULL
;
366 /* The opcode hash table we use for the mips16. */
367 static struct hash_control
*mips16_op_hash
= NULL
;
369 /* This array holds the chars that always start a comment. If the
370 pre-processor is disabled, these aren't very useful */
371 const char comment_chars
[] = "#";
373 /* This array holds the chars that only start a comment at the beginning of
374 a line. If the line seems to have the form '# 123 filename'
375 .line and .file directives will appear in the pre-processed output */
376 /* Note that input_file.c hand checks for '#' at the beginning of the
377 first line of the input file. This is because the compiler outputs
378 #NO_APP at the beginning of its output. */
379 /* Also note that C style comments are always supported. */
380 const char line_comment_chars
[] = "#";
382 /* This array holds machine specific line separator characters. */
383 const char line_separator_chars
[] = ";";
385 /* Chars that can be used to separate mant from exp in floating point nums */
386 const char EXP_CHARS
[] = "eE";
388 /* Chars that mean this number is a floating point constant */
391 const char FLT_CHARS
[] = "rRsSfFdDxXpP";
393 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
394 changed in read.c . Ideally it shouldn't have to know about it at all,
395 but nothing is ideal around here.
398 static char *insn_error
;
400 static int auto_align
= 1;
402 /* When outputting SVR4 PIC code, the assembler needs to know the
403 offset in the stack frame from which to restore the $gp register.
404 This is set by the .cprestore pseudo-op, and saved in this
406 static offsetT mips_cprestore_offset
= -1;
408 /* Similiar for NewABI PIC code, where $gp is callee-saved. NewABI has some
409 more optimizations, it can use a register value instead of a memory-saved
410 offset and even an other than GP as global pointer. */
411 static offsetT mips_cpreturn_offset
= -1;
412 static int mips_cpreturn_register
= -1;
413 static int mips_gp_register
= GP
;
415 /* This is the register which holds the stack frame, as set by the
416 .frame pseudo-op. This is needed to implement .cprestore. */
417 static int mips_frame_reg
= SP
;
419 /* To output NOP instructions correctly, we need to keep information
420 about the previous two instructions. */
422 /* Whether we are optimizing. The default value of 2 means to remove
423 unneeded NOPs and swap branch instructions when possible. A value
424 of 1 means to not swap branches. A value of 0 means to always
426 static int mips_optimize
= 2;
428 /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is
429 equivalent to seeing no -g option at all. */
430 static int mips_debug
= 0;
432 /* The previous instruction. */
433 static struct mips_cl_insn prev_insn
;
435 /* The instruction before prev_insn. */
436 static struct mips_cl_insn prev_prev_insn
;
438 /* If we don't want information for prev_insn or prev_prev_insn, we
439 point the insn_mo field at this dummy integer. */
440 static const struct mips_opcode dummy_opcode
= { NULL
, NULL
, 0, 0, 0, 0 };
442 /* Non-zero if prev_insn is valid. */
443 static int prev_insn_valid
;
445 /* The frag for the previous instruction. */
446 static struct frag
*prev_insn_frag
;
448 /* The offset into prev_insn_frag for the previous instruction. */
449 static long prev_insn_where
;
451 /* The reloc type for the previous instruction, if any. */
452 static bfd_reloc_code_real_type prev_insn_reloc_type
[3];
454 /* The reloc for the previous instruction, if any. */
455 static fixS
*prev_insn_fixp
[3];
457 /* Non-zero if the previous instruction was in a delay slot. */
458 static int prev_insn_is_delay_slot
;
460 /* Non-zero if the previous instruction was in a .set noreorder. */
461 static int prev_insn_unreordered
;
463 /* Non-zero if the previous instruction uses an extend opcode (if
465 static int prev_insn_extended
;
467 /* Non-zero if the previous previous instruction was in a .set
469 static int prev_prev_insn_unreordered
;
471 /* If this is set, it points to a frag holding nop instructions which
472 were inserted before the start of a noreorder section. If those
473 nops turn out to be unnecessary, the size of the frag can be
475 static fragS
*prev_nop_frag
;
477 /* The number of nop instructions we created in prev_nop_frag. */
478 static int prev_nop_frag_holds
;
480 /* The number of nop instructions that we know we need in
482 static int prev_nop_frag_required
;
484 /* The number of instructions we've seen since prev_nop_frag. */
485 static int prev_nop_frag_since
;
487 /* For ECOFF and ELF, relocations against symbols are done in two
488 parts, with a HI relocation and a LO relocation. Each relocation
489 has only 16 bits of space to store an addend. This means that in
490 order for the linker to handle carries correctly, it must be able
491 to locate both the HI and the LO relocation. This means that the
492 relocations must appear in order in the relocation table.
494 In order to implement this, we keep track of each unmatched HI
495 relocation. We then sort them so that they immediately precede the
496 corresponding LO relocation. */
501 struct mips_hi_fixup
*next
;
504 /* The section this fixup is in. */
508 /* The list of unmatched HI relocs. */
510 static struct mips_hi_fixup
*mips_hi_fixup_list
;
512 /* Map normal MIPS register numbers to mips16 register numbers. */
514 #define X ILLEGAL_REG
515 static const int mips32_to_16_reg_map
[] =
517 X
, X
, 2, 3, 4, 5, 6, 7,
518 X
, X
, X
, X
, X
, X
, X
, X
,
519 0, 1, X
, X
, X
, X
, X
, X
,
520 X
, X
, X
, X
, X
, X
, X
, X
524 /* Map mips16 register numbers to normal MIPS register numbers. */
526 static const unsigned int mips16_to_32_reg_map
[] =
528 16, 17, 2, 3, 4, 5, 6, 7
531 /* Since the MIPS does not have multiple forms of PC relative
532 instructions, we do not have to do relaxing as is done on other
533 platforms. However, we do have to handle GP relative addressing
534 correctly, which turns out to be a similar problem.
536 Every macro that refers to a symbol can occur in (at least) two
537 forms, one with GP relative addressing and one without. For
538 example, loading a global variable into a register generally uses
539 a macro instruction like this:
541 If i can be addressed off the GP register (this is true if it is in
542 the .sbss or .sdata section, or if it is known to be smaller than
543 the -G argument) this will generate the following instruction:
545 This instruction will use a GPREL reloc. If i can not be addressed
546 off the GP register, the following instruction sequence will be used:
549 In this case the first instruction will have a HI16 reloc, and the
550 second reloc will have a LO16 reloc. Both relocs will be against
553 The issue here is that we may not know whether i is GP addressable
554 until after we see the instruction that uses it. Therefore, we
555 want to be able to choose the final instruction sequence only at
556 the end of the assembly. This is similar to the way other
557 platforms choose the size of a PC relative instruction only at the
560 When generating position independent code we do not use GP
561 addressing in quite the same way, but the issue still arises as
562 external symbols and local symbols must be handled differently.
564 We handle these issues by actually generating both possible
565 instruction sequences. The longer one is put in a frag_var with
566 type rs_machine_dependent. We encode what to do with the frag in
567 the subtype field. We encode (1) the number of existing bytes to
568 replace, (2) the number of new bytes to use, (3) the offset from
569 the start of the existing bytes to the first reloc we must generate
570 (that is, the offset is applied from the start of the existing
571 bytes after they are replaced by the new bytes, if any), (4) the
572 offset from the start of the existing bytes to the second reloc,
573 (5) whether a third reloc is needed (the third reloc is always four
574 bytes after the second reloc), and (6) whether to warn if this
575 variant is used (this is sometimes needed if .set nomacro or .set
576 noat is in effect). All these numbers are reasonably small.
578 Generating two instruction sequences must be handled carefully to
579 ensure that delay slots are handled correctly. Fortunately, there
580 are a limited number of cases. When the second instruction
581 sequence is generated, append_insn is directed to maintain the
582 existing delay slot information, so it continues to apply to any
583 code after the second instruction sequence. This means that the
584 second instruction sequence must not impose any requirements not
585 required by the first instruction sequence.
587 These variant frags are then handled in functions called by the
588 machine independent code. md_estimate_size_before_relax returns
589 the final size of the frag. md_convert_frag sets up the final form
590 of the frag. tc_gen_reloc adjust the first reloc and adds a second
592 #define RELAX_ENCODE(old, new, reloc1, reloc2, reloc3, warn) \
596 | (((reloc1) + 64) << 9) \
597 | (((reloc2) + 64) << 2) \
598 | ((reloc3) ? (1 << 1) : 0) \
600 #define RELAX_OLD(i) (((i) >> 23) & 0x7f)
601 #define RELAX_NEW(i) (((i) >> 16) & 0x7f)
602 #define RELAX_RELOC1(i) ((valueT) (((i) >> 9) & 0x7f) - 64)
603 #define RELAX_RELOC2(i) ((valueT) (((i) >> 2) & 0x7f) - 64)
604 #define RELAX_RELOC3(i) (((i) >> 1) & 1)
605 #define RELAX_WARN(i) ((i) & 1)
607 /* For mips16 code, we use an entirely different form of relaxation.
608 mips16 supports two versions of most instructions which take
609 immediate values: a small one which takes some small value, and a
610 larger one which takes a 16 bit value. Since branches also follow
611 this pattern, relaxing these values is required.
613 We can assemble both mips16 and normal MIPS code in a single
614 object. Therefore, we need to support this type of relaxation at
615 the same time that we support the relaxation described above. We
616 use the high bit of the subtype field to distinguish these cases.
618 The information we store for this type of relaxation is the
619 argument code found in the opcode file for this relocation, whether
620 the user explicitly requested a small or extended form, and whether
621 the relocation is in a jump or jal delay slot. That tells us the
622 size of the value, and how it should be stored. We also store
623 whether the fragment is considered to be extended or not. We also
624 store whether this is known to be a branch to a different section,
625 whether we have tried to relax this frag yet, and whether we have
626 ever extended a PC relative fragment because of a shift count. */
627 #define RELAX_MIPS16_ENCODE(type, small, ext, dslot, jal_dslot) \
630 | ((small) ? 0x100 : 0) \
631 | ((ext) ? 0x200 : 0) \
632 | ((dslot) ? 0x400 : 0) \
633 | ((jal_dslot) ? 0x800 : 0))
634 #define RELAX_MIPS16_P(i) (((i) & 0x80000000) != 0)
635 #define RELAX_MIPS16_TYPE(i) ((i) & 0xff)
636 #define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x100) != 0)
637 #define RELAX_MIPS16_USER_EXT(i) (((i) & 0x200) != 0)
638 #define RELAX_MIPS16_DSLOT(i) (((i) & 0x400) != 0)
639 #define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x800) != 0)
640 #define RELAX_MIPS16_EXTENDED(i) (((i) & 0x1000) != 0)
641 #define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x1000)
642 #define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) &~ 0x1000)
643 #define RELAX_MIPS16_LONG_BRANCH(i) (((i) & 0x2000) != 0)
644 #define RELAX_MIPS16_MARK_LONG_BRANCH(i) ((i) | 0x2000)
645 #define RELAX_MIPS16_CLEAR_LONG_BRANCH(i) ((i) &~ 0x2000)
647 /* Prototypes for static functions. */
650 #define internalError() \
651 as_fatal (_("internal Error, line %d, %s"), __LINE__, __FILE__)
653 #define internalError() as_fatal (_("MIPS internal Error"));
656 enum mips_regclass
{ MIPS_GR_REG
, MIPS_FP_REG
, MIPS16_REG
};
658 static int insn_uses_reg
PARAMS ((struct mips_cl_insn
*ip
,
659 unsigned int reg
, enum mips_regclass
class));
660 static int reg_needs_delay
PARAMS ((unsigned int));
661 static void mips16_mark_labels
PARAMS ((void));
662 static void append_insn
PARAMS ((char *place
,
663 struct mips_cl_insn
* ip
,
665 bfd_reloc_code_real_type
*r
,
667 static void mips_no_prev_insn
PARAMS ((int));
668 static void mips_emit_delays
PARAMS ((boolean
));
670 static void macro_build
PARAMS ((char *place
, int *counter
, expressionS
* ep
,
671 const char *name
, const char *fmt
,
674 static void macro_build ();
676 static void mips16_macro_build
PARAMS ((char *, int *, expressionS
*,
677 const char *, const char *,
679 static void macro_build_lui
PARAMS ((char *place
, int *counter
,
680 expressionS
* ep
, int regnum
));
681 static void set_at
PARAMS ((int *counter
, int reg
, int unsignedp
));
682 static void check_absolute_expr
PARAMS ((struct mips_cl_insn
* ip
,
684 static void load_register
PARAMS ((int *, int, expressionS
*, int));
685 static void load_address
PARAMS ((int *, int, expressionS
*, int, int *));
686 static void move_register
PARAMS ((int *, int, int));
687 static void macro
PARAMS ((struct mips_cl_insn
* ip
));
688 static void mips16_macro
PARAMS ((struct mips_cl_insn
* ip
));
689 #ifdef LOSING_COMPILER
690 static void macro2
PARAMS ((struct mips_cl_insn
* ip
));
692 static void mips_ip
PARAMS ((char *str
, struct mips_cl_insn
* ip
));
693 static void mips16_ip
PARAMS ((char *str
, struct mips_cl_insn
* ip
));
694 static void mips16_immed
PARAMS ((char *, unsigned int, int, offsetT
, boolean
,
695 boolean
, boolean
, unsigned long *,
696 boolean
*, unsigned short *));
697 static int my_getSmallParser
PARAMS ((char **, unsigned int *, int *));
698 static int my_getSmallExpression
PARAMS ((expressionS
*, char *));
699 static void my_getExpression
PARAMS ((expressionS
*, char *));
701 static int support_64bit_objects
PARAMS((void));
703 static symbolS
*get_symbol
PARAMS ((void));
704 static void mips_align
PARAMS ((int to
, int fill
, symbolS
*label
));
705 static void s_align
PARAMS ((int));
706 static void s_change_sec
PARAMS ((int));
707 static void s_cons
PARAMS ((int));
708 static void s_float_cons
PARAMS ((int));
709 static void s_mips_globl
PARAMS ((int));
710 static void s_option
PARAMS ((int));
711 static void s_mipsset
PARAMS ((int));
712 static void s_abicalls
PARAMS ((int));
713 static void s_cpload
PARAMS ((int));
714 static void s_cpsetup
PARAMS ((int));
715 static void s_cplocal
PARAMS ((int));
716 static void s_cprestore
PARAMS ((int));
717 static void s_cpreturn
PARAMS ((int));
718 static void s_gpvalue
PARAMS ((int));
719 static void s_gpword
PARAMS ((int));
720 static void s_cpadd
PARAMS ((int));
721 static void s_insn
PARAMS ((int));
722 static void md_obj_begin
PARAMS ((void));
723 static void md_obj_end
PARAMS ((void));
724 static long get_number
PARAMS ((void));
725 static void s_mips_ent
PARAMS ((int));
726 static void s_mips_end
PARAMS ((int));
727 static void s_mips_frame
PARAMS ((int));
728 static void s_mips_mask
PARAMS ((int));
729 static void s_mips_stab
PARAMS ((int));
730 static void s_mips_weakext
PARAMS ((int));
731 static void s_file
PARAMS ((int));
732 static int mips16_extended_frag
PARAMS ((fragS
*, asection
*, long));
733 static const char *mips_isa_to_str
PARAMS ((int));
734 static const char *mips_cpu_to_str
PARAMS ((int));
735 static int validate_mips_insn
PARAMS ((const struct mips_opcode
*));
736 static void show
PARAMS ((FILE *, char *, int *, int *));
738 /* Return values of my_getSmallExpression(). */
745 /* Direct relocation creation by %percent_op(). */
764 /* Table and functions used to map between CPU/ISA names, and
765 ISA levels, and CPU numbers. */
769 const char *name
; /* CPU or ISA name. */
770 int is_isa
; /* Is this an ISA? (If 0, a CPU.) */
771 int isa
; /* ISA level. */
772 int cpu
; /* CPU number (default CPU if ISA). */
775 static const struct mips_cpu_info
*mips_cpu_info_from_name
PARAMS ((const char *));
776 static const struct mips_cpu_info
*mips_cpu_info_from_isa
PARAMS ((int));
777 static const struct mips_cpu_info
*mips_cpu_info_from_cpu
PARAMS ((int));
781 The following pseudo-ops from the Kane and Heinrich MIPS book
782 should be defined here, but are currently unsupported: .alias,
783 .galive, .gjaldef, .gjrlive, .livereg, .noalias.
785 The following pseudo-ops from the Kane and Heinrich MIPS book are
786 specific to the type of debugging information being generated, and
787 should be defined by the object format: .aent, .begin, .bend,
788 .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp,
791 The following pseudo-ops from the Kane and Heinrich MIPS book are
792 not MIPS CPU specific, but are also not specific to the object file
793 format. This file is probably the best place to define them, but
794 they are not currently supported: .asm0, .endr, .lab, .repeat,
797 static const pseudo_typeS mips_pseudo_table
[] =
799 /* MIPS specific pseudo-ops. */
800 {"option", s_option
, 0},
801 {"set", s_mipsset
, 0},
802 {"rdata", s_change_sec
, 'r'},
803 {"sdata", s_change_sec
, 's'},
804 {"livereg", s_ignore
, 0},
805 {"abicalls", s_abicalls
, 0},
806 {"cpload", s_cpload
, 0},
807 {"cpsetup", s_cpsetup
, 0},
808 {"cplocal", s_cplocal
, 0},
809 {"cprestore", s_cprestore
, 0},
810 {"cpreturn", s_cpreturn
, 0},
811 {"gpvalue", s_gpvalue
, 0},
812 {"gpword", s_gpword
, 0},
813 {"cpadd", s_cpadd
, 0},
816 /* Relatively generic pseudo-ops that happen to be used on MIPS
818 {"asciiz", stringer
, 1},
819 {"bss", s_change_sec
, 'b'},
822 {"dword", s_cons
, 3},
823 {"weakext", s_mips_weakext
, 0},
825 /* These pseudo-ops are defined in read.c, but must be overridden
826 here for one reason or another. */
827 {"align", s_align
, 0},
829 {"data", s_change_sec
, 'd'},
830 {"double", s_float_cons
, 'd'},
831 {"float", s_float_cons
, 'f'},
832 {"globl", s_mips_globl
, 0},
833 {"global", s_mips_globl
, 0},
834 {"hword", s_cons
, 1},
839 {"short", s_cons
, 1},
840 {"single", s_float_cons
, 'f'},
841 {"stabn", s_mips_stab
, 'n'},
842 {"text", s_change_sec
, 't'},
845 #ifdef MIPS_STABS_ELF
846 { "extern", ecoff_directive_extern
, 0},
852 static const pseudo_typeS mips_nonecoff_pseudo_table
[] =
854 /* These pseudo-ops should be defined by the object file format.
855 However, a.out doesn't support them, so we have versions here. */
856 {"aent", s_mips_ent
, 1},
857 {"bgnb", s_ignore
, 0},
858 {"end", s_mips_end
, 0},
859 {"endb", s_ignore
, 0},
860 {"ent", s_mips_ent
, 0},
862 {"fmask", s_mips_mask
, 'F'},
863 {"frame", s_mips_frame
, 0},
864 {"loc", s_ignore
, 0},
865 {"mask", s_mips_mask
, 'R'},
866 {"verstamp", s_ignore
, 0},
870 extern void pop_insert
PARAMS ((const pseudo_typeS
*));
875 pop_insert (mips_pseudo_table
);
876 if (! ECOFF_DEBUGGING
)
877 pop_insert (mips_nonecoff_pseudo_table
);
880 /* Symbols labelling the current insn. */
882 struct insn_label_list
884 struct insn_label_list
*next
;
888 static struct insn_label_list
*insn_labels
;
889 static struct insn_label_list
*free_insn_labels
;
891 static void mips_clear_insn_labels
PARAMS ((void));
894 mips_clear_insn_labels ()
896 register struct insn_label_list
**pl
;
898 for (pl
= &free_insn_labels
; *pl
!= NULL
; pl
= &(*pl
)->next
)
904 static char *expr_end
;
906 /* Expressions which appear in instructions. These are set by
909 static expressionS imm_expr
;
910 static expressionS offset_expr
;
912 /* Relocs associated with imm_expr and offset_expr. */
914 static bfd_reloc_code_real_type imm_reloc
[3]
915 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
916 static bfd_reloc_code_real_type offset_reloc
[3]
917 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
919 /* This is set by mips_ip if imm_reloc is an unmatched HI16_S reloc. */
921 static boolean imm_unmatched_hi
;
923 /* These are set by mips16_ip if an explicit extension is used. */
925 static boolean mips16_small
, mips16_ext
;
927 #ifdef MIPS_STABS_ELF
928 /* The pdr segment for per procedure frame/regmask info */
934 mips_isa_to_str (isa
)
937 const struct mips_cpu_info
*ci
;
940 ci
= mips_cpu_info_from_isa (isa
);
944 sprintf (s
, "ISA#%d", isa
);
949 mips_cpu_to_str (cpu
)
952 const struct mips_cpu_info
*ci
;
955 ci
= mips_cpu_info_from_cpu (cpu
);
959 sprintf (s
, "CPU#%d", cpu
);
963 /* The default target format to use. */
966 mips_target_format ()
968 switch (OUTPUT_FLAVOR
)
970 case bfd_target_aout_flavour
:
971 return target_big_endian
? "a.out-mips-big" : "a.out-mips-little";
972 case bfd_target_ecoff_flavour
:
973 return target_big_endian
? "ecoff-bigmips" : ECOFF_LITTLE_FORMAT
;
974 case bfd_target_coff_flavour
:
976 case bfd_target_elf_flavour
:
978 /* This is traditional mips */
979 return (target_big_endian
980 ? (HAVE_64BIT_OBJECTS
? "elf64-tradbigmips"
981 : "elf32-tradbigmips")
982 : (HAVE_64BIT_OBJECTS
? "elf64-tradlittlemips"
983 : "elf32-tradlittlemips"));
985 return (target_big_endian
986 ? (HAVE_64BIT_OBJECTS
? "elf64-bigmips" : "elf32-bigmips")
987 : (HAVE_64BIT_OBJECTS
? "elf64-littlemips"
988 : "elf32-littlemips"));
996 /* This function is called once, at assembler startup time. It should
997 set up all the tables, etc. that the MD part of the assembler will need. */
1002 register const char *retval
= NULL
;
1007 int mips_isa_from_cpu
;
1008 int target_cpu_had_mips16
= 0;
1009 const struct mips_cpu_info
*ci
;
1011 /* GP relative stuff not working for PE */
1012 if (strncmp (TARGET_OS
, "pe", 2) == 0
1013 && g_switch_value
!= 0)
1016 as_bad (_("-G not supported in this configuration."));
1021 if (strcmp (cpu
+ (sizeof TARGET_CPU
) - 3, "el") == 0)
1023 a
= xmalloc (sizeof TARGET_CPU
);
1024 strcpy (a
, TARGET_CPU
);
1025 a
[(sizeof TARGET_CPU
) - 3] = '\0';
1029 if (strncmp (cpu
, "mips16", sizeof "mips16" - 1) == 0)
1031 target_cpu_had_mips16
= 1;
1032 cpu
+= sizeof "mips16" - 1;
1035 if (mips_opts
.mips16
< 0)
1036 mips_opts
.mips16
= target_cpu_had_mips16
;
1038 /* Backward compatibility for historic -mcpu= option. Check for
1039 incompatible options, warn if -mcpu is used. */
1040 if (mips_cpu
!= CPU_UNKNOWN
1041 && mips_arch
!= CPU_UNKNOWN
1042 && mips_cpu
!= mips_arch
)
1044 as_fatal (_("The -mcpu option can't be used together with -march. "
1045 "Use -mtune instead of -mcpu."));
1048 if (mips_cpu
!= CPU_UNKNOWN
1049 && mips_tune
!= CPU_UNKNOWN
1050 && mips_cpu
!= mips_tune
)
1052 as_fatal (_("The -mcpu option can't be used together with -mtune. "
1053 "Use -march instead of -mcpu."));
1056 if (mips_arch
== CPU_UNKNOWN
&& mips_cpu
!= CPU_UNKNOWN
)
1058 ci
= mips_cpu_info_from_cpu (mips_cpu
);
1059 assert (ci
!= NULL
);
1060 mips_arch
= ci
->cpu
;
1061 as_warn (_("The -mcpu option is deprecated. Please use -march and "
1062 "-mtune instead."));
1065 /* At this point, mips_arch will either be CPU_UNKNOWN if no ARCH was
1066 specified on the command line, or some other value if one was.
1067 Similarly, mips_opts.isa will be ISA_UNKNOWN if not specified on
1068 the command line, or will be set otherwise if one was. */
1069 if (mips_arch
!= CPU_UNKNOWN
&& mips_opts
.isa
!= ISA_UNKNOWN
)
1071 /* We have to check if the isa is the default isa of arch. Otherwise
1072 we'll get invalid object file headers. */
1073 ci
= mips_cpu_info_from_cpu (mips_arch
);
1074 assert (ci
!= NULL
);
1075 if (mips_opts
.isa
!= ci
->isa
)
1077 /* This really should be an error instead of a warning, but old
1078 compilers only have -mcpu which sets both arch and tune. For
1079 now, we discard arch and preserve tune. */
1080 as_warn (_("The -march option is incompatible to -mipsN and "
1081 "therefore ignored."));
1082 if (mips_tune
== CPU_UNKNOWN
)
1083 mips_tune
= mips_arch
;
1084 ci
= mips_cpu_info_from_isa (mips_opts
.isa
);
1085 assert (ci
!= NULL
);
1086 mips_arch
= ci
->cpu
;
1089 else if (mips_arch
!= CPU_UNKNOWN
&& mips_opts
.isa
== ISA_UNKNOWN
)
1091 /* We have ARCH, we need ISA. */
1092 ci
= mips_cpu_info_from_cpu (mips_arch
);
1093 assert (ci
!= NULL
);
1094 mips_opts
.isa
= ci
->isa
;
1096 else if (mips_arch
== CPU_UNKNOWN
&& mips_opts
.isa
!= ISA_UNKNOWN
)
1098 /* We have ISA, we need default ARCH. */
1099 ci
= mips_cpu_info_from_isa (mips_opts
.isa
);
1100 assert (ci
!= NULL
);
1101 mips_arch
= ci
->cpu
;
1105 /* We need to set both ISA and ARCH from target cpu. */
1106 ci
= mips_cpu_info_from_name (cpu
);
1108 ci
= mips_cpu_info_from_cpu (CPU_R3000
);
1109 assert (ci
!= NULL
);
1110 mips_opts
.isa
= ci
->isa
;
1111 mips_arch
= ci
->cpu
;
1114 if (mips_tune
== CPU_UNKNOWN
)
1115 mips_tune
= mips_arch
;
1117 ci
= mips_cpu_info_from_cpu (mips_arch
);
1118 assert (ci
!= NULL
);
1119 mips_isa_from_cpu
= ci
->isa
;
1121 /* End of TARGET_CPU processing, get rid of malloced memory
1130 if (mips_opts
.isa
== ISA_MIPS1
&& mips_trap
)
1131 as_bad (_("trap exception not supported at ISA 1"));
1133 /* Set the EABI kind based on the ISA before the user gets
1134 to change the ISA with directives. This isn't really
1135 the best, but then neither is basing the abi on the isa. */
1136 if (ISA_HAS_64BIT_REGS (mips_opts
.isa
)
1137 && mips_opts
.abi
== EABI_ABI
)
1140 /* If they asked for mips1 or mips2 and a cpu that is
1141 mips3 or greater, then mark the object file 32BITMODE. */
1142 if (mips_isa_from_cpu
!= ISA_UNKNOWN
1143 && ! ISA_HAS_64BIT_REGS (mips_opts
.isa
)
1144 && ISA_HAS_64BIT_REGS (mips_isa_from_cpu
))
1147 if (! bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, mips_arch
))
1148 as_warn (_("Could not set architecture and machine"));
1150 file_mips_isa
= mips_opts
.isa
;
1151 file_mips_abi
= mips_opts
.abi
;
1152 mips_opts
.gp32
= file_mips_gp32
;
1153 mips_opts
.fp32
= file_mips_fp32
;
1155 op_hash
= hash_new ();
1157 for (i
= 0; i
< NUMOPCODES
;)
1159 const char *name
= mips_opcodes
[i
].name
;
1161 retval
= hash_insert (op_hash
, name
, (PTR
) &mips_opcodes
[i
]);
1164 fprintf (stderr
, _("internal error: can't hash `%s': %s\n"),
1165 mips_opcodes
[i
].name
, retval
);
1166 /* Probably a memory allocation problem? Give up now. */
1167 as_fatal (_("Broken assembler. No assembly attempted."));
1171 if (mips_opcodes
[i
].pinfo
!= INSN_MACRO
)
1173 if (!validate_mips_insn (&mips_opcodes
[i
]))
1178 while ((i
< NUMOPCODES
) && !strcmp (mips_opcodes
[i
].name
, name
));
1181 mips16_op_hash
= hash_new ();
1184 while (i
< bfd_mips16_num_opcodes
)
1186 const char *name
= mips16_opcodes
[i
].name
;
1188 retval
= hash_insert (mips16_op_hash
, name
, (PTR
) &mips16_opcodes
[i
]);
1190 as_fatal (_("internal: can't hash `%s': %s"),
1191 mips16_opcodes
[i
].name
, retval
);
1194 if (mips16_opcodes
[i
].pinfo
!= INSN_MACRO
1195 && ((mips16_opcodes
[i
].match
& mips16_opcodes
[i
].mask
)
1196 != mips16_opcodes
[i
].match
))
1198 fprintf (stderr
, _("internal error: bad mips16 opcode: %s %s\n"),
1199 mips16_opcodes
[i
].name
, mips16_opcodes
[i
].args
);
1204 while (i
< bfd_mips16_num_opcodes
1205 && strcmp (mips16_opcodes
[i
].name
, name
) == 0);
1209 as_fatal (_("Broken assembler. No assembly attempted."));
1211 /* We add all the general register names to the symbol table. This
1212 helps us detect invalid uses of them. */
1213 for (i
= 0; i
< 32; i
++)
1217 sprintf (buf
, "$%d", i
);
1218 symbol_table_insert (symbol_new (buf
, reg_section
, i
,
1219 &zero_address_frag
));
1221 symbol_table_insert (symbol_new ("$fp", reg_section
, FP
,
1222 &zero_address_frag
));
1223 symbol_table_insert (symbol_new ("$sp", reg_section
, SP
,
1224 &zero_address_frag
));
1225 symbol_table_insert (symbol_new ("$gp", reg_section
, GP
,
1226 &zero_address_frag
));
1227 symbol_table_insert (symbol_new ("$at", reg_section
, AT
,
1228 &zero_address_frag
));
1229 symbol_table_insert (symbol_new ("$kt0", reg_section
, KT0
,
1230 &zero_address_frag
));
1231 symbol_table_insert (symbol_new ("$kt1", reg_section
, KT1
,
1232 &zero_address_frag
));
1233 symbol_table_insert (symbol_new ("$pc", reg_section
, -1,
1234 &zero_address_frag
));
1236 mips_no_prev_insn (false);
1239 mips_cprmask
[0] = 0;
1240 mips_cprmask
[1] = 0;
1241 mips_cprmask
[2] = 0;
1242 mips_cprmask
[3] = 0;
1244 /* set the default alignment for the text section (2**2) */
1245 record_alignment (text_section
, 2);
1247 if (USE_GLOBAL_POINTER_OPT
)
1248 bfd_set_gp_size (stdoutput
, g_switch_value
);
1250 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
1252 /* On a native system, sections must be aligned to 16 byte
1253 boundaries. When configured for an embedded ELF target, we
1255 if (strcmp (TARGET_OS
, "elf") != 0)
1257 (void) bfd_set_section_alignment (stdoutput
, text_section
, 4);
1258 (void) bfd_set_section_alignment (stdoutput
, data_section
, 4);
1259 (void) bfd_set_section_alignment (stdoutput
, bss_section
, 4);
1262 /* Create a .reginfo section for register masks and a .mdebug
1263 section for debugging information. */
1271 subseg
= now_subseg
;
1273 /* The ABI says this section should be loaded so that the
1274 running program can access it. However, we don't load it
1275 if we are configured for an embedded target */
1276 flags
= SEC_READONLY
| SEC_DATA
;
1277 if (strcmp (TARGET_OS
, "elf") != 0)
1278 flags
|= SEC_ALLOC
| SEC_LOAD
;
1282 sec
= subseg_new (".reginfo", (subsegT
) 0);
1284 (void) bfd_set_section_flags (stdoutput
, sec
, flags
);
1285 (void) bfd_set_section_alignment (stdoutput
, sec
, 2);
1288 mips_regmask_frag
= frag_more (sizeof (Elf32_External_RegInfo
));
1293 /* The 64-bit ABI uses a .MIPS.options section rather than
1294 .reginfo section. */
1295 sec
= subseg_new (".MIPS.options", (subsegT
) 0);
1296 (void) bfd_set_section_flags (stdoutput
, sec
, flags
);
1297 (void) bfd_set_section_alignment (stdoutput
, sec
, 3);
1300 /* Set up the option header. */
1302 Elf_Internal_Options opthdr
;
1305 opthdr
.kind
= ODK_REGINFO
;
1306 opthdr
.size
= (sizeof (Elf_External_Options
)
1307 + sizeof (Elf64_External_RegInfo
));
1310 f
= frag_more (sizeof (Elf_External_Options
));
1311 bfd_mips_elf_swap_options_out (stdoutput
, &opthdr
,
1312 (Elf_External_Options
*) f
);
1314 mips_regmask_frag
= frag_more (sizeof (Elf64_External_RegInfo
));
1319 if (ECOFF_DEBUGGING
)
1321 sec
= subseg_new (".mdebug", (subsegT
) 0);
1322 (void) bfd_set_section_flags (stdoutput
, sec
,
1323 SEC_HAS_CONTENTS
| SEC_READONLY
);
1324 (void) bfd_set_section_alignment (stdoutput
, sec
, 2);
1327 #ifdef MIPS_STABS_ELF
1328 pdr_seg
= subseg_new (".pdr", (subsegT
) 0);
1329 (void) bfd_set_section_flags (stdoutput
, pdr_seg
,
1330 SEC_READONLY
| SEC_RELOC
| SEC_DEBUGGING
);
1331 (void) bfd_set_section_alignment (stdoutput
, pdr_seg
, 2);
1334 subseg_set (seg
, subseg
);
1338 if (! ECOFF_DEBUGGING
)
1345 if (! ECOFF_DEBUGGING
)
1353 struct mips_cl_insn insn
;
1354 bfd_reloc_code_real_type unused_reloc
[3]
1355 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
1357 imm_expr
.X_op
= O_absent
;
1358 imm_unmatched_hi
= false;
1359 offset_expr
.X_op
= O_absent
;
1360 imm_reloc
[0] = BFD_RELOC_UNUSED
;
1361 imm_reloc
[1] = BFD_RELOC_UNUSED
;
1362 imm_reloc
[2] = BFD_RELOC_UNUSED
;
1363 offset_reloc
[0] = BFD_RELOC_UNUSED
;
1364 offset_reloc
[1] = BFD_RELOC_UNUSED
;
1365 offset_reloc
[2] = BFD_RELOC_UNUSED
;
1367 if (mips_opts
.mips16
)
1368 mips16_ip (str
, &insn
);
1371 mips_ip (str
, &insn
);
1372 DBG ((_("returned from mips_ip(%s) insn_opcode = 0x%x\n"),
1373 str
, insn
.insn_opcode
));
1378 as_bad ("%s `%s'", insn_error
, str
);
1382 if (insn
.insn_mo
->pinfo
== INSN_MACRO
)
1384 if (mips_opts
.mips16
)
1385 mips16_macro (&insn
);
1391 if (imm_expr
.X_op
!= O_absent
)
1392 append_insn (NULL
, &insn
, &imm_expr
, imm_reloc
, imm_unmatched_hi
);
1393 else if (offset_expr
.X_op
!= O_absent
)
1394 append_insn (NULL
, &insn
, &offset_expr
, offset_reloc
, false);
1396 append_insn (NULL
, &insn
, NULL
, unused_reloc
, false);
1400 /* See whether instruction IP reads register REG. CLASS is the type
1404 insn_uses_reg (ip
, reg
, class)
1405 struct mips_cl_insn
*ip
;
1407 enum mips_regclass
class;
1409 if (class == MIPS16_REG
)
1411 assert (mips_opts
.mips16
);
1412 reg
= mips16_to_32_reg_map
[reg
];
1413 class = MIPS_GR_REG
;
1416 /* Don't report on general register 0, since it never changes. */
1417 if (class == MIPS_GR_REG
&& reg
== 0)
1420 if (class == MIPS_FP_REG
)
1422 assert (! mips_opts
.mips16
);
1423 /* If we are called with either $f0 or $f1, we must check $f0.
1424 This is not optimal, because it will introduce an unnecessary
1425 NOP between "lwc1 $f0" and "swc1 $f1". To fix this we would
1426 need to distinguish reading both $f0 and $f1 or just one of
1427 them. Note that we don't have to check the other way,
1428 because there is no instruction that sets both $f0 and $f1
1429 and requires a delay. */
1430 if ((ip
->insn_mo
->pinfo
& INSN_READ_FPR_S
)
1431 && ((((ip
->insn_opcode
>> OP_SH_FS
) & OP_MASK_FS
) &~(unsigned)1)
1432 == (reg
&~ (unsigned) 1)))
1434 if ((ip
->insn_mo
->pinfo
& INSN_READ_FPR_T
)
1435 && ((((ip
->insn_opcode
>> OP_SH_FT
) & OP_MASK_FT
) &~(unsigned)1)
1436 == (reg
&~ (unsigned) 1)))
1439 else if (! mips_opts
.mips16
)
1441 if ((ip
->insn_mo
->pinfo
& INSN_READ_GPR_S
)
1442 && ((ip
->insn_opcode
>> OP_SH_RS
) & OP_MASK_RS
) == reg
)
1444 if ((ip
->insn_mo
->pinfo
& INSN_READ_GPR_T
)
1445 && ((ip
->insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
) == reg
)
1450 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_X
)
1451 && (mips16_to_32_reg_map
[((ip
->insn_opcode
>> MIPS16OP_SH_RX
)
1452 & MIPS16OP_MASK_RX
)]
1455 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_Y
)
1456 && (mips16_to_32_reg_map
[((ip
->insn_opcode
>> MIPS16OP_SH_RY
)
1457 & MIPS16OP_MASK_RY
)]
1460 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_Z
)
1461 && (mips16_to_32_reg_map
[((ip
->insn_opcode
>> MIPS16OP_SH_MOVE32Z
)
1462 & MIPS16OP_MASK_MOVE32Z
)]
1465 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_T
) && reg
== TREG
)
1467 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_SP
) && reg
== SP
)
1469 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_31
) && reg
== RA
)
1471 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_GPR_X
)
1472 && ((ip
->insn_opcode
>> MIPS16OP_SH_REGR32
)
1473 & MIPS16OP_MASK_REGR32
) == reg
)
1480 /* This function returns true if modifying a register requires a
1484 reg_needs_delay (reg
)
1487 unsigned long prev_pinfo
;
1489 prev_pinfo
= prev_insn
.insn_mo
->pinfo
;
1490 if (! mips_opts
.noreorder
1491 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
1492 && ((prev_pinfo
& INSN_LOAD_COPROC_DELAY
)
1493 || (! gpr_interlocks
1494 && (prev_pinfo
& INSN_LOAD_MEMORY_DELAY
))))
1496 /* A load from a coprocessor or from memory. All load
1497 delays delay the use of general register rt for one
1498 instruction on the r3000. The r6000 and r4000 use
1500 /* Itbl support may require additional care here. */
1501 know (prev_pinfo
& INSN_WRITE_GPR_T
);
1502 if (reg
== ((prev_insn
.insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
))
1509 /* Mark instruction labels in mips16 mode. This permits the linker to
1510 handle them specially, such as generating jalx instructions when
1511 needed. We also make them odd for the duration of the assembly, in
1512 order to generate the right sort of code. We will make them even
1513 in the adjust_symtab routine, while leaving them marked. This is
1514 convenient for the debugger and the disassembler. The linker knows
1515 to make them odd again. */
1518 mips16_mark_labels ()
1520 if (mips_opts
.mips16
)
1522 struct insn_label_list
*l
;
1525 for (l
= insn_labels
; l
!= NULL
; l
= l
->next
)
1528 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
1529 S_SET_OTHER (l
->label
, STO_MIPS16
);
1531 val
= S_GET_VALUE (l
->label
);
1533 S_SET_VALUE (l
->label
, val
+ 1);
1538 /* Output an instruction. PLACE is where to put the instruction; if
1539 it is NULL, this uses frag_more to get room. IP is the instruction
1540 information. ADDRESS_EXPR is an operand of the instruction to be
1541 used with RELOC_TYPE. */
1544 append_insn (place
, ip
, address_expr
, reloc_type
, unmatched_hi
)
1546 struct mips_cl_insn
*ip
;
1547 expressionS
*address_expr
;
1548 bfd_reloc_code_real_type
*reloc_type
;
1549 boolean unmatched_hi
;
1551 register unsigned long prev_pinfo
, pinfo
;
1556 /* Mark instruction labels in mips16 mode. */
1557 if (mips_opts
.mips16
)
1558 mips16_mark_labels ();
1560 prev_pinfo
= prev_insn
.insn_mo
->pinfo
;
1561 pinfo
= ip
->insn_mo
->pinfo
;
1563 if (place
== NULL
&& (! mips_opts
.noreorder
|| prev_nop_frag
!= NULL
))
1567 /* If the previous insn required any delay slots, see if we need
1568 to insert a NOP or two. There are eight kinds of possible
1569 hazards, of which an instruction can have at most one type.
1570 (1) a load from memory delay
1571 (2) a load from a coprocessor delay
1572 (3) an unconditional branch delay
1573 (4) a conditional branch delay
1574 (5) a move to coprocessor register delay
1575 (6) a load coprocessor register from memory delay
1576 (7) a coprocessor condition code delay
1577 (8) a HI/LO special register delay
1579 There are a lot of optimizations we could do that we don't.
1580 In particular, we do not, in general, reorder instructions.
1581 If you use gcc with optimization, it will reorder
1582 instructions and generally do much more optimization then we
1583 do here; repeating all that work in the assembler would only
1584 benefit hand written assembly code, and does not seem worth
1587 /* This is how a NOP is emitted. */
1588 #define emit_nop() \
1590 ? md_number_to_chars (frag_more (2), 0x6500, 2) \
1591 : md_number_to_chars (frag_more (4), 0, 4))
1593 /* The previous insn might require a delay slot, depending upon
1594 the contents of the current insn. */
1595 if (! mips_opts
.mips16
1596 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
1597 && (((prev_pinfo
& INSN_LOAD_COPROC_DELAY
)
1598 && ! cop_interlocks
)
1599 || (! gpr_interlocks
1600 && (prev_pinfo
& INSN_LOAD_MEMORY_DELAY
))))
1602 /* A load from a coprocessor or from memory. All load
1603 delays delay the use of general register rt for one
1604 instruction on the r3000. The r6000 and r4000 use
1606 /* Itbl support may require additional care here. */
1607 know (prev_pinfo
& INSN_WRITE_GPR_T
);
1608 if (mips_optimize
== 0
1609 || insn_uses_reg (ip
,
1610 ((prev_insn
.insn_opcode
>> OP_SH_RT
)
1615 else if (! mips_opts
.mips16
1616 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
1617 && (((prev_pinfo
& INSN_COPROC_MOVE_DELAY
)
1618 && ! cop_interlocks
)
1619 || (mips_opts
.isa
== ISA_MIPS1
1620 && (prev_pinfo
& INSN_COPROC_MEMORY_DELAY
))))
1622 /* A generic coprocessor delay. The previous instruction
1623 modified a coprocessor general or control register. If
1624 it modified a control register, we need to avoid any
1625 coprocessor instruction (this is probably not always
1626 required, but it sometimes is). If it modified a general
1627 register, we avoid using that register.
1629 On the r6000 and r4000 loading a coprocessor register
1630 from memory is interlocked, and does not require a delay.
1632 This case is not handled very well. There is no special
1633 knowledge of CP0 handling, and the coprocessors other
1634 than the floating point unit are not distinguished at
1636 /* Itbl support may require additional care here. FIXME!
1637 Need to modify this to include knowledge about
1638 user specified delays! */
1639 if (prev_pinfo
& INSN_WRITE_FPR_T
)
1641 if (mips_optimize
== 0
1642 || insn_uses_reg (ip
,
1643 ((prev_insn
.insn_opcode
>> OP_SH_FT
)
1648 else if (prev_pinfo
& INSN_WRITE_FPR_S
)
1650 if (mips_optimize
== 0
1651 || insn_uses_reg (ip
,
1652 ((prev_insn
.insn_opcode
>> OP_SH_FS
)
1659 /* We don't know exactly what the previous instruction
1660 does. If the current instruction uses a coprocessor
1661 register, we must insert a NOP. If previous
1662 instruction may set the condition codes, and the
1663 current instruction uses them, we must insert two
1665 /* Itbl support may require additional care here. */
1666 if (mips_optimize
== 0
1667 || ((prev_pinfo
& INSN_WRITE_COND_CODE
)
1668 && (pinfo
& INSN_READ_COND_CODE
)))
1670 else if (pinfo
& INSN_COP
)
1674 else if (! mips_opts
.mips16
1675 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
1676 && (prev_pinfo
& INSN_WRITE_COND_CODE
)
1677 && ! cop_interlocks
)
1679 /* The previous instruction sets the coprocessor condition
1680 codes, but does not require a general coprocessor delay
1681 (this means it is a floating point comparison
1682 instruction). If this instruction uses the condition
1683 codes, we need to insert a single NOP. */
1684 /* Itbl support may require additional care here. */
1685 if (mips_optimize
== 0
1686 || (pinfo
& INSN_READ_COND_CODE
))
1690 /* If we're fixing up mfhi/mflo for the r7000 and the
1691 previous insn was an mfhi/mflo and the current insn
1692 reads the register that the mfhi/mflo wrote to, then
1695 else if (mips_7000_hilo_fix
1696 && MF_HILO_INSN (prev_pinfo
)
1697 && insn_uses_reg (ip
, ((prev_insn
.insn_opcode
>> OP_SH_RD
)
1704 /* If we're fixing up mfhi/mflo for the r7000 and the
1705 2nd previous insn was an mfhi/mflo and the current insn
1706 reads the register that the mfhi/mflo wrote to, then
1709 else if (mips_7000_hilo_fix
1710 && MF_HILO_INSN (prev_prev_insn
.insn_opcode
)
1711 && insn_uses_reg (ip
, ((prev_prev_insn
.insn_opcode
>> OP_SH_RD
)
1719 else if (prev_pinfo
& INSN_READ_LO
)
1721 /* The previous instruction reads the LO register; if the
1722 current instruction writes to the LO register, we must
1723 insert two NOPS. Some newer processors have interlocks.
1724 Also the tx39's multiply instructions can be exectuted
1725 immediatly after a read from HI/LO (without the delay),
1726 though the tx39's divide insns still do require the
1728 if (! (hilo_interlocks
1729 || (mips_tune
== CPU_R3900
&& (pinfo
& INSN_MULT
)))
1730 && (mips_optimize
== 0
1731 || (pinfo
& INSN_WRITE_LO
)))
1733 /* Most mips16 branch insns don't have a delay slot.
1734 If a read from LO is immediately followed by a branch
1735 to a write to LO we have a read followed by a write
1736 less than 2 insns away. We assume the target of
1737 a branch might be a write to LO, and insert a nop
1738 between a read and an immediately following branch. */
1739 else if (mips_opts
.mips16
1740 && (mips_optimize
== 0
1741 || (pinfo
& MIPS16_INSN_BRANCH
)))
1744 else if (prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
1746 /* The previous instruction reads the HI register; if the
1747 current instruction writes to the HI register, we must
1748 insert a NOP. Some newer processors have interlocks.
1749 Also the note tx39's multiply above. */
1750 if (! (hilo_interlocks
1751 || (mips_tune
== CPU_R3900
&& (pinfo
& INSN_MULT
)))
1752 && (mips_optimize
== 0
1753 || (pinfo
& INSN_WRITE_HI
)))
1755 /* Most mips16 branch insns don't have a delay slot.
1756 If a read from HI is immediately followed by a branch
1757 to a write to HI we have a read followed by a write
1758 less than 2 insns away. We assume the target of
1759 a branch might be a write to HI, and insert a nop
1760 between a read and an immediately following branch. */
1761 else if (mips_opts
.mips16
1762 && (mips_optimize
== 0
1763 || (pinfo
& MIPS16_INSN_BRANCH
)))
1767 /* If the previous instruction was in a noreorder section, then
1768 we don't want to insert the nop after all. */
1769 /* Itbl support may require additional care here. */
1770 if (prev_insn_unreordered
)
1773 /* There are two cases which require two intervening
1774 instructions: 1) setting the condition codes using a move to
1775 coprocessor instruction which requires a general coprocessor
1776 delay and then reading the condition codes 2) reading the HI
1777 or LO register and then writing to it (except on processors
1778 which have interlocks). If we are not already emitting a NOP
1779 instruction, we must check for these cases compared to the
1780 instruction previous to the previous instruction. */
1781 if ((! mips_opts
.mips16
1782 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
1783 && (prev_prev_insn
.insn_mo
->pinfo
& INSN_COPROC_MOVE_DELAY
)
1784 && (prev_prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
)
1785 && (pinfo
& INSN_READ_COND_CODE
)
1786 && ! cop_interlocks
)
1787 || ((prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
)
1788 && (pinfo
& INSN_WRITE_LO
)
1789 && ! (hilo_interlocks
1790 || (mips_tune
== CPU_R3900
&& (pinfo
& INSN_MULT
))))
1791 || ((prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
1792 && (pinfo
& INSN_WRITE_HI
)
1793 && ! (hilo_interlocks
1794 || (mips_tune
== CPU_R3900
&& (pinfo
& INSN_MULT
)))))
1799 if (prev_prev_insn_unreordered
)
1802 if (prev_prev_nop
&& nops
== 0)
1805 /* If we are being given a nop instruction, don't bother with
1806 one of the nops we would otherwise output. This will only
1807 happen when a nop instruction is used with mips_optimize set
1810 && ! mips_opts
.noreorder
1811 && ip
->insn_opcode
== (unsigned) (mips_opts
.mips16
? 0x6500 : 0))
1814 /* Now emit the right number of NOP instructions. */
1815 if (nops
> 0 && ! mips_opts
.noreorder
)
1818 unsigned long old_frag_offset
;
1820 struct insn_label_list
*l
;
1822 old_frag
= frag_now
;
1823 old_frag_offset
= frag_now_fix ();
1825 for (i
= 0; i
< nops
; i
++)
1830 listing_prev_line ();
1831 /* We may be at the start of a variant frag. In case we
1832 are, make sure there is enough space for the frag
1833 after the frags created by listing_prev_line. The
1834 argument to frag_grow here must be at least as large
1835 as the argument to all other calls to frag_grow in
1836 this file. We don't have to worry about being in the
1837 middle of a variant frag, because the variants insert
1838 all needed nop instructions themselves. */
1842 for (l
= insn_labels
; l
!= NULL
; l
= l
->next
)
1846 assert (S_GET_SEGMENT (l
->label
) == now_seg
);
1847 symbol_set_frag (l
->label
, frag_now
);
1848 val
= (valueT
) frag_now_fix ();
1849 /* mips16 text labels are stored as odd. */
1850 if (mips_opts
.mips16
)
1852 S_SET_VALUE (l
->label
, val
);
1855 #ifndef NO_ECOFF_DEBUGGING
1856 if (ECOFF_DEBUGGING
)
1857 ecoff_fix_loc (old_frag
, old_frag_offset
);
1860 else if (prev_nop_frag
!= NULL
)
1862 /* We have a frag holding nops we may be able to remove. If
1863 we don't need any nops, we can decrease the size of
1864 prev_nop_frag by the size of one instruction. If we do
1865 need some nops, we count them in prev_nops_required. */
1866 if (prev_nop_frag_since
== 0)
1870 prev_nop_frag
->fr_fix
-= mips_opts
.mips16
? 2 : 4;
1871 --prev_nop_frag_holds
;
1874 prev_nop_frag_required
+= nops
;
1878 if (prev_prev_nop
== 0)
1880 prev_nop_frag
->fr_fix
-= mips_opts
.mips16
? 2 : 4;
1881 --prev_nop_frag_holds
;
1884 ++prev_nop_frag_required
;
1887 if (prev_nop_frag_holds
<= prev_nop_frag_required
)
1888 prev_nop_frag
= NULL
;
1890 ++prev_nop_frag_since
;
1892 /* Sanity check: by the time we reach the second instruction
1893 after prev_nop_frag, we should have used up all the nops
1894 one way or another. */
1895 assert (prev_nop_frag_since
<= 1 || prev_nop_frag
== NULL
);
1899 if (*reloc_type
> BFD_RELOC_UNUSED
)
1901 /* We need to set up a variant frag. */
1902 assert (mips_opts
.mips16
&& address_expr
!= NULL
);
1903 f
= frag_var (rs_machine_dependent
, 4, 0,
1904 RELAX_MIPS16_ENCODE (*reloc_type
- BFD_RELOC_UNUSED
,
1905 mips16_small
, mips16_ext
,
1907 & INSN_UNCOND_BRANCH_DELAY
),
1908 (*prev_insn_reloc_type
1909 == BFD_RELOC_MIPS16_JMP
)),
1910 make_expr_symbol (address_expr
), 0, NULL
);
1912 else if (place
!= NULL
)
1914 else if (mips_opts
.mips16
1916 && *reloc_type
!= BFD_RELOC_MIPS16_JMP
)
1918 /* Make sure there is enough room to swap this instruction with
1919 a following jump instruction. */
1925 if (mips_opts
.mips16
1926 && mips_opts
.noreorder
1927 && (prev_pinfo
& INSN_UNCOND_BRANCH_DELAY
) != 0)
1928 as_warn (_("extended instruction in delay slot"));
1933 fixp
[0] = fixp
[1] = fixp
[2] = NULL
;
1934 if (address_expr
!= NULL
&& *reloc_type
< BFD_RELOC_UNUSED
)
1936 if (address_expr
->X_op
== O_constant
)
1940 switch (*reloc_type
)
1943 ip
->insn_opcode
|= address_expr
->X_add_number
;
1946 case BFD_RELOC_MIPS_HIGHEST
:
1947 tmp
= (address_expr
->X_add_number
+ 0x800080008000) >> 16;
1949 ip
->insn_opcode
|= (tmp
>> 16) & 0xffff;
1952 case BFD_RELOC_MIPS_HIGHER
:
1953 tmp
= (address_expr
->X_add_number
+ 0x80008000) >> 16;
1954 ip
->insn_opcode
|= (tmp
>> 16) & 0xffff;
1957 case BFD_RELOC_HI16_S
:
1958 ip
->insn_opcode
|= ((address_expr
->X_add_number
+ 0x8000)
1962 case BFD_RELOC_HI16
:
1963 ip
->insn_opcode
|= (address_expr
->X_add_number
>> 16) & 0xffff;
1966 case BFD_RELOC_LO16
:
1967 ip
->insn_opcode
|= address_expr
->X_add_number
& 0xffff;
1970 case BFD_RELOC_MIPS_JMP
:
1971 if ((address_expr
->X_add_number
& 3) != 0)
1972 as_bad (_("jump to misaligned address (0x%lx)"),
1973 (unsigned long) address_expr
->X_add_number
);
1974 ip
->insn_opcode
|= (address_expr
->X_add_number
>> 2) & 0x3ffffff;
1977 case BFD_RELOC_MIPS16_JMP
:
1978 if ((address_expr
->X_add_number
& 3) != 0)
1979 as_bad (_("jump to misaligned address (0x%lx)"),
1980 (unsigned long) address_expr
->X_add_number
);
1982 (((address_expr
->X_add_number
& 0x7c0000) << 3)
1983 | ((address_expr
->X_add_number
& 0xf800000) >> 7)
1984 | ((address_expr
->X_add_number
& 0x3fffc) >> 2));
1987 case BFD_RELOC_16_PCREL
:
1988 ip
->insn_opcode
|= address_expr
->X_add_number
& 0xffff;
1991 case BFD_RELOC_16_PCREL_S2
:
2001 /* Don't generate a reloc if we are writing into a variant frag. */
2004 fixp
[0] = fix_new_exp (frag_now
, f
- frag_now
->fr_literal
, 4,
2006 (*reloc_type
== BFD_RELOC_16_PCREL
2007 || *reloc_type
== BFD_RELOC_16_PCREL_S2
),
2010 /* These relocations can have an addend that won't fit in
2011 4 octets for 64bit assembly. */
2012 if (HAVE_64BIT_GPRS
&&
2013 (*reloc_type
== BFD_RELOC_16
2014 || *reloc_type
== BFD_RELOC_32
2015 || *reloc_type
== BFD_RELOC_MIPS_JMP
2016 || *reloc_type
== BFD_RELOC_HI16_S
2017 || *reloc_type
== BFD_RELOC_LO16
2018 || *reloc_type
== BFD_RELOC_GPREL16
2019 || *reloc_type
== BFD_RELOC_MIPS_LITERAL
2020 || *reloc_type
== BFD_RELOC_GPREL32
2021 || *reloc_type
== BFD_RELOC_64
2022 || *reloc_type
== BFD_RELOC_CTOR
2023 || *reloc_type
== BFD_RELOC_MIPS_SUB
2024 || *reloc_type
== BFD_RELOC_MIPS_HIGHEST
2025 || *reloc_type
== BFD_RELOC_MIPS_HIGHER
2026 || *reloc_type
== BFD_RELOC_MIPS_SCN_DISP
2027 || *reloc_type
== BFD_RELOC_MIPS_REL16
2028 || *reloc_type
== BFD_RELOC_MIPS_RELGOT
))
2029 fixp
[0]->fx_no_overflow
= 1;
2033 struct mips_hi_fixup
*hi_fixup
;
2035 assert (*reloc_type
== BFD_RELOC_HI16_S
);
2036 hi_fixup
= ((struct mips_hi_fixup
*)
2037 xmalloc (sizeof (struct mips_hi_fixup
)));
2038 hi_fixup
->fixp
= fixp
[0];
2039 hi_fixup
->seg
= now_seg
;
2040 hi_fixup
->next
= mips_hi_fixup_list
;
2041 mips_hi_fixup_list
= hi_fixup
;
2044 if (reloc_type
[1] != BFD_RELOC_UNUSED
)
2046 /* FIXME: This symbol can be one of
2047 RSS_UNDEF, RSS_GP, RSS_GP0, RSS_LOC. */
2048 address_expr
->X_op
= O_absent
;
2049 address_expr
->X_add_symbol
= 0;
2050 address_expr
->X_add_number
= 0;
2052 fixp
[1] = fix_new_exp (frag_now
, f
- frag_now
->fr_literal
,
2053 4, address_expr
, false,
2056 /* These relocations can have an addend that won't fit in
2057 4 octets for 64bit assembly. */
2058 if (HAVE_64BIT_GPRS
&&
2059 (*reloc_type
== BFD_RELOC_16
2060 || *reloc_type
== BFD_RELOC_32
2061 || *reloc_type
== BFD_RELOC_MIPS_JMP
2062 || *reloc_type
== BFD_RELOC_HI16_S
2063 || *reloc_type
== BFD_RELOC_LO16
2064 || *reloc_type
== BFD_RELOC_GPREL16
2065 || *reloc_type
== BFD_RELOC_MIPS_LITERAL
2066 || *reloc_type
== BFD_RELOC_GPREL32
2067 || *reloc_type
== BFD_RELOC_64
2068 || *reloc_type
== BFD_RELOC_CTOR
2069 || *reloc_type
== BFD_RELOC_MIPS_SUB
2070 || *reloc_type
== BFD_RELOC_MIPS_HIGHEST
2071 || *reloc_type
== BFD_RELOC_MIPS_HIGHER
2072 || *reloc_type
== BFD_RELOC_MIPS_SCN_DISP
2073 || *reloc_type
== BFD_RELOC_MIPS_REL16
2074 || *reloc_type
== BFD_RELOC_MIPS_RELGOT
))
2075 fixp
[1]->fx_no_overflow
= 1;
2077 if (reloc_type
[2] != BFD_RELOC_UNUSED
)
2079 address_expr
->X_op
= O_absent
;
2080 address_expr
->X_add_symbol
= 0;
2081 address_expr
->X_add_number
= 0;
2083 fixp
[2] = fix_new_exp (frag_now
,
2084 f
- frag_now
->fr_literal
, 4,
2085 address_expr
, false,
2088 /* These relocations can have an addend that won't fit in
2089 4 octets for 64bit assembly. */
2090 if (HAVE_64BIT_GPRS
&&
2091 (*reloc_type
== BFD_RELOC_16
2092 || *reloc_type
== BFD_RELOC_32
2093 || *reloc_type
== BFD_RELOC_MIPS_JMP
2094 || *reloc_type
== BFD_RELOC_HI16_S
2095 || *reloc_type
== BFD_RELOC_LO16
2096 || *reloc_type
== BFD_RELOC_GPREL16
2097 || *reloc_type
== BFD_RELOC_MIPS_LITERAL
2098 || *reloc_type
== BFD_RELOC_GPREL32
2099 || *reloc_type
== BFD_RELOC_64
2100 || *reloc_type
== BFD_RELOC_CTOR
2101 || *reloc_type
== BFD_RELOC_MIPS_SUB
2102 || *reloc_type
== BFD_RELOC_MIPS_HIGHEST
2103 || *reloc_type
== BFD_RELOC_MIPS_HIGHER
2104 || *reloc_type
== BFD_RELOC_MIPS_SCN_DISP
2105 || *reloc_type
== BFD_RELOC_MIPS_REL16
2106 || *reloc_type
== BFD_RELOC_MIPS_RELGOT
))
2107 fixp
[2]->fx_no_overflow
= 1;
2114 if (! mips_opts
.mips16
)
2115 md_number_to_chars (f
, ip
->insn_opcode
, 4);
2116 else if (*reloc_type
== BFD_RELOC_MIPS16_JMP
)
2118 md_number_to_chars (f
, ip
->insn_opcode
>> 16, 2);
2119 md_number_to_chars (f
+ 2, ip
->insn_opcode
& 0xffff, 2);
2125 md_number_to_chars (f
, 0xf000 | ip
->extend
, 2);
2128 md_number_to_chars (f
, ip
->insn_opcode
, 2);
2131 /* Update the register mask information. */
2132 if (! mips_opts
.mips16
)
2134 if (pinfo
& INSN_WRITE_GPR_D
)
2135 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
);
2136 if ((pinfo
& (INSN_WRITE_GPR_T
| INSN_READ_GPR_T
)) != 0)
2137 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
);
2138 if (pinfo
& INSN_READ_GPR_S
)
2139 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> OP_SH_RS
) & OP_MASK_RS
);
2140 if (pinfo
& INSN_WRITE_GPR_31
)
2141 mips_gprmask
|= 1 << 31;
2142 if (pinfo
& INSN_WRITE_FPR_D
)
2143 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FD
) & OP_MASK_FD
);
2144 if ((pinfo
& (INSN_WRITE_FPR_S
| INSN_READ_FPR_S
)) != 0)
2145 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FS
) & OP_MASK_FS
);
2146 if ((pinfo
& (INSN_WRITE_FPR_T
| INSN_READ_FPR_T
)) != 0)
2147 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FT
) & OP_MASK_FT
);
2148 if ((pinfo
& INSN_READ_FPR_R
) != 0)
2149 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FR
) & OP_MASK_FR
);
2150 if (pinfo
& INSN_COP
)
2152 /* We don't keep enough information to sort these cases out.
2153 The itbl support does keep this information however, although
2154 we currently don't support itbl fprmats as part of the cop
2155 instruction. May want to add this support in the future. */
2157 /* Never set the bit for $0, which is always zero. */
2158 mips_gprmask
&= ~1 << 0;
2162 if (pinfo
& (MIPS16_INSN_WRITE_X
| MIPS16_INSN_READ_X
))
2163 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_RX
)
2164 & MIPS16OP_MASK_RX
);
2165 if (pinfo
& (MIPS16_INSN_WRITE_Y
| MIPS16_INSN_READ_Y
))
2166 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_RY
)
2167 & MIPS16OP_MASK_RY
);
2168 if (pinfo
& MIPS16_INSN_WRITE_Z
)
2169 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_RZ
)
2170 & MIPS16OP_MASK_RZ
);
2171 if (pinfo
& (MIPS16_INSN_WRITE_T
| MIPS16_INSN_READ_T
))
2172 mips_gprmask
|= 1 << TREG
;
2173 if (pinfo
& (MIPS16_INSN_WRITE_SP
| MIPS16_INSN_READ_SP
))
2174 mips_gprmask
|= 1 << SP
;
2175 if (pinfo
& (MIPS16_INSN_WRITE_31
| MIPS16_INSN_READ_31
))
2176 mips_gprmask
|= 1 << RA
;
2177 if (pinfo
& MIPS16_INSN_WRITE_GPR_Y
)
2178 mips_gprmask
|= 1 << MIPS16OP_EXTRACT_REG32R (ip
->insn_opcode
);
2179 if (pinfo
& MIPS16_INSN_READ_Z
)
2180 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_MOVE32Z
)
2181 & MIPS16OP_MASK_MOVE32Z
);
2182 if (pinfo
& MIPS16_INSN_READ_GPR_X
)
2183 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_REGR32
)
2184 & MIPS16OP_MASK_REGR32
);
2187 if (place
== NULL
&& ! mips_opts
.noreorder
)
2189 /* Filling the branch delay slot is more complex. We try to
2190 switch the branch with the previous instruction, which we can
2191 do if the previous instruction does not set up a condition
2192 that the branch tests and if the branch is not itself the
2193 target of any branch. */
2194 if ((pinfo
& INSN_UNCOND_BRANCH_DELAY
)
2195 || (pinfo
& INSN_COND_BRANCH_DELAY
))
2197 if (mips_optimize
< 2
2198 /* If we have seen .set volatile or .set nomove, don't
2200 || mips_opts
.nomove
!= 0
2201 /* If we had to emit any NOP instructions, then we
2202 already know we can not swap. */
2204 /* If we don't even know the previous insn, we can not
2206 || ! prev_insn_valid
2207 /* If the previous insn is already in a branch delay
2208 slot, then we can not swap. */
2209 || prev_insn_is_delay_slot
2210 /* If the previous previous insn was in a .set
2211 noreorder, we can't swap. Actually, the MIPS
2212 assembler will swap in this situation. However, gcc
2213 configured -with-gnu-as will generate code like
2219 in which we can not swap the bne and INSN. If gcc is
2220 not configured -with-gnu-as, it does not output the
2221 .set pseudo-ops. We don't have to check
2222 prev_insn_unreordered, because prev_insn_valid will
2223 be 0 in that case. We don't want to use
2224 prev_prev_insn_valid, because we do want to be able
2225 to swap at the start of a function. */
2226 || prev_prev_insn_unreordered
2227 /* If the branch is itself the target of a branch, we
2228 can not swap. We cheat on this; all we check for is
2229 whether there is a label on this instruction. If
2230 there are any branches to anything other than a
2231 label, users must use .set noreorder. */
2232 || insn_labels
!= NULL
2233 /* If the previous instruction is in a variant frag, we
2234 can not do the swap. This does not apply to the
2235 mips16, which uses variant frags for different
2237 || (! mips_opts
.mips16
2238 && prev_insn_frag
->fr_type
== rs_machine_dependent
)
2239 /* If the branch reads the condition codes, we don't
2240 even try to swap, because in the sequence
2245 we can not swap, and I don't feel like handling that
2247 || (! mips_opts
.mips16
2248 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
2249 && (pinfo
& INSN_READ_COND_CODE
))
2250 /* We can not swap with an instruction that requires a
2251 delay slot, becase the target of the branch might
2252 interfere with that instruction. */
2253 || (! mips_opts
.mips16
2254 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
2256 /* Itbl support may require additional care here. */
2257 & (INSN_LOAD_COPROC_DELAY
2258 | INSN_COPROC_MOVE_DELAY
2259 | INSN_WRITE_COND_CODE
)))
2260 || (! (hilo_interlocks
2261 || (mips_tune
== CPU_R3900
&& (pinfo
& INSN_MULT
)))
2265 || (! mips_opts
.mips16
2267 && (prev_pinfo
& INSN_LOAD_MEMORY_DELAY
))
2268 || (! mips_opts
.mips16
2269 && mips_opts
.isa
== ISA_MIPS1
2270 /* Itbl support may require additional care here. */
2271 && (prev_pinfo
& INSN_COPROC_MEMORY_DELAY
))
2272 /* We can not swap with a branch instruction. */
2274 & (INSN_UNCOND_BRANCH_DELAY
2275 | INSN_COND_BRANCH_DELAY
2276 | INSN_COND_BRANCH_LIKELY
))
2277 /* We do not swap with a trap instruction, since it
2278 complicates trap handlers to have the trap
2279 instruction be in a delay slot. */
2280 || (prev_pinfo
& INSN_TRAP
)
2281 /* If the branch reads a register that the previous
2282 instruction sets, we can not swap. */
2283 || (! mips_opts
.mips16
2284 && (prev_pinfo
& INSN_WRITE_GPR_T
)
2285 && insn_uses_reg (ip
,
2286 ((prev_insn
.insn_opcode
>> OP_SH_RT
)
2289 || (! mips_opts
.mips16
2290 && (prev_pinfo
& INSN_WRITE_GPR_D
)
2291 && insn_uses_reg (ip
,
2292 ((prev_insn
.insn_opcode
>> OP_SH_RD
)
2295 || (mips_opts
.mips16
2296 && (((prev_pinfo
& MIPS16_INSN_WRITE_X
)
2297 && insn_uses_reg (ip
,
2298 ((prev_insn
.insn_opcode
2300 & MIPS16OP_MASK_RX
),
2302 || ((prev_pinfo
& MIPS16_INSN_WRITE_Y
)
2303 && insn_uses_reg (ip
,
2304 ((prev_insn
.insn_opcode
2306 & MIPS16OP_MASK_RY
),
2308 || ((prev_pinfo
& MIPS16_INSN_WRITE_Z
)
2309 && insn_uses_reg (ip
,
2310 ((prev_insn
.insn_opcode
2312 & MIPS16OP_MASK_RZ
),
2314 || ((prev_pinfo
& MIPS16_INSN_WRITE_T
)
2315 && insn_uses_reg (ip
, TREG
, MIPS_GR_REG
))
2316 || ((prev_pinfo
& MIPS16_INSN_WRITE_31
)
2317 && insn_uses_reg (ip
, RA
, MIPS_GR_REG
))
2318 || ((prev_pinfo
& MIPS16_INSN_WRITE_GPR_Y
)
2319 && insn_uses_reg (ip
,
2320 MIPS16OP_EXTRACT_REG32R (prev_insn
.
2323 /* If the branch writes a register that the previous
2324 instruction sets, we can not swap (we know that
2325 branches write only to RD or to $31). */
2326 || (! mips_opts
.mips16
2327 && (prev_pinfo
& INSN_WRITE_GPR_T
)
2328 && (((pinfo
& INSN_WRITE_GPR_D
)
2329 && (((prev_insn
.insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
)
2330 == ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)))
2331 || ((pinfo
& INSN_WRITE_GPR_31
)
2332 && (((prev_insn
.insn_opcode
>> OP_SH_RT
)
2335 || (! mips_opts
.mips16
2336 && (prev_pinfo
& INSN_WRITE_GPR_D
)
2337 && (((pinfo
& INSN_WRITE_GPR_D
)
2338 && (((prev_insn
.insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)
2339 == ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)))
2340 || ((pinfo
& INSN_WRITE_GPR_31
)
2341 && (((prev_insn
.insn_opcode
>> OP_SH_RD
)
2344 || (mips_opts
.mips16
2345 && (pinfo
& MIPS16_INSN_WRITE_31
)
2346 && ((prev_pinfo
& MIPS16_INSN_WRITE_31
)
2347 || ((prev_pinfo
& MIPS16_INSN_WRITE_GPR_Y
)
2348 && (MIPS16OP_EXTRACT_REG32R (prev_insn
.insn_opcode
)
2350 /* If the branch writes a register that the previous
2351 instruction reads, we can not swap (we know that
2352 branches only write to RD or to $31). */
2353 || (! mips_opts
.mips16
2354 && (pinfo
& INSN_WRITE_GPR_D
)
2355 && insn_uses_reg (&prev_insn
,
2356 ((ip
->insn_opcode
>> OP_SH_RD
)
2359 || (! mips_opts
.mips16
2360 && (pinfo
& INSN_WRITE_GPR_31
)
2361 && insn_uses_reg (&prev_insn
, 31, MIPS_GR_REG
))
2362 || (mips_opts
.mips16
2363 && (pinfo
& MIPS16_INSN_WRITE_31
)
2364 && insn_uses_reg (&prev_insn
, RA
, MIPS_GR_REG
))
2365 /* If we are generating embedded PIC code, the branch
2366 might be expanded into a sequence which uses $at, so
2367 we can't swap with an instruction which reads it. */
2368 || (mips_pic
== EMBEDDED_PIC
2369 && insn_uses_reg (&prev_insn
, AT
, MIPS_GR_REG
))
2370 /* If the previous previous instruction has a load
2371 delay, and sets a register that the branch reads, we
2373 || (! mips_opts
.mips16
2374 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
2375 /* Itbl support may require additional care here. */
2376 && ((prev_prev_insn
.insn_mo
->pinfo
& INSN_LOAD_COPROC_DELAY
)
2377 || (! gpr_interlocks
2378 && (prev_prev_insn
.insn_mo
->pinfo
2379 & INSN_LOAD_MEMORY_DELAY
)))
2380 && insn_uses_reg (ip
,
2381 ((prev_prev_insn
.insn_opcode
>> OP_SH_RT
)
2384 /* If one instruction sets a condition code and the
2385 other one uses a condition code, we can not swap. */
2386 || ((pinfo
& INSN_READ_COND_CODE
)
2387 && (prev_pinfo
& INSN_WRITE_COND_CODE
))
2388 || ((pinfo
& INSN_WRITE_COND_CODE
)
2389 && (prev_pinfo
& INSN_READ_COND_CODE
))
2390 /* If the previous instruction uses the PC, we can not
2392 || (mips_opts
.mips16
2393 && (prev_pinfo
& MIPS16_INSN_READ_PC
))
2394 /* If the previous instruction was extended, we can not
2396 || (mips_opts
.mips16
&& prev_insn_extended
)
2397 /* If the previous instruction had a fixup in mips16
2398 mode, we can not swap. This normally means that the
2399 previous instruction was a 4 byte branch anyhow. */
2400 || (mips_opts
.mips16
&& prev_insn_fixp
[0])
2401 /* If the previous instruction is a sync, sync.l, or
2402 sync.p, we can not swap. */
2403 || (prev_pinfo
& INSN_SYNC
))
2405 /* We could do even better for unconditional branches to
2406 portions of this object file; we could pick up the
2407 instruction at the destination, put it in the delay
2408 slot, and bump the destination address. */
2410 /* Update the previous insn information. */
2411 prev_prev_insn
= *ip
;
2412 prev_insn
.insn_mo
= &dummy_opcode
;
2416 /* It looks like we can actually do the swap. */
2417 if (! mips_opts
.mips16
)
2422 prev_f
= prev_insn_frag
->fr_literal
+ prev_insn_where
;
2423 memcpy (temp
, prev_f
, 4);
2424 memcpy (prev_f
, f
, 4);
2425 memcpy (f
, temp
, 4);
2426 if (prev_insn_fixp
[0])
2428 prev_insn_fixp
[0]->fx_frag
= frag_now
;
2429 prev_insn_fixp
[0]->fx_where
= f
- frag_now
->fr_literal
;
2431 if (prev_insn_fixp
[1])
2433 prev_insn_fixp
[1]->fx_frag
= frag_now
;
2434 prev_insn_fixp
[1]->fx_where
= f
- frag_now
->fr_literal
;
2436 if (prev_insn_fixp
[2])
2438 prev_insn_fixp
[2]->fx_frag
= frag_now
;
2439 prev_insn_fixp
[2]->fx_where
= f
- frag_now
->fr_literal
;
2443 fixp
[0]->fx_frag
= prev_insn_frag
;
2444 fixp
[0]->fx_where
= prev_insn_where
;
2448 fixp
[1]->fx_frag
= prev_insn_frag
;
2449 fixp
[1]->fx_where
= prev_insn_where
;
2453 fixp
[2]->fx_frag
= prev_insn_frag
;
2454 fixp
[2]->fx_where
= prev_insn_where
;
2462 assert (prev_insn_fixp
[0] == NULL
);
2463 assert (prev_insn_fixp
[1] == NULL
);
2464 assert (prev_insn_fixp
[2] == NULL
);
2465 prev_f
= prev_insn_frag
->fr_literal
+ prev_insn_where
;
2466 memcpy (temp
, prev_f
, 2);
2467 memcpy (prev_f
, f
, 2);
2468 if (*reloc_type
!= BFD_RELOC_MIPS16_JMP
)
2470 assert (*reloc_type
== BFD_RELOC_UNUSED
);
2471 memcpy (f
, temp
, 2);
2475 memcpy (f
, f
+ 2, 2);
2476 memcpy (f
+ 2, temp
, 2);
2480 fixp
[0]->fx_frag
= prev_insn_frag
;
2481 fixp
[0]->fx_where
= prev_insn_where
;
2485 fixp
[1]->fx_frag
= prev_insn_frag
;
2486 fixp
[1]->fx_where
= prev_insn_where
;
2490 fixp
[2]->fx_frag
= prev_insn_frag
;
2491 fixp
[2]->fx_where
= prev_insn_where
;
2495 /* Update the previous insn information; leave prev_insn
2497 prev_prev_insn
= *ip
;
2499 prev_insn_is_delay_slot
= 1;
2501 /* If that was an unconditional branch, forget the previous
2502 insn information. */
2503 if (pinfo
& INSN_UNCOND_BRANCH_DELAY
)
2505 prev_prev_insn
.insn_mo
= &dummy_opcode
;
2506 prev_insn
.insn_mo
= &dummy_opcode
;
2509 prev_insn_fixp
[0] = NULL
;
2510 prev_insn_fixp
[1] = NULL
;
2511 prev_insn_fixp
[2] = NULL
;
2512 prev_insn_reloc_type
[0] = BFD_RELOC_UNUSED
;
2513 prev_insn_reloc_type
[1] = BFD_RELOC_UNUSED
;
2514 prev_insn_reloc_type
[2] = BFD_RELOC_UNUSED
;
2515 prev_insn_extended
= 0;
2517 else if (pinfo
& INSN_COND_BRANCH_LIKELY
)
2519 /* We don't yet optimize a branch likely. What we should do
2520 is look at the target, copy the instruction found there
2521 into the delay slot, and increment the branch to jump to
2522 the next instruction. */
2524 /* Update the previous insn information. */
2525 prev_prev_insn
= *ip
;
2526 prev_insn
.insn_mo
= &dummy_opcode
;
2527 prev_insn_fixp
[0] = NULL
;
2528 prev_insn_fixp
[1] = NULL
;
2529 prev_insn_fixp
[2] = NULL
;
2530 prev_insn_reloc_type
[0] = BFD_RELOC_UNUSED
;
2531 prev_insn_reloc_type
[1] = BFD_RELOC_UNUSED
;
2532 prev_insn_reloc_type
[2] = BFD_RELOC_UNUSED
;
2533 prev_insn_extended
= 0;
2537 /* Update the previous insn information. */
2539 prev_prev_insn
.insn_mo
= &dummy_opcode
;
2541 prev_prev_insn
= prev_insn
;
2544 /* Any time we see a branch, we always fill the delay slot
2545 immediately; since this insn is not a branch, we know it
2546 is not in a delay slot. */
2547 prev_insn_is_delay_slot
= 0;
2549 prev_insn_fixp
[0] = fixp
[0];
2550 prev_insn_fixp
[1] = fixp
[1];
2551 prev_insn_fixp
[2] = fixp
[2];
2552 prev_insn_reloc_type
[0] = reloc_type
[0];
2553 prev_insn_reloc_type
[1] = reloc_type
[1];
2554 prev_insn_reloc_type
[2] = reloc_type
[2];
2555 if (mips_opts
.mips16
)
2556 prev_insn_extended
= (ip
->use_extend
2557 || *reloc_type
> BFD_RELOC_UNUSED
);
2560 prev_prev_insn_unreordered
= prev_insn_unreordered
;
2561 prev_insn_unreordered
= 0;
2562 prev_insn_frag
= frag_now
;
2563 prev_insn_where
= f
- frag_now
->fr_literal
;
2564 prev_insn_valid
= 1;
2566 else if (place
== NULL
)
2568 /* We need to record a bit of information even when we are not
2569 reordering, in order to determine the base address for mips16
2570 PC relative relocs. */
2571 prev_prev_insn
= prev_insn
;
2573 prev_insn_reloc_type
[0] = reloc_type
[0];
2574 prev_insn_reloc_type
[1] = reloc_type
[1];
2575 prev_insn_reloc_type
[2] = reloc_type
[2];
2576 prev_prev_insn_unreordered
= prev_insn_unreordered
;
2577 prev_insn_unreordered
= 1;
2580 /* We just output an insn, so the next one doesn't have a label. */
2581 mips_clear_insn_labels ();
2583 /* We must ensure that a fixup associated with an unmatched %hi
2584 reloc does not become a variant frag. Otherwise, the
2585 rearrangement of %hi relocs in frob_file may confuse
2589 frag_wane (frag_now
);
2594 /* This function forgets that there was any previous instruction or
2595 label. If PRESERVE is non-zero, it remembers enough information to
2596 know whether nops are needed before a noreorder section. */
2599 mips_no_prev_insn (preserve
)
2604 prev_insn
.insn_mo
= &dummy_opcode
;
2605 prev_prev_insn
.insn_mo
= &dummy_opcode
;
2606 prev_nop_frag
= NULL
;
2607 prev_nop_frag_holds
= 0;
2608 prev_nop_frag_required
= 0;
2609 prev_nop_frag_since
= 0;
2611 prev_insn_valid
= 0;
2612 prev_insn_is_delay_slot
= 0;
2613 prev_insn_unreordered
= 0;
2614 prev_insn_extended
= 0;
2615 prev_insn_reloc_type
[0] = BFD_RELOC_UNUSED
;
2616 prev_insn_reloc_type
[1] = BFD_RELOC_UNUSED
;
2617 prev_insn_reloc_type
[2] = BFD_RELOC_UNUSED
;
2618 prev_prev_insn_unreordered
= 0;
2619 mips_clear_insn_labels ();
2622 /* This function must be called whenever we turn on noreorder or emit
2623 something other than instructions. It inserts any NOPS which might
2624 be needed by the previous instruction, and clears the information
2625 kept for the previous instructions. The INSNS parameter is true if
2626 instructions are to follow. */
2629 mips_emit_delays (insns
)
2632 if (! mips_opts
.noreorder
)
2637 if ((! mips_opts
.mips16
2638 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
2639 && (! cop_interlocks
2640 && (prev_insn
.insn_mo
->pinfo
2641 & (INSN_LOAD_COPROC_DELAY
2642 | INSN_COPROC_MOVE_DELAY
2643 | INSN_WRITE_COND_CODE
))))
2644 || (! hilo_interlocks
2645 && (prev_insn
.insn_mo
->pinfo
2648 || (! mips_opts
.mips16
2650 && (prev_insn
.insn_mo
->pinfo
2651 & INSN_LOAD_MEMORY_DELAY
))
2652 || (! mips_opts
.mips16
2653 && mips_opts
.isa
== ISA_MIPS1
2654 && (prev_insn
.insn_mo
->pinfo
2655 & INSN_COPROC_MEMORY_DELAY
)))
2657 /* Itbl support may require additional care here. */
2659 if ((! mips_opts
.mips16
2660 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
2661 && (! cop_interlocks
2662 && prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
))
2663 || (! hilo_interlocks
2664 && ((prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
2665 || (prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
))))
2668 if (prev_insn_unreordered
)
2671 else if ((! mips_opts
.mips16
2672 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
2673 && (! cop_interlocks
2674 && prev_prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
))
2675 || (! hilo_interlocks
2676 && ((prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
2677 || (prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
))))
2679 /* Itbl support may require additional care here. */
2680 if (! prev_prev_insn_unreordered
)
2686 struct insn_label_list
*l
;
2690 /* Record the frag which holds the nop instructions, so
2691 that we can remove them if we don't need them. */
2692 frag_grow (mips_opts
.mips16
? nops
* 2 : nops
* 4);
2693 prev_nop_frag
= frag_now
;
2694 prev_nop_frag_holds
= nops
;
2695 prev_nop_frag_required
= 0;
2696 prev_nop_frag_since
= 0;
2699 for (; nops
> 0; --nops
)
2704 /* Move on to a new frag, so that it is safe to simply
2705 decrease the size of prev_nop_frag. */
2706 frag_wane (frag_now
);
2710 for (l
= insn_labels
; l
!= NULL
; l
= l
->next
)
2714 assert (S_GET_SEGMENT (l
->label
) == now_seg
);
2715 symbol_set_frag (l
->label
, frag_now
);
2716 val
= (valueT
) frag_now_fix ();
2717 /* mips16 text labels are stored as odd. */
2718 if (mips_opts
.mips16
)
2720 S_SET_VALUE (l
->label
, val
);
2725 /* Mark instruction labels in mips16 mode. */
2726 if (mips_opts
.mips16
&& insns
)
2727 mips16_mark_labels ();
2729 mips_no_prev_insn (insns
);
2732 /* Build an instruction created by a macro expansion. This is passed
2733 a pointer to the count of instructions created so far, an
2734 expression, the name of the instruction to build, an operand format
2735 string, and corresponding arguments. */
2739 macro_build (char *place
,
2747 macro_build (place
, counter
, ep
, name
, fmt
, va_alist
)
2756 struct mips_cl_insn insn
;
2757 bfd_reloc_code_real_type r
[3];
2761 va_start (args
, fmt
);
2767 * If the macro is about to expand into a second instruction,
2768 * print a warning if needed. We need to pass ip as a parameter
2769 * to generate a better warning message here...
2771 if (mips_opts
.warn_about_macros
&& place
== NULL
&& *counter
== 1)
2772 as_warn (_("Macro instruction expanded into multiple instructions"));
2775 *counter
+= 1; /* bump instruction counter */
2777 if (mips_opts
.mips16
)
2779 mips16_macro_build (place
, counter
, ep
, name
, fmt
, args
);
2784 r
[0] = BFD_RELOC_UNUSED
;
2785 r
[1] = BFD_RELOC_UNUSED
;
2786 r
[2] = BFD_RELOC_UNUSED
;
2787 insn
.insn_mo
= (struct mips_opcode
*) hash_find (op_hash
, name
);
2788 assert (insn
.insn_mo
);
2789 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
2791 /* Search until we get a match for NAME. */
2794 if (strcmp (fmt
, insn
.insn_mo
->args
) == 0
2795 && insn
.insn_mo
->pinfo
!= INSN_MACRO
2796 && OPCODE_IS_MEMBER (insn
.insn_mo
, mips_opts
.isa
, mips_arch
)
2797 && (mips_arch
!= CPU_R4650
|| (insn
.insn_mo
->pinfo
& FP_D
) == 0))
2801 assert (insn
.insn_mo
->name
);
2802 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
2805 insn
.insn_opcode
= insn
.insn_mo
->match
;
2821 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_RT
;
2825 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_CODE
;
2830 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_FT
;
2835 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_RD
;
2840 int tmp
= va_arg (args
, int);
2842 insn
.insn_opcode
|= tmp
<< OP_SH_RT
;
2843 insn
.insn_opcode
|= tmp
<< OP_SH_RD
;
2849 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_FS
;
2856 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_SHAMT
;
2860 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_FD
;
2864 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_CODE20
;
2868 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_CODE19
;
2872 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_CODE2
;
2879 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_RS
;
2885 *r
= (bfd_reloc_code_real_type
) va_arg (args
, int);
2886 assert (*r
== BFD_RELOC_MIPS_GPREL
2887 || *r
== BFD_RELOC_MIPS_LITERAL
2888 || *r
== BFD_RELOC_MIPS_HIGHER
2889 || *r
== BFD_RELOC_HI16_S
2890 || *r
== BFD_RELOC_LO16
2891 || *r
== BFD_RELOC_MIPS_GOT16
2892 || *r
== BFD_RELOC_MIPS_CALL16
2893 || *r
== BFD_RELOC_MIPS_GOT_LO16
2894 || *r
== BFD_RELOC_MIPS_CALL_LO16
2895 || (ep
->X_op
== O_subtract
2896 && *r
== BFD_RELOC_PCREL_LO16
));
2900 *r
= (bfd_reloc_code_real_type
) va_arg (args
, int);
2902 && (ep
->X_op
== O_constant
2903 || (ep
->X_op
== O_symbol
2904 && (*r
== BFD_RELOC_MIPS_HIGHEST
2905 || *r
== BFD_RELOC_HI16_S
2906 || *r
== BFD_RELOC_HI16
2907 || *r
== BFD_RELOC_GPREL16
2908 || *r
== BFD_RELOC_MIPS_GOT_HI16
2909 || *r
== BFD_RELOC_MIPS_CALL_HI16
))
2910 || (ep
->X_op
== O_subtract
2911 && *r
== BFD_RELOC_PCREL_HI16_S
)));
2915 assert (ep
!= NULL
);
2917 * This allows macro() to pass an immediate expression for
2918 * creating short branches without creating a symbol.
2919 * Note that the expression still might come from the assembly
2920 * input, in which case the value is not checked for range nor
2921 * is a relocation entry generated (yuck).
2923 if (ep
->X_op
== O_constant
)
2925 insn
.insn_opcode
|= (ep
->X_add_number
>> 2) & 0xffff;
2929 if (mips_pic
== EMBEDDED_PIC
)
2930 *r
= BFD_RELOC_16_PCREL_S2
;
2932 *r
= BFD_RELOC_16_PCREL
;
2936 assert (ep
!= NULL
);
2937 *r
= BFD_RELOC_MIPS_JMP
;
2941 insn
.insn_opcode
|= va_arg (args
, unsigned long);
2950 assert (*r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
2952 append_insn (place
, &insn
, ep
, r
, false);
2956 mips16_macro_build (place
, counter
, ep
, name
, fmt
, args
)
2958 int *counter ATTRIBUTE_UNUSED
;
2964 struct mips_cl_insn insn
;
2965 bfd_reloc_code_real_type r
[3]
2966 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
2968 insn
.insn_mo
= (struct mips_opcode
*) hash_find (mips16_op_hash
, name
);
2969 assert (insn
.insn_mo
);
2970 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
2972 while (strcmp (fmt
, insn
.insn_mo
->args
) != 0
2973 || insn
.insn_mo
->pinfo
== INSN_MACRO
)
2976 assert (insn
.insn_mo
->name
);
2977 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
2980 insn
.insn_opcode
= insn
.insn_mo
->match
;
2981 insn
.use_extend
= false;
3000 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_RY
;
3005 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_RX
;
3009 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_RZ
;
3013 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_MOVE32Z
;
3023 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_REGR32
;
3030 regno
= va_arg (args
, int);
3031 regno
= ((regno
& 7) << 2) | ((regno
& 0x18) >> 3);
3032 insn
.insn_opcode
|= regno
<< MIPS16OP_SH_REG32R
;
3053 assert (ep
!= NULL
);
3055 if (ep
->X_op
!= O_constant
)
3056 *r
= BFD_RELOC_UNUSED
+ c
;
3059 mips16_immed (NULL
, 0, c
, ep
->X_add_number
, false, false,
3060 false, &insn
.insn_opcode
, &insn
.use_extend
,
3063 *r
= BFD_RELOC_UNUSED
;
3069 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_IMM6
;
3076 assert (*r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
3078 append_insn (place
, &insn
, ep
, r
, false);
3082 * Generate a "lui" instruction.
3085 macro_build_lui (place
, counter
, ep
, regnum
)
3091 expressionS high_expr
;
3092 struct mips_cl_insn insn
;
3093 bfd_reloc_code_real_type r
[3]
3094 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
3095 CONST
char *name
= "lui";
3096 CONST
char *fmt
= "t,u";
3098 assert (! mips_opts
.mips16
);
3104 high_expr
.X_op
= O_constant
;
3105 high_expr
.X_add_number
= ep
->X_add_number
;
3108 if (high_expr
.X_op
== O_constant
)
3110 /* we can compute the instruction now without a relocation entry */
3111 high_expr
.X_add_number
= ((high_expr
.X_add_number
+ 0x8000)
3113 *r
= BFD_RELOC_UNUSED
;
3115 else if (! HAVE_NEWABI
)
3117 assert (ep
->X_op
== O_symbol
);
3118 /* _gp_disp is a special case, used from s_cpload. */
3119 assert (mips_pic
== NO_PIC
3120 || strcmp (S_GET_NAME (ep
->X_add_symbol
), "_gp_disp") == 0);
3121 *r
= BFD_RELOC_HI16_S
;
3125 * If the macro is about to expand into a second instruction,
3126 * print a warning if needed. We need to pass ip as a parameter
3127 * to generate a better warning message here...
3129 if (mips_opts
.warn_about_macros
&& place
== NULL
&& *counter
== 1)
3130 as_warn (_("Macro instruction expanded into multiple instructions"));
3133 *counter
+= 1; /* bump instruction counter */
3135 insn
.insn_mo
= (struct mips_opcode
*) hash_find (op_hash
, name
);
3136 assert (insn
.insn_mo
);
3137 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
3138 assert (strcmp (fmt
, insn
.insn_mo
->args
) == 0);
3140 insn
.insn_opcode
= insn
.insn_mo
->match
| (regnum
<< OP_SH_RT
);
3141 if (*r
== BFD_RELOC_UNUSED
)
3143 insn
.insn_opcode
|= high_expr
.X_add_number
;
3144 append_insn (place
, &insn
, NULL
, r
, false);
3147 append_insn (place
, &insn
, &high_expr
, r
, false);
3151 * Generates code to set the $at register to true (one)
3152 * if reg is less than the immediate expression.
3155 set_at (counter
, reg
, unsignedp
)
3160 if (imm_expr
.X_op
== O_constant
3161 && imm_expr
.X_add_number
>= -0x8000
3162 && imm_expr
.X_add_number
< 0x8000)
3163 macro_build ((char *) NULL
, counter
, &imm_expr
,
3164 unsignedp
? "sltiu" : "slti",
3165 "t,r,j", AT
, reg
, (int) BFD_RELOC_LO16
);
3168 load_register (counter
, AT
, &imm_expr
, 0);
3169 macro_build ((char *) NULL
, counter
, (expressionS
*) NULL
,
3170 unsignedp
? "sltu" : "slt",
3171 "d,v,t", AT
, reg
, AT
);
3175 /* Warn if an expression is not a constant. */
3178 check_absolute_expr (ip
, ex
)
3179 struct mips_cl_insn
*ip
;
3182 if (ex
->X_op
== O_big
)
3183 as_bad (_("unsupported large constant"));
3184 else if (ex
->X_op
!= O_constant
)
3185 as_bad (_("Instruction %s requires absolute expression"), ip
->insn_mo
->name
);
3188 /* Count the leading zeroes by performing a binary chop. This is a
3189 bulky bit of source, but performance is a LOT better for the
3190 majority of values than a simple loop to count the bits:
3191 for (lcnt = 0; (lcnt < 32); lcnt++)
3192 if ((v) & (1 << (31 - lcnt)))
3194 However it is not code size friendly, and the gain will drop a bit
3195 on certain cached systems.
3197 #define COUNT_TOP_ZEROES(v) \
3198 (((v) & ~0xffff) == 0 \
3199 ? ((v) & ~0xff) == 0 \
3200 ? ((v) & ~0xf) == 0 \
3201 ? ((v) & ~0x3) == 0 \
3202 ? ((v) & ~0x1) == 0 \
3207 : ((v) & ~0x7) == 0 \
3210 : ((v) & ~0x3f) == 0 \
3211 ? ((v) & ~0x1f) == 0 \
3214 : ((v) & ~0x7f) == 0 \
3217 : ((v) & ~0xfff) == 0 \
3218 ? ((v) & ~0x3ff) == 0 \
3219 ? ((v) & ~0x1ff) == 0 \
3222 : ((v) & ~0x7ff) == 0 \
3225 : ((v) & ~0x3fff) == 0 \
3226 ? ((v) & ~0x1fff) == 0 \
3229 : ((v) & ~0x7fff) == 0 \
3232 : ((v) & ~0xffffff) == 0 \
3233 ? ((v) & ~0xfffff) == 0 \
3234 ? ((v) & ~0x3ffff) == 0 \
3235 ? ((v) & ~0x1ffff) == 0 \
3238 : ((v) & ~0x7ffff) == 0 \
3241 : ((v) & ~0x3fffff) == 0 \
3242 ? ((v) & ~0x1fffff) == 0 \
3245 : ((v) & ~0x7fffff) == 0 \
3248 : ((v) & ~0xfffffff) == 0 \
3249 ? ((v) & ~0x3ffffff) == 0 \
3250 ? ((v) & ~0x1ffffff) == 0 \
3253 : ((v) & ~0x7ffffff) == 0 \
3256 : ((v) & ~0x3fffffff) == 0 \
3257 ? ((v) & ~0x1fffffff) == 0 \
3260 : ((v) & ~0x7fffffff) == 0 \
3265 * This routine generates the least number of instructions neccessary to load
3266 * an absolute expression value into a register.
3269 load_register (counter
, reg
, ep
, dbl
)
3276 expressionS hi32
, lo32
;
3278 if (ep
->X_op
!= O_big
)
3280 assert (ep
->X_op
== O_constant
);
3281 if (ep
->X_add_number
< 0x8000
3282 && (ep
->X_add_number
>= 0
3283 || (ep
->X_add_number
>= -0x8000
3286 || sizeof (ep
->X_add_number
) > 4))))
3288 /* We can handle 16 bit signed values with an addiu to
3289 $zero. No need to ever use daddiu here, since $zero and
3290 the result are always correct in 32 bit mode. */
3291 macro_build ((char *) NULL
, counter
, ep
, "addiu", "t,r,j", reg
, 0,
3292 (int) BFD_RELOC_LO16
);
3295 else if (ep
->X_add_number
>= 0 && ep
->X_add_number
< 0x10000)
3297 /* We can handle 16 bit unsigned values with an ori to
3299 macro_build ((char *) NULL
, counter
, ep
, "ori", "t,r,i", reg
, 0,
3300 (int) BFD_RELOC_LO16
);
3303 else if ((((ep
->X_add_number
&~ (offsetT
) 0x7fffffff) == 0
3304 || ((ep
->X_add_number
&~ (offsetT
) 0x7fffffff)
3305 == ~ (offsetT
) 0x7fffffff))
3308 || sizeof (ep
->X_add_number
) > 4
3309 || (ep
->X_add_number
& 0x80000000) == 0))
3310 || ((HAVE_32BIT_GPRS
|| ! dbl
)
3311 && (ep
->X_add_number
&~ (offsetT
) 0xffffffff) == 0)
3314 && ((ep
->X_add_number
&~ (offsetT
) 0xffffffff)
3315 == ~ (offsetT
) 0xffffffff)))
3317 /* 32 bit values require an lui. */
3318 macro_build ((char *) NULL
, counter
, ep
, "lui", "t,u", reg
,
3319 (int) BFD_RELOC_HI16
);
3320 if ((ep
->X_add_number
& 0xffff) != 0)
3321 macro_build ((char *) NULL
, counter
, ep
, "ori", "t,r,i", reg
, reg
,
3322 (int) BFD_RELOC_LO16
);
3327 /* The value is larger than 32 bits. */
3329 if (HAVE_32BIT_GPRS
)
3331 as_bad (_("Number larger than 32 bits"));
3332 macro_build ((char *) NULL
, counter
, ep
, "addiu", "t,r,j", reg
, 0,
3333 (int) BFD_RELOC_LO16
);
3337 if (ep
->X_op
!= O_big
)
3340 hi32
.X_add_number
= (valueT
) hi32
.X_add_number
>> 16;
3341 hi32
.X_add_number
= (valueT
) hi32
.X_add_number
>> 16;
3342 hi32
.X_add_number
&= 0xffffffff;
3344 lo32
.X_add_number
&= 0xffffffff;
3348 assert (ep
->X_add_number
> 2);
3349 if (ep
->X_add_number
== 3)
3350 generic_bignum
[3] = 0;
3351 else if (ep
->X_add_number
> 4)
3352 as_bad (_("Number larger than 64 bits"));
3353 lo32
.X_op
= O_constant
;
3354 lo32
.X_add_number
= generic_bignum
[0] + (generic_bignum
[1] << 16);
3355 hi32
.X_op
= O_constant
;
3356 hi32
.X_add_number
= generic_bignum
[2] + (generic_bignum
[3] << 16);
3359 if (hi32
.X_add_number
== 0)
3364 unsigned long hi
, lo
;
3366 if (hi32
.X_add_number
== 0xffffffff)
3368 if ((lo32
.X_add_number
& 0xffff8000) == 0xffff8000)
3370 macro_build ((char *) NULL
, counter
, &lo32
, "addiu", "t,r,j",
3371 reg
, 0, (int) BFD_RELOC_LO16
);
3374 if (lo32
.X_add_number
& 0x80000000)
3376 macro_build ((char *) NULL
, counter
, &lo32
, "lui", "t,u", reg
,
3377 (int) BFD_RELOC_HI16
);
3378 if (lo32
.X_add_number
& 0xffff)
3379 macro_build ((char *) NULL
, counter
, &lo32
, "ori", "t,r,i",
3380 reg
, reg
, (int) BFD_RELOC_LO16
);
3385 /* Check for 16bit shifted constant. We know that hi32 is
3386 non-zero, so start the mask on the first bit of the hi32
3391 unsigned long himask
, lomask
;
3395 himask
= 0xffff >> (32 - shift
);
3396 lomask
= (0xffff << shift
) & 0xffffffff;
3400 himask
= 0xffff << (shift
- 32);
3403 if ((hi32
.X_add_number
& ~(offsetT
) himask
) == 0
3404 && (lo32
.X_add_number
& ~(offsetT
) lomask
) == 0)
3408 tmp
.X_op
= O_constant
;
3410 tmp
.X_add_number
= ((hi32
.X_add_number
<< (32 - shift
))
3411 | (lo32
.X_add_number
>> shift
));
3413 tmp
.X_add_number
= hi32
.X_add_number
>> (shift
- 32);
3414 macro_build ((char *) NULL
, counter
, &tmp
,
3415 "ori", "t,r,i", reg
, 0,
3416 (int) BFD_RELOC_LO16
);
3417 macro_build ((char *) NULL
, counter
, (expressionS
*) NULL
,
3418 (shift
>= 32) ? "dsll32" : "dsll",
3420 (shift
>= 32) ? shift
- 32 : shift
);
3425 while (shift
<= (64 - 16));
3427 /* Find the bit number of the lowest one bit, and store the
3428 shifted value in hi/lo. */
3429 hi
= (unsigned long) (hi32
.X_add_number
& 0xffffffff);
3430 lo
= (unsigned long) (lo32
.X_add_number
& 0xffffffff);
3434 while ((lo
& 1) == 0)
3439 lo
|= (hi
& (((unsigned long) 1 << bit
) - 1)) << (32 - bit
);
3445 while ((hi
& 1) == 0)
3454 /* Optimize if the shifted value is a (power of 2) - 1. */
3455 if ((hi
== 0 && ((lo
+ 1) & lo
) == 0)
3456 || (lo
== 0xffffffff && ((hi
+ 1) & hi
) == 0))
3458 shift
= COUNT_TOP_ZEROES ((unsigned int) hi32
.X_add_number
);
3463 /* This instruction will set the register to be all
3465 tmp
.X_op
= O_constant
;
3466 tmp
.X_add_number
= (offsetT
) -1;
3467 macro_build ((char *) NULL
, counter
, &tmp
, "addiu", "t,r,j",
3468 reg
, 0, (int) BFD_RELOC_LO16
);
3472 macro_build ((char *) NULL
, counter
, (expressionS
*) NULL
,
3473 (bit
>= 32) ? "dsll32" : "dsll",
3475 (bit
>= 32) ? bit
- 32 : bit
);
3477 macro_build ((char *) NULL
, counter
, (expressionS
*) NULL
,
3478 (shift
>= 32) ? "dsrl32" : "dsrl",
3480 (shift
>= 32) ? shift
- 32 : shift
);
3485 /* Sign extend hi32 before calling load_register, because we can
3486 generally get better code when we load a sign extended value. */
3487 if ((hi32
.X_add_number
& 0x80000000) != 0)
3488 hi32
.X_add_number
|= ~(offsetT
) 0xffffffff;
3489 load_register (counter
, reg
, &hi32
, 0);
3492 if ((lo32
.X_add_number
& 0xffff0000) == 0)
3496 macro_build ((char *) NULL
, counter
, (expressionS
*) NULL
,
3497 "dsll32", "d,w,<", reg
, freg
, 0);
3505 if ((freg
== 0) && (lo32
.X_add_number
== 0xffffffff))
3507 macro_build ((char *) NULL
, counter
, &lo32
, "lui", "t,u", reg
,
3508 (int) BFD_RELOC_HI16
);
3509 macro_build ((char *) NULL
, counter
, NULL
, "dsrl32", "d,w,<", reg
,
3516 macro_build ((char *) NULL
, counter
, NULL
, "dsll", "d,w,<", reg
,
3521 mid16
.X_add_number
>>= 16;
3522 macro_build ((char *) NULL
, counter
, &mid16
, "ori", "t,r,i", reg
,
3523 freg
, (int) BFD_RELOC_LO16
);
3524 macro_build ((char *) NULL
, counter
, NULL
, "dsll", "d,w,<", reg
,
3528 if ((lo32
.X_add_number
& 0xffff) != 0)
3529 macro_build ((char *) NULL
, counter
, &lo32
, "ori", "t,r,i", reg
, freg
,
3530 (int) BFD_RELOC_LO16
);
3533 /* Load an address into a register. */
3536 load_address (counter
, reg
, ep
, dbl
, used_at
)
3545 if (ep
->X_op
!= O_constant
3546 && ep
->X_op
!= O_symbol
)
3548 as_bad (_("expression too complex"));
3549 ep
->X_op
= O_constant
;
3552 if (ep
->X_op
== O_constant
)
3554 load_register (counter
, reg
, ep
, dbl
);
3558 if (mips_pic
== NO_PIC
)
3560 /* If this is a reference to a GP relative symbol, we want
3561 addiu $reg,$gp,<sym> (BFD_RELOC_MIPS_GPREL)
3563 lui $reg,<sym> (BFD_RELOC_HI16_S)
3564 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
3565 If we have an addend, we always use the latter form.
3567 With 64bit address space and a usable $at we want
3568 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
3569 lui $at,<sym> (BFD_RELOC_HI16_S)
3570 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
3571 daddiu $at,<sym> (BFD_RELOC_LO16)
3575 If $at is already in use, we use an path which is suboptimal
3576 on superscalar processors.
3577 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
3578 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
3580 daddiu $reg,<sym> (BFD_RELOC_HI16_S)
3582 daddiu $reg,<sym> (BFD_RELOC_LO16)
3584 if (HAVE_64BIT_ADDRESSES
)
3588 /* We don't do GP optimization for now because RELAX_ENCODE can't
3589 hold the data for such large chunks. */
3593 macro_build (p
, counter
, ep
, "lui", "t,u",
3594 reg
, (int) BFD_RELOC_MIPS_HIGHEST
);
3595 macro_build (p
, counter
, ep
, "lui", "t,u",
3596 AT
, (int) BFD_RELOC_HI16_S
);
3597 macro_build (p
, counter
, ep
, "daddiu", "t,r,j",
3598 reg
, reg
, (int) BFD_RELOC_MIPS_HIGHER
);
3599 macro_build (p
, counter
, ep
, "daddiu", "t,r,j",
3600 AT
, AT
, (int) BFD_RELOC_LO16
);
3601 macro_build (p
, counter
, (expressionS
*) NULL
, "dsll32",
3602 "d,w,<", reg
, reg
, 0);
3603 macro_build (p
, counter
, (expressionS
*) NULL
, "dadd",
3604 "d,v,t", reg
, reg
, AT
);
3609 macro_build (p
, counter
, ep
, "lui", "t,u",
3610 reg
, (int) BFD_RELOC_MIPS_HIGHEST
);
3611 macro_build (p
, counter
, ep
, "daddiu", "t,r,j",
3612 reg
, reg
, (int) BFD_RELOC_MIPS_HIGHER
);
3613 macro_build (p
, counter
, (expressionS
*) NULL
, "dsll",
3614 "d,w,<", reg
, reg
, 16);
3615 macro_build (p
, counter
, ep
, "daddiu", "t,r,j",
3616 reg
, reg
, (int) BFD_RELOC_HI16_S
);
3617 macro_build (p
, counter
, (expressionS
*) NULL
, "dsll",
3618 "d,w,<", reg
, reg
, 16);
3619 macro_build (p
, counter
, ep
, "daddiu", "t,r,j",
3620 reg
, reg
, (int) BFD_RELOC_LO16
);
3626 if ((valueT
) ep
->X_add_number
<= MAX_GPREL_OFFSET
3627 && ! nopic_need_relax (ep
->X_add_symbol
, 1))
3630 macro_build ((char *) NULL
, counter
, ep
,
3631 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
3632 "t,r,j", reg
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
3633 p
= frag_var (rs_machine_dependent
, 8, 0,
3634 RELAX_ENCODE (4, 8, 0, 4, 0,
3635 mips_opts
.warn_about_macros
),
3636 ep
->X_add_symbol
, (offsetT
) 0, (char *) NULL
);
3638 macro_build_lui (p
, counter
, ep
, reg
);
3641 macro_build (p
, counter
, ep
,
3642 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
3643 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
3646 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
3650 /* If this is a reference to an external symbol, we want
3651 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3653 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3655 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
3656 If there is a constant, it must be added in after. */
3657 ex
.X_add_number
= ep
->X_add_number
;
3658 ep
->X_add_number
= 0;
3660 macro_build ((char *) NULL
, counter
, ep
,
3661 HAVE_32BIT_ADDRESSES
? "lw" : "ld",
3662 "t,o(b)", reg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
3663 macro_build ((char *) NULL
, counter
, (expressionS
*) NULL
, "nop", "");
3664 p
= frag_var (rs_machine_dependent
, 4, 0,
3665 RELAX_ENCODE (0, 4, -8, 0, 0, mips_opts
.warn_about_macros
),
3666 ep
->X_add_symbol
, (offsetT
) 0, (char *) NULL
);
3667 macro_build (p
, counter
, ep
,
3668 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
3669 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
3670 if (ex
.X_add_number
!= 0)
3672 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
3673 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
3674 ex
.X_op
= O_constant
;
3675 macro_build ((char *) NULL
, counter
, &ex
,
3676 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
3677 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
3680 else if (mips_pic
== SVR4_PIC
)
3685 /* This is the large GOT case. If this is a reference to an
3686 external symbol, we want
3687 lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
3689 lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16)
3690 Otherwise, for a reference to a local symbol, we want
3691 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3693 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
3694 If there is a constant, it must be added in after. */
3695 ex
.X_add_number
= ep
->X_add_number
;
3696 ep
->X_add_number
= 0;
3697 if (reg_needs_delay (GP
))
3702 macro_build ((char *) NULL
, counter
, ep
, "lui", "t,u", reg
,
3703 (int) BFD_RELOC_MIPS_GOT_HI16
);
3704 macro_build ((char *) NULL
, counter
, (expressionS
*) NULL
,
3705 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
3706 "d,v,t", reg
, reg
, GP
);
3707 macro_build ((char *) NULL
, counter
, ep
,
3708 HAVE_32BIT_ADDRESSES
? "lw" : "ld",
3709 "t,o(b)", reg
, (int) BFD_RELOC_MIPS_GOT_LO16
, reg
);
3710 p
= frag_var (rs_machine_dependent
, 12 + off
, 0,
3711 RELAX_ENCODE (12, 12 + off
, off
, 8 + off
, 0,
3712 mips_opts
.warn_about_macros
),
3713 ep
->X_add_symbol
, (offsetT
) 0, (char *) NULL
);
3716 /* We need a nop before loading from $gp. This special
3717 check is required because the lui which starts the main
3718 instruction stream does not refer to $gp, and so will not
3719 insert the nop which may be required. */
3720 macro_build (p
, counter
, (expressionS
*) NULL
, "nop", "");
3723 macro_build (p
, counter
, ep
, HAVE_32BIT_ADDRESSES
? "lw" : "ld",
3724 "t,o(b)", reg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
3726 macro_build (p
, counter
, (expressionS
*) NULL
, "nop", "");
3728 macro_build (p
, counter
, ep
, HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
3729 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
3730 if (ex
.X_add_number
!= 0)
3732 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
3733 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
3734 ex
.X_op
= O_constant
;
3735 macro_build ((char *) NULL
, counter
, &ex
,
3736 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
3737 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
3740 else if (mips_pic
== EMBEDDED_PIC
)
3743 addiu $reg,$gp,<sym> (BFD_RELOC_MIPS_GPREL)
3745 macro_build ((char *) NULL
, counter
, ep
,
3746 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
3747 "t,r,j", reg
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
3753 /* Move the contents of register SOURCE into register DEST. */
3756 move_register (counter
, dest
, source
)
3761 macro_build ((char *) NULL
, counter
, (expressionS
*) NULL
,
3762 HAVE_32BIT_GPRS
? "addu" : "daddu",
3763 "d,v,t", dest
, source
, 0);
3768 * This routine implements the seemingly endless macro or synthesized
3769 * instructions and addressing modes in the mips assembly language. Many
3770 * of these macros are simple and are similar to each other. These could
3771 * probably be handled by some kind of table or grammer aproach instead of
3772 * this verbose method. Others are not simple macros but are more like
3773 * optimizing code generation.
3774 * One interesting optimization is when several store macros appear
3775 * consecutivly that would load AT with the upper half of the same address.
3776 * The ensuing load upper instructions are ommited. This implies some kind
3777 * of global optimization. We currently only optimize within a single macro.
3778 * For many of the load and store macros if the address is specified as a
3779 * constant expression in the first 64k of memory (ie ld $2,0x4000c) we
3780 * first load register 'at' with zero and use it as the base register. The
3781 * mips assembler simply uses register $zero. Just one tiny optimization
3786 struct mips_cl_insn
*ip
;
3788 register int treg
, sreg
, dreg
, breg
;
3804 bfd_reloc_code_real_type r
;
3806 int hold_mips_optimize
;
3808 assert (! mips_opts
.mips16
);
3810 treg
= (ip
->insn_opcode
>> 16) & 0x1f;
3811 dreg
= (ip
->insn_opcode
>> 11) & 0x1f;
3812 sreg
= breg
= (ip
->insn_opcode
>> 21) & 0x1f;
3813 mask
= ip
->insn_mo
->mask
;
3815 expr1
.X_op
= O_constant
;
3816 expr1
.X_op_symbol
= NULL
;
3817 expr1
.X_add_symbol
= NULL
;
3818 expr1
.X_add_number
= 1;
3830 mips_emit_delays (true);
3831 ++mips_opts
.noreorder
;
3832 mips_any_noreorder
= 1;
3834 expr1
.X_add_number
= 8;
3835 macro_build ((char *) NULL
, &icnt
, &expr1
, "bgez", "s,p", sreg
);
3837 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "",
3840 move_register (&icnt
, dreg
, sreg
);
3841 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3842 dbl
? "dsub" : "sub", "d,v,t", dreg
, 0, sreg
);
3844 --mips_opts
.noreorder
;
3865 if (imm_expr
.X_op
== O_constant
3866 && imm_expr
.X_add_number
>= -0x8000
3867 && imm_expr
.X_add_number
< 0x8000)
3869 macro_build ((char *) NULL
, &icnt
, &imm_expr
, s
, "t,r,j", treg
, sreg
,
3870 (int) BFD_RELOC_LO16
);
3873 load_register (&icnt
, AT
, &imm_expr
, dbl
);
3874 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s2
, "d,v,t",
3894 if (imm_expr
.X_op
== O_constant
3895 && imm_expr
.X_add_number
>= 0
3896 && imm_expr
.X_add_number
< 0x10000)
3898 if (mask
!= M_NOR_I
)
3899 macro_build ((char *) NULL
, &icnt
, &imm_expr
, s
, "t,r,i", treg
,
3900 sreg
, (int) BFD_RELOC_LO16
);
3903 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "ori", "t,r,i",
3904 treg
, sreg
, (int) BFD_RELOC_LO16
);
3905 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nor",
3906 "d,v,t", treg
, treg
, 0);
3911 load_register (&icnt
, AT
, &imm_expr
, HAVE_64BIT_GPRS
);
3912 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s2
, "d,v,t",
3930 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
3932 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "s,t,p", sreg
,
3936 load_register (&icnt
, AT
, &imm_expr
, 0);
3937 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "s,t,p", sreg
, AT
);
3945 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3946 likely
? "bgezl" : "bgez", "s,p", sreg
);
3951 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3952 likely
? "blezl" : "blez", "s,p", treg
);
3955 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "slt", "d,v,t",
3957 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3958 likely
? "beql" : "beq", "s,t,p", AT
, 0);
3964 /* check for > max integer */
3965 maxnum
= 0x7fffffff;
3966 if (HAVE_64BIT_GPRS
&& sizeof (maxnum
) > 4)
3973 if (imm_expr
.X_op
== O_constant
3974 && imm_expr
.X_add_number
>= maxnum
3975 && (HAVE_32BIT_GPRS
|| sizeof (maxnum
) > 4))
3978 /* result is always false */
3982 as_warn (_("Branch %s is always false (nop)"),
3984 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop",
3990 as_warn (_("Branch likely %s is always false"),
3992 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "bnel",
3997 if (imm_expr
.X_op
!= O_constant
)
3998 as_bad (_("Unsupported large constant"));
3999 imm_expr
.X_add_number
++;
4003 if (mask
== M_BGEL_I
)
4005 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
4007 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4008 likely
? "bgezl" : "bgez", "s,p", sreg
);
4011 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
4013 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4014 likely
? "bgtzl" : "bgtz", "s,p", sreg
);
4017 maxnum
= 0x7fffffff;
4018 if (HAVE_64BIT_GPRS
&& sizeof (maxnum
) > 4)
4025 maxnum
= - maxnum
- 1;
4026 if (imm_expr
.X_op
== O_constant
4027 && imm_expr
.X_add_number
<= maxnum
4028 && (HAVE_32BIT_GPRS
|| sizeof (maxnum
) > 4))
4031 /* result is always true */
4032 as_warn (_("Branch %s is always true"), ip
->insn_mo
->name
);
4033 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "b", "p");
4036 set_at (&icnt
, sreg
, 0);
4037 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4038 likely
? "beql" : "beq", "s,t,p", AT
, 0);
4048 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4049 likely
? "beql" : "beq", "s,t,p", 0, treg
);
4052 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "sltu",
4053 "d,v,t", AT
, sreg
, treg
);
4054 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4055 likely
? "beql" : "beq", "s,t,p", AT
, 0);
4063 && imm_expr
.X_op
== O_constant
4064 && imm_expr
.X_add_number
== 0xffffffff))
4066 if (imm_expr
.X_op
!= O_constant
)
4067 as_bad (_("Unsupported large constant"));
4068 imm_expr
.X_add_number
++;
4072 if (mask
== M_BGEUL_I
)
4074 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
4076 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
4078 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4079 likely
? "bnel" : "bne", "s,t,p", sreg
, 0);
4082 set_at (&icnt
, sreg
, 1);
4083 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4084 likely
? "beql" : "beq", "s,t,p", AT
, 0);
4092 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4093 likely
? "bgtzl" : "bgtz", "s,p", sreg
);
4098 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4099 likely
? "bltzl" : "bltz", "s,p", treg
);
4102 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "slt", "d,v,t",
4104 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4105 likely
? "bnel" : "bne", "s,t,p", AT
, 0);
4113 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4114 likely
? "bnel" : "bne", "s,t,p", sreg
, 0);
4119 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "sltu",
4120 "d,v,t", AT
, treg
, sreg
);
4121 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4122 likely
? "bnel" : "bne", "s,t,p", AT
, 0);
4130 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4131 likely
? "blezl" : "blez", "s,p", sreg
);
4136 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4137 likely
? "bgezl" : "bgez", "s,p", treg
);
4140 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "slt", "d,v,t",
4142 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4143 likely
? "beql" : "beq", "s,t,p", AT
, 0);
4149 maxnum
= 0x7fffffff;
4150 if (HAVE_64BIT_GPRS
&& sizeof (maxnum
) > 4)
4157 if (imm_expr
.X_op
== O_constant
4158 && imm_expr
.X_add_number
>= maxnum
4159 && (HAVE_32BIT_GPRS
|| sizeof (maxnum
) > 4))
4161 if (imm_expr
.X_op
!= O_constant
)
4162 as_bad (_("Unsupported large constant"));
4163 imm_expr
.X_add_number
++;
4167 if (mask
== M_BLTL_I
)
4169 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
4171 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4172 likely
? "bltzl" : "bltz", "s,p", sreg
);
4175 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
4177 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4178 likely
? "blezl" : "blez", "s,p", sreg
);
4181 set_at (&icnt
, sreg
, 0);
4182 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4183 likely
? "bnel" : "bne", "s,t,p", AT
, 0);
4191 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4192 likely
? "beql" : "beq", "s,t,p", sreg
, 0);
4197 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "sltu",
4198 "d,v,t", AT
, treg
, sreg
);
4199 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4200 likely
? "beql" : "beq", "s,t,p", AT
, 0);
4208 && imm_expr
.X_op
== O_constant
4209 && imm_expr
.X_add_number
== 0xffffffff))
4211 if (imm_expr
.X_op
!= O_constant
)
4212 as_bad (_("Unsupported large constant"));
4213 imm_expr
.X_add_number
++;
4217 if (mask
== M_BLTUL_I
)
4219 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
4221 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
4223 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4224 likely
? "beql" : "beq",
4228 set_at (&icnt
, sreg
, 1);
4229 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4230 likely
? "bnel" : "bne", "s,t,p", AT
, 0);
4238 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4239 likely
? "bltzl" : "bltz", "s,p", sreg
);
4244 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4245 likely
? "bgtzl" : "bgtz", "s,p", treg
);
4248 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "slt", "d,v,t",
4250 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4251 likely
? "bnel" : "bne", "s,t,p", AT
, 0);
4261 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4262 likely
? "bnel" : "bne", "s,t,p", 0, treg
);
4265 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "sltu",
4268 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4269 likely
? "bnel" : "bne", "s,t,p", AT
, 0);
4284 as_warn (_("Divide by zero."));
4286 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "teq",
4289 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "break",
4294 mips_emit_delays (true);
4295 ++mips_opts
.noreorder
;
4296 mips_any_noreorder
= 1;
4299 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "teq",
4301 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4302 dbl
? "ddiv" : "div", "z,s,t", sreg
, treg
);
4306 expr1
.X_add_number
= 8;
4307 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", treg
, 0);
4308 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4309 dbl
? "ddiv" : "div", "z,s,t", sreg
, treg
);
4310 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "break",
4313 expr1
.X_add_number
= -1;
4314 macro_build ((char *) NULL
, &icnt
, &expr1
,
4315 dbl
? "daddiu" : "addiu",
4316 "t,r,j", AT
, 0, (int) BFD_RELOC_LO16
);
4317 expr1
.X_add_number
= mips_trap
? (dbl
? 12 : 8) : (dbl
? 20 : 16);
4318 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", treg
, AT
);
4321 expr1
.X_add_number
= 1;
4322 macro_build ((char *) NULL
, &icnt
, &expr1
, "daddiu", "t,r,j", AT
, 0,
4323 (int) BFD_RELOC_LO16
);
4324 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "dsll32",
4325 "d,w,<", AT
, AT
, 31);
4329 expr1
.X_add_number
= 0x80000000;
4330 macro_build ((char *) NULL
, &icnt
, &expr1
, "lui", "t,u", AT
,
4331 (int) BFD_RELOC_HI16
);
4335 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "teq",
4337 /* We want to close the noreorder block as soon as possible, so
4338 that later insns are available for delay slot filling. */
4339 --mips_opts
.noreorder
;
4343 expr1
.X_add_number
= 8;
4344 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", sreg
, AT
);
4345 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "",
4348 /* We want to close the noreorder block as soon as possible, so
4349 that later insns are available for delay slot filling. */
4350 --mips_opts
.noreorder
;
4352 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "break",
4355 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s
, "d", dreg
);
4394 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
4396 as_warn (_("Divide by zero."));
4398 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "teq",
4401 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "break",
4405 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
4407 if (strcmp (s2
, "mflo") == 0)
4408 move_register (&icnt
, dreg
, sreg
);
4410 move_register (&icnt
, dreg
, 0);
4413 if (imm_expr
.X_op
== O_constant
4414 && imm_expr
.X_add_number
== -1
4415 && s
[strlen (s
) - 1] != 'u')
4417 if (strcmp (s2
, "mflo") == 0)
4419 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4420 dbl
? "dneg" : "neg", "d,w", dreg
, sreg
);
4423 move_register (&icnt
, dreg
, 0);
4427 load_register (&icnt
, AT
, &imm_expr
, dbl
);
4428 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s
, "z,s,t",
4430 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s2
, "d", dreg
);
4449 mips_emit_delays (true);
4450 ++mips_opts
.noreorder
;
4451 mips_any_noreorder
= 1;
4454 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "teq",
4456 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s
, "z,s,t",
4458 /* We want to close the noreorder block as soon as possible, so
4459 that later insns are available for delay slot filling. */
4460 --mips_opts
.noreorder
;
4464 expr1
.X_add_number
= 8;
4465 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", treg
, 0);
4466 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s
, "z,s,t",
4469 /* We want to close the noreorder block as soon as possible, so
4470 that later insns are available for delay slot filling. */
4471 --mips_opts
.noreorder
;
4472 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "break",
4475 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s2
, "d", dreg
);
4481 /* Load the address of a symbol into a register. If breg is not
4482 zero, we then add a base register to it. */
4495 /* When generating embedded PIC code, we permit expressions of
4498 la $treg,foo-bar($breg)
4499 where bar is an address in the current section. These are used
4500 when getting the addresses of functions. We don't permit
4501 X_add_number to be non-zero, because if the symbol is
4502 external the relaxing code needs to know that any addend is
4503 purely the offset to X_op_symbol. */
4504 if (mips_pic
== EMBEDDED_PIC
4505 && offset_expr
.X_op
== O_subtract
4506 && (symbol_constant_p (offset_expr
.X_op_symbol
)
4507 ? S_GET_SEGMENT (offset_expr
.X_op_symbol
) == now_seg
4508 : (symbol_equated_p (offset_expr
.X_op_symbol
)
4510 (symbol_get_value_expression (offset_expr
.X_op_symbol
)
4513 && (offset_expr
.X_add_number
== 0
4514 || OUTPUT_FLAVOR
== bfd_target_elf_flavour
))
4520 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
4521 tempreg
, (int) BFD_RELOC_PCREL_HI16_S
);
4525 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
4526 tempreg
, (int) BFD_RELOC_PCREL_HI16_S
);
4527 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4528 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
4529 "d,v,t", tempreg
, tempreg
, breg
);
4531 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4532 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
4533 "t,r,j", treg
, tempreg
, (int) BFD_RELOC_PCREL_LO16
);
4539 if (offset_expr
.X_op
!= O_symbol
4540 && offset_expr
.X_op
!= O_constant
)
4542 as_bad (_("expression too complex"));
4543 offset_expr
.X_op
= O_constant
;
4546 if (offset_expr
.X_op
== O_constant
)
4547 load_register (&icnt
, tempreg
, &offset_expr
, dbl
);
4548 else if (mips_pic
== NO_PIC
)
4550 /* If this is a reference to a GP relative symbol, we want
4551 addiu $tempreg,$gp,<sym> (BFD_RELOC_MIPS_GPREL)
4553 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
4554 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
4555 If we have a constant, we need two instructions anyhow,
4556 so we may as well always use the latter form.
4558 With 64bit address space and a usable $at we want
4559 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
4560 lui $at,<sym> (BFD_RELOC_HI16_S)
4561 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
4562 daddiu $at,<sym> (BFD_RELOC_LO16)
4564 dadd $tempreg,$tempreg,$at
4566 If $at is already in use, we use an path which is suboptimal
4567 on superscalar processors.
4568 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
4569 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
4571 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
4573 daddiu $tempreg,<sym> (BFD_RELOC_LO16)
4576 if (HAVE_64BIT_ADDRESSES
)
4578 /* We don't do GP optimization for now because RELAX_ENCODE can't
4579 hold the data for such large chunks. */
4583 macro_build (p
, &icnt
, &offset_expr
, "lui", "t,u",
4584 tempreg
, (int) BFD_RELOC_MIPS_HIGHEST
);
4585 macro_build (p
, &icnt
, &offset_expr
, "lui", "t,u",
4586 AT
, (int) BFD_RELOC_HI16_S
);
4587 macro_build (p
, &icnt
, &offset_expr
, "daddiu", "t,r,j",
4588 tempreg
, tempreg
, (int) BFD_RELOC_MIPS_HIGHER
);
4589 macro_build (p
, &icnt
, &offset_expr
, "daddiu", "t,r,j",
4590 AT
, AT
, (int) BFD_RELOC_LO16
);
4591 macro_build (p
, &icnt
, (expressionS
*) NULL
, "dsll32",
4592 "d,w,<", tempreg
, tempreg
, 0);
4593 macro_build (p
, &icnt
, (expressionS
*) NULL
, "dadd", "d,v,t",
4594 tempreg
, tempreg
, AT
);
4599 macro_build (p
, &icnt
, &offset_expr
, "lui", "t,u",
4600 tempreg
, (int) BFD_RELOC_MIPS_HIGHEST
);
4601 macro_build (p
, &icnt
, &offset_expr
, "daddiu", "t,r,j",
4602 tempreg
, tempreg
, (int) BFD_RELOC_MIPS_HIGHER
);
4603 macro_build (p
, &icnt
, (expressionS
*) NULL
, "dsll", "d,w,<",
4604 tempreg
, tempreg
, 16);
4605 macro_build (p
, &icnt
, &offset_expr
, "daddiu", "t,r,j",
4606 tempreg
, tempreg
, (int) BFD_RELOC_HI16_S
);
4607 macro_build (p
, &icnt
, (expressionS
*) NULL
, "dsll", "d,w,<",
4608 tempreg
, tempreg
, 16);
4609 macro_build (p
, &icnt
, &offset_expr
, "daddiu", "t,r,j",
4610 tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
4615 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
4616 && ! nopic_need_relax (offset_expr
.X_add_symbol
, 1))
4619 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4620 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
4621 "t,r,j", tempreg
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
4622 p
= frag_var (rs_machine_dependent
, 8, 0,
4623 RELAX_ENCODE (4, 8, 0, 4, 0,
4624 mips_opts
.warn_about_macros
),
4625 offset_expr
.X_add_symbol
, (offsetT
) 0,
4628 macro_build_lui (p
, &icnt
, &offset_expr
, tempreg
);
4631 macro_build (p
, &icnt
, &offset_expr
,
4632 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
4633 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
4636 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
4638 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT16
;
4640 /* If this is a reference to an external symbol, and there
4641 is no constant, we want
4642 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4643 or if tempreg is PIC_CALL_REG
4644 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
4645 For a local symbol, we want
4646 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4648 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
4650 If we have a small constant, and this is a reference to
4651 an external symbol, we want
4652 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4654 addiu $tempreg,$tempreg,<constant>
4655 For a local symbol, we want the same instruction
4656 sequence, but we output a BFD_RELOC_LO16 reloc on the
4659 If we have a large constant, and this is a reference to
4660 an external symbol, we want
4661 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4662 lui $at,<hiconstant>
4663 addiu $at,$at,<loconstant>
4664 addu $tempreg,$tempreg,$at
4665 For a local symbol, we want the same instruction
4666 sequence, but we output a BFD_RELOC_LO16 reloc on the
4667 addiu instruction. */
4668 expr1
.X_add_number
= offset_expr
.X_add_number
;
4669 offset_expr
.X_add_number
= 0;
4671 if (expr1
.X_add_number
== 0 && tempreg
== PIC_CALL_REG
)
4672 lw_reloc_type
= (int) BFD_RELOC_MIPS_CALL16
;
4673 macro_build ((char *) NULL
, &icnt
, &offset_expr
, dbl
? "ld" : "lw",
4674 "t,o(b)", tempreg
, lw_reloc_type
, GP
);
4675 if (expr1
.X_add_number
== 0)
4683 /* We're going to put in an addu instruction using
4684 tempreg, so we may as well insert the nop right
4686 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4690 p
= frag_var (rs_machine_dependent
, 8 - off
, 0,
4691 RELAX_ENCODE (0, 8 - off
, -4 - off
, 4 - off
, 0,
4693 ? mips_opts
.warn_about_macros
4695 offset_expr
.X_add_symbol
, 0, NULL
);
4698 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4701 macro_build (p
, &icnt
, &expr1
,
4702 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
4703 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
4704 /* FIXME: If breg == 0, and the next instruction uses
4705 $tempreg, then if this variant case is used an extra
4706 nop will be generated. */
4708 else if (expr1
.X_add_number
>= -0x8000
4709 && expr1
.X_add_number
< 0x8000)
4711 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4713 macro_build ((char *) NULL
, &icnt
, &expr1
,
4714 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
4715 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
4716 frag_var (rs_machine_dependent
, 0, 0,
4717 RELAX_ENCODE (0, 0, -12, -4, 0, 0),
4718 offset_expr
.X_add_symbol
, 0, NULL
);
4724 /* If we are going to add in a base register, and the
4725 target register and the base register are the same,
4726 then we are using AT as a temporary register. Since
4727 we want to load the constant into AT, we add our
4728 current AT (from the global offset table) and the
4729 register into the register now, and pretend we were
4730 not using a base register. */
4735 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4737 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4738 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
4739 "d,v,t", treg
, AT
, breg
);
4745 /* Set mips_optimize around the lui instruction to avoid
4746 inserting an unnecessary nop after the lw. */
4747 hold_mips_optimize
= mips_optimize
;
4749 macro_build_lui (NULL
, &icnt
, &expr1
, AT
);
4750 mips_optimize
= hold_mips_optimize
;
4752 macro_build ((char *) NULL
, &icnt
, &expr1
,
4753 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
4754 "t,r,j", AT
, AT
, (int) BFD_RELOC_LO16
);
4755 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4756 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
4757 "d,v,t", tempreg
, tempreg
, AT
);
4758 frag_var (rs_machine_dependent
, 0, 0,
4759 RELAX_ENCODE (0, 0, -16 + off1
, -8, 0, 0),
4760 offset_expr
.X_add_symbol
, 0, NULL
);
4764 else if (mips_pic
== SVR4_PIC
)
4767 int lui_reloc_type
= (int) BFD_RELOC_MIPS_GOT_HI16
;
4768 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT_LO16
;
4770 /* This is the large GOT case. If this is a reference to an
4771 external symbol, and there is no constant, we want
4772 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
4773 addu $tempreg,$tempreg,$gp
4774 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
4775 or if tempreg is PIC_CALL_REG
4776 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
4777 addu $tempreg,$tempreg,$gp
4778 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
4779 For a local symbol, we want
4780 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4782 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
4784 If we have a small constant, and this is a reference to
4785 an external symbol, we want
4786 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
4787 addu $tempreg,$tempreg,$gp
4788 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
4790 addiu $tempreg,$tempreg,<constant>
4791 For a local symbol, we want
4792 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4794 addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16)
4796 If we have a large constant, and this is a reference to
4797 an external symbol, we want
4798 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
4799 addu $tempreg,$tempreg,$gp
4800 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
4801 lui $at,<hiconstant>
4802 addiu $at,$at,<loconstant>
4803 addu $tempreg,$tempreg,$at
4804 For a local symbol, we want
4805 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4806 lui $at,<hiconstant>
4807 addiu $at,$at,<loconstant> (BFD_RELOC_LO16)
4808 addu $tempreg,$tempreg,$at
4810 expr1
.X_add_number
= offset_expr
.X_add_number
;
4811 offset_expr
.X_add_number
= 0;
4813 if (reg_needs_delay (GP
))
4817 if (expr1
.X_add_number
== 0 && tempreg
== PIC_CALL_REG
)
4819 lui_reloc_type
= (int) BFD_RELOC_MIPS_CALL_HI16
;
4820 lw_reloc_type
= (int) BFD_RELOC_MIPS_CALL_LO16
;
4822 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
4823 tempreg
, lui_reloc_type
);
4824 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4825 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
4826 "d,v,t", tempreg
, tempreg
, GP
);
4827 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4829 "t,o(b)", tempreg
, lw_reloc_type
, tempreg
);
4830 if (expr1
.X_add_number
== 0)
4838 /* We're going to put in an addu instruction using
4839 tempreg, so we may as well insert the nop right
4841 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4846 p
= frag_var (rs_machine_dependent
, 12 + gpdel
, 0,
4847 RELAX_ENCODE (12 + off
, 12 + gpdel
, gpdel
,
4850 ? mips_opts
.warn_about_macros
4852 offset_expr
.X_add_symbol
, 0, NULL
);
4854 else if (expr1
.X_add_number
>= -0x8000
4855 && expr1
.X_add_number
< 0x8000)
4857 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4859 macro_build ((char *) NULL
, &icnt
, &expr1
,
4860 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
4861 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
4863 p
= frag_var (rs_machine_dependent
, 12 + gpdel
, 0,
4864 RELAX_ENCODE (20, 12 + gpdel
, gpdel
, 8 + gpdel
, 0,
4866 ? mips_opts
.warn_about_macros
4868 offset_expr
.X_add_symbol
, 0, NULL
);
4874 /* If we are going to add in a base register, and the
4875 target register and the base register are the same,
4876 then we are using AT as a temporary register. Since
4877 we want to load the constant into AT, we add our
4878 current AT (from the global offset table) and the
4879 register into the register now, and pretend we were
4880 not using a base register. */
4888 assert (tempreg
== AT
);
4889 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4891 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4892 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
4893 "d,v,t", treg
, AT
, breg
);
4898 /* Set mips_optimize around the lui instruction to avoid
4899 inserting an unnecessary nop after the lw. */
4900 hold_mips_optimize
= mips_optimize
;
4902 macro_build_lui (NULL
, &icnt
, &expr1
, AT
);
4903 mips_optimize
= hold_mips_optimize
;
4905 macro_build ((char *) NULL
, &icnt
, &expr1
,
4906 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
4907 "t,r,j", AT
, AT
, (int) BFD_RELOC_LO16
);
4908 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4909 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
4910 "d,v,t", dreg
, dreg
, AT
);
4912 p
= frag_var (rs_machine_dependent
, 16 + gpdel
+ adj
, 0,
4913 RELAX_ENCODE (24 + adj
, 16 + gpdel
+ adj
, gpdel
,
4916 ? mips_opts
.warn_about_macros
4918 offset_expr
.X_add_symbol
, 0, NULL
);
4925 /* This is needed because this instruction uses $gp, but
4926 the first instruction on the main stream does not. */
4927 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4930 macro_build (p
, &icnt
, &offset_expr
,
4932 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
4934 if (expr1
.X_add_number
>= -0x8000
4935 && expr1
.X_add_number
< 0x8000)
4937 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4939 macro_build (p
, &icnt
, &expr1
,
4940 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
4941 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
4942 /* FIXME: If add_number is 0, and there was no base
4943 register, the external symbol case ended with a load,
4944 so if the symbol turns out to not be external, and
4945 the next instruction uses tempreg, an unnecessary nop
4946 will be inserted. */
4952 /* We must add in the base register now, as in the
4953 external symbol case. */
4954 assert (tempreg
== AT
);
4955 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4957 macro_build (p
, &icnt
, (expressionS
*) NULL
,
4958 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
4959 "d,v,t", treg
, AT
, breg
);
4962 /* We set breg to 0 because we have arranged to add
4963 it in in both cases. */
4967 macro_build_lui (p
, &icnt
, &expr1
, AT
);
4969 macro_build (p
, &icnt
, &expr1
,
4970 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
4971 "t,r,j", AT
, AT
, (int) BFD_RELOC_LO16
);
4973 macro_build (p
, &icnt
, (expressionS
*) NULL
,
4974 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
4975 "d,v,t", tempreg
, tempreg
, AT
);
4979 else if (mips_pic
== EMBEDDED_PIC
)
4982 addiu $tempreg,$gp,<sym> (BFD_RELOC_MIPS_GPREL)
4984 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4985 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
4986 "t,r,j", tempreg
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
4992 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4993 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
4994 "d,v,t", treg
, tempreg
, breg
);
5002 /* The j instruction may not be used in PIC code, since it
5003 requires an absolute address. We convert it to a b
5005 if (mips_pic
== NO_PIC
)
5006 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "j", "a");
5008 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "b", "p");
5011 /* The jal instructions must be handled as macros because when
5012 generating PIC code they expand to multi-instruction
5013 sequences. Normally they are simple instructions. */
5018 if (mips_pic
== NO_PIC
5019 || mips_pic
== EMBEDDED_PIC
)
5020 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "jalr",
5022 else if (mips_pic
== SVR4_PIC
)
5024 if (sreg
!= PIC_CALL_REG
)
5025 as_warn (_("MIPS PIC call to register other than $25"));
5027 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "jalr",
5031 if (mips_cprestore_offset
< 0)
5032 as_warn (_("No .cprestore pseudo-op used in PIC code"));
5035 expr1
.X_add_number
= mips_cprestore_offset
;
5036 macro_build ((char *) NULL
, &icnt
, &expr1
,
5037 HAVE_32BIT_ADDRESSES
? "lw" : "ld", "t,o(b)",
5038 GP
, (int) BFD_RELOC_LO16
, mips_frame_reg
);
5048 if (mips_pic
== NO_PIC
)
5049 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "jal", "a");
5050 else if (mips_pic
== SVR4_PIC
)
5052 /* If this is a reference to an external symbol, and we are
5053 using a small GOT, we want
5054 lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
5058 lw $gp,cprestore($sp)
5059 The cprestore value is set using the .cprestore
5060 pseudo-op. If we are using a big GOT, we want
5061 lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16)
5063 lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16)
5067 lw $gp,cprestore($sp)
5068 If the symbol is not external, we want
5069 lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5071 addiu $25,$25,<sym> (BFD_RELOC_LO16)
5074 lw $gp,cprestore($sp) */
5078 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5079 HAVE_32BIT_ADDRESSES
? "lw" : "ld",
5080 "t,o(b)", PIC_CALL_REG
,
5081 (int) BFD_RELOC_MIPS_CALL16
, GP
);
5082 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5084 p
= frag_var (rs_machine_dependent
, 4, 0,
5085 RELAX_ENCODE (0, 4, -8, 0, 0, 0),
5086 offset_expr
.X_add_symbol
, 0, NULL
);
5092 if (reg_needs_delay (GP
))
5096 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
5097 PIC_CALL_REG
, (int) BFD_RELOC_MIPS_CALL_HI16
);
5098 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5099 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
5100 "d,v,t", PIC_CALL_REG
, PIC_CALL_REG
, GP
);
5101 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5102 HAVE_32BIT_ADDRESSES
? "lw" : "ld",
5103 "t,o(b)", PIC_CALL_REG
,
5104 (int) BFD_RELOC_MIPS_CALL_LO16
, PIC_CALL_REG
);
5105 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5107 p
= frag_var (rs_machine_dependent
, 12 + gpdel
, 0,
5108 RELAX_ENCODE (16, 12 + gpdel
, gpdel
, 8 + gpdel
,
5110 offset_expr
.X_add_symbol
, 0, NULL
);
5113 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
5116 macro_build (p
, &icnt
, &offset_expr
,
5117 HAVE_32BIT_ADDRESSES
? "lw" : "ld",
5118 "t,o(b)", PIC_CALL_REG
,
5119 (int) BFD_RELOC_MIPS_GOT16
, GP
);
5121 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
5124 macro_build (p
, &icnt
, &offset_expr
,
5125 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
5126 "t,r,j", PIC_CALL_REG
, PIC_CALL_REG
,
5127 (int) BFD_RELOC_LO16
);
5128 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5129 "jalr", "s", PIC_CALL_REG
);
5132 if (mips_cprestore_offset
< 0)
5133 as_warn (_("No .cprestore pseudo-op used in PIC code"));
5136 if (mips_opts
.noreorder
)
5137 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5139 expr1
.X_add_number
= mips_cprestore_offset
;
5140 macro_build ((char *) NULL
, &icnt
, &expr1
,
5141 HAVE_32BIT_ADDRESSES
? "lw" : "ld", "t,o(b)",
5142 GP
, (int) BFD_RELOC_LO16
, mips_frame_reg
);
5146 else if (mips_pic
== EMBEDDED_PIC
)
5148 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "bal", "p");
5149 /* The linker may expand the call to a longer sequence which
5150 uses $at, so we must break rather than return. */
5175 /* Itbl support may require additional care here. */
5180 /* Itbl support may require additional care here. */
5185 /* Itbl support may require additional care here. */
5190 /* Itbl support may require additional care here. */
5202 if (mips_arch
== CPU_R4650
)
5204 as_bad (_("opcode not supported on this processor"));
5208 /* Itbl support may require additional care here. */
5213 /* Itbl support may require additional care here. */
5218 /* Itbl support may require additional care here. */
5238 if (breg
== treg
|| coproc
|| lr
)
5260 /* Itbl support may require additional care here. */
5265 /* Itbl support may require additional care here. */
5270 /* Itbl support may require additional care here. */
5275 /* Itbl support may require additional care here. */
5291 if (mips_arch
== CPU_R4650
)
5293 as_bad (_("opcode not supported on this processor"));
5298 /* Itbl support may require additional care here. */
5302 /* Itbl support may require additional care here. */
5307 /* Itbl support may require additional care here. */
5319 /* Itbl support may require additional care here. */
5320 if (mask
== M_LWC1_AB
5321 || mask
== M_SWC1_AB
5322 || mask
== M_LDC1_AB
5323 || mask
== M_SDC1_AB
5332 /* For embedded PIC, we allow loads where the offset is calculated
5333 by subtracting a symbol in the current segment from an unknown
5334 symbol, relative to a base register, e.g.:
5335 <op> $treg, <sym>-<localsym>($breg)
5336 This is used by the compiler for switch statements. */
5337 if (mips_pic
== EMBEDDED_PIC
5338 && offset_expr
.X_op
== O_subtract
5339 && (symbol_constant_p (offset_expr
.X_op_symbol
)
5340 ? S_GET_SEGMENT (offset_expr
.X_op_symbol
) == now_seg
5341 : (symbol_equated_p (offset_expr
.X_op_symbol
)
5343 (symbol_get_value_expression (offset_expr
.X_op_symbol
)
5347 && (offset_expr
.X_add_number
== 0
5348 || OUTPUT_FLAVOR
== bfd_target_elf_flavour
))
5350 /* For this case, we output the instructions:
5351 lui $tempreg,<sym> (BFD_RELOC_PCREL_HI16_S)
5352 addiu $tempreg,$tempreg,$breg
5353 <op> $treg,<sym>($tempreg) (BFD_RELOC_PCREL_LO16)
5354 If the relocation would fit entirely in 16 bits, it would be
5356 <op> $treg,<sym>($breg) (BFD_RELOC_PCREL_LO16)
5357 instead, but that seems quite difficult. */
5358 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
5359 tempreg
, (int) BFD_RELOC_PCREL_HI16_S
);
5360 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5361 ((bfd_arch_bits_per_address (stdoutput
) == 32
5362 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5363 ? "addu" : "daddu"),
5364 "d,v,t", tempreg
, tempreg
, breg
);
5365 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
, treg
,
5366 (int) BFD_RELOC_PCREL_LO16
, tempreg
);
5372 if (offset_expr
.X_op
!= O_constant
5373 && offset_expr
.X_op
!= O_symbol
)
5375 as_bad (_("expression too complex"));
5376 offset_expr
.X_op
= O_constant
;
5379 /* A constant expression in PIC code can be handled just as it
5380 is in non PIC code. */
5381 if (mips_pic
== NO_PIC
5382 || offset_expr
.X_op
== O_constant
)
5384 /* If this is a reference to a GP relative symbol, and there
5385 is no base register, we want
5386 <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL)
5387 Otherwise, if there is no base register, we want
5388 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
5389 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5390 If we have a constant, we need two instructions anyhow,
5391 so we always use the latter form.
5393 If we have a base register, and this is a reference to a
5394 GP relative symbol, we want
5395 addu $tempreg,$breg,$gp
5396 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GPREL)
5398 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
5399 addu $tempreg,$tempreg,$breg
5400 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5401 With a constant we always use the latter case.
5403 With 64bit address space and no base register and $at usable,
5405 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5406 lui $at,<sym> (BFD_RELOC_HI16_S)
5407 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
5410 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5411 If we have a base register, we want
5412 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5413 lui $at,<sym> (BFD_RELOC_HI16_S)
5414 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
5418 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5420 Without $at we can't generate the optimal path for superscalar
5421 processors here since this would require two temporary registers.
5422 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5423 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
5425 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
5427 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5428 If we have a base register, we want
5429 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5430 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
5432 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
5434 daddu $tempreg,$tempreg,$breg
5435 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5437 if (HAVE_64BIT_ADDRESSES
)
5441 /* We don't do GP optimization for now because RELAX_ENCODE can't
5442 hold the data for such large chunks. */
5446 macro_build (p
, &icnt
, &offset_expr
, "lui", "t,u",
5447 tempreg
, (int) BFD_RELOC_MIPS_HIGHEST
);
5448 macro_build (p
, &icnt
, &offset_expr
, "lui", "t,u",
5449 AT
, (int) BFD_RELOC_HI16_S
);
5450 macro_build (p
, &icnt
, &offset_expr
, "daddiu", "t,r,j",
5451 tempreg
, tempreg
, (int) BFD_RELOC_MIPS_HIGHER
);
5453 macro_build (p
, &icnt
, (expressionS
*) NULL
, "daddu",
5454 "d,v,t", AT
, AT
, breg
);
5455 macro_build (p
, &icnt
, (expressionS
*) NULL
, "dsll32",
5456 "d,w,<", tempreg
, tempreg
, 0);
5457 macro_build (p
, &icnt
, (expressionS
*) NULL
, "daddu",
5458 "d,v,t", tempreg
, tempreg
, AT
);
5459 macro_build (p
, &icnt
, &offset_expr
, s
,
5460 fmt
, treg
, (int) BFD_RELOC_LO16
, tempreg
);
5465 macro_build (p
, &icnt
, &offset_expr
, "lui", "t,u",
5466 tempreg
, (int) BFD_RELOC_MIPS_HIGHEST
);
5467 macro_build (p
, &icnt
, &offset_expr
, "daddiu", "t,r,j",
5468 tempreg
, tempreg
, (int) BFD_RELOC_MIPS_HIGHER
);
5469 macro_build (p
, &icnt
, (expressionS
*) NULL
, "dsll",
5470 "d,w,<", tempreg
, tempreg
, 16);
5471 macro_build (p
, &icnt
, &offset_expr
, "daddiu", "t,r,j",
5472 tempreg
, tempreg
, (int) BFD_RELOC_HI16_S
);
5473 macro_build (p
, &icnt
, (expressionS
*) NULL
, "dsll",
5474 "d,w,<", tempreg
, tempreg
, 16);
5476 macro_build (p
, &icnt
, (expressionS
*) NULL
, "daddu",
5477 "d,v,t", tempreg
, tempreg
, breg
);
5478 macro_build (p
, &icnt
, &offset_expr
, s
,
5479 fmt
, treg
, (int) BFD_RELOC_LO16
, tempreg
);
5487 if ((valueT
) offset_expr
.X_add_number
> MAX_GPREL_OFFSET
5488 || nopic_need_relax (offset_expr
.X_add_symbol
, 1))
5493 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
5494 treg
, (int) BFD_RELOC_MIPS_GPREL
, GP
);
5495 p
= frag_var (rs_machine_dependent
, 8, 0,
5496 RELAX_ENCODE (4, 8, 0, 4, 0,
5497 (mips_opts
.warn_about_macros
5499 && mips_opts
.noat
))),
5500 offset_expr
.X_add_symbol
, (offsetT
) 0,
5504 macro_build_lui (p
, &icnt
, &offset_expr
, tempreg
);
5507 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
, treg
,
5508 (int) BFD_RELOC_LO16
, tempreg
);
5512 if ((valueT
) offset_expr
.X_add_number
> MAX_GPREL_OFFSET
5513 || nopic_need_relax (offset_expr
.X_add_symbol
, 1))
5518 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5519 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
5520 "d,v,t", tempreg
, breg
, GP
);
5521 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
5522 treg
, (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
5523 p
= frag_var (rs_machine_dependent
, 12, 0,
5524 RELAX_ENCODE (8, 12, 0, 8, 0, 0),
5525 offset_expr
.X_add_symbol
, (offsetT
) 0,
5528 macro_build_lui (p
, &icnt
, &offset_expr
, tempreg
);
5531 macro_build (p
, &icnt
, (expressionS
*) NULL
,
5532 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
5533 "d,v,t", tempreg
, tempreg
, breg
);
5536 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
, treg
,
5537 (int) BFD_RELOC_LO16
, tempreg
);
5540 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
5542 /* If this is a reference to an external symbol, we want
5543 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5545 <op> $treg,0($tempreg)
5547 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5549 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
5550 <op> $treg,0($tempreg)
5551 If there is a base register, we add it to $tempreg before
5552 the <op>. If there is a constant, we stick it in the
5553 <op> instruction. We don't handle constants larger than
5554 16 bits, because we have no way to load the upper 16 bits
5555 (actually, we could handle them for the subset of cases
5556 in which we are not using $at). */
5557 assert (offset_expr
.X_op
== O_symbol
);
5558 expr1
.X_add_number
= offset_expr
.X_add_number
;
5559 offset_expr
.X_add_number
= 0;
5560 if (expr1
.X_add_number
< -0x8000
5561 || expr1
.X_add_number
>= 0x8000)
5562 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
5564 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5565 HAVE_32BIT_ADDRESSES
? "lw" : "ld",
5566 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
5567 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
5568 p
= frag_var (rs_machine_dependent
, 4, 0,
5569 RELAX_ENCODE (0, 4, -8, 0, 0, 0),
5570 offset_expr
.X_add_symbol
, 0, NULL
);
5571 macro_build (p
, &icnt
, &offset_expr
,
5572 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
5573 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
5575 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5576 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
5577 "d,v,t", tempreg
, tempreg
, breg
);
5578 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
, treg
,
5579 (int) BFD_RELOC_LO16
, tempreg
);
5581 else if (mips_pic
== SVR4_PIC
)
5585 /* If this is a reference to an external symbol, we want
5586 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5587 addu $tempreg,$tempreg,$gp
5588 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5589 <op> $treg,0($tempreg)
5591 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5593 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
5594 <op> $treg,0($tempreg)
5595 If there is a base register, we add it to $tempreg before
5596 the <op>. If there is a constant, we stick it in the
5597 <op> instruction. We don't handle constants larger than
5598 16 bits, because we have no way to load the upper 16 bits
5599 (actually, we could handle them for the subset of cases
5600 in which we are not using $at). */
5601 assert (offset_expr
.X_op
== O_symbol
);
5602 expr1
.X_add_number
= offset_expr
.X_add_number
;
5603 offset_expr
.X_add_number
= 0;
5604 if (expr1
.X_add_number
< -0x8000
5605 || expr1
.X_add_number
>= 0x8000)
5606 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
5607 if (reg_needs_delay (GP
))
5612 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
5613 tempreg
, (int) BFD_RELOC_MIPS_GOT_HI16
);
5614 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5615 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
5616 "d,v,t", tempreg
, tempreg
, GP
);
5617 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5618 HAVE_32BIT_ADDRESSES
? "lw" : "ld",
5619 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT_LO16
,
5621 p
= frag_var (rs_machine_dependent
, 12 + gpdel
, 0,
5622 RELAX_ENCODE (12, 12 + gpdel
, gpdel
, 8 + gpdel
, 0, 0),
5623 offset_expr
.X_add_symbol
, 0, NULL
);
5626 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
5629 macro_build (p
, &icnt
, &offset_expr
,
5630 HAVE_32BIT_ADDRESSES
? "lw" : "ld",
5631 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
5633 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
5635 macro_build (p
, &icnt
, &offset_expr
,
5636 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
5637 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
5639 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5640 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
5641 "d,v,t", tempreg
, tempreg
, breg
);
5642 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
, treg
,
5643 (int) BFD_RELOC_LO16
, tempreg
);
5645 else if (mips_pic
== EMBEDDED_PIC
)
5647 /* If there is no base register, we want
5648 <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL)
5649 If there is a base register, we want
5650 addu $tempreg,$breg,$gp
5651 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GPREL)
5653 assert (offset_expr
.X_op
== O_symbol
);
5656 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
5657 treg
, (int) BFD_RELOC_MIPS_GPREL
, GP
);
5662 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5663 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
5664 "d,v,t", tempreg
, breg
, GP
);
5665 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
5666 treg
, (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
5679 load_register (&icnt
, treg
, &imm_expr
, 0);
5683 load_register (&icnt
, treg
, &imm_expr
, 1);
5687 if (imm_expr
.X_op
== O_constant
)
5689 load_register (&icnt
, AT
, &imm_expr
, 0);
5690 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5691 "mtc1", "t,G", AT
, treg
);
5696 assert (offset_expr
.X_op
== O_symbol
5697 && strcmp (segment_name (S_GET_SEGMENT
5698 (offset_expr
.X_add_symbol
)),
5700 && offset_expr
.X_add_number
== 0);
5701 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lwc1", "T,o(b)",
5702 treg
, (int) BFD_RELOC_MIPS_LITERAL
, GP
);
5707 /* Check if we have a constant in IMM_EXPR. If the GPRs are 64 bits
5708 wide, IMM_EXPR is the entire value. Otherwise IMM_EXPR is the high
5709 order 32 bits of the value and the low order 32 bits are either
5710 zero or in OFFSET_EXPR. */
5711 if (imm_expr
.X_op
== O_constant
|| imm_expr
.X_op
== O_big
)
5713 if (HAVE_64BIT_GPRS
)
5714 load_register (&icnt
, treg
, &imm_expr
, 1);
5719 if (target_big_endian
)
5731 load_register (&icnt
, hreg
, &imm_expr
, 0);
5734 if (offset_expr
.X_op
== O_absent
)
5735 move_register (&icnt
, lreg
, 0);
5738 assert (offset_expr
.X_op
== O_constant
);
5739 load_register (&icnt
, lreg
, &offset_expr
, 0);
5746 /* We know that sym is in the .rdata section. First we get the
5747 upper 16 bits of the address. */
5748 if (mips_pic
== NO_PIC
)
5750 /* FIXME: This won't work for a 64 bit address. */
5751 macro_build_lui ((char *) NULL
, &icnt
, &offset_expr
, AT
);
5753 else if (mips_pic
== SVR4_PIC
)
5755 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5756 HAVE_32BIT_ADDRESSES
? "lw" : "ld",
5757 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
5759 else if (mips_pic
== EMBEDDED_PIC
)
5761 /* For embedded PIC we pick up the entire address off $gp in
5762 a single instruction. */
5763 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5764 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
5765 "t,r,j", AT
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
5766 offset_expr
.X_op
= O_constant
;
5767 offset_expr
.X_add_number
= 0;
5772 /* Now we load the register(s). */
5773 if (HAVE_64BIT_GPRS
)
5774 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "ld", "t,o(b)",
5775 treg
, (int) BFD_RELOC_LO16
, AT
);
5778 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lw", "t,o(b)",
5779 treg
, (int) BFD_RELOC_LO16
, AT
);
5782 /* FIXME: How in the world do we deal with the possible
5784 offset_expr
.X_add_number
+= 4;
5785 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lw", "t,o(b)",
5786 treg
+ 1, (int) BFD_RELOC_LO16
, AT
);
5790 /* To avoid confusion in tc_gen_reloc, we must ensure that this
5791 does not become a variant frag. */
5792 frag_wane (frag_now
);
5798 /* Check if we have a constant in IMM_EXPR. If the FPRs are 64 bits
5799 wide, IMM_EXPR is the entire value and the GPRs are known to be 64
5800 bits wide as well. Otherwise IMM_EXPR is the high order 32 bits of
5801 the value and the low order 32 bits are either zero or in
5803 if (imm_expr
.X_op
== O_constant
|| imm_expr
.X_op
== O_big
)
5805 load_register (&icnt
, AT
, &imm_expr
, HAVE_64BIT_FPRS
);
5806 if (HAVE_64BIT_FPRS
)
5808 assert (HAVE_64BIT_GPRS
);
5809 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5810 "dmtc1", "t,S", AT
, treg
);
5814 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5815 "mtc1", "t,G", AT
, treg
+ 1);
5816 if (offset_expr
.X_op
== O_absent
)
5817 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5818 "mtc1", "t,G", 0, treg
);
5821 assert (offset_expr
.X_op
== O_constant
);
5822 load_register (&icnt
, AT
, &offset_expr
, 0);
5823 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5824 "mtc1", "t,G", AT
, treg
);
5830 assert (offset_expr
.X_op
== O_symbol
5831 && offset_expr
.X_add_number
== 0);
5832 s
= segment_name (S_GET_SEGMENT (offset_expr
.X_add_symbol
));
5833 if (strcmp (s
, ".lit8") == 0)
5835 if (mips_opts
.isa
!= ISA_MIPS1
)
5837 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "ldc1",
5838 "T,o(b)", treg
, (int) BFD_RELOC_MIPS_LITERAL
, GP
);
5842 r
= BFD_RELOC_MIPS_LITERAL
;
5847 assert (strcmp (s
, RDATA_SECTION_NAME
) == 0);
5848 if (mips_pic
== SVR4_PIC
)
5849 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5850 HAVE_32BIT_ADDRESSES
? "lw" : "ld",
5851 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
5854 /* FIXME: This won't work for a 64 bit address. */
5855 macro_build_lui ((char *) NULL
, &icnt
, &offset_expr
, AT
);
5858 if (mips_opts
.isa
!= ISA_MIPS1
)
5860 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "ldc1",
5861 "T,o(b)", treg
, (int) BFD_RELOC_LO16
, AT
);
5863 /* To avoid confusion in tc_gen_reloc, we must ensure
5864 that this does not become a variant frag. */
5865 frag_wane (frag_now
);
5876 if (mips_arch
== CPU_R4650
)
5878 as_bad (_("opcode not supported on this processor"));
5881 /* Even on a big endian machine $fn comes before $fn+1. We have
5882 to adjust when loading from memory. */
5885 assert (mips_opts
.isa
== ISA_MIPS1
);
5886 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lwc1", "T,o(b)",
5887 target_big_endian
? treg
+ 1 : treg
,
5889 /* FIXME: A possible overflow which I don't know how to deal
5891 offset_expr
.X_add_number
+= 4;
5892 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lwc1", "T,o(b)",
5893 target_big_endian
? treg
: treg
+ 1,
5896 /* To avoid confusion in tc_gen_reloc, we must ensure that this
5897 does not become a variant frag. */
5898 frag_wane (frag_now
);
5907 * The MIPS assembler seems to check for X_add_number not
5908 * being double aligned and generating:
5911 * addiu at,at,%lo(foo+1)
5914 * But, the resulting address is the same after relocation so why
5915 * generate the extra instruction?
5917 if (mips_arch
== CPU_R4650
)
5919 as_bad (_("opcode not supported on this processor"));
5922 /* Itbl support may require additional care here. */
5924 if (mips_opts
.isa
!= ISA_MIPS1
)
5935 if (mips_arch
== CPU_R4650
)
5937 as_bad (_("opcode not supported on this processor"));
5941 if (mips_opts
.isa
!= ISA_MIPS1
)
5949 /* Itbl support may require additional care here. */
5954 if (HAVE_64BIT_GPRS
)
5965 if (HAVE_64BIT_GPRS
)
5975 /* We do _not_ bother to allow embedded PIC (symbol-local_symbol)
5976 loads for the case of doing a pair of loads to simulate an 'ld'.
5977 This is not currently done by the compiler, and assembly coders
5978 writing embedded-pic code can cope. */
5980 if (offset_expr
.X_op
!= O_symbol
5981 && offset_expr
.X_op
!= O_constant
)
5983 as_bad (_("expression too complex"));
5984 offset_expr
.X_op
= O_constant
;
5987 /* Even on a big endian machine $fn comes before $fn+1. We have
5988 to adjust when loading from memory. We set coproc if we must
5989 load $fn+1 first. */
5990 /* Itbl support may require additional care here. */
5991 if (! target_big_endian
)
5994 if (mips_pic
== NO_PIC
5995 || offset_expr
.X_op
== O_constant
)
5997 /* If this is a reference to a GP relative symbol, we want
5998 <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL)
5999 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_MIPS_GPREL)
6000 If we have a base register, we use this
6002 <op> $treg,<sym>($at) (BFD_RELOC_MIPS_GPREL)
6003 <op> $treg+1,<sym>+4($at) (BFD_RELOC_MIPS_GPREL)
6004 If this is not a GP relative symbol, we want
6005 lui $at,<sym> (BFD_RELOC_HI16_S)
6006 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
6007 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
6008 If there is a base register, we add it to $at after the
6009 lui instruction. If there is a constant, we always use
6011 if ((valueT
) offset_expr
.X_add_number
> MAX_GPREL_OFFSET
6012 || nopic_need_relax (offset_expr
.X_add_symbol
, 1))
6031 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6032 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
6033 "d,v,t", AT
, breg
, GP
);
6039 /* Itbl support may require additional care here. */
6040 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
6041 coproc
? treg
+ 1 : treg
,
6042 (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
6043 offset_expr
.X_add_number
+= 4;
6045 /* Set mips_optimize to 2 to avoid inserting an
6047 hold_mips_optimize
= mips_optimize
;
6049 /* Itbl support may require additional care here. */
6050 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
6051 coproc
? treg
: treg
+ 1,
6052 (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
6053 mips_optimize
= hold_mips_optimize
;
6055 p
= frag_var (rs_machine_dependent
, 12 + off
, 0,
6056 RELAX_ENCODE (8 + off
, 12 + off
, 0, 4 + off
, 1,
6057 used_at
&& mips_opts
.noat
),
6058 offset_expr
.X_add_symbol
, (offsetT
) 0,
6061 /* We just generated two relocs. When tc_gen_reloc
6062 handles this case, it will skip the first reloc and
6063 handle the second. The second reloc already has an
6064 extra addend of 4, which we added above. We must
6065 subtract it out, and then subtract another 4 to make
6066 the first reloc come out right. The second reloc
6067 will come out right because we are going to add 4 to
6068 offset_expr when we build its instruction below.
6070 If we have a symbol, then we don't want to include
6071 the offset, because it will wind up being included
6072 when we generate the reloc. */
6074 if (offset_expr
.X_op
== O_constant
)
6075 offset_expr
.X_add_number
-= 8;
6078 offset_expr
.X_add_number
= -4;
6079 offset_expr
.X_op
= O_constant
;
6082 macro_build_lui (p
, &icnt
, &offset_expr
, AT
);
6087 macro_build (p
, &icnt
, (expressionS
*) NULL
,
6088 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
6089 "d,v,t", AT
, breg
, AT
);
6093 /* Itbl support may require additional care here. */
6094 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
,
6095 coproc
? treg
+ 1 : treg
,
6096 (int) BFD_RELOC_LO16
, AT
);
6099 /* FIXME: How do we handle overflow here? */
6100 offset_expr
.X_add_number
+= 4;
6101 /* Itbl support may require additional care here. */
6102 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
,
6103 coproc
? treg
: treg
+ 1,
6104 (int) BFD_RELOC_LO16
, AT
);
6106 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
6110 /* If this is a reference to an external symbol, we want
6111 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6116 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6118 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
6119 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
6120 If there is a base register we add it to $at before the
6121 lwc1 instructions. If there is a constant we include it
6122 in the lwc1 instructions. */
6124 expr1
.X_add_number
= offset_expr
.X_add_number
;
6125 offset_expr
.X_add_number
= 0;
6126 if (expr1
.X_add_number
< -0x8000
6127 || expr1
.X_add_number
>= 0x8000 - 4)
6128 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6133 frag_grow (24 + off
);
6134 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
6135 HAVE_32BIT_ADDRESSES
? "lw" : "ld",
6136 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
6137 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
6139 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6140 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
6141 "d,v,t", AT
, breg
, AT
);
6142 /* Itbl support may require additional care here. */
6143 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
6144 coproc
? treg
+ 1 : treg
,
6145 (int) BFD_RELOC_LO16
, AT
);
6146 expr1
.X_add_number
+= 4;
6148 /* Set mips_optimize to 2 to avoid inserting an undesired
6150 hold_mips_optimize
= mips_optimize
;
6152 /* Itbl support may require additional care here. */
6153 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
6154 coproc
? treg
: treg
+ 1,
6155 (int) BFD_RELOC_LO16
, AT
);
6156 mips_optimize
= hold_mips_optimize
;
6158 (void) frag_var (rs_machine_dependent
, 0, 0,
6159 RELAX_ENCODE (0, 0, -16 - off
, -8, 1, 0),
6160 offset_expr
.X_add_symbol
, 0, NULL
);
6162 else if (mips_pic
== SVR4_PIC
)
6166 /* If this is a reference to an external symbol, we want
6167 lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16)
6169 lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16)
6174 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6176 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
6177 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
6178 If there is a base register we add it to $at before the
6179 lwc1 instructions. If there is a constant we include it
6180 in the lwc1 instructions. */
6182 expr1
.X_add_number
= offset_expr
.X_add_number
;
6183 offset_expr
.X_add_number
= 0;
6184 if (expr1
.X_add_number
< -0x8000
6185 || expr1
.X_add_number
>= 0x8000 - 4)
6186 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6187 if (reg_needs_delay (GP
))
6196 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
6197 AT
, (int) BFD_RELOC_MIPS_GOT_HI16
);
6198 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6199 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
6200 "d,v,t", AT
, AT
, GP
);
6201 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
6202 HAVE_32BIT_ADDRESSES
? "lw" : "ld",
6203 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT_LO16
, AT
);
6204 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
6206 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6207 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
6208 "d,v,t", AT
, breg
, AT
);
6209 /* Itbl support may require additional care here. */
6210 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
6211 coproc
? treg
+ 1 : treg
,
6212 (int) BFD_RELOC_LO16
, AT
);
6213 expr1
.X_add_number
+= 4;
6215 /* Set mips_optimize to 2 to avoid inserting an undesired
6217 hold_mips_optimize
= mips_optimize
;
6219 /* Itbl support may require additional care here. */
6220 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
6221 coproc
? treg
: treg
+ 1,
6222 (int) BFD_RELOC_LO16
, AT
);
6223 mips_optimize
= hold_mips_optimize
;
6224 expr1
.X_add_number
-= 4;
6226 p
= frag_var (rs_machine_dependent
, 16 + gpdel
+ off
, 0,
6227 RELAX_ENCODE (24 + off
, 16 + gpdel
+ off
, gpdel
,
6228 8 + gpdel
+ off
, 1, 0),
6229 offset_expr
.X_add_symbol
, 0, NULL
);
6232 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
6235 macro_build (p
, &icnt
, &offset_expr
,
6236 HAVE_32BIT_ADDRESSES
? "lw" : "ld",
6237 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
6239 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
6243 macro_build (p
, &icnt
, (expressionS
*) NULL
,
6244 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
6245 "d,v,t", AT
, breg
, AT
);
6248 /* Itbl support may require additional care here. */
6249 macro_build (p
, &icnt
, &expr1
, s
, fmt
,
6250 coproc
? treg
+ 1 : treg
,
6251 (int) BFD_RELOC_LO16
, AT
);
6253 expr1
.X_add_number
+= 4;
6255 /* Set mips_optimize to 2 to avoid inserting an undesired
6257 hold_mips_optimize
= mips_optimize
;
6259 /* Itbl support may require additional care here. */
6260 macro_build (p
, &icnt
, &expr1
, s
, fmt
,
6261 coproc
? treg
: treg
+ 1,
6262 (int) BFD_RELOC_LO16
, AT
);
6263 mips_optimize
= hold_mips_optimize
;
6265 else if (mips_pic
== EMBEDDED_PIC
)
6267 /* If there is no base register, we use
6268 <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL)
6269 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_MIPS_GPREL)
6270 If we have a base register, we use
6272 <op> $treg,<sym>($at) (BFD_RELOC_MIPS_GPREL)
6273 <op> $treg+1,<sym>+4($at) (BFD_RELOC_MIPS_GPREL)
6282 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6283 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
6284 "d,v,t", AT
, breg
, GP
);
6289 /* Itbl support may require additional care here. */
6290 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
6291 coproc
? treg
+ 1 : treg
,
6292 (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
6293 offset_expr
.X_add_number
+= 4;
6294 /* Itbl support may require additional care here. */
6295 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
6296 coproc
? treg
: treg
+ 1,
6297 (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
6313 assert (HAVE_32BIT_ADDRESSES
);
6314 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
6315 (int) BFD_RELOC_LO16
, breg
);
6316 offset_expr
.X_add_number
+= 4;
6317 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
+ 1,
6318 (int) BFD_RELOC_LO16
, breg
);
6321 /* New code added to support COPZ instructions.
6322 This code builds table entries out of the macros in mip_opcodes.
6323 R4000 uses interlocks to handle coproc delays.
6324 Other chips (like the R3000) require nops to be inserted for delays.
6326 FIXME: Currently, we require that the user handle delays.
6327 In order to fill delay slots for non-interlocked chips,
6328 we must have a way to specify delays based on the coprocessor.
6329 Eg. 4 cycles if load coproc reg from memory, 1 if in cache, etc.
6330 What are the side-effects of the cop instruction?
6331 What cache support might we have and what are its effects?
6332 Both coprocessor & memory require delays. how long???
6333 What registers are read/set/modified?
6335 If an itbl is provided to interpret cop instructions,
6336 this knowledge can be encoded in the itbl spec. */
6350 /* For now we just do C (same as Cz). The parameter will be
6351 stored in insn_opcode by mips_ip. */
6352 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s
, "C",
6357 move_register (&icnt
, dreg
, sreg
);
6360 #ifdef LOSING_COMPILER
6362 /* Try and see if this is a new itbl instruction.
6363 This code builds table entries out of the macros in mip_opcodes.
6364 FIXME: For now we just assemble the expression and pass it's
6365 value along as a 32-bit immediate.
6366 We may want to have the assembler assemble this value,
6367 so that we gain the assembler's knowledge of delay slots,
6369 Would it be more efficient to use mask (id) here? */
6370 if (itbl_have_entries
6371 && (immed_expr
= itbl_assemble (ip
->insn_mo
->name
, "")))
6373 s
= ip
->insn_mo
->name
;
6375 coproc
= ITBL_DECODE_PNUM (immed_expr
);;
6376 macro_build ((char *) NULL
, &icnt
, &immed_expr
, s
, "C");
6383 as_warn (_("Macro used $at after \".set noat\""));
6388 struct mips_cl_insn
*ip
;
6390 register int treg
, sreg
, dreg
, breg
;
6406 bfd_reloc_code_real_type r
;
6409 treg
= (ip
->insn_opcode
>> 16) & 0x1f;
6410 dreg
= (ip
->insn_opcode
>> 11) & 0x1f;
6411 sreg
= breg
= (ip
->insn_opcode
>> 21) & 0x1f;
6412 mask
= ip
->insn_mo
->mask
;
6414 expr1
.X_op
= O_constant
;
6415 expr1
.X_op_symbol
= NULL
;
6416 expr1
.X_add_symbol
= NULL
;
6417 expr1
.X_add_number
= 1;
6421 #endif /* LOSING_COMPILER */
6426 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6427 dbl
? "dmultu" : "multu", "s,t", sreg
, treg
);
6428 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "mflo", "d",
6435 /* The MIPS assembler some times generates shifts and adds. I'm
6436 not trying to be that fancy. GCC should do this for us
6438 load_register (&icnt
, AT
, &imm_expr
, dbl
);
6439 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6440 dbl
? "dmult" : "mult", "s,t", sreg
, AT
);
6441 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "mflo", "d",
6455 mips_emit_delays (true);
6456 ++mips_opts
.noreorder
;
6457 mips_any_noreorder
= 1;
6459 load_register (&icnt
, AT
, &imm_expr
, dbl
);
6460 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6461 dbl
? "dmult" : "mult", "s,t", sreg
, imm
? AT
: treg
);
6462 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "mflo", "d",
6464 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6465 dbl
? "dsra32" : "sra", "d,w,<", dreg
, dreg
, 31);
6466 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "mfhi", "d",
6469 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "tne", "s,t",
6473 expr1
.X_add_number
= 8;
6474 macro_build ((char *) NULL
, &icnt
, &expr1
, "beq", "s,t,p", dreg
,
6476 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "",
6478 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "break",
6481 --mips_opts
.noreorder
;
6482 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "mflo", "d", dreg
);
6495 mips_emit_delays (true);
6496 ++mips_opts
.noreorder
;
6497 mips_any_noreorder
= 1;
6499 load_register (&icnt
, AT
, &imm_expr
, dbl
);
6500 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6501 dbl
? "dmultu" : "multu",
6502 "s,t", sreg
, imm
? AT
: treg
);
6503 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "mfhi", "d",
6505 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "mflo", "d",
6508 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "tne", "s,t",
6512 expr1
.X_add_number
= 8;
6513 macro_build ((char *) NULL
, &icnt
, &expr1
, "beq", "s,t,p", AT
, 0);
6514 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "",
6516 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "break",
6519 --mips_opts
.noreorder
;
6523 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "subu",
6524 "d,v,t", AT
, 0, treg
);
6525 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "srlv",
6526 "d,t,s", AT
, sreg
, AT
);
6527 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "sllv",
6528 "d,t,s", dreg
, sreg
, treg
);
6529 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "or",
6530 "d,v,t", dreg
, dreg
, AT
);
6534 if (imm_expr
.X_op
!= O_constant
)
6535 as_bad (_("rotate count too large"));
6536 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "sll", "d,w,<",
6537 AT
, sreg
, (int) (imm_expr
.X_add_number
& 0x1f));
6538 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "srl", "d,w,<",
6539 dreg
, sreg
, (int) ((0 - imm_expr
.X_add_number
) & 0x1f));
6540 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "or", "d,v,t",
6545 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "subu",
6546 "d,v,t", AT
, 0, treg
);
6547 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "sllv",
6548 "d,t,s", AT
, sreg
, AT
);
6549 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "srlv",
6550 "d,t,s", dreg
, sreg
, treg
);
6551 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "or",
6552 "d,v,t", dreg
, dreg
, AT
);
6556 if (imm_expr
.X_op
!= O_constant
)
6557 as_bad (_("rotate count too large"));
6558 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "srl", "d,w,<",
6559 AT
, sreg
, (int) (imm_expr
.X_add_number
& 0x1f));
6560 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "sll", "d,w,<",
6561 dreg
, sreg
, (int) ((0 - imm_expr
.X_add_number
) & 0x1f));
6562 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "or", "d,v,t",
6567 if (mips_arch
== CPU_R4650
)
6569 as_bad (_("opcode not supported on this processor"));
6572 assert (mips_opts
.isa
== ISA_MIPS1
);
6573 /* Even on a big endian machine $fn comes before $fn+1. We have
6574 to adjust when storing to memory. */
6575 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "swc1", "T,o(b)",
6576 target_big_endian
? treg
+ 1 : treg
,
6577 (int) BFD_RELOC_LO16
, breg
);
6578 offset_expr
.X_add_number
+= 4;
6579 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "swc1", "T,o(b)",
6580 target_big_endian
? treg
: treg
+ 1,
6581 (int) BFD_RELOC_LO16
, breg
);
6586 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
6587 treg
, (int) BFD_RELOC_LO16
);
6589 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
6590 sreg
, (int) BFD_RELOC_LO16
);
6593 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "xor",
6594 "d,v,t", dreg
, sreg
, treg
);
6595 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
6596 dreg
, (int) BFD_RELOC_LO16
);
6601 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
6603 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
6604 sreg
, (int) BFD_RELOC_LO16
);
6609 as_warn (_("Instruction %s: result is always false"),
6611 move_register (&icnt
, dreg
, 0);
6614 if (imm_expr
.X_op
== O_constant
6615 && imm_expr
.X_add_number
>= 0
6616 && imm_expr
.X_add_number
< 0x10000)
6618 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "xori", "t,r,i", dreg
,
6619 sreg
, (int) BFD_RELOC_LO16
);
6622 else if (imm_expr
.X_op
== O_constant
6623 && imm_expr
.X_add_number
> -0x8000
6624 && imm_expr
.X_add_number
< 0)
6626 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
6627 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
6628 HAVE_32BIT_GPRS
? "addiu" : "daddiu",
6629 "t,r,j", dreg
, sreg
,
6630 (int) BFD_RELOC_LO16
);
6635 load_register (&icnt
, AT
, &imm_expr
, 0);
6636 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "xor",
6637 "d,v,t", dreg
, sreg
, AT
);
6640 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
, dreg
,
6641 (int) BFD_RELOC_LO16
);
6646 case M_SGE
: /* sreg >= treg <==> not (sreg < treg) */
6652 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s
, "d,v,t",
6654 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
6655 (int) BFD_RELOC_LO16
);
6658 case M_SGE_I
: /* sreg >= I <==> not (sreg < I) */
6660 if (imm_expr
.X_op
== O_constant
6661 && imm_expr
.X_add_number
>= -0x8000
6662 && imm_expr
.X_add_number
< 0x8000)
6664 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
6665 mask
== M_SGE_I
? "slti" : "sltiu",
6666 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
6671 load_register (&icnt
, AT
, &imm_expr
, 0);
6672 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6673 mask
== M_SGE_I
? "slt" : "sltu", "d,v,t", dreg
, sreg
,
6677 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
6678 (int) BFD_RELOC_LO16
);
6683 case M_SGT
: /* sreg > treg <==> treg < sreg */
6689 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s
, "d,v,t",
6693 case M_SGT_I
: /* sreg > I <==> I < sreg */
6699 load_register (&icnt
, AT
, &imm_expr
, 0);
6700 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s
, "d,v,t",
6704 case M_SLE
: /* sreg <= treg <==> treg >= sreg <==> not (treg < sreg) */
6710 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s
, "d,v,t",
6712 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
6713 (int) BFD_RELOC_LO16
);
6716 case M_SLE_I
: /* sreg <= I <==> I >= sreg <==> not (I < sreg) */
6722 load_register (&icnt
, AT
, &imm_expr
, 0);
6723 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s
, "d,v,t",
6725 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
6726 (int) BFD_RELOC_LO16
);
6730 if (imm_expr
.X_op
== O_constant
6731 && imm_expr
.X_add_number
>= -0x8000
6732 && imm_expr
.X_add_number
< 0x8000)
6734 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "slti", "t,r,j",
6735 dreg
, sreg
, (int) BFD_RELOC_LO16
);
6738 load_register (&icnt
, AT
, &imm_expr
, 0);
6739 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "slt", "d,v,t",
6744 if (imm_expr
.X_op
== O_constant
6745 && imm_expr
.X_add_number
>= -0x8000
6746 && imm_expr
.X_add_number
< 0x8000)
6748 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "sltiu", "t,r,j",
6749 dreg
, sreg
, (int) BFD_RELOC_LO16
);
6752 load_register (&icnt
, AT
, &imm_expr
, 0);
6753 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "sltu",
6754 "d,v,t", dreg
, sreg
, AT
);
6759 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "sltu",
6760 "d,v,t", dreg
, 0, treg
);
6762 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "sltu",
6763 "d,v,t", dreg
, 0, sreg
);
6766 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "xor",
6767 "d,v,t", dreg
, sreg
, treg
);
6768 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "sltu",
6769 "d,v,t", dreg
, 0, dreg
);
6774 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
6776 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "sltu",
6777 "d,v,t", dreg
, 0, sreg
);
6782 as_warn (_("Instruction %s: result is always true"),
6784 macro_build ((char *) NULL
, &icnt
, &expr1
,
6785 HAVE_32BIT_GPRS
? "addiu" : "daddiu",
6786 "t,r,j", dreg
, 0, (int) BFD_RELOC_LO16
);
6789 if (imm_expr
.X_op
== O_constant
6790 && imm_expr
.X_add_number
>= 0
6791 && imm_expr
.X_add_number
< 0x10000)
6793 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "xori", "t,r,i",
6794 dreg
, sreg
, (int) BFD_RELOC_LO16
);
6797 else if (imm_expr
.X_op
== O_constant
6798 && imm_expr
.X_add_number
> -0x8000
6799 && imm_expr
.X_add_number
< 0)
6801 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
6802 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
6803 HAVE_32BIT_GPRS
? "addiu" : "daddiu",
6804 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
6809 load_register (&icnt
, AT
, &imm_expr
, 0);
6810 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "xor",
6811 "d,v,t", dreg
, sreg
, AT
);
6814 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "sltu",
6815 "d,v,t", dreg
, 0, dreg
);
6823 if (imm_expr
.X_op
== O_constant
6824 && imm_expr
.X_add_number
> -0x8000
6825 && imm_expr
.X_add_number
<= 0x8000)
6827 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
6828 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
6829 dbl
? "daddi" : "addi",
6830 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
6833 load_register (&icnt
, AT
, &imm_expr
, dbl
);
6834 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6835 dbl
? "dsub" : "sub", "d,v,t", dreg
, sreg
, AT
);
6841 if (imm_expr
.X_op
== O_constant
6842 && imm_expr
.X_add_number
> -0x8000
6843 && imm_expr
.X_add_number
<= 0x8000)
6845 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
6846 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
6847 dbl
? "daddiu" : "addiu",
6848 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
6851 load_register (&icnt
, AT
, &imm_expr
, dbl
);
6852 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6853 dbl
? "dsubu" : "subu", "d,v,t", dreg
, sreg
, AT
);
6874 load_register (&icnt
, AT
, &imm_expr
, 0);
6875 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s
, "s,t", sreg
,
6881 assert (mips_opts
.isa
== ISA_MIPS1
);
6882 sreg
= (ip
->insn_opcode
>> 11) & 0x1f; /* floating reg */
6883 dreg
= (ip
->insn_opcode
>> 06) & 0x1f; /* floating reg */
6886 * Is the double cfc1 instruction a bug in the mips assembler;
6887 * or is there a reason for it?
6889 mips_emit_delays (true);
6890 ++mips_opts
.noreorder
;
6891 mips_any_noreorder
= 1;
6892 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "cfc1", "t,G",
6894 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "cfc1", "t,G",
6896 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
6897 expr1
.X_add_number
= 3;
6898 macro_build ((char *) NULL
, &icnt
, &expr1
, "ori", "t,r,i", AT
, treg
,
6899 (int) BFD_RELOC_LO16
);
6900 expr1
.X_add_number
= 2;
6901 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", AT
, AT
,
6902 (int) BFD_RELOC_LO16
);
6903 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "ctc1", "t,G",
6905 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
6906 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6907 mask
== M_TRUNCWD
? "cvt.w.d" : "cvt.w.s", "D,S", dreg
, sreg
);
6908 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "ctc1", "t,G",
6910 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
6911 --mips_opts
.noreorder
;
6920 if (offset_expr
.X_add_number
>= 0x7fff)
6921 as_bad (_("operand overflow"));
6922 /* avoid load delay */
6923 if (! target_big_endian
)
6924 offset_expr
.X_add_number
+= 1;
6925 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
6926 (int) BFD_RELOC_LO16
, breg
);
6927 if (! target_big_endian
)
6928 offset_expr
.X_add_number
-= 1;
6930 offset_expr
.X_add_number
+= 1;
6931 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lbu", "t,o(b)", AT
,
6932 (int) BFD_RELOC_LO16
, breg
);
6933 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "sll", "d,w,<",
6935 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "or", "d,v,t",
6949 if (offset_expr
.X_add_number
>= 0x8000 - off
)
6950 as_bad (_("operand overflow"));
6951 if (! target_big_endian
)
6952 offset_expr
.X_add_number
+= off
;
6953 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
6954 (int) BFD_RELOC_LO16
, breg
);
6955 if (! target_big_endian
)
6956 offset_expr
.X_add_number
-= off
;
6958 offset_expr
.X_add_number
+= off
;
6959 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s2
, "t,o(b)", treg
,
6960 (int) BFD_RELOC_LO16
, breg
);
6974 load_address (&icnt
, AT
, &offset_expr
, HAVE_64BIT_ADDRESSES
, &used_at
);
6976 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6977 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
6978 "d,v,t", AT
, AT
, breg
);
6979 if (! target_big_endian
)
6980 expr1
.X_add_number
= off
;
6982 expr1
.X_add_number
= 0;
6983 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, "t,o(b)", treg
,
6984 (int) BFD_RELOC_LO16
, AT
);
6985 if (! target_big_endian
)
6986 expr1
.X_add_number
= 0;
6988 expr1
.X_add_number
= off
;
6989 macro_build ((char *) NULL
, &icnt
, &expr1
, s2
, "t,o(b)", treg
,
6990 (int) BFD_RELOC_LO16
, AT
);
6996 load_address (&icnt
, AT
, &offset_expr
, HAVE_64BIT_ADDRESSES
, &used_at
);
6998 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6999 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
7000 "d,v,t", AT
, AT
, breg
);
7001 if (target_big_endian
)
7002 expr1
.X_add_number
= 0;
7003 macro_build ((char *) NULL
, &icnt
, &expr1
,
7004 mask
== M_ULH_A
? "lb" : "lbu", "t,o(b)", treg
,
7005 (int) BFD_RELOC_LO16
, AT
);
7006 if (target_big_endian
)
7007 expr1
.X_add_number
= 1;
7009 expr1
.X_add_number
= 0;
7010 macro_build ((char *) NULL
, &icnt
, &expr1
, "lbu", "t,o(b)", AT
,
7011 (int) BFD_RELOC_LO16
, AT
);
7012 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "sll", "d,w,<",
7014 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "or", "d,v,t",
7019 if (offset_expr
.X_add_number
>= 0x7fff)
7020 as_bad (_("operand overflow"));
7021 if (target_big_endian
)
7022 offset_expr
.X_add_number
+= 1;
7023 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "sb", "t,o(b)", treg
,
7024 (int) BFD_RELOC_LO16
, breg
);
7025 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "srl", "d,w,<",
7027 if (target_big_endian
)
7028 offset_expr
.X_add_number
-= 1;
7030 offset_expr
.X_add_number
+= 1;
7031 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "sb", "t,o(b)", AT
,
7032 (int) BFD_RELOC_LO16
, breg
);
7045 if (offset_expr
.X_add_number
>= 0x8000 - off
)
7046 as_bad (_("operand overflow"));
7047 if (! target_big_endian
)
7048 offset_expr
.X_add_number
+= off
;
7049 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
7050 (int) BFD_RELOC_LO16
, breg
);
7051 if (! target_big_endian
)
7052 offset_expr
.X_add_number
-= off
;
7054 offset_expr
.X_add_number
+= off
;
7055 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s2
, "t,o(b)", treg
,
7056 (int) BFD_RELOC_LO16
, breg
);
7070 load_address (&icnt
, AT
, &offset_expr
, HAVE_64BIT_ADDRESSES
, &used_at
);
7072 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
7073 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
7074 "d,v,t", AT
, AT
, breg
);
7075 if (! target_big_endian
)
7076 expr1
.X_add_number
= off
;
7078 expr1
.X_add_number
= 0;
7079 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, "t,o(b)", treg
,
7080 (int) BFD_RELOC_LO16
, AT
);
7081 if (! target_big_endian
)
7082 expr1
.X_add_number
= 0;
7084 expr1
.X_add_number
= off
;
7085 macro_build ((char *) NULL
, &icnt
, &expr1
, s2
, "t,o(b)", treg
,
7086 (int) BFD_RELOC_LO16
, AT
);
7091 load_address (&icnt
, AT
, &offset_expr
, HAVE_64BIT_ADDRESSES
, &used_at
);
7093 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
7094 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
7095 "d,v,t", AT
, AT
, breg
);
7096 if (! target_big_endian
)
7097 expr1
.X_add_number
= 0;
7098 macro_build ((char *) NULL
, &icnt
, &expr1
, "sb", "t,o(b)", treg
,
7099 (int) BFD_RELOC_LO16
, AT
);
7100 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "srl", "d,w,<",
7102 if (! target_big_endian
)
7103 expr1
.X_add_number
= 1;
7105 expr1
.X_add_number
= 0;
7106 macro_build ((char *) NULL
, &icnt
, &expr1
, "sb", "t,o(b)", treg
,
7107 (int) BFD_RELOC_LO16
, AT
);
7108 if (! target_big_endian
)
7109 expr1
.X_add_number
= 0;
7111 expr1
.X_add_number
= 1;
7112 macro_build ((char *) NULL
, &icnt
, &expr1
, "lbu", "t,o(b)", AT
,
7113 (int) BFD_RELOC_LO16
, AT
);
7114 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "sll", "d,w,<",
7116 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "or", "d,v,t",
7121 /* FIXME: Check if this is one of the itbl macros, since they
7122 are added dynamically. */
7123 as_bad (_("Macro %s not implemented yet"), ip
->insn_mo
->name
);
7127 as_warn (_("Macro used $at after \".set noat\""));
7130 /* Implement macros in mips16 mode. */
7134 struct mips_cl_insn
*ip
;
7137 int xreg
, yreg
, zreg
, tmp
;
7141 const char *s
, *s2
, *s3
;
7143 mask
= ip
->insn_mo
->mask
;
7145 xreg
= (ip
->insn_opcode
>> MIPS16OP_SH_RX
) & MIPS16OP_MASK_RX
;
7146 yreg
= (ip
->insn_opcode
>> MIPS16OP_SH_RY
) & MIPS16OP_MASK_RY
;
7147 zreg
= (ip
->insn_opcode
>> MIPS16OP_SH_RZ
) & MIPS16OP_MASK_RZ
;
7151 expr1
.X_op
= O_constant
;
7152 expr1
.X_op_symbol
= NULL
;
7153 expr1
.X_add_symbol
= NULL
;
7154 expr1
.X_add_number
= 1;
7173 mips_emit_delays (true);
7174 ++mips_opts
.noreorder
;
7175 mips_any_noreorder
= 1;
7176 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
7177 dbl
? "ddiv" : "div",
7178 "0,x,y", xreg
, yreg
);
7179 expr1
.X_add_number
= 2;
7180 macro_build ((char *) NULL
, &icnt
, &expr1
, "bnez", "x,p", yreg
);
7181 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "break", "6",
7184 /* FIXME: The normal code checks for of -1 / -0x80000000 here,
7185 since that causes an overflow. We should do that as well,
7186 but I don't see how to do the comparisons without a temporary
7188 --mips_opts
.noreorder
;
7189 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s
, "x", zreg
);
7208 mips_emit_delays (true);
7209 ++mips_opts
.noreorder
;
7210 mips_any_noreorder
= 1;
7211 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s
, "0,x,y",
7213 expr1
.X_add_number
= 2;
7214 macro_build ((char *) NULL
, &icnt
, &expr1
, "bnez", "x,p", yreg
);
7215 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "break",
7217 --mips_opts
.noreorder
;
7218 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s2
, "x", zreg
);
7224 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
7225 dbl
? "dmultu" : "multu", "x,y", xreg
, yreg
);
7226 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "mflo", "x",
7235 if (imm_expr
.X_op
!= O_constant
)
7236 as_bad (_("Unsupported large constant"));
7237 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
7238 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
7239 dbl
? "daddiu" : "addiu", "y,x,4", yreg
, xreg
);
7243 if (imm_expr
.X_op
!= O_constant
)
7244 as_bad (_("Unsupported large constant"));
7245 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
7246 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "addiu",
7251 if (imm_expr
.X_op
!= O_constant
)
7252 as_bad (_("Unsupported large constant"));
7253 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
7254 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "daddiu",
7277 goto do_reverse_branch
;
7281 goto do_reverse_branch
;
7293 goto do_reverse_branch
;
7304 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s
, "x,y",
7306 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s2
, "p");
7333 goto do_addone_branch_i
;
7338 goto do_addone_branch_i
;
7353 goto do_addone_branch_i
;
7360 if (imm_expr
.X_op
!= O_constant
)
7361 as_bad (_("Unsupported large constant"));
7362 ++imm_expr
.X_add_number
;
7365 macro_build ((char *) NULL
, &icnt
, &imm_expr
, s
, s3
, xreg
);
7366 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s2
, "p");
7370 expr1
.X_add_number
= 0;
7371 macro_build ((char *) NULL
, &icnt
, &expr1
, "slti", "x,8", yreg
);
7373 move_register (&icnt
, xreg
, yreg
);
7374 expr1
.X_add_number
= 2;
7375 macro_build ((char *) NULL
, &icnt
, &expr1
, "bteqz", "p");
7376 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
7377 "neg", "x,w", xreg
, xreg
);
7381 /* For consistency checking, verify that all bits are specified either
7382 by the match/mask part of the instruction definition, or by the
7385 validate_mips_insn (opc
)
7386 const struct mips_opcode
*opc
;
7388 const char *p
= opc
->args
;
7390 unsigned long used_bits
= opc
->mask
;
7392 if ((used_bits
& opc
->match
) != opc
->match
)
7394 as_bad (_("internal: bad mips opcode (mask error): %s %s"),
7395 opc
->name
, opc
->args
);
7398 #define USE_BITS(mask,shift) (used_bits |= ((mask) << (shift)))
7405 case '<': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
7406 case '>': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
7408 case 'B': USE_BITS (OP_MASK_CODE20
, OP_SH_CODE20
); break;
7409 case 'C': USE_BITS (OP_MASK_COPZ
, OP_SH_COPZ
); break;
7410 case 'D': USE_BITS (OP_MASK_FD
, OP_SH_FD
); break;
7411 case 'E': USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
7413 case 'G': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
7414 case 'H': USE_BITS (OP_MASK_SEL
, OP_SH_SEL
); break;
7416 case 'J': USE_BITS (OP_MASK_CODE19
, OP_SH_CODE19
); break;
7418 case 'M': USE_BITS (OP_MASK_CCC
, OP_SH_CCC
); break;
7419 case 'N': USE_BITS (OP_MASK_BCC
, OP_SH_BCC
); break;
7420 case 'R': USE_BITS (OP_MASK_FR
, OP_SH_FR
); break;
7421 case 'S': USE_BITS (OP_MASK_FS
, OP_SH_FS
); break;
7422 case 'T': USE_BITS (OP_MASK_FT
, OP_SH_FT
); break;
7423 case 'V': USE_BITS (OP_MASK_FS
, OP_SH_FS
); break;
7424 case 'W': USE_BITS (OP_MASK_FT
, OP_SH_FT
); break;
7425 case 'a': USE_BITS (OP_MASK_TARGET
, OP_SH_TARGET
); break;
7426 case 'b': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
7427 case 'c': USE_BITS (OP_MASK_CODE
, OP_SH_CODE
); break;
7428 case 'd': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
7430 case 'h': USE_BITS (OP_MASK_PREFX
, OP_SH_PREFX
); break;
7431 case 'i': USE_BITS (OP_MASK_IMMEDIATE
, OP_SH_IMMEDIATE
); break;
7432 case 'j': USE_BITS (OP_MASK_DELTA
, OP_SH_DELTA
); break;
7433 case 'k': USE_BITS (OP_MASK_CACHE
, OP_SH_CACHE
); break;
7435 case 'o': USE_BITS (OP_MASK_DELTA
, OP_SH_DELTA
); break;
7436 case 'p': USE_BITS (OP_MASK_DELTA
, OP_SH_DELTA
); break;
7437 case 'q': USE_BITS (OP_MASK_CODE2
, OP_SH_CODE2
); break;
7438 case 'r': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
7439 case 's': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
7440 case 't': USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
7441 case 'u': USE_BITS (OP_MASK_IMMEDIATE
, OP_SH_IMMEDIATE
); break;
7442 case 'v': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
7443 case 'w': USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
7446 case 'P': USE_BITS (OP_MASK_PERFREG
, OP_SH_PERFREG
); break;
7447 case 'U': USE_BITS (OP_MASK_RD
, OP_SH_RD
);
7448 USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
7450 as_bad (_("internal: bad mips opcode (unknown operand type `%c'): %s %s"),
7451 c
, opc
->name
, opc
->args
);
7455 if (used_bits
!= 0xffffffff)
7457 as_bad (_("internal: bad mips opcode (bits 0x%lx undefined): %s %s"),
7458 ~used_bits
& 0xffffffff, opc
->name
, opc
->args
);
7464 /* This routine assembles an instruction into its binary format. As a
7465 side effect, it sets one of the global variables imm_reloc or
7466 offset_reloc to the type of relocation to do if one of the operands
7467 is an address expression. */
7472 struct mips_cl_insn
*ip
;
7477 struct mips_opcode
*insn
;
7480 unsigned int lastregno
= 0;
7483 int full_opcode_match
= 1;
7487 /* If the instruction contains a '.', we first try to match an instruction
7488 including the '.'. Then we try again without the '.'. */
7490 for (s
= str
; *s
!= '\0' && !ISSPACE (*s
); ++s
)
7493 /* If we stopped on whitespace, then replace the whitespace with null for
7494 the call to hash_find. Save the character we replaced just in case we
7495 have to re-parse the instruction. */
7502 insn
= (struct mips_opcode
*) hash_find (op_hash
, str
);
7504 /* If we didn't find the instruction in the opcode table, try again, but
7505 this time with just the instruction up to, but not including the
7509 /* Restore the character we overwrite above (if any). */
7513 /* Scan up to the first '.' or whitespace. */
7515 *s
!= '\0' && *s
!= '.' && !ISSPACE (*s
);
7519 /* If we did not find a '.', then we can quit now. */
7522 insn_error
= "unrecognized opcode";
7526 /* Lookup the instruction in the hash table. */
7528 if ((insn
= (struct mips_opcode
*) hash_find (op_hash
, str
)) == NULL
)
7530 insn_error
= "unrecognized opcode";
7534 full_opcode_match
= 0;
7542 assert (strcmp (insn
->name
, str
) == 0);
7544 if (OPCODE_IS_MEMBER (insn
, mips_opts
.isa
, mips_arch
))
7549 if (insn
->pinfo
!= INSN_MACRO
)
7551 if (mips_arch
== CPU_R4650
&& (insn
->pinfo
& FP_D
) != 0)
7557 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
]
7558 && strcmp (insn
->name
, insn
[1].name
) == 0)
7567 static char buf
[100];
7569 _("opcode not supported on this processor: %s (%s)"),
7570 mips_cpu_to_str (mips_arch
),
7571 mips_isa_to_str (mips_opts
.isa
));
7582 ip
->insn_opcode
= insn
->match
;
7584 for (args
= insn
->args
;; ++args
)
7586 s
+= strspn (s
, " \t");
7589 case '\0': /* end of args */
7602 ip
->insn_opcode
|= lastregno
<< OP_SH_RS
;
7606 ip
->insn_opcode
|= lastregno
<< OP_SH_RT
;
7610 ip
->insn_opcode
|= lastregno
<< OP_SH_FT
;
7614 ip
->insn_opcode
|= lastregno
<< OP_SH_FS
;
7620 /* Handle optional base register.
7621 Either the base register is omitted or
7622 we must have a left paren. */
7623 /* This is dependent on the next operand specifier
7624 is a base register specification. */
7625 assert (args
[1] == 'b' || args
[1] == '5'
7626 || args
[1] == '-' || args
[1] == '4');
7630 case ')': /* these must match exactly */
7635 case '<': /* must be at least one digit */
7637 * According to the manual, if the shift amount is greater
7638 * than 31 or less than 0, then the shift amount should be
7639 * mod 32. In reality the mips assembler issues an error.
7640 * We issue a warning and mask out all but the low 5 bits.
7642 my_getExpression (&imm_expr
, s
);
7643 check_absolute_expr (ip
, &imm_expr
);
7644 if ((unsigned long) imm_expr
.X_add_number
> 31)
7646 as_warn (_("Improper shift amount (%ld)"),
7647 (long) imm_expr
.X_add_number
);
7648 imm_expr
.X_add_number
&= OP_MASK_SHAMT
;
7650 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_SHAMT
;
7651 imm_expr
.X_op
= O_absent
;
7655 case '>': /* shift amount minus 32 */
7656 my_getExpression (&imm_expr
, s
);
7657 check_absolute_expr (ip
, &imm_expr
);
7658 if ((unsigned long) imm_expr
.X_add_number
< 32
7659 || (unsigned long) imm_expr
.X_add_number
> 63)
7661 ip
->insn_opcode
|= (imm_expr
.X_add_number
- 32) << OP_SH_SHAMT
;
7662 imm_expr
.X_op
= O_absent
;
7666 case 'k': /* cache code */
7667 case 'h': /* prefx code */
7668 my_getExpression (&imm_expr
, s
);
7669 check_absolute_expr (ip
, &imm_expr
);
7670 if ((unsigned long) imm_expr
.X_add_number
> 31)
7672 as_warn (_("Invalid value for `%s' (%lu)"),
7674 (unsigned long) imm_expr
.X_add_number
);
7675 imm_expr
.X_add_number
&= 0x1f;
7678 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_CACHE
;
7680 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_PREFX
;
7681 imm_expr
.X_op
= O_absent
;
7685 case 'c': /* break code */
7686 my_getExpression (&imm_expr
, s
);
7687 check_absolute_expr (ip
, &imm_expr
);
7688 if ((unsigned) imm_expr
.X_add_number
> 1023)
7690 as_warn (_("Illegal break code (%ld)"),
7691 (long) imm_expr
.X_add_number
);
7692 imm_expr
.X_add_number
&= OP_MASK_CODE
;
7694 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_CODE
;
7695 imm_expr
.X_op
= O_absent
;
7699 case 'q': /* lower break code */
7700 my_getExpression (&imm_expr
, s
);
7701 check_absolute_expr (ip
, &imm_expr
);
7702 if ((unsigned) imm_expr
.X_add_number
> 1023)
7704 as_warn (_("Illegal lower break code (%ld)"),
7705 (long) imm_expr
.X_add_number
);
7706 imm_expr
.X_add_number
&= OP_MASK_CODE2
;
7708 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_CODE2
;
7709 imm_expr
.X_op
= O_absent
;
7713 case 'B': /* 20-bit syscall/break code. */
7714 my_getExpression (&imm_expr
, s
);
7715 check_absolute_expr (ip
, &imm_expr
);
7716 if ((unsigned) imm_expr
.X_add_number
> OP_MASK_CODE20
)
7717 as_warn (_("Illegal 20-bit code (%ld)"),
7718 (long) imm_expr
.X_add_number
);
7719 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_CODE20
;
7720 imm_expr
.X_op
= O_absent
;
7724 case 'C': /* Coprocessor code */
7725 my_getExpression (&imm_expr
, s
);
7726 check_absolute_expr (ip
, &imm_expr
);
7727 if ((unsigned long) imm_expr
.X_add_number
>= (1<<25))
7729 as_warn (_("Coproccesor code > 25 bits (%ld)"),
7730 (long) imm_expr
.X_add_number
);
7731 imm_expr
.X_add_number
&= ((1<<25) - 1);
7733 ip
->insn_opcode
|= imm_expr
.X_add_number
;
7734 imm_expr
.X_op
= O_absent
;
7738 case 'J': /* 19-bit wait code. */
7739 my_getExpression (&imm_expr
, s
);
7740 check_absolute_expr (ip
, &imm_expr
);
7741 if ((unsigned) imm_expr
.X_add_number
> OP_MASK_CODE19
)
7742 as_warn (_("Illegal 19-bit code (%ld)"),
7743 (long) imm_expr
.X_add_number
);
7744 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_CODE19
;
7745 imm_expr
.X_op
= O_absent
;
7749 case 'P': /* Performance register */
7750 my_getExpression (&imm_expr
, s
);
7751 check_absolute_expr (ip
, &imm_expr
);
7752 if (imm_expr
.X_add_number
!= 0 && imm_expr
.X_add_number
!= 1)
7754 as_warn (_("Invalid performance register (%ld)"),
7755 (long) imm_expr
.X_add_number
);
7756 imm_expr
.X_add_number
&= OP_MASK_PERFREG
;
7758 ip
->insn_opcode
|= (imm_expr
.X_add_number
<< OP_SH_PERFREG
);
7759 imm_expr
.X_op
= O_absent
;
7763 case 'b': /* base register */
7764 case 'd': /* destination register */
7765 case 's': /* source register */
7766 case 't': /* target register */
7767 case 'r': /* both target and source */
7768 case 'v': /* both dest and source */
7769 case 'w': /* both dest and target */
7770 case 'E': /* coprocessor target register */
7771 case 'G': /* coprocessor destination register */
7772 case 'x': /* ignore register name */
7773 case 'z': /* must be zero register */
7774 case 'U': /* destination register (clo/clz). */
7789 while (ISDIGIT (*s
));
7791 as_bad (_("Invalid register number (%d)"), regno
);
7793 else if (*args
== 'E' || *args
== 'G')
7797 if (s
[1] == 'f' && s
[2] == 'p')
7802 else if (s
[1] == 's' && s
[2] == 'p')
7807 else if (s
[1] == 'g' && s
[2] == 'p')
7812 else if (s
[1] == 'a' && s
[2] == 't')
7817 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '0')
7822 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '1')
7827 else if (itbl_have_entries
)
7832 p
= s
+ 1; /* advance past '$' */
7833 n
= itbl_get_field (&p
); /* n is name */
7835 /* See if this is a register defined in an
7837 if (itbl_get_reg_val (n
, &r
))
7839 /* Get_field advances to the start of
7840 the next field, so we need to back
7841 rack to the end of the last field. */
7845 s
= strchr (s
, '\0');
7858 as_warn (_("Used $at without \".set noat\""));
7864 if (c
== 'r' || c
== 'v' || c
== 'w')
7871 /* 'z' only matches $0. */
7872 if (c
== 'z' && regno
!= 0)
7875 /* Now that we have assembled one operand, we use the args string
7876 * to figure out where it goes in the instruction. */
7883 ip
->insn_opcode
|= regno
<< OP_SH_RS
;
7887 ip
->insn_opcode
|= regno
<< OP_SH_RD
;
7890 ip
->insn_opcode
|= regno
<< OP_SH_RD
;
7891 ip
->insn_opcode
|= regno
<< OP_SH_RT
;
7896 ip
->insn_opcode
|= regno
<< OP_SH_RT
;
7899 /* This case exists because on the r3000 trunc
7900 expands into a macro which requires a gp
7901 register. On the r6000 or r4000 it is
7902 assembled into a single instruction which
7903 ignores the register. Thus the insn version
7904 is MIPS_ISA2 and uses 'x', and the macro
7905 version is MIPS_ISA1 and uses 't'. */
7908 /* This case is for the div instruction, which
7909 acts differently if the destination argument
7910 is $0. This only matches $0, and is checked
7911 outside the switch. */
7914 /* Itbl operand; not yet implemented. FIXME ?? */
7916 /* What about all other operands like 'i', which
7917 can be specified in the opcode table? */
7927 ip
->insn_opcode
|= lastregno
<< OP_SH_RS
;
7930 ip
->insn_opcode
|= lastregno
<< OP_SH_RT
;
7935 case 'D': /* floating point destination register */
7936 case 'S': /* floating point source register */
7937 case 'T': /* floating point target register */
7938 case 'R': /* floating point source register */
7942 if (s
[0] == '$' && s
[1] == 'f'
7953 while (ISDIGIT (*s
));
7956 as_bad (_("Invalid float register number (%d)"), regno
);
7958 if ((regno
& 1) != 0
7960 && ! (strcmp (str
, "mtc1") == 0
7961 || strcmp (str
, "mfc1") == 0
7962 || strcmp (str
, "lwc1") == 0
7963 || strcmp (str
, "swc1") == 0
7964 || strcmp (str
, "l.s") == 0
7965 || strcmp (str
, "s.s") == 0))
7966 as_warn (_("Float register should be even, was %d"),
7974 if (c
== 'V' || c
== 'W')
7984 ip
->insn_opcode
|= regno
<< OP_SH_FD
;
7988 ip
->insn_opcode
|= regno
<< OP_SH_FS
;
7992 ip
->insn_opcode
|= regno
<< OP_SH_FT
;
7995 ip
->insn_opcode
|= regno
<< OP_SH_FR
;
8005 ip
->insn_opcode
|= lastregno
<< OP_SH_FS
;
8008 ip
->insn_opcode
|= lastregno
<< OP_SH_FT
;
8014 my_getExpression (&imm_expr
, s
);
8015 if (imm_expr
.X_op
!= O_big
8016 && imm_expr
.X_op
!= O_constant
)
8017 insn_error
= _("absolute expression required");
8022 my_getExpression (&offset_expr
, s
);
8023 *imm_reloc
= BFD_RELOC_32
;
8036 unsigned char temp
[8];
8038 unsigned int length
;
8043 /* These only appear as the last operand in an
8044 instruction, and every instruction that accepts
8045 them in any variant accepts them in all variants.
8046 This means we don't have to worry about backing out
8047 any changes if the instruction does not match.
8049 The difference between them is the size of the
8050 floating point constant and where it goes. For 'F'
8051 and 'L' the constant is 64 bits; for 'f' and 'l' it
8052 is 32 bits. Where the constant is placed is based
8053 on how the MIPS assembler does things:
8056 f -- immediate value
8059 The .lit4 and .lit8 sections are only used if
8060 permitted by the -G argument.
8062 When generating embedded PIC code, we use the
8063 .lit8 section but not the .lit4 section (we can do
8064 .lit4 inline easily; we need to put .lit8
8065 somewhere in the data segment, and using .lit8
8066 permits the linker to eventually combine identical
8069 The code below needs to know whether the target register
8070 is 32 or 64 bits wide. It relies on the fact 'f' and
8071 'F' are used with GPR-based instructions and 'l' and
8072 'L' are used with FPR-based instructions. */
8074 f64
= *args
== 'F' || *args
== 'L';
8075 using_gprs
= *args
== 'F' || *args
== 'f';
8077 save_in
= input_line_pointer
;
8078 input_line_pointer
= s
;
8079 err
= md_atof (f64
? 'd' : 'f', (char *) temp
, &len
);
8081 s
= input_line_pointer
;
8082 input_line_pointer
= save_in
;
8083 if (err
!= NULL
&& *err
!= '\0')
8085 as_bad (_("Bad floating point constant: %s"), err
);
8086 memset (temp
, '\0', sizeof temp
);
8087 length
= f64
? 8 : 4;
8090 assert (length
== (unsigned) (f64
? 8 : 4));
8094 && (! USE_GLOBAL_POINTER_OPT
8095 || mips_pic
== EMBEDDED_PIC
8096 || g_switch_value
< 4
8097 || (temp
[0] == 0 && temp
[1] == 0)
8098 || (temp
[2] == 0 && temp
[3] == 0))))
8100 imm_expr
.X_op
= O_constant
;
8101 if (! target_big_endian
)
8102 imm_expr
.X_add_number
= bfd_getl32 (temp
);
8104 imm_expr
.X_add_number
= bfd_getb32 (temp
);
8107 && ! mips_disable_float_construction
8108 /* Constants can only be constructed in GPRs and
8109 copied to FPRs if the GPRs are at least as wide
8110 as the FPRs. Force the constant into memory if
8111 we are using 64-bit FPRs but the GPRs are only
8114 || ! (HAVE_64BIT_FPRS
&& HAVE_32BIT_GPRS
))
8115 && ((temp
[0] == 0 && temp
[1] == 0)
8116 || (temp
[2] == 0 && temp
[3] == 0))
8117 && ((temp
[4] == 0 && temp
[5] == 0)
8118 || (temp
[6] == 0 && temp
[7] == 0)))
8120 /* The value is simple enough to load with a couple of
8121 instructions. If using 32-bit registers, set
8122 imm_expr to the high order 32 bits and offset_expr to
8123 the low order 32 bits. Otherwise, set imm_expr to
8124 the entire 64 bit constant. */
8125 if (using_gprs
? HAVE_32BIT_GPRS
: HAVE_32BIT_FPRS
)
8127 imm_expr
.X_op
= O_constant
;
8128 offset_expr
.X_op
= O_constant
;
8129 if (! target_big_endian
)
8131 imm_expr
.X_add_number
= bfd_getl32 (temp
+ 4);
8132 offset_expr
.X_add_number
= bfd_getl32 (temp
);
8136 imm_expr
.X_add_number
= bfd_getb32 (temp
);
8137 offset_expr
.X_add_number
= bfd_getb32 (temp
+ 4);
8139 if (offset_expr
.X_add_number
== 0)
8140 offset_expr
.X_op
= O_absent
;
8142 else if (sizeof (imm_expr
.X_add_number
) > 4)
8144 imm_expr
.X_op
= O_constant
;
8145 if (! target_big_endian
)
8146 imm_expr
.X_add_number
= bfd_getl64 (temp
);
8148 imm_expr
.X_add_number
= bfd_getb64 (temp
);
8152 imm_expr
.X_op
= O_big
;
8153 imm_expr
.X_add_number
= 4;
8154 if (! target_big_endian
)
8156 generic_bignum
[0] = bfd_getl16 (temp
);
8157 generic_bignum
[1] = bfd_getl16 (temp
+ 2);
8158 generic_bignum
[2] = bfd_getl16 (temp
+ 4);
8159 generic_bignum
[3] = bfd_getl16 (temp
+ 6);
8163 generic_bignum
[0] = bfd_getb16 (temp
+ 6);
8164 generic_bignum
[1] = bfd_getb16 (temp
+ 4);
8165 generic_bignum
[2] = bfd_getb16 (temp
+ 2);
8166 generic_bignum
[3] = bfd_getb16 (temp
);
8172 const char *newname
;
8175 /* Switch to the right section. */
8177 subseg
= now_subseg
;
8180 default: /* unused default case avoids warnings. */
8182 newname
= RDATA_SECTION_NAME
;
8183 if ((USE_GLOBAL_POINTER_OPT
&& g_switch_value
>= 8)
8184 || mips_pic
== EMBEDDED_PIC
)
8188 if (mips_pic
== EMBEDDED_PIC
)
8191 newname
= RDATA_SECTION_NAME
;
8194 assert (!USE_GLOBAL_POINTER_OPT
8195 || g_switch_value
>= 4);
8199 new_seg
= subseg_new (newname
, (subsegT
) 0);
8200 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
8201 bfd_set_section_flags (stdoutput
, new_seg
,
8206 frag_align (*args
== 'l' ? 2 : 3, 0, 0);
8207 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
8208 && strcmp (TARGET_OS
, "elf") != 0)
8209 record_alignment (new_seg
, 4);
8211 record_alignment (new_seg
, *args
== 'l' ? 2 : 3);
8213 as_bad (_("Can't use floating point insn in this section"));
8215 /* Set the argument to the current address in the
8217 offset_expr
.X_op
= O_symbol
;
8218 offset_expr
.X_add_symbol
=
8219 symbol_new ("L0\001", now_seg
,
8220 (valueT
) frag_now_fix (), frag_now
);
8221 offset_expr
.X_add_number
= 0;
8223 /* Put the floating point number into the section. */
8224 p
= frag_more ((int) length
);
8225 memcpy (p
, temp
, length
);
8227 /* Switch back to the original section. */
8228 subseg_set (seg
, subseg
);
8233 case 'i': /* 16 bit unsigned immediate */
8234 case 'j': /* 16 bit signed immediate */
8235 *imm_reloc
= BFD_RELOC_LO16
;
8236 c
= my_getSmallExpression (&imm_expr
, s
);
8241 if (imm_expr
.X_op
== O_constant
)
8242 imm_expr
.X_add_number
=
8243 (imm_expr
.X_add_number
>> 16) & 0xffff;
8245 else if (c
== S_EX_HIGHEST
)
8246 *imm_reloc
= BFD_RELOC_MIPS_HIGHEST
;
8247 else if (c
== S_EX_HIGHER
)
8248 *imm_reloc
= BFD_RELOC_MIPS_HIGHER
;
8249 else if (c
== S_EX_GP_REL
)
8251 /* This occurs in NewABI only. */
8252 c
= my_getSmallExpression (&imm_expr
, s
);
8254 as_bad (_("bad composition of relocations"));
8257 c
= my_getSmallExpression (&imm_expr
, s
);
8259 as_bad (_("bad composition of relocations"));
8262 imm_reloc
[0] = BFD_RELOC_GPREL16
;
8263 imm_reloc
[1] = BFD_RELOC_MIPS_SUB
;
8264 imm_reloc
[2] = BFD_RELOC_LO16
;
8269 else if (c
== S_EX_HI
)
8271 *imm_reloc
= BFD_RELOC_HI16_S
;
8272 imm_unmatched_hi
= true;
8275 *imm_reloc
= BFD_RELOC_HI16
;
8277 else if (imm_expr
.X_op
== O_constant
)
8278 imm_expr
.X_add_number
&= 0xffff;
8282 if ((c
== S_EX_NONE
&& imm_expr
.X_op
!= O_constant
)
8283 || ((imm_expr
.X_add_number
< 0
8284 || imm_expr
.X_add_number
>= 0x10000)
8285 && imm_expr
.X_op
== O_constant
))
8287 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
8288 !strcmp (insn
->name
, insn
[1].name
))
8290 if (imm_expr
.X_op
== O_constant
8291 || imm_expr
.X_op
== O_big
)
8292 as_bad (_("16 bit expression not in range 0..65535"));
8300 /* The upper bound should be 0x8000, but
8301 unfortunately the MIPS assembler accepts numbers
8302 from 0x8000 to 0xffff and sign extends them, and
8303 we want to be compatible. We only permit this
8304 extended range for an instruction which does not
8305 provide any further alternates, since those
8306 alternates may handle other cases. People should
8307 use the numbers they mean, rather than relying on
8308 a mysterious sign extension. */
8309 more
= (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
8310 strcmp (insn
->name
, insn
[1].name
) == 0);
8315 if ((c
== S_EX_NONE
&& imm_expr
.X_op
!= O_constant
)
8316 || ((imm_expr
.X_add_number
< -0x8000
8317 || imm_expr
.X_add_number
>= max
)
8318 && imm_expr
.X_op
== O_constant
)
8320 && imm_expr
.X_add_number
< 0
8322 && imm_expr
.X_unsigned
8323 && sizeof (imm_expr
.X_add_number
) <= 4))
8327 if (imm_expr
.X_op
== O_constant
8328 || imm_expr
.X_op
== O_big
)
8329 as_bad (_("16 bit expression not in range -32768..32767"));
8335 case 'o': /* 16 bit offset */
8336 c
= my_getSmallExpression (&offset_expr
, s
);
8338 /* If this value won't fit into a 16 bit offset, then go
8339 find a macro that will generate the 32 bit offset
8342 && (offset_expr
.X_op
!= O_constant
8343 || offset_expr
.X_add_number
>= 0x8000
8344 || offset_expr
.X_add_number
< -0x8000))
8349 if (offset_expr
.X_op
!= O_constant
)
8351 offset_expr
.X_add_number
=
8352 (offset_expr
.X_add_number
>> 16) & 0xffff;
8354 *offset_reloc
= BFD_RELOC_LO16
;
8358 case 'p': /* pc relative offset */
8359 if (mips_pic
== EMBEDDED_PIC
)
8360 *offset_reloc
= BFD_RELOC_16_PCREL_S2
;
8362 *offset_reloc
= BFD_RELOC_16_PCREL
;
8363 my_getExpression (&offset_expr
, s
);
8367 case 'u': /* upper 16 bits */
8368 c
= my_getSmallExpression (&imm_expr
, s
);
8369 *imm_reloc
= BFD_RELOC_LO16
;
8374 if (imm_expr
.X_op
== O_constant
)
8375 imm_expr
.X_add_number
=
8376 (imm_expr
.X_add_number
>> 16) & 0xffff;
8377 else if (c
== S_EX_HI
)
8379 *imm_reloc
= BFD_RELOC_HI16_S
;
8380 imm_unmatched_hi
= true;
8383 else if (c
== S_EX_HIGHEST
)
8384 *imm_reloc
= BFD_RELOC_MIPS_HIGHEST
;
8385 else if (c
== S_EX_GP_REL
)
8387 /* This occurs in NewABI only. */
8388 c
= my_getSmallExpression (&imm_expr
, s
);
8390 as_bad (_("bad composition of relocations"));
8393 c
= my_getSmallExpression (&imm_expr
, s
);
8395 as_bad (_("bad composition of relocations"));
8398 imm_reloc
[0] = BFD_RELOC_GPREL16
;
8399 imm_reloc
[1] = BFD_RELOC_MIPS_SUB
;
8400 imm_reloc
[2] = BFD_RELOC_HI16_S
;
8406 *imm_reloc
= BFD_RELOC_HI16
;
8408 else if (imm_expr
.X_op
== O_constant
)
8409 imm_expr
.X_add_number
&= 0xffff;
8411 if (imm_expr
.X_op
== O_constant
8412 && (imm_expr
.X_add_number
< 0
8413 || imm_expr
.X_add_number
>= 0x10000))
8414 as_bad (_("lui expression not in range 0..65535"));
8418 case 'a': /* 26 bit address */
8419 my_getExpression (&offset_expr
, s
);
8421 *offset_reloc
= BFD_RELOC_MIPS_JMP
;
8424 case 'N': /* 3 bit branch condition code */
8425 case 'M': /* 3 bit compare condition code */
8426 if (strncmp (s
, "$fcc", 4) != 0)
8436 while (ISDIGIT (*s
));
8438 as_bad (_("invalid condition code register $fcc%d"), regno
);
8440 ip
->insn_opcode
|= regno
<< OP_SH_BCC
;
8442 ip
->insn_opcode
|= regno
<< OP_SH_CCC
;
8446 if (s
[0] == '0' && (s
[1] == 'x' || s
[1] == 'X'))
8457 while (ISDIGIT (*s
));
8460 c
= 8; /* Invalid sel value. */
8463 as_bad (_("invalid coprocessor sub-selection value (0-7)"));
8464 ip
->insn_opcode
|= c
;
8468 as_bad (_("bad char = '%c'\n"), *args
);
8473 /* Args don't match. */
8474 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
8475 !strcmp (insn
->name
, insn
[1].name
))
8479 insn_error
= _("illegal operands");
8484 insn_error
= _("illegal operands");
8489 /* This routine assembles an instruction into its binary format when
8490 assembling for the mips16. As a side effect, it sets one of the
8491 global variables imm_reloc or offset_reloc to the type of
8492 relocation to do if one of the operands is an address expression.
8493 It also sets mips16_small and mips16_ext if the user explicitly
8494 requested a small or extended instruction. */
8499 struct mips_cl_insn
*ip
;
8503 struct mips_opcode
*insn
;
8506 unsigned int lastregno
= 0;
8511 mips16_small
= false;
8514 for (s
= str
; ISLOWER (*s
); ++s
)
8526 if (s
[1] == 't' && s
[2] == ' ')
8529 mips16_small
= true;
8533 else if (s
[1] == 'e' && s
[2] == ' ')
8542 insn_error
= _("unknown opcode");
8546 if (mips_opts
.noautoextend
&& ! mips16_ext
)
8547 mips16_small
= true;
8549 if ((insn
= (struct mips_opcode
*) hash_find (mips16_op_hash
, str
)) == NULL
)
8551 insn_error
= _("unrecognized opcode");
8558 assert (strcmp (insn
->name
, str
) == 0);
8561 ip
->insn_opcode
= insn
->match
;
8562 ip
->use_extend
= false;
8563 imm_expr
.X_op
= O_absent
;
8564 imm_reloc
[0] = BFD_RELOC_UNUSED
;
8565 imm_reloc
[1] = BFD_RELOC_UNUSED
;
8566 imm_reloc
[2] = BFD_RELOC_UNUSED
;
8567 offset_expr
.X_op
= O_absent
;
8568 offset_reloc
[0] = BFD_RELOC_UNUSED
;
8569 offset_reloc
[1] = BFD_RELOC_UNUSED
;
8570 offset_reloc
[2] = BFD_RELOC_UNUSED
;
8571 for (args
= insn
->args
; 1; ++args
)
8578 /* In this switch statement we call break if we did not find
8579 a match, continue if we did find a match, or return if we
8588 /* Stuff the immediate value in now, if we can. */
8589 if (imm_expr
.X_op
== O_constant
8590 && *imm_reloc
> BFD_RELOC_UNUSED
8591 && insn
->pinfo
!= INSN_MACRO
)
8593 mips16_immed (NULL
, 0, *imm_reloc
- BFD_RELOC_UNUSED
,
8594 imm_expr
.X_add_number
, true, mips16_small
,
8595 mips16_ext
, &ip
->insn_opcode
,
8596 &ip
->use_extend
, &ip
->extend
);
8597 imm_expr
.X_op
= O_absent
;
8598 *imm_reloc
= BFD_RELOC_UNUSED
;
8612 ip
->insn_opcode
|= lastregno
<< MIPS16OP_SH_RX
;
8615 ip
->insn_opcode
|= lastregno
<< MIPS16OP_SH_RY
;
8631 ip
->insn_opcode
|= lastregno
<< MIPS16OP_SH_RX
;
8633 ip
->insn_opcode
|= lastregno
<< MIPS16OP_SH_RY
;
8660 while (ISDIGIT (*s
));
8663 as_bad (_("invalid register number (%d)"), regno
);
8669 if (s
[1] == 'f' && s
[2] == 'p')
8674 else if (s
[1] == 's' && s
[2] == 'p')
8679 else if (s
[1] == 'g' && s
[2] == 'p')
8684 else if (s
[1] == 'a' && s
[2] == 't')
8689 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '0')
8694 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '1')
8707 if (c
== 'v' || c
== 'w')
8709 regno
= mips16_to_32_reg_map
[lastregno
];
8723 regno
= mips32_to_16_reg_map
[regno
];
8728 regno
= ILLEGAL_REG
;
8733 regno
= ILLEGAL_REG
;
8738 regno
= ILLEGAL_REG
;
8743 if (regno
== AT
&& ! mips_opts
.noat
)
8744 as_warn (_("used $at without \".set noat\""));
8751 if (regno
== ILLEGAL_REG
)
8758 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_RX
;
8762 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_RY
;
8765 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_RZ
;
8768 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_MOVE32Z
;
8774 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_REGR32
;
8777 regno
= ((regno
& 7) << 2) | ((regno
& 0x18) >> 3);
8778 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_REG32R
;
8788 if (strncmp (s
, "$pc", 3) == 0)
8812 && strncmp (s
+ 1, "gprel(", sizeof "gprel(" - 1) == 0)
8814 /* This is %gprel(SYMBOL). We need to read SYMBOL,
8815 and generate the appropriate reloc. If the text
8816 inside %gprel is not a symbol name with an
8817 optional offset, then we generate a normal reloc
8818 and will probably fail later. */
8819 my_getExpression (&imm_expr
, s
+ sizeof "%gprel" - 1);
8820 if (imm_expr
.X_op
== O_symbol
)
8823 *imm_reloc
= BFD_RELOC_MIPS16_GPREL
;
8825 ip
->use_extend
= true;
8832 /* Just pick up a normal expression. */
8833 my_getExpression (&imm_expr
, s
);
8836 if (imm_expr
.X_op
== O_register
)
8838 /* What we thought was an expression turned out to
8841 if (s
[0] == '(' && args
[1] == '(')
8843 /* It looks like the expression was omitted
8844 before a register indirection, which means
8845 that the expression is implicitly zero. We
8846 still set up imm_expr, so that we handle
8847 explicit extensions correctly. */
8848 imm_expr
.X_op
= O_constant
;
8849 imm_expr
.X_add_number
= 0;
8850 *imm_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
8857 /* We need to relax this instruction. */
8858 *imm_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
8867 /* We use offset_reloc rather than imm_reloc for the PC
8868 relative operands. This lets macros with both
8869 immediate and address operands work correctly. */
8870 my_getExpression (&offset_expr
, s
);
8872 if (offset_expr
.X_op
== O_register
)
8875 /* We need to relax this instruction. */
8876 *offset_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
8880 case '6': /* break code */
8881 my_getExpression (&imm_expr
, s
);
8882 check_absolute_expr (ip
, &imm_expr
);
8883 if ((unsigned long) imm_expr
.X_add_number
> 63)
8885 as_warn (_("Invalid value for `%s' (%lu)"),
8887 (unsigned long) imm_expr
.X_add_number
);
8888 imm_expr
.X_add_number
&= 0x3f;
8890 ip
->insn_opcode
|= imm_expr
.X_add_number
<< MIPS16OP_SH_IMM6
;
8891 imm_expr
.X_op
= O_absent
;
8895 case 'a': /* 26 bit address */
8896 my_getExpression (&offset_expr
, s
);
8898 *offset_reloc
= BFD_RELOC_MIPS16_JMP
;
8899 ip
->insn_opcode
<<= 16;
8902 case 'l': /* register list for entry macro */
8903 case 'L': /* register list for exit macro */
8913 int freg
, reg1
, reg2
;
8915 while (*s
== ' ' || *s
== ',')
8919 as_bad (_("can't parse register list"));
8931 while (ISDIGIT (*s
))
8953 as_bad (_("invalid register list"));
8958 while (ISDIGIT (*s
))
8965 if (freg
&& reg1
== 0 && reg2
== 0 && c
== 'L')
8970 else if (freg
&& reg1
== 0 && reg2
== 1 && c
== 'L')
8975 else if (reg1
== 4 && reg2
>= 4 && reg2
<= 7 && c
!= 'L')
8976 mask
|= (reg2
- 3) << 3;
8977 else if (reg1
== 16 && reg2
>= 16 && reg2
<= 17)
8978 mask
|= (reg2
- 15) << 1;
8979 else if (reg1
== 31 && reg2
== 31)
8983 as_bad (_("invalid register list"));
8987 /* The mask is filled in in the opcode table for the
8988 benefit of the disassembler. We remove it before
8989 applying the actual mask. */
8990 ip
->insn_opcode
&= ~ ((7 << 3) << MIPS16OP_SH_IMM6
);
8991 ip
->insn_opcode
|= mask
<< MIPS16OP_SH_IMM6
;
8995 case 'e': /* extend code */
8996 my_getExpression (&imm_expr
, s
);
8997 check_absolute_expr (ip
, &imm_expr
);
8998 if ((unsigned long) imm_expr
.X_add_number
> 0x7ff)
9000 as_warn (_("Invalid value for `%s' (%lu)"),
9002 (unsigned long) imm_expr
.X_add_number
);
9003 imm_expr
.X_add_number
&= 0x7ff;
9005 ip
->insn_opcode
|= imm_expr
.X_add_number
;
9006 imm_expr
.X_op
= O_absent
;
9016 /* Args don't match. */
9017 if (insn
+ 1 < &mips16_opcodes
[bfd_mips16_num_opcodes
] &&
9018 strcmp (insn
->name
, insn
[1].name
) == 0)
9025 insn_error
= _("illegal operands");
9031 /* This structure holds information we know about a mips16 immediate
9034 struct mips16_immed_operand
9036 /* The type code used in the argument string in the opcode table. */
9038 /* The number of bits in the short form of the opcode. */
9040 /* The number of bits in the extended form of the opcode. */
9042 /* The amount by which the short form is shifted when it is used;
9043 for example, the sw instruction has a shift count of 2. */
9045 /* The amount by which the short form is shifted when it is stored
9046 into the instruction code. */
9048 /* Non-zero if the short form is unsigned. */
9050 /* Non-zero if the extended form is unsigned. */
9052 /* Non-zero if the value is PC relative. */
9056 /* The mips16 immediate operand types. */
9058 static const struct mips16_immed_operand mips16_immed_operands
[] =
9060 { '<', 3, 5, 0, MIPS16OP_SH_RZ
, 1, 1, 0 },
9061 { '>', 3, 5, 0, MIPS16OP_SH_RX
, 1, 1, 0 },
9062 { '[', 3, 6, 0, MIPS16OP_SH_RZ
, 1, 1, 0 },
9063 { ']', 3, 6, 0, MIPS16OP_SH_RX
, 1, 1, 0 },
9064 { '4', 4, 15, 0, MIPS16OP_SH_IMM4
, 0, 0, 0 },
9065 { '5', 5, 16, 0, MIPS16OP_SH_IMM5
, 1, 0, 0 },
9066 { 'H', 5, 16, 1, MIPS16OP_SH_IMM5
, 1, 0, 0 },
9067 { 'W', 5, 16, 2, MIPS16OP_SH_IMM5
, 1, 0, 0 },
9068 { 'D', 5, 16, 3, MIPS16OP_SH_IMM5
, 1, 0, 0 },
9069 { 'j', 5, 16, 0, MIPS16OP_SH_IMM5
, 0, 0, 0 },
9070 { '8', 8, 16, 0, MIPS16OP_SH_IMM8
, 1, 0, 0 },
9071 { 'V', 8, 16, 2, MIPS16OP_SH_IMM8
, 1, 0, 0 },
9072 { 'C', 8, 16, 3, MIPS16OP_SH_IMM8
, 1, 0, 0 },
9073 { 'U', 8, 16, 0, MIPS16OP_SH_IMM8
, 1, 1, 0 },
9074 { 'k', 8, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 0 },
9075 { 'K', 8, 16, 3, MIPS16OP_SH_IMM8
, 0, 0, 0 },
9076 { 'p', 8, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 1 },
9077 { 'q', 11, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 1 },
9078 { 'A', 8, 16, 2, MIPS16OP_SH_IMM8
, 1, 0, 1 },
9079 { 'B', 5, 16, 3, MIPS16OP_SH_IMM5
, 1, 0, 1 },
9080 { 'E', 5, 16, 2, MIPS16OP_SH_IMM5
, 1, 0, 1 }
9083 #define MIPS16_NUM_IMMED \
9084 (sizeof mips16_immed_operands / sizeof mips16_immed_operands[0])
9086 /* Handle a mips16 instruction with an immediate value. This or's the
9087 small immediate value into *INSN. It sets *USE_EXTEND to indicate
9088 whether an extended value is needed; if one is needed, it sets
9089 *EXTEND to the value. The argument type is TYPE. The value is VAL.
9090 If SMALL is true, an unextended opcode was explicitly requested.
9091 If EXT is true, an extended opcode was explicitly requested. If
9092 WARN is true, warn if EXT does not match reality. */
9095 mips16_immed (file
, line
, type
, val
, warn
, small
, ext
, insn
, use_extend
,
9104 unsigned long *insn
;
9105 boolean
*use_extend
;
9106 unsigned short *extend
;
9108 register const struct mips16_immed_operand
*op
;
9109 int mintiny
, maxtiny
;
9112 op
= mips16_immed_operands
;
9113 while (op
->type
!= type
)
9116 assert (op
< mips16_immed_operands
+ MIPS16_NUM_IMMED
);
9121 if (type
== '<' || type
== '>' || type
== '[' || type
== ']')
9124 maxtiny
= 1 << op
->nbits
;
9129 maxtiny
= (1 << op
->nbits
) - 1;
9134 mintiny
= - (1 << (op
->nbits
- 1));
9135 maxtiny
= (1 << (op
->nbits
- 1)) - 1;
9138 /* Branch offsets have an implicit 0 in the lowest bit. */
9139 if (type
== 'p' || type
== 'q')
9142 if ((val
& ((1 << op
->shift
) - 1)) != 0
9143 || val
< (mintiny
<< op
->shift
)
9144 || val
> (maxtiny
<< op
->shift
))
9149 if (warn
&& ext
&& ! needext
)
9150 as_warn_where (file
, line
,
9151 _("extended operand requested but not required"));
9152 if (small
&& needext
)
9153 as_bad_where (file
, line
, _("invalid unextended operand value"));
9155 if (small
|| (! ext
&& ! needext
))
9159 *use_extend
= false;
9160 insnval
= ((val
>> op
->shift
) & ((1 << op
->nbits
) - 1));
9161 insnval
<<= op
->op_shift
;
9166 long minext
, maxext
;
9172 maxext
= (1 << op
->extbits
) - 1;
9176 minext
= - (1 << (op
->extbits
- 1));
9177 maxext
= (1 << (op
->extbits
- 1)) - 1;
9179 if (val
< minext
|| val
> maxext
)
9180 as_bad_where (file
, line
,
9181 _("operand value out of range for instruction"));
9184 if (op
->extbits
== 16)
9186 extval
= ((val
>> 11) & 0x1f) | (val
& 0x7e0);
9189 else if (op
->extbits
== 15)
9191 extval
= ((val
>> 11) & 0xf) | (val
& 0x7f0);
9196 extval
= ((val
& 0x1f) << 6) | (val
& 0x20);
9200 *extend
= (unsigned short) extval
;
9205 static struct percent_op_match
9208 const enum small_ex_type type
;
9212 {"%half", S_EX_HALF
},
9217 {"%gp_rel", S_EX_GP_REL
},
9219 {"%call16", S_EX_CALL16
},
9220 {"%got_disp", S_EX_GOT_DISP
},
9221 {"%got_page", S_EX_GOT_PAGE
},
9222 {"%got_ofst", S_EX_GOT_OFST
},
9223 {"%got_hi", S_EX_GOT_HI
},
9224 {"%got_lo", S_EX_GOT_LO
},
9226 {"%higher", S_EX_HIGHER
},
9227 {"%highest", S_EX_HIGHEST
},
9228 {"%call_hi", S_EX_CALL_HI
},
9229 {"%call_lo", S_EX_CALL_LO
}
9233 /* Parse small expression input. STR gets adjusted to eat up whitespace.
9234 It detects valid "%percent_op(...)" and "($reg)" strings. Percent_op's
9235 can be nested, this is handled by blanking the innermost, parsing the
9236 rest by subsequent calls. */
9239 my_getSmallParser (str
, len
, nestlevel
)
9244 int type
= S_EX_NONE
;
9247 *str
+= strspn (*str
, " \t");
9250 char *b
= *str
+ 1 + strspn (*str
+ 1, " \t");
9253 /* Check for base register. */
9257 && (e
= b
+ strcspn (b
, ") \t"))
9258 && e
- b
> 1 && e
- b
< 4)
9261 && ((b
[1] == 'f' && b
[2] == 'p')
9262 || (b
[1] == 's' && b
[2] == 'p')
9263 || (b
[1] == 'g' && b
[2] == 'p')
9264 || (b
[1] == 'a' && b
[2] == 't')
9266 && ISDIGIT (b
[2]))))
9267 || (ISDIGIT (b
[1])))
9269 *len
= strcspn (*str
, ")") + 1;
9270 return S_EX_REGISTER
;
9274 else if (b
[0] == '%')
9280 /* Some other expression in the braces. */
9281 *len
= strcspn (*str
, ")") + 1;
9283 /* Check for percent_op. */
9284 else if (*str
[0] == '%')
9293 while (ISALPHA (*tmp
) || *tmp
== '_')
9295 *tmp
= TOLOWER (*tmp
);
9298 while (i
< (sizeof (percent_op
) / sizeof (struct percent_op_match
)))
9300 if (strncmp (*str
, percent_op
[i
].str
, strlen (percent_op
[i
].str
)))
9304 type
= percent_op
[i
].type
;
9306 /* Only %hi and %lo are allowed for OldABI. */
9307 if (! HAVE_NEWABI
&& type
!= S_EX_HI
&& type
!= S_EX_LO
)
9310 *len
= strlen (percent_op
[i
].str
);
9317 /* Any other expression. */
9322 my_getSmallExpression (ep
, str
)
9326 static char *oldstr
= NULL
;
9332 /* Don't update oldstr if the last call had nested percent_op's. */
9339 c
= my_getSmallParser (&str
, &len
, &nest_level
);
9340 if (c
!= S_EX_NONE
&& c
!= S_EX_REGISTER
)
9343 while (c
!= S_EX_NONE
&& c
!= S_EX_REGISTER
);
9345 /* A percent_op was encountered. */
9348 /* Don't try to get an expression if it is already blanked out. */
9349 if (*(str
+ strspn (str
+ 1, " )")) != ')')
9353 save
= *(str
+ len
);
9354 *(str
+ len
) = '\0';
9355 my_getExpression (ep
, str
);
9356 *(str
+ len
) = save
;
9360 /* blank out including the % sign. */
9361 char *p
= strrchr (oldstr
, '%');
9362 memset (p
, ' ', str
- p
+ len
);
9367 expr_end
= strchr (str
, ')') + 1;
9371 else if (c
== S_EX_NONE
)
9373 my_getExpression (ep
, str
);
9375 else if (c
== S_EX_REGISTER
)
9377 ep
->X_op
= O_constant
;
9379 ep
->X_add_symbol
= NULL
;
9380 ep
->X_op_symbol
= NULL
;
9381 ep
->X_add_number
= 0;
9385 as_fatal(_("internal error"));
9388 if (nest_level
<= 1)
9395 my_getExpression (ep
, str
)
9402 save_in
= input_line_pointer
;
9403 input_line_pointer
= str
;
9405 expr_end
= input_line_pointer
;
9406 input_line_pointer
= save_in
;
9408 /* If we are in mips16 mode, and this is an expression based on `.',
9409 then we bump the value of the symbol by 1 since that is how other
9410 text symbols are handled. We don't bother to handle complex
9411 expressions, just `.' plus or minus a constant. */
9412 if (mips_opts
.mips16
9413 && ep
->X_op
== O_symbol
9414 && strcmp (S_GET_NAME (ep
->X_add_symbol
), FAKE_LABEL_NAME
) == 0
9415 && S_GET_SEGMENT (ep
->X_add_symbol
) == now_seg
9416 && symbol_get_frag (ep
->X_add_symbol
) == frag_now
9417 && symbol_constant_p (ep
->X_add_symbol
)
9418 && (val
= S_GET_VALUE (ep
->X_add_symbol
)) == frag_now_fix ())
9419 S_SET_VALUE (ep
->X_add_symbol
, val
+ 1);
9422 /* Turn a string in input_line_pointer into a floating point constant
9423 of type TYPE, and store the appropriate bytes in *LITP. The number
9424 of LITTLENUMS emitted is stored in *SIZEP. An error message is
9425 returned, or NULL on OK. */
9428 md_atof (type
, litP
, sizeP
)
9434 LITTLENUM_TYPE words
[4];
9450 return _("bad call to md_atof");
9453 t
= atof_ieee (input_line_pointer
, type
, words
);
9455 input_line_pointer
= t
;
9459 if (! target_big_endian
)
9461 for (i
= prec
- 1; i
>= 0; i
--)
9463 md_number_to_chars (litP
, (valueT
) words
[i
], 2);
9469 for (i
= 0; i
< prec
; i
++)
9471 md_number_to_chars (litP
, (valueT
) words
[i
], 2);
9480 md_number_to_chars (buf
, val
, n
)
9485 if (target_big_endian
)
9486 number_to_chars_bigendian (buf
, val
, n
);
9488 number_to_chars_littleendian (buf
, val
, n
);
9492 static int support_64bit_objects(void)
9494 const char **list
, **l
;
9496 list
= bfd_target_list ();
9497 for (l
= list
; *l
!= NULL
; l
++)
9499 /* This is traditional mips */
9500 if (strcmp (*l
, "elf64-tradbigmips") == 0
9501 || strcmp (*l
, "elf64-tradlittlemips") == 0)
9503 if (strcmp (*l
, "elf64-bigmips") == 0
9504 || strcmp (*l
, "elf64-littlemips") == 0)
9508 return (*l
!= NULL
);
9510 #endif /* OBJ_ELF */
9512 CONST
char *md_shortopts
= "nO::g::G:";
9514 struct option md_longopts
[] =
9516 #define OPTION_MIPS1 (OPTION_MD_BASE + 1)
9517 {"mips0", no_argument
, NULL
, OPTION_MIPS1
},
9518 {"mips1", no_argument
, NULL
, OPTION_MIPS1
},
9519 #define OPTION_MIPS2 (OPTION_MD_BASE + 2)
9520 {"mips2", no_argument
, NULL
, OPTION_MIPS2
},
9521 #define OPTION_MIPS3 (OPTION_MD_BASE + 3)
9522 {"mips3", no_argument
, NULL
, OPTION_MIPS3
},
9523 #define OPTION_MIPS4 (OPTION_MD_BASE + 4)
9524 {"mips4", no_argument
, NULL
, OPTION_MIPS4
},
9525 #define OPTION_MIPS5 (OPTION_MD_BASE + 5)
9526 {"mips5", no_argument
, NULL
, OPTION_MIPS5
},
9527 #define OPTION_MIPS32 (OPTION_MD_BASE + 6)
9528 {"mips32", no_argument
, NULL
, OPTION_MIPS32
},
9529 #define OPTION_MIPS64 (OPTION_MD_BASE + 7)
9530 {"mips64", no_argument
, NULL
, OPTION_MIPS64
},
9531 #define OPTION_MEMBEDDED_PIC (OPTION_MD_BASE + 8)
9532 {"membedded-pic", no_argument
, NULL
, OPTION_MEMBEDDED_PIC
},
9533 #define OPTION_TRAP (OPTION_MD_BASE + 9)
9534 {"trap", no_argument
, NULL
, OPTION_TRAP
},
9535 {"no-break", no_argument
, NULL
, OPTION_TRAP
},
9536 #define OPTION_BREAK (OPTION_MD_BASE + 10)
9537 {"break", no_argument
, NULL
, OPTION_BREAK
},
9538 {"no-trap", no_argument
, NULL
, OPTION_BREAK
},
9539 #define OPTION_EB (OPTION_MD_BASE + 11)
9540 {"EB", no_argument
, NULL
, OPTION_EB
},
9541 #define OPTION_EL (OPTION_MD_BASE + 12)
9542 {"EL", no_argument
, NULL
, OPTION_EL
},
9543 #define OPTION_MIPS16 (OPTION_MD_BASE + 13)
9544 {"mips16", no_argument
, NULL
, OPTION_MIPS16
},
9545 #define OPTION_NO_MIPS16 (OPTION_MD_BASE + 14)
9546 {"no-mips16", no_argument
, NULL
, OPTION_NO_MIPS16
},
9547 #define OPTION_M7000_HILO_FIX (OPTION_MD_BASE + 15)
9548 {"mfix7000", no_argument
, NULL
, OPTION_M7000_HILO_FIX
},
9549 #define OPTION_NO_M7000_HILO_FIX (OPTION_MD_BASE + 16)
9550 {"no-fix-7000", no_argument
, NULL
, OPTION_NO_M7000_HILO_FIX
},
9551 #define OPTION_FP32 (OPTION_MD_BASE + 17)
9552 {"mfp32", no_argument
, NULL
, OPTION_FP32
},
9553 #define OPTION_GP32 (OPTION_MD_BASE + 18)
9554 {"mgp32", no_argument
, NULL
, OPTION_GP32
},
9555 #define OPTION_CONSTRUCT_FLOATS (OPTION_MD_BASE + 19)
9556 {"construct-floats", no_argument
, NULL
, OPTION_CONSTRUCT_FLOATS
},
9557 #define OPTION_NO_CONSTRUCT_FLOATS (OPTION_MD_BASE + 20)
9558 {"no-construct-floats", no_argument
, NULL
, OPTION_NO_CONSTRUCT_FLOATS
},
9559 #define OPTION_MARCH (OPTION_MD_BASE + 21)
9560 {"march", required_argument
, NULL
, OPTION_MARCH
},
9561 #define OPTION_MTUNE (OPTION_MD_BASE + 22)
9562 {"mtune", required_argument
, NULL
, OPTION_MTUNE
},
9563 #define OPTION_MCPU (OPTION_MD_BASE + 23)
9564 {"mcpu", required_argument
, NULL
, OPTION_MCPU
},
9565 #define OPTION_M4650 (OPTION_MD_BASE + 24)
9566 {"m4650", no_argument
, NULL
, OPTION_M4650
},
9567 #define OPTION_NO_M4650 (OPTION_MD_BASE + 25)
9568 {"no-m4650", no_argument
, NULL
, OPTION_NO_M4650
},
9569 #define OPTION_M4010 (OPTION_MD_BASE + 26)
9570 {"m4010", no_argument
, NULL
, OPTION_M4010
},
9571 #define OPTION_NO_M4010 (OPTION_MD_BASE + 27)
9572 {"no-m4010", no_argument
, NULL
, OPTION_NO_M4010
},
9573 #define OPTION_M4100 (OPTION_MD_BASE + 28)
9574 {"m4100", no_argument
, NULL
, OPTION_M4100
},
9575 #define OPTION_NO_M4100 (OPTION_MD_BASE + 29)
9576 {"no-m4100", no_argument
, NULL
, OPTION_NO_M4100
},
9577 #define OPTION_M3900 (OPTION_MD_BASE + 30)
9578 {"m3900", no_argument
, NULL
, OPTION_M3900
},
9579 #define OPTION_NO_M3900 (OPTION_MD_BASE + 31)
9580 {"no-m3900", no_argument
, NULL
, OPTION_NO_M3900
},
9581 #define OPTION_GP64 (OPTION_MD_BASE + 32)
9582 {"mgp64", no_argument
, NULL
, OPTION_GP64
},
9584 #define OPTION_ELF_BASE (OPTION_MD_BASE + 33)
9585 #define OPTION_CALL_SHARED (OPTION_ELF_BASE + 0)
9586 {"KPIC", no_argument
, NULL
, OPTION_CALL_SHARED
},
9587 {"call_shared", no_argument
, NULL
, OPTION_CALL_SHARED
},
9588 #define OPTION_NON_SHARED (OPTION_ELF_BASE + 1)
9589 {"non_shared", no_argument
, NULL
, OPTION_NON_SHARED
},
9590 #define OPTION_XGOT (OPTION_ELF_BASE + 2)
9591 {"xgot", no_argument
, NULL
, OPTION_XGOT
},
9592 #define OPTION_MABI (OPTION_ELF_BASE + 3)
9593 {"mabi", required_argument
, NULL
, OPTION_MABI
},
9594 #define OPTION_32 (OPTION_ELF_BASE + 4)
9595 {"32", no_argument
, NULL
, OPTION_32
},
9596 #define OPTION_N32 (OPTION_ELF_BASE + 5)
9597 {"n32", no_argument
, NULL
, OPTION_N32
},
9598 #define OPTION_64 (OPTION_ELF_BASE + 6)
9599 {"64", no_argument
, NULL
, OPTION_64
},
9600 #endif /* OBJ_ELF */
9601 {NULL
, no_argument
, NULL
, 0}
9603 size_t md_longopts_size
= sizeof (md_longopts
);
9606 md_parse_option (c
, arg
)
9612 case OPTION_CONSTRUCT_FLOATS
:
9613 mips_disable_float_construction
= 0;
9616 case OPTION_NO_CONSTRUCT_FLOATS
:
9617 mips_disable_float_construction
= 1;
9629 target_big_endian
= 1;
9633 target_big_endian
= 0;
9641 if (arg
&& arg
[1] == '0')
9651 mips_debug
= atoi (arg
);
9652 /* When the MIPS assembler sees -g or -g2, it does not do
9653 optimizations which limit full symbolic debugging. We take
9654 that to be equivalent to -O0. */
9655 if (mips_debug
== 2)
9660 mips_opts
.isa
= ISA_MIPS1
;
9664 mips_opts
.isa
= ISA_MIPS2
;
9668 mips_opts
.isa
= ISA_MIPS3
;
9672 mips_opts
.isa
= ISA_MIPS4
;
9676 mips_opts
.isa
= ISA_MIPS5
;
9680 mips_opts
.isa
= ISA_MIPS32
;
9684 mips_opts
.isa
= ISA_MIPS64
;
9691 int cpu
= CPU_UNKNOWN
;
9693 /* Identify the processor type. */
9694 if (strcasecmp (arg
, "default") != 0)
9696 const struct mips_cpu_info
*ci
;
9698 ci
= mips_cpu_info_from_name (arg
);
9699 if (ci
== NULL
|| ci
->is_isa
)
9704 as_fatal (_("invalid architecture -mtune=%s"), arg
);
9707 as_fatal (_("invalid architecture -march=%s"), arg
);
9710 as_fatal (_("invalid architecture -mcpu=%s"), arg
);
9721 if (mips_tune
!= CPU_UNKNOWN
&& mips_tune
!= cpu
)
9722 as_warn(_("A different -mtune= was already specified, is now "
9727 if (mips_arch
!= CPU_UNKNOWN
&& mips_arch
!= cpu
)
9728 as_warn(_("A different -march= was already specified, is now "
9733 if (mips_cpu
!= CPU_UNKNOWN
&& mips_cpu
!= cpu
)
9734 as_warn(_("A different -mcpu= was already specified, is now "
9742 if ((mips_arch
!= CPU_UNKNOWN
&& mips_arch
!= CPU_R4650
)
9743 || (mips_tune
!= CPU_UNKNOWN
&& mips_tune
!= CPU_R4650
))
9744 as_warn(_("A different -march= or -mtune= was already specified, "
9746 mips_arch
= CPU_R4650
;
9747 mips_tune
= CPU_R4650
;
9750 case OPTION_NO_M4650
:
9754 if ((mips_arch
!= CPU_UNKNOWN
&& mips_arch
!= CPU_R4010
)
9755 || (mips_tune
!= CPU_UNKNOWN
&& mips_tune
!= CPU_R4010
))
9756 as_warn(_("A different -march= or -mtune= was already specified, "
9758 mips_arch
= CPU_R4010
;
9759 mips_tune
= CPU_R4010
;
9762 case OPTION_NO_M4010
:
9766 if ((mips_arch
!= CPU_UNKNOWN
&& mips_arch
!= CPU_VR4100
)
9767 || (mips_tune
!= CPU_UNKNOWN
&& mips_tune
!= CPU_VR4100
))
9768 as_warn(_("A different -march= or -mtune= was already specified, "
9770 mips_arch
= CPU_VR4100
;
9771 mips_tune
= CPU_VR4100
;
9774 case OPTION_NO_M4100
:
9778 if ((mips_arch
!= CPU_UNKNOWN
&& mips_arch
!= CPU_R3900
)
9779 || (mips_tune
!= CPU_UNKNOWN
&& mips_tune
!= CPU_R3900
))
9780 as_warn(_("A different -march= or -mtune= was already specified, "
9782 mips_arch
= CPU_R3900
;
9783 mips_tune
= CPU_R3900
;
9786 case OPTION_NO_M3900
:
9790 mips_opts
.mips16
= 1;
9791 mips_no_prev_insn (false);
9794 case OPTION_NO_MIPS16
:
9795 mips_opts
.mips16
= 0;
9796 mips_no_prev_insn (false);
9799 case OPTION_MEMBEDDED_PIC
:
9800 mips_pic
= EMBEDDED_PIC
;
9801 if (USE_GLOBAL_POINTER_OPT
&& g_switch_seen
)
9803 as_bad (_("-G may not be used with embedded PIC code"));
9806 g_switch_value
= 0x7fffffff;
9810 /* When generating ELF code, we permit -KPIC and -call_shared to
9811 select SVR4_PIC, and -non_shared to select no PIC. This is
9812 intended to be compatible with Irix 5. */
9813 case OPTION_CALL_SHARED
:
9814 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
9816 as_bad (_("-call_shared is supported only for ELF format"));
9819 mips_pic
= SVR4_PIC
;
9820 if (g_switch_seen
&& g_switch_value
!= 0)
9822 as_bad (_("-G may not be used with SVR4 PIC code"));
9828 case OPTION_NON_SHARED
:
9829 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
9831 as_bad (_("-non_shared is supported only for ELF format"));
9837 /* The -xgot option tells the assembler to use 32 offsets when
9838 accessing the got in SVR4_PIC mode. It is for Irix
9843 #endif /* OBJ_ELF */
9846 if (! USE_GLOBAL_POINTER_OPT
)
9848 as_bad (_("-G is not supported for this configuration"));
9851 else if (mips_pic
== SVR4_PIC
|| mips_pic
== EMBEDDED_PIC
)
9853 as_bad (_("-G may not be used with SVR4 or embedded PIC code"));
9857 g_switch_value
= atoi (arg
);
9862 /* The -32 and -64 options tell the assembler to output the 32
9863 bit or the 64 bit MIPS ELF format. */
9865 mips_opts
.abi
= O32_ABI
;
9869 mips_opts
.abi
= N32_ABI
;
9873 mips_opts
.abi
= N64_ABI
;
9874 if (! support_64bit_objects())
9875 as_fatal (_("No compiled in support for 64 bit object file format"));
9877 #endif /* OBJ_ELF */
9881 if (mips_opts
.abi
!= O32_ABI
)
9882 mips_opts
.abi
= NO_ABI
;
9887 if (mips_opts
.abi
== O32_ABI
)
9888 mips_opts
.abi
= NO_ABI
;
9893 if (mips_opts
.abi
!= O32_ABI
)
9894 mips_opts
.abi
= NO_ABI
;
9899 if (strcmp (arg
, "32") == 0)
9900 mips_opts
.abi
= O32_ABI
;
9901 else if (strcmp (arg
, "o64") == 0)
9902 mips_opts
.abi
= O64_ABI
;
9903 else if (strcmp (arg
, "n32") == 0)
9904 mips_opts
.abi
= N32_ABI
;
9905 else if (strcmp (arg
, "64") == 0)
9907 mips_opts
.abi
= N64_ABI
;
9908 if (! support_64bit_objects())
9909 as_fatal (_("No compiled in support for 64 bit object file "
9912 else if (strcmp (arg
, "eabi") == 0)
9913 mips_opts
.abi
= EABI_ABI
;
9915 mips_opts
.abi
= NO_ABI
;
9917 #endif /* OBJ_ELF */
9919 case OPTION_M7000_HILO_FIX
:
9920 mips_7000_hilo_fix
= true;
9923 case OPTION_NO_M7000_HILO_FIX
:
9924 mips_7000_hilo_fix
= false;
9935 show (stream
, string
, col_p
, first_p
)
9943 fprintf (stream
, "%24s", "");
9948 fprintf (stream
, ", ");
9952 if (*col_p
+ strlen (string
) > 72)
9954 fprintf (stream
, "\n%24s", "");
9958 fprintf (stream
, "%s", string
);
9959 *col_p
+= strlen (string
);
9965 md_show_usage (stream
)
9970 fprintf (stream
, _("\
9972 -membedded-pic generate embedded position independent code\n\
9973 -EB generate big endian output\n\
9974 -EL generate little endian output\n\
9975 -g, -g2 do not remove unneeded NOPs or swap branches\n\
9976 -G NUM allow referencing objects up to NUM bytes\n\
9977 implicitly with the gp register [default 8]\n"));
9978 fprintf (stream
, _("\
9979 -mips1 generate MIPS ISA I instructions\n\
9980 -mips2 generate MIPS ISA II instructions\n\
9981 -mips3 generate MIPS ISA III instructions\n\
9982 -mips4 generate MIPS ISA IV instructions\n\
9983 -mips5 generate MIPS ISA V instructions\n\
9984 -mips32 generate MIPS32 ISA instructions\n\
9985 -mips64 generate MIPS64 ISA instructions\n\
9986 -march=CPU/-mtune=CPU generate code/schedule for CPU, where CPU is one of:\n"));
9990 show (stream
, "2000", &column
, &first
);
9991 show (stream
, "3000", &column
, &first
);
9992 show (stream
, "3900", &column
, &first
);
9993 show (stream
, "4000", &column
, &first
);
9994 show (stream
, "4010", &column
, &first
);
9995 show (stream
, "4100", &column
, &first
);
9996 show (stream
, "4111", &column
, &first
);
9997 show (stream
, "4300", &column
, &first
);
9998 show (stream
, "4400", &column
, &first
);
9999 show (stream
, "4600", &column
, &first
);
10000 show (stream
, "4650", &column
, &first
);
10001 show (stream
, "5000", &column
, &first
);
10002 show (stream
, "5200", &column
, &first
);
10003 show (stream
, "5230", &column
, &first
);
10004 show (stream
, "5231", &column
, &first
);
10005 show (stream
, "5261", &column
, &first
);
10006 show (stream
, "5721", &column
, &first
);
10007 show (stream
, "6000", &column
, &first
);
10008 show (stream
, "8000", &column
, &first
);
10009 show (stream
, "10000", &column
, &first
);
10010 show (stream
, "12000", &column
, &first
);
10011 show (stream
, "sb1", &column
, &first
);
10012 fputc ('\n', stream
);
10014 fprintf (stream
, _("\
10015 -mCPU equivalent to -march=CPU -mtune=CPU. Deprecated.\n\
10016 -no-mCPU don't generate code specific to CPU.\n\
10017 For -mCPU and -no-mCPU, CPU must be one of:\n"));
10021 show (stream
, "3900", &column
, &first
);
10022 show (stream
, "4010", &column
, &first
);
10023 show (stream
, "4100", &column
, &first
);
10024 show (stream
, "4650", &column
, &first
);
10025 fputc ('\n', stream
);
10027 fprintf (stream
, _("\
10028 -mips16 generate mips16 instructions\n\
10029 -no-mips16 do not generate mips16 instructions\n"));
10030 fprintf (stream
, _("\
10031 -mgp32 use 32-bit GPRs, regardless of the chosen ISA\n\
10032 -mfp32 use 32-bit FPRs, regardless of the chosen ISA\n\
10033 -O0 remove unneeded NOPs, do not swap branches\n\
10034 -O remove unneeded NOPs and swap branches\n\
10035 -n warn about NOPs generated from macros\n\
10036 --[no-]construct-floats [dis]allow floating point values to be constructed\n\
10037 --trap, --no-break trap exception on div by 0 and mult overflow\n\
10038 --break, --no-trap break exception on div by 0 and mult overflow\n"));
10040 fprintf (stream
, _("\
10041 -KPIC, -call_shared generate SVR4 position independent code\n\
10042 -non_shared do not generate position independent code\n\
10043 -xgot assume a 32 bit GOT\n\
10044 -32 create o32 ABI object file (default)\n\
10045 -n32 create n32 ABI object file\n\
10046 -64 create 64 ABI object file\n"));
10051 mips_init_after_args ()
10053 /* initialize opcodes */
10054 bfd_mips_num_opcodes
= bfd_mips_num_builtin_opcodes
;
10055 mips_opcodes
= (struct mips_opcode
*) mips_builtin_opcodes
;
10059 md_pcrel_from (fixP
)
10062 if (OUTPUT_FLAVOR
!= bfd_target_aout_flavour
10063 && fixP
->fx_addsy
!= (symbolS
*) NULL
10064 && ! S_IS_DEFINED (fixP
->fx_addsy
))
10066 /* This makes a branch to an undefined symbol be a branch to the
10067 current location. */
10068 if (mips_pic
== EMBEDDED_PIC
)
10074 /* return the address of the delay slot */
10075 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
10078 /* This is called before the symbol table is processed. In order to
10079 work with gcc when using mips-tfile, we must keep all local labels.
10080 However, in other cases, we want to discard them. If we were
10081 called with -g, but we didn't see any debugging information, it may
10082 mean that gcc is smuggling debugging information through to
10083 mips-tfile, in which case we must generate all local labels. */
10086 mips_frob_file_before_adjust ()
10088 #ifndef NO_ECOFF_DEBUGGING
10089 if (ECOFF_DEBUGGING
10091 && ! ecoff_debugging_seen
)
10092 flag_keep_locals
= 1;
10096 /* Sort any unmatched HI16_S relocs so that they immediately precede
10097 the corresponding LO reloc. This is called before md_apply_fix and
10098 tc_gen_reloc. Unmatched HI16_S relocs can only be generated by
10099 explicit use of the %hi modifier. */
10104 struct mips_hi_fixup
*l
;
10106 for (l
= mips_hi_fixup_list
; l
!= NULL
; l
= l
->next
)
10108 segment_info_type
*seginfo
;
10111 assert (l
->fixp
->fx_r_type
== BFD_RELOC_HI16_S
);
10113 /* Check quickly whether the next fixup happens to be a matching
10115 if (l
->fixp
->fx_next
!= NULL
10116 && l
->fixp
->fx_next
->fx_r_type
== BFD_RELOC_LO16
10117 && l
->fixp
->fx_addsy
== l
->fixp
->fx_next
->fx_addsy
10118 && l
->fixp
->fx_offset
== l
->fixp
->fx_next
->fx_offset
)
10121 /* Look through the fixups for this segment for a matching %lo.
10122 When we find one, move the %hi just in front of it. We do
10123 this in two passes. In the first pass, we try to find a
10124 unique %lo. In the second pass, we permit multiple %hi
10125 relocs for a single %lo (this is a GNU extension). */
10126 seginfo
= seg_info (l
->seg
);
10127 for (pass
= 0; pass
< 2; pass
++)
10132 for (f
= seginfo
->fix_root
; f
!= NULL
; f
= f
->fx_next
)
10134 /* Check whether this is a %lo fixup which matches l->fixp. */
10135 if (f
->fx_r_type
== BFD_RELOC_LO16
10136 && f
->fx_addsy
== l
->fixp
->fx_addsy
10137 && f
->fx_offset
== l
->fixp
->fx_offset
10140 || prev
->fx_r_type
!= BFD_RELOC_HI16_S
10141 || prev
->fx_addsy
!= f
->fx_addsy
10142 || prev
->fx_offset
!= f
->fx_offset
))
10146 /* Move l->fixp before f. */
10147 for (pf
= &seginfo
->fix_root
;
10149 pf
= &(*pf
)->fx_next
)
10150 assert (*pf
!= NULL
);
10152 *pf
= l
->fixp
->fx_next
;
10154 l
->fixp
->fx_next
= f
;
10156 seginfo
->fix_root
= l
->fixp
;
10158 prev
->fx_next
= l
->fixp
;
10169 #if 0 /* GCC code motion plus incomplete dead code elimination
10170 can leave a %hi without a %lo. */
10172 as_warn_where (l
->fixp
->fx_file
, l
->fixp
->fx_line
,
10173 _("Unmatched %%hi reloc"));
10179 /* When generating embedded PIC code we need to use a special
10180 relocation to represent the difference of two symbols in the .text
10181 section (switch tables use a difference of this sort). See
10182 include/coff/mips.h for details. This macro checks whether this
10183 fixup requires the special reloc. */
10184 #define SWITCH_TABLE(fixp) \
10185 ((fixp)->fx_r_type == BFD_RELOC_32 \
10186 && OUTPUT_FLAVOR != bfd_target_elf_flavour \
10187 && (fixp)->fx_addsy != NULL \
10188 && (fixp)->fx_subsy != NULL \
10189 && S_GET_SEGMENT ((fixp)->fx_addsy) == text_section \
10190 && S_GET_SEGMENT ((fixp)->fx_subsy) == text_section)
10192 /* When generating embedded PIC code we must keep all PC relative
10193 relocations, in case the linker has to relax a call. We also need
10194 to keep relocations for switch table entries.
10196 We may have combined relocations without symbols in the N32/N64 ABI.
10197 We have to prevent gas from dropping them. */
10200 mips_force_relocation (fixp
)
10203 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
10204 || fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
10208 && S_GET_SEGMENT (fixp
->fx_addsy
) == bfd_abs_section_ptr
10209 && (fixp
->fx_r_type
== BFD_RELOC_MIPS_SUB
10210 || fixp
->fx_r_type
== BFD_RELOC_HI16_S
10211 || fixp
->fx_r_type
== BFD_RELOC_LO16
))
10214 return (mips_pic
== EMBEDDED_PIC
10216 || SWITCH_TABLE (fixp
)
10217 || fixp
->fx_r_type
== BFD_RELOC_PCREL_HI16_S
10218 || fixp
->fx_r_type
== BFD_RELOC_PCREL_LO16
));
10221 /* Apply a fixup to the object file. */
10224 md_apply_fix (fixP
, valueP
)
10228 unsigned char *buf
;
10232 assert (fixP
->fx_size
== 4
10233 || fixP
->fx_r_type
== BFD_RELOC_16
10234 || fixP
->fx_r_type
== BFD_RELOC_32
10235 || fixP
->fx_r_type
== BFD_RELOC_MIPS_JMP
10236 || fixP
->fx_r_type
== BFD_RELOC_HI16_S
10237 || fixP
->fx_r_type
== BFD_RELOC_LO16
10238 || fixP
->fx_r_type
== BFD_RELOC_GPREL16
10239 || fixP
->fx_r_type
== BFD_RELOC_MIPS_LITERAL
10240 || fixP
->fx_r_type
== BFD_RELOC_GPREL32
10241 || fixP
->fx_r_type
== BFD_RELOC_64
10242 || fixP
->fx_r_type
== BFD_RELOC_CTOR
10243 || fixP
->fx_r_type
== BFD_RELOC_MIPS_SUB
10244 || fixP
->fx_r_type
== BFD_RELOC_MIPS_HIGHEST
10245 || fixP
->fx_r_type
== BFD_RELOC_MIPS_HIGHER
10246 || fixP
->fx_r_type
== BFD_RELOC_MIPS_SCN_DISP
10247 || fixP
->fx_r_type
== BFD_RELOC_MIPS_REL16
10248 || fixP
->fx_r_type
== BFD_RELOC_MIPS_RELGOT
10249 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
10250 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
);
10254 /* If we aren't adjusting this fixup to be against the section
10255 symbol, we need to adjust the value. */
10257 if (fixP
->fx_addsy
!= NULL
&& OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
10259 if (S_GET_OTHER (fixP
->fx_addsy
) == STO_MIPS16
10260 || ((S_IS_WEAK (fixP
->fx_addsy
)
10261 || S_IS_EXTERN (fixP
->fx_addsy
))
10262 && !S_IS_COMMON (fixP
->fx_addsy
))
10263 || (symbol_used_in_reloc_p (fixP
->fx_addsy
)
10264 && (((bfd_get_section_flags (stdoutput
,
10265 S_GET_SEGMENT (fixP
->fx_addsy
))
10266 & SEC_LINK_ONCE
) != 0)
10267 || !strncmp (segment_name (S_GET_SEGMENT (fixP
->fx_addsy
)),
10269 sizeof (".gnu.linkonce") - 1))))
10272 valueT symval
= S_GET_VALUE (fixP
->fx_addsy
);
10275 && ! fixP
->fx_pcrel
10276 && fixP
->fx_r_type
!= BFD_RELOC_MIPS_GPREL
)
10278 /* In this case, the bfd_install_relocation routine will
10279 incorrectly add the symbol value back in. We just want
10280 the addend to appear in the object file. */
10283 /* Make sure the addend is still non-zero. If it became zero
10284 after the last operation, set it to a spurious value and
10285 subtract the same value from the object file's contents. */
10290 /* The in-place addends for LO16 relocations are signed;
10291 leave the matching HI16 in-place addends as zero. */
10292 if (fixP
->fx_r_type
!= BFD_RELOC_HI16_S
)
10294 reloc_howto_type
*howto
;
10295 bfd_vma contents
, mask
, field
;
10297 howto
= bfd_reloc_type_lookup (stdoutput
,
10300 contents
= bfd_get_bits (fixP
->fx_frag
->fr_literal
10303 target_big_endian
);
10305 /* MASK has bits set where the relocation should go.
10306 FIELD is -value, shifted into the appropriate place
10307 for this relocation. */
10308 mask
= 1 << (howto
->bitsize
- 1);
10309 mask
= (((mask
- 1) << 1) | 1) << howto
->bitpos
;
10310 field
= (-value
>> howto
->rightshift
) << howto
->bitpos
;
10312 bfd_put_bits ((field
& mask
) | (contents
& ~mask
),
10313 fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
,
10315 target_big_endian
);
10321 /* This code was generated using trial and error and so is
10322 fragile and not trustworthy. If you change it, you should
10323 rerun the elf-rel, elf-rel2, and empic testcases and ensure
10324 they still pass. */
10325 if (fixP
->fx_pcrel
|| fixP
->fx_subsy
!= NULL
)
10327 value
+= fixP
->fx_frag
->fr_address
+ fixP
->fx_where
;
10329 /* BFD's REL handling, for MIPS, is _very_ weird.
10330 This gives the right results, but it can't possibly
10331 be the way things are supposed to work. */
10332 if ((fixP
->fx_r_type
!= BFD_RELOC_16_PCREL
10333 && fixP
->fx_r_type
!= BFD_RELOC_16_PCREL_S2
)
10334 || S_GET_SEGMENT (fixP
->fx_addsy
) != undefined_section
)
10335 value
+= fixP
->fx_frag
->fr_address
+ fixP
->fx_where
;
10340 fixP
->fx_addnumber
= value
; /* Remember value for tc_gen_reloc */
10342 if (fixP
->fx_addsy
== NULL
&& ! fixP
->fx_pcrel
)
10345 switch (fixP
->fx_r_type
)
10347 case BFD_RELOC_MIPS_JMP
:
10348 case BFD_RELOC_MIPS_SHIFT5
:
10349 case BFD_RELOC_MIPS_SHIFT6
:
10350 case BFD_RELOC_MIPS_GOT_DISP
:
10351 case BFD_RELOC_MIPS_GOT_PAGE
:
10352 case BFD_RELOC_MIPS_GOT_OFST
:
10353 case BFD_RELOC_MIPS_SUB
:
10354 case BFD_RELOC_MIPS_INSERT_A
:
10355 case BFD_RELOC_MIPS_INSERT_B
:
10356 case BFD_RELOC_MIPS_DELETE
:
10357 case BFD_RELOC_MIPS_HIGHEST
:
10358 case BFD_RELOC_MIPS_HIGHER
:
10359 case BFD_RELOC_MIPS_SCN_DISP
:
10360 case BFD_RELOC_MIPS_REL16
:
10361 case BFD_RELOC_MIPS_RELGOT
:
10362 case BFD_RELOC_MIPS_JALR
:
10363 case BFD_RELOC_HI16
:
10364 case BFD_RELOC_HI16_S
:
10365 case BFD_RELOC_MIPS_GPREL
:
10366 case BFD_RELOC_MIPS_LITERAL
:
10367 case BFD_RELOC_MIPS_CALL16
:
10368 case BFD_RELOC_MIPS_GOT16
:
10369 case BFD_RELOC_MIPS_GPREL32
:
10370 case BFD_RELOC_MIPS_GOT_HI16
:
10371 case BFD_RELOC_MIPS_GOT_LO16
:
10372 case BFD_RELOC_MIPS_CALL_HI16
:
10373 case BFD_RELOC_MIPS_CALL_LO16
:
10374 case BFD_RELOC_MIPS16_GPREL
:
10375 if (fixP
->fx_pcrel
)
10376 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
10377 _("Invalid PC relative reloc"));
10378 /* Nothing needed to do. The value comes from the reloc entry */
10381 case BFD_RELOC_MIPS16_JMP
:
10382 /* We currently always generate a reloc against a symbol, which
10383 means that we don't want an addend even if the symbol is
10385 fixP
->fx_addnumber
= 0;
10388 case BFD_RELOC_PCREL_HI16_S
:
10389 /* The addend for this is tricky if it is internal, so we just
10390 do everything here rather than in bfd_install_relocation. */
10391 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
10396 && (symbol_get_bfdsym (fixP
->fx_addsy
)->flags
& BSF_SECTION_SYM
) == 0)
10398 /* For an external symbol adjust by the address to make it
10399 pcrel_offset. We use the address of the RELLO reloc
10400 which follows this one. */
10401 value
+= (fixP
->fx_next
->fx_frag
->fr_address
10402 + fixP
->fx_next
->fx_where
);
10404 value
= ((value
+ 0x8000) >> 16) & 0xffff;
10405 buf
= (unsigned char *) fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
10406 if (target_big_endian
)
10408 md_number_to_chars (buf
, value
, 2);
10411 case BFD_RELOC_PCREL_LO16
:
10412 /* The addend for this is tricky if it is internal, so we just
10413 do everything here rather than in bfd_install_relocation. */
10414 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
10419 && (symbol_get_bfdsym (fixP
->fx_addsy
)->flags
& BSF_SECTION_SYM
) == 0)
10420 value
+= fixP
->fx_frag
->fr_address
+ fixP
->fx_where
;
10421 buf
= (unsigned char *) fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
10422 if (target_big_endian
)
10424 md_number_to_chars (buf
, value
, 2);
10428 /* This is handled like BFD_RELOC_32, but we output a sign
10429 extended value if we are only 32 bits. */
10431 || (mips_pic
== EMBEDDED_PIC
&& SWITCH_TABLE (fixP
)))
10433 if (8 <= sizeof (valueT
))
10434 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
,
10441 w1
= w2
= fixP
->fx_where
;
10442 if (target_big_endian
)
10446 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ w1
, value
, 4);
10447 if ((value
& 0x80000000) != 0)
10451 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ w2
, hiv
, 4);
10456 case BFD_RELOC_RVA
:
10458 /* If we are deleting this reloc entry, we must fill in the
10459 value now. This can happen if we have a .word which is not
10460 resolved when it appears but is later defined. We also need
10461 to fill in the value if this is an embedded PIC switch table
10464 || (mips_pic
== EMBEDDED_PIC
&& SWITCH_TABLE (fixP
)))
10465 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
,
10470 /* If we are deleting this reloc entry, we must fill in the
10472 assert (fixP
->fx_size
== 2);
10474 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
,
10478 case BFD_RELOC_LO16
:
10479 /* When handling an embedded PIC switch statement, we can wind
10480 up deleting a LO16 reloc. See the 'o' case in mips_ip. */
10483 if (value
+ 0x8000 > 0xffff)
10484 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
10485 _("relocation overflow"));
10486 buf
= (unsigned char *) fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
10487 if (target_big_endian
)
10489 md_number_to_chars (buf
, value
, 2);
10493 case BFD_RELOC_16_PCREL_S2
:
10494 if ((value
& 0x3) != 0)
10495 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
10496 _("Branch to odd address (%lx)"), (long) value
);
10498 /* Fall through. */
10500 case BFD_RELOC_16_PCREL
:
10502 * We need to save the bits in the instruction since fixup_segment()
10503 * might be deleting the relocation entry (i.e., a branch within
10504 * the current segment).
10506 if (!fixP
->fx_done
&& value
!= 0)
10508 /* If 'value' is zero, the remaining reloc code won't actually
10509 do the store, so it must be done here. This is probably
10510 a bug somewhere. */
10511 if (!fixP
->fx_done
)
10512 value
-= fixP
->fx_frag
->fr_address
+ fixP
->fx_where
;
10514 value
= (offsetT
) value
>> 2;
10516 /* update old instruction data */
10517 buf
= (unsigned char *) (fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
);
10518 if (target_big_endian
)
10519 insn
= (buf
[0] << 24) | (buf
[1] << 16) | (buf
[2] << 8) | buf
[3];
10521 insn
= (buf
[3] << 24) | (buf
[2] << 16) | (buf
[1] << 8) | buf
[0];
10523 if (value
+ 0x8000 <= 0xffff)
10524 insn
|= value
& 0xffff;
10527 /* The branch offset is too large. If this is an
10528 unconditional branch, and we are not generating PIC code,
10529 we can convert it to an absolute jump instruction. */
10530 if (mips_pic
== NO_PIC
10532 && fixP
->fx_frag
->fr_address
>= text_section
->vma
10533 && (fixP
->fx_frag
->fr_address
10534 < text_section
->vma
+ text_section
->_raw_size
)
10535 && ((insn
& 0xffff0000) == 0x10000000 /* beq $0,$0 */
10536 || (insn
& 0xffff0000) == 0x04010000 /* bgez $0 */
10537 || (insn
& 0xffff0000) == 0x04110000)) /* bgezal $0 */
10539 if ((insn
& 0xffff0000) == 0x04110000) /* bgezal $0 */
10540 insn
= 0x0c000000; /* jal */
10542 insn
= 0x08000000; /* j */
10543 fixP
->fx_r_type
= BFD_RELOC_MIPS_JMP
;
10545 fixP
->fx_addsy
= section_symbol (text_section
);
10546 fixP
->fx_addnumber
= (value
<< 2) + md_pcrel_from (fixP
);
10550 /* FIXME. It would be possible in principle to handle
10551 conditional branches which overflow. They could be
10552 transformed into a branch around a jump. This would
10553 require setting up variant frags for each different
10554 branch type. The native MIPS assembler attempts to
10555 handle these cases, but it appears to do it
10557 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
10558 _("Branch out of range"));
10562 md_number_to_chars ((char *) buf
, (valueT
) insn
, 4);
10565 case BFD_RELOC_VTABLE_INHERIT
:
10568 && !S_IS_DEFINED (fixP
->fx_addsy
)
10569 && !S_IS_WEAK (fixP
->fx_addsy
))
10570 S_SET_WEAK (fixP
->fx_addsy
);
10573 case BFD_RELOC_VTABLE_ENTRY
:
10589 const struct mips_opcode
*p
;
10590 int treg
, sreg
, dreg
, shamt
;
10595 for (i
= 0; i
< NUMOPCODES
; ++i
)
10597 p
= &mips_opcodes
[i
];
10598 if (((oc
& p
->mask
) == p
->match
) && (p
->pinfo
!= INSN_MACRO
))
10600 printf ("%08lx %s\t", oc
, p
->name
);
10601 treg
= (oc
>> 16) & 0x1f;
10602 sreg
= (oc
>> 21) & 0x1f;
10603 dreg
= (oc
>> 11) & 0x1f;
10604 shamt
= (oc
>> 6) & 0x1f;
10606 for (args
= p
->args
;; ++args
)
10617 printf ("%c", *args
);
10621 assert (treg
== sreg
);
10622 printf ("$%d,$%d", treg
, sreg
);
10627 printf ("$%d", dreg
);
10632 printf ("$%d", treg
);
10636 printf ("0x%x", treg
);
10641 printf ("$%d", sreg
);
10645 printf ("0x%08lx", oc
& 0x1ffffff);
10652 printf ("%d", imm
);
10657 printf ("$%d", shamt
);
10668 printf (_("%08lx UNDEFINED\n"), oc
);
10679 name
= input_line_pointer
;
10680 c
= get_symbol_end ();
10681 p
= (symbolS
*) symbol_find_or_make (name
);
10682 *input_line_pointer
= c
;
10686 /* Align the current frag to a given power of two. The MIPS assembler
10687 also automatically adjusts any preceding label. */
10690 mips_align (to
, fill
, label
)
10695 mips_emit_delays (false);
10696 frag_align (to
, fill
, 0);
10697 record_alignment (now_seg
, to
);
10700 assert (S_GET_SEGMENT (label
) == now_seg
);
10701 symbol_set_frag (label
, frag_now
);
10702 S_SET_VALUE (label
, (valueT
) frag_now_fix ());
10706 /* Align to a given power of two. .align 0 turns off the automatic
10707 alignment used by the data creating pseudo-ops. */
10711 int x ATTRIBUTE_UNUSED
;
10714 register long temp_fill
;
10715 long max_alignment
= 15;
10719 o Note that the assembler pulls down any immediately preceeding label
10720 to the aligned address.
10721 o It's not documented but auto alignment is reinstated by
10722 a .align pseudo instruction.
10723 o Note also that after auto alignment is turned off the mips assembler
10724 issues an error on attempt to assemble an improperly aligned data item.
10729 temp
= get_absolute_expression ();
10730 if (temp
> max_alignment
)
10731 as_bad (_("Alignment too large: %d. assumed."), temp
= max_alignment
);
10734 as_warn (_("Alignment negative: 0 assumed."));
10737 if (*input_line_pointer
== ',')
10739 input_line_pointer
++;
10740 temp_fill
= get_absolute_expression ();
10747 mips_align (temp
, (int) temp_fill
,
10748 insn_labels
!= NULL
? insn_labels
->label
: NULL
);
10755 demand_empty_rest_of_line ();
10759 mips_flush_pending_output ()
10761 mips_emit_delays (false);
10762 mips_clear_insn_labels ();
10771 /* When generating embedded PIC code, we only use the .text, .lit8,
10772 .sdata and .sbss sections. We change the .data and .rdata
10773 pseudo-ops to use .sdata. */
10774 if (mips_pic
== EMBEDDED_PIC
10775 && (sec
== 'd' || sec
== 'r'))
10779 /* The ELF backend needs to know that we are changing sections, so
10780 that .previous works correctly. We could do something like check
10781 for an obj_section_change_hook macro, but that might be confusing
10782 as it would not be appropriate to use it in the section changing
10783 functions in read.c, since obj-elf.c intercepts those. FIXME:
10784 This should be cleaner, somehow. */
10785 obj_elf_section_change_hook ();
10788 mips_emit_delays (false);
10798 subseg_set (bss_section
, (subsegT
) get_absolute_expression ());
10799 demand_empty_rest_of_line ();
10803 if (USE_GLOBAL_POINTER_OPT
)
10805 seg
= subseg_new (RDATA_SECTION_NAME
,
10806 (subsegT
) get_absolute_expression ());
10807 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
10809 bfd_set_section_flags (stdoutput
, seg
,
10815 if (strcmp (TARGET_OS
, "elf") != 0)
10816 record_alignment (seg
, 4);
10818 demand_empty_rest_of_line ();
10822 as_bad (_("No read only data section in this object file format"));
10823 demand_empty_rest_of_line ();
10829 if (USE_GLOBAL_POINTER_OPT
)
10831 seg
= subseg_new (".sdata", (subsegT
) get_absolute_expression ());
10832 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
10834 bfd_set_section_flags (stdoutput
, seg
,
10835 SEC_ALLOC
| SEC_LOAD
| SEC_RELOC
10837 if (strcmp (TARGET_OS
, "elf") != 0)
10838 record_alignment (seg
, 4);
10840 demand_empty_rest_of_line ();
10845 as_bad (_("Global pointers not supported; recompile -G 0"));
10846 demand_empty_rest_of_line ();
10855 mips_enable_auto_align ()
10866 label
= insn_labels
!= NULL
? insn_labels
->label
: NULL
;
10867 mips_emit_delays (false);
10868 if (log_size
> 0 && auto_align
)
10869 mips_align (log_size
, 0, label
);
10870 mips_clear_insn_labels ();
10871 cons (1 << log_size
);
10875 s_float_cons (type
)
10880 label
= insn_labels
!= NULL
? insn_labels
->label
: NULL
;
10882 mips_emit_delays (false);
10887 mips_align (3, 0, label
);
10889 mips_align (2, 0, label
);
10892 mips_clear_insn_labels ();
10897 /* Handle .globl. We need to override it because on Irix 5 you are
10900 where foo is an undefined symbol, to mean that foo should be
10901 considered to be the address of a function. */
10905 int x ATTRIBUTE_UNUSED
;
10912 name
= input_line_pointer
;
10913 c
= get_symbol_end ();
10914 symbolP
= symbol_find_or_make (name
);
10915 *input_line_pointer
= c
;
10916 SKIP_WHITESPACE ();
10918 /* On Irix 5, every global symbol that is not explicitly labelled as
10919 being a function is apparently labelled as being an object. */
10922 if (! is_end_of_line
[(unsigned char) *input_line_pointer
])
10927 secname
= input_line_pointer
;
10928 c
= get_symbol_end ();
10929 sec
= bfd_get_section_by_name (stdoutput
, secname
);
10931 as_bad (_("%s: no such section"), secname
);
10932 *input_line_pointer
= c
;
10934 if (sec
!= NULL
&& (sec
->flags
& SEC_CODE
) != 0)
10935 flag
= BSF_FUNCTION
;
10938 symbol_get_bfdsym (symbolP
)->flags
|= flag
;
10940 S_SET_EXTERNAL (symbolP
);
10941 demand_empty_rest_of_line ();
10946 int x ATTRIBUTE_UNUSED
;
10951 opt
= input_line_pointer
;
10952 c
= get_symbol_end ();
10956 /* FIXME: What does this mean? */
10958 else if (strncmp (opt
, "pic", 3) == 0)
10962 i
= atoi (opt
+ 3);
10966 mips_pic
= SVR4_PIC
;
10968 as_bad (_(".option pic%d not supported"), i
);
10970 if (USE_GLOBAL_POINTER_OPT
&& mips_pic
== SVR4_PIC
)
10972 if (g_switch_seen
&& g_switch_value
!= 0)
10973 as_warn (_("-G may not be used with SVR4 PIC code"));
10974 g_switch_value
= 0;
10975 bfd_set_gp_size (stdoutput
, 0);
10979 as_warn (_("Unrecognized option \"%s\""), opt
);
10981 *input_line_pointer
= c
;
10982 demand_empty_rest_of_line ();
10985 /* This structure is used to hold a stack of .set values. */
10987 struct mips_option_stack
10989 struct mips_option_stack
*next
;
10990 struct mips_set_options options
;
10993 static struct mips_option_stack
*mips_opts_stack
;
10995 /* Handle the .set pseudo-op. */
10999 int x ATTRIBUTE_UNUSED
;
11001 char *name
= input_line_pointer
, ch
;
11003 while (!is_end_of_line
[(unsigned char) *input_line_pointer
])
11004 input_line_pointer
++;
11005 ch
= *input_line_pointer
;
11006 *input_line_pointer
= '\0';
11008 if (strcmp (name
, "reorder") == 0)
11010 if (mips_opts
.noreorder
&& prev_nop_frag
!= NULL
)
11012 /* If we still have pending nops, we can discard them. The
11013 usual nop handling will insert any that are still
11015 prev_nop_frag
->fr_fix
-= (prev_nop_frag_holds
11016 * (mips_opts
.mips16
? 2 : 4));
11017 prev_nop_frag
= NULL
;
11019 mips_opts
.noreorder
= 0;
11021 else if (strcmp (name
, "noreorder") == 0)
11023 mips_emit_delays (true);
11024 mips_opts
.noreorder
= 1;
11025 mips_any_noreorder
= 1;
11027 else if (strcmp (name
, "at") == 0)
11029 mips_opts
.noat
= 0;
11031 else if (strcmp (name
, "noat") == 0)
11033 mips_opts
.noat
= 1;
11035 else if (strcmp (name
, "macro") == 0)
11037 mips_opts
.warn_about_macros
= 0;
11039 else if (strcmp (name
, "nomacro") == 0)
11041 if (mips_opts
.noreorder
== 0)
11042 as_bad (_("`noreorder' must be set before `nomacro'"));
11043 mips_opts
.warn_about_macros
= 1;
11045 else if (strcmp (name
, "move") == 0 || strcmp (name
, "novolatile") == 0)
11047 mips_opts
.nomove
= 0;
11049 else if (strcmp (name
, "nomove") == 0 || strcmp (name
, "volatile") == 0)
11051 mips_opts
.nomove
= 1;
11053 else if (strcmp (name
, "bopt") == 0)
11055 mips_opts
.nobopt
= 0;
11057 else if (strcmp (name
, "nobopt") == 0)
11059 mips_opts
.nobopt
= 1;
11061 else if (strcmp (name
, "mips16") == 0
11062 || strcmp (name
, "MIPS-16") == 0)
11063 mips_opts
.mips16
= 1;
11064 else if (strcmp (name
, "nomips16") == 0
11065 || strcmp (name
, "noMIPS-16") == 0)
11066 mips_opts
.mips16
= 0;
11067 else if (strncmp (name
, "mips", 4) == 0)
11071 /* Permit the user to change the ISA on the fly. Needless to
11072 say, misuse can cause serious problems. */
11073 isa
= atoi (name
+ 4);
11077 mips_opts
.gp32
= file_mips_gp32
;
11078 mips_opts
.fp32
= file_mips_fp32
;
11079 mips_opts
.abi
= file_mips_abi
;
11084 mips_opts
.gp32
= 1;
11085 mips_opts
.fp32
= 1;
11091 /* Loosen ABI register width restriction. */
11092 if (mips_opts
.abi
== O32_ABI
)
11093 mips_opts
.abi
= NO_ABI
;
11094 mips_opts
.gp32
= 0;
11095 mips_opts
.fp32
= 0;
11098 as_bad (_("unknown ISA level %s"), name
+ 4);
11104 case 0: mips_opts
.isa
= file_mips_isa
; break;
11105 case 1: mips_opts
.isa
= ISA_MIPS1
; break;
11106 case 2: mips_opts
.isa
= ISA_MIPS2
; break;
11107 case 3: mips_opts
.isa
= ISA_MIPS3
; break;
11108 case 4: mips_opts
.isa
= ISA_MIPS4
; break;
11109 case 5: mips_opts
.isa
= ISA_MIPS5
; break;
11110 case 32: mips_opts
.isa
= ISA_MIPS32
; break;
11111 case 64: mips_opts
.isa
= ISA_MIPS64
; break;
11112 default: as_bad (_("unknown ISA level %s"), name
+ 4); break;
11115 else if (strcmp (name
, "autoextend") == 0)
11116 mips_opts
.noautoextend
= 0;
11117 else if (strcmp (name
, "noautoextend") == 0)
11118 mips_opts
.noautoextend
= 1;
11119 else if (strcmp (name
, "push") == 0)
11121 struct mips_option_stack
*s
;
11123 s
= (struct mips_option_stack
*) xmalloc (sizeof *s
);
11124 s
->next
= mips_opts_stack
;
11125 s
->options
= mips_opts
;
11126 mips_opts_stack
= s
;
11128 else if (strcmp (name
, "pop") == 0)
11130 struct mips_option_stack
*s
;
11132 s
= mips_opts_stack
;
11134 as_bad (_(".set pop with no .set push"));
11137 /* If we're changing the reorder mode we need to handle
11138 delay slots correctly. */
11139 if (s
->options
.noreorder
&& ! mips_opts
.noreorder
)
11140 mips_emit_delays (true);
11141 else if (! s
->options
.noreorder
&& mips_opts
.noreorder
)
11143 if (prev_nop_frag
!= NULL
)
11145 prev_nop_frag
->fr_fix
-= (prev_nop_frag_holds
11146 * (mips_opts
.mips16
? 2 : 4));
11147 prev_nop_frag
= NULL
;
11151 mips_opts
= s
->options
;
11152 mips_opts_stack
= s
->next
;
11158 as_warn (_("Tried to set unrecognized symbol: %s\n"), name
);
11160 *input_line_pointer
= ch
;
11161 demand_empty_rest_of_line ();
11164 /* Handle the .abicalls pseudo-op. I believe this is equivalent to
11165 .option pic2. It means to generate SVR4 PIC calls. */
11168 s_abicalls (ignore
)
11169 int ignore ATTRIBUTE_UNUSED
;
11171 mips_pic
= SVR4_PIC
;
11172 if (USE_GLOBAL_POINTER_OPT
)
11174 if (g_switch_seen
&& g_switch_value
!= 0)
11175 as_warn (_("-G may not be used with SVR4 PIC code"));
11176 g_switch_value
= 0;
11178 bfd_set_gp_size (stdoutput
, 0);
11179 demand_empty_rest_of_line ();
11182 /* Handle the .cpload pseudo-op. This is used when generating SVR4
11183 PIC code. It sets the $gp register for the function based on the
11184 function address, which is in the register named in the argument.
11185 This uses a relocation against _gp_disp, which is handled specially
11186 by the linker. The result is:
11187 lui $gp,%hi(_gp_disp)
11188 addiu $gp,$gp,%lo(_gp_disp)
11189 addu $gp,$gp,.cpload argument
11190 The .cpload argument is normally $25 == $t9. */
11194 int ignore ATTRIBUTE_UNUSED
;
11199 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
11200 .cpload is ignored. */
11201 if (mips_pic
!= SVR4_PIC
|| HAVE_NEWABI
)
11207 /* .cpload should be in a .set noreorder section. */
11208 if (mips_opts
.noreorder
== 0)
11209 as_warn (_(".cpload not in noreorder section"));
11211 ex
.X_op
= O_symbol
;
11212 ex
.X_add_symbol
= symbol_find_or_make ("_gp_disp");
11213 ex
.X_op_symbol
= NULL
;
11214 ex
.X_add_number
= 0;
11216 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
11217 symbol_get_bfdsym (ex
.X_add_symbol
)->flags
|= BSF_OBJECT
;
11219 macro_build_lui (NULL
, &icnt
, &ex
, GP
);
11220 macro_build ((char *) NULL
, &icnt
, &ex
, "addiu", "t,r,j", GP
, GP
,
11221 (int) BFD_RELOC_LO16
);
11223 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "addu", "d,v,t",
11224 GP
, GP
, tc_get_register (0));
11226 demand_empty_rest_of_line ();
11229 /* Handle the .cpsetup pseudo-op defined for NewABI PIC code. The syntax is:
11230 .cpsetup $reg1, offset|$reg2, label
11232 If offset is given, this results in:
11233 sd $gp, offset($sp)
11234 lui $gp, %gp_rel(%neg(%hi(label)))
11235 daddiu $gp, $gp, %gp_rel(%neg(%lo(label)))
11236 addu $gp, $gp, $reg1
11238 If $reg2 is given, this results in:
11239 daddu $reg2, $gp, $0
11240 lui $gp, %gp_rel(%neg(%hi(label)))
11241 daddiu $gp, $gp, %gp_rel(%neg(%lo(label)))
11242 addu $gp, $gp, $reg1
11246 int ignore ATTRIBUTE_UNUSED
;
11248 expressionS ex_off
;
11249 expressionS ex_sym
;
11254 /* If we are not generating SVR4 PIC code, .cpload is ignored.
11255 We also need NewABI support. */
11256 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
11262 reg1
= tc_get_register (0);
11263 SKIP_WHITESPACE ();
11264 if (*input_line_pointer
!= ',')
11266 as_bad (_("missing argument separator ',' for .cpsetup"));
11270 input_line_pointer
++;
11271 SKIP_WHITESPACE ();
11272 if (*input_line_pointer
== '$')
11273 mips_cpreturn_register
= tc_get_register (0);
11275 mips_cpreturn_offset
= get_absolute_expression ();
11276 SKIP_WHITESPACE ();
11277 if (*input_line_pointer
!= ',')
11279 as_bad (_("missing argument separator ',' for .cpsetup"));
11283 input_line_pointer
++;
11284 SKIP_WHITESPACE ();
11285 sym
= input_line_pointer
;
11286 while (ISALNUM (*input_line_pointer
))
11287 input_line_pointer
++;
11288 *input_line_pointer
= 0;
11290 ex_sym
.X_op
= O_symbol
;
11291 ex_sym
.X_add_symbol
= symbol_find_or_make (sym
);
11292 ex_sym
.X_op_symbol
= NULL
;
11293 ex_sym
.X_add_number
= 0;
11295 if (mips_cpreturn_register
== -1)
11297 ex_off
.X_op
= O_constant
;
11298 ex_off
.X_add_symbol
= NULL
;
11299 ex_off
.X_op_symbol
= NULL
;
11300 ex_off
.X_add_number
= mips_cpreturn_offset
;
11302 macro_build ((char *) NULL
, &icnt
, &ex_off
, "sd", "t,o(b)",
11303 mips_gp_register
, (int) BFD_RELOC_LO16
, SP
);
11306 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "daddu",
11307 "d,v,t", mips_cpreturn_register
, mips_gp_register
, 0);
11309 macro_build ((char *) NULL
, &icnt
, &ex_sym
, "lui", "t,u", mips_gp_register
,
11310 (int) BFD_RELOC_GPREL16
);
11311 fix_new (frag_now
, (char *) prev_insn_fixp
- 4 - frag_now
->fr_literal
, 0,
11312 NULL
, 0, 0, BFD_RELOC_MIPS_SUB
);
11313 fix_new (frag_now
, (char *) prev_insn_fixp
- 4 - frag_now
->fr_literal
, 0,
11314 NULL
, 0, 0, BFD_RELOC_HI16_S
);
11315 macro_build ((char *) NULL
, &icnt
, &ex_sym
, "addiu", "t,r,j",
11316 mips_gp_register
, mips_gp_register
, (int) BFD_RELOC_GPREL16
);
11317 fix_new (frag_now
, (char *) prev_insn_fixp
- 4 - frag_now
->fr_literal
, 0,
11318 NULL
, 0, 0, BFD_RELOC_MIPS_SUB
);
11319 fix_new (frag_now
, (char *) prev_insn_fixp
- 4 - frag_now
->fr_literal
, 0,
11320 NULL
, 0, 0, BFD_RELOC_LO16
);
11321 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "daddu",
11322 "d,v,t", mips_gp_register
, mips_gp_register
, reg1
);
11324 demand_empty_rest_of_line ();
11329 int ignore ATTRIBUTE_UNUSED
;
11331 /* If we are not generating SVR4 PIC code, or if this is not NewABI code,
11332 .cplocal is ignored. */
11333 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
11339 mips_gp_register
= tc_get_register (0);
11342 /* Handle the .cprestore pseudo-op. This stores $gp into a given
11343 offset from $sp. The offset is remembered, and after making a PIC
11344 call $gp is restored from that location. */
11347 s_cprestore (ignore
)
11348 int ignore ATTRIBUTE_UNUSED
;
11353 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
11354 .cprestore is ignored. */
11355 if (mips_pic
!= SVR4_PIC
|| HAVE_NEWABI
)
11361 mips_cprestore_offset
= get_absolute_expression ();
11363 ex
.X_op
= O_constant
;
11364 ex
.X_add_symbol
= NULL
;
11365 ex
.X_op_symbol
= NULL
;
11366 ex
.X_add_number
= mips_cprestore_offset
;
11368 macro_build ((char *) NULL
, &icnt
, &ex
,
11369 HAVE_32BIT_ADDRESSES
? "sw" : "sd",
11370 "t,o(b)", GP
, (int) BFD_RELOC_LO16
, SP
);
11372 demand_empty_rest_of_line ();
11375 /* Handle the .cpreturn pseudo-op defined for NewABI PIC code. If an offset
11376 was given in the preceeding .gpsetup, it results in:
11377 ld $gp, offset($sp)
11379 If a register $reg2 was given there, it results in:
11380 daddiu $gp, $gp, $reg2
11383 s_cpreturn (ignore
)
11384 int ignore ATTRIBUTE_UNUSED
;
11389 /* If we are not generating SVR4 PIC code, .cpreturn is ignored.
11390 We also need NewABI support. */
11391 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
11397 if (mips_cpreturn_register
== -1)
11399 ex
.X_op
= O_constant
;
11400 ex
.X_add_symbol
= NULL
;
11401 ex
.X_op_symbol
= NULL
;
11402 ex
.X_add_number
= mips_cpreturn_offset
;
11404 macro_build ((char *) NULL
, &icnt
, &ex
, "ld", "t,o(b)",
11405 mips_gp_register
, (int) BFD_RELOC_LO16
, SP
);
11408 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "daddu",
11409 "d,v,t", mips_gp_register
, mips_cpreturn_register
, 0);
11411 demand_empty_rest_of_line ();
11414 /* Handle the .gpvalue pseudo-op. This is used when generating NewABI PIC
11415 code. It sets the offset to use in gp_rel relocations. */
11419 int ignore ATTRIBUTE_UNUSED
;
11421 /* If we are not generating SVR4 PIC code, .gpvalue is ignored.
11422 We also need NewABI support. */
11423 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
11429 mips_cpreturn_offset
= get_absolute_expression ();
11431 demand_empty_rest_of_line ();
11434 /* Handle the .gpword pseudo-op. This is used when generating PIC
11435 code. It generates a 32 bit GP relative reloc. */
11439 int ignore ATTRIBUTE_UNUSED
;
11445 /* When not generating PIC code, this is treated as .word. */
11446 if (mips_pic
!= SVR4_PIC
)
11452 label
= insn_labels
!= NULL
? insn_labels
->label
: NULL
;
11453 mips_emit_delays (true);
11455 mips_align (2, 0, label
);
11456 mips_clear_insn_labels ();
11460 if (ex
.X_op
!= O_symbol
|| ex
.X_add_number
!= 0)
11462 as_bad (_("Unsupported use of .gpword"));
11463 ignore_rest_of_line ();
11467 md_number_to_chars (p
, (valueT
) 0, 4);
11468 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 4, &ex
, 0,
11469 BFD_RELOC_MIPS_GPREL32
);
11471 demand_empty_rest_of_line ();
11474 /* Handle the .cpadd pseudo-op. This is used when dealing with switch
11475 tables in SVR4 PIC code. */
11479 int ignore ATTRIBUTE_UNUSED
;
11484 /* This is ignored when not generating SVR4 PIC code or if this is NewABI
11486 if (mips_pic
!= SVR4_PIC
|| HAVE_NEWABI
)
11492 /* Add $gp to the register named as an argument. */
11493 reg
= tc_get_register (0);
11494 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
11495 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
11496 "d,v,t", reg
, reg
, GP
);
11498 demand_empty_rest_of_line ();
11501 /* Handle the .insn pseudo-op. This marks instruction labels in
11502 mips16 mode. This permits the linker to handle them specially,
11503 such as generating jalx instructions when needed. We also make
11504 them odd for the duration of the assembly, in order to generate the
11505 right sort of code. We will make them even in the adjust_symtab
11506 routine, while leaving them marked. This is convenient for the
11507 debugger and the disassembler. The linker knows to make them odd
11512 int ignore ATTRIBUTE_UNUSED
;
11514 if (mips_opts
.mips16
)
11515 mips16_mark_labels ();
11517 demand_empty_rest_of_line ();
11520 /* Handle a .stabn directive. We need these in order to mark a label
11521 as being a mips16 text label correctly. Sometimes the compiler
11522 will emit a label, followed by a .stabn, and then switch sections.
11523 If the label and .stabn are in mips16 mode, then the label is
11524 really a mips16 text label. */
11530 if (type
== 'n' && mips_opts
.mips16
)
11531 mips16_mark_labels ();
11536 /* Handle the .weakext pseudo-op as defined in Kane and Heinrich.
11540 s_mips_weakext (ignore
)
11541 int ignore ATTRIBUTE_UNUSED
;
11548 name
= input_line_pointer
;
11549 c
= get_symbol_end ();
11550 symbolP
= symbol_find_or_make (name
);
11551 S_SET_WEAK (symbolP
);
11552 *input_line_pointer
= c
;
11554 SKIP_WHITESPACE ();
11556 if (! is_end_of_line
[(unsigned char) *input_line_pointer
])
11558 if (S_IS_DEFINED (symbolP
))
11560 as_bad ("Ignoring attempt to redefine symbol `%s'.",
11561 S_GET_NAME (symbolP
));
11562 ignore_rest_of_line ();
11566 if (*input_line_pointer
== ',')
11568 ++input_line_pointer
;
11569 SKIP_WHITESPACE ();
11573 if (exp
.X_op
!= O_symbol
)
11575 as_bad ("bad .weakext directive");
11576 ignore_rest_of_line();
11579 symbol_set_value_expression (symbolP
, &exp
);
11582 demand_empty_rest_of_line ();
11585 /* Parse a register string into a number. Called from the ECOFF code
11586 to parse .frame. The argument is non-zero if this is the frame
11587 register, so that we can record it in mips_frame_reg. */
11590 tc_get_register (frame
)
11595 SKIP_WHITESPACE ();
11596 if (*input_line_pointer
++ != '$')
11598 as_warn (_("expected `$'"));
11601 else if (ISDIGIT (*input_line_pointer
))
11603 reg
= get_absolute_expression ();
11604 if (reg
< 0 || reg
>= 32)
11606 as_warn (_("Bad register number"));
11612 if (strncmp (input_line_pointer
, "fp", 2) == 0)
11614 else if (strncmp (input_line_pointer
, "sp", 2) == 0)
11616 else if (strncmp (input_line_pointer
, "gp", 2) == 0)
11618 else if (strncmp (input_line_pointer
, "at", 2) == 0)
11622 as_warn (_("Unrecognized register name"));
11625 input_line_pointer
+= 2;
11628 mips_frame_reg
= reg
!= 0 ? reg
: SP
;
11633 md_section_align (seg
, addr
)
11637 int align
= bfd_get_section_alignment (stdoutput
, seg
);
11640 /* We don't need to align ELF sections to the full alignment.
11641 However, Irix 5 may prefer that we align them at least to a 16
11642 byte boundary. We don't bother to align the sections if we are
11643 targeted for an embedded system. */
11644 if (strcmp (TARGET_OS
, "elf") == 0)
11650 return ((addr
+ (1 << align
) - 1) & (-1 << align
));
11653 /* Utility routine, called from above as well. If called while the
11654 input file is still being read, it's only an approximation. (For
11655 example, a symbol may later become defined which appeared to be
11656 undefined earlier.) */
11659 nopic_need_relax (sym
, before_relaxing
)
11661 int before_relaxing
;
11666 if (USE_GLOBAL_POINTER_OPT
&& g_switch_value
> 0)
11668 const char *symname
;
11671 /* Find out whether this symbol can be referenced off the GP
11672 register. It can be if it is smaller than the -G size or if
11673 it is in the .sdata or .sbss section. Certain symbols can
11674 not be referenced off the GP, although it appears as though
11676 symname
= S_GET_NAME (sym
);
11677 if (symname
!= (const char *) NULL
11678 && (strcmp (symname
, "eprol") == 0
11679 || strcmp (symname
, "etext") == 0
11680 || strcmp (symname
, "_gp") == 0
11681 || strcmp (symname
, "edata") == 0
11682 || strcmp (symname
, "_fbss") == 0
11683 || strcmp (symname
, "_fdata") == 0
11684 || strcmp (symname
, "_ftext") == 0
11685 || strcmp (symname
, "end") == 0
11686 || strcmp (symname
, "_gp_disp") == 0))
11688 else if ((! S_IS_DEFINED (sym
) || S_IS_COMMON (sym
))
11690 #ifndef NO_ECOFF_DEBUGGING
11691 || (symbol_get_obj (sym
)->ecoff_extern_size
!= 0
11692 && (symbol_get_obj (sym
)->ecoff_extern_size
11693 <= g_switch_value
))
11695 /* We must defer this decision until after the whole
11696 file has been read, since there might be a .extern
11697 after the first use of this symbol. */
11698 || (before_relaxing
11699 #ifndef NO_ECOFF_DEBUGGING
11700 && symbol_get_obj (sym
)->ecoff_extern_size
== 0
11702 && S_GET_VALUE (sym
) == 0)
11703 || (S_GET_VALUE (sym
) != 0
11704 && S_GET_VALUE (sym
) <= g_switch_value
)))
11708 const char *segname
;
11710 segname
= segment_name (S_GET_SEGMENT (sym
));
11711 assert (strcmp (segname
, ".lit8") != 0
11712 && strcmp (segname
, ".lit4") != 0);
11713 change
= (strcmp (segname
, ".sdata") != 0
11714 && strcmp (segname
, ".sbss") != 0
11715 && strncmp (segname
, ".sdata.", 7) != 0
11716 && strncmp (segname
, ".gnu.linkonce.s.", 16) != 0);
11721 /* We are not optimizing for the GP register. */
11725 /* Given a mips16 variant frag FRAGP, return non-zero if it needs an
11726 extended opcode. SEC is the section the frag is in. */
11729 mips16_extended_frag (fragp
, sec
, stretch
)
11735 register const struct mips16_immed_operand
*op
;
11737 int mintiny
, maxtiny
;
11741 if (RELAX_MIPS16_USER_SMALL (fragp
->fr_subtype
))
11743 if (RELAX_MIPS16_USER_EXT (fragp
->fr_subtype
))
11746 type
= RELAX_MIPS16_TYPE (fragp
->fr_subtype
);
11747 op
= mips16_immed_operands
;
11748 while (op
->type
!= type
)
11751 assert (op
< mips16_immed_operands
+ MIPS16_NUM_IMMED
);
11756 if (type
== '<' || type
== '>' || type
== '[' || type
== ']')
11759 maxtiny
= 1 << op
->nbits
;
11764 maxtiny
= (1 << op
->nbits
) - 1;
11769 mintiny
= - (1 << (op
->nbits
- 1));
11770 maxtiny
= (1 << (op
->nbits
- 1)) - 1;
11773 sym_frag
= symbol_get_frag (fragp
->fr_symbol
);
11774 val
= S_GET_VALUE (fragp
->fr_symbol
);
11775 symsec
= S_GET_SEGMENT (fragp
->fr_symbol
);
11781 /* We won't have the section when we are called from
11782 mips_relax_frag. However, we will always have been called
11783 from md_estimate_size_before_relax first. If this is a
11784 branch to a different section, we mark it as such. If SEC is
11785 NULL, and the frag is not marked, then it must be a branch to
11786 the same section. */
11789 if (RELAX_MIPS16_LONG_BRANCH (fragp
->fr_subtype
))
11794 /* Must have been called from md_estimate_size_before_relax. */
11797 fragp
->fr_subtype
=
11798 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
11800 /* FIXME: We should support this, and let the linker
11801 catch branches and loads that are out of range. */
11802 as_bad_where (fragp
->fr_file
, fragp
->fr_line
,
11803 _("unsupported PC relative reference to different section"));
11807 if (fragp
!= sym_frag
&& sym_frag
->fr_address
== 0)
11808 /* Assume non-extended on the first relaxation pass.
11809 The address we have calculated will be bogus if this is
11810 a forward branch to another frag, as the forward frag
11811 will have fr_address == 0. */
11815 /* In this case, we know for sure that the symbol fragment is in
11816 the same section. If the relax_marker of the symbol fragment
11817 differs from the relax_marker of this fragment, we have not
11818 yet adjusted the symbol fragment fr_address. We want to add
11819 in STRETCH in order to get a better estimate of the address.
11820 This particularly matters because of the shift bits. */
11822 && sym_frag
->relax_marker
!= fragp
->relax_marker
)
11826 /* Adjust stretch for any alignment frag. Note that if have
11827 been expanding the earlier code, the symbol may be
11828 defined in what appears to be an earlier frag. FIXME:
11829 This doesn't handle the fr_subtype field, which specifies
11830 a maximum number of bytes to skip when doing an
11832 for (f
= fragp
; f
!= NULL
&& f
!= sym_frag
; f
= f
->fr_next
)
11834 if (f
->fr_type
== rs_align
|| f
->fr_type
== rs_align_code
)
11837 stretch
= - ((- stretch
)
11838 & ~ ((1 << (int) f
->fr_offset
) - 1));
11840 stretch
&= ~ ((1 << (int) f
->fr_offset
) - 1);
11849 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
11851 /* The base address rules are complicated. The base address of
11852 a branch is the following instruction. The base address of a
11853 PC relative load or add is the instruction itself, but if it
11854 is in a delay slot (in which case it can not be extended) use
11855 the address of the instruction whose delay slot it is in. */
11856 if (type
== 'p' || type
== 'q')
11860 /* If we are currently assuming that this frag should be
11861 extended, then, the current address is two bytes
11863 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
11866 /* Ignore the low bit in the target, since it will be set
11867 for a text label. */
11868 if ((val
& 1) != 0)
11871 else if (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
))
11873 else if (RELAX_MIPS16_DSLOT (fragp
->fr_subtype
))
11876 val
-= addr
& ~ ((1 << op
->shift
) - 1);
11878 /* Branch offsets have an implicit 0 in the lowest bit. */
11879 if (type
== 'p' || type
== 'q')
11882 /* If any of the shifted bits are set, we must use an extended
11883 opcode. If the address depends on the size of this
11884 instruction, this can lead to a loop, so we arrange to always
11885 use an extended opcode. We only check this when we are in
11886 the main relaxation loop, when SEC is NULL. */
11887 if ((val
& ((1 << op
->shift
) - 1)) != 0 && sec
== NULL
)
11889 fragp
->fr_subtype
=
11890 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
11894 /* If we are about to mark a frag as extended because the value
11895 is precisely maxtiny + 1, then there is a chance of an
11896 infinite loop as in the following code:
11901 In this case when the la is extended, foo is 0x3fc bytes
11902 away, so the la can be shrunk, but then foo is 0x400 away, so
11903 the la must be extended. To avoid this loop, we mark the
11904 frag as extended if it was small, and is about to become
11905 extended with a value of maxtiny + 1. */
11906 if (val
== ((maxtiny
+ 1) << op
->shift
)
11907 && ! RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
)
11910 fragp
->fr_subtype
=
11911 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
11915 else if (symsec
!= absolute_section
&& sec
!= NULL
)
11916 as_bad_where (fragp
->fr_file
, fragp
->fr_line
, _("unsupported relocation"));
11918 if ((val
& ((1 << op
->shift
) - 1)) != 0
11919 || val
< (mintiny
<< op
->shift
)
11920 || val
> (maxtiny
<< op
->shift
))
11926 /* Estimate the size of a frag before relaxing. Unless this is the
11927 mips16, we are not really relaxing here, and the final size is
11928 encoded in the subtype information. For the mips16, we have to
11929 decide whether we are using an extended opcode or not. */
11932 md_estimate_size_before_relax (fragp
, segtype
)
11937 boolean linkonce
= false;
11939 if (RELAX_MIPS16_P (fragp
->fr_subtype
))
11941 if (mips16_extended_frag (fragp
, segtype
, 0))
11943 fragp
->fr_subtype
= RELAX_MIPS16_MARK_EXTENDED (fragp
->fr_subtype
);
11948 fragp
->fr_subtype
= RELAX_MIPS16_CLEAR_EXTENDED (fragp
->fr_subtype
);
11953 if (mips_pic
== NO_PIC
)
11955 change
= nopic_need_relax (fragp
->fr_symbol
, 0);
11957 else if (mips_pic
== SVR4_PIC
)
11962 sym
= fragp
->fr_symbol
;
11964 /* Handle the case of a symbol equated to another symbol. */
11965 while (symbol_equated_reloc_p (sym
))
11969 /* It's possible to get a loop here in a badly written
11971 n
= symbol_get_value_expression (sym
)->X_add_symbol
;
11977 symsec
= S_GET_SEGMENT (sym
);
11979 /* duplicate the test for LINK_ONCE sections as in adjust_reloc_syms */
11980 if (symsec
!= segtype
&& ! S_IS_LOCAL (sym
))
11982 if ((bfd_get_section_flags (stdoutput
, symsec
) & SEC_LINK_ONCE
)
11986 /* The GNU toolchain uses an extension for ELF: a section
11987 beginning with the magic string .gnu.linkonce is a linkonce
11989 if (strncmp (segment_name (symsec
), ".gnu.linkonce",
11990 sizeof ".gnu.linkonce" - 1) == 0)
11994 /* This must duplicate the test in adjust_reloc_syms. */
11995 change
= (symsec
!= &bfd_und_section
11996 && symsec
!= &bfd_abs_section
11997 && ! bfd_is_com_section (symsec
)
12000 /* A global or weak symbol is treated as external. */
12001 && (OUTPUT_FLAVOR
== bfd_target_elf_flavour
12002 && ! (S_IS_EXTERN (sym
) || S_IS_WEAK (sym
)))
12011 /* Record the offset to the first reloc in the fr_opcode field.
12012 This lets md_convert_frag and tc_gen_reloc know that the code
12013 must be expanded. */
12014 fragp
->fr_opcode
= (fragp
->fr_literal
12016 - RELAX_OLD (fragp
->fr_subtype
)
12017 + RELAX_RELOC1 (fragp
->fr_subtype
));
12018 /* FIXME: This really needs as_warn_where. */
12019 if (RELAX_WARN (fragp
->fr_subtype
))
12020 as_warn (_("AT used after \".set noat\" or macro used after "
12021 "\".set nomacro\""));
12023 return RELAX_NEW (fragp
->fr_subtype
) - RELAX_OLD (fragp
->fr_subtype
);
12029 /* This is called to see whether a reloc against a defined symbol
12030 should be converted into a reloc against a section. Don't adjust
12031 MIPS16 jump relocations, so we don't have to worry about the format
12032 of the offset in the .o file. Don't adjust relocations against
12033 mips16 symbols, so that the linker can find them if it needs to set
12037 mips_fix_adjustable (fixp
)
12041 /* Prevent all adjustments to global symbols. */
12042 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
12043 && (S_IS_EXTERN (fixp
->fx_addsy
) || S_IS_WEAK (fixp
->fx_addsy
)))
12046 if (fixp
->fx_r_type
== BFD_RELOC_MIPS16_JMP
)
12048 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
12049 || fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
12051 if (fixp
->fx_addsy
== NULL
)
12054 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
12055 && S_GET_OTHER (fixp
->fx_addsy
) == STO_MIPS16
12056 && fixp
->fx_subsy
== NULL
)
12062 /* Translate internal representation of relocation info to BFD target
12066 tc_gen_reloc (section
, fixp
)
12067 asection
*section ATTRIBUTE_UNUSED
;
12070 static arelent
*retval
[4];
12072 bfd_reloc_code_real_type code
;
12074 reloc
= retval
[0] = (arelent
*) xmalloc (sizeof (arelent
));
12077 reloc
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
12078 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
12079 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
12081 if (mips_pic
== EMBEDDED_PIC
12082 && SWITCH_TABLE (fixp
))
12084 /* For a switch table entry we use a special reloc. The addend
12085 is actually the difference between the reloc address and the
12087 reloc
->addend
= reloc
->address
- S_GET_VALUE (fixp
->fx_subsy
);
12088 if (OUTPUT_FLAVOR
!= bfd_target_ecoff_flavour
)
12089 as_fatal (_("Double check fx_r_type in tc-mips.c:tc_gen_reloc"));
12090 fixp
->fx_r_type
= BFD_RELOC_GPREL32
;
12092 else if (fixp
->fx_pcrel
== 0 || OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
12093 reloc
->addend
= fixp
->fx_addnumber
;
12094 else if (fixp
->fx_r_type
== BFD_RELOC_PCREL_LO16
)
12096 /* We use a special addend for an internal RELLO reloc. */
12097 if (symbol_section_p (fixp
->fx_addsy
))
12098 reloc
->addend
= reloc
->address
- S_GET_VALUE (fixp
->fx_subsy
);
12100 reloc
->addend
= fixp
->fx_addnumber
+ reloc
->address
;
12102 else if (fixp
->fx_r_type
== BFD_RELOC_PCREL_HI16_S
)
12104 assert (fixp
->fx_next
!= NULL
12105 && fixp
->fx_next
->fx_r_type
== BFD_RELOC_PCREL_LO16
);
12106 /* We use a special addend for an internal RELHI reloc. The
12107 reloc is relative to the RELLO; adjust the addend
12109 if (symbol_section_p (fixp
->fx_addsy
))
12110 reloc
->addend
= (fixp
->fx_next
->fx_frag
->fr_address
12111 + fixp
->fx_next
->fx_where
12112 - S_GET_VALUE (fixp
->fx_subsy
));
12114 reloc
->addend
= (fixp
->fx_addnumber
12115 + fixp
->fx_next
->fx_frag
->fr_address
12116 + fixp
->fx_next
->fx_where
);
12120 if (OUTPUT_FLAVOR
!= bfd_target_aout_flavour
)
12121 /* A gruesome hack which is a result of the gruesome gas reloc
12123 reloc
->addend
= reloc
->address
;
12125 reloc
->addend
= -reloc
->address
;
12128 /* If this is a variant frag, we may need to adjust the existing
12129 reloc and generate a new one. */
12130 if (fixp
->fx_frag
->fr_opcode
!= NULL
12131 && (fixp
->fx_r_type
== BFD_RELOC_MIPS_GPREL
12132 || fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT16
12133 || fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL16
12134 || fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT_HI16
12135 || fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT_LO16
12136 || fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL_HI16
12137 || fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL_LO16
)
12142 assert (! RELAX_MIPS16_P (fixp
->fx_frag
->fr_subtype
));
12144 /* If this is not the last reloc in this frag, then we have two
12145 GPREL relocs, or a GOT_HI16/GOT_LO16 pair, or a
12146 CALL_HI16/CALL_LO16, both of which are being replaced. Let
12147 the second one handle all of them. */
12148 if (fixp
->fx_next
!= NULL
12149 && fixp
->fx_frag
== fixp
->fx_next
->fx_frag
)
12151 assert ((fixp
->fx_r_type
== BFD_RELOC_MIPS_GPREL
12152 && fixp
->fx_next
->fx_r_type
== BFD_RELOC_MIPS_GPREL
)
12153 || (fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT_HI16
12154 && (fixp
->fx_next
->fx_r_type
12155 == BFD_RELOC_MIPS_GOT_LO16
))
12156 || (fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL_HI16
12157 && (fixp
->fx_next
->fx_r_type
12158 == BFD_RELOC_MIPS_CALL_LO16
)));
12163 fixp
->fx_where
= fixp
->fx_frag
->fr_opcode
- fixp
->fx_frag
->fr_literal
;
12164 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
12165 reloc2
= retval
[1] = (arelent
*) xmalloc (sizeof (arelent
));
12167 reloc2
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
12168 *reloc2
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
12169 reloc2
->address
= (reloc
->address
12170 + (RELAX_RELOC2 (fixp
->fx_frag
->fr_subtype
)
12171 - RELAX_RELOC1 (fixp
->fx_frag
->fr_subtype
)));
12172 reloc2
->addend
= fixp
->fx_addnumber
;
12173 reloc2
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_LO16
);
12174 assert (reloc2
->howto
!= NULL
);
12176 if (RELAX_RELOC3 (fixp
->fx_frag
->fr_subtype
))
12180 reloc3
= retval
[2] = (arelent
*) xmalloc (sizeof (arelent
));
12183 reloc3
->address
+= 4;
12186 if (mips_pic
== NO_PIC
)
12188 assert (fixp
->fx_r_type
== BFD_RELOC_MIPS_GPREL
);
12189 fixp
->fx_r_type
= BFD_RELOC_HI16_S
;
12191 else if (mips_pic
== SVR4_PIC
)
12193 switch (fixp
->fx_r_type
)
12197 case BFD_RELOC_MIPS_GOT16
:
12199 case BFD_RELOC_MIPS_CALL16
:
12200 case BFD_RELOC_MIPS_GOT_LO16
:
12201 case BFD_RELOC_MIPS_CALL_LO16
:
12202 fixp
->fx_r_type
= BFD_RELOC_MIPS_GOT16
;
12210 /* Since MIPS ELF uses Rel instead of Rela, encode the vtable entry
12211 to be used in the relocation's section offset. */
12212 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
12214 reloc
->address
= reloc
->addend
;
12218 /* Since DIFF_EXPR_OK is defined in tc-mips.h, it is possible that
12219 fixup_segment converted a non-PC relative reloc into a PC
12220 relative reloc. In such a case, we need to convert the reloc
12222 code
= fixp
->fx_r_type
;
12223 if (fixp
->fx_pcrel
)
12228 code
= BFD_RELOC_8_PCREL
;
12231 code
= BFD_RELOC_16_PCREL
;
12234 code
= BFD_RELOC_32_PCREL
;
12237 code
= BFD_RELOC_64_PCREL
;
12239 case BFD_RELOC_8_PCREL
:
12240 case BFD_RELOC_16_PCREL
:
12241 case BFD_RELOC_32_PCREL
:
12242 case BFD_RELOC_64_PCREL
:
12243 case BFD_RELOC_16_PCREL_S2
:
12244 case BFD_RELOC_PCREL_HI16_S
:
12245 case BFD_RELOC_PCREL_LO16
:
12248 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
12249 _("Cannot make %s relocation PC relative"),
12250 bfd_get_reloc_code_name (code
));
12254 /* To support a PC relative reloc when generating embedded PIC code
12255 for ECOFF, we use a Cygnus extension. We check for that here to
12256 make sure that we don't let such a reloc escape normally. */
12257 if ((OUTPUT_FLAVOR
== bfd_target_ecoff_flavour
12258 || OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
12259 && code
== BFD_RELOC_16_PCREL_S2
12260 && mips_pic
!= EMBEDDED_PIC
)
12261 reloc
->howto
= NULL
;
12263 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
12265 if (reloc
->howto
== NULL
)
12267 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
12268 _("Can not represent %s relocation in this object file format"),
12269 bfd_get_reloc_code_name (code
));
12276 /* Relax a machine dependent frag. This returns the amount by which
12277 the current size of the frag should change. */
12280 mips_relax_frag (fragp
, stretch
)
12284 if (! RELAX_MIPS16_P (fragp
->fr_subtype
))
12287 if (mips16_extended_frag (fragp
, NULL
, stretch
))
12289 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
12291 fragp
->fr_subtype
= RELAX_MIPS16_MARK_EXTENDED (fragp
->fr_subtype
);
12296 if (! RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
12298 fragp
->fr_subtype
= RELAX_MIPS16_CLEAR_EXTENDED (fragp
->fr_subtype
);
12305 /* Convert a machine dependent frag. */
12308 md_convert_frag (abfd
, asec
, fragp
)
12309 bfd
*abfd ATTRIBUTE_UNUSED
;
12316 if (RELAX_MIPS16_P (fragp
->fr_subtype
))
12319 register const struct mips16_immed_operand
*op
;
12320 boolean small
, ext
;
12323 unsigned long insn
;
12324 boolean use_extend
;
12325 unsigned short extend
;
12327 type
= RELAX_MIPS16_TYPE (fragp
->fr_subtype
);
12328 op
= mips16_immed_operands
;
12329 while (op
->type
!= type
)
12332 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
12343 resolve_symbol_value (fragp
->fr_symbol
);
12344 val
= S_GET_VALUE (fragp
->fr_symbol
);
12349 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
12351 /* The rules for the base address of a PC relative reloc are
12352 complicated; see mips16_extended_frag. */
12353 if (type
== 'p' || type
== 'q')
12358 /* Ignore the low bit in the target, since it will be
12359 set for a text label. */
12360 if ((val
& 1) != 0)
12363 else if (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
))
12365 else if (RELAX_MIPS16_DSLOT (fragp
->fr_subtype
))
12368 addr
&= ~ (addressT
) ((1 << op
->shift
) - 1);
12371 /* Make sure the section winds up with the alignment we have
12374 record_alignment (asec
, op
->shift
);
12378 && (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
)
12379 || RELAX_MIPS16_DSLOT (fragp
->fr_subtype
)))
12380 as_warn_where (fragp
->fr_file
, fragp
->fr_line
,
12381 _("extended instruction in delay slot"));
12383 buf
= (bfd_byte
*) (fragp
->fr_literal
+ fragp
->fr_fix
);
12385 if (target_big_endian
)
12386 insn
= bfd_getb16 (buf
);
12388 insn
= bfd_getl16 (buf
);
12390 mips16_immed (fragp
->fr_file
, fragp
->fr_line
, type
, val
,
12391 RELAX_MIPS16_USER_EXT (fragp
->fr_subtype
),
12392 small
, ext
, &insn
, &use_extend
, &extend
);
12396 md_number_to_chars (buf
, 0xf000 | extend
, 2);
12397 fragp
->fr_fix
+= 2;
12401 md_number_to_chars (buf
, insn
, 2);
12402 fragp
->fr_fix
+= 2;
12407 if (fragp
->fr_opcode
== NULL
)
12410 old
= RELAX_OLD (fragp
->fr_subtype
);
12411 new = RELAX_NEW (fragp
->fr_subtype
);
12412 fixptr
= fragp
->fr_literal
+ fragp
->fr_fix
;
12415 memcpy (fixptr
- old
, fixptr
, new);
12417 fragp
->fr_fix
+= new - old
;
12423 /* This function is called after the relocs have been generated.
12424 We've been storing mips16 text labels as odd. Here we convert them
12425 back to even for the convenience of the debugger. */
12428 mips_frob_file_after_relocs ()
12431 unsigned int count
, i
;
12433 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
12436 syms
= bfd_get_outsymbols (stdoutput
);
12437 count
= bfd_get_symcount (stdoutput
);
12438 for (i
= 0; i
< count
; i
++, syms
++)
12440 if (elf_symbol (*syms
)->internal_elf_sym
.st_other
== STO_MIPS16
12441 && ((*syms
)->value
& 1) != 0)
12443 (*syms
)->value
&= ~1;
12444 /* If the symbol has an odd size, it was probably computed
12445 incorrectly, so adjust that as well. */
12446 if ((elf_symbol (*syms
)->internal_elf_sym
.st_size
& 1) != 0)
12447 ++elf_symbol (*syms
)->internal_elf_sym
.st_size
;
12454 /* This function is called whenever a label is defined. It is used
12455 when handling branch delays; if a branch has a label, we assume we
12456 can not move it. */
12459 mips_define_label (sym
)
12462 struct insn_label_list
*l
;
12464 if (free_insn_labels
== NULL
)
12465 l
= (struct insn_label_list
*) xmalloc (sizeof *l
);
12468 l
= free_insn_labels
;
12469 free_insn_labels
= l
->next
;
12473 l
->next
= insn_labels
;
12477 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12479 /* Some special processing for a MIPS ELF file. */
12482 mips_elf_final_processing ()
12484 /* Write out the register information. */
12489 s
.ri_gprmask
= mips_gprmask
;
12490 s
.ri_cprmask
[0] = mips_cprmask
[0];
12491 s
.ri_cprmask
[1] = mips_cprmask
[1];
12492 s
.ri_cprmask
[2] = mips_cprmask
[2];
12493 s
.ri_cprmask
[3] = mips_cprmask
[3];
12494 /* The gp_value field is set by the MIPS ELF backend. */
12496 bfd_mips_elf32_swap_reginfo_out (stdoutput
, &s
,
12497 ((Elf32_External_RegInfo
*)
12498 mips_regmask_frag
));
12502 Elf64_Internal_RegInfo s
;
12504 s
.ri_gprmask
= mips_gprmask
;
12506 s
.ri_cprmask
[0] = mips_cprmask
[0];
12507 s
.ri_cprmask
[1] = mips_cprmask
[1];
12508 s
.ri_cprmask
[2] = mips_cprmask
[2];
12509 s
.ri_cprmask
[3] = mips_cprmask
[3];
12510 /* The gp_value field is set by the MIPS ELF backend. */
12512 bfd_mips_elf64_swap_reginfo_out (stdoutput
, &s
,
12513 ((Elf64_External_RegInfo
*)
12514 mips_regmask_frag
));
12517 /* Set the MIPS ELF flag bits. FIXME: There should probably be some
12518 sort of BFD interface for this. */
12519 if (mips_any_noreorder
)
12520 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_NOREORDER
;
12521 if (mips_pic
!= NO_PIC
)
12522 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_PIC
;
12524 /* Set the MIPS ELF ABI flags. */
12525 if (file_mips_abi
== NO_ABI
)
12527 else if (file_mips_abi
== O32_ABI
)
12528 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_O32
;
12529 else if (file_mips_abi
== O64_ABI
)
12530 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_O64
;
12531 else if (file_mips_abi
== EABI_ABI
)
12534 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_EABI64
;
12536 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_EABI32
;
12538 else if (file_mips_abi
== N32_ABI
)
12539 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ABI2
;
12541 /* Nothing to do for "64". */
12543 if (mips_32bitmode
)
12544 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_32BITMODE
;
12547 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */
12549 typedef struct proc
{
12551 unsigned long reg_mask
;
12552 unsigned long reg_offset
;
12553 unsigned long fpreg_mask
;
12554 unsigned long fpreg_offset
;
12555 unsigned long frame_offset
;
12556 unsigned long frame_reg
;
12557 unsigned long pc_reg
;
12560 static procS cur_proc
;
12561 static procS
*cur_proc_ptr
;
12562 static int numprocs
;
12564 /* Fill in an rs_align_code fragment. */
12567 mips_handle_align (fragp
)
12570 if (fragp
->fr_type
!= rs_align_code
)
12573 if (mips_opts
.mips16
)
12575 static const unsigned char be_nop
[] = { 0x65, 0x00 };
12576 static const unsigned char le_nop
[] = { 0x00, 0x65 };
12581 bytes
= fragp
->fr_next
->fr_address
- fragp
->fr_address
- fragp
->fr_fix
;
12582 p
= fragp
->fr_literal
+ fragp
->fr_fix
;
12587 fragp
->fr_fix
+= 1;
12590 memcpy (p
, (target_big_endian
? be_nop
: le_nop
), 2);
12594 /* For mips32, a nop is a zero, which we trivially get by doing nothing. */
12605 /* check for premature end, nesting errors, etc */
12607 as_warn (_("missing .end at end of assembly"));
12616 if (*input_line_pointer
== '-')
12618 ++input_line_pointer
;
12621 if (!ISDIGIT (*input_line_pointer
))
12622 as_bad (_("Expected simple number."));
12623 if (input_line_pointer
[0] == '0')
12625 if (input_line_pointer
[1] == 'x')
12627 input_line_pointer
+= 2;
12628 while (ISXDIGIT (*input_line_pointer
))
12631 val
|= hex_value (*input_line_pointer
++);
12633 return negative
? -val
: val
;
12637 ++input_line_pointer
;
12638 while (ISDIGIT (*input_line_pointer
))
12641 val
|= *input_line_pointer
++ - '0';
12643 return negative
? -val
: val
;
12646 if (!ISDIGIT (*input_line_pointer
))
12648 printf (_(" *input_line_pointer == '%c' 0x%02x\n"),
12649 *input_line_pointer
, *input_line_pointer
);
12650 as_warn (_("Invalid number"));
12653 while (ISDIGIT (*input_line_pointer
))
12656 val
+= *input_line_pointer
++ - '0';
12658 return negative
? -val
: val
;
12661 /* The .file directive; just like the usual .file directive, but there
12662 is an initial number which is the ECOFF file index. */
12666 int x ATTRIBUTE_UNUSED
;
12670 line
= get_number ();
12674 /* The .end directive. */
12678 int x ATTRIBUTE_UNUSED
;
12683 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
12686 demand_empty_rest_of_line ();
12691 #ifdef BFD_ASSEMBLER
12692 if ((bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) != 0)
12697 if (now_seg
!= data_section
&& now_seg
!= bss_section
)
12704 as_warn (_(".end not in text section"));
12708 as_warn (_(".end directive without a preceding .ent directive."));
12709 demand_empty_rest_of_line ();
12715 assert (S_GET_NAME (p
));
12716 if (strcmp (S_GET_NAME (p
), S_GET_NAME (cur_proc_ptr
->isym
)))
12717 as_warn (_(".end symbol does not match .ent symbol."));
12720 as_warn (_(".end directive missing or unknown symbol"));
12722 #ifdef MIPS_STABS_ELF
12724 segT saved_seg
= now_seg
;
12725 subsegT saved_subseg
= now_subseg
;
12730 dot
= frag_now_fix ();
12732 #ifdef md_flush_pending_output
12733 md_flush_pending_output ();
12737 subseg_set (pdr_seg
, 0);
12739 /* Write the symbol. */
12740 exp
.X_op
= O_symbol
;
12741 exp
.X_add_symbol
= p
;
12742 exp
.X_add_number
= 0;
12743 emit_expr (&exp
, 4);
12745 fragp
= frag_more (7 * 4);
12747 md_number_to_chars (fragp
, (valueT
) cur_proc_ptr
->reg_mask
, 4);
12748 md_number_to_chars (fragp
+ 4, (valueT
) cur_proc_ptr
->reg_offset
, 4);
12749 md_number_to_chars (fragp
+ 8, (valueT
) cur_proc_ptr
->fpreg_mask
, 4);
12750 md_number_to_chars (fragp
+ 12, (valueT
) cur_proc_ptr
->fpreg_offset
, 4);
12751 md_number_to_chars (fragp
+ 16, (valueT
) cur_proc_ptr
->frame_offset
, 4);
12752 md_number_to_chars (fragp
+ 20, (valueT
) cur_proc_ptr
->frame_reg
, 4);
12753 md_number_to_chars (fragp
+ 24, (valueT
) cur_proc_ptr
->pc_reg
, 4);
12755 subseg_set (saved_seg
, saved_subseg
);
12759 cur_proc_ptr
= NULL
;
12762 /* The .aent and .ent directives. */
12772 symbolP
= get_symbol ();
12773 if (*input_line_pointer
== ',')
12774 input_line_pointer
++;
12775 SKIP_WHITESPACE ();
12776 if (ISDIGIT (*input_line_pointer
)
12777 || *input_line_pointer
== '-')
12778 number
= get_number ();
12780 #ifdef BFD_ASSEMBLER
12781 if ((bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) != 0)
12786 if (now_seg
!= data_section
&& now_seg
!= bss_section
)
12793 as_warn (_(".ent or .aent not in text section."));
12795 if (!aent
&& cur_proc_ptr
)
12796 as_warn (_("missing .end"));
12800 cur_proc_ptr
= &cur_proc
;
12801 memset (cur_proc_ptr
, '\0', sizeof (procS
));
12803 cur_proc_ptr
->isym
= symbolP
;
12805 symbol_get_bfdsym (symbolP
)->flags
|= BSF_FUNCTION
;
12810 demand_empty_rest_of_line ();
12813 /* The .frame directive. If the mdebug section is present (IRIX 5 native)
12814 then ecoff.c (ecoff_directive_frame) is used. For embedded targets,
12815 s_mips_frame is used so that we can set the PDR information correctly.
12816 We can't use the ecoff routines because they make reference to the ecoff
12817 symbol table (in the mdebug section). */
12820 s_mips_frame (ignore
)
12821 int ignore ATTRIBUTE_UNUSED
;
12823 #ifdef MIPS_STABS_ELF
12827 if (cur_proc_ptr
== (procS
*) NULL
)
12829 as_warn (_(".frame outside of .ent"));
12830 demand_empty_rest_of_line ();
12834 cur_proc_ptr
->frame_reg
= tc_get_register (1);
12836 SKIP_WHITESPACE ();
12837 if (*input_line_pointer
++ != ','
12838 || get_absolute_expression_and_terminator (&val
) != ',')
12840 as_warn (_("Bad .frame directive"));
12841 --input_line_pointer
;
12842 demand_empty_rest_of_line ();
12846 cur_proc_ptr
->frame_offset
= val
;
12847 cur_proc_ptr
->pc_reg
= tc_get_register (0);
12849 demand_empty_rest_of_line ();
12852 #endif /* MIPS_STABS_ELF */
12855 /* The .fmask and .mask directives. If the mdebug section is present
12856 (IRIX 5 native) then ecoff.c (ecoff_directive_mask) is used. For
12857 embedded targets, s_mips_mask is used so that we can set the PDR
12858 information correctly. We can't use the ecoff routines because they
12859 make reference to the ecoff symbol table (in the mdebug section). */
12862 s_mips_mask (reg_type
)
12865 #ifdef MIPS_STABS_ELF
12868 if (cur_proc_ptr
== (procS
*) NULL
)
12870 as_warn (_(".mask/.fmask outside of .ent"));
12871 demand_empty_rest_of_line ();
12875 if (get_absolute_expression_and_terminator (&mask
) != ',')
12877 as_warn (_("Bad .mask/.fmask directive"));
12878 --input_line_pointer
;
12879 demand_empty_rest_of_line ();
12883 off
= get_absolute_expression ();
12885 if (reg_type
== 'F')
12887 cur_proc_ptr
->fpreg_mask
= mask
;
12888 cur_proc_ptr
->fpreg_offset
= off
;
12892 cur_proc_ptr
->reg_mask
= mask
;
12893 cur_proc_ptr
->reg_offset
= off
;
12896 demand_empty_rest_of_line ();
12898 s_ignore (reg_type
);
12899 #endif /* MIPS_STABS_ELF */
12902 /* The .loc directive. */
12913 assert (now_seg
== text_section
);
12915 lineno
= get_number ();
12916 addroff
= frag_now_fix ();
12918 symbolP
= symbol_new ("", N_SLINE
, addroff
, frag_now
);
12919 S_SET_TYPE (symbolP
, N_SLINE
);
12920 S_SET_OTHER (symbolP
, 0);
12921 S_SET_DESC (symbolP
, lineno
);
12922 symbolP
->sy_segment
= now_seg
;
12926 /* CPU name/ISA/number mapping table.
12928 Entries are grouped by type. The first matching CPU or ISA entry
12929 gets chosen by CPU or ISA, so it should be the 'canonical' name
12930 for that type. Entries after that within the type are sorted
12933 Case is ignored in comparison, so put the canonical entry in the
12934 appropriate case but everything else in lower case to ease eye pain. */
12935 static const struct mips_cpu_info mips_cpu_info_table
[] =
12938 { "MIPS1", 1, ISA_MIPS1
, CPU_R3000
, },
12939 { "mips", 1, ISA_MIPS1
, CPU_R3000
, },
12942 { "MIPS2", 1, ISA_MIPS2
, CPU_R6000
, },
12945 { "MIPS3", 1, ISA_MIPS3
, CPU_R4000
, },
12948 { "MIPS4", 1, ISA_MIPS4
, CPU_R8000
, },
12951 { "MIPS5", 1, ISA_MIPS5
, CPU_MIPS5
, },
12952 { "Generic-MIPS5", 0, ISA_MIPS5
, CPU_MIPS5
, },
12955 { "MIPS32", 1, ISA_MIPS32
, CPU_MIPS32
, },
12956 { "mipsisa32", 0, ISA_MIPS32
, CPU_MIPS32
, },
12957 { "Generic-MIPS32", 0, ISA_MIPS32
, CPU_MIPS32
, },
12958 { "4kc", 0, ISA_MIPS32
, CPU_MIPS32
, },
12959 { "4km", 0, ISA_MIPS32
, CPU_MIPS32
, },
12960 { "4kp", 0, ISA_MIPS32
, CPU_MIPS32
, },
12962 /* For historical reasons. */
12963 { "MIPS64", 1, ISA_MIPS3
, CPU_R4000
, },
12966 { "mipsisa64", 1, ISA_MIPS64
, CPU_MIPS64
, },
12967 { "Generic-MIPS64", 0, ISA_MIPS64
, CPU_MIPS64
, },
12968 { "5kc", 0, ISA_MIPS64
, CPU_MIPS64
, },
12969 { "20kc", 0, ISA_MIPS64
, CPU_MIPS64
, },
12972 { "R2000", 0, ISA_MIPS1
, CPU_R2000
, },
12973 { "2000", 0, ISA_MIPS1
, CPU_R2000
, },
12974 { "2k", 0, ISA_MIPS1
, CPU_R2000
, },
12975 { "r2k", 0, ISA_MIPS1
, CPU_R2000
, },
12978 { "R3000", 0, ISA_MIPS1
, CPU_R3000
, },
12979 { "3000", 0, ISA_MIPS1
, CPU_R3000
, },
12980 { "3k", 0, ISA_MIPS1
, CPU_R3000
, },
12981 { "r3k", 0, ISA_MIPS1
, CPU_R3000
, },
12984 { "R3900", 0, ISA_MIPS1
, CPU_R3900
, },
12985 { "3900", 0, ISA_MIPS1
, CPU_R3900
, },
12986 { "mipstx39", 0, ISA_MIPS1
, CPU_R3900
, },
12989 { "R4000", 0, ISA_MIPS3
, CPU_R4000
, },
12990 { "4000", 0, ISA_MIPS3
, CPU_R4000
, },
12991 { "4k", 0, ISA_MIPS3
, CPU_R4000
, }, /* beware */
12992 { "r4k", 0, ISA_MIPS3
, CPU_R4000
, },
12995 { "R4010", 0, ISA_MIPS2
, CPU_R4010
, },
12996 { "4010", 0, ISA_MIPS2
, CPU_R4010
, },
12999 { "R4400", 0, ISA_MIPS3
, CPU_R4400
, },
13000 { "4400", 0, ISA_MIPS3
, CPU_R4400
, },
13003 { "R4600", 0, ISA_MIPS3
, CPU_R4600
, },
13004 { "4600", 0, ISA_MIPS3
, CPU_R4600
, },
13005 { "mips64orion", 0, ISA_MIPS3
, CPU_R4600
, },
13006 { "orion", 0, ISA_MIPS3
, CPU_R4600
, },
13009 { "R4650", 0, ISA_MIPS3
, CPU_R4650
, },
13010 { "4650", 0, ISA_MIPS3
, CPU_R4650
, },
13013 { "R6000", 0, ISA_MIPS2
, CPU_R6000
, },
13014 { "6000", 0, ISA_MIPS2
, CPU_R6000
, },
13015 { "6k", 0, ISA_MIPS2
, CPU_R6000
, },
13016 { "r6k", 0, ISA_MIPS2
, CPU_R6000
, },
13019 { "R8000", 0, ISA_MIPS4
, CPU_R8000
, },
13020 { "8000", 0, ISA_MIPS4
, CPU_R8000
, },
13021 { "8k", 0, ISA_MIPS4
, CPU_R8000
, },
13022 { "r8k", 0, ISA_MIPS4
, CPU_R8000
, },
13025 { "R10000", 0, ISA_MIPS4
, CPU_R10000
, },
13026 { "10000", 0, ISA_MIPS4
, CPU_R10000
, },
13027 { "10k", 0, ISA_MIPS4
, CPU_R10000
, },
13028 { "r10k", 0, ISA_MIPS4
, CPU_R10000
, },
13031 { "R12000", 0, ISA_MIPS4
, CPU_R12000
, },
13032 { "12000", 0, ISA_MIPS4
, CPU_R12000
, },
13033 { "12k", 0, ISA_MIPS4
, CPU_R12000
, },
13034 { "r12k", 0, ISA_MIPS4
, CPU_R12000
, },
13037 { "VR4100", 0, ISA_MIPS3
, CPU_VR4100
, },
13038 { "4100", 0, ISA_MIPS3
, CPU_VR4100
, },
13039 { "mips64vr4100", 0, ISA_MIPS3
, CPU_VR4100
, },
13040 { "r4100", 0, ISA_MIPS3
, CPU_VR4100
, },
13043 { "VR4111", 0, ISA_MIPS3
, CPU_R4111
, },
13044 { "4111", 0, ISA_MIPS3
, CPU_R4111
, },
13045 { "mips64vr4111", 0, ISA_MIPS3
, CPU_R4111
, },
13046 { "r4111", 0, ISA_MIPS3
, CPU_R4111
, },
13049 { "VR4300", 0, ISA_MIPS3
, CPU_R4300
, },
13050 { "4300", 0, ISA_MIPS3
, CPU_R4300
, },
13051 { "mips64vr4300", 0, ISA_MIPS3
, CPU_R4300
, },
13052 { "r4300", 0, ISA_MIPS3
, CPU_R4300
, },
13055 { "VR5000", 0, ISA_MIPS4
, CPU_R5000
, },
13056 { "5000", 0, ISA_MIPS4
, CPU_R5000
, },
13057 { "5k", 0, ISA_MIPS4
, CPU_R5000
, },
13058 { "mips64vr5000", 0, ISA_MIPS4
, CPU_R5000
, },
13059 { "r5000", 0, ISA_MIPS4
, CPU_R5000
, },
13060 { "r5200", 0, ISA_MIPS4
, CPU_R5000
, },
13061 { "rm5200", 0, ISA_MIPS4
, CPU_R5000
, },
13062 { "r5230", 0, ISA_MIPS4
, CPU_R5000
, },
13063 { "rm5230", 0, ISA_MIPS4
, CPU_R5000
, },
13064 { "r5231", 0, ISA_MIPS4
, CPU_R5000
, },
13065 { "rm5231", 0, ISA_MIPS4
, CPU_R5000
, },
13066 { "r5261", 0, ISA_MIPS4
, CPU_R5000
, },
13067 { "rm5261", 0, ISA_MIPS4
, CPU_R5000
, },
13068 { "r5721", 0, ISA_MIPS4
, CPU_R5000
, },
13069 { "rm5721", 0, ISA_MIPS4
, CPU_R5000
, },
13070 { "r5k", 0, ISA_MIPS4
, CPU_R5000
, },
13071 { "r7000", 0, ISA_MIPS4
, CPU_R5000
, },
13073 /* Broadcom SB-1 CPU */
13074 { "SB-1", 0, ISA_MIPS64
, CPU_SB1
, },
13075 { "sb-1250", 0, ISA_MIPS64
, CPU_SB1
, },
13076 { "sb1", 0, ISA_MIPS64
, CPU_SB1
, },
13077 { "sb1250", 0, ISA_MIPS64
, CPU_SB1
, },
13080 { NULL
, 0, 0, 0, },
13083 static const struct mips_cpu_info
*
13084 mips_cpu_info_from_name (name
)
13089 for (i
= 0; mips_cpu_info_table
[i
].name
!= NULL
; i
++)
13090 if (strcasecmp (name
, mips_cpu_info_table
[i
].name
) == 0)
13091 return (&mips_cpu_info_table
[i
]);
13096 static const struct mips_cpu_info
*
13097 mips_cpu_info_from_isa (isa
)
13102 for (i
= 0; mips_cpu_info_table
[i
].name
!= NULL
; i
++)
13103 if (mips_cpu_info_table
[i
].is_isa
13104 && isa
== mips_cpu_info_table
[i
].isa
)
13105 return (&mips_cpu_info_table
[i
]);
13110 static const struct mips_cpu_info
*
13111 mips_cpu_info_from_cpu (cpu
)
13116 for (i
= 0; mips_cpu_info_table
[i
].name
!= NULL
; i
++)
13117 if (!mips_cpu_info_table
[i
].is_isa
13118 && cpu
== mips_cpu_info_table
[i
].cpu
)
13119 return (&mips_cpu_info_table
[i
]);