1 /* tc-mips.c -- assemble code for a MIPS chip.
2 Copyright (C) 1993, 1994, 1995, 1996, 1997 Free Software Foundation, Inc.
3 Contributed by the OSF and Ralph Campbell.
4 Written by Keith Knowles and Ralph Campbell, working independently.
5 Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus
8 This file is part of GAS.
10 GAS is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 2, or (at your option)
15 GAS is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with GAS; see the file COPYING. If not, write to the Free
22 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
38 #include "opcode/mips.h"
41 /* Clean up namespace so we can include obj-elf.h too. */
42 static int mips_output_flavor () { return OUTPUT_FLAVOR
; }
43 #undef OBJ_PROCESS_STAB
49 #undef TARGET_SYMBOL_FIELDS
51 #undef obj_frob_file_after_relocs
52 #undef obj_frob_symbol
54 #undef obj_sec_sym_ok_for_reloc
57 /* Fix any of them that we actually care about. */
59 #define OUTPUT_FLAVOR mips_output_flavor()
66 #ifndef ECOFF_DEBUGGING
67 #define NO_ECOFF_DEBUGGING
68 #define ECOFF_DEBUGGING 0
73 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
74 static char *mips_regmask_frag
;
79 #define PIC_CALL_REG 25
87 #define ILLEGAL_REG (32)
89 extern int target_big_endian
;
91 /* 1 is we should use the 64 bit MIPS ELF ABI, 0 if we should use the
92 32 bit ABI. This has no meaning for ECOFF. */
95 /* The default target format to use. */
99 switch (OUTPUT_FLAVOR
)
101 case bfd_target_aout_flavour
:
102 return target_big_endian
? "a.out-mips-big" : "a.out-mips-little";
103 case bfd_target_ecoff_flavour
:
104 return target_big_endian
? "ecoff-bigmips" : "ecoff-littlemips";
105 case bfd_target_elf_flavour
:
106 return (target_big_endian
107 ? (mips_64
? "elf64-bigmips" : "elf32-bigmips")
108 : (mips_64
? "elf64-littlemips" : "elf32-littlemips"));
114 /* The name of the readonly data section. */
115 #define RDATA_SECTION_NAME (OUTPUT_FLAVOR == bfd_target_aout_flavour \
117 : OUTPUT_FLAVOR == bfd_target_ecoff_flavour \
119 : OUTPUT_FLAVOR == bfd_target_elf_flavour \
123 /* These variables are filled in with the masks of registers used.
124 The object format code reads them and puts them in the appropriate
126 unsigned long mips_gprmask
;
127 unsigned long mips_cprmask
[4];
129 /* MIPS ISA (Instruction Set Architecture) level (may be changed
130 temporarily using .set mipsN). */
131 static int mips_isa
= -1;
133 /* MIPS ISA we are using for this output file. */
134 static int file_mips_isa
;
136 /* Whether we are assembling for the mips16 processor. */
137 static int mips16
= -1;
139 /* The CPU type as a number: 2000, 3000, 4000, 4400, etc. */
140 static int mips_cpu
= -1;
142 /* Whether the 4650 instructions (mad/madu) are permitted. */
143 static int mips_4650
= -1;
145 /* Whether the 4010 instructions are permitted. */
146 static int mips_4010
= -1;
148 /* Whether the 4100 MADD16 and DMADD16 are permitted. */
149 static int mips_4100
= -1;
151 /* Whether the processor uses hardware interlocks, and thus does not
152 require nops to be inserted. */
153 static int interlocks
= -1;
155 /* As with "interlocks" this is used by hardware that has FP
156 (co-processor) interlocks. */
157 static int cop_interlocks
= -1;
159 /* MIPS PIC level. */
163 /* Do not generate PIC code. */
166 /* Generate PIC code as in Irix 4. This is not implemented, and I'm
167 not sure what it is supposed to do. */
170 /* Generate PIC code as in the SVR4 MIPS ABI. */
173 /* Generate PIC code without using a global offset table: the data
174 segment has a maximum size of 64K, all data references are off
175 the $gp register, and all text references are PC relative. This
176 is used on some embedded systems. */
180 static enum mips_pic_level mips_pic
;
182 /* 1 if we should generate 32 bit offsets from the GP register in
183 SVR4_PIC mode. Currently has no meaning in other modes. */
184 static int mips_big_got
;
186 /* 1 if trap instructions should used for overflow rather than break
188 static int mips_trap
;
190 /* 1 if we should autoextend mips16 instructions. */
191 static int mips16_autoextend
= 1;
193 static int mips_warn_about_macros
;
194 static int mips_noreorder
;
195 static int mips_any_noreorder
;
196 static int mips_nomove
;
197 static int mips_noat
;
198 static int mips_nobopt
;
200 /* The size of the small data section. */
201 static int g_switch_value
= 8;
202 /* Whether the -G option was used. */
203 static int g_switch_seen
= 0;
208 /* If we can determine in advance that GP optimization won't be
209 possible, we can skip the relaxation stuff that tries to produce
210 GP-relative references. This makes delay slot optimization work
213 This function can only provide a guess, but it seems to work for
214 gcc output. If it guesses wrong, the only loss should be in
215 efficiency; it shouldn't introduce any bugs.
217 I don't know if a fix is needed for the SVR4_PIC mode. I've only
218 fixed it for the non-PIC mode. KR 95/04/07 */
219 static int nopic_need_relax
PARAMS ((symbolS
*));
221 /* handle of the OPCODE hash table */
222 static struct hash_control
*op_hash
= NULL
;
224 /* The opcode hash table we use for the mips16. */
225 static struct hash_control
*mips16_op_hash
= NULL
;
227 /* This array holds the chars that always start a comment. If the
228 pre-processor is disabled, these aren't very useful */
229 const char comment_chars
[] = "#";
231 /* This array holds the chars that only start a comment at the beginning of
232 a line. If the line seems to have the form '# 123 filename'
233 .line and .file directives will appear in the pre-processed output */
234 /* Note that input_file.c hand checks for '#' at the beginning of the
235 first line of the input file. This is because the compiler outputs
236 #NO_APP at the beginning of its output. */
237 /* Also note that C style comments are always supported. */
238 const char line_comment_chars
[] = "#";
240 /* This array holds machine specific line separator characters. */
241 const char line_separator_chars
[] = "";
243 /* Chars that can be used to separate mant from exp in floating point nums */
244 const char EXP_CHARS
[] = "eE";
246 /* Chars that mean this number is a floating point constant */
249 const char FLT_CHARS
[] = "rRsSfFdDxXpP";
251 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
252 changed in read.c . Ideally it shouldn't have to know about it at all,
253 but nothing is ideal around here.
256 static char *insn_error
;
258 static int auto_align
= 1;
260 /* When outputting SVR4 PIC code, the assembler needs to know the
261 offset in the stack frame from which to restore the $gp register.
262 This is set by the .cprestore pseudo-op, and saved in this
264 static offsetT mips_cprestore_offset
= -1;
266 /* This is the register which holds the stack frame, as set by the
267 .frame pseudo-op. This is needed to implement .cprestore. */
268 static int mips_frame_reg
= SP
;
270 /* To output NOP instructions correctly, we need to keep information
271 about the previous two instructions. */
273 /* Whether we are optimizing. The default value of 2 means to remove
274 unneeded NOPs and swap branch instructions when possible. A value
275 of 1 means to not swap branches. A value of 0 means to always
277 static int mips_optimize
= 2;
279 /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is
280 equivalent to seeing no -g option at all. */
281 static int mips_debug
= 0;
283 /* The previous instruction. */
284 static struct mips_cl_insn prev_insn
;
286 /* The instruction before prev_insn. */
287 static struct mips_cl_insn prev_prev_insn
;
289 /* If we don't want information for prev_insn or prev_prev_insn, we
290 point the insn_mo field at this dummy integer. */
291 static const struct mips_opcode dummy_opcode
= { 0 };
293 /* Non-zero if prev_insn is valid. */
294 static int prev_insn_valid
;
296 /* The frag for the previous instruction. */
297 static struct frag
*prev_insn_frag
;
299 /* The offset into prev_insn_frag for the previous instruction. */
300 static long prev_insn_where
;
302 /* The reloc type for the previous instruction, if any. */
303 static bfd_reloc_code_real_type prev_insn_reloc_type
;
305 /* The reloc for the previous instruction, if any. */
306 static fixS
*prev_insn_fixp
;
308 /* Non-zero if the previous instruction was in a delay slot. */
309 static int prev_insn_is_delay_slot
;
311 /* Non-zero if the previous instruction was in a .set noreorder. */
312 static int prev_insn_unreordered
;
314 /* Non-zero if the previous instruction uses an extend opcode (if
316 static int prev_insn_extended
;
318 /* Non-zero if the previous previous instruction was in a .set
320 static int prev_prev_insn_unreordered
;
322 /* For ECOFF and ELF, relocations against symbols are done in two
323 parts, with a HI relocation and a LO relocation. Each relocation
324 has only 16 bits of space to store an addend. This means that in
325 order for the linker to handle carries correctly, it must be able
326 to locate both the HI and the LO relocation. This means that the
327 relocations must appear in order in the relocation table.
329 In order to implement this, we keep track of each unmatched HI
330 relocation. We then sort them so that they immediately precede the
331 corresponding LO relocation. */
336 struct mips_hi_fixup
*next
;
339 /* The section this fixup is in. */
343 /* The list of unmatched HI relocs. */
345 static struct mips_hi_fixup
*mips_hi_fixup_list
;
347 /* Map normal MIPS register numbers to mips16 register numbers. */
349 #define X ILLEGAL_REG
350 static const int mips32_to_16_reg_map
[] =
352 X
, X
, 2, 3, 4, 5, 6, 7,
353 X
, X
, X
, X
, X
, X
, X
, X
,
354 0, 1, X
, X
, X
, X
, X
, X
,
355 X
, X
, X
, X
, X
, X
, X
, X
359 /* Map mips16 register numbers to normal MIPS register numbers. */
361 static const int mips16_to_32_reg_map
[] =
363 16, 17, 2, 3, 4, 5, 6, 7
366 /* Since the MIPS does not have multiple forms of PC relative
367 instructions, we do not have to do relaxing as is done on other
368 platforms. However, we do have to handle GP relative addressing
369 correctly, which turns out to be a similar problem.
371 Every macro that refers to a symbol can occur in (at least) two
372 forms, one with GP relative addressing and one without. For
373 example, loading a global variable into a register generally uses
374 a macro instruction like this:
376 If i can be addressed off the GP register (this is true if it is in
377 the .sbss or .sdata section, or if it is known to be smaller than
378 the -G argument) this will generate the following instruction:
380 This instruction will use a GPREL reloc. If i can not be addressed
381 off the GP register, the following instruction sequence will be used:
384 In this case the first instruction will have a HI16 reloc, and the
385 second reloc will have a LO16 reloc. Both relocs will be against
388 The issue here is that we may not know whether i is GP addressable
389 until after we see the instruction that uses it. Therefore, we
390 want to be able to choose the final instruction sequence only at
391 the end of the assembly. This is similar to the way other
392 platforms choose the size of a PC relative instruction only at the
395 When generating position independent code we do not use GP
396 addressing in quite the same way, but the issue still arises as
397 external symbols and local symbols must be handled differently.
399 We handle these issues by actually generating both possible
400 instruction sequences. The longer one is put in a frag_var with
401 type rs_machine_dependent. We encode what to do with the frag in
402 the subtype field. We encode (1) the number of existing bytes to
403 replace, (2) the number of new bytes to use, (3) the offset from
404 the start of the existing bytes to the first reloc we must generate
405 (that is, the offset is applied from the start of the existing
406 bytes after they are replaced by the new bytes, if any), (4) the
407 offset from the start of the existing bytes to the second reloc,
408 (5) whether a third reloc is needed (the third reloc is always four
409 bytes after the second reloc), and (6) whether to warn if this
410 variant is used (this is sometimes needed if .set nomacro or .set
411 noat is in effect). All these numbers are reasonably small.
413 Generating two instruction sequences must be handled carefully to
414 ensure that delay slots are handled correctly. Fortunately, there
415 are a limited number of cases. When the second instruction
416 sequence is generated, append_insn is directed to maintain the
417 existing delay slot information, so it continues to apply to any
418 code after the second instruction sequence. This means that the
419 second instruction sequence must not impose any requirements not
420 required by the first instruction sequence.
422 These variant frags are then handled in functions called by the
423 machine independent code. md_estimate_size_before_relax returns
424 the final size of the frag. md_convert_frag sets up the final form
425 of the frag. tc_gen_reloc adjust the first reloc and adds a second
427 #define RELAX_ENCODE(old, new, reloc1, reloc2, reloc3, warn) \
431 | (((reloc1) + 64) << 9) \
432 | (((reloc2) + 64) << 2) \
433 | ((reloc3) ? (1 << 1) : 0) \
435 #define RELAX_OLD(i) (((i) >> 23) & 0x7f)
436 #define RELAX_NEW(i) (((i) >> 16) & 0x7f)
437 #define RELAX_RELOC1(i) ((bfd_vma)(((i) >> 9) & 0x7f) - 64)
438 #define RELAX_RELOC2(i) ((bfd_vma)(((i) >> 2) & 0x7f) - 64)
439 #define RELAX_RELOC3(i) (((i) >> 1) & 1)
440 #define RELAX_WARN(i) ((i) & 1)
442 /* For mips16 code, we use an entirely different form of relaxation.
443 mips16 supports two versions of most instructions which take
444 immediate values: a small one which takes some small value, and a
445 larger one which takes a 16 bit value. Since branches also follow
446 this pattern, relaxing these values is required.
448 We can assemble both mips16 and normal MIPS code in a single
449 object. Therefore, we need to support this type of relaxation at
450 the same time that we support the relaxation described above. We
451 use the high bit of the subtype field to distinguish these cases.
453 The information we store for this type of relaxation is the
454 argument code found in the opcode file for this relocation, whether
455 the user explicitly requested a small or extended form, and whether
456 the relocation is in a jump or jal delay slot. That tells us the
457 size of the value, and how it should be stored. We also store
458 whether the fragment is considered to be extended or not. We also
459 store whether this is known to be a branch to a different section,
460 whether we have tried to relax this frag yet, and whether we have
461 ever extended a PC relative fragment because of a shift count. */
462 #define RELAX_MIPS16_ENCODE(type, small, ext, dslot, jal_dslot) \
465 | ((small) ? 0x100 : 0) \
466 | ((ext) ? 0x200 : 0) \
467 | ((dslot) ? 0x400 : 0) \
468 | ((jal_dslot) ? 0x800 : 0))
469 #define RELAX_MIPS16_P(i) (((i) & 0x80000000) != 0)
470 #define RELAX_MIPS16_TYPE(i) ((i) & 0xff)
471 #define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x100) != 0)
472 #define RELAX_MIPS16_USER_EXT(i) (((i) & 0x200) != 0)
473 #define RELAX_MIPS16_DSLOT(i) (((i) & 0x400) != 0)
474 #define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x800) != 0)
475 #define RELAX_MIPS16_EXTENDED(i) (((i) & 0x1000) != 0)
476 #define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x1000)
477 #define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) &~ 0x1000)
478 #define RELAX_MIPS16_LONG_BRANCH(i) (((i) & 0x2000) != 0)
479 #define RELAX_MIPS16_MARK_LONG_BRANCH(i) ((i) | 0x2000)
480 #define RELAX_MIPS16_CLEAR_LONG_BRANCH(i) ((i) &~ 0x2000)
482 /* Prototypes for static functions. */
485 #define internalError() \
486 as_fatal ("internal Error, line %d, %s", __LINE__, __FILE__)
488 #define internalError() as_fatal ("MIPS internal Error");
491 enum mips_regclass
{ MIPS_GR_REG
, MIPS_FP_REG
, MIPS16_REG
};
493 static int insn_uses_reg
PARAMS ((struct mips_cl_insn
*ip
,
494 unsigned int reg
, enum mips_regclass
class));
495 static int reg_needs_delay
PARAMS ((int));
496 static void append_insn
PARAMS ((char *place
,
497 struct mips_cl_insn
* ip
,
499 bfd_reloc_code_real_type r
,
501 static void mips_no_prev_insn
PARAMS ((void));
502 static void mips_emit_delays
PARAMS ((boolean
));
504 static void macro_build
PARAMS ((char *place
, int *counter
, expressionS
* ep
,
505 const char *name
, const char *fmt
,
508 static void macro_build ();
510 static void mips16_macro_build
PARAMS ((char *, int *, expressionS
*,
511 const char *, const char *,
513 static void macro_build_lui
PARAMS ((char *place
, int *counter
,
514 expressionS
* ep
, int regnum
));
515 static void set_at
PARAMS ((int *counter
, int reg
, int unsignedp
));
516 static void check_absolute_expr
PARAMS ((struct mips_cl_insn
* ip
,
518 static void load_register
PARAMS ((int *, int, expressionS
*, int));
519 static void load_address
PARAMS ((int *counter
, int reg
, expressionS
*ep
));
520 static void macro
PARAMS ((struct mips_cl_insn
* ip
));
521 static void mips16_macro
PARAMS ((struct mips_cl_insn
* ip
));
522 #ifdef LOSING_COMPILER
523 static void macro2
PARAMS ((struct mips_cl_insn
* ip
));
525 static void mips_ip
PARAMS ((char *str
, struct mips_cl_insn
* ip
));
526 static void mips16_ip
PARAMS ((char *str
, struct mips_cl_insn
* ip
));
527 static void mips16_immed
PARAMS ((char *, unsigned int, int, offsetT
, boolean
,
528 boolean
, boolean
, unsigned long *,
529 boolean
*, unsigned short *));
530 static int my_getSmallExpression
PARAMS ((expressionS
* ep
, char *str
));
531 static void my_getExpression
PARAMS ((expressionS
* ep
, char *str
));
532 static symbolS
*get_symbol
PARAMS ((void));
533 static void mips_align
PARAMS ((int to
, int fill
, symbolS
*label
));
534 static void s_align
PARAMS ((int));
535 static void s_change_sec
PARAMS ((int));
536 static void s_cons
PARAMS ((int));
537 static void s_float_cons
PARAMS ((int));
538 static void s_mips_globl
PARAMS ((int));
539 static void s_option
PARAMS ((int));
540 static void s_mipsset
PARAMS ((int));
541 static void s_abicalls
PARAMS ((int));
542 static void s_cpload
PARAMS ((int));
543 static void s_cprestore
PARAMS ((int));
544 static void s_gpword
PARAMS ((int));
545 static void s_cpadd
PARAMS ((int));
546 static void md_obj_begin
PARAMS ((void));
547 static void md_obj_end
PARAMS ((void));
548 static long get_number
PARAMS ((void));
549 static void s_ent
PARAMS ((int));
550 static void s_mipsend
PARAMS ((int));
551 static void s_file
PARAMS ((int));
552 static int mips16_extended_frag
PARAMS ((fragS
*, asection
*, long));
556 The following pseudo-ops from the Kane and Heinrich MIPS book
557 should be defined here, but are currently unsupported: .alias,
558 .galive, .gjaldef, .gjrlive, .livereg, .noalias.
560 The following pseudo-ops from the Kane and Heinrich MIPS book are
561 specific to the type of debugging information being generated, and
562 should be defined by the object format: .aent, .begin, .bend,
563 .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp,
566 The following pseudo-ops from the Kane and Heinrich MIPS book are
567 not MIPS CPU specific, but are also not specific to the object file
568 format. This file is probably the best place to define them, but
569 they are not currently supported: .asm0, .endr, .lab, .repeat,
570 .struct, .weakext. */
572 static const pseudo_typeS mips_pseudo_table
[] =
574 /* MIPS specific pseudo-ops. */
575 {"option", s_option
, 0},
576 {"set", s_mipsset
, 0},
577 {"rdata", s_change_sec
, 'r'},
578 {"sdata", s_change_sec
, 's'},
579 {"livereg", s_ignore
, 0},
580 {"abicalls", s_abicalls
, 0},
581 {"cpload", s_cpload
, 0},
582 {"cprestore", s_cprestore
, 0},
583 {"gpword", s_gpword
, 0},
584 {"cpadd", s_cpadd
, 0},
586 /* Relatively generic pseudo-ops that happen to be used on MIPS
588 {"asciiz", stringer
, 1},
589 {"bss", s_change_sec
, 'b'},
592 {"dword", s_cons
, 3},
594 /* These pseudo-ops are defined in read.c, but must be overridden
595 here for one reason or another. */
596 {"align", s_align
, 0},
598 {"data", s_change_sec
, 'd'},
599 {"double", s_float_cons
, 'd'},
600 {"float", s_float_cons
, 'f'},
601 {"globl", s_mips_globl
, 0},
602 {"global", s_mips_globl
, 0},
603 {"hword", s_cons
, 1},
608 {"short", s_cons
, 1},
609 {"single", s_float_cons
, 'f'},
610 {"text", s_change_sec
, 't'},
615 static const pseudo_typeS mips_nonecoff_pseudo_table
[] = {
616 /* These pseudo-ops should be defined by the object file format.
617 However, a.out doesn't support them, so we have versions here. */
619 {"bgnb", s_ignore
, 0},
620 {"end", s_mipsend
, 0},
621 {"endb", s_ignore
, 0},
624 {"fmask", s_ignore
, 'F'},
625 {"frame", s_ignore
, 0},
626 {"loc", s_ignore
, 0},
627 {"mask", s_ignore
, 'R'},
628 {"verstamp", s_ignore
, 0},
632 extern void pop_insert
PARAMS ((const pseudo_typeS
*));
637 pop_insert (mips_pseudo_table
);
638 if (! ECOFF_DEBUGGING
)
639 pop_insert (mips_nonecoff_pseudo_table
);
642 /* Symbols labelling the current insn. */
644 struct insn_label_list
646 struct insn_label_list
*next
;
650 static struct insn_label_list
*insn_labels
;
651 static struct insn_label_list
*free_insn_labels
;
653 static void mips_clear_insn_labels
PARAMS ((void));
656 mips_clear_insn_labels ()
658 register struct insn_label_list
**pl
;
660 for (pl
= &free_insn_labels
; *pl
!= NULL
; pl
= &(*pl
)->next
)
666 static char *expr_end
;
668 /* Expressions which appear in instructions. These are set by
671 static expressionS imm_expr
;
672 static expressionS offset_expr
;
674 /* Relocs associated with imm_expr and offset_expr. */
676 static bfd_reloc_code_real_type imm_reloc
;
677 static bfd_reloc_code_real_type offset_reloc
;
679 /* This is set by mips_ip if imm_reloc is an unmatched HI16_S reloc. */
681 static boolean imm_unmatched_hi
;
683 /* These are set by mips16_ip if an explicit extension is used. */
685 static boolean mips16_small
, mips16_ext
;
688 * This function is called once, at assembler startup time. It should
689 * set up all the tables, etc. that the MD part of the assembler will need.
695 register const char *retval
= NULL
;
696 register unsigned int i
= 0;
704 if (strcmp (cpu
+ (sizeof TARGET_CPU
) - 3, "el") == 0)
706 a
= xmalloc (sizeof TARGET_CPU
);
707 strcpy (a
, TARGET_CPU
);
708 a
[(sizeof TARGET_CPU
) - 3] = '\0';
712 if (strcmp (cpu
, "mips") == 0)
718 else if (strcmp (cpu
, "r6000") == 0
719 || strcmp (cpu
, "mips2") == 0)
725 else if (strcmp (cpu
, "mips64") == 0
726 || strcmp (cpu
, "r4000") == 0
727 || strcmp (cpu
, "mips3") == 0)
733 else if (strcmp (cpu
, "r4400") == 0)
739 else if (strcmp (cpu
, "mips64orion") == 0
740 || strcmp (cpu
, "r4600") == 0)
746 else if (strcmp (cpu
, "r4650") == 0)
754 else if (strcmp (cpu
, "mips64vr4300") == 0)
760 else if (strcmp (cpu
, "mips64vr4100") == 0)
768 else if (strcmp (cpu
, "r4010") == 0)
776 else if (strcmp (cpu
, "r5000") == 0
777 || strcmp (cpu
, "mips64vr5000") == 0)
783 else if (strcmp (cpu
, "r8000") == 0
784 || strcmp (cpu
, "mips4") == 0)
790 else if (strcmp (cpu
, "r10000") == 0)
796 else if (strcmp (cpu
, "mips16") == 0)
800 mips_cpu
= 0; /* FIXME */
815 if (strncmp (TARGET_CPU
, "mips16", sizeof "mips16" - 1) == 0)
830 if (mips_4010
|| mips_4100
|| mips_cpu
== 4300)
835 if (mips_cpu
== 4300)
840 if (mips_isa
< 2 && mips_trap
)
841 as_bad ("trap exception not supported at ISA 1");
846 ok
= bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, 3000);
849 ok
= bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, 6000);
852 ok
= bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, 4000);
855 ok
= bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, 8000);
859 as_warn ("Could not set architecture and machine");
861 file_mips_isa
= mips_isa
;
863 op_hash
= hash_new ();
865 for (i
= 0; i
< NUMOPCODES
;)
867 const char *name
= mips_opcodes
[i
].name
;
869 retval
= hash_insert (op_hash
, name
, (PTR
) &mips_opcodes
[i
]);
872 fprintf (stderr
, "internal error: can't hash `%s': %s\n",
873 mips_opcodes
[i
].name
, retval
);
874 as_fatal ("Broken assembler. No assembly attempted.");
878 if (mips_opcodes
[i
].pinfo
!= INSN_MACRO
879 && ((mips_opcodes
[i
].match
& mips_opcodes
[i
].mask
)
880 != mips_opcodes
[i
].match
))
882 fprintf (stderr
, "internal error: bad opcode: `%s' \"%s\"\n",
883 mips_opcodes
[i
].name
, mips_opcodes
[i
].args
);
884 as_fatal ("Broken assembler. No assembly attempted.");
888 while ((i
< NUMOPCODES
) && !strcmp (mips_opcodes
[i
].name
, name
));
891 mips16_op_hash
= hash_new ();
894 while (i
< bfd_mips16_num_opcodes
)
896 const char *name
= mips16_opcodes
[i
].name
;
898 retval
= hash_insert (mips16_op_hash
, name
, (PTR
) &mips16_opcodes
[i
]);
900 as_fatal ("internal error: can't hash `%s': %s\n",
901 mips16_opcodes
[i
].name
, retval
);
904 if (mips16_opcodes
[i
].pinfo
!= INSN_MACRO
905 && ((mips16_opcodes
[i
].match
& mips16_opcodes
[i
].mask
)
906 != mips16_opcodes
[i
].match
))
907 as_fatal ("internal error: bad opcode: `%s' \"%s\"\n",
908 mips16_opcodes
[i
].name
, mips16_opcodes
[i
].args
);
911 while (i
< bfd_mips16_num_opcodes
912 && strcmp (mips16_opcodes
[i
].name
, name
) == 0);
915 mips_no_prev_insn ();
923 /* set the default alignment for the text section (2**2) */
924 record_alignment (text_section
, 2);
926 if (USE_GLOBAL_POINTER_OPT
)
927 bfd_set_gp_size (stdoutput
, g_switch_value
);
929 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
931 /* On a native system, sections must be aligned to 16 byte
932 boundaries. When configured for an embedded ELF target, we
934 if (strcmp (TARGET_OS
, "elf") != 0)
936 (void) bfd_set_section_alignment (stdoutput
, text_section
, 4);
937 (void) bfd_set_section_alignment (stdoutput
, data_section
, 4);
938 (void) bfd_set_section_alignment (stdoutput
, bss_section
, 4);
941 /* Create a .reginfo section for register masks and a .mdebug
942 section for debugging information. */
952 /* The ABI says this section should be loaded so that the
953 running program can access it. However, we don't load it
954 if we are configured for an embedded target */
955 flags
= SEC_READONLY
| SEC_DATA
;
956 if (strcmp (TARGET_OS
, "elf") != 0)
957 flags
|= SEC_ALLOC
| SEC_LOAD
;
961 sec
= subseg_new (".reginfo", (subsegT
) 0);
964 (void) bfd_set_section_flags (stdoutput
, sec
, flags
);
965 (void) bfd_set_section_alignment (stdoutput
, sec
, 2);
968 mips_regmask_frag
= frag_more (sizeof (Elf32_External_RegInfo
));
973 /* The 64-bit ABI uses a .MIPS.options section rather than
975 sec
= subseg_new (".MIPS.options", (subsegT
) 0);
976 (void) bfd_set_section_flags (stdoutput
, sec
, flags
);
977 (void) bfd_set_section_alignment (stdoutput
, sec
, 3);
980 /* Set up the option header. */
982 Elf_Internal_Options opthdr
;
985 opthdr
.kind
= ODK_REGINFO
;
986 opthdr
.size
= (sizeof (Elf_External_Options
)
987 + sizeof (Elf64_External_RegInfo
));
990 f
= frag_more (sizeof (Elf_External_Options
));
991 bfd_mips_elf_swap_options_out (stdoutput
, &opthdr
,
992 (Elf_External_Options
*) f
);
994 mips_regmask_frag
= frag_more (sizeof (Elf64_External_RegInfo
));
1001 sec
= subseg_new (".mdebug", (subsegT
) 0);
1002 (void) bfd_set_section_flags (stdoutput
, sec
,
1003 SEC_HAS_CONTENTS
| SEC_READONLY
);
1004 (void) bfd_set_section_alignment (stdoutput
, sec
, 2);
1007 subseg_set (seg
, subseg
);
1011 if (! ECOFF_DEBUGGING
)
1018 if (! ECOFF_DEBUGGING
)
1026 struct mips_cl_insn insn
;
1028 imm_expr
.X_op
= O_absent
;
1029 imm_reloc
= BFD_RELOC_UNUSED
;
1030 imm_unmatched_hi
= false;
1031 offset_expr
.X_op
= O_absent
;
1032 offset_reloc
= BFD_RELOC_UNUSED
;
1035 mips16_ip (str
, &insn
);
1037 mips_ip (str
, &insn
);
1041 as_bad ("%s `%s'", insn_error
, str
);
1045 if (insn
.insn_mo
->pinfo
== INSN_MACRO
)
1048 mips16_macro (&insn
);
1054 if (imm_expr
.X_op
!= O_absent
)
1055 append_insn ((char *) NULL
, &insn
, &imm_expr
, imm_reloc
,
1057 else if (offset_expr
.X_op
!= O_absent
)
1058 append_insn ((char *) NULL
, &insn
, &offset_expr
, offset_reloc
, false);
1060 append_insn ((char *) NULL
, &insn
, NULL
, BFD_RELOC_UNUSED
, false);
1064 /* See whether instruction IP reads register REG. CLASS is the type
1068 insn_uses_reg (ip
, reg
, class)
1069 struct mips_cl_insn
*ip
;
1071 enum mips_regclass
class;
1073 if (class == MIPS16_REG
)
1076 reg
= mips16_to_32_reg_map
[reg
];
1077 class = MIPS_GR_REG
;
1080 /* Don't report on general register 0, since it never changes. */
1081 if (class == MIPS_GR_REG
&& reg
== 0)
1084 if (class == MIPS_FP_REG
)
1087 /* If we are called with either $f0 or $f1, we must check $f0.
1088 This is not optimal, because it will introduce an unnecessary
1089 NOP between "lwc1 $f0" and "swc1 $f1". To fix this we would
1090 need to distinguish reading both $f0 and $f1 or just one of
1091 them. Note that we don't have to check the other way,
1092 because there is no instruction that sets both $f0 and $f1
1093 and requires a delay. */
1094 if ((ip
->insn_mo
->pinfo
& INSN_READ_FPR_S
)
1095 && (((ip
->insn_opcode
>> OP_SH_FS
) & OP_MASK_FS
)
1096 == (reg
&~ (unsigned) 1)))
1098 if ((ip
->insn_mo
->pinfo
& INSN_READ_FPR_T
)
1099 && (((ip
->insn_opcode
>> OP_SH_FT
) & OP_MASK_FT
)
1100 == (reg
&~ (unsigned) 1)))
1105 if ((ip
->insn_mo
->pinfo
& INSN_READ_GPR_S
)
1106 && ((ip
->insn_opcode
>> OP_SH_RS
) & OP_MASK_RS
) == reg
)
1108 if ((ip
->insn_mo
->pinfo
& INSN_READ_GPR_T
)
1109 && ((ip
->insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
) == reg
)
1114 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_X
)
1115 && ((ip
->insn_opcode
>> MIPS16OP_SH_RX
) & MIPS16OP_MASK_RX
) == reg
)
1117 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_Y
)
1118 && ((ip
->insn_opcode
>> MIPS16OP_SH_RY
) & MIPS16OP_MASK_RY
) == reg
)
1120 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_Z
)
1121 && ((ip
->insn_opcode
>> MIPS16OP_SH_MOVE32Z
)
1122 & MIPS16OP_MASK_MOVE32Z
) == reg
)
1124 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_T
) && reg
== TREG
)
1126 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_SP
) && reg
== SP
)
1128 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_31
) && reg
== RA
)
1130 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_GPR_X
)
1131 && ((ip
->insn_opcode
>> MIPS16OP_SH_REGR32
)
1132 & MIPS16OP_MASK_REGR32
) == reg
)
1139 /* This function returns true if modifying a register requires a
1143 reg_needs_delay (reg
)
1146 unsigned long prev_pinfo
;
1148 prev_pinfo
= prev_insn
.insn_mo
->pinfo
;
1149 if (! mips_noreorder
1151 && ((prev_pinfo
& INSN_LOAD_COPROC_DELAY
)
1153 && (prev_pinfo
& INSN_LOAD_MEMORY_DELAY
))))
1155 /* A load from a coprocessor or from memory. All load
1156 delays delay the use of general register rt for one
1157 instruction on the r3000. The r6000 and r4000 use
1159 know (prev_pinfo
& INSN_WRITE_GPR_T
);
1160 if (reg
== ((prev_insn
.insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
))
1167 /* Output an instruction. PLACE is where to put the instruction; if
1168 it is NULL, this uses frag_more to get room. IP is the instruction
1169 information. ADDRESS_EXPR is an operand of the instruction to be
1170 used with RELOC_TYPE. */
1173 append_insn (place
, ip
, address_expr
, reloc_type
, unmatched_hi
)
1175 struct mips_cl_insn
*ip
;
1176 expressionS
*address_expr
;
1177 bfd_reloc_code_real_type reloc_type
;
1178 boolean unmatched_hi
;
1180 register unsigned long prev_pinfo
, pinfo
;
1185 /* Mark instruction labels in mips16 mode. This permits the linker
1186 to handle them specially, such as generating jalx instructions
1187 when needed. We also make them odd for the duration of the
1188 assembly, in order to generate the right sort of code. We will
1189 make them even in the adjust_symtab routine, while leaving them
1190 marked. This is convenient for the debugger and the
1191 disassembler. The linker knows to make them odd again. */
1194 struct insn_label_list
*l
;
1196 for (l
= insn_labels
; l
!= NULL
; l
= l
->next
)
1199 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
1200 S_SET_OTHER (l
->label
, STO_MIPS16
);
1202 ++l
->label
->sy_value
.X_add_number
;
1206 prev_pinfo
= prev_insn
.insn_mo
->pinfo
;
1207 pinfo
= ip
->insn_mo
->pinfo
;
1209 if (place
== NULL
&& ! mips_noreorder
)
1211 /* If the previous insn required any delay slots, see if we need
1212 to insert a NOP or two. There are eight kinds of possible
1213 hazards, of which an instruction can have at most one type.
1214 (1) a load from memory delay
1215 (2) a load from a coprocessor delay
1216 (3) an unconditional branch delay
1217 (4) a conditional branch delay
1218 (5) a move to coprocessor register delay
1219 (6) a load coprocessor register from memory delay
1220 (7) a coprocessor condition code delay
1221 (8) a HI/LO special register delay
1223 There are a lot of optimizations we could do that we don't.
1224 In particular, we do not, in general, reorder instructions.
1225 If you use gcc with optimization, it will reorder
1226 instructions and generally do much more optimization then we
1227 do here; repeating all that work in the assembler would only
1228 benefit hand written assembly code, and does not seem worth
1231 /* This is how a NOP is emitted. */
1232 #define emit_nop() \
1234 ? md_number_to_chars (frag_more (2), 0x6500, 2) \
1235 : md_number_to_chars (frag_more (4), 0, 4))
1237 /* The previous insn might require a delay slot, depending upon
1238 the contents of the current insn. */
1241 && (((prev_pinfo
& INSN_LOAD_COPROC_DELAY
)
1242 && ! cop_interlocks
)
1244 && (prev_pinfo
& INSN_LOAD_MEMORY_DELAY
))))
1246 /* A load from a coprocessor or from memory. All load
1247 delays delay the use of general register rt for one
1248 instruction on the r3000. The r6000 and r4000 use
1250 know (prev_pinfo
& INSN_WRITE_GPR_T
);
1251 if (mips_optimize
== 0
1252 || insn_uses_reg (ip
,
1253 ((prev_insn
.insn_opcode
>> OP_SH_RT
)
1260 && (((prev_pinfo
& INSN_COPROC_MOVE_DELAY
)
1261 && ! cop_interlocks
)
1263 && (prev_pinfo
& INSN_COPROC_MEMORY_DELAY
))))
1265 /* A generic coprocessor delay. The previous instruction
1266 modified a coprocessor general or control register. If
1267 it modified a control register, we need to avoid any
1268 coprocessor instruction (this is probably not always
1269 required, but it sometimes is). If it modified a general
1270 register, we avoid using that register.
1272 On the r6000 and r4000 loading a coprocessor register
1273 from memory is interlocked, and does not require a delay.
1275 This case is not handled very well. There is no special
1276 knowledge of CP0 handling, and the coprocessors other
1277 than the floating point unit are not distinguished at
1279 if (prev_pinfo
& INSN_WRITE_FPR_T
)
1281 if (mips_optimize
== 0
1282 || insn_uses_reg (ip
,
1283 ((prev_insn
.insn_opcode
>> OP_SH_FT
)
1288 else if (prev_pinfo
& INSN_WRITE_FPR_S
)
1290 if (mips_optimize
== 0
1291 || insn_uses_reg (ip
,
1292 ((prev_insn
.insn_opcode
>> OP_SH_FS
)
1299 /* We don't know exactly what the previous instruction
1300 does. If the current instruction uses a coprocessor
1301 register, we must insert a NOP. If previous
1302 instruction may set the condition codes, and the
1303 current instruction uses them, we must insert two
1305 if (mips_optimize
== 0
1306 || ((prev_pinfo
& INSN_WRITE_COND_CODE
)
1307 && (pinfo
& INSN_READ_COND_CODE
)))
1309 else if (pinfo
& INSN_COP
)
1315 && (prev_pinfo
& INSN_WRITE_COND_CODE
)
1316 && ! cop_interlocks
)
1318 /* The previous instruction sets the coprocessor condition
1319 codes, but does not require a general coprocessor delay
1320 (this means it is a floating point comparison
1321 instruction). If this instruction uses the condition
1322 codes, we need to insert a single NOP. */
1323 if (mips_optimize
== 0
1324 || (pinfo
& INSN_READ_COND_CODE
))
1327 else if (prev_pinfo
& INSN_READ_LO
)
1329 /* The previous instruction reads the LO register; if the
1330 current instruction writes to the LO register, we must
1331 insert two NOPS. Some newer processors have interlocks. */
1333 && (mips_optimize
== 0
1334 || (pinfo
& INSN_WRITE_LO
)))
1337 else if (prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
1339 /* The previous instruction reads the HI register; if the
1340 current instruction writes to the HI register, we must
1341 insert a NOP. Some newer processors have interlocks. */
1343 && (mips_optimize
== 0
1344 || (pinfo
& INSN_WRITE_HI
)))
1348 /* There are two cases which require two intervening
1349 instructions: 1) setting the condition codes using a move to
1350 coprocessor instruction which requires a general coprocessor
1351 delay and then reading the condition codes 2) reading the HI
1352 or LO register and then writing to it (except on processors
1353 which have interlocks). If we are not already emitting a NOP
1354 instruction, we must check for these cases compared to the
1355 instruction previous to the previous instruction. */
1359 && (prev_prev_insn
.insn_mo
->pinfo
& INSN_COPROC_MOVE_DELAY
)
1360 && (prev_prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
)
1361 && (pinfo
& INSN_READ_COND_CODE
)
1362 && ! cop_interlocks
)
1363 || ((prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
)
1364 && (pinfo
& INSN_WRITE_LO
)
1366 || ((prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
1367 && (pinfo
& INSN_WRITE_HI
)
1371 /* If we are being given a nop instruction, don't bother with
1372 one of the nops we would otherwise output. This will only
1373 happen when a nop instruction is used with mips_optimize set
1375 if (nops
> 0 && ip
->insn_opcode
== (mips16
? 0x6500 : 0))
1378 /* Now emit the right number of NOP instructions. */
1382 unsigned long old_frag_offset
;
1384 struct insn_label_list
*l
;
1386 old_frag
= frag_now
;
1387 old_frag_offset
= frag_now_fix ();
1389 for (i
= 0; i
< nops
; i
++)
1394 listing_prev_line ();
1395 /* We may be at the start of a variant frag. In case we
1396 are, make sure there is enough space for the frag
1397 after the frags created by listing_prev_line. The
1398 argument to frag_grow here must be at least as large
1399 as the argument to all other calls to frag_grow in
1400 this file. We don't have to worry about being in the
1401 middle of a variant frag, because the variants insert
1402 all needed nop instructions themselves. */
1406 for (l
= insn_labels
; l
!= NULL
; l
= l
->next
)
1408 assert (S_GET_SEGMENT (l
->label
) == now_seg
);
1409 l
->label
->sy_frag
= frag_now
;
1410 S_SET_VALUE (l
->label
, (valueT
) frag_now_fix ());
1411 /* mips16 text labels are stored as odd. */
1413 ++l
->label
->sy_value
.X_add_number
;
1416 #ifndef NO_ECOFF_DEBUGGING
1417 if (ECOFF_DEBUGGING
)
1418 ecoff_fix_loc (old_frag
, old_frag_offset
);
1423 if (reloc_type
> BFD_RELOC_UNUSED
)
1425 /* We need to set up a variant frag. */
1426 assert (mips16
&& address_expr
!= NULL
);
1427 f
= frag_var (rs_machine_dependent
, 4, 0,
1428 RELAX_MIPS16_ENCODE (reloc_type
- BFD_RELOC_UNUSED
,
1429 mips16_small
, mips16_ext
,
1431 & INSN_UNCOND_BRANCH_DELAY
),
1432 (prev_insn_reloc_type
1433 == BFD_RELOC_MIPS16_JMP
)),
1434 make_expr_symbol (address_expr
), (long) 0,
1437 else if (place
!= NULL
)
1439 else if (mips16
&& ! ip
->use_extend
&& reloc_type
!= BFD_RELOC_MIPS16_JMP
)
1441 /* Make sure there is enough room to swap this instruction with
1442 a following jump instruction. */
1449 if (address_expr
!= NULL
&& reloc_type
< BFD_RELOC_UNUSED
)
1451 if (address_expr
->X_op
== O_constant
)
1456 ip
->insn_opcode
|= address_expr
->X_add_number
;
1459 case BFD_RELOC_LO16
:
1460 ip
->insn_opcode
|= address_expr
->X_add_number
& 0xffff;
1463 case BFD_RELOC_MIPS_JMP
:
1464 if ((address_expr
->X_add_number
& 3) != 0)
1465 as_bad ("jump to misaligned address (0x%lx)",
1466 (unsigned long) address_expr
->X_add_number
);
1467 ip
->insn_opcode
|= (address_expr
->X_add_number
>> 2) & 0x3ffffff;
1470 case BFD_RELOC_MIPS16_JMP
:
1471 if ((address_expr
->X_add_number
& 3) != 0)
1472 as_bad ("jump to misaligned address (0x%lx)",
1473 (unsigned long) address_expr
->X_add_number
);
1475 (((address_expr
->X_add_number
& 0x7c0000) << 3)
1476 | ((address_expr
->X_add_number
& 0xf800000) >> 7)
1477 | ((address_expr
->X_add_number
& 0x3fffc) >> 2));
1480 case BFD_RELOC_16_PCREL_S2
:
1490 /* Don't generate a reloc if we are writing into a variant
1494 fixp
= fix_new_exp (frag_now
, f
- frag_now
->fr_literal
, 4,
1496 reloc_type
== BFD_RELOC_16_PCREL_S2
,
1500 struct mips_hi_fixup
*hi_fixup
;
1502 assert (reloc_type
== BFD_RELOC_HI16_S
);
1503 hi_fixup
= ((struct mips_hi_fixup
*)
1504 xmalloc (sizeof (struct mips_hi_fixup
)));
1505 hi_fixup
->fixp
= fixp
;
1506 hi_fixup
->seg
= now_seg
;
1507 hi_fixup
->next
= mips_hi_fixup_list
;
1508 mips_hi_fixup_list
= hi_fixup
;
1514 if (! mips16
|| reloc_type
== BFD_RELOC_MIPS16_JMP
)
1515 md_number_to_chars (f
, ip
->insn_opcode
, 4);
1520 md_number_to_chars (f
, 0xf000 | ip
->extend
, 2);
1523 md_number_to_chars (f
, ip
->insn_opcode
, 2);
1526 /* Update the register mask information. */
1529 if (pinfo
& INSN_WRITE_GPR_D
)
1530 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
);
1531 if ((pinfo
& (INSN_WRITE_GPR_T
| INSN_READ_GPR_T
)) != 0)
1532 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
);
1533 if (pinfo
& INSN_READ_GPR_S
)
1534 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> OP_SH_RS
) & OP_MASK_RS
);
1535 if (pinfo
& INSN_WRITE_GPR_31
)
1536 mips_gprmask
|= 1 << 31;
1537 if (pinfo
& INSN_WRITE_FPR_D
)
1538 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FD
) & OP_MASK_FD
);
1539 if ((pinfo
& (INSN_WRITE_FPR_S
| INSN_READ_FPR_S
)) != 0)
1540 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FS
) & OP_MASK_FS
);
1541 if ((pinfo
& (INSN_WRITE_FPR_T
| INSN_READ_FPR_T
)) != 0)
1542 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FT
) & OP_MASK_FT
);
1543 if ((pinfo
& INSN_READ_FPR_R
) != 0)
1544 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FR
) & OP_MASK_FR
);
1545 if (pinfo
& INSN_COP
)
1547 /* We don't keep enough information to sort these cases out. */
1549 /* Never set the bit for $0, which is always zero. */
1550 mips_gprmask
&=~ 1 << 0;
1554 if (pinfo
& (MIPS16_INSN_WRITE_X
| MIPS16_INSN_READ_X
))
1555 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_RX
)
1556 & MIPS16OP_MASK_RX
);
1557 if (pinfo
& (MIPS16_INSN_WRITE_Y
| MIPS16_INSN_READ_Y
))
1558 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_RY
)
1559 & MIPS16OP_MASK_RY
);
1560 if (pinfo
& MIPS16_INSN_WRITE_Z
)
1561 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_RZ
)
1562 & MIPS16OP_MASK_RZ
);
1563 if (pinfo
& (MIPS16_INSN_WRITE_T
| MIPS16_INSN_READ_T
))
1564 mips_gprmask
|= 1 << TREG
;
1565 if (pinfo
& (MIPS16_INSN_WRITE_SP
| MIPS16_INSN_READ_SP
))
1566 mips_gprmask
|= 1 << SP
;
1567 if (pinfo
& (MIPS16_INSN_WRITE_31
| MIPS16_INSN_READ_31
))
1568 mips_gprmask
|= 1 << RA
;
1569 if (pinfo
& MIPS16_INSN_WRITE_GPR_Y
)
1570 mips_gprmask
|= 1 << MIPS16OP_EXTRACT_REG32R (ip
->insn_opcode
);
1571 if (pinfo
& MIPS16_INSN_READ_Z
)
1572 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_MOVE32Z
)
1573 & MIPS16OP_MASK_MOVE32Z
);
1574 if (pinfo
& MIPS16_INSN_READ_GPR_X
)
1575 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_REGR32
)
1576 & MIPS16OP_MASK_REGR32
);
1579 if (place
== NULL
&& ! mips_noreorder
)
1581 /* Filling the branch delay slot is more complex. We try to
1582 switch the branch with the previous instruction, which we can
1583 do if the previous instruction does not set up a condition
1584 that the branch tests and if the branch is not itself the
1585 target of any branch. */
1586 if ((pinfo
& INSN_UNCOND_BRANCH_DELAY
)
1587 || (pinfo
& INSN_COND_BRANCH_DELAY
))
1589 if (mips_optimize
< 2
1590 /* If we have seen .set volatile or .set nomove, don't
1593 /* If we had to emit any NOP instructions, then we
1594 already know we can not swap. */
1596 /* If we don't even know the previous insn, we can not
1598 || ! prev_insn_valid
1599 /* If the previous insn is already in a branch delay
1600 slot, then we can not swap. */
1601 || prev_insn_is_delay_slot
1602 /* If the previous previous insn was in a .set
1603 noreorder, we can't swap. Actually, the MIPS
1604 assembler will swap in this situation. However, gcc
1605 configured -with-gnu-as will generate code like
1611 in which we can not swap the bne and INSN. If gcc is
1612 not configured -with-gnu-as, it does not output the
1613 .set pseudo-ops. We don't have to check
1614 prev_insn_unreordered, because prev_insn_valid will
1615 be 0 in that case. We don't want to use
1616 prev_prev_insn_valid, because we do want to be able
1617 to swap at the start of a function. */
1618 || prev_prev_insn_unreordered
1619 /* If the branch is itself the target of a branch, we
1620 can not swap. We cheat on this; all we check for is
1621 whether there is a label on this instruction. If
1622 there are any branches to anything other than a
1623 label, users must use .set noreorder. */
1624 || insn_labels
!= NULL
1625 /* If the previous instruction is in a variant frag, we
1626 can not do the swap. This does not apply to the
1627 mips16, which uses variant frags for different
1630 && prev_insn_frag
->fr_type
== rs_machine_dependent
)
1631 /* If the branch reads the condition codes, we don't
1632 even try to swap, because in the sequence
1637 we can not swap, and I don't feel like handling that
1641 && (pinfo
& INSN_READ_COND_CODE
))
1642 /* We can not swap with an instruction that requires a
1643 delay slot, becase the target of the branch might
1644 interfere with that instruction. */
1648 & (INSN_LOAD_COPROC_DELAY
1649 | INSN_COPROC_MOVE_DELAY
1650 | INSN_WRITE_COND_CODE
)))
1658 & (INSN_LOAD_MEMORY_DELAY
1659 | INSN_COPROC_MEMORY_DELAY
)))
1660 /* We can not swap with a branch instruction. */
1662 & (INSN_UNCOND_BRANCH_DELAY
1663 | INSN_COND_BRANCH_DELAY
1664 | INSN_COND_BRANCH_LIKELY
))
1665 /* We do not swap with a trap instruction, since it
1666 complicates trap handlers to have the trap
1667 instruction be in a delay slot. */
1668 || (prev_pinfo
& INSN_TRAP
)
1669 /* If the branch reads a register that the previous
1670 instruction sets, we can not swap. */
1672 && (prev_pinfo
& INSN_WRITE_GPR_T
)
1673 && insn_uses_reg (ip
,
1674 ((prev_insn
.insn_opcode
>> OP_SH_RT
)
1678 && (prev_pinfo
& INSN_WRITE_GPR_D
)
1679 && insn_uses_reg (ip
,
1680 ((prev_insn
.insn_opcode
>> OP_SH_RD
)
1684 && (((prev_pinfo
& MIPS16_INSN_WRITE_X
)
1685 && insn_uses_reg (ip
,
1686 ((prev_insn
.insn_opcode
1688 & MIPS16OP_MASK_RX
),
1690 || ((prev_pinfo
& MIPS16_INSN_WRITE_Y
)
1691 && insn_uses_reg (ip
,
1692 ((prev_insn
.insn_opcode
1694 & MIPS16OP_MASK_RY
),
1696 || ((prev_pinfo
& MIPS16_INSN_WRITE_Z
)
1697 && insn_uses_reg (ip
,
1698 ((prev_insn
.insn_opcode
1700 & MIPS16OP_MASK_RZ
),
1702 || ((prev_pinfo
& MIPS16_INSN_WRITE_T
)
1703 && insn_uses_reg (ip
, TREG
, MIPS_GR_REG
))
1704 || ((prev_pinfo
& MIPS16_INSN_WRITE_31
)
1705 && insn_uses_reg (ip
, RA
, MIPS_GR_REG
))
1706 || ((prev_pinfo
& MIPS16_INSN_WRITE_GPR_Y
)
1707 && insn_uses_reg (ip
,
1708 MIPS16OP_EXTRACT_REG32R (prev_insn
.
1711 /* If the branch writes a register that the previous
1712 instruction sets, we can not swap (we know that
1713 branches write only to RD or to $31). */
1715 && (prev_pinfo
& INSN_WRITE_GPR_T
)
1716 && (((pinfo
& INSN_WRITE_GPR_D
)
1717 && (((prev_insn
.insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
)
1718 == ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)))
1719 || ((pinfo
& INSN_WRITE_GPR_31
)
1720 && (((prev_insn
.insn_opcode
>> OP_SH_RT
)
1724 && (prev_pinfo
& INSN_WRITE_GPR_D
)
1725 && (((pinfo
& INSN_WRITE_GPR_D
)
1726 && (((prev_insn
.insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)
1727 == ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)))
1728 || ((pinfo
& INSN_WRITE_GPR_31
)
1729 && (((prev_insn
.insn_opcode
>> OP_SH_RD
)
1733 && (pinfo
& MIPS16_INSN_WRITE_31
)
1734 && ((prev_pinfo
& MIPS16_INSN_WRITE_31
)
1735 || ((prev_pinfo
& MIPS16_INSN_WRITE_GPR_Y
)
1736 && (MIPS16OP_EXTRACT_REG32R (prev_insn
.insn_opcode
)
1738 /* If the branch writes a register that the previous
1739 instruction reads, we can not swap (we know that
1740 branches only write to RD or to $31). */
1742 && (pinfo
& INSN_WRITE_GPR_D
)
1743 && insn_uses_reg (&prev_insn
,
1744 ((ip
->insn_opcode
>> OP_SH_RD
)
1748 && (pinfo
& INSN_WRITE_GPR_31
)
1749 && insn_uses_reg (&prev_insn
, 31, MIPS_GR_REG
))
1751 && (pinfo
& MIPS16_INSN_WRITE_31
)
1752 && insn_uses_reg (&prev_insn
, RA
, MIPS_GR_REG
))
1753 /* If we are generating embedded PIC code, the branch
1754 might be expanded into a sequence which uses $at, so
1755 we can't swap with an instruction which reads it. */
1756 || (mips_pic
== EMBEDDED_PIC
1757 && insn_uses_reg (&prev_insn
, AT
, MIPS_GR_REG
))
1758 /* If the previous previous instruction has a load
1759 delay, and sets a register that the branch reads, we
1763 && ((prev_prev_insn
.insn_mo
->pinfo
& INSN_LOAD_COPROC_DELAY
)
1765 && (prev_prev_insn
.insn_mo
->pinfo
1766 & INSN_LOAD_MEMORY_DELAY
)))
1767 && insn_uses_reg (ip
,
1768 ((prev_prev_insn
.insn_opcode
>> OP_SH_RT
)
1771 /* If one instruction sets a condition code and the
1772 other one uses a condition code, we can not swap. */
1773 || ((pinfo
& INSN_READ_COND_CODE
)
1774 && (prev_pinfo
& INSN_WRITE_COND_CODE
))
1775 || ((pinfo
& INSN_WRITE_COND_CODE
)
1776 && (prev_pinfo
& INSN_READ_COND_CODE
))
1777 /* If the previous instruction uses the PC, we can not
1780 && (prev_pinfo
& MIPS16_INSN_READ_PC
))
1781 /* If the previous instruction was extended, we can not
1783 || (mips16
&& prev_insn_extended
)
1784 /* If the previous instruction had a fixup in mips16
1785 mode, we can not swap. This normally means that the
1786 previous instruction was a 4 byte branch anyhow. */
1787 || (mips16
&& prev_insn_fixp
))
1789 /* We could do even better for unconditional branches to
1790 portions of this object file; we could pick up the
1791 instruction at the destination, put it in the delay
1792 slot, and bump the destination address. */
1794 /* Update the previous insn information. */
1795 prev_prev_insn
= *ip
;
1796 prev_insn
.insn_mo
= &dummy_opcode
;
1800 /* It looks like we can actually do the swap. */
1806 prev_f
= prev_insn_frag
->fr_literal
+ prev_insn_where
;
1807 memcpy (temp
, prev_f
, 4);
1808 memcpy (prev_f
, f
, 4);
1809 memcpy (f
, temp
, 4);
1812 prev_insn_fixp
->fx_frag
= frag_now
;
1813 prev_insn_fixp
->fx_where
= f
- frag_now
->fr_literal
;
1817 fixp
->fx_frag
= prev_insn_frag
;
1818 fixp
->fx_where
= prev_insn_where
;
1821 else if (reloc_type
> BFD_RELOC_UNUSED
)
1826 /* We are in mips16 mode, and we have just created a
1827 variant frag. We need to extract the old
1828 instruction from the end of the previous frag,
1829 and add it to a new frag. */
1830 prev_f
= prev_insn_frag
->fr_literal
+ prev_insn_where
;
1831 memcpy (temp
, prev_f
, 2);
1832 prev_insn_frag
->fr_fix
-= 2;
1833 if (prev_insn_frag
->fr_type
== rs_machine_dependent
)
1835 assert (prev_insn_where
== prev_insn_frag
->fr_fix
);
1836 memcpy (prev_f
, prev_f
+ 2, 2);
1838 memcpy (frag_more (2), temp
, 2);
1845 assert (prev_insn_fixp
== NULL
);
1846 prev_f
= prev_insn_frag
->fr_literal
+ prev_insn_where
;
1847 memcpy (temp
, prev_f
, 2);
1848 memcpy (prev_f
, f
, 2);
1849 if (reloc_type
!= BFD_RELOC_MIPS16_JMP
)
1850 memcpy (f
, temp
, 2);
1853 memcpy (f
, f
+ 2, 2);
1854 memcpy (f
+ 2, temp
, 2);
1858 fixp
->fx_frag
= prev_insn_frag
;
1859 fixp
->fx_where
= prev_insn_where
;
1863 /* Update the previous insn information; leave prev_insn
1865 prev_prev_insn
= *ip
;
1867 prev_insn_is_delay_slot
= 1;
1869 /* If that was an unconditional branch, forget the previous
1870 insn information. */
1871 if (pinfo
& INSN_UNCOND_BRANCH_DELAY
)
1873 prev_prev_insn
.insn_mo
= &dummy_opcode
;
1874 prev_insn
.insn_mo
= &dummy_opcode
;
1877 prev_insn_fixp
= NULL
;
1878 prev_insn_reloc_type
= BFD_RELOC_UNUSED
;
1879 prev_insn_extended
= 0;
1881 else if (pinfo
& INSN_COND_BRANCH_LIKELY
)
1883 /* We don't yet optimize a branch likely. What we should do
1884 is look at the target, copy the instruction found there
1885 into the delay slot, and increment the branch to jump to
1886 the next instruction. */
1888 /* Update the previous insn information. */
1889 prev_prev_insn
= *ip
;
1890 prev_insn
.insn_mo
= &dummy_opcode
;
1891 prev_insn_fixp
= NULL
;
1892 prev_insn_reloc_type
= BFD_RELOC_UNUSED
;
1893 prev_insn_extended
= 0;
1897 /* Update the previous insn information. */
1899 prev_prev_insn
.insn_mo
= &dummy_opcode
;
1901 prev_prev_insn
= prev_insn
;
1904 /* Any time we see a branch, we always fill the delay slot
1905 immediately; since this insn is not a branch, we know it
1906 is not in a delay slot. */
1907 prev_insn_is_delay_slot
= 0;
1909 prev_insn_fixp
= fixp
;
1910 prev_insn_reloc_type
= reloc_type
;
1912 prev_insn_extended
= (ip
->use_extend
1913 || reloc_type
> BFD_RELOC_UNUSED
);
1916 prev_prev_insn_unreordered
= prev_insn_unreordered
;
1917 prev_insn_unreordered
= 0;
1918 prev_insn_frag
= frag_now
;
1919 prev_insn_where
= f
- frag_now
->fr_literal
;
1920 prev_insn_valid
= 1;
1922 else if (place
== NULL
)
1924 /* We need to record a bit of information even when we are not
1925 reordering, in order to determine the base address for mips16
1926 PC relative relocs. */
1928 prev_insn_reloc_type
= reloc_type
;
1931 /* We just output an insn, so the next one doesn't have a label. */
1932 mips_clear_insn_labels ();
1935 /* This function forgets that there was any previous instruction or
1939 mips_no_prev_insn ()
1941 prev_insn
.insn_mo
= &dummy_opcode
;
1942 prev_prev_insn
.insn_mo
= &dummy_opcode
;
1943 prev_insn_valid
= 0;
1944 prev_insn_is_delay_slot
= 0;
1945 prev_insn_unreordered
= 0;
1946 prev_insn_extended
= 0;
1947 prev_insn_reloc_type
= BFD_RELOC_UNUSED
;
1948 prev_prev_insn_unreordered
= 0;
1949 mips_clear_insn_labels ();
1952 /* This function must be called whenever we turn on noreorder or emit
1953 something other than instructions. It inserts any NOPS which might
1954 be needed by the previous instruction, and clears the information
1955 kept for the previous instructions. The INSNS parameter is true if
1956 instructions are to follow. */
1959 mips_emit_delays (insns
)
1962 if (! mips_noreorder
)
1969 && (! cop_interlocks
1970 && (prev_insn
.insn_mo
->pinfo
1971 & (INSN_LOAD_COPROC_DELAY
1972 | INSN_COPROC_MOVE_DELAY
1973 | INSN_WRITE_COND_CODE
))))
1975 && (prev_insn
.insn_mo
->pinfo
1980 && (prev_insn
.insn_mo
->pinfo
1981 & (INSN_LOAD_MEMORY_DELAY
1982 | INSN_COPROC_MEMORY_DELAY
))))
1987 && (! cop_interlocks
1988 && prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
))
1990 && ((prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
1991 || (prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
))))
1996 && (! cop_interlocks
1997 && prev_prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
))
1999 && ((prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
2000 || (prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
))))
2004 struct insn_label_list
*l
;
2007 for (l
= insn_labels
; l
!= NULL
; l
= l
->next
)
2009 assert (S_GET_SEGMENT (l
->label
) == now_seg
);
2010 l
->label
->sy_frag
= frag_now
;
2011 S_SET_VALUE (l
->label
, (valueT
) frag_now_fix ());
2012 /* mips16 text labels are stored as odd. */
2014 ++l
->label
->sy_value
.X_add_number
;
2019 /* Mark instruction labels in mips16 mode. This permits the linker
2020 to handle them specially, such as generating jalx instructions
2021 when needed. We also make them odd for the duration of the
2022 assembly, in order to generate the right sort of code. We will
2023 make them even in the adjust_symtab routine, while leaving them
2024 marked. This is convenient for the debugger and the
2025 disassembler. The linker knows to make them odd again. */
2026 if (mips16
&& insns
)
2028 struct insn_label_list
*l
;
2030 for (l
= insn_labels
; l
!= NULL
; l
= l
->next
)
2033 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
2034 S_SET_OTHER (l
->label
, STO_MIPS16
);
2036 if ((l
->label
->sy_value
.X_add_number
& 1) == 0)
2037 ++l
->label
->sy_value
.X_add_number
;
2041 mips_no_prev_insn ();
2044 /* Build an instruction created by a macro expansion. This is passed
2045 a pointer to the count of instructions created so far, an
2046 expression, the name of the instruction to build, an operand format
2047 string, and corresponding arguments. */
2051 macro_build (char *place
,
2059 macro_build (place
, counter
, ep
, name
, fmt
, va_alist
)
2068 struct mips_cl_insn insn
;
2069 bfd_reloc_code_real_type r
;
2073 va_start (args
, fmt
);
2079 * If the macro is about to expand into a second instruction,
2080 * print a warning if needed. We need to pass ip as a parameter
2081 * to generate a better warning message here...
2083 if (mips_warn_about_macros
&& place
== NULL
&& *counter
== 1)
2084 as_warn ("Macro instruction expanded into multiple instructions");
2087 *counter
+= 1; /* bump instruction counter */
2091 mips16_macro_build (place
, counter
, ep
, name
, fmt
, args
);
2096 r
= BFD_RELOC_UNUSED
;
2097 insn
.insn_mo
= (struct mips_opcode
*) hash_find (op_hash
, name
);
2098 assert (insn
.insn_mo
);
2099 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
2101 while (strcmp (fmt
, insn
.insn_mo
->args
) != 0
2102 || insn
.insn_mo
->pinfo
== INSN_MACRO
2103 || ((insn
.insn_mo
->pinfo
& INSN_ISA
) == INSN_ISA2
2105 || ((insn
.insn_mo
->pinfo
& INSN_ISA
) == INSN_ISA3
2107 || ((insn
.insn_mo
->pinfo
& INSN_ISA
) == INSN_ISA4
2109 || ((insn
.insn_mo
->pinfo
& INSN_ISA
) == INSN_4650
2111 || ((insn
.insn_mo
->pinfo
& INSN_ISA
) == INSN_4010
2113 || ((insn
.insn_mo
->pinfo
& INSN_ISA
) == INSN_4100
2117 assert (insn
.insn_mo
->name
);
2118 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
2120 insn
.insn_opcode
= insn
.insn_mo
->match
;
2136 insn
.insn_opcode
|= va_arg (args
, int) << 16;
2142 insn
.insn_opcode
|= va_arg (args
, int) << 16;
2147 insn
.insn_opcode
|= va_arg (args
, int) << 11;
2152 insn
.insn_opcode
|= va_arg (args
, int) << 11;
2159 insn
.insn_opcode
|= va_arg (args
, int) << 6;
2163 insn
.insn_opcode
|= va_arg (args
, int) << 6;
2167 insn
.insn_opcode
|= va_arg (args
, int) << 6;
2174 insn
.insn_opcode
|= va_arg (args
, int) << 21;
2180 r
= (bfd_reloc_code_real_type
) va_arg (args
, int);
2181 assert (r
== BFD_RELOC_MIPS_GPREL
2182 || r
== BFD_RELOC_MIPS_LITERAL
2183 || r
== BFD_RELOC_LO16
2184 || r
== BFD_RELOC_MIPS_GOT16
2185 || r
== BFD_RELOC_MIPS_CALL16
2186 || r
== BFD_RELOC_MIPS_GOT_LO16
2187 || r
== BFD_RELOC_MIPS_CALL_LO16
2188 || (ep
->X_op
== O_subtract
2189 && now_seg
== text_section
2190 && r
== BFD_RELOC_PCREL_LO16
));
2194 r
= (bfd_reloc_code_real_type
) va_arg (args
, int);
2196 && (ep
->X_op
== O_constant
2197 || (ep
->X_op
== O_symbol
2198 && (r
== BFD_RELOC_HI16_S
2199 || r
== BFD_RELOC_HI16
2200 || r
== BFD_RELOC_MIPS_GOT_HI16
2201 || r
== BFD_RELOC_MIPS_CALL_HI16
))
2202 || (ep
->X_op
== O_subtract
2203 && now_seg
== text_section
2204 && r
== BFD_RELOC_PCREL_HI16_S
)));
2205 if (ep
->X_op
== O_constant
)
2207 insn
.insn_opcode
|= (ep
->X_add_number
>> 16) & 0xffff;
2209 r
= BFD_RELOC_UNUSED
;
2214 assert (ep
!= NULL
);
2216 * This allows macro() to pass an immediate expression for
2217 * creating short branches without creating a symbol.
2218 * Note that the expression still might come from the assembly
2219 * input, in which case the value is not checked for range nor
2220 * is a relocation entry generated (yuck).
2222 if (ep
->X_op
== O_constant
)
2224 insn
.insn_opcode
|= (ep
->X_add_number
>> 2) & 0xffff;
2228 r
= BFD_RELOC_16_PCREL_S2
;
2232 assert (ep
!= NULL
);
2233 r
= BFD_RELOC_MIPS_JMP
;
2242 assert (r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
2244 append_insn (place
, &insn
, ep
, r
, false);
2248 mips16_macro_build (place
, counter
, ep
, name
, fmt
, args
)
2256 struct mips_cl_insn insn
;
2257 bfd_reloc_code_real_type r
;
2259 r
= BFD_RELOC_UNUSED
;
2260 insn
.insn_mo
= (struct mips_opcode
*) hash_find (mips16_op_hash
, name
);
2261 assert (insn
.insn_mo
);
2262 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
2264 while (strcmp (fmt
, insn
.insn_mo
->args
) != 0
2265 || insn
.insn_mo
->pinfo
== INSN_MACRO
)
2268 assert (insn
.insn_mo
->name
);
2269 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
2272 insn
.insn_opcode
= insn
.insn_mo
->match
;
2273 insn
.use_extend
= false;
2292 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_RY
;
2297 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_RX
;
2301 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_RZ
;
2305 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_MOVE32Z
;
2315 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_REGR32
;
2322 regno
= va_arg (args
, int);
2323 regno
= ((regno
& 7) << 2) | ((regno
& 0x18) >> 3);
2324 insn
.insn_opcode
|= regno
<< MIPS16OP_SH_REG32R
;
2345 assert (ep
!= NULL
);
2347 if (ep
->X_op
!= O_constant
)
2348 r
= BFD_RELOC_UNUSED
+ c
;
2351 mips16_immed ((char *) NULL
, 0, c
, ep
->X_add_number
, false,
2352 false, false, &insn
.insn_opcode
,
2353 &insn
.use_extend
, &insn
.extend
);
2355 r
= BFD_RELOC_UNUSED
;
2361 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_IMM6
;
2368 assert (r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
2370 append_insn (place
, &insn
, ep
, r
, false);
2374 * Generate a "lui" instruction.
2377 macro_build_lui (place
, counter
, ep
, regnum
)
2383 expressionS high_expr
;
2384 struct mips_cl_insn insn
;
2385 bfd_reloc_code_real_type r
;
2386 CONST
char *name
= "lui";
2387 CONST
char *fmt
= "t,u";
2395 high_expr
.X_op
= O_constant
;
2396 high_expr
.X_add_number
= ep
->X_add_number
;
2399 if (high_expr
.X_op
== O_constant
)
2401 /* we can compute the instruction now without a relocation entry */
2402 if (high_expr
.X_add_number
& 0x8000)
2403 high_expr
.X_add_number
+= 0x10000;
2404 high_expr
.X_add_number
=
2405 ((unsigned long) high_expr
.X_add_number
>> 16) & 0xffff;
2406 r
= BFD_RELOC_UNUSED
;
2410 assert (ep
->X_op
== O_symbol
);
2411 /* _gp_disp is a special case, used from s_cpload. */
2412 assert (mips_pic
== NO_PIC
2413 || strcmp (S_GET_NAME (ep
->X_add_symbol
), "_gp_disp") == 0);
2414 r
= BFD_RELOC_HI16_S
;
2418 * If the macro is about to expand into a second instruction,
2419 * print a warning if needed. We need to pass ip as a parameter
2420 * to generate a better warning message here...
2422 if (mips_warn_about_macros
&& place
== NULL
&& *counter
== 1)
2423 as_warn ("Macro instruction expanded into multiple instructions");
2426 *counter
+= 1; /* bump instruction counter */
2428 insn
.insn_mo
= (struct mips_opcode
*) hash_find (op_hash
, name
);
2429 assert (insn
.insn_mo
);
2430 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
2431 assert (strcmp (fmt
, insn
.insn_mo
->args
) == 0);
2433 insn
.insn_opcode
= insn
.insn_mo
->match
| (regnum
<< OP_SH_RT
);
2434 if (r
== BFD_RELOC_UNUSED
)
2436 insn
.insn_opcode
|= high_expr
.X_add_number
;
2437 append_insn (place
, &insn
, NULL
, r
, false);
2440 append_insn (place
, &insn
, &high_expr
, r
, false);
2444 * Generates code to set the $at register to true (one)
2445 * if reg is less than the immediate expression.
2448 set_at (counter
, reg
, unsignedp
)
2453 if (imm_expr
.X_add_number
>= -0x8000 && imm_expr
.X_add_number
< 0x8000)
2454 macro_build ((char *) NULL
, counter
, &imm_expr
,
2455 unsignedp
? "sltiu" : "slti",
2456 "t,r,j", AT
, reg
, (int) BFD_RELOC_LO16
);
2459 load_register (counter
, AT
, &imm_expr
, 0);
2460 macro_build ((char *) NULL
, counter
, NULL
,
2461 unsignedp
? "sltu" : "slt",
2462 "d,v,t", AT
, reg
, AT
);
2466 /* Warn if an expression is not a constant. */
2469 check_absolute_expr (ip
, ex
)
2470 struct mips_cl_insn
*ip
;
2473 if (ex
->X_op
!= O_constant
)
2474 as_warn ("Instruction %s requires absolute expression", ip
->insn_mo
->name
);
2477 /* Count the leading zeroes by performing a binary chop. This is a
2478 bulky bit of source, but performance is a LOT better for the
2479 majority of values than a simple loop to count the bits:
2480 for (lcnt = 0; (lcnt < 32); lcnt++)
2481 if ((v) & (1 << (31 - lcnt)))
2483 However it is not code size friendly, and the gain will drop a bit
2484 on certain cached systems.
2486 #define COUNT_TOP_ZEROES(v) \
2487 (((v) & ~0xffff) == 0 \
2488 ? ((v) & ~0xff) == 0 \
2489 ? ((v) & ~0xf) == 0 \
2490 ? ((v) & ~0x3) == 0 \
2491 ? ((v) & ~0x1) == 0 \
2496 : ((v) & ~0x7) == 0 \
2499 : ((v) & ~0x3f) == 0 \
2500 ? ((v) & ~0x1f) == 0 \
2503 : ((v) & ~0x7f) == 0 \
2506 : ((v) & ~0xfff) == 0 \
2507 ? ((v) & ~0x3ff) == 0 \
2508 ? ((v) & ~0x1ff) == 0 \
2511 : ((v) & ~0x7ff) == 0 \
2514 : ((v) & ~0x3fff) == 0 \
2515 ? ((v) & ~0x1fff) == 0 \
2518 : ((v) & ~0x7fff) == 0 \
2521 : ((v) & ~0xffffff) == 0 \
2522 ? ((v) & ~0xfffff) == 0 \
2523 ? ((v) & ~0x3ffff) == 0 \
2524 ? ((v) & ~0x1ffff) == 0 \
2527 : ((v) & ~0x7ffff) == 0 \
2530 : ((v) & ~0x3fffff) == 0 \
2531 ? ((v) & ~0x1fffff) == 0 \
2534 : ((v) & ~0x7fffff) == 0 \
2537 : ((v) & ~0xfffffff) == 0 \
2538 ? ((v) & ~0x3ffffff) == 0 \
2539 ? ((v) & ~0x1ffffff) == 0 \
2542 : ((v) & ~0x7ffffff) == 0 \
2545 : ((v) & ~0x3fffffff) == 0 \
2546 ? ((v) & ~0x1fffffff) == 0 \
2549 : ((v) & ~0x7fffffff) == 0 \
2554 * This routine generates the least number of instructions neccessary to load
2555 * an absolute expression value into a register.
2558 load_register (counter
, reg
, ep
, dbl
)
2565 expressionS hi32
, lo32
;
2567 if (ep
->X_op
!= O_big
)
2569 assert (ep
->X_op
== O_constant
);
2570 if (ep
->X_add_number
< 0x8000
2571 && (ep
->X_add_number
>= 0
2572 || (ep
->X_add_number
>= -0x8000
2575 || sizeof (ep
->X_add_number
) > 4))))
2577 /* We can handle 16 bit signed values with an addiu to
2578 $zero. No need to ever use daddiu here, since $zero and
2579 the result are always correct in 32 bit mode. */
2580 macro_build ((char *) NULL
, counter
, ep
, "addiu", "t,r,j", reg
, 0,
2581 (int) BFD_RELOC_LO16
);
2584 else if (ep
->X_add_number
>= 0 && ep
->X_add_number
< 0x10000)
2586 /* We can handle 16 bit unsigned values with an ori to
2588 macro_build ((char *) NULL
, counter
, ep
, "ori", "t,r,i", reg
, 0,
2589 (int) BFD_RELOC_LO16
);
2592 else if ((((ep
->X_add_number
&~ (offsetT
) 0x7fffffff) == 0
2593 || ((ep
->X_add_number
&~ (offsetT
) 0x7fffffff)
2594 == ~ (offsetT
) 0x7fffffff))
2597 || sizeof (ep
->X_add_number
) > 4
2598 || (ep
->X_add_number
& 0x80000000) == 0))
2599 || ((mips_isa
< 3 || !dbl
)
2600 && (ep
->X_add_number
&~ (offsetT
) 0xffffffff) == 0))
2602 /* 32 bit values require an lui. */
2603 macro_build ((char *) NULL
, counter
, ep
, "lui", "t,u", reg
,
2604 (int) BFD_RELOC_HI16
);
2605 if ((ep
->X_add_number
& 0xffff) != 0)
2606 macro_build ((char *) NULL
, counter
, ep
, "ori", "t,r,i", reg
, reg
,
2607 (int) BFD_RELOC_LO16
);
2612 /* The value is larger than 32 bits. */
2616 as_bad ("Number larger than 32 bits");
2617 macro_build ((char *) NULL
, counter
, ep
, "addiu", "t,r,j", reg
, 0,
2618 (int) BFD_RELOC_LO16
);
2622 if (ep
->X_op
!= O_big
)
2625 hi32
.X_add_number
= (valueT
) hi32
.X_add_number
>> 16;
2626 hi32
.X_add_number
= (valueT
) hi32
.X_add_number
>> 16;
2627 hi32
.X_add_number
&= 0xffffffff;
2629 lo32
.X_add_number
&= 0xffffffff;
2633 assert (ep
->X_add_number
> 2);
2634 if (ep
->X_add_number
== 3)
2635 generic_bignum
[3] = 0;
2636 else if (ep
->X_add_number
> 4)
2637 as_bad ("Number larger than 64 bits");
2638 lo32
.X_op
= O_constant
;
2639 lo32
.X_add_number
= generic_bignum
[0] + (generic_bignum
[1] << 16);
2640 hi32
.X_op
= O_constant
;
2641 hi32
.X_add_number
= generic_bignum
[2] + (generic_bignum
[3] << 16);
2644 if (hi32
.X_add_number
== 0)
2649 unsigned long hi
, lo
;
2651 if (hi32
.X_add_number
== 0xffffffff)
2653 if ((lo32
.X_add_number
& 0xffff8000) == 0xffff8000)
2655 macro_build ((char *) NULL
, counter
, &lo32
, "addiu", "t,r,j",
2656 reg
, 0, (int) BFD_RELOC_LO16
);
2659 if (lo32
.X_add_number
& 0x80000000)
2661 macro_build ((char *) NULL
, counter
, &lo32
, "lui", "t,u", reg
,
2662 (int) BFD_RELOC_HI16
);
2663 if (lo32
.X_add_number
& 0xffff)
2664 macro_build ((char *) NULL
, counter
, &lo32
, "ori", "t,r,i",
2665 reg
, reg
, (int) BFD_RELOC_LO16
);
2670 /* Check for 16bit shifted constant. We know that hi32 is
2671 non-zero, so start the mask on the first bit of the hi32
2676 unsigned long himask
, lomask
;
2680 himask
= 0xffff >> (32 - shift
);
2681 lomask
= (0xffff << shift
) & 0xffffffff;
2685 himask
= 0xffff << (shift
- 32);
2688 if ((hi32
.X_add_number
& ~ (offsetT
) himask
) == 0
2689 && (lo32
.X_add_number
& ~ (offsetT
) lomask
) == 0)
2693 tmp
.X_op
= O_constant
;
2695 tmp
.X_add_number
= ((hi32
.X_add_number
<< (32 - shift
))
2696 | (lo32
.X_add_number
>> shift
));
2698 tmp
.X_add_number
= hi32
.X_add_number
>> (shift
- 32);
2699 macro_build ((char *) NULL
, counter
, &tmp
, "ori", "t,r,i", reg
, 0,
2700 (int) BFD_RELOC_LO16
);
2701 macro_build ((char *) NULL
, counter
, NULL
,
2702 (shift
>= 32) ? "dsll32" : "dsll",
2704 (shift
>= 32) ? shift
- 32 : shift
);
2708 } while (shift
<= (64 - 16));
2710 /* Find the bit number of the lowest one bit, and store the
2711 shifted value in hi/lo. */
2712 hi
= (unsigned long) (hi32
.X_add_number
& 0xffffffff);
2713 lo
= (unsigned long) (lo32
.X_add_number
& 0xffffffff);
2717 while ((lo
& 1) == 0)
2722 lo
|= (hi
& (((unsigned long) 1 << bit
) - 1)) << (32 - bit
);
2728 while ((hi
& 1) == 0)
2737 /* Optimize if the shifted value is a (power of 2) - 1. */
2738 if ((hi
== 0 && ((lo
+ 1) & lo
) == 0)
2739 || (lo
== 0xffffffff && ((hi
+ 1) & hi
) == 0))
2741 shift
= COUNT_TOP_ZEROES ((unsigned int) hi32
.X_add_number
);
2746 /* This instruction will set the register to be all
2748 tmp
.X_op
= O_constant
;
2749 tmp
.X_add_number
= (offsetT
) -1;
2750 macro_build ((char *) NULL
, counter
, &tmp
, "addiu", "t,r,j",
2751 reg
, 0, (int) BFD_RELOC_LO16
);
2755 macro_build ((char *) NULL
, counter
, NULL
,
2756 (bit
>= 32) ? "dsll32" : "dsll",
2758 (bit
>= 32) ? bit
- 32 : bit
);
2760 macro_build ((char *) NULL
, counter
, NULL
,
2761 (shift
>= 32) ? "dsrl32" : "dsrl",
2763 (shift
>= 32) ? shift
- 32 : shift
);
2768 /* Sign extend hi32 before calling load_register, because we can
2769 generally get better code when we load a sign extended value. */
2770 if ((hi32
.X_add_number
& 0x80000000) != 0)
2771 hi32
.X_add_number
|= ~ (offsetT
) 0xffffffff;
2772 load_register (counter
, reg
, &hi32
, 0);
2775 if ((lo32
.X_add_number
& 0xffff0000) == 0)
2779 macro_build ((char *) NULL
, counter
, NULL
, "dsll32", "d,w,<", reg
,
2788 if ((freg
== 0) && (lo32
.X_add_number
== 0xffffffff))
2790 macro_build ((char *) NULL
, counter
, &lo32
, "lui", "t,u", reg
,
2791 (int) BFD_RELOC_HI16
);
2792 macro_build ((char *) NULL
, counter
, NULL
, "dsrl32", "d,w,<", reg
,
2799 macro_build ((char *) NULL
, counter
, NULL
, "dsll", "d,w,<", reg
,
2804 mid16
.X_add_number
>>= 16;
2805 macro_build ((char *) NULL
, counter
, &mid16
, "ori", "t,r,i", reg
,
2806 freg
, (int) BFD_RELOC_LO16
);
2807 macro_build ((char *) NULL
, counter
, NULL
, "dsll", "d,w,<", reg
,
2811 if ((lo32
.X_add_number
& 0xffff) != 0)
2812 macro_build ((char *) NULL
, counter
, &lo32
, "ori", "t,r,i", reg
, freg
,
2813 (int) BFD_RELOC_LO16
);
2816 /* Load an address into a register. */
2819 load_address (counter
, reg
, ep
)
2826 if (ep
->X_op
!= O_constant
2827 && ep
->X_op
!= O_symbol
)
2829 as_bad ("expression too complex");
2830 ep
->X_op
= O_constant
;
2833 if (ep
->X_op
== O_constant
)
2835 load_register (counter
, reg
, ep
, 0);
2839 if (mips_pic
== NO_PIC
)
2841 /* If this is a reference to a GP relative symbol, we want
2842 addiu $reg,$gp,<sym> (BFD_RELOC_MIPS_GPREL)
2844 lui $reg,<sym> (BFD_RELOC_HI16_S)
2845 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
2846 If we have an addend, we always use the latter form. */
2847 if ((valueT
) ep
->X_add_number
>= MAX_GPREL_OFFSET
2848 || nopic_need_relax (ep
->X_add_symbol
))
2853 macro_build ((char *) NULL
, counter
, ep
,
2854 mips_isa
< 3 ? "addiu" : "daddiu",
2855 "t,r,j", reg
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
2856 p
= frag_var (rs_machine_dependent
, 8, 0,
2857 RELAX_ENCODE (4, 8, 0, 4, 0, mips_warn_about_macros
),
2858 ep
->X_add_symbol
, (long) 0, (char *) NULL
);
2860 macro_build_lui (p
, counter
, ep
, reg
);
2863 macro_build (p
, counter
, ep
,
2864 mips_isa
< 3 ? "addiu" : "daddiu",
2865 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
2867 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
2871 /* If this is a reference to an external symbol, we want
2872 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
2874 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
2876 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
2877 If there is a constant, it must be added in after. */
2878 ex
.X_add_number
= ep
->X_add_number
;
2879 ep
->X_add_number
= 0;
2881 macro_build ((char *) NULL
, counter
, ep
,
2882 mips_isa
< 3 ? "lw" : "ld",
2883 "t,o(b)", reg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
2884 macro_build ((char *) NULL
, counter
, (expressionS
*) NULL
, "nop", "");
2885 p
= frag_var (rs_machine_dependent
, 4, 0,
2886 RELAX_ENCODE (0, 4, -8, 0, 0, mips_warn_about_macros
),
2887 ep
->X_add_symbol
, (long) 0, (char *) NULL
);
2888 macro_build (p
, counter
, ep
,
2889 mips_isa
< 3 ? "addiu" : "daddiu",
2890 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
2891 if (ex
.X_add_number
!= 0)
2893 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
2894 as_bad ("PIC code offset overflow (max 16 signed bits)");
2895 ex
.X_op
= O_constant
;
2896 macro_build ((char *) NULL
, counter
, &ex
,
2897 mips_isa
< 3 ? "addiu" : "daddiu",
2898 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
2901 else if (mips_pic
== SVR4_PIC
)
2906 /* This is the large GOT case. If this is a reference to an
2907 external symbol, we want
2908 lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
2910 lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16)
2911 Otherwise, for a reference to a local symbol, we want
2912 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
2914 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
2915 If there is a constant, it must be added in after. */
2916 ex
.X_add_number
= ep
->X_add_number
;
2917 ep
->X_add_number
= 0;
2918 if (reg_needs_delay (GP
))
2923 macro_build ((char *) NULL
, counter
, ep
, "lui", "t,u", reg
,
2924 (int) BFD_RELOC_MIPS_GOT_HI16
);
2925 macro_build ((char *) NULL
, counter
, (expressionS
*) NULL
,
2926 mips_isa
< 3 ? "addu" : "daddu",
2927 "d,v,t", reg
, reg
, GP
);
2928 macro_build ((char *) NULL
, counter
, ep
,
2929 mips_isa
< 3 ? "lw" : "ld",
2930 "t,o(b)", reg
, (int) BFD_RELOC_MIPS_GOT_LO16
, reg
);
2931 p
= frag_var (rs_machine_dependent
, 12 + off
, 0,
2932 RELAX_ENCODE (12, 12 + off
, off
, 8 + off
, 0,
2933 mips_warn_about_macros
),
2934 ep
->X_add_symbol
, (long) 0, (char *) NULL
);
2937 /* We need a nop before loading from $gp. This special
2938 check is required because the lui which starts the main
2939 instruction stream does not refer to $gp, and so will not
2940 insert the nop which may be required. */
2941 macro_build (p
, counter
, (expressionS
*) NULL
, "nop", "");
2944 macro_build (p
, counter
, ep
,
2945 mips_isa
< 3 ? "lw" : "ld",
2946 "t,o(b)", reg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
2948 macro_build (p
, counter
, (expressionS
*) NULL
, "nop", "");
2950 macro_build (p
, counter
, ep
,
2951 mips_isa
< 3 ? "addiu" : "daddiu",
2952 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
2953 if (ex
.X_add_number
!= 0)
2955 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
2956 as_bad ("PIC code offset overflow (max 16 signed bits)");
2957 ex
.X_op
= O_constant
;
2958 macro_build ((char *) NULL
, counter
, &ex
,
2959 mips_isa
< 3 ? "addiu" : "daddiu",
2960 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
2963 else if (mips_pic
== EMBEDDED_PIC
)
2966 addiu $reg,$gp,<sym> (BFD_RELOC_MIPS_GPREL)
2968 macro_build ((char *) NULL
, counter
, ep
,
2969 mips_isa
< 3 ? "addiu" : "daddiu",
2970 "t,r,j", reg
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
2978 * This routine implements the seemingly endless macro or synthesized
2979 * instructions and addressing modes in the mips assembly language. Many
2980 * of these macros are simple and are similar to each other. These could
2981 * probably be handled by some kind of table or grammer aproach instead of
2982 * this verbose method. Others are not simple macros but are more like
2983 * optimizing code generation.
2984 * One interesting optimization is when several store macros appear
2985 * consecutivly that would load AT with the upper half of the same address.
2986 * The ensuing load upper instructions are ommited. This implies some kind
2987 * of global optimization. We currently only optimize within a single macro.
2988 * For many of the load and store macros if the address is specified as a
2989 * constant expression in the first 64k of memory (ie ld $2,0x4000c) we
2990 * first load register 'at' with zero and use it as the base register. The
2991 * mips assembler simply uses register $zero. Just one tiny optimization
2996 struct mips_cl_insn
*ip
;
2998 register int treg
, sreg
, dreg
, breg
;
3013 bfd_reloc_code_real_type r
;
3015 int hold_mips_optimize
;
3019 treg
= (ip
->insn_opcode
>> 16) & 0x1f;
3020 dreg
= (ip
->insn_opcode
>> 11) & 0x1f;
3021 sreg
= breg
= (ip
->insn_opcode
>> 21) & 0x1f;
3022 mask
= ip
->insn_mo
->mask
;
3024 expr1
.X_op
= O_constant
;
3025 expr1
.X_op_symbol
= NULL
;
3026 expr1
.X_add_symbol
= NULL
;
3027 expr1
.X_add_number
= 1;
3039 mips_emit_delays (true);
3041 mips_any_noreorder
= 1;
3043 expr1
.X_add_number
= 8;
3044 macro_build ((char *) NULL
, &icnt
, &expr1
, "bgez", "s,p", sreg
);
3046 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
3048 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
, sreg
, 0);
3049 macro_build ((char *) NULL
, &icnt
, NULL
,
3050 dbl
? "dsub" : "sub",
3051 "d,v,t", dreg
, 0, sreg
);
3074 if (imm_expr
.X_add_number
>= -0x8000 && imm_expr
.X_add_number
< 0x8000)
3076 macro_build ((char *) NULL
, &icnt
, &imm_expr
, s
, "t,r,j", treg
, sreg
,
3077 (int) BFD_RELOC_LO16
);
3080 load_register (&icnt
, AT
, &imm_expr
, dbl
);
3081 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "d,v,t", treg
, sreg
, AT
);
3100 if (imm_expr
.X_add_number
>= 0 && imm_expr
.X_add_number
< 0x10000)
3102 if (mask
!= M_NOR_I
)
3103 macro_build ((char *) NULL
, &icnt
, &imm_expr
, s
, "t,r,i", treg
,
3104 sreg
, (int) BFD_RELOC_LO16
);
3107 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "ori", "t,r,i",
3108 treg
, sreg
, (int) BFD_RELOC_LO16
);
3109 macro_build ((char *) NULL
, &icnt
, NULL
, "nor", "d,v,t",
3115 load_register (&icnt
, AT
, &imm_expr
, 0);
3116 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "d,v,t", treg
, sreg
, AT
);
3133 if (imm_expr
.X_add_number
== 0)
3135 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "s,t,p", sreg
,
3139 load_register (&icnt
, AT
, &imm_expr
, 0);
3140 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "s,t,p", sreg
, AT
);
3148 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3149 likely
? "bgezl" : "bgez",
3155 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3156 likely
? "blezl" : "blez",
3160 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", AT
, sreg
, treg
);
3161 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3162 likely
? "beql" : "beq",
3169 /* check for > max integer */
3170 maxnum
= 0x7fffffff;
3178 if (imm_expr
.X_add_number
>= maxnum
3179 && (mips_isa
< 3 || sizeof (maxnum
) > 4))
3182 /* result is always false */
3185 as_warn ("Branch %s is always false (nop)", ip
->insn_mo
->name
);
3186 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
3190 as_warn ("Branch likely %s is always false", ip
->insn_mo
->name
);
3191 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "bnel",
3196 imm_expr
.X_add_number
++;
3200 if (mask
== M_BGEL_I
)
3202 if (imm_expr
.X_add_number
== 0)
3204 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3205 likely
? "bgezl" : "bgez",
3209 if (imm_expr
.X_add_number
== 1)
3211 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3212 likely
? "bgtzl" : "bgtz",
3216 maxnum
= 0x7fffffff;
3224 maxnum
= - maxnum
- 1;
3225 if (imm_expr
.X_add_number
<= maxnum
3226 && (mips_isa
< 3 || sizeof (maxnum
) > 4))
3229 /* result is always true */
3230 as_warn ("Branch %s is always true", ip
->insn_mo
->name
);
3231 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "b", "p");
3234 set_at (&icnt
, sreg
, 0);
3235 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3236 likely
? "beql" : "beq",
3247 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3248 likely
? "beql" : "beq",
3252 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", AT
, sreg
,
3254 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3255 likely
? "beql" : "beq",
3262 if (sreg
== 0 || imm_expr
.X_add_number
== -1)
3264 imm_expr
.X_add_number
++;
3268 if (mask
== M_BGEUL_I
)
3270 if (imm_expr
.X_add_number
== 0)
3272 if (imm_expr
.X_add_number
== 1)
3274 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3275 likely
? "bnel" : "bne",
3279 set_at (&icnt
, sreg
, 1);
3280 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3281 likely
? "beql" : "beq",
3290 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3291 likely
? "bgtzl" : "bgtz",
3297 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3298 likely
? "bltzl" : "bltz",
3302 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", AT
, treg
, sreg
);
3303 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3304 likely
? "bnel" : "bne",
3313 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3314 likely
? "bnel" : "bne",
3320 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", AT
, treg
,
3322 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3323 likely
? "bnel" : "bne",
3332 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3333 likely
? "blezl" : "blez",
3339 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3340 likely
? "bgezl" : "bgez",
3344 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", AT
, treg
, sreg
);
3345 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3346 likely
? "beql" : "beq",
3353 maxnum
= 0x7fffffff;
3361 if (imm_expr
.X_add_number
>= maxnum
3362 && (mips_isa
< 3 || sizeof (maxnum
) > 4))
3364 imm_expr
.X_add_number
++;
3368 if (mask
== M_BLTL_I
)
3370 if (imm_expr
.X_add_number
== 0)
3372 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3373 likely
? "bltzl" : "bltz",
3377 if (imm_expr
.X_add_number
== 1)
3379 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3380 likely
? "blezl" : "blez",
3384 set_at (&icnt
, sreg
, 0);
3385 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3386 likely
? "bnel" : "bne",
3395 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3396 likely
? "beql" : "beq",
3402 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", AT
, treg
,
3404 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3405 likely
? "beql" : "beq",
3412 if (sreg
== 0 || imm_expr
.X_add_number
== -1)
3414 imm_expr
.X_add_number
++;
3418 if (mask
== M_BLTUL_I
)
3420 if (imm_expr
.X_add_number
== 0)
3422 if (imm_expr
.X_add_number
== 1)
3424 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3425 likely
? "beql" : "beq",
3429 set_at (&icnt
, sreg
, 1);
3430 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3431 likely
? "bnel" : "bne",
3440 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3441 likely
? "bltzl" : "bltz",
3447 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3448 likely
? "bgtzl" : "bgtz",
3452 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", AT
, sreg
, treg
);
3453 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3454 likely
? "bnel" : "bne",
3465 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3466 likely
? "bnel" : "bne",
3470 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", AT
, sreg
,
3472 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3473 likely
? "bnel" : "bne",
3489 as_warn ("Divide by zero.");
3491 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", 0, 0);
3493 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 7);
3497 mips_emit_delays (true);
3499 mips_any_noreorder
= 1;
3500 macro_build ((char *) NULL
, &icnt
, NULL
,
3501 dbl
? "ddiv" : "div",
3502 "z,s,t", sreg
, treg
);
3504 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", treg
, 0);
3507 expr1
.X_add_number
= 8;
3508 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", treg
, 0);
3509 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
3510 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 7);
3512 expr1
.X_add_number
= -1;
3513 macro_build ((char *) NULL
, &icnt
, &expr1
,
3514 dbl
? "daddiu" : "addiu",
3515 "t,r,j", AT
, 0, (int) BFD_RELOC_LO16
);
3516 expr1
.X_add_number
= mips_trap
? (dbl
? 12 : 8) : (dbl
? 20 : 16);
3517 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", treg
, AT
);
3520 expr1
.X_add_number
= 1;
3521 macro_build ((char *) NULL
, &icnt
, &expr1
, "daddiu", "t,r,j", AT
, 0,
3522 (int) BFD_RELOC_LO16
);
3523 macro_build ((char *) NULL
, &icnt
, NULL
, "dsll32", "d,w,<", AT
, AT
,
3528 expr1
.X_add_number
= 0x80000000;
3529 macro_build ((char *) NULL
, &icnt
, &expr1
, "lui", "t,u", AT
,
3530 (int) BFD_RELOC_HI16
);
3533 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", sreg
, AT
);
3536 expr1
.X_add_number
= 8;
3537 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", sreg
, AT
);
3538 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
3539 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 6);
3542 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d", dreg
);
3581 if (imm_expr
.X_add_number
== 0)
3583 as_warn ("Divide by zero.");
3585 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", 0, 0);
3587 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 7);
3590 if (imm_expr
.X_add_number
== 1)
3592 if (strcmp (s2
, "mflo") == 0)
3593 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
,
3596 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
, 0);
3599 if (imm_expr
.X_add_number
== -1
3600 && s
[strlen (s
) - 1] != 'u')
3602 if (strcmp (s2
, "mflo") == 0)
3605 macro_build ((char *) NULL
, &icnt
, NULL
, "dneg", "d,w", dreg
,
3608 macro_build ((char *) NULL
, &icnt
, NULL
, "neg", "d,w", dreg
,
3612 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
, 0);
3616 load_register (&icnt
, AT
, &imm_expr
, dbl
);
3617 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "z,s,t", sreg
, AT
);
3618 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "d", dreg
);
3637 mips_emit_delays (true);
3639 mips_any_noreorder
= 1;
3640 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "z,s,t", sreg
, treg
);
3642 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", treg
, 0);
3645 expr1
.X_add_number
= 8;
3646 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", treg
, 0);
3647 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
3648 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 7);
3651 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "d", dreg
);
3657 /* Load the address of a symbol into a register. If breg is not
3658 zero, we then add a base register to it. */
3660 /* When generating embedded PIC code, we permit expressions of
3663 where bar is an address in the .text section. These are used
3664 when getting the addresses of functions. We don't permit
3665 X_add_number to be non-zero, because if the symbol is
3666 external the relaxing code needs to know that any addend is
3667 purely the offset to X_op_symbol. */
3668 if (mips_pic
== EMBEDDED_PIC
3669 && offset_expr
.X_op
== O_subtract
3670 && now_seg
== text_section
3671 && (offset_expr
.X_op_symbol
->sy_value
.X_op
== O_constant
3672 ? S_GET_SEGMENT (offset_expr
.X_op_symbol
) == text_section
3673 : (offset_expr
.X_op_symbol
->sy_value
.X_op
== O_symbol
3674 && (S_GET_SEGMENT (offset_expr
.X_op_symbol
3675 ->sy_value
.X_add_symbol
)
3678 && offset_expr
.X_add_number
== 0)
3680 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
3681 treg
, (int) BFD_RELOC_PCREL_HI16_S
);
3682 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3683 mips_isa
< 3 ? "addiu" : "daddiu",
3684 "t,r,j", treg
, treg
, (int) BFD_RELOC_PCREL_LO16
);
3688 if (offset_expr
.X_op
!= O_symbol
3689 && offset_expr
.X_op
!= O_constant
)
3691 as_bad ("expression too complex");
3692 offset_expr
.X_op
= O_constant
;
3706 if (offset_expr
.X_op
== O_constant
)
3707 load_register (&icnt
, tempreg
, &offset_expr
, dbl
);
3708 else if (mips_pic
== NO_PIC
)
3710 /* If this is a reference to an GP relative symbol, we want
3711 addiu $tempreg,$gp,<sym> (BFD_RELOC_MIPS_GPREL)
3713 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
3714 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
3715 If we have a constant, we need two instructions anyhow,
3716 so we may as well always use the latter form. */
3717 if ((valueT
) offset_expr
.X_add_number
>= MAX_GPREL_OFFSET
3718 || nopic_need_relax (offset_expr
.X_add_symbol
))
3723 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3724 mips_isa
< 3 ? "addiu" : "daddiu",
3725 "t,r,j", tempreg
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
3726 p
= frag_var (rs_machine_dependent
, 8, 0,
3727 RELAX_ENCODE (4, 8, 0, 4, 0,
3728 mips_warn_about_macros
),
3729 offset_expr
.X_add_symbol
, (long) 0,
3732 macro_build_lui (p
, &icnt
, &offset_expr
, tempreg
);
3735 macro_build (p
, &icnt
, &offset_expr
,
3736 mips_isa
< 3 ? "addiu" : "daddiu",
3737 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
3739 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
3741 /* If this is a reference to an external symbol, and there
3742 is no constant, we want
3743 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3744 For a local symbol, we want
3745 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3747 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
3749 If we have a small constant, and this is a reference to
3750 an external symbol, we want
3751 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3753 addiu $tempreg,$tempreg,<constant>
3754 For a local symbol, we want the same instruction
3755 sequence, but we output a BFD_RELOC_LO16 reloc on the
3758 If we have a large constant, and this is a reference to
3759 an external symbol, we want
3760 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3761 lui $at,<hiconstant>
3762 addiu $at,$at,<loconstant>
3763 addu $tempreg,$tempreg,$at
3764 For a local symbol, we want the same instruction
3765 sequence, but we output a BFD_RELOC_LO16 reloc on the
3766 addiu instruction. */
3767 expr1
.X_add_number
= offset_expr
.X_add_number
;
3768 offset_expr
.X_add_number
= 0;
3770 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3772 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
3773 if (expr1
.X_add_number
== 0)
3781 /* We're going to put in an addu instruction using
3782 tempreg, so we may as well insert the nop right
3784 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3788 p
= frag_var (rs_machine_dependent
, 8 - off
, 0,
3789 RELAX_ENCODE (0, 8 - off
, -4 - off
, 4 - off
, 0,
3791 ? mips_warn_about_macros
3793 offset_expr
.X_add_symbol
, (long) 0,
3797 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
3800 macro_build (p
, &icnt
, &expr1
,
3801 mips_isa
< 3 ? "addiu" : "daddiu",
3802 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
3803 /* FIXME: If breg == 0, and the next instruction uses
3804 $tempreg, then if this variant case is used an extra
3805 nop will be generated. */
3807 else if (expr1
.X_add_number
>= -0x8000
3808 && expr1
.X_add_number
< 0x8000)
3810 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3812 macro_build ((char *) NULL
, &icnt
, &expr1
,
3813 mips_isa
< 3 ? "addiu" : "daddiu",
3814 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
3815 (void) frag_var (rs_machine_dependent
, 0, 0,
3816 RELAX_ENCODE (0, 0, -12, -4, 0, 0),
3817 offset_expr
.X_add_symbol
, (long) 0,
3824 /* If we are going to add in a base register, and the
3825 target register and the base register are the same,
3826 then we are using AT as a temporary register. Since
3827 we want to load the constant into AT, we add our
3828 current AT (from the global offset table) and the
3829 register into the register now, and pretend we were
3830 not using a base register. */
3835 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3837 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3838 mips_isa
< 3 ? "addu" : "daddu",
3839 "d,v,t", treg
, AT
, breg
);
3845 /* Set mips_optimize around the lui instruction to avoid
3846 inserting an unnecessary nop after the lw. */
3847 hold_mips_optimize
= mips_optimize
;
3849 macro_build_lui ((char *) NULL
, &icnt
, &expr1
, AT
);
3850 mips_optimize
= hold_mips_optimize
;
3852 macro_build ((char *) NULL
, &icnt
, &expr1
,
3853 mips_isa
< 3 ? "addiu" : "daddiu",
3854 "t,r,j", AT
, AT
, (int) BFD_RELOC_LO16
);
3855 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3856 mips_isa
< 3 ? "addu" : "daddu",
3857 "d,v,t", tempreg
, tempreg
, AT
);
3858 (void) frag_var (rs_machine_dependent
, 0, 0,
3859 RELAX_ENCODE (0, 0, -16 + off1
, -8, 0, 0),
3860 offset_expr
.X_add_symbol
, (long) 0,
3865 else if (mips_pic
== SVR4_PIC
)
3869 /* This is the large GOT case. If this is a reference to an
3870 external symbol, and there is no constant, we want
3871 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
3872 addu $tempreg,$tempreg,$gp
3873 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
3874 For a local symbol, we want
3875 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3877 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
3879 If we have a small constant, and this is a reference to
3880 an external symbol, we want
3881 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
3882 addu $tempreg,$tempreg,$gp
3883 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
3885 addiu $tempreg,$tempreg,<constant>
3886 For a local symbol, we want
3887 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3889 addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16)
3891 If we have a large constant, and this is a reference to
3892 an external symbol, we want
3893 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
3894 addu $tempreg,$tempreg,$gp
3895 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
3896 lui $at,<hiconstant>
3897 addiu $at,$at,<loconstant>
3898 addu $tempreg,$tempreg,$at
3899 For a local symbol, we want
3900 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3901 lui $at,<hiconstant>
3902 addiu $at,$at,<loconstant> (BFD_RELOC_LO16)
3903 addu $tempreg,$tempreg,$at
3905 expr1
.X_add_number
= offset_expr
.X_add_number
;
3906 offset_expr
.X_add_number
= 0;
3908 if (reg_needs_delay (GP
))
3912 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
3913 tempreg
, (int) BFD_RELOC_MIPS_GOT_HI16
);
3914 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3915 mips_isa
< 3 ? "addu" : "daddu",
3916 "d,v,t", tempreg
, tempreg
, GP
);
3917 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3919 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT_LO16
,
3921 if (expr1
.X_add_number
== 0)
3929 /* We're going to put in an addu instruction using
3930 tempreg, so we may as well insert the nop right
3932 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3937 p
= frag_var (rs_machine_dependent
, 12 + gpdel
, 0,
3938 RELAX_ENCODE (12 + off
, 12 + gpdel
, gpdel
,
3941 ? mips_warn_about_macros
3943 offset_expr
.X_add_symbol
, (long) 0,
3946 else if (expr1
.X_add_number
>= -0x8000
3947 && expr1
.X_add_number
< 0x8000)
3949 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3951 macro_build ((char *) NULL
, &icnt
, &expr1
,
3952 mips_isa
< 3 ? "addiu" : "daddiu",
3953 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
3955 p
= frag_var (rs_machine_dependent
, 12 + gpdel
, 0,
3956 RELAX_ENCODE (20, 12 + gpdel
, gpdel
, 8 + gpdel
, 0,
3958 ? mips_warn_about_macros
3960 offset_expr
.X_add_symbol
, (long) 0,
3967 /* If we are going to add in a base register, and the
3968 target register and the base register are the same,
3969 then we are using AT as a temporary register. Since
3970 we want to load the constant into AT, we add our
3971 current AT (from the global offset table) and the
3972 register into the register now, and pretend we were
3973 not using a base register. */
3981 assert (tempreg
== AT
);
3982 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3984 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3985 mips_isa
< 3 ? "addu" : "daddu",
3986 "d,v,t", treg
, AT
, breg
);
3991 /* Set mips_optimize around the lui instruction to avoid
3992 inserting an unnecessary nop after the lw. */
3993 hold_mips_optimize
= mips_optimize
;
3995 macro_build_lui ((char *) NULL
, &icnt
, &expr1
, AT
);
3996 mips_optimize
= hold_mips_optimize
;
3998 macro_build ((char *) NULL
, &icnt
, &expr1
,
3999 mips_isa
< 3 ? "addiu" : "daddiu",
4000 "t,r,j", AT
, AT
, (int) BFD_RELOC_LO16
);
4001 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4002 mips_isa
< 3 ? "addu" : "daddu",
4003 "d,v,t", dreg
, dreg
, AT
);
4005 p
= frag_var (rs_machine_dependent
, 16 + gpdel
+ adj
, 0,
4006 RELAX_ENCODE (24 + adj
, 16 + gpdel
+ adj
, gpdel
,
4009 ? mips_warn_about_macros
4011 offset_expr
.X_add_symbol
, (long) 0,
4019 /* This is needed because this instruction uses $gp, but
4020 the first instruction on the main stream does not. */
4021 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4024 macro_build (p
, &icnt
, &offset_expr
,
4026 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
4028 if (expr1
.X_add_number
>= -0x8000
4029 && expr1
.X_add_number
< 0x8000)
4031 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4033 macro_build (p
, &icnt
, &expr1
,
4034 mips_isa
< 3 ? "addiu" : "daddiu",
4035 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
4036 /* FIXME: If add_number is 0, and there was no base
4037 register, the external symbol case ended with a load,
4038 so if the symbol turns out to not be external, and
4039 the next instruction uses tempreg, an unnecessary nop
4040 will be inserted. */
4046 /* We must add in the base register now, as in the
4047 external symbol case. */
4048 assert (tempreg
== AT
);
4049 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4051 macro_build (p
, &icnt
, (expressionS
*) NULL
,
4052 mips_isa
< 3 ? "addu" : "daddu",
4053 "d,v,t", treg
, AT
, breg
);
4056 /* We set breg to 0 because we have arranged to add
4057 it in in both cases. */
4061 macro_build_lui (p
, &icnt
, &expr1
, AT
);
4063 macro_build (p
, &icnt
, &expr1
,
4064 mips_isa
< 3 ? "addiu" : "daddiu",
4065 "t,r,j", AT
, AT
, (int) BFD_RELOC_LO16
);
4067 macro_build (p
, &icnt
, (expressionS
*) NULL
,
4068 mips_isa
< 3 ? "addu" : "daddu",
4069 "d,v,t", tempreg
, tempreg
, AT
);
4073 else if (mips_pic
== EMBEDDED_PIC
)
4076 addiu $tempreg,$gp,<sym> (BFD_RELOC_MIPS_GPREL)
4078 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4079 mips_isa
< 3 ? "addiu" : "daddiu",
4080 "t,r,j", tempreg
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
4086 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4087 mips_isa
< 3 ? "addu" : "daddu",
4088 "d,v,t", treg
, tempreg
, breg
);
4096 /* The j instruction may not be used in PIC code, since it
4097 requires an absolute address. We convert it to a b
4099 if (mips_pic
== NO_PIC
)
4100 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "j", "a");
4102 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "b", "p");
4105 /* The jal instructions must be handled as macros because when
4106 generating PIC code they expand to multi-instruction
4107 sequences. Normally they are simple instructions. */
4112 if (mips_pic
== NO_PIC
4113 || mips_pic
== EMBEDDED_PIC
)
4114 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "jalr",
4116 else if (mips_pic
== SVR4_PIC
)
4118 if (sreg
!= PIC_CALL_REG
)
4119 as_warn ("MIPS PIC call to register other than $25");
4121 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "jalr",
4123 if (mips_cprestore_offset
< 0)
4124 as_warn ("No .cprestore pseudo-op used in PIC code");
4127 expr1
.X_add_number
= mips_cprestore_offset
;
4128 macro_build ((char *) NULL
, &icnt
, &expr1
,
4129 mips_isa
< 3 ? "lw" : "ld",
4130 "t,o(b)", GP
, (int) BFD_RELOC_LO16
, mips_frame_reg
);
4139 if (mips_pic
== NO_PIC
)
4140 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "jal", "a");
4141 else if (mips_pic
== SVR4_PIC
)
4143 /* If this is a reference to an external symbol, and we are
4144 using a small GOT, we want
4145 lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
4149 lw $gp,cprestore($sp)
4150 The cprestore value is set using the .cprestore
4151 pseudo-op. If we are using a big GOT, we want
4152 lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16)
4154 lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16)
4158 lw $gp,cprestore($sp)
4159 If the symbol is not external, we want
4160 lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4162 addiu $25,$25,<sym> (BFD_RELOC_LO16)
4165 lw $gp,cprestore($sp) */
4169 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4170 mips_isa
< 3 ? "lw" : "ld",
4171 "t,o(b)", PIC_CALL_REG
,
4172 (int) BFD_RELOC_MIPS_CALL16
, GP
);
4173 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4175 p
= frag_var (rs_machine_dependent
, 4, 0,
4176 RELAX_ENCODE (0, 4, -8, 0, 0, 0),
4177 offset_expr
.X_add_symbol
, (long) 0, (char *) NULL
);
4183 if (reg_needs_delay (GP
))
4187 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
4188 PIC_CALL_REG
, (int) BFD_RELOC_MIPS_CALL_HI16
);
4189 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4190 mips_isa
< 3 ? "addu" : "daddu",
4191 "d,v,t", PIC_CALL_REG
, PIC_CALL_REG
, GP
);
4192 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4193 mips_isa
< 3 ? "lw" : "ld",
4194 "t,o(b)", PIC_CALL_REG
,
4195 (int) BFD_RELOC_MIPS_CALL_LO16
, PIC_CALL_REG
);
4196 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4198 p
= frag_var (rs_machine_dependent
, 12 + gpdel
, 0,
4199 RELAX_ENCODE (16, 12 + gpdel
, gpdel
, 8 + gpdel
,
4201 offset_expr
.X_add_symbol
, (long) 0, (char *) NULL
);
4204 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4207 macro_build (p
, &icnt
, &offset_expr
,
4208 mips_isa
< 3 ? "lw" : "ld",
4209 "t,o(b)", PIC_CALL_REG
,
4210 (int) BFD_RELOC_MIPS_GOT16
, GP
);
4212 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4215 macro_build (p
, &icnt
, &offset_expr
,
4216 mips_isa
< 3 ? "addiu" : "daddiu",
4217 "t,r,j", PIC_CALL_REG
, PIC_CALL_REG
,
4218 (int) BFD_RELOC_LO16
);
4219 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4220 "jalr", "s", PIC_CALL_REG
);
4221 if (mips_cprestore_offset
< 0)
4222 as_warn ("No .cprestore pseudo-op used in PIC code");
4226 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4228 expr1
.X_add_number
= mips_cprestore_offset
;
4229 macro_build ((char *) NULL
, &icnt
, &expr1
,
4230 mips_isa
< 3 ? "lw" : "ld",
4231 "t,o(b)", GP
, (int) BFD_RELOC_LO16
,
4235 else if (mips_pic
== EMBEDDED_PIC
)
4237 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "bal", "p");
4238 /* The linker may expand the call to a longer sequence which
4239 uses $at, so we must break rather than return. */
4315 if (breg
== treg
|| coproc
|| lr
)
4384 if (mask
== M_LWC1_AB
4385 || mask
== M_SWC1_AB
4386 || mask
== M_LDC1_AB
4387 || mask
== M_SDC1_AB
4396 if (offset_expr
.X_op
!= O_constant
4397 && offset_expr
.X_op
!= O_symbol
)
4399 as_bad ("expression too complex");
4400 offset_expr
.X_op
= O_constant
;
4403 /* A constant expression in PIC code can be handled just as it
4404 is in non PIC code. */
4405 if (mips_pic
== NO_PIC
4406 || offset_expr
.X_op
== O_constant
)
4408 /* If this is a reference to a GP relative symbol, and there
4409 is no base register, we want
4410 <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL)
4411 Otherwise, if there is no base register, we want
4412 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
4413 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
4414 If we have a constant, we need two instructions anyhow,
4415 so we always use the latter form.
4417 If we have a base register, and this is a reference to a
4418 GP relative symbol, we want
4419 addu $tempreg,$breg,$gp
4420 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GPREL)
4422 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
4423 addu $tempreg,$tempreg,$breg
4424 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
4425 With a constant we always use the latter case. */
4428 if ((valueT
) offset_expr
.X_add_number
>= MAX_GPREL_OFFSET
4429 || nopic_need_relax (offset_expr
.X_add_symbol
))
4434 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
4435 treg
, (int) BFD_RELOC_MIPS_GPREL
, GP
);
4436 p
= frag_var (rs_machine_dependent
, 8, 0,
4437 RELAX_ENCODE (4, 8, 0, 4, 0,
4438 (mips_warn_about_macros
4439 || (used_at
&& mips_noat
))),
4440 offset_expr
.X_add_symbol
, (long) 0,
4444 macro_build_lui (p
, &icnt
, &offset_expr
, tempreg
);
4447 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
, treg
,
4448 (int) BFD_RELOC_LO16
, tempreg
);
4452 if ((valueT
) offset_expr
.X_add_number
>= MAX_GPREL_OFFSET
4453 || nopic_need_relax (offset_expr
.X_add_symbol
))
4458 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4459 mips_isa
< 3 ? "addu" : "daddu",
4460 "d,v,t", tempreg
, breg
, GP
);
4461 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
4462 treg
, (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
4463 p
= frag_var (rs_machine_dependent
, 12, 0,
4464 RELAX_ENCODE (8, 12, 0, 8, 0, 0),
4465 offset_expr
.X_add_symbol
, (long) 0,
4468 macro_build_lui (p
, &icnt
, &offset_expr
, tempreg
);
4471 macro_build (p
, &icnt
, (expressionS
*) NULL
,
4472 mips_isa
< 3 ? "addu" : "daddu",
4473 "d,v,t", tempreg
, tempreg
, breg
);
4476 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
, treg
,
4477 (int) BFD_RELOC_LO16
, tempreg
);
4480 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
4482 /* If this is a reference to an external symbol, we want
4483 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4485 <op> $treg,0($tempreg)
4487 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4489 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
4490 <op> $treg,0($tempreg)
4491 If there is a base register, we add it to $tempreg before
4492 the <op>. If there is a constant, we stick it in the
4493 <op> instruction. We don't handle constants larger than
4494 16 bits, because we have no way to load the upper 16 bits
4495 (actually, we could handle them for the subset of cases
4496 in which we are not using $at). */
4497 assert (offset_expr
.X_op
== O_symbol
);
4498 expr1
.X_add_number
= offset_expr
.X_add_number
;
4499 offset_expr
.X_add_number
= 0;
4500 if (expr1
.X_add_number
< -0x8000
4501 || expr1
.X_add_number
>= 0x8000)
4502 as_bad ("PIC code offset overflow (max 16 signed bits)");
4504 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4505 mips_isa
< 3 ? "lw" : "ld",
4506 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
4507 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
4508 p
= frag_var (rs_machine_dependent
, 4, 0,
4509 RELAX_ENCODE (0, 4, -8, 0, 0, 0),
4510 offset_expr
.X_add_symbol
, (long) 0,
4512 macro_build (p
, &icnt
, &offset_expr
,
4513 mips_isa
< 3 ? "addiu" : "daddiu",
4514 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
4516 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4517 mips_isa
< 3 ? "addu" : "daddu",
4518 "d,v,t", tempreg
, tempreg
, breg
);
4519 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
, treg
,
4520 (int) BFD_RELOC_LO16
, tempreg
);
4522 else if (mips_pic
== SVR4_PIC
)
4526 /* If this is a reference to an external symbol, we want
4527 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
4528 addu $tempreg,$tempreg,$gp
4529 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
4530 <op> $treg,0($tempreg)
4532 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4534 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
4535 <op> $treg,0($tempreg)
4536 If there is a base register, we add it to $tempreg before
4537 the <op>. If there is a constant, we stick it in the
4538 <op> instruction. We don't handle constants larger than
4539 16 bits, because we have no way to load the upper 16 bits
4540 (actually, we could handle them for the subset of cases
4541 in which we are not using $at). */
4542 assert (offset_expr
.X_op
== O_symbol
);
4543 expr1
.X_add_number
= offset_expr
.X_add_number
;
4544 offset_expr
.X_add_number
= 0;
4545 if (expr1
.X_add_number
< -0x8000
4546 || expr1
.X_add_number
>= 0x8000)
4547 as_bad ("PIC code offset overflow (max 16 signed bits)");
4548 if (reg_needs_delay (GP
))
4553 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
4554 tempreg
, (int) BFD_RELOC_MIPS_GOT_HI16
);
4555 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4556 mips_isa
< 3 ? "addu" : "daddu",
4557 "d,v,t", tempreg
, tempreg
, GP
);
4558 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4559 mips_isa
< 3 ? "lw" : "ld",
4560 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT_LO16
,
4562 p
= frag_var (rs_machine_dependent
, 12 + gpdel
, 0,
4563 RELAX_ENCODE (12, 12 + gpdel
, gpdel
, 8 + gpdel
, 0, 0),
4564 offset_expr
.X_add_symbol
, (long) 0, (char *) NULL
);
4567 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4570 macro_build (p
, &icnt
, &offset_expr
,
4571 mips_isa
< 3 ? "lw" : "ld",
4572 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
4574 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4576 macro_build (p
, &icnt
, &offset_expr
,
4577 mips_isa
< 3 ? "addiu" : "daddiu",
4578 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
4580 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4581 mips_isa
< 3 ? "addu" : "daddu",
4582 "d,v,t", tempreg
, tempreg
, breg
);
4583 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
, treg
,
4584 (int) BFD_RELOC_LO16
, tempreg
);
4586 else if (mips_pic
== EMBEDDED_PIC
)
4588 /* If there is no base register, we want
4589 <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL)
4590 If there is a base register, we want
4591 addu $tempreg,$breg,$gp
4592 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GPREL)
4594 assert (offset_expr
.X_op
== O_symbol
);
4597 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
4598 treg
, (int) BFD_RELOC_MIPS_GPREL
, GP
);
4603 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4604 mips_isa
< 3 ? "addu" : "daddu",
4605 "d,v,t", tempreg
, breg
, GP
);
4606 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
4607 treg
, (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
4620 load_register (&icnt
, treg
, &imm_expr
, 0);
4624 load_register (&icnt
, treg
, &imm_expr
, 1);
4628 if (imm_expr
.X_op
== O_constant
)
4630 load_register (&icnt
, AT
, &imm_expr
, 0);
4631 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4632 "mtc1", "t,G", AT
, treg
);
4637 assert (offset_expr
.X_op
== O_symbol
4638 && strcmp (segment_name (S_GET_SEGMENT
4639 (offset_expr
.X_add_symbol
)),
4641 && offset_expr
.X_add_number
== 0);
4642 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lwc1", "T,o(b)",
4643 treg
, (int) BFD_RELOC_MIPS_LITERAL
, GP
);
4648 /* We know that sym is in the .rdata section. First we get the
4649 upper 16 bits of the address. */
4650 if (mips_pic
== NO_PIC
)
4652 /* FIXME: This won't work for a 64 bit address. */
4653 macro_build_lui ((char *) NULL
, &icnt
, &offset_expr
, AT
);
4655 else if (mips_pic
== SVR4_PIC
)
4657 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4658 mips_isa
< 3 ? "lw" : "ld",
4659 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
4661 else if (mips_pic
== EMBEDDED_PIC
)
4663 /* For embedded PIC we pick up the entire address off $gp in
4664 a single instruction. */
4665 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4666 mips_isa
< 3 ? "addiu" : "daddiu",
4667 "t,r,j", AT
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
4668 offset_expr
.X_op
= O_constant
;
4669 offset_expr
.X_add_number
= 0;
4674 /* Now we load the register(s). */
4676 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "ld", "t,o(b)",
4677 treg
, (int) BFD_RELOC_LO16
, AT
);
4680 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lw", "t,o(b)",
4681 treg
, (int) BFD_RELOC_LO16
, AT
);
4684 /* FIXME: How in the world do we deal with the possible
4686 offset_expr
.X_add_number
+= 4;
4687 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lw", "t,o(b)",
4688 treg
+ 1, (int) BFD_RELOC_LO16
, AT
);
4692 /* To avoid confusion in tc_gen_reloc, we must ensure that this
4693 does not become a variant frag. */
4694 frag_wane (frag_now
);
4700 assert (offset_expr
.X_op
== O_symbol
4701 && offset_expr
.X_add_number
== 0);
4702 s
= segment_name (S_GET_SEGMENT (offset_expr
.X_add_symbol
));
4703 if (strcmp (s
, ".lit8") == 0)
4707 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "ldc1",
4708 "T,o(b)", treg
, (int) BFD_RELOC_MIPS_LITERAL
, GP
);
4712 r
= BFD_RELOC_MIPS_LITERAL
;
4717 assert (strcmp (s
, RDATA_SECTION_NAME
) == 0);
4718 if (mips_pic
== SVR4_PIC
)
4719 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4720 mips_isa
< 3 ? "lw" : "ld",
4721 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
4724 /* FIXME: This won't work for a 64 bit address. */
4725 macro_build_lui ((char *) NULL
, &icnt
, &offset_expr
, AT
);
4730 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "ldc1",
4731 "T,o(b)", treg
, (int) BFD_RELOC_LO16
, AT
);
4733 /* To avoid confusion in tc_gen_reloc, we must ensure
4734 that this does not become a variant frag. */
4735 frag_wane (frag_now
);
4746 /* Even on a big endian machine $fn comes before $fn+1. We have
4747 to adjust when loading from memory. */
4750 assert (mips_isa
< 2);
4751 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lwc1", "T,o(b)",
4752 target_big_endian
? treg
+ 1 : treg
,
4754 /* FIXME: A possible overflow which I don't know how to deal
4756 offset_expr
.X_add_number
+= 4;
4757 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lwc1", "T,o(b)",
4758 target_big_endian
? treg
: treg
+ 1,
4761 /* To avoid confusion in tc_gen_reloc, we must ensure that this
4762 does not become a variant frag. */
4763 frag_wane (frag_now
);
4772 * The MIPS assembler seems to check for X_add_number not
4773 * being double aligned and generating:
4776 * addiu at,at,%lo(foo+1)
4779 * But, the resulting address is the same after relocation so why
4780 * generate the extra instruction?
4827 if (offset_expr
.X_op
!= O_symbol
4828 && offset_expr
.X_op
!= O_constant
)
4830 as_bad ("expression too complex");
4831 offset_expr
.X_op
= O_constant
;
4834 /* Even on a big endian machine $fn comes before $fn+1. We have
4835 to adjust when loading from memory. We set coproc if we must
4836 load $fn+1 first. */
4837 if (! target_big_endian
)
4840 if (mips_pic
== NO_PIC
4841 || offset_expr
.X_op
== O_constant
)
4843 /* If this is a reference to a GP relative symbol, we want
4844 <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL)
4845 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_MIPS_GPREL)
4846 If we have a base register, we use this
4848 <op> $treg,<sym>($at) (BFD_RELOC_MIPS_GPREL)
4849 <op> $treg+1,<sym>+4($at) (BFD_RELOC_MIPS_GPREL)
4850 If this is not a GP relative symbol, we want
4851 lui $at,<sym> (BFD_RELOC_HI16_S)
4852 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
4853 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
4854 If there is a base register, we add it to $at after the
4855 lui instruction. If there is a constant, we always use
4857 if ((valueT
) offset_expr
.X_add_number
>= MAX_GPREL_OFFSET
4858 || nopic_need_relax (offset_expr
.X_add_symbol
))
4877 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4878 mips_isa
< 3 ? "addu" : "daddu",
4879 "d,v,t", AT
, breg
, GP
);
4885 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
4886 coproc
? treg
+ 1 : treg
,
4887 (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
4888 offset_expr
.X_add_number
+= 4;
4890 /* Set mips_optimize to 2 to avoid inserting an
4892 hold_mips_optimize
= mips_optimize
;
4894 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
4895 coproc
? treg
: treg
+ 1,
4896 (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
4897 mips_optimize
= hold_mips_optimize
;
4899 p
= frag_var (rs_machine_dependent
, 12 + off
, 0,
4900 RELAX_ENCODE (8 + off
, 12 + off
, 0, 4 + off
, 1,
4901 used_at
&& mips_noat
),
4902 offset_expr
.X_add_symbol
, (long) 0,
4905 /* We just generated two relocs. When tc_gen_reloc
4906 handles this case, it will skip the first reloc and
4907 handle the second. The second reloc already has an
4908 extra addend of 4, which we added above. We must
4909 subtract it out, and then subtract another 4 to make
4910 the first reloc come out right. The second reloc
4911 will come out right because we are going to add 4 to
4912 offset_expr when we build its instruction below. */
4913 offset_expr
.X_add_number
-= 8;
4914 offset_expr
.X_op
= O_constant
;
4916 macro_build_lui (p
, &icnt
, &offset_expr
, AT
);
4921 macro_build (p
, &icnt
, (expressionS
*) NULL
,
4922 mips_isa
< 3 ? "addu" : "daddu",
4923 "d,v,t", AT
, breg
, AT
);
4927 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
,
4928 coproc
? treg
+ 1 : treg
,
4929 (int) BFD_RELOC_LO16
, AT
);
4932 /* FIXME: How do we handle overflow here? */
4933 offset_expr
.X_add_number
+= 4;
4934 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
,
4935 coproc
? treg
: treg
+ 1,
4936 (int) BFD_RELOC_LO16
, AT
);
4938 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
4942 /* If this is a reference to an external symbol, we want
4943 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4948 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4950 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
4951 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
4952 If there is a base register we add it to $at before the
4953 lwc1 instructions. If there is a constant we include it
4954 in the lwc1 instructions. */
4956 expr1
.X_add_number
= offset_expr
.X_add_number
;
4957 offset_expr
.X_add_number
= 0;
4958 if (expr1
.X_add_number
< -0x8000
4959 || expr1
.X_add_number
>= 0x8000 - 4)
4960 as_bad ("PIC code offset overflow (max 16 signed bits)");
4965 frag_grow (24 + off
);
4966 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4967 mips_isa
< 3 ? "lw" : "ld",
4968 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
4969 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
4971 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4972 mips_isa
< 3 ? "addu" : "daddu",
4973 "d,v,t", AT
, breg
, AT
);
4974 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
4975 coproc
? treg
+ 1 : treg
,
4976 (int) BFD_RELOC_LO16
, AT
);
4977 expr1
.X_add_number
+= 4;
4979 /* Set mips_optimize to 2 to avoid inserting an undesired
4981 hold_mips_optimize
= mips_optimize
;
4983 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
4984 coproc
? treg
: treg
+ 1,
4985 (int) BFD_RELOC_LO16
, AT
);
4986 mips_optimize
= hold_mips_optimize
;
4988 (void) frag_var (rs_machine_dependent
, 0, 0,
4989 RELAX_ENCODE (0, 0, -16 - off
, -8, 1, 0),
4990 offset_expr
.X_add_symbol
, (long) 0,
4993 else if (mips_pic
== SVR4_PIC
)
4997 /* If this is a reference to an external symbol, we want
4998 lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5000 lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16)
5005 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5007 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
5008 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
5009 If there is a base register we add it to $at before the
5010 lwc1 instructions. If there is a constant we include it
5011 in the lwc1 instructions. */
5013 expr1
.X_add_number
= offset_expr
.X_add_number
;
5014 offset_expr
.X_add_number
= 0;
5015 if (expr1
.X_add_number
< -0x8000
5016 || expr1
.X_add_number
>= 0x8000 - 4)
5017 as_bad ("PIC code offset overflow (max 16 signed bits)");
5018 if (reg_needs_delay (GP
))
5027 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
5028 AT
, (int) BFD_RELOC_MIPS_GOT_HI16
);
5029 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5030 mips_isa
< 3 ? "addu" : "daddu",
5031 "d,v,t", AT
, AT
, GP
);
5032 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5033 mips_isa
< 3 ? "lw" : "ld",
5034 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT_LO16
, AT
);
5035 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
5037 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5038 mips_isa
< 3 ? "addu" : "daddu",
5039 "d,v,t", AT
, breg
, AT
);
5040 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
5041 coproc
? treg
+ 1 : treg
,
5042 (int) BFD_RELOC_LO16
, AT
);
5043 expr1
.X_add_number
+= 4;
5045 /* Set mips_optimize to 2 to avoid inserting an undesired
5047 hold_mips_optimize
= mips_optimize
;
5049 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
5050 coproc
? treg
: treg
+ 1,
5051 (int) BFD_RELOC_LO16
, AT
);
5052 mips_optimize
= hold_mips_optimize
;
5053 expr1
.X_add_number
-= 4;
5055 p
= frag_var (rs_machine_dependent
, 16 + gpdel
+ off
, 0,
5056 RELAX_ENCODE (24 + off
, 16 + gpdel
+ off
, gpdel
,
5057 8 + gpdel
+ off
, 1, 0),
5058 offset_expr
.X_add_symbol
, (long) 0,
5062 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
5065 macro_build (p
, &icnt
, &offset_expr
,
5066 mips_isa
< 3 ? "lw" : "ld",
5067 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
5069 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
5073 macro_build (p
, &icnt
, (expressionS
*) NULL
,
5074 mips_isa
< 3 ? "addu" : "daddu",
5075 "d,v,t", AT
, breg
, AT
);
5078 macro_build (p
, &icnt
, &expr1
, s
, fmt
,
5079 coproc
? treg
+ 1 : treg
,
5080 (int) BFD_RELOC_LO16
, AT
);
5082 expr1
.X_add_number
+= 4;
5084 /* Set mips_optimize to 2 to avoid inserting an undesired
5086 hold_mips_optimize
= mips_optimize
;
5088 macro_build (p
, &icnt
, &expr1
, s
, fmt
,
5089 coproc
? treg
: treg
+ 1,
5090 (int) BFD_RELOC_LO16
, AT
);
5091 mips_optimize
= hold_mips_optimize
;
5093 else if (mips_pic
== EMBEDDED_PIC
)
5095 /* If there is no base register, we use
5096 <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL)
5097 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_MIPS_GPREL)
5098 If we have a base register, we use
5100 <op> $treg,<sym>($at) (BFD_RELOC_MIPS_GPREL)
5101 <op> $treg+1,<sym>+4($at) (BFD_RELOC_MIPS_GPREL)
5110 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5111 mips_isa
< 3 ? "addu" : "daddu",
5112 "d,v,t", AT
, breg
, GP
);
5117 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
5118 coproc
? treg
+ 1 : treg
,
5119 (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
5120 offset_expr
.X_add_number
+= 4;
5121 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
5122 coproc
? treg
: treg
+ 1,
5123 (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
5139 assert (mips_isa
< 3);
5140 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
5141 (int) BFD_RELOC_LO16
, breg
);
5142 offset_expr
.X_add_number
+= 4;
5143 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
+ 1,
5144 (int) BFD_RELOC_LO16
, breg
);
5146 #ifdef LOSING_COMPILER
5152 as_warn ("Macro used $at after \".set noat\"");
5157 struct mips_cl_insn
*ip
;
5159 register int treg
, sreg
, dreg
, breg
;
5174 bfd_reloc_code_real_type r
;
5177 treg
= (ip
->insn_opcode
>> 16) & 0x1f;
5178 dreg
= (ip
->insn_opcode
>> 11) & 0x1f;
5179 sreg
= breg
= (ip
->insn_opcode
>> 21) & 0x1f;
5180 mask
= ip
->insn_mo
->mask
;
5182 expr1
.X_op
= O_constant
;
5183 expr1
.X_op_symbol
= NULL
;
5184 expr1
.X_add_symbol
= NULL
;
5185 expr1
.X_add_number
= 1;
5189 #endif /* LOSING_COMPILER */
5194 macro_build ((char *) NULL
, &icnt
, NULL
,
5195 dbl
? "dmultu" : "multu",
5197 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
5203 /* The MIPS assembler some times generates shifts and adds. I'm
5204 not trying to be that fancy. GCC should do this for us
5206 load_register (&icnt
, AT
, &imm_expr
, dbl
);
5207 macro_build ((char *) NULL
, &icnt
, NULL
,
5208 dbl
? "dmult" : "mult",
5210 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
5216 mips_emit_delays (true);
5218 mips_any_noreorder
= 1;
5219 macro_build ((char *) NULL
, &icnt
, NULL
,
5220 dbl
? "dmult" : "mult",
5222 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
5223 macro_build ((char *) NULL
, &icnt
, NULL
,
5224 dbl
? "dsra32" : "sra",
5225 "d,w,<", dreg
, dreg
, 31);
5226 macro_build ((char *) NULL
, &icnt
, NULL
, "mfhi", "d", AT
);
5228 macro_build ((char *) NULL
, &icnt
, NULL
, "tne", "s,t", dreg
, AT
);
5231 expr1
.X_add_number
= 8;
5232 macro_build ((char *) NULL
, &icnt
, &expr1
, "beq", "s,t,p", dreg
, AT
);
5233 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
5234 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 6);
5237 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
5243 mips_emit_delays (true);
5245 mips_any_noreorder
= 1;
5246 macro_build ((char *) NULL
, &icnt
, NULL
,
5247 dbl
? "dmultu" : "multu",
5249 macro_build ((char *) NULL
, &icnt
, NULL
, "mfhi", "d", AT
);
5250 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
5252 macro_build ((char *) NULL
, &icnt
, NULL
, "tne", "s,t", AT
, 0);
5255 expr1
.X_add_number
= 8;
5256 macro_build ((char *) NULL
, &icnt
, &expr1
, "beq", "s,t,p", AT
, 0);
5257 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
5258 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 6);
5264 macro_build ((char *) NULL
, &icnt
, NULL
, "subu", "d,v,t", AT
, 0, treg
);
5265 macro_build ((char *) NULL
, &icnt
, NULL
, "srlv", "d,t,s", AT
, sreg
, AT
);
5266 macro_build ((char *) NULL
, &icnt
, NULL
, "sllv", "d,t,s", dreg
, sreg
,
5268 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
5272 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", AT
, sreg
,
5273 (int) (imm_expr
.X_add_number
& 0x1f));
5274 macro_build ((char *) NULL
, &icnt
, NULL
, "srl", "d,w,<", dreg
, sreg
,
5275 (int) ((0 - imm_expr
.X_add_number
) & 0x1f));
5276 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
5280 macro_build ((char *) NULL
, &icnt
, NULL
, "subu", "d,v,t", AT
, 0, treg
);
5281 macro_build ((char *) NULL
, &icnt
, NULL
, "sllv", "d,t,s", AT
, sreg
, AT
);
5282 macro_build ((char *) NULL
, &icnt
, NULL
, "srlv", "d,t,s", dreg
, sreg
,
5284 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
5288 macro_build ((char *) NULL
, &icnt
, NULL
, "srl", "d,w,<", AT
, sreg
,
5289 (int) (imm_expr
.X_add_number
& 0x1f));
5290 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", dreg
, sreg
,
5291 (int) ((0 - imm_expr
.X_add_number
) & 0x1f));
5292 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
5296 assert (mips_isa
< 2);
5297 /* Even on a big endian machine $fn comes before $fn+1. We have
5298 to adjust when storing to memory. */
5299 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "swc1", "T,o(b)",
5300 target_big_endian
? treg
+ 1 : treg
,
5301 (int) BFD_RELOC_LO16
, breg
);
5302 offset_expr
.X_add_number
+= 4;
5303 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "swc1", "T,o(b)",
5304 target_big_endian
? treg
: treg
+ 1,
5305 (int) BFD_RELOC_LO16
, breg
);
5310 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
5311 treg
, (int) BFD_RELOC_LO16
);
5313 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
5314 sreg
, (int) BFD_RELOC_LO16
);
5317 macro_build ((char *) NULL
, &icnt
, NULL
, "xor", "d,v,t", dreg
,
5319 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
5320 dreg
, (int) BFD_RELOC_LO16
);
5325 if (imm_expr
.X_add_number
== 0)
5327 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
5328 sreg
, (int) BFD_RELOC_LO16
);
5333 as_warn ("Instruction %s: result is always false",
5335 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
, 0);
5338 if (imm_expr
.X_add_number
>= 0 && imm_expr
.X_add_number
< 0x10000)
5340 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "xori", "t,r,i", dreg
,
5341 sreg
, (int) BFD_RELOC_LO16
);
5344 else if (imm_expr
.X_add_number
> -0x8000 && imm_expr
.X_add_number
< 0)
5346 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
5347 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
5348 mips_isa
< 3 ? "addiu" : "daddiu",
5349 "t,r,j", dreg
, sreg
,
5350 (int) BFD_RELOC_LO16
);
5355 load_register (&icnt
, AT
, &imm_expr
, 0);
5356 macro_build ((char *) NULL
, &icnt
, NULL
, "xor", "d,v,t", dreg
,
5360 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
, dreg
,
5361 (int) BFD_RELOC_LO16
);
5366 case M_SGE
: /* sreg >= treg <==> not (sreg < treg) */
5372 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, sreg
, treg
);
5373 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
5374 (int) BFD_RELOC_LO16
);
5377 case M_SGE_I
: /* sreg >= I <==> not (sreg < I) */
5379 if (imm_expr
.X_add_number
>= -0x8000 && imm_expr
.X_add_number
< 0x8000)
5381 macro_build ((char *) NULL
, &icnt
, &expr1
,
5382 mask
== M_SGE_I
? "slti" : "sltiu",
5383 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
5388 load_register (&icnt
, AT
, &imm_expr
, 0);
5389 macro_build ((char *) NULL
, &icnt
, NULL
,
5390 mask
== M_SGE_I
? "slt" : "sltu",
5391 "d,v,t", dreg
, sreg
, AT
);
5394 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
5395 (int) BFD_RELOC_LO16
);
5400 case M_SGT
: /* sreg > treg <==> treg < sreg */
5406 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, treg
, sreg
);
5409 case M_SGT_I
: /* sreg > I <==> I < sreg */
5415 load_register (&icnt
, AT
, &imm_expr
, 0);
5416 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, AT
, sreg
);
5419 case M_SLE
: /* sreg <= treg <==> treg >= sreg <==> not (treg < sreg) */
5425 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, treg
, sreg
);
5426 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
5427 (int) BFD_RELOC_LO16
);
5430 case M_SLE_I
: /* sreg <= I <==> I >= sreg <==> not (I < sreg) */
5436 load_register (&icnt
, AT
, &imm_expr
, 0);
5437 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, AT
, sreg
);
5438 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
5439 (int) BFD_RELOC_LO16
);
5443 if (imm_expr
.X_add_number
>= -0x8000 && imm_expr
.X_add_number
< 0x8000)
5445 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "slti", "t,r,j",
5446 dreg
, sreg
, (int) BFD_RELOC_LO16
);
5449 load_register (&icnt
, AT
, &imm_expr
, 0);
5450 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", dreg
, sreg
, AT
);
5454 if (imm_expr
.X_add_number
>= -0x8000 && imm_expr
.X_add_number
< 0x8000)
5456 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "sltiu", "t,r,j",
5457 dreg
, sreg
, (int) BFD_RELOC_LO16
);
5460 load_register (&icnt
, AT
, &imm_expr
, 0);
5461 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, sreg
,
5467 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0,
5470 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0,
5474 macro_build ((char *) NULL
, &icnt
, NULL
, "xor", "d,v,t", dreg
,
5476 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0,
5482 if (imm_expr
.X_add_number
== 0)
5484 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0,
5490 as_warn ("Instruction %s: result is always true",
5492 macro_build ((char *) NULL
, &icnt
, &expr1
,
5493 mips_isa
< 3 ? "addiu" : "daddiu",
5494 "t,r,j", dreg
, 0, (int) BFD_RELOC_LO16
);
5497 if (imm_expr
.X_add_number
>= 0 && imm_expr
.X_add_number
< 0x10000)
5499 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "xori", "t,r,i",
5500 dreg
, sreg
, (int) BFD_RELOC_LO16
);
5503 else if (imm_expr
.X_add_number
> -0x8000 && imm_expr
.X_add_number
< 0)
5505 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
5506 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
5507 mips_isa
< 3 ? "addiu" : "daddiu",
5508 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
5513 load_register (&icnt
, AT
, &imm_expr
, 0);
5514 macro_build ((char *) NULL
, &icnt
, NULL
, "xor", "d,v,t", dreg
,
5518 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0, dreg
);
5526 if (imm_expr
.X_add_number
> -0x8000 && imm_expr
.X_add_number
<= 0x8000)
5528 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
5529 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
5530 dbl
? "daddi" : "addi",
5531 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
5534 load_register (&icnt
, AT
, &imm_expr
, dbl
);
5535 macro_build ((char *) NULL
, &icnt
, NULL
,
5536 dbl
? "dsub" : "sub",
5537 "d,v,t", dreg
, sreg
, AT
);
5543 if (imm_expr
.X_add_number
> -0x8000 && imm_expr
.X_add_number
<= 0x8000)
5545 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
5546 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
5547 dbl
? "daddiu" : "addiu",
5548 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
5551 load_register (&icnt
, AT
, &imm_expr
, dbl
);
5552 macro_build ((char *) NULL
, &icnt
, NULL
,
5553 dbl
? "dsubu" : "subu",
5554 "d,v,t", dreg
, sreg
, AT
);
5575 load_register (&icnt
, AT
, &imm_expr
, 0);
5576 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "s,t", sreg
, AT
);
5581 assert (mips_isa
< 2);
5582 sreg
= (ip
->insn_opcode
>> 11) & 0x1f; /* floating reg */
5583 dreg
= (ip
->insn_opcode
>> 06) & 0x1f; /* floating reg */
5586 * Is the double cfc1 instruction a bug in the mips assembler;
5587 * or is there a reason for it?
5589 mips_emit_delays (true);
5591 mips_any_noreorder
= 1;
5592 macro_build ((char *) NULL
, &icnt
, NULL
, "cfc1", "t,G", treg
, 31);
5593 macro_build ((char *) NULL
, &icnt
, NULL
, "cfc1", "t,G", treg
, 31);
5594 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "");
5595 expr1
.X_add_number
= 3;
5596 macro_build ((char *) NULL
, &icnt
, &expr1
, "ori", "t,r,i", AT
, treg
,
5597 (int) BFD_RELOC_LO16
);
5598 expr1
.X_add_number
= 2;
5599 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", AT
, AT
,
5600 (int) BFD_RELOC_LO16
);
5601 macro_build ((char *) NULL
, &icnt
, NULL
, "ctc1", "t,G", AT
, 31);
5602 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "");
5603 macro_build ((char *) NULL
, &icnt
, NULL
,
5604 mask
== M_TRUNCWD
? "cvt.w.d" : "cvt.w.s", "D,S", dreg
, sreg
);
5605 macro_build ((char *) NULL
, &icnt
, NULL
, "ctc1", "t,G", treg
, 31);
5606 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "");
5616 if (offset_expr
.X_add_number
>= 0x7fff)
5617 as_bad ("operand overflow");
5618 /* avoid load delay */
5619 if (! target_big_endian
)
5620 offset_expr
.X_add_number
+= 1;
5621 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
5622 (int) BFD_RELOC_LO16
, breg
);
5623 if (! target_big_endian
)
5624 offset_expr
.X_add_number
-= 1;
5626 offset_expr
.X_add_number
+= 1;
5627 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lbu", "t,o(b)", AT
,
5628 (int) BFD_RELOC_LO16
, breg
);
5629 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", treg
, treg
, 8);
5630 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", treg
, treg
, AT
);
5643 if (offset_expr
.X_add_number
>= 0x8000 - off
)
5644 as_bad ("operand overflow");
5645 if (! target_big_endian
)
5646 offset_expr
.X_add_number
+= off
;
5647 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
5648 (int) BFD_RELOC_LO16
, breg
);
5649 if (! target_big_endian
)
5650 offset_expr
.X_add_number
-= off
;
5652 offset_expr
.X_add_number
+= off
;
5653 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s2
, "t,o(b)", treg
,
5654 (int) BFD_RELOC_LO16
, breg
);
5667 load_address (&icnt
, AT
, &offset_expr
);
5669 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5670 mips_isa
< 3 ? "addu" : "daddu",
5671 "d,v,t", AT
, AT
, breg
);
5672 if (! target_big_endian
)
5673 expr1
.X_add_number
= off
;
5675 expr1
.X_add_number
= 0;
5676 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, "t,o(b)", treg
,
5677 (int) BFD_RELOC_LO16
, AT
);
5678 if (! target_big_endian
)
5679 expr1
.X_add_number
= 0;
5681 expr1
.X_add_number
= off
;
5682 macro_build ((char *) NULL
, &icnt
, &expr1
, s2
, "t,o(b)", treg
,
5683 (int) BFD_RELOC_LO16
, AT
);
5688 load_address (&icnt
, AT
, &offset_expr
);
5690 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5691 mips_isa
< 3 ? "addu" : "daddu",
5692 "d,v,t", AT
, AT
, breg
);
5693 if (target_big_endian
)
5694 expr1
.X_add_number
= 0;
5695 macro_build ((char *) NULL
, &icnt
, &expr1
,
5696 mask
== M_ULH_A
? "lb" : "lbu", "t,o(b)", treg
,
5697 (int) BFD_RELOC_LO16
, AT
);
5698 if (target_big_endian
)
5699 expr1
.X_add_number
= 1;
5701 expr1
.X_add_number
= 0;
5702 macro_build ((char *) NULL
, &icnt
, &expr1
, "lbu", "t,o(b)", AT
,
5703 (int) BFD_RELOC_LO16
, AT
);
5704 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", treg
,
5706 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", treg
,
5711 if (offset_expr
.X_add_number
>= 0x7fff)
5712 as_bad ("operand overflow");
5713 if (target_big_endian
)
5714 offset_expr
.X_add_number
+= 1;
5715 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "sb", "t,o(b)", treg
,
5716 (int) BFD_RELOC_LO16
, breg
);
5717 macro_build ((char *) NULL
, &icnt
, NULL
, "srl", "d,w,<", AT
, treg
, 8);
5718 if (target_big_endian
)
5719 offset_expr
.X_add_number
-= 1;
5721 offset_expr
.X_add_number
+= 1;
5722 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "sb", "t,o(b)", AT
,
5723 (int) BFD_RELOC_LO16
, breg
);
5736 if (offset_expr
.X_add_number
>= 0x8000 - off
)
5737 as_bad ("operand overflow");
5738 if (! target_big_endian
)
5739 offset_expr
.X_add_number
+= off
;
5740 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
5741 (int) BFD_RELOC_LO16
, breg
);
5742 if (! target_big_endian
)
5743 offset_expr
.X_add_number
-= off
;
5745 offset_expr
.X_add_number
+= off
;
5746 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s2
, "t,o(b)", treg
,
5747 (int) BFD_RELOC_LO16
, breg
);
5760 load_address (&icnt
, AT
, &offset_expr
);
5762 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5763 mips_isa
< 3 ? "addu" : "daddu",
5764 "d,v,t", AT
, AT
, breg
);
5765 if (! target_big_endian
)
5766 expr1
.X_add_number
= off
;
5768 expr1
.X_add_number
= 0;
5769 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, "t,o(b)", treg
,
5770 (int) BFD_RELOC_LO16
, AT
);
5771 if (! target_big_endian
)
5772 expr1
.X_add_number
= 0;
5774 expr1
.X_add_number
= off
;
5775 macro_build ((char *) NULL
, &icnt
, &expr1
, s2
, "t,o(b)", treg
,
5776 (int) BFD_RELOC_LO16
, AT
);
5780 load_address (&icnt
, AT
, &offset_expr
);
5782 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5783 mips_isa
< 3 ? "addu" : "daddu",
5784 "d,v,t", AT
, AT
, breg
);
5785 if (! target_big_endian
)
5786 expr1
.X_add_number
= 0;
5787 macro_build ((char *) NULL
, &icnt
, &expr1
, "sb", "t,o(b)", treg
,
5788 (int) BFD_RELOC_LO16
, AT
);
5789 macro_build ((char *) NULL
, &icnt
, NULL
, "srl", "d,w,<", treg
,
5791 if (! target_big_endian
)
5792 expr1
.X_add_number
= 1;
5794 expr1
.X_add_number
= 0;
5795 macro_build ((char *) NULL
, &icnt
, &expr1
, "sb", "t,o(b)", treg
,
5796 (int) BFD_RELOC_LO16
, AT
);
5797 if (! target_big_endian
)
5798 expr1
.X_add_number
= 0;
5800 expr1
.X_add_number
= 1;
5801 macro_build ((char *) NULL
, &icnt
, &expr1
, "lbu", "t,o(b)", AT
,
5802 (int) BFD_RELOC_LO16
, AT
);
5803 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", treg
,
5805 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", treg
,
5810 as_bad ("Macro %s not implemented yet", ip
->insn_mo
->name
);
5814 as_warn ("Macro used $at after \".set noat\"");
5817 /* Implement macros in mips16 mode. */
5821 struct mips_cl_insn
*ip
;
5824 int xreg
, yreg
, zreg
, tmp
;
5828 const char *s
, *s2
, *s3
;
5830 mask
= ip
->insn_mo
->mask
;
5832 xreg
= (ip
->insn_opcode
>> MIPS16OP_SH_RX
) & MIPS16OP_MASK_RX
;
5833 yreg
= (ip
->insn_opcode
>> MIPS16OP_SH_RY
) & MIPS16OP_MASK_RY
;
5834 zreg
= (ip
->insn_opcode
>> MIPS16OP_SH_RZ
) & MIPS16OP_MASK_RZ
;
5838 expr1
.X_op
= O_constant
;
5839 expr1
.X_op_symbol
= NULL
;
5840 expr1
.X_add_symbol
= NULL
;
5841 expr1
.X_add_number
= 1;
5860 mips_emit_delays (true);
5862 mips_any_noreorder
= 1;
5863 macro_build ((char *) NULL
, &icnt
, NULL
,
5864 dbl
? "ddiv" : "div",
5865 "0,x,y", xreg
, yreg
);
5866 expr1
.X_add_number
= 2;
5867 macro_build ((char *) NULL
, &icnt
, &expr1
, "bnez", "x,p", yreg
);
5868 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "6", 7);
5869 /* FIXME: The normal code checks for of -1 / -0x80000000 here,
5870 since that causes an overflow. We should do that as well,
5871 but I don't see how to do the comparisons without a temporary
5874 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "x", zreg
);
5893 mips_emit_delays (true);
5895 mips_any_noreorder
= 1;
5896 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "0,x,y", xreg
, yreg
);
5897 expr1
.X_add_number
= 2;
5898 macro_build ((char *) NULL
, &icnt
, &expr1
, "bnez", "x,p", yreg
);
5899 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "6", 7);
5901 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "x", zreg
);
5909 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
5910 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
5911 dbl
? "daddiu" : "addiu",
5912 "y,x,4", yreg
, xreg
);
5916 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
5917 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "addiu",
5922 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
5923 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "daddiu",
5946 goto do_reverse_branch
;
5950 goto do_reverse_branch
;
5962 goto do_reverse_branch
;
5973 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s
, "x,y",
5975 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s2
, "p");
6002 goto do_addone_branch_i
;
6007 goto do_addone_branch_i
;
6022 goto do_addone_branch_i
;
6029 ++imm_expr
.X_add_number
;
6032 macro_build ((char *) NULL
, &icnt
, &imm_expr
, s
, s3
, xreg
);
6033 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s2
, "p");
6037 expr1
.X_add_number
= 0;
6038 macro_build ((char *) NULL
, &icnt
, &expr1
, "slti", "x,8", yreg
);
6040 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6041 "move", "y,X", xreg
, yreg
);
6042 expr1
.X_add_number
= 2;
6043 macro_build ((char *) NULL
, &icnt
, &expr1
, "bteqz", "p");
6044 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6045 "neg", "x,w", xreg
, xreg
);
6049 /* This routine assembles an instruction into its binary format. As a
6050 side effect, it sets one of the global variables imm_reloc or
6051 offset_reloc to the type of relocation to do if one of the operands
6052 is an address expression. */
6057 struct mips_cl_insn
*ip
;
6062 struct mips_opcode
*insn
;
6065 unsigned int lastregno
= 0;
6070 for (s
= str
; islower (*s
) || (*s
>= '0' && *s
<= '3') || *s
== '6' || *s
== '.'; ++s
)
6082 as_fatal ("Unknown opcode: `%s'", str
);
6084 if ((insn
= (struct mips_opcode
*) hash_find (op_hash
, str
)) == NULL
)
6086 insn_error
= "unrecognized opcode";
6094 assert (strcmp (insn
->name
, str
) == 0);
6096 if (insn
->pinfo
== INSN_MACRO
)
6097 insn_isa
= insn
->match
;
6098 else if ((insn
->pinfo
& INSN_ISA
) == INSN_ISA2
)
6100 else if ((insn
->pinfo
& INSN_ISA
) == INSN_ISA3
)
6102 else if ((insn
->pinfo
& INSN_ISA
) == INSN_ISA4
)
6107 if (insn_isa
> mips_isa
6108 || ((insn
->pinfo
& INSN_ISA
) == INSN_4650
6110 || ((insn
->pinfo
& INSN_ISA
) == INSN_4010
6112 || ((insn
->pinfo
& INSN_ISA
) == INSN_4100
6115 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
]
6116 && strcmp (insn
->name
, insn
[1].name
) == 0)
6121 if (insn_isa
<= mips_isa
)
6122 insn_error
= "opcode not supported on this processor";
6125 static char buf
[100];
6127 sprintf (buf
, "opcode requires -mips%d or greater", insn_isa
);
6134 ip
->insn_opcode
= insn
->match
;
6135 for (args
= insn
->args
;; ++args
)
6141 case '\0': /* end of args */
6154 ip
->insn_opcode
|= lastregno
<< 21;
6159 ip
->insn_opcode
|= lastregno
<< 16;
6163 ip
->insn_opcode
|= lastregno
<< 11;
6169 /* handle optional base register.
6170 Either the base register is omitted or
6171 we must have a left paren. */
6172 /* this is dependent on the next operand specifier
6173 is a 'b' for base register */
6174 assert (args
[1] == 'b');
6178 case ')': /* these must match exactly */
6183 case '<': /* must be at least one digit */
6185 * According to the manual, if the shift amount is greater
6186 * than 31 or less than 0 the the shift amount should be
6187 * mod 32. In reality the mips assembler issues an error.
6188 * We issue a warning and mask out all but the low 5 bits.
6190 my_getExpression (&imm_expr
, s
);
6191 check_absolute_expr (ip
, &imm_expr
);
6192 if ((unsigned long) imm_expr
.X_add_number
> 31)
6194 as_warn ("Improper shift amount (%ld)",
6195 (long) imm_expr
.X_add_number
);
6196 imm_expr
.X_add_number
= imm_expr
.X_add_number
& 0x1f;
6198 ip
->insn_opcode
|= imm_expr
.X_add_number
<< 6;
6199 imm_expr
.X_op
= O_absent
;
6203 case '>': /* shift amount minus 32 */
6204 my_getExpression (&imm_expr
, s
);
6205 check_absolute_expr (ip
, &imm_expr
);
6206 if ((unsigned long) imm_expr
.X_add_number
< 32
6207 || (unsigned long) imm_expr
.X_add_number
> 63)
6209 ip
->insn_opcode
|= (imm_expr
.X_add_number
- 32) << 6;
6210 imm_expr
.X_op
= O_absent
;
6214 case 'k': /* cache code */
6215 case 'h': /* prefx code */
6216 my_getExpression (&imm_expr
, s
);
6217 check_absolute_expr (ip
, &imm_expr
);
6218 if ((unsigned long) imm_expr
.X_add_number
> 31)
6220 as_warn ("Invalid value for `%s' (%lu)",
6222 (unsigned long) imm_expr
.X_add_number
);
6223 imm_expr
.X_add_number
&= 0x1f;
6226 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_CACHE
;
6228 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_PREFX
;
6229 imm_expr
.X_op
= O_absent
;
6233 case 'c': /* break code */
6234 my_getExpression (&imm_expr
, s
);
6235 check_absolute_expr (ip
, &imm_expr
);
6236 if ((unsigned) imm_expr
.X_add_number
> 1023)
6237 as_warn ("Illegal break code (%ld)",
6238 (long) imm_expr
.X_add_number
);
6239 ip
->insn_opcode
|= imm_expr
.X_add_number
<< 16;
6240 imm_expr
.X_op
= O_absent
;
6244 case 'B': /* syscall code */
6245 my_getExpression (&imm_expr
, s
);
6246 check_absolute_expr (ip
, &imm_expr
);
6247 if ((unsigned) imm_expr
.X_add_number
> 0xfffff)
6248 as_warn ("Illegal syscall code (%ld)",
6249 (long) imm_expr
.X_add_number
);
6250 ip
->insn_opcode
|= imm_expr
.X_add_number
<< 6;
6251 imm_expr
.X_op
= O_absent
;
6255 case 'C': /* Coprocessor code */
6256 my_getExpression (&imm_expr
, s
);
6257 check_absolute_expr (ip
, &imm_expr
);
6258 if ((unsigned long) imm_expr
.X_add_number
>= (1<<25))
6260 as_warn ("Coproccesor code > 25 bits (%ld)",
6261 (long) imm_expr
.X_add_number
);
6262 imm_expr
.X_add_number
&= ((1<<25) - 1);
6264 ip
->insn_opcode
|= imm_expr
.X_add_number
;
6265 imm_expr
.X_op
= O_absent
;
6269 case 'b': /* base register */
6270 case 'd': /* destination register */
6271 case 's': /* source register */
6272 case 't': /* target register */
6273 case 'r': /* both target and source */
6274 case 'v': /* both dest and source */
6275 case 'w': /* both dest and target */
6276 case 'E': /* coprocessor target register */
6277 case 'G': /* coprocessor destination register */
6278 case 'x': /* ignore register name */
6279 case 'z': /* must be zero register */
6293 while (isdigit (*s
));
6295 as_bad ("Invalid register number (%d)", regno
);
6297 else if (*args
== 'E' || *args
== 'G')
6301 if (s
[1] == 'f' && s
[2] == 'p')
6306 else if (s
[1] == 's' && s
[2] == 'p')
6311 else if (s
[1] == 'g' && s
[2] == 'p')
6316 else if (s
[1] == 'a' && s
[2] == 't')
6321 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '0')
6326 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '1')
6338 as_warn ("Used $at without \".set noat\"");
6344 if (c
== 'r' || c
== 'v' || c
== 'w')
6351 /* 'z' only matches $0. */
6352 if (c
== 'z' && regno
!= 0)
6360 ip
->insn_opcode
|= regno
<< 21;
6364 ip
->insn_opcode
|= regno
<< 11;
6369 ip
->insn_opcode
|= regno
<< 16;
6372 /* This case exists because on the r3000 trunc
6373 expands into a macro which requires a gp
6374 register. On the r6000 or r4000 it is
6375 assembled into a single instruction which
6376 ignores the register. Thus the insn version
6377 is MIPS_ISA2 and uses 'x', and the macro
6378 version is MIPS_ISA1 and uses 't'. */
6381 /* This case is for the div instruction, which
6382 acts differently if the destination argument
6383 is $0. This only matches $0, and is checked
6384 outside the switch. */
6395 ip
->insn_opcode
|= lastregno
<< 21;
6398 ip
->insn_opcode
|= lastregno
<< 16;
6403 case 'D': /* floating point destination register */
6404 case 'S': /* floating point source register */
6405 case 'T': /* floating point target register */
6406 case 'R': /* floating point source register */
6410 if (s
[0] == '$' && s
[1] == 'f' && isdigit (s
[2]))
6420 while (isdigit (*s
));
6423 as_bad ("Invalid float register number (%d)", regno
);
6425 if ((regno
& 1) != 0
6427 && ! (strcmp (str
, "mtc1") == 0
6428 || strcmp (str
, "mfc1") == 0
6429 || strcmp (str
, "lwc1") == 0
6430 || strcmp (str
, "swc1") == 0
6431 || strcmp (str
, "l.s") == 0
6432 || strcmp (str
, "s.s") == 0))
6433 as_warn ("Float register should be even, was %d",
6441 if (c
== 'V' || c
== 'W')
6451 ip
->insn_opcode
|= regno
<< 6;
6455 ip
->insn_opcode
|= regno
<< 11;
6459 ip
->insn_opcode
|= regno
<< 16;
6462 ip
->insn_opcode
|= regno
<< 21;
6471 ip
->insn_opcode
|= lastregno
<< 11;
6474 ip
->insn_opcode
|= lastregno
<< 16;
6480 my_getExpression (&imm_expr
, s
);
6481 if (imm_expr
.X_op
!= O_big
6482 && imm_expr
.X_op
!= O_constant
)
6483 insn_error
= "absolute expression required";
6488 my_getExpression (&offset_expr
, s
);
6489 imm_reloc
= BFD_RELOC_32
;
6501 unsigned char temp
[8];
6503 unsigned int length
;
6508 /* These only appear as the last operand in an
6509 instruction, and every instruction that accepts
6510 them in any variant accepts them in all variants.
6511 This means we don't have to worry about backing out
6512 any changes if the instruction does not match.
6514 The difference between them is the size of the
6515 floating point constant and where it goes. For 'F'
6516 and 'L' the constant is 64 bits; for 'f' and 'l' it
6517 is 32 bits. Where the constant is placed is based
6518 on how the MIPS assembler does things:
6521 f -- immediate value
6524 The .lit4 and .lit8 sections are only used if
6525 permitted by the -G argument.
6527 When generating embedded PIC code, we use the
6528 .lit8 section but not the .lit4 section (we can do
6529 .lit4 inline easily; we need to put .lit8
6530 somewhere in the data segment, and using .lit8
6531 permits the linker to eventually combine identical
6534 f64
= *args
== 'F' || *args
== 'L';
6536 save_in
= input_line_pointer
;
6537 input_line_pointer
= s
;
6538 err
= md_atof (f64
? 'd' : 'f', (char *) temp
, &len
);
6540 s
= input_line_pointer
;
6541 input_line_pointer
= save_in
;
6542 if (err
!= NULL
&& *err
!= '\0')
6544 as_bad ("Bad floating point constant: %s", err
);
6545 memset (temp
, '\0', sizeof temp
);
6546 length
= f64
? 8 : 4;
6549 assert (length
== (f64
? 8 : 4));
6553 && (! USE_GLOBAL_POINTER_OPT
6554 || mips_pic
== EMBEDDED_PIC
6555 || g_switch_value
< 4)
6558 imm_expr
.X_op
= O_constant
;
6559 if (! target_big_endian
)
6560 imm_expr
.X_add_number
=
6561 (((((((int) temp
[3] << 8)
6566 imm_expr
.X_add_number
=
6567 (((((((int) temp
[0] << 8)
6574 const char *newname
;
6577 /* Switch to the right section. */
6579 subseg
= now_subseg
;
6582 default: /* unused default case avoids warnings. */
6584 newname
= RDATA_SECTION_NAME
;
6585 if (USE_GLOBAL_POINTER_OPT
&& g_switch_value
>= 8)
6589 newname
= RDATA_SECTION_NAME
;
6592 assert (!USE_GLOBAL_POINTER_OPT
6593 || g_switch_value
>= 4);
6597 new_seg
= subseg_new (newname
, (subsegT
) 0);
6598 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
6599 bfd_set_section_flags (stdoutput
, new_seg
,
6604 frag_align (*args
== 'l' ? 2 : 3, 0);
6605 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
6606 record_alignment (new_seg
, 4);
6608 record_alignment (new_seg
, *args
== 'l' ? 2 : 3);
6610 as_bad ("Can't use floating point insn in this section");
6612 /* Set the argument to the current address in the
6614 offset_expr
.X_op
= O_symbol
;
6615 offset_expr
.X_add_symbol
=
6616 symbol_new ("L0\001", now_seg
,
6617 (valueT
) frag_now_fix (), frag_now
);
6618 offset_expr
.X_add_number
= 0;
6620 /* Put the floating point number into the section. */
6621 p
= frag_more ((int) length
);
6622 memcpy (p
, temp
, length
);
6624 /* Switch back to the original section. */
6625 subseg_set (seg
, subseg
);
6630 case 'i': /* 16 bit unsigned immediate */
6631 case 'j': /* 16 bit signed immediate */
6632 imm_reloc
= BFD_RELOC_LO16
;
6633 c
= my_getSmallExpression (&imm_expr
, s
);
6638 if (imm_expr
.X_op
== O_constant
)
6639 imm_expr
.X_add_number
=
6640 (imm_expr
.X_add_number
>> 16) & 0xffff;
6643 imm_reloc
= BFD_RELOC_HI16_S
;
6644 imm_unmatched_hi
= true;
6647 imm_reloc
= BFD_RELOC_HI16
;
6652 if ((c
== '\0' && imm_expr
.X_op
!= O_constant
)
6653 || ((imm_expr
.X_add_number
< 0
6654 || imm_expr
.X_add_number
>= 0x10000)
6655 && imm_expr
.X_op
== O_constant
))
6657 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
6658 !strcmp (insn
->name
, insn
[1].name
))
6660 if (imm_expr
.X_op
!= O_constant
6661 && imm_expr
.X_op
!= O_big
)
6662 insn_error
= "absolute expression required";
6664 as_bad ("16 bit expression not in range 0..65535");
6672 /* The upper bound should be 0x8000, but
6673 unfortunately the MIPS assembler accepts numbers
6674 from 0x8000 to 0xffff and sign extends them, and
6675 we want to be compatible. We only permit this
6676 extended range for an instruction which does not
6677 provide any further alternates, since those
6678 alternates may handle other cases. People should
6679 use the numbers they mean, rather than relying on
6680 a mysterious sign extension. */
6681 more
= (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
6682 strcmp (insn
->name
, insn
[1].name
) == 0);
6687 if ((c
== '\0' && imm_expr
.X_op
!= O_constant
)
6688 || ((imm_expr
.X_add_number
< -0x8000
6689 || imm_expr
.X_add_number
>= max
)
6690 && imm_expr
.X_op
== O_constant
)
6692 && imm_expr
.X_add_number
< 0
6694 && imm_expr
.X_unsigned
6695 && sizeof (imm_expr
.X_add_number
) <= 4))
6699 if (imm_expr
.X_op
!= O_constant
6700 && imm_expr
.X_op
!= O_big
)
6701 insn_error
= "absolute expression required";
6703 as_bad ("16 bit expression not in range -32768..32767");
6709 case 'o': /* 16 bit offset */
6710 c
= my_getSmallExpression (&offset_expr
, s
);
6712 /* If this value won't fit into a 16 bit offset, then go
6713 find a macro that will generate the 32 bit offset
6714 code pattern. As a special hack, we accept the
6715 difference of two local symbols as a constant. This
6716 is required to suppose embedded PIC switches, which
6717 use an instruction which looks like
6718 lw $4,$L12-$LS12($4)
6719 The problem with handling this in a more general
6720 fashion is that the macro function doesn't expect to
6721 see anything which can be handled in a single
6722 constant instruction. */
6724 && (offset_expr
.X_op
!= O_constant
6725 || offset_expr
.X_add_number
>= 0x8000
6726 || offset_expr
.X_add_number
< -0x8000)
6727 && (mips_pic
!= EMBEDDED_PIC
6728 || offset_expr
.X_op
!= O_subtract
6729 || now_seg
!= text_section
6730 || (S_GET_SEGMENT (offset_expr
.X_op_symbol
)
6734 offset_reloc
= BFD_RELOC_LO16
;
6735 if (c
== 'h' || c
== 'H')
6737 assert (offset_expr
.X_op
== O_constant
);
6738 offset_expr
.X_add_number
=
6739 (offset_expr
.X_add_number
>> 16) & 0xffff;
6744 case 'p': /* pc relative offset */
6745 offset_reloc
= BFD_RELOC_16_PCREL_S2
;
6746 my_getExpression (&offset_expr
, s
);
6750 case 'u': /* upper 16 bits */
6751 c
= my_getSmallExpression (&imm_expr
, s
);
6752 if (imm_expr
.X_op
== O_constant
6753 && (imm_expr
.X_add_number
< 0
6754 || imm_expr
.X_add_number
>= 0x10000))
6755 as_bad ("lui expression not in range 0..65535");
6756 imm_reloc
= BFD_RELOC_LO16
;
6761 if (imm_expr
.X_op
== O_constant
)
6762 imm_expr
.X_add_number
=
6763 (imm_expr
.X_add_number
>> 16) & 0xffff;
6766 imm_reloc
= BFD_RELOC_HI16_S
;
6767 imm_unmatched_hi
= true;
6770 imm_reloc
= BFD_RELOC_HI16
;
6776 case 'a': /* 26 bit address */
6777 my_getExpression (&offset_expr
, s
);
6779 offset_reloc
= BFD_RELOC_MIPS_JMP
;
6782 case 'N': /* 3 bit branch condition code */
6783 case 'M': /* 3 bit compare condition code */
6784 if (strncmp (s
, "$fcc", 4) != 0)
6794 while (isdigit (*s
));
6796 as_bad ("invalid condition code register $fcc%d", regno
);
6798 ip
->insn_opcode
|= regno
<< OP_SH_BCC
;
6800 ip
->insn_opcode
|= regno
<< OP_SH_CCC
;
6804 fprintf (stderr
, "bad char = '%c'\n", *args
);
6809 /* Args don't match. */
6810 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
6811 !strcmp (insn
->name
, insn
[1].name
))
6817 insn_error
= "illegal operands";
6822 /* This routine assembles an instruction into its binary format when
6823 assembling for the mips16. As a side effect, it sets one of the
6824 global variables imm_reloc or offset_reloc to the type of
6825 relocation to do if one of the operands is an address expression.
6826 It also sets mips16_small and mips16_ext if the user explicitly
6827 requested a small or extended instruction. */
6832 struct mips_cl_insn
*ip
;
6836 struct mips_opcode
*insn
;
6839 unsigned int lastregno
= 0;
6844 mips16_small
= false;
6847 for (s
= str
; islower (*s
); ++s
)
6859 if (s
[1] == 't' && s
[2] == ' ')
6862 mips16_small
= true;
6866 else if (s
[1] == 'e' && s
[2] == ' ')
6875 insn_error
= "unknown opcode";
6879 if (! mips16_autoextend
&& ! mips16_ext
)
6880 mips16_small
= true;
6882 if ((insn
= (struct mips_opcode
*) hash_find (mips16_op_hash
, str
)) == NULL
)
6884 insn_error
= "unrecognized opcode";
6891 assert (strcmp (insn
->name
, str
) == 0);
6894 ip
->insn_opcode
= insn
->match
;
6895 ip
->use_extend
= false;
6896 imm_expr
.X_op
= O_absent
;
6897 imm_reloc
= BFD_RELOC_UNUSED
;
6898 offset_expr
.X_op
= O_absent
;
6899 offset_reloc
= BFD_RELOC_UNUSED
;
6900 for (args
= insn
->args
; 1; ++args
)
6907 /* In this switch statement we call break if we did not find
6908 a match, continue if we did find a match, or return if we
6917 /* Stuff the immediate value in now, if we can. */
6918 if (imm_expr
.X_op
== O_constant
6919 && imm_reloc
> BFD_RELOC_UNUSED
6920 && insn
->pinfo
!= INSN_MACRO
)
6922 mips16_immed ((char *) NULL
, 0,
6923 imm_reloc
- BFD_RELOC_UNUSED
,
6924 imm_expr
.X_add_number
, true, mips16_small
,
6925 mips16_ext
, &ip
->insn_opcode
,
6926 &ip
->use_extend
, &ip
->extend
);
6927 imm_expr
.X_op
= O_absent
;
6928 imm_reloc
= BFD_RELOC_UNUSED
;
6942 ip
->insn_opcode
|= lastregno
<< MIPS16OP_SH_RX
;
6945 ip
->insn_opcode
|= lastregno
<< MIPS16OP_SH_RY
;
6961 ip
->insn_opcode
|= lastregno
<< MIPS16OP_SH_RX
;
6963 ip
->insn_opcode
|= lastregno
<< MIPS16OP_SH_RY
;
6990 while (isdigit (*s
));
6993 as_bad ("invalid register number (%d)", regno
);
6999 if (s
[1] == 'f' && s
[2] == 'p')
7004 else if (s
[1] == 's' && s
[2] == 'p')
7009 else if (s
[1] == 'g' && s
[2] == 'p')
7014 else if (s
[1] == 'a' && s
[2] == 't')
7019 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '0')
7024 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '1')
7037 if (c
== 'v' || c
== 'w')
7039 regno
= mips16_to_32_reg_map
[lastregno
];
7053 regno
= mips32_to_16_reg_map
[regno
];
7058 regno
= ILLEGAL_REG
;
7063 regno
= ILLEGAL_REG
;
7068 regno
= ILLEGAL_REG
;
7073 if (regno
== AT
&& ! mips_noat
)
7074 as_warn ("used $at without \".set noat\"");
7081 if (regno
== ILLEGAL_REG
)
7088 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_RX
;
7092 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_RY
;
7095 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_RZ
;
7098 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_MOVE32Z
;
7104 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_REGR32
;
7107 regno
= ((regno
& 7) << 2) | ((regno
& 0x18) >> 3);
7108 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_REG32R
;
7118 if (strncmp (s
, "$pc", 3) == 0)
7141 if (s
[0] == '$' && isdigit (s
[1]))
7143 /* Looks like a register name. */
7151 /* It looks like the expression was omitted before a
7152 register indirection, which means that the
7153 expression is implicitly zero. We still set up
7154 imm_expr, so that we handle explicit extensions
7156 imm_expr
.X_op
= O_constant
;
7157 imm_expr
.X_add_number
= 0;
7158 imm_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
7162 my_getExpression (&imm_expr
, s
);
7163 /* We need to relax this instruction. */
7164 imm_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
7173 /* We use offset_reloc rather than imm_reloc for the PC
7174 relative operands. This lets macros with both
7175 immediate and address operands work correctly. */
7176 if (s
[0] == '$' && isdigit (s
[1]))
7178 /* Looks like a register name. */
7181 my_getExpression (&offset_expr
, s
);
7182 /* We need to relax this instruction. */
7183 offset_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
7187 case '6': /* break code */
7188 my_getExpression (&imm_expr
, s
);
7189 check_absolute_expr (ip
, &imm_expr
);
7190 if ((unsigned long) imm_expr
.X_add_number
> 63)
7192 as_warn ("Invalid value for `%s' (%lu)",
7194 (unsigned long) imm_expr
.X_add_number
);
7195 imm_expr
.X_add_number
&= 0x3f;
7197 ip
->insn_opcode
|= imm_expr
.X_add_number
<< MIPS16OP_SH_IMM6
;
7198 imm_expr
.X_op
= O_absent
;
7202 case 'a': /* 26 bit address */
7203 my_getExpression (&offset_expr
, s
);
7205 offset_reloc
= BFD_RELOC_MIPS16_JMP
;
7206 ip
->insn_opcode
<<= 16;
7209 case 'l': /* register list for entry macro */
7210 case 'L': /* register list for exit macro */
7220 int freg
, reg1
, reg2
;
7222 while (*s
== ' ' || *s
== ',')
7226 as_bad ("can't parse register list");
7238 while (isdigit (*s
))
7260 as_bad ("invalid register list");
7265 while (isdigit (*s
))
7272 if (freg
&& reg1
== 0 && reg2
== 0 && c
== 'L')
7277 else if (freg
&& reg1
== 0 && reg2
== 1 && c
== 'L')
7282 else if (reg1
== 4 && reg2
>= 4 && reg2
<= 7 && c
!= 'L')
7283 mask
|= (reg2
- 3) << 3;
7284 else if (reg1
== 16 && reg2
>= 16 && reg2
<= 17)
7285 mask
|= (reg2
- 15) << 1;
7286 else if (reg1
== 31 && reg2
== 31)
7290 as_bad ("invalid register list");
7294 /* The mask is filled in in the opcode table for the
7295 benefit of the disassembler. We remove it before
7296 applying the actual mask. */
7297 ip
->insn_opcode
&= ~ ((7 << 3) << MIPS16OP_SH_IMM6
);
7298 ip
->insn_opcode
|= mask
<< MIPS16OP_SH_IMM6
;
7308 /* Args don't match. */
7309 if (insn
+ 1 < &mips16_opcodes
[bfd_mips16_num_opcodes
] &&
7310 strcmp (insn
->name
, insn
[1].name
) == 0)
7317 insn_error
= "illegal operands";
7323 /* This structure holds information we know about a mips16 immediate
7326 struct mips16_immed_operand
7328 /* The type code used in the argument string in the opcode table. */
7330 /* The number of bits in the short form of the opcode. */
7332 /* The number of bits in the extended form of the opcode. */
7334 /* The amount by which the short form is shifted when it is used;
7335 for example, the sw instruction has a shift count of 2. */
7337 /* The amount by which the short form is shifted when it is stored
7338 into the instruction code. */
7340 /* Non-zero if the short form is unsigned. */
7342 /* Non-zero if the extended form is unsigned. */
7344 /* Non-zero if the value is PC relative. */
7348 /* The mips16 immediate operand types. */
7350 static const struct mips16_immed_operand mips16_immed_operands
[] =
7352 { '<', 3, 5, 0, MIPS16OP_SH_RZ
, 1, 1, 0 },
7353 { '>', 3, 5, 0, MIPS16OP_SH_RX
, 1, 1, 0 },
7354 { '[', 3, 6, 0, MIPS16OP_SH_RZ
, 1, 1, 0 },
7355 { ']', 3, 6, 0, MIPS16OP_SH_RX
, 1, 1, 0 },
7356 { '4', 4, 15, 0, MIPS16OP_SH_IMM4
, 0, 0, 0 },
7357 { '5', 5, 16, 0, MIPS16OP_SH_IMM5
, 1, 0, 0 },
7358 { 'H', 5, 16, 1, MIPS16OP_SH_IMM5
, 1, 0, 0 },
7359 { 'W', 5, 16, 2, MIPS16OP_SH_IMM5
, 1, 0, 0 },
7360 { 'D', 5, 16, 3, MIPS16OP_SH_IMM5
, 1, 0, 0 },
7361 { 'j', 5, 16, 0, MIPS16OP_SH_IMM5
, 0, 0, 0 },
7362 { '8', 8, 16, 0, MIPS16OP_SH_IMM8
, 1, 0, 0 },
7363 { 'V', 8, 16, 2, MIPS16OP_SH_IMM8
, 1, 0, 0 },
7364 { 'C', 8, 16, 3, MIPS16OP_SH_IMM8
, 1, 0, 0 },
7365 { 'U', 8, 16, 0, MIPS16OP_SH_IMM8
, 1, 1, 0 },
7366 { 'k', 8, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 0 },
7367 { 'K', 8, 16, 3, MIPS16OP_SH_IMM8
, 0, 0, 0 },
7368 { 'p', 8, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 1 },
7369 { 'q', 11, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 1 },
7370 { 'A', 8, 16, 2, MIPS16OP_SH_IMM8
, 1, 0, 1 },
7371 { 'B', 5, 16, 3, MIPS16OP_SH_IMM5
, 1, 0, 1 },
7372 { 'E', 5, 16, 2, MIPS16OP_SH_IMM5
, 1, 0, 1 }
7375 #define MIPS16_NUM_IMMED \
7376 (sizeof mips16_immed_operands / sizeof mips16_immed_operands[0])
7378 /* Handle a mips16 instruction with an immediate value. This or's the
7379 small immediate value into *INSN. It sets *USE_EXTEND to indicate
7380 whether an extended value is needed; if one is needed, it sets
7381 *EXTEND to the value. The argument type is TYPE. The value is VAL.
7382 If SMALL is true, an unextended opcode was explicitly requested.
7383 If EXT is true, an extended opcode was explicitly requested. If
7384 WARN is true, warn if EXT does not match reality. */
7387 mips16_immed (file
, line
, type
, val
, warn
, small
, ext
, insn
, use_extend
,
7396 unsigned long *insn
;
7397 boolean
*use_extend
;
7398 unsigned short *extend
;
7400 register const struct mips16_immed_operand
*op
;
7401 int mintiny
, maxtiny
;
7404 op
= mips16_immed_operands
;
7405 while (op
->type
!= type
)
7408 assert (op
< mips16_immed_operands
+ MIPS16_NUM_IMMED
);
7413 if (type
== '<' || type
== '>' || type
== '[' || type
== ']')
7416 maxtiny
= 1 << op
->nbits
;
7421 maxtiny
= (1 << op
->nbits
) - 1;
7426 mintiny
= - (1 << (op
->nbits
- 1));
7427 maxtiny
= (1 << (op
->nbits
- 1)) - 1;
7430 /* Branch offsets have an implicit 0 in the lowest bit. */
7431 if (type
== 'p' || type
== 'q')
7434 if ((val
& ((1 << op
->shift
) - 1)) != 0
7435 || val
< (mintiny
<< op
->shift
)
7436 || val
> (maxtiny
<< op
->shift
))
7441 if (warn
&& ext
&& ! needext
)
7442 as_warn_where (file
, line
, "extended operand requested but not required");
7443 if (small
&& needext
)
7444 as_bad_where (file
, line
, "invalid unextended operand value");
7446 if (small
|| (! ext
&& ! needext
))
7450 *use_extend
= false;
7451 insnval
= ((val
>> op
->shift
) & ((1 << op
->nbits
) - 1));
7452 insnval
<<= op
->op_shift
;
7457 long minext
, maxext
;
7463 maxext
= (1 << op
->extbits
) - 1;
7467 minext
= - (1 << (op
->extbits
- 1));
7468 maxext
= (1 << (op
->extbits
- 1)) - 1;
7470 if (val
< minext
|| val
> maxext
)
7471 as_bad_where (file
, line
,
7472 "operand value out of range for instruction");
7475 if (op
->extbits
== 16)
7477 extval
= ((val
>> 11) & 0x1f) | (val
& 0x7e0);
7480 else if (op
->extbits
== 15)
7482 extval
= ((val
>> 11) & 0xf) | (val
& 0x7f0);
7487 extval
= ((val
& 0x1f) << 6) | (val
& 0x20);
7491 *extend
= (unsigned short) extval
;
7500 my_getSmallExpression (ep
, str
)
7511 ((str
[1] == 'h' && str
[2] == 'i')
7512 || (str
[1] == 'H' && str
[2] == 'I')
7513 || (str
[1] == 'l' && str
[2] == 'o'))
7525 * A small expression may be followed by a base register.
7526 * Scan to the end of this operand, and then back over a possible
7527 * base register. Then scan the small expression up to that
7528 * point. (Based on code in sparc.c...)
7530 for (sp
= str
; *sp
&& *sp
!= ','; sp
++)
7532 if (sp
- 4 >= str
&& sp
[-1] == RP
)
7534 if (isdigit (sp
[-2]))
7536 for (sp
-= 3; sp
>= str
&& isdigit (*sp
); sp
--)
7538 if (*sp
== '$' && sp
> str
&& sp
[-1] == LP
)
7544 else if (sp
- 5 >= str
7547 && ((sp
[-3] == 'f' && sp
[-2] == 'p')
7548 || (sp
[-3] == 's' && sp
[-2] == 'p')
7549 || (sp
[-3] == 'g' && sp
[-2] == 'p')
7550 || (sp
[-3] == 'a' && sp
[-2] == 't')))
7556 /* no expression means zero offset */
7559 /* %xx(reg) is an error */
7560 ep
->X_op
= O_absent
;
7565 ep
->X_op
= O_constant
;
7568 ep
->X_add_symbol
= NULL
;
7569 ep
->X_op_symbol
= NULL
;
7570 ep
->X_add_number
= 0;
7575 my_getExpression (ep
, str
);
7582 my_getExpression (ep
, str
);
7583 return c
; /* => %hi or %lo encountered */
7587 my_getExpression (ep
, str
)
7593 save_in
= input_line_pointer
;
7594 input_line_pointer
= str
;
7596 expr_end
= input_line_pointer
;
7597 input_line_pointer
= save_in
;
7600 /* Turn a string in input_line_pointer into a floating point constant
7601 of type type, and store the appropriate bytes in *litP. The number
7602 of LITTLENUMS emitted is stored in *sizeP . An error message is
7603 returned, or NULL on OK. */
7606 md_atof (type
, litP
, sizeP
)
7612 LITTLENUM_TYPE words
[4];
7628 return "bad call to md_atof";
7631 t
= atof_ieee (input_line_pointer
, type
, words
);
7633 input_line_pointer
= t
;
7637 if (! target_big_endian
)
7639 for (i
= prec
- 1; i
>= 0; i
--)
7641 md_number_to_chars (litP
, (valueT
) words
[i
], 2);
7647 for (i
= 0; i
< prec
; i
++)
7649 md_number_to_chars (litP
, (valueT
) words
[i
], 2);
7658 md_number_to_chars (buf
, val
, n
)
7663 if (target_big_endian
)
7664 number_to_chars_bigendian (buf
, val
, n
);
7666 number_to_chars_littleendian (buf
, val
, n
);
7669 CONST
char *md_shortopts
= "O::g::G:";
7671 struct option md_longopts
[] = {
7672 #define OPTION_MIPS1 (OPTION_MD_BASE + 1)
7673 {"mips0", no_argument
, NULL
, OPTION_MIPS1
},
7674 {"mips1", no_argument
, NULL
, OPTION_MIPS1
},
7675 #define OPTION_MIPS2 (OPTION_MD_BASE + 2)
7676 {"mips2", no_argument
, NULL
, OPTION_MIPS2
},
7677 #define OPTION_MIPS3 (OPTION_MD_BASE + 3)
7678 {"mips3", no_argument
, NULL
, OPTION_MIPS3
},
7679 #define OPTION_MIPS4 (OPTION_MD_BASE + 4)
7680 {"mips4", no_argument
, NULL
, OPTION_MIPS4
},
7681 #define OPTION_MCPU (OPTION_MD_BASE + 5)
7682 {"mcpu", required_argument
, NULL
, OPTION_MCPU
},
7683 #define OPTION_MEMBEDDED_PIC (OPTION_MD_BASE + 6)
7684 {"membedded-pic", no_argument
, NULL
, OPTION_MEMBEDDED_PIC
},
7685 #define OPTION_TRAP (OPTION_MD_BASE + 9)
7686 {"trap", no_argument
, NULL
, OPTION_TRAP
},
7687 {"no-break", no_argument
, NULL
, OPTION_TRAP
},
7688 #define OPTION_BREAK (OPTION_MD_BASE + 10)
7689 {"break", no_argument
, NULL
, OPTION_BREAK
},
7690 {"no-trap", no_argument
, NULL
, OPTION_BREAK
},
7691 #define OPTION_EB (OPTION_MD_BASE + 11)
7692 {"EB", no_argument
, NULL
, OPTION_EB
},
7693 #define OPTION_EL (OPTION_MD_BASE + 12)
7694 {"EL", no_argument
, NULL
, OPTION_EL
},
7695 #define OPTION_M4650 (OPTION_MD_BASE + 13)
7696 {"m4650", no_argument
, NULL
, OPTION_M4650
},
7697 #define OPTION_NO_M4650 (OPTION_MD_BASE + 14)
7698 {"no-m4650", no_argument
, NULL
, OPTION_NO_M4650
},
7699 #define OPTION_M4010 (OPTION_MD_BASE + 15)
7700 {"m4010", no_argument
, NULL
, OPTION_M4010
},
7701 #define OPTION_NO_M4010 (OPTION_MD_BASE + 16)
7702 {"no-m4010", no_argument
, NULL
, OPTION_NO_M4010
},
7703 #define OPTION_M4100 (OPTION_MD_BASE + 17)
7704 {"m4100", no_argument
, NULL
, OPTION_M4100
},
7705 #define OPTION_NO_M4100 (OPTION_MD_BASE + 18)
7706 {"no-m4100", no_argument
, NULL
, OPTION_NO_M4100
},
7707 #define OPTION_MIPS16 (OPTION_MD_BASE + 22)
7708 {"mips16", no_argument
, NULL
, OPTION_MIPS16
},
7709 #define OPTION_NO_MIPS16 (OPTION_MD_BASE + 23)
7710 {"no-mips16", no_argument
, NULL
, OPTION_NO_MIPS16
},
7712 #define OPTION_CALL_SHARED (OPTION_MD_BASE + 7)
7713 #define OPTION_NON_SHARED (OPTION_MD_BASE + 8)
7714 #define OPTION_XGOT (OPTION_MD_BASE + 19)
7715 #define OPTION_32 (OPTION_MD_BASE + 20)
7716 #define OPTION_64 (OPTION_MD_BASE + 21)
7718 {"KPIC", no_argument
, NULL
, OPTION_CALL_SHARED
},
7719 {"xgot", no_argument
, NULL
, OPTION_XGOT
},
7720 {"call_shared", no_argument
, NULL
, OPTION_CALL_SHARED
},
7721 {"non_shared", no_argument
, NULL
, OPTION_NON_SHARED
},
7722 {"32", no_argument
, NULL
, OPTION_32
},
7723 {"64", no_argument
, NULL
, OPTION_64
},
7726 {NULL
, no_argument
, NULL
, 0}
7728 size_t md_longopts_size
= sizeof(md_longopts
);
7731 md_parse_option (c
, arg
)
7746 target_big_endian
= 1;
7750 target_big_endian
= 0;
7754 if (arg
&& arg
[1] == '0')
7764 mips_debug
= atoi (arg
);
7765 /* When the MIPS assembler sees -g or -g2, it does not do
7766 optimizations which limit full symbolic debugging. We take
7767 that to be equivalent to -O0. */
7768 if (mips_debug
== 2)
7800 /* Identify the processor type */
7802 if (strcmp (p
, "default") == 0
7803 || strcmp (p
, "DEFAULT") == 0)
7809 /* We need to cope with the various "vr" prefixes for the 4300
7811 if (*p
== 'v' || *p
== 'V')
7817 if (*p
== 'r' || *p
== 'R')
7824 if (strcmp (p
, "10000") == 0
7825 || strcmp (p
, "10k") == 0
7826 || strcmp (p
, "10K") == 0)
7831 if (strcmp (p
, "2000") == 0
7832 || strcmp (p
, "2k") == 0
7833 || strcmp (p
, "2K") == 0)
7838 if (strcmp (p
, "3000") == 0
7839 || strcmp (p
, "3k") == 0
7840 || strcmp (p
, "3K") == 0)
7845 if (strcmp (p
, "4000") == 0
7846 || strcmp (p
, "4k") == 0
7847 || strcmp (p
, "4K") == 0)
7849 else if (strcmp (p
, "4100") == 0)
7855 else if (strcmp (p
, "4300") == 0)
7857 else if (strcmp (p
, "4400") == 0)
7859 else if (strcmp (p
, "4600") == 0)
7861 else if (strcmp (p
, "4650") == 0)
7867 else if (strcmp (p
, "4010") == 0)
7876 if (strcmp (p
, "5000") == 0
7877 || strcmp (p
, "5k") == 0
7878 || strcmp (p
, "5K") == 0)
7883 if (strcmp (p
, "6000") == 0
7884 || strcmp (p
, "6k") == 0
7885 || strcmp (p
, "6K") == 0)
7890 if (strcmp (p
, "8000") == 0
7891 || strcmp (p
, "8k") == 0
7892 || strcmp (p
, "8K") == 0)
7897 if (strcmp (p
, "orion") == 0)
7902 if (sv
&& mips_cpu
!= 4300 && mips_cpu
!= 4100 && mips_cpu
!= 5000)
7904 as_bad ("ignoring invalid leading 'v' in -mcpu=%s switch", arg
);
7910 as_bad ("invalid architecture -mcpu=%s", arg
);
7921 case OPTION_NO_M4650
:
7929 case OPTION_NO_M4010
:
7937 case OPTION_NO_M4100
:
7943 mips_no_prev_insn ();
7946 case OPTION_NO_MIPS16
:
7948 mips_no_prev_insn ();
7951 case OPTION_MEMBEDDED_PIC
:
7952 mips_pic
= EMBEDDED_PIC
;
7953 if (USE_GLOBAL_POINTER_OPT
&& g_switch_seen
)
7955 as_bad ("-G may not be used with embedded PIC code");
7958 g_switch_value
= 0x7fffffff;
7961 /* When generating ELF code, we permit -KPIC and -call_shared to
7962 select SVR4_PIC, and -non_shared to select no PIC. This is
7963 intended to be compatible with Irix 5. */
7964 case OPTION_CALL_SHARED
:
7965 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
7967 as_bad ("-call_shared is supported only for ELF format");
7970 mips_pic
= SVR4_PIC
;
7971 if (g_switch_seen
&& g_switch_value
!= 0)
7973 as_bad ("-G may not be used with SVR4 PIC code");
7979 case OPTION_NON_SHARED
:
7980 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
7982 as_bad ("-non_shared is supported only for ELF format");
7988 /* The -xgot option tells the assembler to use 32 offsets when
7989 accessing the got in SVR4_PIC mode. It is for Irix
7996 if (! USE_GLOBAL_POINTER_OPT
)
7998 as_bad ("-G is not supported for this configuration");
8001 else if (mips_pic
== SVR4_PIC
|| mips_pic
== EMBEDDED_PIC
)
8003 as_bad ("-G may not be used with SVR4 or embedded PIC code");
8007 g_switch_value
= atoi (arg
);
8011 /* The -32 and -64 options tell the assembler to output the 32
8012 bit or the 64 bit MIPS ELF format. */
8019 const char **list
, **l
;
8021 list
= bfd_target_list ();
8022 for (l
= list
; *l
!= NULL
; l
++)
8023 if (strcmp (*l
, "elf64-bigmips") == 0
8024 || strcmp (*l
, "elf64-littlemips") == 0)
8027 as_fatal ("No compiled in support for 64 bit object file format");
8041 md_show_usage (stream
)
8046 -membedded-pic generate embedded position independent code\n\
8047 -EB generate big endian output\n\
8048 -EL generate little endian output\n\
8049 -g, -g2 do not remove uneeded NOPs or swap branches\n\
8050 -G NUM allow referencing objects up to NUM bytes\n\
8051 implicitly with the gp register [default 8]\n");
8053 -mips1, -mcpu=r{2,3}000 generate code for r2000 and r3000\n\
8054 -mips2, -mcpu=r6000 generate code for r6000\n\
8055 -mips3, -mcpu=r4000 generate code for r4000\n\
8056 -mips4, -mcpu=r8000 generate code for r8000\n\
8057 -mcpu=vr4300 generate code for vr4300\n\
8058 -mcpu=vr4100 generate code for vr4100\n\
8059 -m4650 permit R4650 instructions\n\
8060 -no-m4650 do not permit R4650 instructions\n\
8061 -m4010 permit R4010 instructions\n\
8062 -no-m4010 do not permit R4010 instructions\n\
8063 -m4100 permit VR4100 instructions\n\
8064 -no-m4100 do not permit VR4100 instructions\n");
8066 -mips16 generate mips16 instructions\n\
8067 -no-mips16 do not generate mips16 instructions\n");
8069 -O0 remove unneeded NOPs, do not swap branches\n\
8070 -O remove unneeded NOPs and swap branches\n\
8071 --trap, --no-break trap exception on div by 0 and mult overflow\n\
8072 --break, --no-trap break exception on div by 0 and mult overflow\n");
8075 -KPIC, -call_shared generate SVR4 position independent code\n\
8076 -non_shared do not generate position independent code\n\
8077 -xgot assume a 32 bit GOT\n\
8078 -32 create 32 bit object file (default)\n\
8079 -64 create 64 bit object file\n");
8084 md_pcrel_from (fixP
)
8087 if (OUTPUT_FLAVOR
!= bfd_target_aout_flavour
8088 && fixP
->fx_addsy
!= (symbolS
*) NULL
8089 && ! S_IS_DEFINED (fixP
->fx_addsy
))
8091 /* This makes a branch to an undefined symbol be a branch to the
8092 current location. */
8096 /* return the address of the delay slot */
8097 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
8100 /* This is called by emit_expr via TC_CONS_FIX_NEW when creating a
8101 reloc for a cons. We could use the definition there, except that
8102 we want to handle 64 bit relocs specially. */
8105 cons_fix_new_mips (frag
, where
, nbytes
, exp
)
8108 unsigned int nbytes
;
8112 /* If we are assembling in 32 bit mode, turn an 8 byte reloc into a
8114 if (nbytes
== 8 && ! mips_64
)
8116 if (target_big_endian
)
8122 if (nbytes
!= 2 && nbytes
!= 4 && nbytes
!= 8)
8123 as_bad ("Unsupported reloc size %d", nbytes
);
8125 fix_new_exp (frag_now
, where
, (int) nbytes
, exp
, 0,
8128 : (nbytes
== 4 ? BFD_RELOC_32
: BFD_RELOC_64
)));
8131 /* Sort any unmatched HI16_S relocs so that they immediately precede
8132 the corresponding LO reloc. This is called before md_apply_fix and
8133 tc_gen_reloc. Unmatched HI16_S relocs can only be generated by
8134 explicit use of the %hi modifier. */
8139 struct mips_hi_fixup
*l
;
8141 for (l
= mips_hi_fixup_list
; l
!= NULL
; l
= l
->next
)
8143 segment_info_type
*seginfo
;
8146 assert (l
->fixp
->fx_r_type
== BFD_RELOC_HI16_S
);
8148 /* Check quickly whether the next fixup happens to be a matching
8150 if (l
->fixp
->fx_next
!= NULL
8151 && l
->fixp
->fx_next
->fx_r_type
== BFD_RELOC_LO16
8152 && l
->fixp
->fx_addsy
== l
->fixp
->fx_next
->fx_addsy
8153 && l
->fixp
->fx_offset
== l
->fixp
->fx_next
->fx_offset
)
8156 /* Look through the fixups for this segment for a matching %lo.
8157 When we find one, move the %hi just in front of it. We do
8158 this in two passes. In the first pass, we try to find a
8159 unique %lo. In the second pass, we permit multiple %hi
8160 relocs for a single %lo (this is a GNU extension). */
8161 seginfo
= seg_info (l
->seg
);
8162 for (pass
= 0; pass
< 2; pass
++)
8167 for (f
= seginfo
->fix_root
; f
!= NULL
; f
= f
->fx_next
)
8169 /* Check whether this is a %lo fixup which matches l->fixp. */
8170 if (f
->fx_r_type
== BFD_RELOC_LO16
8171 && f
->fx_addsy
== l
->fixp
->fx_addsy
8172 && f
->fx_offset
== l
->fixp
->fx_offset
8175 || prev
->fx_r_type
!= BFD_RELOC_HI16_S
8176 || prev
->fx_addsy
!= f
->fx_addsy
8177 || prev
->fx_offset
!= f
->fx_offset
))
8181 /* Move l->fixp before f. */
8182 for (pf
= &seginfo
->fix_root
;
8184 pf
= &(*pf
)->fx_next
)
8185 assert (*pf
!= NULL
);
8187 *pf
= l
->fixp
->fx_next
;
8189 l
->fixp
->fx_next
= f
;
8191 seginfo
->fix_root
= l
->fixp
;
8193 prev
->fx_next
= l
->fixp
;
8205 as_warn_where (l
->fixp
->fx_file
, l
->fixp
->fx_line
,
8206 "Unmatched %%hi reloc");
8211 /* When generating embedded PIC code we need to use a special
8212 relocation to represent the difference of two symbols in the .text
8213 section (switch tables use a difference of this sort). See
8214 include/coff/mips.h for details. This macro checks whether this
8215 fixup requires the special reloc. */
8216 #define SWITCH_TABLE(fixp) \
8217 ((fixp)->fx_r_type == BFD_RELOC_32 \
8218 && (fixp)->fx_addsy != NULL \
8219 && (fixp)->fx_subsy != NULL \
8220 && S_GET_SEGMENT ((fixp)->fx_addsy) == text_section \
8221 && S_GET_SEGMENT ((fixp)->fx_subsy) == text_section)
8223 /* When generating embedded PIC code we must keep all PC relative
8224 relocations, in case the linker has to relax a call. We also need
8225 to keep relocations for switch table entries. */
8229 mips_force_relocation (fixp
)
8232 return (mips_pic
== EMBEDDED_PIC
8234 || SWITCH_TABLE (fixp
)
8235 || fixp
->fx_r_type
== BFD_RELOC_PCREL_HI16_S
8236 || fixp
->fx_r_type
== BFD_RELOC_PCREL_LO16
));
8239 /* Apply a fixup to the object file. */
8242 md_apply_fix (fixP
, valueP
)
8249 assert (fixP
->fx_size
== 4
8250 || fixP
->fx_r_type
== BFD_RELOC_16
8251 || fixP
->fx_r_type
== BFD_RELOC_64
);
8255 /* If we aren't adjusting this fixup to be against the section
8256 symbol, we need to adjust the value. */
8258 if (fixP
->fx_addsy
!= NULL
8259 && OUTPUT_FLAVOR
== bfd_target_elf_flavour
8260 && S_GET_OTHER (fixP
->fx_addsy
) == STO_MIPS16
)
8262 value
-= S_GET_VALUE (fixP
->fx_addsy
);
8263 if (value
!= 0 && ! fixP
->fx_pcrel
)
8265 /* In this case, the bfd_install_relocation routine will
8266 incorrectly add the symbol value back in. We just want
8267 the addend to appear in the object file. */
8268 value
-= S_GET_VALUE (fixP
->fx_addsy
);
8273 fixP
->fx_addnumber
= value
; /* Remember value for tc_gen_reloc */
8275 if (fixP
->fx_addsy
== NULL
&& ! fixP
->fx_pcrel
)
8278 switch (fixP
->fx_r_type
)
8280 case BFD_RELOC_MIPS_JMP
:
8281 case BFD_RELOC_HI16
:
8282 case BFD_RELOC_HI16_S
:
8283 case BFD_RELOC_MIPS_GPREL
:
8284 case BFD_RELOC_MIPS_LITERAL
:
8285 case BFD_RELOC_MIPS_CALL16
:
8286 case BFD_RELOC_MIPS_GOT16
:
8287 case BFD_RELOC_MIPS_GPREL32
:
8288 case BFD_RELOC_MIPS_GOT_HI16
:
8289 case BFD_RELOC_MIPS_GOT_LO16
:
8290 case BFD_RELOC_MIPS_CALL_HI16
:
8291 case BFD_RELOC_MIPS_CALL_LO16
:
8293 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
8294 "Invalid PC relative reloc");
8295 /* Nothing needed to do. The value comes from the reloc entry */
8298 case BFD_RELOC_MIPS16_JMP
:
8299 /* We currently always generate a reloc against a symbol, which
8300 means that we don't want an addend even if the symbol is
8302 fixP
->fx_addnumber
= 0;
8305 case BFD_RELOC_PCREL_HI16_S
:
8306 /* The addend for this is tricky if it is internal, so we just
8307 do everything here rather than in bfd_perform_relocation. */
8308 if ((fixP
->fx_addsy
->bsym
->flags
& BSF_SECTION_SYM
) == 0)
8310 /* For an external symbol adjust by the address to make it
8311 pcrel_offset. We use the address of the RELLO reloc
8312 which follows this one. */
8313 value
+= (fixP
->fx_next
->fx_frag
->fr_address
8314 + fixP
->fx_next
->fx_where
);
8319 buf
= (unsigned char *) fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
8320 if (target_big_endian
)
8322 md_number_to_chars (buf
, value
, 2);
8325 case BFD_RELOC_PCREL_LO16
:
8326 /* The addend for this is tricky if it is internal, so we just
8327 do everything here rather than in bfd_perform_relocation. */
8328 if ((fixP
->fx_addsy
->bsym
->flags
& BSF_SECTION_SYM
) == 0)
8329 value
+= fixP
->fx_frag
->fr_address
+ fixP
->fx_where
;
8330 buf
= (unsigned char *) fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
8331 if (target_big_endian
)
8333 md_number_to_chars (buf
, value
, 2);
8337 /* This is handled like BFD_RELOC_32, but we output a sign
8338 extended value if we are only 32 bits. */
8340 || (mips_pic
== EMBEDDED_PIC
&& SWITCH_TABLE (fixP
)))
8342 if (8 <= sizeof (valueT
))
8343 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
,
8350 w1
= w2
= fixP
->fx_where
;
8351 if (target_big_endian
)
8355 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ w1
, value
, 4);
8356 if ((value
& 0x80000000) != 0)
8360 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ w2
, hiv
, 4);
8366 /* If we are deleting this reloc entry, we must fill in the
8367 value now. This can happen if we have a .word which is not
8368 resolved when it appears but is later defined. We also need
8369 to fill in the value if this is an embedded PIC switch table
8372 || (mips_pic
== EMBEDDED_PIC
&& SWITCH_TABLE (fixP
)))
8373 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
,
8378 /* If we are deleting this reloc entry, we must fill in the
8380 assert (fixP
->fx_size
== 2);
8382 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
,
8386 case BFD_RELOC_LO16
:
8387 /* When handling an embedded PIC switch statement, we can wind
8388 up deleting a LO16 reloc. See the 'o' case in mips_ip. */
8391 if (value
< -0x8000 || value
> 0x7fff)
8392 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
8393 "relocation overflow");
8394 buf
= (unsigned char *) fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
8395 if (target_big_endian
)
8397 md_number_to_chars (buf
, value
, 2);
8401 case BFD_RELOC_16_PCREL_S2
:
8403 * We need to save the bits in the instruction since fixup_segment()
8404 * might be deleting the relocation entry (i.e., a branch within
8405 * the current segment).
8407 if ((value
& 0x3) != 0)
8408 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
8409 "Branch to odd address (%lx)", value
);
8412 /* update old instruction data */
8413 buf
= (unsigned char *) (fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
);
8414 if (target_big_endian
)
8415 insn
= (buf
[0] << 24) | (buf
[1] << 16) | (buf
[2] << 8) | buf
[3];
8417 insn
= (buf
[3] << 24) | (buf
[2] << 16) | (buf
[1] << 8) | buf
[0];
8419 if (value
>= -0x8000 && value
< 0x8000)
8420 insn
|= value
& 0xffff;
8423 /* The branch offset is too large. If this is an
8424 unconditional branch, and we are not generating PIC code,
8425 we can convert it to an absolute jump instruction. */
8426 if (mips_pic
== NO_PIC
8428 && fixP
->fx_frag
->fr_address
>= text_section
->vma
8429 && (fixP
->fx_frag
->fr_address
8430 < text_section
->vma
+ text_section
->_raw_size
)
8431 && ((insn
& 0xffff0000) == 0x10000000 /* beq $0,$0 */
8432 || (insn
& 0xffff0000) == 0x04010000 /* bgez $0 */
8433 || (insn
& 0xffff0000) == 0x04110000)) /* bgezal $0 */
8435 if ((insn
& 0xffff0000) == 0x04110000) /* bgezal $0 */
8436 insn
= 0x0c000000; /* jal */
8438 insn
= 0x08000000; /* j */
8439 fixP
->fx_r_type
= BFD_RELOC_MIPS_JMP
;
8441 fixP
->fx_addsy
= section_symbol (text_section
);
8442 fixP
->fx_addnumber
= (value
<< 2) + md_pcrel_from (fixP
);
8446 /* FIXME. It would be possible in principle to handle
8447 conditional branches which overflow. They could be
8448 transformed into a branch around a jump. This would
8449 require setting up variant frags for each different
8450 branch type. The native MIPS assembler attempts to
8451 handle these cases, but it appears to do it
8453 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
8454 "Relocation overflow");
8458 md_number_to_chars ((char *) buf
, (valueT
) insn
, 4);
8473 const struct mips_opcode
*p
;
8474 int treg
, sreg
, dreg
, shamt
;
8479 for (i
= 0; i
< NUMOPCODES
; ++i
)
8481 p
= &mips_opcodes
[i
];
8482 if (((oc
& p
->mask
) == p
->match
) && (p
->pinfo
!= INSN_MACRO
))
8484 printf ("%08lx %s\t", oc
, p
->name
);
8485 treg
= (oc
>> 16) & 0x1f;
8486 sreg
= (oc
>> 21) & 0x1f;
8487 dreg
= (oc
>> 11) & 0x1f;
8488 shamt
= (oc
>> 6) & 0x1f;
8490 for (args
= p
->args
;; ++args
)
8501 printf ("%c", *args
);
8505 assert (treg
== sreg
);
8506 printf ("$%d,$%d", treg
, sreg
);
8511 printf ("$%d", dreg
);
8516 printf ("$%d", treg
);
8520 printf ("0x%x", treg
);
8525 printf ("$%d", sreg
);
8529 printf ("0x%08lx", oc
& 0x1ffffff);
8541 printf ("$%d", shamt
);
8552 printf ("%08lx UNDEFINED\n", oc
);
8563 name
= input_line_pointer
;
8564 c
= get_symbol_end ();
8565 p
= (symbolS
*) symbol_find_or_make (name
);
8566 *input_line_pointer
= c
;
8570 /* Align the current frag to a given power of two. The MIPS assembler
8571 also automatically adjusts any preceding label. */
8574 mips_align (to
, fill
, label
)
8579 mips_emit_delays (false);
8580 frag_align (to
, fill
);
8581 record_alignment (now_seg
, to
);
8584 assert (S_GET_SEGMENT (label
) == now_seg
);
8585 label
->sy_frag
= frag_now
;
8586 S_SET_VALUE (label
, (valueT
) frag_now_fix ());
8590 /* Align to a given power of two. .align 0 turns off the automatic
8591 alignment used by the data creating pseudo-ops. */
8598 register long temp_fill
;
8599 long max_alignment
= 15;
8603 o Note that the assembler pulls down any immediately preceeding label
8604 to the aligned address.
8605 o It's not documented but auto alignment is reinstated by
8606 a .align pseudo instruction.
8607 o Note also that after auto alignment is turned off the mips assembler
8608 issues an error on attempt to assemble an improperly aligned data item.
8613 temp
= get_absolute_expression ();
8614 if (temp
> max_alignment
)
8615 as_bad ("Alignment too large: %d. assumed.", temp
= max_alignment
);
8618 as_warn ("Alignment negative: 0 assumed.");
8621 if (*input_line_pointer
== ',')
8623 input_line_pointer
++;
8624 temp_fill
= get_absolute_expression ();
8631 mips_align (temp
, (int) temp_fill
,
8632 insn_labels
!= NULL
? insn_labels
->label
: NULL
);
8639 demand_empty_rest_of_line ();
8643 mips_flush_pending_output ()
8645 mips_emit_delays (false);
8646 mips_clear_insn_labels ();
8655 /* When generating embedded PIC code, we only use the .text, .lit8,
8656 .sdata and .sbss sections. We change the .data and .rdata
8657 pseudo-ops to use .sdata. */
8658 if (mips_pic
== EMBEDDED_PIC
8659 && (sec
== 'd' || sec
== 'r'))
8662 mips_emit_delays (false);
8672 subseg_set (bss_section
, (subsegT
) get_absolute_expression ());
8673 demand_empty_rest_of_line ();
8677 if (USE_GLOBAL_POINTER_OPT
)
8679 seg
= subseg_new (RDATA_SECTION_NAME
,
8680 (subsegT
) get_absolute_expression ());
8681 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
8683 bfd_set_section_flags (stdoutput
, seg
,
8689 if (strcmp (TARGET_OS
, "elf") != 0)
8690 bfd_set_section_alignment (stdoutput
, seg
, 4);
8692 demand_empty_rest_of_line ();
8696 as_bad ("No read only data section in this object file format");
8697 demand_empty_rest_of_line ();
8703 if (USE_GLOBAL_POINTER_OPT
)
8705 seg
= subseg_new (".sdata", (subsegT
) get_absolute_expression ());
8706 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
8708 bfd_set_section_flags (stdoutput
, seg
,
8709 SEC_ALLOC
| SEC_LOAD
| SEC_RELOC
8711 if (strcmp (TARGET_OS
, "elf") != 0)
8712 bfd_set_section_alignment (stdoutput
, seg
, 4);
8714 demand_empty_rest_of_line ();
8719 as_bad ("Global pointers not supported; recompile -G 0");
8720 demand_empty_rest_of_line ();
8729 mips_enable_auto_align ()
8740 label
= insn_labels
!= NULL
? insn_labels
->label
: NULL
;
8741 mips_emit_delays (false);
8742 if (log_size
> 0 && auto_align
)
8743 mips_align (log_size
, 0, label
);
8744 mips_clear_insn_labels ();
8745 cons (1 << log_size
);
8754 label
= insn_labels
!= NULL
? insn_labels
->label
: NULL
;
8756 mips_emit_delays (false);
8760 mips_align (3, 0, label
);
8762 mips_align (2, 0, label
);
8764 mips_clear_insn_labels ();
8769 /* Handle .globl. We need to override it because on Irix 5 you are
8772 where foo is an undefined symbol, to mean that foo should be
8773 considered to be the address of a function. */
8784 name
= input_line_pointer
;
8785 c
= get_symbol_end ();
8786 symbolP
= symbol_find_or_make (name
);
8787 *input_line_pointer
= c
;
8790 /* On Irix 5, every global symbol that is not explicitly labelled as
8791 being a function is apparently labelled as being an object. */
8794 if (! is_end_of_line
[(unsigned char) *input_line_pointer
])
8799 secname
= input_line_pointer
;
8800 c
= get_symbol_end ();
8801 sec
= bfd_get_section_by_name (stdoutput
, secname
);
8803 as_bad ("%s: no such section", secname
);
8804 *input_line_pointer
= c
;
8806 if (sec
!= NULL
&& (sec
->flags
& SEC_CODE
) != 0)
8807 flag
= BSF_FUNCTION
;
8810 symbolP
->bsym
->flags
|= flag
;
8812 S_SET_EXTERNAL (symbolP
);
8813 demand_empty_rest_of_line ();
8823 opt
= input_line_pointer
;
8824 c
= get_symbol_end ();
8828 /* FIXME: What does this mean? */
8830 else if (strncmp (opt
, "pic", 3) == 0)
8838 mips_pic
= SVR4_PIC
;
8840 as_bad (".option pic%d not supported", i
);
8842 if (USE_GLOBAL_POINTER_OPT
&& mips_pic
== SVR4_PIC
)
8844 if (g_switch_seen
&& g_switch_value
!= 0)
8845 as_warn ("-G may not be used with SVR4 PIC code");
8847 bfd_set_gp_size (stdoutput
, 0);
8851 as_warn ("Unrecognized option \"%s\"", opt
);
8853 *input_line_pointer
= c
;
8854 demand_empty_rest_of_line ();
8861 char *name
= input_line_pointer
, ch
;
8863 while (!is_end_of_line
[(unsigned char) *input_line_pointer
])
8864 input_line_pointer
++;
8865 ch
= *input_line_pointer
;
8866 *input_line_pointer
= '\0';
8868 if (strcmp (name
, "reorder") == 0)
8872 prev_insn_unreordered
= 1;
8873 prev_prev_insn_unreordered
= 1;
8877 else if (strcmp (name
, "noreorder") == 0)
8879 mips_emit_delays (true);
8881 mips_any_noreorder
= 1;
8883 else if (strcmp (name
, "at") == 0)
8887 else if (strcmp (name
, "noat") == 0)
8891 else if (strcmp (name
, "macro") == 0)
8893 mips_warn_about_macros
= 0;
8895 else if (strcmp (name
, "nomacro") == 0)
8897 if (mips_noreorder
== 0)
8898 as_bad ("`noreorder' must be set before `nomacro'");
8899 mips_warn_about_macros
= 1;
8901 else if (strcmp (name
, "move") == 0 || strcmp (name
, "novolatile") == 0)
8905 else if (strcmp (name
, "nomove") == 0 || strcmp (name
, "volatile") == 0)
8909 else if (strcmp (name
, "bopt") == 0)
8913 else if (strcmp (name
, "nobopt") == 0)
8917 else if (strcmp (name
, "mips16") == 0
8918 || strcmp (name
, "MIPS-16") == 0)
8920 else if (strcmp (name
, "nomips16") == 0
8921 || strcmp (name
, "noMIPS-16") == 0)
8923 else if (strncmp (name
, "mips", 4) == 0)
8927 /* Permit the user to change the ISA on the fly. Needless to
8928 say, misuse can cause serious problems. */
8929 isa
= atoi (name
+ 4);
8931 mips_isa
= file_mips_isa
;
8932 else if (isa
< 1 || isa
> 4)
8933 as_bad ("unknown ISA level");
8937 else if (strcmp (name
, "autoextend") == 0)
8938 mips16_autoextend
= 1;
8939 else if (strcmp (name
, "noautoextend") == 0)
8940 mips16_autoextend
= 0;
8943 as_warn ("Tried to set unrecognized symbol: %s\n", name
);
8945 *input_line_pointer
= ch
;
8946 demand_empty_rest_of_line ();
8949 /* Handle the .abicalls pseudo-op. I believe this is equivalent to
8950 .option pic2. It means to generate SVR4 PIC calls. */
8956 mips_pic
= SVR4_PIC
;
8957 if (USE_GLOBAL_POINTER_OPT
)
8959 if (g_switch_seen
&& g_switch_value
!= 0)
8960 as_warn ("-G may not be used with SVR4 PIC code");
8963 bfd_set_gp_size (stdoutput
, 0);
8964 demand_empty_rest_of_line ();
8967 /* Handle the .cpload pseudo-op. This is used when generating SVR4
8968 PIC code. It sets the $gp register for the function based on the
8969 function address, which is in the register named in the argument.
8970 This uses a relocation against _gp_disp, which is handled specially
8971 by the linker. The result is:
8972 lui $gp,%hi(_gp_disp)
8973 addiu $gp,$gp,%lo(_gp_disp)
8974 addu $gp,$gp,.cpload argument
8975 The .cpload argument is normally $25 == $t9. */
8984 /* If we are not generating SVR4 PIC code, .cpload is ignored. */
8985 if (mips_pic
!= SVR4_PIC
)
8991 /* .cpload should be a in .set noreorder section. */
8992 if (mips_noreorder
== 0)
8993 as_warn (".cpload not in noreorder section");
8996 ex
.X_add_symbol
= symbol_find_or_make ("_gp_disp");
8997 ex
.X_op_symbol
= NULL
;
8998 ex
.X_add_number
= 0;
9000 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
9001 ex
.X_add_symbol
->bsym
->flags
|= BSF_OBJECT
;
9003 macro_build_lui ((char *) NULL
, &icnt
, &ex
, GP
);
9004 macro_build ((char *) NULL
, &icnt
, &ex
, "addiu", "t,r,j", GP
, GP
,
9005 (int) BFD_RELOC_LO16
);
9007 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "addu", "d,v,t",
9008 GP
, GP
, tc_get_register (0));
9010 demand_empty_rest_of_line ();
9013 /* Handle the .cprestore pseudo-op. This stores $gp into a given
9014 offset from $sp. The offset is remembered, and after making a PIC
9015 call $gp is restored from that location. */
9018 s_cprestore (ignore
)
9024 /* If we are not generating SVR4 PIC code, .cprestore is ignored. */
9025 if (mips_pic
!= SVR4_PIC
)
9031 mips_cprestore_offset
= get_absolute_expression ();
9033 ex
.X_op
= O_constant
;
9034 ex
.X_add_symbol
= NULL
;
9035 ex
.X_op_symbol
= NULL
;
9036 ex
.X_add_number
= mips_cprestore_offset
;
9038 macro_build ((char *) NULL
, &icnt
, &ex
,
9039 mips_isa
< 3 ? "sw" : "sd",
9040 "t,o(b)", GP
, (int) BFD_RELOC_LO16
, SP
);
9042 demand_empty_rest_of_line ();
9045 /* Handle the .gpword pseudo-op. This is used when generating PIC
9046 code. It generates a 32 bit GP relative reloc. */
9056 /* When not generating PIC code, this is treated as .word. */
9057 if (mips_pic
!= SVR4_PIC
)
9063 label
= insn_labels
!= NULL
? insn_labels
->label
: NULL
;
9064 mips_emit_delays (true);
9066 mips_align (2, 0, label
);
9067 mips_clear_insn_labels ();
9071 if (ex
.X_op
!= O_symbol
|| ex
.X_add_number
!= 0)
9073 as_bad ("Unsupported use of .gpword");
9074 ignore_rest_of_line ();
9078 md_number_to_chars (p
, (valueT
) 0, 4);
9079 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 4, &ex
, 0,
9080 BFD_RELOC_MIPS_GPREL32
);
9082 demand_empty_rest_of_line ();
9085 /* Handle the .cpadd pseudo-op. This is used when dealing with switch
9086 tables in SVR4 PIC code. */
9095 /* This is ignored when not generating SVR4 PIC code. */
9096 if (mips_pic
!= SVR4_PIC
)
9102 /* Add $gp to the register named as an argument. */
9103 reg
= tc_get_register (0);
9104 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
9105 mips_isa
< 3 ? "addu" : "daddu",
9106 "d,v,t", reg
, reg
, GP
);
9108 demand_empty_rest_of_line ();
9111 /* Parse a register string into a number. Called from the ECOFF code
9112 to parse .frame. The argument is non-zero if this is the frame
9113 register, so that we can record it in mips_frame_reg. */
9116 tc_get_register (frame
)
9122 if (*input_line_pointer
++ != '$')
9124 as_warn ("expected `$'");
9127 else if (isdigit ((unsigned char) *input_line_pointer
))
9129 reg
= get_absolute_expression ();
9130 if (reg
< 0 || reg
>= 32)
9132 as_warn ("Bad register number");
9138 if (strncmp (input_line_pointer
, "fp", 2) == 0)
9140 else if (strncmp (input_line_pointer
, "sp", 2) == 0)
9142 else if (strncmp (input_line_pointer
, "gp", 2) == 0)
9144 else if (strncmp (input_line_pointer
, "at", 2) == 0)
9148 as_warn ("Unrecognized register name");
9151 input_line_pointer
+= 2;
9154 mips_frame_reg
= reg
!= 0 ? reg
: SP
;
9159 md_section_align (seg
, addr
)
9163 int align
= bfd_get_section_alignment (stdoutput
, seg
);
9166 /* We don't need to align ELF sections to the full alignment.
9167 However, Irix 5 may prefer that we align them at least to a 16
9168 byte boundary. We don't bother to align the sections if we are
9169 targeted for an embedded system. */
9170 if (strcmp (TARGET_OS
, "elf") == 0)
9176 return ((addr
+ (1 << align
) - 1) & (-1 << align
));
9179 /* Utility routine, called from above as well. If called while the
9180 input file is still being read, it's only an approximation. (For
9181 example, a symbol may later become defined which appeared to be
9182 undefined earlier.) */
9185 nopic_need_relax (sym
)
9191 if (USE_GLOBAL_POINTER_OPT
)
9193 const char *symname
;
9196 /* Find out whether this symbol can be referenced off the GP
9197 register. It can be if it is smaller than the -G size or if
9198 it is in the .sdata or .sbss section. Certain symbols can
9199 not be referenced off the GP, although it appears as though
9201 symname
= S_GET_NAME (sym
);
9202 if (symname
!= (const char *) NULL
9203 && (strcmp (symname
, "eprol") == 0
9204 || strcmp (symname
, "etext") == 0
9205 || strcmp (symname
, "_gp") == 0
9206 || strcmp (symname
, "edata") == 0
9207 || strcmp (symname
, "_fbss") == 0
9208 || strcmp (symname
, "_fdata") == 0
9209 || strcmp (symname
, "_ftext") == 0
9210 || strcmp (symname
, "end") == 0
9211 || strcmp (symname
, "_gp_disp") == 0))
9213 else if (! S_IS_DEFINED (sym
)
9215 #ifndef NO_ECOFF_DEBUGGING
9216 || (sym
->ecoff_extern_size
!= 0
9217 && sym
->ecoff_extern_size
<= g_switch_value
)
9219 || (S_GET_VALUE (sym
) != 0
9220 && S_GET_VALUE (sym
) <= g_switch_value
)))
9224 const char *segname
;
9226 segname
= segment_name (S_GET_SEGMENT (sym
));
9227 assert (strcmp (segname
, ".lit8") != 0
9228 && strcmp (segname
, ".lit4") != 0);
9229 change
= (strcmp (segname
, ".sdata") != 0
9230 && strcmp (segname
, ".sbss") != 0);
9235 /* We are not optimizing for the GP register. */
9239 /* Given a mips16 variant frag FRAGP, return non-zero if it needs an
9240 extended opcode. SEC is the section the frag is in. */
9243 mips16_extended_frag (fragp
, sec
, stretch
)
9249 register const struct mips16_immed_operand
*op
;
9251 int mintiny
, maxtiny
;
9254 if (RELAX_MIPS16_USER_SMALL (fragp
->fr_subtype
))
9256 if (RELAX_MIPS16_USER_EXT (fragp
->fr_subtype
))
9259 type
= RELAX_MIPS16_TYPE (fragp
->fr_subtype
);
9260 op
= mips16_immed_operands
;
9261 while (op
->type
!= type
)
9264 assert (op
< mips16_immed_operands
+ MIPS16_NUM_IMMED
);
9269 if (type
== '<' || type
== '>' || type
== '[' || type
== ']')
9272 maxtiny
= 1 << op
->nbits
;
9277 maxtiny
= (1 << op
->nbits
) - 1;
9282 mintiny
= - (1 << (op
->nbits
- 1));
9283 maxtiny
= (1 << (op
->nbits
- 1)) - 1;
9286 /* We can't call S_GET_VALUE here, because we don't want to lock in
9287 a particular frag address. */
9288 if (fragp
->fr_symbol
->sy_value
.X_op
== O_constant
)
9290 val
= (fragp
->fr_symbol
->sy_value
.X_add_number
9291 + fragp
->fr_symbol
->sy_frag
->fr_address
);
9292 symsec
= S_GET_SEGMENT (fragp
->fr_symbol
);
9294 else if (fragp
->fr_symbol
->sy_value
.X_op
== O_symbol
9295 && (fragp
->fr_symbol
->sy_value
.X_add_symbol
->sy_value
.X_op
9298 val
= (fragp
->fr_symbol
->sy_value
.X_add_symbol
->sy_value
.X_add_number
9299 + fragp
->fr_symbol
->sy_value
.X_add_symbol
->sy_frag
->fr_address
9300 + fragp
->fr_symbol
->sy_value
.X_add_number
9301 + fragp
->fr_symbol
->sy_frag
->fr_address
);
9302 symsec
= S_GET_SEGMENT (fragp
->fr_symbol
->sy_value
.X_add_symbol
);
9311 /* We won't have the section when we are called from
9312 mips_relax_frag. However, we will always have been called
9313 from md_estimate_size_before_relax first. If this is a
9314 branch to a different section, we mark it as such. If SEC is
9315 NULL, and the frag is not marked, then it must be a branch to
9316 the same section. */
9319 if (RELAX_MIPS16_LONG_BRANCH (fragp
->fr_subtype
))
9327 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
9329 /* FIXME: We should support this, and let the linker
9330 catch branches and loads that are out of range. */
9331 as_bad_where (fragp
->fr_file
, fragp
->fr_line
,
9332 "unsupported PC relative reference to different section");
9338 /* In this case, we know for sure that the symbol fragment is in
9339 the same section. If the fr_address of the symbol fragment
9340 is greater then the address of this fragment we want to add
9341 in STRETCH in order to get a better estimate of the address.
9342 This particularly matters because of the shift bits. */
9344 && fragp
->fr_symbol
->sy_frag
->fr_address
>= fragp
->fr_address
)
9348 /* Adjust stretch for any alignment frag. */
9349 for (f
= fragp
; f
!= fragp
->fr_symbol
->sy_frag
; f
= f
->fr_next
)
9352 if (f
->fr_type
== rs_align
|| f
->fr_type
== rs_align_code
)
9355 stretch
= - ((- stretch
)
9356 & ~ ((1 << (int) f
->fr_offset
) - 1));
9358 stretch
&= ~ ((1 << (int) f
->fr_offset
) - 1);
9366 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
9368 /* The base address rules are complicated. The base address of
9369 a branch is the following instruction. The base address of a
9370 PC relative load or add is the instruction itself, but if it
9371 is extended add 2, and if it is in a delay slot (in which
9372 case it can not be extended) use the address of the
9373 instruction whose delay slot it is in. */
9374 if (type
== 'p' || type
== 'q')
9377 /* Ignore the low bit in the target, since it will be set
9378 for a text label. */
9382 else if (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
))
9384 else if (RELAX_MIPS16_DSLOT (fragp
->fr_subtype
))
9387 /* If we are currently assuming that this frag should be
9388 extended, then the current address is two bytes higher. */
9389 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
9392 val
-= addr
& ~ ((1 << op
->shift
) - 1);
9394 /* Branch offsets have an implicit 0 in the lowest bit. */
9395 if (type
== 'p' || type
== 'q')
9398 /* If any of the shifted bits are set, we must use an extended
9399 opcode. If the address depends on the size of this
9400 instruction, this can lead to a loop, so we arrange to always
9401 use an extended opcode. We only check this when we are in
9402 the main relaxation loop, when SEC is NULL. */
9403 if ((val
& ((1 << op
->shift
) - 1)) != 0 && sec
== NULL
)
9406 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
9410 /* If we are about to mark a frag as extended because the value
9411 is precisely maxtiny + 1, then there is a chance of an
9412 infinite loop as in the following code:
9417 In this case when the la is extended, foo is 0x3fc bytes
9418 away, so the la can be shrunk, but then foo is 0x400 away, so
9419 the la must be extended. To avoid this loop, we mark the
9420 frag as extended if it was small, and is about to become
9421 extended with a value of maxtiny + 1. */
9422 if (val
== ((maxtiny
+ 1) << op
->shift
)
9423 && ! RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
)
9427 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
9431 else if (symsec
!= absolute_section
&& sec
!= NULL
)
9432 as_bad_where (fragp
->fr_file
, fragp
->fr_line
, "unsupported relocation");
9434 if ((val
& ((1 << op
->shift
) - 1)) != 0
9435 || val
< (mintiny
<< op
->shift
)
9436 || val
> (maxtiny
<< op
->shift
))
9442 /* Estimate the size of a frag before relaxing. Unless this is the
9443 mips16, we are not really relaxing here, and the final size is
9444 encoded in the subtype information. For the mips16, we have to
9445 decide whether we are using an extended opcode or not. */
9449 md_estimate_size_before_relax (fragp
, segtype
)
9455 if (RELAX_MIPS16_P (fragp
->fr_subtype
))
9457 if (mips16_extended_frag (fragp
, segtype
, 0))
9459 fragp
->fr_subtype
= RELAX_MIPS16_MARK_EXTENDED (fragp
->fr_subtype
);
9464 fragp
->fr_subtype
= RELAX_MIPS16_CLEAR_EXTENDED (fragp
->fr_subtype
);
9469 if (mips_pic
== NO_PIC
)
9471 change
= nopic_need_relax (fragp
->fr_symbol
);
9473 else if (mips_pic
== SVR4_PIC
)
9475 asection
*symsec
= fragp
->fr_symbol
->bsym
->section
;
9477 /* This must duplicate the test in adjust_reloc_syms. */
9478 change
= (symsec
!= &bfd_und_section
9479 && symsec
!= &bfd_abs_section
9480 && ! bfd_is_com_section (symsec
));
9487 /* Record the offset to the first reloc in the fr_opcode field.
9488 This lets md_convert_frag and tc_gen_reloc know that the code
9489 must be expanded. */
9490 fragp
->fr_opcode
= (fragp
->fr_literal
9492 - RELAX_OLD (fragp
->fr_subtype
)
9493 + RELAX_RELOC1 (fragp
->fr_subtype
));
9494 /* FIXME: This really needs as_warn_where. */
9495 if (RELAX_WARN (fragp
->fr_subtype
))
9496 as_warn ("AT used after \".set noat\" or macro used after \".set nomacro\"");
9502 return RELAX_NEW (fragp
->fr_subtype
) - RELAX_OLD (fragp
->fr_subtype
);
9505 /* This is called to see whether a reloc against a defined symbol
9506 should be converted into a reloc against a section. Don't adjust
9507 MIPS16 jump relocations, so we don't have to worry about the format
9508 of the offset in the .o file. Don't adjust relocations against
9509 mips16 symbols, so that the linker can find them if it needs to set
9513 mips_fix_adjustable (fixp
)
9516 if (fixp
->fx_r_type
== BFD_RELOC_MIPS16_JMP
)
9518 if (fixp
->fx_addsy
== NULL
)
9521 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
9522 && S_GET_OTHER (fixp
->fx_addsy
) == STO_MIPS16
)
9528 /* Translate internal representation of relocation info to BFD target
9532 tc_gen_reloc (section
, fixp
)
9536 static arelent
*retval
[4];
9538 bfd_reloc_code_real_type code
;
9540 reloc
= retval
[0] = (arelent
*) xmalloc (sizeof (arelent
));
9543 reloc
->sym_ptr_ptr
= &fixp
->fx_addsy
->bsym
;
9544 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
9546 if (mips_pic
== EMBEDDED_PIC
9547 && SWITCH_TABLE (fixp
))
9549 /* For a switch table entry we use a special reloc. The addend
9550 is actually the difference between the reloc address and the
9552 reloc
->addend
= reloc
->address
- S_GET_VALUE (fixp
->fx_subsy
);
9553 if (OUTPUT_FLAVOR
!= bfd_target_ecoff_flavour
)
9554 as_fatal ("Double check fx_r_type in tc-mips.c:tc_gen_reloc");
9555 fixp
->fx_r_type
= BFD_RELOC_GPREL32
;
9557 else if (fixp
->fx_r_type
== BFD_RELOC_PCREL_LO16
)
9559 /* We use a special addend for an internal RELLO reloc. */
9560 if (fixp
->fx_addsy
->bsym
->flags
& BSF_SECTION_SYM
)
9561 reloc
->addend
= reloc
->address
- S_GET_VALUE (fixp
->fx_subsy
);
9563 reloc
->addend
= fixp
->fx_addnumber
+ reloc
->address
;
9565 else if (fixp
->fx_r_type
== BFD_RELOC_PCREL_HI16_S
)
9567 assert (fixp
->fx_next
!= NULL
9568 && fixp
->fx_next
->fx_r_type
== BFD_RELOC_PCREL_LO16
);
9569 /* We use a special addend for an internal RELHI reloc. The
9570 reloc is relative to the RELLO; adjust the addend
9572 if (fixp
->fx_addsy
->bsym
->flags
& BSF_SECTION_SYM
)
9573 reloc
->addend
= (fixp
->fx_next
->fx_frag
->fr_address
9574 + fixp
->fx_next
->fx_where
9575 - S_GET_VALUE (fixp
->fx_subsy
));
9577 reloc
->addend
= (fixp
->fx_addnumber
9578 + fixp
->fx_next
->fx_frag
->fr_address
9579 + fixp
->fx_next
->fx_where
);
9581 else if (fixp
->fx_pcrel
== 0)
9582 reloc
->addend
= fixp
->fx_addnumber
;
9585 if (OUTPUT_FLAVOR
!= bfd_target_aout_flavour
)
9586 /* A gruesome hack which is a result of the gruesome gas reloc
9588 reloc
->addend
= reloc
->address
;
9590 reloc
->addend
= -reloc
->address
;
9593 /* If this is a variant frag, we may need to adjust the existing
9594 reloc and generate a new one. */
9595 if (fixp
->fx_frag
->fr_opcode
!= NULL
9596 && (fixp
->fx_r_type
== BFD_RELOC_MIPS_GPREL
9597 || fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT16
9598 || fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL16
9599 || fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT_HI16
9600 || fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT_LO16
9601 || fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL_HI16
9602 || fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL_LO16
))
9606 assert (! RELAX_MIPS16_P (fixp
->fx_frag
->fr_subtype
));
9608 /* If this is not the last reloc in this frag, then we have two
9609 GPREL relocs, or a GOT_HI16/GOT_LO16 pair, or a
9610 CALL_HI16/CALL_LO16, both of which are being replaced. Let
9611 the second one handle all of them. */
9612 if (fixp
->fx_next
!= NULL
9613 && fixp
->fx_frag
== fixp
->fx_next
->fx_frag
)
9615 assert ((fixp
->fx_r_type
== BFD_RELOC_MIPS_GPREL
9616 && fixp
->fx_next
->fx_r_type
== BFD_RELOC_MIPS_GPREL
)
9617 || (fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT_HI16
9618 && (fixp
->fx_next
->fx_r_type
9619 == BFD_RELOC_MIPS_GOT_LO16
))
9620 || (fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL_HI16
9621 && (fixp
->fx_next
->fx_r_type
9622 == BFD_RELOC_MIPS_CALL_LO16
)));
9627 fixp
->fx_where
= fixp
->fx_frag
->fr_opcode
- fixp
->fx_frag
->fr_literal
;
9628 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
9629 reloc2
= retval
[1] = (arelent
*) xmalloc (sizeof (arelent
));
9631 reloc2
->sym_ptr_ptr
= &fixp
->fx_addsy
->bsym
;
9632 reloc2
->address
= (reloc
->address
9633 + (RELAX_RELOC2 (fixp
->fx_frag
->fr_subtype
)
9634 - RELAX_RELOC1 (fixp
->fx_frag
->fr_subtype
)));
9635 reloc2
->addend
= fixp
->fx_addnumber
;
9636 reloc2
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_LO16
);
9637 assert (reloc2
->howto
!= NULL
);
9639 if (RELAX_RELOC3 (fixp
->fx_frag
->fr_subtype
))
9643 reloc3
= retval
[2] = (arelent
*) xmalloc (sizeof (arelent
));
9646 reloc3
->address
+= 4;
9649 if (mips_pic
== NO_PIC
)
9651 assert (fixp
->fx_r_type
== BFD_RELOC_MIPS_GPREL
);
9652 fixp
->fx_r_type
= BFD_RELOC_HI16_S
;
9654 else if (mips_pic
== SVR4_PIC
)
9656 switch (fixp
->fx_r_type
)
9660 case BFD_RELOC_MIPS_GOT16
:
9662 case BFD_RELOC_MIPS_CALL16
:
9663 case BFD_RELOC_MIPS_GOT_LO16
:
9664 case BFD_RELOC_MIPS_CALL_LO16
:
9665 fixp
->fx_r_type
= BFD_RELOC_MIPS_GOT16
;
9673 /* Since DIFF_EXPR_OK is defined in tc-mips.h, it is possible that
9674 fixup_segment converted a non-PC relative reloc into a PC
9675 relative reloc. In such a case, we need to convert the reloc
9677 code
= fixp
->fx_r_type
;
9683 code
= BFD_RELOC_8_PCREL
;
9686 code
= BFD_RELOC_16_PCREL
;
9689 code
= BFD_RELOC_32_PCREL
;
9692 code
= BFD_RELOC_64_PCREL
;
9694 case BFD_RELOC_8_PCREL
:
9695 case BFD_RELOC_16_PCREL
:
9696 case BFD_RELOC_32_PCREL
:
9697 case BFD_RELOC_64_PCREL
:
9698 case BFD_RELOC_16_PCREL_S2
:
9699 case BFD_RELOC_PCREL_HI16_S
:
9700 case BFD_RELOC_PCREL_LO16
:
9703 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
9704 "Cannot make %s relocation PC relative",
9705 bfd_get_reloc_code_name (code
));
9709 /* To support a PC relative reloc when generating embedded PIC code
9710 for ECOFF, we use a Cygnus extension. We check for that here to
9711 make sure that we don't let such a reloc escape normally. */
9712 if (OUTPUT_FLAVOR
== bfd_target_ecoff_flavour
9713 && code
== BFD_RELOC_16_PCREL_S2
9714 && mips_pic
!= EMBEDDED_PIC
)
9715 reloc
->howto
= NULL
;
9717 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
9719 if (reloc
->howto
== NULL
)
9721 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
9722 "Can not represent %s relocation in this object file format",
9723 bfd_get_reloc_code_name (code
));
9730 /* Relax a machine dependent frag. This returns the amount by which
9731 the current size of the frag should change. */
9734 mips_relax_frag (fragp
, stretch
)
9738 if (! RELAX_MIPS16_P (fragp
->fr_subtype
))
9741 if (mips16_extended_frag (fragp
, (asection
*) NULL
, stretch
))
9743 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
9745 fragp
->fr_subtype
= RELAX_MIPS16_MARK_EXTENDED (fragp
->fr_subtype
);
9750 if (! RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
9752 fragp
->fr_subtype
= RELAX_MIPS16_CLEAR_EXTENDED (fragp
->fr_subtype
);
9759 /* Convert a machine dependent frag. */
9762 md_convert_frag (abfd
, asec
, fragp
)
9770 if (RELAX_MIPS16_P (fragp
->fr_subtype
))
9773 register const struct mips16_immed_operand
*op
;
9779 unsigned short extend
;
9781 type
= RELAX_MIPS16_TYPE (fragp
->fr_subtype
);
9782 op
= mips16_immed_operands
;
9783 while (op
->type
!= type
)
9786 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
9797 resolve_symbol_value (fragp
->fr_symbol
);
9798 val
= S_GET_VALUE (fragp
->fr_symbol
);
9803 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
9805 /* The rules for the base address of a PC relative reloc are
9806 complicated; see mips16_extended_frag. */
9807 if (type
== 'p' || type
== 'q')
9810 /* Ignore the low bit in the target, since it will be
9811 set for a text label. */
9815 else if (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
))
9817 else if (RELAX_MIPS16_DSLOT (fragp
->fr_subtype
))
9822 addr
&= ~ (addressT
) ((1 << op
->shift
) - 1);
9825 /* Make sure the section winds up with the alignment we have
9828 record_alignment (asec
, op
->shift
);
9831 buf
= (bfd_byte
*) (fragp
->fr_literal
+ fragp
->fr_fix
);
9833 if (target_big_endian
)
9834 insn
= bfd_getb16 (buf
);
9836 insn
= bfd_getl16 (buf
);
9838 mips16_immed (fragp
->fr_file
, fragp
->fr_line
, type
, val
,
9839 RELAX_MIPS16_USER_EXT (fragp
->fr_subtype
),
9840 small
, ext
, &insn
, &use_extend
, &extend
);
9844 md_number_to_chars (buf
, 0xf000 | extend
, 2);
9849 md_number_to_chars (buf
, insn
, 2);
9855 if (fragp
->fr_opcode
== NULL
)
9858 old
= RELAX_OLD (fragp
->fr_subtype
);
9859 new = RELAX_NEW (fragp
->fr_subtype
);
9860 fixptr
= fragp
->fr_literal
+ fragp
->fr_fix
;
9863 memcpy (fixptr
- old
, fixptr
, new);
9865 fragp
->fr_fix
+= new - old
;
9871 /* This function is called after the relocs have been generated.
9872 We've been storing mips16 text labels as odd. Here we convert them
9873 back to even for the convenience of the debugger. */
9876 mips_frob_file_after_relocs ()
9879 unsigned int count
, i
;
9881 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
9884 syms
= bfd_get_outsymbols (stdoutput
);
9885 count
= bfd_get_symcount (stdoutput
);
9886 for (i
= 0; i
< count
; i
++, syms
++)
9888 if (elf_symbol (*syms
)->internal_elf_sym
.st_other
== STO_MIPS16
9889 && ((*syms
)->value
& 1) != 0)
9891 (*syms
)->value
&= ~1;
9892 /* If the symbol has an odd size, it was probably computed
9893 incorrectly, so adjust that as well. */
9894 if ((elf_symbol (*syms
)->internal_elf_sym
.st_size
& 1) != 0)
9895 ++elf_symbol (*syms
)->internal_elf_sym
.st_size
;
9902 /* This function is called whenever a label is defined. It is used
9903 when handling branch delays; if a branch has a label, we assume we
9907 mips_define_label (sym
)
9910 struct insn_label_list
*l
;
9912 if (free_insn_labels
== NULL
)
9913 l
= (struct insn_label_list
*) xmalloc (sizeof *l
);
9916 l
= free_insn_labels
;
9917 free_insn_labels
= l
->next
;
9921 l
->next
= insn_labels
;
9925 /* Decide whether a label is local. This is called by LOCAL_LABEL.
9926 In order to work with gcc when using mips-tfile, we must keep all
9927 local labels. However, in other cases, we want to discard them,
9928 since they are useless. */
9931 mips_local_label (name
)
9934 #ifndef NO_ECOFF_DEBUGGING
9937 && ! ecoff_debugging_seen
)
9939 /* We were called with -g, but we didn't see any debugging
9940 information. That may mean that gcc is smuggling debugging
9941 information through to mips-tfile, in which case we must
9942 generate all local labels. */
9947 /* Here it's OK to discard local labels. */
9949 return name
[0] == '$';
9952 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9954 /* Some special processing for a MIPS ELF file. */
9957 mips_elf_final_processing ()
9959 /* Write out the register information. */
9964 s
.ri_gprmask
= mips_gprmask
;
9965 s
.ri_cprmask
[0] = mips_cprmask
[0];
9966 s
.ri_cprmask
[1] = mips_cprmask
[1];
9967 s
.ri_cprmask
[2] = mips_cprmask
[2];
9968 s
.ri_cprmask
[3] = mips_cprmask
[3];
9969 /* The gp_value field is set by the MIPS ELF backend. */
9971 bfd_mips_elf32_swap_reginfo_out (stdoutput
, &s
,
9972 ((Elf32_External_RegInfo
*)
9973 mips_regmask_frag
));
9977 Elf64_Internal_RegInfo s
;
9979 s
.ri_gprmask
= mips_gprmask
;
9981 s
.ri_cprmask
[0] = mips_cprmask
[0];
9982 s
.ri_cprmask
[1] = mips_cprmask
[1];
9983 s
.ri_cprmask
[2] = mips_cprmask
[2];
9984 s
.ri_cprmask
[3] = mips_cprmask
[3];
9985 /* The gp_value field is set by the MIPS ELF backend. */
9987 bfd_mips_elf64_swap_reginfo_out (stdoutput
, &s
,
9988 ((Elf64_External_RegInfo
*)
9989 mips_regmask_frag
));
9992 /* Set the MIPS ELF flag bits. FIXME: There should probably be some
9993 sort of BFD interface for this. */
9994 if (mips_any_noreorder
)
9995 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_NOREORDER
;
9996 if (mips_pic
!= NO_PIC
)
9997 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_PIC
;
10000 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */
10002 /* These functions should really be defined by the object file format,
10003 since they are related to debugging information. However, this
10004 code has to work for the a.out format, which does not define them,
10005 so we provide simple versions here. These don't actually generate
10006 any debugging information, but they do simple checking and someday
10007 somebody may make them useful. */
10011 struct loc
*loc_next
;
10012 unsigned long loc_fileno
;
10013 unsigned long loc_lineno
;
10014 unsigned long loc_offset
;
10015 unsigned short loc_delta
;
10016 unsigned short loc_count
;
10023 typedef struct proc
10025 struct proc
*proc_next
;
10026 struct symbol
*proc_isym
;
10027 struct symbol
*proc_end
;
10028 unsigned long proc_reg_mask
;
10029 unsigned long proc_reg_offset
;
10030 unsigned long proc_fpreg_mask
;
10031 unsigned long proc_fpreg_offset
;
10032 unsigned long proc_frameoffset
;
10033 unsigned long proc_framereg
;
10034 unsigned long proc_pcreg
;
10036 struct file
*proc_file
;
10041 typedef struct file
10043 struct file
*file_next
;
10044 unsigned long file_fileno
;
10045 struct symbol
*file_symbol
;
10046 struct symbol
*file_end
;
10047 struct proc
*file_proc
;
10052 static struct obstack proc_frags
;
10053 static procS
*proc_lastP
;
10054 static procS
*proc_rootP
;
10055 static int numprocs
;
10060 obstack_begin (&proc_frags
, 0x2000);
10066 /* check for premature end, nesting errors, etc */
10067 if (proc_lastP
&& proc_lastP
->proc_end
== NULL
)
10068 as_warn ("missing `.end' at end of assembly");
10077 if (*input_line_pointer
== '-')
10079 ++input_line_pointer
;
10082 if (!isdigit (*input_line_pointer
))
10083 as_bad ("Expected simple number.");
10084 if (input_line_pointer
[0] == '0')
10086 if (input_line_pointer
[1] == 'x')
10088 input_line_pointer
+= 2;
10089 while (isxdigit (*input_line_pointer
))
10092 val
|= hex_value (*input_line_pointer
++);
10094 return negative
? -val
: val
;
10098 ++input_line_pointer
;
10099 while (isdigit (*input_line_pointer
))
10102 val
|= *input_line_pointer
++ - '0';
10104 return negative
? -val
: val
;
10107 if (!isdigit (*input_line_pointer
))
10109 printf (" *input_line_pointer == '%c' 0x%02x\n",
10110 *input_line_pointer
, *input_line_pointer
);
10111 as_warn ("Invalid number");
10114 while (isdigit (*input_line_pointer
))
10117 val
+= *input_line_pointer
++ - '0';
10119 return negative
? -val
: val
;
10122 /* The .file directive; just like the usual .file directive, but there
10123 is an initial number which is the ECOFF file index. */
10131 line
= get_number ();
10136 /* The .end directive. */
10144 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
10147 demand_empty_rest_of_line ();
10151 if (now_seg
!= text_section
)
10152 as_warn (".end not in text section");
10155 as_warn (".end and no .ent seen yet.");
10161 assert (S_GET_NAME (p
));
10162 if (strcmp (S_GET_NAME (p
), S_GET_NAME (proc_lastP
->proc_isym
)))
10163 as_warn (".end symbol does not match .ent symbol.");
10166 proc_lastP
->proc_end
= (symbolS
*) 1;
10169 /* The .aent and .ent directives. */
10179 symbolP
= get_symbol ();
10180 if (*input_line_pointer
== ',')
10181 input_line_pointer
++;
10182 SKIP_WHITESPACE ();
10183 if (isdigit (*input_line_pointer
) || *input_line_pointer
== '-')
10184 number
= get_number ();
10185 if (now_seg
!= text_section
)
10186 as_warn (".ent or .aent not in text section.");
10188 if (!aent
&& proc_lastP
&& proc_lastP
->proc_end
== NULL
)
10189 as_warn ("missing `.end'");
10193 procP
= (procS
*) obstack_alloc (&proc_frags
, sizeof (*procP
));
10194 procP
->proc_isym
= symbolP
;
10195 procP
->proc_reg_mask
= 0;
10196 procP
->proc_reg_offset
= 0;
10197 procP
->proc_fpreg_mask
= 0;
10198 procP
->proc_fpreg_offset
= 0;
10199 procP
->proc_frameoffset
= 0;
10200 procP
->proc_framereg
= 0;
10201 procP
->proc_pcreg
= 0;
10202 procP
->proc_end
= NULL
;
10203 procP
->proc_next
= NULL
;
10205 proc_lastP
->proc_next
= procP
;
10207 proc_rootP
= procP
;
10208 proc_lastP
= procP
;
10211 demand_empty_rest_of_line ();
10214 /* The .frame directive. */
10227 frame_reg
= tc_get_register (1);
10228 if (*input_line_pointer
== ',')
10229 input_line_pointer
++;
10230 frame_off
= get_absolute_expression ();
10231 if (*input_line_pointer
== ',')
10232 input_line_pointer
++;
10233 pcreg
= tc_get_register (0);
10235 /* bob third eye */
10236 assert (proc_rootP
);
10237 proc_rootP
->proc_framereg
= frame_reg
;
10238 proc_rootP
->proc_frameoffset
= frame_off
;
10239 proc_rootP
->proc_pcreg
= pcreg
;
10240 /* bob macho .frame */
10242 /* We don't have to write out a frame stab for unoptimized code. */
10243 if (!(frame_reg
== FP
&& frame_off
== 0))
10246 as_warn ("No .ent for .frame to use.");
10247 (void) sprintf (str
, "R%d;%d", frame_reg
, frame_off
);
10248 symP
= symbol_new (str
, N_VFP
, 0, frag_now
);
10249 S_SET_TYPE (symP
, N_RMASK
);
10250 S_SET_OTHER (symP
, 0);
10251 S_SET_DESC (symP
, 0);
10252 symP
->sy_forward
= proc_lastP
->proc_isym
;
10253 /* bob perhaps I should have used pseudo set */
10255 demand_empty_rest_of_line ();
10259 /* The .fmask and .mask directives. */
10266 char str
[100], *strP
;
10272 mask
= get_number ();
10273 if (*input_line_pointer
== ',')
10274 input_line_pointer
++;
10275 off
= get_absolute_expression ();
10277 /* bob only for coff */
10278 assert (proc_rootP
);
10279 if (reg_type
== 'F')
10281 proc_rootP
->proc_fpreg_mask
= mask
;
10282 proc_rootP
->proc_fpreg_offset
= off
;
10286 proc_rootP
->proc_reg_mask
= mask
;
10287 proc_rootP
->proc_reg_offset
= off
;
10290 /* bob macho .mask + .fmask */
10292 /* We don't have to write out a mask stab if no saved regs. */
10296 as_warn ("No .ent for .mask to use.");
10298 for (i
= 0; i
< 32; i
++)
10302 sprintf (strP
, "%c%d,", reg_type
, i
);
10303 strP
+= strlen (strP
);
10307 sprintf (strP
, ";%d,", off
);
10308 symP
= symbol_new (str
, N_RMASK
, 0, frag_now
);
10309 S_SET_TYPE (symP
, N_RMASK
);
10310 S_SET_OTHER (symP
, 0);
10311 S_SET_DESC (symP
, 0);
10312 symP
->sy_forward
= proc_lastP
->proc_isym
;
10313 /* bob perhaps I should have used pseudo set */
10318 /* The .loc directive. */
10329 assert (now_seg
== text_section
);
10331 lineno
= get_number ();
10332 addroff
= frag_now_fix ();
10334 symbolP
= symbol_new ("", N_SLINE
, addroff
, frag_now
);
10335 S_SET_TYPE (symbolP
, N_SLINE
);
10336 S_SET_OTHER (symbolP
, 0);
10337 S_SET_DESC (symbolP
, lineno
);
10338 symbolP
->sy_segment
= now_seg
;