1 /* tc-mips.c -- assemble code for a MIPS chip.
2 Copyright (C) 1993 Free Software Foundation, Inc.
3 Contributed by the OSF and Ralph Campbell.
4 Written by Keith Knowles and Ralph Campbell, working independently.
5 Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus
8 This file is part of GAS.
10 GAS is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 2, or (at your option)
15 GAS is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with GAS; see the file COPYING. If not, write to
22 the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */
27 #include "libiberty.h"
42 #endif /* NO_VARARGS */
43 #endif /* NO_STDARG */
45 #include "opcode/mips.h"
50 static char *mips_regmask_frag
;
54 #define PIC_CALL_REG 25
62 /* Decide whether to do GP reference optimizations based on the object
72 /* The default target format to use. */
74 #ifdef TARGET_BYTES_BIG_ENDIAN
75 #define DEFAULT_TARGET_FORMAT "a.out-mips-big"
77 #define DEFAULT_TARGET_FORMAT "a.out-mips-little"
81 #ifdef TARGET_BYTES_BIG_ENDIAN
82 #define DEFAULT_TARGET_FORMAT "ecoff-bigmips"
84 #define DEFAULT_TARGET_FORMAT "ecoff-littlemips"
86 #endif /* OBJ_ECOFF */
88 #ifdef TARGET_BYTES_BIG_ENDIAN
89 #define DEFAULT_TARGET_FORMAT "elf32-bigmips"
91 #define DEFAULT_TARGET_FORMAT "elf32-littlemips"
95 const char *mips_target_format
= DEFAULT_TARGET_FORMAT
;
97 /* The name of the readonly data section. */
99 #define RDATA_SECTION_NAME ".data"
102 #define RDATA_SECTION_NAME ".rdata"
105 #define RDATA_SECTION_NAME ".rodata"
108 /* These variables are filled in with the masks of registers used.
109 The object format code reads them and puts them in the appropriate
111 unsigned long mips_gprmask
;
112 unsigned long mips_cprmask
[4];
114 /* MIPS ISA (Instruction Set Architecture) level (may be changed
115 temporarily using .set mipsN). */
116 static int mips_isa
= -1;
118 /* MIPS ISA we are using for this output file. */
119 static int file_mips_isa
;
121 /* The CPU type as a number: 2000, 3000, 4000, 4400, etc. */
122 static int mips_cpu
= -1;
124 /* Whether the 4650 instructions (mad/madu) are permitted. */
125 static int mips_4650
= -1;
127 /* MIPS PIC level. */
131 /* Do not generate PIC code. */
134 /* Generate PIC code as in Irix 4. This is not implemented, and I'm
135 not sure what it is supposed to do. */
138 /* Generate PIC code as in the SVR4 MIPS ABI. */
141 /* Generate PIC code without using a global offset table: the data
142 segment has a maximum size of 64K, all data references are off
143 the $gp register, and all text references are PC relative. This
144 is used on some embedded systems. */
148 static enum mips_pic_level mips_pic
;
150 /* 1 if trap instructions should used for overflow rather than break
152 static int mips_trap
;
154 static int mips_warn_about_macros
;
155 static int mips_noreorder
;
156 static int mips_any_noreorder
;
157 static int mips_nomove
;
158 static int mips_noat
;
159 static int mips_nobopt
;
162 /* The size of the small data section. */
163 static int g_switch_value
= 8;
164 /* Whether the -G option was used. */
165 static int g_switch_seen
= 0;
171 /* handle of the OPCODE hash table */
172 static struct hash_control
*op_hash
= NULL
;
174 /* This array holds the chars that always start a comment. If the
175 pre-processor is disabled, these aren't very useful */
176 const char comment_chars
[] = "#";
178 /* This array holds the chars that only start a comment at the beginning of
179 a line. If the line seems to have the form '# 123 filename'
180 .line and .file directives will appear in the pre-processed output */
181 /* Note that input_file.c hand checks for '#' at the beginning of the
182 first line of the input file. This is because the compiler outputs
183 #NO_APP at the beginning of its output. */
184 /* Also note that C style comments are always supported. */
185 const char line_comment_chars
[] = "#";
187 /* This array holds machine specific line separator characters. */
188 const char line_separator_chars
[] = "";
190 /* Chars that can be used to separate mant from exp in floating point nums */
191 const char EXP_CHARS
[] = "eE";
193 /* Chars that mean this number is a floating point constant */
196 const char FLT_CHARS
[] = "rRsSfFdDxXpP";
198 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
199 changed in read.c . Ideally it shouldn't have to know about it at all,
200 but nothing is ideal around here.
203 static char *insn_error
;
205 static int byte_order
= BYTE_ORDER
;
207 static int auto_align
= 1;
209 /* Symbol labelling the current insn. */
210 static symbolS
*insn_label
;
212 /* When outputting SVR4 PIC code, the assembler needs to know the
213 offset in the stack frame from which to restore the $gp register.
214 This is set by the .cprestore pseudo-op, and saved in this
216 static offsetT mips_cprestore_offset
= -1;
218 /* This is the register which holds the stack frame, as set by the
219 .frame pseudo-op. This is needed to implement .cprestore. */
220 static int mips_frame_reg
= SP
;
222 /* To output NOP instructions correctly, we need to keep information
223 about the previous two instructions. */
225 /* Whether we are optimizing. The default value of 2 means to remove
226 unneeded NOPs and swap branch instructions when possible. A value
227 of 1 means to not swap branches. A value of 0 means to always
229 static int mips_optimize
= 2;
231 /* The previous instruction. */
232 static struct mips_cl_insn prev_insn
;
234 /* The instruction before prev_insn. */
235 static struct mips_cl_insn prev_prev_insn
;
237 /* If we don't want information for prev_insn or prev_prev_insn, we
238 point the insn_mo field at this dummy integer. */
239 static const struct mips_opcode dummy_opcode
= { 0 };
241 /* Non-zero if prev_insn is valid. */
242 static int prev_insn_valid
;
244 /* The frag for the previous instruction. */
245 static struct frag
*prev_insn_frag
;
247 /* The offset into prev_insn_frag for the previous instruction. */
248 static long prev_insn_where
;
250 /* The reloc for the previous instruction, if any. */
251 static fixS
*prev_insn_fixp
;
253 /* Non-zero if the previous instruction was in a delay slot. */
254 static int prev_insn_is_delay_slot
;
256 /* Non-zero if the previous instruction was in a .set noreorder. */
257 static int prev_insn_unreordered
;
259 /* Non-zero if the previous previous instruction was in a .set
261 static int prev_prev_insn_unreordered
;
263 /* Since the MIPS does not have multiple forms of PC relative
264 instructions, we do not have to do relaxing as is done on other
265 platforms. However, we do have to handle GP relative addressing
266 correctly, which turns out to be a similar problem.
268 Every macro that refers to a symbol can occur in (at least) two
269 forms, one with GP relative addressing and one without. For
270 example, loading a global variable into a register generally uses
271 a macro instruction like this:
273 If i can be addressed off the GP register (this is true if it is in
274 the .sbss or .sdata section, or if it is known to be smaller than
275 the -G argument) this will generate the following instruction:
277 This instruction will use a GPREL reloc. If i can not be addressed
278 off the GP register, the following instruction sequence will be used:
281 In this case the first instruction will have a HI16 reloc, and the
282 second reloc will have a LO16 reloc. Both relocs will be against
285 The issue here is that we may not know whether i is GP addressable
286 until after we see the instruction that uses it. Therefore, we
287 want to be able to choose the final instruction sequence only at
288 the end of the assembly. This is similar to the way other
289 platforms choose the size of a PC relative instruction only at the
292 When generating position independent code we do not use GP
293 addressing in quite the same way, but the issue still arises as
294 external symbols and local symbols must be handled differently.
296 We handle these issues by actually generating both possible
297 instruction sequences. The longer one is put in a frag_var with
298 type rs_machine_dependent. We encode what to do with the frag in
299 the subtype field. We encode (1) the number of existing bytes to
300 replace, (2) the number of new bytes to use, (3) the offset from
301 the start of the existing bytes to the first reloc we must generate
302 (that is, the offset is applied from the start of the existing
303 bytes after they are replaced by the new bytes, if any), (4) the
304 offset from the start of the existing bytes to the second reloc,
305 (5) whether a third reloc is needed (the third reloc is always four
306 bytes after the second reloc), and (6) whether to warn if this
307 variant is used (this is sometimes needed if .set nomacro or .set
308 noat is in effect). All these numbers are reasonably small.
310 Generating two instruction sequences must be handled carefully to
311 ensure that delay slots are handled correctly. Fortunately, there
312 are a limited number of cases. When the second instruction
313 sequence is generated, append_insn is directed to maintain the
314 existing delay slot information, so it continues to apply to any
315 code after the second instruction sequence. This means that the
316 second instruction sequence must not impose any requirements not
317 required by the first instruction sequence.
319 These variant frags are then handled in functions called by the
320 machine independent code. md_estimate_size_before_relax returns
321 the final size of the frag. md_convert_frag sets up the final form
322 of the frag. tc_gen_reloc adjust the first reloc and adds a second
324 #define RELAX_ENCODE(old, new, reloc1, reloc2, reloc3, warn) \
328 | (((reloc1) + 64) << 9) \
329 | (((reloc2) + 64) << 2) \
330 | ((reloc3) ? (1 << 1) : 0) \
332 #define RELAX_OLD(i) (((i) >> 24) & 0xff)
333 #define RELAX_NEW(i) (((i) >> 16) & 0xff)
334 #define RELAX_RELOC1(i) ((bfd_vma)(((i) >> 9) & 0x7f) - 64)
335 #define RELAX_RELOC2(i) ((bfd_vma)(((i) >> 2) & 0x7f) - 64)
336 #define RELAX_RELOC3(i) (((i) >> 1) & 1)
337 #define RELAX_WARN(i) ((i) & 1)
339 /* Prototypes for static functions. */
342 #define internalError() \
343 as_fatal ("internal Error, line %d, %s", __LINE__, __FILE__)
345 #define internalError() as_fatal ("MIPS internal Error");
348 static int insn_uses_reg
PARAMS ((struct mips_cl_insn
*ip
,
349 unsigned int reg
, int fpr
));
350 static void append_insn
PARAMS ((char *place
,
351 struct mips_cl_insn
* ip
,
353 bfd_reloc_code_real_type r
));
354 static void mips_no_prev_insn
PARAMS ((void));
355 static void mips_emit_delays
PARAMS ((void));
356 static void macro_build
PARAMS ((char *place
, int *counter
, expressionS
* ep
,
357 const char *name
, const char *fmt
,
359 static void macro_build_lui
PARAMS ((char *place
, int *counter
,
360 expressionS
* ep
, int regnum
));
361 static void set_at
PARAMS ((int *counter
, int reg
, int unsignedp
));
362 static void check_absolute_expr
PARAMS ((struct mips_cl_insn
* ip
,
364 static void load_register
PARAMS ((int *counter
, int reg
, expressionS
* ep
));
365 static void load_address
PARAMS ((int *counter
, int reg
, expressionS
*ep
));
366 static void macro
PARAMS ((struct mips_cl_insn
* ip
));
367 #ifdef LOSING_COMPILER
368 static void macro2
PARAMS ((struct mips_cl_insn
* ip
));
370 static void mips_ip
PARAMS ((char *str
, struct mips_cl_insn
* ip
));
371 static int my_getSmallExpression
PARAMS ((expressionS
* ep
, char *str
));
372 static void my_getExpression
PARAMS ((expressionS
* ep
, char *str
));
373 static symbolS
*get_symbol
PARAMS ((void));
374 static void mips_align
PARAMS ((int to
, int fill
, symbolS
*label
));
375 static void s_align
PARAMS ((int));
376 static void s_stringer
PARAMS ((int));
377 static void s_change_sec
PARAMS ((int));
378 static void s_cons
PARAMS ((int));
379 static void s_err
PARAMS ((int));
380 static void s_extern
PARAMS ((int));
381 static void s_float_cons
PARAMS ((int));
382 static void s_mips_globl
PARAMS ((int));
383 static void s_option
PARAMS ((int));
384 static void s_mipsset
PARAMS ((int));
385 static void s_mips_space
PARAMS ((int));
386 static void s_abicalls
PARAMS ((int));
387 static void s_cpload
PARAMS ((int));
388 static void s_cprestore
PARAMS ((int));
389 static void s_gpword
PARAMS ((int));
390 static void s_cpadd
PARAMS ((int));
391 #ifndef ECOFF_DEBUGGING
392 static void md_obj_begin
PARAMS ((void));
393 static void md_obj_end
PARAMS ((void));
394 static long get_number
PARAMS ((void));
395 static void s_ent
PARAMS ((int));
396 static void s_mipsend
PARAMS ((int));
397 static void s_file
PARAMS ((int));
399 static void s_frame
PARAMS ((int));
400 static void s_loc
PARAMS ((int));
401 static void s_mask
PARAMS ((char));
405 static void s_elf_section
PARAMS ((int));
410 The following pseudo-ops from the Kane and Heinrich MIPS book
411 should be defined here, but are currently unsupported: .alias,
412 .galive, .gjaldef, .gjrlive, .livereg, .noalias.
414 The following pseudo-ops from the Kane and Heinrich MIPS book are
415 specific to the type of debugging information being generated, and
416 should be defined by the object format: .aent, .begin, .bend,
417 .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp,
420 The following pseudo-ops from the Kane and Heinrich MIPS book are
421 not MIPS CPU specific, but are also not specific to the object file
422 format. This file is probably the best place to define them, but
423 they are not currently supported: .asm0, .endr, .lab, .repeat,
424 .struct, .weakext. */
426 const pseudo_typeS md_pseudo_table
[] =
428 /* MIPS specific pseudo-ops. */
429 {"option", s_option
, 0},
430 {"set", s_mipsset
, 0},
431 {"rdata", s_change_sec
, 'r'},
432 {"sdata", s_change_sec
, 's'},
433 {"livereg", s_ignore
, 0},
434 { "abicalls", s_abicalls
, 0},
435 { "cpload", s_cpload
, 0},
436 { "cprestore", s_cprestore
, 0},
437 { "gpword", s_gpword
, 0},
438 { "cpadd", s_cpadd
, 0},
440 /* Relatively generic pseudo-ops that happen to be used on MIPS
442 {"asciiz", s_stringer
, 1},
443 {"bss", s_change_sec
, 'b'},
446 {"dword", s_cons
, 3},
448 /* These pseudo-ops are defined in read.c, but must be overridden
449 here for one reason or another. */
450 {"align", s_align
, 0},
451 {"ascii", s_stringer
, 0},
452 {"asciz", s_stringer
, 1},
454 {"data", s_change_sec
, 'd'},
455 {"double", s_float_cons
, 'd'},
456 {"extern", s_extern
, 0},
457 {"float", s_float_cons
, 'f'},
458 {"globl", s_mips_globl
, 0},
459 {"global", s_mips_globl
, 0},
460 {"hword", s_cons
, 1},
465 {"short", s_cons
, 1},
466 {"single", s_float_cons
, 'f'},
467 {"space", s_mips_space
, 0},
468 {"text", s_change_sec
, 't'},
471 #ifndef ECOFF_DEBUGGING
472 /* These pseudo-ops should be defined by the object file format.
473 However, a.out doesn't support them, so we have versions here. */
475 {"bgnb", s_ignore
, 0},
476 {"end", s_mipsend
, 0},
477 {"endb", s_ignore
, 0},
480 {"fmask", s_ignore
, 'F'},
481 {"frame", s_ignore
, 0},
482 {"loc", s_ignore
, 0},
483 {"mask", s_ignore
, 'R'},
484 {"verstamp", s_ignore
, 0},
488 /* We need to tweak the ELF ".section" pseudo-op a bit. */
489 {"section", s_elf_section
, 0},
491 /* Redirect additional ELF data allocation pseudo-ops. */
492 {"2byte", s_cons
, 2},
493 {"4byte", s_cons
, 4},
494 {"8byte", s_cons
, 8},
501 const relax_typeS md_relax_table
[] =
506 static char *expr_end
;
508 static expressionS imm_expr
;
509 static expressionS offset_expr
;
510 static bfd_reloc_code_real_type imm_reloc
;
511 static bfd_reloc_code_real_type offset_reloc
;
513 /* FIXME: This should be handled in a different way. */
514 extern int target_big_endian
;
517 * This function is called once, at assembler startup time. It should
518 * set up all the tables, etc. that the MD part of the assembler will need.
524 register const char *retval
= NULL
;
525 register unsigned int i
= 0;
533 if (strcmp (cpu
+ (sizeof TARGET_CPU
) - 3, "el") == 0)
535 a
= xmalloc (sizeof TARGET_CPU
);
536 strcpy (a
, TARGET_CPU
);
537 a
[(sizeof TARGET_CPU
) - 3] = '\0';
541 if (strcmp (cpu
, "mips") == 0)
547 else if (strcmp (cpu
, "r6000") == 0
548 || strcmp (cpu
, "mips2") == 0)
554 else if (strcmp (cpu
, "mips64") == 0
555 || strcmp (cpu
, "r4000") == 0
556 || strcmp (cpu
, "mips3") == 0)
562 else if (strcmp (cpu
, "r4400") == 0)
568 else if (strcmp (cpu
, "mips64orion") == 0
569 || strcmp (cpu
, "r4600") == 0)
575 else if (strcmp (cpu
, "r4650") == 0)
597 if (mips_isa
< 2 && mips_trap
)
598 as_bad ("trap exception not supported at ISA 1");
603 ok
= bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, 3000);
606 ok
= bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, 6000);
609 ok
= bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, 4000);
613 as_warn ("Could not set architecture and machine");
615 file_mips_isa
= mips_isa
;
617 op_hash
= hash_new ();
619 for (i
= 0; i
< NUMOPCODES
;)
621 const char *name
= mips_opcodes
[i
].name
;
623 retval
= hash_insert (op_hash
, name
, (PTR
) &mips_opcodes
[i
]);
626 fprintf (stderr
, "internal error: can't hash `%s': %s\n",
627 mips_opcodes
[i
].name
, retval
);
628 as_fatal ("Broken assembler. No assembly attempted.");
632 if (mips_opcodes
[i
].pinfo
!= INSN_MACRO
633 && ((mips_opcodes
[i
].match
& mips_opcodes
[i
].mask
)
634 != mips_opcodes
[i
].match
))
636 fprintf (stderr
, "internal error: bad opcode: `%s' \"%s\"\n",
637 mips_opcodes
[i
].name
, mips_opcodes
[i
].args
);
638 as_fatal ("Broken assembler. No assembly attempted.");
642 while ((i
< NUMOPCODES
) && !strcmp (mips_opcodes
[i
].name
, name
));
645 mips_no_prev_insn ();
653 /* set the default alignment for the text section (2**2) */
654 record_alignment (text_section
, 2);
656 /* FIXME: This should be handled in a different way. */
657 target_big_endian
= byte_order
== BIG_ENDIAN
;
660 bfd_set_gp_size (stdoutput
, g_switch_value
);
664 /* Sections must be aligned to 16 byte boundaries. */
665 (void) bfd_set_section_alignment (stdoutput
, text_section
, 4);
666 (void) bfd_set_section_alignment (stdoutput
, data_section
, 4);
667 (void) bfd_set_section_alignment (stdoutput
, bss_section
, 4);
669 /* Create a .reginfo section for register masks and a .mdebug
670 section for debugging information. */
678 sec
= subseg_new (".reginfo", (subsegT
) 0);
680 /* The ABI says this section should be loaded so that the running
681 program can access it. */
682 (void) bfd_set_section_flags (stdoutput
, sec
,
683 (SEC_ALLOC
| SEC_LOAD
684 | SEC_READONLY
| SEC_DATA
));
685 (void) bfd_set_section_alignment (stdoutput
, sec
, 2);
687 mips_regmask_frag
= frag_more (sizeof (Elf32_External_RegInfo
));
689 #ifdef ECOFF_DEBUGGING
690 sec
= subseg_new (".mdebug", (subsegT
) 0);
691 (void) bfd_set_section_flags (stdoutput
, sec
,
692 SEC_HAS_CONTENTS
| SEC_READONLY
);
693 (void) bfd_set_section_alignment (stdoutput
, sec
, 2);
696 subseg_set (seg
, subseg
);
700 #ifndef ECOFF_DEBUGGING
708 #ifndef ECOFF_DEBUGGING
717 struct mips_cl_insn insn
;
719 imm_expr
.X_op
= O_absent
;
720 offset_expr
.X_op
= O_absent
;
722 mips_ip (str
, &insn
);
725 as_bad ("%s `%s'", insn_error
, str
);
728 if (insn
.insn_mo
->pinfo
== INSN_MACRO
)
734 if (imm_expr
.X_op
!= O_absent
)
735 append_insn ((char *) NULL
, &insn
, &imm_expr
, imm_reloc
);
736 else if (offset_expr
.X_op
!= O_absent
)
737 append_insn ((char *) NULL
, &insn
, &offset_expr
, offset_reloc
);
739 append_insn ((char *) NULL
, &insn
, NULL
, BFD_RELOC_UNUSED
);
743 /* See whether instruction IP reads register REG. If FPR is non-zero,
744 REG is a floating point register. */
747 insn_uses_reg (ip
, reg
, fpr
)
748 struct mips_cl_insn
*ip
;
752 /* Don't report on general register 0, since it never changes. */
753 if (! fpr
&& reg
== 0)
758 /* If we are called with either $f0 or $f1, we must check $f0.
759 This is not optimal, because it will introduce an unnecessary
760 NOP between "lwc1 $f0" and "swc1 $f1". To fix this we would
761 need to distinguish reading both $f0 and $f1 or just one of
762 them. Note that we don't have to check the other way,
763 because there is no instruction that sets both $f0 and $f1
764 and requires a delay. */
765 if ((ip
->insn_mo
->pinfo
& INSN_READ_FPR_S
)
766 && (((ip
->insn_opcode
>> OP_SH_FS
) & OP_MASK_FS
)
767 == (reg
&~ (unsigned) 1)))
769 if ((ip
->insn_mo
->pinfo
& INSN_READ_FPR_T
)
770 && (((ip
->insn_opcode
>> OP_SH_FT
) & OP_MASK_FT
)
771 == (reg
&~ (unsigned) 1)))
776 if ((ip
->insn_mo
->pinfo
& INSN_READ_GPR_S
)
777 && ((ip
->insn_opcode
>> OP_SH_RS
) & OP_MASK_RS
) == reg
)
779 if ((ip
->insn_mo
->pinfo
& INSN_READ_GPR_T
)
780 && ((ip
->insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
) == reg
)
787 /* Output an instruction. PLACE is where to put the instruction; if
788 it is NULL, this uses frag_more to get room. IP is the instruction
789 information. ADDRESS_EXPR is an operand of the instruction to be
790 used with RELOC_TYPE. */
793 append_insn (place
, ip
, address_expr
, reloc_type
)
795 struct mips_cl_insn
*ip
;
796 expressionS
*address_expr
;
797 bfd_reloc_code_real_type reloc_type
;
799 register unsigned long prev_pinfo
, pinfo
;
804 prev_pinfo
= prev_insn
.insn_mo
->pinfo
;
805 pinfo
= ip
->insn_mo
->pinfo
;
807 if (place
== NULL
&& ! mips_noreorder
)
809 /* If the previous insn required any delay slots, see if we need
810 to insert a NOP or two. There are eight kinds of possible
811 hazards, of which an instruction can have at most one type.
812 (1) a load from memory delay
813 (2) a load from a coprocessor delay
814 (3) an unconditional branch delay
815 (4) a conditional branch delay
816 (5) a move to coprocessor register delay
817 (6) a load coprocessor register from memory delay
818 (7) a coprocessor condition code delay
819 (8) a HI/LO special register delay
821 There are a lot of optimizations we could do that we don't.
822 In particular, we do not, in general, reorder instructions.
823 If you use gcc with optimization, it will reorder
824 instructions and generally do much more optimization then we
825 do here; repeating all that work in the assembler would only
826 benefit hand written assembly code, and does not seem worth
829 /* This is how a NOP is emitted. */
830 #define emit_nop() md_number_to_chars (frag_more (4), 0, 4)
832 /* The previous insn might require a delay slot, depending upon
833 the contents of the current insn. */
834 if ((prev_pinfo
& INSN_LOAD_COPROC_DELAY
)
836 && (prev_pinfo
& INSN_LOAD_MEMORY_DELAY
)))
838 /* A load from a coprocessor or from memory. All load
839 delays delay the use of general register rt for one
840 instruction on the r3000. The r6000 and r4000 use
842 know (prev_pinfo
& INSN_WRITE_GPR_T
);
843 if (mips_optimize
== 0
844 || insn_uses_reg (ip
,
845 ((prev_insn
.insn_opcode
>> OP_SH_RT
)
850 else if ((prev_pinfo
& INSN_COPROC_MOVE_DELAY
)
852 && (prev_pinfo
& INSN_COPROC_MEMORY_DELAY
)))
854 /* A generic coprocessor delay. The previous instruction
855 modified a coprocessor general or control register. If
856 it modified a control register, we need to avoid any
857 coprocessor instruction (this is probably not always
858 required, but it sometimes is). If it modified a general
859 register, we avoid using that register.
861 On the r6000 and r4000 loading a coprocessor register
862 from memory is interlocked, and does not require a delay.
864 This case is not handled very well. There is no special
865 knowledge of CP0 handling, and the coprocessors other
866 than the floating point unit are not distinguished at
868 if (prev_pinfo
& INSN_WRITE_FPR_T
)
870 if (mips_optimize
== 0
871 || insn_uses_reg (ip
,
872 ((prev_insn
.insn_opcode
>> OP_SH_FT
)
877 else if (prev_pinfo
& INSN_WRITE_FPR_S
)
879 if (mips_optimize
== 0
880 || insn_uses_reg (ip
,
881 ((prev_insn
.insn_opcode
>> OP_SH_FS
)
888 /* We don't know exactly what the previous instruction
889 does. If the current instruction uses a coprocessor
890 register, we must insert a NOP. If previous
891 instruction may set the condition codes, and the
892 current instruction uses them, we must insert two
894 if (mips_optimize
== 0
895 || ((prev_pinfo
& INSN_WRITE_COND_CODE
)
896 && (pinfo
& INSN_READ_COND_CODE
)))
898 else if (pinfo
& INSN_COP
)
902 else if (prev_pinfo
& INSN_WRITE_COND_CODE
)
904 /* The previous instruction sets the coprocessor condition
905 codes, but does not require a general coprocessor delay
906 (this means it is a floating point comparison
907 instruction). If this instruction uses the condition
908 codes, we need to insert a single NOP. */
909 if (mips_optimize
== 0
910 || (pinfo
& INSN_READ_COND_CODE
))
913 else if (prev_pinfo
& INSN_READ_LO
)
915 /* The previous instruction reads the LO register; if the
916 current instruction writes to the LO register, we must
917 insert two NOPS. The R4650 has interlocks. */
919 && (mips_optimize
== 0
920 || (pinfo
& INSN_WRITE_LO
)))
923 else if (prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
925 /* The previous instruction reads the HI register; if the
926 current instruction writes to the HI register, we must
927 insert a NOP. The R4650 has interlocks. */
929 && (mips_optimize
== 0
930 || (pinfo
& INSN_WRITE_HI
)))
934 /* There are two cases which require two intervening
935 instructions: 1) setting the condition codes using a move to
936 coprocessor instruction which requires a general coprocessor
937 delay and then reading the condition codes 2) reading the HI
938 or LO register and then writing to it (except on the R4650,
939 which has interlocks). If we are not already emitting a NOP
940 instruction, we must check for these cases compared to the
941 instruction previous to the previous instruction. */
943 && (((prev_prev_insn
.insn_mo
->pinfo
& INSN_COPROC_MOVE_DELAY
)
944 && (prev_prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
)
945 && (pinfo
& INSN_READ_COND_CODE
))
946 || ((prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
)
947 && (pinfo
& INSN_WRITE_LO
)
949 || ((prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
950 && (pinfo
& INSN_WRITE_HI
)
954 /* If we are being given a nop instruction, don't bother with
955 one of the nops we would otherwise output. This will only
956 happen when a nop instruction is used with mips_optimize set
958 if (nops
> 0 && ip
->insn_opcode
== 0)
961 /* Now emit the right number of NOP instructions. */
966 for (i
= 0; i
< nops
; i
++)
970 listing_prev_line ();
971 /* We may be at the start of a variant frag. In case we
972 are, make sure there is enough space for the frag
973 after the frags created by listing_prev_line. The
974 argument to frag_grow here must be at least as large
975 as the argument to all other calls to frag_grow in
976 this file. We don't have to worry about being in the
977 middle of a variant frag, because the variants insert
978 all needed nop instructions themselves. */
981 if (insn_label
!= NULL
)
983 assert (S_GET_SEGMENT (insn_label
) == now_seg
);
984 insn_label
->sy_frag
= frag_now
;
985 S_SET_VALUE (insn_label
, (valueT
) frag_now_fix ());
995 if (address_expr
!= NULL
)
997 if (address_expr
->X_op
== O_constant
)
1002 ip
->insn_opcode
|= address_expr
->X_add_number
;
1005 case BFD_RELOC_LO16
:
1006 ip
->insn_opcode
|= address_expr
->X_add_number
& 0xffff;
1009 case BFD_RELOC_MIPS_JMP
:
1010 case BFD_RELOC_16_PCREL_S2
:
1019 assert (reloc_type
!= BFD_RELOC_UNUSED
);
1021 /* Don't generate a reloc if we are writing into a variant
1024 fixp
= fix_new_exp (frag_now
, f
- frag_now
->fr_literal
, 4,
1026 reloc_type
== BFD_RELOC_16_PCREL_S2
,
1031 md_number_to_chars (f
, ip
->insn_opcode
, 4);
1033 /* Update the register mask information. */
1034 if (pinfo
& INSN_WRITE_GPR_D
)
1035 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
);
1036 if ((pinfo
& (INSN_WRITE_GPR_T
| INSN_READ_GPR_T
)) != 0)
1037 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
);
1038 if (pinfo
& INSN_READ_GPR_S
)
1039 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> OP_SH_RS
) & OP_MASK_RS
);
1040 if (pinfo
& INSN_WRITE_GPR_31
)
1041 mips_gprmask
|= 1 << 31;
1042 if (pinfo
& INSN_WRITE_FPR_D
)
1043 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FD
) & OP_MASK_FD
);
1044 if ((pinfo
& (INSN_WRITE_FPR_S
| INSN_READ_FPR_S
)) != 0)
1045 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FS
) & OP_MASK_FS
);
1046 if ((pinfo
& (INSN_WRITE_FPR_T
| INSN_READ_FPR_T
)) != 0)
1047 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FT
) & OP_MASK_FT
);
1048 if (pinfo
& INSN_COP
)
1050 /* We don't keep enough information to sort these cases out. */
1052 /* Never set the bit for $0, which is always zero. */
1053 mips_gprmask
&=~ 1 << 0;
1055 if (place
== NULL
&& ! mips_noreorder
)
1057 /* Filling the branch delay slot is more complex. We try to
1058 switch the branch with the previous instruction, which we can
1059 do if the previous instruction does not set up a condition
1060 that the branch tests and if the branch is not itself the
1061 target of any branch. */
1062 if ((pinfo
& INSN_UNCOND_BRANCH_DELAY
)
1063 || (pinfo
& INSN_COND_BRANCH_DELAY
))
1065 if (mips_optimize
< 2
1066 /* If we have seen .set volatile or .set nomove, don't
1069 /* If we had to emit any NOP instructions, then we
1070 already know we can not swap. */
1072 /* If we don't even know the previous insn, we can not
1074 || ! prev_insn_valid
1075 /* If the previous insn is already in a branch delay
1076 slot, then we can not swap. */
1077 || prev_insn_is_delay_slot
1078 /* If the previous previous insn was in a .set
1079 noreorder, we can't swap. Actually, the MIPS
1080 assembler will swap in this situation. However, gcc
1081 configured -with-gnu-as will generate code like
1087 in which we can not swap the bne and INSN. If gcc is
1088 not configured -with-gnu-as, it does not output the
1089 .set pseudo-ops. We don't have to check
1090 prev_insn_unreordered, because prev_insn_valid will
1091 be 0 in that case. We don't want to use
1092 prev_prev_insn_valid, because we do want to be able
1093 to swap at the start of a function. */
1094 || prev_prev_insn_unreordered
1095 /* If the branch is itself the target of a branch, we
1096 can not swap. We cheat on this; all we check for is
1097 whether there is a label on this instruction. If
1098 there are any branches to anything other than a
1099 label, users must use .set noreorder. */
1100 || insn_label
!= NULL
1101 /* If the previous instruction is in a variant frag, we
1102 can not do the swap. */
1103 || prev_insn_frag
->fr_type
== rs_machine_dependent
1104 /* If the branch reads the condition codes, we don't
1105 even try to swap, because in the sequence
1110 we can not swap, and I don't feel like handling that
1112 || (pinfo
& INSN_READ_COND_CODE
)
1113 /* We can not swap with an instruction that requires a
1114 delay slot, becase the target of the branch might
1115 interfere with that instruction. */
1117 & (INSN_LOAD_COPROC_DELAY
1118 | INSN_COPROC_MOVE_DELAY
1119 | INSN_WRITE_COND_CODE
))
1126 & (INSN_LOAD_MEMORY_DELAY
1127 | INSN_COPROC_MEMORY_DELAY
)))
1128 /* We can not swap with a branch instruction. */
1130 & (INSN_UNCOND_BRANCH_DELAY
1131 | INSN_COND_BRANCH_DELAY
1132 | INSN_COND_BRANCH_LIKELY
))
1133 /* We do not swap with a trap instruction, since it
1134 complicates trap handlers to have the trap
1135 instruction be in a delay slot. */
1136 || (prev_pinfo
& INSN_TRAP
)
1137 /* If the branch reads a register that the previous
1138 instruction sets, we can not swap. */
1139 || ((prev_pinfo
& INSN_WRITE_GPR_T
)
1140 && insn_uses_reg (ip
,
1141 ((prev_insn
.insn_opcode
>> OP_SH_RT
)
1144 || ((prev_pinfo
& INSN_WRITE_GPR_D
)
1145 && insn_uses_reg (ip
,
1146 ((prev_insn
.insn_opcode
>> OP_SH_RD
)
1149 /* If the branch writes a register that the previous
1150 instruction sets, we can not swap (we know that
1151 branches write only to RD or to $31). */
1152 || ((prev_pinfo
& INSN_WRITE_GPR_T
)
1153 && (((pinfo
& INSN_WRITE_GPR_D
)
1154 && (((prev_insn
.insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
)
1155 == ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)))
1156 || ((pinfo
& INSN_WRITE_GPR_31
)
1157 && (((prev_insn
.insn_opcode
>> OP_SH_RT
)
1160 || ((prev_pinfo
& INSN_WRITE_GPR_D
)
1161 && (((pinfo
& INSN_WRITE_GPR_D
)
1162 && (((prev_insn
.insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)
1163 == ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)))
1164 || ((pinfo
& INSN_WRITE_GPR_31
)
1165 && (((prev_insn
.insn_opcode
>> OP_SH_RD
)
1168 /* If the branch writes a register that the previous
1169 instruction reads, we can not swap (we know that
1170 branches only write to RD or to $31). */
1171 || ((pinfo
& INSN_WRITE_GPR_D
)
1172 && insn_uses_reg (&prev_insn
,
1173 ((ip
->insn_opcode
>> OP_SH_RD
)
1176 || ((pinfo
& INSN_WRITE_GPR_31
)
1177 && insn_uses_reg (&prev_insn
, 31, 0))
1178 /* If we are generating embedded PIC code, the branch
1179 might be expanded into a sequence which uses $at, so
1180 we can't swap with an instruction which reads it. */
1181 || (mips_pic
== EMBEDDED_PIC
1182 && insn_uses_reg (&prev_insn
, AT
, 0))
1183 /* If the previous previous instruction has a load
1184 delay, and sets a register that the branch reads, we
1186 || (((prev_prev_insn
.insn_mo
->pinfo
& INSN_LOAD_COPROC_DELAY
)
1188 && (prev_prev_insn
.insn_mo
->pinfo
1189 & INSN_LOAD_MEMORY_DELAY
)))
1190 && insn_uses_reg (ip
,
1191 ((prev_prev_insn
.insn_opcode
>> OP_SH_RT
)
1195 /* We could do even better for unconditional branches to
1196 portions of this object file; we could pick up the
1197 instruction at the destination, put it in the delay
1198 slot, and bump the destination address. */
1200 /* Update the previous insn information. */
1201 prev_prev_insn
= *ip
;
1202 prev_insn
.insn_mo
= &dummy_opcode
;
1209 /* It looks like we can actually do the swap. */
1210 prev_f
= prev_insn_frag
->fr_literal
+ prev_insn_where
;
1211 memcpy (temp
, prev_f
, 4);
1212 memcpy (prev_f
, f
, 4);
1213 memcpy (f
, temp
, 4);
1216 prev_insn_fixp
->fx_frag
= frag_now
;
1217 prev_insn_fixp
->fx_where
= f
- frag_now
->fr_literal
;
1221 fixp
->fx_frag
= prev_insn_frag
;
1222 fixp
->fx_where
= prev_insn_where
;
1224 /* Update the previous insn information; leave prev_insn
1226 prev_prev_insn
= *ip
;
1228 prev_insn_is_delay_slot
= 1;
1230 /* If that was an unconditional branch, forget the previous
1231 insn information. */
1232 if (pinfo
& INSN_UNCOND_BRANCH_DELAY
)
1234 prev_prev_insn
.insn_mo
= &dummy_opcode
;
1235 prev_insn
.insn_mo
= &dummy_opcode
;
1238 else if (pinfo
& INSN_COND_BRANCH_LIKELY
)
1240 /* We don't yet optimize a branch likely. What we should do
1241 is look at the target, copy the instruction found there
1242 into the delay slot, and increment the branch to jump to
1243 the next instruction. */
1245 /* Update the previous insn information. */
1246 prev_prev_insn
= *ip
;
1247 prev_insn
.insn_mo
= &dummy_opcode
;
1251 /* Update the previous insn information. */
1253 prev_prev_insn
.insn_mo
= &dummy_opcode
;
1255 prev_prev_insn
= prev_insn
;
1258 /* Any time we see a branch, we always fill the delay slot
1259 immediately; since this insn is not a branch, we know it
1260 is not in a delay slot. */
1261 prev_insn_is_delay_slot
= 0;
1264 prev_prev_insn_unreordered
= prev_insn_unreordered
;
1265 prev_insn_unreordered
= 0;
1266 prev_insn_frag
= frag_now
;
1267 prev_insn_where
= f
- frag_now
->fr_literal
;
1268 prev_insn_fixp
= fixp
;
1269 prev_insn_valid
= 1;
1272 /* We just output an insn, so the next one doesn't have a label. */
1276 /* This function forgets that there was any previous instruction or
1280 mips_no_prev_insn ()
1282 prev_insn
.insn_mo
= &dummy_opcode
;
1283 prev_prev_insn
.insn_mo
= &dummy_opcode
;
1284 prev_insn_valid
= 0;
1285 prev_insn_is_delay_slot
= 0;
1286 prev_insn_unreordered
= 0;
1287 prev_prev_insn_unreordered
= 0;
1291 /* This function must be called whenever we turn on noreorder or emit
1292 something other than instructions. It inserts any NOPS which might
1293 be needed by the previous instruction, and clears the information
1294 kept for the previous instructions. */
1299 if (! mips_noreorder
)
1304 if ((prev_insn
.insn_mo
->pinfo
1305 & (INSN_LOAD_COPROC_DELAY
1306 | INSN_COPROC_MOVE_DELAY
1307 | INSN_WRITE_COND_CODE
))
1309 && (prev_insn
.insn_mo
->pinfo
1313 && (prev_insn
.insn_mo
->pinfo
1314 & (INSN_LOAD_MEMORY_DELAY
1315 | INSN_COPROC_MEMORY_DELAY
))))
1318 if ((prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
)
1320 && ((prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
1321 || (prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
))))
1324 else if ((prev_prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
)
1326 && ((prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
1327 || (prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
))))
1332 if (insn_label
!= NULL
)
1334 assert (S_GET_SEGMENT (insn_label
) == now_seg
);
1335 insn_label
->sy_frag
= frag_now
;
1336 S_SET_VALUE (insn_label
, (valueT
) frag_now_fix ());
1341 mips_no_prev_insn ();
1344 /* Build an instruction created by a macro expansion. This is passed
1345 a pointer to the count of instructions created so far, an
1346 expression, the name of the instruction to build, an operand format
1347 string, and corresponding arguments. */
1351 macro_build (char *place
,
1357 #else /* ! defined (NO_STDARG) */
1359 macro_build (place
, counter
, ep
, name
, fmt
, va_alist
)
1366 #endif /* ! defined (NO_STDARG) */
1368 struct mips_cl_insn insn
;
1369 bfd_reloc_code_real_type r
;
1373 va_start (args
, fmt
);
1379 * If the macro is about to expand into a second instruction,
1380 * print a warning if needed. We need to pass ip as a parameter
1381 * to generate a better warning message here...
1383 if (mips_warn_about_macros
&& place
== NULL
&& *counter
== 1)
1384 as_warn ("Macro instruction expanded into multiple instructions");
1387 *counter
+= 1; /* bump instruction counter */
1389 r
= BFD_RELOC_UNUSED
;
1390 insn
.insn_mo
= (struct mips_opcode
*) hash_find (op_hash
, name
);
1391 assert (insn
.insn_mo
);
1392 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
1394 while (strcmp (fmt
, insn
.insn_mo
->args
) != 0
1395 || insn
.insn_mo
->pinfo
== INSN_MACRO
)
1398 assert (insn
.insn_mo
->name
);
1399 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
1401 insn
.insn_opcode
= insn
.insn_mo
->match
;
1417 insn
.insn_opcode
|= va_arg (args
, int) << 16;
1423 insn
.insn_opcode
|= va_arg (args
, int) << 16;
1428 insn
.insn_opcode
|= va_arg (args
, int) << 11;
1433 insn
.insn_opcode
|= va_arg (args
, int) << 11;
1440 insn
.insn_opcode
|= va_arg (args
, int) << 6;
1444 insn
.insn_opcode
|= va_arg (args
, int) << 6;
1448 insn
.insn_opcode
|= va_arg (args
, int) << 6;
1455 insn
.insn_opcode
|= va_arg (args
, int) << 21;
1461 r
= (bfd_reloc_code_real_type
) va_arg (args
, int);
1462 assert (r
== BFD_RELOC_MIPS_GPREL
1463 || r
== BFD_RELOC_MIPS_LITERAL
1464 || r
== BFD_RELOC_LO16
1465 || r
== BFD_RELOC_MIPS_GOT16
1466 || r
== BFD_RELOC_MIPS_CALL16
1467 || (ep
->X_op
== O_subtract
1468 && now_seg
== text_section
1469 && r
== BFD_RELOC_PCREL_LO16
));
1473 r
= (bfd_reloc_code_real_type
) va_arg (args
, int);
1475 && (ep
->X_op
== O_constant
1476 || (ep
->X_op
== O_symbol
1477 && (r
== BFD_RELOC_HI16_S
1478 || r
== BFD_RELOC_HI16
))
1479 || (ep
->X_op
== O_subtract
1480 && now_seg
== text_section
1481 && r
== BFD_RELOC_PCREL_HI16_S
)));
1482 if (ep
->X_op
== O_constant
)
1484 insn
.insn_opcode
|= (ep
->X_add_number
>> 16) & 0xffff;
1486 r
= BFD_RELOC_UNUSED
;
1491 assert (ep
!= NULL
);
1493 * This allows macro() to pass an immediate expression for
1494 * creating short branches without creating a symbol.
1495 * Note that the expression still might come from the assembly
1496 * input, in which case the value is not checked for range nor
1497 * is a relocation entry generated (yuck).
1499 if (ep
->X_op
== O_constant
)
1501 insn
.insn_opcode
|= (ep
->X_add_number
>> 2) & 0xffff;
1505 r
= BFD_RELOC_16_PCREL_S2
;
1509 assert (ep
!= NULL
);
1510 r
= BFD_RELOC_MIPS_JMP
;
1519 assert (r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
1521 append_insn (place
, &insn
, ep
, r
);
1525 * Generate a "lui" instruction.
1528 macro_build_lui (place
, counter
, ep
, regnum
)
1534 expressionS high_expr
;
1535 struct mips_cl_insn insn
;
1536 bfd_reloc_code_real_type r
;
1537 CONST
char *name
= "lui";
1538 CONST
char *fmt
= "t,u";
1544 high_expr
.X_op
= O_constant
;
1545 high_expr
.X_add_number
= 0;
1548 if (high_expr
.X_op
== O_constant
)
1550 /* we can compute the instruction now without a relocation entry */
1551 if (high_expr
.X_add_number
& 0x8000)
1552 high_expr
.X_add_number
+= 0x10000;
1553 high_expr
.X_add_number
=
1554 ((unsigned long) high_expr
.X_add_number
>> 16) & 0xffff;
1555 r
= BFD_RELOC_UNUSED
;
1559 assert (ep
->X_op
== O_symbol
);
1560 /* _gp_disp is a special case, used from s_cpload. */
1561 assert (mips_pic
== NO_PIC
1562 || strcmp (S_GET_NAME (ep
->X_add_symbol
), "_gp_disp") == 0);
1563 r
= BFD_RELOC_HI16_S
;
1567 * If the macro is about to expand into a second instruction,
1568 * print a warning if needed. We need to pass ip as a parameter
1569 * to generate a better warning message here...
1571 if (mips_warn_about_macros
&& place
== NULL
&& *counter
== 1)
1572 as_warn ("Macro instruction expanded into multiple instructions");
1575 *counter
+= 1; /* bump instruction counter */
1577 insn
.insn_mo
= (struct mips_opcode
*) hash_find (op_hash
, name
);
1578 assert (insn
.insn_mo
);
1579 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
1580 assert (strcmp (fmt
, insn
.insn_mo
->args
) == 0);
1582 insn
.insn_opcode
= insn
.insn_mo
->match
| (regnum
<< OP_SH_RT
);
1583 if (r
== BFD_RELOC_UNUSED
)
1585 insn
.insn_opcode
|= high_expr
.X_add_number
;
1586 append_insn (place
, &insn
, NULL
, r
);
1589 append_insn (place
, &insn
, &high_expr
, r
);
1593 * Generates code to set the $at register to true (one)
1594 * if reg is less than the immediate expression.
1597 set_at (counter
, reg
, unsignedp
)
1602 if (imm_expr
.X_add_number
>= -0x8000 && imm_expr
.X_add_number
< 0x8000)
1603 macro_build ((char *) NULL
, counter
, &imm_expr
,
1604 unsignedp
? "sltiu" : "slti",
1605 "t,r,j", AT
, reg
, (int) BFD_RELOC_LO16
);
1608 load_register (counter
, AT
, &imm_expr
);
1609 macro_build ((char *) NULL
, counter
, NULL
,
1610 unsignedp
? "sltu" : "slt",
1611 "d,v,t", AT
, reg
, AT
);
1615 /* Warn if an expression is not a constant. */
1618 check_absolute_expr (ip
, ex
)
1619 struct mips_cl_insn
*ip
;
1622 if (ex
->X_op
!= O_constant
)
1623 as_warn ("Instruction %s requires absolute expression", ip
->insn_mo
->name
);
1627 * This routine generates the least number of instructions neccessary to load
1628 * an absolute expression value into a register.
1631 load_register (counter
, reg
, ep
)
1637 expressionS hi32
, lo32
, tmp
;
1639 if (ep
->X_op
!= O_big
)
1641 assert (ep
->X_op
== O_constant
);
1642 if (ep
->X_add_number
>= -0x8000 && ep
->X_add_number
< 0x8000)
1644 /* We can handle 16 bit signed values with an addiu to
1645 $zero. No need to ever use daddiu here, since $zero and
1646 the result are always correct in 32 bit mode. */
1647 macro_build ((char *) NULL
, counter
, ep
, "addiu", "t,r,j", reg
, 0,
1648 (int) BFD_RELOC_LO16
);
1651 else if (ep
->X_add_number
>= 0 && ep
->X_add_number
< 0x10000)
1653 /* We can handle 16 bit unsigned values with an ori to
1655 macro_build ((char *) NULL
, counter
, ep
, "ori", "t,r,i", reg
, 0,
1656 (int) BFD_RELOC_LO16
);
1659 else if (((ep
->X_add_number
&~ (offsetT
) 0x7fffffff) == 0
1660 || ((ep
->X_add_number
&~ (offsetT
) 0x7fffffff)
1661 == ~ (offsetT
) 0x7fffffff))
1664 || sizeof (ep
->X_add_number
) > 4
1665 || (ep
->X_add_number
& 0x80000000) == 0))
1667 /* 32 bit values require an lui. */
1668 macro_build ((char *) NULL
, counter
, ep
, "lui", "t,u", reg
,
1669 (int) BFD_RELOC_HI16
);
1670 if ((ep
->X_add_number
& 0xffff) != 0)
1671 macro_build ((char *) NULL
, counter
, ep
, "ori", "t,r,i", reg
, reg
,
1672 (int) BFD_RELOC_LO16
);
1677 /* 32 bit value with high bit set being loaded into a 64 bit
1678 register. We can't use lui, because that would
1679 incorrectly set the 32 high bits. */
1680 generic_bignum
[3] = 0;
1681 generic_bignum
[2] = 0;
1682 generic_bignum
[1] = (ep
->X_add_number
>> 16) & 0xffff;
1683 generic_bignum
[0] = ep
->X_add_number
& 0xffff;
1685 tmp
.X_add_number
= 4;
1690 /* The value is larger than 32 bits. */
1694 as_bad ("Number larger than 32 bits");
1695 macro_build ((char *) NULL
, counter
, ep
, "addiu", "t,r,j", reg
, 0,
1696 (int) BFD_RELOC_LO16
);
1700 if (ep
->X_op
!= O_big
)
1704 hi32
.X_add_number
>>= shift
;
1705 hi32
.X_add_number
&= 0xffffffff;
1706 if ((hi32
.X_add_number
& 0x80000000) != 0)
1707 hi32
.X_add_number
|= ~ (offsetT
) 0xffffffff;
1709 lo32
.X_add_number
&= 0xffffffff;
1713 assert (ep
->X_add_number
> 2);
1714 if (ep
->X_add_number
== 3)
1715 generic_bignum
[3] = 0;
1716 else if (ep
->X_add_number
> 4)
1717 as_bad ("Number larger than 64 bits");
1718 lo32
.X_op
= O_constant
;
1719 lo32
.X_add_number
= generic_bignum
[0] + (generic_bignum
[1] << 16);
1720 hi32
.X_op
= O_constant
;
1721 hi32
.X_add_number
= generic_bignum
[2] + (generic_bignum
[3] << 16);
1724 load_register (counter
, reg
, &hi32
);
1725 if ((lo32
.X_add_number
& 0xffff0000) == 0)
1726 macro_build ((char *) NULL
, counter
, NULL
, "dsll32", "d,w,<", reg
,
1732 macro_build ((char *) NULL
, counter
, NULL
, "dsll", "d,w,<", reg
,
1735 mid16
.X_add_number
>>= 16;
1736 macro_build ((char *) NULL
, counter
, &mid16
, "ori", "t,r,i", reg
,
1737 reg
, (int) BFD_RELOC_LO16
);
1738 macro_build ((char *) NULL
, counter
, NULL
, "dsll", "d,w,<", reg
,
1741 if ((lo32
.X_add_number
& 0xffff) != 0)
1742 macro_build ((char *) NULL
, counter
, &lo32
, "ori", "t,r,i", reg
, reg
,
1743 (int) BFD_RELOC_LO16
);
1746 /* Load an address into a register. */
1749 load_address (counter
, reg
, ep
)
1756 if (ep
->X_op
!= O_constant
1757 && ep
->X_op
!= O_symbol
)
1759 as_bad ("expression too complex");
1760 ep
->X_op
= O_constant
;
1763 if (ep
->X_op
== O_constant
)
1765 load_register (counter
, reg
, ep
);
1769 if (mips_pic
== NO_PIC
)
1771 /* If this is a reference to a GP relative symbol, we want
1772 addiu $reg,$gp,<sym> (BFD_RELOC_MIPS_GPREL)
1774 lui $reg,<sym> (BFD_RELOC_HI16_S)
1775 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
1776 If we have an addend, we always use the latter form. */
1777 if (ep
->X_add_number
!= 0)
1782 macro_build ((char *) NULL
, counter
, ep
,
1783 mips_isa
< 3 ? "addiu" : "daddiu",
1784 "t,r,j", reg
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
1785 p
= frag_var (rs_machine_dependent
, 8, 0,
1786 RELAX_ENCODE (4, 8, 0, 4, 0, mips_warn_about_macros
),
1787 ep
->X_add_symbol
, (long) 0, (char *) NULL
);
1789 macro_build_lui (p
, counter
, ep
, reg
);
1792 macro_build (p
, counter
, ep
,
1793 mips_isa
< 3 ? "addiu" : "daddiu",
1794 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
1796 else if (mips_pic
== SVR4_PIC
)
1800 /* If this is a reference to an external symbol, we want
1801 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
1803 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
1805 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
1806 If there is a constant, it must be added in after. */
1807 ex
.X_add_number
= ep
->X_add_number
;
1808 ep
->X_add_number
= 0;
1810 macro_build ((char *) NULL
, counter
, ep
,
1811 mips_isa
< 3 ? "lw" : "ld",
1812 "t,o(b)", reg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
1813 macro_build ((char *) NULL
, counter
, (expressionS
*) NULL
, "nop", "");
1814 p
= frag_var (rs_machine_dependent
, 4, 0,
1815 RELAX_ENCODE (0, 4, -8, 0, 0, mips_warn_about_macros
),
1816 ep
->X_add_symbol
, (long) 0, (char *) NULL
);
1817 macro_build (p
, counter
, ep
,
1818 mips_isa
< 3 ? "addiu" : "daddiu",
1819 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
1820 if (ex
.X_add_number
!= 0)
1822 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
1823 as_bad ("PIC code offset overflow (max 16 signed bits)");
1824 ex
.X_op
= O_constant
;
1825 macro_build (p
, counter
, &ex
,
1826 mips_isa
< 3 ? "addiu" : "daddiu",
1827 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
1830 else if (mips_pic
== EMBEDDED_PIC
)
1833 addiu $reg,$gp,<sym> (BFD_RELOC_MIPS_GPREL)
1835 macro_build ((char *) NULL
, counter
, ep
,
1836 mips_isa
< 3 ? "addiu" : "daddiu",
1837 "t,r,j", reg
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
1845 * This routine implements the seemingly endless macro or synthesized
1846 * instructions and addressing modes in the mips assembly language. Many
1847 * of these macros are simple and are similar to each other. These could
1848 * probably be handled by some kind of table or grammer aproach instead of
1849 * this verbose method. Others are not simple macros but are more like
1850 * optimizing code generation.
1851 * One interesting optimization is when several store macros appear
1852 * consecutivly that would load AT with the upper half of the same address.
1853 * The ensuing load upper instructions are ommited. This implies some kind
1854 * of global optimization. We currently only optimize within a single macro.
1855 * For many of the load and store macros if the address is specified as a
1856 * constant expression in the first 64k of memory (ie ld $2,0x4000c) we
1857 * first load register 'at' with zero and use it as the base register. The
1858 * mips assembler simply uses register $zero. Just one tiny optimization
1863 struct mips_cl_insn
*ip
;
1865 register int treg
, sreg
, dreg
, breg
;
1880 bfd_reloc_code_real_type r
;
1882 int hold_mips_optimize
;
1884 treg
= (ip
->insn_opcode
>> 16) & 0x1f;
1885 dreg
= (ip
->insn_opcode
>> 11) & 0x1f;
1886 sreg
= breg
= (ip
->insn_opcode
>> 21) & 0x1f;
1887 mask
= ip
->insn_mo
->mask
;
1889 expr1
.X_op
= O_constant
;
1890 expr1
.X_op_symbol
= NULL
;
1891 expr1
.X_add_symbol
= NULL
;
1892 expr1
.X_add_number
= 1;
1904 mips_emit_delays ();
1906 mips_any_noreorder
= 1;
1908 expr1
.X_add_number
= 8;
1909 macro_build ((char *) NULL
, &icnt
, &expr1
, "bgez", "s,p", sreg
);
1911 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
1913 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
, sreg
, 0);
1914 macro_build ((char *) NULL
, &icnt
, NULL
,
1915 dbl
? "dsub" : "sub",
1916 "d,v,t", dreg
, 0, sreg
);
1939 if (imm_expr
.X_add_number
>= -0x8000 && imm_expr
.X_add_number
< 0x8000)
1941 macro_build ((char *) NULL
, &icnt
, &imm_expr
, s
, "t,r,j", treg
, sreg
,
1942 (int) BFD_RELOC_LO16
);
1945 load_register (&icnt
, AT
, &imm_expr
);
1946 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "d,v,t", treg
, sreg
, AT
);
1965 if (imm_expr
.X_add_number
>= 0 && imm_expr
.X_add_number
< 0x10000)
1967 if (mask
!= M_NOR_I
)
1968 macro_build ((char *) NULL
, &icnt
, &imm_expr
, s
, "t,r,i", treg
,
1969 sreg
, (int) BFD_RELOC_LO16
);
1972 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "ori", "t,r,i",
1973 treg
, sreg
, (int) BFD_RELOC_LO16
);
1974 macro_build ((char *) NULL
, &icnt
, NULL
, "nor", "d,v,t",
1980 load_register (&icnt
, AT
, &imm_expr
);
1981 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "d,v,t", treg
, sreg
, AT
);
1998 if (imm_expr
.X_add_number
== 0)
2000 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "s,t,p", sreg
,
2004 load_register (&icnt
, AT
, &imm_expr
);
2005 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "s,t,p", sreg
, AT
);
2013 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2014 likely
? "bgezl" : "bgez",
2020 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2021 likely
? "blezl" : "blez",
2025 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", AT
, sreg
, treg
);
2026 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2027 likely
? "beql" : "beq",
2034 /* check for > max integer */
2035 maxnum
= 0x7fffffff;
2043 if (imm_expr
.X_add_number
>= maxnum
2044 && (mips_isa
< 3 || sizeof (maxnum
) > 4))
2047 /* result is always false */
2050 as_warn ("Branch %s is always false (nop)", ip
->insn_mo
->name
);
2051 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
2055 as_warn ("Branch likely %s is always false", ip
->insn_mo
->name
);
2056 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "bnel",
2061 imm_expr
.X_add_number
++;
2065 if (mask
== M_BGEL_I
)
2067 if (imm_expr
.X_add_number
== 0)
2069 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2070 likely
? "bgezl" : "bgez",
2074 if (imm_expr
.X_add_number
== 1)
2076 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2077 likely
? "bgtzl" : "bgtz",
2081 maxnum
= 0x7fffffff;
2089 maxnum
= - maxnum
- 1;
2090 if (imm_expr
.X_add_number
<= maxnum
2091 && (mips_isa
< 3 || sizeof (maxnum
) > 4))
2094 /* result is always true */
2095 as_warn ("Branch %s is always true", ip
->insn_mo
->name
);
2096 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "b", "p");
2099 set_at (&icnt
, sreg
, 0);
2100 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2101 likely
? "beql" : "beq",
2112 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2113 likely
? "beql" : "beq",
2117 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", AT
, sreg
,
2119 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2120 likely
? "beql" : "beq",
2127 if (sreg
== 0 || imm_expr
.X_add_number
== -1)
2129 imm_expr
.X_add_number
++;
2133 if (mask
== M_BGEUL_I
)
2135 if (imm_expr
.X_add_number
== 0)
2137 if (imm_expr
.X_add_number
== 1)
2139 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2140 likely
? "bnel" : "bne",
2144 set_at (&icnt
, sreg
, 1);
2145 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2146 likely
? "beql" : "beq",
2155 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2156 likely
? "bgtzl" : "bgtz",
2162 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2163 likely
? "bltzl" : "bltz",
2167 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", AT
, treg
, sreg
);
2168 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2169 likely
? "bnel" : "bne",
2178 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2179 likely
? "bnel" : "bne",
2185 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", AT
, treg
,
2187 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2188 likely
? "bnel" : "bne",
2197 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2198 likely
? "blezl" : "blez",
2204 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2205 likely
? "bgezl" : "bgez",
2209 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", AT
, treg
, sreg
);
2210 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2211 likely
? "beql" : "beq",
2218 maxnum
= 0x7fffffff;
2226 if (imm_expr
.X_add_number
>= maxnum
2227 && (mips_isa
< 3 || sizeof (maxnum
) > 4))
2229 imm_expr
.X_add_number
++;
2233 if (mask
== M_BLTL_I
)
2235 if (imm_expr
.X_add_number
== 0)
2237 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2238 likely
? "bltzl" : "bltz",
2242 if (imm_expr
.X_add_number
== 1)
2244 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2245 likely
? "blezl" : "blez",
2249 set_at (&icnt
, sreg
, 0);
2250 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2251 likely
? "bnel" : "bne",
2260 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2261 likely
? "beql" : "beq",
2267 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", AT
, treg
,
2269 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2270 likely
? "beql" : "beq",
2277 if (sreg
== 0 || imm_expr
.X_add_number
== -1)
2279 imm_expr
.X_add_number
++;
2283 if (mask
== M_BLTUL_I
)
2285 if (imm_expr
.X_add_number
== 0)
2287 if (imm_expr
.X_add_number
== 1)
2289 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2290 likely
? "beql" : "beq",
2294 set_at (&icnt
, sreg
, 1);
2295 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2296 likely
? "bnel" : "bne",
2305 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2306 likely
? "bltzl" : "bltz",
2312 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2313 likely
? "bgtzl" : "bgtz",
2317 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", AT
, sreg
, treg
);
2318 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2319 likely
? "bnel" : "bne",
2330 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2331 likely
? "bnel" : "bne",
2335 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", AT
, sreg
,
2337 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2338 likely
? "bnel" : "bne",
2354 as_warn ("Divide by zero.");
2356 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", 0, 0);
2358 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 7);
2362 mips_emit_delays ();
2364 mips_any_noreorder
= 1;
2365 macro_build ((char *) NULL
, &icnt
, NULL
,
2366 dbl
? "ddiv" : "div",
2367 "z,s,t", sreg
, treg
);
2369 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", treg
, 0);
2372 expr1
.X_add_number
= 8;
2373 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", treg
, 0);
2374 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
2375 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 7);
2377 expr1
.X_add_number
= -1;
2378 macro_build ((char *) NULL
, &icnt
, &expr1
,
2379 dbl
? "daddiu" : "addiu",
2380 "t,r,j", AT
, 0, (int) BFD_RELOC_LO16
);
2381 expr1
.X_add_number
= mips_trap
? (dbl
? 12 : 8) : (dbl
? 20 : 16);
2382 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", treg
, AT
);
2385 expr1
.X_add_number
= 1;
2386 macro_build ((char *) NULL
, &icnt
, &expr1
, "daddiu", "t,r,j", AT
, 0,
2387 (int) BFD_RELOC_LO16
);
2388 macro_build ((char *) NULL
, &icnt
, NULL
, "dsll32", "d,w,<", AT
, AT
,
2393 expr1
.X_add_number
= 0x80000000;
2394 macro_build ((char *) NULL
, &icnt
, &expr1
, "lui", "t,u", AT
,
2395 (int) BFD_RELOC_HI16
);
2398 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", sreg
, AT
);
2401 expr1
.X_add_number
= 8;
2402 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", sreg
, AT
);
2403 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
2404 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 6);
2407 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d", dreg
);
2446 if (imm_expr
.X_add_number
== 0)
2448 as_warn ("Divide by zero.");
2450 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", 0, 0);
2452 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 7);
2455 if (imm_expr
.X_add_number
== 1)
2457 if (strcmp (s2
, "mflo") == 0)
2458 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
,
2461 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
, 0);
2464 if (imm_expr
.X_add_number
== -1
2465 && s
[strlen (s
) - 1] != 'u')
2467 if (strcmp (s2
, "mflo") == 0)
2470 macro_build ((char *) NULL
, &icnt
, NULL
, "dneg", "d,w", dreg
,
2473 macro_build ((char *) NULL
, &icnt
, NULL
, "neg", "d,w", dreg
,
2477 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
, 0);
2481 load_register (&icnt
, AT
, &imm_expr
);
2482 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "z,s,t", sreg
, AT
);
2483 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "d", dreg
);
2502 mips_emit_delays ();
2504 mips_any_noreorder
= 1;
2505 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "z,s,t", sreg
, treg
);
2507 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", treg
, 0);
2510 expr1
.X_add_number
= 8;
2511 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", treg
, 0);
2512 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
2513 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 7);
2516 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "d", dreg
);
2520 /* Load the address of a symbol into a register. If breg is not
2521 zero, we then add a base register to it. */
2523 /* When generating embedded PIC code, we permit expressions of
2526 where bar is an address in the .text section. These are used
2527 when getting the addresses of functions. We don't permit
2528 X_add_number to be non-zero, because if the symbol is
2529 external the relaxing code needs to know that any addend is
2530 purely the offset to X_op_symbol. */
2531 if (mips_pic
== EMBEDDED_PIC
2532 && offset_expr
.X_op
== O_subtract
2533 && now_seg
== text_section
2534 && (offset_expr
.X_op_symbol
->sy_value
.X_op
== O_constant
2535 ? S_GET_SEGMENT (offset_expr
.X_op_symbol
) == text_section
2536 : (offset_expr
.X_op_symbol
->sy_value
.X_op
== O_symbol
2537 && (S_GET_SEGMENT (offset_expr
.X_op_symbol
2538 ->sy_value
.X_add_symbol
)
2541 && offset_expr
.X_add_number
== 0)
2543 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
2544 treg
, (int) BFD_RELOC_PCREL_HI16_S
);
2545 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2546 mips_isa
< 3 ? "addiu" : "daddiu",
2547 "t,r,j", treg
, treg
, (int) BFD_RELOC_PCREL_LO16
);
2551 if (offset_expr
.X_op
!= O_symbol
2552 && offset_expr
.X_op
!= O_constant
)
2554 as_bad ("expression too complex");
2555 offset_expr
.X_op
= O_constant
;
2569 if (offset_expr
.X_op
== O_constant
)
2570 load_register (&icnt
, tempreg
, &offset_expr
);
2571 else if (mips_pic
== NO_PIC
)
2573 /* If this is a reference to an GP relative symbol, we want
2574 addiu $tempreg,$gp,<sym> (BFD_RELOC_MIPS_GPREL)
2576 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
2577 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
2578 If we have a constant, we need two instructions anyhow,
2579 so we may as well always use the latter form. */
2580 if (offset_expr
.X_add_number
!= 0)
2585 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2586 mips_isa
< 3 ? "addiu" : "daddiu",
2587 "t,r,j", tempreg
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
2588 p
= frag_var (rs_machine_dependent
, 8, 0,
2589 RELAX_ENCODE (4, 8, 0, 4, 0,
2590 mips_warn_about_macros
),
2591 offset_expr
.X_add_symbol
, (long) 0,
2594 macro_build_lui (p
, &icnt
, &offset_expr
, tempreg
);
2597 macro_build (p
, &icnt
, &offset_expr
,
2598 mips_isa
< 3 ? "addiu" : "daddiu",
2599 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
2601 else if (mips_pic
== SVR4_PIC
)
2603 /* If this is a reference to an external symbol, and there
2604 is no constant, we want
2605 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
2606 For a local symbol, we want
2607 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
2609 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
2611 If we have a small constant, and this is a reference to
2612 an external symbol, we want
2613 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
2615 addiu $tempreg,$tempreg,<constant>
2616 For a local symbol, we want the same instruction
2617 sequence, but we output a BFD_RELOC_LO16 reloc on the
2620 If we have a large constant, and this is a reference to
2621 an external symbol, we want
2622 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
2623 lui $at,<hiconstant>
2624 addiu $at,$at,<loconstant>
2625 addu $tempreg,$tempreg,$at
2626 For a local symbol, we want the same instruction
2627 sequence, but we output a BFD_RELOC_LO16 reloc on the
2628 addiu instruction. */
2629 expr1
.X_add_number
= offset_expr
.X_add_number
;
2630 offset_expr
.X_add_number
= 0;
2632 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2633 mips_isa
< 3 ? "lw" : "ld",
2634 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
2635 if (expr1
.X_add_number
== 0)
2643 /* We're going to put in an addu instruction using
2644 tempreg, so we may as well insert the nop right
2646 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
2650 p
= frag_var (rs_machine_dependent
, 8 - off
, 0,
2651 RELAX_ENCODE (0, 8 - off
, -4 - off
, 4 - off
, 0,
2653 ? mips_warn_about_macros
2655 offset_expr
.X_add_symbol
, (long) 0,
2659 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
2662 macro_build (p
, &icnt
, &expr1
,
2663 mips_isa
< 3 ? "addiu" : "daddiu",
2664 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
2665 /* FIXME: If breg == 0, and the next instruction uses
2666 $tempreg, then if this variant case is used an extra
2667 nop will be generated. */
2669 else if (expr1
.X_add_number
>= -0x8000
2670 && expr1
.X_add_number
< 0x8000)
2672 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
2674 macro_build ((char *) NULL
, &icnt
, &expr1
,
2675 mips_isa
< 3 ? "addiu" : "daddiu",
2676 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
2677 (void) frag_var (rs_machine_dependent
, 0, 0,
2678 RELAX_ENCODE (0, 0, -12, -4, 0, 0),
2679 offset_expr
.X_add_symbol
, (long) 0,
2686 /* If we are going to add in a base register, and the
2687 target register and the base register are the same,
2688 then we are using AT as a temporary register. Since
2689 we want to load the constant into AT, we add our
2690 current AT (from the global offset table) and the
2691 register into the register now, and pretend we were
2692 not using a base register. */
2697 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
2699 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
2700 mips_isa
< 3 ? "addu" : "daddu",
2701 "d,v,t", treg
, AT
, breg
);
2707 /* Set mips_optimize around the lui instruction to avoid
2708 inserting an unnecessary nop after the lw. */
2709 hold_mips_optimize
= mips_optimize
;
2711 macro_build_lui ((char *) NULL
, &icnt
, &expr1
, AT
);
2712 mips_optimize
= hold_mips_optimize
;
2714 macro_build ((char *) NULL
, &icnt
, &expr1
,
2715 mips_isa
< 3 ? "addiu" : "daddiu",
2716 "t,r,j", AT
, AT
, (int) BFD_RELOC_LO16
);
2717 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
2718 mips_isa
< 3 ? "addu" : "daddu",
2719 "d,v,t", tempreg
, tempreg
, AT
);
2720 (void) frag_var (rs_machine_dependent
, 0, 0,
2721 RELAX_ENCODE (0, 0, -16 + off1
, -8, 0, 0),
2722 offset_expr
.X_add_symbol
, (long) 0,
2727 else if (mips_pic
== EMBEDDED_PIC
)
2730 addiu $tempreg,$gp,<sym> (BFD_RELOC_MIPS_GPREL)
2732 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2733 mips_isa
< 3 ? "addiu" : "daddiu",
2734 "t,r,j", tempreg
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
2740 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
2741 mips_isa
< 3 ? "addu" : "daddu",
2742 "d,v,t", treg
, tempreg
, breg
);
2750 /* The j instruction may not be used in PIC code, since it
2751 requires an absolute address. We convert it to a b
2753 if (mips_pic
== NO_PIC
)
2754 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "j", "a");
2756 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "b", "p");
2759 /* The jal instructions must be handled as macros because when
2760 generating PIC code they expand to multi-instruction
2761 sequences. Normally they are simple instructions. */
2766 if (mips_pic
== NO_PIC
2767 || mips_pic
== EMBEDDED_PIC
)
2768 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "jalr",
2770 else if (mips_pic
== SVR4_PIC
)
2772 if (sreg
!= PIC_CALL_REG
)
2773 as_warn ("MIPS PIC call to register other than $25");
2775 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "jalr",
2777 if (mips_cprestore_offset
< 0)
2778 as_warn ("No .cprestore pseudo-op used in PIC code");
2781 expr1
.X_add_number
= mips_cprestore_offset
;
2782 macro_build ((char *) NULL
, &icnt
, &expr1
,
2783 mips_isa
< 3 ? "lw" : "ld",
2784 "t,o(b)", GP
, (int) BFD_RELOC_LO16
, mips_frame_reg
);
2793 if (mips_pic
== NO_PIC
)
2794 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "jal", "a");
2795 else if (mips_pic
== SVR4_PIC
)
2797 /* If this is a reference to an external symbol, we want
2798 lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
2802 lw $gp,cprestore($sp)
2803 The cprestore value is set using the .cprestore
2804 pseudo-op. If the symbol is not external, we want
2805 lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
2807 addiu $25,$25,<sym> (BFD_RELOC_LO16)
2810 lw $gp,cprestore($sp)
2813 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2814 mips_isa
< 3 ? "lw" : "ld",
2815 "t,o(b)", PIC_CALL_REG
,
2816 (int) BFD_RELOC_MIPS_CALL16
, GP
);
2817 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
2818 p
= frag_var (rs_machine_dependent
, 4, 0,
2819 RELAX_ENCODE (0, 4, -8, 0, 0, 0),
2820 offset_expr
.X_add_symbol
, (long) 0, (char *) NULL
);
2821 macro_build (p
, &icnt
, &offset_expr
,
2822 mips_isa
< 3 ? "addiu" : "daddiu",
2823 "t,r,j", PIC_CALL_REG
, PIC_CALL_REG
,
2824 (int) BFD_RELOC_LO16
);
2825 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
2826 "jalr", "s", PIC_CALL_REG
);
2827 if (mips_cprestore_offset
< 0)
2828 as_warn ("No .cprestore pseudo-op used in PIC code");
2832 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
2834 expr1
.X_add_number
= mips_cprestore_offset
;
2835 macro_build ((char *) NULL
, &icnt
, &expr1
,
2836 mips_isa
< 3 ? "lw" : "ld",
2837 "t,o(b)", GP
, (int) BFD_RELOC_LO16
,
2841 else if (mips_pic
== EMBEDDED_PIC
)
2843 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "bal", "p");
2844 /* The linker may expand the call to a longer sequence which
2845 uses $at, so we must break rather than return. */
2921 if (breg
== treg
|| coproc
|| lr
)
2990 if (mask
== M_LWC1_AB
2991 || mask
== M_SWC1_AB
2992 || mask
== M_LDC1_AB
2993 || mask
== M_SDC1_AB
3002 if (offset_expr
.X_op
!= O_constant
3003 && offset_expr
.X_op
!= O_symbol
)
3005 as_bad ("expression too complex");
3006 offset_expr
.X_op
= O_constant
;
3009 /* A constant expression in PIC code can be handled just as it
3010 is in non PIC code. */
3011 if (mips_pic
== NO_PIC
3012 || offset_expr
.X_op
== O_constant
)
3014 /* If this is a reference to a GP relative symbol, and there
3015 is no base register, we want
3016 <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL)
3017 Otherwise, if there is no base register, we want
3018 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
3019 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
3020 If we have a constant, we need two instructions anyhow,
3021 so we always use the latter form.
3023 If we have a base register, and this is a reference to a
3024 GP relative symbol, we want
3025 addu $tempreg,$breg,$gp
3026 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GPREL)
3028 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
3029 addu $tempreg,$tempreg,$breg
3030 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
3031 With a constant we always use the latter case. */
3034 if (offset_expr
.X_add_number
!= 0)
3039 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
3040 treg
, (int) BFD_RELOC_MIPS_GPREL
, GP
);
3041 p
= frag_var (rs_machine_dependent
, 8, 0,
3042 RELAX_ENCODE (4, 8, 0, 4, 0,
3043 (mips_warn_about_macros
3044 || (used_at
&& mips_noat
))),
3045 offset_expr
.X_add_symbol
, (long) 0,
3049 macro_build_lui (p
, &icnt
, &offset_expr
, tempreg
);
3052 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
, treg
,
3053 (int) BFD_RELOC_LO16
, tempreg
);
3057 if (offset_expr
.X_add_number
!= 0)
3062 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3063 mips_isa
< 3 ? "addu" : "daddu",
3064 "d,v,t", tempreg
, breg
, GP
);
3065 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
3066 treg
, (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
3067 p
= frag_var (rs_machine_dependent
, 12, 0,
3068 RELAX_ENCODE (8, 12, 0, 8, 0, 0),
3069 offset_expr
.X_add_symbol
, (long) 0,
3072 macro_build_lui (p
, &icnt
, &offset_expr
, tempreg
);
3075 macro_build (p
, &icnt
, (expressionS
*) NULL
,
3076 mips_isa
< 3 ? "addu" : "daddu",
3077 "d,v,t", tempreg
, tempreg
, breg
);
3080 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
, treg
,
3081 (int) BFD_RELOC_LO16
, tempreg
);
3084 else if (mips_pic
== SVR4_PIC
)
3086 /* If this is a reference to an external symbol, we want
3087 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3089 <op> $treg,0($tempreg)
3091 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3093 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
3094 <op> $treg,0($tempreg)
3095 If there is a base register, we add it to $tempreg before
3096 the <op>. If there is a constant, we stick it in the
3097 <op> instruction. We don't handle constants larger than
3098 16 bits, because we have no way to load the upper 16 bits
3099 (actually, we could handle them for the subset of cases
3100 in which we are not using $at). */
3101 assert (offset_expr
.X_op
== O_symbol
);
3102 expr1
.X_add_number
= offset_expr
.X_add_number
;
3103 offset_expr
.X_add_number
= 0;
3104 if (expr1
.X_add_number
< -0x8000
3105 || expr1
.X_add_number
>= 0x8000)
3106 as_bad ("PIC code offset overflow (max 16 signed bits)");
3108 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3109 mips_isa
< 3 ? "lw" : "ld",
3110 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
3111 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
3112 p
= frag_var (rs_machine_dependent
, 4, 0,
3113 RELAX_ENCODE (0, 4, -8, 0, 0, 0),
3114 offset_expr
.X_add_symbol
, (long) 0,
3116 macro_build (p
, &icnt
, &offset_expr
,
3117 mips_isa
< 3 ? "addiu" : "daddiu",
3118 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
3120 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3121 mips_isa
< 3 ? "addu" : "daddu",
3122 "d,v,t", tempreg
, tempreg
, breg
);
3123 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
, treg
,
3124 (int) BFD_RELOC_LO16
, tempreg
);
3126 else if (mips_pic
== EMBEDDED_PIC
)
3128 /* If there is no base register, we want
3129 <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL)
3130 If there is a base register, we want
3131 addu $tempreg,$breg,$gp
3132 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GPREL)
3134 assert (offset_expr
.X_op
== O_symbol
);
3137 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
3138 treg
, (int) BFD_RELOC_MIPS_GPREL
, GP
);
3143 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3144 mips_isa
< 3 ? "addu" : "daddu",
3145 "d,v,t", tempreg
, breg
, GP
);
3146 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
3147 treg
, (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
3160 load_register (&icnt
, treg
, &imm_expr
);
3164 if (imm_expr
.X_op
== O_constant
)
3166 load_register (&icnt
, AT
, &imm_expr
);
3167 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3168 "mtc1", "t,G", AT
, treg
);
3173 assert (offset_expr
.X_op
== O_symbol
3174 && strcmp (segment_name (S_GET_SEGMENT
3175 (offset_expr
.X_add_symbol
)),
3177 && offset_expr
.X_add_number
== 0);
3178 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lwc1", "T,o(b)",
3179 treg
, (int) BFD_RELOC_MIPS_LITERAL
, GP
);
3184 /* We know that sym is in the .rdata section. First we get the
3185 upper 16 bits of the address. */
3186 if (mips_pic
== NO_PIC
)
3188 /* FIXME: This won't work for a 64 bit address. */
3189 macro_build_lui ((char *) NULL
, &icnt
, &offset_expr
, AT
);
3191 else if (mips_pic
== SVR4_PIC
)
3193 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3194 mips_isa
< 3 ? "lw" : "ld",
3195 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
3197 else if (mips_pic
== EMBEDDED_PIC
)
3199 /* For embedded PIC we pick up the entire address off $gp in
3200 a single instruction. */
3201 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3202 mips_isa
< 3 ? "addiu" : "daddiu",
3203 "t,r,j", AT
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
3204 offset_expr
.X_op
= O_constant
;
3205 offset_expr
.X_add_number
= 0;
3210 /* Now we load the register(s). */
3212 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "ld", "t,o(b)",
3213 treg
, (int) BFD_RELOC_LO16
, AT
);
3216 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lw", "t,o(b)",
3217 treg
, (int) BFD_RELOC_LO16
, AT
);
3220 /* FIXME: How in the world do we deal with the possible
3222 offset_expr
.X_add_number
+= 4;
3223 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lw", "t,o(b)",
3224 treg
+ 1, (int) BFD_RELOC_LO16
, AT
);
3228 /* To avoid confusion in tc_gen_reloc, we must ensure that this
3229 does not become a variant frag. */
3230 frag_wane (frag_now
);
3236 assert (offset_expr
.X_op
== O_symbol
3237 && offset_expr
.X_add_number
== 0);
3238 s
= segment_name (S_GET_SEGMENT (offset_expr
.X_add_symbol
));
3239 if (strcmp (s
, ".lit8") == 0)
3243 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "ldc1",
3244 "T,o(b)", treg
, (int) BFD_RELOC_MIPS_LITERAL
, GP
);
3248 r
= BFD_RELOC_MIPS_LITERAL
;
3253 assert (strcmp (s
, RDATA_SECTION_NAME
) == 0);
3254 if (mips_pic
== SVR4_PIC
)
3255 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3256 mips_isa
< 3 ? "lw" : "ld",
3257 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
3260 /* FIXME: This won't work for a 64 bit address. */
3261 macro_build_lui ((char *) NULL
, &icnt
, &offset_expr
, AT
);
3266 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "ldc1",
3267 "T,o(b)", treg
, (int) BFD_RELOC_LO16
, AT
);
3269 /* To avoid confusion in tc_gen_reloc, we must ensure
3270 that this does not become a variant frag. */
3271 frag_wane (frag_now
);
3282 /* Even on a big endian machine $fn comes before $fn+1. We have
3283 to adjust when loading from memory. */
3286 assert (mips_isa
< 2);
3287 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lwc1", "T,o(b)",
3288 byte_order
== LITTLE_ENDIAN
? treg
: treg
+ 1,
3290 /* FIXME: A possible overflow which I don't know how to deal
3292 offset_expr
.X_add_number
+= 4;
3293 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lwc1", "T,o(b)",
3294 byte_order
== LITTLE_ENDIAN
? treg
+ 1 : treg
,
3297 /* To avoid confusion in tc_gen_reloc, we must ensure that this
3298 does not become a variant frag. */
3299 frag_wane (frag_now
);
3308 * The MIPS assembler seems to check for X_add_number not
3309 * being double aligned and generating:
3312 * addiu at,at,%lo(foo+1)
3315 * But, the resulting address is the same after relocation so why
3316 * generate the extra instruction?
3363 if (offset_expr
.X_op
!= O_symbol
3364 && offset_expr
.X_op
!= O_constant
)
3366 as_bad ("expression too complex");
3367 offset_expr
.X_op
= O_constant
;
3370 /* Even on a big endian machine $fn comes before $fn+1. We have
3371 to adjust when loading from memory. We set coproc if we must
3372 load $fn+1 first. */
3373 if (byte_order
== LITTLE_ENDIAN
)
3376 if (mips_pic
== NO_PIC
3377 || offset_expr
.X_op
== O_constant
)
3379 /* If this is a reference to a GP relative symbol, we want
3380 <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL)
3381 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_MIPS_GPREL)
3382 If we have a base register, we use this
3384 <op> $treg,<sym>($at) (BFD_RELOC_MIPS_GPREL)
3385 <op> $treg+1,<sym>+4($at) (BFD_RELOC_MIPS_GPREL)
3386 If this is not a GP relative symbol, we want
3387 lui $at,<sym> (BFD_RELOC_HI16_S)
3388 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
3389 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
3390 If there is a base register, we add it to $at after the
3391 lui instruction. If there is a constant, we always use
3393 if (offset_expr
.X_add_number
!= 0)
3412 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3413 mips_isa
< 3 ? "addu" : "daddu",
3414 "d,v,t", AT
, breg
, GP
);
3420 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
3421 coproc
? treg
+ 1 : treg
,
3422 (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
3423 offset_expr
.X_add_number
+= 4;
3425 /* Set mips_optimize to 2 to avoid inserting an
3427 hold_mips_optimize
= mips_optimize
;
3429 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
3430 coproc
? treg
: treg
+ 1,
3431 (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
3432 mips_optimize
= hold_mips_optimize
;
3434 p
= frag_var (rs_machine_dependent
, 12 + off
, 0,
3435 RELAX_ENCODE (8 + off
, 12 + off
, 0, 4 + off
, 1,
3436 used_at
&& mips_noat
),
3437 offset_expr
.X_add_symbol
, (long) 0,
3440 /* We just generated two relocs. When tc_gen_reloc
3441 handles this case, it will skip the first reloc and
3442 handle the second. The second reloc already has an
3443 extra addend of 4, which we added above. We must
3444 subtract it out, and then subtract another 4 to make
3445 the first reloc come out right. The second reloc
3446 will come out right because we are going to add 4 to
3447 offset_expr when we build its instruction below. */
3448 offset_expr
.X_add_number
-= 8;
3449 offset_expr
.X_op
= O_constant
;
3451 macro_build_lui (p
, &icnt
, &offset_expr
, AT
);
3456 macro_build (p
, &icnt
, (expressionS
*) NULL
,
3457 mips_isa
< 3 ? "addu" : "daddu",
3458 "d,v,t", AT
, breg
, AT
);
3462 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
,
3463 coproc
? treg
+ 1 : treg
,
3464 (int) BFD_RELOC_LO16
, AT
);
3467 /* FIXME: How do we handle overflow here? */
3468 offset_expr
.X_add_number
+= 4;
3469 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
,
3470 coproc
? treg
: treg
+ 1,
3471 (int) BFD_RELOC_LO16
, AT
);
3473 else if (mips_pic
== SVR4_PIC
)
3477 /* If this is a reference to an external symbol, we want
3478 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3483 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3485 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
3486 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
3487 If there is a base register we add it to $at before the
3488 lwc1 instructions. If there is a constant we include it
3489 in the lwc1 instructions. */
3491 expr1
.X_add_number
= offset_expr
.X_add_number
;
3492 offset_expr
.X_add_number
= 0;
3493 if (expr1
.X_add_number
< -0x8000
3494 || expr1
.X_add_number
>= 0x8000 - 4)
3495 as_bad ("PIC code offset overflow (max 16 signed bits)");
3500 frag_grow (24 + off
);
3501 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3502 mips_isa
< 3 ? "lw" : "ld",
3503 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
3504 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
3506 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3507 mips_isa
< 3 ? "addu" : "daddu",
3508 "d,v,t", AT
, breg
, AT
);
3509 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
3510 coproc
? treg
+ 1 : treg
,
3511 (int) BFD_RELOC_LO16
, AT
);
3512 expr1
.X_add_number
+= 4;
3514 /* Set mips_optimize to 2 to avoid inserting an undesired
3516 hold_mips_optimize
= mips_optimize
;
3518 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
3519 coproc
? treg
: treg
+ 1,
3520 (int) BFD_RELOC_LO16
, AT
);
3521 mips_optimize
= hold_mips_optimize
;
3523 (void) frag_var (rs_machine_dependent
, 0, 0,
3524 RELAX_ENCODE (0, 0, -16 - off
, -8, 1, 0),
3525 offset_expr
.X_add_symbol
, (long) 0,
3528 else if (mips_pic
== EMBEDDED_PIC
)
3530 /* If there is no base register, we use
3531 <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL)
3532 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_MIPS_GPREL)
3533 If we have a base register, we use
3535 <op> $treg,<sym>($at) (BFD_RELOC_MIPS_GPREL)
3536 <op> $treg+1,<sym>+4($at) (BFD_RELOC_MIPS_GPREL)
3545 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3546 mips_isa
< 3 ? "addu" : "daddu",
3547 "d,v,t", AT
, breg
, GP
);
3552 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
3553 coproc
? treg
+ 1 : treg
,
3554 (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
3555 offset_expr
.X_add_number
+= 4;
3556 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
3557 coproc
? treg
: treg
+ 1,
3558 (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
3574 assert (mips_isa
< 3);
3575 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
3576 (int) BFD_RELOC_LO16
, breg
);
3577 offset_expr
.X_add_number
+= 4;
3578 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
+ 1,
3579 (int) BFD_RELOC_LO16
, breg
);
3581 #ifdef LOSING_COMPILER
3587 as_warn ("Macro used $at after \".set noat\"");
3592 struct mips_cl_insn
*ip
;
3594 register int treg
, sreg
, dreg
, breg
;
3609 bfd_reloc_code_real_type r
;
3612 treg
= (ip
->insn_opcode
>> 16) & 0x1f;
3613 dreg
= (ip
->insn_opcode
>> 11) & 0x1f;
3614 sreg
= breg
= (ip
->insn_opcode
>> 21) & 0x1f;
3615 mask
= ip
->insn_mo
->mask
;
3617 expr1
.X_op
= O_constant
;
3618 expr1
.X_op_symbol
= NULL
;
3619 expr1
.X_add_symbol
= NULL
;
3620 expr1
.X_add_number
= 1;
3624 #endif /* LOSING_COMPILER */
3629 macro_build ((char *) NULL
, &icnt
, NULL
,
3630 dbl
? "dmultu" : "multu",
3632 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
3638 /* The MIPS assembler some times generates shifts and adds. I'm
3639 not trying to be that fancy. GCC should do this for us
3641 load_register (&icnt
, AT
, &imm_expr
);
3642 macro_build ((char *) NULL
, &icnt
, NULL
,
3643 dbl
? "dmult" : "mult",
3645 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
3651 mips_emit_delays ();
3653 mips_any_noreorder
= 1;
3654 macro_build ((char *) NULL
, &icnt
, NULL
,
3655 dbl
? "dmult" : "mult",
3657 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
3658 macro_build ((char *) NULL
, &icnt
, NULL
,
3659 dbl
? "dsra32" : "sra",
3660 "d,w,<", dreg
, dreg
, 31);
3661 macro_build ((char *) NULL
, &icnt
, NULL
, "mfhi", "d", AT
);
3663 macro_build ((char *) NULL
, &icnt
, NULL
, "tne", "s,t", dreg
, AT
);
3666 expr1
.X_add_number
= 8;
3667 macro_build ((char *) NULL
, &icnt
, &expr1
, "beq", "s,t,p", dreg
, AT
);
3668 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
3669 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 6);
3672 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
3678 mips_emit_delays ();
3680 mips_any_noreorder
= 1;
3681 macro_build ((char *) NULL
, &icnt
, NULL
,
3682 dbl
? "dmultu" : "multu",
3684 macro_build ((char *) NULL
, &icnt
, NULL
, "mfhi", "d", AT
);
3685 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
3687 macro_build ((char *) NULL
, &icnt
, NULL
, "tne", "s,t", AT
, 0);
3690 expr1
.X_add_number
= 8;
3691 macro_build ((char *) NULL
, &icnt
, &expr1
, "beq", "s,t,p", AT
, 0);
3692 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
3693 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 6);
3699 macro_build ((char *) NULL
, &icnt
, NULL
, "subu", "d,v,t", AT
, 0, treg
);
3700 macro_build ((char *) NULL
, &icnt
, NULL
, "srlv", "d,t,s", AT
, sreg
, AT
);
3701 macro_build ((char *) NULL
, &icnt
, NULL
, "sllv", "d,t,s", dreg
, sreg
,
3703 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
3707 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", AT
, sreg
,
3708 imm_expr
.X_add_number
& 0x1f);
3709 macro_build ((char *) NULL
, &icnt
, NULL
, "srl", "d,w,<", dreg
, sreg
,
3710 (0 - imm_expr
.X_add_number
) & 0x1f);
3711 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
3715 macro_build ((char *) NULL
, &icnt
, NULL
, "subu", "d,v,t", AT
, 0, treg
);
3716 macro_build ((char *) NULL
, &icnt
, NULL
, "sllv", "d,t,s", AT
, sreg
, AT
);
3717 macro_build ((char *) NULL
, &icnt
, NULL
, "srlv", "d,t,s", dreg
, sreg
,
3719 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
3723 macro_build ((char *) NULL
, &icnt
, NULL
, "srl", "d,w,<", AT
, sreg
,
3724 imm_expr
.X_add_number
& 0x1f);
3725 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", dreg
, sreg
,
3726 (0 - imm_expr
.X_add_number
) & 0x1f);
3727 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
3731 assert (mips_isa
< 2);
3732 /* Even on a big endian machine $fn comes before $fn+1. We have
3733 to adjust when storing to memory. */
3734 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "swc1", "T,o(b)",
3735 byte_order
== LITTLE_ENDIAN
? treg
: treg
+ 1,
3736 (int) BFD_RELOC_LO16
, breg
);
3737 offset_expr
.X_add_number
+= 4;
3738 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "swc1", "T,o(b)",
3739 byte_order
== LITTLE_ENDIAN
? treg
+ 1 : treg
,
3740 (int) BFD_RELOC_LO16
, breg
);
3745 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
3746 treg
, (int) BFD_RELOC_LO16
);
3748 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
3749 sreg
, (int) BFD_RELOC_LO16
);
3752 macro_build ((char *) NULL
, &icnt
, NULL
, "xor", "d,v,t", dreg
,
3754 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
3755 dreg
, (int) BFD_RELOC_LO16
);
3760 if (imm_expr
.X_add_number
== 0)
3762 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
3763 sreg
, (int) BFD_RELOC_LO16
);
3768 as_warn ("Instruction %s: result is always false",
3770 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
, 0);
3773 if (imm_expr
.X_add_number
>= 0 && imm_expr
.X_add_number
< 0x10000)
3775 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "xori", "t,r,i", dreg
,
3776 sreg
, (int) BFD_RELOC_LO16
);
3779 else if (imm_expr
.X_add_number
> -0x8000 && imm_expr
.X_add_number
< 0)
3781 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
3782 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
3783 mips_isa
< 3 ? "addiu" : "daddiu",
3784 "t,r,j", dreg
, sreg
,
3785 (int) BFD_RELOC_LO16
);
3790 load_register (&icnt
, AT
, &imm_expr
);
3791 macro_build ((char *) NULL
, &icnt
, NULL
, "xor", "d,v,t", dreg
,
3795 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
, dreg
,
3796 (int) BFD_RELOC_LO16
);
3801 case M_SGE
: /* sreg >= treg <==> not (sreg < treg) */
3807 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, sreg
, treg
);
3808 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
3809 (int) BFD_RELOC_LO16
);
3812 case M_SGE_I
: /* sreg >= I <==> not (sreg < I) */
3814 if (imm_expr
.X_add_number
>= -0x8000 && imm_expr
.X_add_number
< 0x8000)
3816 macro_build ((char *) NULL
, &icnt
, &expr1
,
3817 mask
== M_SGE_I
? "slti" : "sltiu",
3818 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
3823 load_register (&icnt
, AT
, &imm_expr
);
3824 macro_build ((char *) NULL
, &icnt
, NULL
,
3825 mask
== M_SGE_I
? "slt" : "sltu",
3826 "d,v,t", dreg
, sreg
, AT
);
3829 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
3830 (int) BFD_RELOC_LO16
);
3835 case M_SGT
: /* sreg > treg <==> treg < sreg */
3841 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, treg
, sreg
);
3844 case M_SGT_I
: /* sreg > I <==> I < sreg */
3850 load_register (&icnt
, AT
, &imm_expr
);
3851 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, AT
, sreg
);
3854 case M_SLE
: /* sreg <= treg <==> treg >= sreg <==> not (treg < sreg) */
3860 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, treg
, sreg
);
3861 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
3862 (int) BFD_RELOC_LO16
);
3865 case M_SLE_I
: /* sreg <= I <==> I >= sreg <==> not (I < sreg) */
3871 load_register (&icnt
, AT
, &imm_expr
);
3872 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, AT
, sreg
);
3873 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
3874 (int) BFD_RELOC_LO16
);
3878 if (imm_expr
.X_add_number
>= -0x8000 && imm_expr
.X_add_number
< 0x8000)
3880 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "slti", "t,r,j",
3881 dreg
, sreg
, (int) BFD_RELOC_LO16
);
3884 load_register (&icnt
, AT
, &imm_expr
);
3885 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", dreg
, sreg
, AT
);
3889 if (imm_expr
.X_add_number
>= -0x8000 && imm_expr
.X_add_number
< 0x8000)
3891 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "sltiu", "t,r,j",
3892 dreg
, sreg
, (int) BFD_RELOC_LO16
);
3895 load_register (&icnt
, AT
, &imm_expr
);
3896 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, sreg
,
3902 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0,
3905 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0,
3909 macro_build ((char *) NULL
, &icnt
, NULL
, "xor", "d,v,t", dreg
,
3911 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0,
3917 if (imm_expr
.X_add_number
== 0)
3919 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0,
3925 as_warn ("Instruction %s: result is always true",
3927 macro_build ((char *) NULL
, &icnt
, &expr1
,
3928 mips_isa
< 3 ? "addiu" : "daddiu",
3929 "t,r,j", dreg
, 0, (int) BFD_RELOC_LO16
);
3932 if (imm_expr
.X_add_number
>= 0 && imm_expr
.X_add_number
< 0x10000)
3934 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "xori", "t,r,i",
3935 dreg
, sreg
, (int) BFD_RELOC_LO16
);
3938 else if (imm_expr
.X_add_number
> -0x8000 && imm_expr
.X_add_number
< 0)
3940 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
3941 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
3942 mips_isa
< 3 ? "addiu" : "daddiu",
3943 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
3948 load_register (&icnt
, AT
, &imm_expr
);
3949 macro_build ((char *) NULL
, &icnt
, NULL
, "xor", "d,v,t", dreg
,
3953 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0, dreg
);
3961 if (imm_expr
.X_add_number
> -0x8000 && imm_expr
.X_add_number
<= 0x8000)
3963 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
3964 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
3965 dbl
? "daddi" : "addi",
3966 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
3969 load_register (&icnt
, AT
, &imm_expr
);
3970 macro_build ((char *) NULL
, &icnt
, NULL
,
3971 dbl
? "dsub" : "sub",
3972 "d,v,t", dreg
, sreg
, AT
);
3978 if (imm_expr
.X_add_number
> -0x8000 && imm_expr
.X_add_number
<= 0x8000)
3980 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
3981 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
3982 dbl
? "daddiu" : "addiu",
3983 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
3986 load_register (&icnt
, AT
, &imm_expr
);
3987 macro_build ((char *) NULL
, &icnt
, NULL
,
3988 dbl
? "dsubu" : "subu",
3989 "d,v,t", dreg
, sreg
, AT
);
4010 load_register (&icnt
, AT
, &imm_expr
);
4011 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "s,t", sreg
, AT
);
4016 assert (mips_isa
< 2);
4017 sreg
= (ip
->insn_opcode
>> 11) & 0x1f; /* floating reg */
4018 dreg
= (ip
->insn_opcode
>> 06) & 0x1f; /* floating reg */
4021 * Is the double cfc1 instruction a bug in the mips assembler;
4022 * or is there a reason for it?
4024 mips_emit_delays ();
4026 mips_any_noreorder
= 1;
4027 macro_build ((char *) NULL
, &icnt
, NULL
, "cfc1", "t,G", treg
, 31);
4028 macro_build ((char *) NULL
, &icnt
, NULL
, "cfc1", "t,G", treg
, 31);
4029 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "");
4030 expr1
.X_add_number
= 3;
4031 macro_build ((char *) NULL
, &icnt
, &expr1
, "ori", "t,r,i", AT
, treg
,
4032 (int) BFD_RELOC_LO16
);
4033 expr1
.X_add_number
= 2;
4034 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", AT
, AT
,
4035 (int) BFD_RELOC_LO16
);
4036 macro_build ((char *) NULL
, &icnt
, NULL
, "ctc1", "t,G", AT
, 31);
4037 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "");
4038 macro_build ((char *) NULL
, &icnt
, NULL
,
4039 mask
== M_TRUNCWD
? "cvt.w.d" : "cvt.w.s", "D,S", dreg
, sreg
);
4040 macro_build ((char *) NULL
, &icnt
, NULL
, "ctc1", "t,G", treg
, 31);
4041 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "");
4051 if (offset_expr
.X_add_number
>= 0x7fff)
4052 as_bad ("operand overflow");
4053 /* avoid load delay */
4054 if (byte_order
== LITTLE_ENDIAN
)
4055 offset_expr
.X_add_number
+= 1;
4056 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
4057 (int) BFD_RELOC_LO16
, breg
);
4058 if (byte_order
== LITTLE_ENDIAN
)
4059 offset_expr
.X_add_number
-= 1;
4061 offset_expr
.X_add_number
+= 1;
4062 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lbu", "t,o(b)", AT
,
4063 (int) BFD_RELOC_LO16
, breg
);
4064 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", treg
, treg
, 8);
4065 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", treg
, treg
, AT
);
4078 if (offset_expr
.X_add_number
>= 0x8000 - off
)
4079 as_bad ("operand overflow");
4080 if (byte_order
== LITTLE_ENDIAN
)
4081 offset_expr
.X_add_number
+= off
;
4082 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
4083 (int) BFD_RELOC_LO16
, breg
);
4084 if (byte_order
== LITTLE_ENDIAN
)
4085 offset_expr
.X_add_number
-= off
;
4087 offset_expr
.X_add_number
+= off
;
4088 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s2
, "t,o(b)", treg
,
4089 (int) BFD_RELOC_LO16
, breg
);
4102 load_address (&icnt
, AT
, &offset_expr
);
4103 if (byte_order
== LITTLE_ENDIAN
)
4104 expr1
.X_add_number
= off
;
4106 expr1
.X_add_number
= 0;
4107 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, "t,o(b)", treg
,
4108 (int) BFD_RELOC_LO16
, AT
);
4109 if (byte_order
== LITTLE_ENDIAN
)
4110 expr1
.X_add_number
= 0;
4112 expr1
.X_add_number
= off
;
4113 macro_build ((char *) NULL
, &icnt
, &expr1
, s2
, "t,o(b)", treg
,
4114 (int) BFD_RELOC_LO16
, AT
);
4119 load_address (&icnt
, AT
, &offset_expr
);
4120 if (byte_order
== BIG_ENDIAN
)
4121 expr1
.X_add_number
= 0;
4122 macro_build ((char *) NULL
, &icnt
, &expr1
,
4123 mask
== M_ULH_A
? "lb" : "lbu", "t,o(b)", treg
,
4124 (int) BFD_RELOC_LO16
, AT
);
4125 if (byte_order
== BIG_ENDIAN
)
4126 expr1
.X_add_number
= 1;
4128 expr1
.X_add_number
= 0;
4129 macro_build ((char *) NULL
, &icnt
, &expr1
, "lbu", "t,o(b)", AT
,
4130 (int) BFD_RELOC_LO16
, AT
);
4131 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", treg
,
4133 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", treg
,
4138 if (offset_expr
.X_add_number
>= 0x7fff)
4139 as_bad ("operand overflow");
4140 if (byte_order
== BIG_ENDIAN
)
4141 offset_expr
.X_add_number
+= 1;
4142 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "sb", "t,o(b)", treg
,
4143 (int) BFD_RELOC_LO16
, breg
);
4144 macro_build ((char *) NULL
, &icnt
, NULL
, "srl", "d,w,<", AT
, treg
, 8);
4145 if (byte_order
== BIG_ENDIAN
)
4146 offset_expr
.X_add_number
-= 1;
4148 offset_expr
.X_add_number
+= 1;
4149 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "sb", "t,o(b)", AT
,
4150 (int) BFD_RELOC_LO16
, breg
);
4163 if (offset_expr
.X_add_number
>= 0x8000 - off
)
4164 as_bad ("operand overflow");
4165 if (byte_order
== LITTLE_ENDIAN
)
4166 offset_expr
.X_add_number
+= off
;
4167 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
4168 (int) BFD_RELOC_LO16
, breg
);
4169 if (byte_order
== LITTLE_ENDIAN
)
4170 offset_expr
.X_add_number
-= off
;
4172 offset_expr
.X_add_number
+= off
;
4173 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s2
, "t,o(b)", treg
,
4174 (int) BFD_RELOC_LO16
, breg
);
4187 load_address (&icnt
, AT
, &offset_expr
);
4188 if (byte_order
== LITTLE_ENDIAN
)
4189 expr1
.X_add_number
= off
;
4191 expr1
.X_add_number
= 0;
4192 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, "t,o(b)", treg
,
4193 (int) BFD_RELOC_LO16
, AT
);
4194 if (byte_order
== LITTLE_ENDIAN
)
4195 expr1
.X_add_number
= 0;
4197 expr1
.X_add_number
= off
;
4198 macro_build ((char *) NULL
, &icnt
, &expr1
, s2
, "t,o(b)", treg
,
4199 (int) BFD_RELOC_LO16
, AT
);
4203 load_address (&icnt
, AT
, &offset_expr
);
4204 if (byte_order
== LITTLE_ENDIAN
)
4205 expr1
.X_add_number
= 0;
4206 macro_build ((char *) NULL
, &icnt
, &expr1
, "sb", "t,o(b)", treg
,
4207 (int) BFD_RELOC_LO16
, AT
);
4208 macro_build ((char *) NULL
, &icnt
, NULL
, "srl", "d,w,<", treg
,
4210 if (byte_order
== LITTLE_ENDIAN
)
4211 expr1
.X_add_number
= 1;
4213 expr1
.X_add_number
= 0;
4214 macro_build ((char *) NULL
, &icnt
, &expr1
, "sb", "t,o(b)", treg
,
4215 (int) BFD_RELOC_LO16
, AT
);
4216 if (byte_order
== LITTLE_ENDIAN
)
4217 expr1
.X_add_number
= 0;
4219 expr1
.X_add_number
= 1;
4220 macro_build ((char *) NULL
, &icnt
, &expr1
, "lbu", "t,o(b)", AT
,
4221 (int) BFD_RELOC_LO16
, AT
);
4222 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", treg
,
4224 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", treg
,
4229 as_bad ("Macro %s not implemented yet", ip
->insn_mo
->name
);
4233 as_warn ("Macro used $at after \".set noat\"");
4238 This routine assembles an instruction into its binary format. As a side
4239 effect it sets one of the global variables imm_reloc or offset_reloc to the
4240 type of relocation to do if one of the operands is an address expression.
4245 struct mips_cl_insn
*ip
;
4250 struct mips_opcode
*insn
;
4253 unsigned int lastregno
= 0;
4258 for (s
= str
; islower (*s
) || (*s
>= '0' && *s
<= '3') || *s
== '.'; ++s
)
4270 as_fatal ("Unknown opcode: `%s'", str
);
4272 if ((insn
= (struct mips_opcode
*) hash_find (op_hash
, str
)) == NULL
)
4274 as_warn ("`%s' not in hash table.", str
);
4275 insn_error
= "ERROR: Unrecognized opcode";
4283 assert (strcmp (insn
->name
, str
) == 0);
4285 if (insn
->pinfo
== INSN_MACRO
)
4286 insn_isa
= insn
->match
;
4287 else if ((insn
->pinfo
& INSN_ISA
) == INSN_ISA2
)
4289 else if ((insn
->pinfo
& INSN_ISA
) == INSN_ISA3
)
4294 if (insn_isa
> mips_isa
4295 || ((insn
->pinfo
& INSN_ISA
) == INSN_4650
4298 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
]
4299 && strcmp (insn
->name
, insn
[1].name
) == 0)
4304 as_warn ("Instruction not supported on this processor");
4308 ip
->insn_opcode
= insn
->match
;
4309 for (args
= insn
->args
;; ++args
)
4315 case '\0': /* end of args */
4328 ip
->insn_opcode
|= lastregno
<< 21;
4333 ip
->insn_opcode
|= lastregno
<< 16;
4337 ip
->insn_opcode
|= lastregno
<< 11;
4343 /* handle optional base register.
4344 Either the base register is omitted or
4345 we must have a left paren. */
4346 /* this is dependent on the next operand specifier
4347 is a 'b' for base register */
4348 assert (args
[1] == 'b');
4352 case ')': /* these must match exactly */
4357 case '<': /* must be at least one digit */
4359 * According to the manual, if the shift amount is greater
4360 * than 31 or less than 0 the the shift amount should be
4361 * mod 32. In reality the mips assembler issues an error.
4362 * We issue a warning and mask out all but the low 5 bits.
4364 my_getExpression (&imm_expr
, s
);
4365 check_absolute_expr (ip
, &imm_expr
);
4366 if ((unsigned long) imm_expr
.X_add_number
> 31)
4368 as_warn ("Improper shift amount (%ld)",
4369 (long) imm_expr
.X_add_number
);
4370 imm_expr
.X_add_number
= imm_expr
.X_add_number
& 0x1f;
4372 ip
->insn_opcode
|= imm_expr
.X_add_number
<< 6;
4373 imm_expr
.X_op
= O_absent
;
4377 case '>': /* shift amount minus 32 */
4378 my_getExpression (&imm_expr
, s
);
4379 check_absolute_expr (ip
, &imm_expr
);
4380 if ((unsigned long) imm_expr
.X_add_number
< 32
4381 || (unsigned long) imm_expr
.X_add_number
> 63)
4383 ip
->insn_opcode
|= (imm_expr
.X_add_number
- 32) << 6;
4384 imm_expr
.X_op
= O_absent
;
4388 case 'k': /* cache code */
4389 my_getExpression (&imm_expr
, s
);
4390 check_absolute_expr (ip
, &imm_expr
);
4391 if ((unsigned long) imm_expr
.X_add_number
> 31)
4393 as_warn ("Invalid cahce opcode (%lu)",
4394 (unsigned long) imm_expr
.X_add_number
);
4395 imm_expr
.X_add_number
&= 0x1f;
4397 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_CACHE
;
4398 imm_expr
.X_op
= O_absent
;
4402 case 'c': /* break code */
4403 my_getExpression (&imm_expr
, s
);
4404 check_absolute_expr (ip
, &imm_expr
);
4405 if ((unsigned) imm_expr
.X_add_number
> 1023)
4406 as_warn ("Illegal break code (%ld)",
4407 (long) imm_expr
.X_add_number
);
4408 ip
->insn_opcode
|= imm_expr
.X_add_number
<< 16;
4409 imm_expr
.X_op
= O_absent
;
4413 case 'B': /* syscall code */
4414 my_getExpression (&imm_expr
, s
);
4415 check_absolute_expr (ip
, &imm_expr
);
4416 if ((unsigned) imm_expr
.X_add_number
> 0xfffff)
4417 as_warn ("Illegal syscall code (%ld)",
4418 (long) imm_expr
.X_add_number
);
4419 ip
->insn_opcode
|= imm_expr
.X_add_number
<< 6;
4420 imm_expr
.X_op
= O_absent
;
4424 case 'C': /* Coprocessor code */
4425 my_getExpression (&imm_expr
, s
);
4426 check_absolute_expr (ip
, &imm_expr
);
4427 if ((unsigned long) imm_expr
.X_add_number
>= (1<<25))
4429 as_warn ("Coproccesor code > 25 bits (%ld)",
4430 (long) imm_expr
.X_add_number
);
4431 imm_expr
.X_add_number
&= ((1<<25) - 1);
4433 ip
->insn_opcode
|= imm_expr
.X_add_number
;
4434 imm_expr
.X_op
= O_absent
;
4438 case 'b': /* base register */
4439 case 'd': /* destination register */
4440 case 's': /* source register */
4441 case 't': /* target register */
4442 case 'r': /* both target and source */
4443 case 'v': /* both dest and source */
4444 case 'w': /* both dest and target */
4445 case 'E': /* coprocessor target register */
4446 case 'G': /* coprocessor destination register */
4447 case 'x': /* ignore register name */
4448 case 'z': /* must be zero register */
4462 while (isdigit (*s
));
4464 as_bad ("Invalid register number (%d)", regno
);
4466 else if (*args
== 'E' || *args
== 'G')
4470 if (s
[1] == 'f' && s
[2] == 'p')
4475 else if (s
[1] == 's' && s
[2] == 'p')
4480 else if (s
[1] == 'g' && s
[2] == 'p')
4485 else if (s
[1] == 'a' && s
[2] == 't')
4490 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '0')
4495 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '1')
4503 if (regno
== AT
&& ! mips_noat
)
4504 as_warn ("Used $at without \".set noat\"");
4510 if (c
== 'r' || c
== 'v' || c
== 'w')
4517 /* 'z' only matches $0. */
4518 if (c
== 'z' && regno
!= 0)
4526 ip
->insn_opcode
|= regno
<< 21;
4530 ip
->insn_opcode
|= regno
<< 11;
4535 ip
->insn_opcode
|= regno
<< 16;
4538 /* This case exists because on the r3000 trunc
4539 expands into a macro which requires a gp
4540 register. On the r6000 or r4000 it is
4541 assembled into a single instruction which
4542 ignores the register. Thus the insn version
4543 is MIPS_ISA2 and uses 'x', and the macro
4544 version is MIPS_ISA1 and uses 't'. */
4547 /* This case is for the div instruction, which
4548 acts differently if the destination argument
4549 is $0. This only matches $0, and is checked
4550 outside the switch. */
4561 ip
->insn_opcode
|= lastregno
<< 21;
4564 ip
->insn_opcode
|= lastregno
<< 16;
4569 case 'D': /* floating point destination register */
4570 case 'S': /* floating point source register */
4571 case 'T': /* floating point target register */
4575 if (s
[0] == '$' && s
[1] == 'f' && isdigit (s
[2]))
4585 while (isdigit (*s
));
4588 as_bad ("Invalid float register number (%d)", regno
);
4590 if ((regno
& 1) != 0
4592 && ! (strcmp (str
, "mtc1") == 0 ||
4593 strcmp (str
, "mfc1") == 0 ||
4594 strcmp (str
, "lwc1") == 0 ||
4595 strcmp (str
, "swc1") == 0))
4596 as_warn ("Float register should be even, was %d",
4604 if (c
== 'V' || c
== 'W')
4614 ip
->insn_opcode
|= regno
<< 6;
4618 ip
->insn_opcode
|= regno
<< 11;
4622 ip
->insn_opcode
|= regno
<< 16;
4630 ip
->insn_opcode
|= lastregno
<< 11;
4633 ip
->insn_opcode
|= lastregno
<< 16;
4639 my_getExpression (&imm_expr
, s
);
4640 if (imm_expr
.X_op
!= O_big
)
4641 check_absolute_expr (ip
, &imm_expr
);
4646 my_getExpression (&offset_expr
, s
);
4647 imm_reloc
= BFD_RELOC_32
;
4659 unsigned char temp
[8];
4661 unsigned int length
;
4666 /* These only appear as the last operand in an
4667 instruction, and every instruction that accepts
4668 them in any variant accepts them in all variants.
4669 This means we don't have to worry about backing out
4670 any changes if the instruction does not match.
4672 The difference between them is the size of the
4673 floating point constant and where it goes. For 'F'
4674 and 'L' the constant is 64 bits; for 'f' and 'l' it
4675 is 32 bits. Where the constant is placed is based
4676 on how the MIPS assembler does things:
4679 f -- immediate value
4682 The .lit4 and .lit8 sections are only used if
4683 permitted by the -G argument.
4685 When generating embedded PIC code, we use the
4686 .lit8 section but not the .lit4 section (we can do
4687 .lit4 inline easily; we need to put .lit8
4688 somewhere in the data segment, and using .lit8
4689 permits the linker to eventually combine identical
4692 f64
= *args
== 'F' || *args
== 'L';
4694 save_in
= input_line_pointer
;
4695 input_line_pointer
= s
;
4696 err
= md_atof (f64
? 'd' : 'f', (char *) temp
, &len
);
4698 s
= input_line_pointer
;
4699 input_line_pointer
= save_in
;
4700 if (err
!= NULL
&& *err
!= '\0')
4702 as_bad ("Bad floating point constant: %s", err
);
4703 memset (temp
, '\0', sizeof temp
);
4704 length
= f64
? 8 : 4;
4707 assert (length
== (f64
? 8 : 4));
4712 && (mips_pic
== EMBEDDED_PIC
4713 || g_switch_value
< 4)
4717 imm_expr
.X_op
= O_constant
;
4718 if (byte_order
== LITTLE_ENDIAN
)
4719 imm_expr
.X_add_number
=
4720 (((((((int) temp
[3] << 8)
4725 imm_expr
.X_add_number
=
4726 (((((((int) temp
[0] << 8)
4733 const char *newname
;
4736 /* Switch to the right section. */
4738 subseg
= now_subseg
;
4741 default: /* unused default case avoids warnings. */
4743 newname
= RDATA_SECTION_NAME
;
4745 if (g_switch_value
>= 8)
4750 newname
= RDATA_SECTION_NAME
;
4754 assert (g_switch_value
>= 4);
4759 new_seg
= subseg_new (newname
, (subsegT
) 0);
4760 frag_align (*args
== 'l' ? 2 : 3, 0);
4762 record_alignment (new_seg
, 4);
4764 record_alignment (new_seg
, *args
== 'l' ? 2 : 3);
4767 as_bad ("Can't use floating point insn in this section");
4769 /* Set the argument to the current address in the
4771 offset_expr
.X_op
= O_symbol
;
4772 offset_expr
.X_add_symbol
=
4773 symbol_new ("L0\001", now_seg
,
4774 (valueT
) frag_now_fix (), frag_now
);
4775 offset_expr
.X_add_number
= 0;
4777 /* Put the floating point number into the section. */
4778 p
= frag_more ((int) length
);
4779 memcpy (p
, temp
, length
);
4781 /* Switch back to the original section. */
4782 subseg_set (seg
, subseg
);
4787 case 'i': /* 16 bit unsigned immediate */
4788 case 'j': /* 16 bit signed immediate */
4789 imm_reloc
= BFD_RELOC_LO16
;
4790 c
= my_getSmallExpression (&imm_expr
, s
);
4795 if (imm_expr
.X_op
== O_constant
)
4796 imm_expr
.X_add_number
=
4797 (imm_expr
.X_add_number
>> 16) & 0xffff;
4799 imm_reloc
= BFD_RELOC_HI16_S
;
4801 imm_reloc
= BFD_RELOC_HI16
;
4804 else if (imm_expr
.X_op
!= O_big
)
4805 check_absolute_expr (ip
, &imm_expr
);
4808 if (imm_expr
.X_op
== O_big
4809 || imm_expr
.X_add_number
< 0
4810 || imm_expr
.X_add_number
>= 0x10000)
4812 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
4813 !strcmp (insn
->name
, insn
[1].name
))
4815 as_bad ("16 bit expression not in range 0..65535");
4823 /* The upper bound should be 0x8000, but
4824 unfortunately the MIPS assembler accepts numbers
4825 from 0x8000 to 0xffff and sign extends them, and
4826 we want to be compatible. We only permit this
4827 extended range for an instruction which does not
4828 provide any further alternates, since those
4829 alternates may handle other cases. People should
4830 use the numbers they mean, rather than relying on
4831 a mysterious sign extension. */
4832 more
= (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
4833 strcmp (insn
->name
, insn
[1].name
) == 0);
4838 if (imm_expr
.X_op
== O_big
4839 || imm_expr
.X_add_number
< -0x8000
4840 || imm_expr
.X_add_number
>= max
)
4844 as_bad ("16 bit expression not in range -32768..32767");
4850 case 'o': /* 16 bit offset */
4851 c
= my_getSmallExpression (&offset_expr
, s
);
4853 /* If this value won't fit into a 16 bit offset, then go
4854 find a macro that will generate the 32 bit offset
4855 code pattern. As a special hack, we accept the
4856 difference of two local symbols as a constant. This
4857 is required to suppose embedded PIC switches, which
4858 use an instruction which looks like
4859 lw $4,$L12-$LS12($4)
4860 The problem with handling this in a more general
4861 fashion is that the macro function doesn't expect to
4862 see anything which can be handled in a single
4863 constant instruction. */
4865 && (offset_expr
.X_op
!= O_constant
4866 || offset_expr
.X_add_number
>= 0x8000
4867 || offset_expr
.X_add_number
< -0x8000)
4868 && (mips_pic
!= EMBEDDED_PIC
4869 || offset_expr
.X_op
!= O_subtract
4870 || now_seg
!= text_section
4871 || (S_GET_SEGMENT (offset_expr
.X_op_symbol
)
4875 offset_reloc
= BFD_RELOC_LO16
;
4876 if (c
== 'h' || c
== 'H')
4878 assert (offset_expr
.X_op
== O_constant
);
4879 offset_expr
.X_add_number
=
4880 (offset_expr
.X_add_number
>> 16) & 0xffff;
4885 case 'p': /* pc relative offset */
4886 offset_reloc
= BFD_RELOC_16_PCREL_S2
;
4887 my_getExpression (&offset_expr
, s
);
4891 case 'u': /* upper 16 bits */
4892 c
= my_getSmallExpression (&imm_expr
, s
);
4893 if (imm_expr
.X_op
== O_constant
4894 && (imm_expr
.X_add_number
< 0
4895 || imm_expr
.X_add_number
>= 0x10000))
4896 as_bad ("lui expression not in range 0..65535");
4897 imm_reloc
= BFD_RELOC_LO16
;
4902 if (imm_expr
.X_op
== O_constant
)
4903 imm_expr
.X_add_number
=
4904 (imm_expr
.X_add_number
>> 16) & 0xffff;
4906 imm_reloc
= BFD_RELOC_HI16_S
;
4908 imm_reloc
= BFD_RELOC_HI16
;
4914 case 'a': /* 26 bit address */
4915 my_getExpression (&offset_expr
, s
);
4917 offset_reloc
= BFD_RELOC_MIPS_JMP
;
4921 fprintf (stderr
, "bad char = '%c'\n", *args
);
4926 /* Args don't match. */
4927 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
4928 !strcmp (insn
->name
, insn
[1].name
))
4934 insn_error
= "ERROR: Illegal operands";
4943 my_getSmallExpression (ep
, str
)
4954 ((str
[1] == 'h' && str
[2] == 'i')
4955 || (str
[1] == 'H' && str
[2] == 'I')
4956 || (str
[1] == 'l' && str
[2] == 'o'))
4968 * A small expression may be followed by a base register.
4969 * Scan to the end of this operand, and then back over a possible
4970 * base register. Then scan the small expression up to that
4971 * point. (Based on code in sparc.c...)
4973 for (sp
= str
; *sp
&& *sp
!= ','; sp
++)
4975 if (sp
- 4 >= str
&& sp
[-1] == RP
)
4977 if (isdigit (sp
[-2]))
4979 for (sp
-= 3; sp
>= str
&& isdigit (*sp
); sp
--)
4981 if (*sp
== '$' && sp
> str
&& sp
[-1] == LP
)
4987 else if (sp
- 5 >= str
4990 && ((sp
[-3] == 'f' && sp
[-2] == 'p')
4991 || (sp
[-3] == 's' && sp
[-2] == 'p')
4992 || (sp
[-3] == 'g' && sp
[-2] == 'p')
4993 || (sp
[-3] == 'a' && sp
[-2] == 't')))
4999 /* no expression means zero offset */
5002 /* %xx(reg) is an error */
5003 ep
->X_op
= O_absent
;
5008 ep
->X_op
= O_constant
;
5011 ep
->X_add_symbol
= NULL
;
5012 ep
->X_op_symbol
= NULL
;
5013 ep
->X_add_number
= 0;
5018 my_getExpression (ep
, str
);
5025 my_getExpression (ep
, str
);
5026 return c
; /* => %hi or %lo encountered */
5030 my_getExpression (ep
, str
)
5036 save_in
= input_line_pointer
;
5037 input_line_pointer
= str
;
5039 expr_end
= input_line_pointer
;
5040 input_line_pointer
= save_in
;
5043 /* Turn a string in input_line_pointer into a floating point constant
5044 of type type, and store the appropriate bytes in *litP. The number
5045 of LITTLENUMS emitted is stored in *sizeP . An error message is
5046 returned, or NULL on OK. */
5049 md_atof (type
, litP
, sizeP
)
5055 LITTLENUM_TYPE words
[4];
5071 return "bad call to md_atof";
5074 t
= atof_ieee (input_line_pointer
, type
, words
);
5076 input_line_pointer
= t
;
5080 if (byte_order
== LITTLE_ENDIAN
)
5082 for (i
= prec
- 1; i
>= 0; i
--)
5084 md_number_to_chars (litP
, (valueT
) words
[i
], 2);
5090 for (i
= 0; i
< prec
; i
++)
5092 md_number_to_chars (litP
, (valueT
) words
[i
], 2);
5101 md_number_to_chars (buf
, val
, n
)
5109 number_to_chars_littleendian (buf
, val
, n
);
5113 number_to_chars_bigendian (buf
, val
, n
);
5122 CONST
char *md_shortopts
= "O::g::G:";
5124 CONST
char *md_shortopts
= "O::g::";
5126 struct option md_longopts
[] = {
5127 #define OPTION_MIPS1 (OPTION_MD_BASE + 1)
5128 {"mips0", no_argument
, NULL
, OPTION_MIPS1
},
5129 {"mips1", no_argument
, NULL
, OPTION_MIPS1
},
5130 #define OPTION_MIPS2 (OPTION_MD_BASE + 2)
5131 {"mips2", no_argument
, NULL
, OPTION_MIPS2
},
5132 #define OPTION_MIPS3 (OPTION_MD_BASE + 3)
5133 {"mips3", no_argument
, NULL
, OPTION_MIPS3
},
5134 #define OPTION_MCPU (OPTION_MD_BASE + 4)
5135 {"mcpu", required_argument
, NULL
, OPTION_MCPU
},
5136 #define OPTION_MEMBEDDED_PIC (OPTION_MD_BASE + 5)
5137 {"membedded-pic", no_argument
, NULL
, OPTION_MEMBEDDED_PIC
},
5138 #define OPTION_TRAP (OPTION_MD_BASE + 8)
5139 {"trap", no_argument
, NULL
, OPTION_TRAP
},
5140 {"no-break", no_argument
, NULL
, OPTION_TRAP
},
5141 #define OPTION_BREAK (OPTION_MD_BASE + 9)
5142 {"break", no_argument
, NULL
, OPTION_BREAK
},
5143 {"no-trap", no_argument
, NULL
, OPTION_BREAK
},
5144 #define OPTION_EB (OPTION_MD_BASE + 10)
5145 {"EB", no_argument
, NULL
, OPTION_EB
},
5146 #define OPTION_EL (OPTION_MD_BASE + 11)
5147 {"EL", no_argument
, NULL
, OPTION_EL
},
5148 #define OPTION_M4650 (OPTION_MD_BASE + 12)
5149 {"m4650", no_argument
, NULL
, OPTION_M4650
},
5150 #define OPTION_NO_M4650 (OPTION_MD_BASE + 13)
5151 {"no-m4650", no_argument
, NULL
, OPTION_NO_M4650
},
5154 #define OPTION_CALL_SHARED (OPTION_MD_BASE + 6)
5155 {"KPIC", no_argument
, NULL
, OPTION_CALL_SHARED
},
5156 {"call_shared", no_argument
, NULL
, OPTION_CALL_SHARED
},
5157 #define OPTION_NON_SHARED (OPTION_MD_BASE + 7)
5158 {"non_shared", no_argument
, NULL
, OPTION_NON_SHARED
},
5161 {NULL
, no_argument
, NULL
, 0}
5163 size_t md_longopts_size
= sizeof(md_longopts
);
5166 md_parse_option (c
, arg
)
5181 byte_order
= BIG_ENDIAN
;
5183 mips_target_format
= "a.out-mips-big";
5186 mips_target_format
= "ecoff-bigmips";
5189 mips_target_format
= "elf32-bigmips";
5194 byte_order
= LITTLE_ENDIAN
;
5196 mips_target_format
= "a.out-mips-little";
5199 mips_target_format
= "ecoff-littlemips";
5202 mips_target_format
= "elf32-littlemips";
5207 if (arg
&& arg
[1] == '0')
5214 if (arg
== NULL
|| arg
[1] == '2')
5240 /* Identify the processor type */
5242 if (strcmp (p
, "default") == 0
5243 || strcmp (p
, "DEFAULT") == 0)
5247 if (*p
== 'r' || *p
== 'R')
5254 if (strcmp (p
, "2000") == 0
5255 || strcmp (p
, "2k") == 0
5256 || strcmp (p
, "2K") == 0)
5261 if (strcmp (p
, "3000") == 0
5262 || strcmp (p
, "3k") == 0
5263 || strcmp (p
, "3K") == 0)
5268 if (strcmp (p
, "4000") == 0
5269 || strcmp (p
, "4k") == 0
5270 || strcmp (p
, "4K") == 0)
5272 else if (strcmp (p
, "4400") == 0)
5274 else if (strcmp (p
, "4600") == 0)
5276 else if (strcmp (p
, "4650") == 0)
5285 if (strcmp (p
, "6000") == 0
5286 || strcmp (p
, "6k") == 0
5287 || strcmp (p
, "6K") == 0)
5292 if (strcmp (p
, "orion") == 0)
5299 as_bad ("invalid architecture -mcpu=%s", arg
);
5310 case OPTION_NO_M4650
:
5314 case OPTION_MEMBEDDED_PIC
:
5315 mips_pic
= EMBEDDED_PIC
;
5319 as_bad ("-G may not be used with embedded PIC code");
5322 g_switch_value
= 0x7fffffff;
5327 /* When generating ELF code, we permit -KPIC and -call_shared to
5328 select SVR4_PIC, and -non_shared to select no PIC. This is
5329 intended to be compatible with Irix 5. */
5330 case OPTION_CALL_SHARED
:
5331 mips_pic
= SVR4_PIC
;
5332 if (g_switch_seen
&& g_switch_value
!= 0)
5334 as_bad ("-G may not be used with SVR4 PIC code");
5340 case OPTION_NON_SHARED
:
5343 #endif /* OBJ_ELF */
5347 if (mips_pic
== SVR4_PIC
|| mips_pic
== EMBEDDED_PIC
)
5349 as_bad ("-G may not be used with SVR4 or embedded PIC code");
5353 g_switch_value
= atoi (arg
);
5366 md_show_usage (stream
)
5371 -membedded-pic generate embedded position independent code\n\
5372 -EB generate big endian output\n\
5373 -EL generate little endian output\n\
5374 -g, -g2 do not remove uneeded NOPs or swap branches\n\
5375 -G NUM allow referencing objects up to NUM bytes\n\
5376 implicitly with the gp register [default 8]\n");
5378 -mips1, -mcpu=r{2,3}000 generate code for r2000 and r3000\n\
5379 -mips2, -mcpu=r6000 generate code for r6000\n\
5380 -mips3, -mcpu=r4000 generate code for r4000\n\
5381 -O0 remove unneeded NOPs, do not swap branches\n\
5382 -O remove unneeded NOPs and swap branches\n\
5383 --trap, --no-break trap exception on div by 0 and mult overflow\n\
5384 --break, --no-trap break exception on div by 0 and mult overflow\n");
5387 -KPIC, -call_shared generate SVR4 position independent code\n\
5388 -non_shared do not generate position independent code\n");
5393 md_pcrel_from (fixP
)
5397 if (fixP
->fx_addsy
!= (symbolS
*) NULL
5398 && ! S_IS_DEFINED (fixP
->fx_addsy
))
5400 /* This makes a branch to an undefined symbol be a branch to the
5401 current location. */
5406 /* return the address of the delay slot */
5407 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
5410 /* This is called by emit_expr via TC_CONS_FIX_NEW when creating a
5411 reloc for a cons. We could use the definition there, except that
5412 we want to handle 64 bit relocs specially. */
5415 cons_fix_new_mips (frag
, where
, nbytes
, exp
)
5418 unsigned int nbytes
;
5421 /* If we are assembling in 32 bit mode, turn an 8 byte reloc into a
5423 FIXME: There is no way to select anything but 32 bit mode right
5427 if (byte_order
== BIG_ENDIAN
)
5432 if (nbytes
!= 2 && nbytes
!= 4)
5433 as_bad ("Unsupported reloc size %d", nbytes
);
5435 fix_new_exp (frag_now
, where
, (int) nbytes
, exp
, 0,
5436 nbytes
== 2 ? BFD_RELOC_16
: BFD_RELOC_32
);
5439 /* When generating embedded PIC code we need to use a special
5440 relocation to represent the difference of two symbols in the .text
5441 section (switch tables use a difference of this sort). See
5442 include/coff/mips.h for details. This macro checks whether this
5443 fixup requires the special reloc. */
5444 #define SWITCH_TABLE(fixp) \
5445 ((fixp)->fx_r_type == BFD_RELOC_32 \
5446 && (fixp)->fx_addsy != NULL \
5447 && (fixp)->fx_subsy != NULL \
5448 && S_GET_SEGMENT ((fixp)->fx_addsy) == text_section \
5449 && S_GET_SEGMENT ((fixp)->fx_subsy) == text_section)
5451 /* When generating embedded PIC code we must keep all PC relative
5452 relocations, in case the linker has to relax a call. We also need
5453 to keep relocations for switch table entries. */
5457 mips_force_relocation (fixp
)
5460 return (mips_pic
== EMBEDDED_PIC
5462 || SWITCH_TABLE (fixp
)
5463 || fixp
->fx_r_type
== BFD_RELOC_PCREL_HI16_S
5464 || fixp
->fx_r_type
== BFD_RELOC_PCREL_LO16
));
5467 /* Apply a fixup to the object file. */
5470 md_apply_fix (fixP
, valueP
)
5477 assert (fixP
->fx_size
== 4 || fixP
->fx_r_type
== BFD_RELOC_16
);
5480 fixP
->fx_addnumber
= value
; /* Remember value for tc_gen_reloc */
5482 if (fixP
->fx_addsy
== NULL
&& ! fixP
->fx_pcrel
)
5485 switch (fixP
->fx_r_type
)
5487 case BFD_RELOC_MIPS_JMP
:
5488 case BFD_RELOC_HI16
:
5489 case BFD_RELOC_HI16_S
:
5490 case BFD_RELOC_MIPS_GPREL
:
5491 case BFD_RELOC_MIPS_LITERAL
:
5492 case BFD_RELOC_MIPS_CALL16
:
5493 case BFD_RELOC_MIPS_GOT16
:
5494 case BFD_RELOC_MIPS_GPREL32
:
5496 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
5497 "Invalid PC relative reloc");
5498 /* Nothing needed to do. The value comes from the reloc entry */
5501 case BFD_RELOC_PCREL_HI16_S
:
5502 /* The addend for this is tricky if it is internal, so we just
5503 do everything here rather than in bfd_perform_relocation. */
5504 if ((fixP
->fx_addsy
->bsym
->flags
& BSF_SECTION_SYM
) == 0)
5506 /* For an external symbol adjust by the address to make it
5507 pcrel_offset. We use the address of the RELLO reloc
5508 which follows this one. */
5509 value
+= (fixP
->fx_next
->fx_frag
->fr_address
5510 + fixP
->fx_next
->fx_where
);
5515 buf
= (unsigned char *) fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
5516 if (byte_order
== BIG_ENDIAN
)
5518 md_number_to_chars (buf
, value
, 2);
5521 case BFD_RELOC_PCREL_LO16
:
5522 /* The addend for this is tricky if it is internal, so we just
5523 do everything here rather than in bfd_perform_relocation. */
5524 if ((fixP
->fx_addsy
->bsym
->flags
& BSF_SECTION_SYM
) == 0)
5525 value
+= fixP
->fx_frag
->fr_address
+ fixP
->fx_where
;
5526 buf
= (unsigned char *) fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
5527 if (byte_order
== BIG_ENDIAN
)
5529 md_number_to_chars (buf
, value
, 2);
5533 /* If we are deleting this reloc entry, we must fill in the
5534 value now. This can happen if we have a .word which is not
5535 resolved when it appears but is later defined. We also need
5536 to fill in the value if this is an embedded PIC switch table
5539 || (mips_pic
== EMBEDDED_PIC
&& SWITCH_TABLE (fixP
)))
5540 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
,
5545 /* If we are deleting this reloc entry, we must fill in the
5547 assert (fixP
->fx_size
== 2);
5549 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
,
5553 case BFD_RELOC_LO16
:
5554 /* When handling an embedded PIC switch statement, we can wind
5555 up deleting a LO16 reloc. See the 'o' case in mips_ip. */
5558 if (value
< -0x8000 || value
> 0x7fff)
5559 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
5560 "relocation overflow");
5561 buf
= (unsigned char *) fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
5562 if (byte_order
== BIG_ENDIAN
)
5564 md_number_to_chars (buf
, value
, 2);
5568 case BFD_RELOC_16_PCREL_S2
:
5570 * We need to save the bits in the instruction since fixup_segment()
5571 * might be deleting the relocation entry (i.e., a branch within
5572 * the current segment).
5575 as_warn_where (fixP
->fx_file
, fixP
->fx_line
,
5576 "Branch to odd address (%lx)", value
);
5579 /* update old instruction data */
5580 buf
= (unsigned char *) (fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
);
5584 insn
= (buf
[3] << 24) | (buf
[2] << 16) | (buf
[1] << 8) | buf
[0];
5588 insn
= (buf
[0] << 24) | (buf
[1] << 16) | (buf
[2] << 8) | buf
[3];
5596 if (value
>= -0x8000 && value
< 0x8000)
5597 insn
|= value
& 0xffff;
5600 /* The branch offset is too large. If this is an
5601 unconditional branch, and we are not generating PIC code,
5602 we can convert it to an absolute jump instruction. */
5603 if (mips_pic
== NO_PIC
5605 && fixP
->fx_frag
->fr_address
>= text_section
->vma
5606 && (fixP
->fx_frag
->fr_address
5607 < text_section
->vma
+ text_section
->_raw_size
)
5608 && ((insn
& 0xffff0000) == 0x10000000 /* beq $0,$0 */
5609 || (insn
& 0xffff0000) == 0x04010000 /* bgez $0 */
5610 || (insn
& 0xffff0000) == 0x04110000)) /* bgezal $0 */
5612 if ((insn
& 0xffff0000) == 0x04110000) /* bgezal $0 */
5613 insn
= 0x0c000000; /* jal */
5615 insn
= 0x08000000; /* j */
5616 fixP
->fx_r_type
= BFD_RELOC_MIPS_JMP
;
5618 fixP
->fx_addsy
= section_symbol (text_section
);
5619 fixP
->fx_addnumber
= (value
<< 2) + md_pcrel_from (fixP
);
5623 /* FIXME. It would be possible in principle to handle
5624 conditional branches which overflow. They could be
5625 transformed into a branch around a jump. This would
5626 require setting up variant frags for each different
5627 branch type. The native MIPS assembler attempts to
5628 handle these cases, but it appears to do it
5630 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
5631 "Relocation overflow");
5635 md_number_to_chars ((char *) buf
, (valueT
) insn
, 4);
5650 const struct mips_opcode
*p
;
5651 int treg
, sreg
, dreg
, shamt
;
5656 for (i
= 0; i
< NUMOPCODES
; ++i
)
5658 p
= &mips_opcodes
[i
];
5659 if (((oc
& p
->mask
) == p
->match
) && (p
->pinfo
!= INSN_MACRO
))
5661 printf ("%08lx %s\t", oc
, p
->name
);
5662 treg
= (oc
>> 16) & 0x1f;
5663 sreg
= (oc
>> 21) & 0x1f;
5664 dreg
= (oc
>> 11) & 0x1f;
5665 shamt
= (oc
>> 6) & 0x1f;
5667 for (args
= p
->args
;; ++args
)
5678 printf ("%c", *args
);
5682 assert (treg
== sreg
);
5683 printf ("$%d,$%d", treg
, sreg
);
5688 printf ("$%d", dreg
);
5693 printf ("$%d", treg
);
5697 printf ("0x%x", treg
);
5702 printf ("$%d", sreg
);
5706 printf ("0x%08lx", oc
& 0x1ffffff);
5718 printf ("$%d", shamt
);
5729 printf ("%08lx UNDEFINED\n", oc
);
5740 name
= input_line_pointer
;
5741 c
= get_symbol_end ();
5742 p
= (symbolS
*) symbol_find_or_make (name
);
5743 *input_line_pointer
= c
;
5747 /* Align the current frag to a given power of two. The MIPS assembler
5748 also automatically adjusts any preceding label. */
5751 mips_align (to
, fill
, label
)
5756 mips_emit_delays ();
5757 frag_align (to
, fill
);
5758 record_alignment (now_seg
, to
);
5761 assert (S_GET_SEGMENT (label
) == now_seg
);
5762 label
->sy_frag
= frag_now
;
5763 S_SET_VALUE (label
, (valueT
) frag_now_fix ());
5767 /* Align to a given power of two. .align 0 turns off the automatic
5768 alignment used by the data creating pseudo-ops. */
5775 register long temp_fill
;
5776 long max_alignment
= 15;
5780 o Note that the assembler pulls down any immediately preceeding label
5781 to the aligned address.
5782 o It's not documented but auto alignment is reinstated by
5783 a .align pseudo instruction.
5784 o Note also that after auto alignment is turned off the mips assembler
5785 issues an error on attempt to assemble an improperly aligned data item.
5790 temp
= get_absolute_expression ();
5791 if (temp
> max_alignment
)
5792 as_bad ("Alignment too large: %d. assumed.", temp
= max_alignment
);
5795 as_warn ("Alignment negative: 0 assumed.");
5798 if (*input_line_pointer
== ',')
5800 input_line_pointer
++;
5801 temp_fill
= get_absolute_expression ();
5808 mips_align (temp
, (int) temp_fill
, insn_label
);
5815 demand_empty_rest_of_line ();
5818 /* Handle .ascii and .asciiz. This just calls stringer and forgets
5819 that there was a previous instruction. */
5822 s_stringer (append_zero
)
5825 mips_emit_delays ();
5827 stringer (append_zero
);
5838 /* When generating embedded PIC code, we only use the .text, .lit8,
5839 .sdata and .sbss sections. We change the .data and .rdata
5840 pseudo-ops to use .sdata. */
5841 if (mips_pic
== EMBEDDED_PIC
5842 && (sec
== 'd' || sec
== 'r'))
5845 mips_emit_delays ();
5855 subseg_set (bss_section
, (subsegT
) get_absolute_expression ());
5856 demand_empty_rest_of_line ();
5861 seg
= subseg_new (RDATA_SECTION_NAME
,
5862 (subsegT
) get_absolute_expression ());
5864 bfd_set_section_flags (stdoutput
, seg
,
5870 bfd_set_section_alignment (stdoutput
, seg
, 4);
5872 demand_empty_rest_of_line ();
5873 #else /* ! defined (GPOPT) */
5874 as_bad ("No read only data section in this object file format");
5875 demand_empty_rest_of_line ();
5877 #endif /* ! defined (GPOPT) */
5882 seg
= subseg_new (".sdata", (subsegT
) get_absolute_expression ());
5884 bfd_set_section_flags (stdoutput
, seg
,
5885 SEC_ALLOC
| SEC_LOAD
| SEC_RELOC
| SEC_DATA
);
5886 bfd_set_section_alignment (stdoutput
, seg
, 4);
5888 demand_empty_rest_of_line ();
5890 #else /* ! defined (GPOPT) */
5891 as_bad ("Global pointers not supported; recompile -G 0");
5892 demand_empty_rest_of_line ();
5894 #endif /* ! defined (GPOPT) */
5902 /* Handle the ELF .section pseudo-op. This is a wrapper around
5909 mips_emit_delays ();
5910 obj_elf_section (x
);
5914 #endif /* OBJ_ELF */
5923 mips_emit_delays ();
5924 if (log_size
> 0 && auto_align
)
5925 mips_align (log_size
, 0, label
);
5927 cons (1 << log_size
);
5934 as_fatal ("Encountered `.err', aborting assembly");
5944 symbolP
= get_symbol ();
5945 if (*input_line_pointer
== ',')
5946 input_line_pointer
++;
5947 size
= get_absolute_expression ();
5948 S_SET_EXTERNAL (symbolP
);
5950 #ifdef ECOFF_DEBUGGING
5951 symbolP
->ecoff_extern_size
= size
;
5963 mips_emit_delays ();
5967 mips_align (3, 0, label
);
5969 mips_align (2, 0, label
);
5976 /* Handle .globl. We need to override it because on Irix 5 you are
5979 where foo is an undefined symbol, to mean that foo should be
5980 considered to be the address of a function. */
5990 name
= input_line_pointer
;
5991 c
= get_symbol_end ();
5992 symbolP
= symbol_find_or_make (name
);
5993 *input_line_pointer
= c
;
5995 if (! is_end_of_line
[(unsigned char) *input_line_pointer
])
6000 secname
= input_line_pointer
;
6001 c
= get_symbol_end ();
6002 sec
= bfd_get_section_by_name (stdoutput
, secname
);
6004 as_bad ("%s: no such section", secname
);
6005 *input_line_pointer
= c
;
6007 if (sec
!= NULL
&& (sec
->flags
& SEC_CODE
) != 0)
6008 symbolP
->bsym
->flags
|= BSF_FUNCTION
;
6011 S_SET_EXTERNAL (symbolP
);
6012 demand_empty_rest_of_line ();
6022 opt
= input_line_pointer
;
6023 c
= get_symbol_end ();
6027 /* FIXME: What does this mean? */
6029 else if (strncmp (opt
, "pic", 3) == 0)
6037 mips_pic
= SVR4_PIC
;
6039 as_bad (".option pic%d not supported", i
);
6042 if (mips_pic
== SVR4_PIC
)
6044 if (g_switch_seen
&& g_switch_value
!= 0)
6045 as_warn ("-G may not be used with SVR4 PIC code");
6047 bfd_set_gp_size (stdoutput
, 0);
6052 as_warn ("Unrecognized option \"%s\"", opt
);
6054 *input_line_pointer
= c
;
6055 demand_empty_rest_of_line ();
6062 char *name
= input_line_pointer
, ch
;
6064 while (!is_end_of_line
[(unsigned char) *input_line_pointer
])
6065 input_line_pointer
++;
6066 ch
= *input_line_pointer
;
6067 *input_line_pointer
= '\0';
6069 if (strcmp (name
, "reorder") == 0)
6073 prev_insn_unreordered
= 1;
6074 prev_prev_insn_unreordered
= 1;
6078 else if (strcmp (name
, "noreorder") == 0)
6080 mips_emit_delays ();
6082 mips_any_noreorder
= 1;
6084 else if (strcmp (name
, "at") == 0)
6088 else if (strcmp (name
, "noat") == 0)
6092 else if (strcmp (name
, "macro") == 0)
6094 mips_warn_about_macros
= 0;
6096 else if (strcmp (name
, "nomacro") == 0)
6098 if (mips_noreorder
== 0)
6099 as_bad ("`noreorder' must be set before `nomacro'");
6100 mips_warn_about_macros
= 1;
6102 else if (strcmp (name
, "move") == 0 || strcmp (name
, "novolatile") == 0)
6106 else if (strcmp (name
, "nomove") == 0 || strcmp (name
, "volatile") == 0)
6110 else if (strcmp (name
, "bopt") == 0)
6114 else if (strcmp (name
, "nobopt") == 0)
6118 else if (strncmp (name
, "mips", 4) == 0)
6122 /* Permit the user to change the ISA on the fly. Needless to
6123 say, misuse can cause serious problems. */
6124 isa
= atoi (name
+ 4);
6126 mips_isa
= file_mips_isa
;
6127 else if (isa
< 1 || isa
> 3)
6128 as_bad ("unknown ISA level");
6134 as_warn ("Tried to set unrecognized symbol: %s\n", name
);
6136 *input_line_pointer
= ch
;
6137 demand_empty_rest_of_line ();
6140 /* The same as the usual .space directive, except that we have to
6141 forget about any previous instruction. */
6144 s_mips_space (param
)
6147 mips_emit_delays ();
6152 /* Handle the .abicalls pseudo-op. I believe this is equivalent to
6153 .option pic2. It means to generate SVR4 PIC calls. */
6159 mips_pic
= SVR4_PIC
;
6161 if (g_switch_seen
&& g_switch_value
!= 0)
6162 as_warn ("-G may not be used with SVR4 PIC code");
6165 bfd_set_gp_size (stdoutput
, 0);
6166 demand_empty_rest_of_line ();
6169 /* Handle the .cpload pseudo-op. This is used when generating SVR4
6170 PIC code. It sets the $gp register for the function based on the
6171 function address, which is in the register named in the argument.
6172 This uses a relocation against _gp_disp, which is handled specially
6173 by the linker. The result is:
6174 lui $gp,%hi(_gp_disp)
6175 addiu $gp,$gp,%lo(_gp_disp)
6176 addu $gp,$gp,.cpload argument
6177 The .cpload argument is normally $25 == $t9. */
6186 /* If we are not generating SVR4 PIC code, .cpload is ignored. */
6187 if (mips_pic
!= SVR4_PIC
)
6193 /* .cpload should be a in .set noreorder section. */
6194 if (mips_noreorder
== 0)
6195 as_warn (".cpload not in noreorder section");
6198 ex
.X_add_symbol
= symbol_find_or_make ("_gp_disp");
6199 ex
.X_op_symbol
= NULL
;
6200 ex
.X_add_number
= 0;
6202 macro_build_lui ((char *) NULL
, &icnt
, &ex
, GP
);
6203 macro_build ((char *) NULL
, &icnt
, &ex
, "addiu", "t,r,j", GP
, GP
,
6204 (int) BFD_RELOC_LO16
);
6206 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "addu", "d,v,t",
6207 GP
, GP
, tc_get_register (0));
6209 demand_empty_rest_of_line ();
6212 /* Handle the .cprestore pseudo-op. This stores $gp into a given
6213 offset from $sp. The offset is remembered, and after making a PIC
6214 call $gp is restored from that location. */
6217 s_cprestore (ignore
)
6223 /* If we are not generating SVR4 PIC code, .cprestore is ignored. */
6224 if (mips_pic
!= SVR4_PIC
)
6230 mips_cprestore_offset
= get_absolute_expression ();
6232 ex
.X_op
= O_constant
;
6233 ex
.X_add_symbol
= NULL
;
6234 ex
.X_op_symbol
= NULL
;
6235 ex
.X_add_number
= mips_cprestore_offset
;
6237 macro_build ((char *) NULL
, &icnt
, &ex
,
6238 mips_isa
< 3 ? "sw" : "sd",
6239 "t,o(b)", GP
, (int) BFD_RELOC_LO16
, SP
);
6241 demand_empty_rest_of_line ();
6244 /* Handle the .gpword pseudo-op. This is used when generating PIC
6245 code. It generates a 32 bit GP relative reloc. */
6255 /* When not generating PIC code, this is treated as .word. */
6256 if (mips_pic
!= SVR4_PIC
)
6263 mips_emit_delays ();
6265 mips_align (2, 0, label
);
6270 if (ex
.X_op
!= O_symbol
|| ex
.X_add_number
!= 0)
6272 as_bad ("Unsupported use of .gpword");
6273 ignore_rest_of_line ();
6277 md_number_to_chars (p
, (valueT
) 0, 4);
6278 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 4, &ex
, 0,
6279 BFD_RELOC_MIPS_GPREL32
);
6281 demand_empty_rest_of_line ();
6284 /* Handle the .cpadd pseudo-op. This is used when dealing with switch
6285 tables in SVR4 PIC code. */
6294 /* This is ignored when not generating SVR4 PIC code. */
6295 if (mips_pic
!= SVR4_PIC
)
6301 /* Add $gp to the register named as an argument. */
6302 reg
= tc_get_register (0);
6303 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6304 mips_isa
< 3 ? "addu" : "daddu",
6305 "d,v,t", reg
, reg
, GP
);
6307 demand_empty_rest_of_line ();
6310 /* Parse a register string into a number. Called from the ECOFF code
6311 to parse .frame. The argument is non-zero if this is the frame
6312 register, so that we can record it in mips_frame_reg. */
6315 tc_get_register (frame
)
6321 if (*input_line_pointer
++ != '$')
6323 as_warn ("expected `$'");
6326 else if (isdigit ((unsigned char) *input_line_pointer
))
6328 reg
= get_absolute_expression ();
6329 if (reg
< 0 || reg
>= 32)
6331 as_warn ("Bad register number");
6337 if (strncmp (input_line_pointer
, "fp", 2) == 0)
6339 else if (strncmp (input_line_pointer
, "sp", 2) == 0)
6341 else if (strncmp (input_line_pointer
, "gp", 2) == 0)
6343 else if (strncmp (input_line_pointer
, "at", 2) == 0)
6347 as_warn ("Unrecognized register name");
6350 input_line_pointer
+= 2;
6353 mips_frame_reg
= reg
!= 0 ? reg
: SP
;
6358 md_section_align (seg
, addr
)
6362 int align
= bfd_get_section_alignment (stdoutput
, seg
);
6364 return ((addr
+ (1 << align
) - 1) & (-1 << align
));
6367 /* Estimate the size of a frag before relaxing. We are not really
6368 relaxing here, and the final size is encoded in the subtype
6373 md_estimate_size_before_relax (fragp
, segtype
)
6379 if (mips_pic
== NO_PIC
)
6382 const char *symname
;
6384 /* Find out whether this symbol can be referenced off the GP
6385 register. It can be if it is smaller than the -G size or if
6386 it is in the .sdata or .sbss section. Certain symbols can
6387 not be referenced off the GP, although it appears as though
6389 symname
= S_GET_NAME (fragp
->fr_symbol
);
6390 if (symname
!= (const char *) NULL
6391 && (strcmp (symname
, "eprol") == 0
6392 || strcmp (symname
, "etext") == 0
6393 || strcmp (symname
, "_gp") == 0
6394 || strcmp (symname
, "edata") == 0
6395 || strcmp (symname
, "_fbss") == 0
6396 || strcmp (symname
, "_fdata") == 0
6397 || strcmp (symname
, "_ftext") == 0
6398 || strcmp (symname
, "end") == 0
6399 || strcmp (symname
, "_gp_disp") == 0))
6401 else if (! S_IS_DEFINED (fragp
->fr_symbol
)
6402 && ((fragp
->fr_symbol
->ecoff_extern_size
!= 0
6403 && fragp
->fr_symbol
->ecoff_extern_size
<= g_switch_value
)
6404 || (S_GET_VALUE (fragp
->fr_symbol
) != 0
6405 && S_GET_VALUE (fragp
->fr_symbol
) <= g_switch_value
)))
6409 const char *segname
;
6411 segname
= segment_name (S_GET_SEGMENT (fragp
->fr_symbol
));
6412 assert (strcmp (segname
, ".lit8") != 0
6413 && strcmp (segname
, ".lit4") != 0);
6414 change
= (strcmp (segname
, ".sdata") != 0
6415 && strcmp (segname
, ".sbss") != 0);
6417 #else /* ! defined (GPOPT) */
6418 /* We are not optimizing for the GP register. */
6420 #endif /* ! defined (GPOPT) */
6422 else if (mips_pic
== SVR4_PIC
)
6424 asection
*symsec
= fragp
->fr_symbol
->bsym
->section
;
6426 /* This must duplicate the test in adjust_reloc_syms. */
6427 change
= (symsec
!= &bfd_und_section
6428 && symsec
!= &bfd_abs_section
6429 && ! bfd_is_com_section (symsec
));
6436 /* Record the offset to the first reloc in the fr_opcode field.
6437 This lets md_convert_frag and tc_gen_reloc know that the code
6438 must be expanded. */
6439 fragp
->fr_opcode
= (fragp
->fr_literal
6441 - RELAX_OLD (fragp
->fr_subtype
)
6442 + RELAX_RELOC1 (fragp
->fr_subtype
));
6443 /* FIXME: This really needs as_warn_where. */
6444 if (RELAX_WARN (fragp
->fr_subtype
))
6445 as_warn ("AT used after \".set noat\" or macro used after \".set nomacro\"");
6451 return RELAX_NEW (fragp
->fr_subtype
) - RELAX_OLD (fragp
->fr_subtype
);
6454 /* Translate internal representation of relocation info to BFD target
6458 tc_gen_reloc (section
, fixp
)
6462 static arelent
*retval
[4];
6465 reloc
= retval
[0] = (arelent
*) xmalloc (sizeof (arelent
));
6468 reloc
->sym_ptr_ptr
= &fixp
->fx_addsy
->bsym
;
6469 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
6471 if (mips_pic
== EMBEDDED_PIC
6472 && SWITCH_TABLE (fixp
))
6474 /* For a switch table entry we use a special reloc. The addend
6475 is actually the difference between the reloc address and the
6477 reloc
->addend
= reloc
->address
- S_GET_VALUE (fixp
->fx_subsy
);
6479 as_fatal ("Double check fx_r_type in tc-mips.c:tc_gen_reloc");
6481 fixp
->fx_r_type
= BFD_RELOC_GPREL32
;
6483 else if (fixp
->fx_r_type
== BFD_RELOC_PCREL_LO16
)
6485 /* We use a special addend for an internal RELLO reloc. */
6486 if (fixp
->fx_addsy
->bsym
->flags
& BSF_SECTION_SYM
)
6487 reloc
->addend
= reloc
->address
- S_GET_VALUE (fixp
->fx_subsy
);
6489 reloc
->addend
= fixp
->fx_addnumber
+ reloc
->address
;
6491 else if (fixp
->fx_r_type
== BFD_RELOC_PCREL_HI16_S
)
6493 assert (fixp
->fx_next
!= NULL
6494 && fixp
->fx_next
->fx_r_type
== BFD_RELOC_PCREL_LO16
);
6495 /* We use a special addend for an internal RELHI reloc. The
6496 reloc is relative to the RELLO; adjust the addend
6498 if (fixp
->fx_addsy
->bsym
->flags
& BSF_SECTION_SYM
)
6499 reloc
->addend
= (fixp
->fx_next
->fx_frag
->fr_address
6500 + fixp
->fx_next
->fx_where
6501 - S_GET_VALUE (fixp
->fx_subsy
));
6503 reloc
->addend
= (fixp
->fx_addnumber
6504 + fixp
->fx_next
->fx_frag
->fr_address
6505 + fixp
->fx_next
->fx_where
);
6507 else if (fixp
->fx_pcrel
== 0)
6508 reloc
->addend
= fixp
->fx_addnumber
;
6512 /* A gruesome hack which is a result of the gruesome gas reloc
6514 reloc
->addend
= reloc
->address
;
6516 reloc
->addend
= -reloc
->address
;
6520 /* If this is a variant frag, we may need to adjust the existing
6521 reloc and generate a new one. */
6522 if (fixp
->fx_frag
->fr_opcode
!= NULL
6523 && (fixp
->fx_r_type
== BFD_RELOC_MIPS_GPREL
6524 || fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT16
6525 || fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL16
))
6529 /* If this is not the last reloc in this frag, then we have two
6530 GPREL relocs, both of which are being replaced. Let the
6531 second one handle all of them. */
6532 if (fixp
->fx_next
!= NULL
6533 && fixp
->fx_frag
== fixp
->fx_next
->fx_frag
)
6535 assert (fixp
->fx_r_type
== BFD_RELOC_MIPS_GPREL
6536 && fixp
->fx_next
->fx_r_type
== BFD_RELOC_MIPS_GPREL
);
6541 fixp
->fx_where
= fixp
->fx_frag
->fr_opcode
- fixp
->fx_frag
->fr_literal
;
6542 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
6543 reloc2
= retval
[1] = (arelent
*) xmalloc (sizeof (arelent
));
6545 reloc2
->sym_ptr_ptr
= &fixp
->fx_addsy
->bsym
;
6546 reloc2
->address
= (reloc
->address
6547 + (RELAX_RELOC2 (fixp
->fx_frag
->fr_subtype
)
6548 - RELAX_RELOC1 (fixp
->fx_frag
->fr_subtype
)));
6549 reloc2
->addend
= fixp
->fx_addnumber
;
6550 reloc2
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_LO16
);
6551 assert (reloc2
->howto
!= NULL
);
6553 if (RELAX_RELOC3 (fixp
->fx_frag
->fr_subtype
))
6557 reloc3
= retval
[2] = (arelent
*) xmalloc (sizeof (arelent
));
6560 reloc3
->address
+= 4;
6563 if (mips_pic
== NO_PIC
)
6565 assert (fixp
->fx_r_type
== BFD_RELOC_MIPS_GPREL
);
6566 fixp
->fx_r_type
= BFD_RELOC_HI16_S
;
6568 else if (mips_pic
== SVR4_PIC
)
6570 if (fixp
->fx_r_type
!= BFD_RELOC_MIPS_GOT16
)
6572 assert (fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL16
);
6573 fixp
->fx_r_type
= BFD_RELOC_MIPS_GOT16
;
6580 /* To support a PC relative reloc when generating embedded PIC code
6581 for ECOFF, we use a Cygnus extension. We check for that here to
6582 make sure that we don't let such a reloc escape normally. */
6584 if (fixp
->fx_r_type
== BFD_RELOC_16_PCREL_S2
6585 && mips_pic
!= EMBEDDED_PIC
)
6586 reloc
->howto
= NULL
;
6589 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, fixp
->fx_r_type
);
6591 if (reloc
->howto
== NULL
)
6593 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
6594 "Can not represent relocation in this object file format");
6601 /* Convert a machine dependent frag. */
6604 md_convert_frag (abfd
, asec
, fragp
)
6612 if (fragp
->fr_opcode
== NULL
)
6615 old
= RELAX_OLD (fragp
->fr_subtype
);
6616 new = RELAX_NEW (fragp
->fr_subtype
);
6617 fixptr
= fragp
->fr_literal
+ fragp
->fr_fix
;
6620 memcpy (fixptr
- old
, fixptr
, new);
6622 fragp
->fr_fix
+= new - old
;
6625 /* This function is called whenever a label is defined. It is used
6626 when handling branch delays; if a branch has a label, we assume we
6630 mips_define_label (sym
)
6638 /* Some special processing for a MIPS ELF file. */
6641 mips_elf_final_processing ()
6645 /* Write out the .reginfo section. */
6646 s
.ri_gprmask
= mips_gprmask
;
6647 s
.ri_cprmask
[0] = mips_cprmask
[0];
6648 s
.ri_cprmask
[1] = mips_cprmask
[1];
6649 s
.ri_cprmask
[2] = mips_cprmask
[2];
6650 s
.ri_cprmask
[3] = mips_cprmask
[3];
6651 /* The gp_value field is set by the MIPS ELF backend. */
6653 bfd_mips_elf32_swap_reginfo_out (stdoutput
, &s
,
6654 ((Elf32_External_RegInfo
*)
6655 mips_regmask_frag
));
6657 /* Set the MIPS ELF flag bits. FIXME: There should probably be some
6658 sort of BFD interface for this. */
6659 if (mips_any_noreorder
)
6660 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_NOREORDER
;
6661 if (mips_pic
!= NO_PIC
)
6662 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_PIC
;
6665 #endif /* OBJ_ELF */
6667 #ifndef ECOFF_DEBUGGING
6669 /* These functions should really be defined by the object file format,
6670 since they are related to debugging information. However, this
6671 code has to work for the a.out format, which does not define them,
6672 so we provide simple versions here. These don't actually generate
6673 any debugging information, but they do simple checking and someday
6674 somebody may make them useful. */
6678 struct loc
*loc_next
;
6679 unsigned long loc_fileno
;
6680 unsigned long loc_lineno
;
6681 unsigned long loc_offset
;
6682 unsigned short loc_delta
;
6683 unsigned short loc_count
;
6692 struct proc
*proc_next
;
6693 struct symbol
*proc_isym
;
6694 struct symbol
*proc_end
;
6695 unsigned long proc_reg_mask
;
6696 unsigned long proc_reg_offset
;
6697 unsigned long proc_fpreg_mask
;
6698 unsigned long proc_fpreg_offset
;
6699 unsigned long proc_frameoffset
;
6700 unsigned long proc_framereg
;
6701 unsigned long proc_pcreg
;
6703 struct file
*proc_file
;
6710 struct file
*file_next
;
6711 unsigned long file_fileno
;
6712 struct symbol
*file_symbol
;
6713 struct symbol
*file_end
;
6714 struct proc
*file_proc
;
6719 static struct obstack proc_frags
;
6720 static procS
*proc_lastP
;
6721 static procS
*proc_rootP
;
6722 static int numprocs
;
6727 obstack_begin (&proc_frags
, 0x2000);
6733 /* check for premature end, nesting errors, etc */
6734 if (proc_lastP
&& proc_lastP
->proc_end
== NULL
)
6735 as_warn ("missing `.end' at end of assembly");
6744 if (*input_line_pointer
== '-')
6746 ++input_line_pointer
;
6749 if (!isdigit (*input_line_pointer
))
6750 as_bad ("Expected simple number.");
6751 if (input_line_pointer
[0] == '0')
6753 if (input_line_pointer
[1] == 'x')
6755 input_line_pointer
+= 2;
6756 while (isxdigit (*input_line_pointer
))
6759 val
|= hex_value (*input_line_pointer
++);
6761 return negative
? -val
: val
;
6765 ++input_line_pointer
;
6766 while (isdigit (*input_line_pointer
))
6769 val
|= *input_line_pointer
++ - '0';
6771 return negative
? -val
: val
;
6774 if (!isdigit (*input_line_pointer
))
6776 printf (" *input_line_pointer == '%c' 0x%02x\n",
6777 *input_line_pointer
, *input_line_pointer
);
6778 as_warn ("Invalid number");
6781 while (isdigit (*input_line_pointer
))
6784 val
+= *input_line_pointer
++ - '0';
6786 return negative
? -val
: val
;
6789 /* The .file directive; just like the usual .file directive, but there
6790 is an initial number which is the ECOFF file index. */
6798 line
= get_number ();
6803 /* The .end directive. */
6811 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
6814 demand_empty_rest_of_line ();
6818 if (now_seg
!= text_section
)
6819 as_warn (".end not in text section");
6822 as_warn (".end and no .ent seen yet.");
6828 assert (S_GET_NAME (p
));
6829 if (strcmp (S_GET_NAME (p
), S_GET_NAME (proc_lastP
->proc_isym
)))
6830 as_warn (".end symbol does not match .ent symbol.");
6833 proc_lastP
->proc_end
= (symbolS
*) 1;
6836 /* The .aent and .ent directives. */
6846 symbolP
= get_symbol ();
6847 if (*input_line_pointer
== ',')
6848 input_line_pointer
++;
6850 if (isdigit (*input_line_pointer
) || *input_line_pointer
== '-')
6851 number
= get_number ();
6852 if (now_seg
!= text_section
)
6853 as_warn (".ent or .aent not in text section.");
6855 if (!aent
&& proc_lastP
&& proc_lastP
->proc_end
== NULL
)
6856 as_warn ("missing `.end'");
6860 procP
= (procS
*) obstack_alloc (&proc_frags
, sizeof (*procP
));
6861 procP
->proc_isym
= symbolP
;
6862 procP
->proc_reg_mask
= 0;
6863 procP
->proc_reg_offset
= 0;
6864 procP
->proc_fpreg_mask
= 0;
6865 procP
->proc_fpreg_offset
= 0;
6866 procP
->proc_frameoffset
= 0;
6867 procP
->proc_framereg
= 0;
6868 procP
->proc_pcreg
= 0;
6869 procP
->proc_end
= NULL
;
6870 procP
->proc_next
= NULL
;
6872 proc_lastP
->proc_next
= procP
;
6878 demand_empty_rest_of_line ();
6881 /* The .frame directive. */
6894 frame_reg
= tc_get_register (1);
6895 if (*input_line_pointer
== ',')
6896 input_line_pointer
++;
6897 frame_off
= get_absolute_expression ();
6898 if (*input_line_pointer
== ',')
6899 input_line_pointer
++;
6900 pcreg
= tc_get_register (0);
6903 assert (proc_rootP
);
6904 proc_rootP
->proc_framereg
= frame_reg
;
6905 proc_rootP
->proc_frameoffset
= frame_off
;
6906 proc_rootP
->proc_pcreg
= pcreg
;
6907 /* bob macho .frame */
6909 /* We don't have to write out a frame stab for unoptimized code. */
6910 if (!(frame_reg
== FP
&& frame_off
== 0))
6913 as_warn ("No .ent for .frame to use.");
6914 (void) sprintf (str
, "R%d;%d", frame_reg
, frame_off
);
6915 symP
= symbol_new (str
, N_VFP
, 0, frag_now
);
6916 S_SET_TYPE (symP
, N_RMASK
);
6917 S_SET_OTHER (symP
, 0);
6918 S_SET_DESC (symP
, 0);
6919 symP
->sy_forward
= proc_lastP
->proc_isym
;
6920 /* bob perhaps I should have used pseudo set */
6922 demand_empty_rest_of_line ();
6926 /* The .fmask and .mask directives. */
6933 char str
[100], *strP
;
6939 mask
= get_number ();
6940 if (*input_line_pointer
== ',')
6941 input_line_pointer
++;
6942 off
= get_absolute_expression ();
6944 /* bob only for coff */
6945 assert (proc_rootP
);
6946 if (reg_type
== 'F')
6948 proc_rootP
->proc_fpreg_mask
= mask
;
6949 proc_rootP
->proc_fpreg_offset
= off
;
6953 proc_rootP
->proc_reg_mask
= mask
;
6954 proc_rootP
->proc_reg_offset
= off
;
6957 /* bob macho .mask + .fmask */
6959 /* We don't have to write out a mask stab if no saved regs. */
6963 as_warn ("No .ent for .mask to use.");
6965 for (i
= 0; i
< 32; i
++)
6969 sprintf (strP
, "%c%d,", reg_type
, i
);
6970 strP
+= strlen (strP
);
6974 sprintf (strP
, ";%d,", off
);
6975 symP
= symbol_new (str
, N_RMASK
, 0, frag_now
);
6976 S_SET_TYPE (symP
, N_RMASK
);
6977 S_SET_OTHER (symP
, 0);
6978 S_SET_DESC (symP
, 0);
6979 symP
->sy_forward
= proc_lastP
->proc_isym
;
6980 /* bob perhaps I should have used pseudo set */
6985 /* The .loc directive. */
6996 assert (now_seg
== text_section
);
6998 lineno
= get_number ();
6999 addroff
= frag_now_fix ();
7001 symbolP
= symbol_new ("", N_SLINE
, addroff
, frag_now
);
7002 S_SET_TYPE (symbolP
, N_SLINE
);
7003 S_SET_OTHER (symbolP
, 0);
7004 S_SET_DESC (symbolP
, lineno
);
7005 symbolP
->sy_segment
= now_seg
;
7009 #endif /* ! defined (ECOFF_DEBUGGING) */