1 /* tc-mips.c -- assemble code for a MIPS chip.
2 Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,
3 2003, 2004, 2005 Free Software Foundation, Inc.
4 Contributed by the OSF and Ralph Campbell.
5 Written by Keith Knowles and Ralph Campbell, working independently.
6 Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus
9 This file is part of GAS.
11 GAS is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 2, or (at your option)
16 GAS is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
21 You should have received a copy of the GNU General Public License
22 along with GAS; see the file COPYING. If not, write to the Free
23 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
29 #include "safe-ctype.h"
33 #include "opcode/mips.h"
35 #include "dwarf2dbg.h"
38 #define DBG(x) printf x
44 /* Clean up namespace so we can include obj-elf.h too. */
45 static int mips_output_flavor (void);
46 static int mips_output_flavor (void) { return OUTPUT_FLAVOR
; }
47 #undef OBJ_PROCESS_STAB
54 #undef obj_frob_file_after_relocs
55 #undef obj_frob_symbol
57 #undef obj_sec_sym_ok_for_reloc
58 #undef OBJ_COPY_SYMBOL_ATTRIBUTES
61 /* Fix any of them that we actually care about. */
63 #define OUTPUT_FLAVOR mips_output_flavor()
70 #ifndef ECOFF_DEBUGGING
71 #define NO_ECOFF_DEBUGGING
72 #define ECOFF_DEBUGGING 0
75 int mips_flag_mdebug
= -1;
77 /* Control generation of .pdr sections. Off by default on IRIX: the native
78 linker doesn't know about and discards them, but relocations against them
79 remain, leading to rld crashes. */
81 int mips_flag_pdr
= FALSE
;
83 int mips_flag_pdr
= TRUE
;
88 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
89 static char *mips_regmask_frag
;
95 #define PIC_CALL_REG 25
103 #define ILLEGAL_REG (32)
105 /* Allow override of standard little-endian ECOFF format. */
107 #ifndef ECOFF_LITTLE_FORMAT
108 #define ECOFF_LITTLE_FORMAT "ecoff-littlemips"
111 extern int target_big_endian
;
113 /* The name of the readonly data section. */
114 #define RDATA_SECTION_NAME (OUTPUT_FLAVOR == bfd_target_ecoff_flavour \
116 : OUTPUT_FLAVOR == bfd_target_coff_flavour \
118 : OUTPUT_FLAVOR == bfd_target_elf_flavour \
122 /* The ABI to use. */
133 /* MIPS ABI we are using for this output file. */
134 static enum mips_abi_level mips_abi
= NO_ABI
;
136 /* Whether or not we have code that can call pic code. */
137 int mips_abicalls
= FALSE
;
139 /* Whether or not we have code which can be put into a shared
141 static bfd_boolean mips_in_shared
= TRUE
;
143 /* This is the set of options which may be modified by the .set
144 pseudo-op. We use a struct so that .set push and .set pop are more
147 struct mips_set_options
149 /* MIPS ISA (Instruction Set Architecture) level. This is set to -1
150 if it has not been initialized. Changed by `.set mipsN', and the
151 -mipsN command line option, and the default CPU. */
153 /* Enabled Application Specific Extensions (ASEs). These are set to -1
154 if they have not been initialized. Changed by `.set <asename>', by
155 command line options, and based on the default architecture. */
158 /* Whether we are assembling for the mips16 processor. 0 if we are
159 not, 1 if we are, and -1 if the value has not been initialized.
160 Changed by `.set mips16' and `.set nomips16', and the -mips16 and
161 -nomips16 command line options, and the default CPU. */
163 /* Non-zero if we should not reorder instructions. Changed by `.set
164 reorder' and `.set noreorder'. */
166 /* Non-zero if we should not permit the $at ($1) register to be used
167 in instructions. Changed by `.set at' and `.set noat'. */
169 /* Non-zero if we should warn when a macro instruction expands into
170 more than one machine instruction. Changed by `.set nomacro' and
172 int warn_about_macros
;
173 /* Non-zero if we should not move instructions. Changed by `.set
174 move', `.set volatile', `.set nomove', and `.set novolatile'. */
176 /* Non-zero if we should not optimize branches by moving the target
177 of the branch into the delay slot. Actually, we don't perform
178 this optimization anyhow. Changed by `.set bopt' and `.set
181 /* Non-zero if we should not autoextend mips16 instructions.
182 Changed by `.set autoextend' and `.set noautoextend'. */
184 /* Restrict general purpose registers and floating point registers
185 to 32 bit. This is initially determined when -mgp32 or -mfp32
186 is passed but can changed if the assembler code uses .set mipsN. */
189 /* MIPS architecture (CPU) type. Changed by .set arch=FOO, the -march
190 command line option, and the default CPU. */
194 /* True if -mgp32 was passed. */
195 static int file_mips_gp32
= -1;
197 /* True if -mfp32 was passed. */
198 static int file_mips_fp32
= -1;
200 /* This is the struct we use to hold the current set of options. Note
201 that we must set the isa field to ISA_UNKNOWN and the ASE fields to
202 -1 to indicate that they have not been initialized. */
204 static struct mips_set_options mips_opts
=
206 ISA_UNKNOWN
, -1, -1, -1, 0, 0, 0, 0, 0, 0, 0, 0, CPU_UNKNOWN
209 /* These variables are filled in with the masks of registers used.
210 The object format code reads them and puts them in the appropriate
212 unsigned long mips_gprmask
;
213 unsigned long mips_cprmask
[4];
215 /* MIPS ISA we are using for this output file. */
216 static int file_mips_isa
= ISA_UNKNOWN
;
218 /* True if -mips16 was passed or implied by arguments passed on the
219 command line (e.g., by -march). */
220 static int file_ase_mips16
;
222 /* True if -mips3d was passed or implied by arguments passed on the
223 command line (e.g., by -march). */
224 static int file_ase_mips3d
;
226 /* True if -mdmx was passed or implied by arguments passed on the
227 command line (e.g., by -march). */
228 static int file_ase_mdmx
;
230 /* The argument of the -march= flag. The architecture we are assembling. */
231 static int file_mips_arch
= CPU_UNKNOWN
;
232 static const char *mips_arch_string
;
234 /* The argument of the -mtune= flag. The architecture for which we
236 static int mips_tune
= CPU_UNKNOWN
;
237 static const char *mips_tune_string
;
239 /* True when generating 32-bit code for a 64-bit processor. */
240 static int mips_32bitmode
= 0;
242 /* True if the given ABI requires 32-bit registers. */
243 #define ABI_NEEDS_32BIT_REGS(ABI) ((ABI) == O32_ABI)
245 /* Likewise 64-bit registers. */
246 #define ABI_NEEDS_64BIT_REGS(ABI) \
248 || (ABI) == N64_ABI \
251 /* Return true if ISA supports 64 bit gp register instructions. */
252 #define ISA_HAS_64BIT_REGS(ISA) ( \
254 || (ISA) == ISA_MIPS4 \
255 || (ISA) == ISA_MIPS5 \
256 || (ISA) == ISA_MIPS64 \
257 || (ISA) == ISA_MIPS64R2 \
260 /* Return true if ISA supports 64-bit right rotate (dror et al.)
262 #define ISA_HAS_DROR(ISA) ( \
263 (ISA) == ISA_MIPS64R2 \
266 /* Return true if ISA supports 32-bit right rotate (ror et al.)
268 #define ISA_HAS_ROR(ISA) ( \
269 (ISA) == ISA_MIPS32R2 \
270 || (ISA) == ISA_MIPS64R2 \
273 #define HAVE_32BIT_GPRS \
274 (mips_opts.gp32 || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
276 #define HAVE_32BIT_FPRS \
277 (mips_opts.fp32 || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
279 #define HAVE_64BIT_GPRS (! HAVE_32BIT_GPRS)
280 #define HAVE_64BIT_FPRS (! HAVE_32BIT_FPRS)
282 #define HAVE_NEWABI (mips_abi == N32_ABI || mips_abi == N64_ABI)
284 #define HAVE_64BIT_OBJECTS (mips_abi == N64_ABI)
286 /* True if relocations are stored in-place. */
287 #define HAVE_IN_PLACE_ADDENDS (!HAVE_NEWABI)
289 /* We can only have 64bit addresses if the object file format supports it. */
290 #define HAVE_32BIT_ADDRESSES \
292 || (bfd_arch_bits_per_address (stdoutput) == 32 \
293 || ! HAVE_64BIT_OBJECTS)) \
295 #define HAVE_64BIT_ADDRESSES (! HAVE_32BIT_ADDRESSES)
297 /* Addresses are loaded in different ways, depending on the address size
298 in use. The n32 ABI Documentation also mandates the use of additions
299 with overflow checking, but existing implementations don't follow it. */
300 #define ADDRESS_ADD_INSN \
301 (HAVE_32BIT_ADDRESSES ? "addu" : "daddu")
303 #define ADDRESS_ADDI_INSN \
304 (HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu")
306 #define ADDRESS_LOAD_INSN \
307 (HAVE_32BIT_ADDRESSES ? "lw" : "ld")
309 #define ADDRESS_STORE_INSN \
310 (HAVE_32BIT_ADDRESSES ? "sw" : "sd")
312 /* Return true if the given CPU supports the MIPS16 ASE. */
313 #define CPU_HAS_MIPS16(cpu) \
314 (strncmp (TARGET_CPU, "mips16", sizeof ("mips16") - 1) == 0 \
315 || strncmp (TARGET_CANONICAL, "mips-lsi-elf", sizeof ("mips-lsi-elf") - 1) == 0)
317 /* Return true if the given CPU supports the MIPS3D ASE. */
318 #define CPU_HAS_MIPS3D(cpu) ((cpu) == CPU_SB1 \
321 /* Return true if the given CPU supports the MDMX ASE. */
322 #define CPU_HAS_MDMX(cpu) (FALSE \
325 /* True if CPU has a dror instruction. */
326 #define CPU_HAS_DROR(CPU) ((CPU) == CPU_VR5400 || (CPU) == CPU_VR5500)
328 /* True if CPU has a ror instruction. */
329 #define CPU_HAS_ROR(CPU) CPU_HAS_DROR (CPU)
331 /* True if mflo and mfhi can be immediately followed by instructions
332 which write to the HI and LO registers.
334 According to MIPS specifications, MIPS ISAs I, II, and III need
335 (at least) two instructions between the reads of HI/LO and
336 instructions which write them, and later ISAs do not. Contradicting
337 the MIPS specifications, some MIPS IV processor user manuals (e.g.
338 the UM for the NEC Vr5000) document needing the instructions between
339 HI/LO reads and writes, as well. Therefore, we declare only MIPS32,
340 MIPS64 and later ISAs to have the interlocks, plus any specific
341 earlier-ISA CPUs for which CPU documentation declares that the
342 instructions are really interlocked. */
343 #define hilo_interlocks \
344 (mips_opts.isa == ISA_MIPS32 \
345 || mips_opts.isa == ISA_MIPS32R2 \
346 || mips_opts.isa == ISA_MIPS64 \
347 || mips_opts.isa == ISA_MIPS64R2 \
348 || mips_opts.arch == CPU_R4010 \
349 || mips_opts.arch == CPU_R10000 \
350 || mips_opts.arch == CPU_R12000 \
351 || mips_opts.arch == CPU_RM7000 \
352 || mips_opts.arch == CPU_VR5500 \
355 /* Whether the processor uses hardware interlocks to protect reads
356 from the GPRs after they are loaded from memory, and thus does not
357 require nops to be inserted. This applies to instructions marked
358 INSN_LOAD_MEMORY_DELAY. These nops are only required at MIPS ISA
360 #define gpr_interlocks \
361 (mips_opts.isa != ISA_MIPS1 \
362 || mips_opts.arch == CPU_R3900)
364 /* Whether the processor uses hardware interlocks to avoid delays
365 required by coprocessor instructions, and thus does not require
366 nops to be inserted. This applies to instructions marked
367 INSN_LOAD_COPROC_DELAY, INSN_COPROC_MOVE_DELAY, and to delays
368 between instructions marked INSN_WRITE_COND_CODE and ones marked
369 INSN_READ_COND_CODE. These nops are only required at MIPS ISA
370 levels I, II, and III. */
371 /* Itbl support may require additional care here. */
372 #define cop_interlocks \
373 ((mips_opts.isa != ISA_MIPS1 \
374 && mips_opts.isa != ISA_MIPS2 \
375 && mips_opts.isa != ISA_MIPS3) \
376 || mips_opts.arch == CPU_R4300 \
379 /* Whether the processor uses hardware interlocks to protect reads
380 from coprocessor registers after they are loaded from memory, and
381 thus does not require nops to be inserted. This applies to
382 instructions marked INSN_COPROC_MEMORY_DELAY. These nops are only
383 requires at MIPS ISA level I. */
384 #define cop_mem_interlocks (mips_opts.isa != ISA_MIPS1)
386 /* Is this a mfhi or mflo instruction? */
387 #define MF_HILO_INSN(PINFO) \
388 ((PINFO & INSN_READ_HI) || (PINFO & INSN_READ_LO))
390 /* MIPS PIC level. */
392 enum mips_pic_level mips_pic
;
394 /* 1 if we should generate 32 bit offsets from the $gp register in
395 SVR4_PIC mode. Currently has no meaning in other modes. */
396 static int mips_big_got
= 0;
398 /* 1 if trap instructions should used for overflow rather than break
400 static int mips_trap
= 0;
402 /* 1 if double width floating point constants should not be constructed
403 by assembling two single width halves into two single width floating
404 point registers which just happen to alias the double width destination
405 register. On some architectures this aliasing can be disabled by a bit
406 in the status register, and the setting of this bit cannot be determined
407 automatically at assemble time. */
408 static int mips_disable_float_construction
;
410 /* Non-zero if any .set noreorder directives were used. */
412 static int mips_any_noreorder
;
414 /* Non-zero if nops should be inserted when the register referenced in
415 an mfhi/mflo instruction is read in the next two instructions. */
416 static int mips_7000_hilo_fix
;
418 /* The size of the small data section. */
419 static unsigned int g_switch_value
= 8;
420 /* Whether the -G option was used. */
421 static int g_switch_seen
= 0;
426 /* If we can determine in advance that GP optimization won't be
427 possible, we can skip the relaxation stuff that tries to produce
428 GP-relative references. This makes delay slot optimization work
431 This function can only provide a guess, but it seems to work for
432 gcc output. It needs to guess right for gcc, otherwise gcc
433 will put what it thinks is a GP-relative instruction in a branch
436 I don't know if a fix is needed for the SVR4_PIC mode. I've only
437 fixed it for the non-PIC mode. KR 95/04/07 */
438 static int nopic_need_relax (symbolS
*, int);
440 /* handle of the OPCODE hash table */
441 static struct hash_control
*op_hash
= NULL
;
443 /* The opcode hash table we use for the mips16. */
444 static struct hash_control
*mips16_op_hash
= NULL
;
446 /* This array holds the chars that always start a comment. If the
447 pre-processor is disabled, these aren't very useful */
448 const char comment_chars
[] = "#";
450 /* This array holds the chars that only start a comment at the beginning of
451 a line. If the line seems to have the form '# 123 filename'
452 .line and .file directives will appear in the pre-processed output */
453 /* Note that input_file.c hand checks for '#' at the beginning of the
454 first line of the input file. This is because the compiler outputs
455 #NO_APP at the beginning of its output. */
456 /* Also note that C style comments are always supported. */
457 const char line_comment_chars
[] = "#";
459 /* This array holds machine specific line separator characters. */
460 const char line_separator_chars
[] = ";";
462 /* Chars that can be used to separate mant from exp in floating point nums */
463 const char EXP_CHARS
[] = "eE";
465 /* Chars that mean this number is a floating point constant */
468 const char FLT_CHARS
[] = "rRsSfFdDxXpP";
470 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
471 changed in read.c . Ideally it shouldn't have to know about it at all,
472 but nothing is ideal around here.
475 static char *insn_error
;
477 static int auto_align
= 1;
479 /* When outputting SVR4 PIC code, the assembler needs to know the
480 offset in the stack frame from which to restore the $gp register.
481 This is set by the .cprestore pseudo-op, and saved in this
483 static offsetT mips_cprestore_offset
= -1;
485 /* Similar for NewABI PIC code, where $gp is callee-saved. NewABI has some
486 more optimizations, it can use a register value instead of a memory-saved
487 offset and even an other register than $gp as global pointer. */
488 static offsetT mips_cpreturn_offset
= -1;
489 static int mips_cpreturn_register
= -1;
490 static int mips_gp_register
= GP
;
491 static int mips_gprel_offset
= 0;
493 /* Whether mips_cprestore_offset has been set in the current function
494 (or whether it has already been warned about, if not). */
495 static int mips_cprestore_valid
= 0;
497 /* This is the register which holds the stack frame, as set by the
498 .frame pseudo-op. This is needed to implement .cprestore. */
499 static int mips_frame_reg
= SP
;
501 /* Whether mips_frame_reg has been set in the current function
502 (or whether it has already been warned about, if not). */
503 static int mips_frame_reg_valid
= 0;
505 /* To output NOP instructions correctly, we need to keep information
506 about the previous two instructions. */
508 /* Whether we are optimizing. The default value of 2 means to remove
509 unneeded NOPs and swap branch instructions when possible. A value
510 of 1 means to not swap branches. A value of 0 means to always
512 static int mips_optimize
= 2;
514 /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is
515 equivalent to seeing no -g option at all. */
516 static int mips_debug
= 0;
518 /* The previous instruction. */
519 static struct mips_cl_insn prev_insn
;
521 /* The instruction before prev_insn. */
522 static struct mips_cl_insn prev_prev_insn
;
524 /* If we don't want information for prev_insn or prev_prev_insn, we
525 point the insn_mo field at this dummy integer. */
526 static const struct mips_opcode dummy_opcode
= { NULL
, NULL
, 0, 0, 0, 0, 0 };
528 /* Non-zero if prev_insn is valid. */
529 static int prev_insn_valid
;
531 /* The frag for the previous instruction. */
532 static struct frag
*prev_insn_frag
;
534 /* The offset into prev_insn_frag for the previous instruction. */
535 static long prev_insn_where
;
537 /* The reloc type for the previous instruction, if any. */
538 static bfd_reloc_code_real_type prev_insn_reloc_type
[3];
540 /* The reloc for the previous instruction, if any. */
541 static fixS
*prev_insn_fixp
[3];
543 /* Non-zero if the previous instruction was in a delay slot. */
544 static int prev_insn_is_delay_slot
;
546 /* Non-zero if the previous instruction was in a .set noreorder. */
547 static int prev_insn_unreordered
;
549 /* Non-zero if the previous instruction uses an extend opcode (if
551 static int prev_insn_extended
;
553 /* Non-zero if the previous previous instruction was in a .set
555 static int prev_prev_insn_unreordered
;
557 /* If this is set, it points to a frag holding nop instructions which
558 were inserted before the start of a noreorder section. If those
559 nops turn out to be unnecessary, the size of the frag can be
561 static fragS
*prev_nop_frag
;
563 /* The number of nop instructions we created in prev_nop_frag. */
564 static int prev_nop_frag_holds
;
566 /* The number of nop instructions that we know we need in
568 static int prev_nop_frag_required
;
570 /* The number of instructions we've seen since prev_nop_frag. */
571 static int prev_nop_frag_since
;
573 /* For ECOFF and ELF, relocations against symbols are done in two
574 parts, with a HI relocation and a LO relocation. Each relocation
575 has only 16 bits of space to store an addend. This means that in
576 order for the linker to handle carries correctly, it must be able
577 to locate both the HI and the LO relocation. This means that the
578 relocations must appear in order in the relocation table.
580 In order to implement this, we keep track of each unmatched HI
581 relocation. We then sort them so that they immediately precede the
582 corresponding LO relocation. */
587 struct mips_hi_fixup
*next
;
590 /* The section this fixup is in. */
594 /* The list of unmatched HI relocs. */
596 static struct mips_hi_fixup
*mips_hi_fixup_list
;
598 /* The frag containing the last explicit relocation operator.
599 Null if explicit relocations have not been used. */
601 static fragS
*prev_reloc_op_frag
;
603 /* Map normal MIPS register numbers to mips16 register numbers. */
605 #define X ILLEGAL_REG
606 static const int mips32_to_16_reg_map
[] =
608 X
, X
, 2, 3, 4, 5, 6, 7,
609 X
, X
, X
, X
, X
, X
, X
, X
,
610 0, 1, X
, X
, X
, X
, X
, X
,
611 X
, X
, X
, X
, X
, X
, X
, X
615 /* Map mips16 register numbers to normal MIPS register numbers. */
617 static const unsigned int mips16_to_32_reg_map
[] =
619 16, 17, 2, 3, 4, 5, 6, 7
622 static int mips_fix_vr4120
;
624 /* We don't relax branches by default, since this causes us to expand
625 `la .l2 - .l1' if there's a branch between .l1 and .l2, because we
626 fail to compute the offset before expanding the macro to the most
627 efficient expansion. */
629 static int mips_relax_branch
;
631 /* The expansion of many macros depends on the type of symbol that
632 they refer to. For example, when generating position-dependent code,
633 a macro that refers to a symbol may have two different expansions,
634 one which uses GP-relative addresses and one which uses absolute
635 addresses. When generating SVR4-style PIC, a macro may have
636 different expansions for local and global symbols.
638 We handle these situations by generating both sequences and putting
639 them in variant frags. In position-dependent code, the first sequence
640 will be the GP-relative one and the second sequence will be the
641 absolute one. In SVR4 PIC, the first sequence will be for global
642 symbols and the second will be for local symbols.
644 The frag's "subtype" is RELAX_ENCODE (FIRST, SECOND), where FIRST and
645 SECOND are the lengths of the two sequences in bytes. These fields
646 can be extracted using RELAX_FIRST() and RELAX_SECOND(). In addition,
647 the subtype has the following flags:
650 Set if it has been decided that we should use the second
651 sequence instead of the first.
654 Set in the first variant frag if the macro's second implementation
655 is longer than its first. This refers to the macro as a whole,
656 not an individual relaxation.
659 Set in the first variant frag if the macro appeared in a .set nomacro
660 block and if one alternative requires a warning but the other does not.
663 Like RELAX_NOMACRO, but indicates that the macro appears in a branch
666 The frag's "opcode" points to the first fixup for relaxable code.
668 Relaxable macros are generated using a sequence such as:
670 relax_start (SYMBOL);
671 ... generate first expansion ...
673 ... generate second expansion ...
676 The code and fixups for the unwanted alternative are discarded
677 by md_convert_frag. */
678 #define RELAX_ENCODE(FIRST, SECOND) (((FIRST) << 8) | (SECOND))
680 #define RELAX_FIRST(X) (((X) >> 8) & 0xff)
681 #define RELAX_SECOND(X) ((X) & 0xff)
682 #define RELAX_USE_SECOND 0x10000
683 #define RELAX_SECOND_LONGER 0x20000
684 #define RELAX_NOMACRO 0x40000
685 #define RELAX_DELAY_SLOT 0x80000
687 /* Branch without likely bit. If label is out of range, we turn:
689 beq reg1, reg2, label
699 with the following opcode replacements:
706 bltzal <-> bgezal (with jal label instead of j label)
708 Even though keeping the delay slot instruction in the delay slot of
709 the branch would be more efficient, it would be very tricky to do
710 correctly, because we'd have to introduce a variable frag *after*
711 the delay slot instruction, and expand that instead. Let's do it
712 the easy way for now, even if the branch-not-taken case now costs
713 one additional instruction. Out-of-range branches are not supposed
714 to be common, anyway.
716 Branch likely. If label is out of range, we turn:
718 beql reg1, reg2, label
719 delay slot (annulled if branch not taken)
728 delay slot (executed only if branch taken)
731 It would be possible to generate a shorter sequence by losing the
732 likely bit, generating something like:
737 delay slot (executed only if branch taken)
749 bltzall -> bgezal (with jal label instead of j label)
750 bgezall -> bltzal (ditto)
753 but it's not clear that it would actually improve performance. */
754 #define RELAX_BRANCH_ENCODE(uncond, likely, link, toofar) \
757 | ((toofar) ? 1 : 0) \
759 | ((likely) ? 4 : 0) \
760 | ((uncond) ? 8 : 0)))
761 #define RELAX_BRANCH_P(i) (((i) & 0xf0000000) == 0xc0000000)
762 #define RELAX_BRANCH_UNCOND(i) (((i) & 8) != 0)
763 #define RELAX_BRANCH_LIKELY(i) (((i) & 4) != 0)
764 #define RELAX_BRANCH_LINK(i) (((i) & 2) != 0)
765 #define RELAX_BRANCH_TOOFAR(i) (((i) & 1) != 0)
767 /* For mips16 code, we use an entirely different form of relaxation.
768 mips16 supports two versions of most instructions which take
769 immediate values: a small one which takes some small value, and a
770 larger one which takes a 16 bit value. Since branches also follow
771 this pattern, relaxing these values is required.
773 We can assemble both mips16 and normal MIPS code in a single
774 object. Therefore, we need to support this type of relaxation at
775 the same time that we support the relaxation described above. We
776 use the high bit of the subtype field to distinguish these cases.
778 The information we store for this type of relaxation is the
779 argument code found in the opcode file for this relocation, whether
780 the user explicitly requested a small or extended form, and whether
781 the relocation is in a jump or jal delay slot. That tells us the
782 size of the value, and how it should be stored. We also store
783 whether the fragment is considered to be extended or not. We also
784 store whether this is known to be a branch to a different section,
785 whether we have tried to relax this frag yet, and whether we have
786 ever extended a PC relative fragment because of a shift count. */
787 #define RELAX_MIPS16_ENCODE(type, small, ext, dslot, jal_dslot) \
790 | ((small) ? 0x100 : 0) \
791 | ((ext) ? 0x200 : 0) \
792 | ((dslot) ? 0x400 : 0) \
793 | ((jal_dslot) ? 0x800 : 0))
794 #define RELAX_MIPS16_P(i) (((i) & 0xc0000000) == 0x80000000)
795 #define RELAX_MIPS16_TYPE(i) ((i) & 0xff)
796 #define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x100) != 0)
797 #define RELAX_MIPS16_USER_EXT(i) (((i) & 0x200) != 0)
798 #define RELAX_MIPS16_DSLOT(i) (((i) & 0x400) != 0)
799 #define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x800) != 0)
800 #define RELAX_MIPS16_EXTENDED(i) (((i) & 0x1000) != 0)
801 #define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x1000)
802 #define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) &~ 0x1000)
803 #define RELAX_MIPS16_LONG_BRANCH(i) (((i) & 0x2000) != 0)
804 #define RELAX_MIPS16_MARK_LONG_BRANCH(i) ((i) | 0x2000)
805 #define RELAX_MIPS16_CLEAR_LONG_BRANCH(i) ((i) &~ 0x2000)
807 /* Is the given value a sign-extended 32-bit value? */
808 #define IS_SEXT_32BIT_NUM(x) \
809 (((x) &~ (offsetT) 0x7fffffff) == 0 \
810 || (((x) &~ (offsetT) 0x7fffffff) == ~ (offsetT) 0x7fffffff))
812 /* Is the given value a sign-extended 16-bit value? */
813 #define IS_SEXT_16BIT_NUM(x) \
814 (((x) &~ (offsetT) 0x7fff) == 0 \
815 || (((x) &~ (offsetT) 0x7fff) == ~ (offsetT) 0x7fff))
818 /* Global variables used when generating relaxable macros. See the
819 comment above RELAX_ENCODE for more details about how relaxation
822 /* 0 if we're not emitting a relaxable macro.
823 1 if we're emitting the first of the two relaxation alternatives.
824 2 if we're emitting the second alternative. */
827 /* The first relaxable fixup in the current frag. (In other words,
828 the first fixup that refers to relaxable code.) */
831 /* sizes[0] says how many bytes of the first alternative are stored in
832 the current frag. Likewise sizes[1] for the second alternative. */
833 unsigned int sizes
[2];
835 /* The symbol on which the choice of sequence depends. */
839 /* Global variables used to decide whether a macro needs a warning. */
841 /* True if the macro is in a branch delay slot. */
842 bfd_boolean delay_slot_p
;
844 /* For relaxable macros, sizes[0] is the length of the first alternative
845 in bytes and sizes[1] is the length of the second alternative.
846 For non-relaxable macros, both elements give the length of the
848 unsigned int sizes
[2];
850 /* The first variant frag for this macro. */
852 } mips_macro_warning
;
854 /* Prototypes for static functions. */
856 #define internalError() \
857 as_fatal (_("internal Error, line %d, %s"), __LINE__, __FILE__)
859 enum mips_regclass
{ MIPS_GR_REG
, MIPS_FP_REG
, MIPS16_REG
};
861 static void append_insn
862 (struct mips_cl_insn
*ip
, expressionS
*p
, bfd_reloc_code_real_type
*r
);
863 static void mips_no_prev_insn (int);
864 static void mips16_macro_build
865 (expressionS
*, const char *, const char *, va_list);
866 static void load_register (int, expressionS
*, int);
867 static void macro_start (void);
868 static void macro_end (void);
869 static void macro (struct mips_cl_insn
* ip
);
870 static void mips16_macro (struct mips_cl_insn
* ip
);
871 #ifdef LOSING_COMPILER
872 static void macro2 (struct mips_cl_insn
* ip
);
874 static void mips_ip (char *str
, struct mips_cl_insn
* ip
);
875 static void mips16_ip (char *str
, struct mips_cl_insn
* ip
);
876 static void mips16_immed
877 (char *, unsigned int, int, offsetT
, bfd_boolean
, bfd_boolean
, bfd_boolean
,
878 unsigned long *, bfd_boolean
*, unsigned short *);
879 static size_t my_getSmallExpression
880 (expressionS
*, bfd_reloc_code_real_type
*, char *);
881 static void my_getExpression (expressionS
*, char *);
882 static void s_align (int);
883 static void s_change_sec (int);
884 static void s_change_section (int);
885 static void s_cons (int);
886 static void s_float_cons (int);
887 static void s_mips_globl (int);
888 static void s_option (int);
889 static void s_mipsset (int);
890 static void s_abicalls (int);
891 static void s_cpload (int);
892 static void s_cpsetup (int);
893 static void s_cplocal (int);
894 static void s_cprestore (int);
895 static void s_cpreturn (int);
896 static void s_gpvalue (int);
897 static void s_gpword (int);
898 static void s_gpdword (int);
899 static void s_cpadd (int);
900 static void s_insn (int);
901 static void md_obj_begin (void);
902 static void md_obj_end (void);
903 static void s_mips_ent (int);
904 static void s_mips_end (int);
905 static void s_mips_frame (int);
906 static void s_mips_mask (int reg_type
);
907 static void s_mips_stab (int);
908 static void s_mips_weakext (int);
909 static void s_mips_file (int);
910 static void s_mips_loc (int);
911 static bfd_boolean
pic_need_relax (symbolS
*, asection
*);
912 static int relaxed_branch_length (fragS
*, asection
*, int);
913 static int validate_mips_insn (const struct mips_opcode
*);
915 /* Table and functions used to map between CPU/ISA names, and
916 ISA levels, and CPU numbers. */
920 const char *name
; /* CPU or ISA name. */
921 int is_isa
; /* Is this an ISA? (If 0, a CPU.) */
922 int isa
; /* ISA level. */
923 int cpu
; /* CPU number (default CPU if ISA). */
926 static const struct mips_cpu_info
*mips_parse_cpu (const char *, const char *);
927 static const struct mips_cpu_info
*mips_cpu_info_from_isa (int);
928 static const struct mips_cpu_info
*mips_cpu_info_from_arch (int);
932 The following pseudo-ops from the Kane and Heinrich MIPS book
933 should be defined here, but are currently unsupported: .alias,
934 .galive, .gjaldef, .gjrlive, .livereg, .noalias.
936 The following pseudo-ops from the Kane and Heinrich MIPS book are
937 specific to the type of debugging information being generated, and
938 should be defined by the object format: .aent, .begin, .bend,
939 .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp,
942 The following pseudo-ops from the Kane and Heinrich MIPS book are
943 not MIPS CPU specific, but are also not specific to the object file
944 format. This file is probably the best place to define them, but
945 they are not currently supported: .asm0, .endr, .lab, .repeat,
948 static const pseudo_typeS mips_pseudo_table
[] =
950 /* MIPS specific pseudo-ops. */
951 {"option", s_option
, 0},
952 {"set", s_mipsset
, 0},
953 {"rdata", s_change_sec
, 'r'},
954 {"sdata", s_change_sec
, 's'},
955 {"livereg", s_ignore
, 0},
956 {"abicalls", s_abicalls
, 0},
957 {"cpload", s_cpload
, 0},
958 {"cpsetup", s_cpsetup
, 0},
959 {"cplocal", s_cplocal
, 0},
960 {"cprestore", s_cprestore
, 0},
961 {"cpreturn", s_cpreturn
, 0},
962 {"gpvalue", s_gpvalue
, 0},
963 {"gpword", s_gpword
, 0},
964 {"gpdword", s_gpdword
, 0},
965 {"cpadd", s_cpadd
, 0},
968 /* Relatively generic pseudo-ops that happen to be used on MIPS
970 {"asciiz", stringer
, 1},
971 {"bss", s_change_sec
, 'b'},
974 {"dword", s_cons
, 3},
975 {"weakext", s_mips_weakext
, 0},
977 /* These pseudo-ops are defined in read.c, but must be overridden
978 here for one reason or another. */
979 {"align", s_align
, 0},
981 {"data", s_change_sec
, 'd'},
982 {"double", s_float_cons
, 'd'},
983 {"float", s_float_cons
, 'f'},
984 {"globl", s_mips_globl
, 0},
985 {"global", s_mips_globl
, 0},
986 {"hword", s_cons
, 1},
991 {"section", s_change_section
, 0},
992 {"short", s_cons
, 1},
993 {"single", s_float_cons
, 'f'},
994 {"stabn", s_mips_stab
, 'n'},
995 {"text", s_change_sec
, 't'},
998 { "extern", ecoff_directive_extern
, 0},
1003 static const pseudo_typeS mips_nonecoff_pseudo_table
[] =
1005 /* These pseudo-ops should be defined by the object file format.
1006 However, a.out doesn't support them, so we have versions here. */
1007 {"aent", s_mips_ent
, 1},
1008 {"bgnb", s_ignore
, 0},
1009 {"end", s_mips_end
, 0},
1010 {"endb", s_ignore
, 0},
1011 {"ent", s_mips_ent
, 0},
1012 {"file", s_mips_file
, 0},
1013 {"fmask", s_mips_mask
, 'F'},
1014 {"frame", s_mips_frame
, 0},
1015 {"loc", s_mips_loc
, 0},
1016 {"mask", s_mips_mask
, 'R'},
1017 {"verstamp", s_ignore
, 0},
1021 extern void pop_insert (const pseudo_typeS
*);
1024 mips_pop_insert (void)
1026 pop_insert (mips_pseudo_table
);
1027 if (! ECOFF_DEBUGGING
)
1028 pop_insert (mips_nonecoff_pseudo_table
);
1031 /* Symbols labelling the current insn. */
1033 struct insn_label_list
1035 struct insn_label_list
*next
;
1039 static struct insn_label_list
*insn_labels
;
1040 static struct insn_label_list
*free_insn_labels
;
1042 static void mips_clear_insn_labels (void);
1045 mips_clear_insn_labels (void)
1047 register struct insn_label_list
**pl
;
1049 for (pl
= &free_insn_labels
; *pl
!= NULL
; pl
= &(*pl
)->next
)
1055 static char *expr_end
;
1057 /* Expressions which appear in instructions. These are set by
1060 static expressionS imm_expr
;
1061 static expressionS imm2_expr
;
1062 static expressionS offset_expr
;
1064 /* Relocs associated with imm_expr and offset_expr. */
1066 static bfd_reloc_code_real_type imm_reloc
[3]
1067 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
1068 static bfd_reloc_code_real_type offset_reloc
[3]
1069 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
1071 /* These are set by mips16_ip if an explicit extension is used. */
1073 static bfd_boolean mips16_small
, mips16_ext
;
1076 /* The pdr segment for per procedure frame/regmask info. Not used for
1079 static segT pdr_seg
;
1082 /* The default target format to use. */
1085 mips_target_format (void)
1087 switch (OUTPUT_FLAVOR
)
1089 case bfd_target_ecoff_flavour
:
1090 return target_big_endian
? "ecoff-bigmips" : ECOFF_LITTLE_FORMAT
;
1091 case bfd_target_coff_flavour
:
1093 case bfd_target_elf_flavour
:
1095 /* This is traditional mips. */
1096 return (target_big_endian
1097 ? (HAVE_64BIT_OBJECTS
1098 ? "elf64-tradbigmips"
1100 ? "elf32-ntradbigmips" : "elf32-tradbigmips"))
1101 : (HAVE_64BIT_OBJECTS
1102 ? "elf64-tradlittlemips"
1104 ? "elf32-ntradlittlemips" : "elf32-tradlittlemips")));
1106 return (target_big_endian
1107 ? (HAVE_64BIT_OBJECTS
1110 ? "elf32-nbigmips" : "elf32-bigmips"))
1111 : (HAVE_64BIT_OBJECTS
1112 ? "elf64-littlemips"
1114 ? "elf32-nlittlemips" : "elf32-littlemips")));
1122 /* This function is called once, at assembler startup time. It should
1123 set up all the tables, etc. that the MD part of the assembler will need. */
1128 register const char *retval
= NULL
;
1132 if (! bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, file_mips_arch
))
1133 as_warn (_("Could not set architecture and machine"));
1135 op_hash
= hash_new ();
1137 for (i
= 0; i
< NUMOPCODES
;)
1139 const char *name
= mips_opcodes
[i
].name
;
1141 retval
= hash_insert (op_hash
, name
, (void *) &mips_opcodes
[i
]);
1144 fprintf (stderr
, _("internal error: can't hash `%s': %s\n"),
1145 mips_opcodes
[i
].name
, retval
);
1146 /* Probably a memory allocation problem? Give up now. */
1147 as_fatal (_("Broken assembler. No assembly attempted."));
1151 if (mips_opcodes
[i
].pinfo
!= INSN_MACRO
)
1153 if (!validate_mips_insn (&mips_opcodes
[i
]))
1158 while ((i
< NUMOPCODES
) && !strcmp (mips_opcodes
[i
].name
, name
));
1161 mips16_op_hash
= hash_new ();
1164 while (i
< bfd_mips16_num_opcodes
)
1166 const char *name
= mips16_opcodes
[i
].name
;
1168 retval
= hash_insert (mips16_op_hash
, name
, (void *) &mips16_opcodes
[i
]);
1170 as_fatal (_("internal: can't hash `%s': %s"),
1171 mips16_opcodes
[i
].name
, retval
);
1174 if (mips16_opcodes
[i
].pinfo
!= INSN_MACRO
1175 && ((mips16_opcodes
[i
].match
& mips16_opcodes
[i
].mask
)
1176 != mips16_opcodes
[i
].match
))
1178 fprintf (stderr
, _("internal error: bad mips16 opcode: %s %s\n"),
1179 mips16_opcodes
[i
].name
, mips16_opcodes
[i
].args
);
1184 while (i
< bfd_mips16_num_opcodes
1185 && strcmp (mips16_opcodes
[i
].name
, name
) == 0);
1189 as_fatal (_("Broken assembler. No assembly attempted."));
1191 /* We add all the general register names to the symbol table. This
1192 helps us detect invalid uses of them. */
1193 for (i
= 0; i
< 32; i
++)
1197 sprintf (buf
, "$%d", i
);
1198 symbol_table_insert (symbol_new (buf
, reg_section
, i
,
1199 &zero_address_frag
));
1201 symbol_table_insert (symbol_new ("$ra", reg_section
, RA
,
1202 &zero_address_frag
));
1203 symbol_table_insert (symbol_new ("$fp", reg_section
, FP
,
1204 &zero_address_frag
));
1205 symbol_table_insert (symbol_new ("$sp", reg_section
, SP
,
1206 &zero_address_frag
));
1207 symbol_table_insert (symbol_new ("$gp", reg_section
, GP
,
1208 &zero_address_frag
));
1209 symbol_table_insert (symbol_new ("$at", reg_section
, AT
,
1210 &zero_address_frag
));
1211 symbol_table_insert (symbol_new ("$kt0", reg_section
, KT0
,
1212 &zero_address_frag
));
1213 symbol_table_insert (symbol_new ("$kt1", reg_section
, KT1
,
1214 &zero_address_frag
));
1215 symbol_table_insert (symbol_new ("$zero", reg_section
, ZERO
,
1216 &zero_address_frag
));
1217 symbol_table_insert (symbol_new ("$pc", reg_section
, -1,
1218 &zero_address_frag
));
1220 /* If we don't add these register names to the symbol table, they
1221 may end up being added as regular symbols by operand(), and then
1222 make it to the object file as undefined in case they're not
1223 regarded as local symbols. They're local in o32, since `$' is a
1224 local symbol prefix, but not in n32 or n64. */
1225 for (i
= 0; i
< 8; i
++)
1229 sprintf (buf
, "$fcc%i", i
);
1230 symbol_table_insert (symbol_new (buf
, reg_section
, -1,
1231 &zero_address_frag
));
1234 mips_no_prev_insn (FALSE
);
1237 mips_cprmask
[0] = 0;
1238 mips_cprmask
[1] = 0;
1239 mips_cprmask
[2] = 0;
1240 mips_cprmask
[3] = 0;
1242 /* set the default alignment for the text section (2**2) */
1243 record_alignment (text_section
, 2);
1245 bfd_set_gp_size (stdoutput
, g_switch_value
);
1247 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
1249 /* On a native system, sections must be aligned to 16 byte
1250 boundaries. When configured for an embedded ELF target, we
1252 if (strcmp (TARGET_OS
, "elf") != 0)
1254 (void) bfd_set_section_alignment (stdoutput
, text_section
, 4);
1255 (void) bfd_set_section_alignment (stdoutput
, data_section
, 4);
1256 (void) bfd_set_section_alignment (stdoutput
, bss_section
, 4);
1259 /* Create a .reginfo section for register masks and a .mdebug
1260 section for debugging information. */
1268 subseg
= now_subseg
;
1270 /* The ABI says this section should be loaded so that the
1271 running program can access it. However, we don't load it
1272 if we are configured for an embedded target */
1273 flags
= SEC_READONLY
| SEC_DATA
;
1274 if (strcmp (TARGET_OS
, "elf") != 0)
1275 flags
|= SEC_ALLOC
| SEC_LOAD
;
1277 if (mips_abi
!= N64_ABI
)
1279 sec
= subseg_new (".reginfo", (subsegT
) 0);
1281 bfd_set_section_flags (stdoutput
, sec
, flags
);
1282 bfd_set_section_alignment (stdoutput
, sec
, HAVE_NEWABI
? 3 : 2);
1285 mips_regmask_frag
= frag_more (sizeof (Elf32_External_RegInfo
));
1290 /* The 64-bit ABI uses a .MIPS.options section rather than
1291 .reginfo section. */
1292 sec
= subseg_new (".MIPS.options", (subsegT
) 0);
1293 bfd_set_section_flags (stdoutput
, sec
, flags
);
1294 bfd_set_section_alignment (stdoutput
, sec
, 3);
1297 /* Set up the option header. */
1299 Elf_Internal_Options opthdr
;
1302 opthdr
.kind
= ODK_REGINFO
;
1303 opthdr
.size
= (sizeof (Elf_External_Options
)
1304 + sizeof (Elf64_External_RegInfo
));
1307 f
= frag_more (sizeof (Elf_External_Options
));
1308 bfd_mips_elf_swap_options_out (stdoutput
, &opthdr
,
1309 (Elf_External_Options
*) f
);
1311 mips_regmask_frag
= frag_more (sizeof (Elf64_External_RegInfo
));
1316 if (ECOFF_DEBUGGING
)
1318 sec
= subseg_new (".mdebug", (subsegT
) 0);
1319 (void) bfd_set_section_flags (stdoutput
, sec
,
1320 SEC_HAS_CONTENTS
| SEC_READONLY
);
1321 (void) bfd_set_section_alignment (stdoutput
, sec
, 2);
1324 else if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
&& mips_flag_pdr
)
1326 pdr_seg
= subseg_new (".pdr", (subsegT
) 0);
1327 (void) bfd_set_section_flags (stdoutput
, pdr_seg
,
1328 SEC_READONLY
| SEC_RELOC
1330 (void) bfd_set_section_alignment (stdoutput
, pdr_seg
, 2);
1334 subseg_set (seg
, subseg
);
1338 if (! ECOFF_DEBUGGING
)
1345 if (! ECOFF_DEBUGGING
)
1350 md_assemble (char *str
)
1352 struct mips_cl_insn insn
;
1353 bfd_reloc_code_real_type unused_reloc
[3]
1354 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
1356 imm_expr
.X_op
= O_absent
;
1357 imm2_expr
.X_op
= O_absent
;
1358 offset_expr
.X_op
= O_absent
;
1359 imm_reloc
[0] = BFD_RELOC_UNUSED
;
1360 imm_reloc
[1] = BFD_RELOC_UNUSED
;
1361 imm_reloc
[2] = BFD_RELOC_UNUSED
;
1362 offset_reloc
[0] = BFD_RELOC_UNUSED
;
1363 offset_reloc
[1] = BFD_RELOC_UNUSED
;
1364 offset_reloc
[2] = BFD_RELOC_UNUSED
;
1366 if (mips_opts
.mips16
)
1367 mips16_ip (str
, &insn
);
1370 mips_ip (str
, &insn
);
1371 DBG ((_("returned from mips_ip(%s) insn_opcode = 0x%x\n"),
1372 str
, insn
.insn_opcode
));
1377 as_bad ("%s `%s'", insn_error
, str
);
1381 if (insn
.insn_mo
->pinfo
== INSN_MACRO
)
1384 if (mips_opts
.mips16
)
1385 mips16_macro (&insn
);
1392 if (imm_expr
.X_op
!= O_absent
)
1393 append_insn (&insn
, &imm_expr
, imm_reloc
);
1394 else if (offset_expr
.X_op
!= O_absent
)
1395 append_insn (&insn
, &offset_expr
, offset_reloc
);
1397 append_insn (&insn
, NULL
, unused_reloc
);
1401 /* Return true if the given relocation might need a matching %lo().
1402 Note that R_MIPS_GOT16 relocations only need a matching %lo() when
1403 applied to local symbols. */
1405 static inline bfd_boolean
1406 reloc_needs_lo_p (bfd_reloc_code_real_type reloc
)
1408 return (HAVE_IN_PLACE_ADDENDS
1409 && (reloc
== BFD_RELOC_HI16_S
1410 || reloc
== BFD_RELOC_MIPS_GOT16
1411 || reloc
== BFD_RELOC_MIPS16_HI16_S
));
1414 /* Return true if the given fixup is followed by a matching R_MIPS_LO16
1417 static inline bfd_boolean
1418 fixup_has_matching_lo_p (fixS
*fixp
)
1420 return (fixp
->fx_next
!= NULL
1421 && (fixp
->fx_next
->fx_r_type
== BFD_RELOC_LO16
1422 || fixp
->fx_next
->fx_r_type
== BFD_RELOC_MIPS16_LO16
)
1423 && fixp
->fx_addsy
== fixp
->fx_next
->fx_addsy
1424 && fixp
->fx_offset
== fixp
->fx_next
->fx_offset
);
1427 /* See whether instruction IP reads register REG. CLASS is the type
1431 insn_uses_reg (struct mips_cl_insn
*ip
, unsigned int reg
,
1432 enum mips_regclass
class)
1434 if (class == MIPS16_REG
)
1436 assert (mips_opts
.mips16
);
1437 reg
= mips16_to_32_reg_map
[reg
];
1438 class = MIPS_GR_REG
;
1441 /* Don't report on general register ZERO, since it never changes. */
1442 if (class == MIPS_GR_REG
&& reg
== ZERO
)
1445 if (class == MIPS_FP_REG
)
1447 assert (! mips_opts
.mips16
);
1448 /* If we are called with either $f0 or $f1, we must check $f0.
1449 This is not optimal, because it will introduce an unnecessary
1450 NOP between "lwc1 $f0" and "swc1 $f1". To fix this we would
1451 need to distinguish reading both $f0 and $f1 or just one of
1452 them. Note that we don't have to check the other way,
1453 because there is no instruction that sets both $f0 and $f1
1454 and requires a delay. */
1455 if ((ip
->insn_mo
->pinfo
& INSN_READ_FPR_S
)
1456 && ((((ip
->insn_opcode
>> OP_SH_FS
) & OP_MASK_FS
) &~(unsigned)1)
1457 == (reg
&~ (unsigned) 1)))
1459 if ((ip
->insn_mo
->pinfo
& INSN_READ_FPR_T
)
1460 && ((((ip
->insn_opcode
>> OP_SH_FT
) & OP_MASK_FT
) &~(unsigned)1)
1461 == (reg
&~ (unsigned) 1)))
1464 else if (! mips_opts
.mips16
)
1466 if ((ip
->insn_mo
->pinfo
& INSN_READ_GPR_S
)
1467 && ((ip
->insn_opcode
>> OP_SH_RS
) & OP_MASK_RS
) == reg
)
1469 if ((ip
->insn_mo
->pinfo
& INSN_READ_GPR_T
)
1470 && ((ip
->insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
) == reg
)
1475 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_X
)
1476 && (mips16_to_32_reg_map
[((ip
->insn_opcode
>> MIPS16OP_SH_RX
)
1477 & MIPS16OP_MASK_RX
)]
1480 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_Y
)
1481 && (mips16_to_32_reg_map
[((ip
->insn_opcode
>> MIPS16OP_SH_RY
)
1482 & MIPS16OP_MASK_RY
)]
1485 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_Z
)
1486 && (mips16_to_32_reg_map
[((ip
->insn_opcode
>> MIPS16OP_SH_MOVE32Z
)
1487 & MIPS16OP_MASK_MOVE32Z
)]
1490 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_T
) && reg
== TREG
)
1492 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_SP
) && reg
== SP
)
1494 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_31
) && reg
== RA
)
1496 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_GPR_X
)
1497 && ((ip
->insn_opcode
>> MIPS16OP_SH_REGR32
)
1498 & MIPS16OP_MASK_REGR32
) == reg
)
1505 /* This function returns true if modifying a register requires a
1509 reg_needs_delay (unsigned int reg
)
1511 unsigned long prev_pinfo
;
1513 prev_pinfo
= prev_insn
.insn_mo
->pinfo
;
1514 if (! mips_opts
.noreorder
1515 && (((prev_pinfo
& INSN_LOAD_MEMORY_DELAY
)
1516 && ! gpr_interlocks
)
1517 || ((prev_pinfo
& INSN_LOAD_COPROC_DELAY
)
1518 && ! cop_interlocks
)))
1520 /* A load from a coprocessor or from memory. All load delays
1521 delay the use of general register rt for one instruction. */
1522 /* Itbl support may require additional care here. */
1523 know (prev_pinfo
& INSN_WRITE_GPR_T
);
1524 if (reg
== ((prev_insn
.insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
))
1531 /* Mark instruction labels in mips16 mode. This permits the linker to
1532 handle them specially, such as generating jalx instructions when
1533 needed. We also make them odd for the duration of the assembly, in
1534 order to generate the right sort of code. We will make them even
1535 in the adjust_symtab routine, while leaving them marked. This is
1536 convenient for the debugger and the disassembler. The linker knows
1537 to make them odd again. */
1540 mips16_mark_labels (void)
1542 if (mips_opts
.mips16
)
1544 struct insn_label_list
*l
;
1547 for (l
= insn_labels
; l
!= NULL
; l
= l
->next
)
1550 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
1551 S_SET_OTHER (l
->label
, STO_MIPS16
);
1553 val
= S_GET_VALUE (l
->label
);
1555 S_SET_VALUE (l
->label
, val
+ 1);
1560 /* End the current frag. Make it a variant frag and record the
1564 relax_close_frag (void)
1566 mips_macro_warning
.first_frag
= frag_now
;
1567 frag_var (rs_machine_dependent
, 0, 0,
1568 RELAX_ENCODE (mips_relax
.sizes
[0], mips_relax
.sizes
[1]),
1569 mips_relax
.symbol
, 0, (char *) mips_relax
.first_fixup
);
1571 memset (&mips_relax
.sizes
, 0, sizeof (mips_relax
.sizes
));
1572 mips_relax
.first_fixup
= 0;
1575 /* Start a new relaxation sequence whose expansion depends on SYMBOL.
1576 See the comment above RELAX_ENCODE for more details. */
1579 relax_start (symbolS
*symbol
)
1581 assert (mips_relax
.sequence
== 0);
1582 mips_relax
.sequence
= 1;
1583 mips_relax
.symbol
= symbol
;
1586 /* Start generating the second version of a relaxable sequence.
1587 See the comment above RELAX_ENCODE for more details. */
1592 assert (mips_relax
.sequence
== 1);
1593 mips_relax
.sequence
= 2;
1596 /* End the current relaxable sequence. */
1601 assert (mips_relax
.sequence
== 2);
1602 relax_close_frag ();
1603 mips_relax
.sequence
= 0;
1606 /* Output an instruction. IP is the instruction information.
1607 ADDRESS_EXPR is an operand of the instruction to be used with
1611 append_insn (struct mips_cl_insn
*ip
, expressionS
*address_expr
,
1612 bfd_reloc_code_real_type
*reloc_type
)
1614 register unsigned long prev_pinfo
, pinfo
;
1618 relax_stateT prev_insn_frag_type
= 0;
1619 bfd_boolean relaxed_branch
= FALSE
;
1620 bfd_boolean force_new_frag
= FALSE
;
1622 /* Mark instruction labels in mips16 mode. */
1623 mips16_mark_labels ();
1625 prev_pinfo
= prev_insn
.insn_mo
->pinfo
;
1626 pinfo
= ip
->insn_mo
->pinfo
;
1628 if (mips_relax
.sequence
!= 2
1629 && (!mips_opts
.noreorder
|| prev_nop_frag
!= NULL
))
1633 /* If the previous insn required any delay slots, see if we need
1634 to insert a NOP or two. There are eight kinds of possible
1635 hazards, of which an instruction can have at most one type.
1636 (1) a load from memory delay
1637 (2) a load from a coprocessor delay
1638 (3) an unconditional branch delay
1639 (4) a conditional branch delay
1640 (5) a move to coprocessor register delay
1641 (6) a load coprocessor register from memory delay
1642 (7) a coprocessor condition code delay
1643 (8) a HI/LO special register delay
1645 There are a lot of optimizations we could do that we don't.
1646 In particular, we do not, in general, reorder instructions.
1647 If you use gcc with optimization, it will reorder
1648 instructions and generally do much more optimization then we
1649 do here; repeating all that work in the assembler would only
1650 benefit hand written assembly code, and does not seem worth
1653 /* This is how a NOP is emitted. */
1654 #define emit_nop() \
1656 ? md_number_to_chars (frag_more (2), 0x6500, 2) \
1657 : md_number_to_chars (frag_more (4), 0, 4))
1659 /* The previous insn might require a delay slot, depending upon
1660 the contents of the current insn. */
1661 if (! mips_opts
.mips16
1662 && (((prev_pinfo
& INSN_LOAD_MEMORY_DELAY
)
1663 && ! gpr_interlocks
)
1664 || ((prev_pinfo
& INSN_LOAD_COPROC_DELAY
)
1665 && ! cop_interlocks
)))
1667 /* A load from a coprocessor or from memory. All load
1668 delays delay the use of general register rt for one
1670 /* Itbl support may require additional care here. */
1671 know (prev_pinfo
& INSN_WRITE_GPR_T
);
1672 if (mips_optimize
== 0
1673 || insn_uses_reg (ip
,
1674 ((prev_insn
.insn_opcode
>> OP_SH_RT
)
1679 else if (! mips_opts
.mips16
1680 && (((prev_pinfo
& INSN_COPROC_MOVE_DELAY
)
1681 && ! cop_interlocks
)
1682 || ((prev_pinfo
& INSN_COPROC_MEMORY_DELAY
)
1683 && ! cop_mem_interlocks
)))
1685 /* A generic coprocessor delay. The previous instruction
1686 modified a coprocessor general or control register. If
1687 it modified a control register, we need to avoid any
1688 coprocessor instruction (this is probably not always
1689 required, but it sometimes is). If it modified a general
1690 register, we avoid using that register.
1692 This case is not handled very well. There is no special
1693 knowledge of CP0 handling, and the coprocessors other
1694 than the floating point unit are not distinguished at
1696 /* Itbl support may require additional care here. FIXME!
1697 Need to modify this to include knowledge about
1698 user specified delays! */
1699 if (prev_pinfo
& INSN_WRITE_FPR_T
)
1701 if (mips_optimize
== 0
1702 || insn_uses_reg (ip
,
1703 ((prev_insn
.insn_opcode
>> OP_SH_FT
)
1708 else if (prev_pinfo
& INSN_WRITE_FPR_S
)
1710 if (mips_optimize
== 0
1711 || insn_uses_reg (ip
,
1712 ((prev_insn
.insn_opcode
>> OP_SH_FS
)
1719 /* We don't know exactly what the previous instruction
1720 does. If the current instruction uses a coprocessor
1721 register, we must insert a NOP. If previous
1722 instruction may set the condition codes, and the
1723 current instruction uses them, we must insert two
1725 /* Itbl support may require additional care here. */
1726 if (mips_optimize
== 0
1727 || ((prev_pinfo
& INSN_WRITE_COND_CODE
)
1728 && (pinfo
& INSN_READ_COND_CODE
)))
1730 else if (pinfo
& INSN_COP
)
1734 else if (! mips_opts
.mips16
1735 && (prev_pinfo
& INSN_WRITE_COND_CODE
)
1736 && ! cop_interlocks
)
1738 /* The previous instruction sets the coprocessor condition
1739 codes, but does not require a general coprocessor delay
1740 (this means it is a floating point comparison
1741 instruction). If this instruction uses the condition
1742 codes, we need to insert a single NOP. */
1743 /* Itbl support may require additional care here. */
1744 if (mips_optimize
== 0
1745 || (pinfo
& INSN_READ_COND_CODE
))
1749 /* If we're fixing up mfhi/mflo for the r7000 and the
1750 previous insn was an mfhi/mflo and the current insn
1751 reads the register that the mfhi/mflo wrote to, then
1754 else if (mips_7000_hilo_fix
1755 && MF_HILO_INSN (prev_pinfo
)
1756 && insn_uses_reg (ip
, ((prev_insn
.insn_opcode
>> OP_SH_RD
)
1763 /* If we're fixing up mfhi/mflo for the r7000 and the
1764 2nd previous insn was an mfhi/mflo and the current insn
1765 reads the register that the mfhi/mflo wrote to, then
1768 else if (mips_7000_hilo_fix
1769 && MF_HILO_INSN (prev_prev_insn
.insn_opcode
)
1770 && insn_uses_reg (ip
, ((prev_prev_insn
.insn_opcode
>> OP_SH_RD
)
1778 else if (prev_pinfo
& INSN_READ_LO
)
1780 /* The previous instruction reads the LO register; if the
1781 current instruction writes to the LO register, we must
1782 insert two NOPS. Some newer processors have interlocks.
1783 Also the tx39's multiply instructions can be executed
1784 immediately after a read from HI/LO (without the delay),
1785 though the tx39's divide insns still do require the
1787 if (! (hilo_interlocks
1788 || (mips_opts
.arch
== CPU_R3900
&& (pinfo
& INSN_MULT
)))
1789 && (mips_optimize
== 0
1790 || (pinfo
& INSN_WRITE_LO
)))
1792 /* Most mips16 branch insns don't have a delay slot.
1793 If a read from LO is immediately followed by a branch
1794 to a write to LO we have a read followed by a write
1795 less than 2 insns away. We assume the target of
1796 a branch might be a write to LO, and insert a nop
1797 between a read and an immediately following branch. */
1798 else if (mips_opts
.mips16
1799 && (mips_optimize
== 0
1800 || (pinfo
& MIPS16_INSN_BRANCH
)))
1803 else if (prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
1805 /* The previous instruction reads the HI register; if the
1806 current instruction writes to the HI register, we must
1807 insert a NOP. Some newer processors have interlocks.
1808 Also the note tx39's multiply above. */
1809 if (! (hilo_interlocks
1810 || (mips_opts
.arch
== CPU_R3900
&& (pinfo
& INSN_MULT
)))
1811 && (mips_optimize
== 0
1812 || (pinfo
& INSN_WRITE_HI
)))
1814 /* Most mips16 branch insns don't have a delay slot.
1815 If a read from HI is immediately followed by a branch
1816 to a write to HI we have a read followed by a write
1817 less than 2 insns away. We assume the target of
1818 a branch might be a write to HI, and insert a nop
1819 between a read and an immediately following branch. */
1820 else if (mips_opts
.mips16
1821 && (mips_optimize
== 0
1822 || (pinfo
& MIPS16_INSN_BRANCH
)))
1826 /* If the previous instruction was in a noreorder section, then
1827 we don't want to insert the nop after all. */
1828 /* Itbl support may require additional care here. */
1829 if (prev_insn_unreordered
)
1832 /* There are two cases which require two intervening
1833 instructions: 1) setting the condition codes using a move to
1834 coprocessor instruction which requires a general coprocessor
1835 delay and then reading the condition codes 2) reading the HI
1836 or LO register and then writing to it (except on processors
1837 which have interlocks). If we are not already emitting a NOP
1838 instruction, we must check for these cases compared to the
1839 instruction previous to the previous instruction. */
1840 if ((! mips_opts
.mips16
1841 && (prev_prev_insn
.insn_mo
->pinfo
& INSN_COPROC_MOVE_DELAY
)
1842 && (prev_prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
)
1843 && (pinfo
& INSN_READ_COND_CODE
)
1844 && ! cop_interlocks
)
1845 || ((prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
)
1846 && (pinfo
& INSN_WRITE_LO
)
1847 && ! (hilo_interlocks
1848 || (mips_opts
.arch
== CPU_R3900
&& (pinfo
& INSN_MULT
))))
1849 || ((prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
1850 && (pinfo
& INSN_WRITE_HI
)
1851 && ! (hilo_interlocks
1852 || (mips_opts
.arch
== CPU_R3900
&& (pinfo
& INSN_MULT
)))))
1857 if (prev_prev_insn_unreordered
)
1860 if (prev_prev_nop
&& nops
== 0)
1863 if (mips_fix_vr4120
&& prev_insn
.insn_mo
->name
)
1865 /* We're out of bits in pinfo, so we must resort to string
1866 ops here. Shortcuts are selected based on opcodes being
1867 limited to the VR4120 instruction set. */
1869 const char *pn
= prev_insn
.insn_mo
->name
;
1870 const char *tn
= ip
->insn_mo
->name
;
1871 if (strncmp (pn
, "macc", 4) == 0
1872 || strncmp (pn
, "dmacc", 5) == 0)
1874 /* Errata 21 - [D]DIV[U] after [D]MACC */
1875 if (strstr (tn
, "div"))
1878 /* VR4181A errata MD(1): "If a MULT, MULTU, DMULT or DMULTU
1879 instruction is executed immediately after a MACC or
1880 DMACC instruction, the result of [either instruction]
1882 if (strncmp (tn
, "mult", 4) == 0
1883 || strncmp (tn
, "dmult", 5) == 0)
1886 /* Errata 23 - Continuous DMULT[U]/DMACC instructions.
1887 Applies on top of VR4181A MD(1) errata. */
1888 if (pn
[0] == 'd' && strncmp (tn
, "dmacc", 5) == 0)
1891 /* Errata 24 - MT{LO,HI} after [D]MACC */
1892 if (strcmp (tn
, "mtlo") == 0
1893 || strcmp (tn
, "mthi") == 0)
1896 else if (strncmp (pn
, "dmult", 5) == 0
1897 && (strncmp (tn
, "dmult", 5) == 0
1898 || strncmp (tn
, "dmacc", 5) == 0))
1900 /* Here is the rest of errata 23. */
1903 else if ((strncmp (pn
, "dmult", 5) == 0 || strstr (pn
, "div"))
1904 && (strncmp (tn
, "macc", 4) == 0
1905 || strncmp (tn
, "dmacc", 5) == 0))
1907 /* VR4181A errata MD(4): "If a MACC or DMACC instruction is
1908 executed immediately after a DMULT, DMULTU, DIV, DIVU,
1909 DDIV or DDIVU instruction, the result of the MACC or
1910 DMACC instruction is incorrect.". This partly overlaps
1911 the workaround for errata 23. */
1914 if (nops
< min_nops
)
1918 /* If we are being given a nop instruction, don't bother with
1919 one of the nops we would otherwise output. This will only
1920 happen when a nop instruction is used with mips_optimize set
1923 && ! mips_opts
.noreorder
1924 && ip
->insn_opcode
== (unsigned) (mips_opts
.mips16
? 0x6500 : 0))
1927 /* Now emit the right number of NOP instructions. */
1928 if (nops
> 0 && ! mips_opts
.noreorder
)
1931 unsigned long old_frag_offset
;
1933 struct insn_label_list
*l
;
1935 old_frag
= frag_now
;
1936 old_frag_offset
= frag_now_fix ();
1938 for (i
= 0; i
< nops
; i
++)
1943 listing_prev_line ();
1944 /* We may be at the start of a variant frag. In case we
1945 are, make sure there is enough space for the frag
1946 after the frags created by listing_prev_line. The
1947 argument to frag_grow here must be at least as large
1948 as the argument to all other calls to frag_grow in
1949 this file. We don't have to worry about being in the
1950 middle of a variant frag, because the variants insert
1951 all needed nop instructions themselves. */
1955 for (l
= insn_labels
; l
!= NULL
; l
= l
->next
)
1959 assert (S_GET_SEGMENT (l
->label
) == now_seg
);
1960 symbol_set_frag (l
->label
, frag_now
);
1961 val
= (valueT
) frag_now_fix ();
1962 /* mips16 text labels are stored as odd. */
1963 if (mips_opts
.mips16
)
1965 S_SET_VALUE (l
->label
, val
);
1968 #ifndef NO_ECOFF_DEBUGGING
1969 if (ECOFF_DEBUGGING
)
1970 ecoff_fix_loc (old_frag
, old_frag_offset
);
1973 else if (prev_nop_frag
!= NULL
)
1975 /* We have a frag holding nops we may be able to remove. If
1976 we don't need any nops, we can decrease the size of
1977 prev_nop_frag by the size of one instruction. If we do
1978 need some nops, we count them in prev_nops_required. */
1979 if (prev_nop_frag_since
== 0)
1983 prev_nop_frag
->fr_fix
-= mips_opts
.mips16
? 2 : 4;
1984 --prev_nop_frag_holds
;
1987 prev_nop_frag_required
+= nops
;
1991 if (prev_prev_nop
== 0)
1993 prev_nop_frag
->fr_fix
-= mips_opts
.mips16
? 2 : 4;
1994 --prev_nop_frag_holds
;
1997 ++prev_nop_frag_required
;
2000 if (prev_nop_frag_holds
<= prev_nop_frag_required
)
2001 prev_nop_frag
= NULL
;
2003 ++prev_nop_frag_since
;
2005 /* Sanity check: by the time we reach the second instruction
2006 after prev_nop_frag, we should have used up all the nops
2007 one way or another. */
2008 assert (prev_nop_frag_since
<= 1 || prev_nop_frag
== NULL
);
2013 /* The value passed to dwarf2_emit_insn is the distance between
2014 the beginning of the current instruction and the address that
2015 should be recorded in the debug tables. For MIPS16 debug info
2016 we want to use ISA-encoded addresses, so we pass -1 for an
2017 address higher by one than the current. */
2018 dwarf2_emit_insn (mips_opts
.mips16
? -1 : 0);
2021 /* Record the frag type before frag_var. */
2023 prev_insn_frag_type
= prev_insn_frag
->fr_type
;
2026 && *reloc_type
== BFD_RELOC_16_PCREL_S2
2027 && (pinfo
& INSN_UNCOND_BRANCH_DELAY
|| pinfo
& INSN_COND_BRANCH_DELAY
2028 || pinfo
& INSN_COND_BRANCH_LIKELY
)
2029 && mips_relax_branch
2030 /* Don't try branch relaxation within .set nomacro, or within
2031 .set noat if we use $at for PIC computations. If it turns
2032 out that the branch was out-of-range, we'll get an error. */
2033 && !mips_opts
.warn_about_macros
2034 && !(mips_opts
.noat
&& mips_pic
!= NO_PIC
)
2035 && !mips_opts
.mips16
)
2037 relaxed_branch
= TRUE
;
2038 f
= frag_var (rs_machine_dependent
,
2039 relaxed_branch_length
2041 (pinfo
& INSN_UNCOND_BRANCH_DELAY
) ? -1
2042 : (pinfo
& INSN_COND_BRANCH_LIKELY
) ? 1 : 0), 4,
2044 (pinfo
& INSN_UNCOND_BRANCH_DELAY
,
2045 pinfo
& INSN_COND_BRANCH_LIKELY
,
2046 pinfo
& INSN_WRITE_GPR_31
,
2048 address_expr
->X_add_symbol
,
2049 address_expr
->X_add_number
,
2051 *reloc_type
= BFD_RELOC_UNUSED
;
2053 else if (*reloc_type
> BFD_RELOC_UNUSED
)
2055 /* We need to set up a variant frag. */
2056 assert (mips_opts
.mips16
&& address_expr
!= NULL
);
2057 f
= frag_var (rs_machine_dependent
, 4, 0,
2058 RELAX_MIPS16_ENCODE (*reloc_type
- BFD_RELOC_UNUSED
,
2059 mips16_small
, mips16_ext
,
2061 & INSN_UNCOND_BRANCH_DELAY
),
2062 (*prev_insn_reloc_type
2063 == BFD_RELOC_MIPS16_JMP
)),
2064 make_expr_symbol (address_expr
), 0, NULL
);
2066 else if (mips_opts
.mips16
2068 && *reloc_type
!= BFD_RELOC_MIPS16_JMP
)
2070 /* Make sure there is enough room to swap this instruction with
2071 a following jump instruction. */
2077 if (mips_opts
.mips16
2078 && mips_opts
.noreorder
2079 && (prev_pinfo
& INSN_UNCOND_BRANCH_DELAY
) != 0)
2080 as_warn (_("extended instruction in delay slot"));
2082 if (mips_relax
.sequence
)
2084 /* If we've reached the end of this frag, turn it into a variant
2085 frag and record the information for the instructions we've
2087 if (frag_room () < 4)
2088 relax_close_frag ();
2089 mips_relax
.sizes
[mips_relax
.sequence
- 1] += 4;
2092 if (mips_relax
.sequence
!= 2)
2093 mips_macro_warning
.sizes
[0] += 4;
2094 if (mips_relax
.sequence
!= 1)
2095 mips_macro_warning
.sizes
[1] += 4;
2100 fixp
[0] = fixp
[1] = fixp
[2] = NULL
;
2101 if (address_expr
!= NULL
&& *reloc_type
<= BFD_RELOC_UNUSED
)
2103 if (address_expr
->X_op
== O_constant
)
2107 switch (*reloc_type
)
2110 ip
->insn_opcode
|= address_expr
->X_add_number
;
2113 case BFD_RELOC_MIPS_HIGHEST
:
2114 tmp
= (address_expr
->X_add_number
+ 0x800080008000ull
) >> 48;
2115 ip
->insn_opcode
|= tmp
& 0xffff;
2118 case BFD_RELOC_MIPS_HIGHER
:
2119 tmp
= (address_expr
->X_add_number
+ 0x80008000ull
) >> 32;
2120 ip
->insn_opcode
|= tmp
& 0xffff;
2123 case BFD_RELOC_HI16_S
:
2124 tmp
= (address_expr
->X_add_number
+ 0x8000) >> 16;
2125 ip
->insn_opcode
|= tmp
& 0xffff;
2128 case BFD_RELOC_HI16
:
2129 ip
->insn_opcode
|= (address_expr
->X_add_number
>> 16) & 0xffff;
2132 case BFD_RELOC_UNUSED
:
2133 case BFD_RELOC_LO16
:
2134 case BFD_RELOC_MIPS_GOT_DISP
:
2135 ip
->insn_opcode
|= address_expr
->X_add_number
& 0xffff;
2138 case BFD_RELOC_MIPS_JMP
:
2139 if ((address_expr
->X_add_number
& 3) != 0)
2140 as_bad (_("jump to misaligned address (0x%lx)"),
2141 (unsigned long) address_expr
->X_add_number
);
2142 if (address_expr
->X_add_number
& ~0xfffffff)
2143 as_bad (_("jump address range overflow (0x%lx)"),
2144 (unsigned long) address_expr
->X_add_number
);
2145 ip
->insn_opcode
|= (address_expr
->X_add_number
>> 2) & 0x3ffffff;
2148 case BFD_RELOC_MIPS16_JMP
:
2149 if ((address_expr
->X_add_number
& 3) != 0)
2150 as_bad (_("jump to misaligned address (0x%lx)"),
2151 (unsigned long) address_expr
->X_add_number
);
2152 if (address_expr
->X_add_number
& ~0xfffffff)
2153 as_bad (_("jump address range overflow (0x%lx)"),
2154 (unsigned long) address_expr
->X_add_number
);
2156 (((address_expr
->X_add_number
& 0x7c0000) << 3)
2157 | ((address_expr
->X_add_number
& 0xf800000) >> 7)
2158 | ((address_expr
->X_add_number
& 0x3fffc) >> 2));
2161 case BFD_RELOC_16_PCREL_S2
:
2168 else if (*reloc_type
< BFD_RELOC_UNUSED
)
2171 reloc_howto_type
*howto
;
2174 /* In a compound relocation, it is the final (outermost)
2175 operator that determines the relocated field. */
2176 for (i
= 1; i
< 3; i
++)
2177 if (reloc_type
[i
] == BFD_RELOC_UNUSED
)
2180 howto
= bfd_reloc_type_lookup (stdoutput
, reloc_type
[i
- 1]);
2181 fixp
[0] = fix_new_exp (frag_now
, f
- frag_now
->fr_literal
,
2182 bfd_get_reloc_size(howto
),
2184 reloc_type
[0] == BFD_RELOC_16_PCREL_S2
,
2187 /* These relocations can have an addend that won't fit in
2188 4 octets for 64bit assembly. */
2190 && ! howto
->partial_inplace
2191 && (reloc_type
[0] == BFD_RELOC_16
2192 || reloc_type
[0] == BFD_RELOC_32
2193 || reloc_type
[0] == BFD_RELOC_MIPS_JMP
2194 || reloc_type
[0] == BFD_RELOC_HI16_S
2195 || reloc_type
[0] == BFD_RELOC_LO16
2196 || reloc_type
[0] == BFD_RELOC_GPREL16
2197 || reloc_type
[0] == BFD_RELOC_MIPS_LITERAL
2198 || reloc_type
[0] == BFD_RELOC_GPREL32
2199 || reloc_type
[0] == BFD_RELOC_64
2200 || reloc_type
[0] == BFD_RELOC_CTOR
2201 || reloc_type
[0] == BFD_RELOC_MIPS_SUB
2202 || reloc_type
[0] == BFD_RELOC_MIPS_HIGHEST
2203 || reloc_type
[0] == BFD_RELOC_MIPS_HIGHER
2204 || reloc_type
[0] == BFD_RELOC_MIPS_SCN_DISP
2205 || reloc_type
[0] == BFD_RELOC_MIPS_REL16
2206 || reloc_type
[0] == BFD_RELOC_MIPS_RELGOT
2207 || reloc_type
[0] == BFD_RELOC_MIPS16_GPREL
2208 || reloc_type
[0] == BFD_RELOC_MIPS16_HI16_S
2209 || reloc_type
[0] == BFD_RELOC_MIPS16_LO16
))
2210 fixp
[0]->fx_no_overflow
= 1;
2212 if (mips_relax
.sequence
)
2214 if (mips_relax
.first_fixup
== 0)
2215 mips_relax
.first_fixup
= fixp
[0];
2217 else if (reloc_needs_lo_p (*reloc_type
))
2219 struct mips_hi_fixup
*hi_fixup
;
2221 /* Reuse the last entry if it already has a matching %lo. */
2222 hi_fixup
= mips_hi_fixup_list
;
2224 || !fixup_has_matching_lo_p (hi_fixup
->fixp
))
2226 hi_fixup
= ((struct mips_hi_fixup
*)
2227 xmalloc (sizeof (struct mips_hi_fixup
)));
2228 hi_fixup
->next
= mips_hi_fixup_list
;
2229 mips_hi_fixup_list
= hi_fixup
;
2231 hi_fixup
->fixp
= fixp
[0];
2232 hi_fixup
->seg
= now_seg
;
2235 /* Add fixups for the second and third relocations, if given.
2236 Note that the ABI allows the second relocation to be
2237 against RSS_UNDEF, RSS_GP, RSS_GP0 or RSS_LOC. At the
2238 moment we only use RSS_UNDEF, but we could add support
2239 for the others if it ever becomes necessary. */
2240 for (i
= 1; i
< 3; i
++)
2241 if (reloc_type
[i
] != BFD_RELOC_UNUSED
)
2243 fixp
[i
] = fix_new (frag_now
, fixp
[0]->fx_where
,
2244 fixp
[0]->fx_size
, NULL
, 0,
2245 FALSE
, reloc_type
[i
]);
2247 /* Use fx_tcbit to mark compound relocs. */
2248 fixp
[0]->fx_tcbit
= 1;
2249 fixp
[i
]->fx_tcbit
= 1;
2254 if (! mips_opts
.mips16
)
2255 md_number_to_chars (f
, ip
->insn_opcode
, 4);
2256 else if (*reloc_type
== BFD_RELOC_MIPS16_JMP
)
2258 md_number_to_chars (f
, ip
->insn_opcode
>> 16, 2);
2259 md_number_to_chars (f
+ 2, ip
->insn_opcode
& 0xffff, 2);
2265 md_number_to_chars (f
, 0xf000 | ip
->extend
, 2);
2268 md_number_to_chars (f
, ip
->insn_opcode
, 2);
2271 /* Update the register mask information. */
2272 if (! mips_opts
.mips16
)
2274 if (pinfo
& INSN_WRITE_GPR_D
)
2275 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
);
2276 if ((pinfo
& (INSN_WRITE_GPR_T
| INSN_READ_GPR_T
)) != 0)
2277 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
);
2278 if (pinfo
& INSN_READ_GPR_S
)
2279 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> OP_SH_RS
) & OP_MASK_RS
);
2280 if (pinfo
& INSN_WRITE_GPR_31
)
2281 mips_gprmask
|= 1 << RA
;
2282 if (pinfo
& INSN_WRITE_FPR_D
)
2283 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FD
) & OP_MASK_FD
);
2284 if ((pinfo
& (INSN_WRITE_FPR_S
| INSN_READ_FPR_S
)) != 0)
2285 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FS
) & OP_MASK_FS
);
2286 if ((pinfo
& (INSN_WRITE_FPR_T
| INSN_READ_FPR_T
)) != 0)
2287 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FT
) & OP_MASK_FT
);
2288 if ((pinfo
& INSN_READ_FPR_R
) != 0)
2289 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FR
) & OP_MASK_FR
);
2290 if (pinfo
& INSN_COP
)
2292 /* We don't keep enough information to sort these cases out.
2293 The itbl support does keep this information however, although
2294 we currently don't support itbl fprmats as part of the cop
2295 instruction. May want to add this support in the future. */
2297 /* Never set the bit for $0, which is always zero. */
2298 mips_gprmask
&= ~1 << 0;
2302 if (pinfo
& (MIPS16_INSN_WRITE_X
| MIPS16_INSN_READ_X
))
2303 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_RX
)
2304 & MIPS16OP_MASK_RX
);
2305 if (pinfo
& (MIPS16_INSN_WRITE_Y
| MIPS16_INSN_READ_Y
))
2306 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_RY
)
2307 & MIPS16OP_MASK_RY
);
2308 if (pinfo
& MIPS16_INSN_WRITE_Z
)
2309 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_RZ
)
2310 & MIPS16OP_MASK_RZ
);
2311 if (pinfo
& (MIPS16_INSN_WRITE_T
| MIPS16_INSN_READ_T
))
2312 mips_gprmask
|= 1 << TREG
;
2313 if (pinfo
& (MIPS16_INSN_WRITE_SP
| MIPS16_INSN_READ_SP
))
2314 mips_gprmask
|= 1 << SP
;
2315 if (pinfo
& (MIPS16_INSN_WRITE_31
| MIPS16_INSN_READ_31
))
2316 mips_gprmask
|= 1 << RA
;
2317 if (pinfo
& MIPS16_INSN_WRITE_GPR_Y
)
2318 mips_gprmask
|= 1 << MIPS16OP_EXTRACT_REG32R (ip
->insn_opcode
);
2319 if (pinfo
& MIPS16_INSN_READ_Z
)
2320 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_MOVE32Z
)
2321 & MIPS16OP_MASK_MOVE32Z
);
2322 if (pinfo
& MIPS16_INSN_READ_GPR_X
)
2323 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_REGR32
)
2324 & MIPS16OP_MASK_REGR32
);
2327 if (mips_relax
.sequence
!= 2 && !mips_opts
.noreorder
)
2329 /* Filling the branch delay slot is more complex. We try to
2330 switch the branch with the previous instruction, which we can
2331 do if the previous instruction does not set up a condition
2332 that the branch tests and if the branch is not itself the
2333 target of any branch. */
2334 if ((pinfo
& INSN_UNCOND_BRANCH_DELAY
)
2335 || (pinfo
& INSN_COND_BRANCH_DELAY
))
2337 if (mips_optimize
< 2
2338 /* If we have seen .set volatile or .set nomove, don't
2340 || mips_opts
.nomove
!= 0
2341 /* If we had to emit any NOP instructions, then we
2342 already know we can not swap. */
2344 /* If we don't even know the previous insn, we can not
2346 || ! prev_insn_valid
2347 /* If the previous insn is already in a branch delay
2348 slot, then we can not swap. */
2349 || prev_insn_is_delay_slot
2350 /* If the previous previous insn was in a .set
2351 noreorder, we can't swap. Actually, the MIPS
2352 assembler will swap in this situation. However, gcc
2353 configured -with-gnu-as will generate code like
2359 in which we can not swap the bne and INSN. If gcc is
2360 not configured -with-gnu-as, it does not output the
2361 .set pseudo-ops. We don't have to check
2362 prev_insn_unreordered, because prev_insn_valid will
2363 be 0 in that case. We don't want to use
2364 prev_prev_insn_valid, because we do want to be able
2365 to swap at the start of a function. */
2366 || prev_prev_insn_unreordered
2367 /* If the branch is itself the target of a branch, we
2368 can not swap. We cheat on this; all we check for is
2369 whether there is a label on this instruction. If
2370 there are any branches to anything other than a
2371 label, users must use .set noreorder. */
2372 || insn_labels
!= NULL
2373 /* If the previous instruction is in a variant frag
2374 other than this branch's one, we cannot do the swap.
2375 This does not apply to the mips16, which uses variant
2376 frags for different purposes. */
2377 || (! mips_opts
.mips16
2378 && prev_insn_frag_type
== rs_machine_dependent
)
2379 /* If the branch reads the condition codes, we don't
2380 even try to swap, because in the sequence
2385 we can not swap, and I don't feel like handling that
2387 || (! mips_opts
.mips16
2388 && (pinfo
& INSN_READ_COND_CODE
)
2389 && ! cop_interlocks
)
2390 /* We can not swap with an instruction that requires a
2391 delay slot, because the target of the branch might
2392 interfere with that instruction. */
2393 || (! mips_opts
.mips16
2395 /* Itbl support may require additional care here. */
2396 & (INSN_LOAD_COPROC_DELAY
2397 | INSN_COPROC_MOVE_DELAY
2398 | INSN_WRITE_COND_CODE
))
2399 && ! cop_interlocks
)
2400 || (! (hilo_interlocks
2401 || (mips_opts
.arch
== CPU_R3900
&& (pinfo
& INSN_MULT
)))
2405 || (! mips_opts
.mips16
2406 && (prev_pinfo
& INSN_LOAD_MEMORY_DELAY
)
2407 && ! gpr_interlocks
)
2408 || (! mips_opts
.mips16
2409 /* Itbl support may require additional care here. */
2410 && (prev_pinfo
& INSN_COPROC_MEMORY_DELAY
)
2411 && ! cop_mem_interlocks
)
2412 /* We can not swap with a branch instruction. */
2414 & (INSN_UNCOND_BRANCH_DELAY
2415 | INSN_COND_BRANCH_DELAY
2416 | INSN_COND_BRANCH_LIKELY
))
2417 /* We do not swap with a trap instruction, since it
2418 complicates trap handlers to have the trap
2419 instruction be in a delay slot. */
2420 || (prev_pinfo
& INSN_TRAP
)
2421 /* If the branch reads a register that the previous
2422 instruction sets, we can not swap. */
2423 || (! mips_opts
.mips16
2424 && (prev_pinfo
& INSN_WRITE_GPR_T
)
2425 && insn_uses_reg (ip
,
2426 ((prev_insn
.insn_opcode
>> OP_SH_RT
)
2429 || (! mips_opts
.mips16
2430 && (prev_pinfo
& INSN_WRITE_GPR_D
)
2431 && insn_uses_reg (ip
,
2432 ((prev_insn
.insn_opcode
>> OP_SH_RD
)
2435 || (mips_opts
.mips16
2436 && (((prev_pinfo
& MIPS16_INSN_WRITE_X
)
2437 && insn_uses_reg (ip
,
2438 ((prev_insn
.insn_opcode
2440 & MIPS16OP_MASK_RX
),
2442 || ((prev_pinfo
& MIPS16_INSN_WRITE_Y
)
2443 && insn_uses_reg (ip
,
2444 ((prev_insn
.insn_opcode
2446 & MIPS16OP_MASK_RY
),
2448 || ((prev_pinfo
& MIPS16_INSN_WRITE_Z
)
2449 && insn_uses_reg (ip
,
2450 ((prev_insn
.insn_opcode
2452 & MIPS16OP_MASK_RZ
),
2454 || ((prev_pinfo
& MIPS16_INSN_WRITE_T
)
2455 && insn_uses_reg (ip
, TREG
, MIPS_GR_REG
))
2456 || ((prev_pinfo
& MIPS16_INSN_WRITE_31
)
2457 && insn_uses_reg (ip
, RA
, MIPS_GR_REG
))
2458 || ((prev_pinfo
& MIPS16_INSN_WRITE_GPR_Y
)
2459 && insn_uses_reg (ip
,
2460 MIPS16OP_EXTRACT_REG32R (prev_insn
.
2463 /* If the branch writes a register that the previous
2464 instruction sets, we can not swap (we know that
2465 branches write only to RD or to $31). */
2466 || (! mips_opts
.mips16
2467 && (prev_pinfo
& INSN_WRITE_GPR_T
)
2468 && (((pinfo
& INSN_WRITE_GPR_D
)
2469 && (((prev_insn
.insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
)
2470 == ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)))
2471 || ((pinfo
& INSN_WRITE_GPR_31
)
2472 && (((prev_insn
.insn_opcode
>> OP_SH_RT
)
2475 || (! mips_opts
.mips16
2476 && (prev_pinfo
& INSN_WRITE_GPR_D
)
2477 && (((pinfo
& INSN_WRITE_GPR_D
)
2478 && (((prev_insn
.insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)
2479 == ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)))
2480 || ((pinfo
& INSN_WRITE_GPR_31
)
2481 && (((prev_insn
.insn_opcode
>> OP_SH_RD
)
2484 || (mips_opts
.mips16
2485 && (pinfo
& MIPS16_INSN_WRITE_31
)
2486 && ((prev_pinfo
& MIPS16_INSN_WRITE_31
)
2487 || ((prev_pinfo
& MIPS16_INSN_WRITE_GPR_Y
)
2488 && (MIPS16OP_EXTRACT_REG32R (prev_insn
.insn_opcode
)
2490 /* If the branch writes a register that the previous
2491 instruction reads, we can not swap (we know that
2492 branches only write to RD or to $31). */
2493 || (! mips_opts
.mips16
2494 && (pinfo
& INSN_WRITE_GPR_D
)
2495 && insn_uses_reg (&prev_insn
,
2496 ((ip
->insn_opcode
>> OP_SH_RD
)
2499 || (! mips_opts
.mips16
2500 && (pinfo
& INSN_WRITE_GPR_31
)
2501 && insn_uses_reg (&prev_insn
, RA
, MIPS_GR_REG
))
2502 || (mips_opts
.mips16
2503 && (pinfo
& MIPS16_INSN_WRITE_31
)
2504 && insn_uses_reg (&prev_insn
, RA
, MIPS_GR_REG
))
2505 /* If the previous previous instruction has a load
2506 delay, and sets a register that the branch reads, we
2508 || (! mips_opts
.mips16
2509 /* Itbl support may require additional care here. */
2510 && (((prev_prev_insn
.insn_mo
->pinfo
& INSN_LOAD_COPROC_DELAY
)
2511 && ! cop_interlocks
)
2512 || ((prev_prev_insn
.insn_mo
->pinfo
2513 & INSN_LOAD_MEMORY_DELAY
)
2514 && ! gpr_interlocks
))
2515 && insn_uses_reg (ip
,
2516 ((prev_prev_insn
.insn_opcode
>> OP_SH_RT
)
2519 /* If one instruction sets a condition code and the
2520 other one uses a condition code, we can not swap. */
2521 || ((pinfo
& INSN_READ_COND_CODE
)
2522 && (prev_pinfo
& INSN_WRITE_COND_CODE
))
2523 || ((pinfo
& INSN_WRITE_COND_CODE
)
2524 && (prev_pinfo
& INSN_READ_COND_CODE
))
2525 /* If the previous instruction uses the PC, we can not
2527 || (mips_opts
.mips16
2528 && (prev_pinfo
& MIPS16_INSN_READ_PC
))
2529 /* If the previous instruction was extended, we can not
2531 || (mips_opts
.mips16
&& prev_insn_extended
)
2532 /* If the previous instruction had a fixup in mips16
2533 mode, we can not swap. This normally means that the
2534 previous instruction was a 4 byte branch anyhow. */
2535 || (mips_opts
.mips16
&& prev_insn_fixp
[0])
2536 /* If the previous instruction is a sync, sync.l, or
2537 sync.p, we can not swap. */
2538 || (prev_pinfo
& INSN_SYNC
))
2540 /* We could do even better for unconditional branches to
2541 portions of this object file; we could pick up the
2542 instruction at the destination, put it in the delay
2543 slot, and bump the destination address. */
2545 if (mips_relax
.sequence
)
2546 mips_relax
.sizes
[mips_relax
.sequence
- 1] += 4;
2547 /* Update the previous insn information. */
2548 prev_prev_insn
= *ip
;
2549 prev_insn
.insn_mo
= &dummy_opcode
;
2553 /* It looks like we can actually do the swap. */
2554 if (! mips_opts
.mips16
)
2559 prev_f
= prev_insn_frag
->fr_literal
+ prev_insn_where
;
2560 if (!relaxed_branch
)
2562 /* If this is not a relaxed branch, then just
2563 swap the instructions. */
2564 memcpy (temp
, prev_f
, 4);
2565 memcpy (prev_f
, f
, 4);
2566 memcpy (f
, temp
, 4);
2570 /* If this is a relaxed branch, then we move the
2571 instruction to be placed in the delay slot to
2572 the current frag, shrinking the fixed part of
2573 the originating frag. If the branch occupies
2574 the tail of the latter, we move it backwards,
2575 into the space freed by the moved instruction. */
2577 memcpy (f
, prev_f
, 4);
2578 prev_insn_frag
->fr_fix
-= 4;
2579 if (prev_insn_frag
->fr_type
== rs_machine_dependent
)
2580 memmove (prev_f
, prev_f
+ 4, prev_insn_frag
->fr_var
);
2583 if (prev_insn_fixp
[0])
2585 prev_insn_fixp
[0]->fx_frag
= frag_now
;
2586 prev_insn_fixp
[0]->fx_where
= f
- frag_now
->fr_literal
;
2588 if (prev_insn_fixp
[1])
2590 prev_insn_fixp
[1]->fx_frag
= frag_now
;
2591 prev_insn_fixp
[1]->fx_where
= f
- frag_now
->fr_literal
;
2593 if (prev_insn_fixp
[2])
2595 prev_insn_fixp
[2]->fx_frag
= frag_now
;
2596 prev_insn_fixp
[2]->fx_where
= f
- frag_now
->fr_literal
;
2598 if (prev_insn_fixp
[0] && HAVE_NEWABI
2599 && prev_insn_frag
!= frag_now
2600 && (prev_insn_fixp
[0]->fx_r_type
2601 == BFD_RELOC_MIPS_GOT_DISP
2602 || (prev_insn_fixp
[0]->fx_r_type
2603 == BFD_RELOC_MIPS_CALL16
)))
2605 /* To avoid confusion in tc_gen_reloc, we must
2606 ensure that this does not become a variant
2608 force_new_frag
= TRUE
;
2611 if (!relaxed_branch
)
2615 fixp
[0]->fx_frag
= prev_insn_frag
;
2616 fixp
[0]->fx_where
= prev_insn_where
;
2620 fixp
[1]->fx_frag
= prev_insn_frag
;
2621 fixp
[1]->fx_where
= prev_insn_where
;
2625 fixp
[2]->fx_frag
= prev_insn_frag
;
2626 fixp
[2]->fx_where
= prev_insn_where
;
2629 else if (prev_insn_frag
->fr_type
== rs_machine_dependent
)
2632 fixp
[0]->fx_where
-= 4;
2634 fixp
[1]->fx_where
-= 4;
2636 fixp
[2]->fx_where
-= 4;
2644 assert (prev_insn_fixp
[0] == NULL
);
2645 assert (prev_insn_fixp
[1] == NULL
);
2646 assert (prev_insn_fixp
[2] == NULL
);
2647 prev_f
= prev_insn_frag
->fr_literal
+ prev_insn_where
;
2648 memcpy (temp
, prev_f
, 2);
2649 memcpy (prev_f
, f
, 2);
2650 if (*reloc_type
!= BFD_RELOC_MIPS16_JMP
)
2652 assert (*reloc_type
== BFD_RELOC_UNUSED
);
2653 memcpy (f
, temp
, 2);
2657 memcpy (f
, f
+ 2, 2);
2658 memcpy (f
+ 2, temp
, 2);
2662 fixp
[0]->fx_frag
= prev_insn_frag
;
2663 fixp
[0]->fx_where
= prev_insn_where
;
2667 fixp
[1]->fx_frag
= prev_insn_frag
;
2668 fixp
[1]->fx_where
= prev_insn_where
;
2672 fixp
[2]->fx_frag
= prev_insn_frag
;
2673 fixp
[2]->fx_where
= prev_insn_where
;
2677 /* Update the previous insn information; leave prev_insn
2679 prev_prev_insn
= *ip
;
2681 prev_insn_is_delay_slot
= 1;
2683 /* If that was an unconditional branch, forget the previous
2684 insn information. */
2685 if (pinfo
& INSN_UNCOND_BRANCH_DELAY
)
2687 prev_prev_insn
.insn_mo
= &dummy_opcode
;
2688 prev_insn
.insn_mo
= &dummy_opcode
;
2691 prev_insn_fixp
[0] = NULL
;
2692 prev_insn_fixp
[1] = NULL
;
2693 prev_insn_fixp
[2] = NULL
;
2694 prev_insn_reloc_type
[0] = BFD_RELOC_UNUSED
;
2695 prev_insn_reloc_type
[1] = BFD_RELOC_UNUSED
;
2696 prev_insn_reloc_type
[2] = BFD_RELOC_UNUSED
;
2697 prev_insn_extended
= 0;
2699 else if (pinfo
& INSN_COND_BRANCH_LIKELY
)
2701 /* We don't yet optimize a branch likely. What we should do
2702 is look at the target, copy the instruction found there
2703 into the delay slot, and increment the branch to jump to
2704 the next instruction. */
2706 /* Update the previous insn information. */
2707 prev_prev_insn
= *ip
;
2708 prev_insn
.insn_mo
= &dummy_opcode
;
2709 prev_insn_fixp
[0] = NULL
;
2710 prev_insn_fixp
[1] = NULL
;
2711 prev_insn_fixp
[2] = NULL
;
2712 prev_insn_reloc_type
[0] = BFD_RELOC_UNUSED
;
2713 prev_insn_reloc_type
[1] = BFD_RELOC_UNUSED
;
2714 prev_insn_reloc_type
[2] = BFD_RELOC_UNUSED
;
2715 prev_insn_extended
= 0;
2716 prev_insn_is_delay_slot
= 1;
2720 /* Update the previous insn information. */
2722 prev_prev_insn
.insn_mo
= &dummy_opcode
;
2724 prev_prev_insn
= prev_insn
;
2727 /* Any time we see a branch, we always fill the delay slot
2728 immediately; since this insn is not a branch, we know it
2729 is not in a delay slot. */
2730 prev_insn_is_delay_slot
= 0;
2732 prev_insn_fixp
[0] = fixp
[0];
2733 prev_insn_fixp
[1] = fixp
[1];
2734 prev_insn_fixp
[2] = fixp
[2];
2735 prev_insn_reloc_type
[0] = reloc_type
[0];
2736 prev_insn_reloc_type
[1] = reloc_type
[1];
2737 prev_insn_reloc_type
[2] = reloc_type
[2];
2738 if (mips_opts
.mips16
)
2739 prev_insn_extended
= (ip
->use_extend
2740 || *reloc_type
> BFD_RELOC_UNUSED
);
2743 prev_prev_insn_unreordered
= prev_insn_unreordered
;
2744 prev_insn_unreordered
= 0;
2745 prev_insn_frag
= frag_now
;
2746 prev_insn_where
= f
- frag_now
->fr_literal
;
2747 prev_insn_valid
= 1;
2749 else if (mips_relax
.sequence
!= 2)
2751 /* We need to record a bit of information even when we are not
2752 reordering, in order to determine the base address for mips16
2753 PC relative relocs. */
2754 prev_prev_insn
= prev_insn
;
2756 prev_insn_reloc_type
[0] = reloc_type
[0];
2757 prev_insn_reloc_type
[1] = reloc_type
[1];
2758 prev_insn_reloc_type
[2] = reloc_type
[2];
2759 prev_prev_insn_unreordered
= prev_insn_unreordered
;
2760 prev_insn_unreordered
= 1;
2763 /* We just output an insn, so the next one doesn't have a label. */
2764 mips_clear_insn_labels ();
2767 /* This function forgets that there was any previous instruction or
2768 label. If PRESERVE is non-zero, it remembers enough information to
2769 know whether nops are needed before a noreorder section. */
2772 mips_no_prev_insn (int preserve
)
2776 prev_insn
.insn_mo
= &dummy_opcode
;
2777 prev_prev_insn
.insn_mo
= &dummy_opcode
;
2778 prev_nop_frag
= NULL
;
2779 prev_nop_frag_holds
= 0;
2780 prev_nop_frag_required
= 0;
2781 prev_nop_frag_since
= 0;
2783 prev_insn_valid
= 0;
2784 prev_insn_is_delay_slot
= 0;
2785 prev_insn_unreordered
= 0;
2786 prev_insn_extended
= 0;
2787 prev_insn_reloc_type
[0] = BFD_RELOC_UNUSED
;
2788 prev_insn_reloc_type
[1] = BFD_RELOC_UNUSED
;
2789 prev_insn_reloc_type
[2] = BFD_RELOC_UNUSED
;
2790 prev_prev_insn_unreordered
= 0;
2791 mips_clear_insn_labels ();
2794 /* This function must be called whenever we turn on noreorder or emit
2795 something other than instructions. It inserts any NOPS which might
2796 be needed by the previous instruction, and clears the information
2797 kept for the previous instructions. The INSNS parameter is true if
2798 instructions are to follow. */
2801 mips_emit_delays (bfd_boolean insns
)
2803 if (! mips_opts
.noreorder
)
2808 if ((! mips_opts
.mips16
2809 && ((prev_insn
.insn_mo
->pinfo
2810 & (INSN_LOAD_COPROC_DELAY
2811 | INSN_COPROC_MOVE_DELAY
2812 | INSN_WRITE_COND_CODE
))
2813 && ! cop_interlocks
))
2814 || (! hilo_interlocks
2815 && (prev_insn
.insn_mo
->pinfo
2818 || (! mips_opts
.mips16
2819 && (prev_insn
.insn_mo
->pinfo
& INSN_LOAD_MEMORY_DELAY
)
2820 && ! gpr_interlocks
)
2821 || (! mips_opts
.mips16
2822 && (prev_insn
.insn_mo
->pinfo
& INSN_COPROC_MEMORY_DELAY
)
2823 && ! cop_mem_interlocks
))
2825 /* Itbl support may require additional care here. */
2827 if ((! mips_opts
.mips16
2828 && ((prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
)
2829 && ! cop_interlocks
))
2830 || (! hilo_interlocks
2831 && ((prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
2832 || (prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
))))
2835 if (prev_insn_unreordered
)
2838 else if ((! mips_opts
.mips16
2839 && ((prev_prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
)
2840 && ! cop_interlocks
))
2841 || (! hilo_interlocks
2842 && ((prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
2843 || (prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
))))
2845 /* Itbl support may require additional care here. */
2846 if (! prev_prev_insn_unreordered
)
2850 if (mips_fix_vr4120
&& prev_insn
.insn_mo
->name
)
2853 const char *pn
= prev_insn
.insn_mo
->name
;
2854 if (strncmp (pn
, "macc", 4) == 0
2855 || strncmp (pn
, "dmacc", 5) == 0
2856 || strncmp (pn
, "dmult", 5) == 0
2857 || strstr (pn
, "div"))
2859 if (nops
< min_nops
)
2865 struct insn_label_list
*l
;
2869 /* Record the frag which holds the nop instructions, so
2870 that we can remove them if we don't need them. */
2871 frag_grow (mips_opts
.mips16
? nops
* 2 : nops
* 4);
2872 prev_nop_frag
= frag_now
;
2873 prev_nop_frag_holds
= nops
;
2874 prev_nop_frag_required
= 0;
2875 prev_nop_frag_since
= 0;
2878 for (; nops
> 0; --nops
)
2883 /* Move on to a new frag, so that it is safe to simply
2884 decrease the size of prev_nop_frag. */
2885 frag_wane (frag_now
);
2889 for (l
= insn_labels
; l
!= NULL
; l
= l
->next
)
2893 assert (S_GET_SEGMENT (l
->label
) == now_seg
);
2894 symbol_set_frag (l
->label
, frag_now
);
2895 val
= (valueT
) frag_now_fix ();
2896 /* mips16 text labels are stored as odd. */
2897 if (mips_opts
.mips16
)
2899 S_SET_VALUE (l
->label
, val
);
2904 /* Mark instruction labels in mips16 mode. */
2906 mips16_mark_labels ();
2908 mips_no_prev_insn (insns
);
2911 /* Set up global variables for the start of a new macro. */
2916 memset (&mips_macro_warning
.sizes
, 0, sizeof (mips_macro_warning
.sizes
));
2917 mips_macro_warning
.delay_slot_p
= (mips_opts
.noreorder
2918 && (prev_insn
.insn_mo
->pinfo
2919 & (INSN_UNCOND_BRANCH_DELAY
2920 | INSN_COND_BRANCH_DELAY
2921 | INSN_COND_BRANCH_LIKELY
)) != 0);
2924 /* Given that a macro is longer than 4 bytes, return the appropriate warning
2925 for it. Return null if no warning is needed. SUBTYPE is a bitmask of
2926 RELAX_DELAY_SLOT and RELAX_NOMACRO. */
2929 macro_warning (relax_substateT subtype
)
2931 if (subtype
& RELAX_DELAY_SLOT
)
2932 return _("Macro instruction expanded into multiple instructions"
2933 " in a branch delay slot");
2934 else if (subtype
& RELAX_NOMACRO
)
2935 return _("Macro instruction expanded into multiple instructions");
2940 /* Finish up a macro. Emit warnings as appropriate. */
2945 if (mips_macro_warning
.sizes
[0] > 4 || mips_macro_warning
.sizes
[1] > 4)
2947 relax_substateT subtype
;
2949 /* Set up the relaxation warning flags. */
2951 if (mips_macro_warning
.sizes
[1] > mips_macro_warning
.sizes
[0])
2952 subtype
|= RELAX_SECOND_LONGER
;
2953 if (mips_opts
.warn_about_macros
)
2954 subtype
|= RELAX_NOMACRO
;
2955 if (mips_macro_warning
.delay_slot_p
)
2956 subtype
|= RELAX_DELAY_SLOT
;
2958 if (mips_macro_warning
.sizes
[0] > 4 && mips_macro_warning
.sizes
[1] > 4)
2960 /* Either the macro has a single implementation or both
2961 implementations are longer than 4 bytes. Emit the
2963 const char *msg
= macro_warning (subtype
);
2969 /* One implementation might need a warning but the other
2970 definitely doesn't. */
2971 mips_macro_warning
.first_frag
->fr_subtype
|= subtype
;
2976 /* Read a macro's relocation codes from *ARGS and store them in *R.
2977 The first argument in *ARGS will be either the code for a single
2978 relocation or -1 followed by the three codes that make up a
2979 composite relocation. */
2982 macro_read_relocs (va_list *args
, bfd_reloc_code_real_type
*r
)
2986 next
= va_arg (*args
, int);
2988 r
[0] = (bfd_reloc_code_real_type
) next
;
2990 for (i
= 0; i
< 3; i
++)
2991 r
[i
] = (bfd_reloc_code_real_type
) va_arg (*args
, int);
2994 /* Build an instruction created by a macro expansion. This is passed
2995 a pointer to the count of instructions created so far, an
2996 expression, the name of the instruction to build, an operand format
2997 string, and corresponding arguments. */
3000 macro_build (expressionS
*ep
, const char *name
, const char *fmt
, ...)
3002 struct mips_cl_insn insn
;
3003 bfd_reloc_code_real_type r
[3];
3006 va_start (args
, fmt
);
3008 if (mips_opts
.mips16
)
3010 mips16_macro_build (ep
, name
, fmt
, args
);
3015 r
[0] = BFD_RELOC_UNUSED
;
3016 r
[1] = BFD_RELOC_UNUSED
;
3017 r
[2] = BFD_RELOC_UNUSED
;
3018 insn
.insn_mo
= (struct mips_opcode
*) hash_find (op_hash
, name
);
3019 assert (insn
.insn_mo
);
3020 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
3022 /* Search until we get a match for NAME. */
3025 /* It is assumed here that macros will never generate
3026 MDMX or MIPS-3D instructions. */
3027 if (strcmp (fmt
, insn
.insn_mo
->args
) == 0
3028 && insn
.insn_mo
->pinfo
!= INSN_MACRO
3029 && OPCODE_IS_MEMBER (insn
.insn_mo
,
3031 | (file_ase_mips16
? INSN_MIPS16
: 0)),
3033 && (mips_opts
.arch
!= CPU_R4650
|| (insn
.insn_mo
->pinfo
& FP_D
) == 0))
3037 assert (insn
.insn_mo
->name
);
3038 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
3041 insn
.insn_opcode
= insn
.insn_mo
->match
;
3059 insn
.insn_opcode
|= (va_arg (args
, int)
3060 & OP_MASK_SHAMT
) << OP_SH_SHAMT
;
3065 /* Note that in the macro case, these arguments are already
3066 in MSB form. (When handling the instruction in the
3067 non-macro case, these arguments are sizes from which
3068 MSB values must be calculated.) */
3069 insn
.insn_opcode
|= (va_arg (args
, int)
3070 & OP_MASK_INSMSB
) << OP_SH_INSMSB
;
3076 /* Note that in the macro case, these arguments are already
3077 in MSBD form. (When handling the instruction in the
3078 non-macro case, these arguments are sizes from which
3079 MSBD values must be calculated.) */
3080 insn
.insn_opcode
|= (va_arg (args
, int)
3081 & OP_MASK_EXTMSBD
) << OP_SH_EXTMSBD
;
3092 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_RT
;
3096 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_CODE
;
3101 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_FT
;
3107 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_RD
;
3112 int tmp
= va_arg (args
, int);
3114 insn
.insn_opcode
|= tmp
<< OP_SH_RT
;
3115 insn
.insn_opcode
|= tmp
<< OP_SH_RD
;
3121 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_FS
;
3128 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_SHAMT
;
3132 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_FD
;
3136 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_CODE20
;
3140 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_CODE19
;
3144 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_CODE2
;
3151 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_RS
;
3157 macro_read_relocs (&args
, r
);
3158 assert (*r
== BFD_RELOC_GPREL16
3159 || *r
== BFD_RELOC_MIPS_LITERAL
3160 || *r
== BFD_RELOC_MIPS_HIGHER
3161 || *r
== BFD_RELOC_HI16_S
3162 || *r
== BFD_RELOC_LO16
3163 || *r
== BFD_RELOC_MIPS_GOT16
3164 || *r
== BFD_RELOC_MIPS_CALL16
3165 || *r
== BFD_RELOC_MIPS_GOT_DISP
3166 || *r
== BFD_RELOC_MIPS_GOT_PAGE
3167 || *r
== BFD_RELOC_MIPS_GOT_OFST
3168 || *r
== BFD_RELOC_MIPS_GOT_LO16
3169 || *r
== BFD_RELOC_MIPS_CALL_LO16
);
3173 macro_read_relocs (&args
, r
);
3175 && (ep
->X_op
== O_constant
3176 || (ep
->X_op
== O_symbol
3177 && (*r
== BFD_RELOC_MIPS_HIGHEST
3178 || *r
== BFD_RELOC_HI16_S
3179 || *r
== BFD_RELOC_HI16
3180 || *r
== BFD_RELOC_GPREL16
3181 || *r
== BFD_RELOC_MIPS_GOT_HI16
3182 || *r
== BFD_RELOC_MIPS_CALL_HI16
))));
3186 assert (ep
!= NULL
);
3188 * This allows macro() to pass an immediate expression for
3189 * creating short branches without creating a symbol.
3190 * Note that the expression still might come from the assembly
3191 * input, in which case the value is not checked for range nor
3192 * is a relocation entry generated (yuck).
3194 if (ep
->X_op
== O_constant
)
3196 insn
.insn_opcode
|= (ep
->X_add_number
>> 2) & 0xffff;
3200 *r
= BFD_RELOC_16_PCREL_S2
;
3204 assert (ep
!= NULL
);
3205 *r
= BFD_RELOC_MIPS_JMP
;
3209 insn
.insn_opcode
|= va_arg (args
, unsigned long);
3218 assert (*r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
3220 append_insn (&insn
, ep
, r
);
3224 mips16_macro_build (expressionS
*ep
, const char *name
, const char *fmt
,
3227 struct mips_cl_insn insn
;
3228 bfd_reloc_code_real_type r
[3]
3229 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
3231 insn
.insn_mo
= (struct mips_opcode
*) hash_find (mips16_op_hash
, name
);
3232 assert (insn
.insn_mo
);
3233 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
3235 while (strcmp (fmt
, insn
.insn_mo
->args
) != 0
3236 || insn
.insn_mo
->pinfo
== INSN_MACRO
)
3239 assert (insn
.insn_mo
->name
);
3240 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
3243 insn
.insn_opcode
= insn
.insn_mo
->match
;
3244 insn
.use_extend
= FALSE
;
3263 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_RY
;
3268 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_RX
;
3272 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_RZ
;
3276 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_MOVE32Z
;
3286 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_REGR32
;
3293 regno
= va_arg (args
, int);
3294 regno
= ((regno
& 7) << 2) | ((regno
& 0x18) >> 3);
3295 insn
.insn_opcode
|= regno
<< MIPS16OP_SH_REG32R
;
3316 assert (ep
!= NULL
);
3318 if (ep
->X_op
!= O_constant
)
3319 *r
= (int) BFD_RELOC_UNUSED
+ c
;
3322 mips16_immed (NULL
, 0, c
, ep
->X_add_number
, FALSE
, FALSE
,
3323 FALSE
, &insn
.insn_opcode
, &insn
.use_extend
,
3326 *r
= BFD_RELOC_UNUSED
;
3332 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_IMM6
;
3339 assert (*r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
3341 append_insn (&insn
, ep
, r
);
3345 * Generate a "jalr" instruction with a relocation hint to the called
3346 * function. This occurs in NewABI PIC code.
3349 macro_build_jalr (expressionS
*ep
)
3358 macro_build (NULL
, "jalr", "d,s", RA
, PIC_CALL_REG
);
3360 fix_new_exp (frag_now
, f
- frag_now
->fr_literal
,
3361 4, ep
, FALSE
, BFD_RELOC_MIPS_JALR
);
3365 * Generate a "lui" instruction.
3368 macro_build_lui (expressionS
*ep
, int regnum
)
3370 expressionS high_expr
;
3371 struct mips_cl_insn insn
;
3372 bfd_reloc_code_real_type r
[3]
3373 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
3374 const char *name
= "lui";
3375 const char *fmt
= "t,u";
3377 assert (! mips_opts
.mips16
);
3381 if (high_expr
.X_op
== O_constant
)
3383 /* we can compute the instruction now without a relocation entry */
3384 high_expr
.X_add_number
= ((high_expr
.X_add_number
+ 0x8000)
3386 *r
= BFD_RELOC_UNUSED
;
3390 assert (ep
->X_op
== O_symbol
);
3391 /* _gp_disp is a special case, used from s_cpload. _gp is used
3392 if mips_no_shared. */
3393 assert (mips_pic
== NO_PIC
3395 && strcmp (S_GET_NAME (ep
->X_add_symbol
), "_gp_disp") == 0)
3396 || (! mips_in_shared
3397 && strcmp (S_GET_NAME (ep
->X_add_symbol
), "_gp") == 0));
3398 *r
= BFD_RELOC_HI16_S
;
3401 insn
.insn_mo
= (struct mips_opcode
*) hash_find (op_hash
, name
);
3402 assert (insn
.insn_mo
);
3403 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
3404 assert (strcmp (fmt
, insn
.insn_mo
->args
) == 0);
3406 insn
.insn_opcode
= insn
.insn_mo
->match
| (regnum
<< OP_SH_RT
);
3407 if (*r
== BFD_RELOC_UNUSED
)
3409 insn
.insn_opcode
|= high_expr
.X_add_number
;
3410 append_insn (&insn
, NULL
, r
);
3413 append_insn (&insn
, &high_expr
, r
);
3416 /* Generate a sequence of instructions to do a load or store from a constant
3417 offset off of a base register (breg) into/from a target register (treg),
3418 using AT if necessary. */
3420 macro_build_ldst_constoffset (expressionS
*ep
, const char *op
,
3421 int treg
, int breg
, int dbl
)
3423 assert (ep
->X_op
== O_constant
);
3425 /* Sign-extending 32-bit constants makes their handling easier. */
3426 if (! dbl
&& ! ((ep
->X_add_number
& ~((bfd_vma
) 0x7fffffff))
3427 == ~((bfd_vma
) 0x7fffffff)))
3429 if (ep
->X_add_number
& ~((bfd_vma
) 0xffffffff))
3430 as_bad (_("constant too large"));
3432 ep
->X_add_number
= (((ep
->X_add_number
& 0xffffffff) ^ 0x80000000)
3436 /* Right now, this routine can only handle signed 32-bit constants. */
3437 if (! IS_SEXT_32BIT_NUM(ep
->X_add_number
+ 0x8000))
3438 as_warn (_("operand overflow"));
3440 if (IS_SEXT_16BIT_NUM(ep
->X_add_number
))
3442 /* Signed 16-bit offset will fit in the op. Easy! */
3443 macro_build (ep
, op
, "t,o(b)", treg
, BFD_RELOC_LO16
, breg
);
3447 /* 32-bit offset, need multiple instructions and AT, like:
3448 lui $tempreg,const_hi (BFD_RELOC_HI16_S)
3449 addu $tempreg,$tempreg,$breg
3450 <op> $treg,const_lo($tempreg) (BFD_RELOC_LO16)
3451 to handle the complete offset. */
3452 macro_build_lui (ep
, AT
);
3453 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, AT
, breg
);
3454 macro_build (ep
, op
, "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
3457 as_bad (_("Macro used $at after \".set noat\""));
3462 * Generates code to set the $at register to true (one)
3463 * if reg is less than the immediate expression.
3466 set_at (int reg
, int unsignedp
)
3468 if (imm_expr
.X_op
== O_constant
3469 && imm_expr
.X_add_number
>= -0x8000
3470 && imm_expr
.X_add_number
< 0x8000)
3471 macro_build (&imm_expr
, unsignedp
? "sltiu" : "slti", "t,r,j",
3472 AT
, reg
, BFD_RELOC_LO16
);
3475 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
3476 macro_build (NULL
, unsignedp
? "sltu" : "slt", "d,v,t", AT
, reg
, AT
);
3481 normalize_constant_expr (expressionS
*ex
)
3483 if (ex
->X_op
== O_constant
&& HAVE_32BIT_GPRS
)
3484 ex
->X_add_number
= (((ex
->X_add_number
& 0xffffffff) ^ 0x80000000)
3488 /* Warn if an expression is not a constant. */
3491 check_absolute_expr (struct mips_cl_insn
*ip
, expressionS
*ex
)
3493 if (ex
->X_op
== O_big
)
3494 as_bad (_("unsupported large constant"));
3495 else if (ex
->X_op
!= O_constant
)
3496 as_bad (_("Instruction %s requires absolute expression"), ip
->insn_mo
->name
);
3498 normalize_constant_expr (ex
);
3501 /* Count the leading zeroes by performing a binary chop. This is a
3502 bulky bit of source, but performance is a LOT better for the
3503 majority of values than a simple loop to count the bits:
3504 for (lcnt = 0; (lcnt < 32); lcnt++)
3505 if ((v) & (1 << (31 - lcnt)))
3507 However it is not code size friendly, and the gain will drop a bit
3508 on certain cached systems.
3510 #define COUNT_TOP_ZEROES(v) \
3511 (((v) & ~0xffff) == 0 \
3512 ? ((v) & ~0xff) == 0 \
3513 ? ((v) & ~0xf) == 0 \
3514 ? ((v) & ~0x3) == 0 \
3515 ? ((v) & ~0x1) == 0 \
3520 : ((v) & ~0x7) == 0 \
3523 : ((v) & ~0x3f) == 0 \
3524 ? ((v) & ~0x1f) == 0 \
3527 : ((v) & ~0x7f) == 0 \
3530 : ((v) & ~0xfff) == 0 \
3531 ? ((v) & ~0x3ff) == 0 \
3532 ? ((v) & ~0x1ff) == 0 \
3535 : ((v) & ~0x7ff) == 0 \
3538 : ((v) & ~0x3fff) == 0 \
3539 ? ((v) & ~0x1fff) == 0 \
3542 : ((v) & ~0x7fff) == 0 \
3545 : ((v) & ~0xffffff) == 0 \
3546 ? ((v) & ~0xfffff) == 0 \
3547 ? ((v) & ~0x3ffff) == 0 \
3548 ? ((v) & ~0x1ffff) == 0 \
3551 : ((v) & ~0x7ffff) == 0 \
3554 : ((v) & ~0x3fffff) == 0 \
3555 ? ((v) & ~0x1fffff) == 0 \
3558 : ((v) & ~0x7fffff) == 0 \
3561 : ((v) & ~0xfffffff) == 0 \
3562 ? ((v) & ~0x3ffffff) == 0 \
3563 ? ((v) & ~0x1ffffff) == 0 \
3566 : ((v) & ~0x7ffffff) == 0 \
3569 : ((v) & ~0x3fffffff) == 0 \
3570 ? ((v) & ~0x1fffffff) == 0 \
3573 : ((v) & ~0x7fffffff) == 0 \
3578 * This routine generates the least number of instructions necessary to load
3579 * an absolute expression value into a register.
3582 load_register (int reg
, expressionS
*ep
, int dbl
)
3585 expressionS hi32
, lo32
;
3587 if (ep
->X_op
!= O_big
)
3589 assert (ep
->X_op
== O_constant
);
3591 /* Sign-extending 32-bit constants makes their handling easier. */
3592 if (! dbl
&& ! ((ep
->X_add_number
& ~((bfd_vma
) 0x7fffffff))
3593 == ~((bfd_vma
) 0x7fffffff)))
3595 if (ep
->X_add_number
& ~((bfd_vma
) 0xffffffff))
3596 as_bad (_("constant too large"));
3598 ep
->X_add_number
= (((ep
->X_add_number
& 0xffffffff) ^ 0x80000000)
3602 if (IS_SEXT_16BIT_NUM (ep
->X_add_number
))
3604 /* We can handle 16 bit signed values with an addiu to
3605 $zero. No need to ever use daddiu here, since $zero and
3606 the result are always correct in 32 bit mode. */
3607 macro_build (ep
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
3610 else if (ep
->X_add_number
>= 0 && ep
->X_add_number
< 0x10000)
3612 /* We can handle 16 bit unsigned values with an ori to
3614 macro_build (ep
, "ori", "t,r,i", reg
, 0, BFD_RELOC_LO16
);
3617 else if ((IS_SEXT_32BIT_NUM (ep
->X_add_number
)))
3619 /* 32 bit values require an lui. */
3620 macro_build (ep
, "lui", "t,u", reg
, BFD_RELOC_HI16
);
3621 if ((ep
->X_add_number
& 0xffff) != 0)
3622 macro_build (ep
, "ori", "t,r,i", reg
, reg
, BFD_RELOC_LO16
);
3627 /* The value is larger than 32 bits. */
3629 if (HAVE_32BIT_GPRS
)
3631 as_bad (_("Number (0x%lx) larger than 32 bits"),
3632 (unsigned long) ep
->X_add_number
);
3633 macro_build (ep
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
3637 if (ep
->X_op
!= O_big
)
3640 hi32
.X_add_number
= (valueT
) hi32
.X_add_number
>> 16;
3641 hi32
.X_add_number
= (valueT
) hi32
.X_add_number
>> 16;
3642 hi32
.X_add_number
&= 0xffffffff;
3644 lo32
.X_add_number
&= 0xffffffff;
3648 assert (ep
->X_add_number
> 2);
3649 if (ep
->X_add_number
== 3)
3650 generic_bignum
[3] = 0;
3651 else if (ep
->X_add_number
> 4)
3652 as_bad (_("Number larger than 64 bits"));
3653 lo32
.X_op
= O_constant
;
3654 lo32
.X_add_number
= generic_bignum
[0] + (generic_bignum
[1] << 16);
3655 hi32
.X_op
= O_constant
;
3656 hi32
.X_add_number
= generic_bignum
[2] + (generic_bignum
[3] << 16);
3659 if (hi32
.X_add_number
== 0)
3664 unsigned long hi
, lo
;
3666 if (hi32
.X_add_number
== (offsetT
) 0xffffffff)
3668 if ((lo32
.X_add_number
& 0xffff8000) == 0xffff8000)
3670 macro_build (&lo32
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
3673 if (lo32
.X_add_number
& 0x80000000)
3675 macro_build (&lo32
, "lui", "t,u", reg
, BFD_RELOC_HI16
);
3676 if (lo32
.X_add_number
& 0xffff)
3677 macro_build (&lo32
, "ori", "t,r,i", reg
, reg
, BFD_RELOC_LO16
);
3682 /* Check for 16bit shifted constant. We know that hi32 is
3683 non-zero, so start the mask on the first bit of the hi32
3688 unsigned long himask
, lomask
;
3692 himask
= 0xffff >> (32 - shift
);
3693 lomask
= (0xffff << shift
) & 0xffffffff;
3697 himask
= 0xffff << (shift
- 32);
3700 if ((hi32
.X_add_number
& ~(offsetT
) himask
) == 0
3701 && (lo32
.X_add_number
& ~(offsetT
) lomask
) == 0)
3705 tmp
.X_op
= O_constant
;
3707 tmp
.X_add_number
= ((hi32
.X_add_number
<< (32 - shift
))
3708 | (lo32
.X_add_number
>> shift
));
3710 tmp
.X_add_number
= hi32
.X_add_number
>> (shift
- 32);
3711 macro_build (&tmp
, "ori", "t,r,i", reg
, 0, BFD_RELOC_LO16
);
3712 macro_build (NULL
, (shift
>= 32) ? "dsll32" : "dsll", "d,w,<",
3713 reg
, reg
, (shift
>= 32) ? shift
- 32 : shift
);
3718 while (shift
<= (64 - 16));
3720 /* Find the bit number of the lowest one bit, and store the
3721 shifted value in hi/lo. */
3722 hi
= (unsigned long) (hi32
.X_add_number
& 0xffffffff);
3723 lo
= (unsigned long) (lo32
.X_add_number
& 0xffffffff);
3727 while ((lo
& 1) == 0)
3732 lo
|= (hi
& (((unsigned long) 1 << bit
) - 1)) << (32 - bit
);
3738 while ((hi
& 1) == 0)
3747 /* Optimize if the shifted value is a (power of 2) - 1. */
3748 if ((hi
== 0 && ((lo
+ 1) & lo
) == 0)
3749 || (lo
== 0xffffffff && ((hi
+ 1) & hi
) == 0))
3751 shift
= COUNT_TOP_ZEROES ((unsigned int) hi32
.X_add_number
);
3756 /* This instruction will set the register to be all
3758 tmp
.X_op
= O_constant
;
3759 tmp
.X_add_number
= (offsetT
) -1;
3760 macro_build (&tmp
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
3764 macro_build (NULL
, (bit
>= 32) ? "dsll32" : "dsll", "d,w,<",
3765 reg
, reg
, (bit
>= 32) ? bit
- 32 : bit
);
3767 macro_build (NULL
, (shift
>= 32) ? "dsrl32" : "dsrl", "d,w,<",
3768 reg
, reg
, (shift
>= 32) ? shift
- 32 : shift
);
3773 /* Sign extend hi32 before calling load_register, because we can
3774 generally get better code when we load a sign extended value. */
3775 if ((hi32
.X_add_number
& 0x80000000) != 0)
3776 hi32
.X_add_number
|= ~(offsetT
) 0xffffffff;
3777 load_register (reg
, &hi32
, 0);
3780 if ((lo32
.X_add_number
& 0xffff0000) == 0)
3784 macro_build (NULL
, "dsll32", "d,w,<", reg
, freg
, 0);
3792 if ((freg
== 0) && (lo32
.X_add_number
== (offsetT
) 0xffffffff))
3794 macro_build (&lo32
, "lui", "t,u", reg
, BFD_RELOC_HI16
);
3795 macro_build (NULL
, "dsrl32", "d,w,<", reg
, reg
, 0);
3801 macro_build (NULL
, "dsll", "d,w,<", reg
, freg
, 16);
3805 mid16
.X_add_number
>>= 16;
3806 macro_build (&mid16
, "ori", "t,r,i", reg
, freg
, BFD_RELOC_LO16
);
3807 macro_build (NULL
, "dsll", "d,w,<", reg
, reg
, 16);
3810 if ((lo32
.X_add_number
& 0xffff) != 0)
3811 macro_build (&lo32
, "ori", "t,r,i", reg
, freg
, BFD_RELOC_LO16
);
3815 load_delay_nop (void)
3817 if (!gpr_interlocks
)
3818 macro_build (NULL
, "nop", "");
3821 /* Load an address into a register. */
3824 load_address (int reg
, expressionS
*ep
, int *used_at
)
3826 if (ep
->X_op
!= O_constant
3827 && ep
->X_op
!= O_symbol
)
3829 as_bad (_("expression too complex"));
3830 ep
->X_op
= O_constant
;
3833 if (ep
->X_op
== O_constant
)
3835 load_register (reg
, ep
, HAVE_64BIT_ADDRESSES
);
3839 if (mips_pic
== NO_PIC
)
3841 /* If this is a reference to a GP relative symbol, we want
3842 addiu $reg,$gp,<sym> (BFD_RELOC_GPREL16)
3844 lui $reg,<sym> (BFD_RELOC_HI16_S)
3845 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
3846 If we have an addend, we always use the latter form.
3848 With 64bit address space and a usable $at we want
3849 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
3850 lui $at,<sym> (BFD_RELOC_HI16_S)
3851 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
3852 daddiu $at,<sym> (BFD_RELOC_LO16)
3856 If $at is already in use, we use a path which is suboptimal
3857 on superscalar processors.
3858 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
3859 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
3861 daddiu $reg,<sym> (BFD_RELOC_HI16_S)
3863 daddiu $reg,<sym> (BFD_RELOC_LO16)
3865 For GP relative symbols in 64bit address space we can use
3866 the same sequence as in 32bit address space. */
3867 if (HAVE_64BIT_ADDRESSES
)
3869 if ((valueT
) ep
->X_add_number
<= MAX_GPREL_OFFSET
3870 && !nopic_need_relax (ep
->X_add_symbol
, 1))
3872 relax_start (ep
->X_add_symbol
);
3873 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
,
3874 mips_gp_register
, BFD_RELOC_GPREL16
);
3878 if (*used_at
== 0 && !mips_opts
.noat
)
3880 macro_build (ep
, "lui", "t,u", reg
, BFD_RELOC_MIPS_HIGHEST
);
3881 macro_build (ep
, "lui", "t,u", AT
, BFD_RELOC_HI16_S
);
3882 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
,
3883 BFD_RELOC_MIPS_HIGHER
);
3884 macro_build (ep
, "daddiu", "t,r,j", AT
, AT
, BFD_RELOC_LO16
);
3885 macro_build (NULL
, "dsll32", "d,w,<", reg
, reg
, 0);
3886 macro_build (NULL
, "daddu", "d,v,t", reg
, reg
, AT
);
3891 macro_build (ep
, "lui", "t,u", reg
, BFD_RELOC_MIPS_HIGHEST
);
3892 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
,
3893 BFD_RELOC_MIPS_HIGHER
);
3894 macro_build (NULL
, "dsll", "d,w,<", reg
, reg
, 16);
3895 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
, BFD_RELOC_HI16_S
);
3896 macro_build (NULL
, "dsll", "d,w,<", reg
, reg
, 16);
3897 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
, BFD_RELOC_LO16
);
3900 if (mips_relax
.sequence
)
3905 if ((valueT
) ep
->X_add_number
<= MAX_GPREL_OFFSET
3906 && !nopic_need_relax (ep
->X_add_symbol
, 1))
3908 relax_start (ep
->X_add_symbol
);
3909 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
,
3910 mips_gp_register
, BFD_RELOC_GPREL16
);
3913 macro_build_lui (ep
, reg
);
3914 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j",
3915 reg
, reg
, BFD_RELOC_LO16
);
3916 if (mips_relax
.sequence
)
3920 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
3924 /* If this is a reference to an external symbol, we want
3925 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3927 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3929 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
3930 If there is a constant, it must be added in after.
3932 If we have NewABI, we want
3933 lw $reg,<sym+cst>($gp) (BFD_RELOC_MIPS_GOT_DISP)
3934 unless we're referencing a global symbol with a non-zero
3935 offset, in which case cst must be added separately. */
3938 if (ep
->X_add_number
)
3940 ex
.X_add_number
= ep
->X_add_number
;
3941 ep
->X_add_number
= 0;
3942 relax_start (ep
->X_add_symbol
);
3943 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
3944 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
3945 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
3946 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
3947 ex
.X_op
= O_constant
;
3948 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j",
3949 reg
, reg
, BFD_RELOC_LO16
);
3950 ep
->X_add_number
= ex
.X_add_number
;
3953 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
3954 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
3955 if (mips_relax
.sequence
)
3960 ex
.X_add_number
= ep
->X_add_number
;
3961 ep
->X_add_number
= 0;
3962 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
3963 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
3965 relax_start (ep
->X_add_symbol
);
3967 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
3971 if (ex
.X_add_number
!= 0)
3973 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
3974 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
3975 ex
.X_op
= O_constant
;
3976 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j",
3977 reg
, reg
, BFD_RELOC_LO16
);
3981 else if (mips_pic
== SVR4_PIC
)
3985 /* This is the large GOT case. If this is a reference to an
3986 external symbol, we want
3987 lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
3989 lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16)
3991 Otherwise, for a reference to a local symbol in old ABI, we want
3992 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3994 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
3995 If there is a constant, it must be added in after.
3997 In the NewABI, for local symbols, with or without offsets, we want:
3998 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
3999 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
4003 ex
.X_add_number
= ep
->X_add_number
;
4004 ep
->X_add_number
= 0;
4005 relax_start (ep
->X_add_symbol
);
4006 macro_build (ep
, "lui", "t,u", reg
, BFD_RELOC_MIPS_GOT_HI16
);
4007 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
4008 reg
, reg
, mips_gp_register
);
4009 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)",
4010 reg
, BFD_RELOC_MIPS_GOT_LO16
, reg
);
4011 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
4012 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
4013 else if (ex
.X_add_number
)
4015 ex
.X_op
= O_constant
;
4016 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
4020 ep
->X_add_number
= ex
.X_add_number
;
4022 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
4023 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
4024 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
4025 BFD_RELOC_MIPS_GOT_OFST
);
4030 ex
.X_add_number
= ep
->X_add_number
;
4031 ep
->X_add_number
= 0;
4032 relax_start (ep
->X_add_symbol
);
4033 macro_build (ep
, "lui", "t,u", reg
, BFD_RELOC_MIPS_GOT_HI16
);
4034 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
4035 reg
, reg
, mips_gp_register
);
4036 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)",
4037 reg
, BFD_RELOC_MIPS_GOT_LO16
, reg
);
4039 if (reg_needs_delay (mips_gp_register
))
4041 /* We need a nop before loading from $gp. This special
4042 check is required because the lui which starts the main
4043 instruction stream does not refer to $gp, and so will not
4044 insert the nop which may be required. */
4045 macro_build (NULL
, "nop", "");
4047 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
4048 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
4050 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
4054 if (ex
.X_add_number
!= 0)
4056 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
4057 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
4058 ex
.X_op
= O_constant
;
4059 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
4067 if (mips_opts
.noat
&& *used_at
== 1)
4068 as_bad (_("Macro used $at after \".set noat\""));
4071 /* Move the contents of register SOURCE into register DEST. */
4074 move_register (int dest
, int source
)
4076 macro_build (NULL
, HAVE_32BIT_GPRS
? "addu" : "daddu", "d,v,t",
4080 /* Emit an SVR4 PIC sequence to load address LOCAL into DEST, where
4081 LOCAL is the sum of a symbol and a 16-bit or 32-bit displacement.
4082 The two alternatives are:
4084 Global symbol Local sybmol
4085 ------------- ------------
4086 lw DEST,%got(SYMBOL) lw DEST,%got(SYMBOL + OFFSET)
4088 addiu DEST,DEST,OFFSET addiu DEST,DEST,%lo(SYMBOL + OFFSET)
4090 load_got_offset emits the first instruction and add_got_offset
4091 emits the second for a 16-bit offset or add_got_offset_hilo emits
4092 a sequence to add a 32-bit offset using a scratch register. */
4095 load_got_offset (int dest
, expressionS
*local
)
4100 global
.X_add_number
= 0;
4102 relax_start (local
->X_add_symbol
);
4103 macro_build (&global
, ADDRESS_LOAD_INSN
, "t,o(b)", dest
,
4104 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
4106 macro_build (local
, ADDRESS_LOAD_INSN
, "t,o(b)", dest
,
4107 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
4112 add_got_offset (int dest
, expressionS
*local
)
4116 global
.X_op
= O_constant
;
4117 global
.X_op_symbol
= NULL
;
4118 global
.X_add_symbol
= NULL
;
4119 global
.X_add_number
= local
->X_add_number
;
4121 relax_start (local
->X_add_symbol
);
4122 macro_build (&global
, ADDRESS_ADDI_INSN
, "t,r,j",
4123 dest
, dest
, BFD_RELOC_LO16
);
4125 macro_build (local
, ADDRESS_ADDI_INSN
, "t,r,j", dest
, dest
, BFD_RELOC_LO16
);
4130 add_got_offset_hilo (int dest
, expressionS
*local
, int tmp
)
4133 int hold_mips_optimize
;
4135 global
.X_op
= O_constant
;
4136 global
.X_op_symbol
= NULL
;
4137 global
.X_add_symbol
= NULL
;
4138 global
.X_add_number
= local
->X_add_number
;
4140 relax_start (local
->X_add_symbol
);
4141 load_register (tmp
, &global
, HAVE_64BIT_ADDRESSES
);
4143 /* Set mips_optimize around the lui instruction to avoid
4144 inserting an unnecessary nop after the lw. */
4145 hold_mips_optimize
= mips_optimize
;
4147 macro_build_lui (&global
, tmp
);
4148 mips_optimize
= hold_mips_optimize
;
4149 macro_build (local
, ADDRESS_ADDI_INSN
, "t,r,j", tmp
, tmp
, BFD_RELOC_LO16
);
4152 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", dest
, dest
, tmp
);
4157 * This routine implements the seemingly endless macro or synthesized
4158 * instructions and addressing modes in the mips assembly language. Many
4159 * of these macros are simple and are similar to each other. These could
4160 * probably be handled by some kind of table or grammar approach instead of
4161 * this verbose method. Others are not simple macros but are more like
4162 * optimizing code generation.
4163 * One interesting optimization is when several store macros appear
4164 * consecutively that would load AT with the upper half of the same address.
4165 * The ensuing load upper instructions are ommited. This implies some kind
4166 * of global optimization. We currently only optimize within a single macro.
4167 * For many of the load and store macros if the address is specified as a
4168 * constant expression in the first 64k of memory (ie ld $2,0x4000c) we
4169 * first load register 'at' with zero and use it as the base register. The
4170 * mips assembler simply uses register $zero. Just one tiny optimization
4174 macro (struct mips_cl_insn
*ip
)
4176 register int treg
, sreg
, dreg
, breg
;
4192 bfd_reloc_code_real_type r
;
4193 int hold_mips_optimize
;
4195 assert (! mips_opts
.mips16
);
4197 treg
= (ip
->insn_opcode
>> 16) & 0x1f;
4198 dreg
= (ip
->insn_opcode
>> 11) & 0x1f;
4199 sreg
= breg
= (ip
->insn_opcode
>> 21) & 0x1f;
4200 mask
= ip
->insn_mo
->mask
;
4202 expr1
.X_op
= O_constant
;
4203 expr1
.X_op_symbol
= NULL
;
4204 expr1
.X_add_symbol
= NULL
;
4205 expr1
.X_add_number
= 1;
4217 mips_emit_delays (TRUE
);
4218 ++mips_opts
.noreorder
;
4219 mips_any_noreorder
= 1;
4221 expr1
.X_add_number
= 8;
4222 macro_build (&expr1
, "bgez", "s,p", sreg
);
4224 macro_build (NULL
, "nop", "", 0);
4226 move_register (dreg
, sreg
);
4227 macro_build (NULL
, dbl
? "dsub" : "sub", "d,v,t", dreg
, 0, sreg
);
4229 --mips_opts
.noreorder
;
4250 if (imm_expr
.X_op
== O_constant
4251 && imm_expr
.X_add_number
>= -0x8000
4252 && imm_expr
.X_add_number
< 0x8000)
4254 macro_build (&imm_expr
, s
, "t,r,j", treg
, sreg
, BFD_RELOC_LO16
);
4258 load_register (AT
, &imm_expr
, dbl
);
4259 macro_build (NULL
, s2
, "d,v,t", treg
, sreg
, AT
);
4278 if (imm_expr
.X_op
== O_constant
4279 && imm_expr
.X_add_number
>= 0
4280 && imm_expr
.X_add_number
< 0x10000)
4282 if (mask
!= M_NOR_I
)
4283 macro_build (&imm_expr
, s
, "t,r,i", treg
, sreg
, BFD_RELOC_LO16
);
4286 macro_build (&imm_expr
, "ori", "t,r,i",
4287 treg
, sreg
, BFD_RELOC_LO16
);
4288 macro_build (NULL
, "nor", "d,v,t", treg
, treg
, 0);
4294 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
4295 macro_build (NULL
, s2
, "d,v,t", treg
, sreg
, AT
);
4312 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
4314 macro_build (&offset_expr
, s
, "s,t,p", sreg
, 0);
4318 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
4319 macro_build (&offset_expr
, s
, "s,t,p", sreg
, AT
);
4327 macro_build (&offset_expr
, likely
? "bgezl" : "bgez", "s,p", sreg
);
4332 macro_build (&offset_expr
, likely
? "blezl" : "blez", "s,p", treg
);
4336 macro_build (NULL
, "slt", "d,v,t", AT
, sreg
, treg
);
4337 macro_build (&offset_expr
, likely
? "beql" : "beq", "s,t,p", AT
, 0);
4343 /* check for > max integer */
4344 maxnum
= 0x7fffffff;
4345 if (HAVE_64BIT_GPRS
&& sizeof (maxnum
) > 4)
4352 if (imm_expr
.X_op
== O_constant
4353 && imm_expr
.X_add_number
>= maxnum
4354 && (HAVE_32BIT_GPRS
|| sizeof (maxnum
) > 4))
4357 /* result is always false */
4359 macro_build (NULL
, "nop", "", 0);
4361 macro_build (&offset_expr
, "bnel", "s,t,p", 0, 0);
4364 if (imm_expr
.X_op
!= O_constant
)
4365 as_bad (_("Unsupported large constant"));
4366 ++imm_expr
.X_add_number
;
4370 if (mask
== M_BGEL_I
)
4372 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
4374 macro_build (&offset_expr
, likely
? "bgezl" : "bgez", "s,p", sreg
);
4377 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
4379 macro_build (&offset_expr
, likely
? "bgtzl" : "bgtz", "s,p", sreg
);
4382 maxnum
= 0x7fffffff;
4383 if (HAVE_64BIT_GPRS
&& sizeof (maxnum
) > 4)
4390 maxnum
= - maxnum
- 1;
4391 if (imm_expr
.X_op
== O_constant
4392 && imm_expr
.X_add_number
<= maxnum
4393 && (HAVE_32BIT_GPRS
|| sizeof (maxnum
) > 4))
4396 /* result is always true */
4397 as_warn (_("Branch %s is always true"), ip
->insn_mo
->name
);
4398 macro_build (&offset_expr
, "b", "p");
4403 macro_build (&offset_expr
, likely
? "beql" : "beq", "s,t,p", AT
, 0);
4413 macro_build (&offset_expr
, likely
? "beql" : "beq",
4418 macro_build (NULL
, "sltu", "d,v,t", AT
, sreg
, treg
);
4419 macro_build (&offset_expr
, likely
? "beql" : "beq", "s,t,p", AT
, 0);
4427 && imm_expr
.X_op
== O_constant
4428 && imm_expr
.X_add_number
== (offsetT
) 0xffffffff))
4430 if (imm_expr
.X_op
!= O_constant
)
4431 as_bad (_("Unsupported large constant"));
4432 ++imm_expr
.X_add_number
;
4436 if (mask
== M_BGEUL_I
)
4438 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
4440 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
4442 macro_build (&offset_expr
, likely
? "bnel" : "bne",
4448 macro_build (&offset_expr
, likely
? "beql" : "beq", "s,t,p", AT
, 0);
4456 macro_build (&offset_expr
, likely
? "bgtzl" : "bgtz", "s,p", sreg
);
4461 macro_build (&offset_expr
, likely
? "bltzl" : "bltz", "s,p", treg
);
4465 macro_build (NULL
, "slt", "d,v,t", AT
, treg
, sreg
);
4466 macro_build (&offset_expr
, likely
? "bnel" : "bne", "s,t,p", AT
, 0);
4474 macro_build (&offset_expr
, likely
? "bnel" : "bne",
4481 macro_build (NULL
, "sltu", "d,v,t", AT
, treg
, sreg
);
4482 macro_build (&offset_expr
, likely
? "bnel" : "bne", "s,t,p", AT
, 0);
4490 macro_build (&offset_expr
, likely
? "blezl" : "blez", "s,p", sreg
);
4495 macro_build (&offset_expr
, likely
? "bgezl" : "bgez", "s,p", treg
);
4499 macro_build (NULL
, "slt", "d,v,t", AT
, treg
, sreg
);
4500 macro_build (&offset_expr
, likely
? "beql" : "beq", "s,t,p", AT
, 0);
4506 maxnum
= 0x7fffffff;
4507 if (HAVE_64BIT_GPRS
&& sizeof (maxnum
) > 4)
4514 if (imm_expr
.X_op
== O_constant
4515 && imm_expr
.X_add_number
>= maxnum
4516 && (HAVE_32BIT_GPRS
|| sizeof (maxnum
) > 4))
4518 if (imm_expr
.X_op
!= O_constant
)
4519 as_bad (_("Unsupported large constant"));
4520 ++imm_expr
.X_add_number
;
4524 if (mask
== M_BLTL_I
)
4526 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
4528 macro_build (&offset_expr
, likely
? "bltzl" : "bltz", "s,p", sreg
);
4531 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
4533 macro_build (&offset_expr
, likely
? "blezl" : "blez", "s,p", sreg
);
4538 macro_build (&offset_expr
, likely
? "bnel" : "bne", "s,t,p", AT
, 0);
4546 macro_build (&offset_expr
, likely
? "beql" : "beq",
4553 macro_build (NULL
, "sltu", "d,v,t", AT
, treg
, sreg
);
4554 macro_build (&offset_expr
, likely
? "beql" : "beq", "s,t,p", AT
, 0);
4562 && imm_expr
.X_op
== O_constant
4563 && imm_expr
.X_add_number
== (offsetT
) 0xffffffff))
4565 if (imm_expr
.X_op
!= O_constant
)
4566 as_bad (_("Unsupported large constant"));
4567 ++imm_expr
.X_add_number
;
4571 if (mask
== M_BLTUL_I
)
4573 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
4575 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
4577 macro_build (&offset_expr
, likely
? "beql" : "beq",
4583 macro_build (&offset_expr
, likely
? "bnel" : "bne", "s,t,p", AT
, 0);
4591 macro_build (&offset_expr
, likely
? "bltzl" : "bltz", "s,p", sreg
);
4596 macro_build (&offset_expr
, likely
? "bgtzl" : "bgtz", "s,p", treg
);
4600 macro_build (NULL
, "slt", "d,v,t", AT
, sreg
, treg
);
4601 macro_build (&offset_expr
, likely
? "bnel" : "bne", "s,t,p", AT
, 0);
4611 macro_build (&offset_expr
, likely
? "bnel" : "bne",
4616 macro_build (NULL
, "sltu", "d,v,t", AT
, sreg
, treg
);
4617 macro_build (&offset_expr
, likely
? "bnel" : "bne", "s,t,p", AT
, 0);
4625 if (imm_expr
.X_op
!= O_constant
|| imm2_expr
.X_op
!= O_constant
)
4627 as_bad (_("Unsupported large constant"));
4632 pos
= (unsigned long) imm_expr
.X_add_number
;
4633 size
= (unsigned long) imm2_expr
.X_add_number
;
4638 as_bad (_("Improper position (%lu)"), pos
);
4641 if (size
== 0 || size
> 64
4642 || (pos
+ size
- 1) > 63)
4644 as_bad (_("Improper extract size (%lu, position %lu)"),
4649 if (size
<= 32 && pos
< 32)
4654 else if (size
<= 32)
4664 macro_build ((expressionS
*) NULL
, s
, fmt
, treg
, sreg
, pos
, size
- 1);
4673 if (imm_expr
.X_op
!= O_constant
|| imm2_expr
.X_op
!= O_constant
)
4675 as_bad (_("Unsupported large constant"));
4680 pos
= (unsigned long) imm_expr
.X_add_number
;
4681 size
= (unsigned long) imm2_expr
.X_add_number
;
4686 as_bad (_("Improper position (%lu)"), pos
);
4689 if (size
== 0 || size
> 64
4690 || (pos
+ size
- 1) > 63)
4692 as_bad (_("Improper insert size (%lu, position %lu)"),
4697 if (pos
< 32 && (pos
+ size
- 1) < 32)
4712 macro_build ((expressionS
*) NULL
, s
, fmt
, treg
, sreg
, pos
,
4729 as_warn (_("Divide by zero."));
4731 macro_build (NULL
, "teq", "s,t,q", 0, 0, 7);
4733 macro_build (NULL
, "break", "c", 7);
4737 mips_emit_delays (TRUE
);
4738 ++mips_opts
.noreorder
;
4739 mips_any_noreorder
= 1;
4742 macro_build (NULL
, "teq", "s,t,q", treg
, 0, 7);
4743 macro_build (NULL
, dbl
? "ddiv" : "div", "z,s,t", sreg
, treg
);
4747 expr1
.X_add_number
= 8;
4748 macro_build (&expr1
, "bne", "s,t,p", treg
, 0);
4749 macro_build (NULL
, dbl
? "ddiv" : "div", "z,s,t", sreg
, treg
);
4750 macro_build (NULL
, "break", "c", 7);
4752 expr1
.X_add_number
= -1;
4754 load_register (AT
, &expr1
, dbl
);
4755 expr1
.X_add_number
= mips_trap
? (dbl
? 12 : 8) : (dbl
? 20 : 16);
4756 macro_build (&expr1
, "bne", "s,t,p", treg
, AT
);
4759 expr1
.X_add_number
= 1;
4760 load_register (AT
, &expr1
, dbl
);
4761 macro_build (NULL
, "dsll32", "d,w,<", AT
, AT
, 31);
4765 expr1
.X_add_number
= 0x80000000;
4766 macro_build (&expr1
, "lui", "t,u", AT
, BFD_RELOC_HI16
);
4770 macro_build (NULL
, "teq", "s,t,q", sreg
, AT
, 6);
4771 /* We want to close the noreorder block as soon as possible, so
4772 that later insns are available for delay slot filling. */
4773 --mips_opts
.noreorder
;
4777 expr1
.X_add_number
= 8;
4778 macro_build (&expr1
, "bne", "s,t,p", sreg
, AT
);
4779 macro_build (NULL
, "nop", "", 0);
4781 /* We want to close the noreorder block as soon as possible, so
4782 that later insns are available for delay slot filling. */
4783 --mips_opts
.noreorder
;
4785 macro_build (NULL
, "break", "c", 6);
4787 macro_build (NULL
, s
, "d", dreg
);
4826 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
4828 as_warn (_("Divide by zero."));
4830 macro_build (NULL
, "teq", "s,t,q", 0, 0, 7);
4832 macro_build (NULL
, "break", "c", 7);
4835 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
4837 if (strcmp (s2
, "mflo") == 0)
4838 move_register (dreg
, sreg
);
4840 move_register (dreg
, 0);
4843 if (imm_expr
.X_op
== O_constant
4844 && imm_expr
.X_add_number
== -1
4845 && s
[strlen (s
) - 1] != 'u')
4847 if (strcmp (s2
, "mflo") == 0)
4849 macro_build (NULL
, dbl
? "dneg" : "neg", "d,w", dreg
, sreg
);
4852 move_register (dreg
, 0);
4857 load_register (AT
, &imm_expr
, dbl
);
4858 macro_build (NULL
, s
, "z,s,t", sreg
, AT
);
4859 macro_build (NULL
, s2
, "d", dreg
);
4878 mips_emit_delays (TRUE
);
4879 ++mips_opts
.noreorder
;
4880 mips_any_noreorder
= 1;
4883 macro_build (NULL
, "teq", "s,t,q", treg
, 0, 7);
4884 macro_build (NULL
, s
, "z,s,t", sreg
, treg
);
4885 /* We want to close the noreorder block as soon as possible, so
4886 that later insns are available for delay slot filling. */
4887 --mips_opts
.noreorder
;
4891 expr1
.X_add_number
= 8;
4892 macro_build (&expr1
, "bne", "s,t,p", treg
, 0);
4893 macro_build (NULL
, s
, "z,s,t", sreg
, treg
);
4895 /* We want to close the noreorder block as soon as possible, so
4896 that later insns are available for delay slot filling. */
4897 --mips_opts
.noreorder
;
4898 macro_build (NULL
, "break", "c", 7);
4900 macro_build (NULL
, s2
, "d", dreg
);
4912 /* Load the address of a symbol into a register. If breg is not
4913 zero, we then add a base register to it. */
4915 if (dbl
&& HAVE_32BIT_GPRS
)
4916 as_warn (_("dla used to load 32-bit register"));
4918 if (! dbl
&& HAVE_64BIT_OBJECTS
)
4919 as_warn (_("la used to load 64-bit address"));
4921 if (offset_expr
.X_op
== O_constant
4922 && offset_expr
.X_add_number
>= -0x8000
4923 && offset_expr
.X_add_number
< 0x8000)
4925 macro_build (&offset_expr
,
4926 (dbl
|| HAVE_64BIT_ADDRESSES
) ? "daddiu" : "addiu",
4927 "t,r,j", treg
, sreg
, BFD_RELOC_LO16
);
4931 if (!mips_opts
.noat
&& (treg
== breg
))
4941 if (offset_expr
.X_op
!= O_symbol
4942 && offset_expr
.X_op
!= O_constant
)
4944 as_bad (_("expression too complex"));
4945 offset_expr
.X_op
= O_constant
;
4948 if (offset_expr
.X_op
== O_constant
)
4949 load_register (tempreg
, &offset_expr
,
4951 ? (dbl
|| HAVE_64BIT_ADDRESSES
)
4952 : HAVE_64BIT_ADDRESSES
));
4953 else if (mips_pic
== NO_PIC
)
4955 /* If this is a reference to a GP relative symbol, we want
4956 addiu $tempreg,$gp,<sym> (BFD_RELOC_GPREL16)
4958 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
4959 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
4960 If we have a constant, we need two instructions anyhow,
4961 so we may as well always use the latter form.
4963 With 64bit address space and a usable $at we want
4964 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
4965 lui $at,<sym> (BFD_RELOC_HI16_S)
4966 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
4967 daddiu $at,<sym> (BFD_RELOC_LO16)
4969 daddu $tempreg,$tempreg,$at
4971 If $at is already in use, we use a path which is suboptimal
4972 on superscalar processors.
4973 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
4974 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
4976 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
4978 daddiu $tempreg,<sym> (BFD_RELOC_LO16)
4980 For GP relative symbols in 64bit address space we can use
4981 the same sequence as in 32bit address space. */
4982 if (HAVE_64BIT_ADDRESSES
)
4984 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
4985 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
4987 relax_start (offset_expr
.X_add_symbol
);
4988 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
4989 tempreg
, mips_gp_register
, BFD_RELOC_GPREL16
);
4993 if (used_at
== 0 && !mips_opts
.noat
)
4995 macro_build (&offset_expr
, "lui", "t,u",
4996 tempreg
, BFD_RELOC_MIPS_HIGHEST
);
4997 macro_build (&offset_expr
, "lui", "t,u",
4998 AT
, BFD_RELOC_HI16_S
);
4999 macro_build (&offset_expr
, "daddiu", "t,r,j",
5000 tempreg
, tempreg
, BFD_RELOC_MIPS_HIGHER
);
5001 macro_build (&offset_expr
, "daddiu", "t,r,j",
5002 AT
, AT
, BFD_RELOC_LO16
);
5003 macro_build (NULL
, "dsll32", "d,w,<", tempreg
, tempreg
, 0);
5004 macro_build (NULL
, "daddu", "d,v,t", tempreg
, tempreg
, AT
);
5009 macro_build (&offset_expr
, "lui", "t,u",
5010 tempreg
, BFD_RELOC_MIPS_HIGHEST
);
5011 macro_build (&offset_expr
, "daddiu", "t,r,j",
5012 tempreg
, tempreg
, BFD_RELOC_MIPS_HIGHER
);
5013 macro_build (NULL
, "dsll", "d,w,<", tempreg
, tempreg
, 16);
5014 macro_build (&offset_expr
, "daddiu", "t,r,j",
5015 tempreg
, tempreg
, BFD_RELOC_HI16_S
);
5016 macro_build (NULL
, "dsll", "d,w,<", tempreg
, tempreg
, 16);
5017 macro_build (&offset_expr
, "daddiu", "t,r,j",
5018 tempreg
, tempreg
, BFD_RELOC_LO16
);
5021 if (mips_relax
.sequence
)
5026 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
5027 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
5029 relax_start (offset_expr
.X_add_symbol
);
5030 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
5031 tempreg
, mips_gp_register
, BFD_RELOC_GPREL16
);
5034 if (!IS_SEXT_32BIT_NUM (offset_expr
.X_add_number
))
5035 as_bad (_("offset too large"));
5036 macro_build_lui (&offset_expr
, tempreg
);
5037 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
5038 tempreg
, tempreg
, BFD_RELOC_LO16
);
5039 if (mips_relax
.sequence
)
5043 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
&& ! HAVE_NEWABI
)
5045 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT16
;
5047 /* If this is a reference to an external symbol, and there
5048 is no constant, we want
5049 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5050 or for lca or if tempreg is PIC_CALL_REG
5051 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
5052 For a local symbol, we want
5053 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5055 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
5057 If we have a small constant, and this is a reference to
5058 an external symbol, we want
5059 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5061 addiu $tempreg,$tempreg,<constant>
5062 For a local symbol, we want the same instruction
5063 sequence, but we output a BFD_RELOC_LO16 reloc on the
5066 If we have a large constant, and this is a reference to
5067 an external symbol, we want
5068 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5069 lui $at,<hiconstant>
5070 addiu $at,$at,<loconstant>
5071 addu $tempreg,$tempreg,$at
5072 For a local symbol, we want the same instruction
5073 sequence, but we output a BFD_RELOC_LO16 reloc on the
5077 if (offset_expr
.X_add_number
== 0)
5079 if (breg
== 0 && (call
|| tempreg
== PIC_CALL_REG
))
5080 lw_reloc_type
= (int) BFD_RELOC_MIPS_CALL16
;
5082 relax_start (offset_expr
.X_add_symbol
);
5083 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
5084 lw_reloc_type
, mips_gp_register
);
5087 /* We're going to put in an addu instruction using
5088 tempreg, so we may as well insert the nop right
5093 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
5094 tempreg
, BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
5096 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
5097 tempreg
, tempreg
, BFD_RELOC_LO16
);
5099 /* FIXME: If breg == 0, and the next instruction uses
5100 $tempreg, then if this variant case is used an extra
5101 nop will be generated. */
5103 else if (offset_expr
.X_add_number
>= -0x8000
5104 && offset_expr
.X_add_number
< 0x8000)
5106 load_got_offset (tempreg
, &offset_expr
);
5108 add_got_offset (tempreg
, &offset_expr
);
5112 expr1
.X_add_number
= offset_expr
.X_add_number
;
5113 offset_expr
.X_add_number
=
5114 ((offset_expr
.X_add_number
+ 0x8000) & 0xffff) - 0x8000;
5115 load_got_offset (tempreg
, &offset_expr
);
5116 offset_expr
.X_add_number
= expr1
.X_add_number
;
5117 /* If we are going to add in a base register, and the
5118 target register and the base register are the same,
5119 then we are using AT as a temporary register. Since
5120 we want to load the constant into AT, we add our
5121 current AT (from the global offset table) and the
5122 register into the register now, and pretend we were
5123 not using a base register. */
5127 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5132 add_got_offset_hilo (tempreg
, &offset_expr
, AT
);
5136 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
&& HAVE_NEWABI
)
5138 int add_breg_early
= 0;
5140 /* If this is a reference to an external, and there is no
5141 constant, or local symbol (*), with or without a
5143 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
5144 or for lca or if tempreg is PIC_CALL_REG
5145 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
5147 If we have a small constant, and this is a reference to
5148 an external symbol, we want
5149 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
5150 addiu $tempreg,$tempreg,<constant>
5152 If we have a large constant, and this is a reference to
5153 an external symbol, we want
5154 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
5155 lui $at,<hiconstant>
5156 addiu $at,$at,<loconstant>
5157 addu $tempreg,$tempreg,$at
5159 (*) Other assemblers seem to prefer GOT_PAGE/GOT_OFST for
5160 local symbols, even though it introduces an additional
5163 if (offset_expr
.X_add_number
)
5165 expr1
.X_add_number
= offset_expr
.X_add_number
;
5166 offset_expr
.X_add_number
= 0;
5168 relax_start (offset_expr
.X_add_symbol
);
5169 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
5170 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
5172 if (expr1
.X_add_number
>= -0x8000
5173 && expr1
.X_add_number
< 0x8000)
5175 macro_build (&expr1
, ADDRESS_ADDI_INSN
, "t,r,j",
5176 tempreg
, tempreg
, BFD_RELOC_LO16
);
5178 else if (IS_SEXT_32BIT_NUM (expr1
.X_add_number
+ 0x8000))
5182 /* If we are going to add in a base register, and the
5183 target register and the base register are the same,
5184 then we are using AT as a temporary register. Since
5185 we want to load the constant into AT, we add our
5186 current AT (from the global offset table) and the
5187 register into the register now, and pretend we were
5188 not using a base register. */
5193 assert (tempreg
== AT
);
5194 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5200 load_register (AT
, &expr1
, HAVE_64BIT_ADDRESSES
);
5201 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5207 as_bad (_("PIC code offset overflow (max 32 signed bits)"));
5210 offset_expr
.X_add_number
= expr1
.X_add_number
;
5212 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
5213 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
5216 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5217 treg
, tempreg
, breg
);
5223 else if (breg
== 0 && (call
|| tempreg
== PIC_CALL_REG
))
5225 relax_start (offset_expr
.X_add_symbol
);
5226 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
5227 BFD_RELOC_MIPS_CALL16
, mips_gp_register
);
5229 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
5230 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
5235 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
5236 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
5239 else if (mips_pic
== SVR4_PIC
&& ! HAVE_NEWABI
)
5242 int lui_reloc_type
= (int) BFD_RELOC_MIPS_GOT_HI16
;
5243 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT_LO16
;
5244 int local_reloc_type
= (int) BFD_RELOC_MIPS_GOT16
;
5246 /* This is the large GOT case. If this is a reference to an
5247 external symbol, and there is no constant, we want
5248 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5249 addu $tempreg,$tempreg,$gp
5250 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5251 or for lca or if tempreg is PIC_CALL_REG
5252 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
5253 addu $tempreg,$tempreg,$gp
5254 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
5255 For a local symbol, we want
5256 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5258 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
5260 If we have a small constant, and this is a reference to
5261 an external symbol, we want
5262 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5263 addu $tempreg,$tempreg,$gp
5264 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5266 addiu $tempreg,$tempreg,<constant>
5267 For a local symbol, we want
5268 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5270 addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16)
5272 If we have a large constant, and this is a reference to
5273 an external symbol, we want
5274 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5275 addu $tempreg,$tempreg,$gp
5276 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5277 lui $at,<hiconstant>
5278 addiu $at,$at,<loconstant>
5279 addu $tempreg,$tempreg,$at
5280 For a local symbol, we want
5281 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5282 lui $at,<hiconstant>
5283 addiu $at,$at,<loconstant> (BFD_RELOC_LO16)
5284 addu $tempreg,$tempreg,$at
5287 expr1
.X_add_number
= offset_expr
.X_add_number
;
5288 offset_expr
.X_add_number
= 0;
5289 relax_start (offset_expr
.X_add_symbol
);
5290 gpdelay
= reg_needs_delay (mips_gp_register
);
5291 if (expr1
.X_add_number
== 0 && breg
== 0
5292 && (call
|| tempreg
== PIC_CALL_REG
))
5294 lui_reloc_type
= (int) BFD_RELOC_MIPS_CALL_HI16
;
5295 lw_reloc_type
= (int) BFD_RELOC_MIPS_CALL_LO16
;
5297 macro_build (&offset_expr
, "lui", "t,u", tempreg
, lui_reloc_type
);
5298 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5299 tempreg
, tempreg
, mips_gp_register
);
5300 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
5301 tempreg
, lw_reloc_type
, tempreg
);
5302 if (expr1
.X_add_number
== 0)
5306 /* We're going to put in an addu instruction using
5307 tempreg, so we may as well insert the nop right
5312 else if (expr1
.X_add_number
>= -0x8000
5313 && expr1
.X_add_number
< 0x8000)
5316 macro_build (&expr1
, ADDRESS_ADDI_INSN
, "t,r,j",
5317 tempreg
, tempreg
, BFD_RELOC_LO16
);
5323 /* If we are going to add in a base register, and the
5324 target register and the base register are the same,
5325 then we are using AT as a temporary register. Since
5326 we want to load the constant into AT, we add our
5327 current AT (from the global offset table) and the
5328 register into the register now, and pretend we were
5329 not using a base register. */
5334 assert (tempreg
== AT
);
5336 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5341 load_register (AT
, &expr1
, HAVE_64BIT_ADDRESSES
);
5342 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", dreg
, dreg
, AT
);
5346 offset_expr
.X_add_number
=
5347 ((expr1
.X_add_number
+ 0x8000) & 0xffff) - 0x8000;
5352 /* This is needed because this instruction uses $gp, but
5353 the first instruction on the main stream does not. */
5354 macro_build (NULL
, "nop", "");
5357 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
5358 local_reloc_type
, mips_gp_register
);
5359 if (expr1
.X_add_number
>= -0x8000
5360 && expr1
.X_add_number
< 0x8000)
5363 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
5364 tempreg
, tempreg
, BFD_RELOC_LO16
);
5365 /* FIXME: If add_number is 0, and there was no base
5366 register, the external symbol case ended with a load,
5367 so if the symbol turns out to not be external, and
5368 the next instruction uses tempreg, an unnecessary nop
5369 will be inserted. */
5375 /* We must add in the base register now, as in the
5376 external symbol case. */
5377 assert (tempreg
== AT
);
5379 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5382 /* We set breg to 0 because we have arranged to add
5383 it in in both cases. */
5387 macro_build_lui (&expr1
, AT
);
5388 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
5389 AT
, AT
, BFD_RELOC_LO16
);
5390 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5391 tempreg
, tempreg
, AT
);
5396 else if (mips_pic
== SVR4_PIC
&& HAVE_NEWABI
)
5398 int lui_reloc_type
= (int) BFD_RELOC_MIPS_GOT_HI16
;
5399 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT_LO16
;
5400 int add_breg_early
= 0;
5402 /* This is the large GOT case. If this is a reference to an
5403 external symbol, and there is no constant, we want
5404 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5405 add $tempreg,$tempreg,$gp
5406 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5407 or for lca or if tempreg is PIC_CALL_REG
5408 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
5409 add $tempreg,$tempreg,$gp
5410 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
5412 If we have a small constant, and this is a reference to
5413 an external symbol, we want
5414 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5415 add $tempreg,$tempreg,$gp
5416 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5417 addi $tempreg,$tempreg,<constant>
5419 If we have a large constant, and this is a reference to
5420 an external symbol, we want
5421 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5422 addu $tempreg,$tempreg,$gp
5423 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5424 lui $at,<hiconstant>
5425 addi $at,$at,<loconstant>
5426 add $tempreg,$tempreg,$at
5428 If we have NewABI, and we know it's a local symbol, we want
5429 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
5430 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
5431 otherwise we have to resort to GOT_HI16/GOT_LO16. */
5433 relax_start (offset_expr
.X_add_symbol
);
5435 expr1
.X_add_number
= offset_expr
.X_add_number
;
5436 offset_expr
.X_add_number
= 0;
5438 if (expr1
.X_add_number
== 0 && breg
== 0
5439 && (call
|| tempreg
== PIC_CALL_REG
))
5441 lui_reloc_type
= (int) BFD_RELOC_MIPS_CALL_HI16
;
5442 lw_reloc_type
= (int) BFD_RELOC_MIPS_CALL_LO16
;
5444 macro_build (&offset_expr
, "lui", "t,u", tempreg
, lui_reloc_type
);
5445 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5446 tempreg
, tempreg
, mips_gp_register
);
5447 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
5448 tempreg
, lw_reloc_type
, tempreg
);
5450 if (expr1
.X_add_number
== 0)
5452 else if (expr1
.X_add_number
>= -0x8000
5453 && expr1
.X_add_number
< 0x8000)
5455 macro_build (&expr1
, ADDRESS_ADDI_INSN
, "t,r,j",
5456 tempreg
, tempreg
, BFD_RELOC_LO16
);
5458 else if (IS_SEXT_32BIT_NUM (expr1
.X_add_number
+ 0x8000))
5462 /* If we are going to add in a base register, and the
5463 target register and the base register are the same,
5464 then we are using AT as a temporary register. Since
5465 we want to load the constant into AT, we add our
5466 current AT (from the global offset table) and the
5467 register into the register now, and pretend we were
5468 not using a base register. */
5473 assert (tempreg
== AT
);
5474 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5480 load_register (AT
, &expr1
, HAVE_64BIT_ADDRESSES
);
5481 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", dreg
, dreg
, AT
);
5486 as_bad (_("PIC code offset overflow (max 32 signed bits)"));
5489 offset_expr
.X_add_number
= expr1
.X_add_number
;
5490 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
5491 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
5492 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j", tempreg
,
5493 tempreg
, BFD_RELOC_MIPS_GOT_OFST
);
5496 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5497 treg
, tempreg
, breg
);
5510 if (mips_pic
== NO_PIC
)
5511 s
= (dbl
|| HAVE_64BIT_ADDRESSES
) ? "daddu" : "addu";
5513 s
= ADDRESS_ADD_INSN
;
5515 macro_build (NULL
, s
, "d,v,t", treg
, tempreg
, breg
);
5520 /* The j instruction may not be used in PIC code, since it
5521 requires an absolute address. We convert it to a b
5523 if (mips_pic
== NO_PIC
)
5524 macro_build (&offset_expr
, "j", "a");
5526 macro_build (&offset_expr
, "b", "p");
5529 /* The jal instructions must be handled as macros because when
5530 generating PIC code they expand to multi-instruction
5531 sequences. Normally they are simple instructions. */
5536 if (mips_pic
== NO_PIC
)
5537 macro_build (NULL
, "jalr", "d,s", dreg
, sreg
);
5538 else if (mips_pic
== SVR4_PIC
)
5540 if (sreg
!= PIC_CALL_REG
)
5541 as_warn (_("MIPS PIC call to register other than $25"));
5543 macro_build (NULL
, "jalr", "d,s", dreg
, sreg
);
5546 if (mips_cprestore_offset
< 0)
5547 as_warn (_("No .cprestore pseudo-op used in PIC code"));
5550 if (! mips_frame_reg_valid
)
5552 as_warn (_("No .frame pseudo-op used in PIC code"));
5553 /* Quiet this warning. */
5554 mips_frame_reg_valid
= 1;
5556 if (! mips_cprestore_valid
)
5558 as_warn (_("No .cprestore pseudo-op used in PIC code"));
5559 /* Quiet this warning. */
5560 mips_cprestore_valid
= 1;
5562 expr1
.X_add_number
= mips_cprestore_offset
;
5563 macro_build_ldst_constoffset (&expr1
, ADDRESS_LOAD_INSN
,
5566 HAVE_64BIT_ADDRESSES
);
5576 if (mips_pic
== NO_PIC
)
5577 macro_build (&offset_expr
, "jal", "a");
5578 else if (mips_pic
== SVR4_PIC
)
5580 /* If this is a reference to an external symbol, and we are
5581 using a small GOT, we want
5582 lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
5586 lw $gp,cprestore($sp)
5587 The cprestore value is set using the .cprestore
5588 pseudo-op. If we are using a big GOT, we want
5589 lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16)
5591 lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16)
5595 lw $gp,cprestore($sp)
5596 If the symbol is not external, we want
5597 lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5599 addiu $25,$25,<sym> (BFD_RELOC_LO16)
5602 lw $gp,cprestore($sp)
5604 For NewABI, we use the same CALL16 or CALL_HI16/CALL_LO16
5605 sequences above, minus nops, unless the symbol is local,
5606 which enables us to use GOT_PAGE/GOT_OFST (big got) or
5612 relax_start (offset_expr
.X_add_symbol
);
5613 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
5614 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL16
,
5617 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
5618 PIC_CALL_REG
, BFD_RELOC_MIPS_GOT_DISP
,
5624 relax_start (offset_expr
.X_add_symbol
);
5625 macro_build (&offset_expr
, "lui", "t,u", PIC_CALL_REG
,
5626 BFD_RELOC_MIPS_CALL_HI16
);
5627 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", PIC_CALL_REG
,
5628 PIC_CALL_REG
, mips_gp_register
);
5629 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
5630 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL_LO16
,
5633 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
5634 PIC_CALL_REG
, BFD_RELOC_MIPS_GOT_PAGE
,
5636 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
5637 PIC_CALL_REG
, PIC_CALL_REG
,
5638 BFD_RELOC_MIPS_GOT_OFST
);
5642 macro_build_jalr (&offset_expr
);
5646 relax_start (offset_expr
.X_add_symbol
);
5649 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
5650 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL16
,
5659 gpdelay
= reg_needs_delay (mips_gp_register
);
5660 macro_build (&offset_expr
, "lui", "t,u", PIC_CALL_REG
,
5661 BFD_RELOC_MIPS_CALL_HI16
);
5662 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", PIC_CALL_REG
,
5663 PIC_CALL_REG
, mips_gp_register
);
5664 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
5665 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL_LO16
,
5670 macro_build (NULL
, "nop", "");
5672 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
5673 PIC_CALL_REG
, BFD_RELOC_MIPS_GOT16
,
5676 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
5677 PIC_CALL_REG
, PIC_CALL_REG
, BFD_RELOC_LO16
);
5679 macro_build_jalr (&offset_expr
);
5681 if (mips_cprestore_offset
< 0)
5682 as_warn (_("No .cprestore pseudo-op used in PIC code"));
5685 if (! mips_frame_reg_valid
)
5687 as_warn (_("No .frame pseudo-op used in PIC code"));
5688 /* Quiet this warning. */
5689 mips_frame_reg_valid
= 1;
5691 if (! mips_cprestore_valid
)
5693 as_warn (_("No .cprestore pseudo-op used in PIC code"));
5694 /* Quiet this warning. */
5695 mips_cprestore_valid
= 1;
5697 if (mips_opts
.noreorder
)
5698 macro_build (NULL
, "nop", "");
5699 expr1
.X_add_number
= mips_cprestore_offset
;
5700 macro_build_ldst_constoffset (&expr1
, ADDRESS_LOAD_INSN
,
5703 HAVE_64BIT_ADDRESSES
);
5729 /* Itbl support may require additional care here. */
5734 /* Itbl support may require additional care here. */
5739 /* Itbl support may require additional care here. */
5744 /* Itbl support may require additional care here. */
5756 if (mips_opts
.arch
== CPU_R4650
)
5758 as_bad (_("opcode not supported on this processor"));
5762 /* Itbl support may require additional care here. */
5767 /* Itbl support may require additional care here. */
5772 /* Itbl support may require additional care here. */
5792 if (breg
== treg
|| coproc
|| lr
)
5813 /* Itbl support may require additional care here. */
5818 /* Itbl support may require additional care here. */
5823 /* Itbl support may require additional care here. */
5828 /* Itbl support may require additional care here. */
5844 if (mips_opts
.arch
== CPU_R4650
)
5846 as_bad (_("opcode not supported on this processor"));
5851 /* Itbl support may require additional care here. */
5855 /* Itbl support may require additional care here. */
5860 /* Itbl support may require additional care here. */
5872 /* Itbl support may require additional care here. */
5873 if (mask
== M_LWC1_AB
5874 || mask
== M_SWC1_AB
5875 || mask
== M_LDC1_AB
5876 || mask
== M_SDC1_AB
5885 /* Sign-extending 32-bit constants makes their handling easier.
5886 The HAVE_64BIT_GPRS... part is due to the linux kernel hack
5888 if ((! HAVE_64BIT_ADDRESSES
5889 && (! HAVE_64BIT_GPRS
&& offset_expr
.X_op
== O_constant
))
5890 && (offset_expr
.X_op
== O_constant
)
5891 && ! ((offset_expr
.X_add_number
& ~((bfd_vma
) 0x7fffffff))
5892 == ~((bfd_vma
) 0x7fffffff)))
5894 if (offset_expr
.X_add_number
& ~((bfd_vma
) 0xffffffff))
5895 as_bad (_("constant too large"));
5897 offset_expr
.X_add_number
= (((offset_expr
.X_add_number
& 0xffffffff)
5898 ^ 0x80000000) - 0x80000000);
5901 if (offset_expr
.X_op
!= O_constant
5902 && offset_expr
.X_op
!= O_symbol
)
5904 as_bad (_("expression too complex"));
5905 offset_expr
.X_op
= O_constant
;
5908 /* A constant expression in PIC code can be handled just as it
5909 is in non PIC code. */
5910 if (mips_pic
== NO_PIC
5911 || offset_expr
.X_op
== O_constant
)
5913 /* If this is a reference to a GP relative symbol, and there
5914 is no base register, we want
5915 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
5916 Otherwise, if there is no base register, we want
5917 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
5918 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5919 If we have a constant, we need two instructions anyhow,
5920 so we always use the latter form.
5922 If we have a base register, and this is a reference to a
5923 GP relative symbol, we want
5924 addu $tempreg,$breg,$gp
5925 <op> $treg,<sym>($tempreg) (BFD_RELOC_GPREL16)
5927 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
5928 addu $tempreg,$tempreg,$breg
5929 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5930 With a constant we always use the latter case.
5932 With 64bit address space and no base register and $at usable,
5934 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5935 lui $at,<sym> (BFD_RELOC_HI16_S)
5936 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
5939 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5940 If we have a base register, we want
5941 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5942 lui $at,<sym> (BFD_RELOC_HI16_S)
5943 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
5947 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5949 Without $at we can't generate the optimal path for superscalar
5950 processors here since this would require two temporary registers.
5951 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5952 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
5954 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
5956 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5957 If we have a base register, we want
5958 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5959 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
5961 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
5963 daddu $tempreg,$tempreg,$breg
5964 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5966 For GP relative symbols in 64bit address space we can use
5967 the same sequence as in 32bit address space.
5969 If we have 64-bit addresses, as an optimization, for
5970 addresses which are 32-bit constants (e.g. kseg0/kseg1
5971 addresses) we fall back to the 32-bit address generation
5972 mechanism since it is more efficient. Note that due to
5973 the signed offset used by memory operations, the 32-bit
5974 range is shifted down by 32768 here. This code should
5975 probably attempt to generate 64-bit constants more
5976 efficiently in general.
5978 As an extension for architectures with 64-bit registers,
5979 we don't truncate 64-bit addresses given as literal
5980 constants down to 32 bits, to support existing practice
5981 in the mips64 Linux (the kernel), that compiles source
5982 files with -mabi=64, assembling them as o32 or n32 (with
5983 -Wa,-32 or -Wa,-n32). This is not beautiful, but since
5984 the whole kernel is loaded into a memory region that is
5985 addressable with sign-extended 32-bit addresses, it is
5986 wasteful to compute the upper 32 bits of every
5987 non-literal address, that takes more space and time.
5988 Some day this should probably be implemented as an
5989 assembler option, such that the kernel doesn't have to
5990 use such ugly hacks, even though it will still have to
5991 end up converting the binary to ELF32 for a number of
5992 platforms whose boot loaders don't support ELF64
5994 if ((HAVE_64BIT_ADDRESSES
5995 && ! (offset_expr
.X_op
== O_constant
5996 && IS_SEXT_32BIT_NUM (offset_expr
.X_add_number
+ 0x8000)))
5998 && offset_expr
.X_op
== O_constant
5999 && ! IS_SEXT_32BIT_NUM (offset_expr
.X_add_number
+ 0x8000)))
6001 if (offset_expr
.X_op
== O_symbol
6002 && (valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
6003 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
6005 relax_start (offset_expr
.X_add_symbol
);
6008 macro_build (&offset_expr
, s
, fmt
, treg
,
6009 BFD_RELOC_GPREL16
, mips_gp_register
);
6013 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6014 tempreg
, breg
, mips_gp_register
);
6015 macro_build (&offset_expr
, s
, fmt
, treg
,
6016 BFD_RELOC_GPREL16
, tempreg
);
6021 if (used_at
== 0 && !mips_opts
.noat
)
6023 macro_build (&offset_expr
, "lui", "t,u", tempreg
,
6024 BFD_RELOC_MIPS_HIGHEST
);
6025 macro_build (&offset_expr
, "lui", "t,u", AT
,
6027 macro_build (&offset_expr
, "daddiu", "t,r,j", tempreg
,
6028 tempreg
, BFD_RELOC_MIPS_HIGHER
);
6030 macro_build (NULL
, "daddu", "d,v,t", AT
, AT
, breg
);
6031 macro_build (NULL
, "dsll32", "d,w,<", tempreg
, tempreg
, 0);
6032 macro_build (NULL
, "daddu", "d,v,t", tempreg
, tempreg
, AT
);
6033 macro_build (&offset_expr
, s
, fmt
, treg
, BFD_RELOC_LO16
,
6039 macro_build (&offset_expr
, "lui", "t,u", tempreg
,
6040 BFD_RELOC_MIPS_HIGHEST
);
6041 macro_build (&offset_expr
, "daddiu", "t,r,j", tempreg
,
6042 tempreg
, BFD_RELOC_MIPS_HIGHER
);
6043 macro_build (NULL
, "dsll", "d,w,<", tempreg
, tempreg
, 16);
6044 macro_build (&offset_expr
, "daddiu", "t,r,j", tempreg
,
6045 tempreg
, BFD_RELOC_HI16_S
);
6046 macro_build (NULL
, "dsll", "d,w,<", tempreg
, tempreg
, 16);
6048 macro_build (NULL
, "daddu", "d,v,t",
6049 tempreg
, tempreg
, breg
);
6050 macro_build (&offset_expr
, s
, fmt
, treg
,
6051 BFD_RELOC_LO16
, tempreg
);
6054 if (mips_relax
.sequence
)
6059 if (offset_expr
.X_op
== O_constant
6060 && ! IS_SEXT_32BIT_NUM (offset_expr
.X_add_number
+ 0x8000))
6061 as_bad (_("load/store address overflow (max 32 bits)"));
6065 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
6066 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
6068 relax_start (offset_expr
.X_add_symbol
);
6069 macro_build (&offset_expr
, s
, fmt
, treg
, BFD_RELOC_GPREL16
,
6073 macro_build_lui (&offset_expr
, tempreg
);
6074 macro_build (&offset_expr
, s
, fmt
, treg
,
6075 BFD_RELOC_LO16
, tempreg
);
6076 if (mips_relax
.sequence
)
6081 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
6082 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
6084 relax_start (offset_expr
.X_add_symbol
);
6085 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6086 tempreg
, breg
, mips_gp_register
);
6087 macro_build (&offset_expr
, s
, fmt
, treg
,
6088 BFD_RELOC_GPREL16
, tempreg
);
6091 macro_build_lui (&offset_expr
, tempreg
);
6092 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6093 tempreg
, tempreg
, breg
);
6094 macro_build (&offset_expr
, s
, fmt
, treg
,
6095 BFD_RELOC_LO16
, tempreg
);
6096 if (mips_relax
.sequence
)
6100 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
6102 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT16
;
6104 /* If this is a reference to an external symbol, we want
6105 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6107 <op> $treg,0($tempreg)
6109 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6111 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
6112 <op> $treg,0($tempreg)
6115 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
6116 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST)
6118 If there is a base register, we add it to $tempreg before
6119 the <op>. If there is a constant, we stick it in the
6120 <op> instruction. We don't handle constants larger than
6121 16 bits, because we have no way to load the upper 16 bits
6122 (actually, we could handle them for the subset of cases
6123 in which we are not using $at). */
6124 assert (offset_expr
.X_op
== O_symbol
);
6127 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
6128 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
6130 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6131 tempreg
, tempreg
, breg
);
6132 macro_build (&offset_expr
, s
, fmt
, treg
,
6133 BFD_RELOC_MIPS_GOT_OFST
, tempreg
);
6136 expr1
.X_add_number
= offset_expr
.X_add_number
;
6137 offset_expr
.X_add_number
= 0;
6138 if (expr1
.X_add_number
< -0x8000
6139 || expr1
.X_add_number
>= 0x8000)
6140 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6141 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
6142 lw_reloc_type
, mips_gp_register
);
6144 relax_start (offset_expr
.X_add_symbol
);
6146 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j", tempreg
,
6147 tempreg
, BFD_RELOC_LO16
);
6150 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6151 tempreg
, tempreg
, breg
);
6152 macro_build (&expr1
, s
, fmt
, treg
, BFD_RELOC_LO16
, tempreg
);
6154 else if (mips_pic
== SVR4_PIC
&& ! HAVE_NEWABI
)
6158 /* If this is a reference to an external symbol, we want
6159 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
6160 addu $tempreg,$tempreg,$gp
6161 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
6162 <op> $treg,0($tempreg)
6164 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6166 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
6167 <op> $treg,0($tempreg)
6168 If there is a base register, we add it to $tempreg before
6169 the <op>. If there is a constant, we stick it in the
6170 <op> instruction. We don't handle constants larger than
6171 16 bits, because we have no way to load the upper 16 bits
6172 (actually, we could handle them for the subset of cases
6173 in which we are not using $at). */
6174 assert (offset_expr
.X_op
== O_symbol
);
6175 expr1
.X_add_number
= offset_expr
.X_add_number
;
6176 offset_expr
.X_add_number
= 0;
6177 if (expr1
.X_add_number
< -0x8000
6178 || expr1
.X_add_number
>= 0x8000)
6179 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6180 gpdelay
= reg_needs_delay (mips_gp_register
);
6181 relax_start (offset_expr
.X_add_symbol
);
6182 macro_build (&offset_expr
, "lui", "t,u", tempreg
,
6183 BFD_RELOC_MIPS_GOT_HI16
);
6184 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", tempreg
, tempreg
,
6186 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
6187 BFD_RELOC_MIPS_GOT_LO16
, tempreg
);
6190 macro_build (NULL
, "nop", "");
6191 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
6192 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
6194 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j", tempreg
,
6195 tempreg
, BFD_RELOC_LO16
);
6199 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6200 tempreg
, tempreg
, breg
);
6201 macro_build (&expr1
, s
, fmt
, treg
, BFD_RELOC_LO16
, tempreg
);
6203 else if (mips_pic
== SVR4_PIC
&& HAVE_NEWABI
)
6205 /* If this is a reference to an external symbol, we want
6206 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
6207 add $tempreg,$tempreg,$gp
6208 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
6209 <op> $treg,<ofst>($tempreg)
6210 Otherwise, for local symbols, we want:
6211 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
6212 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST) */
6213 assert (offset_expr
.X_op
== O_symbol
);
6214 expr1
.X_add_number
= offset_expr
.X_add_number
;
6215 offset_expr
.X_add_number
= 0;
6216 if (expr1
.X_add_number
< -0x8000
6217 || expr1
.X_add_number
>= 0x8000)
6218 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6219 relax_start (offset_expr
.X_add_symbol
);
6220 macro_build (&offset_expr
, "lui", "t,u", tempreg
,
6221 BFD_RELOC_MIPS_GOT_HI16
);
6222 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", tempreg
, tempreg
,
6224 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
6225 BFD_RELOC_MIPS_GOT_LO16
, tempreg
);
6227 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6228 tempreg
, tempreg
, breg
);
6229 macro_build (&expr1
, s
, fmt
, treg
, BFD_RELOC_LO16
, tempreg
);
6232 offset_expr
.X_add_number
= expr1
.X_add_number
;
6233 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
6234 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
6236 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6237 tempreg
, tempreg
, breg
);
6238 macro_build (&offset_expr
, s
, fmt
, treg
,
6239 BFD_RELOC_MIPS_GOT_OFST
, tempreg
);
6249 load_register (treg
, &imm_expr
, 0);
6253 load_register (treg
, &imm_expr
, 1);
6257 if (imm_expr
.X_op
== O_constant
)
6260 load_register (AT
, &imm_expr
, 0);
6261 macro_build (NULL
, "mtc1", "t,G", AT
, treg
);
6266 assert (offset_expr
.X_op
== O_symbol
6267 && strcmp (segment_name (S_GET_SEGMENT
6268 (offset_expr
.X_add_symbol
)),
6270 && offset_expr
.X_add_number
== 0);
6271 macro_build (&offset_expr
, "lwc1", "T,o(b)", treg
,
6272 BFD_RELOC_MIPS_LITERAL
, mips_gp_register
);
6277 /* Check if we have a constant in IMM_EXPR. If the GPRs are 64 bits
6278 wide, IMM_EXPR is the entire value. Otherwise IMM_EXPR is the high
6279 order 32 bits of the value and the low order 32 bits are either
6280 zero or in OFFSET_EXPR. */
6281 if (imm_expr
.X_op
== O_constant
|| imm_expr
.X_op
== O_big
)
6283 if (HAVE_64BIT_GPRS
)
6284 load_register (treg
, &imm_expr
, 1);
6289 if (target_big_endian
)
6301 load_register (hreg
, &imm_expr
, 0);
6304 if (offset_expr
.X_op
== O_absent
)
6305 move_register (lreg
, 0);
6308 assert (offset_expr
.X_op
== O_constant
);
6309 load_register (lreg
, &offset_expr
, 0);
6316 /* We know that sym is in the .rdata section. First we get the
6317 upper 16 bits of the address. */
6318 if (mips_pic
== NO_PIC
)
6320 macro_build_lui (&offset_expr
, AT
);
6323 else if (mips_pic
== SVR4_PIC
)
6325 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", AT
,
6326 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
6332 /* Now we load the register(s). */
6333 if (HAVE_64BIT_GPRS
)
6336 macro_build (&offset_expr
, "ld", "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
6341 macro_build (&offset_expr
, "lw", "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
6344 /* FIXME: How in the world do we deal with the possible
6346 offset_expr
.X_add_number
+= 4;
6347 macro_build (&offset_expr
, "lw", "t,o(b)",
6348 treg
+ 1, BFD_RELOC_LO16
, AT
);
6354 /* Check if we have a constant in IMM_EXPR. If the FPRs are 64 bits
6355 wide, IMM_EXPR is the entire value and the GPRs are known to be 64
6356 bits wide as well. Otherwise IMM_EXPR is the high order 32 bits of
6357 the value and the low order 32 bits are either zero or in
6359 if (imm_expr
.X_op
== O_constant
|| imm_expr
.X_op
== O_big
)
6362 load_register (AT
, &imm_expr
, HAVE_64BIT_FPRS
);
6363 if (HAVE_64BIT_FPRS
)
6365 assert (HAVE_64BIT_GPRS
);
6366 macro_build (NULL
, "dmtc1", "t,S", AT
, treg
);
6370 macro_build (NULL
, "mtc1", "t,G", AT
, treg
+ 1);
6371 if (offset_expr
.X_op
== O_absent
)
6372 macro_build (NULL
, "mtc1", "t,G", 0, treg
);
6375 assert (offset_expr
.X_op
== O_constant
);
6376 load_register (AT
, &offset_expr
, 0);
6377 macro_build (NULL
, "mtc1", "t,G", AT
, treg
);
6383 assert (offset_expr
.X_op
== O_symbol
6384 && offset_expr
.X_add_number
== 0);
6385 s
= segment_name (S_GET_SEGMENT (offset_expr
.X_add_symbol
));
6386 if (strcmp (s
, ".lit8") == 0)
6388 if (mips_opts
.isa
!= ISA_MIPS1
)
6390 macro_build (&offset_expr
, "ldc1", "T,o(b)", treg
,
6391 BFD_RELOC_MIPS_LITERAL
, mips_gp_register
);
6394 breg
= mips_gp_register
;
6395 r
= BFD_RELOC_MIPS_LITERAL
;
6400 assert (strcmp (s
, RDATA_SECTION_NAME
) == 0);
6402 if (mips_pic
== SVR4_PIC
)
6403 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", AT
,
6404 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
6407 /* FIXME: This won't work for a 64 bit address. */
6408 macro_build_lui (&offset_expr
, AT
);
6411 if (mips_opts
.isa
!= ISA_MIPS1
)
6413 macro_build (&offset_expr
, "ldc1", "T,o(b)",
6414 treg
, BFD_RELOC_LO16
, AT
);
6423 if (mips_opts
.arch
== CPU_R4650
)
6425 as_bad (_("opcode not supported on this processor"));
6428 /* Even on a big endian machine $fn comes before $fn+1. We have
6429 to adjust when loading from memory. */
6432 assert (mips_opts
.isa
== ISA_MIPS1
);
6433 macro_build (&offset_expr
, "lwc1", "T,o(b)",
6434 target_big_endian
? treg
+ 1 : treg
, r
, breg
);
6435 /* FIXME: A possible overflow which I don't know how to deal
6437 offset_expr
.X_add_number
+= 4;
6438 macro_build (&offset_expr
, "lwc1", "T,o(b)",
6439 target_big_endian
? treg
: treg
+ 1, r
, breg
);
6444 * The MIPS assembler seems to check for X_add_number not
6445 * being double aligned and generating:
6448 * addiu at,at,%lo(foo+1)
6451 * But, the resulting address is the same after relocation so why
6452 * generate the extra instruction?
6454 if (mips_opts
.arch
== CPU_R4650
)
6456 as_bad (_("opcode not supported on this processor"));
6459 /* Itbl support may require additional care here. */
6461 if (mips_opts
.isa
!= ISA_MIPS1
)
6472 if (mips_opts
.arch
== CPU_R4650
)
6474 as_bad (_("opcode not supported on this processor"));
6478 if (mips_opts
.isa
!= ISA_MIPS1
)
6486 /* Itbl support may require additional care here. */
6491 if (HAVE_64BIT_GPRS
)
6502 if (HAVE_64BIT_GPRS
)
6512 if (offset_expr
.X_op
!= O_symbol
6513 && offset_expr
.X_op
!= O_constant
)
6515 as_bad (_("expression too complex"));
6516 offset_expr
.X_op
= O_constant
;
6519 /* Even on a big endian machine $fn comes before $fn+1. We have
6520 to adjust when loading from memory. We set coproc if we must
6521 load $fn+1 first. */
6522 /* Itbl support may require additional care here. */
6523 if (! target_big_endian
)
6526 if (mips_pic
== NO_PIC
6527 || offset_expr
.X_op
== O_constant
)
6529 /* If this is a reference to a GP relative symbol, we want
6530 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
6531 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_GPREL16)
6532 If we have a base register, we use this
6534 <op> $treg,<sym>($at) (BFD_RELOC_GPREL16)
6535 <op> $treg+1,<sym>+4($at) (BFD_RELOC_GPREL16)
6536 If this is not a GP relative symbol, we want
6537 lui $at,<sym> (BFD_RELOC_HI16_S)
6538 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
6539 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
6540 If there is a base register, we add it to $at after the
6541 lui instruction. If there is a constant, we always use
6543 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
6544 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
6546 relax_start (offset_expr
.X_add_symbol
);
6549 tempreg
= mips_gp_register
;
6553 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6554 AT
, breg
, mips_gp_register
);
6559 /* Itbl support may require additional care here. */
6560 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
+ 1 : treg
,
6561 BFD_RELOC_GPREL16
, tempreg
);
6562 offset_expr
.X_add_number
+= 4;
6564 /* Set mips_optimize to 2 to avoid inserting an
6566 hold_mips_optimize
= mips_optimize
;
6568 /* Itbl support may require additional care here. */
6569 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
: treg
+ 1,
6570 BFD_RELOC_GPREL16
, tempreg
);
6571 mips_optimize
= hold_mips_optimize
;
6575 /* We just generated two relocs. When tc_gen_reloc
6576 handles this case, it will skip the first reloc and
6577 handle the second. The second reloc already has an
6578 extra addend of 4, which we added above. We must
6579 subtract it out, and then subtract another 4 to make
6580 the first reloc come out right. The second reloc
6581 will come out right because we are going to add 4 to
6582 offset_expr when we build its instruction below.
6584 If we have a symbol, then we don't want to include
6585 the offset, because it will wind up being included
6586 when we generate the reloc. */
6588 if (offset_expr
.X_op
== O_constant
)
6589 offset_expr
.X_add_number
-= 8;
6592 offset_expr
.X_add_number
= -4;
6593 offset_expr
.X_op
= O_constant
;
6597 macro_build_lui (&offset_expr
, AT
);
6599 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
6600 /* Itbl support may require additional care here. */
6601 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
+ 1 : treg
,
6602 BFD_RELOC_LO16
, AT
);
6603 /* FIXME: How do we handle overflow here? */
6604 offset_expr
.X_add_number
+= 4;
6605 /* Itbl support may require additional care here. */
6606 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
: treg
+ 1,
6607 BFD_RELOC_LO16
, AT
);
6608 if (mips_relax
.sequence
)
6611 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
6613 /* If this is a reference to an external symbol, we want
6614 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6619 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6621 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
6622 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
6623 If there is a base register we add it to $at before the
6624 lwc1 instructions. If there is a constant we include it
6625 in the lwc1 instructions. */
6627 expr1
.X_add_number
= offset_expr
.X_add_number
;
6628 if (expr1
.X_add_number
< -0x8000
6629 || expr1
.X_add_number
>= 0x8000 - 4)
6630 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6631 load_got_offset (AT
, &offset_expr
);
6634 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
6636 /* Set mips_optimize to 2 to avoid inserting an undesired
6638 hold_mips_optimize
= mips_optimize
;
6641 /* Itbl support may require additional care here. */
6642 relax_start (offset_expr
.X_add_symbol
);
6643 macro_build (&expr1
, s
, fmt
, coproc
? treg
+ 1 : treg
,
6644 BFD_RELOC_LO16
, AT
);
6645 expr1
.X_add_number
+= 4;
6646 macro_build (&expr1
, s
, fmt
, coproc
? treg
: treg
+ 1,
6647 BFD_RELOC_LO16
, AT
);
6649 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
+ 1 : treg
,
6650 BFD_RELOC_LO16
, AT
);
6651 offset_expr
.X_add_number
+= 4;
6652 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
: treg
+ 1,
6653 BFD_RELOC_LO16
, AT
);
6656 mips_optimize
= hold_mips_optimize
;
6658 else if (mips_pic
== SVR4_PIC
)
6662 /* If this is a reference to an external symbol, we want
6663 lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16)
6665 lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16)
6670 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6672 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
6673 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
6674 If there is a base register we add it to $at before the
6675 lwc1 instructions. If there is a constant we include it
6676 in the lwc1 instructions. */
6678 expr1
.X_add_number
= offset_expr
.X_add_number
;
6679 offset_expr
.X_add_number
= 0;
6680 if (expr1
.X_add_number
< -0x8000
6681 || expr1
.X_add_number
>= 0x8000 - 4)
6682 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6683 gpdelay
= reg_needs_delay (mips_gp_register
);
6684 relax_start (offset_expr
.X_add_symbol
);
6685 macro_build (&offset_expr
, "lui", "t,u",
6686 AT
, BFD_RELOC_MIPS_GOT_HI16
);
6687 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6688 AT
, AT
, mips_gp_register
);
6689 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
6690 AT
, BFD_RELOC_MIPS_GOT_LO16
, AT
);
6693 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
6694 /* Itbl support may require additional care here. */
6695 macro_build (&expr1
, s
, fmt
, coproc
? treg
+ 1 : treg
,
6696 BFD_RELOC_LO16
, AT
);
6697 expr1
.X_add_number
+= 4;
6699 /* Set mips_optimize to 2 to avoid inserting an undesired
6701 hold_mips_optimize
= mips_optimize
;
6703 /* Itbl support may require additional care here. */
6704 macro_build (&expr1
, s
, fmt
, coproc
? treg
: treg
+ 1,
6705 BFD_RELOC_LO16
, AT
);
6706 mips_optimize
= hold_mips_optimize
;
6707 expr1
.X_add_number
-= 4;
6710 offset_expr
.X_add_number
= expr1
.X_add_number
;
6712 macro_build (NULL
, "nop", "");
6713 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", AT
,
6714 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
6717 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
6718 /* Itbl support may require additional care here. */
6719 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
+ 1 : treg
,
6720 BFD_RELOC_LO16
, AT
);
6721 offset_expr
.X_add_number
+= 4;
6723 /* Set mips_optimize to 2 to avoid inserting an undesired
6725 hold_mips_optimize
= mips_optimize
;
6727 /* Itbl support may require additional care here. */
6728 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
: treg
+ 1,
6729 BFD_RELOC_LO16
, AT
);
6730 mips_optimize
= hold_mips_optimize
;
6744 assert (HAVE_32BIT_ADDRESSES
);
6745 macro_build (&offset_expr
, s
, "t,o(b)", treg
, BFD_RELOC_LO16
, breg
);
6746 offset_expr
.X_add_number
+= 4;
6747 macro_build (&offset_expr
, s
, "t,o(b)", treg
+ 1, BFD_RELOC_LO16
, breg
);
6750 /* New code added to support COPZ instructions.
6751 This code builds table entries out of the macros in mip_opcodes.
6752 R4000 uses interlocks to handle coproc delays.
6753 Other chips (like the R3000) require nops to be inserted for delays.
6755 FIXME: Currently, we require that the user handle delays.
6756 In order to fill delay slots for non-interlocked chips,
6757 we must have a way to specify delays based on the coprocessor.
6758 Eg. 4 cycles if load coproc reg from memory, 1 if in cache, etc.
6759 What are the side-effects of the cop instruction?
6760 What cache support might we have and what are its effects?
6761 Both coprocessor & memory require delays. how long???
6762 What registers are read/set/modified?
6764 If an itbl is provided to interpret cop instructions,
6765 this knowledge can be encoded in the itbl spec. */
6779 /* For now we just do C (same as Cz). The parameter will be
6780 stored in insn_opcode by mips_ip. */
6781 macro_build (NULL
, s
, "C", ip
->insn_opcode
);
6785 move_register (dreg
, sreg
);
6788 #ifdef LOSING_COMPILER
6790 /* Try and see if this is a new itbl instruction.
6791 This code builds table entries out of the macros in mip_opcodes.
6792 FIXME: For now we just assemble the expression and pass it's
6793 value along as a 32-bit immediate.
6794 We may want to have the assembler assemble this value,
6795 so that we gain the assembler's knowledge of delay slots,
6797 Would it be more efficient to use mask (id) here? */
6798 if (itbl_have_entries
6799 && (immed_expr
= itbl_assemble (ip
->insn_mo
->name
, "")))
6801 s
= ip
->insn_mo
->name
;
6803 coproc
= ITBL_DECODE_PNUM (immed_expr
);;
6804 macro_build (&immed_expr
, s
, "C");
6810 if (mips_opts
.noat
&& used_at
)
6811 as_bad (_("Macro used $at after \".set noat\""));
6815 macro2 (struct mips_cl_insn
*ip
)
6817 register int treg
, sreg
, dreg
, breg
;
6832 bfd_reloc_code_real_type r
;
6834 treg
= (ip
->insn_opcode
>> 16) & 0x1f;
6835 dreg
= (ip
->insn_opcode
>> 11) & 0x1f;
6836 sreg
= breg
= (ip
->insn_opcode
>> 21) & 0x1f;
6837 mask
= ip
->insn_mo
->mask
;
6839 expr1
.X_op
= O_constant
;
6840 expr1
.X_op_symbol
= NULL
;
6841 expr1
.X_add_symbol
= NULL
;
6842 expr1
.X_add_number
= 1;
6846 #endif /* LOSING_COMPILER */
6851 macro_build (NULL
, dbl
? "dmultu" : "multu", "s,t", sreg
, treg
);
6852 macro_build (NULL
, "mflo", "d", dreg
);
6858 /* The MIPS assembler some times generates shifts and adds. I'm
6859 not trying to be that fancy. GCC should do this for us
6862 load_register (AT
, &imm_expr
, dbl
);
6863 macro_build (NULL
, dbl
? "dmult" : "mult", "s,t", sreg
, AT
);
6864 macro_build (NULL
, "mflo", "d", dreg
);
6877 mips_emit_delays (TRUE
);
6878 ++mips_opts
.noreorder
;
6879 mips_any_noreorder
= 1;
6882 load_register (AT
, &imm_expr
, dbl
);
6883 macro_build (NULL
, dbl
? "dmult" : "mult", "s,t", sreg
, imm
? AT
: treg
);
6884 macro_build (NULL
, "mflo", "d", dreg
);
6885 macro_build (NULL
, dbl
? "dsra32" : "sra", "d,w,<", dreg
, dreg
, RA
);
6886 macro_build (NULL
, "mfhi", "d", AT
);
6888 macro_build (NULL
, "tne", "s,t,q", dreg
, AT
, 6);
6891 expr1
.X_add_number
= 8;
6892 macro_build (&expr1
, "beq", "s,t,p", dreg
, AT
);
6893 macro_build (NULL
, "nop", "", 0);
6894 macro_build (NULL
, "break", "c", 6);
6896 --mips_opts
.noreorder
;
6897 macro_build (NULL
, "mflo", "d", dreg
);
6910 mips_emit_delays (TRUE
);
6911 ++mips_opts
.noreorder
;
6912 mips_any_noreorder
= 1;
6915 load_register (AT
, &imm_expr
, dbl
);
6916 macro_build (NULL
, dbl
? "dmultu" : "multu", "s,t",
6917 sreg
, imm
? AT
: treg
);
6918 macro_build (NULL
, "mfhi", "d", AT
);
6919 macro_build (NULL
, "mflo", "d", dreg
);
6921 macro_build (NULL
, "tne", "s,t,q", AT
, 0, 6);
6924 expr1
.X_add_number
= 8;
6925 macro_build (&expr1
, "beq", "s,t,p", AT
, 0);
6926 macro_build (NULL
, "nop", "", 0);
6927 macro_build (NULL
, "break", "c", 6);
6929 --mips_opts
.noreorder
;
6933 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
6944 macro_build (NULL
, "dnegu", "d,w", tempreg
, treg
);
6945 macro_build (NULL
, "drorv", "d,t,s", dreg
, sreg
, tempreg
);
6949 macro_build (NULL
, "dsubu", "d,v,t", AT
, 0, treg
);
6950 macro_build (NULL
, "dsrlv", "d,t,s", AT
, sreg
, AT
);
6951 macro_build (NULL
, "dsllv", "d,t,s", dreg
, sreg
, treg
);
6952 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
6956 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
6967 macro_build (NULL
, "negu", "d,w", tempreg
, treg
);
6968 macro_build (NULL
, "rorv", "d,t,s", dreg
, sreg
, tempreg
);
6972 macro_build (NULL
, "subu", "d,v,t", AT
, 0, treg
);
6973 macro_build (NULL
, "srlv", "d,t,s", AT
, sreg
, AT
);
6974 macro_build (NULL
, "sllv", "d,t,s", dreg
, sreg
, treg
);
6975 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
6983 if (imm_expr
.X_op
!= O_constant
)
6984 as_bad (_("Improper rotate count"));
6985 rot
= imm_expr
.X_add_number
& 0x3f;
6986 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
6988 rot
= (64 - rot
) & 0x3f;
6990 macro_build (NULL
, "dror32", "d,w,<", dreg
, sreg
, rot
- 32);
6992 macro_build (NULL
, "dror", "d,w,<", dreg
, sreg
, rot
);
6997 macro_build (NULL
, "dsrl", "d,w,<", dreg
, sreg
, 0);
7000 l
= (rot
< 0x20) ? "dsll" : "dsll32";
7001 r
= ((0x40 - rot
) < 0x20) ? "dsrl" : "dsrl32";
7004 macro_build (NULL
, l
, "d,w,<", AT
, sreg
, rot
);
7005 macro_build (NULL
, r
, "d,w,<", dreg
, sreg
, (0x20 - rot
) & 0x1f);
7006 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
7014 if (imm_expr
.X_op
!= O_constant
)
7015 as_bad (_("Improper rotate count"));
7016 rot
= imm_expr
.X_add_number
& 0x1f;
7017 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
7019 macro_build (NULL
, "ror", "d,w,<", dreg
, sreg
, (32 - rot
) & 0x1f);
7024 macro_build (NULL
, "srl", "d,w,<", dreg
, sreg
, 0);
7028 macro_build (NULL
, "sll", "d,w,<", AT
, sreg
, rot
);
7029 macro_build (NULL
, "srl", "d,w,<", dreg
, sreg
, (0x20 - rot
) & 0x1f);
7030 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
7035 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
7037 macro_build (NULL
, "drorv", "d,t,s", dreg
, sreg
, treg
);
7041 macro_build (NULL
, "dsubu", "d,v,t", AT
, 0, treg
);
7042 macro_build (NULL
, "dsllv", "d,t,s", AT
, sreg
, AT
);
7043 macro_build (NULL
, "dsrlv", "d,t,s", dreg
, sreg
, treg
);
7044 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
7048 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
7050 macro_build (NULL
, "rorv", "d,t,s", dreg
, sreg
, treg
);
7054 macro_build (NULL
, "subu", "d,v,t", AT
, 0, treg
);
7055 macro_build (NULL
, "sllv", "d,t,s", AT
, sreg
, AT
);
7056 macro_build (NULL
, "srlv", "d,t,s", dreg
, sreg
, treg
);
7057 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
7065 if (imm_expr
.X_op
!= O_constant
)
7066 as_bad (_("Improper rotate count"));
7067 rot
= imm_expr
.X_add_number
& 0x3f;
7068 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
7071 macro_build (NULL
, "dror32", "d,w,<", dreg
, sreg
, rot
- 32);
7073 macro_build (NULL
, "dror", "d,w,<", dreg
, sreg
, rot
);
7078 macro_build (NULL
, "dsrl", "d,w,<", dreg
, sreg
, 0);
7081 r
= (rot
< 0x20) ? "dsrl" : "dsrl32";
7082 l
= ((0x40 - rot
) < 0x20) ? "dsll" : "dsll32";
7085 macro_build (NULL
, r
, "d,w,<", AT
, sreg
, rot
);
7086 macro_build (NULL
, l
, "d,w,<", dreg
, sreg
, (0x20 - rot
) & 0x1f);
7087 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
7095 if (imm_expr
.X_op
!= O_constant
)
7096 as_bad (_("Improper rotate count"));
7097 rot
= imm_expr
.X_add_number
& 0x1f;
7098 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
7100 macro_build (NULL
, "ror", "d,w,<", dreg
, sreg
, rot
);
7105 macro_build (NULL
, "srl", "d,w,<", dreg
, sreg
, 0);
7109 macro_build (NULL
, "srl", "d,w,<", AT
, sreg
, rot
);
7110 macro_build (NULL
, "sll", "d,w,<", dreg
, sreg
, (0x20 - rot
) & 0x1f);
7111 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
7116 if (mips_opts
.arch
== CPU_R4650
)
7118 as_bad (_("opcode not supported on this processor"));
7121 assert (mips_opts
.isa
== ISA_MIPS1
);
7122 /* Even on a big endian machine $fn comes before $fn+1. We have
7123 to adjust when storing to memory. */
7124 macro_build (&offset_expr
, "swc1", "T,o(b)",
7125 target_big_endian
? treg
+ 1 : treg
, BFD_RELOC_LO16
, breg
);
7126 offset_expr
.X_add_number
+= 4;
7127 macro_build (&offset_expr
, "swc1", "T,o(b)",
7128 target_big_endian
? treg
: treg
+ 1, BFD_RELOC_LO16
, breg
);
7133 macro_build (&expr1
, "sltiu", "t,r,j", dreg
, treg
, BFD_RELOC_LO16
);
7135 macro_build (&expr1
, "sltiu", "t,r,j", dreg
, sreg
, BFD_RELOC_LO16
);
7138 macro_build (NULL
, "xor", "d,v,t", dreg
, sreg
, treg
);
7139 macro_build (&expr1
, "sltiu", "t,r,j", dreg
, dreg
, BFD_RELOC_LO16
);
7144 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
7146 macro_build (&expr1
, "sltiu", "t,r,j", dreg
, sreg
, BFD_RELOC_LO16
);
7151 as_warn (_("Instruction %s: result is always false"),
7153 move_register (dreg
, 0);
7156 if (imm_expr
.X_op
== O_constant
7157 && imm_expr
.X_add_number
>= 0
7158 && imm_expr
.X_add_number
< 0x10000)
7160 macro_build (&imm_expr
, "xori", "t,r,i", dreg
, sreg
, BFD_RELOC_LO16
);
7162 else if (imm_expr
.X_op
== O_constant
7163 && imm_expr
.X_add_number
> -0x8000
7164 && imm_expr
.X_add_number
< 0)
7166 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
7167 macro_build (&imm_expr
, HAVE_32BIT_GPRS
? "addiu" : "daddiu",
7168 "t,r,j", dreg
, sreg
, BFD_RELOC_LO16
);
7172 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7173 macro_build (NULL
, "xor", "d,v,t", dreg
, sreg
, AT
);
7176 macro_build (&expr1
, "sltiu", "t,r,j", dreg
, dreg
, BFD_RELOC_LO16
);
7179 case M_SGE
: /* sreg >= treg <==> not (sreg < treg) */
7185 macro_build (NULL
, s
, "d,v,t", dreg
, sreg
, treg
);
7186 macro_build (&expr1
, "xori", "t,r,i", dreg
, dreg
, BFD_RELOC_LO16
);
7189 case M_SGE_I
: /* sreg >= I <==> not (sreg < I) */
7191 if (imm_expr
.X_op
== O_constant
7192 && imm_expr
.X_add_number
>= -0x8000
7193 && imm_expr
.X_add_number
< 0x8000)
7195 macro_build (&imm_expr
, mask
== M_SGE_I
? "slti" : "sltiu", "t,r,j",
7196 dreg
, sreg
, BFD_RELOC_LO16
);
7200 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7201 macro_build (NULL
, mask
== M_SGE_I
? "slt" : "sltu", "d,v,t",
7205 macro_build (&expr1
, "xori", "t,r,i", dreg
, dreg
, BFD_RELOC_LO16
);
7208 case M_SGT
: /* sreg > treg <==> treg < sreg */
7214 macro_build (NULL
, s
, "d,v,t", dreg
, treg
, sreg
);
7217 case M_SGT_I
: /* sreg > I <==> I < sreg */
7224 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7225 macro_build (NULL
, s
, "d,v,t", dreg
, AT
, sreg
);
7228 case M_SLE
: /* sreg <= treg <==> treg >= sreg <==> not (treg < sreg) */
7234 macro_build (NULL
, s
, "d,v,t", dreg
, treg
, sreg
);
7235 macro_build (&expr1
, "xori", "t,r,i", dreg
, dreg
, BFD_RELOC_LO16
);
7238 case M_SLE_I
: /* sreg <= I <==> I >= sreg <==> not (I < sreg) */
7245 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7246 macro_build (NULL
, s
, "d,v,t", dreg
, AT
, sreg
);
7247 macro_build (&expr1
, "xori", "t,r,i", dreg
, dreg
, BFD_RELOC_LO16
);
7251 if (imm_expr
.X_op
== O_constant
7252 && imm_expr
.X_add_number
>= -0x8000
7253 && imm_expr
.X_add_number
< 0x8000)
7255 macro_build (&imm_expr
, "slti", "t,r,j", dreg
, sreg
, BFD_RELOC_LO16
);
7259 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7260 macro_build (NULL
, "slt", "d,v,t", dreg
, sreg
, AT
);
7264 if (imm_expr
.X_op
== O_constant
7265 && imm_expr
.X_add_number
>= -0x8000
7266 && imm_expr
.X_add_number
< 0x8000)
7268 macro_build (&imm_expr
, "sltiu", "t,r,j", dreg
, sreg
,
7273 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7274 macro_build (NULL
, "sltu", "d,v,t", dreg
, sreg
, AT
);
7279 macro_build (NULL
, "sltu", "d,v,t", dreg
, 0, treg
);
7281 macro_build (NULL
, "sltu", "d,v,t", dreg
, 0, sreg
);
7284 macro_build (NULL
, "xor", "d,v,t", dreg
, sreg
, treg
);
7285 macro_build (NULL
, "sltu", "d,v,t", dreg
, 0, dreg
);
7290 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
7292 macro_build (NULL
, "sltu", "d,v,t", dreg
, 0, sreg
);
7297 as_warn (_("Instruction %s: result is always true"),
7299 macro_build (&expr1
, HAVE_32BIT_GPRS
? "addiu" : "daddiu", "t,r,j",
7300 dreg
, 0, BFD_RELOC_LO16
);
7303 if (imm_expr
.X_op
== O_constant
7304 && imm_expr
.X_add_number
>= 0
7305 && imm_expr
.X_add_number
< 0x10000)
7307 macro_build (&imm_expr
, "xori", "t,r,i", dreg
, sreg
, BFD_RELOC_LO16
);
7309 else if (imm_expr
.X_op
== O_constant
7310 && imm_expr
.X_add_number
> -0x8000
7311 && imm_expr
.X_add_number
< 0)
7313 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
7314 macro_build (&imm_expr
, HAVE_32BIT_GPRS
? "addiu" : "daddiu",
7315 "t,r,j", dreg
, sreg
, BFD_RELOC_LO16
);
7319 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7320 macro_build (NULL
, "xor", "d,v,t", dreg
, sreg
, AT
);
7323 macro_build (NULL
, "sltu", "d,v,t", dreg
, 0, dreg
);
7329 if (imm_expr
.X_op
== O_constant
7330 && imm_expr
.X_add_number
> -0x8000
7331 && imm_expr
.X_add_number
<= 0x8000)
7333 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
7334 macro_build (&imm_expr
, dbl
? "daddi" : "addi", "t,r,j",
7335 dreg
, sreg
, BFD_RELOC_LO16
);
7339 load_register (AT
, &imm_expr
, dbl
);
7340 macro_build (NULL
, dbl
? "dsub" : "sub", "d,v,t", dreg
, sreg
, AT
);
7346 if (imm_expr
.X_op
== O_constant
7347 && imm_expr
.X_add_number
> -0x8000
7348 && imm_expr
.X_add_number
<= 0x8000)
7350 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
7351 macro_build (&imm_expr
, dbl
? "daddiu" : "addiu", "t,r,j",
7352 dreg
, sreg
, BFD_RELOC_LO16
);
7356 load_register (AT
, &imm_expr
, dbl
);
7357 macro_build (NULL
, dbl
? "dsubu" : "subu", "d,v,t", dreg
, sreg
, AT
);
7379 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7380 macro_build (NULL
, s
, "s,t", sreg
, AT
);
7385 assert (mips_opts
.isa
== ISA_MIPS1
);
7387 sreg
= (ip
->insn_opcode
>> 11) & 0x1f; /* floating reg */
7388 dreg
= (ip
->insn_opcode
>> 06) & 0x1f; /* floating reg */
7391 * Is the double cfc1 instruction a bug in the mips assembler;
7392 * or is there a reason for it?
7394 mips_emit_delays (TRUE
);
7395 ++mips_opts
.noreorder
;
7396 mips_any_noreorder
= 1;
7397 macro_build (NULL
, "cfc1", "t,G", treg
, RA
);
7398 macro_build (NULL
, "cfc1", "t,G", treg
, RA
);
7399 macro_build (NULL
, "nop", "");
7400 expr1
.X_add_number
= 3;
7401 macro_build (&expr1
, "ori", "t,r,i", AT
, treg
, BFD_RELOC_LO16
);
7402 expr1
.X_add_number
= 2;
7403 macro_build (&expr1
, "xori", "t,r,i", AT
, AT
, BFD_RELOC_LO16
);
7404 macro_build (NULL
, "ctc1", "t,G", AT
, RA
);
7405 macro_build (NULL
, "nop", "");
7406 macro_build (NULL
, mask
== M_TRUNCWD
? "cvt.w.d" : "cvt.w.s", "D,S",
7408 macro_build (NULL
, "ctc1", "t,G", treg
, RA
);
7409 macro_build (NULL
, "nop", "");
7410 --mips_opts
.noreorder
;
7420 if (offset_expr
.X_add_number
>= 0x7fff)
7421 as_bad (_("operand overflow"));
7422 if (! target_big_endian
)
7423 ++offset_expr
.X_add_number
;
7424 macro_build (&offset_expr
, s
, "t,o(b)", AT
, BFD_RELOC_LO16
, breg
);
7425 if (! target_big_endian
)
7426 --offset_expr
.X_add_number
;
7428 ++offset_expr
.X_add_number
;
7429 macro_build (&offset_expr
, "lbu", "t,o(b)", treg
, BFD_RELOC_LO16
, breg
);
7430 macro_build (NULL
, "sll", "d,w,<", AT
, AT
, 8);
7431 macro_build (NULL
, "or", "d,v,t", treg
, treg
, AT
);
7444 if (offset_expr
.X_add_number
>= 0x8000 - off
)
7445 as_bad (_("operand overflow"));
7453 if (! target_big_endian
)
7454 offset_expr
.X_add_number
+= off
;
7455 macro_build (&offset_expr
, s
, "t,o(b)", tempreg
, BFD_RELOC_LO16
, breg
);
7456 if (! target_big_endian
)
7457 offset_expr
.X_add_number
-= off
;
7459 offset_expr
.X_add_number
+= off
;
7460 macro_build (&offset_expr
, s2
, "t,o(b)", tempreg
, BFD_RELOC_LO16
, breg
);
7462 /* If necessary, move the result in tempreg the final destination. */
7463 if (treg
== tempreg
)
7465 /* Protect second load's delay slot. */
7467 move_register (treg
, tempreg
);
7481 load_address (AT
, &offset_expr
, &used_at
);
7483 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, AT
, breg
);
7484 if (! target_big_endian
)
7485 expr1
.X_add_number
= off
;
7487 expr1
.X_add_number
= 0;
7488 macro_build (&expr1
, s
, "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
7489 if (! target_big_endian
)
7490 expr1
.X_add_number
= 0;
7492 expr1
.X_add_number
= off
;
7493 macro_build (&expr1
, s2
, "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
7499 load_address (AT
, &offset_expr
, &used_at
);
7501 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, AT
, breg
);
7502 if (target_big_endian
)
7503 expr1
.X_add_number
= 0;
7504 macro_build (&expr1
, mask
== M_ULH_A
? "lb" : "lbu", "t,o(b)",
7505 treg
, BFD_RELOC_LO16
, AT
);
7506 if (target_big_endian
)
7507 expr1
.X_add_number
= 1;
7509 expr1
.X_add_number
= 0;
7510 macro_build (&expr1
, "lbu", "t,o(b)", AT
, BFD_RELOC_LO16
, AT
);
7511 macro_build (NULL
, "sll", "d,w,<", treg
, treg
, 8);
7512 macro_build (NULL
, "or", "d,v,t", treg
, treg
, AT
);
7517 if (offset_expr
.X_add_number
>= 0x7fff)
7518 as_bad (_("operand overflow"));
7519 if (target_big_endian
)
7520 ++offset_expr
.X_add_number
;
7521 macro_build (&offset_expr
, "sb", "t,o(b)", treg
, BFD_RELOC_LO16
, breg
);
7522 macro_build (NULL
, "srl", "d,w,<", AT
, treg
, 8);
7523 if (target_big_endian
)
7524 --offset_expr
.X_add_number
;
7526 ++offset_expr
.X_add_number
;
7527 macro_build (&offset_expr
, "sb", "t,o(b)", AT
, BFD_RELOC_LO16
, breg
);
7540 if (offset_expr
.X_add_number
>= 0x8000 - off
)
7541 as_bad (_("operand overflow"));
7542 if (! target_big_endian
)
7543 offset_expr
.X_add_number
+= off
;
7544 macro_build (&offset_expr
, s
, "t,o(b)", treg
, BFD_RELOC_LO16
, breg
);
7545 if (! target_big_endian
)
7546 offset_expr
.X_add_number
-= off
;
7548 offset_expr
.X_add_number
+= off
;
7549 macro_build (&offset_expr
, s2
, "t,o(b)", treg
, BFD_RELOC_LO16
, breg
);
7563 load_address (AT
, &offset_expr
, &used_at
);
7565 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, AT
, breg
);
7566 if (! target_big_endian
)
7567 expr1
.X_add_number
= off
;
7569 expr1
.X_add_number
= 0;
7570 macro_build (&expr1
, s
, "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
7571 if (! target_big_endian
)
7572 expr1
.X_add_number
= 0;
7574 expr1
.X_add_number
= off
;
7575 macro_build (&expr1
, s2
, "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
7580 load_address (AT
, &offset_expr
, &used_at
);
7582 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, AT
, breg
);
7583 if (! target_big_endian
)
7584 expr1
.X_add_number
= 0;
7585 macro_build (&expr1
, "sb", "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
7586 macro_build (NULL
, "srl", "d,w,<", treg
, treg
, 8);
7587 if (! target_big_endian
)
7588 expr1
.X_add_number
= 1;
7590 expr1
.X_add_number
= 0;
7591 macro_build (&expr1
, "sb", "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
7592 if (! target_big_endian
)
7593 expr1
.X_add_number
= 0;
7595 expr1
.X_add_number
= 1;
7596 macro_build (&expr1
, "lbu", "t,o(b)", AT
, BFD_RELOC_LO16
, AT
);
7597 macro_build (NULL
, "sll", "d,w,<", treg
, treg
, 8);
7598 macro_build (NULL
, "or", "d,v,t", treg
, treg
, AT
);
7602 /* FIXME: Check if this is one of the itbl macros, since they
7603 are added dynamically. */
7604 as_bad (_("Macro %s not implemented yet"), ip
->insn_mo
->name
);
7607 if (mips_opts
.noat
&& used_at
)
7608 as_bad (_("Macro used $at after \".set noat\""));
7611 /* Implement macros in mips16 mode. */
7614 mips16_macro (struct mips_cl_insn
*ip
)
7617 int xreg
, yreg
, zreg
, tmp
;
7620 const char *s
, *s2
, *s3
;
7622 mask
= ip
->insn_mo
->mask
;
7624 xreg
= (ip
->insn_opcode
>> MIPS16OP_SH_RX
) & MIPS16OP_MASK_RX
;
7625 yreg
= (ip
->insn_opcode
>> MIPS16OP_SH_RY
) & MIPS16OP_MASK_RY
;
7626 zreg
= (ip
->insn_opcode
>> MIPS16OP_SH_RZ
) & MIPS16OP_MASK_RZ
;
7628 expr1
.X_op
= O_constant
;
7629 expr1
.X_op_symbol
= NULL
;
7630 expr1
.X_add_symbol
= NULL
;
7631 expr1
.X_add_number
= 1;
7650 mips_emit_delays (TRUE
);
7651 ++mips_opts
.noreorder
;
7652 mips_any_noreorder
= 1;
7653 macro_build (NULL
, dbl
? "ddiv" : "div", "0,x,y", xreg
, yreg
);
7654 expr1
.X_add_number
= 2;
7655 macro_build (&expr1
, "bnez", "x,p", yreg
);
7656 macro_build (NULL
, "break", "6", 7);
7658 /* FIXME: The normal code checks for of -1 / -0x80000000 here,
7659 since that causes an overflow. We should do that as well,
7660 but I don't see how to do the comparisons without a temporary
7662 --mips_opts
.noreorder
;
7663 macro_build (NULL
, s
, "x", zreg
);
7682 mips_emit_delays (TRUE
);
7683 ++mips_opts
.noreorder
;
7684 mips_any_noreorder
= 1;
7685 macro_build (NULL
, s
, "0,x,y", xreg
, yreg
);
7686 expr1
.X_add_number
= 2;
7687 macro_build (&expr1
, "bnez", "x,p", yreg
);
7688 macro_build (NULL
, "break", "6", 7);
7689 --mips_opts
.noreorder
;
7690 macro_build (NULL
, s2
, "x", zreg
);
7696 macro_build (NULL
, dbl
? "dmultu" : "multu", "x,y", xreg
, yreg
);
7697 macro_build (NULL
, "mflo", "x", zreg
);
7705 if (imm_expr
.X_op
!= O_constant
)
7706 as_bad (_("Unsupported large constant"));
7707 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
7708 macro_build (&imm_expr
, dbl
? "daddiu" : "addiu", "y,x,4", yreg
, xreg
);
7712 if (imm_expr
.X_op
!= O_constant
)
7713 as_bad (_("Unsupported large constant"));
7714 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
7715 macro_build (&imm_expr
, "addiu", "x,k", xreg
);
7719 if (imm_expr
.X_op
!= O_constant
)
7720 as_bad (_("Unsupported large constant"));
7721 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
7722 macro_build (&imm_expr
, "daddiu", "y,j", yreg
);
7744 goto do_reverse_branch
;
7748 goto do_reverse_branch
;
7760 goto do_reverse_branch
;
7771 macro_build (NULL
, s
, "x,y", xreg
, yreg
);
7772 macro_build (&offset_expr
, s2
, "p");
7799 goto do_addone_branch_i
;
7804 goto do_addone_branch_i
;
7819 goto do_addone_branch_i
;
7826 if (imm_expr
.X_op
!= O_constant
)
7827 as_bad (_("Unsupported large constant"));
7828 ++imm_expr
.X_add_number
;
7831 macro_build (&imm_expr
, s
, s3
, xreg
);
7832 macro_build (&offset_expr
, s2
, "p");
7836 expr1
.X_add_number
= 0;
7837 macro_build (&expr1
, "slti", "x,8", yreg
);
7839 move_register (xreg
, yreg
);
7840 expr1
.X_add_number
= 2;
7841 macro_build (&expr1
, "bteqz", "p");
7842 macro_build (NULL
, "neg", "x,w", xreg
, xreg
);
7846 /* For consistency checking, verify that all bits are specified either
7847 by the match/mask part of the instruction definition, or by the
7850 validate_mips_insn (const struct mips_opcode
*opc
)
7852 const char *p
= opc
->args
;
7854 unsigned long used_bits
= opc
->mask
;
7856 if ((used_bits
& opc
->match
) != opc
->match
)
7858 as_bad (_("internal: bad mips opcode (mask error): %s %s"),
7859 opc
->name
, opc
->args
);
7862 #define USE_BITS(mask,shift) (used_bits |= ((mask) << (shift)))
7872 case 'A': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
7873 case 'B': USE_BITS (OP_MASK_INSMSB
, OP_SH_INSMSB
); break;
7874 case 'C': USE_BITS (OP_MASK_EXTMSBD
, OP_SH_EXTMSBD
); break;
7875 case 'D': USE_BITS (OP_MASK_RD
, OP_SH_RD
);
7876 USE_BITS (OP_MASK_SEL
, OP_SH_SEL
); break;
7877 case 'E': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
7878 case 'F': USE_BITS (OP_MASK_INSMSB
, OP_SH_INSMSB
); break;
7879 case 'G': USE_BITS (OP_MASK_EXTMSBD
, OP_SH_EXTMSBD
); break;
7880 case 'H': USE_BITS (OP_MASK_EXTMSBD
, OP_SH_EXTMSBD
); break;
7883 as_bad (_("internal: bad mips opcode (unknown extension operand type `+%c'): %s %s"),
7884 c
, opc
->name
, opc
->args
);
7888 case '<': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
7889 case '>': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
7891 case 'B': USE_BITS (OP_MASK_CODE20
, OP_SH_CODE20
); break;
7892 case 'C': USE_BITS (OP_MASK_COPZ
, OP_SH_COPZ
); break;
7893 case 'D': USE_BITS (OP_MASK_FD
, OP_SH_FD
); break;
7894 case 'E': USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
7896 case 'G': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
7897 case 'H': USE_BITS (OP_MASK_SEL
, OP_SH_SEL
); break;
7899 case 'J': USE_BITS (OP_MASK_CODE19
, OP_SH_CODE19
); break;
7900 case 'K': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
7902 case 'M': USE_BITS (OP_MASK_CCC
, OP_SH_CCC
); break;
7903 case 'N': USE_BITS (OP_MASK_BCC
, OP_SH_BCC
); break;
7904 case 'O': USE_BITS (OP_MASK_ALN
, OP_SH_ALN
); break;
7905 case 'Q': USE_BITS (OP_MASK_VSEL
, OP_SH_VSEL
);
7906 USE_BITS (OP_MASK_FT
, OP_SH_FT
); break;
7907 case 'R': USE_BITS (OP_MASK_FR
, OP_SH_FR
); break;
7908 case 'S': USE_BITS (OP_MASK_FS
, OP_SH_FS
); break;
7909 case 'T': USE_BITS (OP_MASK_FT
, OP_SH_FT
); break;
7910 case 'V': USE_BITS (OP_MASK_FS
, OP_SH_FS
); break;
7911 case 'W': USE_BITS (OP_MASK_FT
, OP_SH_FT
); break;
7912 case 'X': USE_BITS (OP_MASK_FD
, OP_SH_FD
); break;
7913 case 'Y': USE_BITS (OP_MASK_FS
, OP_SH_FS
); break;
7914 case 'Z': USE_BITS (OP_MASK_FT
, OP_SH_FT
); break;
7915 case 'a': USE_BITS (OP_MASK_TARGET
, OP_SH_TARGET
); break;
7916 case 'b': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
7917 case 'c': USE_BITS (OP_MASK_CODE
, OP_SH_CODE
); break;
7918 case 'd': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
7920 case 'h': USE_BITS (OP_MASK_PREFX
, OP_SH_PREFX
); break;
7921 case 'i': USE_BITS (OP_MASK_IMMEDIATE
, OP_SH_IMMEDIATE
); break;
7922 case 'j': USE_BITS (OP_MASK_DELTA
, OP_SH_DELTA
); break;
7923 case 'k': USE_BITS (OP_MASK_CACHE
, OP_SH_CACHE
); break;
7925 case 'o': USE_BITS (OP_MASK_DELTA
, OP_SH_DELTA
); break;
7926 case 'p': USE_BITS (OP_MASK_DELTA
, OP_SH_DELTA
); break;
7927 case 'q': USE_BITS (OP_MASK_CODE2
, OP_SH_CODE2
); break;
7928 case 'r': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
7929 case 's': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
7930 case 't': USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
7931 case 'u': USE_BITS (OP_MASK_IMMEDIATE
, OP_SH_IMMEDIATE
); break;
7932 case 'v': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
7933 case 'w': USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
7936 case 'P': USE_BITS (OP_MASK_PERFREG
, OP_SH_PERFREG
); break;
7937 case 'U': USE_BITS (OP_MASK_RD
, OP_SH_RD
);
7938 USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
7939 case 'e': USE_BITS (OP_MASK_VECBYTE
, OP_SH_VECBYTE
); break;
7940 case '%': USE_BITS (OP_MASK_VECALIGN
, OP_SH_VECALIGN
); break;
7944 as_bad (_("internal: bad mips opcode (unknown operand type `%c'): %s %s"),
7945 c
, opc
->name
, opc
->args
);
7949 if (used_bits
!= 0xffffffff)
7951 as_bad (_("internal: bad mips opcode (bits 0x%lx undefined): %s %s"),
7952 ~used_bits
& 0xffffffff, opc
->name
, opc
->args
);
7958 /* This routine assembles an instruction into its binary format. As a
7959 side effect, it sets one of the global variables imm_reloc or
7960 offset_reloc to the type of relocation to do if one of the operands
7961 is an address expression. */
7964 mips_ip (char *str
, struct mips_cl_insn
*ip
)
7969 struct mips_opcode
*insn
;
7972 unsigned int lastregno
= 0;
7973 unsigned int lastpos
= 0;
7974 unsigned int limlo
, limhi
;
7980 /* If the instruction contains a '.', we first try to match an instruction
7981 including the '.'. Then we try again without the '.'. */
7983 for (s
= str
; *s
!= '\0' && !ISSPACE (*s
); ++s
)
7986 /* If we stopped on whitespace, then replace the whitespace with null for
7987 the call to hash_find. Save the character we replaced just in case we
7988 have to re-parse the instruction. */
7995 insn
= (struct mips_opcode
*) hash_find (op_hash
, str
);
7997 /* If we didn't find the instruction in the opcode table, try again, but
7998 this time with just the instruction up to, but not including the
8002 /* Restore the character we overwrite above (if any). */
8006 /* Scan up to the first '.' or whitespace. */
8008 *s
!= '\0' && *s
!= '.' && !ISSPACE (*s
);
8012 /* If we did not find a '.', then we can quit now. */
8015 insn_error
= "unrecognized opcode";
8019 /* Lookup the instruction in the hash table. */
8021 if ((insn
= (struct mips_opcode
*) hash_find (op_hash
, str
)) == NULL
)
8023 insn_error
= "unrecognized opcode";
8033 assert (strcmp (insn
->name
, str
) == 0);
8035 if (OPCODE_IS_MEMBER (insn
,
8037 | (file_ase_mips16
? INSN_MIPS16
: 0)
8038 | (mips_opts
.ase_mdmx
? INSN_MDMX
: 0)
8039 | (mips_opts
.ase_mips3d
? INSN_MIPS3D
: 0)),
8045 if (insn
->pinfo
!= INSN_MACRO
)
8047 if (mips_opts
.arch
== CPU_R4650
&& (insn
->pinfo
& FP_D
) != 0)
8053 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
]
8054 && strcmp (insn
->name
, insn
[1].name
) == 0)
8063 static char buf
[100];
8065 _("opcode not supported on this processor: %s (%s)"),
8066 mips_cpu_info_from_arch (mips_opts
.arch
)->name
,
8067 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
8077 ip
->insn_opcode
= insn
->match
;
8079 for (args
= insn
->args
;; ++args
)
8083 s
+= strspn (s
, " \t");
8087 case '\0': /* end of args */
8100 ip
->insn_opcode
|= lastregno
<< OP_SH_RS
;
8104 ip
->insn_opcode
|= lastregno
<< OP_SH_RT
;
8108 ip
->insn_opcode
|= lastregno
<< OP_SH_FT
;
8112 ip
->insn_opcode
|= lastregno
<< OP_SH_FS
;
8118 /* Handle optional base register.
8119 Either the base register is omitted or
8120 we must have a left paren. */
8121 /* This is dependent on the next operand specifier
8122 is a base register specification. */
8123 assert (args
[1] == 'b' || args
[1] == '5'
8124 || args
[1] == '-' || args
[1] == '4');
8128 case ')': /* these must match exactly */
8135 case '+': /* Opcode extension character. */
8138 case 'A': /* ins/ext position, becomes LSB. */
8147 my_getExpression (&imm_expr
, s
);
8148 check_absolute_expr (ip
, &imm_expr
);
8149 if ((unsigned long) imm_expr
.X_add_number
< limlo
8150 || (unsigned long) imm_expr
.X_add_number
> limhi
)
8152 as_bad (_("Improper position (%lu)"),
8153 (unsigned long) imm_expr
.X_add_number
);
8154 imm_expr
.X_add_number
= limlo
;
8156 lastpos
= imm_expr
.X_add_number
;
8157 ip
->insn_opcode
|= (imm_expr
.X_add_number
8158 & OP_MASK_SHAMT
) << OP_SH_SHAMT
;
8159 imm_expr
.X_op
= O_absent
;
8163 case 'B': /* ins size, becomes MSB. */
8172 my_getExpression (&imm_expr
, s
);
8173 check_absolute_expr (ip
, &imm_expr
);
8174 /* Check for negative input so that small negative numbers
8175 will not succeed incorrectly. The checks against
8176 (pos+size) transitively check "size" itself,
8177 assuming that "pos" is reasonable. */
8178 if ((long) imm_expr
.X_add_number
< 0
8179 || ((unsigned long) imm_expr
.X_add_number
8181 || ((unsigned long) imm_expr
.X_add_number
8184 as_bad (_("Improper insert size (%lu, position %lu)"),
8185 (unsigned long) imm_expr
.X_add_number
,
8186 (unsigned long) lastpos
);
8187 imm_expr
.X_add_number
= limlo
- lastpos
;
8189 ip
->insn_opcode
|= ((lastpos
+ imm_expr
.X_add_number
- 1)
8190 & OP_MASK_INSMSB
) << OP_SH_INSMSB
;
8191 imm_expr
.X_op
= O_absent
;
8195 case 'C': /* ext size, becomes MSBD. */
8208 my_getExpression (&imm_expr
, s
);
8209 check_absolute_expr (ip
, &imm_expr
);
8210 /* Check for negative input so that small negative numbers
8211 will not succeed incorrectly. The checks against
8212 (pos+size) transitively check "size" itself,
8213 assuming that "pos" is reasonable. */
8214 if ((long) imm_expr
.X_add_number
< 0
8215 || ((unsigned long) imm_expr
.X_add_number
8217 || ((unsigned long) imm_expr
.X_add_number
8220 as_bad (_("Improper extract size (%lu, position %lu)"),
8221 (unsigned long) imm_expr
.X_add_number
,
8222 (unsigned long) lastpos
);
8223 imm_expr
.X_add_number
= limlo
- lastpos
;
8225 ip
->insn_opcode
|= ((imm_expr
.X_add_number
- 1)
8226 & OP_MASK_EXTMSBD
) << OP_SH_EXTMSBD
;
8227 imm_expr
.X_op
= O_absent
;
8232 /* +D is for disassembly only; never match. */
8236 /* "+I" is like "I", except that imm2_expr is used. */
8237 my_getExpression (&imm2_expr
, s
);
8238 if (imm2_expr
.X_op
!= O_big
8239 && imm2_expr
.X_op
!= O_constant
)
8240 insn_error
= _("absolute expression required");
8241 normalize_constant_expr (&imm2_expr
);
8246 as_bad (_("internal: bad mips opcode (unknown extension operand type `+%c'): %s %s"),
8247 *args
, insn
->name
, insn
->args
);
8248 /* Further processing is fruitless. */
8253 case '<': /* must be at least one digit */
8255 * According to the manual, if the shift amount is greater
8256 * than 31 or less than 0, then the shift amount should be
8257 * mod 32. In reality the mips assembler issues an error.
8258 * We issue a warning and mask out all but the low 5 bits.
8260 my_getExpression (&imm_expr
, s
);
8261 check_absolute_expr (ip
, &imm_expr
);
8262 if ((unsigned long) imm_expr
.X_add_number
> 31)
8264 as_warn (_("Improper shift amount (%lu)"),
8265 (unsigned long) imm_expr
.X_add_number
);
8266 imm_expr
.X_add_number
&= OP_MASK_SHAMT
;
8268 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_SHAMT
;
8269 imm_expr
.X_op
= O_absent
;
8273 case '>': /* shift amount minus 32 */
8274 my_getExpression (&imm_expr
, s
);
8275 check_absolute_expr (ip
, &imm_expr
);
8276 if ((unsigned long) imm_expr
.X_add_number
< 32
8277 || (unsigned long) imm_expr
.X_add_number
> 63)
8279 ip
->insn_opcode
|= (imm_expr
.X_add_number
- 32) << OP_SH_SHAMT
;
8280 imm_expr
.X_op
= O_absent
;
8284 case 'k': /* cache code */
8285 case 'h': /* prefx code */
8286 my_getExpression (&imm_expr
, s
);
8287 check_absolute_expr (ip
, &imm_expr
);
8288 if ((unsigned long) imm_expr
.X_add_number
> 31)
8290 as_warn (_("Invalid value for `%s' (%lu)"),
8292 (unsigned long) imm_expr
.X_add_number
);
8293 imm_expr
.X_add_number
&= 0x1f;
8296 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_CACHE
;
8298 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_PREFX
;
8299 imm_expr
.X_op
= O_absent
;
8303 case 'c': /* break code */
8304 my_getExpression (&imm_expr
, s
);
8305 check_absolute_expr (ip
, &imm_expr
);
8306 if ((unsigned long) imm_expr
.X_add_number
> 1023)
8308 as_warn (_("Illegal break code (%lu)"),
8309 (unsigned long) imm_expr
.X_add_number
);
8310 imm_expr
.X_add_number
&= OP_MASK_CODE
;
8312 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_CODE
;
8313 imm_expr
.X_op
= O_absent
;
8317 case 'q': /* lower break code */
8318 my_getExpression (&imm_expr
, s
);
8319 check_absolute_expr (ip
, &imm_expr
);
8320 if ((unsigned long) imm_expr
.X_add_number
> 1023)
8322 as_warn (_("Illegal lower break code (%lu)"),
8323 (unsigned long) imm_expr
.X_add_number
);
8324 imm_expr
.X_add_number
&= OP_MASK_CODE2
;
8326 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_CODE2
;
8327 imm_expr
.X_op
= O_absent
;
8331 case 'B': /* 20-bit syscall/break code. */
8332 my_getExpression (&imm_expr
, s
);
8333 check_absolute_expr (ip
, &imm_expr
);
8334 if ((unsigned long) imm_expr
.X_add_number
> OP_MASK_CODE20
)
8335 as_warn (_("Illegal 20-bit code (%lu)"),
8336 (unsigned long) imm_expr
.X_add_number
);
8337 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_CODE20
;
8338 imm_expr
.X_op
= O_absent
;
8342 case 'C': /* Coprocessor code */
8343 my_getExpression (&imm_expr
, s
);
8344 check_absolute_expr (ip
, &imm_expr
);
8345 if ((unsigned long) imm_expr
.X_add_number
>= (1 << 25))
8347 as_warn (_("Coproccesor code > 25 bits (%lu)"),
8348 (unsigned long) imm_expr
.X_add_number
);
8349 imm_expr
.X_add_number
&= ((1 << 25) - 1);
8351 ip
->insn_opcode
|= imm_expr
.X_add_number
;
8352 imm_expr
.X_op
= O_absent
;
8356 case 'J': /* 19-bit wait code. */
8357 my_getExpression (&imm_expr
, s
);
8358 check_absolute_expr (ip
, &imm_expr
);
8359 if ((unsigned long) imm_expr
.X_add_number
> OP_MASK_CODE19
)
8360 as_warn (_("Illegal 19-bit code (%lu)"),
8361 (unsigned long) imm_expr
.X_add_number
);
8362 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_CODE19
;
8363 imm_expr
.X_op
= O_absent
;
8367 case 'P': /* Performance register */
8368 my_getExpression (&imm_expr
, s
);
8369 check_absolute_expr (ip
, &imm_expr
);
8370 if (imm_expr
.X_add_number
!= 0 && imm_expr
.X_add_number
!= 1)
8372 as_warn (_("Invalid performance register (%lu)"),
8373 (unsigned long) imm_expr
.X_add_number
);
8374 imm_expr
.X_add_number
&= OP_MASK_PERFREG
;
8376 ip
->insn_opcode
|= (imm_expr
.X_add_number
<< OP_SH_PERFREG
);
8377 imm_expr
.X_op
= O_absent
;
8381 case 'b': /* base register */
8382 case 'd': /* destination register */
8383 case 's': /* source register */
8384 case 't': /* target register */
8385 case 'r': /* both target and source */
8386 case 'v': /* both dest and source */
8387 case 'w': /* both dest and target */
8388 case 'E': /* coprocessor target register */
8389 case 'G': /* coprocessor destination register */
8390 case 'K': /* 'rdhwr' destination register */
8391 case 'x': /* ignore register name */
8392 case 'z': /* must be zero register */
8393 case 'U': /* destination register (clo/clz). */
8408 while (ISDIGIT (*s
));
8410 as_bad (_("Invalid register number (%d)"), regno
);
8412 else if (*args
== 'E' || *args
== 'G' || *args
== 'K')
8416 if (s
[1] == 'r' && s
[2] == 'a')
8421 else if (s
[1] == 'f' && s
[2] == 'p')
8426 else if (s
[1] == 's' && s
[2] == 'p')
8431 else if (s
[1] == 'g' && s
[2] == 'p')
8436 else if (s
[1] == 'a' && s
[2] == 't')
8441 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '0')
8446 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '1')
8451 else if (s
[1] == 'z' && s
[2] == 'e' && s
[3] == 'r' && s
[4] == 'o')
8456 else if (itbl_have_entries
)
8461 p
= s
+ 1; /* advance past '$' */
8462 n
= itbl_get_field (&p
); /* n is name */
8464 /* See if this is a register defined in an
8466 if (itbl_get_reg_val (n
, &r
))
8468 /* Get_field advances to the start of
8469 the next field, so we need to back
8470 rack to the end of the last field. */
8474 s
= strchr (s
, '\0');
8488 as_warn (_("Used $at without \".set noat\""));
8494 if (c
== 'r' || c
== 'v' || c
== 'w')
8501 /* 'z' only matches $0. */
8502 if (c
== 'z' && regno
!= 0)
8505 /* Now that we have assembled one operand, we use the args string
8506 * to figure out where it goes in the instruction. */
8513 ip
->insn_opcode
|= regno
<< OP_SH_RS
;
8518 ip
->insn_opcode
|= regno
<< OP_SH_RD
;
8521 ip
->insn_opcode
|= regno
<< OP_SH_RD
;
8522 ip
->insn_opcode
|= regno
<< OP_SH_RT
;
8527 ip
->insn_opcode
|= regno
<< OP_SH_RT
;
8530 /* This case exists because on the r3000 trunc
8531 expands into a macro which requires a gp
8532 register. On the r6000 or r4000 it is
8533 assembled into a single instruction which
8534 ignores the register. Thus the insn version
8535 is MIPS_ISA2 and uses 'x', and the macro
8536 version is MIPS_ISA1 and uses 't'. */
8539 /* This case is for the div instruction, which
8540 acts differently if the destination argument
8541 is $0. This only matches $0, and is checked
8542 outside the switch. */
8545 /* Itbl operand; not yet implemented. FIXME ?? */
8547 /* What about all other operands like 'i', which
8548 can be specified in the opcode table? */
8558 ip
->insn_opcode
|= lastregno
<< OP_SH_RS
;
8561 ip
->insn_opcode
|= lastregno
<< OP_SH_RT
;
8566 case 'O': /* MDMX alignment immediate constant. */
8567 my_getExpression (&imm_expr
, s
);
8568 check_absolute_expr (ip
, &imm_expr
);
8569 if ((unsigned long) imm_expr
.X_add_number
> OP_MASK_ALN
)
8571 as_warn ("Improper align amount (%ld), using low bits",
8572 (long) imm_expr
.X_add_number
);
8573 imm_expr
.X_add_number
&= OP_MASK_ALN
;
8575 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_ALN
;
8576 imm_expr
.X_op
= O_absent
;
8580 case 'Q': /* MDMX vector, element sel, or const. */
8583 /* MDMX Immediate. */
8584 my_getExpression (&imm_expr
, s
);
8585 check_absolute_expr (ip
, &imm_expr
);
8586 if ((unsigned long) imm_expr
.X_add_number
> OP_MASK_FT
)
8588 as_warn (_("Invalid MDMX Immediate (%ld)"),
8589 (long) imm_expr
.X_add_number
);
8590 imm_expr
.X_add_number
&= OP_MASK_FT
;
8592 imm_expr
.X_add_number
&= OP_MASK_FT
;
8593 if (ip
->insn_opcode
& (OP_MASK_VSEL
<< OP_SH_VSEL
))
8594 ip
->insn_opcode
|= MDMX_FMTSEL_IMM_QH
<< OP_SH_VSEL
;
8596 ip
->insn_opcode
|= MDMX_FMTSEL_IMM_OB
<< OP_SH_VSEL
;
8597 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_FT
;
8598 imm_expr
.X_op
= O_absent
;
8602 /* Not MDMX Immediate. Fall through. */
8603 case 'X': /* MDMX destination register. */
8604 case 'Y': /* MDMX source register. */
8605 case 'Z': /* MDMX target register. */
8607 case 'D': /* floating point destination register */
8608 case 'S': /* floating point source register */
8609 case 'T': /* floating point target register */
8610 case 'R': /* floating point source register */
8614 /* Accept $fN for FP and MDMX register numbers, and in
8615 addition accept $vN for MDMX register numbers. */
8616 if ((s
[0] == '$' && s
[1] == 'f' && ISDIGIT (s
[2]))
8617 || (is_mdmx
!= 0 && s
[0] == '$' && s
[1] == 'v'
8628 while (ISDIGIT (*s
));
8631 as_bad (_("Invalid float register number (%d)"), regno
);
8633 if ((regno
& 1) != 0
8635 && ! (strcmp (str
, "mtc1") == 0
8636 || strcmp (str
, "mfc1") == 0
8637 || strcmp (str
, "lwc1") == 0
8638 || strcmp (str
, "swc1") == 0
8639 || strcmp (str
, "l.s") == 0
8640 || strcmp (str
, "s.s") == 0))
8641 as_warn (_("Float register should be even, was %d"),
8649 if (c
== 'V' || c
== 'W')
8660 ip
->insn_opcode
|= regno
<< OP_SH_FD
;
8665 ip
->insn_opcode
|= regno
<< OP_SH_FS
;
8668 /* This is like 'Z', but also needs to fix the MDMX
8669 vector/scalar select bits. Note that the
8670 scalar immediate case is handled above. */
8673 int is_qh
= (ip
->insn_opcode
& (1 << OP_SH_VSEL
));
8674 int max_el
= (is_qh
? 3 : 7);
8676 my_getExpression(&imm_expr
, s
);
8677 check_absolute_expr (ip
, &imm_expr
);
8679 if (imm_expr
.X_add_number
> max_el
)
8680 as_bad(_("Bad element selector %ld"),
8681 (long) imm_expr
.X_add_number
);
8682 imm_expr
.X_add_number
&= max_el
;
8683 ip
->insn_opcode
|= (imm_expr
.X_add_number
8686 imm_expr
.X_op
= O_absent
;
8688 as_warn(_("Expecting ']' found '%s'"), s
);
8694 if (ip
->insn_opcode
& (OP_MASK_VSEL
<< OP_SH_VSEL
))
8695 ip
->insn_opcode
|= (MDMX_FMTSEL_VEC_QH
8698 ip
->insn_opcode
|= (MDMX_FMTSEL_VEC_OB
<<
8705 ip
->insn_opcode
|= regno
<< OP_SH_FT
;
8708 ip
->insn_opcode
|= regno
<< OP_SH_FR
;
8718 ip
->insn_opcode
|= lastregno
<< OP_SH_FS
;
8721 ip
->insn_opcode
|= lastregno
<< OP_SH_FT
;
8727 my_getExpression (&imm_expr
, s
);
8728 if (imm_expr
.X_op
!= O_big
8729 && imm_expr
.X_op
!= O_constant
)
8730 insn_error
= _("absolute expression required");
8731 normalize_constant_expr (&imm_expr
);
8736 my_getExpression (&offset_expr
, s
);
8737 *imm_reloc
= BFD_RELOC_32
;
8750 unsigned char temp
[8];
8752 unsigned int length
;
8757 /* These only appear as the last operand in an
8758 instruction, and every instruction that accepts
8759 them in any variant accepts them in all variants.
8760 This means we don't have to worry about backing out
8761 any changes if the instruction does not match.
8763 The difference between them is the size of the
8764 floating point constant and where it goes. For 'F'
8765 and 'L' the constant is 64 bits; for 'f' and 'l' it
8766 is 32 bits. Where the constant is placed is based
8767 on how the MIPS assembler does things:
8770 f -- immediate value
8773 The .lit4 and .lit8 sections are only used if
8774 permitted by the -G argument.
8776 The code below needs to know whether the target register
8777 is 32 or 64 bits wide. It relies on the fact 'f' and
8778 'F' are used with GPR-based instructions and 'l' and
8779 'L' are used with FPR-based instructions. */
8781 f64
= *args
== 'F' || *args
== 'L';
8782 using_gprs
= *args
== 'F' || *args
== 'f';
8784 save_in
= input_line_pointer
;
8785 input_line_pointer
= s
;
8786 err
= md_atof (f64
? 'd' : 'f', (char *) temp
, &len
);
8788 s
= input_line_pointer
;
8789 input_line_pointer
= save_in
;
8790 if (err
!= NULL
&& *err
!= '\0')
8792 as_bad (_("Bad floating point constant: %s"), err
);
8793 memset (temp
, '\0', sizeof temp
);
8794 length
= f64
? 8 : 4;
8797 assert (length
== (unsigned) (f64
? 8 : 4));
8801 && (g_switch_value
< 4
8802 || (temp
[0] == 0 && temp
[1] == 0)
8803 || (temp
[2] == 0 && temp
[3] == 0))))
8805 imm_expr
.X_op
= O_constant
;
8806 if (! target_big_endian
)
8807 imm_expr
.X_add_number
= bfd_getl32 (temp
);
8809 imm_expr
.X_add_number
= bfd_getb32 (temp
);
8812 && ! mips_disable_float_construction
8813 /* Constants can only be constructed in GPRs and
8814 copied to FPRs if the GPRs are at least as wide
8815 as the FPRs. Force the constant into memory if
8816 we are using 64-bit FPRs but the GPRs are only
8819 || ! (HAVE_64BIT_FPRS
&& HAVE_32BIT_GPRS
))
8820 && ((temp
[0] == 0 && temp
[1] == 0)
8821 || (temp
[2] == 0 && temp
[3] == 0))
8822 && ((temp
[4] == 0 && temp
[5] == 0)
8823 || (temp
[6] == 0 && temp
[7] == 0)))
8825 /* The value is simple enough to load with a couple of
8826 instructions. If using 32-bit registers, set
8827 imm_expr to the high order 32 bits and offset_expr to
8828 the low order 32 bits. Otherwise, set imm_expr to
8829 the entire 64 bit constant. */
8830 if (using_gprs
? HAVE_32BIT_GPRS
: HAVE_32BIT_FPRS
)
8832 imm_expr
.X_op
= O_constant
;
8833 offset_expr
.X_op
= O_constant
;
8834 if (! target_big_endian
)
8836 imm_expr
.X_add_number
= bfd_getl32 (temp
+ 4);
8837 offset_expr
.X_add_number
= bfd_getl32 (temp
);
8841 imm_expr
.X_add_number
= bfd_getb32 (temp
);
8842 offset_expr
.X_add_number
= bfd_getb32 (temp
+ 4);
8844 if (offset_expr
.X_add_number
== 0)
8845 offset_expr
.X_op
= O_absent
;
8847 else if (sizeof (imm_expr
.X_add_number
) > 4)
8849 imm_expr
.X_op
= O_constant
;
8850 if (! target_big_endian
)
8851 imm_expr
.X_add_number
= bfd_getl64 (temp
);
8853 imm_expr
.X_add_number
= bfd_getb64 (temp
);
8857 imm_expr
.X_op
= O_big
;
8858 imm_expr
.X_add_number
= 4;
8859 if (! target_big_endian
)
8861 generic_bignum
[0] = bfd_getl16 (temp
);
8862 generic_bignum
[1] = bfd_getl16 (temp
+ 2);
8863 generic_bignum
[2] = bfd_getl16 (temp
+ 4);
8864 generic_bignum
[3] = bfd_getl16 (temp
+ 6);
8868 generic_bignum
[0] = bfd_getb16 (temp
+ 6);
8869 generic_bignum
[1] = bfd_getb16 (temp
+ 4);
8870 generic_bignum
[2] = bfd_getb16 (temp
+ 2);
8871 generic_bignum
[3] = bfd_getb16 (temp
);
8877 const char *newname
;
8880 /* Switch to the right section. */
8882 subseg
= now_subseg
;
8885 default: /* unused default case avoids warnings. */
8887 newname
= RDATA_SECTION_NAME
;
8888 if (g_switch_value
>= 8)
8892 newname
= RDATA_SECTION_NAME
;
8895 assert (g_switch_value
>= 4);
8899 new_seg
= subseg_new (newname
, (subsegT
) 0);
8900 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
8901 bfd_set_section_flags (stdoutput
, new_seg
,
8906 frag_align (*args
== 'l' ? 2 : 3, 0, 0);
8907 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
8908 && strcmp (TARGET_OS
, "elf") != 0)
8909 record_alignment (new_seg
, 4);
8911 record_alignment (new_seg
, *args
== 'l' ? 2 : 3);
8913 as_bad (_("Can't use floating point insn in this section"));
8915 /* Set the argument to the current address in the
8917 offset_expr
.X_op
= O_symbol
;
8918 offset_expr
.X_add_symbol
=
8919 symbol_new ("L0\001", now_seg
,
8920 (valueT
) frag_now_fix (), frag_now
);
8921 offset_expr
.X_add_number
= 0;
8923 /* Put the floating point number into the section. */
8924 p
= frag_more ((int) length
);
8925 memcpy (p
, temp
, length
);
8927 /* Switch back to the original section. */
8928 subseg_set (seg
, subseg
);
8933 case 'i': /* 16 bit unsigned immediate */
8934 case 'j': /* 16 bit signed immediate */
8935 *imm_reloc
= BFD_RELOC_LO16
;
8936 if (my_getSmallExpression (&imm_expr
, imm_reloc
, s
) == 0)
8939 offsetT minval
, maxval
;
8941 more
= (insn
+ 1 < &mips_opcodes
[NUMOPCODES
]
8942 && strcmp (insn
->name
, insn
[1].name
) == 0);
8944 /* If the expression was written as an unsigned number,
8945 only treat it as signed if there are no more
8949 && sizeof (imm_expr
.X_add_number
) <= 4
8950 && imm_expr
.X_op
== O_constant
8951 && imm_expr
.X_add_number
< 0
8952 && imm_expr
.X_unsigned
8956 /* For compatibility with older assemblers, we accept
8957 0x8000-0xffff as signed 16-bit numbers when only
8958 signed numbers are allowed. */
8960 minval
= 0, maxval
= 0xffff;
8962 minval
= -0x8000, maxval
= 0x7fff;
8964 minval
= -0x8000, maxval
= 0xffff;
8966 if (imm_expr
.X_op
!= O_constant
8967 || imm_expr
.X_add_number
< minval
8968 || imm_expr
.X_add_number
> maxval
)
8972 if (imm_expr
.X_op
== O_constant
8973 || imm_expr
.X_op
== O_big
)
8974 as_bad (_("expression out of range"));
8980 case 'o': /* 16 bit offset */
8981 /* Check whether there is only a single bracketed expression
8982 left. If so, it must be the base register and the
8983 constant must be zero. */
8984 if (*s
== '(' && strchr (s
+ 1, '(') == 0)
8986 offset_expr
.X_op
= O_constant
;
8987 offset_expr
.X_add_number
= 0;
8991 /* If this value won't fit into a 16 bit offset, then go
8992 find a macro that will generate the 32 bit offset
8994 if (my_getSmallExpression (&offset_expr
, offset_reloc
, s
) == 0
8995 && (offset_expr
.X_op
!= O_constant
8996 || offset_expr
.X_add_number
>= 0x8000
8997 || offset_expr
.X_add_number
< -0x8000))
9003 case 'p': /* pc relative offset */
9004 *offset_reloc
= BFD_RELOC_16_PCREL_S2
;
9005 my_getExpression (&offset_expr
, s
);
9009 case 'u': /* upper 16 bits */
9010 if (my_getSmallExpression (&imm_expr
, imm_reloc
, s
) == 0
9011 && imm_expr
.X_op
== O_constant
9012 && (imm_expr
.X_add_number
< 0
9013 || imm_expr
.X_add_number
>= 0x10000))
9014 as_bad (_("lui expression not in range 0..65535"));
9018 case 'a': /* 26 bit address */
9019 my_getExpression (&offset_expr
, s
);
9021 *offset_reloc
= BFD_RELOC_MIPS_JMP
;
9024 case 'N': /* 3 bit branch condition code */
9025 case 'M': /* 3 bit compare condition code */
9026 if (strncmp (s
, "$fcc", 4) != 0)
9036 while (ISDIGIT (*s
));
9038 as_bad (_("Invalid condition code register $fcc%d"), regno
);
9039 if ((strcmp(str
+ strlen(str
) - 3, ".ps") == 0
9040 || strcmp(str
+ strlen(str
) - 5, "any2f") == 0
9041 || strcmp(str
+ strlen(str
) - 5, "any2t") == 0)
9042 && (regno
& 1) != 0)
9043 as_warn(_("Condition code register should be even for %s, was %d"),
9045 if ((strcmp(str
+ strlen(str
) - 5, "any4f") == 0
9046 || strcmp(str
+ strlen(str
) - 5, "any4t") == 0)
9047 && (regno
& 3) != 0)
9048 as_warn(_("Condition code register should be 0 or 4 for %s, was %d"),
9051 ip
->insn_opcode
|= regno
<< OP_SH_BCC
;
9053 ip
->insn_opcode
|= regno
<< OP_SH_CCC
;
9057 if (s
[0] == '0' && (s
[1] == 'x' || s
[1] == 'X'))
9068 while (ISDIGIT (*s
));
9071 c
= 8; /* Invalid sel value. */
9074 as_bad (_("invalid coprocessor sub-selection value (0-7)"));
9075 ip
->insn_opcode
|= c
;
9079 /* Must be at least one digit. */
9080 my_getExpression (&imm_expr
, s
);
9081 check_absolute_expr (ip
, &imm_expr
);
9083 if ((unsigned long) imm_expr
.X_add_number
9084 > (unsigned long) OP_MASK_VECBYTE
)
9086 as_bad (_("bad byte vector index (%ld)"),
9087 (long) imm_expr
.X_add_number
);
9088 imm_expr
.X_add_number
= 0;
9091 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_VECBYTE
;
9092 imm_expr
.X_op
= O_absent
;
9097 my_getExpression (&imm_expr
, s
);
9098 check_absolute_expr (ip
, &imm_expr
);
9100 if ((unsigned long) imm_expr
.X_add_number
9101 > (unsigned long) OP_MASK_VECALIGN
)
9103 as_bad (_("bad byte vector index (%ld)"),
9104 (long) imm_expr
.X_add_number
);
9105 imm_expr
.X_add_number
= 0;
9108 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_VECALIGN
;
9109 imm_expr
.X_op
= O_absent
;
9114 as_bad (_("bad char = '%c'\n"), *args
);
9119 /* Args don't match. */
9120 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
9121 !strcmp (insn
->name
, insn
[1].name
))
9125 insn_error
= _("illegal operands");
9130 insn_error
= _("illegal operands");
9135 /* This routine assembles an instruction into its binary format when
9136 assembling for the mips16. As a side effect, it sets one of the
9137 global variables imm_reloc or offset_reloc to the type of
9138 relocation to do if one of the operands is an address expression.
9139 It also sets mips16_small and mips16_ext if the user explicitly
9140 requested a small or extended instruction. */
9143 mips16_ip (char *str
, struct mips_cl_insn
*ip
)
9147 struct mips_opcode
*insn
;
9150 unsigned int lastregno
= 0;
9156 mips16_small
= FALSE
;
9159 for (s
= str
; ISLOWER (*s
); ++s
)
9171 if (s
[1] == 't' && s
[2] == ' ')
9174 mips16_small
= TRUE
;
9178 else if (s
[1] == 'e' && s
[2] == ' ')
9187 insn_error
= _("unknown opcode");
9191 if (mips_opts
.noautoextend
&& ! mips16_ext
)
9192 mips16_small
= TRUE
;
9194 if ((insn
= (struct mips_opcode
*) hash_find (mips16_op_hash
, str
)) == NULL
)
9196 insn_error
= _("unrecognized opcode");
9203 assert (strcmp (insn
->name
, str
) == 0);
9206 ip
->insn_opcode
= insn
->match
;
9207 ip
->use_extend
= FALSE
;
9208 imm_expr
.X_op
= O_absent
;
9209 imm_reloc
[0] = BFD_RELOC_UNUSED
;
9210 imm_reloc
[1] = BFD_RELOC_UNUSED
;
9211 imm_reloc
[2] = BFD_RELOC_UNUSED
;
9212 imm2_expr
.X_op
= O_absent
;
9213 offset_expr
.X_op
= O_absent
;
9214 offset_reloc
[0] = BFD_RELOC_UNUSED
;
9215 offset_reloc
[1] = BFD_RELOC_UNUSED
;
9216 offset_reloc
[2] = BFD_RELOC_UNUSED
;
9217 for (args
= insn
->args
; 1; ++args
)
9224 /* In this switch statement we call break if we did not find
9225 a match, continue if we did find a match, or return if we
9234 /* Stuff the immediate value in now, if we can. */
9235 if (imm_expr
.X_op
== O_constant
9236 && *imm_reloc
> BFD_RELOC_UNUSED
9237 && insn
->pinfo
!= INSN_MACRO
)
9241 switch (*offset_reloc
)
9243 case BFD_RELOC_MIPS16_HI16_S
:
9244 tmp
= (imm_expr
.X_add_number
+ 0x8000) >> 16;
9247 case BFD_RELOC_MIPS16_HI16
:
9248 tmp
= imm_expr
.X_add_number
>> 16;
9251 case BFD_RELOC_MIPS16_LO16
:
9252 tmp
= ((imm_expr
.X_add_number
+ 0x8000) & 0xffff)
9256 case BFD_RELOC_UNUSED
:
9257 tmp
= imm_expr
.X_add_number
;
9263 *offset_reloc
= BFD_RELOC_UNUSED
;
9265 mips16_immed (NULL
, 0, *imm_reloc
- BFD_RELOC_UNUSED
,
9266 tmp
, TRUE
, mips16_small
,
9267 mips16_ext
, &ip
->insn_opcode
,
9268 &ip
->use_extend
, &ip
->extend
);
9269 imm_expr
.X_op
= O_absent
;
9270 *imm_reloc
= BFD_RELOC_UNUSED
;
9284 ip
->insn_opcode
|= lastregno
<< MIPS16OP_SH_RX
;
9287 ip
->insn_opcode
|= lastregno
<< MIPS16OP_SH_RY
;
9303 ip
->insn_opcode
|= lastregno
<< MIPS16OP_SH_RX
;
9305 ip
->insn_opcode
|= lastregno
<< MIPS16OP_SH_RY
;
9332 while (ISDIGIT (*s
));
9335 as_bad (_("invalid register number (%d)"), regno
);
9341 if (s
[1] == 'r' && s
[2] == 'a')
9346 else if (s
[1] == 'f' && s
[2] == 'p')
9351 else if (s
[1] == 's' && s
[2] == 'p')
9356 else if (s
[1] == 'g' && s
[2] == 'p')
9361 else if (s
[1] == 'a' && s
[2] == 't')
9366 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '0')
9371 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '1')
9376 else if (s
[1] == 'z' && s
[2] == 'e' && s
[3] == 'r' && s
[4] == 'o')
9389 if (c
== 'v' || c
== 'w')
9391 regno
= mips16_to_32_reg_map
[lastregno
];
9405 regno
= mips32_to_16_reg_map
[regno
];
9410 regno
= ILLEGAL_REG
;
9415 regno
= ILLEGAL_REG
;
9420 regno
= ILLEGAL_REG
;
9425 if (regno
== AT
&& ! mips_opts
.noat
)
9426 as_warn (_("used $at without \".set noat\""));
9433 if (regno
== ILLEGAL_REG
)
9440 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_RX
;
9444 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_RY
;
9447 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_RZ
;
9450 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_MOVE32Z
;
9456 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_REGR32
;
9459 regno
= ((regno
& 7) << 2) | ((regno
& 0x18) >> 3);
9460 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_REG32R
;
9470 if (strncmp (s
, "$pc", 3) == 0)
9487 i
= my_getSmallExpression (&imm_expr
, imm_reloc
, s
);
9490 if (imm_expr
.X_op
!= O_constant
)
9493 ip
->use_extend
= TRUE
;
9498 /* We need to relax this instruction. */
9499 *offset_reloc
= *imm_reloc
;
9500 *imm_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
9505 *imm_reloc
= BFD_RELOC_UNUSED
;
9513 my_getExpression (&imm_expr
, s
);
9514 if (imm_expr
.X_op
== O_register
)
9516 /* What we thought was an expression turned out to
9519 if (s
[0] == '(' && args
[1] == '(')
9521 /* It looks like the expression was omitted
9522 before a register indirection, which means
9523 that the expression is implicitly zero. We
9524 still set up imm_expr, so that we handle
9525 explicit extensions correctly. */
9526 imm_expr
.X_op
= O_constant
;
9527 imm_expr
.X_add_number
= 0;
9528 *imm_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
9535 /* We need to relax this instruction. */
9536 *imm_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
9545 /* We use offset_reloc rather than imm_reloc for the PC
9546 relative operands. This lets macros with both
9547 immediate and address operands work correctly. */
9548 my_getExpression (&offset_expr
, s
);
9550 if (offset_expr
.X_op
== O_register
)
9553 /* We need to relax this instruction. */
9554 *offset_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
9558 case '6': /* break code */
9559 my_getExpression (&imm_expr
, s
);
9560 check_absolute_expr (ip
, &imm_expr
);
9561 if ((unsigned long) imm_expr
.X_add_number
> 63)
9563 as_warn (_("Invalid value for `%s' (%lu)"),
9565 (unsigned long) imm_expr
.X_add_number
);
9566 imm_expr
.X_add_number
&= 0x3f;
9568 ip
->insn_opcode
|= imm_expr
.X_add_number
<< MIPS16OP_SH_IMM6
;
9569 imm_expr
.X_op
= O_absent
;
9573 case 'a': /* 26 bit address */
9574 my_getExpression (&offset_expr
, s
);
9576 *offset_reloc
= BFD_RELOC_MIPS16_JMP
;
9577 ip
->insn_opcode
<<= 16;
9580 case 'l': /* register list for entry macro */
9581 case 'L': /* register list for exit macro */
9591 int freg
, reg1
, reg2
;
9593 while (*s
== ' ' || *s
== ',')
9597 as_bad (_("can't parse register list"));
9609 while (ISDIGIT (*s
))
9631 as_bad (_("invalid register list"));
9636 while (ISDIGIT (*s
))
9643 if (freg
&& reg1
== 0 && reg2
== 0 && c
== 'L')
9648 else if (freg
&& reg1
== 0 && reg2
== 1 && c
== 'L')
9653 else if (reg1
== 4 && reg2
>= 4 && reg2
<= 7 && c
!= 'L')
9654 mask
|= (reg2
- 3) << 3;
9655 else if (reg1
== 16 && reg2
>= 16 && reg2
<= 17)
9656 mask
|= (reg2
- 15) << 1;
9657 else if (reg1
== RA
&& reg2
== RA
)
9661 as_bad (_("invalid register list"));
9665 /* The mask is filled in in the opcode table for the
9666 benefit of the disassembler. We remove it before
9667 applying the actual mask. */
9668 ip
->insn_opcode
&= ~ ((7 << 3) << MIPS16OP_SH_IMM6
);
9669 ip
->insn_opcode
|= mask
<< MIPS16OP_SH_IMM6
;
9673 case 'e': /* extend code */
9674 my_getExpression (&imm_expr
, s
);
9675 check_absolute_expr (ip
, &imm_expr
);
9676 if ((unsigned long) imm_expr
.X_add_number
> 0x7ff)
9678 as_warn (_("Invalid value for `%s' (%lu)"),
9680 (unsigned long) imm_expr
.X_add_number
);
9681 imm_expr
.X_add_number
&= 0x7ff;
9683 ip
->insn_opcode
|= imm_expr
.X_add_number
;
9684 imm_expr
.X_op
= O_absent
;
9694 /* Args don't match. */
9695 if (insn
+ 1 < &mips16_opcodes
[bfd_mips16_num_opcodes
] &&
9696 strcmp (insn
->name
, insn
[1].name
) == 0)
9703 insn_error
= _("illegal operands");
9709 /* This structure holds information we know about a mips16 immediate
9712 struct mips16_immed_operand
9714 /* The type code used in the argument string in the opcode table. */
9716 /* The number of bits in the short form of the opcode. */
9718 /* The number of bits in the extended form of the opcode. */
9720 /* The amount by which the short form is shifted when it is used;
9721 for example, the sw instruction has a shift count of 2. */
9723 /* The amount by which the short form is shifted when it is stored
9724 into the instruction code. */
9726 /* Non-zero if the short form is unsigned. */
9728 /* Non-zero if the extended form is unsigned. */
9730 /* Non-zero if the value is PC relative. */
9734 /* The mips16 immediate operand types. */
9736 static const struct mips16_immed_operand mips16_immed_operands
[] =
9738 { '<', 3, 5, 0, MIPS16OP_SH_RZ
, 1, 1, 0 },
9739 { '>', 3, 5, 0, MIPS16OP_SH_RX
, 1, 1, 0 },
9740 { '[', 3, 6, 0, MIPS16OP_SH_RZ
, 1, 1, 0 },
9741 { ']', 3, 6, 0, MIPS16OP_SH_RX
, 1, 1, 0 },
9742 { '4', 4, 15, 0, MIPS16OP_SH_IMM4
, 0, 0, 0 },
9743 { '5', 5, 16, 0, MIPS16OP_SH_IMM5
, 1, 0, 0 },
9744 { 'H', 5, 16, 1, MIPS16OP_SH_IMM5
, 1, 0, 0 },
9745 { 'W', 5, 16, 2, MIPS16OP_SH_IMM5
, 1, 0, 0 },
9746 { 'D', 5, 16, 3, MIPS16OP_SH_IMM5
, 1, 0, 0 },
9747 { 'j', 5, 16, 0, MIPS16OP_SH_IMM5
, 0, 0, 0 },
9748 { '8', 8, 16, 0, MIPS16OP_SH_IMM8
, 1, 0, 0 },
9749 { 'V', 8, 16, 2, MIPS16OP_SH_IMM8
, 1, 0, 0 },
9750 { 'C', 8, 16, 3, MIPS16OP_SH_IMM8
, 1, 0, 0 },
9751 { 'U', 8, 16, 0, MIPS16OP_SH_IMM8
, 1, 1, 0 },
9752 { 'k', 8, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 0 },
9753 { 'K', 8, 16, 3, MIPS16OP_SH_IMM8
, 0, 0, 0 },
9754 { 'p', 8, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 1 },
9755 { 'q', 11, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 1 },
9756 { 'A', 8, 16, 2, MIPS16OP_SH_IMM8
, 1, 0, 1 },
9757 { 'B', 5, 16, 3, MIPS16OP_SH_IMM5
, 1, 0, 1 },
9758 { 'E', 5, 16, 2, MIPS16OP_SH_IMM5
, 1, 0, 1 }
9761 #define MIPS16_NUM_IMMED \
9762 (sizeof mips16_immed_operands / sizeof mips16_immed_operands[0])
9764 /* Handle a mips16 instruction with an immediate value. This or's the
9765 small immediate value into *INSN. It sets *USE_EXTEND to indicate
9766 whether an extended value is needed; if one is needed, it sets
9767 *EXTEND to the value. The argument type is TYPE. The value is VAL.
9768 If SMALL is true, an unextended opcode was explicitly requested.
9769 If EXT is true, an extended opcode was explicitly requested. If
9770 WARN is true, warn if EXT does not match reality. */
9773 mips16_immed (char *file
, unsigned int line
, int type
, offsetT val
,
9774 bfd_boolean warn
, bfd_boolean small
, bfd_boolean ext
,
9775 unsigned long *insn
, bfd_boolean
*use_extend
,
9776 unsigned short *extend
)
9778 register const struct mips16_immed_operand
*op
;
9779 int mintiny
, maxtiny
;
9780 bfd_boolean needext
;
9782 op
= mips16_immed_operands
;
9783 while (op
->type
!= type
)
9786 assert (op
< mips16_immed_operands
+ MIPS16_NUM_IMMED
);
9791 if (type
== '<' || type
== '>' || type
== '[' || type
== ']')
9794 maxtiny
= 1 << op
->nbits
;
9799 maxtiny
= (1 << op
->nbits
) - 1;
9804 mintiny
= - (1 << (op
->nbits
- 1));
9805 maxtiny
= (1 << (op
->nbits
- 1)) - 1;
9808 /* Branch offsets have an implicit 0 in the lowest bit. */
9809 if (type
== 'p' || type
== 'q')
9812 if ((val
& ((1 << op
->shift
) - 1)) != 0
9813 || val
< (mintiny
<< op
->shift
)
9814 || val
> (maxtiny
<< op
->shift
))
9819 if (warn
&& ext
&& ! needext
)
9820 as_warn_where (file
, line
,
9821 _("extended operand requested but not required"));
9822 if (small
&& needext
)
9823 as_bad_where (file
, line
, _("invalid unextended operand value"));
9825 if (small
|| (! ext
&& ! needext
))
9829 *use_extend
= FALSE
;
9830 insnval
= ((val
>> op
->shift
) & ((1 << op
->nbits
) - 1));
9831 insnval
<<= op
->op_shift
;
9836 long minext
, maxext
;
9842 maxext
= (1 << op
->extbits
) - 1;
9846 minext
= - (1 << (op
->extbits
- 1));
9847 maxext
= (1 << (op
->extbits
- 1)) - 1;
9849 if (val
< minext
|| val
> maxext
)
9850 as_bad_where (file
, line
,
9851 _("operand value out of range for instruction"));
9854 if (op
->extbits
== 16)
9856 extval
= ((val
>> 11) & 0x1f) | (val
& 0x7e0);
9859 else if (op
->extbits
== 15)
9861 extval
= ((val
>> 11) & 0xf) | (val
& 0x7f0);
9866 extval
= ((val
& 0x1f) << 6) | (val
& 0x20);
9870 *extend
= (unsigned short) extval
;
9875 struct percent_op_match
9878 bfd_reloc_code_real_type reloc
;
9881 static const struct percent_op_match mips_percent_op
[] =
9883 {"%lo", BFD_RELOC_LO16
},
9885 {"%call_hi", BFD_RELOC_MIPS_CALL_HI16
},
9886 {"%call_lo", BFD_RELOC_MIPS_CALL_LO16
},
9887 {"%call16", BFD_RELOC_MIPS_CALL16
},
9888 {"%got_disp", BFD_RELOC_MIPS_GOT_DISP
},
9889 {"%got_page", BFD_RELOC_MIPS_GOT_PAGE
},
9890 {"%got_ofst", BFD_RELOC_MIPS_GOT_OFST
},
9891 {"%got_hi", BFD_RELOC_MIPS_GOT_HI16
},
9892 {"%got_lo", BFD_RELOC_MIPS_GOT_LO16
},
9893 {"%got", BFD_RELOC_MIPS_GOT16
},
9894 {"%gp_rel", BFD_RELOC_GPREL16
},
9895 {"%half", BFD_RELOC_16
},
9896 {"%highest", BFD_RELOC_MIPS_HIGHEST
},
9897 {"%higher", BFD_RELOC_MIPS_HIGHER
},
9898 {"%neg", BFD_RELOC_MIPS_SUB
},
9899 {"%tlsgd", BFD_RELOC_MIPS_TLS_GD
},
9900 {"%tlsldm", BFD_RELOC_MIPS_TLS_LDM
},
9901 {"%dtprel_hi", BFD_RELOC_MIPS_TLS_DTPREL_HI16
},
9902 {"%dtprel_lo", BFD_RELOC_MIPS_TLS_DTPREL_LO16
},
9903 {"%tprel_hi", BFD_RELOC_MIPS_TLS_TPREL_HI16
},
9904 {"%tprel_lo", BFD_RELOC_MIPS_TLS_TPREL_LO16
},
9905 {"%gottprel", BFD_RELOC_MIPS_TLS_GOTTPREL
},
9907 {"%hi", BFD_RELOC_HI16_S
}
9910 static const struct percent_op_match mips16_percent_op
[] =
9912 {"%lo", BFD_RELOC_MIPS16_LO16
},
9913 {"%gprel", BFD_RELOC_MIPS16_GPREL
},
9914 {"%hi", BFD_RELOC_MIPS16_HI16_S
}
9918 /* Return true if *STR points to a relocation operator. When returning true,
9919 move *STR over the operator and store its relocation code in *RELOC.
9920 Leave both *STR and *RELOC alone when returning false. */
9923 parse_relocation (char **str
, bfd_reloc_code_real_type
*reloc
)
9925 const struct percent_op_match
*percent_op
;
9928 if (mips_opts
.mips16
)
9930 percent_op
= mips16_percent_op
;
9931 limit
= ARRAY_SIZE (mips16_percent_op
);
9935 percent_op
= mips_percent_op
;
9936 limit
= ARRAY_SIZE (mips_percent_op
);
9939 for (i
= 0; i
< limit
; i
++)
9940 if (strncasecmp (*str
, percent_op
[i
].str
, strlen (percent_op
[i
].str
)) == 0)
9942 int len
= strlen (percent_op
[i
].str
);
9944 if (!ISSPACE ((*str
)[len
]) && (*str
)[len
] != '(')
9947 *str
+= strlen (percent_op
[i
].str
);
9948 *reloc
= percent_op
[i
].reloc
;
9950 /* Check whether the output BFD supports this relocation.
9951 If not, issue an error and fall back on something safe. */
9952 if (!bfd_reloc_type_lookup (stdoutput
, percent_op
[i
].reloc
))
9954 as_bad ("relocation %s isn't supported by the current ABI",
9956 *reloc
= BFD_RELOC_UNUSED
;
9964 /* Parse string STR as a 16-bit relocatable operand. Store the
9965 expression in *EP and the relocations in the array starting
9966 at RELOC. Return the number of relocation operators used.
9968 On exit, EXPR_END points to the first character after the expression. */
9971 my_getSmallExpression (expressionS
*ep
, bfd_reloc_code_real_type
*reloc
,
9974 bfd_reloc_code_real_type reversed_reloc
[3];
9975 size_t reloc_index
, i
;
9976 int crux_depth
, str_depth
;
9979 /* Search for the start of the main expression, recoding relocations
9980 in REVERSED_RELOC. End the loop with CRUX pointing to the start
9981 of the main expression and with CRUX_DEPTH containing the number
9982 of open brackets at that point. */
9989 crux_depth
= str_depth
;
9991 /* Skip over whitespace and brackets, keeping count of the number
9993 while (*str
== ' ' || *str
== '\t' || *str
== '(')
9998 && reloc_index
< (HAVE_NEWABI
? 3 : 1)
9999 && parse_relocation (&str
, &reversed_reloc
[reloc_index
]));
10001 my_getExpression (ep
, crux
);
10004 /* Match every open bracket. */
10005 while (crux_depth
> 0 && (*str
== ')' || *str
== ' ' || *str
== '\t'))
10009 if (crux_depth
> 0)
10010 as_bad ("unclosed '('");
10014 if (reloc_index
!= 0)
10016 prev_reloc_op_frag
= frag_now
;
10017 for (i
= 0; i
< reloc_index
; i
++)
10018 reloc
[i
] = reversed_reloc
[reloc_index
- 1 - i
];
10021 return reloc_index
;
10025 my_getExpression (expressionS
*ep
, char *str
)
10030 save_in
= input_line_pointer
;
10031 input_line_pointer
= str
;
10033 expr_end
= input_line_pointer
;
10034 input_line_pointer
= save_in
;
10036 /* If we are in mips16 mode, and this is an expression based on `.',
10037 then we bump the value of the symbol by 1 since that is how other
10038 text symbols are handled. We don't bother to handle complex
10039 expressions, just `.' plus or minus a constant. */
10040 if (mips_opts
.mips16
10041 && ep
->X_op
== O_symbol
10042 && strcmp (S_GET_NAME (ep
->X_add_symbol
), FAKE_LABEL_NAME
) == 0
10043 && S_GET_SEGMENT (ep
->X_add_symbol
) == now_seg
10044 && symbol_get_frag (ep
->X_add_symbol
) == frag_now
10045 && symbol_constant_p (ep
->X_add_symbol
)
10046 && (val
= S_GET_VALUE (ep
->X_add_symbol
)) == frag_now_fix ())
10047 S_SET_VALUE (ep
->X_add_symbol
, val
+ 1);
10050 /* Turn a string in input_line_pointer into a floating point constant
10051 of type TYPE, and store the appropriate bytes in *LITP. The number
10052 of LITTLENUMS emitted is stored in *SIZEP. An error message is
10053 returned, or NULL on OK. */
10056 md_atof (int type
, char *litP
, int *sizeP
)
10059 LITTLENUM_TYPE words
[4];
10075 return _("bad call to md_atof");
10078 t
= atof_ieee (input_line_pointer
, type
, words
);
10080 input_line_pointer
= t
;
10084 if (! target_big_endian
)
10086 for (i
= prec
- 1; i
>= 0; i
--)
10088 md_number_to_chars (litP
, words
[i
], 2);
10094 for (i
= 0; i
< prec
; i
++)
10096 md_number_to_chars (litP
, words
[i
], 2);
10105 md_number_to_chars (char *buf
, valueT val
, int n
)
10107 if (target_big_endian
)
10108 number_to_chars_bigendian (buf
, val
, n
);
10110 number_to_chars_littleendian (buf
, val
, n
);
10114 static int support_64bit_objects(void)
10116 const char **list
, **l
;
10119 list
= bfd_target_list ();
10120 for (l
= list
; *l
!= NULL
; l
++)
10122 /* This is traditional mips */
10123 if (strcmp (*l
, "elf64-tradbigmips") == 0
10124 || strcmp (*l
, "elf64-tradlittlemips") == 0)
10126 if (strcmp (*l
, "elf64-bigmips") == 0
10127 || strcmp (*l
, "elf64-littlemips") == 0)
10130 yes
= (*l
!= NULL
);
10134 #endif /* OBJ_ELF */
10136 const char *md_shortopts
= "O::g::G:";
10138 struct option md_longopts
[] =
10140 /* Options which specify architecture. */
10141 #define OPTION_ARCH_BASE (OPTION_MD_BASE)
10142 #define OPTION_MARCH (OPTION_ARCH_BASE + 0)
10143 {"march", required_argument
, NULL
, OPTION_MARCH
},
10144 #define OPTION_MTUNE (OPTION_ARCH_BASE + 1)
10145 {"mtune", required_argument
, NULL
, OPTION_MTUNE
},
10146 #define OPTION_MIPS1 (OPTION_ARCH_BASE + 2)
10147 {"mips0", no_argument
, NULL
, OPTION_MIPS1
},
10148 {"mips1", no_argument
, NULL
, OPTION_MIPS1
},
10149 #define OPTION_MIPS2 (OPTION_ARCH_BASE + 3)
10150 {"mips2", no_argument
, NULL
, OPTION_MIPS2
},
10151 #define OPTION_MIPS3 (OPTION_ARCH_BASE + 4)
10152 {"mips3", no_argument
, NULL
, OPTION_MIPS3
},
10153 #define OPTION_MIPS4 (OPTION_ARCH_BASE + 5)
10154 {"mips4", no_argument
, NULL
, OPTION_MIPS4
},
10155 #define OPTION_MIPS5 (OPTION_ARCH_BASE + 6)
10156 {"mips5", no_argument
, NULL
, OPTION_MIPS5
},
10157 #define OPTION_MIPS32 (OPTION_ARCH_BASE + 7)
10158 {"mips32", no_argument
, NULL
, OPTION_MIPS32
},
10159 #define OPTION_MIPS64 (OPTION_ARCH_BASE + 8)
10160 {"mips64", no_argument
, NULL
, OPTION_MIPS64
},
10161 #define OPTION_MIPS32R2 (OPTION_ARCH_BASE + 9)
10162 {"mips32r2", no_argument
, NULL
, OPTION_MIPS32R2
},
10163 #define OPTION_MIPS64R2 (OPTION_ARCH_BASE + 10)
10164 {"mips64r2", no_argument
, NULL
, OPTION_MIPS64R2
},
10166 /* Options which specify Application Specific Extensions (ASEs). */
10167 #define OPTION_ASE_BASE (OPTION_ARCH_BASE + 11)
10168 #define OPTION_MIPS16 (OPTION_ASE_BASE + 0)
10169 {"mips16", no_argument
, NULL
, OPTION_MIPS16
},
10170 #define OPTION_NO_MIPS16 (OPTION_ASE_BASE + 1)
10171 {"no-mips16", no_argument
, NULL
, OPTION_NO_MIPS16
},
10172 #define OPTION_MIPS3D (OPTION_ASE_BASE + 2)
10173 {"mips3d", no_argument
, NULL
, OPTION_MIPS3D
},
10174 #define OPTION_NO_MIPS3D (OPTION_ASE_BASE + 3)
10175 {"no-mips3d", no_argument
, NULL
, OPTION_NO_MIPS3D
},
10176 #define OPTION_MDMX (OPTION_ASE_BASE + 4)
10177 {"mdmx", no_argument
, NULL
, OPTION_MDMX
},
10178 #define OPTION_NO_MDMX (OPTION_ASE_BASE + 5)
10179 {"no-mdmx", no_argument
, NULL
, OPTION_NO_MDMX
},
10181 /* Old-style architecture options. Don't add more of these. */
10182 #define OPTION_COMPAT_ARCH_BASE (OPTION_ASE_BASE + 6)
10183 #define OPTION_M4650 (OPTION_COMPAT_ARCH_BASE + 0)
10184 {"m4650", no_argument
, NULL
, OPTION_M4650
},
10185 #define OPTION_NO_M4650 (OPTION_COMPAT_ARCH_BASE + 1)
10186 {"no-m4650", no_argument
, NULL
, OPTION_NO_M4650
},
10187 #define OPTION_M4010 (OPTION_COMPAT_ARCH_BASE + 2)
10188 {"m4010", no_argument
, NULL
, OPTION_M4010
},
10189 #define OPTION_NO_M4010 (OPTION_COMPAT_ARCH_BASE + 3)
10190 {"no-m4010", no_argument
, NULL
, OPTION_NO_M4010
},
10191 #define OPTION_M4100 (OPTION_COMPAT_ARCH_BASE + 4)
10192 {"m4100", no_argument
, NULL
, OPTION_M4100
},
10193 #define OPTION_NO_M4100 (OPTION_COMPAT_ARCH_BASE + 5)
10194 {"no-m4100", no_argument
, NULL
, OPTION_NO_M4100
},
10195 #define OPTION_M3900 (OPTION_COMPAT_ARCH_BASE + 6)
10196 {"m3900", no_argument
, NULL
, OPTION_M3900
},
10197 #define OPTION_NO_M3900 (OPTION_COMPAT_ARCH_BASE + 7)
10198 {"no-m3900", no_argument
, NULL
, OPTION_NO_M3900
},
10200 /* Options which enable bug fixes. */
10201 #define OPTION_FIX_BASE (OPTION_COMPAT_ARCH_BASE + 8)
10202 #define OPTION_M7000_HILO_FIX (OPTION_FIX_BASE + 0)
10203 {"mfix7000", no_argument
, NULL
, OPTION_M7000_HILO_FIX
},
10204 #define OPTION_MNO_7000_HILO_FIX (OPTION_FIX_BASE + 1)
10205 {"no-fix-7000", no_argument
, NULL
, OPTION_MNO_7000_HILO_FIX
},
10206 {"mno-fix7000", no_argument
, NULL
, OPTION_MNO_7000_HILO_FIX
},
10207 #define OPTION_FIX_VR4120 (OPTION_FIX_BASE + 2)
10208 #define OPTION_NO_FIX_VR4120 (OPTION_FIX_BASE + 3)
10209 {"mfix-vr4120", no_argument
, NULL
, OPTION_FIX_VR4120
},
10210 {"mno-fix-vr4120", no_argument
, NULL
, OPTION_NO_FIX_VR4120
},
10212 /* Miscellaneous options. */
10213 #define OPTION_MISC_BASE (OPTION_FIX_BASE + 4)
10214 #define OPTION_TRAP (OPTION_MISC_BASE + 0)
10215 {"trap", no_argument
, NULL
, OPTION_TRAP
},
10216 {"no-break", no_argument
, NULL
, OPTION_TRAP
},
10217 #define OPTION_BREAK (OPTION_MISC_BASE + 1)
10218 {"break", no_argument
, NULL
, OPTION_BREAK
},
10219 {"no-trap", no_argument
, NULL
, OPTION_BREAK
},
10220 #define OPTION_EB (OPTION_MISC_BASE + 2)
10221 {"EB", no_argument
, NULL
, OPTION_EB
},
10222 #define OPTION_EL (OPTION_MISC_BASE + 3)
10223 {"EL", no_argument
, NULL
, OPTION_EL
},
10224 #define OPTION_FP32 (OPTION_MISC_BASE + 4)
10225 {"mfp32", no_argument
, NULL
, OPTION_FP32
},
10226 #define OPTION_GP32 (OPTION_MISC_BASE + 5)
10227 {"mgp32", no_argument
, NULL
, OPTION_GP32
},
10228 #define OPTION_CONSTRUCT_FLOATS (OPTION_MISC_BASE + 6)
10229 {"construct-floats", no_argument
, NULL
, OPTION_CONSTRUCT_FLOATS
},
10230 #define OPTION_NO_CONSTRUCT_FLOATS (OPTION_MISC_BASE + 7)
10231 {"no-construct-floats", no_argument
, NULL
, OPTION_NO_CONSTRUCT_FLOATS
},
10232 #define OPTION_FP64 (OPTION_MISC_BASE + 8)
10233 {"mfp64", no_argument
, NULL
, OPTION_FP64
},
10234 #define OPTION_GP64 (OPTION_MISC_BASE + 9)
10235 {"mgp64", no_argument
, NULL
, OPTION_GP64
},
10236 #define OPTION_RELAX_BRANCH (OPTION_MISC_BASE + 10)
10237 #define OPTION_NO_RELAX_BRANCH (OPTION_MISC_BASE + 11)
10238 {"relax-branch", no_argument
, NULL
, OPTION_RELAX_BRANCH
},
10239 {"no-relax-branch", no_argument
, NULL
, OPTION_NO_RELAX_BRANCH
},
10240 #define OPTION_MSHARED (OPTION_MISC_BASE + 12)
10241 #define OPTION_MNO_SHARED (OPTION_MISC_BASE + 13)
10242 {"mshared", no_argument
, NULL
, OPTION_MSHARED
},
10243 {"mno-shared", no_argument
, NULL
, OPTION_MNO_SHARED
},
10245 /* ELF-specific options. */
10247 #define OPTION_ELF_BASE (OPTION_MISC_BASE + 14)
10248 #define OPTION_CALL_SHARED (OPTION_ELF_BASE + 0)
10249 {"KPIC", no_argument
, NULL
, OPTION_CALL_SHARED
},
10250 {"call_shared", no_argument
, NULL
, OPTION_CALL_SHARED
},
10251 #define OPTION_NON_SHARED (OPTION_ELF_BASE + 1)
10252 {"non_shared", no_argument
, NULL
, OPTION_NON_SHARED
},
10253 #define OPTION_XGOT (OPTION_ELF_BASE + 2)
10254 {"xgot", no_argument
, NULL
, OPTION_XGOT
},
10255 #define OPTION_MABI (OPTION_ELF_BASE + 3)
10256 {"mabi", required_argument
, NULL
, OPTION_MABI
},
10257 #define OPTION_32 (OPTION_ELF_BASE + 4)
10258 {"32", no_argument
, NULL
, OPTION_32
},
10259 #define OPTION_N32 (OPTION_ELF_BASE + 5)
10260 {"n32", no_argument
, NULL
, OPTION_N32
},
10261 #define OPTION_64 (OPTION_ELF_BASE + 6)
10262 {"64", no_argument
, NULL
, OPTION_64
},
10263 #define OPTION_MDEBUG (OPTION_ELF_BASE + 7)
10264 {"mdebug", no_argument
, NULL
, OPTION_MDEBUG
},
10265 #define OPTION_NO_MDEBUG (OPTION_ELF_BASE + 8)
10266 {"no-mdebug", no_argument
, NULL
, OPTION_NO_MDEBUG
},
10267 #define OPTION_PDR (OPTION_ELF_BASE + 9)
10268 {"mpdr", no_argument
, NULL
, OPTION_PDR
},
10269 #define OPTION_NO_PDR (OPTION_ELF_BASE + 10)
10270 {"mno-pdr", no_argument
, NULL
, OPTION_NO_PDR
},
10271 #endif /* OBJ_ELF */
10273 {NULL
, no_argument
, NULL
, 0}
10275 size_t md_longopts_size
= sizeof (md_longopts
);
10277 /* Set STRING_PTR (either &mips_arch_string or &mips_tune_string) to
10278 NEW_VALUE. Warn if another value was already specified. Note:
10279 we have to defer parsing the -march and -mtune arguments in order
10280 to handle 'from-abi' correctly, since the ABI might be specified
10281 in a later argument. */
10284 mips_set_option_string (const char **string_ptr
, const char *new_value
)
10286 if (*string_ptr
!= 0 && strcasecmp (*string_ptr
, new_value
) != 0)
10287 as_warn (_("A different %s was already specified, is now %s"),
10288 string_ptr
== &mips_arch_string
? "-march" : "-mtune",
10291 *string_ptr
= new_value
;
10295 md_parse_option (int c
, char *arg
)
10299 case OPTION_CONSTRUCT_FLOATS
:
10300 mips_disable_float_construction
= 0;
10303 case OPTION_NO_CONSTRUCT_FLOATS
:
10304 mips_disable_float_construction
= 1;
10316 target_big_endian
= 1;
10320 target_big_endian
= 0;
10324 if (arg
&& arg
[1] == '0')
10334 mips_debug
= atoi (arg
);
10335 /* When the MIPS assembler sees -g or -g2, it does not do
10336 optimizations which limit full symbolic debugging. We take
10337 that to be equivalent to -O0. */
10338 if (mips_debug
== 2)
10343 file_mips_isa
= ISA_MIPS1
;
10347 file_mips_isa
= ISA_MIPS2
;
10351 file_mips_isa
= ISA_MIPS3
;
10355 file_mips_isa
= ISA_MIPS4
;
10359 file_mips_isa
= ISA_MIPS5
;
10362 case OPTION_MIPS32
:
10363 file_mips_isa
= ISA_MIPS32
;
10366 case OPTION_MIPS32R2
:
10367 file_mips_isa
= ISA_MIPS32R2
;
10370 case OPTION_MIPS64R2
:
10371 file_mips_isa
= ISA_MIPS64R2
;
10374 case OPTION_MIPS64
:
10375 file_mips_isa
= ISA_MIPS64
;
10379 mips_set_option_string (&mips_tune_string
, arg
);
10383 mips_set_option_string (&mips_arch_string
, arg
);
10387 mips_set_option_string (&mips_arch_string
, "4650");
10388 mips_set_option_string (&mips_tune_string
, "4650");
10391 case OPTION_NO_M4650
:
10395 mips_set_option_string (&mips_arch_string
, "4010");
10396 mips_set_option_string (&mips_tune_string
, "4010");
10399 case OPTION_NO_M4010
:
10403 mips_set_option_string (&mips_arch_string
, "4100");
10404 mips_set_option_string (&mips_tune_string
, "4100");
10407 case OPTION_NO_M4100
:
10411 mips_set_option_string (&mips_arch_string
, "3900");
10412 mips_set_option_string (&mips_tune_string
, "3900");
10415 case OPTION_NO_M3900
:
10419 mips_opts
.ase_mdmx
= 1;
10422 case OPTION_NO_MDMX
:
10423 mips_opts
.ase_mdmx
= 0;
10426 case OPTION_MIPS16
:
10427 mips_opts
.mips16
= 1;
10428 mips_no_prev_insn (FALSE
);
10431 case OPTION_NO_MIPS16
:
10432 mips_opts
.mips16
= 0;
10433 mips_no_prev_insn (FALSE
);
10436 case OPTION_MIPS3D
:
10437 mips_opts
.ase_mips3d
= 1;
10440 case OPTION_NO_MIPS3D
:
10441 mips_opts
.ase_mips3d
= 0;
10444 case OPTION_FIX_VR4120
:
10445 mips_fix_vr4120
= 1;
10448 case OPTION_NO_FIX_VR4120
:
10449 mips_fix_vr4120
= 0;
10452 case OPTION_RELAX_BRANCH
:
10453 mips_relax_branch
= 1;
10456 case OPTION_NO_RELAX_BRANCH
:
10457 mips_relax_branch
= 0;
10460 case OPTION_MSHARED
:
10461 mips_in_shared
= TRUE
;
10464 case OPTION_MNO_SHARED
:
10465 mips_in_shared
= FALSE
;
10469 /* When generating ELF code, we permit -KPIC and -call_shared to
10470 select SVR4_PIC, and -non_shared to select no PIC. This is
10471 intended to be compatible with Irix 5. */
10472 case OPTION_CALL_SHARED
:
10473 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
10475 as_bad (_("-call_shared is supported only for ELF format"));
10478 mips_pic
= SVR4_PIC
;
10479 mips_abicalls
= TRUE
;
10480 if (g_switch_seen
&& g_switch_value
!= 0)
10482 as_bad (_("-G may not be used with SVR4 PIC code"));
10485 g_switch_value
= 0;
10488 case OPTION_NON_SHARED
:
10489 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
10491 as_bad (_("-non_shared is supported only for ELF format"));
10495 mips_abicalls
= FALSE
;
10498 /* The -xgot option tells the assembler to use 32 offsets when
10499 accessing the got in SVR4_PIC mode. It is for Irix
10504 #endif /* OBJ_ELF */
10507 g_switch_value
= atoi (arg
);
10509 if (mips_pic
== SVR4_PIC
&& g_switch_value
!= 0)
10511 as_bad (_("-G may not be used with SVR4 PIC code"));
10517 /* The -32, -n32 and -64 options are shortcuts for -mabi=32, -mabi=n32
10520 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
10522 as_bad (_("-32 is supported for ELF format only"));
10525 mips_abi
= O32_ABI
;
10529 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
10531 as_bad (_("-n32 is supported for ELF format only"));
10534 mips_abi
= N32_ABI
;
10538 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
10540 as_bad (_("-64 is supported for ELF format only"));
10543 mips_abi
= N64_ABI
;
10544 if (! support_64bit_objects())
10545 as_fatal (_("No compiled in support for 64 bit object file format"));
10547 #endif /* OBJ_ELF */
10550 file_mips_gp32
= 1;
10554 file_mips_gp32
= 0;
10558 file_mips_fp32
= 1;
10562 file_mips_fp32
= 0;
10567 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
10569 as_bad (_("-mabi is supported for ELF format only"));
10572 if (strcmp (arg
, "32") == 0)
10573 mips_abi
= O32_ABI
;
10574 else if (strcmp (arg
, "o64") == 0)
10575 mips_abi
= O64_ABI
;
10576 else if (strcmp (arg
, "n32") == 0)
10577 mips_abi
= N32_ABI
;
10578 else if (strcmp (arg
, "64") == 0)
10580 mips_abi
= N64_ABI
;
10581 if (! support_64bit_objects())
10582 as_fatal (_("No compiled in support for 64 bit object file "
10585 else if (strcmp (arg
, "eabi") == 0)
10586 mips_abi
= EABI_ABI
;
10589 as_fatal (_("invalid abi -mabi=%s"), arg
);
10593 #endif /* OBJ_ELF */
10595 case OPTION_M7000_HILO_FIX
:
10596 mips_7000_hilo_fix
= TRUE
;
10599 case OPTION_MNO_7000_HILO_FIX
:
10600 mips_7000_hilo_fix
= FALSE
;
10604 case OPTION_MDEBUG
:
10605 mips_flag_mdebug
= TRUE
;
10608 case OPTION_NO_MDEBUG
:
10609 mips_flag_mdebug
= FALSE
;
10613 mips_flag_pdr
= TRUE
;
10616 case OPTION_NO_PDR
:
10617 mips_flag_pdr
= FALSE
;
10619 #endif /* OBJ_ELF */
10628 /* Set up globals to generate code for the ISA or processor
10629 described by INFO. */
10632 mips_set_architecture (const struct mips_cpu_info
*info
)
10636 file_mips_arch
= info
->cpu
;
10637 mips_opts
.arch
= info
->cpu
;
10638 mips_opts
.isa
= info
->isa
;
10643 /* Likewise for tuning. */
10646 mips_set_tune (const struct mips_cpu_info
*info
)
10649 mips_tune
= info
->cpu
;
10654 mips_after_parse_args (void)
10656 const struct mips_cpu_info
*arch_info
= 0;
10657 const struct mips_cpu_info
*tune_info
= 0;
10659 /* GP relative stuff not working for PE */
10660 if (strncmp (TARGET_OS
, "pe", 2) == 0)
10662 if (g_switch_seen
&& g_switch_value
!= 0)
10663 as_bad (_("-G not supported in this configuration."));
10664 g_switch_value
= 0;
10667 if (mips_abi
== NO_ABI
)
10668 mips_abi
= MIPS_DEFAULT_ABI
;
10670 /* The following code determines the architecture and register size.
10671 Similar code was added to GCC 3.3 (see override_options() in
10672 config/mips/mips.c). The GAS and GCC code should be kept in sync
10673 as much as possible. */
10675 if (mips_arch_string
!= 0)
10676 arch_info
= mips_parse_cpu ("-march", mips_arch_string
);
10678 if (file_mips_isa
!= ISA_UNKNOWN
)
10680 /* Handle -mipsN. At this point, file_mips_isa contains the
10681 ISA level specified by -mipsN, while arch_info->isa contains
10682 the -march selection (if any). */
10683 if (arch_info
!= 0)
10685 /* -march takes precedence over -mipsN, since it is more descriptive.
10686 There's no harm in specifying both as long as the ISA levels
10688 if (file_mips_isa
!= arch_info
->isa
)
10689 as_bad (_("-%s conflicts with the other architecture options, which imply -%s"),
10690 mips_cpu_info_from_isa (file_mips_isa
)->name
,
10691 mips_cpu_info_from_isa (arch_info
->isa
)->name
);
10694 arch_info
= mips_cpu_info_from_isa (file_mips_isa
);
10697 if (arch_info
== 0)
10698 arch_info
= mips_parse_cpu ("default CPU", MIPS_CPU_STRING_DEFAULT
);
10700 if (ABI_NEEDS_64BIT_REGS (mips_abi
) && !ISA_HAS_64BIT_REGS (arch_info
->isa
))
10701 as_bad ("-march=%s is not compatible with the selected ABI",
10704 mips_set_architecture (arch_info
);
10706 /* Optimize for file_mips_arch, unless -mtune selects a different processor. */
10707 if (mips_tune_string
!= 0)
10708 tune_info
= mips_parse_cpu ("-mtune", mips_tune_string
);
10710 if (tune_info
== 0)
10711 mips_set_tune (arch_info
);
10713 mips_set_tune (tune_info
);
10715 if (file_mips_gp32
>= 0)
10717 /* The user specified the size of the integer registers. Make sure
10718 it agrees with the ABI and ISA. */
10719 if (file_mips_gp32
== 0 && !ISA_HAS_64BIT_REGS (mips_opts
.isa
))
10720 as_bad (_("-mgp64 used with a 32-bit processor"));
10721 else if (file_mips_gp32
== 1 && ABI_NEEDS_64BIT_REGS (mips_abi
))
10722 as_bad (_("-mgp32 used with a 64-bit ABI"));
10723 else if (file_mips_gp32
== 0 && ABI_NEEDS_32BIT_REGS (mips_abi
))
10724 as_bad (_("-mgp64 used with a 32-bit ABI"));
10728 /* Infer the integer register size from the ABI and processor.
10729 Restrict ourselves to 32-bit registers if that's all the
10730 processor has, or if the ABI cannot handle 64-bit registers. */
10731 file_mips_gp32
= (ABI_NEEDS_32BIT_REGS (mips_abi
)
10732 || !ISA_HAS_64BIT_REGS (mips_opts
.isa
));
10735 /* ??? GAS treats single-float processors as though they had 64-bit
10736 float registers (although it complains when double-precision
10737 instructions are used). As things stand, saying they have 32-bit
10738 registers would lead to spurious "register must be even" messages.
10739 So here we assume float registers are always the same size as
10740 integer ones, unless the user says otherwise. */
10741 if (file_mips_fp32
< 0)
10742 file_mips_fp32
= file_mips_gp32
;
10744 /* End of GCC-shared inference code. */
10746 /* This flag is set when we have a 64-bit capable CPU but use only
10747 32-bit wide registers. Note that EABI does not use it. */
10748 if (ISA_HAS_64BIT_REGS (mips_opts
.isa
)
10749 && ((mips_abi
== NO_ABI
&& file_mips_gp32
== 1)
10750 || mips_abi
== O32_ABI
))
10751 mips_32bitmode
= 1;
10753 if (mips_opts
.isa
== ISA_MIPS1
&& mips_trap
)
10754 as_bad (_("trap exception not supported at ISA 1"));
10756 /* If the selected architecture includes support for ASEs, enable
10757 generation of code for them. */
10758 if (mips_opts
.mips16
== -1)
10759 mips_opts
.mips16
= (CPU_HAS_MIPS16 (file_mips_arch
)) ? 1 : 0;
10760 if (mips_opts
.ase_mips3d
== -1)
10761 mips_opts
.ase_mips3d
= (CPU_HAS_MIPS3D (file_mips_arch
)) ? 1 : 0;
10762 if (mips_opts
.ase_mdmx
== -1)
10763 mips_opts
.ase_mdmx
= (CPU_HAS_MDMX (file_mips_arch
)) ? 1 : 0;
10765 file_mips_isa
= mips_opts
.isa
;
10766 file_ase_mips16
= mips_opts
.mips16
;
10767 file_ase_mips3d
= mips_opts
.ase_mips3d
;
10768 file_ase_mdmx
= mips_opts
.ase_mdmx
;
10769 mips_opts
.gp32
= file_mips_gp32
;
10770 mips_opts
.fp32
= file_mips_fp32
;
10772 if (mips_flag_mdebug
< 0)
10774 #ifdef OBJ_MAYBE_ECOFF
10775 if (OUTPUT_FLAVOR
== bfd_target_ecoff_flavour
)
10776 mips_flag_mdebug
= 1;
10778 #endif /* OBJ_MAYBE_ECOFF */
10779 mips_flag_mdebug
= 0;
10784 mips_init_after_args (void)
10786 /* initialize opcodes */
10787 bfd_mips_num_opcodes
= bfd_mips_num_builtin_opcodes
;
10788 mips_opcodes
= (struct mips_opcode
*) mips_builtin_opcodes
;
10792 md_pcrel_from (fixS
*fixP
)
10794 valueT addr
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
10795 switch (fixP
->fx_r_type
)
10797 case BFD_RELOC_16_PCREL_S2
:
10798 case BFD_RELOC_MIPS_JMP
:
10799 /* Return the address of the delay slot. */
10806 /* This is called before the symbol table is processed. In order to
10807 work with gcc when using mips-tfile, we must keep all local labels.
10808 However, in other cases, we want to discard them. If we were
10809 called with -g, but we didn't see any debugging information, it may
10810 mean that gcc is smuggling debugging information through to
10811 mips-tfile, in which case we must generate all local labels. */
10814 mips_frob_file_before_adjust (void)
10816 #ifndef NO_ECOFF_DEBUGGING
10817 if (ECOFF_DEBUGGING
10819 && ! ecoff_debugging_seen
)
10820 flag_keep_locals
= 1;
10824 /* Sort any unmatched HI16 and GOT16 relocs so that they immediately precede
10825 the corresponding LO16 reloc. This is called before md_apply_fix3 and
10826 tc_gen_reloc. Unmatched relocs can only be generated by use of explicit
10827 relocation operators.
10829 For our purposes, a %lo() expression matches a %got() or %hi()
10832 (a) it refers to the same symbol; and
10833 (b) the offset applied in the %lo() expression is no lower than
10834 the offset applied in the %got() or %hi().
10836 (b) allows us to cope with code like:
10839 lh $4,%lo(foo+2)($4)
10841 ...which is legal on RELA targets, and has a well-defined behaviour
10842 if the user knows that adding 2 to "foo" will not induce a carry to
10845 When several %lo()s match a particular %got() or %hi(), we use the
10846 following rules to distinguish them:
10848 (1) %lo()s with smaller offsets are a better match than %lo()s with
10851 (2) %lo()s with no matching %got() or %hi() are better than those
10852 that already have a matching %got() or %hi().
10854 (3) later %lo()s are better than earlier %lo()s.
10856 These rules are applied in order.
10858 (1) means, among other things, that %lo()s with identical offsets are
10859 chosen if they exist.
10861 (2) means that we won't associate several high-part relocations with
10862 the same low-part relocation unless there's no alternative. Having
10863 several high parts for the same low part is a GNU extension; this rule
10864 allows careful users to avoid it.
10866 (3) is purely cosmetic. mips_hi_fixup_list is is in reverse order,
10867 with the last high-part relocation being at the front of the list.
10868 It therefore makes sense to choose the last matching low-part
10869 relocation, all other things being equal. It's also easier
10870 to code that way. */
10873 mips_frob_file (void)
10875 struct mips_hi_fixup
*l
;
10877 for (l
= mips_hi_fixup_list
; l
!= NULL
; l
= l
->next
)
10879 segment_info_type
*seginfo
;
10880 bfd_boolean matched_lo_p
;
10881 fixS
**hi_pos
, **lo_pos
, **pos
;
10883 assert (reloc_needs_lo_p (l
->fixp
->fx_r_type
));
10885 /* If a GOT16 relocation turns out to be against a global symbol,
10886 there isn't supposed to be a matching LO. */
10887 if (l
->fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT16
10888 && !pic_need_relax (l
->fixp
->fx_addsy
, l
->seg
))
10891 /* Check quickly whether the next fixup happens to be a matching %lo. */
10892 if (fixup_has_matching_lo_p (l
->fixp
))
10895 seginfo
= seg_info (l
->seg
);
10897 /* Set HI_POS to the position of this relocation in the chain.
10898 Set LO_POS to the position of the chosen low-part relocation.
10899 MATCHED_LO_P is true on entry to the loop if *POS is a low-part
10900 relocation that matches an immediately-preceding high-part
10904 matched_lo_p
= FALSE
;
10905 for (pos
= &seginfo
->fix_root
; *pos
!= NULL
; pos
= &(*pos
)->fx_next
)
10907 if (*pos
== l
->fixp
)
10910 if ((*pos
)->fx_r_type
== BFD_RELOC_LO16
10911 && (*pos
)->fx_addsy
== l
->fixp
->fx_addsy
10912 && (*pos
)->fx_offset
>= l
->fixp
->fx_offset
10914 || (*pos
)->fx_offset
< (*lo_pos
)->fx_offset
10916 && (*pos
)->fx_offset
== (*lo_pos
)->fx_offset
)))
10919 matched_lo_p
= (reloc_needs_lo_p ((*pos
)->fx_r_type
)
10920 && fixup_has_matching_lo_p (*pos
));
10923 /* If we found a match, remove the high-part relocation from its
10924 current position and insert it before the low-part relocation.
10925 Make the offsets match so that fixup_has_matching_lo_p()
10928 We don't warn about unmatched high-part relocations since some
10929 versions of gcc have been known to emit dead "lui ...%hi(...)"
10931 if (lo_pos
!= NULL
)
10933 l
->fixp
->fx_offset
= (*lo_pos
)->fx_offset
;
10934 if (l
->fixp
->fx_next
!= *lo_pos
)
10936 *hi_pos
= l
->fixp
->fx_next
;
10937 l
->fixp
->fx_next
= *lo_pos
;
10944 /* We may have combined relocations without symbols in the N32/N64 ABI.
10945 We have to prevent gas from dropping them. */
10948 mips_force_relocation (fixS
*fixp
)
10950 if (generic_force_reloc (fixp
))
10954 && S_GET_SEGMENT (fixp
->fx_addsy
) == bfd_abs_section_ptr
10955 && (fixp
->fx_r_type
== BFD_RELOC_MIPS_SUB
10956 || fixp
->fx_r_type
== BFD_RELOC_HI16_S
10957 || fixp
->fx_r_type
== BFD_RELOC_LO16
))
10963 /* This hook is called before a fix is simplified. We don't really
10964 decide whether to skip a fix here. Rather, we turn global symbols
10965 used as branch targets into local symbols, such that they undergo
10966 simplification. We can only do this if the symbol is defined and
10967 it is in the same section as the branch. If this doesn't hold, we
10968 emit a better error message than just saying the relocation is not
10969 valid for the selected object format.
10971 FIXP is the fix-up we're going to try to simplify, SEG is the
10972 segment in which the fix up occurs. The return value should be
10973 non-zero to indicate the fix-up is valid for further
10974 simplifications. */
10977 mips_validate_fix (struct fix
*fixP
, asection
*seg
)
10979 /* There's a lot of discussion on whether it should be possible to
10980 use R_MIPS_PC16 to represent branch relocations. The outcome
10981 seems to be that it can, but gas/bfd are very broken in creating
10982 RELA relocations for this, so for now we only accept branches to
10983 symbols in the same section. Anything else is of dubious value,
10984 since there's no guarantee that at link time the symbol would be
10985 in range. Even for branches to local symbols this is arguably
10986 wrong, since it we assume the symbol is not going to be
10987 overridden, which should be possible per ELF library semantics,
10988 but then, there isn't a dynamic relocation that could be used to
10989 this effect, and the target would likely be out of range as well.
10991 Unfortunately, it seems that there is too much code out there
10992 that relies on branches to symbols that are global to be resolved
10993 as if they were local, like the IRIX tools do, so we do it as
10994 well, but with a warning so that people are reminded to fix their
10995 code. If we ever get back to using R_MIPS_PC16 for branch
10996 targets, this entire block should go away (and probably the
10997 whole function). */
10999 if (fixP
->fx_r_type
== BFD_RELOC_16_PCREL_S2
11000 && ((OUTPUT_FLAVOR
== bfd_target_ecoff_flavour
11001 || OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
11002 || bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_16_PCREL_S2
) == NULL
)
11005 if (! S_IS_DEFINED (fixP
->fx_addsy
))
11007 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
11008 _("Cannot branch to undefined symbol."));
11009 /* Avoid any further errors about this fixup. */
11012 else if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
11014 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
11015 _("Cannot branch to symbol in another section."));
11018 else if (S_IS_EXTERNAL (fixP
->fx_addsy
))
11020 symbolS
*sym
= fixP
->fx_addsy
;
11022 if (mips_pic
== SVR4_PIC
)
11023 as_warn_where (fixP
->fx_file
, fixP
->fx_line
,
11024 _("Pretending global symbol used as branch target is local."));
11026 fixP
->fx_addsy
= symbol_create (S_GET_NAME (sym
),
11027 S_GET_SEGMENT (sym
),
11029 symbol_get_frag (sym
));
11030 copy_symbol_attributes (fixP
->fx_addsy
, sym
);
11031 S_CLEAR_EXTERNAL (fixP
->fx_addsy
);
11032 assert (symbol_resolved_p (sym
));
11033 symbol_mark_resolved (fixP
->fx_addsy
);
11040 /* Apply a fixup to the object file. */
11043 md_apply_fix3 (fixS
*fixP
, valueT
*valP
, segT seg ATTRIBUTE_UNUSED
)
11047 reloc_howto_type
*howto
;
11049 /* We ignore generic BFD relocations we don't know about. */
11050 howto
= bfd_reloc_type_lookup (stdoutput
, fixP
->fx_r_type
);
11054 assert (fixP
->fx_size
== 4
11055 || fixP
->fx_r_type
== BFD_RELOC_16
11056 || fixP
->fx_r_type
== BFD_RELOC_64
11057 || fixP
->fx_r_type
== BFD_RELOC_CTOR
11058 || fixP
->fx_r_type
== BFD_RELOC_MIPS_SUB
11059 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
11060 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
);
11062 buf
= (bfd_byte
*) (fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
);
11064 assert (! fixP
->fx_pcrel
);
11066 /* Don't treat parts of a composite relocation as done. There are two
11069 (1) The second and third parts will be against 0 (RSS_UNDEF) but
11070 should nevertheless be emitted if the first part is.
11072 (2) In normal usage, composite relocations are never assembly-time
11073 constants. The easiest way of dealing with the pathological
11074 exceptions is to generate a relocation against STN_UNDEF and
11075 leave everything up to the linker. */
11076 if (fixP
->fx_addsy
== NULL
&& fixP
->fx_tcbit
== 0)
11079 switch (fixP
->fx_r_type
)
11081 case BFD_RELOC_MIPS_TLS_GD
:
11082 case BFD_RELOC_MIPS_TLS_LDM
:
11083 case BFD_RELOC_MIPS_TLS_DTPREL_HI16
:
11084 case BFD_RELOC_MIPS_TLS_DTPREL_LO16
:
11085 case BFD_RELOC_MIPS_TLS_GOTTPREL
:
11086 case BFD_RELOC_MIPS_TLS_TPREL_HI16
:
11087 case BFD_RELOC_MIPS_TLS_TPREL_LO16
:
11088 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
11091 case BFD_RELOC_MIPS_JMP
:
11092 case BFD_RELOC_MIPS_SHIFT5
:
11093 case BFD_RELOC_MIPS_SHIFT6
:
11094 case BFD_RELOC_MIPS_GOT_DISP
:
11095 case BFD_RELOC_MIPS_GOT_PAGE
:
11096 case BFD_RELOC_MIPS_GOT_OFST
:
11097 case BFD_RELOC_MIPS_SUB
:
11098 case BFD_RELOC_MIPS_INSERT_A
:
11099 case BFD_RELOC_MIPS_INSERT_B
:
11100 case BFD_RELOC_MIPS_DELETE
:
11101 case BFD_RELOC_MIPS_HIGHEST
:
11102 case BFD_RELOC_MIPS_HIGHER
:
11103 case BFD_RELOC_MIPS_SCN_DISP
:
11104 case BFD_RELOC_MIPS_REL16
:
11105 case BFD_RELOC_MIPS_RELGOT
:
11106 case BFD_RELOC_MIPS_JALR
:
11107 case BFD_RELOC_HI16
:
11108 case BFD_RELOC_HI16_S
:
11109 case BFD_RELOC_GPREL16
:
11110 case BFD_RELOC_MIPS_LITERAL
:
11111 case BFD_RELOC_MIPS_CALL16
:
11112 case BFD_RELOC_MIPS_GOT16
:
11113 case BFD_RELOC_GPREL32
:
11114 case BFD_RELOC_MIPS_GOT_HI16
:
11115 case BFD_RELOC_MIPS_GOT_LO16
:
11116 case BFD_RELOC_MIPS_CALL_HI16
:
11117 case BFD_RELOC_MIPS_CALL_LO16
:
11118 case BFD_RELOC_MIPS16_GPREL
:
11119 case BFD_RELOC_MIPS16_HI16
:
11120 case BFD_RELOC_MIPS16_HI16_S
:
11121 assert (! fixP
->fx_pcrel
);
11122 /* Nothing needed to do. The value comes from the reloc entry */
11125 case BFD_RELOC_MIPS16_JMP
:
11126 /* We currently always generate a reloc against a symbol, which
11127 means that we don't want an addend even if the symbol is
11133 /* This is handled like BFD_RELOC_32, but we output a sign
11134 extended value if we are only 32 bits. */
11137 if (8 <= sizeof (valueT
))
11138 md_number_to_chars ((char *) buf
, *valP
, 8);
11143 if ((*valP
& 0x80000000) != 0)
11147 md_number_to_chars ((char *)(buf
+ target_big_endian
? 4 : 0),
11149 md_number_to_chars ((char *)(buf
+ target_big_endian
? 0 : 4),
11155 case BFD_RELOC_RVA
:
11157 /* If we are deleting this reloc entry, we must fill in the
11158 value now. This can happen if we have a .word which is not
11159 resolved when it appears but is later defined. */
11161 md_number_to_chars ((char *) buf
, *valP
, 4);
11165 /* If we are deleting this reloc entry, we must fill in the
11168 md_number_to_chars ((char *) buf
, *valP
, 2);
11171 case BFD_RELOC_LO16
:
11172 case BFD_RELOC_MIPS16_LO16
:
11173 /* FIXME: Now that embedded-PIC is gone, some of this code/comment
11174 may be safe to remove, but if so it's not obvious. */
11175 /* When handling an embedded PIC switch statement, we can wind
11176 up deleting a LO16 reloc. See the 'o' case in mips_ip. */
11179 if (*valP
+ 0x8000 > 0xffff)
11180 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
11181 _("relocation overflow"));
11182 if (target_big_endian
)
11184 md_number_to_chars ((char *) buf
, *valP
, 2);
11188 case BFD_RELOC_16_PCREL_S2
:
11189 if ((*valP
& 0x3) != 0)
11190 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
11191 _("Branch to odd address (%lx)"), (long) *valP
);
11194 * We need to save the bits in the instruction since fixup_segment()
11195 * might be deleting the relocation entry (i.e., a branch within
11196 * the current segment).
11198 if (! fixP
->fx_done
)
11201 /* update old instruction data */
11202 if (target_big_endian
)
11203 insn
= (buf
[0] << 24) | (buf
[1] << 16) | (buf
[2] << 8) | buf
[3];
11205 insn
= (buf
[3] << 24) | (buf
[2] << 16) | (buf
[1] << 8) | buf
[0];
11207 if (*valP
+ 0x20000 <= 0x3ffff)
11209 insn
|= (*valP
>> 2) & 0xffff;
11210 md_number_to_chars ((char *) buf
, insn
, 4);
11212 else if (mips_pic
== NO_PIC
11214 && fixP
->fx_frag
->fr_address
>= text_section
->vma
11215 && (fixP
->fx_frag
->fr_address
11216 < text_section
->vma
+ bfd_get_section_size (text_section
))
11217 && ((insn
& 0xffff0000) == 0x10000000 /* beq $0,$0 */
11218 || (insn
& 0xffff0000) == 0x04010000 /* bgez $0 */
11219 || (insn
& 0xffff0000) == 0x04110000)) /* bgezal $0 */
11221 /* The branch offset is too large. If this is an
11222 unconditional branch, and we are not generating PIC code,
11223 we can convert it to an absolute jump instruction. */
11224 if ((insn
& 0xffff0000) == 0x04110000) /* bgezal $0 */
11225 insn
= 0x0c000000; /* jal */
11227 insn
= 0x08000000; /* j */
11228 fixP
->fx_r_type
= BFD_RELOC_MIPS_JMP
;
11230 fixP
->fx_addsy
= section_symbol (text_section
);
11231 *valP
+= md_pcrel_from (fixP
);
11232 md_number_to_chars ((char *) buf
, insn
, 4);
11236 /* If we got here, we have branch-relaxation disabled,
11237 and there's nothing we can do to fix this instruction
11238 without turning it into a longer sequence. */
11239 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
11240 _("Branch out of range"));
11244 case BFD_RELOC_VTABLE_INHERIT
:
11247 && !S_IS_DEFINED (fixP
->fx_addsy
)
11248 && !S_IS_WEAK (fixP
->fx_addsy
))
11249 S_SET_WEAK (fixP
->fx_addsy
);
11252 case BFD_RELOC_VTABLE_ENTRY
:
11260 /* Remember value for tc_gen_reloc. */
11261 fixP
->fx_addnumber
= *valP
;
11271 name
= input_line_pointer
;
11272 c
= get_symbol_end ();
11273 p
= (symbolS
*) symbol_find_or_make (name
);
11274 *input_line_pointer
= c
;
11278 /* Align the current frag to a given power of two. The MIPS assembler
11279 also automatically adjusts any preceding label. */
11282 mips_align (int to
, int fill
, symbolS
*label
)
11284 mips_emit_delays (FALSE
);
11285 frag_align (to
, fill
, 0);
11286 record_alignment (now_seg
, to
);
11289 assert (S_GET_SEGMENT (label
) == now_seg
);
11290 symbol_set_frag (label
, frag_now
);
11291 S_SET_VALUE (label
, (valueT
) frag_now_fix ());
11295 /* Align to a given power of two. .align 0 turns off the automatic
11296 alignment used by the data creating pseudo-ops. */
11299 s_align (int x ATTRIBUTE_UNUSED
)
11302 register long temp_fill
;
11303 long max_alignment
= 15;
11307 o Note that the assembler pulls down any immediately preceding label
11308 to the aligned address.
11309 o It's not documented but auto alignment is reinstated by
11310 a .align pseudo instruction.
11311 o Note also that after auto alignment is turned off the mips assembler
11312 issues an error on attempt to assemble an improperly aligned data item.
11317 temp
= get_absolute_expression ();
11318 if (temp
> max_alignment
)
11319 as_bad (_("Alignment too large: %d. assumed."), temp
= max_alignment
);
11322 as_warn (_("Alignment negative: 0 assumed."));
11325 if (*input_line_pointer
== ',')
11327 ++input_line_pointer
;
11328 temp_fill
= get_absolute_expression ();
11335 mips_align (temp
, (int) temp_fill
,
11336 insn_labels
!= NULL
? insn_labels
->label
: NULL
);
11343 demand_empty_rest_of_line ();
11347 mips_flush_pending_output (void)
11349 mips_emit_delays (FALSE
);
11350 mips_clear_insn_labels ();
11354 s_change_sec (int sec
)
11359 /* The ELF backend needs to know that we are changing sections, so
11360 that .previous works correctly. We could do something like check
11361 for an obj_section_change_hook macro, but that might be confusing
11362 as it would not be appropriate to use it in the section changing
11363 functions in read.c, since obj-elf.c intercepts those. FIXME:
11364 This should be cleaner, somehow. */
11365 obj_elf_section_change_hook ();
11368 mips_emit_delays (FALSE
);
11378 subseg_set (bss_section
, (subsegT
) get_absolute_expression ());
11379 demand_empty_rest_of_line ();
11383 seg
= subseg_new (RDATA_SECTION_NAME
,
11384 (subsegT
) get_absolute_expression ());
11385 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
11387 bfd_set_section_flags (stdoutput
, seg
, (SEC_ALLOC
| SEC_LOAD
11388 | SEC_READONLY
| SEC_RELOC
11390 if (strcmp (TARGET_OS
, "elf") != 0)
11391 record_alignment (seg
, 4);
11393 demand_empty_rest_of_line ();
11397 seg
= subseg_new (".sdata", (subsegT
) get_absolute_expression ());
11398 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
11400 bfd_set_section_flags (stdoutput
, seg
,
11401 SEC_ALLOC
| SEC_LOAD
| SEC_RELOC
| SEC_DATA
);
11402 if (strcmp (TARGET_OS
, "elf") != 0)
11403 record_alignment (seg
, 4);
11405 demand_empty_rest_of_line ();
11413 s_change_section (int ignore ATTRIBUTE_UNUSED
)
11416 char *section_name
;
11421 int section_entry_size
;
11422 int section_alignment
;
11424 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
11427 section_name
= input_line_pointer
;
11428 c
= get_symbol_end ();
11430 next_c
= *(input_line_pointer
+ 1);
11432 /* Do we have .section Name<,"flags">? */
11433 if (c
!= ',' || (c
== ',' && next_c
== '"'))
11435 /* just after name is now '\0'. */
11436 *input_line_pointer
= c
;
11437 input_line_pointer
= section_name
;
11438 obj_elf_section (ignore
);
11441 input_line_pointer
++;
11443 /* Do we have .section Name<,type><,flag><,entry_size><,alignment> */
11445 section_type
= get_absolute_expression ();
11448 if (*input_line_pointer
++ == ',')
11449 section_flag
= get_absolute_expression ();
11452 if (*input_line_pointer
++ == ',')
11453 section_entry_size
= get_absolute_expression ();
11455 section_entry_size
= 0;
11456 if (*input_line_pointer
++ == ',')
11457 section_alignment
= get_absolute_expression ();
11459 section_alignment
= 0;
11461 section_name
= xstrdup (section_name
);
11463 /* When using the generic form of .section (as implemented by obj-elf.c),
11464 there's no way to set the section type to SHT_MIPS_DWARF. Users have
11465 traditionally had to fall back on the more common @progbits instead.
11467 There's nothing really harmful in this, since bfd will correct
11468 SHT_PROGBITS to SHT_MIPS_DWARF before writing out the file. But it
11469 means that, for backwards compatibiltiy, the special_section entries
11470 for dwarf sections must use SHT_PROGBITS rather than SHT_MIPS_DWARF.
11472 Even so, we shouldn't force users of the MIPS .section syntax to
11473 incorrectly label the sections as SHT_PROGBITS. The best compromise
11474 seems to be to map SHT_MIPS_DWARF to SHT_PROGBITS before calling the
11475 generic type-checking code. */
11476 if (section_type
== SHT_MIPS_DWARF
)
11477 section_type
= SHT_PROGBITS
;
11479 obj_elf_change_section (section_name
, section_type
, section_flag
,
11480 section_entry_size
, 0, 0, 0);
11482 if (now_seg
->name
!= section_name
)
11483 free (section_name
);
11484 #endif /* OBJ_ELF */
11488 mips_enable_auto_align (void)
11494 s_cons (int log_size
)
11498 label
= insn_labels
!= NULL
? insn_labels
->label
: NULL
;
11499 mips_emit_delays (FALSE
);
11500 if (log_size
> 0 && auto_align
)
11501 mips_align (log_size
, 0, label
);
11502 mips_clear_insn_labels ();
11503 cons (1 << log_size
);
11507 s_float_cons (int type
)
11511 label
= insn_labels
!= NULL
? insn_labels
->label
: NULL
;
11513 mips_emit_delays (FALSE
);
11518 mips_align (3, 0, label
);
11520 mips_align (2, 0, label
);
11523 mips_clear_insn_labels ();
11528 /* Handle .globl. We need to override it because on Irix 5 you are
11531 where foo is an undefined symbol, to mean that foo should be
11532 considered to be the address of a function. */
11535 s_mips_globl (int x ATTRIBUTE_UNUSED
)
11542 name
= input_line_pointer
;
11543 c
= get_symbol_end ();
11544 symbolP
= symbol_find_or_make (name
);
11545 *input_line_pointer
= c
;
11546 SKIP_WHITESPACE ();
11548 /* On Irix 5, every global symbol that is not explicitly labelled as
11549 being a function is apparently labelled as being an object. */
11552 if (! is_end_of_line
[(unsigned char) *input_line_pointer
])
11557 secname
= input_line_pointer
;
11558 c
= get_symbol_end ();
11559 sec
= bfd_get_section_by_name (stdoutput
, secname
);
11561 as_bad (_("%s: no such section"), secname
);
11562 *input_line_pointer
= c
;
11564 if (sec
!= NULL
&& (sec
->flags
& SEC_CODE
) != 0)
11565 flag
= BSF_FUNCTION
;
11568 symbol_get_bfdsym (symbolP
)->flags
|= flag
;
11570 S_SET_EXTERNAL (symbolP
);
11571 demand_empty_rest_of_line ();
11575 s_option (int x ATTRIBUTE_UNUSED
)
11580 opt
= input_line_pointer
;
11581 c
= get_symbol_end ();
11585 /* FIXME: What does this mean? */
11587 else if (strncmp (opt
, "pic", 3) == 0)
11591 i
= atoi (opt
+ 3);
11596 mips_pic
= SVR4_PIC
;
11597 mips_abicalls
= TRUE
;
11600 as_bad (_(".option pic%d not supported"), i
);
11602 if (mips_pic
== SVR4_PIC
)
11604 if (g_switch_seen
&& g_switch_value
!= 0)
11605 as_warn (_("-G may not be used with SVR4 PIC code"));
11606 g_switch_value
= 0;
11607 bfd_set_gp_size (stdoutput
, 0);
11611 as_warn (_("Unrecognized option \"%s\""), opt
);
11613 *input_line_pointer
= c
;
11614 demand_empty_rest_of_line ();
11617 /* This structure is used to hold a stack of .set values. */
11619 struct mips_option_stack
11621 struct mips_option_stack
*next
;
11622 struct mips_set_options options
;
11625 static struct mips_option_stack
*mips_opts_stack
;
11627 /* Handle the .set pseudo-op. */
11630 s_mipsset (int x ATTRIBUTE_UNUSED
)
11632 char *name
= input_line_pointer
, ch
;
11634 while (!is_end_of_line
[(unsigned char) *input_line_pointer
])
11635 ++input_line_pointer
;
11636 ch
= *input_line_pointer
;
11637 *input_line_pointer
= '\0';
11639 if (strcmp (name
, "reorder") == 0)
11641 if (mips_opts
.noreorder
&& prev_nop_frag
!= NULL
)
11643 /* If we still have pending nops, we can discard them. The
11644 usual nop handling will insert any that are still
11646 prev_nop_frag
->fr_fix
-= (prev_nop_frag_holds
11647 * (mips_opts
.mips16
? 2 : 4));
11648 prev_nop_frag
= NULL
;
11650 mips_opts
.noreorder
= 0;
11652 else if (strcmp (name
, "noreorder") == 0)
11654 mips_emit_delays (TRUE
);
11655 mips_opts
.noreorder
= 1;
11656 mips_any_noreorder
= 1;
11658 else if (strcmp (name
, "at") == 0)
11660 mips_opts
.noat
= 0;
11662 else if (strcmp (name
, "noat") == 0)
11664 mips_opts
.noat
= 1;
11666 else if (strcmp (name
, "macro") == 0)
11668 mips_opts
.warn_about_macros
= 0;
11670 else if (strcmp (name
, "nomacro") == 0)
11672 if (mips_opts
.noreorder
== 0)
11673 as_bad (_("`noreorder' must be set before `nomacro'"));
11674 mips_opts
.warn_about_macros
= 1;
11676 else if (strcmp (name
, "move") == 0 || strcmp (name
, "novolatile") == 0)
11678 mips_opts
.nomove
= 0;
11680 else if (strcmp (name
, "nomove") == 0 || strcmp (name
, "volatile") == 0)
11682 mips_opts
.nomove
= 1;
11684 else if (strcmp (name
, "bopt") == 0)
11686 mips_opts
.nobopt
= 0;
11688 else if (strcmp (name
, "nobopt") == 0)
11690 mips_opts
.nobopt
= 1;
11692 else if (strcmp (name
, "mips16") == 0
11693 || strcmp (name
, "MIPS-16") == 0)
11694 mips_opts
.mips16
= 1;
11695 else if (strcmp (name
, "nomips16") == 0
11696 || strcmp (name
, "noMIPS-16") == 0)
11697 mips_opts
.mips16
= 0;
11698 else if (strcmp (name
, "mips3d") == 0)
11699 mips_opts
.ase_mips3d
= 1;
11700 else if (strcmp (name
, "nomips3d") == 0)
11701 mips_opts
.ase_mips3d
= 0;
11702 else if (strcmp (name
, "mdmx") == 0)
11703 mips_opts
.ase_mdmx
= 1;
11704 else if (strcmp (name
, "nomdmx") == 0)
11705 mips_opts
.ase_mdmx
= 0;
11706 else if (strncmp (name
, "mips", 4) == 0 || strncmp (name
, "arch=", 5) == 0)
11710 /* Permit the user to change the ISA and architecture on the fly.
11711 Needless to say, misuse can cause serious problems. */
11712 if (strcmp (name
, "mips0") == 0 || strcmp (name
, "arch=default") == 0)
11715 mips_opts
.isa
= file_mips_isa
;
11716 mips_opts
.arch
= file_mips_arch
;
11718 else if (strncmp (name
, "arch=", 5) == 0)
11720 const struct mips_cpu_info
*p
;
11722 p
= mips_parse_cpu("internal use", name
+ 5);
11724 as_bad (_("unknown architecture %s"), name
+ 5);
11727 mips_opts
.arch
= p
->cpu
;
11728 mips_opts
.isa
= p
->isa
;
11731 else if (strncmp (name
, "mips", 4) == 0)
11733 const struct mips_cpu_info
*p
;
11735 p
= mips_parse_cpu("internal use", name
);
11737 as_bad (_("unknown ISA level %s"), name
+ 4);
11740 mips_opts
.arch
= p
->cpu
;
11741 mips_opts
.isa
= p
->isa
;
11745 as_bad (_("unknown ISA or architecture %s"), name
);
11747 switch (mips_opts
.isa
)
11755 mips_opts
.gp32
= 1;
11756 mips_opts
.fp32
= 1;
11763 mips_opts
.gp32
= 0;
11764 mips_opts
.fp32
= 0;
11767 as_bad (_("unknown ISA level %s"), name
+ 4);
11772 mips_opts
.gp32
= file_mips_gp32
;
11773 mips_opts
.fp32
= file_mips_fp32
;
11776 else if (strcmp (name
, "autoextend") == 0)
11777 mips_opts
.noautoextend
= 0;
11778 else if (strcmp (name
, "noautoextend") == 0)
11779 mips_opts
.noautoextend
= 1;
11780 else if (strcmp (name
, "push") == 0)
11782 struct mips_option_stack
*s
;
11784 s
= (struct mips_option_stack
*) xmalloc (sizeof *s
);
11785 s
->next
= mips_opts_stack
;
11786 s
->options
= mips_opts
;
11787 mips_opts_stack
= s
;
11789 else if (strcmp (name
, "pop") == 0)
11791 struct mips_option_stack
*s
;
11793 s
= mips_opts_stack
;
11795 as_bad (_(".set pop with no .set push"));
11798 /* If we're changing the reorder mode we need to handle
11799 delay slots correctly. */
11800 if (s
->options
.noreorder
&& ! mips_opts
.noreorder
)
11801 mips_emit_delays (TRUE
);
11802 else if (! s
->options
.noreorder
&& mips_opts
.noreorder
)
11804 if (prev_nop_frag
!= NULL
)
11806 prev_nop_frag
->fr_fix
-= (prev_nop_frag_holds
11807 * (mips_opts
.mips16
? 2 : 4));
11808 prev_nop_frag
= NULL
;
11812 mips_opts
= s
->options
;
11813 mips_opts_stack
= s
->next
;
11819 as_warn (_("Tried to set unrecognized symbol: %s\n"), name
);
11821 *input_line_pointer
= ch
;
11822 demand_empty_rest_of_line ();
11825 /* Handle the .abicalls pseudo-op. I believe this is equivalent to
11826 .option pic2. It means to generate SVR4 PIC calls. */
11829 s_abicalls (int ignore ATTRIBUTE_UNUSED
)
11831 mips_pic
= SVR4_PIC
;
11832 mips_abicalls
= TRUE
;
11834 if (g_switch_seen
&& g_switch_value
!= 0)
11835 as_warn (_("-G may not be used with SVR4 PIC code"));
11836 g_switch_value
= 0;
11838 bfd_set_gp_size (stdoutput
, 0);
11839 demand_empty_rest_of_line ();
11842 /* Handle the .cpload pseudo-op. This is used when generating SVR4
11843 PIC code. It sets the $gp register for the function based on the
11844 function address, which is in the register named in the argument.
11845 This uses a relocation against _gp_disp, which is handled specially
11846 by the linker. The result is:
11847 lui $gp,%hi(_gp_disp)
11848 addiu $gp,$gp,%lo(_gp_disp)
11849 addu $gp,$gp,.cpload argument
11850 The .cpload argument is normally $25 == $t9.
11852 The -mno-shared option changes this to:
11854 addiu $gp,$gp,%lo(_gp)
11855 and the argument is ignored. This saves an instruction, but the
11856 resulting code is not position independent; it uses an absolute
11857 address for _gp. Thus code assembled with -mno-shared can go into
11858 an ordinary executable, but not into a shared library. */
11861 s_cpload (int ignore ATTRIBUTE_UNUSED
)
11867 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
11868 .cpload is ignored. */
11869 if (mips_pic
!= SVR4_PIC
|| HAVE_NEWABI
)
11875 /* .cpload should be in a .set noreorder section. */
11876 if (mips_opts
.noreorder
== 0)
11877 as_warn (_(".cpload not in noreorder section"));
11879 reg
= tc_get_register (0);
11881 /* If we need to produce a 64-bit address, we are better off using
11882 the default instruction sequence. */
11883 in_shared
= mips_in_shared
|| HAVE_64BIT_ADDRESSES
;
11885 ex
.X_op
= O_symbol
;
11886 ex
.X_add_symbol
= symbol_find_or_make (in_shared
? "_gp_disp" : "_gp");
11887 ex
.X_op_symbol
= NULL
;
11888 ex
.X_add_number
= 0;
11890 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
11891 symbol_get_bfdsym (ex
.X_add_symbol
)->flags
|= BSF_OBJECT
;
11894 macro_build_lui (&ex
, mips_gp_register
);
11895 macro_build (&ex
, "addiu", "t,r,j", mips_gp_register
,
11896 mips_gp_register
, BFD_RELOC_LO16
);
11898 macro_build (NULL
, "addu", "d,v,t", mips_gp_register
,
11899 mips_gp_register
, reg
);
11902 demand_empty_rest_of_line ();
11905 /* Handle the .cpsetup pseudo-op defined for NewABI PIC code. The syntax is:
11906 .cpsetup $reg1, offset|$reg2, label
11908 If offset is given, this results in:
11909 sd $gp, offset($sp)
11910 lui $gp, %hi(%neg(%gp_rel(label)))
11911 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
11912 daddu $gp, $gp, $reg1
11914 If $reg2 is given, this results in:
11915 daddu $reg2, $gp, $0
11916 lui $gp, %hi(%neg(%gp_rel(label)))
11917 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
11918 daddu $gp, $gp, $reg1
11919 $reg1 is normally $25 == $t9.
11921 The -mno-shared option replaces the last three instructions with
11923 addiu $gp,$gp,%lo(_gp)
11927 s_cpsetup (int ignore ATTRIBUTE_UNUSED
)
11929 expressionS ex_off
;
11930 expressionS ex_sym
;
11933 /* If we are not generating SVR4 PIC code, .cpsetup is ignored.
11934 We also need NewABI support. */
11935 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
11941 reg1
= tc_get_register (0);
11942 SKIP_WHITESPACE ();
11943 if (*input_line_pointer
!= ',')
11945 as_bad (_("missing argument separator ',' for .cpsetup"));
11949 ++input_line_pointer
;
11950 SKIP_WHITESPACE ();
11951 if (*input_line_pointer
== '$')
11953 mips_cpreturn_register
= tc_get_register (0);
11954 mips_cpreturn_offset
= -1;
11958 mips_cpreturn_offset
= get_absolute_expression ();
11959 mips_cpreturn_register
= -1;
11961 SKIP_WHITESPACE ();
11962 if (*input_line_pointer
!= ',')
11964 as_bad (_("missing argument separator ',' for .cpsetup"));
11968 ++input_line_pointer
;
11969 SKIP_WHITESPACE ();
11970 expression (&ex_sym
);
11973 if (mips_cpreturn_register
== -1)
11975 ex_off
.X_op
= O_constant
;
11976 ex_off
.X_add_symbol
= NULL
;
11977 ex_off
.X_op_symbol
= NULL
;
11978 ex_off
.X_add_number
= mips_cpreturn_offset
;
11980 macro_build (&ex_off
, "sd", "t,o(b)", mips_gp_register
,
11981 BFD_RELOC_LO16
, SP
);
11984 macro_build (NULL
, "daddu", "d,v,t", mips_cpreturn_register
,
11985 mips_gp_register
, 0);
11987 if (mips_in_shared
|| HAVE_64BIT_ADDRESSES
)
11989 macro_build (&ex_sym
, "lui", "t,u", mips_gp_register
,
11990 -1, BFD_RELOC_GPREL16
, BFD_RELOC_MIPS_SUB
,
11993 macro_build (&ex_sym
, "addiu", "t,r,j", mips_gp_register
,
11994 mips_gp_register
, -1, BFD_RELOC_GPREL16
,
11995 BFD_RELOC_MIPS_SUB
, BFD_RELOC_LO16
);
11997 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", mips_gp_register
,
11998 mips_gp_register
, reg1
);
12004 ex
.X_op
= O_symbol
;
12005 ex
.X_add_symbol
= symbol_find_or_make ("_gp");
12006 ex
.X_op_symbol
= NULL
;
12007 ex
.X_add_number
= 0;
12009 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
12010 symbol_get_bfdsym (ex
.X_add_symbol
)->flags
|= BSF_OBJECT
;
12012 macro_build_lui (&ex
, mips_gp_register
);
12013 macro_build (&ex
, "addiu", "t,r,j", mips_gp_register
,
12014 mips_gp_register
, BFD_RELOC_LO16
);
12019 demand_empty_rest_of_line ();
12023 s_cplocal (int ignore ATTRIBUTE_UNUSED
)
12025 /* If we are not generating SVR4 PIC code, or if this is not NewABI code,
12026 .cplocal is ignored. */
12027 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
12033 mips_gp_register
= tc_get_register (0);
12034 demand_empty_rest_of_line ();
12037 /* Handle the .cprestore pseudo-op. This stores $gp into a given
12038 offset from $sp. The offset is remembered, and after making a PIC
12039 call $gp is restored from that location. */
12042 s_cprestore (int ignore ATTRIBUTE_UNUSED
)
12046 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
12047 .cprestore is ignored. */
12048 if (mips_pic
!= SVR4_PIC
|| HAVE_NEWABI
)
12054 mips_cprestore_offset
= get_absolute_expression ();
12055 mips_cprestore_valid
= 1;
12057 ex
.X_op
= O_constant
;
12058 ex
.X_add_symbol
= NULL
;
12059 ex
.X_op_symbol
= NULL
;
12060 ex
.X_add_number
= mips_cprestore_offset
;
12063 macro_build_ldst_constoffset (&ex
, ADDRESS_STORE_INSN
, mips_gp_register
,
12064 SP
, HAVE_64BIT_ADDRESSES
);
12067 demand_empty_rest_of_line ();
12070 /* Handle the .cpreturn pseudo-op defined for NewABI PIC code. If an offset
12071 was given in the preceding .cpsetup, it results in:
12072 ld $gp, offset($sp)
12074 If a register $reg2 was given there, it results in:
12075 daddu $gp, $reg2, $0
12078 s_cpreturn (int ignore ATTRIBUTE_UNUSED
)
12082 /* If we are not generating SVR4 PIC code, .cpreturn is ignored.
12083 We also need NewABI support. */
12084 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
12091 if (mips_cpreturn_register
== -1)
12093 ex
.X_op
= O_constant
;
12094 ex
.X_add_symbol
= NULL
;
12095 ex
.X_op_symbol
= NULL
;
12096 ex
.X_add_number
= mips_cpreturn_offset
;
12098 macro_build (&ex
, "ld", "t,o(b)", mips_gp_register
, BFD_RELOC_LO16
, SP
);
12101 macro_build (NULL
, "daddu", "d,v,t", mips_gp_register
,
12102 mips_cpreturn_register
, 0);
12105 demand_empty_rest_of_line ();
12108 /* Handle the .gpvalue pseudo-op. This is used when generating NewABI PIC
12109 code. It sets the offset to use in gp_rel relocations. */
12112 s_gpvalue (int ignore ATTRIBUTE_UNUSED
)
12114 /* If we are not generating SVR4 PIC code, .gpvalue is ignored.
12115 We also need NewABI support. */
12116 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
12122 mips_gprel_offset
= get_absolute_expression ();
12124 demand_empty_rest_of_line ();
12127 /* Handle the .gpword pseudo-op. This is used when generating PIC
12128 code. It generates a 32 bit GP relative reloc. */
12131 s_gpword (int ignore ATTRIBUTE_UNUSED
)
12137 /* When not generating PIC code, this is treated as .word. */
12138 if (mips_pic
!= SVR4_PIC
)
12144 label
= insn_labels
!= NULL
? insn_labels
->label
: NULL
;
12145 mips_emit_delays (TRUE
);
12147 mips_align (2, 0, label
);
12148 mips_clear_insn_labels ();
12152 if (ex
.X_op
!= O_symbol
|| ex
.X_add_number
!= 0)
12154 as_bad (_("Unsupported use of .gpword"));
12155 ignore_rest_of_line ();
12159 md_number_to_chars (p
, 0, 4);
12160 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 4, &ex
, FALSE
,
12161 BFD_RELOC_GPREL32
);
12163 demand_empty_rest_of_line ();
12167 s_gpdword (int ignore ATTRIBUTE_UNUSED
)
12173 /* When not generating PIC code, this is treated as .dword. */
12174 if (mips_pic
!= SVR4_PIC
)
12180 label
= insn_labels
!= NULL
? insn_labels
->label
: NULL
;
12181 mips_emit_delays (TRUE
);
12183 mips_align (3, 0, label
);
12184 mips_clear_insn_labels ();
12188 if (ex
.X_op
!= O_symbol
|| ex
.X_add_number
!= 0)
12190 as_bad (_("Unsupported use of .gpdword"));
12191 ignore_rest_of_line ();
12195 md_number_to_chars (p
, 0, 8);
12196 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 4, &ex
, FALSE
,
12197 BFD_RELOC_GPREL32
)->fx_tcbit
= 1;
12199 /* GPREL32 composed with 64 gives a 64-bit GP offset. */
12200 fix_new (frag_now
, p
- frag_now
->fr_literal
, 8, NULL
, 0,
12201 FALSE
, BFD_RELOC_64
)->fx_tcbit
= 1;
12203 demand_empty_rest_of_line ();
12206 /* Handle the .cpadd pseudo-op. This is used when dealing with switch
12207 tables in SVR4 PIC code. */
12210 s_cpadd (int ignore ATTRIBUTE_UNUSED
)
12214 /* This is ignored when not generating SVR4 PIC code. */
12215 if (mips_pic
!= SVR4_PIC
)
12221 /* Add $gp to the register named as an argument. */
12223 reg
= tc_get_register (0);
12224 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", reg
, reg
, mips_gp_register
);
12227 demand_empty_rest_of_line ();
12230 /* Handle the .insn pseudo-op. This marks instruction labels in
12231 mips16 mode. This permits the linker to handle them specially,
12232 such as generating jalx instructions when needed. We also make
12233 them odd for the duration of the assembly, in order to generate the
12234 right sort of code. We will make them even in the adjust_symtab
12235 routine, while leaving them marked. This is convenient for the
12236 debugger and the disassembler. The linker knows to make them odd
12240 s_insn (int ignore ATTRIBUTE_UNUSED
)
12242 mips16_mark_labels ();
12244 demand_empty_rest_of_line ();
12247 /* Handle a .stabn directive. We need these in order to mark a label
12248 as being a mips16 text label correctly. Sometimes the compiler
12249 will emit a label, followed by a .stabn, and then switch sections.
12250 If the label and .stabn are in mips16 mode, then the label is
12251 really a mips16 text label. */
12254 s_mips_stab (int type
)
12257 mips16_mark_labels ();
12262 /* Handle the .weakext pseudo-op as defined in Kane and Heinrich.
12266 s_mips_weakext (int ignore ATTRIBUTE_UNUSED
)
12273 name
= input_line_pointer
;
12274 c
= get_symbol_end ();
12275 symbolP
= symbol_find_or_make (name
);
12276 S_SET_WEAK (symbolP
);
12277 *input_line_pointer
= c
;
12279 SKIP_WHITESPACE ();
12281 if (! is_end_of_line
[(unsigned char) *input_line_pointer
])
12283 if (S_IS_DEFINED (symbolP
))
12285 as_bad ("ignoring attempt to redefine symbol %s",
12286 S_GET_NAME (symbolP
));
12287 ignore_rest_of_line ();
12291 if (*input_line_pointer
== ',')
12293 ++input_line_pointer
;
12294 SKIP_WHITESPACE ();
12298 if (exp
.X_op
!= O_symbol
)
12300 as_bad ("bad .weakext directive");
12301 ignore_rest_of_line ();
12304 symbol_set_value_expression (symbolP
, &exp
);
12307 demand_empty_rest_of_line ();
12310 /* Parse a register string into a number. Called from the ECOFF code
12311 to parse .frame. The argument is non-zero if this is the frame
12312 register, so that we can record it in mips_frame_reg. */
12315 tc_get_register (int frame
)
12319 SKIP_WHITESPACE ();
12320 if (*input_line_pointer
++ != '$')
12322 as_warn (_("expected `$'"));
12325 else if (ISDIGIT (*input_line_pointer
))
12327 reg
= get_absolute_expression ();
12328 if (reg
< 0 || reg
>= 32)
12330 as_warn (_("Bad register number"));
12336 if (strncmp (input_line_pointer
, "ra", 2) == 0)
12339 input_line_pointer
+= 2;
12341 else if (strncmp (input_line_pointer
, "fp", 2) == 0)
12344 input_line_pointer
+= 2;
12346 else if (strncmp (input_line_pointer
, "sp", 2) == 0)
12349 input_line_pointer
+= 2;
12351 else if (strncmp (input_line_pointer
, "gp", 2) == 0)
12354 input_line_pointer
+= 2;
12356 else if (strncmp (input_line_pointer
, "at", 2) == 0)
12359 input_line_pointer
+= 2;
12361 else if (strncmp (input_line_pointer
, "kt0", 3) == 0)
12364 input_line_pointer
+= 3;
12366 else if (strncmp (input_line_pointer
, "kt1", 3) == 0)
12369 input_line_pointer
+= 3;
12371 else if (strncmp (input_line_pointer
, "zero", 4) == 0)
12374 input_line_pointer
+= 4;
12378 as_warn (_("Unrecognized register name"));
12380 while (ISALNUM(*input_line_pointer
))
12381 input_line_pointer
++;
12386 mips_frame_reg
= reg
!= 0 ? reg
: SP
;
12387 mips_frame_reg_valid
= 1;
12388 mips_cprestore_valid
= 0;
12394 md_section_align (asection
*seg
, valueT addr
)
12396 int align
= bfd_get_section_alignment (stdoutput
, seg
);
12399 /* We don't need to align ELF sections to the full alignment.
12400 However, Irix 5 may prefer that we align them at least to a 16
12401 byte boundary. We don't bother to align the sections if we are
12402 targeted for an embedded system. */
12403 if (strcmp (TARGET_OS
, "elf") == 0)
12409 return ((addr
+ (1 << align
) - 1) & (-1 << align
));
12412 /* Utility routine, called from above as well. If called while the
12413 input file is still being read, it's only an approximation. (For
12414 example, a symbol may later become defined which appeared to be
12415 undefined earlier.) */
12418 nopic_need_relax (symbolS
*sym
, int before_relaxing
)
12423 if (g_switch_value
> 0)
12425 const char *symname
;
12428 /* Find out whether this symbol can be referenced off the $gp
12429 register. It can be if it is smaller than the -G size or if
12430 it is in the .sdata or .sbss section. Certain symbols can
12431 not be referenced off the $gp, although it appears as though
12433 symname
= S_GET_NAME (sym
);
12434 if (symname
!= (const char *) NULL
12435 && (strcmp (symname
, "eprol") == 0
12436 || strcmp (symname
, "etext") == 0
12437 || strcmp (symname
, "_gp") == 0
12438 || strcmp (symname
, "edata") == 0
12439 || strcmp (symname
, "_fbss") == 0
12440 || strcmp (symname
, "_fdata") == 0
12441 || strcmp (symname
, "_ftext") == 0
12442 || strcmp (symname
, "end") == 0
12443 || strcmp (symname
, "_gp_disp") == 0))
12445 else if ((! S_IS_DEFINED (sym
) || S_IS_COMMON (sym
))
12447 #ifndef NO_ECOFF_DEBUGGING
12448 || (symbol_get_obj (sym
)->ecoff_extern_size
!= 0
12449 && (symbol_get_obj (sym
)->ecoff_extern_size
12450 <= g_switch_value
))
12452 /* We must defer this decision until after the whole
12453 file has been read, since there might be a .extern
12454 after the first use of this symbol. */
12455 || (before_relaxing
12456 #ifndef NO_ECOFF_DEBUGGING
12457 && symbol_get_obj (sym
)->ecoff_extern_size
== 0
12459 && S_GET_VALUE (sym
) == 0)
12460 || (S_GET_VALUE (sym
) != 0
12461 && S_GET_VALUE (sym
) <= g_switch_value
)))
12465 const char *segname
;
12467 segname
= segment_name (S_GET_SEGMENT (sym
));
12468 assert (strcmp (segname
, ".lit8") != 0
12469 && strcmp (segname
, ".lit4") != 0);
12470 change
= (strcmp (segname
, ".sdata") != 0
12471 && strcmp (segname
, ".sbss") != 0
12472 && strncmp (segname
, ".sdata.", 7) != 0
12473 && strncmp (segname
, ".gnu.linkonce.s.", 16) != 0);
12478 /* We are not optimizing for the $gp register. */
12483 /* Return true if the given symbol should be considered local for SVR4 PIC. */
12486 pic_need_relax (symbolS
*sym
, asection
*segtype
)
12489 bfd_boolean linkonce
;
12491 /* Handle the case of a symbol equated to another symbol. */
12492 while (symbol_equated_reloc_p (sym
))
12496 /* It's possible to get a loop here in a badly written
12498 n
= symbol_get_value_expression (sym
)->X_add_symbol
;
12504 symsec
= S_GET_SEGMENT (sym
);
12506 /* duplicate the test for LINK_ONCE sections as in adjust_reloc_syms */
12508 if (symsec
!= segtype
&& ! S_IS_LOCAL (sym
))
12510 if ((bfd_get_section_flags (stdoutput
, symsec
) & SEC_LINK_ONCE
)
12514 /* The GNU toolchain uses an extension for ELF: a section
12515 beginning with the magic string .gnu.linkonce is a linkonce
12517 if (strncmp (segment_name (symsec
), ".gnu.linkonce",
12518 sizeof ".gnu.linkonce" - 1) == 0)
12522 /* This must duplicate the test in adjust_reloc_syms. */
12523 return (symsec
!= &bfd_und_section
12524 && symsec
!= &bfd_abs_section
12525 && ! bfd_is_com_section (symsec
)
12528 /* A global or weak symbol is treated as external. */
12529 && (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
12530 || (! S_IS_WEAK (sym
) && ! S_IS_EXTERNAL (sym
)))
12536 /* Given a mips16 variant frag FRAGP, return non-zero if it needs an
12537 extended opcode. SEC is the section the frag is in. */
12540 mips16_extended_frag (fragS
*fragp
, asection
*sec
, long stretch
)
12543 register const struct mips16_immed_operand
*op
;
12545 int mintiny
, maxtiny
;
12549 if (RELAX_MIPS16_USER_SMALL (fragp
->fr_subtype
))
12551 if (RELAX_MIPS16_USER_EXT (fragp
->fr_subtype
))
12554 type
= RELAX_MIPS16_TYPE (fragp
->fr_subtype
);
12555 op
= mips16_immed_operands
;
12556 while (op
->type
!= type
)
12559 assert (op
< mips16_immed_operands
+ MIPS16_NUM_IMMED
);
12564 if (type
== '<' || type
== '>' || type
== '[' || type
== ']')
12567 maxtiny
= 1 << op
->nbits
;
12572 maxtiny
= (1 << op
->nbits
) - 1;
12577 mintiny
= - (1 << (op
->nbits
- 1));
12578 maxtiny
= (1 << (op
->nbits
- 1)) - 1;
12581 sym_frag
= symbol_get_frag (fragp
->fr_symbol
);
12582 val
= S_GET_VALUE (fragp
->fr_symbol
);
12583 symsec
= S_GET_SEGMENT (fragp
->fr_symbol
);
12589 /* We won't have the section when we are called from
12590 mips_relax_frag. However, we will always have been called
12591 from md_estimate_size_before_relax first. If this is a
12592 branch to a different section, we mark it as such. If SEC is
12593 NULL, and the frag is not marked, then it must be a branch to
12594 the same section. */
12597 if (RELAX_MIPS16_LONG_BRANCH (fragp
->fr_subtype
))
12602 /* Must have been called from md_estimate_size_before_relax. */
12605 fragp
->fr_subtype
=
12606 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
12608 /* FIXME: We should support this, and let the linker
12609 catch branches and loads that are out of range. */
12610 as_bad_where (fragp
->fr_file
, fragp
->fr_line
,
12611 _("unsupported PC relative reference to different section"));
12615 if (fragp
!= sym_frag
&& sym_frag
->fr_address
== 0)
12616 /* Assume non-extended on the first relaxation pass.
12617 The address we have calculated will be bogus if this is
12618 a forward branch to another frag, as the forward frag
12619 will have fr_address == 0. */
12623 /* In this case, we know for sure that the symbol fragment is in
12624 the same section. If the relax_marker of the symbol fragment
12625 differs from the relax_marker of this fragment, we have not
12626 yet adjusted the symbol fragment fr_address. We want to add
12627 in STRETCH in order to get a better estimate of the address.
12628 This particularly matters because of the shift bits. */
12630 && sym_frag
->relax_marker
!= fragp
->relax_marker
)
12634 /* Adjust stretch for any alignment frag. Note that if have
12635 been expanding the earlier code, the symbol may be
12636 defined in what appears to be an earlier frag. FIXME:
12637 This doesn't handle the fr_subtype field, which specifies
12638 a maximum number of bytes to skip when doing an
12640 for (f
= fragp
; f
!= NULL
&& f
!= sym_frag
; f
= f
->fr_next
)
12642 if (f
->fr_type
== rs_align
|| f
->fr_type
== rs_align_code
)
12645 stretch
= - ((- stretch
)
12646 & ~ ((1 << (int) f
->fr_offset
) - 1));
12648 stretch
&= ~ ((1 << (int) f
->fr_offset
) - 1);
12657 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
12659 /* The base address rules are complicated. The base address of
12660 a branch is the following instruction. The base address of a
12661 PC relative load or add is the instruction itself, but if it
12662 is in a delay slot (in which case it can not be extended) use
12663 the address of the instruction whose delay slot it is in. */
12664 if (type
== 'p' || type
== 'q')
12668 /* If we are currently assuming that this frag should be
12669 extended, then, the current address is two bytes
12671 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
12674 /* Ignore the low bit in the target, since it will be set
12675 for a text label. */
12676 if ((val
& 1) != 0)
12679 else if (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
))
12681 else if (RELAX_MIPS16_DSLOT (fragp
->fr_subtype
))
12684 val
-= addr
& ~ ((1 << op
->shift
) - 1);
12686 /* Branch offsets have an implicit 0 in the lowest bit. */
12687 if (type
== 'p' || type
== 'q')
12690 /* If any of the shifted bits are set, we must use an extended
12691 opcode. If the address depends on the size of this
12692 instruction, this can lead to a loop, so we arrange to always
12693 use an extended opcode. We only check this when we are in
12694 the main relaxation loop, when SEC is NULL. */
12695 if ((val
& ((1 << op
->shift
) - 1)) != 0 && sec
== NULL
)
12697 fragp
->fr_subtype
=
12698 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
12702 /* If we are about to mark a frag as extended because the value
12703 is precisely maxtiny + 1, then there is a chance of an
12704 infinite loop as in the following code:
12709 In this case when the la is extended, foo is 0x3fc bytes
12710 away, so the la can be shrunk, but then foo is 0x400 away, so
12711 the la must be extended. To avoid this loop, we mark the
12712 frag as extended if it was small, and is about to become
12713 extended with a value of maxtiny + 1. */
12714 if (val
== ((maxtiny
+ 1) << op
->shift
)
12715 && ! RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
)
12718 fragp
->fr_subtype
=
12719 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
12723 else if (symsec
!= absolute_section
&& sec
!= NULL
)
12724 as_bad_where (fragp
->fr_file
, fragp
->fr_line
, _("unsupported relocation"));
12726 if ((val
& ((1 << op
->shift
) - 1)) != 0
12727 || val
< (mintiny
<< op
->shift
)
12728 || val
> (maxtiny
<< op
->shift
))
12734 /* Compute the length of a branch sequence, and adjust the
12735 RELAX_BRANCH_TOOFAR bit accordingly. If FRAGP is NULL, the
12736 worst-case length is computed, with UPDATE being used to indicate
12737 whether an unconditional (-1), branch-likely (+1) or regular (0)
12738 branch is to be computed. */
12740 relaxed_branch_length (fragS
*fragp
, asection
*sec
, int update
)
12742 bfd_boolean toofar
;
12746 && S_IS_DEFINED (fragp
->fr_symbol
)
12747 && sec
== S_GET_SEGMENT (fragp
->fr_symbol
))
12752 val
= S_GET_VALUE (fragp
->fr_symbol
) + fragp
->fr_offset
;
12754 addr
= fragp
->fr_address
+ fragp
->fr_fix
+ 4;
12758 toofar
= val
< - (0x8000 << 2) || val
>= (0x8000 << 2);
12761 /* If the symbol is not defined or it's in a different segment,
12762 assume the user knows what's going on and emit a short
12768 if (fragp
&& update
&& toofar
!= RELAX_BRANCH_TOOFAR (fragp
->fr_subtype
))
12770 = RELAX_BRANCH_ENCODE (RELAX_BRANCH_UNCOND (fragp
->fr_subtype
),
12771 RELAX_BRANCH_LIKELY (fragp
->fr_subtype
),
12772 RELAX_BRANCH_LINK (fragp
->fr_subtype
),
12778 if (fragp
? RELAX_BRANCH_LIKELY (fragp
->fr_subtype
) : (update
> 0))
12781 if (mips_pic
!= NO_PIC
)
12783 /* Additional space for PIC loading of target address. */
12785 if (mips_opts
.isa
== ISA_MIPS1
)
12786 /* Additional space for $at-stabilizing nop. */
12790 /* If branch is conditional. */
12791 if (fragp
? !RELAX_BRANCH_UNCOND (fragp
->fr_subtype
) : (update
>= 0))
12798 /* Estimate the size of a frag before relaxing. Unless this is the
12799 mips16, we are not really relaxing here, and the final size is
12800 encoded in the subtype information. For the mips16, we have to
12801 decide whether we are using an extended opcode or not. */
12804 md_estimate_size_before_relax (fragS
*fragp
, asection
*segtype
)
12808 if (RELAX_BRANCH_P (fragp
->fr_subtype
))
12811 fragp
->fr_var
= relaxed_branch_length (fragp
, segtype
, FALSE
);
12813 return fragp
->fr_var
;
12816 if (RELAX_MIPS16_P (fragp
->fr_subtype
))
12817 /* We don't want to modify the EXTENDED bit here; it might get us
12818 into infinite loops. We change it only in mips_relax_frag(). */
12819 return (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
) ? 4 : 2);
12821 if (mips_pic
== NO_PIC
)
12822 change
= nopic_need_relax (fragp
->fr_symbol
, 0);
12823 else if (mips_pic
== SVR4_PIC
)
12824 change
= pic_need_relax (fragp
->fr_symbol
, segtype
);
12830 fragp
->fr_subtype
|= RELAX_USE_SECOND
;
12831 return -RELAX_FIRST (fragp
->fr_subtype
);
12834 return -RELAX_SECOND (fragp
->fr_subtype
);
12837 /* This is called to see whether a reloc against a defined symbol
12838 should be converted into a reloc against a section. */
12841 mips_fix_adjustable (fixS
*fixp
)
12843 /* Don't adjust MIPS16 jump relocations, so we don't have to worry
12844 about the format of the offset in the .o file. */
12845 if (fixp
->fx_r_type
== BFD_RELOC_MIPS16_JMP
)
12848 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
12849 || fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
12852 if (fixp
->fx_addsy
== NULL
)
12855 /* If symbol SYM is in a mergeable section, relocations of the form
12856 SYM + 0 can usually be made section-relative. The mergeable data
12857 is then identified by the section offset rather than by the symbol.
12859 However, if we're generating REL LO16 relocations, the offset is split
12860 between the LO16 and parterning high part relocation. The linker will
12861 need to recalculate the complete offset in order to correctly identify
12864 The linker has traditionally not looked for the parterning high part
12865 relocation, and has thus allowed orphaned R_MIPS_LO16 relocations to be
12866 placed anywhere. Rather than break backwards compatibility by changing
12867 this, it seems better not to force the issue, and instead keep the
12868 original symbol. This will work with either linker behavior. */
12869 if ((fixp
->fx_r_type
== BFD_RELOC_LO16
|| reloc_needs_lo_p (fixp
->fx_r_type
))
12870 && HAVE_IN_PLACE_ADDENDS
12871 && (S_GET_SEGMENT (fixp
->fx_addsy
)->flags
& SEC_MERGE
) != 0)
12875 /* Don't adjust relocations against mips16 symbols, so that the linker
12876 can find them if it needs to set up a stub. */
12877 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
12878 && S_GET_OTHER (fixp
->fx_addsy
) == STO_MIPS16
12879 && fixp
->fx_subsy
== NULL
)
12886 /* Translate internal representation of relocation info to BFD target
12890 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
, fixS
*fixp
)
12892 static arelent
*retval
[4];
12894 bfd_reloc_code_real_type code
;
12896 memset (retval
, 0, sizeof(retval
));
12897 reloc
= retval
[0] = (arelent
*) xcalloc (1, sizeof (arelent
));
12898 reloc
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
12899 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
12900 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
12902 assert (! fixp
->fx_pcrel
);
12903 reloc
->addend
= fixp
->fx_addnumber
;
12905 /* Since the old MIPS ELF ABI uses Rel instead of Rela, encode the vtable
12906 entry to be used in the relocation's section offset. */
12907 if (! HAVE_NEWABI
&& fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
12909 reloc
->address
= reloc
->addend
;
12913 code
= fixp
->fx_r_type
;
12915 /* To support a PC relative reloc, we used a Cygnus extension.
12916 We check for that here to make sure that we don't let such a
12917 reloc escape normally. (FIXME: This was formerly used by
12918 embedded-PIC support, but is now used by branch handling in
12919 general. That probably should be fixed.) */
12920 if ((OUTPUT_FLAVOR
== bfd_target_ecoff_flavour
12921 || OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
12922 && code
== BFD_RELOC_16_PCREL_S2
)
12923 reloc
->howto
= NULL
;
12925 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
12927 if (reloc
->howto
== NULL
)
12929 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
12930 _("Can not represent %s relocation in this object file format"),
12931 bfd_get_reloc_code_name (code
));
12938 /* Relax a machine dependent frag. This returns the amount by which
12939 the current size of the frag should change. */
12942 mips_relax_frag (asection
*sec
, fragS
*fragp
, long stretch
)
12944 if (RELAX_BRANCH_P (fragp
->fr_subtype
))
12946 offsetT old_var
= fragp
->fr_var
;
12948 fragp
->fr_var
= relaxed_branch_length (fragp
, sec
, TRUE
);
12950 return fragp
->fr_var
- old_var
;
12953 if (! RELAX_MIPS16_P (fragp
->fr_subtype
))
12956 if (mips16_extended_frag (fragp
, NULL
, stretch
))
12958 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
12960 fragp
->fr_subtype
= RELAX_MIPS16_MARK_EXTENDED (fragp
->fr_subtype
);
12965 if (! RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
12967 fragp
->fr_subtype
= RELAX_MIPS16_CLEAR_EXTENDED (fragp
->fr_subtype
);
12974 /* Convert a machine dependent frag. */
12977 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
, segT asec
, fragS
*fragp
)
12979 if (RELAX_BRANCH_P (fragp
->fr_subtype
))
12982 unsigned long insn
;
12986 buf
= (bfd_byte
*)fragp
->fr_literal
+ fragp
->fr_fix
;
12988 if (target_big_endian
)
12989 insn
= bfd_getb32 (buf
);
12991 insn
= bfd_getl32 (buf
);
12993 if (!RELAX_BRANCH_TOOFAR (fragp
->fr_subtype
))
12995 /* We generate a fixup instead of applying it right now
12996 because, if there are linker relaxations, we're going to
12997 need the relocations. */
12998 exp
.X_op
= O_symbol
;
12999 exp
.X_add_symbol
= fragp
->fr_symbol
;
13000 exp
.X_add_number
= fragp
->fr_offset
;
13002 fixp
= fix_new_exp (fragp
, buf
- (bfd_byte
*)fragp
->fr_literal
,
13004 BFD_RELOC_16_PCREL_S2
);
13005 fixp
->fx_file
= fragp
->fr_file
;
13006 fixp
->fx_line
= fragp
->fr_line
;
13008 md_number_to_chars ((char *) buf
, insn
, 4);
13015 as_warn_where (fragp
->fr_file
, fragp
->fr_line
,
13016 _("relaxed out-of-range branch into a jump"));
13018 if (RELAX_BRANCH_UNCOND (fragp
->fr_subtype
))
13021 if (!RELAX_BRANCH_LIKELY (fragp
->fr_subtype
))
13023 /* Reverse the branch. */
13024 switch ((insn
>> 28) & 0xf)
13027 /* bc[0-3][tf]l? and bc1any[24][ft] instructions can
13028 have the condition reversed by tweaking a single
13029 bit, and their opcodes all have 0x4???????. */
13030 assert ((insn
& 0xf1000000) == 0x41000000);
13031 insn
^= 0x00010000;
13035 /* bltz 0x04000000 bgez 0x04010000
13036 bltzal 0x04100000 bgezal 0x04110000 */
13037 assert ((insn
& 0xfc0e0000) == 0x04000000);
13038 insn
^= 0x00010000;
13042 /* beq 0x10000000 bne 0x14000000
13043 blez 0x18000000 bgtz 0x1c000000 */
13044 insn
^= 0x04000000;
13052 if (RELAX_BRANCH_LINK (fragp
->fr_subtype
))
13054 /* Clear the and-link bit. */
13055 assert ((insn
& 0xfc1c0000) == 0x04100000);
13057 /* bltzal 0x04100000 bgezal 0x04110000
13058 bltzall 0x04120000 bgezall 0x04130000 */
13059 insn
&= ~0x00100000;
13062 /* Branch over the branch (if the branch was likely) or the
13063 full jump (not likely case). Compute the offset from the
13064 current instruction to branch to. */
13065 if (RELAX_BRANCH_LIKELY (fragp
->fr_subtype
))
13069 /* How many bytes in instructions we've already emitted? */
13070 i
= buf
- (bfd_byte
*)fragp
->fr_literal
- fragp
->fr_fix
;
13071 /* How many bytes in instructions from here to the end? */
13072 i
= fragp
->fr_var
- i
;
13074 /* Convert to instruction count. */
13076 /* Branch counts from the next instruction. */
13079 /* Branch over the jump. */
13080 md_number_to_chars ((char *) buf
, insn
, 4);
13084 md_number_to_chars ((char *) buf
, 0, 4);
13087 if (RELAX_BRANCH_LIKELY (fragp
->fr_subtype
))
13089 /* beql $0, $0, 2f */
13091 /* Compute the PC offset from the current instruction to
13092 the end of the variable frag. */
13093 /* How many bytes in instructions we've already emitted? */
13094 i
= buf
- (bfd_byte
*)fragp
->fr_literal
- fragp
->fr_fix
;
13095 /* How many bytes in instructions from here to the end? */
13096 i
= fragp
->fr_var
- i
;
13097 /* Convert to instruction count. */
13099 /* Don't decrement i, because we want to branch over the
13103 md_number_to_chars ((char *) buf
, insn
, 4);
13106 md_number_to_chars ((char *) buf
, 0, 4);
13111 if (mips_pic
== NO_PIC
)
13114 insn
= (RELAX_BRANCH_LINK (fragp
->fr_subtype
)
13115 ? 0x0c000000 : 0x08000000);
13116 exp
.X_op
= O_symbol
;
13117 exp
.X_add_symbol
= fragp
->fr_symbol
;
13118 exp
.X_add_number
= fragp
->fr_offset
;
13120 fixp
= fix_new_exp (fragp
, buf
- (bfd_byte
*)fragp
->fr_literal
,
13121 4, &exp
, 0, BFD_RELOC_MIPS_JMP
);
13122 fixp
->fx_file
= fragp
->fr_file
;
13123 fixp
->fx_line
= fragp
->fr_line
;
13125 md_number_to_chars ((char *) buf
, insn
, 4);
13130 /* lw/ld $at, <sym>($gp) R_MIPS_GOT16 */
13131 insn
= HAVE_64BIT_ADDRESSES
? 0xdf810000 : 0x8f810000;
13132 exp
.X_op
= O_symbol
;
13133 exp
.X_add_symbol
= fragp
->fr_symbol
;
13134 exp
.X_add_number
= fragp
->fr_offset
;
13136 if (fragp
->fr_offset
)
13138 exp
.X_add_symbol
= make_expr_symbol (&exp
);
13139 exp
.X_add_number
= 0;
13142 fixp
= fix_new_exp (fragp
, buf
- (bfd_byte
*)fragp
->fr_literal
,
13143 4, &exp
, 0, BFD_RELOC_MIPS_GOT16
);
13144 fixp
->fx_file
= fragp
->fr_file
;
13145 fixp
->fx_line
= fragp
->fr_line
;
13147 md_number_to_chars ((char *) buf
, insn
, 4);
13150 if (mips_opts
.isa
== ISA_MIPS1
)
13153 md_number_to_chars ((char *) buf
, 0, 4);
13157 /* d/addiu $at, $at, <sym> R_MIPS_LO16 */
13158 insn
= HAVE_64BIT_ADDRESSES
? 0x64210000 : 0x24210000;
13160 fixp
= fix_new_exp (fragp
, buf
- (bfd_byte
*)fragp
->fr_literal
,
13161 4, &exp
, 0, BFD_RELOC_LO16
);
13162 fixp
->fx_file
= fragp
->fr_file
;
13163 fixp
->fx_line
= fragp
->fr_line
;
13165 md_number_to_chars ((char *) buf
, insn
, 4);
13169 if (RELAX_BRANCH_LINK (fragp
->fr_subtype
))
13174 md_number_to_chars ((char *) buf
, insn
, 4);
13179 assert (buf
== (bfd_byte
*)fragp
->fr_literal
13180 + fragp
->fr_fix
+ fragp
->fr_var
);
13182 fragp
->fr_fix
+= fragp
->fr_var
;
13187 if (RELAX_MIPS16_P (fragp
->fr_subtype
))
13190 register const struct mips16_immed_operand
*op
;
13191 bfd_boolean small
, ext
;
13194 unsigned long insn
;
13195 bfd_boolean use_extend
;
13196 unsigned short extend
;
13198 type
= RELAX_MIPS16_TYPE (fragp
->fr_subtype
);
13199 op
= mips16_immed_operands
;
13200 while (op
->type
!= type
)
13203 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
13214 resolve_symbol_value (fragp
->fr_symbol
);
13215 val
= S_GET_VALUE (fragp
->fr_symbol
);
13220 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
13222 /* The rules for the base address of a PC relative reloc are
13223 complicated; see mips16_extended_frag. */
13224 if (type
== 'p' || type
== 'q')
13229 /* Ignore the low bit in the target, since it will be
13230 set for a text label. */
13231 if ((val
& 1) != 0)
13234 else if (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
))
13236 else if (RELAX_MIPS16_DSLOT (fragp
->fr_subtype
))
13239 addr
&= ~ (addressT
) ((1 << op
->shift
) - 1);
13242 /* Make sure the section winds up with the alignment we have
13245 record_alignment (asec
, op
->shift
);
13249 && (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
)
13250 || RELAX_MIPS16_DSLOT (fragp
->fr_subtype
)))
13251 as_warn_where (fragp
->fr_file
, fragp
->fr_line
,
13252 _("extended instruction in delay slot"));
13254 buf
= (bfd_byte
*) (fragp
->fr_literal
+ fragp
->fr_fix
);
13256 if (target_big_endian
)
13257 insn
= bfd_getb16 (buf
);
13259 insn
= bfd_getl16 (buf
);
13261 mips16_immed (fragp
->fr_file
, fragp
->fr_line
, type
, val
,
13262 RELAX_MIPS16_USER_EXT (fragp
->fr_subtype
),
13263 small
, ext
, &insn
, &use_extend
, &extend
);
13267 md_number_to_chars ((char *) buf
, 0xf000 | extend
, 2);
13268 fragp
->fr_fix
+= 2;
13272 md_number_to_chars ((char *) buf
, insn
, 2);
13273 fragp
->fr_fix
+= 2;
13281 first
= RELAX_FIRST (fragp
->fr_subtype
);
13282 second
= RELAX_SECOND (fragp
->fr_subtype
);
13283 fixp
= (fixS
*) fragp
->fr_opcode
;
13285 /* Possibly emit a warning if we've chosen the longer option. */
13286 if (((fragp
->fr_subtype
& RELAX_USE_SECOND
) != 0)
13287 == ((fragp
->fr_subtype
& RELAX_SECOND_LONGER
) != 0))
13289 const char *msg
= macro_warning (fragp
->fr_subtype
);
13291 as_warn_where (fragp
->fr_file
, fragp
->fr_line
, msg
);
13294 /* Go through all the fixups for the first sequence. Disable them
13295 (by marking them as done) if we're going to use the second
13296 sequence instead. */
13298 && fixp
->fx_frag
== fragp
13299 && fixp
->fx_where
< fragp
->fr_fix
- second
)
13301 if (fragp
->fr_subtype
& RELAX_USE_SECOND
)
13303 fixp
= fixp
->fx_next
;
13306 /* Go through the fixups for the second sequence. Disable them if
13307 we're going to use the first sequence, otherwise adjust their
13308 addresses to account for the relaxation. */
13309 while (fixp
&& fixp
->fx_frag
== fragp
)
13311 if (fragp
->fr_subtype
& RELAX_USE_SECOND
)
13312 fixp
->fx_where
-= first
;
13315 fixp
= fixp
->fx_next
;
13318 /* Now modify the frag contents. */
13319 if (fragp
->fr_subtype
& RELAX_USE_SECOND
)
13323 start
= fragp
->fr_literal
+ fragp
->fr_fix
- first
- second
;
13324 memmove (start
, start
+ first
, second
);
13325 fragp
->fr_fix
-= first
;
13328 fragp
->fr_fix
-= second
;
13334 /* This function is called after the relocs have been generated.
13335 We've been storing mips16 text labels as odd. Here we convert them
13336 back to even for the convenience of the debugger. */
13339 mips_frob_file_after_relocs (void)
13342 unsigned int count
, i
;
13344 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
13347 syms
= bfd_get_outsymbols (stdoutput
);
13348 count
= bfd_get_symcount (stdoutput
);
13349 for (i
= 0; i
< count
; i
++, syms
++)
13351 if (elf_symbol (*syms
)->internal_elf_sym
.st_other
== STO_MIPS16
13352 && ((*syms
)->value
& 1) != 0)
13354 (*syms
)->value
&= ~1;
13355 /* If the symbol has an odd size, it was probably computed
13356 incorrectly, so adjust that as well. */
13357 if ((elf_symbol (*syms
)->internal_elf_sym
.st_size
& 1) != 0)
13358 ++elf_symbol (*syms
)->internal_elf_sym
.st_size
;
13365 /* This function is called whenever a label is defined. It is used
13366 when handling branch delays; if a branch has a label, we assume we
13367 can not move it. */
13370 mips_define_label (symbolS
*sym
)
13372 struct insn_label_list
*l
;
13374 if (free_insn_labels
== NULL
)
13375 l
= (struct insn_label_list
*) xmalloc (sizeof *l
);
13378 l
= free_insn_labels
;
13379 free_insn_labels
= l
->next
;
13383 l
->next
= insn_labels
;
13387 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13389 /* Some special processing for a MIPS ELF file. */
13392 mips_elf_final_processing (void)
13394 /* Write out the register information. */
13395 if (mips_abi
!= N64_ABI
)
13399 s
.ri_gprmask
= mips_gprmask
;
13400 s
.ri_cprmask
[0] = mips_cprmask
[0];
13401 s
.ri_cprmask
[1] = mips_cprmask
[1];
13402 s
.ri_cprmask
[2] = mips_cprmask
[2];
13403 s
.ri_cprmask
[3] = mips_cprmask
[3];
13404 /* The gp_value field is set by the MIPS ELF backend. */
13406 bfd_mips_elf32_swap_reginfo_out (stdoutput
, &s
,
13407 ((Elf32_External_RegInfo
*)
13408 mips_regmask_frag
));
13412 Elf64_Internal_RegInfo s
;
13414 s
.ri_gprmask
= mips_gprmask
;
13416 s
.ri_cprmask
[0] = mips_cprmask
[0];
13417 s
.ri_cprmask
[1] = mips_cprmask
[1];
13418 s
.ri_cprmask
[2] = mips_cprmask
[2];
13419 s
.ri_cprmask
[3] = mips_cprmask
[3];
13420 /* The gp_value field is set by the MIPS ELF backend. */
13422 bfd_mips_elf64_swap_reginfo_out (stdoutput
, &s
,
13423 ((Elf64_External_RegInfo
*)
13424 mips_regmask_frag
));
13427 /* Set the MIPS ELF flag bits. FIXME: There should probably be some
13428 sort of BFD interface for this. */
13429 if (mips_any_noreorder
)
13430 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_NOREORDER
;
13431 if (mips_pic
!= NO_PIC
)
13433 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_PIC
;
13434 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_CPIC
;
13437 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_CPIC
;
13439 /* Set MIPS ELF flags for ASEs. */
13440 if (file_ase_mips16
)
13441 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ARCH_ASE_M16
;
13442 #if 0 /* XXX FIXME */
13443 if (file_ase_mips3d
)
13444 elf_elfheader (stdoutput
)->e_flags
|= ???;
13447 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ARCH_ASE_MDMX
;
13449 /* Set the MIPS ELF ABI flags. */
13450 if (mips_abi
== O32_ABI
&& USE_E_MIPS_ABI_O32
)
13451 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_O32
;
13452 else if (mips_abi
== O64_ABI
)
13453 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_O64
;
13454 else if (mips_abi
== EABI_ABI
)
13456 if (!file_mips_gp32
)
13457 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_EABI64
;
13459 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_EABI32
;
13461 else if (mips_abi
== N32_ABI
)
13462 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ABI2
;
13464 /* Nothing to do for N64_ABI. */
13466 if (mips_32bitmode
)
13467 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_32BITMODE
;
13470 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */
13472 typedef struct proc
{
13474 symbolS
*func_end_sym
;
13475 unsigned long reg_mask
;
13476 unsigned long reg_offset
;
13477 unsigned long fpreg_mask
;
13478 unsigned long fpreg_offset
;
13479 unsigned long frame_offset
;
13480 unsigned long frame_reg
;
13481 unsigned long pc_reg
;
13484 static procS cur_proc
;
13485 static procS
*cur_proc_ptr
;
13486 static int numprocs
;
13488 /* Fill in an rs_align_code fragment. */
13491 mips_handle_align (fragS
*fragp
)
13493 if (fragp
->fr_type
!= rs_align_code
)
13496 if (mips_opts
.mips16
)
13498 static const unsigned char be_nop
[] = { 0x65, 0x00 };
13499 static const unsigned char le_nop
[] = { 0x00, 0x65 };
13504 bytes
= fragp
->fr_next
->fr_address
- fragp
->fr_address
- fragp
->fr_fix
;
13505 p
= fragp
->fr_literal
+ fragp
->fr_fix
;
13513 memcpy (p
, (target_big_endian
? be_nop
: le_nop
), 2);
13517 /* For mips32, a nop is a zero, which we trivially get by doing nothing. */
13521 md_obj_begin (void)
13528 /* check for premature end, nesting errors, etc */
13530 as_warn (_("missing .end at end of assembly"));
13539 if (*input_line_pointer
== '-')
13541 ++input_line_pointer
;
13544 if (!ISDIGIT (*input_line_pointer
))
13545 as_bad (_("expected simple number"));
13546 if (input_line_pointer
[0] == '0')
13548 if (input_line_pointer
[1] == 'x')
13550 input_line_pointer
+= 2;
13551 while (ISXDIGIT (*input_line_pointer
))
13554 val
|= hex_value (*input_line_pointer
++);
13556 return negative
? -val
: val
;
13560 ++input_line_pointer
;
13561 while (ISDIGIT (*input_line_pointer
))
13564 val
|= *input_line_pointer
++ - '0';
13566 return negative
? -val
: val
;
13569 if (!ISDIGIT (*input_line_pointer
))
13571 printf (_(" *input_line_pointer == '%c' 0x%02x\n"),
13572 *input_line_pointer
, *input_line_pointer
);
13573 as_warn (_("invalid number"));
13576 while (ISDIGIT (*input_line_pointer
))
13579 val
+= *input_line_pointer
++ - '0';
13581 return negative
? -val
: val
;
13584 /* The .file directive; just like the usual .file directive, but there
13585 is an initial number which is the ECOFF file index. In the non-ECOFF
13586 case .file implies DWARF-2. */
13589 s_mips_file (int x ATTRIBUTE_UNUSED
)
13591 static int first_file_directive
= 0;
13593 if (ECOFF_DEBUGGING
)
13602 filename
= dwarf2_directive_file (0);
13604 /* Versions of GCC up to 3.1 start files with a ".file"
13605 directive even for stabs output. Make sure that this
13606 ".file" is handled. Note that you need a version of GCC
13607 after 3.1 in order to support DWARF-2 on MIPS. */
13608 if (filename
!= NULL
&& ! first_file_directive
)
13610 (void) new_logical_line (filename
, -1);
13611 s_app_file_string (filename
, 0);
13613 first_file_directive
= 1;
13617 /* The .loc directive, implying DWARF-2. */
13620 s_mips_loc (int x ATTRIBUTE_UNUSED
)
13622 if (!ECOFF_DEBUGGING
)
13623 dwarf2_directive_loc (0);
13626 /* The .end directive. */
13629 s_mips_end (int x ATTRIBUTE_UNUSED
)
13633 /* Following functions need their own .frame and .cprestore directives. */
13634 mips_frame_reg_valid
= 0;
13635 mips_cprestore_valid
= 0;
13637 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
13640 demand_empty_rest_of_line ();
13645 if ((bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) == 0)
13646 as_warn (_(".end not in text section"));
13650 as_warn (_(".end directive without a preceding .ent directive."));
13651 demand_empty_rest_of_line ();
13657 assert (S_GET_NAME (p
));
13658 if (strcmp (S_GET_NAME (p
), S_GET_NAME (cur_proc_ptr
->func_sym
)))
13659 as_warn (_(".end symbol does not match .ent symbol."));
13661 if (debug_type
== DEBUG_STABS
)
13662 stabs_generate_asm_endfunc (S_GET_NAME (p
),
13666 as_warn (_(".end directive missing or unknown symbol"));
13669 /* Create an expression to calculate the size of the function. */
13670 if (p
&& cur_proc_ptr
)
13672 OBJ_SYMFIELD_TYPE
*obj
= symbol_get_obj (p
);
13673 expressionS
*exp
= xmalloc (sizeof (expressionS
));
13676 exp
->X_op
= O_subtract
;
13677 exp
->X_add_symbol
= symbol_temp_new_now ();
13678 exp
->X_op_symbol
= p
;
13679 exp
->X_add_number
= 0;
13681 cur_proc_ptr
->func_end_sym
= exp
->X_add_symbol
;
13684 /* Generate a .pdr section. */
13685 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
&& ! ECOFF_DEBUGGING
13688 segT saved_seg
= now_seg
;
13689 subsegT saved_subseg
= now_subseg
;
13694 dot
= frag_now_fix ();
13696 #ifdef md_flush_pending_output
13697 md_flush_pending_output ();
13701 subseg_set (pdr_seg
, 0);
13703 /* Write the symbol. */
13704 exp
.X_op
= O_symbol
;
13705 exp
.X_add_symbol
= p
;
13706 exp
.X_add_number
= 0;
13707 emit_expr (&exp
, 4);
13709 fragp
= frag_more (7 * 4);
13711 md_number_to_chars (fragp
, cur_proc_ptr
->reg_mask
, 4);
13712 md_number_to_chars (fragp
+ 4, cur_proc_ptr
->reg_offset
, 4);
13713 md_number_to_chars (fragp
+ 8, cur_proc_ptr
->fpreg_mask
, 4);
13714 md_number_to_chars (fragp
+ 12, cur_proc_ptr
->fpreg_offset
, 4);
13715 md_number_to_chars (fragp
+ 16, cur_proc_ptr
->frame_offset
, 4);
13716 md_number_to_chars (fragp
+ 20, cur_proc_ptr
->frame_reg
, 4);
13717 md_number_to_chars (fragp
+ 24, cur_proc_ptr
->pc_reg
, 4);
13719 subseg_set (saved_seg
, saved_subseg
);
13721 #endif /* OBJ_ELF */
13723 cur_proc_ptr
= NULL
;
13726 /* The .aent and .ent directives. */
13729 s_mips_ent (int aent
)
13733 symbolP
= get_symbol ();
13734 if (*input_line_pointer
== ',')
13735 ++input_line_pointer
;
13736 SKIP_WHITESPACE ();
13737 if (ISDIGIT (*input_line_pointer
)
13738 || *input_line_pointer
== '-')
13741 if ((bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) == 0)
13742 as_warn (_(".ent or .aent not in text section."));
13744 if (!aent
&& cur_proc_ptr
)
13745 as_warn (_("missing .end"));
13749 /* This function needs its own .frame and .cprestore directives. */
13750 mips_frame_reg_valid
= 0;
13751 mips_cprestore_valid
= 0;
13753 cur_proc_ptr
= &cur_proc
;
13754 memset (cur_proc_ptr
, '\0', sizeof (procS
));
13756 cur_proc_ptr
->func_sym
= symbolP
;
13758 symbol_get_bfdsym (symbolP
)->flags
|= BSF_FUNCTION
;
13762 if (debug_type
== DEBUG_STABS
)
13763 stabs_generate_asm_func (S_GET_NAME (symbolP
),
13764 S_GET_NAME (symbolP
));
13767 demand_empty_rest_of_line ();
13770 /* The .frame directive. If the mdebug section is present (IRIX 5 native)
13771 then ecoff.c (ecoff_directive_frame) is used. For embedded targets,
13772 s_mips_frame is used so that we can set the PDR information correctly.
13773 We can't use the ecoff routines because they make reference to the ecoff
13774 symbol table (in the mdebug section). */
13777 s_mips_frame (int ignore ATTRIBUTE_UNUSED
)
13780 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
&& ! ECOFF_DEBUGGING
)
13784 if (cur_proc_ptr
== (procS
*) NULL
)
13786 as_warn (_(".frame outside of .ent"));
13787 demand_empty_rest_of_line ();
13791 cur_proc_ptr
->frame_reg
= tc_get_register (1);
13793 SKIP_WHITESPACE ();
13794 if (*input_line_pointer
++ != ','
13795 || get_absolute_expression_and_terminator (&val
) != ',')
13797 as_warn (_("Bad .frame directive"));
13798 --input_line_pointer
;
13799 demand_empty_rest_of_line ();
13803 cur_proc_ptr
->frame_offset
= val
;
13804 cur_proc_ptr
->pc_reg
= tc_get_register (0);
13806 demand_empty_rest_of_line ();
13809 #endif /* OBJ_ELF */
13813 /* The .fmask and .mask directives. If the mdebug section is present
13814 (IRIX 5 native) then ecoff.c (ecoff_directive_mask) is used. For
13815 embedded targets, s_mips_mask is used so that we can set the PDR
13816 information correctly. We can't use the ecoff routines because they
13817 make reference to the ecoff symbol table (in the mdebug section). */
13820 s_mips_mask (int reg_type
)
13823 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
&& ! ECOFF_DEBUGGING
)
13827 if (cur_proc_ptr
== (procS
*) NULL
)
13829 as_warn (_(".mask/.fmask outside of .ent"));
13830 demand_empty_rest_of_line ();
13834 if (get_absolute_expression_and_terminator (&mask
) != ',')
13836 as_warn (_("Bad .mask/.fmask directive"));
13837 --input_line_pointer
;
13838 demand_empty_rest_of_line ();
13842 off
= get_absolute_expression ();
13844 if (reg_type
== 'F')
13846 cur_proc_ptr
->fpreg_mask
= mask
;
13847 cur_proc_ptr
->fpreg_offset
= off
;
13851 cur_proc_ptr
->reg_mask
= mask
;
13852 cur_proc_ptr
->reg_offset
= off
;
13855 demand_empty_rest_of_line ();
13858 #endif /* OBJ_ELF */
13859 s_ignore (reg_type
);
13862 /* A table describing all the processors gas knows about. Names are
13863 matched in the order listed.
13865 To ease comparison, please keep this table in the same order as
13866 gcc's mips_cpu_info_table[]. */
13867 static const struct mips_cpu_info mips_cpu_info_table
[] =
13869 /* Entries for generic ISAs */
13870 { "mips1", 1, ISA_MIPS1
, CPU_R3000
},
13871 { "mips2", 1, ISA_MIPS2
, CPU_R6000
},
13872 { "mips3", 1, ISA_MIPS3
, CPU_R4000
},
13873 { "mips4", 1, ISA_MIPS4
, CPU_R8000
},
13874 { "mips5", 1, ISA_MIPS5
, CPU_MIPS5
},
13875 { "mips32", 1, ISA_MIPS32
, CPU_MIPS32
},
13876 { "mips32r2", 1, ISA_MIPS32R2
, CPU_MIPS32R2
},
13877 { "mips64", 1, ISA_MIPS64
, CPU_MIPS64
},
13878 { "mips64r2", 1, ISA_MIPS64R2
, CPU_MIPS64R2
},
13881 { "r3000", 0, ISA_MIPS1
, CPU_R3000
},
13882 { "r2000", 0, ISA_MIPS1
, CPU_R3000
},
13883 { "r3900", 0, ISA_MIPS1
, CPU_R3900
},
13886 { "r6000", 0, ISA_MIPS2
, CPU_R6000
},
13889 { "r4000", 0, ISA_MIPS3
, CPU_R4000
},
13890 { "r4010", 0, ISA_MIPS2
, CPU_R4010
},
13891 { "vr4100", 0, ISA_MIPS3
, CPU_VR4100
},
13892 { "vr4111", 0, ISA_MIPS3
, CPU_R4111
},
13893 { "vr4120", 0, ISA_MIPS3
, CPU_VR4120
},
13894 { "vr4130", 0, ISA_MIPS3
, CPU_VR4120
},
13895 { "vr4181", 0, ISA_MIPS3
, CPU_R4111
},
13896 { "vr4300", 0, ISA_MIPS3
, CPU_R4300
},
13897 { "r4400", 0, ISA_MIPS3
, CPU_R4400
},
13898 { "r4600", 0, ISA_MIPS3
, CPU_R4600
},
13899 { "orion", 0, ISA_MIPS3
, CPU_R4600
},
13900 { "r4650", 0, ISA_MIPS3
, CPU_R4650
},
13903 { "r8000", 0, ISA_MIPS4
, CPU_R8000
},
13904 { "r10000", 0, ISA_MIPS4
, CPU_R10000
},
13905 { "r12000", 0, ISA_MIPS4
, CPU_R12000
},
13906 { "vr5000", 0, ISA_MIPS4
, CPU_R5000
},
13907 { "vr5400", 0, ISA_MIPS4
, CPU_VR5400
},
13908 { "vr5500", 0, ISA_MIPS4
, CPU_VR5500
},
13909 { "rm5200", 0, ISA_MIPS4
, CPU_R5000
},
13910 { "rm5230", 0, ISA_MIPS4
, CPU_R5000
},
13911 { "rm5231", 0, ISA_MIPS4
, CPU_R5000
},
13912 { "rm5261", 0, ISA_MIPS4
, CPU_R5000
},
13913 { "rm5721", 0, ISA_MIPS4
, CPU_R5000
},
13914 { "rm7000", 0, ISA_MIPS4
, CPU_RM7000
},
13915 { "rm9000", 0, ISA_MIPS4
, CPU_RM9000
},
13918 { "4kc", 0, ISA_MIPS32
, CPU_MIPS32
},
13919 { "4km", 0, ISA_MIPS32
, CPU_MIPS32
},
13920 { "4kp", 0, ISA_MIPS32
, CPU_MIPS32
},
13923 { "5kc", 0, ISA_MIPS64
, CPU_MIPS64
},
13924 { "20kc", 0, ISA_MIPS64
, CPU_MIPS64
},
13926 /* Broadcom SB-1 CPU core */
13927 { "sb1", 0, ISA_MIPS64
, CPU_SB1
},
13934 /* Return true if GIVEN is the same as CANONICAL, or if it is CANONICAL
13935 with a final "000" replaced by "k". Ignore case.
13937 Note: this function is shared between GCC and GAS. */
13940 mips_strict_matching_cpu_name_p (const char *canonical
, const char *given
)
13942 while (*given
!= 0 && TOLOWER (*given
) == TOLOWER (*canonical
))
13943 given
++, canonical
++;
13945 return ((*given
== 0 && *canonical
== 0)
13946 || (strcmp (canonical
, "000") == 0 && strcasecmp (given
, "k") == 0));
13950 /* Return true if GIVEN matches CANONICAL, where GIVEN is a user-supplied
13951 CPU name. We've traditionally allowed a lot of variation here.
13953 Note: this function is shared between GCC and GAS. */
13956 mips_matching_cpu_name_p (const char *canonical
, const char *given
)
13958 /* First see if the name matches exactly, or with a final "000"
13959 turned into "k". */
13960 if (mips_strict_matching_cpu_name_p (canonical
, given
))
13963 /* If not, try comparing based on numerical designation alone.
13964 See if GIVEN is an unadorned number, or 'r' followed by a number. */
13965 if (TOLOWER (*given
) == 'r')
13967 if (!ISDIGIT (*given
))
13970 /* Skip over some well-known prefixes in the canonical name,
13971 hoping to find a number there too. */
13972 if (TOLOWER (canonical
[0]) == 'v' && TOLOWER (canonical
[1]) == 'r')
13974 else if (TOLOWER (canonical
[0]) == 'r' && TOLOWER (canonical
[1]) == 'm')
13976 else if (TOLOWER (canonical
[0]) == 'r')
13979 return mips_strict_matching_cpu_name_p (canonical
, given
);
13983 /* Parse an option that takes the name of a processor as its argument.
13984 OPTION is the name of the option and CPU_STRING is the argument.
13985 Return the corresponding processor enumeration if the CPU_STRING is
13986 recognized, otherwise report an error and return null.
13988 A similar function exists in GCC. */
13990 static const struct mips_cpu_info
*
13991 mips_parse_cpu (const char *option
, const char *cpu_string
)
13993 const struct mips_cpu_info
*p
;
13995 /* 'from-abi' selects the most compatible architecture for the given
13996 ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit ABIs. For the
13997 EABIs, we have to decide whether we're using the 32-bit or 64-bit
13998 version. Look first at the -mgp options, if given, otherwise base
13999 the choice on MIPS_DEFAULT_64BIT.
14001 Treat NO_ABI like the EABIs. One reason to do this is that the
14002 plain 'mips' and 'mips64' configs have 'from-abi' as their default
14003 architecture. This code picks MIPS I for 'mips' and MIPS III for
14004 'mips64', just as we did in the days before 'from-abi'. */
14005 if (strcasecmp (cpu_string
, "from-abi") == 0)
14007 if (ABI_NEEDS_32BIT_REGS (mips_abi
))
14008 return mips_cpu_info_from_isa (ISA_MIPS1
);
14010 if (ABI_NEEDS_64BIT_REGS (mips_abi
))
14011 return mips_cpu_info_from_isa (ISA_MIPS3
);
14013 if (file_mips_gp32
>= 0)
14014 return mips_cpu_info_from_isa (file_mips_gp32
? ISA_MIPS1
: ISA_MIPS3
);
14016 return mips_cpu_info_from_isa (MIPS_DEFAULT_64BIT
14021 /* 'default' has traditionally been a no-op. Probably not very useful. */
14022 if (strcasecmp (cpu_string
, "default") == 0)
14025 for (p
= mips_cpu_info_table
; p
->name
!= 0; p
++)
14026 if (mips_matching_cpu_name_p (p
->name
, cpu_string
))
14029 as_bad ("Bad value (%s) for %s", cpu_string
, option
);
14033 /* Return the canonical processor information for ISA (a member of the
14034 ISA_MIPS* enumeration). */
14036 static const struct mips_cpu_info
*
14037 mips_cpu_info_from_isa (int isa
)
14041 for (i
= 0; mips_cpu_info_table
[i
].name
!= NULL
; i
++)
14042 if (mips_cpu_info_table
[i
].is_isa
14043 && isa
== mips_cpu_info_table
[i
].isa
)
14044 return (&mips_cpu_info_table
[i
]);
14049 static const struct mips_cpu_info
*
14050 mips_cpu_info_from_arch (int arch
)
14054 for (i
= 0; mips_cpu_info_table
[i
].name
!= NULL
; i
++)
14055 if (arch
== mips_cpu_info_table
[i
].cpu
)
14056 return (&mips_cpu_info_table
[i
]);
14062 show (FILE *stream
, const char *string
, int *col_p
, int *first_p
)
14066 fprintf (stream
, "%24s", "");
14071 fprintf (stream
, ", ");
14075 if (*col_p
+ strlen (string
) > 72)
14077 fprintf (stream
, "\n%24s", "");
14081 fprintf (stream
, "%s", string
);
14082 *col_p
+= strlen (string
);
14088 md_show_usage (FILE *stream
)
14093 fprintf (stream
, _("\
14095 -EB generate big endian output\n\
14096 -EL generate little endian output\n\
14097 -g, -g2 do not remove unneeded NOPs or swap branches\n\
14098 -G NUM allow referencing objects up to NUM bytes\n\
14099 implicitly with the gp register [default 8]\n"));
14100 fprintf (stream
, _("\
14101 -mips1 generate MIPS ISA I instructions\n\
14102 -mips2 generate MIPS ISA II instructions\n\
14103 -mips3 generate MIPS ISA III instructions\n\
14104 -mips4 generate MIPS ISA IV instructions\n\
14105 -mips5 generate MIPS ISA V instructions\n\
14106 -mips32 generate MIPS32 ISA instructions\n\
14107 -mips32r2 generate MIPS32 release 2 ISA instructions\n\
14108 -mips64 generate MIPS64 ISA instructions\n\
14109 -mips64r2 generate MIPS64 release 2 ISA instructions\n\
14110 -march=CPU/-mtune=CPU generate code/schedule for CPU, where CPU is one of:\n"));
14114 for (i
= 0; mips_cpu_info_table
[i
].name
!= NULL
; i
++)
14115 show (stream
, mips_cpu_info_table
[i
].name
, &column
, &first
);
14116 show (stream
, "from-abi", &column
, &first
);
14117 fputc ('\n', stream
);
14119 fprintf (stream
, _("\
14120 -mCPU equivalent to -march=CPU -mtune=CPU. Deprecated.\n\
14121 -no-mCPU don't generate code specific to CPU.\n\
14122 For -mCPU and -no-mCPU, CPU must be one of:\n"));
14126 show (stream
, "3900", &column
, &first
);
14127 show (stream
, "4010", &column
, &first
);
14128 show (stream
, "4100", &column
, &first
);
14129 show (stream
, "4650", &column
, &first
);
14130 fputc ('\n', stream
);
14132 fprintf (stream
, _("\
14133 -mips16 generate mips16 instructions\n\
14134 -no-mips16 do not generate mips16 instructions\n"));
14135 fprintf (stream
, _("\
14136 -mfix-vr4120 work around certain VR4120 errata\n\
14137 -mgp32 use 32-bit GPRs, regardless of the chosen ISA\n\
14138 -mfp32 use 32-bit FPRs, regardless of the chosen ISA\n\
14139 -O0 remove unneeded NOPs, do not swap branches\n\
14140 -O remove unneeded NOPs and swap branches\n\
14141 --[no-]construct-floats [dis]allow floating point values to be constructed\n\
14142 --trap, --no-break trap exception on div by 0 and mult overflow\n\
14143 --break, --no-trap break exception on div by 0 and mult overflow\n"));
14145 fprintf (stream
, _("\
14146 -KPIC, -call_shared generate SVR4 position independent code\n\
14147 -non_shared do not generate position independent code\n\
14148 -xgot assume a 32 bit GOT\n\
14149 -mpdr, -mno-pdr enable/disable creation of .pdr sections\n\
14150 -mabi=ABI create ABI conformant object file for:\n"));
14154 show (stream
, "32", &column
, &first
);
14155 show (stream
, "o64", &column
, &first
);
14156 show (stream
, "n32", &column
, &first
);
14157 show (stream
, "64", &column
, &first
);
14158 show (stream
, "eabi", &column
, &first
);
14160 fputc ('\n', stream
);
14162 fprintf (stream
, _("\
14163 -32 create o32 ABI object file (default)\n\
14164 -n32 create n32 ABI object file\n\
14165 -64 create 64 ABI object file\n"));
14170 mips_dwarf2_format (void)
14172 if (mips_abi
== N64_ABI
)
14175 return dwarf2_format_64bit_irix
;
14177 return dwarf2_format_64bit
;
14181 return dwarf2_format_32bit
;
14185 mips_dwarf2_addr_size (void)
14187 if (mips_abi
== N64_ABI
)