1 /* tc-mips.c -- assemble code for a MIPS chip.
2 Copyright (C) 1993 Free Software Foundation, Inc.
3 Contributed by the OSF and Ralph Campbell.
4 Written by Keith Knowles and Ralph Campbell, working independently.
5 Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus
8 This file is part of GAS.
10 GAS is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 2, or (at your option)
15 GAS is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with GAS; see the file COPYING. If not, write to
22 the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */
40 #endif /* NO_VARARGS */
41 #endif /* NO_STDARG */
43 #include "opcode/mips.h"
48 static char *mips_regmask_frag
;
52 #define PIC_CALL_REG 25
58 /* Decide whether to do GP reference optimizations based on the object
68 /* The default target format to use. */
70 #ifdef TARGET_BYTES_BIG_ENDIAN
71 #define DEFAULT_TARGET_FORMAT "a.out-mips-big"
73 #define DEFAULT_TARGET_FORMAT "a.out-mips-little"
77 #ifdef TARGET_BYTES_BIG_ENDIAN
78 #define DEFAULT_TARGET_FORMAT "ecoff-bigmips"
80 #define DEFAULT_TARGET_FORMAT "ecoff-littlemips"
82 #endif /* OBJ_ECOFF */
84 #ifdef TARGET_BYTES_BIG_ENDIAN
85 #define DEFAULT_TARGET_FORMAT "elf32-bigmips"
87 #define DEFAULT_TARGET_FORMAT "elf32-littlemips"
91 const char *mips_target_format
= DEFAULT_TARGET_FORMAT
;
93 /* These variables are filled in with the masks of registers used.
94 The object format code reads them and puts them in the appropriate
96 unsigned long mips_gprmask
;
97 unsigned long mips_cprmask
[4];
99 /* MIPS ISA (Instruction Set Architecture) level (may be changed
100 temporarily using .set mipsN). */
101 static int mips_isa
= -1;
103 /* MIPS ISA we are using for this output file. */
104 static int file_mips_isa
;
106 /* MIPS PIC level. */
110 /* Do not generate PIC code. */
113 /* Generate PIC code as in Irix 4. This is not implemented, and I'm
114 not sure what it is supposed to do. */
117 /* Generate PIC code as in the SVR4 MIPS ABI. */
120 /* Generate PIC code without using a global offset table: the data
121 segment has a maximum size of 64K, all data references are off
122 the $gp register, and all text references are PC relative. This
123 is used on some embedded systems. */
127 static enum mips_pic_level mips_pic
;
129 /* 1 if trap instructions should used for overflow rather than break
131 static int mips_trap
;
133 static int mips_warn_about_macros
;
134 static int mips_noreorder
;
135 static int mips_any_noreorder
;
136 static int mips_nomove
;
137 static int mips_noat
;
138 static int mips_nobopt
;
141 /* The size of the small data section. */
142 static int g_switch_value
= 8;
143 /* Whether the -G option was used. */
144 static int g_switch_seen
= 0;
150 /* handle of the OPCODE hash table */
151 static struct hash_control
*op_hash
= NULL
;
153 /* This array holds the chars that always start a comment. If the
154 pre-processor is disabled, these aren't very useful */
155 const char comment_chars
[] = "#";
157 /* This array holds the chars that only start a comment at the beginning of
158 a line. If the line seems to have the form '# 123 filename'
159 .line and .file directives will appear in the pre-processed output */
160 /* Note that input_file.c hand checks for '#' at the beginning of the
161 first line of the input file. This is because the compiler outputs
162 #NO_APP at the beginning of its output. */
163 /* Also note that C style comments are always supported. */
164 const char line_comment_chars
[] = "#";
166 /* This array holds machine specific line separator characters. */
167 const char line_separator_chars
[] = "";
169 /* Chars that can be used to separate mant from exp in floating point nums */
170 const char EXP_CHARS
[] = "eE";
172 /* Chars that mean this number is a floating point constant */
175 const char FLT_CHARS
[] = "rRsSfFdDxXpP";
177 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
178 changed in read.c . Ideally it shouldn't have to know about it at all,
179 but nothing is ideal around here.
182 static char *insn_error
;
184 static int byte_order
= BYTE_ORDER
;
186 static int auto_align
= 1;
188 /* Symbol labelling the current insn. */
189 static symbolS
*insn_label
;
191 /* When outputting SVR4 PIC code, the assembler needs to know the
192 offset in the stack frame from which to restore the $gp register.
193 This is set by the .cprestore pseudo-op, and saved in this
195 static offsetT mips_cprestore_offset
= -1;
197 /* This is the register which holds the stack frame, as set by the
198 .frame pseudo-op. This is needed to implement .cprestore. */
199 static int mips_frame_reg
= SP
;
201 /* To output NOP instructions correctly, we need to keep information
202 about the previous two instructions. */
204 /* Whether we are optimizing. The default value of 2 means to remove
205 unneeded NOPs and swap branch instructions when possible. A value
206 of 1 means to not swap branches. A value of 0 means to always
208 static int mips_optimize
= 2;
210 /* The previous instruction. */
211 static struct mips_cl_insn prev_insn
;
213 /* The instruction before prev_insn. */
214 static struct mips_cl_insn prev_prev_insn
;
216 /* If we don't want information for prev_insn or prev_prev_insn, we
217 point the insn_mo field at this dummy integer. */
218 static const struct mips_opcode dummy_opcode
= { 0 };
220 /* Non-zero if prev_insn is valid. */
221 static int prev_insn_valid
;
223 /* The frag for the previous instruction. */
224 static struct frag
*prev_insn_frag
;
226 /* The offset into prev_insn_frag for the previous instruction. */
227 static long prev_insn_where
;
229 /* The reloc for the previous instruction, if any. */
230 static fixS
*prev_insn_fixp
;
232 /* Non-zero if the previous instruction was in a delay slot. */
233 static int prev_insn_is_delay_slot
;
235 /* Non-zero if the previous instruction was in a .set noreorder. */
236 static int prev_insn_unreordered
;
238 /* Non-zero if the previous previous instruction was in a .set
240 static int prev_prev_insn_unreordered
;
242 /* Since the MIPS does not have multiple forms of PC relative
243 instructions, we do not have to do relaxing as is done on other
244 platforms. However, we do have to handle GP relative addressing
245 correctly, which turns out to be a similar problem.
247 Every macro that refers to a symbol can occur in (at least) two
248 forms, one with GP relative addressing and one without. For
249 example, loading a global variable into a register generally uses
250 a macro instruction like this:
252 If i can be addressed off the GP register (this is true if it is in
253 the .sbss or .sdata section, or if it is known to be smaller than
254 the -G argument) this will generate the following instruction:
256 This instruction will use a GPREL reloc. If i can not be addressed
257 off the GP register, the following instruction sequence will be used:
260 In this case the first instruction will have a HI16 reloc, and the
261 second reloc will have a LO16 reloc. Both relocs will be against
264 The issue here is that we may not know whether i is GP addressable
265 until after we see the instruction that uses it. Therefore, we
266 want to be able to choose the final instruction sequence only at
267 the end of the assembly. This is similar to the way other
268 platforms choose the size of a PC relative instruction only at the
271 When generating position independent code we do not use GP
272 addressing in quite the same way, but the issue still arises as
273 external symbols and local symbols must be handled differently.
275 We handle these issues by actually generating both possible
276 instruction sequences. The longer one is put in a frag_var with
277 type rs_machine_dependent. We encode what to do with the frag in
278 the subtype field. We encode (1) the number of existing bytes to
279 replace, (2) the number of new bytes to use, (3) the offset from
280 the start of the existing bytes to the first reloc we must generate
281 (that is, the offset is applied from the start of the existing
282 bytes after they are replaced by the new bytes, if any), (4) the
283 offset from the start of the existing bytes to the second reloc,
284 (5) whether a third reloc is needed (the third reloc is always four
285 bytes after the second reloc), and (6) whether to warn if this
286 variant is used (this is sometimes needed if .set nomacro or .set
287 noat is in effect). All these numbers are reasonably small.
289 Generating two instruction sequences must be handled carefully to
290 ensure that delay slots are handled correctly. Fortunately, there
291 are a limited number of cases. When the second instruction
292 sequence is generated, append_insn is directed to maintain the
293 existing delay slot information, so it continues to apply to any
294 code after the second instruction sequence. This means that the
295 second instruction sequence must not impose any requirements not
296 required by the first instruction sequence.
298 These variant frags are then handled in functions called by the
299 machine independent code. md_estimate_size_before_relax returns
300 the final size of the frag. md_convert_frag sets up the final form
301 of the frag. tc_gen_reloc adjust the first reloc and adds a second
303 #define RELAX_ENCODE(old, new, reloc1, reloc2, reloc3, warn) \
307 | (((reloc1) + 64) << 9) \
308 | (((reloc2) + 64) << 2) \
309 | ((reloc3) ? (1 << 1) : 0) \
311 #define RELAX_OLD(i) (((i) >> 24) & 0xff)
312 #define RELAX_NEW(i) (((i) >> 16) & 0xff)
313 #define RELAX_RELOC1(i) ((((i) >> 9) & 0x7f) - 64)
314 #define RELAX_RELOC2(i) ((((i) >> 2) & 0x7f) - 64)
315 #define RELAX_RELOC3(i) (((i) >> 1) & 1)
316 #define RELAX_WARN(i) ((i) & 1)
318 /* Prototypes for static functions. */
321 #define internalError() \
322 as_fatal ("internal Error, line %d, %s", __LINE__, __FILE__)
324 #define internalError() as_fatal ("MIPS internal Error");
327 static int insn_uses_reg
PARAMS ((struct mips_cl_insn
*ip
,
328 unsigned int reg
, int fpr
));
329 static void append_insn
PARAMS ((char *place
,
330 struct mips_cl_insn
* ip
,
332 bfd_reloc_code_real_type r
));
333 static void mips_no_prev_insn
PARAMS ((void));
334 static void mips_emit_delays
PARAMS ((void));
335 static void macro_build
PARAMS ((char *place
, int *counter
, expressionS
* ep
,
336 const char *name
, const char *fmt
,
338 static void macro_build_lui
PARAMS ((char *place
, int *counter
,
339 expressionS
* ep
, int regnum
));
340 static void set_at
PARAMS ((int *counter
, int reg
, int unsignedp
));
341 static void check_absolute_expr
PARAMS ((struct mips_cl_insn
* ip
,
343 static void load_register
PARAMS ((int *counter
, int reg
, expressionS
* ep
));
344 static void load_address
PARAMS ((int *counter
, int reg
, expressionS
*ep
));
345 static void macro
PARAMS ((struct mips_cl_insn
* ip
));
346 #ifdef LOSING_COMPILER
347 static void macro2
PARAMS ((struct mips_cl_insn
* ip
));
349 static void mips_ip
PARAMS ((char *str
, struct mips_cl_insn
* ip
));
350 static int my_getSmallExpression
PARAMS ((expressionS
* ep
, char *str
));
351 static void my_getExpression
PARAMS ((expressionS
* ep
, char *str
));
352 static symbolS
*get_symbol
PARAMS ((void));
353 static void mips_align
PARAMS ((int to
, int fill
, symbolS
*label
));
354 static void s_align
PARAMS ((int));
355 static void s_stringer
PARAMS ((int));
356 static void s_change_sec
PARAMS ((int));
357 static void s_cons
PARAMS ((int));
358 static void s_err
PARAMS ((int));
359 static void s_extern
PARAMS ((int));
360 static void s_float_cons
PARAMS ((int));
361 static void s_option
PARAMS ((int));
362 static void s_mipsset
PARAMS ((int));
363 static void s_mips_space
PARAMS ((int));
364 static void s_abicalls
PARAMS ((int));
365 static void s_cpload
PARAMS ((int));
366 static void s_cprestore
PARAMS ((int));
367 static void s_gpword
PARAMS ((int));
368 static void s_cpadd
PARAMS ((int));
369 #ifndef ECOFF_DEBUGGING
370 static void md_obj_begin
PARAMS ((void));
371 static void md_obj_end
PARAMS ((void));
372 static long get_number
PARAMS ((void));
373 static void s_ent
PARAMS ((int));
374 static void s_mipsend
PARAMS ((int));
375 static void s_file
PARAMS ((int));
377 static void s_frame
PARAMS ((int));
378 static void s_loc
PARAMS ((int));
379 static void s_mask
PARAMS ((char));
385 The following pseudo-ops from the Kane and Heinrich MIPS book
386 should be defined here, but are currently unsupported: .alias,
387 .galive, .gjaldef, .gjrlive, .livereg, .noalias.
389 The following pseudo-ops from the Kane and Heinrich MIPS book are
390 specific to the type of debugging information being generated, and
391 should be defined by the object format: .aent, .begin, .bend,
392 .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp,
395 The following pseudo-ops from the Kane and Heinrich MIPS book are
396 not MIPS CPU specific, but are also not specific to the object file
397 format. This file is probably the best place to define them, but
398 they are not currently supported: .asm0, .endr, .lab, .repeat,
399 .struct, .weakext. */
401 const pseudo_typeS md_pseudo_table
[] =
403 /* MIPS specific pseudo-ops. */
404 {"option", s_option
, 0},
405 {"set", s_mipsset
, 0},
406 {"rdata", s_change_sec
, 'r'},
407 {"sdata", s_change_sec
, 's'},
408 {"livereg", s_ignore
, 0},
409 { "abicalls", s_abicalls
, 0},
410 { "cpload", s_cpload
, 0},
411 { "cprestore", s_cprestore
, 0},
412 { "gpword", s_gpword
, 0},
413 { "cpadd", s_cpadd
, 0},
415 /* Relatively generic pseudo-ops that happen to be used on MIPS
417 {"asciiz", s_stringer
, 1},
418 {"bss", s_change_sec
, 'b'},
421 {"dword", s_cons
, 3},
423 /* These pseudo-ops are defined in read.c, but must be overridden
424 here for one reason or another. */
425 {"align", s_align
, 0},
426 {"ascii", s_stringer
, 0},
427 {"asciz", s_stringer
, 1},
429 {"data", s_change_sec
, 'd'},
430 {"double", s_float_cons
, 'd'},
431 {"extern", s_extern
, 0},
432 {"float", s_float_cons
, 'f'},
433 {"hword", s_cons
, 1},
438 {"short", s_cons
, 1},
439 {"single", s_float_cons
, 'f'},
440 {"space", s_mips_space
, 0},
441 {"text", s_change_sec
, 't'},
444 #ifndef ECOFF_DEBUGGING
445 /* These pseudo-ops should be defined by the object file format.
446 However, a.out doesn't support them, so we have versions here. */
448 {"bgnb", s_ignore
, 0},
449 {"end", s_mipsend
, 0},
450 {"endb", s_ignore
, 0},
453 {"fmask", s_ignore
, 'F'},
454 {"frame", s_ignore
, 0},
455 {"loc", s_ignore
, 0},
456 {"mask", s_ignore
, 'R'},
457 {"verstamp", s_ignore
, 0},
464 const relax_typeS md_relax_table
[] =
469 static char *expr_end
;
471 static expressionS imm_expr
;
472 static expressionS offset_expr
;
473 static bfd_reloc_code_real_type imm_reloc
;
474 static bfd_reloc_code_real_type offset_reloc
;
476 /* FIXME: This should be handled in a different way. */
477 extern int target_big_endian
;
480 * This function is called once, at assembler startup time. It should
481 * set up all the tables, etc. that the MD part of the assembler will need.
487 register const char *retval
= NULL
;
488 register unsigned int i
= 0;
492 if (strcmp (TARGET_CPU
, "mips") == 0)
494 else if (strcmp (TARGET_CPU
, "r6000") == 0
495 || strcmp (TARGET_CPU
, "mips2") == 0)
497 else if (strcmp (TARGET_CPU
, "mips64") == 0
498 || strcmp (TARGET_CPU
, "r4000") == 0
499 || strcmp (TARGET_CPU
, "mips3") == 0)
505 if (mips_isa
< 2 && mips_trap
)
506 as_bad ("trap exception not supported at ISA 1");
511 ok
= bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, 3000);
514 ok
= bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, 6000);
517 ok
= bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, 4000);
521 as_warn ("Could not set architecture and machine");
523 file_mips_isa
= mips_isa
;
525 op_hash
= hash_new ();
527 for (i
= 0; i
< NUMOPCODES
;)
529 const char *name
= mips_opcodes
[i
].name
;
531 retval
= hash_insert (op_hash
, name
, (PTR
) &mips_opcodes
[i
]);
534 fprintf (stderr
, "internal error: can't hash `%s': %s\n",
535 mips_opcodes
[i
].name
, retval
);
536 as_fatal ("Broken assembler. No assembly attempted.");
540 if (mips_opcodes
[i
].pinfo
!= INSN_MACRO
541 && ((mips_opcodes
[i
].match
& mips_opcodes
[i
].mask
)
542 != mips_opcodes
[i
].match
))
544 fprintf (stderr
, "internal error: bad opcode: `%s' \"%s\"\n",
545 mips_opcodes
[i
].name
, mips_opcodes
[i
].args
);
546 as_fatal ("Broken assembler. No assembly attempted.");
550 while ((i
< NUMOPCODES
) && !strcmp (mips_opcodes
[i
].name
, name
));
553 mips_no_prev_insn ();
561 /* set the default alignment for the text section (2**2) */
562 record_alignment (text_section
, 2);
564 /* FIXME: This should be handled in a different way. */
565 target_big_endian
= byte_order
== BIG_ENDIAN
;
568 bfd_set_gp_size (stdoutput
, g_switch_value
);
572 /* Sections must be aligned to 16 byte boundaries. */
573 (void) bfd_set_section_alignment (stdoutput
, text_section
, 4);
574 (void) bfd_set_section_alignment (stdoutput
, data_section
, 4);
575 (void) bfd_set_section_alignment (stdoutput
, bss_section
, 4);
577 /* Create a .reginfo section for register masks and a .mdebug
578 section for debugging information. */
586 sec
= subseg_new (".reginfo", (subsegT
) 0);
588 /* The ABI says this section should be loaded so that the running
589 program can access it. */
590 (void) bfd_set_section_flags (stdoutput
, sec
,
591 (SEC_ALLOC
| SEC_LOAD
592 | SEC_READONLY
| SEC_DATA
));
593 (void) bfd_set_section_alignment (stdoutput
, sec
, 2);
595 mips_regmask_frag
= frag_more (sizeof (Elf32_External_RegInfo
));
597 #ifdef ECOFF_DEBUGGING
598 sec
= subseg_new (".mdebug", (subsegT
) 0);
599 (void) bfd_set_section_flags (stdoutput
, sec
,
600 SEC_HAS_CONTENTS
| SEC_READONLY
);
601 (void) bfd_set_section_alignment (stdoutput
, sec
, 2);
604 subseg_set (seg
, subseg
);
608 #ifndef ECOFF_DEBUGGING
616 #ifndef ECOFF_DEBUGGING
625 struct mips_cl_insn insn
;
627 imm_expr
.X_op
= O_absent
;
628 offset_expr
.X_op
= O_absent
;
630 mips_ip (str
, &insn
);
633 as_bad ("%s `%s'", insn_error
, str
);
636 if (insn
.insn_mo
->pinfo
== INSN_MACRO
)
642 if (imm_expr
.X_op
!= O_absent
)
643 append_insn ((char *) NULL
, &insn
, &imm_expr
, imm_reloc
);
644 else if (offset_expr
.X_op
!= O_absent
)
645 append_insn ((char *) NULL
, &insn
, &offset_expr
, offset_reloc
);
647 append_insn ((char *) NULL
, &insn
, NULL
, BFD_RELOC_UNUSED
);
651 /* See whether instruction IP reads register REG. If FPR is non-zero,
652 REG is a floating point register. */
655 insn_uses_reg (ip
, reg
, fpr
)
656 struct mips_cl_insn
*ip
;
660 /* Don't report on general register 0, since it never changes. */
661 if (! fpr
&& reg
== 0)
666 /* If we are called with either $f0 or $f1, we must check $f0.
667 This is not optimal, because it will introduce an unnecessary
668 NOP between "lwc1 $f0" and "swc1 $f1". To fix this we would
669 need to distinguish reading both $f0 and $f1 or just one of
670 them. Note that we don't have to check the other way,
671 because there is no instruction that sets both $f0 and $f1
672 and requires a delay. */
673 if ((ip
->insn_mo
->pinfo
& INSN_READ_FPR_S
)
674 && (((ip
->insn_opcode
>> OP_SH_FS
) & OP_MASK_FS
)
675 == (reg
&~ (unsigned) 1)))
677 if ((ip
->insn_mo
->pinfo
& INSN_READ_FPR_T
)
678 && (((ip
->insn_opcode
>> OP_SH_FT
) & OP_MASK_FT
)
679 == (reg
&~ (unsigned) 1)))
684 if ((ip
->insn_mo
->pinfo
& INSN_READ_GPR_S
)
685 && ((ip
->insn_opcode
>> OP_SH_RS
) & OP_MASK_RS
) == reg
)
687 if ((ip
->insn_mo
->pinfo
& INSN_READ_GPR_T
)
688 && ((ip
->insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
) == reg
)
695 /* Output an instruction. PLACE is where to put the instruction; if
696 it is NULL, this uses frag_more to get room. IP is the instruction
697 information. ADDRESS_EXPR is an operand of the instruction to be
698 used with RELOC_TYPE. */
701 append_insn (place
, ip
, address_expr
, reloc_type
)
703 struct mips_cl_insn
*ip
;
704 expressionS
*address_expr
;
705 bfd_reloc_code_real_type reloc_type
;
707 register unsigned long prev_pinfo
, pinfo
;
712 prev_pinfo
= prev_insn
.insn_mo
->pinfo
;
713 pinfo
= ip
->insn_mo
->pinfo
;
715 if (place
== NULL
&& ! mips_noreorder
)
717 /* If the previous insn required any delay slots, see if we need
718 to insert a NOP or two. There are eight kinds of possible
719 hazards, of which an instruction can have at most one type.
720 (1) a load from memory delay
721 (2) a load from a coprocessor delay
722 (3) an unconditional branch delay
723 (4) a conditional branch delay
724 (5) a move to coprocessor register delay
725 (6) a load coprocessor register from memory delay
726 (7) a coprocessor condition code delay
727 (8) a HI/LO special register delay
729 There are a lot of optimizations we could do that we don't.
730 In particular, we do not, in general, reorder instructions.
731 If you use gcc with optimization, it will reorder
732 instructions and generally do much more optimization then we
733 do here; repeating all that work in the assembler would only
734 benefit hand written assembly code, and does not seem worth
737 /* This is how a NOP is emitted. */
738 #define emit_nop() md_number_to_chars (frag_more (4), 0, 4)
740 /* The previous insn might require a delay slot, depending upon
741 the contents of the current insn. */
742 if ((prev_pinfo
& INSN_LOAD_COPROC_DELAY
)
744 && (prev_pinfo
& INSN_LOAD_MEMORY_DELAY
)))
746 /* A load from a coprocessor or from memory. All load
747 delays delay the use of general register rt for one
748 instruction on the r3000. The r6000 and r4000 use
750 know (prev_pinfo
& INSN_WRITE_GPR_T
);
751 if (mips_optimize
== 0
752 || insn_uses_reg (ip
,
753 ((prev_insn
.insn_opcode
>> OP_SH_RT
)
758 else if ((prev_pinfo
& INSN_COPROC_MOVE_DELAY
)
760 && (prev_pinfo
& INSN_COPROC_MEMORY_DELAY
)))
762 /* A generic coprocessor delay. The previous instruction
763 modified a coprocessor general or control register. If
764 it modified a control register, we need to avoid any
765 coprocessor instruction (this is probably not always
766 required, but it sometimes is). If it modified a general
767 register, we avoid using that register.
769 On the r6000 and r4000 loading a coprocessor register
770 from memory is interlocked, and does not require a delay.
772 This case is not handled very well. There is no special
773 knowledge of CP0 handling, and the coprocessors other
774 than the floating point unit are not distinguished at
776 if (prev_pinfo
& INSN_WRITE_FPR_T
)
778 if (mips_optimize
== 0
779 || insn_uses_reg (ip
,
780 ((prev_insn
.insn_opcode
>> OP_SH_FT
)
785 else if (prev_pinfo
& INSN_WRITE_FPR_S
)
787 if (mips_optimize
== 0
788 || insn_uses_reg (ip
,
789 ((prev_insn
.insn_opcode
>> OP_SH_FS
)
796 /* We don't know exactly what the previous instruction
797 does. If the current instruction uses a coprocessor
798 register, we must insert a NOP. If previous
799 instruction may set the condition codes, and the
800 current instruction uses them, we must insert two
802 if (mips_optimize
== 0
803 || ((prev_pinfo
& INSN_WRITE_COND_CODE
)
804 && (pinfo
& INSN_READ_COND_CODE
)))
806 else if (pinfo
& INSN_COP
)
810 else if (prev_pinfo
& INSN_WRITE_COND_CODE
)
812 /* The previous instruction sets the coprocessor condition
813 codes, but does not require a general coprocessor delay
814 (this means it is a floating point comparison
815 instruction). If this instruction uses the condition
816 codes, we need to insert a single NOP. */
817 if (mips_optimize
== 0
818 || (pinfo
& INSN_READ_COND_CODE
))
821 else if (prev_pinfo
& INSN_READ_LO
)
823 /* The previous instruction reads the LO register; if the
824 current instruction writes to the LO register, we must
826 if (mips_optimize
== 0
827 || (pinfo
& INSN_WRITE_LO
))
830 else if (prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
832 /* The previous instruction reads the HI register; if the
833 current instruction writes to the HI register, we must
835 if (mips_optimize
== 0
836 || (pinfo
& INSN_WRITE_HI
))
840 /* There are two cases which require two intervening
841 instructions: 1) setting the condition codes using a move to
842 coprocessor instruction which requires a general coprocessor
843 delay and then reading the condition codes 2) reading the HI
844 or LO register and then writing to it. If we are not already
845 emitting a NOP instruction, we must check for these cases
846 compared to the instruction previous to the previous
849 && (((prev_prev_insn
.insn_mo
->pinfo
& INSN_COPROC_MOVE_DELAY
)
850 && (prev_prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
)
851 && (pinfo
& INSN_READ_COND_CODE
))
852 || ((prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
)
853 && (pinfo
& INSN_WRITE_LO
))
854 || ((prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
855 && (pinfo
& INSN_WRITE_HI
))))
858 /* If we are being given a nop instruction, don't bother with
859 one of the nops we would otherwise output. This will only
860 happen when a nop instruction is used with mips_optimize set
862 if (nops
> 0 && ip
->insn_opcode
== 0)
865 /* Now emit the right number of NOP instructions. */
872 listing_prev_line ();
873 if (insn_label
!= NULL
)
875 assert (S_GET_SEGMENT (insn_label
) == now_seg
);
876 insn_label
->sy_frag
= frag_now
;
877 S_SET_VALUE (insn_label
, (valueT
) frag_now_fix ());
887 if (address_expr
!= NULL
)
889 if (address_expr
->X_op
== O_constant
)
894 ip
->insn_opcode
|= address_expr
->X_add_number
;
898 ip
->insn_opcode
|= address_expr
->X_add_number
& 0xffff;
901 case BFD_RELOC_MIPS_JMP
:
902 case BFD_RELOC_16_PCREL_S2
:
911 assert (reloc_type
!= BFD_RELOC_UNUSED
);
913 /* Don't generate a reloc if we are writing into a variant
916 fixp
= fix_new_exp (frag_now
, f
- frag_now
->fr_literal
, 4,
918 reloc_type
== BFD_RELOC_16_PCREL_S2
,
923 md_number_to_chars (f
, ip
->insn_opcode
, 4);
925 /* Update the register mask information. */
926 if (pinfo
& INSN_WRITE_GPR_D
)
927 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
);
928 if ((pinfo
& (INSN_WRITE_GPR_T
| INSN_READ_GPR_T
)) != 0)
929 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
);
930 if (pinfo
& INSN_READ_GPR_S
)
931 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> OP_SH_RS
) & OP_MASK_RS
);
932 if (pinfo
& INSN_WRITE_GPR_31
)
933 mips_gprmask
|= 1 << 31;
934 if (pinfo
& INSN_WRITE_FPR_D
)
935 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FD
) & OP_MASK_FD
);
936 if ((pinfo
& (INSN_WRITE_FPR_S
| INSN_READ_FPR_S
)) != 0)
937 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FS
) & OP_MASK_FS
);
938 if ((pinfo
& (INSN_WRITE_FPR_T
| INSN_READ_FPR_T
)) != 0)
939 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FT
) & OP_MASK_FT
);
940 if (pinfo
& INSN_COP
)
942 /* We don't keep enough information to sort these cases out. */
944 /* Never set the bit for $0, which is always zero. */
945 mips_gprmask
&=~ 1 << 0;
947 if (place
== NULL
&& ! mips_noreorder
)
949 /* Filling the branch delay slot is more complex. We try to
950 switch the branch with the previous instruction, which we can
951 do if the previous instruction does not set up a condition
952 that the branch tests and if the branch is not itself the
953 target of any branch. */
954 if ((pinfo
& INSN_UNCOND_BRANCH_DELAY
)
955 || (pinfo
& INSN_COND_BRANCH_DELAY
))
957 if (mips_optimize
< 2
958 /* If we have seen .set volatile or .set nomove, don't
961 /* If we had to emit any NOP instructions, then we
962 already know we can not swap. */
964 /* If we don't even know the previous insn, we can not
967 /* If the previous insn is already in a branch delay
968 slot, then we can not swap. */
969 || prev_insn_is_delay_slot
970 /* If the previous previous insn was in a .set
971 noreorder, we can't swap. Actually, the MIPS
972 assembler will swap in this situation. However, gcc
973 configured -with-gnu-as will generate code like
979 in which we can not swap the bne and INSN. If gcc is
980 not configured -with-gnu-as, it does not output the
981 .set pseudo-ops. We don't have to check
982 prev_insn_unreordered, because prev_insn_valid will
983 be 0 in that case. We don't want to use
984 prev_prev_insn_valid, because we do want to be able
985 to swap at the start of a function. */
986 || prev_prev_insn_unreordered
987 /* If the branch is itself the target of a branch, we
988 can not swap. We cheat on this; all we check for is
989 whether there is a label on this instruction. If
990 there are any branches to anything other than a
991 label, users must use .set noreorder. */
992 || insn_label
!= NULL
993 /* If the previous instruction is in a variant frag, we
994 can not do the swap. */
995 || prev_insn_frag
->fr_type
== rs_machine_dependent
996 /* If the branch reads the condition codes, we don't
997 even try to swap, because in the sequence
1002 we can not swap, and I don't feel like handling that
1004 || (pinfo
& INSN_READ_COND_CODE
)
1005 /* We can not swap with an instruction that requires a
1006 delay slot, becase the target of the branch might
1007 interfere with that instruction. */
1009 & (INSN_LOAD_COPROC_DELAY
1010 | INSN_COPROC_MOVE_DELAY
1011 | INSN_WRITE_COND_CODE
1016 & (INSN_LOAD_MEMORY_DELAY
1017 | INSN_COPROC_MEMORY_DELAY
)))
1018 /* We can not swap with a branch instruction. */
1020 & (INSN_UNCOND_BRANCH_DELAY
1021 | INSN_COND_BRANCH_DELAY
1022 | INSN_COND_BRANCH_LIKELY
))
1023 /* We do not swap with a trap instruction, since it
1024 complicates trap handlers to have the trap
1025 instruction be in a delay slot. */
1026 || (prev_pinfo
& INSN_TRAP
)
1027 /* If the branch reads a register that the previous
1028 instruction sets, we can not swap. */
1029 || ((prev_pinfo
& INSN_WRITE_GPR_T
)
1030 && insn_uses_reg (ip
,
1031 ((prev_insn
.insn_opcode
>> OP_SH_RT
)
1034 || ((prev_pinfo
& INSN_WRITE_GPR_D
)
1035 && insn_uses_reg (ip
,
1036 ((prev_insn
.insn_opcode
>> OP_SH_RD
)
1039 /* If the branch writes a register that the previous
1040 instruction sets, we can not swap (we know that
1041 branches write only to RD or to $31). */
1042 || ((prev_pinfo
& INSN_WRITE_GPR_T
)
1043 && (((pinfo
& INSN_WRITE_GPR_D
)
1044 && (((prev_insn
.insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
)
1045 == ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)))
1046 || ((pinfo
& INSN_WRITE_GPR_31
)
1047 && (((prev_insn
.insn_opcode
>> OP_SH_RT
)
1050 || ((prev_pinfo
& INSN_WRITE_GPR_D
)
1051 && (((pinfo
& INSN_WRITE_GPR_D
)
1052 && (((prev_insn
.insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)
1053 == ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)))
1054 || ((pinfo
& INSN_WRITE_GPR_31
)
1055 && (((prev_insn
.insn_opcode
>> OP_SH_RD
)
1058 /* If the branch writes a register that the previous
1059 instruction reads, we can not swap (we know that
1060 branches only write to RD or to $31). */
1061 || ((pinfo
& INSN_WRITE_GPR_D
)
1062 && insn_uses_reg (&prev_insn
,
1063 ((ip
->insn_opcode
>> OP_SH_RD
)
1066 || ((pinfo
& INSN_WRITE_GPR_31
)
1067 && insn_uses_reg (&prev_insn
, 31, 0))
1068 /* If we are generating embedded PIC code, the branch
1069 might be expanded into a sequence which uses $at, so
1070 we can't swap with an instruction which reads it. */
1071 || (mips_pic
== EMBEDDED_PIC
1072 && insn_uses_reg (&prev_insn
, AT
, 0))
1073 /* If the previous previous instruction has a load
1074 delay, and sets a register that the branch reads, we
1076 || (((prev_prev_insn
.insn_mo
->pinfo
& INSN_LOAD_COPROC_DELAY
)
1078 && (prev_prev_insn
.insn_mo
->pinfo
1079 & INSN_LOAD_MEMORY_DELAY
)))
1080 && insn_uses_reg (ip
,
1081 ((prev_prev_insn
.insn_opcode
>> OP_SH_RT
)
1085 /* We could do even better for unconditional branches to
1086 portions of this object file; we could pick up the
1087 instruction at the destination, put it in the delay
1088 slot, and bump the destination address. */
1090 /* Update the previous insn information. */
1091 prev_prev_insn
= *ip
;
1092 prev_insn
.insn_mo
= &dummy_opcode
;
1099 /* It looks like we can actually do the swap. */
1100 prev_f
= prev_insn_frag
->fr_literal
+ prev_insn_where
;
1101 memcpy (temp
, prev_f
, 4);
1102 memcpy (prev_f
, f
, 4);
1103 memcpy (f
, temp
, 4);
1106 prev_insn_fixp
->fx_frag
= frag_now
;
1107 prev_insn_fixp
->fx_where
= f
- frag_now
->fr_literal
;
1111 fixp
->fx_frag
= prev_insn_frag
;
1112 fixp
->fx_where
= prev_insn_where
;
1114 /* Update the previous insn information; leave prev_insn
1116 prev_prev_insn
= *ip
;
1118 prev_insn_is_delay_slot
= 1;
1120 /* If that was an unconditional branch, forget the previous
1121 insn information. */
1122 if (pinfo
& INSN_UNCOND_BRANCH_DELAY
)
1124 prev_prev_insn
.insn_mo
= &dummy_opcode
;
1125 prev_insn
.insn_mo
= &dummy_opcode
;
1128 else if (pinfo
& INSN_COND_BRANCH_LIKELY
)
1130 /* We don't yet optimize a branch likely. What we should do
1131 is look at the target, copy the instruction found there
1132 into the delay slot, and increment the branch to jump to
1133 the next instruction. */
1135 /* Update the previous insn information. */
1136 prev_prev_insn
= *ip
;
1137 prev_insn
.insn_mo
= &dummy_opcode
;
1141 /* Update the previous insn information. */
1143 prev_prev_insn
.insn_mo
= &dummy_opcode
;
1145 prev_prev_insn
= prev_insn
;
1148 /* Any time we see a branch, we always fill the delay slot
1149 immediately; since this insn is not a branch, we know it
1150 is not in a delay slot. */
1151 prev_insn_is_delay_slot
= 0;
1154 prev_prev_insn_unreordered
= prev_insn_unreordered
;
1155 prev_insn_unreordered
= 0;
1156 prev_insn_frag
= frag_now
;
1157 prev_insn_where
= f
- frag_now
->fr_literal
;
1158 prev_insn_fixp
= fixp
;
1159 prev_insn_valid
= 1;
1162 /* We just output an insn, so the next one doesn't have a label. */
1166 /* This function forgets that there was any previous instruction or
1170 mips_no_prev_insn ()
1172 prev_insn
.insn_mo
= &dummy_opcode
;
1173 prev_prev_insn
.insn_mo
= &dummy_opcode
;
1174 prev_insn_valid
= 0;
1175 prev_insn_is_delay_slot
= 0;
1176 prev_insn_unreordered
= 0;
1177 prev_prev_insn_unreordered
= 0;
1181 /* This function must be called whenever we turn on noreorder or emit
1182 something other than instructions. It inserts any NOPS which might
1183 be needed by the previous instruction, and clears the information
1184 kept for the previous instructions. */
1189 if (! mips_noreorder
)
1194 if ((prev_insn
.insn_mo
->pinfo
1195 & (INSN_LOAD_COPROC_DELAY
1196 | INSN_COPROC_MOVE_DELAY
1197 | INSN_WRITE_COND_CODE
1201 && (prev_insn
.insn_mo
->pinfo
1202 & (INSN_LOAD_MEMORY_DELAY
1203 | INSN_COPROC_MEMORY_DELAY
))))
1206 if ((prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
)
1207 || (prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
1208 || (prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
))
1211 else if ((prev_prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
)
1212 || (prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
1213 || (prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
))
1218 if (insn_label
!= NULL
)
1220 assert (S_GET_SEGMENT (insn_label
) == now_seg
);
1221 insn_label
->sy_frag
= frag_now
;
1222 S_SET_VALUE (insn_label
, (valueT
) frag_now_fix ());
1225 mips_no_prev_insn ();
1229 /* Build an instruction created by a macro expansion. This is passed
1230 a pointer to the count of instructions created so far, an
1231 expression, the name of the instruction to build, an operand format
1232 string, and corresponding arguments. */
1236 macro_build (char *place
,
1242 #else /* ! defined (NO_STDARG) */
1244 macro_build (place
, counter
, ep
, name
, fmt
, va_alist
)
1251 #endif /* ! defined (NO_STDARG) */
1253 struct mips_cl_insn insn
;
1254 bfd_reloc_code_real_type r
;
1258 va_start (args
, fmt
);
1264 * If the macro is about to expand into a second instruction,
1265 * print a warning if needed. We need to pass ip as a parameter
1266 * to generate a better warning message here...
1268 if (mips_warn_about_macros
&& place
== NULL
&& *counter
== 1)
1269 as_warn ("Macro instruction expanded into multiple instructions");
1272 *counter
+= 1; /* bump instruction counter */
1274 r
= BFD_RELOC_UNUSED
;
1275 insn
.insn_mo
= (struct mips_opcode
*) hash_find (op_hash
, name
);
1276 assert (insn
.insn_mo
);
1277 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
1279 while (strcmp (fmt
, insn
.insn_mo
->args
) != 0
1280 || insn
.insn_mo
->pinfo
== INSN_MACRO
)
1283 assert (insn
.insn_mo
->name
);
1284 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
1286 insn
.insn_opcode
= insn
.insn_mo
->match
;
1302 insn
.insn_opcode
|= va_arg (args
, int) << 16;
1308 insn
.insn_opcode
|= va_arg (args
, int) << 16;
1313 insn
.insn_opcode
|= va_arg (args
, int) << 11;
1318 insn
.insn_opcode
|= va_arg (args
, int) << 11;
1325 insn
.insn_opcode
|= va_arg (args
, int) << 6;
1329 insn
.insn_opcode
|= va_arg (args
, int) << 6;
1333 insn
.insn_opcode
|= va_arg (args
, int) << 6;
1340 insn
.insn_opcode
|= va_arg (args
, int) << 21;
1346 r
= (bfd_reloc_code_real_type
) va_arg (args
, int);
1347 assert (r
== BFD_RELOC_MIPS_GPREL
1348 || r
== BFD_RELOC_MIPS_LITERAL
1349 || r
== BFD_RELOC_LO16
1350 || r
== BFD_RELOC_MIPS_GOT16
1351 || r
== BFD_RELOC_MIPS_CALL16
1352 || (ep
->X_op
== O_subtract
1353 && now_seg
== text_section
1354 && S_GET_SEGMENT (ep
->X_op_symbol
) == text_section
1355 && r
== BFD_RELOC_PCREL_LO16
));
1359 r
= (bfd_reloc_code_real_type
) va_arg (args
, int);
1361 && (ep
->X_op
== O_constant
1362 || (ep
->X_op
== O_symbol
1363 && (r
== BFD_RELOC_HI16_S
1364 || r
== BFD_RELOC_HI16
))
1365 || (ep
->X_op
== O_subtract
1366 && now_seg
== text_section
1367 && S_GET_SEGMENT (ep
->X_op_symbol
) == text_section
1368 && r
== BFD_RELOC_PCREL_HI16_S
)));
1369 if (ep
->X_op
== O_constant
)
1371 insn
.insn_opcode
|= (ep
->X_add_number
>> 16) & 0xffff;
1373 r
= BFD_RELOC_UNUSED
;
1378 assert (ep
!= NULL
);
1380 * This allows macro() to pass an immediate expression for
1381 * creating short branches without creating a symbol.
1382 * Note that the expression still might come from the assembly
1383 * input, in which case the value is not checked for range nor
1384 * is a relocation entry generated (yuck).
1386 if (ep
->X_op
== O_constant
)
1388 insn
.insn_opcode
|= (ep
->X_add_number
>> 2) & 0xffff;
1392 r
= BFD_RELOC_16_PCREL_S2
;
1396 assert (ep
!= NULL
);
1397 r
= BFD_RELOC_MIPS_JMP
;
1406 assert (r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
1408 append_insn (place
, &insn
, ep
, r
);
1412 * Generate a "lui" instruction.
1415 macro_build_lui (place
, counter
, ep
, regnum
)
1421 expressionS high_expr
;
1422 struct mips_cl_insn insn
;
1423 bfd_reloc_code_real_type r
;
1424 CONST
char *name
= "lui";
1425 CONST
char *fmt
= "t,u";
1431 high_expr
.X_op
= O_constant
;
1432 high_expr
.X_add_number
= 0;
1435 if (high_expr
.X_op
== O_constant
)
1437 /* we can compute the instruction now without a relocation entry */
1438 if (high_expr
.X_add_number
& 0x8000)
1439 high_expr
.X_add_number
+= 0x10000;
1440 high_expr
.X_add_number
=
1441 ((unsigned long) high_expr
.X_add_number
>> 16) & 0xffff;
1442 r
= BFD_RELOC_UNUSED
;
1446 assert (ep
->X_op
== O_symbol
);
1447 /* _gp_disp is a special case, used from s_cpload. */
1448 assert (mips_pic
== NO_PIC
1449 || strcmp (S_GET_NAME (ep
->X_add_symbol
), "_gp_disp") == 0);
1450 r
= BFD_RELOC_HI16_S
;
1454 * If the macro is about to expand into a second instruction,
1455 * print a warning if needed. We need to pass ip as a parameter
1456 * to generate a better warning message here...
1458 if (mips_warn_about_macros
&& place
== NULL
&& *counter
== 1)
1459 as_warn ("Macro instruction expanded into multiple instructions");
1462 *counter
+= 1; /* bump instruction counter */
1464 insn
.insn_mo
= (struct mips_opcode
*) hash_find (op_hash
, name
);
1465 assert (insn
.insn_mo
);
1466 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
1467 assert (strcmp (fmt
, insn
.insn_mo
->args
) == 0);
1469 insn
.insn_opcode
= insn
.insn_mo
->match
| (regnum
<< OP_SH_RT
);
1470 if (r
== BFD_RELOC_UNUSED
)
1472 insn
.insn_opcode
|= high_expr
.X_add_number
;
1473 append_insn (place
, &insn
, NULL
, r
);
1476 append_insn (place
, &insn
, &high_expr
, r
);
1480 * Generates code to set the $at register to true (one)
1481 * if reg is less than the immediate expression.
1484 set_at (counter
, reg
, unsignedp
)
1489 if (imm_expr
.X_add_number
>= -0x8000 && imm_expr
.X_add_number
< 0x8000)
1490 macro_build ((char *) NULL
, counter
, &imm_expr
,
1491 unsignedp
? "sltiu" : "slti",
1492 "t,r,j", AT
, reg
, (int) BFD_RELOC_LO16
);
1495 load_register (counter
, AT
, &imm_expr
);
1496 macro_build ((char *) NULL
, counter
, NULL
,
1497 unsignedp
? "sltu" : "slt",
1498 "d,v,t", AT
, reg
, AT
);
1502 /* Warn if an expression is not a constant. */
1505 check_absolute_expr (ip
, ex
)
1506 struct mips_cl_insn
*ip
;
1509 if (ex
->X_op
!= O_constant
)
1510 as_warn ("Instruction %s requires absolute expression", ip
->insn_mo
->name
);
1514 * This routine generates the least number of instructions neccessary to load
1515 * an absolute expression value into a register.
1518 load_register (counter
, reg
, ep
)
1523 assert (ep
->X_op
== O_constant
);
1524 if (ep
->X_add_number
>= -0x8000 && ep
->X_add_number
< 0x8000)
1525 macro_build ((char *) NULL
, counter
, ep
,
1526 mips_isa
< 3 ? "addiu" : "daddiu",
1527 "t,r,j", reg
, 0, (int) BFD_RELOC_LO16
);
1528 else if (ep
->X_add_number
>= 0 && ep
->X_add_number
< 0x10000)
1529 macro_build ((char *) NULL
, counter
, ep
, "ori", "t,r,i", reg
, 0,
1530 (int) BFD_RELOC_LO16
);
1531 else if ((ep
->X_add_number
&~ (offsetT
) 0x7fffffff) == 0
1532 || ((ep
->X_add_number
&~ (offsetT
) 0x7fffffff)
1533 == ~ (offsetT
) 0x7fffffff))
1535 macro_build ((char *) NULL
, counter
, ep
, "lui", "t,u", reg
,
1536 (int) BFD_RELOC_HI16
);
1537 if ((ep
->X_add_number
& 0xffff) != 0)
1538 macro_build ((char *) NULL
, counter
, ep
, "ori", "t,r,i", reg
, reg
,
1539 (int) BFD_RELOC_LO16
);
1541 else if (mips_isa
< 3)
1543 as_bad ("Number larger than 32 bits");
1544 macro_build ((char *) NULL
, counter
, ep
, "addiu", "t,r,j", reg
, 0,
1545 (int) BFD_RELOC_LO16
);
1550 expressionS hi32
, lo32
;
1554 hi32
.X_add_number
>>= shift
;
1555 hi32
.X_add_number
&= 0xffffffff;
1556 if ((hi32
.X_add_number
& 0x80000000) != 0)
1557 hi32
.X_add_number
|= ~ (offsetT
) 0xffffffff;
1558 load_register (counter
, reg
, &hi32
);
1560 lo32
.X_add_number
&= 0xffffffff;
1561 if ((lo32
.X_add_number
& 0xffff0000) == 0)
1562 macro_build ((char *) NULL
, counter
, NULL
, "dsll32", "d,w,<", reg
,
1568 macro_build ((char *) NULL
, counter
, NULL
, "dsll", "d,w,<", reg
,
1571 mid16
.X_add_number
>>= 16;
1572 macro_build ((char *) NULL
, counter
, &mid16
, "ori", "t,r,i", reg
,
1573 reg
, (int) BFD_RELOC_LO16
);
1574 macro_build ((char *) NULL
, counter
, NULL
, "dsll", "d,w,<", reg
,
1577 if ((lo32
.X_add_number
& 0xffff) != 0)
1578 macro_build ((char *) NULL
, counter
, &lo32
, "ori", "t,r,i", reg
, reg
,
1579 (int) BFD_RELOC_LO16
);
1583 /* Load an address into a register. */
1586 load_address (counter
, reg
, ep
)
1593 if (ep
->X_op
!= O_constant
1594 && ep
->X_op
!= O_symbol
)
1596 as_bad ("expression too complex");
1597 ep
->X_op
= O_constant
;
1600 if (ep
->X_op
== O_constant
)
1602 load_register (counter
, reg
, ep
);
1606 if (mips_pic
== NO_PIC
)
1608 /* If this is a reference to a GP relative symbol, we want
1609 addiu $reg,$gp,<sym> (BFD_RELOC_MIPS_GPREL)
1611 lui $reg,<sym> (BFD_RELOC_HI16_S)
1612 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
1613 If we have an addend, we always use the latter form. */
1614 if (ep
->X_add_number
!= 0)
1619 macro_build ((char *) NULL
, counter
, ep
,
1620 mips_isa
< 3 ? "addiu" : "daddiu",
1621 "t,r,j", reg
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
1622 p
= frag_var (rs_machine_dependent
, 8, 0,
1623 RELAX_ENCODE (4, 8, -4, 0, 0, mips_warn_about_macros
),
1624 ep
->X_add_symbol
, (long) 0, (char *) NULL
);
1626 macro_build_lui (p
, counter
, ep
, reg
);
1629 macro_build (p
, counter
, ep
,
1630 mips_isa
< 3 ? "addiu" : "daddiu",
1631 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
1633 else if (mips_pic
== SVR4_PIC
)
1637 /* If this is a reference to an external symbol, we want
1638 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
1640 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
1642 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
1643 If there is a constant, it must be added in after. */
1644 ex
.X_add_number
= ep
->X_add_number
;
1645 ep
->X_add_number
= 0;
1647 macro_build ((char *) NULL
, counter
, ep
,
1648 mips_isa
< 3 ? "lw" : "ld",
1649 "t,o(b)", reg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
1650 macro_build ((char *) NULL
, counter
, (expressionS
*) NULL
, "nop", "");
1651 p
= frag_var (rs_machine_dependent
, 4, 0,
1652 RELAX_ENCODE (0, 4, -8, 0, 0, mips_warn_about_macros
),
1653 ep
->X_add_symbol
, (long) 0, (char *) NULL
);
1654 macro_build (p
, counter
, ep
,
1655 mips_isa
< 3 ? "addiu" : "daddiu",
1656 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
1657 if (ex
.X_add_number
!= 0)
1659 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
1660 as_bad ("PIC code offset overflow (max 16 signed bits)");
1661 ex
.X_op
= O_constant
;
1662 macro_build (p
, counter
, &ex
,
1663 mips_isa
< 3 ? "addiu" : "daddiu",
1664 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
1667 else if (mips_pic
== EMBEDDED_PIC
)
1670 addiu $reg,$gp,<sym> (BFD_RELOC_MIPS_GPREL)
1672 macro_build ((char *) NULL
, counter
, ep
,
1673 mips_isa
< 3 ? "addiu" : "daddiu",
1674 "t,r,j", reg
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
1682 * This routine implements the seemingly endless macro or synthesized
1683 * instructions and addressing modes in the mips assembly language. Many
1684 * of these macros are simple and are similar to each other. These could
1685 * probably be handled by some kind of table or grammer aproach instead of
1686 * this verbose method. Others are not simple macros but are more like
1687 * optimizing code generation.
1688 * One interesting optimization is when several store macros appear
1689 * consecutivly that would load AT with the upper half of the same address.
1690 * The ensuing load upper instructions are ommited. This implies some kind
1691 * of global optimization. We currently only optimize within a single macro.
1692 * For many of the load and store macros if the address is specified as a
1693 * constant expression in the first 64k of memory (ie ld $2,0x4000c) we
1694 * first load register 'at' with zero and use it as the base register. The
1695 * mips assembler simply uses register $zero. Just one tiny optimization
1700 struct mips_cl_insn
*ip
;
1702 register int treg
, sreg
, dreg
, breg
;
1715 bfd_reloc_code_real_type r
;
1718 treg
= (ip
->insn_opcode
>> 16) & 0x1f;
1719 dreg
= (ip
->insn_opcode
>> 11) & 0x1f;
1720 sreg
= breg
= (ip
->insn_opcode
>> 21) & 0x1f;
1721 mask
= ip
->insn_mo
->mask
;
1723 expr1
.X_op
= O_constant
;
1724 expr1
.X_op_symbol
= NULL
;
1725 expr1
.X_add_symbol
= NULL
;
1726 expr1
.X_add_number
= 1;
1738 mips_emit_delays ();
1740 mips_any_noreorder
= 1;
1742 expr1
.X_add_number
= 8;
1743 macro_build ((char *) NULL
, &icnt
, &expr1
, "bgez", "s,p", sreg
);
1745 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
1747 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
, sreg
, 0);
1748 macro_build ((char *) NULL
, &icnt
, NULL
,
1749 dbl
? "dsub" : "sub",
1750 "d,v,t", dreg
, 0, sreg
);
1773 if (imm_expr
.X_add_number
>= -0x8000 && imm_expr
.X_add_number
< 0x8000)
1775 macro_build ((char *) NULL
, &icnt
, &imm_expr
, s
, "t,r,j", treg
, sreg
,
1776 (int) BFD_RELOC_LO16
);
1779 load_register (&icnt
, AT
, &imm_expr
);
1780 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "d,v,t", treg
, sreg
, AT
);
1799 if (imm_expr
.X_add_number
>= 0 && imm_expr
.X_add_number
< 0x10000)
1801 if (mask
!= M_NOR_I
)
1802 macro_build ((char *) NULL
, &icnt
, &imm_expr
, s
, "t,r,i", treg
,
1803 sreg
, (int) BFD_RELOC_LO16
);
1806 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "ori", "t,r,i",
1807 treg
, sreg
, (int) BFD_RELOC_LO16
);
1808 macro_build ((char *) NULL
, &icnt
, NULL
, "nor", "d,v,t",
1814 load_register (&icnt
, AT
, &imm_expr
);
1815 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "d,v,t", treg
, sreg
, AT
);
1832 if (imm_expr
.X_add_number
== 0)
1834 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "s,t,p", sreg
,
1838 load_register (&icnt
, AT
, &imm_expr
);
1839 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "s,t,p", sreg
, AT
);
1847 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
1848 likely
? "bgezl" : "bgez",
1854 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
1855 likely
? "blezl" : "blez",
1859 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", AT
, sreg
, treg
);
1860 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
1861 likely
? "beql" : "beq",
1868 /* check for > max integer */
1869 maxnum
= 0x7fffffff;
1877 if (imm_expr
.X_add_number
>= maxnum
)
1880 /* result is always false */
1883 as_warn ("Branch %s is always false (nop)", ip
->insn_mo
->name
);
1884 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
1888 as_warn ("Branch likely %s is always false", ip
->insn_mo
->name
);
1889 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "bnel",
1894 imm_expr
.X_add_number
++;
1898 if (mask
== M_BGEL_I
)
1900 if (imm_expr
.X_add_number
== 0)
1902 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
1903 likely
? "bgezl" : "bgez",
1907 if (imm_expr
.X_add_number
== 1)
1909 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
1910 likely
? "bgtzl" : "bgtz",
1914 maxnum
= 0x7fffffff;
1922 maxnum
= - maxnum
- 1;
1923 if (imm_expr
.X_add_number
<= maxnum
)
1926 /* result is always true */
1927 as_warn ("Branch %s is always true", ip
->insn_mo
->name
);
1928 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "b", "p");
1931 set_at (&icnt
, sreg
, 0);
1932 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
1933 likely
? "beql" : "beq",
1944 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
1945 likely
? "beql" : "beq",
1949 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", AT
, sreg
,
1951 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
1952 likely
? "beql" : "beq",
1959 if (sreg
== 0 || imm_expr
.X_add_number
== -1)
1961 imm_expr
.X_add_number
++;
1965 if (mask
== M_BGEUL_I
)
1967 if (imm_expr
.X_add_number
== 0)
1969 if (imm_expr
.X_add_number
== 1)
1971 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
1972 likely
? "bnel" : "bne",
1976 set_at (&icnt
, sreg
, 1);
1977 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
1978 likely
? "beql" : "beq",
1987 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
1988 likely
? "bgtzl" : "bgtz",
1994 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
1995 likely
? "bltzl" : "bltz",
1999 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", AT
, treg
, sreg
);
2000 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2001 likely
? "bnel" : "bne",
2010 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2011 likely
? "bnel" : "bne",
2017 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", AT
, treg
,
2019 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2020 likely
? "bnel" : "bne",
2029 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2030 likely
? "blezl" : "blez",
2036 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2037 likely
? "bgezl" : "bgez",
2041 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", AT
, treg
, sreg
);
2042 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2043 likely
? "beql" : "beq",
2050 maxnum
= 0x7fffffff;
2058 if (imm_expr
.X_add_number
>= maxnum
)
2060 imm_expr
.X_add_number
++;
2064 if (mask
== M_BLTL_I
)
2066 if (imm_expr
.X_add_number
== 0)
2068 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2069 likely
? "bltzl" : "bltz",
2073 if (imm_expr
.X_add_number
== 1)
2075 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2076 likely
? "blezl" : "blez",
2080 set_at (&icnt
, sreg
, 0);
2081 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2082 likely
? "bnel" : "bne",
2091 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2092 likely
? "beql" : "beq",
2098 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", AT
, treg
,
2100 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2101 likely
? "beql" : "beq",
2108 if (sreg
== 0 || imm_expr
.X_add_number
== -1)
2110 imm_expr
.X_add_number
++;
2114 if (mask
== M_BLTUL_I
)
2116 if (imm_expr
.X_add_number
== 0)
2118 if (imm_expr
.X_add_number
== 1)
2120 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2121 likely
? "beql" : "beq",
2125 set_at (&icnt
, sreg
, 1);
2126 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2127 likely
? "bnel" : "bne",
2136 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2137 likely
? "bltzl" : "bltz",
2143 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2144 likely
? "bgtzl" : "bgtz",
2148 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", AT
, sreg
, treg
);
2149 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2150 likely
? "bnel" : "bne",
2161 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2162 likely
? "bnel" : "bne",
2166 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", AT
, sreg
,
2168 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2169 likely
? "bnel" : "bne",
2185 as_warn ("Divide by zero.");
2187 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", 0, 0);
2189 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 7);
2193 mips_emit_delays ();
2195 mips_any_noreorder
= 1;
2196 macro_build ((char *) NULL
, &icnt
, NULL
,
2197 dbl
? "ddiv" : "div",
2198 "z,s,t", sreg
, treg
);
2200 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", treg
, 0);
2203 expr1
.X_add_number
= 8;
2204 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", treg
, 0);
2205 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
2206 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 7);
2208 expr1
.X_add_number
= -1;
2209 macro_build ((char *) NULL
, &icnt
, &expr1
,
2210 dbl
? "daddiu" : "addiu",
2211 "t,r,j", AT
, 0, (int) BFD_RELOC_LO16
);
2212 expr1
.X_add_number
= mips_trap
? (dbl
? 12 : 8) : (dbl
? 20 : 16);
2213 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", treg
, AT
);
2216 expr1
.X_add_number
= 1;
2217 macro_build ((char *) NULL
, &icnt
, &expr1
, "daddiu", "t,r,j", AT
, 0,
2218 (int) BFD_RELOC_LO16
);
2219 macro_build ((char *) NULL
, &icnt
, NULL
, "dsll32", "d,w,<", AT
, AT
,
2224 expr1
.X_add_number
= 0x80000000;
2225 macro_build ((char *) NULL
, &icnt
, &expr1
, "lui", "t,u", AT
,
2226 (int) BFD_RELOC_HI16
);
2229 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", sreg
, AT
);
2232 expr1
.X_add_number
= 8;
2233 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", sreg
, AT
);
2234 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
2235 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 6);
2238 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d", dreg
);
2277 if (imm_expr
.X_add_number
== 0)
2279 as_warn ("Divide by zero.");
2281 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", 0, 0);
2283 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 7);
2286 if (imm_expr
.X_add_number
== 1)
2288 if (strcmp (s2
, "mflo") == 0)
2289 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
,
2292 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
, 0);
2295 if (imm_expr
.X_add_number
== -1
2296 && s
[strlen (s
) - 1] != 'u')
2298 if (strcmp (s2
, "mflo") == 0)
2301 macro_build ((char *) NULL
, &icnt
, NULL
, "dneg", "d,w", dreg
,
2304 macro_build ((char *) NULL
, &icnt
, NULL
, "neg", "d,w", dreg
,
2308 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
, 0);
2312 load_register (&icnt
, AT
, &imm_expr
);
2313 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "z,s,t", sreg
, AT
);
2314 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "d", dreg
);
2333 mips_emit_delays ();
2335 mips_any_noreorder
= 1;
2336 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "z,s,t", sreg
, treg
);
2338 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", treg
, 0);
2341 expr1
.X_add_number
= 8;
2342 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", treg
, 0);
2343 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
2344 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 7);
2347 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "d", dreg
);
2351 /* Load the address of a symbol into a register. If breg is not
2352 zero, we then add a base register to it. */
2354 /* When generating embedded PIC code, we permit expressions of
2357 where bar is an address in the .text section. These are used
2358 when getting the addresses of functions. We don't permit
2359 X_add_number to be non-zero, because if the symbol is
2360 external the relaxing code needs to know that any addend is
2361 purely the offset to X_op_symbol. */
2362 if (mips_pic
== EMBEDDED_PIC
2363 && offset_expr
.X_op
== O_subtract
2364 && now_seg
== text_section
2365 && S_GET_SEGMENT (offset_expr
.X_op_symbol
) == text_section
2367 && offset_expr
.X_add_number
== 0)
2369 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
2370 treg
, (int) BFD_RELOC_PCREL_HI16_S
);
2371 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2372 mips_isa
< 3 ? "addiu" : "daddiu",
2373 "t,r,j", treg
, treg
, (int) BFD_RELOC_PCREL_LO16
);
2377 if (offset_expr
.X_op
!= O_symbol
2378 && offset_expr
.X_op
!= O_constant
)
2380 as_bad ("expression too complex");
2381 offset_expr
.X_op
= O_constant
;
2395 if (offset_expr
.X_op
== O_constant
)
2396 load_register (&icnt
, tempreg
, &offset_expr
);
2397 else if (mips_pic
== NO_PIC
)
2399 /* If this is a reference to an GP relative symbol, we want
2400 addiu $tempreg,$gp,<sym> (BFD_RELOC_MIPS_GPREL)
2402 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
2403 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
2404 If we have a constant, we need two instructions anyhow,
2405 so we may as well always use the latter form. */
2406 if (offset_expr
.X_add_number
!= 0)
2411 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2412 mips_isa
< 3 ? "addiu" : "daddiu",
2413 "t,r,j", tempreg
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
2414 p
= frag_var (rs_machine_dependent
, 8, 0,
2415 RELAX_ENCODE (4, 8, 0, 4, 0,
2416 mips_warn_about_macros
),
2417 offset_expr
.X_add_symbol
, (long) 0,
2420 macro_build_lui (p
, &icnt
, &offset_expr
, tempreg
);
2423 macro_build (p
, &icnt
, &offset_expr
,
2424 mips_isa
< 3 ? "addiu" : "daddiu",
2425 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
2427 else if (mips_pic
== SVR4_PIC
)
2429 /* If this is a reference to an external symbol, and there
2430 is no constant, we want
2431 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
2432 For a local symbol, we want
2433 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
2435 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
2437 If we have a small constant, and this is a reference to
2438 an external symbol, we want
2439 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
2441 addiu $tempreg,$tempreg,<constant>
2442 For a local symbol, we want the same instruction
2443 sequence, but we output a BFD_RELOC_LO16 reloc on the
2446 If we have a large constant, and this is a reference to
2447 an external symbol, we want
2448 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
2449 lui $at,<hiconstant>
2450 addiu $at,$at,<loconstant>
2451 addu $tempreg,$tempreg,$at
2452 For a local symbol, we want the same instruction
2453 sequence, but we output a BFD_RELOC_LO16 reloc on the
2454 addiu instruction. */
2455 expr1
.X_add_number
= offset_expr
.X_add_number
;
2456 offset_expr
.X_add_number
= 0;
2458 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2459 mips_isa
< 3 ? "lw" : "ld",
2460 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
2461 if (expr1
.X_add_number
== 0)
2469 /* We're going to put in an addu instruction using
2470 tempreg, so we may as well insert the nop right
2472 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
2476 p
= frag_var (rs_machine_dependent
, 8 - off
, 0,
2477 RELAX_ENCODE (0, 8 - off
, -4 - off
, 4 - off
, 0,
2479 ? mips_warn_about_macros
2481 offset_expr
.X_add_symbol
, (long) 0,
2485 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
2488 macro_build (p
, &icnt
, &expr1
,
2489 mips_isa
< 3 ? "addiu" : "daddiu",
2490 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
2491 /* FIXME: If breg == 0, and the next instruction uses
2492 $tempreg, then if this variant case is used an extra
2493 nop will be generated. */
2495 else if (expr1
.X_add_number
>= -0x8000
2496 && expr1
.X_add_number
< 0x8000)
2498 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
2500 macro_build ((char *) NULL
, &icnt
, &expr1
,
2501 mips_isa
< 3 ? "addiu" : "daddiu",
2502 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
2503 (void) frag_var (rs_machine_dependent
, 0, 0,
2504 RELAX_ENCODE (0, 0, -12, -4, 0, 0),
2505 offset_expr
.X_add_symbol
, (long) 0,
2512 /* If we are going to add in a base register, and the
2513 target register and the base register are the same,
2514 then we are using AT as a temporary register. Since
2515 we want to load the constant into AT, we add our
2516 current AT (from the global offset table) and the
2517 register into the register now, and pretend we were
2518 not using a base register. */
2523 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
2525 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
2526 mips_isa
< 3 ? "addu" : "daddu",
2527 "d,v,t", treg
, AT
, breg
);
2533 macro_build_lui ((char *) NULL
, &icnt
, &expr1
, AT
);
2534 macro_build ((char *) NULL
, &icnt
, &expr1
,
2535 mips_isa
< 3 ? "addiu" : "daddiu",
2536 "t,r,j", AT
, AT
, (int) BFD_RELOC_LO16
);
2537 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
2538 mips_isa
< 3 ? "addu" : "daddu",
2539 "d,v,t", tempreg
, tempreg
, AT
);
2540 (void) frag_var (rs_machine_dependent
, 0, 0,
2541 RELAX_ENCODE (0, 0, -16 + off1
, -8, 0, 0),
2542 offset_expr
.X_add_symbol
, (long) 0,
2547 else if (mips_pic
== EMBEDDED_PIC
)
2550 addiu $tempreg,$gp,<sym> (BFD_RELOC_MIPS_GPREL)
2552 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2553 mips_isa
< 3 ? "addiu" : "daddiu",
2554 "t,r,j", tempreg
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
2560 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
2561 mips_isa
< 3 ? "addu" : "daddu",
2562 "d,v,t", treg
, tempreg
, breg
);
2570 /* The j instruction may not be used in PIC code, since it
2571 requires an absolute address. We convert it to a b
2573 if (mips_pic
== NO_PIC
)
2574 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "j", "a");
2576 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "b", "p");
2579 /* The jal instructions must be handled as macros because when
2580 generating PIC code they expand to multi-instruction
2581 sequences. Normally they are simple instructions. */
2586 if (mips_pic
== NO_PIC
2587 || mips_pic
== EMBEDDED_PIC
)
2588 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "jalr",
2590 else if (mips_pic
== SVR4_PIC
)
2592 if (sreg
!= PIC_CALL_REG
)
2593 as_warn ("MIPS PIC call to register other than $25");
2595 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "jalr",
2597 if (mips_cprestore_offset
< 0)
2598 as_warn ("No .cprestore pseudo-op used in PIC code");
2601 expr1
.X_add_number
= mips_cprestore_offset
;
2602 macro_build ((char *) NULL
, &icnt
, &expr1
,
2603 mips_isa
< 3 ? "lw" : "ld",
2604 "t,o(b)", GP
, (int) BFD_RELOC_LO16
, mips_frame_reg
);
2613 if (mips_pic
== NO_PIC
)
2614 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "jal", "a");
2615 else if (mips_pic
== SVR4_PIC
)
2617 /* If this is a reference to an external symbol, we want
2618 lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
2622 lw $gp,cprestore($sp)
2623 The cprestore value is set using the .cprestore
2624 pseudo-op. If the symbol is not external, we want
2625 lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
2627 addiu $25,$25,<sym> (BFD_RELOC_LO16)
2630 lw $gp,cprestore($sp)
2633 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2634 mips_isa
< 3 ? "lw" : "ld",
2635 "t,o(b)", PIC_CALL_REG
,
2636 (int) BFD_RELOC_MIPS_CALL16
, GP
);
2637 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
2638 p
= frag_var (rs_machine_dependent
, 4, 0,
2639 RELAX_ENCODE (0, 4, -8, 0, 0, 0),
2640 offset_expr
.X_add_symbol
, (long) 0, (char *) NULL
);
2641 macro_build (p
, &icnt
, &offset_expr
,
2642 mips_isa
< 3 ? "addiu" : "daddiu",
2643 "t,r,j", PIC_CALL_REG
, PIC_CALL_REG
,
2644 (int) BFD_RELOC_LO16
);
2645 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
2646 "jalr", "s", PIC_CALL_REG
);
2647 if (mips_cprestore_offset
< 0)
2648 as_warn ("No .cprestore pseudo-op used in PIC code");
2652 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
2654 expr1
.X_add_number
= mips_cprestore_offset
;
2655 macro_build ((char *) NULL
, &icnt
, &expr1
,
2656 mips_isa
< 3 ? "lw" : "ld",
2657 "t,o(b)", GP
, (int) BFD_RELOC_LO16
,
2661 else if (mips_pic
== EMBEDDED_PIC
)
2663 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "bal", "p");
2664 /* The linker may expand the call to a longer sequence which
2665 uses $at, so we must break rather than return. */
2737 if (breg
== treg
|| coproc
)
2806 if (mask
== M_LWC1_AB
2807 || mask
== M_SWC1_AB
2808 || mask
== M_LDC1_AB
2809 || mask
== M_SDC1_AB
2818 if (offset_expr
.X_op
!= O_constant
2819 && offset_expr
.X_op
!= O_symbol
)
2821 as_bad ("expression too complex");
2822 offset_expr
.X_op
= O_constant
;
2825 /* A constant expression in PIC code can be handled just as it
2826 is in non PIC code. */
2827 if (mips_pic
== NO_PIC
2828 || offset_expr
.X_op
== O_constant
)
2830 /* If this is a reference to a GP relative symbol, and there
2831 is no base register, we want
2832 <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL)
2833 Otherwise, if there is no base register, we want
2834 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
2835 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
2836 If we have a constant, we need two instructions anyhow,
2837 so we always use the latter form.
2839 If we have a base register, and this is a reference to a
2840 GP relative symbol, we want
2841 addu $tempreg,$breg,$gp
2842 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GPREL)
2844 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
2845 addu $tempreg,$tempreg,$breg
2846 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
2847 With a constant we always use the latter case. */
2850 if (offset_expr
.X_add_number
!= 0)
2855 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
2856 treg
, (int) BFD_RELOC_MIPS_GPREL
, GP
);
2857 p
= frag_var (rs_machine_dependent
, 8, 0,
2858 RELAX_ENCODE (4, 8, 0, 4, 0,
2859 (mips_warn_about_macros
2860 || (used_at
&& mips_noat
))),
2861 offset_expr
.X_add_symbol
, (long) 0,
2865 macro_build_lui (p
, &icnt
, &offset_expr
, tempreg
);
2868 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
, treg
,
2869 (int) BFD_RELOC_LO16
, tempreg
);
2873 if (offset_expr
.X_add_number
!= 0)
2878 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
2879 mips_isa
< 3 ? "addu" : "daddu",
2880 "d,v,t", tempreg
, breg
, GP
);
2881 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
2882 treg
, (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
2883 p
= frag_var (rs_machine_dependent
, 12, 0,
2884 RELAX_ENCODE (8, 12, 0, 8, 0, 0),
2885 offset_expr
.X_add_symbol
, (long) 0,
2888 macro_build_lui (p
, &icnt
, &offset_expr
, tempreg
);
2891 macro_build (p
, &icnt
, (expressionS
*) NULL
,
2892 mips_isa
< 3 ? "addu" : "daddu",
2893 "d,v,t", tempreg
, tempreg
, breg
);
2896 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
, treg
,
2897 (int) BFD_RELOC_LO16
, tempreg
);
2900 else if (mips_pic
== SVR4_PIC
)
2902 /* If this is a reference to an external symbol, we want
2903 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
2905 <op> $treg,0($tempreg)
2907 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
2909 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
2910 <op> $treg,0($tempreg)
2911 If there is a base register, we add it to $tempreg before
2912 the <op>. If there is a constant, we stick it in the
2913 <op> instruction. We don't handle constants larger than
2914 16 bits, because we have no way to load the upper 16 bits
2915 (actually, we could handle them for the subset of cases
2916 in which we are not using $at). */
2917 assert (offset_expr
.X_op
== O_symbol
);
2918 expr1
.X_add_number
= offset_expr
.X_add_number
;
2919 offset_expr
.X_add_number
= 0;
2920 if (expr1
.X_add_number
< -0x8000
2921 || expr1
.X_add_number
>= 0x8000)
2922 as_bad ("PIC code offset overflow (max 16 signed bits)");
2924 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2925 mips_isa
< 3 ? "lw" : "ld",
2926 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
2927 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
2928 p
= frag_var (rs_machine_dependent
, 4, 0,
2929 RELAX_ENCODE (0, 4, -8, 0, 0, 0),
2930 offset_expr
.X_add_symbol
, (long) 0,
2932 macro_build (p
, &icnt
, &offset_expr
,
2933 mips_isa
< 3 ? "addiu" : "daddiu",
2934 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
2936 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
2937 mips_isa
< 3 ? "addu" : "daddu",
2938 "d,v,t", tempreg
, tempreg
, breg
);
2939 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
, treg
,
2940 (int) BFD_RELOC_LO16
, tempreg
);
2942 else if (mips_pic
== EMBEDDED_PIC
)
2944 /* If there is no base register, we want
2945 <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL)
2946 If there is a base register, we want
2947 addu $tempreg,$breg,$gp
2948 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GPREL)
2950 assert (offset_expr
.X_op
== O_symbol
);
2953 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
2954 treg
, (int) BFD_RELOC_MIPS_GPREL
, GP
);
2959 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
2960 mips_isa
< 3 ? "addu" : "daddu",
2961 "d,v,t", tempreg
, breg
, GP
);
2962 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
2963 treg
, (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
2976 load_register (&icnt
, treg
, &imm_expr
);
2980 if (mips_pic
== NO_PIC
)
2982 assert (offset_expr
.X_op
== O_symbol
2983 && strcmp (segment_name (S_GET_SEGMENT
2984 (offset_expr
.X_add_symbol
)),
2986 && offset_expr
.X_add_number
== 0);
2987 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lwc1", "T,o(b)",
2988 treg
, (int) BFD_RELOC_MIPS_LITERAL
, GP
);
2990 else if (mips_pic
== SVR4_PIC
2991 || mips_pic
== EMBEDDED_PIC
)
2993 assert (imm_expr
.X_op
== O_constant
);
2994 load_register (&icnt
, treg
, &imm_expr
);
3002 /* We know that sym is in the .rdata section. First we get the
3003 upper 16 bits of the address. */
3004 if (mips_pic
== NO_PIC
)
3006 /* FIXME: This won't work for a 64 bit address. */
3007 macro_build_lui ((char *) NULL
, &icnt
, &offset_expr
, AT
);
3009 else if (mips_pic
== SVR4_PIC
)
3011 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3012 mips_isa
< 3 ? "lw" : "ld",
3013 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
3015 else if (mips_pic
== EMBEDDED_PIC
)
3017 /* For embedded PIC we pick up the entire address off $gp in
3018 a single instruction. */
3019 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3020 mips_isa
< 3 ? "addiu" : "daddiu",
3021 "t,r,j", AT
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
3022 offset_expr
.X_op
= O_constant
;
3023 offset_expr
.X_add_number
= 0;
3028 /* Now we load the register(s). */
3030 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "ld", "t,o(b)",
3031 treg
, (int) BFD_RELOC_LO16
, AT
);
3034 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lw", "t,o(b)",
3035 treg
, (int) BFD_RELOC_LO16
, AT
);
3038 /* FIXME: How in the world do we deal with the possible
3040 offset_expr
.X_add_number
+= 4;
3041 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lw", "t,o(b)",
3042 treg
+ 1, (int) BFD_RELOC_LO16
, AT
);
3049 if (mips_pic
== NO_PIC
3050 || mips_pic
== EMBEDDED_PIC
)
3052 /* Load a floating point number from the .lit8 section. */
3053 assert (offset_expr
.X_op
== O_symbol
3054 && strcmp (segment_name (S_GET_SEGMENT
3055 (offset_expr
.X_add_symbol
)),
3057 && offset_expr
.X_add_number
== 0);
3060 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "ldc1",
3061 "T,o(b)", treg
, (int) BFD_RELOC_MIPS_LITERAL
, GP
);
3065 r
= BFD_RELOC_MIPS_LITERAL
;
3068 else if (mips_pic
== SVR4_PIC
)
3070 /* Load the double from the .rdata section. */
3071 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3072 mips_isa
< 3 ? "lw" : "ld",
3073 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
3076 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "ldc1",
3077 "T,o(b)", treg
, (int) BFD_RELOC_LO16
, GP
);
3088 /* Even on a big endian machine $fn comes before $fn+1. We have
3089 to adjust when loading from memory. */
3092 assert (mips_isa
< 2);
3093 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lwc1", "T,o(b)",
3094 byte_order
== LITTLE_ENDIAN
? treg
: treg
+ 1,
3096 /* FIXME: A possible overflow which I don't know how to deal
3098 offset_expr
.X_add_number
+= 4;
3099 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lwc1", "T,o(b)",
3100 byte_order
== LITTLE_ENDIAN
? treg
+ 1 : treg
,
3108 * The MIPS assembler seems to check for X_add_number not
3109 * being double aligned and generating:
3112 * addiu at,at,%lo(foo+1)
3115 * But, the resulting address is the same after relocation so why
3116 * generate the extra instruction?
3163 if (offset_expr
.X_op
!= O_symbol
3164 && offset_expr
.X_op
!= O_constant
)
3166 as_bad ("expression too complex");
3167 offset_expr
.X_op
= O_constant
;
3170 /* Even on a big endian machine $fn comes before $fn+1. We have
3171 to adjust when loading from memory. We set coproc if we must
3172 load $fn+1 first. */
3173 if (byte_order
== LITTLE_ENDIAN
)
3176 if (mips_pic
== NO_PIC
3177 || offset_expr
.X_op
== O_constant
)
3179 /* If this is a reference to a GP relative symbol, we want
3180 <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL)
3181 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_MIPS_GPREL)
3182 If we have a base register, we use this
3184 <op> $treg,<sym>($at) (BFD_RELOC_MIPS_GPREL)
3185 <op> $treg+1,<sym>+4($at) (BFD_RELOC_MIPS_GPREL)
3186 If this is not a GP relative symbol, we want
3187 lui $at,<sym> (BFD_RELOC_HI16_S)
3188 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
3189 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
3190 If there is a base register, we add it to $at after the
3191 lui instruction. If there is a constant, we always use
3193 if (offset_expr
.X_add_number
!= 0)
3212 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3213 mips_isa
< 3 ? "addu" : "daddu",
3214 "d,v,t", AT
, breg
, GP
);
3220 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
3221 coproc
? treg
+ 1 : treg
,
3222 (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
3223 offset_expr
.X_add_number
+= 4;
3224 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
3225 coproc
? treg
: treg
+ 1,
3226 (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
3227 p
= frag_var (rs_machine_dependent
, 12 + off
, 0,
3228 RELAX_ENCODE (8 + off
, 12 + off
, 0, 4 + off
, 1,
3229 used_at
&& mips_noat
),
3230 offset_expr
.X_add_symbol
, (long) 0,
3233 /* We just generated two relocs. When tc_gen_reloc
3234 handles this case, it will skip the first reloc and
3235 handle the second. The second reloc already has an
3236 extra addend of 4, which we added above. We must
3237 subtract it out, and then subtract another 4 to make
3238 the first reloc come out right. The second reloc
3239 will come out right because we are going to add 4 to
3240 offset_expr when we build its instruction below. */
3241 offset_expr
.X_add_number
-= 8;
3242 offset_expr
.X_op
= O_constant
;
3244 macro_build_lui (p
, &icnt
, &offset_expr
, AT
);
3249 macro_build (p
, &icnt
, (expressionS
*) NULL
,
3250 mips_isa
< 3 ? "addu" : "daddu",
3251 "d,v,t", AT
, breg
, AT
);
3255 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
,
3256 coproc
? treg
+ 1 : treg
,
3257 (int) BFD_RELOC_LO16
, AT
);
3260 /* FIXME: How do we handle overflow here? */
3261 offset_expr
.X_add_number
+= 4;
3262 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
,
3263 coproc
? treg
: treg
+ 1,
3264 (int) BFD_RELOC_LO16
, AT
);
3266 else if (mips_pic
== SVR4_PIC
)
3270 /* If this is a reference to an external symbol, we want
3271 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3276 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3278 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
3279 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
3280 If there is a base register we add it to $at before the
3281 lwc1 instructions. If there is a constant we include it
3282 in the lwc1 instructions. */
3284 expr1
.X_add_number
= offset_expr
.X_add_number
;
3285 offset_expr
.X_add_number
= 0;
3286 if (expr1
.X_add_number
< -0x8000
3287 || expr1
.X_add_number
>= 0x8000 - 4)
3288 as_bad ("PIC code offset overflow (max 16 signed bits)");
3293 frag_grow (24 + off
);
3294 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3295 mips_isa
< 3 ? "lw" : "ld",
3296 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
3297 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
3299 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3300 mips_isa
< 3 ? "addu" : "daddu",
3301 "d,v,t", AT
, breg
, AT
);
3302 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
3303 coproc
? treg
+ 1 : treg
,
3304 (int) BFD_RELOC_LO16
, AT
);
3305 expr1
.X_add_number
+= 4;
3306 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
3307 coproc
? treg
: treg
+ 1,
3308 (int) BFD_RELOC_LO16
, AT
);
3309 (void) frag_var (rs_machine_dependent
, 0, 0,
3310 RELAX_ENCODE (0, 0, -16 - off
, -8, 1, 0),
3311 offset_expr
.X_add_symbol
, (long) 0,
3314 else if (mips_pic
== EMBEDDED_PIC
)
3316 /* If there is no base register, we use
3317 <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL)
3318 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_MIPS_GPREL)
3319 If we have a base register, we use
3321 <op> $treg,<sym>($at) (BFD_RELOC_MIPS_GPREL)
3322 <op> $treg+1,<sym>+4($at) (BFD_RELOC_MIPS_GPREL)
3331 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3332 mips_isa
< 3 ? "addu" : "daddu",
3333 "d,v,t", AT
, breg
, GP
);
3338 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
3339 coproc
? treg
+ 1 : treg
,
3340 (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
3341 offset_expr
.X_add_number
+= 4;
3342 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
3343 coproc
? treg
: treg
+ 1,
3344 (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
3360 assert (mips_isa
< 3);
3361 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
3362 (int) BFD_RELOC_LO16
, breg
);
3363 offset_expr
.X_add_number
+= 4;
3364 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
+ 1,
3365 (int) BFD_RELOC_LO16
, breg
);
3367 #ifdef LOSING_COMPILER
3373 as_warn ("Macro used $at after \".set noat\"");
3378 struct mips_cl_insn
*ip
;
3380 register int treg
, sreg
, dreg
, breg
;
3393 bfd_reloc_code_real_type r
;
3396 treg
= (ip
->insn_opcode
>> 16) & 0x1f;
3397 dreg
= (ip
->insn_opcode
>> 11) & 0x1f;
3398 sreg
= breg
= (ip
->insn_opcode
>> 21) & 0x1f;
3399 mask
= ip
->insn_mo
->mask
;
3401 expr1
.X_op
= O_constant
;
3402 expr1
.X_op_symbol
= NULL
;
3403 expr1
.X_add_symbol
= NULL
;
3404 expr1
.X_add_number
= 1;
3408 #endif /* LOSING_COMPILER */
3413 macro_build ((char *) NULL
, &icnt
, NULL
,
3414 dbl
? "dmultu" : "multu",
3416 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
3422 /* The MIPS assembler some times generates shifts and adds. I'm
3423 not trying to be that fancy. GCC should do this for us
3425 load_register (&icnt
, AT
, &imm_expr
);
3426 macro_build ((char *) NULL
, &icnt
, NULL
,
3427 dbl
? "dmult" : "mult",
3429 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
3435 mips_emit_delays ();
3437 mips_any_noreorder
= 1;
3438 macro_build ((char *) NULL
, &icnt
, NULL
,
3439 dbl
? "dmult" : "mult",
3441 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
3442 macro_build ((char *) NULL
, &icnt
, NULL
,
3443 dbl
? "dsra32" : "sra",
3444 "d,w,<", dreg
, dreg
, 31);
3445 macro_build ((char *) NULL
, &icnt
, NULL
, "mfhi", "d", AT
);
3447 macro_build ((char *) NULL
, &icnt
, NULL
, "tne", "s,t", dreg
, AT
);
3450 expr1
.X_add_number
= 8;
3451 macro_build ((char *) NULL
, &icnt
, &expr1
, "beq", "s,t,p", dreg
, AT
);
3452 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
3453 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 6);
3456 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
3462 mips_emit_delays ();
3464 mips_any_noreorder
= 1;
3465 macro_build ((char *) NULL
, &icnt
, NULL
,
3466 dbl
? "dmultu" : "multu",
3468 macro_build ((char *) NULL
, &icnt
, NULL
, "mfhi", "d", AT
);
3469 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
3471 macro_build ((char *) NULL
, &icnt
, NULL
, "tne", "s,t", AT
, 0);
3474 expr1
.X_add_number
= 8;
3475 macro_build ((char *) NULL
, &icnt
, &expr1
, "beq", "s,t,p", AT
, 0);
3476 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
3477 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 6);
3483 macro_build ((char *) NULL
, &icnt
, NULL
, "subu", "d,v,t", AT
, 0, treg
);
3484 macro_build ((char *) NULL
, &icnt
, NULL
, "srlv", "d,t,s", AT
, sreg
, AT
);
3485 macro_build ((char *) NULL
, &icnt
, NULL
, "sllv", "d,t,s", dreg
, sreg
,
3487 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
3491 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", AT
, sreg
,
3492 imm_expr
.X_add_number
& 0x1f);
3493 macro_build ((char *) NULL
, &icnt
, NULL
, "srl", "d,w,<", dreg
, sreg
,
3494 (0 - imm_expr
.X_add_number
) & 0x1f);
3495 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
3499 macro_build ((char *) NULL
, &icnt
, NULL
, "subu", "d,v,t", AT
, 0, treg
);
3500 macro_build ((char *) NULL
, &icnt
, NULL
, "sllv", "d,t,s", AT
, sreg
, AT
);
3501 macro_build ((char *) NULL
, &icnt
, NULL
, "srlv", "d,t,s", dreg
, sreg
,
3503 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
3507 macro_build ((char *) NULL
, &icnt
, NULL
, "srl", "d,w,<", AT
, sreg
,
3508 imm_expr
.X_add_number
& 0x1f);
3509 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", dreg
, sreg
,
3510 (0 - imm_expr
.X_add_number
) & 0x1f);
3511 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
3515 assert (mips_isa
< 2);
3516 /* Even on a big endian machine $fn comes before $fn+1. We have
3517 to adjust when storing to memory. */
3518 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "swc1", "T,o(b)",
3519 byte_order
== LITTLE_ENDIAN
? treg
: treg
+ 1,
3520 (int) BFD_RELOC_LO16
, breg
);
3521 offset_expr
.X_add_number
+= 4;
3522 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "swc1", "T,o(b)",
3523 byte_order
== LITTLE_ENDIAN
? treg
+ 1 : treg
,
3524 (int) BFD_RELOC_LO16
, breg
);
3529 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
3530 treg
, (int) BFD_RELOC_LO16
);
3532 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
3533 sreg
, (int) BFD_RELOC_LO16
);
3536 macro_build ((char *) NULL
, &icnt
, NULL
, "xor", "d,v,t", dreg
,
3538 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
3539 dreg
, (int) BFD_RELOC_LO16
);
3544 if (imm_expr
.X_add_number
== 0)
3546 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
3547 sreg
, (int) BFD_RELOC_LO16
);
3552 as_warn ("Instruction %s: result is always false",
3554 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
, 0);
3557 if (imm_expr
.X_add_number
>= 0 && imm_expr
.X_add_number
< 0x10000)
3559 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "xori", "t,r,i", dreg
,
3560 sreg
, (int) BFD_RELOC_LO16
);
3563 else if (imm_expr
.X_add_number
> -0x8000 && imm_expr
.X_add_number
< 0)
3565 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
3566 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
3567 mips_isa
< 3 ? "addiu" : "daddiu",
3568 "t,r,j", dreg
, sreg
,
3569 (int) BFD_RELOC_LO16
);
3574 load_register (&icnt
, AT
, &imm_expr
);
3575 macro_build ((char *) NULL
, &icnt
, NULL
, "xor", "d,v,t", dreg
,
3579 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
, dreg
,
3580 (int) BFD_RELOC_LO16
);
3585 case M_SGE
: /* sreg >= treg <==> not (sreg < treg) */
3591 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, sreg
, treg
);
3592 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
3593 (int) BFD_RELOC_LO16
);
3596 case M_SGE_I
: /* sreg >= I <==> not (sreg < I) */
3598 if (imm_expr
.X_add_number
>= -0x8000 && imm_expr
.X_add_number
< 0x8000)
3600 macro_build ((char *) NULL
, &icnt
, &expr1
,
3601 mask
== M_SGE_I
? "slti" : "sltiu",
3602 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
3607 load_register (&icnt
, AT
, &imm_expr
);
3608 macro_build ((char *) NULL
, &icnt
, NULL
,
3609 mask
== M_SGE_I
? "slt" : "sltu",
3610 "d,v,t", dreg
, sreg
, AT
);
3613 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
3614 (int) BFD_RELOC_LO16
);
3619 case M_SGT
: /* sreg > treg <==> treg < sreg */
3625 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, treg
, sreg
);
3628 case M_SGT_I
: /* sreg > I <==> I < sreg */
3634 load_register (&icnt
, AT
, &imm_expr
);
3635 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, AT
, sreg
);
3638 case M_SLE
: /* sreg <= treg <==> treg >= sreg <==> not (treg < sreg) */
3644 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, treg
, sreg
);
3645 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
3646 (int) BFD_RELOC_LO16
);
3649 case M_SLE_I
: /* sreg <= I <==> I >= sreg <==> not (I < sreg) */
3655 load_register (&icnt
, AT
, &imm_expr
);
3656 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, AT
, sreg
);
3657 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
3658 (int) BFD_RELOC_LO16
);
3662 if (imm_expr
.X_add_number
>= -0x8000 && imm_expr
.X_add_number
< 0x8000)
3664 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "slti", "t,r,j",
3665 dreg
, sreg
, (int) BFD_RELOC_LO16
);
3668 load_register (&icnt
, AT
, &imm_expr
);
3669 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", dreg
, sreg
, AT
);
3673 if (imm_expr
.X_add_number
>= -0x8000 && imm_expr
.X_add_number
< 0x8000)
3675 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "sltiu", "t,r,j",
3676 dreg
, sreg
, (int) BFD_RELOC_LO16
);
3679 load_register (&icnt
, AT
, &imm_expr
);
3680 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, sreg
,
3686 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0,
3689 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0,
3693 macro_build ((char *) NULL
, &icnt
, NULL
, "xor", "d,v,t", dreg
,
3695 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0,
3701 if (imm_expr
.X_add_number
== 0)
3703 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0,
3709 as_warn ("Instruction %s: result is always true",
3711 macro_build ((char *) NULL
, &icnt
, &expr1
,
3712 mips_isa
< 3 ? "addiu" : "daddiu",
3713 "t,r,j", dreg
, 0, (int) BFD_RELOC_LO16
);
3716 if (imm_expr
.X_add_number
>= 0 && imm_expr
.X_add_number
< 0x10000)
3718 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "xori", "t,r,i",
3719 dreg
, sreg
, (int) BFD_RELOC_LO16
);
3722 else if (imm_expr
.X_add_number
> -0x8000 && imm_expr
.X_add_number
< 0)
3724 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
3725 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
3726 mips_isa
< 3 ? "addiu" : "daddiu",
3727 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
3732 load_register (&icnt
, AT
, &imm_expr
);
3733 macro_build ((char *) NULL
, &icnt
, NULL
, "xor", "d,v,t", dreg
,
3737 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0, dreg
);
3745 if (imm_expr
.X_add_number
> -0x8000 && imm_expr
.X_add_number
<= 0x8000)
3747 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
3748 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
3749 dbl
? "daddi" : "addi",
3750 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
3753 load_register (&icnt
, AT
, &imm_expr
);
3754 macro_build ((char *) NULL
, &icnt
, NULL
,
3755 dbl
? "dsub" : "sub",
3756 "d,v,t", dreg
, sreg
, AT
);
3762 if (imm_expr
.X_add_number
> -0x8000 && imm_expr
.X_add_number
<= 0x8000)
3764 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
3765 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
3766 dbl
? "daddiu" : "addiu",
3767 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
3770 load_register (&icnt
, AT
, &imm_expr
);
3771 macro_build ((char *) NULL
, &icnt
, NULL
,
3772 dbl
? "dsubu" : "subu",
3773 "d,v,t", dreg
, sreg
, AT
);
3794 load_register (&icnt
, AT
, &imm_expr
);
3795 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "s,t", sreg
, AT
);
3800 assert (mips_isa
< 2);
3801 sreg
= (ip
->insn_opcode
>> 11) & 0x1f; /* floating reg */
3802 dreg
= (ip
->insn_opcode
>> 06) & 0x1f; /* floating reg */
3805 * Is the double cfc1 instruction a bug in the mips assembler;
3806 * or is there a reason for it?
3808 mips_emit_delays ();
3810 mips_any_noreorder
= 1;
3811 macro_build ((char *) NULL
, &icnt
, NULL
, "cfc1", "t,G", treg
, 31);
3812 macro_build ((char *) NULL
, &icnt
, NULL
, "cfc1", "t,G", treg
, 31);
3813 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "");
3814 expr1
.X_add_number
= 3;
3815 macro_build ((char *) NULL
, &icnt
, &expr1
, "ori", "t,r,i", AT
, treg
,
3816 (int) BFD_RELOC_LO16
);
3817 expr1
.X_add_number
= 2;
3818 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", AT
, AT
,
3819 (int) BFD_RELOC_LO16
);
3820 macro_build ((char *) NULL
, &icnt
, NULL
, "ctc1", "t,G", AT
, 31);
3821 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "");
3822 macro_build ((char *) NULL
, &icnt
, NULL
,
3823 mask
== M_TRUNCWD
? "cvt.w.d" : "cvt.w.s", "D,S", dreg
, sreg
);
3824 macro_build ((char *) NULL
, &icnt
, NULL
, "ctc1", "t,G", treg
, 31);
3825 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "");
3835 if (offset_expr
.X_add_number
>= 0x7fff)
3836 as_bad ("operand overflow");
3837 /* avoid load delay */
3838 if (byte_order
== LITTLE_ENDIAN
)
3839 offset_expr
.X_add_number
+= 1;
3840 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
3841 (int) BFD_RELOC_LO16
, breg
);
3842 if (byte_order
== LITTLE_ENDIAN
)
3843 offset_expr
.X_add_number
-= 1;
3845 offset_expr
.X_add_number
+= 1;
3846 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lbu", "t,o(b)", AT
,
3847 (int) BFD_RELOC_LO16
, breg
);
3848 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", treg
, treg
, 8);
3849 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", treg
, treg
, AT
);
3853 if (offset_expr
.X_add_number
>= 0x7ffd)
3854 as_bad ("operand overflow");
3855 if (byte_order
== LITTLE_ENDIAN
)
3856 offset_expr
.X_add_number
+= 3;
3857 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lwl", "t,o(b)", treg
,
3858 (int) BFD_RELOC_LO16
, breg
);
3859 if (byte_order
== LITTLE_ENDIAN
)
3860 offset_expr
.X_add_number
-= 3;
3862 offset_expr
.X_add_number
+= 3;
3863 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lwr", "t,o(b)", treg
,
3864 (int) BFD_RELOC_LO16
, breg
);
3870 load_address (&icnt
, AT
, &offset_expr
);
3871 if (mask
== M_ULW_A
)
3873 if (byte_order
== LITTLE_ENDIAN
)
3874 expr1
.X_add_number
= 3;
3876 expr1
.X_add_number
= 0;
3877 macro_build ((char *) NULL
, &icnt
, &expr1
, "lwl", "t,o(b)", treg
,
3878 (int) BFD_RELOC_LO16
, AT
);
3879 if (byte_order
== LITTLE_ENDIAN
)
3880 expr1
.X_add_number
= 0;
3882 expr1
.X_add_number
= 3;
3883 macro_build ((char *) NULL
, &icnt
, &expr1
, "lwr", "t,o(b)", treg
,
3884 (int) BFD_RELOC_LO16
, AT
);
3888 if (byte_order
== BIG_ENDIAN
)
3889 expr1
.X_add_number
= 0;
3890 macro_build ((char *) NULL
, &icnt
, &expr1
,
3891 mask
== M_ULH_A
? "lb" : "lbu", "t,o(b)", treg
,
3892 (int) BFD_RELOC_LO16
, AT
);
3893 if (byte_order
== BIG_ENDIAN
)
3894 expr1
.X_add_number
= 1;
3896 expr1
.X_add_number
= 0;
3897 macro_build ((char *) NULL
, &icnt
, &expr1
, "lbu", "t,o(b)", AT
,
3898 (int) BFD_RELOC_LO16
, AT
);
3899 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", treg
,
3901 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", treg
,
3907 if (offset_expr
.X_add_number
>= 0x7fff)
3908 as_bad ("operand overflow");
3909 if (byte_order
== BIG_ENDIAN
)
3910 offset_expr
.X_add_number
+= 1;
3911 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "sb", "t,o(b)", treg
,
3912 (int) BFD_RELOC_LO16
, breg
);
3913 macro_build ((char *) NULL
, &icnt
, NULL
, "srl", "d,w,<", AT
, treg
, 8);
3914 if (byte_order
== BIG_ENDIAN
)
3915 offset_expr
.X_add_number
-= 1;
3917 offset_expr
.X_add_number
+= 1;
3918 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "sb", "t,o(b)", AT
,
3919 (int) BFD_RELOC_LO16
, breg
);
3923 if (offset_expr
.X_add_number
>= 0x7ffd)
3924 as_bad ("operand overflow");
3925 if (byte_order
== LITTLE_ENDIAN
)
3926 offset_expr
.X_add_number
+= 3;
3927 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "swl", "t,o(b)", treg
,
3928 (int) BFD_RELOC_LO16
, breg
);
3929 if (byte_order
== LITTLE_ENDIAN
)
3930 offset_expr
.X_add_number
-= 3;
3932 offset_expr
.X_add_number
+= 3;
3933 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "swr", "t,o(b)", treg
,
3934 (int) BFD_RELOC_LO16
, breg
);
3939 load_address (&icnt
, AT
, &offset_expr
);
3940 if (mask
== M_USW_A
)
3942 if (byte_order
== LITTLE_ENDIAN
)
3943 expr1
.X_add_number
= 3;
3945 expr1
.X_add_number
= 0;
3946 macro_build ((char *) NULL
, &icnt
, &expr1
, "swl", "t,o(b)", treg
,
3947 (int) BFD_RELOC_LO16
, AT
);
3948 if (byte_order
== LITTLE_ENDIAN
)
3949 expr1
.X_add_number
= 0;
3951 expr1
.X_add_number
= 3;
3952 macro_build ((char *) NULL
, &icnt
, &expr1
, "swr", "t,o(b)", treg
,
3953 (int) BFD_RELOC_LO16
, AT
);
3957 if (byte_order
== LITTLE_ENDIAN
)
3958 expr1
.X_add_number
= 0;
3959 macro_build ((char *) NULL
, &icnt
, &expr1
, "sb", "t,o(b)", treg
,
3960 (int) BFD_RELOC_LO16
, AT
);
3961 macro_build ((char *) NULL
, &icnt
, NULL
, "srl", "d,w,<", treg
,
3963 if (byte_order
== LITTLE_ENDIAN
)
3964 expr1
.X_add_number
= 1;
3966 expr1
.X_add_number
= 0;
3967 macro_build ((char *) NULL
, &icnt
, &expr1
, "sb", "t,o(b)", treg
,
3968 (int) BFD_RELOC_LO16
, AT
);
3969 if (byte_order
== LITTLE_ENDIAN
)
3970 expr1
.X_add_number
= 0;
3972 expr1
.X_add_number
= 1;
3973 macro_build ((char *) NULL
, &icnt
, &expr1
, "lbu", "t,o(b)", AT
,
3974 (int) BFD_RELOC_LO16
, AT
);
3975 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", treg
,
3977 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", treg
,
3983 as_bad ("Macro %s not implemented yet", ip
->insn_mo
->name
);
3987 as_warn ("Macro used $at after \".set noat\"");
3992 This routine assembles an instruction into its binary format. As a side
3993 effect it sets one of the global variables imm_reloc or offset_reloc to the
3994 type of relocation to do if one of the operands is an address expression.
3999 struct mips_cl_insn
*ip
;
4004 struct mips_opcode
*insn
;
4007 unsigned int lastregno
= 0;
4012 for (s
= str
; islower (*s
) || (*s
>= '0' && *s
<= '3') || *s
== '.'; ++s
)
4024 as_warn ("Unknown opcode: `%s'", str
);
4027 if ((insn
= (struct mips_opcode
*) hash_find (op_hash
, str
)) == NULL
)
4029 as_warn ("`%s' not in hash table.", str
);
4030 insn_error
= "ERROR: Unrecognized opcode";
4038 assert (strcmp (insn
->name
, str
) == 0);
4040 if (insn
->pinfo
== INSN_MACRO
)
4041 insn_isa
= insn
->match
;
4042 else if (insn
->pinfo
& INSN_ISA2
)
4044 else if (insn
->pinfo
& INSN_ISA3
)
4049 if (insn_isa
> mips_isa
)
4051 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
]
4052 && strcmp (insn
->name
, insn
[1].name
) == 0)
4057 as_warn ("Instruction not supported on this processor");
4061 ip
->insn_opcode
= insn
->match
;
4062 for (args
= insn
->args
;; ++args
)
4068 case '\0': /* end of args */
4081 ip
->insn_opcode
|= lastregno
<< 21;
4086 ip
->insn_opcode
|= lastregno
<< 16;
4090 ip
->insn_opcode
|= lastregno
<< 11;
4096 /* handle optional base register.
4097 Either the base register is omitted or
4098 we must have a left paren. */
4099 /* this is dependent on the next operand specifier
4100 is a 'b' for base register */
4101 assert (args
[1] == 'b');
4105 case ')': /* these must match exactly */
4110 case '<': /* must be at least one digit */
4112 * According to the manual, if the shift amount is greater
4113 * than 31 or less than 0 the the shift amount should be
4114 * mod 32. In reality the mips assembler issues an error.
4115 * We issue a warning and mask out all but the low 5 bits.
4117 my_getExpression (&imm_expr
, s
);
4118 check_absolute_expr (ip
, &imm_expr
);
4119 if ((unsigned long) imm_expr
.X_add_number
> 31)
4121 as_warn ("Improper shift amount (%ld)",
4122 (long) imm_expr
.X_add_number
);
4123 imm_expr
.X_add_number
= imm_expr
.X_add_number
& 0x1f;
4125 ip
->insn_opcode
|= imm_expr
.X_add_number
<< 6;
4126 imm_expr
.X_op
= O_absent
;
4130 case '>': /* shift amount minus 32 */
4131 my_getExpression (&imm_expr
, s
);
4132 check_absolute_expr (ip
, &imm_expr
);
4133 if ((unsigned long) imm_expr
.X_add_number
< 32
4134 || (unsigned long) imm_expr
.X_add_number
> 63)
4136 ip
->insn_opcode
|= (imm_expr
.X_add_number
- 32) << 6;
4137 imm_expr
.X_op
= O_absent
;
4141 case 'k': /* cache code */
4142 my_getExpression (&imm_expr
, s
);
4143 check_absolute_expr (ip
, &imm_expr
);
4144 if ((unsigned long) imm_expr
.X_add_number
> 31)
4146 as_warn ("Invalid cahce opcode (%lu)",
4147 (unsigned long) imm_expr
.X_add_number
);
4148 imm_expr
.X_add_number
&= 0x1f;
4150 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_CACHE
;
4151 imm_expr
.X_op
= O_absent
;
4155 case 'c': /* break code */
4156 my_getExpression (&imm_expr
, s
);
4157 check_absolute_expr (ip
, &imm_expr
);
4158 if ((unsigned) imm_expr
.X_add_number
> 1023)
4159 as_warn ("Illegal break code (%ld)",
4160 (long) imm_expr
.X_add_number
);
4161 ip
->insn_opcode
|= imm_expr
.X_add_number
<< 16;
4162 imm_expr
.X_op
= O_absent
;
4166 case 'B': /* syscall code */
4167 my_getExpression (&imm_expr
, s
);
4168 check_absolute_expr (ip
, &imm_expr
);
4169 if ((unsigned) imm_expr
.X_add_number
> 0xfffff)
4170 as_warn ("Illegal syscall code (%ld)",
4171 (long) imm_expr
.X_add_number
);
4172 ip
->insn_opcode
|= imm_expr
.X_add_number
<< 6;
4173 imm_expr
.X_op
= O_absent
;
4177 case 'C': /* Coprocessor code */
4178 my_getExpression (&imm_expr
, s
);
4179 check_absolute_expr (ip
, &imm_expr
);
4180 if ((unsigned long) imm_expr
.X_add_number
>= (1<<25))
4182 as_warn ("Coproccesor code > 25 bits (%ld)",
4183 (long) imm_expr
.X_add_number
);
4184 imm_expr
.X_add_number
&= ((1<<25) - 1);
4186 ip
->insn_opcode
|= imm_expr
.X_add_number
;
4187 imm_expr
.X_op
= O_absent
;
4191 case 'b': /* base register */
4192 case 'd': /* destination register */
4193 case 's': /* source register */
4194 case 't': /* target register */
4195 case 'r': /* both target and source */
4196 case 'v': /* both dest and source */
4197 case 'w': /* both dest and target */
4198 case 'E': /* coprocessor target register */
4199 case 'G': /* coprocessor destination register */
4200 case 'x': /* ignore register name */
4201 case 'z': /* must be zero register */
4215 while (isdigit (*s
));
4217 as_bad ("Invalid register number (%d)", regno
);
4219 else if (*args
== 'E' || *args
== 'G')
4223 if (s
[1] == 'f' && s
[2] == 'p')
4228 else if (s
[1] == 's' && s
[2] == 'p')
4233 else if (s
[1] == 'g' && s
[2] == 'p')
4238 else if (s
[1] == 'a' && s
[2] == 't')
4246 if (regno
== AT
&& ! mips_noat
)
4247 as_warn ("Used $at without \".set noat\"");
4253 if (c
== 'r' || c
== 'v' || c
== 'w')
4260 /* 'z' only matches $0. */
4261 if (c
== 'z' && regno
!= 0)
4269 ip
->insn_opcode
|= regno
<< 21;
4273 ip
->insn_opcode
|= regno
<< 11;
4278 ip
->insn_opcode
|= regno
<< 16;
4281 /* This case exists because on the r3000 trunc
4282 expands into a macro which requires a gp
4283 register. On the r6000 or r4000 it is
4284 assembled into a single instruction which
4285 ignores the register. Thus the insn version
4286 is MIPS_ISA2 and uses 'x', and the macro
4287 version is MIPS_ISA1 and uses 't'. */
4290 /* This case is for the div instruction, which
4291 acts differently if the destination argument
4292 is $0. This only matches $0, and is checked
4293 outside the switch. */
4304 ip
->insn_opcode
|= lastregno
<< 21;
4307 ip
->insn_opcode
|= lastregno
<< 16;
4312 case 'D': /* floating point destination register */
4313 case 'S': /* floating point source register */
4314 case 'T': /* floating point target register */
4318 if (s
[0] == '$' && s
[1] == 'f' && isdigit (s
[2]))
4328 while (isdigit (*s
));
4331 as_bad ("Invalid float register number (%d)", regno
);
4333 if ((regno
& 1) != 0
4335 && ! (strcmp (str
, "mtc1") == 0 ||
4336 strcmp (str
, "mfc1") == 0 ||
4337 strcmp (str
, "lwc1") == 0 ||
4338 strcmp (str
, "swc1") == 0))
4339 as_warn ("Float register should be even, was %d",
4347 if (c
== 'V' || c
== 'W')
4357 ip
->insn_opcode
|= regno
<< 6;
4361 ip
->insn_opcode
|= regno
<< 11;
4365 ip
->insn_opcode
|= regno
<< 16;
4373 ip
->insn_opcode
|= lastregno
<< 11;
4376 ip
->insn_opcode
|= lastregno
<< 16;
4382 my_getExpression (&imm_expr
, s
);
4383 check_absolute_expr (ip
, &imm_expr
);
4388 my_getExpression (&offset_expr
, s
);
4389 imm_reloc
= BFD_RELOC_32
;
4401 unsigned char temp
[8];
4403 unsigned int length
;
4408 /* These only appear as the last operand in an
4409 instruction, and every instruction that accepts
4410 them in any variant accepts them in all variants.
4411 This means we don't have to worry about backing out
4412 any changes if the instruction does not match.
4414 The difference between them is the size of the
4415 floating point constant and where it goes. For 'F'
4416 and 'L' the constant is 64 bits; for 'f' and 'l' it
4417 is 32 bits. Where the constant is placed is based
4418 on how the MIPS assembler does things:
4421 f -- immediate value
4424 When generating SVR4 PIC code, we do not use the
4425 .lit8 or .lit4 sections at all, in order to
4426 reserve the entire global offset table. When
4427 generating embedded PIC code, we use the .lit8
4428 section but not the .lit4 section (we can do .lit4
4429 inline easily; we need to put .lit8 somewhere in
4430 the data segment, and using .lit8 permits the
4431 linker to eventually combine identical .lit8
4434 f64
= *args
== 'F' || *args
== 'L';
4436 save_in
= input_line_pointer
;
4437 input_line_pointer
= s
;
4438 err
= md_atof (f64
? 'd' : 'f', (char *) temp
, &len
);
4440 s
= input_line_pointer
;
4441 input_line_pointer
= save_in
;
4442 if (err
!= NULL
&& *err
!= '\0')
4444 as_bad ("Bad floating point constant: %s", err
);
4445 memset (temp
, '\0', sizeof temp
);
4446 length
= f64
? 8 : 4;
4449 assert (length
== (f64
? 8 : 4));
4452 || (mips_pic
!= NO_PIC
&& *args
== 'l'))
4454 imm_expr
.X_op
= O_constant
;
4455 if (byte_order
== LITTLE_ENDIAN
)
4456 imm_expr
.X_add_number
=
4457 (((((((int) temp
[3] << 8)
4462 imm_expr
.X_add_number
=
4463 (((((((int) temp
[0] << 8)
4470 const char *newname
;
4473 /* Switch to the right section. */
4475 subseg
= now_subseg
;
4478 default: /* unused default case avoids warnings. */
4480 newname
= (mips_pic
!= SVR4_PIC
? ".lit8" : ".rdata");
4486 assert (mips_pic
== NO_PIC
);
4490 new_seg
= subseg_new (newname
, (subsegT
) 0);
4492 bfd_set_section_alignment (stdoutput
, new_seg
, 4);
4495 as_bad ("Can't use floating point insn in this section");
4497 /* Set the argument to the current address in the
4499 offset_expr
.X_op
= O_symbol
;
4500 offset_expr
.X_add_symbol
=
4501 symbol_new ("L0\001", now_seg
,
4502 (valueT
) frag_now_fix (), frag_now
);
4503 offset_expr
.X_add_number
= 0;
4505 /* Put the floating point number into the section. */
4506 p
= frag_more ((int) length
);
4507 memcpy (p
, temp
, length
);
4509 /* Switch back to the original section. */
4510 subseg_set (seg
, subseg
);
4515 case 'i': /* 16 bit unsigned immediate */
4516 case 'j': /* 16 bit signed immediate */
4517 imm_reloc
= BFD_RELOC_LO16
;
4518 c
= my_getSmallExpression (&imm_expr
, s
);
4523 if (imm_expr
.X_op
== O_constant
)
4524 imm_expr
.X_add_number
=
4525 (imm_expr
.X_add_number
>> 16) & 0xffff;
4527 imm_reloc
= BFD_RELOC_HI16_S
;
4529 imm_reloc
= BFD_RELOC_HI16
;
4533 check_absolute_expr (ip
, &imm_expr
);
4536 if (imm_expr
.X_add_number
< 0
4537 || imm_expr
.X_add_number
>= 0x10000)
4539 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
4540 !strcmp (insn
->name
, insn
[1].name
))
4542 as_bad ("16 bit expression not in range 0..65535");
4550 /* The upper bound should be 0x8000, but
4551 unfortunately the MIPS assembler accepts numbers
4552 from 0x8000 to 0xffff and sign extends them, and
4553 we want to be compatible. We only permit this
4554 extended range for an instruction which does not
4555 provide any further alternates, since those
4556 alternates may handle other cases. People should
4557 use the numbers they mean, rather than relying on
4558 a mysterious sign extension. */
4559 more
= (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
4560 strcmp (insn
->name
, insn
[1].name
) == 0);
4565 if (imm_expr
.X_add_number
< -0x8000 ||
4566 imm_expr
.X_add_number
>= max
)
4570 as_bad ("16 bit expression not in range -32768..32767");
4576 case 'o': /* 16 bit offset */
4577 c
= my_getSmallExpression (&offset_expr
, s
);
4579 /* If this value won't fit into a 16 bit offset, then go
4580 find a macro that will generate the 32 bit offset
4581 code pattern. As a special hack, we accept the
4582 difference of two local symbols as a constant. This
4583 is required to suppose embedded PIC switches, which
4584 use an instruction which looks like
4585 lw $4,$L12-$LS12($4)
4586 The problem with handling this in a more general
4587 fashion is that the macro function doesn't expect to
4588 see anything which can be handled in a single
4589 constant instruction. */
4590 if ((offset_expr
.X_op
!= O_constant
4591 || offset_expr
.X_add_number
>= 0x8000
4592 || offset_expr
.X_add_number
< -0x8000)
4593 && (mips_pic
!= EMBEDDED_PIC
4594 || offset_expr
.X_op
!= O_subtract
4595 || ! S_IS_LOCAL (offset_expr
.X_add_symbol
)
4596 || ! S_IS_LOCAL (offset_expr
.X_op_symbol
)))
4599 offset_reloc
= BFD_RELOC_LO16
;
4600 if (c
== 'h' || c
== 'H')
4602 assert (offset_expr
.X_op
== O_constant
);
4603 offset_expr
.X_add_number
=
4604 (offset_expr
.X_add_number
>> 16) & 0xffff;
4609 case 'p': /* pc relative offset */
4610 offset_reloc
= BFD_RELOC_16_PCREL_S2
;
4611 my_getExpression (&offset_expr
, s
);
4615 case 'u': /* upper 16 bits */
4616 c
= my_getSmallExpression (&imm_expr
, s
);
4617 if (imm_expr
.X_op
!= O_constant
4618 || imm_expr
.X_add_number
< 0
4619 || imm_expr
.X_add_number
>= 0x10000)
4620 as_bad ("lui expression not in range 0..65535");
4621 imm_reloc
= BFD_RELOC_LO16
;
4626 if (imm_expr
.X_op
== O_constant
)
4627 imm_expr
.X_add_number
=
4628 (imm_expr
.X_add_number
>> 16) & 0xffff;
4630 imm_reloc
= BFD_RELOC_HI16_S
;
4632 imm_reloc
= BFD_RELOC_HI16
;
4638 case 'a': /* 26 bit address */
4639 my_getExpression (&offset_expr
, s
);
4641 offset_reloc
= BFD_RELOC_MIPS_JMP
;
4645 fprintf (stderr
, "bad char = '%c'\n", *args
);
4650 /* Args don't match. */
4651 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
4652 !strcmp (insn
->name
, insn
[1].name
))
4658 insn_error
= "ERROR: Illegal operands";
4667 my_getSmallExpression (ep
, str
)
4678 ((str
[1] == 'h' && str
[2] == 'i')
4679 || (str
[1] == 'H' && str
[2] == 'I')
4680 || (str
[1] == 'l' && str
[2] == 'o'))
4692 * A small expression may be followed by a base register.
4693 * Scan to the end of this operand, and then back over a possible
4694 * base register. Then scan the small expression up to that
4695 * point. (Based on code in sparc.c...)
4697 for (sp
= str
; *sp
&& *sp
!= ','; sp
++)
4699 if (sp
- 4 >= str
&& sp
[-1] == RP
)
4701 if (isdigit (sp
[-2]))
4703 for (sp
-= 3; sp
>= str
&& isdigit (*sp
); sp
--)
4705 if (*sp
== '$' && sp
> str
&& sp
[-1] == LP
)
4711 else if (sp
- 5 >= str
4714 && ((sp
[-3] == 'f' && sp
[-2] == 'p')
4715 || (sp
[-3] == 's' && sp
[-2] == 'p')
4716 || (sp
[-3] == 'g' && sp
[-2] == 'p')
4717 || (sp
[-3] == 'a' && sp
[-2] == 't')))
4723 /* no expression means zero offset */
4726 /* %xx(reg) is an error */
4727 ep
->X_op
= O_absent
;
4732 ep
->X_op
= O_constant
;
4735 ep
->X_add_symbol
= NULL
;
4736 ep
->X_op_symbol
= NULL
;
4737 ep
->X_add_number
= 0;
4742 my_getExpression (ep
, str
);
4749 my_getExpression (ep
, str
);
4750 return c
; /* => %hi or %lo encountered */
4754 my_getExpression (ep
, str
)
4760 save_in
= input_line_pointer
;
4761 input_line_pointer
= str
;
4763 expr_end
= input_line_pointer
;
4764 input_line_pointer
= save_in
;
4767 /* Turn a string in input_line_pointer into a floating point constant
4768 of type type, and store the appropriate bytes in *litP. The number
4769 of LITTLENUMS emitted is stored in *sizeP . An error message is
4770 returned, or NULL on OK. */
4773 md_atof (type
, litP
, sizeP
)
4779 LITTLENUM_TYPE words
[4];
4795 return "bad call to md_atof";
4798 t
= atof_ieee (input_line_pointer
, type
, words
);
4800 input_line_pointer
= t
;
4804 if (byte_order
== LITTLE_ENDIAN
)
4806 for (i
= prec
- 1; i
>= 0; i
--)
4808 md_number_to_chars (litP
, (valueT
) words
[i
], 2);
4814 for (i
= 0; i
< prec
; i
++)
4816 md_number_to_chars (litP
, (valueT
) words
[i
], 2);
4825 md_number_to_chars (buf
, val
, n
)
4833 number_to_chars_littleendian (buf
, val
, n
);
4837 number_to_chars_bigendian (buf
, val
, n
);
4846 md_parse_option (argP
, cntP
, vecP
)
4851 /* Accept -nocpp but ignore it. */
4852 if (strcmp (*argP
, "nocpp") == 0)
4858 if (strcmp (*argP
, "EL") == 0
4859 || strcmp (*argP
, "EB") == 0)
4861 if ((*argP
)[1] == 'B')
4862 byte_order
= BIG_ENDIAN
;
4864 byte_order
= LITTLE_ENDIAN
;
4867 if ((*argP
)[1] == 'B')
4868 mips_target_format
= "a.out-mips-big";
4870 mips_target_format
= "a.out-mips-little";
4873 if ((*argP
)[1] == 'B')
4874 mips_target_format
= "ecoff-bigmips";
4876 mips_target_format
= "ecoff-littlemips";
4879 if ((*argP
)[1] == 'B')
4880 mips_target_format
= "elf32-bigmips";
4882 mips_target_format
= "elf32-littlemips";
4885 /* FIXME: This breaks -L -EL. */
4893 if ((*argP
)[1] == '0')
4902 if ((*argP
)[1] == '\0' || (*argP
)[1] == '2')
4907 if (strncmp (*argP
, "mips", 4) == 0)
4909 mips_isa
= atol (*argP
+ 4);
4912 else if (mips_isa
< 1 || mips_isa
> 3)
4914 as_bad ("-mips%d not supported", mips_isa
);
4921 if (strncmp (*argP
, "mcpu=", 5) == 0)
4925 /* Identify the processor type */
4927 if (strcmp (p
, "default") == 0
4928 || strcmp (p
, "DEFAULT") == 0)
4932 if (*p
== 'r' || *p
== 'R')
4939 if (strcmp (p
, "2000") == 0
4940 || strcmp (p
, "2k") == 0
4941 || strcmp (p
, "2K") == 0)
4946 if (strcmp (p
, "3000") == 0
4947 || strcmp (p
, "3k") == 0
4948 || strcmp (p
, "3K") == 0)
4953 if (strcmp (p
, "4000") == 0
4954 || strcmp (p
, "4k") == 0
4955 || strcmp (p
, "4K") == 0)
4960 if (strcmp (p
, "6000") == 0
4961 || strcmp (p
, "6k") == 0
4962 || strcmp (p
, "6K") == 0)
4969 as_bad ("bad value (%s) for -mcpu= switch", *argP
+ 5);
4978 /* Argument -membedded-pic means to use EMBEDDED_PIC. */
4979 if (strcmp (*argP
, "membedded-pic") == 0)
4981 mips_pic
= EMBEDDED_PIC
;
4984 as_warn ("-G may not be used with embedded PIC code");
4985 g_switch_value
= 0x7fffffff;
4992 /* When generating ELF code, we permit -KPIC and -call_shared to
4993 select SVR4_PIC, and -non_shared to select no PIC. This is
4994 intended to be compatible with Irix 5. */
4995 if (strcmp (*argP
, "KPIC") == 0
4996 || strcmp (*argP
, "call_shared") == 0)
4998 mips_pic
= SVR4_PIC
;
4999 if (g_switch_seen
&& g_switch_value
!= 0)
5000 as_warn ("-G may not be used with SVR4 PIC code");
5005 else if (strcmp (*argP
, "non_shared") == 0)
5011 #endif /* OBJ_ELF */
5016 if (mips_pic
== SVR4_PIC
|| mips_pic
== EMBEDDED_PIC
)
5017 as_warn ("-G may not be used with SVR4 or embedded PIC code");
5018 else if ((*argP
)[1] != '\0')
5019 g_switch_value
= atoi (*argP
+ 1);
5022 **vecP
= (char *) NULL
;
5025 g_switch_value
= atoi (**vecP
);
5028 as_warn ("Number expected after -G");
5035 return 1; /* pretend you parsed the character */
5038 /* Handle a long option name. */
5041 mips_parse_long_option (arg
)
5044 if (strcmp (arg
, "--trap") == 0
5045 || strcmp (arg
, "--no-break") == 0)
5050 else if (strcmp (arg
, "--no-trap") == 0
5051 || strcmp (arg
, "--break") == 0)
5061 md_pcrel_from (fixP
)
5065 if (fixP
->fx_addsy
!= (symbolS
*) NULL
5066 && ! S_IS_DEFINED (fixP
->fx_addsy
))
5068 /* This makes a branch to an undefined symbol be a branch to the
5069 current location. */
5074 /* return the address of the delay slot */
5075 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
5078 /* This is called by emit_expr via TC_CONS_FIX_NEW when creating a
5079 reloc for a cons. We could use the definition there, except that
5080 we want to handle 64 bit relocs specially. */
5083 cons_fix_new_mips (frag
, where
, nbytes
, exp
)
5086 unsigned int nbytes
;
5089 /* If we are assembling in 32 bit mode, turn an 8 byte reloc into a
5091 FIXME: There is no way to select anything but 32 bit mode right
5095 if (byte_order
== BIG_ENDIAN
)
5100 if (nbytes
!= 2 && nbytes
!= 4)
5101 as_bad ("Unsupported reloc size %d", nbytes
);
5103 fix_new_exp (frag_now
, where
, (int) nbytes
, exp
, 0,
5104 nbytes
== 2 ? BFD_RELOC_16
: BFD_RELOC_32
);
5107 /* When generating embedded PIC code we need to use a special
5108 relocation to represent the difference of two symbols in the .text
5109 section (switch tables use a difference of this sort). See
5110 include/coff/mips.h for details. This macro checks whether this
5111 fixup requires the special reloc. */
5112 #define SWITCH_TABLE(fixp) \
5113 ((fixp)->fx_r_type == BFD_RELOC_32 \
5114 && (fixp)->fx_addsy != NULL \
5115 && (fixp)->fx_subsy != NULL \
5116 && S_GET_SEGMENT ((fixp)->fx_addsy) == text_section \
5117 && S_GET_SEGMENT ((fixp)->fx_subsy) == text_section)
5119 /* When generating embedded PIC code we must keep all PC relative
5120 relocations, in case the linker has to relax a call. We also need
5121 to keep relocations for switch table entries. */
5125 mips_force_relocation (fixp
)
5128 return (mips_pic
== EMBEDDED_PIC
5130 || SWITCH_TABLE (fixp
)
5131 || fixp
->fx_r_type
== BFD_RELOC_PCREL_HI16_S
5132 || fixp
->fx_r_type
== BFD_RELOC_PCREL_LO16
));
5135 /* Apply a fixup to the object file. */
5138 md_apply_fix (fixP
, valueP
)
5145 assert (fixP
->fx_size
== 4);
5148 fixP
->fx_addnumber
= value
; /* Remember value for tc_gen_reloc */
5150 if (fixP
->fx_addsy
== NULL
&& ! fixP
->fx_pcrel
)
5153 switch (fixP
->fx_r_type
)
5155 case BFD_RELOC_MIPS_JMP
:
5156 case BFD_RELOC_HI16
:
5157 case BFD_RELOC_HI16_S
:
5158 case BFD_RELOC_MIPS_GPREL
:
5159 case BFD_RELOC_MIPS_LITERAL
:
5160 case BFD_RELOC_MIPS_CALL16
:
5161 case BFD_RELOC_MIPS_GOT16
:
5162 case BFD_RELOC_MIPS_GPREL32
:
5164 as_bad ("Invalid PC relative reloc");
5165 /* Nothing needed to do. The value comes from the reloc entry */
5168 case BFD_RELOC_PCREL_HI16_S
:
5169 /* The addend for this is tricky if it is internal, so we just
5170 do everything here rather than in bfd_perform_relocation. */
5171 if ((fixP
->fx_addsy
->bsym
->flags
& BSF_SECTION_SYM
) == 0)
5173 /* For an external symbol adjust by the address to make it
5174 pcrel_offset. We use the address of the RELLO reloc
5175 which follows this one. */
5176 value
+= (fixP
->fx_next
->fx_frag
->fr_address
5177 + fixP
->fx_next
->fx_where
);
5182 buf
= fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
5183 if (byte_order
== BIG_ENDIAN
)
5185 md_number_to_chars (buf
, value
, 2);
5188 case BFD_RELOC_PCREL_LO16
:
5189 /* The addend for this is tricky if it is internal, so we just
5190 do everything here rather than in bfd_perform_relocation. */
5191 if ((fixP
->fx_addsy
->bsym
->flags
& BSF_SECTION_SYM
) == 0)
5192 value
+= fixP
->fx_frag
->fr_address
+ fixP
->fx_where
;
5193 buf
= fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
5194 if (byte_order
== BIG_ENDIAN
)
5196 md_number_to_chars (buf
, value
, 2);
5200 /* If we are deleting this reloc entry, we must fill in the
5201 value now. This can happen if we have a .word which is not
5202 resolved when it appears but is later defined. We also need
5203 to fill in the value if this is an embedded PIC switch table
5206 || (mips_pic
== EMBEDDED_PIC
&& SWITCH_TABLE (fixP
)))
5207 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
,
5211 case BFD_RELOC_LO16
:
5212 /* When handling an embedded PIC switch statement, we can wind
5213 up deleting a LO16 reloc. See the 'o' case in mips_ip. */
5216 if (value
< -0x8000 || value
> 0x7fff)
5217 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
5218 "relocation overflow");
5219 buf
= fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
5220 if (byte_order
== BIG_ENDIAN
)
5222 md_number_to_chars (buf
, value
, 2);
5226 case BFD_RELOC_16_PCREL_S2
:
5228 * We need to save the bits in the instruction since fixup_segment()
5229 * might be deleting the relocation entry (i.e., a branch within
5230 * the current segment).
5233 as_warn ("Branch to odd address (%lx)", value
);
5235 if ((value
& ~0xFFFF) && (value
& ~0xFFFF) != (-1 & ~0xFFFF))
5236 as_bad ("Relocation overflow");
5238 /* update old instruction data */
5239 buf
= (unsigned char *) (fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
);
5243 insn
= (buf
[3] << 24) | (buf
[2] << 16) | (buf
[1] << 8) | buf
[0];
5247 insn
= (buf
[0] << 24) | (buf
[1] << 16) | (buf
[2] << 8) | buf
[3];
5254 insn
|= value
& 0xFFFF;
5255 md_number_to_chars ((char *) buf
, (valueT
) insn
, 4);
5270 const struct mips_opcode
*p
;
5271 int treg
, sreg
, dreg
, shamt
;
5276 for (i
= 0; i
< NUMOPCODES
; ++i
)
5278 p
= &mips_opcodes
[i
];
5279 if (((oc
& p
->mask
) == p
->match
) && (p
->pinfo
!= INSN_MACRO
))
5281 printf ("%08lx %s\t", oc
, p
->name
);
5282 treg
= (oc
>> 16) & 0x1f;
5283 sreg
= (oc
>> 21) & 0x1f;
5284 dreg
= (oc
>> 11) & 0x1f;
5285 shamt
= (oc
>> 6) & 0x1f;
5287 for (args
= p
->args
;; ++args
)
5298 printf ("%c", *args
);
5302 assert (treg
== sreg
);
5303 printf ("$%d,$%d", treg
, sreg
);
5308 printf ("$%d", dreg
);
5313 printf ("$%d", treg
);
5317 printf ("0x%x", treg
);
5322 printf ("$%d", sreg
);
5326 printf ("0x%08lx", oc
& 0x1ffffff);
5338 printf ("$%d", shamt
);
5349 printf ("%08lx UNDEFINED\n", oc
);
5360 name
= input_line_pointer
;
5361 c
= get_symbol_end ();
5362 p
= (symbolS
*) symbol_find_or_make (name
);
5363 *input_line_pointer
= c
;
5367 /* Align the current frag to a given power of two. The MIPS assembler
5368 also automatically adjusts any preceding label. */
5371 mips_align (to
, fill
, label
)
5376 mips_emit_delays ();
5377 frag_align (to
, fill
);
5378 record_alignment (now_seg
, to
);
5381 assert (S_GET_SEGMENT (label
) == now_seg
);
5382 label
->sy_frag
= frag_now
;
5383 S_SET_VALUE (label
, (valueT
) frag_now_fix ());
5387 /* Align to a given power of two. .align 0 turns off the automatic
5388 alignment used by the data creating pseudo-ops. */
5395 register long temp_fill
;
5396 long max_alignment
= 15;
5400 o Note that the assembler pulls down any immediately preceeding label
5401 to the aligned address.
5402 o It's not documented but auto alignment is reinstated by
5403 a .align pseudo instruction.
5404 o Note also that after auto alignment is turned off the mips assembler
5405 issues an error on attempt to assemble an improperly aligned data item.
5410 temp
= get_absolute_expression ();
5411 if (temp
> max_alignment
)
5412 as_bad ("Alignment too large: %d. assumed.", temp
= max_alignment
);
5415 as_warn ("Alignment negative: 0 assumed.");
5418 if (*input_line_pointer
== ',')
5420 input_line_pointer
++;
5421 temp_fill
= get_absolute_expression ();
5428 mips_align (temp
, (int) temp_fill
, insn_label
);
5435 demand_empty_rest_of_line ();
5438 /* Handle .ascii and .asciiz. This just calls stringer and forgets
5439 that there was a previous instruction. */
5442 s_stringer (append_zero
)
5445 mips_emit_delays ();
5447 stringer (append_zero
);
5458 /* When generating embedded PIC code, we only use the .text, .lit8,
5459 .sdata and .sbss sections. We change the .data and .rdata
5460 pseudo-ops to use .sdata. */
5461 if (mips_pic
== EMBEDDED_PIC
5462 && (sec
== 'd' || sec
== 'r'))
5465 mips_emit_delays ();
5475 subseg_set (bss_section
, (subsegT
) get_absolute_expression ());
5476 demand_empty_rest_of_line ();
5481 subseg_new (".rdata", (subsegT
) get_absolute_expression ());
5482 demand_empty_rest_of_line ();
5484 #else /* ! defined (OBJ_ECOFF) */
5486 seg
= subseg_new (".rodata", (subsegT
) get_absolute_expression ());
5487 bfd_set_section_flags (stdoutput
, seg
,
5493 bfd_set_section_alignment (stdoutput
, seg
, 4);
5494 demand_empty_rest_of_line ();
5496 #else /* ! defined (OBJ_ELF) */
5499 #endif /* ! defined (OBJ_ELF) */
5500 #endif /* ! defined (OBJ_ECOFF) */
5504 seg
= subseg_new (".sdata", (subsegT
) get_absolute_expression ());
5506 bfd_set_section_flags (stdoutput
, seg
,
5507 SEC_ALLOC
| SEC_LOAD
| SEC_RELOC
| SEC_DATA
);
5508 bfd_set_section_alignment (stdoutput
, seg
, 4);
5510 demand_empty_rest_of_line ();
5512 #else /* ! defined (GPOPT) */
5513 as_bad ("Global pointers not supported; recompile -G 0");
5514 demand_empty_rest_of_line ();
5516 #endif /* ! defined (GPOPT) */
5529 mips_emit_delays ();
5530 if (log_size
> 0 && auto_align
)
5531 mips_align (log_size
, 0, label
);
5533 cons (1 << log_size
);
5540 as_fatal ("Encountered `.err', aborting assembly");
5550 symbolP
= get_symbol ();
5551 if (*input_line_pointer
== ',')
5552 input_line_pointer
++;
5553 size
= get_absolute_expression ();
5554 S_SET_EXTERNAL (symbolP
);
5556 #ifdef ECOFF_DEBUGGING
5557 symbolP
->ecoff_extern_size
= size
;
5569 mips_emit_delays ();
5573 mips_align (3, 0, label
);
5575 mips_align (2, 0, label
);
5589 opt
= input_line_pointer
;
5590 c
= get_symbol_end ();
5594 /* FIXME: What does this mean? */
5596 else if (strncmp (opt
, "pic", 3) == 0)
5604 mips_pic
= SVR4_PIC
;
5606 as_bad (".option pic%d not supported", i
);
5608 if (mips_pic
== SVR4_PIC
)
5610 if (g_switch_seen
&& g_switch_value
!= 0)
5611 as_warn ("-G may not be used with SVR4 PIC code");
5613 bfd_set_gp_size (stdoutput
, 0);
5617 as_warn ("Unrecognized option \"%s\"", opt
);
5619 *input_line_pointer
= c
;
5620 demand_empty_rest_of_line ();
5627 char *name
= input_line_pointer
, ch
;
5629 while (!is_end_of_line
[(unsigned char) *input_line_pointer
])
5630 input_line_pointer
++;
5631 ch
= *input_line_pointer
;
5632 *input_line_pointer
= '\0';
5634 if (strcmp (name
, "reorder") == 0)
5638 prev_insn_unreordered
= 1;
5639 prev_prev_insn_unreordered
= 1;
5643 else if (strcmp (name
, "noreorder") == 0)
5645 mips_emit_delays ();
5647 mips_any_noreorder
= 1;
5649 else if (strcmp (name
, "at") == 0)
5653 else if (strcmp (name
, "noat") == 0)
5657 else if (strcmp (name
, "macro") == 0)
5659 mips_warn_about_macros
= 0;
5661 else if (strcmp (name
, "nomacro") == 0)
5663 if (mips_noreorder
== 0)
5664 as_bad ("`noreorder' must be set before `nomacro'");
5665 mips_warn_about_macros
= 1;
5667 else if (strcmp (name
, "move") == 0 || strcmp (name
, "novolatile") == 0)
5671 else if (strcmp (name
, "nomove") == 0 || strcmp (name
, "volatile") == 0)
5675 else if (strcmp (name
, "bopt") == 0)
5679 else if (strcmp (name
, "nobopt") == 0)
5683 else if (strncmp (name
, "mips", 4) == 0)
5687 /* Permit the user to change the ISA on the fly. Needless to
5688 say, misuse can cause serious problems. */
5689 isa
= atoi (name
+ 4);
5691 mips_isa
= file_mips_isa
;
5692 else if (isa
< 1 || isa
> 3)
5693 as_bad ("unknown ISA level");
5699 as_warn ("Tried to set unrecognized symbol: %s\n", name
);
5701 *input_line_pointer
= ch
;
5702 demand_empty_rest_of_line ();
5705 /* The same as the usual .space directive, except that we have to
5706 forget about any previous instruction. */
5709 s_mips_space (param
)
5712 mips_emit_delays ();
5717 /* Handle the .abicalls pseudo-op. I believe this is equivalent to
5718 .option pic2. It means to generate SVR4 PIC calls. */
5724 mips_pic
= SVR4_PIC
;
5725 if (g_switch_seen
&& g_switch_value
!= 0)
5726 as_warn ("-G may not be used with SVR4 PIC code");
5728 bfd_set_gp_size (stdoutput
, 0);
5729 demand_empty_rest_of_line ();
5732 /* Handle the .cpload pseudo-op. This is used when generating SVR4
5733 PIC code. It sets the $gp register for the function based on the
5734 function address, which is in the register named in the argument.
5735 This uses a relocation against _gp_disp, which is handled specially
5736 by the linker. The result is:
5737 lui $gp,%hi(_gp_disp)
5738 addiu $gp,$gp,%lo(_gp_disp)
5739 addu $gp,$gp,.cpload argument
5740 The .cpload argument is normally $25 == $t9. */
5749 /* If we are not generating SVR4 PIC code, .cpload is ignored. */
5750 if (mips_pic
!= SVR4_PIC
)
5756 /* .cpload should be a in .set noreorder section. */
5757 if (mips_noreorder
== 0)
5758 as_warn (".cpload not in noreorder section");
5761 ex
.X_add_symbol
= symbol_find_or_make ("_gp_disp");
5762 ex
.X_op_symbol
= NULL
;
5763 ex
.X_add_number
= 0;
5765 macro_build_lui ((char *) NULL
, &icnt
, &ex
, GP
);
5766 macro_build ((char *) NULL
, &icnt
, &ex
, "addiu", "t,r,j", GP
, GP
,
5767 (int) BFD_RELOC_LO16
);
5769 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "addu", "d,v,t",
5770 GP
, GP
, tc_get_register (0));
5772 demand_empty_rest_of_line ();
5775 /* Handle the .cprestore pseudo-op. This stores $gp into a given
5776 offset from $sp. The offset is remembered, and after making a PIC
5777 call $gp is restored from that location. */
5780 s_cprestore (ignore
)
5786 /* If we are not generating SVR4 PIC code, .cprestore is ignored. */
5787 if (mips_pic
!= SVR4_PIC
)
5793 mips_cprestore_offset
= get_absolute_expression ();
5795 ex
.X_op
= O_constant
;
5796 ex
.X_add_symbol
= NULL
;
5797 ex
.X_op_symbol
= NULL
;
5798 ex
.X_add_number
= mips_cprestore_offset
;
5800 macro_build ((char *) NULL
, &icnt
, &ex
,
5801 mips_isa
< 3 ? "sw" : "sd",
5802 "t,o(b)", GP
, (int) BFD_RELOC_LO16
, SP
);
5804 demand_empty_rest_of_line ();
5807 /* Handle the .gpword pseudo-op. This is used when generating PIC
5808 code. It generates a 32 bit GP relative reloc. */
5818 /* When not generating PIC code, this is treated as .word. */
5819 if (mips_pic
!= SVR4_PIC
)
5826 mips_emit_delays ();
5828 mips_align (2, 0, label
);
5833 if (ex
.X_op
!= O_symbol
|| ex
.X_add_number
!= 0)
5835 as_bad ("Unsupported use of .gpword");
5836 ignore_rest_of_line ();
5840 md_number_to_chars (p
, (valueT
) 0, 4);
5841 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 4, &ex
, 0,
5842 BFD_RELOC_MIPS_GPREL32
);
5844 demand_empty_rest_of_line ();
5847 /* Handle the .cpadd pseudo-op. This is used when dealing with switch
5848 tables in SVR4 PIC code. */
5857 /* This is ignored when not generating SVR4 PIC code. */
5858 if (mips_pic
!= SVR4_PIC
)
5864 /* Add $gp to the register named as an argument. */
5865 reg
= tc_get_register (0);
5866 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5867 mips_isa
< 3 ? "addu" : "daddu",
5868 "d,v,t", reg
, reg
, GP
);
5870 demand_empty_rest_of_line ();
5873 /* Parse a register string into a number. Called from the ECOFF code
5874 to parse .frame. The argument is non-zero if this is the frame
5875 register, so that we can record it in mips_frame_reg. */
5878 tc_get_register (frame
)
5884 if (*input_line_pointer
++ != '$')
5886 as_warn ("expected `$'");
5889 else if (isdigit ((unsigned char) *input_line_pointer
))
5891 reg
= get_absolute_expression ();
5892 if (reg
< 0 || reg
>= 32)
5894 as_warn ("Bad register number");
5900 if (strncmp (input_line_pointer
, "fp", 2) == 0)
5902 else if (strncmp (input_line_pointer
, "sp", 2) == 0)
5904 else if (strncmp (input_line_pointer
, "gp", 2) == 0)
5906 else if (strncmp (input_line_pointer
, "at", 2) == 0)
5910 as_warn ("Unrecognized register name");
5913 input_line_pointer
+= 2;
5916 mips_frame_reg
= reg
!= 0 ? reg
: SP
;
5921 md_section_align (seg
, addr
)
5925 int align
= bfd_get_section_alignment (stdoutput
, seg
);
5927 return ((addr
+ (1 << align
) - 1) & (-1 << align
));
5930 /* Estimate the size of a frag before relaxing. We are not really
5931 relaxing here, and the final size is encoded in the subtype
5936 md_estimate_size_before_relax (fragp
, segtype
)
5942 if (mips_pic
== NO_PIC
)
5945 const char *symname
;
5947 /* Find out whether this symbol can be referenced off the GP
5948 register. It can be if it is smaller than the -G size or if
5949 it is in the .sdata or .sbss section. Certain symbols can
5950 not be referenced off the GP, although it appears as though
5952 symname
= S_GET_NAME (fragp
->fr_symbol
);
5953 if (symname
!= (const char *) NULL
5954 && (strcmp (symname
, "eprol") == 0
5955 || strcmp (symname
, "etext") == 0
5956 || strcmp (symname
, "_gp") == 0
5957 || strcmp (symname
, "edata") == 0
5958 || strcmp (symname
, "_fbss") == 0
5959 || strcmp (symname
, "_fdata") == 0
5960 || strcmp (symname
, "_ftext") == 0
5961 || strcmp (symname
, "end") == 0
5962 || strcmp (symname
, "_gp_disp") == 0))
5964 else if (! S_IS_DEFINED (fragp
->fr_symbol
)
5965 && ((fragp
->fr_symbol
->ecoff_extern_size
!= 0
5966 && fragp
->fr_symbol
->ecoff_extern_size
<= g_switch_value
)
5967 || (S_GET_VALUE (fragp
->fr_symbol
) != 0
5968 && S_GET_VALUE (fragp
->fr_symbol
) <= g_switch_value
)))
5972 const char *segname
;
5974 segname
= segment_name (S_GET_SEGMENT (fragp
->fr_symbol
));
5975 assert (strcmp (segname
, ".lit8") != 0
5976 && strcmp (segname
, ".lit4") != 0);
5977 change
= (strcmp (segname
, ".sdata") != 0
5978 && strcmp (segname
, ".sbss") != 0);
5980 #else /* ! defined (GPOPT) */
5981 /* We are not optimizing for the GP register. */
5983 #endif /* ! defined (GPOPT) */
5985 else if (mips_pic
== SVR4_PIC
)
5987 asection
*symsec
= fragp
->fr_symbol
->bsym
->section
;
5989 /* This must duplicate the test in adjust_reloc_syms. */
5990 change
= (symsec
!= &bfd_und_section
5991 && symsec
!= &bfd_abs_section
5992 && ! bfd_is_com_section (symsec
));
5999 /* Record the offset to the first reloc in the fr_opcode field.
6000 This lets md_convert_frag and tc_gen_reloc know that the code
6001 must be expanded. */
6002 fragp
->fr_opcode
= (fragp
->fr_literal
6004 - RELAX_OLD (fragp
->fr_subtype
)
6005 + RELAX_RELOC1 (fragp
->fr_subtype
));
6006 /* FIXME: This really needs as_warn_where. */
6007 if (RELAX_WARN (fragp
->fr_subtype
))
6008 as_warn ("AT used after \".set noat\" or macro used after \".set nomacro\"");
6014 return RELAX_NEW (fragp
->fr_subtype
) - RELAX_OLD (fragp
->fr_subtype
);
6017 /* Translate internal representation of relocation info to BFD target
6021 tc_gen_reloc (section
, fixp
)
6025 static arelent
*retval
[4];
6028 reloc
= retval
[0] = (arelent
*) xmalloc (sizeof (arelent
));
6031 reloc
->sym_ptr_ptr
= &fixp
->fx_addsy
->bsym
;
6032 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
6034 if (mips_pic
== EMBEDDED_PIC
6035 && SWITCH_TABLE (fixp
))
6037 /* For a switch table entry we use a special reloc. The addend
6038 is actually the difference between the reloc address and the
6040 reloc
->addend
= reloc
->address
- S_GET_VALUE (fixp
->fx_subsy
);
6042 as_fatal ("Double check fx_r_type in tc-mips.c:tc_gen_reloc");
6044 fixp
->fx_r_type
= BFD_RELOC_GPREL32
;
6046 else if (fixp
->fx_r_type
== BFD_RELOC_PCREL_LO16
)
6048 /* We use a special addend for an internal RELLO reloc. */
6049 if (fixp
->fx_addsy
->bsym
->flags
& BSF_SECTION_SYM
)
6050 reloc
->addend
= reloc
->address
- S_GET_VALUE (fixp
->fx_subsy
);
6052 reloc
->addend
= fixp
->fx_addnumber
+ reloc
->address
;
6054 else if (fixp
->fx_r_type
== BFD_RELOC_PCREL_HI16_S
)
6056 assert (fixp
->fx_next
!= NULL
6057 && fixp
->fx_next
->fx_r_type
== BFD_RELOC_PCREL_LO16
);
6058 /* We use a special addend for an internal RELHI reloc. The
6059 reloc is relative to the RELLO; adjust the addend
6061 if (fixp
->fx_addsy
->bsym
->flags
& BSF_SECTION_SYM
)
6062 reloc
->addend
= (fixp
->fx_next
->fx_frag
->fr_address
6063 + fixp
->fx_next
->fx_where
6064 - S_GET_VALUE (fixp
->fx_subsy
));
6066 reloc
->addend
= (fixp
->fx_addnumber
6067 + fixp
->fx_next
->fx_frag
->fr_address
6068 + fixp
->fx_next
->fx_where
);
6070 else if (fixp
->fx_pcrel
== 0)
6071 reloc
->addend
= fixp
->fx_addnumber
;
6075 /* A gruesome hack which is a result of the gruesome gas reloc
6077 reloc
->addend
= reloc
->address
;
6079 reloc
->addend
= -reloc
->address
;
6083 /* If this is a variant frag, we may need to adjust the existing
6084 reloc and generate a new one. */
6085 if (fixp
->fx_frag
->fr_opcode
!= NULL
6086 && (fixp
->fx_r_type
== BFD_RELOC_MIPS_GPREL
6087 || fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT16
6088 || fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL16
))
6092 /* If this is not the last reloc in this frag, then we have two
6093 GPREL relocs, both of which are being replaced. Let the
6094 second one handle all of them. */
6095 if (fixp
->fx_next
!= NULL
6096 && fixp
->fx_frag
== fixp
->fx_next
->fx_frag
)
6098 assert (fixp
->fx_r_type
== BFD_RELOC_MIPS_GPREL
6099 && fixp
->fx_next
->fx_r_type
== BFD_RELOC_MIPS_GPREL
);
6104 fixp
->fx_where
= fixp
->fx_frag
->fr_opcode
- fixp
->fx_frag
->fr_literal
;
6105 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
6106 reloc2
= retval
[1] = (arelent
*) xmalloc (sizeof (arelent
));
6108 reloc2
->sym_ptr_ptr
= &fixp
->fx_addsy
->bsym
;
6109 reloc2
->address
= (reloc
->address
6110 + (RELAX_RELOC2 (fixp
->fx_frag
->fr_subtype
)
6111 - RELAX_RELOC1 (fixp
->fx_frag
->fr_subtype
)));
6112 reloc2
->addend
= fixp
->fx_addnumber
;
6113 reloc2
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_LO16
);
6114 assert (reloc2
->howto
!= NULL
);
6116 if (RELAX_RELOC3 (fixp
->fx_frag
->fr_subtype
))
6120 reloc3
= retval
[2] = (arelent
*) xmalloc (sizeof (arelent
));
6123 reloc3
->address
+= 4;
6126 if (mips_pic
== NO_PIC
)
6128 assert (fixp
->fx_r_type
== BFD_RELOC_MIPS_GPREL
);
6129 fixp
->fx_r_type
= BFD_RELOC_HI16_S
;
6131 else if (mips_pic
== SVR4_PIC
)
6133 if (fixp
->fx_r_type
!= BFD_RELOC_MIPS_GOT16
)
6135 assert (fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL16
);
6136 fixp
->fx_r_type
= BFD_RELOC_MIPS_GOT16
;
6143 /* To support a PC relative reloc when generating embedded PIC code
6144 for ECOFF, we use a Cygnus extension. We check for that here to
6145 make sure that we don't let such a reloc escape normally. */
6147 if (fixp
->fx_r_type
== BFD_RELOC_16_PCREL_S2
6148 && mips_pic
!= EMBEDDED_PIC
)
6149 reloc
->howto
= NULL
;
6152 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, fixp
->fx_r_type
);
6154 if (reloc
->howto
== NULL
)
6156 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
6157 "Can not represent relocation in this object file format");
6164 /* Convert a machine dependent frag. */
6167 md_convert_frag (abfd
, asec
, fragp
)
6175 if (fragp
->fr_opcode
== NULL
)
6178 old
= RELAX_OLD (fragp
->fr_subtype
);
6179 new = RELAX_NEW (fragp
->fr_subtype
);
6180 fixptr
= fragp
->fr_literal
+ fragp
->fr_fix
;
6183 memcpy (fixptr
- old
, fixptr
, new);
6185 fragp
->fr_fix
+= new - old
;
6188 /* This function is called whenever a label is defined. It is used
6189 when handling branch delays; if a branch has a label, we assume we
6193 mips_define_label (sym
)
6201 /* Some special processing for a MIPS ELF file. */
6204 mips_elf_final_processing ()
6208 /* Write out the .reginfo section. */
6209 s
.ri_gprmask
= mips_gprmask
;
6210 s
.ri_cprmask
[0] = mips_cprmask
[0];
6211 s
.ri_cprmask
[1] = mips_cprmask
[1];
6212 s
.ri_cprmask
[2] = mips_cprmask
[2];
6213 s
.ri_cprmask
[3] = mips_cprmask
[3];
6214 /* The gp_value field is set by the MIPS ELF backend. */
6216 bfd_mips_elf32_swap_reginfo_out (stdoutput
, &s
,
6217 ((Elf32_External_RegInfo
*)
6218 mips_regmask_frag
));
6220 /* Set the MIPS ELF flag bits. FIXME: There should probably be some
6221 sort of BFD interface for this. */
6222 if (mips_any_noreorder
)
6223 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_NOREORDER
;
6224 if (mips_pic
!= NO_PIC
)
6225 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_PIC
;
6228 #endif /* OBJ_ELF */
6230 #ifndef ECOFF_DEBUGGING
6232 /* These functions should really be defined by the object file format,
6233 since they are related to debugging information. However, this
6234 code has to work for the a.out format, which does not define them,
6235 so we provide simple versions here. These don't actually generate
6236 any debugging information, but they do simple checking and someday
6237 somebody may make them useful. */
6241 struct loc
*loc_next
;
6242 unsigned long loc_fileno
;
6243 unsigned long loc_lineno
;
6244 unsigned long loc_offset
;
6245 unsigned short loc_delta
;
6246 unsigned short loc_count
;
6255 struct proc
*proc_next
;
6256 struct symbol
*proc_isym
;
6257 struct symbol
*proc_end
;
6258 unsigned long proc_reg_mask
;
6259 unsigned long proc_reg_offset
;
6260 unsigned long proc_fpreg_mask
;
6261 unsigned long proc_fpreg_offset
;
6262 unsigned long proc_frameoffset
;
6263 unsigned long proc_framereg
;
6264 unsigned long proc_pcreg
;
6266 struct file
*proc_file
;
6273 struct file
*file_next
;
6274 unsigned long file_fileno
;
6275 struct symbol
*file_symbol
;
6276 struct symbol
*file_end
;
6277 struct proc
*file_proc
;
6282 static struct obstack proc_frags
;
6283 static procS
*proc_lastP
;
6284 static procS
*proc_rootP
;
6285 static int numprocs
;
6290 obstack_begin (&proc_frags
, 0x2000);
6296 /* check for premature end, nesting errors, etc */
6297 if (proc_lastP
&& proc_lastP
->proc_end
== NULL
)
6298 as_warn ("missing `.end' at end of assembly");
6301 extern char hex_value
[];
6309 if (*input_line_pointer
== '-')
6311 ++input_line_pointer
;
6314 if (!isdigit (*input_line_pointer
))
6315 as_bad ("Expected simple number.");
6316 if (input_line_pointer
[0] == '0')
6318 if (input_line_pointer
[1] == 'x')
6320 input_line_pointer
+= 2;
6321 while (isxdigit (*input_line_pointer
))
6324 val
|= hex_value
[(int) *input_line_pointer
++];
6326 return negative
? -val
: val
;
6330 ++input_line_pointer
;
6331 while (isdigit (*input_line_pointer
))
6334 val
|= *input_line_pointer
++ - '0';
6336 return negative
? -val
: val
;
6339 if (!isdigit (*input_line_pointer
))
6341 printf (" *input_line_pointer == '%c' 0x%02x\n",
6342 *input_line_pointer
, *input_line_pointer
);
6343 as_warn ("Invalid number");
6346 while (isdigit (*input_line_pointer
))
6349 val
+= *input_line_pointer
++ - '0';
6351 return negative
? -val
: val
;
6354 /* The .file directive; just like the usual .file directive, but there
6355 is an initial number which is the ECOFF file index. */
6363 line
= get_number ();
6368 /* The .end directive. */
6376 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
6379 demand_empty_rest_of_line ();
6383 if (now_seg
!= text_section
)
6384 as_warn (".end not in text section");
6387 as_warn (".end and no .ent seen yet.");
6393 assert (S_GET_NAME (p
));
6394 if (strcmp (S_GET_NAME (p
), S_GET_NAME (proc_lastP
->proc_isym
)))
6395 as_warn (".end symbol does not match .ent symbol.");
6398 proc_lastP
->proc_end
= (symbolS
*) 1;
6401 /* The .aent and .ent directives. */
6411 symbolP
= get_symbol ();
6412 if (*input_line_pointer
== ',')
6413 input_line_pointer
++;
6415 if (isdigit (*input_line_pointer
) || *input_line_pointer
== '-')
6416 number
= get_number ();
6417 if (now_seg
!= text_section
)
6418 as_warn (".ent or .aent not in text section.");
6420 if (!aent
&& proc_lastP
&& proc_lastP
->proc_end
== NULL
)
6421 as_warn ("missing `.end'");
6425 procP
= (procS
*) obstack_alloc (&proc_frags
, sizeof (*procP
));
6426 procP
->proc_isym
= symbolP
;
6427 procP
->proc_reg_mask
= 0;
6428 procP
->proc_reg_offset
= 0;
6429 procP
->proc_fpreg_mask
= 0;
6430 procP
->proc_fpreg_offset
= 0;
6431 procP
->proc_frameoffset
= 0;
6432 procP
->proc_framereg
= 0;
6433 procP
->proc_pcreg
= 0;
6434 procP
->proc_end
= NULL
;
6435 procP
->proc_next
= NULL
;
6437 proc_lastP
->proc_next
= procP
;
6443 demand_empty_rest_of_line ();
6446 /* The .frame directive. */
6459 frame_reg
= tc_get_register (1);
6460 if (*input_line_pointer
== ',')
6461 input_line_pointer
++;
6462 frame_off
= get_absolute_expression ();
6463 if (*input_line_pointer
== ',')
6464 input_line_pointer
++;
6465 pcreg
= tc_get_register (0);
6468 assert (proc_rootP
);
6469 proc_rootP
->proc_framereg
= frame_reg
;
6470 proc_rootP
->proc_frameoffset
= frame_off
;
6471 proc_rootP
->proc_pcreg
= pcreg
;
6472 /* bob macho .frame */
6474 /* We don't have to write out a frame stab for unoptimized code. */
6475 if (!(frame_reg
== FP
&& frame_off
== 0))
6478 as_warn ("No .ent for .frame to use.");
6479 (void) sprintf (str
, "R%d;%d", frame_reg
, frame_off
);
6480 symP
= symbol_new (str
, N_VFP
, 0, frag_now
);
6481 S_SET_TYPE (symP
, N_RMASK
);
6482 S_SET_OTHER (symP
, 0);
6483 S_SET_DESC (symP
, 0);
6484 symP
->sy_forward
= proc_lastP
->proc_isym
;
6485 /* bob perhaps I should have used pseudo set */
6487 demand_empty_rest_of_line ();
6491 /* The .fmask and .mask directives. */
6498 char str
[100], *strP
;
6504 mask
= get_number ();
6505 if (*input_line_pointer
== ',')
6506 input_line_pointer
++;
6507 off
= get_absolute_expression ();
6509 /* bob only for coff */
6510 assert (proc_rootP
);
6511 if (reg_type
== 'F')
6513 proc_rootP
->proc_fpreg_mask
= mask
;
6514 proc_rootP
->proc_fpreg_offset
= off
;
6518 proc_rootP
->proc_reg_mask
= mask
;
6519 proc_rootP
->proc_reg_offset
= off
;
6522 /* bob macho .mask + .fmask */
6524 /* We don't have to write out a mask stab if no saved regs. */
6528 as_warn ("No .ent for .mask to use.");
6530 for (i
= 0; i
< 32; i
++)
6534 sprintf (strP
, "%c%d,", reg_type
, i
);
6535 strP
+= strlen (strP
);
6539 sprintf (strP
, ";%d,", off
);
6540 symP
= symbol_new (str
, N_RMASK
, 0, frag_now
);
6541 S_SET_TYPE (symP
, N_RMASK
);
6542 S_SET_OTHER (symP
, 0);
6543 S_SET_DESC (symP
, 0);
6544 symP
->sy_forward
= proc_lastP
->proc_isym
;
6545 /* bob perhaps I should have used pseudo set */
6550 /* The .loc directive. */
6561 assert (now_seg
== text_section
);
6563 lineno
= get_number ();
6564 addroff
= obstack_next_free (&frags
) - frag_now
->fr_literal
;
6566 symbolP
= symbol_new ("", N_SLINE
, addroff
, frag_now
);
6567 S_SET_TYPE (symbolP
, N_SLINE
);
6568 S_SET_OTHER (symbolP
, 0);
6569 S_SET_DESC (symbolP
, lineno
);
6570 symbolP
->sy_segment
= now_seg
;
6574 #endif /* ! defined (ECOFF_DEBUGGING) */