1 /* tc-mips.c -- assemble code for a MIPS chip.
2 Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,
3 2003, 2004, 2005 Free Software Foundation, Inc.
4 Contributed by the OSF and Ralph Campbell.
5 Written by Keith Knowles and Ralph Campbell, working independently.
6 Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus
9 This file is part of GAS.
11 GAS is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 2, or (at your option)
16 GAS is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
21 You should have received a copy of the GNU General Public License
22 along with GAS; see the file COPYING. If not, write to the Free
23 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
29 #include "safe-ctype.h"
33 #include "opcode/mips.h"
35 #include "dwarf2dbg.h"
38 #define DBG(x) printf x
44 /* Clean up namespace so we can include obj-elf.h too. */
45 static int mips_output_flavor (void);
46 static int mips_output_flavor (void) { return OUTPUT_FLAVOR
; }
47 #undef OBJ_PROCESS_STAB
54 #undef obj_frob_file_after_relocs
55 #undef obj_frob_symbol
57 #undef obj_sec_sym_ok_for_reloc
58 #undef OBJ_COPY_SYMBOL_ATTRIBUTES
61 /* Fix any of them that we actually care about. */
63 #define OUTPUT_FLAVOR mips_output_flavor()
70 #ifndef ECOFF_DEBUGGING
71 #define NO_ECOFF_DEBUGGING
72 #define ECOFF_DEBUGGING 0
75 int mips_flag_mdebug
= -1;
77 /* Control generation of .pdr sections. Off by default on IRIX: the native
78 linker doesn't know about and discards them, but relocations against them
79 remain, leading to rld crashes. */
81 int mips_flag_pdr
= FALSE
;
83 int mips_flag_pdr
= TRUE
;
88 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
89 static char *mips_regmask_frag
;
95 #define PIC_CALL_REG 25
103 #define ILLEGAL_REG (32)
105 /* Allow override of standard little-endian ECOFF format. */
107 #ifndef ECOFF_LITTLE_FORMAT
108 #define ECOFF_LITTLE_FORMAT "ecoff-littlemips"
111 extern int target_big_endian
;
113 /* The name of the readonly data section. */
114 #define RDATA_SECTION_NAME (OUTPUT_FLAVOR == bfd_target_ecoff_flavour \
116 : OUTPUT_FLAVOR == bfd_target_coff_flavour \
118 : OUTPUT_FLAVOR == bfd_target_elf_flavour \
122 /* Information about an instruction, including its format, operands
126 /* The opcode's entry in mips_opcodes or mips16_opcodes. */
127 const struct mips_opcode
*insn_mo
;
129 /* True if this is a mips16 instruction and if we want the extended
131 bfd_boolean use_extend
;
133 /* The 16-bit extension instruction to use when USE_EXTEND is true. */
134 unsigned short extend
;
136 /* The 16-bit or 32-bit bitstring of the instruction itself. This is
137 a copy of INSN_MO->match with the operands filled in. */
138 unsigned long insn_opcode
;
140 /* The frag that contains the instruction. */
143 /* The offset into FRAG of the first instruction byte. */
146 /* The relocs associated with the instruction, if any. */
149 /* True if this entry cannot be moved from its current position. */
150 unsigned int fixed_p
: 1;
152 /* True if this instruction occured in a .set noreorder block. */
153 unsigned int noreorder_p
: 1;
155 /* True for mips16 instructions that jump to an absolute address. */
156 unsigned int mips16_absolute_jump_p
: 1;
159 /* The ABI to use. */
170 /* MIPS ABI we are using for this output file. */
171 static enum mips_abi_level mips_abi
= NO_ABI
;
173 /* Whether or not we have code that can call pic code. */
174 int mips_abicalls
= FALSE
;
176 /* Whether or not we have code which can be put into a shared
178 static bfd_boolean mips_in_shared
= TRUE
;
180 /* This is the set of options which may be modified by the .set
181 pseudo-op. We use a struct so that .set push and .set pop are more
184 struct mips_set_options
186 /* MIPS ISA (Instruction Set Architecture) level. This is set to -1
187 if it has not been initialized. Changed by `.set mipsN', and the
188 -mipsN command line option, and the default CPU. */
190 /* Enabled Application Specific Extensions (ASEs). These are set to -1
191 if they have not been initialized. Changed by `.set <asename>', by
192 command line options, and based on the default architecture. */
195 /* Whether we are assembling for the mips16 processor. 0 if we are
196 not, 1 if we are, and -1 if the value has not been initialized.
197 Changed by `.set mips16' and `.set nomips16', and the -mips16 and
198 -nomips16 command line options, and the default CPU. */
200 /* Non-zero if we should not reorder instructions. Changed by `.set
201 reorder' and `.set noreorder'. */
203 /* Non-zero if we should not permit the $at ($1) register to be used
204 in instructions. Changed by `.set at' and `.set noat'. */
206 /* Non-zero if we should warn when a macro instruction expands into
207 more than one machine instruction. Changed by `.set nomacro' and
209 int warn_about_macros
;
210 /* Non-zero if we should not move instructions. Changed by `.set
211 move', `.set volatile', `.set nomove', and `.set novolatile'. */
213 /* Non-zero if we should not optimize branches by moving the target
214 of the branch into the delay slot. Actually, we don't perform
215 this optimization anyhow. Changed by `.set bopt' and `.set
218 /* Non-zero if we should not autoextend mips16 instructions.
219 Changed by `.set autoextend' and `.set noautoextend'. */
221 /* Restrict general purpose registers and floating point registers
222 to 32 bit. This is initially determined when -mgp32 or -mfp32
223 is passed but can changed if the assembler code uses .set mipsN. */
226 /* MIPS architecture (CPU) type. Changed by .set arch=FOO, the -march
227 command line option, and the default CPU. */
229 /* True if ".set sym32" is in effect. */
233 /* True if -mgp32 was passed. */
234 static int file_mips_gp32
= -1;
236 /* True if -mfp32 was passed. */
237 static int file_mips_fp32
= -1;
239 /* This is the struct we use to hold the current set of options. Note
240 that we must set the isa field to ISA_UNKNOWN and the ASE fields to
241 -1 to indicate that they have not been initialized. */
243 static struct mips_set_options mips_opts
=
245 ISA_UNKNOWN
, -1, -1, -1, 0, 0, 0, 0, 0, 0, 0, 0, CPU_UNKNOWN
, FALSE
248 /* These variables are filled in with the masks of registers used.
249 The object format code reads them and puts them in the appropriate
251 unsigned long mips_gprmask
;
252 unsigned long mips_cprmask
[4];
254 /* MIPS ISA we are using for this output file. */
255 static int file_mips_isa
= ISA_UNKNOWN
;
257 /* True if -mips16 was passed or implied by arguments passed on the
258 command line (e.g., by -march). */
259 static int file_ase_mips16
;
261 /* True if -mips3d was passed or implied by arguments passed on the
262 command line (e.g., by -march). */
263 static int file_ase_mips3d
;
265 /* True if -mdmx was passed or implied by arguments passed on the
266 command line (e.g., by -march). */
267 static int file_ase_mdmx
;
269 /* The argument of the -march= flag. The architecture we are assembling. */
270 static int file_mips_arch
= CPU_UNKNOWN
;
271 static const char *mips_arch_string
;
273 /* The argument of the -mtune= flag. The architecture for which we
275 static int mips_tune
= CPU_UNKNOWN
;
276 static const char *mips_tune_string
;
278 /* True when generating 32-bit code for a 64-bit processor. */
279 static int mips_32bitmode
= 0;
281 /* True if the given ABI requires 32-bit registers. */
282 #define ABI_NEEDS_32BIT_REGS(ABI) ((ABI) == O32_ABI)
284 /* Likewise 64-bit registers. */
285 #define ABI_NEEDS_64BIT_REGS(ABI) \
287 || (ABI) == N64_ABI \
290 /* Return true if ISA supports 64 bit gp register instructions. */
291 #define ISA_HAS_64BIT_REGS(ISA) ( \
293 || (ISA) == ISA_MIPS4 \
294 || (ISA) == ISA_MIPS5 \
295 || (ISA) == ISA_MIPS64 \
296 || (ISA) == ISA_MIPS64R2 \
299 /* Return true if ISA supports 64-bit right rotate (dror et al.)
301 #define ISA_HAS_DROR(ISA) ( \
302 (ISA) == ISA_MIPS64R2 \
305 /* Return true if ISA supports 32-bit right rotate (ror et al.)
307 #define ISA_HAS_ROR(ISA) ( \
308 (ISA) == ISA_MIPS32R2 \
309 || (ISA) == ISA_MIPS64R2 \
312 #define HAVE_32BIT_GPRS \
313 (mips_opts.gp32 || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
315 #define HAVE_32BIT_FPRS \
316 (mips_opts.fp32 || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
318 #define HAVE_64BIT_GPRS (! HAVE_32BIT_GPRS)
319 #define HAVE_64BIT_FPRS (! HAVE_32BIT_FPRS)
321 #define HAVE_NEWABI (mips_abi == N32_ABI || mips_abi == N64_ABI)
323 #define HAVE_64BIT_OBJECTS (mips_abi == N64_ABI)
325 /* True if relocations are stored in-place. */
326 #define HAVE_IN_PLACE_ADDENDS (!HAVE_NEWABI)
328 /* The ABI-derived address size. */
329 #define HAVE_64BIT_ADDRESSES \
330 (HAVE_64BIT_GPRS && (mips_abi == EABI_ABI || mips_abi == N64_ABI))
331 #define HAVE_32BIT_ADDRESSES (!HAVE_64BIT_ADDRESSES)
333 /* The size of symbolic constants (i.e., expressions of the form
334 "SYMBOL" or "SYMBOL + OFFSET"). */
335 #define HAVE_32BIT_SYMBOLS \
336 (HAVE_32BIT_ADDRESSES || !HAVE_64BIT_OBJECTS || mips_opts.sym32)
337 #define HAVE_64BIT_SYMBOLS (!HAVE_32BIT_SYMBOLS)
339 /* Addresses are loaded in different ways, depending on the address size
340 in use. The n32 ABI Documentation also mandates the use of additions
341 with overflow checking, but existing implementations don't follow it. */
342 #define ADDRESS_ADD_INSN \
343 (HAVE_32BIT_ADDRESSES ? "addu" : "daddu")
345 #define ADDRESS_ADDI_INSN \
346 (HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu")
348 #define ADDRESS_LOAD_INSN \
349 (HAVE_32BIT_ADDRESSES ? "lw" : "ld")
351 #define ADDRESS_STORE_INSN \
352 (HAVE_32BIT_ADDRESSES ? "sw" : "sd")
354 /* Return true if the given CPU supports the MIPS16 ASE. */
355 #define CPU_HAS_MIPS16(cpu) \
356 (strncmp (TARGET_CPU, "mips16", sizeof ("mips16") - 1) == 0 \
357 || strncmp (TARGET_CANONICAL, "mips-lsi-elf", sizeof ("mips-lsi-elf") - 1) == 0)
359 /* Return true if the given CPU supports the MIPS3D ASE. */
360 #define CPU_HAS_MIPS3D(cpu) ((cpu) == CPU_SB1 \
363 /* Return true if the given CPU supports the MDMX ASE. */
364 #define CPU_HAS_MDMX(cpu) (FALSE \
367 /* True if CPU has a dror instruction. */
368 #define CPU_HAS_DROR(CPU) ((CPU) == CPU_VR5400 || (CPU) == CPU_VR5500)
370 /* True if CPU has a ror instruction. */
371 #define CPU_HAS_ROR(CPU) CPU_HAS_DROR (CPU)
373 /* True if mflo and mfhi can be immediately followed by instructions
374 which write to the HI and LO registers.
376 According to MIPS specifications, MIPS ISAs I, II, and III need
377 (at least) two instructions between the reads of HI/LO and
378 instructions which write them, and later ISAs do not. Contradicting
379 the MIPS specifications, some MIPS IV processor user manuals (e.g.
380 the UM for the NEC Vr5000) document needing the instructions between
381 HI/LO reads and writes, as well. Therefore, we declare only MIPS32,
382 MIPS64 and later ISAs to have the interlocks, plus any specific
383 earlier-ISA CPUs for which CPU documentation declares that the
384 instructions are really interlocked. */
385 #define hilo_interlocks \
386 (mips_opts.isa == ISA_MIPS32 \
387 || mips_opts.isa == ISA_MIPS32R2 \
388 || mips_opts.isa == ISA_MIPS64 \
389 || mips_opts.isa == ISA_MIPS64R2 \
390 || mips_opts.arch == CPU_R4010 \
391 || mips_opts.arch == CPU_R10000 \
392 || mips_opts.arch == CPU_R12000 \
393 || mips_opts.arch == CPU_RM7000 \
394 || mips_opts.arch == CPU_VR5500 \
397 /* Whether the processor uses hardware interlocks to protect reads
398 from the GPRs after they are loaded from memory, and thus does not
399 require nops to be inserted. This applies to instructions marked
400 INSN_LOAD_MEMORY_DELAY. These nops are only required at MIPS ISA
402 #define gpr_interlocks \
403 (mips_opts.isa != ISA_MIPS1 \
404 || mips_opts.arch == CPU_R3900)
406 /* Whether the processor uses hardware interlocks to avoid delays
407 required by coprocessor instructions, and thus does not require
408 nops to be inserted. This applies to instructions marked
409 INSN_LOAD_COPROC_DELAY, INSN_COPROC_MOVE_DELAY, and to delays
410 between instructions marked INSN_WRITE_COND_CODE and ones marked
411 INSN_READ_COND_CODE. These nops are only required at MIPS ISA
412 levels I, II, and III. */
413 /* Itbl support may require additional care here. */
414 #define cop_interlocks \
415 ((mips_opts.isa != ISA_MIPS1 \
416 && mips_opts.isa != ISA_MIPS2 \
417 && mips_opts.isa != ISA_MIPS3) \
418 || mips_opts.arch == CPU_R4300 \
421 /* Whether the processor uses hardware interlocks to protect reads
422 from coprocessor registers after they are loaded from memory, and
423 thus does not require nops to be inserted. This applies to
424 instructions marked INSN_COPROC_MEMORY_DELAY. These nops are only
425 requires at MIPS ISA level I. */
426 #define cop_mem_interlocks (mips_opts.isa != ISA_MIPS1)
428 /* Is this a mfhi or mflo instruction? */
429 #define MF_HILO_INSN(PINFO) \
430 ((PINFO & INSN_READ_HI) || (PINFO & INSN_READ_LO))
432 /* MIPS PIC level. */
434 enum mips_pic_level mips_pic
;
436 /* 1 if we should generate 32 bit offsets from the $gp register in
437 SVR4_PIC mode. Currently has no meaning in other modes. */
438 static int mips_big_got
= 0;
440 /* 1 if trap instructions should used for overflow rather than break
442 static int mips_trap
= 0;
444 /* 1 if double width floating point constants should not be constructed
445 by assembling two single width halves into two single width floating
446 point registers which just happen to alias the double width destination
447 register. On some architectures this aliasing can be disabled by a bit
448 in the status register, and the setting of this bit cannot be determined
449 automatically at assemble time. */
450 static int mips_disable_float_construction
;
452 /* Non-zero if any .set noreorder directives were used. */
454 static int mips_any_noreorder
;
456 /* Non-zero if nops should be inserted when the register referenced in
457 an mfhi/mflo instruction is read in the next two instructions. */
458 static int mips_7000_hilo_fix
;
460 /* The size of the small data section. */
461 static unsigned int g_switch_value
= 8;
462 /* Whether the -G option was used. */
463 static int g_switch_seen
= 0;
468 /* If we can determine in advance that GP optimization won't be
469 possible, we can skip the relaxation stuff that tries to produce
470 GP-relative references. This makes delay slot optimization work
473 This function can only provide a guess, but it seems to work for
474 gcc output. It needs to guess right for gcc, otherwise gcc
475 will put what it thinks is a GP-relative instruction in a branch
478 I don't know if a fix is needed for the SVR4_PIC mode. I've only
479 fixed it for the non-PIC mode. KR 95/04/07 */
480 static int nopic_need_relax (symbolS
*, int);
482 /* handle of the OPCODE hash table */
483 static struct hash_control
*op_hash
= NULL
;
485 /* The opcode hash table we use for the mips16. */
486 static struct hash_control
*mips16_op_hash
= NULL
;
488 /* This array holds the chars that always start a comment. If the
489 pre-processor is disabled, these aren't very useful */
490 const char comment_chars
[] = "#";
492 /* This array holds the chars that only start a comment at the beginning of
493 a line. If the line seems to have the form '# 123 filename'
494 .line and .file directives will appear in the pre-processed output */
495 /* Note that input_file.c hand checks for '#' at the beginning of the
496 first line of the input file. This is because the compiler outputs
497 #NO_APP at the beginning of its output. */
498 /* Also note that C style comments are always supported. */
499 const char line_comment_chars
[] = "#";
501 /* This array holds machine specific line separator characters. */
502 const char line_separator_chars
[] = ";";
504 /* Chars that can be used to separate mant from exp in floating point nums */
505 const char EXP_CHARS
[] = "eE";
507 /* Chars that mean this number is a floating point constant */
510 const char FLT_CHARS
[] = "rRsSfFdDxXpP";
512 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
513 changed in read.c . Ideally it shouldn't have to know about it at all,
514 but nothing is ideal around here.
517 static char *insn_error
;
519 static int auto_align
= 1;
521 /* When outputting SVR4 PIC code, the assembler needs to know the
522 offset in the stack frame from which to restore the $gp register.
523 This is set by the .cprestore pseudo-op, and saved in this
525 static offsetT mips_cprestore_offset
= -1;
527 /* Similar for NewABI PIC code, where $gp is callee-saved. NewABI has some
528 more optimizations, it can use a register value instead of a memory-saved
529 offset and even an other register than $gp as global pointer. */
530 static offsetT mips_cpreturn_offset
= -1;
531 static int mips_cpreturn_register
= -1;
532 static int mips_gp_register
= GP
;
533 static int mips_gprel_offset
= 0;
535 /* Whether mips_cprestore_offset has been set in the current function
536 (or whether it has already been warned about, if not). */
537 static int mips_cprestore_valid
= 0;
539 /* This is the register which holds the stack frame, as set by the
540 .frame pseudo-op. This is needed to implement .cprestore. */
541 static int mips_frame_reg
= SP
;
543 /* Whether mips_frame_reg has been set in the current function
544 (or whether it has already been warned about, if not). */
545 static int mips_frame_reg_valid
= 0;
547 /* To output NOP instructions correctly, we need to keep information
548 about the previous two instructions. */
550 /* Whether we are optimizing. The default value of 2 means to remove
551 unneeded NOPs and swap branch instructions when possible. A value
552 of 1 means to not swap branches. A value of 0 means to always
554 static int mips_optimize
= 2;
556 /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is
557 equivalent to seeing no -g option at all. */
558 static int mips_debug
= 0;
560 /* The maximum number of NOPs needed to satisfy a hardware hazard
561 or processor errata. */
564 /* A list of previous instructions, with index 0 being the most recent.
565 We need to look back MAX_NOPS instructions when filling delay slots
566 or working around processor errata. We need to look back one
567 instruction further if we're thinking about using history[0] to
568 fill a branch delay slot. */
569 static struct mips_cl_insn history
[1 + MAX_NOPS
];
571 /* Nop instructions used by emit_nop. */
572 static struct mips_cl_insn nop_insn
, mips16_nop_insn
;
574 /* The appropriate nop for the current mode. */
575 #define NOP_INSN (mips_opts.mips16 ? &mips16_nop_insn : &nop_insn)
577 /* If this is set, it points to a frag holding nop instructions which
578 were inserted before the start of a noreorder section. If those
579 nops turn out to be unnecessary, the size of the frag can be
581 static fragS
*prev_nop_frag
;
583 /* The number of nop instructions we created in prev_nop_frag. */
584 static int prev_nop_frag_holds
;
586 /* The number of nop instructions that we know we need in
588 static int prev_nop_frag_required
;
590 /* The number of instructions we've seen since prev_nop_frag. */
591 static int prev_nop_frag_since
;
593 /* For ECOFF and ELF, relocations against symbols are done in two
594 parts, with a HI relocation and a LO relocation. Each relocation
595 has only 16 bits of space to store an addend. This means that in
596 order for the linker to handle carries correctly, it must be able
597 to locate both the HI and the LO relocation. This means that the
598 relocations must appear in order in the relocation table.
600 In order to implement this, we keep track of each unmatched HI
601 relocation. We then sort them so that they immediately precede the
602 corresponding LO relocation. */
607 struct mips_hi_fixup
*next
;
610 /* The section this fixup is in. */
614 /* The list of unmatched HI relocs. */
616 static struct mips_hi_fixup
*mips_hi_fixup_list
;
618 /* The frag containing the last explicit relocation operator.
619 Null if explicit relocations have not been used. */
621 static fragS
*prev_reloc_op_frag
;
623 /* Map normal MIPS register numbers to mips16 register numbers. */
625 #define X ILLEGAL_REG
626 static const int mips32_to_16_reg_map
[] =
628 X
, X
, 2, 3, 4, 5, 6, 7,
629 X
, X
, X
, X
, X
, X
, X
, X
,
630 0, 1, X
, X
, X
, X
, X
, X
,
631 X
, X
, X
, X
, X
, X
, X
, X
635 /* Map mips16 register numbers to normal MIPS register numbers. */
637 static const unsigned int mips16_to_32_reg_map
[] =
639 16, 17, 2, 3, 4, 5, 6, 7
642 /* Classifies the kind of instructions we're interested in when
643 implementing -mfix-vr4120. */
644 enum fix_vr4120_class
{
651 NUM_FIX_VR4120_CLASSES
654 /* Given two FIX_VR4120_* values X and Y, bit Y of element X is set if
655 there must be at least one other instruction between an instruction
656 of type X and an instruction of type Y. */
657 static unsigned int vr4120_conflicts
[NUM_FIX_VR4120_CLASSES
];
659 /* True if -mfix-vr4120 is in force. */
660 static int mips_fix_vr4120
;
662 /* We don't relax branches by default, since this causes us to expand
663 `la .l2 - .l1' if there's a branch between .l1 and .l2, because we
664 fail to compute the offset before expanding the macro to the most
665 efficient expansion. */
667 static int mips_relax_branch
;
669 /* The expansion of many macros depends on the type of symbol that
670 they refer to. For example, when generating position-dependent code,
671 a macro that refers to a symbol may have two different expansions,
672 one which uses GP-relative addresses and one which uses absolute
673 addresses. When generating SVR4-style PIC, a macro may have
674 different expansions for local and global symbols.
676 We handle these situations by generating both sequences and putting
677 them in variant frags. In position-dependent code, the first sequence
678 will be the GP-relative one and the second sequence will be the
679 absolute one. In SVR4 PIC, the first sequence will be for global
680 symbols and the second will be for local symbols.
682 The frag's "subtype" is RELAX_ENCODE (FIRST, SECOND), where FIRST and
683 SECOND are the lengths of the two sequences in bytes. These fields
684 can be extracted using RELAX_FIRST() and RELAX_SECOND(). In addition,
685 the subtype has the following flags:
688 Set if it has been decided that we should use the second
689 sequence instead of the first.
692 Set in the first variant frag if the macro's second implementation
693 is longer than its first. This refers to the macro as a whole,
694 not an individual relaxation.
697 Set in the first variant frag if the macro appeared in a .set nomacro
698 block and if one alternative requires a warning but the other does not.
701 Like RELAX_NOMACRO, but indicates that the macro appears in a branch
704 The frag's "opcode" points to the first fixup for relaxable code.
706 Relaxable macros are generated using a sequence such as:
708 relax_start (SYMBOL);
709 ... generate first expansion ...
711 ... generate second expansion ...
714 The code and fixups for the unwanted alternative are discarded
715 by md_convert_frag. */
716 #define RELAX_ENCODE(FIRST, SECOND) (((FIRST) << 8) | (SECOND))
718 #define RELAX_FIRST(X) (((X) >> 8) & 0xff)
719 #define RELAX_SECOND(X) ((X) & 0xff)
720 #define RELAX_USE_SECOND 0x10000
721 #define RELAX_SECOND_LONGER 0x20000
722 #define RELAX_NOMACRO 0x40000
723 #define RELAX_DELAY_SLOT 0x80000
725 /* Branch without likely bit. If label is out of range, we turn:
727 beq reg1, reg2, label
737 with the following opcode replacements:
744 bltzal <-> bgezal (with jal label instead of j label)
746 Even though keeping the delay slot instruction in the delay slot of
747 the branch would be more efficient, it would be very tricky to do
748 correctly, because we'd have to introduce a variable frag *after*
749 the delay slot instruction, and expand that instead. Let's do it
750 the easy way for now, even if the branch-not-taken case now costs
751 one additional instruction. Out-of-range branches are not supposed
752 to be common, anyway.
754 Branch likely. If label is out of range, we turn:
756 beql reg1, reg2, label
757 delay slot (annulled if branch not taken)
766 delay slot (executed only if branch taken)
769 It would be possible to generate a shorter sequence by losing the
770 likely bit, generating something like:
775 delay slot (executed only if branch taken)
787 bltzall -> bgezal (with jal label instead of j label)
788 bgezall -> bltzal (ditto)
791 but it's not clear that it would actually improve performance. */
792 #define RELAX_BRANCH_ENCODE(uncond, likely, link, toofar) \
795 | ((toofar) ? 1 : 0) \
797 | ((likely) ? 4 : 0) \
798 | ((uncond) ? 8 : 0)))
799 #define RELAX_BRANCH_P(i) (((i) & 0xf0000000) == 0xc0000000)
800 #define RELAX_BRANCH_UNCOND(i) (((i) & 8) != 0)
801 #define RELAX_BRANCH_LIKELY(i) (((i) & 4) != 0)
802 #define RELAX_BRANCH_LINK(i) (((i) & 2) != 0)
803 #define RELAX_BRANCH_TOOFAR(i) (((i) & 1) != 0)
805 /* For mips16 code, we use an entirely different form of relaxation.
806 mips16 supports two versions of most instructions which take
807 immediate values: a small one which takes some small value, and a
808 larger one which takes a 16 bit value. Since branches also follow
809 this pattern, relaxing these values is required.
811 We can assemble both mips16 and normal MIPS code in a single
812 object. Therefore, we need to support this type of relaxation at
813 the same time that we support the relaxation described above. We
814 use the high bit of the subtype field to distinguish these cases.
816 The information we store for this type of relaxation is the
817 argument code found in the opcode file for this relocation, whether
818 the user explicitly requested a small or extended form, and whether
819 the relocation is in a jump or jal delay slot. That tells us the
820 size of the value, and how it should be stored. We also store
821 whether the fragment is considered to be extended or not. We also
822 store whether this is known to be a branch to a different section,
823 whether we have tried to relax this frag yet, and whether we have
824 ever extended a PC relative fragment because of a shift count. */
825 #define RELAX_MIPS16_ENCODE(type, small, ext, dslot, jal_dslot) \
828 | ((small) ? 0x100 : 0) \
829 | ((ext) ? 0x200 : 0) \
830 | ((dslot) ? 0x400 : 0) \
831 | ((jal_dslot) ? 0x800 : 0))
832 #define RELAX_MIPS16_P(i) (((i) & 0xc0000000) == 0x80000000)
833 #define RELAX_MIPS16_TYPE(i) ((i) & 0xff)
834 #define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x100) != 0)
835 #define RELAX_MIPS16_USER_EXT(i) (((i) & 0x200) != 0)
836 #define RELAX_MIPS16_DSLOT(i) (((i) & 0x400) != 0)
837 #define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x800) != 0)
838 #define RELAX_MIPS16_EXTENDED(i) (((i) & 0x1000) != 0)
839 #define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x1000)
840 #define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) &~ 0x1000)
841 #define RELAX_MIPS16_LONG_BRANCH(i) (((i) & 0x2000) != 0)
842 #define RELAX_MIPS16_MARK_LONG_BRANCH(i) ((i) | 0x2000)
843 #define RELAX_MIPS16_CLEAR_LONG_BRANCH(i) ((i) &~ 0x2000)
845 /* Is the given value a sign-extended 32-bit value? */
846 #define IS_SEXT_32BIT_NUM(x) \
847 (((x) &~ (offsetT) 0x7fffffff) == 0 \
848 || (((x) &~ (offsetT) 0x7fffffff) == ~ (offsetT) 0x7fffffff))
850 /* Is the given value a sign-extended 16-bit value? */
851 #define IS_SEXT_16BIT_NUM(x) \
852 (((x) &~ (offsetT) 0x7fff) == 0 \
853 || (((x) &~ (offsetT) 0x7fff) == ~ (offsetT) 0x7fff))
855 /* Replace bits MASK << SHIFT of STRUCT with the equivalent bits in
856 VALUE << SHIFT. VALUE is evaluated exactly once. */
857 #define INSERT_BITS(STRUCT, VALUE, MASK, SHIFT) \
858 (STRUCT) = (((STRUCT) & ~((MASK) << (SHIFT))) \
859 | (((VALUE) & (MASK)) << (SHIFT)))
861 /* Extract bits MASK << SHIFT from STRUCT and shift them right
863 #define EXTRACT_BITS(STRUCT, MASK, SHIFT) \
864 (((STRUCT) >> (SHIFT)) & (MASK))
866 /* Change INSN's opcode so that the operand given by FIELD has value VALUE.
867 INSN is a mips_cl_insn structure and VALUE is evaluated exactly once.
869 include/opcode/mips.h specifies operand fields using the macros
870 OP_MASK_<FIELD> and OP_SH_<FIELD>. The MIPS16 equivalents start
871 with "MIPS16OP" instead of "OP". */
872 #define INSERT_OPERAND(FIELD, INSN, VALUE) \
873 INSERT_BITS ((INSN).insn_opcode, VALUE, OP_MASK_##FIELD, OP_SH_##FIELD)
874 #define MIPS16_INSERT_OPERAND(FIELD, INSN, VALUE) \
875 INSERT_BITS ((INSN).insn_opcode, VALUE, \
876 MIPS16OP_MASK_##FIELD, MIPS16OP_SH_##FIELD)
878 /* Extract the operand given by FIELD from mips_cl_insn INSN. */
879 #define EXTRACT_OPERAND(FIELD, INSN) \
880 EXTRACT_BITS ((INSN).insn_opcode, OP_MASK_##FIELD, OP_SH_##FIELD)
881 #define MIPS16_EXTRACT_OPERAND(FIELD, INSN) \
882 EXTRACT_BITS ((INSN).insn_opcode, \
883 MIPS16OP_MASK_##FIELD, \
886 /* Global variables used when generating relaxable macros. See the
887 comment above RELAX_ENCODE for more details about how relaxation
890 /* 0 if we're not emitting a relaxable macro.
891 1 if we're emitting the first of the two relaxation alternatives.
892 2 if we're emitting the second alternative. */
895 /* The first relaxable fixup in the current frag. (In other words,
896 the first fixup that refers to relaxable code.) */
899 /* sizes[0] says how many bytes of the first alternative are stored in
900 the current frag. Likewise sizes[1] for the second alternative. */
901 unsigned int sizes
[2];
903 /* The symbol on which the choice of sequence depends. */
907 /* Global variables used to decide whether a macro needs a warning. */
909 /* True if the macro is in a branch delay slot. */
910 bfd_boolean delay_slot_p
;
912 /* For relaxable macros, sizes[0] is the length of the first alternative
913 in bytes and sizes[1] is the length of the second alternative.
914 For non-relaxable macros, both elements give the length of the
916 unsigned int sizes
[2];
918 /* The first variant frag for this macro. */
920 } mips_macro_warning
;
922 /* Prototypes for static functions. */
924 #define internalError() \
925 as_fatal (_("internal Error, line %d, %s"), __LINE__, __FILE__)
927 enum mips_regclass
{ MIPS_GR_REG
, MIPS_FP_REG
, MIPS16_REG
};
929 static void append_insn
930 (struct mips_cl_insn
*ip
, expressionS
*p
, bfd_reloc_code_real_type
*r
);
931 static void mips_no_prev_insn (int);
932 static void mips16_macro_build
933 (expressionS
*, const char *, const char *, va_list);
934 static void load_register (int, expressionS
*, int);
935 static void macro_start (void);
936 static void macro_end (void);
937 static void macro (struct mips_cl_insn
* ip
);
938 static void mips16_macro (struct mips_cl_insn
* ip
);
939 #ifdef LOSING_COMPILER
940 static void macro2 (struct mips_cl_insn
* ip
);
942 static void mips_ip (char *str
, struct mips_cl_insn
* ip
);
943 static void mips16_ip (char *str
, struct mips_cl_insn
* ip
);
944 static void mips16_immed
945 (char *, unsigned int, int, offsetT
, bfd_boolean
, bfd_boolean
, bfd_boolean
,
946 unsigned long *, bfd_boolean
*, unsigned short *);
947 static size_t my_getSmallExpression
948 (expressionS
*, bfd_reloc_code_real_type
*, char *);
949 static void my_getExpression (expressionS
*, char *);
950 static void s_align (int);
951 static void s_change_sec (int);
952 static void s_change_section (int);
953 static void s_cons (int);
954 static void s_float_cons (int);
955 static void s_mips_globl (int);
956 static void s_option (int);
957 static void s_mipsset (int);
958 static void s_abicalls (int);
959 static void s_cpload (int);
960 static void s_cpsetup (int);
961 static void s_cplocal (int);
962 static void s_cprestore (int);
963 static void s_cpreturn (int);
964 static void s_gpvalue (int);
965 static void s_gpword (int);
966 static void s_gpdword (int);
967 static void s_cpadd (int);
968 static void s_insn (int);
969 static void md_obj_begin (void);
970 static void md_obj_end (void);
971 static void s_mips_ent (int);
972 static void s_mips_end (int);
973 static void s_mips_frame (int);
974 static void s_mips_mask (int reg_type
);
975 static void s_mips_stab (int);
976 static void s_mips_weakext (int);
977 static void s_mips_file (int);
978 static void s_mips_loc (int);
979 static bfd_boolean
pic_need_relax (symbolS
*, asection
*);
980 static int relaxed_branch_length (fragS
*, asection
*, int);
981 static int validate_mips_insn (const struct mips_opcode
*);
983 /* Table and functions used to map between CPU/ISA names, and
984 ISA levels, and CPU numbers. */
988 const char *name
; /* CPU or ISA name. */
989 int is_isa
; /* Is this an ISA? (If 0, a CPU.) */
990 int isa
; /* ISA level. */
991 int cpu
; /* CPU number (default CPU if ISA). */
994 static const struct mips_cpu_info
*mips_parse_cpu (const char *, const char *);
995 static const struct mips_cpu_info
*mips_cpu_info_from_isa (int);
996 static const struct mips_cpu_info
*mips_cpu_info_from_arch (int);
1000 The following pseudo-ops from the Kane and Heinrich MIPS book
1001 should be defined here, but are currently unsupported: .alias,
1002 .galive, .gjaldef, .gjrlive, .livereg, .noalias.
1004 The following pseudo-ops from the Kane and Heinrich MIPS book are
1005 specific to the type of debugging information being generated, and
1006 should be defined by the object format: .aent, .begin, .bend,
1007 .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp,
1010 The following pseudo-ops from the Kane and Heinrich MIPS book are
1011 not MIPS CPU specific, but are also not specific to the object file
1012 format. This file is probably the best place to define them, but
1013 they are not currently supported: .asm0, .endr, .lab, .repeat,
1016 static const pseudo_typeS mips_pseudo_table
[] =
1018 /* MIPS specific pseudo-ops. */
1019 {"option", s_option
, 0},
1020 {"set", s_mipsset
, 0},
1021 {"rdata", s_change_sec
, 'r'},
1022 {"sdata", s_change_sec
, 's'},
1023 {"livereg", s_ignore
, 0},
1024 {"abicalls", s_abicalls
, 0},
1025 {"cpload", s_cpload
, 0},
1026 {"cpsetup", s_cpsetup
, 0},
1027 {"cplocal", s_cplocal
, 0},
1028 {"cprestore", s_cprestore
, 0},
1029 {"cpreturn", s_cpreturn
, 0},
1030 {"gpvalue", s_gpvalue
, 0},
1031 {"gpword", s_gpword
, 0},
1032 {"gpdword", s_gpdword
, 0},
1033 {"cpadd", s_cpadd
, 0},
1034 {"insn", s_insn
, 0},
1036 /* Relatively generic pseudo-ops that happen to be used on MIPS
1038 {"asciiz", stringer
, 1},
1039 {"bss", s_change_sec
, 'b'},
1041 {"half", s_cons
, 1},
1042 {"dword", s_cons
, 3},
1043 {"weakext", s_mips_weakext
, 0},
1045 /* These pseudo-ops are defined in read.c, but must be overridden
1046 here for one reason or another. */
1047 {"align", s_align
, 0},
1048 {"byte", s_cons
, 0},
1049 {"data", s_change_sec
, 'd'},
1050 {"double", s_float_cons
, 'd'},
1051 {"float", s_float_cons
, 'f'},
1052 {"globl", s_mips_globl
, 0},
1053 {"global", s_mips_globl
, 0},
1054 {"hword", s_cons
, 1},
1056 {"long", s_cons
, 2},
1057 {"octa", s_cons
, 4},
1058 {"quad", s_cons
, 3},
1059 {"section", s_change_section
, 0},
1060 {"short", s_cons
, 1},
1061 {"single", s_float_cons
, 'f'},
1062 {"stabn", s_mips_stab
, 'n'},
1063 {"text", s_change_sec
, 't'},
1064 {"word", s_cons
, 2},
1066 { "extern", ecoff_directive_extern
, 0},
1071 static const pseudo_typeS mips_nonecoff_pseudo_table
[] =
1073 /* These pseudo-ops should be defined by the object file format.
1074 However, a.out doesn't support them, so we have versions here. */
1075 {"aent", s_mips_ent
, 1},
1076 {"bgnb", s_ignore
, 0},
1077 {"end", s_mips_end
, 0},
1078 {"endb", s_ignore
, 0},
1079 {"ent", s_mips_ent
, 0},
1080 {"file", s_mips_file
, 0},
1081 {"fmask", s_mips_mask
, 'F'},
1082 {"frame", s_mips_frame
, 0},
1083 {"loc", s_mips_loc
, 0},
1084 {"mask", s_mips_mask
, 'R'},
1085 {"verstamp", s_ignore
, 0},
1089 extern void pop_insert (const pseudo_typeS
*);
1092 mips_pop_insert (void)
1094 pop_insert (mips_pseudo_table
);
1095 if (! ECOFF_DEBUGGING
)
1096 pop_insert (mips_nonecoff_pseudo_table
);
1099 /* Symbols labelling the current insn. */
1101 struct insn_label_list
1103 struct insn_label_list
*next
;
1107 static struct insn_label_list
*insn_labels
;
1108 static struct insn_label_list
*free_insn_labels
;
1110 static void mips_clear_insn_labels (void);
1113 mips_clear_insn_labels (void)
1115 register struct insn_label_list
**pl
;
1117 for (pl
= &free_insn_labels
; *pl
!= NULL
; pl
= &(*pl
)->next
)
1123 static char *expr_end
;
1125 /* Expressions which appear in instructions. These are set by
1128 static expressionS imm_expr
;
1129 static expressionS imm2_expr
;
1130 static expressionS offset_expr
;
1132 /* Relocs associated with imm_expr and offset_expr. */
1134 static bfd_reloc_code_real_type imm_reloc
[3]
1135 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
1136 static bfd_reloc_code_real_type offset_reloc
[3]
1137 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
1139 /* These are set by mips16_ip if an explicit extension is used. */
1141 static bfd_boolean mips16_small
, mips16_ext
;
1144 /* The pdr segment for per procedure frame/regmask info. Not used for
1147 static segT pdr_seg
;
1150 /* The default target format to use. */
1153 mips_target_format (void)
1155 switch (OUTPUT_FLAVOR
)
1157 case bfd_target_ecoff_flavour
:
1158 return target_big_endian
? "ecoff-bigmips" : ECOFF_LITTLE_FORMAT
;
1159 case bfd_target_coff_flavour
:
1161 case bfd_target_elf_flavour
:
1163 /* This is traditional mips. */
1164 return (target_big_endian
1165 ? (HAVE_64BIT_OBJECTS
1166 ? "elf64-tradbigmips"
1168 ? "elf32-ntradbigmips" : "elf32-tradbigmips"))
1169 : (HAVE_64BIT_OBJECTS
1170 ? "elf64-tradlittlemips"
1172 ? "elf32-ntradlittlemips" : "elf32-tradlittlemips")));
1174 return (target_big_endian
1175 ? (HAVE_64BIT_OBJECTS
1178 ? "elf32-nbigmips" : "elf32-bigmips"))
1179 : (HAVE_64BIT_OBJECTS
1180 ? "elf64-littlemips"
1182 ? "elf32-nlittlemips" : "elf32-littlemips")));
1190 /* Return the length of instruction INSN. */
1192 static inline unsigned int
1193 insn_length (const struct mips_cl_insn
*insn
)
1195 if (!mips_opts
.mips16
)
1197 return insn
->mips16_absolute_jump_p
|| insn
->use_extend
? 4 : 2;
1200 /* Initialise INSN from opcode entry MO. Leave its position unspecified. */
1203 create_insn (struct mips_cl_insn
*insn
, const struct mips_opcode
*mo
)
1208 insn
->use_extend
= FALSE
;
1210 insn
->insn_opcode
= mo
->match
;
1213 for (i
= 0; i
< ARRAY_SIZE (insn
->fixp
); i
++)
1214 insn
->fixp
[i
] = NULL
;
1215 insn
->fixed_p
= (mips_opts
.noreorder
> 0);
1216 insn
->noreorder_p
= (mips_opts
.noreorder
> 0);
1217 insn
->mips16_absolute_jump_p
= 0;
1220 /* Install INSN at the location specified by its "frag" and "where" fields. */
1223 install_insn (const struct mips_cl_insn
*insn
)
1225 char *f
= insn
->frag
->fr_literal
+ insn
->where
;
1226 if (!mips_opts
.mips16
)
1227 md_number_to_chars (f
, insn
->insn_opcode
, 4);
1228 else if (insn
->mips16_absolute_jump_p
)
1230 md_number_to_chars (f
, insn
->insn_opcode
>> 16, 2);
1231 md_number_to_chars (f
+ 2, insn
->insn_opcode
& 0xffff, 2);
1235 if (insn
->use_extend
)
1237 md_number_to_chars (f
, 0xf000 | insn
->extend
, 2);
1240 md_number_to_chars (f
, insn
->insn_opcode
, 2);
1244 /* Move INSN to offset WHERE in FRAG. Adjust the fixups accordingly
1245 and install the opcode in the new location. */
1248 move_insn (struct mips_cl_insn
*insn
, fragS
*frag
, long where
)
1253 insn
->where
= where
;
1254 for (i
= 0; i
< ARRAY_SIZE (insn
->fixp
); i
++)
1255 if (insn
->fixp
[i
] != NULL
)
1257 insn
->fixp
[i
]->fx_frag
= frag
;
1258 insn
->fixp
[i
]->fx_where
= where
;
1260 install_insn (insn
);
1263 /* Add INSN to the end of the output. */
1266 add_fixed_insn (struct mips_cl_insn
*insn
)
1268 char *f
= frag_more (insn_length (insn
));
1269 move_insn (insn
, frag_now
, f
- frag_now
->fr_literal
);
1272 /* Start a variant frag and move INSN to the start of the variant part,
1273 marking it as fixed. The other arguments are as for frag_var. */
1276 add_relaxed_insn (struct mips_cl_insn
*insn
, int max_chars
, int var
,
1277 relax_substateT subtype
, symbolS
*symbol
, offsetT offset
)
1279 frag_grow (max_chars
);
1280 move_insn (insn
, frag_now
, frag_more (0) - frag_now
->fr_literal
);
1282 frag_var (rs_machine_dependent
, max_chars
, var
,
1283 subtype
, symbol
, offset
, NULL
);
1286 /* Insert N copies of INSN into the history buffer, starting at
1287 position FIRST. Neither FIRST nor N need to be clipped. */
1290 insert_into_history (unsigned int first
, unsigned int n
,
1291 const struct mips_cl_insn
*insn
)
1293 if (mips_relax
.sequence
!= 2)
1297 for (i
= ARRAY_SIZE (history
); i
-- > first
;)
1299 history
[i
] = history
[i
- n
];
1305 /* Emit a nop instruction, recording it in the history buffer. */
1310 add_fixed_insn (NOP_INSN
);
1311 insert_into_history (0, 1, NOP_INSN
);
1314 /* Initialize vr4120_conflicts. There is a bit of duplication here:
1315 the idea is to make it obvious at a glance that each errata is
1319 init_vr4120_conflicts (void)
1321 #define CONFLICT(FIRST, SECOND) \
1322 vr4120_conflicts[FIX_VR4120_##FIRST] |= 1 << FIX_VR4120_##SECOND
1324 /* Errata 21 - [D]DIV[U] after [D]MACC */
1325 CONFLICT (MACC
, DIV
);
1326 CONFLICT (DMACC
, DIV
);
1328 /* Errata 23 - Continuous DMULT[U]/DMACC instructions. */
1329 CONFLICT (DMULT
, DMULT
);
1330 CONFLICT (DMULT
, DMACC
);
1331 CONFLICT (DMACC
, DMULT
);
1332 CONFLICT (DMACC
, DMACC
);
1334 /* Errata 24 - MT{LO,HI} after [D]MACC */
1335 CONFLICT (MACC
, MTHILO
);
1336 CONFLICT (DMACC
, MTHILO
);
1338 /* VR4181A errata MD(1): "If a MULT, MULTU, DMULT or DMULTU
1339 instruction is executed immediately after a MACC or DMACC
1340 instruction, the result of [either instruction] is incorrect." */
1341 CONFLICT (MACC
, MULT
);
1342 CONFLICT (MACC
, DMULT
);
1343 CONFLICT (DMACC
, MULT
);
1344 CONFLICT (DMACC
, DMULT
);
1346 /* VR4181A errata MD(4): "If a MACC or DMACC instruction is
1347 executed immediately after a DMULT, DMULTU, DIV, DIVU,
1348 DDIV or DDIVU instruction, the result of the MACC or
1349 DMACC instruction is incorrect.". */
1350 CONFLICT (DMULT
, MACC
);
1351 CONFLICT (DMULT
, DMACC
);
1352 CONFLICT (DIV
, MACC
);
1353 CONFLICT (DIV
, DMACC
);
1358 /* This function is called once, at assembler startup time. It should
1359 set up all the tables, etc. that the MD part of the assembler will need. */
1364 register const char *retval
= NULL
;
1368 if (! bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, file_mips_arch
))
1369 as_warn (_("Could not set architecture and machine"));
1371 op_hash
= hash_new ();
1373 for (i
= 0; i
< NUMOPCODES
;)
1375 const char *name
= mips_opcodes
[i
].name
;
1377 retval
= hash_insert (op_hash
, name
, (void *) &mips_opcodes
[i
]);
1380 fprintf (stderr
, _("internal error: can't hash `%s': %s\n"),
1381 mips_opcodes
[i
].name
, retval
);
1382 /* Probably a memory allocation problem? Give up now. */
1383 as_fatal (_("Broken assembler. No assembly attempted."));
1387 if (mips_opcodes
[i
].pinfo
!= INSN_MACRO
)
1389 if (!validate_mips_insn (&mips_opcodes
[i
]))
1391 if (nop_insn
.insn_mo
== NULL
&& strcmp (name
, "nop") == 0)
1393 create_insn (&nop_insn
, mips_opcodes
+ i
);
1394 nop_insn
.fixed_p
= 1;
1399 while ((i
< NUMOPCODES
) && !strcmp (mips_opcodes
[i
].name
, name
));
1402 mips16_op_hash
= hash_new ();
1405 while (i
< bfd_mips16_num_opcodes
)
1407 const char *name
= mips16_opcodes
[i
].name
;
1409 retval
= hash_insert (mips16_op_hash
, name
, (void *) &mips16_opcodes
[i
]);
1411 as_fatal (_("internal: can't hash `%s': %s"),
1412 mips16_opcodes
[i
].name
, retval
);
1415 if (mips16_opcodes
[i
].pinfo
!= INSN_MACRO
1416 && ((mips16_opcodes
[i
].match
& mips16_opcodes
[i
].mask
)
1417 != mips16_opcodes
[i
].match
))
1419 fprintf (stderr
, _("internal error: bad mips16 opcode: %s %s\n"),
1420 mips16_opcodes
[i
].name
, mips16_opcodes
[i
].args
);
1423 if (mips16_nop_insn
.insn_mo
== NULL
&& strcmp (name
, "nop") == 0)
1425 create_insn (&mips16_nop_insn
, mips16_opcodes
+ i
);
1426 mips16_nop_insn
.fixed_p
= 1;
1430 while (i
< bfd_mips16_num_opcodes
1431 && strcmp (mips16_opcodes
[i
].name
, name
) == 0);
1435 as_fatal (_("Broken assembler. No assembly attempted."));
1437 /* We add all the general register names to the symbol table. This
1438 helps us detect invalid uses of them. */
1439 for (i
= 0; i
< 32; i
++)
1443 sprintf (buf
, "$%d", i
);
1444 symbol_table_insert (symbol_new (buf
, reg_section
, i
,
1445 &zero_address_frag
));
1447 symbol_table_insert (symbol_new ("$ra", reg_section
, RA
,
1448 &zero_address_frag
));
1449 symbol_table_insert (symbol_new ("$fp", reg_section
, FP
,
1450 &zero_address_frag
));
1451 symbol_table_insert (symbol_new ("$sp", reg_section
, SP
,
1452 &zero_address_frag
));
1453 symbol_table_insert (symbol_new ("$gp", reg_section
, GP
,
1454 &zero_address_frag
));
1455 symbol_table_insert (symbol_new ("$at", reg_section
, AT
,
1456 &zero_address_frag
));
1457 symbol_table_insert (symbol_new ("$kt0", reg_section
, KT0
,
1458 &zero_address_frag
));
1459 symbol_table_insert (symbol_new ("$kt1", reg_section
, KT1
,
1460 &zero_address_frag
));
1461 symbol_table_insert (symbol_new ("$zero", reg_section
, ZERO
,
1462 &zero_address_frag
));
1463 symbol_table_insert (symbol_new ("$pc", reg_section
, -1,
1464 &zero_address_frag
));
1466 /* If we don't add these register names to the symbol table, they
1467 may end up being added as regular symbols by operand(), and then
1468 make it to the object file as undefined in case they're not
1469 regarded as local symbols. They're local in o32, since `$' is a
1470 local symbol prefix, but not in n32 or n64. */
1471 for (i
= 0; i
< 8; i
++)
1475 sprintf (buf
, "$fcc%i", i
);
1476 symbol_table_insert (symbol_new (buf
, reg_section
, -1,
1477 &zero_address_frag
));
1480 mips_no_prev_insn (FALSE
);
1483 mips_cprmask
[0] = 0;
1484 mips_cprmask
[1] = 0;
1485 mips_cprmask
[2] = 0;
1486 mips_cprmask
[3] = 0;
1488 /* set the default alignment for the text section (2**2) */
1489 record_alignment (text_section
, 2);
1491 bfd_set_gp_size (stdoutput
, g_switch_value
);
1493 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
1495 /* On a native system, sections must be aligned to 16 byte
1496 boundaries. When configured for an embedded ELF target, we
1498 if (strcmp (TARGET_OS
, "elf") != 0)
1500 (void) bfd_set_section_alignment (stdoutput
, text_section
, 4);
1501 (void) bfd_set_section_alignment (stdoutput
, data_section
, 4);
1502 (void) bfd_set_section_alignment (stdoutput
, bss_section
, 4);
1505 /* Create a .reginfo section for register masks and a .mdebug
1506 section for debugging information. */
1514 subseg
= now_subseg
;
1516 /* The ABI says this section should be loaded so that the
1517 running program can access it. However, we don't load it
1518 if we are configured for an embedded target */
1519 flags
= SEC_READONLY
| SEC_DATA
;
1520 if (strcmp (TARGET_OS
, "elf") != 0)
1521 flags
|= SEC_ALLOC
| SEC_LOAD
;
1523 if (mips_abi
!= N64_ABI
)
1525 sec
= subseg_new (".reginfo", (subsegT
) 0);
1527 bfd_set_section_flags (stdoutput
, sec
, flags
);
1528 bfd_set_section_alignment (stdoutput
, sec
, HAVE_NEWABI
? 3 : 2);
1531 mips_regmask_frag
= frag_more (sizeof (Elf32_External_RegInfo
));
1536 /* The 64-bit ABI uses a .MIPS.options section rather than
1537 .reginfo section. */
1538 sec
= subseg_new (".MIPS.options", (subsegT
) 0);
1539 bfd_set_section_flags (stdoutput
, sec
, flags
);
1540 bfd_set_section_alignment (stdoutput
, sec
, 3);
1543 /* Set up the option header. */
1545 Elf_Internal_Options opthdr
;
1548 opthdr
.kind
= ODK_REGINFO
;
1549 opthdr
.size
= (sizeof (Elf_External_Options
)
1550 + sizeof (Elf64_External_RegInfo
));
1553 f
= frag_more (sizeof (Elf_External_Options
));
1554 bfd_mips_elf_swap_options_out (stdoutput
, &opthdr
,
1555 (Elf_External_Options
*) f
);
1557 mips_regmask_frag
= frag_more (sizeof (Elf64_External_RegInfo
));
1562 if (ECOFF_DEBUGGING
)
1564 sec
= subseg_new (".mdebug", (subsegT
) 0);
1565 (void) bfd_set_section_flags (stdoutput
, sec
,
1566 SEC_HAS_CONTENTS
| SEC_READONLY
);
1567 (void) bfd_set_section_alignment (stdoutput
, sec
, 2);
1570 else if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
&& mips_flag_pdr
)
1572 pdr_seg
= subseg_new (".pdr", (subsegT
) 0);
1573 (void) bfd_set_section_flags (stdoutput
, pdr_seg
,
1574 SEC_READONLY
| SEC_RELOC
1576 (void) bfd_set_section_alignment (stdoutput
, pdr_seg
, 2);
1580 subseg_set (seg
, subseg
);
1584 if (! ECOFF_DEBUGGING
)
1587 if (mips_fix_vr4120
)
1588 init_vr4120_conflicts ();
1594 if (! ECOFF_DEBUGGING
)
1599 md_assemble (char *str
)
1601 struct mips_cl_insn insn
;
1602 bfd_reloc_code_real_type unused_reloc
[3]
1603 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
1605 imm_expr
.X_op
= O_absent
;
1606 imm2_expr
.X_op
= O_absent
;
1607 offset_expr
.X_op
= O_absent
;
1608 imm_reloc
[0] = BFD_RELOC_UNUSED
;
1609 imm_reloc
[1] = BFD_RELOC_UNUSED
;
1610 imm_reloc
[2] = BFD_RELOC_UNUSED
;
1611 offset_reloc
[0] = BFD_RELOC_UNUSED
;
1612 offset_reloc
[1] = BFD_RELOC_UNUSED
;
1613 offset_reloc
[2] = BFD_RELOC_UNUSED
;
1615 if (mips_opts
.mips16
)
1616 mips16_ip (str
, &insn
);
1619 mips_ip (str
, &insn
);
1620 DBG ((_("returned from mips_ip(%s) insn_opcode = 0x%x\n"),
1621 str
, insn
.insn_opcode
));
1626 as_bad ("%s `%s'", insn_error
, str
);
1630 if (insn
.insn_mo
->pinfo
== INSN_MACRO
)
1633 if (mips_opts
.mips16
)
1634 mips16_macro (&insn
);
1641 if (imm_expr
.X_op
!= O_absent
)
1642 append_insn (&insn
, &imm_expr
, imm_reloc
);
1643 else if (offset_expr
.X_op
!= O_absent
)
1644 append_insn (&insn
, &offset_expr
, offset_reloc
);
1646 append_insn (&insn
, NULL
, unused_reloc
);
1650 /* Return true if the given relocation might need a matching %lo().
1651 Note that R_MIPS_GOT16 relocations only need a matching %lo() when
1652 applied to local symbols. */
1654 static inline bfd_boolean
1655 reloc_needs_lo_p (bfd_reloc_code_real_type reloc
)
1657 return (HAVE_IN_PLACE_ADDENDS
1658 && (reloc
== BFD_RELOC_HI16_S
1659 || reloc
== BFD_RELOC_MIPS_GOT16
1660 || reloc
== BFD_RELOC_MIPS16_HI16_S
));
1663 /* Return true if the given fixup is followed by a matching R_MIPS_LO16
1666 static inline bfd_boolean
1667 fixup_has_matching_lo_p (fixS
*fixp
)
1669 return (fixp
->fx_next
!= NULL
1670 && (fixp
->fx_next
->fx_r_type
== BFD_RELOC_LO16
1671 || fixp
->fx_next
->fx_r_type
== BFD_RELOC_MIPS16_LO16
)
1672 && fixp
->fx_addsy
== fixp
->fx_next
->fx_addsy
1673 && fixp
->fx_offset
== fixp
->fx_next
->fx_offset
);
1676 /* See whether instruction IP reads register REG. CLASS is the type
1680 insn_uses_reg (const struct mips_cl_insn
*ip
, unsigned int reg
,
1681 enum mips_regclass
class)
1683 if (class == MIPS16_REG
)
1685 assert (mips_opts
.mips16
);
1686 reg
= mips16_to_32_reg_map
[reg
];
1687 class = MIPS_GR_REG
;
1690 /* Don't report on general register ZERO, since it never changes. */
1691 if (class == MIPS_GR_REG
&& reg
== ZERO
)
1694 if (class == MIPS_FP_REG
)
1696 assert (! mips_opts
.mips16
);
1697 /* If we are called with either $f0 or $f1, we must check $f0.
1698 This is not optimal, because it will introduce an unnecessary
1699 NOP between "lwc1 $f0" and "swc1 $f1". To fix this we would
1700 need to distinguish reading both $f0 and $f1 or just one of
1701 them. Note that we don't have to check the other way,
1702 because there is no instruction that sets both $f0 and $f1
1703 and requires a delay. */
1704 if ((ip
->insn_mo
->pinfo
& INSN_READ_FPR_S
)
1705 && ((EXTRACT_OPERAND (FS
, *ip
) & ~(unsigned) 1)
1706 == (reg
&~ (unsigned) 1)))
1708 if ((ip
->insn_mo
->pinfo
& INSN_READ_FPR_T
)
1709 && ((EXTRACT_OPERAND (FT
, *ip
) & ~(unsigned) 1)
1710 == (reg
&~ (unsigned) 1)))
1713 else if (! mips_opts
.mips16
)
1715 if ((ip
->insn_mo
->pinfo
& INSN_READ_GPR_S
)
1716 && EXTRACT_OPERAND (RS
, *ip
) == reg
)
1718 if ((ip
->insn_mo
->pinfo
& INSN_READ_GPR_T
)
1719 && EXTRACT_OPERAND (RT
, *ip
) == reg
)
1724 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_X
)
1725 && mips16_to_32_reg_map
[MIPS16_EXTRACT_OPERAND (RX
, *ip
)] == reg
)
1727 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_Y
)
1728 && mips16_to_32_reg_map
[MIPS16_EXTRACT_OPERAND (RY
, *ip
)] == reg
)
1730 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_Z
)
1731 && (mips16_to_32_reg_map
[MIPS16_EXTRACT_OPERAND (MOVE32Z
, *ip
)]
1734 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_T
) && reg
== TREG
)
1736 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_SP
) && reg
== SP
)
1738 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_31
) && reg
== RA
)
1740 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_GPR_X
)
1741 && MIPS16_EXTRACT_OPERAND (REGR32
, *ip
) == reg
)
1748 /* This function returns true if modifying a register requires a
1752 reg_needs_delay (unsigned int reg
)
1754 unsigned long prev_pinfo
;
1756 prev_pinfo
= history
[0].insn_mo
->pinfo
;
1757 if (! mips_opts
.noreorder
1758 && (((prev_pinfo
& INSN_LOAD_MEMORY_DELAY
)
1759 && ! gpr_interlocks
)
1760 || ((prev_pinfo
& INSN_LOAD_COPROC_DELAY
)
1761 && ! cop_interlocks
)))
1763 /* A load from a coprocessor or from memory. All load delays
1764 delay the use of general register rt for one instruction. */
1765 /* Itbl support may require additional care here. */
1766 know (prev_pinfo
& INSN_WRITE_GPR_T
);
1767 if (reg
== EXTRACT_OPERAND (RT
, history
[0]))
1774 /* Mark instruction labels in mips16 mode. This permits the linker to
1775 handle them specially, such as generating jalx instructions when
1776 needed. We also make them odd for the duration of the assembly, in
1777 order to generate the right sort of code. We will make them even
1778 in the adjust_symtab routine, while leaving them marked. This is
1779 convenient for the debugger and the disassembler. The linker knows
1780 to make them odd again. */
1783 mips16_mark_labels (void)
1785 if (mips_opts
.mips16
)
1787 struct insn_label_list
*l
;
1790 for (l
= insn_labels
; l
!= NULL
; l
= l
->next
)
1793 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
1794 S_SET_OTHER (l
->label
, STO_MIPS16
);
1796 val
= S_GET_VALUE (l
->label
);
1798 S_SET_VALUE (l
->label
, val
+ 1);
1803 /* End the current frag. Make it a variant frag and record the
1807 relax_close_frag (void)
1809 mips_macro_warning
.first_frag
= frag_now
;
1810 frag_var (rs_machine_dependent
, 0, 0,
1811 RELAX_ENCODE (mips_relax
.sizes
[0], mips_relax
.sizes
[1]),
1812 mips_relax
.symbol
, 0, (char *) mips_relax
.first_fixup
);
1814 memset (&mips_relax
.sizes
, 0, sizeof (mips_relax
.sizes
));
1815 mips_relax
.first_fixup
= 0;
1818 /* Start a new relaxation sequence whose expansion depends on SYMBOL.
1819 See the comment above RELAX_ENCODE for more details. */
1822 relax_start (symbolS
*symbol
)
1824 assert (mips_relax
.sequence
== 0);
1825 mips_relax
.sequence
= 1;
1826 mips_relax
.symbol
= symbol
;
1829 /* Start generating the second version of a relaxable sequence.
1830 See the comment above RELAX_ENCODE for more details. */
1835 assert (mips_relax
.sequence
== 1);
1836 mips_relax
.sequence
= 2;
1839 /* End the current relaxable sequence. */
1844 assert (mips_relax
.sequence
== 2);
1845 relax_close_frag ();
1846 mips_relax
.sequence
= 0;
1849 /* Classify an instruction according to the FIX_VR4120_* enumeration.
1850 Return NUM_FIX_VR4120_CLASSES if the instruction isn't affected
1851 by VR4120 errata. */
1854 classify_vr4120_insn (const char *name
)
1856 if (strncmp (name
, "macc", 4) == 0)
1857 return FIX_VR4120_MACC
;
1858 if (strncmp (name
, "dmacc", 5) == 0)
1859 return FIX_VR4120_DMACC
;
1860 if (strncmp (name
, "mult", 4) == 0)
1861 return FIX_VR4120_MULT
;
1862 if (strncmp (name
, "dmult", 5) == 0)
1863 return FIX_VR4120_DMULT
;
1864 if (strstr (name
, "div"))
1865 return FIX_VR4120_DIV
;
1866 if (strcmp (name
, "mtlo") == 0 || strcmp (name
, "mthi") == 0)
1867 return FIX_VR4120_MTHILO
;
1868 return NUM_FIX_VR4120_CLASSES
;
1871 /* Return the number of instructions that must separate INSN1 and INSN2,
1872 where INSN1 is the earlier instruction. Return the worst-case value
1873 for any INSN2 if INSN2 is null. */
1876 insns_between (const struct mips_cl_insn
*insn1
,
1877 const struct mips_cl_insn
*insn2
)
1879 unsigned long pinfo1
, pinfo2
;
1881 /* This function needs to know which pinfo flags are set for INSN2
1882 and which registers INSN2 uses. The former is stored in PINFO2 and
1883 the latter is tested via INSN2_USES_REG. If INSN2 is null, PINFO2
1884 will have every flag set and INSN2_USES_REG will always return true. */
1885 pinfo1
= insn1
->insn_mo
->pinfo
;
1886 pinfo2
= insn2
? insn2
->insn_mo
->pinfo
: ~0U;
1888 #define INSN2_USES_REG(REG, CLASS) \
1889 (insn2 == NULL || insn_uses_reg (insn2, REG, CLASS))
1891 /* For most targets, write-after-read dependencies on the HI and LO
1892 registers must be separated by at least two instructions. */
1893 if (!hilo_interlocks
)
1895 if ((pinfo1
& INSN_READ_LO
) && (pinfo2
& INSN_WRITE_LO
))
1897 if ((pinfo1
& INSN_READ_HI
) && (pinfo2
& INSN_WRITE_HI
))
1901 /* If we're working around r7000 errata, there must be two instructions
1902 between an mfhi or mflo and any instruction that uses the result. */
1903 if (mips_7000_hilo_fix
1904 && MF_HILO_INSN (pinfo1
)
1905 && INSN2_USES_REG (EXTRACT_OPERAND (RD
, *insn1
), MIPS_GR_REG
))
1908 /* If working around VR4120 errata, check for combinations that need
1909 a single intervening instruction. */
1910 if (mips_fix_vr4120
)
1912 unsigned int class1
, class2
;
1914 class1
= classify_vr4120_insn (insn1
->insn_mo
->name
);
1915 if (class1
!= NUM_FIX_VR4120_CLASSES
&& vr4120_conflicts
[class1
] != 0)
1919 class2
= classify_vr4120_insn (insn2
->insn_mo
->name
);
1920 if (vr4120_conflicts
[class1
] & (1 << class2
))
1925 if (!mips_opts
.mips16
)
1927 /* Check for GPR or coprocessor load delays. All such delays
1928 are on the RT register. */
1929 /* Itbl support may require additional care here. */
1930 if ((!gpr_interlocks
&& (pinfo1
& INSN_LOAD_MEMORY_DELAY
))
1931 || (!cop_interlocks
&& (pinfo1
& INSN_LOAD_COPROC_DELAY
)))
1933 know (pinfo1
& INSN_WRITE_GPR_T
);
1934 if (INSN2_USES_REG (EXTRACT_OPERAND (RT
, *insn1
), MIPS_GR_REG
))
1938 /* Check for generic coprocessor hazards.
1940 This case is not handled very well. There is no special
1941 knowledge of CP0 handling, and the coprocessors other than
1942 the floating point unit are not distinguished at all. */
1943 /* Itbl support may require additional care here. FIXME!
1944 Need to modify this to include knowledge about
1945 user specified delays! */
1946 else if ((!cop_interlocks
&& (pinfo1
& INSN_COPROC_MOVE_DELAY
))
1947 || (!cop_mem_interlocks
&& (pinfo1
& INSN_COPROC_MEMORY_DELAY
)))
1949 /* Handle cases where INSN1 writes to a known general coprocessor
1950 register. There must be a one instruction delay before INSN2
1951 if INSN2 reads that register, otherwise no delay is needed. */
1952 if (pinfo1
& INSN_WRITE_FPR_T
)
1954 if (INSN2_USES_REG (EXTRACT_OPERAND (FT
, *insn1
), MIPS_FP_REG
))
1957 else if (pinfo1
& INSN_WRITE_FPR_S
)
1959 if (INSN2_USES_REG (EXTRACT_OPERAND (FS
, *insn1
), MIPS_FP_REG
))
1964 /* Read-after-write dependencies on the control registers
1965 require a two-instruction gap. */
1966 if ((pinfo1
& INSN_WRITE_COND_CODE
)
1967 && (pinfo2
& INSN_READ_COND_CODE
))
1970 /* We don't know exactly what INSN1 does. If INSN2 is
1971 also a coprocessor instruction, assume there must be
1972 a one instruction gap. */
1973 if (pinfo2
& INSN_COP
)
1978 /* Check for read-after-write dependencies on the coprocessor
1979 control registers in cases where INSN1 does not need a general
1980 coprocessor delay. This means that INSN1 is a floating point
1981 comparison instruction. */
1982 /* Itbl support may require additional care here. */
1983 else if (!cop_interlocks
1984 && (pinfo1
& INSN_WRITE_COND_CODE
)
1985 && (pinfo2
& INSN_READ_COND_CODE
))
1989 #undef INSN2_USES_REG
1994 /* Return the number of nops that would be needed if instruction INSN
1995 immediately followed the MAX_NOPS instructions given by HISTORY,
1996 where HISTORY[0] is the most recent instruction. If INSN is null,
1997 return the worse-case number of nops for any instruction. */
2000 nops_for_insn (const struct mips_cl_insn
*history
,
2001 const struct mips_cl_insn
*insn
)
2003 int i
, nops
, tmp_nops
;
2006 for (i
= 0; i
< MAX_NOPS
; i
++)
2007 if (!history
[i
].noreorder_p
)
2009 tmp_nops
= insns_between (history
+ i
, insn
) - i
;
2010 if (tmp_nops
> nops
)
2016 /* The variable arguments provide NUM_INSNS extra instructions that
2017 might be added to HISTORY. Return the largest number of nops that
2018 would be needed after the extended sequence. */
2021 nops_for_sequence (int num_insns
, const struct mips_cl_insn
*history
, ...)
2024 struct mips_cl_insn buffer
[MAX_NOPS
];
2025 struct mips_cl_insn
*cursor
;
2028 va_start (args
, history
);
2029 cursor
= buffer
+ num_insns
;
2030 memcpy (cursor
, history
, (MAX_NOPS
- num_insns
) * sizeof (*cursor
));
2031 while (cursor
> buffer
)
2032 *--cursor
= *va_arg (args
, const struct mips_cl_insn
*);
2034 nops
= nops_for_insn (buffer
, NULL
);
2039 /* Like nops_for_insn, but if INSN is a branch, take into account the
2040 worst-case delay for the branch target. */
2043 nops_for_insn_or_target (const struct mips_cl_insn
*history
,
2044 const struct mips_cl_insn
*insn
)
2048 nops
= nops_for_insn (history
, insn
);
2049 if (insn
->insn_mo
->pinfo
& (INSN_UNCOND_BRANCH_DELAY
2050 | INSN_COND_BRANCH_DELAY
2051 | INSN_COND_BRANCH_LIKELY
))
2053 tmp_nops
= nops_for_sequence (2, history
, insn
, NOP_INSN
);
2054 if (tmp_nops
> nops
)
2057 else if (mips_opts
.mips16
&& (insn
->insn_mo
->pinfo
& MIPS16_INSN_BRANCH
))
2059 tmp_nops
= nops_for_sequence (1, history
, insn
);
2060 if (tmp_nops
> nops
)
2066 /* Output an instruction. IP is the instruction information.
2067 ADDRESS_EXPR is an operand of the instruction to be used with
2071 append_insn (struct mips_cl_insn
*ip
, expressionS
*address_expr
,
2072 bfd_reloc_code_real_type
*reloc_type
)
2074 register unsigned long prev_pinfo
, pinfo
;
2075 relax_stateT prev_insn_frag_type
= 0;
2076 bfd_boolean relaxed_branch
= FALSE
;
2078 /* Mark instruction labels in mips16 mode. */
2079 mips16_mark_labels ();
2081 prev_pinfo
= history
[0].insn_mo
->pinfo
;
2082 pinfo
= ip
->insn_mo
->pinfo
;
2084 if (mips_relax
.sequence
!= 2 && !mips_opts
.noreorder
)
2086 /* There are a lot of optimizations we could do that we don't.
2087 In particular, we do not, in general, reorder instructions.
2088 If you use gcc with optimization, it will reorder
2089 instructions and generally do much more optimization then we
2090 do here; repeating all that work in the assembler would only
2091 benefit hand written assembly code, and does not seem worth
2093 int nops
= (mips_optimize
== 0
2094 ? nops_for_insn (history
, NULL
)
2095 : nops_for_insn_or_target (history
, ip
));
2099 unsigned long old_frag_offset
;
2101 struct insn_label_list
*l
;
2103 old_frag
= frag_now
;
2104 old_frag_offset
= frag_now_fix ();
2106 for (i
= 0; i
< nops
; i
++)
2111 listing_prev_line ();
2112 /* We may be at the start of a variant frag. In case we
2113 are, make sure there is enough space for the frag
2114 after the frags created by listing_prev_line. The
2115 argument to frag_grow here must be at least as large
2116 as the argument to all other calls to frag_grow in
2117 this file. We don't have to worry about being in the
2118 middle of a variant frag, because the variants insert
2119 all needed nop instructions themselves. */
2123 for (l
= insn_labels
; l
!= NULL
; l
= l
->next
)
2127 assert (S_GET_SEGMENT (l
->label
) == now_seg
);
2128 symbol_set_frag (l
->label
, frag_now
);
2129 val
= (valueT
) frag_now_fix ();
2130 /* mips16 text labels are stored as odd. */
2131 if (mips_opts
.mips16
)
2133 S_SET_VALUE (l
->label
, val
);
2136 #ifndef NO_ECOFF_DEBUGGING
2137 if (ECOFF_DEBUGGING
)
2138 ecoff_fix_loc (old_frag
, old_frag_offset
);
2142 else if (mips_relax
.sequence
!= 2 && prev_nop_frag
!= NULL
)
2144 /* Work out how many nops in prev_nop_frag are needed by IP. */
2145 int nops
= nops_for_insn_or_target (history
, ip
);
2146 assert (nops
<= prev_nop_frag_holds
);
2148 /* Enforce NOPS as a minimum. */
2149 if (nops
> prev_nop_frag_required
)
2150 prev_nop_frag_required
= nops
;
2152 if (prev_nop_frag_holds
== prev_nop_frag_required
)
2154 /* Settle for the current number of nops. Update the history
2155 accordingly (for the benefit of any future .set reorder code). */
2156 prev_nop_frag
= NULL
;
2157 insert_into_history (prev_nop_frag_since
,
2158 prev_nop_frag_holds
, NOP_INSN
);
2162 /* Allow this instruction to replace one of the nops that was
2163 tentatively added to prev_nop_frag. */
2164 prev_nop_frag
->fr_fix
-= mips_opts
.mips16
? 2 : 4;
2165 prev_nop_frag_holds
--;
2166 prev_nop_frag_since
++;
2171 /* The value passed to dwarf2_emit_insn is the distance between
2172 the beginning of the current instruction and the address that
2173 should be recorded in the debug tables. For MIPS16 debug info
2174 we want to use ISA-encoded addresses, so we pass -1 for an
2175 address higher by one than the current. */
2176 dwarf2_emit_insn (mips_opts
.mips16
? -1 : 0);
2179 /* Record the frag type before frag_var. */
2180 if (history
[0].frag
)
2181 prev_insn_frag_type
= history
[0].frag
->fr_type
;
2184 && *reloc_type
== BFD_RELOC_16_PCREL_S2
2185 && (pinfo
& INSN_UNCOND_BRANCH_DELAY
|| pinfo
& INSN_COND_BRANCH_DELAY
2186 || pinfo
& INSN_COND_BRANCH_LIKELY
)
2187 && mips_relax_branch
2188 /* Don't try branch relaxation within .set nomacro, or within
2189 .set noat if we use $at for PIC computations. If it turns
2190 out that the branch was out-of-range, we'll get an error. */
2191 && !mips_opts
.warn_about_macros
2192 && !(mips_opts
.noat
&& mips_pic
!= NO_PIC
)
2193 && !mips_opts
.mips16
)
2195 relaxed_branch
= TRUE
;
2196 add_relaxed_insn (ip
, (relaxed_branch_length
2198 (pinfo
& INSN_UNCOND_BRANCH_DELAY
) ? -1
2199 : (pinfo
& INSN_COND_BRANCH_LIKELY
) ? 1
2202 (pinfo
& INSN_UNCOND_BRANCH_DELAY
,
2203 pinfo
& INSN_COND_BRANCH_LIKELY
,
2204 pinfo
& INSN_WRITE_GPR_31
,
2206 address_expr
->X_add_symbol
,
2207 address_expr
->X_add_number
);
2208 *reloc_type
= BFD_RELOC_UNUSED
;
2210 else if (*reloc_type
> BFD_RELOC_UNUSED
)
2212 /* We need to set up a variant frag. */
2213 assert (mips_opts
.mips16
&& address_expr
!= NULL
);
2214 add_relaxed_insn (ip
, 4, 0,
2216 (*reloc_type
- BFD_RELOC_UNUSED
,
2217 mips16_small
, mips16_ext
,
2218 prev_pinfo
& INSN_UNCOND_BRANCH_DELAY
,
2219 history
[0].mips16_absolute_jump_p
),
2220 make_expr_symbol (address_expr
), 0);
2222 else if (mips_opts
.mips16
2224 && *reloc_type
!= BFD_RELOC_MIPS16_JMP
)
2226 /* Make sure there is enough room to swap this instruction with
2227 a following jump instruction. */
2229 add_fixed_insn (ip
);
2233 if (mips_opts
.mips16
2234 && mips_opts
.noreorder
2235 && (prev_pinfo
& INSN_UNCOND_BRANCH_DELAY
) != 0)
2236 as_warn (_("extended instruction in delay slot"));
2238 if (mips_relax
.sequence
)
2240 /* If we've reached the end of this frag, turn it into a variant
2241 frag and record the information for the instructions we've
2243 if (frag_room () < 4)
2244 relax_close_frag ();
2245 mips_relax
.sizes
[mips_relax
.sequence
- 1] += 4;
2248 if (mips_relax
.sequence
!= 2)
2249 mips_macro_warning
.sizes
[0] += 4;
2250 if (mips_relax
.sequence
!= 1)
2251 mips_macro_warning
.sizes
[1] += 4;
2253 if (mips_opts
.mips16
)
2256 ip
->mips16_absolute_jump_p
= (*reloc_type
== BFD_RELOC_MIPS16_JMP
);
2258 add_fixed_insn (ip
);
2261 if (address_expr
!= NULL
&& *reloc_type
<= BFD_RELOC_UNUSED
)
2263 if (address_expr
->X_op
== O_constant
)
2267 switch (*reloc_type
)
2270 ip
->insn_opcode
|= address_expr
->X_add_number
;
2273 case BFD_RELOC_MIPS_HIGHEST
:
2274 tmp
= (address_expr
->X_add_number
+ 0x800080008000ull
) >> 48;
2275 ip
->insn_opcode
|= tmp
& 0xffff;
2278 case BFD_RELOC_MIPS_HIGHER
:
2279 tmp
= (address_expr
->X_add_number
+ 0x80008000ull
) >> 32;
2280 ip
->insn_opcode
|= tmp
& 0xffff;
2283 case BFD_RELOC_HI16_S
:
2284 tmp
= (address_expr
->X_add_number
+ 0x8000) >> 16;
2285 ip
->insn_opcode
|= tmp
& 0xffff;
2288 case BFD_RELOC_HI16
:
2289 ip
->insn_opcode
|= (address_expr
->X_add_number
>> 16) & 0xffff;
2292 case BFD_RELOC_UNUSED
:
2293 case BFD_RELOC_LO16
:
2294 case BFD_RELOC_MIPS_GOT_DISP
:
2295 ip
->insn_opcode
|= address_expr
->X_add_number
& 0xffff;
2298 case BFD_RELOC_MIPS_JMP
:
2299 if ((address_expr
->X_add_number
& 3) != 0)
2300 as_bad (_("jump to misaligned address (0x%lx)"),
2301 (unsigned long) address_expr
->X_add_number
);
2302 if (address_expr
->X_add_number
& ~0xfffffff)
2303 as_bad (_("jump address range overflow (0x%lx)"),
2304 (unsigned long) address_expr
->X_add_number
);
2305 ip
->insn_opcode
|= (address_expr
->X_add_number
>> 2) & 0x3ffffff;
2308 case BFD_RELOC_MIPS16_JMP
:
2309 if ((address_expr
->X_add_number
& 3) != 0)
2310 as_bad (_("jump to misaligned address (0x%lx)"),
2311 (unsigned long) address_expr
->X_add_number
);
2312 if (address_expr
->X_add_number
& ~0xfffffff)
2313 as_bad (_("jump address range overflow (0x%lx)"),
2314 (unsigned long) address_expr
->X_add_number
);
2316 (((address_expr
->X_add_number
& 0x7c0000) << 3)
2317 | ((address_expr
->X_add_number
& 0xf800000) >> 7)
2318 | ((address_expr
->X_add_number
& 0x3fffc) >> 2));
2321 case BFD_RELOC_16_PCREL_S2
:
2328 else if (*reloc_type
< BFD_RELOC_UNUSED
)
2331 reloc_howto_type
*howto
;
2334 /* In a compound relocation, it is the final (outermost)
2335 operator that determines the relocated field. */
2336 for (i
= 1; i
< 3; i
++)
2337 if (reloc_type
[i
] == BFD_RELOC_UNUSED
)
2340 howto
= bfd_reloc_type_lookup (stdoutput
, reloc_type
[i
- 1]);
2341 ip
->fixp
[0] = fix_new_exp (ip
->frag
, ip
->where
,
2342 bfd_get_reloc_size (howto
),
2344 reloc_type
[0] == BFD_RELOC_16_PCREL_S2
,
2347 /* These relocations can have an addend that won't fit in
2348 4 octets for 64bit assembly. */
2350 && ! howto
->partial_inplace
2351 && (reloc_type
[0] == BFD_RELOC_16
2352 || reloc_type
[0] == BFD_RELOC_32
2353 || reloc_type
[0] == BFD_RELOC_MIPS_JMP
2354 || reloc_type
[0] == BFD_RELOC_HI16_S
2355 || reloc_type
[0] == BFD_RELOC_LO16
2356 || reloc_type
[0] == BFD_RELOC_GPREL16
2357 || reloc_type
[0] == BFD_RELOC_MIPS_LITERAL
2358 || reloc_type
[0] == BFD_RELOC_GPREL32
2359 || reloc_type
[0] == BFD_RELOC_64
2360 || reloc_type
[0] == BFD_RELOC_CTOR
2361 || reloc_type
[0] == BFD_RELOC_MIPS_SUB
2362 || reloc_type
[0] == BFD_RELOC_MIPS_HIGHEST
2363 || reloc_type
[0] == BFD_RELOC_MIPS_HIGHER
2364 || reloc_type
[0] == BFD_RELOC_MIPS_SCN_DISP
2365 || reloc_type
[0] == BFD_RELOC_MIPS_REL16
2366 || reloc_type
[0] == BFD_RELOC_MIPS_RELGOT
2367 || reloc_type
[0] == BFD_RELOC_MIPS16_GPREL
2368 || reloc_type
[0] == BFD_RELOC_MIPS16_HI16_S
2369 || reloc_type
[0] == BFD_RELOC_MIPS16_LO16
))
2370 ip
->fixp
[0]->fx_no_overflow
= 1;
2372 if (mips_relax
.sequence
)
2374 if (mips_relax
.first_fixup
== 0)
2375 mips_relax
.first_fixup
= ip
->fixp
[0];
2377 else if (reloc_needs_lo_p (*reloc_type
))
2379 struct mips_hi_fixup
*hi_fixup
;
2381 /* Reuse the last entry if it already has a matching %lo. */
2382 hi_fixup
= mips_hi_fixup_list
;
2384 || !fixup_has_matching_lo_p (hi_fixup
->fixp
))
2386 hi_fixup
= ((struct mips_hi_fixup
*)
2387 xmalloc (sizeof (struct mips_hi_fixup
)));
2388 hi_fixup
->next
= mips_hi_fixup_list
;
2389 mips_hi_fixup_list
= hi_fixup
;
2391 hi_fixup
->fixp
= ip
->fixp
[0];
2392 hi_fixup
->seg
= now_seg
;
2395 /* Add fixups for the second and third relocations, if given.
2396 Note that the ABI allows the second relocation to be
2397 against RSS_UNDEF, RSS_GP, RSS_GP0 or RSS_LOC. At the
2398 moment we only use RSS_UNDEF, but we could add support
2399 for the others if it ever becomes necessary. */
2400 for (i
= 1; i
< 3; i
++)
2401 if (reloc_type
[i
] != BFD_RELOC_UNUSED
)
2403 ip
->fixp
[i
] = fix_new (ip
->frag
, ip
->where
,
2404 ip
->fixp
[0]->fx_size
, NULL
, 0,
2405 FALSE
, reloc_type
[i
]);
2407 /* Use fx_tcbit to mark compound relocs. */
2408 ip
->fixp
[0]->fx_tcbit
= 1;
2409 ip
->fixp
[i
]->fx_tcbit
= 1;
2415 /* Update the register mask information. */
2416 if (! mips_opts
.mips16
)
2418 if (pinfo
& INSN_WRITE_GPR_D
)
2419 mips_gprmask
|= 1 << EXTRACT_OPERAND (RD
, *ip
);
2420 if ((pinfo
& (INSN_WRITE_GPR_T
| INSN_READ_GPR_T
)) != 0)
2421 mips_gprmask
|= 1 << EXTRACT_OPERAND (RT
, *ip
);
2422 if (pinfo
& INSN_READ_GPR_S
)
2423 mips_gprmask
|= 1 << EXTRACT_OPERAND (RS
, *ip
);
2424 if (pinfo
& INSN_WRITE_GPR_31
)
2425 mips_gprmask
|= 1 << RA
;
2426 if (pinfo
& INSN_WRITE_FPR_D
)
2427 mips_cprmask
[1] |= 1 << EXTRACT_OPERAND (FD
, *ip
);
2428 if ((pinfo
& (INSN_WRITE_FPR_S
| INSN_READ_FPR_S
)) != 0)
2429 mips_cprmask
[1] |= 1 << EXTRACT_OPERAND (FS
, *ip
);
2430 if ((pinfo
& (INSN_WRITE_FPR_T
| INSN_READ_FPR_T
)) != 0)
2431 mips_cprmask
[1] |= 1 << EXTRACT_OPERAND (FT
, *ip
);
2432 if ((pinfo
& INSN_READ_FPR_R
) != 0)
2433 mips_cprmask
[1] |= 1 << EXTRACT_OPERAND (FR
, *ip
);
2434 if (pinfo
& INSN_COP
)
2436 /* We don't keep enough information to sort these cases out.
2437 The itbl support does keep this information however, although
2438 we currently don't support itbl fprmats as part of the cop
2439 instruction. May want to add this support in the future. */
2441 /* Never set the bit for $0, which is always zero. */
2442 mips_gprmask
&= ~1 << 0;
2446 if (pinfo
& (MIPS16_INSN_WRITE_X
| MIPS16_INSN_READ_X
))
2447 mips_gprmask
|= 1 << MIPS16_EXTRACT_OPERAND (RX
, *ip
);
2448 if (pinfo
& (MIPS16_INSN_WRITE_Y
| MIPS16_INSN_READ_Y
))
2449 mips_gprmask
|= 1 << MIPS16_EXTRACT_OPERAND (RY
, *ip
);
2450 if (pinfo
& MIPS16_INSN_WRITE_Z
)
2451 mips_gprmask
|= 1 << MIPS16_EXTRACT_OPERAND (RZ
, *ip
);
2452 if (pinfo
& (MIPS16_INSN_WRITE_T
| MIPS16_INSN_READ_T
))
2453 mips_gprmask
|= 1 << TREG
;
2454 if (pinfo
& (MIPS16_INSN_WRITE_SP
| MIPS16_INSN_READ_SP
))
2455 mips_gprmask
|= 1 << SP
;
2456 if (pinfo
& (MIPS16_INSN_WRITE_31
| MIPS16_INSN_READ_31
))
2457 mips_gprmask
|= 1 << RA
;
2458 if (pinfo
& MIPS16_INSN_WRITE_GPR_Y
)
2459 mips_gprmask
|= 1 << MIPS16OP_EXTRACT_REG32R (ip
->insn_opcode
);
2460 if (pinfo
& MIPS16_INSN_READ_Z
)
2461 mips_gprmask
|= 1 << MIPS16_EXTRACT_OPERAND (MOVE32Z
, *ip
);
2462 if (pinfo
& MIPS16_INSN_READ_GPR_X
)
2463 mips_gprmask
|= 1 << MIPS16_EXTRACT_OPERAND (REGR32
, *ip
);
2466 if (mips_relax
.sequence
!= 2 && !mips_opts
.noreorder
)
2468 /* Filling the branch delay slot is more complex. We try to
2469 switch the branch with the previous instruction, which we can
2470 do if the previous instruction does not set up a condition
2471 that the branch tests and if the branch is not itself the
2472 target of any branch. */
2473 if ((pinfo
& INSN_UNCOND_BRANCH_DELAY
)
2474 || (pinfo
& INSN_COND_BRANCH_DELAY
))
2476 if (mips_optimize
< 2
2477 /* If we have seen .set volatile or .set nomove, don't
2479 || mips_opts
.nomove
!= 0
2480 /* We can't swap if the previous instruction's position
2482 || history
[0].fixed_p
2483 /* If the previous previous insn was in a .set
2484 noreorder, we can't swap. Actually, the MIPS
2485 assembler will swap in this situation. However, gcc
2486 configured -with-gnu-as will generate code like
2492 in which we can not swap the bne and INSN. If gcc is
2493 not configured -with-gnu-as, it does not output the
2495 || history
[1].noreorder_p
2496 /* If the branch is itself the target of a branch, we
2497 can not swap. We cheat on this; all we check for is
2498 whether there is a label on this instruction. If
2499 there are any branches to anything other than a
2500 label, users must use .set noreorder. */
2501 || insn_labels
!= NULL
2502 /* If the previous instruction is in a variant frag
2503 other than this branch's one, we cannot do the swap.
2504 This does not apply to the mips16, which uses variant
2505 frags for different purposes. */
2506 || (! mips_opts
.mips16
2507 && prev_insn_frag_type
== rs_machine_dependent
)
2508 /* If the branch reads the condition codes, we don't
2509 even try to swap, because in the sequence
2514 we can not swap, and I don't feel like handling that
2516 || (! mips_opts
.mips16
2517 && (pinfo
& INSN_READ_COND_CODE
)
2518 && ! cop_interlocks
)
2519 /* Check for conflicts between the branch and the instructions
2520 before the candidate delay slot. */
2521 || nops_for_insn (history
+ 1, ip
) > 0
2522 /* Check for conflicts between the swapped sequence and the
2523 target of the branch. */
2524 || nops_for_sequence (2, history
+ 1, ip
, history
) > 0
2525 /* We do not swap with a trap instruction, since it
2526 complicates trap handlers to have the trap
2527 instruction be in a delay slot. */
2528 || (prev_pinfo
& INSN_TRAP
)
2529 /* If the branch reads a register that the previous
2530 instruction sets, we can not swap. */
2531 || (! mips_opts
.mips16
2532 && (prev_pinfo
& INSN_WRITE_GPR_T
)
2533 && insn_uses_reg (ip
, EXTRACT_OPERAND (RT
, history
[0]),
2535 || (! mips_opts
.mips16
2536 && (prev_pinfo
& INSN_WRITE_GPR_D
)
2537 && insn_uses_reg (ip
, EXTRACT_OPERAND (RD
, history
[0]),
2539 || (mips_opts
.mips16
2540 && (((prev_pinfo
& MIPS16_INSN_WRITE_X
)
2542 (ip
, MIPS16_EXTRACT_OPERAND (RX
, history
[0]),
2544 || ((prev_pinfo
& MIPS16_INSN_WRITE_Y
)
2546 (ip
, MIPS16_EXTRACT_OPERAND (RY
, history
[0]),
2548 || ((prev_pinfo
& MIPS16_INSN_WRITE_Z
)
2550 (ip
, MIPS16_EXTRACT_OPERAND (RZ
, history
[0]),
2552 || ((prev_pinfo
& MIPS16_INSN_WRITE_T
)
2553 && insn_uses_reg (ip
, TREG
, MIPS_GR_REG
))
2554 || ((prev_pinfo
& MIPS16_INSN_WRITE_31
)
2555 && insn_uses_reg (ip
, RA
, MIPS_GR_REG
))
2556 || ((prev_pinfo
& MIPS16_INSN_WRITE_GPR_Y
)
2557 && insn_uses_reg (ip
,
2558 MIPS16OP_EXTRACT_REG32R
2559 (history
[0].insn_opcode
),
2561 /* If the branch writes a register that the previous
2562 instruction sets, we can not swap (we know that
2563 branches write only to RD or to $31). */
2564 || (! mips_opts
.mips16
2565 && (prev_pinfo
& INSN_WRITE_GPR_T
)
2566 && (((pinfo
& INSN_WRITE_GPR_D
)
2567 && (EXTRACT_OPERAND (RT
, history
[0])
2568 == EXTRACT_OPERAND (RD
, *ip
)))
2569 || ((pinfo
& INSN_WRITE_GPR_31
)
2570 && EXTRACT_OPERAND (RT
, history
[0]) == RA
)))
2571 || (! mips_opts
.mips16
2572 && (prev_pinfo
& INSN_WRITE_GPR_D
)
2573 && (((pinfo
& INSN_WRITE_GPR_D
)
2574 && (EXTRACT_OPERAND (RD
, history
[0])
2575 == EXTRACT_OPERAND (RD
, *ip
)))
2576 || ((pinfo
& INSN_WRITE_GPR_31
)
2577 && EXTRACT_OPERAND (RD
, history
[0]) == RA
)))
2578 || (mips_opts
.mips16
2579 && (pinfo
& MIPS16_INSN_WRITE_31
)
2580 && ((prev_pinfo
& MIPS16_INSN_WRITE_31
)
2581 || ((prev_pinfo
& MIPS16_INSN_WRITE_GPR_Y
)
2582 && (MIPS16OP_EXTRACT_REG32R (history
[0].insn_opcode
)
2584 /* If the branch writes a register that the previous
2585 instruction reads, we can not swap (we know that
2586 branches only write to RD or to $31). */
2587 || (! mips_opts
.mips16
2588 && (pinfo
& INSN_WRITE_GPR_D
)
2589 && insn_uses_reg (&history
[0],
2590 EXTRACT_OPERAND (RD
, *ip
),
2592 || (! mips_opts
.mips16
2593 && (pinfo
& INSN_WRITE_GPR_31
)
2594 && insn_uses_reg (&history
[0], RA
, MIPS_GR_REG
))
2595 || (mips_opts
.mips16
2596 && (pinfo
& MIPS16_INSN_WRITE_31
)
2597 && insn_uses_reg (&history
[0], RA
, MIPS_GR_REG
))
2598 /* If one instruction sets a condition code and the
2599 other one uses a condition code, we can not swap. */
2600 || ((pinfo
& INSN_READ_COND_CODE
)
2601 && (prev_pinfo
& INSN_WRITE_COND_CODE
))
2602 || ((pinfo
& INSN_WRITE_COND_CODE
)
2603 && (prev_pinfo
& INSN_READ_COND_CODE
))
2604 /* If the previous instruction uses the PC, we can not
2606 || (mips_opts
.mips16
2607 && (prev_pinfo
& MIPS16_INSN_READ_PC
))
2608 /* If the previous instruction had a fixup in mips16
2609 mode, we can not swap. This normally means that the
2610 previous instruction was a 4 byte branch anyhow. */
2611 || (mips_opts
.mips16
&& history
[0].fixp
[0])
2612 /* If the previous instruction is a sync, sync.l, or
2613 sync.p, we can not swap. */
2614 || (prev_pinfo
& INSN_SYNC
))
2616 /* We could do even better for unconditional branches to
2617 portions of this object file; we could pick up the
2618 instruction at the destination, put it in the delay
2619 slot, and bump the destination address. */
2620 insert_into_history (0, 1, ip
);
2622 if (mips_relax
.sequence
)
2623 mips_relax
.sizes
[mips_relax
.sequence
- 1] += 4;
2627 /* It looks like we can actually do the swap. */
2628 struct mips_cl_insn delay
= history
[0];
2629 if (mips_opts
.mips16
)
2631 know (delay
.frag
== ip
->frag
);
2632 move_insn (ip
, delay
.frag
, delay
.where
);
2633 move_insn (&delay
, ip
->frag
, ip
->where
+ insn_length (ip
));
2635 else if (relaxed_branch
)
2637 /* Add the delay slot instruction to the end of the
2638 current frag and shrink the fixed part of the
2639 original frag. If the branch occupies the tail of
2640 the latter, move it backwards to cover the gap. */
2641 delay
.frag
->fr_fix
-= 4;
2642 if (delay
.frag
== ip
->frag
)
2643 move_insn (ip
, ip
->frag
, ip
->where
- 4);
2644 add_fixed_insn (&delay
);
2648 move_insn (&delay
, ip
->frag
, ip
->where
);
2649 move_insn (ip
, history
[0].frag
, history
[0].where
);
2653 insert_into_history (0, 1, &delay
);
2656 /* If that was an unconditional branch, forget the previous
2657 insn information. */
2658 if (pinfo
& INSN_UNCOND_BRANCH_DELAY
)
2659 mips_no_prev_insn (FALSE
);
2661 else if (pinfo
& INSN_COND_BRANCH_LIKELY
)
2663 /* We don't yet optimize a branch likely. What we should do
2664 is look at the target, copy the instruction found there
2665 into the delay slot, and increment the branch to jump to
2666 the next instruction. */
2667 insert_into_history (0, 1, ip
);
2671 insert_into_history (0, 1, ip
);
2674 insert_into_history (0, 1, ip
);
2676 /* We just output an insn, so the next one doesn't have a label. */
2677 mips_clear_insn_labels ();
2680 /* This function forgets that there was any previous instruction or
2681 label. If PRESERVE is non-zero, it remembers enough information to
2682 know whether nops are needed before a noreorder section. */
2685 mips_no_prev_insn (int preserve
)
2691 prev_nop_frag
= NULL
;
2692 prev_nop_frag_holds
= 0;
2693 prev_nop_frag_required
= 0;
2694 prev_nop_frag_since
= 0;
2695 for (i
= 0; i
< ARRAY_SIZE (history
); i
++)
2696 history
[i
] = (mips_opts
.mips16
? mips16_nop_insn
: nop_insn
);
2699 for (i
= 0; i
< ARRAY_SIZE (history
); i
++)
2701 history
[i
].fixed_p
= 1;
2702 history
[i
].noreorder_p
= 0;
2703 history
[i
].mips16_absolute_jump_p
= 0;
2705 mips_clear_insn_labels ();
2708 /* This function must be called whenever we turn on noreorder or emit
2709 something other than instructions. It inserts any NOPS which might
2710 be needed by the previous instruction, and clears the information
2711 kept for the previous instructions. The INSNS parameter is true if
2712 instructions are to follow. */
2715 mips_emit_delays (bfd_boolean insns
)
2717 if (! mips_opts
.noreorder
)
2719 int nops
= nops_for_insn (history
, NULL
);
2722 struct insn_label_list
*l
;
2724 if (insns
&& mips_optimize
!= 0)
2726 /* Record the frag which holds the nop instructions, so
2727 that we can remove them if we don't need them. */
2728 frag_grow (mips_opts
.mips16
? nops
* 2 : nops
* 4);
2729 prev_nop_frag
= frag_now
;
2730 prev_nop_frag_holds
= nops
;
2731 prev_nop_frag_required
= 0;
2732 prev_nop_frag_since
= 0;
2735 for (; nops
> 0; --nops
)
2736 add_fixed_insn (NOP_INSN
);
2740 /* Move on to a new frag, so that it is safe to simply
2741 decrease the size of prev_nop_frag. */
2742 frag_wane (frag_now
);
2746 for (l
= insn_labels
; l
!= NULL
; l
= l
->next
)
2750 assert (S_GET_SEGMENT (l
->label
) == now_seg
);
2751 symbol_set_frag (l
->label
, frag_now
);
2752 val
= (valueT
) frag_now_fix ();
2753 /* mips16 text labels are stored as odd. */
2754 if (mips_opts
.mips16
)
2756 S_SET_VALUE (l
->label
, val
);
2761 /* Mark instruction labels in mips16 mode. */
2763 mips16_mark_labels ();
2765 mips_no_prev_insn (insns
);
2768 /* Set up global variables for the start of a new macro. */
2773 memset (&mips_macro_warning
.sizes
, 0, sizeof (mips_macro_warning
.sizes
));
2774 mips_macro_warning
.delay_slot_p
= (mips_opts
.noreorder
2775 && (history
[0].insn_mo
->pinfo
2776 & (INSN_UNCOND_BRANCH_DELAY
2777 | INSN_COND_BRANCH_DELAY
2778 | INSN_COND_BRANCH_LIKELY
)) != 0);
2781 /* Given that a macro is longer than 4 bytes, return the appropriate warning
2782 for it. Return null if no warning is needed. SUBTYPE is a bitmask of
2783 RELAX_DELAY_SLOT and RELAX_NOMACRO. */
2786 macro_warning (relax_substateT subtype
)
2788 if (subtype
& RELAX_DELAY_SLOT
)
2789 return _("Macro instruction expanded into multiple instructions"
2790 " in a branch delay slot");
2791 else if (subtype
& RELAX_NOMACRO
)
2792 return _("Macro instruction expanded into multiple instructions");
2797 /* Finish up a macro. Emit warnings as appropriate. */
2802 if (mips_macro_warning
.sizes
[0] > 4 || mips_macro_warning
.sizes
[1] > 4)
2804 relax_substateT subtype
;
2806 /* Set up the relaxation warning flags. */
2808 if (mips_macro_warning
.sizes
[1] > mips_macro_warning
.sizes
[0])
2809 subtype
|= RELAX_SECOND_LONGER
;
2810 if (mips_opts
.warn_about_macros
)
2811 subtype
|= RELAX_NOMACRO
;
2812 if (mips_macro_warning
.delay_slot_p
)
2813 subtype
|= RELAX_DELAY_SLOT
;
2815 if (mips_macro_warning
.sizes
[0] > 4 && mips_macro_warning
.sizes
[1] > 4)
2817 /* Either the macro has a single implementation or both
2818 implementations are longer than 4 bytes. Emit the
2820 const char *msg
= macro_warning (subtype
);
2826 /* One implementation might need a warning but the other
2827 definitely doesn't. */
2828 mips_macro_warning
.first_frag
->fr_subtype
|= subtype
;
2833 /* Read a macro's relocation codes from *ARGS and store them in *R.
2834 The first argument in *ARGS will be either the code for a single
2835 relocation or -1 followed by the three codes that make up a
2836 composite relocation. */
2839 macro_read_relocs (va_list *args
, bfd_reloc_code_real_type
*r
)
2843 next
= va_arg (*args
, int);
2845 r
[0] = (bfd_reloc_code_real_type
) next
;
2847 for (i
= 0; i
< 3; i
++)
2848 r
[i
] = (bfd_reloc_code_real_type
) va_arg (*args
, int);
2851 /* Build an instruction created by a macro expansion. This is passed
2852 a pointer to the count of instructions created so far, an
2853 expression, the name of the instruction to build, an operand format
2854 string, and corresponding arguments. */
2857 macro_build (expressionS
*ep
, const char *name
, const char *fmt
, ...)
2859 const struct mips_opcode
*mo
;
2860 struct mips_cl_insn insn
;
2861 bfd_reloc_code_real_type r
[3];
2864 va_start (args
, fmt
);
2866 if (mips_opts
.mips16
)
2868 mips16_macro_build (ep
, name
, fmt
, args
);
2873 r
[0] = BFD_RELOC_UNUSED
;
2874 r
[1] = BFD_RELOC_UNUSED
;
2875 r
[2] = BFD_RELOC_UNUSED
;
2876 mo
= (struct mips_opcode
*) hash_find (op_hash
, name
);
2878 assert (strcmp (name
, mo
->name
) == 0);
2880 /* Search until we get a match for NAME. It is assumed here that
2881 macros will never generate MDMX or MIPS-3D instructions. */
2882 while (strcmp (fmt
, mo
->args
) != 0
2883 || mo
->pinfo
== INSN_MACRO
2884 || !OPCODE_IS_MEMBER (mo
,
2886 | (file_ase_mips16
? INSN_MIPS16
: 0)),
2888 || (mips_opts
.arch
== CPU_R4650
&& (mo
->pinfo
& FP_D
) != 0))
2892 assert (strcmp (name
, mo
->name
) == 0);
2895 create_insn (&insn
, mo
);
2913 INSERT_OPERAND (SHAMT
, insn
, va_arg (args
, int));
2918 /* Note that in the macro case, these arguments are already
2919 in MSB form. (When handling the instruction in the
2920 non-macro case, these arguments are sizes from which
2921 MSB values must be calculated.) */
2922 INSERT_OPERAND (INSMSB
, insn
, va_arg (args
, int));
2928 /* Note that in the macro case, these arguments are already
2929 in MSBD form. (When handling the instruction in the
2930 non-macro case, these arguments are sizes from which
2931 MSBD values must be calculated.) */
2932 INSERT_OPERAND (EXTMSBD
, insn
, va_arg (args
, int));
2943 INSERT_OPERAND (RT
, insn
, va_arg (args
, int));
2947 INSERT_OPERAND (CODE
, insn
, va_arg (args
, int));
2952 INSERT_OPERAND (FT
, insn
, va_arg (args
, int));
2958 INSERT_OPERAND (RD
, insn
, va_arg (args
, int));
2963 int tmp
= va_arg (args
, int);
2965 INSERT_OPERAND (RT
, insn
, tmp
);
2966 INSERT_OPERAND (RD
, insn
, tmp
);
2972 INSERT_OPERAND (FS
, insn
, va_arg (args
, int));
2979 INSERT_OPERAND (SHAMT
, insn
, va_arg (args
, int));
2983 INSERT_OPERAND (FD
, insn
, va_arg (args
, int));
2987 INSERT_OPERAND (CODE20
, insn
, va_arg (args
, int));
2991 INSERT_OPERAND (CODE19
, insn
, va_arg (args
, int));
2995 INSERT_OPERAND (CODE2
, insn
, va_arg (args
, int));
3002 INSERT_OPERAND (RS
, insn
, va_arg (args
, int));
3008 macro_read_relocs (&args
, r
);
3009 assert (*r
== BFD_RELOC_GPREL16
3010 || *r
== BFD_RELOC_MIPS_LITERAL
3011 || *r
== BFD_RELOC_MIPS_HIGHER
3012 || *r
== BFD_RELOC_HI16_S
3013 || *r
== BFD_RELOC_LO16
3014 || *r
== BFD_RELOC_MIPS_GOT16
3015 || *r
== BFD_RELOC_MIPS_CALL16
3016 || *r
== BFD_RELOC_MIPS_GOT_DISP
3017 || *r
== BFD_RELOC_MIPS_GOT_PAGE
3018 || *r
== BFD_RELOC_MIPS_GOT_OFST
3019 || *r
== BFD_RELOC_MIPS_GOT_LO16
3020 || *r
== BFD_RELOC_MIPS_CALL_LO16
);
3024 macro_read_relocs (&args
, r
);
3026 && (ep
->X_op
== O_constant
3027 || (ep
->X_op
== O_symbol
3028 && (*r
== BFD_RELOC_MIPS_HIGHEST
3029 || *r
== BFD_RELOC_HI16_S
3030 || *r
== BFD_RELOC_HI16
3031 || *r
== BFD_RELOC_GPREL16
3032 || *r
== BFD_RELOC_MIPS_GOT_HI16
3033 || *r
== BFD_RELOC_MIPS_CALL_HI16
))));
3037 assert (ep
!= NULL
);
3039 * This allows macro() to pass an immediate expression for
3040 * creating short branches without creating a symbol.
3041 * Note that the expression still might come from the assembly
3042 * input, in which case the value is not checked for range nor
3043 * is a relocation entry generated (yuck).
3045 if (ep
->X_op
== O_constant
)
3047 insn
.insn_opcode
|= (ep
->X_add_number
>> 2) & 0xffff;
3051 *r
= BFD_RELOC_16_PCREL_S2
;
3055 assert (ep
!= NULL
);
3056 *r
= BFD_RELOC_MIPS_JMP
;
3060 insn
.insn_opcode
|= va_arg (args
, unsigned long);
3069 assert (*r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
3071 append_insn (&insn
, ep
, r
);
3075 mips16_macro_build (expressionS
*ep
, const char *name
, const char *fmt
,
3078 struct mips_opcode
*mo
;
3079 struct mips_cl_insn insn
;
3080 bfd_reloc_code_real_type r
[3]
3081 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
3083 mo
= (struct mips_opcode
*) hash_find (mips16_op_hash
, name
);
3085 assert (strcmp (name
, mo
->name
) == 0);
3087 while (strcmp (fmt
, mo
->args
) != 0 || mo
->pinfo
== INSN_MACRO
)
3091 assert (strcmp (name
, mo
->name
) == 0);
3094 create_insn (&insn
, mo
);
3112 MIPS16_INSERT_OPERAND (RY
, insn
, va_arg (args
, int));
3117 MIPS16_INSERT_OPERAND (RX
, insn
, va_arg (args
, int));
3121 MIPS16_INSERT_OPERAND (RZ
, insn
, va_arg (args
, int));
3125 MIPS16_INSERT_OPERAND (MOVE32Z
, insn
, va_arg (args
, int));
3135 MIPS16_INSERT_OPERAND (REGR32
, insn
, va_arg (args
, int));
3142 regno
= va_arg (args
, int);
3143 regno
= ((regno
& 7) << 2) | ((regno
& 0x18) >> 3);
3144 insn
.insn_opcode
|= regno
<< MIPS16OP_SH_REG32R
;
3165 assert (ep
!= NULL
);
3167 if (ep
->X_op
!= O_constant
)
3168 *r
= (int) BFD_RELOC_UNUSED
+ c
;
3171 mips16_immed (NULL
, 0, c
, ep
->X_add_number
, FALSE
, FALSE
,
3172 FALSE
, &insn
.insn_opcode
, &insn
.use_extend
,
3175 *r
= BFD_RELOC_UNUSED
;
3181 MIPS16_INSERT_OPERAND (IMM6
, insn
, va_arg (args
, int));
3188 assert (*r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
3190 append_insn (&insn
, ep
, r
);
3194 * Generate a "jalr" instruction with a relocation hint to the called
3195 * function. This occurs in NewABI PIC code.
3198 macro_build_jalr (expressionS
*ep
)
3207 macro_build (NULL
, "jalr", "d,s", RA
, PIC_CALL_REG
);
3209 fix_new_exp (frag_now
, f
- frag_now
->fr_literal
,
3210 4, ep
, FALSE
, BFD_RELOC_MIPS_JALR
);
3214 * Generate a "lui" instruction.
3217 macro_build_lui (expressionS
*ep
, int regnum
)
3219 expressionS high_expr
;
3220 const struct mips_opcode
*mo
;
3221 struct mips_cl_insn insn
;
3222 bfd_reloc_code_real_type r
[3]
3223 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
3224 const char *name
= "lui";
3225 const char *fmt
= "t,u";
3227 assert (! mips_opts
.mips16
);
3231 if (high_expr
.X_op
== O_constant
)
3233 /* we can compute the instruction now without a relocation entry */
3234 high_expr
.X_add_number
= ((high_expr
.X_add_number
+ 0x8000)
3236 *r
= BFD_RELOC_UNUSED
;
3240 assert (ep
->X_op
== O_symbol
);
3241 /* _gp_disp is a special case, used from s_cpload.
3242 __gnu_local_gp is used if mips_no_shared. */
3243 assert (mips_pic
== NO_PIC
3245 && strcmp (S_GET_NAME (ep
->X_add_symbol
), "_gp_disp") == 0)
3246 || (! mips_in_shared
3247 && strcmp (S_GET_NAME (ep
->X_add_symbol
),
3248 "__gnu_local_gp") == 0));
3249 *r
= BFD_RELOC_HI16_S
;
3252 mo
= hash_find (op_hash
, name
);
3253 assert (strcmp (name
, mo
->name
) == 0);
3254 assert (strcmp (fmt
, mo
->args
) == 0);
3255 create_insn (&insn
, mo
);
3257 insn
.insn_opcode
= insn
.insn_mo
->match
;
3258 INSERT_OPERAND (RT
, insn
, regnum
);
3259 if (*r
== BFD_RELOC_UNUSED
)
3261 insn
.insn_opcode
|= high_expr
.X_add_number
;
3262 append_insn (&insn
, NULL
, r
);
3265 append_insn (&insn
, &high_expr
, r
);
3268 /* Generate a sequence of instructions to do a load or store from a constant
3269 offset off of a base register (breg) into/from a target register (treg),
3270 using AT if necessary. */
3272 macro_build_ldst_constoffset (expressionS
*ep
, const char *op
,
3273 int treg
, int breg
, int dbl
)
3275 assert (ep
->X_op
== O_constant
);
3277 /* Sign-extending 32-bit constants makes their handling easier. */
3278 if (! dbl
&& ! ((ep
->X_add_number
& ~((bfd_vma
) 0x7fffffff))
3279 == ~((bfd_vma
) 0x7fffffff)))
3281 if (ep
->X_add_number
& ~((bfd_vma
) 0xffffffff))
3282 as_bad (_("constant too large"));
3284 ep
->X_add_number
= (((ep
->X_add_number
& 0xffffffff) ^ 0x80000000)
3288 /* Right now, this routine can only handle signed 32-bit constants. */
3289 if (! IS_SEXT_32BIT_NUM(ep
->X_add_number
+ 0x8000))
3290 as_warn (_("operand overflow"));
3292 if (IS_SEXT_16BIT_NUM(ep
->X_add_number
))
3294 /* Signed 16-bit offset will fit in the op. Easy! */
3295 macro_build (ep
, op
, "t,o(b)", treg
, BFD_RELOC_LO16
, breg
);
3299 /* 32-bit offset, need multiple instructions and AT, like:
3300 lui $tempreg,const_hi (BFD_RELOC_HI16_S)
3301 addu $tempreg,$tempreg,$breg
3302 <op> $treg,const_lo($tempreg) (BFD_RELOC_LO16)
3303 to handle the complete offset. */
3304 macro_build_lui (ep
, AT
);
3305 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, AT
, breg
);
3306 macro_build (ep
, op
, "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
3309 as_bad (_("Macro used $at after \".set noat\""));
3314 * Generates code to set the $at register to true (one)
3315 * if reg is less than the immediate expression.
3318 set_at (int reg
, int unsignedp
)
3320 if (imm_expr
.X_op
== O_constant
3321 && imm_expr
.X_add_number
>= -0x8000
3322 && imm_expr
.X_add_number
< 0x8000)
3323 macro_build (&imm_expr
, unsignedp
? "sltiu" : "slti", "t,r,j",
3324 AT
, reg
, BFD_RELOC_LO16
);
3327 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
3328 macro_build (NULL
, unsignedp
? "sltu" : "slt", "d,v,t", AT
, reg
, AT
);
3333 normalize_constant_expr (expressionS
*ex
)
3335 if (ex
->X_op
== O_constant
&& HAVE_32BIT_GPRS
)
3336 ex
->X_add_number
= (((ex
->X_add_number
& 0xffffffff) ^ 0x80000000)
3340 /* Warn if an expression is not a constant. */
3343 check_absolute_expr (struct mips_cl_insn
*ip
, expressionS
*ex
)
3345 if (ex
->X_op
== O_big
)
3346 as_bad (_("unsupported large constant"));
3347 else if (ex
->X_op
!= O_constant
)
3348 as_bad (_("Instruction %s requires absolute expression"), ip
->insn_mo
->name
);
3350 normalize_constant_expr (ex
);
3353 /* Count the leading zeroes by performing a binary chop. This is a
3354 bulky bit of source, but performance is a LOT better for the
3355 majority of values than a simple loop to count the bits:
3356 for (lcnt = 0; (lcnt < 32); lcnt++)
3357 if ((v) & (1 << (31 - lcnt)))
3359 However it is not code size friendly, and the gain will drop a bit
3360 on certain cached systems.
3362 #define COUNT_TOP_ZEROES(v) \
3363 (((v) & ~0xffff) == 0 \
3364 ? ((v) & ~0xff) == 0 \
3365 ? ((v) & ~0xf) == 0 \
3366 ? ((v) & ~0x3) == 0 \
3367 ? ((v) & ~0x1) == 0 \
3372 : ((v) & ~0x7) == 0 \
3375 : ((v) & ~0x3f) == 0 \
3376 ? ((v) & ~0x1f) == 0 \
3379 : ((v) & ~0x7f) == 0 \
3382 : ((v) & ~0xfff) == 0 \
3383 ? ((v) & ~0x3ff) == 0 \
3384 ? ((v) & ~0x1ff) == 0 \
3387 : ((v) & ~0x7ff) == 0 \
3390 : ((v) & ~0x3fff) == 0 \
3391 ? ((v) & ~0x1fff) == 0 \
3394 : ((v) & ~0x7fff) == 0 \
3397 : ((v) & ~0xffffff) == 0 \
3398 ? ((v) & ~0xfffff) == 0 \
3399 ? ((v) & ~0x3ffff) == 0 \
3400 ? ((v) & ~0x1ffff) == 0 \
3403 : ((v) & ~0x7ffff) == 0 \
3406 : ((v) & ~0x3fffff) == 0 \
3407 ? ((v) & ~0x1fffff) == 0 \
3410 : ((v) & ~0x7fffff) == 0 \
3413 : ((v) & ~0xfffffff) == 0 \
3414 ? ((v) & ~0x3ffffff) == 0 \
3415 ? ((v) & ~0x1ffffff) == 0 \
3418 : ((v) & ~0x7ffffff) == 0 \
3421 : ((v) & ~0x3fffffff) == 0 \
3422 ? ((v) & ~0x1fffffff) == 0 \
3425 : ((v) & ~0x7fffffff) == 0 \
3430 * This routine generates the least number of instructions necessary to load
3431 * an absolute expression value into a register.
3434 load_register (int reg
, expressionS
*ep
, int dbl
)
3437 expressionS hi32
, lo32
;
3439 if (ep
->X_op
!= O_big
)
3441 assert (ep
->X_op
== O_constant
);
3443 /* Sign-extending 32-bit constants makes their handling easier. */
3444 if (! dbl
&& ! ((ep
->X_add_number
& ~((bfd_vma
) 0x7fffffff))
3445 == ~((bfd_vma
) 0x7fffffff)))
3447 if (ep
->X_add_number
& ~((bfd_vma
) 0xffffffff))
3448 as_bad (_("constant too large"));
3450 ep
->X_add_number
= (((ep
->X_add_number
& 0xffffffff) ^ 0x80000000)
3454 if (IS_SEXT_16BIT_NUM (ep
->X_add_number
))
3456 /* We can handle 16 bit signed values with an addiu to
3457 $zero. No need to ever use daddiu here, since $zero and
3458 the result are always correct in 32 bit mode. */
3459 macro_build (ep
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
3462 else if (ep
->X_add_number
>= 0 && ep
->X_add_number
< 0x10000)
3464 /* We can handle 16 bit unsigned values with an ori to
3466 macro_build (ep
, "ori", "t,r,i", reg
, 0, BFD_RELOC_LO16
);
3469 else if ((IS_SEXT_32BIT_NUM (ep
->X_add_number
)))
3471 /* 32 bit values require an lui. */
3472 macro_build (ep
, "lui", "t,u", reg
, BFD_RELOC_HI16
);
3473 if ((ep
->X_add_number
& 0xffff) != 0)
3474 macro_build (ep
, "ori", "t,r,i", reg
, reg
, BFD_RELOC_LO16
);
3479 /* The value is larger than 32 bits. */
3481 if (HAVE_32BIT_GPRS
)
3483 as_bad (_("Number (0x%lx) larger than 32 bits"),
3484 (unsigned long) ep
->X_add_number
);
3485 macro_build (ep
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
3489 if (ep
->X_op
!= O_big
)
3492 hi32
.X_add_number
= (valueT
) hi32
.X_add_number
>> 16;
3493 hi32
.X_add_number
= (valueT
) hi32
.X_add_number
>> 16;
3494 hi32
.X_add_number
&= 0xffffffff;
3496 lo32
.X_add_number
&= 0xffffffff;
3500 assert (ep
->X_add_number
> 2);
3501 if (ep
->X_add_number
== 3)
3502 generic_bignum
[3] = 0;
3503 else if (ep
->X_add_number
> 4)
3504 as_bad (_("Number larger than 64 bits"));
3505 lo32
.X_op
= O_constant
;
3506 lo32
.X_add_number
= generic_bignum
[0] + (generic_bignum
[1] << 16);
3507 hi32
.X_op
= O_constant
;
3508 hi32
.X_add_number
= generic_bignum
[2] + (generic_bignum
[3] << 16);
3511 if (hi32
.X_add_number
== 0)
3516 unsigned long hi
, lo
;
3518 if (hi32
.X_add_number
== (offsetT
) 0xffffffff)
3520 if ((lo32
.X_add_number
& 0xffff8000) == 0xffff8000)
3522 macro_build (&lo32
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
3525 if (lo32
.X_add_number
& 0x80000000)
3527 macro_build (&lo32
, "lui", "t,u", reg
, BFD_RELOC_HI16
);
3528 if (lo32
.X_add_number
& 0xffff)
3529 macro_build (&lo32
, "ori", "t,r,i", reg
, reg
, BFD_RELOC_LO16
);
3534 /* Check for 16bit shifted constant. We know that hi32 is
3535 non-zero, so start the mask on the first bit of the hi32
3540 unsigned long himask
, lomask
;
3544 himask
= 0xffff >> (32 - shift
);
3545 lomask
= (0xffff << shift
) & 0xffffffff;
3549 himask
= 0xffff << (shift
- 32);
3552 if ((hi32
.X_add_number
& ~(offsetT
) himask
) == 0
3553 && (lo32
.X_add_number
& ~(offsetT
) lomask
) == 0)
3557 tmp
.X_op
= O_constant
;
3559 tmp
.X_add_number
= ((hi32
.X_add_number
<< (32 - shift
))
3560 | (lo32
.X_add_number
>> shift
));
3562 tmp
.X_add_number
= hi32
.X_add_number
>> (shift
- 32);
3563 macro_build (&tmp
, "ori", "t,r,i", reg
, 0, BFD_RELOC_LO16
);
3564 macro_build (NULL
, (shift
>= 32) ? "dsll32" : "dsll", "d,w,<",
3565 reg
, reg
, (shift
>= 32) ? shift
- 32 : shift
);
3570 while (shift
<= (64 - 16));
3572 /* Find the bit number of the lowest one bit, and store the
3573 shifted value in hi/lo. */
3574 hi
= (unsigned long) (hi32
.X_add_number
& 0xffffffff);
3575 lo
= (unsigned long) (lo32
.X_add_number
& 0xffffffff);
3579 while ((lo
& 1) == 0)
3584 lo
|= (hi
& (((unsigned long) 1 << bit
) - 1)) << (32 - bit
);
3590 while ((hi
& 1) == 0)
3599 /* Optimize if the shifted value is a (power of 2) - 1. */
3600 if ((hi
== 0 && ((lo
+ 1) & lo
) == 0)
3601 || (lo
== 0xffffffff && ((hi
+ 1) & hi
) == 0))
3603 shift
= COUNT_TOP_ZEROES ((unsigned int) hi32
.X_add_number
);
3608 /* This instruction will set the register to be all
3610 tmp
.X_op
= O_constant
;
3611 tmp
.X_add_number
= (offsetT
) -1;
3612 macro_build (&tmp
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
3616 macro_build (NULL
, (bit
>= 32) ? "dsll32" : "dsll", "d,w,<",
3617 reg
, reg
, (bit
>= 32) ? bit
- 32 : bit
);
3619 macro_build (NULL
, (shift
>= 32) ? "dsrl32" : "dsrl", "d,w,<",
3620 reg
, reg
, (shift
>= 32) ? shift
- 32 : shift
);
3625 /* Sign extend hi32 before calling load_register, because we can
3626 generally get better code when we load a sign extended value. */
3627 if ((hi32
.X_add_number
& 0x80000000) != 0)
3628 hi32
.X_add_number
|= ~(offsetT
) 0xffffffff;
3629 load_register (reg
, &hi32
, 0);
3632 if ((lo32
.X_add_number
& 0xffff0000) == 0)
3636 macro_build (NULL
, "dsll32", "d,w,<", reg
, freg
, 0);
3644 if ((freg
== 0) && (lo32
.X_add_number
== (offsetT
) 0xffffffff))
3646 macro_build (&lo32
, "lui", "t,u", reg
, BFD_RELOC_HI16
);
3647 macro_build (NULL
, "dsrl32", "d,w,<", reg
, reg
, 0);
3653 macro_build (NULL
, "dsll", "d,w,<", reg
, freg
, 16);
3657 mid16
.X_add_number
>>= 16;
3658 macro_build (&mid16
, "ori", "t,r,i", reg
, freg
, BFD_RELOC_LO16
);
3659 macro_build (NULL
, "dsll", "d,w,<", reg
, reg
, 16);
3662 if ((lo32
.X_add_number
& 0xffff) != 0)
3663 macro_build (&lo32
, "ori", "t,r,i", reg
, freg
, BFD_RELOC_LO16
);
3667 load_delay_nop (void)
3669 if (!gpr_interlocks
)
3670 macro_build (NULL
, "nop", "");
3673 /* Load an address into a register. */
3676 load_address (int reg
, expressionS
*ep
, int *used_at
)
3678 if (ep
->X_op
!= O_constant
3679 && ep
->X_op
!= O_symbol
)
3681 as_bad (_("expression too complex"));
3682 ep
->X_op
= O_constant
;
3685 if (ep
->X_op
== O_constant
)
3687 load_register (reg
, ep
, HAVE_64BIT_ADDRESSES
);
3691 if (mips_pic
== NO_PIC
)
3693 /* If this is a reference to a GP relative symbol, we want
3694 addiu $reg,$gp,<sym> (BFD_RELOC_GPREL16)
3696 lui $reg,<sym> (BFD_RELOC_HI16_S)
3697 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
3698 If we have an addend, we always use the latter form.
3700 With 64bit address space and a usable $at we want
3701 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
3702 lui $at,<sym> (BFD_RELOC_HI16_S)
3703 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
3704 daddiu $at,<sym> (BFD_RELOC_LO16)
3708 If $at is already in use, we use a path which is suboptimal
3709 on superscalar processors.
3710 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
3711 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
3713 daddiu $reg,<sym> (BFD_RELOC_HI16_S)
3715 daddiu $reg,<sym> (BFD_RELOC_LO16)
3717 For GP relative symbols in 64bit address space we can use
3718 the same sequence as in 32bit address space. */
3719 if (HAVE_64BIT_SYMBOLS
)
3721 if ((valueT
) ep
->X_add_number
<= MAX_GPREL_OFFSET
3722 && !nopic_need_relax (ep
->X_add_symbol
, 1))
3724 relax_start (ep
->X_add_symbol
);
3725 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
,
3726 mips_gp_register
, BFD_RELOC_GPREL16
);
3730 if (*used_at
== 0 && !mips_opts
.noat
)
3732 macro_build (ep
, "lui", "t,u", reg
, BFD_RELOC_MIPS_HIGHEST
);
3733 macro_build (ep
, "lui", "t,u", AT
, BFD_RELOC_HI16_S
);
3734 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
,
3735 BFD_RELOC_MIPS_HIGHER
);
3736 macro_build (ep
, "daddiu", "t,r,j", AT
, AT
, BFD_RELOC_LO16
);
3737 macro_build (NULL
, "dsll32", "d,w,<", reg
, reg
, 0);
3738 macro_build (NULL
, "daddu", "d,v,t", reg
, reg
, AT
);
3743 macro_build (ep
, "lui", "t,u", reg
, BFD_RELOC_MIPS_HIGHEST
);
3744 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
,
3745 BFD_RELOC_MIPS_HIGHER
);
3746 macro_build (NULL
, "dsll", "d,w,<", reg
, reg
, 16);
3747 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
, BFD_RELOC_HI16_S
);
3748 macro_build (NULL
, "dsll", "d,w,<", reg
, reg
, 16);
3749 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
, BFD_RELOC_LO16
);
3752 if (mips_relax
.sequence
)
3757 if ((valueT
) ep
->X_add_number
<= MAX_GPREL_OFFSET
3758 && !nopic_need_relax (ep
->X_add_symbol
, 1))
3760 relax_start (ep
->X_add_symbol
);
3761 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
,
3762 mips_gp_register
, BFD_RELOC_GPREL16
);
3765 macro_build_lui (ep
, reg
);
3766 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j",
3767 reg
, reg
, BFD_RELOC_LO16
);
3768 if (mips_relax
.sequence
)
3772 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
3776 /* If this is a reference to an external symbol, we want
3777 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3779 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3781 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
3782 If there is a constant, it must be added in after.
3784 If we have NewABI, we want
3785 lw $reg,<sym+cst>($gp) (BFD_RELOC_MIPS_GOT_DISP)
3786 unless we're referencing a global symbol with a non-zero
3787 offset, in which case cst must be added separately. */
3790 if (ep
->X_add_number
)
3792 ex
.X_add_number
= ep
->X_add_number
;
3793 ep
->X_add_number
= 0;
3794 relax_start (ep
->X_add_symbol
);
3795 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
3796 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
3797 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
3798 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
3799 ex
.X_op
= O_constant
;
3800 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j",
3801 reg
, reg
, BFD_RELOC_LO16
);
3802 ep
->X_add_number
= ex
.X_add_number
;
3805 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
3806 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
3807 if (mips_relax
.sequence
)
3812 ex
.X_add_number
= ep
->X_add_number
;
3813 ep
->X_add_number
= 0;
3814 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
3815 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
3817 relax_start (ep
->X_add_symbol
);
3819 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
3823 if (ex
.X_add_number
!= 0)
3825 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
3826 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
3827 ex
.X_op
= O_constant
;
3828 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j",
3829 reg
, reg
, BFD_RELOC_LO16
);
3833 else if (mips_pic
== SVR4_PIC
)
3837 /* This is the large GOT case. If this is a reference to an
3838 external symbol, we want
3839 lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
3841 lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16)
3843 Otherwise, for a reference to a local symbol in old ABI, we want
3844 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3846 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
3847 If there is a constant, it must be added in after.
3849 In the NewABI, for local symbols, with or without offsets, we want:
3850 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
3851 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
3855 ex
.X_add_number
= ep
->X_add_number
;
3856 ep
->X_add_number
= 0;
3857 relax_start (ep
->X_add_symbol
);
3858 macro_build (ep
, "lui", "t,u", reg
, BFD_RELOC_MIPS_GOT_HI16
);
3859 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
3860 reg
, reg
, mips_gp_register
);
3861 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)",
3862 reg
, BFD_RELOC_MIPS_GOT_LO16
, reg
);
3863 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
3864 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
3865 else if (ex
.X_add_number
)
3867 ex
.X_op
= O_constant
;
3868 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
3872 ep
->X_add_number
= ex
.X_add_number
;
3874 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
3875 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
3876 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
3877 BFD_RELOC_MIPS_GOT_OFST
);
3882 ex
.X_add_number
= ep
->X_add_number
;
3883 ep
->X_add_number
= 0;
3884 relax_start (ep
->X_add_symbol
);
3885 macro_build (ep
, "lui", "t,u", reg
, BFD_RELOC_MIPS_GOT_HI16
);
3886 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
3887 reg
, reg
, mips_gp_register
);
3888 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)",
3889 reg
, BFD_RELOC_MIPS_GOT_LO16
, reg
);
3891 if (reg_needs_delay (mips_gp_register
))
3893 /* We need a nop before loading from $gp. This special
3894 check is required because the lui which starts the main
3895 instruction stream does not refer to $gp, and so will not
3896 insert the nop which may be required. */
3897 macro_build (NULL
, "nop", "");
3899 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
3900 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
3902 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
3906 if (ex
.X_add_number
!= 0)
3908 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
3909 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
3910 ex
.X_op
= O_constant
;
3911 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
3919 if (mips_opts
.noat
&& *used_at
== 1)
3920 as_bad (_("Macro used $at after \".set noat\""));
3923 /* Move the contents of register SOURCE into register DEST. */
3926 move_register (int dest
, int source
)
3928 macro_build (NULL
, HAVE_32BIT_GPRS
? "addu" : "daddu", "d,v,t",
3932 /* Emit an SVR4 PIC sequence to load address LOCAL into DEST, where
3933 LOCAL is the sum of a symbol and a 16-bit or 32-bit displacement.
3934 The two alternatives are:
3936 Global symbol Local sybmol
3937 ------------- ------------
3938 lw DEST,%got(SYMBOL) lw DEST,%got(SYMBOL + OFFSET)
3940 addiu DEST,DEST,OFFSET addiu DEST,DEST,%lo(SYMBOL + OFFSET)
3942 load_got_offset emits the first instruction and add_got_offset
3943 emits the second for a 16-bit offset or add_got_offset_hilo emits
3944 a sequence to add a 32-bit offset using a scratch register. */
3947 load_got_offset (int dest
, expressionS
*local
)
3952 global
.X_add_number
= 0;
3954 relax_start (local
->X_add_symbol
);
3955 macro_build (&global
, ADDRESS_LOAD_INSN
, "t,o(b)", dest
,
3956 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
3958 macro_build (local
, ADDRESS_LOAD_INSN
, "t,o(b)", dest
,
3959 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
3964 add_got_offset (int dest
, expressionS
*local
)
3968 global
.X_op
= O_constant
;
3969 global
.X_op_symbol
= NULL
;
3970 global
.X_add_symbol
= NULL
;
3971 global
.X_add_number
= local
->X_add_number
;
3973 relax_start (local
->X_add_symbol
);
3974 macro_build (&global
, ADDRESS_ADDI_INSN
, "t,r,j",
3975 dest
, dest
, BFD_RELOC_LO16
);
3977 macro_build (local
, ADDRESS_ADDI_INSN
, "t,r,j", dest
, dest
, BFD_RELOC_LO16
);
3982 add_got_offset_hilo (int dest
, expressionS
*local
, int tmp
)
3985 int hold_mips_optimize
;
3987 global
.X_op
= O_constant
;
3988 global
.X_op_symbol
= NULL
;
3989 global
.X_add_symbol
= NULL
;
3990 global
.X_add_number
= local
->X_add_number
;
3992 relax_start (local
->X_add_symbol
);
3993 load_register (tmp
, &global
, HAVE_64BIT_ADDRESSES
);
3995 /* Set mips_optimize around the lui instruction to avoid
3996 inserting an unnecessary nop after the lw. */
3997 hold_mips_optimize
= mips_optimize
;
3999 macro_build_lui (&global
, tmp
);
4000 mips_optimize
= hold_mips_optimize
;
4001 macro_build (local
, ADDRESS_ADDI_INSN
, "t,r,j", tmp
, tmp
, BFD_RELOC_LO16
);
4004 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", dest
, dest
, tmp
);
4009 * This routine implements the seemingly endless macro or synthesized
4010 * instructions and addressing modes in the mips assembly language. Many
4011 * of these macros are simple and are similar to each other. These could
4012 * probably be handled by some kind of table or grammar approach instead of
4013 * this verbose method. Others are not simple macros but are more like
4014 * optimizing code generation.
4015 * One interesting optimization is when several store macros appear
4016 * consecutively that would load AT with the upper half of the same address.
4017 * The ensuing load upper instructions are ommited. This implies some kind
4018 * of global optimization. We currently only optimize within a single macro.
4019 * For many of the load and store macros if the address is specified as a
4020 * constant expression in the first 64k of memory (ie ld $2,0x4000c) we
4021 * first load register 'at' with zero and use it as the base register. The
4022 * mips assembler simply uses register $zero. Just one tiny optimization
4026 macro (struct mips_cl_insn
*ip
)
4028 register int treg
, sreg
, dreg
, breg
;
4044 bfd_reloc_code_real_type r
;
4045 int hold_mips_optimize
;
4047 assert (! mips_opts
.mips16
);
4049 treg
= (ip
->insn_opcode
>> 16) & 0x1f;
4050 dreg
= (ip
->insn_opcode
>> 11) & 0x1f;
4051 sreg
= breg
= (ip
->insn_opcode
>> 21) & 0x1f;
4052 mask
= ip
->insn_mo
->mask
;
4054 expr1
.X_op
= O_constant
;
4055 expr1
.X_op_symbol
= NULL
;
4056 expr1
.X_add_symbol
= NULL
;
4057 expr1
.X_add_number
= 1;
4069 mips_emit_delays (TRUE
);
4070 ++mips_opts
.noreorder
;
4071 mips_any_noreorder
= 1;
4073 expr1
.X_add_number
= 8;
4074 macro_build (&expr1
, "bgez", "s,p", sreg
);
4076 macro_build (NULL
, "nop", "", 0);
4078 move_register (dreg
, sreg
);
4079 macro_build (NULL
, dbl
? "dsub" : "sub", "d,v,t", dreg
, 0, sreg
);
4081 --mips_opts
.noreorder
;
4102 if (imm_expr
.X_op
== O_constant
4103 && imm_expr
.X_add_number
>= -0x8000
4104 && imm_expr
.X_add_number
< 0x8000)
4106 macro_build (&imm_expr
, s
, "t,r,j", treg
, sreg
, BFD_RELOC_LO16
);
4110 load_register (AT
, &imm_expr
, dbl
);
4111 macro_build (NULL
, s2
, "d,v,t", treg
, sreg
, AT
);
4130 if (imm_expr
.X_op
== O_constant
4131 && imm_expr
.X_add_number
>= 0
4132 && imm_expr
.X_add_number
< 0x10000)
4134 if (mask
!= M_NOR_I
)
4135 macro_build (&imm_expr
, s
, "t,r,i", treg
, sreg
, BFD_RELOC_LO16
);
4138 macro_build (&imm_expr
, "ori", "t,r,i",
4139 treg
, sreg
, BFD_RELOC_LO16
);
4140 macro_build (NULL
, "nor", "d,v,t", treg
, treg
, 0);
4146 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
4147 macro_build (NULL
, s2
, "d,v,t", treg
, sreg
, AT
);
4164 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
4166 macro_build (&offset_expr
, s
, "s,t,p", sreg
, 0);
4170 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
4171 macro_build (&offset_expr
, s
, "s,t,p", sreg
, AT
);
4179 macro_build (&offset_expr
, likely
? "bgezl" : "bgez", "s,p", sreg
);
4184 macro_build (&offset_expr
, likely
? "blezl" : "blez", "s,p", treg
);
4188 macro_build (NULL
, "slt", "d,v,t", AT
, sreg
, treg
);
4189 macro_build (&offset_expr
, likely
? "beql" : "beq", "s,t,p", AT
, 0);
4195 /* check for > max integer */
4196 maxnum
= 0x7fffffff;
4197 if (HAVE_64BIT_GPRS
&& sizeof (maxnum
) > 4)
4204 if (imm_expr
.X_op
== O_constant
4205 && imm_expr
.X_add_number
>= maxnum
4206 && (HAVE_32BIT_GPRS
|| sizeof (maxnum
) > 4))
4209 /* result is always false */
4211 macro_build (NULL
, "nop", "", 0);
4213 macro_build (&offset_expr
, "bnel", "s,t,p", 0, 0);
4216 if (imm_expr
.X_op
!= O_constant
)
4217 as_bad (_("Unsupported large constant"));
4218 ++imm_expr
.X_add_number
;
4222 if (mask
== M_BGEL_I
)
4224 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
4226 macro_build (&offset_expr
, likely
? "bgezl" : "bgez", "s,p", sreg
);
4229 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
4231 macro_build (&offset_expr
, likely
? "bgtzl" : "bgtz", "s,p", sreg
);
4234 maxnum
= 0x7fffffff;
4235 if (HAVE_64BIT_GPRS
&& sizeof (maxnum
) > 4)
4242 maxnum
= - maxnum
- 1;
4243 if (imm_expr
.X_op
== O_constant
4244 && imm_expr
.X_add_number
<= maxnum
4245 && (HAVE_32BIT_GPRS
|| sizeof (maxnum
) > 4))
4248 /* result is always true */
4249 as_warn (_("Branch %s is always true"), ip
->insn_mo
->name
);
4250 macro_build (&offset_expr
, "b", "p");
4255 macro_build (&offset_expr
, likely
? "beql" : "beq", "s,t,p", AT
, 0);
4265 macro_build (&offset_expr
, likely
? "beql" : "beq",
4270 macro_build (NULL
, "sltu", "d,v,t", AT
, sreg
, treg
);
4271 macro_build (&offset_expr
, likely
? "beql" : "beq", "s,t,p", AT
, 0);
4279 && imm_expr
.X_op
== O_constant
4280 && imm_expr
.X_add_number
== (offsetT
) 0xffffffff))
4282 if (imm_expr
.X_op
!= O_constant
)
4283 as_bad (_("Unsupported large constant"));
4284 ++imm_expr
.X_add_number
;
4288 if (mask
== M_BGEUL_I
)
4290 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
4292 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
4294 macro_build (&offset_expr
, likely
? "bnel" : "bne",
4300 macro_build (&offset_expr
, likely
? "beql" : "beq", "s,t,p", AT
, 0);
4308 macro_build (&offset_expr
, likely
? "bgtzl" : "bgtz", "s,p", sreg
);
4313 macro_build (&offset_expr
, likely
? "bltzl" : "bltz", "s,p", treg
);
4317 macro_build (NULL
, "slt", "d,v,t", AT
, treg
, sreg
);
4318 macro_build (&offset_expr
, likely
? "bnel" : "bne", "s,t,p", AT
, 0);
4326 macro_build (&offset_expr
, likely
? "bnel" : "bne",
4333 macro_build (NULL
, "sltu", "d,v,t", AT
, treg
, sreg
);
4334 macro_build (&offset_expr
, likely
? "bnel" : "bne", "s,t,p", AT
, 0);
4342 macro_build (&offset_expr
, likely
? "blezl" : "blez", "s,p", sreg
);
4347 macro_build (&offset_expr
, likely
? "bgezl" : "bgez", "s,p", treg
);
4351 macro_build (NULL
, "slt", "d,v,t", AT
, treg
, sreg
);
4352 macro_build (&offset_expr
, likely
? "beql" : "beq", "s,t,p", AT
, 0);
4358 maxnum
= 0x7fffffff;
4359 if (HAVE_64BIT_GPRS
&& sizeof (maxnum
) > 4)
4366 if (imm_expr
.X_op
== O_constant
4367 && imm_expr
.X_add_number
>= maxnum
4368 && (HAVE_32BIT_GPRS
|| sizeof (maxnum
) > 4))
4370 if (imm_expr
.X_op
!= O_constant
)
4371 as_bad (_("Unsupported large constant"));
4372 ++imm_expr
.X_add_number
;
4376 if (mask
== M_BLTL_I
)
4378 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
4380 macro_build (&offset_expr
, likely
? "bltzl" : "bltz", "s,p", sreg
);
4383 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
4385 macro_build (&offset_expr
, likely
? "blezl" : "blez", "s,p", sreg
);
4390 macro_build (&offset_expr
, likely
? "bnel" : "bne", "s,t,p", AT
, 0);
4398 macro_build (&offset_expr
, likely
? "beql" : "beq",
4405 macro_build (NULL
, "sltu", "d,v,t", AT
, treg
, sreg
);
4406 macro_build (&offset_expr
, likely
? "beql" : "beq", "s,t,p", AT
, 0);
4414 && imm_expr
.X_op
== O_constant
4415 && imm_expr
.X_add_number
== (offsetT
) 0xffffffff))
4417 if (imm_expr
.X_op
!= O_constant
)
4418 as_bad (_("Unsupported large constant"));
4419 ++imm_expr
.X_add_number
;
4423 if (mask
== M_BLTUL_I
)
4425 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
4427 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
4429 macro_build (&offset_expr
, likely
? "beql" : "beq",
4435 macro_build (&offset_expr
, likely
? "bnel" : "bne", "s,t,p", AT
, 0);
4443 macro_build (&offset_expr
, likely
? "bltzl" : "bltz", "s,p", sreg
);
4448 macro_build (&offset_expr
, likely
? "bgtzl" : "bgtz", "s,p", treg
);
4452 macro_build (NULL
, "slt", "d,v,t", AT
, sreg
, treg
);
4453 macro_build (&offset_expr
, likely
? "bnel" : "bne", "s,t,p", AT
, 0);
4463 macro_build (&offset_expr
, likely
? "bnel" : "bne",
4468 macro_build (NULL
, "sltu", "d,v,t", AT
, sreg
, treg
);
4469 macro_build (&offset_expr
, likely
? "bnel" : "bne", "s,t,p", AT
, 0);
4477 if (imm_expr
.X_op
!= O_constant
|| imm2_expr
.X_op
!= O_constant
)
4479 as_bad (_("Unsupported large constant"));
4484 pos
= (unsigned long) imm_expr
.X_add_number
;
4485 size
= (unsigned long) imm2_expr
.X_add_number
;
4490 as_bad (_("Improper position (%lu)"), pos
);
4493 if (size
== 0 || size
> 64
4494 || (pos
+ size
- 1) > 63)
4496 as_bad (_("Improper extract size (%lu, position %lu)"),
4501 if (size
<= 32 && pos
< 32)
4506 else if (size
<= 32)
4516 macro_build ((expressionS
*) NULL
, s
, fmt
, treg
, sreg
, pos
, size
- 1);
4525 if (imm_expr
.X_op
!= O_constant
|| imm2_expr
.X_op
!= O_constant
)
4527 as_bad (_("Unsupported large constant"));
4532 pos
= (unsigned long) imm_expr
.X_add_number
;
4533 size
= (unsigned long) imm2_expr
.X_add_number
;
4538 as_bad (_("Improper position (%lu)"), pos
);
4541 if (size
== 0 || size
> 64
4542 || (pos
+ size
- 1) > 63)
4544 as_bad (_("Improper insert size (%lu, position %lu)"),
4549 if (pos
< 32 && (pos
+ size
- 1) < 32)
4564 macro_build ((expressionS
*) NULL
, s
, fmt
, treg
, sreg
, pos
,
4581 as_warn (_("Divide by zero."));
4583 macro_build (NULL
, "teq", "s,t,q", 0, 0, 7);
4585 macro_build (NULL
, "break", "c", 7);
4589 mips_emit_delays (TRUE
);
4590 ++mips_opts
.noreorder
;
4591 mips_any_noreorder
= 1;
4594 macro_build (NULL
, "teq", "s,t,q", treg
, 0, 7);
4595 macro_build (NULL
, dbl
? "ddiv" : "div", "z,s,t", sreg
, treg
);
4599 expr1
.X_add_number
= 8;
4600 macro_build (&expr1
, "bne", "s,t,p", treg
, 0);
4601 macro_build (NULL
, dbl
? "ddiv" : "div", "z,s,t", sreg
, treg
);
4602 macro_build (NULL
, "break", "c", 7);
4604 expr1
.X_add_number
= -1;
4606 load_register (AT
, &expr1
, dbl
);
4607 expr1
.X_add_number
= mips_trap
? (dbl
? 12 : 8) : (dbl
? 20 : 16);
4608 macro_build (&expr1
, "bne", "s,t,p", treg
, AT
);
4611 expr1
.X_add_number
= 1;
4612 load_register (AT
, &expr1
, dbl
);
4613 macro_build (NULL
, "dsll32", "d,w,<", AT
, AT
, 31);
4617 expr1
.X_add_number
= 0x80000000;
4618 macro_build (&expr1
, "lui", "t,u", AT
, BFD_RELOC_HI16
);
4622 macro_build (NULL
, "teq", "s,t,q", sreg
, AT
, 6);
4623 /* We want to close the noreorder block as soon as possible, so
4624 that later insns are available for delay slot filling. */
4625 --mips_opts
.noreorder
;
4629 expr1
.X_add_number
= 8;
4630 macro_build (&expr1
, "bne", "s,t,p", sreg
, AT
);
4631 macro_build (NULL
, "nop", "", 0);
4633 /* We want to close the noreorder block as soon as possible, so
4634 that later insns are available for delay slot filling. */
4635 --mips_opts
.noreorder
;
4637 macro_build (NULL
, "break", "c", 6);
4639 macro_build (NULL
, s
, "d", dreg
);
4678 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
4680 as_warn (_("Divide by zero."));
4682 macro_build (NULL
, "teq", "s,t,q", 0, 0, 7);
4684 macro_build (NULL
, "break", "c", 7);
4687 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
4689 if (strcmp (s2
, "mflo") == 0)
4690 move_register (dreg
, sreg
);
4692 move_register (dreg
, 0);
4695 if (imm_expr
.X_op
== O_constant
4696 && imm_expr
.X_add_number
== -1
4697 && s
[strlen (s
) - 1] != 'u')
4699 if (strcmp (s2
, "mflo") == 0)
4701 macro_build (NULL
, dbl
? "dneg" : "neg", "d,w", dreg
, sreg
);
4704 move_register (dreg
, 0);
4709 load_register (AT
, &imm_expr
, dbl
);
4710 macro_build (NULL
, s
, "z,s,t", sreg
, AT
);
4711 macro_build (NULL
, s2
, "d", dreg
);
4730 mips_emit_delays (TRUE
);
4731 ++mips_opts
.noreorder
;
4732 mips_any_noreorder
= 1;
4735 macro_build (NULL
, "teq", "s,t,q", treg
, 0, 7);
4736 macro_build (NULL
, s
, "z,s,t", sreg
, treg
);
4737 /* We want to close the noreorder block as soon as possible, so
4738 that later insns are available for delay slot filling. */
4739 --mips_opts
.noreorder
;
4743 expr1
.X_add_number
= 8;
4744 macro_build (&expr1
, "bne", "s,t,p", treg
, 0);
4745 macro_build (NULL
, s
, "z,s,t", sreg
, treg
);
4747 /* We want to close the noreorder block as soon as possible, so
4748 that later insns are available for delay slot filling. */
4749 --mips_opts
.noreorder
;
4750 macro_build (NULL
, "break", "c", 7);
4752 macro_build (NULL
, s2
, "d", dreg
);
4764 /* Load the address of a symbol into a register. If breg is not
4765 zero, we then add a base register to it. */
4767 if (dbl
&& HAVE_32BIT_GPRS
)
4768 as_warn (_("dla used to load 32-bit register"));
4770 if (! dbl
&& HAVE_64BIT_OBJECTS
)
4771 as_warn (_("la used to load 64-bit address"));
4773 if (offset_expr
.X_op
== O_constant
4774 && offset_expr
.X_add_number
>= -0x8000
4775 && offset_expr
.X_add_number
< 0x8000)
4777 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
,
4778 "t,r,j", treg
, sreg
, BFD_RELOC_LO16
);
4782 if (!mips_opts
.noat
&& (treg
== breg
))
4792 if (offset_expr
.X_op
!= O_symbol
4793 && offset_expr
.X_op
!= O_constant
)
4795 as_bad (_("expression too complex"));
4796 offset_expr
.X_op
= O_constant
;
4799 if (offset_expr
.X_op
== O_constant
)
4800 load_register (tempreg
, &offset_expr
, HAVE_64BIT_ADDRESSES
);
4801 else if (mips_pic
== NO_PIC
)
4803 /* If this is a reference to a GP relative symbol, we want
4804 addiu $tempreg,$gp,<sym> (BFD_RELOC_GPREL16)
4806 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
4807 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
4808 If we have a constant, we need two instructions anyhow,
4809 so we may as well always use the latter form.
4811 With 64bit address space and a usable $at we want
4812 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
4813 lui $at,<sym> (BFD_RELOC_HI16_S)
4814 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
4815 daddiu $at,<sym> (BFD_RELOC_LO16)
4817 daddu $tempreg,$tempreg,$at
4819 If $at is already in use, we use a path which is suboptimal
4820 on superscalar processors.
4821 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
4822 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
4824 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
4826 daddiu $tempreg,<sym> (BFD_RELOC_LO16)
4828 For GP relative symbols in 64bit address space we can use
4829 the same sequence as in 32bit address space. */
4830 if (HAVE_64BIT_SYMBOLS
)
4832 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
4833 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
4835 relax_start (offset_expr
.X_add_symbol
);
4836 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
4837 tempreg
, mips_gp_register
, BFD_RELOC_GPREL16
);
4841 if (used_at
== 0 && !mips_opts
.noat
)
4843 macro_build (&offset_expr
, "lui", "t,u",
4844 tempreg
, BFD_RELOC_MIPS_HIGHEST
);
4845 macro_build (&offset_expr
, "lui", "t,u",
4846 AT
, BFD_RELOC_HI16_S
);
4847 macro_build (&offset_expr
, "daddiu", "t,r,j",
4848 tempreg
, tempreg
, BFD_RELOC_MIPS_HIGHER
);
4849 macro_build (&offset_expr
, "daddiu", "t,r,j",
4850 AT
, AT
, BFD_RELOC_LO16
);
4851 macro_build (NULL
, "dsll32", "d,w,<", tempreg
, tempreg
, 0);
4852 macro_build (NULL
, "daddu", "d,v,t", tempreg
, tempreg
, AT
);
4857 macro_build (&offset_expr
, "lui", "t,u",
4858 tempreg
, BFD_RELOC_MIPS_HIGHEST
);
4859 macro_build (&offset_expr
, "daddiu", "t,r,j",
4860 tempreg
, tempreg
, BFD_RELOC_MIPS_HIGHER
);
4861 macro_build (NULL
, "dsll", "d,w,<", tempreg
, tempreg
, 16);
4862 macro_build (&offset_expr
, "daddiu", "t,r,j",
4863 tempreg
, tempreg
, BFD_RELOC_HI16_S
);
4864 macro_build (NULL
, "dsll", "d,w,<", tempreg
, tempreg
, 16);
4865 macro_build (&offset_expr
, "daddiu", "t,r,j",
4866 tempreg
, tempreg
, BFD_RELOC_LO16
);
4869 if (mips_relax
.sequence
)
4874 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
4875 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
4877 relax_start (offset_expr
.X_add_symbol
);
4878 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
4879 tempreg
, mips_gp_register
, BFD_RELOC_GPREL16
);
4882 if (!IS_SEXT_32BIT_NUM (offset_expr
.X_add_number
))
4883 as_bad (_("offset too large"));
4884 macro_build_lui (&offset_expr
, tempreg
);
4885 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
4886 tempreg
, tempreg
, BFD_RELOC_LO16
);
4887 if (mips_relax
.sequence
)
4891 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
&& ! HAVE_NEWABI
)
4893 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT16
;
4895 /* If this is a reference to an external symbol, and there
4896 is no constant, we want
4897 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4898 or for lca or if tempreg is PIC_CALL_REG
4899 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
4900 For a local symbol, we want
4901 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4903 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
4905 If we have a small constant, and this is a reference to
4906 an external symbol, we want
4907 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4909 addiu $tempreg,$tempreg,<constant>
4910 For a local symbol, we want the same instruction
4911 sequence, but we output a BFD_RELOC_LO16 reloc on the
4914 If we have a large constant, and this is a reference to
4915 an external symbol, we want
4916 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4917 lui $at,<hiconstant>
4918 addiu $at,$at,<loconstant>
4919 addu $tempreg,$tempreg,$at
4920 For a local symbol, we want the same instruction
4921 sequence, but we output a BFD_RELOC_LO16 reloc on the
4925 if (offset_expr
.X_add_number
== 0)
4927 if (breg
== 0 && (call
|| tempreg
== PIC_CALL_REG
))
4928 lw_reloc_type
= (int) BFD_RELOC_MIPS_CALL16
;
4930 relax_start (offset_expr
.X_add_symbol
);
4931 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
4932 lw_reloc_type
, mips_gp_register
);
4935 /* We're going to put in an addu instruction using
4936 tempreg, so we may as well insert the nop right
4941 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
4942 tempreg
, BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
4944 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
4945 tempreg
, tempreg
, BFD_RELOC_LO16
);
4947 /* FIXME: If breg == 0, and the next instruction uses
4948 $tempreg, then if this variant case is used an extra
4949 nop will be generated. */
4951 else if (offset_expr
.X_add_number
>= -0x8000
4952 && offset_expr
.X_add_number
< 0x8000)
4954 load_got_offset (tempreg
, &offset_expr
);
4956 add_got_offset (tempreg
, &offset_expr
);
4960 expr1
.X_add_number
= offset_expr
.X_add_number
;
4961 offset_expr
.X_add_number
=
4962 ((offset_expr
.X_add_number
+ 0x8000) & 0xffff) - 0x8000;
4963 load_got_offset (tempreg
, &offset_expr
);
4964 offset_expr
.X_add_number
= expr1
.X_add_number
;
4965 /* If we are going to add in a base register, and the
4966 target register and the base register are the same,
4967 then we are using AT as a temporary register. Since
4968 we want to load the constant into AT, we add our
4969 current AT (from the global offset table) and the
4970 register into the register now, and pretend we were
4971 not using a base register. */
4975 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
4980 add_got_offset_hilo (tempreg
, &offset_expr
, AT
);
4984 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
&& HAVE_NEWABI
)
4986 int add_breg_early
= 0;
4988 /* If this is a reference to an external, and there is no
4989 constant, or local symbol (*), with or without a
4991 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
4992 or for lca or if tempreg is PIC_CALL_REG
4993 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
4995 If we have a small constant, and this is a reference to
4996 an external symbol, we want
4997 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
4998 addiu $tempreg,$tempreg,<constant>
5000 If we have a large constant, and this is a reference to
5001 an external symbol, we want
5002 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
5003 lui $at,<hiconstant>
5004 addiu $at,$at,<loconstant>
5005 addu $tempreg,$tempreg,$at
5007 (*) Other assemblers seem to prefer GOT_PAGE/GOT_OFST for
5008 local symbols, even though it introduces an additional
5011 if (offset_expr
.X_add_number
)
5013 expr1
.X_add_number
= offset_expr
.X_add_number
;
5014 offset_expr
.X_add_number
= 0;
5016 relax_start (offset_expr
.X_add_symbol
);
5017 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
5018 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
5020 if (expr1
.X_add_number
>= -0x8000
5021 && expr1
.X_add_number
< 0x8000)
5023 macro_build (&expr1
, ADDRESS_ADDI_INSN
, "t,r,j",
5024 tempreg
, tempreg
, BFD_RELOC_LO16
);
5026 else if (IS_SEXT_32BIT_NUM (expr1
.X_add_number
+ 0x8000))
5030 /* If we are going to add in a base register, and the
5031 target register and the base register are the same,
5032 then we are using AT as a temporary register. Since
5033 we want to load the constant into AT, we add our
5034 current AT (from the global offset table) and the
5035 register into the register now, and pretend we were
5036 not using a base register. */
5041 assert (tempreg
== AT
);
5042 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5048 load_register (AT
, &expr1
, HAVE_64BIT_ADDRESSES
);
5049 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5055 as_bad (_("PIC code offset overflow (max 32 signed bits)"));
5058 offset_expr
.X_add_number
= expr1
.X_add_number
;
5060 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
5061 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
5064 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5065 treg
, tempreg
, breg
);
5071 else if (breg
== 0 && (call
|| tempreg
== PIC_CALL_REG
))
5073 relax_start (offset_expr
.X_add_symbol
);
5074 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
5075 BFD_RELOC_MIPS_CALL16
, mips_gp_register
);
5077 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
5078 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
5083 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
5084 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
5087 else if (mips_pic
== SVR4_PIC
&& ! HAVE_NEWABI
)
5090 int lui_reloc_type
= (int) BFD_RELOC_MIPS_GOT_HI16
;
5091 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT_LO16
;
5092 int local_reloc_type
= (int) BFD_RELOC_MIPS_GOT16
;
5094 /* This is the large GOT case. If this is a reference to an
5095 external symbol, and there is no constant, we want
5096 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5097 addu $tempreg,$tempreg,$gp
5098 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5099 or for lca or if tempreg is PIC_CALL_REG
5100 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
5101 addu $tempreg,$tempreg,$gp
5102 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
5103 For a local symbol, we want
5104 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5106 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
5108 If we have a small constant, and this is a reference to
5109 an external symbol, we want
5110 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5111 addu $tempreg,$tempreg,$gp
5112 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5114 addiu $tempreg,$tempreg,<constant>
5115 For a local symbol, we want
5116 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5118 addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16)
5120 If we have a large constant, and this is a reference to
5121 an external symbol, we want
5122 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5123 addu $tempreg,$tempreg,$gp
5124 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5125 lui $at,<hiconstant>
5126 addiu $at,$at,<loconstant>
5127 addu $tempreg,$tempreg,$at
5128 For a local symbol, we want
5129 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5130 lui $at,<hiconstant>
5131 addiu $at,$at,<loconstant> (BFD_RELOC_LO16)
5132 addu $tempreg,$tempreg,$at
5135 expr1
.X_add_number
= offset_expr
.X_add_number
;
5136 offset_expr
.X_add_number
= 0;
5137 relax_start (offset_expr
.X_add_symbol
);
5138 gpdelay
= reg_needs_delay (mips_gp_register
);
5139 if (expr1
.X_add_number
== 0 && breg
== 0
5140 && (call
|| tempreg
== PIC_CALL_REG
))
5142 lui_reloc_type
= (int) BFD_RELOC_MIPS_CALL_HI16
;
5143 lw_reloc_type
= (int) BFD_RELOC_MIPS_CALL_LO16
;
5145 macro_build (&offset_expr
, "lui", "t,u", tempreg
, lui_reloc_type
);
5146 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5147 tempreg
, tempreg
, mips_gp_register
);
5148 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
5149 tempreg
, lw_reloc_type
, tempreg
);
5150 if (expr1
.X_add_number
== 0)
5154 /* We're going to put in an addu instruction using
5155 tempreg, so we may as well insert the nop right
5160 else if (expr1
.X_add_number
>= -0x8000
5161 && expr1
.X_add_number
< 0x8000)
5164 macro_build (&expr1
, ADDRESS_ADDI_INSN
, "t,r,j",
5165 tempreg
, tempreg
, BFD_RELOC_LO16
);
5171 /* If we are going to add in a base register, and the
5172 target register and the base register are the same,
5173 then we are using AT as a temporary register. Since
5174 we want to load the constant into AT, we add our
5175 current AT (from the global offset table) and the
5176 register into the register now, and pretend we were
5177 not using a base register. */
5182 assert (tempreg
== AT
);
5184 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5189 load_register (AT
, &expr1
, HAVE_64BIT_ADDRESSES
);
5190 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", dreg
, dreg
, AT
);
5194 offset_expr
.X_add_number
=
5195 ((expr1
.X_add_number
+ 0x8000) & 0xffff) - 0x8000;
5200 /* This is needed because this instruction uses $gp, but
5201 the first instruction on the main stream does not. */
5202 macro_build (NULL
, "nop", "");
5205 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
5206 local_reloc_type
, mips_gp_register
);
5207 if (expr1
.X_add_number
>= -0x8000
5208 && expr1
.X_add_number
< 0x8000)
5211 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
5212 tempreg
, tempreg
, BFD_RELOC_LO16
);
5213 /* FIXME: If add_number is 0, and there was no base
5214 register, the external symbol case ended with a load,
5215 so if the symbol turns out to not be external, and
5216 the next instruction uses tempreg, an unnecessary nop
5217 will be inserted. */
5223 /* We must add in the base register now, as in the
5224 external symbol case. */
5225 assert (tempreg
== AT
);
5227 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5230 /* We set breg to 0 because we have arranged to add
5231 it in in both cases. */
5235 macro_build_lui (&expr1
, AT
);
5236 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
5237 AT
, AT
, BFD_RELOC_LO16
);
5238 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5239 tempreg
, tempreg
, AT
);
5244 else if (mips_pic
== SVR4_PIC
&& HAVE_NEWABI
)
5246 int lui_reloc_type
= (int) BFD_RELOC_MIPS_GOT_HI16
;
5247 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT_LO16
;
5248 int add_breg_early
= 0;
5250 /* This is the large GOT case. If this is a reference to an
5251 external symbol, and there is no constant, we want
5252 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5253 add $tempreg,$tempreg,$gp
5254 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5255 or for lca or if tempreg is PIC_CALL_REG
5256 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
5257 add $tempreg,$tempreg,$gp
5258 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
5260 If we have a small constant, and this is a reference to
5261 an external symbol, we want
5262 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5263 add $tempreg,$tempreg,$gp
5264 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5265 addi $tempreg,$tempreg,<constant>
5267 If we have a large constant, and this is a reference to
5268 an external symbol, we want
5269 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5270 addu $tempreg,$tempreg,$gp
5271 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5272 lui $at,<hiconstant>
5273 addi $at,$at,<loconstant>
5274 add $tempreg,$tempreg,$at
5276 If we have NewABI, and we know it's a local symbol, we want
5277 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
5278 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
5279 otherwise we have to resort to GOT_HI16/GOT_LO16. */
5281 relax_start (offset_expr
.X_add_symbol
);
5283 expr1
.X_add_number
= offset_expr
.X_add_number
;
5284 offset_expr
.X_add_number
= 0;
5286 if (expr1
.X_add_number
== 0 && breg
== 0
5287 && (call
|| tempreg
== PIC_CALL_REG
))
5289 lui_reloc_type
= (int) BFD_RELOC_MIPS_CALL_HI16
;
5290 lw_reloc_type
= (int) BFD_RELOC_MIPS_CALL_LO16
;
5292 macro_build (&offset_expr
, "lui", "t,u", tempreg
, lui_reloc_type
);
5293 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5294 tempreg
, tempreg
, mips_gp_register
);
5295 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
5296 tempreg
, lw_reloc_type
, tempreg
);
5298 if (expr1
.X_add_number
== 0)
5300 else if (expr1
.X_add_number
>= -0x8000
5301 && expr1
.X_add_number
< 0x8000)
5303 macro_build (&expr1
, ADDRESS_ADDI_INSN
, "t,r,j",
5304 tempreg
, tempreg
, BFD_RELOC_LO16
);
5306 else if (IS_SEXT_32BIT_NUM (expr1
.X_add_number
+ 0x8000))
5310 /* If we are going to add in a base register, and the
5311 target register and the base register are the same,
5312 then we are using AT as a temporary register. Since
5313 we want to load the constant into AT, we add our
5314 current AT (from the global offset table) and the
5315 register into the register now, and pretend we were
5316 not using a base register. */
5321 assert (tempreg
== AT
);
5322 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5328 load_register (AT
, &expr1
, HAVE_64BIT_ADDRESSES
);
5329 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", dreg
, dreg
, AT
);
5334 as_bad (_("PIC code offset overflow (max 32 signed bits)"));
5337 offset_expr
.X_add_number
= expr1
.X_add_number
;
5338 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
5339 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
5340 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j", tempreg
,
5341 tempreg
, BFD_RELOC_MIPS_GOT_OFST
);
5344 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5345 treg
, tempreg
, breg
);
5355 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", treg
, tempreg
, breg
);
5359 /* The j instruction may not be used in PIC code, since it
5360 requires an absolute address. We convert it to a b
5362 if (mips_pic
== NO_PIC
)
5363 macro_build (&offset_expr
, "j", "a");
5365 macro_build (&offset_expr
, "b", "p");
5368 /* The jal instructions must be handled as macros because when
5369 generating PIC code they expand to multi-instruction
5370 sequences. Normally they are simple instructions. */
5375 if (mips_pic
== NO_PIC
)
5376 macro_build (NULL
, "jalr", "d,s", dreg
, sreg
);
5377 else if (mips_pic
== SVR4_PIC
)
5379 if (sreg
!= PIC_CALL_REG
)
5380 as_warn (_("MIPS PIC call to register other than $25"));
5382 macro_build (NULL
, "jalr", "d,s", dreg
, sreg
);
5385 if (mips_cprestore_offset
< 0)
5386 as_warn (_("No .cprestore pseudo-op used in PIC code"));
5389 if (! mips_frame_reg_valid
)
5391 as_warn (_("No .frame pseudo-op used in PIC code"));
5392 /* Quiet this warning. */
5393 mips_frame_reg_valid
= 1;
5395 if (! mips_cprestore_valid
)
5397 as_warn (_("No .cprestore pseudo-op used in PIC code"));
5398 /* Quiet this warning. */
5399 mips_cprestore_valid
= 1;
5401 expr1
.X_add_number
= mips_cprestore_offset
;
5402 macro_build_ldst_constoffset (&expr1
, ADDRESS_LOAD_INSN
,
5405 HAVE_64BIT_ADDRESSES
);
5415 if (mips_pic
== NO_PIC
)
5416 macro_build (&offset_expr
, "jal", "a");
5417 else if (mips_pic
== SVR4_PIC
)
5419 /* If this is a reference to an external symbol, and we are
5420 using a small GOT, we want
5421 lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
5425 lw $gp,cprestore($sp)
5426 The cprestore value is set using the .cprestore
5427 pseudo-op. If we are using a big GOT, we want
5428 lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16)
5430 lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16)
5434 lw $gp,cprestore($sp)
5435 If the symbol is not external, we want
5436 lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5438 addiu $25,$25,<sym> (BFD_RELOC_LO16)
5441 lw $gp,cprestore($sp)
5443 For NewABI, we use the same CALL16 or CALL_HI16/CALL_LO16
5444 sequences above, minus nops, unless the symbol is local,
5445 which enables us to use GOT_PAGE/GOT_OFST (big got) or
5451 relax_start (offset_expr
.X_add_symbol
);
5452 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
5453 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL16
,
5456 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
5457 PIC_CALL_REG
, BFD_RELOC_MIPS_GOT_DISP
,
5463 relax_start (offset_expr
.X_add_symbol
);
5464 macro_build (&offset_expr
, "lui", "t,u", PIC_CALL_REG
,
5465 BFD_RELOC_MIPS_CALL_HI16
);
5466 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", PIC_CALL_REG
,
5467 PIC_CALL_REG
, mips_gp_register
);
5468 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
5469 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL_LO16
,
5472 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
5473 PIC_CALL_REG
, BFD_RELOC_MIPS_GOT_PAGE
,
5475 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
5476 PIC_CALL_REG
, PIC_CALL_REG
,
5477 BFD_RELOC_MIPS_GOT_OFST
);
5481 macro_build_jalr (&offset_expr
);
5485 relax_start (offset_expr
.X_add_symbol
);
5488 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
5489 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL16
,
5498 gpdelay
= reg_needs_delay (mips_gp_register
);
5499 macro_build (&offset_expr
, "lui", "t,u", PIC_CALL_REG
,
5500 BFD_RELOC_MIPS_CALL_HI16
);
5501 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", PIC_CALL_REG
,
5502 PIC_CALL_REG
, mips_gp_register
);
5503 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
5504 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL_LO16
,
5509 macro_build (NULL
, "nop", "");
5511 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
5512 PIC_CALL_REG
, BFD_RELOC_MIPS_GOT16
,
5515 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
5516 PIC_CALL_REG
, PIC_CALL_REG
, BFD_RELOC_LO16
);
5518 macro_build_jalr (&offset_expr
);
5520 if (mips_cprestore_offset
< 0)
5521 as_warn (_("No .cprestore pseudo-op used in PIC code"));
5524 if (! mips_frame_reg_valid
)
5526 as_warn (_("No .frame pseudo-op used in PIC code"));
5527 /* Quiet this warning. */
5528 mips_frame_reg_valid
= 1;
5530 if (! mips_cprestore_valid
)
5532 as_warn (_("No .cprestore pseudo-op used in PIC code"));
5533 /* Quiet this warning. */
5534 mips_cprestore_valid
= 1;
5536 if (mips_opts
.noreorder
)
5537 macro_build (NULL
, "nop", "");
5538 expr1
.X_add_number
= mips_cprestore_offset
;
5539 macro_build_ldst_constoffset (&expr1
, ADDRESS_LOAD_INSN
,
5542 HAVE_64BIT_ADDRESSES
);
5568 /* Itbl support may require additional care here. */
5573 /* Itbl support may require additional care here. */
5578 /* Itbl support may require additional care here. */
5583 /* Itbl support may require additional care here. */
5595 if (mips_opts
.arch
== CPU_R4650
)
5597 as_bad (_("opcode not supported on this processor"));
5601 /* Itbl support may require additional care here. */
5606 /* Itbl support may require additional care here. */
5611 /* Itbl support may require additional care here. */
5631 if (breg
== treg
|| coproc
|| lr
)
5652 /* Itbl support may require additional care here. */
5657 /* Itbl support may require additional care here. */
5662 /* Itbl support may require additional care here. */
5667 /* Itbl support may require additional care here. */
5683 if (mips_opts
.arch
== CPU_R4650
)
5685 as_bad (_("opcode not supported on this processor"));
5690 /* Itbl support may require additional care here. */
5694 /* Itbl support may require additional care here. */
5699 /* Itbl support may require additional care here. */
5711 /* Itbl support may require additional care here. */
5712 if (mask
== M_LWC1_AB
5713 || mask
== M_SWC1_AB
5714 || mask
== M_LDC1_AB
5715 || mask
== M_SDC1_AB
5724 if (offset_expr
.X_op
!= O_constant
5725 && offset_expr
.X_op
!= O_symbol
)
5727 as_bad (_("expression too complex"));
5728 offset_expr
.X_op
= O_constant
;
5731 /* A constant expression in PIC code can be handled just as it
5732 is in non PIC code. */
5733 if (offset_expr
.X_op
== O_constant
)
5735 if (HAVE_32BIT_ADDRESSES
5736 && !IS_SEXT_32BIT_NUM (offset_expr
.X_add_number
))
5737 as_bad (_("constant too large"));
5739 expr1
.X_add_number
= ((offset_expr
.X_add_number
+ 0x8000)
5740 & ~(bfd_vma
) 0xffff);
5741 load_register (tempreg
, &expr1
, HAVE_64BIT_ADDRESSES
);
5743 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5744 tempreg
, tempreg
, breg
);
5745 macro_build (&offset_expr
, s
, fmt
, treg
, BFD_RELOC_LO16
, tempreg
);
5747 else if (mips_pic
== NO_PIC
)
5749 /* If this is a reference to a GP relative symbol, and there
5750 is no base register, we want
5751 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
5752 Otherwise, if there is no base register, we want
5753 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
5754 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5755 If we have a constant, we need two instructions anyhow,
5756 so we always use the latter form.
5758 If we have a base register, and this is a reference to a
5759 GP relative symbol, we want
5760 addu $tempreg,$breg,$gp
5761 <op> $treg,<sym>($tempreg) (BFD_RELOC_GPREL16)
5763 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
5764 addu $tempreg,$tempreg,$breg
5765 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5766 With a constant we always use the latter case.
5768 With 64bit address space and no base register and $at usable,
5770 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5771 lui $at,<sym> (BFD_RELOC_HI16_S)
5772 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
5775 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5776 If we have a base register, we want
5777 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5778 lui $at,<sym> (BFD_RELOC_HI16_S)
5779 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
5783 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5785 Without $at we can't generate the optimal path for superscalar
5786 processors here since this would require two temporary registers.
5787 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5788 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
5790 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
5792 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5793 If we have a base register, we want
5794 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5795 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
5797 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
5799 daddu $tempreg,$tempreg,$breg
5800 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5802 For GP relative symbols in 64bit address space we can use
5803 the same sequence as in 32bit address space. */
5804 if (HAVE_64BIT_SYMBOLS
)
5806 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
5807 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
5809 relax_start (offset_expr
.X_add_symbol
);
5812 macro_build (&offset_expr
, s
, fmt
, treg
,
5813 BFD_RELOC_GPREL16
, mips_gp_register
);
5817 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5818 tempreg
, breg
, mips_gp_register
);
5819 macro_build (&offset_expr
, s
, fmt
, treg
,
5820 BFD_RELOC_GPREL16
, tempreg
);
5825 if (used_at
== 0 && !mips_opts
.noat
)
5827 macro_build (&offset_expr
, "lui", "t,u", tempreg
,
5828 BFD_RELOC_MIPS_HIGHEST
);
5829 macro_build (&offset_expr
, "lui", "t,u", AT
,
5831 macro_build (&offset_expr
, "daddiu", "t,r,j", tempreg
,
5832 tempreg
, BFD_RELOC_MIPS_HIGHER
);
5834 macro_build (NULL
, "daddu", "d,v,t", AT
, AT
, breg
);
5835 macro_build (NULL
, "dsll32", "d,w,<", tempreg
, tempreg
, 0);
5836 macro_build (NULL
, "daddu", "d,v,t", tempreg
, tempreg
, AT
);
5837 macro_build (&offset_expr
, s
, fmt
, treg
, BFD_RELOC_LO16
,
5843 macro_build (&offset_expr
, "lui", "t,u", tempreg
,
5844 BFD_RELOC_MIPS_HIGHEST
);
5845 macro_build (&offset_expr
, "daddiu", "t,r,j", tempreg
,
5846 tempreg
, BFD_RELOC_MIPS_HIGHER
);
5847 macro_build (NULL
, "dsll", "d,w,<", tempreg
, tempreg
, 16);
5848 macro_build (&offset_expr
, "daddiu", "t,r,j", tempreg
,
5849 tempreg
, BFD_RELOC_HI16_S
);
5850 macro_build (NULL
, "dsll", "d,w,<", tempreg
, tempreg
, 16);
5852 macro_build (NULL
, "daddu", "d,v,t",
5853 tempreg
, tempreg
, breg
);
5854 macro_build (&offset_expr
, s
, fmt
, treg
,
5855 BFD_RELOC_LO16
, tempreg
);
5858 if (mips_relax
.sequence
)
5865 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
5866 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
5868 relax_start (offset_expr
.X_add_symbol
);
5869 macro_build (&offset_expr
, s
, fmt
, treg
, BFD_RELOC_GPREL16
,
5873 macro_build_lui (&offset_expr
, tempreg
);
5874 macro_build (&offset_expr
, s
, fmt
, treg
,
5875 BFD_RELOC_LO16
, tempreg
);
5876 if (mips_relax
.sequence
)
5881 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
5882 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
5884 relax_start (offset_expr
.X_add_symbol
);
5885 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5886 tempreg
, breg
, mips_gp_register
);
5887 macro_build (&offset_expr
, s
, fmt
, treg
,
5888 BFD_RELOC_GPREL16
, tempreg
);
5891 macro_build_lui (&offset_expr
, tempreg
);
5892 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5893 tempreg
, tempreg
, breg
);
5894 macro_build (&offset_expr
, s
, fmt
, treg
,
5895 BFD_RELOC_LO16
, tempreg
);
5896 if (mips_relax
.sequence
)
5900 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
5902 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT16
;
5904 /* If this is a reference to an external symbol, we want
5905 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5907 <op> $treg,0($tempreg)
5909 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5911 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
5912 <op> $treg,0($tempreg)
5915 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
5916 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST)
5918 If there is a base register, we add it to $tempreg before
5919 the <op>. If there is a constant, we stick it in the
5920 <op> instruction. We don't handle constants larger than
5921 16 bits, because we have no way to load the upper 16 bits
5922 (actually, we could handle them for the subset of cases
5923 in which we are not using $at). */
5924 assert (offset_expr
.X_op
== O_symbol
);
5927 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
5928 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
5930 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5931 tempreg
, tempreg
, breg
);
5932 macro_build (&offset_expr
, s
, fmt
, treg
,
5933 BFD_RELOC_MIPS_GOT_OFST
, tempreg
);
5936 expr1
.X_add_number
= offset_expr
.X_add_number
;
5937 offset_expr
.X_add_number
= 0;
5938 if (expr1
.X_add_number
< -0x8000
5939 || expr1
.X_add_number
>= 0x8000)
5940 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
5941 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
5942 lw_reloc_type
, mips_gp_register
);
5944 relax_start (offset_expr
.X_add_symbol
);
5946 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j", tempreg
,
5947 tempreg
, BFD_RELOC_LO16
);
5950 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5951 tempreg
, tempreg
, breg
);
5952 macro_build (&expr1
, s
, fmt
, treg
, BFD_RELOC_LO16
, tempreg
);
5954 else if (mips_pic
== SVR4_PIC
&& ! HAVE_NEWABI
)
5958 /* If this is a reference to an external symbol, we want
5959 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5960 addu $tempreg,$tempreg,$gp
5961 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5962 <op> $treg,0($tempreg)
5964 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5966 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
5967 <op> $treg,0($tempreg)
5968 If there is a base register, we add it to $tempreg before
5969 the <op>. If there is a constant, we stick it in the
5970 <op> instruction. We don't handle constants larger than
5971 16 bits, because we have no way to load the upper 16 bits
5972 (actually, we could handle them for the subset of cases
5973 in which we are not using $at). */
5974 assert (offset_expr
.X_op
== O_symbol
);
5975 expr1
.X_add_number
= offset_expr
.X_add_number
;
5976 offset_expr
.X_add_number
= 0;
5977 if (expr1
.X_add_number
< -0x8000
5978 || expr1
.X_add_number
>= 0x8000)
5979 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
5980 gpdelay
= reg_needs_delay (mips_gp_register
);
5981 relax_start (offset_expr
.X_add_symbol
);
5982 macro_build (&offset_expr
, "lui", "t,u", tempreg
,
5983 BFD_RELOC_MIPS_GOT_HI16
);
5984 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", tempreg
, tempreg
,
5986 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
5987 BFD_RELOC_MIPS_GOT_LO16
, tempreg
);
5990 macro_build (NULL
, "nop", "");
5991 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
5992 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
5994 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j", tempreg
,
5995 tempreg
, BFD_RELOC_LO16
);
5999 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6000 tempreg
, tempreg
, breg
);
6001 macro_build (&expr1
, s
, fmt
, treg
, BFD_RELOC_LO16
, tempreg
);
6003 else if (mips_pic
== SVR4_PIC
&& HAVE_NEWABI
)
6005 /* If this is a reference to an external symbol, we want
6006 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
6007 add $tempreg,$tempreg,$gp
6008 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
6009 <op> $treg,<ofst>($tempreg)
6010 Otherwise, for local symbols, we want:
6011 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
6012 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST) */
6013 assert (offset_expr
.X_op
== O_symbol
);
6014 expr1
.X_add_number
= offset_expr
.X_add_number
;
6015 offset_expr
.X_add_number
= 0;
6016 if (expr1
.X_add_number
< -0x8000
6017 || expr1
.X_add_number
>= 0x8000)
6018 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6019 relax_start (offset_expr
.X_add_symbol
);
6020 macro_build (&offset_expr
, "lui", "t,u", tempreg
,
6021 BFD_RELOC_MIPS_GOT_HI16
);
6022 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", tempreg
, tempreg
,
6024 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
6025 BFD_RELOC_MIPS_GOT_LO16
, tempreg
);
6027 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6028 tempreg
, tempreg
, breg
);
6029 macro_build (&expr1
, s
, fmt
, treg
, BFD_RELOC_LO16
, tempreg
);
6032 offset_expr
.X_add_number
= expr1
.X_add_number
;
6033 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
6034 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
6036 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6037 tempreg
, tempreg
, breg
);
6038 macro_build (&offset_expr
, s
, fmt
, treg
,
6039 BFD_RELOC_MIPS_GOT_OFST
, tempreg
);
6049 load_register (treg
, &imm_expr
, 0);
6053 load_register (treg
, &imm_expr
, 1);
6057 if (imm_expr
.X_op
== O_constant
)
6060 load_register (AT
, &imm_expr
, 0);
6061 macro_build (NULL
, "mtc1", "t,G", AT
, treg
);
6066 assert (offset_expr
.X_op
== O_symbol
6067 && strcmp (segment_name (S_GET_SEGMENT
6068 (offset_expr
.X_add_symbol
)),
6070 && offset_expr
.X_add_number
== 0);
6071 macro_build (&offset_expr
, "lwc1", "T,o(b)", treg
,
6072 BFD_RELOC_MIPS_LITERAL
, mips_gp_register
);
6077 /* Check if we have a constant in IMM_EXPR. If the GPRs are 64 bits
6078 wide, IMM_EXPR is the entire value. Otherwise IMM_EXPR is the high
6079 order 32 bits of the value and the low order 32 bits are either
6080 zero or in OFFSET_EXPR. */
6081 if (imm_expr
.X_op
== O_constant
|| imm_expr
.X_op
== O_big
)
6083 if (HAVE_64BIT_GPRS
)
6084 load_register (treg
, &imm_expr
, 1);
6089 if (target_big_endian
)
6101 load_register (hreg
, &imm_expr
, 0);
6104 if (offset_expr
.X_op
== O_absent
)
6105 move_register (lreg
, 0);
6108 assert (offset_expr
.X_op
== O_constant
);
6109 load_register (lreg
, &offset_expr
, 0);
6116 /* We know that sym is in the .rdata section. First we get the
6117 upper 16 bits of the address. */
6118 if (mips_pic
== NO_PIC
)
6120 macro_build_lui (&offset_expr
, AT
);
6123 else if (mips_pic
== SVR4_PIC
)
6125 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", AT
,
6126 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
6132 /* Now we load the register(s). */
6133 if (HAVE_64BIT_GPRS
)
6136 macro_build (&offset_expr
, "ld", "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
6141 macro_build (&offset_expr
, "lw", "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
6144 /* FIXME: How in the world do we deal with the possible
6146 offset_expr
.X_add_number
+= 4;
6147 macro_build (&offset_expr
, "lw", "t,o(b)",
6148 treg
+ 1, BFD_RELOC_LO16
, AT
);
6154 /* Check if we have a constant in IMM_EXPR. If the FPRs are 64 bits
6155 wide, IMM_EXPR is the entire value and the GPRs are known to be 64
6156 bits wide as well. Otherwise IMM_EXPR is the high order 32 bits of
6157 the value and the low order 32 bits are either zero or in
6159 if (imm_expr
.X_op
== O_constant
|| imm_expr
.X_op
== O_big
)
6162 load_register (AT
, &imm_expr
, HAVE_64BIT_FPRS
);
6163 if (HAVE_64BIT_FPRS
)
6165 assert (HAVE_64BIT_GPRS
);
6166 macro_build (NULL
, "dmtc1", "t,S", AT
, treg
);
6170 macro_build (NULL
, "mtc1", "t,G", AT
, treg
+ 1);
6171 if (offset_expr
.X_op
== O_absent
)
6172 macro_build (NULL
, "mtc1", "t,G", 0, treg
);
6175 assert (offset_expr
.X_op
== O_constant
);
6176 load_register (AT
, &offset_expr
, 0);
6177 macro_build (NULL
, "mtc1", "t,G", AT
, treg
);
6183 assert (offset_expr
.X_op
== O_symbol
6184 && offset_expr
.X_add_number
== 0);
6185 s
= segment_name (S_GET_SEGMENT (offset_expr
.X_add_symbol
));
6186 if (strcmp (s
, ".lit8") == 0)
6188 if (mips_opts
.isa
!= ISA_MIPS1
)
6190 macro_build (&offset_expr
, "ldc1", "T,o(b)", treg
,
6191 BFD_RELOC_MIPS_LITERAL
, mips_gp_register
);
6194 breg
= mips_gp_register
;
6195 r
= BFD_RELOC_MIPS_LITERAL
;
6200 assert (strcmp (s
, RDATA_SECTION_NAME
) == 0);
6202 if (mips_pic
== SVR4_PIC
)
6203 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", AT
,
6204 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
6207 /* FIXME: This won't work for a 64 bit address. */
6208 macro_build_lui (&offset_expr
, AT
);
6211 if (mips_opts
.isa
!= ISA_MIPS1
)
6213 macro_build (&offset_expr
, "ldc1", "T,o(b)",
6214 treg
, BFD_RELOC_LO16
, AT
);
6223 if (mips_opts
.arch
== CPU_R4650
)
6225 as_bad (_("opcode not supported on this processor"));
6228 /* Even on a big endian machine $fn comes before $fn+1. We have
6229 to adjust when loading from memory. */
6232 assert (mips_opts
.isa
== ISA_MIPS1
);
6233 macro_build (&offset_expr
, "lwc1", "T,o(b)",
6234 target_big_endian
? treg
+ 1 : treg
, r
, breg
);
6235 /* FIXME: A possible overflow which I don't know how to deal
6237 offset_expr
.X_add_number
+= 4;
6238 macro_build (&offset_expr
, "lwc1", "T,o(b)",
6239 target_big_endian
? treg
: treg
+ 1, r
, breg
);
6244 * The MIPS assembler seems to check for X_add_number not
6245 * being double aligned and generating:
6248 * addiu at,at,%lo(foo+1)
6251 * But, the resulting address is the same after relocation so why
6252 * generate the extra instruction?
6254 if (mips_opts
.arch
== CPU_R4650
)
6256 as_bad (_("opcode not supported on this processor"));
6259 /* Itbl support may require additional care here. */
6261 if (mips_opts
.isa
!= ISA_MIPS1
)
6272 if (mips_opts
.arch
== CPU_R4650
)
6274 as_bad (_("opcode not supported on this processor"));
6278 if (mips_opts
.isa
!= ISA_MIPS1
)
6286 /* Itbl support may require additional care here. */
6291 if (HAVE_64BIT_GPRS
)
6302 if (HAVE_64BIT_GPRS
)
6312 if (offset_expr
.X_op
!= O_symbol
6313 && offset_expr
.X_op
!= O_constant
)
6315 as_bad (_("expression too complex"));
6316 offset_expr
.X_op
= O_constant
;
6319 /* Even on a big endian machine $fn comes before $fn+1. We have
6320 to adjust when loading from memory. We set coproc if we must
6321 load $fn+1 first. */
6322 /* Itbl support may require additional care here. */
6323 if (! target_big_endian
)
6326 if (mips_pic
== NO_PIC
6327 || offset_expr
.X_op
== O_constant
)
6329 /* If this is a reference to a GP relative symbol, we want
6330 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
6331 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_GPREL16)
6332 If we have a base register, we use this
6334 <op> $treg,<sym>($at) (BFD_RELOC_GPREL16)
6335 <op> $treg+1,<sym>+4($at) (BFD_RELOC_GPREL16)
6336 If this is not a GP relative symbol, we want
6337 lui $at,<sym> (BFD_RELOC_HI16_S)
6338 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
6339 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
6340 If there is a base register, we add it to $at after the
6341 lui instruction. If there is a constant, we always use
6343 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
6344 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
6346 relax_start (offset_expr
.X_add_symbol
);
6349 tempreg
= mips_gp_register
;
6353 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6354 AT
, breg
, mips_gp_register
);
6359 /* Itbl support may require additional care here. */
6360 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
+ 1 : treg
,
6361 BFD_RELOC_GPREL16
, tempreg
);
6362 offset_expr
.X_add_number
+= 4;
6364 /* Set mips_optimize to 2 to avoid inserting an
6366 hold_mips_optimize
= mips_optimize
;
6368 /* Itbl support may require additional care here. */
6369 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
: treg
+ 1,
6370 BFD_RELOC_GPREL16
, tempreg
);
6371 mips_optimize
= hold_mips_optimize
;
6375 /* We just generated two relocs. When tc_gen_reloc
6376 handles this case, it will skip the first reloc and
6377 handle the second. The second reloc already has an
6378 extra addend of 4, which we added above. We must
6379 subtract it out, and then subtract another 4 to make
6380 the first reloc come out right. The second reloc
6381 will come out right because we are going to add 4 to
6382 offset_expr when we build its instruction below.
6384 If we have a symbol, then we don't want to include
6385 the offset, because it will wind up being included
6386 when we generate the reloc. */
6388 if (offset_expr
.X_op
== O_constant
)
6389 offset_expr
.X_add_number
-= 8;
6392 offset_expr
.X_add_number
= -4;
6393 offset_expr
.X_op
= O_constant
;
6397 macro_build_lui (&offset_expr
, AT
);
6399 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
6400 /* Itbl support may require additional care here. */
6401 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
+ 1 : treg
,
6402 BFD_RELOC_LO16
, AT
);
6403 /* FIXME: How do we handle overflow here? */
6404 offset_expr
.X_add_number
+= 4;
6405 /* Itbl support may require additional care here. */
6406 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
: treg
+ 1,
6407 BFD_RELOC_LO16
, AT
);
6408 if (mips_relax
.sequence
)
6411 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
6413 /* If this is a reference to an external symbol, we want
6414 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6419 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6421 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
6422 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
6423 If there is a base register we add it to $at before the
6424 lwc1 instructions. If there is a constant we include it
6425 in the lwc1 instructions. */
6427 expr1
.X_add_number
= offset_expr
.X_add_number
;
6428 if (expr1
.X_add_number
< -0x8000
6429 || expr1
.X_add_number
>= 0x8000 - 4)
6430 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6431 load_got_offset (AT
, &offset_expr
);
6434 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
6436 /* Set mips_optimize to 2 to avoid inserting an undesired
6438 hold_mips_optimize
= mips_optimize
;
6441 /* Itbl support may require additional care here. */
6442 relax_start (offset_expr
.X_add_symbol
);
6443 macro_build (&expr1
, s
, fmt
, coproc
? treg
+ 1 : treg
,
6444 BFD_RELOC_LO16
, AT
);
6445 expr1
.X_add_number
+= 4;
6446 macro_build (&expr1
, s
, fmt
, coproc
? treg
: treg
+ 1,
6447 BFD_RELOC_LO16
, AT
);
6449 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
+ 1 : treg
,
6450 BFD_RELOC_LO16
, AT
);
6451 offset_expr
.X_add_number
+= 4;
6452 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
: treg
+ 1,
6453 BFD_RELOC_LO16
, AT
);
6456 mips_optimize
= hold_mips_optimize
;
6458 else if (mips_pic
== SVR4_PIC
)
6462 /* If this is a reference to an external symbol, we want
6463 lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16)
6465 lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16)
6470 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6472 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
6473 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
6474 If there is a base register we add it to $at before the
6475 lwc1 instructions. If there is a constant we include it
6476 in the lwc1 instructions. */
6478 expr1
.X_add_number
= offset_expr
.X_add_number
;
6479 offset_expr
.X_add_number
= 0;
6480 if (expr1
.X_add_number
< -0x8000
6481 || expr1
.X_add_number
>= 0x8000 - 4)
6482 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6483 gpdelay
= reg_needs_delay (mips_gp_register
);
6484 relax_start (offset_expr
.X_add_symbol
);
6485 macro_build (&offset_expr
, "lui", "t,u",
6486 AT
, BFD_RELOC_MIPS_GOT_HI16
);
6487 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6488 AT
, AT
, mips_gp_register
);
6489 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
6490 AT
, BFD_RELOC_MIPS_GOT_LO16
, AT
);
6493 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
6494 /* Itbl support may require additional care here. */
6495 macro_build (&expr1
, s
, fmt
, coproc
? treg
+ 1 : treg
,
6496 BFD_RELOC_LO16
, AT
);
6497 expr1
.X_add_number
+= 4;
6499 /* Set mips_optimize to 2 to avoid inserting an undesired
6501 hold_mips_optimize
= mips_optimize
;
6503 /* Itbl support may require additional care here. */
6504 macro_build (&expr1
, s
, fmt
, coproc
? treg
: treg
+ 1,
6505 BFD_RELOC_LO16
, AT
);
6506 mips_optimize
= hold_mips_optimize
;
6507 expr1
.X_add_number
-= 4;
6510 offset_expr
.X_add_number
= expr1
.X_add_number
;
6512 macro_build (NULL
, "nop", "");
6513 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", AT
,
6514 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
6517 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
6518 /* Itbl support may require additional care here. */
6519 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
+ 1 : treg
,
6520 BFD_RELOC_LO16
, AT
);
6521 offset_expr
.X_add_number
+= 4;
6523 /* Set mips_optimize to 2 to avoid inserting an undesired
6525 hold_mips_optimize
= mips_optimize
;
6527 /* Itbl support may require additional care here. */
6528 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
: treg
+ 1,
6529 BFD_RELOC_LO16
, AT
);
6530 mips_optimize
= hold_mips_optimize
;
6544 assert (HAVE_32BIT_ADDRESSES
);
6545 macro_build (&offset_expr
, s
, "t,o(b)", treg
, BFD_RELOC_LO16
, breg
);
6546 offset_expr
.X_add_number
+= 4;
6547 macro_build (&offset_expr
, s
, "t,o(b)", treg
+ 1, BFD_RELOC_LO16
, breg
);
6550 /* New code added to support COPZ instructions.
6551 This code builds table entries out of the macros in mip_opcodes.
6552 R4000 uses interlocks to handle coproc delays.
6553 Other chips (like the R3000) require nops to be inserted for delays.
6555 FIXME: Currently, we require that the user handle delays.
6556 In order to fill delay slots for non-interlocked chips,
6557 we must have a way to specify delays based on the coprocessor.
6558 Eg. 4 cycles if load coproc reg from memory, 1 if in cache, etc.
6559 What are the side-effects of the cop instruction?
6560 What cache support might we have and what are its effects?
6561 Both coprocessor & memory require delays. how long???
6562 What registers are read/set/modified?
6564 If an itbl is provided to interpret cop instructions,
6565 this knowledge can be encoded in the itbl spec. */
6579 /* For now we just do C (same as Cz). The parameter will be
6580 stored in insn_opcode by mips_ip. */
6581 macro_build (NULL
, s
, "C", ip
->insn_opcode
);
6585 move_register (dreg
, sreg
);
6588 #ifdef LOSING_COMPILER
6590 /* Try and see if this is a new itbl instruction.
6591 This code builds table entries out of the macros in mip_opcodes.
6592 FIXME: For now we just assemble the expression and pass it's
6593 value along as a 32-bit immediate.
6594 We may want to have the assembler assemble this value,
6595 so that we gain the assembler's knowledge of delay slots,
6597 Would it be more efficient to use mask (id) here? */
6598 if (itbl_have_entries
6599 && (immed_expr
= itbl_assemble (ip
->insn_mo
->name
, "")))
6601 s
= ip
->insn_mo
->name
;
6603 coproc
= ITBL_DECODE_PNUM (immed_expr
);;
6604 macro_build (&immed_expr
, s
, "C");
6610 if (mips_opts
.noat
&& used_at
)
6611 as_bad (_("Macro used $at after \".set noat\""));
6615 macro2 (struct mips_cl_insn
*ip
)
6617 register int treg
, sreg
, dreg
, breg
;
6632 bfd_reloc_code_real_type r
;
6634 treg
= (ip
->insn_opcode
>> 16) & 0x1f;
6635 dreg
= (ip
->insn_opcode
>> 11) & 0x1f;
6636 sreg
= breg
= (ip
->insn_opcode
>> 21) & 0x1f;
6637 mask
= ip
->insn_mo
->mask
;
6639 expr1
.X_op
= O_constant
;
6640 expr1
.X_op_symbol
= NULL
;
6641 expr1
.X_add_symbol
= NULL
;
6642 expr1
.X_add_number
= 1;
6646 #endif /* LOSING_COMPILER */
6651 macro_build (NULL
, dbl
? "dmultu" : "multu", "s,t", sreg
, treg
);
6652 macro_build (NULL
, "mflo", "d", dreg
);
6658 /* The MIPS assembler some times generates shifts and adds. I'm
6659 not trying to be that fancy. GCC should do this for us
6662 load_register (AT
, &imm_expr
, dbl
);
6663 macro_build (NULL
, dbl
? "dmult" : "mult", "s,t", sreg
, AT
);
6664 macro_build (NULL
, "mflo", "d", dreg
);
6677 mips_emit_delays (TRUE
);
6678 ++mips_opts
.noreorder
;
6679 mips_any_noreorder
= 1;
6682 load_register (AT
, &imm_expr
, dbl
);
6683 macro_build (NULL
, dbl
? "dmult" : "mult", "s,t", sreg
, imm
? AT
: treg
);
6684 macro_build (NULL
, "mflo", "d", dreg
);
6685 macro_build (NULL
, dbl
? "dsra32" : "sra", "d,w,<", dreg
, dreg
, RA
);
6686 macro_build (NULL
, "mfhi", "d", AT
);
6688 macro_build (NULL
, "tne", "s,t,q", dreg
, AT
, 6);
6691 expr1
.X_add_number
= 8;
6692 macro_build (&expr1
, "beq", "s,t,p", dreg
, AT
);
6693 macro_build (NULL
, "nop", "", 0);
6694 macro_build (NULL
, "break", "c", 6);
6696 --mips_opts
.noreorder
;
6697 macro_build (NULL
, "mflo", "d", dreg
);
6710 mips_emit_delays (TRUE
);
6711 ++mips_opts
.noreorder
;
6712 mips_any_noreorder
= 1;
6715 load_register (AT
, &imm_expr
, dbl
);
6716 macro_build (NULL
, dbl
? "dmultu" : "multu", "s,t",
6717 sreg
, imm
? AT
: treg
);
6718 macro_build (NULL
, "mfhi", "d", AT
);
6719 macro_build (NULL
, "mflo", "d", dreg
);
6721 macro_build (NULL
, "tne", "s,t,q", AT
, 0, 6);
6724 expr1
.X_add_number
= 8;
6725 macro_build (&expr1
, "beq", "s,t,p", AT
, 0);
6726 macro_build (NULL
, "nop", "", 0);
6727 macro_build (NULL
, "break", "c", 6);
6729 --mips_opts
.noreorder
;
6733 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
6744 macro_build (NULL
, "dnegu", "d,w", tempreg
, treg
);
6745 macro_build (NULL
, "drorv", "d,t,s", dreg
, sreg
, tempreg
);
6749 macro_build (NULL
, "dsubu", "d,v,t", AT
, 0, treg
);
6750 macro_build (NULL
, "dsrlv", "d,t,s", AT
, sreg
, AT
);
6751 macro_build (NULL
, "dsllv", "d,t,s", dreg
, sreg
, treg
);
6752 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
6756 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
6767 macro_build (NULL
, "negu", "d,w", tempreg
, treg
);
6768 macro_build (NULL
, "rorv", "d,t,s", dreg
, sreg
, tempreg
);
6772 macro_build (NULL
, "subu", "d,v,t", AT
, 0, treg
);
6773 macro_build (NULL
, "srlv", "d,t,s", AT
, sreg
, AT
);
6774 macro_build (NULL
, "sllv", "d,t,s", dreg
, sreg
, treg
);
6775 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
6783 if (imm_expr
.X_op
!= O_constant
)
6784 as_bad (_("Improper rotate count"));
6785 rot
= imm_expr
.X_add_number
& 0x3f;
6786 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
6788 rot
= (64 - rot
) & 0x3f;
6790 macro_build (NULL
, "dror32", "d,w,<", dreg
, sreg
, rot
- 32);
6792 macro_build (NULL
, "dror", "d,w,<", dreg
, sreg
, rot
);
6797 macro_build (NULL
, "dsrl", "d,w,<", dreg
, sreg
, 0);
6800 l
= (rot
< 0x20) ? "dsll" : "dsll32";
6801 r
= ((0x40 - rot
) < 0x20) ? "dsrl" : "dsrl32";
6804 macro_build (NULL
, l
, "d,w,<", AT
, sreg
, rot
);
6805 macro_build (NULL
, r
, "d,w,<", dreg
, sreg
, (0x20 - rot
) & 0x1f);
6806 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
6814 if (imm_expr
.X_op
!= O_constant
)
6815 as_bad (_("Improper rotate count"));
6816 rot
= imm_expr
.X_add_number
& 0x1f;
6817 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
6819 macro_build (NULL
, "ror", "d,w,<", dreg
, sreg
, (32 - rot
) & 0x1f);
6824 macro_build (NULL
, "srl", "d,w,<", dreg
, sreg
, 0);
6828 macro_build (NULL
, "sll", "d,w,<", AT
, sreg
, rot
);
6829 macro_build (NULL
, "srl", "d,w,<", dreg
, sreg
, (0x20 - rot
) & 0x1f);
6830 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
6835 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
6837 macro_build (NULL
, "drorv", "d,t,s", dreg
, sreg
, treg
);
6841 macro_build (NULL
, "dsubu", "d,v,t", AT
, 0, treg
);
6842 macro_build (NULL
, "dsllv", "d,t,s", AT
, sreg
, AT
);
6843 macro_build (NULL
, "dsrlv", "d,t,s", dreg
, sreg
, treg
);
6844 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
6848 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
6850 macro_build (NULL
, "rorv", "d,t,s", dreg
, sreg
, treg
);
6854 macro_build (NULL
, "subu", "d,v,t", AT
, 0, treg
);
6855 macro_build (NULL
, "sllv", "d,t,s", AT
, sreg
, AT
);
6856 macro_build (NULL
, "srlv", "d,t,s", dreg
, sreg
, treg
);
6857 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
6865 if (imm_expr
.X_op
!= O_constant
)
6866 as_bad (_("Improper rotate count"));
6867 rot
= imm_expr
.X_add_number
& 0x3f;
6868 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
6871 macro_build (NULL
, "dror32", "d,w,<", dreg
, sreg
, rot
- 32);
6873 macro_build (NULL
, "dror", "d,w,<", dreg
, sreg
, rot
);
6878 macro_build (NULL
, "dsrl", "d,w,<", dreg
, sreg
, 0);
6881 r
= (rot
< 0x20) ? "dsrl" : "dsrl32";
6882 l
= ((0x40 - rot
) < 0x20) ? "dsll" : "dsll32";
6885 macro_build (NULL
, r
, "d,w,<", AT
, sreg
, rot
);
6886 macro_build (NULL
, l
, "d,w,<", dreg
, sreg
, (0x20 - rot
) & 0x1f);
6887 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
6895 if (imm_expr
.X_op
!= O_constant
)
6896 as_bad (_("Improper rotate count"));
6897 rot
= imm_expr
.X_add_number
& 0x1f;
6898 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
6900 macro_build (NULL
, "ror", "d,w,<", dreg
, sreg
, rot
);
6905 macro_build (NULL
, "srl", "d,w,<", dreg
, sreg
, 0);
6909 macro_build (NULL
, "srl", "d,w,<", AT
, sreg
, rot
);
6910 macro_build (NULL
, "sll", "d,w,<", dreg
, sreg
, (0x20 - rot
) & 0x1f);
6911 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
6916 if (mips_opts
.arch
== CPU_R4650
)
6918 as_bad (_("opcode not supported on this processor"));
6921 assert (mips_opts
.isa
== ISA_MIPS1
);
6922 /* Even on a big endian machine $fn comes before $fn+1. We have
6923 to adjust when storing to memory. */
6924 macro_build (&offset_expr
, "swc1", "T,o(b)",
6925 target_big_endian
? treg
+ 1 : treg
, BFD_RELOC_LO16
, breg
);
6926 offset_expr
.X_add_number
+= 4;
6927 macro_build (&offset_expr
, "swc1", "T,o(b)",
6928 target_big_endian
? treg
: treg
+ 1, BFD_RELOC_LO16
, breg
);
6933 macro_build (&expr1
, "sltiu", "t,r,j", dreg
, treg
, BFD_RELOC_LO16
);
6935 macro_build (&expr1
, "sltiu", "t,r,j", dreg
, sreg
, BFD_RELOC_LO16
);
6938 macro_build (NULL
, "xor", "d,v,t", dreg
, sreg
, treg
);
6939 macro_build (&expr1
, "sltiu", "t,r,j", dreg
, dreg
, BFD_RELOC_LO16
);
6944 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
6946 macro_build (&expr1
, "sltiu", "t,r,j", dreg
, sreg
, BFD_RELOC_LO16
);
6951 as_warn (_("Instruction %s: result is always false"),
6953 move_register (dreg
, 0);
6956 if (imm_expr
.X_op
== O_constant
6957 && imm_expr
.X_add_number
>= 0
6958 && imm_expr
.X_add_number
< 0x10000)
6960 macro_build (&imm_expr
, "xori", "t,r,i", dreg
, sreg
, BFD_RELOC_LO16
);
6962 else if (imm_expr
.X_op
== O_constant
6963 && imm_expr
.X_add_number
> -0x8000
6964 && imm_expr
.X_add_number
< 0)
6966 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
6967 macro_build (&imm_expr
, HAVE_32BIT_GPRS
? "addiu" : "daddiu",
6968 "t,r,j", dreg
, sreg
, BFD_RELOC_LO16
);
6972 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
6973 macro_build (NULL
, "xor", "d,v,t", dreg
, sreg
, AT
);
6976 macro_build (&expr1
, "sltiu", "t,r,j", dreg
, dreg
, BFD_RELOC_LO16
);
6979 case M_SGE
: /* sreg >= treg <==> not (sreg < treg) */
6985 macro_build (NULL
, s
, "d,v,t", dreg
, sreg
, treg
);
6986 macro_build (&expr1
, "xori", "t,r,i", dreg
, dreg
, BFD_RELOC_LO16
);
6989 case M_SGE_I
: /* sreg >= I <==> not (sreg < I) */
6991 if (imm_expr
.X_op
== O_constant
6992 && imm_expr
.X_add_number
>= -0x8000
6993 && imm_expr
.X_add_number
< 0x8000)
6995 macro_build (&imm_expr
, mask
== M_SGE_I
? "slti" : "sltiu", "t,r,j",
6996 dreg
, sreg
, BFD_RELOC_LO16
);
7000 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7001 macro_build (NULL
, mask
== M_SGE_I
? "slt" : "sltu", "d,v,t",
7005 macro_build (&expr1
, "xori", "t,r,i", dreg
, dreg
, BFD_RELOC_LO16
);
7008 case M_SGT
: /* sreg > treg <==> treg < sreg */
7014 macro_build (NULL
, s
, "d,v,t", dreg
, treg
, sreg
);
7017 case M_SGT_I
: /* sreg > I <==> I < sreg */
7024 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7025 macro_build (NULL
, s
, "d,v,t", dreg
, AT
, sreg
);
7028 case M_SLE
: /* sreg <= treg <==> treg >= sreg <==> not (treg < sreg) */
7034 macro_build (NULL
, s
, "d,v,t", dreg
, treg
, sreg
);
7035 macro_build (&expr1
, "xori", "t,r,i", dreg
, dreg
, BFD_RELOC_LO16
);
7038 case M_SLE_I
: /* sreg <= I <==> I >= sreg <==> not (I < sreg) */
7045 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7046 macro_build (NULL
, s
, "d,v,t", dreg
, AT
, sreg
);
7047 macro_build (&expr1
, "xori", "t,r,i", dreg
, dreg
, BFD_RELOC_LO16
);
7051 if (imm_expr
.X_op
== O_constant
7052 && imm_expr
.X_add_number
>= -0x8000
7053 && imm_expr
.X_add_number
< 0x8000)
7055 macro_build (&imm_expr
, "slti", "t,r,j", dreg
, sreg
, BFD_RELOC_LO16
);
7059 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7060 macro_build (NULL
, "slt", "d,v,t", dreg
, sreg
, AT
);
7064 if (imm_expr
.X_op
== O_constant
7065 && imm_expr
.X_add_number
>= -0x8000
7066 && imm_expr
.X_add_number
< 0x8000)
7068 macro_build (&imm_expr
, "sltiu", "t,r,j", dreg
, sreg
,
7073 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7074 macro_build (NULL
, "sltu", "d,v,t", dreg
, sreg
, AT
);
7079 macro_build (NULL
, "sltu", "d,v,t", dreg
, 0, treg
);
7081 macro_build (NULL
, "sltu", "d,v,t", dreg
, 0, sreg
);
7084 macro_build (NULL
, "xor", "d,v,t", dreg
, sreg
, treg
);
7085 macro_build (NULL
, "sltu", "d,v,t", dreg
, 0, dreg
);
7090 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
7092 macro_build (NULL
, "sltu", "d,v,t", dreg
, 0, sreg
);
7097 as_warn (_("Instruction %s: result is always true"),
7099 macro_build (&expr1
, HAVE_32BIT_GPRS
? "addiu" : "daddiu", "t,r,j",
7100 dreg
, 0, BFD_RELOC_LO16
);
7103 if (imm_expr
.X_op
== O_constant
7104 && imm_expr
.X_add_number
>= 0
7105 && imm_expr
.X_add_number
< 0x10000)
7107 macro_build (&imm_expr
, "xori", "t,r,i", dreg
, sreg
, BFD_RELOC_LO16
);
7109 else if (imm_expr
.X_op
== O_constant
7110 && imm_expr
.X_add_number
> -0x8000
7111 && imm_expr
.X_add_number
< 0)
7113 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
7114 macro_build (&imm_expr
, HAVE_32BIT_GPRS
? "addiu" : "daddiu",
7115 "t,r,j", dreg
, sreg
, BFD_RELOC_LO16
);
7119 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7120 macro_build (NULL
, "xor", "d,v,t", dreg
, sreg
, AT
);
7123 macro_build (NULL
, "sltu", "d,v,t", dreg
, 0, dreg
);
7129 if (imm_expr
.X_op
== O_constant
7130 && imm_expr
.X_add_number
> -0x8000
7131 && imm_expr
.X_add_number
<= 0x8000)
7133 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
7134 macro_build (&imm_expr
, dbl
? "daddi" : "addi", "t,r,j",
7135 dreg
, sreg
, BFD_RELOC_LO16
);
7139 load_register (AT
, &imm_expr
, dbl
);
7140 macro_build (NULL
, dbl
? "dsub" : "sub", "d,v,t", dreg
, sreg
, AT
);
7146 if (imm_expr
.X_op
== O_constant
7147 && imm_expr
.X_add_number
> -0x8000
7148 && imm_expr
.X_add_number
<= 0x8000)
7150 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
7151 macro_build (&imm_expr
, dbl
? "daddiu" : "addiu", "t,r,j",
7152 dreg
, sreg
, BFD_RELOC_LO16
);
7156 load_register (AT
, &imm_expr
, dbl
);
7157 macro_build (NULL
, dbl
? "dsubu" : "subu", "d,v,t", dreg
, sreg
, AT
);
7179 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7180 macro_build (NULL
, s
, "s,t", sreg
, AT
);
7185 assert (mips_opts
.isa
== ISA_MIPS1
);
7187 sreg
= (ip
->insn_opcode
>> 11) & 0x1f; /* floating reg */
7188 dreg
= (ip
->insn_opcode
>> 06) & 0x1f; /* floating reg */
7191 * Is the double cfc1 instruction a bug in the mips assembler;
7192 * or is there a reason for it?
7194 mips_emit_delays (TRUE
);
7195 ++mips_opts
.noreorder
;
7196 mips_any_noreorder
= 1;
7197 macro_build (NULL
, "cfc1", "t,G", treg
, RA
);
7198 macro_build (NULL
, "cfc1", "t,G", treg
, RA
);
7199 macro_build (NULL
, "nop", "");
7200 expr1
.X_add_number
= 3;
7201 macro_build (&expr1
, "ori", "t,r,i", AT
, treg
, BFD_RELOC_LO16
);
7202 expr1
.X_add_number
= 2;
7203 macro_build (&expr1
, "xori", "t,r,i", AT
, AT
, BFD_RELOC_LO16
);
7204 macro_build (NULL
, "ctc1", "t,G", AT
, RA
);
7205 macro_build (NULL
, "nop", "");
7206 macro_build (NULL
, mask
== M_TRUNCWD
? "cvt.w.d" : "cvt.w.s", "D,S",
7208 macro_build (NULL
, "ctc1", "t,G", treg
, RA
);
7209 macro_build (NULL
, "nop", "");
7210 --mips_opts
.noreorder
;
7220 if (offset_expr
.X_add_number
>= 0x7fff)
7221 as_bad (_("operand overflow"));
7222 if (! target_big_endian
)
7223 ++offset_expr
.X_add_number
;
7224 macro_build (&offset_expr
, s
, "t,o(b)", AT
, BFD_RELOC_LO16
, breg
);
7225 if (! target_big_endian
)
7226 --offset_expr
.X_add_number
;
7228 ++offset_expr
.X_add_number
;
7229 macro_build (&offset_expr
, "lbu", "t,o(b)", treg
, BFD_RELOC_LO16
, breg
);
7230 macro_build (NULL
, "sll", "d,w,<", AT
, AT
, 8);
7231 macro_build (NULL
, "or", "d,v,t", treg
, treg
, AT
);
7244 if (offset_expr
.X_add_number
>= 0x8000 - off
)
7245 as_bad (_("operand overflow"));
7253 if (! target_big_endian
)
7254 offset_expr
.X_add_number
+= off
;
7255 macro_build (&offset_expr
, s
, "t,o(b)", tempreg
, BFD_RELOC_LO16
, breg
);
7256 if (! target_big_endian
)
7257 offset_expr
.X_add_number
-= off
;
7259 offset_expr
.X_add_number
+= off
;
7260 macro_build (&offset_expr
, s2
, "t,o(b)", tempreg
, BFD_RELOC_LO16
, breg
);
7262 /* If necessary, move the result in tempreg the final destination. */
7263 if (treg
== tempreg
)
7265 /* Protect second load's delay slot. */
7267 move_register (treg
, tempreg
);
7281 load_address (AT
, &offset_expr
, &used_at
);
7283 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, AT
, breg
);
7284 if (! target_big_endian
)
7285 expr1
.X_add_number
= off
;
7287 expr1
.X_add_number
= 0;
7288 macro_build (&expr1
, s
, "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
7289 if (! target_big_endian
)
7290 expr1
.X_add_number
= 0;
7292 expr1
.X_add_number
= off
;
7293 macro_build (&expr1
, s2
, "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
7299 load_address (AT
, &offset_expr
, &used_at
);
7301 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, AT
, breg
);
7302 if (target_big_endian
)
7303 expr1
.X_add_number
= 0;
7304 macro_build (&expr1
, mask
== M_ULH_A
? "lb" : "lbu", "t,o(b)",
7305 treg
, BFD_RELOC_LO16
, AT
);
7306 if (target_big_endian
)
7307 expr1
.X_add_number
= 1;
7309 expr1
.X_add_number
= 0;
7310 macro_build (&expr1
, "lbu", "t,o(b)", AT
, BFD_RELOC_LO16
, AT
);
7311 macro_build (NULL
, "sll", "d,w,<", treg
, treg
, 8);
7312 macro_build (NULL
, "or", "d,v,t", treg
, treg
, AT
);
7317 if (offset_expr
.X_add_number
>= 0x7fff)
7318 as_bad (_("operand overflow"));
7319 if (target_big_endian
)
7320 ++offset_expr
.X_add_number
;
7321 macro_build (&offset_expr
, "sb", "t,o(b)", treg
, BFD_RELOC_LO16
, breg
);
7322 macro_build (NULL
, "srl", "d,w,<", AT
, treg
, 8);
7323 if (target_big_endian
)
7324 --offset_expr
.X_add_number
;
7326 ++offset_expr
.X_add_number
;
7327 macro_build (&offset_expr
, "sb", "t,o(b)", AT
, BFD_RELOC_LO16
, breg
);
7340 if (offset_expr
.X_add_number
>= 0x8000 - off
)
7341 as_bad (_("operand overflow"));
7342 if (! target_big_endian
)
7343 offset_expr
.X_add_number
+= off
;
7344 macro_build (&offset_expr
, s
, "t,o(b)", treg
, BFD_RELOC_LO16
, breg
);
7345 if (! target_big_endian
)
7346 offset_expr
.X_add_number
-= off
;
7348 offset_expr
.X_add_number
+= off
;
7349 macro_build (&offset_expr
, s2
, "t,o(b)", treg
, BFD_RELOC_LO16
, breg
);
7363 load_address (AT
, &offset_expr
, &used_at
);
7365 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, AT
, breg
);
7366 if (! target_big_endian
)
7367 expr1
.X_add_number
= off
;
7369 expr1
.X_add_number
= 0;
7370 macro_build (&expr1
, s
, "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
7371 if (! target_big_endian
)
7372 expr1
.X_add_number
= 0;
7374 expr1
.X_add_number
= off
;
7375 macro_build (&expr1
, s2
, "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
7380 load_address (AT
, &offset_expr
, &used_at
);
7382 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, AT
, breg
);
7383 if (! target_big_endian
)
7384 expr1
.X_add_number
= 0;
7385 macro_build (&expr1
, "sb", "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
7386 macro_build (NULL
, "srl", "d,w,<", treg
, treg
, 8);
7387 if (! target_big_endian
)
7388 expr1
.X_add_number
= 1;
7390 expr1
.X_add_number
= 0;
7391 macro_build (&expr1
, "sb", "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
7392 if (! target_big_endian
)
7393 expr1
.X_add_number
= 0;
7395 expr1
.X_add_number
= 1;
7396 macro_build (&expr1
, "lbu", "t,o(b)", AT
, BFD_RELOC_LO16
, AT
);
7397 macro_build (NULL
, "sll", "d,w,<", treg
, treg
, 8);
7398 macro_build (NULL
, "or", "d,v,t", treg
, treg
, AT
);
7402 /* FIXME: Check if this is one of the itbl macros, since they
7403 are added dynamically. */
7404 as_bad (_("Macro %s not implemented yet"), ip
->insn_mo
->name
);
7407 if (mips_opts
.noat
&& used_at
)
7408 as_bad (_("Macro used $at after \".set noat\""));
7411 /* Implement macros in mips16 mode. */
7414 mips16_macro (struct mips_cl_insn
*ip
)
7417 int xreg
, yreg
, zreg
, tmp
;
7420 const char *s
, *s2
, *s3
;
7422 mask
= ip
->insn_mo
->mask
;
7424 xreg
= MIPS16_EXTRACT_OPERAND (RX
, *ip
);
7425 yreg
= MIPS16_EXTRACT_OPERAND (RY
, *ip
);
7426 zreg
= MIPS16_EXTRACT_OPERAND (RZ
, *ip
);
7428 expr1
.X_op
= O_constant
;
7429 expr1
.X_op_symbol
= NULL
;
7430 expr1
.X_add_symbol
= NULL
;
7431 expr1
.X_add_number
= 1;
7450 mips_emit_delays (TRUE
);
7451 ++mips_opts
.noreorder
;
7452 mips_any_noreorder
= 1;
7453 macro_build (NULL
, dbl
? "ddiv" : "div", "0,x,y", xreg
, yreg
);
7454 expr1
.X_add_number
= 2;
7455 macro_build (&expr1
, "bnez", "x,p", yreg
);
7456 macro_build (NULL
, "break", "6", 7);
7458 /* FIXME: The normal code checks for of -1 / -0x80000000 here,
7459 since that causes an overflow. We should do that as well,
7460 but I don't see how to do the comparisons without a temporary
7462 --mips_opts
.noreorder
;
7463 macro_build (NULL
, s
, "x", zreg
);
7482 mips_emit_delays (TRUE
);
7483 ++mips_opts
.noreorder
;
7484 mips_any_noreorder
= 1;
7485 macro_build (NULL
, s
, "0,x,y", xreg
, yreg
);
7486 expr1
.X_add_number
= 2;
7487 macro_build (&expr1
, "bnez", "x,p", yreg
);
7488 macro_build (NULL
, "break", "6", 7);
7489 --mips_opts
.noreorder
;
7490 macro_build (NULL
, s2
, "x", zreg
);
7496 macro_build (NULL
, dbl
? "dmultu" : "multu", "x,y", xreg
, yreg
);
7497 macro_build (NULL
, "mflo", "x", zreg
);
7505 if (imm_expr
.X_op
!= O_constant
)
7506 as_bad (_("Unsupported large constant"));
7507 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
7508 macro_build (&imm_expr
, dbl
? "daddiu" : "addiu", "y,x,4", yreg
, xreg
);
7512 if (imm_expr
.X_op
!= O_constant
)
7513 as_bad (_("Unsupported large constant"));
7514 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
7515 macro_build (&imm_expr
, "addiu", "x,k", xreg
);
7519 if (imm_expr
.X_op
!= O_constant
)
7520 as_bad (_("Unsupported large constant"));
7521 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
7522 macro_build (&imm_expr
, "daddiu", "y,j", yreg
);
7544 goto do_reverse_branch
;
7548 goto do_reverse_branch
;
7560 goto do_reverse_branch
;
7571 macro_build (NULL
, s
, "x,y", xreg
, yreg
);
7572 macro_build (&offset_expr
, s2
, "p");
7599 goto do_addone_branch_i
;
7604 goto do_addone_branch_i
;
7619 goto do_addone_branch_i
;
7626 if (imm_expr
.X_op
!= O_constant
)
7627 as_bad (_("Unsupported large constant"));
7628 ++imm_expr
.X_add_number
;
7631 macro_build (&imm_expr
, s
, s3
, xreg
);
7632 macro_build (&offset_expr
, s2
, "p");
7636 expr1
.X_add_number
= 0;
7637 macro_build (&expr1
, "slti", "x,8", yreg
);
7639 move_register (xreg
, yreg
);
7640 expr1
.X_add_number
= 2;
7641 macro_build (&expr1
, "bteqz", "p");
7642 macro_build (NULL
, "neg", "x,w", xreg
, xreg
);
7646 /* For consistency checking, verify that all bits are specified either
7647 by the match/mask part of the instruction definition, or by the
7650 validate_mips_insn (const struct mips_opcode
*opc
)
7652 const char *p
= opc
->args
;
7654 unsigned long used_bits
= opc
->mask
;
7656 if ((used_bits
& opc
->match
) != opc
->match
)
7658 as_bad (_("internal: bad mips opcode (mask error): %s %s"),
7659 opc
->name
, opc
->args
);
7662 #define USE_BITS(mask,shift) (used_bits |= ((mask) << (shift)))
7672 case 'A': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
7673 case 'B': USE_BITS (OP_MASK_INSMSB
, OP_SH_INSMSB
); break;
7674 case 'C': USE_BITS (OP_MASK_EXTMSBD
, OP_SH_EXTMSBD
); break;
7675 case 'D': USE_BITS (OP_MASK_RD
, OP_SH_RD
);
7676 USE_BITS (OP_MASK_SEL
, OP_SH_SEL
); break;
7677 case 'E': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
7678 case 'F': USE_BITS (OP_MASK_INSMSB
, OP_SH_INSMSB
); break;
7679 case 'G': USE_BITS (OP_MASK_EXTMSBD
, OP_SH_EXTMSBD
); break;
7680 case 'H': USE_BITS (OP_MASK_EXTMSBD
, OP_SH_EXTMSBD
); break;
7683 as_bad (_("internal: bad mips opcode (unknown extension operand type `+%c'): %s %s"),
7684 c
, opc
->name
, opc
->args
);
7688 case '<': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
7689 case '>': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
7691 case 'B': USE_BITS (OP_MASK_CODE20
, OP_SH_CODE20
); break;
7692 case 'C': USE_BITS (OP_MASK_COPZ
, OP_SH_COPZ
); break;
7693 case 'D': USE_BITS (OP_MASK_FD
, OP_SH_FD
); break;
7694 case 'E': USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
7696 case 'G': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
7697 case 'H': USE_BITS (OP_MASK_SEL
, OP_SH_SEL
); break;
7699 case 'J': USE_BITS (OP_MASK_CODE19
, OP_SH_CODE19
); break;
7700 case 'K': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
7702 case 'M': USE_BITS (OP_MASK_CCC
, OP_SH_CCC
); break;
7703 case 'N': USE_BITS (OP_MASK_BCC
, OP_SH_BCC
); break;
7704 case 'O': USE_BITS (OP_MASK_ALN
, OP_SH_ALN
); break;
7705 case 'Q': USE_BITS (OP_MASK_VSEL
, OP_SH_VSEL
);
7706 USE_BITS (OP_MASK_FT
, OP_SH_FT
); break;
7707 case 'R': USE_BITS (OP_MASK_FR
, OP_SH_FR
); break;
7708 case 'S': USE_BITS (OP_MASK_FS
, OP_SH_FS
); break;
7709 case 'T': USE_BITS (OP_MASK_FT
, OP_SH_FT
); break;
7710 case 'V': USE_BITS (OP_MASK_FS
, OP_SH_FS
); break;
7711 case 'W': USE_BITS (OP_MASK_FT
, OP_SH_FT
); break;
7712 case 'X': USE_BITS (OP_MASK_FD
, OP_SH_FD
); break;
7713 case 'Y': USE_BITS (OP_MASK_FS
, OP_SH_FS
); break;
7714 case 'Z': USE_BITS (OP_MASK_FT
, OP_SH_FT
); break;
7715 case 'a': USE_BITS (OP_MASK_TARGET
, OP_SH_TARGET
); break;
7716 case 'b': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
7717 case 'c': USE_BITS (OP_MASK_CODE
, OP_SH_CODE
); break;
7718 case 'd': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
7720 case 'h': USE_BITS (OP_MASK_PREFX
, OP_SH_PREFX
); break;
7721 case 'i': USE_BITS (OP_MASK_IMMEDIATE
, OP_SH_IMMEDIATE
); break;
7722 case 'j': USE_BITS (OP_MASK_DELTA
, OP_SH_DELTA
); break;
7723 case 'k': USE_BITS (OP_MASK_CACHE
, OP_SH_CACHE
); break;
7725 case 'o': USE_BITS (OP_MASK_DELTA
, OP_SH_DELTA
); break;
7726 case 'p': USE_BITS (OP_MASK_DELTA
, OP_SH_DELTA
); break;
7727 case 'q': USE_BITS (OP_MASK_CODE2
, OP_SH_CODE2
); break;
7728 case 'r': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
7729 case 's': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
7730 case 't': USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
7731 case 'u': USE_BITS (OP_MASK_IMMEDIATE
, OP_SH_IMMEDIATE
); break;
7732 case 'v': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
7733 case 'w': USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
7736 case 'P': USE_BITS (OP_MASK_PERFREG
, OP_SH_PERFREG
); break;
7737 case 'U': USE_BITS (OP_MASK_RD
, OP_SH_RD
);
7738 USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
7739 case 'e': USE_BITS (OP_MASK_VECBYTE
, OP_SH_VECBYTE
); break;
7740 case '%': USE_BITS (OP_MASK_VECALIGN
, OP_SH_VECALIGN
); break;
7744 as_bad (_("internal: bad mips opcode (unknown operand type `%c'): %s %s"),
7745 c
, opc
->name
, opc
->args
);
7749 if (used_bits
!= 0xffffffff)
7751 as_bad (_("internal: bad mips opcode (bits 0x%lx undefined): %s %s"),
7752 ~used_bits
& 0xffffffff, opc
->name
, opc
->args
);
7758 /* This routine assembles an instruction into its binary format. As a
7759 side effect, it sets one of the global variables imm_reloc or
7760 offset_reloc to the type of relocation to do if one of the operands
7761 is an address expression. */
7764 mips_ip (char *str
, struct mips_cl_insn
*ip
)
7769 struct mips_opcode
*insn
;
7772 unsigned int lastregno
= 0;
7773 unsigned int lastpos
= 0;
7774 unsigned int limlo
, limhi
;
7780 /* If the instruction contains a '.', we first try to match an instruction
7781 including the '.'. Then we try again without the '.'. */
7783 for (s
= str
; *s
!= '\0' && !ISSPACE (*s
); ++s
)
7786 /* If we stopped on whitespace, then replace the whitespace with null for
7787 the call to hash_find. Save the character we replaced just in case we
7788 have to re-parse the instruction. */
7795 insn
= (struct mips_opcode
*) hash_find (op_hash
, str
);
7797 /* If we didn't find the instruction in the opcode table, try again, but
7798 this time with just the instruction up to, but not including the
7802 /* Restore the character we overwrite above (if any). */
7806 /* Scan up to the first '.' or whitespace. */
7808 *s
!= '\0' && *s
!= '.' && !ISSPACE (*s
);
7812 /* If we did not find a '.', then we can quit now. */
7815 insn_error
= "unrecognized opcode";
7819 /* Lookup the instruction in the hash table. */
7821 if ((insn
= (struct mips_opcode
*) hash_find (op_hash
, str
)) == NULL
)
7823 insn_error
= "unrecognized opcode";
7833 assert (strcmp (insn
->name
, str
) == 0);
7835 if (OPCODE_IS_MEMBER (insn
,
7837 | (file_ase_mips16
? INSN_MIPS16
: 0)
7838 | (mips_opts
.ase_mdmx
? INSN_MDMX
: 0)
7839 | (mips_opts
.ase_mips3d
? INSN_MIPS3D
: 0)),
7845 if (insn
->pinfo
!= INSN_MACRO
)
7847 if (mips_opts
.arch
== CPU_R4650
&& (insn
->pinfo
& FP_D
) != 0)
7853 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
]
7854 && strcmp (insn
->name
, insn
[1].name
) == 0)
7863 static char buf
[100];
7865 _("opcode not supported on this processor: %s (%s)"),
7866 mips_cpu_info_from_arch (mips_opts
.arch
)->name
,
7867 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
7876 create_insn (ip
, insn
);
7878 for (args
= insn
->args
;; ++args
)
7882 s
+= strspn (s
, " \t");
7886 case '\0': /* end of args */
7899 INSERT_OPERAND (RS
, *ip
, lastregno
);
7903 INSERT_OPERAND (RT
, *ip
, lastregno
);
7907 INSERT_OPERAND (FT
, *ip
, lastregno
);
7911 INSERT_OPERAND (FS
, *ip
, lastregno
);
7917 /* Handle optional base register.
7918 Either the base register is omitted or
7919 we must have a left paren. */
7920 /* This is dependent on the next operand specifier
7921 is a base register specification. */
7922 assert (args
[1] == 'b' || args
[1] == '5'
7923 || args
[1] == '-' || args
[1] == '4');
7927 case ')': /* these must match exactly */
7934 case '+': /* Opcode extension character. */
7937 case 'A': /* ins/ext position, becomes LSB. */
7946 my_getExpression (&imm_expr
, s
);
7947 check_absolute_expr (ip
, &imm_expr
);
7948 if ((unsigned long) imm_expr
.X_add_number
< limlo
7949 || (unsigned long) imm_expr
.X_add_number
> limhi
)
7951 as_bad (_("Improper position (%lu)"),
7952 (unsigned long) imm_expr
.X_add_number
);
7953 imm_expr
.X_add_number
= limlo
;
7955 lastpos
= imm_expr
.X_add_number
;
7956 INSERT_OPERAND (SHAMT
, *ip
, imm_expr
.X_add_number
);
7957 imm_expr
.X_op
= O_absent
;
7961 case 'B': /* ins size, becomes MSB. */
7970 my_getExpression (&imm_expr
, s
);
7971 check_absolute_expr (ip
, &imm_expr
);
7972 /* Check for negative input so that small negative numbers
7973 will not succeed incorrectly. The checks against
7974 (pos+size) transitively check "size" itself,
7975 assuming that "pos" is reasonable. */
7976 if ((long) imm_expr
.X_add_number
< 0
7977 || ((unsigned long) imm_expr
.X_add_number
7979 || ((unsigned long) imm_expr
.X_add_number
7982 as_bad (_("Improper insert size (%lu, position %lu)"),
7983 (unsigned long) imm_expr
.X_add_number
,
7984 (unsigned long) lastpos
);
7985 imm_expr
.X_add_number
= limlo
- lastpos
;
7987 INSERT_OPERAND (INSMSB
, *ip
,
7988 lastpos
+ imm_expr
.X_add_number
- 1);
7989 imm_expr
.X_op
= O_absent
;
7993 case 'C': /* ext size, becomes MSBD. */
8006 my_getExpression (&imm_expr
, s
);
8007 check_absolute_expr (ip
, &imm_expr
);
8008 /* Check for negative input so that small negative numbers
8009 will not succeed incorrectly. The checks against
8010 (pos+size) transitively check "size" itself,
8011 assuming that "pos" is reasonable. */
8012 if ((long) imm_expr
.X_add_number
< 0
8013 || ((unsigned long) imm_expr
.X_add_number
8015 || ((unsigned long) imm_expr
.X_add_number
8018 as_bad (_("Improper extract size (%lu, position %lu)"),
8019 (unsigned long) imm_expr
.X_add_number
,
8020 (unsigned long) lastpos
);
8021 imm_expr
.X_add_number
= limlo
- lastpos
;
8023 INSERT_OPERAND (EXTMSBD
, *ip
, imm_expr
.X_add_number
- 1);
8024 imm_expr
.X_op
= O_absent
;
8029 /* +D is for disassembly only; never match. */
8033 /* "+I" is like "I", except that imm2_expr is used. */
8034 my_getExpression (&imm2_expr
, s
);
8035 if (imm2_expr
.X_op
!= O_big
8036 && imm2_expr
.X_op
!= O_constant
)
8037 insn_error
= _("absolute expression required");
8038 normalize_constant_expr (&imm2_expr
);
8043 as_bad (_("internal: bad mips opcode (unknown extension operand type `+%c'): %s %s"),
8044 *args
, insn
->name
, insn
->args
);
8045 /* Further processing is fruitless. */
8050 case '<': /* must be at least one digit */
8052 * According to the manual, if the shift amount is greater
8053 * than 31 or less than 0, then the shift amount should be
8054 * mod 32. In reality the mips assembler issues an error.
8055 * We issue a warning and mask out all but the low 5 bits.
8057 my_getExpression (&imm_expr
, s
);
8058 check_absolute_expr (ip
, &imm_expr
);
8059 if ((unsigned long) imm_expr
.X_add_number
> 31)
8060 as_warn (_("Improper shift amount (%lu)"),
8061 (unsigned long) imm_expr
.X_add_number
);
8062 INSERT_OPERAND (SHAMT
, *ip
, imm_expr
.X_add_number
);
8063 imm_expr
.X_op
= O_absent
;
8067 case '>': /* shift amount minus 32 */
8068 my_getExpression (&imm_expr
, s
);
8069 check_absolute_expr (ip
, &imm_expr
);
8070 if ((unsigned long) imm_expr
.X_add_number
< 32
8071 || (unsigned long) imm_expr
.X_add_number
> 63)
8073 INSERT_OPERAND (SHAMT
, *ip
, imm_expr
.X_add_number
- 32);
8074 imm_expr
.X_op
= O_absent
;
8078 case 'k': /* cache code */
8079 case 'h': /* prefx code */
8080 my_getExpression (&imm_expr
, s
);
8081 check_absolute_expr (ip
, &imm_expr
);
8082 if ((unsigned long) imm_expr
.X_add_number
> 31)
8083 as_warn (_("Invalid value for `%s' (%lu)"),
8085 (unsigned long) imm_expr
.X_add_number
);
8087 INSERT_OPERAND (CACHE
, *ip
, imm_expr
.X_add_number
);
8089 INSERT_OPERAND (PREFX
, *ip
, imm_expr
.X_add_number
);
8090 imm_expr
.X_op
= O_absent
;
8094 case 'c': /* break code */
8095 my_getExpression (&imm_expr
, s
);
8096 check_absolute_expr (ip
, &imm_expr
);
8097 if ((unsigned long) imm_expr
.X_add_number
> 1023)
8098 as_warn (_("Illegal break code (%lu)"),
8099 (unsigned long) imm_expr
.X_add_number
);
8100 INSERT_OPERAND (CODE
, *ip
, imm_expr
.X_add_number
);
8101 imm_expr
.X_op
= O_absent
;
8105 case 'q': /* lower break code */
8106 my_getExpression (&imm_expr
, s
);
8107 check_absolute_expr (ip
, &imm_expr
);
8108 if ((unsigned long) imm_expr
.X_add_number
> 1023)
8109 as_warn (_("Illegal lower break code (%lu)"),
8110 (unsigned long) imm_expr
.X_add_number
);
8111 INSERT_OPERAND (CODE2
, *ip
, imm_expr
.X_add_number
);
8112 imm_expr
.X_op
= O_absent
;
8116 case 'B': /* 20-bit syscall/break code. */
8117 my_getExpression (&imm_expr
, s
);
8118 check_absolute_expr (ip
, &imm_expr
);
8119 if ((unsigned long) imm_expr
.X_add_number
> OP_MASK_CODE20
)
8120 as_warn (_("Illegal 20-bit code (%lu)"),
8121 (unsigned long) imm_expr
.X_add_number
);
8122 INSERT_OPERAND (CODE20
, *ip
, imm_expr
.X_add_number
);
8123 imm_expr
.X_op
= O_absent
;
8127 case 'C': /* Coprocessor code */
8128 my_getExpression (&imm_expr
, s
);
8129 check_absolute_expr (ip
, &imm_expr
);
8130 if ((unsigned long) imm_expr
.X_add_number
>= (1 << 25))
8132 as_warn (_("Coproccesor code > 25 bits (%lu)"),
8133 (unsigned long) imm_expr
.X_add_number
);
8134 imm_expr
.X_add_number
&= ((1 << 25) - 1);
8136 ip
->insn_opcode
|= imm_expr
.X_add_number
;
8137 imm_expr
.X_op
= O_absent
;
8141 case 'J': /* 19-bit wait code. */
8142 my_getExpression (&imm_expr
, s
);
8143 check_absolute_expr (ip
, &imm_expr
);
8144 if ((unsigned long) imm_expr
.X_add_number
> OP_MASK_CODE19
)
8145 as_warn (_("Illegal 19-bit code (%lu)"),
8146 (unsigned long) imm_expr
.X_add_number
);
8147 INSERT_OPERAND (CODE19
, *ip
, imm_expr
.X_add_number
);
8148 imm_expr
.X_op
= O_absent
;
8152 case 'P': /* Performance register */
8153 my_getExpression (&imm_expr
, s
);
8154 check_absolute_expr (ip
, &imm_expr
);
8155 if (imm_expr
.X_add_number
!= 0 && imm_expr
.X_add_number
!= 1)
8156 as_warn (_("Invalid performance register (%lu)"),
8157 (unsigned long) imm_expr
.X_add_number
);
8158 INSERT_OPERAND (PERFREG
, *ip
, imm_expr
.X_add_number
);
8159 imm_expr
.X_op
= O_absent
;
8163 case 'b': /* base register */
8164 case 'd': /* destination register */
8165 case 's': /* source register */
8166 case 't': /* target register */
8167 case 'r': /* both target and source */
8168 case 'v': /* both dest and source */
8169 case 'w': /* both dest and target */
8170 case 'E': /* coprocessor target register */
8171 case 'G': /* coprocessor destination register */
8172 case 'K': /* 'rdhwr' destination register */
8173 case 'x': /* ignore register name */
8174 case 'z': /* must be zero register */
8175 case 'U': /* destination register (clo/clz). */
8190 while (ISDIGIT (*s
));
8192 as_bad (_("Invalid register number (%d)"), regno
);
8194 else if (*args
== 'E' || *args
== 'G' || *args
== 'K')
8198 if (s
[1] == 'r' && s
[2] == 'a')
8203 else if (s
[1] == 'f' && s
[2] == 'p')
8208 else if (s
[1] == 's' && s
[2] == 'p')
8213 else if (s
[1] == 'g' && s
[2] == 'p')
8218 else if (s
[1] == 'a' && s
[2] == 't')
8223 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '0')
8228 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '1')
8233 else if (s
[1] == 'z' && s
[2] == 'e' && s
[3] == 'r' && s
[4] == 'o')
8238 else if (itbl_have_entries
)
8243 p
= s
+ 1; /* advance past '$' */
8244 n
= itbl_get_field (&p
); /* n is name */
8246 /* See if this is a register defined in an
8248 if (itbl_get_reg_val (n
, &r
))
8250 /* Get_field advances to the start of
8251 the next field, so we need to back
8252 rack to the end of the last field. */
8256 s
= strchr (s
, '\0');
8270 as_warn (_("Used $at without \".set noat\""));
8276 if (c
== 'r' || c
== 'v' || c
== 'w')
8283 /* 'z' only matches $0. */
8284 if (c
== 'z' && regno
!= 0)
8287 /* Now that we have assembled one operand, we use the args string
8288 * to figure out where it goes in the instruction. */
8295 INSERT_OPERAND (RS
, *ip
, regno
);
8300 INSERT_OPERAND (RD
, *ip
, regno
);
8303 INSERT_OPERAND (RD
, *ip
, regno
);
8304 INSERT_OPERAND (RT
, *ip
, regno
);
8309 INSERT_OPERAND (RT
, *ip
, regno
);
8312 /* This case exists because on the r3000 trunc
8313 expands into a macro which requires a gp
8314 register. On the r6000 or r4000 it is
8315 assembled into a single instruction which
8316 ignores the register. Thus the insn version
8317 is MIPS_ISA2 and uses 'x', and the macro
8318 version is MIPS_ISA1 and uses 't'. */
8321 /* This case is for the div instruction, which
8322 acts differently if the destination argument
8323 is $0. This only matches $0, and is checked
8324 outside the switch. */
8327 /* Itbl operand; not yet implemented. FIXME ?? */
8329 /* What about all other operands like 'i', which
8330 can be specified in the opcode table? */
8340 INSERT_OPERAND (RS
, *ip
, lastregno
);
8343 INSERT_OPERAND (RT
, *ip
, lastregno
);
8348 case 'O': /* MDMX alignment immediate constant. */
8349 my_getExpression (&imm_expr
, s
);
8350 check_absolute_expr (ip
, &imm_expr
);
8351 if ((unsigned long) imm_expr
.X_add_number
> OP_MASK_ALN
)
8352 as_warn ("Improper align amount (%ld), using low bits",
8353 (long) imm_expr
.X_add_number
);
8354 INSERT_OPERAND (ALN
, *ip
, imm_expr
.X_add_number
);
8355 imm_expr
.X_op
= O_absent
;
8359 case 'Q': /* MDMX vector, element sel, or const. */
8362 /* MDMX Immediate. */
8363 my_getExpression (&imm_expr
, s
);
8364 check_absolute_expr (ip
, &imm_expr
);
8365 if ((unsigned long) imm_expr
.X_add_number
> OP_MASK_FT
)
8366 as_warn (_("Invalid MDMX Immediate (%ld)"),
8367 (long) imm_expr
.X_add_number
);
8368 INSERT_OPERAND (FT
, *ip
, imm_expr
.X_add_number
);
8369 if (ip
->insn_opcode
& (OP_MASK_VSEL
<< OP_SH_VSEL
))
8370 ip
->insn_opcode
|= MDMX_FMTSEL_IMM_QH
<< OP_SH_VSEL
;
8372 ip
->insn_opcode
|= MDMX_FMTSEL_IMM_OB
<< OP_SH_VSEL
;
8373 imm_expr
.X_op
= O_absent
;
8377 /* Not MDMX Immediate. Fall through. */
8378 case 'X': /* MDMX destination register. */
8379 case 'Y': /* MDMX source register. */
8380 case 'Z': /* MDMX target register. */
8382 case 'D': /* floating point destination register */
8383 case 'S': /* floating point source register */
8384 case 'T': /* floating point target register */
8385 case 'R': /* floating point source register */
8389 /* Accept $fN for FP and MDMX register numbers, and in
8390 addition accept $vN for MDMX register numbers. */
8391 if ((s
[0] == '$' && s
[1] == 'f' && ISDIGIT (s
[2]))
8392 || (is_mdmx
!= 0 && s
[0] == '$' && s
[1] == 'v'
8403 while (ISDIGIT (*s
));
8406 as_bad (_("Invalid float register number (%d)"), regno
);
8408 if ((regno
& 1) != 0
8410 && ! (strcmp (str
, "mtc1") == 0
8411 || strcmp (str
, "mfc1") == 0
8412 || strcmp (str
, "lwc1") == 0
8413 || strcmp (str
, "swc1") == 0
8414 || strcmp (str
, "l.s") == 0
8415 || strcmp (str
, "s.s") == 0))
8416 as_warn (_("Float register should be even, was %d"),
8424 if (c
== 'V' || c
== 'W')
8435 INSERT_OPERAND (FD
, *ip
, regno
);
8440 INSERT_OPERAND (FS
, *ip
, regno
);
8443 /* This is like 'Z', but also needs to fix the MDMX
8444 vector/scalar select bits. Note that the
8445 scalar immediate case is handled above. */
8448 int is_qh
= (ip
->insn_opcode
& (1 << OP_SH_VSEL
));
8449 int max_el
= (is_qh
? 3 : 7);
8451 my_getExpression(&imm_expr
, s
);
8452 check_absolute_expr (ip
, &imm_expr
);
8454 if (imm_expr
.X_add_number
> max_el
)
8455 as_bad(_("Bad element selector %ld"),
8456 (long) imm_expr
.X_add_number
);
8457 imm_expr
.X_add_number
&= max_el
;
8458 ip
->insn_opcode
|= (imm_expr
.X_add_number
8461 imm_expr
.X_op
= O_absent
;
8463 as_warn(_("Expecting ']' found '%s'"), s
);
8469 if (ip
->insn_opcode
& (OP_MASK_VSEL
<< OP_SH_VSEL
))
8470 ip
->insn_opcode
|= (MDMX_FMTSEL_VEC_QH
8473 ip
->insn_opcode
|= (MDMX_FMTSEL_VEC_OB
<<
8480 INSERT_OPERAND (FT
, *ip
, regno
);
8483 INSERT_OPERAND (FR
, *ip
, regno
);
8493 INSERT_OPERAND (FS
, *ip
, lastregno
);
8496 INSERT_OPERAND (FT
, *ip
, lastregno
);
8502 my_getExpression (&imm_expr
, s
);
8503 if (imm_expr
.X_op
!= O_big
8504 && imm_expr
.X_op
!= O_constant
)
8505 insn_error
= _("absolute expression required");
8506 normalize_constant_expr (&imm_expr
);
8511 my_getExpression (&offset_expr
, s
);
8512 *imm_reloc
= BFD_RELOC_32
;
8525 unsigned char temp
[8];
8527 unsigned int length
;
8532 /* These only appear as the last operand in an
8533 instruction, and every instruction that accepts
8534 them in any variant accepts them in all variants.
8535 This means we don't have to worry about backing out
8536 any changes if the instruction does not match.
8538 The difference between them is the size of the
8539 floating point constant and where it goes. For 'F'
8540 and 'L' the constant is 64 bits; for 'f' and 'l' it
8541 is 32 bits. Where the constant is placed is based
8542 on how the MIPS assembler does things:
8545 f -- immediate value
8548 The .lit4 and .lit8 sections are only used if
8549 permitted by the -G argument.
8551 The code below needs to know whether the target register
8552 is 32 or 64 bits wide. It relies on the fact 'f' and
8553 'F' are used with GPR-based instructions and 'l' and
8554 'L' are used with FPR-based instructions. */
8556 f64
= *args
== 'F' || *args
== 'L';
8557 using_gprs
= *args
== 'F' || *args
== 'f';
8559 save_in
= input_line_pointer
;
8560 input_line_pointer
= s
;
8561 err
= md_atof (f64
? 'd' : 'f', (char *) temp
, &len
);
8563 s
= input_line_pointer
;
8564 input_line_pointer
= save_in
;
8565 if (err
!= NULL
&& *err
!= '\0')
8567 as_bad (_("Bad floating point constant: %s"), err
);
8568 memset (temp
, '\0', sizeof temp
);
8569 length
= f64
? 8 : 4;
8572 assert (length
== (unsigned) (f64
? 8 : 4));
8576 && (g_switch_value
< 4
8577 || (temp
[0] == 0 && temp
[1] == 0)
8578 || (temp
[2] == 0 && temp
[3] == 0))))
8580 imm_expr
.X_op
= O_constant
;
8581 if (! target_big_endian
)
8582 imm_expr
.X_add_number
= bfd_getl32 (temp
);
8584 imm_expr
.X_add_number
= bfd_getb32 (temp
);
8587 && ! mips_disable_float_construction
8588 /* Constants can only be constructed in GPRs and
8589 copied to FPRs if the GPRs are at least as wide
8590 as the FPRs. Force the constant into memory if
8591 we are using 64-bit FPRs but the GPRs are only
8594 || ! (HAVE_64BIT_FPRS
&& HAVE_32BIT_GPRS
))
8595 && ((temp
[0] == 0 && temp
[1] == 0)
8596 || (temp
[2] == 0 && temp
[3] == 0))
8597 && ((temp
[4] == 0 && temp
[5] == 0)
8598 || (temp
[6] == 0 && temp
[7] == 0)))
8600 /* The value is simple enough to load with a couple of
8601 instructions. If using 32-bit registers, set
8602 imm_expr to the high order 32 bits and offset_expr to
8603 the low order 32 bits. Otherwise, set imm_expr to
8604 the entire 64 bit constant. */
8605 if (using_gprs
? HAVE_32BIT_GPRS
: HAVE_32BIT_FPRS
)
8607 imm_expr
.X_op
= O_constant
;
8608 offset_expr
.X_op
= O_constant
;
8609 if (! target_big_endian
)
8611 imm_expr
.X_add_number
= bfd_getl32 (temp
+ 4);
8612 offset_expr
.X_add_number
= bfd_getl32 (temp
);
8616 imm_expr
.X_add_number
= bfd_getb32 (temp
);
8617 offset_expr
.X_add_number
= bfd_getb32 (temp
+ 4);
8619 if (offset_expr
.X_add_number
== 0)
8620 offset_expr
.X_op
= O_absent
;
8622 else if (sizeof (imm_expr
.X_add_number
) > 4)
8624 imm_expr
.X_op
= O_constant
;
8625 if (! target_big_endian
)
8626 imm_expr
.X_add_number
= bfd_getl64 (temp
);
8628 imm_expr
.X_add_number
= bfd_getb64 (temp
);
8632 imm_expr
.X_op
= O_big
;
8633 imm_expr
.X_add_number
= 4;
8634 if (! target_big_endian
)
8636 generic_bignum
[0] = bfd_getl16 (temp
);
8637 generic_bignum
[1] = bfd_getl16 (temp
+ 2);
8638 generic_bignum
[2] = bfd_getl16 (temp
+ 4);
8639 generic_bignum
[3] = bfd_getl16 (temp
+ 6);
8643 generic_bignum
[0] = bfd_getb16 (temp
+ 6);
8644 generic_bignum
[1] = bfd_getb16 (temp
+ 4);
8645 generic_bignum
[2] = bfd_getb16 (temp
+ 2);
8646 generic_bignum
[3] = bfd_getb16 (temp
);
8652 const char *newname
;
8655 /* Switch to the right section. */
8657 subseg
= now_subseg
;
8660 default: /* unused default case avoids warnings. */
8662 newname
= RDATA_SECTION_NAME
;
8663 if (g_switch_value
>= 8)
8667 newname
= RDATA_SECTION_NAME
;
8670 assert (g_switch_value
>= 4);
8674 new_seg
= subseg_new (newname
, (subsegT
) 0);
8675 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
8676 bfd_set_section_flags (stdoutput
, new_seg
,
8681 frag_align (*args
== 'l' ? 2 : 3, 0, 0);
8682 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
8683 && strcmp (TARGET_OS
, "elf") != 0)
8684 record_alignment (new_seg
, 4);
8686 record_alignment (new_seg
, *args
== 'l' ? 2 : 3);
8688 as_bad (_("Can't use floating point insn in this section"));
8690 /* Set the argument to the current address in the
8692 offset_expr
.X_op
= O_symbol
;
8693 offset_expr
.X_add_symbol
=
8694 symbol_new ("L0\001", now_seg
,
8695 (valueT
) frag_now_fix (), frag_now
);
8696 offset_expr
.X_add_number
= 0;
8698 /* Put the floating point number into the section. */
8699 p
= frag_more ((int) length
);
8700 memcpy (p
, temp
, length
);
8702 /* Switch back to the original section. */
8703 subseg_set (seg
, subseg
);
8708 case 'i': /* 16 bit unsigned immediate */
8709 case 'j': /* 16 bit signed immediate */
8710 *imm_reloc
= BFD_RELOC_LO16
;
8711 if (my_getSmallExpression (&imm_expr
, imm_reloc
, s
) == 0)
8714 offsetT minval
, maxval
;
8716 more
= (insn
+ 1 < &mips_opcodes
[NUMOPCODES
]
8717 && strcmp (insn
->name
, insn
[1].name
) == 0);
8719 /* If the expression was written as an unsigned number,
8720 only treat it as signed if there are no more
8724 && sizeof (imm_expr
.X_add_number
) <= 4
8725 && imm_expr
.X_op
== O_constant
8726 && imm_expr
.X_add_number
< 0
8727 && imm_expr
.X_unsigned
8731 /* For compatibility with older assemblers, we accept
8732 0x8000-0xffff as signed 16-bit numbers when only
8733 signed numbers are allowed. */
8735 minval
= 0, maxval
= 0xffff;
8737 minval
= -0x8000, maxval
= 0x7fff;
8739 minval
= -0x8000, maxval
= 0xffff;
8741 if (imm_expr
.X_op
!= O_constant
8742 || imm_expr
.X_add_number
< minval
8743 || imm_expr
.X_add_number
> maxval
)
8747 if (imm_expr
.X_op
== O_constant
8748 || imm_expr
.X_op
== O_big
)
8749 as_bad (_("expression out of range"));
8755 case 'o': /* 16 bit offset */
8756 /* Check whether there is only a single bracketed expression
8757 left. If so, it must be the base register and the
8758 constant must be zero. */
8759 if (*s
== '(' && strchr (s
+ 1, '(') == 0)
8761 offset_expr
.X_op
= O_constant
;
8762 offset_expr
.X_add_number
= 0;
8766 /* If this value won't fit into a 16 bit offset, then go
8767 find a macro that will generate the 32 bit offset
8769 if (my_getSmallExpression (&offset_expr
, offset_reloc
, s
) == 0
8770 && (offset_expr
.X_op
!= O_constant
8771 || offset_expr
.X_add_number
>= 0x8000
8772 || offset_expr
.X_add_number
< -0x8000))
8778 case 'p': /* pc relative offset */
8779 *offset_reloc
= BFD_RELOC_16_PCREL_S2
;
8780 my_getExpression (&offset_expr
, s
);
8784 case 'u': /* upper 16 bits */
8785 if (my_getSmallExpression (&imm_expr
, imm_reloc
, s
) == 0
8786 && imm_expr
.X_op
== O_constant
8787 && (imm_expr
.X_add_number
< 0
8788 || imm_expr
.X_add_number
>= 0x10000))
8789 as_bad (_("lui expression not in range 0..65535"));
8793 case 'a': /* 26 bit address */
8794 my_getExpression (&offset_expr
, s
);
8796 *offset_reloc
= BFD_RELOC_MIPS_JMP
;
8799 case 'N': /* 3 bit branch condition code */
8800 case 'M': /* 3 bit compare condition code */
8801 if (strncmp (s
, "$fcc", 4) != 0)
8811 while (ISDIGIT (*s
));
8813 as_bad (_("Invalid condition code register $fcc%d"), regno
);
8814 if ((strcmp(str
+ strlen(str
) - 3, ".ps") == 0
8815 || strcmp(str
+ strlen(str
) - 5, "any2f") == 0
8816 || strcmp(str
+ strlen(str
) - 5, "any2t") == 0)
8817 && (regno
& 1) != 0)
8818 as_warn(_("Condition code register should be even for %s, was %d"),
8820 if ((strcmp(str
+ strlen(str
) - 5, "any4f") == 0
8821 || strcmp(str
+ strlen(str
) - 5, "any4t") == 0)
8822 && (regno
& 3) != 0)
8823 as_warn(_("Condition code register should be 0 or 4 for %s, was %d"),
8826 INSERT_OPERAND (BCC
, *ip
, regno
);
8828 INSERT_OPERAND (CCC
, *ip
, regno
);
8832 if (s
[0] == '0' && (s
[1] == 'x' || s
[1] == 'X'))
8843 while (ISDIGIT (*s
));
8846 c
= 8; /* Invalid sel value. */
8849 as_bad (_("invalid coprocessor sub-selection value (0-7)"));
8850 ip
->insn_opcode
|= c
;
8854 /* Must be at least one digit. */
8855 my_getExpression (&imm_expr
, s
);
8856 check_absolute_expr (ip
, &imm_expr
);
8858 if ((unsigned long) imm_expr
.X_add_number
8859 > (unsigned long) OP_MASK_VECBYTE
)
8861 as_bad (_("bad byte vector index (%ld)"),
8862 (long) imm_expr
.X_add_number
);
8863 imm_expr
.X_add_number
= 0;
8866 INSERT_OPERAND (VECBYTE
, *ip
, imm_expr
.X_add_number
);
8867 imm_expr
.X_op
= O_absent
;
8872 my_getExpression (&imm_expr
, s
);
8873 check_absolute_expr (ip
, &imm_expr
);
8875 if ((unsigned long) imm_expr
.X_add_number
8876 > (unsigned long) OP_MASK_VECALIGN
)
8878 as_bad (_("bad byte vector index (%ld)"),
8879 (long) imm_expr
.X_add_number
);
8880 imm_expr
.X_add_number
= 0;
8883 INSERT_OPERAND (VECALIGN
, *ip
, imm_expr
.X_add_number
);
8884 imm_expr
.X_op
= O_absent
;
8889 as_bad (_("bad char = '%c'\n"), *args
);
8894 /* Args don't match. */
8895 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
8896 !strcmp (insn
->name
, insn
[1].name
))
8900 insn_error
= _("illegal operands");
8905 insn_error
= _("illegal operands");
8910 /* This routine assembles an instruction into its binary format when
8911 assembling for the mips16. As a side effect, it sets one of the
8912 global variables imm_reloc or offset_reloc to the type of
8913 relocation to do if one of the operands is an address expression.
8914 It also sets mips16_small and mips16_ext if the user explicitly
8915 requested a small or extended instruction. */
8918 mips16_ip (char *str
, struct mips_cl_insn
*ip
)
8922 struct mips_opcode
*insn
;
8925 unsigned int lastregno
= 0;
8931 mips16_small
= FALSE
;
8934 for (s
= str
; ISLOWER (*s
); ++s
)
8946 if (s
[1] == 't' && s
[2] == ' ')
8949 mips16_small
= TRUE
;
8953 else if (s
[1] == 'e' && s
[2] == ' ')
8962 insn_error
= _("unknown opcode");
8966 if (mips_opts
.noautoextend
&& ! mips16_ext
)
8967 mips16_small
= TRUE
;
8969 if ((insn
= (struct mips_opcode
*) hash_find (mips16_op_hash
, str
)) == NULL
)
8971 insn_error
= _("unrecognized opcode");
8978 assert (strcmp (insn
->name
, str
) == 0);
8980 create_insn (ip
, insn
);
8981 imm_expr
.X_op
= O_absent
;
8982 imm_reloc
[0] = BFD_RELOC_UNUSED
;
8983 imm_reloc
[1] = BFD_RELOC_UNUSED
;
8984 imm_reloc
[2] = BFD_RELOC_UNUSED
;
8985 imm2_expr
.X_op
= O_absent
;
8986 offset_expr
.X_op
= O_absent
;
8987 offset_reloc
[0] = BFD_RELOC_UNUSED
;
8988 offset_reloc
[1] = BFD_RELOC_UNUSED
;
8989 offset_reloc
[2] = BFD_RELOC_UNUSED
;
8990 for (args
= insn
->args
; 1; ++args
)
8997 /* In this switch statement we call break if we did not find
8998 a match, continue if we did find a match, or return if we
9007 /* Stuff the immediate value in now, if we can. */
9008 if (imm_expr
.X_op
== O_constant
9009 && *imm_reloc
> BFD_RELOC_UNUSED
9010 && insn
->pinfo
!= INSN_MACRO
)
9014 switch (*offset_reloc
)
9016 case BFD_RELOC_MIPS16_HI16_S
:
9017 tmp
= (imm_expr
.X_add_number
+ 0x8000) >> 16;
9020 case BFD_RELOC_MIPS16_HI16
:
9021 tmp
= imm_expr
.X_add_number
>> 16;
9024 case BFD_RELOC_MIPS16_LO16
:
9025 tmp
= ((imm_expr
.X_add_number
+ 0x8000) & 0xffff)
9029 case BFD_RELOC_UNUSED
:
9030 tmp
= imm_expr
.X_add_number
;
9036 *offset_reloc
= BFD_RELOC_UNUSED
;
9038 mips16_immed (NULL
, 0, *imm_reloc
- BFD_RELOC_UNUSED
,
9039 tmp
, TRUE
, mips16_small
,
9040 mips16_ext
, &ip
->insn_opcode
,
9041 &ip
->use_extend
, &ip
->extend
);
9042 imm_expr
.X_op
= O_absent
;
9043 *imm_reloc
= BFD_RELOC_UNUSED
;
9057 MIPS16_INSERT_OPERAND (RX
, *ip
, lastregno
);
9060 MIPS16_INSERT_OPERAND (RY
, *ip
, lastregno
);
9076 MIPS16_INSERT_OPERAND (RX
, *ip
, lastregno
);
9078 MIPS16_INSERT_OPERAND (RY
, *ip
, lastregno
);
9105 while (ISDIGIT (*s
));
9108 as_bad (_("invalid register number (%d)"), regno
);
9114 if (s
[1] == 'r' && s
[2] == 'a')
9119 else if (s
[1] == 'f' && s
[2] == 'p')
9124 else if (s
[1] == 's' && s
[2] == 'p')
9129 else if (s
[1] == 'g' && s
[2] == 'p')
9134 else if (s
[1] == 'a' && s
[2] == 't')
9139 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '0')
9144 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '1')
9149 else if (s
[1] == 'z' && s
[2] == 'e' && s
[3] == 'r' && s
[4] == 'o')
9162 if (c
== 'v' || c
== 'w')
9164 regno
= mips16_to_32_reg_map
[lastregno
];
9178 regno
= mips32_to_16_reg_map
[regno
];
9183 regno
= ILLEGAL_REG
;
9188 regno
= ILLEGAL_REG
;
9193 regno
= ILLEGAL_REG
;
9198 if (regno
== AT
&& ! mips_opts
.noat
)
9199 as_warn (_("used $at without \".set noat\""));
9206 if (regno
== ILLEGAL_REG
)
9213 MIPS16_INSERT_OPERAND (RX
, *ip
, regno
);
9217 MIPS16_INSERT_OPERAND (RY
, *ip
, regno
);
9220 MIPS16_INSERT_OPERAND (RZ
, *ip
, regno
);
9223 MIPS16_INSERT_OPERAND (MOVE32Z
, *ip
, regno
);
9229 MIPS16_INSERT_OPERAND (REGR32
, *ip
, regno
);
9232 regno
= ((regno
& 7) << 2) | ((regno
& 0x18) >> 3);
9233 MIPS16_INSERT_OPERAND (REG32R
, *ip
, regno
);
9243 if (strncmp (s
, "$pc", 3) == 0)
9260 i
= my_getSmallExpression (&imm_expr
, imm_reloc
, s
);
9263 if (imm_expr
.X_op
!= O_constant
)
9266 ip
->use_extend
= TRUE
;
9271 /* We need to relax this instruction. */
9272 *offset_reloc
= *imm_reloc
;
9273 *imm_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
9278 *imm_reloc
= BFD_RELOC_UNUSED
;
9286 my_getExpression (&imm_expr
, s
);
9287 if (imm_expr
.X_op
== O_register
)
9289 /* What we thought was an expression turned out to
9292 if (s
[0] == '(' && args
[1] == '(')
9294 /* It looks like the expression was omitted
9295 before a register indirection, which means
9296 that the expression is implicitly zero. We
9297 still set up imm_expr, so that we handle
9298 explicit extensions correctly. */
9299 imm_expr
.X_op
= O_constant
;
9300 imm_expr
.X_add_number
= 0;
9301 *imm_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
9308 /* We need to relax this instruction. */
9309 *imm_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
9318 /* We use offset_reloc rather than imm_reloc for the PC
9319 relative operands. This lets macros with both
9320 immediate and address operands work correctly. */
9321 my_getExpression (&offset_expr
, s
);
9323 if (offset_expr
.X_op
== O_register
)
9326 /* We need to relax this instruction. */
9327 *offset_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
9331 case '6': /* break code */
9332 my_getExpression (&imm_expr
, s
);
9333 check_absolute_expr (ip
, &imm_expr
);
9334 if ((unsigned long) imm_expr
.X_add_number
> 63)
9335 as_warn (_("Invalid value for `%s' (%lu)"),
9337 (unsigned long) imm_expr
.X_add_number
);
9338 MIPS16_INSERT_OPERAND (IMM6
, *ip
, imm_expr
.X_add_number
);
9339 imm_expr
.X_op
= O_absent
;
9343 case 'a': /* 26 bit address */
9344 my_getExpression (&offset_expr
, s
);
9346 *offset_reloc
= BFD_RELOC_MIPS16_JMP
;
9347 ip
->insn_opcode
<<= 16;
9350 case 'l': /* register list for entry macro */
9351 case 'L': /* register list for exit macro */
9361 int freg
, reg1
, reg2
;
9363 while (*s
== ' ' || *s
== ',')
9367 as_bad (_("can't parse register list"));
9379 while (ISDIGIT (*s
))
9401 as_bad (_("invalid register list"));
9406 while (ISDIGIT (*s
))
9413 if (freg
&& reg1
== 0 && reg2
== 0 && c
== 'L')
9418 else if (freg
&& reg1
== 0 && reg2
== 1 && c
== 'L')
9423 else if (reg1
== 4 && reg2
>= 4 && reg2
<= 7 && c
!= 'L')
9424 mask
|= (reg2
- 3) << 3;
9425 else if (reg1
== 16 && reg2
>= 16 && reg2
<= 17)
9426 mask
|= (reg2
- 15) << 1;
9427 else if (reg1
== RA
&& reg2
== RA
)
9431 as_bad (_("invalid register list"));
9435 /* The mask is filled in in the opcode table for the
9436 benefit of the disassembler. We remove it before
9437 applying the actual mask. */
9438 ip
->insn_opcode
&= ~ ((7 << 3) << MIPS16OP_SH_IMM6
);
9439 ip
->insn_opcode
|= mask
<< MIPS16OP_SH_IMM6
;
9443 case 'e': /* extend code */
9444 my_getExpression (&imm_expr
, s
);
9445 check_absolute_expr (ip
, &imm_expr
);
9446 if ((unsigned long) imm_expr
.X_add_number
> 0x7ff)
9448 as_warn (_("Invalid value for `%s' (%lu)"),
9450 (unsigned long) imm_expr
.X_add_number
);
9451 imm_expr
.X_add_number
&= 0x7ff;
9453 ip
->insn_opcode
|= imm_expr
.X_add_number
;
9454 imm_expr
.X_op
= O_absent
;
9464 /* Args don't match. */
9465 if (insn
+ 1 < &mips16_opcodes
[bfd_mips16_num_opcodes
] &&
9466 strcmp (insn
->name
, insn
[1].name
) == 0)
9473 insn_error
= _("illegal operands");
9479 /* This structure holds information we know about a mips16 immediate
9482 struct mips16_immed_operand
9484 /* The type code used in the argument string in the opcode table. */
9486 /* The number of bits in the short form of the opcode. */
9488 /* The number of bits in the extended form of the opcode. */
9490 /* The amount by which the short form is shifted when it is used;
9491 for example, the sw instruction has a shift count of 2. */
9493 /* The amount by which the short form is shifted when it is stored
9494 into the instruction code. */
9496 /* Non-zero if the short form is unsigned. */
9498 /* Non-zero if the extended form is unsigned. */
9500 /* Non-zero if the value is PC relative. */
9504 /* The mips16 immediate operand types. */
9506 static const struct mips16_immed_operand mips16_immed_operands
[] =
9508 { '<', 3, 5, 0, MIPS16OP_SH_RZ
, 1, 1, 0 },
9509 { '>', 3, 5, 0, MIPS16OP_SH_RX
, 1, 1, 0 },
9510 { '[', 3, 6, 0, MIPS16OP_SH_RZ
, 1, 1, 0 },
9511 { ']', 3, 6, 0, MIPS16OP_SH_RX
, 1, 1, 0 },
9512 { '4', 4, 15, 0, MIPS16OP_SH_IMM4
, 0, 0, 0 },
9513 { '5', 5, 16, 0, MIPS16OP_SH_IMM5
, 1, 0, 0 },
9514 { 'H', 5, 16, 1, MIPS16OP_SH_IMM5
, 1, 0, 0 },
9515 { 'W', 5, 16, 2, MIPS16OP_SH_IMM5
, 1, 0, 0 },
9516 { 'D', 5, 16, 3, MIPS16OP_SH_IMM5
, 1, 0, 0 },
9517 { 'j', 5, 16, 0, MIPS16OP_SH_IMM5
, 0, 0, 0 },
9518 { '8', 8, 16, 0, MIPS16OP_SH_IMM8
, 1, 0, 0 },
9519 { 'V', 8, 16, 2, MIPS16OP_SH_IMM8
, 1, 0, 0 },
9520 { 'C', 8, 16, 3, MIPS16OP_SH_IMM8
, 1, 0, 0 },
9521 { 'U', 8, 16, 0, MIPS16OP_SH_IMM8
, 1, 1, 0 },
9522 { 'k', 8, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 0 },
9523 { 'K', 8, 16, 3, MIPS16OP_SH_IMM8
, 0, 0, 0 },
9524 { 'p', 8, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 1 },
9525 { 'q', 11, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 1 },
9526 { 'A', 8, 16, 2, MIPS16OP_SH_IMM8
, 1, 0, 1 },
9527 { 'B', 5, 16, 3, MIPS16OP_SH_IMM5
, 1, 0, 1 },
9528 { 'E', 5, 16, 2, MIPS16OP_SH_IMM5
, 1, 0, 1 }
9531 #define MIPS16_NUM_IMMED \
9532 (sizeof mips16_immed_operands / sizeof mips16_immed_operands[0])
9534 /* Handle a mips16 instruction with an immediate value. This or's the
9535 small immediate value into *INSN. It sets *USE_EXTEND to indicate
9536 whether an extended value is needed; if one is needed, it sets
9537 *EXTEND to the value. The argument type is TYPE. The value is VAL.
9538 If SMALL is true, an unextended opcode was explicitly requested.
9539 If EXT is true, an extended opcode was explicitly requested. If
9540 WARN is true, warn if EXT does not match reality. */
9543 mips16_immed (char *file
, unsigned int line
, int type
, offsetT val
,
9544 bfd_boolean warn
, bfd_boolean small
, bfd_boolean ext
,
9545 unsigned long *insn
, bfd_boolean
*use_extend
,
9546 unsigned short *extend
)
9548 register const struct mips16_immed_operand
*op
;
9549 int mintiny
, maxtiny
;
9550 bfd_boolean needext
;
9552 op
= mips16_immed_operands
;
9553 while (op
->type
!= type
)
9556 assert (op
< mips16_immed_operands
+ MIPS16_NUM_IMMED
);
9561 if (type
== '<' || type
== '>' || type
== '[' || type
== ']')
9564 maxtiny
= 1 << op
->nbits
;
9569 maxtiny
= (1 << op
->nbits
) - 1;
9574 mintiny
= - (1 << (op
->nbits
- 1));
9575 maxtiny
= (1 << (op
->nbits
- 1)) - 1;
9578 /* Branch offsets have an implicit 0 in the lowest bit. */
9579 if (type
== 'p' || type
== 'q')
9582 if ((val
& ((1 << op
->shift
) - 1)) != 0
9583 || val
< (mintiny
<< op
->shift
)
9584 || val
> (maxtiny
<< op
->shift
))
9589 if (warn
&& ext
&& ! needext
)
9590 as_warn_where (file
, line
,
9591 _("extended operand requested but not required"));
9592 if (small
&& needext
)
9593 as_bad_where (file
, line
, _("invalid unextended operand value"));
9595 if (small
|| (! ext
&& ! needext
))
9599 *use_extend
= FALSE
;
9600 insnval
= ((val
>> op
->shift
) & ((1 << op
->nbits
) - 1));
9601 insnval
<<= op
->op_shift
;
9606 long minext
, maxext
;
9612 maxext
= (1 << op
->extbits
) - 1;
9616 minext
= - (1 << (op
->extbits
- 1));
9617 maxext
= (1 << (op
->extbits
- 1)) - 1;
9619 if (val
< minext
|| val
> maxext
)
9620 as_bad_where (file
, line
,
9621 _("operand value out of range for instruction"));
9624 if (op
->extbits
== 16)
9626 extval
= ((val
>> 11) & 0x1f) | (val
& 0x7e0);
9629 else if (op
->extbits
== 15)
9631 extval
= ((val
>> 11) & 0xf) | (val
& 0x7f0);
9636 extval
= ((val
& 0x1f) << 6) | (val
& 0x20);
9640 *extend
= (unsigned short) extval
;
9645 struct percent_op_match
9648 bfd_reloc_code_real_type reloc
;
9651 static const struct percent_op_match mips_percent_op
[] =
9653 {"%lo", BFD_RELOC_LO16
},
9655 {"%call_hi", BFD_RELOC_MIPS_CALL_HI16
},
9656 {"%call_lo", BFD_RELOC_MIPS_CALL_LO16
},
9657 {"%call16", BFD_RELOC_MIPS_CALL16
},
9658 {"%got_disp", BFD_RELOC_MIPS_GOT_DISP
},
9659 {"%got_page", BFD_RELOC_MIPS_GOT_PAGE
},
9660 {"%got_ofst", BFD_RELOC_MIPS_GOT_OFST
},
9661 {"%got_hi", BFD_RELOC_MIPS_GOT_HI16
},
9662 {"%got_lo", BFD_RELOC_MIPS_GOT_LO16
},
9663 {"%got", BFD_RELOC_MIPS_GOT16
},
9664 {"%gp_rel", BFD_RELOC_GPREL16
},
9665 {"%half", BFD_RELOC_16
},
9666 {"%highest", BFD_RELOC_MIPS_HIGHEST
},
9667 {"%higher", BFD_RELOC_MIPS_HIGHER
},
9668 {"%neg", BFD_RELOC_MIPS_SUB
},
9669 {"%tlsgd", BFD_RELOC_MIPS_TLS_GD
},
9670 {"%tlsldm", BFD_RELOC_MIPS_TLS_LDM
},
9671 {"%dtprel_hi", BFD_RELOC_MIPS_TLS_DTPREL_HI16
},
9672 {"%dtprel_lo", BFD_RELOC_MIPS_TLS_DTPREL_LO16
},
9673 {"%tprel_hi", BFD_RELOC_MIPS_TLS_TPREL_HI16
},
9674 {"%tprel_lo", BFD_RELOC_MIPS_TLS_TPREL_LO16
},
9675 {"%gottprel", BFD_RELOC_MIPS_TLS_GOTTPREL
},
9677 {"%hi", BFD_RELOC_HI16_S
}
9680 static const struct percent_op_match mips16_percent_op
[] =
9682 {"%lo", BFD_RELOC_MIPS16_LO16
},
9683 {"%gprel", BFD_RELOC_MIPS16_GPREL
},
9684 {"%hi", BFD_RELOC_MIPS16_HI16_S
}
9688 /* Return true if *STR points to a relocation operator. When returning true,
9689 move *STR over the operator and store its relocation code in *RELOC.
9690 Leave both *STR and *RELOC alone when returning false. */
9693 parse_relocation (char **str
, bfd_reloc_code_real_type
*reloc
)
9695 const struct percent_op_match
*percent_op
;
9698 if (mips_opts
.mips16
)
9700 percent_op
= mips16_percent_op
;
9701 limit
= ARRAY_SIZE (mips16_percent_op
);
9705 percent_op
= mips_percent_op
;
9706 limit
= ARRAY_SIZE (mips_percent_op
);
9709 for (i
= 0; i
< limit
; i
++)
9710 if (strncasecmp (*str
, percent_op
[i
].str
, strlen (percent_op
[i
].str
)) == 0)
9712 int len
= strlen (percent_op
[i
].str
);
9714 if (!ISSPACE ((*str
)[len
]) && (*str
)[len
] != '(')
9717 *str
+= strlen (percent_op
[i
].str
);
9718 *reloc
= percent_op
[i
].reloc
;
9720 /* Check whether the output BFD supports this relocation.
9721 If not, issue an error and fall back on something safe. */
9722 if (!bfd_reloc_type_lookup (stdoutput
, percent_op
[i
].reloc
))
9724 as_bad ("relocation %s isn't supported by the current ABI",
9726 *reloc
= BFD_RELOC_UNUSED
;
9734 /* Parse string STR as a 16-bit relocatable operand. Store the
9735 expression in *EP and the relocations in the array starting
9736 at RELOC. Return the number of relocation operators used.
9738 On exit, EXPR_END points to the first character after the expression. */
9741 my_getSmallExpression (expressionS
*ep
, bfd_reloc_code_real_type
*reloc
,
9744 bfd_reloc_code_real_type reversed_reloc
[3];
9745 size_t reloc_index
, i
;
9746 int crux_depth
, str_depth
;
9749 /* Search for the start of the main expression, recoding relocations
9750 in REVERSED_RELOC. End the loop with CRUX pointing to the start
9751 of the main expression and with CRUX_DEPTH containing the number
9752 of open brackets at that point. */
9759 crux_depth
= str_depth
;
9761 /* Skip over whitespace and brackets, keeping count of the number
9763 while (*str
== ' ' || *str
== '\t' || *str
== '(')
9768 && reloc_index
< (HAVE_NEWABI
? 3 : 1)
9769 && parse_relocation (&str
, &reversed_reloc
[reloc_index
]));
9771 my_getExpression (ep
, crux
);
9774 /* Match every open bracket. */
9775 while (crux_depth
> 0 && (*str
== ')' || *str
== ' ' || *str
== '\t'))
9780 as_bad ("unclosed '('");
9784 if (reloc_index
!= 0)
9786 prev_reloc_op_frag
= frag_now
;
9787 for (i
= 0; i
< reloc_index
; i
++)
9788 reloc
[i
] = reversed_reloc
[reloc_index
- 1 - i
];
9795 my_getExpression (expressionS
*ep
, char *str
)
9800 save_in
= input_line_pointer
;
9801 input_line_pointer
= str
;
9803 expr_end
= input_line_pointer
;
9804 input_line_pointer
= save_in
;
9806 /* If we are in mips16 mode, and this is an expression based on `.',
9807 then we bump the value of the symbol by 1 since that is how other
9808 text symbols are handled. We don't bother to handle complex
9809 expressions, just `.' plus or minus a constant. */
9810 if (mips_opts
.mips16
9811 && ep
->X_op
== O_symbol
9812 && strcmp (S_GET_NAME (ep
->X_add_symbol
), FAKE_LABEL_NAME
) == 0
9813 && S_GET_SEGMENT (ep
->X_add_symbol
) == now_seg
9814 && symbol_get_frag (ep
->X_add_symbol
) == frag_now
9815 && symbol_constant_p (ep
->X_add_symbol
)
9816 && (val
= S_GET_VALUE (ep
->X_add_symbol
)) == frag_now_fix ())
9817 S_SET_VALUE (ep
->X_add_symbol
, val
+ 1);
9820 /* Turn a string in input_line_pointer into a floating point constant
9821 of type TYPE, and store the appropriate bytes in *LITP. The number
9822 of LITTLENUMS emitted is stored in *SIZEP. An error message is
9823 returned, or NULL on OK. */
9826 md_atof (int type
, char *litP
, int *sizeP
)
9829 LITTLENUM_TYPE words
[4];
9845 return _("bad call to md_atof");
9848 t
= atof_ieee (input_line_pointer
, type
, words
);
9850 input_line_pointer
= t
;
9854 if (! target_big_endian
)
9856 for (i
= prec
- 1; i
>= 0; i
--)
9858 md_number_to_chars (litP
, words
[i
], 2);
9864 for (i
= 0; i
< prec
; i
++)
9866 md_number_to_chars (litP
, words
[i
], 2);
9875 md_number_to_chars (char *buf
, valueT val
, int n
)
9877 if (target_big_endian
)
9878 number_to_chars_bigendian (buf
, val
, n
);
9880 number_to_chars_littleendian (buf
, val
, n
);
9884 static int support_64bit_objects(void)
9886 const char **list
, **l
;
9889 list
= bfd_target_list ();
9890 for (l
= list
; *l
!= NULL
; l
++)
9892 /* This is traditional mips */
9893 if (strcmp (*l
, "elf64-tradbigmips") == 0
9894 || strcmp (*l
, "elf64-tradlittlemips") == 0)
9896 if (strcmp (*l
, "elf64-bigmips") == 0
9897 || strcmp (*l
, "elf64-littlemips") == 0)
9904 #endif /* OBJ_ELF */
9906 const char *md_shortopts
= "O::g::G:";
9908 struct option md_longopts
[] =
9910 /* Options which specify architecture. */
9911 #define OPTION_ARCH_BASE (OPTION_MD_BASE)
9912 #define OPTION_MARCH (OPTION_ARCH_BASE + 0)
9913 {"march", required_argument
, NULL
, OPTION_MARCH
},
9914 #define OPTION_MTUNE (OPTION_ARCH_BASE + 1)
9915 {"mtune", required_argument
, NULL
, OPTION_MTUNE
},
9916 #define OPTION_MIPS1 (OPTION_ARCH_BASE + 2)
9917 {"mips0", no_argument
, NULL
, OPTION_MIPS1
},
9918 {"mips1", no_argument
, NULL
, OPTION_MIPS1
},
9919 #define OPTION_MIPS2 (OPTION_ARCH_BASE + 3)
9920 {"mips2", no_argument
, NULL
, OPTION_MIPS2
},
9921 #define OPTION_MIPS3 (OPTION_ARCH_BASE + 4)
9922 {"mips3", no_argument
, NULL
, OPTION_MIPS3
},
9923 #define OPTION_MIPS4 (OPTION_ARCH_BASE + 5)
9924 {"mips4", no_argument
, NULL
, OPTION_MIPS4
},
9925 #define OPTION_MIPS5 (OPTION_ARCH_BASE + 6)
9926 {"mips5", no_argument
, NULL
, OPTION_MIPS5
},
9927 #define OPTION_MIPS32 (OPTION_ARCH_BASE + 7)
9928 {"mips32", no_argument
, NULL
, OPTION_MIPS32
},
9929 #define OPTION_MIPS64 (OPTION_ARCH_BASE + 8)
9930 {"mips64", no_argument
, NULL
, OPTION_MIPS64
},
9931 #define OPTION_MIPS32R2 (OPTION_ARCH_BASE + 9)
9932 {"mips32r2", no_argument
, NULL
, OPTION_MIPS32R2
},
9933 #define OPTION_MIPS64R2 (OPTION_ARCH_BASE + 10)
9934 {"mips64r2", no_argument
, NULL
, OPTION_MIPS64R2
},
9936 /* Options which specify Application Specific Extensions (ASEs). */
9937 #define OPTION_ASE_BASE (OPTION_ARCH_BASE + 11)
9938 #define OPTION_MIPS16 (OPTION_ASE_BASE + 0)
9939 {"mips16", no_argument
, NULL
, OPTION_MIPS16
},
9940 #define OPTION_NO_MIPS16 (OPTION_ASE_BASE + 1)
9941 {"no-mips16", no_argument
, NULL
, OPTION_NO_MIPS16
},
9942 #define OPTION_MIPS3D (OPTION_ASE_BASE + 2)
9943 {"mips3d", no_argument
, NULL
, OPTION_MIPS3D
},
9944 #define OPTION_NO_MIPS3D (OPTION_ASE_BASE + 3)
9945 {"no-mips3d", no_argument
, NULL
, OPTION_NO_MIPS3D
},
9946 #define OPTION_MDMX (OPTION_ASE_BASE + 4)
9947 {"mdmx", no_argument
, NULL
, OPTION_MDMX
},
9948 #define OPTION_NO_MDMX (OPTION_ASE_BASE + 5)
9949 {"no-mdmx", no_argument
, NULL
, OPTION_NO_MDMX
},
9951 /* Old-style architecture options. Don't add more of these. */
9952 #define OPTION_COMPAT_ARCH_BASE (OPTION_ASE_BASE + 6)
9953 #define OPTION_M4650 (OPTION_COMPAT_ARCH_BASE + 0)
9954 {"m4650", no_argument
, NULL
, OPTION_M4650
},
9955 #define OPTION_NO_M4650 (OPTION_COMPAT_ARCH_BASE + 1)
9956 {"no-m4650", no_argument
, NULL
, OPTION_NO_M4650
},
9957 #define OPTION_M4010 (OPTION_COMPAT_ARCH_BASE + 2)
9958 {"m4010", no_argument
, NULL
, OPTION_M4010
},
9959 #define OPTION_NO_M4010 (OPTION_COMPAT_ARCH_BASE + 3)
9960 {"no-m4010", no_argument
, NULL
, OPTION_NO_M4010
},
9961 #define OPTION_M4100 (OPTION_COMPAT_ARCH_BASE + 4)
9962 {"m4100", no_argument
, NULL
, OPTION_M4100
},
9963 #define OPTION_NO_M4100 (OPTION_COMPAT_ARCH_BASE + 5)
9964 {"no-m4100", no_argument
, NULL
, OPTION_NO_M4100
},
9965 #define OPTION_M3900 (OPTION_COMPAT_ARCH_BASE + 6)
9966 {"m3900", no_argument
, NULL
, OPTION_M3900
},
9967 #define OPTION_NO_M3900 (OPTION_COMPAT_ARCH_BASE + 7)
9968 {"no-m3900", no_argument
, NULL
, OPTION_NO_M3900
},
9970 /* Options which enable bug fixes. */
9971 #define OPTION_FIX_BASE (OPTION_COMPAT_ARCH_BASE + 8)
9972 #define OPTION_M7000_HILO_FIX (OPTION_FIX_BASE + 0)
9973 {"mfix7000", no_argument
, NULL
, OPTION_M7000_HILO_FIX
},
9974 #define OPTION_MNO_7000_HILO_FIX (OPTION_FIX_BASE + 1)
9975 {"no-fix-7000", no_argument
, NULL
, OPTION_MNO_7000_HILO_FIX
},
9976 {"mno-fix7000", no_argument
, NULL
, OPTION_MNO_7000_HILO_FIX
},
9977 #define OPTION_FIX_VR4120 (OPTION_FIX_BASE + 2)
9978 #define OPTION_NO_FIX_VR4120 (OPTION_FIX_BASE + 3)
9979 {"mfix-vr4120", no_argument
, NULL
, OPTION_FIX_VR4120
},
9980 {"mno-fix-vr4120", no_argument
, NULL
, OPTION_NO_FIX_VR4120
},
9982 /* Miscellaneous options. */
9983 #define OPTION_MISC_BASE (OPTION_FIX_BASE + 4)
9984 #define OPTION_TRAP (OPTION_MISC_BASE + 0)
9985 {"trap", no_argument
, NULL
, OPTION_TRAP
},
9986 {"no-break", no_argument
, NULL
, OPTION_TRAP
},
9987 #define OPTION_BREAK (OPTION_MISC_BASE + 1)
9988 {"break", no_argument
, NULL
, OPTION_BREAK
},
9989 {"no-trap", no_argument
, NULL
, OPTION_BREAK
},
9990 #define OPTION_EB (OPTION_MISC_BASE + 2)
9991 {"EB", no_argument
, NULL
, OPTION_EB
},
9992 #define OPTION_EL (OPTION_MISC_BASE + 3)
9993 {"EL", no_argument
, NULL
, OPTION_EL
},
9994 #define OPTION_FP32 (OPTION_MISC_BASE + 4)
9995 {"mfp32", no_argument
, NULL
, OPTION_FP32
},
9996 #define OPTION_GP32 (OPTION_MISC_BASE + 5)
9997 {"mgp32", no_argument
, NULL
, OPTION_GP32
},
9998 #define OPTION_CONSTRUCT_FLOATS (OPTION_MISC_BASE + 6)
9999 {"construct-floats", no_argument
, NULL
, OPTION_CONSTRUCT_FLOATS
},
10000 #define OPTION_NO_CONSTRUCT_FLOATS (OPTION_MISC_BASE + 7)
10001 {"no-construct-floats", no_argument
, NULL
, OPTION_NO_CONSTRUCT_FLOATS
},
10002 #define OPTION_FP64 (OPTION_MISC_BASE + 8)
10003 {"mfp64", no_argument
, NULL
, OPTION_FP64
},
10004 #define OPTION_GP64 (OPTION_MISC_BASE + 9)
10005 {"mgp64", no_argument
, NULL
, OPTION_GP64
},
10006 #define OPTION_RELAX_BRANCH (OPTION_MISC_BASE + 10)
10007 #define OPTION_NO_RELAX_BRANCH (OPTION_MISC_BASE + 11)
10008 {"relax-branch", no_argument
, NULL
, OPTION_RELAX_BRANCH
},
10009 {"no-relax-branch", no_argument
, NULL
, OPTION_NO_RELAX_BRANCH
},
10010 #define OPTION_MSHARED (OPTION_MISC_BASE + 12)
10011 #define OPTION_MNO_SHARED (OPTION_MISC_BASE + 13)
10012 {"mshared", no_argument
, NULL
, OPTION_MSHARED
},
10013 {"mno-shared", no_argument
, NULL
, OPTION_MNO_SHARED
},
10014 #define OPTION_MSYM32 (OPTION_MISC_BASE + 14)
10015 #define OPTION_MNO_SYM32 (OPTION_MISC_BASE + 15)
10016 {"msym32", no_argument
, NULL
, OPTION_MSYM32
},
10017 {"mno-sym32", no_argument
, NULL
, OPTION_MNO_SYM32
},
10019 /* ELF-specific options. */
10021 #define OPTION_ELF_BASE (OPTION_MISC_BASE + 16)
10022 #define OPTION_CALL_SHARED (OPTION_ELF_BASE + 0)
10023 {"KPIC", no_argument
, NULL
, OPTION_CALL_SHARED
},
10024 {"call_shared", no_argument
, NULL
, OPTION_CALL_SHARED
},
10025 #define OPTION_NON_SHARED (OPTION_ELF_BASE + 1)
10026 {"non_shared", no_argument
, NULL
, OPTION_NON_SHARED
},
10027 #define OPTION_XGOT (OPTION_ELF_BASE + 2)
10028 {"xgot", no_argument
, NULL
, OPTION_XGOT
},
10029 #define OPTION_MABI (OPTION_ELF_BASE + 3)
10030 {"mabi", required_argument
, NULL
, OPTION_MABI
},
10031 #define OPTION_32 (OPTION_ELF_BASE + 4)
10032 {"32", no_argument
, NULL
, OPTION_32
},
10033 #define OPTION_N32 (OPTION_ELF_BASE + 5)
10034 {"n32", no_argument
, NULL
, OPTION_N32
},
10035 #define OPTION_64 (OPTION_ELF_BASE + 6)
10036 {"64", no_argument
, NULL
, OPTION_64
},
10037 #define OPTION_MDEBUG (OPTION_ELF_BASE + 7)
10038 {"mdebug", no_argument
, NULL
, OPTION_MDEBUG
},
10039 #define OPTION_NO_MDEBUG (OPTION_ELF_BASE + 8)
10040 {"no-mdebug", no_argument
, NULL
, OPTION_NO_MDEBUG
},
10041 #define OPTION_PDR (OPTION_ELF_BASE + 9)
10042 {"mpdr", no_argument
, NULL
, OPTION_PDR
},
10043 #define OPTION_NO_PDR (OPTION_ELF_BASE + 10)
10044 {"mno-pdr", no_argument
, NULL
, OPTION_NO_PDR
},
10045 #endif /* OBJ_ELF */
10047 {NULL
, no_argument
, NULL
, 0}
10049 size_t md_longopts_size
= sizeof (md_longopts
);
10051 /* Set STRING_PTR (either &mips_arch_string or &mips_tune_string) to
10052 NEW_VALUE. Warn if another value was already specified. Note:
10053 we have to defer parsing the -march and -mtune arguments in order
10054 to handle 'from-abi' correctly, since the ABI might be specified
10055 in a later argument. */
10058 mips_set_option_string (const char **string_ptr
, const char *new_value
)
10060 if (*string_ptr
!= 0 && strcasecmp (*string_ptr
, new_value
) != 0)
10061 as_warn (_("A different %s was already specified, is now %s"),
10062 string_ptr
== &mips_arch_string
? "-march" : "-mtune",
10065 *string_ptr
= new_value
;
10069 md_parse_option (int c
, char *arg
)
10073 case OPTION_CONSTRUCT_FLOATS
:
10074 mips_disable_float_construction
= 0;
10077 case OPTION_NO_CONSTRUCT_FLOATS
:
10078 mips_disable_float_construction
= 1;
10090 target_big_endian
= 1;
10094 target_big_endian
= 0;
10098 if (arg
&& arg
[1] == '0')
10108 mips_debug
= atoi (arg
);
10109 /* When the MIPS assembler sees -g or -g2, it does not do
10110 optimizations which limit full symbolic debugging. We take
10111 that to be equivalent to -O0. */
10112 if (mips_debug
== 2)
10117 file_mips_isa
= ISA_MIPS1
;
10121 file_mips_isa
= ISA_MIPS2
;
10125 file_mips_isa
= ISA_MIPS3
;
10129 file_mips_isa
= ISA_MIPS4
;
10133 file_mips_isa
= ISA_MIPS5
;
10136 case OPTION_MIPS32
:
10137 file_mips_isa
= ISA_MIPS32
;
10140 case OPTION_MIPS32R2
:
10141 file_mips_isa
= ISA_MIPS32R2
;
10144 case OPTION_MIPS64R2
:
10145 file_mips_isa
= ISA_MIPS64R2
;
10148 case OPTION_MIPS64
:
10149 file_mips_isa
= ISA_MIPS64
;
10153 mips_set_option_string (&mips_tune_string
, arg
);
10157 mips_set_option_string (&mips_arch_string
, arg
);
10161 mips_set_option_string (&mips_arch_string
, "4650");
10162 mips_set_option_string (&mips_tune_string
, "4650");
10165 case OPTION_NO_M4650
:
10169 mips_set_option_string (&mips_arch_string
, "4010");
10170 mips_set_option_string (&mips_tune_string
, "4010");
10173 case OPTION_NO_M4010
:
10177 mips_set_option_string (&mips_arch_string
, "4100");
10178 mips_set_option_string (&mips_tune_string
, "4100");
10181 case OPTION_NO_M4100
:
10185 mips_set_option_string (&mips_arch_string
, "3900");
10186 mips_set_option_string (&mips_tune_string
, "3900");
10189 case OPTION_NO_M3900
:
10193 mips_opts
.ase_mdmx
= 1;
10196 case OPTION_NO_MDMX
:
10197 mips_opts
.ase_mdmx
= 0;
10200 case OPTION_MIPS16
:
10201 mips_opts
.mips16
= 1;
10202 mips_no_prev_insn (FALSE
);
10205 case OPTION_NO_MIPS16
:
10206 mips_opts
.mips16
= 0;
10207 mips_no_prev_insn (FALSE
);
10210 case OPTION_MIPS3D
:
10211 mips_opts
.ase_mips3d
= 1;
10214 case OPTION_NO_MIPS3D
:
10215 mips_opts
.ase_mips3d
= 0;
10218 case OPTION_FIX_VR4120
:
10219 mips_fix_vr4120
= 1;
10222 case OPTION_NO_FIX_VR4120
:
10223 mips_fix_vr4120
= 0;
10226 case OPTION_RELAX_BRANCH
:
10227 mips_relax_branch
= 1;
10230 case OPTION_NO_RELAX_BRANCH
:
10231 mips_relax_branch
= 0;
10234 case OPTION_MSHARED
:
10235 mips_in_shared
= TRUE
;
10238 case OPTION_MNO_SHARED
:
10239 mips_in_shared
= FALSE
;
10242 case OPTION_MSYM32
:
10243 mips_opts
.sym32
= TRUE
;
10246 case OPTION_MNO_SYM32
:
10247 mips_opts
.sym32
= FALSE
;
10251 /* When generating ELF code, we permit -KPIC and -call_shared to
10252 select SVR4_PIC, and -non_shared to select no PIC. This is
10253 intended to be compatible with Irix 5. */
10254 case OPTION_CALL_SHARED
:
10255 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
10257 as_bad (_("-call_shared is supported only for ELF format"));
10260 mips_pic
= SVR4_PIC
;
10261 mips_abicalls
= TRUE
;
10262 if (g_switch_seen
&& g_switch_value
!= 0)
10264 as_bad (_("-G may not be used with SVR4 PIC code"));
10267 g_switch_value
= 0;
10270 case OPTION_NON_SHARED
:
10271 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
10273 as_bad (_("-non_shared is supported only for ELF format"));
10277 mips_abicalls
= FALSE
;
10280 /* The -xgot option tells the assembler to use 32 offsets when
10281 accessing the got in SVR4_PIC mode. It is for Irix
10286 #endif /* OBJ_ELF */
10289 g_switch_value
= atoi (arg
);
10291 if (mips_pic
== SVR4_PIC
&& g_switch_value
!= 0)
10293 as_bad (_("-G may not be used with SVR4 PIC code"));
10299 /* The -32, -n32 and -64 options are shortcuts for -mabi=32, -mabi=n32
10302 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
10304 as_bad (_("-32 is supported for ELF format only"));
10307 mips_abi
= O32_ABI
;
10311 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
10313 as_bad (_("-n32 is supported for ELF format only"));
10316 mips_abi
= N32_ABI
;
10320 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
10322 as_bad (_("-64 is supported for ELF format only"));
10325 mips_abi
= N64_ABI
;
10326 if (! support_64bit_objects())
10327 as_fatal (_("No compiled in support for 64 bit object file format"));
10329 #endif /* OBJ_ELF */
10332 file_mips_gp32
= 1;
10336 file_mips_gp32
= 0;
10340 file_mips_fp32
= 1;
10344 file_mips_fp32
= 0;
10349 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
10351 as_bad (_("-mabi is supported for ELF format only"));
10354 if (strcmp (arg
, "32") == 0)
10355 mips_abi
= O32_ABI
;
10356 else if (strcmp (arg
, "o64") == 0)
10357 mips_abi
= O64_ABI
;
10358 else if (strcmp (arg
, "n32") == 0)
10359 mips_abi
= N32_ABI
;
10360 else if (strcmp (arg
, "64") == 0)
10362 mips_abi
= N64_ABI
;
10363 if (! support_64bit_objects())
10364 as_fatal (_("No compiled in support for 64 bit object file "
10367 else if (strcmp (arg
, "eabi") == 0)
10368 mips_abi
= EABI_ABI
;
10371 as_fatal (_("invalid abi -mabi=%s"), arg
);
10375 #endif /* OBJ_ELF */
10377 case OPTION_M7000_HILO_FIX
:
10378 mips_7000_hilo_fix
= TRUE
;
10381 case OPTION_MNO_7000_HILO_FIX
:
10382 mips_7000_hilo_fix
= FALSE
;
10386 case OPTION_MDEBUG
:
10387 mips_flag_mdebug
= TRUE
;
10390 case OPTION_NO_MDEBUG
:
10391 mips_flag_mdebug
= FALSE
;
10395 mips_flag_pdr
= TRUE
;
10398 case OPTION_NO_PDR
:
10399 mips_flag_pdr
= FALSE
;
10401 #endif /* OBJ_ELF */
10410 /* Set up globals to generate code for the ISA or processor
10411 described by INFO. */
10414 mips_set_architecture (const struct mips_cpu_info
*info
)
10418 file_mips_arch
= info
->cpu
;
10419 mips_opts
.arch
= info
->cpu
;
10420 mips_opts
.isa
= info
->isa
;
10425 /* Likewise for tuning. */
10428 mips_set_tune (const struct mips_cpu_info
*info
)
10431 mips_tune
= info
->cpu
;
10436 mips_after_parse_args (void)
10438 const struct mips_cpu_info
*arch_info
= 0;
10439 const struct mips_cpu_info
*tune_info
= 0;
10441 /* GP relative stuff not working for PE */
10442 if (strncmp (TARGET_OS
, "pe", 2) == 0)
10444 if (g_switch_seen
&& g_switch_value
!= 0)
10445 as_bad (_("-G not supported in this configuration."));
10446 g_switch_value
= 0;
10449 if (mips_abi
== NO_ABI
)
10450 mips_abi
= MIPS_DEFAULT_ABI
;
10452 /* The following code determines the architecture and register size.
10453 Similar code was added to GCC 3.3 (see override_options() in
10454 config/mips/mips.c). The GAS and GCC code should be kept in sync
10455 as much as possible. */
10457 if (mips_arch_string
!= 0)
10458 arch_info
= mips_parse_cpu ("-march", mips_arch_string
);
10460 if (file_mips_isa
!= ISA_UNKNOWN
)
10462 /* Handle -mipsN. At this point, file_mips_isa contains the
10463 ISA level specified by -mipsN, while arch_info->isa contains
10464 the -march selection (if any). */
10465 if (arch_info
!= 0)
10467 /* -march takes precedence over -mipsN, since it is more descriptive.
10468 There's no harm in specifying both as long as the ISA levels
10470 if (file_mips_isa
!= arch_info
->isa
)
10471 as_bad (_("-%s conflicts with the other architecture options, which imply -%s"),
10472 mips_cpu_info_from_isa (file_mips_isa
)->name
,
10473 mips_cpu_info_from_isa (arch_info
->isa
)->name
);
10476 arch_info
= mips_cpu_info_from_isa (file_mips_isa
);
10479 if (arch_info
== 0)
10480 arch_info
= mips_parse_cpu ("default CPU", MIPS_CPU_STRING_DEFAULT
);
10482 if (ABI_NEEDS_64BIT_REGS (mips_abi
) && !ISA_HAS_64BIT_REGS (arch_info
->isa
))
10483 as_bad ("-march=%s is not compatible with the selected ABI",
10486 mips_set_architecture (arch_info
);
10488 /* Optimize for file_mips_arch, unless -mtune selects a different processor. */
10489 if (mips_tune_string
!= 0)
10490 tune_info
= mips_parse_cpu ("-mtune", mips_tune_string
);
10492 if (tune_info
== 0)
10493 mips_set_tune (arch_info
);
10495 mips_set_tune (tune_info
);
10497 if (file_mips_gp32
>= 0)
10499 /* The user specified the size of the integer registers. Make sure
10500 it agrees with the ABI and ISA. */
10501 if (file_mips_gp32
== 0 && !ISA_HAS_64BIT_REGS (mips_opts
.isa
))
10502 as_bad (_("-mgp64 used with a 32-bit processor"));
10503 else if (file_mips_gp32
== 1 && ABI_NEEDS_64BIT_REGS (mips_abi
))
10504 as_bad (_("-mgp32 used with a 64-bit ABI"));
10505 else if (file_mips_gp32
== 0 && ABI_NEEDS_32BIT_REGS (mips_abi
))
10506 as_bad (_("-mgp64 used with a 32-bit ABI"));
10510 /* Infer the integer register size from the ABI and processor.
10511 Restrict ourselves to 32-bit registers if that's all the
10512 processor has, or if the ABI cannot handle 64-bit registers. */
10513 file_mips_gp32
= (ABI_NEEDS_32BIT_REGS (mips_abi
)
10514 || !ISA_HAS_64BIT_REGS (mips_opts
.isa
));
10517 /* ??? GAS treats single-float processors as though they had 64-bit
10518 float registers (although it complains when double-precision
10519 instructions are used). As things stand, saying they have 32-bit
10520 registers would lead to spurious "register must be even" messages.
10521 So here we assume float registers are always the same size as
10522 integer ones, unless the user says otherwise. */
10523 if (file_mips_fp32
< 0)
10524 file_mips_fp32
= file_mips_gp32
;
10526 /* End of GCC-shared inference code. */
10528 /* This flag is set when we have a 64-bit capable CPU but use only
10529 32-bit wide registers. Note that EABI does not use it. */
10530 if (ISA_HAS_64BIT_REGS (mips_opts
.isa
)
10531 && ((mips_abi
== NO_ABI
&& file_mips_gp32
== 1)
10532 || mips_abi
== O32_ABI
))
10533 mips_32bitmode
= 1;
10535 if (mips_opts
.isa
== ISA_MIPS1
&& mips_trap
)
10536 as_bad (_("trap exception not supported at ISA 1"));
10538 /* If the selected architecture includes support for ASEs, enable
10539 generation of code for them. */
10540 if (mips_opts
.mips16
== -1)
10541 mips_opts
.mips16
= (CPU_HAS_MIPS16 (file_mips_arch
)) ? 1 : 0;
10542 if (mips_opts
.ase_mips3d
== -1)
10543 mips_opts
.ase_mips3d
= (CPU_HAS_MIPS3D (file_mips_arch
)) ? 1 : 0;
10544 if (mips_opts
.ase_mdmx
== -1)
10545 mips_opts
.ase_mdmx
= (CPU_HAS_MDMX (file_mips_arch
)) ? 1 : 0;
10547 file_mips_isa
= mips_opts
.isa
;
10548 file_ase_mips16
= mips_opts
.mips16
;
10549 file_ase_mips3d
= mips_opts
.ase_mips3d
;
10550 file_ase_mdmx
= mips_opts
.ase_mdmx
;
10551 mips_opts
.gp32
= file_mips_gp32
;
10552 mips_opts
.fp32
= file_mips_fp32
;
10554 if (mips_flag_mdebug
< 0)
10556 #ifdef OBJ_MAYBE_ECOFF
10557 if (OUTPUT_FLAVOR
== bfd_target_ecoff_flavour
)
10558 mips_flag_mdebug
= 1;
10560 #endif /* OBJ_MAYBE_ECOFF */
10561 mips_flag_mdebug
= 0;
10566 mips_init_after_args (void)
10568 /* initialize opcodes */
10569 bfd_mips_num_opcodes
= bfd_mips_num_builtin_opcodes
;
10570 mips_opcodes
= (struct mips_opcode
*) mips_builtin_opcodes
;
10574 md_pcrel_from (fixS
*fixP
)
10576 valueT addr
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
10577 switch (fixP
->fx_r_type
)
10579 case BFD_RELOC_16_PCREL_S2
:
10580 case BFD_RELOC_MIPS_JMP
:
10581 /* Return the address of the delay slot. */
10588 /* This is called before the symbol table is processed. In order to
10589 work with gcc when using mips-tfile, we must keep all local labels.
10590 However, in other cases, we want to discard them. If we were
10591 called with -g, but we didn't see any debugging information, it may
10592 mean that gcc is smuggling debugging information through to
10593 mips-tfile, in which case we must generate all local labels. */
10596 mips_frob_file_before_adjust (void)
10598 #ifndef NO_ECOFF_DEBUGGING
10599 if (ECOFF_DEBUGGING
10601 && ! ecoff_debugging_seen
)
10602 flag_keep_locals
= 1;
10606 /* Sort any unmatched HI16 and GOT16 relocs so that they immediately precede
10607 the corresponding LO16 reloc. This is called before md_apply_fix3 and
10608 tc_gen_reloc. Unmatched relocs can only be generated by use of explicit
10609 relocation operators.
10611 For our purposes, a %lo() expression matches a %got() or %hi()
10614 (a) it refers to the same symbol; and
10615 (b) the offset applied in the %lo() expression is no lower than
10616 the offset applied in the %got() or %hi().
10618 (b) allows us to cope with code like:
10621 lh $4,%lo(foo+2)($4)
10623 ...which is legal on RELA targets, and has a well-defined behaviour
10624 if the user knows that adding 2 to "foo" will not induce a carry to
10627 When several %lo()s match a particular %got() or %hi(), we use the
10628 following rules to distinguish them:
10630 (1) %lo()s with smaller offsets are a better match than %lo()s with
10633 (2) %lo()s with no matching %got() or %hi() are better than those
10634 that already have a matching %got() or %hi().
10636 (3) later %lo()s are better than earlier %lo()s.
10638 These rules are applied in order.
10640 (1) means, among other things, that %lo()s with identical offsets are
10641 chosen if they exist.
10643 (2) means that we won't associate several high-part relocations with
10644 the same low-part relocation unless there's no alternative. Having
10645 several high parts for the same low part is a GNU extension; this rule
10646 allows careful users to avoid it.
10648 (3) is purely cosmetic. mips_hi_fixup_list is is in reverse order,
10649 with the last high-part relocation being at the front of the list.
10650 It therefore makes sense to choose the last matching low-part
10651 relocation, all other things being equal. It's also easier
10652 to code that way. */
10655 mips_frob_file (void)
10657 struct mips_hi_fixup
*l
;
10659 for (l
= mips_hi_fixup_list
; l
!= NULL
; l
= l
->next
)
10661 segment_info_type
*seginfo
;
10662 bfd_boolean matched_lo_p
;
10663 fixS
**hi_pos
, **lo_pos
, **pos
;
10665 assert (reloc_needs_lo_p (l
->fixp
->fx_r_type
));
10667 /* If a GOT16 relocation turns out to be against a global symbol,
10668 there isn't supposed to be a matching LO. */
10669 if (l
->fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT16
10670 && !pic_need_relax (l
->fixp
->fx_addsy
, l
->seg
))
10673 /* Check quickly whether the next fixup happens to be a matching %lo. */
10674 if (fixup_has_matching_lo_p (l
->fixp
))
10677 seginfo
= seg_info (l
->seg
);
10679 /* Set HI_POS to the position of this relocation in the chain.
10680 Set LO_POS to the position of the chosen low-part relocation.
10681 MATCHED_LO_P is true on entry to the loop if *POS is a low-part
10682 relocation that matches an immediately-preceding high-part
10686 matched_lo_p
= FALSE
;
10687 for (pos
= &seginfo
->fix_root
; *pos
!= NULL
; pos
= &(*pos
)->fx_next
)
10689 if (*pos
== l
->fixp
)
10692 if ((*pos
)->fx_r_type
== BFD_RELOC_LO16
10693 && (*pos
)->fx_addsy
== l
->fixp
->fx_addsy
10694 && (*pos
)->fx_offset
>= l
->fixp
->fx_offset
10696 || (*pos
)->fx_offset
< (*lo_pos
)->fx_offset
10698 && (*pos
)->fx_offset
== (*lo_pos
)->fx_offset
)))
10701 matched_lo_p
= (reloc_needs_lo_p ((*pos
)->fx_r_type
)
10702 && fixup_has_matching_lo_p (*pos
));
10705 /* If we found a match, remove the high-part relocation from its
10706 current position and insert it before the low-part relocation.
10707 Make the offsets match so that fixup_has_matching_lo_p()
10710 We don't warn about unmatched high-part relocations since some
10711 versions of gcc have been known to emit dead "lui ...%hi(...)"
10713 if (lo_pos
!= NULL
)
10715 l
->fixp
->fx_offset
= (*lo_pos
)->fx_offset
;
10716 if (l
->fixp
->fx_next
!= *lo_pos
)
10718 *hi_pos
= l
->fixp
->fx_next
;
10719 l
->fixp
->fx_next
= *lo_pos
;
10726 /* We may have combined relocations without symbols in the N32/N64 ABI.
10727 We have to prevent gas from dropping them. */
10730 mips_force_relocation (fixS
*fixp
)
10732 if (generic_force_reloc (fixp
))
10736 && S_GET_SEGMENT (fixp
->fx_addsy
) == bfd_abs_section_ptr
10737 && (fixp
->fx_r_type
== BFD_RELOC_MIPS_SUB
10738 || fixp
->fx_r_type
== BFD_RELOC_HI16_S
10739 || fixp
->fx_r_type
== BFD_RELOC_LO16
))
10745 /* This hook is called before a fix is simplified. We don't really
10746 decide whether to skip a fix here. Rather, we turn global symbols
10747 used as branch targets into local symbols, such that they undergo
10748 simplification. We can only do this if the symbol is defined and
10749 it is in the same section as the branch. If this doesn't hold, we
10750 emit a better error message than just saying the relocation is not
10751 valid for the selected object format.
10753 FIXP is the fix-up we're going to try to simplify, SEG is the
10754 segment in which the fix up occurs. The return value should be
10755 non-zero to indicate the fix-up is valid for further
10756 simplifications. */
10759 mips_validate_fix (struct fix
*fixP
, asection
*seg
)
10761 /* There's a lot of discussion on whether it should be possible to
10762 use R_MIPS_PC16 to represent branch relocations. The outcome
10763 seems to be that it can, but gas/bfd are very broken in creating
10764 RELA relocations for this, so for now we only accept branches to
10765 symbols in the same section. Anything else is of dubious value,
10766 since there's no guarantee that at link time the symbol would be
10767 in range. Even for branches to local symbols this is arguably
10768 wrong, since it we assume the symbol is not going to be
10769 overridden, which should be possible per ELF library semantics,
10770 but then, there isn't a dynamic relocation that could be used to
10771 this effect, and the target would likely be out of range as well.
10773 Unfortunately, it seems that there is too much code out there
10774 that relies on branches to symbols that are global to be resolved
10775 as if they were local, like the IRIX tools do, so we do it as
10776 well, but with a warning so that people are reminded to fix their
10777 code. If we ever get back to using R_MIPS_PC16 for branch
10778 targets, this entire block should go away (and probably the
10779 whole function). */
10781 if (fixP
->fx_r_type
== BFD_RELOC_16_PCREL_S2
10782 && ((OUTPUT_FLAVOR
== bfd_target_ecoff_flavour
10783 || OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
10784 || bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_16_PCREL_S2
) == NULL
)
10787 if (! S_IS_DEFINED (fixP
->fx_addsy
))
10789 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
10790 _("Cannot branch to undefined symbol."));
10791 /* Avoid any further errors about this fixup. */
10794 else if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
10796 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
10797 _("Cannot branch to symbol in another section."));
10800 else if (S_IS_EXTERNAL (fixP
->fx_addsy
))
10802 symbolS
*sym
= fixP
->fx_addsy
;
10804 if (mips_pic
== SVR4_PIC
)
10805 as_warn_where (fixP
->fx_file
, fixP
->fx_line
,
10806 _("Pretending global symbol used as branch target is local."));
10808 fixP
->fx_addsy
= symbol_create (S_GET_NAME (sym
),
10809 S_GET_SEGMENT (sym
),
10811 symbol_get_frag (sym
));
10812 copy_symbol_attributes (fixP
->fx_addsy
, sym
);
10813 S_CLEAR_EXTERNAL (fixP
->fx_addsy
);
10814 assert (symbol_resolved_p (sym
));
10815 symbol_mark_resolved (fixP
->fx_addsy
);
10822 /* Apply a fixup to the object file. */
10825 md_apply_fix3 (fixS
*fixP
, valueT
*valP
, segT seg ATTRIBUTE_UNUSED
)
10829 reloc_howto_type
*howto
;
10831 /* We ignore generic BFD relocations we don't know about. */
10832 howto
= bfd_reloc_type_lookup (stdoutput
, fixP
->fx_r_type
);
10836 assert (fixP
->fx_size
== 4
10837 || fixP
->fx_r_type
== BFD_RELOC_16
10838 || fixP
->fx_r_type
== BFD_RELOC_64
10839 || fixP
->fx_r_type
== BFD_RELOC_CTOR
10840 || fixP
->fx_r_type
== BFD_RELOC_MIPS_SUB
10841 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
10842 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
);
10844 buf
= (bfd_byte
*) (fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
);
10846 assert (! fixP
->fx_pcrel
);
10848 /* Don't treat parts of a composite relocation as done. There are two
10851 (1) The second and third parts will be against 0 (RSS_UNDEF) but
10852 should nevertheless be emitted if the first part is.
10854 (2) In normal usage, composite relocations are never assembly-time
10855 constants. The easiest way of dealing with the pathological
10856 exceptions is to generate a relocation against STN_UNDEF and
10857 leave everything up to the linker. */
10858 if (fixP
->fx_addsy
== NULL
&& fixP
->fx_tcbit
== 0)
10861 switch (fixP
->fx_r_type
)
10863 case BFD_RELOC_MIPS_TLS_GD
:
10864 case BFD_RELOC_MIPS_TLS_LDM
:
10865 case BFD_RELOC_MIPS_TLS_DTPREL_HI16
:
10866 case BFD_RELOC_MIPS_TLS_DTPREL_LO16
:
10867 case BFD_RELOC_MIPS_TLS_GOTTPREL
:
10868 case BFD_RELOC_MIPS_TLS_TPREL_HI16
:
10869 case BFD_RELOC_MIPS_TLS_TPREL_LO16
:
10870 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
10873 case BFD_RELOC_MIPS_JMP
:
10874 case BFD_RELOC_MIPS_SHIFT5
:
10875 case BFD_RELOC_MIPS_SHIFT6
:
10876 case BFD_RELOC_MIPS_GOT_DISP
:
10877 case BFD_RELOC_MIPS_GOT_PAGE
:
10878 case BFD_RELOC_MIPS_GOT_OFST
:
10879 case BFD_RELOC_MIPS_SUB
:
10880 case BFD_RELOC_MIPS_INSERT_A
:
10881 case BFD_RELOC_MIPS_INSERT_B
:
10882 case BFD_RELOC_MIPS_DELETE
:
10883 case BFD_RELOC_MIPS_HIGHEST
:
10884 case BFD_RELOC_MIPS_HIGHER
:
10885 case BFD_RELOC_MIPS_SCN_DISP
:
10886 case BFD_RELOC_MIPS_REL16
:
10887 case BFD_RELOC_MIPS_RELGOT
:
10888 case BFD_RELOC_MIPS_JALR
:
10889 case BFD_RELOC_HI16
:
10890 case BFD_RELOC_HI16_S
:
10891 case BFD_RELOC_GPREL16
:
10892 case BFD_RELOC_MIPS_LITERAL
:
10893 case BFD_RELOC_MIPS_CALL16
:
10894 case BFD_RELOC_MIPS_GOT16
:
10895 case BFD_RELOC_GPREL32
:
10896 case BFD_RELOC_MIPS_GOT_HI16
:
10897 case BFD_RELOC_MIPS_GOT_LO16
:
10898 case BFD_RELOC_MIPS_CALL_HI16
:
10899 case BFD_RELOC_MIPS_CALL_LO16
:
10900 case BFD_RELOC_MIPS16_GPREL
:
10901 case BFD_RELOC_MIPS16_HI16
:
10902 case BFD_RELOC_MIPS16_HI16_S
:
10903 assert (! fixP
->fx_pcrel
);
10904 /* Nothing needed to do. The value comes from the reloc entry */
10907 case BFD_RELOC_MIPS16_JMP
:
10908 /* We currently always generate a reloc against a symbol, which
10909 means that we don't want an addend even if the symbol is
10915 /* This is handled like BFD_RELOC_32, but we output a sign
10916 extended value if we are only 32 bits. */
10919 if (8 <= sizeof (valueT
))
10920 md_number_to_chars ((char *) buf
, *valP
, 8);
10925 if ((*valP
& 0x80000000) != 0)
10929 md_number_to_chars ((char *)(buf
+ target_big_endian
? 4 : 0),
10931 md_number_to_chars ((char *)(buf
+ target_big_endian
? 0 : 4),
10937 case BFD_RELOC_RVA
:
10939 /* If we are deleting this reloc entry, we must fill in the
10940 value now. This can happen if we have a .word which is not
10941 resolved when it appears but is later defined. */
10943 md_number_to_chars ((char *) buf
, *valP
, 4);
10947 /* If we are deleting this reloc entry, we must fill in the
10950 md_number_to_chars ((char *) buf
, *valP
, 2);
10953 case BFD_RELOC_LO16
:
10954 case BFD_RELOC_MIPS16_LO16
:
10955 /* FIXME: Now that embedded-PIC is gone, some of this code/comment
10956 may be safe to remove, but if so it's not obvious. */
10957 /* When handling an embedded PIC switch statement, we can wind
10958 up deleting a LO16 reloc. See the 'o' case in mips_ip. */
10961 if (*valP
+ 0x8000 > 0xffff)
10962 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
10963 _("relocation overflow"));
10964 if (target_big_endian
)
10966 md_number_to_chars ((char *) buf
, *valP
, 2);
10970 case BFD_RELOC_16_PCREL_S2
:
10971 if ((*valP
& 0x3) != 0)
10972 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
10973 _("Branch to odd address (%lx)"), (long) *valP
);
10976 * We need to save the bits in the instruction since fixup_segment()
10977 * might be deleting the relocation entry (i.e., a branch within
10978 * the current segment).
10980 if (! fixP
->fx_done
)
10983 /* update old instruction data */
10984 if (target_big_endian
)
10985 insn
= (buf
[0] << 24) | (buf
[1] << 16) | (buf
[2] << 8) | buf
[3];
10987 insn
= (buf
[3] << 24) | (buf
[2] << 16) | (buf
[1] << 8) | buf
[0];
10989 if (*valP
+ 0x20000 <= 0x3ffff)
10991 insn
|= (*valP
>> 2) & 0xffff;
10992 md_number_to_chars ((char *) buf
, insn
, 4);
10994 else if (mips_pic
== NO_PIC
10996 && fixP
->fx_frag
->fr_address
>= text_section
->vma
10997 && (fixP
->fx_frag
->fr_address
10998 < text_section
->vma
+ bfd_get_section_size (text_section
))
10999 && ((insn
& 0xffff0000) == 0x10000000 /* beq $0,$0 */
11000 || (insn
& 0xffff0000) == 0x04010000 /* bgez $0 */
11001 || (insn
& 0xffff0000) == 0x04110000)) /* bgezal $0 */
11003 /* The branch offset is too large. If this is an
11004 unconditional branch, and we are not generating PIC code,
11005 we can convert it to an absolute jump instruction. */
11006 if ((insn
& 0xffff0000) == 0x04110000) /* bgezal $0 */
11007 insn
= 0x0c000000; /* jal */
11009 insn
= 0x08000000; /* j */
11010 fixP
->fx_r_type
= BFD_RELOC_MIPS_JMP
;
11012 fixP
->fx_addsy
= section_symbol (text_section
);
11013 *valP
+= md_pcrel_from (fixP
);
11014 md_number_to_chars ((char *) buf
, insn
, 4);
11018 /* If we got here, we have branch-relaxation disabled,
11019 and there's nothing we can do to fix this instruction
11020 without turning it into a longer sequence. */
11021 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
11022 _("Branch out of range"));
11026 case BFD_RELOC_VTABLE_INHERIT
:
11029 && !S_IS_DEFINED (fixP
->fx_addsy
)
11030 && !S_IS_WEAK (fixP
->fx_addsy
))
11031 S_SET_WEAK (fixP
->fx_addsy
);
11034 case BFD_RELOC_VTABLE_ENTRY
:
11042 /* Remember value for tc_gen_reloc. */
11043 fixP
->fx_addnumber
= *valP
;
11053 name
= input_line_pointer
;
11054 c
= get_symbol_end ();
11055 p
= (symbolS
*) symbol_find_or_make (name
);
11056 *input_line_pointer
= c
;
11060 /* Align the current frag to a given power of two. The MIPS assembler
11061 also automatically adjusts any preceding label. */
11064 mips_align (int to
, int fill
, symbolS
*label
)
11066 mips_emit_delays (FALSE
);
11067 frag_align (to
, fill
, 0);
11068 record_alignment (now_seg
, to
);
11071 assert (S_GET_SEGMENT (label
) == now_seg
);
11072 symbol_set_frag (label
, frag_now
);
11073 S_SET_VALUE (label
, (valueT
) frag_now_fix ());
11077 /* Align to a given power of two. .align 0 turns off the automatic
11078 alignment used by the data creating pseudo-ops. */
11081 s_align (int x ATTRIBUTE_UNUSED
)
11084 register long temp_fill
;
11085 long max_alignment
= 15;
11089 o Note that the assembler pulls down any immediately preceding label
11090 to the aligned address.
11091 o It's not documented but auto alignment is reinstated by
11092 a .align pseudo instruction.
11093 o Note also that after auto alignment is turned off the mips assembler
11094 issues an error on attempt to assemble an improperly aligned data item.
11099 temp
= get_absolute_expression ();
11100 if (temp
> max_alignment
)
11101 as_bad (_("Alignment too large: %d. assumed."), temp
= max_alignment
);
11104 as_warn (_("Alignment negative: 0 assumed."));
11107 if (*input_line_pointer
== ',')
11109 ++input_line_pointer
;
11110 temp_fill
= get_absolute_expression ();
11117 mips_align (temp
, (int) temp_fill
,
11118 insn_labels
!= NULL
? insn_labels
->label
: NULL
);
11125 demand_empty_rest_of_line ();
11129 mips_flush_pending_output (void)
11131 mips_emit_delays (FALSE
);
11132 mips_clear_insn_labels ();
11136 s_change_sec (int sec
)
11141 /* The ELF backend needs to know that we are changing sections, so
11142 that .previous works correctly. We could do something like check
11143 for an obj_section_change_hook macro, but that might be confusing
11144 as it would not be appropriate to use it in the section changing
11145 functions in read.c, since obj-elf.c intercepts those. FIXME:
11146 This should be cleaner, somehow. */
11147 obj_elf_section_change_hook ();
11150 mips_emit_delays (FALSE
);
11160 subseg_set (bss_section
, (subsegT
) get_absolute_expression ());
11161 demand_empty_rest_of_line ();
11165 seg
= subseg_new (RDATA_SECTION_NAME
,
11166 (subsegT
) get_absolute_expression ());
11167 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
11169 bfd_set_section_flags (stdoutput
, seg
, (SEC_ALLOC
| SEC_LOAD
11170 | SEC_READONLY
| SEC_RELOC
11172 if (strcmp (TARGET_OS
, "elf") != 0)
11173 record_alignment (seg
, 4);
11175 demand_empty_rest_of_line ();
11179 seg
= subseg_new (".sdata", (subsegT
) get_absolute_expression ());
11180 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
11182 bfd_set_section_flags (stdoutput
, seg
,
11183 SEC_ALLOC
| SEC_LOAD
| SEC_RELOC
| SEC_DATA
);
11184 if (strcmp (TARGET_OS
, "elf") != 0)
11185 record_alignment (seg
, 4);
11187 demand_empty_rest_of_line ();
11195 s_change_section (int ignore ATTRIBUTE_UNUSED
)
11198 char *section_name
;
11203 int section_entry_size
;
11204 int section_alignment
;
11206 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
11209 section_name
= input_line_pointer
;
11210 c
= get_symbol_end ();
11212 next_c
= *(input_line_pointer
+ 1);
11214 /* Do we have .section Name<,"flags">? */
11215 if (c
!= ',' || (c
== ',' && next_c
== '"'))
11217 /* just after name is now '\0'. */
11218 *input_line_pointer
= c
;
11219 input_line_pointer
= section_name
;
11220 obj_elf_section (ignore
);
11223 input_line_pointer
++;
11225 /* Do we have .section Name<,type><,flag><,entry_size><,alignment> */
11227 section_type
= get_absolute_expression ();
11230 if (*input_line_pointer
++ == ',')
11231 section_flag
= get_absolute_expression ();
11234 if (*input_line_pointer
++ == ',')
11235 section_entry_size
= get_absolute_expression ();
11237 section_entry_size
= 0;
11238 if (*input_line_pointer
++ == ',')
11239 section_alignment
= get_absolute_expression ();
11241 section_alignment
= 0;
11243 section_name
= xstrdup (section_name
);
11245 /* When using the generic form of .section (as implemented by obj-elf.c),
11246 there's no way to set the section type to SHT_MIPS_DWARF. Users have
11247 traditionally had to fall back on the more common @progbits instead.
11249 There's nothing really harmful in this, since bfd will correct
11250 SHT_PROGBITS to SHT_MIPS_DWARF before writing out the file. But it
11251 means that, for backwards compatibiltiy, the special_section entries
11252 for dwarf sections must use SHT_PROGBITS rather than SHT_MIPS_DWARF.
11254 Even so, we shouldn't force users of the MIPS .section syntax to
11255 incorrectly label the sections as SHT_PROGBITS. The best compromise
11256 seems to be to map SHT_MIPS_DWARF to SHT_PROGBITS before calling the
11257 generic type-checking code. */
11258 if (section_type
== SHT_MIPS_DWARF
)
11259 section_type
= SHT_PROGBITS
;
11261 obj_elf_change_section (section_name
, section_type
, section_flag
,
11262 section_entry_size
, 0, 0, 0);
11264 if (now_seg
->name
!= section_name
)
11265 free (section_name
);
11266 #endif /* OBJ_ELF */
11270 mips_enable_auto_align (void)
11276 s_cons (int log_size
)
11280 label
= insn_labels
!= NULL
? insn_labels
->label
: NULL
;
11281 mips_emit_delays (FALSE
);
11282 if (log_size
> 0 && auto_align
)
11283 mips_align (log_size
, 0, label
);
11284 mips_clear_insn_labels ();
11285 cons (1 << log_size
);
11289 s_float_cons (int type
)
11293 label
= insn_labels
!= NULL
? insn_labels
->label
: NULL
;
11295 mips_emit_delays (FALSE
);
11300 mips_align (3, 0, label
);
11302 mips_align (2, 0, label
);
11305 mips_clear_insn_labels ();
11310 /* Handle .globl. We need to override it because on Irix 5 you are
11313 where foo is an undefined symbol, to mean that foo should be
11314 considered to be the address of a function. */
11317 s_mips_globl (int x ATTRIBUTE_UNUSED
)
11324 name
= input_line_pointer
;
11325 c
= get_symbol_end ();
11326 symbolP
= symbol_find_or_make (name
);
11327 *input_line_pointer
= c
;
11328 SKIP_WHITESPACE ();
11330 /* On Irix 5, every global symbol that is not explicitly labelled as
11331 being a function is apparently labelled as being an object. */
11334 if (! is_end_of_line
[(unsigned char) *input_line_pointer
])
11339 secname
= input_line_pointer
;
11340 c
= get_symbol_end ();
11341 sec
= bfd_get_section_by_name (stdoutput
, secname
);
11343 as_bad (_("%s: no such section"), secname
);
11344 *input_line_pointer
= c
;
11346 if (sec
!= NULL
&& (sec
->flags
& SEC_CODE
) != 0)
11347 flag
= BSF_FUNCTION
;
11350 symbol_get_bfdsym (symbolP
)->flags
|= flag
;
11352 S_SET_EXTERNAL (symbolP
);
11353 demand_empty_rest_of_line ();
11357 s_option (int x ATTRIBUTE_UNUSED
)
11362 opt
= input_line_pointer
;
11363 c
= get_symbol_end ();
11367 /* FIXME: What does this mean? */
11369 else if (strncmp (opt
, "pic", 3) == 0)
11373 i
= atoi (opt
+ 3);
11378 mips_pic
= SVR4_PIC
;
11379 mips_abicalls
= TRUE
;
11382 as_bad (_(".option pic%d not supported"), i
);
11384 if (mips_pic
== SVR4_PIC
)
11386 if (g_switch_seen
&& g_switch_value
!= 0)
11387 as_warn (_("-G may not be used with SVR4 PIC code"));
11388 g_switch_value
= 0;
11389 bfd_set_gp_size (stdoutput
, 0);
11393 as_warn (_("Unrecognized option \"%s\""), opt
);
11395 *input_line_pointer
= c
;
11396 demand_empty_rest_of_line ();
11399 /* This structure is used to hold a stack of .set values. */
11401 struct mips_option_stack
11403 struct mips_option_stack
*next
;
11404 struct mips_set_options options
;
11407 static struct mips_option_stack
*mips_opts_stack
;
11409 /* Handle the .set pseudo-op. */
11412 s_mipsset (int x ATTRIBUTE_UNUSED
)
11414 char *name
= input_line_pointer
, ch
;
11416 while (!is_end_of_line
[(unsigned char) *input_line_pointer
])
11417 ++input_line_pointer
;
11418 ch
= *input_line_pointer
;
11419 *input_line_pointer
= '\0';
11421 if (strcmp (name
, "reorder") == 0)
11423 if (mips_opts
.noreorder
&& prev_nop_frag
!= NULL
)
11425 /* If we still have pending nops, we can discard them. The
11426 usual nop handling will insert any that are still
11428 prev_nop_frag
->fr_fix
-= (prev_nop_frag_holds
11429 * (mips_opts
.mips16
? 2 : 4));
11430 prev_nop_frag
= NULL
;
11432 mips_opts
.noreorder
= 0;
11434 else if (strcmp (name
, "noreorder") == 0)
11436 mips_emit_delays (TRUE
);
11437 mips_opts
.noreorder
= 1;
11438 mips_any_noreorder
= 1;
11440 else if (strcmp (name
, "at") == 0)
11442 mips_opts
.noat
= 0;
11444 else if (strcmp (name
, "noat") == 0)
11446 mips_opts
.noat
= 1;
11448 else if (strcmp (name
, "macro") == 0)
11450 mips_opts
.warn_about_macros
= 0;
11452 else if (strcmp (name
, "nomacro") == 0)
11454 if (mips_opts
.noreorder
== 0)
11455 as_bad (_("`noreorder' must be set before `nomacro'"));
11456 mips_opts
.warn_about_macros
= 1;
11458 else if (strcmp (name
, "move") == 0 || strcmp (name
, "novolatile") == 0)
11460 mips_opts
.nomove
= 0;
11462 else if (strcmp (name
, "nomove") == 0 || strcmp (name
, "volatile") == 0)
11464 mips_opts
.nomove
= 1;
11466 else if (strcmp (name
, "bopt") == 0)
11468 mips_opts
.nobopt
= 0;
11470 else if (strcmp (name
, "nobopt") == 0)
11472 mips_opts
.nobopt
= 1;
11474 else if (strcmp (name
, "mips16") == 0
11475 || strcmp (name
, "MIPS-16") == 0)
11476 mips_opts
.mips16
= 1;
11477 else if (strcmp (name
, "nomips16") == 0
11478 || strcmp (name
, "noMIPS-16") == 0)
11479 mips_opts
.mips16
= 0;
11480 else if (strcmp (name
, "mips3d") == 0)
11481 mips_opts
.ase_mips3d
= 1;
11482 else if (strcmp (name
, "nomips3d") == 0)
11483 mips_opts
.ase_mips3d
= 0;
11484 else if (strcmp (name
, "mdmx") == 0)
11485 mips_opts
.ase_mdmx
= 1;
11486 else if (strcmp (name
, "nomdmx") == 0)
11487 mips_opts
.ase_mdmx
= 0;
11488 else if (strncmp (name
, "mips", 4) == 0 || strncmp (name
, "arch=", 5) == 0)
11492 /* Permit the user to change the ISA and architecture on the fly.
11493 Needless to say, misuse can cause serious problems. */
11494 if (strcmp (name
, "mips0") == 0 || strcmp (name
, "arch=default") == 0)
11497 mips_opts
.isa
= file_mips_isa
;
11498 mips_opts
.arch
= file_mips_arch
;
11500 else if (strncmp (name
, "arch=", 5) == 0)
11502 const struct mips_cpu_info
*p
;
11504 p
= mips_parse_cpu("internal use", name
+ 5);
11506 as_bad (_("unknown architecture %s"), name
+ 5);
11509 mips_opts
.arch
= p
->cpu
;
11510 mips_opts
.isa
= p
->isa
;
11513 else if (strncmp (name
, "mips", 4) == 0)
11515 const struct mips_cpu_info
*p
;
11517 p
= mips_parse_cpu("internal use", name
);
11519 as_bad (_("unknown ISA level %s"), name
+ 4);
11522 mips_opts
.arch
= p
->cpu
;
11523 mips_opts
.isa
= p
->isa
;
11527 as_bad (_("unknown ISA or architecture %s"), name
);
11529 switch (mips_opts
.isa
)
11537 mips_opts
.gp32
= 1;
11538 mips_opts
.fp32
= 1;
11545 mips_opts
.gp32
= 0;
11546 mips_opts
.fp32
= 0;
11549 as_bad (_("unknown ISA level %s"), name
+ 4);
11554 mips_opts
.gp32
= file_mips_gp32
;
11555 mips_opts
.fp32
= file_mips_fp32
;
11558 else if (strcmp (name
, "autoextend") == 0)
11559 mips_opts
.noautoextend
= 0;
11560 else if (strcmp (name
, "noautoextend") == 0)
11561 mips_opts
.noautoextend
= 1;
11562 else if (strcmp (name
, "push") == 0)
11564 struct mips_option_stack
*s
;
11566 s
= (struct mips_option_stack
*) xmalloc (sizeof *s
);
11567 s
->next
= mips_opts_stack
;
11568 s
->options
= mips_opts
;
11569 mips_opts_stack
= s
;
11571 else if (strcmp (name
, "pop") == 0)
11573 struct mips_option_stack
*s
;
11575 s
= mips_opts_stack
;
11577 as_bad (_(".set pop with no .set push"));
11580 /* If we're changing the reorder mode we need to handle
11581 delay slots correctly. */
11582 if (s
->options
.noreorder
&& ! mips_opts
.noreorder
)
11583 mips_emit_delays (TRUE
);
11584 else if (! s
->options
.noreorder
&& mips_opts
.noreorder
)
11586 if (prev_nop_frag
!= NULL
)
11588 prev_nop_frag
->fr_fix
-= (prev_nop_frag_holds
11589 * (mips_opts
.mips16
? 2 : 4));
11590 prev_nop_frag
= NULL
;
11594 mips_opts
= s
->options
;
11595 mips_opts_stack
= s
->next
;
11599 else if (strcmp (name
, "sym32") == 0)
11600 mips_opts
.sym32
= TRUE
;
11601 else if (strcmp (name
, "nosym32") == 0)
11602 mips_opts
.sym32
= FALSE
;
11605 as_warn (_("Tried to set unrecognized symbol: %s\n"), name
);
11607 *input_line_pointer
= ch
;
11608 demand_empty_rest_of_line ();
11611 /* Handle the .abicalls pseudo-op. I believe this is equivalent to
11612 .option pic2. It means to generate SVR4 PIC calls. */
11615 s_abicalls (int ignore ATTRIBUTE_UNUSED
)
11617 mips_pic
= SVR4_PIC
;
11618 mips_abicalls
= TRUE
;
11620 if (g_switch_seen
&& g_switch_value
!= 0)
11621 as_warn (_("-G may not be used with SVR4 PIC code"));
11622 g_switch_value
= 0;
11624 bfd_set_gp_size (stdoutput
, 0);
11625 demand_empty_rest_of_line ();
11628 /* Handle the .cpload pseudo-op. This is used when generating SVR4
11629 PIC code. It sets the $gp register for the function based on the
11630 function address, which is in the register named in the argument.
11631 This uses a relocation against _gp_disp, which is handled specially
11632 by the linker. The result is:
11633 lui $gp,%hi(_gp_disp)
11634 addiu $gp,$gp,%lo(_gp_disp)
11635 addu $gp,$gp,.cpload argument
11636 The .cpload argument is normally $25 == $t9.
11638 The -mno-shared option changes this to:
11639 lui $gp,%hi(__gnu_local_gp)
11640 addiu $gp,$gp,%lo(__gnu_local_gp)
11641 and the argument is ignored. This saves an instruction, but the
11642 resulting code is not position independent; it uses an absolute
11643 address for __gnu_local_gp. Thus code assembled with -mno-shared
11644 can go into an ordinary executable, but not into a shared library. */
11647 s_cpload (int ignore ATTRIBUTE_UNUSED
)
11653 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
11654 .cpload is ignored. */
11655 if (mips_pic
!= SVR4_PIC
|| HAVE_NEWABI
)
11661 /* .cpload should be in a .set noreorder section. */
11662 if (mips_opts
.noreorder
== 0)
11663 as_warn (_(".cpload not in noreorder section"));
11665 reg
= tc_get_register (0);
11667 /* If we need to produce a 64-bit address, we are better off using
11668 the default instruction sequence. */
11669 in_shared
= mips_in_shared
|| HAVE_64BIT_SYMBOLS
;
11671 ex
.X_op
= O_symbol
;
11672 ex
.X_add_symbol
= symbol_find_or_make (in_shared
? "_gp_disp" :
11674 ex
.X_op_symbol
= NULL
;
11675 ex
.X_add_number
= 0;
11677 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
11678 symbol_get_bfdsym (ex
.X_add_symbol
)->flags
|= BSF_OBJECT
;
11681 macro_build_lui (&ex
, mips_gp_register
);
11682 macro_build (&ex
, "addiu", "t,r,j", mips_gp_register
,
11683 mips_gp_register
, BFD_RELOC_LO16
);
11685 macro_build (NULL
, "addu", "d,v,t", mips_gp_register
,
11686 mips_gp_register
, reg
);
11689 demand_empty_rest_of_line ();
11692 /* Handle the .cpsetup pseudo-op defined for NewABI PIC code. The syntax is:
11693 .cpsetup $reg1, offset|$reg2, label
11695 If offset is given, this results in:
11696 sd $gp, offset($sp)
11697 lui $gp, %hi(%neg(%gp_rel(label)))
11698 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
11699 daddu $gp, $gp, $reg1
11701 If $reg2 is given, this results in:
11702 daddu $reg2, $gp, $0
11703 lui $gp, %hi(%neg(%gp_rel(label)))
11704 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
11705 daddu $gp, $gp, $reg1
11706 $reg1 is normally $25 == $t9.
11708 The -mno-shared option replaces the last three instructions with
11710 addiu $gp,$gp,%lo(_gp)
11714 s_cpsetup (int ignore ATTRIBUTE_UNUSED
)
11716 expressionS ex_off
;
11717 expressionS ex_sym
;
11720 /* If we are not generating SVR4 PIC code, .cpsetup is ignored.
11721 We also need NewABI support. */
11722 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
11728 reg1
= tc_get_register (0);
11729 SKIP_WHITESPACE ();
11730 if (*input_line_pointer
!= ',')
11732 as_bad (_("missing argument separator ',' for .cpsetup"));
11736 ++input_line_pointer
;
11737 SKIP_WHITESPACE ();
11738 if (*input_line_pointer
== '$')
11740 mips_cpreturn_register
= tc_get_register (0);
11741 mips_cpreturn_offset
= -1;
11745 mips_cpreturn_offset
= get_absolute_expression ();
11746 mips_cpreturn_register
= -1;
11748 SKIP_WHITESPACE ();
11749 if (*input_line_pointer
!= ',')
11751 as_bad (_("missing argument separator ',' for .cpsetup"));
11755 ++input_line_pointer
;
11756 SKIP_WHITESPACE ();
11757 expression (&ex_sym
);
11760 if (mips_cpreturn_register
== -1)
11762 ex_off
.X_op
= O_constant
;
11763 ex_off
.X_add_symbol
= NULL
;
11764 ex_off
.X_op_symbol
= NULL
;
11765 ex_off
.X_add_number
= mips_cpreturn_offset
;
11767 macro_build (&ex_off
, "sd", "t,o(b)", mips_gp_register
,
11768 BFD_RELOC_LO16
, SP
);
11771 macro_build (NULL
, "daddu", "d,v,t", mips_cpreturn_register
,
11772 mips_gp_register
, 0);
11774 if (mips_in_shared
|| HAVE_64BIT_SYMBOLS
)
11776 macro_build (&ex_sym
, "lui", "t,u", mips_gp_register
,
11777 -1, BFD_RELOC_GPREL16
, BFD_RELOC_MIPS_SUB
,
11780 macro_build (&ex_sym
, "addiu", "t,r,j", mips_gp_register
,
11781 mips_gp_register
, -1, BFD_RELOC_GPREL16
,
11782 BFD_RELOC_MIPS_SUB
, BFD_RELOC_LO16
);
11784 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", mips_gp_register
,
11785 mips_gp_register
, reg1
);
11791 ex
.X_op
= O_symbol
;
11792 ex
.X_add_symbol
= symbol_find_or_make ("_gp");
11793 ex
.X_op_symbol
= NULL
;
11794 ex
.X_add_number
= 0;
11796 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
11797 symbol_get_bfdsym (ex
.X_add_symbol
)->flags
|= BSF_OBJECT
;
11799 macro_build_lui (&ex
, mips_gp_register
);
11800 macro_build (&ex
, "addiu", "t,r,j", mips_gp_register
,
11801 mips_gp_register
, BFD_RELOC_LO16
);
11806 demand_empty_rest_of_line ();
11810 s_cplocal (int ignore ATTRIBUTE_UNUSED
)
11812 /* If we are not generating SVR4 PIC code, or if this is not NewABI code,
11813 .cplocal is ignored. */
11814 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
11820 mips_gp_register
= tc_get_register (0);
11821 demand_empty_rest_of_line ();
11824 /* Handle the .cprestore pseudo-op. This stores $gp into a given
11825 offset from $sp. The offset is remembered, and after making a PIC
11826 call $gp is restored from that location. */
11829 s_cprestore (int ignore ATTRIBUTE_UNUSED
)
11833 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
11834 .cprestore is ignored. */
11835 if (mips_pic
!= SVR4_PIC
|| HAVE_NEWABI
)
11841 mips_cprestore_offset
= get_absolute_expression ();
11842 mips_cprestore_valid
= 1;
11844 ex
.X_op
= O_constant
;
11845 ex
.X_add_symbol
= NULL
;
11846 ex
.X_op_symbol
= NULL
;
11847 ex
.X_add_number
= mips_cprestore_offset
;
11850 macro_build_ldst_constoffset (&ex
, ADDRESS_STORE_INSN
, mips_gp_register
,
11851 SP
, HAVE_64BIT_ADDRESSES
);
11854 demand_empty_rest_of_line ();
11857 /* Handle the .cpreturn pseudo-op defined for NewABI PIC code. If an offset
11858 was given in the preceding .cpsetup, it results in:
11859 ld $gp, offset($sp)
11861 If a register $reg2 was given there, it results in:
11862 daddu $gp, $reg2, $0
11865 s_cpreturn (int ignore ATTRIBUTE_UNUSED
)
11869 /* If we are not generating SVR4 PIC code, .cpreturn is ignored.
11870 We also need NewABI support. */
11871 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
11878 if (mips_cpreturn_register
== -1)
11880 ex
.X_op
= O_constant
;
11881 ex
.X_add_symbol
= NULL
;
11882 ex
.X_op_symbol
= NULL
;
11883 ex
.X_add_number
= mips_cpreturn_offset
;
11885 macro_build (&ex
, "ld", "t,o(b)", mips_gp_register
, BFD_RELOC_LO16
, SP
);
11888 macro_build (NULL
, "daddu", "d,v,t", mips_gp_register
,
11889 mips_cpreturn_register
, 0);
11892 demand_empty_rest_of_line ();
11895 /* Handle the .gpvalue pseudo-op. This is used when generating NewABI PIC
11896 code. It sets the offset to use in gp_rel relocations. */
11899 s_gpvalue (int ignore ATTRIBUTE_UNUSED
)
11901 /* If we are not generating SVR4 PIC code, .gpvalue is ignored.
11902 We also need NewABI support. */
11903 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
11909 mips_gprel_offset
= get_absolute_expression ();
11911 demand_empty_rest_of_line ();
11914 /* Handle the .gpword pseudo-op. This is used when generating PIC
11915 code. It generates a 32 bit GP relative reloc. */
11918 s_gpword (int ignore ATTRIBUTE_UNUSED
)
11924 /* When not generating PIC code, this is treated as .word. */
11925 if (mips_pic
!= SVR4_PIC
)
11931 label
= insn_labels
!= NULL
? insn_labels
->label
: NULL
;
11932 mips_emit_delays (TRUE
);
11934 mips_align (2, 0, label
);
11935 mips_clear_insn_labels ();
11939 if (ex
.X_op
!= O_symbol
|| ex
.X_add_number
!= 0)
11941 as_bad (_("Unsupported use of .gpword"));
11942 ignore_rest_of_line ();
11946 md_number_to_chars (p
, 0, 4);
11947 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 4, &ex
, FALSE
,
11948 BFD_RELOC_GPREL32
);
11950 demand_empty_rest_of_line ();
11954 s_gpdword (int ignore ATTRIBUTE_UNUSED
)
11960 /* When not generating PIC code, this is treated as .dword. */
11961 if (mips_pic
!= SVR4_PIC
)
11967 label
= insn_labels
!= NULL
? insn_labels
->label
: NULL
;
11968 mips_emit_delays (TRUE
);
11970 mips_align (3, 0, label
);
11971 mips_clear_insn_labels ();
11975 if (ex
.X_op
!= O_symbol
|| ex
.X_add_number
!= 0)
11977 as_bad (_("Unsupported use of .gpdword"));
11978 ignore_rest_of_line ();
11982 md_number_to_chars (p
, 0, 8);
11983 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 4, &ex
, FALSE
,
11984 BFD_RELOC_GPREL32
)->fx_tcbit
= 1;
11986 /* GPREL32 composed with 64 gives a 64-bit GP offset. */
11987 fix_new (frag_now
, p
- frag_now
->fr_literal
, 8, NULL
, 0,
11988 FALSE
, BFD_RELOC_64
)->fx_tcbit
= 1;
11990 demand_empty_rest_of_line ();
11993 /* Handle the .cpadd pseudo-op. This is used when dealing with switch
11994 tables in SVR4 PIC code. */
11997 s_cpadd (int ignore ATTRIBUTE_UNUSED
)
12001 /* This is ignored when not generating SVR4 PIC code. */
12002 if (mips_pic
!= SVR4_PIC
)
12008 /* Add $gp to the register named as an argument. */
12010 reg
= tc_get_register (0);
12011 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", reg
, reg
, mips_gp_register
);
12014 demand_empty_rest_of_line ();
12017 /* Handle the .insn pseudo-op. This marks instruction labels in
12018 mips16 mode. This permits the linker to handle them specially,
12019 such as generating jalx instructions when needed. We also make
12020 them odd for the duration of the assembly, in order to generate the
12021 right sort of code. We will make them even in the adjust_symtab
12022 routine, while leaving them marked. This is convenient for the
12023 debugger and the disassembler. The linker knows to make them odd
12027 s_insn (int ignore ATTRIBUTE_UNUSED
)
12029 mips16_mark_labels ();
12031 demand_empty_rest_of_line ();
12034 /* Handle a .stabn directive. We need these in order to mark a label
12035 as being a mips16 text label correctly. Sometimes the compiler
12036 will emit a label, followed by a .stabn, and then switch sections.
12037 If the label and .stabn are in mips16 mode, then the label is
12038 really a mips16 text label. */
12041 s_mips_stab (int type
)
12044 mips16_mark_labels ();
12049 /* Handle the .weakext pseudo-op as defined in Kane and Heinrich.
12053 s_mips_weakext (int ignore ATTRIBUTE_UNUSED
)
12060 name
= input_line_pointer
;
12061 c
= get_symbol_end ();
12062 symbolP
= symbol_find_or_make (name
);
12063 S_SET_WEAK (symbolP
);
12064 *input_line_pointer
= c
;
12066 SKIP_WHITESPACE ();
12068 if (! is_end_of_line
[(unsigned char) *input_line_pointer
])
12070 if (S_IS_DEFINED (symbolP
))
12072 as_bad ("ignoring attempt to redefine symbol %s",
12073 S_GET_NAME (symbolP
));
12074 ignore_rest_of_line ();
12078 if (*input_line_pointer
== ',')
12080 ++input_line_pointer
;
12081 SKIP_WHITESPACE ();
12085 if (exp
.X_op
!= O_symbol
)
12087 as_bad ("bad .weakext directive");
12088 ignore_rest_of_line ();
12091 symbol_set_value_expression (symbolP
, &exp
);
12094 demand_empty_rest_of_line ();
12097 /* Parse a register string into a number. Called from the ECOFF code
12098 to parse .frame. The argument is non-zero if this is the frame
12099 register, so that we can record it in mips_frame_reg. */
12102 tc_get_register (int frame
)
12106 SKIP_WHITESPACE ();
12107 if (*input_line_pointer
++ != '$')
12109 as_warn (_("expected `$'"));
12112 else if (ISDIGIT (*input_line_pointer
))
12114 reg
= get_absolute_expression ();
12115 if (reg
< 0 || reg
>= 32)
12117 as_warn (_("Bad register number"));
12123 if (strncmp (input_line_pointer
, "ra", 2) == 0)
12126 input_line_pointer
+= 2;
12128 else if (strncmp (input_line_pointer
, "fp", 2) == 0)
12131 input_line_pointer
+= 2;
12133 else if (strncmp (input_line_pointer
, "sp", 2) == 0)
12136 input_line_pointer
+= 2;
12138 else if (strncmp (input_line_pointer
, "gp", 2) == 0)
12141 input_line_pointer
+= 2;
12143 else if (strncmp (input_line_pointer
, "at", 2) == 0)
12146 input_line_pointer
+= 2;
12148 else if (strncmp (input_line_pointer
, "kt0", 3) == 0)
12151 input_line_pointer
+= 3;
12153 else if (strncmp (input_line_pointer
, "kt1", 3) == 0)
12156 input_line_pointer
+= 3;
12158 else if (strncmp (input_line_pointer
, "zero", 4) == 0)
12161 input_line_pointer
+= 4;
12165 as_warn (_("Unrecognized register name"));
12167 while (ISALNUM(*input_line_pointer
))
12168 input_line_pointer
++;
12173 mips_frame_reg
= reg
!= 0 ? reg
: SP
;
12174 mips_frame_reg_valid
= 1;
12175 mips_cprestore_valid
= 0;
12181 md_section_align (asection
*seg
, valueT addr
)
12183 int align
= bfd_get_section_alignment (stdoutput
, seg
);
12186 /* We don't need to align ELF sections to the full alignment.
12187 However, Irix 5 may prefer that we align them at least to a 16
12188 byte boundary. We don't bother to align the sections if we are
12189 targeted for an embedded system. */
12190 if (strcmp (TARGET_OS
, "elf") == 0)
12196 return ((addr
+ (1 << align
) - 1) & (-1 << align
));
12199 /* Utility routine, called from above as well. If called while the
12200 input file is still being read, it's only an approximation. (For
12201 example, a symbol may later become defined which appeared to be
12202 undefined earlier.) */
12205 nopic_need_relax (symbolS
*sym
, int before_relaxing
)
12210 if (g_switch_value
> 0)
12212 const char *symname
;
12215 /* Find out whether this symbol can be referenced off the $gp
12216 register. It can be if it is smaller than the -G size or if
12217 it is in the .sdata or .sbss section. Certain symbols can
12218 not be referenced off the $gp, although it appears as though
12220 symname
= S_GET_NAME (sym
);
12221 if (symname
!= (const char *) NULL
12222 && (strcmp (symname
, "eprol") == 0
12223 || strcmp (symname
, "etext") == 0
12224 || strcmp (symname
, "_gp") == 0
12225 || strcmp (symname
, "edata") == 0
12226 || strcmp (symname
, "_fbss") == 0
12227 || strcmp (symname
, "_fdata") == 0
12228 || strcmp (symname
, "_ftext") == 0
12229 || strcmp (symname
, "end") == 0
12230 || strcmp (symname
, "_gp_disp") == 0))
12232 else if ((! S_IS_DEFINED (sym
) || S_IS_COMMON (sym
))
12234 #ifndef NO_ECOFF_DEBUGGING
12235 || (symbol_get_obj (sym
)->ecoff_extern_size
!= 0
12236 && (symbol_get_obj (sym
)->ecoff_extern_size
12237 <= g_switch_value
))
12239 /* We must defer this decision until after the whole
12240 file has been read, since there might be a .extern
12241 after the first use of this symbol. */
12242 || (before_relaxing
12243 #ifndef NO_ECOFF_DEBUGGING
12244 && symbol_get_obj (sym
)->ecoff_extern_size
== 0
12246 && S_GET_VALUE (sym
) == 0)
12247 || (S_GET_VALUE (sym
) != 0
12248 && S_GET_VALUE (sym
) <= g_switch_value
)))
12252 const char *segname
;
12254 segname
= segment_name (S_GET_SEGMENT (sym
));
12255 assert (strcmp (segname
, ".lit8") != 0
12256 && strcmp (segname
, ".lit4") != 0);
12257 change
= (strcmp (segname
, ".sdata") != 0
12258 && strcmp (segname
, ".sbss") != 0
12259 && strncmp (segname
, ".sdata.", 7) != 0
12260 && strncmp (segname
, ".gnu.linkonce.s.", 16) != 0);
12265 /* We are not optimizing for the $gp register. */
12270 /* Return true if the given symbol should be considered local for SVR4 PIC. */
12273 pic_need_relax (symbolS
*sym
, asection
*segtype
)
12276 bfd_boolean linkonce
;
12278 /* Handle the case of a symbol equated to another symbol. */
12279 while (symbol_equated_reloc_p (sym
))
12283 /* It's possible to get a loop here in a badly written
12285 n
= symbol_get_value_expression (sym
)->X_add_symbol
;
12291 symsec
= S_GET_SEGMENT (sym
);
12293 /* duplicate the test for LINK_ONCE sections as in adjust_reloc_syms */
12295 if (symsec
!= segtype
&& ! S_IS_LOCAL (sym
))
12297 if ((bfd_get_section_flags (stdoutput
, symsec
) & SEC_LINK_ONCE
)
12301 /* The GNU toolchain uses an extension for ELF: a section
12302 beginning with the magic string .gnu.linkonce is a linkonce
12304 if (strncmp (segment_name (symsec
), ".gnu.linkonce",
12305 sizeof ".gnu.linkonce" - 1) == 0)
12309 /* This must duplicate the test in adjust_reloc_syms. */
12310 return (symsec
!= &bfd_und_section
12311 && symsec
!= &bfd_abs_section
12312 && ! bfd_is_com_section (symsec
)
12315 /* A global or weak symbol is treated as external. */
12316 && (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
12317 || (! S_IS_WEAK (sym
) && ! S_IS_EXTERNAL (sym
)))
12323 /* Given a mips16 variant frag FRAGP, return non-zero if it needs an
12324 extended opcode. SEC is the section the frag is in. */
12327 mips16_extended_frag (fragS
*fragp
, asection
*sec
, long stretch
)
12330 register const struct mips16_immed_operand
*op
;
12332 int mintiny
, maxtiny
;
12336 if (RELAX_MIPS16_USER_SMALL (fragp
->fr_subtype
))
12338 if (RELAX_MIPS16_USER_EXT (fragp
->fr_subtype
))
12341 type
= RELAX_MIPS16_TYPE (fragp
->fr_subtype
);
12342 op
= mips16_immed_operands
;
12343 while (op
->type
!= type
)
12346 assert (op
< mips16_immed_operands
+ MIPS16_NUM_IMMED
);
12351 if (type
== '<' || type
== '>' || type
== '[' || type
== ']')
12354 maxtiny
= 1 << op
->nbits
;
12359 maxtiny
= (1 << op
->nbits
) - 1;
12364 mintiny
= - (1 << (op
->nbits
- 1));
12365 maxtiny
= (1 << (op
->nbits
- 1)) - 1;
12368 sym_frag
= symbol_get_frag (fragp
->fr_symbol
);
12369 val
= S_GET_VALUE (fragp
->fr_symbol
);
12370 symsec
= S_GET_SEGMENT (fragp
->fr_symbol
);
12376 /* We won't have the section when we are called from
12377 mips_relax_frag. However, we will always have been called
12378 from md_estimate_size_before_relax first. If this is a
12379 branch to a different section, we mark it as such. If SEC is
12380 NULL, and the frag is not marked, then it must be a branch to
12381 the same section. */
12384 if (RELAX_MIPS16_LONG_BRANCH (fragp
->fr_subtype
))
12389 /* Must have been called from md_estimate_size_before_relax. */
12392 fragp
->fr_subtype
=
12393 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
12395 /* FIXME: We should support this, and let the linker
12396 catch branches and loads that are out of range. */
12397 as_bad_where (fragp
->fr_file
, fragp
->fr_line
,
12398 _("unsupported PC relative reference to different section"));
12402 if (fragp
!= sym_frag
&& sym_frag
->fr_address
== 0)
12403 /* Assume non-extended on the first relaxation pass.
12404 The address we have calculated will be bogus if this is
12405 a forward branch to another frag, as the forward frag
12406 will have fr_address == 0. */
12410 /* In this case, we know for sure that the symbol fragment is in
12411 the same section. If the relax_marker of the symbol fragment
12412 differs from the relax_marker of this fragment, we have not
12413 yet adjusted the symbol fragment fr_address. We want to add
12414 in STRETCH in order to get a better estimate of the address.
12415 This particularly matters because of the shift bits. */
12417 && sym_frag
->relax_marker
!= fragp
->relax_marker
)
12421 /* Adjust stretch for any alignment frag. Note that if have
12422 been expanding the earlier code, the symbol may be
12423 defined in what appears to be an earlier frag. FIXME:
12424 This doesn't handle the fr_subtype field, which specifies
12425 a maximum number of bytes to skip when doing an
12427 for (f
= fragp
; f
!= NULL
&& f
!= sym_frag
; f
= f
->fr_next
)
12429 if (f
->fr_type
== rs_align
|| f
->fr_type
== rs_align_code
)
12432 stretch
= - ((- stretch
)
12433 & ~ ((1 << (int) f
->fr_offset
) - 1));
12435 stretch
&= ~ ((1 << (int) f
->fr_offset
) - 1);
12444 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
12446 /* The base address rules are complicated. The base address of
12447 a branch is the following instruction. The base address of a
12448 PC relative load or add is the instruction itself, but if it
12449 is in a delay slot (in which case it can not be extended) use
12450 the address of the instruction whose delay slot it is in. */
12451 if (type
== 'p' || type
== 'q')
12455 /* If we are currently assuming that this frag should be
12456 extended, then, the current address is two bytes
12458 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
12461 /* Ignore the low bit in the target, since it will be set
12462 for a text label. */
12463 if ((val
& 1) != 0)
12466 else if (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
))
12468 else if (RELAX_MIPS16_DSLOT (fragp
->fr_subtype
))
12471 val
-= addr
& ~ ((1 << op
->shift
) - 1);
12473 /* Branch offsets have an implicit 0 in the lowest bit. */
12474 if (type
== 'p' || type
== 'q')
12477 /* If any of the shifted bits are set, we must use an extended
12478 opcode. If the address depends on the size of this
12479 instruction, this can lead to a loop, so we arrange to always
12480 use an extended opcode. We only check this when we are in
12481 the main relaxation loop, when SEC is NULL. */
12482 if ((val
& ((1 << op
->shift
) - 1)) != 0 && sec
== NULL
)
12484 fragp
->fr_subtype
=
12485 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
12489 /* If we are about to mark a frag as extended because the value
12490 is precisely maxtiny + 1, then there is a chance of an
12491 infinite loop as in the following code:
12496 In this case when the la is extended, foo is 0x3fc bytes
12497 away, so the la can be shrunk, but then foo is 0x400 away, so
12498 the la must be extended. To avoid this loop, we mark the
12499 frag as extended if it was small, and is about to become
12500 extended with a value of maxtiny + 1. */
12501 if (val
== ((maxtiny
+ 1) << op
->shift
)
12502 && ! RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
)
12505 fragp
->fr_subtype
=
12506 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
12510 else if (symsec
!= absolute_section
&& sec
!= NULL
)
12511 as_bad_where (fragp
->fr_file
, fragp
->fr_line
, _("unsupported relocation"));
12513 if ((val
& ((1 << op
->shift
) - 1)) != 0
12514 || val
< (mintiny
<< op
->shift
)
12515 || val
> (maxtiny
<< op
->shift
))
12521 /* Compute the length of a branch sequence, and adjust the
12522 RELAX_BRANCH_TOOFAR bit accordingly. If FRAGP is NULL, the
12523 worst-case length is computed, with UPDATE being used to indicate
12524 whether an unconditional (-1), branch-likely (+1) or regular (0)
12525 branch is to be computed. */
12527 relaxed_branch_length (fragS
*fragp
, asection
*sec
, int update
)
12529 bfd_boolean toofar
;
12533 && S_IS_DEFINED (fragp
->fr_symbol
)
12534 && sec
== S_GET_SEGMENT (fragp
->fr_symbol
))
12539 val
= S_GET_VALUE (fragp
->fr_symbol
) + fragp
->fr_offset
;
12541 addr
= fragp
->fr_address
+ fragp
->fr_fix
+ 4;
12545 toofar
= val
< - (0x8000 << 2) || val
>= (0x8000 << 2);
12548 /* If the symbol is not defined or it's in a different segment,
12549 assume the user knows what's going on and emit a short
12555 if (fragp
&& update
&& toofar
!= RELAX_BRANCH_TOOFAR (fragp
->fr_subtype
))
12557 = RELAX_BRANCH_ENCODE (RELAX_BRANCH_UNCOND (fragp
->fr_subtype
),
12558 RELAX_BRANCH_LIKELY (fragp
->fr_subtype
),
12559 RELAX_BRANCH_LINK (fragp
->fr_subtype
),
12565 if (fragp
? RELAX_BRANCH_LIKELY (fragp
->fr_subtype
) : (update
> 0))
12568 if (mips_pic
!= NO_PIC
)
12570 /* Additional space for PIC loading of target address. */
12572 if (mips_opts
.isa
== ISA_MIPS1
)
12573 /* Additional space for $at-stabilizing nop. */
12577 /* If branch is conditional. */
12578 if (fragp
? !RELAX_BRANCH_UNCOND (fragp
->fr_subtype
) : (update
>= 0))
12585 /* Estimate the size of a frag before relaxing. Unless this is the
12586 mips16, we are not really relaxing here, and the final size is
12587 encoded in the subtype information. For the mips16, we have to
12588 decide whether we are using an extended opcode or not. */
12591 md_estimate_size_before_relax (fragS
*fragp
, asection
*segtype
)
12595 if (RELAX_BRANCH_P (fragp
->fr_subtype
))
12598 fragp
->fr_var
= relaxed_branch_length (fragp
, segtype
, FALSE
);
12600 return fragp
->fr_var
;
12603 if (RELAX_MIPS16_P (fragp
->fr_subtype
))
12604 /* We don't want to modify the EXTENDED bit here; it might get us
12605 into infinite loops. We change it only in mips_relax_frag(). */
12606 return (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
) ? 4 : 2);
12608 if (mips_pic
== NO_PIC
)
12609 change
= nopic_need_relax (fragp
->fr_symbol
, 0);
12610 else if (mips_pic
== SVR4_PIC
)
12611 change
= pic_need_relax (fragp
->fr_symbol
, segtype
);
12617 fragp
->fr_subtype
|= RELAX_USE_SECOND
;
12618 return -RELAX_FIRST (fragp
->fr_subtype
);
12621 return -RELAX_SECOND (fragp
->fr_subtype
);
12624 /* This is called to see whether a reloc against a defined symbol
12625 should be converted into a reloc against a section. */
12628 mips_fix_adjustable (fixS
*fixp
)
12630 /* Don't adjust MIPS16 jump relocations, so we don't have to worry
12631 about the format of the offset in the .o file. */
12632 if (fixp
->fx_r_type
== BFD_RELOC_MIPS16_JMP
)
12635 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
12636 || fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
12639 if (fixp
->fx_addsy
== NULL
)
12642 /* If symbol SYM is in a mergeable section, relocations of the form
12643 SYM + 0 can usually be made section-relative. The mergeable data
12644 is then identified by the section offset rather than by the symbol.
12646 However, if we're generating REL LO16 relocations, the offset is split
12647 between the LO16 and parterning high part relocation. The linker will
12648 need to recalculate the complete offset in order to correctly identify
12651 The linker has traditionally not looked for the parterning high part
12652 relocation, and has thus allowed orphaned R_MIPS_LO16 relocations to be
12653 placed anywhere. Rather than break backwards compatibility by changing
12654 this, it seems better not to force the issue, and instead keep the
12655 original symbol. This will work with either linker behavior. */
12656 if ((fixp
->fx_r_type
== BFD_RELOC_LO16
|| reloc_needs_lo_p (fixp
->fx_r_type
))
12657 && HAVE_IN_PLACE_ADDENDS
12658 && (S_GET_SEGMENT (fixp
->fx_addsy
)->flags
& SEC_MERGE
) != 0)
12662 /* Don't adjust relocations against mips16 symbols, so that the linker
12663 can find them if it needs to set up a stub. */
12664 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
12665 && S_GET_OTHER (fixp
->fx_addsy
) == STO_MIPS16
12666 && fixp
->fx_subsy
== NULL
)
12673 /* Translate internal representation of relocation info to BFD target
12677 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
, fixS
*fixp
)
12679 static arelent
*retval
[4];
12681 bfd_reloc_code_real_type code
;
12683 memset (retval
, 0, sizeof(retval
));
12684 reloc
= retval
[0] = (arelent
*) xcalloc (1, sizeof (arelent
));
12685 reloc
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
12686 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
12687 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
12689 assert (! fixp
->fx_pcrel
);
12690 reloc
->addend
= fixp
->fx_addnumber
;
12692 /* Since the old MIPS ELF ABI uses Rel instead of Rela, encode the vtable
12693 entry to be used in the relocation's section offset. */
12694 if (! HAVE_NEWABI
&& fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
12696 reloc
->address
= reloc
->addend
;
12700 code
= fixp
->fx_r_type
;
12702 /* To support a PC relative reloc, we used a Cygnus extension.
12703 We check for that here to make sure that we don't let such a
12704 reloc escape normally. (FIXME: This was formerly used by
12705 embedded-PIC support, but is now used by branch handling in
12706 general. That probably should be fixed.) */
12707 if ((OUTPUT_FLAVOR
== bfd_target_ecoff_flavour
12708 || OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
12709 && code
== BFD_RELOC_16_PCREL_S2
)
12710 reloc
->howto
= NULL
;
12712 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
12714 if (reloc
->howto
== NULL
)
12716 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
12717 _("Can not represent %s relocation in this object file format"),
12718 bfd_get_reloc_code_name (code
));
12725 /* Relax a machine dependent frag. This returns the amount by which
12726 the current size of the frag should change. */
12729 mips_relax_frag (asection
*sec
, fragS
*fragp
, long stretch
)
12731 if (RELAX_BRANCH_P (fragp
->fr_subtype
))
12733 offsetT old_var
= fragp
->fr_var
;
12735 fragp
->fr_var
= relaxed_branch_length (fragp
, sec
, TRUE
);
12737 return fragp
->fr_var
- old_var
;
12740 if (! RELAX_MIPS16_P (fragp
->fr_subtype
))
12743 if (mips16_extended_frag (fragp
, NULL
, stretch
))
12745 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
12747 fragp
->fr_subtype
= RELAX_MIPS16_MARK_EXTENDED (fragp
->fr_subtype
);
12752 if (! RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
12754 fragp
->fr_subtype
= RELAX_MIPS16_CLEAR_EXTENDED (fragp
->fr_subtype
);
12761 /* Convert a machine dependent frag. */
12764 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
, segT asec
, fragS
*fragp
)
12766 if (RELAX_BRANCH_P (fragp
->fr_subtype
))
12769 unsigned long insn
;
12773 buf
= (bfd_byte
*)fragp
->fr_literal
+ fragp
->fr_fix
;
12775 if (target_big_endian
)
12776 insn
= bfd_getb32 (buf
);
12778 insn
= bfd_getl32 (buf
);
12780 if (!RELAX_BRANCH_TOOFAR (fragp
->fr_subtype
))
12782 /* We generate a fixup instead of applying it right now
12783 because, if there are linker relaxations, we're going to
12784 need the relocations. */
12785 exp
.X_op
= O_symbol
;
12786 exp
.X_add_symbol
= fragp
->fr_symbol
;
12787 exp
.X_add_number
= fragp
->fr_offset
;
12789 fixp
= fix_new_exp (fragp
, buf
- (bfd_byte
*)fragp
->fr_literal
,
12791 BFD_RELOC_16_PCREL_S2
);
12792 fixp
->fx_file
= fragp
->fr_file
;
12793 fixp
->fx_line
= fragp
->fr_line
;
12795 md_number_to_chars ((char *) buf
, insn
, 4);
12802 as_warn_where (fragp
->fr_file
, fragp
->fr_line
,
12803 _("relaxed out-of-range branch into a jump"));
12805 if (RELAX_BRANCH_UNCOND (fragp
->fr_subtype
))
12808 if (!RELAX_BRANCH_LIKELY (fragp
->fr_subtype
))
12810 /* Reverse the branch. */
12811 switch ((insn
>> 28) & 0xf)
12814 /* bc[0-3][tf]l? and bc1any[24][ft] instructions can
12815 have the condition reversed by tweaking a single
12816 bit, and their opcodes all have 0x4???????. */
12817 assert ((insn
& 0xf1000000) == 0x41000000);
12818 insn
^= 0x00010000;
12822 /* bltz 0x04000000 bgez 0x04010000
12823 bltzal 0x04100000 bgezal 0x04110000 */
12824 assert ((insn
& 0xfc0e0000) == 0x04000000);
12825 insn
^= 0x00010000;
12829 /* beq 0x10000000 bne 0x14000000
12830 blez 0x18000000 bgtz 0x1c000000 */
12831 insn
^= 0x04000000;
12839 if (RELAX_BRANCH_LINK (fragp
->fr_subtype
))
12841 /* Clear the and-link bit. */
12842 assert ((insn
& 0xfc1c0000) == 0x04100000);
12844 /* bltzal 0x04100000 bgezal 0x04110000
12845 bltzall 0x04120000 bgezall 0x04130000 */
12846 insn
&= ~0x00100000;
12849 /* Branch over the branch (if the branch was likely) or the
12850 full jump (not likely case). Compute the offset from the
12851 current instruction to branch to. */
12852 if (RELAX_BRANCH_LIKELY (fragp
->fr_subtype
))
12856 /* How many bytes in instructions we've already emitted? */
12857 i
= buf
- (bfd_byte
*)fragp
->fr_literal
- fragp
->fr_fix
;
12858 /* How many bytes in instructions from here to the end? */
12859 i
= fragp
->fr_var
- i
;
12861 /* Convert to instruction count. */
12863 /* Branch counts from the next instruction. */
12866 /* Branch over the jump. */
12867 md_number_to_chars ((char *) buf
, insn
, 4);
12871 md_number_to_chars ((char *) buf
, 0, 4);
12874 if (RELAX_BRANCH_LIKELY (fragp
->fr_subtype
))
12876 /* beql $0, $0, 2f */
12878 /* Compute the PC offset from the current instruction to
12879 the end of the variable frag. */
12880 /* How many bytes in instructions we've already emitted? */
12881 i
= buf
- (bfd_byte
*)fragp
->fr_literal
- fragp
->fr_fix
;
12882 /* How many bytes in instructions from here to the end? */
12883 i
= fragp
->fr_var
- i
;
12884 /* Convert to instruction count. */
12886 /* Don't decrement i, because we want to branch over the
12890 md_number_to_chars ((char *) buf
, insn
, 4);
12893 md_number_to_chars ((char *) buf
, 0, 4);
12898 if (mips_pic
== NO_PIC
)
12901 insn
= (RELAX_BRANCH_LINK (fragp
->fr_subtype
)
12902 ? 0x0c000000 : 0x08000000);
12903 exp
.X_op
= O_symbol
;
12904 exp
.X_add_symbol
= fragp
->fr_symbol
;
12905 exp
.X_add_number
= fragp
->fr_offset
;
12907 fixp
= fix_new_exp (fragp
, buf
- (bfd_byte
*)fragp
->fr_literal
,
12908 4, &exp
, 0, BFD_RELOC_MIPS_JMP
);
12909 fixp
->fx_file
= fragp
->fr_file
;
12910 fixp
->fx_line
= fragp
->fr_line
;
12912 md_number_to_chars ((char *) buf
, insn
, 4);
12917 /* lw/ld $at, <sym>($gp) R_MIPS_GOT16 */
12918 insn
= HAVE_64BIT_ADDRESSES
? 0xdf810000 : 0x8f810000;
12919 exp
.X_op
= O_symbol
;
12920 exp
.X_add_symbol
= fragp
->fr_symbol
;
12921 exp
.X_add_number
= fragp
->fr_offset
;
12923 if (fragp
->fr_offset
)
12925 exp
.X_add_symbol
= make_expr_symbol (&exp
);
12926 exp
.X_add_number
= 0;
12929 fixp
= fix_new_exp (fragp
, buf
- (bfd_byte
*)fragp
->fr_literal
,
12930 4, &exp
, 0, BFD_RELOC_MIPS_GOT16
);
12931 fixp
->fx_file
= fragp
->fr_file
;
12932 fixp
->fx_line
= fragp
->fr_line
;
12934 md_number_to_chars ((char *) buf
, insn
, 4);
12937 if (mips_opts
.isa
== ISA_MIPS1
)
12940 md_number_to_chars ((char *) buf
, 0, 4);
12944 /* d/addiu $at, $at, <sym> R_MIPS_LO16 */
12945 insn
= HAVE_64BIT_ADDRESSES
? 0x64210000 : 0x24210000;
12947 fixp
= fix_new_exp (fragp
, buf
- (bfd_byte
*)fragp
->fr_literal
,
12948 4, &exp
, 0, BFD_RELOC_LO16
);
12949 fixp
->fx_file
= fragp
->fr_file
;
12950 fixp
->fx_line
= fragp
->fr_line
;
12952 md_number_to_chars ((char *) buf
, insn
, 4);
12956 if (RELAX_BRANCH_LINK (fragp
->fr_subtype
))
12961 md_number_to_chars ((char *) buf
, insn
, 4);
12966 assert (buf
== (bfd_byte
*)fragp
->fr_literal
12967 + fragp
->fr_fix
+ fragp
->fr_var
);
12969 fragp
->fr_fix
+= fragp
->fr_var
;
12974 if (RELAX_MIPS16_P (fragp
->fr_subtype
))
12977 register const struct mips16_immed_operand
*op
;
12978 bfd_boolean small
, ext
;
12981 unsigned long insn
;
12982 bfd_boolean use_extend
;
12983 unsigned short extend
;
12985 type
= RELAX_MIPS16_TYPE (fragp
->fr_subtype
);
12986 op
= mips16_immed_operands
;
12987 while (op
->type
!= type
)
12990 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
13001 resolve_symbol_value (fragp
->fr_symbol
);
13002 val
= S_GET_VALUE (fragp
->fr_symbol
);
13007 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
13009 /* The rules for the base address of a PC relative reloc are
13010 complicated; see mips16_extended_frag. */
13011 if (type
== 'p' || type
== 'q')
13016 /* Ignore the low bit in the target, since it will be
13017 set for a text label. */
13018 if ((val
& 1) != 0)
13021 else if (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
))
13023 else if (RELAX_MIPS16_DSLOT (fragp
->fr_subtype
))
13026 addr
&= ~ (addressT
) ((1 << op
->shift
) - 1);
13029 /* Make sure the section winds up with the alignment we have
13032 record_alignment (asec
, op
->shift
);
13036 && (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
)
13037 || RELAX_MIPS16_DSLOT (fragp
->fr_subtype
)))
13038 as_warn_where (fragp
->fr_file
, fragp
->fr_line
,
13039 _("extended instruction in delay slot"));
13041 buf
= (bfd_byte
*) (fragp
->fr_literal
+ fragp
->fr_fix
);
13043 if (target_big_endian
)
13044 insn
= bfd_getb16 (buf
);
13046 insn
= bfd_getl16 (buf
);
13048 mips16_immed (fragp
->fr_file
, fragp
->fr_line
, type
, val
,
13049 RELAX_MIPS16_USER_EXT (fragp
->fr_subtype
),
13050 small
, ext
, &insn
, &use_extend
, &extend
);
13054 md_number_to_chars ((char *) buf
, 0xf000 | extend
, 2);
13055 fragp
->fr_fix
+= 2;
13059 md_number_to_chars ((char *) buf
, insn
, 2);
13060 fragp
->fr_fix
+= 2;
13068 first
= RELAX_FIRST (fragp
->fr_subtype
);
13069 second
= RELAX_SECOND (fragp
->fr_subtype
);
13070 fixp
= (fixS
*) fragp
->fr_opcode
;
13072 /* Possibly emit a warning if we've chosen the longer option. */
13073 if (((fragp
->fr_subtype
& RELAX_USE_SECOND
) != 0)
13074 == ((fragp
->fr_subtype
& RELAX_SECOND_LONGER
) != 0))
13076 const char *msg
= macro_warning (fragp
->fr_subtype
);
13078 as_warn_where (fragp
->fr_file
, fragp
->fr_line
, msg
);
13081 /* Go through all the fixups for the first sequence. Disable them
13082 (by marking them as done) if we're going to use the second
13083 sequence instead. */
13085 && fixp
->fx_frag
== fragp
13086 && fixp
->fx_where
< fragp
->fr_fix
- second
)
13088 if (fragp
->fr_subtype
& RELAX_USE_SECOND
)
13090 fixp
= fixp
->fx_next
;
13093 /* Go through the fixups for the second sequence. Disable them if
13094 we're going to use the first sequence, otherwise adjust their
13095 addresses to account for the relaxation. */
13096 while (fixp
&& fixp
->fx_frag
== fragp
)
13098 if (fragp
->fr_subtype
& RELAX_USE_SECOND
)
13099 fixp
->fx_where
-= first
;
13102 fixp
= fixp
->fx_next
;
13105 /* Now modify the frag contents. */
13106 if (fragp
->fr_subtype
& RELAX_USE_SECOND
)
13110 start
= fragp
->fr_literal
+ fragp
->fr_fix
- first
- second
;
13111 memmove (start
, start
+ first
, second
);
13112 fragp
->fr_fix
-= first
;
13115 fragp
->fr_fix
-= second
;
13121 /* This function is called after the relocs have been generated.
13122 We've been storing mips16 text labels as odd. Here we convert them
13123 back to even for the convenience of the debugger. */
13126 mips_frob_file_after_relocs (void)
13129 unsigned int count
, i
;
13131 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
13134 syms
= bfd_get_outsymbols (stdoutput
);
13135 count
= bfd_get_symcount (stdoutput
);
13136 for (i
= 0; i
< count
; i
++, syms
++)
13138 if (elf_symbol (*syms
)->internal_elf_sym
.st_other
== STO_MIPS16
13139 && ((*syms
)->value
& 1) != 0)
13141 (*syms
)->value
&= ~1;
13142 /* If the symbol has an odd size, it was probably computed
13143 incorrectly, so adjust that as well. */
13144 if ((elf_symbol (*syms
)->internal_elf_sym
.st_size
& 1) != 0)
13145 ++elf_symbol (*syms
)->internal_elf_sym
.st_size
;
13152 /* This function is called whenever a label is defined. It is used
13153 when handling branch delays; if a branch has a label, we assume we
13154 can not move it. */
13157 mips_define_label (symbolS
*sym
)
13159 struct insn_label_list
*l
;
13161 if (free_insn_labels
== NULL
)
13162 l
= (struct insn_label_list
*) xmalloc (sizeof *l
);
13165 l
= free_insn_labels
;
13166 free_insn_labels
= l
->next
;
13170 l
->next
= insn_labels
;
13174 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13176 /* Some special processing for a MIPS ELF file. */
13179 mips_elf_final_processing (void)
13181 /* Write out the register information. */
13182 if (mips_abi
!= N64_ABI
)
13186 s
.ri_gprmask
= mips_gprmask
;
13187 s
.ri_cprmask
[0] = mips_cprmask
[0];
13188 s
.ri_cprmask
[1] = mips_cprmask
[1];
13189 s
.ri_cprmask
[2] = mips_cprmask
[2];
13190 s
.ri_cprmask
[3] = mips_cprmask
[3];
13191 /* The gp_value field is set by the MIPS ELF backend. */
13193 bfd_mips_elf32_swap_reginfo_out (stdoutput
, &s
,
13194 ((Elf32_External_RegInfo
*)
13195 mips_regmask_frag
));
13199 Elf64_Internal_RegInfo s
;
13201 s
.ri_gprmask
= mips_gprmask
;
13203 s
.ri_cprmask
[0] = mips_cprmask
[0];
13204 s
.ri_cprmask
[1] = mips_cprmask
[1];
13205 s
.ri_cprmask
[2] = mips_cprmask
[2];
13206 s
.ri_cprmask
[3] = mips_cprmask
[3];
13207 /* The gp_value field is set by the MIPS ELF backend. */
13209 bfd_mips_elf64_swap_reginfo_out (stdoutput
, &s
,
13210 ((Elf64_External_RegInfo
*)
13211 mips_regmask_frag
));
13214 /* Set the MIPS ELF flag bits. FIXME: There should probably be some
13215 sort of BFD interface for this. */
13216 if (mips_any_noreorder
)
13217 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_NOREORDER
;
13218 if (mips_pic
!= NO_PIC
)
13220 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_PIC
;
13221 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_CPIC
;
13224 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_CPIC
;
13226 /* Set MIPS ELF flags for ASEs. */
13227 if (file_ase_mips16
)
13228 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ARCH_ASE_M16
;
13229 #if 0 /* XXX FIXME */
13230 if (file_ase_mips3d
)
13231 elf_elfheader (stdoutput
)->e_flags
|= ???;
13234 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ARCH_ASE_MDMX
;
13236 /* Set the MIPS ELF ABI flags. */
13237 if (mips_abi
== O32_ABI
&& USE_E_MIPS_ABI_O32
)
13238 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_O32
;
13239 else if (mips_abi
== O64_ABI
)
13240 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_O64
;
13241 else if (mips_abi
== EABI_ABI
)
13243 if (!file_mips_gp32
)
13244 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_EABI64
;
13246 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_EABI32
;
13248 else if (mips_abi
== N32_ABI
)
13249 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ABI2
;
13251 /* Nothing to do for N64_ABI. */
13253 if (mips_32bitmode
)
13254 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_32BITMODE
;
13257 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */
13259 typedef struct proc
{
13261 symbolS
*func_end_sym
;
13262 unsigned long reg_mask
;
13263 unsigned long reg_offset
;
13264 unsigned long fpreg_mask
;
13265 unsigned long fpreg_offset
;
13266 unsigned long frame_offset
;
13267 unsigned long frame_reg
;
13268 unsigned long pc_reg
;
13271 static procS cur_proc
;
13272 static procS
*cur_proc_ptr
;
13273 static int numprocs
;
13275 /* Fill in an rs_align_code fragment. */
13278 mips_handle_align (fragS
*fragp
)
13280 if (fragp
->fr_type
!= rs_align_code
)
13283 if (mips_opts
.mips16
)
13285 static const unsigned char be_nop
[] = { 0x65, 0x00 };
13286 static const unsigned char le_nop
[] = { 0x00, 0x65 };
13291 bytes
= fragp
->fr_next
->fr_address
- fragp
->fr_address
- fragp
->fr_fix
;
13292 p
= fragp
->fr_literal
+ fragp
->fr_fix
;
13300 memcpy (p
, (target_big_endian
? be_nop
: le_nop
), 2);
13304 /* For mips32, a nop is a zero, which we trivially get by doing nothing. */
13308 md_obj_begin (void)
13315 /* check for premature end, nesting errors, etc */
13317 as_warn (_("missing .end at end of assembly"));
13326 if (*input_line_pointer
== '-')
13328 ++input_line_pointer
;
13331 if (!ISDIGIT (*input_line_pointer
))
13332 as_bad (_("expected simple number"));
13333 if (input_line_pointer
[0] == '0')
13335 if (input_line_pointer
[1] == 'x')
13337 input_line_pointer
+= 2;
13338 while (ISXDIGIT (*input_line_pointer
))
13341 val
|= hex_value (*input_line_pointer
++);
13343 return negative
? -val
: val
;
13347 ++input_line_pointer
;
13348 while (ISDIGIT (*input_line_pointer
))
13351 val
|= *input_line_pointer
++ - '0';
13353 return negative
? -val
: val
;
13356 if (!ISDIGIT (*input_line_pointer
))
13358 printf (_(" *input_line_pointer == '%c' 0x%02x\n"),
13359 *input_line_pointer
, *input_line_pointer
);
13360 as_warn (_("invalid number"));
13363 while (ISDIGIT (*input_line_pointer
))
13366 val
+= *input_line_pointer
++ - '0';
13368 return negative
? -val
: val
;
13371 /* The .file directive; just like the usual .file directive, but there
13372 is an initial number which is the ECOFF file index. In the non-ECOFF
13373 case .file implies DWARF-2. */
13376 s_mips_file (int x ATTRIBUTE_UNUSED
)
13378 static int first_file_directive
= 0;
13380 if (ECOFF_DEBUGGING
)
13389 filename
= dwarf2_directive_file (0);
13391 /* Versions of GCC up to 3.1 start files with a ".file"
13392 directive even for stabs output. Make sure that this
13393 ".file" is handled. Note that you need a version of GCC
13394 after 3.1 in order to support DWARF-2 on MIPS. */
13395 if (filename
!= NULL
&& ! first_file_directive
)
13397 (void) new_logical_line (filename
, -1);
13398 s_app_file_string (filename
, 0);
13400 first_file_directive
= 1;
13404 /* The .loc directive, implying DWARF-2. */
13407 s_mips_loc (int x ATTRIBUTE_UNUSED
)
13409 if (!ECOFF_DEBUGGING
)
13410 dwarf2_directive_loc (0);
13413 /* The .end directive. */
13416 s_mips_end (int x ATTRIBUTE_UNUSED
)
13420 /* Following functions need their own .frame and .cprestore directives. */
13421 mips_frame_reg_valid
= 0;
13422 mips_cprestore_valid
= 0;
13424 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
13427 demand_empty_rest_of_line ();
13432 if ((bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) == 0)
13433 as_warn (_(".end not in text section"));
13437 as_warn (_(".end directive without a preceding .ent directive."));
13438 demand_empty_rest_of_line ();
13444 assert (S_GET_NAME (p
));
13445 if (strcmp (S_GET_NAME (p
), S_GET_NAME (cur_proc_ptr
->func_sym
)))
13446 as_warn (_(".end symbol does not match .ent symbol."));
13448 if (debug_type
== DEBUG_STABS
)
13449 stabs_generate_asm_endfunc (S_GET_NAME (p
),
13453 as_warn (_(".end directive missing or unknown symbol"));
13456 /* Create an expression to calculate the size of the function. */
13457 if (p
&& cur_proc_ptr
)
13459 OBJ_SYMFIELD_TYPE
*obj
= symbol_get_obj (p
);
13460 expressionS
*exp
= xmalloc (sizeof (expressionS
));
13463 exp
->X_op
= O_subtract
;
13464 exp
->X_add_symbol
= symbol_temp_new_now ();
13465 exp
->X_op_symbol
= p
;
13466 exp
->X_add_number
= 0;
13468 cur_proc_ptr
->func_end_sym
= exp
->X_add_symbol
;
13471 /* Generate a .pdr section. */
13472 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
&& ! ECOFF_DEBUGGING
13475 segT saved_seg
= now_seg
;
13476 subsegT saved_subseg
= now_subseg
;
13481 dot
= frag_now_fix ();
13483 #ifdef md_flush_pending_output
13484 md_flush_pending_output ();
13488 subseg_set (pdr_seg
, 0);
13490 /* Write the symbol. */
13491 exp
.X_op
= O_symbol
;
13492 exp
.X_add_symbol
= p
;
13493 exp
.X_add_number
= 0;
13494 emit_expr (&exp
, 4);
13496 fragp
= frag_more (7 * 4);
13498 md_number_to_chars (fragp
, cur_proc_ptr
->reg_mask
, 4);
13499 md_number_to_chars (fragp
+ 4, cur_proc_ptr
->reg_offset
, 4);
13500 md_number_to_chars (fragp
+ 8, cur_proc_ptr
->fpreg_mask
, 4);
13501 md_number_to_chars (fragp
+ 12, cur_proc_ptr
->fpreg_offset
, 4);
13502 md_number_to_chars (fragp
+ 16, cur_proc_ptr
->frame_offset
, 4);
13503 md_number_to_chars (fragp
+ 20, cur_proc_ptr
->frame_reg
, 4);
13504 md_number_to_chars (fragp
+ 24, cur_proc_ptr
->pc_reg
, 4);
13506 subseg_set (saved_seg
, saved_subseg
);
13508 #endif /* OBJ_ELF */
13510 cur_proc_ptr
= NULL
;
13513 /* The .aent and .ent directives. */
13516 s_mips_ent (int aent
)
13520 symbolP
= get_symbol ();
13521 if (*input_line_pointer
== ',')
13522 ++input_line_pointer
;
13523 SKIP_WHITESPACE ();
13524 if (ISDIGIT (*input_line_pointer
)
13525 || *input_line_pointer
== '-')
13528 if ((bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) == 0)
13529 as_warn (_(".ent or .aent not in text section."));
13531 if (!aent
&& cur_proc_ptr
)
13532 as_warn (_("missing .end"));
13536 /* This function needs its own .frame and .cprestore directives. */
13537 mips_frame_reg_valid
= 0;
13538 mips_cprestore_valid
= 0;
13540 cur_proc_ptr
= &cur_proc
;
13541 memset (cur_proc_ptr
, '\0', sizeof (procS
));
13543 cur_proc_ptr
->func_sym
= symbolP
;
13545 symbol_get_bfdsym (symbolP
)->flags
|= BSF_FUNCTION
;
13549 if (debug_type
== DEBUG_STABS
)
13550 stabs_generate_asm_func (S_GET_NAME (symbolP
),
13551 S_GET_NAME (symbolP
));
13554 demand_empty_rest_of_line ();
13557 /* The .frame directive. If the mdebug section is present (IRIX 5 native)
13558 then ecoff.c (ecoff_directive_frame) is used. For embedded targets,
13559 s_mips_frame is used so that we can set the PDR information correctly.
13560 We can't use the ecoff routines because they make reference to the ecoff
13561 symbol table (in the mdebug section). */
13564 s_mips_frame (int ignore ATTRIBUTE_UNUSED
)
13567 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
&& ! ECOFF_DEBUGGING
)
13571 if (cur_proc_ptr
== (procS
*) NULL
)
13573 as_warn (_(".frame outside of .ent"));
13574 demand_empty_rest_of_line ();
13578 cur_proc_ptr
->frame_reg
= tc_get_register (1);
13580 SKIP_WHITESPACE ();
13581 if (*input_line_pointer
++ != ','
13582 || get_absolute_expression_and_terminator (&val
) != ',')
13584 as_warn (_("Bad .frame directive"));
13585 --input_line_pointer
;
13586 demand_empty_rest_of_line ();
13590 cur_proc_ptr
->frame_offset
= val
;
13591 cur_proc_ptr
->pc_reg
= tc_get_register (0);
13593 demand_empty_rest_of_line ();
13596 #endif /* OBJ_ELF */
13600 /* The .fmask and .mask directives. If the mdebug section is present
13601 (IRIX 5 native) then ecoff.c (ecoff_directive_mask) is used. For
13602 embedded targets, s_mips_mask is used so that we can set the PDR
13603 information correctly. We can't use the ecoff routines because they
13604 make reference to the ecoff symbol table (in the mdebug section). */
13607 s_mips_mask (int reg_type
)
13610 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
&& ! ECOFF_DEBUGGING
)
13614 if (cur_proc_ptr
== (procS
*) NULL
)
13616 as_warn (_(".mask/.fmask outside of .ent"));
13617 demand_empty_rest_of_line ();
13621 if (get_absolute_expression_and_terminator (&mask
) != ',')
13623 as_warn (_("Bad .mask/.fmask directive"));
13624 --input_line_pointer
;
13625 demand_empty_rest_of_line ();
13629 off
= get_absolute_expression ();
13631 if (reg_type
== 'F')
13633 cur_proc_ptr
->fpreg_mask
= mask
;
13634 cur_proc_ptr
->fpreg_offset
= off
;
13638 cur_proc_ptr
->reg_mask
= mask
;
13639 cur_proc_ptr
->reg_offset
= off
;
13642 demand_empty_rest_of_line ();
13645 #endif /* OBJ_ELF */
13646 s_ignore (reg_type
);
13649 /* A table describing all the processors gas knows about. Names are
13650 matched in the order listed.
13652 To ease comparison, please keep this table in the same order as
13653 gcc's mips_cpu_info_table[]. */
13654 static const struct mips_cpu_info mips_cpu_info_table
[] =
13656 /* Entries for generic ISAs */
13657 { "mips1", 1, ISA_MIPS1
, CPU_R3000
},
13658 { "mips2", 1, ISA_MIPS2
, CPU_R6000
},
13659 { "mips3", 1, ISA_MIPS3
, CPU_R4000
},
13660 { "mips4", 1, ISA_MIPS4
, CPU_R8000
},
13661 { "mips5", 1, ISA_MIPS5
, CPU_MIPS5
},
13662 { "mips32", 1, ISA_MIPS32
, CPU_MIPS32
},
13663 { "mips32r2", 1, ISA_MIPS32R2
, CPU_MIPS32R2
},
13664 { "mips64", 1, ISA_MIPS64
, CPU_MIPS64
},
13665 { "mips64r2", 1, ISA_MIPS64R2
, CPU_MIPS64R2
},
13668 { "r3000", 0, ISA_MIPS1
, CPU_R3000
},
13669 { "r2000", 0, ISA_MIPS1
, CPU_R3000
},
13670 { "r3900", 0, ISA_MIPS1
, CPU_R3900
},
13673 { "r6000", 0, ISA_MIPS2
, CPU_R6000
},
13676 { "r4000", 0, ISA_MIPS3
, CPU_R4000
},
13677 { "r4010", 0, ISA_MIPS2
, CPU_R4010
},
13678 { "vr4100", 0, ISA_MIPS3
, CPU_VR4100
},
13679 { "vr4111", 0, ISA_MIPS3
, CPU_R4111
},
13680 { "vr4120", 0, ISA_MIPS3
, CPU_VR4120
},
13681 { "vr4130", 0, ISA_MIPS3
, CPU_VR4120
},
13682 { "vr4181", 0, ISA_MIPS3
, CPU_R4111
},
13683 { "vr4300", 0, ISA_MIPS3
, CPU_R4300
},
13684 { "r4400", 0, ISA_MIPS3
, CPU_R4400
},
13685 { "r4600", 0, ISA_MIPS3
, CPU_R4600
},
13686 { "orion", 0, ISA_MIPS3
, CPU_R4600
},
13687 { "r4650", 0, ISA_MIPS3
, CPU_R4650
},
13690 { "r8000", 0, ISA_MIPS4
, CPU_R8000
},
13691 { "r10000", 0, ISA_MIPS4
, CPU_R10000
},
13692 { "r12000", 0, ISA_MIPS4
, CPU_R12000
},
13693 { "vr5000", 0, ISA_MIPS4
, CPU_R5000
},
13694 { "vr5400", 0, ISA_MIPS4
, CPU_VR5400
},
13695 { "vr5500", 0, ISA_MIPS4
, CPU_VR5500
},
13696 { "rm5200", 0, ISA_MIPS4
, CPU_R5000
},
13697 { "rm5230", 0, ISA_MIPS4
, CPU_R5000
},
13698 { "rm5231", 0, ISA_MIPS4
, CPU_R5000
},
13699 { "rm5261", 0, ISA_MIPS4
, CPU_R5000
},
13700 { "rm5721", 0, ISA_MIPS4
, CPU_R5000
},
13701 { "rm7000", 0, ISA_MIPS4
, CPU_RM7000
},
13702 { "rm9000", 0, ISA_MIPS4
, CPU_RM9000
},
13705 { "4kc", 0, ISA_MIPS32
, CPU_MIPS32
},
13706 { "4km", 0, ISA_MIPS32
, CPU_MIPS32
},
13707 { "4kp", 0, ISA_MIPS32
, CPU_MIPS32
},
13710 { "5kc", 0, ISA_MIPS64
, CPU_MIPS64
},
13711 { "20kc", 0, ISA_MIPS64
, CPU_MIPS64
},
13713 /* Broadcom SB-1 CPU core */
13714 { "sb1", 0, ISA_MIPS64
, CPU_SB1
},
13721 /* Return true if GIVEN is the same as CANONICAL, or if it is CANONICAL
13722 with a final "000" replaced by "k". Ignore case.
13724 Note: this function is shared between GCC and GAS. */
13727 mips_strict_matching_cpu_name_p (const char *canonical
, const char *given
)
13729 while (*given
!= 0 && TOLOWER (*given
) == TOLOWER (*canonical
))
13730 given
++, canonical
++;
13732 return ((*given
== 0 && *canonical
== 0)
13733 || (strcmp (canonical
, "000") == 0 && strcasecmp (given
, "k") == 0));
13737 /* Return true if GIVEN matches CANONICAL, where GIVEN is a user-supplied
13738 CPU name. We've traditionally allowed a lot of variation here.
13740 Note: this function is shared between GCC and GAS. */
13743 mips_matching_cpu_name_p (const char *canonical
, const char *given
)
13745 /* First see if the name matches exactly, or with a final "000"
13746 turned into "k". */
13747 if (mips_strict_matching_cpu_name_p (canonical
, given
))
13750 /* If not, try comparing based on numerical designation alone.
13751 See if GIVEN is an unadorned number, or 'r' followed by a number. */
13752 if (TOLOWER (*given
) == 'r')
13754 if (!ISDIGIT (*given
))
13757 /* Skip over some well-known prefixes in the canonical name,
13758 hoping to find a number there too. */
13759 if (TOLOWER (canonical
[0]) == 'v' && TOLOWER (canonical
[1]) == 'r')
13761 else if (TOLOWER (canonical
[0]) == 'r' && TOLOWER (canonical
[1]) == 'm')
13763 else if (TOLOWER (canonical
[0]) == 'r')
13766 return mips_strict_matching_cpu_name_p (canonical
, given
);
13770 /* Parse an option that takes the name of a processor as its argument.
13771 OPTION is the name of the option and CPU_STRING is the argument.
13772 Return the corresponding processor enumeration if the CPU_STRING is
13773 recognized, otherwise report an error and return null.
13775 A similar function exists in GCC. */
13777 static const struct mips_cpu_info
*
13778 mips_parse_cpu (const char *option
, const char *cpu_string
)
13780 const struct mips_cpu_info
*p
;
13782 /* 'from-abi' selects the most compatible architecture for the given
13783 ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit ABIs. For the
13784 EABIs, we have to decide whether we're using the 32-bit or 64-bit
13785 version. Look first at the -mgp options, if given, otherwise base
13786 the choice on MIPS_DEFAULT_64BIT.
13788 Treat NO_ABI like the EABIs. One reason to do this is that the
13789 plain 'mips' and 'mips64' configs have 'from-abi' as their default
13790 architecture. This code picks MIPS I for 'mips' and MIPS III for
13791 'mips64', just as we did in the days before 'from-abi'. */
13792 if (strcasecmp (cpu_string
, "from-abi") == 0)
13794 if (ABI_NEEDS_32BIT_REGS (mips_abi
))
13795 return mips_cpu_info_from_isa (ISA_MIPS1
);
13797 if (ABI_NEEDS_64BIT_REGS (mips_abi
))
13798 return mips_cpu_info_from_isa (ISA_MIPS3
);
13800 if (file_mips_gp32
>= 0)
13801 return mips_cpu_info_from_isa (file_mips_gp32
? ISA_MIPS1
: ISA_MIPS3
);
13803 return mips_cpu_info_from_isa (MIPS_DEFAULT_64BIT
13808 /* 'default' has traditionally been a no-op. Probably not very useful. */
13809 if (strcasecmp (cpu_string
, "default") == 0)
13812 for (p
= mips_cpu_info_table
; p
->name
!= 0; p
++)
13813 if (mips_matching_cpu_name_p (p
->name
, cpu_string
))
13816 as_bad ("Bad value (%s) for %s", cpu_string
, option
);
13820 /* Return the canonical processor information for ISA (a member of the
13821 ISA_MIPS* enumeration). */
13823 static const struct mips_cpu_info
*
13824 mips_cpu_info_from_isa (int isa
)
13828 for (i
= 0; mips_cpu_info_table
[i
].name
!= NULL
; i
++)
13829 if (mips_cpu_info_table
[i
].is_isa
13830 && isa
== mips_cpu_info_table
[i
].isa
)
13831 return (&mips_cpu_info_table
[i
]);
13836 static const struct mips_cpu_info
*
13837 mips_cpu_info_from_arch (int arch
)
13841 for (i
= 0; mips_cpu_info_table
[i
].name
!= NULL
; i
++)
13842 if (arch
== mips_cpu_info_table
[i
].cpu
)
13843 return (&mips_cpu_info_table
[i
]);
13849 show (FILE *stream
, const char *string
, int *col_p
, int *first_p
)
13853 fprintf (stream
, "%24s", "");
13858 fprintf (stream
, ", ");
13862 if (*col_p
+ strlen (string
) > 72)
13864 fprintf (stream
, "\n%24s", "");
13868 fprintf (stream
, "%s", string
);
13869 *col_p
+= strlen (string
);
13875 md_show_usage (FILE *stream
)
13880 fprintf (stream
, _("\
13882 -EB generate big endian output\n\
13883 -EL generate little endian output\n\
13884 -g, -g2 do not remove unneeded NOPs or swap branches\n\
13885 -G NUM allow referencing objects up to NUM bytes\n\
13886 implicitly with the gp register [default 8]\n"));
13887 fprintf (stream
, _("\
13888 -mips1 generate MIPS ISA I instructions\n\
13889 -mips2 generate MIPS ISA II instructions\n\
13890 -mips3 generate MIPS ISA III instructions\n\
13891 -mips4 generate MIPS ISA IV instructions\n\
13892 -mips5 generate MIPS ISA V instructions\n\
13893 -mips32 generate MIPS32 ISA instructions\n\
13894 -mips32r2 generate MIPS32 release 2 ISA instructions\n\
13895 -mips64 generate MIPS64 ISA instructions\n\
13896 -mips64r2 generate MIPS64 release 2 ISA instructions\n\
13897 -march=CPU/-mtune=CPU generate code/schedule for CPU, where CPU is one of:\n"));
13901 for (i
= 0; mips_cpu_info_table
[i
].name
!= NULL
; i
++)
13902 show (stream
, mips_cpu_info_table
[i
].name
, &column
, &first
);
13903 show (stream
, "from-abi", &column
, &first
);
13904 fputc ('\n', stream
);
13906 fprintf (stream
, _("\
13907 -mCPU equivalent to -march=CPU -mtune=CPU. Deprecated.\n\
13908 -no-mCPU don't generate code specific to CPU.\n\
13909 For -mCPU and -no-mCPU, CPU must be one of:\n"));
13913 show (stream
, "3900", &column
, &first
);
13914 show (stream
, "4010", &column
, &first
);
13915 show (stream
, "4100", &column
, &first
);
13916 show (stream
, "4650", &column
, &first
);
13917 fputc ('\n', stream
);
13919 fprintf (stream
, _("\
13920 -mips16 generate mips16 instructions\n\
13921 -no-mips16 do not generate mips16 instructions\n"));
13922 fprintf (stream
, _("\
13923 -mfix-vr4120 work around certain VR4120 errata\n\
13924 -mgp32 use 32-bit GPRs, regardless of the chosen ISA\n\
13925 -mfp32 use 32-bit FPRs, regardless of the chosen ISA\n\
13926 -mno-shared optimize output for executables\n\
13927 -msym32 assume all symbols have 32-bit values\n\
13928 -O0 remove unneeded NOPs, do not swap branches\n\
13929 -O remove unneeded NOPs and swap branches\n\
13930 --[no-]construct-floats [dis]allow floating point values to be constructed\n\
13931 --trap, --no-break trap exception on div by 0 and mult overflow\n\
13932 --break, --no-trap break exception on div by 0 and mult overflow\n"));
13934 fprintf (stream
, _("\
13935 -KPIC, -call_shared generate SVR4 position independent code\n\
13936 -non_shared do not generate position independent code\n\
13937 -xgot assume a 32 bit GOT\n\
13938 -mpdr, -mno-pdr enable/disable creation of .pdr sections\n\
13939 -mshared, -mno-shared disable/enable .cpload optimization for\n\
13941 -mabi=ABI create ABI conformant object file for:\n"));
13945 show (stream
, "32", &column
, &first
);
13946 show (stream
, "o64", &column
, &first
);
13947 show (stream
, "n32", &column
, &first
);
13948 show (stream
, "64", &column
, &first
);
13949 show (stream
, "eabi", &column
, &first
);
13951 fputc ('\n', stream
);
13953 fprintf (stream
, _("\
13954 -32 create o32 ABI object file (default)\n\
13955 -n32 create n32 ABI object file\n\
13956 -64 create 64 ABI object file\n"));
13961 mips_dwarf2_format (void)
13963 if (mips_abi
== N64_ABI
)
13966 return dwarf2_format_64bit_irix
;
13968 return dwarf2_format_64bit
;
13972 return dwarf2_format_32bit
;
13976 mips_dwarf2_addr_size (void)
13978 if (mips_abi
== N64_ABI
)