1 /* tc-mips.c -- assemble code for a MIPS chip.
2 Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,
3 2003, 2004, 2005 Free Software Foundation, Inc.
4 Contributed by the OSF and Ralph Campbell.
5 Written by Keith Knowles and Ralph Campbell, working independently.
6 Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus
9 This file is part of GAS.
11 GAS is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 2, or (at your option)
16 GAS is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
21 You should have received a copy of the GNU General Public License
22 along with GAS; see the file COPYING. If not, write to the Free
23 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
29 #include "safe-ctype.h"
33 #include "opcode/mips.h"
35 #include "dwarf2dbg.h"
36 #include "dw2gencfi.h"
39 #define DBG(x) printf x
45 /* Clean up namespace so we can include obj-elf.h too. */
46 static int mips_output_flavor (void);
47 static int mips_output_flavor (void) { return OUTPUT_FLAVOR
; }
48 #undef OBJ_PROCESS_STAB
55 #undef obj_frob_file_after_relocs
56 #undef obj_frob_symbol
58 #undef obj_sec_sym_ok_for_reloc
59 #undef OBJ_COPY_SYMBOL_ATTRIBUTES
62 /* Fix any of them that we actually care about. */
64 #define OUTPUT_FLAVOR mips_output_flavor()
71 #ifndef ECOFF_DEBUGGING
72 #define NO_ECOFF_DEBUGGING
73 #define ECOFF_DEBUGGING 0
76 int mips_flag_mdebug
= -1;
78 /* Control generation of .pdr sections. Off by default on IRIX: the native
79 linker doesn't know about and discards them, but relocations against them
80 remain, leading to rld crashes. */
82 int mips_flag_pdr
= FALSE
;
84 int mips_flag_pdr
= TRUE
;
89 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
90 static char *mips_regmask_frag
;
96 #define PIC_CALL_REG 25
104 #define ILLEGAL_REG (32)
106 /* Allow override of standard little-endian ECOFF format. */
108 #ifndef ECOFF_LITTLE_FORMAT
109 #define ECOFF_LITTLE_FORMAT "ecoff-littlemips"
112 extern int target_big_endian
;
114 /* The name of the readonly data section. */
115 #define RDATA_SECTION_NAME (OUTPUT_FLAVOR == bfd_target_ecoff_flavour \
117 : OUTPUT_FLAVOR == bfd_target_coff_flavour \
119 : OUTPUT_FLAVOR == bfd_target_elf_flavour \
123 /* Information about an instruction, including its format, operands
127 /* The opcode's entry in mips_opcodes or mips16_opcodes. */
128 const struct mips_opcode
*insn_mo
;
130 /* True if this is a mips16 instruction and if we want the extended
132 bfd_boolean use_extend
;
134 /* The 16-bit extension instruction to use when USE_EXTEND is true. */
135 unsigned short extend
;
137 /* The 16-bit or 32-bit bitstring of the instruction itself. This is
138 a copy of INSN_MO->match with the operands filled in. */
139 unsigned long insn_opcode
;
141 /* The frag that contains the instruction. */
144 /* The offset into FRAG of the first instruction byte. */
147 /* The relocs associated with the instruction, if any. */
150 /* True if this entry cannot be moved from its current position. */
151 unsigned int fixed_p
: 1;
153 /* True if this instruction occured in a .set noreorder block. */
154 unsigned int noreorder_p
: 1;
156 /* True for mips16 instructions that jump to an absolute address. */
157 unsigned int mips16_absolute_jump_p
: 1;
160 /* The ABI to use. */
171 /* MIPS ABI we are using for this output file. */
172 static enum mips_abi_level mips_abi
= NO_ABI
;
174 /* Whether or not we have code that can call pic code. */
175 int mips_abicalls
= FALSE
;
177 /* Whether or not we have code which can be put into a shared
179 static bfd_boolean mips_in_shared
= TRUE
;
181 /* This is the set of options which may be modified by the .set
182 pseudo-op. We use a struct so that .set push and .set pop are more
185 struct mips_set_options
187 /* MIPS ISA (Instruction Set Architecture) level. This is set to -1
188 if it has not been initialized. Changed by `.set mipsN', and the
189 -mipsN command line option, and the default CPU. */
191 /* Enabled Application Specific Extensions (ASEs). These are set to -1
192 if they have not been initialized. Changed by `.set <asename>', by
193 command line options, and based on the default architecture. */
197 /* Whether we are assembling for the mips16 processor. 0 if we are
198 not, 1 if we are, and -1 if the value has not been initialized.
199 Changed by `.set mips16' and `.set nomips16', and the -mips16 and
200 -nomips16 command line options, and the default CPU. */
202 /* Non-zero if we should not reorder instructions. Changed by `.set
203 reorder' and `.set noreorder'. */
205 /* Non-zero if we should not permit the $at ($1) register to be used
206 in instructions. Changed by `.set at' and `.set noat'. */
208 /* Non-zero if we should warn when a macro instruction expands into
209 more than one machine instruction. Changed by `.set nomacro' and
211 int warn_about_macros
;
212 /* Non-zero if we should not move instructions. Changed by `.set
213 move', `.set volatile', `.set nomove', and `.set novolatile'. */
215 /* Non-zero if we should not optimize branches by moving the target
216 of the branch into the delay slot. Actually, we don't perform
217 this optimization anyhow. Changed by `.set bopt' and `.set
220 /* Non-zero if we should not autoextend mips16 instructions.
221 Changed by `.set autoextend' and `.set noautoextend'. */
223 /* Restrict general purpose registers and floating point registers
224 to 32 bit. This is initially determined when -mgp32 or -mfp32
225 is passed but can changed if the assembler code uses .set mipsN. */
228 /* MIPS architecture (CPU) type. Changed by .set arch=FOO, the -march
229 command line option, and the default CPU. */
231 /* True if ".set sym32" is in effect. */
235 /* True if -mgp32 was passed. */
236 static int file_mips_gp32
= -1;
238 /* True if -mfp32 was passed. */
239 static int file_mips_fp32
= -1;
241 /* This is the struct we use to hold the current set of options. Note
242 that we must set the isa field to ISA_UNKNOWN and the ASE fields to
243 -1 to indicate that they have not been initialized. */
245 static struct mips_set_options mips_opts
=
247 ISA_UNKNOWN
, -1, -1, -1, -1, 0, 0, 0, 0, 0, 0, 0, 0, CPU_UNKNOWN
, FALSE
250 /* These variables are filled in with the masks of registers used.
251 The object format code reads them and puts them in the appropriate
253 unsigned long mips_gprmask
;
254 unsigned long mips_cprmask
[4];
256 /* MIPS ISA we are using for this output file. */
257 static int file_mips_isa
= ISA_UNKNOWN
;
259 /* True if -mips16 was passed or implied by arguments passed on the
260 command line (e.g., by -march). */
261 static int file_ase_mips16
;
263 /* True if -mips3d was passed or implied by arguments passed on the
264 command line (e.g., by -march). */
265 static int file_ase_mips3d
;
267 /* True if -mdmx was passed or implied by arguments passed on the
268 command line (e.g., by -march). */
269 static int file_ase_mdmx
;
271 /* True if -mdsp was passed or implied by arguments passed on the
272 command line (e.g., by -march). */
273 static int file_ase_dsp
;
275 /* The argument of the -march= flag. The architecture we are assembling. */
276 static int file_mips_arch
= CPU_UNKNOWN
;
277 static const char *mips_arch_string
;
279 /* The argument of the -mtune= flag. The architecture for which we
281 static int mips_tune
= CPU_UNKNOWN
;
282 static const char *mips_tune_string
;
284 /* True when generating 32-bit code for a 64-bit processor. */
285 static int mips_32bitmode
= 0;
287 /* True if the given ABI requires 32-bit registers. */
288 #define ABI_NEEDS_32BIT_REGS(ABI) ((ABI) == O32_ABI)
290 /* Likewise 64-bit registers. */
291 #define ABI_NEEDS_64BIT_REGS(ABI) \
293 || (ABI) == N64_ABI \
296 /* Return true if ISA supports 64 bit gp register instructions. */
297 #define ISA_HAS_64BIT_REGS(ISA) ( \
299 || (ISA) == ISA_MIPS4 \
300 || (ISA) == ISA_MIPS5 \
301 || (ISA) == ISA_MIPS64 \
302 || (ISA) == ISA_MIPS64R2 \
305 /* Return true if ISA supports 64-bit right rotate (dror et al.)
307 #define ISA_HAS_DROR(ISA) ( \
308 (ISA) == ISA_MIPS64R2 \
311 /* Return true if ISA supports 32-bit right rotate (ror et al.)
313 #define ISA_HAS_ROR(ISA) ( \
314 (ISA) == ISA_MIPS32R2 \
315 || (ISA) == ISA_MIPS64R2 \
318 #define HAVE_32BIT_GPRS \
319 (mips_opts.gp32 || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
321 #define HAVE_32BIT_FPRS \
322 (mips_opts.fp32 || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
324 #define HAVE_64BIT_GPRS (! HAVE_32BIT_GPRS)
325 #define HAVE_64BIT_FPRS (! HAVE_32BIT_FPRS)
327 #define HAVE_NEWABI (mips_abi == N32_ABI || mips_abi == N64_ABI)
329 #define HAVE_64BIT_OBJECTS (mips_abi == N64_ABI)
331 /* True if relocations are stored in-place. */
332 #define HAVE_IN_PLACE_ADDENDS (!HAVE_NEWABI)
334 /* The ABI-derived address size. */
335 #define HAVE_64BIT_ADDRESSES \
336 (HAVE_64BIT_GPRS && (mips_abi == EABI_ABI || mips_abi == N64_ABI))
337 #define HAVE_32BIT_ADDRESSES (!HAVE_64BIT_ADDRESSES)
339 /* The size of symbolic constants (i.e., expressions of the form
340 "SYMBOL" or "SYMBOL + OFFSET"). */
341 #define HAVE_32BIT_SYMBOLS \
342 (HAVE_32BIT_ADDRESSES || !HAVE_64BIT_OBJECTS || mips_opts.sym32)
343 #define HAVE_64BIT_SYMBOLS (!HAVE_32BIT_SYMBOLS)
345 /* Addresses are loaded in different ways, depending on the address size
346 in use. The n32 ABI Documentation also mandates the use of additions
347 with overflow checking, but existing implementations don't follow it. */
348 #define ADDRESS_ADD_INSN \
349 (HAVE_32BIT_ADDRESSES ? "addu" : "daddu")
351 #define ADDRESS_ADDI_INSN \
352 (HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu")
354 #define ADDRESS_LOAD_INSN \
355 (HAVE_32BIT_ADDRESSES ? "lw" : "ld")
357 #define ADDRESS_STORE_INSN \
358 (HAVE_32BIT_ADDRESSES ? "sw" : "sd")
360 /* Return true if the given CPU supports the MIPS16 ASE. */
361 #define CPU_HAS_MIPS16(cpu) \
362 (strncmp (TARGET_CPU, "mips16", sizeof ("mips16") - 1) == 0 \
363 || strncmp (TARGET_CANONICAL, "mips-lsi-elf", sizeof ("mips-lsi-elf") - 1) == 0)
365 /* Return true if the given CPU supports the MIPS3D ASE. */
366 #define CPU_HAS_MIPS3D(cpu) ((cpu) == CPU_SB1 \
369 /* Return true if the given CPU supports the MDMX ASE. */
370 #define CPU_HAS_MDMX(cpu) (FALSE \
373 /* Return true if the given CPU supports the DSP ASE. */
374 #define CPU_HAS_DSP(cpu) (FALSE \
377 /* True if CPU has a dror instruction. */
378 #define CPU_HAS_DROR(CPU) ((CPU) == CPU_VR5400 || (CPU) == CPU_VR5500)
380 /* True if CPU has a ror instruction. */
381 #define CPU_HAS_ROR(CPU) CPU_HAS_DROR (CPU)
383 /* True if mflo and mfhi can be immediately followed by instructions
384 which write to the HI and LO registers.
386 According to MIPS specifications, MIPS ISAs I, II, and III need
387 (at least) two instructions between the reads of HI/LO and
388 instructions which write them, and later ISAs do not. Contradicting
389 the MIPS specifications, some MIPS IV processor user manuals (e.g.
390 the UM for the NEC Vr5000) document needing the instructions between
391 HI/LO reads and writes, as well. Therefore, we declare only MIPS32,
392 MIPS64 and later ISAs to have the interlocks, plus any specific
393 earlier-ISA CPUs for which CPU documentation declares that the
394 instructions are really interlocked. */
395 #define hilo_interlocks \
396 (mips_opts.isa == ISA_MIPS32 \
397 || mips_opts.isa == ISA_MIPS32R2 \
398 || mips_opts.isa == ISA_MIPS64 \
399 || mips_opts.isa == ISA_MIPS64R2 \
400 || mips_opts.arch == CPU_R4010 \
401 || mips_opts.arch == CPU_R10000 \
402 || mips_opts.arch == CPU_R12000 \
403 || mips_opts.arch == CPU_RM7000 \
404 || mips_opts.arch == CPU_VR5500 \
407 /* Whether the processor uses hardware interlocks to protect reads
408 from the GPRs after they are loaded from memory, and thus does not
409 require nops to be inserted. This applies to instructions marked
410 INSN_LOAD_MEMORY_DELAY. These nops are only required at MIPS ISA
412 #define gpr_interlocks \
413 (mips_opts.isa != ISA_MIPS1 \
414 || mips_opts.arch == CPU_R3900)
416 /* Whether the processor uses hardware interlocks to avoid delays
417 required by coprocessor instructions, and thus does not require
418 nops to be inserted. This applies to instructions marked
419 INSN_LOAD_COPROC_DELAY, INSN_COPROC_MOVE_DELAY, and to delays
420 between instructions marked INSN_WRITE_COND_CODE and ones marked
421 INSN_READ_COND_CODE. These nops are only required at MIPS ISA
422 levels I, II, and III. */
423 /* Itbl support may require additional care here. */
424 #define cop_interlocks \
425 ((mips_opts.isa != ISA_MIPS1 \
426 && mips_opts.isa != ISA_MIPS2 \
427 && mips_opts.isa != ISA_MIPS3) \
428 || mips_opts.arch == CPU_R4300 \
431 /* Whether the processor uses hardware interlocks to protect reads
432 from coprocessor registers after they are loaded from memory, and
433 thus does not require nops to be inserted. This applies to
434 instructions marked INSN_COPROC_MEMORY_DELAY. These nops are only
435 requires at MIPS ISA level I. */
436 #define cop_mem_interlocks (mips_opts.isa != ISA_MIPS1)
438 /* Is this a mfhi or mflo instruction? */
439 #define MF_HILO_INSN(PINFO) \
440 ((PINFO & INSN_READ_HI) || (PINFO & INSN_READ_LO))
442 /* MIPS PIC level. */
444 enum mips_pic_level mips_pic
;
446 /* 1 if we should generate 32 bit offsets from the $gp register in
447 SVR4_PIC mode. Currently has no meaning in other modes. */
448 static int mips_big_got
= 0;
450 /* 1 if trap instructions should used for overflow rather than break
452 static int mips_trap
= 0;
454 /* 1 if double width floating point constants should not be constructed
455 by assembling two single width halves into two single width floating
456 point registers which just happen to alias the double width destination
457 register. On some architectures this aliasing can be disabled by a bit
458 in the status register, and the setting of this bit cannot be determined
459 automatically at assemble time. */
460 static int mips_disable_float_construction
;
462 /* Non-zero if any .set noreorder directives were used. */
464 static int mips_any_noreorder
;
466 /* Non-zero if nops should be inserted when the register referenced in
467 an mfhi/mflo instruction is read in the next two instructions. */
468 static int mips_7000_hilo_fix
;
470 /* The size of the small data section. */
471 static unsigned int g_switch_value
= 8;
472 /* Whether the -G option was used. */
473 static int g_switch_seen
= 0;
478 /* If we can determine in advance that GP optimization won't be
479 possible, we can skip the relaxation stuff that tries to produce
480 GP-relative references. This makes delay slot optimization work
483 This function can only provide a guess, but it seems to work for
484 gcc output. It needs to guess right for gcc, otherwise gcc
485 will put what it thinks is a GP-relative instruction in a branch
488 I don't know if a fix is needed for the SVR4_PIC mode. I've only
489 fixed it for the non-PIC mode. KR 95/04/07 */
490 static int nopic_need_relax (symbolS
*, int);
492 /* handle of the OPCODE hash table */
493 static struct hash_control
*op_hash
= NULL
;
495 /* The opcode hash table we use for the mips16. */
496 static struct hash_control
*mips16_op_hash
= NULL
;
498 /* This array holds the chars that always start a comment. If the
499 pre-processor is disabled, these aren't very useful */
500 const char comment_chars
[] = "#";
502 /* This array holds the chars that only start a comment at the beginning of
503 a line. If the line seems to have the form '# 123 filename'
504 .line and .file directives will appear in the pre-processed output */
505 /* Note that input_file.c hand checks for '#' at the beginning of the
506 first line of the input file. This is because the compiler outputs
507 #NO_APP at the beginning of its output. */
508 /* Also note that C style comments are always supported. */
509 const char line_comment_chars
[] = "#";
511 /* This array holds machine specific line separator characters. */
512 const char line_separator_chars
[] = ";";
514 /* Chars that can be used to separate mant from exp in floating point nums */
515 const char EXP_CHARS
[] = "eE";
517 /* Chars that mean this number is a floating point constant */
520 const char FLT_CHARS
[] = "rRsSfFdDxXpP";
522 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
523 changed in read.c . Ideally it shouldn't have to know about it at all,
524 but nothing is ideal around here.
527 static char *insn_error
;
529 static int auto_align
= 1;
531 /* When outputting SVR4 PIC code, the assembler needs to know the
532 offset in the stack frame from which to restore the $gp register.
533 This is set by the .cprestore pseudo-op, and saved in this
535 static offsetT mips_cprestore_offset
= -1;
537 /* Similar for NewABI PIC code, where $gp is callee-saved. NewABI has some
538 more optimizations, it can use a register value instead of a memory-saved
539 offset and even an other register than $gp as global pointer. */
540 static offsetT mips_cpreturn_offset
= -1;
541 static int mips_cpreturn_register
= -1;
542 static int mips_gp_register
= GP
;
543 static int mips_gprel_offset
= 0;
545 /* Whether mips_cprestore_offset has been set in the current function
546 (or whether it has already been warned about, if not). */
547 static int mips_cprestore_valid
= 0;
549 /* This is the register which holds the stack frame, as set by the
550 .frame pseudo-op. This is needed to implement .cprestore. */
551 static int mips_frame_reg
= SP
;
553 /* Whether mips_frame_reg has been set in the current function
554 (or whether it has already been warned about, if not). */
555 static int mips_frame_reg_valid
= 0;
557 /* To output NOP instructions correctly, we need to keep information
558 about the previous two instructions. */
560 /* Whether we are optimizing. The default value of 2 means to remove
561 unneeded NOPs and swap branch instructions when possible. A value
562 of 1 means to not swap branches. A value of 0 means to always
564 static int mips_optimize
= 2;
566 /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is
567 equivalent to seeing no -g option at all. */
568 static int mips_debug
= 0;
570 /* The maximum number of NOPs needed to avoid the VR4130 mflo/mfhi errata. */
571 #define MAX_VR4130_NOPS 4
573 /* The maximum number of NOPs needed to fill delay slots. */
574 #define MAX_DELAY_NOPS 2
576 /* The maximum number of NOPs needed for any purpose. */
579 /* A list of previous instructions, with index 0 being the most recent.
580 We need to look back MAX_NOPS instructions when filling delay slots
581 or working around processor errata. We need to look back one
582 instruction further if we're thinking about using history[0] to
583 fill a branch delay slot. */
584 static struct mips_cl_insn history
[1 + MAX_NOPS
];
586 /* Nop instructions used by emit_nop. */
587 static struct mips_cl_insn nop_insn
, mips16_nop_insn
;
589 /* The appropriate nop for the current mode. */
590 #define NOP_INSN (mips_opts.mips16 ? &mips16_nop_insn : &nop_insn)
592 /* If this is set, it points to a frag holding nop instructions which
593 were inserted before the start of a noreorder section. If those
594 nops turn out to be unnecessary, the size of the frag can be
596 static fragS
*prev_nop_frag
;
598 /* The number of nop instructions we created in prev_nop_frag. */
599 static int prev_nop_frag_holds
;
601 /* The number of nop instructions that we know we need in
603 static int prev_nop_frag_required
;
605 /* The number of instructions we've seen since prev_nop_frag. */
606 static int prev_nop_frag_since
;
608 /* For ECOFF and ELF, relocations against symbols are done in two
609 parts, with a HI relocation and a LO relocation. Each relocation
610 has only 16 bits of space to store an addend. This means that in
611 order for the linker to handle carries correctly, it must be able
612 to locate both the HI and the LO relocation. This means that the
613 relocations must appear in order in the relocation table.
615 In order to implement this, we keep track of each unmatched HI
616 relocation. We then sort them so that they immediately precede the
617 corresponding LO relocation. */
622 struct mips_hi_fixup
*next
;
625 /* The section this fixup is in. */
629 /* The list of unmatched HI relocs. */
631 static struct mips_hi_fixup
*mips_hi_fixup_list
;
633 /* The frag containing the last explicit relocation operator.
634 Null if explicit relocations have not been used. */
636 static fragS
*prev_reloc_op_frag
;
638 /* Map normal MIPS register numbers to mips16 register numbers. */
640 #define X ILLEGAL_REG
641 static const int mips32_to_16_reg_map
[] =
643 X
, X
, 2, 3, 4, 5, 6, 7,
644 X
, X
, X
, X
, X
, X
, X
, X
,
645 0, 1, X
, X
, X
, X
, X
, X
,
646 X
, X
, X
, X
, X
, X
, X
, X
650 /* Map mips16 register numbers to normal MIPS register numbers. */
652 static const unsigned int mips16_to_32_reg_map
[] =
654 16, 17, 2, 3, 4, 5, 6, 7
657 /* Classifies the kind of instructions we're interested in when
658 implementing -mfix-vr4120. */
659 enum fix_vr4120_class
{
666 NUM_FIX_VR4120_CLASSES
669 /* Given two FIX_VR4120_* values X and Y, bit Y of element X is set if
670 there must be at least one other instruction between an instruction
671 of type X and an instruction of type Y. */
672 static unsigned int vr4120_conflicts
[NUM_FIX_VR4120_CLASSES
];
674 /* True if -mfix-vr4120 is in force. */
675 static int mips_fix_vr4120
;
677 /* ...likewise -mfix-vr4130. */
678 static int mips_fix_vr4130
;
680 /* We don't relax branches by default, since this causes us to expand
681 `la .l2 - .l1' if there's a branch between .l1 and .l2, because we
682 fail to compute the offset before expanding the macro to the most
683 efficient expansion. */
685 static int mips_relax_branch
;
687 /* The expansion of many macros depends on the type of symbol that
688 they refer to. For example, when generating position-dependent code,
689 a macro that refers to a symbol may have two different expansions,
690 one which uses GP-relative addresses and one which uses absolute
691 addresses. When generating SVR4-style PIC, a macro may have
692 different expansions for local and global symbols.
694 We handle these situations by generating both sequences and putting
695 them in variant frags. In position-dependent code, the first sequence
696 will be the GP-relative one and the second sequence will be the
697 absolute one. In SVR4 PIC, the first sequence will be for global
698 symbols and the second will be for local symbols.
700 The frag's "subtype" is RELAX_ENCODE (FIRST, SECOND), where FIRST and
701 SECOND are the lengths of the two sequences in bytes. These fields
702 can be extracted using RELAX_FIRST() and RELAX_SECOND(). In addition,
703 the subtype has the following flags:
706 Set if it has been decided that we should use the second
707 sequence instead of the first.
710 Set in the first variant frag if the macro's second implementation
711 is longer than its first. This refers to the macro as a whole,
712 not an individual relaxation.
715 Set in the first variant frag if the macro appeared in a .set nomacro
716 block and if one alternative requires a warning but the other does not.
719 Like RELAX_NOMACRO, but indicates that the macro appears in a branch
722 The frag's "opcode" points to the first fixup for relaxable code.
724 Relaxable macros are generated using a sequence such as:
726 relax_start (SYMBOL);
727 ... generate first expansion ...
729 ... generate second expansion ...
732 The code and fixups for the unwanted alternative are discarded
733 by md_convert_frag. */
734 #define RELAX_ENCODE(FIRST, SECOND) (((FIRST) << 8) | (SECOND))
736 #define RELAX_FIRST(X) (((X) >> 8) & 0xff)
737 #define RELAX_SECOND(X) ((X) & 0xff)
738 #define RELAX_USE_SECOND 0x10000
739 #define RELAX_SECOND_LONGER 0x20000
740 #define RELAX_NOMACRO 0x40000
741 #define RELAX_DELAY_SLOT 0x80000
743 /* Branch without likely bit. If label is out of range, we turn:
745 beq reg1, reg2, label
755 with the following opcode replacements:
762 bltzal <-> bgezal (with jal label instead of j label)
764 Even though keeping the delay slot instruction in the delay slot of
765 the branch would be more efficient, it would be very tricky to do
766 correctly, because we'd have to introduce a variable frag *after*
767 the delay slot instruction, and expand that instead. Let's do it
768 the easy way for now, even if the branch-not-taken case now costs
769 one additional instruction. Out-of-range branches are not supposed
770 to be common, anyway.
772 Branch likely. If label is out of range, we turn:
774 beql reg1, reg2, label
775 delay slot (annulled if branch not taken)
784 delay slot (executed only if branch taken)
787 It would be possible to generate a shorter sequence by losing the
788 likely bit, generating something like:
793 delay slot (executed only if branch taken)
805 bltzall -> bgezal (with jal label instead of j label)
806 bgezall -> bltzal (ditto)
809 but it's not clear that it would actually improve performance. */
810 #define RELAX_BRANCH_ENCODE(uncond, likely, link, toofar) \
813 | ((toofar) ? 1 : 0) \
815 | ((likely) ? 4 : 0) \
816 | ((uncond) ? 8 : 0)))
817 #define RELAX_BRANCH_P(i) (((i) & 0xf0000000) == 0xc0000000)
818 #define RELAX_BRANCH_UNCOND(i) (((i) & 8) != 0)
819 #define RELAX_BRANCH_LIKELY(i) (((i) & 4) != 0)
820 #define RELAX_BRANCH_LINK(i) (((i) & 2) != 0)
821 #define RELAX_BRANCH_TOOFAR(i) (((i) & 1) != 0)
823 /* For mips16 code, we use an entirely different form of relaxation.
824 mips16 supports two versions of most instructions which take
825 immediate values: a small one which takes some small value, and a
826 larger one which takes a 16 bit value. Since branches also follow
827 this pattern, relaxing these values is required.
829 We can assemble both mips16 and normal MIPS code in a single
830 object. Therefore, we need to support this type of relaxation at
831 the same time that we support the relaxation described above. We
832 use the high bit of the subtype field to distinguish these cases.
834 The information we store for this type of relaxation is the
835 argument code found in the opcode file for this relocation, whether
836 the user explicitly requested a small or extended form, and whether
837 the relocation is in a jump or jal delay slot. That tells us the
838 size of the value, and how it should be stored. We also store
839 whether the fragment is considered to be extended or not. We also
840 store whether this is known to be a branch to a different section,
841 whether we have tried to relax this frag yet, and whether we have
842 ever extended a PC relative fragment because of a shift count. */
843 #define RELAX_MIPS16_ENCODE(type, small, ext, dslot, jal_dslot) \
846 | ((small) ? 0x100 : 0) \
847 | ((ext) ? 0x200 : 0) \
848 | ((dslot) ? 0x400 : 0) \
849 | ((jal_dslot) ? 0x800 : 0))
850 #define RELAX_MIPS16_P(i) (((i) & 0xc0000000) == 0x80000000)
851 #define RELAX_MIPS16_TYPE(i) ((i) & 0xff)
852 #define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x100) != 0)
853 #define RELAX_MIPS16_USER_EXT(i) (((i) & 0x200) != 0)
854 #define RELAX_MIPS16_DSLOT(i) (((i) & 0x400) != 0)
855 #define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x800) != 0)
856 #define RELAX_MIPS16_EXTENDED(i) (((i) & 0x1000) != 0)
857 #define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x1000)
858 #define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) &~ 0x1000)
859 #define RELAX_MIPS16_LONG_BRANCH(i) (((i) & 0x2000) != 0)
860 #define RELAX_MIPS16_MARK_LONG_BRANCH(i) ((i) | 0x2000)
861 #define RELAX_MIPS16_CLEAR_LONG_BRANCH(i) ((i) &~ 0x2000)
863 /* Is the given value a sign-extended 32-bit value? */
864 #define IS_SEXT_32BIT_NUM(x) \
865 (((x) &~ (offsetT) 0x7fffffff) == 0 \
866 || (((x) &~ (offsetT) 0x7fffffff) == ~ (offsetT) 0x7fffffff))
868 /* Is the given value a sign-extended 16-bit value? */
869 #define IS_SEXT_16BIT_NUM(x) \
870 (((x) &~ (offsetT) 0x7fff) == 0 \
871 || (((x) &~ (offsetT) 0x7fff) == ~ (offsetT) 0x7fff))
873 /* Is the given value a zero-extended 32-bit value? Or a negated one? */
874 #define IS_ZEXT_32BIT_NUM(x) \
875 (((x) &~ (offsetT) 0xffffffff) == 0 \
876 || (((x) &~ (offsetT) 0xffffffff) == ~ (offsetT) 0xffffffff))
878 /* Replace bits MASK << SHIFT of STRUCT with the equivalent bits in
879 VALUE << SHIFT. VALUE is evaluated exactly once. */
880 #define INSERT_BITS(STRUCT, VALUE, MASK, SHIFT) \
881 (STRUCT) = (((STRUCT) & ~((MASK) << (SHIFT))) \
882 | (((VALUE) & (MASK)) << (SHIFT)))
884 /* Extract bits MASK << SHIFT from STRUCT and shift them right
886 #define EXTRACT_BITS(STRUCT, MASK, SHIFT) \
887 (((STRUCT) >> (SHIFT)) & (MASK))
889 /* Change INSN's opcode so that the operand given by FIELD has value VALUE.
890 INSN is a mips_cl_insn structure and VALUE is evaluated exactly once.
892 include/opcode/mips.h specifies operand fields using the macros
893 OP_MASK_<FIELD> and OP_SH_<FIELD>. The MIPS16 equivalents start
894 with "MIPS16OP" instead of "OP". */
895 #define INSERT_OPERAND(FIELD, INSN, VALUE) \
896 INSERT_BITS ((INSN).insn_opcode, VALUE, OP_MASK_##FIELD, OP_SH_##FIELD)
897 #define MIPS16_INSERT_OPERAND(FIELD, INSN, VALUE) \
898 INSERT_BITS ((INSN).insn_opcode, VALUE, \
899 MIPS16OP_MASK_##FIELD, MIPS16OP_SH_##FIELD)
901 /* Extract the operand given by FIELD from mips_cl_insn INSN. */
902 #define EXTRACT_OPERAND(FIELD, INSN) \
903 EXTRACT_BITS ((INSN).insn_opcode, OP_MASK_##FIELD, OP_SH_##FIELD)
904 #define MIPS16_EXTRACT_OPERAND(FIELD, INSN) \
905 EXTRACT_BITS ((INSN).insn_opcode, \
906 MIPS16OP_MASK_##FIELD, \
909 /* Global variables used when generating relaxable macros. See the
910 comment above RELAX_ENCODE for more details about how relaxation
913 /* 0 if we're not emitting a relaxable macro.
914 1 if we're emitting the first of the two relaxation alternatives.
915 2 if we're emitting the second alternative. */
918 /* The first relaxable fixup in the current frag. (In other words,
919 the first fixup that refers to relaxable code.) */
922 /* sizes[0] says how many bytes of the first alternative are stored in
923 the current frag. Likewise sizes[1] for the second alternative. */
924 unsigned int sizes
[2];
926 /* The symbol on which the choice of sequence depends. */
930 /* Global variables used to decide whether a macro needs a warning. */
932 /* True if the macro is in a branch delay slot. */
933 bfd_boolean delay_slot_p
;
935 /* For relaxable macros, sizes[0] is the length of the first alternative
936 in bytes and sizes[1] is the length of the second alternative.
937 For non-relaxable macros, both elements give the length of the
939 unsigned int sizes
[2];
941 /* The first variant frag for this macro. */
943 } mips_macro_warning
;
945 /* Prototypes for static functions. */
947 #define internalError() \
948 as_fatal (_("internal Error, line %d, %s"), __LINE__, __FILE__)
950 enum mips_regclass
{ MIPS_GR_REG
, MIPS_FP_REG
, MIPS16_REG
};
952 static void append_insn
953 (struct mips_cl_insn
*ip
, expressionS
*p
, bfd_reloc_code_real_type
*r
);
954 static void mips_no_prev_insn (void);
955 static void mips16_macro_build
956 (expressionS
*, const char *, const char *, va_list);
957 static void load_register (int, expressionS
*, int);
958 static void macro_start (void);
959 static void macro_end (void);
960 static void macro (struct mips_cl_insn
* ip
);
961 static void mips16_macro (struct mips_cl_insn
* ip
);
962 #ifdef LOSING_COMPILER
963 static void macro2 (struct mips_cl_insn
* ip
);
965 static void mips_ip (char *str
, struct mips_cl_insn
* ip
);
966 static void mips16_ip (char *str
, struct mips_cl_insn
* ip
);
967 static void mips16_immed
968 (char *, unsigned int, int, offsetT
, bfd_boolean
, bfd_boolean
, bfd_boolean
,
969 unsigned long *, bfd_boolean
*, unsigned short *);
970 static size_t my_getSmallExpression
971 (expressionS
*, bfd_reloc_code_real_type
*, char *);
972 static void my_getExpression (expressionS
*, char *);
973 static void s_align (int);
974 static void s_change_sec (int);
975 static void s_change_section (int);
976 static void s_cons (int);
977 static void s_float_cons (int);
978 static void s_mips_globl (int);
979 static void s_option (int);
980 static void s_mipsset (int);
981 static void s_abicalls (int);
982 static void s_cpload (int);
983 static void s_cpsetup (int);
984 static void s_cplocal (int);
985 static void s_cprestore (int);
986 static void s_cpreturn (int);
987 static void s_gpvalue (int);
988 static void s_gpword (int);
989 static void s_gpdword (int);
990 static void s_cpadd (int);
991 static void s_insn (int);
992 static void md_obj_begin (void);
993 static void md_obj_end (void);
994 static void s_mips_ent (int);
995 static void s_mips_end (int);
996 static void s_mips_frame (int);
997 static void s_mips_mask (int reg_type
);
998 static void s_mips_stab (int);
999 static void s_mips_weakext (int);
1000 static void s_mips_file (int);
1001 static void s_mips_loc (int);
1002 static bfd_boolean
pic_need_relax (symbolS
*, asection
*);
1003 static int relaxed_branch_length (fragS
*, asection
*, int);
1004 static int validate_mips_insn (const struct mips_opcode
*);
1006 /* Table and functions used to map between CPU/ISA names, and
1007 ISA levels, and CPU numbers. */
1009 struct mips_cpu_info
1011 const char *name
; /* CPU or ISA name. */
1012 int is_isa
; /* Is this an ISA? (If 0, a CPU.) */
1013 int isa
; /* ISA level. */
1014 int cpu
; /* CPU number (default CPU if ISA). */
1017 static const struct mips_cpu_info
*mips_parse_cpu (const char *, const char *);
1018 static const struct mips_cpu_info
*mips_cpu_info_from_isa (int);
1019 static const struct mips_cpu_info
*mips_cpu_info_from_arch (int);
1023 The following pseudo-ops from the Kane and Heinrich MIPS book
1024 should be defined here, but are currently unsupported: .alias,
1025 .galive, .gjaldef, .gjrlive, .livereg, .noalias.
1027 The following pseudo-ops from the Kane and Heinrich MIPS book are
1028 specific to the type of debugging information being generated, and
1029 should be defined by the object format: .aent, .begin, .bend,
1030 .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp,
1033 The following pseudo-ops from the Kane and Heinrich MIPS book are
1034 not MIPS CPU specific, but are also not specific to the object file
1035 format. This file is probably the best place to define them, but
1036 they are not currently supported: .asm0, .endr, .lab, .repeat,
1039 static const pseudo_typeS mips_pseudo_table
[] =
1041 /* MIPS specific pseudo-ops. */
1042 {"option", s_option
, 0},
1043 {"set", s_mipsset
, 0},
1044 {"rdata", s_change_sec
, 'r'},
1045 {"sdata", s_change_sec
, 's'},
1046 {"livereg", s_ignore
, 0},
1047 {"abicalls", s_abicalls
, 0},
1048 {"cpload", s_cpload
, 0},
1049 {"cpsetup", s_cpsetup
, 0},
1050 {"cplocal", s_cplocal
, 0},
1051 {"cprestore", s_cprestore
, 0},
1052 {"cpreturn", s_cpreturn
, 0},
1053 {"gpvalue", s_gpvalue
, 0},
1054 {"gpword", s_gpword
, 0},
1055 {"gpdword", s_gpdword
, 0},
1056 {"cpadd", s_cpadd
, 0},
1057 {"insn", s_insn
, 0},
1059 /* Relatively generic pseudo-ops that happen to be used on MIPS
1061 {"asciiz", stringer
, 1},
1062 {"bss", s_change_sec
, 'b'},
1064 {"half", s_cons
, 1},
1065 {"dword", s_cons
, 3},
1066 {"weakext", s_mips_weakext
, 0},
1068 /* These pseudo-ops are defined in read.c, but must be overridden
1069 here for one reason or another. */
1070 {"align", s_align
, 0},
1071 {"byte", s_cons
, 0},
1072 {"data", s_change_sec
, 'd'},
1073 {"double", s_float_cons
, 'd'},
1074 {"float", s_float_cons
, 'f'},
1075 {"globl", s_mips_globl
, 0},
1076 {"global", s_mips_globl
, 0},
1077 {"hword", s_cons
, 1},
1079 {"long", s_cons
, 2},
1080 {"octa", s_cons
, 4},
1081 {"quad", s_cons
, 3},
1082 {"section", s_change_section
, 0},
1083 {"short", s_cons
, 1},
1084 {"single", s_float_cons
, 'f'},
1085 {"stabn", s_mips_stab
, 'n'},
1086 {"text", s_change_sec
, 't'},
1087 {"word", s_cons
, 2},
1089 { "extern", ecoff_directive_extern
, 0},
1094 static const pseudo_typeS mips_nonecoff_pseudo_table
[] =
1096 /* These pseudo-ops should be defined by the object file format.
1097 However, a.out doesn't support them, so we have versions here. */
1098 {"aent", s_mips_ent
, 1},
1099 {"bgnb", s_ignore
, 0},
1100 {"end", s_mips_end
, 0},
1101 {"endb", s_ignore
, 0},
1102 {"ent", s_mips_ent
, 0},
1103 {"file", s_mips_file
, 0},
1104 {"fmask", s_mips_mask
, 'F'},
1105 {"frame", s_mips_frame
, 0},
1106 {"loc", s_mips_loc
, 0},
1107 {"mask", s_mips_mask
, 'R'},
1108 {"verstamp", s_ignore
, 0},
1112 extern void pop_insert (const pseudo_typeS
*);
1115 mips_pop_insert (void)
1117 pop_insert (mips_pseudo_table
);
1118 if (! ECOFF_DEBUGGING
)
1119 pop_insert (mips_nonecoff_pseudo_table
);
1122 /* Symbols labelling the current insn. */
1124 struct insn_label_list
1126 struct insn_label_list
*next
;
1130 static struct insn_label_list
*insn_labels
;
1131 static struct insn_label_list
*free_insn_labels
;
1133 static void mips_clear_insn_labels (void);
1136 mips_clear_insn_labels (void)
1138 register struct insn_label_list
**pl
;
1140 for (pl
= &free_insn_labels
; *pl
!= NULL
; pl
= &(*pl
)->next
)
1146 static char *expr_end
;
1148 /* Expressions which appear in instructions. These are set by
1151 static expressionS imm_expr
;
1152 static expressionS imm2_expr
;
1153 static expressionS offset_expr
;
1155 /* Relocs associated with imm_expr and offset_expr. */
1157 static bfd_reloc_code_real_type imm_reloc
[3]
1158 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
1159 static bfd_reloc_code_real_type offset_reloc
[3]
1160 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
1162 /* These are set by mips16_ip if an explicit extension is used. */
1164 static bfd_boolean mips16_small
, mips16_ext
;
1167 /* The pdr segment for per procedure frame/regmask info. Not used for
1170 static segT pdr_seg
;
1173 /* The default target format to use. */
1176 mips_target_format (void)
1178 switch (OUTPUT_FLAVOR
)
1180 case bfd_target_ecoff_flavour
:
1181 return target_big_endian
? "ecoff-bigmips" : ECOFF_LITTLE_FORMAT
;
1182 case bfd_target_coff_flavour
:
1184 case bfd_target_elf_flavour
:
1186 /* This is traditional mips. */
1187 return (target_big_endian
1188 ? (HAVE_64BIT_OBJECTS
1189 ? "elf64-tradbigmips"
1191 ? "elf32-ntradbigmips" : "elf32-tradbigmips"))
1192 : (HAVE_64BIT_OBJECTS
1193 ? "elf64-tradlittlemips"
1195 ? "elf32-ntradlittlemips" : "elf32-tradlittlemips")));
1197 return (target_big_endian
1198 ? (HAVE_64BIT_OBJECTS
1201 ? "elf32-nbigmips" : "elf32-bigmips"))
1202 : (HAVE_64BIT_OBJECTS
1203 ? "elf64-littlemips"
1205 ? "elf32-nlittlemips" : "elf32-littlemips")));
1213 /* Return the length of instruction INSN. */
1215 static inline unsigned int
1216 insn_length (const struct mips_cl_insn
*insn
)
1218 if (!mips_opts
.mips16
)
1220 return insn
->mips16_absolute_jump_p
|| insn
->use_extend
? 4 : 2;
1223 /* Initialise INSN from opcode entry MO. Leave its position unspecified. */
1226 create_insn (struct mips_cl_insn
*insn
, const struct mips_opcode
*mo
)
1231 insn
->use_extend
= FALSE
;
1233 insn
->insn_opcode
= mo
->match
;
1236 for (i
= 0; i
< ARRAY_SIZE (insn
->fixp
); i
++)
1237 insn
->fixp
[i
] = NULL
;
1238 insn
->fixed_p
= (mips_opts
.noreorder
> 0);
1239 insn
->noreorder_p
= (mips_opts
.noreorder
> 0);
1240 insn
->mips16_absolute_jump_p
= 0;
1243 /* Install INSN at the location specified by its "frag" and "where" fields. */
1246 install_insn (const struct mips_cl_insn
*insn
)
1248 char *f
= insn
->frag
->fr_literal
+ insn
->where
;
1249 if (!mips_opts
.mips16
)
1250 md_number_to_chars (f
, insn
->insn_opcode
, 4);
1251 else if (insn
->mips16_absolute_jump_p
)
1253 md_number_to_chars (f
, insn
->insn_opcode
>> 16, 2);
1254 md_number_to_chars (f
+ 2, insn
->insn_opcode
& 0xffff, 2);
1258 if (insn
->use_extend
)
1260 md_number_to_chars (f
, 0xf000 | insn
->extend
, 2);
1263 md_number_to_chars (f
, insn
->insn_opcode
, 2);
1267 /* Move INSN to offset WHERE in FRAG. Adjust the fixups accordingly
1268 and install the opcode in the new location. */
1271 move_insn (struct mips_cl_insn
*insn
, fragS
*frag
, long where
)
1276 insn
->where
= where
;
1277 for (i
= 0; i
< ARRAY_SIZE (insn
->fixp
); i
++)
1278 if (insn
->fixp
[i
] != NULL
)
1280 insn
->fixp
[i
]->fx_frag
= frag
;
1281 insn
->fixp
[i
]->fx_where
= where
;
1283 install_insn (insn
);
1286 /* Add INSN to the end of the output. */
1289 add_fixed_insn (struct mips_cl_insn
*insn
)
1291 char *f
= frag_more (insn_length (insn
));
1292 move_insn (insn
, frag_now
, f
- frag_now
->fr_literal
);
1295 /* Start a variant frag and move INSN to the start of the variant part,
1296 marking it as fixed. The other arguments are as for frag_var. */
1299 add_relaxed_insn (struct mips_cl_insn
*insn
, int max_chars
, int var
,
1300 relax_substateT subtype
, symbolS
*symbol
, offsetT offset
)
1302 frag_grow (max_chars
);
1303 move_insn (insn
, frag_now
, frag_more (0) - frag_now
->fr_literal
);
1305 frag_var (rs_machine_dependent
, max_chars
, var
,
1306 subtype
, symbol
, offset
, NULL
);
1309 /* Insert N copies of INSN into the history buffer, starting at
1310 position FIRST. Neither FIRST nor N need to be clipped. */
1313 insert_into_history (unsigned int first
, unsigned int n
,
1314 const struct mips_cl_insn
*insn
)
1316 if (mips_relax
.sequence
!= 2)
1320 for (i
= ARRAY_SIZE (history
); i
-- > first
;)
1322 history
[i
] = history
[i
- n
];
1328 /* Emit a nop instruction, recording it in the history buffer. */
1333 add_fixed_insn (NOP_INSN
);
1334 insert_into_history (0, 1, NOP_INSN
);
1337 /* Initialize vr4120_conflicts. There is a bit of duplication here:
1338 the idea is to make it obvious at a glance that each errata is
1342 init_vr4120_conflicts (void)
1344 #define CONFLICT(FIRST, SECOND) \
1345 vr4120_conflicts[FIX_VR4120_##FIRST] |= 1 << FIX_VR4120_##SECOND
1347 /* Errata 21 - [D]DIV[U] after [D]MACC */
1348 CONFLICT (MACC
, DIV
);
1349 CONFLICT (DMACC
, DIV
);
1351 /* Errata 23 - Continuous DMULT[U]/DMACC instructions. */
1352 CONFLICT (DMULT
, DMULT
);
1353 CONFLICT (DMULT
, DMACC
);
1354 CONFLICT (DMACC
, DMULT
);
1355 CONFLICT (DMACC
, DMACC
);
1357 /* Errata 24 - MT{LO,HI} after [D]MACC */
1358 CONFLICT (MACC
, MTHILO
);
1359 CONFLICT (DMACC
, MTHILO
);
1361 /* VR4181A errata MD(1): "If a MULT, MULTU, DMULT or DMULTU
1362 instruction is executed immediately after a MACC or DMACC
1363 instruction, the result of [either instruction] is incorrect." */
1364 CONFLICT (MACC
, MULT
);
1365 CONFLICT (MACC
, DMULT
);
1366 CONFLICT (DMACC
, MULT
);
1367 CONFLICT (DMACC
, DMULT
);
1369 /* VR4181A errata MD(4): "If a MACC or DMACC instruction is
1370 executed immediately after a DMULT, DMULTU, DIV, DIVU,
1371 DDIV or DDIVU instruction, the result of the MACC or
1372 DMACC instruction is incorrect.". */
1373 CONFLICT (DMULT
, MACC
);
1374 CONFLICT (DMULT
, DMACC
);
1375 CONFLICT (DIV
, MACC
);
1376 CONFLICT (DIV
, DMACC
);
1381 /* This function is called once, at assembler startup time. It should
1382 set up all the tables, etc. that the MD part of the assembler will need. */
1387 register const char *retval
= NULL
;
1391 if (! bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, file_mips_arch
))
1392 as_warn (_("Could not set architecture and machine"));
1394 op_hash
= hash_new ();
1396 for (i
= 0; i
< NUMOPCODES
;)
1398 const char *name
= mips_opcodes
[i
].name
;
1400 retval
= hash_insert (op_hash
, name
, (void *) &mips_opcodes
[i
]);
1403 fprintf (stderr
, _("internal error: can't hash `%s': %s\n"),
1404 mips_opcodes
[i
].name
, retval
);
1405 /* Probably a memory allocation problem? Give up now. */
1406 as_fatal (_("Broken assembler. No assembly attempted."));
1410 if (mips_opcodes
[i
].pinfo
!= INSN_MACRO
)
1412 if (!validate_mips_insn (&mips_opcodes
[i
]))
1414 if (nop_insn
.insn_mo
== NULL
&& strcmp (name
, "nop") == 0)
1416 create_insn (&nop_insn
, mips_opcodes
+ i
);
1417 nop_insn
.fixed_p
= 1;
1422 while ((i
< NUMOPCODES
) && !strcmp (mips_opcodes
[i
].name
, name
));
1425 mips16_op_hash
= hash_new ();
1428 while (i
< bfd_mips16_num_opcodes
)
1430 const char *name
= mips16_opcodes
[i
].name
;
1432 retval
= hash_insert (mips16_op_hash
, name
, (void *) &mips16_opcodes
[i
]);
1434 as_fatal (_("internal: can't hash `%s': %s"),
1435 mips16_opcodes
[i
].name
, retval
);
1438 if (mips16_opcodes
[i
].pinfo
!= INSN_MACRO
1439 && ((mips16_opcodes
[i
].match
& mips16_opcodes
[i
].mask
)
1440 != mips16_opcodes
[i
].match
))
1442 fprintf (stderr
, _("internal error: bad mips16 opcode: %s %s\n"),
1443 mips16_opcodes
[i
].name
, mips16_opcodes
[i
].args
);
1446 if (mips16_nop_insn
.insn_mo
== NULL
&& strcmp (name
, "nop") == 0)
1448 create_insn (&mips16_nop_insn
, mips16_opcodes
+ i
);
1449 mips16_nop_insn
.fixed_p
= 1;
1453 while (i
< bfd_mips16_num_opcodes
1454 && strcmp (mips16_opcodes
[i
].name
, name
) == 0);
1458 as_fatal (_("Broken assembler. No assembly attempted."));
1460 /* We add all the general register names to the symbol table. This
1461 helps us detect invalid uses of them. */
1462 for (i
= 0; i
< 32; i
++)
1466 sprintf (buf
, "$%d", i
);
1467 symbol_table_insert (symbol_new (buf
, reg_section
, i
,
1468 &zero_address_frag
));
1470 symbol_table_insert (symbol_new ("$ra", reg_section
, RA
,
1471 &zero_address_frag
));
1472 symbol_table_insert (symbol_new ("$fp", reg_section
, FP
,
1473 &zero_address_frag
));
1474 symbol_table_insert (symbol_new ("$sp", reg_section
, SP
,
1475 &zero_address_frag
));
1476 symbol_table_insert (symbol_new ("$gp", reg_section
, GP
,
1477 &zero_address_frag
));
1478 symbol_table_insert (symbol_new ("$at", reg_section
, AT
,
1479 &zero_address_frag
));
1480 symbol_table_insert (symbol_new ("$kt0", reg_section
, KT0
,
1481 &zero_address_frag
));
1482 symbol_table_insert (symbol_new ("$kt1", reg_section
, KT1
,
1483 &zero_address_frag
));
1484 symbol_table_insert (symbol_new ("$zero", reg_section
, ZERO
,
1485 &zero_address_frag
));
1486 symbol_table_insert (symbol_new ("$pc", reg_section
, -1,
1487 &zero_address_frag
));
1489 /* If we don't add these register names to the symbol table, they
1490 may end up being added as regular symbols by operand(), and then
1491 make it to the object file as undefined in case they're not
1492 regarded as local symbols. They're local in o32, since `$' is a
1493 local symbol prefix, but not in n32 or n64. */
1494 for (i
= 0; i
< 8; i
++)
1498 sprintf (buf
, "$fcc%i", i
);
1499 symbol_table_insert (symbol_new (buf
, reg_section
, -1,
1500 &zero_address_frag
));
1503 mips_no_prev_insn ();
1506 mips_cprmask
[0] = 0;
1507 mips_cprmask
[1] = 0;
1508 mips_cprmask
[2] = 0;
1509 mips_cprmask
[3] = 0;
1511 /* set the default alignment for the text section (2**2) */
1512 record_alignment (text_section
, 2);
1514 bfd_set_gp_size (stdoutput
, g_switch_value
);
1516 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
1518 /* On a native system, sections must be aligned to 16 byte
1519 boundaries. When configured for an embedded ELF target, we
1521 if (strcmp (TARGET_OS
, "elf") != 0)
1523 (void) bfd_set_section_alignment (stdoutput
, text_section
, 4);
1524 (void) bfd_set_section_alignment (stdoutput
, data_section
, 4);
1525 (void) bfd_set_section_alignment (stdoutput
, bss_section
, 4);
1528 /* Create a .reginfo section for register masks and a .mdebug
1529 section for debugging information. */
1537 subseg
= now_subseg
;
1539 /* The ABI says this section should be loaded so that the
1540 running program can access it. However, we don't load it
1541 if we are configured for an embedded target */
1542 flags
= SEC_READONLY
| SEC_DATA
;
1543 if (strcmp (TARGET_OS
, "elf") != 0)
1544 flags
|= SEC_ALLOC
| SEC_LOAD
;
1546 if (mips_abi
!= N64_ABI
)
1548 sec
= subseg_new (".reginfo", (subsegT
) 0);
1550 bfd_set_section_flags (stdoutput
, sec
, flags
);
1551 bfd_set_section_alignment (stdoutput
, sec
, HAVE_NEWABI
? 3 : 2);
1554 mips_regmask_frag
= frag_more (sizeof (Elf32_External_RegInfo
));
1559 /* The 64-bit ABI uses a .MIPS.options section rather than
1560 .reginfo section. */
1561 sec
= subseg_new (".MIPS.options", (subsegT
) 0);
1562 bfd_set_section_flags (stdoutput
, sec
, flags
);
1563 bfd_set_section_alignment (stdoutput
, sec
, 3);
1566 /* Set up the option header. */
1568 Elf_Internal_Options opthdr
;
1571 opthdr
.kind
= ODK_REGINFO
;
1572 opthdr
.size
= (sizeof (Elf_External_Options
)
1573 + sizeof (Elf64_External_RegInfo
));
1576 f
= frag_more (sizeof (Elf_External_Options
));
1577 bfd_mips_elf_swap_options_out (stdoutput
, &opthdr
,
1578 (Elf_External_Options
*) f
);
1580 mips_regmask_frag
= frag_more (sizeof (Elf64_External_RegInfo
));
1585 if (ECOFF_DEBUGGING
)
1587 sec
= subseg_new (".mdebug", (subsegT
) 0);
1588 (void) bfd_set_section_flags (stdoutput
, sec
,
1589 SEC_HAS_CONTENTS
| SEC_READONLY
);
1590 (void) bfd_set_section_alignment (stdoutput
, sec
, 2);
1593 else if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
&& mips_flag_pdr
)
1595 pdr_seg
= subseg_new (".pdr", (subsegT
) 0);
1596 (void) bfd_set_section_flags (stdoutput
, pdr_seg
,
1597 SEC_READONLY
| SEC_RELOC
1599 (void) bfd_set_section_alignment (stdoutput
, pdr_seg
, 2);
1603 subseg_set (seg
, subseg
);
1607 if (! ECOFF_DEBUGGING
)
1610 if (mips_fix_vr4120
)
1611 init_vr4120_conflicts ();
1617 if (! ECOFF_DEBUGGING
)
1622 md_assemble (char *str
)
1624 struct mips_cl_insn insn
;
1625 bfd_reloc_code_real_type unused_reloc
[3]
1626 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
1628 imm_expr
.X_op
= O_absent
;
1629 imm2_expr
.X_op
= O_absent
;
1630 offset_expr
.X_op
= O_absent
;
1631 imm_reloc
[0] = BFD_RELOC_UNUSED
;
1632 imm_reloc
[1] = BFD_RELOC_UNUSED
;
1633 imm_reloc
[2] = BFD_RELOC_UNUSED
;
1634 offset_reloc
[0] = BFD_RELOC_UNUSED
;
1635 offset_reloc
[1] = BFD_RELOC_UNUSED
;
1636 offset_reloc
[2] = BFD_RELOC_UNUSED
;
1638 if (mips_opts
.mips16
)
1639 mips16_ip (str
, &insn
);
1642 mips_ip (str
, &insn
);
1643 DBG ((_("returned from mips_ip(%s) insn_opcode = 0x%x\n"),
1644 str
, insn
.insn_opcode
));
1649 as_bad ("%s `%s'", insn_error
, str
);
1653 if (insn
.insn_mo
->pinfo
== INSN_MACRO
)
1656 if (mips_opts
.mips16
)
1657 mips16_macro (&insn
);
1664 if (imm_expr
.X_op
!= O_absent
)
1665 append_insn (&insn
, &imm_expr
, imm_reloc
);
1666 else if (offset_expr
.X_op
!= O_absent
)
1667 append_insn (&insn
, &offset_expr
, offset_reloc
);
1669 append_insn (&insn
, NULL
, unused_reloc
);
1673 /* Return true if the given relocation might need a matching %lo().
1674 Note that R_MIPS_GOT16 relocations only need a matching %lo() when
1675 applied to local symbols. */
1677 static inline bfd_boolean
1678 reloc_needs_lo_p (bfd_reloc_code_real_type reloc
)
1680 return (HAVE_IN_PLACE_ADDENDS
1681 && (reloc
== BFD_RELOC_HI16_S
1682 || reloc
== BFD_RELOC_MIPS_GOT16
1683 || reloc
== BFD_RELOC_MIPS16_HI16_S
));
1686 /* Return true if the given fixup is followed by a matching R_MIPS_LO16
1689 static inline bfd_boolean
1690 fixup_has_matching_lo_p (fixS
*fixp
)
1692 return (fixp
->fx_next
!= NULL
1693 && (fixp
->fx_next
->fx_r_type
== BFD_RELOC_LO16
1694 || fixp
->fx_next
->fx_r_type
== BFD_RELOC_MIPS16_LO16
)
1695 && fixp
->fx_addsy
== fixp
->fx_next
->fx_addsy
1696 && fixp
->fx_offset
== fixp
->fx_next
->fx_offset
);
1699 /* See whether instruction IP reads register REG. CLASS is the type
1703 insn_uses_reg (const struct mips_cl_insn
*ip
, unsigned int reg
,
1704 enum mips_regclass
class)
1706 if (class == MIPS16_REG
)
1708 assert (mips_opts
.mips16
);
1709 reg
= mips16_to_32_reg_map
[reg
];
1710 class = MIPS_GR_REG
;
1713 /* Don't report on general register ZERO, since it never changes. */
1714 if (class == MIPS_GR_REG
&& reg
== ZERO
)
1717 if (class == MIPS_FP_REG
)
1719 assert (! mips_opts
.mips16
);
1720 /* If we are called with either $f0 or $f1, we must check $f0.
1721 This is not optimal, because it will introduce an unnecessary
1722 NOP between "lwc1 $f0" and "swc1 $f1". To fix this we would
1723 need to distinguish reading both $f0 and $f1 or just one of
1724 them. Note that we don't have to check the other way,
1725 because there is no instruction that sets both $f0 and $f1
1726 and requires a delay. */
1727 if ((ip
->insn_mo
->pinfo
& INSN_READ_FPR_S
)
1728 && ((EXTRACT_OPERAND (FS
, *ip
) & ~(unsigned) 1)
1729 == (reg
&~ (unsigned) 1)))
1731 if ((ip
->insn_mo
->pinfo
& INSN_READ_FPR_T
)
1732 && ((EXTRACT_OPERAND (FT
, *ip
) & ~(unsigned) 1)
1733 == (reg
&~ (unsigned) 1)))
1736 else if (! mips_opts
.mips16
)
1738 if ((ip
->insn_mo
->pinfo
& INSN_READ_GPR_S
)
1739 && EXTRACT_OPERAND (RS
, *ip
) == reg
)
1741 if ((ip
->insn_mo
->pinfo
& INSN_READ_GPR_T
)
1742 && EXTRACT_OPERAND (RT
, *ip
) == reg
)
1747 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_X
)
1748 && mips16_to_32_reg_map
[MIPS16_EXTRACT_OPERAND (RX
, *ip
)] == reg
)
1750 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_Y
)
1751 && mips16_to_32_reg_map
[MIPS16_EXTRACT_OPERAND (RY
, *ip
)] == reg
)
1753 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_Z
)
1754 && (mips16_to_32_reg_map
[MIPS16_EXTRACT_OPERAND (MOVE32Z
, *ip
)]
1757 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_T
) && reg
== TREG
)
1759 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_SP
) && reg
== SP
)
1761 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_31
) && reg
== RA
)
1763 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_GPR_X
)
1764 && MIPS16_EXTRACT_OPERAND (REGR32
, *ip
) == reg
)
1771 /* This function returns true if modifying a register requires a
1775 reg_needs_delay (unsigned int reg
)
1777 unsigned long prev_pinfo
;
1779 prev_pinfo
= history
[0].insn_mo
->pinfo
;
1780 if (! mips_opts
.noreorder
1781 && (((prev_pinfo
& INSN_LOAD_MEMORY_DELAY
)
1782 && ! gpr_interlocks
)
1783 || ((prev_pinfo
& INSN_LOAD_COPROC_DELAY
)
1784 && ! cop_interlocks
)))
1786 /* A load from a coprocessor or from memory. All load delays
1787 delay the use of general register rt for one instruction. */
1788 /* Itbl support may require additional care here. */
1789 know (prev_pinfo
& INSN_WRITE_GPR_T
);
1790 if (reg
== EXTRACT_OPERAND (RT
, history
[0]))
1797 /* Move all labels in insn_labels to the current insertion point. */
1800 mips_move_labels (void)
1802 struct insn_label_list
*l
;
1805 for (l
= insn_labels
; l
!= NULL
; l
= l
->next
)
1807 assert (S_GET_SEGMENT (l
->label
) == now_seg
);
1808 symbol_set_frag (l
->label
, frag_now
);
1809 val
= (valueT
) frag_now_fix ();
1810 /* mips16 text labels are stored as odd. */
1811 if (mips_opts
.mips16
)
1813 S_SET_VALUE (l
->label
, val
);
1817 /* Mark instruction labels in mips16 mode. This permits the linker to
1818 handle them specially, such as generating jalx instructions when
1819 needed. We also make them odd for the duration of the assembly, in
1820 order to generate the right sort of code. We will make them even
1821 in the adjust_symtab routine, while leaving them marked. This is
1822 convenient for the debugger and the disassembler. The linker knows
1823 to make them odd again. */
1826 mips16_mark_labels (void)
1828 if (mips_opts
.mips16
)
1830 struct insn_label_list
*l
;
1833 for (l
= insn_labels
; l
!= NULL
; l
= l
->next
)
1836 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
1837 S_SET_OTHER (l
->label
, STO_MIPS16
);
1839 val
= S_GET_VALUE (l
->label
);
1841 S_SET_VALUE (l
->label
, val
+ 1);
1846 /* End the current frag. Make it a variant frag and record the
1850 relax_close_frag (void)
1852 mips_macro_warning
.first_frag
= frag_now
;
1853 frag_var (rs_machine_dependent
, 0, 0,
1854 RELAX_ENCODE (mips_relax
.sizes
[0], mips_relax
.sizes
[1]),
1855 mips_relax
.symbol
, 0, (char *) mips_relax
.first_fixup
);
1857 memset (&mips_relax
.sizes
, 0, sizeof (mips_relax
.sizes
));
1858 mips_relax
.first_fixup
= 0;
1861 /* Start a new relaxation sequence whose expansion depends on SYMBOL.
1862 See the comment above RELAX_ENCODE for more details. */
1865 relax_start (symbolS
*symbol
)
1867 assert (mips_relax
.sequence
== 0);
1868 mips_relax
.sequence
= 1;
1869 mips_relax
.symbol
= symbol
;
1872 /* Start generating the second version of a relaxable sequence.
1873 See the comment above RELAX_ENCODE for more details. */
1878 assert (mips_relax
.sequence
== 1);
1879 mips_relax
.sequence
= 2;
1882 /* End the current relaxable sequence. */
1887 assert (mips_relax
.sequence
== 2);
1888 relax_close_frag ();
1889 mips_relax
.sequence
= 0;
1892 /* Classify an instruction according to the FIX_VR4120_* enumeration.
1893 Return NUM_FIX_VR4120_CLASSES if the instruction isn't affected
1894 by VR4120 errata. */
1897 classify_vr4120_insn (const char *name
)
1899 if (strncmp (name
, "macc", 4) == 0)
1900 return FIX_VR4120_MACC
;
1901 if (strncmp (name
, "dmacc", 5) == 0)
1902 return FIX_VR4120_DMACC
;
1903 if (strncmp (name
, "mult", 4) == 0)
1904 return FIX_VR4120_MULT
;
1905 if (strncmp (name
, "dmult", 5) == 0)
1906 return FIX_VR4120_DMULT
;
1907 if (strstr (name
, "div"))
1908 return FIX_VR4120_DIV
;
1909 if (strcmp (name
, "mtlo") == 0 || strcmp (name
, "mthi") == 0)
1910 return FIX_VR4120_MTHILO
;
1911 return NUM_FIX_VR4120_CLASSES
;
1914 /* Return the number of instructions that must separate INSN1 and INSN2,
1915 where INSN1 is the earlier instruction. Return the worst-case value
1916 for any INSN2 if INSN2 is null. */
1919 insns_between (const struct mips_cl_insn
*insn1
,
1920 const struct mips_cl_insn
*insn2
)
1922 unsigned long pinfo1
, pinfo2
;
1924 /* This function needs to know which pinfo flags are set for INSN2
1925 and which registers INSN2 uses. The former is stored in PINFO2 and
1926 the latter is tested via INSN2_USES_REG. If INSN2 is null, PINFO2
1927 will have every flag set and INSN2_USES_REG will always return true. */
1928 pinfo1
= insn1
->insn_mo
->pinfo
;
1929 pinfo2
= insn2
? insn2
->insn_mo
->pinfo
: ~0U;
1931 #define INSN2_USES_REG(REG, CLASS) \
1932 (insn2 == NULL || insn_uses_reg (insn2, REG, CLASS))
1934 /* For most targets, write-after-read dependencies on the HI and LO
1935 registers must be separated by at least two instructions. */
1936 if (!hilo_interlocks
)
1938 if ((pinfo1
& INSN_READ_LO
) && (pinfo2
& INSN_WRITE_LO
))
1940 if ((pinfo1
& INSN_READ_HI
) && (pinfo2
& INSN_WRITE_HI
))
1944 /* If we're working around r7000 errata, there must be two instructions
1945 between an mfhi or mflo and any instruction that uses the result. */
1946 if (mips_7000_hilo_fix
1947 && MF_HILO_INSN (pinfo1
)
1948 && INSN2_USES_REG (EXTRACT_OPERAND (RD
, *insn1
), MIPS_GR_REG
))
1951 /* If working around VR4120 errata, check for combinations that need
1952 a single intervening instruction. */
1953 if (mips_fix_vr4120
)
1955 unsigned int class1
, class2
;
1957 class1
= classify_vr4120_insn (insn1
->insn_mo
->name
);
1958 if (class1
!= NUM_FIX_VR4120_CLASSES
&& vr4120_conflicts
[class1
] != 0)
1962 class2
= classify_vr4120_insn (insn2
->insn_mo
->name
);
1963 if (vr4120_conflicts
[class1
] & (1 << class2
))
1968 if (!mips_opts
.mips16
)
1970 /* Check for GPR or coprocessor load delays. All such delays
1971 are on the RT register. */
1972 /* Itbl support may require additional care here. */
1973 if ((!gpr_interlocks
&& (pinfo1
& INSN_LOAD_MEMORY_DELAY
))
1974 || (!cop_interlocks
&& (pinfo1
& INSN_LOAD_COPROC_DELAY
)))
1976 know (pinfo1
& INSN_WRITE_GPR_T
);
1977 if (INSN2_USES_REG (EXTRACT_OPERAND (RT
, *insn1
), MIPS_GR_REG
))
1981 /* Check for generic coprocessor hazards.
1983 This case is not handled very well. There is no special
1984 knowledge of CP0 handling, and the coprocessors other than
1985 the floating point unit are not distinguished at all. */
1986 /* Itbl support may require additional care here. FIXME!
1987 Need to modify this to include knowledge about
1988 user specified delays! */
1989 else if ((!cop_interlocks
&& (pinfo1
& INSN_COPROC_MOVE_DELAY
))
1990 || (!cop_mem_interlocks
&& (pinfo1
& INSN_COPROC_MEMORY_DELAY
)))
1992 /* Handle cases where INSN1 writes to a known general coprocessor
1993 register. There must be a one instruction delay before INSN2
1994 if INSN2 reads that register, otherwise no delay is needed. */
1995 if (pinfo1
& INSN_WRITE_FPR_T
)
1997 if (INSN2_USES_REG (EXTRACT_OPERAND (FT
, *insn1
), MIPS_FP_REG
))
2000 else if (pinfo1
& INSN_WRITE_FPR_S
)
2002 if (INSN2_USES_REG (EXTRACT_OPERAND (FS
, *insn1
), MIPS_FP_REG
))
2007 /* Read-after-write dependencies on the control registers
2008 require a two-instruction gap. */
2009 if ((pinfo1
& INSN_WRITE_COND_CODE
)
2010 && (pinfo2
& INSN_READ_COND_CODE
))
2013 /* We don't know exactly what INSN1 does. If INSN2 is
2014 also a coprocessor instruction, assume there must be
2015 a one instruction gap. */
2016 if (pinfo2
& INSN_COP
)
2021 /* Check for read-after-write dependencies on the coprocessor
2022 control registers in cases where INSN1 does not need a general
2023 coprocessor delay. This means that INSN1 is a floating point
2024 comparison instruction. */
2025 /* Itbl support may require additional care here. */
2026 else if (!cop_interlocks
2027 && (pinfo1
& INSN_WRITE_COND_CODE
)
2028 && (pinfo2
& INSN_READ_COND_CODE
))
2032 #undef INSN2_USES_REG
2037 /* Return the number of nops that would be needed to work around the
2038 VR4130 mflo/mfhi errata if instruction INSN immediately followed
2039 the MAX_VR4130_NOPS instructions described by HISTORY. */
2042 nops_for_vr4130 (const struct mips_cl_insn
*history
,
2043 const struct mips_cl_insn
*insn
)
2047 /* Check if the instruction writes to HI or LO. MTHI and MTLO
2048 are not affected by the errata. */
2050 && ((insn
->insn_mo
->pinfo
& (INSN_WRITE_HI
| INSN_WRITE_LO
)) == 0
2051 || strcmp (insn
->insn_mo
->name
, "mtlo") == 0
2052 || strcmp (insn
->insn_mo
->name
, "mthi") == 0))
2055 /* Search for the first MFLO or MFHI. */
2056 for (i
= 0; i
< MAX_VR4130_NOPS
; i
++)
2057 if (!history
[i
].noreorder_p
&& MF_HILO_INSN (history
[i
].insn_mo
->pinfo
))
2059 /* Extract the destination register. */
2060 if (mips_opts
.mips16
)
2061 reg
= mips16_to_32_reg_map
[MIPS16_EXTRACT_OPERAND (RX
, history
[i
])];
2063 reg
= EXTRACT_OPERAND (RD
, history
[i
]);
2065 /* No nops are needed if INSN reads that register. */
2066 if (insn
!= NULL
&& insn_uses_reg (insn
, reg
, MIPS_GR_REG
))
2069 /* ...or if any of the intervening instructions do. */
2070 for (j
= 0; j
< i
; j
++)
2071 if (insn_uses_reg (&history
[j
], reg
, MIPS_GR_REG
))
2074 return MAX_VR4130_NOPS
- i
;
2079 /* Return the number of nops that would be needed if instruction INSN
2080 immediately followed the MAX_NOPS instructions given by HISTORY,
2081 where HISTORY[0] is the most recent instruction. If INSN is null,
2082 return the worse-case number of nops for any instruction. */
2085 nops_for_insn (const struct mips_cl_insn
*history
,
2086 const struct mips_cl_insn
*insn
)
2088 int i
, nops
, tmp_nops
;
2091 for (i
= 0; i
< MAX_DELAY_NOPS
; i
++)
2092 if (!history
[i
].noreorder_p
)
2094 tmp_nops
= insns_between (history
+ i
, insn
) - i
;
2095 if (tmp_nops
> nops
)
2099 if (mips_fix_vr4130
)
2101 tmp_nops
= nops_for_vr4130 (history
, insn
);
2102 if (tmp_nops
> nops
)
2109 /* The variable arguments provide NUM_INSNS extra instructions that
2110 might be added to HISTORY. Return the largest number of nops that
2111 would be needed after the extended sequence. */
2114 nops_for_sequence (int num_insns
, const struct mips_cl_insn
*history
, ...)
2117 struct mips_cl_insn buffer
[MAX_NOPS
];
2118 struct mips_cl_insn
*cursor
;
2121 va_start (args
, history
);
2122 cursor
= buffer
+ num_insns
;
2123 memcpy (cursor
, history
, (MAX_NOPS
- num_insns
) * sizeof (*cursor
));
2124 while (cursor
> buffer
)
2125 *--cursor
= *va_arg (args
, const struct mips_cl_insn
*);
2127 nops
= nops_for_insn (buffer
, NULL
);
2132 /* Like nops_for_insn, but if INSN is a branch, take into account the
2133 worst-case delay for the branch target. */
2136 nops_for_insn_or_target (const struct mips_cl_insn
*history
,
2137 const struct mips_cl_insn
*insn
)
2141 nops
= nops_for_insn (history
, insn
);
2142 if (insn
->insn_mo
->pinfo
& (INSN_UNCOND_BRANCH_DELAY
2143 | INSN_COND_BRANCH_DELAY
2144 | INSN_COND_BRANCH_LIKELY
))
2146 tmp_nops
= nops_for_sequence (2, history
, insn
, NOP_INSN
);
2147 if (tmp_nops
> nops
)
2150 else if (mips_opts
.mips16
&& (insn
->insn_mo
->pinfo
& MIPS16_INSN_BRANCH
))
2152 tmp_nops
= nops_for_sequence (1, history
, insn
);
2153 if (tmp_nops
> nops
)
2159 /* Output an instruction. IP is the instruction information.
2160 ADDRESS_EXPR is an operand of the instruction to be used with
2164 append_insn (struct mips_cl_insn
*ip
, expressionS
*address_expr
,
2165 bfd_reloc_code_real_type
*reloc_type
)
2167 register unsigned long prev_pinfo
, pinfo
;
2168 relax_stateT prev_insn_frag_type
= 0;
2169 bfd_boolean relaxed_branch
= FALSE
;
2171 /* Mark instruction labels in mips16 mode. */
2172 mips16_mark_labels ();
2174 prev_pinfo
= history
[0].insn_mo
->pinfo
;
2175 pinfo
= ip
->insn_mo
->pinfo
;
2177 if (mips_relax
.sequence
!= 2 && !mips_opts
.noreorder
)
2179 /* There are a lot of optimizations we could do that we don't.
2180 In particular, we do not, in general, reorder instructions.
2181 If you use gcc with optimization, it will reorder
2182 instructions and generally do much more optimization then we
2183 do here; repeating all that work in the assembler would only
2184 benefit hand written assembly code, and does not seem worth
2186 int nops
= (mips_optimize
== 0
2187 ? nops_for_insn (history
, NULL
)
2188 : nops_for_insn_or_target (history
, ip
));
2192 unsigned long old_frag_offset
;
2195 old_frag
= frag_now
;
2196 old_frag_offset
= frag_now_fix ();
2198 for (i
= 0; i
< nops
; i
++)
2203 listing_prev_line ();
2204 /* We may be at the start of a variant frag. In case we
2205 are, make sure there is enough space for the frag
2206 after the frags created by listing_prev_line. The
2207 argument to frag_grow here must be at least as large
2208 as the argument to all other calls to frag_grow in
2209 this file. We don't have to worry about being in the
2210 middle of a variant frag, because the variants insert
2211 all needed nop instructions themselves. */
2215 mips_move_labels ();
2217 #ifndef NO_ECOFF_DEBUGGING
2218 if (ECOFF_DEBUGGING
)
2219 ecoff_fix_loc (old_frag
, old_frag_offset
);
2223 else if (mips_relax
.sequence
!= 2 && prev_nop_frag
!= NULL
)
2225 /* Work out how many nops in prev_nop_frag are needed by IP. */
2226 int nops
= nops_for_insn_or_target (history
, ip
);
2227 assert (nops
<= prev_nop_frag_holds
);
2229 /* Enforce NOPS as a minimum. */
2230 if (nops
> prev_nop_frag_required
)
2231 prev_nop_frag_required
= nops
;
2233 if (prev_nop_frag_holds
== prev_nop_frag_required
)
2235 /* Settle for the current number of nops. Update the history
2236 accordingly (for the benefit of any future .set reorder code). */
2237 prev_nop_frag
= NULL
;
2238 insert_into_history (prev_nop_frag_since
,
2239 prev_nop_frag_holds
, NOP_INSN
);
2243 /* Allow this instruction to replace one of the nops that was
2244 tentatively added to prev_nop_frag. */
2245 prev_nop_frag
->fr_fix
-= mips_opts
.mips16
? 2 : 4;
2246 prev_nop_frag_holds
--;
2247 prev_nop_frag_since
++;
2252 /* The value passed to dwarf2_emit_insn is the distance between
2253 the beginning of the current instruction and the address that
2254 should be recorded in the debug tables. For MIPS16 debug info
2255 we want to use ISA-encoded addresses, so we pass -1 for an
2256 address higher by one than the current. */
2257 dwarf2_emit_insn (mips_opts
.mips16
? -1 : 0);
2260 /* Record the frag type before frag_var. */
2261 if (history
[0].frag
)
2262 prev_insn_frag_type
= history
[0].frag
->fr_type
;
2265 && *reloc_type
== BFD_RELOC_16_PCREL_S2
2266 && (pinfo
& INSN_UNCOND_BRANCH_DELAY
|| pinfo
& INSN_COND_BRANCH_DELAY
2267 || pinfo
& INSN_COND_BRANCH_LIKELY
)
2268 && mips_relax_branch
2269 /* Don't try branch relaxation within .set nomacro, or within
2270 .set noat if we use $at for PIC computations. If it turns
2271 out that the branch was out-of-range, we'll get an error. */
2272 && !mips_opts
.warn_about_macros
2273 && !(mips_opts
.noat
&& mips_pic
!= NO_PIC
)
2274 && !mips_opts
.mips16
)
2276 relaxed_branch
= TRUE
;
2277 add_relaxed_insn (ip
, (relaxed_branch_length
2279 (pinfo
& INSN_UNCOND_BRANCH_DELAY
) ? -1
2280 : (pinfo
& INSN_COND_BRANCH_LIKELY
) ? 1
2283 (pinfo
& INSN_UNCOND_BRANCH_DELAY
,
2284 pinfo
& INSN_COND_BRANCH_LIKELY
,
2285 pinfo
& INSN_WRITE_GPR_31
,
2287 address_expr
->X_add_symbol
,
2288 address_expr
->X_add_number
);
2289 *reloc_type
= BFD_RELOC_UNUSED
;
2291 else if (*reloc_type
> BFD_RELOC_UNUSED
)
2293 /* We need to set up a variant frag. */
2294 assert (mips_opts
.mips16
&& address_expr
!= NULL
);
2295 add_relaxed_insn (ip
, 4, 0,
2297 (*reloc_type
- BFD_RELOC_UNUSED
,
2298 mips16_small
, mips16_ext
,
2299 prev_pinfo
& INSN_UNCOND_BRANCH_DELAY
,
2300 history
[0].mips16_absolute_jump_p
),
2301 make_expr_symbol (address_expr
), 0);
2303 else if (mips_opts
.mips16
2305 && *reloc_type
!= BFD_RELOC_MIPS16_JMP
)
2307 /* Make sure there is enough room to swap this instruction with
2308 a following jump instruction. */
2310 add_fixed_insn (ip
);
2314 if (mips_opts
.mips16
2315 && mips_opts
.noreorder
2316 && (prev_pinfo
& INSN_UNCOND_BRANCH_DELAY
) != 0)
2317 as_warn (_("extended instruction in delay slot"));
2319 if (mips_relax
.sequence
)
2321 /* If we've reached the end of this frag, turn it into a variant
2322 frag and record the information for the instructions we've
2324 if (frag_room () < 4)
2325 relax_close_frag ();
2326 mips_relax
.sizes
[mips_relax
.sequence
- 1] += 4;
2329 if (mips_relax
.sequence
!= 2)
2330 mips_macro_warning
.sizes
[0] += 4;
2331 if (mips_relax
.sequence
!= 1)
2332 mips_macro_warning
.sizes
[1] += 4;
2334 if (mips_opts
.mips16
)
2337 ip
->mips16_absolute_jump_p
= (*reloc_type
== BFD_RELOC_MIPS16_JMP
);
2339 add_fixed_insn (ip
);
2342 if (address_expr
!= NULL
&& *reloc_type
<= BFD_RELOC_UNUSED
)
2344 if (address_expr
->X_op
== O_constant
)
2348 switch (*reloc_type
)
2351 ip
->insn_opcode
|= address_expr
->X_add_number
;
2354 case BFD_RELOC_MIPS_HIGHEST
:
2355 tmp
= (address_expr
->X_add_number
+ 0x800080008000ull
) >> 48;
2356 ip
->insn_opcode
|= tmp
& 0xffff;
2359 case BFD_RELOC_MIPS_HIGHER
:
2360 tmp
= (address_expr
->X_add_number
+ 0x80008000ull
) >> 32;
2361 ip
->insn_opcode
|= tmp
& 0xffff;
2364 case BFD_RELOC_HI16_S
:
2365 tmp
= (address_expr
->X_add_number
+ 0x8000) >> 16;
2366 ip
->insn_opcode
|= tmp
& 0xffff;
2369 case BFD_RELOC_HI16
:
2370 ip
->insn_opcode
|= (address_expr
->X_add_number
>> 16) & 0xffff;
2373 case BFD_RELOC_UNUSED
:
2374 case BFD_RELOC_LO16
:
2375 case BFD_RELOC_MIPS_GOT_DISP
:
2376 ip
->insn_opcode
|= address_expr
->X_add_number
& 0xffff;
2379 case BFD_RELOC_MIPS_JMP
:
2380 if ((address_expr
->X_add_number
& 3) != 0)
2381 as_bad (_("jump to misaligned address (0x%lx)"),
2382 (unsigned long) address_expr
->X_add_number
);
2383 if (address_expr
->X_add_number
& ~0xfffffff)
2384 as_bad (_("jump address range overflow (0x%lx)"),
2385 (unsigned long) address_expr
->X_add_number
);
2386 ip
->insn_opcode
|= (address_expr
->X_add_number
>> 2) & 0x3ffffff;
2389 case BFD_RELOC_MIPS16_JMP
:
2390 if ((address_expr
->X_add_number
& 3) != 0)
2391 as_bad (_("jump to misaligned address (0x%lx)"),
2392 (unsigned long) address_expr
->X_add_number
);
2393 if (address_expr
->X_add_number
& ~0xfffffff)
2394 as_bad (_("jump address range overflow (0x%lx)"),
2395 (unsigned long) address_expr
->X_add_number
);
2397 (((address_expr
->X_add_number
& 0x7c0000) << 3)
2398 | ((address_expr
->X_add_number
& 0xf800000) >> 7)
2399 | ((address_expr
->X_add_number
& 0x3fffc) >> 2));
2402 case BFD_RELOC_16_PCREL_S2
:
2409 else if (*reloc_type
< BFD_RELOC_UNUSED
)
2412 reloc_howto_type
*howto
;
2415 /* In a compound relocation, it is the final (outermost)
2416 operator that determines the relocated field. */
2417 for (i
= 1; i
< 3; i
++)
2418 if (reloc_type
[i
] == BFD_RELOC_UNUSED
)
2421 howto
= bfd_reloc_type_lookup (stdoutput
, reloc_type
[i
- 1]);
2422 ip
->fixp
[0] = fix_new_exp (ip
->frag
, ip
->where
,
2423 bfd_get_reloc_size (howto
),
2425 reloc_type
[0] == BFD_RELOC_16_PCREL_S2
,
2428 /* These relocations can have an addend that won't fit in
2429 4 octets for 64bit assembly. */
2431 && ! howto
->partial_inplace
2432 && (reloc_type
[0] == BFD_RELOC_16
2433 || reloc_type
[0] == BFD_RELOC_32
2434 || reloc_type
[0] == BFD_RELOC_MIPS_JMP
2435 || reloc_type
[0] == BFD_RELOC_HI16_S
2436 || reloc_type
[0] == BFD_RELOC_LO16
2437 || reloc_type
[0] == BFD_RELOC_GPREL16
2438 || reloc_type
[0] == BFD_RELOC_MIPS_LITERAL
2439 || reloc_type
[0] == BFD_RELOC_GPREL32
2440 || reloc_type
[0] == BFD_RELOC_64
2441 || reloc_type
[0] == BFD_RELOC_CTOR
2442 || reloc_type
[0] == BFD_RELOC_MIPS_SUB
2443 || reloc_type
[0] == BFD_RELOC_MIPS_HIGHEST
2444 || reloc_type
[0] == BFD_RELOC_MIPS_HIGHER
2445 || reloc_type
[0] == BFD_RELOC_MIPS_SCN_DISP
2446 || reloc_type
[0] == BFD_RELOC_MIPS_REL16
2447 || reloc_type
[0] == BFD_RELOC_MIPS_RELGOT
2448 || reloc_type
[0] == BFD_RELOC_MIPS16_GPREL
2449 || reloc_type
[0] == BFD_RELOC_MIPS16_HI16_S
2450 || reloc_type
[0] == BFD_RELOC_MIPS16_LO16
))
2451 ip
->fixp
[0]->fx_no_overflow
= 1;
2453 if (mips_relax
.sequence
)
2455 if (mips_relax
.first_fixup
== 0)
2456 mips_relax
.first_fixup
= ip
->fixp
[0];
2458 else if (reloc_needs_lo_p (*reloc_type
))
2460 struct mips_hi_fixup
*hi_fixup
;
2462 /* Reuse the last entry if it already has a matching %lo. */
2463 hi_fixup
= mips_hi_fixup_list
;
2465 || !fixup_has_matching_lo_p (hi_fixup
->fixp
))
2467 hi_fixup
= ((struct mips_hi_fixup
*)
2468 xmalloc (sizeof (struct mips_hi_fixup
)));
2469 hi_fixup
->next
= mips_hi_fixup_list
;
2470 mips_hi_fixup_list
= hi_fixup
;
2472 hi_fixup
->fixp
= ip
->fixp
[0];
2473 hi_fixup
->seg
= now_seg
;
2476 /* Add fixups for the second and third relocations, if given.
2477 Note that the ABI allows the second relocation to be
2478 against RSS_UNDEF, RSS_GP, RSS_GP0 or RSS_LOC. At the
2479 moment we only use RSS_UNDEF, but we could add support
2480 for the others if it ever becomes necessary. */
2481 for (i
= 1; i
< 3; i
++)
2482 if (reloc_type
[i
] != BFD_RELOC_UNUSED
)
2484 ip
->fixp
[i
] = fix_new (ip
->frag
, ip
->where
,
2485 ip
->fixp
[0]->fx_size
, NULL
, 0,
2486 FALSE
, reloc_type
[i
]);
2488 /* Use fx_tcbit to mark compound relocs. */
2489 ip
->fixp
[0]->fx_tcbit
= 1;
2490 ip
->fixp
[i
]->fx_tcbit
= 1;
2496 /* Update the register mask information. */
2497 if (! mips_opts
.mips16
)
2499 if (pinfo
& INSN_WRITE_GPR_D
)
2500 mips_gprmask
|= 1 << EXTRACT_OPERAND (RD
, *ip
);
2501 if ((pinfo
& (INSN_WRITE_GPR_T
| INSN_READ_GPR_T
)) != 0)
2502 mips_gprmask
|= 1 << EXTRACT_OPERAND (RT
, *ip
);
2503 if (pinfo
& INSN_READ_GPR_S
)
2504 mips_gprmask
|= 1 << EXTRACT_OPERAND (RS
, *ip
);
2505 if (pinfo
& INSN_WRITE_GPR_31
)
2506 mips_gprmask
|= 1 << RA
;
2507 if (pinfo
& INSN_WRITE_FPR_D
)
2508 mips_cprmask
[1] |= 1 << EXTRACT_OPERAND (FD
, *ip
);
2509 if ((pinfo
& (INSN_WRITE_FPR_S
| INSN_READ_FPR_S
)) != 0)
2510 mips_cprmask
[1] |= 1 << EXTRACT_OPERAND (FS
, *ip
);
2511 if ((pinfo
& (INSN_WRITE_FPR_T
| INSN_READ_FPR_T
)) != 0)
2512 mips_cprmask
[1] |= 1 << EXTRACT_OPERAND (FT
, *ip
);
2513 if ((pinfo
& INSN_READ_FPR_R
) != 0)
2514 mips_cprmask
[1] |= 1 << EXTRACT_OPERAND (FR
, *ip
);
2515 if (pinfo
& INSN_COP
)
2517 /* We don't keep enough information to sort these cases out.
2518 The itbl support does keep this information however, although
2519 we currently don't support itbl fprmats as part of the cop
2520 instruction. May want to add this support in the future. */
2522 /* Never set the bit for $0, which is always zero. */
2523 mips_gprmask
&= ~1 << 0;
2527 if (pinfo
& (MIPS16_INSN_WRITE_X
| MIPS16_INSN_READ_X
))
2528 mips_gprmask
|= 1 << MIPS16_EXTRACT_OPERAND (RX
, *ip
);
2529 if (pinfo
& (MIPS16_INSN_WRITE_Y
| MIPS16_INSN_READ_Y
))
2530 mips_gprmask
|= 1 << MIPS16_EXTRACT_OPERAND (RY
, *ip
);
2531 if (pinfo
& MIPS16_INSN_WRITE_Z
)
2532 mips_gprmask
|= 1 << MIPS16_EXTRACT_OPERAND (RZ
, *ip
);
2533 if (pinfo
& (MIPS16_INSN_WRITE_T
| MIPS16_INSN_READ_T
))
2534 mips_gprmask
|= 1 << TREG
;
2535 if (pinfo
& (MIPS16_INSN_WRITE_SP
| MIPS16_INSN_READ_SP
))
2536 mips_gprmask
|= 1 << SP
;
2537 if (pinfo
& (MIPS16_INSN_WRITE_31
| MIPS16_INSN_READ_31
))
2538 mips_gprmask
|= 1 << RA
;
2539 if (pinfo
& MIPS16_INSN_WRITE_GPR_Y
)
2540 mips_gprmask
|= 1 << MIPS16OP_EXTRACT_REG32R (ip
->insn_opcode
);
2541 if (pinfo
& MIPS16_INSN_READ_Z
)
2542 mips_gprmask
|= 1 << MIPS16_EXTRACT_OPERAND (MOVE32Z
, *ip
);
2543 if (pinfo
& MIPS16_INSN_READ_GPR_X
)
2544 mips_gprmask
|= 1 << MIPS16_EXTRACT_OPERAND (REGR32
, *ip
);
2547 if (mips_relax
.sequence
!= 2 && !mips_opts
.noreorder
)
2549 /* Filling the branch delay slot is more complex. We try to
2550 switch the branch with the previous instruction, which we can
2551 do if the previous instruction does not set up a condition
2552 that the branch tests and if the branch is not itself the
2553 target of any branch. */
2554 if ((pinfo
& INSN_UNCOND_BRANCH_DELAY
)
2555 || (pinfo
& INSN_COND_BRANCH_DELAY
))
2557 if (mips_optimize
< 2
2558 /* If we have seen .set volatile or .set nomove, don't
2560 || mips_opts
.nomove
!= 0
2561 /* We can't swap if the previous instruction's position
2563 || history
[0].fixed_p
2564 /* If the previous previous insn was in a .set
2565 noreorder, we can't swap. Actually, the MIPS
2566 assembler will swap in this situation. However, gcc
2567 configured -with-gnu-as will generate code like
2573 in which we can not swap the bne and INSN. If gcc is
2574 not configured -with-gnu-as, it does not output the
2576 || history
[1].noreorder_p
2577 /* If the branch is itself the target of a branch, we
2578 can not swap. We cheat on this; all we check for is
2579 whether there is a label on this instruction. If
2580 there are any branches to anything other than a
2581 label, users must use .set noreorder. */
2582 || insn_labels
!= NULL
2583 /* If the previous instruction is in a variant frag
2584 other than this branch's one, we cannot do the swap.
2585 This does not apply to the mips16, which uses variant
2586 frags for different purposes. */
2587 || (! mips_opts
.mips16
2588 && prev_insn_frag_type
== rs_machine_dependent
)
2589 /* Check for conflicts between the branch and the instructions
2590 before the candidate delay slot. */
2591 || nops_for_insn (history
+ 1, ip
) > 0
2592 /* Check for conflicts between the swapped sequence and the
2593 target of the branch. */
2594 || nops_for_sequence (2, history
+ 1, ip
, history
) > 0
2595 /* We do not swap with a trap instruction, since it
2596 complicates trap handlers to have the trap
2597 instruction be in a delay slot. */
2598 || (prev_pinfo
& INSN_TRAP
)
2599 /* If the branch reads a register that the previous
2600 instruction sets, we can not swap. */
2601 || (! mips_opts
.mips16
2602 && (prev_pinfo
& INSN_WRITE_GPR_T
)
2603 && insn_uses_reg (ip
, EXTRACT_OPERAND (RT
, history
[0]),
2605 || (! mips_opts
.mips16
2606 && (prev_pinfo
& INSN_WRITE_GPR_D
)
2607 && insn_uses_reg (ip
, EXTRACT_OPERAND (RD
, history
[0]),
2609 || (mips_opts
.mips16
2610 && (((prev_pinfo
& MIPS16_INSN_WRITE_X
)
2612 (ip
, MIPS16_EXTRACT_OPERAND (RX
, history
[0]),
2614 || ((prev_pinfo
& MIPS16_INSN_WRITE_Y
)
2616 (ip
, MIPS16_EXTRACT_OPERAND (RY
, history
[0]),
2618 || ((prev_pinfo
& MIPS16_INSN_WRITE_Z
)
2620 (ip
, MIPS16_EXTRACT_OPERAND (RZ
, history
[0]),
2622 || ((prev_pinfo
& MIPS16_INSN_WRITE_T
)
2623 && insn_uses_reg (ip
, TREG
, MIPS_GR_REG
))
2624 || ((prev_pinfo
& MIPS16_INSN_WRITE_31
)
2625 && insn_uses_reg (ip
, RA
, MIPS_GR_REG
))
2626 || ((prev_pinfo
& MIPS16_INSN_WRITE_GPR_Y
)
2627 && insn_uses_reg (ip
,
2628 MIPS16OP_EXTRACT_REG32R
2629 (history
[0].insn_opcode
),
2631 /* If the branch writes a register that the previous
2632 instruction sets, we can not swap (we know that
2633 branches write only to RD or to $31). */
2634 || (! mips_opts
.mips16
2635 && (prev_pinfo
& INSN_WRITE_GPR_T
)
2636 && (((pinfo
& INSN_WRITE_GPR_D
)
2637 && (EXTRACT_OPERAND (RT
, history
[0])
2638 == EXTRACT_OPERAND (RD
, *ip
)))
2639 || ((pinfo
& INSN_WRITE_GPR_31
)
2640 && EXTRACT_OPERAND (RT
, history
[0]) == RA
)))
2641 || (! mips_opts
.mips16
2642 && (prev_pinfo
& INSN_WRITE_GPR_D
)
2643 && (((pinfo
& INSN_WRITE_GPR_D
)
2644 && (EXTRACT_OPERAND (RD
, history
[0])
2645 == EXTRACT_OPERAND (RD
, *ip
)))
2646 || ((pinfo
& INSN_WRITE_GPR_31
)
2647 && EXTRACT_OPERAND (RD
, history
[0]) == RA
)))
2648 || (mips_opts
.mips16
2649 && (pinfo
& MIPS16_INSN_WRITE_31
)
2650 && ((prev_pinfo
& MIPS16_INSN_WRITE_31
)
2651 || ((prev_pinfo
& MIPS16_INSN_WRITE_GPR_Y
)
2652 && (MIPS16OP_EXTRACT_REG32R (history
[0].insn_opcode
)
2654 /* If the branch writes a register that the previous
2655 instruction reads, we can not swap (we know that
2656 branches only write to RD or to $31). */
2657 || (! mips_opts
.mips16
2658 && (pinfo
& INSN_WRITE_GPR_D
)
2659 && insn_uses_reg (&history
[0],
2660 EXTRACT_OPERAND (RD
, *ip
),
2662 || (! mips_opts
.mips16
2663 && (pinfo
& INSN_WRITE_GPR_31
)
2664 && insn_uses_reg (&history
[0], RA
, MIPS_GR_REG
))
2665 || (mips_opts
.mips16
2666 && (pinfo
& MIPS16_INSN_WRITE_31
)
2667 && insn_uses_reg (&history
[0], RA
, MIPS_GR_REG
))
2668 /* If one instruction sets a condition code and the
2669 other one uses a condition code, we can not swap. */
2670 || ((pinfo
& INSN_READ_COND_CODE
)
2671 && (prev_pinfo
& INSN_WRITE_COND_CODE
))
2672 || ((pinfo
& INSN_WRITE_COND_CODE
)
2673 && (prev_pinfo
& INSN_READ_COND_CODE
))
2674 /* If the previous instruction uses the PC, we can not
2676 || (mips_opts
.mips16
2677 && (prev_pinfo
& MIPS16_INSN_READ_PC
))
2678 /* If the previous instruction had a fixup in mips16
2679 mode, we can not swap. This normally means that the
2680 previous instruction was a 4 byte branch anyhow. */
2681 || (mips_opts
.mips16
&& history
[0].fixp
[0])
2682 /* If the previous instruction is a sync, sync.l, or
2683 sync.p, we can not swap. */
2684 || (prev_pinfo
& INSN_SYNC
))
2686 /* We could do even better for unconditional branches to
2687 portions of this object file; we could pick up the
2688 instruction at the destination, put it in the delay
2689 slot, and bump the destination address. */
2690 insert_into_history (0, 1, ip
);
2692 if (mips_relax
.sequence
)
2693 mips_relax
.sizes
[mips_relax
.sequence
- 1] += 4;
2697 /* It looks like we can actually do the swap. */
2698 struct mips_cl_insn delay
= history
[0];
2699 if (mips_opts
.mips16
)
2701 know (delay
.frag
== ip
->frag
);
2702 move_insn (ip
, delay
.frag
, delay
.where
);
2703 move_insn (&delay
, ip
->frag
, ip
->where
+ insn_length (ip
));
2705 else if (relaxed_branch
)
2707 /* Add the delay slot instruction to the end of the
2708 current frag and shrink the fixed part of the
2709 original frag. If the branch occupies the tail of
2710 the latter, move it backwards to cover the gap. */
2711 delay
.frag
->fr_fix
-= 4;
2712 if (delay
.frag
== ip
->frag
)
2713 move_insn (ip
, ip
->frag
, ip
->where
- 4);
2714 add_fixed_insn (&delay
);
2718 move_insn (&delay
, ip
->frag
, ip
->where
);
2719 move_insn (ip
, history
[0].frag
, history
[0].where
);
2723 insert_into_history (0, 1, &delay
);
2726 /* If that was an unconditional branch, forget the previous
2727 insn information. */
2728 if (pinfo
& INSN_UNCOND_BRANCH_DELAY
)
2729 mips_no_prev_insn ();
2731 else if (pinfo
& INSN_COND_BRANCH_LIKELY
)
2733 /* We don't yet optimize a branch likely. What we should do
2734 is look at the target, copy the instruction found there
2735 into the delay slot, and increment the branch to jump to
2736 the next instruction. */
2737 insert_into_history (0, 1, ip
);
2741 insert_into_history (0, 1, ip
);
2744 insert_into_history (0, 1, ip
);
2746 /* We just output an insn, so the next one doesn't have a label. */
2747 mips_clear_insn_labels ();
2750 /* Forget that there was any previous instruction or label. */
2753 mips_no_prev_insn (void)
2755 prev_nop_frag
= NULL
;
2756 insert_into_history (0, ARRAY_SIZE (history
), NOP_INSN
);
2757 mips_clear_insn_labels ();
2760 /* This function must be called before we emit something other than
2761 instructions. It is like mips_no_prev_insn except that it inserts
2762 any NOPS that might be needed by previous instructions. */
2765 mips_emit_delays (void)
2767 if (! mips_opts
.noreorder
)
2769 int nops
= nops_for_insn (history
, NULL
);
2773 add_fixed_insn (NOP_INSN
);
2774 mips_move_labels ();
2777 mips_no_prev_insn ();
2780 /* Start a (possibly nested) noreorder block. */
2783 start_noreorder (void)
2785 if (mips_opts
.noreorder
== 0)
2790 /* None of the instructions before the .set noreorder can be moved. */
2791 for (i
= 0; i
< ARRAY_SIZE (history
); i
++)
2792 history
[i
].fixed_p
= 1;
2794 /* Insert any nops that might be needed between the .set noreorder
2795 block and the previous instructions. We will later remove any
2796 nops that turn out not to be needed. */
2797 nops
= nops_for_insn (history
, NULL
);
2800 if (mips_optimize
!= 0)
2802 /* Record the frag which holds the nop instructions, so
2803 that we can remove them if we don't need them. */
2804 frag_grow (mips_opts
.mips16
? nops
* 2 : nops
* 4);
2805 prev_nop_frag
= frag_now
;
2806 prev_nop_frag_holds
= nops
;
2807 prev_nop_frag_required
= 0;
2808 prev_nop_frag_since
= 0;
2811 for (; nops
> 0; --nops
)
2812 add_fixed_insn (NOP_INSN
);
2814 /* Move on to a new frag, so that it is safe to simply
2815 decrease the size of prev_nop_frag. */
2816 frag_wane (frag_now
);
2818 mips_move_labels ();
2820 mips16_mark_labels ();
2821 mips_clear_insn_labels ();
2823 mips_opts
.noreorder
++;
2824 mips_any_noreorder
= 1;
2827 /* End a nested noreorder block. */
2830 end_noreorder (void)
2832 mips_opts
.noreorder
--;
2833 if (mips_opts
.noreorder
== 0 && prev_nop_frag
!= NULL
)
2835 /* Commit to inserting prev_nop_frag_required nops and go back to
2836 handling nop insertion the .set reorder way. */
2837 prev_nop_frag
->fr_fix
-= ((prev_nop_frag_holds
- prev_nop_frag_required
)
2838 * (mips_opts
.mips16
? 2 : 4));
2839 insert_into_history (prev_nop_frag_since
,
2840 prev_nop_frag_required
, NOP_INSN
);
2841 prev_nop_frag
= NULL
;
2845 /* Set up global variables for the start of a new macro. */
2850 memset (&mips_macro_warning
.sizes
, 0, sizeof (mips_macro_warning
.sizes
));
2851 mips_macro_warning
.delay_slot_p
= (mips_opts
.noreorder
2852 && (history
[0].insn_mo
->pinfo
2853 & (INSN_UNCOND_BRANCH_DELAY
2854 | INSN_COND_BRANCH_DELAY
2855 | INSN_COND_BRANCH_LIKELY
)) != 0);
2858 /* Given that a macro is longer than 4 bytes, return the appropriate warning
2859 for it. Return null if no warning is needed. SUBTYPE is a bitmask of
2860 RELAX_DELAY_SLOT and RELAX_NOMACRO. */
2863 macro_warning (relax_substateT subtype
)
2865 if (subtype
& RELAX_DELAY_SLOT
)
2866 return _("Macro instruction expanded into multiple instructions"
2867 " in a branch delay slot");
2868 else if (subtype
& RELAX_NOMACRO
)
2869 return _("Macro instruction expanded into multiple instructions");
2874 /* Finish up a macro. Emit warnings as appropriate. */
2879 if (mips_macro_warning
.sizes
[0] > 4 || mips_macro_warning
.sizes
[1] > 4)
2881 relax_substateT subtype
;
2883 /* Set up the relaxation warning flags. */
2885 if (mips_macro_warning
.sizes
[1] > mips_macro_warning
.sizes
[0])
2886 subtype
|= RELAX_SECOND_LONGER
;
2887 if (mips_opts
.warn_about_macros
)
2888 subtype
|= RELAX_NOMACRO
;
2889 if (mips_macro_warning
.delay_slot_p
)
2890 subtype
|= RELAX_DELAY_SLOT
;
2892 if (mips_macro_warning
.sizes
[0] > 4 && mips_macro_warning
.sizes
[1] > 4)
2894 /* Either the macro has a single implementation or both
2895 implementations are longer than 4 bytes. Emit the
2897 const char *msg
= macro_warning (subtype
);
2903 /* One implementation might need a warning but the other
2904 definitely doesn't. */
2905 mips_macro_warning
.first_frag
->fr_subtype
|= subtype
;
2910 /* Read a macro's relocation codes from *ARGS and store them in *R.
2911 The first argument in *ARGS will be either the code for a single
2912 relocation or -1 followed by the three codes that make up a
2913 composite relocation. */
2916 macro_read_relocs (va_list *args
, bfd_reloc_code_real_type
*r
)
2920 next
= va_arg (*args
, int);
2922 r
[0] = (bfd_reloc_code_real_type
) next
;
2924 for (i
= 0; i
< 3; i
++)
2925 r
[i
] = (bfd_reloc_code_real_type
) va_arg (*args
, int);
2928 /* Build an instruction created by a macro expansion. This is passed
2929 a pointer to the count of instructions created so far, an
2930 expression, the name of the instruction to build, an operand format
2931 string, and corresponding arguments. */
2934 macro_build (expressionS
*ep
, const char *name
, const char *fmt
, ...)
2936 const struct mips_opcode
*mo
;
2937 struct mips_cl_insn insn
;
2938 bfd_reloc_code_real_type r
[3];
2941 va_start (args
, fmt
);
2943 if (mips_opts
.mips16
)
2945 mips16_macro_build (ep
, name
, fmt
, args
);
2950 r
[0] = BFD_RELOC_UNUSED
;
2951 r
[1] = BFD_RELOC_UNUSED
;
2952 r
[2] = BFD_RELOC_UNUSED
;
2953 mo
= (struct mips_opcode
*) hash_find (op_hash
, name
);
2955 assert (strcmp (name
, mo
->name
) == 0);
2957 /* Search until we get a match for NAME. It is assumed here that
2958 macros will never generate MDMX or MIPS-3D instructions. */
2959 while (strcmp (fmt
, mo
->args
) != 0
2960 || mo
->pinfo
== INSN_MACRO
2961 || !OPCODE_IS_MEMBER (mo
,
2963 | (file_ase_mips16
? INSN_MIPS16
: 0)),
2965 || (mips_opts
.arch
== CPU_R4650
&& (mo
->pinfo
& FP_D
) != 0))
2969 assert (strcmp (name
, mo
->name
) == 0);
2972 create_insn (&insn
, mo
);
2990 INSERT_OPERAND (SHAMT
, insn
, va_arg (args
, int));
2995 /* Note that in the macro case, these arguments are already
2996 in MSB form. (When handling the instruction in the
2997 non-macro case, these arguments are sizes from which
2998 MSB values must be calculated.) */
2999 INSERT_OPERAND (INSMSB
, insn
, va_arg (args
, int));
3005 /* Note that in the macro case, these arguments are already
3006 in MSBD form. (When handling the instruction in the
3007 non-macro case, these arguments are sizes from which
3008 MSBD values must be calculated.) */
3009 INSERT_OPERAND (EXTMSBD
, insn
, va_arg (args
, int));
3020 INSERT_OPERAND (RT
, insn
, va_arg (args
, int));
3024 INSERT_OPERAND (CODE
, insn
, va_arg (args
, int));
3029 INSERT_OPERAND (FT
, insn
, va_arg (args
, int));
3035 INSERT_OPERAND (RD
, insn
, va_arg (args
, int));
3040 int tmp
= va_arg (args
, int);
3042 INSERT_OPERAND (RT
, insn
, tmp
);
3043 INSERT_OPERAND (RD
, insn
, tmp
);
3049 INSERT_OPERAND (FS
, insn
, va_arg (args
, int));
3056 INSERT_OPERAND (SHAMT
, insn
, va_arg (args
, int));
3060 INSERT_OPERAND (FD
, insn
, va_arg (args
, int));
3064 INSERT_OPERAND (CODE20
, insn
, va_arg (args
, int));
3068 INSERT_OPERAND (CODE19
, insn
, va_arg (args
, int));
3072 INSERT_OPERAND (CODE2
, insn
, va_arg (args
, int));
3079 INSERT_OPERAND (RS
, insn
, va_arg (args
, int));
3085 macro_read_relocs (&args
, r
);
3086 assert (*r
== BFD_RELOC_GPREL16
3087 || *r
== BFD_RELOC_MIPS_LITERAL
3088 || *r
== BFD_RELOC_MIPS_HIGHER
3089 || *r
== BFD_RELOC_HI16_S
3090 || *r
== BFD_RELOC_LO16
3091 || *r
== BFD_RELOC_MIPS_GOT16
3092 || *r
== BFD_RELOC_MIPS_CALL16
3093 || *r
== BFD_RELOC_MIPS_GOT_DISP
3094 || *r
== BFD_RELOC_MIPS_GOT_PAGE
3095 || *r
== BFD_RELOC_MIPS_GOT_OFST
3096 || *r
== BFD_RELOC_MIPS_GOT_LO16
3097 || *r
== BFD_RELOC_MIPS_CALL_LO16
);
3101 macro_read_relocs (&args
, r
);
3103 && (ep
->X_op
== O_constant
3104 || (ep
->X_op
== O_symbol
3105 && (*r
== BFD_RELOC_MIPS_HIGHEST
3106 || *r
== BFD_RELOC_HI16_S
3107 || *r
== BFD_RELOC_HI16
3108 || *r
== BFD_RELOC_GPREL16
3109 || *r
== BFD_RELOC_MIPS_GOT_HI16
3110 || *r
== BFD_RELOC_MIPS_CALL_HI16
))));
3114 assert (ep
!= NULL
);
3116 * This allows macro() to pass an immediate expression for
3117 * creating short branches without creating a symbol.
3118 * Note that the expression still might come from the assembly
3119 * input, in which case the value is not checked for range nor
3120 * is a relocation entry generated (yuck).
3122 if (ep
->X_op
== O_constant
)
3124 insn
.insn_opcode
|= (ep
->X_add_number
>> 2) & 0xffff;
3128 *r
= BFD_RELOC_16_PCREL_S2
;
3132 assert (ep
!= NULL
);
3133 *r
= BFD_RELOC_MIPS_JMP
;
3137 insn
.insn_opcode
|= va_arg (args
, unsigned long);
3146 assert (*r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
3148 append_insn (&insn
, ep
, r
);
3152 mips16_macro_build (expressionS
*ep
, const char *name
, const char *fmt
,
3155 struct mips_opcode
*mo
;
3156 struct mips_cl_insn insn
;
3157 bfd_reloc_code_real_type r
[3]
3158 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
3160 mo
= (struct mips_opcode
*) hash_find (mips16_op_hash
, name
);
3162 assert (strcmp (name
, mo
->name
) == 0);
3164 while (strcmp (fmt
, mo
->args
) != 0 || mo
->pinfo
== INSN_MACRO
)
3168 assert (strcmp (name
, mo
->name
) == 0);
3171 create_insn (&insn
, mo
);
3189 MIPS16_INSERT_OPERAND (RY
, insn
, va_arg (args
, int));
3194 MIPS16_INSERT_OPERAND (RX
, insn
, va_arg (args
, int));
3198 MIPS16_INSERT_OPERAND (RZ
, insn
, va_arg (args
, int));
3202 MIPS16_INSERT_OPERAND (MOVE32Z
, insn
, va_arg (args
, int));
3212 MIPS16_INSERT_OPERAND (REGR32
, insn
, va_arg (args
, int));
3219 regno
= va_arg (args
, int);
3220 regno
= ((regno
& 7) << 2) | ((regno
& 0x18) >> 3);
3221 insn
.insn_opcode
|= regno
<< MIPS16OP_SH_REG32R
;
3242 assert (ep
!= NULL
);
3244 if (ep
->X_op
!= O_constant
)
3245 *r
= (int) BFD_RELOC_UNUSED
+ c
;
3248 mips16_immed (NULL
, 0, c
, ep
->X_add_number
, FALSE
, FALSE
,
3249 FALSE
, &insn
.insn_opcode
, &insn
.use_extend
,
3252 *r
= BFD_RELOC_UNUSED
;
3258 MIPS16_INSERT_OPERAND (IMM6
, insn
, va_arg (args
, int));
3265 assert (*r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
3267 append_insn (&insn
, ep
, r
);
3271 * Sign-extend 32-bit mode constants that have bit 31 set and all
3272 * higher bits unset.
3275 normalize_constant_expr (expressionS
*ex
)
3277 if (ex
->X_op
== O_constant
3278 && IS_ZEXT_32BIT_NUM (ex
->X_add_number
))
3279 ex
->X_add_number
= (((ex
->X_add_number
& 0xffffffff) ^ 0x80000000)
3284 * Sign-extend 32-bit mode address offsets that have bit 31 set and
3285 * all higher bits unset.
3288 normalize_address_expr (expressionS
*ex
)
3290 if (((ex
->X_op
== O_constant
&& HAVE_32BIT_ADDRESSES
)
3291 || (ex
->X_op
== O_symbol
&& HAVE_32BIT_SYMBOLS
))
3292 && IS_ZEXT_32BIT_NUM (ex
->X_add_number
))
3293 ex
->X_add_number
= (((ex
->X_add_number
& 0xffffffff) ^ 0x80000000)
3298 * Generate a "jalr" instruction with a relocation hint to the called
3299 * function. This occurs in NewABI PIC code.
3302 macro_build_jalr (expressionS
*ep
)
3311 macro_build (NULL
, "jalr", "d,s", RA
, PIC_CALL_REG
);
3313 fix_new_exp (frag_now
, f
- frag_now
->fr_literal
,
3314 4, ep
, FALSE
, BFD_RELOC_MIPS_JALR
);
3318 * Generate a "lui" instruction.
3321 macro_build_lui (expressionS
*ep
, int regnum
)
3323 expressionS high_expr
;
3324 const struct mips_opcode
*mo
;
3325 struct mips_cl_insn insn
;
3326 bfd_reloc_code_real_type r
[3]
3327 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
3328 const char *name
= "lui";
3329 const char *fmt
= "t,u";
3331 assert (! mips_opts
.mips16
);
3335 if (high_expr
.X_op
== O_constant
)
3337 /* we can compute the instruction now without a relocation entry */
3338 high_expr
.X_add_number
= ((high_expr
.X_add_number
+ 0x8000)
3340 *r
= BFD_RELOC_UNUSED
;
3344 assert (ep
->X_op
== O_symbol
);
3345 /* _gp_disp is a special case, used from s_cpload.
3346 __gnu_local_gp is used if mips_no_shared. */
3347 assert (mips_pic
== NO_PIC
3349 && strcmp (S_GET_NAME (ep
->X_add_symbol
), "_gp_disp") == 0)
3350 || (! mips_in_shared
3351 && strcmp (S_GET_NAME (ep
->X_add_symbol
),
3352 "__gnu_local_gp") == 0));
3353 *r
= BFD_RELOC_HI16_S
;
3356 mo
= hash_find (op_hash
, name
);
3357 assert (strcmp (name
, mo
->name
) == 0);
3358 assert (strcmp (fmt
, mo
->args
) == 0);
3359 create_insn (&insn
, mo
);
3361 insn
.insn_opcode
= insn
.insn_mo
->match
;
3362 INSERT_OPERAND (RT
, insn
, regnum
);
3363 if (*r
== BFD_RELOC_UNUSED
)
3365 insn
.insn_opcode
|= high_expr
.X_add_number
;
3366 append_insn (&insn
, NULL
, r
);
3369 append_insn (&insn
, &high_expr
, r
);
3372 /* Generate a sequence of instructions to do a load or store from a constant
3373 offset off of a base register (breg) into/from a target register (treg),
3374 using AT if necessary. */
3376 macro_build_ldst_constoffset (expressionS
*ep
, const char *op
,
3377 int treg
, int breg
, int dbl
)
3379 assert (ep
->X_op
== O_constant
);
3381 /* Sign-extending 32-bit constants makes their handling easier. */
3383 normalize_constant_expr (ep
);
3385 /* Right now, this routine can only handle signed 32-bit constants. */
3386 if (! IS_SEXT_32BIT_NUM(ep
->X_add_number
+ 0x8000))
3387 as_warn (_("operand overflow"));
3389 if (IS_SEXT_16BIT_NUM(ep
->X_add_number
))
3391 /* Signed 16-bit offset will fit in the op. Easy! */
3392 macro_build (ep
, op
, "t,o(b)", treg
, BFD_RELOC_LO16
, breg
);
3396 /* 32-bit offset, need multiple instructions and AT, like:
3397 lui $tempreg,const_hi (BFD_RELOC_HI16_S)
3398 addu $tempreg,$tempreg,$breg
3399 <op> $treg,const_lo($tempreg) (BFD_RELOC_LO16)
3400 to handle the complete offset. */
3401 macro_build_lui (ep
, AT
);
3402 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, AT
, breg
);
3403 macro_build (ep
, op
, "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
3406 as_bad (_("Macro used $at after \".set noat\""));
3411 * Generates code to set the $at register to true (one)
3412 * if reg is less than the immediate expression.
3415 set_at (int reg
, int unsignedp
)
3417 if (imm_expr
.X_op
== O_constant
3418 && imm_expr
.X_add_number
>= -0x8000
3419 && imm_expr
.X_add_number
< 0x8000)
3420 macro_build (&imm_expr
, unsignedp
? "sltiu" : "slti", "t,r,j",
3421 AT
, reg
, BFD_RELOC_LO16
);
3424 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
3425 macro_build (NULL
, unsignedp
? "sltu" : "slt", "d,v,t", AT
, reg
, AT
);
3429 /* Warn if an expression is not a constant. */
3432 check_absolute_expr (struct mips_cl_insn
*ip
, expressionS
*ex
)
3434 if (ex
->X_op
== O_big
)
3435 as_bad (_("unsupported large constant"));
3436 else if (ex
->X_op
!= O_constant
)
3437 as_bad (_("Instruction %s requires absolute expression"),
3440 if (HAVE_32BIT_GPRS
)
3441 normalize_constant_expr (ex
);
3444 /* Count the leading zeroes by performing a binary chop. This is a
3445 bulky bit of source, but performance is a LOT better for the
3446 majority of values than a simple loop to count the bits:
3447 for (lcnt = 0; (lcnt < 32); lcnt++)
3448 if ((v) & (1 << (31 - lcnt)))
3450 However it is not code size friendly, and the gain will drop a bit
3451 on certain cached systems.
3453 #define COUNT_TOP_ZEROES(v) \
3454 (((v) & ~0xffff) == 0 \
3455 ? ((v) & ~0xff) == 0 \
3456 ? ((v) & ~0xf) == 0 \
3457 ? ((v) & ~0x3) == 0 \
3458 ? ((v) & ~0x1) == 0 \
3463 : ((v) & ~0x7) == 0 \
3466 : ((v) & ~0x3f) == 0 \
3467 ? ((v) & ~0x1f) == 0 \
3470 : ((v) & ~0x7f) == 0 \
3473 : ((v) & ~0xfff) == 0 \
3474 ? ((v) & ~0x3ff) == 0 \
3475 ? ((v) & ~0x1ff) == 0 \
3478 : ((v) & ~0x7ff) == 0 \
3481 : ((v) & ~0x3fff) == 0 \
3482 ? ((v) & ~0x1fff) == 0 \
3485 : ((v) & ~0x7fff) == 0 \
3488 : ((v) & ~0xffffff) == 0 \
3489 ? ((v) & ~0xfffff) == 0 \
3490 ? ((v) & ~0x3ffff) == 0 \
3491 ? ((v) & ~0x1ffff) == 0 \
3494 : ((v) & ~0x7ffff) == 0 \
3497 : ((v) & ~0x3fffff) == 0 \
3498 ? ((v) & ~0x1fffff) == 0 \
3501 : ((v) & ~0x7fffff) == 0 \
3504 : ((v) & ~0xfffffff) == 0 \
3505 ? ((v) & ~0x3ffffff) == 0 \
3506 ? ((v) & ~0x1ffffff) == 0 \
3509 : ((v) & ~0x7ffffff) == 0 \
3512 : ((v) & ~0x3fffffff) == 0 \
3513 ? ((v) & ~0x1fffffff) == 0 \
3516 : ((v) & ~0x7fffffff) == 0 \
3521 * This routine generates the least number of instructions necessary to load
3522 * an absolute expression value into a register.
3525 load_register (int reg
, expressionS
*ep
, int dbl
)
3528 expressionS hi32
, lo32
;
3530 if (ep
->X_op
!= O_big
)
3532 assert (ep
->X_op
== O_constant
);
3534 /* Sign-extending 32-bit constants makes their handling easier. */
3536 normalize_constant_expr (ep
);
3538 if (IS_SEXT_16BIT_NUM (ep
->X_add_number
))
3540 /* We can handle 16 bit signed values with an addiu to
3541 $zero. No need to ever use daddiu here, since $zero and
3542 the result are always correct in 32 bit mode. */
3543 macro_build (ep
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
3546 else if (ep
->X_add_number
>= 0 && ep
->X_add_number
< 0x10000)
3548 /* We can handle 16 bit unsigned values with an ori to
3550 macro_build (ep
, "ori", "t,r,i", reg
, 0, BFD_RELOC_LO16
);
3553 else if ((IS_SEXT_32BIT_NUM (ep
->X_add_number
)))
3555 /* 32 bit values require an lui. */
3556 macro_build (ep
, "lui", "t,u", reg
, BFD_RELOC_HI16
);
3557 if ((ep
->X_add_number
& 0xffff) != 0)
3558 macro_build (ep
, "ori", "t,r,i", reg
, reg
, BFD_RELOC_LO16
);
3563 /* The value is larger than 32 bits. */
3565 if (!dbl
|| HAVE_32BIT_GPRS
)
3569 sprintf_vma (value
, ep
->X_add_number
);
3570 as_bad (_("Number (0x%s) larger than 32 bits"), value
);
3571 macro_build (ep
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
3575 if (ep
->X_op
!= O_big
)
3578 hi32
.X_add_number
= (valueT
) hi32
.X_add_number
>> 16;
3579 hi32
.X_add_number
= (valueT
) hi32
.X_add_number
>> 16;
3580 hi32
.X_add_number
&= 0xffffffff;
3582 lo32
.X_add_number
&= 0xffffffff;
3586 assert (ep
->X_add_number
> 2);
3587 if (ep
->X_add_number
== 3)
3588 generic_bignum
[3] = 0;
3589 else if (ep
->X_add_number
> 4)
3590 as_bad (_("Number larger than 64 bits"));
3591 lo32
.X_op
= O_constant
;
3592 lo32
.X_add_number
= generic_bignum
[0] + (generic_bignum
[1] << 16);
3593 hi32
.X_op
= O_constant
;
3594 hi32
.X_add_number
= generic_bignum
[2] + (generic_bignum
[3] << 16);
3597 if (hi32
.X_add_number
== 0)
3602 unsigned long hi
, lo
;
3604 if (hi32
.X_add_number
== (offsetT
) 0xffffffff)
3606 if ((lo32
.X_add_number
& 0xffff8000) == 0xffff8000)
3608 macro_build (&lo32
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
3611 if (lo32
.X_add_number
& 0x80000000)
3613 macro_build (&lo32
, "lui", "t,u", reg
, BFD_RELOC_HI16
);
3614 if (lo32
.X_add_number
& 0xffff)
3615 macro_build (&lo32
, "ori", "t,r,i", reg
, reg
, BFD_RELOC_LO16
);
3620 /* Check for 16bit shifted constant. We know that hi32 is
3621 non-zero, so start the mask on the first bit of the hi32
3626 unsigned long himask
, lomask
;
3630 himask
= 0xffff >> (32 - shift
);
3631 lomask
= (0xffff << shift
) & 0xffffffff;
3635 himask
= 0xffff << (shift
- 32);
3638 if ((hi32
.X_add_number
& ~(offsetT
) himask
) == 0
3639 && (lo32
.X_add_number
& ~(offsetT
) lomask
) == 0)
3643 tmp
.X_op
= O_constant
;
3645 tmp
.X_add_number
= ((hi32
.X_add_number
<< (32 - shift
))
3646 | (lo32
.X_add_number
>> shift
));
3648 tmp
.X_add_number
= hi32
.X_add_number
>> (shift
- 32);
3649 macro_build (&tmp
, "ori", "t,r,i", reg
, 0, BFD_RELOC_LO16
);
3650 macro_build (NULL
, (shift
>= 32) ? "dsll32" : "dsll", "d,w,<",
3651 reg
, reg
, (shift
>= 32) ? shift
- 32 : shift
);
3656 while (shift
<= (64 - 16));
3658 /* Find the bit number of the lowest one bit, and store the
3659 shifted value in hi/lo. */
3660 hi
= (unsigned long) (hi32
.X_add_number
& 0xffffffff);
3661 lo
= (unsigned long) (lo32
.X_add_number
& 0xffffffff);
3665 while ((lo
& 1) == 0)
3670 lo
|= (hi
& (((unsigned long) 1 << bit
) - 1)) << (32 - bit
);
3676 while ((hi
& 1) == 0)
3685 /* Optimize if the shifted value is a (power of 2) - 1. */
3686 if ((hi
== 0 && ((lo
+ 1) & lo
) == 0)
3687 || (lo
== 0xffffffff && ((hi
+ 1) & hi
) == 0))
3689 shift
= COUNT_TOP_ZEROES ((unsigned int) hi32
.X_add_number
);
3694 /* This instruction will set the register to be all
3696 tmp
.X_op
= O_constant
;
3697 tmp
.X_add_number
= (offsetT
) -1;
3698 macro_build (&tmp
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
3702 macro_build (NULL
, (bit
>= 32) ? "dsll32" : "dsll", "d,w,<",
3703 reg
, reg
, (bit
>= 32) ? bit
- 32 : bit
);
3705 macro_build (NULL
, (shift
>= 32) ? "dsrl32" : "dsrl", "d,w,<",
3706 reg
, reg
, (shift
>= 32) ? shift
- 32 : shift
);
3711 /* Sign extend hi32 before calling load_register, because we can
3712 generally get better code when we load a sign extended value. */
3713 if ((hi32
.X_add_number
& 0x80000000) != 0)
3714 hi32
.X_add_number
|= ~(offsetT
) 0xffffffff;
3715 load_register (reg
, &hi32
, 0);
3718 if ((lo32
.X_add_number
& 0xffff0000) == 0)
3722 macro_build (NULL
, "dsll32", "d,w,<", reg
, freg
, 0);
3730 if ((freg
== 0) && (lo32
.X_add_number
== (offsetT
) 0xffffffff))
3732 macro_build (&lo32
, "lui", "t,u", reg
, BFD_RELOC_HI16
);
3733 macro_build (NULL
, "dsrl32", "d,w,<", reg
, reg
, 0);
3739 macro_build (NULL
, "dsll", "d,w,<", reg
, freg
, 16);
3743 mid16
.X_add_number
>>= 16;
3744 macro_build (&mid16
, "ori", "t,r,i", reg
, freg
, BFD_RELOC_LO16
);
3745 macro_build (NULL
, "dsll", "d,w,<", reg
, reg
, 16);
3748 if ((lo32
.X_add_number
& 0xffff) != 0)
3749 macro_build (&lo32
, "ori", "t,r,i", reg
, freg
, BFD_RELOC_LO16
);
3753 load_delay_nop (void)
3755 if (!gpr_interlocks
)
3756 macro_build (NULL
, "nop", "");
3759 /* Load an address into a register. */
3762 load_address (int reg
, expressionS
*ep
, int *used_at
)
3764 if (ep
->X_op
!= O_constant
3765 && ep
->X_op
!= O_symbol
)
3767 as_bad (_("expression too complex"));
3768 ep
->X_op
= O_constant
;
3771 if (ep
->X_op
== O_constant
)
3773 load_register (reg
, ep
, HAVE_64BIT_ADDRESSES
);
3777 if (mips_pic
== NO_PIC
)
3779 /* If this is a reference to a GP relative symbol, we want
3780 addiu $reg,$gp,<sym> (BFD_RELOC_GPREL16)
3782 lui $reg,<sym> (BFD_RELOC_HI16_S)
3783 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
3784 If we have an addend, we always use the latter form.
3786 With 64bit address space and a usable $at we want
3787 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
3788 lui $at,<sym> (BFD_RELOC_HI16_S)
3789 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
3790 daddiu $at,<sym> (BFD_RELOC_LO16)
3794 If $at is already in use, we use a path which is suboptimal
3795 on superscalar processors.
3796 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
3797 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
3799 daddiu $reg,<sym> (BFD_RELOC_HI16_S)
3801 daddiu $reg,<sym> (BFD_RELOC_LO16)
3803 For GP relative symbols in 64bit address space we can use
3804 the same sequence as in 32bit address space. */
3805 if (HAVE_64BIT_SYMBOLS
)
3807 if ((valueT
) ep
->X_add_number
<= MAX_GPREL_OFFSET
3808 && !nopic_need_relax (ep
->X_add_symbol
, 1))
3810 relax_start (ep
->X_add_symbol
);
3811 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
,
3812 mips_gp_register
, BFD_RELOC_GPREL16
);
3816 if (*used_at
== 0 && !mips_opts
.noat
)
3818 macro_build (ep
, "lui", "t,u", reg
, BFD_RELOC_MIPS_HIGHEST
);
3819 macro_build (ep
, "lui", "t,u", AT
, BFD_RELOC_HI16_S
);
3820 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
,
3821 BFD_RELOC_MIPS_HIGHER
);
3822 macro_build (ep
, "daddiu", "t,r,j", AT
, AT
, BFD_RELOC_LO16
);
3823 macro_build (NULL
, "dsll32", "d,w,<", reg
, reg
, 0);
3824 macro_build (NULL
, "daddu", "d,v,t", reg
, reg
, AT
);
3829 macro_build (ep
, "lui", "t,u", reg
, BFD_RELOC_MIPS_HIGHEST
);
3830 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
,
3831 BFD_RELOC_MIPS_HIGHER
);
3832 macro_build (NULL
, "dsll", "d,w,<", reg
, reg
, 16);
3833 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
, BFD_RELOC_HI16_S
);
3834 macro_build (NULL
, "dsll", "d,w,<", reg
, reg
, 16);
3835 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
, BFD_RELOC_LO16
);
3838 if (mips_relax
.sequence
)
3843 if ((valueT
) ep
->X_add_number
<= MAX_GPREL_OFFSET
3844 && !nopic_need_relax (ep
->X_add_symbol
, 1))
3846 relax_start (ep
->X_add_symbol
);
3847 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
,
3848 mips_gp_register
, BFD_RELOC_GPREL16
);
3851 macro_build_lui (ep
, reg
);
3852 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j",
3853 reg
, reg
, BFD_RELOC_LO16
);
3854 if (mips_relax
.sequence
)
3858 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
3862 /* If this is a reference to an external symbol, we want
3863 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3865 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3867 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
3868 If there is a constant, it must be added in after.
3870 If we have NewABI, we want
3871 lw $reg,<sym+cst>($gp) (BFD_RELOC_MIPS_GOT_DISP)
3872 unless we're referencing a global symbol with a non-zero
3873 offset, in which case cst must be added separately. */
3876 if (ep
->X_add_number
)
3878 ex
.X_add_number
= ep
->X_add_number
;
3879 ep
->X_add_number
= 0;
3880 relax_start (ep
->X_add_symbol
);
3881 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
3882 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
3883 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
3884 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
3885 ex
.X_op
= O_constant
;
3886 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j",
3887 reg
, reg
, BFD_RELOC_LO16
);
3888 ep
->X_add_number
= ex
.X_add_number
;
3891 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
3892 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
3893 if (mips_relax
.sequence
)
3898 ex
.X_add_number
= ep
->X_add_number
;
3899 ep
->X_add_number
= 0;
3900 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
3901 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
3903 relax_start (ep
->X_add_symbol
);
3905 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
3909 if (ex
.X_add_number
!= 0)
3911 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
3912 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
3913 ex
.X_op
= O_constant
;
3914 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j",
3915 reg
, reg
, BFD_RELOC_LO16
);
3919 else if (mips_pic
== SVR4_PIC
)
3923 /* This is the large GOT case. If this is a reference to an
3924 external symbol, we want
3925 lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
3927 lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16)
3929 Otherwise, for a reference to a local symbol in old ABI, we want
3930 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3932 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
3933 If there is a constant, it must be added in after.
3935 In the NewABI, for local symbols, with or without offsets, we want:
3936 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
3937 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
3941 ex
.X_add_number
= ep
->X_add_number
;
3942 ep
->X_add_number
= 0;
3943 relax_start (ep
->X_add_symbol
);
3944 macro_build (ep
, "lui", "t,u", reg
, BFD_RELOC_MIPS_GOT_HI16
);
3945 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
3946 reg
, reg
, mips_gp_register
);
3947 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)",
3948 reg
, BFD_RELOC_MIPS_GOT_LO16
, reg
);
3949 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
3950 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
3951 else if (ex
.X_add_number
)
3953 ex
.X_op
= O_constant
;
3954 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
3958 ep
->X_add_number
= ex
.X_add_number
;
3960 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
3961 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
3962 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
3963 BFD_RELOC_MIPS_GOT_OFST
);
3968 ex
.X_add_number
= ep
->X_add_number
;
3969 ep
->X_add_number
= 0;
3970 relax_start (ep
->X_add_symbol
);
3971 macro_build (ep
, "lui", "t,u", reg
, BFD_RELOC_MIPS_GOT_HI16
);
3972 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
3973 reg
, reg
, mips_gp_register
);
3974 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)",
3975 reg
, BFD_RELOC_MIPS_GOT_LO16
, reg
);
3977 if (reg_needs_delay (mips_gp_register
))
3979 /* We need a nop before loading from $gp. This special
3980 check is required because the lui which starts the main
3981 instruction stream does not refer to $gp, and so will not
3982 insert the nop which may be required. */
3983 macro_build (NULL
, "nop", "");
3985 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
3986 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
3988 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
3992 if (ex
.X_add_number
!= 0)
3994 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
3995 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
3996 ex
.X_op
= O_constant
;
3997 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
4005 if (mips_opts
.noat
&& *used_at
== 1)
4006 as_bad (_("Macro used $at after \".set noat\""));
4009 /* Move the contents of register SOURCE into register DEST. */
4012 move_register (int dest
, int source
)
4014 macro_build (NULL
, HAVE_32BIT_GPRS
? "addu" : "daddu", "d,v,t",
4018 /* Emit an SVR4 PIC sequence to load address LOCAL into DEST, where
4019 LOCAL is the sum of a symbol and a 16-bit or 32-bit displacement.
4020 The two alternatives are:
4022 Global symbol Local sybmol
4023 ------------- ------------
4024 lw DEST,%got(SYMBOL) lw DEST,%got(SYMBOL + OFFSET)
4026 addiu DEST,DEST,OFFSET addiu DEST,DEST,%lo(SYMBOL + OFFSET)
4028 load_got_offset emits the first instruction and add_got_offset
4029 emits the second for a 16-bit offset or add_got_offset_hilo emits
4030 a sequence to add a 32-bit offset using a scratch register. */
4033 load_got_offset (int dest
, expressionS
*local
)
4038 global
.X_add_number
= 0;
4040 relax_start (local
->X_add_symbol
);
4041 macro_build (&global
, ADDRESS_LOAD_INSN
, "t,o(b)", dest
,
4042 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
4044 macro_build (local
, ADDRESS_LOAD_INSN
, "t,o(b)", dest
,
4045 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
4050 add_got_offset (int dest
, expressionS
*local
)
4054 global
.X_op
= O_constant
;
4055 global
.X_op_symbol
= NULL
;
4056 global
.X_add_symbol
= NULL
;
4057 global
.X_add_number
= local
->X_add_number
;
4059 relax_start (local
->X_add_symbol
);
4060 macro_build (&global
, ADDRESS_ADDI_INSN
, "t,r,j",
4061 dest
, dest
, BFD_RELOC_LO16
);
4063 macro_build (local
, ADDRESS_ADDI_INSN
, "t,r,j", dest
, dest
, BFD_RELOC_LO16
);
4068 add_got_offset_hilo (int dest
, expressionS
*local
, int tmp
)
4071 int hold_mips_optimize
;
4073 global
.X_op
= O_constant
;
4074 global
.X_op_symbol
= NULL
;
4075 global
.X_add_symbol
= NULL
;
4076 global
.X_add_number
= local
->X_add_number
;
4078 relax_start (local
->X_add_symbol
);
4079 load_register (tmp
, &global
, HAVE_64BIT_ADDRESSES
);
4081 /* Set mips_optimize around the lui instruction to avoid
4082 inserting an unnecessary nop after the lw. */
4083 hold_mips_optimize
= mips_optimize
;
4085 macro_build_lui (&global
, tmp
);
4086 mips_optimize
= hold_mips_optimize
;
4087 macro_build (local
, ADDRESS_ADDI_INSN
, "t,r,j", tmp
, tmp
, BFD_RELOC_LO16
);
4090 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", dest
, dest
, tmp
);
4095 * This routine implements the seemingly endless macro or synthesized
4096 * instructions and addressing modes in the mips assembly language. Many
4097 * of these macros are simple and are similar to each other. These could
4098 * probably be handled by some kind of table or grammar approach instead of
4099 * this verbose method. Others are not simple macros but are more like
4100 * optimizing code generation.
4101 * One interesting optimization is when several store macros appear
4102 * consecutively that would load AT with the upper half of the same address.
4103 * The ensuing load upper instructions are ommited. This implies some kind
4104 * of global optimization. We currently only optimize within a single macro.
4105 * For many of the load and store macros if the address is specified as a
4106 * constant expression in the first 64k of memory (ie ld $2,0x4000c) we
4107 * first load register 'at' with zero and use it as the base register. The
4108 * mips assembler simply uses register $zero. Just one tiny optimization
4112 macro (struct mips_cl_insn
*ip
)
4114 register int treg
, sreg
, dreg
, breg
;
4130 bfd_reloc_code_real_type r
;
4131 int hold_mips_optimize
;
4133 assert (! mips_opts
.mips16
);
4135 treg
= (ip
->insn_opcode
>> 16) & 0x1f;
4136 dreg
= (ip
->insn_opcode
>> 11) & 0x1f;
4137 sreg
= breg
= (ip
->insn_opcode
>> 21) & 0x1f;
4138 mask
= ip
->insn_mo
->mask
;
4140 expr1
.X_op
= O_constant
;
4141 expr1
.X_op_symbol
= NULL
;
4142 expr1
.X_add_symbol
= NULL
;
4143 expr1
.X_add_number
= 1;
4157 expr1
.X_add_number
= 8;
4158 macro_build (&expr1
, "bgez", "s,p", sreg
);
4160 macro_build (NULL
, "nop", "", 0);
4162 move_register (dreg
, sreg
);
4163 macro_build (NULL
, dbl
? "dsub" : "sub", "d,v,t", dreg
, 0, sreg
);
4186 if (imm_expr
.X_op
== O_constant
4187 && imm_expr
.X_add_number
>= -0x8000
4188 && imm_expr
.X_add_number
< 0x8000)
4190 macro_build (&imm_expr
, s
, "t,r,j", treg
, sreg
, BFD_RELOC_LO16
);
4194 load_register (AT
, &imm_expr
, dbl
);
4195 macro_build (NULL
, s2
, "d,v,t", treg
, sreg
, AT
);
4214 if (imm_expr
.X_op
== O_constant
4215 && imm_expr
.X_add_number
>= 0
4216 && imm_expr
.X_add_number
< 0x10000)
4218 if (mask
!= M_NOR_I
)
4219 macro_build (&imm_expr
, s
, "t,r,i", treg
, sreg
, BFD_RELOC_LO16
);
4222 macro_build (&imm_expr
, "ori", "t,r,i",
4223 treg
, sreg
, BFD_RELOC_LO16
);
4224 macro_build (NULL
, "nor", "d,v,t", treg
, treg
, 0);
4230 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
4231 macro_build (NULL
, s2
, "d,v,t", treg
, sreg
, AT
);
4248 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
4250 macro_build (&offset_expr
, s
, "s,t,p", sreg
, 0);
4254 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
4255 macro_build (&offset_expr
, s
, "s,t,p", sreg
, AT
);
4263 macro_build (&offset_expr
, likely
? "bgezl" : "bgez", "s,p", sreg
);
4268 macro_build (&offset_expr
, likely
? "blezl" : "blez", "s,p", treg
);
4272 macro_build (NULL
, "slt", "d,v,t", AT
, sreg
, treg
);
4273 macro_build (&offset_expr
, likely
? "beql" : "beq", "s,t,p", AT
, 0);
4279 /* check for > max integer */
4280 maxnum
= 0x7fffffff;
4281 if (HAVE_64BIT_GPRS
&& sizeof (maxnum
) > 4)
4288 if (imm_expr
.X_op
== O_constant
4289 && imm_expr
.X_add_number
>= maxnum
4290 && (HAVE_32BIT_GPRS
|| sizeof (maxnum
) > 4))
4293 /* result is always false */
4295 macro_build (NULL
, "nop", "", 0);
4297 macro_build (&offset_expr
, "bnel", "s,t,p", 0, 0);
4300 if (imm_expr
.X_op
!= O_constant
)
4301 as_bad (_("Unsupported large constant"));
4302 ++imm_expr
.X_add_number
;
4306 if (mask
== M_BGEL_I
)
4308 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
4310 macro_build (&offset_expr
, likely
? "bgezl" : "bgez", "s,p", sreg
);
4313 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
4315 macro_build (&offset_expr
, likely
? "bgtzl" : "bgtz", "s,p", sreg
);
4318 maxnum
= 0x7fffffff;
4319 if (HAVE_64BIT_GPRS
&& sizeof (maxnum
) > 4)
4326 maxnum
= - maxnum
- 1;
4327 if (imm_expr
.X_op
== O_constant
4328 && imm_expr
.X_add_number
<= maxnum
4329 && (HAVE_32BIT_GPRS
|| sizeof (maxnum
) > 4))
4332 /* result is always true */
4333 as_warn (_("Branch %s is always true"), ip
->insn_mo
->name
);
4334 macro_build (&offset_expr
, "b", "p");
4339 macro_build (&offset_expr
, likely
? "beql" : "beq", "s,t,p", AT
, 0);
4349 macro_build (&offset_expr
, likely
? "beql" : "beq",
4354 macro_build (NULL
, "sltu", "d,v,t", AT
, sreg
, treg
);
4355 macro_build (&offset_expr
, likely
? "beql" : "beq", "s,t,p", AT
, 0);
4363 && imm_expr
.X_op
== O_constant
4364 && imm_expr
.X_add_number
== (offsetT
) 0xffffffff))
4366 if (imm_expr
.X_op
!= O_constant
)
4367 as_bad (_("Unsupported large constant"));
4368 ++imm_expr
.X_add_number
;
4372 if (mask
== M_BGEUL_I
)
4374 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
4376 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
4378 macro_build (&offset_expr
, likely
? "bnel" : "bne",
4384 macro_build (&offset_expr
, likely
? "beql" : "beq", "s,t,p", AT
, 0);
4392 macro_build (&offset_expr
, likely
? "bgtzl" : "bgtz", "s,p", sreg
);
4397 macro_build (&offset_expr
, likely
? "bltzl" : "bltz", "s,p", treg
);
4401 macro_build (NULL
, "slt", "d,v,t", AT
, treg
, sreg
);
4402 macro_build (&offset_expr
, likely
? "bnel" : "bne", "s,t,p", AT
, 0);
4410 macro_build (&offset_expr
, likely
? "bnel" : "bne",
4417 macro_build (NULL
, "sltu", "d,v,t", AT
, treg
, sreg
);
4418 macro_build (&offset_expr
, likely
? "bnel" : "bne", "s,t,p", AT
, 0);
4426 macro_build (&offset_expr
, likely
? "blezl" : "blez", "s,p", sreg
);
4431 macro_build (&offset_expr
, likely
? "bgezl" : "bgez", "s,p", treg
);
4435 macro_build (NULL
, "slt", "d,v,t", AT
, treg
, sreg
);
4436 macro_build (&offset_expr
, likely
? "beql" : "beq", "s,t,p", AT
, 0);
4442 maxnum
= 0x7fffffff;
4443 if (HAVE_64BIT_GPRS
&& sizeof (maxnum
) > 4)
4450 if (imm_expr
.X_op
== O_constant
4451 && imm_expr
.X_add_number
>= maxnum
4452 && (HAVE_32BIT_GPRS
|| sizeof (maxnum
) > 4))
4454 if (imm_expr
.X_op
!= O_constant
)
4455 as_bad (_("Unsupported large constant"));
4456 ++imm_expr
.X_add_number
;
4460 if (mask
== M_BLTL_I
)
4462 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
4464 macro_build (&offset_expr
, likely
? "bltzl" : "bltz", "s,p", sreg
);
4467 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
4469 macro_build (&offset_expr
, likely
? "blezl" : "blez", "s,p", sreg
);
4474 macro_build (&offset_expr
, likely
? "bnel" : "bne", "s,t,p", AT
, 0);
4482 macro_build (&offset_expr
, likely
? "beql" : "beq",
4489 macro_build (NULL
, "sltu", "d,v,t", AT
, treg
, sreg
);
4490 macro_build (&offset_expr
, likely
? "beql" : "beq", "s,t,p", AT
, 0);
4498 && imm_expr
.X_op
== O_constant
4499 && imm_expr
.X_add_number
== (offsetT
) 0xffffffff))
4501 if (imm_expr
.X_op
!= O_constant
)
4502 as_bad (_("Unsupported large constant"));
4503 ++imm_expr
.X_add_number
;
4507 if (mask
== M_BLTUL_I
)
4509 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
4511 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
4513 macro_build (&offset_expr
, likely
? "beql" : "beq",
4519 macro_build (&offset_expr
, likely
? "bnel" : "bne", "s,t,p", AT
, 0);
4527 macro_build (&offset_expr
, likely
? "bltzl" : "bltz", "s,p", sreg
);
4532 macro_build (&offset_expr
, likely
? "bgtzl" : "bgtz", "s,p", treg
);
4536 macro_build (NULL
, "slt", "d,v,t", AT
, sreg
, treg
);
4537 macro_build (&offset_expr
, likely
? "bnel" : "bne", "s,t,p", AT
, 0);
4547 macro_build (&offset_expr
, likely
? "bnel" : "bne",
4552 macro_build (NULL
, "sltu", "d,v,t", AT
, sreg
, treg
);
4553 macro_build (&offset_expr
, likely
? "bnel" : "bne", "s,t,p", AT
, 0);
4561 if (imm_expr
.X_op
!= O_constant
|| imm2_expr
.X_op
!= O_constant
)
4563 as_bad (_("Unsupported large constant"));
4568 pos
= (unsigned long) imm_expr
.X_add_number
;
4569 size
= (unsigned long) imm2_expr
.X_add_number
;
4574 as_bad (_("Improper position (%lu)"), pos
);
4577 if (size
== 0 || size
> 64
4578 || (pos
+ size
- 1) > 63)
4580 as_bad (_("Improper extract size (%lu, position %lu)"),
4585 if (size
<= 32 && pos
< 32)
4590 else if (size
<= 32)
4600 macro_build ((expressionS
*) NULL
, s
, fmt
, treg
, sreg
, pos
, size
- 1);
4609 if (imm_expr
.X_op
!= O_constant
|| imm2_expr
.X_op
!= O_constant
)
4611 as_bad (_("Unsupported large constant"));
4616 pos
= (unsigned long) imm_expr
.X_add_number
;
4617 size
= (unsigned long) imm2_expr
.X_add_number
;
4622 as_bad (_("Improper position (%lu)"), pos
);
4625 if (size
== 0 || size
> 64
4626 || (pos
+ size
- 1) > 63)
4628 as_bad (_("Improper insert size (%lu, position %lu)"),
4633 if (pos
< 32 && (pos
+ size
- 1) < 32)
4648 macro_build ((expressionS
*) NULL
, s
, fmt
, treg
, sreg
, pos
,
4665 as_warn (_("Divide by zero."));
4667 macro_build (NULL
, "teq", "s,t,q", 0, 0, 7);
4669 macro_build (NULL
, "break", "c", 7);
4676 macro_build (NULL
, "teq", "s,t,q", treg
, 0, 7);
4677 macro_build (NULL
, dbl
? "ddiv" : "div", "z,s,t", sreg
, treg
);
4681 expr1
.X_add_number
= 8;
4682 macro_build (&expr1
, "bne", "s,t,p", treg
, 0);
4683 macro_build (NULL
, dbl
? "ddiv" : "div", "z,s,t", sreg
, treg
);
4684 macro_build (NULL
, "break", "c", 7);
4686 expr1
.X_add_number
= -1;
4688 load_register (AT
, &expr1
, dbl
);
4689 expr1
.X_add_number
= mips_trap
? (dbl
? 12 : 8) : (dbl
? 20 : 16);
4690 macro_build (&expr1
, "bne", "s,t,p", treg
, AT
);
4693 expr1
.X_add_number
= 1;
4694 load_register (AT
, &expr1
, dbl
);
4695 macro_build (NULL
, "dsll32", "d,w,<", AT
, AT
, 31);
4699 expr1
.X_add_number
= 0x80000000;
4700 macro_build (&expr1
, "lui", "t,u", AT
, BFD_RELOC_HI16
);
4704 macro_build (NULL
, "teq", "s,t,q", sreg
, AT
, 6);
4705 /* We want to close the noreorder block as soon as possible, so
4706 that later insns are available for delay slot filling. */
4711 expr1
.X_add_number
= 8;
4712 macro_build (&expr1
, "bne", "s,t,p", sreg
, AT
);
4713 macro_build (NULL
, "nop", "", 0);
4715 /* We want to close the noreorder block as soon as possible, so
4716 that later insns are available for delay slot filling. */
4719 macro_build (NULL
, "break", "c", 6);
4721 macro_build (NULL
, s
, "d", dreg
);
4760 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
4762 as_warn (_("Divide by zero."));
4764 macro_build (NULL
, "teq", "s,t,q", 0, 0, 7);
4766 macro_build (NULL
, "break", "c", 7);
4769 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
4771 if (strcmp (s2
, "mflo") == 0)
4772 move_register (dreg
, sreg
);
4774 move_register (dreg
, 0);
4777 if (imm_expr
.X_op
== O_constant
4778 && imm_expr
.X_add_number
== -1
4779 && s
[strlen (s
) - 1] != 'u')
4781 if (strcmp (s2
, "mflo") == 0)
4783 macro_build (NULL
, dbl
? "dneg" : "neg", "d,w", dreg
, sreg
);
4786 move_register (dreg
, 0);
4791 load_register (AT
, &imm_expr
, dbl
);
4792 macro_build (NULL
, s
, "z,s,t", sreg
, AT
);
4793 macro_build (NULL
, s2
, "d", dreg
);
4815 macro_build (NULL
, "teq", "s,t,q", treg
, 0, 7);
4816 macro_build (NULL
, s
, "z,s,t", sreg
, treg
);
4817 /* We want to close the noreorder block as soon as possible, so
4818 that later insns are available for delay slot filling. */
4823 expr1
.X_add_number
= 8;
4824 macro_build (&expr1
, "bne", "s,t,p", treg
, 0);
4825 macro_build (NULL
, s
, "z,s,t", sreg
, treg
);
4827 /* We want to close the noreorder block as soon as possible, so
4828 that later insns are available for delay slot filling. */
4830 macro_build (NULL
, "break", "c", 7);
4832 macro_build (NULL
, s2
, "d", dreg
);
4844 /* Load the address of a symbol into a register. If breg is not
4845 zero, we then add a base register to it. */
4847 if (dbl
&& HAVE_32BIT_GPRS
)
4848 as_warn (_("dla used to load 32-bit register"));
4850 if (! dbl
&& HAVE_64BIT_OBJECTS
)
4851 as_warn (_("la used to load 64-bit address"));
4853 if (offset_expr
.X_op
== O_constant
4854 && offset_expr
.X_add_number
>= -0x8000
4855 && offset_expr
.X_add_number
< 0x8000)
4857 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
,
4858 "t,r,j", treg
, sreg
, BFD_RELOC_LO16
);
4862 if (!mips_opts
.noat
&& (treg
== breg
))
4872 if (offset_expr
.X_op
!= O_symbol
4873 && offset_expr
.X_op
!= O_constant
)
4875 as_bad (_("expression too complex"));
4876 offset_expr
.X_op
= O_constant
;
4879 if (offset_expr
.X_op
== O_constant
)
4880 load_register (tempreg
, &offset_expr
, HAVE_64BIT_ADDRESSES
);
4881 else if (mips_pic
== NO_PIC
)
4883 /* If this is a reference to a GP relative symbol, we want
4884 addiu $tempreg,$gp,<sym> (BFD_RELOC_GPREL16)
4886 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
4887 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
4888 If we have a constant, we need two instructions anyhow,
4889 so we may as well always use the latter form.
4891 With 64bit address space and a usable $at we want
4892 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
4893 lui $at,<sym> (BFD_RELOC_HI16_S)
4894 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
4895 daddiu $at,<sym> (BFD_RELOC_LO16)
4897 daddu $tempreg,$tempreg,$at
4899 If $at is already in use, we use a path which is suboptimal
4900 on superscalar processors.
4901 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
4902 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
4904 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
4906 daddiu $tempreg,<sym> (BFD_RELOC_LO16)
4908 For GP relative symbols in 64bit address space we can use
4909 the same sequence as in 32bit address space. */
4910 if (HAVE_64BIT_SYMBOLS
)
4912 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
4913 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
4915 relax_start (offset_expr
.X_add_symbol
);
4916 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
4917 tempreg
, mips_gp_register
, BFD_RELOC_GPREL16
);
4921 if (used_at
== 0 && !mips_opts
.noat
)
4923 macro_build (&offset_expr
, "lui", "t,u",
4924 tempreg
, BFD_RELOC_MIPS_HIGHEST
);
4925 macro_build (&offset_expr
, "lui", "t,u",
4926 AT
, BFD_RELOC_HI16_S
);
4927 macro_build (&offset_expr
, "daddiu", "t,r,j",
4928 tempreg
, tempreg
, BFD_RELOC_MIPS_HIGHER
);
4929 macro_build (&offset_expr
, "daddiu", "t,r,j",
4930 AT
, AT
, BFD_RELOC_LO16
);
4931 macro_build (NULL
, "dsll32", "d,w,<", tempreg
, tempreg
, 0);
4932 macro_build (NULL
, "daddu", "d,v,t", tempreg
, tempreg
, AT
);
4937 macro_build (&offset_expr
, "lui", "t,u",
4938 tempreg
, BFD_RELOC_MIPS_HIGHEST
);
4939 macro_build (&offset_expr
, "daddiu", "t,r,j",
4940 tempreg
, tempreg
, BFD_RELOC_MIPS_HIGHER
);
4941 macro_build (NULL
, "dsll", "d,w,<", tempreg
, tempreg
, 16);
4942 macro_build (&offset_expr
, "daddiu", "t,r,j",
4943 tempreg
, tempreg
, BFD_RELOC_HI16_S
);
4944 macro_build (NULL
, "dsll", "d,w,<", tempreg
, tempreg
, 16);
4945 macro_build (&offset_expr
, "daddiu", "t,r,j",
4946 tempreg
, tempreg
, BFD_RELOC_LO16
);
4949 if (mips_relax
.sequence
)
4954 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
4955 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
4957 relax_start (offset_expr
.X_add_symbol
);
4958 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
4959 tempreg
, mips_gp_register
, BFD_RELOC_GPREL16
);
4962 if (!IS_SEXT_32BIT_NUM (offset_expr
.X_add_number
))
4963 as_bad (_("offset too large"));
4964 macro_build_lui (&offset_expr
, tempreg
);
4965 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
4966 tempreg
, tempreg
, BFD_RELOC_LO16
);
4967 if (mips_relax
.sequence
)
4971 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
&& ! HAVE_NEWABI
)
4973 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT16
;
4975 /* If this is a reference to an external symbol, and there
4976 is no constant, we want
4977 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4978 or for lca or if tempreg is PIC_CALL_REG
4979 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
4980 For a local symbol, we want
4981 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4983 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
4985 If we have a small constant, and this is a reference to
4986 an external symbol, we want
4987 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4989 addiu $tempreg,$tempreg,<constant>
4990 For a local symbol, we want the same instruction
4991 sequence, but we output a BFD_RELOC_LO16 reloc on the
4994 If we have a large constant, and this is a reference to
4995 an external symbol, we want
4996 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4997 lui $at,<hiconstant>
4998 addiu $at,$at,<loconstant>
4999 addu $tempreg,$tempreg,$at
5000 For a local symbol, we want the same instruction
5001 sequence, but we output a BFD_RELOC_LO16 reloc on the
5005 if (offset_expr
.X_add_number
== 0)
5007 if (breg
== 0 && (call
|| tempreg
== PIC_CALL_REG
))
5008 lw_reloc_type
= (int) BFD_RELOC_MIPS_CALL16
;
5010 relax_start (offset_expr
.X_add_symbol
);
5011 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
5012 lw_reloc_type
, mips_gp_register
);
5015 /* We're going to put in an addu instruction using
5016 tempreg, so we may as well insert the nop right
5021 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
5022 tempreg
, BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
5024 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
5025 tempreg
, tempreg
, BFD_RELOC_LO16
);
5027 /* FIXME: If breg == 0, and the next instruction uses
5028 $tempreg, then if this variant case is used an extra
5029 nop will be generated. */
5031 else if (offset_expr
.X_add_number
>= -0x8000
5032 && offset_expr
.X_add_number
< 0x8000)
5034 load_got_offset (tempreg
, &offset_expr
);
5036 add_got_offset (tempreg
, &offset_expr
);
5040 expr1
.X_add_number
= offset_expr
.X_add_number
;
5041 offset_expr
.X_add_number
=
5042 ((offset_expr
.X_add_number
+ 0x8000) & 0xffff) - 0x8000;
5043 load_got_offset (tempreg
, &offset_expr
);
5044 offset_expr
.X_add_number
= expr1
.X_add_number
;
5045 /* If we are going to add in a base register, and the
5046 target register and the base register are the same,
5047 then we are using AT as a temporary register. Since
5048 we want to load the constant into AT, we add our
5049 current AT (from the global offset table) and the
5050 register into the register now, and pretend we were
5051 not using a base register. */
5055 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5060 add_got_offset_hilo (tempreg
, &offset_expr
, AT
);
5064 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
&& HAVE_NEWABI
)
5066 int add_breg_early
= 0;
5068 /* If this is a reference to an external, and there is no
5069 constant, or local symbol (*), with or without a
5071 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
5072 or for lca or if tempreg is PIC_CALL_REG
5073 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
5075 If we have a small constant, and this is a reference to
5076 an external symbol, we want
5077 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
5078 addiu $tempreg,$tempreg,<constant>
5080 If we have a large constant, and this is a reference to
5081 an external symbol, we want
5082 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
5083 lui $at,<hiconstant>
5084 addiu $at,$at,<loconstant>
5085 addu $tempreg,$tempreg,$at
5087 (*) Other assemblers seem to prefer GOT_PAGE/GOT_OFST for
5088 local symbols, even though it introduces an additional
5091 if (offset_expr
.X_add_number
)
5093 expr1
.X_add_number
= offset_expr
.X_add_number
;
5094 offset_expr
.X_add_number
= 0;
5096 relax_start (offset_expr
.X_add_symbol
);
5097 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
5098 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
5100 if (expr1
.X_add_number
>= -0x8000
5101 && expr1
.X_add_number
< 0x8000)
5103 macro_build (&expr1
, ADDRESS_ADDI_INSN
, "t,r,j",
5104 tempreg
, tempreg
, BFD_RELOC_LO16
);
5106 else if (IS_SEXT_32BIT_NUM (expr1
.X_add_number
+ 0x8000))
5110 /* If we are going to add in a base register, and the
5111 target register and the base register are the same,
5112 then we are using AT as a temporary register. Since
5113 we want to load the constant into AT, we add our
5114 current AT (from the global offset table) and the
5115 register into the register now, and pretend we were
5116 not using a base register. */
5121 assert (tempreg
== AT
);
5122 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5128 load_register (AT
, &expr1
, HAVE_64BIT_ADDRESSES
);
5129 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5135 as_bad (_("PIC code offset overflow (max 32 signed bits)"));
5138 offset_expr
.X_add_number
= expr1
.X_add_number
;
5140 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
5141 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
5144 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5145 treg
, tempreg
, breg
);
5151 else if (breg
== 0 && (call
|| tempreg
== PIC_CALL_REG
))
5153 relax_start (offset_expr
.X_add_symbol
);
5154 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
5155 BFD_RELOC_MIPS_CALL16
, mips_gp_register
);
5157 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
5158 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
5163 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
5164 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
5167 else if (mips_pic
== SVR4_PIC
&& ! HAVE_NEWABI
)
5170 int lui_reloc_type
= (int) BFD_RELOC_MIPS_GOT_HI16
;
5171 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT_LO16
;
5172 int local_reloc_type
= (int) BFD_RELOC_MIPS_GOT16
;
5174 /* This is the large GOT case. If this is a reference to an
5175 external symbol, and there is no constant, we want
5176 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5177 addu $tempreg,$tempreg,$gp
5178 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5179 or for lca or if tempreg is PIC_CALL_REG
5180 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
5181 addu $tempreg,$tempreg,$gp
5182 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
5183 For a local symbol, we want
5184 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5186 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
5188 If we have a small constant, and this is a reference to
5189 an external symbol, we want
5190 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5191 addu $tempreg,$tempreg,$gp
5192 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5194 addiu $tempreg,$tempreg,<constant>
5195 For a local symbol, we want
5196 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5198 addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16)
5200 If we have a large constant, and this is a reference to
5201 an external symbol, we want
5202 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5203 addu $tempreg,$tempreg,$gp
5204 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5205 lui $at,<hiconstant>
5206 addiu $at,$at,<loconstant>
5207 addu $tempreg,$tempreg,$at
5208 For a local symbol, we want
5209 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5210 lui $at,<hiconstant>
5211 addiu $at,$at,<loconstant> (BFD_RELOC_LO16)
5212 addu $tempreg,$tempreg,$at
5215 expr1
.X_add_number
= offset_expr
.X_add_number
;
5216 offset_expr
.X_add_number
= 0;
5217 relax_start (offset_expr
.X_add_symbol
);
5218 gpdelay
= reg_needs_delay (mips_gp_register
);
5219 if (expr1
.X_add_number
== 0 && breg
== 0
5220 && (call
|| tempreg
== PIC_CALL_REG
))
5222 lui_reloc_type
= (int) BFD_RELOC_MIPS_CALL_HI16
;
5223 lw_reloc_type
= (int) BFD_RELOC_MIPS_CALL_LO16
;
5225 macro_build (&offset_expr
, "lui", "t,u", tempreg
, lui_reloc_type
);
5226 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5227 tempreg
, tempreg
, mips_gp_register
);
5228 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
5229 tempreg
, lw_reloc_type
, tempreg
);
5230 if (expr1
.X_add_number
== 0)
5234 /* We're going to put in an addu instruction using
5235 tempreg, so we may as well insert the nop right
5240 else if (expr1
.X_add_number
>= -0x8000
5241 && expr1
.X_add_number
< 0x8000)
5244 macro_build (&expr1
, ADDRESS_ADDI_INSN
, "t,r,j",
5245 tempreg
, tempreg
, BFD_RELOC_LO16
);
5251 /* If we are going to add in a base register, and the
5252 target register and the base register are the same,
5253 then we are using AT as a temporary register. Since
5254 we want to load the constant into AT, we add our
5255 current AT (from the global offset table) and the
5256 register into the register now, and pretend we were
5257 not using a base register. */
5262 assert (tempreg
== AT
);
5264 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5269 load_register (AT
, &expr1
, HAVE_64BIT_ADDRESSES
);
5270 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", dreg
, dreg
, AT
);
5274 offset_expr
.X_add_number
=
5275 ((expr1
.X_add_number
+ 0x8000) & 0xffff) - 0x8000;
5280 /* This is needed because this instruction uses $gp, but
5281 the first instruction on the main stream does not. */
5282 macro_build (NULL
, "nop", "");
5285 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
5286 local_reloc_type
, mips_gp_register
);
5287 if (expr1
.X_add_number
>= -0x8000
5288 && expr1
.X_add_number
< 0x8000)
5291 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
5292 tempreg
, tempreg
, BFD_RELOC_LO16
);
5293 /* FIXME: If add_number is 0, and there was no base
5294 register, the external symbol case ended with a load,
5295 so if the symbol turns out to not be external, and
5296 the next instruction uses tempreg, an unnecessary nop
5297 will be inserted. */
5303 /* We must add in the base register now, as in the
5304 external symbol case. */
5305 assert (tempreg
== AT
);
5307 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5310 /* We set breg to 0 because we have arranged to add
5311 it in in both cases. */
5315 macro_build_lui (&expr1
, AT
);
5316 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
5317 AT
, AT
, BFD_RELOC_LO16
);
5318 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5319 tempreg
, tempreg
, AT
);
5324 else if (mips_pic
== SVR4_PIC
&& HAVE_NEWABI
)
5326 int lui_reloc_type
= (int) BFD_RELOC_MIPS_GOT_HI16
;
5327 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT_LO16
;
5328 int add_breg_early
= 0;
5330 /* This is the large GOT case. If this is a reference to an
5331 external symbol, and there is no constant, we want
5332 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5333 add $tempreg,$tempreg,$gp
5334 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5335 or for lca or if tempreg is PIC_CALL_REG
5336 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
5337 add $tempreg,$tempreg,$gp
5338 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
5340 If we have a small constant, and this is a reference to
5341 an external symbol, we want
5342 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5343 add $tempreg,$tempreg,$gp
5344 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5345 addi $tempreg,$tempreg,<constant>
5347 If we have a large constant, and this is a reference to
5348 an external symbol, we want
5349 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5350 addu $tempreg,$tempreg,$gp
5351 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5352 lui $at,<hiconstant>
5353 addi $at,$at,<loconstant>
5354 add $tempreg,$tempreg,$at
5356 If we have NewABI, and we know it's a local symbol, we want
5357 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
5358 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
5359 otherwise we have to resort to GOT_HI16/GOT_LO16. */
5361 relax_start (offset_expr
.X_add_symbol
);
5363 expr1
.X_add_number
= offset_expr
.X_add_number
;
5364 offset_expr
.X_add_number
= 0;
5366 if (expr1
.X_add_number
== 0 && breg
== 0
5367 && (call
|| tempreg
== PIC_CALL_REG
))
5369 lui_reloc_type
= (int) BFD_RELOC_MIPS_CALL_HI16
;
5370 lw_reloc_type
= (int) BFD_RELOC_MIPS_CALL_LO16
;
5372 macro_build (&offset_expr
, "lui", "t,u", tempreg
, lui_reloc_type
);
5373 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5374 tempreg
, tempreg
, mips_gp_register
);
5375 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
5376 tempreg
, lw_reloc_type
, tempreg
);
5378 if (expr1
.X_add_number
== 0)
5380 else if (expr1
.X_add_number
>= -0x8000
5381 && expr1
.X_add_number
< 0x8000)
5383 macro_build (&expr1
, ADDRESS_ADDI_INSN
, "t,r,j",
5384 tempreg
, tempreg
, BFD_RELOC_LO16
);
5386 else if (IS_SEXT_32BIT_NUM (expr1
.X_add_number
+ 0x8000))
5390 /* If we are going to add in a base register, and the
5391 target register and the base register are the same,
5392 then we are using AT as a temporary register. Since
5393 we want to load the constant into AT, we add our
5394 current AT (from the global offset table) and the
5395 register into the register now, and pretend we were
5396 not using a base register. */
5401 assert (tempreg
== AT
);
5402 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5408 load_register (AT
, &expr1
, HAVE_64BIT_ADDRESSES
);
5409 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", dreg
, dreg
, AT
);
5414 as_bad (_("PIC code offset overflow (max 32 signed bits)"));
5417 offset_expr
.X_add_number
= expr1
.X_add_number
;
5418 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
5419 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
5420 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j", tempreg
,
5421 tempreg
, BFD_RELOC_MIPS_GOT_OFST
);
5424 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5425 treg
, tempreg
, breg
);
5435 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", treg
, tempreg
, breg
);
5439 /* The j instruction may not be used in PIC code, since it
5440 requires an absolute address. We convert it to a b
5442 if (mips_pic
== NO_PIC
)
5443 macro_build (&offset_expr
, "j", "a");
5445 macro_build (&offset_expr
, "b", "p");
5448 /* The jal instructions must be handled as macros because when
5449 generating PIC code they expand to multi-instruction
5450 sequences. Normally they are simple instructions. */
5455 if (mips_pic
== NO_PIC
)
5456 macro_build (NULL
, "jalr", "d,s", dreg
, sreg
);
5457 else if (mips_pic
== SVR4_PIC
)
5459 if (sreg
!= PIC_CALL_REG
)
5460 as_warn (_("MIPS PIC call to register other than $25"));
5462 macro_build (NULL
, "jalr", "d,s", dreg
, sreg
);
5465 if (mips_cprestore_offset
< 0)
5466 as_warn (_("No .cprestore pseudo-op used in PIC code"));
5469 if (! mips_frame_reg_valid
)
5471 as_warn (_("No .frame pseudo-op used in PIC code"));
5472 /* Quiet this warning. */
5473 mips_frame_reg_valid
= 1;
5475 if (! mips_cprestore_valid
)
5477 as_warn (_("No .cprestore pseudo-op used in PIC code"));
5478 /* Quiet this warning. */
5479 mips_cprestore_valid
= 1;
5481 expr1
.X_add_number
= mips_cprestore_offset
;
5482 macro_build_ldst_constoffset (&expr1
, ADDRESS_LOAD_INSN
,
5485 HAVE_64BIT_ADDRESSES
);
5495 if (mips_pic
== NO_PIC
)
5496 macro_build (&offset_expr
, "jal", "a");
5497 else if (mips_pic
== SVR4_PIC
)
5499 /* If this is a reference to an external symbol, and we are
5500 using a small GOT, we want
5501 lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
5505 lw $gp,cprestore($sp)
5506 The cprestore value is set using the .cprestore
5507 pseudo-op. If we are using a big GOT, we want
5508 lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16)
5510 lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16)
5514 lw $gp,cprestore($sp)
5515 If the symbol is not external, we want
5516 lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5518 addiu $25,$25,<sym> (BFD_RELOC_LO16)
5521 lw $gp,cprestore($sp)
5523 For NewABI, we use the same CALL16 or CALL_HI16/CALL_LO16
5524 sequences above, minus nops, unless the symbol is local,
5525 which enables us to use GOT_PAGE/GOT_OFST (big got) or
5531 relax_start (offset_expr
.X_add_symbol
);
5532 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
5533 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL16
,
5536 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
5537 PIC_CALL_REG
, BFD_RELOC_MIPS_GOT_DISP
,
5543 relax_start (offset_expr
.X_add_symbol
);
5544 macro_build (&offset_expr
, "lui", "t,u", PIC_CALL_REG
,
5545 BFD_RELOC_MIPS_CALL_HI16
);
5546 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", PIC_CALL_REG
,
5547 PIC_CALL_REG
, mips_gp_register
);
5548 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
5549 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL_LO16
,
5552 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
5553 PIC_CALL_REG
, BFD_RELOC_MIPS_GOT_PAGE
,
5555 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
5556 PIC_CALL_REG
, PIC_CALL_REG
,
5557 BFD_RELOC_MIPS_GOT_OFST
);
5561 macro_build_jalr (&offset_expr
);
5565 relax_start (offset_expr
.X_add_symbol
);
5568 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
5569 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL16
,
5578 gpdelay
= reg_needs_delay (mips_gp_register
);
5579 macro_build (&offset_expr
, "lui", "t,u", PIC_CALL_REG
,
5580 BFD_RELOC_MIPS_CALL_HI16
);
5581 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", PIC_CALL_REG
,
5582 PIC_CALL_REG
, mips_gp_register
);
5583 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
5584 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL_LO16
,
5589 macro_build (NULL
, "nop", "");
5591 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
5592 PIC_CALL_REG
, BFD_RELOC_MIPS_GOT16
,
5595 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
5596 PIC_CALL_REG
, PIC_CALL_REG
, BFD_RELOC_LO16
);
5598 macro_build_jalr (&offset_expr
);
5600 if (mips_cprestore_offset
< 0)
5601 as_warn (_("No .cprestore pseudo-op used in PIC code"));
5604 if (! mips_frame_reg_valid
)
5606 as_warn (_("No .frame pseudo-op used in PIC code"));
5607 /* Quiet this warning. */
5608 mips_frame_reg_valid
= 1;
5610 if (! mips_cprestore_valid
)
5612 as_warn (_("No .cprestore pseudo-op used in PIC code"));
5613 /* Quiet this warning. */
5614 mips_cprestore_valid
= 1;
5616 if (mips_opts
.noreorder
)
5617 macro_build (NULL
, "nop", "");
5618 expr1
.X_add_number
= mips_cprestore_offset
;
5619 macro_build_ldst_constoffset (&expr1
, ADDRESS_LOAD_INSN
,
5622 HAVE_64BIT_ADDRESSES
);
5648 /* Itbl support may require additional care here. */
5653 /* Itbl support may require additional care here. */
5658 /* Itbl support may require additional care here. */
5663 /* Itbl support may require additional care here. */
5675 if (mips_opts
.arch
== CPU_R4650
)
5677 as_bad (_("opcode not supported on this processor"));
5681 /* Itbl support may require additional care here. */
5686 /* Itbl support may require additional care here. */
5691 /* Itbl support may require additional care here. */
5711 if (breg
== treg
|| coproc
|| lr
)
5732 /* Itbl support may require additional care here. */
5737 /* Itbl support may require additional care here. */
5742 /* Itbl support may require additional care here. */
5747 /* Itbl support may require additional care here. */
5763 if (mips_opts
.arch
== CPU_R4650
)
5765 as_bad (_("opcode not supported on this processor"));
5770 /* Itbl support may require additional care here. */
5774 /* Itbl support may require additional care here. */
5779 /* Itbl support may require additional care here. */
5791 /* Itbl support may require additional care here. */
5792 if (mask
== M_LWC1_AB
5793 || mask
== M_SWC1_AB
5794 || mask
== M_LDC1_AB
5795 || mask
== M_SDC1_AB
5804 if (offset_expr
.X_op
!= O_constant
5805 && offset_expr
.X_op
!= O_symbol
)
5807 as_bad (_("expression too complex"));
5808 offset_expr
.X_op
= O_constant
;
5811 if (HAVE_32BIT_ADDRESSES
5812 && !IS_SEXT_32BIT_NUM (offset_expr
.X_add_number
))
5816 sprintf_vma (value
, offset_expr
.X_add_number
);
5817 as_bad (_("Number (0x%s) larger than 32 bits"), value
);
5820 /* A constant expression in PIC code can be handled just as it
5821 is in non PIC code. */
5822 if (offset_expr
.X_op
== O_constant
)
5824 expr1
.X_add_number
= ((offset_expr
.X_add_number
+ 0x8000)
5825 & ~(bfd_vma
) 0xffff);
5826 normalize_address_expr (&expr1
);
5827 load_register (tempreg
, &expr1
, HAVE_64BIT_ADDRESSES
);
5829 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5830 tempreg
, tempreg
, breg
);
5831 macro_build (&offset_expr
, s
, fmt
, treg
, BFD_RELOC_LO16
, tempreg
);
5833 else if (mips_pic
== NO_PIC
)
5835 /* If this is a reference to a GP relative symbol, and there
5836 is no base register, we want
5837 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
5838 Otherwise, if there is no base register, we want
5839 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
5840 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5841 If we have a constant, we need two instructions anyhow,
5842 so we always use the latter form.
5844 If we have a base register, and this is a reference to a
5845 GP relative symbol, we want
5846 addu $tempreg,$breg,$gp
5847 <op> $treg,<sym>($tempreg) (BFD_RELOC_GPREL16)
5849 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
5850 addu $tempreg,$tempreg,$breg
5851 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5852 With a constant we always use the latter case.
5854 With 64bit address space and no base register and $at usable,
5856 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5857 lui $at,<sym> (BFD_RELOC_HI16_S)
5858 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
5861 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5862 If we have a base register, we want
5863 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5864 lui $at,<sym> (BFD_RELOC_HI16_S)
5865 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
5869 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5871 Without $at we can't generate the optimal path for superscalar
5872 processors here since this would require two temporary registers.
5873 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5874 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
5876 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
5878 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5879 If we have a base register, we want
5880 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5881 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
5883 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
5885 daddu $tempreg,$tempreg,$breg
5886 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5888 For GP relative symbols in 64bit address space we can use
5889 the same sequence as in 32bit address space. */
5890 if (HAVE_64BIT_SYMBOLS
)
5892 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
5893 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
5895 relax_start (offset_expr
.X_add_symbol
);
5898 macro_build (&offset_expr
, s
, fmt
, treg
,
5899 BFD_RELOC_GPREL16
, mips_gp_register
);
5903 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5904 tempreg
, breg
, mips_gp_register
);
5905 macro_build (&offset_expr
, s
, fmt
, treg
,
5906 BFD_RELOC_GPREL16
, tempreg
);
5911 if (used_at
== 0 && !mips_opts
.noat
)
5913 macro_build (&offset_expr
, "lui", "t,u", tempreg
,
5914 BFD_RELOC_MIPS_HIGHEST
);
5915 macro_build (&offset_expr
, "lui", "t,u", AT
,
5917 macro_build (&offset_expr
, "daddiu", "t,r,j", tempreg
,
5918 tempreg
, BFD_RELOC_MIPS_HIGHER
);
5920 macro_build (NULL
, "daddu", "d,v,t", AT
, AT
, breg
);
5921 macro_build (NULL
, "dsll32", "d,w,<", tempreg
, tempreg
, 0);
5922 macro_build (NULL
, "daddu", "d,v,t", tempreg
, tempreg
, AT
);
5923 macro_build (&offset_expr
, s
, fmt
, treg
, BFD_RELOC_LO16
,
5929 macro_build (&offset_expr
, "lui", "t,u", tempreg
,
5930 BFD_RELOC_MIPS_HIGHEST
);
5931 macro_build (&offset_expr
, "daddiu", "t,r,j", tempreg
,
5932 tempreg
, BFD_RELOC_MIPS_HIGHER
);
5933 macro_build (NULL
, "dsll", "d,w,<", tempreg
, tempreg
, 16);
5934 macro_build (&offset_expr
, "daddiu", "t,r,j", tempreg
,
5935 tempreg
, BFD_RELOC_HI16_S
);
5936 macro_build (NULL
, "dsll", "d,w,<", tempreg
, tempreg
, 16);
5938 macro_build (NULL
, "daddu", "d,v,t",
5939 tempreg
, tempreg
, breg
);
5940 macro_build (&offset_expr
, s
, fmt
, treg
,
5941 BFD_RELOC_LO16
, tempreg
);
5944 if (mips_relax
.sequence
)
5951 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
5952 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
5954 relax_start (offset_expr
.X_add_symbol
);
5955 macro_build (&offset_expr
, s
, fmt
, treg
, BFD_RELOC_GPREL16
,
5959 macro_build_lui (&offset_expr
, tempreg
);
5960 macro_build (&offset_expr
, s
, fmt
, treg
,
5961 BFD_RELOC_LO16
, tempreg
);
5962 if (mips_relax
.sequence
)
5967 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
5968 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
5970 relax_start (offset_expr
.X_add_symbol
);
5971 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5972 tempreg
, breg
, mips_gp_register
);
5973 macro_build (&offset_expr
, s
, fmt
, treg
,
5974 BFD_RELOC_GPREL16
, tempreg
);
5977 macro_build_lui (&offset_expr
, tempreg
);
5978 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5979 tempreg
, tempreg
, breg
);
5980 macro_build (&offset_expr
, s
, fmt
, treg
,
5981 BFD_RELOC_LO16
, tempreg
);
5982 if (mips_relax
.sequence
)
5986 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
5988 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT16
;
5990 /* If this is a reference to an external symbol, we want
5991 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5993 <op> $treg,0($tempreg)
5995 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5997 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
5998 <op> $treg,0($tempreg)
6001 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
6002 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST)
6004 If there is a base register, we add it to $tempreg before
6005 the <op>. If there is a constant, we stick it in the
6006 <op> instruction. We don't handle constants larger than
6007 16 bits, because we have no way to load the upper 16 bits
6008 (actually, we could handle them for the subset of cases
6009 in which we are not using $at). */
6010 assert (offset_expr
.X_op
== O_symbol
);
6013 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
6014 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
6016 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6017 tempreg
, tempreg
, breg
);
6018 macro_build (&offset_expr
, s
, fmt
, treg
,
6019 BFD_RELOC_MIPS_GOT_OFST
, tempreg
);
6022 expr1
.X_add_number
= offset_expr
.X_add_number
;
6023 offset_expr
.X_add_number
= 0;
6024 if (expr1
.X_add_number
< -0x8000
6025 || expr1
.X_add_number
>= 0x8000)
6026 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6027 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
6028 lw_reloc_type
, mips_gp_register
);
6030 relax_start (offset_expr
.X_add_symbol
);
6032 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j", tempreg
,
6033 tempreg
, BFD_RELOC_LO16
);
6036 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6037 tempreg
, tempreg
, breg
);
6038 macro_build (&expr1
, s
, fmt
, treg
, BFD_RELOC_LO16
, tempreg
);
6040 else if (mips_pic
== SVR4_PIC
&& ! HAVE_NEWABI
)
6044 /* If this is a reference to an external symbol, we want
6045 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
6046 addu $tempreg,$tempreg,$gp
6047 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
6048 <op> $treg,0($tempreg)
6050 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6052 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
6053 <op> $treg,0($tempreg)
6054 If there is a base register, we add it to $tempreg before
6055 the <op>. If there is a constant, we stick it in the
6056 <op> instruction. We don't handle constants larger than
6057 16 bits, because we have no way to load the upper 16 bits
6058 (actually, we could handle them for the subset of cases
6059 in which we are not using $at). */
6060 assert (offset_expr
.X_op
== O_symbol
);
6061 expr1
.X_add_number
= offset_expr
.X_add_number
;
6062 offset_expr
.X_add_number
= 0;
6063 if (expr1
.X_add_number
< -0x8000
6064 || expr1
.X_add_number
>= 0x8000)
6065 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6066 gpdelay
= reg_needs_delay (mips_gp_register
);
6067 relax_start (offset_expr
.X_add_symbol
);
6068 macro_build (&offset_expr
, "lui", "t,u", tempreg
,
6069 BFD_RELOC_MIPS_GOT_HI16
);
6070 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", tempreg
, tempreg
,
6072 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
6073 BFD_RELOC_MIPS_GOT_LO16
, tempreg
);
6076 macro_build (NULL
, "nop", "");
6077 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
6078 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
6080 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j", tempreg
,
6081 tempreg
, BFD_RELOC_LO16
);
6085 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6086 tempreg
, tempreg
, breg
);
6087 macro_build (&expr1
, s
, fmt
, treg
, BFD_RELOC_LO16
, tempreg
);
6089 else if (mips_pic
== SVR4_PIC
&& HAVE_NEWABI
)
6091 /* If this is a reference to an external symbol, we want
6092 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
6093 add $tempreg,$tempreg,$gp
6094 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
6095 <op> $treg,<ofst>($tempreg)
6096 Otherwise, for local symbols, we want:
6097 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
6098 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST) */
6099 assert (offset_expr
.X_op
== O_symbol
);
6100 expr1
.X_add_number
= offset_expr
.X_add_number
;
6101 offset_expr
.X_add_number
= 0;
6102 if (expr1
.X_add_number
< -0x8000
6103 || expr1
.X_add_number
>= 0x8000)
6104 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6105 relax_start (offset_expr
.X_add_symbol
);
6106 macro_build (&offset_expr
, "lui", "t,u", tempreg
,
6107 BFD_RELOC_MIPS_GOT_HI16
);
6108 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", tempreg
, tempreg
,
6110 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
6111 BFD_RELOC_MIPS_GOT_LO16
, tempreg
);
6113 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6114 tempreg
, tempreg
, breg
);
6115 macro_build (&expr1
, s
, fmt
, treg
, BFD_RELOC_LO16
, tempreg
);
6118 offset_expr
.X_add_number
= expr1
.X_add_number
;
6119 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
6120 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
6122 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6123 tempreg
, tempreg
, breg
);
6124 macro_build (&offset_expr
, s
, fmt
, treg
,
6125 BFD_RELOC_MIPS_GOT_OFST
, tempreg
);
6135 load_register (treg
, &imm_expr
, 0);
6139 load_register (treg
, &imm_expr
, 1);
6143 if (imm_expr
.X_op
== O_constant
)
6146 load_register (AT
, &imm_expr
, 0);
6147 macro_build (NULL
, "mtc1", "t,G", AT
, treg
);
6152 assert (offset_expr
.X_op
== O_symbol
6153 && strcmp (segment_name (S_GET_SEGMENT
6154 (offset_expr
.X_add_symbol
)),
6156 && offset_expr
.X_add_number
== 0);
6157 macro_build (&offset_expr
, "lwc1", "T,o(b)", treg
,
6158 BFD_RELOC_MIPS_LITERAL
, mips_gp_register
);
6163 /* Check if we have a constant in IMM_EXPR. If the GPRs are 64 bits
6164 wide, IMM_EXPR is the entire value. Otherwise IMM_EXPR is the high
6165 order 32 bits of the value and the low order 32 bits are either
6166 zero or in OFFSET_EXPR. */
6167 if (imm_expr
.X_op
== O_constant
|| imm_expr
.X_op
== O_big
)
6169 if (HAVE_64BIT_GPRS
)
6170 load_register (treg
, &imm_expr
, 1);
6175 if (target_big_endian
)
6187 load_register (hreg
, &imm_expr
, 0);
6190 if (offset_expr
.X_op
== O_absent
)
6191 move_register (lreg
, 0);
6194 assert (offset_expr
.X_op
== O_constant
);
6195 load_register (lreg
, &offset_expr
, 0);
6202 /* We know that sym is in the .rdata section. First we get the
6203 upper 16 bits of the address. */
6204 if (mips_pic
== NO_PIC
)
6206 macro_build_lui (&offset_expr
, AT
);
6209 else if (mips_pic
== SVR4_PIC
)
6211 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", AT
,
6212 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
6218 /* Now we load the register(s). */
6219 if (HAVE_64BIT_GPRS
)
6222 macro_build (&offset_expr
, "ld", "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
6227 macro_build (&offset_expr
, "lw", "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
6230 /* FIXME: How in the world do we deal with the possible
6232 offset_expr
.X_add_number
+= 4;
6233 macro_build (&offset_expr
, "lw", "t,o(b)",
6234 treg
+ 1, BFD_RELOC_LO16
, AT
);
6240 /* Check if we have a constant in IMM_EXPR. If the FPRs are 64 bits
6241 wide, IMM_EXPR is the entire value and the GPRs are known to be 64
6242 bits wide as well. Otherwise IMM_EXPR is the high order 32 bits of
6243 the value and the low order 32 bits are either zero or in
6245 if (imm_expr
.X_op
== O_constant
|| imm_expr
.X_op
== O_big
)
6248 load_register (AT
, &imm_expr
, HAVE_64BIT_FPRS
);
6249 if (HAVE_64BIT_FPRS
)
6251 assert (HAVE_64BIT_GPRS
);
6252 macro_build (NULL
, "dmtc1", "t,S", AT
, treg
);
6256 macro_build (NULL
, "mtc1", "t,G", AT
, treg
+ 1);
6257 if (offset_expr
.X_op
== O_absent
)
6258 macro_build (NULL
, "mtc1", "t,G", 0, treg
);
6261 assert (offset_expr
.X_op
== O_constant
);
6262 load_register (AT
, &offset_expr
, 0);
6263 macro_build (NULL
, "mtc1", "t,G", AT
, treg
);
6269 assert (offset_expr
.X_op
== O_symbol
6270 && offset_expr
.X_add_number
== 0);
6271 s
= segment_name (S_GET_SEGMENT (offset_expr
.X_add_symbol
));
6272 if (strcmp (s
, ".lit8") == 0)
6274 if (mips_opts
.isa
!= ISA_MIPS1
)
6276 macro_build (&offset_expr
, "ldc1", "T,o(b)", treg
,
6277 BFD_RELOC_MIPS_LITERAL
, mips_gp_register
);
6280 breg
= mips_gp_register
;
6281 r
= BFD_RELOC_MIPS_LITERAL
;
6286 assert (strcmp (s
, RDATA_SECTION_NAME
) == 0);
6288 if (mips_pic
== SVR4_PIC
)
6289 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", AT
,
6290 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
6293 /* FIXME: This won't work for a 64 bit address. */
6294 macro_build_lui (&offset_expr
, AT
);
6297 if (mips_opts
.isa
!= ISA_MIPS1
)
6299 macro_build (&offset_expr
, "ldc1", "T,o(b)",
6300 treg
, BFD_RELOC_LO16
, AT
);
6309 if (mips_opts
.arch
== CPU_R4650
)
6311 as_bad (_("opcode not supported on this processor"));
6314 /* Even on a big endian machine $fn comes before $fn+1. We have
6315 to adjust when loading from memory. */
6318 assert (mips_opts
.isa
== ISA_MIPS1
);
6319 macro_build (&offset_expr
, "lwc1", "T,o(b)",
6320 target_big_endian
? treg
+ 1 : treg
, r
, breg
);
6321 /* FIXME: A possible overflow which I don't know how to deal
6323 offset_expr
.X_add_number
+= 4;
6324 macro_build (&offset_expr
, "lwc1", "T,o(b)",
6325 target_big_endian
? treg
: treg
+ 1, r
, breg
);
6330 * The MIPS assembler seems to check for X_add_number not
6331 * being double aligned and generating:
6334 * addiu at,at,%lo(foo+1)
6337 * But, the resulting address is the same after relocation so why
6338 * generate the extra instruction?
6340 if (mips_opts
.arch
== CPU_R4650
)
6342 as_bad (_("opcode not supported on this processor"));
6345 /* Itbl support may require additional care here. */
6347 if (mips_opts
.isa
!= ISA_MIPS1
)
6358 if (mips_opts
.arch
== CPU_R4650
)
6360 as_bad (_("opcode not supported on this processor"));
6364 if (mips_opts
.isa
!= ISA_MIPS1
)
6372 /* Itbl support may require additional care here. */
6377 if (HAVE_64BIT_GPRS
)
6388 if (HAVE_64BIT_GPRS
)
6398 if (offset_expr
.X_op
!= O_symbol
6399 && offset_expr
.X_op
!= O_constant
)
6401 as_bad (_("expression too complex"));
6402 offset_expr
.X_op
= O_constant
;
6405 if (HAVE_32BIT_ADDRESSES
6406 && !IS_SEXT_32BIT_NUM (offset_expr
.X_add_number
))
6410 sprintf_vma (value
, offset_expr
.X_add_number
);
6411 as_bad (_("Number (0x%s) larger than 32 bits"), value
);
6414 /* Even on a big endian machine $fn comes before $fn+1. We have
6415 to adjust when loading from memory. We set coproc if we must
6416 load $fn+1 first. */
6417 /* Itbl support may require additional care here. */
6418 if (! target_big_endian
)
6421 if (mips_pic
== NO_PIC
6422 || offset_expr
.X_op
== O_constant
)
6424 /* If this is a reference to a GP relative symbol, we want
6425 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
6426 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_GPREL16)
6427 If we have a base register, we use this
6429 <op> $treg,<sym>($at) (BFD_RELOC_GPREL16)
6430 <op> $treg+1,<sym>+4($at) (BFD_RELOC_GPREL16)
6431 If this is not a GP relative symbol, we want
6432 lui $at,<sym> (BFD_RELOC_HI16_S)
6433 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
6434 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
6435 If there is a base register, we add it to $at after the
6436 lui instruction. If there is a constant, we always use
6438 if (offset_expr
.X_op
== O_symbol
6439 && (valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
6440 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
6442 relax_start (offset_expr
.X_add_symbol
);
6445 tempreg
= mips_gp_register
;
6449 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6450 AT
, breg
, mips_gp_register
);
6455 /* Itbl support may require additional care here. */
6456 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
+ 1 : treg
,
6457 BFD_RELOC_GPREL16
, tempreg
);
6458 offset_expr
.X_add_number
+= 4;
6460 /* Set mips_optimize to 2 to avoid inserting an
6462 hold_mips_optimize
= mips_optimize
;
6464 /* Itbl support may require additional care here. */
6465 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
: treg
+ 1,
6466 BFD_RELOC_GPREL16
, tempreg
);
6467 mips_optimize
= hold_mips_optimize
;
6471 /* We just generated two relocs. When tc_gen_reloc
6472 handles this case, it will skip the first reloc and
6473 handle the second. The second reloc already has an
6474 extra addend of 4, which we added above. We must
6475 subtract it out, and then subtract another 4 to make
6476 the first reloc come out right. The second reloc
6477 will come out right because we are going to add 4 to
6478 offset_expr when we build its instruction below.
6480 If we have a symbol, then we don't want to include
6481 the offset, because it will wind up being included
6482 when we generate the reloc. */
6484 if (offset_expr
.X_op
== O_constant
)
6485 offset_expr
.X_add_number
-= 8;
6488 offset_expr
.X_add_number
= -4;
6489 offset_expr
.X_op
= O_constant
;
6493 macro_build_lui (&offset_expr
, AT
);
6495 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
6496 /* Itbl support may require additional care here. */
6497 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
+ 1 : treg
,
6498 BFD_RELOC_LO16
, AT
);
6499 /* FIXME: How do we handle overflow here? */
6500 offset_expr
.X_add_number
+= 4;
6501 /* Itbl support may require additional care here. */
6502 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
: treg
+ 1,
6503 BFD_RELOC_LO16
, AT
);
6504 if (mips_relax
.sequence
)
6507 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
6509 /* If this is a reference to an external symbol, we want
6510 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6515 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6517 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
6518 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
6519 If there is a base register we add it to $at before the
6520 lwc1 instructions. If there is a constant we include it
6521 in the lwc1 instructions. */
6523 expr1
.X_add_number
= offset_expr
.X_add_number
;
6524 if (expr1
.X_add_number
< -0x8000
6525 || expr1
.X_add_number
>= 0x8000 - 4)
6526 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6527 load_got_offset (AT
, &offset_expr
);
6530 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
6532 /* Set mips_optimize to 2 to avoid inserting an undesired
6534 hold_mips_optimize
= mips_optimize
;
6537 /* Itbl support may require additional care here. */
6538 relax_start (offset_expr
.X_add_symbol
);
6539 macro_build (&expr1
, s
, fmt
, coproc
? treg
+ 1 : treg
,
6540 BFD_RELOC_LO16
, AT
);
6541 expr1
.X_add_number
+= 4;
6542 macro_build (&expr1
, s
, fmt
, coproc
? treg
: treg
+ 1,
6543 BFD_RELOC_LO16
, AT
);
6545 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
+ 1 : treg
,
6546 BFD_RELOC_LO16
, AT
);
6547 offset_expr
.X_add_number
+= 4;
6548 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
: treg
+ 1,
6549 BFD_RELOC_LO16
, AT
);
6552 mips_optimize
= hold_mips_optimize
;
6554 else if (mips_pic
== SVR4_PIC
)
6558 /* If this is a reference to an external symbol, we want
6559 lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16)
6561 lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16)
6566 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6568 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
6569 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
6570 If there is a base register we add it to $at before the
6571 lwc1 instructions. If there is a constant we include it
6572 in the lwc1 instructions. */
6574 expr1
.X_add_number
= offset_expr
.X_add_number
;
6575 offset_expr
.X_add_number
= 0;
6576 if (expr1
.X_add_number
< -0x8000
6577 || expr1
.X_add_number
>= 0x8000 - 4)
6578 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6579 gpdelay
= reg_needs_delay (mips_gp_register
);
6580 relax_start (offset_expr
.X_add_symbol
);
6581 macro_build (&offset_expr
, "lui", "t,u",
6582 AT
, BFD_RELOC_MIPS_GOT_HI16
);
6583 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6584 AT
, AT
, mips_gp_register
);
6585 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
6586 AT
, BFD_RELOC_MIPS_GOT_LO16
, AT
);
6589 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
6590 /* Itbl support may require additional care here. */
6591 macro_build (&expr1
, s
, fmt
, coproc
? treg
+ 1 : treg
,
6592 BFD_RELOC_LO16
, AT
);
6593 expr1
.X_add_number
+= 4;
6595 /* Set mips_optimize to 2 to avoid inserting an undesired
6597 hold_mips_optimize
= mips_optimize
;
6599 /* Itbl support may require additional care here. */
6600 macro_build (&expr1
, s
, fmt
, coproc
? treg
: treg
+ 1,
6601 BFD_RELOC_LO16
, AT
);
6602 mips_optimize
= hold_mips_optimize
;
6603 expr1
.X_add_number
-= 4;
6606 offset_expr
.X_add_number
= expr1
.X_add_number
;
6608 macro_build (NULL
, "nop", "");
6609 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", AT
,
6610 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
6613 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
6614 /* Itbl support may require additional care here. */
6615 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
+ 1 : treg
,
6616 BFD_RELOC_LO16
, AT
);
6617 offset_expr
.X_add_number
+= 4;
6619 /* Set mips_optimize to 2 to avoid inserting an undesired
6621 hold_mips_optimize
= mips_optimize
;
6623 /* Itbl support may require additional care here. */
6624 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
: treg
+ 1,
6625 BFD_RELOC_LO16
, AT
);
6626 mips_optimize
= hold_mips_optimize
;
6640 assert (HAVE_32BIT_ADDRESSES
);
6641 macro_build (&offset_expr
, s
, "t,o(b)", treg
, BFD_RELOC_LO16
, breg
);
6642 offset_expr
.X_add_number
+= 4;
6643 macro_build (&offset_expr
, s
, "t,o(b)", treg
+ 1, BFD_RELOC_LO16
, breg
);
6646 /* New code added to support COPZ instructions.
6647 This code builds table entries out of the macros in mip_opcodes.
6648 R4000 uses interlocks to handle coproc delays.
6649 Other chips (like the R3000) require nops to be inserted for delays.
6651 FIXME: Currently, we require that the user handle delays.
6652 In order to fill delay slots for non-interlocked chips,
6653 we must have a way to specify delays based on the coprocessor.
6654 Eg. 4 cycles if load coproc reg from memory, 1 if in cache, etc.
6655 What are the side-effects of the cop instruction?
6656 What cache support might we have and what are its effects?
6657 Both coprocessor & memory require delays. how long???
6658 What registers are read/set/modified?
6660 If an itbl is provided to interpret cop instructions,
6661 this knowledge can be encoded in the itbl spec. */
6675 /* For now we just do C (same as Cz). The parameter will be
6676 stored in insn_opcode by mips_ip. */
6677 macro_build (NULL
, s
, "C", ip
->insn_opcode
);
6681 move_register (dreg
, sreg
);
6684 #ifdef LOSING_COMPILER
6686 /* Try and see if this is a new itbl instruction.
6687 This code builds table entries out of the macros in mip_opcodes.
6688 FIXME: For now we just assemble the expression and pass it's
6689 value along as a 32-bit immediate.
6690 We may want to have the assembler assemble this value,
6691 so that we gain the assembler's knowledge of delay slots,
6693 Would it be more efficient to use mask (id) here? */
6694 if (itbl_have_entries
6695 && (immed_expr
= itbl_assemble (ip
->insn_mo
->name
, "")))
6697 s
= ip
->insn_mo
->name
;
6699 coproc
= ITBL_DECODE_PNUM (immed_expr
);;
6700 macro_build (&immed_expr
, s
, "C");
6706 if (mips_opts
.noat
&& used_at
)
6707 as_bad (_("Macro used $at after \".set noat\""));
6711 macro2 (struct mips_cl_insn
*ip
)
6713 register int treg
, sreg
, dreg
, breg
;
6728 bfd_reloc_code_real_type r
;
6730 treg
= (ip
->insn_opcode
>> 16) & 0x1f;
6731 dreg
= (ip
->insn_opcode
>> 11) & 0x1f;
6732 sreg
= breg
= (ip
->insn_opcode
>> 21) & 0x1f;
6733 mask
= ip
->insn_mo
->mask
;
6735 expr1
.X_op
= O_constant
;
6736 expr1
.X_op_symbol
= NULL
;
6737 expr1
.X_add_symbol
= NULL
;
6738 expr1
.X_add_number
= 1;
6742 #endif /* LOSING_COMPILER */
6747 macro_build (NULL
, dbl
? "dmultu" : "multu", "s,t", sreg
, treg
);
6748 macro_build (NULL
, "mflo", "d", dreg
);
6754 /* The MIPS assembler some times generates shifts and adds. I'm
6755 not trying to be that fancy. GCC should do this for us
6758 load_register (AT
, &imm_expr
, dbl
);
6759 macro_build (NULL
, dbl
? "dmult" : "mult", "s,t", sreg
, AT
);
6760 macro_build (NULL
, "mflo", "d", dreg
);
6776 load_register (AT
, &imm_expr
, dbl
);
6777 macro_build (NULL
, dbl
? "dmult" : "mult", "s,t", sreg
, imm
? AT
: treg
);
6778 macro_build (NULL
, "mflo", "d", dreg
);
6779 macro_build (NULL
, dbl
? "dsra32" : "sra", "d,w,<", dreg
, dreg
, RA
);
6780 macro_build (NULL
, "mfhi", "d", AT
);
6782 macro_build (NULL
, "tne", "s,t,q", dreg
, AT
, 6);
6785 expr1
.X_add_number
= 8;
6786 macro_build (&expr1
, "beq", "s,t,p", dreg
, AT
);
6787 macro_build (NULL
, "nop", "", 0);
6788 macro_build (NULL
, "break", "c", 6);
6791 macro_build (NULL
, "mflo", "d", dreg
);
6807 load_register (AT
, &imm_expr
, dbl
);
6808 macro_build (NULL
, dbl
? "dmultu" : "multu", "s,t",
6809 sreg
, imm
? AT
: treg
);
6810 macro_build (NULL
, "mfhi", "d", AT
);
6811 macro_build (NULL
, "mflo", "d", dreg
);
6813 macro_build (NULL
, "tne", "s,t,q", AT
, 0, 6);
6816 expr1
.X_add_number
= 8;
6817 macro_build (&expr1
, "beq", "s,t,p", AT
, 0);
6818 macro_build (NULL
, "nop", "", 0);
6819 macro_build (NULL
, "break", "c", 6);
6825 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
6836 macro_build (NULL
, "dnegu", "d,w", tempreg
, treg
);
6837 macro_build (NULL
, "drorv", "d,t,s", dreg
, sreg
, tempreg
);
6841 macro_build (NULL
, "dsubu", "d,v,t", AT
, 0, treg
);
6842 macro_build (NULL
, "dsrlv", "d,t,s", AT
, sreg
, AT
);
6843 macro_build (NULL
, "dsllv", "d,t,s", dreg
, sreg
, treg
);
6844 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
6848 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
6859 macro_build (NULL
, "negu", "d,w", tempreg
, treg
);
6860 macro_build (NULL
, "rorv", "d,t,s", dreg
, sreg
, tempreg
);
6864 macro_build (NULL
, "subu", "d,v,t", AT
, 0, treg
);
6865 macro_build (NULL
, "srlv", "d,t,s", AT
, sreg
, AT
);
6866 macro_build (NULL
, "sllv", "d,t,s", dreg
, sreg
, treg
);
6867 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
6875 if (imm_expr
.X_op
!= O_constant
)
6876 as_bad (_("Improper rotate count"));
6877 rot
= imm_expr
.X_add_number
& 0x3f;
6878 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
6880 rot
= (64 - rot
) & 0x3f;
6882 macro_build (NULL
, "dror32", "d,w,<", dreg
, sreg
, rot
- 32);
6884 macro_build (NULL
, "dror", "d,w,<", dreg
, sreg
, rot
);
6889 macro_build (NULL
, "dsrl", "d,w,<", dreg
, sreg
, 0);
6892 l
= (rot
< 0x20) ? "dsll" : "dsll32";
6893 r
= ((0x40 - rot
) < 0x20) ? "dsrl" : "dsrl32";
6896 macro_build (NULL
, l
, "d,w,<", AT
, sreg
, rot
);
6897 macro_build (NULL
, r
, "d,w,<", dreg
, sreg
, (0x20 - rot
) & 0x1f);
6898 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
6906 if (imm_expr
.X_op
!= O_constant
)
6907 as_bad (_("Improper rotate count"));
6908 rot
= imm_expr
.X_add_number
& 0x1f;
6909 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
6911 macro_build (NULL
, "ror", "d,w,<", dreg
, sreg
, (32 - rot
) & 0x1f);
6916 macro_build (NULL
, "srl", "d,w,<", dreg
, sreg
, 0);
6920 macro_build (NULL
, "sll", "d,w,<", AT
, sreg
, rot
);
6921 macro_build (NULL
, "srl", "d,w,<", dreg
, sreg
, (0x20 - rot
) & 0x1f);
6922 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
6927 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
6929 macro_build (NULL
, "drorv", "d,t,s", dreg
, sreg
, treg
);
6933 macro_build (NULL
, "dsubu", "d,v,t", AT
, 0, treg
);
6934 macro_build (NULL
, "dsllv", "d,t,s", AT
, sreg
, AT
);
6935 macro_build (NULL
, "dsrlv", "d,t,s", dreg
, sreg
, treg
);
6936 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
6940 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
6942 macro_build (NULL
, "rorv", "d,t,s", dreg
, sreg
, treg
);
6946 macro_build (NULL
, "subu", "d,v,t", AT
, 0, treg
);
6947 macro_build (NULL
, "sllv", "d,t,s", AT
, sreg
, AT
);
6948 macro_build (NULL
, "srlv", "d,t,s", dreg
, sreg
, treg
);
6949 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
6957 if (imm_expr
.X_op
!= O_constant
)
6958 as_bad (_("Improper rotate count"));
6959 rot
= imm_expr
.X_add_number
& 0x3f;
6960 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
6963 macro_build (NULL
, "dror32", "d,w,<", dreg
, sreg
, rot
- 32);
6965 macro_build (NULL
, "dror", "d,w,<", dreg
, sreg
, rot
);
6970 macro_build (NULL
, "dsrl", "d,w,<", dreg
, sreg
, 0);
6973 r
= (rot
< 0x20) ? "dsrl" : "dsrl32";
6974 l
= ((0x40 - rot
) < 0x20) ? "dsll" : "dsll32";
6977 macro_build (NULL
, r
, "d,w,<", AT
, sreg
, rot
);
6978 macro_build (NULL
, l
, "d,w,<", dreg
, sreg
, (0x20 - rot
) & 0x1f);
6979 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
6987 if (imm_expr
.X_op
!= O_constant
)
6988 as_bad (_("Improper rotate count"));
6989 rot
= imm_expr
.X_add_number
& 0x1f;
6990 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
6992 macro_build (NULL
, "ror", "d,w,<", dreg
, sreg
, rot
);
6997 macro_build (NULL
, "srl", "d,w,<", dreg
, sreg
, 0);
7001 macro_build (NULL
, "srl", "d,w,<", AT
, sreg
, rot
);
7002 macro_build (NULL
, "sll", "d,w,<", dreg
, sreg
, (0x20 - rot
) & 0x1f);
7003 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
7008 if (mips_opts
.arch
== CPU_R4650
)
7010 as_bad (_("opcode not supported on this processor"));
7013 assert (mips_opts
.isa
== ISA_MIPS1
);
7014 /* Even on a big endian machine $fn comes before $fn+1. We have
7015 to adjust when storing to memory. */
7016 macro_build (&offset_expr
, "swc1", "T,o(b)",
7017 target_big_endian
? treg
+ 1 : treg
, BFD_RELOC_LO16
, breg
);
7018 offset_expr
.X_add_number
+= 4;
7019 macro_build (&offset_expr
, "swc1", "T,o(b)",
7020 target_big_endian
? treg
: treg
+ 1, BFD_RELOC_LO16
, breg
);
7025 macro_build (&expr1
, "sltiu", "t,r,j", dreg
, treg
, BFD_RELOC_LO16
);
7027 macro_build (&expr1
, "sltiu", "t,r,j", dreg
, sreg
, BFD_RELOC_LO16
);
7030 macro_build (NULL
, "xor", "d,v,t", dreg
, sreg
, treg
);
7031 macro_build (&expr1
, "sltiu", "t,r,j", dreg
, dreg
, BFD_RELOC_LO16
);
7036 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
7038 macro_build (&expr1
, "sltiu", "t,r,j", dreg
, sreg
, BFD_RELOC_LO16
);
7043 as_warn (_("Instruction %s: result is always false"),
7045 move_register (dreg
, 0);
7048 if (imm_expr
.X_op
== O_constant
7049 && imm_expr
.X_add_number
>= 0
7050 && imm_expr
.X_add_number
< 0x10000)
7052 macro_build (&imm_expr
, "xori", "t,r,i", dreg
, sreg
, BFD_RELOC_LO16
);
7054 else if (imm_expr
.X_op
== O_constant
7055 && imm_expr
.X_add_number
> -0x8000
7056 && imm_expr
.X_add_number
< 0)
7058 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
7059 macro_build (&imm_expr
, HAVE_32BIT_GPRS
? "addiu" : "daddiu",
7060 "t,r,j", dreg
, sreg
, BFD_RELOC_LO16
);
7064 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7065 macro_build (NULL
, "xor", "d,v,t", dreg
, sreg
, AT
);
7068 macro_build (&expr1
, "sltiu", "t,r,j", dreg
, dreg
, BFD_RELOC_LO16
);
7071 case M_SGE
: /* sreg >= treg <==> not (sreg < treg) */
7077 macro_build (NULL
, s
, "d,v,t", dreg
, sreg
, treg
);
7078 macro_build (&expr1
, "xori", "t,r,i", dreg
, dreg
, BFD_RELOC_LO16
);
7081 case M_SGE_I
: /* sreg >= I <==> not (sreg < I) */
7083 if (imm_expr
.X_op
== O_constant
7084 && imm_expr
.X_add_number
>= -0x8000
7085 && imm_expr
.X_add_number
< 0x8000)
7087 macro_build (&imm_expr
, mask
== M_SGE_I
? "slti" : "sltiu", "t,r,j",
7088 dreg
, sreg
, BFD_RELOC_LO16
);
7092 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7093 macro_build (NULL
, mask
== M_SGE_I
? "slt" : "sltu", "d,v,t",
7097 macro_build (&expr1
, "xori", "t,r,i", dreg
, dreg
, BFD_RELOC_LO16
);
7100 case M_SGT
: /* sreg > treg <==> treg < sreg */
7106 macro_build (NULL
, s
, "d,v,t", dreg
, treg
, sreg
);
7109 case M_SGT_I
: /* sreg > I <==> I < sreg */
7116 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7117 macro_build (NULL
, s
, "d,v,t", dreg
, AT
, sreg
);
7120 case M_SLE
: /* sreg <= treg <==> treg >= sreg <==> not (treg < sreg) */
7126 macro_build (NULL
, s
, "d,v,t", dreg
, treg
, sreg
);
7127 macro_build (&expr1
, "xori", "t,r,i", dreg
, dreg
, BFD_RELOC_LO16
);
7130 case M_SLE_I
: /* sreg <= I <==> I >= sreg <==> not (I < sreg) */
7137 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7138 macro_build (NULL
, s
, "d,v,t", dreg
, AT
, sreg
);
7139 macro_build (&expr1
, "xori", "t,r,i", dreg
, dreg
, BFD_RELOC_LO16
);
7143 if (imm_expr
.X_op
== O_constant
7144 && imm_expr
.X_add_number
>= -0x8000
7145 && imm_expr
.X_add_number
< 0x8000)
7147 macro_build (&imm_expr
, "slti", "t,r,j", dreg
, sreg
, BFD_RELOC_LO16
);
7151 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7152 macro_build (NULL
, "slt", "d,v,t", dreg
, sreg
, AT
);
7156 if (imm_expr
.X_op
== O_constant
7157 && imm_expr
.X_add_number
>= -0x8000
7158 && imm_expr
.X_add_number
< 0x8000)
7160 macro_build (&imm_expr
, "sltiu", "t,r,j", dreg
, sreg
,
7165 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7166 macro_build (NULL
, "sltu", "d,v,t", dreg
, sreg
, AT
);
7171 macro_build (NULL
, "sltu", "d,v,t", dreg
, 0, treg
);
7173 macro_build (NULL
, "sltu", "d,v,t", dreg
, 0, sreg
);
7176 macro_build (NULL
, "xor", "d,v,t", dreg
, sreg
, treg
);
7177 macro_build (NULL
, "sltu", "d,v,t", dreg
, 0, dreg
);
7182 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
7184 macro_build (NULL
, "sltu", "d,v,t", dreg
, 0, sreg
);
7189 as_warn (_("Instruction %s: result is always true"),
7191 macro_build (&expr1
, HAVE_32BIT_GPRS
? "addiu" : "daddiu", "t,r,j",
7192 dreg
, 0, BFD_RELOC_LO16
);
7195 if (imm_expr
.X_op
== O_constant
7196 && imm_expr
.X_add_number
>= 0
7197 && imm_expr
.X_add_number
< 0x10000)
7199 macro_build (&imm_expr
, "xori", "t,r,i", dreg
, sreg
, BFD_RELOC_LO16
);
7201 else if (imm_expr
.X_op
== O_constant
7202 && imm_expr
.X_add_number
> -0x8000
7203 && imm_expr
.X_add_number
< 0)
7205 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
7206 macro_build (&imm_expr
, HAVE_32BIT_GPRS
? "addiu" : "daddiu",
7207 "t,r,j", dreg
, sreg
, BFD_RELOC_LO16
);
7211 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7212 macro_build (NULL
, "xor", "d,v,t", dreg
, sreg
, AT
);
7215 macro_build (NULL
, "sltu", "d,v,t", dreg
, 0, dreg
);
7221 if (imm_expr
.X_op
== O_constant
7222 && imm_expr
.X_add_number
> -0x8000
7223 && imm_expr
.X_add_number
<= 0x8000)
7225 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
7226 macro_build (&imm_expr
, dbl
? "daddi" : "addi", "t,r,j",
7227 dreg
, sreg
, BFD_RELOC_LO16
);
7231 load_register (AT
, &imm_expr
, dbl
);
7232 macro_build (NULL
, dbl
? "dsub" : "sub", "d,v,t", dreg
, sreg
, AT
);
7238 if (imm_expr
.X_op
== O_constant
7239 && imm_expr
.X_add_number
> -0x8000
7240 && imm_expr
.X_add_number
<= 0x8000)
7242 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
7243 macro_build (&imm_expr
, dbl
? "daddiu" : "addiu", "t,r,j",
7244 dreg
, sreg
, BFD_RELOC_LO16
);
7248 load_register (AT
, &imm_expr
, dbl
);
7249 macro_build (NULL
, dbl
? "dsubu" : "subu", "d,v,t", dreg
, sreg
, AT
);
7271 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7272 macro_build (NULL
, s
, "s,t", sreg
, AT
);
7277 assert (mips_opts
.isa
== ISA_MIPS1
);
7279 sreg
= (ip
->insn_opcode
>> 11) & 0x1f; /* floating reg */
7280 dreg
= (ip
->insn_opcode
>> 06) & 0x1f; /* floating reg */
7283 * Is the double cfc1 instruction a bug in the mips assembler;
7284 * or is there a reason for it?
7287 macro_build (NULL
, "cfc1", "t,G", treg
, RA
);
7288 macro_build (NULL
, "cfc1", "t,G", treg
, RA
);
7289 macro_build (NULL
, "nop", "");
7290 expr1
.X_add_number
= 3;
7291 macro_build (&expr1
, "ori", "t,r,i", AT
, treg
, BFD_RELOC_LO16
);
7292 expr1
.X_add_number
= 2;
7293 macro_build (&expr1
, "xori", "t,r,i", AT
, AT
, BFD_RELOC_LO16
);
7294 macro_build (NULL
, "ctc1", "t,G", AT
, RA
);
7295 macro_build (NULL
, "nop", "");
7296 macro_build (NULL
, mask
== M_TRUNCWD
? "cvt.w.d" : "cvt.w.s", "D,S",
7298 macro_build (NULL
, "ctc1", "t,G", treg
, RA
);
7299 macro_build (NULL
, "nop", "");
7310 if (offset_expr
.X_add_number
>= 0x7fff)
7311 as_bad (_("operand overflow"));
7312 if (! target_big_endian
)
7313 ++offset_expr
.X_add_number
;
7314 macro_build (&offset_expr
, s
, "t,o(b)", AT
, BFD_RELOC_LO16
, breg
);
7315 if (! target_big_endian
)
7316 --offset_expr
.X_add_number
;
7318 ++offset_expr
.X_add_number
;
7319 macro_build (&offset_expr
, "lbu", "t,o(b)", treg
, BFD_RELOC_LO16
, breg
);
7320 macro_build (NULL
, "sll", "d,w,<", AT
, AT
, 8);
7321 macro_build (NULL
, "or", "d,v,t", treg
, treg
, AT
);
7334 if (offset_expr
.X_add_number
>= 0x8000 - off
)
7335 as_bad (_("operand overflow"));
7343 if (! target_big_endian
)
7344 offset_expr
.X_add_number
+= off
;
7345 macro_build (&offset_expr
, s
, "t,o(b)", tempreg
, BFD_RELOC_LO16
, breg
);
7346 if (! target_big_endian
)
7347 offset_expr
.X_add_number
-= off
;
7349 offset_expr
.X_add_number
+= off
;
7350 macro_build (&offset_expr
, s2
, "t,o(b)", tempreg
, BFD_RELOC_LO16
, breg
);
7352 /* If necessary, move the result in tempreg the final destination. */
7353 if (treg
== tempreg
)
7355 /* Protect second load's delay slot. */
7357 move_register (treg
, tempreg
);
7371 load_address (AT
, &offset_expr
, &used_at
);
7373 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, AT
, breg
);
7374 if (! target_big_endian
)
7375 expr1
.X_add_number
= off
;
7377 expr1
.X_add_number
= 0;
7378 macro_build (&expr1
, s
, "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
7379 if (! target_big_endian
)
7380 expr1
.X_add_number
= 0;
7382 expr1
.X_add_number
= off
;
7383 macro_build (&expr1
, s2
, "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
7389 load_address (AT
, &offset_expr
, &used_at
);
7391 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, AT
, breg
);
7392 if (target_big_endian
)
7393 expr1
.X_add_number
= 0;
7394 macro_build (&expr1
, mask
== M_ULH_A
? "lb" : "lbu", "t,o(b)",
7395 treg
, BFD_RELOC_LO16
, AT
);
7396 if (target_big_endian
)
7397 expr1
.X_add_number
= 1;
7399 expr1
.X_add_number
= 0;
7400 macro_build (&expr1
, "lbu", "t,o(b)", AT
, BFD_RELOC_LO16
, AT
);
7401 macro_build (NULL
, "sll", "d,w,<", treg
, treg
, 8);
7402 macro_build (NULL
, "or", "d,v,t", treg
, treg
, AT
);
7407 if (offset_expr
.X_add_number
>= 0x7fff)
7408 as_bad (_("operand overflow"));
7409 if (target_big_endian
)
7410 ++offset_expr
.X_add_number
;
7411 macro_build (&offset_expr
, "sb", "t,o(b)", treg
, BFD_RELOC_LO16
, breg
);
7412 macro_build (NULL
, "srl", "d,w,<", AT
, treg
, 8);
7413 if (target_big_endian
)
7414 --offset_expr
.X_add_number
;
7416 ++offset_expr
.X_add_number
;
7417 macro_build (&offset_expr
, "sb", "t,o(b)", AT
, BFD_RELOC_LO16
, breg
);
7430 if (offset_expr
.X_add_number
>= 0x8000 - off
)
7431 as_bad (_("operand overflow"));
7432 if (! target_big_endian
)
7433 offset_expr
.X_add_number
+= off
;
7434 macro_build (&offset_expr
, s
, "t,o(b)", treg
, BFD_RELOC_LO16
, breg
);
7435 if (! target_big_endian
)
7436 offset_expr
.X_add_number
-= off
;
7438 offset_expr
.X_add_number
+= off
;
7439 macro_build (&offset_expr
, s2
, "t,o(b)", treg
, BFD_RELOC_LO16
, breg
);
7453 load_address (AT
, &offset_expr
, &used_at
);
7455 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, AT
, breg
);
7456 if (! target_big_endian
)
7457 expr1
.X_add_number
= off
;
7459 expr1
.X_add_number
= 0;
7460 macro_build (&expr1
, s
, "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
7461 if (! target_big_endian
)
7462 expr1
.X_add_number
= 0;
7464 expr1
.X_add_number
= off
;
7465 macro_build (&expr1
, s2
, "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
7470 load_address (AT
, &offset_expr
, &used_at
);
7472 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, AT
, breg
);
7473 if (! target_big_endian
)
7474 expr1
.X_add_number
= 0;
7475 macro_build (&expr1
, "sb", "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
7476 macro_build (NULL
, "srl", "d,w,<", treg
, treg
, 8);
7477 if (! target_big_endian
)
7478 expr1
.X_add_number
= 1;
7480 expr1
.X_add_number
= 0;
7481 macro_build (&expr1
, "sb", "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
7482 if (! target_big_endian
)
7483 expr1
.X_add_number
= 0;
7485 expr1
.X_add_number
= 1;
7486 macro_build (&expr1
, "lbu", "t,o(b)", AT
, BFD_RELOC_LO16
, AT
);
7487 macro_build (NULL
, "sll", "d,w,<", treg
, treg
, 8);
7488 macro_build (NULL
, "or", "d,v,t", treg
, treg
, AT
);
7492 /* FIXME: Check if this is one of the itbl macros, since they
7493 are added dynamically. */
7494 as_bad (_("Macro %s not implemented yet"), ip
->insn_mo
->name
);
7497 if (mips_opts
.noat
&& used_at
)
7498 as_bad (_("Macro used $at after \".set noat\""));
7501 /* Implement macros in mips16 mode. */
7504 mips16_macro (struct mips_cl_insn
*ip
)
7507 int xreg
, yreg
, zreg
, tmp
;
7510 const char *s
, *s2
, *s3
;
7512 mask
= ip
->insn_mo
->mask
;
7514 xreg
= MIPS16_EXTRACT_OPERAND (RX
, *ip
);
7515 yreg
= MIPS16_EXTRACT_OPERAND (RY
, *ip
);
7516 zreg
= MIPS16_EXTRACT_OPERAND (RZ
, *ip
);
7518 expr1
.X_op
= O_constant
;
7519 expr1
.X_op_symbol
= NULL
;
7520 expr1
.X_add_symbol
= NULL
;
7521 expr1
.X_add_number
= 1;
7541 macro_build (NULL
, dbl
? "ddiv" : "div", "0,x,y", xreg
, yreg
);
7542 expr1
.X_add_number
= 2;
7543 macro_build (&expr1
, "bnez", "x,p", yreg
);
7544 macro_build (NULL
, "break", "6", 7);
7546 /* FIXME: The normal code checks for of -1 / -0x80000000 here,
7547 since that causes an overflow. We should do that as well,
7548 but I don't see how to do the comparisons without a temporary
7551 macro_build (NULL
, s
, "x", zreg
);
7571 macro_build (NULL
, s
, "0,x,y", xreg
, yreg
);
7572 expr1
.X_add_number
= 2;
7573 macro_build (&expr1
, "bnez", "x,p", yreg
);
7574 macro_build (NULL
, "break", "6", 7);
7576 macro_build (NULL
, s2
, "x", zreg
);
7582 macro_build (NULL
, dbl
? "dmultu" : "multu", "x,y", xreg
, yreg
);
7583 macro_build (NULL
, "mflo", "x", zreg
);
7591 if (imm_expr
.X_op
!= O_constant
)
7592 as_bad (_("Unsupported large constant"));
7593 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
7594 macro_build (&imm_expr
, dbl
? "daddiu" : "addiu", "y,x,4", yreg
, xreg
);
7598 if (imm_expr
.X_op
!= O_constant
)
7599 as_bad (_("Unsupported large constant"));
7600 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
7601 macro_build (&imm_expr
, "addiu", "x,k", xreg
);
7605 if (imm_expr
.X_op
!= O_constant
)
7606 as_bad (_("Unsupported large constant"));
7607 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
7608 macro_build (&imm_expr
, "daddiu", "y,j", yreg
);
7630 goto do_reverse_branch
;
7634 goto do_reverse_branch
;
7646 goto do_reverse_branch
;
7657 macro_build (NULL
, s
, "x,y", xreg
, yreg
);
7658 macro_build (&offset_expr
, s2
, "p");
7685 goto do_addone_branch_i
;
7690 goto do_addone_branch_i
;
7705 goto do_addone_branch_i
;
7712 if (imm_expr
.X_op
!= O_constant
)
7713 as_bad (_("Unsupported large constant"));
7714 ++imm_expr
.X_add_number
;
7717 macro_build (&imm_expr
, s
, s3
, xreg
);
7718 macro_build (&offset_expr
, s2
, "p");
7722 expr1
.X_add_number
= 0;
7723 macro_build (&expr1
, "slti", "x,8", yreg
);
7725 move_register (xreg
, yreg
);
7726 expr1
.X_add_number
= 2;
7727 macro_build (&expr1
, "bteqz", "p");
7728 macro_build (NULL
, "neg", "x,w", xreg
, xreg
);
7732 /* For consistency checking, verify that all bits are specified either
7733 by the match/mask part of the instruction definition, or by the
7736 validate_mips_insn (const struct mips_opcode
*opc
)
7738 const char *p
= opc
->args
;
7740 unsigned long used_bits
= opc
->mask
;
7742 if ((used_bits
& opc
->match
) != opc
->match
)
7744 as_bad (_("internal: bad mips opcode (mask error): %s %s"),
7745 opc
->name
, opc
->args
);
7748 #define USE_BITS(mask,shift) (used_bits |= ((mask) << (shift)))
7758 case 'A': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
7759 case 'B': USE_BITS (OP_MASK_INSMSB
, OP_SH_INSMSB
); break;
7760 case 'C': USE_BITS (OP_MASK_EXTMSBD
, OP_SH_EXTMSBD
); break;
7761 case 'D': USE_BITS (OP_MASK_RD
, OP_SH_RD
);
7762 USE_BITS (OP_MASK_SEL
, OP_SH_SEL
); break;
7763 case 'E': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
7764 case 'F': USE_BITS (OP_MASK_INSMSB
, OP_SH_INSMSB
); break;
7765 case 'G': USE_BITS (OP_MASK_EXTMSBD
, OP_SH_EXTMSBD
); break;
7766 case 'H': USE_BITS (OP_MASK_EXTMSBD
, OP_SH_EXTMSBD
); break;
7769 as_bad (_("internal: bad mips opcode (unknown extension operand type `+%c'): %s %s"),
7770 c
, opc
->name
, opc
->args
);
7774 case '<': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
7775 case '>': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
7777 case 'B': USE_BITS (OP_MASK_CODE20
, OP_SH_CODE20
); break;
7778 case 'C': USE_BITS (OP_MASK_COPZ
, OP_SH_COPZ
); break;
7779 case 'D': USE_BITS (OP_MASK_FD
, OP_SH_FD
); break;
7780 case 'E': USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
7782 case 'G': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
7783 case 'H': USE_BITS (OP_MASK_SEL
, OP_SH_SEL
); break;
7785 case 'J': USE_BITS (OP_MASK_CODE19
, OP_SH_CODE19
); break;
7786 case 'K': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
7788 case 'M': USE_BITS (OP_MASK_CCC
, OP_SH_CCC
); break;
7789 case 'N': USE_BITS (OP_MASK_BCC
, OP_SH_BCC
); break;
7790 case 'O': USE_BITS (OP_MASK_ALN
, OP_SH_ALN
); break;
7791 case 'Q': USE_BITS (OP_MASK_VSEL
, OP_SH_VSEL
);
7792 USE_BITS (OP_MASK_FT
, OP_SH_FT
); break;
7793 case 'R': USE_BITS (OP_MASK_FR
, OP_SH_FR
); break;
7794 case 'S': USE_BITS (OP_MASK_FS
, OP_SH_FS
); break;
7795 case 'T': USE_BITS (OP_MASK_FT
, OP_SH_FT
); break;
7796 case 'V': USE_BITS (OP_MASK_FS
, OP_SH_FS
); break;
7797 case 'W': USE_BITS (OP_MASK_FT
, OP_SH_FT
); break;
7798 case 'X': USE_BITS (OP_MASK_FD
, OP_SH_FD
); break;
7799 case 'Y': USE_BITS (OP_MASK_FS
, OP_SH_FS
); break;
7800 case 'Z': USE_BITS (OP_MASK_FT
, OP_SH_FT
); break;
7801 case 'a': USE_BITS (OP_MASK_TARGET
, OP_SH_TARGET
); break;
7802 case 'b': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
7803 case 'c': USE_BITS (OP_MASK_CODE
, OP_SH_CODE
); break;
7804 case 'd': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
7806 case 'h': USE_BITS (OP_MASK_PREFX
, OP_SH_PREFX
); break;
7807 case 'i': USE_BITS (OP_MASK_IMMEDIATE
, OP_SH_IMMEDIATE
); break;
7808 case 'j': USE_BITS (OP_MASK_DELTA
, OP_SH_DELTA
); break;
7809 case 'k': USE_BITS (OP_MASK_CACHE
, OP_SH_CACHE
); break;
7811 case 'o': USE_BITS (OP_MASK_DELTA
, OP_SH_DELTA
); break;
7812 case 'p': USE_BITS (OP_MASK_DELTA
, OP_SH_DELTA
); break;
7813 case 'q': USE_BITS (OP_MASK_CODE2
, OP_SH_CODE2
); break;
7814 case 'r': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
7815 case 's': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
7816 case 't': USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
7817 case 'u': USE_BITS (OP_MASK_IMMEDIATE
, OP_SH_IMMEDIATE
); break;
7818 case 'v': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
7819 case 'w': USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
7822 case 'P': USE_BITS (OP_MASK_PERFREG
, OP_SH_PERFREG
); break;
7823 case 'U': USE_BITS (OP_MASK_RD
, OP_SH_RD
);
7824 USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
7825 case 'e': USE_BITS (OP_MASK_VECBYTE
, OP_SH_VECBYTE
); break;
7826 case '%': USE_BITS (OP_MASK_VECALIGN
, OP_SH_VECALIGN
); break;
7829 case '3': USE_BITS (OP_MASK_SA3
, OP_SH_SA3
); break;
7830 case '4': USE_BITS (OP_MASK_SA4
, OP_SH_SA4
); break;
7831 case '5': USE_BITS (OP_MASK_IMM8
, OP_SH_IMM8
); break;
7832 case '6': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
7833 case '7': USE_BITS (OP_MASK_DSPACC
, OP_SH_DSPACC
); break;
7834 case '8': USE_BITS (OP_MASK_WRDSP
, OP_SH_WRDSP
); break;
7835 case '9': USE_BITS (OP_MASK_DSPACC_S
, OP_SH_DSPACC_S
);break;
7836 case '0': USE_BITS (OP_MASK_DSPSFT
, OP_SH_DSPSFT
); break;
7837 case '\'': USE_BITS (OP_MASK_RDDSP
, OP_SH_RDDSP
); break;
7838 case ':': USE_BITS (OP_MASK_DSPSFT_7
, OP_SH_DSPSFT_7
);break;
7839 case '@': USE_BITS (OP_MASK_IMM10
, OP_SH_IMM10
); break;
7841 as_bad (_("internal: bad mips opcode (unknown operand type `%c'): %s %s"),
7842 c
, opc
->name
, opc
->args
);
7846 if (used_bits
!= 0xffffffff)
7848 as_bad (_("internal: bad mips opcode (bits 0x%lx undefined): %s %s"),
7849 ~used_bits
& 0xffffffff, opc
->name
, opc
->args
);
7855 /* This routine assembles an instruction into its binary format. As a
7856 side effect, it sets one of the global variables imm_reloc or
7857 offset_reloc to the type of relocation to do if one of the operands
7858 is an address expression. */
7861 mips_ip (char *str
, struct mips_cl_insn
*ip
)
7866 struct mips_opcode
*insn
;
7869 unsigned int lastregno
= 0;
7870 unsigned int lastpos
= 0;
7871 unsigned int limlo
, limhi
;
7874 offsetT min_range
, max_range
;
7878 /* If the instruction contains a '.', we first try to match an instruction
7879 including the '.'. Then we try again without the '.'. */
7881 for (s
= str
; *s
!= '\0' && !ISSPACE (*s
); ++s
)
7884 /* If we stopped on whitespace, then replace the whitespace with null for
7885 the call to hash_find. Save the character we replaced just in case we
7886 have to re-parse the instruction. */
7893 insn
= (struct mips_opcode
*) hash_find (op_hash
, str
);
7895 /* If we didn't find the instruction in the opcode table, try again, but
7896 this time with just the instruction up to, but not including the
7900 /* Restore the character we overwrite above (if any). */
7904 /* Scan up to the first '.' or whitespace. */
7906 *s
!= '\0' && *s
!= '.' && !ISSPACE (*s
);
7910 /* If we did not find a '.', then we can quit now. */
7913 insn_error
= "unrecognized opcode";
7917 /* Lookup the instruction in the hash table. */
7919 if ((insn
= (struct mips_opcode
*) hash_find (op_hash
, str
)) == NULL
)
7921 insn_error
= "unrecognized opcode";
7931 assert (strcmp (insn
->name
, str
) == 0);
7933 if (OPCODE_IS_MEMBER (insn
,
7935 | (file_ase_mips16
? INSN_MIPS16
: 0)
7936 | (mips_opts
.ase_mdmx
? INSN_MDMX
: 0)
7937 | (mips_opts
.ase_dsp
? INSN_DSP
: 0)
7938 | (mips_opts
.ase_mips3d
? INSN_MIPS3D
: 0)),
7944 if (insn
->pinfo
!= INSN_MACRO
)
7946 if (mips_opts
.arch
== CPU_R4650
&& (insn
->pinfo
& FP_D
) != 0)
7952 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
]
7953 && strcmp (insn
->name
, insn
[1].name
) == 0)
7962 static char buf
[100];
7964 _("opcode not supported on this processor: %s (%s)"),
7965 mips_cpu_info_from_arch (mips_opts
.arch
)->name
,
7966 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
7975 create_insn (ip
, insn
);
7977 for (args
= insn
->args
;; ++args
)
7981 s
+= strspn (s
, " \t");
7985 case '\0': /* end of args */
7990 case '3': /* dsp 3-bit unsigned immediate in bit 21 */
7991 my_getExpression (&imm_expr
, s
);
7992 check_absolute_expr (ip
, &imm_expr
);
7993 if (imm_expr
.X_add_number
& ~OP_MASK_SA3
)
7995 as_warn (_("DSP immediate not in range 0..%d (%lu)"),
7996 OP_MASK_SA3
, (unsigned long) imm_expr
.X_add_number
);
7997 imm_expr
.X_add_number
&= OP_MASK_SA3
;
7999 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_SA3
;
8000 imm_expr
.X_op
= O_absent
;
8004 case '4': /* dsp 4-bit unsigned immediate in bit 21 */
8005 my_getExpression (&imm_expr
, s
);
8006 check_absolute_expr (ip
, &imm_expr
);
8007 if (imm_expr
.X_add_number
& ~OP_MASK_SA4
)
8009 as_warn (_("DSP immediate not in range 0..%d (%lu)"),
8010 OP_MASK_SA4
, (unsigned long) imm_expr
.X_add_number
);
8011 imm_expr
.X_add_number
&= OP_MASK_SA4
;
8013 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_SA4
;
8014 imm_expr
.X_op
= O_absent
;
8018 case '5': /* dsp 8-bit unsigned immediate in bit 16 */
8019 my_getExpression (&imm_expr
, s
);
8020 check_absolute_expr (ip
, &imm_expr
);
8021 if (imm_expr
.X_add_number
& ~OP_MASK_IMM8
)
8023 as_warn (_("DSP immediate not in range 0..%d (%lu)"),
8024 OP_MASK_IMM8
, (unsigned long) imm_expr
.X_add_number
);
8025 imm_expr
.X_add_number
&= OP_MASK_IMM8
;
8027 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_IMM8
;
8028 imm_expr
.X_op
= O_absent
;
8032 case '6': /* dsp 5-bit unsigned immediate in bit 21 */
8033 my_getExpression (&imm_expr
, s
);
8034 check_absolute_expr (ip
, &imm_expr
);
8035 if (imm_expr
.X_add_number
& ~OP_MASK_RS
)
8037 as_warn (_("DSP immediate not in range 0..%d (%lu)"),
8038 OP_MASK_RS
, (unsigned long) imm_expr
.X_add_number
);
8039 imm_expr
.X_add_number
&= OP_MASK_RS
;
8041 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_RS
;
8042 imm_expr
.X_op
= O_absent
;
8046 case '7': /* four dsp accumulators in bits 11,12 */
8047 if (s
[0] == '$' && s
[1] == 'a' && s
[2] == 'c' &&
8048 s
[3] >= '0' && s
[3] <= '3')
8052 ip
->insn_opcode
|= regno
<< OP_SH_DSPACC
;
8056 as_bad (_("Invalid dsp acc register"));
8059 case '8': /* dsp 6-bit unsigned immediate in bit 11 */
8060 my_getExpression (&imm_expr
, s
);
8061 check_absolute_expr (ip
, &imm_expr
);
8062 if (imm_expr
.X_add_number
& ~OP_MASK_WRDSP
)
8064 as_warn (_("DSP immediate not in range 0..%d (%lu)"),
8066 (unsigned long) imm_expr
.X_add_number
);
8067 imm_expr
.X_add_number
&= OP_MASK_WRDSP
;
8069 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_WRDSP
;
8070 imm_expr
.X_op
= O_absent
;
8074 case '9': /* four dsp accumulators in bits 21,22 */
8075 if (s
[0] == '$' && s
[1] == 'a' && s
[2] == 'c' &&
8076 s
[3] >= '0' && s
[3] <= '3')
8080 ip
->insn_opcode
|= regno
<< OP_SH_DSPACC_S
;
8084 as_bad (_("Invalid dsp acc register"));
8087 case '0': /* dsp 6-bit signed immediate in bit 20 */
8088 my_getExpression (&imm_expr
, s
);
8089 check_absolute_expr (ip
, &imm_expr
);
8090 min_range
= -((OP_MASK_DSPSFT
+ 1) >> 1);
8091 max_range
= ((OP_MASK_DSPSFT
+ 1) >> 1) - 1;
8092 if (imm_expr
.X_add_number
< min_range
||
8093 imm_expr
.X_add_number
> max_range
)
8095 as_warn (_("DSP immediate not in range %ld..%ld (%ld)"),
8096 (long) min_range
, (long) max_range
,
8097 (long) imm_expr
.X_add_number
);
8099 imm_expr
.X_add_number
&= OP_MASK_DSPSFT
;
8100 ip
->insn_opcode
|= ((unsigned long) imm_expr
.X_add_number
8102 imm_expr
.X_op
= O_absent
;
8106 case '\'': /* dsp 6-bit unsigned immediate in bit 16 */
8107 my_getExpression (&imm_expr
, s
);
8108 check_absolute_expr (ip
, &imm_expr
);
8109 if (imm_expr
.X_add_number
& ~OP_MASK_RDDSP
)
8111 as_warn (_("DSP immediate not in range 0..%d (%lu)"),
8113 (unsigned long) imm_expr
.X_add_number
);
8114 imm_expr
.X_add_number
&= OP_MASK_RDDSP
;
8116 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_RDDSP
;
8117 imm_expr
.X_op
= O_absent
;
8121 case ':': /* dsp 7-bit signed immediate in bit 19 */
8122 my_getExpression (&imm_expr
, s
);
8123 check_absolute_expr (ip
, &imm_expr
);
8124 min_range
= -((OP_MASK_DSPSFT_7
+ 1) >> 1);
8125 max_range
= ((OP_MASK_DSPSFT_7
+ 1) >> 1) - 1;
8126 if (imm_expr
.X_add_number
< min_range
||
8127 imm_expr
.X_add_number
> max_range
)
8129 as_warn (_("DSP immediate not in range %ld..%ld (%ld)"),
8130 (long) min_range
, (long) max_range
,
8131 (long) imm_expr
.X_add_number
);
8133 imm_expr
.X_add_number
&= OP_MASK_DSPSFT_7
;
8134 ip
->insn_opcode
|= ((unsigned long) imm_expr
.X_add_number
8136 imm_expr
.X_op
= O_absent
;
8140 case '@': /* dsp 10-bit signed immediate in bit 16 */
8141 my_getExpression (&imm_expr
, s
);
8142 check_absolute_expr (ip
, &imm_expr
);
8143 min_range
= -((OP_MASK_IMM10
+ 1) >> 1);
8144 max_range
= ((OP_MASK_IMM10
+ 1) >> 1) - 1;
8145 if (imm_expr
.X_add_number
< min_range
||
8146 imm_expr
.X_add_number
> max_range
)
8148 as_warn (_("DSP immediate not in range %ld..%ld (%ld)"),
8149 (long) min_range
, (long) max_range
,
8150 (long) imm_expr
.X_add_number
);
8152 imm_expr
.X_add_number
&= OP_MASK_IMM10
;
8153 ip
->insn_opcode
|= ((unsigned long) imm_expr
.X_add_number
8155 imm_expr
.X_op
= O_absent
;
8167 INSERT_OPERAND (RS
, *ip
, lastregno
);
8171 INSERT_OPERAND (RT
, *ip
, lastregno
);
8175 INSERT_OPERAND (FT
, *ip
, lastregno
);
8179 INSERT_OPERAND (FS
, *ip
, lastregno
);
8185 /* Handle optional base register.
8186 Either the base register is omitted or
8187 we must have a left paren. */
8188 /* This is dependent on the next operand specifier
8189 is a base register specification. */
8190 assert (args
[1] == 'b' || args
[1] == '5'
8191 || args
[1] == '-' || args
[1] == '4');
8195 case ')': /* these must match exactly */
8202 case '+': /* Opcode extension character. */
8205 case 'A': /* ins/ext position, becomes LSB. */
8214 my_getExpression (&imm_expr
, s
);
8215 check_absolute_expr (ip
, &imm_expr
);
8216 if ((unsigned long) imm_expr
.X_add_number
< limlo
8217 || (unsigned long) imm_expr
.X_add_number
> limhi
)
8219 as_bad (_("Improper position (%lu)"),
8220 (unsigned long) imm_expr
.X_add_number
);
8221 imm_expr
.X_add_number
= limlo
;
8223 lastpos
= imm_expr
.X_add_number
;
8224 INSERT_OPERAND (SHAMT
, *ip
, imm_expr
.X_add_number
);
8225 imm_expr
.X_op
= O_absent
;
8229 case 'B': /* ins size, becomes MSB. */
8238 my_getExpression (&imm_expr
, s
);
8239 check_absolute_expr (ip
, &imm_expr
);
8240 /* Check for negative input so that small negative numbers
8241 will not succeed incorrectly. The checks against
8242 (pos+size) transitively check "size" itself,
8243 assuming that "pos" is reasonable. */
8244 if ((long) imm_expr
.X_add_number
< 0
8245 || ((unsigned long) imm_expr
.X_add_number
8247 || ((unsigned long) imm_expr
.X_add_number
8250 as_bad (_("Improper insert size (%lu, position %lu)"),
8251 (unsigned long) imm_expr
.X_add_number
,
8252 (unsigned long) lastpos
);
8253 imm_expr
.X_add_number
= limlo
- lastpos
;
8255 INSERT_OPERAND (INSMSB
, *ip
,
8256 lastpos
+ imm_expr
.X_add_number
- 1);
8257 imm_expr
.X_op
= O_absent
;
8261 case 'C': /* ext size, becomes MSBD. */
8274 my_getExpression (&imm_expr
, s
);
8275 check_absolute_expr (ip
, &imm_expr
);
8276 /* Check for negative input so that small negative numbers
8277 will not succeed incorrectly. The checks against
8278 (pos+size) transitively check "size" itself,
8279 assuming that "pos" is reasonable. */
8280 if ((long) imm_expr
.X_add_number
< 0
8281 || ((unsigned long) imm_expr
.X_add_number
8283 || ((unsigned long) imm_expr
.X_add_number
8286 as_bad (_("Improper extract size (%lu, position %lu)"),
8287 (unsigned long) imm_expr
.X_add_number
,
8288 (unsigned long) lastpos
);
8289 imm_expr
.X_add_number
= limlo
- lastpos
;
8291 INSERT_OPERAND (EXTMSBD
, *ip
, imm_expr
.X_add_number
- 1);
8292 imm_expr
.X_op
= O_absent
;
8297 /* +D is for disassembly only; never match. */
8301 /* "+I" is like "I", except that imm2_expr is used. */
8302 my_getExpression (&imm2_expr
, s
);
8303 if (imm2_expr
.X_op
!= O_big
8304 && imm2_expr
.X_op
!= O_constant
)
8305 insn_error
= _("absolute expression required");
8306 if (HAVE_32BIT_GPRS
)
8307 normalize_constant_expr (&imm2_expr
);
8312 as_bad (_("internal: bad mips opcode (unknown extension operand type `+%c'): %s %s"),
8313 *args
, insn
->name
, insn
->args
);
8314 /* Further processing is fruitless. */
8319 case '<': /* must be at least one digit */
8321 * According to the manual, if the shift amount is greater
8322 * than 31 or less than 0, then the shift amount should be
8323 * mod 32. In reality the mips assembler issues an error.
8324 * We issue a warning and mask out all but the low 5 bits.
8326 my_getExpression (&imm_expr
, s
);
8327 check_absolute_expr (ip
, &imm_expr
);
8328 if ((unsigned long) imm_expr
.X_add_number
> 31)
8329 as_warn (_("Improper shift amount (%lu)"),
8330 (unsigned long) imm_expr
.X_add_number
);
8331 INSERT_OPERAND (SHAMT
, *ip
, imm_expr
.X_add_number
);
8332 imm_expr
.X_op
= O_absent
;
8336 case '>': /* shift amount minus 32 */
8337 my_getExpression (&imm_expr
, s
);
8338 check_absolute_expr (ip
, &imm_expr
);
8339 if ((unsigned long) imm_expr
.X_add_number
< 32
8340 || (unsigned long) imm_expr
.X_add_number
> 63)
8342 INSERT_OPERAND (SHAMT
, *ip
, imm_expr
.X_add_number
- 32);
8343 imm_expr
.X_op
= O_absent
;
8347 case 'k': /* cache code */
8348 case 'h': /* prefx code */
8349 my_getExpression (&imm_expr
, s
);
8350 check_absolute_expr (ip
, &imm_expr
);
8351 if ((unsigned long) imm_expr
.X_add_number
> 31)
8352 as_warn (_("Invalid value for `%s' (%lu)"),
8354 (unsigned long) imm_expr
.X_add_number
);
8356 INSERT_OPERAND (CACHE
, *ip
, imm_expr
.X_add_number
);
8358 INSERT_OPERAND (PREFX
, *ip
, imm_expr
.X_add_number
);
8359 imm_expr
.X_op
= O_absent
;
8363 case 'c': /* break code */
8364 my_getExpression (&imm_expr
, s
);
8365 check_absolute_expr (ip
, &imm_expr
);
8366 if ((unsigned long) imm_expr
.X_add_number
> 1023)
8367 as_warn (_("Illegal break code (%lu)"),
8368 (unsigned long) imm_expr
.X_add_number
);
8369 INSERT_OPERAND (CODE
, *ip
, imm_expr
.X_add_number
);
8370 imm_expr
.X_op
= O_absent
;
8374 case 'q': /* lower break code */
8375 my_getExpression (&imm_expr
, s
);
8376 check_absolute_expr (ip
, &imm_expr
);
8377 if ((unsigned long) imm_expr
.X_add_number
> 1023)
8378 as_warn (_("Illegal lower break code (%lu)"),
8379 (unsigned long) imm_expr
.X_add_number
);
8380 INSERT_OPERAND (CODE2
, *ip
, imm_expr
.X_add_number
);
8381 imm_expr
.X_op
= O_absent
;
8385 case 'B': /* 20-bit syscall/break code. */
8386 my_getExpression (&imm_expr
, s
);
8387 check_absolute_expr (ip
, &imm_expr
);
8388 if ((unsigned long) imm_expr
.X_add_number
> OP_MASK_CODE20
)
8389 as_warn (_("Illegal 20-bit code (%lu)"),
8390 (unsigned long) imm_expr
.X_add_number
);
8391 INSERT_OPERAND (CODE20
, *ip
, imm_expr
.X_add_number
);
8392 imm_expr
.X_op
= O_absent
;
8396 case 'C': /* Coprocessor code */
8397 my_getExpression (&imm_expr
, s
);
8398 check_absolute_expr (ip
, &imm_expr
);
8399 if ((unsigned long) imm_expr
.X_add_number
>= (1 << 25))
8401 as_warn (_("Coproccesor code > 25 bits (%lu)"),
8402 (unsigned long) imm_expr
.X_add_number
);
8403 imm_expr
.X_add_number
&= ((1 << 25) - 1);
8405 ip
->insn_opcode
|= imm_expr
.X_add_number
;
8406 imm_expr
.X_op
= O_absent
;
8410 case 'J': /* 19-bit wait code. */
8411 my_getExpression (&imm_expr
, s
);
8412 check_absolute_expr (ip
, &imm_expr
);
8413 if ((unsigned long) imm_expr
.X_add_number
> OP_MASK_CODE19
)
8414 as_warn (_("Illegal 19-bit code (%lu)"),
8415 (unsigned long) imm_expr
.X_add_number
);
8416 INSERT_OPERAND (CODE19
, *ip
, imm_expr
.X_add_number
);
8417 imm_expr
.X_op
= O_absent
;
8421 case 'P': /* Performance register */
8422 my_getExpression (&imm_expr
, s
);
8423 check_absolute_expr (ip
, &imm_expr
);
8424 if (imm_expr
.X_add_number
!= 0 && imm_expr
.X_add_number
!= 1)
8425 as_warn (_("Invalid performance register (%lu)"),
8426 (unsigned long) imm_expr
.X_add_number
);
8427 INSERT_OPERAND (PERFREG
, *ip
, imm_expr
.X_add_number
);
8428 imm_expr
.X_op
= O_absent
;
8432 case 'b': /* base register */
8433 case 'd': /* destination register */
8434 case 's': /* source register */
8435 case 't': /* target register */
8436 case 'r': /* both target and source */
8437 case 'v': /* both dest and source */
8438 case 'w': /* both dest and target */
8439 case 'E': /* coprocessor target register */
8440 case 'G': /* coprocessor destination register */
8441 case 'K': /* 'rdhwr' destination register */
8442 case 'x': /* ignore register name */
8443 case 'z': /* must be zero register */
8444 case 'U': /* destination register (clo/clz). */
8459 while (ISDIGIT (*s
));
8461 as_bad (_("Invalid register number (%d)"), regno
);
8463 else if (*args
== 'E' || *args
== 'G' || *args
== 'K')
8467 if (s
[1] == 'r' && s
[2] == 'a')
8472 else if (s
[1] == 'f' && s
[2] == 'p')
8477 else if (s
[1] == 's' && s
[2] == 'p')
8482 else if (s
[1] == 'g' && s
[2] == 'p')
8487 else if (s
[1] == 'a' && s
[2] == 't')
8492 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '0')
8497 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '1')
8502 else if (s
[1] == 'z' && s
[2] == 'e' && s
[3] == 'r' && s
[4] == 'o')
8507 else if (itbl_have_entries
)
8512 p
= s
+ 1; /* advance past '$' */
8513 n
= itbl_get_field (&p
); /* n is name */
8515 /* See if this is a register defined in an
8517 if (itbl_get_reg_val (n
, &r
))
8519 /* Get_field advances to the start of
8520 the next field, so we need to back
8521 rack to the end of the last field. */
8525 s
= strchr (s
, '\0');
8539 as_warn (_("Used $at without \".set noat\""));
8545 if (c
== 'r' || c
== 'v' || c
== 'w')
8552 /* 'z' only matches $0. */
8553 if (c
== 'z' && regno
!= 0)
8556 /* Now that we have assembled one operand, we use the args string
8557 * to figure out where it goes in the instruction. */
8564 INSERT_OPERAND (RS
, *ip
, regno
);
8569 INSERT_OPERAND (RD
, *ip
, regno
);
8572 INSERT_OPERAND (RD
, *ip
, regno
);
8573 INSERT_OPERAND (RT
, *ip
, regno
);
8578 INSERT_OPERAND (RT
, *ip
, regno
);
8581 /* This case exists because on the r3000 trunc
8582 expands into a macro which requires a gp
8583 register. On the r6000 or r4000 it is
8584 assembled into a single instruction which
8585 ignores the register. Thus the insn version
8586 is MIPS_ISA2 and uses 'x', and the macro
8587 version is MIPS_ISA1 and uses 't'. */
8590 /* This case is for the div instruction, which
8591 acts differently if the destination argument
8592 is $0. This only matches $0, and is checked
8593 outside the switch. */
8596 /* Itbl operand; not yet implemented. FIXME ?? */
8598 /* What about all other operands like 'i', which
8599 can be specified in the opcode table? */
8609 INSERT_OPERAND (RS
, *ip
, lastregno
);
8612 INSERT_OPERAND (RT
, *ip
, lastregno
);
8617 case 'O': /* MDMX alignment immediate constant. */
8618 my_getExpression (&imm_expr
, s
);
8619 check_absolute_expr (ip
, &imm_expr
);
8620 if ((unsigned long) imm_expr
.X_add_number
> OP_MASK_ALN
)
8621 as_warn ("Improper align amount (%ld), using low bits",
8622 (long) imm_expr
.X_add_number
);
8623 INSERT_OPERAND (ALN
, *ip
, imm_expr
.X_add_number
);
8624 imm_expr
.X_op
= O_absent
;
8628 case 'Q': /* MDMX vector, element sel, or const. */
8631 /* MDMX Immediate. */
8632 my_getExpression (&imm_expr
, s
);
8633 check_absolute_expr (ip
, &imm_expr
);
8634 if ((unsigned long) imm_expr
.X_add_number
> OP_MASK_FT
)
8635 as_warn (_("Invalid MDMX Immediate (%ld)"),
8636 (long) imm_expr
.X_add_number
);
8637 INSERT_OPERAND (FT
, *ip
, imm_expr
.X_add_number
);
8638 if (ip
->insn_opcode
& (OP_MASK_VSEL
<< OP_SH_VSEL
))
8639 ip
->insn_opcode
|= MDMX_FMTSEL_IMM_QH
<< OP_SH_VSEL
;
8641 ip
->insn_opcode
|= MDMX_FMTSEL_IMM_OB
<< OP_SH_VSEL
;
8642 imm_expr
.X_op
= O_absent
;
8646 /* Not MDMX Immediate. Fall through. */
8647 case 'X': /* MDMX destination register. */
8648 case 'Y': /* MDMX source register. */
8649 case 'Z': /* MDMX target register. */
8651 case 'D': /* floating point destination register */
8652 case 'S': /* floating point source register */
8653 case 'T': /* floating point target register */
8654 case 'R': /* floating point source register */
8658 /* Accept $fN for FP and MDMX register numbers, and in
8659 addition accept $vN for MDMX register numbers. */
8660 if ((s
[0] == '$' && s
[1] == 'f' && ISDIGIT (s
[2]))
8661 || (is_mdmx
!= 0 && s
[0] == '$' && s
[1] == 'v'
8672 while (ISDIGIT (*s
));
8675 as_bad (_("Invalid float register number (%d)"), regno
);
8677 if ((regno
& 1) != 0
8679 && ! (strcmp (str
, "mtc1") == 0
8680 || strcmp (str
, "mfc1") == 0
8681 || strcmp (str
, "lwc1") == 0
8682 || strcmp (str
, "swc1") == 0
8683 || strcmp (str
, "l.s") == 0
8684 || strcmp (str
, "s.s") == 0))
8685 as_warn (_("Float register should be even, was %d"),
8693 if (c
== 'V' || c
== 'W')
8704 INSERT_OPERAND (FD
, *ip
, regno
);
8709 INSERT_OPERAND (FS
, *ip
, regno
);
8712 /* This is like 'Z', but also needs to fix the MDMX
8713 vector/scalar select bits. Note that the
8714 scalar immediate case is handled above. */
8717 int is_qh
= (ip
->insn_opcode
& (1 << OP_SH_VSEL
));
8718 int max_el
= (is_qh
? 3 : 7);
8720 my_getExpression(&imm_expr
, s
);
8721 check_absolute_expr (ip
, &imm_expr
);
8723 if (imm_expr
.X_add_number
> max_el
)
8724 as_bad(_("Bad element selector %ld"),
8725 (long) imm_expr
.X_add_number
);
8726 imm_expr
.X_add_number
&= max_el
;
8727 ip
->insn_opcode
|= (imm_expr
.X_add_number
8730 imm_expr
.X_op
= O_absent
;
8732 as_warn(_("Expecting ']' found '%s'"), s
);
8738 if (ip
->insn_opcode
& (OP_MASK_VSEL
<< OP_SH_VSEL
))
8739 ip
->insn_opcode
|= (MDMX_FMTSEL_VEC_QH
8742 ip
->insn_opcode
|= (MDMX_FMTSEL_VEC_OB
<<
8749 INSERT_OPERAND (FT
, *ip
, regno
);
8752 INSERT_OPERAND (FR
, *ip
, regno
);
8762 INSERT_OPERAND (FS
, *ip
, lastregno
);
8765 INSERT_OPERAND (FT
, *ip
, lastregno
);
8771 my_getExpression (&imm_expr
, s
);
8772 if (imm_expr
.X_op
!= O_big
8773 && imm_expr
.X_op
!= O_constant
)
8774 insn_error
= _("absolute expression required");
8775 if (HAVE_32BIT_GPRS
)
8776 normalize_constant_expr (&imm_expr
);
8781 my_getExpression (&offset_expr
, s
);
8782 normalize_address_expr (&offset_expr
);
8783 *imm_reloc
= BFD_RELOC_32
;
8796 unsigned char temp
[8];
8798 unsigned int length
;
8803 /* These only appear as the last operand in an
8804 instruction, and every instruction that accepts
8805 them in any variant accepts them in all variants.
8806 This means we don't have to worry about backing out
8807 any changes if the instruction does not match.
8809 The difference between them is the size of the
8810 floating point constant and where it goes. For 'F'
8811 and 'L' the constant is 64 bits; for 'f' and 'l' it
8812 is 32 bits. Where the constant is placed is based
8813 on how the MIPS assembler does things:
8816 f -- immediate value
8819 The .lit4 and .lit8 sections are only used if
8820 permitted by the -G argument.
8822 The code below needs to know whether the target register
8823 is 32 or 64 bits wide. It relies on the fact 'f' and
8824 'F' are used with GPR-based instructions and 'l' and
8825 'L' are used with FPR-based instructions. */
8827 f64
= *args
== 'F' || *args
== 'L';
8828 using_gprs
= *args
== 'F' || *args
== 'f';
8830 save_in
= input_line_pointer
;
8831 input_line_pointer
= s
;
8832 err
= md_atof (f64
? 'd' : 'f', (char *) temp
, &len
);
8834 s
= input_line_pointer
;
8835 input_line_pointer
= save_in
;
8836 if (err
!= NULL
&& *err
!= '\0')
8838 as_bad (_("Bad floating point constant: %s"), err
);
8839 memset (temp
, '\0', sizeof temp
);
8840 length
= f64
? 8 : 4;
8843 assert (length
== (unsigned) (f64
? 8 : 4));
8847 && (g_switch_value
< 4
8848 || (temp
[0] == 0 && temp
[1] == 0)
8849 || (temp
[2] == 0 && temp
[3] == 0))))
8851 imm_expr
.X_op
= O_constant
;
8852 if (! target_big_endian
)
8853 imm_expr
.X_add_number
= bfd_getl32 (temp
);
8855 imm_expr
.X_add_number
= bfd_getb32 (temp
);
8858 && ! mips_disable_float_construction
8859 /* Constants can only be constructed in GPRs and
8860 copied to FPRs if the GPRs are at least as wide
8861 as the FPRs. Force the constant into memory if
8862 we are using 64-bit FPRs but the GPRs are only
8865 || ! (HAVE_64BIT_FPRS
&& HAVE_32BIT_GPRS
))
8866 && ((temp
[0] == 0 && temp
[1] == 0)
8867 || (temp
[2] == 0 && temp
[3] == 0))
8868 && ((temp
[4] == 0 && temp
[5] == 0)
8869 || (temp
[6] == 0 && temp
[7] == 0)))
8871 /* The value is simple enough to load with a couple of
8872 instructions. If using 32-bit registers, set
8873 imm_expr to the high order 32 bits and offset_expr to
8874 the low order 32 bits. Otherwise, set imm_expr to
8875 the entire 64 bit constant. */
8876 if (using_gprs
? HAVE_32BIT_GPRS
: HAVE_32BIT_FPRS
)
8878 imm_expr
.X_op
= O_constant
;
8879 offset_expr
.X_op
= O_constant
;
8880 if (! target_big_endian
)
8882 imm_expr
.X_add_number
= bfd_getl32 (temp
+ 4);
8883 offset_expr
.X_add_number
= bfd_getl32 (temp
);
8887 imm_expr
.X_add_number
= bfd_getb32 (temp
);
8888 offset_expr
.X_add_number
= bfd_getb32 (temp
+ 4);
8890 if (offset_expr
.X_add_number
== 0)
8891 offset_expr
.X_op
= O_absent
;
8893 else if (sizeof (imm_expr
.X_add_number
) > 4)
8895 imm_expr
.X_op
= O_constant
;
8896 if (! target_big_endian
)
8897 imm_expr
.X_add_number
= bfd_getl64 (temp
);
8899 imm_expr
.X_add_number
= bfd_getb64 (temp
);
8903 imm_expr
.X_op
= O_big
;
8904 imm_expr
.X_add_number
= 4;
8905 if (! target_big_endian
)
8907 generic_bignum
[0] = bfd_getl16 (temp
);
8908 generic_bignum
[1] = bfd_getl16 (temp
+ 2);
8909 generic_bignum
[2] = bfd_getl16 (temp
+ 4);
8910 generic_bignum
[3] = bfd_getl16 (temp
+ 6);
8914 generic_bignum
[0] = bfd_getb16 (temp
+ 6);
8915 generic_bignum
[1] = bfd_getb16 (temp
+ 4);
8916 generic_bignum
[2] = bfd_getb16 (temp
+ 2);
8917 generic_bignum
[3] = bfd_getb16 (temp
);
8923 const char *newname
;
8926 /* Switch to the right section. */
8928 subseg
= now_subseg
;
8931 default: /* unused default case avoids warnings. */
8933 newname
= RDATA_SECTION_NAME
;
8934 if (g_switch_value
>= 8)
8938 newname
= RDATA_SECTION_NAME
;
8941 assert (g_switch_value
>= 4);
8945 new_seg
= subseg_new (newname
, (subsegT
) 0);
8946 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
8947 bfd_set_section_flags (stdoutput
, new_seg
,
8952 frag_align (*args
== 'l' ? 2 : 3, 0, 0);
8953 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
8954 && strcmp (TARGET_OS
, "elf") != 0)
8955 record_alignment (new_seg
, 4);
8957 record_alignment (new_seg
, *args
== 'l' ? 2 : 3);
8959 as_bad (_("Can't use floating point insn in this section"));
8961 /* Set the argument to the current address in the
8963 offset_expr
.X_op
= O_symbol
;
8964 offset_expr
.X_add_symbol
=
8965 symbol_new ("L0\001", now_seg
,
8966 (valueT
) frag_now_fix (), frag_now
);
8967 offset_expr
.X_add_number
= 0;
8969 /* Put the floating point number into the section. */
8970 p
= frag_more ((int) length
);
8971 memcpy (p
, temp
, length
);
8973 /* Switch back to the original section. */
8974 subseg_set (seg
, subseg
);
8979 case 'i': /* 16 bit unsigned immediate */
8980 case 'j': /* 16 bit signed immediate */
8981 *imm_reloc
= BFD_RELOC_LO16
;
8982 if (my_getSmallExpression (&imm_expr
, imm_reloc
, s
) == 0)
8985 offsetT minval
, maxval
;
8987 more
= (insn
+ 1 < &mips_opcodes
[NUMOPCODES
]
8988 && strcmp (insn
->name
, insn
[1].name
) == 0);
8990 /* If the expression was written as an unsigned number,
8991 only treat it as signed if there are no more
8995 && sizeof (imm_expr
.X_add_number
) <= 4
8996 && imm_expr
.X_op
== O_constant
8997 && imm_expr
.X_add_number
< 0
8998 && imm_expr
.X_unsigned
9002 /* For compatibility with older assemblers, we accept
9003 0x8000-0xffff as signed 16-bit numbers when only
9004 signed numbers are allowed. */
9006 minval
= 0, maxval
= 0xffff;
9008 minval
= -0x8000, maxval
= 0x7fff;
9010 minval
= -0x8000, maxval
= 0xffff;
9012 if (imm_expr
.X_op
!= O_constant
9013 || imm_expr
.X_add_number
< minval
9014 || imm_expr
.X_add_number
> maxval
)
9018 if (imm_expr
.X_op
== O_constant
9019 || imm_expr
.X_op
== O_big
)
9020 as_bad (_("expression out of range"));
9026 case 'o': /* 16 bit offset */
9027 /* Check whether there is only a single bracketed expression
9028 left. If so, it must be the base register and the
9029 constant must be zero. */
9030 if (*s
== '(' && strchr (s
+ 1, '(') == 0)
9032 offset_expr
.X_op
= O_constant
;
9033 offset_expr
.X_add_number
= 0;
9037 /* If this value won't fit into a 16 bit offset, then go
9038 find a macro that will generate the 32 bit offset
9040 if (my_getSmallExpression (&offset_expr
, offset_reloc
, s
) == 0
9041 && (offset_expr
.X_op
!= O_constant
9042 || offset_expr
.X_add_number
>= 0x8000
9043 || offset_expr
.X_add_number
< -0x8000))
9049 case 'p': /* pc relative offset */
9050 *offset_reloc
= BFD_RELOC_16_PCREL_S2
;
9051 my_getExpression (&offset_expr
, s
);
9055 case 'u': /* upper 16 bits */
9056 if (my_getSmallExpression (&imm_expr
, imm_reloc
, s
) == 0
9057 && imm_expr
.X_op
== O_constant
9058 && (imm_expr
.X_add_number
< 0
9059 || imm_expr
.X_add_number
>= 0x10000))
9060 as_bad (_("lui expression not in range 0..65535"));
9064 case 'a': /* 26 bit address */
9065 my_getExpression (&offset_expr
, s
);
9067 *offset_reloc
= BFD_RELOC_MIPS_JMP
;
9070 case 'N': /* 3 bit branch condition code */
9071 case 'M': /* 3 bit compare condition code */
9072 if (strncmp (s
, "$fcc", 4) != 0)
9082 while (ISDIGIT (*s
));
9084 as_bad (_("Invalid condition code register $fcc%d"), regno
);
9085 if ((strcmp(str
+ strlen(str
) - 3, ".ps") == 0
9086 || strcmp(str
+ strlen(str
) - 5, "any2f") == 0
9087 || strcmp(str
+ strlen(str
) - 5, "any2t") == 0)
9088 && (regno
& 1) != 0)
9089 as_warn(_("Condition code register should be even for %s, was %d"),
9091 if ((strcmp(str
+ strlen(str
) - 5, "any4f") == 0
9092 || strcmp(str
+ strlen(str
) - 5, "any4t") == 0)
9093 && (regno
& 3) != 0)
9094 as_warn(_("Condition code register should be 0 or 4 for %s, was %d"),
9097 INSERT_OPERAND (BCC
, *ip
, regno
);
9099 INSERT_OPERAND (CCC
, *ip
, regno
);
9103 if (s
[0] == '0' && (s
[1] == 'x' || s
[1] == 'X'))
9114 while (ISDIGIT (*s
));
9117 c
= 8; /* Invalid sel value. */
9120 as_bad (_("invalid coprocessor sub-selection value (0-7)"));
9121 ip
->insn_opcode
|= c
;
9125 /* Must be at least one digit. */
9126 my_getExpression (&imm_expr
, s
);
9127 check_absolute_expr (ip
, &imm_expr
);
9129 if ((unsigned long) imm_expr
.X_add_number
9130 > (unsigned long) OP_MASK_VECBYTE
)
9132 as_bad (_("bad byte vector index (%ld)"),
9133 (long) imm_expr
.X_add_number
);
9134 imm_expr
.X_add_number
= 0;
9137 INSERT_OPERAND (VECBYTE
, *ip
, imm_expr
.X_add_number
);
9138 imm_expr
.X_op
= O_absent
;
9143 my_getExpression (&imm_expr
, s
);
9144 check_absolute_expr (ip
, &imm_expr
);
9146 if ((unsigned long) imm_expr
.X_add_number
9147 > (unsigned long) OP_MASK_VECALIGN
)
9149 as_bad (_("bad byte vector index (%ld)"),
9150 (long) imm_expr
.X_add_number
);
9151 imm_expr
.X_add_number
= 0;
9154 INSERT_OPERAND (VECALIGN
, *ip
, imm_expr
.X_add_number
);
9155 imm_expr
.X_op
= O_absent
;
9160 as_bad (_("bad char = '%c'\n"), *args
);
9165 /* Args don't match. */
9166 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
9167 !strcmp (insn
->name
, insn
[1].name
))
9171 insn_error
= _("illegal operands");
9176 insn_error
= _("illegal operands");
9181 /* This routine assembles an instruction into its binary format when
9182 assembling for the mips16. As a side effect, it sets one of the
9183 global variables imm_reloc or offset_reloc to the type of
9184 relocation to do if one of the operands is an address expression.
9185 It also sets mips16_small and mips16_ext if the user explicitly
9186 requested a small or extended instruction. */
9189 mips16_ip (char *str
, struct mips_cl_insn
*ip
)
9193 struct mips_opcode
*insn
;
9196 unsigned int lastregno
= 0;
9202 mips16_small
= FALSE
;
9205 for (s
= str
; ISLOWER (*s
); ++s
)
9217 if (s
[1] == 't' && s
[2] == ' ')
9220 mips16_small
= TRUE
;
9224 else if (s
[1] == 'e' && s
[2] == ' ')
9233 insn_error
= _("unknown opcode");
9237 if (mips_opts
.noautoextend
&& ! mips16_ext
)
9238 mips16_small
= TRUE
;
9240 if ((insn
= (struct mips_opcode
*) hash_find (mips16_op_hash
, str
)) == NULL
)
9242 insn_error
= _("unrecognized opcode");
9249 assert (strcmp (insn
->name
, str
) == 0);
9251 create_insn (ip
, insn
);
9252 imm_expr
.X_op
= O_absent
;
9253 imm_reloc
[0] = BFD_RELOC_UNUSED
;
9254 imm_reloc
[1] = BFD_RELOC_UNUSED
;
9255 imm_reloc
[2] = BFD_RELOC_UNUSED
;
9256 imm2_expr
.X_op
= O_absent
;
9257 offset_expr
.X_op
= O_absent
;
9258 offset_reloc
[0] = BFD_RELOC_UNUSED
;
9259 offset_reloc
[1] = BFD_RELOC_UNUSED
;
9260 offset_reloc
[2] = BFD_RELOC_UNUSED
;
9261 for (args
= insn
->args
; 1; ++args
)
9268 /* In this switch statement we call break if we did not find
9269 a match, continue if we did find a match, or return if we
9278 /* Stuff the immediate value in now, if we can. */
9279 if (imm_expr
.X_op
== O_constant
9280 && *imm_reloc
> BFD_RELOC_UNUSED
9281 && insn
->pinfo
!= INSN_MACRO
)
9285 switch (*offset_reloc
)
9287 case BFD_RELOC_MIPS16_HI16_S
:
9288 tmp
= (imm_expr
.X_add_number
+ 0x8000) >> 16;
9291 case BFD_RELOC_MIPS16_HI16
:
9292 tmp
= imm_expr
.X_add_number
>> 16;
9295 case BFD_RELOC_MIPS16_LO16
:
9296 tmp
= ((imm_expr
.X_add_number
+ 0x8000) & 0xffff)
9300 case BFD_RELOC_UNUSED
:
9301 tmp
= imm_expr
.X_add_number
;
9307 *offset_reloc
= BFD_RELOC_UNUSED
;
9309 mips16_immed (NULL
, 0, *imm_reloc
- BFD_RELOC_UNUSED
,
9310 tmp
, TRUE
, mips16_small
,
9311 mips16_ext
, &ip
->insn_opcode
,
9312 &ip
->use_extend
, &ip
->extend
);
9313 imm_expr
.X_op
= O_absent
;
9314 *imm_reloc
= BFD_RELOC_UNUSED
;
9328 MIPS16_INSERT_OPERAND (RX
, *ip
, lastregno
);
9331 MIPS16_INSERT_OPERAND (RY
, *ip
, lastregno
);
9347 MIPS16_INSERT_OPERAND (RX
, *ip
, lastregno
);
9349 MIPS16_INSERT_OPERAND (RY
, *ip
, lastregno
);
9376 while (ISDIGIT (*s
));
9379 as_bad (_("invalid register number (%d)"), regno
);
9385 if (s
[1] == 'r' && s
[2] == 'a')
9390 else if (s
[1] == 'f' && s
[2] == 'p')
9395 else if (s
[1] == 's' && s
[2] == 'p')
9400 else if (s
[1] == 'g' && s
[2] == 'p')
9405 else if (s
[1] == 'a' && s
[2] == 't')
9410 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '0')
9415 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '1')
9420 else if (s
[1] == 'z' && s
[2] == 'e' && s
[3] == 'r' && s
[4] == 'o')
9433 if (c
== 'v' || c
== 'w')
9435 regno
= mips16_to_32_reg_map
[lastregno
];
9449 regno
= mips32_to_16_reg_map
[regno
];
9454 regno
= ILLEGAL_REG
;
9459 regno
= ILLEGAL_REG
;
9464 regno
= ILLEGAL_REG
;
9469 if (regno
== AT
&& ! mips_opts
.noat
)
9470 as_warn (_("used $at without \".set noat\""));
9477 if (regno
== ILLEGAL_REG
)
9484 MIPS16_INSERT_OPERAND (RX
, *ip
, regno
);
9488 MIPS16_INSERT_OPERAND (RY
, *ip
, regno
);
9491 MIPS16_INSERT_OPERAND (RZ
, *ip
, regno
);
9494 MIPS16_INSERT_OPERAND (MOVE32Z
, *ip
, regno
);
9500 MIPS16_INSERT_OPERAND (REGR32
, *ip
, regno
);
9503 regno
= ((regno
& 7) << 2) | ((regno
& 0x18) >> 3);
9504 MIPS16_INSERT_OPERAND (REG32R
, *ip
, regno
);
9514 if (strncmp (s
, "$pc", 3) == 0)
9531 i
= my_getSmallExpression (&imm_expr
, imm_reloc
, s
);
9534 if (imm_expr
.X_op
!= O_constant
)
9537 ip
->use_extend
= TRUE
;
9542 /* We need to relax this instruction. */
9543 *offset_reloc
= *imm_reloc
;
9544 *imm_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
9549 *imm_reloc
= BFD_RELOC_UNUSED
;
9557 my_getExpression (&imm_expr
, s
);
9558 if (imm_expr
.X_op
== O_register
)
9560 /* What we thought was an expression turned out to
9563 if (s
[0] == '(' && args
[1] == '(')
9565 /* It looks like the expression was omitted
9566 before a register indirection, which means
9567 that the expression is implicitly zero. We
9568 still set up imm_expr, so that we handle
9569 explicit extensions correctly. */
9570 imm_expr
.X_op
= O_constant
;
9571 imm_expr
.X_add_number
= 0;
9572 *imm_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
9579 /* We need to relax this instruction. */
9580 *imm_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
9589 /* We use offset_reloc rather than imm_reloc for the PC
9590 relative operands. This lets macros with both
9591 immediate and address operands work correctly. */
9592 my_getExpression (&offset_expr
, s
);
9594 if (offset_expr
.X_op
== O_register
)
9597 /* We need to relax this instruction. */
9598 *offset_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
9602 case '6': /* break code */
9603 my_getExpression (&imm_expr
, s
);
9604 check_absolute_expr (ip
, &imm_expr
);
9605 if ((unsigned long) imm_expr
.X_add_number
> 63)
9606 as_warn (_("Invalid value for `%s' (%lu)"),
9608 (unsigned long) imm_expr
.X_add_number
);
9609 MIPS16_INSERT_OPERAND (IMM6
, *ip
, imm_expr
.X_add_number
);
9610 imm_expr
.X_op
= O_absent
;
9614 case 'a': /* 26 bit address */
9615 my_getExpression (&offset_expr
, s
);
9617 *offset_reloc
= BFD_RELOC_MIPS16_JMP
;
9618 ip
->insn_opcode
<<= 16;
9621 case 'l': /* register list for entry macro */
9622 case 'L': /* register list for exit macro */
9632 int freg
, reg1
, reg2
;
9634 while (*s
== ' ' || *s
== ',')
9638 as_bad (_("can't parse register list"));
9650 while (ISDIGIT (*s
))
9672 as_bad (_("invalid register list"));
9677 while (ISDIGIT (*s
))
9684 if (freg
&& reg1
== 0 && reg2
== 0 && c
== 'L')
9689 else if (freg
&& reg1
== 0 && reg2
== 1 && c
== 'L')
9694 else if (reg1
== 4 && reg2
>= 4 && reg2
<= 7 && c
!= 'L')
9695 mask
|= (reg2
- 3) << 3;
9696 else if (reg1
== 16 && reg2
>= 16 && reg2
<= 17)
9697 mask
|= (reg2
- 15) << 1;
9698 else if (reg1
== RA
&& reg2
== RA
)
9702 as_bad (_("invalid register list"));
9706 /* The mask is filled in in the opcode table for the
9707 benefit of the disassembler. We remove it before
9708 applying the actual mask. */
9709 ip
->insn_opcode
&= ~ ((7 << 3) << MIPS16OP_SH_IMM6
);
9710 ip
->insn_opcode
|= mask
<< MIPS16OP_SH_IMM6
;
9714 case 'e': /* extend code */
9715 my_getExpression (&imm_expr
, s
);
9716 check_absolute_expr (ip
, &imm_expr
);
9717 if ((unsigned long) imm_expr
.X_add_number
> 0x7ff)
9719 as_warn (_("Invalid value for `%s' (%lu)"),
9721 (unsigned long) imm_expr
.X_add_number
);
9722 imm_expr
.X_add_number
&= 0x7ff;
9724 ip
->insn_opcode
|= imm_expr
.X_add_number
;
9725 imm_expr
.X_op
= O_absent
;
9735 /* Args don't match. */
9736 if (insn
+ 1 < &mips16_opcodes
[bfd_mips16_num_opcodes
] &&
9737 strcmp (insn
->name
, insn
[1].name
) == 0)
9744 insn_error
= _("illegal operands");
9750 /* This structure holds information we know about a mips16 immediate
9753 struct mips16_immed_operand
9755 /* The type code used in the argument string in the opcode table. */
9757 /* The number of bits in the short form of the opcode. */
9759 /* The number of bits in the extended form of the opcode. */
9761 /* The amount by which the short form is shifted when it is used;
9762 for example, the sw instruction has a shift count of 2. */
9764 /* The amount by which the short form is shifted when it is stored
9765 into the instruction code. */
9767 /* Non-zero if the short form is unsigned. */
9769 /* Non-zero if the extended form is unsigned. */
9771 /* Non-zero if the value is PC relative. */
9775 /* The mips16 immediate operand types. */
9777 static const struct mips16_immed_operand mips16_immed_operands
[] =
9779 { '<', 3, 5, 0, MIPS16OP_SH_RZ
, 1, 1, 0 },
9780 { '>', 3, 5, 0, MIPS16OP_SH_RX
, 1, 1, 0 },
9781 { '[', 3, 6, 0, MIPS16OP_SH_RZ
, 1, 1, 0 },
9782 { ']', 3, 6, 0, MIPS16OP_SH_RX
, 1, 1, 0 },
9783 { '4', 4, 15, 0, MIPS16OP_SH_IMM4
, 0, 0, 0 },
9784 { '5', 5, 16, 0, MIPS16OP_SH_IMM5
, 1, 0, 0 },
9785 { 'H', 5, 16, 1, MIPS16OP_SH_IMM5
, 1, 0, 0 },
9786 { 'W', 5, 16, 2, MIPS16OP_SH_IMM5
, 1, 0, 0 },
9787 { 'D', 5, 16, 3, MIPS16OP_SH_IMM5
, 1, 0, 0 },
9788 { 'j', 5, 16, 0, MIPS16OP_SH_IMM5
, 0, 0, 0 },
9789 { '8', 8, 16, 0, MIPS16OP_SH_IMM8
, 1, 0, 0 },
9790 { 'V', 8, 16, 2, MIPS16OP_SH_IMM8
, 1, 0, 0 },
9791 { 'C', 8, 16, 3, MIPS16OP_SH_IMM8
, 1, 0, 0 },
9792 { 'U', 8, 16, 0, MIPS16OP_SH_IMM8
, 1, 1, 0 },
9793 { 'k', 8, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 0 },
9794 { 'K', 8, 16, 3, MIPS16OP_SH_IMM8
, 0, 0, 0 },
9795 { 'p', 8, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 1 },
9796 { 'q', 11, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 1 },
9797 { 'A', 8, 16, 2, MIPS16OP_SH_IMM8
, 1, 0, 1 },
9798 { 'B', 5, 16, 3, MIPS16OP_SH_IMM5
, 1, 0, 1 },
9799 { 'E', 5, 16, 2, MIPS16OP_SH_IMM5
, 1, 0, 1 }
9802 #define MIPS16_NUM_IMMED \
9803 (sizeof mips16_immed_operands / sizeof mips16_immed_operands[0])
9805 /* Handle a mips16 instruction with an immediate value. This or's the
9806 small immediate value into *INSN. It sets *USE_EXTEND to indicate
9807 whether an extended value is needed; if one is needed, it sets
9808 *EXTEND to the value. The argument type is TYPE. The value is VAL.
9809 If SMALL is true, an unextended opcode was explicitly requested.
9810 If EXT is true, an extended opcode was explicitly requested. If
9811 WARN is true, warn if EXT does not match reality. */
9814 mips16_immed (char *file
, unsigned int line
, int type
, offsetT val
,
9815 bfd_boolean warn
, bfd_boolean small
, bfd_boolean ext
,
9816 unsigned long *insn
, bfd_boolean
*use_extend
,
9817 unsigned short *extend
)
9819 register const struct mips16_immed_operand
*op
;
9820 int mintiny
, maxtiny
;
9821 bfd_boolean needext
;
9823 op
= mips16_immed_operands
;
9824 while (op
->type
!= type
)
9827 assert (op
< mips16_immed_operands
+ MIPS16_NUM_IMMED
);
9832 if (type
== '<' || type
== '>' || type
== '[' || type
== ']')
9835 maxtiny
= 1 << op
->nbits
;
9840 maxtiny
= (1 << op
->nbits
) - 1;
9845 mintiny
= - (1 << (op
->nbits
- 1));
9846 maxtiny
= (1 << (op
->nbits
- 1)) - 1;
9849 /* Branch offsets have an implicit 0 in the lowest bit. */
9850 if (type
== 'p' || type
== 'q')
9853 if ((val
& ((1 << op
->shift
) - 1)) != 0
9854 || val
< (mintiny
<< op
->shift
)
9855 || val
> (maxtiny
<< op
->shift
))
9860 if (warn
&& ext
&& ! needext
)
9861 as_warn_where (file
, line
,
9862 _("extended operand requested but not required"));
9863 if (small
&& needext
)
9864 as_bad_where (file
, line
, _("invalid unextended operand value"));
9866 if (small
|| (! ext
&& ! needext
))
9870 *use_extend
= FALSE
;
9871 insnval
= ((val
>> op
->shift
) & ((1 << op
->nbits
) - 1));
9872 insnval
<<= op
->op_shift
;
9877 long minext
, maxext
;
9883 maxext
= (1 << op
->extbits
) - 1;
9887 minext
= - (1 << (op
->extbits
- 1));
9888 maxext
= (1 << (op
->extbits
- 1)) - 1;
9890 if (val
< minext
|| val
> maxext
)
9891 as_bad_where (file
, line
,
9892 _("operand value out of range for instruction"));
9895 if (op
->extbits
== 16)
9897 extval
= ((val
>> 11) & 0x1f) | (val
& 0x7e0);
9900 else if (op
->extbits
== 15)
9902 extval
= ((val
>> 11) & 0xf) | (val
& 0x7f0);
9907 extval
= ((val
& 0x1f) << 6) | (val
& 0x20);
9911 *extend
= (unsigned short) extval
;
9916 struct percent_op_match
9919 bfd_reloc_code_real_type reloc
;
9922 static const struct percent_op_match mips_percent_op
[] =
9924 {"%lo", BFD_RELOC_LO16
},
9926 {"%call_hi", BFD_RELOC_MIPS_CALL_HI16
},
9927 {"%call_lo", BFD_RELOC_MIPS_CALL_LO16
},
9928 {"%call16", BFD_RELOC_MIPS_CALL16
},
9929 {"%got_disp", BFD_RELOC_MIPS_GOT_DISP
},
9930 {"%got_page", BFD_RELOC_MIPS_GOT_PAGE
},
9931 {"%got_ofst", BFD_RELOC_MIPS_GOT_OFST
},
9932 {"%got_hi", BFD_RELOC_MIPS_GOT_HI16
},
9933 {"%got_lo", BFD_RELOC_MIPS_GOT_LO16
},
9934 {"%got", BFD_RELOC_MIPS_GOT16
},
9935 {"%gp_rel", BFD_RELOC_GPREL16
},
9936 {"%half", BFD_RELOC_16
},
9937 {"%highest", BFD_RELOC_MIPS_HIGHEST
},
9938 {"%higher", BFD_RELOC_MIPS_HIGHER
},
9939 {"%neg", BFD_RELOC_MIPS_SUB
},
9940 {"%tlsgd", BFD_RELOC_MIPS_TLS_GD
},
9941 {"%tlsldm", BFD_RELOC_MIPS_TLS_LDM
},
9942 {"%dtprel_hi", BFD_RELOC_MIPS_TLS_DTPREL_HI16
},
9943 {"%dtprel_lo", BFD_RELOC_MIPS_TLS_DTPREL_LO16
},
9944 {"%tprel_hi", BFD_RELOC_MIPS_TLS_TPREL_HI16
},
9945 {"%tprel_lo", BFD_RELOC_MIPS_TLS_TPREL_LO16
},
9946 {"%gottprel", BFD_RELOC_MIPS_TLS_GOTTPREL
},
9948 {"%hi", BFD_RELOC_HI16_S
}
9951 static const struct percent_op_match mips16_percent_op
[] =
9953 {"%lo", BFD_RELOC_MIPS16_LO16
},
9954 {"%gprel", BFD_RELOC_MIPS16_GPREL
},
9955 {"%hi", BFD_RELOC_MIPS16_HI16_S
}
9959 /* Return true if *STR points to a relocation operator. When returning true,
9960 move *STR over the operator and store its relocation code in *RELOC.
9961 Leave both *STR and *RELOC alone when returning false. */
9964 parse_relocation (char **str
, bfd_reloc_code_real_type
*reloc
)
9966 const struct percent_op_match
*percent_op
;
9969 if (mips_opts
.mips16
)
9971 percent_op
= mips16_percent_op
;
9972 limit
= ARRAY_SIZE (mips16_percent_op
);
9976 percent_op
= mips_percent_op
;
9977 limit
= ARRAY_SIZE (mips_percent_op
);
9980 for (i
= 0; i
< limit
; i
++)
9981 if (strncasecmp (*str
, percent_op
[i
].str
, strlen (percent_op
[i
].str
)) == 0)
9983 int len
= strlen (percent_op
[i
].str
);
9985 if (!ISSPACE ((*str
)[len
]) && (*str
)[len
] != '(')
9988 *str
+= strlen (percent_op
[i
].str
);
9989 *reloc
= percent_op
[i
].reloc
;
9991 /* Check whether the output BFD supports this relocation.
9992 If not, issue an error and fall back on something safe. */
9993 if (!bfd_reloc_type_lookup (stdoutput
, percent_op
[i
].reloc
))
9995 as_bad ("relocation %s isn't supported by the current ABI",
9997 *reloc
= BFD_RELOC_UNUSED
;
10005 /* Parse string STR as a 16-bit relocatable operand. Store the
10006 expression in *EP and the relocations in the array starting
10007 at RELOC. Return the number of relocation operators used.
10009 On exit, EXPR_END points to the first character after the expression. */
10012 my_getSmallExpression (expressionS
*ep
, bfd_reloc_code_real_type
*reloc
,
10015 bfd_reloc_code_real_type reversed_reloc
[3];
10016 size_t reloc_index
, i
;
10017 int crux_depth
, str_depth
;
10020 /* Search for the start of the main expression, recoding relocations
10021 in REVERSED_RELOC. End the loop with CRUX pointing to the start
10022 of the main expression and with CRUX_DEPTH containing the number
10023 of open brackets at that point. */
10030 crux_depth
= str_depth
;
10032 /* Skip over whitespace and brackets, keeping count of the number
10034 while (*str
== ' ' || *str
== '\t' || *str
== '(')
10039 && reloc_index
< (HAVE_NEWABI
? 3 : 1)
10040 && parse_relocation (&str
, &reversed_reloc
[reloc_index
]));
10042 my_getExpression (ep
, crux
);
10045 /* Match every open bracket. */
10046 while (crux_depth
> 0 && (*str
== ')' || *str
== ' ' || *str
== '\t'))
10050 if (crux_depth
> 0)
10051 as_bad ("unclosed '('");
10055 if (reloc_index
!= 0)
10057 prev_reloc_op_frag
= frag_now
;
10058 for (i
= 0; i
< reloc_index
; i
++)
10059 reloc
[i
] = reversed_reloc
[reloc_index
- 1 - i
];
10062 return reloc_index
;
10066 my_getExpression (expressionS
*ep
, char *str
)
10071 save_in
= input_line_pointer
;
10072 input_line_pointer
= str
;
10074 expr_end
= input_line_pointer
;
10075 input_line_pointer
= save_in
;
10077 /* If we are in mips16 mode, and this is an expression based on `.',
10078 then we bump the value of the symbol by 1 since that is how other
10079 text symbols are handled. We don't bother to handle complex
10080 expressions, just `.' plus or minus a constant. */
10081 if (mips_opts
.mips16
10082 && ep
->X_op
== O_symbol
10083 && strcmp (S_GET_NAME (ep
->X_add_symbol
), FAKE_LABEL_NAME
) == 0
10084 && S_GET_SEGMENT (ep
->X_add_symbol
) == now_seg
10085 && symbol_get_frag (ep
->X_add_symbol
) == frag_now
10086 && symbol_constant_p (ep
->X_add_symbol
)
10087 && (val
= S_GET_VALUE (ep
->X_add_symbol
)) == frag_now_fix ())
10088 S_SET_VALUE (ep
->X_add_symbol
, val
+ 1);
10091 /* Turn a string in input_line_pointer into a floating point constant
10092 of type TYPE, and store the appropriate bytes in *LITP. The number
10093 of LITTLENUMS emitted is stored in *SIZEP. An error message is
10094 returned, or NULL on OK. */
10097 md_atof (int type
, char *litP
, int *sizeP
)
10100 LITTLENUM_TYPE words
[4];
10116 return _("bad call to md_atof");
10119 t
= atof_ieee (input_line_pointer
, type
, words
);
10121 input_line_pointer
= t
;
10125 if (! target_big_endian
)
10127 for (i
= prec
- 1; i
>= 0; i
--)
10129 md_number_to_chars (litP
, words
[i
], 2);
10135 for (i
= 0; i
< prec
; i
++)
10137 md_number_to_chars (litP
, words
[i
], 2);
10146 md_number_to_chars (char *buf
, valueT val
, int n
)
10148 if (target_big_endian
)
10149 number_to_chars_bigendian (buf
, val
, n
);
10151 number_to_chars_littleendian (buf
, val
, n
);
10155 static int support_64bit_objects(void)
10157 const char **list
, **l
;
10160 list
= bfd_target_list ();
10161 for (l
= list
; *l
!= NULL
; l
++)
10163 /* This is traditional mips */
10164 if (strcmp (*l
, "elf64-tradbigmips") == 0
10165 || strcmp (*l
, "elf64-tradlittlemips") == 0)
10167 if (strcmp (*l
, "elf64-bigmips") == 0
10168 || strcmp (*l
, "elf64-littlemips") == 0)
10171 yes
= (*l
!= NULL
);
10175 #endif /* OBJ_ELF */
10177 const char *md_shortopts
= "O::g::G:";
10179 struct option md_longopts
[] =
10181 /* Options which specify architecture. */
10182 #define OPTION_ARCH_BASE (OPTION_MD_BASE)
10183 #define OPTION_MARCH (OPTION_ARCH_BASE + 0)
10184 {"march", required_argument
, NULL
, OPTION_MARCH
},
10185 #define OPTION_MTUNE (OPTION_ARCH_BASE + 1)
10186 {"mtune", required_argument
, NULL
, OPTION_MTUNE
},
10187 #define OPTION_MIPS1 (OPTION_ARCH_BASE + 2)
10188 {"mips0", no_argument
, NULL
, OPTION_MIPS1
},
10189 {"mips1", no_argument
, NULL
, OPTION_MIPS1
},
10190 #define OPTION_MIPS2 (OPTION_ARCH_BASE + 3)
10191 {"mips2", no_argument
, NULL
, OPTION_MIPS2
},
10192 #define OPTION_MIPS3 (OPTION_ARCH_BASE + 4)
10193 {"mips3", no_argument
, NULL
, OPTION_MIPS3
},
10194 #define OPTION_MIPS4 (OPTION_ARCH_BASE + 5)
10195 {"mips4", no_argument
, NULL
, OPTION_MIPS4
},
10196 #define OPTION_MIPS5 (OPTION_ARCH_BASE + 6)
10197 {"mips5", no_argument
, NULL
, OPTION_MIPS5
},
10198 #define OPTION_MIPS32 (OPTION_ARCH_BASE + 7)
10199 {"mips32", no_argument
, NULL
, OPTION_MIPS32
},
10200 #define OPTION_MIPS64 (OPTION_ARCH_BASE + 8)
10201 {"mips64", no_argument
, NULL
, OPTION_MIPS64
},
10202 #define OPTION_MIPS32R2 (OPTION_ARCH_BASE + 9)
10203 {"mips32r2", no_argument
, NULL
, OPTION_MIPS32R2
},
10204 #define OPTION_MIPS64R2 (OPTION_ARCH_BASE + 10)
10205 {"mips64r2", no_argument
, NULL
, OPTION_MIPS64R2
},
10207 /* Options which specify Application Specific Extensions (ASEs). */
10208 #define OPTION_ASE_BASE (OPTION_ARCH_BASE + 11)
10209 #define OPTION_MIPS16 (OPTION_ASE_BASE + 0)
10210 {"mips16", no_argument
, NULL
, OPTION_MIPS16
},
10211 #define OPTION_NO_MIPS16 (OPTION_ASE_BASE + 1)
10212 {"no-mips16", no_argument
, NULL
, OPTION_NO_MIPS16
},
10213 #define OPTION_MIPS3D (OPTION_ASE_BASE + 2)
10214 {"mips3d", no_argument
, NULL
, OPTION_MIPS3D
},
10215 #define OPTION_NO_MIPS3D (OPTION_ASE_BASE + 3)
10216 {"no-mips3d", no_argument
, NULL
, OPTION_NO_MIPS3D
},
10217 #define OPTION_MDMX (OPTION_ASE_BASE + 4)
10218 {"mdmx", no_argument
, NULL
, OPTION_MDMX
},
10219 #define OPTION_NO_MDMX (OPTION_ASE_BASE + 5)
10220 {"no-mdmx", no_argument
, NULL
, OPTION_NO_MDMX
},
10221 #define OPTION_DSP (OPTION_ASE_BASE + 6)
10222 {"mdsp", no_argument
, NULL
, OPTION_DSP
},
10223 #define OPTION_NO_DSP (OPTION_ASE_BASE + 7)
10224 {"mno-dsp", no_argument
, NULL
, OPTION_NO_DSP
},
10226 /* Old-style architecture options. Don't add more of these. */
10227 #define OPTION_COMPAT_ARCH_BASE (OPTION_ASE_BASE + 8)
10228 #define OPTION_M4650 (OPTION_COMPAT_ARCH_BASE + 0)
10229 {"m4650", no_argument
, NULL
, OPTION_M4650
},
10230 #define OPTION_NO_M4650 (OPTION_COMPAT_ARCH_BASE + 1)
10231 {"no-m4650", no_argument
, NULL
, OPTION_NO_M4650
},
10232 #define OPTION_M4010 (OPTION_COMPAT_ARCH_BASE + 2)
10233 {"m4010", no_argument
, NULL
, OPTION_M4010
},
10234 #define OPTION_NO_M4010 (OPTION_COMPAT_ARCH_BASE + 3)
10235 {"no-m4010", no_argument
, NULL
, OPTION_NO_M4010
},
10236 #define OPTION_M4100 (OPTION_COMPAT_ARCH_BASE + 4)
10237 {"m4100", no_argument
, NULL
, OPTION_M4100
},
10238 #define OPTION_NO_M4100 (OPTION_COMPAT_ARCH_BASE + 5)
10239 {"no-m4100", no_argument
, NULL
, OPTION_NO_M4100
},
10240 #define OPTION_M3900 (OPTION_COMPAT_ARCH_BASE + 6)
10241 {"m3900", no_argument
, NULL
, OPTION_M3900
},
10242 #define OPTION_NO_M3900 (OPTION_COMPAT_ARCH_BASE + 7)
10243 {"no-m3900", no_argument
, NULL
, OPTION_NO_M3900
},
10245 /* Options which enable bug fixes. */
10246 #define OPTION_FIX_BASE (OPTION_COMPAT_ARCH_BASE + 8)
10247 #define OPTION_M7000_HILO_FIX (OPTION_FIX_BASE + 0)
10248 {"mfix7000", no_argument
, NULL
, OPTION_M7000_HILO_FIX
},
10249 #define OPTION_MNO_7000_HILO_FIX (OPTION_FIX_BASE + 1)
10250 {"no-fix-7000", no_argument
, NULL
, OPTION_MNO_7000_HILO_FIX
},
10251 {"mno-fix7000", no_argument
, NULL
, OPTION_MNO_7000_HILO_FIX
},
10252 #define OPTION_FIX_VR4120 (OPTION_FIX_BASE + 2)
10253 #define OPTION_NO_FIX_VR4120 (OPTION_FIX_BASE + 3)
10254 {"mfix-vr4120", no_argument
, NULL
, OPTION_FIX_VR4120
},
10255 {"mno-fix-vr4120", no_argument
, NULL
, OPTION_NO_FIX_VR4120
},
10256 #define OPTION_FIX_VR4130 (OPTION_FIX_BASE + 4)
10257 #define OPTION_NO_FIX_VR4130 (OPTION_FIX_BASE + 5)
10258 {"mfix-vr4130", no_argument
, NULL
, OPTION_FIX_VR4130
},
10259 {"mno-fix-vr4130", no_argument
, NULL
, OPTION_NO_FIX_VR4130
},
10261 /* Miscellaneous options. */
10262 #define OPTION_MISC_BASE (OPTION_FIX_BASE + 6)
10263 #define OPTION_TRAP (OPTION_MISC_BASE + 0)
10264 {"trap", no_argument
, NULL
, OPTION_TRAP
},
10265 {"no-break", no_argument
, NULL
, OPTION_TRAP
},
10266 #define OPTION_BREAK (OPTION_MISC_BASE + 1)
10267 {"break", no_argument
, NULL
, OPTION_BREAK
},
10268 {"no-trap", no_argument
, NULL
, OPTION_BREAK
},
10269 #define OPTION_EB (OPTION_MISC_BASE + 2)
10270 {"EB", no_argument
, NULL
, OPTION_EB
},
10271 #define OPTION_EL (OPTION_MISC_BASE + 3)
10272 {"EL", no_argument
, NULL
, OPTION_EL
},
10273 #define OPTION_FP32 (OPTION_MISC_BASE + 4)
10274 {"mfp32", no_argument
, NULL
, OPTION_FP32
},
10275 #define OPTION_GP32 (OPTION_MISC_BASE + 5)
10276 {"mgp32", no_argument
, NULL
, OPTION_GP32
},
10277 #define OPTION_CONSTRUCT_FLOATS (OPTION_MISC_BASE + 6)
10278 {"construct-floats", no_argument
, NULL
, OPTION_CONSTRUCT_FLOATS
},
10279 #define OPTION_NO_CONSTRUCT_FLOATS (OPTION_MISC_BASE + 7)
10280 {"no-construct-floats", no_argument
, NULL
, OPTION_NO_CONSTRUCT_FLOATS
},
10281 #define OPTION_FP64 (OPTION_MISC_BASE + 8)
10282 {"mfp64", no_argument
, NULL
, OPTION_FP64
},
10283 #define OPTION_GP64 (OPTION_MISC_BASE + 9)
10284 {"mgp64", no_argument
, NULL
, OPTION_GP64
},
10285 #define OPTION_RELAX_BRANCH (OPTION_MISC_BASE + 10)
10286 #define OPTION_NO_RELAX_BRANCH (OPTION_MISC_BASE + 11)
10287 {"relax-branch", no_argument
, NULL
, OPTION_RELAX_BRANCH
},
10288 {"no-relax-branch", no_argument
, NULL
, OPTION_NO_RELAX_BRANCH
},
10289 #define OPTION_MSHARED (OPTION_MISC_BASE + 12)
10290 #define OPTION_MNO_SHARED (OPTION_MISC_BASE + 13)
10291 {"mshared", no_argument
, NULL
, OPTION_MSHARED
},
10292 {"mno-shared", no_argument
, NULL
, OPTION_MNO_SHARED
},
10293 #define OPTION_MSYM32 (OPTION_MISC_BASE + 14)
10294 #define OPTION_MNO_SYM32 (OPTION_MISC_BASE + 15)
10295 {"msym32", no_argument
, NULL
, OPTION_MSYM32
},
10296 {"mno-sym32", no_argument
, NULL
, OPTION_MNO_SYM32
},
10298 /* ELF-specific options. */
10300 #define OPTION_ELF_BASE (OPTION_MISC_BASE + 16)
10301 #define OPTION_CALL_SHARED (OPTION_ELF_BASE + 0)
10302 {"KPIC", no_argument
, NULL
, OPTION_CALL_SHARED
},
10303 {"call_shared", no_argument
, NULL
, OPTION_CALL_SHARED
},
10304 #define OPTION_NON_SHARED (OPTION_ELF_BASE + 1)
10305 {"non_shared", no_argument
, NULL
, OPTION_NON_SHARED
},
10306 #define OPTION_XGOT (OPTION_ELF_BASE + 2)
10307 {"xgot", no_argument
, NULL
, OPTION_XGOT
},
10308 #define OPTION_MABI (OPTION_ELF_BASE + 3)
10309 {"mabi", required_argument
, NULL
, OPTION_MABI
},
10310 #define OPTION_32 (OPTION_ELF_BASE + 4)
10311 {"32", no_argument
, NULL
, OPTION_32
},
10312 #define OPTION_N32 (OPTION_ELF_BASE + 5)
10313 {"n32", no_argument
, NULL
, OPTION_N32
},
10314 #define OPTION_64 (OPTION_ELF_BASE + 6)
10315 {"64", no_argument
, NULL
, OPTION_64
},
10316 #define OPTION_MDEBUG (OPTION_ELF_BASE + 7)
10317 {"mdebug", no_argument
, NULL
, OPTION_MDEBUG
},
10318 #define OPTION_NO_MDEBUG (OPTION_ELF_BASE + 8)
10319 {"no-mdebug", no_argument
, NULL
, OPTION_NO_MDEBUG
},
10320 #define OPTION_PDR (OPTION_ELF_BASE + 9)
10321 {"mpdr", no_argument
, NULL
, OPTION_PDR
},
10322 #define OPTION_NO_PDR (OPTION_ELF_BASE + 10)
10323 {"mno-pdr", no_argument
, NULL
, OPTION_NO_PDR
},
10324 #endif /* OBJ_ELF */
10326 {NULL
, no_argument
, NULL
, 0}
10328 size_t md_longopts_size
= sizeof (md_longopts
);
10330 /* Set STRING_PTR (either &mips_arch_string or &mips_tune_string) to
10331 NEW_VALUE. Warn if another value was already specified. Note:
10332 we have to defer parsing the -march and -mtune arguments in order
10333 to handle 'from-abi' correctly, since the ABI might be specified
10334 in a later argument. */
10337 mips_set_option_string (const char **string_ptr
, const char *new_value
)
10339 if (*string_ptr
!= 0 && strcasecmp (*string_ptr
, new_value
) != 0)
10340 as_warn (_("A different %s was already specified, is now %s"),
10341 string_ptr
== &mips_arch_string
? "-march" : "-mtune",
10344 *string_ptr
= new_value
;
10348 md_parse_option (int c
, char *arg
)
10352 case OPTION_CONSTRUCT_FLOATS
:
10353 mips_disable_float_construction
= 0;
10356 case OPTION_NO_CONSTRUCT_FLOATS
:
10357 mips_disable_float_construction
= 1;
10369 target_big_endian
= 1;
10373 target_big_endian
= 0;
10377 if (arg
&& arg
[1] == '0')
10387 mips_debug
= atoi (arg
);
10388 /* When the MIPS assembler sees -g or -g2, it does not do
10389 optimizations which limit full symbolic debugging. We take
10390 that to be equivalent to -O0. */
10391 if (mips_debug
== 2)
10396 file_mips_isa
= ISA_MIPS1
;
10400 file_mips_isa
= ISA_MIPS2
;
10404 file_mips_isa
= ISA_MIPS3
;
10408 file_mips_isa
= ISA_MIPS4
;
10412 file_mips_isa
= ISA_MIPS5
;
10415 case OPTION_MIPS32
:
10416 file_mips_isa
= ISA_MIPS32
;
10419 case OPTION_MIPS32R2
:
10420 file_mips_isa
= ISA_MIPS32R2
;
10423 case OPTION_MIPS64R2
:
10424 file_mips_isa
= ISA_MIPS64R2
;
10427 case OPTION_MIPS64
:
10428 file_mips_isa
= ISA_MIPS64
;
10432 mips_set_option_string (&mips_tune_string
, arg
);
10436 mips_set_option_string (&mips_arch_string
, arg
);
10440 mips_set_option_string (&mips_arch_string
, "4650");
10441 mips_set_option_string (&mips_tune_string
, "4650");
10444 case OPTION_NO_M4650
:
10448 mips_set_option_string (&mips_arch_string
, "4010");
10449 mips_set_option_string (&mips_tune_string
, "4010");
10452 case OPTION_NO_M4010
:
10456 mips_set_option_string (&mips_arch_string
, "4100");
10457 mips_set_option_string (&mips_tune_string
, "4100");
10460 case OPTION_NO_M4100
:
10464 mips_set_option_string (&mips_arch_string
, "3900");
10465 mips_set_option_string (&mips_tune_string
, "3900");
10468 case OPTION_NO_M3900
:
10472 mips_opts
.ase_mdmx
= 1;
10475 case OPTION_NO_MDMX
:
10476 mips_opts
.ase_mdmx
= 0;
10480 mips_opts
.ase_dsp
= 1;
10483 case OPTION_NO_DSP
:
10484 mips_opts
.ase_dsp
= 0;
10487 case OPTION_MIPS16
:
10488 mips_opts
.mips16
= 1;
10489 mips_no_prev_insn ();
10492 case OPTION_NO_MIPS16
:
10493 mips_opts
.mips16
= 0;
10494 mips_no_prev_insn ();
10497 case OPTION_MIPS3D
:
10498 mips_opts
.ase_mips3d
= 1;
10501 case OPTION_NO_MIPS3D
:
10502 mips_opts
.ase_mips3d
= 0;
10505 case OPTION_FIX_VR4120
:
10506 mips_fix_vr4120
= 1;
10509 case OPTION_NO_FIX_VR4120
:
10510 mips_fix_vr4120
= 0;
10513 case OPTION_FIX_VR4130
:
10514 mips_fix_vr4130
= 1;
10517 case OPTION_NO_FIX_VR4130
:
10518 mips_fix_vr4130
= 0;
10521 case OPTION_RELAX_BRANCH
:
10522 mips_relax_branch
= 1;
10525 case OPTION_NO_RELAX_BRANCH
:
10526 mips_relax_branch
= 0;
10529 case OPTION_MSHARED
:
10530 mips_in_shared
= TRUE
;
10533 case OPTION_MNO_SHARED
:
10534 mips_in_shared
= FALSE
;
10537 case OPTION_MSYM32
:
10538 mips_opts
.sym32
= TRUE
;
10541 case OPTION_MNO_SYM32
:
10542 mips_opts
.sym32
= FALSE
;
10546 /* When generating ELF code, we permit -KPIC and -call_shared to
10547 select SVR4_PIC, and -non_shared to select no PIC. This is
10548 intended to be compatible with Irix 5. */
10549 case OPTION_CALL_SHARED
:
10550 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
10552 as_bad (_("-call_shared is supported only for ELF format"));
10555 mips_pic
= SVR4_PIC
;
10556 mips_abicalls
= TRUE
;
10557 if (g_switch_seen
&& g_switch_value
!= 0)
10559 as_bad (_("-G may not be used with SVR4 PIC code"));
10562 g_switch_value
= 0;
10565 case OPTION_NON_SHARED
:
10566 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
10568 as_bad (_("-non_shared is supported only for ELF format"));
10572 mips_abicalls
= FALSE
;
10575 /* The -xgot option tells the assembler to use 32 offsets when
10576 accessing the got in SVR4_PIC mode. It is for Irix
10581 #endif /* OBJ_ELF */
10584 g_switch_value
= atoi (arg
);
10586 if (mips_pic
== SVR4_PIC
&& g_switch_value
!= 0)
10588 as_bad (_("-G may not be used with SVR4 PIC code"));
10594 /* The -32, -n32 and -64 options are shortcuts for -mabi=32, -mabi=n32
10597 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
10599 as_bad (_("-32 is supported for ELF format only"));
10602 mips_abi
= O32_ABI
;
10606 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
10608 as_bad (_("-n32 is supported for ELF format only"));
10611 mips_abi
= N32_ABI
;
10615 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
10617 as_bad (_("-64 is supported for ELF format only"));
10620 mips_abi
= N64_ABI
;
10621 if (! support_64bit_objects())
10622 as_fatal (_("No compiled in support for 64 bit object file format"));
10624 #endif /* OBJ_ELF */
10627 file_mips_gp32
= 1;
10631 file_mips_gp32
= 0;
10635 file_mips_fp32
= 1;
10639 file_mips_fp32
= 0;
10644 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
10646 as_bad (_("-mabi is supported for ELF format only"));
10649 if (strcmp (arg
, "32") == 0)
10650 mips_abi
= O32_ABI
;
10651 else if (strcmp (arg
, "o64") == 0)
10652 mips_abi
= O64_ABI
;
10653 else if (strcmp (arg
, "n32") == 0)
10654 mips_abi
= N32_ABI
;
10655 else if (strcmp (arg
, "64") == 0)
10657 mips_abi
= N64_ABI
;
10658 if (! support_64bit_objects())
10659 as_fatal (_("No compiled in support for 64 bit object file "
10662 else if (strcmp (arg
, "eabi") == 0)
10663 mips_abi
= EABI_ABI
;
10666 as_fatal (_("invalid abi -mabi=%s"), arg
);
10670 #endif /* OBJ_ELF */
10672 case OPTION_M7000_HILO_FIX
:
10673 mips_7000_hilo_fix
= TRUE
;
10676 case OPTION_MNO_7000_HILO_FIX
:
10677 mips_7000_hilo_fix
= FALSE
;
10681 case OPTION_MDEBUG
:
10682 mips_flag_mdebug
= TRUE
;
10685 case OPTION_NO_MDEBUG
:
10686 mips_flag_mdebug
= FALSE
;
10690 mips_flag_pdr
= TRUE
;
10693 case OPTION_NO_PDR
:
10694 mips_flag_pdr
= FALSE
;
10696 #endif /* OBJ_ELF */
10705 /* Set up globals to generate code for the ISA or processor
10706 described by INFO. */
10709 mips_set_architecture (const struct mips_cpu_info
*info
)
10713 file_mips_arch
= info
->cpu
;
10714 mips_opts
.arch
= info
->cpu
;
10715 mips_opts
.isa
= info
->isa
;
10720 /* Likewise for tuning. */
10723 mips_set_tune (const struct mips_cpu_info
*info
)
10726 mips_tune
= info
->cpu
;
10731 mips_after_parse_args (void)
10733 const struct mips_cpu_info
*arch_info
= 0;
10734 const struct mips_cpu_info
*tune_info
= 0;
10736 /* GP relative stuff not working for PE */
10737 if (strncmp (TARGET_OS
, "pe", 2) == 0)
10739 if (g_switch_seen
&& g_switch_value
!= 0)
10740 as_bad (_("-G not supported in this configuration."));
10741 g_switch_value
= 0;
10744 if (mips_abi
== NO_ABI
)
10745 mips_abi
= MIPS_DEFAULT_ABI
;
10747 /* The following code determines the architecture and register size.
10748 Similar code was added to GCC 3.3 (see override_options() in
10749 config/mips/mips.c). The GAS and GCC code should be kept in sync
10750 as much as possible. */
10752 if (mips_arch_string
!= 0)
10753 arch_info
= mips_parse_cpu ("-march", mips_arch_string
);
10755 if (file_mips_isa
!= ISA_UNKNOWN
)
10757 /* Handle -mipsN. At this point, file_mips_isa contains the
10758 ISA level specified by -mipsN, while arch_info->isa contains
10759 the -march selection (if any). */
10760 if (arch_info
!= 0)
10762 /* -march takes precedence over -mipsN, since it is more descriptive.
10763 There's no harm in specifying both as long as the ISA levels
10765 if (file_mips_isa
!= arch_info
->isa
)
10766 as_bad (_("-%s conflicts with the other architecture options, which imply -%s"),
10767 mips_cpu_info_from_isa (file_mips_isa
)->name
,
10768 mips_cpu_info_from_isa (arch_info
->isa
)->name
);
10771 arch_info
= mips_cpu_info_from_isa (file_mips_isa
);
10774 if (arch_info
== 0)
10775 arch_info
= mips_parse_cpu ("default CPU", MIPS_CPU_STRING_DEFAULT
);
10777 if (ABI_NEEDS_64BIT_REGS (mips_abi
) && !ISA_HAS_64BIT_REGS (arch_info
->isa
))
10778 as_bad ("-march=%s is not compatible with the selected ABI",
10781 mips_set_architecture (arch_info
);
10783 /* Optimize for file_mips_arch, unless -mtune selects a different processor. */
10784 if (mips_tune_string
!= 0)
10785 tune_info
= mips_parse_cpu ("-mtune", mips_tune_string
);
10787 if (tune_info
== 0)
10788 mips_set_tune (arch_info
);
10790 mips_set_tune (tune_info
);
10792 if (file_mips_gp32
>= 0)
10794 /* The user specified the size of the integer registers. Make sure
10795 it agrees with the ABI and ISA. */
10796 if (file_mips_gp32
== 0 && !ISA_HAS_64BIT_REGS (mips_opts
.isa
))
10797 as_bad (_("-mgp64 used with a 32-bit processor"));
10798 else if (file_mips_gp32
== 1 && ABI_NEEDS_64BIT_REGS (mips_abi
))
10799 as_bad (_("-mgp32 used with a 64-bit ABI"));
10800 else if (file_mips_gp32
== 0 && ABI_NEEDS_32BIT_REGS (mips_abi
))
10801 as_bad (_("-mgp64 used with a 32-bit ABI"));
10805 /* Infer the integer register size from the ABI and processor.
10806 Restrict ourselves to 32-bit registers if that's all the
10807 processor has, or if the ABI cannot handle 64-bit registers. */
10808 file_mips_gp32
= (ABI_NEEDS_32BIT_REGS (mips_abi
)
10809 || !ISA_HAS_64BIT_REGS (mips_opts
.isa
));
10812 /* ??? GAS treats single-float processors as though they had 64-bit
10813 float registers (although it complains when double-precision
10814 instructions are used). As things stand, saying they have 32-bit
10815 registers would lead to spurious "register must be even" messages.
10816 So here we assume float registers are always the same size as
10817 integer ones, unless the user says otherwise. */
10818 if (file_mips_fp32
< 0)
10819 file_mips_fp32
= file_mips_gp32
;
10821 /* End of GCC-shared inference code. */
10823 /* This flag is set when we have a 64-bit capable CPU but use only
10824 32-bit wide registers. Note that EABI does not use it. */
10825 if (ISA_HAS_64BIT_REGS (mips_opts
.isa
)
10826 && ((mips_abi
== NO_ABI
&& file_mips_gp32
== 1)
10827 || mips_abi
== O32_ABI
))
10828 mips_32bitmode
= 1;
10830 if (mips_opts
.isa
== ISA_MIPS1
&& mips_trap
)
10831 as_bad (_("trap exception not supported at ISA 1"));
10833 /* If the selected architecture includes support for ASEs, enable
10834 generation of code for them. */
10835 if (mips_opts
.mips16
== -1)
10836 mips_opts
.mips16
= (CPU_HAS_MIPS16 (file_mips_arch
)) ? 1 : 0;
10837 if (mips_opts
.ase_mips3d
== -1)
10838 mips_opts
.ase_mips3d
= (CPU_HAS_MIPS3D (file_mips_arch
)) ? 1 : 0;
10839 if (mips_opts
.ase_mdmx
== -1)
10840 mips_opts
.ase_mdmx
= (CPU_HAS_MDMX (file_mips_arch
)) ? 1 : 0;
10841 if (mips_opts
.ase_dsp
== -1)
10842 mips_opts
.ase_dsp
= (CPU_HAS_DSP (file_mips_arch
)) ? 1 : 0;
10844 file_mips_isa
= mips_opts
.isa
;
10845 file_ase_mips16
= mips_opts
.mips16
;
10846 file_ase_mips3d
= mips_opts
.ase_mips3d
;
10847 file_ase_mdmx
= mips_opts
.ase_mdmx
;
10848 file_ase_dsp
= mips_opts
.ase_dsp
;
10849 mips_opts
.gp32
= file_mips_gp32
;
10850 mips_opts
.fp32
= file_mips_fp32
;
10852 if (mips_flag_mdebug
< 0)
10854 #ifdef OBJ_MAYBE_ECOFF
10855 if (OUTPUT_FLAVOR
== bfd_target_ecoff_flavour
)
10856 mips_flag_mdebug
= 1;
10858 #endif /* OBJ_MAYBE_ECOFF */
10859 mips_flag_mdebug
= 0;
10864 mips_init_after_args (void)
10866 /* initialize opcodes */
10867 bfd_mips_num_opcodes
= bfd_mips_num_builtin_opcodes
;
10868 mips_opcodes
= (struct mips_opcode
*) mips_builtin_opcodes
;
10872 md_pcrel_from (fixS
*fixP
)
10874 valueT addr
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
10875 switch (fixP
->fx_r_type
)
10877 case BFD_RELOC_16_PCREL_S2
:
10878 case BFD_RELOC_MIPS_JMP
:
10879 /* Return the address of the delay slot. */
10886 /* This is called before the symbol table is processed. In order to
10887 work with gcc when using mips-tfile, we must keep all local labels.
10888 However, in other cases, we want to discard them. If we were
10889 called with -g, but we didn't see any debugging information, it may
10890 mean that gcc is smuggling debugging information through to
10891 mips-tfile, in which case we must generate all local labels. */
10894 mips_frob_file_before_adjust (void)
10896 #ifndef NO_ECOFF_DEBUGGING
10897 if (ECOFF_DEBUGGING
10899 && ! ecoff_debugging_seen
)
10900 flag_keep_locals
= 1;
10904 /* Sort any unmatched HI16 and GOT16 relocs so that they immediately precede
10905 the corresponding LO16 reloc. This is called before md_apply_fix and
10906 tc_gen_reloc. Unmatched relocs can only be generated by use of explicit
10907 relocation operators.
10909 For our purposes, a %lo() expression matches a %got() or %hi()
10912 (a) it refers to the same symbol; and
10913 (b) the offset applied in the %lo() expression is no lower than
10914 the offset applied in the %got() or %hi().
10916 (b) allows us to cope with code like:
10919 lh $4,%lo(foo+2)($4)
10921 ...which is legal on RELA targets, and has a well-defined behaviour
10922 if the user knows that adding 2 to "foo" will not induce a carry to
10925 When several %lo()s match a particular %got() or %hi(), we use the
10926 following rules to distinguish them:
10928 (1) %lo()s with smaller offsets are a better match than %lo()s with
10931 (2) %lo()s with no matching %got() or %hi() are better than those
10932 that already have a matching %got() or %hi().
10934 (3) later %lo()s are better than earlier %lo()s.
10936 These rules are applied in order.
10938 (1) means, among other things, that %lo()s with identical offsets are
10939 chosen if they exist.
10941 (2) means that we won't associate several high-part relocations with
10942 the same low-part relocation unless there's no alternative. Having
10943 several high parts for the same low part is a GNU extension; this rule
10944 allows careful users to avoid it.
10946 (3) is purely cosmetic. mips_hi_fixup_list is is in reverse order,
10947 with the last high-part relocation being at the front of the list.
10948 It therefore makes sense to choose the last matching low-part
10949 relocation, all other things being equal. It's also easier
10950 to code that way. */
10953 mips_frob_file (void)
10955 struct mips_hi_fixup
*l
;
10957 for (l
= mips_hi_fixup_list
; l
!= NULL
; l
= l
->next
)
10959 segment_info_type
*seginfo
;
10960 bfd_boolean matched_lo_p
;
10961 fixS
**hi_pos
, **lo_pos
, **pos
;
10963 assert (reloc_needs_lo_p (l
->fixp
->fx_r_type
));
10965 /* If a GOT16 relocation turns out to be against a global symbol,
10966 there isn't supposed to be a matching LO. */
10967 if (l
->fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT16
10968 && !pic_need_relax (l
->fixp
->fx_addsy
, l
->seg
))
10971 /* Check quickly whether the next fixup happens to be a matching %lo. */
10972 if (fixup_has_matching_lo_p (l
->fixp
))
10975 seginfo
= seg_info (l
->seg
);
10977 /* Set HI_POS to the position of this relocation in the chain.
10978 Set LO_POS to the position of the chosen low-part relocation.
10979 MATCHED_LO_P is true on entry to the loop if *POS is a low-part
10980 relocation that matches an immediately-preceding high-part
10984 matched_lo_p
= FALSE
;
10985 for (pos
= &seginfo
->fix_root
; *pos
!= NULL
; pos
= &(*pos
)->fx_next
)
10987 if (*pos
== l
->fixp
)
10990 if (((*pos
)->fx_r_type
== BFD_RELOC_LO16
10991 || (*pos
)->fx_r_type
== BFD_RELOC_MIPS16_LO16
)
10992 && (*pos
)->fx_addsy
== l
->fixp
->fx_addsy
10993 && (*pos
)->fx_offset
>= l
->fixp
->fx_offset
10995 || (*pos
)->fx_offset
< (*lo_pos
)->fx_offset
10997 && (*pos
)->fx_offset
== (*lo_pos
)->fx_offset
)))
11000 matched_lo_p
= (reloc_needs_lo_p ((*pos
)->fx_r_type
)
11001 && fixup_has_matching_lo_p (*pos
));
11004 /* If we found a match, remove the high-part relocation from its
11005 current position and insert it before the low-part relocation.
11006 Make the offsets match so that fixup_has_matching_lo_p()
11009 We don't warn about unmatched high-part relocations since some
11010 versions of gcc have been known to emit dead "lui ...%hi(...)"
11012 if (lo_pos
!= NULL
)
11014 l
->fixp
->fx_offset
= (*lo_pos
)->fx_offset
;
11015 if (l
->fixp
->fx_next
!= *lo_pos
)
11017 *hi_pos
= l
->fixp
->fx_next
;
11018 l
->fixp
->fx_next
= *lo_pos
;
11025 /* We may have combined relocations without symbols in the N32/N64 ABI.
11026 We have to prevent gas from dropping them. */
11029 mips_force_relocation (fixS
*fixp
)
11031 if (generic_force_reloc (fixp
))
11035 && S_GET_SEGMENT (fixp
->fx_addsy
) == bfd_abs_section_ptr
11036 && (fixp
->fx_r_type
== BFD_RELOC_MIPS_SUB
11037 || fixp
->fx_r_type
== BFD_RELOC_HI16_S
11038 || fixp
->fx_r_type
== BFD_RELOC_LO16
))
11044 /* This hook is called before a fix is simplified. We don't really
11045 decide whether to skip a fix here. Rather, we turn global symbols
11046 used as branch targets into local symbols, such that they undergo
11047 simplification. We can only do this if the symbol is defined and
11048 it is in the same section as the branch. If this doesn't hold, we
11049 emit a better error message than just saying the relocation is not
11050 valid for the selected object format.
11052 FIXP is the fix-up we're going to try to simplify, SEG is the
11053 segment in which the fix up occurs. The return value should be
11054 non-zero to indicate the fix-up is valid for further
11055 simplifications. */
11058 mips_validate_fix (struct fix
*fixP
, asection
*seg
)
11060 /* There's a lot of discussion on whether it should be possible to
11061 use R_MIPS_PC16 to represent branch relocations. The outcome
11062 seems to be that it can, but gas/bfd are very broken in creating
11063 RELA relocations for this, so for now we only accept branches to
11064 symbols in the same section. Anything else is of dubious value,
11065 since there's no guarantee that at link time the symbol would be
11066 in range. Even for branches to local symbols this is arguably
11067 wrong, since it we assume the symbol is not going to be
11068 overridden, which should be possible per ELF library semantics,
11069 but then, there isn't a dynamic relocation that could be used to
11070 this effect, and the target would likely be out of range as well.
11072 Unfortunately, it seems that there is too much code out there
11073 that relies on branches to symbols that are global to be resolved
11074 as if they were local, like the IRIX tools do, so we do it as
11075 well, but with a warning so that people are reminded to fix their
11076 code. If we ever get back to using R_MIPS_PC16 for branch
11077 targets, this entire block should go away (and probably the
11078 whole function). */
11080 if (fixP
->fx_r_type
== BFD_RELOC_16_PCREL_S2
11081 && ((OUTPUT_FLAVOR
== bfd_target_ecoff_flavour
11082 || OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
11083 || bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_16_PCREL_S2
) == NULL
)
11086 if (! S_IS_DEFINED (fixP
->fx_addsy
))
11088 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
11089 _("Cannot branch to undefined symbol."));
11090 /* Avoid any further errors about this fixup. */
11093 else if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
11095 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
11096 _("Cannot branch to symbol in another section."));
11099 else if (S_IS_EXTERNAL (fixP
->fx_addsy
))
11101 symbolS
*sym
= fixP
->fx_addsy
;
11103 if (mips_pic
== SVR4_PIC
)
11104 as_warn_where (fixP
->fx_file
, fixP
->fx_line
,
11105 _("Pretending global symbol used as branch target is local."));
11107 fixP
->fx_addsy
= symbol_create (S_GET_NAME (sym
),
11108 S_GET_SEGMENT (sym
),
11110 symbol_get_frag (sym
));
11111 copy_symbol_attributes (fixP
->fx_addsy
, sym
);
11112 S_CLEAR_EXTERNAL (fixP
->fx_addsy
);
11113 assert (symbol_resolved_p (sym
));
11114 symbol_mark_resolved (fixP
->fx_addsy
);
11121 /* Apply a fixup to the object file. */
11124 md_apply_fix (fixS
*fixP
, valueT
*valP
, segT seg ATTRIBUTE_UNUSED
)
11128 reloc_howto_type
*howto
;
11130 /* We ignore generic BFD relocations we don't know about. */
11131 howto
= bfd_reloc_type_lookup (stdoutput
, fixP
->fx_r_type
);
11135 assert (fixP
->fx_size
== 4
11136 || fixP
->fx_r_type
== BFD_RELOC_16
11137 || fixP
->fx_r_type
== BFD_RELOC_64
11138 || fixP
->fx_r_type
== BFD_RELOC_CTOR
11139 || fixP
->fx_r_type
== BFD_RELOC_MIPS_SUB
11140 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
11141 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
);
11143 buf
= (bfd_byte
*) (fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
);
11145 assert (! fixP
->fx_pcrel
);
11147 /* Don't treat parts of a composite relocation as done. There are two
11150 (1) The second and third parts will be against 0 (RSS_UNDEF) but
11151 should nevertheless be emitted if the first part is.
11153 (2) In normal usage, composite relocations are never assembly-time
11154 constants. The easiest way of dealing with the pathological
11155 exceptions is to generate a relocation against STN_UNDEF and
11156 leave everything up to the linker. */
11157 if (fixP
->fx_addsy
== NULL
&& fixP
->fx_tcbit
== 0)
11160 switch (fixP
->fx_r_type
)
11162 case BFD_RELOC_MIPS_TLS_GD
:
11163 case BFD_RELOC_MIPS_TLS_LDM
:
11164 case BFD_RELOC_MIPS_TLS_DTPREL_HI16
:
11165 case BFD_RELOC_MIPS_TLS_DTPREL_LO16
:
11166 case BFD_RELOC_MIPS_TLS_GOTTPREL
:
11167 case BFD_RELOC_MIPS_TLS_TPREL_HI16
:
11168 case BFD_RELOC_MIPS_TLS_TPREL_LO16
:
11169 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
11172 case BFD_RELOC_MIPS_JMP
:
11173 case BFD_RELOC_MIPS_SHIFT5
:
11174 case BFD_RELOC_MIPS_SHIFT6
:
11175 case BFD_RELOC_MIPS_GOT_DISP
:
11176 case BFD_RELOC_MIPS_GOT_PAGE
:
11177 case BFD_RELOC_MIPS_GOT_OFST
:
11178 case BFD_RELOC_MIPS_SUB
:
11179 case BFD_RELOC_MIPS_INSERT_A
:
11180 case BFD_RELOC_MIPS_INSERT_B
:
11181 case BFD_RELOC_MIPS_DELETE
:
11182 case BFD_RELOC_MIPS_HIGHEST
:
11183 case BFD_RELOC_MIPS_HIGHER
:
11184 case BFD_RELOC_MIPS_SCN_DISP
:
11185 case BFD_RELOC_MIPS_REL16
:
11186 case BFD_RELOC_MIPS_RELGOT
:
11187 case BFD_RELOC_MIPS_JALR
:
11188 case BFD_RELOC_HI16
:
11189 case BFD_RELOC_HI16_S
:
11190 case BFD_RELOC_GPREL16
:
11191 case BFD_RELOC_MIPS_LITERAL
:
11192 case BFD_RELOC_MIPS_CALL16
:
11193 case BFD_RELOC_MIPS_GOT16
:
11194 case BFD_RELOC_GPREL32
:
11195 case BFD_RELOC_MIPS_GOT_HI16
:
11196 case BFD_RELOC_MIPS_GOT_LO16
:
11197 case BFD_RELOC_MIPS_CALL_HI16
:
11198 case BFD_RELOC_MIPS_CALL_LO16
:
11199 case BFD_RELOC_MIPS16_GPREL
:
11200 case BFD_RELOC_MIPS16_HI16
:
11201 case BFD_RELOC_MIPS16_HI16_S
:
11202 assert (! fixP
->fx_pcrel
);
11203 /* Nothing needed to do. The value comes from the reloc entry */
11206 case BFD_RELOC_MIPS16_JMP
:
11207 /* We currently always generate a reloc against a symbol, which
11208 means that we don't want an addend even if the symbol is
11214 /* This is handled like BFD_RELOC_32, but we output a sign
11215 extended value if we are only 32 bits. */
11218 if (8 <= sizeof (valueT
))
11219 md_number_to_chars ((char *) buf
, *valP
, 8);
11224 if ((*valP
& 0x80000000) != 0)
11228 md_number_to_chars ((char *)(buf
+ (target_big_endian
? 4 : 0)),
11230 md_number_to_chars ((char *)(buf
+ (target_big_endian
? 0 : 4)),
11236 case BFD_RELOC_RVA
:
11238 /* If we are deleting this reloc entry, we must fill in the
11239 value now. This can happen if we have a .word which is not
11240 resolved when it appears but is later defined. */
11242 md_number_to_chars ((char *) buf
, *valP
, 4);
11246 /* If we are deleting this reloc entry, we must fill in the
11249 md_number_to_chars ((char *) buf
, *valP
, 2);
11252 case BFD_RELOC_LO16
:
11253 case BFD_RELOC_MIPS16_LO16
:
11254 /* FIXME: Now that embedded-PIC is gone, some of this code/comment
11255 may be safe to remove, but if so it's not obvious. */
11256 /* When handling an embedded PIC switch statement, we can wind
11257 up deleting a LO16 reloc. See the 'o' case in mips_ip. */
11260 if (*valP
+ 0x8000 > 0xffff)
11261 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
11262 _("relocation overflow"));
11263 if (target_big_endian
)
11265 md_number_to_chars ((char *) buf
, *valP
, 2);
11269 case BFD_RELOC_16_PCREL_S2
:
11270 if ((*valP
& 0x3) != 0)
11271 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
11272 _("Branch to odd address (%lx)"), (long) *valP
);
11275 * We need to save the bits in the instruction since fixup_segment()
11276 * might be deleting the relocation entry (i.e., a branch within
11277 * the current segment).
11279 if (! fixP
->fx_done
)
11282 /* update old instruction data */
11283 if (target_big_endian
)
11284 insn
= (buf
[0] << 24) | (buf
[1] << 16) | (buf
[2] << 8) | buf
[3];
11286 insn
= (buf
[3] << 24) | (buf
[2] << 16) | (buf
[1] << 8) | buf
[0];
11288 if (*valP
+ 0x20000 <= 0x3ffff)
11290 insn
|= (*valP
>> 2) & 0xffff;
11291 md_number_to_chars ((char *) buf
, insn
, 4);
11293 else if (mips_pic
== NO_PIC
11295 && fixP
->fx_frag
->fr_address
>= text_section
->vma
11296 && (fixP
->fx_frag
->fr_address
11297 < text_section
->vma
+ bfd_get_section_size (text_section
))
11298 && ((insn
& 0xffff0000) == 0x10000000 /* beq $0,$0 */
11299 || (insn
& 0xffff0000) == 0x04010000 /* bgez $0 */
11300 || (insn
& 0xffff0000) == 0x04110000)) /* bgezal $0 */
11302 /* The branch offset is too large. If this is an
11303 unconditional branch, and we are not generating PIC code,
11304 we can convert it to an absolute jump instruction. */
11305 if ((insn
& 0xffff0000) == 0x04110000) /* bgezal $0 */
11306 insn
= 0x0c000000; /* jal */
11308 insn
= 0x08000000; /* j */
11309 fixP
->fx_r_type
= BFD_RELOC_MIPS_JMP
;
11311 fixP
->fx_addsy
= section_symbol (text_section
);
11312 *valP
+= md_pcrel_from (fixP
);
11313 md_number_to_chars ((char *) buf
, insn
, 4);
11317 /* If we got here, we have branch-relaxation disabled,
11318 and there's nothing we can do to fix this instruction
11319 without turning it into a longer sequence. */
11320 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
11321 _("Branch out of range"));
11325 case BFD_RELOC_VTABLE_INHERIT
:
11328 && !S_IS_DEFINED (fixP
->fx_addsy
)
11329 && !S_IS_WEAK (fixP
->fx_addsy
))
11330 S_SET_WEAK (fixP
->fx_addsy
);
11333 case BFD_RELOC_VTABLE_ENTRY
:
11341 /* Remember value for tc_gen_reloc. */
11342 fixP
->fx_addnumber
= *valP
;
11352 name
= input_line_pointer
;
11353 c
= get_symbol_end ();
11354 p
= (symbolS
*) symbol_find_or_make (name
);
11355 *input_line_pointer
= c
;
11359 /* Align the current frag to a given power of two. The MIPS assembler
11360 also automatically adjusts any preceding label. */
11363 mips_align (int to
, int fill
, symbolS
*label
)
11365 mips_emit_delays ();
11366 frag_align (to
, fill
, 0);
11367 record_alignment (now_seg
, to
);
11370 assert (S_GET_SEGMENT (label
) == now_seg
);
11371 symbol_set_frag (label
, frag_now
);
11372 S_SET_VALUE (label
, (valueT
) frag_now_fix ());
11376 /* Align to a given power of two. .align 0 turns off the automatic
11377 alignment used by the data creating pseudo-ops. */
11380 s_align (int x ATTRIBUTE_UNUSED
)
11383 register long temp_fill
;
11384 long max_alignment
= 15;
11388 o Note that the assembler pulls down any immediately preceding label
11389 to the aligned address.
11390 o It's not documented but auto alignment is reinstated by
11391 a .align pseudo instruction.
11392 o Note also that after auto alignment is turned off the mips assembler
11393 issues an error on attempt to assemble an improperly aligned data item.
11398 temp
= get_absolute_expression ();
11399 if (temp
> max_alignment
)
11400 as_bad (_("Alignment too large: %d. assumed."), temp
= max_alignment
);
11403 as_warn (_("Alignment negative: 0 assumed."));
11406 if (*input_line_pointer
== ',')
11408 ++input_line_pointer
;
11409 temp_fill
= get_absolute_expression ();
11416 mips_align (temp
, (int) temp_fill
,
11417 insn_labels
!= NULL
? insn_labels
->label
: NULL
);
11424 demand_empty_rest_of_line ();
11428 s_change_sec (int sec
)
11433 /* The ELF backend needs to know that we are changing sections, so
11434 that .previous works correctly. We could do something like check
11435 for an obj_section_change_hook macro, but that might be confusing
11436 as it would not be appropriate to use it in the section changing
11437 functions in read.c, since obj-elf.c intercepts those. FIXME:
11438 This should be cleaner, somehow. */
11439 obj_elf_section_change_hook ();
11442 mips_emit_delays ();
11452 subseg_set (bss_section
, (subsegT
) get_absolute_expression ());
11453 demand_empty_rest_of_line ();
11457 seg
= subseg_new (RDATA_SECTION_NAME
,
11458 (subsegT
) get_absolute_expression ());
11459 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
11461 bfd_set_section_flags (stdoutput
, seg
, (SEC_ALLOC
| SEC_LOAD
11462 | SEC_READONLY
| SEC_RELOC
11464 if (strcmp (TARGET_OS
, "elf") != 0)
11465 record_alignment (seg
, 4);
11467 demand_empty_rest_of_line ();
11471 seg
= subseg_new (".sdata", (subsegT
) get_absolute_expression ());
11472 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
11474 bfd_set_section_flags (stdoutput
, seg
,
11475 SEC_ALLOC
| SEC_LOAD
| SEC_RELOC
| SEC_DATA
);
11476 if (strcmp (TARGET_OS
, "elf") != 0)
11477 record_alignment (seg
, 4);
11479 demand_empty_rest_of_line ();
11487 s_change_section (int ignore ATTRIBUTE_UNUSED
)
11490 char *section_name
;
11495 int section_entry_size
;
11496 int section_alignment
;
11498 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
11501 section_name
= input_line_pointer
;
11502 c
= get_symbol_end ();
11504 next_c
= *(input_line_pointer
+ 1);
11506 /* Do we have .section Name<,"flags">? */
11507 if (c
!= ',' || (c
== ',' && next_c
== '"'))
11509 /* just after name is now '\0'. */
11510 *input_line_pointer
= c
;
11511 input_line_pointer
= section_name
;
11512 obj_elf_section (ignore
);
11515 input_line_pointer
++;
11517 /* Do we have .section Name<,type><,flag><,entry_size><,alignment> */
11519 section_type
= get_absolute_expression ();
11522 if (*input_line_pointer
++ == ',')
11523 section_flag
= get_absolute_expression ();
11526 if (*input_line_pointer
++ == ',')
11527 section_entry_size
= get_absolute_expression ();
11529 section_entry_size
= 0;
11530 if (*input_line_pointer
++ == ',')
11531 section_alignment
= get_absolute_expression ();
11533 section_alignment
= 0;
11535 section_name
= xstrdup (section_name
);
11537 /* When using the generic form of .section (as implemented by obj-elf.c),
11538 there's no way to set the section type to SHT_MIPS_DWARF. Users have
11539 traditionally had to fall back on the more common @progbits instead.
11541 There's nothing really harmful in this, since bfd will correct
11542 SHT_PROGBITS to SHT_MIPS_DWARF before writing out the file. But it
11543 means that, for backwards compatibiltiy, the special_section entries
11544 for dwarf sections must use SHT_PROGBITS rather than SHT_MIPS_DWARF.
11546 Even so, we shouldn't force users of the MIPS .section syntax to
11547 incorrectly label the sections as SHT_PROGBITS. The best compromise
11548 seems to be to map SHT_MIPS_DWARF to SHT_PROGBITS before calling the
11549 generic type-checking code. */
11550 if (section_type
== SHT_MIPS_DWARF
)
11551 section_type
= SHT_PROGBITS
;
11553 obj_elf_change_section (section_name
, section_type
, section_flag
,
11554 section_entry_size
, 0, 0, 0);
11556 if (now_seg
->name
!= section_name
)
11557 free (section_name
);
11558 #endif /* OBJ_ELF */
11562 mips_enable_auto_align (void)
11568 s_cons (int log_size
)
11572 label
= insn_labels
!= NULL
? insn_labels
->label
: NULL
;
11573 mips_emit_delays ();
11574 if (log_size
> 0 && auto_align
)
11575 mips_align (log_size
, 0, label
);
11576 mips_clear_insn_labels ();
11577 cons (1 << log_size
);
11581 s_float_cons (int type
)
11585 label
= insn_labels
!= NULL
? insn_labels
->label
: NULL
;
11587 mips_emit_delays ();
11592 mips_align (3, 0, label
);
11594 mips_align (2, 0, label
);
11597 mips_clear_insn_labels ();
11602 /* Handle .globl. We need to override it because on Irix 5 you are
11605 where foo is an undefined symbol, to mean that foo should be
11606 considered to be the address of a function. */
11609 s_mips_globl (int x ATTRIBUTE_UNUSED
)
11618 name
= input_line_pointer
;
11619 c
= get_symbol_end ();
11620 symbolP
= symbol_find_or_make (name
);
11621 S_SET_EXTERNAL (symbolP
);
11623 *input_line_pointer
= c
;
11624 SKIP_WHITESPACE ();
11626 /* On Irix 5, every global symbol that is not explicitly labelled as
11627 being a function is apparently labelled as being an object. */
11630 if (!is_end_of_line
[(unsigned char) *input_line_pointer
]
11631 && (*input_line_pointer
!= ','))
11636 secname
= input_line_pointer
;
11637 c
= get_symbol_end ();
11638 sec
= bfd_get_section_by_name (stdoutput
, secname
);
11640 as_bad (_("%s: no such section"), secname
);
11641 *input_line_pointer
= c
;
11643 if (sec
!= NULL
&& (sec
->flags
& SEC_CODE
) != 0)
11644 flag
= BSF_FUNCTION
;
11647 symbol_get_bfdsym (symbolP
)->flags
|= flag
;
11649 c
= *input_line_pointer
;
11652 input_line_pointer
++;
11653 SKIP_WHITESPACE ();
11654 if (is_end_of_line
[(unsigned char) *input_line_pointer
])
11660 demand_empty_rest_of_line ();
11664 s_option (int x ATTRIBUTE_UNUSED
)
11669 opt
= input_line_pointer
;
11670 c
= get_symbol_end ();
11674 /* FIXME: What does this mean? */
11676 else if (strncmp (opt
, "pic", 3) == 0)
11680 i
= atoi (opt
+ 3);
11685 mips_pic
= SVR4_PIC
;
11686 mips_abicalls
= TRUE
;
11689 as_bad (_(".option pic%d not supported"), i
);
11691 if (mips_pic
== SVR4_PIC
)
11693 if (g_switch_seen
&& g_switch_value
!= 0)
11694 as_warn (_("-G may not be used with SVR4 PIC code"));
11695 g_switch_value
= 0;
11696 bfd_set_gp_size (stdoutput
, 0);
11700 as_warn (_("Unrecognized option \"%s\""), opt
);
11702 *input_line_pointer
= c
;
11703 demand_empty_rest_of_line ();
11706 /* This structure is used to hold a stack of .set values. */
11708 struct mips_option_stack
11710 struct mips_option_stack
*next
;
11711 struct mips_set_options options
;
11714 static struct mips_option_stack
*mips_opts_stack
;
11716 /* Handle the .set pseudo-op. */
11719 s_mipsset (int x ATTRIBUTE_UNUSED
)
11721 char *name
= input_line_pointer
, ch
;
11723 while (!is_end_of_line
[(unsigned char) *input_line_pointer
])
11724 ++input_line_pointer
;
11725 ch
= *input_line_pointer
;
11726 *input_line_pointer
= '\0';
11728 if (strcmp (name
, "reorder") == 0)
11730 if (mips_opts
.noreorder
)
11733 else if (strcmp (name
, "noreorder") == 0)
11735 if (!mips_opts
.noreorder
)
11736 start_noreorder ();
11738 else if (strcmp (name
, "at") == 0)
11740 mips_opts
.noat
= 0;
11742 else if (strcmp (name
, "noat") == 0)
11744 mips_opts
.noat
= 1;
11746 else if (strcmp (name
, "macro") == 0)
11748 mips_opts
.warn_about_macros
= 0;
11750 else if (strcmp (name
, "nomacro") == 0)
11752 if (mips_opts
.noreorder
== 0)
11753 as_bad (_("`noreorder' must be set before `nomacro'"));
11754 mips_opts
.warn_about_macros
= 1;
11756 else if (strcmp (name
, "move") == 0 || strcmp (name
, "novolatile") == 0)
11758 mips_opts
.nomove
= 0;
11760 else if (strcmp (name
, "nomove") == 0 || strcmp (name
, "volatile") == 0)
11762 mips_opts
.nomove
= 1;
11764 else if (strcmp (name
, "bopt") == 0)
11766 mips_opts
.nobopt
= 0;
11768 else if (strcmp (name
, "nobopt") == 0)
11770 mips_opts
.nobopt
= 1;
11772 else if (strcmp (name
, "mips16") == 0
11773 || strcmp (name
, "MIPS-16") == 0)
11774 mips_opts
.mips16
= 1;
11775 else if (strcmp (name
, "nomips16") == 0
11776 || strcmp (name
, "noMIPS-16") == 0)
11777 mips_opts
.mips16
= 0;
11778 else if (strcmp (name
, "mips3d") == 0)
11779 mips_opts
.ase_mips3d
= 1;
11780 else if (strcmp (name
, "nomips3d") == 0)
11781 mips_opts
.ase_mips3d
= 0;
11782 else if (strcmp (name
, "mdmx") == 0)
11783 mips_opts
.ase_mdmx
= 1;
11784 else if (strcmp (name
, "nomdmx") == 0)
11785 mips_opts
.ase_mdmx
= 0;
11786 else if (strcmp (name
, "dsp") == 0)
11787 mips_opts
.ase_dsp
= 1;
11788 else if (strcmp (name
, "nodsp") == 0)
11789 mips_opts
.ase_dsp
= 0;
11790 else if (strncmp (name
, "mips", 4) == 0 || strncmp (name
, "arch=", 5) == 0)
11794 /* Permit the user to change the ISA and architecture on the fly.
11795 Needless to say, misuse can cause serious problems. */
11796 if (strcmp (name
, "mips0") == 0 || strcmp (name
, "arch=default") == 0)
11799 mips_opts
.isa
= file_mips_isa
;
11800 mips_opts
.arch
= file_mips_arch
;
11802 else if (strncmp (name
, "arch=", 5) == 0)
11804 const struct mips_cpu_info
*p
;
11806 p
= mips_parse_cpu("internal use", name
+ 5);
11808 as_bad (_("unknown architecture %s"), name
+ 5);
11811 mips_opts
.arch
= p
->cpu
;
11812 mips_opts
.isa
= p
->isa
;
11815 else if (strncmp (name
, "mips", 4) == 0)
11817 const struct mips_cpu_info
*p
;
11819 p
= mips_parse_cpu("internal use", name
);
11821 as_bad (_("unknown ISA level %s"), name
+ 4);
11824 mips_opts
.arch
= p
->cpu
;
11825 mips_opts
.isa
= p
->isa
;
11829 as_bad (_("unknown ISA or architecture %s"), name
);
11831 switch (mips_opts
.isa
)
11839 mips_opts
.gp32
= 1;
11840 mips_opts
.fp32
= 1;
11847 mips_opts
.gp32
= 0;
11848 mips_opts
.fp32
= 0;
11851 as_bad (_("unknown ISA level %s"), name
+ 4);
11856 mips_opts
.gp32
= file_mips_gp32
;
11857 mips_opts
.fp32
= file_mips_fp32
;
11860 else if (strcmp (name
, "autoextend") == 0)
11861 mips_opts
.noautoextend
= 0;
11862 else if (strcmp (name
, "noautoextend") == 0)
11863 mips_opts
.noautoextend
= 1;
11864 else if (strcmp (name
, "push") == 0)
11866 struct mips_option_stack
*s
;
11868 s
= (struct mips_option_stack
*) xmalloc (sizeof *s
);
11869 s
->next
= mips_opts_stack
;
11870 s
->options
= mips_opts
;
11871 mips_opts_stack
= s
;
11873 else if (strcmp (name
, "pop") == 0)
11875 struct mips_option_stack
*s
;
11877 s
= mips_opts_stack
;
11879 as_bad (_(".set pop with no .set push"));
11882 /* If we're changing the reorder mode we need to handle
11883 delay slots correctly. */
11884 if (s
->options
.noreorder
&& ! mips_opts
.noreorder
)
11885 start_noreorder ();
11886 else if (! s
->options
.noreorder
&& mips_opts
.noreorder
)
11889 mips_opts
= s
->options
;
11890 mips_opts_stack
= s
->next
;
11894 else if (strcmp (name
, "sym32") == 0)
11895 mips_opts
.sym32
= TRUE
;
11896 else if (strcmp (name
, "nosym32") == 0)
11897 mips_opts
.sym32
= FALSE
;
11900 as_warn (_("Tried to set unrecognized symbol: %s\n"), name
);
11902 *input_line_pointer
= ch
;
11903 demand_empty_rest_of_line ();
11906 /* Handle the .abicalls pseudo-op. I believe this is equivalent to
11907 .option pic2. It means to generate SVR4 PIC calls. */
11910 s_abicalls (int ignore ATTRIBUTE_UNUSED
)
11912 mips_pic
= SVR4_PIC
;
11913 mips_abicalls
= TRUE
;
11915 if (g_switch_seen
&& g_switch_value
!= 0)
11916 as_warn (_("-G may not be used with SVR4 PIC code"));
11917 g_switch_value
= 0;
11919 bfd_set_gp_size (stdoutput
, 0);
11920 demand_empty_rest_of_line ();
11923 /* Handle the .cpload pseudo-op. This is used when generating SVR4
11924 PIC code. It sets the $gp register for the function based on the
11925 function address, which is in the register named in the argument.
11926 This uses a relocation against _gp_disp, which is handled specially
11927 by the linker. The result is:
11928 lui $gp,%hi(_gp_disp)
11929 addiu $gp,$gp,%lo(_gp_disp)
11930 addu $gp,$gp,.cpload argument
11931 The .cpload argument is normally $25 == $t9.
11933 The -mno-shared option changes this to:
11934 lui $gp,%hi(__gnu_local_gp)
11935 addiu $gp,$gp,%lo(__gnu_local_gp)
11936 and the argument is ignored. This saves an instruction, but the
11937 resulting code is not position independent; it uses an absolute
11938 address for __gnu_local_gp. Thus code assembled with -mno-shared
11939 can go into an ordinary executable, but not into a shared library. */
11942 s_cpload (int ignore ATTRIBUTE_UNUSED
)
11948 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
11949 .cpload is ignored. */
11950 if (mips_pic
!= SVR4_PIC
|| HAVE_NEWABI
)
11956 /* .cpload should be in a .set noreorder section. */
11957 if (mips_opts
.noreorder
== 0)
11958 as_warn (_(".cpload not in noreorder section"));
11960 reg
= tc_get_register (0);
11962 /* If we need to produce a 64-bit address, we are better off using
11963 the default instruction sequence. */
11964 in_shared
= mips_in_shared
|| HAVE_64BIT_SYMBOLS
;
11966 ex
.X_op
= O_symbol
;
11967 ex
.X_add_symbol
= symbol_find_or_make (in_shared
? "_gp_disp" :
11969 ex
.X_op_symbol
= NULL
;
11970 ex
.X_add_number
= 0;
11972 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
11973 symbol_get_bfdsym (ex
.X_add_symbol
)->flags
|= BSF_OBJECT
;
11976 macro_build_lui (&ex
, mips_gp_register
);
11977 macro_build (&ex
, "addiu", "t,r,j", mips_gp_register
,
11978 mips_gp_register
, BFD_RELOC_LO16
);
11980 macro_build (NULL
, "addu", "d,v,t", mips_gp_register
,
11981 mips_gp_register
, reg
);
11984 demand_empty_rest_of_line ();
11987 /* Handle the .cpsetup pseudo-op defined for NewABI PIC code. The syntax is:
11988 .cpsetup $reg1, offset|$reg2, label
11990 If offset is given, this results in:
11991 sd $gp, offset($sp)
11992 lui $gp, %hi(%neg(%gp_rel(label)))
11993 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
11994 daddu $gp, $gp, $reg1
11996 If $reg2 is given, this results in:
11997 daddu $reg2, $gp, $0
11998 lui $gp, %hi(%neg(%gp_rel(label)))
11999 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
12000 daddu $gp, $gp, $reg1
12001 $reg1 is normally $25 == $t9.
12003 The -mno-shared option replaces the last three instructions with
12005 addiu $gp,$gp,%lo(_gp)
12009 s_cpsetup (int ignore ATTRIBUTE_UNUSED
)
12011 expressionS ex_off
;
12012 expressionS ex_sym
;
12015 /* If we are not generating SVR4 PIC code, .cpsetup is ignored.
12016 We also need NewABI support. */
12017 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
12023 reg1
= tc_get_register (0);
12024 SKIP_WHITESPACE ();
12025 if (*input_line_pointer
!= ',')
12027 as_bad (_("missing argument separator ',' for .cpsetup"));
12031 ++input_line_pointer
;
12032 SKIP_WHITESPACE ();
12033 if (*input_line_pointer
== '$')
12035 mips_cpreturn_register
= tc_get_register (0);
12036 mips_cpreturn_offset
= -1;
12040 mips_cpreturn_offset
= get_absolute_expression ();
12041 mips_cpreturn_register
= -1;
12043 SKIP_WHITESPACE ();
12044 if (*input_line_pointer
!= ',')
12046 as_bad (_("missing argument separator ',' for .cpsetup"));
12050 ++input_line_pointer
;
12051 SKIP_WHITESPACE ();
12052 expression (&ex_sym
);
12055 if (mips_cpreturn_register
== -1)
12057 ex_off
.X_op
= O_constant
;
12058 ex_off
.X_add_symbol
= NULL
;
12059 ex_off
.X_op_symbol
= NULL
;
12060 ex_off
.X_add_number
= mips_cpreturn_offset
;
12062 macro_build (&ex_off
, "sd", "t,o(b)", mips_gp_register
,
12063 BFD_RELOC_LO16
, SP
);
12066 macro_build (NULL
, "daddu", "d,v,t", mips_cpreturn_register
,
12067 mips_gp_register
, 0);
12069 if (mips_in_shared
|| HAVE_64BIT_SYMBOLS
)
12071 macro_build (&ex_sym
, "lui", "t,u", mips_gp_register
,
12072 -1, BFD_RELOC_GPREL16
, BFD_RELOC_MIPS_SUB
,
12075 macro_build (&ex_sym
, "addiu", "t,r,j", mips_gp_register
,
12076 mips_gp_register
, -1, BFD_RELOC_GPREL16
,
12077 BFD_RELOC_MIPS_SUB
, BFD_RELOC_LO16
);
12079 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", mips_gp_register
,
12080 mips_gp_register
, reg1
);
12086 ex
.X_op
= O_symbol
;
12087 ex
.X_add_symbol
= symbol_find_or_make ("__gnu_local_gp");
12088 ex
.X_op_symbol
= NULL
;
12089 ex
.X_add_number
= 0;
12091 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
12092 symbol_get_bfdsym (ex
.X_add_symbol
)->flags
|= BSF_OBJECT
;
12094 macro_build_lui (&ex
, mips_gp_register
);
12095 macro_build (&ex
, "addiu", "t,r,j", mips_gp_register
,
12096 mips_gp_register
, BFD_RELOC_LO16
);
12101 demand_empty_rest_of_line ();
12105 s_cplocal (int ignore ATTRIBUTE_UNUSED
)
12107 /* If we are not generating SVR4 PIC code, or if this is not NewABI code,
12108 .cplocal is ignored. */
12109 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
12115 mips_gp_register
= tc_get_register (0);
12116 demand_empty_rest_of_line ();
12119 /* Handle the .cprestore pseudo-op. This stores $gp into a given
12120 offset from $sp. The offset is remembered, and after making a PIC
12121 call $gp is restored from that location. */
12124 s_cprestore (int ignore ATTRIBUTE_UNUSED
)
12128 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
12129 .cprestore is ignored. */
12130 if (mips_pic
!= SVR4_PIC
|| HAVE_NEWABI
)
12136 mips_cprestore_offset
= get_absolute_expression ();
12137 mips_cprestore_valid
= 1;
12139 ex
.X_op
= O_constant
;
12140 ex
.X_add_symbol
= NULL
;
12141 ex
.X_op_symbol
= NULL
;
12142 ex
.X_add_number
= mips_cprestore_offset
;
12145 macro_build_ldst_constoffset (&ex
, ADDRESS_STORE_INSN
, mips_gp_register
,
12146 SP
, HAVE_64BIT_ADDRESSES
);
12149 demand_empty_rest_of_line ();
12152 /* Handle the .cpreturn pseudo-op defined for NewABI PIC code. If an offset
12153 was given in the preceding .cpsetup, it results in:
12154 ld $gp, offset($sp)
12156 If a register $reg2 was given there, it results in:
12157 daddu $gp, $reg2, $0
12160 s_cpreturn (int ignore ATTRIBUTE_UNUSED
)
12164 /* If we are not generating SVR4 PIC code, .cpreturn is ignored.
12165 We also need NewABI support. */
12166 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
12173 if (mips_cpreturn_register
== -1)
12175 ex
.X_op
= O_constant
;
12176 ex
.X_add_symbol
= NULL
;
12177 ex
.X_op_symbol
= NULL
;
12178 ex
.X_add_number
= mips_cpreturn_offset
;
12180 macro_build (&ex
, "ld", "t,o(b)", mips_gp_register
, BFD_RELOC_LO16
, SP
);
12183 macro_build (NULL
, "daddu", "d,v,t", mips_gp_register
,
12184 mips_cpreturn_register
, 0);
12187 demand_empty_rest_of_line ();
12190 /* Handle the .gpvalue pseudo-op. This is used when generating NewABI PIC
12191 code. It sets the offset to use in gp_rel relocations. */
12194 s_gpvalue (int ignore ATTRIBUTE_UNUSED
)
12196 /* If we are not generating SVR4 PIC code, .gpvalue is ignored.
12197 We also need NewABI support. */
12198 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
12204 mips_gprel_offset
= get_absolute_expression ();
12206 demand_empty_rest_of_line ();
12209 /* Handle the .gpword pseudo-op. This is used when generating PIC
12210 code. It generates a 32 bit GP relative reloc. */
12213 s_gpword (int ignore ATTRIBUTE_UNUSED
)
12219 /* When not generating PIC code, this is treated as .word. */
12220 if (mips_pic
!= SVR4_PIC
)
12226 label
= insn_labels
!= NULL
? insn_labels
->label
: NULL
;
12227 mips_emit_delays ();
12229 mips_align (2, 0, label
);
12230 mips_clear_insn_labels ();
12234 if (ex
.X_op
!= O_symbol
|| ex
.X_add_number
!= 0)
12236 as_bad (_("Unsupported use of .gpword"));
12237 ignore_rest_of_line ();
12241 md_number_to_chars (p
, 0, 4);
12242 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 4, &ex
, FALSE
,
12243 BFD_RELOC_GPREL32
);
12245 demand_empty_rest_of_line ();
12249 s_gpdword (int ignore ATTRIBUTE_UNUSED
)
12255 /* When not generating PIC code, this is treated as .dword. */
12256 if (mips_pic
!= SVR4_PIC
)
12262 label
= insn_labels
!= NULL
? insn_labels
->label
: NULL
;
12263 mips_emit_delays ();
12265 mips_align (3, 0, label
);
12266 mips_clear_insn_labels ();
12270 if (ex
.X_op
!= O_symbol
|| ex
.X_add_number
!= 0)
12272 as_bad (_("Unsupported use of .gpdword"));
12273 ignore_rest_of_line ();
12277 md_number_to_chars (p
, 0, 8);
12278 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 4, &ex
, FALSE
,
12279 BFD_RELOC_GPREL32
)->fx_tcbit
= 1;
12281 /* GPREL32 composed with 64 gives a 64-bit GP offset. */
12282 fix_new (frag_now
, p
- frag_now
->fr_literal
, 8, NULL
, 0,
12283 FALSE
, BFD_RELOC_64
)->fx_tcbit
= 1;
12285 demand_empty_rest_of_line ();
12288 /* Handle the .cpadd pseudo-op. This is used when dealing with switch
12289 tables in SVR4 PIC code. */
12292 s_cpadd (int ignore ATTRIBUTE_UNUSED
)
12296 /* This is ignored when not generating SVR4 PIC code. */
12297 if (mips_pic
!= SVR4_PIC
)
12303 /* Add $gp to the register named as an argument. */
12305 reg
= tc_get_register (0);
12306 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", reg
, reg
, mips_gp_register
);
12309 demand_empty_rest_of_line ();
12312 /* Handle the .insn pseudo-op. This marks instruction labels in
12313 mips16 mode. This permits the linker to handle them specially,
12314 such as generating jalx instructions when needed. We also make
12315 them odd for the duration of the assembly, in order to generate the
12316 right sort of code. We will make them even in the adjust_symtab
12317 routine, while leaving them marked. This is convenient for the
12318 debugger and the disassembler. The linker knows to make them odd
12322 s_insn (int ignore ATTRIBUTE_UNUSED
)
12324 mips16_mark_labels ();
12326 demand_empty_rest_of_line ();
12329 /* Handle a .stabn directive. We need these in order to mark a label
12330 as being a mips16 text label correctly. Sometimes the compiler
12331 will emit a label, followed by a .stabn, and then switch sections.
12332 If the label and .stabn are in mips16 mode, then the label is
12333 really a mips16 text label. */
12336 s_mips_stab (int type
)
12339 mips16_mark_labels ();
12344 /* Handle the .weakext pseudo-op as defined in Kane and Heinrich.
12348 s_mips_weakext (int ignore ATTRIBUTE_UNUSED
)
12355 name
= input_line_pointer
;
12356 c
= get_symbol_end ();
12357 symbolP
= symbol_find_or_make (name
);
12358 S_SET_WEAK (symbolP
);
12359 *input_line_pointer
= c
;
12361 SKIP_WHITESPACE ();
12363 if (! is_end_of_line
[(unsigned char) *input_line_pointer
])
12365 if (S_IS_DEFINED (symbolP
))
12367 as_bad ("ignoring attempt to redefine symbol %s",
12368 S_GET_NAME (symbolP
));
12369 ignore_rest_of_line ();
12373 if (*input_line_pointer
== ',')
12375 ++input_line_pointer
;
12376 SKIP_WHITESPACE ();
12380 if (exp
.X_op
!= O_symbol
)
12382 as_bad ("bad .weakext directive");
12383 ignore_rest_of_line ();
12386 symbol_set_value_expression (symbolP
, &exp
);
12389 demand_empty_rest_of_line ();
12392 /* Parse a register string into a number. Called from the ECOFF code
12393 to parse .frame. The argument is non-zero if this is the frame
12394 register, so that we can record it in mips_frame_reg. */
12397 tc_get_register (int frame
)
12401 SKIP_WHITESPACE ();
12402 if (*input_line_pointer
++ != '$')
12404 as_warn (_("expected `$'"));
12407 else if (ISDIGIT (*input_line_pointer
))
12409 reg
= get_absolute_expression ();
12410 if (reg
< 0 || reg
>= 32)
12412 as_warn (_("Bad register number"));
12418 if (strncmp (input_line_pointer
, "ra", 2) == 0)
12421 input_line_pointer
+= 2;
12423 else if (strncmp (input_line_pointer
, "fp", 2) == 0)
12426 input_line_pointer
+= 2;
12428 else if (strncmp (input_line_pointer
, "sp", 2) == 0)
12431 input_line_pointer
+= 2;
12433 else if (strncmp (input_line_pointer
, "gp", 2) == 0)
12436 input_line_pointer
+= 2;
12438 else if (strncmp (input_line_pointer
, "at", 2) == 0)
12441 input_line_pointer
+= 2;
12443 else if (strncmp (input_line_pointer
, "kt0", 3) == 0)
12446 input_line_pointer
+= 3;
12448 else if (strncmp (input_line_pointer
, "kt1", 3) == 0)
12451 input_line_pointer
+= 3;
12453 else if (strncmp (input_line_pointer
, "zero", 4) == 0)
12456 input_line_pointer
+= 4;
12460 as_warn (_("Unrecognized register name"));
12462 while (ISALNUM(*input_line_pointer
))
12463 input_line_pointer
++;
12468 mips_frame_reg
= reg
!= 0 ? reg
: SP
;
12469 mips_frame_reg_valid
= 1;
12470 mips_cprestore_valid
= 0;
12476 md_section_align (asection
*seg
, valueT addr
)
12478 int align
= bfd_get_section_alignment (stdoutput
, seg
);
12481 /* We don't need to align ELF sections to the full alignment.
12482 However, Irix 5 may prefer that we align them at least to a 16
12483 byte boundary. We don't bother to align the sections if we are
12484 targeted for an embedded system. */
12485 if (strcmp (TARGET_OS
, "elf") == 0)
12491 return ((addr
+ (1 << align
) - 1) & (-1 << align
));
12494 /* Utility routine, called from above as well. If called while the
12495 input file is still being read, it's only an approximation. (For
12496 example, a symbol may later become defined which appeared to be
12497 undefined earlier.) */
12500 nopic_need_relax (symbolS
*sym
, int before_relaxing
)
12505 if (g_switch_value
> 0)
12507 const char *symname
;
12510 /* Find out whether this symbol can be referenced off the $gp
12511 register. It can be if it is smaller than the -G size or if
12512 it is in the .sdata or .sbss section. Certain symbols can
12513 not be referenced off the $gp, although it appears as though
12515 symname
= S_GET_NAME (sym
);
12516 if (symname
!= (const char *) NULL
12517 && (strcmp (symname
, "eprol") == 0
12518 || strcmp (symname
, "etext") == 0
12519 || strcmp (symname
, "_gp") == 0
12520 || strcmp (symname
, "edata") == 0
12521 || strcmp (symname
, "_fbss") == 0
12522 || strcmp (symname
, "_fdata") == 0
12523 || strcmp (symname
, "_ftext") == 0
12524 || strcmp (symname
, "end") == 0
12525 || strcmp (symname
, "_gp_disp") == 0))
12527 else if ((! S_IS_DEFINED (sym
) || S_IS_COMMON (sym
))
12529 #ifndef NO_ECOFF_DEBUGGING
12530 || (symbol_get_obj (sym
)->ecoff_extern_size
!= 0
12531 && (symbol_get_obj (sym
)->ecoff_extern_size
12532 <= g_switch_value
))
12534 /* We must defer this decision until after the whole
12535 file has been read, since there might be a .extern
12536 after the first use of this symbol. */
12537 || (before_relaxing
12538 #ifndef NO_ECOFF_DEBUGGING
12539 && symbol_get_obj (sym
)->ecoff_extern_size
== 0
12541 && S_GET_VALUE (sym
) == 0)
12542 || (S_GET_VALUE (sym
) != 0
12543 && S_GET_VALUE (sym
) <= g_switch_value
)))
12547 const char *segname
;
12549 segname
= segment_name (S_GET_SEGMENT (sym
));
12550 assert (strcmp (segname
, ".lit8") != 0
12551 && strcmp (segname
, ".lit4") != 0);
12552 change
= (strcmp (segname
, ".sdata") != 0
12553 && strcmp (segname
, ".sbss") != 0
12554 && strncmp (segname
, ".sdata.", 7) != 0
12555 && strncmp (segname
, ".gnu.linkonce.s.", 16) != 0);
12560 /* We are not optimizing for the $gp register. */
12565 /* Return true if the given symbol should be considered local for SVR4 PIC. */
12568 pic_need_relax (symbolS
*sym
, asection
*segtype
)
12571 bfd_boolean linkonce
;
12573 /* Handle the case of a symbol equated to another symbol. */
12574 while (symbol_equated_reloc_p (sym
))
12578 /* It's possible to get a loop here in a badly written
12580 n
= symbol_get_value_expression (sym
)->X_add_symbol
;
12586 symsec
= S_GET_SEGMENT (sym
);
12588 /* duplicate the test for LINK_ONCE sections as in adjust_reloc_syms */
12590 if (symsec
!= segtype
&& ! S_IS_LOCAL (sym
))
12592 if ((bfd_get_section_flags (stdoutput
, symsec
) & SEC_LINK_ONCE
)
12596 /* The GNU toolchain uses an extension for ELF: a section
12597 beginning with the magic string .gnu.linkonce is a linkonce
12599 if (strncmp (segment_name (symsec
), ".gnu.linkonce",
12600 sizeof ".gnu.linkonce" - 1) == 0)
12604 /* This must duplicate the test in adjust_reloc_syms. */
12605 return (symsec
!= &bfd_und_section
12606 && symsec
!= &bfd_abs_section
12607 && ! bfd_is_com_section (symsec
)
12610 /* A global or weak symbol is treated as external. */
12611 && (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
12612 || (! S_IS_WEAK (sym
) && ! S_IS_EXTERNAL (sym
)))
12618 /* Given a mips16 variant frag FRAGP, return non-zero if it needs an
12619 extended opcode. SEC is the section the frag is in. */
12622 mips16_extended_frag (fragS
*fragp
, asection
*sec
, long stretch
)
12625 register const struct mips16_immed_operand
*op
;
12627 int mintiny
, maxtiny
;
12631 if (RELAX_MIPS16_USER_SMALL (fragp
->fr_subtype
))
12633 if (RELAX_MIPS16_USER_EXT (fragp
->fr_subtype
))
12636 type
= RELAX_MIPS16_TYPE (fragp
->fr_subtype
);
12637 op
= mips16_immed_operands
;
12638 while (op
->type
!= type
)
12641 assert (op
< mips16_immed_operands
+ MIPS16_NUM_IMMED
);
12646 if (type
== '<' || type
== '>' || type
== '[' || type
== ']')
12649 maxtiny
= 1 << op
->nbits
;
12654 maxtiny
= (1 << op
->nbits
) - 1;
12659 mintiny
= - (1 << (op
->nbits
- 1));
12660 maxtiny
= (1 << (op
->nbits
- 1)) - 1;
12663 sym_frag
= symbol_get_frag (fragp
->fr_symbol
);
12664 val
= S_GET_VALUE (fragp
->fr_symbol
);
12665 symsec
= S_GET_SEGMENT (fragp
->fr_symbol
);
12671 /* We won't have the section when we are called from
12672 mips_relax_frag. However, we will always have been called
12673 from md_estimate_size_before_relax first. If this is a
12674 branch to a different section, we mark it as such. If SEC is
12675 NULL, and the frag is not marked, then it must be a branch to
12676 the same section. */
12679 if (RELAX_MIPS16_LONG_BRANCH (fragp
->fr_subtype
))
12684 /* Must have been called from md_estimate_size_before_relax. */
12687 fragp
->fr_subtype
=
12688 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
12690 /* FIXME: We should support this, and let the linker
12691 catch branches and loads that are out of range. */
12692 as_bad_where (fragp
->fr_file
, fragp
->fr_line
,
12693 _("unsupported PC relative reference to different section"));
12697 if (fragp
!= sym_frag
&& sym_frag
->fr_address
== 0)
12698 /* Assume non-extended on the first relaxation pass.
12699 The address we have calculated will be bogus if this is
12700 a forward branch to another frag, as the forward frag
12701 will have fr_address == 0. */
12705 /* In this case, we know for sure that the symbol fragment is in
12706 the same section. If the relax_marker of the symbol fragment
12707 differs from the relax_marker of this fragment, we have not
12708 yet adjusted the symbol fragment fr_address. We want to add
12709 in STRETCH in order to get a better estimate of the address.
12710 This particularly matters because of the shift bits. */
12712 && sym_frag
->relax_marker
!= fragp
->relax_marker
)
12716 /* Adjust stretch for any alignment frag. Note that if have
12717 been expanding the earlier code, the symbol may be
12718 defined in what appears to be an earlier frag. FIXME:
12719 This doesn't handle the fr_subtype field, which specifies
12720 a maximum number of bytes to skip when doing an
12722 for (f
= fragp
; f
!= NULL
&& f
!= sym_frag
; f
= f
->fr_next
)
12724 if (f
->fr_type
== rs_align
|| f
->fr_type
== rs_align_code
)
12727 stretch
= - ((- stretch
)
12728 & ~ ((1 << (int) f
->fr_offset
) - 1));
12730 stretch
&= ~ ((1 << (int) f
->fr_offset
) - 1);
12739 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
12741 /* The base address rules are complicated. The base address of
12742 a branch is the following instruction. The base address of a
12743 PC relative load or add is the instruction itself, but if it
12744 is in a delay slot (in which case it can not be extended) use
12745 the address of the instruction whose delay slot it is in. */
12746 if (type
== 'p' || type
== 'q')
12750 /* If we are currently assuming that this frag should be
12751 extended, then, the current address is two bytes
12753 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
12756 /* Ignore the low bit in the target, since it will be set
12757 for a text label. */
12758 if ((val
& 1) != 0)
12761 else if (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
))
12763 else if (RELAX_MIPS16_DSLOT (fragp
->fr_subtype
))
12766 val
-= addr
& ~ ((1 << op
->shift
) - 1);
12768 /* Branch offsets have an implicit 0 in the lowest bit. */
12769 if (type
== 'p' || type
== 'q')
12772 /* If any of the shifted bits are set, we must use an extended
12773 opcode. If the address depends on the size of this
12774 instruction, this can lead to a loop, so we arrange to always
12775 use an extended opcode. We only check this when we are in
12776 the main relaxation loop, when SEC is NULL. */
12777 if ((val
& ((1 << op
->shift
) - 1)) != 0 && sec
== NULL
)
12779 fragp
->fr_subtype
=
12780 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
12784 /* If we are about to mark a frag as extended because the value
12785 is precisely maxtiny + 1, then there is a chance of an
12786 infinite loop as in the following code:
12791 In this case when the la is extended, foo is 0x3fc bytes
12792 away, so the la can be shrunk, but then foo is 0x400 away, so
12793 the la must be extended. To avoid this loop, we mark the
12794 frag as extended if it was small, and is about to become
12795 extended with a value of maxtiny + 1. */
12796 if (val
== ((maxtiny
+ 1) << op
->shift
)
12797 && ! RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
)
12800 fragp
->fr_subtype
=
12801 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
12805 else if (symsec
!= absolute_section
&& sec
!= NULL
)
12806 as_bad_where (fragp
->fr_file
, fragp
->fr_line
, _("unsupported relocation"));
12808 if ((val
& ((1 << op
->shift
) - 1)) != 0
12809 || val
< (mintiny
<< op
->shift
)
12810 || val
> (maxtiny
<< op
->shift
))
12816 /* Compute the length of a branch sequence, and adjust the
12817 RELAX_BRANCH_TOOFAR bit accordingly. If FRAGP is NULL, the
12818 worst-case length is computed, with UPDATE being used to indicate
12819 whether an unconditional (-1), branch-likely (+1) or regular (0)
12820 branch is to be computed. */
12822 relaxed_branch_length (fragS
*fragp
, asection
*sec
, int update
)
12824 bfd_boolean toofar
;
12828 && S_IS_DEFINED (fragp
->fr_symbol
)
12829 && sec
== S_GET_SEGMENT (fragp
->fr_symbol
))
12834 val
= S_GET_VALUE (fragp
->fr_symbol
) + fragp
->fr_offset
;
12836 addr
= fragp
->fr_address
+ fragp
->fr_fix
+ 4;
12840 toofar
= val
< - (0x8000 << 2) || val
>= (0x8000 << 2);
12843 /* If the symbol is not defined or it's in a different segment,
12844 assume the user knows what's going on and emit a short
12850 if (fragp
&& update
&& toofar
!= RELAX_BRANCH_TOOFAR (fragp
->fr_subtype
))
12852 = RELAX_BRANCH_ENCODE (RELAX_BRANCH_UNCOND (fragp
->fr_subtype
),
12853 RELAX_BRANCH_LIKELY (fragp
->fr_subtype
),
12854 RELAX_BRANCH_LINK (fragp
->fr_subtype
),
12860 if (fragp
? RELAX_BRANCH_LIKELY (fragp
->fr_subtype
) : (update
> 0))
12863 if (mips_pic
!= NO_PIC
)
12865 /* Additional space for PIC loading of target address. */
12867 if (mips_opts
.isa
== ISA_MIPS1
)
12868 /* Additional space for $at-stabilizing nop. */
12872 /* If branch is conditional. */
12873 if (fragp
? !RELAX_BRANCH_UNCOND (fragp
->fr_subtype
) : (update
>= 0))
12880 /* Estimate the size of a frag before relaxing. Unless this is the
12881 mips16, we are not really relaxing here, and the final size is
12882 encoded in the subtype information. For the mips16, we have to
12883 decide whether we are using an extended opcode or not. */
12886 md_estimate_size_before_relax (fragS
*fragp
, asection
*segtype
)
12890 if (RELAX_BRANCH_P (fragp
->fr_subtype
))
12893 fragp
->fr_var
= relaxed_branch_length (fragp
, segtype
, FALSE
);
12895 return fragp
->fr_var
;
12898 if (RELAX_MIPS16_P (fragp
->fr_subtype
))
12899 /* We don't want to modify the EXTENDED bit here; it might get us
12900 into infinite loops. We change it only in mips_relax_frag(). */
12901 return (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
) ? 4 : 2);
12903 if (mips_pic
== NO_PIC
)
12904 change
= nopic_need_relax (fragp
->fr_symbol
, 0);
12905 else if (mips_pic
== SVR4_PIC
)
12906 change
= pic_need_relax (fragp
->fr_symbol
, segtype
);
12912 fragp
->fr_subtype
|= RELAX_USE_SECOND
;
12913 return -RELAX_FIRST (fragp
->fr_subtype
);
12916 return -RELAX_SECOND (fragp
->fr_subtype
);
12919 /* This is called to see whether a reloc against a defined symbol
12920 should be converted into a reloc against a section. */
12923 mips_fix_adjustable (fixS
*fixp
)
12925 /* Don't adjust MIPS16 jump relocations, so we don't have to worry
12926 about the format of the offset in the .o file. */
12927 if (fixp
->fx_r_type
== BFD_RELOC_MIPS16_JMP
)
12930 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
12931 || fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
12934 if (fixp
->fx_addsy
== NULL
)
12937 /* If symbol SYM is in a mergeable section, relocations of the form
12938 SYM + 0 can usually be made section-relative. The mergeable data
12939 is then identified by the section offset rather than by the symbol.
12941 However, if we're generating REL LO16 relocations, the offset is split
12942 between the LO16 and parterning high part relocation. The linker will
12943 need to recalculate the complete offset in order to correctly identify
12946 The linker has traditionally not looked for the parterning high part
12947 relocation, and has thus allowed orphaned R_MIPS_LO16 relocations to be
12948 placed anywhere. Rather than break backwards compatibility by changing
12949 this, it seems better not to force the issue, and instead keep the
12950 original symbol. This will work with either linker behavior. */
12951 if ((fixp
->fx_r_type
== BFD_RELOC_LO16
12952 || fixp
->fx_r_type
== BFD_RELOC_MIPS16_LO16
12953 || reloc_needs_lo_p (fixp
->fx_r_type
))
12954 && HAVE_IN_PLACE_ADDENDS
12955 && (S_GET_SEGMENT (fixp
->fx_addsy
)->flags
& SEC_MERGE
) != 0)
12959 /* Don't adjust relocations against mips16 symbols, so that the linker
12960 can find them if it needs to set up a stub. */
12961 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
12962 && S_GET_OTHER (fixp
->fx_addsy
) == STO_MIPS16
12963 && fixp
->fx_subsy
== NULL
)
12970 /* Translate internal representation of relocation info to BFD target
12974 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
, fixS
*fixp
)
12976 static arelent
*retval
[4];
12978 bfd_reloc_code_real_type code
;
12980 memset (retval
, 0, sizeof(retval
));
12981 reloc
= retval
[0] = (arelent
*) xcalloc (1, sizeof (arelent
));
12982 reloc
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
12983 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
12984 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
12986 assert (! fixp
->fx_pcrel
);
12987 reloc
->addend
= fixp
->fx_addnumber
;
12989 /* Since the old MIPS ELF ABI uses Rel instead of Rela, encode the vtable
12990 entry to be used in the relocation's section offset. */
12991 if (! HAVE_NEWABI
&& fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
12993 reloc
->address
= reloc
->addend
;
12997 code
= fixp
->fx_r_type
;
12999 /* To support a PC relative reloc, we used a Cygnus extension.
13000 We check for that here to make sure that we don't let such a
13001 reloc escape normally. (FIXME: This was formerly used by
13002 embedded-PIC support, but is now used by branch handling in
13003 general. That probably should be fixed.) */
13004 if ((OUTPUT_FLAVOR
== bfd_target_ecoff_flavour
13005 || OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
13006 && code
== BFD_RELOC_16_PCREL_S2
)
13007 reloc
->howto
= NULL
;
13009 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
13011 if (reloc
->howto
== NULL
)
13013 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
13014 _("Can not represent %s relocation in this object file format"),
13015 bfd_get_reloc_code_name (code
));
13022 /* Relax a machine dependent frag. This returns the amount by which
13023 the current size of the frag should change. */
13026 mips_relax_frag (asection
*sec
, fragS
*fragp
, long stretch
)
13028 if (RELAX_BRANCH_P (fragp
->fr_subtype
))
13030 offsetT old_var
= fragp
->fr_var
;
13032 fragp
->fr_var
= relaxed_branch_length (fragp
, sec
, TRUE
);
13034 return fragp
->fr_var
- old_var
;
13037 if (! RELAX_MIPS16_P (fragp
->fr_subtype
))
13040 if (mips16_extended_frag (fragp
, NULL
, stretch
))
13042 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
13044 fragp
->fr_subtype
= RELAX_MIPS16_MARK_EXTENDED (fragp
->fr_subtype
);
13049 if (! RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
13051 fragp
->fr_subtype
= RELAX_MIPS16_CLEAR_EXTENDED (fragp
->fr_subtype
);
13058 /* Convert a machine dependent frag. */
13061 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
, segT asec
, fragS
*fragp
)
13063 if (RELAX_BRANCH_P (fragp
->fr_subtype
))
13066 unsigned long insn
;
13070 buf
= (bfd_byte
*)fragp
->fr_literal
+ fragp
->fr_fix
;
13072 if (target_big_endian
)
13073 insn
= bfd_getb32 (buf
);
13075 insn
= bfd_getl32 (buf
);
13077 if (!RELAX_BRANCH_TOOFAR (fragp
->fr_subtype
))
13079 /* We generate a fixup instead of applying it right now
13080 because, if there are linker relaxations, we're going to
13081 need the relocations. */
13082 exp
.X_op
= O_symbol
;
13083 exp
.X_add_symbol
= fragp
->fr_symbol
;
13084 exp
.X_add_number
= fragp
->fr_offset
;
13086 fixp
= fix_new_exp (fragp
, buf
- (bfd_byte
*)fragp
->fr_literal
,
13088 BFD_RELOC_16_PCREL_S2
);
13089 fixp
->fx_file
= fragp
->fr_file
;
13090 fixp
->fx_line
= fragp
->fr_line
;
13092 md_number_to_chars ((char *) buf
, insn
, 4);
13099 as_warn_where (fragp
->fr_file
, fragp
->fr_line
,
13100 _("relaxed out-of-range branch into a jump"));
13102 if (RELAX_BRANCH_UNCOND (fragp
->fr_subtype
))
13105 if (!RELAX_BRANCH_LIKELY (fragp
->fr_subtype
))
13107 /* Reverse the branch. */
13108 switch ((insn
>> 28) & 0xf)
13111 /* bc[0-3][tf]l? and bc1any[24][ft] instructions can
13112 have the condition reversed by tweaking a single
13113 bit, and their opcodes all have 0x4???????. */
13114 assert ((insn
& 0xf1000000) == 0x41000000);
13115 insn
^= 0x00010000;
13119 /* bltz 0x04000000 bgez 0x04010000
13120 bltzal 0x04100000 bgezal 0x04110000 */
13121 assert ((insn
& 0xfc0e0000) == 0x04000000);
13122 insn
^= 0x00010000;
13126 /* beq 0x10000000 bne 0x14000000
13127 blez 0x18000000 bgtz 0x1c000000 */
13128 insn
^= 0x04000000;
13136 if (RELAX_BRANCH_LINK (fragp
->fr_subtype
))
13138 /* Clear the and-link bit. */
13139 assert ((insn
& 0xfc1c0000) == 0x04100000);
13141 /* bltzal 0x04100000 bgezal 0x04110000
13142 bltzall 0x04120000 bgezall 0x04130000 */
13143 insn
&= ~0x00100000;
13146 /* Branch over the branch (if the branch was likely) or the
13147 full jump (not likely case). Compute the offset from the
13148 current instruction to branch to. */
13149 if (RELAX_BRANCH_LIKELY (fragp
->fr_subtype
))
13153 /* How many bytes in instructions we've already emitted? */
13154 i
= buf
- (bfd_byte
*)fragp
->fr_literal
- fragp
->fr_fix
;
13155 /* How many bytes in instructions from here to the end? */
13156 i
= fragp
->fr_var
- i
;
13158 /* Convert to instruction count. */
13160 /* Branch counts from the next instruction. */
13163 /* Branch over the jump. */
13164 md_number_to_chars ((char *) buf
, insn
, 4);
13168 md_number_to_chars ((char *) buf
, 0, 4);
13171 if (RELAX_BRANCH_LIKELY (fragp
->fr_subtype
))
13173 /* beql $0, $0, 2f */
13175 /* Compute the PC offset from the current instruction to
13176 the end of the variable frag. */
13177 /* How many bytes in instructions we've already emitted? */
13178 i
= buf
- (bfd_byte
*)fragp
->fr_literal
- fragp
->fr_fix
;
13179 /* How many bytes in instructions from here to the end? */
13180 i
= fragp
->fr_var
- i
;
13181 /* Convert to instruction count. */
13183 /* Don't decrement i, because we want to branch over the
13187 md_number_to_chars ((char *) buf
, insn
, 4);
13190 md_number_to_chars ((char *) buf
, 0, 4);
13195 if (mips_pic
== NO_PIC
)
13198 insn
= (RELAX_BRANCH_LINK (fragp
->fr_subtype
)
13199 ? 0x0c000000 : 0x08000000);
13200 exp
.X_op
= O_symbol
;
13201 exp
.X_add_symbol
= fragp
->fr_symbol
;
13202 exp
.X_add_number
= fragp
->fr_offset
;
13204 fixp
= fix_new_exp (fragp
, buf
- (bfd_byte
*)fragp
->fr_literal
,
13205 4, &exp
, 0, BFD_RELOC_MIPS_JMP
);
13206 fixp
->fx_file
= fragp
->fr_file
;
13207 fixp
->fx_line
= fragp
->fr_line
;
13209 md_number_to_chars ((char *) buf
, insn
, 4);
13214 /* lw/ld $at, <sym>($gp) R_MIPS_GOT16 */
13215 insn
= HAVE_64BIT_ADDRESSES
? 0xdf810000 : 0x8f810000;
13216 exp
.X_op
= O_symbol
;
13217 exp
.X_add_symbol
= fragp
->fr_symbol
;
13218 exp
.X_add_number
= fragp
->fr_offset
;
13220 if (fragp
->fr_offset
)
13222 exp
.X_add_symbol
= make_expr_symbol (&exp
);
13223 exp
.X_add_number
= 0;
13226 fixp
= fix_new_exp (fragp
, buf
- (bfd_byte
*)fragp
->fr_literal
,
13227 4, &exp
, 0, BFD_RELOC_MIPS_GOT16
);
13228 fixp
->fx_file
= fragp
->fr_file
;
13229 fixp
->fx_line
= fragp
->fr_line
;
13231 md_number_to_chars ((char *) buf
, insn
, 4);
13234 if (mips_opts
.isa
== ISA_MIPS1
)
13237 md_number_to_chars ((char *) buf
, 0, 4);
13241 /* d/addiu $at, $at, <sym> R_MIPS_LO16 */
13242 insn
= HAVE_64BIT_ADDRESSES
? 0x64210000 : 0x24210000;
13244 fixp
= fix_new_exp (fragp
, buf
- (bfd_byte
*)fragp
->fr_literal
,
13245 4, &exp
, 0, BFD_RELOC_LO16
);
13246 fixp
->fx_file
= fragp
->fr_file
;
13247 fixp
->fx_line
= fragp
->fr_line
;
13249 md_number_to_chars ((char *) buf
, insn
, 4);
13253 if (RELAX_BRANCH_LINK (fragp
->fr_subtype
))
13258 md_number_to_chars ((char *) buf
, insn
, 4);
13263 assert (buf
== (bfd_byte
*)fragp
->fr_literal
13264 + fragp
->fr_fix
+ fragp
->fr_var
);
13266 fragp
->fr_fix
+= fragp
->fr_var
;
13271 if (RELAX_MIPS16_P (fragp
->fr_subtype
))
13274 register const struct mips16_immed_operand
*op
;
13275 bfd_boolean small
, ext
;
13278 unsigned long insn
;
13279 bfd_boolean use_extend
;
13280 unsigned short extend
;
13282 type
= RELAX_MIPS16_TYPE (fragp
->fr_subtype
);
13283 op
= mips16_immed_operands
;
13284 while (op
->type
!= type
)
13287 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
13298 resolve_symbol_value (fragp
->fr_symbol
);
13299 val
= S_GET_VALUE (fragp
->fr_symbol
);
13304 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
13306 /* The rules for the base address of a PC relative reloc are
13307 complicated; see mips16_extended_frag. */
13308 if (type
== 'p' || type
== 'q')
13313 /* Ignore the low bit in the target, since it will be
13314 set for a text label. */
13315 if ((val
& 1) != 0)
13318 else if (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
))
13320 else if (RELAX_MIPS16_DSLOT (fragp
->fr_subtype
))
13323 addr
&= ~ (addressT
) ((1 << op
->shift
) - 1);
13326 /* Make sure the section winds up with the alignment we have
13329 record_alignment (asec
, op
->shift
);
13333 && (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
)
13334 || RELAX_MIPS16_DSLOT (fragp
->fr_subtype
)))
13335 as_warn_where (fragp
->fr_file
, fragp
->fr_line
,
13336 _("extended instruction in delay slot"));
13338 buf
= (bfd_byte
*) (fragp
->fr_literal
+ fragp
->fr_fix
);
13340 if (target_big_endian
)
13341 insn
= bfd_getb16 (buf
);
13343 insn
= bfd_getl16 (buf
);
13345 mips16_immed (fragp
->fr_file
, fragp
->fr_line
, type
, val
,
13346 RELAX_MIPS16_USER_EXT (fragp
->fr_subtype
),
13347 small
, ext
, &insn
, &use_extend
, &extend
);
13351 md_number_to_chars ((char *) buf
, 0xf000 | extend
, 2);
13352 fragp
->fr_fix
+= 2;
13356 md_number_to_chars ((char *) buf
, insn
, 2);
13357 fragp
->fr_fix
+= 2;
13365 first
= RELAX_FIRST (fragp
->fr_subtype
);
13366 second
= RELAX_SECOND (fragp
->fr_subtype
);
13367 fixp
= (fixS
*) fragp
->fr_opcode
;
13369 /* Possibly emit a warning if we've chosen the longer option. */
13370 if (((fragp
->fr_subtype
& RELAX_USE_SECOND
) != 0)
13371 == ((fragp
->fr_subtype
& RELAX_SECOND_LONGER
) != 0))
13373 const char *msg
= macro_warning (fragp
->fr_subtype
);
13375 as_warn_where (fragp
->fr_file
, fragp
->fr_line
, msg
);
13378 /* Go through all the fixups for the first sequence. Disable them
13379 (by marking them as done) if we're going to use the second
13380 sequence instead. */
13382 && fixp
->fx_frag
== fragp
13383 && fixp
->fx_where
< fragp
->fr_fix
- second
)
13385 if (fragp
->fr_subtype
& RELAX_USE_SECOND
)
13387 fixp
= fixp
->fx_next
;
13390 /* Go through the fixups for the second sequence. Disable them if
13391 we're going to use the first sequence, otherwise adjust their
13392 addresses to account for the relaxation. */
13393 while (fixp
&& fixp
->fx_frag
== fragp
)
13395 if (fragp
->fr_subtype
& RELAX_USE_SECOND
)
13396 fixp
->fx_where
-= first
;
13399 fixp
= fixp
->fx_next
;
13402 /* Now modify the frag contents. */
13403 if (fragp
->fr_subtype
& RELAX_USE_SECOND
)
13407 start
= fragp
->fr_literal
+ fragp
->fr_fix
- first
- second
;
13408 memmove (start
, start
+ first
, second
);
13409 fragp
->fr_fix
-= first
;
13412 fragp
->fr_fix
-= second
;
13418 /* This function is called after the relocs have been generated.
13419 We've been storing mips16 text labels as odd. Here we convert them
13420 back to even for the convenience of the debugger. */
13423 mips_frob_file_after_relocs (void)
13426 unsigned int count
, i
;
13428 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
13431 syms
= bfd_get_outsymbols (stdoutput
);
13432 count
= bfd_get_symcount (stdoutput
);
13433 for (i
= 0; i
< count
; i
++, syms
++)
13435 if (elf_symbol (*syms
)->internal_elf_sym
.st_other
== STO_MIPS16
13436 && ((*syms
)->value
& 1) != 0)
13438 (*syms
)->value
&= ~1;
13439 /* If the symbol has an odd size, it was probably computed
13440 incorrectly, so adjust that as well. */
13441 if ((elf_symbol (*syms
)->internal_elf_sym
.st_size
& 1) != 0)
13442 ++elf_symbol (*syms
)->internal_elf_sym
.st_size
;
13449 /* This function is called whenever a label is defined. It is used
13450 when handling branch delays; if a branch has a label, we assume we
13451 can not move it. */
13454 mips_define_label (symbolS
*sym
)
13456 struct insn_label_list
*l
;
13458 if (free_insn_labels
== NULL
)
13459 l
= (struct insn_label_list
*) xmalloc (sizeof *l
);
13462 l
= free_insn_labels
;
13463 free_insn_labels
= l
->next
;
13467 l
->next
= insn_labels
;
13471 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13473 /* Some special processing for a MIPS ELF file. */
13476 mips_elf_final_processing (void)
13478 /* Write out the register information. */
13479 if (mips_abi
!= N64_ABI
)
13483 s
.ri_gprmask
= mips_gprmask
;
13484 s
.ri_cprmask
[0] = mips_cprmask
[0];
13485 s
.ri_cprmask
[1] = mips_cprmask
[1];
13486 s
.ri_cprmask
[2] = mips_cprmask
[2];
13487 s
.ri_cprmask
[3] = mips_cprmask
[3];
13488 /* The gp_value field is set by the MIPS ELF backend. */
13490 bfd_mips_elf32_swap_reginfo_out (stdoutput
, &s
,
13491 ((Elf32_External_RegInfo
*)
13492 mips_regmask_frag
));
13496 Elf64_Internal_RegInfo s
;
13498 s
.ri_gprmask
= mips_gprmask
;
13500 s
.ri_cprmask
[0] = mips_cprmask
[0];
13501 s
.ri_cprmask
[1] = mips_cprmask
[1];
13502 s
.ri_cprmask
[2] = mips_cprmask
[2];
13503 s
.ri_cprmask
[3] = mips_cprmask
[3];
13504 /* The gp_value field is set by the MIPS ELF backend. */
13506 bfd_mips_elf64_swap_reginfo_out (stdoutput
, &s
,
13507 ((Elf64_External_RegInfo
*)
13508 mips_regmask_frag
));
13511 /* Set the MIPS ELF flag bits. FIXME: There should probably be some
13512 sort of BFD interface for this. */
13513 if (mips_any_noreorder
)
13514 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_NOREORDER
;
13515 if (mips_pic
!= NO_PIC
)
13517 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_PIC
;
13518 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_CPIC
;
13521 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_CPIC
;
13523 /* Set MIPS ELF flags for ASEs. */
13524 /* We may need to define a new flag for DSP ASE, and set this flag when
13525 file_ase_dsp is true. */
13526 if (file_ase_mips16
)
13527 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ARCH_ASE_M16
;
13528 #if 0 /* XXX FIXME */
13529 if (file_ase_mips3d
)
13530 elf_elfheader (stdoutput
)->e_flags
|= ???;
13533 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ARCH_ASE_MDMX
;
13535 /* Set the MIPS ELF ABI flags. */
13536 if (mips_abi
== O32_ABI
&& USE_E_MIPS_ABI_O32
)
13537 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_O32
;
13538 else if (mips_abi
== O64_ABI
)
13539 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_O64
;
13540 else if (mips_abi
== EABI_ABI
)
13542 if (!file_mips_gp32
)
13543 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_EABI64
;
13545 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_EABI32
;
13547 else if (mips_abi
== N32_ABI
)
13548 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ABI2
;
13550 /* Nothing to do for N64_ABI. */
13552 if (mips_32bitmode
)
13553 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_32BITMODE
;
13556 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */
13558 typedef struct proc
{
13560 symbolS
*func_end_sym
;
13561 unsigned long reg_mask
;
13562 unsigned long reg_offset
;
13563 unsigned long fpreg_mask
;
13564 unsigned long fpreg_offset
;
13565 unsigned long frame_offset
;
13566 unsigned long frame_reg
;
13567 unsigned long pc_reg
;
13570 static procS cur_proc
;
13571 static procS
*cur_proc_ptr
;
13572 static int numprocs
;
13574 /* Fill in an rs_align_code fragment. */
13577 mips_handle_align (fragS
*fragp
)
13579 if (fragp
->fr_type
!= rs_align_code
)
13582 if (mips_opts
.mips16
)
13584 static const unsigned char be_nop
[] = { 0x65, 0x00 };
13585 static const unsigned char le_nop
[] = { 0x00, 0x65 };
13590 bytes
= fragp
->fr_next
->fr_address
- fragp
->fr_address
- fragp
->fr_fix
;
13591 p
= fragp
->fr_literal
+ fragp
->fr_fix
;
13599 memcpy (p
, (target_big_endian
? be_nop
: le_nop
), 2);
13603 /* For mips32, a nop is a zero, which we trivially get by doing nothing. */
13607 md_obj_begin (void)
13614 /* check for premature end, nesting errors, etc */
13616 as_warn (_("missing .end at end of assembly"));
13625 if (*input_line_pointer
== '-')
13627 ++input_line_pointer
;
13630 if (!ISDIGIT (*input_line_pointer
))
13631 as_bad (_("expected simple number"));
13632 if (input_line_pointer
[0] == '0')
13634 if (input_line_pointer
[1] == 'x')
13636 input_line_pointer
+= 2;
13637 while (ISXDIGIT (*input_line_pointer
))
13640 val
|= hex_value (*input_line_pointer
++);
13642 return negative
? -val
: val
;
13646 ++input_line_pointer
;
13647 while (ISDIGIT (*input_line_pointer
))
13650 val
|= *input_line_pointer
++ - '0';
13652 return negative
? -val
: val
;
13655 if (!ISDIGIT (*input_line_pointer
))
13657 printf (_(" *input_line_pointer == '%c' 0x%02x\n"),
13658 *input_line_pointer
, *input_line_pointer
);
13659 as_warn (_("invalid number"));
13662 while (ISDIGIT (*input_line_pointer
))
13665 val
+= *input_line_pointer
++ - '0';
13667 return negative
? -val
: val
;
13670 /* The .file directive; just like the usual .file directive, but there
13671 is an initial number which is the ECOFF file index. In the non-ECOFF
13672 case .file implies DWARF-2. */
13675 s_mips_file (int x ATTRIBUTE_UNUSED
)
13677 static int first_file_directive
= 0;
13679 if (ECOFF_DEBUGGING
)
13688 filename
= dwarf2_directive_file (0);
13690 /* Versions of GCC up to 3.1 start files with a ".file"
13691 directive even for stabs output. Make sure that this
13692 ".file" is handled. Note that you need a version of GCC
13693 after 3.1 in order to support DWARF-2 on MIPS. */
13694 if (filename
!= NULL
&& ! first_file_directive
)
13696 (void) new_logical_line (filename
, -1);
13697 s_app_file_string (filename
, 0);
13699 first_file_directive
= 1;
13703 /* The .loc directive, implying DWARF-2. */
13706 s_mips_loc (int x ATTRIBUTE_UNUSED
)
13708 if (!ECOFF_DEBUGGING
)
13709 dwarf2_directive_loc (0);
13712 /* The .end directive. */
13715 s_mips_end (int x ATTRIBUTE_UNUSED
)
13719 /* Following functions need their own .frame and .cprestore directives. */
13720 mips_frame_reg_valid
= 0;
13721 mips_cprestore_valid
= 0;
13723 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
13726 demand_empty_rest_of_line ();
13731 if ((bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) == 0)
13732 as_warn (_(".end not in text section"));
13736 as_warn (_(".end directive without a preceding .ent directive."));
13737 demand_empty_rest_of_line ();
13743 assert (S_GET_NAME (p
));
13744 if (strcmp (S_GET_NAME (p
), S_GET_NAME (cur_proc_ptr
->func_sym
)))
13745 as_warn (_(".end symbol does not match .ent symbol."));
13747 if (debug_type
== DEBUG_STABS
)
13748 stabs_generate_asm_endfunc (S_GET_NAME (p
),
13752 as_warn (_(".end directive missing or unknown symbol"));
13755 /* Create an expression to calculate the size of the function. */
13756 if (p
&& cur_proc_ptr
)
13758 OBJ_SYMFIELD_TYPE
*obj
= symbol_get_obj (p
);
13759 expressionS
*exp
= xmalloc (sizeof (expressionS
));
13762 exp
->X_op
= O_subtract
;
13763 exp
->X_add_symbol
= symbol_temp_new_now ();
13764 exp
->X_op_symbol
= p
;
13765 exp
->X_add_number
= 0;
13767 cur_proc_ptr
->func_end_sym
= exp
->X_add_symbol
;
13770 /* Generate a .pdr section. */
13771 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
&& ! ECOFF_DEBUGGING
13774 segT saved_seg
= now_seg
;
13775 subsegT saved_subseg
= now_subseg
;
13780 dot
= frag_now_fix ();
13782 #ifdef md_flush_pending_output
13783 md_flush_pending_output ();
13787 subseg_set (pdr_seg
, 0);
13789 /* Write the symbol. */
13790 exp
.X_op
= O_symbol
;
13791 exp
.X_add_symbol
= p
;
13792 exp
.X_add_number
= 0;
13793 emit_expr (&exp
, 4);
13795 fragp
= frag_more (7 * 4);
13797 md_number_to_chars (fragp
, cur_proc_ptr
->reg_mask
, 4);
13798 md_number_to_chars (fragp
+ 4, cur_proc_ptr
->reg_offset
, 4);
13799 md_number_to_chars (fragp
+ 8, cur_proc_ptr
->fpreg_mask
, 4);
13800 md_number_to_chars (fragp
+ 12, cur_proc_ptr
->fpreg_offset
, 4);
13801 md_number_to_chars (fragp
+ 16, cur_proc_ptr
->frame_offset
, 4);
13802 md_number_to_chars (fragp
+ 20, cur_proc_ptr
->frame_reg
, 4);
13803 md_number_to_chars (fragp
+ 24, cur_proc_ptr
->pc_reg
, 4);
13805 subseg_set (saved_seg
, saved_subseg
);
13807 #endif /* OBJ_ELF */
13809 cur_proc_ptr
= NULL
;
13812 /* The .aent and .ent directives. */
13815 s_mips_ent (int aent
)
13819 symbolP
= get_symbol ();
13820 if (*input_line_pointer
== ',')
13821 ++input_line_pointer
;
13822 SKIP_WHITESPACE ();
13823 if (ISDIGIT (*input_line_pointer
)
13824 || *input_line_pointer
== '-')
13827 if ((bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) == 0)
13828 as_warn (_(".ent or .aent not in text section."));
13830 if (!aent
&& cur_proc_ptr
)
13831 as_warn (_("missing .end"));
13835 /* This function needs its own .frame and .cprestore directives. */
13836 mips_frame_reg_valid
= 0;
13837 mips_cprestore_valid
= 0;
13839 cur_proc_ptr
= &cur_proc
;
13840 memset (cur_proc_ptr
, '\0', sizeof (procS
));
13842 cur_proc_ptr
->func_sym
= symbolP
;
13844 symbol_get_bfdsym (symbolP
)->flags
|= BSF_FUNCTION
;
13848 if (debug_type
== DEBUG_STABS
)
13849 stabs_generate_asm_func (S_GET_NAME (symbolP
),
13850 S_GET_NAME (symbolP
));
13853 demand_empty_rest_of_line ();
13856 /* The .frame directive. If the mdebug section is present (IRIX 5 native)
13857 then ecoff.c (ecoff_directive_frame) is used. For embedded targets,
13858 s_mips_frame is used so that we can set the PDR information correctly.
13859 We can't use the ecoff routines because they make reference to the ecoff
13860 symbol table (in the mdebug section). */
13863 s_mips_frame (int ignore ATTRIBUTE_UNUSED
)
13866 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
&& ! ECOFF_DEBUGGING
)
13870 if (cur_proc_ptr
== (procS
*) NULL
)
13872 as_warn (_(".frame outside of .ent"));
13873 demand_empty_rest_of_line ();
13877 cur_proc_ptr
->frame_reg
= tc_get_register (1);
13879 SKIP_WHITESPACE ();
13880 if (*input_line_pointer
++ != ','
13881 || get_absolute_expression_and_terminator (&val
) != ',')
13883 as_warn (_("Bad .frame directive"));
13884 --input_line_pointer
;
13885 demand_empty_rest_of_line ();
13889 cur_proc_ptr
->frame_offset
= val
;
13890 cur_proc_ptr
->pc_reg
= tc_get_register (0);
13892 demand_empty_rest_of_line ();
13895 #endif /* OBJ_ELF */
13899 /* The .fmask and .mask directives. If the mdebug section is present
13900 (IRIX 5 native) then ecoff.c (ecoff_directive_mask) is used. For
13901 embedded targets, s_mips_mask is used so that we can set the PDR
13902 information correctly. We can't use the ecoff routines because they
13903 make reference to the ecoff symbol table (in the mdebug section). */
13906 s_mips_mask (int reg_type
)
13909 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
&& ! ECOFF_DEBUGGING
)
13913 if (cur_proc_ptr
== (procS
*) NULL
)
13915 as_warn (_(".mask/.fmask outside of .ent"));
13916 demand_empty_rest_of_line ();
13920 if (get_absolute_expression_and_terminator (&mask
) != ',')
13922 as_warn (_("Bad .mask/.fmask directive"));
13923 --input_line_pointer
;
13924 demand_empty_rest_of_line ();
13928 off
= get_absolute_expression ();
13930 if (reg_type
== 'F')
13932 cur_proc_ptr
->fpreg_mask
= mask
;
13933 cur_proc_ptr
->fpreg_offset
= off
;
13937 cur_proc_ptr
->reg_mask
= mask
;
13938 cur_proc_ptr
->reg_offset
= off
;
13941 demand_empty_rest_of_line ();
13944 #endif /* OBJ_ELF */
13945 s_ignore (reg_type
);
13948 /* A table describing all the processors gas knows about. Names are
13949 matched in the order listed.
13951 To ease comparison, please keep this table in the same order as
13952 gcc's mips_cpu_info_table[]. */
13953 static const struct mips_cpu_info mips_cpu_info_table
[] =
13955 /* Entries for generic ISAs */
13956 { "mips1", 1, ISA_MIPS1
, CPU_R3000
},
13957 { "mips2", 1, ISA_MIPS2
, CPU_R6000
},
13958 { "mips3", 1, ISA_MIPS3
, CPU_R4000
},
13959 { "mips4", 1, ISA_MIPS4
, CPU_R8000
},
13960 { "mips5", 1, ISA_MIPS5
, CPU_MIPS5
},
13961 { "mips32", 1, ISA_MIPS32
, CPU_MIPS32
},
13962 { "mips32r2", 1, ISA_MIPS32R2
, CPU_MIPS32R2
},
13963 { "mips64", 1, ISA_MIPS64
, CPU_MIPS64
},
13964 { "mips64r2", 1, ISA_MIPS64R2
, CPU_MIPS64R2
},
13967 { "r3000", 0, ISA_MIPS1
, CPU_R3000
},
13968 { "r2000", 0, ISA_MIPS1
, CPU_R3000
},
13969 { "r3900", 0, ISA_MIPS1
, CPU_R3900
},
13972 { "r6000", 0, ISA_MIPS2
, CPU_R6000
},
13975 { "r4000", 0, ISA_MIPS3
, CPU_R4000
},
13976 { "r4010", 0, ISA_MIPS2
, CPU_R4010
},
13977 { "vr4100", 0, ISA_MIPS3
, CPU_VR4100
},
13978 { "vr4111", 0, ISA_MIPS3
, CPU_R4111
},
13979 { "vr4120", 0, ISA_MIPS3
, CPU_VR4120
},
13980 { "vr4130", 0, ISA_MIPS3
, CPU_VR4120
},
13981 { "vr4181", 0, ISA_MIPS3
, CPU_R4111
},
13982 { "vr4300", 0, ISA_MIPS3
, CPU_R4300
},
13983 { "r4400", 0, ISA_MIPS3
, CPU_R4400
},
13984 { "r4600", 0, ISA_MIPS3
, CPU_R4600
},
13985 { "orion", 0, ISA_MIPS3
, CPU_R4600
},
13986 { "r4650", 0, ISA_MIPS3
, CPU_R4650
},
13989 { "r8000", 0, ISA_MIPS4
, CPU_R8000
},
13990 { "r10000", 0, ISA_MIPS4
, CPU_R10000
},
13991 { "r12000", 0, ISA_MIPS4
, CPU_R12000
},
13992 { "vr5000", 0, ISA_MIPS4
, CPU_R5000
},
13993 { "vr5400", 0, ISA_MIPS4
, CPU_VR5400
},
13994 { "vr5500", 0, ISA_MIPS4
, CPU_VR5500
},
13995 { "rm5200", 0, ISA_MIPS4
, CPU_R5000
},
13996 { "rm5230", 0, ISA_MIPS4
, CPU_R5000
},
13997 { "rm5231", 0, ISA_MIPS4
, CPU_R5000
},
13998 { "rm5261", 0, ISA_MIPS4
, CPU_R5000
},
13999 { "rm5721", 0, ISA_MIPS4
, CPU_R5000
},
14000 { "rm7000", 0, ISA_MIPS4
, CPU_RM7000
},
14001 { "rm9000", 0, ISA_MIPS4
, CPU_RM9000
},
14004 { "4kc", 0, ISA_MIPS32
, CPU_MIPS32
},
14005 { "4km", 0, ISA_MIPS32
, CPU_MIPS32
},
14006 { "4kp", 0, ISA_MIPS32
, CPU_MIPS32
},
14008 /* MIPS32 Release 2 */
14009 { "m4k", 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
14010 { "24k", 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
14011 { "24kc", 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
14012 { "24kf", 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
14013 { "24kx", 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
14016 { "5kc", 0, ISA_MIPS64
, CPU_MIPS64
},
14017 { "5kf", 0, ISA_MIPS64
, CPU_MIPS64
},
14018 { "20kc", 0, ISA_MIPS64
, CPU_MIPS64
},
14020 /* Broadcom SB-1 CPU core */
14021 { "sb1", 0, ISA_MIPS64
, CPU_SB1
},
14028 /* Return true if GIVEN is the same as CANONICAL, or if it is CANONICAL
14029 with a final "000" replaced by "k". Ignore case.
14031 Note: this function is shared between GCC and GAS. */
14034 mips_strict_matching_cpu_name_p (const char *canonical
, const char *given
)
14036 while (*given
!= 0 && TOLOWER (*given
) == TOLOWER (*canonical
))
14037 given
++, canonical
++;
14039 return ((*given
== 0 && *canonical
== 0)
14040 || (strcmp (canonical
, "000") == 0 && strcasecmp (given
, "k") == 0));
14044 /* Return true if GIVEN matches CANONICAL, where GIVEN is a user-supplied
14045 CPU name. We've traditionally allowed a lot of variation here.
14047 Note: this function is shared between GCC and GAS. */
14050 mips_matching_cpu_name_p (const char *canonical
, const char *given
)
14052 /* First see if the name matches exactly, or with a final "000"
14053 turned into "k". */
14054 if (mips_strict_matching_cpu_name_p (canonical
, given
))
14057 /* If not, try comparing based on numerical designation alone.
14058 See if GIVEN is an unadorned number, or 'r' followed by a number. */
14059 if (TOLOWER (*given
) == 'r')
14061 if (!ISDIGIT (*given
))
14064 /* Skip over some well-known prefixes in the canonical name,
14065 hoping to find a number there too. */
14066 if (TOLOWER (canonical
[0]) == 'v' && TOLOWER (canonical
[1]) == 'r')
14068 else if (TOLOWER (canonical
[0]) == 'r' && TOLOWER (canonical
[1]) == 'm')
14070 else if (TOLOWER (canonical
[0]) == 'r')
14073 return mips_strict_matching_cpu_name_p (canonical
, given
);
14077 /* Parse an option that takes the name of a processor as its argument.
14078 OPTION is the name of the option and CPU_STRING is the argument.
14079 Return the corresponding processor enumeration if the CPU_STRING is
14080 recognized, otherwise report an error and return null.
14082 A similar function exists in GCC. */
14084 static const struct mips_cpu_info
*
14085 mips_parse_cpu (const char *option
, const char *cpu_string
)
14087 const struct mips_cpu_info
*p
;
14089 /* 'from-abi' selects the most compatible architecture for the given
14090 ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit ABIs. For the
14091 EABIs, we have to decide whether we're using the 32-bit or 64-bit
14092 version. Look first at the -mgp options, if given, otherwise base
14093 the choice on MIPS_DEFAULT_64BIT.
14095 Treat NO_ABI like the EABIs. One reason to do this is that the
14096 plain 'mips' and 'mips64' configs have 'from-abi' as their default
14097 architecture. This code picks MIPS I for 'mips' and MIPS III for
14098 'mips64', just as we did in the days before 'from-abi'. */
14099 if (strcasecmp (cpu_string
, "from-abi") == 0)
14101 if (ABI_NEEDS_32BIT_REGS (mips_abi
))
14102 return mips_cpu_info_from_isa (ISA_MIPS1
);
14104 if (ABI_NEEDS_64BIT_REGS (mips_abi
))
14105 return mips_cpu_info_from_isa (ISA_MIPS3
);
14107 if (file_mips_gp32
>= 0)
14108 return mips_cpu_info_from_isa (file_mips_gp32
? ISA_MIPS1
: ISA_MIPS3
);
14110 return mips_cpu_info_from_isa (MIPS_DEFAULT_64BIT
14115 /* 'default' has traditionally been a no-op. Probably not very useful. */
14116 if (strcasecmp (cpu_string
, "default") == 0)
14119 for (p
= mips_cpu_info_table
; p
->name
!= 0; p
++)
14120 if (mips_matching_cpu_name_p (p
->name
, cpu_string
))
14123 as_bad ("Bad value (%s) for %s", cpu_string
, option
);
14127 /* Return the canonical processor information for ISA (a member of the
14128 ISA_MIPS* enumeration). */
14130 static const struct mips_cpu_info
*
14131 mips_cpu_info_from_isa (int isa
)
14135 for (i
= 0; mips_cpu_info_table
[i
].name
!= NULL
; i
++)
14136 if (mips_cpu_info_table
[i
].is_isa
14137 && isa
== mips_cpu_info_table
[i
].isa
)
14138 return (&mips_cpu_info_table
[i
]);
14143 static const struct mips_cpu_info
*
14144 mips_cpu_info_from_arch (int arch
)
14148 for (i
= 0; mips_cpu_info_table
[i
].name
!= NULL
; i
++)
14149 if (arch
== mips_cpu_info_table
[i
].cpu
)
14150 return (&mips_cpu_info_table
[i
]);
14156 show (FILE *stream
, const char *string
, int *col_p
, int *first_p
)
14160 fprintf (stream
, "%24s", "");
14165 fprintf (stream
, ", ");
14169 if (*col_p
+ strlen (string
) > 72)
14171 fprintf (stream
, "\n%24s", "");
14175 fprintf (stream
, "%s", string
);
14176 *col_p
+= strlen (string
);
14182 md_show_usage (FILE *stream
)
14187 fprintf (stream
, _("\
14189 -EB generate big endian output\n\
14190 -EL generate little endian output\n\
14191 -g, -g2 do not remove unneeded NOPs or swap branches\n\
14192 -G NUM allow referencing objects up to NUM bytes\n\
14193 implicitly with the gp register [default 8]\n"));
14194 fprintf (stream
, _("\
14195 -mips1 generate MIPS ISA I instructions\n\
14196 -mips2 generate MIPS ISA II instructions\n\
14197 -mips3 generate MIPS ISA III instructions\n\
14198 -mips4 generate MIPS ISA IV instructions\n\
14199 -mips5 generate MIPS ISA V instructions\n\
14200 -mips32 generate MIPS32 ISA instructions\n\
14201 -mips32r2 generate MIPS32 release 2 ISA instructions\n\
14202 -mips64 generate MIPS64 ISA instructions\n\
14203 -mips64r2 generate MIPS64 release 2 ISA instructions\n\
14204 -march=CPU/-mtune=CPU generate code/schedule for CPU, where CPU is one of:\n"));
14208 for (i
= 0; mips_cpu_info_table
[i
].name
!= NULL
; i
++)
14209 show (stream
, mips_cpu_info_table
[i
].name
, &column
, &first
);
14210 show (stream
, "from-abi", &column
, &first
);
14211 fputc ('\n', stream
);
14213 fprintf (stream
, _("\
14214 -mCPU equivalent to -march=CPU -mtune=CPU. Deprecated.\n\
14215 -no-mCPU don't generate code specific to CPU.\n\
14216 For -mCPU and -no-mCPU, CPU must be one of:\n"));
14220 show (stream
, "3900", &column
, &first
);
14221 show (stream
, "4010", &column
, &first
);
14222 show (stream
, "4100", &column
, &first
);
14223 show (stream
, "4650", &column
, &first
);
14224 fputc ('\n', stream
);
14226 fprintf (stream
, _("\
14227 -mips16 generate mips16 instructions\n\
14228 -no-mips16 do not generate mips16 instructions\n"));
14229 fprintf (stream
, _("\
14230 -mdsp generate DSP instructions\n\
14231 -mno-dsp do not generate DSP instructions\n"));
14232 fprintf (stream
, _("\
14233 -mfix-vr4120 work around certain VR4120 errata\n\
14234 -mfix-vr4130 work around VR4130 mflo/mfhi errata\n\
14235 -mgp32 use 32-bit GPRs, regardless of the chosen ISA\n\
14236 -mfp32 use 32-bit FPRs, regardless of the chosen ISA\n\
14237 -mno-shared optimize output for executables\n\
14238 -msym32 assume all symbols have 32-bit values\n\
14239 -O0 remove unneeded NOPs, do not swap branches\n\
14240 -O remove unneeded NOPs and swap branches\n\
14241 --[no-]construct-floats [dis]allow floating point values to be constructed\n\
14242 --trap, --no-break trap exception on div by 0 and mult overflow\n\
14243 --break, --no-trap break exception on div by 0 and mult overflow\n"));
14245 fprintf (stream
, _("\
14246 -KPIC, -call_shared generate SVR4 position independent code\n\
14247 -non_shared do not generate position independent code\n\
14248 -xgot assume a 32 bit GOT\n\
14249 -mpdr, -mno-pdr enable/disable creation of .pdr sections\n\
14250 -mshared, -mno-shared disable/enable .cpload optimization for\n\
14252 -mabi=ABI create ABI conformant object file for:\n"));
14256 show (stream
, "32", &column
, &first
);
14257 show (stream
, "o64", &column
, &first
);
14258 show (stream
, "n32", &column
, &first
);
14259 show (stream
, "64", &column
, &first
);
14260 show (stream
, "eabi", &column
, &first
);
14262 fputc ('\n', stream
);
14264 fprintf (stream
, _("\
14265 -32 create o32 ABI object file (default)\n\
14266 -n32 create n32 ABI object file\n\
14267 -64 create 64 ABI object file\n"));
14272 mips_dwarf2_format (void)
14274 if (mips_abi
== N64_ABI
)
14277 return dwarf2_format_64bit_irix
;
14279 return dwarf2_format_64bit
;
14283 return dwarf2_format_32bit
;
14287 mips_dwarf2_addr_size (void)
14289 if (mips_abi
== N64_ABI
)
14295 /* Standard calling conventions leave the CFA at SP on entry. */
14297 mips_cfi_frame_initial_instructions (void)
14299 cfi_add_CFA_def_cfa_register (SP
);