1 /* tc-mips.c -- assemble code for a MIPS chip.
2 Copyright (C) 1993 Free Software Foundation, Inc.
3 Contributed by the OSF and Ralph Campbell.
4 Written by Keith Knowles and Ralph Campbell, working independently.
5 Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus
8 This file is part of GAS.
10 GAS is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 2, or (at your option)
15 GAS is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with GAS; see the file COPYING. If not, write to
22 the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */
27 #include "libiberty.h"
42 #endif /* NO_VARARGS */
43 #endif /* NO_STDARG */
45 #include "opcode/mips.h"
50 static char *mips_regmask_frag
;
54 #define PIC_CALL_REG 25
62 /* Decide whether to do GP reference optimizations based on the object
72 /* The default target format to use. */
74 #ifdef TARGET_BYTES_BIG_ENDIAN
75 #define DEFAULT_TARGET_FORMAT "a.out-mips-big"
77 #define DEFAULT_TARGET_FORMAT "a.out-mips-little"
81 #ifdef TARGET_BYTES_BIG_ENDIAN
82 #define DEFAULT_TARGET_FORMAT "ecoff-bigmips"
84 #define DEFAULT_TARGET_FORMAT "ecoff-littlemips"
86 #endif /* OBJ_ECOFF */
88 #ifdef TARGET_BYTES_BIG_ENDIAN
89 #define DEFAULT_TARGET_FORMAT "elf32-bigmips"
91 #define DEFAULT_TARGET_FORMAT "elf32-littlemips"
95 const char *mips_target_format
= DEFAULT_TARGET_FORMAT
;
97 /* The name of the readonly data section. */
99 #define RDATA_SECTION_NAME ".data"
102 #define RDATA_SECTION_NAME ".rdata"
105 #define RDATA_SECTION_NAME ".rodata"
108 /* These variables are filled in with the masks of registers used.
109 The object format code reads them and puts them in the appropriate
111 unsigned long mips_gprmask
;
112 unsigned long mips_cprmask
[4];
114 /* MIPS ISA (Instruction Set Architecture) level (may be changed
115 temporarily using .set mipsN). */
116 static int mips_isa
= -1;
118 /* MIPS ISA we are using for this output file. */
119 static int file_mips_isa
;
121 /* The CPU type as a number: 2000, 3000, 4000, 4400, etc. */
122 static int mips_cpu
= -1;
124 /* Whether the 4650 instructions (mad/madu) are permitted. */
125 static int mips_4650
= -1;
127 /* MIPS PIC level. */
131 /* Do not generate PIC code. */
134 /* Generate PIC code as in Irix 4. This is not implemented, and I'm
135 not sure what it is supposed to do. */
138 /* Generate PIC code as in the SVR4 MIPS ABI. */
141 /* Generate PIC code without using a global offset table: the data
142 segment has a maximum size of 64K, all data references are off
143 the $gp register, and all text references are PC relative. This
144 is used on some embedded systems. */
148 static enum mips_pic_level mips_pic
;
150 /* 1 if trap instructions should used for overflow rather than break
152 static int mips_trap
;
154 static int mips_warn_about_macros
;
155 static int mips_noreorder
;
156 static int mips_any_noreorder
;
157 static int mips_nomove
;
158 static int mips_noat
;
159 static int mips_nobopt
;
162 /* The size of the small data section. */
163 static int g_switch_value
= 8;
164 /* Whether the -G option was used. */
165 static int g_switch_seen
= 0;
171 /* handle of the OPCODE hash table */
172 static struct hash_control
*op_hash
= NULL
;
174 /* This array holds the chars that always start a comment. If the
175 pre-processor is disabled, these aren't very useful */
176 const char comment_chars
[] = "#";
178 /* This array holds the chars that only start a comment at the beginning of
179 a line. If the line seems to have the form '# 123 filename'
180 .line and .file directives will appear in the pre-processed output */
181 /* Note that input_file.c hand checks for '#' at the beginning of the
182 first line of the input file. This is because the compiler outputs
183 #NO_APP at the beginning of its output. */
184 /* Also note that C style comments are always supported. */
185 const char line_comment_chars
[] = "#";
187 /* This array holds machine specific line separator characters. */
188 const char line_separator_chars
[] = "";
190 /* Chars that can be used to separate mant from exp in floating point nums */
191 const char EXP_CHARS
[] = "eE";
193 /* Chars that mean this number is a floating point constant */
196 const char FLT_CHARS
[] = "rRsSfFdDxXpP";
198 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
199 changed in read.c . Ideally it shouldn't have to know about it at all,
200 but nothing is ideal around here.
203 static char *insn_error
;
205 static int byte_order
= BYTE_ORDER
;
207 static int auto_align
= 1;
209 /* Symbol labelling the current insn. */
210 static symbolS
*insn_label
;
212 /* When outputting SVR4 PIC code, the assembler needs to know the
213 offset in the stack frame from which to restore the $gp register.
214 This is set by the .cprestore pseudo-op, and saved in this
216 static offsetT mips_cprestore_offset
= -1;
218 /* This is the register which holds the stack frame, as set by the
219 .frame pseudo-op. This is needed to implement .cprestore. */
220 static int mips_frame_reg
= SP
;
222 /* To output NOP instructions correctly, we need to keep information
223 about the previous two instructions. */
225 /* Whether we are optimizing. The default value of 2 means to remove
226 unneeded NOPs and swap branch instructions when possible. A value
227 of 1 means to not swap branches. A value of 0 means to always
229 static int mips_optimize
= 2;
231 /* The previous instruction. */
232 static struct mips_cl_insn prev_insn
;
234 /* The instruction before prev_insn. */
235 static struct mips_cl_insn prev_prev_insn
;
237 /* If we don't want information for prev_insn or prev_prev_insn, we
238 point the insn_mo field at this dummy integer. */
239 static const struct mips_opcode dummy_opcode
= { 0 };
241 /* Non-zero if prev_insn is valid. */
242 static int prev_insn_valid
;
244 /* The frag for the previous instruction. */
245 static struct frag
*prev_insn_frag
;
247 /* The offset into prev_insn_frag for the previous instruction. */
248 static long prev_insn_where
;
250 /* The reloc for the previous instruction, if any. */
251 static fixS
*prev_insn_fixp
;
253 /* Non-zero if the previous instruction was in a delay slot. */
254 static int prev_insn_is_delay_slot
;
256 /* Non-zero if the previous instruction was in a .set noreorder. */
257 static int prev_insn_unreordered
;
259 /* Non-zero if the previous previous instruction was in a .set
261 static int prev_prev_insn_unreordered
;
263 /* Since the MIPS does not have multiple forms of PC relative
264 instructions, we do not have to do relaxing as is done on other
265 platforms. However, we do have to handle GP relative addressing
266 correctly, which turns out to be a similar problem.
268 Every macro that refers to a symbol can occur in (at least) two
269 forms, one with GP relative addressing and one without. For
270 example, loading a global variable into a register generally uses
271 a macro instruction like this:
273 If i can be addressed off the GP register (this is true if it is in
274 the .sbss or .sdata section, or if it is known to be smaller than
275 the -G argument) this will generate the following instruction:
277 This instruction will use a GPREL reloc. If i can not be addressed
278 off the GP register, the following instruction sequence will be used:
281 In this case the first instruction will have a HI16 reloc, and the
282 second reloc will have a LO16 reloc. Both relocs will be against
285 The issue here is that we may not know whether i is GP addressable
286 until after we see the instruction that uses it. Therefore, we
287 want to be able to choose the final instruction sequence only at
288 the end of the assembly. This is similar to the way other
289 platforms choose the size of a PC relative instruction only at the
292 When generating position independent code we do not use GP
293 addressing in quite the same way, but the issue still arises as
294 external symbols and local symbols must be handled differently.
296 We handle these issues by actually generating both possible
297 instruction sequences. The longer one is put in a frag_var with
298 type rs_machine_dependent. We encode what to do with the frag in
299 the subtype field. We encode (1) the number of existing bytes to
300 replace, (2) the number of new bytes to use, (3) the offset from
301 the start of the existing bytes to the first reloc we must generate
302 (that is, the offset is applied from the start of the existing
303 bytes after they are replaced by the new bytes, if any), (4) the
304 offset from the start of the existing bytes to the second reloc,
305 (5) whether a third reloc is needed (the third reloc is always four
306 bytes after the second reloc), and (6) whether to warn if this
307 variant is used (this is sometimes needed if .set nomacro or .set
308 noat is in effect). All these numbers are reasonably small.
310 Generating two instruction sequences must be handled carefully to
311 ensure that delay slots are handled correctly. Fortunately, there
312 are a limited number of cases. When the second instruction
313 sequence is generated, append_insn is directed to maintain the
314 existing delay slot information, so it continues to apply to any
315 code after the second instruction sequence. This means that the
316 second instruction sequence must not impose any requirements not
317 required by the first instruction sequence.
319 These variant frags are then handled in functions called by the
320 machine independent code. md_estimate_size_before_relax returns
321 the final size of the frag. md_convert_frag sets up the final form
322 of the frag. tc_gen_reloc adjust the first reloc and adds a second
324 #define RELAX_ENCODE(old, new, reloc1, reloc2, reloc3, warn) \
328 | (((reloc1) + 64) << 9) \
329 | (((reloc2) + 64) << 2) \
330 | ((reloc3) ? (1 << 1) : 0) \
332 #define RELAX_OLD(i) (((i) >> 24) & 0xff)
333 #define RELAX_NEW(i) (((i) >> 16) & 0xff)
334 #define RELAX_RELOC1(i) ((bfd_vma)(((i) >> 9) & 0x7f) - 64)
335 #define RELAX_RELOC2(i) ((bfd_vma)(((i) >> 2) & 0x7f) - 64)
336 #define RELAX_RELOC3(i) (((i) >> 1) & 1)
337 #define RELAX_WARN(i) ((i) & 1)
339 /* Prototypes for static functions. */
342 #define internalError() \
343 as_fatal ("internal Error, line %d, %s", __LINE__, __FILE__)
345 #define internalError() as_fatal ("MIPS internal Error");
348 static int insn_uses_reg
PARAMS ((struct mips_cl_insn
*ip
,
349 unsigned int reg
, int fpr
));
350 static void append_insn
PARAMS ((char *place
,
351 struct mips_cl_insn
* ip
,
353 bfd_reloc_code_real_type r
));
354 static void mips_no_prev_insn
PARAMS ((void));
355 static void mips_emit_delays
PARAMS ((void));
356 static void macro_build
PARAMS ((char *place
, int *counter
, expressionS
* ep
,
357 const char *name
, const char *fmt
,
359 static void macro_build_lui
PARAMS ((char *place
, int *counter
,
360 expressionS
* ep
, int regnum
));
361 static void set_at
PARAMS ((int *counter
, int reg
, int unsignedp
));
362 static void check_absolute_expr
PARAMS ((struct mips_cl_insn
* ip
,
364 static void load_register
PARAMS ((int *counter
, int reg
, expressionS
* ep
));
365 static void load_address
PARAMS ((int *counter
, int reg
, expressionS
*ep
));
366 static void macro
PARAMS ((struct mips_cl_insn
* ip
));
367 #ifdef LOSING_COMPILER
368 static void macro2
PARAMS ((struct mips_cl_insn
* ip
));
370 static void mips_ip
PARAMS ((char *str
, struct mips_cl_insn
* ip
));
371 static int my_getSmallExpression
PARAMS ((expressionS
* ep
, char *str
));
372 static void my_getExpression
PARAMS ((expressionS
* ep
, char *str
));
373 static symbolS
*get_symbol
PARAMS ((void));
374 static void mips_align
PARAMS ((int to
, int fill
, symbolS
*label
));
375 static void s_align
PARAMS ((int));
376 static void s_stringer
PARAMS ((int));
377 static void s_change_sec
PARAMS ((int));
378 static void s_cons
PARAMS ((int));
379 static void s_err
PARAMS ((int));
380 static void s_extern
PARAMS ((int));
381 static void s_float_cons
PARAMS ((int));
382 static void s_mips_globl
PARAMS ((int));
383 static void s_option
PARAMS ((int));
384 static void s_mipsset
PARAMS ((int));
385 static void s_mips_space
PARAMS ((int));
386 static void s_abicalls
PARAMS ((int));
387 static void s_cpload
PARAMS ((int));
388 static void s_cprestore
PARAMS ((int));
389 static void s_gpword
PARAMS ((int));
390 static void s_cpadd
PARAMS ((int));
391 #ifndef ECOFF_DEBUGGING
392 static void md_obj_begin
PARAMS ((void));
393 static void md_obj_end
PARAMS ((void));
394 static long get_number
PARAMS ((void));
395 static void s_ent
PARAMS ((int));
396 static void s_mipsend
PARAMS ((int));
397 static void s_file
PARAMS ((int));
399 static void s_frame
PARAMS ((int));
400 static void s_loc
PARAMS ((int));
401 static void s_mask
PARAMS ((char));
405 static void s_elf_section
PARAMS ((int));
410 The following pseudo-ops from the Kane and Heinrich MIPS book
411 should be defined here, but are currently unsupported: .alias,
412 .galive, .gjaldef, .gjrlive, .livereg, .noalias.
414 The following pseudo-ops from the Kane and Heinrich MIPS book are
415 specific to the type of debugging information being generated, and
416 should be defined by the object format: .aent, .begin, .bend,
417 .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp,
420 The following pseudo-ops from the Kane and Heinrich MIPS book are
421 not MIPS CPU specific, but are also not specific to the object file
422 format. This file is probably the best place to define them, but
423 they are not currently supported: .asm0, .endr, .lab, .repeat,
424 .struct, .weakext. */
426 const pseudo_typeS md_pseudo_table
[] =
428 /* MIPS specific pseudo-ops. */
429 {"option", s_option
, 0},
430 {"set", s_mipsset
, 0},
431 {"rdata", s_change_sec
, 'r'},
432 {"sdata", s_change_sec
, 's'},
433 {"livereg", s_ignore
, 0},
434 { "abicalls", s_abicalls
, 0},
435 { "cpload", s_cpload
, 0},
436 { "cprestore", s_cprestore
, 0},
437 { "gpword", s_gpword
, 0},
438 { "cpadd", s_cpadd
, 0},
440 /* Relatively generic pseudo-ops that happen to be used on MIPS
442 {"asciiz", s_stringer
, 1},
443 {"bss", s_change_sec
, 'b'},
446 {"dword", s_cons
, 3},
448 /* These pseudo-ops are defined in read.c, but must be overridden
449 here for one reason or another. */
450 {"align", s_align
, 0},
451 {"ascii", s_stringer
, 0},
452 {"asciz", s_stringer
, 1},
454 {"data", s_change_sec
, 'd'},
455 {"double", s_float_cons
, 'd'},
456 {"extern", s_extern
, 0},
457 {"float", s_float_cons
, 'f'},
458 {"globl", s_mips_globl
, 0},
459 {"global", s_mips_globl
, 0},
460 {"hword", s_cons
, 1},
465 {"short", s_cons
, 1},
466 {"single", s_float_cons
, 'f'},
467 {"space", s_mips_space
, 0},
468 {"text", s_change_sec
, 't'},
471 #ifndef ECOFF_DEBUGGING
472 /* These pseudo-ops should be defined by the object file format.
473 However, a.out doesn't support them, so we have versions here. */
475 {"bgnb", s_ignore
, 0},
476 {"end", s_mipsend
, 0},
477 {"endb", s_ignore
, 0},
480 {"fmask", s_ignore
, 'F'},
481 {"frame", s_ignore
, 0},
482 {"loc", s_ignore
, 0},
483 {"mask", s_ignore
, 'R'},
484 {"verstamp", s_ignore
, 0},
488 /* We need to tweak the ELF ".section" pseudo-op a bit. */
489 {"section", s_elf_section
, 0},
491 /* Redirect additional ELF data allocation pseudo-ops. */
492 {"2byte", s_cons
, 2},
493 {"4byte", s_cons
, 4},
494 {"8byte", s_cons
, 8},
501 const relax_typeS md_relax_table
[] =
506 static char *expr_end
;
508 static expressionS imm_expr
;
509 static expressionS offset_expr
;
510 static bfd_reloc_code_real_type imm_reloc
;
511 static bfd_reloc_code_real_type offset_reloc
;
513 /* FIXME: This should be handled in a different way. */
514 extern int target_big_endian
;
517 * This function is called once, at assembler startup time. It should
518 * set up all the tables, etc. that the MD part of the assembler will need.
524 register const char *retval
= NULL
;
525 register unsigned int i
= 0;
533 if (strcmp (cpu
+ (sizeof TARGET_CPU
) - 3, "el") == 0)
535 a
= xmalloc (sizeof TARGET_CPU
);
536 strcpy (a
, TARGET_CPU
);
537 a
[(sizeof TARGET_CPU
) - 3] = '\0';
541 if (strcmp (cpu
, "mips") == 0)
547 else if (strcmp (cpu
, "r6000") == 0
548 || strcmp (cpu
, "mips2") == 0)
554 else if (strcmp (cpu
, "mips64") == 0
555 || strcmp (cpu
, "r4000") == 0
556 || strcmp (cpu
, "mips3") == 0)
562 else if (strcmp (cpu
, "r4400") == 0)
568 else if (strcmp (cpu
, "mips64orion") == 0
569 || strcmp (cpu
, "r4600") == 0)
575 else if (strcmp (cpu
, "r4650") == 0)
597 if (mips_isa
< 2 && mips_trap
)
598 as_bad ("trap exception not supported at ISA 1");
603 ok
= bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, 3000);
606 ok
= bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, 6000);
609 ok
= bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, 4000);
613 as_warn ("Could not set architecture and machine");
615 file_mips_isa
= mips_isa
;
617 op_hash
= hash_new ();
619 for (i
= 0; i
< NUMOPCODES
;)
621 const char *name
= mips_opcodes
[i
].name
;
623 retval
= hash_insert (op_hash
, name
, (PTR
) &mips_opcodes
[i
]);
626 fprintf (stderr
, "internal error: can't hash `%s': %s\n",
627 mips_opcodes
[i
].name
, retval
);
628 as_fatal ("Broken assembler. No assembly attempted.");
632 if (mips_opcodes
[i
].pinfo
!= INSN_MACRO
633 && ((mips_opcodes
[i
].match
& mips_opcodes
[i
].mask
)
634 != mips_opcodes
[i
].match
))
636 fprintf (stderr
, "internal error: bad opcode: `%s' \"%s\"\n",
637 mips_opcodes
[i
].name
, mips_opcodes
[i
].args
);
638 as_fatal ("Broken assembler. No assembly attempted.");
642 while ((i
< NUMOPCODES
) && !strcmp (mips_opcodes
[i
].name
, name
));
645 mips_no_prev_insn ();
653 /* set the default alignment for the text section (2**2) */
654 record_alignment (text_section
, 2);
656 /* FIXME: This should be handled in a different way. */
657 target_big_endian
= byte_order
== BIG_ENDIAN
;
660 bfd_set_gp_size (stdoutput
, g_switch_value
);
664 /* Sections must be aligned to 16 byte boundaries. */
665 (void) bfd_set_section_alignment (stdoutput
, text_section
, 4);
666 (void) bfd_set_section_alignment (stdoutput
, data_section
, 4);
667 (void) bfd_set_section_alignment (stdoutput
, bss_section
, 4);
669 /* Create a .reginfo section for register masks and a .mdebug
670 section for debugging information. */
678 sec
= subseg_new (".reginfo", (subsegT
) 0);
680 /* The ABI says this section should be loaded so that the running
681 program can access it. */
682 (void) bfd_set_section_flags (stdoutput
, sec
,
683 (SEC_ALLOC
| SEC_LOAD
684 | SEC_READONLY
| SEC_DATA
));
685 (void) bfd_set_section_alignment (stdoutput
, sec
, 2);
687 mips_regmask_frag
= frag_more (sizeof (Elf32_External_RegInfo
));
689 #ifdef ECOFF_DEBUGGING
690 sec
= subseg_new (".mdebug", (subsegT
) 0);
691 (void) bfd_set_section_flags (stdoutput
, sec
,
692 SEC_HAS_CONTENTS
| SEC_READONLY
);
693 (void) bfd_set_section_alignment (stdoutput
, sec
, 2);
696 subseg_set (seg
, subseg
);
700 #ifndef ECOFF_DEBUGGING
708 #ifndef ECOFF_DEBUGGING
717 struct mips_cl_insn insn
;
719 imm_expr
.X_op
= O_absent
;
720 offset_expr
.X_op
= O_absent
;
722 mips_ip (str
, &insn
);
725 as_bad ("%s `%s'", insn_error
, str
);
728 if (insn
.insn_mo
->pinfo
== INSN_MACRO
)
734 if (imm_expr
.X_op
!= O_absent
)
735 append_insn ((char *) NULL
, &insn
, &imm_expr
, imm_reloc
);
736 else if (offset_expr
.X_op
!= O_absent
)
737 append_insn ((char *) NULL
, &insn
, &offset_expr
, offset_reloc
);
739 append_insn ((char *) NULL
, &insn
, NULL
, BFD_RELOC_UNUSED
);
743 /* See whether instruction IP reads register REG. If FPR is non-zero,
744 REG is a floating point register. */
747 insn_uses_reg (ip
, reg
, fpr
)
748 struct mips_cl_insn
*ip
;
752 /* Don't report on general register 0, since it never changes. */
753 if (! fpr
&& reg
== 0)
758 /* If we are called with either $f0 or $f1, we must check $f0.
759 This is not optimal, because it will introduce an unnecessary
760 NOP between "lwc1 $f0" and "swc1 $f1". To fix this we would
761 need to distinguish reading both $f0 and $f1 or just one of
762 them. Note that we don't have to check the other way,
763 because there is no instruction that sets both $f0 and $f1
764 and requires a delay. */
765 if ((ip
->insn_mo
->pinfo
& INSN_READ_FPR_S
)
766 && (((ip
->insn_opcode
>> OP_SH_FS
) & OP_MASK_FS
)
767 == (reg
&~ (unsigned) 1)))
769 if ((ip
->insn_mo
->pinfo
& INSN_READ_FPR_T
)
770 && (((ip
->insn_opcode
>> OP_SH_FT
) & OP_MASK_FT
)
771 == (reg
&~ (unsigned) 1)))
776 if ((ip
->insn_mo
->pinfo
& INSN_READ_GPR_S
)
777 && ((ip
->insn_opcode
>> OP_SH_RS
) & OP_MASK_RS
) == reg
)
779 if ((ip
->insn_mo
->pinfo
& INSN_READ_GPR_T
)
780 && ((ip
->insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
) == reg
)
787 /* Output an instruction. PLACE is where to put the instruction; if
788 it is NULL, this uses frag_more to get room. IP is the instruction
789 information. ADDRESS_EXPR is an operand of the instruction to be
790 used with RELOC_TYPE. */
793 append_insn (place
, ip
, address_expr
, reloc_type
)
795 struct mips_cl_insn
*ip
;
796 expressionS
*address_expr
;
797 bfd_reloc_code_real_type reloc_type
;
799 register unsigned long prev_pinfo
, pinfo
;
804 prev_pinfo
= prev_insn
.insn_mo
->pinfo
;
805 pinfo
= ip
->insn_mo
->pinfo
;
807 if (place
== NULL
&& ! mips_noreorder
)
809 /* If the previous insn required any delay slots, see if we need
810 to insert a NOP or two. There are eight kinds of possible
811 hazards, of which an instruction can have at most one type.
812 (1) a load from memory delay
813 (2) a load from a coprocessor delay
814 (3) an unconditional branch delay
815 (4) a conditional branch delay
816 (5) a move to coprocessor register delay
817 (6) a load coprocessor register from memory delay
818 (7) a coprocessor condition code delay
819 (8) a HI/LO special register delay
821 There are a lot of optimizations we could do that we don't.
822 In particular, we do not, in general, reorder instructions.
823 If you use gcc with optimization, it will reorder
824 instructions and generally do much more optimization then we
825 do here; repeating all that work in the assembler would only
826 benefit hand written assembly code, and does not seem worth
829 /* This is how a NOP is emitted. */
830 #define emit_nop() md_number_to_chars (frag_more (4), 0, 4)
832 /* The previous insn might require a delay slot, depending upon
833 the contents of the current insn. */
834 if ((prev_pinfo
& INSN_LOAD_COPROC_DELAY
)
836 && (prev_pinfo
& INSN_LOAD_MEMORY_DELAY
)))
838 /* A load from a coprocessor or from memory. All load
839 delays delay the use of general register rt for one
840 instruction on the r3000. The r6000 and r4000 use
842 know (prev_pinfo
& INSN_WRITE_GPR_T
);
843 if (mips_optimize
== 0
844 || insn_uses_reg (ip
,
845 ((prev_insn
.insn_opcode
>> OP_SH_RT
)
850 else if ((prev_pinfo
& INSN_COPROC_MOVE_DELAY
)
852 && (prev_pinfo
& INSN_COPROC_MEMORY_DELAY
)))
854 /* A generic coprocessor delay. The previous instruction
855 modified a coprocessor general or control register. If
856 it modified a control register, we need to avoid any
857 coprocessor instruction (this is probably not always
858 required, but it sometimes is). If it modified a general
859 register, we avoid using that register.
861 On the r6000 and r4000 loading a coprocessor register
862 from memory is interlocked, and does not require a delay.
864 This case is not handled very well. There is no special
865 knowledge of CP0 handling, and the coprocessors other
866 than the floating point unit are not distinguished at
868 if (prev_pinfo
& INSN_WRITE_FPR_T
)
870 if (mips_optimize
== 0
871 || insn_uses_reg (ip
,
872 ((prev_insn
.insn_opcode
>> OP_SH_FT
)
877 else if (prev_pinfo
& INSN_WRITE_FPR_S
)
879 if (mips_optimize
== 0
880 || insn_uses_reg (ip
,
881 ((prev_insn
.insn_opcode
>> OP_SH_FS
)
888 /* We don't know exactly what the previous instruction
889 does. If the current instruction uses a coprocessor
890 register, we must insert a NOP. If previous
891 instruction may set the condition codes, and the
892 current instruction uses them, we must insert two
894 if (mips_optimize
== 0
895 || ((prev_pinfo
& INSN_WRITE_COND_CODE
)
896 && (pinfo
& INSN_READ_COND_CODE
)))
898 else if (pinfo
& INSN_COP
)
902 else if (prev_pinfo
& INSN_WRITE_COND_CODE
)
904 /* The previous instruction sets the coprocessor condition
905 codes, but does not require a general coprocessor delay
906 (this means it is a floating point comparison
907 instruction). If this instruction uses the condition
908 codes, we need to insert a single NOP. */
909 if (mips_optimize
== 0
910 || (pinfo
& INSN_READ_COND_CODE
))
913 else if (prev_pinfo
& INSN_READ_LO
)
915 /* The previous instruction reads the LO register; if the
916 current instruction writes to the LO register, we must
917 insert two NOPS. The R4650 has interlocks. */
919 && (mips_optimize
== 0
920 || (pinfo
& INSN_WRITE_LO
)))
923 else if (prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
925 /* The previous instruction reads the HI register; if the
926 current instruction writes to the HI register, we must
927 insert a NOP. The R4650 has interlocks. */
929 && (mips_optimize
== 0
930 || (pinfo
& INSN_WRITE_HI
)))
934 /* There are two cases which require two intervening
935 instructions: 1) setting the condition codes using a move to
936 coprocessor instruction which requires a general coprocessor
937 delay and then reading the condition codes 2) reading the HI
938 or LO register and then writing to it (except on the R4650,
939 which has interlocks). If we are not already emitting a NOP
940 instruction, we must check for these cases compared to the
941 instruction previous to the previous instruction. */
943 && (((prev_prev_insn
.insn_mo
->pinfo
& INSN_COPROC_MOVE_DELAY
)
944 && (prev_prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
)
945 && (pinfo
& INSN_READ_COND_CODE
))
946 || ((prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
)
947 && (pinfo
& INSN_WRITE_LO
)
949 || ((prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
950 && (pinfo
& INSN_WRITE_HI
)
954 /* If we are being given a nop instruction, don't bother with
955 one of the nops we would otherwise output. This will only
956 happen when a nop instruction is used with mips_optimize set
958 if (nops
> 0 && ip
->insn_opcode
== 0)
961 /* Now emit the right number of NOP instructions. */
966 for (i
= 0; i
< nops
; i
++)
970 listing_prev_line ();
971 /* We may be at the start of a variant frag. In case we
972 are, make sure there is enough space for the frag
973 after the frags created by listing_prev_line. The
974 argument to frag_grow here must be at least as large
975 as the argument to all other calls to frag_grow in
976 this file. We don't have to worry about being in the
977 middle of a variant frag, because the variants insert
978 all needed nop instructions themselves. */
981 if (insn_label
!= NULL
)
983 assert (S_GET_SEGMENT (insn_label
) == now_seg
);
984 insn_label
->sy_frag
= frag_now
;
985 S_SET_VALUE (insn_label
, (valueT
) frag_now_fix ());
995 if (address_expr
!= NULL
)
997 if (address_expr
->X_op
== O_constant
)
1002 ip
->insn_opcode
|= address_expr
->X_add_number
;
1005 case BFD_RELOC_LO16
:
1006 ip
->insn_opcode
|= address_expr
->X_add_number
& 0xffff;
1009 case BFD_RELOC_MIPS_JMP
:
1010 case BFD_RELOC_16_PCREL_S2
:
1019 assert (reloc_type
!= BFD_RELOC_UNUSED
);
1021 /* Don't generate a reloc if we are writing into a variant
1024 fixp
= fix_new_exp (frag_now
, f
- frag_now
->fr_literal
, 4,
1026 reloc_type
== BFD_RELOC_16_PCREL_S2
,
1031 md_number_to_chars (f
, ip
->insn_opcode
, 4);
1033 /* Update the register mask information. */
1034 if (pinfo
& INSN_WRITE_GPR_D
)
1035 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
);
1036 if ((pinfo
& (INSN_WRITE_GPR_T
| INSN_READ_GPR_T
)) != 0)
1037 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
);
1038 if (pinfo
& INSN_READ_GPR_S
)
1039 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> OP_SH_RS
) & OP_MASK_RS
);
1040 if (pinfo
& INSN_WRITE_GPR_31
)
1041 mips_gprmask
|= 1 << 31;
1042 if (pinfo
& INSN_WRITE_FPR_D
)
1043 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FD
) & OP_MASK_FD
);
1044 if ((pinfo
& (INSN_WRITE_FPR_S
| INSN_READ_FPR_S
)) != 0)
1045 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FS
) & OP_MASK_FS
);
1046 if ((pinfo
& (INSN_WRITE_FPR_T
| INSN_READ_FPR_T
)) != 0)
1047 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FT
) & OP_MASK_FT
);
1048 if (pinfo
& INSN_COP
)
1050 /* We don't keep enough information to sort these cases out. */
1052 /* Never set the bit for $0, which is always zero. */
1053 mips_gprmask
&=~ 1 << 0;
1055 if (place
== NULL
&& ! mips_noreorder
)
1057 /* Filling the branch delay slot is more complex. We try to
1058 switch the branch with the previous instruction, which we can
1059 do if the previous instruction does not set up a condition
1060 that the branch tests and if the branch is not itself the
1061 target of any branch. */
1062 if ((pinfo
& INSN_UNCOND_BRANCH_DELAY
)
1063 || (pinfo
& INSN_COND_BRANCH_DELAY
))
1065 if (mips_optimize
< 2
1066 /* If we have seen .set volatile or .set nomove, don't
1069 /* If we had to emit any NOP instructions, then we
1070 already know we can not swap. */
1072 /* If we don't even know the previous insn, we can not
1074 || ! prev_insn_valid
1075 /* If the previous insn is already in a branch delay
1076 slot, then we can not swap. */
1077 || prev_insn_is_delay_slot
1078 /* If the previous previous insn was in a .set
1079 noreorder, we can't swap. Actually, the MIPS
1080 assembler will swap in this situation. However, gcc
1081 configured -with-gnu-as will generate code like
1087 in which we can not swap the bne and INSN. If gcc is
1088 not configured -with-gnu-as, it does not output the
1089 .set pseudo-ops. We don't have to check
1090 prev_insn_unreordered, because prev_insn_valid will
1091 be 0 in that case. We don't want to use
1092 prev_prev_insn_valid, because we do want to be able
1093 to swap at the start of a function. */
1094 || prev_prev_insn_unreordered
1095 /* If the branch is itself the target of a branch, we
1096 can not swap. We cheat on this; all we check for is
1097 whether there is a label on this instruction. If
1098 there are any branches to anything other than a
1099 label, users must use .set noreorder. */
1100 || insn_label
!= NULL
1101 /* If the previous instruction is in a variant frag, we
1102 can not do the swap. */
1103 || prev_insn_frag
->fr_type
== rs_machine_dependent
1104 /* If the branch reads the condition codes, we don't
1105 even try to swap, because in the sequence
1110 we can not swap, and I don't feel like handling that
1112 || (pinfo
& INSN_READ_COND_CODE
)
1113 /* We can not swap with an instruction that requires a
1114 delay slot, becase the target of the branch might
1115 interfere with that instruction. */
1117 & (INSN_LOAD_COPROC_DELAY
1118 | INSN_COPROC_MOVE_DELAY
1119 | INSN_WRITE_COND_CODE
))
1126 & (INSN_LOAD_MEMORY_DELAY
1127 | INSN_COPROC_MEMORY_DELAY
)))
1128 /* We can not swap with a branch instruction. */
1130 & (INSN_UNCOND_BRANCH_DELAY
1131 | INSN_COND_BRANCH_DELAY
1132 | INSN_COND_BRANCH_LIKELY
))
1133 /* We do not swap with a trap instruction, since it
1134 complicates trap handlers to have the trap
1135 instruction be in a delay slot. */
1136 || (prev_pinfo
& INSN_TRAP
)
1137 /* If the branch reads a register that the previous
1138 instruction sets, we can not swap. */
1139 || ((prev_pinfo
& INSN_WRITE_GPR_T
)
1140 && insn_uses_reg (ip
,
1141 ((prev_insn
.insn_opcode
>> OP_SH_RT
)
1144 || ((prev_pinfo
& INSN_WRITE_GPR_D
)
1145 && insn_uses_reg (ip
,
1146 ((prev_insn
.insn_opcode
>> OP_SH_RD
)
1149 /* If the branch writes a register that the previous
1150 instruction sets, we can not swap (we know that
1151 branches write only to RD or to $31). */
1152 || ((prev_pinfo
& INSN_WRITE_GPR_T
)
1153 && (((pinfo
& INSN_WRITE_GPR_D
)
1154 && (((prev_insn
.insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
)
1155 == ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)))
1156 || ((pinfo
& INSN_WRITE_GPR_31
)
1157 && (((prev_insn
.insn_opcode
>> OP_SH_RT
)
1160 || ((prev_pinfo
& INSN_WRITE_GPR_D
)
1161 && (((pinfo
& INSN_WRITE_GPR_D
)
1162 && (((prev_insn
.insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)
1163 == ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)))
1164 || ((pinfo
& INSN_WRITE_GPR_31
)
1165 && (((prev_insn
.insn_opcode
>> OP_SH_RD
)
1168 /* If the branch writes a register that the previous
1169 instruction reads, we can not swap (we know that
1170 branches only write to RD or to $31). */
1171 || ((pinfo
& INSN_WRITE_GPR_D
)
1172 && insn_uses_reg (&prev_insn
,
1173 ((ip
->insn_opcode
>> OP_SH_RD
)
1176 || ((pinfo
& INSN_WRITE_GPR_31
)
1177 && insn_uses_reg (&prev_insn
, 31, 0))
1178 /* If we are generating embedded PIC code, the branch
1179 might be expanded into a sequence which uses $at, so
1180 we can't swap with an instruction which reads it. */
1181 || (mips_pic
== EMBEDDED_PIC
1182 && insn_uses_reg (&prev_insn
, AT
, 0))
1183 /* If the previous previous instruction has a load
1184 delay, and sets a register that the branch reads, we
1186 || (((prev_prev_insn
.insn_mo
->pinfo
& INSN_LOAD_COPROC_DELAY
)
1188 && (prev_prev_insn
.insn_mo
->pinfo
1189 & INSN_LOAD_MEMORY_DELAY
)))
1190 && insn_uses_reg (ip
,
1191 ((prev_prev_insn
.insn_opcode
>> OP_SH_RT
)
1195 /* We could do even better for unconditional branches to
1196 portions of this object file; we could pick up the
1197 instruction at the destination, put it in the delay
1198 slot, and bump the destination address. */
1200 /* Update the previous insn information. */
1201 prev_prev_insn
= *ip
;
1202 prev_insn
.insn_mo
= &dummy_opcode
;
1209 /* It looks like we can actually do the swap. */
1210 prev_f
= prev_insn_frag
->fr_literal
+ prev_insn_where
;
1211 memcpy (temp
, prev_f
, 4);
1212 memcpy (prev_f
, f
, 4);
1213 memcpy (f
, temp
, 4);
1216 prev_insn_fixp
->fx_frag
= frag_now
;
1217 prev_insn_fixp
->fx_where
= f
- frag_now
->fr_literal
;
1221 fixp
->fx_frag
= prev_insn_frag
;
1222 fixp
->fx_where
= prev_insn_where
;
1224 /* Update the previous insn information; leave prev_insn
1226 prev_prev_insn
= *ip
;
1228 prev_insn_is_delay_slot
= 1;
1230 /* If that was an unconditional branch, forget the previous
1231 insn information. */
1232 if (pinfo
& INSN_UNCOND_BRANCH_DELAY
)
1234 prev_prev_insn
.insn_mo
= &dummy_opcode
;
1235 prev_insn
.insn_mo
= &dummy_opcode
;
1238 else if (pinfo
& INSN_COND_BRANCH_LIKELY
)
1240 /* We don't yet optimize a branch likely. What we should do
1241 is look at the target, copy the instruction found there
1242 into the delay slot, and increment the branch to jump to
1243 the next instruction. */
1245 /* Update the previous insn information. */
1246 prev_prev_insn
= *ip
;
1247 prev_insn
.insn_mo
= &dummy_opcode
;
1251 /* Update the previous insn information. */
1253 prev_prev_insn
.insn_mo
= &dummy_opcode
;
1255 prev_prev_insn
= prev_insn
;
1258 /* Any time we see a branch, we always fill the delay slot
1259 immediately; since this insn is not a branch, we know it
1260 is not in a delay slot. */
1261 prev_insn_is_delay_slot
= 0;
1264 prev_prev_insn_unreordered
= prev_insn_unreordered
;
1265 prev_insn_unreordered
= 0;
1266 prev_insn_frag
= frag_now
;
1267 prev_insn_where
= f
- frag_now
->fr_literal
;
1268 prev_insn_fixp
= fixp
;
1269 prev_insn_valid
= 1;
1272 /* We just output an insn, so the next one doesn't have a label. */
1276 /* This function forgets that there was any previous instruction or
1280 mips_no_prev_insn ()
1282 prev_insn
.insn_mo
= &dummy_opcode
;
1283 prev_prev_insn
.insn_mo
= &dummy_opcode
;
1284 prev_insn_valid
= 0;
1285 prev_insn_is_delay_slot
= 0;
1286 prev_insn_unreordered
= 0;
1287 prev_prev_insn_unreordered
= 0;
1291 /* This function must be called whenever we turn on noreorder or emit
1292 something other than instructions. It inserts any NOPS which might
1293 be needed by the previous instruction, and clears the information
1294 kept for the previous instructions. */
1299 if (! mips_noreorder
)
1304 if ((prev_insn
.insn_mo
->pinfo
1305 & (INSN_LOAD_COPROC_DELAY
1306 | INSN_COPROC_MOVE_DELAY
1307 | INSN_WRITE_COND_CODE
))
1309 && (prev_insn
.insn_mo
->pinfo
1313 && (prev_insn
.insn_mo
->pinfo
1314 & (INSN_LOAD_MEMORY_DELAY
1315 | INSN_COPROC_MEMORY_DELAY
))))
1318 if ((prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
)
1320 && ((prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
1321 || (prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
))))
1324 else if ((prev_prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
)
1326 && ((prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
1327 || (prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
))))
1332 if (insn_label
!= NULL
)
1334 assert (S_GET_SEGMENT (insn_label
) == now_seg
);
1335 insn_label
->sy_frag
= frag_now
;
1336 S_SET_VALUE (insn_label
, (valueT
) frag_now_fix ());
1341 mips_no_prev_insn ();
1344 /* Build an instruction created by a macro expansion. This is passed
1345 a pointer to the count of instructions created so far, an
1346 expression, the name of the instruction to build, an operand format
1347 string, and corresponding arguments. */
1351 macro_build (char *place
,
1357 #else /* ! defined (NO_STDARG) */
1359 macro_build (place
, counter
, ep
, name
, fmt
, va_alist
)
1366 #endif /* ! defined (NO_STDARG) */
1368 struct mips_cl_insn insn
;
1369 bfd_reloc_code_real_type r
;
1373 va_start (args
, fmt
);
1379 * If the macro is about to expand into a second instruction,
1380 * print a warning if needed. We need to pass ip as a parameter
1381 * to generate a better warning message here...
1383 if (mips_warn_about_macros
&& place
== NULL
&& *counter
== 1)
1384 as_warn ("Macro instruction expanded into multiple instructions");
1387 *counter
+= 1; /* bump instruction counter */
1389 r
= BFD_RELOC_UNUSED
;
1390 insn
.insn_mo
= (struct mips_opcode
*) hash_find (op_hash
, name
);
1391 assert (insn
.insn_mo
);
1392 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
1394 while (strcmp (fmt
, insn
.insn_mo
->args
) != 0
1395 || insn
.insn_mo
->pinfo
== INSN_MACRO
)
1398 assert (insn
.insn_mo
->name
);
1399 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
1401 insn
.insn_opcode
= insn
.insn_mo
->match
;
1417 insn
.insn_opcode
|= va_arg (args
, int) << 16;
1423 insn
.insn_opcode
|= va_arg (args
, int) << 16;
1428 insn
.insn_opcode
|= va_arg (args
, int) << 11;
1433 insn
.insn_opcode
|= va_arg (args
, int) << 11;
1440 insn
.insn_opcode
|= va_arg (args
, int) << 6;
1444 insn
.insn_opcode
|= va_arg (args
, int) << 6;
1448 insn
.insn_opcode
|= va_arg (args
, int) << 6;
1455 insn
.insn_opcode
|= va_arg (args
, int) << 21;
1461 r
= (bfd_reloc_code_real_type
) va_arg (args
, int);
1462 assert (r
== BFD_RELOC_MIPS_GPREL
1463 || r
== BFD_RELOC_MIPS_LITERAL
1464 || r
== BFD_RELOC_LO16
1465 || r
== BFD_RELOC_MIPS_GOT16
1466 || r
== BFD_RELOC_MIPS_CALL16
1467 || (ep
->X_op
== O_subtract
1468 && now_seg
== text_section
1469 && r
== BFD_RELOC_PCREL_LO16
));
1473 r
= (bfd_reloc_code_real_type
) va_arg (args
, int);
1475 && (ep
->X_op
== O_constant
1476 || (ep
->X_op
== O_symbol
1477 && (r
== BFD_RELOC_HI16_S
1478 || r
== BFD_RELOC_HI16
))
1479 || (ep
->X_op
== O_subtract
1480 && now_seg
== text_section
1481 && r
== BFD_RELOC_PCREL_HI16_S
)));
1482 if (ep
->X_op
== O_constant
)
1484 insn
.insn_opcode
|= (ep
->X_add_number
>> 16) & 0xffff;
1486 r
= BFD_RELOC_UNUSED
;
1491 assert (ep
!= NULL
);
1493 * This allows macro() to pass an immediate expression for
1494 * creating short branches without creating a symbol.
1495 * Note that the expression still might come from the assembly
1496 * input, in which case the value is not checked for range nor
1497 * is a relocation entry generated (yuck).
1499 if (ep
->X_op
== O_constant
)
1501 insn
.insn_opcode
|= (ep
->X_add_number
>> 2) & 0xffff;
1505 r
= BFD_RELOC_16_PCREL_S2
;
1509 assert (ep
!= NULL
);
1510 r
= BFD_RELOC_MIPS_JMP
;
1519 assert (r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
1521 append_insn (place
, &insn
, ep
, r
);
1525 * Generate a "lui" instruction.
1528 macro_build_lui (place
, counter
, ep
, regnum
)
1534 expressionS high_expr
;
1535 struct mips_cl_insn insn
;
1536 bfd_reloc_code_real_type r
;
1537 CONST
char *name
= "lui";
1538 CONST
char *fmt
= "t,u";
1544 high_expr
.X_op
= O_constant
;
1545 high_expr
.X_add_number
= 0;
1548 if (high_expr
.X_op
== O_constant
)
1550 /* we can compute the instruction now without a relocation entry */
1551 if (high_expr
.X_add_number
& 0x8000)
1552 high_expr
.X_add_number
+= 0x10000;
1553 high_expr
.X_add_number
=
1554 ((unsigned long) high_expr
.X_add_number
>> 16) & 0xffff;
1555 r
= BFD_RELOC_UNUSED
;
1559 assert (ep
->X_op
== O_symbol
);
1560 /* _gp_disp is a special case, used from s_cpload. */
1561 assert (mips_pic
== NO_PIC
1562 || strcmp (S_GET_NAME (ep
->X_add_symbol
), "_gp_disp") == 0);
1563 r
= BFD_RELOC_HI16_S
;
1567 * If the macro is about to expand into a second instruction,
1568 * print a warning if needed. We need to pass ip as a parameter
1569 * to generate a better warning message here...
1571 if (mips_warn_about_macros
&& place
== NULL
&& *counter
== 1)
1572 as_warn ("Macro instruction expanded into multiple instructions");
1575 *counter
+= 1; /* bump instruction counter */
1577 insn
.insn_mo
= (struct mips_opcode
*) hash_find (op_hash
, name
);
1578 assert (insn
.insn_mo
);
1579 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
1580 assert (strcmp (fmt
, insn
.insn_mo
->args
) == 0);
1582 insn
.insn_opcode
= insn
.insn_mo
->match
| (regnum
<< OP_SH_RT
);
1583 if (r
== BFD_RELOC_UNUSED
)
1585 insn
.insn_opcode
|= high_expr
.X_add_number
;
1586 append_insn (place
, &insn
, NULL
, r
);
1589 append_insn (place
, &insn
, &high_expr
, r
);
1593 * Generates code to set the $at register to true (one)
1594 * if reg is less than the immediate expression.
1597 set_at (counter
, reg
, unsignedp
)
1602 if (imm_expr
.X_add_number
>= -0x8000 && imm_expr
.X_add_number
< 0x8000)
1603 macro_build ((char *) NULL
, counter
, &imm_expr
,
1604 unsignedp
? "sltiu" : "slti",
1605 "t,r,j", AT
, reg
, (int) BFD_RELOC_LO16
);
1608 load_register (counter
, AT
, &imm_expr
);
1609 macro_build ((char *) NULL
, counter
, NULL
,
1610 unsignedp
? "sltu" : "slt",
1611 "d,v,t", AT
, reg
, AT
);
1615 /* Warn if an expression is not a constant. */
1618 check_absolute_expr (ip
, ex
)
1619 struct mips_cl_insn
*ip
;
1622 if (ex
->X_op
!= O_constant
)
1623 as_warn ("Instruction %s requires absolute expression", ip
->insn_mo
->name
);
1627 * This routine generates the least number of instructions neccessary to load
1628 * an absolute expression value into a register.
1631 load_register (counter
, reg
, ep
)
1637 expressionS hi32
, lo32
, tmp
;
1639 if (ep
->X_op
!= O_big
)
1641 assert (ep
->X_op
== O_constant
);
1642 if (ep
->X_add_number
>= -0x8000 && ep
->X_add_number
< 0x8000)
1644 /* We can handle 16 bit signed values with an addiu to
1645 $zero. No need to ever use daddiu here, since $zero and
1646 the result are always correct in 32 bit mode. */
1647 macro_build ((char *) NULL
, counter
, ep
, "addiu", "t,r,j", reg
, 0,
1648 (int) BFD_RELOC_LO16
);
1651 else if (ep
->X_add_number
>= 0 && ep
->X_add_number
< 0x10000)
1653 /* We can handle 16 bit unsigned values with an ori to
1655 macro_build ((char *) NULL
, counter
, ep
, "ori", "t,r,i", reg
, 0,
1656 (int) BFD_RELOC_LO16
);
1659 else if (((ep
->X_add_number
&~ (offsetT
) 0x7fffffff) == 0
1660 || ((ep
->X_add_number
&~ (offsetT
) 0x7fffffff)
1661 == ~ (offsetT
) 0x7fffffff))
1663 || sizeof (ep
->X_add_number
) > 4
1664 || (ep
->X_add_number
& 0x80000000) == 0))
1666 /* 32 bit values require an lui. */
1667 macro_build ((char *) NULL
, counter
, ep
, "lui", "t,u", reg
,
1668 (int) BFD_RELOC_HI16
);
1669 if ((ep
->X_add_number
& 0xffff) != 0)
1670 macro_build ((char *) NULL
, counter
, ep
, "ori", "t,r,i", reg
, reg
,
1671 (int) BFD_RELOC_LO16
);
1676 /* 32 bit value with high bit set being loaded into a 64 bit
1677 register. We can't use lui, because that would
1678 incorrectly set the 32 high bits. */
1679 generic_bignum
[3] = 0;
1680 generic_bignum
[2] = 0;
1681 generic_bignum
[1] = (ep
->X_add_number
>> 16) & 0xffff;
1682 generic_bignum
[0] = ep
->X_add_number
& 0xffff;
1684 tmp
.X_add_number
= 4;
1689 /* The value is larger than 32 bits. */
1693 as_bad ("Number larger than 32 bits");
1694 macro_build ((char *) NULL
, counter
, ep
, "addiu", "t,r,j", reg
, 0,
1695 (int) BFD_RELOC_LO16
);
1699 if (ep
->X_op
!= O_big
)
1703 hi32
.X_add_number
>>= shift
;
1704 hi32
.X_add_number
&= 0xffffffff;
1705 if ((hi32
.X_add_number
& 0x80000000) != 0)
1706 hi32
.X_add_number
|= ~ (offsetT
) 0xffffffff;
1708 lo32
.X_add_number
&= 0xffffffff;
1712 assert (ep
->X_add_number
> 2);
1713 if (ep
->X_add_number
== 3)
1714 generic_bignum
[3] = 0;
1715 else if (ep
->X_add_number
> 4)
1716 as_bad ("Number larger than 64 bits");
1717 lo32
.X_op
= O_constant
;
1718 lo32
.X_add_number
= generic_bignum
[0] + (generic_bignum
[1] << 16);
1719 hi32
.X_op
= O_constant
;
1720 hi32
.X_add_number
= generic_bignum
[2] + (generic_bignum
[3] << 16);
1723 load_register (counter
, reg
, &hi32
);
1724 if ((lo32
.X_add_number
& 0xffff0000) == 0)
1725 macro_build ((char *) NULL
, counter
, NULL
, "dsll32", "d,w,<", reg
,
1731 macro_build ((char *) NULL
, counter
, NULL
, "dsll", "d,w,<", reg
,
1734 mid16
.X_add_number
>>= 16;
1735 macro_build ((char *) NULL
, counter
, &mid16
, "ori", "t,r,i", reg
,
1736 reg
, (int) BFD_RELOC_LO16
);
1737 macro_build ((char *) NULL
, counter
, NULL
, "dsll", "d,w,<", reg
,
1740 if ((lo32
.X_add_number
& 0xffff) != 0)
1741 macro_build ((char *) NULL
, counter
, &lo32
, "ori", "t,r,i", reg
, reg
,
1742 (int) BFD_RELOC_LO16
);
1745 /* Load an address into a register. */
1748 load_address (counter
, reg
, ep
)
1755 if (ep
->X_op
!= O_constant
1756 && ep
->X_op
!= O_symbol
)
1758 as_bad ("expression too complex");
1759 ep
->X_op
= O_constant
;
1762 if (ep
->X_op
== O_constant
)
1764 load_register (counter
, reg
, ep
);
1768 if (mips_pic
== NO_PIC
)
1770 /* If this is a reference to a GP relative symbol, we want
1771 addiu $reg,$gp,<sym> (BFD_RELOC_MIPS_GPREL)
1773 lui $reg,<sym> (BFD_RELOC_HI16_S)
1774 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
1775 If we have an addend, we always use the latter form. */
1776 if (ep
->X_add_number
!= 0)
1781 macro_build ((char *) NULL
, counter
, ep
,
1782 mips_isa
< 3 ? "addiu" : "daddiu",
1783 "t,r,j", reg
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
1784 p
= frag_var (rs_machine_dependent
, 8, 0,
1785 RELAX_ENCODE (4, 8, 0, 4, 0, mips_warn_about_macros
),
1786 ep
->X_add_symbol
, (long) 0, (char *) NULL
);
1788 macro_build_lui (p
, counter
, ep
, reg
);
1791 macro_build (p
, counter
, ep
,
1792 mips_isa
< 3 ? "addiu" : "daddiu",
1793 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
1795 else if (mips_pic
== SVR4_PIC
)
1799 /* If this is a reference to an external symbol, we want
1800 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
1802 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
1804 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
1805 If there is a constant, it must be added in after. */
1806 ex
.X_add_number
= ep
->X_add_number
;
1807 ep
->X_add_number
= 0;
1809 macro_build ((char *) NULL
, counter
, ep
,
1810 mips_isa
< 3 ? "lw" : "ld",
1811 "t,o(b)", reg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
1812 macro_build ((char *) NULL
, counter
, (expressionS
*) NULL
, "nop", "");
1813 p
= frag_var (rs_machine_dependent
, 4, 0,
1814 RELAX_ENCODE (0, 4, -8, 0, 0, mips_warn_about_macros
),
1815 ep
->X_add_symbol
, (long) 0, (char *) NULL
);
1816 macro_build (p
, counter
, ep
,
1817 mips_isa
< 3 ? "addiu" : "daddiu",
1818 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
1819 if (ex
.X_add_number
!= 0)
1821 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
1822 as_bad ("PIC code offset overflow (max 16 signed bits)");
1823 ex
.X_op
= O_constant
;
1824 macro_build (p
, counter
, &ex
,
1825 mips_isa
< 3 ? "addiu" : "daddiu",
1826 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
1829 else if (mips_pic
== EMBEDDED_PIC
)
1832 addiu $reg,$gp,<sym> (BFD_RELOC_MIPS_GPREL)
1834 macro_build ((char *) NULL
, counter
, ep
,
1835 mips_isa
< 3 ? "addiu" : "daddiu",
1836 "t,r,j", reg
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
1844 * This routine implements the seemingly endless macro or synthesized
1845 * instructions and addressing modes in the mips assembly language. Many
1846 * of these macros are simple and are similar to each other. These could
1847 * probably be handled by some kind of table or grammer aproach instead of
1848 * this verbose method. Others are not simple macros but are more like
1849 * optimizing code generation.
1850 * One interesting optimization is when several store macros appear
1851 * consecutivly that would load AT with the upper half of the same address.
1852 * The ensuing load upper instructions are ommited. This implies some kind
1853 * of global optimization. We currently only optimize within a single macro.
1854 * For many of the load and store macros if the address is specified as a
1855 * constant expression in the first 64k of memory (ie ld $2,0x4000c) we
1856 * first load register 'at' with zero and use it as the base register. The
1857 * mips assembler simply uses register $zero. Just one tiny optimization
1862 struct mips_cl_insn
*ip
;
1864 register int treg
, sreg
, dreg
, breg
;
1879 bfd_reloc_code_real_type r
;
1881 int hold_mips_optimize
;
1883 treg
= (ip
->insn_opcode
>> 16) & 0x1f;
1884 dreg
= (ip
->insn_opcode
>> 11) & 0x1f;
1885 sreg
= breg
= (ip
->insn_opcode
>> 21) & 0x1f;
1886 mask
= ip
->insn_mo
->mask
;
1888 expr1
.X_op
= O_constant
;
1889 expr1
.X_op_symbol
= NULL
;
1890 expr1
.X_add_symbol
= NULL
;
1891 expr1
.X_add_number
= 1;
1903 mips_emit_delays ();
1905 mips_any_noreorder
= 1;
1907 expr1
.X_add_number
= 8;
1908 macro_build ((char *) NULL
, &icnt
, &expr1
, "bgez", "s,p", sreg
);
1910 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
1912 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
, sreg
, 0);
1913 macro_build ((char *) NULL
, &icnt
, NULL
,
1914 dbl
? "dsub" : "sub",
1915 "d,v,t", dreg
, 0, sreg
);
1938 if (imm_expr
.X_add_number
>= -0x8000 && imm_expr
.X_add_number
< 0x8000)
1940 macro_build ((char *) NULL
, &icnt
, &imm_expr
, s
, "t,r,j", treg
, sreg
,
1941 (int) BFD_RELOC_LO16
);
1944 load_register (&icnt
, AT
, &imm_expr
);
1945 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "d,v,t", treg
, sreg
, AT
);
1964 if (imm_expr
.X_add_number
>= 0 && imm_expr
.X_add_number
< 0x10000)
1966 if (mask
!= M_NOR_I
)
1967 macro_build ((char *) NULL
, &icnt
, &imm_expr
, s
, "t,r,i", treg
,
1968 sreg
, (int) BFD_RELOC_LO16
);
1971 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "ori", "t,r,i",
1972 treg
, sreg
, (int) BFD_RELOC_LO16
);
1973 macro_build ((char *) NULL
, &icnt
, NULL
, "nor", "d,v,t",
1979 load_register (&icnt
, AT
, &imm_expr
);
1980 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "d,v,t", treg
, sreg
, AT
);
1997 if (imm_expr
.X_add_number
== 0)
1999 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "s,t,p", sreg
,
2003 load_register (&icnt
, AT
, &imm_expr
);
2004 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "s,t,p", sreg
, AT
);
2012 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2013 likely
? "bgezl" : "bgez",
2019 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2020 likely
? "blezl" : "blez",
2024 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", AT
, sreg
, treg
);
2025 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2026 likely
? "beql" : "beq",
2033 /* check for > max integer */
2034 maxnum
= 0x7fffffff;
2042 if (imm_expr
.X_add_number
>= maxnum
2043 && (mips_isa
< 3 || sizeof (maxnum
) > 4))
2046 /* result is always false */
2049 as_warn ("Branch %s is always false (nop)", ip
->insn_mo
->name
);
2050 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
2054 as_warn ("Branch likely %s is always false", ip
->insn_mo
->name
);
2055 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "bnel",
2060 imm_expr
.X_add_number
++;
2064 if (mask
== M_BGEL_I
)
2066 if (imm_expr
.X_add_number
== 0)
2068 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2069 likely
? "bgezl" : "bgez",
2073 if (imm_expr
.X_add_number
== 1)
2075 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2076 likely
? "bgtzl" : "bgtz",
2080 maxnum
= 0x7fffffff;
2088 maxnum
= - maxnum
- 1;
2089 if (imm_expr
.X_add_number
<= maxnum
2090 && (mips_isa
< 3 || sizeof (maxnum
) > 4))
2093 /* result is always true */
2094 as_warn ("Branch %s is always true", ip
->insn_mo
->name
);
2095 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "b", "p");
2098 set_at (&icnt
, sreg
, 0);
2099 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2100 likely
? "beql" : "beq",
2111 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2112 likely
? "beql" : "beq",
2116 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", AT
, sreg
,
2118 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2119 likely
? "beql" : "beq",
2126 if (sreg
== 0 || imm_expr
.X_add_number
== -1)
2128 imm_expr
.X_add_number
++;
2132 if (mask
== M_BGEUL_I
)
2134 if (imm_expr
.X_add_number
== 0)
2136 if (imm_expr
.X_add_number
== 1)
2138 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2139 likely
? "bnel" : "bne",
2143 set_at (&icnt
, sreg
, 1);
2144 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2145 likely
? "beql" : "beq",
2154 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2155 likely
? "bgtzl" : "bgtz",
2161 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2162 likely
? "bltzl" : "bltz",
2166 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", AT
, treg
, sreg
);
2167 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2168 likely
? "bnel" : "bne",
2177 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2178 likely
? "bnel" : "bne",
2184 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", AT
, treg
,
2186 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2187 likely
? "bnel" : "bne",
2196 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2197 likely
? "blezl" : "blez",
2203 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2204 likely
? "bgezl" : "bgez",
2208 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", AT
, treg
, sreg
);
2209 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2210 likely
? "beql" : "beq",
2217 maxnum
= 0x7fffffff;
2225 if (imm_expr
.X_add_number
>= maxnum
2226 && (mips_isa
< 3 || sizeof (maxnum
) > 4))
2228 imm_expr
.X_add_number
++;
2232 if (mask
== M_BLTL_I
)
2234 if (imm_expr
.X_add_number
== 0)
2236 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2237 likely
? "bltzl" : "bltz",
2241 if (imm_expr
.X_add_number
== 1)
2243 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2244 likely
? "blezl" : "blez",
2248 set_at (&icnt
, sreg
, 0);
2249 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2250 likely
? "bnel" : "bne",
2259 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2260 likely
? "beql" : "beq",
2266 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", AT
, treg
,
2268 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2269 likely
? "beql" : "beq",
2276 if (sreg
== 0 || imm_expr
.X_add_number
== -1)
2278 imm_expr
.X_add_number
++;
2282 if (mask
== M_BLTUL_I
)
2284 if (imm_expr
.X_add_number
== 0)
2286 if (imm_expr
.X_add_number
== 1)
2288 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2289 likely
? "beql" : "beq",
2293 set_at (&icnt
, sreg
, 1);
2294 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2295 likely
? "bnel" : "bne",
2304 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2305 likely
? "bltzl" : "bltz",
2311 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2312 likely
? "bgtzl" : "bgtz",
2316 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", AT
, sreg
, treg
);
2317 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2318 likely
? "bnel" : "bne",
2329 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2330 likely
? "bnel" : "bne",
2334 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", AT
, sreg
,
2336 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2337 likely
? "bnel" : "bne",
2353 as_warn ("Divide by zero.");
2355 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", 0, 0);
2357 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 7);
2361 mips_emit_delays ();
2363 mips_any_noreorder
= 1;
2364 macro_build ((char *) NULL
, &icnt
, NULL
,
2365 dbl
? "ddiv" : "div",
2366 "z,s,t", sreg
, treg
);
2368 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", treg
, 0);
2371 expr1
.X_add_number
= 8;
2372 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", treg
, 0);
2373 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
2374 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 7);
2376 expr1
.X_add_number
= -1;
2377 macro_build ((char *) NULL
, &icnt
, &expr1
,
2378 dbl
? "daddiu" : "addiu",
2379 "t,r,j", AT
, 0, (int) BFD_RELOC_LO16
);
2380 expr1
.X_add_number
= mips_trap
? (dbl
? 12 : 8) : (dbl
? 20 : 16);
2381 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", treg
, AT
);
2384 expr1
.X_add_number
= 1;
2385 macro_build ((char *) NULL
, &icnt
, &expr1
, "daddiu", "t,r,j", AT
, 0,
2386 (int) BFD_RELOC_LO16
);
2387 macro_build ((char *) NULL
, &icnt
, NULL
, "dsll32", "d,w,<", AT
, AT
,
2392 expr1
.X_add_number
= 0x80000000;
2393 macro_build ((char *) NULL
, &icnt
, &expr1
, "lui", "t,u", AT
,
2394 (int) BFD_RELOC_HI16
);
2397 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", sreg
, AT
);
2400 expr1
.X_add_number
= 8;
2401 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", sreg
, AT
);
2402 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
2403 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 6);
2406 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d", dreg
);
2445 if (imm_expr
.X_add_number
== 0)
2447 as_warn ("Divide by zero.");
2449 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", 0, 0);
2451 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 7);
2454 if (imm_expr
.X_add_number
== 1)
2456 if (strcmp (s2
, "mflo") == 0)
2457 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
,
2460 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
, 0);
2463 if (imm_expr
.X_add_number
== -1
2464 && s
[strlen (s
) - 1] != 'u')
2466 if (strcmp (s2
, "mflo") == 0)
2469 macro_build ((char *) NULL
, &icnt
, NULL
, "dneg", "d,w", dreg
,
2472 macro_build ((char *) NULL
, &icnt
, NULL
, "neg", "d,w", dreg
,
2476 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
, 0);
2480 load_register (&icnt
, AT
, &imm_expr
);
2481 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "z,s,t", sreg
, AT
);
2482 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "d", dreg
);
2501 mips_emit_delays ();
2503 mips_any_noreorder
= 1;
2504 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "z,s,t", sreg
, treg
);
2506 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", treg
, 0);
2509 expr1
.X_add_number
= 8;
2510 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", treg
, 0);
2511 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
2512 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 7);
2515 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "d", dreg
);
2519 /* Load the address of a symbol into a register. If breg is not
2520 zero, we then add a base register to it. */
2522 /* When generating embedded PIC code, we permit expressions of
2525 where bar is an address in the .text section. These are used
2526 when getting the addresses of functions. We don't permit
2527 X_add_number to be non-zero, because if the symbol is
2528 external the relaxing code needs to know that any addend is
2529 purely the offset to X_op_symbol. */
2530 if (mips_pic
== EMBEDDED_PIC
2531 && offset_expr
.X_op
== O_subtract
2532 && now_seg
== text_section
2533 && (offset_expr
.X_op_symbol
->sy_value
.X_op
== O_constant
2534 ? S_GET_SEGMENT (offset_expr
.X_op_symbol
) == text_section
2535 : (offset_expr
.X_op_symbol
->sy_value
.X_op
== O_symbol
2536 && (S_GET_SEGMENT (offset_expr
.X_op_symbol
2537 ->sy_value
.X_add_symbol
)
2540 && offset_expr
.X_add_number
== 0)
2542 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
2543 treg
, (int) BFD_RELOC_PCREL_HI16_S
);
2544 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2545 mips_isa
< 3 ? "addiu" : "daddiu",
2546 "t,r,j", treg
, treg
, (int) BFD_RELOC_PCREL_LO16
);
2550 if (offset_expr
.X_op
!= O_symbol
2551 && offset_expr
.X_op
!= O_constant
)
2553 as_bad ("expression too complex");
2554 offset_expr
.X_op
= O_constant
;
2568 if (offset_expr
.X_op
== O_constant
)
2569 load_register (&icnt
, tempreg
, &offset_expr
);
2570 else if (mips_pic
== NO_PIC
)
2572 /* If this is a reference to an GP relative symbol, we want
2573 addiu $tempreg,$gp,<sym> (BFD_RELOC_MIPS_GPREL)
2575 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
2576 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
2577 If we have a constant, we need two instructions anyhow,
2578 so we may as well always use the latter form. */
2579 if (offset_expr
.X_add_number
!= 0)
2584 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2585 mips_isa
< 3 ? "addiu" : "daddiu",
2586 "t,r,j", tempreg
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
2587 p
= frag_var (rs_machine_dependent
, 8, 0,
2588 RELAX_ENCODE (4, 8, 0, 4, 0,
2589 mips_warn_about_macros
),
2590 offset_expr
.X_add_symbol
, (long) 0,
2593 macro_build_lui (p
, &icnt
, &offset_expr
, tempreg
);
2596 macro_build (p
, &icnt
, &offset_expr
,
2597 mips_isa
< 3 ? "addiu" : "daddiu",
2598 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
2600 else if (mips_pic
== SVR4_PIC
)
2602 /* If this is a reference to an external symbol, and there
2603 is no constant, we want
2604 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
2605 For a local symbol, we want
2606 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
2608 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
2610 If we have a small constant, and this is a reference to
2611 an external symbol, we want
2612 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
2614 addiu $tempreg,$tempreg,<constant>
2615 For a local symbol, we want the same instruction
2616 sequence, but we output a BFD_RELOC_LO16 reloc on the
2619 If we have a large constant, and this is a reference to
2620 an external symbol, we want
2621 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
2622 lui $at,<hiconstant>
2623 addiu $at,$at,<loconstant>
2624 addu $tempreg,$tempreg,$at
2625 For a local symbol, we want the same instruction
2626 sequence, but we output a BFD_RELOC_LO16 reloc on the
2627 addiu instruction. */
2628 expr1
.X_add_number
= offset_expr
.X_add_number
;
2629 offset_expr
.X_add_number
= 0;
2631 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2632 mips_isa
< 3 ? "lw" : "ld",
2633 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
2634 if (expr1
.X_add_number
== 0)
2642 /* We're going to put in an addu instruction using
2643 tempreg, so we may as well insert the nop right
2645 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
2649 p
= frag_var (rs_machine_dependent
, 8 - off
, 0,
2650 RELAX_ENCODE (0, 8 - off
, -4 - off
, 4 - off
, 0,
2652 ? mips_warn_about_macros
2654 offset_expr
.X_add_symbol
, (long) 0,
2658 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
2661 macro_build (p
, &icnt
, &expr1
,
2662 mips_isa
< 3 ? "addiu" : "daddiu",
2663 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
2664 /* FIXME: If breg == 0, and the next instruction uses
2665 $tempreg, then if this variant case is used an extra
2666 nop will be generated. */
2668 else if (expr1
.X_add_number
>= -0x8000
2669 && expr1
.X_add_number
< 0x8000)
2671 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
2673 macro_build ((char *) NULL
, &icnt
, &expr1
,
2674 mips_isa
< 3 ? "addiu" : "daddiu",
2675 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
2676 (void) frag_var (rs_machine_dependent
, 0, 0,
2677 RELAX_ENCODE (0, 0, -12, -4, 0, 0),
2678 offset_expr
.X_add_symbol
, (long) 0,
2685 /* If we are going to add in a base register, and the
2686 target register and the base register are the same,
2687 then we are using AT as a temporary register. Since
2688 we want to load the constant into AT, we add our
2689 current AT (from the global offset table) and the
2690 register into the register now, and pretend we were
2691 not using a base register. */
2696 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
2698 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
2699 mips_isa
< 3 ? "addu" : "daddu",
2700 "d,v,t", treg
, AT
, breg
);
2706 /* Set mips_optimize around the lui instruction to avoid
2707 inserting an unnecessary nop after the lw. */
2708 hold_mips_optimize
= mips_optimize
;
2710 macro_build_lui ((char *) NULL
, &icnt
, &expr1
, AT
);
2711 mips_optimize
= hold_mips_optimize
;
2713 macro_build ((char *) NULL
, &icnt
, &expr1
,
2714 mips_isa
< 3 ? "addiu" : "daddiu",
2715 "t,r,j", AT
, AT
, (int) BFD_RELOC_LO16
);
2716 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
2717 mips_isa
< 3 ? "addu" : "daddu",
2718 "d,v,t", tempreg
, tempreg
, AT
);
2719 (void) frag_var (rs_machine_dependent
, 0, 0,
2720 RELAX_ENCODE (0, 0, -16 + off1
, -8, 0, 0),
2721 offset_expr
.X_add_symbol
, (long) 0,
2726 else if (mips_pic
== EMBEDDED_PIC
)
2729 addiu $tempreg,$gp,<sym> (BFD_RELOC_MIPS_GPREL)
2731 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2732 mips_isa
< 3 ? "addiu" : "daddiu",
2733 "t,r,j", tempreg
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
2739 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
2740 mips_isa
< 3 ? "addu" : "daddu",
2741 "d,v,t", treg
, tempreg
, breg
);
2749 /* The j instruction may not be used in PIC code, since it
2750 requires an absolute address. We convert it to a b
2752 if (mips_pic
== NO_PIC
)
2753 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "j", "a");
2755 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "b", "p");
2758 /* The jal instructions must be handled as macros because when
2759 generating PIC code they expand to multi-instruction
2760 sequences. Normally they are simple instructions. */
2765 if (mips_pic
== NO_PIC
2766 || mips_pic
== EMBEDDED_PIC
)
2767 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "jalr",
2769 else if (mips_pic
== SVR4_PIC
)
2771 if (sreg
!= PIC_CALL_REG
)
2772 as_warn ("MIPS PIC call to register other than $25");
2774 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "jalr",
2776 if (mips_cprestore_offset
< 0)
2777 as_warn ("No .cprestore pseudo-op used in PIC code");
2780 expr1
.X_add_number
= mips_cprestore_offset
;
2781 macro_build ((char *) NULL
, &icnt
, &expr1
,
2782 mips_isa
< 3 ? "lw" : "ld",
2783 "t,o(b)", GP
, (int) BFD_RELOC_LO16
, mips_frame_reg
);
2792 if (mips_pic
== NO_PIC
)
2793 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "jal", "a");
2794 else if (mips_pic
== SVR4_PIC
)
2796 /* If this is a reference to an external symbol, we want
2797 lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
2801 lw $gp,cprestore($sp)
2802 The cprestore value is set using the .cprestore
2803 pseudo-op. If the symbol is not external, we want
2804 lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
2806 addiu $25,$25,<sym> (BFD_RELOC_LO16)
2809 lw $gp,cprestore($sp)
2812 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2813 mips_isa
< 3 ? "lw" : "ld",
2814 "t,o(b)", PIC_CALL_REG
,
2815 (int) BFD_RELOC_MIPS_CALL16
, GP
);
2816 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
2817 p
= frag_var (rs_machine_dependent
, 4, 0,
2818 RELAX_ENCODE (0, 4, -8, 0, 0, 0),
2819 offset_expr
.X_add_symbol
, (long) 0, (char *) NULL
);
2820 macro_build (p
, &icnt
, &offset_expr
,
2821 mips_isa
< 3 ? "addiu" : "daddiu",
2822 "t,r,j", PIC_CALL_REG
, PIC_CALL_REG
,
2823 (int) BFD_RELOC_LO16
);
2824 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
2825 "jalr", "s", PIC_CALL_REG
);
2826 if (mips_cprestore_offset
< 0)
2827 as_warn ("No .cprestore pseudo-op used in PIC code");
2831 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
2833 expr1
.X_add_number
= mips_cprestore_offset
;
2834 macro_build ((char *) NULL
, &icnt
, &expr1
,
2835 mips_isa
< 3 ? "lw" : "ld",
2836 "t,o(b)", GP
, (int) BFD_RELOC_LO16
,
2840 else if (mips_pic
== EMBEDDED_PIC
)
2842 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "bal", "p");
2843 /* The linker may expand the call to a longer sequence which
2844 uses $at, so we must break rather than return. */
2920 if (breg
== treg
|| coproc
|| lr
)
2989 if (mask
== M_LWC1_AB
2990 || mask
== M_SWC1_AB
2991 || mask
== M_LDC1_AB
2992 || mask
== M_SDC1_AB
3001 if (offset_expr
.X_op
!= O_constant
3002 && offset_expr
.X_op
!= O_symbol
)
3004 as_bad ("expression too complex");
3005 offset_expr
.X_op
= O_constant
;
3008 /* A constant expression in PIC code can be handled just as it
3009 is in non PIC code. */
3010 if (mips_pic
== NO_PIC
3011 || offset_expr
.X_op
== O_constant
)
3013 /* If this is a reference to a GP relative symbol, and there
3014 is no base register, we want
3015 <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL)
3016 Otherwise, if there is no base register, we want
3017 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
3018 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
3019 If we have a constant, we need two instructions anyhow,
3020 so we always use the latter form.
3022 If we have a base register, and this is a reference to a
3023 GP relative symbol, we want
3024 addu $tempreg,$breg,$gp
3025 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GPREL)
3027 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
3028 addu $tempreg,$tempreg,$breg
3029 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
3030 With a constant we always use the latter case. */
3033 if (offset_expr
.X_add_number
!= 0)
3038 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
3039 treg
, (int) BFD_RELOC_MIPS_GPREL
, GP
);
3040 p
= frag_var (rs_machine_dependent
, 8, 0,
3041 RELAX_ENCODE (4, 8, 0, 4, 0,
3042 (mips_warn_about_macros
3043 || (used_at
&& mips_noat
))),
3044 offset_expr
.X_add_symbol
, (long) 0,
3048 macro_build_lui (p
, &icnt
, &offset_expr
, tempreg
);
3051 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
, treg
,
3052 (int) BFD_RELOC_LO16
, tempreg
);
3056 if (offset_expr
.X_add_number
!= 0)
3061 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3062 mips_isa
< 3 ? "addu" : "daddu",
3063 "d,v,t", tempreg
, breg
, GP
);
3064 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
3065 treg
, (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
3066 p
= frag_var (rs_machine_dependent
, 12, 0,
3067 RELAX_ENCODE (8, 12, 0, 8, 0, 0),
3068 offset_expr
.X_add_symbol
, (long) 0,
3071 macro_build_lui (p
, &icnt
, &offset_expr
, tempreg
);
3074 macro_build (p
, &icnt
, (expressionS
*) NULL
,
3075 mips_isa
< 3 ? "addu" : "daddu",
3076 "d,v,t", tempreg
, tempreg
, breg
);
3079 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
, treg
,
3080 (int) BFD_RELOC_LO16
, tempreg
);
3083 else if (mips_pic
== SVR4_PIC
)
3085 /* If this is a reference to an external symbol, we want
3086 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3088 <op> $treg,0($tempreg)
3090 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3092 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
3093 <op> $treg,0($tempreg)
3094 If there is a base register, we add it to $tempreg before
3095 the <op>. If there is a constant, we stick it in the
3096 <op> instruction. We don't handle constants larger than
3097 16 bits, because we have no way to load the upper 16 bits
3098 (actually, we could handle them for the subset of cases
3099 in which we are not using $at). */
3100 assert (offset_expr
.X_op
== O_symbol
);
3101 expr1
.X_add_number
= offset_expr
.X_add_number
;
3102 offset_expr
.X_add_number
= 0;
3103 if (expr1
.X_add_number
< -0x8000
3104 || expr1
.X_add_number
>= 0x8000)
3105 as_bad ("PIC code offset overflow (max 16 signed bits)");
3107 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3108 mips_isa
< 3 ? "lw" : "ld",
3109 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
3110 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
3111 p
= frag_var (rs_machine_dependent
, 4, 0,
3112 RELAX_ENCODE (0, 4, -8, 0, 0, 0),
3113 offset_expr
.X_add_symbol
, (long) 0,
3115 macro_build (p
, &icnt
, &offset_expr
,
3116 mips_isa
< 3 ? "addiu" : "daddiu",
3117 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
3119 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3120 mips_isa
< 3 ? "addu" : "daddu",
3121 "d,v,t", tempreg
, tempreg
, breg
);
3122 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
, treg
,
3123 (int) BFD_RELOC_LO16
, tempreg
);
3125 else if (mips_pic
== EMBEDDED_PIC
)
3127 /* If there is no base register, we want
3128 <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL)
3129 If there is a base register, we want
3130 addu $tempreg,$breg,$gp
3131 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GPREL)
3133 assert (offset_expr
.X_op
== O_symbol
);
3136 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
3137 treg
, (int) BFD_RELOC_MIPS_GPREL
, GP
);
3142 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3143 mips_isa
< 3 ? "addu" : "daddu",
3144 "d,v,t", tempreg
, breg
, GP
);
3145 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
3146 treg
, (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
3159 load_register (&icnt
, treg
, &imm_expr
);
3163 if (imm_expr
.X_op
== O_constant
)
3165 load_register (&icnt
, AT
, &imm_expr
);
3166 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3167 "mtc1", "t,G", AT
, treg
);
3172 assert (offset_expr
.X_op
== O_symbol
3173 && strcmp (segment_name (S_GET_SEGMENT
3174 (offset_expr
.X_add_symbol
)),
3176 && offset_expr
.X_add_number
== 0);
3177 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lwc1", "T,o(b)",
3178 treg
, (int) BFD_RELOC_MIPS_LITERAL
, GP
);
3183 /* We know that sym is in the .rdata section. First we get the
3184 upper 16 bits of the address. */
3185 if (mips_pic
== NO_PIC
)
3187 /* FIXME: This won't work for a 64 bit address. */
3188 macro_build_lui ((char *) NULL
, &icnt
, &offset_expr
, AT
);
3190 else if (mips_pic
== SVR4_PIC
)
3192 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3193 mips_isa
< 3 ? "lw" : "ld",
3194 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
3196 else if (mips_pic
== EMBEDDED_PIC
)
3198 /* For embedded PIC we pick up the entire address off $gp in
3199 a single instruction. */
3200 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3201 mips_isa
< 3 ? "addiu" : "daddiu",
3202 "t,r,j", AT
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
3203 offset_expr
.X_op
= O_constant
;
3204 offset_expr
.X_add_number
= 0;
3209 /* Now we load the register(s). */
3211 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "ld", "t,o(b)",
3212 treg
, (int) BFD_RELOC_LO16
, AT
);
3215 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lw", "t,o(b)",
3216 treg
, (int) BFD_RELOC_LO16
, AT
);
3219 /* FIXME: How in the world do we deal with the possible
3221 offset_expr
.X_add_number
+= 4;
3222 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lw", "t,o(b)",
3223 treg
+ 1, (int) BFD_RELOC_LO16
, AT
);
3227 /* To avoid confusion in tc_gen_reloc, we must ensure that this
3228 does not become a variant frag. */
3229 frag_wane (frag_now
);
3235 assert (offset_expr
.X_op
== O_symbol
3236 && offset_expr
.X_add_number
== 0);
3237 s
= segment_name (S_GET_SEGMENT (offset_expr
.X_add_symbol
));
3238 if (strcmp (s
, ".lit8") == 0)
3242 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "ldc1",
3243 "T,o(b)", treg
, (int) BFD_RELOC_MIPS_LITERAL
, GP
);
3247 r
= BFD_RELOC_MIPS_LITERAL
;
3252 assert (strcmp (s
, RDATA_SECTION_NAME
) == 0);
3253 if (mips_pic
== SVR4_PIC
)
3254 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3255 mips_isa
< 3 ? "lw" : "ld",
3256 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
3259 /* FIXME: This won't work for a 64 bit address. */
3260 macro_build_lui ((char *) NULL
, &icnt
, &offset_expr
, AT
);
3265 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "ldc1",
3266 "T,o(b)", treg
, (int) BFD_RELOC_LO16
, AT
);
3268 /* To avoid confusion in tc_gen_reloc, we must ensure
3269 that this does not become a variant frag. */
3270 frag_wane (frag_now
);
3281 /* Even on a big endian machine $fn comes before $fn+1. We have
3282 to adjust when loading from memory. */
3285 assert (mips_isa
< 2);
3286 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lwc1", "T,o(b)",
3287 byte_order
== LITTLE_ENDIAN
? treg
: treg
+ 1,
3289 /* FIXME: A possible overflow which I don't know how to deal
3291 offset_expr
.X_add_number
+= 4;
3292 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lwc1", "T,o(b)",
3293 byte_order
== LITTLE_ENDIAN
? treg
+ 1 : treg
,
3296 /* To avoid confusion in tc_gen_reloc, we must ensure that this
3297 does not become a variant frag. */
3298 frag_wane (frag_now
);
3307 * The MIPS assembler seems to check for X_add_number not
3308 * being double aligned and generating:
3311 * addiu at,at,%lo(foo+1)
3314 * But, the resulting address is the same after relocation so why
3315 * generate the extra instruction?
3362 if (offset_expr
.X_op
!= O_symbol
3363 && offset_expr
.X_op
!= O_constant
)
3365 as_bad ("expression too complex");
3366 offset_expr
.X_op
= O_constant
;
3369 /* Even on a big endian machine $fn comes before $fn+1. We have
3370 to adjust when loading from memory. We set coproc if we must
3371 load $fn+1 first. */
3372 if (byte_order
== LITTLE_ENDIAN
)
3375 if (mips_pic
== NO_PIC
3376 || offset_expr
.X_op
== O_constant
)
3378 /* If this is a reference to a GP relative symbol, we want
3379 <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL)
3380 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_MIPS_GPREL)
3381 If we have a base register, we use this
3383 <op> $treg,<sym>($at) (BFD_RELOC_MIPS_GPREL)
3384 <op> $treg+1,<sym>+4($at) (BFD_RELOC_MIPS_GPREL)
3385 If this is not a GP relative symbol, we want
3386 lui $at,<sym> (BFD_RELOC_HI16_S)
3387 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
3388 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
3389 If there is a base register, we add it to $at after the
3390 lui instruction. If there is a constant, we always use
3392 if (offset_expr
.X_add_number
!= 0)
3411 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3412 mips_isa
< 3 ? "addu" : "daddu",
3413 "d,v,t", AT
, breg
, GP
);
3419 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
3420 coproc
? treg
+ 1 : treg
,
3421 (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
3422 offset_expr
.X_add_number
+= 4;
3424 /* Set mips_optimize to 2 to avoid inserting an
3426 hold_mips_optimize
= mips_optimize
;
3428 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
3429 coproc
? treg
: treg
+ 1,
3430 (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
3431 mips_optimize
= hold_mips_optimize
;
3433 p
= frag_var (rs_machine_dependent
, 12 + off
, 0,
3434 RELAX_ENCODE (8 + off
, 12 + off
, 0, 4 + off
, 1,
3435 used_at
&& mips_noat
),
3436 offset_expr
.X_add_symbol
, (long) 0,
3439 /* We just generated two relocs. When tc_gen_reloc
3440 handles this case, it will skip the first reloc and
3441 handle the second. The second reloc already has an
3442 extra addend of 4, which we added above. We must
3443 subtract it out, and then subtract another 4 to make
3444 the first reloc come out right. The second reloc
3445 will come out right because we are going to add 4 to
3446 offset_expr when we build its instruction below. */
3447 offset_expr
.X_add_number
-= 8;
3448 offset_expr
.X_op
= O_constant
;
3450 macro_build_lui (p
, &icnt
, &offset_expr
, AT
);
3455 macro_build (p
, &icnt
, (expressionS
*) NULL
,
3456 mips_isa
< 3 ? "addu" : "daddu",
3457 "d,v,t", AT
, breg
, AT
);
3461 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
,
3462 coproc
? treg
+ 1 : treg
,
3463 (int) BFD_RELOC_LO16
, AT
);
3466 /* FIXME: How do we handle overflow here? */
3467 offset_expr
.X_add_number
+= 4;
3468 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
,
3469 coproc
? treg
: treg
+ 1,
3470 (int) BFD_RELOC_LO16
, AT
);
3472 else if (mips_pic
== SVR4_PIC
)
3476 /* If this is a reference to an external symbol, we want
3477 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3482 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3484 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
3485 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
3486 If there is a base register we add it to $at before the
3487 lwc1 instructions. If there is a constant we include it
3488 in the lwc1 instructions. */
3490 expr1
.X_add_number
= offset_expr
.X_add_number
;
3491 offset_expr
.X_add_number
= 0;
3492 if (expr1
.X_add_number
< -0x8000
3493 || expr1
.X_add_number
>= 0x8000 - 4)
3494 as_bad ("PIC code offset overflow (max 16 signed bits)");
3499 frag_grow (24 + off
);
3500 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3501 mips_isa
< 3 ? "lw" : "ld",
3502 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
3503 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
3505 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3506 mips_isa
< 3 ? "addu" : "daddu",
3507 "d,v,t", AT
, breg
, AT
);
3508 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
3509 coproc
? treg
+ 1 : treg
,
3510 (int) BFD_RELOC_LO16
, AT
);
3511 expr1
.X_add_number
+= 4;
3513 /* Set mips_optimize to 2 to avoid inserting an undesired
3515 hold_mips_optimize
= mips_optimize
;
3517 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
3518 coproc
? treg
: treg
+ 1,
3519 (int) BFD_RELOC_LO16
, AT
);
3520 mips_optimize
= hold_mips_optimize
;
3522 (void) frag_var (rs_machine_dependent
, 0, 0,
3523 RELAX_ENCODE (0, 0, -16 - off
, -8, 1, 0),
3524 offset_expr
.X_add_symbol
, (long) 0,
3527 else if (mips_pic
== EMBEDDED_PIC
)
3529 /* If there is no base register, we use
3530 <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL)
3531 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_MIPS_GPREL)
3532 If we have a base register, we use
3534 <op> $treg,<sym>($at) (BFD_RELOC_MIPS_GPREL)
3535 <op> $treg+1,<sym>+4($at) (BFD_RELOC_MIPS_GPREL)
3544 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3545 mips_isa
< 3 ? "addu" : "daddu",
3546 "d,v,t", AT
, breg
, GP
);
3551 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
3552 coproc
? treg
+ 1 : treg
,
3553 (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
3554 offset_expr
.X_add_number
+= 4;
3555 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
3556 coproc
? treg
: treg
+ 1,
3557 (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
3573 assert (mips_isa
< 3);
3574 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
3575 (int) BFD_RELOC_LO16
, breg
);
3576 offset_expr
.X_add_number
+= 4;
3577 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
+ 1,
3578 (int) BFD_RELOC_LO16
, breg
);
3580 #ifdef LOSING_COMPILER
3586 as_warn ("Macro used $at after \".set noat\"");
3591 struct mips_cl_insn
*ip
;
3593 register int treg
, sreg
, dreg
, breg
;
3608 bfd_reloc_code_real_type r
;
3611 treg
= (ip
->insn_opcode
>> 16) & 0x1f;
3612 dreg
= (ip
->insn_opcode
>> 11) & 0x1f;
3613 sreg
= breg
= (ip
->insn_opcode
>> 21) & 0x1f;
3614 mask
= ip
->insn_mo
->mask
;
3616 expr1
.X_op
= O_constant
;
3617 expr1
.X_op_symbol
= NULL
;
3618 expr1
.X_add_symbol
= NULL
;
3619 expr1
.X_add_number
= 1;
3623 #endif /* LOSING_COMPILER */
3628 macro_build ((char *) NULL
, &icnt
, NULL
,
3629 dbl
? "dmultu" : "multu",
3631 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
3637 /* The MIPS assembler some times generates shifts and adds. I'm
3638 not trying to be that fancy. GCC should do this for us
3640 load_register (&icnt
, AT
, &imm_expr
);
3641 macro_build ((char *) NULL
, &icnt
, NULL
,
3642 dbl
? "dmult" : "mult",
3644 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
3650 mips_emit_delays ();
3652 mips_any_noreorder
= 1;
3653 macro_build ((char *) NULL
, &icnt
, NULL
,
3654 dbl
? "dmult" : "mult",
3656 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
3657 macro_build ((char *) NULL
, &icnt
, NULL
,
3658 dbl
? "dsra32" : "sra",
3659 "d,w,<", dreg
, dreg
, 31);
3660 macro_build ((char *) NULL
, &icnt
, NULL
, "mfhi", "d", AT
);
3662 macro_build ((char *) NULL
, &icnt
, NULL
, "tne", "s,t", dreg
, AT
);
3665 expr1
.X_add_number
= 8;
3666 macro_build ((char *) NULL
, &icnt
, &expr1
, "beq", "s,t,p", dreg
, AT
);
3667 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
3668 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 6);
3671 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
3677 mips_emit_delays ();
3679 mips_any_noreorder
= 1;
3680 macro_build ((char *) NULL
, &icnt
, NULL
,
3681 dbl
? "dmultu" : "multu",
3683 macro_build ((char *) NULL
, &icnt
, NULL
, "mfhi", "d", AT
);
3684 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
3686 macro_build ((char *) NULL
, &icnt
, NULL
, "tne", "s,t", AT
, 0);
3689 expr1
.X_add_number
= 8;
3690 macro_build ((char *) NULL
, &icnt
, &expr1
, "beq", "s,t,p", AT
, 0);
3691 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
3692 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 6);
3698 macro_build ((char *) NULL
, &icnt
, NULL
, "subu", "d,v,t", AT
, 0, treg
);
3699 macro_build ((char *) NULL
, &icnt
, NULL
, "srlv", "d,t,s", AT
, sreg
, AT
);
3700 macro_build ((char *) NULL
, &icnt
, NULL
, "sllv", "d,t,s", dreg
, sreg
,
3702 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
3706 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", AT
, sreg
,
3707 imm_expr
.X_add_number
& 0x1f);
3708 macro_build ((char *) NULL
, &icnt
, NULL
, "srl", "d,w,<", dreg
, sreg
,
3709 (0 - imm_expr
.X_add_number
) & 0x1f);
3710 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
3714 macro_build ((char *) NULL
, &icnt
, NULL
, "subu", "d,v,t", AT
, 0, treg
);
3715 macro_build ((char *) NULL
, &icnt
, NULL
, "sllv", "d,t,s", AT
, sreg
, AT
);
3716 macro_build ((char *) NULL
, &icnt
, NULL
, "srlv", "d,t,s", dreg
, sreg
,
3718 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
3722 macro_build ((char *) NULL
, &icnt
, NULL
, "srl", "d,w,<", AT
, sreg
,
3723 imm_expr
.X_add_number
& 0x1f);
3724 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", dreg
, sreg
,
3725 (0 - imm_expr
.X_add_number
) & 0x1f);
3726 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
3730 assert (mips_isa
< 2);
3731 /* Even on a big endian machine $fn comes before $fn+1. We have
3732 to adjust when storing to memory. */
3733 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "swc1", "T,o(b)",
3734 byte_order
== LITTLE_ENDIAN
? treg
: treg
+ 1,
3735 (int) BFD_RELOC_LO16
, breg
);
3736 offset_expr
.X_add_number
+= 4;
3737 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "swc1", "T,o(b)",
3738 byte_order
== LITTLE_ENDIAN
? treg
+ 1 : treg
,
3739 (int) BFD_RELOC_LO16
, breg
);
3744 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
3745 treg
, (int) BFD_RELOC_LO16
);
3747 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
3748 sreg
, (int) BFD_RELOC_LO16
);
3751 macro_build ((char *) NULL
, &icnt
, NULL
, "xor", "d,v,t", dreg
,
3753 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
3754 dreg
, (int) BFD_RELOC_LO16
);
3759 if (imm_expr
.X_add_number
== 0)
3761 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
3762 sreg
, (int) BFD_RELOC_LO16
);
3767 as_warn ("Instruction %s: result is always false",
3769 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
, 0);
3772 if (imm_expr
.X_add_number
>= 0 && imm_expr
.X_add_number
< 0x10000)
3774 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "xori", "t,r,i", dreg
,
3775 sreg
, (int) BFD_RELOC_LO16
);
3778 else if (imm_expr
.X_add_number
> -0x8000 && imm_expr
.X_add_number
< 0)
3780 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
3781 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
3782 mips_isa
< 3 ? "addiu" : "daddiu",
3783 "t,r,j", dreg
, sreg
,
3784 (int) BFD_RELOC_LO16
);
3789 load_register (&icnt
, AT
, &imm_expr
);
3790 macro_build ((char *) NULL
, &icnt
, NULL
, "xor", "d,v,t", dreg
,
3794 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
, dreg
,
3795 (int) BFD_RELOC_LO16
);
3800 case M_SGE
: /* sreg >= treg <==> not (sreg < treg) */
3806 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, sreg
, treg
);
3807 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
3808 (int) BFD_RELOC_LO16
);
3811 case M_SGE_I
: /* sreg >= I <==> not (sreg < I) */
3813 if (imm_expr
.X_add_number
>= -0x8000 && imm_expr
.X_add_number
< 0x8000)
3815 macro_build ((char *) NULL
, &icnt
, &expr1
,
3816 mask
== M_SGE_I
? "slti" : "sltiu",
3817 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
3822 load_register (&icnt
, AT
, &imm_expr
);
3823 macro_build ((char *) NULL
, &icnt
, NULL
,
3824 mask
== M_SGE_I
? "slt" : "sltu",
3825 "d,v,t", dreg
, sreg
, AT
);
3828 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
3829 (int) BFD_RELOC_LO16
);
3834 case M_SGT
: /* sreg > treg <==> treg < sreg */
3840 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, treg
, sreg
);
3843 case M_SGT_I
: /* sreg > I <==> I < sreg */
3849 load_register (&icnt
, AT
, &imm_expr
);
3850 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, AT
, sreg
);
3853 case M_SLE
: /* sreg <= treg <==> treg >= sreg <==> not (treg < sreg) */
3859 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, treg
, sreg
);
3860 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
3861 (int) BFD_RELOC_LO16
);
3864 case M_SLE_I
: /* sreg <= I <==> I >= sreg <==> not (I < sreg) */
3870 load_register (&icnt
, AT
, &imm_expr
);
3871 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, AT
, sreg
);
3872 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
3873 (int) BFD_RELOC_LO16
);
3877 if (imm_expr
.X_add_number
>= -0x8000 && imm_expr
.X_add_number
< 0x8000)
3879 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "slti", "t,r,j",
3880 dreg
, sreg
, (int) BFD_RELOC_LO16
);
3883 load_register (&icnt
, AT
, &imm_expr
);
3884 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", dreg
, sreg
, AT
);
3888 if (imm_expr
.X_add_number
>= -0x8000 && imm_expr
.X_add_number
< 0x8000)
3890 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "sltiu", "t,r,j",
3891 dreg
, sreg
, (int) BFD_RELOC_LO16
);
3894 load_register (&icnt
, AT
, &imm_expr
);
3895 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, sreg
,
3901 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0,
3904 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0,
3908 macro_build ((char *) NULL
, &icnt
, NULL
, "xor", "d,v,t", dreg
,
3910 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0,
3916 if (imm_expr
.X_add_number
== 0)
3918 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0,
3924 as_warn ("Instruction %s: result is always true",
3926 macro_build ((char *) NULL
, &icnt
, &expr1
,
3927 mips_isa
< 3 ? "addiu" : "daddiu",
3928 "t,r,j", dreg
, 0, (int) BFD_RELOC_LO16
);
3931 if (imm_expr
.X_add_number
>= 0 && imm_expr
.X_add_number
< 0x10000)
3933 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "xori", "t,r,i",
3934 dreg
, sreg
, (int) BFD_RELOC_LO16
);
3937 else if (imm_expr
.X_add_number
> -0x8000 && imm_expr
.X_add_number
< 0)
3939 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
3940 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
3941 mips_isa
< 3 ? "addiu" : "daddiu",
3942 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
3947 load_register (&icnt
, AT
, &imm_expr
);
3948 macro_build ((char *) NULL
, &icnt
, NULL
, "xor", "d,v,t", dreg
,
3952 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0, dreg
);
3960 if (imm_expr
.X_add_number
> -0x8000 && imm_expr
.X_add_number
<= 0x8000)
3962 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
3963 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
3964 dbl
? "daddi" : "addi",
3965 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
3968 load_register (&icnt
, AT
, &imm_expr
);
3969 macro_build ((char *) NULL
, &icnt
, NULL
,
3970 dbl
? "dsub" : "sub",
3971 "d,v,t", dreg
, sreg
, AT
);
3977 if (imm_expr
.X_add_number
> -0x8000 && imm_expr
.X_add_number
<= 0x8000)
3979 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
3980 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
3981 dbl
? "daddiu" : "addiu",
3982 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
3985 load_register (&icnt
, AT
, &imm_expr
);
3986 macro_build ((char *) NULL
, &icnt
, NULL
,
3987 dbl
? "dsubu" : "subu",
3988 "d,v,t", dreg
, sreg
, AT
);
4009 load_register (&icnt
, AT
, &imm_expr
);
4010 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "s,t", sreg
, AT
);
4015 assert (mips_isa
< 2);
4016 sreg
= (ip
->insn_opcode
>> 11) & 0x1f; /* floating reg */
4017 dreg
= (ip
->insn_opcode
>> 06) & 0x1f; /* floating reg */
4020 * Is the double cfc1 instruction a bug in the mips assembler;
4021 * or is there a reason for it?
4023 mips_emit_delays ();
4025 mips_any_noreorder
= 1;
4026 macro_build ((char *) NULL
, &icnt
, NULL
, "cfc1", "t,G", treg
, 31);
4027 macro_build ((char *) NULL
, &icnt
, NULL
, "cfc1", "t,G", treg
, 31);
4028 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "");
4029 expr1
.X_add_number
= 3;
4030 macro_build ((char *) NULL
, &icnt
, &expr1
, "ori", "t,r,i", AT
, treg
,
4031 (int) BFD_RELOC_LO16
);
4032 expr1
.X_add_number
= 2;
4033 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", AT
, AT
,
4034 (int) BFD_RELOC_LO16
);
4035 macro_build ((char *) NULL
, &icnt
, NULL
, "ctc1", "t,G", AT
, 31);
4036 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "");
4037 macro_build ((char *) NULL
, &icnt
, NULL
,
4038 mask
== M_TRUNCWD
? "cvt.w.d" : "cvt.w.s", "D,S", dreg
, sreg
);
4039 macro_build ((char *) NULL
, &icnt
, NULL
, "ctc1", "t,G", treg
, 31);
4040 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "");
4050 if (offset_expr
.X_add_number
>= 0x7fff)
4051 as_bad ("operand overflow");
4052 /* avoid load delay */
4053 if (byte_order
== LITTLE_ENDIAN
)
4054 offset_expr
.X_add_number
+= 1;
4055 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
4056 (int) BFD_RELOC_LO16
, breg
);
4057 if (byte_order
== LITTLE_ENDIAN
)
4058 offset_expr
.X_add_number
-= 1;
4060 offset_expr
.X_add_number
+= 1;
4061 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lbu", "t,o(b)", AT
,
4062 (int) BFD_RELOC_LO16
, breg
);
4063 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", treg
, treg
, 8);
4064 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", treg
, treg
, AT
);
4077 if (offset_expr
.X_add_number
>= 0x8000 - off
)
4078 as_bad ("operand overflow");
4079 if (byte_order
== LITTLE_ENDIAN
)
4080 offset_expr
.X_add_number
+= off
;
4081 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
4082 (int) BFD_RELOC_LO16
, breg
);
4083 if (byte_order
== LITTLE_ENDIAN
)
4084 offset_expr
.X_add_number
-= off
;
4086 offset_expr
.X_add_number
+= off
;
4087 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s2
, "t,o(b)", treg
,
4088 (int) BFD_RELOC_LO16
, breg
);
4101 load_address (&icnt
, AT
, &offset_expr
);
4102 if (byte_order
== LITTLE_ENDIAN
)
4103 expr1
.X_add_number
= off
;
4105 expr1
.X_add_number
= 0;
4106 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, "t,o(b)", treg
,
4107 (int) BFD_RELOC_LO16
, AT
);
4108 if (byte_order
== LITTLE_ENDIAN
)
4109 expr1
.X_add_number
= 0;
4111 expr1
.X_add_number
= off
;
4112 macro_build ((char *) NULL
, &icnt
, &expr1
, s2
, "t,o(b)", treg
,
4113 (int) BFD_RELOC_LO16
, AT
);
4118 load_address (&icnt
, AT
, &offset_expr
);
4119 if (byte_order
== BIG_ENDIAN
)
4120 expr1
.X_add_number
= 0;
4121 macro_build ((char *) NULL
, &icnt
, &expr1
,
4122 mask
== M_ULH_A
? "lb" : "lbu", "t,o(b)", treg
,
4123 (int) BFD_RELOC_LO16
, AT
);
4124 if (byte_order
== BIG_ENDIAN
)
4125 expr1
.X_add_number
= 1;
4127 expr1
.X_add_number
= 0;
4128 macro_build ((char *) NULL
, &icnt
, &expr1
, "lbu", "t,o(b)", AT
,
4129 (int) BFD_RELOC_LO16
, AT
);
4130 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", treg
,
4132 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", treg
,
4137 if (offset_expr
.X_add_number
>= 0x7fff)
4138 as_bad ("operand overflow");
4139 if (byte_order
== BIG_ENDIAN
)
4140 offset_expr
.X_add_number
+= 1;
4141 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "sb", "t,o(b)", treg
,
4142 (int) BFD_RELOC_LO16
, breg
);
4143 macro_build ((char *) NULL
, &icnt
, NULL
, "srl", "d,w,<", AT
, treg
, 8);
4144 if (byte_order
== BIG_ENDIAN
)
4145 offset_expr
.X_add_number
-= 1;
4147 offset_expr
.X_add_number
+= 1;
4148 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "sb", "t,o(b)", AT
,
4149 (int) BFD_RELOC_LO16
, breg
);
4162 if (offset_expr
.X_add_number
>= 0x8000 - off
)
4163 as_bad ("operand overflow");
4164 if (byte_order
== LITTLE_ENDIAN
)
4165 offset_expr
.X_add_number
+= off
;
4166 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
4167 (int) BFD_RELOC_LO16
, breg
);
4168 if (byte_order
== LITTLE_ENDIAN
)
4169 offset_expr
.X_add_number
-= off
;
4171 offset_expr
.X_add_number
+= off
;
4172 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s2
, "t,o(b)", treg
,
4173 (int) BFD_RELOC_LO16
, breg
);
4186 load_address (&icnt
, AT
, &offset_expr
);
4187 if (byte_order
== LITTLE_ENDIAN
)
4188 expr1
.X_add_number
= off
;
4190 expr1
.X_add_number
= 0;
4191 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, "t,o(b)", treg
,
4192 (int) BFD_RELOC_LO16
, AT
);
4193 if (byte_order
== LITTLE_ENDIAN
)
4194 expr1
.X_add_number
= 0;
4196 expr1
.X_add_number
= off
;
4197 macro_build ((char *) NULL
, &icnt
, &expr1
, s2
, "t,o(b)", treg
,
4198 (int) BFD_RELOC_LO16
, AT
);
4202 load_address (&icnt
, AT
, &offset_expr
);
4203 if (byte_order
== LITTLE_ENDIAN
)
4204 expr1
.X_add_number
= 0;
4205 macro_build ((char *) NULL
, &icnt
, &expr1
, "sb", "t,o(b)", treg
,
4206 (int) BFD_RELOC_LO16
, AT
);
4207 macro_build ((char *) NULL
, &icnt
, NULL
, "srl", "d,w,<", treg
,
4209 if (byte_order
== LITTLE_ENDIAN
)
4210 expr1
.X_add_number
= 1;
4212 expr1
.X_add_number
= 0;
4213 macro_build ((char *) NULL
, &icnt
, &expr1
, "sb", "t,o(b)", treg
,
4214 (int) BFD_RELOC_LO16
, AT
);
4215 if (byte_order
== LITTLE_ENDIAN
)
4216 expr1
.X_add_number
= 0;
4218 expr1
.X_add_number
= 1;
4219 macro_build ((char *) NULL
, &icnt
, &expr1
, "lbu", "t,o(b)", AT
,
4220 (int) BFD_RELOC_LO16
, AT
);
4221 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", treg
,
4223 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", treg
,
4228 as_bad ("Macro %s not implemented yet", ip
->insn_mo
->name
);
4232 as_warn ("Macro used $at after \".set noat\"");
4237 This routine assembles an instruction into its binary format. As a side
4238 effect it sets one of the global variables imm_reloc or offset_reloc to the
4239 type of relocation to do if one of the operands is an address expression.
4244 struct mips_cl_insn
*ip
;
4249 struct mips_opcode
*insn
;
4252 unsigned int lastregno
= 0;
4257 for (s
= str
; islower (*s
) || (*s
>= '0' && *s
<= '3') || *s
== '.'; ++s
)
4269 as_fatal ("Unknown opcode: `%s'", str
);
4271 if ((insn
= (struct mips_opcode
*) hash_find (op_hash
, str
)) == NULL
)
4273 as_warn ("`%s' not in hash table.", str
);
4274 insn_error
= "ERROR: Unrecognized opcode";
4282 assert (strcmp (insn
->name
, str
) == 0);
4284 if (insn
->pinfo
== INSN_MACRO
)
4285 insn_isa
= insn
->match
;
4286 else if ((insn
->pinfo
& INSN_ISA
) == INSN_ISA2
)
4288 else if ((insn
->pinfo
& INSN_ISA
) == INSN_ISA3
)
4293 if (insn_isa
> mips_isa
4294 || ((insn
->pinfo
& INSN_ISA
) == INSN_4650
4297 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
]
4298 && strcmp (insn
->name
, insn
[1].name
) == 0)
4303 as_warn ("Instruction not supported on this processor");
4307 ip
->insn_opcode
= insn
->match
;
4308 for (args
= insn
->args
;; ++args
)
4314 case '\0': /* end of args */
4327 ip
->insn_opcode
|= lastregno
<< 21;
4332 ip
->insn_opcode
|= lastregno
<< 16;
4336 ip
->insn_opcode
|= lastregno
<< 11;
4342 /* handle optional base register.
4343 Either the base register is omitted or
4344 we must have a left paren. */
4345 /* this is dependent on the next operand specifier
4346 is a 'b' for base register */
4347 assert (args
[1] == 'b');
4351 case ')': /* these must match exactly */
4356 case '<': /* must be at least one digit */
4358 * According to the manual, if the shift amount is greater
4359 * than 31 or less than 0 the the shift amount should be
4360 * mod 32. In reality the mips assembler issues an error.
4361 * We issue a warning and mask out all but the low 5 bits.
4363 my_getExpression (&imm_expr
, s
);
4364 check_absolute_expr (ip
, &imm_expr
);
4365 if ((unsigned long) imm_expr
.X_add_number
> 31)
4367 as_warn ("Improper shift amount (%ld)",
4368 (long) imm_expr
.X_add_number
);
4369 imm_expr
.X_add_number
= imm_expr
.X_add_number
& 0x1f;
4371 ip
->insn_opcode
|= imm_expr
.X_add_number
<< 6;
4372 imm_expr
.X_op
= O_absent
;
4376 case '>': /* shift amount minus 32 */
4377 my_getExpression (&imm_expr
, s
);
4378 check_absolute_expr (ip
, &imm_expr
);
4379 if ((unsigned long) imm_expr
.X_add_number
< 32
4380 || (unsigned long) imm_expr
.X_add_number
> 63)
4382 ip
->insn_opcode
|= (imm_expr
.X_add_number
- 32) << 6;
4383 imm_expr
.X_op
= O_absent
;
4387 case 'k': /* cache code */
4388 my_getExpression (&imm_expr
, s
);
4389 check_absolute_expr (ip
, &imm_expr
);
4390 if ((unsigned long) imm_expr
.X_add_number
> 31)
4392 as_warn ("Invalid cahce opcode (%lu)",
4393 (unsigned long) imm_expr
.X_add_number
);
4394 imm_expr
.X_add_number
&= 0x1f;
4396 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_CACHE
;
4397 imm_expr
.X_op
= O_absent
;
4401 case 'c': /* break code */
4402 my_getExpression (&imm_expr
, s
);
4403 check_absolute_expr (ip
, &imm_expr
);
4404 if ((unsigned) imm_expr
.X_add_number
> 1023)
4405 as_warn ("Illegal break code (%ld)",
4406 (long) imm_expr
.X_add_number
);
4407 ip
->insn_opcode
|= imm_expr
.X_add_number
<< 16;
4408 imm_expr
.X_op
= O_absent
;
4412 case 'B': /* syscall code */
4413 my_getExpression (&imm_expr
, s
);
4414 check_absolute_expr (ip
, &imm_expr
);
4415 if ((unsigned) imm_expr
.X_add_number
> 0xfffff)
4416 as_warn ("Illegal syscall code (%ld)",
4417 (long) imm_expr
.X_add_number
);
4418 ip
->insn_opcode
|= imm_expr
.X_add_number
<< 6;
4419 imm_expr
.X_op
= O_absent
;
4423 case 'C': /* Coprocessor code */
4424 my_getExpression (&imm_expr
, s
);
4425 check_absolute_expr (ip
, &imm_expr
);
4426 if ((unsigned long) imm_expr
.X_add_number
>= (1<<25))
4428 as_warn ("Coproccesor code > 25 bits (%ld)",
4429 (long) imm_expr
.X_add_number
);
4430 imm_expr
.X_add_number
&= ((1<<25) - 1);
4432 ip
->insn_opcode
|= imm_expr
.X_add_number
;
4433 imm_expr
.X_op
= O_absent
;
4437 case 'b': /* base register */
4438 case 'd': /* destination register */
4439 case 's': /* source register */
4440 case 't': /* target register */
4441 case 'r': /* both target and source */
4442 case 'v': /* both dest and source */
4443 case 'w': /* both dest and target */
4444 case 'E': /* coprocessor target register */
4445 case 'G': /* coprocessor destination register */
4446 case 'x': /* ignore register name */
4447 case 'z': /* must be zero register */
4461 while (isdigit (*s
));
4463 as_bad ("Invalid register number (%d)", regno
);
4465 else if (*args
== 'E' || *args
== 'G')
4469 if (s
[1] == 'f' && s
[2] == 'p')
4474 else if (s
[1] == 's' && s
[2] == 'p')
4479 else if (s
[1] == 'g' && s
[2] == 'p')
4484 else if (s
[1] == 'a' && s
[2] == 't')
4489 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '0')
4494 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '1')
4502 if (regno
== AT
&& ! mips_noat
)
4503 as_warn ("Used $at without \".set noat\"");
4509 if (c
== 'r' || c
== 'v' || c
== 'w')
4516 /* 'z' only matches $0. */
4517 if (c
== 'z' && regno
!= 0)
4525 ip
->insn_opcode
|= regno
<< 21;
4529 ip
->insn_opcode
|= regno
<< 11;
4534 ip
->insn_opcode
|= regno
<< 16;
4537 /* This case exists because on the r3000 trunc
4538 expands into a macro which requires a gp
4539 register. On the r6000 or r4000 it is
4540 assembled into a single instruction which
4541 ignores the register. Thus the insn version
4542 is MIPS_ISA2 and uses 'x', and the macro
4543 version is MIPS_ISA1 and uses 't'. */
4546 /* This case is for the div instruction, which
4547 acts differently if the destination argument
4548 is $0. This only matches $0, and is checked
4549 outside the switch. */
4560 ip
->insn_opcode
|= lastregno
<< 21;
4563 ip
->insn_opcode
|= lastregno
<< 16;
4568 case 'D': /* floating point destination register */
4569 case 'S': /* floating point source register */
4570 case 'T': /* floating point target register */
4574 if (s
[0] == '$' && s
[1] == 'f' && isdigit (s
[2]))
4584 while (isdigit (*s
));
4587 as_bad ("Invalid float register number (%d)", regno
);
4589 if ((regno
& 1) != 0
4591 && ! (strcmp (str
, "mtc1") == 0 ||
4592 strcmp (str
, "mfc1") == 0 ||
4593 strcmp (str
, "lwc1") == 0 ||
4594 strcmp (str
, "swc1") == 0))
4595 as_warn ("Float register should be even, was %d",
4603 if (c
== 'V' || c
== 'W')
4613 ip
->insn_opcode
|= regno
<< 6;
4617 ip
->insn_opcode
|= regno
<< 11;
4621 ip
->insn_opcode
|= regno
<< 16;
4629 ip
->insn_opcode
|= lastregno
<< 11;
4632 ip
->insn_opcode
|= lastregno
<< 16;
4638 my_getExpression (&imm_expr
, s
);
4639 if (imm_expr
.X_op
!= O_big
)
4640 check_absolute_expr (ip
, &imm_expr
);
4645 my_getExpression (&offset_expr
, s
);
4646 imm_reloc
= BFD_RELOC_32
;
4658 unsigned char temp
[8];
4660 unsigned int length
;
4665 /* These only appear as the last operand in an
4666 instruction, and every instruction that accepts
4667 them in any variant accepts them in all variants.
4668 This means we don't have to worry about backing out
4669 any changes if the instruction does not match.
4671 The difference between them is the size of the
4672 floating point constant and where it goes. For 'F'
4673 and 'L' the constant is 64 bits; for 'f' and 'l' it
4674 is 32 bits. Where the constant is placed is based
4675 on how the MIPS assembler does things:
4678 f -- immediate value
4681 The .lit4 and .lit8 sections are only used if
4682 permitted by the -G argument.
4684 When generating embedded PIC code, we use the
4685 .lit8 section but not the .lit4 section (we can do
4686 .lit4 inline easily; we need to put .lit8
4687 somewhere in the data segment, and using .lit8
4688 permits the linker to eventually combine identical
4691 f64
= *args
== 'F' || *args
== 'L';
4693 save_in
= input_line_pointer
;
4694 input_line_pointer
= s
;
4695 err
= md_atof (f64
? 'd' : 'f', (char *) temp
, &len
);
4697 s
= input_line_pointer
;
4698 input_line_pointer
= save_in
;
4699 if (err
!= NULL
&& *err
!= '\0')
4701 as_bad ("Bad floating point constant: %s", err
);
4702 memset (temp
, '\0', sizeof temp
);
4703 length
= f64
? 8 : 4;
4706 assert (length
== (f64
? 8 : 4));
4711 && (mips_pic
== EMBEDDED_PIC
4712 || g_switch_value
< 4)
4716 imm_expr
.X_op
= O_constant
;
4717 if (byte_order
== LITTLE_ENDIAN
)
4718 imm_expr
.X_add_number
=
4719 (((((((int) temp
[3] << 8)
4724 imm_expr
.X_add_number
=
4725 (((((((int) temp
[0] << 8)
4732 const char *newname
;
4735 /* Switch to the right section. */
4737 subseg
= now_subseg
;
4740 default: /* unused default case avoids warnings. */
4742 newname
= RDATA_SECTION_NAME
;
4744 if (g_switch_value
>= 8)
4749 newname
= RDATA_SECTION_NAME
;
4753 assert (g_switch_value
>= 4);
4758 new_seg
= subseg_new (newname
, (subsegT
) 0);
4759 frag_align (*args
== 'l' ? 2 : 3, 0);
4761 record_alignment (new_seg
, 4);
4763 record_alignment (new_seg
, *args
== 'l' ? 2 : 3);
4766 as_bad ("Can't use floating point insn in this section");
4768 /* Set the argument to the current address in the
4770 offset_expr
.X_op
= O_symbol
;
4771 offset_expr
.X_add_symbol
=
4772 symbol_new ("L0\001", now_seg
,
4773 (valueT
) frag_now_fix (), frag_now
);
4774 offset_expr
.X_add_number
= 0;
4776 /* Put the floating point number into the section. */
4777 p
= frag_more ((int) length
);
4778 memcpy (p
, temp
, length
);
4780 /* Switch back to the original section. */
4781 subseg_set (seg
, subseg
);
4786 case 'i': /* 16 bit unsigned immediate */
4787 case 'j': /* 16 bit signed immediate */
4788 imm_reloc
= BFD_RELOC_LO16
;
4789 c
= my_getSmallExpression (&imm_expr
, s
);
4794 if (imm_expr
.X_op
== O_constant
)
4795 imm_expr
.X_add_number
=
4796 (imm_expr
.X_add_number
>> 16) & 0xffff;
4798 imm_reloc
= BFD_RELOC_HI16_S
;
4800 imm_reloc
= BFD_RELOC_HI16
;
4803 else if (imm_expr
.X_op
!= O_big
)
4804 check_absolute_expr (ip
, &imm_expr
);
4807 if (imm_expr
.X_op
== O_big
4808 || imm_expr
.X_add_number
< 0
4809 || imm_expr
.X_add_number
>= 0x10000)
4811 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
4812 !strcmp (insn
->name
, insn
[1].name
))
4814 as_bad ("16 bit expression not in range 0..65535");
4822 /* The upper bound should be 0x8000, but
4823 unfortunately the MIPS assembler accepts numbers
4824 from 0x8000 to 0xffff and sign extends them, and
4825 we want to be compatible. We only permit this
4826 extended range for an instruction which does not
4827 provide any further alternates, since those
4828 alternates may handle other cases. People should
4829 use the numbers they mean, rather than relying on
4830 a mysterious sign extension. */
4831 more
= (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
4832 strcmp (insn
->name
, insn
[1].name
) == 0);
4837 if (imm_expr
.X_op
== O_big
4838 || imm_expr
.X_add_number
< -0x8000
4839 || imm_expr
.X_add_number
>= max
)
4843 as_bad ("16 bit expression not in range -32768..32767");
4849 case 'o': /* 16 bit offset */
4850 c
= my_getSmallExpression (&offset_expr
, s
);
4852 /* If this value won't fit into a 16 bit offset, then go
4853 find a macro that will generate the 32 bit offset
4854 code pattern. As a special hack, we accept the
4855 difference of two local symbols as a constant. This
4856 is required to suppose embedded PIC switches, which
4857 use an instruction which looks like
4858 lw $4,$L12-$LS12($4)
4859 The problem with handling this in a more general
4860 fashion is that the macro function doesn't expect to
4861 see anything which can be handled in a single
4862 constant instruction. */
4864 && (offset_expr
.X_op
!= O_constant
4865 || offset_expr
.X_add_number
>= 0x8000
4866 || offset_expr
.X_add_number
< -0x8000)
4867 && (mips_pic
!= EMBEDDED_PIC
4868 || offset_expr
.X_op
!= O_subtract
4869 || now_seg
!= text_section
4870 || (S_GET_SEGMENT (offset_expr
.X_op_symbol
)
4874 offset_reloc
= BFD_RELOC_LO16
;
4875 if (c
== 'h' || c
== 'H')
4877 assert (offset_expr
.X_op
== O_constant
);
4878 offset_expr
.X_add_number
=
4879 (offset_expr
.X_add_number
>> 16) & 0xffff;
4884 case 'p': /* pc relative offset */
4885 offset_reloc
= BFD_RELOC_16_PCREL_S2
;
4886 my_getExpression (&offset_expr
, s
);
4890 case 'u': /* upper 16 bits */
4891 c
= my_getSmallExpression (&imm_expr
, s
);
4892 if (imm_expr
.X_op
== O_constant
4893 && (imm_expr
.X_add_number
< 0
4894 || imm_expr
.X_add_number
>= 0x10000))
4895 as_bad ("lui expression not in range 0..65535");
4896 imm_reloc
= BFD_RELOC_LO16
;
4901 if (imm_expr
.X_op
== O_constant
)
4902 imm_expr
.X_add_number
=
4903 (imm_expr
.X_add_number
>> 16) & 0xffff;
4905 imm_reloc
= BFD_RELOC_HI16_S
;
4907 imm_reloc
= BFD_RELOC_HI16
;
4913 case 'a': /* 26 bit address */
4914 my_getExpression (&offset_expr
, s
);
4916 offset_reloc
= BFD_RELOC_MIPS_JMP
;
4920 fprintf (stderr
, "bad char = '%c'\n", *args
);
4925 /* Args don't match. */
4926 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
4927 !strcmp (insn
->name
, insn
[1].name
))
4933 insn_error
= "ERROR: Illegal operands";
4942 my_getSmallExpression (ep
, str
)
4953 ((str
[1] == 'h' && str
[2] == 'i')
4954 || (str
[1] == 'H' && str
[2] == 'I')
4955 || (str
[1] == 'l' && str
[2] == 'o'))
4967 * A small expression may be followed by a base register.
4968 * Scan to the end of this operand, and then back over a possible
4969 * base register. Then scan the small expression up to that
4970 * point. (Based on code in sparc.c...)
4972 for (sp
= str
; *sp
&& *sp
!= ','; sp
++)
4974 if (sp
- 4 >= str
&& sp
[-1] == RP
)
4976 if (isdigit (sp
[-2]))
4978 for (sp
-= 3; sp
>= str
&& isdigit (*sp
); sp
--)
4980 if (*sp
== '$' && sp
> str
&& sp
[-1] == LP
)
4986 else if (sp
- 5 >= str
4989 && ((sp
[-3] == 'f' && sp
[-2] == 'p')
4990 || (sp
[-3] == 's' && sp
[-2] == 'p')
4991 || (sp
[-3] == 'g' && sp
[-2] == 'p')
4992 || (sp
[-3] == 'a' && sp
[-2] == 't')))
4998 /* no expression means zero offset */
5001 /* %xx(reg) is an error */
5002 ep
->X_op
= O_absent
;
5007 ep
->X_op
= O_constant
;
5010 ep
->X_add_symbol
= NULL
;
5011 ep
->X_op_symbol
= NULL
;
5012 ep
->X_add_number
= 0;
5017 my_getExpression (ep
, str
);
5024 my_getExpression (ep
, str
);
5025 return c
; /* => %hi or %lo encountered */
5029 my_getExpression (ep
, str
)
5035 save_in
= input_line_pointer
;
5036 input_line_pointer
= str
;
5038 expr_end
= input_line_pointer
;
5039 input_line_pointer
= save_in
;
5042 /* Turn a string in input_line_pointer into a floating point constant
5043 of type type, and store the appropriate bytes in *litP. The number
5044 of LITTLENUMS emitted is stored in *sizeP . An error message is
5045 returned, or NULL on OK. */
5048 md_atof (type
, litP
, sizeP
)
5054 LITTLENUM_TYPE words
[4];
5070 return "bad call to md_atof";
5073 t
= atof_ieee (input_line_pointer
, type
, words
);
5075 input_line_pointer
= t
;
5079 if (byte_order
== LITTLE_ENDIAN
)
5081 for (i
= prec
- 1; i
>= 0; i
--)
5083 md_number_to_chars (litP
, (valueT
) words
[i
], 2);
5089 for (i
= 0; i
< prec
; i
++)
5091 md_number_to_chars (litP
, (valueT
) words
[i
], 2);
5100 md_number_to_chars (buf
, val
, n
)
5108 number_to_chars_littleendian (buf
, val
, n
);
5112 number_to_chars_bigendian (buf
, val
, n
);
5121 CONST
char *md_shortopts
= "O::g::G:";
5123 CONST
char *md_shortopts
= "O::g::";
5125 struct option md_longopts
[] = {
5126 #define OPTION_MIPS1 (OPTION_MD_BASE + 1)
5127 {"mips0", no_argument
, NULL
, OPTION_MIPS1
},
5128 {"mips1", no_argument
, NULL
, OPTION_MIPS1
},
5129 #define OPTION_MIPS2 (OPTION_MD_BASE + 2)
5130 {"mips2", no_argument
, NULL
, OPTION_MIPS2
},
5131 #define OPTION_MIPS3 (OPTION_MD_BASE + 3)
5132 {"mips3", no_argument
, NULL
, OPTION_MIPS3
},
5133 #define OPTION_MCPU (OPTION_MD_BASE + 4)
5134 {"mcpu", required_argument
, NULL
, OPTION_MCPU
},
5135 #define OPTION_MEMBEDDED_PIC (OPTION_MD_BASE + 5)
5136 {"membedded-pic", no_argument
, NULL
, OPTION_MEMBEDDED_PIC
},
5137 #define OPTION_TRAP (OPTION_MD_BASE + 8)
5138 {"trap", no_argument
, NULL
, OPTION_TRAP
},
5139 {"no-break", no_argument
, NULL
, OPTION_TRAP
},
5140 #define OPTION_BREAK (OPTION_MD_BASE + 9)
5141 {"break", no_argument
, NULL
, OPTION_BREAK
},
5142 {"no-trap", no_argument
, NULL
, OPTION_BREAK
},
5143 #define OPTION_EB (OPTION_MD_BASE + 10)
5144 {"EB", no_argument
, NULL
, OPTION_EB
},
5145 #define OPTION_EL (OPTION_MD_BASE + 11)
5146 {"EL", no_argument
, NULL
, OPTION_EL
},
5147 #define OPTION_M4650 (OPTION_MD_BASE + 12)
5148 {"m4650", no_argument
, NULL
, OPTION_M4650
},
5149 #define OPTION_NO_M4650 (OPTION_MD_BASE + 13)
5150 {"no-m4650", no_argument
, NULL
, OPTION_NO_M4650
},
5153 #define OPTION_CALL_SHARED (OPTION_MD_BASE + 6)
5154 {"KPIC", no_argument
, NULL
, OPTION_CALL_SHARED
},
5155 {"call_shared", no_argument
, NULL
, OPTION_CALL_SHARED
},
5156 #define OPTION_NON_SHARED (OPTION_MD_BASE + 7)
5157 {"non_shared", no_argument
, NULL
, OPTION_NON_SHARED
},
5160 {NULL
, no_argument
, NULL
, 0}
5162 size_t md_longopts_size
= sizeof(md_longopts
);
5165 md_parse_option (c
, arg
)
5180 byte_order
= BIG_ENDIAN
;
5182 mips_target_format
= "a.out-mips-big";
5185 mips_target_format
= "ecoff-bigmips";
5188 mips_target_format
= "elf32-bigmips";
5193 byte_order
= LITTLE_ENDIAN
;
5195 mips_target_format
= "a.out-mips-little";
5198 mips_target_format
= "ecoff-littlemips";
5201 mips_target_format
= "elf32-littlemips";
5206 if (arg
&& arg
[1] == '0')
5213 if (arg
== NULL
|| arg
[1] == '2')
5239 /* Identify the processor type */
5241 if (strcmp (p
, "default") == 0
5242 || strcmp (p
, "DEFAULT") == 0)
5246 if (*p
== 'r' || *p
== 'R')
5253 if (strcmp (p
, "2000") == 0
5254 || strcmp (p
, "2k") == 0
5255 || strcmp (p
, "2K") == 0)
5260 if (strcmp (p
, "3000") == 0
5261 || strcmp (p
, "3k") == 0
5262 || strcmp (p
, "3K") == 0)
5267 if (strcmp (p
, "4000") == 0
5268 || strcmp (p
, "4k") == 0
5269 || strcmp (p
, "4K") == 0)
5271 else if (strcmp (p
, "4400") == 0)
5273 else if (strcmp (p
, "4600") == 0)
5275 else if (strcmp (p
, "4650") == 0)
5284 if (strcmp (p
, "6000") == 0
5285 || strcmp (p
, "6k") == 0
5286 || strcmp (p
, "6K") == 0)
5291 if (strcmp (p
, "orion") == 0)
5298 as_bad ("invalid architecture -mcpu=%s", arg
);
5309 case OPTION_NO_M4650
:
5313 case OPTION_MEMBEDDED_PIC
:
5314 mips_pic
= EMBEDDED_PIC
;
5318 as_bad ("-G may not be used with embedded PIC code");
5321 g_switch_value
= 0x7fffffff;
5326 /* When generating ELF code, we permit -KPIC and -call_shared to
5327 select SVR4_PIC, and -non_shared to select no PIC. This is
5328 intended to be compatible with Irix 5. */
5329 case OPTION_CALL_SHARED
:
5330 mips_pic
= SVR4_PIC
;
5331 if (g_switch_seen
&& g_switch_value
!= 0)
5333 as_bad ("-G may not be used with SVR4 PIC code");
5339 case OPTION_NON_SHARED
:
5342 #endif /* OBJ_ELF */
5346 if (mips_pic
== SVR4_PIC
|| mips_pic
== EMBEDDED_PIC
)
5348 as_bad ("-G may not be used with SVR4 or embedded PIC code");
5352 g_switch_value
= atoi (arg
);
5365 md_show_usage (stream
)
5370 -membedded-pic generate embedded position independent code\n\
5371 -EB generate big endian output\n\
5372 -EL generate little endian output\n\
5373 -g, -g2 do not remove uneeded NOPs or swap branches\n\
5374 -G NUM allow referencing objects up to NUM bytes\n\
5375 implicitly with the gp register [default 8]\n");
5377 -mips1, -mcpu=r{2,3}000 generate code for r2000 and r3000\n\
5378 -mips2, -mcpu=r6000 generate code for r6000\n\
5379 -mips3, -mcpu=r4000 generate code for r4000\n\
5380 -O0 remove unneeded NOPs, do not swap branches\n\
5381 -O remove unneeded NOPs and swap branches\n\
5382 --trap, --no-break trap exception on div by 0 and mult overflow\n\
5383 --break, --no-trap break exception on div by 0 and mult overflow\n");
5386 -KPIC, -call_shared generate SVR4 position independent code\n\
5387 -non_shared do not generate position independent code\n");
5392 md_pcrel_from (fixP
)
5396 if (fixP
->fx_addsy
!= (symbolS
*) NULL
5397 && ! S_IS_DEFINED (fixP
->fx_addsy
))
5399 /* This makes a branch to an undefined symbol be a branch to the
5400 current location. */
5405 /* return the address of the delay slot */
5406 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
5409 /* This is called by emit_expr via TC_CONS_FIX_NEW when creating a
5410 reloc for a cons. We could use the definition there, except that
5411 we want to handle 64 bit relocs specially. */
5414 cons_fix_new_mips (frag
, where
, nbytes
, exp
)
5417 unsigned int nbytes
;
5420 /* If we are assembling in 32 bit mode, turn an 8 byte reloc into a
5422 FIXME: There is no way to select anything but 32 bit mode right
5426 if (byte_order
== BIG_ENDIAN
)
5431 if (nbytes
!= 2 && nbytes
!= 4)
5432 as_bad ("Unsupported reloc size %d", nbytes
);
5434 fix_new_exp (frag_now
, where
, (int) nbytes
, exp
, 0,
5435 nbytes
== 2 ? BFD_RELOC_16
: BFD_RELOC_32
);
5438 /* When generating embedded PIC code we need to use a special
5439 relocation to represent the difference of two symbols in the .text
5440 section (switch tables use a difference of this sort). See
5441 include/coff/mips.h for details. This macro checks whether this
5442 fixup requires the special reloc. */
5443 #define SWITCH_TABLE(fixp) \
5444 ((fixp)->fx_r_type == BFD_RELOC_32 \
5445 && (fixp)->fx_addsy != NULL \
5446 && (fixp)->fx_subsy != NULL \
5447 && S_GET_SEGMENT ((fixp)->fx_addsy) == text_section \
5448 && S_GET_SEGMENT ((fixp)->fx_subsy) == text_section)
5450 /* When generating embedded PIC code we must keep all PC relative
5451 relocations, in case the linker has to relax a call. We also need
5452 to keep relocations for switch table entries. */
5456 mips_force_relocation (fixp
)
5459 return (mips_pic
== EMBEDDED_PIC
5461 || SWITCH_TABLE (fixp
)
5462 || fixp
->fx_r_type
== BFD_RELOC_PCREL_HI16_S
5463 || fixp
->fx_r_type
== BFD_RELOC_PCREL_LO16
));
5466 /* Apply a fixup to the object file. */
5469 md_apply_fix (fixP
, valueP
)
5476 assert (fixP
->fx_size
== 4 || fixP
->fx_r_type
== BFD_RELOC_16
);
5479 fixP
->fx_addnumber
= value
; /* Remember value for tc_gen_reloc */
5481 if (fixP
->fx_addsy
== NULL
&& ! fixP
->fx_pcrel
)
5484 switch (fixP
->fx_r_type
)
5486 case BFD_RELOC_MIPS_JMP
:
5487 case BFD_RELOC_HI16
:
5488 case BFD_RELOC_HI16_S
:
5489 case BFD_RELOC_MIPS_GPREL
:
5490 case BFD_RELOC_MIPS_LITERAL
:
5491 case BFD_RELOC_MIPS_CALL16
:
5492 case BFD_RELOC_MIPS_GOT16
:
5493 case BFD_RELOC_MIPS_GPREL32
:
5495 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
5496 "Invalid PC relative reloc");
5497 /* Nothing needed to do. The value comes from the reloc entry */
5500 case BFD_RELOC_PCREL_HI16_S
:
5501 /* The addend for this is tricky if it is internal, so we just
5502 do everything here rather than in bfd_perform_relocation. */
5503 if ((fixP
->fx_addsy
->bsym
->flags
& BSF_SECTION_SYM
) == 0)
5505 /* For an external symbol adjust by the address to make it
5506 pcrel_offset. We use the address of the RELLO reloc
5507 which follows this one. */
5508 value
+= (fixP
->fx_next
->fx_frag
->fr_address
5509 + fixP
->fx_next
->fx_where
);
5514 buf
= (unsigned char *) fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
5515 if (byte_order
== BIG_ENDIAN
)
5517 md_number_to_chars (buf
, value
, 2);
5520 case BFD_RELOC_PCREL_LO16
:
5521 /* The addend for this is tricky if it is internal, so we just
5522 do everything here rather than in bfd_perform_relocation. */
5523 if ((fixP
->fx_addsy
->bsym
->flags
& BSF_SECTION_SYM
) == 0)
5524 value
+= fixP
->fx_frag
->fr_address
+ fixP
->fx_where
;
5525 buf
= (unsigned char *) fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
5526 if (byte_order
== BIG_ENDIAN
)
5528 md_number_to_chars (buf
, value
, 2);
5532 /* If we are deleting this reloc entry, we must fill in the
5533 value now. This can happen if we have a .word which is not
5534 resolved when it appears but is later defined. We also need
5535 to fill in the value if this is an embedded PIC switch table
5538 || (mips_pic
== EMBEDDED_PIC
&& SWITCH_TABLE (fixP
)))
5539 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
,
5544 /* If we are deleting this reloc entry, we must fill in the
5546 assert (fixP
->fx_size
== 2);
5548 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
,
5552 case BFD_RELOC_LO16
:
5553 /* When handling an embedded PIC switch statement, we can wind
5554 up deleting a LO16 reloc. See the 'o' case in mips_ip. */
5557 if (value
< -0x8000 || value
> 0x7fff)
5558 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
5559 "relocation overflow");
5560 buf
= (unsigned char *) fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
5561 if (byte_order
== BIG_ENDIAN
)
5563 md_number_to_chars (buf
, value
, 2);
5567 case BFD_RELOC_16_PCREL_S2
:
5569 * We need to save the bits in the instruction since fixup_segment()
5570 * might be deleting the relocation entry (i.e., a branch within
5571 * the current segment).
5574 as_warn_where (fixP
->fx_file
, fixP
->fx_line
,
5575 "Branch to odd address (%lx)", value
);
5578 /* update old instruction data */
5579 buf
= (unsigned char *) (fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
);
5583 insn
= (buf
[3] << 24) | (buf
[2] << 16) | (buf
[1] << 8) | buf
[0];
5587 insn
= (buf
[0] << 24) | (buf
[1] << 16) | (buf
[2] << 8) | buf
[3];
5595 if (value
>= -0x8000 && value
< 0x8000)
5596 insn
|= value
& 0xffff;
5599 /* The branch offset is too large. If this is an
5600 unconditional branch, and we are not generating PIC code,
5601 we can convert it to an absolute jump instruction. */
5602 if (mips_pic
== NO_PIC
5604 && fixP
->fx_frag
->fr_address
>= text_section
->vma
5605 && (fixP
->fx_frag
->fr_address
5606 < text_section
->vma
+ text_section
->_raw_size
)
5607 && ((insn
& 0xffff0000) == 0x10000000 /* beq $0,$0 */
5608 || (insn
& 0xffff0000) == 0x04010000 /* bgez $0 */
5609 || (insn
& 0xffff0000) == 0x04110000)) /* bgezal $0 */
5611 if ((insn
& 0xffff0000) == 0x04110000) /* bgezal $0 */
5612 insn
= 0x0c000000; /* jal */
5614 insn
= 0x08000000; /* j */
5615 fixP
->fx_r_type
= BFD_RELOC_MIPS_JMP
;
5617 fixP
->fx_addsy
= section_symbol (text_section
);
5618 fixP
->fx_addnumber
= (value
<< 2) + md_pcrel_from (fixP
);
5622 /* FIXME. It would be possible in principle to handle
5623 conditional branches which overflow. They could be
5624 transformed into a branch around a jump. This would
5625 require setting up variant frags for each different
5626 branch type. The native MIPS assembler attempts to
5627 handle these cases, but it appears to do it
5629 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
5630 "Relocation overflow");
5634 md_number_to_chars ((char *) buf
, (valueT
) insn
, 4);
5649 const struct mips_opcode
*p
;
5650 int treg
, sreg
, dreg
, shamt
;
5655 for (i
= 0; i
< NUMOPCODES
; ++i
)
5657 p
= &mips_opcodes
[i
];
5658 if (((oc
& p
->mask
) == p
->match
) && (p
->pinfo
!= INSN_MACRO
))
5660 printf ("%08lx %s\t", oc
, p
->name
);
5661 treg
= (oc
>> 16) & 0x1f;
5662 sreg
= (oc
>> 21) & 0x1f;
5663 dreg
= (oc
>> 11) & 0x1f;
5664 shamt
= (oc
>> 6) & 0x1f;
5666 for (args
= p
->args
;; ++args
)
5677 printf ("%c", *args
);
5681 assert (treg
== sreg
);
5682 printf ("$%d,$%d", treg
, sreg
);
5687 printf ("$%d", dreg
);
5692 printf ("$%d", treg
);
5696 printf ("0x%x", treg
);
5701 printf ("$%d", sreg
);
5705 printf ("0x%08lx", oc
& 0x1ffffff);
5717 printf ("$%d", shamt
);
5728 printf ("%08lx UNDEFINED\n", oc
);
5739 name
= input_line_pointer
;
5740 c
= get_symbol_end ();
5741 p
= (symbolS
*) symbol_find_or_make (name
);
5742 *input_line_pointer
= c
;
5746 /* Align the current frag to a given power of two. The MIPS assembler
5747 also automatically adjusts any preceding label. */
5750 mips_align (to
, fill
, label
)
5755 mips_emit_delays ();
5756 frag_align (to
, fill
);
5757 record_alignment (now_seg
, to
);
5760 assert (S_GET_SEGMENT (label
) == now_seg
);
5761 label
->sy_frag
= frag_now
;
5762 S_SET_VALUE (label
, (valueT
) frag_now_fix ());
5766 /* Align to a given power of two. .align 0 turns off the automatic
5767 alignment used by the data creating pseudo-ops. */
5774 register long temp_fill
;
5775 long max_alignment
= 15;
5779 o Note that the assembler pulls down any immediately preceeding label
5780 to the aligned address.
5781 o It's not documented but auto alignment is reinstated by
5782 a .align pseudo instruction.
5783 o Note also that after auto alignment is turned off the mips assembler
5784 issues an error on attempt to assemble an improperly aligned data item.
5789 temp
= get_absolute_expression ();
5790 if (temp
> max_alignment
)
5791 as_bad ("Alignment too large: %d. assumed.", temp
= max_alignment
);
5794 as_warn ("Alignment negative: 0 assumed.");
5797 if (*input_line_pointer
== ',')
5799 input_line_pointer
++;
5800 temp_fill
= get_absolute_expression ();
5807 mips_align (temp
, (int) temp_fill
, insn_label
);
5814 demand_empty_rest_of_line ();
5817 /* Handle .ascii and .asciiz. This just calls stringer and forgets
5818 that there was a previous instruction. */
5821 s_stringer (append_zero
)
5824 mips_emit_delays ();
5826 stringer (append_zero
);
5837 /* When generating embedded PIC code, we only use the .text, .lit8,
5838 .sdata and .sbss sections. We change the .data and .rdata
5839 pseudo-ops to use .sdata. */
5840 if (mips_pic
== EMBEDDED_PIC
5841 && (sec
== 'd' || sec
== 'r'))
5844 mips_emit_delays ();
5854 subseg_set (bss_section
, (subsegT
) get_absolute_expression ());
5855 demand_empty_rest_of_line ();
5860 seg
= subseg_new (RDATA_SECTION_NAME
,
5861 (subsegT
) get_absolute_expression ());
5863 bfd_set_section_flags (stdoutput
, seg
,
5869 bfd_set_section_alignment (stdoutput
, seg
, 4);
5871 demand_empty_rest_of_line ();
5872 #else /* ! defined (GPOPT) */
5873 as_bad ("No read only data section in this object file format");
5874 demand_empty_rest_of_line ();
5876 #endif /* ! defined (GPOPT) */
5881 seg
= subseg_new (".sdata", (subsegT
) get_absolute_expression ());
5883 bfd_set_section_flags (stdoutput
, seg
,
5884 SEC_ALLOC
| SEC_LOAD
| SEC_RELOC
| SEC_DATA
);
5885 bfd_set_section_alignment (stdoutput
, seg
, 4);
5887 demand_empty_rest_of_line ();
5889 #else /* ! defined (GPOPT) */
5890 as_bad ("Global pointers not supported; recompile -G 0");
5891 demand_empty_rest_of_line ();
5893 #endif /* ! defined (GPOPT) */
5901 /* Handle the ELF .section pseudo-op. This is a wrapper around
5908 mips_emit_delays ();
5909 obj_elf_section (x
);
5913 #endif /* OBJ_ELF */
5922 mips_emit_delays ();
5923 if (log_size
> 0 && auto_align
)
5924 mips_align (log_size
, 0, label
);
5926 cons (1 << log_size
);
5933 as_fatal ("Encountered `.err', aborting assembly");
5943 symbolP
= get_symbol ();
5944 if (*input_line_pointer
== ',')
5945 input_line_pointer
++;
5946 size
= get_absolute_expression ();
5947 S_SET_EXTERNAL (symbolP
);
5949 #ifdef ECOFF_DEBUGGING
5950 symbolP
->ecoff_extern_size
= size
;
5962 mips_emit_delays ();
5966 mips_align (3, 0, label
);
5968 mips_align (2, 0, label
);
5975 /* Handle .globl. We need to override it because on Irix 5 you are
5978 where foo is an undefined symbol, to mean that foo should be
5979 considered to be the address of a function. */
5989 name
= input_line_pointer
;
5990 c
= get_symbol_end ();
5991 symbolP
= symbol_find_or_make (name
);
5992 *input_line_pointer
= c
;
5994 if (! is_end_of_line
[(unsigned char) *input_line_pointer
])
5999 secname
= input_line_pointer
;
6000 c
= get_symbol_end ();
6001 sec
= bfd_get_section_by_name (stdoutput
, secname
);
6003 as_bad ("%s: no such section", secname
);
6004 *input_line_pointer
= c
;
6006 if (sec
!= NULL
&& (sec
->flags
& SEC_CODE
) != 0)
6007 symbolP
->bsym
->flags
|= BSF_FUNCTION
;
6010 S_SET_EXTERNAL (symbolP
);
6011 demand_empty_rest_of_line ();
6021 opt
= input_line_pointer
;
6022 c
= get_symbol_end ();
6026 /* FIXME: What does this mean? */
6028 else if (strncmp (opt
, "pic", 3) == 0)
6036 mips_pic
= SVR4_PIC
;
6038 as_bad (".option pic%d not supported", i
);
6041 if (mips_pic
== SVR4_PIC
)
6043 if (g_switch_seen
&& g_switch_value
!= 0)
6044 as_warn ("-G may not be used with SVR4 PIC code");
6046 bfd_set_gp_size (stdoutput
, 0);
6051 as_warn ("Unrecognized option \"%s\"", opt
);
6053 *input_line_pointer
= c
;
6054 demand_empty_rest_of_line ();
6061 char *name
= input_line_pointer
, ch
;
6063 while (!is_end_of_line
[(unsigned char) *input_line_pointer
])
6064 input_line_pointer
++;
6065 ch
= *input_line_pointer
;
6066 *input_line_pointer
= '\0';
6068 if (strcmp (name
, "reorder") == 0)
6072 prev_insn_unreordered
= 1;
6073 prev_prev_insn_unreordered
= 1;
6077 else if (strcmp (name
, "noreorder") == 0)
6079 mips_emit_delays ();
6081 mips_any_noreorder
= 1;
6083 else if (strcmp (name
, "at") == 0)
6087 else if (strcmp (name
, "noat") == 0)
6091 else if (strcmp (name
, "macro") == 0)
6093 mips_warn_about_macros
= 0;
6095 else if (strcmp (name
, "nomacro") == 0)
6097 if (mips_noreorder
== 0)
6098 as_bad ("`noreorder' must be set before `nomacro'");
6099 mips_warn_about_macros
= 1;
6101 else if (strcmp (name
, "move") == 0 || strcmp (name
, "novolatile") == 0)
6105 else if (strcmp (name
, "nomove") == 0 || strcmp (name
, "volatile") == 0)
6109 else if (strcmp (name
, "bopt") == 0)
6113 else if (strcmp (name
, "nobopt") == 0)
6117 else if (strncmp (name
, "mips", 4) == 0)
6121 /* Permit the user to change the ISA on the fly. Needless to
6122 say, misuse can cause serious problems. */
6123 isa
= atoi (name
+ 4);
6125 mips_isa
= file_mips_isa
;
6126 else if (isa
< 1 || isa
> 3)
6127 as_bad ("unknown ISA level");
6133 as_warn ("Tried to set unrecognized symbol: %s\n", name
);
6135 *input_line_pointer
= ch
;
6136 demand_empty_rest_of_line ();
6139 /* The same as the usual .space directive, except that we have to
6140 forget about any previous instruction. */
6143 s_mips_space (param
)
6146 mips_emit_delays ();
6151 /* Handle the .abicalls pseudo-op. I believe this is equivalent to
6152 .option pic2. It means to generate SVR4 PIC calls. */
6158 mips_pic
= SVR4_PIC
;
6160 if (g_switch_seen
&& g_switch_value
!= 0)
6161 as_warn ("-G may not be used with SVR4 PIC code");
6164 bfd_set_gp_size (stdoutput
, 0);
6165 demand_empty_rest_of_line ();
6168 /* Handle the .cpload pseudo-op. This is used when generating SVR4
6169 PIC code. It sets the $gp register for the function based on the
6170 function address, which is in the register named in the argument.
6171 This uses a relocation against _gp_disp, which is handled specially
6172 by the linker. The result is:
6173 lui $gp,%hi(_gp_disp)
6174 addiu $gp,$gp,%lo(_gp_disp)
6175 addu $gp,$gp,.cpload argument
6176 The .cpload argument is normally $25 == $t9. */
6185 /* If we are not generating SVR4 PIC code, .cpload is ignored. */
6186 if (mips_pic
!= SVR4_PIC
)
6192 /* .cpload should be a in .set noreorder section. */
6193 if (mips_noreorder
== 0)
6194 as_warn (".cpload not in noreorder section");
6197 ex
.X_add_symbol
= symbol_find_or_make ("_gp_disp");
6198 ex
.X_op_symbol
= NULL
;
6199 ex
.X_add_number
= 0;
6201 macro_build_lui ((char *) NULL
, &icnt
, &ex
, GP
);
6202 macro_build ((char *) NULL
, &icnt
, &ex
, "addiu", "t,r,j", GP
, GP
,
6203 (int) BFD_RELOC_LO16
);
6205 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "addu", "d,v,t",
6206 GP
, GP
, tc_get_register (0));
6208 demand_empty_rest_of_line ();
6211 /* Handle the .cprestore pseudo-op. This stores $gp into a given
6212 offset from $sp. The offset is remembered, and after making a PIC
6213 call $gp is restored from that location. */
6216 s_cprestore (ignore
)
6222 /* If we are not generating SVR4 PIC code, .cprestore is ignored. */
6223 if (mips_pic
!= SVR4_PIC
)
6229 mips_cprestore_offset
= get_absolute_expression ();
6231 ex
.X_op
= O_constant
;
6232 ex
.X_add_symbol
= NULL
;
6233 ex
.X_op_symbol
= NULL
;
6234 ex
.X_add_number
= mips_cprestore_offset
;
6236 macro_build ((char *) NULL
, &icnt
, &ex
,
6237 mips_isa
< 3 ? "sw" : "sd",
6238 "t,o(b)", GP
, (int) BFD_RELOC_LO16
, SP
);
6240 demand_empty_rest_of_line ();
6243 /* Handle the .gpword pseudo-op. This is used when generating PIC
6244 code. It generates a 32 bit GP relative reloc. */
6254 /* When not generating PIC code, this is treated as .word. */
6255 if (mips_pic
!= SVR4_PIC
)
6262 mips_emit_delays ();
6264 mips_align (2, 0, label
);
6269 if (ex
.X_op
!= O_symbol
|| ex
.X_add_number
!= 0)
6271 as_bad ("Unsupported use of .gpword");
6272 ignore_rest_of_line ();
6276 md_number_to_chars (p
, (valueT
) 0, 4);
6277 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 4, &ex
, 0,
6278 BFD_RELOC_MIPS_GPREL32
);
6280 demand_empty_rest_of_line ();
6283 /* Handle the .cpadd pseudo-op. This is used when dealing with switch
6284 tables in SVR4 PIC code. */
6293 /* This is ignored when not generating SVR4 PIC code. */
6294 if (mips_pic
!= SVR4_PIC
)
6300 /* Add $gp to the register named as an argument. */
6301 reg
= tc_get_register (0);
6302 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6303 mips_isa
< 3 ? "addu" : "daddu",
6304 "d,v,t", reg
, reg
, GP
);
6306 demand_empty_rest_of_line ();
6309 /* Parse a register string into a number. Called from the ECOFF code
6310 to parse .frame. The argument is non-zero if this is the frame
6311 register, so that we can record it in mips_frame_reg. */
6314 tc_get_register (frame
)
6320 if (*input_line_pointer
++ != '$')
6322 as_warn ("expected `$'");
6325 else if (isdigit ((unsigned char) *input_line_pointer
))
6327 reg
= get_absolute_expression ();
6328 if (reg
< 0 || reg
>= 32)
6330 as_warn ("Bad register number");
6336 if (strncmp (input_line_pointer
, "fp", 2) == 0)
6338 else if (strncmp (input_line_pointer
, "sp", 2) == 0)
6340 else if (strncmp (input_line_pointer
, "gp", 2) == 0)
6342 else if (strncmp (input_line_pointer
, "at", 2) == 0)
6346 as_warn ("Unrecognized register name");
6349 input_line_pointer
+= 2;
6352 mips_frame_reg
= reg
!= 0 ? reg
: SP
;
6357 md_section_align (seg
, addr
)
6361 int align
= bfd_get_section_alignment (stdoutput
, seg
);
6363 return ((addr
+ (1 << align
) - 1) & (-1 << align
));
6366 /* Estimate the size of a frag before relaxing. We are not really
6367 relaxing here, and the final size is encoded in the subtype
6372 md_estimate_size_before_relax (fragp
, segtype
)
6378 if (mips_pic
== NO_PIC
)
6381 const char *symname
;
6383 /* Find out whether this symbol can be referenced off the GP
6384 register. It can be if it is smaller than the -G size or if
6385 it is in the .sdata or .sbss section. Certain symbols can
6386 not be referenced off the GP, although it appears as though
6388 symname
= S_GET_NAME (fragp
->fr_symbol
);
6389 if (symname
!= (const char *) NULL
6390 && (strcmp (symname
, "eprol") == 0
6391 || strcmp (symname
, "etext") == 0
6392 || strcmp (symname
, "_gp") == 0
6393 || strcmp (symname
, "edata") == 0
6394 || strcmp (symname
, "_fbss") == 0
6395 || strcmp (symname
, "_fdata") == 0
6396 || strcmp (symname
, "_ftext") == 0
6397 || strcmp (symname
, "end") == 0
6398 || strcmp (symname
, "_gp_disp") == 0))
6400 else if (! S_IS_DEFINED (fragp
->fr_symbol
)
6401 && ((fragp
->fr_symbol
->ecoff_extern_size
!= 0
6402 && fragp
->fr_symbol
->ecoff_extern_size
<= g_switch_value
)
6403 || (S_GET_VALUE (fragp
->fr_symbol
) != 0
6404 && S_GET_VALUE (fragp
->fr_symbol
) <= g_switch_value
)))
6408 const char *segname
;
6410 segname
= segment_name (S_GET_SEGMENT (fragp
->fr_symbol
));
6411 assert (strcmp (segname
, ".lit8") != 0
6412 && strcmp (segname
, ".lit4") != 0);
6413 change
= (strcmp (segname
, ".sdata") != 0
6414 && strcmp (segname
, ".sbss") != 0);
6416 #else /* ! defined (GPOPT) */
6417 /* We are not optimizing for the GP register. */
6419 #endif /* ! defined (GPOPT) */
6421 else if (mips_pic
== SVR4_PIC
)
6423 asection
*symsec
= fragp
->fr_symbol
->bsym
->section
;
6425 /* This must duplicate the test in adjust_reloc_syms. */
6426 change
= (symsec
!= &bfd_und_section
6427 && symsec
!= &bfd_abs_section
6428 && ! bfd_is_com_section (symsec
));
6435 /* Record the offset to the first reloc in the fr_opcode field.
6436 This lets md_convert_frag and tc_gen_reloc know that the code
6437 must be expanded. */
6438 fragp
->fr_opcode
= (fragp
->fr_literal
6440 - RELAX_OLD (fragp
->fr_subtype
)
6441 + RELAX_RELOC1 (fragp
->fr_subtype
));
6442 /* FIXME: This really needs as_warn_where. */
6443 if (RELAX_WARN (fragp
->fr_subtype
))
6444 as_warn ("AT used after \".set noat\" or macro used after \".set nomacro\"");
6450 return RELAX_NEW (fragp
->fr_subtype
) - RELAX_OLD (fragp
->fr_subtype
);
6453 /* Translate internal representation of relocation info to BFD target
6457 tc_gen_reloc (section
, fixp
)
6461 static arelent
*retval
[4];
6464 reloc
= retval
[0] = (arelent
*) xmalloc (sizeof (arelent
));
6467 reloc
->sym_ptr_ptr
= &fixp
->fx_addsy
->bsym
;
6468 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
6470 if (mips_pic
== EMBEDDED_PIC
6471 && SWITCH_TABLE (fixp
))
6473 /* For a switch table entry we use a special reloc. The addend
6474 is actually the difference between the reloc address and the
6476 reloc
->addend
= reloc
->address
- S_GET_VALUE (fixp
->fx_subsy
);
6478 as_fatal ("Double check fx_r_type in tc-mips.c:tc_gen_reloc");
6480 fixp
->fx_r_type
= BFD_RELOC_GPREL32
;
6482 else if (fixp
->fx_r_type
== BFD_RELOC_PCREL_LO16
)
6484 /* We use a special addend for an internal RELLO reloc. */
6485 if (fixp
->fx_addsy
->bsym
->flags
& BSF_SECTION_SYM
)
6486 reloc
->addend
= reloc
->address
- S_GET_VALUE (fixp
->fx_subsy
);
6488 reloc
->addend
= fixp
->fx_addnumber
+ reloc
->address
;
6490 else if (fixp
->fx_r_type
== BFD_RELOC_PCREL_HI16_S
)
6492 assert (fixp
->fx_next
!= NULL
6493 && fixp
->fx_next
->fx_r_type
== BFD_RELOC_PCREL_LO16
);
6494 /* We use a special addend for an internal RELHI reloc. The
6495 reloc is relative to the RELLO; adjust the addend
6497 if (fixp
->fx_addsy
->bsym
->flags
& BSF_SECTION_SYM
)
6498 reloc
->addend
= (fixp
->fx_next
->fx_frag
->fr_address
6499 + fixp
->fx_next
->fx_where
6500 - S_GET_VALUE (fixp
->fx_subsy
));
6502 reloc
->addend
= (fixp
->fx_addnumber
6503 + fixp
->fx_next
->fx_frag
->fr_address
6504 + fixp
->fx_next
->fx_where
);
6506 else if (fixp
->fx_pcrel
== 0)
6507 reloc
->addend
= fixp
->fx_addnumber
;
6511 /* A gruesome hack which is a result of the gruesome gas reloc
6513 reloc
->addend
= reloc
->address
;
6515 reloc
->addend
= -reloc
->address
;
6519 /* If this is a variant frag, we may need to adjust the existing
6520 reloc and generate a new one. */
6521 if (fixp
->fx_frag
->fr_opcode
!= NULL
6522 && (fixp
->fx_r_type
== BFD_RELOC_MIPS_GPREL
6523 || fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT16
6524 || fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL16
))
6528 /* If this is not the last reloc in this frag, then we have two
6529 GPREL relocs, both of which are being replaced. Let the
6530 second one handle all of them. */
6531 if (fixp
->fx_next
!= NULL
6532 && fixp
->fx_frag
== fixp
->fx_next
->fx_frag
)
6534 assert (fixp
->fx_r_type
== BFD_RELOC_MIPS_GPREL
6535 && fixp
->fx_next
->fx_r_type
== BFD_RELOC_MIPS_GPREL
);
6540 fixp
->fx_where
= fixp
->fx_frag
->fr_opcode
- fixp
->fx_frag
->fr_literal
;
6541 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
6542 reloc2
= retval
[1] = (arelent
*) xmalloc (sizeof (arelent
));
6544 reloc2
->sym_ptr_ptr
= &fixp
->fx_addsy
->bsym
;
6545 reloc2
->address
= (reloc
->address
6546 + (RELAX_RELOC2 (fixp
->fx_frag
->fr_subtype
)
6547 - RELAX_RELOC1 (fixp
->fx_frag
->fr_subtype
)));
6548 reloc2
->addend
= fixp
->fx_addnumber
;
6549 reloc2
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_LO16
);
6550 assert (reloc2
->howto
!= NULL
);
6552 if (RELAX_RELOC3 (fixp
->fx_frag
->fr_subtype
))
6556 reloc3
= retval
[2] = (arelent
*) xmalloc (sizeof (arelent
));
6559 reloc3
->address
+= 4;
6562 if (mips_pic
== NO_PIC
)
6564 assert (fixp
->fx_r_type
== BFD_RELOC_MIPS_GPREL
);
6565 fixp
->fx_r_type
= BFD_RELOC_HI16_S
;
6567 else if (mips_pic
== SVR4_PIC
)
6569 if (fixp
->fx_r_type
!= BFD_RELOC_MIPS_GOT16
)
6571 assert (fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL16
);
6572 fixp
->fx_r_type
= BFD_RELOC_MIPS_GOT16
;
6579 /* To support a PC relative reloc when generating embedded PIC code
6580 for ECOFF, we use a Cygnus extension. We check for that here to
6581 make sure that we don't let such a reloc escape normally. */
6583 if (fixp
->fx_r_type
== BFD_RELOC_16_PCREL_S2
6584 && mips_pic
!= EMBEDDED_PIC
)
6585 reloc
->howto
= NULL
;
6588 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, fixp
->fx_r_type
);
6590 if (reloc
->howto
== NULL
)
6592 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
6593 "Can not represent relocation in this object file format");
6600 /* Convert a machine dependent frag. */
6603 md_convert_frag (abfd
, asec
, fragp
)
6611 if (fragp
->fr_opcode
== NULL
)
6614 old
= RELAX_OLD (fragp
->fr_subtype
);
6615 new = RELAX_NEW (fragp
->fr_subtype
);
6616 fixptr
= fragp
->fr_literal
+ fragp
->fr_fix
;
6619 memcpy (fixptr
- old
, fixptr
, new);
6621 fragp
->fr_fix
+= new - old
;
6624 /* This function is called whenever a label is defined. It is used
6625 when handling branch delays; if a branch has a label, we assume we
6629 mips_define_label (sym
)
6637 /* Some special processing for a MIPS ELF file. */
6640 mips_elf_final_processing ()
6644 /* Write out the .reginfo section. */
6645 s
.ri_gprmask
= mips_gprmask
;
6646 s
.ri_cprmask
[0] = mips_cprmask
[0];
6647 s
.ri_cprmask
[1] = mips_cprmask
[1];
6648 s
.ri_cprmask
[2] = mips_cprmask
[2];
6649 s
.ri_cprmask
[3] = mips_cprmask
[3];
6650 /* The gp_value field is set by the MIPS ELF backend. */
6652 bfd_mips_elf32_swap_reginfo_out (stdoutput
, &s
,
6653 ((Elf32_External_RegInfo
*)
6654 mips_regmask_frag
));
6656 /* Set the MIPS ELF flag bits. FIXME: There should probably be some
6657 sort of BFD interface for this. */
6658 if (mips_any_noreorder
)
6659 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_NOREORDER
;
6660 if (mips_pic
!= NO_PIC
)
6661 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_PIC
;
6664 #endif /* OBJ_ELF */
6666 #ifndef ECOFF_DEBUGGING
6668 /* These functions should really be defined by the object file format,
6669 since they are related to debugging information. However, this
6670 code has to work for the a.out format, which does not define them,
6671 so we provide simple versions here. These don't actually generate
6672 any debugging information, but they do simple checking and someday
6673 somebody may make them useful. */
6677 struct loc
*loc_next
;
6678 unsigned long loc_fileno
;
6679 unsigned long loc_lineno
;
6680 unsigned long loc_offset
;
6681 unsigned short loc_delta
;
6682 unsigned short loc_count
;
6691 struct proc
*proc_next
;
6692 struct symbol
*proc_isym
;
6693 struct symbol
*proc_end
;
6694 unsigned long proc_reg_mask
;
6695 unsigned long proc_reg_offset
;
6696 unsigned long proc_fpreg_mask
;
6697 unsigned long proc_fpreg_offset
;
6698 unsigned long proc_frameoffset
;
6699 unsigned long proc_framereg
;
6700 unsigned long proc_pcreg
;
6702 struct file
*proc_file
;
6709 struct file
*file_next
;
6710 unsigned long file_fileno
;
6711 struct symbol
*file_symbol
;
6712 struct symbol
*file_end
;
6713 struct proc
*file_proc
;
6718 static struct obstack proc_frags
;
6719 static procS
*proc_lastP
;
6720 static procS
*proc_rootP
;
6721 static int numprocs
;
6726 obstack_begin (&proc_frags
, 0x2000);
6732 /* check for premature end, nesting errors, etc */
6733 if (proc_lastP
&& proc_lastP
->proc_end
== NULL
)
6734 as_warn ("missing `.end' at end of assembly");
6743 if (*input_line_pointer
== '-')
6745 ++input_line_pointer
;
6748 if (!isdigit (*input_line_pointer
))
6749 as_bad ("Expected simple number.");
6750 if (input_line_pointer
[0] == '0')
6752 if (input_line_pointer
[1] == 'x')
6754 input_line_pointer
+= 2;
6755 while (isxdigit (*input_line_pointer
))
6758 val
|= hex_value (*input_line_pointer
++);
6760 return negative
? -val
: val
;
6764 ++input_line_pointer
;
6765 while (isdigit (*input_line_pointer
))
6768 val
|= *input_line_pointer
++ - '0';
6770 return negative
? -val
: val
;
6773 if (!isdigit (*input_line_pointer
))
6775 printf (" *input_line_pointer == '%c' 0x%02x\n",
6776 *input_line_pointer
, *input_line_pointer
);
6777 as_warn ("Invalid number");
6780 while (isdigit (*input_line_pointer
))
6783 val
+= *input_line_pointer
++ - '0';
6785 return negative
? -val
: val
;
6788 /* The .file directive; just like the usual .file directive, but there
6789 is an initial number which is the ECOFF file index. */
6797 line
= get_number ();
6802 /* The .end directive. */
6810 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
6813 demand_empty_rest_of_line ();
6817 if (now_seg
!= text_section
)
6818 as_warn (".end not in text section");
6821 as_warn (".end and no .ent seen yet.");
6827 assert (S_GET_NAME (p
));
6828 if (strcmp (S_GET_NAME (p
), S_GET_NAME (proc_lastP
->proc_isym
)))
6829 as_warn (".end symbol does not match .ent symbol.");
6832 proc_lastP
->proc_end
= (symbolS
*) 1;
6835 /* The .aent and .ent directives. */
6845 symbolP
= get_symbol ();
6846 if (*input_line_pointer
== ',')
6847 input_line_pointer
++;
6849 if (isdigit (*input_line_pointer
) || *input_line_pointer
== '-')
6850 number
= get_number ();
6851 if (now_seg
!= text_section
)
6852 as_warn (".ent or .aent not in text section.");
6854 if (!aent
&& proc_lastP
&& proc_lastP
->proc_end
== NULL
)
6855 as_warn ("missing `.end'");
6859 procP
= (procS
*) obstack_alloc (&proc_frags
, sizeof (*procP
));
6860 procP
->proc_isym
= symbolP
;
6861 procP
->proc_reg_mask
= 0;
6862 procP
->proc_reg_offset
= 0;
6863 procP
->proc_fpreg_mask
= 0;
6864 procP
->proc_fpreg_offset
= 0;
6865 procP
->proc_frameoffset
= 0;
6866 procP
->proc_framereg
= 0;
6867 procP
->proc_pcreg
= 0;
6868 procP
->proc_end
= NULL
;
6869 procP
->proc_next
= NULL
;
6871 proc_lastP
->proc_next
= procP
;
6877 demand_empty_rest_of_line ();
6880 /* The .frame directive. */
6893 frame_reg
= tc_get_register (1);
6894 if (*input_line_pointer
== ',')
6895 input_line_pointer
++;
6896 frame_off
= get_absolute_expression ();
6897 if (*input_line_pointer
== ',')
6898 input_line_pointer
++;
6899 pcreg
= tc_get_register (0);
6902 assert (proc_rootP
);
6903 proc_rootP
->proc_framereg
= frame_reg
;
6904 proc_rootP
->proc_frameoffset
= frame_off
;
6905 proc_rootP
->proc_pcreg
= pcreg
;
6906 /* bob macho .frame */
6908 /* We don't have to write out a frame stab for unoptimized code. */
6909 if (!(frame_reg
== FP
&& frame_off
== 0))
6912 as_warn ("No .ent for .frame to use.");
6913 (void) sprintf (str
, "R%d;%d", frame_reg
, frame_off
);
6914 symP
= symbol_new (str
, N_VFP
, 0, frag_now
);
6915 S_SET_TYPE (symP
, N_RMASK
);
6916 S_SET_OTHER (symP
, 0);
6917 S_SET_DESC (symP
, 0);
6918 symP
->sy_forward
= proc_lastP
->proc_isym
;
6919 /* bob perhaps I should have used pseudo set */
6921 demand_empty_rest_of_line ();
6925 /* The .fmask and .mask directives. */
6932 char str
[100], *strP
;
6938 mask
= get_number ();
6939 if (*input_line_pointer
== ',')
6940 input_line_pointer
++;
6941 off
= get_absolute_expression ();
6943 /* bob only for coff */
6944 assert (proc_rootP
);
6945 if (reg_type
== 'F')
6947 proc_rootP
->proc_fpreg_mask
= mask
;
6948 proc_rootP
->proc_fpreg_offset
= off
;
6952 proc_rootP
->proc_reg_mask
= mask
;
6953 proc_rootP
->proc_reg_offset
= off
;
6956 /* bob macho .mask + .fmask */
6958 /* We don't have to write out a mask stab if no saved regs. */
6962 as_warn ("No .ent for .mask to use.");
6964 for (i
= 0; i
< 32; i
++)
6968 sprintf (strP
, "%c%d,", reg_type
, i
);
6969 strP
+= strlen (strP
);
6973 sprintf (strP
, ";%d,", off
);
6974 symP
= symbol_new (str
, N_RMASK
, 0, frag_now
);
6975 S_SET_TYPE (symP
, N_RMASK
);
6976 S_SET_OTHER (symP
, 0);
6977 S_SET_DESC (symP
, 0);
6978 symP
->sy_forward
= proc_lastP
->proc_isym
;
6979 /* bob perhaps I should have used pseudo set */
6984 /* The .loc directive. */
6995 assert (now_seg
== text_section
);
6997 lineno
= get_number ();
6998 addroff
= frag_now_fix ();
7000 symbolP
= symbol_new ("", N_SLINE
, addroff
, frag_now
);
7001 S_SET_TYPE (symbolP
, N_SLINE
);
7002 S_SET_OTHER (symbolP
, 0);
7003 S_SET_DESC (symbolP
, lineno
);
7004 symbolP
->sy_segment
= now_seg
;
7008 #endif /* ! defined (ECOFF_DEBUGGING) */