1 /* tc-mips.c -- assemble code for a MIPS chip.
2 Copyright (C) 1993 Free Software Foundation, Inc.
3 Contributed by the OSF and Ralph Campbell.
4 Written by Keith Knowles and Ralph Campbell, working independently.
5 Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus
8 This file is part of GAS.
10 GAS is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 2, or (at your option)
15 GAS is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with GAS; see the file COPYING. If not, write to
22 the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */
40 #endif /* NO_VARARGS */
41 #endif /* NO_STDARG */
43 #include "opcode/mips.h"
48 static char *mips_regmask_frag
;
52 #define PIC_CALL_REG 25
58 /* Decide whether to do GP reference optimizations based on the object
68 /* The default target format to use. */
70 #ifdef TARGET_BYTES_BIG_ENDIAN
71 #define DEFAULT_TARGET_FORMAT "a.out-mips-big"
73 #define DEFAULT_TARGET_FORMAT "a.out-mips-little"
77 #ifdef TARGET_BYTES_BIG_ENDIAN
78 #define DEFAULT_TARGET_FORMAT "ecoff-bigmips"
80 #define DEFAULT_TARGET_FORMAT "ecoff-littlemips"
82 #endif /* OBJ_ECOFF */
84 #ifdef TARGET_BYTES_BIG_ENDIAN
85 #define DEFAULT_TARGET_FORMAT "elf32-bigmips"
87 #define DEFAULT_TARGET_FORMAT "elf32-littlemips"
91 const char *mips_target_format
= DEFAULT_TARGET_FORMAT
;
93 /* These variables are filled in with the masks of registers used.
94 The object format code reads them and puts them in the appropriate
96 unsigned long mips_gprmask
;
97 unsigned long mips_cprmask
[4];
99 /* MIPS ISA (Instruction Set Architecture) level (may be changed
100 temporarily using .set mipsN). */
101 static int mips_isa
= -1;
103 /* MIPS ISA we are using for this output file. */
104 static int file_mips_isa
;
106 /* MIPS PIC level. */
110 /* Do not generate PIC code. */
113 /* Generate PIC code as in Irix 4. This is not implemented, and I'm
114 not sure what it is supposed to do. */
117 /* Generate PIC code as in the SVR4 MIPS ABI. */
120 /* Generate PIC code without using a global offset table: the data
121 segment has a maximum size of 64K, all data references are off
122 the $gp register, and all text references are PC relative. This
123 is used on some embedded systems. */
127 static enum mips_pic_level mips_pic
;
129 /* 1 if trap instructions should used for overflow rather than break
131 static int mips_trap
;
133 static int mips_warn_about_macros
;
134 static int mips_noreorder
;
135 static int mips_any_noreorder
;
136 static int mips_nomove
;
137 static int mips_noat
;
138 static int mips_nobopt
;
141 /* The size of the small data section. */
142 static int g_switch_value
= 8;
143 /* Whether the -G option was used. */
144 static int g_switch_seen
= 0;
150 /* handle of the OPCODE hash table */
151 static struct hash_control
*op_hash
= NULL
;
153 /* This array holds the chars that always start a comment. If the
154 pre-processor is disabled, these aren't very useful */
155 const char comment_chars
[] = "#";
157 /* This array holds the chars that only start a comment at the beginning of
158 a line. If the line seems to have the form '# 123 filename'
159 .line and .file directives will appear in the pre-processed output */
160 /* Note that input_file.c hand checks for '#' at the beginning of the
161 first line of the input file. This is because the compiler outputs
162 #NO_APP at the beginning of its output. */
163 /* Also note that C style comments are always supported. */
164 const char line_comment_chars
[] = "#";
166 /* This array holds machine specific line separator characters. */
167 const char line_separator_chars
[] = "";
169 /* Chars that can be used to separate mant from exp in floating point nums */
170 const char EXP_CHARS
[] = "eE";
172 /* Chars that mean this number is a floating point constant */
175 const char FLT_CHARS
[] = "rRsSfFdDxXpP";
177 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
178 changed in read.c . Ideally it shouldn't have to know about it at all,
179 but nothing is ideal around here.
182 static char *insn_error
;
184 static int byte_order
= BYTE_ORDER
;
186 static int auto_align
= 1;
188 /* Symbol labelling the current insn. */
189 static symbolS
*insn_label
;
191 /* When outputting SVR4 PIC code, the assembler needs to know the
192 offset in the stack frame from which to restore the $gp register.
193 This is set by the .cprestore pseudo-op, and saved in this
195 static offsetT mips_cprestore_offset
= -1;
197 /* This is the register which holds the stack frame, as set by the
198 .frame pseudo-op. This is needed to implement .cprestore. */
199 static int mips_frame_reg
= SP
;
201 /* To output NOP instructions correctly, we need to keep information
202 about the previous two instructions. */
204 /* Whether we are optimizing. The default value of 2 means to remove
205 unneeded NOPs and swap branch instructions when possible. A value
206 of 1 means to not swap branches. A value of 0 means to always
208 static int mips_optimize
= 2;
210 /* The previous instruction. */
211 static struct mips_cl_insn prev_insn
;
213 /* The instruction before prev_insn. */
214 static struct mips_cl_insn prev_prev_insn
;
216 /* If we don't want information for prev_insn or prev_prev_insn, we
217 point the insn_mo field at this dummy integer. */
218 static const struct mips_opcode dummy_opcode
= { 0 };
220 /* Non-zero if prev_insn is valid. */
221 static int prev_insn_valid
;
223 /* The frag for the previous instruction. */
224 static struct frag
*prev_insn_frag
;
226 /* The offset into prev_insn_frag for the previous instruction. */
227 static long prev_insn_where
;
229 /* The reloc for the previous instruction, if any. */
230 static fixS
*prev_insn_fixp
;
232 /* Non-zero if the previous instruction was in a delay slot. */
233 static int prev_insn_is_delay_slot
;
235 /* Non-zero if the previous instruction was in a .set noreorder. */
236 static int prev_insn_unreordered
;
238 /* Non-zero if the previous previous instruction was in a .set
240 static int prev_prev_insn_unreordered
;
242 /* Since the MIPS does not have multiple forms of PC relative
243 instructions, we do not have to do relaxing as is done on other
244 platforms. However, we do have to handle GP relative addressing
245 correctly, which turns out to be a similar problem.
247 Every macro that refers to a symbol can occur in (at least) two
248 forms, one with GP relative addressing and one without. For
249 example, loading a global variable into a register generally uses
250 a macro instruction like this:
252 If i can be addressed off the GP register (this is true if it is in
253 the .sbss or .sdata section, or if it is known to be smaller than
254 the -G argument) this will generate the following instruction:
256 This instruction will use a GPREL reloc. If i can not be addressed
257 off the GP register, the following instruction sequence will be used:
260 In this case the first instruction will have a HI16 reloc, and the
261 second reloc will have a LO16 reloc. Both relocs will be against
264 The issue here is that we may not know whether i is GP addressable
265 until after we see the instruction that uses it. Therefore, we
266 want to be able to choose the final instruction sequence only at
267 the end of the assembly. This is similar to the way other
268 platforms choose the size of a PC relative instruction only at the
271 When generating position independent code we do not use GP
272 addressing in quite the same way, but the issue still arises as
273 external symbols and local symbols must be handled differently.
275 We handle these issues by actually generating both possible
276 instruction sequences. The longer one is put in a frag_var with
277 type rs_machine_dependent. We encode what to do with the frag in
278 the subtype field. We encode (1) the number of existing bytes to
279 replace, (2) the number of new bytes to use, (3) the offset from
280 the start of the existing bytes to the first reloc we must generate
281 (that is, the offset is applied from the start of the existing
282 bytes after they are replaced by the new bytes, if any), (4) the
283 offset from the start of the existing bytes to the second reloc,
284 (5) whether a third reloc is needed (the third reloc is always four
285 bytes after the second reloc), and (6) whether to warn if this
286 variant is used (this is sometimes needed if .set nomacro or .set
287 noat is in effect). All these numbers are reasonably small.
289 Generating two instruction sequences must be handled carefully to
290 ensure that delay slots are handled correctly. Fortunately, there
291 are a limited number of cases. When the second instruction
292 sequence is generated, append_insn is directed to maintain the
293 existing delay slot information, so it continues to apply to any
294 code after the second instruction sequence. This means that the
295 second instruction sequence must not impose any requirements not
296 required by the first instruction sequence.
298 These variant frags are then handled in functions called by the
299 machine independent code. md_estimate_size_before_relax returns
300 the final size of the frag. md_convert_frag sets up the final form
301 of the frag. tc_gen_reloc adjust the first reloc and adds a second
303 #define RELAX_ENCODE(old, new, reloc1, reloc2, reloc3, warn) \
307 | (((reloc1) + 64) << 9) \
308 | (((reloc2) + 64) << 2) \
309 | ((reloc3) ? (1 << 1) : 0) \
311 #define RELAX_OLD(i) (((i) >> 24) & 0xff)
312 #define RELAX_NEW(i) (((i) >> 16) & 0xff)
313 #define RELAX_RELOC1(i) ((((i) >> 9) & 0x7f) - 64)
314 #define RELAX_RELOC2(i) ((((i) >> 2) & 0x7f) - 64)
315 #define RELAX_RELOC3(i) (((i) >> 1) & 1)
316 #define RELAX_WARN(i) ((i) & 1)
318 /* Prototypes for static functions. */
321 #define internalError() \
322 as_fatal ("internal Error, line %d, %s", __LINE__, __FILE__)
324 #define internalError() as_fatal ("MIPS internal Error");
327 static int insn_uses_reg
PARAMS ((struct mips_cl_insn
*ip
,
328 unsigned int reg
, int fpr
));
329 static void append_insn
PARAMS ((char *place
,
330 struct mips_cl_insn
* ip
,
332 bfd_reloc_code_real_type r
));
333 static void mips_no_prev_insn
PARAMS ((void));
334 static void mips_emit_delays
PARAMS ((void));
335 static void macro_build
PARAMS ((char *place
, int *counter
, expressionS
* ep
,
336 const char *name
, const char *fmt
,
338 static void macro_build_lui
PARAMS ((char *place
, int *counter
,
339 expressionS
* ep
, int regnum
));
340 static void set_at
PARAMS ((int *counter
, int reg
, int unsignedp
));
341 static void check_absolute_expr
PARAMS ((struct mips_cl_insn
* ip
,
343 static void load_register
PARAMS ((int *counter
, int reg
, expressionS
* ep
));
344 static void load_address
PARAMS ((int *counter
, int reg
, expressionS
*ep
));
345 static void macro
PARAMS ((struct mips_cl_insn
* ip
));
346 #ifdef LOSING_COMPILER
347 static void macro2
PARAMS ((struct mips_cl_insn
* ip
));
349 static void mips_ip
PARAMS ((char *str
, struct mips_cl_insn
* ip
));
350 static int my_getSmallExpression
PARAMS ((expressionS
* ep
, char *str
));
351 static void my_getExpression
PARAMS ((expressionS
* ep
, char *str
));
352 static symbolS
*get_symbol
PARAMS ((void));
353 static void mips_align
PARAMS ((int to
, int fill
, symbolS
*label
));
354 static void s_align
PARAMS ((int));
355 static void s_stringer
PARAMS ((int));
356 static void s_change_sec
PARAMS ((int));
357 static void s_cons
PARAMS ((int));
358 static void s_err
PARAMS ((int));
359 static void s_extern
PARAMS ((int));
360 static void s_float_cons
PARAMS ((int));
361 static void s_option
PARAMS ((int));
362 static void s_mipsset
PARAMS ((int));
363 static void s_mips_space
PARAMS ((int));
364 static void s_abicalls
PARAMS ((int));
365 static void s_cpload
PARAMS ((int));
366 static void s_cprestore
PARAMS ((int));
367 static void s_gpword
PARAMS ((int));
368 static void s_cpadd
PARAMS ((int));
369 #ifndef ECOFF_DEBUGGING
370 static void md_obj_begin
PARAMS ((void));
371 static void md_obj_end
PARAMS ((void));
372 static long get_number
PARAMS ((void));
373 static void s_ent
PARAMS ((int));
374 static void s_mipsend
PARAMS ((int));
375 static void s_file
PARAMS ((int));
377 static void s_frame
PARAMS ((int));
378 static void s_loc
PARAMS ((int));
379 static void s_mask
PARAMS ((char));
385 The following pseudo-ops from the Kane and Heinrich MIPS book
386 should be defined here, but are currently unsupported: .alias,
387 .galive, .gjaldef, .gjrlive, .livereg, .noalias.
389 The following pseudo-ops from the Kane and Heinrich MIPS book are
390 specific to the type of debugging information being generated, and
391 should be defined by the object format: .aent, .begin, .bend,
392 .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp,
395 The following pseudo-ops from the Kane and Heinrich MIPS book are
396 not MIPS CPU specific, but are also not specific to the object file
397 format. This file is probably the best place to define them, but
398 they are not currently supported: .asm0, .endr, .lab, .repeat,
399 .struct, .weakext. */
401 const pseudo_typeS md_pseudo_table
[] =
403 /* MIPS specific pseudo-ops. */
404 {"option", s_option
, 0},
405 {"set", s_mipsset
, 0},
406 {"rdata", s_change_sec
, 'r'},
407 {"sdata", s_change_sec
, 's'},
408 {"livereg", s_ignore
, 0},
409 { "abicalls", s_abicalls
, 0},
410 { "cpload", s_cpload
, 0},
411 { "cprestore", s_cprestore
, 0},
412 { "gpword", s_gpword
, 0},
413 { "cpadd", s_cpadd
, 0},
415 /* Relatively generic pseudo-ops that happen to be used on MIPS
417 {"asciiz", s_stringer
, 1},
418 {"bss", s_change_sec
, 'b'},
421 {"dword", s_cons
, 3},
423 /* These pseudo-ops are defined in read.c, but must be overridden
424 here for one reason or another. */
425 {"align", s_align
, 0},
426 {"ascii", s_stringer
, 0},
427 {"asciz", s_stringer
, 1},
429 {"data", s_change_sec
, 'd'},
430 {"double", s_float_cons
, 'd'},
431 {"extern", s_extern
, 0},
432 {"float", s_float_cons
, 'f'},
433 {"hword", s_cons
, 1},
438 {"short", s_cons
, 1},
439 {"single", s_float_cons
, 'f'},
440 {"space", s_mips_space
, 0},
441 {"text", s_change_sec
, 't'},
444 #ifndef ECOFF_DEBUGGING
445 /* These pseudo-ops should be defined by the object file format.
446 However, a.out doesn't support them, so we have versions here. */
448 {"bgnb", s_ignore
, 0},
449 {"end", s_mipsend
, 0},
450 {"endb", s_ignore
, 0},
453 {"fmask", s_ignore
, 'F'},
454 {"frame", s_ignore
, 0},
455 {"loc", s_ignore
, 0},
456 {"mask", s_ignore
, 'R'},
457 {"verstamp", s_ignore
, 0},
464 const relax_typeS md_relax_table
[] =
469 static char *expr_end
;
471 static expressionS imm_expr
;
472 static expressionS offset_expr
;
473 static bfd_reloc_code_real_type imm_reloc
;
474 static bfd_reloc_code_real_type offset_reloc
;
476 /* FIXME: This should be handled in a different way. */
477 extern int target_big_endian
;
480 * This function is called once, at assembler startup time. It should
481 * set up all the tables, etc. that the MD part of the assembler will need.
487 register const char *retval
= NULL
;
488 register unsigned int i
= 0;
492 if (strcmp (TARGET_CPU
, "mips") == 0)
494 else if (strcmp (TARGET_CPU
, "r6000") == 0
495 || strcmp (TARGET_CPU
, "mips2") == 0)
497 else if (strcmp (TARGET_CPU
, "mips64") == 0
498 || strcmp (TARGET_CPU
, "r4000") == 0
499 || strcmp (TARGET_CPU
, "mips3") == 0)
505 if (mips_isa
< 2 && mips_trap
)
506 as_bad ("trap exception not supported at ISA 1");
511 ok
= bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, 3000);
514 ok
= bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, 6000);
517 ok
= bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, 4000);
521 as_warn ("Could not set architecture and machine");
523 file_mips_isa
= mips_isa
;
525 op_hash
= hash_new ();
527 for (i
= 0; i
< NUMOPCODES
;)
529 const char *name
= mips_opcodes
[i
].name
;
531 retval
= hash_insert (op_hash
, name
, (PTR
) &mips_opcodes
[i
]);
534 fprintf (stderr
, "internal error: can't hash `%s': %s\n",
535 mips_opcodes
[i
].name
, retval
);
536 as_fatal ("Broken assembler. No assembly attempted.");
540 if (mips_opcodes
[i
].pinfo
!= INSN_MACRO
541 && ((mips_opcodes
[i
].match
& mips_opcodes
[i
].mask
)
542 != mips_opcodes
[i
].match
))
544 fprintf (stderr
, "internal error: bad opcode: `%s' \"%s\"\n",
545 mips_opcodes
[i
].name
, mips_opcodes
[i
].args
);
546 as_fatal ("Broken assembler. No assembly attempted.");
550 while ((i
< NUMOPCODES
) && !strcmp (mips_opcodes
[i
].name
, name
));
553 mips_no_prev_insn ();
561 /* set the default alignment for the text section (2**2) */
562 record_alignment (text_section
, 2);
564 /* FIXME: This should be handled in a different way. */
565 target_big_endian
= byte_order
== BIG_ENDIAN
;
568 bfd_set_gp_size (stdoutput
, g_switch_value
);
572 /* Sections must be aligned to 16 byte boundaries. */
573 (void) bfd_set_section_alignment (stdoutput
, text_section
, 4);
574 (void) bfd_set_section_alignment (stdoutput
, data_section
, 4);
575 (void) bfd_set_section_alignment (stdoutput
, bss_section
, 4);
577 /* Create a .reginfo section for register masks and a .mdebug
578 section for debugging information. */
586 sec
= subseg_new (".reginfo", (subsegT
) 0);
588 /* The ABI says this section should be loaded so that the running
589 program can access it. */
590 (void) bfd_set_section_flags (stdoutput
, sec
,
591 (SEC_ALLOC
| SEC_LOAD
592 | SEC_READONLY
| SEC_DATA
));
593 (void) bfd_set_section_alignment (stdoutput
, sec
, 2);
595 mips_regmask_frag
= frag_more (sizeof (Elf32_External_RegInfo
));
597 #ifdef ECOFF_DEBUGGING
598 sec
= subseg_new (".mdebug", (subsegT
) 0);
599 (void) bfd_set_section_flags (stdoutput
, sec
,
600 SEC_HAS_CONTENTS
| SEC_READONLY
);
601 (void) bfd_set_section_alignment (stdoutput
, sec
, 2);
604 subseg_set (seg
, subseg
);
608 #ifndef ECOFF_DEBUGGING
616 #ifndef ECOFF_DEBUGGING
625 struct mips_cl_insn insn
;
627 imm_expr
.X_op
= O_absent
;
628 offset_expr
.X_op
= O_absent
;
630 mips_ip (str
, &insn
);
633 as_bad ("%s `%s'", insn_error
, str
);
636 if (insn
.insn_mo
->pinfo
== INSN_MACRO
)
642 if (imm_expr
.X_op
!= O_absent
)
643 append_insn ((char *) NULL
, &insn
, &imm_expr
, imm_reloc
);
644 else if (offset_expr
.X_op
!= O_absent
)
645 append_insn ((char *) NULL
, &insn
, &offset_expr
, offset_reloc
);
647 append_insn ((char *) NULL
, &insn
, NULL
, BFD_RELOC_UNUSED
);
651 /* See whether instruction IP reads register REG. If FPR is non-zero,
652 REG is a floating point register. */
655 insn_uses_reg (ip
, reg
, fpr
)
656 struct mips_cl_insn
*ip
;
660 /* Don't report on general register 0, since it never changes. */
661 if (! fpr
&& reg
== 0)
666 /* If we are called with either $f0 or $f1, we must check $f0.
667 This is not optimal, because it will introduce an unnecessary
668 NOP between "lwc1 $f0" and "swc1 $f1". To fix this we would
669 need to distinguish reading both $f0 and $f1 or just one of
670 them. Note that we don't have to check the other way,
671 because there is no instruction that sets both $f0 and $f1
672 and requires a delay. */
673 if ((ip
->insn_mo
->pinfo
& INSN_READ_FPR_S
)
674 && (((ip
->insn_opcode
>> OP_SH_FS
) & OP_MASK_FS
)
675 == (reg
&~ (unsigned) 1)))
677 if ((ip
->insn_mo
->pinfo
& INSN_READ_FPR_T
)
678 && (((ip
->insn_opcode
>> OP_SH_FT
) & OP_MASK_FT
)
679 == (reg
&~ (unsigned) 1)))
684 if ((ip
->insn_mo
->pinfo
& INSN_READ_GPR_S
)
685 && ((ip
->insn_opcode
>> OP_SH_RS
) & OP_MASK_RS
) == reg
)
687 if ((ip
->insn_mo
->pinfo
& INSN_READ_GPR_T
)
688 && ((ip
->insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
) == reg
)
695 /* Output an instruction. PLACE is where to put the instruction; if
696 it is NULL, this uses frag_more to get room. IP is the instruction
697 information. ADDRESS_EXPR is an operand of the instruction to be
698 used with RELOC_TYPE. */
701 append_insn (place
, ip
, address_expr
, reloc_type
)
703 struct mips_cl_insn
*ip
;
704 expressionS
*address_expr
;
705 bfd_reloc_code_real_type reloc_type
;
707 register unsigned long prev_pinfo
, pinfo
;
712 prev_pinfo
= prev_insn
.insn_mo
->pinfo
;
713 pinfo
= ip
->insn_mo
->pinfo
;
715 if (place
== NULL
&& ! mips_noreorder
)
717 /* If the previous insn required any delay slots, see if we need
718 to insert a NOP or two. There are eight kinds of possible
719 hazards, of which an instruction can have at most one type.
720 (1) a load from memory delay
721 (2) a load from a coprocessor delay
722 (3) an unconditional branch delay
723 (4) a conditional branch delay
724 (5) a move to coprocessor register delay
725 (6) a load coprocessor register from memory delay
726 (7) a coprocessor condition code delay
727 (8) a HI/LO special register delay
729 There are a lot of optimizations we could do that we don't.
730 In particular, we do not, in general, reorder instructions.
731 If you use gcc with optimization, it will reorder
732 instructions and generally do much more optimization then we
733 do here; repeating all that work in the assembler would only
734 benefit hand written assembly code, and does not seem worth
737 /* This is how a NOP is emitted. */
738 #define emit_nop() md_number_to_chars (frag_more (4), 0, 4)
740 /* The previous insn might require a delay slot, depending upon
741 the contents of the current insn. */
742 if ((prev_pinfo
& INSN_LOAD_COPROC_DELAY
)
744 && (prev_pinfo
& INSN_LOAD_MEMORY_DELAY
)))
746 /* A load from a coprocessor or from memory. All load
747 delays delay the use of general register rt for one
748 instruction on the r3000. The r6000 and r4000 use
750 know (prev_pinfo
& INSN_WRITE_GPR_T
);
751 if (mips_optimize
== 0
752 || insn_uses_reg (ip
,
753 ((prev_insn
.insn_opcode
>> OP_SH_RT
)
758 else if ((prev_pinfo
& INSN_COPROC_MOVE_DELAY
)
760 && (prev_pinfo
& INSN_COPROC_MEMORY_DELAY
)))
762 /* A generic coprocessor delay. The previous instruction
763 modified a coprocessor general or control register. If
764 it modified a control register, we need to avoid any
765 coprocessor instruction (this is probably not always
766 required, but it sometimes is). If it modified a general
767 register, we avoid using that register.
769 On the r6000 and r4000 loading a coprocessor register
770 from memory is interlocked, and does not require a delay.
772 This case is not handled very well. There is no special
773 knowledge of CP0 handling, and the coprocessors other
774 than the floating point unit are not distinguished at
776 if (prev_pinfo
& INSN_WRITE_FPR_T
)
778 if (mips_optimize
== 0
779 || insn_uses_reg (ip
,
780 ((prev_insn
.insn_opcode
>> OP_SH_FT
)
785 else if (prev_pinfo
& INSN_WRITE_FPR_S
)
787 if (mips_optimize
== 0
788 || insn_uses_reg (ip
,
789 ((prev_insn
.insn_opcode
>> OP_SH_FS
)
796 /* We don't know exactly what the previous instruction
797 does. If the current instruction uses a coprocessor
798 register, we must insert a NOP. If previous
799 instruction may set the condition codes, and the
800 current instruction uses them, we must insert two
802 if (mips_optimize
== 0
803 || ((prev_pinfo
& INSN_WRITE_COND_CODE
)
804 && (pinfo
& INSN_READ_COND_CODE
)))
806 else if (pinfo
& INSN_COP
)
810 else if (prev_pinfo
& INSN_WRITE_COND_CODE
)
812 /* The previous instruction sets the coprocessor condition
813 codes, but does not require a general coprocessor delay
814 (this means it is a floating point comparison
815 instruction). If this instruction uses the condition
816 codes, we need to insert a single NOP. */
817 if (mips_optimize
== 0
818 || (pinfo
& INSN_READ_COND_CODE
))
821 else if (prev_pinfo
& INSN_READ_LO
)
823 /* The previous instruction reads the LO register; if the
824 current instruction writes to the LO register, we must
826 if (mips_optimize
== 0
827 || (pinfo
& INSN_WRITE_LO
))
830 else if (prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
832 /* The previous instruction reads the HI register; if the
833 current instruction writes to the HI register, we must
835 if (mips_optimize
== 0
836 || (pinfo
& INSN_WRITE_HI
))
840 /* There are two cases which require two intervening
841 instructions: 1) setting the condition codes using a move to
842 coprocessor instruction which requires a general coprocessor
843 delay and then reading the condition codes 2) reading the HI
844 or LO register and then writing to it. If we are not already
845 emitting a NOP instruction, we must check for these cases
846 compared to the instruction previous to the previous
849 && (((prev_prev_insn
.insn_mo
->pinfo
& INSN_COPROC_MOVE_DELAY
)
850 && (prev_prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
)
851 && (pinfo
& INSN_READ_COND_CODE
))
852 || ((prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
)
853 && (pinfo
& INSN_WRITE_LO
))
854 || ((prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
855 && (pinfo
& INSN_WRITE_HI
))))
858 /* If we are being given a nop instruction, don't bother with
859 one of the nops we would otherwise output. This will only
860 happen when a nop instruction is used with mips_optimize set
862 if (nops
> 0 && ip
->insn_opcode
== 0)
865 /* Now emit the right number of NOP instructions. */
872 listing_prev_line ();
873 if (insn_label
!= NULL
)
875 assert (S_GET_SEGMENT (insn_label
) == now_seg
);
876 insn_label
->sy_frag
= frag_now
;
877 S_SET_VALUE (insn_label
, (valueT
) frag_now_fix ());
887 if (address_expr
!= NULL
)
889 if (address_expr
->X_op
== O_constant
)
894 ip
->insn_opcode
|= address_expr
->X_add_number
;
898 ip
->insn_opcode
|= address_expr
->X_add_number
& 0xffff;
901 case BFD_RELOC_MIPS_JMP
:
902 case BFD_RELOC_16_PCREL_S2
:
911 assert (reloc_type
!= BFD_RELOC_UNUSED
);
913 /* Don't generate a reloc if we are writing into a variant
916 fixp
= fix_new_exp (frag_now
, f
- frag_now
->fr_literal
, 4,
918 reloc_type
== BFD_RELOC_16_PCREL_S2
,
923 md_number_to_chars (f
, ip
->insn_opcode
, 4);
925 /* Update the register mask information. */
926 if (pinfo
& INSN_WRITE_GPR_D
)
927 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
);
928 if ((pinfo
& (INSN_WRITE_GPR_T
| INSN_READ_GPR_T
)) != 0)
929 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
);
930 if (pinfo
& INSN_READ_GPR_S
)
931 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> OP_SH_RS
) & OP_MASK_RS
);
932 if (pinfo
& INSN_WRITE_GPR_31
)
933 mips_gprmask
|= 1 << 31;
934 if (pinfo
& INSN_WRITE_FPR_D
)
935 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FD
) & OP_MASK_FD
);
936 if ((pinfo
& (INSN_WRITE_FPR_S
| INSN_READ_FPR_S
)) != 0)
937 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FS
) & OP_MASK_FS
);
938 if ((pinfo
& (INSN_WRITE_FPR_T
| INSN_READ_FPR_T
)) != 0)
939 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FT
) & OP_MASK_FT
);
940 if (pinfo
& INSN_COP
)
942 /* We don't keep enough information to sort these cases out. */
944 /* Never set the bit for $0, which is always zero. */
945 mips_gprmask
&=~ 1 << 0;
947 if (place
== NULL
&& ! mips_noreorder
)
949 /* Filling the branch delay slot is more complex. We try to
950 switch the branch with the previous instruction, which we can
951 do if the previous instruction does not set up a condition
952 that the branch tests and if the branch is not itself the
953 target of any branch. */
954 if ((pinfo
& INSN_UNCOND_BRANCH_DELAY
)
955 || (pinfo
& INSN_COND_BRANCH_DELAY
))
957 if (mips_optimize
< 2
958 /* If we have seen .set nobopt, don't optimize. */
960 /* If we have seen .set volatile or .set nomove, don't
963 /* If we had to emit any NOP instructions, then we
964 already know we can not swap. */
966 /* If we don't even know the previous insn, we can not
969 /* If the previous insn is already in a branch delay
970 slot, then we can not swap. */
971 || prev_insn_is_delay_slot
972 /* If the previous previous insn was in a .set
973 noreorder, we can't swap. Actually, the MIPS
974 assembler will swap in this situation. However, gcc
975 configured -with-gnu-as will generate code like
981 in which we can not swap the bne and INSN. If gcc is
982 not configured -with-gnu-as, it does not output the
983 .set pseudo-ops. We don't have to check
984 prev_insn_unreordered, because prev_insn_valid will
985 be 0 in that case. We don't want to use
986 prev_prev_insn_valid, because we do want to be able
987 to swap at the start of a function. */
988 || prev_prev_insn_unreordered
989 /* If the branch is itself the target of a branch, we
990 can not swap. We cheat on this; all we check for is
991 whether there is a label on this instruction. If
992 there are any branches to anything other than a
993 label, users must use .set noreorder. */
994 || insn_label
!= NULL
995 /* If the previous instruction is in a variant frag, we
996 can not do the swap. */
997 || prev_insn_frag
->fr_type
== rs_machine_dependent
998 /* If the branch reads the condition codes, we don't
999 even try to swap, because in the sequence
1004 we can not swap, and I don't feel like handling that
1006 || (pinfo
& INSN_READ_COND_CODE
)
1007 /* We can not swap with an instruction that requires a
1008 delay slot, becase the target of the branch might
1009 interfere with that instruction. */
1011 & (INSN_LOAD_COPROC_DELAY
1012 | INSN_COPROC_MOVE_DELAY
1013 | INSN_WRITE_COND_CODE
1018 & (INSN_LOAD_MEMORY_DELAY
1019 | INSN_COPROC_MEMORY_DELAY
)))
1020 /* We can not swap with a branch instruction. */
1022 & (INSN_UNCOND_BRANCH_DELAY
1023 | INSN_COND_BRANCH_DELAY
1024 | INSN_COND_BRANCH_LIKELY
))
1025 /* We do not swap with a trap instruction, since it
1026 complicates trap handlers to have the trap
1027 instruction be in a delay slot. */
1028 || (prev_pinfo
& INSN_TRAP
)
1029 /* If the branch reads a register that the previous
1030 instruction sets, we can not swap. */
1031 || ((prev_pinfo
& INSN_WRITE_GPR_T
)
1032 && insn_uses_reg (ip
,
1033 ((prev_insn
.insn_opcode
>> OP_SH_RT
)
1036 || ((prev_pinfo
& INSN_WRITE_GPR_D
)
1037 && insn_uses_reg (ip
,
1038 ((prev_insn
.insn_opcode
>> OP_SH_RD
)
1041 /* If the branch writes a register that the previous
1042 instruction sets, we can not swap (we know that
1043 branches write only to RD or to $31). */
1044 || ((prev_pinfo
& INSN_WRITE_GPR_T
)
1045 && (((pinfo
& INSN_WRITE_GPR_D
)
1046 && (((prev_insn
.insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
)
1047 == ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)))
1048 || ((pinfo
& INSN_WRITE_GPR_31
)
1049 && (((prev_insn
.insn_opcode
>> OP_SH_RT
)
1052 || ((prev_pinfo
& INSN_WRITE_GPR_D
)
1053 && (((pinfo
& INSN_WRITE_GPR_D
)
1054 && (((prev_insn
.insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)
1055 == ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)))
1056 || ((pinfo
& INSN_WRITE_GPR_31
)
1057 && (((prev_insn
.insn_opcode
>> OP_SH_RD
)
1060 /* If the branch writes a register that the previous
1061 instruction reads, we can not swap (we know that
1062 branches only write to RD or to $31). */
1063 || ((pinfo
& INSN_WRITE_GPR_D
)
1064 && insn_uses_reg (&prev_insn
,
1065 ((ip
->insn_opcode
>> OP_SH_RD
)
1068 || ((pinfo
& INSN_WRITE_GPR_31
)
1069 && insn_uses_reg (&prev_insn
, 31, 0))
1070 /* If the previous previous instruction has a load
1071 delay, and sets a register that the branch reads, we
1073 || (((prev_prev_insn
.insn_mo
->pinfo
& INSN_LOAD_COPROC_DELAY
)
1075 && (prev_prev_insn
.insn_mo
->pinfo
1076 & INSN_LOAD_MEMORY_DELAY
)))
1077 && insn_uses_reg (ip
,
1078 ((prev_prev_insn
.insn_opcode
>> OP_SH_RT
)
1082 /* We could do even better for unconditional branches to
1083 portions of this object file; we could pick up the
1084 instruction at the destination, put it in the delay
1085 slot, and bump the destination address. */
1087 /* Update the previous insn information. */
1088 prev_prev_insn
= *ip
;
1089 prev_insn
.insn_mo
= &dummy_opcode
;
1096 /* It looks like we can actually do the swap. */
1097 prev_f
= prev_insn_frag
->fr_literal
+ prev_insn_where
;
1098 memcpy (temp
, prev_f
, 4);
1099 memcpy (prev_f
, f
, 4);
1100 memcpy (f
, temp
, 4);
1103 prev_insn_fixp
->fx_frag
= frag_now
;
1104 prev_insn_fixp
->fx_where
= f
- frag_now
->fr_literal
;
1108 fixp
->fx_frag
= prev_insn_frag
;
1109 fixp
->fx_where
= prev_insn_where
;
1111 /* Update the previous insn information; leave prev_insn
1113 prev_prev_insn
= *ip
;
1115 prev_insn_is_delay_slot
= 1;
1117 /* If that was an unconditional branch, forget the previous
1118 insn information. */
1119 if (pinfo
& INSN_UNCOND_BRANCH_DELAY
)
1121 prev_prev_insn
.insn_mo
= &dummy_opcode
;
1122 prev_insn
.insn_mo
= &dummy_opcode
;
1125 else if (pinfo
& INSN_COND_BRANCH_LIKELY
)
1127 /* We don't yet optimize a branch likely. What we should do
1128 is look at the target, copy the instruction found there
1129 into the delay slot, and increment the branch to jump to
1130 the next instruction. */
1132 /* Update the previous insn information. */
1133 prev_prev_insn
= *ip
;
1134 prev_insn
.insn_mo
= &dummy_opcode
;
1138 /* Update the previous insn information. */
1140 prev_prev_insn
.insn_mo
= &dummy_opcode
;
1142 prev_prev_insn
= prev_insn
;
1145 /* Any time we see a branch, we always fill the delay slot
1146 immediately; since this insn is not a branch, we know it
1147 is not in a delay slot. */
1148 prev_insn_is_delay_slot
= 0;
1151 prev_prev_insn_unreordered
= prev_insn_unreordered
;
1152 prev_insn_unreordered
= 0;
1153 prev_insn_frag
= frag_now
;
1154 prev_insn_where
= f
- frag_now
->fr_literal
;
1155 prev_insn_fixp
= fixp
;
1156 prev_insn_valid
= 1;
1159 /* We just output an insn, so the next one doesn't have a label. */
1163 /* This function forgets that there was any previous instruction or
1167 mips_no_prev_insn ()
1169 prev_insn
.insn_mo
= &dummy_opcode
;
1170 prev_prev_insn
.insn_mo
= &dummy_opcode
;
1171 prev_insn_valid
= 0;
1172 prev_insn_is_delay_slot
= 0;
1173 prev_insn_unreordered
= 0;
1174 prev_prev_insn_unreordered
= 0;
1178 /* This function must be called whenever we turn on noreorder or emit
1179 something other than instructions. It inserts any NOPS which might
1180 be needed by the previous instruction, and clears the information
1181 kept for the previous instructions. */
1186 if (! mips_noreorder
)
1191 if ((prev_insn
.insn_mo
->pinfo
1192 & (INSN_LOAD_COPROC_DELAY
1193 | INSN_COPROC_MOVE_DELAY
1194 | INSN_WRITE_COND_CODE
1198 && (prev_insn
.insn_mo
->pinfo
1199 & (INSN_LOAD_MEMORY_DELAY
1200 | INSN_COPROC_MEMORY_DELAY
))))
1203 if ((prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
)
1204 || (prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
1205 || (prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
))
1208 else if ((prev_prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
)
1209 || (prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
1210 || (prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
))
1215 if (insn_label
!= NULL
)
1217 assert (S_GET_SEGMENT (insn_label
) == now_seg
);
1218 insn_label
->sy_frag
= frag_now
;
1219 S_SET_VALUE (insn_label
, (valueT
) frag_now_fix ());
1222 mips_no_prev_insn ();
1226 /* Build an instruction created by a macro expansion. This is passed
1227 a pointer to the count of instructions created so far, an
1228 expression, the name of the instruction to build, an operand format
1229 string, and corresponding arguments. */
1233 macro_build (char *place
,
1239 #else /* ! defined (NO_STDARG) */
1241 macro_build (place
, counter
, ep
, name
, fmt
, va_alist
)
1248 #endif /* ! defined (NO_STDARG) */
1250 struct mips_cl_insn insn
;
1251 bfd_reloc_code_real_type r
;
1255 va_start (args
, fmt
);
1261 * If the macro is about to expand into a second instruction,
1262 * print a warning if needed. We need to pass ip as a parameter
1263 * to generate a better warning message here...
1265 if (mips_warn_about_macros
&& place
== NULL
&& *counter
== 1)
1266 as_warn ("Macro instruction expanded into multiple instructions");
1269 *counter
+= 1; /* bump instruction counter */
1271 r
= BFD_RELOC_UNUSED
;
1272 insn
.insn_mo
= (struct mips_opcode
*) hash_find (op_hash
, name
);
1273 assert (insn
.insn_mo
);
1274 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
1276 while (strcmp (fmt
, insn
.insn_mo
->args
) != 0
1277 || insn
.insn_mo
->pinfo
== INSN_MACRO
)
1280 assert (insn
.insn_mo
->name
);
1281 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
1283 insn
.insn_opcode
= insn
.insn_mo
->match
;
1299 insn
.insn_opcode
|= va_arg (args
, int) << 16;
1305 insn
.insn_opcode
|= va_arg (args
, int) << 16;
1310 insn
.insn_opcode
|= va_arg (args
, int) << 11;
1315 insn
.insn_opcode
|= va_arg (args
, int) << 11;
1322 insn
.insn_opcode
|= va_arg (args
, int) << 6;
1326 insn
.insn_opcode
|= va_arg (args
, int) << 6;
1330 insn
.insn_opcode
|= va_arg (args
, int) << 6;
1337 insn
.insn_opcode
|= va_arg (args
, int) << 21;
1343 r
= (bfd_reloc_code_real_type
) va_arg (args
, int);
1344 assert (r
== BFD_RELOC_MIPS_GPREL
1345 || r
== BFD_RELOC_MIPS_LITERAL
1346 || r
== BFD_RELOC_LO16
1347 || r
== BFD_RELOC_MIPS_GOT16
1348 || r
== BFD_RELOC_MIPS_CALL16
);
1352 assert (ep
!= NULL
&& ep
->X_op
== O_constant
);
1353 insn
.insn_opcode
|= (ep
->X_add_number
>> 16) & 0xffff;
1358 assert (ep
!= NULL
);
1360 * This allows macro() to pass an immediate expression for
1361 * creating short branches without creating a symbol.
1362 * Note that the expression still might come from the assembly
1363 * input, in which case the value is not checked for range nor
1364 * is a relocation entry generated (yuck).
1366 if (ep
->X_op
== O_constant
)
1368 insn
.insn_opcode
|= (ep
->X_add_number
>> 2) & 0xffff;
1372 r
= BFD_RELOC_16_PCREL_S2
;
1376 assert (ep
!= NULL
);
1377 r
= BFD_RELOC_MIPS_JMP
;
1386 assert (r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
1388 append_insn (place
, &insn
, ep
, r
);
1392 * Generate a "lui" instruction.
1395 macro_build_lui (place
, counter
, ep
, regnum
)
1401 expressionS high_expr
;
1402 struct mips_cl_insn insn
;
1403 bfd_reloc_code_real_type r
;
1404 CONST
char *name
= "lui";
1405 CONST
char *fmt
= "t,u";
1411 high_expr
.X_op
= O_constant
;
1412 high_expr
.X_add_number
= 0;
1415 if (high_expr
.X_op
== O_constant
)
1417 /* we can compute the instruction now without a relocation entry */
1418 if (high_expr
.X_add_number
& 0x8000)
1419 high_expr
.X_add_number
+= 0x10000;
1420 high_expr
.X_add_number
=
1421 ((unsigned long) high_expr
.X_add_number
>> 16) & 0xffff;
1422 r
= BFD_RELOC_UNUSED
;
1426 assert (ep
->X_op
== O_symbol
);
1427 /* _gp_disp is a special case, used from s_cpload. */
1428 assert (mips_pic
== NO_PIC
1429 || strcmp (S_GET_NAME (ep
->X_add_symbol
), "_gp_disp") == 0);
1430 r
= BFD_RELOC_HI16_S
;
1434 * If the macro is about to expand into a second instruction,
1435 * print a warning if needed. We need to pass ip as a parameter
1436 * to generate a better warning message here...
1438 if (mips_warn_about_macros
&& place
== NULL
&& *counter
== 1)
1439 as_warn ("Macro instruction expanded into multiple instructions");
1442 *counter
+= 1; /* bump instruction counter */
1444 insn
.insn_mo
= (struct mips_opcode
*) hash_find (op_hash
, name
);
1445 assert (insn
.insn_mo
);
1446 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
1447 assert (strcmp (fmt
, insn
.insn_mo
->args
) == 0);
1449 insn
.insn_opcode
= insn
.insn_mo
->match
| (regnum
<< OP_SH_RT
);
1450 if (r
== BFD_RELOC_UNUSED
)
1452 insn
.insn_opcode
|= high_expr
.X_add_number
;
1453 append_insn (place
, &insn
, NULL
, r
);
1456 append_insn (place
, &insn
, &high_expr
, r
);
1460 * Generates code to set the $at register to true (one)
1461 * if reg is less than the immediate expression.
1464 set_at (counter
, reg
, unsignedp
)
1469 if (imm_expr
.X_add_number
>= -0x8000 && imm_expr
.X_add_number
< 0x8000)
1470 macro_build ((char *) NULL
, counter
, &imm_expr
,
1471 unsignedp
? "sltiu" : "slti",
1472 "t,r,j", AT
, reg
, (int) BFD_RELOC_LO16
);
1475 load_register (counter
, AT
, &imm_expr
);
1476 macro_build ((char *) NULL
, counter
, NULL
,
1477 unsignedp
? "sltu" : "slt",
1478 "d,v,t", AT
, reg
, AT
);
1482 /* Warn if an expression is not a constant. */
1485 check_absolute_expr (ip
, ex
)
1486 struct mips_cl_insn
*ip
;
1489 if (ex
->X_op
!= O_constant
)
1490 as_warn ("Instruction %s requires absolute expression", ip
->insn_mo
->name
);
1494 * This routine generates the least number of instructions neccessary to load
1495 * an absolute expression value into a register.
1498 load_register (counter
, reg
, ep
)
1503 assert (ep
->X_op
== O_constant
);
1504 if (ep
->X_add_number
>= -0x8000 && ep
->X_add_number
< 0x8000)
1505 macro_build ((char *) NULL
, counter
, ep
,
1506 mips_isa
< 3 ? "addiu" : "daddiu",
1507 "t,r,j", reg
, 0, (int) BFD_RELOC_LO16
);
1508 else if (ep
->X_add_number
>= 0 && ep
->X_add_number
< 0x10000)
1509 macro_build ((char *) NULL
, counter
, ep
, "ori", "t,r,i", reg
, 0,
1510 (int) BFD_RELOC_LO16
);
1511 else if ((ep
->X_add_number
&~ (offsetT
) 0x7fffffff) == 0
1512 || ((ep
->X_add_number
&~ (offsetT
) 0x7fffffff)
1513 == ~ (offsetT
) 0x7fffffff))
1515 macro_build ((char *) NULL
, counter
, ep
, "lui", "t,u", reg
);
1516 if ((ep
->X_add_number
& 0xffff) != 0)
1517 macro_build ((char *) NULL
, counter
, ep
, "ori", "t,r,i", reg
, reg
,
1518 (int) BFD_RELOC_LO16
);
1520 else if (mips_isa
< 3)
1522 as_bad ("Number larger than 32 bits");
1523 macro_build ((char *) NULL
, counter
, ep
, "addiu", "t,r,j", reg
, 0,
1524 (int) BFD_RELOC_LO16
);
1529 expressionS hi32
, lo32
;
1533 hi32
.X_add_number
>>= shift
;
1534 hi32
.X_add_number
&= 0xffffffff;
1535 if ((hi32
.X_add_number
& 0x80000000) != 0)
1536 hi32
.X_add_number
|= ~ (offsetT
) 0xffffffff;
1537 load_register (counter
, reg
, &hi32
);
1539 lo32
.X_add_number
&= 0xffffffff;
1540 if ((lo32
.X_add_number
& 0xffff0000) == 0)
1541 macro_build ((char *) NULL
, counter
, NULL
, "dsll32", "d,w,<", reg
,
1547 macro_build ((char *) NULL
, counter
, NULL
, "dsll", "d,w,<", reg
,
1550 mid16
.X_add_number
>>= 16;
1551 macro_build ((char *) NULL
, counter
, &mid16
, "ori", "t,r,i", reg
,
1552 reg
, (int) BFD_RELOC_LO16
);
1553 macro_build ((char *) NULL
, counter
, NULL
, "dsll", "d,w,<", reg
,
1556 if ((lo32
.X_add_number
& 0xffff) != 0)
1557 macro_build ((char *) NULL
, counter
, &lo32
, "ori", "t,r,i", reg
, reg
,
1558 (int) BFD_RELOC_LO16
);
1562 /* Load an address into a register. */
1565 load_address (counter
, reg
, ep
)
1572 if (ep
->X_op
!= O_constant
1573 && ep
->X_op
!= O_symbol
)
1575 as_bad ("expression too complex");
1576 ep
->X_op
= O_constant
;
1579 if (ep
->X_op
== O_constant
)
1581 load_register (counter
, reg
, ep
);
1585 if (mips_pic
== NO_PIC
)
1587 /* If this is a reference to a GP relative symbol, we want
1588 addiu $reg,$gp,<sym> (BFD_RELOC_MIPS_GPREL)
1590 lui $reg,<sym> (BFD_RELOC_HI16_S)
1591 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
1592 If we have an addend, we always use the latter form. */
1593 if (ep
->X_add_number
!= 0)
1598 macro_build ((char *) NULL
, counter
, ep
,
1599 mips_isa
< 3 ? "addiu" : "daddiu",
1600 "t,r,j", reg
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
1601 p
= frag_var (rs_machine_dependent
, 8, 0,
1602 RELAX_ENCODE (4, 8, -4, 0, 0, mips_warn_about_macros
),
1603 ep
->X_add_symbol
, (long) 0, (char *) NULL
);
1605 macro_build_lui (p
, counter
, ep
, reg
);
1608 macro_build (p
, counter
, ep
,
1609 mips_isa
< 3 ? "addiu" : "daddiu",
1610 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
1612 else if (mips_pic
== SVR4_PIC
)
1616 /* If this is a reference to an external symbol, we want
1617 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
1619 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
1621 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
1622 If there is a constant, it must be added in after. */
1623 ex
.X_add_number
= ep
->X_add_number
;
1624 ep
->X_add_number
= 0;
1626 macro_build ((char *) NULL
, counter
, ep
,
1627 mips_isa
< 3 ? "lw" : "ld",
1628 "t,o(b)", reg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
1629 macro_build ((char *) NULL
, counter
, (expressionS
*) NULL
, "nop", "");
1630 p
= frag_var (rs_machine_dependent
, 4, 0,
1631 RELAX_ENCODE (0, 4, -8, 0, 0, mips_warn_about_macros
),
1632 ep
->X_add_symbol
, (long) 0, (char *) NULL
);
1633 macro_build (p
, counter
, ep
,
1634 mips_isa
< 3 ? "addiu" : "daddiu",
1635 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
1636 if (ex
.X_add_number
!= 0)
1638 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
1639 as_bad ("PIC code offset overflow (max 16 signed bits)");
1640 ex
.X_op
= O_constant
;
1641 macro_build (p
, counter
, &ex
,
1642 mips_isa
< 3 ? "addiu" : "daddiu",
1643 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
1646 else if (mips_pic
== EMBEDDED_PIC
)
1649 addiu $reg,$gp,<sym> (BFD_RELOC_MIPS_GPREL)
1651 macro_build ((char *) NULL
, counter
, ep
,
1652 mips_isa
< 3 ? "addiu" : "daddiu",
1653 "t,r,j", reg
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
1661 * This routine implements the seemingly endless macro or synthesized
1662 * instructions and addressing modes in the mips assembly language. Many
1663 * of these macros are simple and are similar to each other. These could
1664 * probably be handled by some kind of table or grammer aproach instead of
1665 * this verbose method. Others are not simple macros but are more like
1666 * optimizing code generation.
1667 * One interesting optimization is when several store macros appear
1668 * consecutivly that would load AT with the upper half of the same address.
1669 * The ensuing load upper instructions are ommited. This implies some kind
1670 * of global optimization. We currently only optimize within a single macro.
1671 * For many of the load and store macros if the address is specified as a
1672 * constant expression in the first 64k of memory (ie ld $2,0x4000c) we
1673 * first load register 'at' with zero and use it as the base register. The
1674 * mips assembler simply uses register $zero. Just one tiny optimization
1679 struct mips_cl_insn
*ip
;
1681 register int treg
, sreg
, dreg
, breg
;
1694 bfd_reloc_code_real_type r
;
1697 treg
= (ip
->insn_opcode
>> 16) & 0x1f;
1698 dreg
= (ip
->insn_opcode
>> 11) & 0x1f;
1699 sreg
= breg
= (ip
->insn_opcode
>> 21) & 0x1f;
1700 mask
= ip
->insn_mo
->mask
;
1702 expr1
.X_op
= O_constant
;
1703 expr1
.X_op_symbol
= NULL
;
1704 expr1
.X_add_symbol
= NULL
;
1705 expr1
.X_add_number
= 1;
1717 mips_emit_delays ();
1719 mips_any_noreorder
= 1;
1721 expr1
.X_add_number
= 8;
1722 macro_build ((char *) NULL
, &icnt
, &expr1
, "bgez", "s,p", sreg
);
1724 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
1726 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
, sreg
, 0);
1727 macro_build ((char *) NULL
, &icnt
, NULL
,
1728 dbl
? "dsub" : "sub",
1729 "d,v,t", dreg
, 0, sreg
);
1752 if (imm_expr
.X_add_number
>= -0x8000 && imm_expr
.X_add_number
< 0x8000)
1754 macro_build ((char *) NULL
, &icnt
, &imm_expr
, s
, "t,r,j", treg
, sreg
,
1755 (int) BFD_RELOC_LO16
);
1758 load_register (&icnt
, AT
, &imm_expr
);
1759 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "d,v,t", treg
, sreg
, AT
);
1778 if (imm_expr
.X_add_number
>= 0 && imm_expr
.X_add_number
< 0x10000)
1780 if (mask
!= M_NOR_I
)
1781 macro_build ((char *) NULL
, &icnt
, &imm_expr
, s
, "t,r,i", treg
,
1782 sreg
, (int) BFD_RELOC_LO16
);
1785 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "ori", "t,r,i",
1786 treg
, sreg
, (int) BFD_RELOC_LO16
);
1787 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "nor", "d,v,t",
1793 load_register (&icnt
, AT
, &imm_expr
);
1794 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "d,v,t", treg
, sreg
, AT
);
1811 if (imm_expr
.X_add_number
== 0)
1813 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "s,t,p", sreg
,
1817 load_register (&icnt
, AT
, &imm_expr
);
1818 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "s,t,p", sreg
, AT
);
1826 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
1827 likely
? "bgezl" : "bgez",
1833 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
1834 likely
? "blezl" : "blez",
1838 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", AT
, sreg
, treg
);
1839 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
1840 likely
? "beql" : "beq",
1847 /* check for > max integer */
1848 maxnum
= 0x7fffffff;
1856 if (imm_expr
.X_add_number
>= maxnum
)
1859 /* result is always false */
1862 as_warn ("Branch %s is always false (nop)", ip
->insn_mo
->name
);
1863 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
1867 as_warn ("Branch likely %s is always false", ip
->insn_mo
->name
);
1868 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "bnel",
1873 imm_expr
.X_add_number
++;
1877 if (mask
== M_BGEL_I
)
1879 if (imm_expr
.X_add_number
== 0)
1881 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
1882 likely
? "bgezl" : "bgez",
1886 if (imm_expr
.X_add_number
== 1)
1888 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
1889 likely
? "bgtzl" : "bgtz",
1893 maxnum
= 0x7fffffff;
1901 maxnum
= - maxnum
- 1;
1902 if (imm_expr
.X_add_number
<= maxnum
)
1905 /* result is always true */
1906 as_warn ("Branch %s is always true", ip
->insn_mo
->name
);
1907 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "b", "p");
1910 set_at (&icnt
, sreg
, 0);
1911 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
1912 likely
? "beql" : "beq",
1923 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
1924 likely
? "beql" : "beq",
1928 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", AT
, sreg
,
1930 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
1931 likely
? "beql" : "beq",
1938 if (sreg
== 0 || imm_expr
.X_add_number
== -1)
1940 imm_expr
.X_add_number
++;
1944 if (mask
== M_BGEUL_I
)
1946 if (imm_expr
.X_add_number
== 0)
1948 if (imm_expr
.X_add_number
== 1)
1950 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
1951 likely
? "bnel" : "bne",
1955 set_at (&icnt
, sreg
, 1);
1956 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
1957 likely
? "beql" : "beq",
1966 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
1967 likely
? "bgtzl" : "bgtz",
1973 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
1974 likely
? "bltzl" : "bltz",
1978 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", AT
, treg
, sreg
);
1979 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
1980 likely
? "bnel" : "bne",
1989 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
1990 likely
? "bnel" : "bne",
1996 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", AT
, treg
,
1998 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
1999 likely
? "bnel" : "bne",
2008 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2009 likely
? "blezl" : "blez",
2015 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2016 likely
? "bgezl" : "bgez",
2020 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", AT
, treg
, sreg
);
2021 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2022 likely
? "beql" : "beq",
2029 maxnum
= 0x7fffffff;
2037 if (imm_expr
.X_add_number
>= maxnum
)
2039 imm_expr
.X_add_number
++;
2043 if (mask
== M_BLTL_I
)
2045 if (imm_expr
.X_add_number
== 0)
2047 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2048 likely
? "bltzl" : "bltz",
2052 if (imm_expr
.X_add_number
== 1)
2054 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2055 likely
? "blezl" : "blez",
2059 set_at (&icnt
, sreg
, 0);
2060 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2061 likely
? "bnel" : "bne",
2070 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2071 likely
? "beql" : "beq",
2077 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", AT
, treg
,
2079 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2080 likely
? "beql" : "beq",
2087 if (sreg
== 0 || imm_expr
.X_add_number
== -1)
2089 imm_expr
.X_add_number
++;
2093 if (mask
== M_BLTUL_I
)
2095 if (imm_expr
.X_add_number
== 0)
2097 if (imm_expr
.X_add_number
== 1)
2099 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2100 likely
? "beql" : "beq",
2104 set_at (&icnt
, sreg
, 1);
2105 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2106 likely
? "bnel" : "bne",
2115 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2116 likely
? "bltzl" : "bltz",
2122 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2123 likely
? "bgtzl" : "bgtz",
2127 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", AT
, sreg
, treg
);
2128 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2129 likely
? "bnel" : "bne",
2140 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2141 likely
? "bnel" : "bne",
2145 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", AT
, sreg
,
2147 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2148 likely
? "bnel" : "bne",
2164 as_warn ("Divide by zero.");
2166 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", 0, 0);
2168 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 7);
2172 mips_emit_delays ();
2174 mips_any_noreorder
= 1;
2175 macro_build ((char *) NULL
, &icnt
, NULL
,
2176 dbl
? "ddiv" : "div",
2177 "z,s,t", sreg
, treg
);
2179 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", treg
, 0);
2182 expr1
.X_add_number
= 8;
2183 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", treg
, 0);
2184 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
2185 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 7);
2187 expr1
.X_add_number
= -1;
2188 macro_build ((char *) NULL
, &icnt
, &expr1
,
2189 dbl
? "daddiu" : "addiu",
2190 "t,r,j", AT
, 0, (int) BFD_RELOC_LO16
);
2191 expr1
.X_add_number
= mips_trap
? (dbl
? 12 : 8) : (dbl
? 20 : 16);
2192 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", treg
, AT
);
2195 expr1
.X_add_number
= 1;
2196 macro_build ((char *) NULL
, &icnt
, &expr1
, "daddiu", "t,r,j", AT
, 0,
2197 (int) BFD_RELOC_LO16
);
2198 macro_build ((char *) NULL
, &icnt
, NULL
, "dsll32", "d,w,<", AT
, AT
,
2203 expr1
.X_add_number
= 0x80000000;
2204 macro_build ((char *) NULL
, &icnt
, &expr1
, "lui", "t,u", AT
);
2207 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", sreg
, AT
);
2210 expr1
.X_add_number
= 8;
2211 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", sreg
, AT
);
2212 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
2213 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 6);
2216 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d", dreg
);
2255 if (imm_expr
.X_add_number
== 0)
2257 as_warn ("Divide by zero.");
2259 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", 0, 0);
2261 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 7);
2264 if (imm_expr
.X_add_number
== 1)
2266 if (strcmp (s2
, "mflo") == 0)
2267 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
,
2270 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
, 0);
2273 if (imm_expr
.X_add_number
== -1
2274 && s
[strlen (s
) - 1] != 'u')
2276 if (strcmp (s2
, "mflo") == 0)
2279 macro_build ((char *) NULL
, &icnt
, NULL
, "dneg", "d,w", dreg
,
2282 macro_build ((char *) NULL
, &icnt
, NULL
, "neg", "d,w", dreg
,
2286 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
, 0);
2290 load_register (&icnt
, AT
, &imm_expr
);
2291 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "z,s,t", sreg
, AT
);
2292 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "d", dreg
);
2311 mips_emit_delays ();
2313 mips_any_noreorder
= 1;
2314 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "z,s,t", sreg
, treg
);
2316 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", treg
, 0);
2319 expr1
.X_add_number
= 8;
2320 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", treg
, 0);
2321 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
2322 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 7);
2325 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "d", dreg
);
2329 /* Load the address of a symbol into a register. If breg is not
2330 zero, we then add a base register to it. */
2331 if (offset_expr
.X_op
!= O_symbol
2332 && offset_expr
.X_op
!= O_constant
)
2334 as_bad ("expression too complex");
2335 offset_expr
.X_op
= O_constant
;
2349 if (offset_expr
.X_op
== O_constant
)
2350 load_register (&icnt
, tempreg
, &offset_expr
);
2351 else if (mips_pic
== NO_PIC
)
2353 /* If this is a reference to an GP relative symbol, we want
2354 addiu $tempreg,$gp,<sym> (BFD_RELOC_MIPS_GPREL)
2356 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
2357 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
2358 If we have a constant, we need two instructions anyhow,
2359 so we may as well always use the latter form. */
2360 if (offset_expr
.X_add_number
!= 0)
2365 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2366 mips_isa
< 3 ? "addiu" : "daddiu",
2367 "t,r,j", tempreg
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
2368 p
= frag_var (rs_machine_dependent
, 8, 0,
2369 RELAX_ENCODE (4, 8, 0, 4, 0,
2370 mips_warn_about_macros
),
2371 offset_expr
.X_add_symbol
, (long) 0,
2374 macro_build_lui (p
, &icnt
, &offset_expr
, tempreg
);
2377 macro_build (p
, &icnt
, &offset_expr
,
2378 mips_isa
< 3 ? "addiu" : "daddiu",
2379 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
2381 else if (mips_pic
== SVR4_PIC
)
2383 /* If this is a reference to an external symbol, and there
2384 is no constant, we want
2385 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
2386 For a local symbol, we want
2387 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
2389 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
2391 If we have a small constant, and this is a reference to
2392 an external symbol, we want
2393 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
2395 addiu $tempreg,$tempreg,<constant>
2396 For a local symbol, we want the same instruction
2397 sequence, but we output a BFD_RELOC_LO16 reloc on the
2400 If we have a large constant, and this is a reference to
2401 an external symbol, we want
2402 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
2403 lui $at,<hiconstant>
2404 addiu $at,$at,<loconstant>
2405 addu $tempreg,$tempreg,$at
2406 For a local symbol, we want the same instruction
2407 sequence, but we output a BFD_RELOC_LO16 reloc on the
2408 addiu instruction. */
2409 expr1
.X_add_number
= offset_expr
.X_add_number
;
2410 offset_expr
.X_add_number
= 0;
2412 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2413 mips_isa
< 3 ? "lw" : "ld",
2414 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
2415 if (expr1
.X_add_number
== 0)
2423 /* We're going to put in an addu instruction using
2424 tempreg, so we may as well insert the nop right
2426 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
2430 p
= frag_var (rs_machine_dependent
, 8 - off
, 0,
2431 RELAX_ENCODE (0, 8 - off
, -4 - off
, 4 - off
, 0,
2433 ? mips_warn_about_macros
2435 offset_expr
.X_add_symbol
, (long) 0,
2439 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
2442 macro_build (p
, &icnt
, &expr1
,
2443 mips_isa
< 3 ? "addiu" : "daddiu",
2444 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
2445 /* FIXME: If breg == 0, and the next instruction uses
2446 $tempreg, then if this variant case is used an extra
2447 nop will be generated. */
2449 else if (expr1
.X_add_number
>= -0x8000
2450 && expr1
.X_add_number
< 0x8000)
2452 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
2454 macro_build ((char *) NULL
, &icnt
, &expr1
,
2455 mips_isa
< 3 ? "addiu" : "daddiu",
2456 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
2457 (void) frag_var (rs_machine_dependent
, 0, 0,
2458 RELAX_ENCODE (0, 0, -12, -4, 0, 0),
2459 offset_expr
.X_add_symbol
, (long) 0,
2466 /* If we are going to add in a base register, and the
2467 target register and the base register are the same,
2468 then we are using AT as a temporary register. Since
2469 we want to load the constant into AT, we add our
2470 current AT (from the global offset table) and the
2471 register into the register now, and pretend we were
2472 not using a base register. */
2477 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
2479 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
2480 mips_isa
< 3 ? "addu" : "daddu",
2481 "d,v,t", treg
, AT
, breg
);
2487 macro_build_lui ((char *) NULL
, &icnt
, &expr1
, AT
);
2488 macro_build ((char *) NULL
, &icnt
, &expr1
,
2489 mips_isa
< 3 ? "addiu" : "daddiu",
2490 "t,r,j", AT
, AT
, (int) BFD_RELOC_LO16
);
2491 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
2492 mips_isa
< 3 ? "addu" : "daddu",
2493 "d,v,t", tempreg
, tempreg
, AT
);
2494 (void) frag_var (rs_machine_dependent
, 0, 0,
2495 RELAX_ENCODE (0, 0, -16 + off1
, -8, 0, 0),
2496 offset_expr
.X_add_symbol
, (long) 0,
2501 else if (mips_pic
== EMBEDDED_PIC
)
2504 addiu $tempreg,$gp,<sym> (BFD_RELOC_MIPS_GPREL)
2506 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2507 mips_isa
< 3 ? "addiu" : "daddiu",
2508 "t,r,j", tempreg
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
2514 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
2515 mips_isa
< 3 ? "addu" : "daddu",
2516 "d,v,t", treg
, tempreg
, breg
);
2524 /* The j instruction may not be used in PIC code, since it
2525 requires an absolute address. We convert it to a b
2527 if (mips_pic
== NO_PIC
)
2528 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "j", "a");
2530 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "b", "p");
2533 /* The jal instructions must be handled as macros because when
2534 generating PIC code they expand to multi-instruction
2535 sequences. Normally they are simple instructions. */
2540 if (mips_pic
== NO_PIC
2541 || mips_pic
== EMBEDDED_PIC
)
2542 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "jalr",
2544 else if (mips_pic
== SVR4_PIC
)
2546 if (sreg
!= PIC_CALL_REG
)
2547 as_warn ("MIPS PIC call to register other than $25");
2549 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "jalr",
2551 if (mips_cprestore_offset
< 0)
2552 as_warn ("No .cprestore pseudo-op used in PIC code");
2555 expr1
.X_add_number
= mips_cprestore_offset
;
2556 macro_build ((char *) NULL
, &icnt
, &expr1
,
2557 mips_isa
< 3 ? "lw" : "ld",
2558 "t,o(b)", GP
, (int) BFD_RELOC_LO16
, mips_frame_reg
);
2567 if (mips_pic
== NO_PIC
)
2568 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "jal", "a");
2569 else if (mips_pic
== SVR4_PIC
)
2571 /* If this is a reference to an external symbol, we want
2572 lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
2576 lw $gp,cprestore($sp)
2577 The cprestore value is set using the .cprestore
2578 pseudo-op. If the symbol is not external, we want
2579 lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
2581 addiu $25,$25,<sym> (BFD_RELOC_LO16)
2584 lw $gp,cprestore($sp)
2587 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2588 mips_isa
< 3 ? "lw" : "ld",
2589 "t,o(b)", PIC_CALL_REG
,
2590 (int) BFD_RELOC_MIPS_CALL16
, GP
);
2591 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
2592 p
= frag_var (rs_machine_dependent
, 4, 0,
2593 RELAX_ENCODE (0, 4, -8, 0, 0, 0),
2594 offset_expr
.X_add_symbol
, (long) 0, (char *) NULL
);
2595 macro_build (p
, &icnt
, &offset_expr
,
2596 mips_isa
< 3 ? "addiu" : "daddiu",
2597 "t,r,j", PIC_CALL_REG
, PIC_CALL_REG
,
2598 (int) BFD_RELOC_LO16
);
2599 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
2600 "jalr", "s", PIC_CALL_REG
);
2601 if (mips_cprestore_offset
< 0)
2602 as_warn ("No .cprestore pseudo-op used in PIC code");
2606 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
2608 expr1
.X_add_number
= mips_cprestore_offset
;
2609 macro_build ((char *) NULL
, &icnt
, &expr1
,
2610 mips_isa
< 3 ? "lw" : "ld",
2611 "t,o(b)", GP
, (int) BFD_RELOC_LO16
,
2615 else if (mips_pic
== EMBEDDED_PIC
)
2616 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "bal", "p");
2686 if (breg
== treg
|| coproc
)
2755 if (mask
== M_LWC1_AB
2756 || mask
== M_SWC1_AB
2757 || mask
== M_LDC1_AB
2758 || mask
== M_SDC1_AB
2767 if (offset_expr
.X_op
!= O_constant
2768 && offset_expr
.X_op
!= O_symbol
)
2770 as_bad ("expression too complex");
2771 offset_expr
.X_op
= O_constant
;
2774 /* A constant expression in PIC code can be handled just as it
2775 is in non PIC code. */
2776 if (mips_pic
== NO_PIC
2777 || offset_expr
.X_op
== O_constant
)
2779 /* If this is a reference to a GP relative symbol, and there
2780 is no base register, we want
2781 <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL)
2782 Otherwise, if there is no base register, we want
2783 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
2784 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
2785 If we have a constant, we need two instructions anyhow,
2786 so we always use the latter form.
2788 If we have a base register, and this is a reference to a
2789 GP relative symbol, we want
2790 addu $tempreg,$breg,$gp
2791 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GPREL)
2793 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
2794 addu $tempreg,$tempreg,$breg
2795 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
2796 With a constant we always use the latter case. */
2799 if (offset_expr
.X_add_number
!= 0)
2804 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
2805 treg
, (int) BFD_RELOC_MIPS_GPREL
, GP
);
2806 p
= frag_var (rs_machine_dependent
, 8, 0,
2807 RELAX_ENCODE (4, 8, 0, 4, 0,
2808 (mips_warn_about_macros
2809 || (used_at
&& mips_noat
))),
2810 offset_expr
.X_add_symbol
, (long) 0,
2814 macro_build_lui (p
, &icnt
, &offset_expr
, tempreg
);
2817 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
, treg
,
2818 (int) BFD_RELOC_LO16
, tempreg
);
2822 if (offset_expr
.X_add_number
!= 0)
2827 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
2828 mips_isa
< 3 ? "addu" : "daddu",
2829 "d,v,t", tempreg
, breg
, GP
);
2830 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
2831 treg
, (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
2832 p
= frag_var (rs_machine_dependent
, 12, 0,
2833 RELAX_ENCODE (8, 12, 0, 8, 0, 0),
2834 offset_expr
.X_add_symbol
, (long) 0,
2837 macro_build_lui (p
, &icnt
, &offset_expr
, tempreg
);
2840 macro_build (p
, &icnt
, (expressionS
*) NULL
,
2841 mips_isa
< 3 ? "addu" : "daddu",
2842 "d,v,t", tempreg
, tempreg
, breg
);
2845 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
, treg
,
2846 (int) BFD_RELOC_LO16
, tempreg
);
2849 else if (mips_pic
== SVR4_PIC
)
2851 /* If this is a reference to an external symbol, we want
2852 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
2854 <op> $treg,0($tempreg)
2856 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
2858 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
2859 <op> $treg,0($tempreg)
2860 If there is a base register, we add it to $tempreg before
2861 the <op>. If there is a constant, we stick it in the
2862 <op> instruction. We don't handle constants larger than
2863 16 bits, because we have no way to load the upper 16 bits
2864 (actually, we could handle them for the subset of cases
2865 in which we are not using $at). */
2866 assert (offset_expr
.X_op
== O_symbol
);
2867 expr1
.X_add_number
= offset_expr
.X_add_number
;
2868 offset_expr
.X_add_number
= 0;
2869 if (expr1
.X_add_number
< -0x8000
2870 || expr1
.X_add_number
>= 0x8000)
2871 as_bad ("PIC code offset overflow (max 16 signed bits)");
2873 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2874 mips_isa
< 3 ? "lw" : "ld",
2875 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
2876 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
2877 p
= frag_var (rs_machine_dependent
, 4, 0,
2878 RELAX_ENCODE (0, 4, -8, 0, 0, 0),
2879 offset_expr
.X_add_symbol
, (long) 0,
2881 macro_build (p
, &icnt
, &offset_expr
,
2882 mips_isa
< 3 ? "addiu" : "daddiu",
2883 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
2885 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
2886 mips_isa
< 3 ? "addu" : "daddu",
2887 "d,v,t", tempreg
, tempreg
, breg
);
2888 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
, treg
,
2889 (int) BFD_RELOC_LO16
, tempreg
);
2891 else if (mips_pic
== EMBEDDED_PIC
)
2893 /* If there is no base register, we want
2894 <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL)
2895 If there is a base register, we want
2896 addu $tempreg,$breg,$gp
2897 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GPREL)
2899 assert (offset_expr
.X_op
== O_symbol
);
2902 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
2903 treg
, (int) BFD_RELOC_MIPS_GPREL
, GP
);
2908 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
2909 mips_isa
< 3 ? "addu" : "daddu",
2910 "d,v,t", tempreg
, breg
, GP
);
2911 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
2912 treg
, (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
2925 load_register (&icnt
, treg
, &imm_expr
);
2929 if (mips_pic
== NO_PIC
)
2931 assert (offset_expr
.X_op
== O_symbol
2932 && strcmp (segment_name (S_GET_SEGMENT
2933 (offset_expr
.X_add_symbol
)),
2935 && offset_expr
.X_add_number
== 0);
2936 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lwc1", "T,o(b)",
2937 treg
, (int) BFD_RELOC_MIPS_LITERAL
, GP
);
2939 else if (mips_pic
== SVR4_PIC
2940 || mips_pic
== EMBEDDED_PIC
)
2942 assert (imm_expr
.X_op
== O_constant
);
2943 load_register (&icnt
, treg
, &imm_expr
);
2951 /* We know that sym is in the .rdata section. First we get the
2952 upper 16 bits of the address. */
2953 if (mips_pic
== NO_PIC
)
2955 /* FIXME: This won't work for a 64 bit address. */
2956 macro_build_lui ((char *) NULL
, &icnt
, &offset_expr
, AT
);
2958 else if (mips_pic
== SVR4_PIC
)
2960 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2961 mips_isa
< 3 ? "lw" : "ld",
2962 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
2964 else if (mips_pic
== EMBEDDED_PIC
)
2966 /* For embedded PIC we pick up the entire address off $gp in
2967 a single instruction. */
2968 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2969 mips_isa
< 3 ? "addiu" : "daddiu",
2970 "t,r,j", AT
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
2971 offset_expr
.X_op
= O_constant
;
2972 offset_expr
.X_add_number
= 0;
2977 /* Now we load the register(s). */
2979 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "ld", "t,o(b)",
2980 treg
, (int) BFD_RELOC_LO16
, AT
);
2983 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lw", "t,o(b)",
2984 treg
, (int) BFD_RELOC_LO16
, AT
);
2987 /* FIXME: How in the world do we deal with the possible
2989 offset_expr
.X_add_number
+= 4;
2990 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lw", "t,o(b)",
2991 treg
+ 1, (int) BFD_RELOC_LO16
, AT
);
2998 if (mips_pic
== NO_PIC
2999 || mips_pic
== EMBEDDED_PIC
)
3001 /* Load a floating point number from the .lit8 section. */
3002 assert (offset_expr
.X_op
== O_symbol
3003 && strcmp (segment_name (S_GET_SEGMENT
3004 (offset_expr
.X_add_symbol
)),
3006 && offset_expr
.X_add_number
== 0);
3009 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "ldc1",
3010 "T,o(b)", treg
, (int) BFD_RELOC_MIPS_LITERAL
, GP
);
3014 r
= BFD_RELOC_MIPS_LITERAL
;
3017 else if (mips_pic
== SVR4_PIC
)
3019 /* Load the double from the .rdata section. */
3020 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3021 mips_isa
< 3 ? "lw" : "ld",
3022 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
3025 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "ldc1",
3026 "T,o(b)", treg
, (int) BFD_RELOC_LO16
, GP
);
3037 /* Even on a big endian machine $fn comes before $fn+1. We have
3038 to adjust when loading from memory. */
3041 assert (mips_isa
< 2);
3042 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lwc1", "T,o(b)",
3043 byte_order
== LITTLE_ENDIAN
? treg
: treg
+ 1,
3045 /* FIXME: A possible overflow which I don't know how to deal
3047 offset_expr
.X_add_number
+= 4;
3048 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lwc1", "T,o(b)",
3049 byte_order
== LITTLE_ENDIAN
? treg
+ 1 : treg
,
3057 * The MIPS assembler seems to check for X_add_number not
3058 * being double aligned and generating:
3061 * addiu at,at,%lo(foo+1)
3064 * But, the resulting address is the same after relocation so why
3065 * generate the extra instruction?
3112 if (offset_expr
.X_op
!= O_symbol
3113 && offset_expr
.X_op
!= O_constant
)
3115 as_bad ("expression too complex");
3116 offset_expr
.X_op
= O_constant
;
3119 /* Even on a big endian machine $fn comes before $fn+1. We have
3120 to adjust when loading from memory. We set coproc if we must
3121 load $fn+1 first. */
3122 if (byte_order
== LITTLE_ENDIAN
)
3125 if (mips_pic
== NO_PIC
3126 || offset_expr
.X_op
== O_constant
)
3128 /* If this is a reference to a GP relative symbol, we want
3129 <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL)
3130 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_MIPS_GPREL)
3131 If we have a base register, we use this
3133 <op> $treg,<sym>($at) (BFD_RELOC_MIPS_GPREL)
3134 <op> $treg+1,<sym>+4($at) (BFD_RELOC_MIPS_GPREL)
3135 If this is not a GP relative symbol, we want
3136 lui $at,<sym> (BFD_RELOC_HI16_S)
3137 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
3138 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
3139 If there is a base register, we add it to $at after the
3140 lui instruction. If there is a constant, we always use
3142 if (offset_expr
.X_add_number
!= 0)
3161 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3162 mips_isa
< 3 ? "addu" : "daddu",
3163 "d,v,t", AT
, breg
, GP
);
3169 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
3170 coproc
? treg
+ 1 : treg
,
3171 (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
3172 offset_expr
.X_add_number
+= 4;
3173 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
3174 coproc
? treg
: treg
+ 1,
3175 (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
3176 p
= frag_var (rs_machine_dependent
, 12 + off
, 0,
3177 RELAX_ENCODE (8 + off
, 12 + off
, 0, 4 + off
, 1,
3178 used_at
&& mips_noat
),
3179 offset_expr
.X_add_symbol
, (long) 0,
3182 /* We just generated two relocs. When tc_gen_reloc
3183 handles this case, it will skip the first reloc and
3184 handle the second. The second reloc already has an
3185 extra addend of 4, which we added above. We must
3186 subtract it out, and then subtract another 4 to make
3187 the first reloc come out right. The second reloc
3188 will come out right because we are going to add 4 to
3189 offset_expr when we build its instruction below. */
3190 offset_expr
.X_add_number
-= 8;
3191 offset_expr
.X_op
= O_constant
;
3193 macro_build_lui (p
, &icnt
, &offset_expr
, AT
);
3198 macro_build (p
, &icnt
, (expressionS
*) NULL
,
3199 mips_isa
< 3 ? "addu" : "daddu",
3200 "d,v,t", AT
, breg
, AT
);
3204 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
,
3205 coproc
? treg
+ 1 : treg
,
3206 (int) BFD_RELOC_LO16
, AT
);
3209 /* FIXME: How do we handle overflow here? */
3210 offset_expr
.X_add_number
+= 4;
3211 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
,
3212 coproc
? treg
: treg
+ 1,
3213 (int) BFD_RELOC_LO16
, AT
);
3215 else if (mips_pic
== SVR4_PIC
)
3219 /* If this is a reference to an external symbol, we want
3220 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3225 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3227 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
3228 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
3229 If there is a base register we add it to $at before the
3230 lwc1 instructions. If there is a constant we include it
3231 in the lwc1 instructions. */
3233 expr1
.X_add_number
= offset_expr
.X_add_number
;
3234 offset_expr
.X_add_number
= 0;
3235 if (expr1
.X_add_number
< -0x8000
3236 || expr1
.X_add_number
>= 0x8000 - 4)
3237 as_bad ("PIC code offset overflow (max 16 signed bits)");
3242 frag_grow (24 + off
);
3243 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3244 mips_isa
< 3 ? "lw" : "ld",
3245 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
3246 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
3248 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3249 mips_isa
< 3 ? "addu" : "daddu",
3250 "d,v,t", AT
, breg
, AT
);
3251 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
3252 coproc
? treg
+ 1 : treg
,
3253 (int) BFD_RELOC_LO16
, AT
);
3254 expr1
.X_add_number
+= 4;
3255 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
3256 coproc
? treg
: treg
+ 1,
3257 (int) BFD_RELOC_LO16
, AT
);
3258 (void) frag_var (rs_machine_dependent
, 0, 0,
3259 RELAX_ENCODE (0, 0, -16 - off
, -8, 1, 0),
3260 offset_expr
.X_add_symbol
, (long) 0,
3263 else if (mips_pic
== EMBEDDED_PIC
)
3265 /* If there is no base register, we use
3266 <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL)
3267 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_MIPS_GPREL)
3268 If we have a base register, we use
3270 <op> $treg,<sym>($at) (BFD_RELOC_MIPS_GPREL)
3271 <op> $treg+1,<sym>+4($at) (BFD_RELOC_MIPS_GPREL)
3280 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3281 mips_isa
< 3 ? "addu" : "daddu",
3282 "d,v,t", AT
, breg
, GP
);
3287 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
3288 coproc
? treg
+ 1 : treg
,
3289 (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
3290 offset_expr
.X_add_number
+= 4;
3291 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
3292 coproc
? treg
: treg
+ 1,
3293 (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
3309 assert (mips_isa
< 3);
3310 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
3311 (int) BFD_RELOC_LO16
, breg
);
3312 offset_expr
.X_add_number
+= 4;
3313 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
+ 1,
3314 (int) BFD_RELOC_LO16
, breg
);
3316 #ifdef LOSING_COMPILER
3322 as_warn ("Macro used $at after \".set noat\"");
3327 struct mips_cl_insn
*ip
;
3329 register int treg
, sreg
, dreg
, breg
;
3342 bfd_reloc_code_real_type r
;
3345 treg
= (ip
->insn_opcode
>> 16) & 0x1f;
3346 dreg
= (ip
->insn_opcode
>> 11) & 0x1f;
3347 sreg
= breg
= (ip
->insn_opcode
>> 21) & 0x1f;
3348 mask
= ip
->insn_mo
->mask
;
3350 expr1
.X_op
= O_constant
;
3351 expr1
.X_op_symbol
= NULL
;
3352 expr1
.X_add_symbol
= NULL
;
3353 expr1
.X_add_number
= 1;
3357 #endif /* LOSING_COMPILER */
3362 macro_build ((char *) NULL
, &icnt
, NULL
,
3363 dbl
? "dmultu" : "multu",
3365 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
3371 /* The MIPS assembler some times generates shifts and adds. I'm
3372 not trying to be that fancy. GCC should do this for us
3374 load_register (&icnt
, AT
, &imm_expr
);
3375 macro_build ((char *) NULL
, &icnt
, NULL
,
3376 dbl
? "dmult" : "mult",
3378 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
3384 mips_emit_delays ();
3386 mips_any_noreorder
= 1;
3387 macro_build ((char *) NULL
, &icnt
, NULL
,
3388 dbl
? "dmult" : "mult",
3390 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
3391 macro_build ((char *) NULL
, &icnt
, NULL
,
3392 dbl
? "dsra32" : "sra",
3393 "d,w,<", dreg
, dreg
, 31);
3394 macro_build ((char *) NULL
, &icnt
, NULL
, "mfhi", "d", AT
);
3396 macro_build ((char *) NULL
, &icnt
, NULL
, "tne", "s,t", dreg
, AT
);
3399 expr1
.X_add_number
= 8;
3400 macro_build ((char *) NULL
, &icnt
, &expr1
, "beq", "s,t,p", dreg
, AT
);
3401 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
3402 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 6);
3405 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
3411 mips_emit_delays ();
3413 mips_any_noreorder
= 1;
3414 macro_build ((char *) NULL
, &icnt
, NULL
,
3415 dbl
? "dmultu" : "multu",
3417 macro_build ((char *) NULL
, &icnt
, NULL
, "mfhi", "d", AT
);
3418 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
3420 macro_build ((char *) NULL
, &icnt
, NULL
, "tne", "s,t", AT
, 0);
3423 expr1
.X_add_number
= 8;
3424 macro_build ((char *) NULL
, &icnt
, &expr1
, "beq", "s,t,p", AT
, 0);
3425 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
3426 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 6);
3432 macro_build ((char *) NULL
, &icnt
, NULL
, "subu", "d,v,t", AT
, 0, treg
);
3433 macro_build ((char *) NULL
, &icnt
, NULL
, "srlv", "d,t,s", AT
, sreg
, AT
);
3434 macro_build ((char *) NULL
, &icnt
, NULL
, "sllv", "d,t,s", dreg
, sreg
,
3436 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
3440 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", AT
, sreg
,
3441 imm_expr
.X_add_number
& 0x1f);
3442 macro_build ((char *) NULL
, &icnt
, NULL
, "srl", "d,w,<", dreg
, sreg
,
3443 (0 - imm_expr
.X_add_number
) & 0x1f);
3444 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
3448 macro_build ((char *) NULL
, &icnt
, NULL
, "subu", "d,v,t", AT
, 0, treg
);
3449 macro_build ((char *) NULL
, &icnt
, NULL
, "sllv", "d,t,s", AT
, sreg
, AT
);
3450 macro_build ((char *) NULL
, &icnt
, NULL
, "srlv", "d,t,s", dreg
, sreg
,
3452 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
3456 macro_build ((char *) NULL
, &icnt
, NULL
, "srl", "d,w,<", AT
, sreg
,
3457 imm_expr
.X_add_number
& 0x1f);
3458 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", dreg
, sreg
,
3459 (0 - imm_expr
.X_add_number
) & 0x1f);
3460 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
3464 assert (mips_isa
< 2);
3465 /* Even on a big endian machine $fn comes before $fn+1. We have
3466 to adjust when storing to memory. */
3467 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "swc1", "T,o(b)",
3468 byte_order
== LITTLE_ENDIAN
? treg
: treg
+ 1,
3469 (int) BFD_RELOC_LO16
, breg
);
3470 offset_expr
.X_add_number
+= 4;
3471 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "swc1", "T,o(b)",
3472 byte_order
== LITTLE_ENDIAN
? treg
+ 1 : treg
,
3473 (int) BFD_RELOC_LO16
, breg
);
3478 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
3479 treg
, (int) BFD_RELOC_LO16
);
3481 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
3482 sreg
, (int) BFD_RELOC_LO16
);
3485 macro_build ((char *) NULL
, &icnt
, NULL
, "xor", "d,v,t", dreg
,
3487 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
3488 dreg
, (int) BFD_RELOC_LO16
);
3493 if (imm_expr
.X_add_number
== 0)
3495 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
3496 sreg
, (int) BFD_RELOC_LO16
);
3501 as_warn ("Instruction %s: result is always false",
3503 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
, 0);
3506 if (imm_expr
.X_add_number
>= 0 && imm_expr
.X_add_number
< 0x10000)
3508 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "xori", "t,r,i", dreg
,
3509 sreg
, (int) BFD_RELOC_LO16
);
3512 else if (imm_expr
.X_add_number
> -0x8000 && imm_expr
.X_add_number
< 0)
3514 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
3515 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
3516 mips_isa
< 3 ? "addiu" : "daddiu",
3517 "t,r,j", dreg
, sreg
,
3518 (int) BFD_RELOC_LO16
);
3523 load_register (&icnt
, AT
, &imm_expr
);
3524 macro_build ((char *) NULL
, &icnt
, NULL
, "xor", "d,v,t", dreg
,
3528 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
, dreg
,
3529 (int) BFD_RELOC_LO16
);
3534 case M_SGE
: /* sreg >= treg <==> not (sreg < treg) */
3540 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, sreg
, treg
);
3541 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
3542 (int) BFD_RELOC_LO16
);
3545 case M_SGE_I
: /* sreg >= I <==> not (sreg < I) */
3547 if (imm_expr
.X_add_number
>= -0x8000 && imm_expr
.X_add_number
< 0x8000)
3549 macro_build ((char *) NULL
, &icnt
, &expr1
,
3550 mask
== M_SGE_I
? "slti" : "sltiu",
3551 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
3556 load_register (&icnt
, AT
, &imm_expr
);
3557 macro_build ((char *) NULL
, &icnt
, NULL
,
3558 mask
== M_SGE_I
? "slt" : "sltu",
3559 "d,v,t", dreg
, sreg
, AT
);
3562 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
3563 (int) BFD_RELOC_LO16
);
3568 case M_SGT
: /* sreg > treg <==> treg < sreg */
3574 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, treg
, sreg
);
3577 case M_SGT_I
: /* sreg > I <==> I < sreg */
3583 load_register (&icnt
, AT
, &imm_expr
);
3584 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, AT
, sreg
);
3587 case M_SLE
: /* sreg <= treg <==> treg >= sreg <==> not (treg < sreg) */
3593 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, treg
, sreg
);
3594 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
3595 (int) BFD_RELOC_LO16
);
3598 case M_SLE_I
: /* sreg <= I <==> I >= sreg <==> not (I < sreg) */
3604 load_register (&icnt
, AT
, &imm_expr
);
3605 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, AT
, sreg
);
3606 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
3607 (int) BFD_RELOC_LO16
);
3611 if (imm_expr
.X_add_number
>= -0x8000 && imm_expr
.X_add_number
< 0x8000)
3613 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "slti", "t,r,j",
3614 dreg
, sreg
, (int) BFD_RELOC_LO16
);
3617 load_register (&icnt
, AT
, &imm_expr
);
3618 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", dreg
, sreg
, AT
);
3622 if (imm_expr
.X_add_number
>= -0x8000 && imm_expr
.X_add_number
< 0x8000)
3624 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "sltiu", "t,r,j",
3625 dreg
, sreg
, (int) BFD_RELOC_LO16
);
3628 load_register (&icnt
, AT
, &imm_expr
);
3629 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, sreg
,
3635 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0,
3638 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0,
3642 macro_build ((char *) NULL
, &icnt
, NULL
, "xor", "d,v,t", dreg
,
3644 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0,
3650 if (imm_expr
.X_add_number
== 0)
3652 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0,
3658 as_warn ("Instruction %s: result is always true",
3660 macro_build ((char *) NULL
, &icnt
, &expr1
,
3661 mips_isa
< 3 ? "addiu" : "daddiu",
3662 "t,r,j", dreg
, 0, (int) BFD_RELOC_LO16
);
3665 if (imm_expr
.X_add_number
>= 0 && imm_expr
.X_add_number
< 0x10000)
3667 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "xori", "t,r,i",
3668 dreg
, sreg
, (int) BFD_RELOC_LO16
);
3671 else if (imm_expr
.X_add_number
> -0x8000 && imm_expr
.X_add_number
< 0)
3673 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
3674 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
3675 mips_isa
< 3 ? "addiu" : "daddiu",
3676 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
3681 load_register (&icnt
, AT
, &imm_expr
);
3682 macro_build ((char *) NULL
, &icnt
, NULL
, "xor", "d,v,t", dreg
,
3686 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0, dreg
);
3694 if (imm_expr
.X_add_number
> -0x8000 && imm_expr
.X_add_number
<= 0x8000)
3696 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
3697 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
3698 dbl
? "daddi" : "addi",
3699 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
3702 load_register (&icnt
, AT
, &imm_expr
);
3703 macro_build ((char *) NULL
, &icnt
, NULL
,
3704 dbl
? "dsub" : "sub",
3705 "d,v,t", dreg
, sreg
, AT
);
3711 if (imm_expr
.X_add_number
> -0x8000 && imm_expr
.X_add_number
<= 0x8000)
3713 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
3714 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
3715 dbl
? "daddiu" : "addiu",
3716 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
3719 load_register (&icnt
, AT
, &imm_expr
);
3720 macro_build ((char *) NULL
, &icnt
, NULL
,
3721 dbl
? "dsubu" : "subu",
3722 "d,v,t", dreg
, sreg
, AT
);
3743 load_register (&icnt
, AT
, &imm_expr
);
3744 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "s,t", sreg
, AT
);
3749 assert (mips_isa
< 2);
3750 sreg
= (ip
->insn_opcode
>> 11) & 0x1f; /* floating reg */
3751 dreg
= (ip
->insn_opcode
>> 06) & 0x1f; /* floating reg */
3754 * Is the double cfc1 instruction a bug in the mips assembler;
3755 * or is there a reason for it?
3757 mips_emit_delays ();
3759 mips_any_noreorder
= 1;
3760 macro_build ((char *) NULL
, &icnt
, NULL
, "cfc1", "t,G", treg
, 31);
3761 macro_build ((char *) NULL
, &icnt
, NULL
, "cfc1", "t,G", treg
, 31);
3762 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "");
3763 expr1
.X_add_number
= 3;
3764 macro_build ((char *) NULL
, &icnt
, &expr1
, "ori", "t,r,i", AT
, treg
,
3765 (int) BFD_RELOC_LO16
);
3766 expr1
.X_add_number
= 2;
3767 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", AT
, AT
,
3768 (int) BFD_RELOC_LO16
);
3769 macro_build ((char *) NULL
, &icnt
, NULL
, "ctc1", "t,G", AT
, 31);
3770 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "");
3771 macro_build ((char *) NULL
, &icnt
, NULL
,
3772 mask
== M_TRUNCWD
? "cvt.w.d" : "cvt.w.s", "D,S", dreg
, sreg
);
3773 macro_build ((char *) NULL
, &icnt
, NULL
, "ctc1", "t,G", treg
, 31);
3774 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "");
3784 if (offset_expr
.X_add_number
>= 0x7fff)
3785 as_bad ("operand overflow");
3786 /* avoid load delay */
3787 if (byte_order
== LITTLE_ENDIAN
)
3788 offset_expr
.X_add_number
+= 1;
3789 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
3790 (int) BFD_RELOC_LO16
, breg
);
3791 if (byte_order
== LITTLE_ENDIAN
)
3792 offset_expr
.X_add_number
-= 1;
3794 offset_expr
.X_add_number
+= 1;
3795 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lbu", "t,o(b)", AT
,
3796 (int) BFD_RELOC_LO16
, breg
);
3797 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", treg
, treg
, 8);
3798 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", treg
, treg
, AT
);
3802 if (offset_expr
.X_add_number
>= 0x7ffd)
3803 as_bad ("operand overflow");
3804 if (byte_order
== LITTLE_ENDIAN
)
3805 offset_expr
.X_add_number
+= 3;
3806 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lwl", "t,o(b)", treg
,
3807 (int) BFD_RELOC_LO16
, breg
);
3808 if (byte_order
== LITTLE_ENDIAN
)
3809 offset_expr
.X_add_number
-= 3;
3811 offset_expr
.X_add_number
+= 3;
3812 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lwr", "t,o(b)", treg
,
3813 (int) BFD_RELOC_LO16
, breg
);
3819 load_address (&icnt
, AT
, &offset_expr
);
3820 if (mask
== M_ULW_A
)
3822 if (byte_order
== LITTLE_ENDIAN
)
3823 expr1
.X_add_number
= 3;
3825 expr1
.X_add_number
= 0;
3826 macro_build ((char *) NULL
, &icnt
, &expr1
, "lwl", "t,o(b)", treg
,
3827 (int) BFD_RELOC_LO16
, AT
);
3828 if (byte_order
== LITTLE_ENDIAN
)
3829 expr1
.X_add_number
= 0;
3831 expr1
.X_add_number
= 3;
3832 macro_build ((char *) NULL
, &icnt
, &expr1
, "lwr", "t,o(b)", treg
,
3833 (int) BFD_RELOC_LO16
, AT
);
3837 if (byte_order
== BIG_ENDIAN
)
3838 expr1
.X_add_number
= 0;
3839 macro_build ((char *) NULL
, &icnt
, &expr1
,
3840 mask
== M_ULH_A
? "lb" : "lbu", "t,o(b)", treg
,
3841 (int) BFD_RELOC_LO16
, AT
);
3842 if (byte_order
== BIG_ENDIAN
)
3843 expr1
.X_add_number
= 1;
3845 expr1
.X_add_number
= 0;
3846 macro_build ((char *) NULL
, &icnt
, &expr1
, "lbu", "t,o(b)", AT
,
3847 (int) BFD_RELOC_LO16
, AT
);
3848 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", treg
,
3850 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", treg
,
3856 if (offset_expr
.X_add_number
>= 0x7fff)
3857 as_bad ("operand overflow");
3858 if (byte_order
== BIG_ENDIAN
)
3859 offset_expr
.X_add_number
+= 1;
3860 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "sb", "t,o(b)", treg
,
3861 (int) BFD_RELOC_LO16
, breg
);
3862 macro_build ((char *) NULL
, &icnt
, NULL
, "srl", "d,w,<", AT
, treg
, 8);
3863 if (byte_order
== BIG_ENDIAN
)
3864 offset_expr
.X_add_number
-= 1;
3866 offset_expr
.X_add_number
+= 1;
3867 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "sb", "t,o(b)", AT
,
3868 (int) BFD_RELOC_LO16
, breg
);
3872 if (offset_expr
.X_add_number
>= 0x7ffd)
3873 as_bad ("operand overflow");
3874 if (byte_order
== LITTLE_ENDIAN
)
3875 offset_expr
.X_add_number
+= 3;
3876 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "swl", "t,o(b)", treg
,
3877 (int) BFD_RELOC_LO16
, breg
);
3878 if (byte_order
== LITTLE_ENDIAN
)
3879 offset_expr
.X_add_number
-= 3;
3881 offset_expr
.X_add_number
+= 3;
3882 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "swr", "t,o(b)", treg
,
3883 (int) BFD_RELOC_LO16
, breg
);
3888 load_address (&icnt
, AT
, &offset_expr
);
3889 if (mask
== M_USW_A
)
3891 if (byte_order
== LITTLE_ENDIAN
)
3892 expr1
.X_add_number
= 3;
3894 expr1
.X_add_number
= 0;
3895 macro_build ((char *) NULL
, &icnt
, &expr1
, "swl", "t,o(b)", treg
,
3896 (int) BFD_RELOC_LO16
, AT
);
3897 if (byte_order
== LITTLE_ENDIAN
)
3898 expr1
.X_add_number
= 0;
3900 expr1
.X_add_number
= 3;
3901 macro_build ((char *) NULL
, &icnt
, &expr1
, "swr", "t,o(b)", treg
,
3902 (int) BFD_RELOC_LO16
, AT
);
3906 if (byte_order
== LITTLE_ENDIAN
)
3907 expr1
.X_add_number
= 0;
3908 macro_build ((char *) NULL
, &icnt
, &expr1
, "sb", "t,o(b)", treg
,
3909 (int) BFD_RELOC_LO16
, AT
);
3910 macro_build ((char *) NULL
, &icnt
, NULL
, "srl", "d,w,<", treg
,
3912 if (byte_order
== LITTLE_ENDIAN
)
3913 expr1
.X_add_number
= 1;
3915 expr1
.X_add_number
= 0;
3916 macro_build ((char *) NULL
, &icnt
, &expr1
, "sb", "t,o(b)", treg
,
3917 (int) BFD_RELOC_LO16
, AT
);
3918 if (byte_order
== LITTLE_ENDIAN
)
3919 expr1
.X_add_number
= 0;
3921 expr1
.X_add_number
= 1;
3922 macro_build ((char *) NULL
, &icnt
, &expr1
, "lbu", "t,o(b)", AT
,
3923 (int) BFD_RELOC_LO16
, AT
);
3924 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", treg
,
3926 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", treg
,
3932 as_bad ("Macro %s not implemented yet", ip
->insn_mo
->name
);
3936 as_warn ("Macro used $at after \".set noat\"");
3941 This routine assembles an instruction into its binary format. As a side
3942 effect it sets one of the global variables imm_reloc or offset_reloc to the
3943 type of relocation to do if one of the operands is an address expression.
3948 struct mips_cl_insn
*ip
;
3953 struct mips_opcode
*insn
;
3956 unsigned int lastregno
= 0;
3961 for (s
= str
; islower (*s
) || (*s
>= '0' && *s
<= '3') || *s
== '.'; ++s
)
3973 as_warn ("Unknown opcode: `%s'", str
);
3976 if ((insn
= (struct mips_opcode
*) hash_find (op_hash
, str
)) == NULL
)
3978 as_warn ("`%s' not in hash table.", str
);
3979 insn_error
= "ERROR: Unrecognized opcode";
3987 assert (strcmp (insn
->name
, str
) == 0);
3989 if (insn
->pinfo
== INSN_MACRO
)
3990 insn_isa
= insn
->match
;
3991 else if (insn
->pinfo
& INSN_ISA2
)
3993 else if (insn
->pinfo
& INSN_ISA3
)
3998 if (insn_isa
> mips_isa
)
4000 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
]
4001 && strcmp (insn
->name
, insn
[1].name
) == 0)
4006 as_warn ("Instruction not supported on this processor");
4010 ip
->insn_opcode
= insn
->match
;
4011 for (args
= insn
->args
;; ++args
)
4017 case '\0': /* end of args */
4030 ip
->insn_opcode
|= lastregno
<< 21;
4035 ip
->insn_opcode
|= lastregno
<< 16;
4039 ip
->insn_opcode
|= lastregno
<< 11;
4045 /* handle optional base register.
4046 Either the base register is omitted or
4047 we must have a left paren. */
4048 /* this is dependent on the next operand specifier
4049 is a 'b' for base register */
4050 assert (args
[1] == 'b');
4054 case ')': /* these must match exactly */
4059 case '<': /* must be at least one digit */
4061 * According to the manual, if the shift amount is greater
4062 * than 31 or less than 0 the the shift amount should be
4063 * mod 32. In reality the mips assembler issues an error.
4064 * We issue a warning and mask out all but the low 5 bits.
4066 my_getExpression (&imm_expr
, s
);
4067 check_absolute_expr (ip
, &imm_expr
);
4068 if ((unsigned long) imm_expr
.X_add_number
> 31)
4070 as_warn ("Improper shift amount (%ld)",
4071 (long) imm_expr
.X_add_number
);
4072 imm_expr
.X_add_number
= imm_expr
.X_add_number
& 0x1f;
4074 ip
->insn_opcode
|= imm_expr
.X_add_number
<< 6;
4075 imm_expr
.X_op
= O_absent
;
4079 case '>': /* shift amount minus 32 */
4080 my_getExpression (&imm_expr
, s
);
4081 check_absolute_expr (ip
, &imm_expr
);
4082 if ((unsigned long) imm_expr
.X_add_number
< 32
4083 || (unsigned long) imm_expr
.X_add_number
> 63)
4085 ip
->insn_opcode
|= (imm_expr
.X_add_number
- 32) << 6;
4086 imm_expr
.X_op
= O_absent
;
4090 case 'k': /* cache code */
4091 my_getExpression (&imm_expr
, s
);
4092 check_absolute_expr (ip
, &imm_expr
);
4093 if ((unsigned long) imm_expr
.X_add_number
> 31)
4095 as_warn ("Invalid cahce opcode (%lu)",
4096 (unsigned long) imm_expr
.X_add_number
);
4097 imm_expr
.X_add_number
&= 0x1f;
4099 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_CACHE
;
4100 imm_expr
.X_op
= O_absent
;
4104 case 'c': /* break code */
4105 my_getExpression (&imm_expr
, s
);
4106 check_absolute_expr (ip
, &imm_expr
);
4107 if ((unsigned) imm_expr
.X_add_number
> 1023)
4108 as_warn ("Illegal break code (%ld)",
4109 (long) imm_expr
.X_add_number
);
4110 ip
->insn_opcode
|= imm_expr
.X_add_number
<< 16;
4111 imm_expr
.X_op
= O_absent
;
4115 case 'B': /* syscall code */
4116 my_getExpression (&imm_expr
, s
);
4117 check_absolute_expr (ip
, &imm_expr
);
4118 if ((unsigned) imm_expr
.X_add_number
> 0xfffff)
4119 as_warn ("Illegal syscall code (%ld)",
4120 (long) imm_expr
.X_add_number
);
4121 ip
->insn_opcode
|= imm_expr
.X_add_number
<< 6;
4122 imm_expr
.X_op
= O_absent
;
4126 case 'C': /* Coprocessor code */
4127 my_getExpression (&imm_expr
, s
);
4128 check_absolute_expr (ip
, &imm_expr
);
4129 if ((unsigned long) imm_expr
.X_add_number
>= (1<<25))
4131 as_warn ("Coproccesor code > 25 bits (%ld)",
4132 (long) imm_expr
.X_add_number
);
4133 imm_expr
.X_add_number
&= ((1<<25) - 1);
4135 ip
->insn_opcode
|= imm_expr
.X_add_number
;
4136 imm_expr
.X_op
= O_absent
;
4140 case 'b': /* base register */
4141 case 'd': /* destination register */
4142 case 's': /* source register */
4143 case 't': /* target register */
4144 case 'r': /* both target and source */
4145 case 'v': /* both dest and source */
4146 case 'w': /* both dest and target */
4147 case 'E': /* coprocessor target register */
4148 case 'G': /* coprocessor destination register */
4149 case 'x': /* ignore register name */
4150 case 'z': /* must be zero register */
4164 while (isdigit (*s
));
4166 as_bad ("Invalid register number (%d)", regno
);
4168 else if (*args
== 'E' || *args
== 'G')
4172 if (s
[1] == 'f' && s
[2] == 'p')
4177 else if (s
[1] == 's' && s
[2] == 'p')
4182 else if (s
[1] == 'g' && s
[2] == 'p')
4187 else if (s
[1] == 'a' && s
[2] == 't')
4195 if (regno
== AT
&& ! mips_noat
)
4196 as_warn ("Used $at without \".set noat\"");
4202 if (c
== 'r' || c
== 'v' || c
== 'w')
4209 /* 'z' only matches $0. */
4210 if (c
== 'z' && regno
!= 0)
4218 ip
->insn_opcode
|= regno
<< 21;
4222 ip
->insn_opcode
|= regno
<< 11;
4227 ip
->insn_opcode
|= regno
<< 16;
4230 /* This case exists because on the r3000 trunc
4231 expands into a macro which requires a gp
4232 register. On the r6000 or r4000 it is
4233 assembled into a single instruction which
4234 ignores the register. Thus the insn version
4235 is MIPS_ISA2 and uses 'x', and the macro
4236 version is MIPS_ISA1 and uses 't'. */
4239 /* This case is for the div instruction, which
4240 acts differently if the destination argument
4241 is $0. This only matches $0, and is checked
4242 outside the switch. */
4253 ip
->insn_opcode
|= lastregno
<< 21;
4256 ip
->insn_opcode
|= lastregno
<< 16;
4261 case 'D': /* floating point destination register */
4262 case 'S': /* floating point source register */
4263 case 'T': /* floating point target register */
4267 if (s
[0] == '$' && s
[1] == 'f' && isdigit (s
[2]))
4277 while (isdigit (*s
));
4280 as_bad ("Invalid float register number (%d)", regno
);
4282 if ((regno
& 1) != 0
4284 && ! (strcmp (str
, "mtc1") == 0 ||
4285 strcmp (str
, "mfc1") == 0 ||
4286 strcmp (str
, "lwc1") == 0 ||
4287 strcmp (str
, "swc1") == 0))
4288 as_warn ("Float register should be even, was %d",
4296 if (c
== 'V' || c
== 'W')
4306 ip
->insn_opcode
|= regno
<< 6;
4310 ip
->insn_opcode
|= regno
<< 11;
4314 ip
->insn_opcode
|= regno
<< 16;
4322 ip
->insn_opcode
|= lastregno
<< 11;
4325 ip
->insn_opcode
|= lastregno
<< 16;
4331 my_getExpression (&imm_expr
, s
);
4332 check_absolute_expr (ip
, &imm_expr
);
4337 my_getExpression (&offset_expr
, s
);
4338 imm_reloc
= BFD_RELOC_32
;
4350 unsigned char temp
[8];
4352 unsigned int length
;
4357 /* These only appear as the last operand in an
4358 instruction, and every instruction that accepts
4359 them in any variant accepts them in all variants.
4360 This means we don't have to worry about backing out
4361 any changes if the instruction does not match.
4363 The difference between them is the size of the
4364 floating point constant and where it goes. For 'F'
4365 and 'L' the constant is 64 bits; for 'f' and 'l' it
4366 is 32 bits. Where the constant is placed is based
4367 on how the MIPS assembler does things:
4370 f -- immediate value
4373 When generating SVR4 PIC code, we do not use the
4374 .lit8 or .lit4 sections at all, in order to
4375 reserve the entire global offset table. When
4376 generating embedded PIC code, we use the .lit8
4377 section but not the .lit4 section (we can do .lit4
4378 inline easily; we need to put .lit8 somewhere in
4379 the data segment, and using .lit8 permits the
4380 linker to eventually combine identical .lit8
4383 f64
= *args
== 'F' || *args
== 'L';
4385 save_in
= input_line_pointer
;
4386 input_line_pointer
= s
;
4387 err
= md_atof (f64
? 'd' : 'f', (char *) temp
, &len
);
4389 s
= input_line_pointer
;
4390 input_line_pointer
= save_in
;
4391 if (err
!= NULL
&& *err
!= '\0')
4393 as_bad ("Bad floating point constant: %s", err
);
4394 memset (temp
, '\0', sizeof temp
);
4395 length
= f64
? 8 : 4;
4398 assert (length
== (f64
? 8 : 4));
4401 || (mips_pic
!= NO_PIC
&& *args
== 'l'))
4403 imm_expr
.X_op
= O_constant
;
4404 if (byte_order
== LITTLE_ENDIAN
)
4405 imm_expr
.X_add_number
=
4406 (((((((int) temp
[3] << 8)
4411 imm_expr
.X_add_number
=
4412 (((((((int) temp
[0] << 8)
4419 const char *newname
;
4422 /* Switch to the right section. */
4424 subseg
= now_subseg
;
4427 default: /* unused default case avoids warnings. */
4429 newname
= (mips_pic
!= SVR4_PIC
? ".lit8" : ".rdata");
4435 assert (mips_pic
== NO_PIC
);
4439 new_seg
= subseg_new (newname
, (subsegT
) 0);
4441 bfd_set_section_alignment (stdoutput
, new_seg
, 4);
4444 as_bad ("Can't use floating point insn in this section");
4446 /* Set the argument to the current address in the
4448 offset_expr
.X_op
= O_symbol
;
4449 offset_expr
.X_add_symbol
=
4450 symbol_new ("L0\001", now_seg
,
4451 (valueT
) frag_now_fix (), frag_now
);
4452 offset_expr
.X_add_number
= 0;
4454 /* Put the floating point number into the section. */
4455 p
= frag_more ((int) length
);
4456 memcpy (p
, temp
, length
);
4458 /* Switch back to the original section. */
4459 subseg_set (seg
, subseg
);
4464 case 'i': /* 16 bit unsigned immediate */
4465 case 'j': /* 16 bit signed immediate */
4466 imm_reloc
= BFD_RELOC_LO16
;
4467 c
= my_getSmallExpression (&imm_expr
, s
);
4472 if (imm_expr
.X_op
== O_constant
)
4473 imm_expr
.X_add_number
=
4474 (imm_expr
.X_add_number
>> 16) & 0xffff;
4476 imm_reloc
= BFD_RELOC_HI16_S
;
4478 imm_reloc
= BFD_RELOC_HI16
;
4482 check_absolute_expr (ip
, &imm_expr
);
4485 if (imm_expr
.X_add_number
< 0
4486 || imm_expr
.X_add_number
>= 0x10000)
4488 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
4489 !strcmp (insn
->name
, insn
[1].name
))
4491 as_bad ("16 bit expression not in range 0..65535");
4499 /* The upper bound should be 0x8000, but
4500 unfortunately the MIPS assembler accepts numbers
4501 from 0x8000 to 0xffff and sign extends them, and
4502 we want to be compatible. We only permit this
4503 extended range for an instruction which does not
4504 provide any further alternates, since those
4505 alternates may handle other cases. People should
4506 use the numbers they mean, rather than relying on
4507 a mysterious sign extension. */
4508 more
= (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
4509 strcmp (insn
->name
, insn
[1].name
) == 0);
4514 if (imm_expr
.X_add_number
< -0x8000 ||
4515 imm_expr
.X_add_number
>= max
)
4519 as_bad ("16 bit expression not in range -32768..32767");
4525 case 'o': /* 16 bit offset */
4526 c
= my_getSmallExpression (&offset_expr
, s
);
4528 * If this value won't fit into a 16 bit offset, then
4529 * go find a macro that will generate the 32 bit offset
4532 if (offset_expr
.X_op
!= O_constant
4533 || offset_expr
.X_add_number
>= 0x8000
4534 || offset_expr
.X_add_number
< -0x8000)
4537 offset_reloc
= BFD_RELOC_LO16
;
4538 if (c
== 'h' || c
== 'H')
4540 assert (offset_expr
.X_op
== O_constant
);
4541 offset_expr
.X_add_number
=
4542 (offset_expr
.X_add_number
>> 16) & 0xffff;
4547 case 'p': /* pc relative offset */
4548 offset_reloc
= BFD_RELOC_16_PCREL_S2
;
4549 my_getExpression (&offset_expr
, s
);
4553 case 'u': /* upper 16 bits */
4554 c
= my_getSmallExpression (&imm_expr
, s
);
4555 if (imm_expr
.X_op
!= O_constant
4556 || imm_expr
.X_add_number
< 0
4557 || imm_expr
.X_add_number
>= 0x10000)
4558 as_bad ("lui expression not in range 0..65535");
4559 imm_reloc
= BFD_RELOC_LO16
;
4564 if (imm_expr
.X_op
== O_constant
)
4565 imm_expr
.X_add_number
=
4566 (imm_expr
.X_add_number
>> 16) & 0xffff;
4568 imm_reloc
= BFD_RELOC_HI16_S
;
4570 imm_reloc
= BFD_RELOC_HI16
;
4576 case 'a': /* 26 bit address */
4577 my_getExpression (&offset_expr
, s
);
4579 offset_reloc
= BFD_RELOC_MIPS_JMP
;
4583 fprintf (stderr
, "bad char = '%c'\n", *args
);
4588 /* Args don't match. */
4589 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
4590 !strcmp (insn
->name
, insn
[1].name
))
4596 insn_error
= "ERROR: Illegal operands";
4605 my_getSmallExpression (ep
, str
)
4616 ((str
[1] == 'h' && str
[2] == 'i')
4617 || (str
[1] == 'H' && str
[2] == 'I')
4618 || (str
[1] == 'l' && str
[2] == 'o'))
4630 * A small expression may be followed by a base register.
4631 * Scan to the end of this operand, and then back over a possible
4632 * base register. Then scan the small expression up to that
4633 * point. (Based on code in sparc.c...)
4635 for (sp
= str
; *sp
&& *sp
!= ','; sp
++)
4637 if (sp
- 4 >= str
&& sp
[-1] == RP
)
4639 if (isdigit (sp
[-2]))
4641 for (sp
-= 3; sp
>= str
&& isdigit (*sp
); sp
--)
4643 if (*sp
== '$' && sp
> str
&& sp
[-1] == LP
)
4649 else if (sp
- 5 >= str
4652 && ((sp
[-3] == 'f' && sp
[-2] == 'p')
4653 || (sp
[-3] == 's' && sp
[-2] == 'p')
4654 || (sp
[-3] == 'g' && sp
[-2] == 'p')
4655 || (sp
[-3] == 'a' && sp
[-2] == 't')))
4661 /* no expression means zero offset */
4664 /* %xx(reg) is an error */
4665 ep
->X_op
= O_absent
;
4670 ep
->X_op
= O_constant
;
4673 ep
->X_add_symbol
= NULL
;
4674 ep
->X_op_symbol
= NULL
;
4675 ep
->X_add_number
= 0;
4680 my_getExpression (ep
, str
);
4687 my_getExpression (ep
, str
);
4688 return c
; /* => %hi or %lo encountered */
4692 my_getExpression (ep
, str
)
4698 save_in
= input_line_pointer
;
4699 input_line_pointer
= str
;
4701 expr_end
= input_line_pointer
;
4702 input_line_pointer
= save_in
;
4705 /* Turn a string in input_line_pointer into a floating point constant
4706 of type type, and store the appropriate bytes in *litP. The number
4707 of LITTLENUMS emitted is stored in *sizeP . An error message is
4708 returned, or NULL on OK. */
4711 md_atof (type
, litP
, sizeP
)
4717 LITTLENUM_TYPE words
[4];
4733 return "bad call to md_atof";
4736 t
= atof_ieee (input_line_pointer
, type
, words
);
4738 input_line_pointer
= t
;
4742 if (byte_order
== LITTLE_ENDIAN
)
4744 for (i
= prec
- 1; i
>= 0; i
--)
4746 md_number_to_chars (litP
, (valueT
) words
[i
], 2);
4752 for (i
= 0; i
< prec
; i
++)
4754 md_number_to_chars (litP
, (valueT
) words
[i
], 2);
4763 md_number_to_chars (buf
, val
, n
)
4771 number_to_chars_littleendian (buf
, val
, n
);
4775 number_to_chars_bigendian (buf
, val
, n
);
4784 md_parse_option (argP
, cntP
, vecP
)
4789 /* Accept -nocpp but ignore it. */
4790 if (strcmp (*argP
, "nocpp") == 0)
4796 if (strcmp (*argP
, "EL") == 0
4797 || strcmp (*argP
, "EB") == 0)
4799 if ((*argP
)[1] == 'B')
4800 byte_order
= BIG_ENDIAN
;
4802 byte_order
= LITTLE_ENDIAN
;
4805 if ((*argP
)[1] == 'B')
4806 mips_target_format
= "a.out-mips-big";
4808 mips_target_format
= "a.out-mips-little";
4811 if ((*argP
)[1] == 'B')
4812 mips_target_format
= "ecoff-bigmips";
4814 mips_target_format
= "ecoff-littlemips";
4817 if ((*argP
)[1] == 'B')
4818 mips_target_format
= "elf32-bigmips";
4820 mips_target_format
= "elf32-littlemips";
4823 /* FIXME: This breaks -L -EL. */
4831 if ((*argP
)[1] == '0')
4840 if ((*argP
)[1] == '\0' || (*argP
)[1] == '2')
4845 if (strncmp (*argP
, "mips", 4) == 0)
4847 mips_isa
= atol (*argP
+ 4);
4850 else if (mips_isa
< 1 || mips_isa
> 3)
4852 as_bad ("-mips%d not supported", mips_isa
);
4859 if (strncmp (*argP
, "mcpu=", 5) == 0)
4863 /* Identify the processor type */
4865 if (strcmp (p
, "default") == 0
4866 || strcmp (p
, "DEFAULT") == 0)
4870 if (*p
== 'r' || *p
== 'R')
4877 if (strcmp (p
, "2000") == 0
4878 || strcmp (p
, "2k") == 0
4879 || strcmp (p
, "2K") == 0)
4884 if (strcmp (p
, "3000") == 0
4885 || strcmp (p
, "3k") == 0
4886 || strcmp (p
, "3K") == 0)
4891 if (strcmp (p
, "4000") == 0
4892 || strcmp (p
, "4k") == 0
4893 || strcmp (p
, "4K") == 0)
4898 if (strcmp (p
, "6000") == 0
4899 || strcmp (p
, "6k") == 0
4900 || strcmp (p
, "6K") == 0)
4907 as_bad ("bad value (%s) for -mcpu= switch", *argP
+ 5);
4916 /* Argument -membedded-pic means to use EMBEDDED_PIC. */
4917 if (strcmp (*argP
, "membedded-pic") == 0)
4919 mips_pic
= EMBEDDED_PIC
;
4925 /* When generating ELF code, we permit -KPIC and -call_shared to
4926 select SVR4_PIC, and -non_shared to select no PIC. This is
4927 intended to be compatible with Irix 5. */
4928 if (strcmp (*argP
, "KPIC") == 0
4929 || strcmp (*argP
, "call_shared") == 0)
4931 mips_pic
= SVR4_PIC
;
4932 if (g_switch_seen
&& g_switch_value
!= 0)
4933 as_warn ("-G may not be used with SVR4 PIC code");
4935 bfd_set_gp_size (stdoutput
, 0);
4939 else if (strcmp (*argP
, "non_shared") == 0)
4945 #endif /* OBJ_ELF */
4950 if (mips_pic
== SVR4_PIC
)
4951 as_warn ("-G may not be used with SVR4 PIC code");
4952 else if ((*argP
)[1] != '\0')
4953 g_switch_value
= atoi (*argP
+ 1);
4956 **vecP
= (char *) NULL
;
4959 g_switch_value
= atoi (**vecP
);
4962 as_warn ("Number expected after -G");
4969 return 1; /* pretend you parsed the character */
4972 /* Handle a long option name. */
4975 mips_parse_long_option (arg
)
4978 if (strcmp (arg
, "--trap") == 0
4979 || strcmp (arg
, "--no-break") == 0)
4984 else if (strcmp (arg
, "--no-trap") == 0
4985 || strcmp (arg
, "--break") == 0)
4995 md_pcrel_from (fixP
)
4998 /* return the address of the delay slot */
4999 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
5002 /* This is called by emit_expr via TC_CONS_FIX_NEW when creating a
5003 reloc for a cons. We could use the definition there, except that
5004 we want to handle 64 bit relocs specially. */
5007 cons_fix_new_mips (frag
, where
, nbytes
, exp
)
5010 unsigned int nbytes
;
5013 /* If we are assembling in 32 bit mode, turn an 8 byte reloc into a
5015 FIXME: There is no way to select anything but 32 bit mode right
5019 if (byte_order
== BIG_ENDIAN
)
5024 if (nbytes
!= 2 && nbytes
!= 4)
5025 as_bad ("Unsupported reloc size %d", nbytes
);
5027 fix_new_exp (frag_now
, where
, (int) nbytes
, exp
, 0,
5028 nbytes
== 2 ? BFD_RELOC_16
: BFD_RELOC_32
);
5032 md_apply_fix (fixP
, valueP
)
5039 assert (fixP
->fx_size
== 4);
5042 fixP
->fx_addnumber
= value
; /* Remember value for tc_gen_reloc */
5044 switch (fixP
->fx_r_type
)
5047 case BFD_RELOC_MIPS_JMP
:
5048 case BFD_RELOC_HI16
:
5049 case BFD_RELOC_HI16_S
:
5050 case BFD_RELOC_LO16
:
5051 case BFD_RELOC_MIPS_GPREL
:
5052 case BFD_RELOC_MIPS_LITERAL
:
5053 case BFD_RELOC_MIPS_CALL16
:
5054 case BFD_RELOC_MIPS_GOT16
:
5055 case BFD_RELOC_MIPS_GPREL32
:
5056 /* Nothing needed to do. The value comes from the reloc entry */
5059 case BFD_RELOC_16_PCREL_S2
:
5061 * We need to save the bits in the instruction since fixup_segment()
5062 * might be deleting the relocation entry (i.e., a branch within
5063 * the current segment).
5066 as_warn ("Branch to odd address (%lx)", value
);
5068 if ((value
& ~0xFFFF) && (value
& ~0xFFFF) != (-1 & ~0xFFFF))
5069 as_bad ("Relocation overflow");
5071 /* update old instruction data */
5072 buf
= (unsigned char *) (fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
);
5076 insn
= (buf
[3] << 24) | (buf
[2] << 16) | (buf
[1] << 8) | buf
[0];
5080 insn
= (buf
[0] << 24) | (buf
[1] << 16) | (buf
[2] << 8) | buf
[3];
5087 insn
|= value
& 0xFFFF;
5088 md_number_to_chars ((char *) buf
, (valueT
) insn
, 4);
5102 const struct mips_opcode
*p
;
5103 int treg
, sreg
, dreg
, shamt
;
5108 for (i
= 0; i
< NUMOPCODES
; ++i
)
5110 p
= &mips_opcodes
[i
];
5111 if (((oc
& p
->mask
) == p
->match
) && (p
->pinfo
!= INSN_MACRO
))
5113 printf ("%08lx %s\t", oc
, p
->name
);
5114 treg
= (oc
>> 16) & 0x1f;
5115 sreg
= (oc
>> 21) & 0x1f;
5116 dreg
= (oc
>> 11) & 0x1f;
5117 shamt
= (oc
>> 6) & 0x1f;
5119 for (args
= p
->args
;; ++args
)
5130 printf ("%c", *args
);
5134 assert (treg
== sreg
);
5135 printf ("$%d,$%d", treg
, sreg
);
5140 printf ("$%d", dreg
);
5145 printf ("$%d", treg
);
5149 printf ("0x%x", treg
);
5154 printf ("$%d", sreg
);
5158 printf ("0x%08lx", oc
& 0x1ffffff);
5170 printf ("$%d", shamt
);
5181 printf ("%08lx UNDEFINED\n", oc
);
5192 name
= input_line_pointer
;
5193 c
= get_symbol_end ();
5194 p
= (symbolS
*) symbol_find_or_make (name
);
5195 *input_line_pointer
= c
;
5199 /* Align the current frag to a given power of two. The MIPS assembler
5200 also automatically adjusts any preceding label. */
5203 mips_align (to
, fill
, label
)
5208 mips_emit_delays ();
5209 frag_align (to
, fill
);
5210 record_alignment (now_seg
, to
);
5213 assert (S_GET_SEGMENT (label
) == now_seg
);
5214 label
->sy_frag
= frag_now
;
5215 S_SET_VALUE (label
, (valueT
) frag_now_fix ());
5219 /* Align to a given power of two. .align 0 turns off the automatic
5220 alignment used by the data creating pseudo-ops. */
5227 register long temp_fill
;
5228 long max_alignment
= 15;
5232 o Note that the assembler pulls down any immediately preceeding label
5233 to the aligned address.
5234 o It's not documented but auto alignment is reinstated by
5235 a .align pseudo instruction.
5236 o Note also that after auto alignment is turned off the mips assembler
5237 issues an error on attempt to assemble an improperly aligned data item.
5242 temp
= get_absolute_expression ();
5243 if (temp
> max_alignment
)
5244 as_bad ("Alignment too large: %d. assumed.", temp
= max_alignment
);
5247 as_warn ("Alignment negative: 0 assumed.");
5250 if (*input_line_pointer
== ',')
5252 input_line_pointer
++;
5253 temp_fill
= get_absolute_expression ();
5260 mips_align (temp
, (int) temp_fill
, insn_label
);
5267 demand_empty_rest_of_line ();
5270 /* Handle .ascii and .asciiz. This just calls stringer and forgets
5271 that there was a previous instruction. */
5274 s_stringer (append_zero
)
5277 mips_emit_delays ();
5279 stringer (append_zero
);
5290 mips_emit_delays ();
5300 subseg_set (bss_section
, (subsegT
) get_absolute_expression ());
5301 demand_empty_rest_of_line ();
5306 subseg_new (".rdata", (subsegT
) get_absolute_expression ());
5307 demand_empty_rest_of_line ();
5309 #else /* ! defined (OBJ_ECOFF) */
5311 seg
= subseg_new (".rodata", (subsegT
) get_absolute_expression ());
5312 bfd_set_section_flags (stdoutput
, seg
,
5318 bfd_set_section_alignment (stdoutput
, seg
, 4);
5319 demand_empty_rest_of_line ();
5321 #else /* ! defined (OBJ_ELF) */
5324 #endif /* ! defined (OBJ_ELF) */
5325 #endif /* ! defined (OBJ_ECOFF) */
5329 seg
= subseg_new (".sdata", (subsegT
) get_absolute_expression ());
5331 bfd_set_section_flags (stdoutput
, seg
,
5332 SEC_ALLOC
| SEC_LOAD
| SEC_RELOC
| SEC_DATA
);
5333 bfd_set_section_alignment (stdoutput
, seg
, 4);
5335 demand_empty_rest_of_line ();
5337 #else /* ! defined (GPOPT) */
5338 as_bad ("Global pointers not supported; recompile -G 0");
5339 demand_empty_rest_of_line ();
5341 #endif /* ! defined (GPOPT) */
5354 mips_emit_delays ();
5355 if (log_size
> 0 && auto_align
)
5356 mips_align (log_size
, 0, label
);
5358 cons (1 << log_size
);
5365 as_fatal ("Encountered `.err', aborting assembly");
5375 symbolP
= get_symbol ();
5376 if (*input_line_pointer
== ',')
5377 input_line_pointer
++;
5378 size
= get_absolute_expression ();
5379 S_SET_EXTERNAL (symbolP
);
5381 #ifdef ECOFF_DEBUGGING
5382 symbolP
->ecoff_extern_size
= size
;
5394 mips_emit_delays ();
5398 mips_align (3, 0, label
);
5400 mips_align (2, 0, label
);
5414 opt
= input_line_pointer
;
5415 c
= get_symbol_end ();
5419 /* FIXME: What does this mean? */
5421 else if (strncmp (opt
, "pic", 3) == 0)
5429 mips_pic
= SVR4_PIC
;
5431 as_bad (".option pic%d not supported", i
);
5433 if (mips_pic
== SVR4_PIC
)
5435 if (g_switch_seen
&& g_switch_value
!= 0)
5436 as_warn ("-G may not be used with SVR4 PIC code");
5438 bfd_set_gp_size (stdoutput
, 0);
5442 as_warn ("Unrecognized option \"%s\"", opt
);
5444 *input_line_pointer
= c
;
5445 demand_empty_rest_of_line ();
5452 char *name
= input_line_pointer
, ch
;
5454 while (!is_end_of_line
[(unsigned char) *input_line_pointer
])
5455 input_line_pointer
++;
5456 ch
= *input_line_pointer
;
5457 *input_line_pointer
= '\0';
5459 if (strcmp (name
, "reorder") == 0)
5463 prev_insn_unreordered
= 1;
5464 prev_prev_insn_unreordered
= 1;
5468 else if (strcmp (name
, "noreorder") == 0)
5470 mips_emit_delays ();
5472 mips_any_noreorder
= 1;
5474 else if (strcmp (name
, "at") == 0)
5478 else if (strcmp (name
, "noat") == 0)
5482 else if (strcmp (name
, "macro") == 0)
5484 mips_warn_about_macros
= 0;
5486 else if (strcmp (name
, "nomacro") == 0)
5488 if (mips_noreorder
== 0)
5489 as_bad ("`noreorder' must be set before `nomacro'");
5490 mips_warn_about_macros
= 1;
5492 else if (strcmp (name
, "move") == 0 || strcmp (name
, "novolatile") == 0)
5496 else if (strcmp (name
, "nomove") == 0 || strcmp (name
, "volatile") == 0)
5500 else if (strcmp (name
, "bopt") == 0)
5504 else if (strcmp (name
, "nobopt") == 0)
5508 else if (strncmp (name
, "mips", 4) == 0)
5512 /* Permit the user to change the ISA on the fly. Needless to
5513 say, misuse can cause serious problems. */
5514 isa
= atoi (name
+ 4);
5516 mips_isa
= file_mips_isa
;
5517 else if (isa
< 1 || isa
> 3)
5518 as_bad ("unknown ISA level");
5524 as_warn ("Tried to set unrecognized symbol: %s\n", name
);
5526 *input_line_pointer
= ch
;
5527 demand_empty_rest_of_line ();
5530 /* The same as the usual .space directive, except that we have to
5531 forget about any previous instruction. */
5534 s_mips_space (param
)
5537 mips_emit_delays ();
5542 /* Handle the .abicalls pseudo-op. I believe this is equivalent to
5543 .option pic2. It means to generate SVR4 PIC calls. */
5549 mips_pic
= SVR4_PIC
;
5550 if (g_switch_seen
&& g_switch_value
!= 0)
5551 as_warn ("-G may not be used with SVR4 PIC code");
5553 bfd_set_gp_size (stdoutput
, 0);
5554 demand_empty_rest_of_line ();
5557 /* Handle the .cpload pseudo-op. This is used when generating SVR4
5558 PIC code. It sets the $gp register for the function based on the
5559 function address, which is in the register named in the argument.
5560 This uses a relocation against _gp_disp, which is handled specially
5561 by the linker. The result is:
5562 lui $gp,%hi(_gp_disp)
5563 addiu $gp,$gp,%lo(_gp_disp)
5564 addu $gp,$gp,.cpload argument
5565 The .cpload argument is normally $25 == $t9. */
5574 /* If we are not generating SVR4 PIC code, .cpload is ignored. */
5575 if (mips_pic
!= SVR4_PIC
)
5581 /* .cpload should be a in .set noreorder section. */
5582 if (mips_noreorder
== 0)
5583 as_warn (".cpload not in noreorder section");
5586 ex
.X_add_symbol
= symbol_find_or_make ("_gp_disp");
5587 ex
.X_op_symbol
= NULL
;
5588 ex
.X_add_number
= 0;
5590 macro_build_lui ((char *) NULL
, &icnt
, &ex
, GP
);
5591 macro_build ((char *) NULL
, &icnt
, &ex
, "addiu", "t,r,j", GP
, GP
,
5592 (int) BFD_RELOC_LO16
);
5594 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "addu", "d,v,t",
5595 GP
, GP
, tc_get_register (0));
5597 demand_empty_rest_of_line ();
5600 /* Handle the .cprestore pseudo-op. This stores $gp into a given
5601 offset from $sp. The offset is remembered, and after making a PIC
5602 call $gp is restored from that location. */
5605 s_cprestore (ignore
)
5611 /* If we are not generating SVR4 PIC code, .cprestore is ignored. */
5612 if (mips_pic
!= SVR4_PIC
)
5618 mips_cprestore_offset
= get_absolute_expression ();
5620 ex
.X_op
= O_constant
;
5621 ex
.X_add_symbol
= NULL
;
5622 ex
.X_op_symbol
= NULL
;
5623 ex
.X_add_number
= mips_cprestore_offset
;
5625 macro_build ((char *) NULL
, &icnt
, &ex
,
5626 mips_isa
< 3 ? "sw" : "sd",
5627 "t,o(b)", GP
, (int) BFD_RELOC_LO16
, SP
);
5629 demand_empty_rest_of_line ();
5632 /* Handle the .gpword pseudo-op. This is used when generating PIC
5633 code. It generates a 32 bit GP relative reloc. */
5643 /* When not generating PIC code, this is treated as .word. */
5644 if (mips_pic
!= SVR4_PIC
)
5651 mips_emit_delays ();
5653 mips_align (2, 0, label
);
5658 if (ex
.X_op
!= O_symbol
|| ex
.X_add_number
!= 0)
5660 as_bad ("Unsupported use of .gpword");
5661 ignore_rest_of_line ();
5665 md_number_to_chars (p
, (valueT
) 0, 4);
5666 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 4, &ex
, 0,
5667 BFD_RELOC_MIPS_GPREL32
);
5669 demand_empty_rest_of_line ();
5672 /* Handle the .cpadd pseudo-op. This is used when dealing with switch
5673 tables in SVR4 PIC code. */
5682 /* This is ignored when not generating SVR4 PIC code. */
5683 if (mips_pic
!= SVR4_PIC
)
5689 /* Add $gp to the register named as an argument. */
5690 reg
= tc_get_register (0);
5691 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5692 mips_isa
< 3 ? "addu" : "daddu",
5693 "d,v,t", reg
, reg
, GP
);
5695 demand_empty_rest_of_line ();
5698 /* Parse a register string into a number. Called from the ECOFF code
5699 to parse .frame. The argument is non-zero if this is the frame
5700 register, so that we can record it in mips_frame_reg. */
5703 tc_get_register (frame
)
5709 if (*input_line_pointer
++ != '$')
5711 as_warn ("expected `$'");
5714 else if (isdigit ((unsigned char) *input_line_pointer
))
5716 reg
= get_absolute_expression ();
5717 if (reg
< 0 || reg
>= 32)
5719 as_warn ("Bad register number");
5725 if (strncmp (input_line_pointer
, "fp", 2) == 0)
5727 else if (strncmp (input_line_pointer
, "sp", 2) == 0)
5729 else if (strncmp (input_line_pointer
, "gp", 2) == 0)
5731 else if (strncmp (input_line_pointer
, "at", 2) == 0)
5735 as_warn ("Unrecognized register name");
5738 input_line_pointer
+= 2;
5741 mips_frame_reg
= reg
!= 0 ? reg
: SP
;
5746 md_section_align (seg
, addr
)
5750 int align
= bfd_get_section_alignment (stdoutput
, seg
);
5752 return ((addr
+ (1 << align
) - 1) & (-1 << align
));
5755 /* Estimate the size of a frag before relaxing. We are not really
5756 relaxing here, and the final size is encoded in the subtype
5761 md_estimate_size_before_relax (fragp
, segtype
)
5767 if (mips_pic
== NO_PIC
)
5770 const char *symname
;
5772 /* Find out whether this symbol can be referenced off the GP
5773 register. It can be if it is smaller than the -G size or if
5774 it is in the .sdata or .sbss section. Certain symbols can
5775 not be referenced off the GP, although it appears as though
5777 symname
= S_GET_NAME (fragp
->fr_symbol
);
5778 if (symname
!= (const char *) NULL
5779 && (strcmp (symname
, "eprol") == 0
5780 || strcmp (symname
, "etext") == 0
5781 || strcmp (symname
, "_gp") == 0
5782 || strcmp (symname
, "edata") == 0
5783 || strcmp (symname
, "_fbss") == 0
5784 || strcmp (symname
, "_fdata") == 0
5785 || strcmp (symname
, "_ftext") == 0
5786 || strcmp (symname
, "end") == 0
5787 || strcmp (symname
, "_gp_disp") == 0))
5789 else if (! S_IS_DEFINED (fragp
->fr_symbol
)
5790 && ((fragp
->fr_symbol
->ecoff_extern_size
!= 0
5791 && fragp
->fr_symbol
->ecoff_extern_size
<= g_switch_value
)
5792 || (S_GET_VALUE (fragp
->fr_symbol
) != 0
5793 && S_GET_VALUE (fragp
->fr_symbol
) <= g_switch_value
)))
5797 const char *segname
;
5799 segname
= segment_name (S_GET_SEGMENT (fragp
->fr_symbol
));
5800 assert (strcmp (segname
, ".lit8") != 0
5801 && strcmp (segname
, ".lit4") != 0);
5802 change
= (strcmp (segname
, ".sdata") != 0
5803 && strcmp (segname
, ".sbss") != 0);
5805 #else /* ! defined (GPOPT) */
5806 /* We are not optimizing for the GP register. */
5808 #endif /* ! defined (GPOPT) */
5810 else if (mips_pic
== SVR4_PIC
)
5812 asection
*symsec
= fragp
->fr_symbol
->bsym
->section
;
5814 /* This must duplicate the test in adjust_reloc_syms. */
5815 change
= (symsec
!= &bfd_und_section
5816 && symsec
!= &bfd_abs_section
5817 && ! bfd_is_com_section (symsec
));
5824 /* Record the offset to the first reloc in the fr_opcode field.
5825 This lets md_convert_frag and tc_gen_reloc know that the code
5826 must be expanded. */
5827 fragp
->fr_opcode
= (fragp
->fr_literal
5829 - RELAX_OLD (fragp
->fr_subtype
)
5830 + RELAX_RELOC1 (fragp
->fr_subtype
));
5831 /* FIXME: This really needs as_warn_where. */
5832 if (RELAX_WARN (fragp
->fr_subtype
))
5833 as_warn ("AT used after \".set noat\" or macro used after \".set nomacro\"");
5839 return RELAX_NEW (fragp
->fr_subtype
) - RELAX_OLD (fragp
->fr_subtype
);
5842 /* Translate internal representation of relocation info to BFD target
5846 tc_gen_reloc (section
, fixp
)
5850 static arelent
*retval
[4];
5853 reloc
= retval
[0] = (arelent
*) xmalloc (sizeof (arelent
));
5856 reloc
->sym_ptr_ptr
= &fixp
->fx_addsy
->bsym
;
5857 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
5858 if (fixp
->fx_pcrel
== 0)
5859 reloc
->addend
= fixp
->fx_addnumber
;
5864 reloc
->addend
= -reloc
->address
;
5867 /* If this is a variant frag, we may need to adjust the existing
5868 reloc and generate a new one. */
5869 if (fixp
->fx_frag
->fr_opcode
!= NULL
5870 && (fixp
->fx_r_type
== BFD_RELOC_MIPS_GPREL
5871 || fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT16
5872 || fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL16
))
5876 /* If this is not the last reloc in this frag, then we have two
5877 GPREL relocs, both of which are being replaced. Let the
5878 second one handle all of them. */
5879 if (fixp
->fx_next
!= NULL
5880 && fixp
->fx_frag
== fixp
->fx_next
->fx_frag
)
5882 assert (fixp
->fx_r_type
== BFD_RELOC_MIPS_GPREL
5883 && fixp
->fx_next
->fx_r_type
== BFD_RELOC_MIPS_GPREL
);
5888 fixp
->fx_where
= fixp
->fx_frag
->fr_opcode
- fixp
->fx_frag
->fr_literal
;
5889 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
5890 reloc2
= retval
[1] = (arelent
*) xmalloc (sizeof (arelent
));
5892 reloc2
->sym_ptr_ptr
= &fixp
->fx_addsy
->bsym
;
5893 reloc2
->address
= (reloc
->address
5894 + (RELAX_RELOC2 (fixp
->fx_frag
->fr_subtype
)
5895 - RELAX_RELOC1 (fixp
->fx_frag
->fr_subtype
)));
5896 reloc2
->addend
= fixp
->fx_addnumber
;
5897 reloc2
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_LO16
);
5898 assert (reloc2
->howto
!= NULL
);
5900 if (RELAX_RELOC3 (fixp
->fx_frag
->fr_subtype
))
5904 reloc3
= retval
[2] = (arelent
*) xmalloc (sizeof (arelent
));
5907 reloc3
->address
+= 4;
5910 if (mips_pic
== NO_PIC
)
5912 assert (fixp
->fx_r_type
== BFD_RELOC_MIPS_GPREL
);
5913 fixp
->fx_r_type
= BFD_RELOC_HI16_S
;
5915 else if (mips_pic
== SVR4_PIC
)
5917 if (fixp
->fx_r_type
!= BFD_RELOC_MIPS_GOT16
)
5919 assert (fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL16
);
5920 fixp
->fx_r_type
= BFD_RELOC_MIPS_GOT16
;
5927 /* To support a PC relative reloc when generating embedded PIC code
5928 for ECOFF, we use a Cygnus extension. We check for that here to
5929 make sure that we don't let such a reloc escape normally. */
5931 if (fixp
->fx_r_type
== BFD_RELOC_16_PCREL_S2
5932 && mips_pic
!= EMBEDDED_PIC
)
5933 reloc
->howto
= NULL
;
5936 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, fixp
->fx_r_type
);
5938 if (reloc
->howto
== NULL
)
5940 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
5941 "Can not represent relocation in this object file format");
5948 /* Convert a machine dependent frag. */
5951 md_convert_frag (abfd
, asec
, fragp
)
5959 if (fragp
->fr_opcode
== NULL
)
5962 old
= RELAX_OLD (fragp
->fr_subtype
);
5963 new = RELAX_NEW (fragp
->fr_subtype
);
5964 fixptr
= fragp
->fr_literal
+ fragp
->fr_fix
;
5967 memcpy (fixptr
- old
, fixptr
, new);
5969 fragp
->fr_fix
+= new - old
;
5972 /* This function is called whenever a label is defined. It is used
5973 when handling branch delays; if a branch has a label, we assume we
5977 mips_define_label (sym
)
5985 /* Some special processing for a MIPS ELF file. */
5988 mips_elf_final_processing ()
5992 /* Write out the .reginfo section. */
5993 s
.ri_gprmask
= mips_gprmask
;
5994 s
.ri_cprmask
[0] = mips_cprmask
[0];
5995 s
.ri_cprmask
[1] = mips_cprmask
[1];
5996 s
.ri_cprmask
[2] = mips_cprmask
[2];
5997 s
.ri_cprmask
[3] = mips_cprmask
[3];
5998 /* The gp_value field is set by the MIPS ELF backend. */
6000 bfd_mips_elf32_swap_reginfo_out (stdoutput
, &s
,
6001 ((Elf32_External_RegInfo
*)
6002 mips_regmask_frag
));
6004 /* Set the MIPS ELF flag bits. FIXME: There should probably be some
6005 sort of BFD interface for this. */
6006 if (mips_any_noreorder
)
6007 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_NOREORDER
;
6008 if (mips_pic
!= NO_PIC
)
6009 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_PIC
;
6012 #endif /* OBJ_ELF */
6014 #ifndef ECOFF_DEBUGGING
6016 /* These functions should really be defined by the object file format,
6017 since they are related to debugging information. However, this
6018 code has to work for the a.out format, which does not define them,
6019 so we provide simple versions here. These don't actually generate
6020 any debugging information, but they do simple checking and someday
6021 somebody may make them useful. */
6025 struct loc
*loc_next
;
6026 unsigned long loc_fileno
;
6027 unsigned long loc_lineno
;
6028 unsigned long loc_offset
;
6029 unsigned short loc_delta
;
6030 unsigned short loc_count
;
6039 struct proc
*proc_next
;
6040 struct symbol
*proc_isym
;
6041 struct symbol
*proc_end
;
6042 unsigned long proc_reg_mask
;
6043 unsigned long proc_reg_offset
;
6044 unsigned long proc_fpreg_mask
;
6045 unsigned long proc_fpreg_offset
;
6046 unsigned long proc_frameoffset
;
6047 unsigned long proc_framereg
;
6048 unsigned long proc_pcreg
;
6050 struct file
*proc_file
;
6057 struct file
*file_next
;
6058 unsigned long file_fileno
;
6059 struct symbol
*file_symbol
;
6060 struct symbol
*file_end
;
6061 struct proc
*file_proc
;
6066 static struct obstack proc_frags
;
6067 static procS
*proc_lastP
;
6068 static procS
*proc_rootP
;
6069 static int numprocs
;
6074 obstack_begin (&proc_frags
, 0x2000);
6080 /* check for premature end, nesting errors, etc */
6081 if (proc_lastP
&& proc_lastP
->proc_end
== NULL
)
6082 as_warn ("missing `.end' at end of assembly");
6085 extern char hex_value
[];
6093 if (*input_line_pointer
== '-')
6095 ++input_line_pointer
;
6098 if (!isdigit (*input_line_pointer
))
6099 as_bad ("Expected simple number.");
6100 if (input_line_pointer
[0] == '0')
6102 if (input_line_pointer
[1] == 'x')
6104 input_line_pointer
+= 2;
6105 while (isxdigit (*input_line_pointer
))
6108 val
|= hex_value
[(int) *input_line_pointer
++];
6110 return negative
? -val
: val
;
6114 ++input_line_pointer
;
6115 while (isdigit (*input_line_pointer
))
6118 val
|= *input_line_pointer
++ - '0';
6120 return negative
? -val
: val
;
6123 if (!isdigit (*input_line_pointer
))
6125 printf (" *input_line_pointer == '%c' 0x%02x\n",
6126 *input_line_pointer
, *input_line_pointer
);
6127 as_warn ("Invalid number");
6130 while (isdigit (*input_line_pointer
))
6133 val
+= *input_line_pointer
++ - '0';
6135 return negative
? -val
: val
;
6138 /* The .file directive; just like the usual .file directive, but there
6139 is an initial number which is the ECOFF file index. */
6147 line
= get_number ();
6152 /* The .end directive. */
6160 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
6163 demand_empty_rest_of_line ();
6167 if (now_seg
!= text_section
)
6168 as_warn (".end not in text section");
6171 as_warn (".end and no .ent seen yet.");
6177 assert (S_GET_NAME (p
));
6178 if (strcmp (S_GET_NAME (p
), S_GET_NAME (proc_lastP
->proc_isym
)))
6179 as_warn (".end symbol does not match .ent symbol.");
6182 proc_lastP
->proc_end
= (symbolS
*) 1;
6185 /* The .aent and .ent directives. */
6195 symbolP
= get_symbol ();
6196 if (*input_line_pointer
== ',')
6197 input_line_pointer
++;
6199 if (isdigit (*input_line_pointer
) || *input_line_pointer
== '-')
6200 number
= get_number ();
6201 if (now_seg
!= text_section
)
6202 as_warn (".ent or .aent not in text section.");
6204 if (!aent
&& proc_lastP
&& proc_lastP
->proc_end
== NULL
)
6205 as_warn ("missing `.end'");
6209 procP
= (procS
*) obstack_alloc (&proc_frags
, sizeof (*procP
));
6210 procP
->proc_isym
= symbolP
;
6211 procP
->proc_reg_mask
= 0;
6212 procP
->proc_reg_offset
= 0;
6213 procP
->proc_fpreg_mask
= 0;
6214 procP
->proc_fpreg_offset
= 0;
6215 procP
->proc_frameoffset
= 0;
6216 procP
->proc_framereg
= 0;
6217 procP
->proc_pcreg
= 0;
6218 procP
->proc_end
= NULL
;
6219 procP
->proc_next
= NULL
;
6221 proc_lastP
->proc_next
= procP
;
6227 demand_empty_rest_of_line ();
6230 /* The .frame directive. */
6243 frame_reg
= tc_get_register (1);
6244 if (*input_line_pointer
== ',')
6245 input_line_pointer
++;
6246 frame_off
= get_absolute_expression ();
6247 if (*input_line_pointer
== ',')
6248 input_line_pointer
++;
6249 pcreg
= tc_get_register (0);
6252 assert (proc_rootP
);
6253 proc_rootP
->proc_framereg
= frame_reg
;
6254 proc_rootP
->proc_frameoffset
= frame_off
;
6255 proc_rootP
->proc_pcreg
= pcreg
;
6256 /* bob macho .frame */
6258 /* We don't have to write out a frame stab for unoptimized code. */
6259 if (!(frame_reg
== FP
&& frame_off
== 0))
6262 as_warn ("No .ent for .frame to use.");
6263 (void) sprintf (str
, "R%d;%d", frame_reg
, frame_off
);
6264 symP
= symbol_new (str
, N_VFP
, 0, frag_now
);
6265 S_SET_TYPE (symP
, N_RMASK
);
6266 S_SET_OTHER (symP
, 0);
6267 S_SET_DESC (symP
, 0);
6268 symP
->sy_forward
= proc_lastP
->proc_isym
;
6269 /* bob perhaps I should have used pseudo set */
6271 demand_empty_rest_of_line ();
6275 /* The .fmask and .mask directives. */
6282 char str
[100], *strP
;
6288 mask
= get_number ();
6289 if (*input_line_pointer
== ',')
6290 input_line_pointer
++;
6291 off
= get_absolute_expression ();
6293 /* bob only for coff */
6294 assert (proc_rootP
);
6295 if (reg_type
== 'F')
6297 proc_rootP
->proc_fpreg_mask
= mask
;
6298 proc_rootP
->proc_fpreg_offset
= off
;
6302 proc_rootP
->proc_reg_mask
= mask
;
6303 proc_rootP
->proc_reg_offset
= off
;
6306 /* bob macho .mask + .fmask */
6308 /* We don't have to write out a mask stab if no saved regs. */
6312 as_warn ("No .ent for .mask to use.");
6314 for (i
= 0; i
< 32; i
++)
6318 sprintf (strP
, "%c%d,", reg_type
, i
);
6319 strP
+= strlen (strP
);
6323 sprintf (strP
, ";%d,", off
);
6324 symP
= symbol_new (str
, N_RMASK
, 0, frag_now
);
6325 S_SET_TYPE (symP
, N_RMASK
);
6326 S_SET_OTHER (symP
, 0);
6327 S_SET_DESC (symP
, 0);
6328 symP
->sy_forward
= proc_lastP
->proc_isym
;
6329 /* bob perhaps I should have used pseudo set */
6334 /* The .loc directive. */
6345 assert (now_seg
== text_section
);
6347 lineno
= get_number ();
6348 addroff
= obstack_next_free (&frags
) - frag_now
->fr_literal
;
6350 symbolP
= symbol_new ("", N_SLINE
, addroff
, frag_now
);
6351 S_SET_TYPE (symbolP
, N_SLINE
);
6352 S_SET_OTHER (symbolP
, 0);
6353 S_SET_DESC (symbolP
, lineno
);
6354 symbolP
->sy_segment
= now_seg
;
6358 #endif /* ! defined (ECOFF_DEBUGGING) */