1 /* tc-mips.c -- assemble code for a MIPS chip.
2 Copyright (C) 1993, 1995, 1996 Free Software Foundation, Inc.
3 Contributed by the OSF and Ralph Campbell.
4 Written by Keith Knowles and Ralph Campbell, working independently.
5 Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus
8 This file is part of GAS.
10 GAS is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 2, or (at your option)
15 GAS is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with GAS; see the file COPYING. If not, write to the Free
22 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
28 #include "libiberty.h"
39 #include "opcode/mips.h"
42 /* Clean up namespace so we can include obj-elf.h too. */
43 static int mips_output_flavor () { return OUTPUT_FLAVOR
; }
44 #undef OBJ_PROCESS_STAB
50 #undef TARGET_SYMBOL_FIELDS
52 #undef obj_frob_symbol
54 #undef obj_sec_sym_ok_for_reloc
57 /* Fix any of them that we actually care about. */
59 #define OUTPUT_FLAVOR mips_output_flavor()
66 #ifndef ECOFF_DEBUGGING
67 #define NO_ECOFF_DEBUGGING
68 #define ECOFF_DEBUGGING 0
73 static char *mips_regmask_frag
;
76 #define PIC_CALL_REG 25
84 extern int target_big_endian
;
86 /* 1 is we should use the 64 bit MIPS ELF ABI, 0 if we should use the
87 32 bit ABI. This has no meaning for ECOFF. */
90 /* The default target format to use. */
94 switch (OUTPUT_FLAVOR
)
96 case bfd_target_aout_flavour
:
97 return target_big_endian
? "a.out-mips-big" : "a.out-mips-little";
98 case bfd_target_ecoff_flavour
:
99 return target_big_endian
? "ecoff-bigmips" : "ecoff-littlemips";
100 case bfd_target_elf_flavour
:
101 return (target_big_endian
102 ? (mips_64
? "elf64-bigmips" : "elf32-bigmips")
103 : (mips_64
? "elf64-littlemips" : "elf32-littlemips"));
109 /* The name of the readonly data section. */
110 #define RDATA_SECTION_NAME (OUTPUT_FLAVOR == bfd_target_aout_flavour \
112 : OUTPUT_FLAVOR == bfd_target_ecoff_flavour \
114 : OUTPUT_FLAVOR == bfd_target_elf_flavour \
118 /* These variables are filled in with the masks of registers used.
119 The object format code reads them and puts them in the appropriate
121 unsigned long mips_gprmask
;
122 unsigned long mips_cprmask
[4];
124 /* MIPS ISA (Instruction Set Architecture) level (may be changed
125 temporarily using .set mipsN). */
126 static int mips_isa
= -1;
128 /* MIPS ISA we are using for this output file. */
129 static int file_mips_isa
;
131 /* The CPU type as a number: 2000, 3000, 4000, 4400, etc. */
132 static int mips_cpu
= -1;
134 /* Whether the 4650 instructions (mad/madu) are permitted. */
135 static int mips_4650
= -1;
137 /* Whether the 4010 instructions are permitted. */
138 static int mips_4010
= -1;
140 /* Whether the 4100 MADD16 and DMADD16 are permitted. */
141 static int mips_4100
= -1;
143 /* Whether the processor uses hardware interlocks, and thus does not
144 require nops to be inserted. */
145 static int interlocks
= -1;
147 /* MIPS PIC level. */
151 /* Do not generate PIC code. */
154 /* Generate PIC code as in Irix 4. This is not implemented, and I'm
155 not sure what it is supposed to do. */
158 /* Generate PIC code as in the SVR4 MIPS ABI. */
161 /* Generate PIC code without using a global offset table: the data
162 segment has a maximum size of 64K, all data references are off
163 the $gp register, and all text references are PC relative. This
164 is used on some embedded systems. */
168 static enum mips_pic_level mips_pic
;
170 /* 1 if we should generate 32 bit offsets from the GP register in
171 SVR4_PIC mode. Currently has no meaning in other modes. */
172 static int mips_big_got
;
174 /* 1 if trap instructions should used for overflow rather than break
176 static int mips_trap
;
178 static int mips_warn_about_macros
;
179 static int mips_noreorder
;
180 static int mips_any_noreorder
;
181 static int mips_nomove
;
182 static int mips_noat
;
183 static int mips_nobopt
;
185 /* The size of the small data section. */
186 static int g_switch_value
= 8;
187 /* Whether the -G option was used. */
188 static int g_switch_seen
= 0;
193 /* If we can determine in advance that GP optimization won't be
194 possible, we can skip the relaxation stuff that tries to produce
195 GP-relative references. This makes delay slot optimization work
198 This function can only provide a guess, but it seems to work for
199 gcc output. If it guesses wrong, the only loss should be in
200 efficiency; it shouldn't introduce any bugs.
202 I don't know if a fix is needed for the SVR4_PIC mode. I've only
203 fixed it for the non-PIC mode. KR 95/04/07 */
204 static int nopic_need_relax
PARAMS ((symbolS
*));
206 /* handle of the OPCODE hash table */
207 static struct hash_control
*op_hash
= NULL
;
209 /* This array holds the chars that always start a comment. If the
210 pre-processor is disabled, these aren't very useful */
211 const char comment_chars
[] = "#";
213 /* This array holds the chars that only start a comment at the beginning of
214 a line. If the line seems to have the form '# 123 filename'
215 .line and .file directives will appear in the pre-processed output */
216 /* Note that input_file.c hand checks for '#' at the beginning of the
217 first line of the input file. This is because the compiler outputs
218 #NO_APP at the beginning of its output. */
219 /* Also note that C style comments are always supported. */
220 const char line_comment_chars
[] = "#";
222 /* This array holds machine specific line separator characters. */
223 const char line_separator_chars
[] = "";
225 /* Chars that can be used to separate mant from exp in floating point nums */
226 const char EXP_CHARS
[] = "eE";
228 /* Chars that mean this number is a floating point constant */
231 const char FLT_CHARS
[] = "rRsSfFdDxXpP";
233 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
234 changed in read.c . Ideally it shouldn't have to know about it at all,
235 but nothing is ideal around here.
238 static char *insn_error
;
240 static int byte_order
;
242 static int auto_align
= 1;
244 /* Symbol labelling the current insn. */
245 static symbolS
*insn_label
;
247 /* When outputting SVR4 PIC code, the assembler needs to know the
248 offset in the stack frame from which to restore the $gp register.
249 This is set by the .cprestore pseudo-op, and saved in this
251 static offsetT mips_cprestore_offset
= -1;
253 /* This is the register which holds the stack frame, as set by the
254 .frame pseudo-op. This is needed to implement .cprestore. */
255 static int mips_frame_reg
= SP
;
257 /* To output NOP instructions correctly, we need to keep information
258 about the previous two instructions. */
260 /* Whether we are optimizing. The default value of 2 means to remove
261 unneeded NOPs and swap branch instructions when possible. A value
262 of 1 means to not swap branches. A value of 0 means to always
264 static int mips_optimize
= 2;
266 /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is
267 equivalent to seeing no -g option at all. */
268 static int mips_debug
= 0;
270 /* The previous instruction. */
271 static struct mips_cl_insn prev_insn
;
273 /* The instruction before prev_insn. */
274 static struct mips_cl_insn prev_prev_insn
;
276 /* If we don't want information for prev_insn or prev_prev_insn, we
277 point the insn_mo field at this dummy integer. */
278 static const struct mips_opcode dummy_opcode
= { 0 };
280 /* Non-zero if prev_insn is valid. */
281 static int prev_insn_valid
;
283 /* The frag for the previous instruction. */
284 static struct frag
*prev_insn_frag
;
286 /* The offset into prev_insn_frag for the previous instruction. */
287 static long prev_insn_where
;
289 /* The reloc for the previous instruction, if any. */
290 static fixS
*prev_insn_fixp
;
292 /* Non-zero if the previous instruction was in a delay slot. */
293 static int prev_insn_is_delay_slot
;
295 /* Non-zero if the previous instruction was in a .set noreorder. */
296 static int prev_insn_unreordered
;
298 /* Non-zero if the previous previous instruction was in a .set
300 static int prev_prev_insn_unreordered
;
302 /* For ECOFF and ELF, relocations against symbols are done in two
303 parts, with a HI relocation and a LO relocation. Each relocation
304 has only 16 bits of space to store an addend. This means that in
305 order for the linker to handle carries correctly, it must be able
306 to locate both the HI and the LO relocation. This means that the
307 relocations must appear in order in the relocation table.
309 In order to implement this, we keep track of each unmatched HI
310 relocation. We then sort them so that they immediately precede the
311 corresponding LO relocation. */
316 struct mips_hi_fixup
*next
;
319 /* The section this fixup is in. */
323 /* The list of unmatched HI relocs. */
325 static struct mips_hi_fixup
*mips_hi_fixup_list
;
327 /* Since the MIPS does not have multiple forms of PC relative
328 instructions, we do not have to do relaxing as is done on other
329 platforms. However, we do have to handle GP relative addressing
330 correctly, which turns out to be a similar problem.
332 Every macro that refers to a symbol can occur in (at least) two
333 forms, one with GP relative addressing and one without. For
334 example, loading a global variable into a register generally uses
335 a macro instruction like this:
337 If i can be addressed off the GP register (this is true if it is in
338 the .sbss or .sdata section, or if it is known to be smaller than
339 the -G argument) this will generate the following instruction:
341 This instruction will use a GPREL reloc. If i can not be addressed
342 off the GP register, the following instruction sequence will be used:
345 In this case the first instruction will have a HI16 reloc, and the
346 second reloc will have a LO16 reloc. Both relocs will be against
349 The issue here is that we may not know whether i is GP addressable
350 until after we see the instruction that uses it. Therefore, we
351 want to be able to choose the final instruction sequence only at
352 the end of the assembly. This is similar to the way other
353 platforms choose the size of a PC relative instruction only at the
356 When generating position independent code we do not use GP
357 addressing in quite the same way, but the issue still arises as
358 external symbols and local symbols must be handled differently.
360 We handle these issues by actually generating both possible
361 instruction sequences. The longer one is put in a frag_var with
362 type rs_machine_dependent. We encode what to do with the frag in
363 the subtype field. We encode (1) the number of existing bytes to
364 replace, (2) the number of new bytes to use, (3) the offset from
365 the start of the existing bytes to the first reloc we must generate
366 (that is, the offset is applied from the start of the existing
367 bytes after they are replaced by the new bytes, if any), (4) the
368 offset from the start of the existing bytes to the second reloc,
369 (5) whether a third reloc is needed (the third reloc is always four
370 bytes after the second reloc), and (6) whether to warn if this
371 variant is used (this is sometimes needed if .set nomacro or .set
372 noat is in effect). All these numbers are reasonably small.
374 Generating two instruction sequences must be handled carefully to
375 ensure that delay slots are handled correctly. Fortunately, there
376 are a limited number of cases. When the second instruction
377 sequence is generated, append_insn is directed to maintain the
378 existing delay slot information, so it continues to apply to any
379 code after the second instruction sequence. This means that the
380 second instruction sequence must not impose any requirements not
381 required by the first instruction sequence.
383 These variant frags are then handled in functions called by the
384 machine independent code. md_estimate_size_before_relax returns
385 the final size of the frag. md_convert_frag sets up the final form
386 of the frag. tc_gen_reloc adjust the first reloc and adds a second
388 #define RELAX_ENCODE(old, new, reloc1, reloc2, reloc3, warn) \
392 | (((reloc1) + 64) << 9) \
393 | (((reloc2) + 64) << 2) \
394 | ((reloc3) ? (1 << 1) : 0) \
396 #define RELAX_OLD(i) (((i) >> 24) & 0xff)
397 #define RELAX_NEW(i) (((i) >> 16) & 0xff)
398 #define RELAX_RELOC1(i) ((bfd_vma)(((i) >> 9) & 0x7f) - 64)
399 #define RELAX_RELOC2(i) ((bfd_vma)(((i) >> 2) & 0x7f) - 64)
400 #define RELAX_RELOC3(i) (((i) >> 1) & 1)
401 #define RELAX_WARN(i) ((i) & 1)
403 /* Prototypes for static functions. */
406 #define internalError() \
407 as_fatal ("internal Error, line %d, %s", __LINE__, __FILE__)
409 #define internalError() as_fatal ("MIPS internal Error");
412 static int insn_uses_reg
PARAMS ((struct mips_cl_insn
*ip
,
413 unsigned int reg
, int fpr
));
414 static int reg_needs_delay
PARAMS ((int));
415 static void append_insn
PARAMS ((char *place
,
416 struct mips_cl_insn
* ip
,
418 bfd_reloc_code_real_type r
,
420 static void mips_no_prev_insn
PARAMS ((void));
421 static void mips_emit_delays
PARAMS ((void));
423 static void macro_build
PARAMS ((char *place
, int *counter
, expressionS
* ep
,
424 const char *name
, const char *fmt
,
427 static void macro_build ();
429 static void macro_build_lui
PARAMS ((char *place
, int *counter
,
430 expressionS
* ep
, int regnum
));
431 static void set_at
PARAMS ((int *counter
, int reg
, int unsignedp
));
432 static void check_absolute_expr
PARAMS ((struct mips_cl_insn
* ip
,
434 static void load_register
PARAMS ((int *, int, expressionS
*, int));
435 static void load_address
PARAMS ((int *counter
, int reg
, expressionS
*ep
));
436 static void macro
PARAMS ((struct mips_cl_insn
* ip
));
437 #ifdef LOSING_COMPILER
438 static void macro2
PARAMS ((struct mips_cl_insn
* ip
));
440 static void mips_ip
PARAMS ((char *str
, struct mips_cl_insn
* ip
));
441 static int my_getSmallExpression
PARAMS ((expressionS
* ep
, char *str
));
442 static void my_getExpression
PARAMS ((expressionS
* ep
, char *str
));
443 static symbolS
*get_symbol
PARAMS ((void));
444 static void mips_align
PARAMS ((int to
, int fill
, symbolS
*label
));
445 static void s_align
PARAMS ((int));
446 static void s_change_sec
PARAMS ((int));
447 static void s_cons
PARAMS ((int));
448 static void s_float_cons
PARAMS ((int));
449 static void s_mips_globl
PARAMS ((int));
450 static void s_option
PARAMS ((int));
451 static void s_mipsset
PARAMS ((int));
452 static void s_abicalls
PARAMS ((int));
453 static void s_cpload
PARAMS ((int));
454 static void s_cprestore
PARAMS ((int));
455 static void s_gpword
PARAMS ((int));
456 static void s_cpadd
PARAMS ((int));
457 static void md_obj_begin
PARAMS ((void));
458 static void md_obj_end
PARAMS ((void));
459 static long get_number
PARAMS ((void));
460 static void s_ent
PARAMS ((int));
461 static void s_mipsend
PARAMS ((int));
462 static void s_file
PARAMS ((int));
466 The following pseudo-ops from the Kane and Heinrich MIPS book
467 should be defined here, but are currently unsupported: .alias,
468 .galive, .gjaldef, .gjrlive, .livereg, .noalias.
470 The following pseudo-ops from the Kane and Heinrich MIPS book are
471 specific to the type of debugging information being generated, and
472 should be defined by the object format: .aent, .begin, .bend,
473 .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp,
476 The following pseudo-ops from the Kane and Heinrich MIPS book are
477 not MIPS CPU specific, but are also not specific to the object file
478 format. This file is probably the best place to define them, but
479 they are not currently supported: .asm0, .endr, .lab, .repeat,
480 .struct, .weakext. */
482 static const pseudo_typeS mips_pseudo_table
[] =
484 /* MIPS specific pseudo-ops. */
485 {"option", s_option
, 0},
486 {"set", s_mipsset
, 0},
487 {"rdata", s_change_sec
, 'r'},
488 {"sdata", s_change_sec
, 's'},
489 {"livereg", s_ignore
, 0},
490 {"abicalls", s_abicalls
, 0},
491 {"cpload", s_cpload
, 0},
492 {"cprestore", s_cprestore
, 0},
493 {"gpword", s_gpword
, 0},
494 {"cpadd", s_cpadd
, 0},
496 /* Relatively generic pseudo-ops that happen to be used on MIPS
498 {"asciiz", stringer
, 1},
499 {"bss", s_change_sec
, 'b'},
502 {"dword", s_cons
, 3},
504 /* These pseudo-ops are defined in read.c, but must be overridden
505 here for one reason or another. */
506 {"align", s_align
, 0},
508 {"data", s_change_sec
, 'd'},
509 {"double", s_float_cons
, 'd'},
510 {"float", s_float_cons
, 'f'},
511 {"globl", s_mips_globl
, 0},
512 {"global", s_mips_globl
, 0},
513 {"hword", s_cons
, 1},
518 {"short", s_cons
, 1},
519 {"single", s_float_cons
, 'f'},
520 {"text", s_change_sec
, 't'},
525 static const pseudo_typeS mips_nonecoff_pseudo_table
[] = {
526 /* These pseudo-ops should be defined by the object file format.
527 However, a.out doesn't support them, so we have versions here. */
529 {"bgnb", s_ignore
, 0},
530 {"end", s_mipsend
, 0},
531 {"endb", s_ignore
, 0},
534 {"fmask", s_ignore
, 'F'},
535 {"frame", s_ignore
, 0},
536 {"loc", s_ignore
, 0},
537 {"mask", s_ignore
, 'R'},
538 {"verstamp", s_ignore
, 0},
542 extern void pop_insert
PARAMS ((const pseudo_typeS
*));
547 pop_insert (mips_pseudo_table
);
548 if (! ECOFF_DEBUGGING
)
549 pop_insert (mips_nonecoff_pseudo_table
);
552 static char *expr_end
;
554 /* Expressions which appear in instructions. These are set by
557 static expressionS imm_expr
;
558 static expressionS offset_expr
;
560 /* Relocs associated with imm_expr and offset_expr. */
562 static bfd_reloc_code_real_type imm_reloc
;
563 static bfd_reloc_code_real_type offset_reloc
;
565 /* This is set by mips_ip if imm_reloc is an unmatched HI16_S reloc. */
567 static boolean imm_unmatched_hi
;
570 * This function is called once, at assembler startup time. It should
571 * set up all the tables, etc. that the MD part of the assembler will need.
577 register const char *retval
= NULL
;
578 register unsigned int i
= 0;
586 if (strcmp (cpu
+ (sizeof TARGET_CPU
) - 3, "el") == 0)
588 a
= xmalloc (sizeof TARGET_CPU
);
589 strcpy (a
, TARGET_CPU
);
590 a
[(sizeof TARGET_CPU
) - 3] = '\0';
594 if (strcmp (cpu
, "mips") == 0)
600 else if (strcmp (cpu
, "r6000") == 0
601 || strcmp (cpu
, "mips2") == 0)
607 else if (strcmp (cpu
, "mips64") == 0
608 || strcmp (cpu
, "r4000") == 0
609 || strcmp (cpu
, "mips3") == 0)
615 else if (strcmp (cpu
, "r4400") == 0)
621 else if (strcmp (cpu
, "mips64orion") == 0
622 || strcmp (cpu
, "r4600") == 0)
628 else if (strcmp (cpu
, "r4650") == 0)
636 else if (strcmp (cpu
, "mips64vr4300") == 0)
642 else if (strcmp (cpu
, "mips64vr4100") == 0)
650 else if (strcmp (cpu
, "r4010") == 0)
658 else if (strcmp (cpu
, "r8000") == 0
659 || strcmp (cpu
, "mips4") == 0)
665 else if (strcmp (cpu
, "r10000") == 0)
691 if (mips_4650
|| mips_4010
|| mips_4100
)
696 if (mips_isa
< 2 && mips_trap
)
697 as_bad ("trap exception not supported at ISA 1");
702 ok
= bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, 3000);
705 ok
= bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, 6000);
708 ok
= bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, 4000);
711 ok
= bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, 8000);
715 as_warn ("Could not set architecture and machine");
717 file_mips_isa
= mips_isa
;
719 op_hash
= hash_new ();
721 for (i
= 0; i
< NUMOPCODES
;)
723 const char *name
= mips_opcodes
[i
].name
;
725 retval
= hash_insert (op_hash
, name
, (PTR
) &mips_opcodes
[i
]);
728 fprintf (stderr
, "internal error: can't hash `%s': %s\n",
729 mips_opcodes
[i
].name
, retval
);
730 as_fatal ("Broken assembler. No assembly attempted.");
734 if (mips_opcodes
[i
].pinfo
!= INSN_MACRO
735 && ((mips_opcodes
[i
].match
& mips_opcodes
[i
].mask
)
736 != mips_opcodes
[i
].match
))
738 fprintf (stderr
, "internal error: bad opcode: `%s' \"%s\"\n",
739 mips_opcodes
[i
].name
, mips_opcodes
[i
].args
);
740 as_fatal ("Broken assembler. No assembly attempted.");
744 while ((i
< NUMOPCODES
) && !strcmp (mips_opcodes
[i
].name
, name
));
747 mips_no_prev_insn ();
755 /* set the default alignment for the text section (2**2) */
756 record_alignment (text_section
, 2);
758 if (USE_GLOBAL_POINTER_OPT
)
759 bfd_set_gp_size (stdoutput
, g_switch_value
);
761 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
763 /* Sections must be aligned to 16 byte boundaries. */
764 (void) bfd_set_section_alignment (stdoutput
, text_section
, 4);
765 (void) bfd_set_section_alignment (stdoutput
, data_section
, 4);
766 (void) bfd_set_section_alignment (stdoutput
, bss_section
, 4);
768 /* Create a .reginfo section for register masks and a .mdebug
769 section for debugging information. */
777 sec
= subseg_new (".reginfo", (subsegT
) 0);
779 /* The ABI says this section should be loaded so that the
780 running program can access it. */
781 (void) bfd_set_section_flags (stdoutput
, sec
,
782 (SEC_ALLOC
| SEC_LOAD
783 | SEC_READONLY
| SEC_DATA
));
784 (void) bfd_set_section_alignment (stdoutput
, sec
, 2);
787 mips_regmask_frag
= frag_more (sizeof (Elf32_External_RegInfo
));
792 sec
= subseg_new (".mdebug", (subsegT
) 0);
793 (void) bfd_set_section_flags (stdoutput
, sec
,
794 SEC_HAS_CONTENTS
| SEC_READONLY
);
795 (void) bfd_set_section_alignment (stdoutput
, sec
, 2);
798 subseg_set (seg
, subseg
);
802 if (! ECOFF_DEBUGGING
)
809 if (! ECOFF_DEBUGGING
)
817 struct mips_cl_insn insn
;
819 imm_expr
.X_op
= O_absent
;
820 imm_reloc
= BFD_RELOC_UNUSED
;
821 imm_unmatched_hi
= false;
822 offset_expr
.X_op
= O_absent
;
823 offset_reloc
= BFD_RELOC_UNUSED
;
825 mips_ip (str
, &insn
);
828 as_bad ("%s `%s'", insn_error
, str
);
831 if (insn
.insn_mo
->pinfo
== INSN_MACRO
)
837 if (imm_expr
.X_op
!= O_absent
)
838 append_insn ((char *) NULL
, &insn
, &imm_expr
, imm_reloc
,
840 else if (offset_expr
.X_op
!= O_absent
)
841 append_insn ((char *) NULL
, &insn
, &offset_expr
, offset_reloc
, false);
843 append_insn ((char *) NULL
, &insn
, NULL
, BFD_RELOC_UNUSED
, false);
847 /* See whether instruction IP reads register REG. If FPR is non-zero,
848 REG is a floating point register. */
851 insn_uses_reg (ip
, reg
, fpr
)
852 struct mips_cl_insn
*ip
;
856 /* Don't report on general register 0, since it never changes. */
857 if (! fpr
&& reg
== 0)
862 /* If we are called with either $f0 or $f1, we must check $f0.
863 This is not optimal, because it will introduce an unnecessary
864 NOP between "lwc1 $f0" and "swc1 $f1". To fix this we would
865 need to distinguish reading both $f0 and $f1 or just one of
866 them. Note that we don't have to check the other way,
867 because there is no instruction that sets both $f0 and $f1
868 and requires a delay. */
869 if ((ip
->insn_mo
->pinfo
& INSN_READ_FPR_S
)
870 && (((ip
->insn_opcode
>> OP_SH_FS
) & OP_MASK_FS
)
871 == (reg
&~ (unsigned) 1)))
873 if ((ip
->insn_mo
->pinfo
& INSN_READ_FPR_T
)
874 && (((ip
->insn_opcode
>> OP_SH_FT
) & OP_MASK_FT
)
875 == (reg
&~ (unsigned) 1)))
880 if ((ip
->insn_mo
->pinfo
& INSN_READ_GPR_S
)
881 && ((ip
->insn_opcode
>> OP_SH_RS
) & OP_MASK_RS
) == reg
)
883 if ((ip
->insn_mo
->pinfo
& INSN_READ_GPR_T
)
884 && ((ip
->insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
) == reg
)
891 /* This function returns true if modifying a register requires a
895 reg_needs_delay (reg
)
898 unsigned long prev_pinfo
;
900 prev_pinfo
= prev_insn
.insn_mo
->pinfo
;
903 && ((prev_pinfo
& INSN_LOAD_COPROC_DELAY
)
905 && (prev_pinfo
& INSN_LOAD_MEMORY_DELAY
))))
907 /* A load from a coprocessor or from memory. All load
908 delays delay the use of general register rt for one
909 instruction on the r3000. The r6000 and r4000 use
911 know (prev_pinfo
& INSN_WRITE_GPR_T
);
912 if (reg
== ((prev_insn
.insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
))
919 /* Output an instruction. PLACE is where to put the instruction; if
920 it is NULL, this uses frag_more to get room. IP is the instruction
921 information. ADDRESS_EXPR is an operand of the instruction to be
922 used with RELOC_TYPE. */
925 append_insn (place
, ip
, address_expr
, reloc_type
, unmatched_hi
)
927 struct mips_cl_insn
*ip
;
928 expressionS
*address_expr
;
929 bfd_reloc_code_real_type reloc_type
;
930 boolean unmatched_hi
;
932 register unsigned long prev_pinfo
, pinfo
;
937 prev_pinfo
= prev_insn
.insn_mo
->pinfo
;
938 pinfo
= ip
->insn_mo
->pinfo
;
940 if (place
== NULL
&& ! mips_noreorder
)
942 /* If the previous insn required any delay slots, see if we need
943 to insert a NOP or two. There are eight kinds of possible
944 hazards, of which an instruction can have at most one type.
945 (1) a load from memory delay
946 (2) a load from a coprocessor delay
947 (3) an unconditional branch delay
948 (4) a conditional branch delay
949 (5) a move to coprocessor register delay
950 (6) a load coprocessor register from memory delay
951 (7) a coprocessor condition code delay
952 (8) a HI/LO special register delay
954 There are a lot of optimizations we could do that we don't.
955 In particular, we do not, in general, reorder instructions.
956 If you use gcc with optimization, it will reorder
957 instructions and generally do much more optimization then we
958 do here; repeating all that work in the assembler would only
959 benefit hand written assembly code, and does not seem worth
962 /* This is how a NOP is emitted. */
963 #define emit_nop() md_number_to_chars (frag_more (4), 0, 4)
965 /* The previous insn might require a delay slot, depending upon
966 the contents of the current insn. */
968 && ((prev_pinfo
& INSN_LOAD_COPROC_DELAY
)
970 && (prev_pinfo
& INSN_LOAD_MEMORY_DELAY
))))
972 /* A load from a coprocessor or from memory. All load
973 delays delay the use of general register rt for one
974 instruction on the r3000. The r6000 and r4000 use
976 know (prev_pinfo
& INSN_WRITE_GPR_T
);
977 if (mips_optimize
== 0
978 || insn_uses_reg (ip
,
979 ((prev_insn
.insn_opcode
>> OP_SH_RT
)
984 else if (mips_isa
< 4
985 && ((prev_pinfo
& INSN_COPROC_MOVE_DELAY
)
987 && (prev_pinfo
& INSN_COPROC_MEMORY_DELAY
))))
989 /* A generic coprocessor delay. The previous instruction
990 modified a coprocessor general or control register. If
991 it modified a control register, we need to avoid any
992 coprocessor instruction (this is probably not always
993 required, but it sometimes is). If it modified a general
994 register, we avoid using that register.
996 On the r6000 and r4000 loading a coprocessor register
997 from memory is interlocked, and does not require a delay.
999 This case is not handled very well. There is no special
1000 knowledge of CP0 handling, and the coprocessors other
1001 than the floating point unit are not distinguished at
1003 if (prev_pinfo
& INSN_WRITE_FPR_T
)
1005 if (mips_optimize
== 0
1006 || insn_uses_reg (ip
,
1007 ((prev_insn
.insn_opcode
>> OP_SH_FT
)
1012 else if (prev_pinfo
& INSN_WRITE_FPR_S
)
1014 if (mips_optimize
== 0
1015 || insn_uses_reg (ip
,
1016 ((prev_insn
.insn_opcode
>> OP_SH_FS
)
1023 /* We don't know exactly what the previous instruction
1024 does. If the current instruction uses a coprocessor
1025 register, we must insert a NOP. If previous
1026 instruction may set the condition codes, and the
1027 current instruction uses them, we must insert two
1029 if (mips_optimize
== 0
1030 || ((prev_pinfo
& INSN_WRITE_COND_CODE
)
1031 && (pinfo
& INSN_READ_COND_CODE
)))
1033 else if (pinfo
& INSN_COP
)
1037 else if (mips_isa
< 4
1038 && (prev_pinfo
& INSN_WRITE_COND_CODE
))
1040 /* The previous instruction sets the coprocessor condition
1041 codes, but does not require a general coprocessor delay
1042 (this means it is a floating point comparison
1043 instruction). If this instruction uses the condition
1044 codes, we need to insert a single NOP. */
1045 if (mips_optimize
== 0
1046 || (pinfo
& INSN_READ_COND_CODE
))
1049 else if (prev_pinfo
& INSN_READ_LO
)
1051 /* The previous instruction reads the LO register; if the
1052 current instruction writes to the LO register, we must
1053 insert two NOPS. The R4650 and VR4100 have interlocks. */
1055 && (mips_optimize
== 0
1056 || (pinfo
& INSN_WRITE_LO
)))
1059 else if (prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
1061 /* The previous instruction reads the HI register; if the
1062 current instruction writes to the HI register, we must
1063 insert a NOP. The R4650 and VR4100 have interlocks. */
1065 && (mips_optimize
== 0
1066 || (pinfo
& INSN_WRITE_HI
)))
1070 /* There are two cases which require two intervening
1071 instructions: 1) setting the condition codes using a move to
1072 coprocessor instruction which requires a general coprocessor
1073 delay and then reading the condition codes 2) reading the HI
1074 or LO register and then writing to it (except on the R4650,
1075 and VR4100 which have interlocks). If we are not already
1076 emitting a NOP instruction, we must check for these cases
1077 compared to the instruction previous to the previous
1081 && (prev_prev_insn
.insn_mo
->pinfo
& INSN_COPROC_MOVE_DELAY
)
1082 && (prev_prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
)
1083 && (pinfo
& INSN_READ_COND_CODE
))
1084 || ((prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
)
1085 && (pinfo
& INSN_WRITE_LO
)
1087 || ((prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
1088 && (pinfo
& INSN_WRITE_HI
)
1092 /* If we are being given a nop instruction, don't bother with
1093 one of the nops we would otherwise output. This will only
1094 happen when a nop instruction is used with mips_optimize set
1096 if (nops
> 0 && ip
->insn_opcode
== 0)
1099 /* Now emit the right number of NOP instructions. */
1104 for (i
= 0; i
< nops
; i
++)
1108 listing_prev_line ();
1109 /* We may be at the start of a variant frag. In case we
1110 are, make sure there is enough space for the frag
1111 after the frags created by listing_prev_line. The
1112 argument to frag_grow here must be at least as large
1113 as the argument to all other calls to frag_grow in
1114 this file. We don't have to worry about being in the
1115 middle of a variant frag, because the variants insert
1116 all needed nop instructions themselves. */
1119 if (insn_label
!= NULL
)
1121 assert (S_GET_SEGMENT (insn_label
) == now_seg
);
1122 insn_label
->sy_frag
= frag_now
;
1123 S_SET_VALUE (insn_label
, (valueT
) frag_now_fix ());
1133 if (address_expr
!= NULL
)
1135 if (address_expr
->X_op
== O_constant
)
1140 ip
->insn_opcode
|= address_expr
->X_add_number
;
1143 case BFD_RELOC_LO16
:
1144 ip
->insn_opcode
|= address_expr
->X_add_number
& 0xffff;
1147 case BFD_RELOC_MIPS_JMP
:
1148 case BFD_RELOC_16_PCREL_S2
:
1157 assert (reloc_type
!= BFD_RELOC_UNUSED
);
1159 /* Don't generate a reloc if we are writing into a variant
1163 fixp
= fix_new_exp (frag_now
, f
- frag_now
->fr_literal
, 4,
1165 reloc_type
== BFD_RELOC_16_PCREL_S2
,
1169 struct mips_hi_fixup
*hi_fixup
;
1171 assert (reloc_type
== BFD_RELOC_HI16_S
);
1172 hi_fixup
= ((struct mips_hi_fixup
*)
1173 xmalloc (sizeof (struct mips_hi_fixup
)));
1174 hi_fixup
->fixp
= fixp
;
1175 hi_fixup
->seg
= now_seg
;
1176 hi_fixup
->next
= mips_hi_fixup_list
;
1177 mips_hi_fixup_list
= hi_fixup
;
1183 md_number_to_chars (f
, ip
->insn_opcode
, 4);
1185 /* Update the register mask information. */
1186 if (pinfo
& INSN_WRITE_GPR_D
)
1187 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
);
1188 if ((pinfo
& (INSN_WRITE_GPR_T
| INSN_READ_GPR_T
)) != 0)
1189 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
);
1190 if (pinfo
& INSN_READ_GPR_S
)
1191 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> OP_SH_RS
) & OP_MASK_RS
);
1192 if (pinfo
& INSN_WRITE_GPR_31
)
1193 mips_gprmask
|= 1 << 31;
1194 if (pinfo
& INSN_WRITE_FPR_D
)
1195 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FD
) & OP_MASK_FD
);
1196 if ((pinfo
& (INSN_WRITE_FPR_S
| INSN_READ_FPR_S
)) != 0)
1197 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FS
) & OP_MASK_FS
);
1198 if ((pinfo
& (INSN_WRITE_FPR_T
| INSN_READ_FPR_T
)) != 0)
1199 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FT
) & OP_MASK_FT
);
1200 if ((pinfo
& INSN_READ_FPR_R
) != 0)
1201 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FR
) & OP_MASK_FR
);
1202 if (pinfo
& INSN_COP
)
1204 /* We don't keep enough information to sort these cases out. */
1206 /* Never set the bit for $0, which is always zero. */
1207 mips_gprmask
&=~ 1 << 0;
1209 if (place
== NULL
&& ! mips_noreorder
)
1211 /* Filling the branch delay slot is more complex. We try to
1212 switch the branch with the previous instruction, which we can
1213 do if the previous instruction does not set up a condition
1214 that the branch tests and if the branch is not itself the
1215 target of any branch. */
1216 if ((pinfo
& INSN_UNCOND_BRANCH_DELAY
)
1217 || (pinfo
& INSN_COND_BRANCH_DELAY
))
1219 if (mips_optimize
< 2
1220 /* If we have seen .set volatile or .set nomove, don't
1223 /* If we had to emit any NOP instructions, then we
1224 already know we can not swap. */
1226 /* If we don't even know the previous insn, we can not
1228 || ! prev_insn_valid
1229 /* If the previous insn is already in a branch delay
1230 slot, then we can not swap. */
1231 || prev_insn_is_delay_slot
1232 /* If the previous previous insn was in a .set
1233 noreorder, we can't swap. Actually, the MIPS
1234 assembler will swap in this situation. However, gcc
1235 configured -with-gnu-as will generate code like
1241 in which we can not swap the bne and INSN. If gcc is
1242 not configured -with-gnu-as, it does not output the
1243 .set pseudo-ops. We don't have to check
1244 prev_insn_unreordered, because prev_insn_valid will
1245 be 0 in that case. We don't want to use
1246 prev_prev_insn_valid, because we do want to be able
1247 to swap at the start of a function. */
1248 || prev_prev_insn_unreordered
1249 /* If the branch is itself the target of a branch, we
1250 can not swap. We cheat on this; all we check for is
1251 whether there is a label on this instruction. If
1252 there are any branches to anything other than a
1253 label, users must use .set noreorder. */
1254 || insn_label
!= NULL
1255 /* If the previous instruction is in a variant frag, we
1256 can not do the swap. */
1257 || prev_insn_frag
->fr_type
== rs_machine_dependent
1258 /* If the branch reads the condition codes, we don't
1259 even try to swap, because in the sequence
1264 we can not swap, and I don't feel like handling that
1267 && (pinfo
& INSN_READ_COND_CODE
))
1268 /* We can not swap with an instruction that requires a
1269 delay slot, becase the target of the branch might
1270 interfere with that instruction. */
1273 & (INSN_LOAD_COPROC_DELAY
1274 | INSN_COPROC_MOVE_DELAY
1275 | INSN_WRITE_COND_CODE
)))
1282 & (INSN_LOAD_MEMORY_DELAY
1283 | INSN_COPROC_MEMORY_DELAY
)))
1284 /* We can not swap with a branch instruction. */
1286 & (INSN_UNCOND_BRANCH_DELAY
1287 | INSN_COND_BRANCH_DELAY
1288 | INSN_COND_BRANCH_LIKELY
))
1289 /* We do not swap with a trap instruction, since it
1290 complicates trap handlers to have the trap
1291 instruction be in a delay slot. */
1292 || (prev_pinfo
& INSN_TRAP
)
1293 /* If the branch reads a register that the previous
1294 instruction sets, we can not swap. */
1295 || ((prev_pinfo
& INSN_WRITE_GPR_T
)
1296 && insn_uses_reg (ip
,
1297 ((prev_insn
.insn_opcode
>> OP_SH_RT
)
1300 || ((prev_pinfo
& INSN_WRITE_GPR_D
)
1301 && insn_uses_reg (ip
,
1302 ((prev_insn
.insn_opcode
>> OP_SH_RD
)
1305 /* If the branch writes a register that the previous
1306 instruction sets, we can not swap (we know that
1307 branches write only to RD or to $31). */
1308 || ((prev_pinfo
& INSN_WRITE_GPR_T
)
1309 && (((pinfo
& INSN_WRITE_GPR_D
)
1310 && (((prev_insn
.insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
)
1311 == ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)))
1312 || ((pinfo
& INSN_WRITE_GPR_31
)
1313 && (((prev_insn
.insn_opcode
>> OP_SH_RT
)
1316 || ((prev_pinfo
& INSN_WRITE_GPR_D
)
1317 && (((pinfo
& INSN_WRITE_GPR_D
)
1318 && (((prev_insn
.insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)
1319 == ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)))
1320 || ((pinfo
& INSN_WRITE_GPR_31
)
1321 && (((prev_insn
.insn_opcode
>> OP_SH_RD
)
1324 /* If the branch writes a register that the previous
1325 instruction reads, we can not swap (we know that
1326 branches only write to RD or to $31). */
1327 || ((pinfo
& INSN_WRITE_GPR_D
)
1328 && insn_uses_reg (&prev_insn
,
1329 ((ip
->insn_opcode
>> OP_SH_RD
)
1332 || ((pinfo
& INSN_WRITE_GPR_31
)
1333 && insn_uses_reg (&prev_insn
, 31, 0))
1334 /* If we are generating embedded PIC code, the branch
1335 might be expanded into a sequence which uses $at, so
1336 we can't swap with an instruction which reads it. */
1337 || (mips_pic
== EMBEDDED_PIC
1338 && insn_uses_reg (&prev_insn
, AT
, 0))
1339 /* If the previous previous instruction has a load
1340 delay, and sets a register that the branch reads, we
1343 && ((prev_prev_insn
.insn_mo
->pinfo
& INSN_LOAD_COPROC_DELAY
)
1345 && (prev_prev_insn
.insn_mo
->pinfo
1346 & INSN_LOAD_MEMORY_DELAY
)))
1347 && insn_uses_reg (ip
,
1348 ((prev_prev_insn
.insn_opcode
>> OP_SH_RT
)
1352 /* We could do even better for unconditional branches to
1353 portions of this object file; we could pick up the
1354 instruction at the destination, put it in the delay
1355 slot, and bump the destination address. */
1357 /* Update the previous insn information. */
1358 prev_prev_insn
= *ip
;
1359 prev_insn
.insn_mo
= &dummy_opcode
;
1366 /* It looks like we can actually do the swap. */
1367 prev_f
= prev_insn_frag
->fr_literal
+ prev_insn_where
;
1368 memcpy (temp
, prev_f
, 4);
1369 memcpy (prev_f
, f
, 4);
1370 memcpy (f
, temp
, 4);
1373 prev_insn_fixp
->fx_frag
= frag_now
;
1374 prev_insn_fixp
->fx_where
= f
- frag_now
->fr_literal
;
1378 fixp
->fx_frag
= prev_insn_frag
;
1379 fixp
->fx_where
= prev_insn_where
;
1381 /* Update the previous insn information; leave prev_insn
1383 prev_prev_insn
= *ip
;
1385 prev_insn_is_delay_slot
= 1;
1387 /* If that was an unconditional branch, forget the previous
1388 insn information. */
1389 if (pinfo
& INSN_UNCOND_BRANCH_DELAY
)
1391 prev_prev_insn
.insn_mo
= &dummy_opcode
;
1392 prev_insn
.insn_mo
= &dummy_opcode
;
1395 else if (pinfo
& INSN_COND_BRANCH_LIKELY
)
1397 /* We don't yet optimize a branch likely. What we should do
1398 is look at the target, copy the instruction found there
1399 into the delay slot, and increment the branch to jump to
1400 the next instruction. */
1402 /* Update the previous insn information. */
1403 prev_prev_insn
= *ip
;
1404 prev_insn
.insn_mo
= &dummy_opcode
;
1408 /* Update the previous insn information. */
1410 prev_prev_insn
.insn_mo
= &dummy_opcode
;
1412 prev_prev_insn
= prev_insn
;
1415 /* Any time we see a branch, we always fill the delay slot
1416 immediately; since this insn is not a branch, we know it
1417 is not in a delay slot. */
1418 prev_insn_is_delay_slot
= 0;
1421 prev_prev_insn_unreordered
= prev_insn_unreordered
;
1422 prev_insn_unreordered
= 0;
1423 prev_insn_frag
= frag_now
;
1424 prev_insn_where
= f
- frag_now
->fr_literal
;
1425 prev_insn_fixp
= fixp
;
1426 prev_insn_valid
= 1;
1429 /* We just output an insn, so the next one doesn't have a label. */
1433 /* This function forgets that there was any previous instruction or
1437 mips_no_prev_insn ()
1439 prev_insn
.insn_mo
= &dummy_opcode
;
1440 prev_prev_insn
.insn_mo
= &dummy_opcode
;
1441 prev_insn_valid
= 0;
1442 prev_insn_is_delay_slot
= 0;
1443 prev_insn_unreordered
= 0;
1444 prev_prev_insn_unreordered
= 0;
1448 /* This function must be called whenever we turn on noreorder or emit
1449 something other than instructions. It inserts any NOPS which might
1450 be needed by the previous instruction, and clears the information
1451 kept for the previous instructions. */
1456 if (! mips_noreorder
)
1462 && (prev_insn
.insn_mo
->pinfo
1463 & (INSN_LOAD_COPROC_DELAY
1464 | INSN_COPROC_MOVE_DELAY
1465 | INSN_WRITE_COND_CODE
)))
1467 && (prev_insn
.insn_mo
->pinfo
1471 && (prev_insn
.insn_mo
->pinfo
1472 & (INSN_LOAD_MEMORY_DELAY
1473 | INSN_COPROC_MEMORY_DELAY
))))
1477 && (prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
))
1479 && ((prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
1480 || (prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
))))
1483 else if ((mips_isa
< 4
1484 && (prev_prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
))
1486 && ((prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
1487 || (prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
))))
1492 if (insn_label
!= NULL
)
1494 assert (S_GET_SEGMENT (insn_label
) == now_seg
);
1495 insn_label
->sy_frag
= frag_now
;
1496 S_SET_VALUE (insn_label
, (valueT
) frag_now_fix ());
1501 mips_no_prev_insn ();
1504 /* Build an instruction created by a macro expansion. This is passed
1505 a pointer to the count of instructions created so far, an
1506 expression, the name of the instruction to build, an operand format
1507 string, and corresponding arguments. */
1511 macro_build (char *place
,
1519 macro_build (place
, counter
, ep
, name
, fmt
, va_alist
)
1528 struct mips_cl_insn insn
;
1529 bfd_reloc_code_real_type r
;
1533 va_start (args
, fmt
);
1539 * If the macro is about to expand into a second instruction,
1540 * print a warning if needed. We need to pass ip as a parameter
1541 * to generate a better warning message here...
1543 if (mips_warn_about_macros
&& place
== NULL
&& *counter
== 1)
1544 as_warn ("Macro instruction expanded into multiple instructions");
1547 *counter
+= 1; /* bump instruction counter */
1549 r
= BFD_RELOC_UNUSED
;
1550 insn
.insn_mo
= (struct mips_opcode
*) hash_find (op_hash
, name
);
1551 assert (insn
.insn_mo
);
1552 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
1554 while (strcmp (fmt
, insn
.insn_mo
->args
) != 0
1555 || insn
.insn_mo
->pinfo
== INSN_MACRO
1556 || ((insn
.insn_mo
->pinfo
& INSN_ISA
) == INSN_ISA2
1558 || ((insn
.insn_mo
->pinfo
& INSN_ISA
) == INSN_ISA3
1560 || ((insn
.insn_mo
->pinfo
& INSN_ISA
) == INSN_ISA4
1562 || ((insn
.insn_mo
->pinfo
& INSN_ISA
) == INSN_4650
1564 || ((insn
.insn_mo
->pinfo
& INSN_ISA
) == INSN_4010
1566 || ((insn
.insn_mo
->pinfo
& INSN_ISA
) == INSN_4100
1570 assert (insn
.insn_mo
->name
);
1571 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
1573 insn
.insn_opcode
= insn
.insn_mo
->match
;
1589 insn
.insn_opcode
|= va_arg (args
, int) << 16;
1595 insn
.insn_opcode
|= va_arg (args
, int) << 16;
1600 insn
.insn_opcode
|= va_arg (args
, int) << 11;
1605 insn
.insn_opcode
|= va_arg (args
, int) << 11;
1612 insn
.insn_opcode
|= va_arg (args
, int) << 6;
1616 insn
.insn_opcode
|= va_arg (args
, int) << 6;
1620 insn
.insn_opcode
|= va_arg (args
, int) << 6;
1627 insn
.insn_opcode
|= va_arg (args
, int) << 21;
1633 r
= (bfd_reloc_code_real_type
) va_arg (args
, int);
1634 assert (r
== BFD_RELOC_MIPS_GPREL
1635 || r
== BFD_RELOC_MIPS_LITERAL
1636 || r
== BFD_RELOC_LO16
1637 || r
== BFD_RELOC_MIPS_GOT16
1638 || r
== BFD_RELOC_MIPS_CALL16
1639 || r
== BFD_RELOC_MIPS_GOT_LO16
1640 || r
== BFD_RELOC_MIPS_CALL_LO16
1641 || (ep
->X_op
== O_subtract
1642 && now_seg
== text_section
1643 && r
== BFD_RELOC_PCREL_LO16
));
1647 r
= (bfd_reloc_code_real_type
) va_arg (args
, int);
1649 && (ep
->X_op
== O_constant
1650 || (ep
->X_op
== O_symbol
1651 && (r
== BFD_RELOC_HI16_S
1652 || r
== BFD_RELOC_HI16
1653 || r
== BFD_RELOC_MIPS_GOT_HI16
1654 || r
== BFD_RELOC_MIPS_CALL_HI16
))
1655 || (ep
->X_op
== O_subtract
1656 && now_seg
== text_section
1657 && r
== BFD_RELOC_PCREL_HI16_S
)));
1658 if (ep
->X_op
== O_constant
)
1660 insn
.insn_opcode
|= (ep
->X_add_number
>> 16) & 0xffff;
1662 r
= BFD_RELOC_UNUSED
;
1667 assert (ep
!= NULL
);
1669 * This allows macro() to pass an immediate expression for
1670 * creating short branches without creating a symbol.
1671 * Note that the expression still might come from the assembly
1672 * input, in which case the value is not checked for range nor
1673 * is a relocation entry generated (yuck).
1675 if (ep
->X_op
== O_constant
)
1677 insn
.insn_opcode
|= (ep
->X_add_number
>> 2) & 0xffff;
1681 r
= BFD_RELOC_16_PCREL_S2
;
1685 assert (ep
!= NULL
);
1686 r
= BFD_RELOC_MIPS_JMP
;
1695 assert (r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
1697 append_insn (place
, &insn
, ep
, r
, false);
1701 * Generate a "lui" instruction.
1704 macro_build_lui (place
, counter
, ep
, regnum
)
1710 expressionS high_expr
;
1711 struct mips_cl_insn insn
;
1712 bfd_reloc_code_real_type r
;
1713 CONST
char *name
= "lui";
1714 CONST
char *fmt
= "t,u";
1720 high_expr
.X_op
= O_constant
;
1721 high_expr
.X_add_number
= ep
->X_add_number
;
1724 if (high_expr
.X_op
== O_constant
)
1726 /* we can compute the instruction now without a relocation entry */
1727 if (high_expr
.X_add_number
& 0x8000)
1728 high_expr
.X_add_number
+= 0x10000;
1729 high_expr
.X_add_number
=
1730 ((unsigned long) high_expr
.X_add_number
>> 16) & 0xffff;
1731 r
= BFD_RELOC_UNUSED
;
1735 assert (ep
->X_op
== O_symbol
);
1736 /* _gp_disp is a special case, used from s_cpload. */
1737 assert (mips_pic
== NO_PIC
1738 || strcmp (S_GET_NAME (ep
->X_add_symbol
), "_gp_disp") == 0);
1739 r
= BFD_RELOC_HI16_S
;
1743 * If the macro is about to expand into a second instruction,
1744 * print a warning if needed. We need to pass ip as a parameter
1745 * to generate a better warning message here...
1747 if (mips_warn_about_macros
&& place
== NULL
&& *counter
== 1)
1748 as_warn ("Macro instruction expanded into multiple instructions");
1751 *counter
+= 1; /* bump instruction counter */
1753 insn
.insn_mo
= (struct mips_opcode
*) hash_find (op_hash
, name
);
1754 assert (insn
.insn_mo
);
1755 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
1756 assert (strcmp (fmt
, insn
.insn_mo
->args
) == 0);
1758 insn
.insn_opcode
= insn
.insn_mo
->match
| (regnum
<< OP_SH_RT
);
1759 if (r
== BFD_RELOC_UNUSED
)
1761 insn
.insn_opcode
|= high_expr
.X_add_number
;
1762 append_insn (place
, &insn
, NULL
, r
, false);
1765 append_insn (place
, &insn
, &high_expr
, r
, false);
1769 * Generates code to set the $at register to true (one)
1770 * if reg is less than the immediate expression.
1773 set_at (counter
, reg
, unsignedp
)
1778 if (imm_expr
.X_add_number
>= -0x8000 && imm_expr
.X_add_number
< 0x8000)
1779 macro_build ((char *) NULL
, counter
, &imm_expr
,
1780 unsignedp
? "sltiu" : "slti",
1781 "t,r,j", AT
, reg
, (int) BFD_RELOC_LO16
);
1784 load_register (counter
, AT
, &imm_expr
, 0);
1785 macro_build ((char *) NULL
, counter
, NULL
,
1786 unsignedp
? "sltu" : "slt",
1787 "d,v,t", AT
, reg
, AT
);
1791 /* Warn if an expression is not a constant. */
1794 check_absolute_expr (ip
, ex
)
1795 struct mips_cl_insn
*ip
;
1798 if (ex
->X_op
!= O_constant
)
1799 as_warn ("Instruction %s requires absolute expression", ip
->insn_mo
->name
);
1803 * This routine generates the least number of instructions neccessary to load
1804 * an absolute expression value into a register.
1807 load_register (counter
, reg
, ep
, dbl
)
1814 expressionS hi32
, lo32
, tmp
;
1816 if (ep
->X_op
!= O_big
)
1818 assert (ep
->X_op
== O_constant
);
1819 if (ep
->X_add_number
< 0x8000
1820 && (ep
->X_add_number
>= 0
1821 || (ep
->X_add_number
>= -0x8000
1824 || sizeof (ep
->X_add_number
) > 4))))
1826 /* We can handle 16 bit signed values with an addiu to
1827 $zero. No need to ever use daddiu here, since $zero and
1828 the result are always correct in 32 bit mode. */
1829 macro_build ((char *) NULL
, counter
, ep
, "addiu", "t,r,j", reg
, 0,
1830 (int) BFD_RELOC_LO16
);
1833 else if (ep
->X_add_number
>= 0 && ep
->X_add_number
< 0x10000)
1835 /* We can handle 16 bit unsigned values with an ori to
1837 macro_build ((char *) NULL
, counter
, ep
, "ori", "t,r,i", reg
, 0,
1838 (int) BFD_RELOC_LO16
);
1841 else if (((ep
->X_add_number
&~ (offsetT
) 0x7fffffff) == 0
1842 || ((ep
->X_add_number
&~ (offsetT
) 0x7fffffff)
1843 == ~ (offsetT
) 0x7fffffff))
1846 || sizeof (ep
->X_add_number
) > 4
1847 || (ep
->X_add_number
& 0x80000000) == 0))
1849 /* 32 bit values require an lui. */
1850 macro_build ((char *) NULL
, counter
, ep
, "lui", "t,u", reg
,
1851 (int) BFD_RELOC_HI16
);
1852 if ((ep
->X_add_number
& 0xffff) != 0)
1853 macro_build ((char *) NULL
, counter
, ep
, "ori", "t,r,i", reg
, reg
,
1854 (int) BFD_RELOC_LO16
);
1859 /* 32 bit value with high bit set being loaded into a 64 bit
1860 register. We can't use lui, because that would
1861 incorrectly set the 32 high bits. */
1862 generic_bignum
[3] = 0;
1863 generic_bignum
[2] = 0;
1864 generic_bignum
[1] = (ep
->X_add_number
>> 16) & 0xffff;
1865 generic_bignum
[0] = ep
->X_add_number
& 0xffff;
1867 tmp
.X_add_number
= 4;
1872 /* The value is larger than 32 bits. */
1876 as_bad ("Number larger than 32 bits");
1877 macro_build ((char *) NULL
, counter
, ep
, "addiu", "t,r,j", reg
, 0,
1878 (int) BFD_RELOC_LO16
);
1882 if (ep
->X_op
!= O_big
)
1886 hi32
.X_add_number
>>= shift
;
1887 hi32
.X_add_number
&= 0xffffffff;
1888 if ((hi32
.X_add_number
& 0x80000000) != 0)
1889 hi32
.X_add_number
|= ~ (offsetT
) 0xffffffff;
1891 lo32
.X_add_number
&= 0xffffffff;
1895 assert (ep
->X_add_number
> 2);
1896 if (ep
->X_add_number
== 3)
1897 generic_bignum
[3] = 0;
1898 else if (ep
->X_add_number
> 4)
1899 as_bad ("Number larger than 64 bits");
1900 lo32
.X_op
= O_constant
;
1901 lo32
.X_add_number
= generic_bignum
[0] + (generic_bignum
[1] << 16);
1902 hi32
.X_op
= O_constant
;
1903 hi32
.X_add_number
= generic_bignum
[2] + (generic_bignum
[3] << 16);
1906 if (hi32
.X_add_number
== 0)
1910 if (hi32
.X_add_number
== 0xffffffff)
1912 if ((lo32
.X_add_number
& 0xffff8000) == 0xffff8000)
1914 macro_build ((char *) NULL
, counter
, &lo32
, "addiu", "t,r,j", reg
, 0,
1915 (int) BFD_RELOC_LO16
);
1918 if (lo32
.X_add_number
& 0x80000000)
1920 macro_build ((char *) NULL
, counter
, &lo32
, "lui", "t,u", reg
,
1921 (int) BFD_RELOC_HI16
);
1922 macro_build ((char *) NULL
, counter
, &lo32
, "ori", "t,r,i", reg
, reg
,
1923 (int) BFD_RELOC_LO16
);
1927 load_register (counter
, reg
, &hi32
, 0);
1930 if ((lo32
.X_add_number
& 0xffff0000) == 0)
1934 macro_build ((char *) NULL
, counter
, NULL
, "dsll32", "d,w,<", reg
,
1943 if ((freg
== 0) && (lo32
.X_add_number
== 0xffffffff))
1945 macro_build ((char *) NULL
, counter
, &lo32
, "lui", "t,u", reg
,
1946 (int) BFD_RELOC_HI16
);
1947 macro_build ((char *) NULL
, counter
, NULL
, "dsrl32", "d,w,<", reg
,
1954 macro_build ((char *) NULL
, counter
, NULL
, "dsll", "d,w,<", reg
,
1959 mid16
.X_add_number
>>= 16;
1960 macro_build ((char *) NULL
, counter
, &mid16
, "ori", "t,r,i", reg
,
1961 freg
, (int) BFD_RELOC_LO16
);
1962 macro_build ((char *) NULL
, counter
, NULL
, "dsll", "d,w,<", reg
,
1966 if ((lo32
.X_add_number
& 0xffff) != 0)
1967 macro_build ((char *) NULL
, counter
, &lo32
, "ori", "t,r,i", reg
, freg
,
1968 (int) BFD_RELOC_LO16
);
1971 /* Load an address into a register. */
1974 load_address (counter
, reg
, ep
)
1981 if (ep
->X_op
!= O_constant
1982 && ep
->X_op
!= O_symbol
)
1984 as_bad ("expression too complex");
1985 ep
->X_op
= O_constant
;
1988 if (ep
->X_op
== O_constant
)
1990 load_register (counter
, reg
, ep
, 0);
1994 if (mips_pic
== NO_PIC
)
1996 /* If this is a reference to a GP relative symbol, we want
1997 addiu $reg,$gp,<sym> (BFD_RELOC_MIPS_GPREL)
1999 lui $reg,<sym> (BFD_RELOC_HI16_S)
2000 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
2001 If we have an addend, we always use the latter form. */
2002 if ((valueT
) ep
->X_add_number
>= MAX_GPREL_OFFSET
2003 || nopic_need_relax (ep
->X_add_symbol
))
2008 macro_build ((char *) NULL
, counter
, ep
,
2009 mips_isa
< 3 ? "addiu" : "daddiu",
2010 "t,r,j", reg
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
2011 p
= frag_var (rs_machine_dependent
, 8, 0,
2012 RELAX_ENCODE (4, 8, 0, 4, 0, mips_warn_about_macros
),
2013 ep
->X_add_symbol
, (long) 0, (char *) NULL
);
2015 macro_build_lui (p
, counter
, ep
, reg
);
2018 macro_build (p
, counter
, ep
,
2019 mips_isa
< 3 ? "addiu" : "daddiu",
2020 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
2022 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
2026 /* If this is a reference to an external symbol, we want
2027 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
2029 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
2031 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
2032 If there is a constant, it must be added in after. */
2033 ex
.X_add_number
= ep
->X_add_number
;
2034 ep
->X_add_number
= 0;
2036 macro_build ((char *) NULL
, counter
, ep
,
2037 mips_isa
< 3 ? "lw" : "ld",
2038 "t,o(b)", reg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
2039 macro_build ((char *) NULL
, counter
, (expressionS
*) NULL
, "nop", "");
2040 p
= frag_var (rs_machine_dependent
, 4, 0,
2041 RELAX_ENCODE (0, 4, -8, 0, 0, mips_warn_about_macros
),
2042 ep
->X_add_symbol
, (long) 0, (char *) NULL
);
2043 macro_build (p
, counter
, ep
,
2044 mips_isa
< 3 ? "addiu" : "daddiu",
2045 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
2046 if (ex
.X_add_number
!= 0)
2048 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
2049 as_bad ("PIC code offset overflow (max 16 signed bits)");
2050 ex
.X_op
= O_constant
;
2051 macro_build ((char *) NULL
, counter
, &ex
,
2052 mips_isa
< 3 ? "addiu" : "daddiu",
2053 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
2056 else if (mips_pic
== SVR4_PIC
)
2061 /* This is the large GOT case. If this is a reference to an
2062 external symbol, we want
2063 lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
2065 lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16)
2066 Otherwise, for a reference to a local symbol, we want
2067 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
2069 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
2070 If there is a constant, it must be added in after. */
2071 ex
.X_add_number
= ep
->X_add_number
;
2072 ep
->X_add_number
= 0;
2073 if (reg_needs_delay (GP
))
2078 macro_build ((char *) NULL
, counter
, ep
, "lui", "t,u", reg
,
2079 (int) BFD_RELOC_MIPS_GOT_HI16
);
2080 macro_build ((char *) NULL
, counter
, (expressionS
*) NULL
,
2081 mips_isa
< 3 ? "addu" : "daddu",
2082 "d,v,t", reg
, reg
, GP
);
2083 macro_build ((char *) NULL
, counter
, ep
,
2084 mips_isa
< 3 ? "lw" : "ld",
2085 "t,o(b)", reg
, (int) BFD_RELOC_MIPS_GOT_LO16
, reg
);
2086 p
= frag_var (rs_machine_dependent
, 12 + off
, 0,
2087 RELAX_ENCODE (12, 12 + off
, off
, 8 + off
, 0,
2088 mips_warn_about_macros
),
2089 ep
->X_add_symbol
, (long) 0, (char *) NULL
);
2092 /* We need a nop before loading from $gp. This special
2093 check is required because the lui which starts the main
2094 instruction stream does not refer to $gp, and so will not
2095 insert the nop which may be required. */
2096 macro_build (p
, counter
, (expressionS
*) NULL
, "nop", "");
2099 macro_build (p
, counter
, ep
,
2100 mips_isa
< 3 ? "lw" : "ld",
2101 "t,o(b)", reg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
2103 macro_build (p
, counter
, (expressionS
*) NULL
, "nop", "");
2105 macro_build (p
, counter
, ep
,
2106 mips_isa
< 3 ? "addiu" : "daddiu",
2107 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
2108 if (ex
.X_add_number
!= 0)
2110 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
2111 as_bad ("PIC code offset overflow (max 16 signed bits)");
2112 ex
.X_op
= O_constant
;
2113 macro_build ((char *) NULL
, counter
, &ex
,
2114 mips_isa
< 3 ? "addiu" : "daddiu",
2115 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
2118 else if (mips_pic
== EMBEDDED_PIC
)
2121 addiu $reg,$gp,<sym> (BFD_RELOC_MIPS_GPREL)
2123 macro_build ((char *) NULL
, counter
, ep
,
2124 mips_isa
< 3 ? "addiu" : "daddiu",
2125 "t,r,j", reg
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
2133 * This routine implements the seemingly endless macro or synthesized
2134 * instructions and addressing modes in the mips assembly language. Many
2135 * of these macros are simple and are similar to each other. These could
2136 * probably be handled by some kind of table or grammer aproach instead of
2137 * this verbose method. Others are not simple macros but are more like
2138 * optimizing code generation.
2139 * One interesting optimization is when several store macros appear
2140 * consecutivly that would load AT with the upper half of the same address.
2141 * The ensuing load upper instructions are ommited. This implies some kind
2142 * of global optimization. We currently only optimize within a single macro.
2143 * For many of the load and store macros if the address is specified as a
2144 * constant expression in the first 64k of memory (ie ld $2,0x4000c) we
2145 * first load register 'at' with zero and use it as the base register. The
2146 * mips assembler simply uses register $zero. Just one tiny optimization
2151 struct mips_cl_insn
*ip
;
2153 register int treg
, sreg
, dreg
, breg
;
2168 bfd_reloc_code_real_type r
;
2170 int hold_mips_optimize
;
2172 treg
= (ip
->insn_opcode
>> 16) & 0x1f;
2173 dreg
= (ip
->insn_opcode
>> 11) & 0x1f;
2174 sreg
= breg
= (ip
->insn_opcode
>> 21) & 0x1f;
2175 mask
= ip
->insn_mo
->mask
;
2177 expr1
.X_op
= O_constant
;
2178 expr1
.X_op_symbol
= NULL
;
2179 expr1
.X_add_symbol
= NULL
;
2180 expr1
.X_add_number
= 1;
2192 mips_emit_delays ();
2194 mips_any_noreorder
= 1;
2196 expr1
.X_add_number
= 8;
2197 macro_build ((char *) NULL
, &icnt
, &expr1
, "bgez", "s,p", sreg
);
2199 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
2201 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
, sreg
, 0);
2202 macro_build ((char *) NULL
, &icnt
, NULL
,
2203 dbl
? "dsub" : "sub",
2204 "d,v,t", dreg
, 0, sreg
);
2227 if (imm_expr
.X_add_number
>= -0x8000 && imm_expr
.X_add_number
< 0x8000)
2229 macro_build ((char *) NULL
, &icnt
, &imm_expr
, s
, "t,r,j", treg
, sreg
,
2230 (int) BFD_RELOC_LO16
);
2233 load_register (&icnt
, AT
, &imm_expr
, dbl
);
2234 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "d,v,t", treg
, sreg
, AT
);
2253 if (imm_expr
.X_add_number
>= 0 && imm_expr
.X_add_number
< 0x10000)
2255 if (mask
!= M_NOR_I
)
2256 macro_build ((char *) NULL
, &icnt
, &imm_expr
, s
, "t,r,i", treg
,
2257 sreg
, (int) BFD_RELOC_LO16
);
2260 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "ori", "t,r,i",
2261 treg
, sreg
, (int) BFD_RELOC_LO16
);
2262 macro_build ((char *) NULL
, &icnt
, NULL
, "nor", "d,v,t",
2268 load_register (&icnt
, AT
, &imm_expr
, 0);
2269 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "d,v,t", treg
, sreg
, AT
);
2286 if (imm_expr
.X_add_number
== 0)
2288 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "s,t,p", sreg
,
2292 load_register (&icnt
, AT
, &imm_expr
, 0);
2293 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "s,t,p", sreg
, AT
);
2301 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2302 likely
? "bgezl" : "bgez",
2308 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2309 likely
? "blezl" : "blez",
2313 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", AT
, sreg
, treg
);
2314 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2315 likely
? "beql" : "beq",
2322 /* check for > max integer */
2323 maxnum
= 0x7fffffff;
2331 if (imm_expr
.X_add_number
>= maxnum
2332 && (mips_isa
< 3 || sizeof (maxnum
) > 4))
2335 /* result is always false */
2338 as_warn ("Branch %s is always false (nop)", ip
->insn_mo
->name
);
2339 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
2343 as_warn ("Branch likely %s is always false", ip
->insn_mo
->name
);
2344 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "bnel",
2349 imm_expr
.X_add_number
++;
2353 if (mask
== M_BGEL_I
)
2355 if (imm_expr
.X_add_number
== 0)
2357 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2358 likely
? "bgezl" : "bgez",
2362 if (imm_expr
.X_add_number
== 1)
2364 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2365 likely
? "bgtzl" : "bgtz",
2369 maxnum
= 0x7fffffff;
2377 maxnum
= - maxnum
- 1;
2378 if (imm_expr
.X_add_number
<= maxnum
2379 && (mips_isa
< 3 || sizeof (maxnum
) > 4))
2382 /* result is always true */
2383 as_warn ("Branch %s is always true", ip
->insn_mo
->name
);
2384 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "b", "p");
2387 set_at (&icnt
, sreg
, 0);
2388 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2389 likely
? "beql" : "beq",
2400 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2401 likely
? "beql" : "beq",
2405 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", AT
, sreg
,
2407 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2408 likely
? "beql" : "beq",
2415 if (sreg
== 0 || imm_expr
.X_add_number
== -1)
2417 imm_expr
.X_add_number
++;
2421 if (mask
== M_BGEUL_I
)
2423 if (imm_expr
.X_add_number
== 0)
2425 if (imm_expr
.X_add_number
== 1)
2427 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2428 likely
? "bnel" : "bne",
2432 set_at (&icnt
, sreg
, 1);
2433 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2434 likely
? "beql" : "beq",
2443 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2444 likely
? "bgtzl" : "bgtz",
2450 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2451 likely
? "bltzl" : "bltz",
2455 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", AT
, treg
, sreg
);
2456 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2457 likely
? "bnel" : "bne",
2466 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2467 likely
? "bnel" : "bne",
2473 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", AT
, treg
,
2475 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2476 likely
? "bnel" : "bne",
2485 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2486 likely
? "blezl" : "blez",
2492 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2493 likely
? "bgezl" : "bgez",
2497 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", AT
, treg
, sreg
);
2498 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2499 likely
? "beql" : "beq",
2506 maxnum
= 0x7fffffff;
2514 if (imm_expr
.X_add_number
>= maxnum
2515 && (mips_isa
< 3 || sizeof (maxnum
) > 4))
2517 imm_expr
.X_add_number
++;
2521 if (mask
== M_BLTL_I
)
2523 if (imm_expr
.X_add_number
== 0)
2525 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2526 likely
? "bltzl" : "bltz",
2530 if (imm_expr
.X_add_number
== 1)
2532 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2533 likely
? "blezl" : "blez",
2537 set_at (&icnt
, sreg
, 0);
2538 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2539 likely
? "bnel" : "bne",
2548 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2549 likely
? "beql" : "beq",
2555 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", AT
, treg
,
2557 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2558 likely
? "beql" : "beq",
2565 if (sreg
== 0 || imm_expr
.X_add_number
== -1)
2567 imm_expr
.X_add_number
++;
2571 if (mask
== M_BLTUL_I
)
2573 if (imm_expr
.X_add_number
== 0)
2575 if (imm_expr
.X_add_number
== 1)
2577 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2578 likely
? "beql" : "beq",
2582 set_at (&icnt
, sreg
, 1);
2583 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2584 likely
? "bnel" : "bne",
2593 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2594 likely
? "bltzl" : "bltz",
2600 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2601 likely
? "bgtzl" : "bgtz",
2605 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", AT
, sreg
, treg
);
2606 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2607 likely
? "bnel" : "bne",
2618 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2619 likely
? "bnel" : "bne",
2623 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", AT
, sreg
,
2625 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2626 likely
? "bnel" : "bne",
2642 as_warn ("Divide by zero.");
2644 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", 0, 0);
2646 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 7);
2650 mips_emit_delays ();
2652 mips_any_noreorder
= 1;
2653 macro_build ((char *) NULL
, &icnt
, NULL
,
2654 dbl
? "ddiv" : "div",
2655 "z,s,t", sreg
, treg
);
2657 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", treg
, 0);
2660 expr1
.X_add_number
= 8;
2661 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", treg
, 0);
2662 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
2663 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 7);
2665 expr1
.X_add_number
= -1;
2666 macro_build ((char *) NULL
, &icnt
, &expr1
,
2667 dbl
? "daddiu" : "addiu",
2668 "t,r,j", AT
, 0, (int) BFD_RELOC_LO16
);
2669 expr1
.X_add_number
= mips_trap
? (dbl
? 12 : 8) : (dbl
? 20 : 16);
2670 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", treg
, AT
);
2673 expr1
.X_add_number
= 1;
2674 macro_build ((char *) NULL
, &icnt
, &expr1
, "daddiu", "t,r,j", AT
, 0,
2675 (int) BFD_RELOC_LO16
);
2676 macro_build ((char *) NULL
, &icnt
, NULL
, "dsll32", "d,w,<", AT
, AT
,
2681 expr1
.X_add_number
= 0x80000000;
2682 macro_build ((char *) NULL
, &icnt
, &expr1
, "lui", "t,u", AT
,
2683 (int) BFD_RELOC_HI16
);
2686 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", sreg
, AT
);
2689 expr1
.X_add_number
= 8;
2690 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", sreg
, AT
);
2691 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
2692 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 6);
2695 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d", dreg
);
2734 if (imm_expr
.X_add_number
== 0)
2736 as_warn ("Divide by zero.");
2738 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", 0, 0);
2740 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 7);
2743 if (imm_expr
.X_add_number
== 1)
2745 if (strcmp (s2
, "mflo") == 0)
2746 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
,
2749 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
, 0);
2752 if (imm_expr
.X_add_number
== -1
2753 && s
[strlen (s
) - 1] != 'u')
2755 if (strcmp (s2
, "mflo") == 0)
2758 macro_build ((char *) NULL
, &icnt
, NULL
, "dneg", "d,w", dreg
,
2761 macro_build ((char *) NULL
, &icnt
, NULL
, "neg", "d,w", dreg
,
2765 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
, 0);
2769 load_register (&icnt
, AT
, &imm_expr
, dbl
);
2770 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "z,s,t", sreg
, AT
);
2771 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "d", dreg
);
2790 mips_emit_delays ();
2792 mips_any_noreorder
= 1;
2793 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "z,s,t", sreg
, treg
);
2795 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", treg
, 0);
2798 expr1
.X_add_number
= 8;
2799 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", treg
, 0);
2800 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
2801 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 7);
2804 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "d", dreg
);
2810 /* Load the address of a symbol into a register. If breg is not
2811 zero, we then add a base register to it. */
2813 /* When generating embedded PIC code, we permit expressions of
2816 where bar is an address in the .text section. These are used
2817 when getting the addresses of functions. We don't permit
2818 X_add_number to be non-zero, because if the symbol is
2819 external the relaxing code needs to know that any addend is
2820 purely the offset to X_op_symbol. */
2821 if (mips_pic
== EMBEDDED_PIC
2822 && offset_expr
.X_op
== O_subtract
2823 && now_seg
== text_section
2824 && (offset_expr
.X_op_symbol
->sy_value
.X_op
== O_constant
2825 ? S_GET_SEGMENT (offset_expr
.X_op_symbol
) == text_section
2826 : (offset_expr
.X_op_symbol
->sy_value
.X_op
== O_symbol
2827 && (S_GET_SEGMENT (offset_expr
.X_op_symbol
2828 ->sy_value
.X_add_symbol
)
2831 && offset_expr
.X_add_number
== 0)
2833 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
2834 treg
, (int) BFD_RELOC_PCREL_HI16_S
);
2835 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2836 mips_isa
< 3 ? "addiu" : "daddiu",
2837 "t,r,j", treg
, treg
, (int) BFD_RELOC_PCREL_LO16
);
2841 if (offset_expr
.X_op
!= O_symbol
2842 && offset_expr
.X_op
!= O_constant
)
2844 as_bad ("expression too complex");
2845 offset_expr
.X_op
= O_constant
;
2859 if (offset_expr
.X_op
== O_constant
)
2860 load_register (&icnt
, tempreg
, &offset_expr
, dbl
);
2861 else if (mips_pic
== NO_PIC
)
2863 /* If this is a reference to an GP relative symbol, we want
2864 addiu $tempreg,$gp,<sym> (BFD_RELOC_MIPS_GPREL)
2866 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
2867 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
2868 If we have a constant, we need two instructions anyhow,
2869 so we may as well always use the latter form. */
2870 if ((valueT
) offset_expr
.X_add_number
>= MAX_GPREL_OFFSET
2871 || nopic_need_relax (offset_expr
.X_add_symbol
))
2876 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2877 mips_isa
< 3 ? "addiu" : "daddiu",
2878 "t,r,j", tempreg
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
2879 p
= frag_var (rs_machine_dependent
, 8, 0,
2880 RELAX_ENCODE (4, 8, 0, 4, 0,
2881 mips_warn_about_macros
),
2882 offset_expr
.X_add_symbol
, (long) 0,
2885 macro_build_lui (p
, &icnt
, &offset_expr
, tempreg
);
2888 macro_build (p
, &icnt
, &offset_expr
,
2889 mips_isa
< 3 ? "addiu" : "daddiu",
2890 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
2892 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
2894 /* If this is a reference to an external symbol, and there
2895 is no constant, we want
2896 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
2897 For a local symbol, we want
2898 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
2900 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
2902 If we have a small constant, and this is a reference to
2903 an external symbol, we want
2904 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
2906 addiu $tempreg,$tempreg,<constant>
2907 For a local symbol, we want the same instruction
2908 sequence, but we output a BFD_RELOC_LO16 reloc on the
2911 If we have a large constant, and this is a reference to
2912 an external symbol, we want
2913 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
2914 lui $at,<hiconstant>
2915 addiu $at,$at,<loconstant>
2916 addu $tempreg,$tempreg,$at
2917 For a local symbol, we want the same instruction
2918 sequence, but we output a BFD_RELOC_LO16 reloc on the
2919 addiu instruction. */
2920 expr1
.X_add_number
= offset_expr
.X_add_number
;
2921 offset_expr
.X_add_number
= 0;
2923 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2925 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
2926 if (expr1
.X_add_number
== 0)
2934 /* We're going to put in an addu instruction using
2935 tempreg, so we may as well insert the nop right
2937 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
2941 p
= frag_var (rs_machine_dependent
, 8 - off
, 0,
2942 RELAX_ENCODE (0, 8 - off
, -4 - off
, 4 - off
, 0,
2944 ? mips_warn_about_macros
2946 offset_expr
.X_add_symbol
, (long) 0,
2950 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
2953 macro_build (p
, &icnt
, &expr1
,
2954 mips_isa
< 3 ? "addiu" : "daddiu",
2955 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
2956 /* FIXME: If breg == 0, and the next instruction uses
2957 $tempreg, then if this variant case is used an extra
2958 nop will be generated. */
2960 else if (expr1
.X_add_number
>= -0x8000
2961 && expr1
.X_add_number
< 0x8000)
2963 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
2965 macro_build ((char *) NULL
, &icnt
, &expr1
,
2966 mips_isa
< 3 ? "addiu" : "daddiu",
2967 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
2968 (void) frag_var (rs_machine_dependent
, 0, 0,
2969 RELAX_ENCODE (0, 0, -12, -4, 0, 0),
2970 offset_expr
.X_add_symbol
, (long) 0,
2977 /* If we are going to add in a base register, and the
2978 target register and the base register are the same,
2979 then we are using AT as a temporary register. Since
2980 we want to load the constant into AT, we add our
2981 current AT (from the global offset table) and the
2982 register into the register now, and pretend we were
2983 not using a base register. */
2988 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
2990 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
2991 mips_isa
< 3 ? "addu" : "daddu",
2992 "d,v,t", treg
, AT
, breg
);
2998 /* Set mips_optimize around the lui instruction to avoid
2999 inserting an unnecessary nop after the lw. */
3000 hold_mips_optimize
= mips_optimize
;
3002 macro_build_lui ((char *) NULL
, &icnt
, &expr1
, AT
);
3003 mips_optimize
= hold_mips_optimize
;
3005 macro_build ((char *) NULL
, &icnt
, &expr1
,
3006 mips_isa
< 3 ? "addiu" : "daddiu",
3007 "t,r,j", AT
, AT
, (int) BFD_RELOC_LO16
);
3008 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3009 mips_isa
< 3 ? "addu" : "daddu",
3010 "d,v,t", tempreg
, tempreg
, AT
);
3011 (void) frag_var (rs_machine_dependent
, 0, 0,
3012 RELAX_ENCODE (0, 0, -16 + off1
, -8, 0, 0),
3013 offset_expr
.X_add_symbol
, (long) 0,
3018 else if (mips_pic
== SVR4_PIC
)
3022 /* This is the large GOT case. If this is a reference to an
3023 external symbol, and there is no constant, we want
3024 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
3025 addu $tempreg,$tempreg,$gp
3026 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
3027 For a local symbol, we want
3028 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3030 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
3032 If we have a small constant, and this is a reference to
3033 an external symbol, we want
3034 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
3035 addu $tempreg,$tempreg,$gp
3036 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
3038 addiu $tempreg,$tempreg,<constant>
3039 For a local symbol, we want
3040 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3042 addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16)
3044 If we have a large constant, and this is a reference to
3045 an external symbol, we want
3046 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
3047 addu $tempreg,$tempreg,$gp
3048 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
3049 lui $at,<hiconstant>
3050 addiu $at,$at,<loconstant>
3051 addu $tempreg,$tempreg,$at
3052 For a local symbol, we want
3053 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3054 lui $at,<hiconstant>
3055 addiu $at,$at,<loconstant> (BFD_RELOC_LO16)
3056 addu $tempreg,$tempreg,$at
3058 expr1
.X_add_number
= offset_expr
.X_add_number
;
3059 offset_expr
.X_add_number
= 0;
3061 if (reg_needs_delay (GP
))
3065 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
3066 tempreg
, (int) BFD_RELOC_MIPS_GOT_HI16
);
3067 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3068 mips_isa
< 3 ? "addu" : "daddu",
3069 "d,v,t", tempreg
, tempreg
, GP
);
3070 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3072 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT_LO16
,
3074 if (expr1
.X_add_number
== 0)
3082 /* We're going to put in an addu instruction using
3083 tempreg, so we may as well insert the nop right
3085 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3090 p
= frag_var (rs_machine_dependent
, 12 + gpdel
, 0,
3091 RELAX_ENCODE (12 + off
, 12 + gpdel
, gpdel
,
3094 ? mips_warn_about_macros
3096 offset_expr
.X_add_symbol
, (long) 0,
3099 else if (expr1
.X_add_number
>= -0x8000
3100 && expr1
.X_add_number
< 0x8000)
3102 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3104 macro_build ((char *) NULL
, &icnt
, &expr1
,
3105 mips_isa
< 3 ? "addiu" : "daddiu",
3106 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
3108 p
= frag_var (rs_machine_dependent
, 12 + gpdel
, 0,
3109 RELAX_ENCODE (20, 12 + gpdel
, gpdel
, 8 + gpdel
, 0,
3111 ? mips_warn_about_macros
3113 offset_expr
.X_add_symbol
, (long) 0,
3120 /* If we are going to add in a base register, and the
3121 target register and the base register are the same,
3122 then we are using AT as a temporary register. Since
3123 we want to load the constant into AT, we add our
3124 current AT (from the global offset table) and the
3125 register into the register now, and pretend we were
3126 not using a base register. */
3134 assert (tempreg
== AT
);
3135 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3137 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3138 mips_isa
< 3 ? "addu" : "daddu",
3139 "d,v,t", treg
, AT
, breg
);
3144 /* Set mips_optimize around the lui instruction to avoid
3145 inserting an unnecessary nop after the lw. */
3146 hold_mips_optimize
= mips_optimize
;
3148 macro_build_lui ((char *) NULL
, &icnt
, &expr1
, AT
);
3149 mips_optimize
= hold_mips_optimize
;
3151 macro_build ((char *) NULL
, &icnt
, &expr1
,
3152 mips_isa
< 3 ? "addiu" : "daddiu",
3153 "t,r,j", AT
, AT
, (int) BFD_RELOC_LO16
);
3154 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3155 mips_isa
< 3 ? "addu" : "daddu",
3156 "d,v,t", dreg
, dreg
, AT
);
3158 p
= frag_var (rs_machine_dependent
, 16 + gpdel
+ adj
, 0,
3159 RELAX_ENCODE (24 + adj
, 16 + gpdel
+ adj
, gpdel
,
3162 ? mips_warn_about_macros
3164 offset_expr
.X_add_symbol
, (long) 0,
3172 /* This is needed because this instruction uses $gp, but
3173 the first instruction on the main stream does not. */
3174 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
3177 macro_build (p
, &icnt
, &offset_expr
,
3179 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
3181 if (expr1
.X_add_number
>= -0x8000
3182 && expr1
.X_add_number
< 0x8000)
3184 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
3186 macro_build (p
, &icnt
, &expr1
,
3187 mips_isa
< 3 ? "addiu" : "daddiu",
3188 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
3189 /* FIXME: If add_number is 0, and there was no base
3190 register, the external symbol case ended with a load,
3191 so if the symbol turns out to not be external, and
3192 the next instruction uses tempreg, an unnecessary nop
3193 will be inserted. */
3199 /* We must add in the base register now, as in the
3200 external symbol case. */
3201 assert (tempreg
== AT
);
3202 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
3204 macro_build (p
, &icnt
, (expressionS
*) NULL
,
3205 mips_isa
< 3 ? "addu" : "daddu",
3206 "d,v,t", treg
, AT
, breg
);
3209 /* We set breg to 0 because we have arranged to add
3210 it in in both cases. */
3214 macro_build_lui (p
, &icnt
, &expr1
, AT
);
3216 macro_build (p
, &icnt
, &expr1
,
3217 mips_isa
< 3 ? "addiu" : "daddiu",
3218 "t,r,j", AT
, AT
, (int) BFD_RELOC_LO16
);
3220 macro_build (p
, &icnt
, (expressionS
*) NULL
,
3221 mips_isa
< 3 ? "addu" : "daddu",
3222 "d,v,t", tempreg
, tempreg
, AT
);
3226 else if (mips_pic
== EMBEDDED_PIC
)
3229 addiu $tempreg,$gp,<sym> (BFD_RELOC_MIPS_GPREL)
3231 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3232 mips_isa
< 3 ? "addiu" : "daddiu",
3233 "t,r,j", tempreg
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
3239 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3240 mips_isa
< 3 ? "addu" : "daddu",
3241 "d,v,t", treg
, tempreg
, breg
);
3249 /* The j instruction may not be used in PIC code, since it
3250 requires an absolute address. We convert it to a b
3252 if (mips_pic
== NO_PIC
)
3253 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "j", "a");
3255 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "b", "p");
3258 /* The jal instructions must be handled as macros because when
3259 generating PIC code they expand to multi-instruction
3260 sequences. Normally they are simple instructions. */
3265 if (mips_pic
== NO_PIC
3266 || mips_pic
== EMBEDDED_PIC
)
3267 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "jalr",
3269 else if (mips_pic
== SVR4_PIC
)
3271 if (sreg
!= PIC_CALL_REG
)
3272 as_warn ("MIPS PIC call to register other than $25");
3274 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "jalr",
3276 if (mips_cprestore_offset
< 0)
3277 as_warn ("No .cprestore pseudo-op used in PIC code");
3280 expr1
.X_add_number
= mips_cprestore_offset
;
3281 macro_build ((char *) NULL
, &icnt
, &expr1
,
3282 mips_isa
< 3 ? "lw" : "ld",
3283 "t,o(b)", GP
, (int) BFD_RELOC_LO16
, mips_frame_reg
);
3292 if (mips_pic
== NO_PIC
)
3293 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "jal", "a");
3294 else if (mips_pic
== SVR4_PIC
)
3296 /* If this is a reference to an external symbol, and we are
3297 using a small GOT, we want
3298 lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
3302 lw $gp,cprestore($sp)
3303 The cprestore value is set using the .cprestore
3304 pseudo-op. If we are using a big GOT, we want
3305 lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16)
3307 lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16)
3311 lw $gp,cprestore($sp)
3312 If the symbol is not external, we want
3313 lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3315 addiu $25,$25,<sym> (BFD_RELOC_LO16)
3318 lw $gp,cprestore($sp) */
3322 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3323 mips_isa
< 3 ? "lw" : "ld",
3324 "t,o(b)", PIC_CALL_REG
,
3325 (int) BFD_RELOC_MIPS_CALL16
, GP
);
3326 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3328 p
= frag_var (rs_machine_dependent
, 4, 0,
3329 RELAX_ENCODE (0, 4, -8, 0, 0, 0),
3330 offset_expr
.X_add_symbol
, (long) 0, (char *) NULL
);
3336 if (reg_needs_delay (GP
))
3340 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
3341 PIC_CALL_REG
, (int) BFD_RELOC_MIPS_CALL_HI16
);
3342 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3343 mips_isa
< 3 ? "addu" : "daddu",
3344 "d,v,t", PIC_CALL_REG
, PIC_CALL_REG
, GP
);
3345 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3346 mips_isa
< 3 ? "lw" : "ld",
3347 "t,o(b)", PIC_CALL_REG
,
3348 (int) BFD_RELOC_MIPS_CALL_LO16
, PIC_CALL_REG
);
3349 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3351 p
= frag_var (rs_machine_dependent
, 12 + gpdel
, 0,
3352 RELAX_ENCODE (16, 12 + gpdel
, gpdel
, 8 + gpdel
,
3354 offset_expr
.X_add_symbol
, (long) 0, (char *) NULL
);
3357 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
3360 macro_build (p
, &icnt
, &offset_expr
,
3361 mips_isa
< 3 ? "lw" : "ld",
3362 "t,o(b)", PIC_CALL_REG
,
3363 (int) BFD_RELOC_MIPS_GOT16
, GP
);
3365 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
3368 macro_build (p
, &icnt
, &offset_expr
,
3369 mips_isa
< 3 ? "addiu" : "daddiu",
3370 "t,r,j", PIC_CALL_REG
, PIC_CALL_REG
,
3371 (int) BFD_RELOC_LO16
);
3372 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3373 "jalr", "s", PIC_CALL_REG
);
3374 if (mips_cprestore_offset
< 0)
3375 as_warn ("No .cprestore pseudo-op used in PIC code");
3379 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3381 expr1
.X_add_number
= mips_cprestore_offset
;
3382 macro_build ((char *) NULL
, &icnt
, &expr1
,
3383 mips_isa
< 3 ? "lw" : "ld",
3384 "t,o(b)", GP
, (int) BFD_RELOC_LO16
,
3388 else if (mips_pic
== EMBEDDED_PIC
)
3390 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "bal", "p");
3391 /* The linker may expand the call to a longer sequence which
3392 uses $at, so we must break rather than return. */
3468 if (breg
== treg
|| coproc
|| lr
)
3537 if (mask
== M_LWC1_AB
3538 || mask
== M_SWC1_AB
3539 || mask
== M_LDC1_AB
3540 || mask
== M_SDC1_AB
3549 if (offset_expr
.X_op
!= O_constant
3550 && offset_expr
.X_op
!= O_symbol
)
3552 as_bad ("expression too complex");
3553 offset_expr
.X_op
= O_constant
;
3556 /* A constant expression in PIC code can be handled just as it
3557 is in non PIC code. */
3558 if (mips_pic
== NO_PIC
3559 || offset_expr
.X_op
== O_constant
)
3561 /* If this is a reference to a GP relative symbol, and there
3562 is no base register, we want
3563 <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL)
3564 Otherwise, if there is no base register, we want
3565 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
3566 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
3567 If we have a constant, we need two instructions anyhow,
3568 so we always use the latter form.
3570 If we have a base register, and this is a reference to a
3571 GP relative symbol, we want
3572 addu $tempreg,$breg,$gp
3573 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GPREL)
3575 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
3576 addu $tempreg,$tempreg,$breg
3577 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
3578 With a constant we always use the latter case. */
3581 if ((valueT
) offset_expr
.X_add_number
>= MAX_GPREL_OFFSET
3582 || nopic_need_relax (offset_expr
.X_add_symbol
))
3587 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
3588 treg
, (int) BFD_RELOC_MIPS_GPREL
, GP
);
3589 p
= frag_var (rs_machine_dependent
, 8, 0,
3590 RELAX_ENCODE (4, 8, 0, 4, 0,
3591 (mips_warn_about_macros
3592 || (used_at
&& mips_noat
))),
3593 offset_expr
.X_add_symbol
, (long) 0,
3597 macro_build_lui (p
, &icnt
, &offset_expr
, tempreg
);
3600 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
, treg
,
3601 (int) BFD_RELOC_LO16
, tempreg
);
3605 if ((valueT
) offset_expr
.X_add_number
>= MAX_GPREL_OFFSET
3606 || nopic_need_relax (offset_expr
.X_add_symbol
))
3611 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3612 mips_isa
< 3 ? "addu" : "daddu",
3613 "d,v,t", tempreg
, breg
, GP
);
3614 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
3615 treg
, (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
3616 p
= frag_var (rs_machine_dependent
, 12, 0,
3617 RELAX_ENCODE (8, 12, 0, 8, 0, 0),
3618 offset_expr
.X_add_symbol
, (long) 0,
3621 macro_build_lui (p
, &icnt
, &offset_expr
, tempreg
);
3624 macro_build (p
, &icnt
, (expressionS
*) NULL
,
3625 mips_isa
< 3 ? "addu" : "daddu",
3626 "d,v,t", tempreg
, tempreg
, breg
);
3629 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
, treg
,
3630 (int) BFD_RELOC_LO16
, tempreg
);
3633 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
3635 /* If this is a reference to an external symbol, we want
3636 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3638 <op> $treg,0($tempreg)
3640 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3642 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
3643 <op> $treg,0($tempreg)
3644 If there is a base register, we add it to $tempreg before
3645 the <op>. If there is a constant, we stick it in the
3646 <op> instruction. We don't handle constants larger than
3647 16 bits, because we have no way to load the upper 16 bits
3648 (actually, we could handle them for the subset of cases
3649 in which we are not using $at). */
3650 assert (offset_expr
.X_op
== O_symbol
);
3651 expr1
.X_add_number
= offset_expr
.X_add_number
;
3652 offset_expr
.X_add_number
= 0;
3653 if (expr1
.X_add_number
< -0x8000
3654 || expr1
.X_add_number
>= 0x8000)
3655 as_bad ("PIC code offset overflow (max 16 signed bits)");
3657 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3658 mips_isa
< 3 ? "lw" : "ld",
3659 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
3660 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
3661 p
= frag_var (rs_machine_dependent
, 4, 0,
3662 RELAX_ENCODE (0, 4, -8, 0, 0, 0),
3663 offset_expr
.X_add_symbol
, (long) 0,
3665 macro_build (p
, &icnt
, &offset_expr
,
3666 mips_isa
< 3 ? "addiu" : "daddiu",
3667 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
3669 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3670 mips_isa
< 3 ? "addu" : "daddu",
3671 "d,v,t", tempreg
, tempreg
, breg
);
3672 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
, treg
,
3673 (int) BFD_RELOC_LO16
, tempreg
);
3675 else if (mips_pic
== SVR4_PIC
)
3679 /* If this is a reference to an external symbol, we want
3680 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
3681 addu $tempreg,$tempreg,$gp
3682 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
3683 <op> $treg,0($tempreg)
3685 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3687 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
3688 <op> $treg,0($tempreg)
3689 If there is a base register, we add it to $tempreg before
3690 the <op>. If there is a constant, we stick it in the
3691 <op> instruction. We don't handle constants larger than
3692 16 bits, because we have no way to load the upper 16 bits
3693 (actually, we could handle them for the subset of cases
3694 in which we are not using $at). */
3695 assert (offset_expr
.X_op
== O_symbol
);
3696 expr1
.X_add_number
= offset_expr
.X_add_number
;
3697 offset_expr
.X_add_number
= 0;
3698 if (expr1
.X_add_number
< -0x8000
3699 || expr1
.X_add_number
>= 0x8000)
3700 as_bad ("PIC code offset overflow (max 16 signed bits)");
3701 if (reg_needs_delay (GP
))
3706 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
3707 tempreg
, (int) BFD_RELOC_MIPS_GOT_HI16
);
3708 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3709 mips_isa
< 3 ? "addu" : "daddu",
3710 "d,v,t", tempreg
, tempreg
, GP
);
3711 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3712 mips_isa
< 3 ? "lw" : "ld",
3713 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT_LO16
,
3715 p
= frag_var (rs_machine_dependent
, 12 + gpdel
, 0,
3716 RELAX_ENCODE (12, 12 + gpdel
, gpdel
, 8 + gpdel
, 0, 0),
3717 offset_expr
.X_add_symbol
, (long) 0, (char *) NULL
);
3720 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
3723 macro_build (p
, &icnt
, &offset_expr
,
3724 mips_isa
< 3 ? "lw" : "ld",
3725 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
3727 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
3729 macro_build (p
, &icnt
, &offset_expr
,
3730 mips_isa
< 3 ? "addiu" : "daddiu",
3731 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
3733 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3734 mips_isa
< 3 ? "addu" : "daddu",
3735 "d,v,t", tempreg
, tempreg
, breg
);
3736 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
, treg
,
3737 (int) BFD_RELOC_LO16
, tempreg
);
3739 else if (mips_pic
== EMBEDDED_PIC
)
3741 /* If there is no base register, we want
3742 <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL)
3743 If there is a base register, we want
3744 addu $tempreg,$breg,$gp
3745 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GPREL)
3747 assert (offset_expr
.X_op
== O_symbol
);
3750 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
3751 treg
, (int) BFD_RELOC_MIPS_GPREL
, GP
);
3756 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3757 mips_isa
< 3 ? "addu" : "daddu",
3758 "d,v,t", tempreg
, breg
, GP
);
3759 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
3760 treg
, (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
3773 load_register (&icnt
, treg
, &imm_expr
, 0);
3777 load_register (&icnt
, treg
, &imm_expr
, 1);
3781 if (imm_expr
.X_op
== O_constant
)
3783 load_register (&icnt
, AT
, &imm_expr
, 0);
3784 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3785 "mtc1", "t,G", AT
, treg
);
3790 assert (offset_expr
.X_op
== O_symbol
3791 && strcmp (segment_name (S_GET_SEGMENT
3792 (offset_expr
.X_add_symbol
)),
3794 && offset_expr
.X_add_number
== 0);
3795 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lwc1", "T,o(b)",
3796 treg
, (int) BFD_RELOC_MIPS_LITERAL
, GP
);
3801 /* We know that sym is in the .rdata section. First we get the
3802 upper 16 bits of the address. */
3803 if (mips_pic
== NO_PIC
)
3805 /* FIXME: This won't work for a 64 bit address. */
3806 macro_build_lui ((char *) NULL
, &icnt
, &offset_expr
, AT
);
3808 else if (mips_pic
== SVR4_PIC
)
3810 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3811 mips_isa
< 3 ? "lw" : "ld",
3812 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
3814 else if (mips_pic
== EMBEDDED_PIC
)
3816 /* For embedded PIC we pick up the entire address off $gp in
3817 a single instruction. */
3818 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3819 mips_isa
< 3 ? "addiu" : "daddiu",
3820 "t,r,j", AT
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
3821 offset_expr
.X_op
= O_constant
;
3822 offset_expr
.X_add_number
= 0;
3827 /* Now we load the register(s). */
3829 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "ld", "t,o(b)",
3830 treg
, (int) BFD_RELOC_LO16
, AT
);
3833 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lw", "t,o(b)",
3834 treg
, (int) BFD_RELOC_LO16
, AT
);
3837 /* FIXME: How in the world do we deal with the possible
3839 offset_expr
.X_add_number
+= 4;
3840 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lw", "t,o(b)",
3841 treg
+ 1, (int) BFD_RELOC_LO16
, AT
);
3845 /* To avoid confusion in tc_gen_reloc, we must ensure that this
3846 does not become a variant frag. */
3847 frag_wane (frag_now
);
3853 assert (offset_expr
.X_op
== O_symbol
3854 && offset_expr
.X_add_number
== 0);
3855 s
= segment_name (S_GET_SEGMENT (offset_expr
.X_add_symbol
));
3856 if (strcmp (s
, ".lit8") == 0)
3860 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "ldc1",
3861 "T,o(b)", treg
, (int) BFD_RELOC_MIPS_LITERAL
, GP
);
3865 r
= BFD_RELOC_MIPS_LITERAL
;
3870 assert (strcmp (s
, RDATA_SECTION_NAME
) == 0);
3871 if (mips_pic
== SVR4_PIC
)
3872 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3873 mips_isa
< 3 ? "lw" : "ld",
3874 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
3877 /* FIXME: This won't work for a 64 bit address. */
3878 macro_build_lui ((char *) NULL
, &icnt
, &offset_expr
, AT
);
3883 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "ldc1",
3884 "T,o(b)", treg
, (int) BFD_RELOC_LO16
, AT
);
3886 /* To avoid confusion in tc_gen_reloc, we must ensure
3887 that this does not become a variant frag. */
3888 frag_wane (frag_now
);
3899 /* Even on a big endian machine $fn comes before $fn+1. We have
3900 to adjust when loading from memory. */
3903 assert (mips_isa
< 2);
3904 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lwc1", "T,o(b)",
3905 byte_order
== LITTLE_ENDIAN
? treg
: treg
+ 1,
3907 /* FIXME: A possible overflow which I don't know how to deal
3909 offset_expr
.X_add_number
+= 4;
3910 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lwc1", "T,o(b)",
3911 byte_order
== LITTLE_ENDIAN
? treg
+ 1 : treg
,
3914 /* To avoid confusion in tc_gen_reloc, we must ensure that this
3915 does not become a variant frag. */
3916 frag_wane (frag_now
);
3925 * The MIPS assembler seems to check for X_add_number not
3926 * being double aligned and generating:
3929 * addiu at,at,%lo(foo+1)
3932 * But, the resulting address is the same after relocation so why
3933 * generate the extra instruction?
3980 if (offset_expr
.X_op
!= O_symbol
3981 && offset_expr
.X_op
!= O_constant
)
3983 as_bad ("expression too complex");
3984 offset_expr
.X_op
= O_constant
;
3987 /* Even on a big endian machine $fn comes before $fn+1. We have
3988 to adjust when loading from memory. We set coproc if we must
3989 load $fn+1 first. */
3990 if (byte_order
== LITTLE_ENDIAN
)
3993 if (mips_pic
== NO_PIC
3994 || offset_expr
.X_op
== O_constant
)
3996 /* If this is a reference to a GP relative symbol, we want
3997 <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL)
3998 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_MIPS_GPREL)
3999 If we have a base register, we use this
4001 <op> $treg,<sym>($at) (BFD_RELOC_MIPS_GPREL)
4002 <op> $treg+1,<sym>+4($at) (BFD_RELOC_MIPS_GPREL)
4003 If this is not a GP relative symbol, we want
4004 lui $at,<sym> (BFD_RELOC_HI16_S)
4005 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
4006 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
4007 If there is a base register, we add it to $at after the
4008 lui instruction. If there is a constant, we always use
4010 if ((valueT
) offset_expr
.X_add_number
>= MAX_GPREL_OFFSET
4011 || nopic_need_relax (offset_expr
.X_add_symbol
))
4030 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4031 mips_isa
< 3 ? "addu" : "daddu",
4032 "d,v,t", AT
, breg
, GP
);
4038 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
4039 coproc
? treg
+ 1 : treg
,
4040 (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
4041 offset_expr
.X_add_number
+= 4;
4043 /* Set mips_optimize to 2 to avoid inserting an
4045 hold_mips_optimize
= mips_optimize
;
4047 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
4048 coproc
? treg
: treg
+ 1,
4049 (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
4050 mips_optimize
= hold_mips_optimize
;
4052 p
= frag_var (rs_machine_dependent
, 12 + off
, 0,
4053 RELAX_ENCODE (8 + off
, 12 + off
, 0, 4 + off
, 1,
4054 used_at
&& mips_noat
),
4055 offset_expr
.X_add_symbol
, (long) 0,
4058 /* We just generated two relocs. When tc_gen_reloc
4059 handles this case, it will skip the first reloc and
4060 handle the second. The second reloc already has an
4061 extra addend of 4, which we added above. We must
4062 subtract it out, and then subtract another 4 to make
4063 the first reloc come out right. The second reloc
4064 will come out right because we are going to add 4 to
4065 offset_expr when we build its instruction below. */
4066 offset_expr
.X_add_number
-= 8;
4067 offset_expr
.X_op
= O_constant
;
4069 macro_build_lui (p
, &icnt
, &offset_expr
, AT
);
4074 macro_build (p
, &icnt
, (expressionS
*) NULL
,
4075 mips_isa
< 3 ? "addu" : "daddu",
4076 "d,v,t", AT
, breg
, AT
);
4080 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
,
4081 coproc
? treg
+ 1 : treg
,
4082 (int) BFD_RELOC_LO16
, AT
);
4085 /* FIXME: How do we handle overflow here? */
4086 offset_expr
.X_add_number
+= 4;
4087 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
,
4088 coproc
? treg
: treg
+ 1,
4089 (int) BFD_RELOC_LO16
, AT
);
4091 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
4095 /* If this is a reference to an external symbol, we want
4096 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4101 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4103 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
4104 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
4105 If there is a base register we add it to $at before the
4106 lwc1 instructions. If there is a constant we include it
4107 in the lwc1 instructions. */
4109 expr1
.X_add_number
= offset_expr
.X_add_number
;
4110 offset_expr
.X_add_number
= 0;
4111 if (expr1
.X_add_number
< -0x8000
4112 || expr1
.X_add_number
>= 0x8000 - 4)
4113 as_bad ("PIC code offset overflow (max 16 signed bits)");
4118 frag_grow (24 + off
);
4119 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4120 mips_isa
< 3 ? "lw" : "ld",
4121 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
4122 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
4124 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4125 mips_isa
< 3 ? "addu" : "daddu",
4126 "d,v,t", AT
, breg
, AT
);
4127 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
4128 coproc
? treg
+ 1 : treg
,
4129 (int) BFD_RELOC_LO16
, AT
);
4130 expr1
.X_add_number
+= 4;
4132 /* Set mips_optimize to 2 to avoid inserting an undesired
4134 hold_mips_optimize
= mips_optimize
;
4136 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
4137 coproc
? treg
: treg
+ 1,
4138 (int) BFD_RELOC_LO16
, AT
);
4139 mips_optimize
= hold_mips_optimize
;
4141 (void) frag_var (rs_machine_dependent
, 0, 0,
4142 RELAX_ENCODE (0, 0, -16 - off
, -8, 1, 0),
4143 offset_expr
.X_add_symbol
, (long) 0,
4146 else if (mips_pic
== SVR4_PIC
)
4150 /* If this is a reference to an external symbol, we want
4151 lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16)
4153 lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16)
4158 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4160 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
4161 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
4162 If there is a base register we add it to $at before the
4163 lwc1 instructions. If there is a constant we include it
4164 in the lwc1 instructions. */
4166 expr1
.X_add_number
= offset_expr
.X_add_number
;
4167 offset_expr
.X_add_number
= 0;
4168 if (expr1
.X_add_number
< -0x8000
4169 || expr1
.X_add_number
>= 0x8000 - 4)
4170 as_bad ("PIC code offset overflow (max 16 signed bits)");
4171 if (reg_needs_delay (GP
))
4180 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
4181 AT
, (int) BFD_RELOC_MIPS_GOT_HI16
);
4182 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4183 mips_isa
< 3 ? "addu" : "daddu",
4184 "d,v,t", AT
, AT
, GP
);
4185 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4186 mips_isa
< 3 ? "lw" : "ld",
4187 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT_LO16
, AT
);
4188 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
4190 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4191 mips_isa
< 3 ? "addu" : "daddu",
4192 "d,v,t", AT
, breg
, AT
);
4193 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
4194 coproc
? treg
+ 1 : treg
,
4195 (int) BFD_RELOC_LO16
, AT
);
4196 expr1
.X_add_number
+= 4;
4198 /* Set mips_optimize to 2 to avoid inserting an undesired
4200 hold_mips_optimize
= mips_optimize
;
4202 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
4203 coproc
? treg
: treg
+ 1,
4204 (int) BFD_RELOC_LO16
, AT
);
4205 mips_optimize
= hold_mips_optimize
;
4206 expr1
.X_add_number
-= 4;
4208 p
= frag_var (rs_machine_dependent
, 16 + gpdel
+ off
, 0,
4209 RELAX_ENCODE (24 + off
, 16 + gpdel
+ off
, gpdel
,
4210 8 + gpdel
+ off
, 1, 0),
4211 offset_expr
.X_add_symbol
, (long) 0,
4215 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4218 macro_build (p
, &icnt
, &offset_expr
,
4219 mips_isa
< 3 ? "lw" : "ld",
4220 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
4222 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4226 macro_build (p
, &icnt
, (expressionS
*) NULL
,
4227 mips_isa
< 3 ? "addu" : "daddu",
4228 "d,v,t", AT
, breg
, AT
);
4231 macro_build (p
, &icnt
, &expr1
, s
, fmt
,
4232 coproc
? treg
+ 1 : treg
,
4233 (int) BFD_RELOC_LO16
, AT
);
4235 expr1
.X_add_number
+= 4;
4237 /* Set mips_optimize to 2 to avoid inserting an undesired
4239 hold_mips_optimize
= mips_optimize
;
4241 macro_build (p
, &icnt
, &expr1
, s
, fmt
,
4242 coproc
? treg
: treg
+ 1,
4243 (int) BFD_RELOC_LO16
, AT
);
4244 mips_optimize
= hold_mips_optimize
;
4246 else if (mips_pic
== EMBEDDED_PIC
)
4248 /* If there is no base register, we use
4249 <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL)
4250 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_MIPS_GPREL)
4251 If we have a base register, we use
4253 <op> $treg,<sym>($at) (BFD_RELOC_MIPS_GPREL)
4254 <op> $treg+1,<sym>+4($at) (BFD_RELOC_MIPS_GPREL)
4263 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4264 mips_isa
< 3 ? "addu" : "daddu",
4265 "d,v,t", AT
, breg
, GP
);
4270 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
4271 coproc
? treg
+ 1 : treg
,
4272 (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
4273 offset_expr
.X_add_number
+= 4;
4274 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
4275 coproc
? treg
: treg
+ 1,
4276 (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
4292 assert (mips_isa
< 3);
4293 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
4294 (int) BFD_RELOC_LO16
, breg
);
4295 offset_expr
.X_add_number
+= 4;
4296 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
+ 1,
4297 (int) BFD_RELOC_LO16
, breg
);
4299 #ifdef LOSING_COMPILER
4305 as_warn ("Macro used $at after \".set noat\"");
4310 struct mips_cl_insn
*ip
;
4312 register int treg
, sreg
, dreg
, breg
;
4327 bfd_reloc_code_real_type r
;
4330 treg
= (ip
->insn_opcode
>> 16) & 0x1f;
4331 dreg
= (ip
->insn_opcode
>> 11) & 0x1f;
4332 sreg
= breg
= (ip
->insn_opcode
>> 21) & 0x1f;
4333 mask
= ip
->insn_mo
->mask
;
4335 expr1
.X_op
= O_constant
;
4336 expr1
.X_op_symbol
= NULL
;
4337 expr1
.X_add_symbol
= NULL
;
4338 expr1
.X_add_number
= 1;
4342 #endif /* LOSING_COMPILER */
4347 macro_build ((char *) NULL
, &icnt
, NULL
,
4348 dbl
? "dmultu" : "multu",
4350 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
4356 /* The MIPS assembler some times generates shifts and adds. I'm
4357 not trying to be that fancy. GCC should do this for us
4359 load_register (&icnt
, AT
, &imm_expr
, dbl
);
4360 macro_build ((char *) NULL
, &icnt
, NULL
,
4361 dbl
? "dmult" : "mult",
4363 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
4369 mips_emit_delays ();
4371 mips_any_noreorder
= 1;
4372 macro_build ((char *) NULL
, &icnt
, NULL
,
4373 dbl
? "dmult" : "mult",
4375 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
4376 macro_build ((char *) NULL
, &icnt
, NULL
,
4377 dbl
? "dsra32" : "sra",
4378 "d,w,<", dreg
, dreg
, 31);
4379 macro_build ((char *) NULL
, &icnt
, NULL
, "mfhi", "d", AT
);
4381 macro_build ((char *) NULL
, &icnt
, NULL
, "tne", "s,t", dreg
, AT
);
4384 expr1
.X_add_number
= 8;
4385 macro_build ((char *) NULL
, &icnt
, &expr1
, "beq", "s,t,p", dreg
, AT
);
4386 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
4387 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 6);
4390 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
4396 mips_emit_delays ();
4398 mips_any_noreorder
= 1;
4399 macro_build ((char *) NULL
, &icnt
, NULL
,
4400 dbl
? "dmultu" : "multu",
4402 macro_build ((char *) NULL
, &icnt
, NULL
, "mfhi", "d", AT
);
4403 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
4405 macro_build ((char *) NULL
, &icnt
, NULL
, "tne", "s,t", AT
, 0);
4408 expr1
.X_add_number
= 8;
4409 macro_build ((char *) NULL
, &icnt
, &expr1
, "beq", "s,t,p", AT
, 0);
4410 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
4411 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 6);
4417 macro_build ((char *) NULL
, &icnt
, NULL
, "subu", "d,v,t", AT
, 0, treg
);
4418 macro_build ((char *) NULL
, &icnt
, NULL
, "srlv", "d,t,s", AT
, sreg
, AT
);
4419 macro_build ((char *) NULL
, &icnt
, NULL
, "sllv", "d,t,s", dreg
, sreg
,
4421 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
4425 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", AT
, sreg
,
4426 (int) (imm_expr
.X_add_number
& 0x1f));
4427 macro_build ((char *) NULL
, &icnt
, NULL
, "srl", "d,w,<", dreg
, sreg
,
4428 (int) ((0 - imm_expr
.X_add_number
) & 0x1f));
4429 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
4433 macro_build ((char *) NULL
, &icnt
, NULL
, "subu", "d,v,t", AT
, 0, treg
);
4434 macro_build ((char *) NULL
, &icnt
, NULL
, "sllv", "d,t,s", AT
, sreg
, AT
);
4435 macro_build ((char *) NULL
, &icnt
, NULL
, "srlv", "d,t,s", dreg
, sreg
,
4437 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
4441 macro_build ((char *) NULL
, &icnt
, NULL
, "srl", "d,w,<", AT
, sreg
,
4442 (int) (imm_expr
.X_add_number
& 0x1f));
4443 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", dreg
, sreg
,
4444 (int) ((0 - imm_expr
.X_add_number
) & 0x1f));
4445 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
4449 assert (mips_isa
< 2);
4450 /* Even on a big endian machine $fn comes before $fn+1. We have
4451 to adjust when storing to memory. */
4452 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "swc1", "T,o(b)",
4453 byte_order
== LITTLE_ENDIAN
? treg
: treg
+ 1,
4454 (int) BFD_RELOC_LO16
, breg
);
4455 offset_expr
.X_add_number
+= 4;
4456 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "swc1", "T,o(b)",
4457 byte_order
== LITTLE_ENDIAN
? treg
+ 1 : treg
,
4458 (int) BFD_RELOC_LO16
, breg
);
4463 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
4464 treg
, (int) BFD_RELOC_LO16
);
4466 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
4467 sreg
, (int) BFD_RELOC_LO16
);
4470 macro_build ((char *) NULL
, &icnt
, NULL
, "xor", "d,v,t", dreg
,
4472 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
4473 dreg
, (int) BFD_RELOC_LO16
);
4478 if (imm_expr
.X_add_number
== 0)
4480 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
4481 sreg
, (int) BFD_RELOC_LO16
);
4486 as_warn ("Instruction %s: result is always false",
4488 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
, 0);
4491 if (imm_expr
.X_add_number
>= 0 && imm_expr
.X_add_number
< 0x10000)
4493 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "xori", "t,r,i", dreg
,
4494 sreg
, (int) BFD_RELOC_LO16
);
4497 else if (imm_expr
.X_add_number
> -0x8000 && imm_expr
.X_add_number
< 0)
4499 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
4500 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
4501 mips_isa
< 3 ? "addiu" : "daddiu",
4502 "t,r,j", dreg
, sreg
,
4503 (int) BFD_RELOC_LO16
);
4508 load_register (&icnt
, AT
, &imm_expr
, 0);
4509 macro_build ((char *) NULL
, &icnt
, NULL
, "xor", "d,v,t", dreg
,
4513 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
, dreg
,
4514 (int) BFD_RELOC_LO16
);
4519 case M_SGE
: /* sreg >= treg <==> not (sreg < treg) */
4525 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, sreg
, treg
);
4526 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
4527 (int) BFD_RELOC_LO16
);
4530 case M_SGE_I
: /* sreg >= I <==> not (sreg < I) */
4532 if (imm_expr
.X_add_number
>= -0x8000 && imm_expr
.X_add_number
< 0x8000)
4534 macro_build ((char *) NULL
, &icnt
, &expr1
,
4535 mask
== M_SGE_I
? "slti" : "sltiu",
4536 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
4541 load_register (&icnt
, AT
, &imm_expr
, 0);
4542 macro_build ((char *) NULL
, &icnt
, NULL
,
4543 mask
== M_SGE_I
? "slt" : "sltu",
4544 "d,v,t", dreg
, sreg
, AT
);
4547 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
4548 (int) BFD_RELOC_LO16
);
4553 case M_SGT
: /* sreg > treg <==> treg < sreg */
4559 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, treg
, sreg
);
4562 case M_SGT_I
: /* sreg > I <==> I < sreg */
4568 load_register (&icnt
, AT
, &imm_expr
, 0);
4569 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, AT
, sreg
);
4572 case M_SLE
: /* sreg <= treg <==> treg >= sreg <==> not (treg < sreg) */
4578 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, treg
, sreg
);
4579 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
4580 (int) BFD_RELOC_LO16
);
4583 case M_SLE_I
: /* sreg <= I <==> I >= sreg <==> not (I < sreg) */
4589 load_register (&icnt
, AT
, &imm_expr
, 0);
4590 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, AT
, sreg
);
4591 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
4592 (int) BFD_RELOC_LO16
);
4596 if (imm_expr
.X_add_number
>= -0x8000 && imm_expr
.X_add_number
< 0x8000)
4598 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "slti", "t,r,j",
4599 dreg
, sreg
, (int) BFD_RELOC_LO16
);
4602 load_register (&icnt
, AT
, &imm_expr
, 0);
4603 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", dreg
, sreg
, AT
);
4607 if (imm_expr
.X_add_number
>= -0x8000 && imm_expr
.X_add_number
< 0x8000)
4609 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "sltiu", "t,r,j",
4610 dreg
, sreg
, (int) BFD_RELOC_LO16
);
4613 load_register (&icnt
, AT
, &imm_expr
, 0);
4614 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, sreg
,
4620 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0,
4623 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0,
4627 macro_build ((char *) NULL
, &icnt
, NULL
, "xor", "d,v,t", dreg
,
4629 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0,
4635 if (imm_expr
.X_add_number
== 0)
4637 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0,
4643 as_warn ("Instruction %s: result is always true",
4645 macro_build ((char *) NULL
, &icnt
, &expr1
,
4646 mips_isa
< 3 ? "addiu" : "daddiu",
4647 "t,r,j", dreg
, 0, (int) BFD_RELOC_LO16
);
4650 if (imm_expr
.X_add_number
>= 0 && imm_expr
.X_add_number
< 0x10000)
4652 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "xori", "t,r,i",
4653 dreg
, sreg
, (int) BFD_RELOC_LO16
);
4656 else if (imm_expr
.X_add_number
> -0x8000 && imm_expr
.X_add_number
< 0)
4658 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
4659 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
4660 mips_isa
< 3 ? "addiu" : "daddiu",
4661 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
4666 load_register (&icnt
, AT
, &imm_expr
, 0);
4667 macro_build ((char *) NULL
, &icnt
, NULL
, "xor", "d,v,t", dreg
,
4671 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0, dreg
);
4679 if (imm_expr
.X_add_number
> -0x8000 && imm_expr
.X_add_number
<= 0x8000)
4681 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
4682 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
4683 dbl
? "daddi" : "addi",
4684 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
4687 load_register (&icnt
, AT
, &imm_expr
, dbl
);
4688 macro_build ((char *) NULL
, &icnt
, NULL
,
4689 dbl
? "dsub" : "sub",
4690 "d,v,t", dreg
, sreg
, AT
);
4696 if (imm_expr
.X_add_number
> -0x8000 && imm_expr
.X_add_number
<= 0x8000)
4698 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
4699 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
4700 dbl
? "daddiu" : "addiu",
4701 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
4704 load_register (&icnt
, AT
, &imm_expr
, dbl
);
4705 macro_build ((char *) NULL
, &icnt
, NULL
,
4706 dbl
? "dsubu" : "subu",
4707 "d,v,t", dreg
, sreg
, AT
);
4728 load_register (&icnt
, AT
, &imm_expr
, 0);
4729 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "s,t", sreg
, AT
);
4734 assert (mips_isa
< 2);
4735 sreg
= (ip
->insn_opcode
>> 11) & 0x1f; /* floating reg */
4736 dreg
= (ip
->insn_opcode
>> 06) & 0x1f; /* floating reg */
4739 * Is the double cfc1 instruction a bug in the mips assembler;
4740 * or is there a reason for it?
4742 mips_emit_delays ();
4744 mips_any_noreorder
= 1;
4745 macro_build ((char *) NULL
, &icnt
, NULL
, "cfc1", "t,G", treg
, 31);
4746 macro_build ((char *) NULL
, &icnt
, NULL
, "cfc1", "t,G", treg
, 31);
4747 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "");
4748 expr1
.X_add_number
= 3;
4749 macro_build ((char *) NULL
, &icnt
, &expr1
, "ori", "t,r,i", AT
, treg
,
4750 (int) BFD_RELOC_LO16
);
4751 expr1
.X_add_number
= 2;
4752 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", AT
, AT
,
4753 (int) BFD_RELOC_LO16
);
4754 macro_build ((char *) NULL
, &icnt
, NULL
, "ctc1", "t,G", AT
, 31);
4755 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "");
4756 macro_build ((char *) NULL
, &icnt
, NULL
,
4757 mask
== M_TRUNCWD
? "cvt.w.d" : "cvt.w.s", "D,S", dreg
, sreg
);
4758 macro_build ((char *) NULL
, &icnt
, NULL
, "ctc1", "t,G", treg
, 31);
4759 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "");
4769 if (offset_expr
.X_add_number
>= 0x7fff)
4770 as_bad ("operand overflow");
4771 /* avoid load delay */
4772 if (byte_order
== LITTLE_ENDIAN
)
4773 offset_expr
.X_add_number
+= 1;
4774 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
4775 (int) BFD_RELOC_LO16
, breg
);
4776 if (byte_order
== LITTLE_ENDIAN
)
4777 offset_expr
.X_add_number
-= 1;
4779 offset_expr
.X_add_number
+= 1;
4780 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lbu", "t,o(b)", AT
,
4781 (int) BFD_RELOC_LO16
, breg
);
4782 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", treg
, treg
, 8);
4783 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", treg
, treg
, AT
);
4796 if (offset_expr
.X_add_number
>= 0x8000 - off
)
4797 as_bad ("operand overflow");
4798 if (byte_order
== LITTLE_ENDIAN
)
4799 offset_expr
.X_add_number
+= off
;
4800 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
4801 (int) BFD_RELOC_LO16
, breg
);
4802 if (byte_order
== LITTLE_ENDIAN
)
4803 offset_expr
.X_add_number
-= off
;
4805 offset_expr
.X_add_number
+= off
;
4806 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s2
, "t,o(b)", treg
,
4807 (int) BFD_RELOC_LO16
, breg
);
4820 load_address (&icnt
, AT
, &offset_expr
);
4822 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4823 mips_isa
< 3 ? "addu" : "daddu",
4824 "d,v,t", AT
, AT
, breg
);
4825 if (byte_order
== LITTLE_ENDIAN
)
4826 expr1
.X_add_number
= off
;
4828 expr1
.X_add_number
= 0;
4829 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, "t,o(b)", treg
,
4830 (int) BFD_RELOC_LO16
, AT
);
4831 if (byte_order
== LITTLE_ENDIAN
)
4832 expr1
.X_add_number
= 0;
4834 expr1
.X_add_number
= off
;
4835 macro_build ((char *) NULL
, &icnt
, &expr1
, s2
, "t,o(b)", treg
,
4836 (int) BFD_RELOC_LO16
, AT
);
4841 load_address (&icnt
, AT
, &offset_expr
);
4843 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4844 mips_isa
< 3 ? "addu" : "daddu",
4845 "d,v,t", AT
, AT
, breg
);
4846 if (byte_order
== BIG_ENDIAN
)
4847 expr1
.X_add_number
= 0;
4848 macro_build ((char *) NULL
, &icnt
, &expr1
,
4849 mask
== M_ULH_A
? "lb" : "lbu", "t,o(b)", treg
,
4850 (int) BFD_RELOC_LO16
, AT
);
4851 if (byte_order
== BIG_ENDIAN
)
4852 expr1
.X_add_number
= 1;
4854 expr1
.X_add_number
= 0;
4855 macro_build ((char *) NULL
, &icnt
, &expr1
, "lbu", "t,o(b)", AT
,
4856 (int) BFD_RELOC_LO16
, AT
);
4857 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", treg
,
4859 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", treg
,
4864 if (offset_expr
.X_add_number
>= 0x7fff)
4865 as_bad ("operand overflow");
4866 if (byte_order
== BIG_ENDIAN
)
4867 offset_expr
.X_add_number
+= 1;
4868 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "sb", "t,o(b)", treg
,
4869 (int) BFD_RELOC_LO16
, breg
);
4870 macro_build ((char *) NULL
, &icnt
, NULL
, "srl", "d,w,<", AT
, treg
, 8);
4871 if (byte_order
== BIG_ENDIAN
)
4872 offset_expr
.X_add_number
-= 1;
4874 offset_expr
.X_add_number
+= 1;
4875 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "sb", "t,o(b)", AT
,
4876 (int) BFD_RELOC_LO16
, breg
);
4889 if (offset_expr
.X_add_number
>= 0x8000 - off
)
4890 as_bad ("operand overflow");
4891 if (byte_order
== LITTLE_ENDIAN
)
4892 offset_expr
.X_add_number
+= off
;
4893 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
4894 (int) BFD_RELOC_LO16
, breg
);
4895 if (byte_order
== LITTLE_ENDIAN
)
4896 offset_expr
.X_add_number
-= off
;
4898 offset_expr
.X_add_number
+= off
;
4899 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s2
, "t,o(b)", treg
,
4900 (int) BFD_RELOC_LO16
, breg
);
4913 load_address (&icnt
, AT
, &offset_expr
);
4915 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4916 mips_isa
< 3 ? "addu" : "daddu",
4917 "d,v,t", AT
, AT
, breg
);
4918 if (byte_order
== LITTLE_ENDIAN
)
4919 expr1
.X_add_number
= off
;
4921 expr1
.X_add_number
= 0;
4922 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, "t,o(b)", treg
,
4923 (int) BFD_RELOC_LO16
, AT
);
4924 if (byte_order
== LITTLE_ENDIAN
)
4925 expr1
.X_add_number
= 0;
4927 expr1
.X_add_number
= off
;
4928 macro_build ((char *) NULL
, &icnt
, &expr1
, s2
, "t,o(b)", treg
,
4929 (int) BFD_RELOC_LO16
, AT
);
4933 load_address (&icnt
, AT
, &offset_expr
);
4935 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4936 mips_isa
< 3 ? "addu" : "daddu",
4937 "d,v,t", AT
, AT
, breg
);
4938 if (byte_order
== LITTLE_ENDIAN
)
4939 expr1
.X_add_number
= 0;
4940 macro_build ((char *) NULL
, &icnt
, &expr1
, "sb", "t,o(b)", treg
,
4941 (int) BFD_RELOC_LO16
, AT
);
4942 macro_build ((char *) NULL
, &icnt
, NULL
, "srl", "d,w,<", treg
,
4944 if (byte_order
== LITTLE_ENDIAN
)
4945 expr1
.X_add_number
= 1;
4947 expr1
.X_add_number
= 0;
4948 macro_build ((char *) NULL
, &icnt
, &expr1
, "sb", "t,o(b)", treg
,
4949 (int) BFD_RELOC_LO16
, AT
);
4950 if (byte_order
== LITTLE_ENDIAN
)
4951 expr1
.X_add_number
= 0;
4953 expr1
.X_add_number
= 1;
4954 macro_build ((char *) NULL
, &icnt
, &expr1
, "lbu", "t,o(b)", AT
,
4955 (int) BFD_RELOC_LO16
, AT
);
4956 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", treg
,
4958 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", treg
,
4963 as_bad ("Macro %s not implemented yet", ip
->insn_mo
->name
);
4967 as_warn ("Macro used $at after \".set noat\"");
4970 /* This routine assembles an instruction into its binary format. As a
4971 side effect, it sets one of the global variables imm_reloc or
4972 offset_reloc to the type of relocation to do if one of the operands
4973 is an address expression. */
4978 struct mips_cl_insn
*ip
;
4983 struct mips_opcode
*insn
;
4986 unsigned int lastregno
= 0;
4991 for (s
= str
; islower (*s
) || (*s
>= '0' && *s
<= '3') || *s
== '6' || *s
== '.'; ++s
)
5003 as_fatal ("Unknown opcode: `%s'", str
);
5005 if ((insn
= (struct mips_opcode
*) hash_find (op_hash
, str
)) == NULL
)
5007 as_warn ("`%s' not in hash table.", str
);
5008 insn_error
= "ERROR: Unrecognized opcode";
5016 assert (strcmp (insn
->name
, str
) == 0);
5018 if (insn
->pinfo
== INSN_MACRO
)
5019 insn_isa
= insn
->match
;
5020 else if ((insn
->pinfo
& INSN_ISA
) == INSN_ISA2
)
5022 else if ((insn
->pinfo
& INSN_ISA
) == INSN_ISA3
)
5024 else if ((insn
->pinfo
& INSN_ISA
) == INSN_ISA4
)
5029 if (insn_isa
> mips_isa
5030 || ((insn
->pinfo
& INSN_ISA
) == INSN_4650
5032 || ((insn
->pinfo
& INSN_ISA
) == INSN_4010
5034 || ((insn
->pinfo
& INSN_ISA
) == INSN_4100
5037 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
]
5038 && strcmp (insn
->name
, insn
[1].name
) == 0)
5043 as_warn ("Instruction not supported on this processor");
5047 ip
->insn_opcode
= insn
->match
;
5048 for (args
= insn
->args
;; ++args
)
5054 case '\0': /* end of args */
5067 ip
->insn_opcode
|= lastregno
<< 21;
5072 ip
->insn_opcode
|= lastregno
<< 16;
5076 ip
->insn_opcode
|= lastregno
<< 11;
5082 /* handle optional base register.
5083 Either the base register is omitted or
5084 we must have a left paren. */
5085 /* this is dependent on the next operand specifier
5086 is a 'b' for base register */
5087 assert (args
[1] == 'b');
5091 case ')': /* these must match exactly */
5096 case '<': /* must be at least one digit */
5098 * According to the manual, if the shift amount is greater
5099 * than 31 or less than 0 the the shift amount should be
5100 * mod 32. In reality the mips assembler issues an error.
5101 * We issue a warning and mask out all but the low 5 bits.
5103 my_getExpression (&imm_expr
, s
);
5104 check_absolute_expr (ip
, &imm_expr
);
5105 if ((unsigned long) imm_expr
.X_add_number
> 31)
5107 as_warn ("Improper shift amount (%ld)",
5108 (long) imm_expr
.X_add_number
);
5109 imm_expr
.X_add_number
= imm_expr
.X_add_number
& 0x1f;
5111 ip
->insn_opcode
|= imm_expr
.X_add_number
<< 6;
5112 imm_expr
.X_op
= O_absent
;
5116 case '>': /* shift amount minus 32 */
5117 my_getExpression (&imm_expr
, s
);
5118 check_absolute_expr (ip
, &imm_expr
);
5119 if ((unsigned long) imm_expr
.X_add_number
< 32
5120 || (unsigned long) imm_expr
.X_add_number
> 63)
5122 ip
->insn_opcode
|= (imm_expr
.X_add_number
- 32) << 6;
5123 imm_expr
.X_op
= O_absent
;
5127 case 'k': /* cache code */
5128 case 'h': /* prefx code */
5129 my_getExpression (&imm_expr
, s
);
5130 check_absolute_expr (ip
, &imm_expr
);
5131 if ((unsigned long) imm_expr
.X_add_number
> 31)
5133 as_warn ("Invalid value for `%s' (%lu)",
5135 (unsigned long) imm_expr
.X_add_number
);
5136 imm_expr
.X_add_number
&= 0x1f;
5139 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_CACHE
;
5141 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_PREFX
;
5142 imm_expr
.X_op
= O_absent
;
5146 case 'c': /* break code */
5147 my_getExpression (&imm_expr
, s
);
5148 check_absolute_expr (ip
, &imm_expr
);
5149 if ((unsigned) imm_expr
.X_add_number
> 1023)
5150 as_warn ("Illegal break code (%ld)",
5151 (long) imm_expr
.X_add_number
);
5152 ip
->insn_opcode
|= imm_expr
.X_add_number
<< 16;
5153 imm_expr
.X_op
= O_absent
;
5157 case 'B': /* syscall code */
5158 my_getExpression (&imm_expr
, s
);
5159 check_absolute_expr (ip
, &imm_expr
);
5160 if ((unsigned) imm_expr
.X_add_number
> 0xfffff)
5161 as_warn ("Illegal syscall code (%ld)",
5162 (long) imm_expr
.X_add_number
);
5163 ip
->insn_opcode
|= imm_expr
.X_add_number
<< 6;
5164 imm_expr
.X_op
= O_absent
;
5168 case 'C': /* Coprocessor code */
5169 my_getExpression (&imm_expr
, s
);
5170 check_absolute_expr (ip
, &imm_expr
);
5171 if ((unsigned long) imm_expr
.X_add_number
>= (1<<25))
5173 as_warn ("Coproccesor code > 25 bits (%ld)",
5174 (long) imm_expr
.X_add_number
);
5175 imm_expr
.X_add_number
&= ((1<<25) - 1);
5177 ip
->insn_opcode
|= imm_expr
.X_add_number
;
5178 imm_expr
.X_op
= O_absent
;
5182 case 'b': /* base register */
5183 case 'd': /* destination register */
5184 case 's': /* source register */
5185 case 't': /* target register */
5186 case 'r': /* both target and source */
5187 case 'v': /* both dest and source */
5188 case 'w': /* both dest and target */
5189 case 'E': /* coprocessor target register */
5190 case 'G': /* coprocessor destination register */
5191 case 'x': /* ignore register name */
5192 case 'z': /* must be zero register */
5206 while (isdigit (*s
));
5208 as_bad ("Invalid register number (%d)", regno
);
5210 else if (*args
== 'E' || *args
== 'G')
5214 if (s
[1] == 'f' && s
[2] == 'p')
5219 else if (s
[1] == 's' && s
[2] == 'p')
5224 else if (s
[1] == 'g' && s
[2] == 'p')
5229 else if (s
[1] == 'a' && s
[2] == 't')
5234 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '0')
5239 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '1')
5247 if (regno
== AT
&& ! mips_noat
)
5248 as_warn ("Used $at without \".set noat\"");
5254 if (c
== 'r' || c
== 'v' || c
== 'w')
5261 /* 'z' only matches $0. */
5262 if (c
== 'z' && regno
!= 0)
5270 ip
->insn_opcode
|= regno
<< 21;
5274 ip
->insn_opcode
|= regno
<< 11;
5279 ip
->insn_opcode
|= regno
<< 16;
5282 /* This case exists because on the r3000 trunc
5283 expands into a macro which requires a gp
5284 register. On the r6000 or r4000 it is
5285 assembled into a single instruction which
5286 ignores the register. Thus the insn version
5287 is MIPS_ISA2 and uses 'x', and the macro
5288 version is MIPS_ISA1 and uses 't'. */
5291 /* This case is for the div instruction, which
5292 acts differently if the destination argument
5293 is $0. This only matches $0, and is checked
5294 outside the switch. */
5305 ip
->insn_opcode
|= lastregno
<< 21;
5308 ip
->insn_opcode
|= lastregno
<< 16;
5313 case 'D': /* floating point destination register */
5314 case 'S': /* floating point source register */
5315 case 'T': /* floating point target register */
5316 case 'R': /* floating point source register */
5320 if (s
[0] == '$' && s
[1] == 'f' && isdigit (s
[2]))
5330 while (isdigit (*s
));
5333 as_bad ("Invalid float register number (%d)", regno
);
5335 if ((regno
& 1) != 0
5337 && ! (strcmp (str
, "mtc1") == 0 ||
5338 strcmp (str
, "mfc1") == 0 ||
5339 strcmp (str
, "lwc1") == 0 ||
5340 strcmp (str
, "swc1") == 0))
5341 as_warn ("Float register should be even, was %d",
5349 if (c
== 'V' || c
== 'W')
5359 ip
->insn_opcode
|= regno
<< 6;
5363 ip
->insn_opcode
|= regno
<< 11;
5367 ip
->insn_opcode
|= regno
<< 16;
5370 ip
->insn_opcode
|= regno
<< 21;
5379 ip
->insn_opcode
|= lastregno
<< 11;
5382 ip
->insn_opcode
|= lastregno
<< 16;
5388 my_getExpression (&imm_expr
, s
);
5389 if (imm_expr
.X_op
!= O_big
)
5390 check_absolute_expr (ip
, &imm_expr
);
5395 my_getExpression (&offset_expr
, s
);
5396 imm_reloc
= BFD_RELOC_32
;
5408 unsigned char temp
[8];
5410 unsigned int length
;
5415 /* These only appear as the last operand in an
5416 instruction, and every instruction that accepts
5417 them in any variant accepts them in all variants.
5418 This means we don't have to worry about backing out
5419 any changes if the instruction does not match.
5421 The difference between them is the size of the
5422 floating point constant and where it goes. For 'F'
5423 and 'L' the constant is 64 bits; for 'f' and 'l' it
5424 is 32 bits. Where the constant is placed is based
5425 on how the MIPS assembler does things:
5428 f -- immediate value
5431 The .lit4 and .lit8 sections are only used if
5432 permitted by the -G argument.
5434 When generating embedded PIC code, we use the
5435 .lit8 section but not the .lit4 section (we can do
5436 .lit4 inline easily; we need to put .lit8
5437 somewhere in the data segment, and using .lit8
5438 permits the linker to eventually combine identical
5441 f64
= *args
== 'F' || *args
== 'L';
5443 save_in
= input_line_pointer
;
5444 input_line_pointer
= s
;
5445 err
= md_atof (f64
? 'd' : 'f', (char *) temp
, &len
);
5447 s
= input_line_pointer
;
5448 input_line_pointer
= save_in
;
5449 if (err
!= NULL
&& *err
!= '\0')
5451 as_bad ("Bad floating point constant: %s", err
);
5452 memset (temp
, '\0', sizeof temp
);
5453 length
= f64
? 8 : 4;
5456 assert (length
== (f64
? 8 : 4));
5460 && (! USE_GLOBAL_POINTER_OPT
5461 || mips_pic
== EMBEDDED_PIC
5462 || g_switch_value
< 4)
5465 imm_expr
.X_op
= O_constant
;
5466 if (byte_order
== LITTLE_ENDIAN
)
5467 imm_expr
.X_add_number
=
5468 (((((((int) temp
[3] << 8)
5473 imm_expr
.X_add_number
=
5474 (((((((int) temp
[0] << 8)
5481 const char *newname
;
5484 /* Switch to the right section. */
5486 subseg
= now_subseg
;
5489 default: /* unused default case avoids warnings. */
5491 newname
= RDATA_SECTION_NAME
;
5492 if (USE_GLOBAL_POINTER_OPT
&& g_switch_value
>= 8)
5496 newname
= RDATA_SECTION_NAME
;
5499 assert (!USE_GLOBAL_POINTER_OPT
5500 || g_switch_value
>= 4);
5504 new_seg
= subseg_new (newname
, (subsegT
) 0);
5505 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
5506 bfd_set_section_flags (stdoutput
, new_seg
,
5511 frag_align (*args
== 'l' ? 2 : 3, 0);
5512 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
5513 record_alignment (new_seg
, 4);
5515 record_alignment (new_seg
, *args
== 'l' ? 2 : 3);
5517 as_bad ("Can't use floating point insn in this section");
5519 /* Set the argument to the current address in the
5521 offset_expr
.X_op
= O_symbol
;
5522 offset_expr
.X_add_symbol
=
5523 symbol_new ("L0\001", now_seg
,
5524 (valueT
) frag_now_fix (), frag_now
);
5525 offset_expr
.X_add_number
= 0;
5527 /* Put the floating point number into the section. */
5528 p
= frag_more ((int) length
);
5529 memcpy (p
, temp
, length
);
5531 /* Switch back to the original section. */
5532 subseg_set (seg
, subseg
);
5537 case 'i': /* 16 bit unsigned immediate */
5538 case 'j': /* 16 bit signed immediate */
5539 imm_reloc
= BFD_RELOC_LO16
;
5540 c
= my_getSmallExpression (&imm_expr
, s
);
5545 if (imm_expr
.X_op
== O_constant
)
5546 imm_expr
.X_add_number
=
5547 (imm_expr
.X_add_number
>> 16) & 0xffff;
5550 imm_reloc
= BFD_RELOC_HI16_S
;
5551 imm_unmatched_hi
= true;
5554 imm_reloc
= BFD_RELOC_HI16
;
5557 else if (imm_expr
.X_op
!= O_big
)
5558 check_absolute_expr (ip
, &imm_expr
);
5561 if (imm_expr
.X_op
== O_big
5562 || imm_expr
.X_add_number
< 0
5563 || imm_expr
.X_add_number
>= 0x10000)
5565 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
5566 !strcmp (insn
->name
, insn
[1].name
))
5568 as_bad ("16 bit expression not in range 0..65535");
5576 /* The upper bound should be 0x8000, but
5577 unfortunately the MIPS assembler accepts numbers
5578 from 0x8000 to 0xffff and sign extends them, and
5579 we want to be compatible. We only permit this
5580 extended range for an instruction which does not
5581 provide any further alternates, since those
5582 alternates may handle other cases. People should
5583 use the numbers they mean, rather than relying on
5584 a mysterious sign extension. */
5585 more
= (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
5586 strcmp (insn
->name
, insn
[1].name
) == 0);
5591 if (imm_expr
.X_op
== O_big
5592 || imm_expr
.X_add_number
< -0x8000
5593 || imm_expr
.X_add_number
>= max
5595 && imm_expr
.X_add_number
< 0
5597 && imm_expr
.X_unsigned
5598 && sizeof (imm_expr
.X_add_number
) <= 4))
5602 as_bad ("16 bit expression not in range -32768..32767");
5608 case 'o': /* 16 bit offset */
5609 c
= my_getSmallExpression (&offset_expr
, s
);
5611 /* If this value won't fit into a 16 bit offset, then go
5612 find a macro that will generate the 32 bit offset
5613 code pattern. As a special hack, we accept the
5614 difference of two local symbols as a constant. This
5615 is required to suppose embedded PIC switches, which
5616 use an instruction which looks like
5617 lw $4,$L12-$LS12($4)
5618 The problem with handling this in a more general
5619 fashion is that the macro function doesn't expect to
5620 see anything which can be handled in a single
5621 constant instruction. */
5623 && (offset_expr
.X_op
!= O_constant
5624 || offset_expr
.X_add_number
>= 0x8000
5625 || offset_expr
.X_add_number
< -0x8000)
5626 && (mips_pic
!= EMBEDDED_PIC
5627 || offset_expr
.X_op
!= O_subtract
5628 || now_seg
!= text_section
5629 || (S_GET_SEGMENT (offset_expr
.X_op_symbol
)
5633 offset_reloc
= BFD_RELOC_LO16
;
5634 if (c
== 'h' || c
== 'H')
5636 assert (offset_expr
.X_op
== O_constant
);
5637 offset_expr
.X_add_number
=
5638 (offset_expr
.X_add_number
>> 16) & 0xffff;
5643 case 'p': /* pc relative offset */
5644 offset_reloc
= BFD_RELOC_16_PCREL_S2
;
5645 my_getExpression (&offset_expr
, s
);
5649 case 'u': /* upper 16 bits */
5650 c
= my_getSmallExpression (&imm_expr
, s
);
5651 if (imm_expr
.X_op
== O_constant
5652 && (imm_expr
.X_add_number
< 0
5653 || imm_expr
.X_add_number
>= 0x10000))
5654 as_bad ("lui expression not in range 0..65535");
5655 imm_reloc
= BFD_RELOC_LO16
;
5660 if (imm_expr
.X_op
== O_constant
)
5661 imm_expr
.X_add_number
=
5662 (imm_expr
.X_add_number
>> 16) & 0xffff;
5665 imm_reloc
= BFD_RELOC_HI16_S
;
5666 imm_unmatched_hi
= true;
5669 imm_reloc
= BFD_RELOC_HI16
;
5675 case 'a': /* 26 bit address */
5676 my_getExpression (&offset_expr
, s
);
5678 offset_reloc
= BFD_RELOC_MIPS_JMP
;
5681 case 'N': /* 3 bit branch condition code */
5682 case 'M': /* 3 bit compare condition code */
5683 my_getExpression (&imm_expr
, s
);
5684 check_absolute_expr (ip
, &imm_expr
);
5685 if ((unsigned long) imm_expr
.X_add_number
> 7)
5687 as_warn ("Condition code > 7 (%ld)",
5688 (long) imm_expr
.X_add_number
);
5689 imm_expr
.X_add_number
&= 7;
5692 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_BCC
;
5694 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_CCC
;
5695 imm_expr
.X_op
= O_absent
;
5700 fprintf (stderr
, "bad char = '%c'\n", *args
);
5705 /* Args don't match. */
5706 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
5707 !strcmp (insn
->name
, insn
[1].name
))
5713 insn_error
= "ERROR: Illegal operands";
5722 my_getSmallExpression (ep
, str
)
5733 ((str
[1] == 'h' && str
[2] == 'i')
5734 || (str
[1] == 'H' && str
[2] == 'I')
5735 || (str
[1] == 'l' && str
[2] == 'o'))
5747 * A small expression may be followed by a base register.
5748 * Scan to the end of this operand, and then back over a possible
5749 * base register. Then scan the small expression up to that
5750 * point. (Based on code in sparc.c...)
5752 for (sp
= str
; *sp
&& *sp
!= ','; sp
++)
5754 if (sp
- 4 >= str
&& sp
[-1] == RP
)
5756 if (isdigit (sp
[-2]))
5758 for (sp
-= 3; sp
>= str
&& isdigit (*sp
); sp
--)
5760 if (*sp
== '$' && sp
> str
&& sp
[-1] == LP
)
5766 else if (sp
- 5 >= str
5769 && ((sp
[-3] == 'f' && sp
[-2] == 'p')
5770 || (sp
[-3] == 's' && sp
[-2] == 'p')
5771 || (sp
[-3] == 'g' && sp
[-2] == 'p')
5772 || (sp
[-3] == 'a' && sp
[-2] == 't')))
5778 /* no expression means zero offset */
5781 /* %xx(reg) is an error */
5782 ep
->X_op
= O_absent
;
5787 ep
->X_op
= O_constant
;
5790 ep
->X_add_symbol
= NULL
;
5791 ep
->X_op_symbol
= NULL
;
5792 ep
->X_add_number
= 0;
5797 my_getExpression (ep
, str
);
5804 my_getExpression (ep
, str
);
5805 return c
; /* => %hi or %lo encountered */
5809 my_getExpression (ep
, str
)
5815 save_in
= input_line_pointer
;
5816 input_line_pointer
= str
;
5818 expr_end
= input_line_pointer
;
5819 input_line_pointer
= save_in
;
5822 /* Turn a string in input_line_pointer into a floating point constant
5823 of type type, and store the appropriate bytes in *litP. The number
5824 of LITTLENUMS emitted is stored in *sizeP . An error message is
5825 returned, or NULL on OK. */
5828 md_atof (type
, litP
, sizeP
)
5834 LITTLENUM_TYPE words
[4];
5850 return "bad call to md_atof";
5853 t
= atof_ieee (input_line_pointer
, type
, words
);
5855 input_line_pointer
= t
;
5859 if (byte_order
== LITTLE_ENDIAN
)
5861 for (i
= prec
- 1; i
>= 0; i
--)
5863 md_number_to_chars (litP
, (valueT
) words
[i
], 2);
5869 for (i
= 0; i
< prec
; i
++)
5871 md_number_to_chars (litP
, (valueT
) words
[i
], 2);
5880 md_number_to_chars (buf
, val
, n
)
5888 number_to_chars_littleendian (buf
, val
, n
);
5892 number_to_chars_bigendian (buf
, val
, n
);
5900 CONST
char *md_shortopts
= "O::g::G:";
5902 struct option md_longopts
[] = {
5903 #define OPTION_MIPS1 (OPTION_MD_BASE + 1)
5904 {"mips0", no_argument
, NULL
, OPTION_MIPS1
},
5905 {"mips1", no_argument
, NULL
, OPTION_MIPS1
},
5906 #define OPTION_MIPS2 (OPTION_MD_BASE + 2)
5907 {"mips2", no_argument
, NULL
, OPTION_MIPS2
},
5908 #define OPTION_MIPS3 (OPTION_MD_BASE + 3)
5909 {"mips3", no_argument
, NULL
, OPTION_MIPS3
},
5910 #define OPTION_MIPS4 (OPTION_MD_BASE + 4)
5911 {"mips4", no_argument
, NULL
, OPTION_MIPS4
},
5912 #define OPTION_MCPU (OPTION_MD_BASE + 5)
5913 {"mcpu", required_argument
, NULL
, OPTION_MCPU
},
5914 #define OPTION_MEMBEDDED_PIC (OPTION_MD_BASE + 6)
5915 {"membedded-pic", no_argument
, NULL
, OPTION_MEMBEDDED_PIC
},
5916 #define OPTION_TRAP (OPTION_MD_BASE + 9)
5917 {"trap", no_argument
, NULL
, OPTION_TRAP
},
5918 {"no-break", no_argument
, NULL
, OPTION_TRAP
},
5919 #define OPTION_BREAK (OPTION_MD_BASE + 10)
5920 {"break", no_argument
, NULL
, OPTION_BREAK
},
5921 {"no-trap", no_argument
, NULL
, OPTION_BREAK
},
5922 #define OPTION_EB (OPTION_MD_BASE + 11)
5923 {"EB", no_argument
, NULL
, OPTION_EB
},
5924 #define OPTION_EL (OPTION_MD_BASE + 12)
5925 {"EL", no_argument
, NULL
, OPTION_EL
},
5926 #define OPTION_M4650 (OPTION_MD_BASE + 13)
5927 {"m4650", no_argument
, NULL
, OPTION_M4650
},
5928 #define OPTION_NO_M4650 (OPTION_MD_BASE + 14)
5929 {"no-m4650", no_argument
, NULL
, OPTION_NO_M4650
},
5930 #define OPTION_M4010 (OPTION_MD_BASE + 15)
5931 {"m4010", no_argument
, NULL
, OPTION_M4010
},
5932 #define OPTION_NO_M4010 (OPTION_MD_BASE + 16)
5933 {"no-m4010", no_argument
, NULL
, OPTION_NO_M4010
},
5934 #define OPTION_M4100 (OPTION_MD_BASE + 17)
5935 {"m4100", no_argument
, NULL
, OPTION_M4100
},
5936 #define OPTION_NO_M4100 (OPTION_MD_BASE + 18)
5937 {"no-m4100", no_argument
, NULL
, OPTION_NO_M4100
},
5939 #define OPTION_CALL_SHARED (OPTION_MD_BASE + 7)
5940 #define OPTION_NON_SHARED (OPTION_MD_BASE + 8)
5941 #define OPTION_XGOT (OPTION_MD_BASE + 19)
5942 #define OPTION_32 (OPTION_MD_BASE + 20)
5943 #define OPTION_64 (OPTION_MD_BASE + 21)
5945 {"KPIC", no_argument
, NULL
, OPTION_CALL_SHARED
},
5946 {"xgot", no_argument
, NULL
, OPTION_XGOT
},
5947 {"call_shared", no_argument
, NULL
, OPTION_CALL_SHARED
},
5948 {"non_shared", no_argument
, NULL
, OPTION_NON_SHARED
},
5949 {"32", no_argument
, NULL
, OPTION_32
},
5950 {"64", no_argument
, NULL
, OPTION_64
},
5953 {NULL
, no_argument
, NULL
, 0}
5955 size_t md_longopts_size
= sizeof(md_longopts
);
5958 md_parse_option (c
, arg
)
5973 target_big_endian
= 1;
5977 target_big_endian
= 0;
5981 if (arg
&& arg
[1] == '0')
5991 mips_debug
= atoi (arg
);
5992 /* When the MIPS assembler sees -g or -g2, it does not do
5993 optimizations which limit full symbolic debugging. We take
5994 that to be equivalent to -O0. */
5995 if (mips_debug
== 2)
6027 /* Identify the processor type */
6029 if (strcmp (p
, "default") == 0
6030 || strcmp (p
, "DEFAULT") == 0)
6036 /* We need to cope with the various "vr" prefixes for the 4300
6038 if (*p
== 'v' || *p
== 'V')
6044 if (*p
== 'r' || *p
== 'R')
6051 if (strcmp (p
, "10000") == 0
6052 || strcmp (p
, "10k") == 0
6053 || strcmp (p
, "10K") == 0)
6058 if (strcmp (p
, "2000") == 0
6059 || strcmp (p
, "2k") == 0
6060 || strcmp (p
, "2K") == 0)
6065 if (strcmp (p
, "3000") == 0
6066 || strcmp (p
, "3k") == 0
6067 || strcmp (p
, "3K") == 0)
6072 if (strcmp (p
, "4000") == 0
6073 || strcmp (p
, "4k") == 0
6074 || strcmp (p
, "4K") == 0)
6076 else if (strcmp (p
, "4100") == 0)
6082 else if (strcmp (p
, "4300") == 0)
6084 else if (strcmp (p
, "4400") == 0)
6086 else if (strcmp (p
, "4600") == 0)
6088 else if (strcmp (p
, "4650") == 0)
6094 else if (strcmp (p
, "4010") == 0)
6103 if (strcmp (p
, "6000") == 0
6104 || strcmp (p
, "6k") == 0
6105 || strcmp (p
, "6K") == 0)
6110 if (strcmp (p
, "8000") == 0
6111 || strcmp (p
, "8k") == 0
6112 || strcmp (p
, "8K") == 0)
6117 if (strcmp (p
, "orion") == 0)
6122 if (sv
&& mips_cpu
!= 4300 && mips_cpu
!= 4100)
6124 as_bad ("ignoring invalid leading 'v' in -mcpu=%s switch", arg
);
6130 as_bad ("invalid architecture -mcpu=%s", arg
);
6141 case OPTION_NO_M4650
:
6149 case OPTION_NO_M4010
:
6157 case OPTION_NO_M4100
:
6161 case OPTION_MEMBEDDED_PIC
:
6162 mips_pic
= EMBEDDED_PIC
;
6163 if (USE_GLOBAL_POINTER_OPT
&& g_switch_seen
)
6165 as_bad ("-G may not be used with embedded PIC code");
6168 g_switch_value
= 0x7fffffff;
6171 /* When generating ELF code, we permit -KPIC and -call_shared to
6172 select SVR4_PIC, and -non_shared to select no PIC. This is
6173 intended to be compatible with Irix 5. */
6174 case OPTION_CALL_SHARED
:
6175 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
6177 as_bad ("-call_shared is supported only for ELF format");
6180 mips_pic
= SVR4_PIC
;
6181 if (g_switch_seen
&& g_switch_value
!= 0)
6183 as_bad ("-G may not be used with SVR4 PIC code");
6189 case OPTION_NON_SHARED
:
6190 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
6192 as_bad ("-non_shared is supported only for ELF format");
6198 /* The -xgot option tells the assembler to use 32 offsets when
6199 accessing the got in SVR4_PIC mode. It is for Irix
6206 if (! USE_GLOBAL_POINTER_OPT
)
6208 as_bad ("-G is not supported for this configuration");
6211 else if (mips_pic
== SVR4_PIC
|| mips_pic
== EMBEDDED_PIC
)
6213 as_bad ("-G may not be used with SVR4 or embedded PIC code");
6217 g_switch_value
= atoi (arg
);
6221 /* The -32 and -64 options tell the assembler to output the 32
6222 bit or the 64 bit MIPS ELF format. */
6239 md_show_usage (stream
)
6244 -membedded-pic generate embedded position independent code\n\
6245 -EB generate big endian output\n\
6246 -EL generate little endian output\n\
6247 -g, -g2 do not remove uneeded NOPs or swap branches\n\
6248 -G NUM allow referencing objects up to NUM bytes\n\
6249 implicitly with the gp register [default 8]\n");
6251 -mips1, -mcpu=r{2,3}000 generate code for r2000 and r3000\n\
6252 -mips2, -mcpu=r6000 generate code for r6000\n\
6253 -mips3, -mcpu=r4000 generate code for r4000\n\
6254 -mips4, -mcpu=r8000 generate code for r8000\n\
6255 -mcpu=vr4300 generate code for vr4300\n\
6256 -mcpu=vr4100 generate code for vr4100\n\
6257 -m4650 permit R4650 instructions\n\
6258 -no-m4650 do not permit R4650 instructions\n\
6259 -m4010 permit R4010 instructions\n\
6260 -no-m4010 do not permit R4010 instructions\n\
6261 -m4100 permit VR4100 instructions\n\
6262 -no-m4100 do not permit VR4100 instructions\n");
6264 -O0 remove unneeded NOPs, do not swap branches\n\
6265 -O remove unneeded NOPs and swap branches\n\
6266 --trap, --no-break trap exception on div by 0 and mult overflow\n\
6267 --break, --no-trap break exception on div by 0 and mult overflow\n");
6270 -KPIC, -call_shared generate SVR4 position independent code\n\
6271 -non_shared do not generate position independent code\n\
6272 -xgot assume a 32 bit GOT\n\
6273 -32 create 32 bit object file (default)\n\
6274 -64 create 64 bit object file\n");
6279 mips_init_after_args ()
6281 if (target_big_endian
)
6282 byte_order
= BIG_ENDIAN
;
6284 byte_order
= LITTLE_ENDIAN
;
6288 md_pcrel_from (fixP
)
6291 if (OUTPUT_FLAVOR
!= bfd_target_aout_flavour
6292 && fixP
->fx_addsy
!= (symbolS
*) NULL
6293 && ! S_IS_DEFINED (fixP
->fx_addsy
))
6295 /* This makes a branch to an undefined symbol be a branch to the
6296 current location. */
6300 /* return the address of the delay slot */
6301 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
6304 /* This is called by emit_expr via TC_CONS_FIX_NEW when creating a
6305 reloc for a cons. We could use the definition there, except that
6306 we want to handle 64 bit relocs specially. */
6309 cons_fix_new_mips (frag
, where
, nbytes
, exp
)
6312 unsigned int nbytes
;
6315 /* If we are assembling in 32 bit mode, turn an 8 byte reloc into a
6317 if (nbytes
== 8 && ! mips_64
)
6319 if (byte_order
== BIG_ENDIAN
)
6324 if (nbytes
!= 2 && nbytes
!= 4 && nbytes
!= 8)
6325 as_bad ("Unsupported reloc size %d", nbytes
);
6327 fix_new_exp (frag_now
, where
, (int) nbytes
, exp
, 0,
6330 : (nbytes
== 4 ? BFD_RELOC_32
: BFD_RELOC_64
)));
6333 /* Sort any unmatched HI16_S relocs so that they immediately precede
6334 the corresponding LO reloc. This is called before md_apply_fix and
6335 tc_gen_reloc. Unmatched HI16_S relocs can only be generated by
6336 explicit use of the %hi modifier. */
6341 struct mips_hi_fixup
*l
;
6343 for (l
= mips_hi_fixup_list
; l
!= NULL
; l
= l
->next
)
6345 segment_info_type
*seginfo
;
6348 assert (l
->fixp
->fx_r_type
== BFD_RELOC_HI16_S
);
6350 /* Check quickly whether the next fixup happens to be a matching
6352 if (l
->fixp
->fx_next
!= NULL
6353 && l
->fixp
->fx_next
->fx_r_type
== BFD_RELOC_LO16
6354 && l
->fixp
->fx_addsy
== l
->fixp
->fx_next
->fx_addsy
6355 && l
->fixp
->fx_offset
== l
->fixp
->fx_next
->fx_offset
)
6358 /* Look through the fixups for this segment for a matching %lo.
6359 When we find one, move the %hi just in front of it. We do
6360 this in two passes. In the first pass, we try to find a
6361 unique %lo. In the second pass, we permit multiple %hi
6362 relocs for a single %lo (this is a GNU extension). */
6363 seginfo
= seg_info (l
->seg
);
6364 for (pass
= 0; pass
< 2; pass
++)
6369 for (f
= seginfo
->fix_root
; f
!= NULL
; f
= f
->fx_next
)
6371 /* Check whether this is a %lo fixup which matches l->fixp. */
6372 if (f
->fx_r_type
== BFD_RELOC_LO16
6373 && f
->fx_addsy
== l
->fixp
->fx_addsy
6374 && f
->fx_offset
== l
->fixp
->fx_offset
6377 || prev
->fx_r_type
!= BFD_RELOC_HI16_S
6378 || prev
->fx_addsy
!= f
->fx_addsy
6379 || prev
->fx_offset
!= f
->fx_offset
))
6383 /* Move l->fixp before f. */
6384 for (pf
= &seginfo
->fix_root
;
6386 pf
= &(*pf
)->fx_next
)
6387 assert (*pf
!= NULL
);
6389 *pf
= l
->fixp
->fx_next
;
6391 l
->fixp
->fx_next
= f
;
6393 seginfo
->fix_root
= l
->fixp
;
6395 prev
->fx_next
= l
->fixp
;
6407 as_warn_where (l
->fixp
->fx_file
, l
->fixp
->fx_line
,
6408 "Unmatched %%hi reloc");
6413 /* When generating embedded PIC code we need to use a special
6414 relocation to represent the difference of two symbols in the .text
6415 section (switch tables use a difference of this sort). See
6416 include/coff/mips.h for details. This macro checks whether this
6417 fixup requires the special reloc. */
6418 #define SWITCH_TABLE(fixp) \
6419 ((fixp)->fx_r_type == BFD_RELOC_32 \
6420 && (fixp)->fx_addsy != NULL \
6421 && (fixp)->fx_subsy != NULL \
6422 && S_GET_SEGMENT ((fixp)->fx_addsy) == text_section \
6423 && S_GET_SEGMENT ((fixp)->fx_subsy) == text_section)
6425 /* When generating embedded PIC code we must keep all PC relative
6426 relocations, in case the linker has to relax a call. We also need
6427 to keep relocations for switch table entries. */
6431 mips_force_relocation (fixp
)
6434 return (mips_pic
== EMBEDDED_PIC
6436 || SWITCH_TABLE (fixp
)
6437 || fixp
->fx_r_type
== BFD_RELOC_PCREL_HI16_S
6438 || fixp
->fx_r_type
== BFD_RELOC_PCREL_LO16
));
6441 /* Apply a fixup to the object file. */
6444 md_apply_fix (fixP
, valueP
)
6451 assert (fixP
->fx_size
== 4 || fixP
->fx_r_type
== BFD_RELOC_16
);
6454 fixP
->fx_addnumber
= value
; /* Remember value for tc_gen_reloc */
6456 if (fixP
->fx_addsy
== NULL
&& ! fixP
->fx_pcrel
)
6459 switch (fixP
->fx_r_type
)
6461 case BFD_RELOC_MIPS_JMP
:
6462 case BFD_RELOC_HI16
:
6463 case BFD_RELOC_HI16_S
:
6464 case BFD_RELOC_MIPS_GPREL
:
6465 case BFD_RELOC_MIPS_LITERAL
:
6466 case BFD_RELOC_MIPS_CALL16
:
6467 case BFD_RELOC_MIPS_GOT16
:
6468 case BFD_RELOC_MIPS_GPREL32
:
6469 case BFD_RELOC_MIPS_GOT_HI16
:
6470 case BFD_RELOC_MIPS_GOT_LO16
:
6471 case BFD_RELOC_MIPS_CALL_HI16
:
6472 case BFD_RELOC_MIPS_CALL_LO16
:
6474 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
6475 "Invalid PC relative reloc");
6476 /* Nothing needed to do. The value comes from the reloc entry */
6479 case BFD_RELOC_PCREL_HI16_S
:
6480 /* The addend for this is tricky if it is internal, so we just
6481 do everything here rather than in bfd_perform_relocation. */
6482 if ((fixP
->fx_addsy
->bsym
->flags
& BSF_SECTION_SYM
) == 0)
6484 /* For an external symbol adjust by the address to make it
6485 pcrel_offset. We use the address of the RELLO reloc
6486 which follows this one. */
6487 value
+= (fixP
->fx_next
->fx_frag
->fr_address
6488 + fixP
->fx_next
->fx_where
);
6493 buf
= (unsigned char *) fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
6494 if (byte_order
== BIG_ENDIAN
)
6496 md_number_to_chars (buf
, value
, 2);
6499 case BFD_RELOC_PCREL_LO16
:
6500 /* The addend for this is tricky if it is internal, so we just
6501 do everything here rather than in bfd_perform_relocation. */
6502 if ((fixP
->fx_addsy
->bsym
->flags
& BSF_SECTION_SYM
) == 0)
6503 value
+= fixP
->fx_frag
->fr_address
+ fixP
->fx_where
;
6504 buf
= (unsigned char *) fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
6505 if (byte_order
== BIG_ENDIAN
)
6507 md_number_to_chars (buf
, value
, 2);
6511 /* If we are deleting this reloc entry, we must fill in the
6512 value now. This can happen if we have a .word which is not
6513 resolved when it appears but is later defined. We also need
6514 to fill in the value if this is an embedded PIC switch table
6517 || (mips_pic
== EMBEDDED_PIC
&& SWITCH_TABLE (fixP
)))
6518 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
,
6523 /* If we are deleting this reloc entry, we must fill in the
6525 assert (fixP
->fx_size
== 2);
6527 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
,
6531 case BFD_RELOC_LO16
:
6532 /* When handling an embedded PIC switch statement, we can wind
6533 up deleting a LO16 reloc. See the 'o' case in mips_ip. */
6536 if (value
< -0x8000 || value
> 0x7fff)
6537 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
6538 "relocation overflow");
6539 buf
= (unsigned char *) fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
6540 if (byte_order
== BIG_ENDIAN
)
6542 md_number_to_chars (buf
, value
, 2);
6546 case BFD_RELOC_16_PCREL_S2
:
6548 * We need to save the bits in the instruction since fixup_segment()
6549 * might be deleting the relocation entry (i.e., a branch within
6550 * the current segment).
6553 as_warn_where (fixP
->fx_file
, fixP
->fx_line
,
6554 "Branch to odd address (%lx)", value
);
6557 /* update old instruction data */
6558 buf
= (unsigned char *) (fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
);
6562 insn
= (buf
[3] << 24) | (buf
[2] << 16) | (buf
[1] << 8) | buf
[0];
6566 insn
= (buf
[0] << 24) | (buf
[1] << 16) | (buf
[2] << 8) | buf
[3];
6574 if (value
>= -0x8000 && value
< 0x8000)
6575 insn
|= value
& 0xffff;
6578 /* The branch offset is too large. If this is an
6579 unconditional branch, and we are not generating PIC code,
6580 we can convert it to an absolute jump instruction. */
6581 if (mips_pic
== NO_PIC
6583 && fixP
->fx_frag
->fr_address
>= text_section
->vma
6584 && (fixP
->fx_frag
->fr_address
6585 < text_section
->vma
+ text_section
->_raw_size
)
6586 && ((insn
& 0xffff0000) == 0x10000000 /* beq $0,$0 */
6587 || (insn
& 0xffff0000) == 0x04010000 /* bgez $0 */
6588 || (insn
& 0xffff0000) == 0x04110000)) /* bgezal $0 */
6590 if ((insn
& 0xffff0000) == 0x04110000) /* bgezal $0 */
6591 insn
= 0x0c000000; /* jal */
6593 insn
= 0x08000000; /* j */
6594 fixP
->fx_r_type
= BFD_RELOC_MIPS_JMP
;
6596 fixP
->fx_addsy
= section_symbol (text_section
);
6597 fixP
->fx_addnumber
= (value
<< 2) + md_pcrel_from (fixP
);
6601 /* FIXME. It would be possible in principle to handle
6602 conditional branches which overflow. They could be
6603 transformed into a branch around a jump. This would
6604 require setting up variant frags for each different
6605 branch type. The native MIPS assembler attempts to
6606 handle these cases, but it appears to do it
6608 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
6609 "Relocation overflow");
6613 md_number_to_chars ((char *) buf
, (valueT
) insn
, 4);
6628 const struct mips_opcode
*p
;
6629 int treg
, sreg
, dreg
, shamt
;
6634 for (i
= 0; i
< NUMOPCODES
; ++i
)
6636 p
= &mips_opcodes
[i
];
6637 if (((oc
& p
->mask
) == p
->match
) && (p
->pinfo
!= INSN_MACRO
))
6639 printf ("%08lx %s\t", oc
, p
->name
);
6640 treg
= (oc
>> 16) & 0x1f;
6641 sreg
= (oc
>> 21) & 0x1f;
6642 dreg
= (oc
>> 11) & 0x1f;
6643 shamt
= (oc
>> 6) & 0x1f;
6645 for (args
= p
->args
;; ++args
)
6656 printf ("%c", *args
);
6660 assert (treg
== sreg
);
6661 printf ("$%d,$%d", treg
, sreg
);
6666 printf ("$%d", dreg
);
6671 printf ("$%d", treg
);
6675 printf ("0x%x", treg
);
6680 printf ("$%d", sreg
);
6684 printf ("0x%08lx", oc
& 0x1ffffff);
6696 printf ("$%d", shamt
);
6707 printf ("%08lx UNDEFINED\n", oc
);
6718 name
= input_line_pointer
;
6719 c
= get_symbol_end ();
6720 p
= (symbolS
*) symbol_find_or_make (name
);
6721 *input_line_pointer
= c
;
6725 /* Align the current frag to a given power of two. The MIPS assembler
6726 also automatically adjusts any preceding label. */
6729 mips_align (to
, fill
, label
)
6734 mips_emit_delays ();
6735 frag_align (to
, fill
);
6736 record_alignment (now_seg
, to
);
6739 assert (S_GET_SEGMENT (label
) == now_seg
);
6740 label
->sy_frag
= frag_now
;
6741 S_SET_VALUE (label
, (valueT
) frag_now_fix ());
6745 /* Align to a given power of two. .align 0 turns off the automatic
6746 alignment used by the data creating pseudo-ops. */
6753 register long temp_fill
;
6754 long max_alignment
= 15;
6758 o Note that the assembler pulls down any immediately preceeding label
6759 to the aligned address.
6760 o It's not documented but auto alignment is reinstated by
6761 a .align pseudo instruction.
6762 o Note also that after auto alignment is turned off the mips assembler
6763 issues an error on attempt to assemble an improperly aligned data item.
6768 temp
= get_absolute_expression ();
6769 if (temp
> max_alignment
)
6770 as_bad ("Alignment too large: %d. assumed.", temp
= max_alignment
);
6773 as_warn ("Alignment negative: 0 assumed.");
6776 if (*input_line_pointer
== ',')
6778 input_line_pointer
++;
6779 temp_fill
= get_absolute_expression ();
6786 mips_align (temp
, (int) temp_fill
, insn_label
);
6793 demand_empty_rest_of_line ();
6797 mips_flush_pending_output ()
6799 mips_emit_delays ();
6809 /* When generating embedded PIC code, we only use the .text, .lit8,
6810 .sdata and .sbss sections. We change the .data and .rdata
6811 pseudo-ops to use .sdata. */
6812 if (mips_pic
== EMBEDDED_PIC
6813 && (sec
== 'd' || sec
== 'r'))
6816 mips_emit_delays ();
6826 subseg_set (bss_section
, (subsegT
) get_absolute_expression ());
6827 demand_empty_rest_of_line ();
6831 if (USE_GLOBAL_POINTER_OPT
)
6833 seg
= subseg_new (RDATA_SECTION_NAME
,
6834 (subsegT
) get_absolute_expression ());
6835 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
6837 bfd_set_section_flags (stdoutput
, seg
,
6843 bfd_set_section_alignment (stdoutput
, seg
, 4);
6845 demand_empty_rest_of_line ();
6849 as_bad ("No read only data section in this object file format");
6850 demand_empty_rest_of_line ();
6856 if (USE_GLOBAL_POINTER_OPT
)
6858 seg
= subseg_new (".sdata", (subsegT
) get_absolute_expression ());
6859 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
6861 bfd_set_section_flags (stdoutput
, seg
,
6862 SEC_ALLOC
| SEC_LOAD
| SEC_RELOC
6864 bfd_set_section_alignment (stdoutput
, seg
, 4);
6866 demand_empty_rest_of_line ();
6871 as_bad ("Global pointers not supported; recompile -G 0");
6872 demand_empty_rest_of_line ();
6881 mips_enable_auto_align ()
6893 mips_emit_delays ();
6894 if (log_size
> 0 && auto_align
)
6895 mips_align (log_size
, 0, label
);
6897 cons (1 << log_size
);
6908 mips_emit_delays ();
6912 mips_align (3, 0, label
);
6914 mips_align (2, 0, label
);
6921 /* Handle .globl. We need to override it because on Irix 5 you are
6924 where foo is an undefined symbol, to mean that foo should be
6925 considered to be the address of a function. */
6936 name
= input_line_pointer
;
6937 c
= get_symbol_end ();
6938 symbolP
= symbol_find_or_make (name
);
6939 *input_line_pointer
= c
;
6942 /* On Irix 5, every global symbol that is not explicitly labelled as
6943 being a function is apparently labelled as being an object. */
6946 if (! is_end_of_line
[(unsigned char) *input_line_pointer
])
6951 secname
= input_line_pointer
;
6952 c
= get_symbol_end ();
6953 sec
= bfd_get_section_by_name (stdoutput
, secname
);
6955 as_bad ("%s: no such section", secname
);
6956 *input_line_pointer
= c
;
6958 if (sec
!= NULL
&& (sec
->flags
& SEC_CODE
) != 0)
6959 flag
= BSF_FUNCTION
;
6962 symbolP
->bsym
->flags
|= flag
;
6964 S_SET_EXTERNAL (symbolP
);
6965 demand_empty_rest_of_line ();
6975 opt
= input_line_pointer
;
6976 c
= get_symbol_end ();
6980 /* FIXME: What does this mean? */
6982 else if (strncmp (opt
, "pic", 3) == 0)
6990 mips_pic
= SVR4_PIC
;
6992 as_bad (".option pic%d not supported", i
);
6994 if (USE_GLOBAL_POINTER_OPT
&& mips_pic
== SVR4_PIC
)
6996 if (g_switch_seen
&& g_switch_value
!= 0)
6997 as_warn ("-G may not be used with SVR4 PIC code");
6999 bfd_set_gp_size (stdoutput
, 0);
7003 as_warn ("Unrecognized option \"%s\"", opt
);
7005 *input_line_pointer
= c
;
7006 demand_empty_rest_of_line ();
7013 char *name
= input_line_pointer
, ch
;
7015 while (!is_end_of_line
[(unsigned char) *input_line_pointer
])
7016 input_line_pointer
++;
7017 ch
= *input_line_pointer
;
7018 *input_line_pointer
= '\0';
7020 if (strcmp (name
, "reorder") == 0)
7024 prev_insn_unreordered
= 1;
7025 prev_prev_insn_unreordered
= 1;
7029 else if (strcmp (name
, "noreorder") == 0)
7031 mips_emit_delays ();
7033 mips_any_noreorder
= 1;
7035 else if (strcmp (name
, "at") == 0)
7039 else if (strcmp (name
, "noat") == 0)
7043 else if (strcmp (name
, "macro") == 0)
7045 mips_warn_about_macros
= 0;
7047 else if (strcmp (name
, "nomacro") == 0)
7049 if (mips_noreorder
== 0)
7050 as_bad ("`noreorder' must be set before `nomacro'");
7051 mips_warn_about_macros
= 1;
7053 else if (strcmp (name
, "move") == 0 || strcmp (name
, "novolatile") == 0)
7057 else if (strcmp (name
, "nomove") == 0 || strcmp (name
, "volatile") == 0)
7061 else if (strcmp (name
, "bopt") == 0)
7065 else if (strcmp (name
, "nobopt") == 0)
7069 else if (strncmp (name
, "mips", 4) == 0)
7073 /* Permit the user to change the ISA on the fly. Needless to
7074 say, misuse can cause serious problems. */
7075 isa
= atoi (name
+ 4);
7077 mips_isa
= file_mips_isa
;
7078 else if (isa
< 1 || isa
> 4)
7079 as_bad ("unknown ISA level");
7085 as_warn ("Tried to set unrecognized symbol: %s\n", name
);
7087 *input_line_pointer
= ch
;
7088 demand_empty_rest_of_line ();
7091 /* Handle the .abicalls pseudo-op. I believe this is equivalent to
7092 .option pic2. It means to generate SVR4 PIC calls. */
7098 mips_pic
= SVR4_PIC
;
7099 if (USE_GLOBAL_POINTER_OPT
)
7101 if (g_switch_seen
&& g_switch_value
!= 0)
7102 as_warn ("-G may not be used with SVR4 PIC code");
7105 bfd_set_gp_size (stdoutput
, 0);
7106 demand_empty_rest_of_line ();
7109 /* Handle the .cpload pseudo-op. This is used when generating SVR4
7110 PIC code. It sets the $gp register for the function based on the
7111 function address, which is in the register named in the argument.
7112 This uses a relocation against _gp_disp, which is handled specially
7113 by the linker. The result is:
7114 lui $gp,%hi(_gp_disp)
7115 addiu $gp,$gp,%lo(_gp_disp)
7116 addu $gp,$gp,.cpload argument
7117 The .cpload argument is normally $25 == $t9. */
7126 /* If we are not generating SVR4 PIC code, .cpload is ignored. */
7127 if (mips_pic
!= SVR4_PIC
)
7133 /* .cpload should be a in .set noreorder section. */
7134 if (mips_noreorder
== 0)
7135 as_warn (".cpload not in noreorder section");
7138 ex
.X_add_symbol
= symbol_find_or_make ("_gp_disp");
7139 ex
.X_op_symbol
= NULL
;
7140 ex
.X_add_number
= 0;
7142 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
7143 ex
.X_add_symbol
->bsym
->flags
|= BSF_OBJECT
;
7145 macro_build_lui ((char *) NULL
, &icnt
, &ex
, GP
);
7146 macro_build ((char *) NULL
, &icnt
, &ex
, "addiu", "t,r,j", GP
, GP
,
7147 (int) BFD_RELOC_LO16
);
7149 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "addu", "d,v,t",
7150 GP
, GP
, tc_get_register (0));
7152 demand_empty_rest_of_line ();
7155 /* Handle the .cprestore pseudo-op. This stores $gp into a given
7156 offset from $sp. The offset is remembered, and after making a PIC
7157 call $gp is restored from that location. */
7160 s_cprestore (ignore
)
7166 /* If we are not generating SVR4 PIC code, .cprestore is ignored. */
7167 if (mips_pic
!= SVR4_PIC
)
7173 mips_cprestore_offset
= get_absolute_expression ();
7175 ex
.X_op
= O_constant
;
7176 ex
.X_add_symbol
= NULL
;
7177 ex
.X_op_symbol
= NULL
;
7178 ex
.X_add_number
= mips_cprestore_offset
;
7180 macro_build ((char *) NULL
, &icnt
, &ex
,
7181 mips_isa
< 3 ? "sw" : "sd",
7182 "t,o(b)", GP
, (int) BFD_RELOC_LO16
, SP
);
7184 demand_empty_rest_of_line ();
7187 /* Handle the .gpword pseudo-op. This is used when generating PIC
7188 code. It generates a 32 bit GP relative reloc. */
7198 /* When not generating PIC code, this is treated as .word. */
7199 if (mips_pic
!= SVR4_PIC
)
7206 mips_emit_delays ();
7208 mips_align (2, 0, label
);
7213 if (ex
.X_op
!= O_symbol
|| ex
.X_add_number
!= 0)
7215 as_bad ("Unsupported use of .gpword");
7216 ignore_rest_of_line ();
7220 md_number_to_chars (p
, (valueT
) 0, 4);
7221 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 4, &ex
, 0,
7222 BFD_RELOC_MIPS_GPREL32
);
7224 demand_empty_rest_of_line ();
7227 /* Handle the .cpadd pseudo-op. This is used when dealing with switch
7228 tables in SVR4 PIC code. */
7237 /* This is ignored when not generating SVR4 PIC code. */
7238 if (mips_pic
!= SVR4_PIC
)
7244 /* Add $gp to the register named as an argument. */
7245 reg
= tc_get_register (0);
7246 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
7247 mips_isa
< 3 ? "addu" : "daddu",
7248 "d,v,t", reg
, reg
, GP
);
7250 demand_empty_rest_of_line ();
7253 /* Parse a register string into a number. Called from the ECOFF code
7254 to parse .frame. The argument is non-zero if this is the frame
7255 register, so that we can record it in mips_frame_reg. */
7258 tc_get_register (frame
)
7264 if (*input_line_pointer
++ != '$')
7266 as_warn ("expected `$'");
7269 else if (isdigit ((unsigned char) *input_line_pointer
))
7271 reg
= get_absolute_expression ();
7272 if (reg
< 0 || reg
>= 32)
7274 as_warn ("Bad register number");
7280 if (strncmp (input_line_pointer
, "fp", 2) == 0)
7282 else if (strncmp (input_line_pointer
, "sp", 2) == 0)
7284 else if (strncmp (input_line_pointer
, "gp", 2) == 0)
7286 else if (strncmp (input_line_pointer
, "at", 2) == 0)
7290 as_warn ("Unrecognized register name");
7293 input_line_pointer
+= 2;
7296 mips_frame_reg
= reg
!= 0 ? reg
: SP
;
7301 md_section_align (seg
, addr
)
7305 int align
= bfd_get_section_alignment (stdoutput
, seg
);
7307 return ((addr
+ (1 << align
) - 1) & (-1 << align
));
7310 /* Utility routine, called from above as well. If called while the
7311 input file is still being read, it's only an approximation. (For
7312 example, a symbol may later become defined which appeared to be
7313 undefined earlier.) */
7316 nopic_need_relax (sym
)
7322 if (USE_GLOBAL_POINTER_OPT
)
7324 const char *symname
;
7327 /* Find out whether this symbol can be referenced off the GP
7328 register. It can be if it is smaller than the -G size or if
7329 it is in the .sdata or .sbss section. Certain symbols can
7330 not be referenced off the GP, although it appears as though
7332 symname
= S_GET_NAME (sym
);
7333 if (symname
!= (const char *) NULL
7334 && (strcmp (symname
, "eprol") == 0
7335 || strcmp (symname
, "etext") == 0
7336 || strcmp (symname
, "_gp") == 0
7337 || strcmp (symname
, "edata") == 0
7338 || strcmp (symname
, "_fbss") == 0
7339 || strcmp (symname
, "_fdata") == 0
7340 || strcmp (symname
, "_ftext") == 0
7341 || strcmp (symname
, "end") == 0
7342 || strcmp (symname
, "_gp_disp") == 0))
7344 else if (! S_IS_DEFINED (sym
)
7346 #ifndef NO_ECOFF_DEBUGGING
7347 || (sym
->ecoff_extern_size
!= 0
7348 && sym
->ecoff_extern_size
<= g_switch_value
)
7350 || (S_GET_VALUE (sym
) != 0
7351 && S_GET_VALUE (sym
) <= g_switch_value
)))
7355 const char *segname
;
7357 segname
= segment_name (S_GET_SEGMENT (sym
));
7358 assert (strcmp (segname
, ".lit8") != 0
7359 && strcmp (segname
, ".lit4") != 0);
7360 change
= (strcmp (segname
, ".sdata") != 0
7361 && strcmp (segname
, ".sbss") != 0);
7366 /* We are not optimizing for the GP register. */
7370 /* Estimate the size of a frag before relaxing. We are not really
7371 relaxing here, and the final size is encoded in the subtype
7376 md_estimate_size_before_relax (fragp
, segtype
)
7382 if (mips_pic
== NO_PIC
)
7384 change
= nopic_need_relax (fragp
->fr_symbol
);
7386 else if (mips_pic
== SVR4_PIC
)
7388 asection
*symsec
= fragp
->fr_symbol
->bsym
->section
;
7390 /* This must duplicate the test in adjust_reloc_syms. */
7391 change
= (symsec
!= &bfd_und_section
7392 && symsec
!= &bfd_abs_section
7393 && ! bfd_is_com_section (symsec
));
7400 /* Record the offset to the first reloc in the fr_opcode field.
7401 This lets md_convert_frag and tc_gen_reloc know that the code
7402 must be expanded. */
7403 fragp
->fr_opcode
= (fragp
->fr_literal
7405 - RELAX_OLD (fragp
->fr_subtype
)
7406 + RELAX_RELOC1 (fragp
->fr_subtype
));
7407 /* FIXME: This really needs as_warn_where. */
7408 if (RELAX_WARN (fragp
->fr_subtype
))
7409 as_warn ("AT used after \".set noat\" or macro used after \".set nomacro\"");
7415 return RELAX_NEW (fragp
->fr_subtype
) - RELAX_OLD (fragp
->fr_subtype
);
7418 /* Translate internal representation of relocation info to BFD target
7422 tc_gen_reloc (section
, fixp
)
7426 static arelent
*retval
[4];
7429 reloc
= retval
[0] = (arelent
*) xmalloc (sizeof (arelent
));
7432 reloc
->sym_ptr_ptr
= &fixp
->fx_addsy
->bsym
;
7433 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
7435 if (mips_pic
== EMBEDDED_PIC
7436 && SWITCH_TABLE (fixp
))
7438 /* For a switch table entry we use a special reloc. The addend
7439 is actually the difference between the reloc address and the
7441 reloc
->addend
= reloc
->address
- S_GET_VALUE (fixp
->fx_subsy
);
7442 if (OUTPUT_FLAVOR
!= bfd_target_ecoff_flavour
)
7443 as_fatal ("Double check fx_r_type in tc-mips.c:tc_gen_reloc");
7444 fixp
->fx_r_type
= BFD_RELOC_GPREL32
;
7446 else if (fixp
->fx_r_type
== BFD_RELOC_PCREL_LO16
)
7448 /* We use a special addend for an internal RELLO reloc. */
7449 if (fixp
->fx_addsy
->bsym
->flags
& BSF_SECTION_SYM
)
7450 reloc
->addend
= reloc
->address
- S_GET_VALUE (fixp
->fx_subsy
);
7452 reloc
->addend
= fixp
->fx_addnumber
+ reloc
->address
;
7454 else if (fixp
->fx_r_type
== BFD_RELOC_PCREL_HI16_S
)
7456 assert (fixp
->fx_next
!= NULL
7457 && fixp
->fx_next
->fx_r_type
== BFD_RELOC_PCREL_LO16
);
7458 /* We use a special addend for an internal RELHI reloc. The
7459 reloc is relative to the RELLO; adjust the addend
7461 if (fixp
->fx_addsy
->bsym
->flags
& BSF_SECTION_SYM
)
7462 reloc
->addend
= (fixp
->fx_next
->fx_frag
->fr_address
7463 + fixp
->fx_next
->fx_where
7464 - S_GET_VALUE (fixp
->fx_subsy
));
7466 reloc
->addend
= (fixp
->fx_addnumber
7467 + fixp
->fx_next
->fx_frag
->fr_address
7468 + fixp
->fx_next
->fx_where
);
7470 else if (fixp
->fx_pcrel
== 0)
7471 reloc
->addend
= fixp
->fx_addnumber
;
7474 if (OUTPUT_FLAVOR
!= bfd_target_aout_flavour
)
7475 /* A gruesome hack which is a result of the gruesome gas reloc
7477 reloc
->addend
= reloc
->address
;
7479 reloc
->addend
= -reloc
->address
;
7482 /* If this is a variant frag, we may need to adjust the existing
7483 reloc and generate a new one. */
7484 if (fixp
->fx_frag
->fr_opcode
!= NULL
7485 && (fixp
->fx_r_type
== BFD_RELOC_MIPS_GPREL
7486 || fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT16
7487 || fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL16
7488 || fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT_HI16
7489 || fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT_LO16
7490 || fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL_HI16
7491 || fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL_LO16
))
7495 /* If this is not the last reloc in this frag, then we have two
7496 GPREL relocs, or a GOT_HI16/GOT_LO16 pair, or a
7497 CALL_HI16/CALL_LO16, both of which are being replaced. Let
7498 the second one handle all of them. */
7499 if (fixp
->fx_next
!= NULL
7500 && fixp
->fx_frag
== fixp
->fx_next
->fx_frag
)
7502 assert ((fixp
->fx_r_type
== BFD_RELOC_MIPS_GPREL
7503 && fixp
->fx_next
->fx_r_type
== BFD_RELOC_MIPS_GPREL
)
7504 || (fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT_HI16
7505 && (fixp
->fx_next
->fx_r_type
7506 == BFD_RELOC_MIPS_GOT_LO16
))
7507 || (fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL_HI16
7508 && (fixp
->fx_next
->fx_r_type
7509 == BFD_RELOC_MIPS_CALL_LO16
)));
7514 fixp
->fx_where
= fixp
->fx_frag
->fr_opcode
- fixp
->fx_frag
->fr_literal
;
7515 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
7516 reloc2
= retval
[1] = (arelent
*) xmalloc (sizeof (arelent
));
7518 reloc2
->sym_ptr_ptr
= &fixp
->fx_addsy
->bsym
;
7519 reloc2
->address
= (reloc
->address
7520 + (RELAX_RELOC2 (fixp
->fx_frag
->fr_subtype
)
7521 - RELAX_RELOC1 (fixp
->fx_frag
->fr_subtype
)));
7522 reloc2
->addend
= fixp
->fx_addnumber
;
7523 reloc2
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_LO16
);
7524 assert (reloc2
->howto
!= NULL
);
7526 if (RELAX_RELOC3 (fixp
->fx_frag
->fr_subtype
))
7530 reloc3
= retval
[2] = (arelent
*) xmalloc (sizeof (arelent
));
7533 reloc3
->address
+= 4;
7536 if (mips_pic
== NO_PIC
)
7538 assert (fixp
->fx_r_type
== BFD_RELOC_MIPS_GPREL
);
7539 fixp
->fx_r_type
= BFD_RELOC_HI16_S
;
7541 else if (mips_pic
== SVR4_PIC
)
7543 switch (fixp
->fx_r_type
)
7547 case BFD_RELOC_MIPS_GOT16
:
7549 case BFD_RELOC_MIPS_CALL16
:
7550 case BFD_RELOC_MIPS_GOT_LO16
:
7551 case BFD_RELOC_MIPS_CALL_LO16
:
7552 fixp
->fx_r_type
= BFD_RELOC_MIPS_GOT16
;
7560 /* To support a PC relative reloc when generating embedded PIC code
7561 for ECOFF, we use a Cygnus extension. We check for that here to
7562 make sure that we don't let such a reloc escape normally. */
7563 if (OUTPUT_FLAVOR
== bfd_target_ecoff_flavour
7564 && fixp
->fx_r_type
== BFD_RELOC_16_PCREL_S2
7565 && mips_pic
!= EMBEDDED_PIC
)
7566 reloc
->howto
= NULL
;
7568 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, fixp
->fx_r_type
);
7570 if (reloc
->howto
== NULL
)
7572 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
7573 "Can not represent relocation in this object file format");
7580 /* Convert a machine dependent frag. */
7583 md_convert_frag (abfd
, asec
, fragp
)
7591 if (fragp
->fr_opcode
== NULL
)
7594 old
= RELAX_OLD (fragp
->fr_subtype
);
7595 new = RELAX_NEW (fragp
->fr_subtype
);
7596 fixptr
= fragp
->fr_literal
+ fragp
->fr_fix
;
7599 memcpy (fixptr
- old
, fixptr
, new);
7601 fragp
->fr_fix
+= new - old
;
7604 /* This function is called whenever a label is defined. It is used
7605 when handling branch delays; if a branch has a label, we assume we
7609 mips_define_label (sym
)
7615 /* Decide whether a label is local. This is called by LOCAL_LABEL.
7616 In order to work with gcc when using mips-tfile, we must keep all
7617 local labels. However, in other cases, we want to discard them,
7618 since they are useless. */
7621 mips_local_label (name
)
7624 #ifndef NO_ECOFF_DEBUGGING
7627 && ! ecoff_debugging_seen
)
7629 /* We were called with -g, but we didn't see any debugging
7630 information. That may mean that gcc is smuggling debugging
7631 information through to mips-tfile, in which case we must
7632 generate all local labels. */
7637 /* Here it's OK to discard local labels. */
7639 return name
[0] == '$';
7642 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7644 /* Some special processing for a MIPS ELF file. */
7647 mips_elf_final_processing ()
7651 /* Write out the .reginfo section. */
7652 s
.ri_gprmask
= mips_gprmask
;
7653 s
.ri_cprmask
[0] = mips_cprmask
[0];
7654 s
.ri_cprmask
[1] = mips_cprmask
[1];
7655 s
.ri_cprmask
[2] = mips_cprmask
[2];
7656 s
.ri_cprmask
[3] = mips_cprmask
[3];
7657 /* The gp_value field is set by the MIPS ELF backend. */
7659 bfd_mips_elf32_swap_reginfo_out (stdoutput
, &s
,
7660 ((Elf32_External_RegInfo
*)
7661 mips_regmask_frag
));
7663 /* Set the MIPS ELF flag bits. FIXME: There should probably be some
7664 sort of BFD interface for this. */
7665 if (mips_any_noreorder
)
7666 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_NOREORDER
;
7667 if (mips_pic
!= NO_PIC
)
7668 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_PIC
;
7671 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */
7673 /* These functions should really be defined by the object file format,
7674 since they are related to debugging information. However, this
7675 code has to work for the a.out format, which does not define them,
7676 so we provide simple versions here. These don't actually generate
7677 any debugging information, but they do simple checking and someday
7678 somebody may make them useful. */
7682 struct loc
*loc_next
;
7683 unsigned long loc_fileno
;
7684 unsigned long loc_lineno
;
7685 unsigned long loc_offset
;
7686 unsigned short loc_delta
;
7687 unsigned short loc_count
;
7696 struct proc
*proc_next
;
7697 struct symbol
*proc_isym
;
7698 struct symbol
*proc_end
;
7699 unsigned long proc_reg_mask
;
7700 unsigned long proc_reg_offset
;
7701 unsigned long proc_fpreg_mask
;
7702 unsigned long proc_fpreg_offset
;
7703 unsigned long proc_frameoffset
;
7704 unsigned long proc_framereg
;
7705 unsigned long proc_pcreg
;
7707 struct file
*proc_file
;
7714 struct file
*file_next
;
7715 unsigned long file_fileno
;
7716 struct symbol
*file_symbol
;
7717 struct symbol
*file_end
;
7718 struct proc
*file_proc
;
7723 static struct obstack proc_frags
;
7724 static procS
*proc_lastP
;
7725 static procS
*proc_rootP
;
7726 static int numprocs
;
7731 obstack_begin (&proc_frags
, 0x2000);
7737 /* check for premature end, nesting errors, etc */
7738 if (proc_lastP
&& proc_lastP
->proc_end
== NULL
)
7739 as_warn ("missing `.end' at end of assembly");
7748 if (*input_line_pointer
== '-')
7750 ++input_line_pointer
;
7753 if (!isdigit (*input_line_pointer
))
7754 as_bad ("Expected simple number.");
7755 if (input_line_pointer
[0] == '0')
7757 if (input_line_pointer
[1] == 'x')
7759 input_line_pointer
+= 2;
7760 while (isxdigit (*input_line_pointer
))
7763 val
|= hex_value (*input_line_pointer
++);
7765 return negative
? -val
: val
;
7769 ++input_line_pointer
;
7770 while (isdigit (*input_line_pointer
))
7773 val
|= *input_line_pointer
++ - '0';
7775 return negative
? -val
: val
;
7778 if (!isdigit (*input_line_pointer
))
7780 printf (" *input_line_pointer == '%c' 0x%02x\n",
7781 *input_line_pointer
, *input_line_pointer
);
7782 as_warn ("Invalid number");
7785 while (isdigit (*input_line_pointer
))
7788 val
+= *input_line_pointer
++ - '0';
7790 return negative
? -val
: val
;
7793 /* The .file directive; just like the usual .file directive, but there
7794 is an initial number which is the ECOFF file index. */
7802 line
= get_number ();
7807 /* The .end directive. */
7815 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
7818 demand_empty_rest_of_line ();
7822 if (now_seg
!= text_section
)
7823 as_warn (".end not in text section");
7826 as_warn (".end and no .ent seen yet.");
7832 assert (S_GET_NAME (p
));
7833 if (strcmp (S_GET_NAME (p
), S_GET_NAME (proc_lastP
->proc_isym
)))
7834 as_warn (".end symbol does not match .ent symbol.");
7837 proc_lastP
->proc_end
= (symbolS
*) 1;
7840 /* The .aent and .ent directives. */
7850 symbolP
= get_symbol ();
7851 if (*input_line_pointer
== ',')
7852 input_line_pointer
++;
7854 if (isdigit (*input_line_pointer
) || *input_line_pointer
== '-')
7855 number
= get_number ();
7856 if (now_seg
!= text_section
)
7857 as_warn (".ent or .aent not in text section.");
7859 if (!aent
&& proc_lastP
&& proc_lastP
->proc_end
== NULL
)
7860 as_warn ("missing `.end'");
7864 procP
= (procS
*) obstack_alloc (&proc_frags
, sizeof (*procP
));
7865 procP
->proc_isym
= symbolP
;
7866 procP
->proc_reg_mask
= 0;
7867 procP
->proc_reg_offset
= 0;
7868 procP
->proc_fpreg_mask
= 0;
7869 procP
->proc_fpreg_offset
= 0;
7870 procP
->proc_frameoffset
= 0;
7871 procP
->proc_framereg
= 0;
7872 procP
->proc_pcreg
= 0;
7873 procP
->proc_end
= NULL
;
7874 procP
->proc_next
= NULL
;
7876 proc_lastP
->proc_next
= procP
;
7882 demand_empty_rest_of_line ();
7885 /* The .frame directive. */
7898 frame_reg
= tc_get_register (1);
7899 if (*input_line_pointer
== ',')
7900 input_line_pointer
++;
7901 frame_off
= get_absolute_expression ();
7902 if (*input_line_pointer
== ',')
7903 input_line_pointer
++;
7904 pcreg
= tc_get_register (0);
7907 assert (proc_rootP
);
7908 proc_rootP
->proc_framereg
= frame_reg
;
7909 proc_rootP
->proc_frameoffset
= frame_off
;
7910 proc_rootP
->proc_pcreg
= pcreg
;
7911 /* bob macho .frame */
7913 /* We don't have to write out a frame stab for unoptimized code. */
7914 if (!(frame_reg
== FP
&& frame_off
== 0))
7917 as_warn ("No .ent for .frame to use.");
7918 (void) sprintf (str
, "R%d;%d", frame_reg
, frame_off
);
7919 symP
= symbol_new (str
, N_VFP
, 0, frag_now
);
7920 S_SET_TYPE (symP
, N_RMASK
);
7921 S_SET_OTHER (symP
, 0);
7922 S_SET_DESC (symP
, 0);
7923 symP
->sy_forward
= proc_lastP
->proc_isym
;
7924 /* bob perhaps I should have used pseudo set */
7926 demand_empty_rest_of_line ();
7930 /* The .fmask and .mask directives. */
7937 char str
[100], *strP
;
7943 mask
= get_number ();
7944 if (*input_line_pointer
== ',')
7945 input_line_pointer
++;
7946 off
= get_absolute_expression ();
7948 /* bob only for coff */
7949 assert (proc_rootP
);
7950 if (reg_type
== 'F')
7952 proc_rootP
->proc_fpreg_mask
= mask
;
7953 proc_rootP
->proc_fpreg_offset
= off
;
7957 proc_rootP
->proc_reg_mask
= mask
;
7958 proc_rootP
->proc_reg_offset
= off
;
7961 /* bob macho .mask + .fmask */
7963 /* We don't have to write out a mask stab if no saved regs. */
7967 as_warn ("No .ent for .mask to use.");
7969 for (i
= 0; i
< 32; i
++)
7973 sprintf (strP
, "%c%d,", reg_type
, i
);
7974 strP
+= strlen (strP
);
7978 sprintf (strP
, ";%d,", off
);
7979 symP
= symbol_new (str
, N_RMASK
, 0, frag_now
);
7980 S_SET_TYPE (symP
, N_RMASK
);
7981 S_SET_OTHER (symP
, 0);
7982 S_SET_DESC (symP
, 0);
7983 symP
->sy_forward
= proc_lastP
->proc_isym
;
7984 /* bob perhaps I should have used pseudo set */
7989 /* The .loc directive. */
8000 assert (now_seg
== text_section
);
8002 lineno
= get_number ();
8003 addroff
= frag_now_fix ();
8005 symbolP
= symbol_new ("", N_SLINE
, addroff
, frag_now
);
8006 S_SET_TYPE (symbolP
, N_SLINE
);
8007 S_SET_OTHER (symbolP
, 0);
8008 S_SET_DESC (symbolP
, lineno
);
8009 symbolP
->sy_segment
= now_seg
;