1 /* tc-mips.c -- assemble code for a MIPS chip.
2 Copyright (C) 1993 Free Software Foundation, Inc.
3 Contributed by the OSF and Ralph Campbell.
4 Written by Keith Knowles and Ralph Campbell, working independently.
5 Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus
8 This file is part of GAS.
10 GAS is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 2, or (at your option)
15 GAS is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with GAS; see the file COPYING. If not, write to
22 the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */
40 #endif /* NO_VARARGS */
41 #endif /* NO_STDARG */
43 #include "opcode/mips.h"
49 /* MIPS ISA (Instruction Set Architecture) level. */
50 static int mips_isa
= -1;
52 static int mips_warn_about_macros
;
53 static int mips_noreorder
;
54 static int mips_nomove
;
56 static int mips_nobopt
;
59 /* The size of the small data section. */
60 static int g_switch_value
= 8;
66 /* handle of the OPCODE hash table */
67 static struct hash_control
*op_hash
= NULL
;
69 /* This array holds the chars that always start a comment. If the
70 pre-processor is disabled, these aren't very useful */
71 const char comment_chars
[] = "#";
73 /* This array holds the chars that only start a comment at the beginning of
74 a line. If the line seems to have the form '# 123 filename'
75 .line and .file directives will appear in the pre-processed output */
76 /* Note that input_file.c hand checks for '#' at the beginning of the
77 first line of the input file. This is because the compiler outputs
78 #NO_APP at the beginning of its output. */
79 /* Also note that C style comments are always supported. */
80 const char line_comment_chars
[] = "#";
82 /* This array holds machine specific line separator characters. */
83 const char line_separator_chars
[] = "";
85 /* Chars that can be used to separate mant from exp in floating point nums */
86 const char EXP_CHARS
[] = "eE";
88 /* Chars that mean this number is a floating point constant */
91 const char FLT_CHARS
[] = "rRsSfFdDxXpP";
93 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
94 changed in read.c . Ideally it shouldn't have to know about it at all,
95 but nothing is ideal around here.
98 static char *insn_error
;
100 static int byte_order
= BYTE_ORDER
;
102 static int auto_align
= 1;
104 /* Symbol labelling the current insn. */
105 static symbolS
*insn_label
;
107 /* To output NOP instructions correctly, we need to keep information
108 about the previous two instructions. */
110 /* Whether we are optimizing. The default value of 2 means to remove
111 unneeded NOPs and swap branch instructions when possible. A value
112 of 1 means to not swap branches. A value of 0 means to always
114 static int mips_optimize
= 2;
116 /* The previous instruction. */
117 static struct mips_cl_insn prev_insn
;
119 /* The instruction before prev_insn. */
120 static struct mips_cl_insn prev_prev_insn
;
122 /* If we don't want information for prev_insn or prev_prev_insn, we
123 point the insn_mo field at this dummy integer. */
124 static const struct mips_opcode dummy_opcode
= { 0 };
126 /* Non-zero if prev_insn is valid. */
127 static int prev_insn_valid
;
129 /* The frag for the previous instruction. */
130 static struct frag
*prev_insn_frag
;
132 /* The offset into prev_insn_frag for the previous instruction. */
133 static long prev_insn_where
;
135 /* The reloc for the previous instruction, if any. */
136 static fixS
*prev_insn_fixp
;
138 /* Non-zero if the previous instruction was in a delay slot. */
139 static int prev_insn_is_delay_slot
;
141 /* Non-zero if the previous instruction was in a .set noreorder. */
142 static int prev_insn_unreordered
;
144 /* Non-zero if the previous previous instruction was in a .set
146 static int prev_prev_insn_unreordered
;
148 /* Prototypes for static functions. */
151 #define internalError() \
152 as_fatal ("internal Error, line %d, %s", __LINE__, __FILE__)
154 #define internalError() as_fatal ("MIPS internal Error");
157 static int insn_uses_reg
PARAMS ((struct mips_cl_insn
*ip
,
159 static void append_insn
PARAMS ((struct mips_cl_insn
* ip
,
161 bfd_reloc_code_real_type r
));
162 static void mips_no_prev_insn
PARAMS ((void));
163 static void mips_emit_delays
PARAMS ((void));
164 static int gp_reference
PARAMS ((expressionS
* ep
));
165 static void macro_build
PARAMS ((int *counter
, expressionS
* ep
,
166 const char *name
, const char *fmt
,
168 static void macro_build_lui
PARAMS ((int *counter
, expressionS
* ep
,
170 static void set_at
PARAMS ((int *counter
, int reg
));
171 static void set_at_unsigned
PARAMS ((int *counter
, int reg
));
172 static void check_absolute_expr
PARAMS ((struct mips_cl_insn
* ip
,
174 static void load_register
PARAMS ((int *counter
,
175 struct mips_cl_insn
* ip
,
176 int reg
, expressionS
* ep
));
177 static void macro
PARAMS ((struct mips_cl_insn
* ip
));
178 static void mips_ip
PARAMS ((char *str
, struct mips_cl_insn
* ip
));
179 static int my_getSmallExpression
PARAMS ((expressionS
* ep
, char *str
));
180 static void my_getExpression
PARAMS ((expressionS
* ep
, char *str
));
181 static symbolS
*get_symbol
PARAMS ((void));
182 static void mips_align
PARAMS ((int to
, int fill
));
183 static void s_align
PARAMS ((int));
184 static void s_stringer
PARAMS ((int));
185 static void s_change_sec
PARAMS ((int));
186 static void s_cons
PARAMS ((int));
187 static void s_err
PARAMS ((int));
188 static void s_extern
PARAMS ((int));
189 static void s_float_cons
PARAMS ((int));
190 static void s_option
PARAMS ((int));
191 static void s_mipsset
PARAMS ((int));
192 static void s_mips_space
PARAMS ((int));
194 static void md_obj_begin
PARAMS ((void));
195 static void md_obj_end
PARAMS ((void));
196 static long get_number
PARAMS ((void));
197 static void s_ent
PARAMS ((int));
198 static void s_mipsend
PARAMS ((int));
199 static void s_file
PARAMS ((int));
200 static void s_frame
PARAMS ((int));
201 static void s_loc
PARAMS ((int));
202 static void s_mask
PARAMS ((char));
207 The following pseudo-ops from the Kane and Heinrich MIPS book
208 should be defined here, but are currently unsupported: .alias,
209 .galive, .gjaldef, .gjrlive, .livereg, .noalias.
211 The following pseudo-ops from the Kane and Heinrich MIPS book are
212 specific to the type of debugging information being generated, and
213 should be defined by the object format: .aent, .begin, .bend,
214 .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp,
217 The following pseudo-ops from the Kane and Heinrich MIPS book are
218 not MIPS CPU specific, but are also not specific to the object file
219 format. This file is probably the best place to define them, but
220 they are not currently supported: .asm0, .endr, .lab, .repeat,
221 .struct, .weakext. */
223 const pseudo_typeS md_pseudo_table
[] =
225 /* MIPS specific pseudo-ops. */
226 {"option", s_option
, 0},
227 {"set", s_mipsset
, 0},
228 {"rdata", s_change_sec
, 'r',},
229 {"sdata", s_change_sec
, 's',},
231 /* Relatively generic pseudo-ops that happen to be used on MIPS
233 {"asciiz", s_stringer
, 1},
234 {"bss", s_change_sec
, 'b'},
238 /* These pseudo-ops are defined in read.c, but must be overridden
239 here for one reason or another. */
240 {"align", s_align
, 0},
241 {"ascii", s_stringer
, 0},
242 {"asciz", s_stringer
, 1},
244 {"data", s_change_sec
, 'd'},
245 {"double", s_float_cons
, 'd'},
246 {"extern", s_extern
, 0},
247 {"float", s_float_cons
, 'f'},
248 {"space", s_mips_space
, 0},
249 {"text", s_change_sec
, 't'},
253 /* These pseudo-ops should be defined by the object file format.
254 However, ECOFF is the only format which currently defines them,
255 so we have versions here for a.out. */
257 {"end", s_mipsend
, 0},
260 {"fmask", s_ignore
, 'F'},
261 {"frame", s_ignore
, 0},
262 {"loc", s_ignore
, 0},
263 {"mask", s_ignore
, 'R'},
264 {"verstamp", s_ignore
, 0},
271 const relax_typeS md_relax_table
[] =
277 static char *expr_end
;
279 static expressionS imm_expr
;
280 static expressionS offset_expr
;
281 static bfd_reloc_code_real_type imm_reloc
;
282 static bfd_reloc_code_real_type offset_reloc
;
285 * This function is called once, at assembler startup time. It should
286 * set up all the tables, etc. that the MD part of the assembler will need.
291 register char *retval
= NULL
;
292 register unsigned int i
= 0;
296 if (strcmp (TARGET_CPU
, "mips") == 0)
298 else if (strcmp (TARGET_CPU
, "r6000") == 0
299 || strcmp (TARGET_CPU
, "mips2") == 0)
301 else if (strcmp (TARGET_CPU
, "mips64") == 0
302 || strcmp (TARGET_CPU
, "r4000") == 0
303 || strcmp (TARGET_CPU
, "mips3") == 0)
309 if ((op_hash
= hash_new ()) == NULL
)
311 as_fatal ("Virtual memory exhausted");
313 for (i
= 0; i
< NUMOPCODES
;)
315 const char *name
= mips_opcodes
[i
].name
;
317 retval
= hash_insert (op_hash
, name
, &mips_opcodes
[i
]);
318 if (retval
!= NULL
&& *retval
!= '\0')
320 fprintf (stderr
, "internal error: can't hash `%s': %s\n",
321 mips_opcodes
[i
].name
, retval
);
322 as_fatal ("Broken assembler. No assembly attempted.");
326 if (mips_opcodes
[i
].pinfo
!= INSN_MACRO
327 && ((mips_opcodes
[i
].match
& mips_opcodes
[i
].mask
)
328 != mips_opcodes
[i
].match
))
330 fprintf (stderr
, "internal error: bad opcode: `%s' \"%s\"\n",
331 mips_opcodes
[i
].name
, mips_opcodes
[i
].args
);
332 as_fatal ("Broken assembler. No assembly attempted.");
336 while ((i
< NUMOPCODES
) && !strcmp (mips_opcodes
[i
].name
, name
));
339 mips_no_prev_insn ();
341 /* set the default alignment for the text section (2**2) */
342 record_alignment (text_section
, 2);
345 bfd_set_gp_size (stdoutput
, g_switch_value
);
365 struct mips_cl_insn insn
;
367 imm_expr
.X_op
= O_absent
;
368 offset_expr
.X_op
= O_absent
;
370 mips_ip (str
, &insn
);
373 as_bad ("%s `%s'", insn_error
, str
);
376 if (insn
.insn_mo
->pinfo
== INSN_MACRO
)
382 if (imm_expr
.X_op
!= O_absent
)
383 append_insn (&insn
, &imm_expr
, imm_reloc
);
384 else if (offset_expr
.X_op
!= O_absent
)
385 append_insn (&insn
, &offset_expr
, offset_reloc
);
387 append_insn (&insn
, NULL
, BFD_RELOC_UNUSED
);
391 /* See whether instruction IP reads register REG. If FPR is non-zero,
392 REG is a floating point register. */
395 insn_uses_reg (ip
, reg
, fpr
)
396 struct mips_cl_insn
*ip
;
400 /* Don't report on general register 0, since it never changes. */
401 if (! fpr
&& reg
== 0)
406 /* If we are called with either $f0 or $f1, we must check $f0.
407 This is not optimal, because it will introduce an unnecessary
408 NOP between "lwc1 $f0" and "swc1 $f1". To fix this we would
409 need to distinguish reading both $f0 and $f1 or just one of
410 them. Note that we don't have to check the other way,
411 because there is no instruction that sets both $f0 and $f1
412 and requires a delay. */
413 if ((ip
->insn_mo
->pinfo
& INSN_READ_FPR_S
)
414 && ((ip
->insn_opcode
>> OP_SH_FS
) & OP_MASK_FS
) == (reg
&~ 1))
416 if ((ip
->insn_mo
->pinfo
& INSN_READ_FPR_T
)
417 && ((ip
->insn_opcode
>> OP_SH_FT
) & OP_MASK_FT
) == (reg
&~ 1))
422 if ((ip
->insn_mo
->pinfo
& INSN_READ_GPR_S
)
423 && ((ip
->insn_opcode
>> OP_SH_RS
) & OP_MASK_RS
) == reg
)
425 if ((ip
->insn_mo
->pinfo
& INSN_READ_GPR_T
)
426 && ((ip
->insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
) == reg
)
433 #define ALIGN_ERR "Attempt to assemble instruction onto non word boundary."
434 #define ALIGN_ERR2 "GAS doesn't do implicit alignment; use .align directive."
438 * Output an instruction.
441 append_insn (ip
, address_expr
, reloc_type
)
442 struct mips_cl_insn
*ip
;
443 expressionS
*address_expr
;
444 bfd_reloc_code_real_type reloc_type
;
450 if (! mips_noreorder
)
452 /* If the previous insn required any delay slots, see if we need
453 to insert a NOP or two. There are eight kinds of possible
454 hazards, of which an instruction can have at most one type.
455 (1) a load from memory delay
456 (2) a load from a coprocessor delay
457 (3) an unconditional branch delay
458 (4) a conditional branch delay
459 (5) a move to coprocessor register delay
460 (6) a load coprocessor register from memory delay
461 (7) a coprocessor condition code delay
462 (8) a HI/LO special register delay
464 There are a lot of optimizations we could do that we don't.
465 In particular, we do not, in general, reorder instructions.
466 If you use gcc with optimization, it will reorder
467 instructions and generally do much more optimization then we
468 do here; repeating all that work in the assembler would only
469 benefit hand written assembly code, and does not seem worth
472 /* This is how a NOP is emitted. */
473 #define emit_nop() md_number_to_chars (frag_more (4), 0, 4)
475 /* The previous insn might require a delay slot, depending upon
476 the contents of the current insn. */
477 if ((prev_insn
.insn_mo
->pinfo
& INSN_LOAD_COPROC_DELAY
)
479 && (prev_insn
.insn_mo
->pinfo
& INSN_LOAD_MEMORY_DELAY
)))
481 /* A load from a coprocessor or from memory. All load
482 delays delay the use of general register rt for one
483 instruction on the r3000. The r6000 and r4000 use
485 know (prev_insn
.insn_mo
->pinfo
& INSN_WRITE_GPR_T
);
486 if (mips_optimize
== 0
487 || insn_uses_reg (ip
,
488 ((prev_insn
.insn_opcode
>> OP_SH_RT
)
493 else if ((prev_insn
.insn_mo
->pinfo
& INSN_COPROC_MOVE_DELAY
)
495 && (prev_insn
.insn_mo
->pinfo
& INSN_COPROC_MEMORY_DELAY
)))
497 /* A generic coprocessor delay. The previous instruction
498 modified a coprocessor general or control register. If
499 it modified a control register, we need to avoid any
500 coprocessor instruction (this is probably not always
501 required, but it sometimes is). If it modified a general
502 register, we avoid using that register.
504 On the r6000 and r4000 loading a coprocessor register
505 from memory is interlocked, and does not require a delay.
507 This case is not handled very well. There is no special
508 knowledge of CP0 handling, and the coprocessors other
509 than the floating point unit are not distinguished at
511 if (prev_insn
.insn_mo
->pinfo
& INSN_WRITE_FPR_T
)
513 if (mips_optimize
== 0
514 || insn_uses_reg (ip
,
515 ((prev_insn
.insn_opcode
>> OP_SH_FT
)
520 else if (prev_insn
.insn_mo
->pinfo
& INSN_WRITE_FPR_S
)
522 if (mips_optimize
== 0
523 || insn_uses_reg (ip
,
524 ((prev_insn
.insn_opcode
>> OP_SH_FS
)
531 /* We don't know exactly what the previous instruction
532 does. If the current instruction uses a coprocessor
533 register, we must insert a NOP. If previous
534 instruction may set the condition codes, and the
535 current instruction uses them, we must insert two
537 if (mips_optimize
== 0
538 || ((prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
)
539 && (ip
->insn_mo
->pinfo
& INSN_READ_COND_CODE
)))
541 else if (ip
->insn_mo
->pinfo
& INSN_COP
)
545 else if (prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
)
547 /* The previous instruction sets the coprocessor condition
548 codes, but does not require a general coprocessor delay
549 (this means it is a floating point comparison
550 instruction). If this instruction uses the condition
551 codes, we need to insert a single NOP. */
552 if (mips_optimize
== 0
553 || ip
->insn_mo
->pinfo
& INSN_READ_COND_CODE
)
556 else if (prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
)
558 /* The previous instruction reads the LO register; if the
559 current instruction writes to the LO register, we must
561 if (mips_optimize
== 0
562 || ip
->insn_mo
->pinfo
& INSN_WRITE_LO
)
565 else if (prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
567 /* The previous instruction reads the HI register; if the
568 current instruction writes to the HI register, we must
570 if (mips_optimize
== 0
571 || ip
->insn_mo
->pinfo
& INSN_WRITE_HI
)
575 /* There are two cases which require two intervening
576 instructions: 1) setting the condition codes using a move to
577 coprocessor instruction which requires a general coprocessor
578 delay and then reading the condition codes 2) reading the HI
579 or LO register and then writing to it. If we are not already
580 emitting a NOP instruction, we must check for these cases
581 compared to the instruction previous to the previous
584 && (((prev_prev_insn
.insn_mo
->pinfo
& INSN_COPROC_MOVE_DELAY
)
585 && (prev_prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
)
586 && (ip
->insn_mo
->pinfo
& INSN_READ_COND_CODE
))
587 || ((prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
)
588 && (ip
->insn_mo
->pinfo
& INSN_WRITE_LO
))
589 || ((prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
590 && (ip
->insn_mo
->pinfo
& INSN_WRITE_HI
))))
593 /* Now emit the right number of NOP instructions. */
599 if (insn_label
!= NULL
)
601 assert (S_GET_SEGMENT (insn_label
) == now_seg
);
602 insn_label
->sy_frag
= frag_now
;
603 S_SET_VALUE (insn_label
, frag_now_fix ());
610 /* This is testing the address of the frag, not the alignment of
611 the instruction in the current section. */
619 if (address_expr
!= NULL
)
621 if (address_expr
->X_op
== O_constant
)
626 ip
->insn_opcode
|= address_expr
->X_add_number
;
630 ip
->insn_opcode
|= address_expr
->X_add_number
& 0xffff;
633 case BFD_RELOC_MIPS_JMP
:
634 case BFD_RELOC_16_PCREL_S2
:
643 assert (reloc_type
!= BFD_RELOC_UNUSED
);
645 fixp
= fix_new_exp (frag_now
, f
- frag_now
->fr_literal
, 4,
647 reloc_type
== BFD_RELOC_16_PCREL_S2
,
652 md_number_to_chars (f
, ip
->insn_opcode
, 4);
654 if (! mips_noreorder
)
656 /* Filling the branch delay slot is more complex. We try to
657 switch the branch with the previous instruction, which we can
658 do if the previous instruction does not set up a condition
659 that the branch tests and if the branch is not itself the
660 target of any branch. */
661 if ((ip
->insn_mo
->pinfo
& INSN_UNCOND_BRANCH_DELAY
)
662 || (ip
->insn_mo
->pinfo
& INSN_COND_BRANCH_DELAY
))
664 if (mips_optimize
< 2
665 /* If we have seen .set nobopt, don't optimize. */
667 /* If we have seen .set volatile or .set nomove, don't
670 /* If we had to emit any NOP instructions, then we
671 already know we can not swap. */
673 /* If we don't even know the previous insn, we can not
676 /* If the previous insn is already in a branch delay
677 slot, then we can not swap. */
678 || prev_insn_is_delay_slot
679 /* If the previous previous insn was in a .set
680 noreorder, we can't swap. Actually, the MIPS
681 assembler will swap in this situation. However, gcc
682 configured -with-gnu-as will generate code like
688 in which we can not swap the bne and INSN. If gcc is
689 not configured -with-gnu-as, it does not output the
690 .set pseudo-ops. We don't have to check
691 prev_insn_unreordered, because prev_insn_valid will
692 be 0 in that case. We don't want to use
693 prev_prev_insn_valid, because we do want to be able
694 to swap at the start of a function. */
695 || prev_prev_insn_unreordered
696 /* If the branch is itself the target of a branch, we
697 can not swap. We cheat on this; all we check for is
698 whether there is a label on this instruction. If
699 there are any branches to anything other than a
700 label, users must use .set noreorder. */
701 || insn_label
!= NULL
702 /* If the branch reads the condition codes, we don't
703 even try to swap, because in the sequence
708 we can not swap, and I don't feel like handling that
710 || (ip
->insn_mo
->pinfo
& INSN_READ_COND_CODE
)
711 /* We can not swap with an instruction that requires a
712 delay slot, becase the target of the branch might
713 interfere with that instruction. */
714 || (prev_insn
.insn_mo
->pinfo
715 & (INSN_LOAD_COPROC_DELAY
716 | INSN_COPROC_MOVE_DELAY
717 | INSN_WRITE_COND_CODE
721 && (prev_insn
.insn_mo
->pinfo
722 & (INSN_LOAD_MEMORY_DELAY
723 | INSN_COPROC_MEMORY_DELAY
)))
724 /* We can not swap with a branch instruction. */
725 || (prev_insn
.insn_mo
->pinfo
726 & (INSN_UNCOND_BRANCH_DELAY
| INSN_COND_BRANCH_DELAY
))
727 /* If the branch reads a register that the previous
728 instruction sets, we can not swap. */
729 || ((prev_insn
.insn_mo
->pinfo
& INSN_WRITE_GPR_T
)
730 && insn_uses_reg (ip
,
731 ((prev_insn
.insn_opcode
>> OP_SH_RT
)
734 || ((prev_insn
.insn_mo
->pinfo
& INSN_WRITE_GPR_D
)
735 && insn_uses_reg (ip
,
736 ((prev_insn
.insn_opcode
>> OP_SH_RD
)
739 /* If the branch writes a register that the previous
740 instruction reads, we can not swap (we know that
741 branches only write to RD or to $31). */
742 || ((ip
->insn_mo
->pinfo
& INSN_WRITE_GPR_D
)
743 && insn_uses_reg (&prev_insn
,
744 ((ip
->insn_opcode
>> OP_SH_RD
)
747 || ((ip
->insn_mo
->pinfo
& INSN_WRITE_GPR_31
)
748 && insn_uses_reg (&prev_insn
, 31, 0))
749 /* If the previous previous instruction has a load
750 delay, and sets a register that the branch reads, we
752 || (((prev_prev_insn
.insn_mo
->pinfo
& INSN_LOAD_COPROC_DELAY
)
754 && (prev_prev_insn
.insn_mo
->pinfo
755 & INSN_LOAD_MEMORY_DELAY
)))
756 && insn_uses_reg (ip
,
757 ((prev_prev_insn
.insn_opcode
>> OP_SH_RT
)
761 /* We could do even better for unconditional branches to
762 portions of this object file; we could pick up the
763 instruction at the destination, put it in the delay
764 slot, and bump the destination address. */
766 /* Update the previous insn information. */
767 prev_prev_insn
= *ip
;
768 prev_insn
.insn_mo
= &dummy_opcode
;
775 /* It looks like we can actually do the swap. */
776 prev_f
= prev_insn_frag
->fr_literal
+ prev_insn_where
;
777 memcpy (temp
, prev_f
, 4);
778 memcpy (prev_f
, f
, 4);
782 prev_insn_fixp
->fx_frag
= frag_now
;
783 prev_insn_fixp
->fx_where
= f
- frag_now
->fr_literal
;
787 fixp
->fx_frag
= prev_insn_frag
;
788 fixp
->fx_where
= prev_insn_where
;
790 /* Update the previous insn information; leave prev_insn
792 prev_prev_insn
= *ip
;
794 prev_insn_is_delay_slot
= 1;
796 /* If that was an unconditional branch, forget the previous
798 if (ip
->insn_mo
->pinfo
& INSN_UNCOND_BRANCH_DELAY
)
800 prev_prev_insn
.insn_mo
= &dummy_opcode
;
801 prev_insn
.insn_mo
= &dummy_opcode
;
804 else if (ip
->insn_mo
->pinfo
& INSN_COND_BRANCH_LIKELY
)
806 /* We don't yet optimize a branch likely. What we should do
807 is look at the target, copy the instruction found there
808 into the delay slot, and increment the branch to jump to
809 the next instruction. */
811 /* Update the previous insn information. */
812 prev_prev_insn
= *ip
;
813 prev_insn
.insn_mo
= &dummy_opcode
;
817 /* Update the previous insn information. */
819 prev_prev_insn
.insn_mo
= &dummy_opcode
;
821 prev_prev_insn
= prev_insn
;
824 /* Any time we see a branch, we always fill the delay slot
825 immediately; since this insn is not a branch, we know it
826 is not in a delay slot. */
827 prev_insn_is_delay_slot
= 0;
830 prev_prev_insn_unreordered
= prev_insn_unreordered
;
831 prev_insn_unreordered
= 0;
832 prev_insn_frag
= frag_now
;
833 prev_insn_where
= f
- frag_now
->fr_literal
;
834 prev_insn_fixp
= fixp
;
838 /* We just output an insn, so the next one doesn't have a label. */
842 /* This function forgets that there was any previous instruction or
848 prev_insn
.insn_mo
= &dummy_opcode
;
849 prev_prev_insn
.insn_mo
= &dummy_opcode
;
851 prev_insn_is_delay_slot
= 0;
852 prev_insn_unreordered
= 0;
853 prev_prev_insn_unreordered
= 0;
857 /* This function must be called whenever we turn on noreorder or emit
858 something other than instructions. It inserts any NOPS which might
859 be needed by the previous instruction, and clears the information
860 kept for the previous instructions. */
865 if (! mips_noreorder
)
870 if ((prev_insn
.insn_mo
->pinfo
871 & (INSN_LOAD_COPROC_DELAY
872 | INSN_COPROC_MOVE_DELAY
873 | INSN_WRITE_COND_CODE
877 && (prev_insn
.insn_mo
->pinfo
878 & (INSN_LOAD_MEMORY_DELAY
879 | INSN_COPROC_MEMORY_DELAY
))))
882 if ((prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
)
883 || (prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
884 || (prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
))
887 else if ((prev_prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
)
888 || (prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
889 || (prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
))
894 if (insn_label
!= NULL
)
896 assert (S_GET_SEGMENT (insn_label
) == now_seg
);
897 insn_label
->sy_frag
= frag_now
;
898 S_SET_VALUE (insn_label
, frag_now_fix ());
901 mips_no_prev_insn ();
905 /* Return 1 if an expression can be accessed via the GP register. */
916 sym
= ep
->X_add_symbol
;
917 if (sym
== (symbolS
*) NULL
918 || ep
->X_op_symbol
!= (symbolS
*) NULL
)
921 /* Certain symbols can not be referenced off the GP, although it
922 appears as though they can. */
923 symname
= S_GET_NAME (sym
);
924 if (symname
!= (const char *) NULL
925 && (strcmp (symname
, "eprol") == 0
926 || strcmp (symname
, "etext") == 0
927 || strcmp (symname
, "_gp") == 0
928 || strcmp (symname
, "edata") == 0
929 || strcmp (symname
, "_fbss") == 0
930 || strcmp (symname
, "_fdata") == 0
931 || strcmp (symname
, "_ftext") == 0
932 || strcmp (symname
, "end") == 0))
934 if (! S_IS_DEFINED (sym
)
935 && S_GET_VALUE (sym
) != 0
936 && S_GET_VALUE (sym
) <= g_switch_value
)
938 segname
= segment_name (S_GET_SEGMENT (ep
->X_add_symbol
));
939 return (strcmp (segname
, ".sdata") == 0
940 || strcmp (segname
, ".sbss") == 0
941 || strcmp (segname
, ".lit8") == 0
942 || strcmp (segname
, ".lit4") == 0);
943 #else /* ! defined (OBJ_ECOFF) */
944 /* The GP register is only used for ECOFF. */
946 #endif /* ! defined (OBJ_ECOFF) */
949 /* Build an instruction created by a macro expansion. This is passed
950 a pointer to the count of instructions created so far, an
951 expression, the name of the instruction to build, an operand format
952 string, and corresponding arguments. */
956 macro_build (int *counter
,
961 #else /* ! defined (NO_STDARG) */
963 macro_build (counter
, ep
, name
, fmt
, va_alist
)
969 #endif /* ! defined (NO_STDARG) */
971 struct mips_cl_insn insn
;
972 bfd_reloc_code_real_type r
;
976 va_start (args
, fmt
);
982 * If the macro is about to expand into a second instruction,
983 * print a warning if needed. We need to pass ip as a parameter
984 * to generate a better warning message here...
986 if (mips_warn_about_macros
&& *counter
== 1)
987 as_warn ("Macro instruction expanded into multiple instructions");
989 *counter
+= 1; /* bump instruction counter */
991 r
= BFD_RELOC_UNUSED
;
992 insn
.insn_mo
= (struct mips_opcode
*) hash_find (op_hash
, name
);
993 assert (insn
.insn_mo
);
994 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
996 while (strcmp (fmt
, insn
.insn_mo
->args
) != 0)
999 assert (insn
.insn_mo
->name
);
1000 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
1002 assert (insn
.insn_mo
->pinfo
!= INSN_MACRO
);
1003 insn
.insn_opcode
= insn
.insn_mo
->match
;
1019 insn
.insn_opcode
|= va_arg (args
, int) << 16;
1025 insn
.insn_opcode
|= va_arg (args
, int) << 16;
1030 insn
.insn_opcode
|= va_arg (args
, int) << 11;
1035 insn
.insn_opcode
|= va_arg (args
, int) << 11;
1039 insn
.insn_opcode
|= va_arg (args
, int) << 6;
1043 insn
.insn_opcode
|= va_arg (args
, int) << 6;
1047 insn
.insn_opcode
|= va_arg (args
, int) << 6;
1054 insn
.insn_opcode
|= va_arg (args
, int) << 21;
1064 assert (ep
!= NULL
);
1066 * This allows macro() to pass an immediate expression for
1067 * creating short branches without creating a symbol.
1068 * Note that the expression still might come from the assembly
1069 * input, in which case the value is not checked for range nor
1070 * is a relocation entry generated (yuck).
1072 if (ep
->X_op
== O_constant
)
1074 insn
.insn_opcode
|= (ep
->X_add_number
>> 2) & 0xffff;
1078 r
= BFD_RELOC_16_PCREL_S2
;
1087 assert (r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
1089 /* Use GP relative addressing if possible. */
1090 if (r
== BFD_RELOC_LO16
1091 && gp_reference (ep
))
1092 r
= BFD_RELOC_MIPS_GPREL
;
1094 append_insn (&insn
, ep
, r
);
1098 * Generate a "lui" instruction.
1101 macro_build_lui (counter
, ep
, regnum
)
1106 expressionS high_expr
;
1107 struct mips_cl_insn insn
;
1108 bfd_reloc_code_real_type r
;
1109 CONST
char *name
= "lui";
1110 CONST
char *fmt
= "t,u";
1114 if (high_expr
.X_op
== O_constant
)
1116 /* we can compute the instruction now without a relocation entry */
1117 if (high_expr
.X_add_number
& 0x8000)
1118 high_expr
.X_add_number
+= 0x10000;
1119 high_expr
.X_add_number
=
1120 ((unsigned long) high_expr
.X_add_number
>> 16) & 0xffff;
1121 r
= BFD_RELOC_UNUSED
;
1124 r
= BFD_RELOC_HI16_S
;
1127 * If the macro is about to expand into a second instruction,
1128 * print a warning if needed. We need to pass ip as a parameter
1129 * to generate a better warning message here...
1131 if (mips_warn_about_macros
&& *counter
== 1)
1132 as_warn ("Macro instruction expanded into multiple instructions");
1134 *counter
+= 1; /* bump instruction counter */
1136 insn
.insn_mo
= (struct mips_opcode
*) hash_find (op_hash
, name
);
1137 assert (insn
.insn_mo
);
1138 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
1139 assert (strcmp (fmt
, insn
.insn_mo
->args
) == 0);
1141 insn
.insn_opcode
= insn
.insn_mo
->match
| (regnum
<< 16);
1142 if (r
== BFD_RELOC_UNUSED
)
1144 insn
.insn_opcode
|= high_expr
.X_add_number
;
1145 append_insn (&insn
, NULL
, r
);
1148 append_insn (&insn
, &high_expr
, r
);
1152 * Generates code to set the $at register to true (one)
1153 * if reg is less than the immediate expression.
1156 set_at (counter
, reg
)
1161 switch (imm_expr
.X_add_number
& 0xffff8000)
1165 macro_build (counter
, &imm_expr
, "slti", "t,r,j", AT
, reg
);
1169 macro_build (counter
, &imm_expr
, "ori", "t,r,i", AT
, 0);
1173 macro_build_lui (counter
, &imm_expr
, AT
);
1174 if (imm_expr
.X_add_number
& 0xffff)
1175 macro_build (counter
, &imm_expr
, "addiu", "t,r,j", AT
, AT
);
1177 macro_build (counter
, NULL
, "slt", "d,v,t", AT
, reg
, AT
);
1180 /* set_at_unsigned()
1181 * Generates code to set the $at register to true (one)
1182 * if reg is less than the immediate expression.
1183 * Unsigned comparison is perfomed.
1186 set_at_unsigned (counter
, reg
)
1191 switch (imm_expr
.X_add_number
& 0xffff8000)
1195 macro_build (counter
, &imm_expr
, "sltiu", "t,r,j", AT
, reg
);
1199 macro_build (counter
, &imm_expr
, "ori", "t,r,i", AT
, 0);
1203 macro_build_lui (counter
, &imm_expr
, AT
);
1204 if (imm_expr
.X_add_number
& 0xffff)
1205 macro_build (counter
, &imm_expr
, "addiu", "t,r,j", AT
, AT
);
1207 macro_build (counter
, NULL
, "sltu", "d,v,t", AT
, reg
, AT
);
1211 check_absolute_expr (ip
, ex
)
1212 struct mips_cl_insn
*ip
;
1215 if (ex
->X_op
!= O_constant
)
1216 as_warn ("Instruction %s requires absolute expression", ip
->insn_mo
->name
);
1220 * This routine generates the least number of instructions neccessary to load
1221 * an absolute expression value into a register.
1224 load_register (counter
, ip
, reg
, ep
)
1226 struct mips_cl_insn
*ip
;
1230 switch (ep
->X_add_number
& 0xffff8000)
1234 macro_build (counter
, ep
, "addiu", "t,r,j", reg
, 0);
1238 macro_build (counter
, ep
, "ori", "t,r,i", reg
, 0);
1242 macro_build_lui (counter
, ep
, reg
);
1243 if (ep
->X_add_number
& 0xffff)
1244 macro_build (counter
, ep
, "addiu", "t,r,j", reg
, reg
);
1251 * This routine implements the seemingly endless macro or synthesized
1252 * instructions and addressing modes in the mips assembly language. Many
1253 * of these macros are simple and are similar to each other. These could
1254 * probably be handled by some kind of table or grammer aproach instead of
1255 * this verbose method. Others are not simple macros but are more like
1256 * optimizing code generation.
1257 * One interesting optimization is when several store macros appear
1258 * consecutivly that would load AT with the upper half of the same address.
1259 * The ensuing load upper instructions are ommited. This implies some kind
1260 * of global optimization. We currently only optimize within a single macro.
1261 * For many of the load and store macros if the address is specified as a
1262 * constant expression in the first 64k of memory (ie ld $2,0x4000c) we
1263 * first load register 'at' with zero and use it as the base register. The
1264 * mips assembler simply uses register $zero. Just one tiny optimization
1269 struct mips_cl_insn
*ip
;
1271 register int treg
, sreg
, dreg
, breg
;
1284 treg
= (ip
->insn_opcode
>> 16) & 0x1f;
1285 dreg
= (ip
->insn_opcode
>> 11) & 0x1f;
1286 sreg
= breg
= (ip
->insn_opcode
>> 21) & 0x1f;
1287 mask
= ip
->insn_mo
->mask
;
1289 expr1
.X_op
= O_constant
;
1290 expr1
.X_op_symbol
= NULL
;
1291 expr1
.X_add_symbol
= NULL
;
1292 expr1
.X_add_number
= 1;
1299 Note: mips algorithm requires the move in the delay slot.
1300 <main>: bgez $a0,0x4001bc <main+12>
1301 <main+4>: move v0,$a0
1302 <main+8>: sub v0,$zero,$a0
1306 mips_emit_delays ();
1309 expr1
.X_add_number
= 8;
1310 macro_build (&icnt
, &expr1
, "bgez", "s,p", sreg
);
1311 macro_build (&icnt
, NULL
, "move", "d,s", dreg
, sreg
, 0);
1312 macro_build (&icnt
, NULL
, mask
== M_ABS
? "sub" : "subu", "d,v,t",
1334 switch (imm_expr
.X_add_number
& 0xffff8000)
1338 macro_build (&icnt
, &imm_expr
, s
, "t,r,j", treg
, sreg
);
1342 macro_build (&icnt
, &imm_expr
, "ori", "t,r,i", AT
, 0);
1346 macro_build_lui (&icnt
, &imm_expr
, AT
);
1347 if (imm_expr
.X_add_number
& 0xffff)
1348 macro_build (&icnt
, &imm_expr
, "addiu", "t,r,j", AT
, AT
);
1351 macro_build (&icnt
, NULL
, s2
, "d,v,t", treg
, sreg
, AT
);
1358 switch (imm_expr
.X_add_number
& 0xffff8000)
1365 macro_build (&icnt
, &imm_expr
, "andi", "t,r,i", treg
, sreg
);
1368 macro_build (&icnt
, &imm_expr
, "ori", "t,r,i", treg
, sreg
);
1371 macro_build (&icnt
, &imm_expr
, "ori", "t,r,i", treg
, sreg
);
1372 macro_build (&icnt
, &imm_expr
, "nor", "d,v,t", treg
, treg
, 0);
1375 macro_build (&icnt
, &imm_expr
, "xori", "t,r,i", treg
, sreg
);
1382 macro_build (&icnt
, &imm_expr
, "addiu", "t,r,j", AT
, 0);
1386 macro_build_lui (&icnt
, &imm_expr
, AT
);
1387 if (imm_expr
.X_add_number
& 0xffff)
1388 macro_build (&icnt
, &imm_expr
, "addiu", "t,r,j", AT
, AT
);
1393 macro_build (&icnt
, NULL
, "and", "d,v,t", treg
, sreg
, AT
);
1396 macro_build (&icnt
, NULL
, "or", "d,v,t", treg
, sreg
, AT
);
1399 macro_build (&icnt
, NULL
, "nor", "d,v,t", treg
, sreg
, AT
);
1402 macro_build (&icnt
, NULL
, "xor", "d,v,t", treg
, sreg
, AT
);
1423 if (imm_expr
.X_add_number
== 0)
1425 macro_build (&icnt
, &offset_expr
, s
, "s,t,p", sreg
, 0);
1428 load_register (&icnt
, ip
, AT
, &imm_expr
);
1429 macro_build (&icnt
, &offset_expr
, s
, "s,t,p", sreg
, AT
);
1437 macro_build (&icnt
, &offset_expr
,
1438 likely
? "bgezl" : "bgez",
1444 macro_build (&icnt
, &offset_expr
,
1445 likely
? "blezl" : "blez",
1449 macro_build (&icnt
, NULL
, "slt", "d,v,t", AT
, sreg
, treg
);
1450 macro_build (&icnt
, &offset_expr
,
1451 likely
? "beql" : "beq",
1458 /* check for > max integer */
1459 if (imm_expr
.X_add_number
== 0x7fffffff)
1462 /* result is always false */
1465 as_warn ("Branch %s is always false (nop)", ip
->insn_mo
->name
);
1466 macro_build (&icnt
, NULL
, "nop", "", 0);
1470 as_warn ("Branch likely %s is always false", ip
->insn_mo
->name
);
1471 macro_build (&icnt
, &offset_expr
, "bnel", "s,t,p", 0, 0);
1475 imm_expr
.X_add_number
++;
1479 if (mask
== M_BGEL_I
)
1481 if (imm_expr
.X_add_number
== 0)
1483 macro_build (&icnt
, &offset_expr
,
1484 likely
? "bgezl" : "bgez",
1488 if (imm_expr
.X_add_number
== 1)
1490 macro_build (&icnt
, &offset_expr
,
1491 likely
? "bgtzl" : "bgtz",
1495 if (imm_expr
.X_add_number
== 0x80000000)
1498 /* result is always true */
1499 as_warn ("Branch %s is always true", ip
->insn_mo
->name
);
1500 macro_build (&icnt
, &offset_expr
, "b", "p");
1503 set_at (&icnt
, sreg
);
1504 macro_build (&icnt
, &offset_expr
,
1505 likely
? "beql" : "beq",
1516 macro_build (&icnt
, &offset_expr
,
1517 likely
? "beql" : "beq",
1521 macro_build (&icnt
, NULL
, "sltu", "d,v,t", AT
, sreg
, treg
);
1522 macro_build (&icnt
, &offset_expr
,
1523 likely
? "beql" : "beq",
1530 if (sreg
== 0 || imm_expr
.X_add_number
== 0xffffffff)
1532 imm_expr
.X_add_number
++;
1536 if (mask
== M_BGEUL_I
)
1538 if (imm_expr
.X_add_number
== 0)
1540 if (imm_expr
.X_add_number
== 1)
1542 macro_build (&icnt
, &offset_expr
,
1543 likely
? "bnel" : "bne",
1547 set_at_unsigned (&icnt
, sreg
);
1548 macro_build (&icnt
, &offset_expr
,
1549 likely
? "beql" : "beq",
1558 macro_build (&icnt
, &offset_expr
,
1559 likely
? "bgtzl" : "bgtz",
1565 macro_build (&icnt
, &offset_expr
,
1566 likely
? "bltzl" : "bltz",
1570 macro_build (&icnt
, NULL
, "slt", "d,v,t", AT
, treg
, sreg
);
1571 macro_build (&icnt
, &offset_expr
,
1572 likely
? "bnel" : "bne",
1581 macro_build (&icnt
, &offset_expr
,
1582 likely
? "bnel" : "bne",
1588 macro_build (&icnt
, NULL
, "sltu", "d,v,t", AT
, treg
, sreg
);
1589 macro_build (&icnt
, &offset_expr
,
1590 likely
? "bnel" : "bne",
1599 macro_build (&icnt
, &offset_expr
,
1600 likely
? "blezl" : "blez",
1606 macro_build (&icnt
, &offset_expr
,
1607 likely
? "bgezl" : "bgez",
1611 macro_build (&icnt
, NULL
, "slt", "d,v,t", AT
, treg
, sreg
);
1612 macro_build (&icnt
, &offset_expr
,
1613 likely
? "beql" : "beq",
1620 if (imm_expr
.X_add_number
== 0x7fffffff)
1622 imm_expr
.X_add_number
++;
1626 if (mask
== M_BLTL_I
)
1628 if (imm_expr
.X_add_number
== 0)
1630 macro_build (&icnt
, &offset_expr
,
1631 likely
? "bltzl" : "bltz",
1635 if (imm_expr
.X_add_number
== 1)
1637 macro_build (&icnt
, &offset_expr
,
1638 likely
? "blezl" : "blez",
1642 set_at (&icnt
, sreg
);
1643 macro_build (&icnt
, &offset_expr
,
1644 likely
? "bnel" : "bne",
1653 macro_build (&icnt
, &offset_expr
,
1654 likely
? "beql" : "beq",
1660 macro_build (&icnt
, NULL
, "sltu", "d,v,t", AT
, treg
, sreg
);
1661 macro_build (&icnt
, &offset_expr
,
1662 likely
? "beql" : "beq",
1669 if (sreg
== 0 || imm_expr
.X_add_number
== 0xffffffff)
1671 imm_expr
.X_add_number
++;
1675 if (mask
== M_BLTUL_I
)
1677 if (imm_expr
.X_add_number
== 0)
1679 if (imm_expr
.X_add_number
== 1)
1681 macro_build (&icnt
, &offset_expr
,
1682 likely
? "beql" : "beq",
1686 set_at_unsigned (&icnt
, sreg
);
1687 macro_build (&icnt
, &offset_expr
,
1688 likely
? "bnel" : "bne",
1697 macro_build (&icnt
, &offset_expr
,
1698 likely
? "bltzl" : "bltz",
1704 macro_build (&icnt
, &offset_expr
,
1705 likely
? "bgtzl" : "bgtz",
1709 macro_build (&icnt
, NULL
, "slt", "d,v,t", AT
, sreg
, treg
);
1710 macro_build (&icnt
, &offset_expr
,
1711 likely
? "bnel" : "bne",
1722 macro_build (&icnt
, &offset_expr
,
1723 likely
? "bnel" : "bne",
1727 macro_build (&icnt
, NULL
, "sltu", "d,v,t", AT
, sreg
, treg
);
1728 macro_build (&icnt
, &offset_expr
,
1729 likely
? "bnel" : "bne",
1745 as_warn ("Divide by zero.");
1746 macro_build (&icnt
, NULL
, "break", "c", 7);
1750 mips_emit_delays ();
1752 macro_build (&icnt
, NULL
,
1753 dbl
? "ddiv" : "div",
1755 expr1
.X_add_number
= 8;
1756 macro_build (&icnt
, &expr1
, "bne", "s,t,p", treg
, 0);
1757 macro_build (&icnt
, NULL
, "nop", "", 0);
1758 macro_build (&icnt
, NULL
, "break", "c", 7);
1759 expr1
.X_add_number
= -1;
1760 macro_build (&icnt
, &expr1
,
1761 dbl
? "daddiu" : "addiu",
1763 expr1
.X_add_number
= dbl
? 20 : 16;
1764 macro_build (&icnt
, &expr1
, "bne", "s,t,p", treg
, AT
);
1767 expr1
.X_add_number
= 1;
1768 macro_build (&icnt
, &expr1
, "daddiu", "t,r,j", AT
, 0);
1769 macro_build (&icnt
, NULL
, "dsll32", "d,w,<", AT
, AT
, 31);
1773 expr1
.X_add_number
= 0x80000000;
1774 macro_build_lui (&icnt
, &expr1
, AT
);
1776 expr1
.X_add_number
= 8;
1777 macro_build (&icnt
, &expr1
, "bne", "s,t,p", sreg
, AT
);
1778 macro_build (&icnt
, NULL
, "nop", "", 0);
1779 macro_build (&icnt
, NULL
, "break", "c", 6);
1781 macro_build (&icnt
, NULL
, s
, "d", dreg
);
1782 /* with reorder on there will be two implicit nop instructions here. */
1821 if (imm_expr
.X_add_number
== 0)
1823 as_warn ("Divide by zero.");
1824 macro_build (&icnt
, NULL
, "break", "c", 7);
1827 if (imm_expr
.X_add_number
== 1)
1829 if (strcmp (s2
, "mflo") == 0)
1830 macro_build (&icnt
, NULL
, "move", "d,s", dreg
, sreg
);
1832 macro_build (&icnt
, NULL
, "move", "d,s", dreg
, 0);
1835 if (imm_expr
.X_add_number
== -1
1836 && s
[strlen (s
) - 1] != 'u')
1838 if (strcmp (s2
, "mflo") == 0)
1841 macro_build (&icnt
, NULL
, "dneg", "d,w", dreg
, sreg
);
1843 macro_build (&icnt
, NULL
, "neg", "d,w", dreg
, sreg
);
1846 macro_build (&icnt
, NULL
, "move", "d,s", dreg
, 0);
1850 load_register (&icnt
, ip
, AT
, &imm_expr
);
1851 macro_build (&icnt
, NULL
, s
, "s,t", sreg
, AT
);
1852 macro_build (&icnt
, NULL
, s2
, "d", dreg
);
1853 /* two implicit nop's required for mflo or mfhi */
1872 mips_emit_delays ();
1874 macro_build (&icnt
, NULL
, s
, "s,t", sreg
, treg
);
1875 expr1
.X_add_number
= 8;
1876 macro_build (&icnt
, &expr1
, "bne", "s,t,p", treg
, 0);
1877 macro_build (&icnt
, NULL
, "nop", "", 0);
1878 macro_build (&icnt
, NULL
, "break", "c", 7);
1880 macro_build (&icnt
, NULL
, s2
, "d", dreg
);
1881 /* with reorder on there will be two implicit nop instructions here. */
1885 if (offset_expr
.X_op
== O_constant
)
1887 load_register (&icnt
, ip
, treg
, &offset_expr
);
1890 if (gp_reference (&offset_expr
))
1891 macro_build (&icnt
, &offset_expr
, "addiu", "t,r,j", treg
, GP
);
1894 macro_build_lui (&icnt
, &offset_expr
, treg
);
1895 macro_build (&icnt
, &offset_expr
, "addiu", "t,r,j", treg
, treg
);
1900 tempreg
= (breg
== treg
) ? AT
: treg
;
1901 if (offset_expr
.X_op
== O_constant
)
1902 load_register (&icnt
, ip
, tempreg
, &offset_expr
);
1903 else if (gp_reference (&offset_expr
))
1904 macro_build (&icnt
, &offset_expr
, "addiu", "t,r,j", tempreg
, GP
);
1907 macro_build_lui (&icnt
, &offset_expr
, tempreg
);
1908 macro_build (&icnt
, &offset_expr
, "addiu", "t,r,j", tempreg
, tempreg
);
1911 macro_build (&icnt
, NULL
, "addu", "d,v,t", treg
, tempreg
, breg
);
1981 if (breg
== treg
|| coproc
)
2050 if (mask
== M_LWC1_AB
2051 || mask
== M_SWC1_AB
2053 || mask
== M_LDC1_AB
2054 || mask
== M_SDC1_AB
)
2060 if (gp_reference (&offset_expr
))
2064 macro_build (&icnt
, &offset_expr
, s
, fmt
, treg
, GP
);
2067 macro_build (&icnt
, (expressionS
*) NULL
, "addu", "d,v,t",
2072 macro_build_lui (&icnt
, &offset_expr
, tempreg
);
2074 macro_build (&icnt
, NULL
, "addu", "d,v,t", tempreg
, tempreg
, breg
);
2076 macro_build (&icnt
, &offset_expr
, s
, fmt
, treg
, tempreg
);
2083 load_register (&icnt
, ip
, treg
, &imm_expr
);
2088 lw $v0,%lo(foo)($at)
2089 lw $v1,%lo(foo+4)($at)
2094 macro_build_lui (&icnt
, &offset_expr
, AT
);
2096 macro_build (&icnt
, &offset_expr
, "ld", "t,o(b)", treg
, AT
);
2099 macro_build (&icnt
, &offset_expr
, "lw", "t,o(b)", treg
, AT
);
2100 offset_expr
.X_add_number
+= 4;
2101 macro_build (&icnt
, &offset_expr
, "lw", "t,o(b)", treg
+ 1, AT
);
2106 /* Load a floating point number from the .lit8 section. */
2109 macro_build (&icnt
, &offset_expr
, "ldc1", "T,o(b)", treg
, GP
);
2115 /* Even on a big endian machine $fn comes before $fn+1. We have
2116 to adjust when loading from memory. */
2117 assert (mips_isa
< 2);
2118 macro_build (&icnt
, &offset_expr
, "lwc1", "T,o(b)",
2119 byte_order
== LITTLE_ENDIAN
? treg
: treg
+ 1,
2121 offset_expr
.X_add_number
+= 4;
2122 macro_build (&icnt
, &offset_expr
, "lwc1", "T,o(b)",
2123 byte_order
== LITTLE_ENDIAN
? treg
+ 1 : treg
,
2129 * The MIPS assembler seems to check for X_add_number not
2130 * being double aligned and generating:
2133 * addiu at,at,%lo(foo+1)
2136 * But, the resulting address is the same after relocation so why
2137 * generate the extra instruction?
2139 if (gp_reference (&offset_expr
))
2145 macro_build (&icnt
, &offset_expr
, "addu", "d,v,t", AT
, breg
, GP
);
2151 macro_build_lui (&icnt
, &offset_expr
, AT
);
2153 macro_build (&icnt
, NULL
, "addu", "d,v,t", AT
, AT
, breg
);
2157 macro_build (&icnt
, &offset_expr
, "ldc1", "T,o(b)", treg
, tempreg
);
2160 /* Even on a big endian machine $fn comes before $fn+1. We
2161 have to adjust when loading from memory. */
2162 macro_build (&icnt
, &offset_expr
, "lwc1", "T,o(b)",
2163 byte_order
== LITTLE_ENDIAN
? treg
: treg
+ 1,
2165 offset_expr
.X_add_number
+= 4;
2166 macro_build (&icnt
, &offset_expr
, "lwc1", "T,o(b)",
2167 byte_order
== LITTLE_ENDIAN
? treg
+ 1 : treg
,
2180 assert (mips_isa
< 3);
2181 macro_build (&icnt
, &offset_expr
, s
, "t,o(b)", treg
, breg
);
2182 offset_expr
.X_add_number
+= 4;
2183 macro_build (&icnt
, &offset_expr
, s
, "t,o(b)", treg
+ 1, breg
);
2206 if (gp_reference (&offset_expr
))
2214 macro_build (&icnt
, (expressionS
*) NULL
, "addu", "d,v,t",
2219 macro_build_lui (&icnt
, &offset_expr
, tempreg
);
2221 macro_build (&icnt
, NULL
, "addu", "d,v,t", tempreg
, tempreg
, breg
);
2224 macro_build (&icnt
, &offset_expr
, s2
, "t,o(b)", treg
, tempreg
);
2227 macro_build (&icnt
, &offset_expr
, s
, "t,o(b)", treg
, tempreg
);
2228 offset_expr
.X_add_number
+= 4;
2229 macro_build (&icnt
, &offset_expr
, s
, "t,o(b)", treg
+ 1, tempreg
);
2238 macro_build (&icnt
, NULL
,
2239 dbl
? "dmultu" : "multu",
2241 macro_build (&icnt
, NULL
, "mflo", "d", dreg
);
2242 /* two implicit nop's required for mflo */
2248 /* The MIPS assembler some times generates shifts and adds. I'm
2249 not trying to be that fancy. GCC should do this for us
2251 load_register (&icnt
, ip
, AT
, &imm_expr
);
2252 macro_build (&icnt
, NULL
,
2253 dbl
? "dmult" : "mult",
2255 macro_build (&icnt
, NULL
, "mflo", "d", dreg
);
2256 /* two implicit nop's required for mflo */
2262 mips_emit_delays ();
2264 macro_build (&icnt
, NULL
,
2265 dbl
? "dmult" : "mult",
2267 macro_build (&icnt
, NULL
, "mflo", "d", dreg
);
2268 macro_build (&icnt
, NULL
,
2269 dbl
? "dsra32" : "sra",
2270 "d,w,<", dreg
, dreg
, 31);
2271 macro_build (&icnt
, NULL
, "mfhi", "d", AT
);
2272 expr1
.X_add_number
= 8;
2273 macro_build (&icnt
, &expr1
, "beq", "s,t,p", dreg
, AT
);
2274 macro_build (&icnt
, NULL
, "nop", "", 0);
2275 macro_build (&icnt
, NULL
, "break", "c", 6);
2277 macro_build (&icnt
, NULL
, "mflo", "d", dreg
);
2283 mips_emit_delays ();
2285 macro_build (&icnt
, NULL
,
2286 dbl
? "dmultu" : "multu",
2288 macro_build (&icnt
, NULL
, "mfhi", "d", AT
);
2289 macro_build (&icnt
, NULL
, "mflo", "d", dreg
);
2290 expr1
.X_add_number
= 8;
2291 macro_build (&icnt
, &expr1
, "beq", "s,t,p", AT
, 0);
2292 macro_build (&icnt
, NULL
, "nop", "", 0);
2293 macro_build (&icnt
, NULL
, "break", "c", 6);
2298 macro_build (&icnt
, NULL
, "subu", "d,v,t", AT
, 0, treg
);
2299 macro_build (&icnt
, NULL
, "srlv", "d,t,s", AT
, sreg
, AT
);
2300 macro_build (&icnt
, NULL
, "sllv", "d,t,s", dreg
, sreg
, treg
);
2301 macro_build (&icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
2305 macro_build (&icnt
, NULL
, "sll", "d,w,<", AT
, sreg
,
2306 imm_expr
.X_add_number
& 0x1f);
2307 macro_build (&icnt
, NULL
, "srl", "d,w,<", dreg
, sreg
,
2308 (0 - imm_expr
.X_add_number
) & 0x1f);
2309 macro_build (&icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
2313 macro_build (&icnt
, NULL
, "subu", "d,v,t", AT
, 0, treg
);
2314 macro_build (&icnt
, NULL
, "sllv", "d,t,s", AT
, sreg
, AT
);
2315 macro_build (&icnt
, NULL
, "srlv", "d,t,s", dreg
, sreg
, treg
);
2316 macro_build (&icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
2320 macro_build (&icnt
, NULL
, "srl", "d,w,<", AT
, sreg
,
2321 imm_expr
.X_add_number
& 0x1f);
2322 macro_build (&icnt
, NULL
, "sll", "d,w,<", dreg
, sreg
,
2323 (0 - imm_expr
.X_add_number
) & 0x1f);
2324 macro_build (&icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
2328 assert (mips_isa
< 2);
2329 /* Even on a big endian machine $fn comes before $fn+1. We have
2330 to adjust when storing to memory. */
2331 macro_build (&icnt
, &offset_expr
, "swc1", "T,o(b)",
2332 byte_order
== LITTLE_ENDIAN
? treg
: treg
+ 1,
2334 offset_expr
.X_add_number
+= 4;
2335 macro_build (&icnt
, &offset_expr
, "swc1", "T,o(b)",
2336 byte_order
== LITTLE_ENDIAN
? treg
+ 1 : treg
,
2341 if (gp_reference (&offset_expr
))
2347 macro_build (&icnt
, (expressionS
*) NULL
, "addu", "d,v,t",
2354 macro_build_lui (&icnt
, &offset_expr
, AT
);
2356 macro_build (&icnt
, NULL
, "addu", "d,v,t", AT
, AT
, breg
);
2360 macro_build (&icnt
, &offset_expr
, "sdc1", "T,o(b)", treg
, tempreg
);
2363 /* Even on a big endian machine $fn comes before $fn+1. We
2364 have to adjust when storing to memory. */
2365 macro_build (&icnt
, &offset_expr
, "swc1", "T,o(b)",
2366 byte_order
== LITTLE_ENDIAN
? treg
: treg
+ 1,
2368 offset_expr
.X_add_number
+= 4;
2369 macro_build (&icnt
, &offset_expr
, "swc1", "T,o(b)",
2370 byte_order
== LITTLE_ENDIAN
? treg
+ 1 : treg
,
2379 macro_build (&icnt
, &expr1
, "sltiu", "t,r,j", dreg
, treg
);
2381 macro_build (&icnt
, &expr1
, "sltiu", "t,r,j", dreg
, sreg
);
2384 macro_build (&icnt
, NULL
, "xor", "d,v,t", dreg
, sreg
, treg
);
2385 macro_build (&icnt
, &expr1
, "sltiu", "t,r,j", dreg
, dreg
);
2390 if (imm_expr
.X_add_number
== 0)
2392 macro_build (&icnt
, &expr1
, "sltiu", "t,r,j", dreg
, sreg
);
2397 as_warn ("Instruction %s: result is always false",
2399 macro_build (&icnt
, NULL
, "move", "d,s", dreg
, 0);
2402 switch (imm_expr
.X_add_number
& 0xffff8000)
2406 macro_build (&icnt
, &imm_expr
, "xori", "t,r,i", dreg
, sreg
);
2411 if (imm_expr
.X_add_number
!= -32768)
2413 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
2414 macro_build (&icnt
, &imm_expr
, "addiu", "t,r,j", dreg
, sreg
);
2421 macro_build_lui (&icnt
, &imm_expr
, AT
);
2422 if (imm_expr
.X_add_number
& 0xffff)
2423 macro_build (&icnt
, &imm_expr
, "addiu", "t,r,j", AT
, AT
);
2424 macro_build (&icnt
, NULL
, "xor", "d,v,t", dreg
, sreg
, AT
);
2427 macro_build (&icnt
, &expr1
, "sltiu", "t,r,j", dreg
, dreg
);
2432 case M_SGE
: /* sreg >= treg <==> not (sreg < treg) */
2438 macro_build (&icnt
, NULL
, s
, "d,v,t", dreg
, sreg
, treg
);
2439 macro_build (&icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
);
2442 case M_SGE_I
: /* sreg >= I <==> not (sreg < I) */
2444 if (imm_expr
.X_add_number
< 32768 && imm_expr
.X_add_number
> -32769)
2446 macro_build (&icnt
, &expr1
,
2447 mask
== M_SGE_I
? "slti" : "sltiu", "t,r,j", dreg
, sreg
);
2452 load_register (&icnt
, ip
, AT
, &imm_expr
);
2453 macro_build (&icnt
, NULL
,
2454 mask
== M_SGE_I
? "slt" : "sltu", "d,v,t", dreg
, sreg
, AT
);
2457 macro_build (&icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
);
2462 case M_SGT
: /* sreg > treg <==> treg < sreg */
2468 macro_build (&icnt
, NULL
, s
, "d,v,t", dreg
, treg
, sreg
);
2471 case M_SGT_I
: /* sreg > I <==> I < sreg */
2477 load_register (&icnt
, ip
, AT
, &imm_expr
);
2478 macro_build (&icnt
, NULL
, s
, "d,v,t", dreg
, AT
, sreg
);
2481 case M_SLE
: /* sreg <= treg <==> treg >= sreg <==> not (treg < sreg) */
2487 macro_build (&icnt
, NULL
, s
, "d,v,t", dreg
, treg
, sreg
);
2488 macro_build (&icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
);
2491 case M_SLE_I
: /* sreg <= I <==> I >= sreg <==> not (I < sreg) */
2497 load_register (&icnt
, ip
, AT
, &imm_expr
);
2498 macro_build (&icnt
, NULL
, s
, "d,v,t", dreg
, AT
, sreg
);
2499 macro_build (&icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
);
2503 if (imm_expr
.X_add_number
< 32768 && imm_expr
.X_add_number
> -32769)
2505 macro_build (&icnt
, &imm_expr
, "slti", "t,r,j", dreg
, sreg
);
2508 load_register (&icnt
, ip
, AT
, &imm_expr
);
2509 macro_build (&icnt
, NULL
, "slt", "d,v,t", dreg
, sreg
, AT
);
2513 if (imm_expr
.X_add_number
< 32768 && imm_expr
.X_add_number
> -32769)
2515 macro_build (&icnt
, &imm_expr
, "sltiu", "t,r,j", dreg
, sreg
);
2518 load_register (&icnt
, ip
, AT
, &imm_expr
);
2519 macro_build (&icnt
, NULL
, "sltu", "d,v,t", dreg
, sreg
, AT
);
2524 macro_build (&icnt
, NULL
, "sltu", "d,v,t", dreg
, 0, treg
);
2526 macro_build (&icnt
, NULL
, "sltu", "d,v,t", dreg
, 0, sreg
);
2529 macro_build (&icnt
, NULL
, "xor", "d,v,t", dreg
, sreg
, treg
);
2530 macro_build (&icnt
, NULL
, "sltu", "d,v,t", dreg
, 0, dreg
);
2535 if (imm_expr
.X_add_number
== 0)
2537 macro_build (&icnt
, NULL
, "sltu", "d,v,t", dreg
, 0, sreg
);
2542 as_warn ("Instruction %s: result is always true",
2544 macro_build (&icnt
, &expr1
, "addiu", "t,r,j", dreg
, 0);
2547 switch (imm_expr
.X_add_number
& 0xffff8000)
2551 macro_build (&icnt
, &imm_expr
, "xori", "t,r,i", dreg
, sreg
);
2556 if (imm_expr
.X_add_number
!= -32768)
2558 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
2559 macro_build (&icnt
, &imm_expr
, "addiu", "t,r,j", dreg
, sreg
);
2566 macro_build_lui (&icnt
, &imm_expr
, AT
);
2567 if (imm_expr
.X_add_number
& 0xffff)
2568 macro_build (&icnt
, &imm_expr
, "addiu", "t,r,j", AT
, AT
);
2569 macro_build (&icnt
, NULL
, "xor", "d,v,t", dreg
, sreg
, AT
);
2572 macro_build (&icnt
, NULL
, "sltu", "d,v,t", dreg
, 0, dreg
);
2580 if (imm_expr
.X_add_number
< 32768 && imm_expr
.X_add_number
> -32768)
2582 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
2583 macro_build (&icnt
, &imm_expr
,
2584 dbl
? "daddi" : "addi",
2585 "t,r,j", dreg
, sreg
);
2588 load_register (&icnt
, ip
, AT
, &imm_expr
);
2589 macro_build (&icnt
, NULL
,
2590 dbl
? "dsub" : "sub",
2591 "d,v,t", dreg
, sreg
, AT
);
2597 if (imm_expr
.X_add_number
< 32768 && imm_expr
.X_add_number
> -32768)
2599 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
2600 macro_build (&icnt
, &imm_expr
,
2601 dbl
? "daddiu" : "addiu",
2602 "t,r,j", dreg
, sreg
);
2605 load_register (&icnt
, ip
, AT
, &imm_expr
);
2606 macro_build (&icnt
, NULL
,
2607 dbl
? "dsubu" : "subu",
2608 "d,v,t", dreg
, sreg
, AT
);
2629 load_register (&icnt
, ip
, AT
, &imm_expr
);
2630 macro_build (&icnt
, NULL
, s
, "s,t", sreg
, AT
);
2635 assert (mips_isa
< 2);
2636 sreg
= (ip
->insn_opcode
>> 11) & 0x1f; /* floating reg */
2637 dreg
= (ip
->insn_opcode
>> 06) & 0x1f; /* floating reg */
2640 * Is the double cfc1 instruction a bug in the mips assembler;
2641 * or is there a reason for it?
2643 mips_emit_delays ();
2645 macro_build (&icnt
, NULL
, "cfc1", "t,G", treg
, 31);
2646 macro_build (&icnt
, NULL
, "cfc1", "t,G", treg
, 31);
2647 macro_build (&icnt
, NULL
, "nop", "");
2648 expr1
.X_add_number
= 3;
2649 macro_build (&icnt
, &expr1
, "ori", "t,r,i", AT
, treg
);
2650 expr1
.X_add_number
= 2;
2651 macro_build (&icnt
, &expr1
, "xori", "t,r,i", AT
, AT
);
2652 macro_build (&icnt
, NULL
, "ctc1", "t,G", AT
, 31);
2653 macro_build (&icnt
, NULL
, "nop", "");
2654 macro_build (&icnt
, NULL
,
2655 mask
== M_TRUNCWD
? "cvt.w.d" : "cvt.w.s", "D,S", dreg
, sreg
);
2656 macro_build (&icnt
, NULL
, "ctc1", "t,G", treg
, 31);
2657 macro_build (&icnt
, NULL
, "nop", "");
2667 /* avoid load delay */
2668 offset_expr
.X_add_number
+= 1;
2669 macro_build (&icnt
, &offset_expr
, s
, "t,o(b)", treg
, breg
);
2670 offset_expr
.X_add_number
-= 1;
2671 macro_build (&icnt
, &offset_expr
, "lbu", "t,o(b)", AT
, breg
);
2672 macro_build (&icnt
, NULL
, "sll", "d,w,<", treg
, treg
, 8);
2673 macro_build (&icnt
, NULL
, "or", "d,v,t", treg
, treg
, AT
);
2677 /* does this work on a big endian machine? */
2678 offset_expr
.X_add_number
+= 3;
2679 macro_build (&icnt
, &offset_expr
, "lwl", "t,o(b)", treg
, breg
);
2680 offset_expr
.X_add_number
-= 3;
2681 macro_build (&icnt
, &offset_expr
, "lwr", "t,o(b)", treg
, breg
);
2687 if (offset_expr
.X_op
== O_constant
)
2688 load_register (&icnt
, ip
, AT
, &offset_expr
);
2689 else if (gp_reference (&offset_expr
))
2690 macro_build (&icnt
, &offset_expr
, "addiu", "t,r,j", AT
, GP
);
2693 macro_build_lui (&icnt
, &offset_expr
, AT
);
2694 macro_build (&icnt
, &offset_expr
, "addiu", "t,r,j", AT
, AT
);
2696 if (mask
== M_ULW_A
)
2698 expr1
.X_add_number
= 3;
2699 macro_build (&icnt
, &expr1
, "lwl", "t,o(b)", treg
, AT
);
2700 imm_expr
.X_add_number
= 0;
2701 macro_build (&icnt
, &expr1
, "lwr", "t,o(b)", treg
, AT
);
2705 macro_build (&icnt
, &expr1
,
2706 mask
== M_ULH_A
? "lb" : "lbu", "t,o(b)", treg
, AT
);
2707 imm_expr
.X_add_number
= 0;
2708 macro_build (&icnt
, &expr1
, "lbu", "t,o(b)", AT
, AT
);
2709 macro_build (&icnt
, NULL
, "sll", "d,w,<", treg
, treg
, 8);
2710 macro_build (&icnt
, NULL
, "or", "d,v,t", treg
, treg
, AT
);
2715 macro_build (&icnt
, &offset_expr
, "sb", "t,o(b)", treg
, breg
);
2716 macro_build (&icnt
, NULL
, "srl", "d,w,<", AT
, treg
, 8);
2717 offset_expr
.X_add_number
+= 1;
2718 macro_build (&icnt
, &offset_expr
, "sb", "t,o(b)", AT
, breg
);
2722 offset_expr
.X_add_number
+= 3;
2723 macro_build (&icnt
, &offset_expr
, "swl", "t,o(b)", treg
, breg
);
2724 offset_expr
.X_add_number
-= 3;
2725 macro_build (&icnt
, &offset_expr
, "swr", "t,o(b)", treg
, breg
);
2730 if (offset_expr
.X_op
== O_constant
)
2731 load_register (&icnt
, ip
, AT
, &offset_expr
);
2732 else if (gp_reference (&offset_expr
))
2733 macro_build (&icnt
, &offset_expr
, "addiu", "t,r,j", AT
, GP
);
2736 macro_build_lui (&icnt
, &offset_expr
, AT
);
2737 macro_build (&icnt
, &offset_expr
, "addiu", "t,r,j", AT
, AT
);
2739 if (mask
== M_USW_A
)
2741 expr1
.X_add_number
= 3;
2742 macro_build (&icnt
, &expr1
, "swl", "t,o(b)", treg
, AT
);
2743 expr1
.X_add_number
= 0;
2744 macro_build (&icnt
, &expr1
, "swr", "t,o(b)", treg
, AT
);
2748 expr1
.X_add_number
= 0;
2749 macro_build (&icnt
, &expr1
, "sb", "t,o(b)", treg
, AT
);
2750 macro_build (&icnt
, NULL
, "srl", "d,w,<", treg
, treg
, 8);
2751 expr1
.X_add_number
= 1;
2752 macro_build (&icnt
, &expr1
, "sb", "t,o(b)", treg
, AT
);
2753 expr1
.X_add_number
= 0;
2754 macro_build (&icnt
, &expr1
, "lbu", "t,o(b)", AT
, AT
);
2755 macro_build (&icnt
, NULL
, "sll", "d,w,<", treg
, treg
, 8);
2756 macro_build (&icnt
, NULL
, "or", "d,v,t", treg
, treg
, AT
);
2761 as_bad ("Macro %s not implemented yet", ip
->insn_mo
->name
);
2765 as_warn ("Macro used $at after \".set noat\"");
2770 This routine assembles an instruction into its binary format. As a side
2771 effect it sets one of the global variables imm_reloc or offset_reloc to the
2772 type of relocation to do if one of the operands is an address expression.
2777 struct mips_cl_insn
*ip
;
2782 struct mips_opcode
*insn
;
2785 unsigned int lastregno
= 0;
2790 for (s
= str
; islower (*s
) || (*s
>= '0' && *s
<= '3') || *s
== '.'; ++s
)
2802 as_warn ("Unknown opcode: `%s'", str
);
2805 if ((insn
= (struct mips_opcode
*) hash_find (op_hash
, str
)) == NULL
)
2807 as_warn ("`%s' not in hash table.", str
);
2808 insn_error
= "ERROR: Unrecognized opcode";
2816 assert (strcmp (insn
->name
, str
) == 0);
2818 if (insn
->pinfo
== INSN_MACRO
)
2819 insn_isa
= insn
->match
;
2820 else if (insn
->pinfo
& INSN_ISA2
)
2822 else if (insn
->pinfo
& INSN_ISA3
)
2827 if (insn_isa
> mips_isa
)
2829 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
]
2830 && strcmp (insn
->name
, insn
[1].name
) == 0)
2835 insn_error
= "ERROR: instruction not supported on this processor";
2840 ip
->insn_opcode
= insn
->match
;
2841 for (args
= insn
->args
;; ++args
)
2847 case '\0': /* end of args */
2860 ip
->insn_opcode
|= lastregno
<< 21;
2865 ip
->insn_opcode
|= lastregno
<< 16;
2869 ip
->insn_opcode
|= lastregno
<< 11;
2875 /* handle optional base register.
2876 Either the base register is omitted or
2877 we must have a left paren. */
2878 /* this is dependent on the next operand specifier
2879 is a 'b' for base register */
2880 assert (args
[1] == 'b');
2884 case ')': /* these must match exactly */
2889 case '<': /* must be at least one digit */
2891 * According to the manual, if the shift amount is greater
2892 * than 31 or less than 0 the the shift amount should be
2893 * mod 32. In reality the mips assembler issues an error.
2894 * We issue a warning and do the mod.
2896 my_getExpression (&imm_expr
, s
);
2897 check_absolute_expr (ip
, &imm_expr
);
2898 if ((unsigned long) imm_expr
.X_add_number
> 31)
2900 as_warn ("Improper shift amount (%d)",
2901 imm_expr
.X_add_number
);
2902 imm_expr
.X_add_number
= imm_expr
.X_add_number
% 32;
2904 ip
->insn_opcode
|= imm_expr
.X_add_number
<< 6;
2905 imm_expr
.X_op
= O_absent
;
2909 case 'c': /* break code */
2910 my_getExpression (&imm_expr
, s
);
2911 check_absolute_expr (ip
, &imm_expr
);
2912 if ((unsigned) imm_expr
.X_add_number
> 1023)
2913 as_warn ("Illegal break code (%d)", imm_expr
.X_add_number
);
2914 ip
->insn_opcode
|= imm_expr
.X_add_number
<< 16;
2915 imm_expr
.X_op
= O_absent
;
2919 case 'B': /* syscall code */
2920 my_getExpression (&imm_expr
, s
);
2921 check_absolute_expr (ip
, &imm_expr
);
2922 if ((unsigned) imm_expr
.X_add_number
> 0xfffff)
2923 as_warn ("Illegal syscall code (%d)", imm_expr
.X_add_number
);
2924 ip
->insn_opcode
|= imm_expr
.X_add_number
<< 6;
2925 imm_expr
.X_op
= O_absent
;
2929 case 'C': /* Coprocessor code */
2930 my_getExpression (&imm_expr
, s
);
2931 check_absolute_expr (ip
, &imm_expr
);
2932 if ((unsigned long) imm_expr
.X_add_number
>= (1<<25))
2934 as_warn ("Coproccesor code > 25 bits (%d)",
2935 imm_expr
.X_add_number
);
2936 imm_expr
.X_add_number
&= ((1<<25) - 1);
2938 ip
->insn_opcode
|= imm_expr
.X_add_number
;
2939 imm_expr
.X_op
= O_absent
;
2943 case 'b': /* base register */
2944 case 'd': /* destination register */
2945 case 's': /* source register */
2946 case 't': /* target register */
2947 case 'r': /* both target and source */
2948 case 'v': /* both dest and source */
2949 case 'w': /* both dest and target */
2950 case 'E': /* coprocessor target register */
2951 case 'G': /* coprocessor destination register */
2952 case 'x': /* ignore register name */
2966 while (isdigit (*s
));
2968 as_bad ("Invalid register number (%d)", regno
);
2970 else if (*args
!= 'E' && *args
!= 'G')
2972 if (s
[1] == 'f' && s
[2] == 'p')
2977 else if (s
[1] == 's' && s
[2] == 'p')
2982 else if (s
[1] == 'g' && s
[2] == 'p')
2987 else if (s
[1] == 'a' && s
[2] == 't')
2994 if (regno
== AT
&& ! mips_noat
)
2995 as_warn ("Used $at without \".set noat\"");
3002 if (c
== 'r' || c
== 'v' || c
== 'w')
3015 ip
->insn_opcode
|= regno
<< 21;
3019 ip
->insn_opcode
|= regno
<< 11;
3024 ip
->insn_opcode
|= regno
<< 16;
3027 /* This case exists because on the r3000 trunc
3028 expands into a macro which requires a gp
3029 register. On the r6000 or r4000 it is
3030 assembled into a single instruction which
3031 ignores the register. Thus the insn version
3032 is MIPS_ISA2 and uses 'x', and the macro
3033 version is MIPS_ISA1 and uses 't'. */
3044 ip
->insn_opcode
|= lastregno
<< 21;
3047 ip
->insn_opcode
|= lastregno
<< 16;
3052 case 'D': /* floating point destination register */
3053 case 'S': /* floating point source register */
3054 case 'T': /* floating point target register */
3058 if (s
[0] == '$' && s
[1] == 'f' && isdigit (s
[2]))
3068 while (isdigit (*s
));
3071 as_bad ("Invalid float register number (%d)", regno
);
3074 !(strcmp (str
, "mtc1") == 0 ||
3075 strcmp (str
, "mfc1") == 0 ||
3076 strcmp (str
, "lwc1") == 0 ||
3077 strcmp (str
, "swc1") == 0))
3078 as_warn ("Float register should be even, was %d",
3086 if (c
== 'V' || c
== 'W')
3096 ip
->insn_opcode
|= regno
<< 6;
3100 ip
->insn_opcode
|= regno
<< 11;
3104 ip
->insn_opcode
|= regno
<< 16;
3112 ip
->insn_opcode
|= lastregno
<< 11;
3115 ip
->insn_opcode
|= lastregno
<< 16;
3121 my_getExpression (&imm_expr
, s
);
3122 check_absolute_expr (ip
, &imm_expr
);
3127 my_getExpression (&offset_expr
, s
);
3128 imm_reloc
= BFD_RELOC_32
;
3140 unsigned char temp
[8];
3146 /* These only appear as the last operand in an
3147 instruction, and every instruction that accepts
3148 them in any variant accepts them in all variants.
3149 This means we don't have to worry about backing out
3150 any changes if the instruction does not match.
3152 The difference between them is the size of the
3153 floating point constant and where it goes. For 'F'
3154 and 'L' the constant is 64 bits; for 'f' and 'l' it
3155 is 32 bits. Where the constant is placed is based
3156 on how the MIPS assembler does things:
3159 f -- immediate value
3163 f64
= *args
== 'F' || *args
== 'L';
3165 save_in
= input_line_pointer
;
3166 input_line_pointer
= s
;
3167 err
= md_atof (f64
? 'd' : 'f', (char *) temp
, &length
);
3168 s
= input_line_pointer
;
3169 input_line_pointer
= save_in
;
3170 if (err
!= NULL
&& *err
!= '\0')
3172 as_bad ("Bad floating point constant: %s", err
);
3173 memset (temp
, '\0', sizeof temp
);
3174 length
= f64
? 8 : 4;
3177 assert (length
== (f64
? 8 : 4));
3181 imm_expr
.X_op
= O_constant
;
3182 if (byte_order
== LITTLE_ENDIAN
)
3183 imm_expr
.X_add_number
=
3184 (((((((int) temp
[3] << 8)
3189 imm_expr
.X_add_number
=
3190 (((((((int) temp
[0] << 8)
3197 /* Switch to the right section. */
3199 subseg
= now_subseg
;
3203 subseg_new (".rdata", (subsegT
) 0);
3206 subseg_new (".lit8", (subsegT
) 0);
3209 subseg_new (".lit4", (subsegT
) 0);
3213 as_bad ("Can't use floating point insn in this section");
3215 /* Set the argument to the current address in the
3217 offset_expr
.X_op
= O_symbol
;
3218 offset_expr
.X_add_symbol
=
3219 symbol_new ("L0\001", now_seg
,
3220 (valueT
) frag_now_fix (), frag_now
);
3221 offset_expr
.X_add_number
= 0;
3223 /* Put the floating point number into the section. */
3224 p
= frag_more (length
);
3225 memcpy (p
, temp
, length
);
3227 /* Switch back to the original section. */
3228 subseg_set (seg
, subseg
);
3233 case 'i': /* 16 bit unsigned immediate */
3234 case 'j': /* 16 bit signed immediate */
3235 imm_reloc
= BFD_RELOC_LO16
;
3236 c
= my_getSmallExpression (&imm_expr
, s
);
3241 if (imm_expr
.X_op
== O_constant
)
3242 imm_expr
.X_add_number
=
3243 (imm_expr
.X_add_number
>> 16) & 0xffff;
3245 imm_reloc
= BFD_RELOC_HI16_S
;
3247 imm_reloc
= BFD_RELOC_HI16
;
3251 check_absolute_expr (ip
, &imm_expr
);
3254 if ((unsigned long) imm_expr
.X_add_number
> 65535)
3256 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
3257 !strcmp (insn
->name
, insn
[1].name
))
3259 as_bad ("16 bit expression not in range 0..65535");
3264 if (imm_expr
.X_add_number
< -32768 ||
3265 imm_expr
.X_add_number
> 32767)
3267 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
3268 !strcmp (insn
->name
, insn
[1].name
))
3270 as_bad ("16 bit expression not in range -32768..32767");
3276 case 'o': /* 16 bit offset */
3277 c
= my_getSmallExpression (&offset_expr
, s
);
3279 * If this value won't fit into a 16 bit offset, then
3280 * go find a macro that will generate the 32 bit offset
3283 if ((offset_expr
.X_add_symbol
3284 && offset_expr
.X_op
!= O_constant
)
3285 || offset_expr
.X_op_symbol
3286 || offset_expr
.X_add_number
> 32767
3287 || offset_expr
.X_add_number
< -32768)
3290 offset_reloc
= BFD_RELOC_LO16
;
3291 if (c
== 'h' || c
== 'H')
3292 offset_expr
.X_add_number
=
3293 (offset_expr
.X_add_number
>> 16) & 0xffff;
3297 case 'p': /* pc relative offset */
3298 offset_reloc
= BFD_RELOC_16_PCREL_S2
;
3299 my_getExpression (&offset_expr
, s
);
3303 case 'u': /* upper 16 bits */
3304 c
= my_getSmallExpression (&imm_expr
, s
);
3305 if ((unsigned long) imm_expr
.X_add_number
> 65535)
3306 as_bad ("lui expression not in range 0..65535");
3307 imm_reloc
= BFD_RELOC_LO16
;
3312 if (imm_expr
.X_op
== O_constant
)
3313 imm_expr
.X_add_number
=
3314 (imm_expr
.X_add_number
>> 16) & 0xffff;
3316 imm_reloc
= BFD_RELOC_HI16_S
;
3318 imm_reloc
= BFD_RELOC_HI16
;
3324 case 'a': /* 26 bit address */
3325 my_getExpression (&offset_expr
, s
);
3327 offset_reloc
= BFD_RELOC_MIPS_JMP
;
3331 fprintf (stderr
, "bad char = '%c'\n", *args
);
3336 /* Args don't match. */
3337 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
3338 !strcmp (insn
->name
, insn
[1].name
))
3344 insn_error
= "ERROR: Illegal operands";
3353 my_getSmallExpression (ep
, str
)
3364 ((str
[1] == 'h' && str
[2] == 'i')
3365 || (str
[1] == 'H' && str
[2] == 'I')
3366 || (str
[1] == 'l' && str
[2] == 'o'))
3378 * A small expression may be followed by a base register.
3379 * Scan to the end of this operand, and then back over a possible
3380 * base register. Then scan the small expression up to that
3381 * point. (Based on code in sparc.c...)
3383 for (sp
= str
; *sp
&& *sp
!= ','; sp
++)
3385 if (sp
- 4 >= str
&& sp
[-1] == RP
)
3387 if (isdigit (sp
[-2]))
3389 for (sp
-= 3; sp
>= str
&& isdigit (*sp
); sp
--)
3391 if (*sp
== '$' && sp
> str
&& sp
[-1] == LP
)
3397 else if (sp
- 5 >= str
3400 && ((sp
[-3] == 'f' && sp
[-2] == 'p')
3401 || (sp
[-3] == 's' && sp
[-2] == 'p')
3402 || (sp
[-3] == 'g' && sp
[-2] == 'p')
3403 || (sp
[-3] == 'a' && sp
[-2] == 't')))
3409 /* no expression means zero offset */
3412 /* %xx(reg) is an error */
3413 ep
->X_op
= O_absent
;
3418 ep
->X_op
= O_absent
;
3421 ep
->X_add_symbol
= NULL
;
3422 ep
->X_op_symbol
= NULL
;
3423 ep
->X_add_number
= 0;
3428 my_getExpression (ep
, str
);
3435 my_getExpression (ep
, str
);
3436 return c
; /* => %hi or %lo encountered */
3440 my_getExpression (ep
, str
)
3446 save_in
= input_line_pointer
;
3447 input_line_pointer
= str
;
3449 expr_end
= input_line_pointer
;
3450 input_line_pointer
= save_in
;
3453 /* Turn a string in input_line_pointer into a floating point constant
3454 of type type, and store the appropriate bytes in *litP. The number
3455 of LITTLENUMS emitted is stored in *sizeP . An error message is
3456 returned, or NULL on OK. */
3459 md_atof (type
, litP
, sizeP
)
3465 LITTLENUM_TYPE words
[4];
3481 return "bad call to md_atof";
3484 t
= atof_ieee (input_line_pointer
, type
, words
);
3486 input_line_pointer
= t
;
3490 if (byte_order
== LITTLE_ENDIAN
)
3492 for (i
= prec
- 1; i
>= 0; i
--)
3494 md_number_to_chars (litP
, (valueT
) words
[i
], 2);
3500 for (i
= 0; i
< prec
; i
++)
3502 md_number_to_chars (litP
, (valueT
) words
[i
], 2);
3511 md_number_to_chars (buf
, val
, n
)
3563 md_parse_option (argP
, cntP
, vecP
)
3568 /* Accept -nocpp but ignore it. */
3569 if (strcmp (*argP
, "nocpp") == 0)
3575 if (strcmp (*argP
, "EL") == 0
3576 || strcmp (*argP
, "EB") == 0)
3578 /* FIXME: This breaks -L -EL. */
3586 if ((*argP
)[1] == '0')
3595 if ((*argP
)[1] == '\0' || (*argP
)[1] == '2')
3600 if (strncmp (*argP
, "mips", 4) == 0)
3602 mips_isa
= atol (*argP
+ 4);
3605 else if (mips_isa
< 1 || mips_isa
> 3)
3607 as_bad ("-mips%d not supported", mips_isa
);
3614 if (strncmp (*argP
, "mcpu=", 5) == 0)
3618 /* Identify the processor type */
3620 if (strcmp (p
, "default") == 0
3621 || strcmp (p
, "DEFAULT") == 0)
3625 if (*p
== 'r' || *p
== 'R')
3632 if (strcmp (p
, "2000") == 0
3633 || strcmp (p
, "2k") == 0
3634 || strcmp (p
, "2K") == 0)
3639 if (strcmp (p
, "3000") == 0
3640 || strcmp (p
, "3k") == 0
3641 || strcmp (p
, "3K") == 0)
3646 if (strcmp (p
, "4000") == 0
3647 || strcmp (p
, "4k") == 0
3648 || strcmp (p
, "4K") == 0)
3653 if (strcmp (p
, "6000") == 0
3654 || strcmp (p
, "6k") == 0
3655 || strcmp (p
, "6K") == 0)
3662 as_bad ("bad value (%s) for -mcpu= switch", *argP
+ 5);
3675 if ((*argP
)[1] != '\0')
3676 g_switch_value
= atoi (*argP
+ 1);
3679 **vecP
= (char *) NULL
;
3682 g_switch_value
= atoi (**vecP
);
3685 as_warn ("Number expected after -G");
3691 return 1; /* pretend you parsed the character */
3695 md_pcrel_from (fixP
)
3698 /* return the address of the delay slot */
3699 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
3703 md_apply_fix (fixP
, valueP
)
3710 assert (fixP
->fx_size
== 4);
3713 fixP
->fx_addnumber
= value
; /* Remember value for tc_gen_reloc */
3715 switch (fixP
->fx_r_type
)
3718 case BFD_RELOC_MIPS_JMP
:
3719 case BFD_RELOC_HI16
:
3720 case BFD_RELOC_HI16_S
:
3721 case BFD_RELOC_LO16
:
3722 case BFD_RELOC_MIPS_GPREL
:
3723 /* Nothing needed to do. The value comes from the reloc entry */
3726 case BFD_RELOC_16_PCREL_S2
:
3728 * We need to save the bits in the instruction since fixup_segment()
3729 * might be deleting the relocation entry (i.e., a branch within
3730 * the current segment).
3733 as_warn ("Branch to odd address (%x)", value
);
3735 if ((value
& ~0xFFFF) && (value
& ~0xFFFF) != (-1 & ~0xFFFF))
3736 as_bad ("Relocation overflow");
3738 /* update old instruction data */
3739 buf
= (unsigned char *) (fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
);
3743 insn
= (buf
[3] << 24) | (buf
[2] << 16) | (buf
[1] << 8) | buf
[0];
3747 insn
= (buf
[0] << 24) | (buf
[1] << 16) | (buf
[2] << 8) | buf
[3];
3754 insn
|= value
& 0xFFFF;
3755 md_number_to_chars ((char *) buf
, insn
, 4);
3769 const struct mips_opcode
*p
;
3770 int treg
, sreg
, dreg
, shamt
;
3775 for (i
= 0; i
< NUMOPCODES
; ++i
)
3777 p
= &mips_opcodes
[i
];
3778 if (((oc
& p
->mask
) == p
->match
) && (p
->pinfo
!= INSN_MACRO
))
3780 printf ("%08lx %s\t", oc
, p
->name
);
3781 treg
= (oc
>> 16) & 0x1f;
3782 sreg
= (oc
>> 21) & 0x1f;
3783 dreg
= (oc
>> 11) & 0x1f;
3784 shamt
= (oc
>> 6) & 0x1f;
3786 for (args
= p
->args
;; ++args
)
3797 printf ("%c", *args
);
3801 assert (treg
== sreg
);
3802 printf ("$%d,$%d", treg
, sreg
);
3807 printf ("$%d", dreg
);
3812 printf ("$%d", treg
);
3817 printf ("$%d", sreg
);
3821 printf ("0x%08lx", oc
& 0x1ffffff);
3832 printf ("$%d", shamt
);
3843 printf ("%08lx UNDEFINED\n", oc
);
3854 name
= input_line_pointer
;
3855 c
= get_symbol_end ();
3856 p
= (symbolS
*) symbol_find_or_make (name
);
3857 *input_line_pointer
= c
;
3861 /* Align the current frag to a given power of two. The MIPS assembler
3862 also automatically adjusts any preceding label. */
3865 mips_align (to
, fill
)
3869 mips_emit_delays ();
3870 frag_align (to
, fill
);
3871 record_alignment (now_seg
, to
);
3872 if (insn_label
!= NULL
)
3874 assert (S_GET_SEGMENT (insn_label
) == now_seg
);
3875 insn_label
->sy_frag
= frag_now
;
3876 S_SET_VALUE (insn_label
, frag_now_fix ());
3880 /* Align to a given power of two. .align 0 turns off the automatic
3881 alignment used by the data creating pseudo-ops. */
3888 register long temp_fill
;
3889 long max_alignment
= 15;
3893 o Note that the assembler pulls down any immediately preceeding label
3894 to the aligned address.
3895 o It's not documented but auto alignment is reinstated by
3896 a .align pseudo instruction.
3897 o Note also that after auto alignment is turned off the mips assembler
3898 issues an error on attempt to assemble an improperly aligned data item.
3903 temp
= get_absolute_expression ();
3904 if (temp
> max_alignment
)
3905 as_bad ("Alignment too large: %d. assumed.", temp
= max_alignment
);
3908 as_warn ("Alignment negative: 0 assumed.");
3911 if (*input_line_pointer
== ',')
3913 input_line_pointer
++;
3914 temp_fill
= get_absolute_expression ();
3921 mips_align (temp
, (int) temp_fill
);
3928 demand_empty_rest_of_line ();
3931 /* Handle .ascii and .asciiz. This just calls stringer and forgets
3932 that there was a previous instruction. */
3935 s_stringer (append_zero
)
3938 mips_emit_delays ();
3939 stringer (append_zero
);
3948 mips_emit_delays ();
3957 subseg_new (".rdata", (subsegT
) get_absolute_expression ());
3958 demand_empty_rest_of_line ();
3967 #ifdef BFD_ASSEMBLER
3968 subseg_set (bss_section
, (subsegT
) get_absolute_expression ());
3970 subseg_new (bss_section
, (subsegT
) get_absolute_expression ());
3972 demand_empty_rest_of_line ();
3976 subseg_new (".sdata", (subsegT
) get_absolute_expression ());
3977 demand_empty_rest_of_line ();
3980 as_bad ("Global pointers not supported; recompile -G 0");
3981 demand_empty_rest_of_line ();
3992 mips_emit_delays ();
3993 if (log_size
> 0 && auto_align
)
3994 mips_align (log_size
, 0);
3995 cons (1 << log_size
);
4002 as_fatal ("Encountered `.err', aborting assembly");
4012 symbolP
= get_symbol ();
4013 if (*input_line_pointer
== ',')
4014 input_line_pointer
++;
4015 size
= get_absolute_expression ();
4016 S_SET_VALUE (symbolP
, size
);
4017 S_SET_EXTERNAL (symbolP
);
4020 /* ECOFF needs to distinguish a .comm symbol from a .extern symbol,
4021 so we use an additional ECOFF specific field. */
4022 symbolP
->ecoff_undefined
= 1;
4030 mips_emit_delays ();
4045 if (strcmp (input_line_pointer
, "O1") != 0
4046 && strcmp (input_line_pointer
, "O2") != 0)
4047 as_warn ("Unrecognized option");
4048 demand_empty_rest_of_line ();
4055 char *name
= input_line_pointer
, ch
;
4057 while (!is_end_of_line
[(unsigned char) *input_line_pointer
])
4058 input_line_pointer
++;
4059 ch
= *input_line_pointer
;
4060 *input_line_pointer
= '\0';
4062 if (strcmp (name
, "reorder") == 0)
4066 prev_insn_unreordered
= 1;
4067 prev_prev_insn_unreordered
= 1;
4071 else if (strcmp (name
, "noreorder") == 0)
4073 mips_emit_delays ();
4076 else if (strcmp (name
, "at") == 0)
4080 else if (strcmp (name
, "noat") == 0)
4084 else if (strcmp (name
, "macro") == 0)
4086 mips_warn_about_macros
= 0;
4088 else if (strcmp (name
, "nomacro") == 0)
4090 if (mips_noreorder
== 0)
4091 as_bad ("`noreorder' must be set before `nomacro'");
4092 mips_warn_about_macros
= 1;
4094 else if (strcmp (name
, "move") == 0 || strcmp (name
, "novolatile") == 0)
4098 else if (strcmp (name
, "nomove") == 0 || strcmp (name
, "volatile") == 0)
4102 else if (strcmp (name
, "bopt") == 0)
4106 else if (strcmp (name
, "nobopt") == 0)
4112 as_warn ("Tried to set unrecognized symbol: %s\n", name
);
4114 *input_line_pointer
= ch
;
4115 demand_empty_rest_of_line ();
4118 /* The same as the usual .space directive, except that we have to
4119 forget about any previous instruction. */
4122 s_mips_space (param
)
4125 mips_emit_delays ();
4135 if (*input_line_pointer
++ != '$')
4137 as_warn ("expected `$'");
4140 if (isdigit ((unsigned char) *input_line_pointer
))
4142 reg
= get_absolute_expression ();
4143 if (reg
< 0 || reg
>= 32)
4145 as_warn ("Bad register number");
4151 if (strncmp (input_line_pointer
, "fp", 2) == 0)
4153 else if (strncmp (input_line_pointer
, "sp", 2) == 0)
4155 else if (strncmp (input_line_pointer
, "gp", 2) == 0)
4157 else if (strncmp (input_line_pointer
, "at", 2) == 0)
4161 as_warn ("Unrecognized register name");
4164 input_line_pointer
+= 2;
4170 * Translate internal representation of relocation info to BFD target format.
4173 tc_gen_reloc (section
, fixp
)
4179 reloc
= (arelent
*) xmalloc (sizeof (arelent
));
4180 assert (reloc
!= 0);
4182 reloc
->sym_ptr_ptr
= &fixp
->fx_addsy
->bsym
;
4183 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
4184 if (fixp
->fx_pcrel
== 0)
4185 reloc
->addend
= fixp
->fx_addnumber
;
4190 reloc
->addend
= -reloc
->address
;
4192 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, fixp
->fx_r_type
);
4193 assert (reloc
->howto
!= 0);
4198 /* should never be called */
4200 md_section_align (seg
, addr
)
4204 int align
= bfd_get_section_alignment (stdoutput
, seg
);
4206 return ((addr
+ (1 << align
) - 1) & (-1 << align
));
4210 md_estimate_size_before_relax (fragP
, segtype
)
4214 as_fatal ("md_estimate_size_before_relax");
4216 } /* md_estimate_size_before_relax() */
4218 /* This function is called whenever a label is defined. It is used
4219 when handling branch delays; if a branch has a label, we assume we
4223 mips_define_label (sym
)
4231 /* These functions should really be defined by the object file format,
4232 since they are related to debugging information. However, this
4233 code has to work for the a.out format, which does not define them,
4234 so we provide simple versions here. These don't actually generate
4235 any debugging information, but they do simple checking and someday
4236 somebody may make them useful. */
4240 struct loc
*loc_next
;
4241 unsigned long loc_fileno
;
4242 unsigned long loc_lineno
;
4243 unsigned long loc_offset
;
4244 unsigned short loc_delta
;
4245 unsigned short loc_count
;
4254 struct proc
*proc_next
;
4255 struct symbol
*proc_isym
;
4256 struct symbol
*proc_end
;
4257 unsigned long proc_reg_mask
;
4258 unsigned long proc_reg_offset
;
4259 unsigned long proc_fpreg_mask
;
4260 unsigned long proc_fpreg_offset
;
4261 unsigned long proc_frameoffset
;
4262 unsigned long proc_framereg
;
4263 unsigned long proc_pcreg
;
4265 struct file
*proc_file
;
4272 struct file
*file_next
;
4273 unsigned long file_fileno
;
4274 struct symbol
*file_symbol
;
4275 struct symbol
*file_end
;
4276 struct proc
*file_proc
;
4281 static struct obstack proc_frags
;
4282 static procS
*proc_lastP
;
4283 static procS
*proc_rootP
;
4284 static int numprocs
;
4289 obstack_begin (&proc_frags
, 0x2000);
4295 /* check for premature end, nesting errors, etc */
4296 if (proc_lastP
&& proc_lastP
->proc_end
== NULL
)
4297 as_warn ("missing `.end' at end of assembly");
4300 extern char hex_value
[];
4308 if (*input_line_pointer
== '-')
4310 ++input_line_pointer
;
4313 if (!isdigit (*input_line_pointer
))
4314 as_bad ("Expected simple number.");
4315 if (input_line_pointer
[0] == '0')
4317 if (input_line_pointer
[1] == 'x')
4319 input_line_pointer
+= 2;
4320 while (isxdigit (*input_line_pointer
))
4323 val
|= hex_value
[(int) *input_line_pointer
++];
4325 return negative
? -val
: val
;
4329 ++input_line_pointer
;
4330 while (isdigit (*input_line_pointer
))
4333 val
|= *input_line_pointer
++ - '0';
4335 return negative
? -val
: val
;
4338 if (!isdigit (*input_line_pointer
))
4340 printf (" *input_line_pointer == '%c' 0x%02x\n",
4341 *input_line_pointer
, *input_line_pointer
);
4342 as_warn ("Invalid number");
4345 while (isdigit (*input_line_pointer
))
4348 val
+= *input_line_pointer
++ - '0';
4350 return negative
? -val
: val
;
4353 /* The .file directive; just like the usual .file directive, but there
4354 is an initial number which is the ECOFF file index. */
4362 line
= get_number ();
4367 /* The .end directive. */
4375 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
4378 demand_empty_rest_of_line ();
4382 if (now_seg
!= text_section
)
4383 as_warn (".end not in text section");
4386 as_warn (".end and no .ent seen yet.");
4392 assert (S_GET_NAME (p
));
4393 if (strcmp (S_GET_NAME (p
), S_GET_NAME (proc_lastP
->proc_isym
)))
4394 as_warn (".end symbol does not match .ent symbol.");
4397 proc_lastP
->proc_end
= (symbolS
*) 1;
4400 /* The .aent and .ent directives. */
4410 symbolP
= get_symbol ();
4411 if (*input_line_pointer
== ',')
4412 input_line_pointer
++;
4413 if (isdigit (*input_line_pointer
) || *input_line_pointer
== '-')
4414 number
= get_number ();
4415 if (now_seg
!= text_section
)
4416 as_warn (".ent or .aent not in text section.");
4418 if (!aent
&& proc_lastP
&& proc_lastP
->proc_end
== NULL
)
4419 as_warn ("missing `.end'");
4423 procP
= (procS
*) obstack_alloc (&proc_frags
, sizeof (*procP
));
4424 procP
->proc_isym
= symbolP
;
4425 procP
->proc_reg_mask
= 0;
4426 procP
->proc_reg_offset
= 0;
4427 procP
->proc_fpreg_mask
= 0;
4428 procP
->proc_fpreg_offset
= 0;
4429 procP
->proc_frameoffset
= 0;
4430 procP
->proc_framereg
= 0;
4431 procP
->proc_pcreg
= 0;
4432 procP
->proc_end
= NULL
;
4433 procP
->proc_next
= NULL
;
4435 proc_lastP
->proc_next
= procP
;
4441 demand_empty_rest_of_line ();
4444 /* The .frame directive. */
4457 frame_reg
= tc_get_register ();
4458 if (*input_line_pointer
== ',')
4459 input_line_pointer
++;
4460 frame_off
= get_absolute_expression ();
4461 if (*input_line_pointer
== ',')
4462 input_line_pointer
++;
4463 pcreg
= tc_get_register ();
4466 assert (proc_rootP
);
4467 proc_rootP
->proc_framereg
= frame_reg
;
4468 proc_rootP
->proc_frameoffset
= frame_off
;
4469 proc_rootP
->proc_pcreg
= pcreg
;
4470 /* bob macho .frame */
4472 /* We don't have to write out a frame stab for unoptimized code. */
4473 if (!(frame_reg
== 30 && frame_off
== 0))
4476 as_warn ("No .ent for .frame to use.");
4477 (void) sprintf (str
, "R%d;%d", frame_reg
, frame_off
);
4478 symP
= symbol_new (str
, N_VFP
, 0, frag_now
);
4479 S_SET_TYPE (symP
, N_RMASK
);
4480 S_SET_OTHER (symP
, 0);
4481 S_SET_DESC (symP
, 0);
4482 symP
->sy_forward
= proc_lastP
->proc_isym
;
4483 /* bob perhaps I should have used pseudo set */
4485 demand_empty_rest_of_line ();
4489 /* The .fmask and .mask directives. */
4496 char str
[100], *strP
;
4502 mask
= get_number ();
4503 if (*input_line_pointer
== ',')
4504 input_line_pointer
++;
4505 off
= get_absolute_expression ();
4507 /* bob only for coff */
4508 assert (proc_rootP
);
4509 if (reg_type
== 'F')
4511 proc_rootP
->proc_fpreg_mask
= mask
;
4512 proc_rootP
->proc_fpreg_offset
= off
;
4516 proc_rootP
->proc_reg_mask
= mask
;
4517 proc_rootP
->proc_reg_offset
= off
;
4520 /* bob macho .mask + .fmask */
4522 /* We don't have to write out a mask stab if no saved regs. */
4526 as_warn ("No .ent for .mask to use.");
4528 for (i
= 0; i
< 32; i
++)
4532 sprintf (strP
, "%c%d,", reg_type
, i
);
4533 strP
+= strlen (strP
);
4537 sprintf (strP
, ";%d,", off
);
4538 symP
= symbol_new (str
, N_RMASK
, 0, frag_now
);
4539 S_SET_TYPE (symP
, N_RMASK
);
4540 S_SET_OTHER (symP
, 0);
4541 S_SET_DESC (symP
, 0);
4542 symP
->sy_forward
= proc_lastP
->proc_isym
;
4543 /* bob perhaps I should have used pseudo set */
4548 /* The .loc directive. */
4559 assert (now_seg
== text_section
);
4561 lineno
= get_number ();
4562 addroff
= obstack_next_free (&frags
) - frag_now
->fr_literal
;
4564 symbolP
= symbol_new ("", N_SLINE
, addroff
, frag_now
);
4565 S_SET_TYPE (symbolP
, N_SLINE
);
4566 S_SET_OTHER (symbolP
, 0);
4567 S_SET_DESC (symbolP
, lineno
);
4568 symbolP
->sy_segment
= now_seg
;
4572 #endif /* ! defined (OBJ_ECOFF) */