1 /* tc-mips.c -- assemble code for a MIPS chip.
2 Copyright (C) 1993, 1995, 1996 Free Software Foundation, Inc.
3 Contributed by the OSF and Ralph Campbell.
4 Written by Keith Knowles and Ralph Campbell, working independently.
5 Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus
8 This file is part of GAS.
10 GAS is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 2, or (at your option)
15 GAS is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with GAS; see the file COPYING. If not, write to the Free
22 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
28 #include "libiberty.h"
39 #include "opcode/mips.h"
42 /* Clean up namespace so we can include obj-elf.h too. */
43 static int mips_output_flavor () { return OUTPUT_FLAVOR
; }
44 #undef OBJ_PROCESS_STAB
50 #undef TARGET_SYMBOL_FIELDS
52 #undef obj_frob_symbol
54 #undef obj_sec_sym_ok_for_reloc
57 /* Fix any of them that we actually care about. */
59 #define OUTPUT_FLAVOR mips_output_flavor()
66 #ifndef ECOFF_DEBUGGING
67 #define NO_ECOFF_DEBUGGING
68 #define ECOFF_DEBUGGING 0
73 static char *mips_regmask_frag
;
76 #define PIC_CALL_REG 25
84 extern int target_big_endian
;
86 /* The default target format to use. */
90 switch (OUTPUT_FLAVOR
)
92 case bfd_target_aout_flavour
:
93 return target_big_endian
? "a.out-mips-big" : "a.out-mips-little";
94 case bfd_target_ecoff_flavour
:
95 return target_big_endian
? "ecoff-bigmips" : "ecoff-littlemips";
96 case bfd_target_elf_flavour
:
97 return target_big_endian
? "elf32-bigmips" : "elf32-littlemips";
103 /* The name of the readonly data section. */
104 #define RDATA_SECTION_NAME (OUTPUT_FLAVOR == bfd_target_aout_flavour \
106 : OUTPUT_FLAVOR == bfd_target_ecoff_flavour \
108 : OUTPUT_FLAVOR == bfd_target_elf_flavour \
112 /* These variables are filled in with the masks of registers used.
113 The object format code reads them and puts them in the appropriate
115 unsigned long mips_gprmask
;
116 unsigned long mips_cprmask
[4];
118 /* MIPS ISA (Instruction Set Architecture) level (may be changed
119 temporarily using .set mipsN). */
120 static int mips_isa
= -1;
122 /* MIPS ISA we are using for this output file. */
123 static int file_mips_isa
;
125 /* The CPU type as a number: 2000, 3000, 4000, 4400, etc. */
126 static int mips_cpu
= -1;
128 /* Whether the 4650 instructions (mad/madu) are permitted. */
129 static int mips_4650
= -1;
131 /* Whether the 4010 instructions are permitted. */
132 static int mips_4010
= -1;
134 /* Whether the 4100 MADD16 and DMADD16 are permitted. */
135 static int mips_4100
= -1;
137 /* Whether the processor uses hardware interlocks, and thus does not
138 require nops to be inserted. */
139 static int interlocks
= -1;
141 /* MIPS PIC level. */
145 /* Do not generate PIC code. */
148 /* Generate PIC code as in Irix 4. This is not implemented, and I'm
149 not sure what it is supposed to do. */
152 /* Generate PIC code as in the SVR4 MIPS ABI. */
155 /* Generate PIC code without using a global offset table: the data
156 segment has a maximum size of 64K, all data references are off
157 the $gp register, and all text references are PC relative. This
158 is used on some embedded systems. */
162 static enum mips_pic_level mips_pic
;
164 /* 1 if we should generate 32 bit offsets from the GP register in
165 SVR4_PIC mode. Currently has no meaning in other modes. */
166 static int mips_big_got
;
168 /* 1 if trap instructions should used for overflow rather than break
170 static int mips_trap
;
172 static int mips_warn_about_macros
;
173 static int mips_noreorder
;
174 static int mips_any_noreorder
;
175 static int mips_nomove
;
176 static int mips_noat
;
177 static int mips_nobopt
;
179 /* The size of the small data section. */
180 static int g_switch_value
= 8;
181 /* Whether the -G option was used. */
182 static int g_switch_seen
= 0;
187 /* If we can determine in advance that GP optimization won't be
188 possible, we can skip the relaxation stuff that tries to produce
189 GP-relative references. This makes delay slot optimization work
192 This function can only provide a guess, but it seems to work for
193 gcc output. If it guesses wrong, the only loss should be in
194 efficiency; it shouldn't introduce any bugs.
196 I don't know if a fix is needed for the SVR4_PIC mode. I've only
197 fixed it for the non-PIC mode. KR 95/04/07 */
198 static int nopic_need_relax
PARAMS ((symbolS
*));
200 /* handle of the OPCODE hash table */
201 static struct hash_control
*op_hash
= NULL
;
203 /* This array holds the chars that always start a comment. If the
204 pre-processor is disabled, these aren't very useful */
205 const char comment_chars
[] = "#";
207 /* This array holds the chars that only start a comment at the beginning of
208 a line. If the line seems to have the form '# 123 filename'
209 .line and .file directives will appear in the pre-processed output */
210 /* Note that input_file.c hand checks for '#' at the beginning of the
211 first line of the input file. This is because the compiler outputs
212 #NO_APP at the beginning of its output. */
213 /* Also note that C style comments are always supported. */
214 const char line_comment_chars
[] = "#";
216 /* This array holds machine specific line separator characters. */
217 const char line_separator_chars
[] = "";
219 /* Chars that can be used to separate mant from exp in floating point nums */
220 const char EXP_CHARS
[] = "eE";
222 /* Chars that mean this number is a floating point constant */
225 const char FLT_CHARS
[] = "rRsSfFdDxXpP";
227 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
228 changed in read.c . Ideally it shouldn't have to know about it at all,
229 but nothing is ideal around here.
232 static char *insn_error
;
234 static int byte_order
;
236 static int auto_align
= 1;
238 /* Symbol labelling the current insn. */
239 static symbolS
*insn_label
;
241 /* When outputting SVR4 PIC code, the assembler needs to know the
242 offset in the stack frame from which to restore the $gp register.
243 This is set by the .cprestore pseudo-op, and saved in this
245 static offsetT mips_cprestore_offset
= -1;
247 /* This is the register which holds the stack frame, as set by the
248 .frame pseudo-op. This is needed to implement .cprestore. */
249 static int mips_frame_reg
= SP
;
251 /* To output NOP instructions correctly, we need to keep information
252 about the previous two instructions. */
254 /* Whether we are optimizing. The default value of 2 means to remove
255 unneeded NOPs and swap branch instructions when possible. A value
256 of 1 means to not swap branches. A value of 0 means to always
258 static int mips_optimize
= 2;
260 /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is
261 equivalent to seeing no -g option at all. */
262 static int mips_debug
= 0;
264 /* The previous instruction. */
265 static struct mips_cl_insn prev_insn
;
267 /* The instruction before prev_insn. */
268 static struct mips_cl_insn prev_prev_insn
;
270 /* If we don't want information for prev_insn or prev_prev_insn, we
271 point the insn_mo field at this dummy integer. */
272 static const struct mips_opcode dummy_opcode
= { 0 };
274 /* Non-zero if prev_insn is valid. */
275 static int prev_insn_valid
;
277 /* The frag for the previous instruction. */
278 static struct frag
*prev_insn_frag
;
280 /* The offset into prev_insn_frag for the previous instruction. */
281 static long prev_insn_where
;
283 /* The reloc for the previous instruction, if any. */
284 static fixS
*prev_insn_fixp
;
286 /* Non-zero if the previous instruction was in a delay slot. */
287 static int prev_insn_is_delay_slot
;
289 /* Non-zero if the previous instruction was in a .set noreorder. */
290 static int prev_insn_unreordered
;
292 /* Non-zero if the previous previous instruction was in a .set
294 static int prev_prev_insn_unreordered
;
296 /* For ECOFF and ELF, relocations against symbols are done in two
297 parts, with a HI relocation and a LO relocation. Each relocation
298 has only 16 bits of space to store an addend. This means that in
299 order for the linker to handle carries correctly, it must be able
300 to locate both the HI and the LO relocation. This means that the
301 relocations must appear in order in the relocation table.
303 In order to implement this, we keep track of each unmatched HI
304 relocation. We then sort them so that they immediately precede the
305 corresponding LO relocation. */
310 struct mips_hi_fixup
*next
;
313 /* The section this fixup is in. */
317 /* The list of unmatched HI relocs. */
319 static struct mips_hi_fixup
*mips_hi_fixup_list
;
321 /* Since the MIPS does not have multiple forms of PC relative
322 instructions, we do not have to do relaxing as is done on other
323 platforms. However, we do have to handle GP relative addressing
324 correctly, which turns out to be a similar problem.
326 Every macro that refers to a symbol can occur in (at least) two
327 forms, one with GP relative addressing and one without. For
328 example, loading a global variable into a register generally uses
329 a macro instruction like this:
331 If i can be addressed off the GP register (this is true if it is in
332 the .sbss or .sdata section, or if it is known to be smaller than
333 the -G argument) this will generate the following instruction:
335 This instruction will use a GPREL reloc. If i can not be addressed
336 off the GP register, the following instruction sequence will be used:
339 In this case the first instruction will have a HI16 reloc, and the
340 second reloc will have a LO16 reloc. Both relocs will be against
343 The issue here is that we may not know whether i is GP addressable
344 until after we see the instruction that uses it. Therefore, we
345 want to be able to choose the final instruction sequence only at
346 the end of the assembly. This is similar to the way other
347 platforms choose the size of a PC relative instruction only at the
350 When generating position independent code we do not use GP
351 addressing in quite the same way, but the issue still arises as
352 external symbols and local symbols must be handled differently.
354 We handle these issues by actually generating both possible
355 instruction sequences. The longer one is put in a frag_var with
356 type rs_machine_dependent. We encode what to do with the frag in
357 the subtype field. We encode (1) the number of existing bytes to
358 replace, (2) the number of new bytes to use, (3) the offset from
359 the start of the existing bytes to the first reloc we must generate
360 (that is, the offset is applied from the start of the existing
361 bytes after they are replaced by the new bytes, if any), (4) the
362 offset from the start of the existing bytes to the second reloc,
363 (5) whether a third reloc is needed (the third reloc is always four
364 bytes after the second reloc), and (6) whether to warn if this
365 variant is used (this is sometimes needed if .set nomacro or .set
366 noat is in effect). All these numbers are reasonably small.
368 Generating two instruction sequences must be handled carefully to
369 ensure that delay slots are handled correctly. Fortunately, there
370 are a limited number of cases. When the second instruction
371 sequence is generated, append_insn is directed to maintain the
372 existing delay slot information, so it continues to apply to any
373 code after the second instruction sequence. This means that the
374 second instruction sequence must not impose any requirements not
375 required by the first instruction sequence.
377 These variant frags are then handled in functions called by the
378 machine independent code. md_estimate_size_before_relax returns
379 the final size of the frag. md_convert_frag sets up the final form
380 of the frag. tc_gen_reloc adjust the first reloc and adds a second
382 #define RELAX_ENCODE(old, new, reloc1, reloc2, reloc3, warn) \
386 | (((reloc1) + 64) << 9) \
387 | (((reloc2) + 64) << 2) \
388 | ((reloc3) ? (1 << 1) : 0) \
390 #define RELAX_OLD(i) (((i) >> 24) & 0xff)
391 #define RELAX_NEW(i) (((i) >> 16) & 0xff)
392 #define RELAX_RELOC1(i) ((bfd_vma)(((i) >> 9) & 0x7f) - 64)
393 #define RELAX_RELOC2(i) ((bfd_vma)(((i) >> 2) & 0x7f) - 64)
394 #define RELAX_RELOC3(i) (((i) >> 1) & 1)
395 #define RELAX_WARN(i) ((i) & 1)
397 /* Prototypes for static functions. */
400 #define internalError() \
401 as_fatal ("internal Error, line %d, %s", __LINE__, __FILE__)
403 #define internalError() as_fatal ("MIPS internal Error");
406 static int insn_uses_reg
PARAMS ((struct mips_cl_insn
*ip
,
407 unsigned int reg
, int fpr
));
408 static int reg_needs_delay
PARAMS ((int));
409 static void append_insn
PARAMS ((char *place
,
410 struct mips_cl_insn
* ip
,
412 bfd_reloc_code_real_type r
,
414 static void mips_no_prev_insn
PARAMS ((void));
415 static void mips_emit_delays
PARAMS ((void));
417 static void macro_build
PARAMS ((char *place
, int *counter
, expressionS
* ep
,
418 const char *name
, const char *fmt
,
421 static void macro_build ();
423 static void macro_build_lui
PARAMS ((char *place
, int *counter
,
424 expressionS
* ep
, int regnum
));
425 static void set_at
PARAMS ((int *counter
, int reg
, int unsignedp
));
426 static void check_absolute_expr
PARAMS ((struct mips_cl_insn
* ip
,
428 static void load_register
PARAMS ((int *, int, expressionS
*, int));
429 static void load_address
PARAMS ((int *counter
, int reg
, expressionS
*ep
));
430 static void macro
PARAMS ((struct mips_cl_insn
* ip
));
431 #ifdef LOSING_COMPILER
432 static void macro2
PARAMS ((struct mips_cl_insn
* ip
));
434 static void mips_ip
PARAMS ((char *str
, struct mips_cl_insn
* ip
));
435 static int my_getSmallExpression
PARAMS ((expressionS
* ep
, char *str
));
436 static void my_getExpression
PARAMS ((expressionS
* ep
, char *str
));
437 static symbolS
*get_symbol
PARAMS ((void));
438 static void mips_align
PARAMS ((int to
, int fill
, symbolS
*label
));
439 static void s_align
PARAMS ((int));
440 static void s_change_sec
PARAMS ((int));
441 static void s_cons
PARAMS ((int));
442 static void s_float_cons
PARAMS ((int));
443 static void s_mips_globl
PARAMS ((int));
444 static void s_option
PARAMS ((int));
445 static void s_mipsset
PARAMS ((int));
446 static void s_abicalls
PARAMS ((int));
447 static void s_cpload
PARAMS ((int));
448 static void s_cprestore
PARAMS ((int));
449 static void s_gpword
PARAMS ((int));
450 static void s_cpadd
PARAMS ((int));
451 static void md_obj_begin
PARAMS ((void));
452 static void md_obj_end
PARAMS ((void));
453 static long get_number
PARAMS ((void));
454 static void s_ent
PARAMS ((int));
455 static void s_mipsend
PARAMS ((int));
456 static void s_file
PARAMS ((int));
460 The following pseudo-ops from the Kane and Heinrich MIPS book
461 should be defined here, but are currently unsupported: .alias,
462 .galive, .gjaldef, .gjrlive, .livereg, .noalias.
464 The following pseudo-ops from the Kane and Heinrich MIPS book are
465 specific to the type of debugging information being generated, and
466 should be defined by the object format: .aent, .begin, .bend,
467 .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp,
470 The following pseudo-ops from the Kane and Heinrich MIPS book are
471 not MIPS CPU specific, but are also not specific to the object file
472 format. This file is probably the best place to define them, but
473 they are not currently supported: .asm0, .endr, .lab, .repeat,
474 .struct, .weakext. */
476 static const pseudo_typeS mips_pseudo_table
[] =
478 /* MIPS specific pseudo-ops. */
479 {"option", s_option
, 0},
480 {"set", s_mipsset
, 0},
481 {"rdata", s_change_sec
, 'r'},
482 {"sdata", s_change_sec
, 's'},
483 {"livereg", s_ignore
, 0},
484 {"abicalls", s_abicalls
, 0},
485 {"cpload", s_cpload
, 0},
486 {"cprestore", s_cprestore
, 0},
487 {"gpword", s_gpword
, 0},
488 {"cpadd", s_cpadd
, 0},
490 /* Relatively generic pseudo-ops that happen to be used on MIPS
492 {"asciiz", stringer
, 1},
493 {"bss", s_change_sec
, 'b'},
496 {"dword", s_cons
, 3},
498 /* These pseudo-ops are defined in read.c, but must be overridden
499 here for one reason or another. */
500 {"align", s_align
, 0},
502 {"data", s_change_sec
, 'd'},
503 {"double", s_float_cons
, 'd'},
504 {"float", s_float_cons
, 'f'},
505 {"globl", s_mips_globl
, 0},
506 {"global", s_mips_globl
, 0},
507 {"hword", s_cons
, 1},
512 {"short", s_cons
, 1},
513 {"single", s_float_cons
, 'f'},
514 {"text", s_change_sec
, 't'},
519 static const pseudo_typeS mips_nonecoff_pseudo_table
[] = {
520 /* These pseudo-ops should be defined by the object file format.
521 However, a.out doesn't support them, so we have versions here. */
523 {"bgnb", s_ignore
, 0},
524 {"end", s_mipsend
, 0},
525 {"endb", s_ignore
, 0},
528 {"fmask", s_ignore
, 'F'},
529 {"frame", s_ignore
, 0},
530 {"loc", s_ignore
, 0},
531 {"mask", s_ignore
, 'R'},
532 {"verstamp", s_ignore
, 0},
536 extern void pop_insert
PARAMS ((const pseudo_typeS
*));
541 pop_insert (mips_pseudo_table
);
542 if (! ECOFF_DEBUGGING
)
543 pop_insert (mips_nonecoff_pseudo_table
);
546 static char *expr_end
;
548 /* Expressions which appear in instructions. These are set by
551 static expressionS imm_expr
;
552 static expressionS offset_expr
;
554 /* Relocs associated with imm_expr and offset_expr. */
556 static bfd_reloc_code_real_type imm_reloc
;
557 static bfd_reloc_code_real_type offset_reloc
;
559 /* This is set by mips_ip if imm_reloc is an unmatched HI16_S reloc. */
561 static boolean imm_unmatched_hi
;
564 * This function is called once, at assembler startup time. It should
565 * set up all the tables, etc. that the MD part of the assembler will need.
571 register const char *retval
= NULL
;
572 register unsigned int i
= 0;
580 if (strcmp (cpu
+ (sizeof TARGET_CPU
) - 3, "el") == 0)
582 a
= xmalloc (sizeof TARGET_CPU
);
583 strcpy (a
, TARGET_CPU
);
584 a
[(sizeof TARGET_CPU
) - 3] = '\0';
588 if (strcmp (cpu
, "mips") == 0)
594 else if (strcmp (cpu
, "r6000") == 0
595 || strcmp (cpu
, "mips2") == 0)
601 else if (strcmp (cpu
, "mips64") == 0
602 || strcmp (cpu
, "r4000") == 0
603 || strcmp (cpu
, "mips3") == 0)
609 else if (strcmp (cpu
, "r4400") == 0)
615 else if (strcmp (cpu
, "mips64orion") == 0
616 || strcmp (cpu
, "r4600") == 0)
622 else if (strcmp (cpu
, "r4650") == 0)
630 else if (strcmp (cpu
, "mips64vr4300") == 0)
636 else if (strcmp (cpu
, "mips64vr4100") == 0)
644 else if (strcmp (cpu
, "r4010") == 0)
652 else if (strcmp (cpu
, "r8000") == 0
653 || strcmp (cpu
, "mips4") == 0)
659 else if (strcmp (cpu
, "r10000") == 0)
685 if (mips_4650
|| mips_4010
|| mips_4100
)
690 if (mips_isa
< 2 && mips_trap
)
691 as_bad ("trap exception not supported at ISA 1");
696 ok
= bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, 3000);
699 ok
= bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, 6000);
702 ok
= bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, 4000);
705 ok
= bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, 8000);
709 as_warn ("Could not set architecture and machine");
711 file_mips_isa
= mips_isa
;
713 op_hash
= hash_new ();
715 for (i
= 0; i
< NUMOPCODES
;)
717 const char *name
= mips_opcodes
[i
].name
;
719 retval
= hash_insert (op_hash
, name
, (PTR
) &mips_opcodes
[i
]);
722 fprintf (stderr
, "internal error: can't hash `%s': %s\n",
723 mips_opcodes
[i
].name
, retval
);
724 as_fatal ("Broken assembler. No assembly attempted.");
728 if (mips_opcodes
[i
].pinfo
!= INSN_MACRO
729 && ((mips_opcodes
[i
].match
& mips_opcodes
[i
].mask
)
730 != mips_opcodes
[i
].match
))
732 fprintf (stderr
, "internal error: bad opcode: `%s' \"%s\"\n",
733 mips_opcodes
[i
].name
, mips_opcodes
[i
].args
);
734 as_fatal ("Broken assembler. No assembly attempted.");
738 while ((i
< NUMOPCODES
) && !strcmp (mips_opcodes
[i
].name
, name
));
741 mips_no_prev_insn ();
749 /* set the default alignment for the text section (2**2) */
750 record_alignment (text_section
, 2);
752 if (USE_GLOBAL_POINTER_OPT
)
753 bfd_set_gp_size (stdoutput
, g_switch_value
);
755 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
757 /* Sections must be aligned to 16 byte boundaries. */
758 (void) bfd_set_section_alignment (stdoutput
, text_section
, 4);
759 (void) bfd_set_section_alignment (stdoutput
, data_section
, 4);
760 (void) bfd_set_section_alignment (stdoutput
, bss_section
, 4);
762 /* Create a .reginfo section for register masks and a .mdebug
763 section for debugging information. */
771 sec
= subseg_new (".reginfo", (subsegT
) 0);
773 /* The ABI says this section should be loaded so that the
774 running program can access it. */
775 (void) bfd_set_section_flags (stdoutput
, sec
,
776 (SEC_ALLOC
| SEC_LOAD
777 | SEC_READONLY
| SEC_DATA
));
778 (void) bfd_set_section_alignment (stdoutput
, sec
, 2);
781 mips_regmask_frag
= frag_more (sizeof (Elf32_External_RegInfo
));
786 sec
= subseg_new (".mdebug", (subsegT
) 0);
787 (void) bfd_set_section_flags (stdoutput
, sec
,
788 SEC_HAS_CONTENTS
| SEC_READONLY
);
789 (void) bfd_set_section_alignment (stdoutput
, sec
, 2);
792 subseg_set (seg
, subseg
);
796 if (! ECOFF_DEBUGGING
)
803 if (! ECOFF_DEBUGGING
)
811 struct mips_cl_insn insn
;
813 imm_expr
.X_op
= O_absent
;
814 imm_reloc
= BFD_RELOC_UNUSED
;
815 imm_unmatched_hi
= false;
816 offset_expr
.X_op
= O_absent
;
817 offset_reloc
= BFD_RELOC_UNUSED
;
819 mips_ip (str
, &insn
);
822 as_bad ("%s `%s'", insn_error
, str
);
825 if (insn
.insn_mo
->pinfo
== INSN_MACRO
)
831 if (imm_expr
.X_op
!= O_absent
)
832 append_insn ((char *) NULL
, &insn
, &imm_expr
, imm_reloc
,
834 else if (offset_expr
.X_op
!= O_absent
)
835 append_insn ((char *) NULL
, &insn
, &offset_expr
, offset_reloc
, false);
837 append_insn ((char *) NULL
, &insn
, NULL
, BFD_RELOC_UNUSED
, false);
841 /* See whether instruction IP reads register REG. If FPR is non-zero,
842 REG is a floating point register. */
845 insn_uses_reg (ip
, reg
, fpr
)
846 struct mips_cl_insn
*ip
;
850 /* Don't report on general register 0, since it never changes. */
851 if (! fpr
&& reg
== 0)
856 /* If we are called with either $f0 or $f1, we must check $f0.
857 This is not optimal, because it will introduce an unnecessary
858 NOP between "lwc1 $f0" and "swc1 $f1". To fix this we would
859 need to distinguish reading both $f0 and $f1 or just one of
860 them. Note that we don't have to check the other way,
861 because there is no instruction that sets both $f0 and $f1
862 and requires a delay. */
863 if ((ip
->insn_mo
->pinfo
& INSN_READ_FPR_S
)
864 && (((ip
->insn_opcode
>> OP_SH_FS
) & OP_MASK_FS
)
865 == (reg
&~ (unsigned) 1)))
867 if ((ip
->insn_mo
->pinfo
& INSN_READ_FPR_T
)
868 && (((ip
->insn_opcode
>> OP_SH_FT
) & OP_MASK_FT
)
869 == (reg
&~ (unsigned) 1)))
874 if ((ip
->insn_mo
->pinfo
& INSN_READ_GPR_S
)
875 && ((ip
->insn_opcode
>> OP_SH_RS
) & OP_MASK_RS
) == reg
)
877 if ((ip
->insn_mo
->pinfo
& INSN_READ_GPR_T
)
878 && ((ip
->insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
) == reg
)
885 /* This function returns true if modifying a register requires a
889 reg_needs_delay (reg
)
892 unsigned long prev_pinfo
;
894 prev_pinfo
= prev_insn
.insn_mo
->pinfo
;
897 && ((prev_pinfo
& INSN_LOAD_COPROC_DELAY
)
899 && (prev_pinfo
& INSN_LOAD_MEMORY_DELAY
))))
901 /* A load from a coprocessor or from memory. All load
902 delays delay the use of general register rt for one
903 instruction on the r3000. The r6000 and r4000 use
905 know (prev_pinfo
& INSN_WRITE_GPR_T
);
906 if (reg
== ((prev_insn
.insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
))
913 /* Output an instruction. PLACE is where to put the instruction; if
914 it is NULL, this uses frag_more to get room. IP is the instruction
915 information. ADDRESS_EXPR is an operand of the instruction to be
916 used with RELOC_TYPE. */
919 append_insn (place
, ip
, address_expr
, reloc_type
, unmatched_hi
)
921 struct mips_cl_insn
*ip
;
922 expressionS
*address_expr
;
923 bfd_reloc_code_real_type reloc_type
;
924 boolean unmatched_hi
;
926 register unsigned long prev_pinfo
, pinfo
;
931 prev_pinfo
= prev_insn
.insn_mo
->pinfo
;
932 pinfo
= ip
->insn_mo
->pinfo
;
934 if (place
== NULL
&& ! mips_noreorder
)
936 /* If the previous insn required any delay slots, see if we need
937 to insert a NOP or two. There are eight kinds of possible
938 hazards, of which an instruction can have at most one type.
939 (1) a load from memory delay
940 (2) a load from a coprocessor delay
941 (3) an unconditional branch delay
942 (4) a conditional branch delay
943 (5) a move to coprocessor register delay
944 (6) a load coprocessor register from memory delay
945 (7) a coprocessor condition code delay
946 (8) a HI/LO special register delay
948 There are a lot of optimizations we could do that we don't.
949 In particular, we do not, in general, reorder instructions.
950 If you use gcc with optimization, it will reorder
951 instructions and generally do much more optimization then we
952 do here; repeating all that work in the assembler would only
953 benefit hand written assembly code, and does not seem worth
956 /* This is how a NOP is emitted. */
957 #define emit_nop() md_number_to_chars (frag_more (4), 0, 4)
959 /* The previous insn might require a delay slot, depending upon
960 the contents of the current insn. */
962 && ((prev_pinfo
& INSN_LOAD_COPROC_DELAY
)
964 && (prev_pinfo
& INSN_LOAD_MEMORY_DELAY
))))
966 /* A load from a coprocessor or from memory. All load
967 delays delay the use of general register rt for one
968 instruction on the r3000. The r6000 and r4000 use
970 know (prev_pinfo
& INSN_WRITE_GPR_T
);
971 if (mips_optimize
== 0
972 || insn_uses_reg (ip
,
973 ((prev_insn
.insn_opcode
>> OP_SH_RT
)
978 else if (mips_isa
< 4
979 && ((prev_pinfo
& INSN_COPROC_MOVE_DELAY
)
981 && (prev_pinfo
& INSN_COPROC_MEMORY_DELAY
))))
983 /* A generic coprocessor delay. The previous instruction
984 modified a coprocessor general or control register. If
985 it modified a control register, we need to avoid any
986 coprocessor instruction (this is probably not always
987 required, but it sometimes is). If it modified a general
988 register, we avoid using that register.
990 On the r6000 and r4000 loading a coprocessor register
991 from memory is interlocked, and does not require a delay.
993 This case is not handled very well. There is no special
994 knowledge of CP0 handling, and the coprocessors other
995 than the floating point unit are not distinguished at
997 if (prev_pinfo
& INSN_WRITE_FPR_T
)
999 if (mips_optimize
== 0
1000 || insn_uses_reg (ip
,
1001 ((prev_insn
.insn_opcode
>> OP_SH_FT
)
1006 else if (prev_pinfo
& INSN_WRITE_FPR_S
)
1008 if (mips_optimize
== 0
1009 || insn_uses_reg (ip
,
1010 ((prev_insn
.insn_opcode
>> OP_SH_FS
)
1017 /* We don't know exactly what the previous instruction
1018 does. If the current instruction uses a coprocessor
1019 register, we must insert a NOP. If previous
1020 instruction may set the condition codes, and the
1021 current instruction uses them, we must insert two
1023 if (mips_optimize
== 0
1024 || ((prev_pinfo
& INSN_WRITE_COND_CODE
)
1025 && (pinfo
& INSN_READ_COND_CODE
)))
1027 else if (pinfo
& INSN_COP
)
1031 else if (mips_isa
< 4
1032 && (prev_pinfo
& INSN_WRITE_COND_CODE
))
1034 /* The previous instruction sets the coprocessor condition
1035 codes, but does not require a general coprocessor delay
1036 (this means it is a floating point comparison
1037 instruction). If this instruction uses the condition
1038 codes, we need to insert a single NOP. */
1039 if (mips_optimize
== 0
1040 || (pinfo
& INSN_READ_COND_CODE
))
1043 else if (prev_pinfo
& INSN_READ_LO
)
1045 /* The previous instruction reads the LO register; if the
1046 current instruction writes to the LO register, we must
1047 insert two NOPS. The R4650 and VR4100 have interlocks. */
1049 && (mips_optimize
== 0
1050 || (pinfo
& INSN_WRITE_LO
)))
1053 else if (prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
1055 /* The previous instruction reads the HI register; if the
1056 current instruction writes to the HI register, we must
1057 insert a NOP. The R4650 and VR4100 have interlocks. */
1059 && (mips_optimize
== 0
1060 || (pinfo
& INSN_WRITE_HI
)))
1064 /* There are two cases which require two intervening
1065 instructions: 1) setting the condition codes using a move to
1066 coprocessor instruction which requires a general coprocessor
1067 delay and then reading the condition codes 2) reading the HI
1068 or LO register and then writing to it (except on the R4650,
1069 and VR4100 which have interlocks). If we are not already
1070 emitting a NOP instruction, we must check for these cases
1071 compared to the instruction previous to the previous
1075 && (prev_prev_insn
.insn_mo
->pinfo
& INSN_COPROC_MOVE_DELAY
)
1076 && (prev_prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
)
1077 && (pinfo
& INSN_READ_COND_CODE
))
1078 || ((prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
)
1079 && (pinfo
& INSN_WRITE_LO
)
1081 || ((prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
1082 && (pinfo
& INSN_WRITE_HI
)
1086 /* If we are being given a nop instruction, don't bother with
1087 one of the nops we would otherwise output. This will only
1088 happen when a nop instruction is used with mips_optimize set
1090 if (nops
> 0 && ip
->insn_opcode
== 0)
1093 /* Now emit the right number of NOP instructions. */
1098 for (i
= 0; i
< nops
; i
++)
1102 listing_prev_line ();
1103 /* We may be at the start of a variant frag. In case we
1104 are, make sure there is enough space for the frag
1105 after the frags created by listing_prev_line. The
1106 argument to frag_grow here must be at least as large
1107 as the argument to all other calls to frag_grow in
1108 this file. We don't have to worry about being in the
1109 middle of a variant frag, because the variants insert
1110 all needed nop instructions themselves. */
1113 if (insn_label
!= NULL
)
1115 assert (S_GET_SEGMENT (insn_label
) == now_seg
);
1116 insn_label
->sy_frag
= frag_now
;
1117 S_SET_VALUE (insn_label
, (valueT
) frag_now_fix ());
1127 if (address_expr
!= NULL
)
1129 if (address_expr
->X_op
== O_constant
)
1134 ip
->insn_opcode
|= address_expr
->X_add_number
;
1137 case BFD_RELOC_LO16
:
1138 ip
->insn_opcode
|= address_expr
->X_add_number
& 0xffff;
1141 case BFD_RELOC_MIPS_JMP
:
1142 case BFD_RELOC_16_PCREL_S2
:
1151 assert (reloc_type
!= BFD_RELOC_UNUSED
);
1153 /* Don't generate a reloc if we are writing into a variant
1157 fixp
= fix_new_exp (frag_now
, f
- frag_now
->fr_literal
, 4,
1159 reloc_type
== BFD_RELOC_16_PCREL_S2
,
1163 struct mips_hi_fixup
*hi_fixup
;
1165 assert (reloc_type
== BFD_RELOC_HI16_S
);
1166 hi_fixup
= ((struct mips_hi_fixup
*)
1167 xmalloc (sizeof (struct mips_hi_fixup
)));
1168 hi_fixup
->fixp
= fixp
;
1169 hi_fixup
->seg
= now_seg
;
1170 hi_fixup
->next
= mips_hi_fixup_list
;
1171 mips_hi_fixup_list
= hi_fixup
;
1177 md_number_to_chars (f
, ip
->insn_opcode
, 4);
1179 /* Update the register mask information. */
1180 if (pinfo
& INSN_WRITE_GPR_D
)
1181 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
);
1182 if ((pinfo
& (INSN_WRITE_GPR_T
| INSN_READ_GPR_T
)) != 0)
1183 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
);
1184 if (pinfo
& INSN_READ_GPR_S
)
1185 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> OP_SH_RS
) & OP_MASK_RS
);
1186 if (pinfo
& INSN_WRITE_GPR_31
)
1187 mips_gprmask
|= 1 << 31;
1188 if (pinfo
& INSN_WRITE_FPR_D
)
1189 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FD
) & OP_MASK_FD
);
1190 if ((pinfo
& (INSN_WRITE_FPR_S
| INSN_READ_FPR_S
)) != 0)
1191 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FS
) & OP_MASK_FS
);
1192 if ((pinfo
& (INSN_WRITE_FPR_T
| INSN_READ_FPR_T
)) != 0)
1193 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FT
) & OP_MASK_FT
);
1194 if ((pinfo
& INSN_READ_FPR_R
) != 0)
1195 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FR
) & OP_MASK_FR
);
1196 if (pinfo
& INSN_COP
)
1198 /* We don't keep enough information to sort these cases out. */
1200 /* Never set the bit for $0, which is always zero. */
1201 mips_gprmask
&=~ 1 << 0;
1203 if (place
== NULL
&& ! mips_noreorder
)
1205 /* Filling the branch delay slot is more complex. We try to
1206 switch the branch with the previous instruction, which we can
1207 do if the previous instruction does not set up a condition
1208 that the branch tests and if the branch is not itself the
1209 target of any branch. */
1210 if ((pinfo
& INSN_UNCOND_BRANCH_DELAY
)
1211 || (pinfo
& INSN_COND_BRANCH_DELAY
))
1213 if (mips_optimize
< 2
1214 /* If we have seen .set volatile or .set nomove, don't
1217 /* If we had to emit any NOP instructions, then we
1218 already know we can not swap. */
1220 /* If we don't even know the previous insn, we can not
1222 || ! prev_insn_valid
1223 /* If the previous insn is already in a branch delay
1224 slot, then we can not swap. */
1225 || prev_insn_is_delay_slot
1226 /* If the previous previous insn was in a .set
1227 noreorder, we can't swap. Actually, the MIPS
1228 assembler will swap in this situation. However, gcc
1229 configured -with-gnu-as will generate code like
1235 in which we can not swap the bne and INSN. If gcc is
1236 not configured -with-gnu-as, it does not output the
1237 .set pseudo-ops. We don't have to check
1238 prev_insn_unreordered, because prev_insn_valid will
1239 be 0 in that case. We don't want to use
1240 prev_prev_insn_valid, because we do want to be able
1241 to swap at the start of a function. */
1242 || prev_prev_insn_unreordered
1243 /* If the branch is itself the target of a branch, we
1244 can not swap. We cheat on this; all we check for is
1245 whether there is a label on this instruction. If
1246 there are any branches to anything other than a
1247 label, users must use .set noreorder. */
1248 || insn_label
!= NULL
1249 /* If the previous instruction is in a variant frag, we
1250 can not do the swap. */
1251 || prev_insn_frag
->fr_type
== rs_machine_dependent
1252 /* If the branch reads the condition codes, we don't
1253 even try to swap, because in the sequence
1258 we can not swap, and I don't feel like handling that
1261 && (pinfo
& INSN_READ_COND_CODE
))
1262 /* We can not swap with an instruction that requires a
1263 delay slot, becase the target of the branch might
1264 interfere with that instruction. */
1267 & (INSN_LOAD_COPROC_DELAY
1268 | INSN_COPROC_MOVE_DELAY
1269 | INSN_WRITE_COND_CODE
)))
1276 & (INSN_LOAD_MEMORY_DELAY
1277 | INSN_COPROC_MEMORY_DELAY
)))
1278 /* We can not swap with a branch instruction. */
1280 & (INSN_UNCOND_BRANCH_DELAY
1281 | INSN_COND_BRANCH_DELAY
1282 | INSN_COND_BRANCH_LIKELY
))
1283 /* We do not swap with a trap instruction, since it
1284 complicates trap handlers to have the trap
1285 instruction be in a delay slot. */
1286 || (prev_pinfo
& INSN_TRAP
)
1287 /* If the branch reads a register that the previous
1288 instruction sets, we can not swap. */
1289 || ((prev_pinfo
& INSN_WRITE_GPR_T
)
1290 && insn_uses_reg (ip
,
1291 ((prev_insn
.insn_opcode
>> OP_SH_RT
)
1294 || ((prev_pinfo
& INSN_WRITE_GPR_D
)
1295 && insn_uses_reg (ip
,
1296 ((prev_insn
.insn_opcode
>> OP_SH_RD
)
1299 /* If the branch writes a register that the previous
1300 instruction sets, we can not swap (we know that
1301 branches write only to RD or to $31). */
1302 || ((prev_pinfo
& INSN_WRITE_GPR_T
)
1303 && (((pinfo
& INSN_WRITE_GPR_D
)
1304 && (((prev_insn
.insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
)
1305 == ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)))
1306 || ((pinfo
& INSN_WRITE_GPR_31
)
1307 && (((prev_insn
.insn_opcode
>> OP_SH_RT
)
1310 || ((prev_pinfo
& INSN_WRITE_GPR_D
)
1311 && (((pinfo
& INSN_WRITE_GPR_D
)
1312 && (((prev_insn
.insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)
1313 == ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)))
1314 || ((pinfo
& INSN_WRITE_GPR_31
)
1315 && (((prev_insn
.insn_opcode
>> OP_SH_RD
)
1318 /* If the branch writes a register that the previous
1319 instruction reads, we can not swap (we know that
1320 branches only write to RD or to $31). */
1321 || ((pinfo
& INSN_WRITE_GPR_D
)
1322 && insn_uses_reg (&prev_insn
,
1323 ((ip
->insn_opcode
>> OP_SH_RD
)
1326 || ((pinfo
& INSN_WRITE_GPR_31
)
1327 && insn_uses_reg (&prev_insn
, 31, 0))
1328 /* If we are generating embedded PIC code, the branch
1329 might be expanded into a sequence which uses $at, so
1330 we can't swap with an instruction which reads it. */
1331 || (mips_pic
== EMBEDDED_PIC
1332 && insn_uses_reg (&prev_insn
, AT
, 0))
1333 /* If the previous previous instruction has a load
1334 delay, and sets a register that the branch reads, we
1337 && ((prev_prev_insn
.insn_mo
->pinfo
& INSN_LOAD_COPROC_DELAY
)
1339 && (prev_prev_insn
.insn_mo
->pinfo
1340 & INSN_LOAD_MEMORY_DELAY
)))
1341 && insn_uses_reg (ip
,
1342 ((prev_prev_insn
.insn_opcode
>> OP_SH_RT
)
1346 /* We could do even better for unconditional branches to
1347 portions of this object file; we could pick up the
1348 instruction at the destination, put it in the delay
1349 slot, and bump the destination address. */
1351 /* Update the previous insn information. */
1352 prev_prev_insn
= *ip
;
1353 prev_insn
.insn_mo
= &dummy_opcode
;
1360 /* It looks like we can actually do the swap. */
1361 prev_f
= prev_insn_frag
->fr_literal
+ prev_insn_where
;
1362 memcpy (temp
, prev_f
, 4);
1363 memcpy (prev_f
, f
, 4);
1364 memcpy (f
, temp
, 4);
1367 prev_insn_fixp
->fx_frag
= frag_now
;
1368 prev_insn_fixp
->fx_where
= f
- frag_now
->fr_literal
;
1372 fixp
->fx_frag
= prev_insn_frag
;
1373 fixp
->fx_where
= prev_insn_where
;
1375 /* Update the previous insn information; leave prev_insn
1377 prev_prev_insn
= *ip
;
1379 prev_insn_is_delay_slot
= 1;
1381 /* If that was an unconditional branch, forget the previous
1382 insn information. */
1383 if (pinfo
& INSN_UNCOND_BRANCH_DELAY
)
1385 prev_prev_insn
.insn_mo
= &dummy_opcode
;
1386 prev_insn
.insn_mo
= &dummy_opcode
;
1389 else if (pinfo
& INSN_COND_BRANCH_LIKELY
)
1391 /* We don't yet optimize a branch likely. What we should do
1392 is look at the target, copy the instruction found there
1393 into the delay slot, and increment the branch to jump to
1394 the next instruction. */
1396 /* Update the previous insn information. */
1397 prev_prev_insn
= *ip
;
1398 prev_insn
.insn_mo
= &dummy_opcode
;
1402 /* Update the previous insn information. */
1404 prev_prev_insn
.insn_mo
= &dummy_opcode
;
1406 prev_prev_insn
= prev_insn
;
1409 /* Any time we see a branch, we always fill the delay slot
1410 immediately; since this insn is not a branch, we know it
1411 is not in a delay slot. */
1412 prev_insn_is_delay_slot
= 0;
1415 prev_prev_insn_unreordered
= prev_insn_unreordered
;
1416 prev_insn_unreordered
= 0;
1417 prev_insn_frag
= frag_now
;
1418 prev_insn_where
= f
- frag_now
->fr_literal
;
1419 prev_insn_fixp
= fixp
;
1420 prev_insn_valid
= 1;
1423 /* We just output an insn, so the next one doesn't have a label. */
1427 /* This function forgets that there was any previous instruction or
1431 mips_no_prev_insn ()
1433 prev_insn
.insn_mo
= &dummy_opcode
;
1434 prev_prev_insn
.insn_mo
= &dummy_opcode
;
1435 prev_insn_valid
= 0;
1436 prev_insn_is_delay_slot
= 0;
1437 prev_insn_unreordered
= 0;
1438 prev_prev_insn_unreordered
= 0;
1442 /* This function must be called whenever we turn on noreorder or emit
1443 something other than instructions. It inserts any NOPS which might
1444 be needed by the previous instruction, and clears the information
1445 kept for the previous instructions. */
1450 if (! mips_noreorder
)
1456 && (prev_insn
.insn_mo
->pinfo
1457 & (INSN_LOAD_COPROC_DELAY
1458 | INSN_COPROC_MOVE_DELAY
1459 | INSN_WRITE_COND_CODE
)))
1461 && (prev_insn
.insn_mo
->pinfo
1465 && (prev_insn
.insn_mo
->pinfo
1466 & (INSN_LOAD_MEMORY_DELAY
1467 | INSN_COPROC_MEMORY_DELAY
))))
1471 && (prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
))
1473 && ((prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
1474 || (prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
))))
1477 else if ((mips_isa
< 4
1478 && (prev_prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
))
1480 && ((prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
1481 || (prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
))))
1486 if (insn_label
!= NULL
)
1488 assert (S_GET_SEGMENT (insn_label
) == now_seg
);
1489 insn_label
->sy_frag
= frag_now
;
1490 S_SET_VALUE (insn_label
, (valueT
) frag_now_fix ());
1495 mips_no_prev_insn ();
1498 /* Build an instruction created by a macro expansion. This is passed
1499 a pointer to the count of instructions created so far, an
1500 expression, the name of the instruction to build, an operand format
1501 string, and corresponding arguments. */
1505 macro_build (char *place
,
1513 macro_build (place
, counter
, ep
, name
, fmt
, va_alist
)
1522 struct mips_cl_insn insn
;
1523 bfd_reloc_code_real_type r
;
1527 va_start (args
, fmt
);
1533 * If the macro is about to expand into a second instruction,
1534 * print a warning if needed. We need to pass ip as a parameter
1535 * to generate a better warning message here...
1537 if (mips_warn_about_macros
&& place
== NULL
&& *counter
== 1)
1538 as_warn ("Macro instruction expanded into multiple instructions");
1541 *counter
+= 1; /* bump instruction counter */
1543 r
= BFD_RELOC_UNUSED
;
1544 insn
.insn_mo
= (struct mips_opcode
*) hash_find (op_hash
, name
);
1545 assert (insn
.insn_mo
);
1546 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
1548 while (strcmp (fmt
, insn
.insn_mo
->args
) != 0
1549 || insn
.insn_mo
->pinfo
== INSN_MACRO
1550 || ((insn
.insn_mo
->pinfo
& INSN_ISA
) == INSN_ISA2
1552 || ((insn
.insn_mo
->pinfo
& INSN_ISA
) == INSN_ISA3
1554 || ((insn
.insn_mo
->pinfo
& INSN_ISA
) == INSN_ISA4
1556 || ((insn
.insn_mo
->pinfo
& INSN_ISA
) == INSN_4650
1558 || ((insn
.insn_mo
->pinfo
& INSN_ISA
) == INSN_4010
1560 || ((insn
.insn_mo
->pinfo
& INSN_ISA
) == INSN_4100
1564 assert (insn
.insn_mo
->name
);
1565 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
1567 insn
.insn_opcode
= insn
.insn_mo
->match
;
1583 insn
.insn_opcode
|= va_arg (args
, int) << 16;
1589 insn
.insn_opcode
|= va_arg (args
, int) << 16;
1594 insn
.insn_opcode
|= va_arg (args
, int) << 11;
1599 insn
.insn_opcode
|= va_arg (args
, int) << 11;
1606 insn
.insn_opcode
|= va_arg (args
, int) << 6;
1610 insn
.insn_opcode
|= va_arg (args
, int) << 6;
1614 insn
.insn_opcode
|= va_arg (args
, int) << 6;
1621 insn
.insn_opcode
|= va_arg (args
, int) << 21;
1627 r
= (bfd_reloc_code_real_type
) va_arg (args
, int);
1628 assert (r
== BFD_RELOC_MIPS_GPREL
1629 || r
== BFD_RELOC_MIPS_LITERAL
1630 || r
== BFD_RELOC_LO16
1631 || r
== BFD_RELOC_MIPS_GOT16
1632 || r
== BFD_RELOC_MIPS_CALL16
1633 || r
== BFD_RELOC_MIPS_GOT_LO16
1634 || r
== BFD_RELOC_MIPS_CALL_LO16
1635 || (ep
->X_op
== O_subtract
1636 && now_seg
== text_section
1637 && r
== BFD_RELOC_PCREL_LO16
));
1641 r
= (bfd_reloc_code_real_type
) va_arg (args
, int);
1643 && (ep
->X_op
== O_constant
1644 || (ep
->X_op
== O_symbol
1645 && (r
== BFD_RELOC_HI16_S
1646 || r
== BFD_RELOC_HI16
1647 || r
== BFD_RELOC_MIPS_GOT_HI16
1648 || r
== BFD_RELOC_MIPS_CALL_HI16
))
1649 || (ep
->X_op
== O_subtract
1650 && now_seg
== text_section
1651 && r
== BFD_RELOC_PCREL_HI16_S
)));
1652 if (ep
->X_op
== O_constant
)
1654 insn
.insn_opcode
|= (ep
->X_add_number
>> 16) & 0xffff;
1656 r
= BFD_RELOC_UNUSED
;
1661 assert (ep
!= NULL
);
1663 * This allows macro() to pass an immediate expression for
1664 * creating short branches without creating a symbol.
1665 * Note that the expression still might come from the assembly
1666 * input, in which case the value is not checked for range nor
1667 * is a relocation entry generated (yuck).
1669 if (ep
->X_op
== O_constant
)
1671 insn
.insn_opcode
|= (ep
->X_add_number
>> 2) & 0xffff;
1675 r
= BFD_RELOC_16_PCREL_S2
;
1679 assert (ep
!= NULL
);
1680 r
= BFD_RELOC_MIPS_JMP
;
1689 assert (r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
1691 append_insn (place
, &insn
, ep
, r
, false);
1695 * Generate a "lui" instruction.
1698 macro_build_lui (place
, counter
, ep
, regnum
)
1704 expressionS high_expr
;
1705 struct mips_cl_insn insn
;
1706 bfd_reloc_code_real_type r
;
1707 CONST
char *name
= "lui";
1708 CONST
char *fmt
= "t,u";
1714 high_expr
.X_op
= O_constant
;
1715 high_expr
.X_add_number
= ep
->X_add_number
;
1718 if (high_expr
.X_op
== O_constant
)
1720 /* we can compute the instruction now without a relocation entry */
1721 if (high_expr
.X_add_number
& 0x8000)
1722 high_expr
.X_add_number
+= 0x10000;
1723 high_expr
.X_add_number
=
1724 ((unsigned long) high_expr
.X_add_number
>> 16) & 0xffff;
1725 r
= BFD_RELOC_UNUSED
;
1729 assert (ep
->X_op
== O_symbol
);
1730 /* _gp_disp is a special case, used from s_cpload. */
1731 assert (mips_pic
== NO_PIC
1732 || strcmp (S_GET_NAME (ep
->X_add_symbol
), "_gp_disp") == 0);
1733 r
= BFD_RELOC_HI16_S
;
1737 * If the macro is about to expand into a second instruction,
1738 * print a warning if needed. We need to pass ip as a parameter
1739 * to generate a better warning message here...
1741 if (mips_warn_about_macros
&& place
== NULL
&& *counter
== 1)
1742 as_warn ("Macro instruction expanded into multiple instructions");
1745 *counter
+= 1; /* bump instruction counter */
1747 insn
.insn_mo
= (struct mips_opcode
*) hash_find (op_hash
, name
);
1748 assert (insn
.insn_mo
);
1749 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
1750 assert (strcmp (fmt
, insn
.insn_mo
->args
) == 0);
1752 insn
.insn_opcode
= insn
.insn_mo
->match
| (regnum
<< OP_SH_RT
);
1753 if (r
== BFD_RELOC_UNUSED
)
1755 insn
.insn_opcode
|= high_expr
.X_add_number
;
1756 append_insn (place
, &insn
, NULL
, r
, false);
1759 append_insn (place
, &insn
, &high_expr
, r
, false);
1763 * Generates code to set the $at register to true (one)
1764 * if reg is less than the immediate expression.
1767 set_at (counter
, reg
, unsignedp
)
1772 if (imm_expr
.X_add_number
>= -0x8000 && imm_expr
.X_add_number
< 0x8000)
1773 macro_build ((char *) NULL
, counter
, &imm_expr
,
1774 unsignedp
? "sltiu" : "slti",
1775 "t,r,j", AT
, reg
, (int) BFD_RELOC_LO16
);
1778 load_register (counter
, AT
, &imm_expr
, 0);
1779 macro_build ((char *) NULL
, counter
, NULL
,
1780 unsignedp
? "sltu" : "slt",
1781 "d,v,t", AT
, reg
, AT
);
1785 /* Warn if an expression is not a constant. */
1788 check_absolute_expr (ip
, ex
)
1789 struct mips_cl_insn
*ip
;
1792 if (ex
->X_op
!= O_constant
)
1793 as_warn ("Instruction %s requires absolute expression", ip
->insn_mo
->name
);
1797 * This routine generates the least number of instructions neccessary to load
1798 * an absolute expression value into a register.
1801 load_register (counter
, reg
, ep
, dbl
)
1808 expressionS hi32
, lo32
, tmp
;
1810 if (ep
->X_op
!= O_big
)
1812 assert (ep
->X_op
== O_constant
);
1813 if (ep
->X_add_number
< 0x8000
1814 && (ep
->X_add_number
>= 0
1815 || (ep
->X_add_number
>= -0x8000
1818 || sizeof (ep
->X_add_number
) > 4))))
1820 /* We can handle 16 bit signed values with an addiu to
1821 $zero. No need to ever use daddiu here, since $zero and
1822 the result are always correct in 32 bit mode. */
1823 macro_build ((char *) NULL
, counter
, ep
, "addiu", "t,r,j", reg
, 0,
1824 (int) BFD_RELOC_LO16
);
1827 else if (ep
->X_add_number
>= 0 && ep
->X_add_number
< 0x10000)
1829 /* We can handle 16 bit unsigned values with an ori to
1831 macro_build ((char *) NULL
, counter
, ep
, "ori", "t,r,i", reg
, 0,
1832 (int) BFD_RELOC_LO16
);
1835 else if (((ep
->X_add_number
&~ (offsetT
) 0x7fffffff) == 0
1836 || ((ep
->X_add_number
&~ (offsetT
) 0x7fffffff)
1837 == ~ (offsetT
) 0x7fffffff))
1840 || sizeof (ep
->X_add_number
) > 4
1841 || (ep
->X_add_number
& 0x80000000) == 0))
1843 /* 32 bit values require an lui. */
1844 macro_build ((char *) NULL
, counter
, ep
, "lui", "t,u", reg
,
1845 (int) BFD_RELOC_HI16
);
1846 if ((ep
->X_add_number
& 0xffff) != 0)
1847 macro_build ((char *) NULL
, counter
, ep
, "ori", "t,r,i", reg
, reg
,
1848 (int) BFD_RELOC_LO16
);
1853 /* 32 bit value with high bit set being loaded into a 64 bit
1854 register. We can't use lui, because that would
1855 incorrectly set the 32 high bits. */
1856 generic_bignum
[3] = 0;
1857 generic_bignum
[2] = 0;
1858 generic_bignum
[1] = (ep
->X_add_number
>> 16) & 0xffff;
1859 generic_bignum
[0] = ep
->X_add_number
& 0xffff;
1861 tmp
.X_add_number
= 4;
1866 /* The value is larger than 32 bits. */
1870 as_bad ("Number larger than 32 bits");
1871 macro_build ((char *) NULL
, counter
, ep
, "addiu", "t,r,j", reg
, 0,
1872 (int) BFD_RELOC_LO16
);
1876 if (ep
->X_op
!= O_big
)
1880 hi32
.X_add_number
>>= shift
;
1881 hi32
.X_add_number
&= 0xffffffff;
1882 if ((hi32
.X_add_number
& 0x80000000) != 0)
1883 hi32
.X_add_number
|= ~ (offsetT
) 0xffffffff;
1885 lo32
.X_add_number
&= 0xffffffff;
1889 assert (ep
->X_add_number
> 2);
1890 if (ep
->X_add_number
== 3)
1891 generic_bignum
[3] = 0;
1892 else if (ep
->X_add_number
> 4)
1893 as_bad ("Number larger than 64 bits");
1894 lo32
.X_op
= O_constant
;
1895 lo32
.X_add_number
= generic_bignum
[0] + (generic_bignum
[1] << 16);
1896 hi32
.X_op
= O_constant
;
1897 hi32
.X_add_number
= generic_bignum
[2] + (generic_bignum
[3] << 16);
1900 if (hi32
.X_add_number
== 0)
1904 if (hi32
.X_add_number
== 0xffffffff)
1906 if ((lo32
.X_add_number
& 0xffff8000) == 0xffff8000)
1908 macro_build ((char *) NULL
, counter
, &lo32
, "addiu", "t,r,j", reg
, 0,
1909 (int) BFD_RELOC_LO16
);
1912 if (lo32
.X_add_number
& 0x80000000)
1914 macro_build ((char *) NULL
, counter
, &lo32
, "lui", "t,u", reg
,
1915 (int) BFD_RELOC_HI16
);
1916 macro_build ((char *) NULL
, counter
, &lo32
, "ori", "t,r,i", reg
, reg
,
1917 (int) BFD_RELOC_LO16
);
1921 load_register (counter
, reg
, &hi32
, 0);
1924 if ((lo32
.X_add_number
& 0xffff0000) == 0)
1928 macro_build ((char *) NULL
, counter
, NULL
, "dsll32", "d,w,<", reg
,
1937 if ((freg
== 0) && (lo32
.X_add_number
== 0xffffffff))
1939 macro_build ((char *) NULL
, counter
, &lo32
, "lui", "t,u", reg
,
1940 (int) BFD_RELOC_HI16
);
1941 macro_build ((char *) NULL
, counter
, NULL
, "dsrl32", "d,w,<", reg
,
1948 macro_build ((char *) NULL
, counter
, NULL
, "dsll", "d,w,<", reg
,
1953 mid16
.X_add_number
>>= 16;
1954 macro_build ((char *) NULL
, counter
, &mid16
, "ori", "t,r,i", reg
,
1955 freg
, (int) BFD_RELOC_LO16
);
1956 macro_build ((char *) NULL
, counter
, NULL
, "dsll", "d,w,<", reg
,
1960 if ((lo32
.X_add_number
& 0xffff) != 0)
1961 macro_build ((char *) NULL
, counter
, &lo32
, "ori", "t,r,i", reg
, freg
,
1962 (int) BFD_RELOC_LO16
);
1965 /* Load an address into a register. */
1968 load_address (counter
, reg
, ep
)
1975 if (ep
->X_op
!= O_constant
1976 && ep
->X_op
!= O_symbol
)
1978 as_bad ("expression too complex");
1979 ep
->X_op
= O_constant
;
1982 if (ep
->X_op
== O_constant
)
1984 load_register (counter
, reg
, ep
, 0);
1988 if (mips_pic
== NO_PIC
)
1990 /* If this is a reference to a GP relative symbol, we want
1991 addiu $reg,$gp,<sym> (BFD_RELOC_MIPS_GPREL)
1993 lui $reg,<sym> (BFD_RELOC_HI16_S)
1994 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
1995 If we have an addend, we always use the latter form. */
1996 if (ep
->X_add_number
!= 0 || nopic_need_relax (ep
->X_add_symbol
))
2001 macro_build ((char *) NULL
, counter
, ep
,
2002 mips_isa
< 3 ? "addiu" : "daddiu",
2003 "t,r,j", reg
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
2004 p
= frag_var (rs_machine_dependent
, 8, 0,
2005 RELAX_ENCODE (4, 8, 0, 4, 0, mips_warn_about_macros
),
2006 ep
->X_add_symbol
, (long) 0, (char *) NULL
);
2008 macro_build_lui (p
, counter
, ep
, reg
);
2011 macro_build (p
, counter
, ep
,
2012 mips_isa
< 3 ? "addiu" : "daddiu",
2013 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
2015 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
2019 /* If this is a reference to an external symbol, we want
2020 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
2022 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
2024 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
2025 If there is a constant, it must be added in after. */
2026 ex
.X_add_number
= ep
->X_add_number
;
2027 ep
->X_add_number
= 0;
2029 macro_build ((char *) NULL
, counter
, ep
,
2030 mips_isa
< 3 ? "lw" : "ld",
2031 "t,o(b)", reg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
2032 macro_build ((char *) NULL
, counter
, (expressionS
*) NULL
, "nop", "");
2033 p
= frag_var (rs_machine_dependent
, 4, 0,
2034 RELAX_ENCODE (0, 4, -8, 0, 0, mips_warn_about_macros
),
2035 ep
->X_add_symbol
, (long) 0, (char *) NULL
);
2036 macro_build (p
, counter
, ep
,
2037 mips_isa
< 3 ? "addiu" : "daddiu",
2038 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
2039 if (ex
.X_add_number
!= 0)
2041 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
2042 as_bad ("PIC code offset overflow (max 16 signed bits)");
2043 ex
.X_op
= O_constant
;
2044 macro_build ((char *) NULL
, counter
, &ex
,
2045 mips_isa
< 3 ? "addiu" : "daddiu",
2046 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
2049 else if (mips_pic
== SVR4_PIC
)
2054 /* This is the large GOT case. If this is a reference to an
2055 external symbol, we want
2056 lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
2058 lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16)
2059 Otherwise, for a reference to a local symbol, we want
2060 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
2062 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
2063 If there is a constant, it must be added in after. */
2064 ex
.X_add_number
= ep
->X_add_number
;
2065 ep
->X_add_number
= 0;
2066 if (reg_needs_delay (GP
))
2071 macro_build ((char *) NULL
, counter
, ep
, "lui", "t,u", reg
,
2072 (int) BFD_RELOC_MIPS_GOT_HI16
);
2073 macro_build ((char *) NULL
, counter
, (expressionS
*) NULL
,
2074 mips_isa
< 3 ? "addu" : "daddu",
2075 "d,v,t", reg
, reg
, GP
);
2076 macro_build ((char *) NULL
, counter
, ep
,
2077 mips_isa
< 3 ? "lw" : "ld",
2078 "t,o(b)", reg
, (int) BFD_RELOC_MIPS_GOT_LO16
, reg
);
2079 p
= frag_var (rs_machine_dependent
, 12 + off
, 0,
2080 RELAX_ENCODE (12, 12 + off
, off
, 8 + off
, 0,
2081 mips_warn_about_macros
),
2082 ep
->X_add_symbol
, (long) 0, (char *) NULL
);
2085 /* We need a nop before loading from $gp. This special
2086 check is required because the lui which starts the main
2087 instruction stream does not refer to $gp, and so will not
2088 insert the nop which may be required. */
2089 macro_build (p
, counter
, (expressionS
*) NULL
, "nop", "");
2092 macro_build (p
, counter
, ep
,
2093 mips_isa
< 3 ? "lw" : "ld",
2094 "t,o(b)", reg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
2096 macro_build (p
, counter
, (expressionS
*) NULL
, "nop", "");
2098 macro_build (p
, counter
, ep
,
2099 mips_isa
< 3 ? "addiu" : "daddiu",
2100 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
2101 if (ex
.X_add_number
!= 0)
2103 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
2104 as_bad ("PIC code offset overflow (max 16 signed bits)");
2105 ex
.X_op
= O_constant
;
2106 macro_build ((char *) NULL
, counter
, &ex
,
2107 mips_isa
< 3 ? "addiu" : "daddiu",
2108 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
2111 else if (mips_pic
== EMBEDDED_PIC
)
2114 addiu $reg,$gp,<sym> (BFD_RELOC_MIPS_GPREL)
2116 macro_build ((char *) NULL
, counter
, ep
,
2117 mips_isa
< 3 ? "addiu" : "daddiu",
2118 "t,r,j", reg
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
2126 * This routine implements the seemingly endless macro or synthesized
2127 * instructions and addressing modes in the mips assembly language. Many
2128 * of these macros are simple and are similar to each other. These could
2129 * probably be handled by some kind of table or grammer aproach instead of
2130 * this verbose method. Others are not simple macros but are more like
2131 * optimizing code generation.
2132 * One interesting optimization is when several store macros appear
2133 * consecutivly that would load AT with the upper half of the same address.
2134 * The ensuing load upper instructions are ommited. This implies some kind
2135 * of global optimization. We currently only optimize within a single macro.
2136 * For many of the load and store macros if the address is specified as a
2137 * constant expression in the first 64k of memory (ie ld $2,0x4000c) we
2138 * first load register 'at' with zero and use it as the base register. The
2139 * mips assembler simply uses register $zero. Just one tiny optimization
2144 struct mips_cl_insn
*ip
;
2146 register int treg
, sreg
, dreg
, breg
;
2161 bfd_reloc_code_real_type r
;
2163 int hold_mips_optimize
;
2165 treg
= (ip
->insn_opcode
>> 16) & 0x1f;
2166 dreg
= (ip
->insn_opcode
>> 11) & 0x1f;
2167 sreg
= breg
= (ip
->insn_opcode
>> 21) & 0x1f;
2168 mask
= ip
->insn_mo
->mask
;
2170 expr1
.X_op
= O_constant
;
2171 expr1
.X_op_symbol
= NULL
;
2172 expr1
.X_add_symbol
= NULL
;
2173 expr1
.X_add_number
= 1;
2185 mips_emit_delays ();
2187 mips_any_noreorder
= 1;
2189 expr1
.X_add_number
= 8;
2190 macro_build ((char *) NULL
, &icnt
, &expr1
, "bgez", "s,p", sreg
);
2192 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
2194 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
, sreg
, 0);
2195 macro_build ((char *) NULL
, &icnt
, NULL
,
2196 dbl
? "dsub" : "sub",
2197 "d,v,t", dreg
, 0, sreg
);
2220 if (imm_expr
.X_add_number
>= -0x8000 && imm_expr
.X_add_number
< 0x8000)
2222 macro_build ((char *) NULL
, &icnt
, &imm_expr
, s
, "t,r,j", treg
, sreg
,
2223 (int) BFD_RELOC_LO16
);
2226 load_register (&icnt
, AT
, &imm_expr
, dbl
);
2227 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "d,v,t", treg
, sreg
, AT
);
2246 if (imm_expr
.X_add_number
>= 0 && imm_expr
.X_add_number
< 0x10000)
2248 if (mask
!= M_NOR_I
)
2249 macro_build ((char *) NULL
, &icnt
, &imm_expr
, s
, "t,r,i", treg
,
2250 sreg
, (int) BFD_RELOC_LO16
);
2253 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "ori", "t,r,i",
2254 treg
, sreg
, (int) BFD_RELOC_LO16
);
2255 macro_build ((char *) NULL
, &icnt
, NULL
, "nor", "d,v,t",
2261 load_register (&icnt
, AT
, &imm_expr
, 0);
2262 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "d,v,t", treg
, sreg
, AT
);
2279 if (imm_expr
.X_add_number
== 0)
2281 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "s,t,p", sreg
,
2285 load_register (&icnt
, AT
, &imm_expr
, 0);
2286 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "s,t,p", sreg
, AT
);
2294 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2295 likely
? "bgezl" : "bgez",
2301 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2302 likely
? "blezl" : "blez",
2306 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", AT
, sreg
, treg
);
2307 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2308 likely
? "beql" : "beq",
2315 /* check for > max integer */
2316 maxnum
= 0x7fffffff;
2324 if (imm_expr
.X_add_number
>= maxnum
2325 && (mips_isa
< 3 || sizeof (maxnum
) > 4))
2328 /* result is always false */
2331 as_warn ("Branch %s is always false (nop)", ip
->insn_mo
->name
);
2332 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
2336 as_warn ("Branch likely %s is always false", ip
->insn_mo
->name
);
2337 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "bnel",
2342 imm_expr
.X_add_number
++;
2346 if (mask
== M_BGEL_I
)
2348 if (imm_expr
.X_add_number
== 0)
2350 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2351 likely
? "bgezl" : "bgez",
2355 if (imm_expr
.X_add_number
== 1)
2357 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2358 likely
? "bgtzl" : "bgtz",
2362 maxnum
= 0x7fffffff;
2370 maxnum
= - maxnum
- 1;
2371 if (imm_expr
.X_add_number
<= maxnum
2372 && (mips_isa
< 3 || sizeof (maxnum
) > 4))
2375 /* result is always true */
2376 as_warn ("Branch %s is always true", ip
->insn_mo
->name
);
2377 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "b", "p");
2380 set_at (&icnt
, sreg
, 0);
2381 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2382 likely
? "beql" : "beq",
2393 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2394 likely
? "beql" : "beq",
2398 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", AT
, sreg
,
2400 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2401 likely
? "beql" : "beq",
2408 if (sreg
== 0 || imm_expr
.X_add_number
== -1)
2410 imm_expr
.X_add_number
++;
2414 if (mask
== M_BGEUL_I
)
2416 if (imm_expr
.X_add_number
== 0)
2418 if (imm_expr
.X_add_number
== 1)
2420 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2421 likely
? "bnel" : "bne",
2425 set_at (&icnt
, sreg
, 1);
2426 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2427 likely
? "beql" : "beq",
2436 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2437 likely
? "bgtzl" : "bgtz",
2443 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2444 likely
? "bltzl" : "bltz",
2448 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", AT
, treg
, sreg
);
2449 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2450 likely
? "bnel" : "bne",
2459 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2460 likely
? "bnel" : "bne",
2466 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", AT
, treg
,
2468 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2469 likely
? "bnel" : "bne",
2478 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2479 likely
? "blezl" : "blez",
2485 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2486 likely
? "bgezl" : "bgez",
2490 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", AT
, treg
, sreg
);
2491 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2492 likely
? "beql" : "beq",
2499 maxnum
= 0x7fffffff;
2507 if (imm_expr
.X_add_number
>= maxnum
2508 && (mips_isa
< 3 || sizeof (maxnum
) > 4))
2510 imm_expr
.X_add_number
++;
2514 if (mask
== M_BLTL_I
)
2516 if (imm_expr
.X_add_number
== 0)
2518 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2519 likely
? "bltzl" : "bltz",
2523 if (imm_expr
.X_add_number
== 1)
2525 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2526 likely
? "blezl" : "blez",
2530 set_at (&icnt
, sreg
, 0);
2531 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2532 likely
? "bnel" : "bne",
2541 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2542 likely
? "beql" : "beq",
2548 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", AT
, treg
,
2550 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2551 likely
? "beql" : "beq",
2558 if (sreg
== 0 || imm_expr
.X_add_number
== -1)
2560 imm_expr
.X_add_number
++;
2564 if (mask
== M_BLTUL_I
)
2566 if (imm_expr
.X_add_number
== 0)
2568 if (imm_expr
.X_add_number
== 1)
2570 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2571 likely
? "beql" : "beq",
2575 set_at (&icnt
, sreg
, 1);
2576 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2577 likely
? "bnel" : "bne",
2586 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2587 likely
? "bltzl" : "bltz",
2593 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2594 likely
? "bgtzl" : "bgtz",
2598 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", AT
, sreg
, treg
);
2599 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2600 likely
? "bnel" : "bne",
2611 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2612 likely
? "bnel" : "bne",
2616 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", AT
, sreg
,
2618 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2619 likely
? "bnel" : "bne",
2635 as_warn ("Divide by zero.");
2637 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", 0, 0);
2639 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 7);
2643 mips_emit_delays ();
2645 mips_any_noreorder
= 1;
2646 macro_build ((char *) NULL
, &icnt
, NULL
,
2647 dbl
? "ddiv" : "div",
2648 "z,s,t", sreg
, treg
);
2650 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", treg
, 0);
2653 expr1
.X_add_number
= 8;
2654 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", treg
, 0);
2655 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
2656 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 7);
2658 expr1
.X_add_number
= -1;
2659 macro_build ((char *) NULL
, &icnt
, &expr1
,
2660 dbl
? "daddiu" : "addiu",
2661 "t,r,j", AT
, 0, (int) BFD_RELOC_LO16
);
2662 expr1
.X_add_number
= mips_trap
? (dbl
? 12 : 8) : (dbl
? 20 : 16);
2663 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", treg
, AT
);
2666 expr1
.X_add_number
= 1;
2667 macro_build ((char *) NULL
, &icnt
, &expr1
, "daddiu", "t,r,j", AT
, 0,
2668 (int) BFD_RELOC_LO16
);
2669 macro_build ((char *) NULL
, &icnt
, NULL
, "dsll32", "d,w,<", AT
, AT
,
2674 expr1
.X_add_number
= 0x80000000;
2675 macro_build ((char *) NULL
, &icnt
, &expr1
, "lui", "t,u", AT
,
2676 (int) BFD_RELOC_HI16
);
2679 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", sreg
, AT
);
2682 expr1
.X_add_number
= 8;
2683 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", sreg
, AT
);
2684 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
2685 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 6);
2688 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d", dreg
);
2727 if (imm_expr
.X_add_number
== 0)
2729 as_warn ("Divide by zero.");
2731 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", 0, 0);
2733 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 7);
2736 if (imm_expr
.X_add_number
== 1)
2738 if (strcmp (s2
, "mflo") == 0)
2739 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
,
2742 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
, 0);
2745 if (imm_expr
.X_add_number
== -1
2746 && s
[strlen (s
) - 1] != 'u')
2748 if (strcmp (s2
, "mflo") == 0)
2751 macro_build ((char *) NULL
, &icnt
, NULL
, "dneg", "d,w", dreg
,
2754 macro_build ((char *) NULL
, &icnt
, NULL
, "neg", "d,w", dreg
,
2758 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
, 0);
2762 load_register (&icnt
, AT
, &imm_expr
, dbl
);
2763 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "z,s,t", sreg
, AT
);
2764 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "d", dreg
);
2783 mips_emit_delays ();
2785 mips_any_noreorder
= 1;
2786 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "z,s,t", sreg
, treg
);
2788 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", treg
, 0);
2791 expr1
.X_add_number
= 8;
2792 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", treg
, 0);
2793 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
2794 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 7);
2797 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "d", dreg
);
2803 /* Load the address of a symbol into a register. If breg is not
2804 zero, we then add a base register to it. */
2806 /* When generating embedded PIC code, we permit expressions of
2809 where bar is an address in the .text section. These are used
2810 when getting the addresses of functions. We don't permit
2811 X_add_number to be non-zero, because if the symbol is
2812 external the relaxing code needs to know that any addend is
2813 purely the offset to X_op_symbol. */
2814 if (mips_pic
== EMBEDDED_PIC
2815 && offset_expr
.X_op
== O_subtract
2816 && now_seg
== text_section
2817 && (offset_expr
.X_op_symbol
->sy_value
.X_op
== O_constant
2818 ? S_GET_SEGMENT (offset_expr
.X_op_symbol
) == text_section
2819 : (offset_expr
.X_op_symbol
->sy_value
.X_op
== O_symbol
2820 && (S_GET_SEGMENT (offset_expr
.X_op_symbol
2821 ->sy_value
.X_add_symbol
)
2824 && offset_expr
.X_add_number
== 0)
2826 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
2827 treg
, (int) BFD_RELOC_PCREL_HI16_S
);
2828 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2829 mips_isa
< 3 ? "addiu" : "daddiu",
2830 "t,r,j", treg
, treg
, (int) BFD_RELOC_PCREL_LO16
);
2834 if (offset_expr
.X_op
!= O_symbol
2835 && offset_expr
.X_op
!= O_constant
)
2837 as_bad ("expression too complex");
2838 offset_expr
.X_op
= O_constant
;
2852 if (offset_expr
.X_op
== O_constant
)
2853 load_register (&icnt
, tempreg
, &offset_expr
, dbl
);
2854 else if (mips_pic
== NO_PIC
)
2856 /* If this is a reference to an GP relative symbol, we want
2857 addiu $tempreg,$gp,<sym> (BFD_RELOC_MIPS_GPREL)
2859 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
2860 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
2861 If we have a constant, we need two instructions anyhow,
2862 so we may as well always use the latter form. */
2863 if (offset_expr
.X_add_number
!= 0
2864 || nopic_need_relax (offset_expr
.X_add_symbol
))
2869 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2870 mips_isa
< 3 ? "addiu" : "daddiu",
2871 "t,r,j", tempreg
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
2872 p
= frag_var (rs_machine_dependent
, 8, 0,
2873 RELAX_ENCODE (4, 8, 0, 4, 0,
2874 mips_warn_about_macros
),
2875 offset_expr
.X_add_symbol
, (long) 0,
2878 macro_build_lui (p
, &icnt
, &offset_expr
, tempreg
);
2881 macro_build (p
, &icnt
, &offset_expr
,
2882 mips_isa
< 3 ? "addiu" : "daddiu",
2883 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
2885 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
2887 /* If this is a reference to an external symbol, and there
2888 is no constant, we want
2889 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
2890 For a local symbol, we want
2891 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
2893 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
2895 If we have a small constant, and this is a reference to
2896 an external symbol, we want
2897 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
2899 addiu $tempreg,$tempreg,<constant>
2900 For a local symbol, we want the same instruction
2901 sequence, but we output a BFD_RELOC_LO16 reloc on the
2904 If we have a large constant, and this is a reference to
2905 an external symbol, we want
2906 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
2907 lui $at,<hiconstant>
2908 addiu $at,$at,<loconstant>
2909 addu $tempreg,$tempreg,$at
2910 For a local symbol, we want the same instruction
2911 sequence, but we output a BFD_RELOC_LO16 reloc on the
2912 addiu instruction. */
2913 expr1
.X_add_number
= offset_expr
.X_add_number
;
2914 offset_expr
.X_add_number
= 0;
2916 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2918 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
2919 if (expr1
.X_add_number
== 0)
2927 /* We're going to put in an addu instruction using
2928 tempreg, so we may as well insert the nop right
2930 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
2934 p
= frag_var (rs_machine_dependent
, 8 - off
, 0,
2935 RELAX_ENCODE (0, 8 - off
, -4 - off
, 4 - off
, 0,
2937 ? mips_warn_about_macros
2939 offset_expr
.X_add_symbol
, (long) 0,
2943 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
2946 macro_build (p
, &icnt
, &expr1
,
2947 mips_isa
< 3 ? "addiu" : "daddiu",
2948 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
2949 /* FIXME: If breg == 0, and the next instruction uses
2950 $tempreg, then if this variant case is used an extra
2951 nop will be generated. */
2953 else if (expr1
.X_add_number
>= -0x8000
2954 && expr1
.X_add_number
< 0x8000)
2956 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
2958 macro_build ((char *) NULL
, &icnt
, &expr1
,
2959 mips_isa
< 3 ? "addiu" : "daddiu",
2960 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
2961 (void) frag_var (rs_machine_dependent
, 0, 0,
2962 RELAX_ENCODE (0, 0, -12, -4, 0, 0),
2963 offset_expr
.X_add_symbol
, (long) 0,
2970 /* If we are going to add in a base register, and the
2971 target register and the base register are the same,
2972 then we are using AT as a temporary register. Since
2973 we want to load the constant into AT, we add our
2974 current AT (from the global offset table) and the
2975 register into the register now, and pretend we were
2976 not using a base register. */
2981 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
2983 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
2984 mips_isa
< 3 ? "addu" : "daddu",
2985 "d,v,t", treg
, AT
, breg
);
2991 /* Set mips_optimize around the lui instruction to avoid
2992 inserting an unnecessary nop after the lw. */
2993 hold_mips_optimize
= mips_optimize
;
2995 macro_build_lui ((char *) NULL
, &icnt
, &expr1
, AT
);
2996 mips_optimize
= hold_mips_optimize
;
2998 macro_build ((char *) NULL
, &icnt
, &expr1
,
2999 mips_isa
< 3 ? "addiu" : "daddiu",
3000 "t,r,j", AT
, AT
, (int) BFD_RELOC_LO16
);
3001 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3002 mips_isa
< 3 ? "addu" : "daddu",
3003 "d,v,t", tempreg
, tempreg
, AT
);
3004 (void) frag_var (rs_machine_dependent
, 0, 0,
3005 RELAX_ENCODE (0, 0, -16 + off1
, -8, 0, 0),
3006 offset_expr
.X_add_symbol
, (long) 0,
3011 else if (mips_pic
== SVR4_PIC
)
3015 /* This is the large GOT case. If this is a reference to an
3016 external symbol, and there is no constant, we want
3017 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
3018 addu $tempreg,$tempreg,$gp
3019 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
3020 For a local symbol, we want
3021 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3023 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
3025 If we have a small constant, and this is a reference to
3026 an external symbol, we want
3027 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
3028 addu $tempreg,$tempreg,$gp
3029 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
3031 addiu $tempreg,$tempreg,<constant>
3032 For a local symbol, we want
3033 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3035 addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16)
3037 If we have a large constant, and this is a reference to
3038 an external symbol, we want
3039 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
3040 addu $tempreg,$tempreg,$gp
3041 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
3042 lui $at,<hiconstant>
3043 addiu $at,$at,<loconstant>
3044 addu $tempreg,$tempreg,$at
3045 For a local symbol, we want
3046 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3047 lui $at,<hiconstant>
3048 addiu $at,$at,<loconstant> (BFD_RELOC_LO16)
3049 addu $tempreg,$tempreg,$at
3051 expr1
.X_add_number
= offset_expr
.X_add_number
;
3052 offset_expr
.X_add_number
= 0;
3054 if (reg_needs_delay (GP
))
3058 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
3059 tempreg
, (int) BFD_RELOC_MIPS_GOT_HI16
);
3060 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3061 mips_isa
< 3 ? "addu" : "daddu",
3062 "d,v,t", tempreg
, tempreg
, GP
);
3063 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3065 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT_LO16
,
3067 if (expr1
.X_add_number
== 0)
3075 /* We're going to put in an addu instruction using
3076 tempreg, so we may as well insert the nop right
3078 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3083 p
= frag_var (rs_machine_dependent
, 12 + gpdel
, 0,
3084 RELAX_ENCODE (12 + off
, 12 + gpdel
, gpdel
,
3087 ? mips_warn_about_macros
3089 offset_expr
.X_add_symbol
, (long) 0,
3092 else if (expr1
.X_add_number
>= -0x8000
3093 && expr1
.X_add_number
< 0x8000)
3095 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3097 macro_build ((char *) NULL
, &icnt
, &expr1
,
3098 mips_isa
< 3 ? "addiu" : "daddiu",
3099 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
3101 p
= frag_var (rs_machine_dependent
, 12 + gpdel
, 0,
3102 RELAX_ENCODE (20, 12 + gpdel
, gpdel
, 8 + gpdel
, 0,
3104 ? mips_warn_about_macros
3106 offset_expr
.X_add_symbol
, (long) 0,
3113 /* If we are going to add in a base register, and the
3114 target register and the base register are the same,
3115 then we are using AT as a temporary register. Since
3116 we want to load the constant into AT, we add our
3117 current AT (from the global offset table) and the
3118 register into the register now, and pretend we were
3119 not using a base register. */
3127 assert (tempreg
== AT
);
3128 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3130 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3131 mips_isa
< 3 ? "addu" : "daddu",
3132 "d,v,t", treg
, AT
, breg
);
3137 /* Set mips_optimize around the lui instruction to avoid
3138 inserting an unnecessary nop after the lw. */
3139 hold_mips_optimize
= mips_optimize
;
3141 macro_build_lui ((char *) NULL
, &icnt
, &expr1
, AT
);
3142 mips_optimize
= hold_mips_optimize
;
3144 macro_build ((char *) NULL
, &icnt
, &expr1
,
3145 mips_isa
< 3 ? "addiu" : "daddiu",
3146 "t,r,j", AT
, AT
, (int) BFD_RELOC_LO16
);
3147 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3148 mips_isa
< 3 ? "addu" : "daddu",
3149 "d,v,t", dreg
, dreg
, AT
);
3151 p
= frag_var (rs_machine_dependent
, 16 + gpdel
+ adj
, 0,
3152 RELAX_ENCODE (24 + adj
, 16 + gpdel
+ adj
, gpdel
,
3155 ? mips_warn_about_macros
3157 offset_expr
.X_add_symbol
, (long) 0,
3165 /* This is needed because this instruction uses $gp, but
3166 the first instruction on the main stream does not. */
3167 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
3170 macro_build (p
, &icnt
, &offset_expr
,
3172 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
3174 if (expr1
.X_add_number
>= -0x8000
3175 && expr1
.X_add_number
< 0x8000)
3177 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
3179 macro_build (p
, &icnt
, &expr1
,
3180 mips_isa
< 3 ? "addiu" : "daddiu",
3181 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
3182 /* FIXME: If add_number is 0, and there was no base
3183 register, the external symbol case ended with a load,
3184 so if the symbol turns out to not be external, and
3185 the next instruction uses tempreg, an unnecessary nop
3186 will be inserted. */
3192 /* We must add in the base register now, as in the
3193 external symbol case. */
3194 assert (tempreg
== AT
);
3195 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
3197 macro_build (p
, &icnt
, (expressionS
*) NULL
,
3198 mips_isa
< 3 ? "addu" : "daddu",
3199 "d,v,t", treg
, AT
, breg
);
3202 /* We set breg to 0 because we have arranged to add
3203 it in in both cases. */
3207 macro_build_lui (p
, &icnt
, &expr1
, AT
);
3209 macro_build (p
, &icnt
, &expr1
,
3210 mips_isa
< 3 ? "addiu" : "daddiu",
3211 "t,r,j", AT
, AT
, (int) BFD_RELOC_LO16
);
3213 macro_build (p
, &icnt
, (expressionS
*) NULL
,
3214 mips_isa
< 3 ? "addu" : "daddu",
3215 "d,v,t", tempreg
, tempreg
, AT
);
3219 else if (mips_pic
== EMBEDDED_PIC
)
3222 addiu $tempreg,$gp,<sym> (BFD_RELOC_MIPS_GPREL)
3224 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3225 mips_isa
< 3 ? "addiu" : "daddiu",
3226 "t,r,j", tempreg
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
3232 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3233 mips_isa
< 3 ? "addu" : "daddu",
3234 "d,v,t", treg
, tempreg
, breg
);
3242 /* The j instruction may not be used in PIC code, since it
3243 requires an absolute address. We convert it to a b
3245 if (mips_pic
== NO_PIC
)
3246 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "j", "a");
3248 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "b", "p");
3251 /* The jal instructions must be handled as macros because when
3252 generating PIC code they expand to multi-instruction
3253 sequences. Normally they are simple instructions. */
3258 if (mips_pic
== NO_PIC
3259 || mips_pic
== EMBEDDED_PIC
)
3260 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "jalr",
3262 else if (mips_pic
== SVR4_PIC
)
3264 if (sreg
!= PIC_CALL_REG
)
3265 as_warn ("MIPS PIC call to register other than $25");
3267 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "jalr",
3269 if (mips_cprestore_offset
< 0)
3270 as_warn ("No .cprestore pseudo-op used in PIC code");
3273 expr1
.X_add_number
= mips_cprestore_offset
;
3274 macro_build ((char *) NULL
, &icnt
, &expr1
,
3275 mips_isa
< 3 ? "lw" : "ld",
3276 "t,o(b)", GP
, (int) BFD_RELOC_LO16
, mips_frame_reg
);
3285 if (mips_pic
== NO_PIC
)
3286 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "jal", "a");
3287 else if (mips_pic
== SVR4_PIC
)
3289 /* If this is a reference to an external symbol, and we are
3290 using a small GOT, we want
3291 lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
3295 lw $gp,cprestore($sp)
3296 The cprestore value is set using the .cprestore
3297 pseudo-op. If we are using a big GOT, we want
3298 lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16)
3300 lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16)
3304 lw $gp,cprestore($sp)
3305 If the symbol is not external, we want
3306 lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3308 addiu $25,$25,<sym> (BFD_RELOC_LO16)
3311 lw $gp,cprestore($sp) */
3315 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3316 mips_isa
< 3 ? "lw" : "ld",
3317 "t,o(b)", PIC_CALL_REG
,
3318 (int) BFD_RELOC_MIPS_CALL16
, GP
);
3319 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3321 p
= frag_var (rs_machine_dependent
, 4, 0,
3322 RELAX_ENCODE (0, 4, -8, 0, 0, 0),
3323 offset_expr
.X_add_symbol
, (long) 0, (char *) NULL
);
3329 if (reg_needs_delay (GP
))
3333 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
3334 PIC_CALL_REG
, (int) BFD_RELOC_MIPS_CALL_HI16
);
3335 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3336 mips_isa
< 3 ? "addu" : "daddu",
3337 "d,v,t", PIC_CALL_REG
, PIC_CALL_REG
, GP
);
3338 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3339 mips_isa
< 3 ? "lw" : "ld",
3340 "t,o(b)", PIC_CALL_REG
,
3341 (int) BFD_RELOC_MIPS_CALL_LO16
, PIC_CALL_REG
);
3342 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3344 p
= frag_var (rs_machine_dependent
, 12 + gpdel
, 0,
3345 RELAX_ENCODE (16, 12 + gpdel
, gpdel
, 8 + gpdel
,
3347 offset_expr
.X_add_symbol
, (long) 0, (char *) NULL
);
3350 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
3353 macro_build (p
, &icnt
, &offset_expr
,
3354 mips_isa
< 3 ? "lw" : "ld",
3355 "t,o(b)", PIC_CALL_REG
,
3356 (int) BFD_RELOC_MIPS_GOT16
, GP
);
3358 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
3361 macro_build (p
, &icnt
, &offset_expr
,
3362 mips_isa
< 3 ? "addiu" : "daddiu",
3363 "t,r,j", PIC_CALL_REG
, PIC_CALL_REG
,
3364 (int) BFD_RELOC_LO16
);
3365 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3366 "jalr", "s", PIC_CALL_REG
);
3367 if (mips_cprestore_offset
< 0)
3368 as_warn ("No .cprestore pseudo-op used in PIC code");
3372 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3374 expr1
.X_add_number
= mips_cprestore_offset
;
3375 macro_build ((char *) NULL
, &icnt
, &expr1
,
3376 mips_isa
< 3 ? "lw" : "ld",
3377 "t,o(b)", GP
, (int) BFD_RELOC_LO16
,
3381 else if (mips_pic
== EMBEDDED_PIC
)
3383 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "bal", "p");
3384 /* The linker may expand the call to a longer sequence which
3385 uses $at, so we must break rather than return. */
3461 if (breg
== treg
|| coproc
|| lr
)
3530 if (mask
== M_LWC1_AB
3531 || mask
== M_SWC1_AB
3532 || mask
== M_LDC1_AB
3533 || mask
== M_SDC1_AB
3542 if (offset_expr
.X_op
!= O_constant
3543 && offset_expr
.X_op
!= O_symbol
)
3545 as_bad ("expression too complex");
3546 offset_expr
.X_op
= O_constant
;
3549 /* A constant expression in PIC code can be handled just as it
3550 is in non PIC code. */
3551 if (mips_pic
== NO_PIC
3552 || offset_expr
.X_op
== O_constant
)
3554 /* If this is a reference to a GP relative symbol, and there
3555 is no base register, we want
3556 <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL)
3557 Otherwise, if there is no base register, we want
3558 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
3559 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
3560 If we have a constant, we need two instructions anyhow,
3561 so we always use the latter form.
3563 If we have a base register, and this is a reference to a
3564 GP relative symbol, we want
3565 addu $tempreg,$breg,$gp
3566 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GPREL)
3568 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
3569 addu $tempreg,$tempreg,$breg
3570 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
3571 With a constant we always use the latter case. */
3574 if (offset_expr
.X_add_number
!= 0
3575 || nopic_need_relax (offset_expr
.X_add_symbol
))
3580 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
3581 treg
, (int) BFD_RELOC_MIPS_GPREL
, GP
);
3582 p
= frag_var (rs_machine_dependent
, 8, 0,
3583 RELAX_ENCODE (4, 8, 0, 4, 0,
3584 (mips_warn_about_macros
3585 || (used_at
&& mips_noat
))),
3586 offset_expr
.X_add_symbol
, (long) 0,
3590 macro_build_lui (p
, &icnt
, &offset_expr
, tempreg
);
3593 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
, treg
,
3594 (int) BFD_RELOC_LO16
, tempreg
);
3598 if (offset_expr
.X_add_number
!= 0
3599 || nopic_need_relax (offset_expr
.X_add_symbol
))
3604 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3605 mips_isa
< 3 ? "addu" : "daddu",
3606 "d,v,t", tempreg
, breg
, GP
);
3607 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
3608 treg
, (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
3609 p
= frag_var (rs_machine_dependent
, 12, 0,
3610 RELAX_ENCODE (8, 12, 0, 8, 0, 0),
3611 offset_expr
.X_add_symbol
, (long) 0,
3614 macro_build_lui (p
, &icnt
, &offset_expr
, tempreg
);
3617 macro_build (p
, &icnt
, (expressionS
*) NULL
,
3618 mips_isa
< 3 ? "addu" : "daddu",
3619 "d,v,t", tempreg
, tempreg
, breg
);
3622 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
, treg
,
3623 (int) BFD_RELOC_LO16
, tempreg
);
3626 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
3628 /* If this is a reference to an external symbol, we want
3629 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3631 <op> $treg,0($tempreg)
3633 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3635 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
3636 <op> $treg,0($tempreg)
3637 If there is a base register, we add it to $tempreg before
3638 the <op>. If there is a constant, we stick it in the
3639 <op> instruction. We don't handle constants larger than
3640 16 bits, because we have no way to load the upper 16 bits
3641 (actually, we could handle them for the subset of cases
3642 in which we are not using $at). */
3643 assert (offset_expr
.X_op
== O_symbol
);
3644 expr1
.X_add_number
= offset_expr
.X_add_number
;
3645 offset_expr
.X_add_number
= 0;
3646 if (expr1
.X_add_number
< -0x8000
3647 || expr1
.X_add_number
>= 0x8000)
3648 as_bad ("PIC code offset overflow (max 16 signed bits)");
3650 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3651 mips_isa
< 3 ? "lw" : "ld",
3652 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
3653 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
3654 p
= frag_var (rs_machine_dependent
, 4, 0,
3655 RELAX_ENCODE (0, 4, -8, 0, 0, 0),
3656 offset_expr
.X_add_symbol
, (long) 0,
3658 macro_build (p
, &icnt
, &offset_expr
,
3659 mips_isa
< 3 ? "addiu" : "daddiu",
3660 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
3662 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3663 mips_isa
< 3 ? "addu" : "daddu",
3664 "d,v,t", tempreg
, tempreg
, breg
);
3665 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
, treg
,
3666 (int) BFD_RELOC_LO16
, tempreg
);
3668 else if (mips_pic
== SVR4_PIC
)
3672 /* If this is a reference to an external symbol, we want
3673 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
3674 addu $tempreg,$tempreg,$gp
3675 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
3676 <op> $treg,0($tempreg)
3678 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3680 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
3681 <op> $treg,0($tempreg)
3682 If there is a base register, we add it to $tempreg before
3683 the <op>. If there is a constant, we stick it in the
3684 <op> instruction. We don't handle constants larger than
3685 16 bits, because we have no way to load the upper 16 bits
3686 (actually, we could handle them for the subset of cases
3687 in which we are not using $at). */
3688 assert (offset_expr
.X_op
== O_symbol
);
3689 expr1
.X_add_number
= offset_expr
.X_add_number
;
3690 offset_expr
.X_add_number
= 0;
3691 if (expr1
.X_add_number
< -0x8000
3692 || expr1
.X_add_number
>= 0x8000)
3693 as_bad ("PIC code offset overflow (max 16 signed bits)");
3694 if (reg_needs_delay (GP
))
3699 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
3700 tempreg
, (int) BFD_RELOC_MIPS_GOT_HI16
);
3701 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3702 mips_isa
< 3 ? "addu" : "daddu",
3703 "d,v,t", tempreg
, tempreg
, GP
);
3704 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3705 mips_isa
< 3 ? "lw" : "ld",
3706 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT_LO16
,
3708 p
= frag_var (rs_machine_dependent
, 12 + gpdel
, 0,
3709 RELAX_ENCODE (12, 12 + gpdel
, gpdel
, 8 + gpdel
, 0, 0),
3710 offset_expr
.X_add_symbol
, (long) 0, (char *) NULL
);
3713 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
3716 macro_build (p
, &icnt
, &offset_expr
,
3717 mips_isa
< 3 ? "lw" : "ld",
3718 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
3720 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
3722 macro_build (p
, &icnt
, &offset_expr
,
3723 mips_isa
< 3 ? "addiu" : "daddiu",
3724 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
3726 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3727 mips_isa
< 3 ? "addu" : "daddu",
3728 "d,v,t", tempreg
, tempreg
, breg
);
3729 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
, treg
,
3730 (int) BFD_RELOC_LO16
, tempreg
);
3732 else if (mips_pic
== EMBEDDED_PIC
)
3734 /* If there is no base register, we want
3735 <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL)
3736 If there is a base register, we want
3737 addu $tempreg,$breg,$gp
3738 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GPREL)
3740 assert (offset_expr
.X_op
== O_symbol
);
3743 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
3744 treg
, (int) BFD_RELOC_MIPS_GPREL
, GP
);
3749 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3750 mips_isa
< 3 ? "addu" : "daddu",
3751 "d,v,t", tempreg
, breg
, GP
);
3752 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
3753 treg
, (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
3766 load_register (&icnt
, treg
, &imm_expr
, 0);
3770 load_register (&icnt
, treg
, &imm_expr
, 1);
3774 if (imm_expr
.X_op
== O_constant
)
3776 load_register (&icnt
, AT
, &imm_expr
, 0);
3777 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3778 "mtc1", "t,G", AT
, treg
);
3783 assert (offset_expr
.X_op
== O_symbol
3784 && strcmp (segment_name (S_GET_SEGMENT
3785 (offset_expr
.X_add_symbol
)),
3787 && offset_expr
.X_add_number
== 0);
3788 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lwc1", "T,o(b)",
3789 treg
, (int) BFD_RELOC_MIPS_LITERAL
, GP
);
3794 /* We know that sym is in the .rdata section. First we get the
3795 upper 16 bits of the address. */
3796 if (mips_pic
== NO_PIC
)
3798 /* FIXME: This won't work for a 64 bit address. */
3799 macro_build_lui ((char *) NULL
, &icnt
, &offset_expr
, AT
);
3801 else if (mips_pic
== SVR4_PIC
)
3803 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3804 mips_isa
< 3 ? "lw" : "ld",
3805 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
3807 else if (mips_pic
== EMBEDDED_PIC
)
3809 /* For embedded PIC we pick up the entire address off $gp in
3810 a single instruction. */
3811 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3812 mips_isa
< 3 ? "addiu" : "daddiu",
3813 "t,r,j", AT
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
3814 offset_expr
.X_op
= O_constant
;
3815 offset_expr
.X_add_number
= 0;
3820 /* Now we load the register(s). */
3822 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "ld", "t,o(b)",
3823 treg
, (int) BFD_RELOC_LO16
, AT
);
3826 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lw", "t,o(b)",
3827 treg
, (int) BFD_RELOC_LO16
, AT
);
3830 /* FIXME: How in the world do we deal with the possible
3832 offset_expr
.X_add_number
+= 4;
3833 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lw", "t,o(b)",
3834 treg
+ 1, (int) BFD_RELOC_LO16
, AT
);
3838 /* To avoid confusion in tc_gen_reloc, we must ensure that this
3839 does not become a variant frag. */
3840 frag_wane (frag_now
);
3846 assert (offset_expr
.X_op
== O_symbol
3847 && offset_expr
.X_add_number
== 0);
3848 s
= segment_name (S_GET_SEGMENT (offset_expr
.X_add_symbol
));
3849 if (strcmp (s
, ".lit8") == 0)
3853 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "ldc1",
3854 "T,o(b)", treg
, (int) BFD_RELOC_MIPS_LITERAL
, GP
);
3858 r
= BFD_RELOC_MIPS_LITERAL
;
3863 assert (strcmp (s
, RDATA_SECTION_NAME
) == 0);
3864 if (mips_pic
== SVR4_PIC
)
3865 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3866 mips_isa
< 3 ? "lw" : "ld",
3867 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
3870 /* FIXME: This won't work for a 64 bit address. */
3871 macro_build_lui ((char *) NULL
, &icnt
, &offset_expr
, AT
);
3876 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "ldc1",
3877 "T,o(b)", treg
, (int) BFD_RELOC_LO16
, AT
);
3879 /* To avoid confusion in tc_gen_reloc, we must ensure
3880 that this does not become a variant frag. */
3881 frag_wane (frag_now
);
3892 /* Even on a big endian machine $fn comes before $fn+1. We have
3893 to adjust when loading from memory. */
3896 assert (mips_isa
< 2);
3897 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lwc1", "T,o(b)",
3898 byte_order
== LITTLE_ENDIAN
? treg
: treg
+ 1,
3900 /* FIXME: A possible overflow which I don't know how to deal
3902 offset_expr
.X_add_number
+= 4;
3903 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lwc1", "T,o(b)",
3904 byte_order
== LITTLE_ENDIAN
? treg
+ 1 : treg
,
3907 /* To avoid confusion in tc_gen_reloc, we must ensure that this
3908 does not become a variant frag. */
3909 frag_wane (frag_now
);
3918 * The MIPS assembler seems to check for X_add_number not
3919 * being double aligned and generating:
3922 * addiu at,at,%lo(foo+1)
3925 * But, the resulting address is the same after relocation so why
3926 * generate the extra instruction?
3973 if (offset_expr
.X_op
!= O_symbol
3974 && offset_expr
.X_op
!= O_constant
)
3976 as_bad ("expression too complex");
3977 offset_expr
.X_op
= O_constant
;
3980 /* Even on a big endian machine $fn comes before $fn+1. We have
3981 to adjust when loading from memory. We set coproc if we must
3982 load $fn+1 first. */
3983 if (byte_order
== LITTLE_ENDIAN
)
3986 if (mips_pic
== NO_PIC
3987 || offset_expr
.X_op
== O_constant
)
3989 /* If this is a reference to a GP relative symbol, we want
3990 <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL)
3991 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_MIPS_GPREL)
3992 If we have a base register, we use this
3994 <op> $treg,<sym>($at) (BFD_RELOC_MIPS_GPREL)
3995 <op> $treg+1,<sym>+4($at) (BFD_RELOC_MIPS_GPREL)
3996 If this is not a GP relative symbol, we want
3997 lui $at,<sym> (BFD_RELOC_HI16_S)
3998 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
3999 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
4000 If there is a base register, we add it to $at after the
4001 lui instruction. If there is a constant, we always use
4003 if (offset_expr
.X_add_number
!= 0
4004 || nopic_need_relax (offset_expr
.X_add_symbol
))
4023 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4024 mips_isa
< 3 ? "addu" : "daddu",
4025 "d,v,t", AT
, breg
, GP
);
4031 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
4032 coproc
? treg
+ 1 : treg
,
4033 (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
4034 offset_expr
.X_add_number
+= 4;
4036 /* Set mips_optimize to 2 to avoid inserting an
4038 hold_mips_optimize
= mips_optimize
;
4040 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
4041 coproc
? treg
: treg
+ 1,
4042 (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
4043 mips_optimize
= hold_mips_optimize
;
4045 p
= frag_var (rs_machine_dependent
, 12 + off
, 0,
4046 RELAX_ENCODE (8 + off
, 12 + off
, 0, 4 + off
, 1,
4047 used_at
&& mips_noat
),
4048 offset_expr
.X_add_symbol
, (long) 0,
4051 /* We just generated two relocs. When tc_gen_reloc
4052 handles this case, it will skip the first reloc and
4053 handle the second. The second reloc already has an
4054 extra addend of 4, which we added above. We must
4055 subtract it out, and then subtract another 4 to make
4056 the first reloc come out right. The second reloc
4057 will come out right because we are going to add 4 to
4058 offset_expr when we build its instruction below. */
4059 offset_expr
.X_add_number
-= 8;
4060 offset_expr
.X_op
= O_constant
;
4062 macro_build_lui (p
, &icnt
, &offset_expr
, AT
);
4067 macro_build (p
, &icnt
, (expressionS
*) NULL
,
4068 mips_isa
< 3 ? "addu" : "daddu",
4069 "d,v,t", AT
, breg
, AT
);
4073 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
,
4074 coproc
? treg
+ 1 : treg
,
4075 (int) BFD_RELOC_LO16
, AT
);
4078 /* FIXME: How do we handle overflow here? */
4079 offset_expr
.X_add_number
+= 4;
4080 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
,
4081 coproc
? treg
: treg
+ 1,
4082 (int) BFD_RELOC_LO16
, AT
);
4084 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
4088 /* If this is a reference to an external symbol, we want
4089 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4094 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4096 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
4097 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
4098 If there is a base register we add it to $at before the
4099 lwc1 instructions. If there is a constant we include it
4100 in the lwc1 instructions. */
4102 expr1
.X_add_number
= offset_expr
.X_add_number
;
4103 offset_expr
.X_add_number
= 0;
4104 if (expr1
.X_add_number
< -0x8000
4105 || expr1
.X_add_number
>= 0x8000 - 4)
4106 as_bad ("PIC code offset overflow (max 16 signed bits)");
4111 frag_grow (24 + off
);
4112 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4113 mips_isa
< 3 ? "lw" : "ld",
4114 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
4115 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
4117 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4118 mips_isa
< 3 ? "addu" : "daddu",
4119 "d,v,t", AT
, breg
, AT
);
4120 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
4121 coproc
? treg
+ 1 : treg
,
4122 (int) BFD_RELOC_LO16
, AT
);
4123 expr1
.X_add_number
+= 4;
4125 /* Set mips_optimize to 2 to avoid inserting an undesired
4127 hold_mips_optimize
= mips_optimize
;
4129 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
4130 coproc
? treg
: treg
+ 1,
4131 (int) BFD_RELOC_LO16
, AT
);
4132 mips_optimize
= hold_mips_optimize
;
4134 (void) frag_var (rs_machine_dependent
, 0, 0,
4135 RELAX_ENCODE (0, 0, -16 - off
, -8, 1, 0),
4136 offset_expr
.X_add_symbol
, (long) 0,
4139 else if (mips_pic
== SVR4_PIC
)
4143 /* If this is a reference to an external symbol, we want
4144 lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16)
4146 lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16)
4151 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4153 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
4154 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
4155 If there is a base register we add it to $at before the
4156 lwc1 instructions. If there is a constant we include it
4157 in the lwc1 instructions. */
4159 expr1
.X_add_number
= offset_expr
.X_add_number
;
4160 offset_expr
.X_add_number
= 0;
4161 if (expr1
.X_add_number
< -0x8000
4162 || expr1
.X_add_number
>= 0x8000 - 4)
4163 as_bad ("PIC code offset overflow (max 16 signed bits)");
4164 if (reg_needs_delay (GP
))
4173 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
4174 AT
, (int) BFD_RELOC_MIPS_GOT_HI16
);
4175 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4176 mips_isa
< 3 ? "addu" : "daddu",
4177 "d,v,t", AT
, AT
, GP
);
4178 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4179 mips_isa
< 3 ? "lw" : "ld",
4180 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT_LO16
, AT
);
4181 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
4183 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4184 mips_isa
< 3 ? "addu" : "daddu",
4185 "d,v,t", AT
, breg
, AT
);
4186 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
4187 coproc
? treg
+ 1 : treg
,
4188 (int) BFD_RELOC_LO16
, AT
);
4189 expr1
.X_add_number
+= 4;
4191 /* Set mips_optimize to 2 to avoid inserting an undesired
4193 hold_mips_optimize
= mips_optimize
;
4195 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
4196 coproc
? treg
: treg
+ 1,
4197 (int) BFD_RELOC_LO16
, AT
);
4198 mips_optimize
= hold_mips_optimize
;
4199 expr1
.X_add_number
-= 4;
4201 p
= frag_var (rs_machine_dependent
, 16 + gpdel
+ off
, 0,
4202 RELAX_ENCODE (24 + off
, 16 + gpdel
+ off
, gpdel
,
4203 8 + gpdel
+ off
, 1, 0),
4204 offset_expr
.X_add_symbol
, (long) 0,
4208 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4211 macro_build (p
, &icnt
, &offset_expr
,
4212 mips_isa
< 3 ? "lw" : "ld",
4213 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
4215 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4219 macro_build (p
, &icnt
, (expressionS
*) NULL
,
4220 mips_isa
< 3 ? "addu" : "daddu",
4221 "d,v,t", AT
, breg
, AT
);
4224 macro_build (p
, &icnt
, &expr1
, s
, fmt
,
4225 coproc
? treg
+ 1 : treg
,
4226 (int) BFD_RELOC_LO16
, AT
);
4228 expr1
.X_add_number
+= 4;
4230 /* Set mips_optimize to 2 to avoid inserting an undesired
4232 hold_mips_optimize
= mips_optimize
;
4234 macro_build (p
, &icnt
, &expr1
, s
, fmt
,
4235 coproc
? treg
: treg
+ 1,
4236 (int) BFD_RELOC_LO16
, AT
);
4237 mips_optimize
= hold_mips_optimize
;
4239 else if (mips_pic
== EMBEDDED_PIC
)
4241 /* If there is no base register, we use
4242 <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL)
4243 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_MIPS_GPREL)
4244 If we have a base register, we use
4246 <op> $treg,<sym>($at) (BFD_RELOC_MIPS_GPREL)
4247 <op> $treg+1,<sym>+4($at) (BFD_RELOC_MIPS_GPREL)
4256 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4257 mips_isa
< 3 ? "addu" : "daddu",
4258 "d,v,t", AT
, breg
, GP
);
4263 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
4264 coproc
? treg
+ 1 : treg
,
4265 (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
4266 offset_expr
.X_add_number
+= 4;
4267 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
4268 coproc
? treg
: treg
+ 1,
4269 (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
4285 assert (mips_isa
< 3);
4286 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
4287 (int) BFD_RELOC_LO16
, breg
);
4288 offset_expr
.X_add_number
+= 4;
4289 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
+ 1,
4290 (int) BFD_RELOC_LO16
, breg
);
4292 #ifdef LOSING_COMPILER
4298 as_warn ("Macro used $at after \".set noat\"");
4303 struct mips_cl_insn
*ip
;
4305 register int treg
, sreg
, dreg
, breg
;
4320 bfd_reloc_code_real_type r
;
4323 treg
= (ip
->insn_opcode
>> 16) & 0x1f;
4324 dreg
= (ip
->insn_opcode
>> 11) & 0x1f;
4325 sreg
= breg
= (ip
->insn_opcode
>> 21) & 0x1f;
4326 mask
= ip
->insn_mo
->mask
;
4328 expr1
.X_op
= O_constant
;
4329 expr1
.X_op_symbol
= NULL
;
4330 expr1
.X_add_symbol
= NULL
;
4331 expr1
.X_add_number
= 1;
4335 #endif /* LOSING_COMPILER */
4340 macro_build ((char *) NULL
, &icnt
, NULL
,
4341 dbl
? "dmultu" : "multu",
4343 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
4349 /* The MIPS assembler some times generates shifts and adds. I'm
4350 not trying to be that fancy. GCC should do this for us
4352 load_register (&icnt
, AT
, &imm_expr
, dbl
);
4353 macro_build ((char *) NULL
, &icnt
, NULL
,
4354 dbl
? "dmult" : "mult",
4356 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
4362 mips_emit_delays ();
4364 mips_any_noreorder
= 1;
4365 macro_build ((char *) NULL
, &icnt
, NULL
,
4366 dbl
? "dmult" : "mult",
4368 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
4369 macro_build ((char *) NULL
, &icnt
, NULL
,
4370 dbl
? "dsra32" : "sra",
4371 "d,w,<", dreg
, dreg
, 31);
4372 macro_build ((char *) NULL
, &icnt
, NULL
, "mfhi", "d", AT
);
4374 macro_build ((char *) NULL
, &icnt
, NULL
, "tne", "s,t", dreg
, AT
);
4377 expr1
.X_add_number
= 8;
4378 macro_build ((char *) NULL
, &icnt
, &expr1
, "beq", "s,t,p", dreg
, AT
);
4379 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
4380 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 6);
4383 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
4389 mips_emit_delays ();
4391 mips_any_noreorder
= 1;
4392 macro_build ((char *) NULL
, &icnt
, NULL
,
4393 dbl
? "dmultu" : "multu",
4395 macro_build ((char *) NULL
, &icnt
, NULL
, "mfhi", "d", AT
);
4396 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
4398 macro_build ((char *) NULL
, &icnt
, NULL
, "tne", "s,t", AT
, 0);
4401 expr1
.X_add_number
= 8;
4402 macro_build ((char *) NULL
, &icnt
, &expr1
, "beq", "s,t,p", AT
, 0);
4403 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
4404 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 6);
4410 macro_build ((char *) NULL
, &icnt
, NULL
, "subu", "d,v,t", AT
, 0, treg
);
4411 macro_build ((char *) NULL
, &icnt
, NULL
, "srlv", "d,t,s", AT
, sreg
, AT
);
4412 macro_build ((char *) NULL
, &icnt
, NULL
, "sllv", "d,t,s", dreg
, sreg
,
4414 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
4418 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", AT
, sreg
,
4419 imm_expr
.X_add_number
& 0x1f);
4420 macro_build ((char *) NULL
, &icnt
, NULL
, "srl", "d,w,<", dreg
, sreg
,
4421 (0 - imm_expr
.X_add_number
) & 0x1f);
4422 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
4426 macro_build ((char *) NULL
, &icnt
, NULL
, "subu", "d,v,t", AT
, 0, treg
);
4427 macro_build ((char *) NULL
, &icnt
, NULL
, "sllv", "d,t,s", AT
, sreg
, AT
);
4428 macro_build ((char *) NULL
, &icnt
, NULL
, "srlv", "d,t,s", dreg
, sreg
,
4430 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
4434 macro_build ((char *) NULL
, &icnt
, NULL
, "srl", "d,w,<", AT
, sreg
,
4435 imm_expr
.X_add_number
& 0x1f);
4436 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", dreg
, sreg
,
4437 (0 - imm_expr
.X_add_number
) & 0x1f);
4438 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
4442 assert (mips_isa
< 2);
4443 /* Even on a big endian machine $fn comes before $fn+1. We have
4444 to adjust when storing to memory. */
4445 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "swc1", "T,o(b)",
4446 byte_order
== LITTLE_ENDIAN
? treg
: treg
+ 1,
4447 (int) BFD_RELOC_LO16
, breg
);
4448 offset_expr
.X_add_number
+= 4;
4449 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "swc1", "T,o(b)",
4450 byte_order
== LITTLE_ENDIAN
? treg
+ 1 : treg
,
4451 (int) BFD_RELOC_LO16
, breg
);
4456 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
4457 treg
, (int) BFD_RELOC_LO16
);
4459 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
4460 sreg
, (int) BFD_RELOC_LO16
);
4463 macro_build ((char *) NULL
, &icnt
, NULL
, "xor", "d,v,t", dreg
,
4465 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
4466 dreg
, (int) BFD_RELOC_LO16
);
4471 if (imm_expr
.X_add_number
== 0)
4473 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
4474 sreg
, (int) BFD_RELOC_LO16
);
4479 as_warn ("Instruction %s: result is always false",
4481 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
, 0);
4484 if (imm_expr
.X_add_number
>= 0 && imm_expr
.X_add_number
< 0x10000)
4486 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "xori", "t,r,i", dreg
,
4487 sreg
, (int) BFD_RELOC_LO16
);
4490 else if (imm_expr
.X_add_number
> -0x8000 && imm_expr
.X_add_number
< 0)
4492 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
4493 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
4494 mips_isa
< 3 ? "addiu" : "daddiu",
4495 "t,r,j", dreg
, sreg
,
4496 (int) BFD_RELOC_LO16
);
4501 load_register (&icnt
, AT
, &imm_expr
, 0);
4502 macro_build ((char *) NULL
, &icnt
, NULL
, "xor", "d,v,t", dreg
,
4506 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
, dreg
,
4507 (int) BFD_RELOC_LO16
);
4512 case M_SGE
: /* sreg >= treg <==> not (sreg < treg) */
4518 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, sreg
, treg
);
4519 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
4520 (int) BFD_RELOC_LO16
);
4523 case M_SGE_I
: /* sreg >= I <==> not (sreg < I) */
4525 if (imm_expr
.X_add_number
>= -0x8000 && imm_expr
.X_add_number
< 0x8000)
4527 macro_build ((char *) NULL
, &icnt
, &expr1
,
4528 mask
== M_SGE_I
? "slti" : "sltiu",
4529 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
4534 load_register (&icnt
, AT
, &imm_expr
, 0);
4535 macro_build ((char *) NULL
, &icnt
, NULL
,
4536 mask
== M_SGE_I
? "slt" : "sltu",
4537 "d,v,t", dreg
, sreg
, AT
);
4540 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
4541 (int) BFD_RELOC_LO16
);
4546 case M_SGT
: /* sreg > treg <==> treg < sreg */
4552 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, treg
, sreg
);
4555 case M_SGT_I
: /* sreg > I <==> I < sreg */
4561 load_register (&icnt
, AT
, &imm_expr
, 0);
4562 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, AT
, sreg
);
4565 case M_SLE
: /* sreg <= treg <==> treg >= sreg <==> not (treg < sreg) */
4571 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, treg
, sreg
);
4572 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
4573 (int) BFD_RELOC_LO16
);
4576 case M_SLE_I
: /* sreg <= I <==> I >= sreg <==> not (I < sreg) */
4582 load_register (&icnt
, AT
, &imm_expr
, 0);
4583 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, AT
, sreg
);
4584 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
4585 (int) BFD_RELOC_LO16
);
4589 if (imm_expr
.X_add_number
>= -0x8000 && imm_expr
.X_add_number
< 0x8000)
4591 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "slti", "t,r,j",
4592 dreg
, sreg
, (int) BFD_RELOC_LO16
);
4595 load_register (&icnt
, AT
, &imm_expr
, 0);
4596 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", dreg
, sreg
, AT
);
4600 if (imm_expr
.X_add_number
>= -0x8000 && imm_expr
.X_add_number
< 0x8000)
4602 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "sltiu", "t,r,j",
4603 dreg
, sreg
, (int) BFD_RELOC_LO16
);
4606 load_register (&icnt
, AT
, &imm_expr
, 0);
4607 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, sreg
,
4613 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0,
4616 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0,
4620 macro_build ((char *) NULL
, &icnt
, NULL
, "xor", "d,v,t", dreg
,
4622 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0,
4628 if (imm_expr
.X_add_number
== 0)
4630 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0,
4636 as_warn ("Instruction %s: result is always true",
4638 macro_build ((char *) NULL
, &icnt
, &expr1
,
4639 mips_isa
< 3 ? "addiu" : "daddiu",
4640 "t,r,j", dreg
, 0, (int) BFD_RELOC_LO16
);
4643 if (imm_expr
.X_add_number
>= 0 && imm_expr
.X_add_number
< 0x10000)
4645 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "xori", "t,r,i",
4646 dreg
, sreg
, (int) BFD_RELOC_LO16
);
4649 else if (imm_expr
.X_add_number
> -0x8000 && imm_expr
.X_add_number
< 0)
4651 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
4652 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
4653 mips_isa
< 3 ? "addiu" : "daddiu",
4654 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
4659 load_register (&icnt
, AT
, &imm_expr
, 0);
4660 macro_build ((char *) NULL
, &icnt
, NULL
, "xor", "d,v,t", dreg
,
4664 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0, dreg
);
4672 if (imm_expr
.X_add_number
> -0x8000 && imm_expr
.X_add_number
<= 0x8000)
4674 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
4675 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
4676 dbl
? "daddi" : "addi",
4677 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
4680 load_register (&icnt
, AT
, &imm_expr
, dbl
);
4681 macro_build ((char *) NULL
, &icnt
, NULL
,
4682 dbl
? "dsub" : "sub",
4683 "d,v,t", dreg
, sreg
, AT
);
4689 if (imm_expr
.X_add_number
> -0x8000 && imm_expr
.X_add_number
<= 0x8000)
4691 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
4692 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
4693 dbl
? "daddiu" : "addiu",
4694 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
4697 load_register (&icnt
, AT
, &imm_expr
, dbl
);
4698 macro_build ((char *) NULL
, &icnt
, NULL
,
4699 dbl
? "dsubu" : "subu",
4700 "d,v,t", dreg
, sreg
, AT
);
4721 load_register (&icnt
, AT
, &imm_expr
, 0);
4722 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "s,t", sreg
, AT
);
4727 assert (mips_isa
< 2);
4728 sreg
= (ip
->insn_opcode
>> 11) & 0x1f; /* floating reg */
4729 dreg
= (ip
->insn_opcode
>> 06) & 0x1f; /* floating reg */
4732 * Is the double cfc1 instruction a bug in the mips assembler;
4733 * or is there a reason for it?
4735 mips_emit_delays ();
4737 mips_any_noreorder
= 1;
4738 macro_build ((char *) NULL
, &icnt
, NULL
, "cfc1", "t,G", treg
, 31);
4739 macro_build ((char *) NULL
, &icnt
, NULL
, "cfc1", "t,G", treg
, 31);
4740 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "");
4741 expr1
.X_add_number
= 3;
4742 macro_build ((char *) NULL
, &icnt
, &expr1
, "ori", "t,r,i", AT
, treg
,
4743 (int) BFD_RELOC_LO16
);
4744 expr1
.X_add_number
= 2;
4745 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", AT
, AT
,
4746 (int) BFD_RELOC_LO16
);
4747 macro_build ((char *) NULL
, &icnt
, NULL
, "ctc1", "t,G", AT
, 31);
4748 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "");
4749 macro_build ((char *) NULL
, &icnt
, NULL
,
4750 mask
== M_TRUNCWD
? "cvt.w.d" : "cvt.w.s", "D,S", dreg
, sreg
);
4751 macro_build ((char *) NULL
, &icnt
, NULL
, "ctc1", "t,G", treg
, 31);
4752 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "");
4762 if (offset_expr
.X_add_number
>= 0x7fff)
4763 as_bad ("operand overflow");
4764 /* avoid load delay */
4765 if (byte_order
== LITTLE_ENDIAN
)
4766 offset_expr
.X_add_number
+= 1;
4767 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
4768 (int) BFD_RELOC_LO16
, breg
);
4769 if (byte_order
== LITTLE_ENDIAN
)
4770 offset_expr
.X_add_number
-= 1;
4772 offset_expr
.X_add_number
+= 1;
4773 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lbu", "t,o(b)", AT
,
4774 (int) BFD_RELOC_LO16
, breg
);
4775 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", treg
, treg
, 8);
4776 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", treg
, treg
, AT
);
4789 if (offset_expr
.X_add_number
>= 0x8000 - off
)
4790 as_bad ("operand overflow");
4791 if (byte_order
== LITTLE_ENDIAN
)
4792 offset_expr
.X_add_number
+= off
;
4793 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
4794 (int) BFD_RELOC_LO16
, breg
);
4795 if (byte_order
== LITTLE_ENDIAN
)
4796 offset_expr
.X_add_number
-= off
;
4798 offset_expr
.X_add_number
+= off
;
4799 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s2
, "t,o(b)", treg
,
4800 (int) BFD_RELOC_LO16
, breg
);
4813 load_address (&icnt
, AT
, &offset_expr
);
4815 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4816 mips_isa
< 3 ? "addu" : "daddu",
4817 "d,v,t", AT
, AT
, breg
);
4818 if (byte_order
== LITTLE_ENDIAN
)
4819 expr1
.X_add_number
= off
;
4821 expr1
.X_add_number
= 0;
4822 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, "t,o(b)", treg
,
4823 (int) BFD_RELOC_LO16
, AT
);
4824 if (byte_order
== LITTLE_ENDIAN
)
4825 expr1
.X_add_number
= 0;
4827 expr1
.X_add_number
= off
;
4828 macro_build ((char *) NULL
, &icnt
, &expr1
, s2
, "t,o(b)", treg
,
4829 (int) BFD_RELOC_LO16
, AT
);
4834 load_address (&icnt
, AT
, &offset_expr
);
4836 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4837 mips_isa
< 3 ? "addu" : "daddu",
4838 "d,v,t", AT
, AT
, breg
);
4839 if (byte_order
== BIG_ENDIAN
)
4840 expr1
.X_add_number
= 0;
4841 macro_build ((char *) NULL
, &icnt
, &expr1
,
4842 mask
== M_ULH_A
? "lb" : "lbu", "t,o(b)", treg
,
4843 (int) BFD_RELOC_LO16
, AT
);
4844 if (byte_order
== BIG_ENDIAN
)
4845 expr1
.X_add_number
= 1;
4847 expr1
.X_add_number
= 0;
4848 macro_build ((char *) NULL
, &icnt
, &expr1
, "lbu", "t,o(b)", AT
,
4849 (int) BFD_RELOC_LO16
, AT
);
4850 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", treg
,
4852 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", treg
,
4857 if (offset_expr
.X_add_number
>= 0x7fff)
4858 as_bad ("operand overflow");
4859 if (byte_order
== BIG_ENDIAN
)
4860 offset_expr
.X_add_number
+= 1;
4861 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "sb", "t,o(b)", treg
,
4862 (int) BFD_RELOC_LO16
, breg
);
4863 macro_build ((char *) NULL
, &icnt
, NULL
, "srl", "d,w,<", AT
, treg
, 8);
4864 if (byte_order
== BIG_ENDIAN
)
4865 offset_expr
.X_add_number
-= 1;
4867 offset_expr
.X_add_number
+= 1;
4868 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "sb", "t,o(b)", AT
,
4869 (int) BFD_RELOC_LO16
, breg
);
4882 if (offset_expr
.X_add_number
>= 0x8000 - off
)
4883 as_bad ("operand overflow");
4884 if (byte_order
== LITTLE_ENDIAN
)
4885 offset_expr
.X_add_number
+= off
;
4886 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
4887 (int) BFD_RELOC_LO16
, breg
);
4888 if (byte_order
== LITTLE_ENDIAN
)
4889 offset_expr
.X_add_number
-= off
;
4891 offset_expr
.X_add_number
+= off
;
4892 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s2
, "t,o(b)", treg
,
4893 (int) BFD_RELOC_LO16
, breg
);
4906 load_address (&icnt
, AT
, &offset_expr
);
4908 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4909 mips_isa
< 3 ? "addu" : "daddu",
4910 "d,v,t", AT
, AT
, breg
);
4911 if (byte_order
== LITTLE_ENDIAN
)
4912 expr1
.X_add_number
= off
;
4914 expr1
.X_add_number
= 0;
4915 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, "t,o(b)", treg
,
4916 (int) BFD_RELOC_LO16
, AT
);
4917 if (byte_order
== LITTLE_ENDIAN
)
4918 expr1
.X_add_number
= 0;
4920 expr1
.X_add_number
= off
;
4921 macro_build ((char *) NULL
, &icnt
, &expr1
, s2
, "t,o(b)", treg
,
4922 (int) BFD_RELOC_LO16
, AT
);
4926 load_address (&icnt
, AT
, &offset_expr
);
4928 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4929 mips_isa
< 3 ? "addu" : "daddu",
4930 "d,v,t", AT
, AT
, breg
);
4931 if (byte_order
== LITTLE_ENDIAN
)
4932 expr1
.X_add_number
= 0;
4933 macro_build ((char *) NULL
, &icnt
, &expr1
, "sb", "t,o(b)", treg
,
4934 (int) BFD_RELOC_LO16
, AT
);
4935 macro_build ((char *) NULL
, &icnt
, NULL
, "srl", "d,w,<", treg
,
4937 if (byte_order
== LITTLE_ENDIAN
)
4938 expr1
.X_add_number
= 1;
4940 expr1
.X_add_number
= 0;
4941 macro_build ((char *) NULL
, &icnt
, &expr1
, "sb", "t,o(b)", treg
,
4942 (int) BFD_RELOC_LO16
, AT
);
4943 if (byte_order
== LITTLE_ENDIAN
)
4944 expr1
.X_add_number
= 0;
4946 expr1
.X_add_number
= 1;
4947 macro_build ((char *) NULL
, &icnt
, &expr1
, "lbu", "t,o(b)", AT
,
4948 (int) BFD_RELOC_LO16
, AT
);
4949 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", treg
,
4951 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", treg
,
4956 as_bad ("Macro %s not implemented yet", ip
->insn_mo
->name
);
4960 as_warn ("Macro used $at after \".set noat\"");
4963 /* This routine assembles an instruction into its binary format. As a
4964 side effect, it sets one of the global variables imm_reloc or
4965 offset_reloc to the type of relocation to do if one of the operands
4966 is an address expression. */
4971 struct mips_cl_insn
*ip
;
4976 struct mips_opcode
*insn
;
4979 unsigned int lastregno
= 0;
4984 for (s
= str
; islower (*s
) || (*s
>= '0' && *s
<= '3') || *s
== '6' || *s
== '.'; ++s
)
4996 as_fatal ("Unknown opcode: `%s'", str
);
4998 if ((insn
= (struct mips_opcode
*) hash_find (op_hash
, str
)) == NULL
)
5000 as_warn ("`%s' not in hash table.", str
);
5001 insn_error
= "ERROR: Unrecognized opcode";
5009 assert (strcmp (insn
->name
, str
) == 0);
5011 if (insn
->pinfo
== INSN_MACRO
)
5012 insn_isa
= insn
->match
;
5013 else if ((insn
->pinfo
& INSN_ISA
) == INSN_ISA2
)
5015 else if ((insn
->pinfo
& INSN_ISA
) == INSN_ISA3
)
5017 else if ((insn
->pinfo
& INSN_ISA
) == INSN_ISA4
)
5022 if (insn_isa
> mips_isa
5023 || ((insn
->pinfo
& INSN_ISA
) == INSN_4650
5025 || ((insn
->pinfo
& INSN_ISA
) == INSN_4010
5027 || ((insn
->pinfo
& INSN_ISA
) == INSN_4100
5030 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
]
5031 && strcmp (insn
->name
, insn
[1].name
) == 0)
5036 as_warn ("Instruction not supported on this processor");
5040 ip
->insn_opcode
= insn
->match
;
5041 for (args
= insn
->args
;; ++args
)
5047 case '\0': /* end of args */
5060 ip
->insn_opcode
|= lastregno
<< 21;
5065 ip
->insn_opcode
|= lastregno
<< 16;
5069 ip
->insn_opcode
|= lastregno
<< 11;
5075 /* handle optional base register.
5076 Either the base register is omitted or
5077 we must have a left paren. */
5078 /* this is dependent on the next operand specifier
5079 is a 'b' for base register */
5080 assert (args
[1] == 'b');
5084 case ')': /* these must match exactly */
5089 case '<': /* must be at least one digit */
5091 * According to the manual, if the shift amount is greater
5092 * than 31 or less than 0 the the shift amount should be
5093 * mod 32. In reality the mips assembler issues an error.
5094 * We issue a warning and mask out all but the low 5 bits.
5096 my_getExpression (&imm_expr
, s
);
5097 check_absolute_expr (ip
, &imm_expr
);
5098 if ((unsigned long) imm_expr
.X_add_number
> 31)
5100 as_warn ("Improper shift amount (%ld)",
5101 (long) imm_expr
.X_add_number
);
5102 imm_expr
.X_add_number
= imm_expr
.X_add_number
& 0x1f;
5104 ip
->insn_opcode
|= imm_expr
.X_add_number
<< 6;
5105 imm_expr
.X_op
= O_absent
;
5109 case '>': /* shift amount minus 32 */
5110 my_getExpression (&imm_expr
, s
);
5111 check_absolute_expr (ip
, &imm_expr
);
5112 if ((unsigned long) imm_expr
.X_add_number
< 32
5113 || (unsigned long) imm_expr
.X_add_number
> 63)
5115 ip
->insn_opcode
|= (imm_expr
.X_add_number
- 32) << 6;
5116 imm_expr
.X_op
= O_absent
;
5120 case 'k': /* cache code */
5121 case 'h': /* prefx code */
5122 my_getExpression (&imm_expr
, s
);
5123 check_absolute_expr (ip
, &imm_expr
);
5124 if ((unsigned long) imm_expr
.X_add_number
> 31)
5126 as_warn ("Invalid value for `%s' (%lu)",
5128 (unsigned long) imm_expr
.X_add_number
);
5129 imm_expr
.X_add_number
&= 0x1f;
5132 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_CACHE
;
5134 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_PREFX
;
5135 imm_expr
.X_op
= O_absent
;
5139 case 'c': /* break code */
5140 my_getExpression (&imm_expr
, s
);
5141 check_absolute_expr (ip
, &imm_expr
);
5142 if ((unsigned) imm_expr
.X_add_number
> 1023)
5143 as_warn ("Illegal break code (%ld)",
5144 (long) imm_expr
.X_add_number
);
5145 ip
->insn_opcode
|= imm_expr
.X_add_number
<< 16;
5146 imm_expr
.X_op
= O_absent
;
5150 case 'B': /* syscall code */
5151 my_getExpression (&imm_expr
, s
);
5152 check_absolute_expr (ip
, &imm_expr
);
5153 if ((unsigned) imm_expr
.X_add_number
> 0xfffff)
5154 as_warn ("Illegal syscall code (%ld)",
5155 (long) imm_expr
.X_add_number
);
5156 ip
->insn_opcode
|= imm_expr
.X_add_number
<< 6;
5157 imm_expr
.X_op
= O_absent
;
5161 case 'C': /* Coprocessor code */
5162 my_getExpression (&imm_expr
, s
);
5163 check_absolute_expr (ip
, &imm_expr
);
5164 if ((unsigned long) imm_expr
.X_add_number
>= (1<<25))
5166 as_warn ("Coproccesor code > 25 bits (%ld)",
5167 (long) imm_expr
.X_add_number
);
5168 imm_expr
.X_add_number
&= ((1<<25) - 1);
5170 ip
->insn_opcode
|= imm_expr
.X_add_number
;
5171 imm_expr
.X_op
= O_absent
;
5175 case 'b': /* base register */
5176 case 'd': /* destination register */
5177 case 's': /* source register */
5178 case 't': /* target register */
5179 case 'r': /* both target and source */
5180 case 'v': /* both dest and source */
5181 case 'w': /* both dest and target */
5182 case 'E': /* coprocessor target register */
5183 case 'G': /* coprocessor destination register */
5184 case 'x': /* ignore register name */
5185 case 'z': /* must be zero register */
5199 while (isdigit (*s
));
5201 as_bad ("Invalid register number (%d)", regno
);
5203 else if (*args
== 'E' || *args
== 'G')
5207 if (s
[1] == 'f' && s
[2] == 'p')
5212 else if (s
[1] == 's' && s
[2] == 'p')
5217 else if (s
[1] == 'g' && s
[2] == 'p')
5222 else if (s
[1] == 'a' && s
[2] == 't')
5227 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '0')
5232 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '1')
5240 if (regno
== AT
&& ! mips_noat
)
5241 as_warn ("Used $at without \".set noat\"");
5247 if (c
== 'r' || c
== 'v' || c
== 'w')
5254 /* 'z' only matches $0. */
5255 if (c
== 'z' && regno
!= 0)
5263 ip
->insn_opcode
|= regno
<< 21;
5267 ip
->insn_opcode
|= regno
<< 11;
5272 ip
->insn_opcode
|= regno
<< 16;
5275 /* This case exists because on the r3000 trunc
5276 expands into a macro which requires a gp
5277 register. On the r6000 or r4000 it is
5278 assembled into a single instruction which
5279 ignores the register. Thus the insn version
5280 is MIPS_ISA2 and uses 'x', and the macro
5281 version is MIPS_ISA1 and uses 't'. */
5284 /* This case is for the div instruction, which
5285 acts differently if the destination argument
5286 is $0. This only matches $0, and is checked
5287 outside the switch. */
5298 ip
->insn_opcode
|= lastregno
<< 21;
5301 ip
->insn_opcode
|= lastregno
<< 16;
5306 case 'D': /* floating point destination register */
5307 case 'S': /* floating point source register */
5308 case 'T': /* floating point target register */
5309 case 'R': /* floating point source register */
5313 if (s
[0] == '$' && s
[1] == 'f' && isdigit (s
[2]))
5323 while (isdigit (*s
));
5326 as_bad ("Invalid float register number (%d)", regno
);
5328 if ((regno
& 1) != 0
5330 && ! (strcmp (str
, "mtc1") == 0 ||
5331 strcmp (str
, "mfc1") == 0 ||
5332 strcmp (str
, "lwc1") == 0 ||
5333 strcmp (str
, "swc1") == 0))
5334 as_warn ("Float register should be even, was %d",
5342 if (c
== 'V' || c
== 'W')
5352 ip
->insn_opcode
|= regno
<< 6;
5356 ip
->insn_opcode
|= regno
<< 11;
5360 ip
->insn_opcode
|= regno
<< 16;
5363 ip
->insn_opcode
|= regno
<< 21;
5372 ip
->insn_opcode
|= lastregno
<< 11;
5375 ip
->insn_opcode
|= lastregno
<< 16;
5381 my_getExpression (&imm_expr
, s
);
5382 if (imm_expr
.X_op
!= O_big
)
5383 check_absolute_expr (ip
, &imm_expr
);
5388 my_getExpression (&offset_expr
, s
);
5389 imm_reloc
= BFD_RELOC_32
;
5401 unsigned char temp
[8];
5403 unsigned int length
;
5408 /* These only appear as the last operand in an
5409 instruction, and every instruction that accepts
5410 them in any variant accepts them in all variants.
5411 This means we don't have to worry about backing out
5412 any changes if the instruction does not match.
5414 The difference between them is the size of the
5415 floating point constant and where it goes. For 'F'
5416 and 'L' the constant is 64 bits; for 'f' and 'l' it
5417 is 32 bits. Where the constant is placed is based
5418 on how the MIPS assembler does things:
5421 f -- immediate value
5424 The .lit4 and .lit8 sections are only used if
5425 permitted by the -G argument.
5427 When generating embedded PIC code, we use the
5428 .lit8 section but not the .lit4 section (we can do
5429 .lit4 inline easily; we need to put .lit8
5430 somewhere in the data segment, and using .lit8
5431 permits the linker to eventually combine identical
5434 f64
= *args
== 'F' || *args
== 'L';
5436 save_in
= input_line_pointer
;
5437 input_line_pointer
= s
;
5438 err
= md_atof (f64
? 'd' : 'f', (char *) temp
, &len
);
5440 s
= input_line_pointer
;
5441 input_line_pointer
= save_in
;
5442 if (err
!= NULL
&& *err
!= '\0')
5444 as_bad ("Bad floating point constant: %s", err
);
5445 memset (temp
, '\0', sizeof temp
);
5446 length
= f64
? 8 : 4;
5449 assert (length
== (f64
? 8 : 4));
5453 && (! USE_GLOBAL_POINTER_OPT
5454 || mips_pic
== EMBEDDED_PIC
5455 || g_switch_value
< 4)
5458 imm_expr
.X_op
= O_constant
;
5459 if (byte_order
== LITTLE_ENDIAN
)
5460 imm_expr
.X_add_number
=
5461 (((((((int) temp
[3] << 8)
5466 imm_expr
.X_add_number
=
5467 (((((((int) temp
[0] << 8)
5474 const char *newname
;
5477 /* Switch to the right section. */
5479 subseg
= now_subseg
;
5482 default: /* unused default case avoids warnings. */
5484 newname
= RDATA_SECTION_NAME
;
5485 if (USE_GLOBAL_POINTER_OPT
&& g_switch_value
>= 8)
5489 newname
= RDATA_SECTION_NAME
;
5492 assert (!USE_GLOBAL_POINTER_OPT
5493 || g_switch_value
>= 4);
5497 new_seg
= subseg_new (newname
, (subsegT
) 0);
5498 frag_align (*args
== 'l' ? 2 : 3, 0);
5499 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
5500 record_alignment (new_seg
, 4);
5502 record_alignment (new_seg
, *args
== 'l' ? 2 : 3);
5504 as_bad ("Can't use floating point insn in this section");
5506 /* Set the argument to the current address in the
5508 offset_expr
.X_op
= O_symbol
;
5509 offset_expr
.X_add_symbol
=
5510 symbol_new ("L0\001", now_seg
,
5511 (valueT
) frag_now_fix (), frag_now
);
5512 offset_expr
.X_add_number
= 0;
5514 /* Put the floating point number into the section. */
5515 p
= frag_more ((int) length
);
5516 memcpy (p
, temp
, length
);
5518 /* Switch back to the original section. */
5519 subseg_set (seg
, subseg
);
5524 case 'i': /* 16 bit unsigned immediate */
5525 case 'j': /* 16 bit signed immediate */
5526 imm_reloc
= BFD_RELOC_LO16
;
5527 c
= my_getSmallExpression (&imm_expr
, s
);
5532 if (imm_expr
.X_op
== O_constant
)
5533 imm_expr
.X_add_number
=
5534 (imm_expr
.X_add_number
>> 16) & 0xffff;
5537 imm_reloc
= BFD_RELOC_HI16_S
;
5538 imm_unmatched_hi
= true;
5541 imm_reloc
= BFD_RELOC_HI16
;
5544 else if (imm_expr
.X_op
!= O_big
)
5545 check_absolute_expr (ip
, &imm_expr
);
5548 if (imm_expr
.X_op
== O_big
5549 || imm_expr
.X_add_number
< 0
5550 || imm_expr
.X_add_number
>= 0x10000)
5552 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
5553 !strcmp (insn
->name
, insn
[1].name
))
5555 as_bad ("16 bit expression not in range 0..65535");
5563 /* The upper bound should be 0x8000, but
5564 unfortunately the MIPS assembler accepts numbers
5565 from 0x8000 to 0xffff and sign extends them, and
5566 we want to be compatible. We only permit this
5567 extended range for an instruction which does not
5568 provide any further alternates, since those
5569 alternates may handle other cases. People should
5570 use the numbers they mean, rather than relying on
5571 a mysterious sign extension. */
5572 more
= (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
5573 strcmp (insn
->name
, insn
[1].name
) == 0);
5578 if (imm_expr
.X_op
== O_big
5579 || imm_expr
.X_add_number
< -0x8000
5580 || imm_expr
.X_add_number
>= max
5582 && imm_expr
.X_add_number
< 0
5584 && imm_expr
.X_unsigned
5585 && sizeof (imm_expr
.X_add_number
) <= 4))
5589 as_bad ("16 bit expression not in range -32768..32767");
5595 case 'o': /* 16 bit offset */
5596 c
= my_getSmallExpression (&offset_expr
, s
);
5598 /* If this value won't fit into a 16 bit offset, then go
5599 find a macro that will generate the 32 bit offset
5600 code pattern. As a special hack, we accept the
5601 difference of two local symbols as a constant. This
5602 is required to suppose embedded PIC switches, which
5603 use an instruction which looks like
5604 lw $4,$L12-$LS12($4)
5605 The problem with handling this in a more general
5606 fashion is that the macro function doesn't expect to
5607 see anything which can be handled in a single
5608 constant instruction. */
5610 && (offset_expr
.X_op
!= O_constant
5611 || offset_expr
.X_add_number
>= 0x8000
5612 || offset_expr
.X_add_number
< -0x8000)
5613 && (mips_pic
!= EMBEDDED_PIC
5614 || offset_expr
.X_op
!= O_subtract
5615 || now_seg
!= text_section
5616 || (S_GET_SEGMENT (offset_expr
.X_op_symbol
)
5620 offset_reloc
= BFD_RELOC_LO16
;
5621 if (c
== 'h' || c
== 'H')
5623 assert (offset_expr
.X_op
== O_constant
);
5624 offset_expr
.X_add_number
=
5625 (offset_expr
.X_add_number
>> 16) & 0xffff;
5630 case 'p': /* pc relative offset */
5631 offset_reloc
= BFD_RELOC_16_PCREL_S2
;
5632 my_getExpression (&offset_expr
, s
);
5636 case 'u': /* upper 16 bits */
5637 c
= my_getSmallExpression (&imm_expr
, s
);
5638 if (imm_expr
.X_op
== O_constant
5639 && (imm_expr
.X_add_number
< 0
5640 || imm_expr
.X_add_number
>= 0x10000))
5641 as_bad ("lui expression not in range 0..65535");
5642 imm_reloc
= BFD_RELOC_LO16
;
5647 if (imm_expr
.X_op
== O_constant
)
5648 imm_expr
.X_add_number
=
5649 (imm_expr
.X_add_number
>> 16) & 0xffff;
5652 imm_reloc
= BFD_RELOC_HI16_S
;
5653 imm_unmatched_hi
= true;
5656 imm_reloc
= BFD_RELOC_HI16
;
5662 case 'a': /* 26 bit address */
5663 my_getExpression (&offset_expr
, s
);
5665 offset_reloc
= BFD_RELOC_MIPS_JMP
;
5668 case 'N': /* 3 bit branch condition code */
5669 case 'M': /* 3 bit compare condition code */
5670 my_getExpression (&imm_expr
, s
);
5671 check_absolute_expr (ip
, &imm_expr
);
5672 if ((unsigned long) imm_expr
.X_add_number
> 7)
5674 as_warn ("Condition code > 7 (%ld)",
5675 (long) imm_expr
.X_add_number
);
5676 imm_expr
.X_add_number
&= 7;
5679 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_BCC
;
5681 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_CCC
;
5682 imm_expr
.X_op
= O_absent
;
5687 fprintf (stderr
, "bad char = '%c'\n", *args
);
5692 /* Args don't match. */
5693 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
5694 !strcmp (insn
->name
, insn
[1].name
))
5700 insn_error
= "ERROR: Illegal operands";
5709 my_getSmallExpression (ep
, str
)
5720 ((str
[1] == 'h' && str
[2] == 'i')
5721 || (str
[1] == 'H' && str
[2] == 'I')
5722 || (str
[1] == 'l' && str
[2] == 'o'))
5734 * A small expression may be followed by a base register.
5735 * Scan to the end of this operand, and then back over a possible
5736 * base register. Then scan the small expression up to that
5737 * point. (Based on code in sparc.c...)
5739 for (sp
= str
; *sp
&& *sp
!= ','; sp
++)
5741 if (sp
- 4 >= str
&& sp
[-1] == RP
)
5743 if (isdigit (sp
[-2]))
5745 for (sp
-= 3; sp
>= str
&& isdigit (*sp
); sp
--)
5747 if (*sp
== '$' && sp
> str
&& sp
[-1] == LP
)
5753 else if (sp
- 5 >= str
5756 && ((sp
[-3] == 'f' && sp
[-2] == 'p')
5757 || (sp
[-3] == 's' && sp
[-2] == 'p')
5758 || (sp
[-3] == 'g' && sp
[-2] == 'p')
5759 || (sp
[-3] == 'a' && sp
[-2] == 't')))
5765 /* no expression means zero offset */
5768 /* %xx(reg) is an error */
5769 ep
->X_op
= O_absent
;
5774 ep
->X_op
= O_constant
;
5777 ep
->X_add_symbol
= NULL
;
5778 ep
->X_op_symbol
= NULL
;
5779 ep
->X_add_number
= 0;
5784 my_getExpression (ep
, str
);
5791 my_getExpression (ep
, str
);
5792 return c
; /* => %hi or %lo encountered */
5796 my_getExpression (ep
, str
)
5802 save_in
= input_line_pointer
;
5803 input_line_pointer
= str
;
5805 expr_end
= input_line_pointer
;
5806 input_line_pointer
= save_in
;
5809 /* Turn a string in input_line_pointer into a floating point constant
5810 of type type, and store the appropriate bytes in *litP. The number
5811 of LITTLENUMS emitted is stored in *sizeP . An error message is
5812 returned, or NULL on OK. */
5815 md_atof (type
, litP
, sizeP
)
5821 LITTLENUM_TYPE words
[4];
5837 return "bad call to md_atof";
5840 t
= atof_ieee (input_line_pointer
, type
, words
);
5842 input_line_pointer
= t
;
5846 if (byte_order
== LITTLE_ENDIAN
)
5848 for (i
= prec
- 1; i
>= 0; i
--)
5850 md_number_to_chars (litP
, (valueT
) words
[i
], 2);
5856 for (i
= 0; i
< prec
; i
++)
5858 md_number_to_chars (litP
, (valueT
) words
[i
], 2);
5867 md_number_to_chars (buf
, val
, n
)
5875 number_to_chars_littleendian (buf
, val
, n
);
5879 number_to_chars_bigendian (buf
, val
, n
);
5887 CONST
char *md_shortopts
= "O::g::G:";
5889 struct option md_longopts
[] = {
5890 #define OPTION_MIPS1 (OPTION_MD_BASE + 1)
5891 {"mips0", no_argument
, NULL
, OPTION_MIPS1
},
5892 {"mips1", no_argument
, NULL
, OPTION_MIPS1
},
5893 #define OPTION_MIPS2 (OPTION_MD_BASE + 2)
5894 {"mips2", no_argument
, NULL
, OPTION_MIPS2
},
5895 #define OPTION_MIPS3 (OPTION_MD_BASE + 3)
5896 {"mips3", no_argument
, NULL
, OPTION_MIPS3
},
5897 #define OPTION_MIPS4 (OPTION_MD_BASE + 4)
5898 {"mips4", no_argument
, NULL
, OPTION_MIPS4
},
5899 #define OPTION_MCPU (OPTION_MD_BASE + 5)
5900 {"mcpu", required_argument
, NULL
, OPTION_MCPU
},
5901 #define OPTION_MEMBEDDED_PIC (OPTION_MD_BASE + 6)
5902 {"membedded-pic", no_argument
, NULL
, OPTION_MEMBEDDED_PIC
},
5903 #define OPTION_TRAP (OPTION_MD_BASE + 9)
5904 {"trap", no_argument
, NULL
, OPTION_TRAP
},
5905 {"no-break", no_argument
, NULL
, OPTION_TRAP
},
5906 #define OPTION_BREAK (OPTION_MD_BASE + 10)
5907 {"break", no_argument
, NULL
, OPTION_BREAK
},
5908 {"no-trap", no_argument
, NULL
, OPTION_BREAK
},
5909 #define OPTION_EB (OPTION_MD_BASE + 11)
5910 {"EB", no_argument
, NULL
, OPTION_EB
},
5911 #define OPTION_EL (OPTION_MD_BASE + 12)
5912 {"EL", no_argument
, NULL
, OPTION_EL
},
5913 #define OPTION_M4650 (OPTION_MD_BASE + 13)
5914 {"m4650", no_argument
, NULL
, OPTION_M4650
},
5915 #define OPTION_NO_M4650 (OPTION_MD_BASE + 14)
5916 {"no-m4650", no_argument
, NULL
, OPTION_NO_M4650
},
5917 #define OPTION_M4010 (OPTION_MD_BASE + 15)
5918 {"m4010", no_argument
, NULL
, OPTION_M4010
},
5919 #define OPTION_NO_M4010 (OPTION_MD_BASE + 16)
5920 {"no-m4010", no_argument
, NULL
, OPTION_NO_M4010
},
5921 #define OPTION_M4100 (OPTION_MD_BASE + 17)
5922 {"m4100", no_argument
, NULL
, OPTION_M4100
},
5923 #define OPTION_NO_M4100 (OPTION_MD_BASE + 18)
5924 {"no-m4100", no_argument
, NULL
, OPTION_NO_M4100
},
5926 #define OPTION_CALL_SHARED (OPTION_MD_BASE + 7)
5927 #define OPTION_NON_SHARED (OPTION_MD_BASE + 8)
5928 #define OPTION_XGOT (OPTION_MD_BASE + 19)
5930 {"KPIC", no_argument
, NULL
, OPTION_CALL_SHARED
},
5931 {"xgot", no_argument
, NULL
, OPTION_XGOT
},
5932 {"call_shared", no_argument
, NULL
, OPTION_CALL_SHARED
},
5933 {"non_shared", no_argument
, NULL
, OPTION_NON_SHARED
},
5936 {NULL
, no_argument
, NULL
, 0}
5938 size_t md_longopts_size
= sizeof(md_longopts
);
5941 md_parse_option (c
, arg
)
5956 target_big_endian
= 1;
5960 target_big_endian
= 0;
5964 if (arg
&& arg
[1] == '0')
5974 mips_debug
= atoi (arg
);
5975 /* When the MIPS assembler sees -g or -g2, it does not do
5976 optimizations which limit full symbolic debugging. We take
5977 that to be equivalent to -O0. */
5978 if (mips_debug
== 2)
6010 /* Identify the processor type */
6012 if (strcmp (p
, "default") == 0
6013 || strcmp (p
, "DEFAULT") == 0)
6019 /* We need to cope with the various "vr" prefixes for the 4300
6021 if (*p
== 'v' || *p
== 'V')
6027 if (*p
== 'r' || *p
== 'R')
6034 if (strcmp (p
, "10000") == 0
6035 || strcmp (p
, "10k") == 0
6036 || strcmp (p
, "10K") == 0)
6041 if (strcmp (p
, "2000") == 0
6042 || strcmp (p
, "2k") == 0
6043 || strcmp (p
, "2K") == 0)
6048 if (strcmp (p
, "3000") == 0
6049 || strcmp (p
, "3k") == 0
6050 || strcmp (p
, "3K") == 0)
6055 if (strcmp (p
, "4000") == 0
6056 || strcmp (p
, "4k") == 0
6057 || strcmp (p
, "4K") == 0)
6059 else if (strcmp (p
, "4100") == 0)
6065 else if (strcmp (p
, "4300") == 0)
6067 else if (strcmp (p
, "4400") == 0)
6069 else if (strcmp (p
, "4600") == 0)
6071 else if (strcmp (p
, "4650") == 0)
6077 else if (strcmp (p
, "4010") == 0)
6086 if (strcmp (p
, "6000") == 0
6087 || strcmp (p
, "6k") == 0
6088 || strcmp (p
, "6K") == 0)
6093 if (strcmp (p
, "8000") == 0
6094 || strcmp (p
, "8k") == 0
6095 || strcmp (p
, "8K") == 0)
6100 if (strcmp (p
, "orion") == 0)
6105 if (sv
&& mips_cpu
!= 4300 && mips_cpu
!= 4100)
6107 as_bad ("ignoring invalid leading 'v' in -mcpu=%s switch", arg
);
6113 as_bad ("invalid architecture -mcpu=%s", arg
);
6124 case OPTION_NO_M4650
:
6132 case OPTION_NO_M4010
:
6140 case OPTION_NO_M4100
:
6144 case OPTION_MEMBEDDED_PIC
:
6145 mips_pic
= EMBEDDED_PIC
;
6146 if (USE_GLOBAL_POINTER_OPT
&& g_switch_seen
)
6148 as_bad ("-G may not be used with embedded PIC code");
6151 g_switch_value
= 0x7fffffff;
6154 /* When generating ELF code, we permit -KPIC and -call_shared to
6155 select SVR4_PIC, and -non_shared to select no PIC. This is
6156 intended to be compatible with Irix 5. */
6157 case OPTION_CALL_SHARED
:
6158 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
6160 as_bad ("-call_shared is supported only for ELF format");
6163 mips_pic
= SVR4_PIC
;
6164 if (g_switch_seen
&& g_switch_value
!= 0)
6166 as_bad ("-G may not be used with SVR4 PIC code");
6172 case OPTION_NON_SHARED
:
6173 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
6175 as_bad ("-non_shared is supported only for ELF format");
6181 /* The -xgot option tells the assembler to use 32 offsets when
6182 accessing the got in SVR4_PIC mode. It is for Irix
6189 if (! USE_GLOBAL_POINTER_OPT
)
6191 as_bad ("-G is not supported for this configuration");
6194 else if (mips_pic
== SVR4_PIC
|| mips_pic
== EMBEDDED_PIC
)
6196 as_bad ("-G may not be used with SVR4 or embedded PIC code");
6200 g_switch_value
= atoi (arg
);
6212 md_show_usage (stream
)
6217 -membedded-pic generate embedded position independent code\n\
6218 -EB generate big endian output\n\
6219 -EL generate little endian output\n\
6220 -g, -g2 do not remove uneeded NOPs or swap branches\n\
6221 -G NUM allow referencing objects up to NUM bytes\n\
6222 implicitly with the gp register [default 8]\n");
6224 -mips1, -mcpu=r{2,3}000 generate code for r2000 and r3000\n\
6225 -mips2, -mcpu=r6000 generate code for r6000\n\
6226 -mips3, -mcpu=r4000 generate code for r4000\n\
6227 -mips4, -mcpu=r8000 generate code for r8000\n\
6228 -mcpu=vr4300 generate code for vr4300\n\
6229 -mcpu=vr4100 generate code for vr4100\n\
6230 -m4650 permit R4650 instructions\n\
6231 -no-m4650 do not permit R4650 instructions\n\
6232 -m4010 permit R4010 instructions\n\
6233 -no-m4010 do not permit R4010 instructions\n\
6234 -m4100 permit VR4100 instructions\n\
6235 -no-m4100 do not permit VR4100 instructions\n");
6237 -O0 remove unneeded NOPs, do not swap branches\n\
6238 -O remove unneeded NOPs and swap branches\n\
6239 --trap, --no-break trap exception on div by 0 and mult overflow\n\
6240 --break, --no-trap break exception on div by 0 and mult overflow\n");
6243 -KPIC, -call_shared generate SVR4 position independent code\n\
6244 -non_shared do not generate position independent code\n\
6245 -xgot assume a 32 bit GOT\n");
6250 mips_init_after_args ()
6252 if (target_big_endian
)
6253 byte_order
= BIG_ENDIAN
;
6255 byte_order
= LITTLE_ENDIAN
;
6259 md_pcrel_from (fixP
)
6262 if (OUTPUT_FLAVOR
!= bfd_target_aout_flavour
6263 && fixP
->fx_addsy
!= (symbolS
*) NULL
6264 && ! S_IS_DEFINED (fixP
->fx_addsy
))
6266 /* This makes a branch to an undefined symbol be a branch to the
6267 current location. */
6271 /* return the address of the delay slot */
6272 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
6275 /* This is called by emit_expr via TC_CONS_FIX_NEW when creating a
6276 reloc for a cons. We could use the definition there, except that
6277 we want to handle 64 bit relocs specially. */
6280 cons_fix_new_mips (frag
, where
, nbytes
, exp
)
6283 unsigned int nbytes
;
6286 /* If we are assembling in 32 bit mode, turn an 8 byte reloc into a
6288 FIXME: There is no way to select anything but 32 bit mode right
6292 if (byte_order
== BIG_ENDIAN
)
6297 if (nbytes
!= 2 && nbytes
!= 4)
6298 as_bad ("Unsupported reloc size %d", nbytes
);
6300 fix_new_exp (frag_now
, where
, (int) nbytes
, exp
, 0,
6301 nbytes
== 2 ? BFD_RELOC_16
: BFD_RELOC_32
);
6304 /* Sort any unmatched HI16_S relocs so that they immediately precede
6305 the corresponding LO reloc. This is called before md_apply_fix and
6306 tc_gen_reloc. Unmatched HI16_S relocs can only be generated by
6307 explicit use of the %hi modifier. */
6312 struct mips_hi_fixup
*l
;
6314 for (l
= mips_hi_fixup_list
; l
!= NULL
; l
= l
->next
)
6316 segment_info_type
*seginfo
;
6319 assert (l
->fixp
->fx_r_type
== BFD_RELOC_HI16_S
);
6321 /* Check quickly whether the next fixup happens to be a matching
6323 if (l
->fixp
->fx_next
!= NULL
6324 && l
->fixp
->fx_next
->fx_r_type
== BFD_RELOC_LO16
6325 && l
->fixp
->fx_addsy
== l
->fixp
->fx_next
->fx_addsy
6326 && l
->fixp
->fx_offset
== l
->fixp
->fx_next
->fx_offset
)
6329 /* Look through the fixups for this segment for a matching %lo.
6330 When we find one, move the %hi just in front of it. */
6331 seginfo
= seg_info (l
->seg
);
6333 for (f
= seginfo
->fix_root
; f
!= NULL
; f
= f
->fx_next
)
6335 /* Check whether this is a %lo fixup which matches l->fixp;
6336 we can't use it if the %lo is already matching a %hi. */
6337 if (f
->fx_r_type
== BFD_RELOC_LO16
6338 && f
->fx_addsy
== l
->fixp
->fx_addsy
6339 && f
->fx_offset
== l
->fixp
->fx_offset
6341 || prev
->fx_r_type
!= BFD_RELOC_HI16_S
6342 || prev
->fx_addsy
!= f
->fx_addsy
6343 || prev
->fx_offset
!= f
->fx_offset
))
6347 /* Move l->fixp before f. */
6348 for (pf
= &seginfo
->fix_root
;
6350 pf
= &(*pf
)->fx_next
)
6351 assert (*pf
!= NULL
);
6353 *pf
= l
->fixp
->fx_next
;
6355 l
->fixp
->fx_next
= f
;
6357 seginfo
->fix_root
= l
->fixp
;
6359 prev
->fx_next
= l
->fixp
;
6368 as_warn_where (l
->fixp
->fx_file
, l
->fixp
->fx_line
,
6369 "Unmatched %%hi reloc");
6373 /* When generating embedded PIC code we need to use a special
6374 relocation to represent the difference of two symbols in the .text
6375 section (switch tables use a difference of this sort). See
6376 include/coff/mips.h for details. This macro checks whether this
6377 fixup requires the special reloc. */
6378 #define SWITCH_TABLE(fixp) \
6379 ((fixp)->fx_r_type == BFD_RELOC_32 \
6380 && (fixp)->fx_addsy != NULL \
6381 && (fixp)->fx_subsy != NULL \
6382 && S_GET_SEGMENT ((fixp)->fx_addsy) == text_section \
6383 && S_GET_SEGMENT ((fixp)->fx_subsy) == text_section)
6385 /* When generating embedded PIC code we must keep all PC relative
6386 relocations, in case the linker has to relax a call. We also need
6387 to keep relocations for switch table entries. */
6391 mips_force_relocation (fixp
)
6394 return (mips_pic
== EMBEDDED_PIC
6396 || SWITCH_TABLE (fixp
)
6397 || fixp
->fx_r_type
== BFD_RELOC_PCREL_HI16_S
6398 || fixp
->fx_r_type
== BFD_RELOC_PCREL_LO16
));
6401 /* Apply a fixup to the object file. */
6404 md_apply_fix (fixP
, valueP
)
6411 assert (fixP
->fx_size
== 4 || fixP
->fx_r_type
== BFD_RELOC_16
);
6414 fixP
->fx_addnumber
= value
; /* Remember value for tc_gen_reloc */
6416 if (fixP
->fx_addsy
== NULL
&& ! fixP
->fx_pcrel
)
6419 switch (fixP
->fx_r_type
)
6421 case BFD_RELOC_MIPS_JMP
:
6422 case BFD_RELOC_HI16
:
6423 case BFD_RELOC_HI16_S
:
6424 case BFD_RELOC_MIPS_GPREL
:
6425 case BFD_RELOC_MIPS_LITERAL
:
6426 case BFD_RELOC_MIPS_CALL16
:
6427 case BFD_RELOC_MIPS_GOT16
:
6428 case BFD_RELOC_MIPS_GPREL32
:
6429 case BFD_RELOC_MIPS_GOT_HI16
:
6430 case BFD_RELOC_MIPS_GOT_LO16
:
6431 case BFD_RELOC_MIPS_CALL_HI16
:
6432 case BFD_RELOC_MIPS_CALL_LO16
:
6434 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
6435 "Invalid PC relative reloc");
6436 /* Nothing needed to do. The value comes from the reloc entry */
6439 case BFD_RELOC_PCREL_HI16_S
:
6440 /* The addend for this is tricky if it is internal, so we just
6441 do everything here rather than in bfd_perform_relocation. */
6442 if ((fixP
->fx_addsy
->bsym
->flags
& BSF_SECTION_SYM
) == 0)
6444 /* For an external symbol adjust by the address to make it
6445 pcrel_offset. We use the address of the RELLO reloc
6446 which follows this one. */
6447 value
+= (fixP
->fx_next
->fx_frag
->fr_address
6448 + fixP
->fx_next
->fx_where
);
6453 buf
= (unsigned char *) fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
6454 if (byte_order
== BIG_ENDIAN
)
6456 md_number_to_chars (buf
, value
, 2);
6459 case BFD_RELOC_PCREL_LO16
:
6460 /* The addend for this is tricky if it is internal, so we just
6461 do everything here rather than in bfd_perform_relocation. */
6462 if ((fixP
->fx_addsy
->bsym
->flags
& BSF_SECTION_SYM
) == 0)
6463 value
+= fixP
->fx_frag
->fr_address
+ fixP
->fx_where
;
6464 buf
= (unsigned char *) fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
6465 if (byte_order
== BIG_ENDIAN
)
6467 md_number_to_chars (buf
, value
, 2);
6471 /* If we are deleting this reloc entry, we must fill in the
6472 value now. This can happen if we have a .word which is not
6473 resolved when it appears but is later defined. We also need
6474 to fill in the value if this is an embedded PIC switch table
6477 || (mips_pic
== EMBEDDED_PIC
&& SWITCH_TABLE (fixP
)))
6478 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
,
6483 /* If we are deleting this reloc entry, we must fill in the
6485 assert (fixP
->fx_size
== 2);
6487 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
,
6491 case BFD_RELOC_LO16
:
6492 /* When handling an embedded PIC switch statement, we can wind
6493 up deleting a LO16 reloc. See the 'o' case in mips_ip. */
6496 if (value
< -0x8000 || value
> 0x7fff)
6497 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
6498 "relocation overflow");
6499 buf
= (unsigned char *) fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
6500 if (byte_order
== BIG_ENDIAN
)
6502 md_number_to_chars (buf
, value
, 2);
6506 case BFD_RELOC_16_PCREL_S2
:
6508 * We need to save the bits in the instruction since fixup_segment()
6509 * might be deleting the relocation entry (i.e., a branch within
6510 * the current segment).
6513 as_warn_where (fixP
->fx_file
, fixP
->fx_line
,
6514 "Branch to odd address (%lx)", value
);
6517 /* update old instruction data */
6518 buf
= (unsigned char *) (fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
);
6522 insn
= (buf
[3] << 24) | (buf
[2] << 16) | (buf
[1] << 8) | buf
[0];
6526 insn
= (buf
[0] << 24) | (buf
[1] << 16) | (buf
[2] << 8) | buf
[3];
6534 if (value
>= -0x8000 && value
< 0x8000)
6535 insn
|= value
& 0xffff;
6538 /* The branch offset is too large. If this is an
6539 unconditional branch, and we are not generating PIC code,
6540 we can convert it to an absolute jump instruction. */
6541 if (mips_pic
== NO_PIC
6543 && fixP
->fx_frag
->fr_address
>= text_section
->vma
6544 && (fixP
->fx_frag
->fr_address
6545 < text_section
->vma
+ text_section
->_raw_size
)
6546 && ((insn
& 0xffff0000) == 0x10000000 /* beq $0,$0 */
6547 || (insn
& 0xffff0000) == 0x04010000 /* bgez $0 */
6548 || (insn
& 0xffff0000) == 0x04110000)) /* bgezal $0 */
6550 if ((insn
& 0xffff0000) == 0x04110000) /* bgezal $0 */
6551 insn
= 0x0c000000; /* jal */
6553 insn
= 0x08000000; /* j */
6554 fixP
->fx_r_type
= BFD_RELOC_MIPS_JMP
;
6556 fixP
->fx_addsy
= section_symbol (text_section
);
6557 fixP
->fx_addnumber
= (value
<< 2) + md_pcrel_from (fixP
);
6561 /* FIXME. It would be possible in principle to handle
6562 conditional branches which overflow. They could be
6563 transformed into a branch around a jump. This would
6564 require setting up variant frags for each different
6565 branch type. The native MIPS assembler attempts to
6566 handle these cases, but it appears to do it
6568 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
6569 "Relocation overflow");
6573 md_number_to_chars ((char *) buf
, (valueT
) insn
, 4);
6588 const struct mips_opcode
*p
;
6589 int treg
, sreg
, dreg
, shamt
;
6594 for (i
= 0; i
< NUMOPCODES
; ++i
)
6596 p
= &mips_opcodes
[i
];
6597 if (((oc
& p
->mask
) == p
->match
) && (p
->pinfo
!= INSN_MACRO
))
6599 printf ("%08lx %s\t", oc
, p
->name
);
6600 treg
= (oc
>> 16) & 0x1f;
6601 sreg
= (oc
>> 21) & 0x1f;
6602 dreg
= (oc
>> 11) & 0x1f;
6603 shamt
= (oc
>> 6) & 0x1f;
6605 for (args
= p
->args
;; ++args
)
6616 printf ("%c", *args
);
6620 assert (treg
== sreg
);
6621 printf ("$%d,$%d", treg
, sreg
);
6626 printf ("$%d", dreg
);
6631 printf ("$%d", treg
);
6635 printf ("0x%x", treg
);
6640 printf ("$%d", sreg
);
6644 printf ("0x%08lx", oc
& 0x1ffffff);
6656 printf ("$%d", shamt
);
6667 printf ("%08lx UNDEFINED\n", oc
);
6678 name
= input_line_pointer
;
6679 c
= get_symbol_end ();
6680 p
= (symbolS
*) symbol_find_or_make (name
);
6681 *input_line_pointer
= c
;
6685 /* Align the current frag to a given power of two. The MIPS assembler
6686 also automatically adjusts any preceding label. */
6689 mips_align (to
, fill
, label
)
6694 mips_emit_delays ();
6695 frag_align (to
, fill
);
6696 record_alignment (now_seg
, to
);
6699 assert (S_GET_SEGMENT (label
) == now_seg
);
6700 label
->sy_frag
= frag_now
;
6701 S_SET_VALUE (label
, (valueT
) frag_now_fix ());
6705 /* Align to a given power of two. .align 0 turns off the automatic
6706 alignment used by the data creating pseudo-ops. */
6713 register long temp_fill
;
6714 long max_alignment
= 15;
6718 o Note that the assembler pulls down any immediately preceeding label
6719 to the aligned address.
6720 o It's not documented but auto alignment is reinstated by
6721 a .align pseudo instruction.
6722 o Note also that after auto alignment is turned off the mips assembler
6723 issues an error on attempt to assemble an improperly aligned data item.
6728 temp
= get_absolute_expression ();
6729 if (temp
> max_alignment
)
6730 as_bad ("Alignment too large: %d. assumed.", temp
= max_alignment
);
6733 as_warn ("Alignment negative: 0 assumed.");
6736 if (*input_line_pointer
== ',')
6738 input_line_pointer
++;
6739 temp_fill
= get_absolute_expression ();
6746 mips_align (temp
, (int) temp_fill
, insn_label
);
6753 demand_empty_rest_of_line ();
6757 mips_flush_pending_output ()
6759 mips_emit_delays ();
6769 /* When generating embedded PIC code, we only use the .text, .lit8,
6770 .sdata and .sbss sections. We change the .data and .rdata
6771 pseudo-ops to use .sdata. */
6772 if (mips_pic
== EMBEDDED_PIC
6773 && (sec
== 'd' || sec
== 'r'))
6776 mips_emit_delays ();
6786 subseg_set (bss_section
, (subsegT
) get_absolute_expression ());
6787 demand_empty_rest_of_line ();
6791 if (USE_GLOBAL_POINTER_OPT
)
6793 seg
= subseg_new (RDATA_SECTION_NAME
,
6794 (subsegT
) get_absolute_expression ());
6795 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
6797 bfd_set_section_flags (stdoutput
, seg
,
6803 bfd_set_section_alignment (stdoutput
, seg
, 4);
6805 demand_empty_rest_of_line ();
6809 as_bad ("No read only data section in this object file format");
6810 demand_empty_rest_of_line ();
6816 if (USE_GLOBAL_POINTER_OPT
)
6818 seg
= subseg_new (".sdata", (subsegT
) get_absolute_expression ());
6819 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
6821 bfd_set_section_flags (stdoutput
, seg
,
6822 SEC_ALLOC
| SEC_LOAD
| SEC_RELOC
6824 bfd_set_section_alignment (stdoutput
, seg
, 4);
6826 demand_empty_rest_of_line ();
6831 as_bad ("Global pointers not supported; recompile -G 0");
6832 demand_empty_rest_of_line ();
6841 mips_enable_auto_align ()
6853 mips_emit_delays ();
6854 if (log_size
> 0 && auto_align
)
6855 mips_align (log_size
, 0, label
);
6857 cons (1 << log_size
);
6868 mips_emit_delays ();
6872 mips_align (3, 0, label
);
6874 mips_align (2, 0, label
);
6881 /* Handle .globl. We need to override it because on Irix 5 you are
6884 where foo is an undefined symbol, to mean that foo should be
6885 considered to be the address of a function. */
6896 name
= input_line_pointer
;
6897 c
= get_symbol_end ();
6898 symbolP
= symbol_find_or_make (name
);
6899 *input_line_pointer
= c
;
6902 /* On Irix 5, every global symbol that is not explicitly labelled as
6903 being a function is apparently labelled as being an object. */
6906 if (! is_end_of_line
[(unsigned char) *input_line_pointer
])
6911 secname
= input_line_pointer
;
6912 c
= get_symbol_end ();
6913 sec
= bfd_get_section_by_name (stdoutput
, secname
);
6915 as_bad ("%s: no such section", secname
);
6916 *input_line_pointer
= c
;
6918 if (sec
!= NULL
&& (sec
->flags
& SEC_CODE
) != 0)
6919 flag
= BSF_FUNCTION
;
6922 symbolP
->bsym
->flags
|= flag
;
6924 S_SET_EXTERNAL (symbolP
);
6925 demand_empty_rest_of_line ();
6935 opt
= input_line_pointer
;
6936 c
= get_symbol_end ();
6940 /* FIXME: What does this mean? */
6942 else if (strncmp (opt
, "pic", 3) == 0)
6950 mips_pic
= SVR4_PIC
;
6952 as_bad (".option pic%d not supported", i
);
6954 if (USE_GLOBAL_POINTER_OPT
&& mips_pic
== SVR4_PIC
)
6956 if (g_switch_seen
&& g_switch_value
!= 0)
6957 as_warn ("-G may not be used with SVR4 PIC code");
6959 bfd_set_gp_size (stdoutput
, 0);
6963 as_warn ("Unrecognized option \"%s\"", opt
);
6965 *input_line_pointer
= c
;
6966 demand_empty_rest_of_line ();
6973 char *name
= input_line_pointer
, ch
;
6975 while (!is_end_of_line
[(unsigned char) *input_line_pointer
])
6976 input_line_pointer
++;
6977 ch
= *input_line_pointer
;
6978 *input_line_pointer
= '\0';
6980 if (strcmp (name
, "reorder") == 0)
6984 prev_insn_unreordered
= 1;
6985 prev_prev_insn_unreordered
= 1;
6989 else if (strcmp (name
, "noreorder") == 0)
6991 mips_emit_delays ();
6993 mips_any_noreorder
= 1;
6995 else if (strcmp (name
, "at") == 0)
6999 else if (strcmp (name
, "noat") == 0)
7003 else if (strcmp (name
, "macro") == 0)
7005 mips_warn_about_macros
= 0;
7007 else if (strcmp (name
, "nomacro") == 0)
7009 if (mips_noreorder
== 0)
7010 as_bad ("`noreorder' must be set before `nomacro'");
7011 mips_warn_about_macros
= 1;
7013 else if (strcmp (name
, "move") == 0 || strcmp (name
, "novolatile") == 0)
7017 else if (strcmp (name
, "nomove") == 0 || strcmp (name
, "volatile") == 0)
7021 else if (strcmp (name
, "bopt") == 0)
7025 else if (strcmp (name
, "nobopt") == 0)
7029 else if (strncmp (name
, "mips", 4) == 0)
7033 /* Permit the user to change the ISA on the fly. Needless to
7034 say, misuse can cause serious problems. */
7035 isa
= atoi (name
+ 4);
7037 mips_isa
= file_mips_isa
;
7038 else if (isa
< 1 || isa
> 4)
7039 as_bad ("unknown ISA level");
7045 as_warn ("Tried to set unrecognized symbol: %s\n", name
);
7047 *input_line_pointer
= ch
;
7048 demand_empty_rest_of_line ();
7051 /* Handle the .abicalls pseudo-op. I believe this is equivalent to
7052 .option pic2. It means to generate SVR4 PIC calls. */
7058 mips_pic
= SVR4_PIC
;
7059 if (USE_GLOBAL_POINTER_OPT
)
7061 if (g_switch_seen
&& g_switch_value
!= 0)
7062 as_warn ("-G may not be used with SVR4 PIC code");
7065 bfd_set_gp_size (stdoutput
, 0);
7066 demand_empty_rest_of_line ();
7069 /* Handle the .cpload pseudo-op. This is used when generating SVR4
7070 PIC code. It sets the $gp register for the function based on the
7071 function address, which is in the register named in the argument.
7072 This uses a relocation against _gp_disp, which is handled specially
7073 by the linker. The result is:
7074 lui $gp,%hi(_gp_disp)
7075 addiu $gp,$gp,%lo(_gp_disp)
7076 addu $gp,$gp,.cpload argument
7077 The .cpload argument is normally $25 == $t9. */
7086 /* If we are not generating SVR4 PIC code, .cpload is ignored. */
7087 if (mips_pic
!= SVR4_PIC
)
7093 /* .cpload should be a in .set noreorder section. */
7094 if (mips_noreorder
== 0)
7095 as_warn (".cpload not in noreorder section");
7098 ex
.X_add_symbol
= symbol_find_or_make ("_gp_disp");
7099 ex
.X_op_symbol
= NULL
;
7100 ex
.X_add_number
= 0;
7102 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
7103 ex
.X_add_symbol
->bsym
->flags
|= BSF_OBJECT
;
7105 macro_build_lui ((char *) NULL
, &icnt
, &ex
, GP
);
7106 macro_build ((char *) NULL
, &icnt
, &ex
, "addiu", "t,r,j", GP
, GP
,
7107 (int) BFD_RELOC_LO16
);
7109 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "addu", "d,v,t",
7110 GP
, GP
, tc_get_register (0));
7112 demand_empty_rest_of_line ();
7115 /* Handle the .cprestore pseudo-op. This stores $gp into a given
7116 offset from $sp. The offset is remembered, and after making a PIC
7117 call $gp is restored from that location. */
7120 s_cprestore (ignore
)
7126 /* If we are not generating SVR4 PIC code, .cprestore is ignored. */
7127 if (mips_pic
!= SVR4_PIC
)
7133 mips_cprestore_offset
= get_absolute_expression ();
7135 ex
.X_op
= O_constant
;
7136 ex
.X_add_symbol
= NULL
;
7137 ex
.X_op_symbol
= NULL
;
7138 ex
.X_add_number
= mips_cprestore_offset
;
7140 macro_build ((char *) NULL
, &icnt
, &ex
,
7141 mips_isa
< 3 ? "sw" : "sd",
7142 "t,o(b)", GP
, (int) BFD_RELOC_LO16
, SP
);
7144 demand_empty_rest_of_line ();
7147 /* Handle the .gpword pseudo-op. This is used when generating PIC
7148 code. It generates a 32 bit GP relative reloc. */
7158 /* When not generating PIC code, this is treated as .word. */
7159 if (mips_pic
!= SVR4_PIC
)
7166 mips_emit_delays ();
7168 mips_align (2, 0, label
);
7173 if (ex
.X_op
!= O_symbol
|| ex
.X_add_number
!= 0)
7175 as_bad ("Unsupported use of .gpword");
7176 ignore_rest_of_line ();
7180 md_number_to_chars (p
, (valueT
) 0, 4);
7181 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 4, &ex
, 0,
7182 BFD_RELOC_MIPS_GPREL32
);
7184 demand_empty_rest_of_line ();
7187 /* Handle the .cpadd pseudo-op. This is used when dealing with switch
7188 tables in SVR4 PIC code. */
7197 /* This is ignored when not generating SVR4 PIC code. */
7198 if (mips_pic
!= SVR4_PIC
)
7204 /* Add $gp to the register named as an argument. */
7205 reg
= tc_get_register (0);
7206 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
7207 mips_isa
< 3 ? "addu" : "daddu",
7208 "d,v,t", reg
, reg
, GP
);
7210 demand_empty_rest_of_line ();
7213 /* Parse a register string into a number. Called from the ECOFF code
7214 to parse .frame. The argument is non-zero if this is the frame
7215 register, so that we can record it in mips_frame_reg. */
7218 tc_get_register (frame
)
7224 if (*input_line_pointer
++ != '$')
7226 as_warn ("expected `$'");
7229 else if (isdigit ((unsigned char) *input_line_pointer
))
7231 reg
= get_absolute_expression ();
7232 if (reg
< 0 || reg
>= 32)
7234 as_warn ("Bad register number");
7240 if (strncmp (input_line_pointer
, "fp", 2) == 0)
7242 else if (strncmp (input_line_pointer
, "sp", 2) == 0)
7244 else if (strncmp (input_line_pointer
, "gp", 2) == 0)
7246 else if (strncmp (input_line_pointer
, "at", 2) == 0)
7250 as_warn ("Unrecognized register name");
7253 input_line_pointer
+= 2;
7256 mips_frame_reg
= reg
!= 0 ? reg
: SP
;
7261 md_section_align (seg
, addr
)
7265 int align
= bfd_get_section_alignment (stdoutput
, seg
);
7267 return ((addr
+ (1 << align
) - 1) & (-1 << align
));
7270 /* Utility routine, called from above as well. If called while the
7271 input file is still being read, it's only an approximation. (For
7272 example, a symbol may later become defined which appeared to be
7273 undefined earlier.) */
7276 nopic_need_relax (sym
)
7282 if (USE_GLOBAL_POINTER_OPT
)
7284 const char *symname
;
7287 /* Find out whether this symbol can be referenced off the GP
7288 register. It can be if it is smaller than the -G size or if
7289 it is in the .sdata or .sbss section. Certain symbols can
7290 not be referenced off the GP, although it appears as though
7292 symname
= S_GET_NAME (sym
);
7293 if (symname
!= (const char *) NULL
7294 && (strcmp (symname
, "eprol") == 0
7295 || strcmp (symname
, "etext") == 0
7296 || strcmp (symname
, "_gp") == 0
7297 || strcmp (symname
, "edata") == 0
7298 || strcmp (symname
, "_fbss") == 0
7299 || strcmp (symname
, "_fdata") == 0
7300 || strcmp (symname
, "_ftext") == 0
7301 || strcmp (symname
, "end") == 0
7302 || strcmp (symname
, "_gp_disp") == 0))
7304 else if (! S_IS_DEFINED (sym
)
7306 #ifndef NO_ECOFF_DEBUGGING
7307 || (sym
->ecoff_extern_size
!= 0
7308 && sym
->ecoff_extern_size
<= g_switch_value
)
7310 || (S_GET_VALUE (sym
) != 0
7311 && S_GET_VALUE (sym
) <= g_switch_value
)))
7315 const char *segname
;
7317 segname
= segment_name (S_GET_SEGMENT (sym
));
7318 assert (strcmp (segname
, ".lit8") != 0
7319 && strcmp (segname
, ".lit4") != 0);
7320 change
= (strcmp (segname
, ".sdata") != 0
7321 && strcmp (segname
, ".sbss") != 0);
7326 /* We are not optimizing for the GP register. */
7330 /* Estimate the size of a frag before relaxing. We are not really
7331 relaxing here, and the final size is encoded in the subtype
7336 md_estimate_size_before_relax (fragp
, segtype
)
7342 if (mips_pic
== NO_PIC
)
7344 change
= nopic_need_relax (fragp
->fr_symbol
);
7346 else if (mips_pic
== SVR4_PIC
)
7348 asection
*symsec
= fragp
->fr_symbol
->bsym
->section
;
7350 /* This must duplicate the test in adjust_reloc_syms. */
7351 change
= (symsec
!= &bfd_und_section
7352 && symsec
!= &bfd_abs_section
7353 && ! bfd_is_com_section (symsec
));
7360 /* Record the offset to the first reloc in the fr_opcode field.
7361 This lets md_convert_frag and tc_gen_reloc know that the code
7362 must be expanded. */
7363 fragp
->fr_opcode
= (fragp
->fr_literal
7365 - RELAX_OLD (fragp
->fr_subtype
)
7366 + RELAX_RELOC1 (fragp
->fr_subtype
));
7367 /* FIXME: This really needs as_warn_where. */
7368 if (RELAX_WARN (fragp
->fr_subtype
))
7369 as_warn ("AT used after \".set noat\" or macro used after \".set nomacro\"");
7375 return RELAX_NEW (fragp
->fr_subtype
) - RELAX_OLD (fragp
->fr_subtype
);
7378 /* Translate internal representation of relocation info to BFD target
7382 tc_gen_reloc (section
, fixp
)
7386 static arelent
*retval
[4];
7389 reloc
= retval
[0] = (arelent
*) xmalloc (sizeof (arelent
));
7392 reloc
->sym_ptr_ptr
= &fixp
->fx_addsy
->bsym
;
7393 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
7395 if (mips_pic
== EMBEDDED_PIC
7396 && SWITCH_TABLE (fixp
))
7398 /* For a switch table entry we use a special reloc. The addend
7399 is actually the difference between the reloc address and the
7401 reloc
->addend
= reloc
->address
- S_GET_VALUE (fixp
->fx_subsy
);
7402 if (OUTPUT_FLAVOR
!= bfd_target_ecoff_flavour
)
7403 as_fatal ("Double check fx_r_type in tc-mips.c:tc_gen_reloc");
7404 fixp
->fx_r_type
= BFD_RELOC_GPREL32
;
7406 else if (fixp
->fx_r_type
== BFD_RELOC_PCREL_LO16
)
7408 /* We use a special addend for an internal RELLO reloc. */
7409 if (fixp
->fx_addsy
->bsym
->flags
& BSF_SECTION_SYM
)
7410 reloc
->addend
= reloc
->address
- S_GET_VALUE (fixp
->fx_subsy
);
7412 reloc
->addend
= fixp
->fx_addnumber
+ reloc
->address
;
7414 else if (fixp
->fx_r_type
== BFD_RELOC_PCREL_HI16_S
)
7416 assert (fixp
->fx_next
!= NULL
7417 && fixp
->fx_next
->fx_r_type
== BFD_RELOC_PCREL_LO16
);
7418 /* We use a special addend for an internal RELHI reloc. The
7419 reloc is relative to the RELLO; adjust the addend
7421 if (fixp
->fx_addsy
->bsym
->flags
& BSF_SECTION_SYM
)
7422 reloc
->addend
= (fixp
->fx_next
->fx_frag
->fr_address
7423 + fixp
->fx_next
->fx_where
7424 - S_GET_VALUE (fixp
->fx_subsy
));
7426 reloc
->addend
= (fixp
->fx_addnumber
7427 + fixp
->fx_next
->fx_frag
->fr_address
7428 + fixp
->fx_next
->fx_where
);
7430 else if (fixp
->fx_pcrel
== 0)
7431 reloc
->addend
= fixp
->fx_addnumber
;
7434 if (OUTPUT_FLAVOR
!= bfd_target_aout_flavour
)
7435 /* A gruesome hack which is a result of the gruesome gas reloc
7437 reloc
->addend
= reloc
->address
;
7439 reloc
->addend
= -reloc
->address
;
7442 /* If this is a variant frag, we may need to adjust the existing
7443 reloc and generate a new one. */
7444 if (fixp
->fx_frag
->fr_opcode
!= NULL
7445 && (fixp
->fx_r_type
== BFD_RELOC_MIPS_GPREL
7446 || fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT16
7447 || fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL16
7448 || fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT_HI16
7449 || fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT_LO16
7450 || fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL_HI16
7451 || fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL_LO16
))
7455 /* If this is not the last reloc in this frag, then we have two
7456 GPREL relocs, or a GOT_HI16/GOT_LO16 pair, or a
7457 CALL_HI16/CALL_LO16, both of which are being replaced. Let
7458 the second one handle all of them. */
7459 if (fixp
->fx_next
!= NULL
7460 && fixp
->fx_frag
== fixp
->fx_next
->fx_frag
)
7462 assert ((fixp
->fx_r_type
== BFD_RELOC_MIPS_GPREL
7463 && fixp
->fx_next
->fx_r_type
== BFD_RELOC_MIPS_GPREL
)
7464 || (fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT_HI16
7465 && (fixp
->fx_next
->fx_r_type
7466 == BFD_RELOC_MIPS_GOT_LO16
))
7467 || (fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL_HI16
7468 && (fixp
->fx_next
->fx_r_type
7469 == BFD_RELOC_MIPS_CALL_LO16
)));
7474 fixp
->fx_where
= fixp
->fx_frag
->fr_opcode
- fixp
->fx_frag
->fr_literal
;
7475 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
7476 reloc2
= retval
[1] = (arelent
*) xmalloc (sizeof (arelent
));
7478 reloc2
->sym_ptr_ptr
= &fixp
->fx_addsy
->bsym
;
7479 reloc2
->address
= (reloc
->address
7480 + (RELAX_RELOC2 (fixp
->fx_frag
->fr_subtype
)
7481 - RELAX_RELOC1 (fixp
->fx_frag
->fr_subtype
)));
7482 reloc2
->addend
= fixp
->fx_addnumber
;
7483 reloc2
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_LO16
);
7484 assert (reloc2
->howto
!= NULL
);
7486 if (RELAX_RELOC3 (fixp
->fx_frag
->fr_subtype
))
7490 reloc3
= retval
[2] = (arelent
*) xmalloc (sizeof (arelent
));
7493 reloc3
->address
+= 4;
7496 if (mips_pic
== NO_PIC
)
7498 assert (fixp
->fx_r_type
== BFD_RELOC_MIPS_GPREL
);
7499 fixp
->fx_r_type
= BFD_RELOC_HI16_S
;
7501 else if (mips_pic
== SVR4_PIC
)
7503 switch (fixp
->fx_r_type
)
7507 case BFD_RELOC_MIPS_GOT16
:
7509 case BFD_RELOC_MIPS_CALL16
:
7510 case BFD_RELOC_MIPS_GOT_LO16
:
7511 case BFD_RELOC_MIPS_CALL_LO16
:
7512 fixp
->fx_r_type
= BFD_RELOC_MIPS_GOT16
;
7520 /* To support a PC relative reloc when generating embedded PIC code
7521 for ECOFF, we use a Cygnus extension. We check for that here to
7522 make sure that we don't let such a reloc escape normally. */
7523 if (OUTPUT_FLAVOR
== bfd_target_ecoff_flavour
7524 && fixp
->fx_r_type
== BFD_RELOC_16_PCREL_S2
7525 && mips_pic
!= EMBEDDED_PIC
)
7526 reloc
->howto
= NULL
;
7528 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, fixp
->fx_r_type
);
7530 if (reloc
->howto
== NULL
)
7532 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
7533 "Can not represent relocation in this object file format");
7540 /* Convert a machine dependent frag. */
7543 md_convert_frag (abfd
, asec
, fragp
)
7551 if (fragp
->fr_opcode
== NULL
)
7554 old
= RELAX_OLD (fragp
->fr_subtype
);
7555 new = RELAX_NEW (fragp
->fr_subtype
);
7556 fixptr
= fragp
->fr_literal
+ fragp
->fr_fix
;
7559 memcpy (fixptr
- old
, fixptr
, new);
7561 fragp
->fr_fix
+= new - old
;
7564 /* This function is called whenever a label is defined. It is used
7565 when handling branch delays; if a branch has a label, we assume we
7569 mips_define_label (sym
)
7575 /* Decide whether a label is local. This is called by LOCAL_LABEL.
7576 In order to work with gcc when using mips-tfile, we must keep all
7577 local labels. However, in other cases, we want to discard them,
7578 since they are useless. */
7581 mips_local_label (name
)
7584 #ifndef NO_ECOFF_DEBUGGING
7587 && ! ecoff_debugging_seen
)
7589 /* We were called with -g, but we didn't see any debugging
7590 information. That may mean that gcc is smuggling debugging
7591 information through to mips-tfile, in which case we must
7592 generate all local labels. */
7597 /* Here it's OK to discard local labels. */
7599 return name
[0] == '$';
7602 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7604 /* Some special processing for a MIPS ELF file. */
7607 mips_elf_final_processing ()
7611 /* Write out the .reginfo section. */
7612 s
.ri_gprmask
= mips_gprmask
;
7613 s
.ri_cprmask
[0] = mips_cprmask
[0];
7614 s
.ri_cprmask
[1] = mips_cprmask
[1];
7615 s
.ri_cprmask
[2] = mips_cprmask
[2];
7616 s
.ri_cprmask
[3] = mips_cprmask
[3];
7617 /* The gp_value field is set by the MIPS ELF backend. */
7619 bfd_mips_elf32_swap_reginfo_out (stdoutput
, &s
,
7620 ((Elf32_External_RegInfo
*)
7621 mips_regmask_frag
));
7623 /* Set the MIPS ELF flag bits. FIXME: There should probably be some
7624 sort of BFD interface for this. */
7625 if (mips_any_noreorder
)
7626 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_NOREORDER
;
7627 if (mips_pic
!= NO_PIC
)
7628 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_PIC
;
7631 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */
7633 /* These functions should really be defined by the object file format,
7634 since they are related to debugging information. However, this
7635 code has to work for the a.out format, which does not define them,
7636 so we provide simple versions here. These don't actually generate
7637 any debugging information, but they do simple checking and someday
7638 somebody may make them useful. */
7642 struct loc
*loc_next
;
7643 unsigned long loc_fileno
;
7644 unsigned long loc_lineno
;
7645 unsigned long loc_offset
;
7646 unsigned short loc_delta
;
7647 unsigned short loc_count
;
7656 struct proc
*proc_next
;
7657 struct symbol
*proc_isym
;
7658 struct symbol
*proc_end
;
7659 unsigned long proc_reg_mask
;
7660 unsigned long proc_reg_offset
;
7661 unsigned long proc_fpreg_mask
;
7662 unsigned long proc_fpreg_offset
;
7663 unsigned long proc_frameoffset
;
7664 unsigned long proc_framereg
;
7665 unsigned long proc_pcreg
;
7667 struct file
*proc_file
;
7674 struct file
*file_next
;
7675 unsigned long file_fileno
;
7676 struct symbol
*file_symbol
;
7677 struct symbol
*file_end
;
7678 struct proc
*file_proc
;
7683 static struct obstack proc_frags
;
7684 static procS
*proc_lastP
;
7685 static procS
*proc_rootP
;
7686 static int numprocs
;
7691 obstack_begin (&proc_frags
, 0x2000);
7697 /* check for premature end, nesting errors, etc */
7698 if (proc_lastP
&& proc_lastP
->proc_end
== NULL
)
7699 as_warn ("missing `.end' at end of assembly");
7708 if (*input_line_pointer
== '-')
7710 ++input_line_pointer
;
7713 if (!isdigit (*input_line_pointer
))
7714 as_bad ("Expected simple number.");
7715 if (input_line_pointer
[0] == '0')
7717 if (input_line_pointer
[1] == 'x')
7719 input_line_pointer
+= 2;
7720 while (isxdigit (*input_line_pointer
))
7723 val
|= hex_value (*input_line_pointer
++);
7725 return negative
? -val
: val
;
7729 ++input_line_pointer
;
7730 while (isdigit (*input_line_pointer
))
7733 val
|= *input_line_pointer
++ - '0';
7735 return negative
? -val
: val
;
7738 if (!isdigit (*input_line_pointer
))
7740 printf (" *input_line_pointer == '%c' 0x%02x\n",
7741 *input_line_pointer
, *input_line_pointer
);
7742 as_warn ("Invalid number");
7745 while (isdigit (*input_line_pointer
))
7748 val
+= *input_line_pointer
++ - '0';
7750 return negative
? -val
: val
;
7753 /* The .file directive; just like the usual .file directive, but there
7754 is an initial number which is the ECOFF file index. */
7762 line
= get_number ();
7767 /* The .end directive. */
7775 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
7778 demand_empty_rest_of_line ();
7782 if (now_seg
!= text_section
)
7783 as_warn (".end not in text section");
7786 as_warn (".end and no .ent seen yet.");
7792 assert (S_GET_NAME (p
));
7793 if (strcmp (S_GET_NAME (p
), S_GET_NAME (proc_lastP
->proc_isym
)))
7794 as_warn (".end symbol does not match .ent symbol.");
7797 proc_lastP
->proc_end
= (symbolS
*) 1;
7800 /* The .aent and .ent directives. */
7810 symbolP
= get_symbol ();
7811 if (*input_line_pointer
== ',')
7812 input_line_pointer
++;
7814 if (isdigit (*input_line_pointer
) || *input_line_pointer
== '-')
7815 number
= get_number ();
7816 if (now_seg
!= text_section
)
7817 as_warn (".ent or .aent not in text section.");
7819 if (!aent
&& proc_lastP
&& proc_lastP
->proc_end
== NULL
)
7820 as_warn ("missing `.end'");
7824 procP
= (procS
*) obstack_alloc (&proc_frags
, sizeof (*procP
));
7825 procP
->proc_isym
= symbolP
;
7826 procP
->proc_reg_mask
= 0;
7827 procP
->proc_reg_offset
= 0;
7828 procP
->proc_fpreg_mask
= 0;
7829 procP
->proc_fpreg_offset
= 0;
7830 procP
->proc_frameoffset
= 0;
7831 procP
->proc_framereg
= 0;
7832 procP
->proc_pcreg
= 0;
7833 procP
->proc_end
= NULL
;
7834 procP
->proc_next
= NULL
;
7836 proc_lastP
->proc_next
= procP
;
7842 demand_empty_rest_of_line ();
7845 /* The .frame directive. */
7858 frame_reg
= tc_get_register (1);
7859 if (*input_line_pointer
== ',')
7860 input_line_pointer
++;
7861 frame_off
= get_absolute_expression ();
7862 if (*input_line_pointer
== ',')
7863 input_line_pointer
++;
7864 pcreg
= tc_get_register (0);
7867 assert (proc_rootP
);
7868 proc_rootP
->proc_framereg
= frame_reg
;
7869 proc_rootP
->proc_frameoffset
= frame_off
;
7870 proc_rootP
->proc_pcreg
= pcreg
;
7871 /* bob macho .frame */
7873 /* We don't have to write out a frame stab for unoptimized code. */
7874 if (!(frame_reg
== FP
&& frame_off
== 0))
7877 as_warn ("No .ent for .frame to use.");
7878 (void) sprintf (str
, "R%d;%d", frame_reg
, frame_off
);
7879 symP
= symbol_new (str
, N_VFP
, 0, frag_now
);
7880 S_SET_TYPE (symP
, N_RMASK
);
7881 S_SET_OTHER (symP
, 0);
7882 S_SET_DESC (symP
, 0);
7883 symP
->sy_forward
= proc_lastP
->proc_isym
;
7884 /* bob perhaps I should have used pseudo set */
7886 demand_empty_rest_of_line ();
7890 /* The .fmask and .mask directives. */
7897 char str
[100], *strP
;
7903 mask
= get_number ();
7904 if (*input_line_pointer
== ',')
7905 input_line_pointer
++;
7906 off
= get_absolute_expression ();
7908 /* bob only for coff */
7909 assert (proc_rootP
);
7910 if (reg_type
== 'F')
7912 proc_rootP
->proc_fpreg_mask
= mask
;
7913 proc_rootP
->proc_fpreg_offset
= off
;
7917 proc_rootP
->proc_reg_mask
= mask
;
7918 proc_rootP
->proc_reg_offset
= off
;
7921 /* bob macho .mask + .fmask */
7923 /* We don't have to write out a mask stab if no saved regs. */
7927 as_warn ("No .ent for .mask to use.");
7929 for (i
= 0; i
< 32; i
++)
7933 sprintf (strP
, "%c%d,", reg_type
, i
);
7934 strP
+= strlen (strP
);
7938 sprintf (strP
, ";%d,", off
);
7939 symP
= symbol_new (str
, N_RMASK
, 0, frag_now
);
7940 S_SET_TYPE (symP
, N_RMASK
);
7941 S_SET_OTHER (symP
, 0);
7942 S_SET_DESC (symP
, 0);
7943 symP
->sy_forward
= proc_lastP
->proc_isym
;
7944 /* bob perhaps I should have used pseudo set */
7949 /* The .loc directive. */
7960 assert (now_seg
== text_section
);
7962 lineno
= get_number ();
7963 addroff
= frag_now_fix ();
7965 symbolP
= symbol_new ("", N_SLINE
, addroff
, frag_now
);
7966 S_SET_TYPE (symbolP
, N_SLINE
);
7967 S_SET_OTHER (symbolP
, 0);
7968 S_SET_DESC (symbolP
, lineno
);
7969 symbolP
->sy_segment
= now_seg
;