1 /* tc-mips.c -- assemble code for a MIPS chip.
2 Copyright (C) 1993 Free Software Foundation, Inc.
3 Contributed by the OSF and Ralph Campbell.
4 Written by Keith Knowles and Ralph Campbell, working independently.
5 Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus
8 This file is part of GAS.
10 GAS is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 2, or (at your option)
15 GAS is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with GAS; see the file COPYING. If not, write to
22 the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */
40 #endif /* NO_VARARGS */
41 #endif /* NO_STDARG */
43 #include "opcode/mips.h"
49 /* Decide whether to do GP reference optimizations based on the object
59 /* MIPS ISA (Instruction Set Architecture) level. */
60 static int mips_isa
= -1;
62 static int mips_warn_about_macros
;
63 static int mips_noreorder
;
64 static int mips_nomove
;
66 static int mips_nobopt
;
69 /* The size of the small data section. */
70 static int g_switch_value
= 8;
76 /* handle of the OPCODE hash table */
77 static struct hash_control
*op_hash
= NULL
;
79 /* This array holds the chars that always start a comment. If the
80 pre-processor is disabled, these aren't very useful */
81 const char comment_chars
[] = "#";
83 /* This array holds the chars that only start a comment at the beginning of
84 a line. If the line seems to have the form '# 123 filename'
85 .line and .file directives will appear in the pre-processed output */
86 /* Note that input_file.c hand checks for '#' at the beginning of the
87 first line of the input file. This is because the compiler outputs
88 #NO_APP at the beginning of its output. */
89 /* Also note that C style comments are always supported. */
90 const char line_comment_chars
[] = "#";
92 /* This array holds machine specific line separator characters. */
93 const char line_separator_chars
[] = "";
95 /* Chars that can be used to separate mant from exp in floating point nums */
96 const char EXP_CHARS
[] = "eE";
98 /* Chars that mean this number is a floating point constant */
101 const char FLT_CHARS
[] = "rRsSfFdDxXpP";
103 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
104 changed in read.c . Ideally it shouldn't have to know about it at all,
105 but nothing is ideal around here.
108 static char *insn_error
;
110 static int byte_order
= BYTE_ORDER
;
112 static int auto_align
= 1;
114 /* Symbol labelling the current insn. */
115 static symbolS
*insn_label
;
117 /* To output NOP instructions correctly, we need to keep information
118 about the previous two instructions. */
120 /* Whether we are optimizing. The default value of 2 means to remove
121 unneeded NOPs and swap branch instructions when possible. A value
122 of 1 means to not swap branches. A value of 0 means to always
124 static int mips_optimize
= 2;
126 /* The previous instruction. */
127 static struct mips_cl_insn prev_insn
;
129 /* The instruction before prev_insn. */
130 static struct mips_cl_insn prev_prev_insn
;
132 /* If we don't want information for prev_insn or prev_prev_insn, we
133 point the insn_mo field at this dummy integer. */
134 static const struct mips_opcode dummy_opcode
= { 0 };
136 /* Non-zero if prev_insn is valid. */
137 static int prev_insn_valid
;
139 /* The frag for the previous instruction. */
140 static struct frag
*prev_insn_frag
;
142 /* The offset into prev_insn_frag for the previous instruction. */
143 static long prev_insn_where
;
145 /* The reloc for the previous instruction, if any. */
146 static fixS
*prev_insn_fixp
;
148 /* Non-zero if the previous instruction was in a delay slot. */
149 static int prev_insn_is_delay_slot
;
151 /* Non-zero if the previous instruction was in a .set noreorder. */
152 static int prev_insn_unreordered
;
154 /* Non-zero if the previous previous instruction was in a .set
156 static int prev_prev_insn_unreordered
;
158 /* Prototypes for static functions. */
161 #define internalError() \
162 as_fatal ("internal Error, line %d, %s", __LINE__, __FILE__)
164 #define internalError() as_fatal ("MIPS internal Error");
167 static int insn_uses_reg
PARAMS ((struct mips_cl_insn
*ip
,
168 unsigned int reg
, int fpr
));
169 static void append_insn
PARAMS ((struct mips_cl_insn
* ip
,
171 bfd_reloc_code_real_type r
));
172 static void mips_no_prev_insn
PARAMS ((void));
173 static void mips_emit_delays
PARAMS ((void));
174 static int gp_reference
PARAMS ((expressionS
* ep
));
175 static void macro_build
PARAMS ((int *counter
, expressionS
* ep
,
176 const char *name
, const char *fmt
,
178 static void macro_build_lui
PARAMS ((int *counter
, expressionS
* ep
,
180 static void set_at
PARAMS ((int *counter
, int reg
, int unsignedp
));
181 static void check_absolute_expr
PARAMS ((struct mips_cl_insn
* ip
,
183 static void load_register
PARAMS ((int *counter
,
184 int reg
, expressionS
* ep
));
185 static void macro
PARAMS ((struct mips_cl_insn
* ip
));
186 static void mips_ip
PARAMS ((char *str
, struct mips_cl_insn
* ip
));
187 static int my_getSmallExpression
PARAMS ((expressionS
* ep
, char *str
));
188 static void my_getExpression
PARAMS ((expressionS
* ep
, char *str
));
189 static symbolS
*get_symbol
PARAMS ((void));
190 static void mips_align
PARAMS ((int to
, int fill
));
191 static void s_align
PARAMS ((int));
192 static void s_stringer
PARAMS ((int));
193 static void s_change_sec
PARAMS ((int));
194 static void s_cons
PARAMS ((int));
195 static void s_err
PARAMS ((int));
196 static void s_extern
PARAMS ((int));
197 static void s_float_cons
PARAMS ((int));
198 static void s_option
PARAMS ((int));
199 static void s_mipsset
PARAMS ((int));
200 static void s_mips_space
PARAMS ((int));
202 static void md_obj_begin
PARAMS ((void));
203 static void md_obj_end
PARAMS ((void));
204 static long get_number
PARAMS ((void));
205 static void s_ent
PARAMS ((int));
206 static void s_mipsend
PARAMS ((int));
207 static void s_file
PARAMS ((int));
209 static void s_frame
PARAMS ((int));
210 static void s_loc
PARAMS ((int));
211 static void s_mask
PARAMS ((char));
217 The following pseudo-ops from the Kane and Heinrich MIPS book
218 should be defined here, but are currently unsupported: .alias,
219 .galive, .gjaldef, .gjrlive, .livereg, .noalias.
221 The following pseudo-ops from the Kane and Heinrich MIPS book are
222 specific to the type of debugging information being generated, and
223 should be defined by the object format: .aent, .begin, .bend,
224 .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp,
227 The following pseudo-ops from the Kane and Heinrich MIPS book are
228 not MIPS CPU specific, but are also not specific to the object file
229 format. This file is probably the best place to define them, but
230 they are not currently supported: .asm0, .endr, .lab, .repeat,
231 .struct, .weakext. */
233 const pseudo_typeS md_pseudo_table
[] =
235 /* MIPS specific pseudo-ops. */
236 {"option", s_option
, 0},
237 {"set", s_mipsset
, 0},
238 {"rdata", s_change_sec
, 'r',},
239 {"sdata", s_change_sec
, 's',},
241 /* Relatively generic pseudo-ops that happen to be used on MIPS
243 {"asciiz", s_stringer
, 1},
244 {"bss", s_change_sec
, 'b'},
248 /* These pseudo-ops are defined in read.c, but must be overridden
249 here for one reason or another. */
250 {"align", s_align
, 0},
251 {"ascii", s_stringer
, 0},
252 {"asciz", s_stringer
, 1},
254 {"data", s_change_sec
, 'd'},
255 {"double", s_float_cons
, 'd'},
256 {"extern", s_extern
, 0},
257 {"float", s_float_cons
, 'f'},
258 {"space", s_mips_space
, 0},
259 {"text", s_change_sec
, 't'},
263 /* These pseudo-ops should be defined by the object file format.
264 However, ECOFF is the only format which currently defines them,
265 so we have versions here for a.out. */
267 {"end", s_mipsend
, 0},
270 {"fmask", s_ignore
, 'F'},
271 {"frame", s_ignore
, 0},
272 {"loc", s_ignore
, 0},
273 {"mask", s_ignore
, 'R'},
274 {"verstamp", s_ignore
, 0},
281 const relax_typeS md_relax_table
[] =
287 static char *expr_end
;
289 static expressionS imm_expr
;
290 static expressionS offset_expr
;
291 static bfd_reloc_code_real_type imm_reloc
;
292 static bfd_reloc_code_real_type offset_reloc
;
294 /* FIXME: This should be handled in a different way. */
295 extern int target_big_endian
;
298 * This function is called once, at assembler startup time. It should
299 * set up all the tables, etc. that the MD part of the assembler will need.
305 register const char *retval
= NULL
;
306 register unsigned int i
= 0;
310 if (strcmp (TARGET_CPU
, "mips") == 0)
312 else if (strcmp (TARGET_CPU
, "r6000") == 0
313 || strcmp (TARGET_CPU
, "mips2") == 0)
315 else if (strcmp (TARGET_CPU
, "mips64") == 0
316 || strcmp (TARGET_CPU
, "r4000") == 0
317 || strcmp (TARGET_CPU
, "mips3") == 0)
326 ok
= bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, 3000);
329 ok
= bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, 6000);
332 ok
= bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, 4000);
336 as_warn ("Could not set architecture and machine");
338 if ((op_hash
= hash_new ()) == NULL
)
340 as_fatal ("Virtual memory exhausted");
342 for (i
= 0; i
< NUMOPCODES
;)
344 const char *name
= mips_opcodes
[i
].name
;
346 retval
= hash_insert (op_hash
, name
, (PTR
) &mips_opcodes
[i
]);
349 fprintf (stderr
, "internal error: can't hash `%s': %s\n",
350 mips_opcodes
[i
].name
, retval
);
351 as_fatal ("Broken assembler. No assembly attempted.");
355 if (mips_opcodes
[i
].pinfo
!= INSN_MACRO
356 && ((mips_opcodes
[i
].match
& mips_opcodes
[i
].mask
)
357 != mips_opcodes
[i
].match
))
359 fprintf (stderr
, "internal error: bad opcode: `%s' \"%s\"\n",
360 mips_opcodes
[i
].name
, mips_opcodes
[i
].args
);
361 as_fatal ("Broken assembler. No assembly attempted.");
365 while ((i
< NUMOPCODES
) && !strcmp (mips_opcodes
[i
].name
, name
));
368 mips_no_prev_insn ();
370 /* set the default alignment for the text section (2**2) */
371 record_alignment (text_section
, 2);
373 /* FIXME: This should be handled in a different way. */
374 target_big_endian
= byte_order
== BIG_ENDIAN
;
377 bfd_set_gp_size (stdoutput
, g_switch_value
);
397 struct mips_cl_insn insn
;
399 imm_expr
.X_op
= O_absent
;
400 offset_expr
.X_op
= O_absent
;
402 mips_ip (str
, &insn
);
405 as_bad ("%s `%s'", insn_error
, str
);
408 if (insn
.insn_mo
->pinfo
== INSN_MACRO
)
414 if (imm_expr
.X_op
!= O_absent
)
415 append_insn (&insn
, &imm_expr
, imm_reloc
);
416 else if (offset_expr
.X_op
!= O_absent
)
417 append_insn (&insn
, &offset_expr
, offset_reloc
);
419 append_insn (&insn
, NULL
, BFD_RELOC_UNUSED
);
423 /* See whether instruction IP reads register REG. If FPR is non-zero,
424 REG is a floating point register. */
427 insn_uses_reg (ip
, reg
, fpr
)
428 struct mips_cl_insn
*ip
;
432 /* Don't report on general register 0, since it never changes. */
433 if (! fpr
&& reg
== 0)
438 /* If we are called with either $f0 or $f1, we must check $f0.
439 This is not optimal, because it will introduce an unnecessary
440 NOP between "lwc1 $f0" and "swc1 $f1". To fix this we would
441 need to distinguish reading both $f0 and $f1 or just one of
442 them. Note that we don't have to check the other way,
443 because there is no instruction that sets both $f0 and $f1
444 and requires a delay. */
445 if ((ip
->insn_mo
->pinfo
& INSN_READ_FPR_S
)
446 && (((ip
->insn_opcode
>> OP_SH_FS
) & OP_MASK_FS
)
447 == (reg
&~ (unsigned) 1)))
449 if ((ip
->insn_mo
->pinfo
& INSN_READ_FPR_T
)
450 && (((ip
->insn_opcode
>> OP_SH_FT
) & OP_MASK_FT
)
451 == (reg
&~ (unsigned) 1)))
456 if ((ip
->insn_mo
->pinfo
& INSN_READ_GPR_S
)
457 && ((ip
->insn_opcode
>> OP_SH_RS
) & OP_MASK_RS
) == reg
)
459 if ((ip
->insn_mo
->pinfo
& INSN_READ_GPR_T
)
460 && ((ip
->insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
) == reg
)
467 #define ALIGN_ERR "Attempt to assemble instruction onto non word boundary."
468 #define ALIGN_ERR2 "GAS doesn't do implicit alignment; use .align directive."
472 * Output an instruction.
475 append_insn (ip
, address_expr
, reloc_type
)
476 struct mips_cl_insn
*ip
;
477 expressionS
*address_expr
;
478 bfd_reloc_code_real_type reloc_type
;
484 if (! mips_noreorder
)
486 /* If the previous insn required any delay slots, see if we need
487 to insert a NOP or two. There are eight kinds of possible
488 hazards, of which an instruction can have at most one type.
489 (1) a load from memory delay
490 (2) a load from a coprocessor delay
491 (3) an unconditional branch delay
492 (4) a conditional branch delay
493 (5) a move to coprocessor register delay
494 (6) a load coprocessor register from memory delay
495 (7) a coprocessor condition code delay
496 (8) a HI/LO special register delay
498 There are a lot of optimizations we could do that we don't.
499 In particular, we do not, in general, reorder instructions.
500 If you use gcc with optimization, it will reorder
501 instructions and generally do much more optimization then we
502 do here; repeating all that work in the assembler would only
503 benefit hand written assembly code, and does not seem worth
506 /* This is how a NOP is emitted. */
507 #define emit_nop() md_number_to_chars (frag_more (4), 0, 4)
509 /* The previous insn might require a delay slot, depending upon
510 the contents of the current insn. */
511 if ((prev_insn
.insn_mo
->pinfo
& INSN_LOAD_COPROC_DELAY
)
513 && (prev_insn
.insn_mo
->pinfo
& INSN_LOAD_MEMORY_DELAY
)))
515 /* A load from a coprocessor or from memory. All load
516 delays delay the use of general register rt for one
517 instruction on the r3000. The r6000 and r4000 use
519 know (prev_insn
.insn_mo
->pinfo
& INSN_WRITE_GPR_T
);
520 if (mips_optimize
== 0
521 || insn_uses_reg (ip
,
522 ((prev_insn
.insn_opcode
>> OP_SH_RT
)
527 else if ((prev_insn
.insn_mo
->pinfo
& INSN_COPROC_MOVE_DELAY
)
529 && (prev_insn
.insn_mo
->pinfo
& INSN_COPROC_MEMORY_DELAY
)))
531 /* A generic coprocessor delay. The previous instruction
532 modified a coprocessor general or control register. If
533 it modified a control register, we need to avoid any
534 coprocessor instruction (this is probably not always
535 required, but it sometimes is). If it modified a general
536 register, we avoid using that register.
538 On the r6000 and r4000 loading a coprocessor register
539 from memory is interlocked, and does not require a delay.
541 This case is not handled very well. There is no special
542 knowledge of CP0 handling, and the coprocessors other
543 than the floating point unit are not distinguished at
545 if (prev_insn
.insn_mo
->pinfo
& INSN_WRITE_FPR_T
)
547 if (mips_optimize
== 0
548 || insn_uses_reg (ip
,
549 ((prev_insn
.insn_opcode
>> OP_SH_FT
)
554 else if (prev_insn
.insn_mo
->pinfo
& INSN_WRITE_FPR_S
)
556 if (mips_optimize
== 0
557 || insn_uses_reg (ip
,
558 ((prev_insn
.insn_opcode
>> OP_SH_FS
)
565 /* We don't know exactly what the previous instruction
566 does. If the current instruction uses a coprocessor
567 register, we must insert a NOP. If previous
568 instruction may set the condition codes, and the
569 current instruction uses them, we must insert two
571 if (mips_optimize
== 0
572 || ((prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
)
573 && (ip
->insn_mo
->pinfo
& INSN_READ_COND_CODE
)))
575 else if (ip
->insn_mo
->pinfo
& INSN_COP
)
579 else if (prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
)
581 /* The previous instruction sets the coprocessor condition
582 codes, but does not require a general coprocessor delay
583 (this means it is a floating point comparison
584 instruction). If this instruction uses the condition
585 codes, we need to insert a single NOP. */
586 if (mips_optimize
== 0
587 || ip
->insn_mo
->pinfo
& INSN_READ_COND_CODE
)
590 else if (prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
)
592 /* The previous instruction reads the LO register; if the
593 current instruction writes to the LO register, we must
595 if (mips_optimize
== 0
596 || ip
->insn_mo
->pinfo
& INSN_WRITE_LO
)
599 else if (prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
601 /* The previous instruction reads the HI register; if the
602 current instruction writes to the HI register, we must
604 if (mips_optimize
== 0
605 || ip
->insn_mo
->pinfo
& INSN_WRITE_HI
)
609 /* There are two cases which require two intervening
610 instructions: 1) setting the condition codes using a move to
611 coprocessor instruction which requires a general coprocessor
612 delay and then reading the condition codes 2) reading the HI
613 or LO register and then writing to it. If we are not already
614 emitting a NOP instruction, we must check for these cases
615 compared to the instruction previous to the previous
618 && (((prev_prev_insn
.insn_mo
->pinfo
& INSN_COPROC_MOVE_DELAY
)
619 && (prev_prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
)
620 && (ip
->insn_mo
->pinfo
& INSN_READ_COND_CODE
))
621 || ((prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
)
622 && (ip
->insn_mo
->pinfo
& INSN_WRITE_LO
))
623 || ((prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
624 && (ip
->insn_mo
->pinfo
& INSN_WRITE_HI
))))
627 /* Now emit the right number of NOP instructions. */
633 if (insn_label
!= NULL
)
635 assert (S_GET_SEGMENT (insn_label
) == now_seg
);
636 insn_label
->sy_frag
= frag_now
;
637 S_SET_VALUE (insn_label
, (valueT
) frag_now_fix ());
644 /* This is testing the address of the frag, not the alignment of
645 the instruction in the current section. */
653 if (address_expr
!= NULL
)
655 if (address_expr
->X_op
== O_constant
)
660 ip
->insn_opcode
|= address_expr
->X_add_number
;
664 ip
->insn_opcode
|= address_expr
->X_add_number
& 0xffff;
667 case BFD_RELOC_MIPS_JMP
:
668 case BFD_RELOC_16_PCREL_S2
:
677 assert (reloc_type
!= BFD_RELOC_UNUSED
);
679 fixp
= fix_new_exp (frag_now
, f
- frag_now
->fr_literal
, 4,
681 reloc_type
== BFD_RELOC_16_PCREL_S2
,
686 md_number_to_chars (f
, ip
->insn_opcode
, 4);
688 if (! mips_noreorder
)
690 /* Filling the branch delay slot is more complex. We try to
691 switch the branch with the previous instruction, which we can
692 do if the previous instruction does not set up a condition
693 that the branch tests and if the branch is not itself the
694 target of any branch. */
695 if ((ip
->insn_mo
->pinfo
& INSN_UNCOND_BRANCH_DELAY
)
696 || (ip
->insn_mo
->pinfo
& INSN_COND_BRANCH_DELAY
))
698 if (mips_optimize
< 2
699 /* If we have seen .set nobopt, don't optimize. */
701 /* If we have seen .set volatile or .set nomove, don't
704 /* If we had to emit any NOP instructions, then we
705 already know we can not swap. */
707 /* If we don't even know the previous insn, we can not
710 /* If the previous insn is already in a branch delay
711 slot, then we can not swap. */
712 || prev_insn_is_delay_slot
713 /* If the previous previous insn was in a .set
714 noreorder, we can't swap. Actually, the MIPS
715 assembler will swap in this situation. However, gcc
716 configured -with-gnu-as will generate code like
722 in which we can not swap the bne and INSN. If gcc is
723 not configured -with-gnu-as, it does not output the
724 .set pseudo-ops. We don't have to check
725 prev_insn_unreordered, because prev_insn_valid will
726 be 0 in that case. We don't want to use
727 prev_prev_insn_valid, because we do want to be able
728 to swap at the start of a function. */
729 || prev_prev_insn_unreordered
730 /* If the branch is itself the target of a branch, we
731 can not swap. We cheat on this; all we check for is
732 whether there is a label on this instruction. If
733 there are any branches to anything other than a
734 label, users must use .set noreorder. */
735 || insn_label
!= NULL
736 /* If the branch reads the condition codes, we don't
737 even try to swap, because in the sequence
742 we can not swap, and I don't feel like handling that
744 || (ip
->insn_mo
->pinfo
& INSN_READ_COND_CODE
)
745 /* We can not swap with an instruction that requires a
746 delay slot, becase the target of the branch might
747 interfere with that instruction. */
748 || (prev_insn
.insn_mo
->pinfo
749 & (INSN_LOAD_COPROC_DELAY
750 | INSN_COPROC_MOVE_DELAY
751 | INSN_WRITE_COND_CODE
755 && (prev_insn
.insn_mo
->pinfo
756 & (INSN_LOAD_MEMORY_DELAY
757 | INSN_COPROC_MEMORY_DELAY
)))
758 /* We can not swap with a branch instruction. */
759 || (prev_insn
.insn_mo
->pinfo
760 & (INSN_UNCOND_BRANCH_DELAY
761 | INSN_COND_BRANCH_DELAY
762 | INSN_COND_BRANCH_LIKELY
))
763 /* We do not swap with a trap instruction, since it
764 complicates trap handlers to have the trap
765 instruction be in a delay slot. */
766 || (prev_insn
.insn_mo
->pinfo
& INSN_TRAP
)
767 /* If the branch reads a register that the previous
768 instruction sets, we can not swap. */
769 || ((prev_insn
.insn_mo
->pinfo
& INSN_WRITE_GPR_T
)
770 && insn_uses_reg (ip
,
771 ((prev_insn
.insn_opcode
>> OP_SH_RT
)
774 || ((prev_insn
.insn_mo
->pinfo
& INSN_WRITE_GPR_D
)
775 && insn_uses_reg (ip
,
776 ((prev_insn
.insn_opcode
>> OP_SH_RD
)
779 /* If the branch writes a register that the previous
780 instruction sets, we can not swap (we know that
781 branches write only to RD or to $31). */
782 || ((prev_insn
.insn_mo
->pinfo
& INSN_WRITE_GPR_T
)
783 && (((ip
->insn_mo
->pinfo
& INSN_WRITE_GPR_D
)
784 && (((prev_insn
.insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
)
785 == ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)))
786 || ((ip
->insn_mo
->pinfo
& INSN_WRITE_GPR_31
)
787 && (((prev_insn
.insn_opcode
>> OP_SH_RT
)
790 || ((prev_insn
.insn_mo
->pinfo
& INSN_WRITE_GPR_D
)
791 && (((ip
->insn_mo
->pinfo
& INSN_WRITE_GPR_D
)
792 && (((prev_insn
.insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)
793 == ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)))
794 || ((ip
->insn_mo
->pinfo
& INSN_WRITE_GPR_31
)
795 && (((prev_insn
.insn_opcode
>> OP_SH_RD
)
798 /* If the branch writes a register that the previous
799 instruction reads, we can not swap (we know that
800 branches only write to RD or to $31). */
801 || ((ip
->insn_mo
->pinfo
& INSN_WRITE_GPR_D
)
802 && insn_uses_reg (&prev_insn
,
803 ((ip
->insn_opcode
>> OP_SH_RD
)
806 || ((ip
->insn_mo
->pinfo
& INSN_WRITE_GPR_31
)
807 && insn_uses_reg (&prev_insn
, 31, 0))
808 /* If the previous previous instruction has a load
809 delay, and sets a register that the branch reads, we
811 || (((prev_prev_insn
.insn_mo
->pinfo
& INSN_LOAD_COPROC_DELAY
)
813 && (prev_prev_insn
.insn_mo
->pinfo
814 & INSN_LOAD_MEMORY_DELAY
)))
815 && insn_uses_reg (ip
,
816 ((prev_prev_insn
.insn_opcode
>> OP_SH_RT
)
820 /* We could do even better for unconditional branches to
821 portions of this object file; we could pick up the
822 instruction at the destination, put it in the delay
823 slot, and bump the destination address. */
825 /* Update the previous insn information. */
826 prev_prev_insn
= *ip
;
827 prev_insn
.insn_mo
= &dummy_opcode
;
834 /* It looks like we can actually do the swap. */
835 prev_f
= prev_insn_frag
->fr_literal
+ prev_insn_where
;
836 memcpy (temp
, prev_f
, 4);
837 memcpy (prev_f
, f
, 4);
841 prev_insn_fixp
->fx_frag
= frag_now
;
842 prev_insn_fixp
->fx_where
= f
- frag_now
->fr_literal
;
846 fixp
->fx_frag
= prev_insn_frag
;
847 fixp
->fx_where
= prev_insn_where
;
849 /* Update the previous insn information; leave prev_insn
851 prev_prev_insn
= *ip
;
853 prev_insn_is_delay_slot
= 1;
855 /* If that was an unconditional branch, forget the previous
857 if (ip
->insn_mo
->pinfo
& INSN_UNCOND_BRANCH_DELAY
)
859 prev_prev_insn
.insn_mo
= &dummy_opcode
;
860 prev_insn
.insn_mo
= &dummy_opcode
;
863 else if (ip
->insn_mo
->pinfo
& INSN_COND_BRANCH_LIKELY
)
865 /* We don't yet optimize a branch likely. What we should do
866 is look at the target, copy the instruction found there
867 into the delay slot, and increment the branch to jump to
868 the next instruction. */
870 /* Update the previous insn information. */
871 prev_prev_insn
= *ip
;
872 prev_insn
.insn_mo
= &dummy_opcode
;
876 /* Update the previous insn information. */
878 prev_prev_insn
.insn_mo
= &dummy_opcode
;
880 prev_prev_insn
= prev_insn
;
883 /* Any time we see a branch, we always fill the delay slot
884 immediately; since this insn is not a branch, we know it
885 is not in a delay slot. */
886 prev_insn_is_delay_slot
= 0;
889 prev_prev_insn_unreordered
= prev_insn_unreordered
;
890 prev_insn_unreordered
= 0;
891 prev_insn_frag
= frag_now
;
892 prev_insn_where
= f
- frag_now
->fr_literal
;
893 prev_insn_fixp
= fixp
;
897 /* We just output an insn, so the next one doesn't have a label. */
901 /* This function forgets that there was any previous instruction or
907 prev_insn
.insn_mo
= &dummy_opcode
;
908 prev_prev_insn
.insn_mo
= &dummy_opcode
;
910 prev_insn_is_delay_slot
= 0;
911 prev_insn_unreordered
= 0;
912 prev_prev_insn_unreordered
= 0;
916 /* This function must be called whenever we turn on noreorder or emit
917 something other than instructions. It inserts any NOPS which might
918 be needed by the previous instruction, and clears the information
919 kept for the previous instructions. */
924 if (! mips_noreorder
)
929 if ((prev_insn
.insn_mo
->pinfo
930 & (INSN_LOAD_COPROC_DELAY
931 | INSN_COPROC_MOVE_DELAY
932 | INSN_WRITE_COND_CODE
936 && (prev_insn
.insn_mo
->pinfo
937 & (INSN_LOAD_MEMORY_DELAY
938 | INSN_COPROC_MEMORY_DELAY
))))
941 if ((prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
)
942 || (prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
943 || (prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
))
946 else if ((prev_prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
)
947 || (prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
948 || (prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
))
953 if (insn_label
!= NULL
)
955 assert (S_GET_SEGMENT (insn_label
) == now_seg
);
956 insn_label
->sy_frag
= frag_now
;
957 S_SET_VALUE (insn_label
, (valueT
) frag_now_fix ());
960 mips_no_prev_insn ();
964 /* Return 1 if an expression can be accessed via the GP register. */
975 sym
= ep
->X_add_symbol
;
976 if (sym
== (symbolS
*) NULL
977 || ep
->X_op_symbol
!= (symbolS
*) NULL
)
980 /* Certain symbols can not be referenced off the GP, although it
981 appears as though they can. */
982 symname
= S_GET_NAME (sym
);
983 if (symname
!= (const char *) NULL
984 && (strcmp (symname
, "eprol") == 0
985 || strcmp (symname
, "etext") == 0
986 || strcmp (symname
, "_gp") == 0
987 || strcmp (symname
, "edata") == 0
988 || strcmp (symname
, "_fbss") == 0
989 || strcmp (symname
, "_fdata") == 0
990 || strcmp (symname
, "_ftext") == 0
991 || strcmp (symname
, "end") == 0))
993 if (! S_IS_DEFINED (sym
)
994 && S_GET_VALUE (sym
) != 0
995 && S_GET_VALUE (sym
) <= g_switch_value
)
997 segname
= segment_name (S_GET_SEGMENT (ep
->X_add_symbol
));
998 return (strcmp (segname
, ".sdata") == 0
999 || strcmp (segname
, ".sbss") == 0
1000 || strcmp (segname
, ".lit8") == 0
1001 || strcmp (segname
, ".lit4") == 0);
1002 #else /* ! defined (GPOPT) */
1003 /* We are not optimizing for the GP register. */
1005 #endif /* ! defined (GPOPT) */
1008 /* Build an instruction created by a macro expansion. This is passed
1009 a pointer to the count of instructions created so far, an
1010 expression, the name of the instruction to build, an operand format
1011 string, and corresponding arguments. */
1015 macro_build (int *counter
,
1020 #else /* ! defined (NO_STDARG) */
1022 macro_build (counter
, ep
, name
, fmt
, va_alist
)
1028 #endif /* ! defined (NO_STDARG) */
1030 struct mips_cl_insn insn
;
1031 bfd_reloc_code_real_type r
;
1035 va_start (args
, fmt
);
1041 * If the macro is about to expand into a second instruction,
1042 * print a warning if needed. We need to pass ip as a parameter
1043 * to generate a better warning message here...
1045 if (mips_warn_about_macros
&& *counter
== 1)
1046 as_warn ("Macro instruction expanded into multiple instructions");
1048 *counter
+= 1; /* bump instruction counter */
1050 r
= BFD_RELOC_UNUSED
;
1051 insn
.insn_mo
= (struct mips_opcode
*) hash_find (op_hash
, name
);
1052 assert (insn
.insn_mo
);
1053 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
1055 while (strcmp (fmt
, insn
.insn_mo
->args
) != 0)
1058 assert (insn
.insn_mo
->name
);
1059 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
1061 assert (insn
.insn_mo
->pinfo
!= INSN_MACRO
);
1062 insn
.insn_opcode
= insn
.insn_mo
->match
;
1078 insn
.insn_opcode
|= va_arg (args
, int) << 16;
1084 insn
.insn_opcode
|= va_arg (args
, int) << 16;
1089 insn
.insn_opcode
|= va_arg (args
, int) << 11;
1094 insn
.insn_opcode
|= va_arg (args
, int) << 11;
1101 insn
.insn_opcode
|= va_arg (args
, int) << 6;
1105 insn
.insn_opcode
|= va_arg (args
, int) << 6;
1109 insn
.insn_opcode
|= va_arg (args
, int) << 6;
1116 insn
.insn_opcode
|= va_arg (args
, int) << 21;
1126 assert (ep
!= NULL
&& ep
->X_op
== O_constant
);
1127 insn
.insn_opcode
|= (ep
->X_add_number
>> 16) & 0xffff;
1132 assert (ep
!= NULL
);
1134 * This allows macro() to pass an immediate expression for
1135 * creating short branches without creating a symbol.
1136 * Note that the expression still might come from the assembly
1137 * input, in which case the value is not checked for range nor
1138 * is a relocation entry generated (yuck).
1140 if (ep
->X_op
== O_constant
)
1142 insn
.insn_opcode
|= (ep
->X_add_number
>> 2) & 0xffff;
1146 r
= BFD_RELOC_16_PCREL_S2
;
1155 assert (r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
1157 /* Use GP relative addressing if possible. */
1158 if (r
== BFD_RELOC_LO16
1159 && gp_reference (ep
))
1160 r
= BFD_RELOC_MIPS_GPREL
;
1162 append_insn (&insn
, ep
, r
);
1166 * Generate a "lui" instruction.
1169 macro_build_lui (counter
, ep
, regnum
)
1174 expressionS high_expr
;
1175 struct mips_cl_insn insn
;
1176 bfd_reloc_code_real_type r
;
1177 CONST
char *name
= "lui";
1178 CONST
char *fmt
= "t,u";
1182 if (high_expr
.X_op
== O_constant
)
1184 /* we can compute the instruction now without a relocation entry */
1185 if (high_expr
.X_add_number
& 0x8000)
1186 high_expr
.X_add_number
+= 0x10000;
1187 high_expr
.X_add_number
=
1188 ((unsigned long) high_expr
.X_add_number
>> 16) & 0xffff;
1189 r
= BFD_RELOC_UNUSED
;
1192 r
= BFD_RELOC_HI16_S
;
1195 * If the macro is about to expand into a second instruction,
1196 * print a warning if needed. We need to pass ip as a parameter
1197 * to generate a better warning message here...
1199 if (mips_warn_about_macros
&& *counter
== 1)
1200 as_warn ("Macro instruction expanded into multiple instructions");
1202 *counter
+= 1; /* bump instruction counter */
1204 insn
.insn_mo
= (struct mips_opcode
*) hash_find (op_hash
, name
);
1205 assert (insn
.insn_mo
);
1206 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
1207 assert (strcmp (fmt
, insn
.insn_mo
->args
) == 0);
1209 insn
.insn_opcode
= insn
.insn_mo
->match
| (regnum
<< 16);
1210 if (r
== BFD_RELOC_UNUSED
)
1212 insn
.insn_opcode
|= high_expr
.X_add_number
;
1213 append_insn (&insn
, NULL
, r
);
1216 append_insn (&insn
, &high_expr
, r
);
1220 * Generates code to set the $at register to true (one)
1221 * if reg is less than the immediate expression.
1224 set_at (counter
, reg
, unsignedp
)
1229 if (imm_expr
.X_add_number
>= -0x8000 && imm_expr
.X_add_number
< 0x8000)
1230 macro_build (counter
, &imm_expr
,
1231 unsignedp
? "sltiu" : "slti",
1235 load_register (counter
, AT
, &imm_expr
);
1236 macro_build (counter
, NULL
,
1237 unsignedp
? "sltu" : "slt",
1238 "d,v,t", AT
, reg
, AT
);
1242 /* Warn if an expression is not a constant. */
1245 check_absolute_expr (ip
, ex
)
1246 struct mips_cl_insn
*ip
;
1249 if (ex
->X_op
!= O_constant
)
1250 as_warn ("Instruction %s requires absolute expression", ip
->insn_mo
->name
);
1254 * This routine generates the least number of instructions neccessary to load
1255 * an absolute expression value into a register.
1258 load_register (counter
, reg
, ep
)
1263 assert (ep
->X_op
== O_constant
);
1264 if (ep
->X_add_number
>= -0x8000 && ep
->X_add_number
< 0x8000)
1265 macro_build (counter
, ep
,
1266 mips_isa
< 3 ? "addiu" : "daddiu",
1268 else if (ep
->X_add_number
>= 0 && ep
->X_add_number
< 0x10000)
1269 macro_build (counter
, ep
, "ori", "t,r,i", reg
, 0);
1270 else if ((ep
->X_add_number
&~ (offsetT
) 0x7fffffff) == 0
1271 || ((ep
->X_add_number
&~ (offsetT
) 0x7fffffff)
1272 == ~ (offsetT
) 0x7fffffff))
1274 macro_build (counter
, ep
, "lui", "t,u", reg
);
1275 if ((ep
->X_add_number
& 0xffff) != 0)
1276 macro_build (counter
, ep
, "ori", "t,r,i", reg
, reg
);
1278 else if (mips_isa
< 3)
1280 as_bad ("Number larger than 32 bits");
1281 macro_build (counter
, ep
, "addiu", "t,r,j", reg
, 0);
1286 expressionS hi32
, lo32
;
1290 hi32
.X_add_number
>>= shift
;
1291 hi32
.X_add_number
&= 0xffffffff;
1292 if ((hi32
.X_add_number
& 0x80000000) != 0)
1293 hi32
.X_add_number
|= ~ (offsetT
) 0xffffffff;
1294 load_register (counter
, reg
, &hi32
);
1296 lo32
.X_add_number
&= 0xffffffff;
1297 if ((lo32
.X_add_number
& 0xffff0000) == 0)
1298 macro_build (counter
, NULL
, "dsll32", "d,w,<", reg
, reg
, 0);
1303 macro_build (counter
, NULL
, "dsll", "d,w,<", reg
, reg
, 16);
1305 mid16
.X_add_number
>>= 16;
1306 macro_build (counter
, &mid16
, "ori", "t,r,i", reg
, reg
);
1307 macro_build (counter
, NULL
, "dsll", "d,w,<", reg
, reg
, 16);
1309 if ((lo32
.X_add_number
& 0xffff) != 0)
1310 macro_build (counter
, &lo32
, "ori", "t,r,i", reg
, reg
);
1316 * This routine implements the seemingly endless macro or synthesized
1317 * instructions and addressing modes in the mips assembly language. Many
1318 * of these macros are simple and are similar to each other. These could
1319 * probably be handled by some kind of table or grammer aproach instead of
1320 * this verbose method. Others are not simple macros but are more like
1321 * optimizing code generation.
1322 * One interesting optimization is when several store macros appear
1323 * consecutivly that would load AT with the upper half of the same address.
1324 * The ensuing load upper instructions are ommited. This implies some kind
1325 * of global optimization. We currently only optimize within a single macro.
1326 * For many of the load and store macros if the address is specified as a
1327 * constant expression in the first 64k of memory (ie ld $2,0x4000c) we
1328 * first load register 'at' with zero and use it as the base register. The
1329 * mips assembler simply uses register $zero. Just one tiny optimization
1334 struct mips_cl_insn
*ip
;
1336 register int treg
, sreg
, dreg
, breg
;
1350 treg
= (ip
->insn_opcode
>> 16) & 0x1f;
1351 dreg
= (ip
->insn_opcode
>> 11) & 0x1f;
1352 sreg
= breg
= (ip
->insn_opcode
>> 21) & 0x1f;
1353 mask
= ip
->insn_mo
->mask
;
1355 expr1
.X_op
= O_constant
;
1356 expr1
.X_op_symbol
= NULL
;
1357 expr1
.X_add_symbol
= NULL
;
1358 expr1
.X_add_number
= 1;
1370 mips_emit_delays ();
1373 expr1
.X_add_number
= 8;
1374 macro_build (&icnt
, &expr1
, "bgez", "s,p", sreg
);
1376 macro_build (&icnt
, NULL
, "nop", "", 0);
1378 macro_build (&icnt
, NULL
, "move", "d,s", dreg
, sreg
, 0);
1379 macro_build (&icnt
, NULL
,
1380 dbl
? "dsub" : "sub",
1381 "d,v,t", dreg
, 0, sreg
);
1404 if (imm_expr
.X_add_number
>= -0x8000 && imm_expr
.X_add_number
< 0x8000)
1406 macro_build (&icnt
, &imm_expr
, s
, "t,r,j", treg
, sreg
);
1409 load_register (&icnt
, AT
, &imm_expr
);
1410 macro_build (&icnt
, NULL
, s2
, "d,v,t", treg
, sreg
, AT
);
1429 if (imm_expr
.X_add_number
>= 0 && imm_expr
.X_add_number
< 0x10000)
1431 if (mask
!= M_NOR_I
)
1432 macro_build (&icnt
, &imm_expr
, s
, "t,r,i", treg
, sreg
);
1435 macro_build (&icnt
, &imm_expr
, "ori", "t,r,i", treg
, sreg
);
1436 macro_build (&icnt
, &imm_expr
, "nor", "d,v,t", treg
, treg
, 0);
1441 load_register (&icnt
, AT
, &imm_expr
);
1442 macro_build (&icnt
, NULL
, s2
, "d,v,t", treg
, sreg
, AT
);
1459 if (imm_expr
.X_add_number
== 0)
1461 macro_build (&icnt
, &offset_expr
, s
, "s,t,p", sreg
, 0);
1464 load_register (&icnt
, AT
, &imm_expr
);
1465 macro_build (&icnt
, &offset_expr
, s
, "s,t,p", sreg
, AT
);
1473 macro_build (&icnt
, &offset_expr
,
1474 likely
? "bgezl" : "bgez",
1480 macro_build (&icnt
, &offset_expr
,
1481 likely
? "blezl" : "blez",
1485 macro_build (&icnt
, NULL
, "slt", "d,v,t", AT
, sreg
, treg
);
1486 macro_build (&icnt
, &offset_expr
,
1487 likely
? "beql" : "beq",
1494 /* check for > max integer */
1495 maxnum
= 0x7fffffff;
1503 if (imm_expr
.X_add_number
>= maxnum
)
1506 /* result is always false */
1509 as_warn ("Branch %s is always false (nop)", ip
->insn_mo
->name
);
1510 macro_build (&icnt
, NULL
, "nop", "", 0);
1514 as_warn ("Branch likely %s is always false", ip
->insn_mo
->name
);
1515 macro_build (&icnt
, &offset_expr
, "bnel", "s,t,p", 0, 0);
1519 imm_expr
.X_add_number
++;
1523 if (mask
== M_BGEL_I
)
1525 if (imm_expr
.X_add_number
== 0)
1527 macro_build (&icnt
, &offset_expr
,
1528 likely
? "bgezl" : "bgez",
1532 if (imm_expr
.X_add_number
== 1)
1534 macro_build (&icnt
, &offset_expr
,
1535 likely
? "bgtzl" : "bgtz",
1539 maxnum
= 0x7fffffff;
1547 maxnum
= - maxnum
- 1;
1548 if (imm_expr
.X_add_number
<= maxnum
)
1551 /* result is always true */
1552 as_warn ("Branch %s is always true", ip
->insn_mo
->name
);
1553 macro_build (&icnt
, &offset_expr
, "b", "p");
1556 set_at (&icnt
, sreg
, 0);
1557 macro_build (&icnt
, &offset_expr
,
1558 likely
? "beql" : "beq",
1569 macro_build (&icnt
, &offset_expr
,
1570 likely
? "beql" : "beq",
1574 macro_build (&icnt
, NULL
, "sltu", "d,v,t", AT
, sreg
, treg
);
1575 macro_build (&icnt
, &offset_expr
,
1576 likely
? "beql" : "beq",
1583 if (sreg
== 0 || imm_expr
.X_add_number
== -1)
1585 imm_expr
.X_add_number
++;
1589 if (mask
== M_BGEUL_I
)
1591 if (imm_expr
.X_add_number
== 0)
1593 if (imm_expr
.X_add_number
== 1)
1595 macro_build (&icnt
, &offset_expr
,
1596 likely
? "bnel" : "bne",
1600 set_at (&icnt
, sreg
, 1);
1601 macro_build (&icnt
, &offset_expr
,
1602 likely
? "beql" : "beq",
1611 macro_build (&icnt
, &offset_expr
,
1612 likely
? "bgtzl" : "bgtz",
1618 macro_build (&icnt
, &offset_expr
,
1619 likely
? "bltzl" : "bltz",
1623 macro_build (&icnt
, NULL
, "slt", "d,v,t", AT
, treg
, sreg
);
1624 macro_build (&icnt
, &offset_expr
,
1625 likely
? "bnel" : "bne",
1634 macro_build (&icnt
, &offset_expr
,
1635 likely
? "bnel" : "bne",
1641 macro_build (&icnt
, NULL
, "sltu", "d,v,t", AT
, treg
, sreg
);
1642 macro_build (&icnt
, &offset_expr
,
1643 likely
? "bnel" : "bne",
1652 macro_build (&icnt
, &offset_expr
,
1653 likely
? "blezl" : "blez",
1659 macro_build (&icnt
, &offset_expr
,
1660 likely
? "bgezl" : "bgez",
1664 macro_build (&icnt
, NULL
, "slt", "d,v,t", AT
, treg
, sreg
);
1665 macro_build (&icnt
, &offset_expr
,
1666 likely
? "beql" : "beq",
1673 maxnum
= 0x7fffffff;
1681 if (imm_expr
.X_add_number
>= maxnum
)
1683 imm_expr
.X_add_number
++;
1687 if (mask
== M_BLTL_I
)
1689 if (imm_expr
.X_add_number
== 0)
1691 macro_build (&icnt
, &offset_expr
,
1692 likely
? "bltzl" : "bltz",
1696 if (imm_expr
.X_add_number
== 1)
1698 macro_build (&icnt
, &offset_expr
,
1699 likely
? "blezl" : "blez",
1703 set_at (&icnt
, sreg
, 0);
1704 macro_build (&icnt
, &offset_expr
,
1705 likely
? "bnel" : "bne",
1714 macro_build (&icnt
, &offset_expr
,
1715 likely
? "beql" : "beq",
1721 macro_build (&icnt
, NULL
, "sltu", "d,v,t", AT
, treg
, sreg
);
1722 macro_build (&icnt
, &offset_expr
,
1723 likely
? "beql" : "beq",
1730 if (sreg
== 0 || imm_expr
.X_add_number
== -1)
1732 imm_expr
.X_add_number
++;
1736 if (mask
== M_BLTUL_I
)
1738 if (imm_expr
.X_add_number
== 0)
1740 if (imm_expr
.X_add_number
== 1)
1742 macro_build (&icnt
, &offset_expr
,
1743 likely
? "beql" : "beq",
1747 set_at (&icnt
, sreg
, 1);
1748 macro_build (&icnt
, &offset_expr
,
1749 likely
? "bnel" : "bne",
1758 macro_build (&icnt
, &offset_expr
,
1759 likely
? "bltzl" : "bltz",
1765 macro_build (&icnt
, &offset_expr
,
1766 likely
? "bgtzl" : "bgtz",
1770 macro_build (&icnt
, NULL
, "slt", "d,v,t", AT
, sreg
, treg
);
1771 macro_build (&icnt
, &offset_expr
,
1772 likely
? "bnel" : "bne",
1783 macro_build (&icnt
, &offset_expr
,
1784 likely
? "bnel" : "bne",
1788 macro_build (&icnt
, NULL
, "sltu", "d,v,t", AT
, sreg
, treg
);
1789 macro_build (&icnt
, &offset_expr
,
1790 likely
? "bnel" : "bne",
1806 as_warn ("Divide by zero.");
1807 macro_build (&icnt
, NULL
, "break", "c", 7);
1811 mips_emit_delays ();
1813 macro_build (&icnt
, NULL
,
1814 dbl
? "ddiv" : "div",
1815 "z,s,t", sreg
, treg
);
1816 expr1
.X_add_number
= 8;
1817 macro_build (&icnt
, &expr1
, "bne", "s,t,p", treg
, 0);
1818 macro_build (&icnt
, NULL
, "nop", "", 0);
1819 macro_build (&icnt
, NULL
, "break", "c", 7);
1820 expr1
.X_add_number
= -1;
1821 macro_build (&icnt
, &expr1
,
1822 dbl
? "daddiu" : "addiu",
1824 expr1
.X_add_number
= dbl
? 20 : 16;
1825 macro_build (&icnt
, &expr1
, "bne", "s,t,p", treg
, AT
);
1828 expr1
.X_add_number
= 1;
1829 macro_build (&icnt
, &expr1
, "daddiu", "t,r,j", AT
, 0);
1830 macro_build (&icnt
, NULL
, "dsll32", "d,w,<", AT
, AT
, 31);
1834 expr1
.X_add_number
= 0x80000000;
1835 macro_build (&icnt
, &expr1
, "lui", "t,u", AT
);
1837 expr1
.X_add_number
= 8;
1838 macro_build (&icnt
, &expr1
, "bne", "s,t,p", sreg
, AT
);
1839 macro_build (&icnt
, NULL
, "nop", "", 0);
1840 macro_build (&icnt
, NULL
, "break", "c", 6);
1842 macro_build (&icnt
, NULL
, s
, "d", dreg
);
1881 if (imm_expr
.X_add_number
== 0)
1883 as_warn ("Divide by zero.");
1884 macro_build (&icnt
, NULL
, "break", "c", 7);
1887 if (imm_expr
.X_add_number
== 1)
1889 if (strcmp (s2
, "mflo") == 0)
1890 macro_build (&icnt
, NULL
, "move", "d,s", dreg
, sreg
);
1892 macro_build (&icnt
, NULL
, "move", "d,s", dreg
, 0);
1895 if (imm_expr
.X_add_number
== -1
1896 && s
[strlen (s
) - 1] != 'u')
1898 if (strcmp (s2
, "mflo") == 0)
1901 macro_build (&icnt
, NULL
, "dneg", "d,w", dreg
, sreg
);
1903 macro_build (&icnt
, NULL
, "neg", "d,w", dreg
, sreg
);
1906 macro_build (&icnt
, NULL
, "move", "d,s", dreg
, 0);
1910 load_register (&icnt
, AT
, &imm_expr
);
1911 macro_build (&icnt
, NULL
, s
, "z,s,t", sreg
, AT
);
1912 macro_build (&icnt
, NULL
, s2
, "d", dreg
);
1931 mips_emit_delays ();
1933 macro_build (&icnt
, NULL
, s
, "z,s,t", sreg
, treg
);
1934 expr1
.X_add_number
= 8;
1935 macro_build (&icnt
, &expr1
, "bne", "s,t,p", treg
, 0);
1936 macro_build (&icnt
, NULL
, "nop", "", 0);
1937 macro_build (&icnt
, NULL
, "break", "c", 7);
1939 macro_build (&icnt
, NULL
, s2
, "d", dreg
);
1943 if (offset_expr
.X_op
== O_constant
)
1945 load_register (&icnt
, treg
, &offset_expr
);
1948 if (gp_reference (&offset_expr
))
1949 macro_build (&icnt
, &offset_expr
,
1950 mips_isa
< 3 ? "addiu" : "daddiu",
1954 /* FIXME: This won't work for a 64 bit address. */
1955 macro_build_lui (&icnt
, &offset_expr
, treg
);
1956 macro_build (&icnt
, &offset_expr
,
1957 mips_isa
< 3 ? "addiu" : "daddiu",
1958 "t,r,j", treg
, treg
);
1963 tempreg
= (breg
== treg
) ? AT
: treg
;
1964 if (offset_expr
.X_op
== O_constant
)
1965 load_register (&icnt
, tempreg
, &offset_expr
);
1966 else if (gp_reference (&offset_expr
))
1967 macro_build (&icnt
, &offset_expr
,
1968 mips_isa
< 3 ? "addiu" : "daddiu",
1969 "t,r,j", tempreg
, GP
);
1972 /* FIXME: This won't work for a 64 bit address. */
1973 macro_build_lui (&icnt
, &offset_expr
, tempreg
);
1974 macro_build (&icnt
, &offset_expr
,
1975 mips_isa
< 3 ? "addiu" : "daddiu",
1976 "t,r,j", tempreg
, tempreg
);
1979 macro_build (&icnt
, NULL
, "addu", "d,v,t", treg
, tempreg
, breg
);
2049 if (breg
== treg
|| coproc
)
2118 if (mask
== M_LWC1_AB
2119 || mask
== M_SWC1_AB
2121 || mask
== M_LDC1_AB
2122 || mask
== M_SDC1_AB
)
2128 if (gp_reference (&offset_expr
))
2132 macro_build (&icnt
, &offset_expr
, s
, fmt
, treg
, GP
);
2135 macro_build (&icnt
, (expressionS
*) NULL
,
2136 mips_isa
< 3 ? "addu" : "daddu",
2137 "d,v,t", tempreg
, breg
, GP
);
2141 /* FIXME: This won't work for a 64 bit address. */
2142 macro_build_lui (&icnt
, &offset_expr
, tempreg
);
2144 macro_build (&icnt
, NULL
,
2145 mips_isa
< 3 ? "addu" : "daddu",
2146 "d,v,t", tempreg
, tempreg
, breg
);
2148 macro_build (&icnt
, &offset_expr
, s
, fmt
, treg
, tempreg
);
2155 load_register (&icnt
, treg
, &imm_expr
);
2160 lw $v0,%lo(foo)($at)
2161 lw $v1,%lo(foo+4)($at)
2166 /* FIXME: This won't work for a 64 bit address. */
2167 macro_build_lui (&icnt
, &offset_expr
, AT
);
2169 macro_build (&icnt
, &offset_expr
, "ld", "t,o(b)", treg
, AT
);
2172 macro_build (&icnt
, &offset_expr
, "lw", "t,o(b)", treg
, AT
);
2173 offset_expr
.X_add_number
+= 4;
2174 macro_build (&icnt
, &offset_expr
, "lw", "t,o(b)", treg
+ 1, AT
);
2179 /* Load a floating point number from the .lit8 section. */
2182 macro_build (&icnt
, &offset_expr
, "ldc1", "T,o(b)", treg
, GP
);
2188 /* Even on a big endian machine $fn comes before $fn+1. We have
2189 to adjust when loading from memory. */
2190 assert (mips_isa
< 2);
2191 macro_build (&icnt
, &offset_expr
, "lwc1", "T,o(b)",
2192 byte_order
== LITTLE_ENDIAN
? treg
: treg
+ 1,
2194 offset_expr
.X_add_number
+= 4;
2195 macro_build (&icnt
, &offset_expr
, "lwc1", "T,o(b)",
2196 byte_order
== LITTLE_ENDIAN
? treg
+ 1 : treg
,
2202 * The MIPS assembler seems to check for X_add_number not
2203 * being double aligned and generating:
2206 * addiu at,at,%lo(foo+1)
2209 * But, the resulting address is the same after relocation so why
2210 * generate the extra instruction?
2212 if (gp_reference (&offset_expr
))
2218 macro_build (&icnt
, &offset_expr
,
2219 mips_isa
< 3 ? "addu" : "daddu",
2220 "d,v,t", AT
, breg
, GP
);
2226 /* FIXME: This won't work for a 64 bit address. */
2227 macro_build_lui (&icnt
, &offset_expr
, AT
);
2229 macro_build (&icnt
, NULL
,
2230 mips_isa
< 3 ? "addu" : "daddu",
2231 "d,v,t", AT
, AT
, breg
);
2235 macro_build (&icnt
, &offset_expr
, "ldc1", "T,o(b)", treg
, tempreg
);
2238 /* Even on a big endian machine $fn comes before $fn+1. We
2239 have to adjust when loading from memory. */
2240 macro_build (&icnt
, &offset_expr
, "lwc1", "T,o(b)",
2241 byte_order
== LITTLE_ENDIAN
? treg
: treg
+ 1,
2243 offset_expr
.X_add_number
+= 4;
2244 macro_build (&icnt
, &offset_expr
, "lwc1", "T,o(b)",
2245 byte_order
== LITTLE_ENDIAN
? treg
+ 1 : treg
,
2258 assert (mips_isa
< 3);
2259 macro_build (&icnt
, &offset_expr
, s
, "t,o(b)", treg
, breg
);
2260 offset_expr
.X_add_number
+= 4;
2261 macro_build (&icnt
, &offset_expr
, s
, "t,o(b)", treg
+ 1, breg
);
2284 if (gp_reference (&offset_expr
))
2292 macro_build (&icnt
, (expressionS
*) NULL
,
2293 mips_isa
< 3 ? "addu" : "daddu",
2294 "d,v,t", tempreg
, breg
, GP
);
2298 /* FIXME: This won't work for a 64 bit address. */
2299 macro_build_lui (&icnt
, &offset_expr
, tempreg
);
2301 macro_build (&icnt
, NULL
,
2302 mips_isa
< 3 ? "addu" : "daddu",
2303 "d,v,t", tempreg
, tempreg
, breg
);
2306 macro_build (&icnt
, &offset_expr
, s2
, "t,o(b)", treg
, tempreg
);
2309 macro_build (&icnt
, &offset_expr
, s
, "t,o(b)", treg
, tempreg
);
2310 offset_expr
.X_add_number
+= 4;
2311 macro_build (&icnt
, &offset_expr
, s
, "t,o(b)", treg
+ 1, tempreg
);
2320 macro_build (&icnt
, NULL
,
2321 dbl
? "dmultu" : "multu",
2323 macro_build (&icnt
, NULL
, "mflo", "d", dreg
);
2329 /* The MIPS assembler some times generates shifts and adds. I'm
2330 not trying to be that fancy. GCC should do this for us
2332 load_register (&icnt
, AT
, &imm_expr
);
2333 macro_build (&icnt
, NULL
,
2334 dbl
? "dmult" : "mult",
2336 macro_build (&icnt
, NULL
, "mflo", "d", dreg
);
2342 mips_emit_delays ();
2344 macro_build (&icnt
, NULL
,
2345 dbl
? "dmult" : "mult",
2347 macro_build (&icnt
, NULL
, "mflo", "d", dreg
);
2348 macro_build (&icnt
, NULL
,
2349 dbl
? "dsra32" : "sra",
2350 "d,w,<", dreg
, dreg
, 31);
2351 macro_build (&icnt
, NULL
, "mfhi", "d", AT
);
2352 expr1
.X_add_number
= 8;
2353 macro_build (&icnt
, &expr1
, "beq", "s,t,p", dreg
, AT
);
2354 macro_build (&icnt
, NULL
, "nop", "", 0);
2355 macro_build (&icnt
, NULL
, "break", "c", 6);
2357 macro_build (&icnt
, NULL
, "mflo", "d", dreg
);
2363 mips_emit_delays ();
2365 macro_build (&icnt
, NULL
,
2366 dbl
? "dmultu" : "multu",
2368 macro_build (&icnt
, NULL
, "mfhi", "d", AT
);
2369 macro_build (&icnt
, NULL
, "mflo", "d", dreg
);
2370 expr1
.X_add_number
= 8;
2371 macro_build (&icnt
, &expr1
, "beq", "s,t,p", AT
, 0);
2372 macro_build (&icnt
, NULL
, "nop", "", 0);
2373 macro_build (&icnt
, NULL
, "break", "c", 6);
2378 macro_build (&icnt
, NULL
, "subu", "d,v,t", AT
, 0, treg
);
2379 macro_build (&icnt
, NULL
, "srlv", "d,t,s", AT
, sreg
, AT
);
2380 macro_build (&icnt
, NULL
, "sllv", "d,t,s", dreg
, sreg
, treg
);
2381 macro_build (&icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
2385 macro_build (&icnt
, NULL
, "sll", "d,w,<", AT
, sreg
,
2386 imm_expr
.X_add_number
& 0x1f);
2387 macro_build (&icnt
, NULL
, "srl", "d,w,<", dreg
, sreg
,
2388 (0 - imm_expr
.X_add_number
) & 0x1f);
2389 macro_build (&icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
2393 macro_build (&icnt
, NULL
, "subu", "d,v,t", AT
, 0, treg
);
2394 macro_build (&icnt
, NULL
, "sllv", "d,t,s", AT
, sreg
, AT
);
2395 macro_build (&icnt
, NULL
, "srlv", "d,t,s", dreg
, sreg
, treg
);
2396 macro_build (&icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
2400 macro_build (&icnt
, NULL
, "srl", "d,w,<", AT
, sreg
,
2401 imm_expr
.X_add_number
& 0x1f);
2402 macro_build (&icnt
, NULL
, "sll", "d,w,<", dreg
, sreg
,
2403 (0 - imm_expr
.X_add_number
) & 0x1f);
2404 macro_build (&icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
2408 assert (mips_isa
< 2);
2409 /* Even on a big endian machine $fn comes before $fn+1. We have
2410 to adjust when storing to memory. */
2411 macro_build (&icnt
, &offset_expr
, "swc1", "T,o(b)",
2412 byte_order
== LITTLE_ENDIAN
? treg
: treg
+ 1,
2414 offset_expr
.X_add_number
+= 4;
2415 macro_build (&icnt
, &offset_expr
, "swc1", "T,o(b)",
2416 byte_order
== LITTLE_ENDIAN
? treg
+ 1 : treg
,
2421 if (gp_reference (&offset_expr
))
2427 macro_build (&icnt
, (expressionS
*) NULL
,
2428 mips_isa
< 3 ? "addu" : "daddu",
2429 "d,v,t", AT
, breg
, GP
);
2435 /* FIXME: This won't work for a 64 bit address. */
2436 macro_build_lui (&icnt
, &offset_expr
, AT
);
2438 macro_build (&icnt
, NULL
,
2439 mips_isa
< 3 ? "addu" : "daddu",
2440 "d,v,t", AT
, AT
, breg
);
2444 macro_build (&icnt
, &offset_expr
, "sdc1", "T,o(b)", treg
, tempreg
);
2447 /* Even on a big endian machine $fn comes before $fn+1. We
2448 have to adjust when storing to memory. */
2449 macro_build (&icnt
, &offset_expr
, "swc1", "T,o(b)",
2450 byte_order
== LITTLE_ENDIAN
? treg
: treg
+ 1,
2452 offset_expr
.X_add_number
+= 4;
2453 macro_build (&icnt
, &offset_expr
, "swc1", "T,o(b)",
2454 byte_order
== LITTLE_ENDIAN
? treg
+ 1 : treg
,
2463 macro_build (&icnt
, &expr1
, "sltiu", "t,r,j", dreg
, treg
);
2465 macro_build (&icnt
, &expr1
, "sltiu", "t,r,j", dreg
, sreg
);
2468 macro_build (&icnt
, NULL
, "xor", "d,v,t", dreg
, sreg
, treg
);
2469 macro_build (&icnt
, &expr1
, "sltiu", "t,r,j", dreg
, dreg
);
2474 if (imm_expr
.X_add_number
== 0)
2476 macro_build (&icnt
, &expr1
, "sltiu", "t,r,j", dreg
, sreg
);
2481 as_warn ("Instruction %s: result is always false",
2483 macro_build (&icnt
, NULL
, "move", "d,s", dreg
, 0);
2486 if (imm_expr
.X_add_number
>= 0 && imm_expr
.X_add_number
< 0x10000)
2488 macro_build (&icnt
, &imm_expr
, "xori", "t,r,i", dreg
, sreg
);
2491 else if (imm_expr
.X_add_number
> -0x8000 && imm_expr
.X_add_number
< 0)
2493 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
2494 macro_build (&icnt
, &imm_expr
,
2495 mips_isa
< 3 ? "addiu" : "daddiu",
2496 "t,r,j", dreg
, sreg
);
2501 load_register (&icnt
, AT
, &imm_expr
);
2502 macro_build (&icnt
, NULL
, "xor", "d,v,t", dreg
, sreg
, AT
);
2505 macro_build (&icnt
, &expr1
, "sltiu", "t,r,j", dreg
, dreg
);
2510 case M_SGE
: /* sreg >= treg <==> not (sreg < treg) */
2516 macro_build (&icnt
, NULL
, s
, "d,v,t", dreg
, sreg
, treg
);
2517 macro_build (&icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
);
2520 case M_SGE_I
: /* sreg >= I <==> not (sreg < I) */
2522 if (imm_expr
.X_add_number
>= -0x8000 && imm_expr
.X_add_number
< 0x8000)
2524 macro_build (&icnt
, &expr1
,
2525 mask
== M_SGE_I
? "slti" : "sltiu",
2526 "t,r,j", dreg
, sreg
);
2531 load_register (&icnt
, AT
, &imm_expr
);
2532 macro_build (&icnt
, NULL
,
2533 mask
== M_SGE_I
? "slt" : "sltu",
2534 "d,v,t", dreg
, sreg
, AT
);
2537 macro_build (&icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
);
2542 case M_SGT
: /* sreg > treg <==> treg < sreg */
2548 macro_build (&icnt
, NULL
, s
, "d,v,t", dreg
, treg
, sreg
);
2551 case M_SGT_I
: /* sreg > I <==> I < sreg */
2557 load_register (&icnt
, AT
, &imm_expr
);
2558 macro_build (&icnt
, NULL
, s
, "d,v,t", dreg
, AT
, sreg
);
2561 case M_SLE
: /* sreg <= treg <==> treg >= sreg <==> not (treg < sreg) */
2567 macro_build (&icnt
, NULL
, s
, "d,v,t", dreg
, treg
, sreg
);
2568 macro_build (&icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
);
2571 case M_SLE_I
: /* sreg <= I <==> I >= sreg <==> not (I < sreg) */
2577 load_register (&icnt
, AT
, &imm_expr
);
2578 macro_build (&icnt
, NULL
, s
, "d,v,t", dreg
, AT
, sreg
);
2579 macro_build (&icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
);
2583 if (imm_expr
.X_add_number
>= -0x8000 && imm_expr
.X_add_number
< 0x8000)
2585 macro_build (&icnt
, &imm_expr
, "slti", "t,r,j", dreg
, sreg
);
2588 load_register (&icnt
, AT
, &imm_expr
);
2589 macro_build (&icnt
, NULL
, "slt", "d,v,t", dreg
, sreg
, AT
);
2593 if (imm_expr
.X_add_number
>= -0x8000 && imm_expr
.X_add_number
< 0x8000)
2595 macro_build (&icnt
, &imm_expr
, "sltiu", "t,r,j", dreg
, sreg
);
2598 load_register (&icnt
, AT
, &imm_expr
);
2599 macro_build (&icnt
, NULL
, "sltu", "d,v,t", dreg
, sreg
, AT
);
2604 macro_build (&icnt
, NULL
, "sltu", "d,v,t", dreg
, 0, treg
);
2606 macro_build (&icnt
, NULL
, "sltu", "d,v,t", dreg
, 0, sreg
);
2609 macro_build (&icnt
, NULL
, "xor", "d,v,t", dreg
, sreg
, treg
);
2610 macro_build (&icnt
, NULL
, "sltu", "d,v,t", dreg
, 0, dreg
);
2615 if (imm_expr
.X_add_number
== 0)
2617 macro_build (&icnt
, NULL
, "sltu", "d,v,t", dreg
, 0, sreg
);
2622 as_warn ("Instruction %s: result is always true",
2624 macro_build (&icnt
, &expr1
,
2625 mips_isa
< 3 ? "addiu" : "daddiu",
2629 if (imm_expr
.X_add_number
>= 0 && imm_expr
.X_add_number
< 0x10000)
2631 macro_build (&icnt
, &imm_expr
, "xori", "t,r,i", dreg
, sreg
);
2634 else if (imm_expr
.X_add_number
> -0x8000 && imm_expr
.X_add_number
< 0)
2636 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
2637 macro_build (&icnt
, &imm_expr
,
2638 mips_isa
< 3 ? "addiu" : "daddiu",
2639 "t,r,j", dreg
, sreg
);
2644 load_register (&icnt
, AT
, &imm_expr
);
2645 macro_build (&icnt
, NULL
, "xor", "d,v,t", dreg
, sreg
, AT
);
2648 macro_build (&icnt
, NULL
, "sltu", "d,v,t", dreg
, 0, dreg
);
2656 if (imm_expr
.X_add_number
> -0x8000 && imm_expr
.X_add_number
<= 0x8000)
2658 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
2659 macro_build (&icnt
, &imm_expr
,
2660 dbl
? "daddi" : "addi",
2661 "t,r,j", dreg
, sreg
);
2664 load_register (&icnt
, AT
, &imm_expr
);
2665 macro_build (&icnt
, NULL
,
2666 dbl
? "dsub" : "sub",
2667 "d,v,t", dreg
, sreg
, AT
);
2673 if (imm_expr
.X_add_number
> -0x8000 && imm_expr
.X_add_number
<= 0x8000)
2675 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
2676 macro_build (&icnt
, &imm_expr
,
2677 dbl
? "daddiu" : "addiu",
2678 "t,r,j", dreg
, sreg
);
2681 load_register (&icnt
, AT
, &imm_expr
);
2682 macro_build (&icnt
, NULL
,
2683 dbl
? "dsubu" : "subu",
2684 "d,v,t", dreg
, sreg
, AT
);
2705 load_register (&icnt
, AT
, &imm_expr
);
2706 macro_build (&icnt
, NULL
, s
, "s,t", sreg
, AT
);
2711 assert (mips_isa
< 2);
2712 sreg
= (ip
->insn_opcode
>> 11) & 0x1f; /* floating reg */
2713 dreg
= (ip
->insn_opcode
>> 06) & 0x1f; /* floating reg */
2716 * Is the double cfc1 instruction a bug in the mips assembler;
2717 * or is there a reason for it?
2719 mips_emit_delays ();
2721 macro_build (&icnt
, NULL
, "cfc1", "t,G", treg
, 31);
2722 macro_build (&icnt
, NULL
, "cfc1", "t,G", treg
, 31);
2723 macro_build (&icnt
, NULL
, "nop", "");
2724 expr1
.X_add_number
= 3;
2725 macro_build (&icnt
, &expr1
, "ori", "t,r,i", AT
, treg
);
2726 expr1
.X_add_number
= 2;
2727 macro_build (&icnt
, &expr1
, "xori", "t,r,i", AT
, AT
);
2728 macro_build (&icnt
, NULL
, "ctc1", "t,G", AT
, 31);
2729 macro_build (&icnt
, NULL
, "nop", "");
2730 macro_build (&icnt
, NULL
,
2731 mask
== M_TRUNCWD
? "cvt.w.d" : "cvt.w.s", "D,S", dreg
, sreg
);
2732 macro_build (&icnt
, NULL
, "ctc1", "t,G", treg
, 31);
2733 macro_build (&icnt
, NULL
, "nop", "");
2743 /* avoid load delay */
2744 offset_expr
.X_add_number
+= 1;
2745 macro_build (&icnt
, &offset_expr
, s
, "t,o(b)", treg
, breg
);
2746 offset_expr
.X_add_number
-= 1;
2747 macro_build (&icnt
, &offset_expr
, "lbu", "t,o(b)", AT
, breg
);
2748 macro_build (&icnt
, NULL
, "sll", "d,w,<", treg
, treg
, 8);
2749 macro_build (&icnt
, NULL
, "or", "d,v,t", treg
, treg
, AT
);
2753 /* does this work on a big endian machine? */
2754 offset_expr
.X_add_number
+= 3;
2755 macro_build (&icnt
, &offset_expr
, "lwl", "t,o(b)", treg
, breg
);
2756 offset_expr
.X_add_number
-= 3;
2757 macro_build (&icnt
, &offset_expr
, "lwr", "t,o(b)", treg
, breg
);
2763 if (offset_expr
.X_op
== O_constant
)
2764 load_register (&icnt
, AT
, &offset_expr
);
2765 else if (gp_reference (&offset_expr
))
2766 macro_build (&icnt
, &offset_expr
,
2767 mips_isa
< 3 ? "addiu" : "daddiu",
2771 /* FIXME: This won't work for a 64 bit address. */
2772 macro_build_lui (&icnt
, &offset_expr
, AT
);
2773 macro_build (&icnt
, &offset_expr
,
2774 mips_isa
< 3 ? "addiu" : "daddiu",
2777 if (mask
== M_ULW_A
)
2779 expr1
.X_add_number
= 3;
2780 macro_build (&icnt
, &expr1
, "lwl", "t,o(b)", treg
, AT
);
2781 imm_expr
.X_add_number
= 0;
2782 macro_build (&icnt
, &expr1
, "lwr", "t,o(b)", treg
, AT
);
2786 macro_build (&icnt
, &expr1
,
2787 mask
== M_ULH_A
? "lb" : "lbu", "t,o(b)", treg
, AT
);
2788 imm_expr
.X_add_number
= 0;
2789 macro_build (&icnt
, &expr1
, "lbu", "t,o(b)", AT
, AT
);
2790 macro_build (&icnt
, NULL
, "sll", "d,w,<", treg
, treg
, 8);
2791 macro_build (&icnt
, NULL
, "or", "d,v,t", treg
, treg
, AT
);
2796 macro_build (&icnt
, &offset_expr
, "sb", "t,o(b)", treg
, breg
);
2797 macro_build (&icnt
, NULL
, "srl", "d,w,<", AT
, treg
, 8);
2798 offset_expr
.X_add_number
+= 1;
2799 macro_build (&icnt
, &offset_expr
, "sb", "t,o(b)", AT
, breg
);
2803 offset_expr
.X_add_number
+= 3;
2804 macro_build (&icnt
, &offset_expr
, "swl", "t,o(b)", treg
, breg
);
2805 offset_expr
.X_add_number
-= 3;
2806 macro_build (&icnt
, &offset_expr
, "swr", "t,o(b)", treg
, breg
);
2811 if (offset_expr
.X_op
== O_constant
)
2812 load_register (&icnt
, AT
, &offset_expr
);
2813 else if (gp_reference (&offset_expr
))
2814 macro_build (&icnt
, &offset_expr
,
2815 mips_isa
< 3 ? "addiu" : "daddiu",
2819 /* FIXME: This won't work for a 64 bit address. */
2820 macro_build_lui (&icnt
, &offset_expr
, AT
);
2821 macro_build (&icnt
, &offset_expr
,
2822 mips_isa
< 3 ? "addiu" : "daddiu",
2825 if (mask
== M_USW_A
)
2827 expr1
.X_add_number
= 3;
2828 macro_build (&icnt
, &expr1
, "swl", "t,o(b)", treg
, AT
);
2829 expr1
.X_add_number
= 0;
2830 macro_build (&icnt
, &expr1
, "swr", "t,o(b)", treg
, AT
);
2834 expr1
.X_add_number
= 0;
2835 macro_build (&icnt
, &expr1
, "sb", "t,o(b)", treg
, AT
);
2836 macro_build (&icnt
, NULL
, "srl", "d,w,<", treg
, treg
, 8);
2837 expr1
.X_add_number
= 1;
2838 macro_build (&icnt
, &expr1
, "sb", "t,o(b)", treg
, AT
);
2839 expr1
.X_add_number
= 0;
2840 macro_build (&icnt
, &expr1
, "lbu", "t,o(b)", AT
, AT
);
2841 macro_build (&icnt
, NULL
, "sll", "d,w,<", treg
, treg
, 8);
2842 macro_build (&icnt
, NULL
, "or", "d,v,t", treg
, treg
, AT
);
2847 as_bad ("Macro %s not implemented yet", ip
->insn_mo
->name
);
2851 as_warn ("Macro used $at after \".set noat\"");
2856 This routine assembles an instruction into its binary format. As a side
2857 effect it sets one of the global variables imm_reloc or offset_reloc to the
2858 type of relocation to do if one of the operands is an address expression.
2863 struct mips_cl_insn
*ip
;
2868 struct mips_opcode
*insn
;
2871 unsigned int lastregno
= 0;
2876 for (s
= str
; islower (*s
) || (*s
>= '0' && *s
<= '3') || *s
== '.'; ++s
)
2888 as_warn ("Unknown opcode: `%s'", str
);
2891 if ((insn
= (struct mips_opcode
*) hash_find (op_hash
, str
)) == NULL
)
2893 as_warn ("`%s' not in hash table.", str
);
2894 insn_error
= "ERROR: Unrecognized opcode";
2902 assert (strcmp (insn
->name
, str
) == 0);
2904 if (insn
->pinfo
== INSN_MACRO
)
2905 insn_isa
= insn
->match
;
2906 else if (insn
->pinfo
& INSN_ISA2
)
2908 else if (insn
->pinfo
& INSN_ISA3
)
2913 if (insn_isa
> mips_isa
)
2915 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
]
2916 && strcmp (insn
->name
, insn
[1].name
) == 0)
2921 insn_error
= "ERROR: instruction not supported on this processor";
2926 ip
->insn_opcode
= insn
->match
;
2927 for (args
= insn
->args
;; ++args
)
2933 case '\0': /* end of args */
2946 ip
->insn_opcode
|= lastregno
<< 21;
2951 ip
->insn_opcode
|= lastregno
<< 16;
2955 ip
->insn_opcode
|= lastregno
<< 11;
2961 /* handle optional base register.
2962 Either the base register is omitted or
2963 we must have a left paren. */
2964 /* this is dependent on the next operand specifier
2965 is a 'b' for base register */
2966 assert (args
[1] == 'b');
2970 case ')': /* these must match exactly */
2975 case '<': /* must be at least one digit */
2977 * According to the manual, if the shift amount is greater
2978 * than 31 or less than 0 the the shift amount should be
2979 * mod 32. In reality the mips assembler issues an error.
2980 * We issue a warning and do the mod.
2982 my_getExpression (&imm_expr
, s
);
2983 check_absolute_expr (ip
, &imm_expr
);
2984 if ((unsigned long) imm_expr
.X_add_number
> 31)
2986 as_warn ("Improper shift amount (%ld)",
2987 (long) imm_expr
.X_add_number
);
2988 imm_expr
.X_add_number
= imm_expr
.X_add_number
% 32;
2990 ip
->insn_opcode
|= imm_expr
.X_add_number
<< 6;
2991 imm_expr
.X_op
= O_absent
;
2995 case 'c': /* break code */
2996 my_getExpression (&imm_expr
, s
);
2997 check_absolute_expr (ip
, &imm_expr
);
2998 if ((unsigned) imm_expr
.X_add_number
> 1023)
2999 as_warn ("Illegal break code (%ld)",
3000 (long) imm_expr
.X_add_number
);
3001 ip
->insn_opcode
|= imm_expr
.X_add_number
<< 16;
3002 imm_expr
.X_op
= O_absent
;
3006 case 'B': /* syscall code */
3007 my_getExpression (&imm_expr
, s
);
3008 check_absolute_expr (ip
, &imm_expr
);
3009 if ((unsigned) imm_expr
.X_add_number
> 0xfffff)
3010 as_warn ("Illegal syscall code (%ld)",
3011 (long) imm_expr
.X_add_number
);
3012 ip
->insn_opcode
|= imm_expr
.X_add_number
<< 6;
3013 imm_expr
.X_op
= O_absent
;
3017 case 'C': /* Coprocessor code */
3018 my_getExpression (&imm_expr
, s
);
3019 check_absolute_expr (ip
, &imm_expr
);
3020 if ((unsigned long) imm_expr
.X_add_number
>= (1<<25))
3022 as_warn ("Coproccesor code > 25 bits (%ld)",
3023 (long) imm_expr
.X_add_number
);
3024 imm_expr
.X_add_number
&= ((1<<25) - 1);
3026 ip
->insn_opcode
|= imm_expr
.X_add_number
;
3027 imm_expr
.X_op
= O_absent
;
3031 case 'b': /* base register */
3032 case 'd': /* destination register */
3033 case 's': /* source register */
3034 case 't': /* target register */
3035 case 'r': /* both target and source */
3036 case 'v': /* both dest and source */
3037 case 'w': /* both dest and target */
3038 case 'E': /* coprocessor target register */
3039 case 'G': /* coprocessor destination register */
3040 case 'x': /* ignore register name */
3041 case 'z': /* must be zero register */
3055 while (isdigit (*s
));
3057 as_bad ("Invalid register number (%d)", regno
);
3059 else if (*args
!= 'E' && *args
!= 'G')
3061 if (s
[1] == 'f' && s
[2] == 'p')
3066 else if (s
[1] == 's' && s
[2] == 'p')
3071 else if (s
[1] == 'g' && s
[2] == 'p')
3076 else if (s
[1] == 'a' && s
[2] == 't')
3083 if (regno
== AT
&& ! mips_noat
)
3084 as_warn ("Used $at without \".set noat\"");
3091 if (c
== 'r' || c
== 'v' || c
== 'w')
3098 /* 'z' only matches $0. */
3099 if (c
== 'z' && regno
!= 0)
3107 ip
->insn_opcode
|= regno
<< 21;
3111 ip
->insn_opcode
|= regno
<< 11;
3116 ip
->insn_opcode
|= regno
<< 16;
3119 /* This case exists because on the r3000 trunc
3120 expands into a macro which requires a gp
3121 register. On the r6000 or r4000 it is
3122 assembled into a single instruction which
3123 ignores the register. Thus the insn version
3124 is MIPS_ISA2 and uses 'x', and the macro
3125 version is MIPS_ISA1 and uses 't'. */
3128 /* This case is for the div instruction, which
3129 acts differently if the destination argument
3130 is $0. This only matches $0, and is checked
3131 outside the switch. */
3142 ip
->insn_opcode
|= lastregno
<< 21;
3145 ip
->insn_opcode
|= lastregno
<< 16;
3150 case 'D': /* floating point destination register */
3151 case 'S': /* floating point source register */
3152 case 'T': /* floating point target register */
3156 if (s
[0] == '$' && s
[1] == 'f' && isdigit (s
[2]))
3166 while (isdigit (*s
));
3169 as_bad ("Invalid float register number (%d)", regno
);
3172 !(strcmp (str
, "mtc1") == 0 ||
3173 strcmp (str
, "mfc1") == 0 ||
3174 strcmp (str
, "lwc1") == 0 ||
3175 strcmp (str
, "swc1") == 0))
3176 as_warn ("Float register should be even, was %d",
3184 if (c
== 'V' || c
== 'W')
3194 ip
->insn_opcode
|= regno
<< 6;
3198 ip
->insn_opcode
|= regno
<< 11;
3202 ip
->insn_opcode
|= regno
<< 16;
3210 ip
->insn_opcode
|= lastregno
<< 11;
3213 ip
->insn_opcode
|= lastregno
<< 16;
3219 my_getExpression (&imm_expr
, s
);
3220 check_absolute_expr (ip
, &imm_expr
);
3225 my_getExpression (&offset_expr
, s
);
3226 imm_reloc
= BFD_RELOC_32
;
3238 unsigned char temp
[8];
3240 unsigned int length
;
3245 /* These only appear as the last operand in an
3246 instruction, and every instruction that accepts
3247 them in any variant accepts them in all variants.
3248 This means we don't have to worry about backing out
3249 any changes if the instruction does not match.
3251 The difference between them is the size of the
3252 floating point constant and where it goes. For 'F'
3253 and 'L' the constant is 64 bits; for 'f' and 'l' it
3254 is 32 bits. Where the constant is placed is based
3255 on how the MIPS assembler does things:
3258 f -- immediate value
3262 f64
= *args
== 'F' || *args
== 'L';
3264 save_in
= input_line_pointer
;
3265 input_line_pointer
= s
;
3266 err
= md_atof (f64
? 'd' : 'f', (char *) temp
, &len
);
3268 s
= input_line_pointer
;
3269 input_line_pointer
= save_in
;
3270 if (err
!= NULL
&& *err
!= '\0')
3272 as_bad ("Bad floating point constant: %s", err
);
3273 memset (temp
, '\0', sizeof temp
);
3274 length
= f64
? 8 : 4;
3277 assert (length
== (f64
? 8 : 4));
3281 imm_expr
.X_op
= O_constant
;
3282 if (byte_order
== LITTLE_ENDIAN
)
3283 imm_expr
.X_add_number
=
3284 (((((((int) temp
[3] << 8)
3289 imm_expr
.X_add_number
=
3290 (((((((int) temp
[0] << 8)
3297 /* Switch to the right section. */
3299 subseg
= now_subseg
;
3303 subseg_new (".rdata", (subsegT
) 0);
3306 subseg_new (".lit8", (subsegT
) 0);
3309 subseg_new (".lit4", (subsegT
) 0);
3313 as_bad ("Can't use floating point insn in this section");
3315 /* Set the argument to the current address in the
3317 offset_expr
.X_op
= O_symbol
;
3318 offset_expr
.X_add_symbol
=
3319 symbol_new ("L0\001", now_seg
,
3320 (valueT
) frag_now_fix (), frag_now
);
3321 offset_expr
.X_add_number
= 0;
3323 /* Put the floating point number into the section. */
3324 p
= frag_more ((int) length
);
3325 memcpy (p
, temp
, length
);
3327 /* Switch back to the original section. */
3328 subseg_set (seg
, subseg
);
3333 case 'i': /* 16 bit unsigned immediate */
3334 case 'j': /* 16 bit signed immediate */
3335 imm_reloc
= BFD_RELOC_LO16
;
3336 c
= my_getSmallExpression (&imm_expr
, s
);
3341 if (imm_expr
.X_op
== O_constant
)
3342 imm_expr
.X_add_number
=
3343 (imm_expr
.X_add_number
>> 16) & 0xffff;
3345 imm_reloc
= BFD_RELOC_HI16_S
;
3347 imm_reloc
= BFD_RELOC_HI16
;
3351 check_absolute_expr (ip
, &imm_expr
);
3354 if (imm_expr
.X_add_number
< 0
3355 || imm_expr
.X_add_number
>= 0x10000)
3357 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
3358 !strcmp (insn
->name
, insn
[1].name
))
3360 as_bad ("16 bit expression not in range 0..65535");
3365 if (imm_expr
.X_add_number
< -0x8000 ||
3366 imm_expr
.X_add_number
>= 0x8000)
3368 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
3369 !strcmp (insn
->name
, insn
[1].name
))
3371 as_bad ("16 bit expression not in range -32768..32767");
3377 case 'o': /* 16 bit offset */
3378 c
= my_getSmallExpression (&offset_expr
, s
);
3380 * If this value won't fit into a 16 bit offset, then
3381 * go find a macro that will generate the 32 bit offset
3384 if (offset_expr
.X_op
!= O_constant
3385 || offset_expr
.X_add_number
>= 0x8000
3386 || offset_expr
.X_add_number
< -0x8000)
3389 offset_reloc
= BFD_RELOC_LO16
;
3390 if (c
== 'h' || c
== 'H')
3392 assert (offset_expr
.X_op
== O_constant
);
3393 offset_expr
.X_add_number
=
3394 (offset_expr
.X_add_number
>> 16) & 0xffff;
3399 case 'p': /* pc relative offset */
3400 offset_reloc
= BFD_RELOC_16_PCREL_S2
;
3401 my_getExpression (&offset_expr
, s
);
3405 case 'u': /* upper 16 bits */
3406 c
= my_getSmallExpression (&imm_expr
, s
);
3407 if (imm_expr
.X_op
!= O_constant
3408 || imm_expr
.X_add_number
< 0
3409 || imm_expr
.X_add_number
>= 0x10000)
3410 as_bad ("lui expression not in range 0..65535");
3411 imm_reloc
= BFD_RELOC_LO16
;
3416 if (imm_expr
.X_op
== O_constant
)
3417 imm_expr
.X_add_number
=
3418 (imm_expr
.X_add_number
>> 16) & 0xffff;
3420 imm_reloc
= BFD_RELOC_HI16_S
;
3422 imm_reloc
= BFD_RELOC_HI16
;
3428 case 'a': /* 26 bit address */
3429 my_getExpression (&offset_expr
, s
);
3431 offset_reloc
= BFD_RELOC_MIPS_JMP
;
3435 fprintf (stderr
, "bad char = '%c'\n", *args
);
3440 /* Args don't match. */
3441 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
3442 !strcmp (insn
->name
, insn
[1].name
))
3448 insn_error
= "ERROR: Illegal operands";
3457 my_getSmallExpression (ep
, str
)
3468 ((str
[1] == 'h' && str
[2] == 'i')
3469 || (str
[1] == 'H' && str
[2] == 'I')
3470 || (str
[1] == 'l' && str
[2] == 'o'))
3482 * A small expression may be followed by a base register.
3483 * Scan to the end of this operand, and then back over a possible
3484 * base register. Then scan the small expression up to that
3485 * point. (Based on code in sparc.c...)
3487 for (sp
= str
; *sp
&& *sp
!= ','; sp
++)
3489 if (sp
- 4 >= str
&& sp
[-1] == RP
)
3491 if (isdigit (sp
[-2]))
3493 for (sp
-= 3; sp
>= str
&& isdigit (*sp
); sp
--)
3495 if (*sp
== '$' && sp
> str
&& sp
[-1] == LP
)
3501 else if (sp
- 5 >= str
3504 && ((sp
[-3] == 'f' && sp
[-2] == 'p')
3505 || (sp
[-3] == 's' && sp
[-2] == 'p')
3506 || (sp
[-3] == 'g' && sp
[-2] == 'p')
3507 || (sp
[-3] == 'a' && sp
[-2] == 't')))
3513 /* no expression means zero offset */
3516 /* %xx(reg) is an error */
3517 ep
->X_op
= O_absent
;
3522 ep
->X_op
= O_absent
;
3525 ep
->X_add_symbol
= NULL
;
3526 ep
->X_op_symbol
= NULL
;
3527 ep
->X_add_number
= 0;
3532 my_getExpression (ep
, str
);
3539 my_getExpression (ep
, str
);
3540 return c
; /* => %hi or %lo encountered */
3544 my_getExpression (ep
, str
)
3550 save_in
= input_line_pointer
;
3551 input_line_pointer
= str
;
3553 expr_end
= input_line_pointer
;
3554 input_line_pointer
= save_in
;
3557 /* Turn a string in input_line_pointer into a floating point constant
3558 of type type, and store the appropriate bytes in *litP. The number
3559 of LITTLENUMS emitted is stored in *sizeP . An error message is
3560 returned, or NULL on OK. */
3563 md_atof (type
, litP
, sizeP
)
3569 LITTLENUM_TYPE words
[4];
3585 return "bad call to md_atof";
3588 t
= atof_ieee (input_line_pointer
, type
, words
);
3590 input_line_pointer
= t
;
3594 if (byte_order
== LITTLE_ENDIAN
)
3596 for (i
= prec
- 1; i
>= 0; i
--)
3598 md_number_to_chars (litP
, (valueT
) words
[i
], 2);
3604 for (i
= 0; i
< prec
; i
++)
3606 md_number_to_chars (litP
, (valueT
) words
[i
], 2);
3615 md_number_to_chars (buf
, val
, n
)
3663 md_number_to_chars (buf
, hi
, 4);
3688 md_parse_option (argP
, cntP
, vecP
)
3693 /* Accept -nocpp but ignore it. */
3694 if (strcmp (*argP
, "nocpp") == 0)
3700 if (strcmp (*argP
, "EL") == 0
3701 || strcmp (*argP
, "EB") == 0)
3703 /* FIXME: This breaks -L -EL. */
3711 if ((*argP
)[1] == '0')
3720 if ((*argP
)[1] == '\0' || (*argP
)[1] == '2')
3725 if (strncmp (*argP
, "mips", 4) == 0)
3727 mips_isa
= atol (*argP
+ 4);
3730 else if (mips_isa
< 1 || mips_isa
> 3)
3732 as_bad ("-mips%d not supported", mips_isa
);
3739 if (strncmp (*argP
, "mcpu=", 5) == 0)
3743 /* Identify the processor type */
3745 if (strcmp (p
, "default") == 0
3746 || strcmp (p
, "DEFAULT") == 0)
3750 if (*p
== 'r' || *p
== 'R')
3757 if (strcmp (p
, "2000") == 0
3758 || strcmp (p
, "2k") == 0
3759 || strcmp (p
, "2K") == 0)
3764 if (strcmp (p
, "3000") == 0
3765 || strcmp (p
, "3k") == 0
3766 || strcmp (p
, "3K") == 0)
3771 if (strcmp (p
, "4000") == 0
3772 || strcmp (p
, "4k") == 0
3773 || strcmp (p
, "4K") == 0)
3778 if (strcmp (p
, "6000") == 0
3779 || strcmp (p
, "6k") == 0
3780 || strcmp (p
, "6K") == 0)
3787 as_bad ("bad value (%s) for -mcpu= switch", *argP
+ 5);
3800 if ((*argP
)[1] != '\0')
3801 g_switch_value
= atoi (*argP
+ 1);
3804 **vecP
= (char *) NULL
;
3807 g_switch_value
= atoi (**vecP
);
3810 as_warn ("Number expected after -G");
3816 return 1; /* pretend you parsed the character */
3820 md_pcrel_from (fixP
)
3823 /* return the address of the delay slot */
3824 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
3827 /* This is called by emit_expr via TC_CONS_FIX_NEW when creating a
3828 reloc for a cons. We could use the definition there, except that
3829 we want to handle 64 bit relocs specially. */
3832 cons_fix_new_mips (frag
, where
, nbytes
, exp
)
3835 unsigned int nbytes
;
3838 /* If we are assembling in 32 bit mode, turn an 8 byte reloc into a
3840 FIXME: There is no way to select anything but 32 bit mode right
3844 if (byte_order
== BIG_ENDIAN
)
3849 if (nbytes
!= 2 && nbytes
!= 4)
3850 as_bad ("Unsupported reloc size %d", nbytes
);
3852 fix_new_exp (frag_now
, where
, (int) nbytes
, exp
, 0,
3853 nbytes
== 2 ? BFD_RELOC_16
: BFD_RELOC_32
);
3857 md_apply_fix (fixP
, valueP
)
3864 assert (fixP
->fx_size
== 4);
3867 fixP
->fx_addnumber
= value
; /* Remember value for tc_gen_reloc */
3869 switch (fixP
->fx_r_type
)
3872 case BFD_RELOC_MIPS_JMP
:
3873 case BFD_RELOC_HI16
:
3874 case BFD_RELOC_HI16_S
:
3875 case BFD_RELOC_LO16
:
3876 case BFD_RELOC_MIPS_GPREL
:
3877 /* Nothing needed to do. The value comes from the reloc entry */
3880 case BFD_RELOC_16_PCREL_S2
:
3882 * We need to save the bits in the instruction since fixup_segment()
3883 * might be deleting the relocation entry (i.e., a branch within
3884 * the current segment).
3887 as_warn ("Branch to odd address (%lx)", value
);
3889 if ((value
& ~0xFFFF) && (value
& ~0xFFFF) != (-1 & ~0xFFFF))
3890 as_bad ("Relocation overflow");
3892 /* update old instruction data */
3893 buf
= (unsigned char *) (fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
);
3897 insn
= (buf
[3] << 24) | (buf
[2] << 16) | (buf
[1] << 8) | buf
[0];
3901 insn
= (buf
[0] << 24) | (buf
[1] << 16) | (buf
[2] << 8) | buf
[3];
3908 insn
|= value
& 0xFFFF;
3909 md_number_to_chars ((char *) buf
, (valueT
) insn
, 4);
3923 const struct mips_opcode
*p
;
3924 int treg
, sreg
, dreg
, shamt
;
3929 for (i
= 0; i
< NUMOPCODES
; ++i
)
3931 p
= &mips_opcodes
[i
];
3932 if (((oc
& p
->mask
) == p
->match
) && (p
->pinfo
!= INSN_MACRO
))
3934 printf ("%08lx %s\t", oc
, p
->name
);
3935 treg
= (oc
>> 16) & 0x1f;
3936 sreg
= (oc
>> 21) & 0x1f;
3937 dreg
= (oc
>> 11) & 0x1f;
3938 shamt
= (oc
>> 6) & 0x1f;
3940 for (args
= p
->args
;; ++args
)
3951 printf ("%c", *args
);
3955 assert (treg
== sreg
);
3956 printf ("$%d,$%d", treg
, sreg
);
3961 printf ("$%d", dreg
);
3966 printf ("$%d", treg
);
3971 printf ("$%d", sreg
);
3975 printf ("0x%08lx", oc
& 0x1ffffff);
3986 printf ("$%d", shamt
);
3997 printf ("%08lx UNDEFINED\n", oc
);
4008 name
= input_line_pointer
;
4009 c
= get_symbol_end ();
4010 p
= (symbolS
*) symbol_find_or_make (name
);
4011 *input_line_pointer
= c
;
4015 /* Align the current frag to a given power of two. The MIPS assembler
4016 also automatically adjusts any preceding label. */
4019 mips_align (to
, fill
)
4023 mips_emit_delays ();
4024 frag_align (to
, fill
);
4025 record_alignment (now_seg
, to
);
4026 if (insn_label
!= NULL
)
4028 assert (S_GET_SEGMENT (insn_label
) == now_seg
);
4029 insn_label
->sy_frag
= frag_now
;
4030 S_SET_VALUE (insn_label
, (valueT
) frag_now_fix ());
4035 /* Align to a given power of two. .align 0 turns off the automatic
4036 alignment used by the data creating pseudo-ops. */
4043 register long temp_fill
;
4044 long max_alignment
= 15;
4048 o Note that the assembler pulls down any immediately preceeding label
4049 to the aligned address.
4050 o It's not documented but auto alignment is reinstated by
4051 a .align pseudo instruction.
4052 o Note also that after auto alignment is turned off the mips assembler
4053 issues an error on attempt to assemble an improperly aligned data item.
4058 temp
= get_absolute_expression ();
4059 if (temp
> max_alignment
)
4060 as_bad ("Alignment too large: %d. assumed.", temp
= max_alignment
);
4063 as_warn ("Alignment negative: 0 assumed.");
4066 if (*input_line_pointer
== ',')
4068 input_line_pointer
++;
4069 temp_fill
= get_absolute_expression ();
4076 mips_align (temp
, (int) temp_fill
);
4083 demand_empty_rest_of_line ();
4086 /* Handle .ascii and .asciiz. This just calls stringer and forgets
4087 that there was a previous instruction. */
4090 s_stringer (append_zero
)
4093 mips_emit_delays ();
4095 stringer (append_zero
);
4106 mips_emit_delays ();
4116 subseg_set (bss_section
, (subsegT
) get_absolute_expression ());
4117 demand_empty_rest_of_line ();
4122 subseg_new (".rdata", (subsegT
) get_absolute_expression ());
4123 demand_empty_rest_of_line ();
4125 #else /* ! defined (OBJ_ECOFF) */
4127 seg
= subseg_new (".rodata", (subsegT
) get_absolute_expression ());
4128 bfd_set_section_flags (stdoutput
, seg
,
4134 demand_empty_rest_of_line ();
4136 #else /* ! defined (OBJ_ELF) */
4139 #endif /* ! defined (OBJ_ELF) */
4140 #endif /* ! defined (OBJ_ECOFF) */
4144 seg
= subseg_new (".sdata", (subsegT
) get_absolute_expression ());
4146 bfd_set_section_flags (stdoutput
, seg
,
4147 SEC_ALLOC
| SEC_LOAD
| SEC_RELOC
| SEC_DATA
);
4149 demand_empty_rest_of_line ();
4151 #else /* ! defined (GPOPT) */
4152 as_bad ("Global pointers not supported; recompile -G 0");
4153 demand_empty_rest_of_line ();
4155 #endif /* ! defined (GPOPT) */
4165 mips_emit_delays ();
4166 if (log_size
> 0 && auto_align
)
4167 mips_align (log_size
, 0);
4169 cons (1 << log_size
);
4176 as_fatal ("Encountered `.err', aborting assembly");
4186 symbolP
= get_symbol ();
4187 if (*input_line_pointer
== ',')
4188 input_line_pointer
++;
4189 size
= get_absolute_expression ();
4190 S_SET_VALUE (symbolP
, size
);
4191 S_SET_EXTERNAL (symbolP
);
4194 /* ECOFF needs to distinguish a .comm symbol from a .extern symbol,
4195 so we use an additional ECOFF specific field. */
4196 symbolP
->ecoff_undefined
= 1;
4204 mips_emit_delays ();
4221 if (strcmp (input_line_pointer
, "O1") != 0
4222 && strcmp (input_line_pointer
, "O2") != 0)
4223 as_warn ("Unrecognized option");
4224 demand_empty_rest_of_line ();
4231 char *name
= input_line_pointer
, ch
;
4233 while (!is_end_of_line
[(unsigned char) *input_line_pointer
])
4234 input_line_pointer
++;
4235 ch
= *input_line_pointer
;
4236 *input_line_pointer
= '\0';
4238 if (strcmp (name
, "reorder") == 0)
4242 prev_insn_unreordered
= 1;
4243 prev_prev_insn_unreordered
= 1;
4247 else if (strcmp (name
, "noreorder") == 0)
4249 mips_emit_delays ();
4252 else if (strcmp (name
, "at") == 0)
4256 else if (strcmp (name
, "noat") == 0)
4260 else if (strcmp (name
, "macro") == 0)
4262 mips_warn_about_macros
= 0;
4264 else if (strcmp (name
, "nomacro") == 0)
4266 if (mips_noreorder
== 0)
4267 as_bad ("`noreorder' must be set before `nomacro'");
4268 mips_warn_about_macros
= 1;
4270 else if (strcmp (name
, "move") == 0 || strcmp (name
, "novolatile") == 0)
4274 else if (strcmp (name
, "nomove") == 0 || strcmp (name
, "volatile") == 0)
4278 else if (strcmp (name
, "bopt") == 0)
4282 else if (strcmp (name
, "nobopt") == 0)
4288 as_warn ("Tried to set unrecognized symbol: %s\n", name
);
4290 *input_line_pointer
= ch
;
4291 demand_empty_rest_of_line ();
4294 /* The same as the usual .space directive, except that we have to
4295 forget about any previous instruction. */
4298 s_mips_space (param
)
4301 mips_emit_delays ();
4312 if (*input_line_pointer
++ != '$')
4314 as_warn ("expected `$'");
4317 if (isdigit ((unsigned char) *input_line_pointer
))
4319 reg
= get_absolute_expression ();
4320 if (reg
< 0 || reg
>= 32)
4322 as_warn ("Bad register number");
4328 if (strncmp (input_line_pointer
, "fp", 2) == 0)
4330 else if (strncmp (input_line_pointer
, "sp", 2) == 0)
4332 else if (strncmp (input_line_pointer
, "gp", 2) == 0)
4334 else if (strncmp (input_line_pointer
, "at", 2) == 0)
4338 as_warn ("Unrecognized register name");
4341 input_line_pointer
+= 2;
4347 * Translate internal representation of relocation info to BFD target format.
4350 tc_gen_reloc (section
, fixp
)
4356 reloc
= (arelent
*) xmalloc (sizeof (arelent
));
4357 assert (reloc
!= 0);
4359 reloc
->sym_ptr_ptr
= &fixp
->fx_addsy
->bsym
;
4360 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
4361 if (fixp
->fx_pcrel
== 0)
4362 reloc
->addend
= fixp
->fx_addnumber
;
4367 reloc
->addend
= -reloc
->address
;
4369 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, fixp
->fx_r_type
);
4370 assert (reloc
->howto
!= 0);
4375 /* should never be called */
4377 md_section_align (seg
, addr
)
4381 int align
= bfd_get_section_alignment (stdoutput
, seg
);
4383 return ((addr
+ (1 << align
) - 1) & (-1 << align
));
4387 md_estimate_size_before_relax (fragP
, segtype
)
4391 as_fatal ("md_estimate_size_before_relax");
4393 } /* md_estimate_size_before_relax() */
4395 /* This function is called whenever a label is defined. It is used
4396 when handling branch delays; if a branch has a label, we assume we
4400 mips_define_label (sym
)
4408 /* These functions should really be defined by the object file format,
4409 since they are related to debugging information. However, this
4410 code has to work for the a.out format, which does not define them,
4411 so we provide simple versions here. These don't actually generate
4412 any debugging information, but they do simple checking and someday
4413 somebody may make them useful. */
4417 struct loc
*loc_next
;
4418 unsigned long loc_fileno
;
4419 unsigned long loc_lineno
;
4420 unsigned long loc_offset
;
4421 unsigned short loc_delta
;
4422 unsigned short loc_count
;
4431 struct proc
*proc_next
;
4432 struct symbol
*proc_isym
;
4433 struct symbol
*proc_end
;
4434 unsigned long proc_reg_mask
;
4435 unsigned long proc_reg_offset
;
4436 unsigned long proc_fpreg_mask
;
4437 unsigned long proc_fpreg_offset
;
4438 unsigned long proc_frameoffset
;
4439 unsigned long proc_framereg
;
4440 unsigned long proc_pcreg
;
4442 struct file
*proc_file
;
4449 struct file
*file_next
;
4450 unsigned long file_fileno
;
4451 struct symbol
*file_symbol
;
4452 struct symbol
*file_end
;
4453 struct proc
*file_proc
;
4458 static struct obstack proc_frags
;
4459 static procS
*proc_lastP
;
4460 static procS
*proc_rootP
;
4461 static int numprocs
;
4466 obstack_begin (&proc_frags
, 0x2000);
4472 /* check for premature end, nesting errors, etc */
4473 if (proc_lastP
&& proc_lastP
->proc_end
== NULL
)
4474 as_warn ("missing `.end' at end of assembly");
4477 extern char hex_value
[];
4485 if (*input_line_pointer
== '-')
4487 ++input_line_pointer
;
4490 if (!isdigit (*input_line_pointer
))
4491 as_bad ("Expected simple number.");
4492 if (input_line_pointer
[0] == '0')
4494 if (input_line_pointer
[1] == 'x')
4496 input_line_pointer
+= 2;
4497 while (isxdigit (*input_line_pointer
))
4500 val
|= hex_value
[(int) *input_line_pointer
++];
4502 return negative
? -val
: val
;
4506 ++input_line_pointer
;
4507 while (isdigit (*input_line_pointer
))
4510 val
|= *input_line_pointer
++ - '0';
4512 return negative
? -val
: val
;
4515 if (!isdigit (*input_line_pointer
))
4517 printf (" *input_line_pointer == '%c' 0x%02x\n",
4518 *input_line_pointer
, *input_line_pointer
);
4519 as_warn ("Invalid number");
4522 while (isdigit (*input_line_pointer
))
4525 val
+= *input_line_pointer
++ - '0';
4527 return negative
? -val
: val
;
4530 /* The .file directive; just like the usual .file directive, but there
4531 is an initial number which is the ECOFF file index. */
4539 line
= get_number ();
4544 /* The .end directive. */
4552 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
4555 demand_empty_rest_of_line ();
4559 if (now_seg
!= text_section
)
4560 as_warn (".end not in text section");
4563 as_warn (".end and no .ent seen yet.");
4569 assert (S_GET_NAME (p
));
4570 if (strcmp (S_GET_NAME (p
), S_GET_NAME (proc_lastP
->proc_isym
)))
4571 as_warn (".end symbol does not match .ent symbol.");
4574 proc_lastP
->proc_end
= (symbolS
*) 1;
4577 /* The .aent and .ent directives. */
4587 symbolP
= get_symbol ();
4588 if (*input_line_pointer
== ',')
4589 input_line_pointer
++;
4590 if (isdigit (*input_line_pointer
) || *input_line_pointer
== '-')
4591 number
= get_number ();
4592 if (now_seg
!= text_section
)
4593 as_warn (".ent or .aent not in text section.");
4595 if (!aent
&& proc_lastP
&& proc_lastP
->proc_end
== NULL
)
4596 as_warn ("missing `.end'");
4600 procP
= (procS
*) obstack_alloc (&proc_frags
, sizeof (*procP
));
4601 procP
->proc_isym
= symbolP
;
4602 procP
->proc_reg_mask
= 0;
4603 procP
->proc_reg_offset
= 0;
4604 procP
->proc_fpreg_mask
= 0;
4605 procP
->proc_fpreg_offset
= 0;
4606 procP
->proc_frameoffset
= 0;
4607 procP
->proc_framereg
= 0;
4608 procP
->proc_pcreg
= 0;
4609 procP
->proc_end
= NULL
;
4610 procP
->proc_next
= NULL
;
4612 proc_lastP
->proc_next
= procP
;
4618 demand_empty_rest_of_line ();
4621 /* The .frame directive. */
4634 frame_reg
= tc_get_register ();
4635 if (*input_line_pointer
== ',')
4636 input_line_pointer
++;
4637 frame_off
= get_absolute_expression ();
4638 if (*input_line_pointer
== ',')
4639 input_line_pointer
++;
4640 pcreg
= tc_get_register ();
4643 assert (proc_rootP
);
4644 proc_rootP
->proc_framereg
= frame_reg
;
4645 proc_rootP
->proc_frameoffset
= frame_off
;
4646 proc_rootP
->proc_pcreg
= pcreg
;
4647 /* bob macho .frame */
4649 /* We don't have to write out a frame stab for unoptimized code. */
4650 if (!(frame_reg
== 30 && frame_off
== 0))
4653 as_warn ("No .ent for .frame to use.");
4654 (void) sprintf (str
, "R%d;%d", frame_reg
, frame_off
);
4655 symP
= symbol_new (str
, N_VFP
, 0, frag_now
);
4656 S_SET_TYPE (symP
, N_RMASK
);
4657 S_SET_OTHER (symP
, 0);
4658 S_SET_DESC (symP
, 0);
4659 symP
->sy_forward
= proc_lastP
->proc_isym
;
4660 /* bob perhaps I should have used pseudo set */
4662 demand_empty_rest_of_line ();
4666 /* The .fmask and .mask directives. */
4673 char str
[100], *strP
;
4679 mask
= get_number ();
4680 if (*input_line_pointer
== ',')
4681 input_line_pointer
++;
4682 off
= get_absolute_expression ();
4684 /* bob only for coff */
4685 assert (proc_rootP
);
4686 if (reg_type
== 'F')
4688 proc_rootP
->proc_fpreg_mask
= mask
;
4689 proc_rootP
->proc_fpreg_offset
= off
;
4693 proc_rootP
->proc_reg_mask
= mask
;
4694 proc_rootP
->proc_reg_offset
= off
;
4697 /* bob macho .mask + .fmask */
4699 /* We don't have to write out a mask stab if no saved regs. */
4703 as_warn ("No .ent for .mask to use.");
4705 for (i
= 0; i
< 32; i
++)
4709 sprintf (strP
, "%c%d,", reg_type
, i
);
4710 strP
+= strlen (strP
);
4714 sprintf (strP
, ";%d,", off
);
4715 symP
= symbol_new (str
, N_RMASK
, 0, frag_now
);
4716 S_SET_TYPE (symP
, N_RMASK
);
4717 S_SET_OTHER (symP
, 0);
4718 S_SET_DESC (symP
, 0);
4719 symP
->sy_forward
= proc_lastP
->proc_isym
;
4720 /* bob perhaps I should have used pseudo set */
4725 /* The .loc directive. */
4736 assert (now_seg
== text_section
);
4738 lineno
= get_number ();
4739 addroff
= obstack_next_free (&frags
) - frag_now
->fr_literal
;
4741 symbolP
= symbol_new ("", N_SLINE
, addroff
, frag_now
);
4742 S_SET_TYPE (symbolP
, N_SLINE
);
4743 S_SET_OTHER (symbolP
, 0);
4744 S_SET_DESC (symbolP
, lineno
);
4745 symbolP
->sy_segment
= now_seg
;
4749 #endif /* ! defined (OBJ_ECOFF) */