1 /* tc-mips.c -- assemble code for a MIPS chip.
2 Copyright (C) 1993 Free Software Foundation, Inc.
3 Contributed by the OSF and Ralph Campbell.
4 Written by Keith Knowles and Ralph Campbell, working independently.
5 Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus
8 This file is part of GAS.
10 GAS is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 2, or (at your option)
15 GAS is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with GAS; see the file COPYING. If not, write to
22 the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */
40 #endif /* NO_VARARGS */
41 #endif /* NO_STDARG */
43 #include "opcode/mips.h"
48 static char *mips_regmask_frag
;
52 #define PIC_CALL_REG 25
58 /* Decide whether to do GP reference optimizations based on the object
68 /* These variables are filled in with the masks of registers used.
69 The object format code reads them and puts them in the appropriate
71 unsigned long mips_gprmask
;
72 unsigned long mips_cprmask
[4];
74 /* MIPS ISA (Instruction Set Architecture) level. */
75 static int mips_isa
= -1;
77 /* MIPS PIC level. 0 is normal, non-PIC code. 2 means to generate
78 SVR4 ABI PIC calls. 1 doesn't mean anything. */
81 static int mips_warn_about_macros
;
82 static int mips_noreorder
;
83 static int mips_any_noreorder
;
84 static int mips_nomove
;
86 static int mips_nobopt
;
89 /* The size of the small data section. */
90 static int g_switch_value
= 8;
96 /* handle of the OPCODE hash table */
97 static struct hash_control
*op_hash
= NULL
;
99 /* This array holds the chars that always start a comment. If the
100 pre-processor is disabled, these aren't very useful */
101 const char comment_chars
[] = "#";
103 /* This array holds the chars that only start a comment at the beginning of
104 a line. If the line seems to have the form '# 123 filename'
105 .line and .file directives will appear in the pre-processed output */
106 /* Note that input_file.c hand checks for '#' at the beginning of the
107 first line of the input file. This is because the compiler outputs
108 #NO_APP at the beginning of its output. */
109 /* Also note that C style comments are always supported. */
110 const char line_comment_chars
[] = "#";
112 /* This array holds machine specific line separator characters. */
113 const char line_separator_chars
[] = "";
115 /* Chars that can be used to separate mant from exp in floating point nums */
116 const char EXP_CHARS
[] = "eE";
118 /* Chars that mean this number is a floating point constant */
121 const char FLT_CHARS
[] = "rRsSfFdDxXpP";
123 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
124 changed in read.c . Ideally it shouldn't have to know about it at all,
125 but nothing is ideal around here.
128 static char *insn_error
;
130 static int byte_order
= BYTE_ORDER
;
132 static int auto_align
= 1;
134 /* Symbol labelling the current insn. */
135 static symbolS
*insn_label
;
137 /* When outputting SVR4 PIC code, the assembler needs to know the
138 offset in the stack frame from which to restore the $gp register.
139 This is set by the .cprestore pseudo-op, and saved in this
141 static offsetT mips_cprestore_offset
= -1;
143 /* This is the register which holds the stack frame, as set by the
144 .frame pseudo-op. This is needed to implement .cprestore. */
145 static int mips_frame_reg
= SP
;
147 /* To output NOP instructions correctly, we need to keep information
148 about the previous two instructions. */
150 /* Whether we are optimizing. The default value of 2 means to remove
151 unneeded NOPs and swap branch instructions when possible. A value
152 of 1 means to not swap branches. A value of 0 means to always
154 static int mips_optimize
= 2;
156 /* The previous instruction. */
157 static struct mips_cl_insn prev_insn
;
159 /* The instruction before prev_insn. */
160 static struct mips_cl_insn prev_prev_insn
;
162 /* If we don't want information for prev_insn or prev_prev_insn, we
163 point the insn_mo field at this dummy integer. */
164 static const struct mips_opcode dummy_opcode
= { 0 };
166 /* Non-zero if prev_insn is valid. */
167 static int prev_insn_valid
;
169 /* The frag for the previous instruction. */
170 static struct frag
*prev_insn_frag
;
172 /* The offset into prev_insn_frag for the previous instruction. */
173 static long prev_insn_where
;
175 /* The reloc for the previous instruction, if any. */
176 static fixS
*prev_insn_fixp
;
178 /* Non-zero if the previous instruction was in a delay slot. */
179 static int prev_insn_is_delay_slot
;
181 /* Non-zero if the previous instruction was in a .set noreorder. */
182 static int prev_insn_unreordered
;
184 /* Non-zero if the previous previous instruction was in a .set
186 static int prev_prev_insn_unreordered
;
188 /* Since the MIPS does not have multiple forms of PC relative
189 instructions, we do not have to do relaxing as is done on other
190 platforms. However, we do have to handle GP relative addressing
191 correctly, which turns out to be a similar problem.
193 Every macro that refers to a symbol can occur in (at least) two
194 forms, one with GP relative addressing and one without. For
195 example, loading a global variable into a register generally uses
196 an macroinstruction like this:
198 If i can be addressed off the GP register (this is true if it is in
199 the .sbss or .sdata section, or if it is known to be smaller than
200 the -G argument) this will generate the following instruction:
202 This instruction will use a GPREL reloc. If i can not be addressed
203 off the GP register, the following instruction sequence will be used:
206 In this case the first instruction will have a HI16 reloc, and the
207 second reloc will have a LO16 reloc. Both relocs will be against
210 The issue here is that we may not know whether i is GP addressable
211 until after we see the instruction that uses it. Therefore, we
212 want to be able to choose the final instruction sequence only at
213 the end of the assembly. This is similar to the way other
214 platforms choose the form of a PC relative instruction only at the
217 When generating position independent code we do not use GP
218 addressing in the same way, but the issue still arises as external
219 symbols and local symbols must be handled differently.
221 We handle these issues by actually generating both possible
222 instruction sequences. The longer one is put in a frag_var with
223 type rs_machine_dependent. We encode what to do with the frag in
224 the subtype field. We encode (1) the number of existing bytes to
225 replace, (2) the number of new bytes to use, (3) the offset from
226 the start of the existing bytes to the first reloc we must generate
227 (that is, the offset is applied from the start of the existing
228 bytes after they are replaced by the new bytes, if any), (4) the
229 offset from the start of the existing bytes to the second reloc,
230 (5) whether a third reloc is needed (the third reloc is always four
231 bytes after the second reloc), and (6) whether to warn if this
232 variant is used (this is sometimes needed if .set nomacro or .set
233 noat is in effect). All these numbers are reasonably small.
235 Generating two instruction sequences must be handled carefully to
236 ensure that delay slots are handled correctly. Fortunately, the
237 issue only arises in a restricted number of cases. When the second
238 instruction sequence is generated, append_insn is directed to
239 maintain the existing delay slot information, so it continues to
240 apply to any code after the second instruction sequence. This
241 means that the second instruction sequence must not impose any
242 requirements not required by the first instruction sequence.
244 These variant frags are then handled in functions called by the
245 machine independent code. md_estimate_size_before_relax returns
246 the final size of the frag. md_convert_frag sets up the final form
247 of the frag. tc_gen_reloc adjust the first reloc and adds a second
249 #define RELAX_ENCODE(old, new, reloc1, reloc2, reloc3, warn) \
253 | (((reloc1) + 64) << 9) \
254 | (((reloc2) + 64) << 2) \
255 | ((reloc3) ? (1 << 1) : 0) \
257 #define RELAX_OLD(i) (((i) >> 24) & 0xff)
258 #define RELAX_NEW(i) (((i) >> 16) & 0xff)
259 #define RELAX_RELOC1(i) ((((i) >> 9) & 0x7f) - 64)
260 #define RELAX_RELOC2(i) ((((i) >> 2) & 0x7f) - 64)
261 #define RELAX_RELOC3(i) (((i) >> 1) & 1)
262 #define RELAX_WARN(i) ((i) & 1)
264 /* Prototypes for static functions. */
267 #define internalError() \
268 as_fatal ("internal Error, line %d, %s", __LINE__, __FILE__)
270 #define internalError() as_fatal ("MIPS internal Error");
273 static int insn_uses_reg
PARAMS ((struct mips_cl_insn
*ip
,
274 unsigned int reg
, int fpr
));
275 static void append_insn
PARAMS ((char *place
,
276 struct mips_cl_insn
* ip
,
278 bfd_reloc_code_real_type r
));
279 static void mips_no_prev_insn
PARAMS ((void));
280 static void mips_emit_delays
PARAMS ((void));
281 static void macro_build
PARAMS ((char *place
, int *counter
, expressionS
* ep
,
282 const char *name
, const char *fmt
,
284 static void macro_build_lui
PARAMS ((char *place
, int *counter
,
285 expressionS
* ep
, int regnum
));
286 static void set_at
PARAMS ((int *counter
, int reg
, int unsignedp
));
287 static void check_absolute_expr
PARAMS ((struct mips_cl_insn
* ip
,
289 static void load_register
PARAMS ((int *counter
, int reg
, expressionS
* ep
));
290 static void load_address
PARAMS ((int *counter
, int reg
, expressionS
*ep
));
291 static void macro
PARAMS ((struct mips_cl_insn
* ip
));
292 #ifdef LOSING_COMPILER
293 static void macro2
PARAMS ((struct mips_cl_insn
* ip
));
295 static void mips_ip
PARAMS ((char *str
, struct mips_cl_insn
* ip
));
296 static int my_getSmallExpression
PARAMS ((expressionS
* ep
, char *str
));
297 static void my_getExpression
PARAMS ((expressionS
* ep
, char *str
));
298 static symbolS
*get_symbol
PARAMS ((void));
299 static void mips_align
PARAMS ((int to
, int fill
));
300 static void s_align
PARAMS ((int));
301 static void s_stringer
PARAMS ((int));
302 static void s_change_sec
PARAMS ((int));
303 static void s_cons
PARAMS ((int));
304 static void s_err
PARAMS ((int));
305 static void s_extern
PARAMS ((int));
306 static void s_float_cons
PARAMS ((int));
307 static void s_option
PARAMS ((int));
308 static void s_mipsset
PARAMS ((int));
309 static void s_mips_space
PARAMS ((int));
310 static void s_abicalls
PARAMS ((int));
311 static void s_cpload
PARAMS ((int));
312 static void s_cprestore
PARAMS ((int));
313 static void s_gpword
PARAMS ((int));
314 static void s_cpadd
PARAMS ((int));
315 #ifndef ECOFF_DEBUGGING
316 static void md_obj_begin
PARAMS ((void));
317 static void md_obj_end
PARAMS ((void));
318 static long get_number
PARAMS ((void));
319 static void s_ent
PARAMS ((int));
320 static void s_mipsend
PARAMS ((int));
321 static void s_file
PARAMS ((int));
323 static void s_frame
PARAMS ((int));
324 static void s_loc
PARAMS ((int));
325 static void s_mask
PARAMS ((char));
331 The following pseudo-ops from the Kane and Heinrich MIPS book
332 should be defined here, but are currently unsupported: .alias,
333 .galive, .gjaldef, .gjrlive, .livereg, .noalias.
335 The following pseudo-ops from the Kane and Heinrich MIPS book are
336 specific to the type of debugging information being generated, and
337 should be defined by the object format: .aent, .begin, .bend,
338 .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp,
341 The following pseudo-ops from the Kane and Heinrich MIPS book are
342 not MIPS CPU specific, but are also not specific to the object file
343 format. This file is probably the best place to define them, but
344 they are not currently supported: .asm0, .endr, .lab, .repeat,
345 .struct, .weakext. */
347 const pseudo_typeS md_pseudo_table
[] =
349 /* MIPS specific pseudo-ops. */
350 {"option", s_option
, 0},
351 {"set", s_mipsset
, 0},
352 {"rdata", s_change_sec
, 'r'},
353 {"sdata", s_change_sec
, 's'},
354 {"livereg", s_ignore
, 0},
355 { "abicalls", s_abicalls
, 0},
356 { "cpload", s_cpload
, 0},
357 { "cprestore", s_cprestore
, 0},
358 { "gpword", s_gpword
, 0},
359 { "cpadd", s_cpadd
, 0},
361 /* Relatively generic pseudo-ops that happen to be used on MIPS
363 {"asciiz", s_stringer
, 1},
364 {"bss", s_change_sec
, 'b'},
367 {"dword", s_cons
, 3},
369 /* These pseudo-ops are defined in read.c, but must be overridden
370 here for one reason or another. */
371 {"align", s_align
, 0},
372 {"ascii", s_stringer
, 0},
373 {"asciz", s_stringer
, 1},
375 {"data", s_change_sec
, 'd'},
376 {"double", s_float_cons
, 'd'},
377 {"extern", s_extern
, 0},
378 {"float", s_float_cons
, 'f'},
379 {"space", s_mips_space
, 0},
380 {"text", s_change_sec
, 't'},
383 #ifndef ECOFF_DEBUGGING
384 /* These pseudo-ops should be defined by the object file format.
385 However, a.out doesn't support them, so we have versions here. */
387 {"bgnb", s_ignore
, 0},
388 {"end", s_mipsend
, 0},
389 {"endb", s_ignore
, 0},
392 {"fmask", s_ignore
, 'F'},
393 {"frame", s_ignore
, 0},
394 {"loc", s_ignore
, 0},
395 {"mask", s_ignore
, 'R'},
396 {"verstamp", s_ignore
, 0},
403 const relax_typeS md_relax_table
[] =
409 static char *expr_end
;
411 static expressionS imm_expr
;
412 static expressionS offset_expr
;
413 static bfd_reloc_code_real_type imm_reloc
;
414 static bfd_reloc_code_real_type offset_reloc
;
416 /* FIXME: This should be handled in a different way. */
417 extern int target_big_endian
;
420 * This function is called once, at assembler startup time. It should
421 * set up all the tables, etc. that the MD part of the assembler will need.
427 register const char *retval
= NULL
;
428 register unsigned int i
= 0;
432 if (strcmp (TARGET_CPU
, "mips") == 0)
434 else if (strcmp (TARGET_CPU
, "r6000") == 0
435 || strcmp (TARGET_CPU
, "mips2") == 0)
437 else if (strcmp (TARGET_CPU
, "mips64") == 0
438 || strcmp (TARGET_CPU
, "r4000") == 0
439 || strcmp (TARGET_CPU
, "mips3") == 0)
448 ok
= bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, 3000);
451 ok
= bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, 6000);
454 ok
= bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, 4000);
458 as_warn ("Could not set architecture and machine");
460 op_hash
= hash_new ();
462 for (i
= 0; i
< NUMOPCODES
;)
464 const char *name
= mips_opcodes
[i
].name
;
466 retval
= hash_insert (op_hash
, name
, (PTR
) &mips_opcodes
[i
]);
469 fprintf (stderr
, "internal error: can't hash `%s': %s\n",
470 mips_opcodes
[i
].name
, retval
);
471 as_fatal ("Broken assembler. No assembly attempted.");
475 if (mips_opcodes
[i
].pinfo
!= INSN_MACRO
476 && ((mips_opcodes
[i
].match
& mips_opcodes
[i
].mask
)
477 != mips_opcodes
[i
].match
))
479 fprintf (stderr
, "internal error: bad opcode: `%s' \"%s\"\n",
480 mips_opcodes
[i
].name
, mips_opcodes
[i
].args
);
481 as_fatal ("Broken assembler. No assembly attempted.");
485 while ((i
< NUMOPCODES
) && !strcmp (mips_opcodes
[i
].name
, name
));
488 mips_no_prev_insn ();
496 /* set the default alignment for the text section (2**2) */
497 record_alignment (text_section
, 2);
499 /* FIXME: This should be handled in a different way. */
500 target_big_endian
= byte_order
== BIG_ENDIAN
;
503 bfd_set_gp_size (stdoutput
, g_switch_value
);
507 /* Sections must be aligned to 16 byte boundaries. */
508 (void) bfd_set_section_alignment (stdoutput
, text_section
, 4);
509 (void) bfd_set_section_alignment (stdoutput
, data_section
, 4);
510 (void) bfd_set_section_alignment (stdoutput
, bss_section
, 4);
512 /* Create a .reginfo section for register masks and a .mdebug
513 section for debugging information. */
521 sec
= subseg_new (".reginfo", (subsegT
) 0);
523 /* I don't know why this section should be loaded, but the ABI
524 says that SHF_ALLOC should be set. */
525 (void) bfd_set_section_flags (stdoutput
, sec
,
526 (SEC_ALLOC
| SEC_LOAD
527 | SEC_READONLY
| SEC_DATA
));
528 (void) bfd_set_section_alignment (stdoutput
, sec
, 2);
530 mips_regmask_frag
= frag_more (sizeof (Elf32_External_RegInfo
));
532 #ifdef ECOFF_DEBUGGING
533 sec
= subseg_new (".mdebug", (subsegT
) 0);
534 (void) bfd_set_section_flags (stdoutput
, sec
,
535 SEC_HAS_CONTENTS
| SEC_READONLY
);
536 (void) bfd_set_section_alignment (stdoutput
, sec
, 2);
539 subseg_set (seg
, subseg
);
543 #ifndef ECOFF_DEBUGGING
551 #ifndef ECOFF_DEBUGGING
560 struct mips_cl_insn insn
;
562 imm_expr
.X_op
= O_absent
;
563 offset_expr
.X_op
= O_absent
;
565 mips_ip (str
, &insn
);
568 as_bad ("%s `%s'", insn_error
, str
);
571 if (insn
.insn_mo
->pinfo
== INSN_MACRO
)
577 if (imm_expr
.X_op
!= O_absent
)
578 append_insn ((char *) NULL
, &insn
, &imm_expr
, imm_reloc
);
579 else if (offset_expr
.X_op
!= O_absent
)
580 append_insn ((char *) NULL
, &insn
, &offset_expr
, offset_reloc
);
582 append_insn ((char *) NULL
, &insn
, NULL
, BFD_RELOC_UNUSED
);
586 /* See whether instruction IP reads register REG. If FPR is non-zero,
587 REG is a floating point register. */
590 insn_uses_reg (ip
, reg
, fpr
)
591 struct mips_cl_insn
*ip
;
595 /* Don't report on general register 0, since it never changes. */
596 if (! fpr
&& reg
== 0)
601 /* If we are called with either $f0 or $f1, we must check $f0.
602 This is not optimal, because it will introduce an unnecessary
603 NOP between "lwc1 $f0" and "swc1 $f1". To fix this we would
604 need to distinguish reading both $f0 and $f1 or just one of
605 them. Note that we don't have to check the other way,
606 because there is no instruction that sets both $f0 and $f1
607 and requires a delay. */
608 if ((ip
->insn_mo
->pinfo
& INSN_READ_FPR_S
)
609 && (((ip
->insn_opcode
>> OP_SH_FS
) & OP_MASK_FS
)
610 == (reg
&~ (unsigned) 1)))
612 if ((ip
->insn_mo
->pinfo
& INSN_READ_FPR_T
)
613 && (((ip
->insn_opcode
>> OP_SH_FT
) & OP_MASK_FT
)
614 == (reg
&~ (unsigned) 1)))
619 if ((ip
->insn_mo
->pinfo
& INSN_READ_GPR_S
)
620 && ((ip
->insn_opcode
>> OP_SH_RS
) & OP_MASK_RS
) == reg
)
622 if ((ip
->insn_mo
->pinfo
& INSN_READ_GPR_T
)
623 && ((ip
->insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
) == reg
)
630 /* Output an instruction. PLACE is where to put the instruction; if
631 it is NULL, this uses frag_more to get room. IP is the instruction
632 information. ADDRESS_EXPR is an operand of the instruction to be
633 used with RELOC_TYPE. */
636 append_insn (place
, ip
, address_expr
, reloc_type
)
638 struct mips_cl_insn
*ip
;
639 expressionS
*address_expr
;
640 bfd_reloc_code_real_type reloc_type
;
642 register unsigned long prev_pinfo
, pinfo
;
647 prev_pinfo
= prev_insn
.insn_mo
->pinfo
;
648 pinfo
= ip
->insn_mo
->pinfo
;
650 if (place
== NULL
&& ! mips_noreorder
)
652 /* If the previous insn required any delay slots, see if we need
653 to insert a NOP or two. There are eight kinds of possible
654 hazards, of which an instruction can have at most one type.
655 (1) a load from memory delay
656 (2) a load from a coprocessor delay
657 (3) an unconditional branch delay
658 (4) a conditional branch delay
659 (5) a move to coprocessor register delay
660 (6) a load coprocessor register from memory delay
661 (7) a coprocessor condition code delay
662 (8) a HI/LO special register delay
664 There are a lot of optimizations we could do that we don't.
665 In particular, we do not, in general, reorder instructions.
666 If you use gcc with optimization, it will reorder
667 instructions and generally do much more optimization then we
668 do here; repeating all that work in the assembler would only
669 benefit hand written assembly code, and does not seem worth
672 /* This is how a NOP is emitted. */
673 #define emit_nop() md_number_to_chars (frag_more (4), 0, 4)
675 /* The previous insn might require a delay slot, depending upon
676 the contents of the current insn. */
677 if ((prev_pinfo
& INSN_LOAD_COPROC_DELAY
)
679 && (prev_pinfo
& INSN_LOAD_MEMORY_DELAY
)))
681 /* A load from a coprocessor or from memory. All load
682 delays delay the use of general register rt for one
683 instruction on the r3000. The r6000 and r4000 use
685 know (prev_pinfo
& INSN_WRITE_GPR_T
);
686 if (mips_optimize
== 0
687 || insn_uses_reg (ip
,
688 ((prev_insn
.insn_opcode
>> OP_SH_RT
)
693 else if ((prev_pinfo
& INSN_COPROC_MOVE_DELAY
)
695 && (prev_pinfo
& INSN_COPROC_MEMORY_DELAY
)))
697 /* A generic coprocessor delay. The previous instruction
698 modified a coprocessor general or control register. If
699 it modified a control register, we need to avoid any
700 coprocessor instruction (this is probably not always
701 required, but it sometimes is). If it modified a general
702 register, we avoid using that register.
704 On the r6000 and r4000 loading a coprocessor register
705 from memory is interlocked, and does not require a delay.
707 This case is not handled very well. There is no special
708 knowledge of CP0 handling, and the coprocessors other
709 than the floating point unit are not distinguished at
711 if (prev_pinfo
& INSN_WRITE_FPR_T
)
713 if (mips_optimize
== 0
714 || insn_uses_reg (ip
,
715 ((prev_insn
.insn_opcode
>> OP_SH_FT
)
720 else if (prev_pinfo
& INSN_WRITE_FPR_S
)
722 if (mips_optimize
== 0
723 || insn_uses_reg (ip
,
724 ((prev_insn
.insn_opcode
>> OP_SH_FS
)
731 /* We don't know exactly what the previous instruction
732 does. If the current instruction uses a coprocessor
733 register, we must insert a NOP. If previous
734 instruction may set the condition codes, and the
735 current instruction uses them, we must insert two
737 if (mips_optimize
== 0
738 || ((prev_pinfo
& INSN_WRITE_COND_CODE
)
739 && (pinfo
& INSN_READ_COND_CODE
)))
741 else if (pinfo
& INSN_COP
)
745 else if (prev_pinfo
& INSN_WRITE_COND_CODE
)
747 /* The previous instruction sets the coprocessor condition
748 codes, but does not require a general coprocessor delay
749 (this means it is a floating point comparison
750 instruction). If this instruction uses the condition
751 codes, we need to insert a single NOP. */
752 if (mips_optimize
== 0
753 || (pinfo
& INSN_READ_COND_CODE
))
756 else if (prev_pinfo
& INSN_READ_LO
)
758 /* The previous instruction reads the LO register; if the
759 current instruction writes to the LO register, we must
761 if (mips_optimize
== 0
762 || (pinfo
& INSN_WRITE_LO
))
765 else if (prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
767 /* The previous instruction reads the HI register; if the
768 current instruction writes to the HI register, we must
770 if (mips_optimize
== 0
771 || (pinfo
& INSN_WRITE_HI
))
775 /* There are two cases which require two intervening
776 instructions: 1) setting the condition codes using a move to
777 coprocessor instruction which requires a general coprocessor
778 delay and then reading the condition codes 2) reading the HI
779 or LO register and then writing to it. If we are not already
780 emitting a NOP instruction, we must check for these cases
781 compared to the instruction previous to the previous
784 && (((prev_prev_insn
.insn_mo
->pinfo
& INSN_COPROC_MOVE_DELAY
)
785 && (prev_prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
)
786 && (pinfo
& INSN_READ_COND_CODE
))
787 || ((prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
)
788 && (pinfo
& INSN_WRITE_LO
))
789 || ((prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
790 && (pinfo
& INSN_WRITE_HI
))))
793 /* If we are being given a nop instruction, don't bother with
794 one of the nops we would otherwise output. This will only
795 happen when a nop instruction is used with mips_optimize set
797 if (nops
> 0 && ip
->insn_opcode
== 0)
800 /* Now emit the right number of NOP instructions. */
806 if (insn_label
!= NULL
)
808 assert (S_GET_SEGMENT (insn_label
) == now_seg
);
809 insn_label
->sy_frag
= frag_now
;
810 S_SET_VALUE (insn_label
, (valueT
) frag_now_fix ());
820 if (address_expr
!= NULL
)
822 if (address_expr
->X_op
== O_constant
)
827 ip
->insn_opcode
|= address_expr
->X_add_number
;
831 ip
->insn_opcode
|= address_expr
->X_add_number
& 0xffff;
834 case BFD_RELOC_MIPS_JMP
:
835 case BFD_RELOC_16_PCREL_S2
:
844 assert (reloc_type
!= BFD_RELOC_UNUSED
);
846 /* Don't generate a reloc if we are writing into a variant
849 fixp
= fix_new_exp (frag_now
, f
- frag_now
->fr_literal
, 4,
851 reloc_type
== BFD_RELOC_16_PCREL_S2
,
856 md_number_to_chars (f
, ip
->insn_opcode
, 4);
858 /* Update the register mask information. */
859 if (pinfo
& INSN_WRITE_GPR_D
)
860 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
);
861 if ((pinfo
& (INSN_WRITE_GPR_T
| INSN_READ_GPR_T
)) != 0)
862 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
);
863 if (pinfo
& INSN_READ_GPR_S
)
864 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> OP_SH_RS
) & OP_MASK_RS
);
865 if (pinfo
& INSN_WRITE_GPR_31
)
866 mips_gprmask
|= 1 << 31;
867 if (pinfo
& INSN_WRITE_FPR_D
)
868 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FD
) & OP_MASK_FD
);
869 if ((pinfo
& (INSN_WRITE_FPR_S
| INSN_READ_FPR_S
)) != 0)
870 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FS
) & OP_MASK_FS
);
871 if ((pinfo
& (INSN_WRITE_FPR_T
| INSN_READ_FPR_T
)) != 0)
872 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FT
) & OP_MASK_FT
);
873 if (pinfo
& INSN_COP
)
875 /* We don't keep enough information to sort these cases out. */
877 /* Never set the bit for $0, which is always zero. */
878 mips_gprmask
&=~ 1 << 0;
880 if (place
== NULL
&& ! mips_noreorder
)
882 /* Filling the branch delay slot is more complex. We try to
883 switch the branch with the previous instruction, which we can
884 do if the previous instruction does not set up a condition
885 that the branch tests and if the branch is not itself the
886 target of any branch. */
887 if ((pinfo
& INSN_UNCOND_BRANCH_DELAY
)
888 || (pinfo
& INSN_COND_BRANCH_DELAY
))
890 if (mips_optimize
< 2
891 /* If we have seen .set nobopt, don't optimize. */
893 /* If we have seen .set volatile or .set nomove, don't
896 /* If we had to emit any NOP instructions, then we
897 already know we can not swap. */
899 /* If we don't even know the previous insn, we can not
902 /* If the previous insn is already in a branch delay
903 slot, then we can not swap. */
904 || prev_insn_is_delay_slot
905 /* If the previous previous insn was in a .set
906 noreorder, we can't swap. Actually, the MIPS
907 assembler will swap in this situation. However, gcc
908 configured -with-gnu-as will generate code like
914 in which we can not swap the bne and INSN. If gcc is
915 not configured -with-gnu-as, it does not output the
916 .set pseudo-ops. We don't have to check
917 prev_insn_unreordered, because prev_insn_valid will
918 be 0 in that case. We don't want to use
919 prev_prev_insn_valid, because we do want to be able
920 to swap at the start of a function. */
921 || prev_prev_insn_unreordered
922 /* If the branch is itself the target of a branch, we
923 can not swap. We cheat on this; all we check for is
924 whether there is a label on this instruction. If
925 there are any branches to anything other than a
926 label, users must use .set noreorder. */
927 || insn_label
!= NULL
928 /* If the previous instruction is in a variant frag, we
929 can not do the swap. */
930 || prev_insn_frag
->fr_type
== rs_machine_dependent
931 /* If the branch reads the condition codes, we don't
932 even try to swap, because in the sequence
937 we can not swap, and I don't feel like handling that
939 || (pinfo
& INSN_READ_COND_CODE
)
940 /* We can not swap with an instruction that requires a
941 delay slot, becase the target of the branch might
942 interfere with that instruction. */
944 & (INSN_LOAD_COPROC_DELAY
945 | INSN_COPROC_MOVE_DELAY
946 | INSN_WRITE_COND_CODE
951 & (INSN_LOAD_MEMORY_DELAY
952 | INSN_COPROC_MEMORY_DELAY
)))
953 /* We can not swap with a branch instruction. */
955 & (INSN_UNCOND_BRANCH_DELAY
956 | INSN_COND_BRANCH_DELAY
957 | INSN_COND_BRANCH_LIKELY
))
958 /* We do not swap with a trap instruction, since it
959 complicates trap handlers to have the trap
960 instruction be in a delay slot. */
961 || (prev_pinfo
& INSN_TRAP
)
962 /* If the branch reads a register that the previous
963 instruction sets, we can not swap. */
964 || ((prev_pinfo
& INSN_WRITE_GPR_T
)
965 && insn_uses_reg (ip
,
966 ((prev_insn
.insn_opcode
>> OP_SH_RT
)
969 || ((prev_pinfo
& INSN_WRITE_GPR_D
)
970 && insn_uses_reg (ip
,
971 ((prev_insn
.insn_opcode
>> OP_SH_RD
)
974 /* If the branch writes a register that the previous
975 instruction sets, we can not swap (we know that
976 branches write only to RD or to $31). */
977 || ((prev_pinfo
& INSN_WRITE_GPR_T
)
978 && (((pinfo
& INSN_WRITE_GPR_D
)
979 && (((prev_insn
.insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
)
980 == ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)))
981 || ((pinfo
& INSN_WRITE_GPR_31
)
982 && (((prev_insn
.insn_opcode
>> OP_SH_RT
)
985 || ((prev_pinfo
& INSN_WRITE_GPR_D
)
986 && (((pinfo
& INSN_WRITE_GPR_D
)
987 && (((prev_insn
.insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)
988 == ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)))
989 || ((pinfo
& INSN_WRITE_GPR_31
)
990 && (((prev_insn
.insn_opcode
>> OP_SH_RD
)
993 /* If the branch writes a register that the previous
994 instruction reads, we can not swap (we know that
995 branches only write to RD or to $31). */
996 || ((pinfo
& INSN_WRITE_GPR_D
)
997 && insn_uses_reg (&prev_insn
,
998 ((ip
->insn_opcode
>> OP_SH_RD
)
1001 || ((pinfo
& INSN_WRITE_GPR_31
)
1002 && insn_uses_reg (&prev_insn
, 31, 0))
1003 /* If the previous previous instruction has a load
1004 delay, and sets a register that the branch reads, we
1006 || (((prev_prev_insn
.insn_mo
->pinfo
& INSN_LOAD_COPROC_DELAY
)
1008 && (prev_prev_insn
.insn_mo
->pinfo
1009 & INSN_LOAD_MEMORY_DELAY
)))
1010 && insn_uses_reg (ip
,
1011 ((prev_prev_insn
.insn_opcode
>> OP_SH_RT
)
1015 /* We could do even better for unconditional branches to
1016 portions of this object file; we could pick up the
1017 instruction at the destination, put it in the delay
1018 slot, and bump the destination address. */
1020 /* Update the previous insn information. */
1021 prev_prev_insn
= *ip
;
1022 prev_insn
.insn_mo
= &dummy_opcode
;
1029 /* It looks like we can actually do the swap. */
1030 prev_f
= prev_insn_frag
->fr_literal
+ prev_insn_where
;
1031 memcpy (temp
, prev_f
, 4);
1032 memcpy (prev_f
, f
, 4);
1033 memcpy (f
, temp
, 4);
1036 prev_insn_fixp
->fx_frag
= frag_now
;
1037 prev_insn_fixp
->fx_where
= f
- frag_now
->fr_literal
;
1041 fixp
->fx_frag
= prev_insn_frag
;
1042 fixp
->fx_where
= prev_insn_where
;
1044 /* Update the previous insn information; leave prev_insn
1046 prev_prev_insn
= *ip
;
1048 prev_insn_is_delay_slot
= 1;
1050 /* If that was an unconditional branch, forget the previous
1051 insn information. */
1052 if (pinfo
& INSN_UNCOND_BRANCH_DELAY
)
1054 prev_prev_insn
.insn_mo
= &dummy_opcode
;
1055 prev_insn
.insn_mo
= &dummy_opcode
;
1058 else if (pinfo
& INSN_COND_BRANCH_LIKELY
)
1060 /* We don't yet optimize a branch likely. What we should do
1061 is look at the target, copy the instruction found there
1062 into the delay slot, and increment the branch to jump to
1063 the next instruction. */
1065 /* Update the previous insn information. */
1066 prev_prev_insn
= *ip
;
1067 prev_insn
.insn_mo
= &dummy_opcode
;
1071 /* Update the previous insn information. */
1073 prev_prev_insn
.insn_mo
= &dummy_opcode
;
1075 prev_prev_insn
= prev_insn
;
1078 /* Any time we see a branch, we always fill the delay slot
1079 immediately; since this insn is not a branch, we know it
1080 is not in a delay slot. */
1081 prev_insn_is_delay_slot
= 0;
1084 prev_prev_insn_unreordered
= prev_insn_unreordered
;
1085 prev_insn_unreordered
= 0;
1086 prev_insn_frag
= frag_now
;
1087 prev_insn_where
= f
- frag_now
->fr_literal
;
1088 prev_insn_fixp
= fixp
;
1089 prev_insn_valid
= 1;
1092 /* We just output an insn, so the next one doesn't have a label. */
1096 /* This function forgets that there was any previous instruction or
1100 mips_no_prev_insn ()
1102 prev_insn
.insn_mo
= &dummy_opcode
;
1103 prev_prev_insn
.insn_mo
= &dummy_opcode
;
1104 prev_insn_valid
= 0;
1105 prev_insn_is_delay_slot
= 0;
1106 prev_insn_unreordered
= 0;
1107 prev_prev_insn_unreordered
= 0;
1111 /* This function must be called whenever we turn on noreorder or emit
1112 something other than instructions. It inserts any NOPS which might
1113 be needed by the previous instruction, and clears the information
1114 kept for the previous instructions. */
1119 if (! mips_noreorder
)
1124 if ((prev_insn
.insn_mo
->pinfo
1125 & (INSN_LOAD_COPROC_DELAY
1126 | INSN_COPROC_MOVE_DELAY
1127 | INSN_WRITE_COND_CODE
1131 && (prev_insn
.insn_mo
->pinfo
1132 & (INSN_LOAD_MEMORY_DELAY
1133 | INSN_COPROC_MEMORY_DELAY
))))
1136 if ((prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
)
1137 || (prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
1138 || (prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
))
1141 else if ((prev_prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
)
1142 || (prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
1143 || (prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
))
1148 if (insn_label
!= NULL
)
1150 assert (S_GET_SEGMENT (insn_label
) == now_seg
);
1151 insn_label
->sy_frag
= frag_now
;
1152 S_SET_VALUE (insn_label
, (valueT
) frag_now_fix ());
1155 mips_no_prev_insn ();
1159 /* Build an instruction created by a macro expansion. This is passed
1160 a pointer to the count of instructions created so far, an
1161 expression, the name of the instruction to build, an operand format
1162 string, and corresponding arguments. */
1166 macro_build (char *place
,
1172 #else /* ! defined (NO_STDARG) */
1174 macro_build (place
, counter
, ep
, name
, fmt
, va_alist
)
1181 #endif /* ! defined (NO_STDARG) */
1183 struct mips_cl_insn insn
;
1184 bfd_reloc_code_real_type r
;
1188 va_start (args
, fmt
);
1194 * If the macro is about to expand into a second instruction,
1195 * print a warning if needed. We need to pass ip as a parameter
1196 * to generate a better warning message here...
1198 if (mips_warn_about_macros
&& place
== NULL
&& *counter
== 1)
1199 as_warn ("Macro instruction expanded into multiple instructions");
1202 *counter
+= 1; /* bump instruction counter */
1204 r
= BFD_RELOC_UNUSED
;
1205 insn
.insn_mo
= (struct mips_opcode
*) hash_find (op_hash
, name
);
1206 assert (insn
.insn_mo
);
1207 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
1209 while (strcmp (fmt
, insn
.insn_mo
->args
) != 0
1210 || insn
.insn_mo
->pinfo
== INSN_MACRO
)
1213 assert (insn
.insn_mo
->name
);
1214 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
1216 insn
.insn_opcode
= insn
.insn_mo
->match
;
1232 insn
.insn_opcode
|= va_arg (args
, int) << 16;
1238 insn
.insn_opcode
|= va_arg (args
, int) << 16;
1243 insn
.insn_opcode
|= va_arg (args
, int) << 11;
1248 insn
.insn_opcode
|= va_arg (args
, int) << 11;
1255 insn
.insn_opcode
|= va_arg (args
, int) << 6;
1259 insn
.insn_opcode
|= va_arg (args
, int) << 6;
1263 insn
.insn_opcode
|= va_arg (args
, int) << 6;
1270 insn
.insn_opcode
|= va_arg (args
, int) << 21;
1276 r
= (bfd_reloc_code_real_type
) va_arg (args
, int);
1277 assert (r
== BFD_RELOC_MIPS_GPREL
1278 || r
== BFD_RELOC_MIPS_LITERAL
1279 || r
== BFD_RELOC_LO16
1280 || r
== BFD_RELOC_MIPS_GOT16
1281 || r
== BFD_RELOC_MIPS_CALL16
);
1285 assert (ep
!= NULL
&& ep
->X_op
== O_constant
);
1286 insn
.insn_opcode
|= (ep
->X_add_number
>> 16) & 0xffff;
1291 assert (ep
!= NULL
);
1293 * This allows macro() to pass an immediate expression for
1294 * creating short branches without creating a symbol.
1295 * Note that the expression still might come from the assembly
1296 * input, in which case the value is not checked for range nor
1297 * is a relocation entry generated (yuck).
1299 if (ep
->X_op
== O_constant
)
1301 insn
.insn_opcode
|= (ep
->X_add_number
>> 2) & 0xffff;
1305 r
= BFD_RELOC_16_PCREL_S2
;
1309 assert (ep
!= NULL
);
1310 r
= BFD_RELOC_MIPS_JMP
;
1319 assert (r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
1321 append_insn (place
, &insn
, ep
, r
);
1325 * Generate a "lui" instruction.
1328 macro_build_lui (place
, counter
, ep
, regnum
)
1334 expressionS high_expr
;
1335 struct mips_cl_insn insn
;
1336 bfd_reloc_code_real_type r
;
1337 CONST
char *name
= "lui";
1338 CONST
char *fmt
= "t,u";
1344 high_expr
.X_op
= O_constant
;
1345 high_expr
.X_add_number
= 0;
1348 if (high_expr
.X_op
== O_constant
)
1350 /* we can compute the instruction now without a relocation entry */
1351 if (high_expr
.X_add_number
& 0x8000)
1352 high_expr
.X_add_number
+= 0x10000;
1353 high_expr
.X_add_number
=
1354 ((unsigned long) high_expr
.X_add_number
>> 16) & 0xffff;
1355 r
= BFD_RELOC_UNUSED
;
1359 assert (ep
->X_op
== O_symbol
);
1360 /* _gp_disp is a special case, used from s_cpload. */
1361 assert (mips_pic
== 0
1362 || strcmp (S_GET_NAME (ep
->X_add_symbol
), "_gp_disp") == 0);
1363 r
= BFD_RELOC_HI16_S
;
1367 * If the macro is about to expand into a second instruction,
1368 * print a warning if needed. We need to pass ip as a parameter
1369 * to generate a better warning message here...
1371 if (mips_warn_about_macros
&& place
== NULL
&& *counter
== 1)
1372 as_warn ("Macro instruction expanded into multiple instructions");
1375 *counter
+= 1; /* bump instruction counter */
1377 insn
.insn_mo
= (struct mips_opcode
*) hash_find (op_hash
, name
);
1378 assert (insn
.insn_mo
);
1379 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
1380 assert (strcmp (fmt
, insn
.insn_mo
->args
) == 0);
1382 insn
.insn_opcode
= insn
.insn_mo
->match
| (regnum
<< OP_SH_RT
);
1383 if (r
== BFD_RELOC_UNUSED
)
1385 insn
.insn_opcode
|= high_expr
.X_add_number
;
1386 append_insn (place
, &insn
, NULL
, r
);
1389 append_insn (place
, &insn
, &high_expr
, r
);
1393 * Generates code to set the $at register to true (one)
1394 * if reg is less than the immediate expression.
1397 set_at (counter
, reg
, unsignedp
)
1402 if (imm_expr
.X_add_number
>= -0x8000 && imm_expr
.X_add_number
< 0x8000)
1403 macro_build ((char *) NULL
, counter
, &imm_expr
,
1404 unsignedp
? "sltiu" : "slti",
1405 "t,r,j", AT
, reg
, (int) BFD_RELOC_LO16
);
1408 load_register (counter
, AT
, &imm_expr
);
1409 macro_build ((char *) NULL
, counter
, NULL
,
1410 unsignedp
? "sltu" : "slt",
1411 "d,v,t", AT
, reg
, AT
);
1415 /* Warn if an expression is not a constant. */
1418 check_absolute_expr (ip
, ex
)
1419 struct mips_cl_insn
*ip
;
1422 if (ex
->X_op
!= O_constant
)
1423 as_warn ("Instruction %s requires absolute expression", ip
->insn_mo
->name
);
1427 * This routine generates the least number of instructions neccessary to load
1428 * an absolute expression value into a register.
1431 load_register (counter
, reg
, ep
)
1436 assert (ep
->X_op
== O_constant
);
1437 if (ep
->X_add_number
>= -0x8000 && ep
->X_add_number
< 0x8000)
1438 macro_build ((char *) NULL
, counter
, ep
,
1439 mips_isa
< 3 ? "addiu" : "daddiu",
1440 "t,r,j", reg
, 0, (int) BFD_RELOC_LO16
);
1441 else if (ep
->X_add_number
>= 0 && ep
->X_add_number
< 0x10000)
1442 macro_build ((char *) NULL
, counter
, ep
, "ori", "t,r,i", reg
, 0,
1443 (int) BFD_RELOC_LO16
);
1444 else if ((ep
->X_add_number
&~ (offsetT
) 0x7fffffff) == 0
1445 || ((ep
->X_add_number
&~ (offsetT
) 0x7fffffff)
1446 == ~ (offsetT
) 0x7fffffff))
1448 macro_build ((char *) NULL
, counter
, ep
, "lui", "t,u", reg
);
1449 if ((ep
->X_add_number
& 0xffff) != 0)
1450 macro_build ((char *) NULL
, counter
, ep
, "ori", "t,r,i", reg
, reg
,
1451 (int) BFD_RELOC_LO16
);
1453 else if (mips_isa
< 3)
1455 as_bad ("Number larger than 32 bits");
1456 macro_build ((char *) NULL
, counter
, ep
, "addiu", "t,r,j", reg
, 0,
1457 (int) BFD_RELOC_LO16
);
1462 expressionS hi32
, lo32
;
1466 hi32
.X_add_number
>>= shift
;
1467 hi32
.X_add_number
&= 0xffffffff;
1468 if ((hi32
.X_add_number
& 0x80000000) != 0)
1469 hi32
.X_add_number
|= ~ (offsetT
) 0xffffffff;
1470 load_register (counter
, reg
, &hi32
);
1472 lo32
.X_add_number
&= 0xffffffff;
1473 if ((lo32
.X_add_number
& 0xffff0000) == 0)
1474 macro_build ((char *) NULL
, counter
, NULL
, "dsll32", "d,w,<", reg
,
1480 macro_build ((char *) NULL
, counter
, NULL
, "dsll", "d,w,<", reg
,
1483 mid16
.X_add_number
>>= 16;
1484 macro_build ((char *) NULL
, counter
, &mid16
, "ori", "t,r,i", reg
,
1485 reg
, (int) BFD_RELOC_LO16
);
1486 macro_build ((char *) NULL
, counter
, NULL
, "dsll", "d,w,<", reg
,
1489 if ((lo32
.X_add_number
& 0xffff) != 0)
1490 macro_build ((char *) NULL
, counter
, &lo32
, "ori", "t,r,i", reg
, reg
,
1491 (int) BFD_RELOC_LO16
);
1495 /* Load an address into a register. */
1498 load_address (counter
, reg
, ep
)
1505 if (ep
->X_op
!= O_constant
1506 && ep
->X_op
!= O_symbol
)
1508 as_bad ("expression too complex");
1509 ep
->X_op
= O_constant
;
1512 if (ep
->X_op
== O_constant
)
1513 load_register (counter
, reg
, ep
);
1514 else if (mips_pic
== 0)
1516 /* If this is a reference to a GP relative symbol, we want
1517 addiu $reg,$gp,<sym> (BFD_RELOC_MIPS_GPREL)
1519 lui $reg,$gp,<sym> (BFD_RELOC_HI16_S)
1520 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
1521 If we have an addend, we always use the latter form. */
1522 if (ep
->X_add_number
!= 0)
1527 macro_build ((char *) NULL
, counter
, ep
,
1528 mips_isa
< 3 ? "addiu" : "daddiu",
1529 "t,r,j", reg
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
1530 p
= frag_var (rs_machine_dependent
, 8, 0,
1531 RELAX_ENCODE (4, 8, -4, 0, 0, mips_warn_about_macros
),
1532 ep
->X_add_symbol
, (long) 0, (char *) NULL
);
1534 macro_build_lui (p
, counter
, ep
, reg
);
1537 macro_build (p
, counter
, ep
,
1538 mips_isa
< 3 ? "addiu" : "daddiu",
1539 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
1545 /* If this is a reference to an external symbol, we want
1546 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
1548 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
1550 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
1551 If there is a constant, it must be added in afterward. */
1552 ex
.X_add_number
= ep
->X_add_number
;
1553 ep
->X_add_number
= 0;
1555 macro_build ((char *) NULL
, counter
, ep
,
1556 mips_isa
< 3 ? "lw" : "ld",
1557 "t,o(b)", reg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
1558 macro_build ((char *) NULL
, counter
, (expressionS
*) NULL
, "nop", "");
1559 p
= frag_var (rs_machine_dependent
, 4, 0,
1560 RELAX_ENCODE (0, 4, -8, 0, 0, mips_warn_about_macros
),
1561 ep
->X_add_symbol
, (long) 0, (char *) NULL
);
1562 macro_build (p
, counter
, ep
,
1563 mips_isa
< 3 ? "addiu" : "daddiu",
1564 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
1565 if (ex
.X_add_number
!= 0)
1567 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
1568 as_bad ("PIC code offset overflow (max 16 signed bits)");
1569 ex
.X_op
= O_constant
;
1570 macro_build (p
, counter
, &ex
,
1571 mips_isa
< 3 ? "addiu" : "daddiu",
1572 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
1579 * This routine implements the seemingly endless macro or synthesized
1580 * instructions and addressing modes in the mips assembly language. Many
1581 * of these macros are simple and are similar to each other. These could
1582 * probably be handled by some kind of table or grammer aproach instead of
1583 * this verbose method. Others are not simple macros but are more like
1584 * optimizing code generation.
1585 * One interesting optimization is when several store macros appear
1586 * consecutivly that would load AT with the upper half of the same address.
1587 * The ensuing load upper instructions are ommited. This implies some kind
1588 * of global optimization. We currently only optimize within a single macro.
1589 * For many of the load and store macros if the address is specified as a
1590 * constant expression in the first 64k of memory (ie ld $2,0x4000c) we
1591 * first load register 'at' with zero and use it as the base register. The
1592 * mips assembler simply uses register $zero. Just one tiny optimization
1597 struct mips_cl_insn
*ip
;
1599 register int treg
, sreg
, dreg
, breg
;
1612 bfd_reloc_code_real_type r
;
1615 treg
= (ip
->insn_opcode
>> 16) & 0x1f;
1616 dreg
= (ip
->insn_opcode
>> 11) & 0x1f;
1617 sreg
= breg
= (ip
->insn_opcode
>> 21) & 0x1f;
1618 mask
= ip
->insn_mo
->mask
;
1620 expr1
.X_op
= O_constant
;
1621 expr1
.X_op_symbol
= NULL
;
1622 expr1
.X_add_symbol
= NULL
;
1623 expr1
.X_add_number
= 1;
1635 mips_emit_delays ();
1637 mips_any_noreorder
= 1;
1639 expr1
.X_add_number
= 8;
1640 macro_build ((char *) NULL
, &icnt
, &expr1
, "bgez", "s,p", sreg
);
1642 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
1644 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
, sreg
, 0);
1645 macro_build ((char *) NULL
, &icnt
, NULL
,
1646 dbl
? "dsub" : "sub",
1647 "d,v,t", dreg
, 0, sreg
);
1670 if (imm_expr
.X_add_number
>= -0x8000 && imm_expr
.X_add_number
< 0x8000)
1672 macro_build ((char *) NULL
, &icnt
, &imm_expr
, s
, "t,r,j", treg
, sreg
,
1673 (int) BFD_RELOC_LO16
);
1676 load_register (&icnt
, AT
, &imm_expr
);
1677 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "d,v,t", treg
, sreg
, AT
);
1696 if (imm_expr
.X_add_number
>= 0 && imm_expr
.X_add_number
< 0x10000)
1698 if (mask
!= M_NOR_I
)
1699 macro_build ((char *) NULL
, &icnt
, &imm_expr
, s
, "t,r,i", treg
,
1700 sreg
, (int) BFD_RELOC_LO16
);
1703 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "ori", "t,r,i",
1704 treg
, sreg
, (int) BFD_RELOC_LO16
);
1705 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "nor", "d,v,t",
1711 load_register (&icnt
, AT
, &imm_expr
);
1712 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "d,v,t", treg
, sreg
, AT
);
1729 if (imm_expr
.X_add_number
== 0)
1731 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "s,t,p", sreg
,
1735 load_register (&icnt
, AT
, &imm_expr
);
1736 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "s,t,p", sreg
, AT
);
1744 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
1745 likely
? "bgezl" : "bgez",
1751 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
1752 likely
? "blezl" : "blez",
1756 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", AT
, sreg
, treg
);
1757 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
1758 likely
? "beql" : "beq",
1765 /* check for > max integer */
1766 maxnum
= 0x7fffffff;
1774 if (imm_expr
.X_add_number
>= maxnum
)
1777 /* result is always false */
1780 as_warn ("Branch %s is always false (nop)", ip
->insn_mo
->name
);
1781 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
1785 as_warn ("Branch likely %s is always false", ip
->insn_mo
->name
);
1786 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "bnel",
1791 imm_expr
.X_add_number
++;
1795 if (mask
== M_BGEL_I
)
1797 if (imm_expr
.X_add_number
== 0)
1799 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
1800 likely
? "bgezl" : "bgez",
1804 if (imm_expr
.X_add_number
== 1)
1806 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
1807 likely
? "bgtzl" : "bgtz",
1811 maxnum
= 0x7fffffff;
1819 maxnum
= - maxnum
- 1;
1820 if (imm_expr
.X_add_number
<= maxnum
)
1823 /* result is always true */
1824 as_warn ("Branch %s is always true", ip
->insn_mo
->name
);
1825 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "b", "p");
1828 set_at (&icnt
, sreg
, 0);
1829 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
1830 likely
? "beql" : "beq",
1841 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
1842 likely
? "beql" : "beq",
1846 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", AT
, sreg
,
1848 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
1849 likely
? "beql" : "beq",
1856 if (sreg
== 0 || imm_expr
.X_add_number
== -1)
1858 imm_expr
.X_add_number
++;
1862 if (mask
== M_BGEUL_I
)
1864 if (imm_expr
.X_add_number
== 0)
1866 if (imm_expr
.X_add_number
== 1)
1868 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
1869 likely
? "bnel" : "bne",
1873 set_at (&icnt
, sreg
, 1);
1874 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
1875 likely
? "beql" : "beq",
1884 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
1885 likely
? "bgtzl" : "bgtz",
1891 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
1892 likely
? "bltzl" : "bltz",
1896 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", AT
, treg
, sreg
);
1897 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
1898 likely
? "bnel" : "bne",
1907 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
1908 likely
? "bnel" : "bne",
1914 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", AT
, treg
,
1916 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
1917 likely
? "bnel" : "bne",
1926 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
1927 likely
? "blezl" : "blez",
1933 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
1934 likely
? "bgezl" : "bgez",
1938 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", AT
, treg
, sreg
);
1939 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
1940 likely
? "beql" : "beq",
1947 maxnum
= 0x7fffffff;
1955 if (imm_expr
.X_add_number
>= maxnum
)
1957 imm_expr
.X_add_number
++;
1961 if (mask
== M_BLTL_I
)
1963 if (imm_expr
.X_add_number
== 0)
1965 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
1966 likely
? "bltzl" : "bltz",
1970 if (imm_expr
.X_add_number
== 1)
1972 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
1973 likely
? "blezl" : "blez",
1977 set_at (&icnt
, sreg
, 0);
1978 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
1979 likely
? "bnel" : "bne",
1988 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
1989 likely
? "beql" : "beq",
1995 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", AT
, treg
,
1997 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
1998 likely
? "beql" : "beq",
2005 if (sreg
== 0 || imm_expr
.X_add_number
== -1)
2007 imm_expr
.X_add_number
++;
2011 if (mask
== M_BLTUL_I
)
2013 if (imm_expr
.X_add_number
== 0)
2015 if (imm_expr
.X_add_number
== 1)
2017 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2018 likely
? "beql" : "beq",
2022 set_at (&icnt
, sreg
, 1);
2023 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2024 likely
? "bnel" : "bne",
2033 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2034 likely
? "bltzl" : "bltz",
2040 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2041 likely
? "bgtzl" : "bgtz",
2045 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", AT
, sreg
, treg
);
2046 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2047 likely
? "bnel" : "bne",
2058 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2059 likely
? "bnel" : "bne",
2063 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", AT
, sreg
,
2065 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2066 likely
? "bnel" : "bne",
2082 as_warn ("Divide by zero.");
2083 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 7);
2087 mips_emit_delays ();
2089 mips_any_noreorder
= 1;
2090 macro_build ((char *) NULL
, &icnt
, NULL
,
2091 dbl
? "ddiv" : "div",
2092 "z,s,t", sreg
, treg
);
2093 expr1
.X_add_number
= 8;
2094 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", treg
, 0);
2095 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
2096 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 7);
2097 expr1
.X_add_number
= -1;
2098 macro_build ((char *) NULL
, &icnt
, &expr1
,
2099 dbl
? "daddiu" : "addiu",
2100 "t,r,j", AT
, 0, (int) BFD_RELOC_LO16
);
2101 expr1
.X_add_number
= dbl
? 20 : 16;
2102 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", treg
, AT
);
2105 expr1
.X_add_number
= 1;
2106 macro_build ((char *) NULL
, &icnt
, &expr1
, "daddiu", "t,r,j", AT
, 0,
2107 (int) BFD_RELOC_LO16
);
2108 macro_build ((char *) NULL
, &icnt
, NULL
, "dsll32", "d,w,<", AT
, AT
,
2113 expr1
.X_add_number
= 0x80000000;
2114 macro_build ((char *) NULL
, &icnt
, &expr1
, "lui", "t,u", AT
);
2116 expr1
.X_add_number
= 8;
2117 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", sreg
, AT
);
2118 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
2119 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 6);
2121 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d", dreg
);
2160 if (imm_expr
.X_add_number
== 0)
2162 as_warn ("Divide by zero.");
2163 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 7);
2166 if (imm_expr
.X_add_number
== 1)
2168 if (strcmp (s2
, "mflo") == 0)
2169 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
,
2172 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
, 0);
2175 if (imm_expr
.X_add_number
== -1
2176 && s
[strlen (s
) - 1] != 'u')
2178 if (strcmp (s2
, "mflo") == 0)
2181 macro_build ((char *) NULL
, &icnt
, NULL
, "dneg", "d,w", dreg
,
2184 macro_build ((char *) NULL
, &icnt
, NULL
, "neg", "d,w", dreg
,
2188 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
, 0);
2192 load_register (&icnt
, AT
, &imm_expr
);
2193 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "z,s,t", sreg
, AT
);
2194 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "d", dreg
);
2213 mips_emit_delays ();
2215 mips_any_noreorder
= 1;
2216 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "z,s,t", sreg
, treg
);
2217 expr1
.X_add_number
= 8;
2218 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", treg
, 0);
2219 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
2220 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 7);
2222 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "d", dreg
);
2226 /* Load the address of a symbol into a register. If M_LA_AB, we
2227 then add a base register to it. */
2228 if (offset_expr
.X_op
!= O_symbol
2229 && offset_expr
.X_op
!= O_constant
)
2231 as_bad ("expression too complex");
2232 offset_expr
.X_op
= O_constant
;
2246 if (offset_expr
.X_op
== O_constant
)
2247 load_register (&icnt
, tempreg
, &offset_expr
);
2248 else if (mips_pic
== 0)
2250 /* If this is a reference to an GP relative symbol, we want
2251 addiu $tempreg,$gp,<sym> (BFD_RELOC_MIPS_GPREL)
2253 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
2254 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
2255 If we have a constant, we need two instructions anyhow,
2256 so we may as well always use the latter form. */
2257 if (offset_expr
.X_add_number
!= 0)
2262 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2263 mips_isa
< 3 ? "addiu" : "daddiu",
2264 "t,r,j", tempreg
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
2265 p
= frag_var (rs_machine_dependent
, 8, 0,
2266 RELAX_ENCODE (4, 8, 0, 4, 0,
2267 mips_warn_about_macros
),
2268 offset_expr
.X_add_symbol
, (long) 0,
2271 macro_build_lui (p
, &icnt
, &offset_expr
, tempreg
);
2274 macro_build (p
, &icnt
, &offset_expr
,
2275 mips_isa
< 3 ? "addiu" : "daddiu",
2276 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
2280 /* If this is a reference to an external symbol, and there
2281 is no constant, we want
2282 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
2283 For a local symbol, we want
2284 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
2286 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
2288 If we have a small constant, and this is a reference to
2289 an external symbol, we want
2290 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
2292 addiu $tempreg,$tempreg,<constant>
2293 For a local symbol, we want the same instruction
2294 sequence, but we output a BFD_RELOC_LO16 reloc on the
2297 If we have a large constant, and this is a reference to
2298 an external symbol, we want
2299 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
2300 lui $at,<hiconstant>
2301 addiu $at,$at,<loconstant>
2302 addu $tempreg,$tempreg,$at
2303 For a local symbol, we want the same instruction
2304 sequence, but we output a BFD_RELOC_LO16 reloc on the
2305 addiu instruction. */
2306 expr1
.X_add_number
= offset_expr
.X_add_number
;
2307 offset_expr
.X_add_number
= 0;
2309 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2310 mips_isa
< 3 ? "lw" : "ld",
2311 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
2312 if (expr1
.X_add_number
== 0)
2320 /* We're going to put in an addu instruction using
2321 tempreg, so we may as well insert the nop right
2323 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
2327 p
= frag_var (rs_machine_dependent
, 8 - off
, 0,
2328 RELAX_ENCODE (0, 8 - off
, -4 - off
, 4 - off
, 0,
2330 ? mips_warn_about_macros
2332 offset_expr
.X_add_symbol
, (long) 0,
2336 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
2339 macro_build (p
, &icnt
, &expr1
,
2340 mips_isa
< 3 ? "addiu" : "daddiu",
2341 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
2342 /* FIXME: If breg == 0, and the next instruction uses
2343 $tempreg, then if this variant case is used an extra
2344 nop will be generated. */
2346 else if (expr1
.X_add_number
>= -0x8000
2347 && expr1
.X_add_number
< 0x8000)
2349 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
2351 macro_build ((char *) NULL
, &icnt
, &expr1
,
2352 mips_isa
< 3 ? "addiu" : "daddiu",
2353 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
2354 (void) frag_var (rs_machine_dependent
, 0, 0,
2355 RELAX_ENCODE (0, 0, -12, -4, 0, 0),
2356 offset_expr
.X_add_symbol
, (long) 0,
2363 /* If we are going to add in a base register, and the
2364 target register and the base register are the same,
2365 then we are using AT as a temporary register. Since
2366 we want to load the constant into AT, we add our
2367 current AT (from the global offset table) and the
2368 register into the register now, and pretend we were
2369 not using a base register. */
2374 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
2376 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
2377 mips_isa
< 3 ? "addu" : "daddu",
2378 "d,v,t", treg
, AT
, breg
);
2384 macro_build_lui ((char *) NULL
, &icnt
, &expr1
, AT
);
2385 macro_build ((char *) NULL
, &icnt
, &expr1
,
2386 mips_isa
< 3 ? "addiu" : "daddiu",
2387 "t,r,j", AT
, AT
, (int) BFD_RELOC_LO16
);
2388 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
2389 mips_isa
< 3 ? "addu" : "daddu",
2390 "d,v,t", tempreg
, tempreg
, AT
);
2391 (void) frag_var (rs_machine_dependent
, 0, 0,
2392 RELAX_ENCODE (0, 0, -16 + off1
, -8, 0, 0),
2393 offset_expr
.X_add_symbol
, (long) 0,
2400 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
2401 mips_isa
< 3 ? "addu" : "daddu",
2402 "d,v,t", treg
, tempreg
, breg
);
2410 /* The j instruction may not be used in PIC code, since it
2411 requires an absolute address. We convert it to a b
2414 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "j", "a");
2416 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "b", "p");
2419 /* The jal instructions must be handled as macros because when
2420 generating PIC code they expand to multi-instruction
2421 sequences. Normally they are simple instructions. */
2428 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "jalr",
2433 /* I only know how to handle pic2. */
2434 assert (mips_pic
== 2);
2436 if (sreg
!= PIC_CALL_REG
)
2437 as_warn ("MIPS PIC call to register other than $25");
2439 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "jalr", "d,s",
2441 if (mips_cprestore_offset
< 0)
2442 as_warn ("No .cprestore pseudo-op used in PIC code");
2445 expr1
.X_add_number
= mips_cprestore_offset
;
2446 macro_build ((char *) NULL
, &icnt
, &expr1
,
2447 mips_isa
< 3 ? "lw" : "ld",
2448 "t,o(b)", GP
, (int) BFD_RELOC_LO16
, mips_frame_reg
);
2455 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "jal", "a");
2459 /* I only know how to handle pic2. */
2460 assert (mips_pic
== 2);
2462 /* If this is a reference to an external symbol, we want
2463 lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
2467 lw $gp,cprestore($sp)
2468 The cprestore value is set using the .cprestore pseudo-op.
2469 If the symbol is not external, we want
2470 lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
2472 addiu $25,$25,<sym> (BFD_RELOC_LO16)
2475 lw $gp,cprestore($sp)
2478 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2479 mips_isa
< 3 ? "lw" : "ld",
2480 "t,o(b)", PIC_CALL_REG
, (int) BFD_RELOC_MIPS_CALL16
, GP
);
2481 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
2482 p
= frag_var (rs_machine_dependent
, 4, 0,
2483 RELAX_ENCODE (0, 4, -8, 0, 0, 0),
2484 offset_expr
.X_add_symbol
, (long) 0, (char *) NULL
);
2485 macro_build (p
, &icnt
, &offset_expr
,
2486 mips_isa
< 3 ? "addiu" : "daddiu",
2487 "t,r,j", PIC_CALL_REG
, PIC_CALL_REG
,
2488 (int) BFD_RELOC_LO16
);
2489 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "jalr", "s",
2491 if (mips_cprestore_offset
< 0)
2492 as_warn ("No .cprestore pseudo-op used in PIC code");
2496 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
2498 expr1
.X_add_number
= mips_cprestore_offset
;
2499 macro_build ((char *) NULL
, &icnt
, &expr1
,
2500 mips_isa
< 3 ? "lw" : "ld",
2501 "t,o(b)", GP
, (int) BFD_RELOC_LO16
, mips_frame_reg
);
2569 if (breg
== treg
|| coproc
)
2638 if (mask
== M_LWC1_AB
2639 || mask
== M_SWC1_AB
2640 || mask
== M_LDC1_AB
2641 || mask
== M_SDC1_AB
2650 if (offset_expr
.X_op
!= O_constant
2651 && offset_expr
.X_op
!= O_symbol
)
2653 as_bad ("expression too complex");
2654 offset_expr
.X_op
= O_constant
;
2657 /* A constant expression in PIC code can be handled just as it
2658 is in non PIC code. */
2660 || offset_expr
.X_op
== O_constant
)
2662 /* If this is a reference to a GP relative symbol, and there
2663 is no base register, we want
2664 <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL)
2666 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
2667 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
2668 If we have a constant, we need two instructions anyhow,
2669 so we always use the latter form.
2671 If we have a base register, and this is a reference to a
2672 GP relative symbol, we want
2673 addu $tempreg,$breg,$gp
2674 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GPREL)
2676 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
2677 addu $tempreg,$tempreg,$breg
2678 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
2679 With a constant we always use the latter case. */
2682 if (offset_expr
.X_add_number
!= 0)
2687 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
2688 treg
, (int) BFD_RELOC_MIPS_GPREL
, GP
);
2689 p
= frag_var (rs_machine_dependent
, 8, 0,
2690 RELAX_ENCODE (4, 8, 0, 4, 0,
2691 mips_warn_about_macros
),
2692 offset_expr
.X_add_symbol
, (long) 0,
2695 macro_build_lui (p
, &icnt
, &offset_expr
, tempreg
);
2698 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
, treg
,
2699 (int) BFD_RELOC_LO16
, tempreg
);
2703 if (offset_expr
.X_add_number
!= 0)
2708 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
2709 mips_isa
< 3 ? "addu" : "daddu",
2710 "d,v,t", tempreg
, breg
, GP
);
2711 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
2712 treg
, (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
2713 p
= frag_var (rs_machine_dependent
, 12, 0,
2714 RELAX_ENCODE (8, 12, 0, 8, 0, 0),
2715 offset_expr
.X_add_symbol
, (long) 0,
2718 macro_build_lui (p
, &icnt
, &offset_expr
, tempreg
);
2721 macro_build (p
, &icnt
, (expressionS
*) NULL
,
2722 mips_isa
< 3 ? "addu" : "daddu",
2723 "d,v,t", tempreg
, tempreg
, breg
);
2726 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
, treg
,
2727 (int) BFD_RELOC_LO16
, tempreg
);
2732 /* If this is a reference to an external symbol, we want
2733 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
2735 <op> $treg,0($tempreg)
2737 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
2739 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
2740 <op> $treg,0($tempreg)
2741 If there is a base register, we add it to $tempreg before
2742 the <op>. If there is a constant, we stick it in the
2743 <op> instruction. We don't handle constants larger than
2744 16 bits, because we have no way to load the upper 16 bits
2745 (actually, we could handle them for the subset of cases
2746 in which we are not using $at). */
2747 assert (offset_expr
.X_op
== O_symbol
);
2748 expr1
.X_add_number
= offset_expr
.X_add_number
;
2749 offset_expr
.X_add_number
= 0;
2750 if (expr1
.X_add_number
< -0x8000
2751 || expr1
.X_add_number
>= 0x8000)
2752 as_bad ("PIC code offset overflow (max 16 signed bits)");
2754 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2755 mips_isa
< 3 ? "lw" : "ld",
2756 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
2757 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
2758 p
= frag_var (rs_machine_dependent
, 4, 0,
2759 RELAX_ENCODE (0, 4, -8, 0, 0, 0),
2760 offset_expr
.X_add_symbol
, (long) 0,
2762 macro_build (p
, &icnt
, &offset_expr
,
2763 mips_isa
< 3 ? "addiu" : "daddiu",
2764 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
2766 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
2767 mips_isa
< 3 ? "addu" : "daddu",
2768 "d,v,t", tempreg
, tempreg
, breg
);
2769 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
, treg
,
2770 (int) BFD_RELOC_LO16
, tempreg
);
2780 load_register (&icnt
, treg
, &imm_expr
);
2786 assert (offset_expr
.X_op
== O_symbol
2787 && strcmp (segment_name (S_GET_SEGMENT
2788 (offset_expr
.X_add_symbol
)),
2790 && offset_expr
.X_add_number
== 0);
2791 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lwc1", "T,o(b)",
2792 treg
, (int) BFD_RELOC_MIPS_LITERAL
, GP
);
2796 assert (imm_expr
.X_op
== O_constant
);
2797 load_register (&icnt
, treg
, &imm_expr
);
2802 /* We know that sym is in the .rdata instruction. First we get
2803 the upper 16 bits of the address. */
2806 /* FIXME: This won't work for a 64 bit address. */
2807 macro_build_lui ((char *) NULL
, &icnt
, &offset_expr
, AT
);
2811 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2812 mips_isa
< 3 ? "lw" : "ld",
2813 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
2815 /* Now we load the register(s). */
2817 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "ld", "t,o(b)",
2818 treg
, (int) BFD_RELOC_LO16
, AT
);
2821 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lw", "t,o(b)",
2822 treg
, (int) BFD_RELOC_LO16
, AT
);
2825 /* FIXME: How in the world do we deal with the possible
2827 offset_expr
.X_add_number
+= 4;
2828 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lw", "t,o(b)",
2829 treg
+ 1, (int) BFD_RELOC_LO16
, AT
);
2838 /* Load a floating point number from the .lit8 section. */
2839 assert (offset_expr
.X_op
== O_symbol
2840 && strcmp (segment_name (S_GET_SEGMENT
2841 (offset_expr
.X_add_symbol
)),
2843 && offset_expr
.X_add_number
== 0);
2846 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "ldc1",
2847 "T,o(b)", treg
, (int) BFD_RELOC_MIPS_LITERAL
, GP
);
2851 r
= BFD_RELOC_MIPS_LITERAL
;
2856 /* Load the double from the .rdata section. */
2857 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2858 mips_isa
< 3 ? "lw" : "ld",
2859 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
2862 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "ldc1",
2863 "T,o(b)", treg
, (int) BFD_RELOC_LO16
, GP
);
2872 /* Even on a big endian machine $fn comes before $fn+1. We have
2873 to adjust when loading from memory. */
2876 assert (mips_isa
< 2);
2877 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lwc1", "T,o(b)",
2878 byte_order
== LITTLE_ENDIAN
? treg
: treg
+ 1,
2880 /* FIXME: A possible overflow which I don't know how to deal
2882 offset_expr
.X_add_number
+= 4;
2883 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lwc1", "T,o(b)",
2884 byte_order
== LITTLE_ENDIAN
? treg
+ 1 : treg
,
2892 * The MIPS assembler seems to check for X_add_number not
2893 * being double aligned and generating:
2896 * addiu at,at,%lo(foo+1)
2899 * But, the resulting address is the same after relocation so why
2900 * generate the extra instruction?
2947 if (offset_expr
.X_op
!= O_symbol
2948 && offset_expr
.X_op
!= O_constant
)
2950 as_bad ("expression too complex");
2951 offset_expr
.X_op
= O_constant
;
2954 /* Even on a big endian machine $fn comes before $fn+1. We have
2955 to adjust when loading from memory. We set coproc if we must
2956 load $fn+1 first. */
2957 if (byte_order
== LITTLE_ENDIAN
)
2961 || offset_expr
.X_op
== O_constant
)
2963 /* If this is a reference to a GP relative symbol, we want
2964 <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL)
2965 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_MIPS_GPREL)
2966 If we have a base register, we use this
2968 <op> $treg,<sym>($at) (BFD_RELOC_MIPS_GPREL)
2969 <op> $treg+1,<sym>+4($at) (BFD_RELOC_MIPS_GPREL)
2970 If this is not a GP relative symbol, we want
2971 lui $at,<sym> (BFD_RELOC_HI16_S)
2972 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
2973 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
2974 If there is a base register, we add it to $at after the
2975 lui instruction. If there is a constant, we always use
2977 if (offset_expr
.X_add_number
!= 0)
2996 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
2997 mips_isa
< 3 ? "addu" : "daddu",
2998 "d,v,t", AT
, breg
, GP
);
3004 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
3005 coproc
? treg
+ 1 : treg
,
3006 (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
3007 offset_expr
.X_add_number
+= 4;
3008 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
3009 coproc
? treg
: treg
+ 1,
3010 (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
3011 p
= frag_var (rs_machine_dependent
, 12 + off
, 0,
3012 RELAX_ENCODE (8 + off
, 12 + off
, 0, 4 + off
, 1,
3013 ! used_at
&& mips_noat
),
3014 offset_expr
.X_add_symbol
, (long) 0,
3017 /* We just generated two relocs. When tc_gen_reloc
3018 handles this case, it will skip the first reloc and
3019 handle the second. The second reloc already has an
3020 extra addend of 4, which we added above. We must
3021 subtract it out, and then subtract another 4 to make
3022 the first reloc come out right. The second reloc
3023 will come out right because we are going to add 4 to
3024 offset_expr when we build its instruction below. */
3025 offset_expr
.X_add_number
-= 8;
3026 offset_expr
.X_op
= O_constant
;
3028 macro_build_lui (p
, &icnt
, &offset_expr
, AT
);
3033 macro_build (p
, &icnt
, (expressionS
*) NULL
,
3034 mips_isa
< 3 ? "addu" : "daddu",
3035 "d,v,t", AT
, breg
, AT
);
3039 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
,
3040 coproc
? treg
+ 1 : treg
,
3041 (int) BFD_RELOC_LO16
, AT
);
3044 /* FIXME: How do we handle overflow here? */
3045 offset_expr
.X_add_number
+= 4;
3046 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
,
3047 coproc
? treg
: treg
+ 1,
3048 (int) BFD_RELOC_LO16
, AT
);
3054 /* If this is a reference to an external symbol, we want
3055 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3060 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3062 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
3063 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
3064 If there is a base register we add it to $at before the
3065 lwc1 instructions. If there is a constant we include it
3066 in the lwc1 instructions. */
3068 expr1
.X_add_number
= offset_expr
.X_add_number
;
3069 offset_expr
.X_add_number
= 0;
3070 if (expr1
.X_add_number
< -0x8000
3071 || expr1
.X_add_number
>= 0x8000 - 4)
3072 as_bad ("PIC code offset overflow (max 16 signed bits)");
3077 frag_grow (16 + off
);
3078 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3079 mips_isa
< 3 ? "lw" : "ld",
3080 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
3081 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
3083 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3084 mips_isa
< 3 ? "addu" : "daddu",
3085 "d,v,t", AT
, breg
, AT
);
3086 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
3087 coproc
? treg
+ 1 : treg
,
3088 (int) BFD_RELOC_LO16
, AT
);
3089 expr1
.X_add_number
+= 4;
3090 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
3091 coproc
? treg
: treg
+ 1,
3092 (int) BFD_RELOC_LO16
, AT
);
3093 (void) frag_var (rs_machine_dependent
, 0, 0,
3094 RELAX_ENCODE (0, 0, -16 - off
, -8, 1, 0),
3095 offset_expr
.X_add_symbol
, (long) 0,
3110 assert (mips_isa
< 3);
3111 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
3112 (int) BFD_RELOC_LO16
, breg
);
3113 offset_expr
.X_add_number
+= 4;
3114 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
+ 1,
3115 (int) BFD_RELOC_LO16
, breg
);
3117 #ifdef LOSING_COMPILER
3123 as_warn ("Macro used $at after \".set noat\"");
3128 struct mips_cl_insn
*ip
;
3130 register int treg
, sreg
, dreg
, breg
;
3143 bfd_reloc_code_real_type r
;
3146 treg
= (ip
->insn_opcode
>> 16) & 0x1f;
3147 dreg
= (ip
->insn_opcode
>> 11) & 0x1f;
3148 sreg
= breg
= (ip
->insn_opcode
>> 21) & 0x1f;
3149 mask
= ip
->insn_mo
->mask
;
3151 expr1
.X_op
= O_constant
;
3152 expr1
.X_op_symbol
= NULL
;
3153 expr1
.X_add_symbol
= NULL
;
3154 expr1
.X_add_number
= 1;
3158 #endif /* LOSING_COMPILER */
3163 macro_build ((char *) NULL
, &icnt
, NULL
,
3164 dbl
? "dmultu" : "multu",
3166 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
3172 /* The MIPS assembler some times generates shifts and adds. I'm
3173 not trying to be that fancy. GCC should do this for us
3175 load_register (&icnt
, AT
, &imm_expr
);
3176 macro_build ((char *) NULL
, &icnt
, NULL
,
3177 dbl
? "dmult" : "mult",
3179 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
3185 mips_emit_delays ();
3187 mips_any_noreorder
= 1;
3188 macro_build ((char *) NULL
, &icnt
, NULL
,
3189 dbl
? "dmult" : "mult",
3191 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
3192 macro_build ((char *) NULL
, &icnt
, NULL
,
3193 dbl
? "dsra32" : "sra",
3194 "d,w,<", dreg
, dreg
, 31);
3195 macro_build ((char *) NULL
, &icnt
, NULL
, "mfhi", "d", AT
);
3196 expr1
.X_add_number
= 8;
3197 macro_build ((char *) NULL
, &icnt
, &expr1
, "beq", "s,t,p", dreg
, AT
);
3198 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
3199 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 6);
3201 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
3207 mips_emit_delays ();
3209 mips_any_noreorder
= 1;
3210 macro_build ((char *) NULL
, &icnt
, NULL
,
3211 dbl
? "dmultu" : "multu",
3213 macro_build ((char *) NULL
, &icnt
, NULL
, "mfhi", "d", AT
);
3214 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
3215 expr1
.X_add_number
= 8;
3216 macro_build ((char *) NULL
, &icnt
, &expr1
, "beq", "s,t,p", AT
, 0);
3217 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
3218 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 6);
3223 macro_build ((char *) NULL
, &icnt
, NULL
, "subu", "d,v,t", AT
, 0, treg
);
3224 macro_build ((char *) NULL
, &icnt
, NULL
, "srlv", "d,t,s", AT
, sreg
, AT
);
3225 macro_build ((char *) NULL
, &icnt
, NULL
, "sllv", "d,t,s", dreg
, sreg
,
3227 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
3231 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", AT
, sreg
,
3232 imm_expr
.X_add_number
& 0x1f);
3233 macro_build ((char *) NULL
, &icnt
, NULL
, "srl", "d,w,<", dreg
, sreg
,
3234 (0 - imm_expr
.X_add_number
) & 0x1f);
3235 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
3239 macro_build ((char *) NULL
, &icnt
, NULL
, "subu", "d,v,t", AT
, 0, treg
);
3240 macro_build ((char *) NULL
, &icnt
, NULL
, "sllv", "d,t,s", AT
, sreg
, AT
);
3241 macro_build ((char *) NULL
, &icnt
, NULL
, "srlv", "d,t,s", dreg
, sreg
,
3243 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
3247 macro_build ((char *) NULL
, &icnt
, NULL
, "srl", "d,w,<", AT
, sreg
,
3248 imm_expr
.X_add_number
& 0x1f);
3249 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", dreg
, sreg
,
3250 (0 - imm_expr
.X_add_number
) & 0x1f);
3251 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
3255 assert (mips_isa
< 2);
3256 /* Even on a big endian machine $fn comes before $fn+1. We have
3257 to adjust when storing to memory. */
3258 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "swc1", "T,o(b)",
3259 byte_order
== LITTLE_ENDIAN
? treg
: treg
+ 1,
3260 (int) BFD_RELOC_LO16
, breg
);
3261 offset_expr
.X_add_number
+= 4;
3262 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "swc1", "T,o(b)",
3263 byte_order
== LITTLE_ENDIAN
? treg
+ 1 : treg
,
3264 (int) BFD_RELOC_LO16
, breg
);
3269 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
3270 treg
, (int) BFD_RELOC_LO16
);
3272 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
3273 sreg
, (int) BFD_RELOC_LO16
);
3276 macro_build ((char *) NULL
, &icnt
, NULL
, "xor", "d,v,t", dreg
,
3278 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
3279 dreg
, (int) BFD_RELOC_LO16
);
3284 if (imm_expr
.X_add_number
== 0)
3286 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
3287 sreg
, (int) BFD_RELOC_LO16
);
3292 as_warn ("Instruction %s: result is always false",
3294 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
, 0);
3297 if (imm_expr
.X_add_number
>= 0 && imm_expr
.X_add_number
< 0x10000)
3299 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "xori", "t,r,i", dreg
,
3300 sreg
, (int) BFD_RELOC_LO16
);
3303 else if (imm_expr
.X_add_number
> -0x8000 && imm_expr
.X_add_number
< 0)
3305 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
3306 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
3307 mips_isa
< 3 ? "addiu" : "daddiu",
3308 "t,r,j", dreg
, sreg
,
3309 (int) BFD_RELOC_LO16
);
3314 load_register (&icnt
, AT
, &imm_expr
);
3315 macro_build ((char *) NULL
, &icnt
, NULL
, "xor", "d,v,t", dreg
,
3319 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
, dreg
,
3320 (int) BFD_RELOC_LO16
);
3325 case M_SGE
: /* sreg >= treg <==> not (sreg < treg) */
3331 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, sreg
, treg
);
3332 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
3333 (int) BFD_RELOC_LO16
);
3336 case M_SGE_I
: /* sreg >= I <==> not (sreg < I) */
3338 if (imm_expr
.X_add_number
>= -0x8000 && imm_expr
.X_add_number
< 0x8000)
3340 macro_build ((char *) NULL
, &icnt
, &expr1
,
3341 mask
== M_SGE_I
? "slti" : "sltiu",
3342 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
3347 load_register (&icnt
, AT
, &imm_expr
);
3348 macro_build ((char *) NULL
, &icnt
, NULL
,
3349 mask
== M_SGE_I
? "slt" : "sltu",
3350 "d,v,t", dreg
, sreg
, AT
);
3353 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
3354 (int) BFD_RELOC_LO16
);
3359 case M_SGT
: /* sreg > treg <==> treg < sreg */
3365 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, treg
, sreg
);
3368 case M_SGT_I
: /* sreg > I <==> I < sreg */
3374 load_register (&icnt
, AT
, &imm_expr
);
3375 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, AT
, sreg
);
3378 case M_SLE
: /* sreg <= treg <==> treg >= sreg <==> not (treg < sreg) */
3384 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, treg
, sreg
);
3385 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
3386 (int) BFD_RELOC_LO16
);
3389 case M_SLE_I
: /* sreg <= I <==> I >= sreg <==> not (I < sreg) */
3395 load_register (&icnt
, AT
, &imm_expr
);
3396 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, AT
, sreg
);
3397 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
3398 (int) BFD_RELOC_LO16
);
3402 if (imm_expr
.X_add_number
>= -0x8000 && imm_expr
.X_add_number
< 0x8000)
3404 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "slti", "t,r,j",
3405 dreg
, sreg
, (int) BFD_RELOC_LO16
);
3408 load_register (&icnt
, AT
, &imm_expr
);
3409 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", dreg
, sreg
, AT
);
3413 if (imm_expr
.X_add_number
>= -0x8000 && imm_expr
.X_add_number
< 0x8000)
3415 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "sltiu", "t,r,j",
3416 dreg
, sreg
, (int) BFD_RELOC_LO16
);
3419 load_register (&icnt
, AT
, &imm_expr
);
3420 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, sreg
,
3426 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0,
3429 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0,
3433 macro_build ((char *) NULL
, &icnt
, NULL
, "xor", "d,v,t", dreg
,
3435 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0,
3441 if (imm_expr
.X_add_number
== 0)
3443 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0,
3449 as_warn ("Instruction %s: result is always true",
3451 macro_build ((char *) NULL
, &icnt
, &expr1
,
3452 mips_isa
< 3 ? "addiu" : "daddiu",
3453 "t,r,j", dreg
, 0, (int) BFD_RELOC_LO16
);
3456 if (imm_expr
.X_add_number
>= 0 && imm_expr
.X_add_number
< 0x10000)
3458 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "xori", "t,r,i",
3459 dreg
, sreg
, (int) BFD_RELOC_LO16
);
3462 else if (imm_expr
.X_add_number
> -0x8000 && imm_expr
.X_add_number
< 0)
3464 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
3465 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
3466 mips_isa
< 3 ? "addiu" : "daddiu",
3467 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
3472 load_register (&icnt
, AT
, &imm_expr
);
3473 macro_build ((char *) NULL
, &icnt
, NULL
, "xor", "d,v,t", dreg
,
3477 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0, dreg
);
3485 if (imm_expr
.X_add_number
> -0x8000 && imm_expr
.X_add_number
<= 0x8000)
3487 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
3488 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
3489 dbl
? "daddi" : "addi",
3490 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
3493 load_register (&icnt
, AT
, &imm_expr
);
3494 macro_build ((char *) NULL
, &icnt
, NULL
,
3495 dbl
? "dsub" : "sub",
3496 "d,v,t", dreg
, sreg
, AT
);
3502 if (imm_expr
.X_add_number
> -0x8000 && imm_expr
.X_add_number
<= 0x8000)
3504 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
3505 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
3506 dbl
? "daddiu" : "addiu",
3507 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
3510 load_register (&icnt
, AT
, &imm_expr
);
3511 macro_build ((char *) NULL
, &icnt
, NULL
,
3512 dbl
? "dsubu" : "subu",
3513 "d,v,t", dreg
, sreg
, AT
);
3534 load_register (&icnt
, AT
, &imm_expr
);
3535 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "s,t", sreg
, AT
);
3540 assert (mips_isa
< 2);
3541 sreg
= (ip
->insn_opcode
>> 11) & 0x1f; /* floating reg */
3542 dreg
= (ip
->insn_opcode
>> 06) & 0x1f; /* floating reg */
3545 * Is the double cfc1 instruction a bug in the mips assembler;
3546 * or is there a reason for it?
3548 mips_emit_delays ();
3550 mips_any_noreorder
= 1;
3551 macro_build ((char *) NULL
, &icnt
, NULL
, "cfc1", "t,G", treg
, 31);
3552 macro_build ((char *) NULL
, &icnt
, NULL
, "cfc1", "t,G", treg
, 31);
3553 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "");
3554 expr1
.X_add_number
= 3;
3555 macro_build ((char *) NULL
, &icnt
, &expr1
, "ori", "t,r,i", AT
, treg
,
3556 (int) BFD_RELOC_LO16
);
3557 expr1
.X_add_number
= 2;
3558 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", AT
, AT
,
3559 (int) BFD_RELOC_LO16
);
3560 macro_build ((char *) NULL
, &icnt
, NULL
, "ctc1", "t,G", AT
, 31);
3561 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "");
3562 macro_build ((char *) NULL
, &icnt
, NULL
,
3563 mask
== M_TRUNCWD
? "cvt.w.d" : "cvt.w.s", "D,S", dreg
, sreg
);
3564 macro_build ((char *) NULL
, &icnt
, NULL
, "ctc1", "t,G", treg
, 31);
3565 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "");
3575 /* avoid load delay */
3576 offset_expr
.X_add_number
+= 1;
3577 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
3578 (int) BFD_RELOC_LO16
, breg
);
3579 offset_expr
.X_add_number
-= 1;
3580 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lbu", "t,o(b)", AT
,
3581 (int) BFD_RELOC_LO16
, breg
);
3582 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", treg
, treg
, 8);
3583 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", treg
, treg
, AT
);
3587 /* does this work on a big endian machine? */
3588 offset_expr
.X_add_number
+= 3;
3589 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lwl", "t,o(b)", treg
,
3590 (int) BFD_RELOC_LO16
, breg
);
3591 offset_expr
.X_add_number
-= 3;
3592 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lwr", "t,o(b)", treg
,
3593 (int) BFD_RELOC_LO16
, breg
);
3599 load_address (&icnt
, AT
, &offset_expr
);
3600 if (mask
== M_ULW_A
)
3602 expr1
.X_add_number
= 3;
3603 macro_build ((char *) NULL
, &icnt
, &expr1
, "lwl", "t,o(b)", treg
,
3604 (int) BFD_RELOC_LO16
, AT
);
3605 expr1
.X_add_number
= 0;
3606 macro_build ((char *) NULL
, &icnt
, &expr1
, "lwr", "t,o(b)", treg
,
3607 (int) BFD_RELOC_LO16
, AT
);
3611 macro_build ((char *) NULL
, &icnt
, &expr1
,
3612 mask
== M_ULH_A
? "lb" : "lbu", "t,o(b)", treg
,
3613 (int) BFD_RELOC_LO16
, AT
);
3614 expr1
.X_add_number
= 0;
3615 macro_build ((char *) NULL
, &icnt
, &expr1
, "lbu", "t,o(b)", AT
,
3616 (int) BFD_RELOC_LO16
, AT
);
3617 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", treg
,
3619 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", treg
,
3625 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "sb", "t,o(b)", treg
,
3626 (int) BFD_RELOC_LO16
, breg
);
3627 macro_build ((char *) NULL
, &icnt
, NULL
, "srl", "d,w,<", AT
, treg
, 8);
3628 offset_expr
.X_add_number
+= 1;
3629 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "sb", "t,o(b)", AT
,
3630 (int) BFD_RELOC_LO16
, breg
);
3634 offset_expr
.X_add_number
+= 3;
3635 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "swl", "t,o(b)", treg
,
3636 (int) BFD_RELOC_LO16
, breg
);
3637 offset_expr
.X_add_number
-= 3;
3638 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "swr", "t,o(b)", treg
,
3639 (int) BFD_RELOC_LO16
, breg
);
3644 load_address (&icnt
, AT
, &offset_expr
);
3645 if (mask
== M_USW_A
)
3647 expr1
.X_add_number
= 3;
3648 macro_build ((char *) NULL
, &icnt
, &expr1
, "swl", "t,o(b)", treg
,
3649 (int) BFD_RELOC_LO16
, AT
);
3650 expr1
.X_add_number
= 0;
3651 macro_build ((char *) NULL
, &icnt
, &expr1
, "swr", "t,o(b)", treg
,
3652 (int) BFD_RELOC_LO16
, AT
);
3656 expr1
.X_add_number
= 0;
3657 macro_build ((char *) NULL
, &icnt
, &expr1
, "sb", "t,o(b)", treg
,
3658 (int) BFD_RELOC_LO16
, AT
);
3659 macro_build ((char *) NULL
, &icnt
, NULL
, "srl", "d,w,<", treg
,
3661 expr1
.X_add_number
= 1;
3662 macro_build ((char *) NULL
, &icnt
, &expr1
, "sb", "t,o(b)", treg
,
3663 (int) BFD_RELOC_LO16
, AT
);
3664 expr1
.X_add_number
= 0;
3665 macro_build ((char *) NULL
, &icnt
, &expr1
, "lbu", "t,o(b)", AT
,
3666 (int) BFD_RELOC_LO16
, AT
);
3667 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", treg
,
3669 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", treg
,
3675 as_bad ("Macro %s not implemented yet", ip
->insn_mo
->name
);
3679 as_warn ("Macro used $at after \".set noat\"");
3684 This routine assembles an instruction into its binary format. As a side
3685 effect it sets one of the global variables imm_reloc or offset_reloc to the
3686 type of relocation to do if one of the operands is an address expression.
3691 struct mips_cl_insn
*ip
;
3696 struct mips_opcode
*insn
;
3699 unsigned int lastregno
= 0;
3704 for (s
= str
; islower (*s
) || (*s
>= '0' && *s
<= '3') || *s
== '.'; ++s
)
3716 as_warn ("Unknown opcode: `%s'", str
);
3719 if ((insn
= (struct mips_opcode
*) hash_find (op_hash
, str
)) == NULL
)
3721 as_warn ("`%s' not in hash table.", str
);
3722 insn_error
= "ERROR: Unrecognized opcode";
3730 assert (strcmp (insn
->name
, str
) == 0);
3732 if (insn
->pinfo
== INSN_MACRO
)
3733 insn_isa
= insn
->match
;
3734 else if (insn
->pinfo
& INSN_ISA2
)
3736 else if (insn
->pinfo
& INSN_ISA3
)
3741 if (insn_isa
> mips_isa
)
3743 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
]
3744 && strcmp (insn
->name
, insn
[1].name
) == 0)
3749 insn_error
= "ERROR: instruction not supported on this processor";
3754 ip
->insn_opcode
= insn
->match
;
3755 for (args
= insn
->args
;; ++args
)
3761 case '\0': /* end of args */
3774 ip
->insn_opcode
|= lastregno
<< 21;
3779 ip
->insn_opcode
|= lastregno
<< 16;
3783 ip
->insn_opcode
|= lastregno
<< 11;
3789 /* handle optional base register.
3790 Either the base register is omitted or
3791 we must have a left paren. */
3792 /* this is dependent on the next operand specifier
3793 is a 'b' for base register */
3794 assert (args
[1] == 'b');
3798 case ')': /* these must match exactly */
3803 case '<': /* must be at least one digit */
3805 * According to the manual, if the shift amount is greater
3806 * than 31 or less than 0 the the shift amount should be
3807 * mod 32. In reality the mips assembler issues an error.
3808 * We issue a warning and mask out all but the low 5 bits.
3810 my_getExpression (&imm_expr
, s
);
3811 check_absolute_expr (ip
, &imm_expr
);
3812 if ((unsigned long) imm_expr
.X_add_number
> 31)
3814 as_warn ("Improper shift amount (%ld)",
3815 (long) imm_expr
.X_add_number
);
3816 imm_expr
.X_add_number
= imm_expr
.X_add_number
& 0x1f;
3818 ip
->insn_opcode
|= imm_expr
.X_add_number
<< 6;
3819 imm_expr
.X_op
= O_absent
;
3823 case '>': /* shift amount minus 32 */
3824 my_getExpression (&imm_expr
, s
);
3825 check_absolute_expr (ip
, &imm_expr
);
3826 if ((unsigned long) imm_expr
.X_add_number
< 32
3827 || (unsigned long) imm_expr
.X_add_number
> 63)
3829 ip
->insn_opcode
|= (imm_expr
.X_add_number
- 32) << 6;
3830 imm_expr
.X_op
= O_absent
;
3834 case 'k': /* cache code */
3835 my_getExpression (&imm_expr
, s
);
3836 check_absolute_expr (ip
, &imm_expr
);
3837 if ((unsigned long) imm_expr
.X_add_number
> 31)
3839 as_warn ("Invalid cahce opcode (%lu)",
3840 (unsigned long) imm_expr
.X_add_number
);
3841 imm_expr
.X_add_number
&= 0x1f;
3843 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_CACHE
;
3844 imm_expr
.X_op
= O_absent
;
3848 case 'c': /* break code */
3849 my_getExpression (&imm_expr
, s
);
3850 check_absolute_expr (ip
, &imm_expr
);
3851 if ((unsigned) imm_expr
.X_add_number
> 1023)
3852 as_warn ("Illegal break code (%ld)",
3853 (long) imm_expr
.X_add_number
);
3854 ip
->insn_opcode
|= imm_expr
.X_add_number
<< 16;
3855 imm_expr
.X_op
= O_absent
;
3859 case 'B': /* syscall code */
3860 my_getExpression (&imm_expr
, s
);
3861 check_absolute_expr (ip
, &imm_expr
);
3862 if ((unsigned) imm_expr
.X_add_number
> 0xfffff)
3863 as_warn ("Illegal syscall code (%ld)",
3864 (long) imm_expr
.X_add_number
);
3865 ip
->insn_opcode
|= imm_expr
.X_add_number
<< 6;
3866 imm_expr
.X_op
= O_absent
;
3870 case 'C': /* Coprocessor code */
3871 my_getExpression (&imm_expr
, s
);
3872 check_absolute_expr (ip
, &imm_expr
);
3873 if ((unsigned long) imm_expr
.X_add_number
>= (1<<25))
3875 as_warn ("Coproccesor code > 25 bits (%ld)",
3876 (long) imm_expr
.X_add_number
);
3877 imm_expr
.X_add_number
&= ((1<<25) - 1);
3879 ip
->insn_opcode
|= imm_expr
.X_add_number
;
3880 imm_expr
.X_op
= O_absent
;
3884 case 'b': /* base register */
3885 case 'd': /* destination register */
3886 case 's': /* source register */
3887 case 't': /* target register */
3888 case 'r': /* both target and source */
3889 case 'v': /* both dest and source */
3890 case 'w': /* both dest and target */
3891 case 'E': /* coprocessor target register */
3892 case 'G': /* coprocessor destination register */
3893 case 'x': /* ignore register name */
3894 case 'z': /* must be zero register */
3908 while (isdigit (*s
));
3910 as_bad ("Invalid register number (%d)", regno
);
3912 else if (*args
== 'E' || *args
== 'G')
3916 if (s
[1] == 'f' && s
[2] == 'p')
3921 else if (s
[1] == 's' && s
[2] == 'p')
3926 else if (s
[1] == 'g' && s
[2] == 'p')
3931 else if (s
[1] == 'a' && s
[2] == 't')
3939 if (regno
== AT
&& ! mips_noat
)
3940 as_warn ("Used $at without \".set noat\"");
3946 if (c
== 'r' || c
== 'v' || c
== 'w')
3953 /* 'z' only matches $0. */
3954 if (c
== 'z' && regno
!= 0)
3962 ip
->insn_opcode
|= regno
<< 21;
3966 ip
->insn_opcode
|= regno
<< 11;
3971 ip
->insn_opcode
|= regno
<< 16;
3974 /* This case exists because on the r3000 trunc
3975 expands into a macro which requires a gp
3976 register. On the r6000 or r4000 it is
3977 assembled into a single instruction which
3978 ignores the register. Thus the insn version
3979 is MIPS_ISA2 and uses 'x', and the macro
3980 version is MIPS_ISA1 and uses 't'. */
3983 /* This case is for the div instruction, which
3984 acts differently if the destination argument
3985 is $0. This only matches $0, and is checked
3986 outside the switch. */
3997 ip
->insn_opcode
|= lastregno
<< 21;
4000 ip
->insn_opcode
|= lastregno
<< 16;
4005 case 'D': /* floating point destination register */
4006 case 'S': /* floating point source register */
4007 case 'T': /* floating point target register */
4011 if (s
[0] == '$' && s
[1] == 'f' && isdigit (s
[2]))
4021 while (isdigit (*s
));
4024 as_bad ("Invalid float register number (%d)", regno
);
4026 if ((regno
& 1) != 0
4028 && ! (strcmp (str
, "mtc1") == 0 ||
4029 strcmp (str
, "mfc1") == 0 ||
4030 strcmp (str
, "lwc1") == 0 ||
4031 strcmp (str
, "swc1") == 0))
4032 as_warn ("Float register should be even, was %d",
4040 if (c
== 'V' || c
== 'W')
4050 ip
->insn_opcode
|= regno
<< 6;
4054 ip
->insn_opcode
|= regno
<< 11;
4058 ip
->insn_opcode
|= regno
<< 16;
4066 ip
->insn_opcode
|= lastregno
<< 11;
4069 ip
->insn_opcode
|= lastregno
<< 16;
4075 my_getExpression (&imm_expr
, s
);
4076 check_absolute_expr (ip
, &imm_expr
);
4081 my_getExpression (&offset_expr
, s
);
4082 imm_reloc
= BFD_RELOC_32
;
4094 unsigned char temp
[8];
4096 unsigned int length
;
4101 /* These only appear as the last operand in an
4102 instruction, and every instruction that accepts
4103 them in any variant accepts them in all variants.
4104 This means we don't have to worry about backing out
4105 any changes if the instruction does not match.
4107 The difference between them is the size of the
4108 floating point constant and where it goes. For 'F'
4109 and 'L' the constant is 64 bits; for 'f' and 'l' it
4110 is 32 bits. Where the constant is placed is based
4111 on how the MIPS assembler does things:
4114 f -- immediate value
4117 When generating PIC code, we do not use the .lit8
4118 or .lit4 sections at all, in order to reserve the
4119 entire global offset table. */
4121 f64
= *args
== 'F' || *args
== 'L';
4123 save_in
= input_line_pointer
;
4124 input_line_pointer
= s
;
4125 err
= md_atof (f64
? 'd' : 'f', (char *) temp
, &len
);
4127 s
= input_line_pointer
;
4128 input_line_pointer
= save_in
;
4129 if (err
!= NULL
&& *err
!= '\0')
4131 as_bad ("Bad floating point constant: %s", err
);
4132 memset (temp
, '\0', sizeof temp
);
4133 length
= f64
? 8 : 4;
4136 assert (length
== (f64
? 8 : 4));
4139 || (mips_pic
!= 0 && *args
== 'l'))
4141 imm_expr
.X_op
= O_constant
;
4142 if (byte_order
== LITTLE_ENDIAN
)
4143 imm_expr
.X_add_number
=
4144 (((((((int) temp
[3] << 8)
4149 imm_expr
.X_add_number
=
4150 (((((((int) temp
[0] << 8)
4157 const char *newname
;
4160 /* Switch to the right section. */
4162 subseg
= now_subseg
;
4165 default: /* unused default case avoids warnings. */
4167 newname
= (mips_pic
== 0 ? ".lit8" : ".rdata");
4173 assert (mips_pic
== 0);
4177 new_seg
= subseg_new (newname
, (subsegT
) 0);
4179 bfd_set_section_alignment (stdoutput
, new_seg
, 4);
4182 as_bad ("Can't use floating point insn in this section");
4184 /* Set the argument to the current address in the
4186 offset_expr
.X_op
= O_symbol
;
4187 offset_expr
.X_add_symbol
=
4188 symbol_new ("L0\001", now_seg
,
4189 (valueT
) frag_now_fix (), frag_now
);
4190 offset_expr
.X_add_number
= 0;
4192 /* Put the floating point number into the section. */
4193 p
= frag_more ((int) length
);
4194 memcpy (p
, temp
, length
);
4196 /* Switch back to the original section. */
4197 subseg_set (seg
, subseg
);
4202 case 'i': /* 16 bit unsigned immediate */
4203 case 'j': /* 16 bit signed immediate */
4204 imm_reloc
= BFD_RELOC_LO16
;
4205 c
= my_getSmallExpression (&imm_expr
, s
);
4210 if (imm_expr
.X_op
== O_constant
)
4211 imm_expr
.X_add_number
=
4212 (imm_expr
.X_add_number
>> 16) & 0xffff;
4214 imm_reloc
= BFD_RELOC_HI16_S
;
4216 imm_reloc
= BFD_RELOC_HI16
;
4220 check_absolute_expr (ip
, &imm_expr
);
4223 if (imm_expr
.X_add_number
< 0
4224 || imm_expr
.X_add_number
>= 0x10000)
4226 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
4227 !strcmp (insn
->name
, insn
[1].name
))
4229 as_bad ("16 bit expression not in range 0..65535");
4234 if (imm_expr
.X_add_number
< -0x8000 ||
4235 imm_expr
.X_add_number
>= 0x8000)
4237 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
4238 !strcmp (insn
->name
, insn
[1].name
))
4240 as_bad ("16 bit expression not in range -32768..32767");
4246 case 'o': /* 16 bit offset */
4247 c
= my_getSmallExpression (&offset_expr
, s
);
4249 * If this value won't fit into a 16 bit offset, then
4250 * go find a macro that will generate the 32 bit offset
4253 if (offset_expr
.X_op
!= O_constant
4254 || offset_expr
.X_add_number
>= 0x8000
4255 || offset_expr
.X_add_number
< -0x8000)
4258 offset_reloc
= BFD_RELOC_LO16
;
4259 if (c
== 'h' || c
== 'H')
4261 assert (offset_expr
.X_op
== O_constant
);
4262 offset_expr
.X_add_number
=
4263 (offset_expr
.X_add_number
>> 16) & 0xffff;
4268 case 'p': /* pc relative offset */
4269 offset_reloc
= BFD_RELOC_16_PCREL_S2
;
4270 my_getExpression (&offset_expr
, s
);
4274 case 'u': /* upper 16 bits */
4275 c
= my_getSmallExpression (&imm_expr
, s
);
4276 if (imm_expr
.X_op
!= O_constant
4277 || imm_expr
.X_add_number
< 0
4278 || imm_expr
.X_add_number
>= 0x10000)
4279 as_bad ("lui expression not in range 0..65535");
4280 imm_reloc
= BFD_RELOC_LO16
;
4285 if (imm_expr
.X_op
== O_constant
)
4286 imm_expr
.X_add_number
=
4287 (imm_expr
.X_add_number
>> 16) & 0xffff;
4289 imm_reloc
= BFD_RELOC_HI16_S
;
4291 imm_reloc
= BFD_RELOC_HI16
;
4297 case 'a': /* 26 bit address */
4298 my_getExpression (&offset_expr
, s
);
4300 offset_reloc
= BFD_RELOC_MIPS_JMP
;
4304 fprintf (stderr
, "bad char = '%c'\n", *args
);
4309 /* Args don't match. */
4310 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
4311 !strcmp (insn
->name
, insn
[1].name
))
4317 insn_error
= "ERROR: Illegal operands";
4326 my_getSmallExpression (ep
, str
)
4337 ((str
[1] == 'h' && str
[2] == 'i')
4338 || (str
[1] == 'H' && str
[2] == 'I')
4339 || (str
[1] == 'l' && str
[2] == 'o'))
4351 * A small expression may be followed by a base register.
4352 * Scan to the end of this operand, and then back over a possible
4353 * base register. Then scan the small expression up to that
4354 * point. (Based on code in sparc.c...)
4356 for (sp
= str
; *sp
&& *sp
!= ','; sp
++)
4358 if (sp
- 4 >= str
&& sp
[-1] == RP
)
4360 if (isdigit (sp
[-2]))
4362 for (sp
-= 3; sp
>= str
&& isdigit (*sp
); sp
--)
4364 if (*sp
== '$' && sp
> str
&& sp
[-1] == LP
)
4370 else if (sp
- 5 >= str
4373 && ((sp
[-3] == 'f' && sp
[-2] == 'p')
4374 || (sp
[-3] == 's' && sp
[-2] == 'p')
4375 || (sp
[-3] == 'g' && sp
[-2] == 'p')
4376 || (sp
[-3] == 'a' && sp
[-2] == 't')))
4382 /* no expression means zero offset */
4385 /* %xx(reg) is an error */
4386 ep
->X_op
= O_absent
;
4391 ep
->X_op
= O_constant
;
4394 ep
->X_add_symbol
= NULL
;
4395 ep
->X_op_symbol
= NULL
;
4396 ep
->X_add_number
= 0;
4401 my_getExpression (ep
, str
);
4408 my_getExpression (ep
, str
);
4409 return c
; /* => %hi or %lo encountered */
4413 my_getExpression (ep
, str
)
4419 save_in
= input_line_pointer
;
4420 input_line_pointer
= str
;
4422 expr_end
= input_line_pointer
;
4423 input_line_pointer
= save_in
;
4426 /* Turn a string in input_line_pointer into a floating point constant
4427 of type type, and store the appropriate bytes in *litP. The number
4428 of LITTLENUMS emitted is stored in *sizeP . An error message is
4429 returned, or NULL on OK. */
4432 md_atof (type
, litP
, sizeP
)
4438 LITTLENUM_TYPE words
[4];
4454 return "bad call to md_atof";
4457 t
= atof_ieee (input_line_pointer
, type
, words
);
4459 input_line_pointer
= t
;
4463 if (byte_order
== LITTLE_ENDIAN
)
4465 for (i
= prec
- 1; i
>= 0; i
--)
4467 md_number_to_chars (litP
, (valueT
) words
[i
], 2);
4473 for (i
= 0; i
< prec
; i
++)
4475 md_number_to_chars (litP
, (valueT
) words
[i
], 2);
4484 md_number_to_chars (buf
, val
, n
)
4492 number_to_chars_littleendian (buf
, val
, n
);
4496 number_to_chars_bigendian (buf
, val
, n
);
4505 md_parse_option (argP
, cntP
, vecP
)
4510 /* Accept -nocpp but ignore it. */
4511 if (strcmp (*argP
, "nocpp") == 0)
4517 if (strcmp (*argP
, "EL") == 0
4518 || strcmp (*argP
, "EB") == 0)
4520 /* FIXME: This breaks -L -EL. */
4528 if ((*argP
)[1] == '0')
4537 if ((*argP
)[1] == '\0' || (*argP
)[1] == '2')
4542 if (strncmp (*argP
, "mips", 4) == 0)
4544 mips_isa
= atol (*argP
+ 4);
4547 else if (mips_isa
< 1 || mips_isa
> 3)
4549 as_bad ("-mips%d not supported", mips_isa
);
4556 if (strncmp (*argP
, "mcpu=", 5) == 0)
4560 /* Identify the processor type */
4562 if (strcmp (p
, "default") == 0
4563 || strcmp (p
, "DEFAULT") == 0)
4567 if (*p
== 'r' || *p
== 'R')
4574 if (strcmp (p
, "2000") == 0
4575 || strcmp (p
, "2k") == 0
4576 || strcmp (p
, "2K") == 0)
4581 if (strcmp (p
, "3000") == 0
4582 || strcmp (p
, "3k") == 0
4583 || strcmp (p
, "3K") == 0)
4588 if (strcmp (p
, "4000") == 0
4589 || strcmp (p
, "4k") == 0
4590 || strcmp (p
, "4K") == 0)
4595 if (strcmp (p
, "6000") == 0
4596 || strcmp (p
, "6k") == 0
4597 || strcmp (p
, "6K") == 0)
4604 as_bad ("bad value (%s) for -mcpu= switch", *argP
+ 5);
4617 if ((*argP
)[1] != '\0')
4618 g_switch_value
= atoi (*argP
+ 1);
4621 **vecP
= (char *) NULL
;
4624 g_switch_value
= atoi (**vecP
);
4627 as_warn ("Number expected after -G");
4633 return 1; /* pretend you parsed the character */
4637 md_pcrel_from (fixP
)
4640 /* return the address of the delay slot */
4641 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
4644 /* This is called by emit_expr via TC_CONS_FIX_NEW when creating a
4645 reloc for a cons. We could use the definition there, except that
4646 we want to handle 64 bit relocs specially. */
4649 cons_fix_new_mips (frag
, where
, nbytes
, exp
)
4652 unsigned int nbytes
;
4655 /* If we are assembling in 32 bit mode, turn an 8 byte reloc into a
4657 FIXME: There is no way to select anything but 32 bit mode right
4661 if (byte_order
== BIG_ENDIAN
)
4666 if (nbytes
!= 2 && nbytes
!= 4)
4667 as_bad ("Unsupported reloc size %d", nbytes
);
4669 fix_new_exp (frag_now
, where
, (int) nbytes
, exp
, 0,
4670 nbytes
== 2 ? BFD_RELOC_16
: BFD_RELOC_32
);
4674 md_apply_fix (fixP
, valueP
)
4681 assert (fixP
->fx_size
== 4);
4684 fixP
->fx_addnumber
= value
; /* Remember value for tc_gen_reloc */
4686 switch (fixP
->fx_r_type
)
4689 case BFD_RELOC_MIPS_JMP
:
4690 case BFD_RELOC_HI16
:
4691 case BFD_RELOC_HI16_S
:
4692 case BFD_RELOC_LO16
:
4693 case BFD_RELOC_MIPS_GPREL
:
4694 case BFD_RELOC_MIPS_LITERAL
:
4695 case BFD_RELOC_MIPS_CALL16
:
4696 case BFD_RELOC_MIPS_GOT16
:
4697 case BFD_RELOC_MIPS_GPREL32
:
4698 /* Nothing needed to do. The value comes from the reloc entry */
4701 case BFD_RELOC_16_PCREL_S2
:
4703 * We need to save the bits in the instruction since fixup_segment()
4704 * might be deleting the relocation entry (i.e., a branch within
4705 * the current segment).
4708 as_warn ("Branch to odd address (%lx)", value
);
4710 if ((value
& ~0xFFFF) && (value
& ~0xFFFF) != (-1 & ~0xFFFF))
4711 as_bad ("Relocation overflow");
4713 /* update old instruction data */
4714 buf
= (unsigned char *) (fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
);
4718 insn
= (buf
[3] << 24) | (buf
[2] << 16) | (buf
[1] << 8) | buf
[0];
4722 insn
= (buf
[0] << 24) | (buf
[1] << 16) | (buf
[2] << 8) | buf
[3];
4729 insn
|= value
& 0xFFFF;
4730 md_number_to_chars ((char *) buf
, (valueT
) insn
, 4);
4744 const struct mips_opcode
*p
;
4745 int treg
, sreg
, dreg
, shamt
;
4750 for (i
= 0; i
< NUMOPCODES
; ++i
)
4752 p
= &mips_opcodes
[i
];
4753 if (((oc
& p
->mask
) == p
->match
) && (p
->pinfo
!= INSN_MACRO
))
4755 printf ("%08lx %s\t", oc
, p
->name
);
4756 treg
= (oc
>> 16) & 0x1f;
4757 sreg
= (oc
>> 21) & 0x1f;
4758 dreg
= (oc
>> 11) & 0x1f;
4759 shamt
= (oc
>> 6) & 0x1f;
4761 for (args
= p
->args
;; ++args
)
4772 printf ("%c", *args
);
4776 assert (treg
== sreg
);
4777 printf ("$%d,$%d", treg
, sreg
);
4782 printf ("$%d", dreg
);
4787 printf ("$%d", treg
);
4791 printf ("0x%x", treg
);
4796 printf ("$%d", sreg
);
4800 printf ("0x%08lx", oc
& 0x1ffffff);
4812 printf ("$%d", shamt
);
4823 printf ("%08lx UNDEFINED\n", oc
);
4834 name
= input_line_pointer
;
4835 c
= get_symbol_end ();
4836 p
= (symbolS
*) symbol_find_or_make (name
);
4837 *input_line_pointer
= c
;
4841 /* Align the current frag to a given power of two. The MIPS assembler
4842 also automatically adjusts any preceding label. */
4845 mips_align (to
, fill
)
4849 mips_emit_delays ();
4850 frag_align (to
, fill
);
4851 record_alignment (now_seg
, to
);
4852 if (insn_label
!= NULL
)
4854 assert (S_GET_SEGMENT (insn_label
) == now_seg
);
4855 insn_label
->sy_frag
= frag_now
;
4856 S_SET_VALUE (insn_label
, (valueT
) frag_now_fix ());
4861 /* Align to a given power of two. .align 0 turns off the automatic
4862 alignment used by the data creating pseudo-ops. */
4869 register long temp_fill
;
4870 long max_alignment
= 15;
4874 o Note that the assembler pulls down any immediately preceeding label
4875 to the aligned address.
4876 o It's not documented but auto alignment is reinstated by
4877 a .align pseudo instruction.
4878 o Note also that after auto alignment is turned off the mips assembler
4879 issues an error on attempt to assemble an improperly aligned data item.
4884 temp
= get_absolute_expression ();
4885 if (temp
> max_alignment
)
4886 as_bad ("Alignment too large: %d. assumed.", temp
= max_alignment
);
4889 as_warn ("Alignment negative: 0 assumed.");
4892 if (*input_line_pointer
== ',')
4894 input_line_pointer
++;
4895 temp_fill
= get_absolute_expression ();
4902 mips_align (temp
, (int) temp_fill
);
4909 demand_empty_rest_of_line ();
4912 /* Handle .ascii and .asciiz. This just calls stringer and forgets
4913 that there was a previous instruction. */
4916 s_stringer (append_zero
)
4919 mips_emit_delays ();
4921 stringer (append_zero
);
4932 mips_emit_delays ();
4942 subseg_set (bss_section
, (subsegT
) get_absolute_expression ());
4943 demand_empty_rest_of_line ();
4948 subseg_new (".rdata", (subsegT
) get_absolute_expression ());
4949 demand_empty_rest_of_line ();
4951 #else /* ! defined (OBJ_ECOFF) */
4953 seg
= subseg_new (".rodata", (subsegT
) get_absolute_expression ());
4954 bfd_set_section_flags (stdoutput
, seg
,
4960 bfd_set_section_alignment (stdoutput
, seg
, 4);
4961 demand_empty_rest_of_line ();
4963 #else /* ! defined (OBJ_ELF) */
4966 #endif /* ! defined (OBJ_ELF) */
4967 #endif /* ! defined (OBJ_ECOFF) */
4971 seg
= subseg_new (".sdata", (subsegT
) get_absolute_expression ());
4973 bfd_set_section_flags (stdoutput
, seg
,
4974 SEC_ALLOC
| SEC_LOAD
| SEC_RELOC
| SEC_DATA
);
4975 bfd_set_section_alignment (stdoutput
, seg
, 4);
4977 demand_empty_rest_of_line ();
4979 #else /* ! defined (GPOPT) */
4980 as_bad ("Global pointers not supported; recompile -G 0");
4981 demand_empty_rest_of_line ();
4983 #endif /* ! defined (GPOPT) */
4993 mips_emit_delays ();
4994 if (log_size
> 0 && auto_align
)
4995 mips_align (log_size
, 0);
4997 cons (1 << log_size
);
5004 as_fatal ("Encountered `.err', aborting assembly");
5014 symbolP
= get_symbol ();
5015 if (*input_line_pointer
== ',')
5016 input_line_pointer
++;
5017 size
= get_absolute_expression ();
5018 S_SET_VALUE (symbolP
, size
);
5019 S_SET_EXTERNAL (symbolP
);
5021 #ifdef ECOFF_DEBUGGING
5022 /* ECOFF needs to distinguish a .comm symbol from a .extern symbol,
5023 so we use an additional ECOFF specific field. */
5024 symbolP
->ecoff_undefined
= 1;
5032 mips_emit_delays ();
5052 opt
= input_line_pointer
;
5053 c
= get_symbol_end ();
5057 /* FIXME: What does this mean? */
5059 else if (strncmp (opt
, "pic", 3) == 0)
5061 mips_pic
= atoi (opt
+ 3);
5062 /* Supposedly no other values are used. */
5063 assert (mips_pic
== 0 || mips_pic
== 2);
5066 as_warn ("Unrecognized option \"%s\"", opt
);
5068 *input_line_pointer
= c
;
5069 demand_empty_rest_of_line ();
5076 char *name
= input_line_pointer
, ch
;
5078 while (!is_end_of_line
[(unsigned char) *input_line_pointer
])
5079 input_line_pointer
++;
5080 ch
= *input_line_pointer
;
5081 *input_line_pointer
= '\0';
5083 if (strcmp (name
, "reorder") == 0)
5087 prev_insn_unreordered
= 1;
5088 prev_prev_insn_unreordered
= 1;
5092 else if (strcmp (name
, "noreorder") == 0)
5094 mips_emit_delays ();
5096 mips_any_noreorder
= 1;
5098 else if (strcmp (name
, "at") == 0)
5102 else if (strcmp (name
, "noat") == 0)
5106 else if (strcmp (name
, "macro") == 0)
5108 mips_warn_about_macros
= 0;
5110 else if (strcmp (name
, "nomacro") == 0)
5112 if (mips_noreorder
== 0)
5113 as_bad ("`noreorder' must be set before `nomacro'");
5114 mips_warn_about_macros
= 1;
5116 else if (strcmp (name
, "move") == 0 || strcmp (name
, "novolatile") == 0)
5120 else if (strcmp (name
, "nomove") == 0 || strcmp (name
, "volatile") == 0)
5124 else if (strcmp (name
, "bopt") == 0)
5128 else if (strcmp (name
, "nobopt") == 0)
5134 as_warn ("Tried to set unrecognized symbol: %s\n", name
);
5136 *input_line_pointer
= ch
;
5137 demand_empty_rest_of_line ();
5140 /* The same as the usual .space directive, except that we have to
5141 forget about any previous instruction. */
5144 s_mips_space (param
)
5147 mips_emit_delays ();
5152 /* Handle the .abicalls pseudo-op. I believe this is equivalent to
5153 .option pic2. It means to generate SVR4 PIC calls. */
5160 demand_empty_rest_of_line ();
5163 /* Handle the .cpload pseudo-op. This is used when generating SVR4
5164 PIC code. It sets the $gp register for the function based on the
5165 function address, which is in the register named in the argument.
5166 This uses a relocation against _gp_disp, which is handled specially
5167 by the linker. The result is:
5168 lui $gp,%hi(_gp_disp)
5169 addiu $gp,$gp,%lo(_gp_disp)
5170 addu $gp,$gp,.cpload argument
5171 The .cpload argument is normally $25 == $t9. */
5180 /* If we are not generating PIC code, .cpload is ignored. */
5187 /* .cpload should be a in .set noreorder section. */
5188 if (mips_noreorder
== 0)
5189 as_warn (".cpload not in noreorder section");
5192 ex
.X_add_symbol
= symbol_find_or_make ("_gp_disp");
5193 ex
.X_op_symbol
= NULL
;
5194 ex
.X_add_number
= 0;
5196 macro_build_lui ((char *) NULL
, &icnt
, &ex
, GP
);
5197 macro_build ((char *) NULL
, &icnt
, &ex
, "addiu", "t,r,j", GP
, GP
,
5198 (int) BFD_RELOC_LO16
);
5200 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "addu", "d,v,t",
5201 GP
, GP
, tc_get_register (0));
5203 demand_empty_rest_of_line ();
5206 /* Handle the .cprestore pseudo-op. This stores $gp into a given
5207 offset from $sp. The offset is remembered, and after making a PIC
5208 call $gp is restored from that location. */
5211 s_cprestore (ignore
)
5217 /* If we are not generating PIC code, .cprestore is ignored. */
5224 mips_cprestore_offset
= get_absolute_expression ();
5226 ex
.X_op
= O_constant
;
5227 ex
.X_add_symbol
= NULL
;
5228 ex
.X_op_symbol
= NULL
;
5229 ex
.X_add_number
= mips_cprestore_offset
;
5231 macro_build ((char *) NULL
, &icnt
, &ex
,
5232 mips_isa
< 3 ? "sw" : "sd",
5233 "t,o(b)", GP
, (int) BFD_RELOC_LO16
, SP
);
5235 demand_empty_rest_of_line ();
5238 /* Handle the .gpword pseudo-op. This is used when generating PIC
5239 code. It generates a 32 bit GP relative reloc. */
5248 /* When not generating PIC code, this is treated as .word. */
5255 mips_emit_delays ();
5262 if (ex
.X_op
!= O_symbol
|| ex
.X_add_number
!= 0)
5264 as_bad ("Unsupported use of .gpword");
5265 ignore_rest_of_line ();
5269 md_number_to_chars (p
, (valueT
) 0, 4);
5270 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 4, &ex
, 0,
5271 BFD_RELOC_MIPS_GPREL32
);
5273 demand_empty_rest_of_line ();
5276 /* Handle the .cpadd pseudo-op. This is used when dealing with switch
5277 tables in SVR4 PIC code. */
5286 /* This is ignored when not generating SVR4 PIC code. */
5293 /* Add $gp to the register named as an argument. */
5294 reg
= tc_get_register (0);
5295 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5296 mips_isa
< 3 ? "addu" : "daddu",
5297 "d,v,t", reg
, reg
, GP
);
5299 demand_empty_rest_of_line ();
5302 /* Parse a register string into a number. Called from the ECOFF code
5303 to parse .frame. The argument is non-zero if this is the frame
5304 register, so that we can record it in mips_frame_reg. */
5307 tc_get_register (frame
)
5313 if (*input_line_pointer
++ != '$')
5315 as_warn ("expected `$'");
5318 else if (isdigit ((unsigned char) *input_line_pointer
))
5320 reg
= get_absolute_expression ();
5321 if (reg
< 0 || reg
>= 32)
5323 as_warn ("Bad register number");
5329 if (strncmp (input_line_pointer
, "fp", 2) == 0)
5331 else if (strncmp (input_line_pointer
, "sp", 2) == 0)
5333 else if (strncmp (input_line_pointer
, "gp", 2) == 0)
5335 else if (strncmp (input_line_pointer
, "at", 2) == 0)
5339 as_warn ("Unrecognized register name");
5342 input_line_pointer
+= 2;
5345 mips_frame_reg
= reg
!= 0 ? reg
: SP
;
5350 md_section_align (seg
, addr
)
5354 int align
= bfd_get_section_alignment (stdoutput
, seg
);
5356 return ((addr
+ (1 << align
) - 1) & (-1 << align
));
5359 /* Estimate the size of a frag before relaxing. We are not really
5360 relaxing here, and the final size is encoded in the subtype
5365 md_estimate_size_before_relax (fragp
, segtype
)
5374 const char *symname
;
5376 /* Find out whether this symbol can be referenced off the GP
5377 register. It can be if it is smaller than the -G size or if
5378 it is in the .sdata or .sbss section. Certain symbols can
5379 not be referenced off the GP, although it appears as though
5381 symname
= S_GET_NAME (fragp
->fr_symbol
);
5382 if (symname
!= (const char *) NULL
5383 && (strcmp (symname
, "eprol") == 0
5384 || strcmp (symname
, "etext") == 0
5385 || strcmp (symname
, "_gp") == 0
5386 || strcmp (symname
, "edata") == 0
5387 || strcmp (symname
, "_fbss") == 0
5388 || strcmp (symname
, "_fdata") == 0
5389 || strcmp (symname
, "_ftext") == 0
5390 || strcmp (symname
, "end") == 0
5391 || strcmp (symname
, "_gp_disp") == 0))
5393 else if (! S_IS_DEFINED (fragp
->fr_symbol
)
5394 && S_GET_VALUE (fragp
->fr_symbol
) != 0
5395 && S_GET_VALUE (fragp
->fr_symbol
) <= g_switch_value
)
5399 const char *segname
;
5401 segname
= segment_name (S_GET_SEGMENT (fragp
->fr_symbol
));
5402 assert (strcmp (segname
, ".lit8") != 0
5403 && strcmp (segname
, ".lit4") != 0);
5404 change
= (strcmp (segname
, ".sdata") != 0
5405 && strcmp (segname
, ".sbss") != 0);
5407 #else /* ! defined (GPOPT) */
5408 /* We are not optimizing for the GP register. */
5410 #endif /* ! defined (GPOPT) */
5414 asection
*symsec
= fragp
->fr_symbol
->bsym
->section
;
5416 /* This must duplicate the test in adjust_reloc_syms. */
5417 change
= (symsec
!= &bfd_und_section
5418 && symsec
!= &bfd_abs_section
5419 && ! bfd_is_com_section (symsec
));
5424 /* Record the offset to the first reloc in the fr_opcode field.
5425 This lets md_convert_frag and tc_gen_reloc know that the code
5426 must be expanded. */
5427 fragp
->fr_opcode
= (fragp
->fr_literal
5429 - RELAX_OLD (fragp
->fr_subtype
)
5430 + RELAX_RELOC1 (fragp
->fr_subtype
));
5431 /* FIXME: This really needs as_warn_where. */
5432 if (RELAX_WARN (fragp
->fr_subtype
))
5433 as_warn ("AT used after \".set noat\" or macro used after \".set nomacro\"");
5439 return RELAX_NEW (fragp
->fr_subtype
) - RELAX_OLD (fragp
->fr_subtype
);
5442 /* Translate internal representation of relocation info to BFD target
5446 tc_gen_reloc (section
, fixp
)
5450 static arelent
*retval
[4];
5453 reloc
= retval
[0] = (arelent
*) xmalloc (sizeof (arelent
));
5456 reloc
->sym_ptr_ptr
= &fixp
->fx_addsy
->bsym
;
5457 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
5458 if (fixp
->fx_pcrel
== 0)
5459 reloc
->addend
= fixp
->fx_addnumber
;
5464 reloc
->addend
= -reloc
->address
;
5467 /* If this is a variant frag, we may need to adjust the existing
5468 reloc and generate a new one. */
5469 if (fixp
->fx_frag
->fr_opcode
!= NULL
5470 && (fixp
->fx_r_type
== BFD_RELOC_MIPS_GPREL
5471 || fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT16
5472 || fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL16
))
5476 /* If this is not the last reloc in this frag, then we have two
5477 GPREL relocs, both of which are being replaced. Let the
5478 second one handle all of them. */
5479 if (fixp
->fx_next
!= NULL
5480 && fixp
->fx_frag
== fixp
->fx_next
->fx_frag
)
5482 assert (fixp
->fx_r_type
== BFD_RELOC_MIPS_GPREL
5483 && fixp
->fx_next
->fx_r_type
== BFD_RELOC_MIPS_GPREL
);
5488 fixp
->fx_where
= fixp
->fx_frag
->fr_opcode
- fixp
->fx_frag
->fr_literal
;
5489 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
5490 reloc2
= retval
[1] = (arelent
*) xmalloc (sizeof (arelent
));
5492 reloc2
->sym_ptr_ptr
= &fixp
->fx_addsy
->bsym
;
5493 reloc2
->address
= (reloc
->address
5494 + (RELAX_RELOC2 (fixp
->fx_frag
->fr_subtype
)
5495 - RELAX_RELOC1 (fixp
->fx_frag
->fr_subtype
)));
5496 reloc2
->addend
= fixp
->fx_addnumber
;
5497 reloc2
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_LO16
);
5498 assert (reloc2
->howto
!= NULL
);
5500 if (RELAX_RELOC3 (fixp
->fx_frag
->fr_subtype
))
5504 reloc3
= retval
[2] = (arelent
*) xmalloc (sizeof (arelent
));
5507 reloc3
->address
+= 4;
5512 assert (fixp
->fx_r_type
== BFD_RELOC_MIPS_GPREL
);
5513 fixp
->fx_r_type
= BFD_RELOC_HI16_S
;
5517 if (fixp
->fx_r_type
!= BFD_RELOC_MIPS_GOT16
)
5519 assert (fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL16
);
5520 fixp
->fx_r_type
= BFD_RELOC_MIPS_GOT16
;
5525 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, fixp
->fx_r_type
);
5527 if (reloc
->howto
== NULL
)
5529 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
5530 "Can not represent relocation in this object file format");
5537 /* Convert a machine dependent frag. */
5540 md_convert_frag (abfd
, asec
, fragp
)
5548 if (fragp
->fr_opcode
== NULL
)
5551 old
= RELAX_OLD (fragp
->fr_subtype
);
5552 new = RELAX_NEW (fragp
->fr_subtype
);
5553 fixptr
= fragp
->fr_literal
+ fragp
->fr_fix
;
5556 memcpy (fixptr
- old
, fixptr
, new);
5558 fragp
->fr_fix
+= new - old
;
5561 /* This function is called whenever a label is defined. It is used
5562 when handling branch delays; if a branch has a label, we assume we
5566 mips_define_label (sym
)
5574 /* Some special processing for a MIPS ELF file. */
5577 mips_elf_final_processing ()
5581 /* Write out the .reginfo section. */
5582 s
.ri_gprmask
= mips_gprmask
;
5583 s
.ri_cprmask
[0] = mips_cprmask
[0];
5584 s
.ri_cprmask
[1] = mips_cprmask
[1];
5585 s
.ri_cprmask
[2] = mips_cprmask
[2];
5586 s
.ri_cprmask
[3] = mips_cprmask
[3];
5587 /* The gp_value field is set by the MIPS ELF backend. */
5589 bfd_mips_elf32_swap_reginfo_out (stdoutput
, &s
,
5590 ((Elf32_External_RegInfo
*)
5591 mips_regmask_frag
));
5593 /* Set the MIPS ELF flag bits. FIXME: There should probably be some
5594 sort of BFD interface for this. */
5595 if (mips_any_noreorder
)
5596 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_NOREORDER
;
5598 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_PIC
;
5601 #endif /* OBJ_ELF */
5603 #ifndef ECOFF_DEBUGGING
5605 /* These functions should really be defined by the object file format,
5606 since they are related to debugging information. However, this
5607 code has to work for the a.out format, which does not define them,
5608 so we provide simple versions here. These don't actually generate
5609 any debugging information, but they do simple checking and someday
5610 somebody may make them useful. */
5614 struct loc
*loc_next
;
5615 unsigned long loc_fileno
;
5616 unsigned long loc_lineno
;
5617 unsigned long loc_offset
;
5618 unsigned short loc_delta
;
5619 unsigned short loc_count
;
5628 struct proc
*proc_next
;
5629 struct symbol
*proc_isym
;
5630 struct symbol
*proc_end
;
5631 unsigned long proc_reg_mask
;
5632 unsigned long proc_reg_offset
;
5633 unsigned long proc_fpreg_mask
;
5634 unsigned long proc_fpreg_offset
;
5635 unsigned long proc_frameoffset
;
5636 unsigned long proc_framereg
;
5637 unsigned long proc_pcreg
;
5639 struct file
*proc_file
;
5646 struct file
*file_next
;
5647 unsigned long file_fileno
;
5648 struct symbol
*file_symbol
;
5649 struct symbol
*file_end
;
5650 struct proc
*file_proc
;
5655 static struct obstack proc_frags
;
5656 static procS
*proc_lastP
;
5657 static procS
*proc_rootP
;
5658 static int numprocs
;
5663 obstack_begin (&proc_frags
, 0x2000);
5669 /* check for premature end, nesting errors, etc */
5670 if (proc_lastP
&& proc_lastP
->proc_end
== NULL
)
5671 as_warn ("missing `.end' at end of assembly");
5674 extern char hex_value
[];
5682 if (*input_line_pointer
== '-')
5684 ++input_line_pointer
;
5687 if (!isdigit (*input_line_pointer
))
5688 as_bad ("Expected simple number.");
5689 if (input_line_pointer
[0] == '0')
5691 if (input_line_pointer
[1] == 'x')
5693 input_line_pointer
+= 2;
5694 while (isxdigit (*input_line_pointer
))
5697 val
|= hex_value
[(int) *input_line_pointer
++];
5699 return negative
? -val
: val
;
5703 ++input_line_pointer
;
5704 while (isdigit (*input_line_pointer
))
5707 val
|= *input_line_pointer
++ - '0';
5709 return negative
? -val
: val
;
5712 if (!isdigit (*input_line_pointer
))
5714 printf (" *input_line_pointer == '%c' 0x%02x\n",
5715 *input_line_pointer
, *input_line_pointer
);
5716 as_warn ("Invalid number");
5719 while (isdigit (*input_line_pointer
))
5722 val
+= *input_line_pointer
++ - '0';
5724 return negative
? -val
: val
;
5727 /* The .file directive; just like the usual .file directive, but there
5728 is an initial number which is the ECOFF file index. */
5736 line
= get_number ();
5741 /* The .end directive. */
5749 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
5752 demand_empty_rest_of_line ();
5756 if (now_seg
!= text_section
)
5757 as_warn (".end not in text section");
5760 as_warn (".end and no .ent seen yet.");
5766 assert (S_GET_NAME (p
));
5767 if (strcmp (S_GET_NAME (p
), S_GET_NAME (proc_lastP
->proc_isym
)))
5768 as_warn (".end symbol does not match .ent symbol.");
5771 proc_lastP
->proc_end
= (symbolS
*) 1;
5774 /* The .aent and .ent directives. */
5784 symbolP
= get_symbol ();
5785 if (*input_line_pointer
== ',')
5786 input_line_pointer
++;
5788 if (isdigit (*input_line_pointer
) || *input_line_pointer
== '-')
5789 number
= get_number ();
5790 if (now_seg
!= text_section
)
5791 as_warn (".ent or .aent not in text section.");
5793 if (!aent
&& proc_lastP
&& proc_lastP
->proc_end
== NULL
)
5794 as_warn ("missing `.end'");
5798 procP
= (procS
*) obstack_alloc (&proc_frags
, sizeof (*procP
));
5799 procP
->proc_isym
= symbolP
;
5800 procP
->proc_reg_mask
= 0;
5801 procP
->proc_reg_offset
= 0;
5802 procP
->proc_fpreg_mask
= 0;
5803 procP
->proc_fpreg_offset
= 0;
5804 procP
->proc_frameoffset
= 0;
5805 procP
->proc_framereg
= 0;
5806 procP
->proc_pcreg
= 0;
5807 procP
->proc_end
= NULL
;
5808 procP
->proc_next
= NULL
;
5810 proc_lastP
->proc_next
= procP
;
5816 demand_empty_rest_of_line ();
5819 /* The .frame directive. */
5832 frame_reg
= tc_get_register (1);
5833 if (*input_line_pointer
== ',')
5834 input_line_pointer
++;
5835 frame_off
= get_absolute_expression ();
5836 if (*input_line_pointer
== ',')
5837 input_line_pointer
++;
5838 pcreg
= tc_get_register (0);
5841 assert (proc_rootP
);
5842 proc_rootP
->proc_framereg
= frame_reg
;
5843 proc_rootP
->proc_frameoffset
= frame_off
;
5844 proc_rootP
->proc_pcreg
= pcreg
;
5845 /* bob macho .frame */
5847 /* We don't have to write out a frame stab for unoptimized code. */
5848 if (!(frame_reg
== FP
&& frame_off
== 0))
5851 as_warn ("No .ent for .frame to use.");
5852 (void) sprintf (str
, "R%d;%d", frame_reg
, frame_off
);
5853 symP
= symbol_new (str
, N_VFP
, 0, frag_now
);
5854 S_SET_TYPE (symP
, N_RMASK
);
5855 S_SET_OTHER (symP
, 0);
5856 S_SET_DESC (symP
, 0);
5857 symP
->sy_forward
= proc_lastP
->proc_isym
;
5858 /* bob perhaps I should have used pseudo set */
5860 demand_empty_rest_of_line ();
5864 /* The .fmask and .mask directives. */
5871 char str
[100], *strP
;
5877 mask
= get_number ();
5878 if (*input_line_pointer
== ',')
5879 input_line_pointer
++;
5880 off
= get_absolute_expression ();
5882 /* bob only for coff */
5883 assert (proc_rootP
);
5884 if (reg_type
== 'F')
5886 proc_rootP
->proc_fpreg_mask
= mask
;
5887 proc_rootP
->proc_fpreg_offset
= off
;
5891 proc_rootP
->proc_reg_mask
= mask
;
5892 proc_rootP
->proc_reg_offset
= off
;
5895 /* bob macho .mask + .fmask */
5897 /* We don't have to write out a mask stab if no saved regs. */
5901 as_warn ("No .ent for .mask to use.");
5903 for (i
= 0; i
< 32; i
++)
5907 sprintf (strP
, "%c%d,", reg_type
, i
);
5908 strP
+= strlen (strP
);
5912 sprintf (strP
, ";%d,", off
);
5913 symP
= symbol_new (str
, N_RMASK
, 0, frag_now
);
5914 S_SET_TYPE (symP
, N_RMASK
);
5915 S_SET_OTHER (symP
, 0);
5916 S_SET_DESC (symP
, 0);
5917 symP
->sy_forward
= proc_lastP
->proc_isym
;
5918 /* bob perhaps I should have used pseudo set */
5923 /* The .loc directive. */
5934 assert (now_seg
== text_section
);
5936 lineno
= get_number ();
5937 addroff
= obstack_next_free (&frags
) - frag_now
->fr_literal
;
5939 symbolP
= symbol_new ("", N_SLINE
, addroff
, frag_now
);
5940 S_SET_TYPE (symbolP
, N_SLINE
);
5941 S_SET_OTHER (symbolP
, 0);
5942 S_SET_DESC (symbolP
, lineno
);
5943 symbolP
->sy_segment
= now_seg
;
5947 #endif /* ! defined (ECOFF_DEBUGGING) */