1 /* tc-mips.c -- assemble code for a MIPS chip.
2 Copyright (C) 1993, 1995, 1996 Free Software Foundation, Inc.
3 Contributed by the OSF and Ralph Campbell.
4 Written by Keith Knowles and Ralph Campbell, working independently.
5 Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus
8 This file is part of GAS.
10 GAS is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 2, or (at your option)
15 GAS is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with GAS; see the file COPYING. If not, write to the Free
22 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
38 #include "opcode/mips.h"
41 /* Clean up namespace so we can include obj-elf.h too. */
42 static int mips_output_flavor () { return OUTPUT_FLAVOR
; }
43 #undef OBJ_PROCESS_STAB
49 #undef TARGET_SYMBOL_FIELDS
51 #undef obj_frob_file_after_relocs
52 #undef obj_frob_symbol
54 #undef obj_sec_sym_ok_for_reloc
57 /* Fix any of them that we actually care about. */
59 #define OUTPUT_FLAVOR mips_output_flavor()
66 #ifndef ECOFF_DEBUGGING
67 #define NO_ECOFF_DEBUGGING
68 #define ECOFF_DEBUGGING 0
73 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
74 static char *mips_regmask_frag
;
79 #define PIC_CALL_REG 25
87 #define ILLEGAL_REG (32)
89 extern int target_big_endian
;
91 /* 1 is we should use the 64 bit MIPS ELF ABI, 0 if we should use the
92 32 bit ABI. This has no meaning for ECOFF. */
95 /* The default target format to use. */
99 switch (OUTPUT_FLAVOR
)
101 case bfd_target_aout_flavour
:
102 return target_big_endian
? "a.out-mips-big" : "a.out-mips-little";
103 case bfd_target_ecoff_flavour
:
104 return target_big_endian
? "ecoff-bigmips" : "ecoff-littlemips";
105 case bfd_target_elf_flavour
:
106 return (target_big_endian
107 ? (mips_64
? "elf64-bigmips" : "elf32-bigmips")
108 : (mips_64
? "elf64-littlemips" : "elf32-littlemips"));
114 /* The name of the readonly data section. */
115 #define RDATA_SECTION_NAME (OUTPUT_FLAVOR == bfd_target_aout_flavour \
117 : OUTPUT_FLAVOR == bfd_target_ecoff_flavour \
119 : OUTPUT_FLAVOR == bfd_target_elf_flavour \
123 /* These variables are filled in with the masks of registers used.
124 The object format code reads them and puts them in the appropriate
126 unsigned long mips_gprmask
;
127 unsigned long mips_cprmask
[4];
129 /* MIPS ISA (Instruction Set Architecture) level (may be changed
130 temporarily using .set mipsN). */
131 static int mips_isa
= -1;
133 /* MIPS ISA we are using for this output file. */
134 static int file_mips_isa
;
136 /* Whether we are assembling for the mips16 processor. */
137 static int mips16
= -1;
139 /* The CPU type as a number: 2000, 3000, 4000, 4400, etc. */
140 static int mips_cpu
= -1;
142 /* Whether the 4650 instructions (mad/madu) are permitted. */
143 static int mips_4650
= -1;
145 /* Whether the 4010 instructions are permitted. */
146 static int mips_4010
= -1;
148 /* Whether the 4100 MADD16 and DMADD16 are permitted. */
149 static int mips_4100
= -1;
151 /* Whether the processor uses hardware interlocks, and thus does not
152 require nops to be inserted. */
153 static int interlocks
= -1;
155 /* As with "interlocks" this is used by hardware that has FP
156 (co-processor) interlocks. */
157 static int cop_interlocks
= -1;
159 /* MIPS PIC level. */
163 /* Do not generate PIC code. */
166 /* Generate PIC code as in Irix 4. This is not implemented, and I'm
167 not sure what it is supposed to do. */
170 /* Generate PIC code as in the SVR4 MIPS ABI. */
173 /* Generate PIC code without using a global offset table: the data
174 segment has a maximum size of 64K, all data references are off
175 the $gp register, and all text references are PC relative. This
176 is used on some embedded systems. */
180 static enum mips_pic_level mips_pic
;
182 /* 1 if we should generate 32 bit offsets from the GP register in
183 SVR4_PIC mode. Currently has no meaning in other modes. */
184 static int mips_big_got
;
186 /* 1 if trap instructions should used for overflow rather than break
188 static int mips_trap
;
190 /* 1 if we should autoextend mips16 instructions. */
191 static int mips16_autoextend
= 1;
193 static int mips_warn_about_macros
;
194 static int mips_noreorder
;
195 static int mips_any_noreorder
;
196 static int mips_nomove
;
197 static int mips_noat
;
198 static int mips_nobopt
;
200 /* The size of the small data section. */
201 static int g_switch_value
= 8;
202 /* Whether the -G option was used. */
203 static int g_switch_seen
= 0;
208 /* If we can determine in advance that GP optimization won't be
209 possible, we can skip the relaxation stuff that tries to produce
210 GP-relative references. This makes delay slot optimization work
213 This function can only provide a guess, but it seems to work for
214 gcc output. If it guesses wrong, the only loss should be in
215 efficiency; it shouldn't introduce any bugs.
217 I don't know if a fix is needed for the SVR4_PIC mode. I've only
218 fixed it for the non-PIC mode. KR 95/04/07 */
219 static int nopic_need_relax
PARAMS ((symbolS
*));
221 /* handle of the OPCODE hash table */
222 static struct hash_control
*op_hash
= NULL
;
224 /* The opcode hash table we use for the mips16. */
225 static struct hash_control
*mips16_op_hash
= NULL
;
227 /* This array holds the chars that always start a comment. If the
228 pre-processor is disabled, these aren't very useful */
229 const char comment_chars
[] = "#";
231 /* This array holds the chars that only start a comment at the beginning of
232 a line. If the line seems to have the form '# 123 filename'
233 .line and .file directives will appear in the pre-processed output */
234 /* Note that input_file.c hand checks for '#' at the beginning of the
235 first line of the input file. This is because the compiler outputs
236 #NO_APP at the beginning of its output. */
237 /* Also note that C style comments are always supported. */
238 const char line_comment_chars
[] = "#";
240 /* This array holds machine specific line separator characters. */
241 const char line_separator_chars
[] = "";
243 /* Chars that can be used to separate mant from exp in floating point nums */
244 const char EXP_CHARS
[] = "eE";
246 /* Chars that mean this number is a floating point constant */
249 const char FLT_CHARS
[] = "rRsSfFdDxXpP";
251 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
252 changed in read.c . Ideally it shouldn't have to know about it at all,
253 but nothing is ideal around here.
256 static char *insn_error
;
258 static int byte_order
;
260 static int auto_align
= 1;
262 /* Symbol labelling the current insn. */
263 static symbolS
*insn_label
;
265 /* When outputting SVR4 PIC code, the assembler needs to know the
266 offset in the stack frame from which to restore the $gp register.
267 This is set by the .cprestore pseudo-op, and saved in this
269 static offsetT mips_cprestore_offset
= -1;
271 /* This is the register which holds the stack frame, as set by the
272 .frame pseudo-op. This is needed to implement .cprestore. */
273 static int mips_frame_reg
= SP
;
275 /* To output NOP instructions correctly, we need to keep information
276 about the previous two instructions. */
278 /* Whether we are optimizing. The default value of 2 means to remove
279 unneeded NOPs and swap branch instructions when possible. A value
280 of 1 means to not swap branches. A value of 0 means to always
282 static int mips_optimize
= 2;
284 /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is
285 equivalent to seeing no -g option at all. */
286 static int mips_debug
= 0;
288 /* The previous instruction. */
289 static struct mips_cl_insn prev_insn
;
291 /* The instruction before prev_insn. */
292 static struct mips_cl_insn prev_prev_insn
;
294 /* If we don't want information for prev_insn or prev_prev_insn, we
295 point the insn_mo field at this dummy integer. */
296 static const struct mips_opcode dummy_opcode
= { 0 };
298 /* Non-zero if prev_insn is valid. */
299 static int prev_insn_valid
;
301 /* The frag for the previous instruction. */
302 static struct frag
*prev_insn_frag
;
304 /* The offset into prev_insn_frag for the previous instruction. */
305 static long prev_insn_where
;
307 /* The reloc for the previous instruction, if any. */
308 static fixS
*prev_insn_fixp
;
310 /* Non-zero if the previous instruction was in a delay slot. */
311 static int prev_insn_is_delay_slot
;
313 /* Non-zero if the previous instruction was in a .set noreorder. */
314 static int prev_insn_unreordered
;
316 /* Non-zero if the previous instruction uses an extend opcode (if
318 static int prev_insn_extended
;
320 /* Non-zero if the previous previous instruction was in a .set
322 static int prev_prev_insn_unreordered
;
324 /* For ECOFF and ELF, relocations against symbols are done in two
325 parts, with a HI relocation and a LO relocation. Each relocation
326 has only 16 bits of space to store an addend. This means that in
327 order for the linker to handle carries correctly, it must be able
328 to locate both the HI and the LO relocation. This means that the
329 relocations must appear in order in the relocation table.
331 In order to implement this, we keep track of each unmatched HI
332 relocation. We then sort them so that they immediately precede the
333 corresponding LO relocation. */
338 struct mips_hi_fixup
*next
;
341 /* The section this fixup is in. */
345 /* The list of unmatched HI relocs. */
347 static struct mips_hi_fixup
*mips_hi_fixup_list
;
349 /* Map normal MIPS register numbers to mips16 register numbers. */
351 #define X ILLEGAL_REG
352 static const int mips32_to_16_reg_map
[] =
354 X
, X
, 2, 3, 4, 5, 6, 7,
355 X
, X
, X
, X
, X
, X
, X
, X
,
356 0, 1, X
, X
, X
, X
, X
, X
,
357 X
, X
, X
, X
, X
, X
, X
, X
361 /* Map mips16 register numbers to normal MIPS register numbers. */
363 static const int mips16_to_32_reg_map
[] =
365 16, 17, 2, 3, 4, 5, 6, 7
368 /* Since the MIPS does not have multiple forms of PC relative
369 instructions, we do not have to do relaxing as is done on other
370 platforms. However, we do have to handle GP relative addressing
371 correctly, which turns out to be a similar problem.
373 Every macro that refers to a symbol can occur in (at least) two
374 forms, one with GP relative addressing and one without. For
375 example, loading a global variable into a register generally uses
376 a macro instruction like this:
378 If i can be addressed off the GP register (this is true if it is in
379 the .sbss or .sdata section, or if it is known to be smaller than
380 the -G argument) this will generate the following instruction:
382 This instruction will use a GPREL reloc. If i can not be addressed
383 off the GP register, the following instruction sequence will be used:
386 In this case the first instruction will have a HI16 reloc, and the
387 second reloc will have a LO16 reloc. Both relocs will be against
390 The issue here is that we may not know whether i is GP addressable
391 until after we see the instruction that uses it. Therefore, we
392 want to be able to choose the final instruction sequence only at
393 the end of the assembly. This is similar to the way other
394 platforms choose the size of a PC relative instruction only at the
397 When generating position independent code we do not use GP
398 addressing in quite the same way, but the issue still arises as
399 external symbols and local symbols must be handled differently.
401 We handle these issues by actually generating both possible
402 instruction sequences. The longer one is put in a frag_var with
403 type rs_machine_dependent. We encode what to do with the frag in
404 the subtype field. We encode (1) the number of existing bytes to
405 replace, (2) the number of new bytes to use, (3) the offset from
406 the start of the existing bytes to the first reloc we must generate
407 (that is, the offset is applied from the start of the existing
408 bytes after they are replaced by the new bytes, if any), (4) the
409 offset from the start of the existing bytes to the second reloc,
410 (5) whether a third reloc is needed (the third reloc is always four
411 bytes after the second reloc), and (6) whether to warn if this
412 variant is used (this is sometimes needed if .set nomacro or .set
413 noat is in effect). All these numbers are reasonably small.
415 Generating two instruction sequences must be handled carefully to
416 ensure that delay slots are handled correctly. Fortunately, there
417 are a limited number of cases. When the second instruction
418 sequence is generated, append_insn is directed to maintain the
419 existing delay slot information, so it continues to apply to any
420 code after the second instruction sequence. This means that the
421 second instruction sequence must not impose any requirements not
422 required by the first instruction sequence.
424 These variant frags are then handled in functions called by the
425 machine independent code. md_estimate_size_before_relax returns
426 the final size of the frag. md_convert_frag sets up the final form
427 of the frag. tc_gen_reloc adjust the first reloc and adds a second
429 #define RELAX_ENCODE(old, new, reloc1, reloc2, reloc3, warn) \
433 | (((reloc1) + 64) << 9) \
434 | (((reloc2) + 64) << 2) \
435 | ((reloc3) ? (1 << 1) : 0) \
437 #define RELAX_OLD(i) (((i) >> 23) & 0x7f)
438 #define RELAX_NEW(i) (((i) >> 16) & 0x7f)
439 #define RELAX_RELOC1(i) ((bfd_vma)(((i) >> 9) & 0x7f) - 64)
440 #define RELAX_RELOC2(i) ((bfd_vma)(((i) >> 2) & 0x7f) - 64)
441 #define RELAX_RELOC3(i) (((i) >> 1) & 1)
442 #define RELAX_WARN(i) ((i) & 1)
444 /* For mips16 code, we use an entirely different form of relaxation.
445 mips16 supports two versions of most instructions which take
446 immediate values: a small one which takes some small value, and a
447 larger one which takes a 16 bit value. Since branches also follow
448 this pattern, relaxing these values is required.
450 We can assemble both mips16 and normal MIPS code in a single
451 object. Therefore, we need to support this type of relaxation at
452 the same time that we support the relaxation described above. We
453 use the high bit of the subtype field to distinguish these cases.
455 The information we store for this type of relaxation is simply the
456 argument code found in the opcode file for this relocation. That
457 tells us the size of the value, and how it should be stored. We
458 also store whether the fragment is considered to be extended or
459 not. We also store whether this is known to be a branch to a
460 different section, whether we have tried to relax this frag yet,
461 and whether we have ever extended a PC relative fragment because of
463 #define RELAX_MIPS16_ENCODE(type) \
464 (0x80000000 | ((type) & 0xff))
465 #define RELAX_MIPS16_P(i) (((i) & 0x80000000) != 0)
466 #define RELAX_MIPS16_TYPE(i) ((i) & 0xff)
467 #define RELAX_MIPS16_EXTENDED(i) (((i) & 0x100) != 0)
468 #define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x100)
469 #define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) &~ 0x100)
470 #define RELAX_MIPS16_LONG_BRANCH(i) (((i) & 0x200) != 0)
471 #define RELAX_MIPS16_MARK_LONG_BRANCH(i) ((i) | 0x200)
472 #define RELAX_MIPS16_CLEAR_LONG_BRANCH(i) ((i) &~ 0x200)
474 /* Prototypes for static functions. */
477 #define internalError() \
478 as_fatal ("internal Error, line %d, %s", __LINE__, __FILE__)
480 #define internalError() as_fatal ("MIPS internal Error");
483 enum mips_regclass
{ MIPS_GR_REG
, MIPS_FP_REG
, MIPS16_REG
};
485 static int insn_uses_reg
PARAMS ((struct mips_cl_insn
*ip
,
486 unsigned int reg
, enum mips_regclass
class));
487 static int reg_needs_delay
PARAMS ((int));
488 static void append_insn
PARAMS ((char *place
,
489 struct mips_cl_insn
* ip
,
491 bfd_reloc_code_real_type r
,
493 static void mips_no_prev_insn
PARAMS ((void));
494 static void mips_emit_delays
PARAMS ((void));
496 static void macro_build
PARAMS ((char *place
, int *counter
, expressionS
* ep
,
497 const char *name
, const char *fmt
,
500 static void macro_build ();
502 static void mips16_macro_build
PARAMS ((char *, int *, expressionS
*,
503 const char *, const char *,
505 static void macro_build_lui
PARAMS ((char *place
, int *counter
,
506 expressionS
* ep
, int regnum
));
507 static void set_at
PARAMS ((int *counter
, int reg
, int unsignedp
));
508 static void check_absolute_expr
PARAMS ((struct mips_cl_insn
* ip
,
510 static void load_register
PARAMS ((int *, int, expressionS
*, int));
511 static void load_address
PARAMS ((int *counter
, int reg
, expressionS
*ep
));
512 static void macro
PARAMS ((struct mips_cl_insn
* ip
));
513 static void mips16_macro
PARAMS ((struct mips_cl_insn
* ip
));
514 #ifdef LOSING_COMPILER
515 static void macro2
PARAMS ((struct mips_cl_insn
* ip
));
517 static void mips_ip
PARAMS ((char *str
, struct mips_cl_insn
* ip
));
518 static void mips16_ip
PARAMS ((char *str
, struct mips_cl_insn
* ip
));
519 static void mips16_immed
PARAMS ((int, offsetT
, boolean
, boolean
, boolean
,
520 unsigned long *, boolean
*,
522 static int my_getSmallExpression
PARAMS ((expressionS
* ep
, char *str
));
523 static void my_getExpression
PARAMS ((expressionS
* ep
, char *str
));
524 static symbolS
*get_symbol
PARAMS ((void));
525 static void mips_align
PARAMS ((int to
, int fill
, symbolS
*label
));
526 static void s_align
PARAMS ((int));
527 static void s_change_sec
PARAMS ((int));
528 static void s_cons
PARAMS ((int));
529 static void s_float_cons
PARAMS ((int));
530 static void s_mips_globl
PARAMS ((int));
531 static void s_option
PARAMS ((int));
532 static void s_mipsset
PARAMS ((int));
533 static void s_abicalls
PARAMS ((int));
534 static void s_cpload
PARAMS ((int));
535 static void s_cprestore
PARAMS ((int));
536 static void s_gpword
PARAMS ((int));
537 static void s_cpadd
PARAMS ((int));
538 static void md_obj_begin
PARAMS ((void));
539 static void md_obj_end
PARAMS ((void));
540 static long get_number
PARAMS ((void));
541 static void s_ent
PARAMS ((int));
542 static void s_mipsend
PARAMS ((int));
543 static void s_file
PARAMS ((int));
544 static int mips16_extended_frag
PARAMS ((fragS
*, asection
*, long));
548 The following pseudo-ops from the Kane and Heinrich MIPS book
549 should be defined here, but are currently unsupported: .alias,
550 .galive, .gjaldef, .gjrlive, .livereg, .noalias.
552 The following pseudo-ops from the Kane and Heinrich MIPS book are
553 specific to the type of debugging information being generated, and
554 should be defined by the object format: .aent, .begin, .bend,
555 .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp,
558 The following pseudo-ops from the Kane and Heinrich MIPS book are
559 not MIPS CPU specific, but are also not specific to the object file
560 format. This file is probably the best place to define them, but
561 they are not currently supported: .asm0, .endr, .lab, .repeat,
562 .struct, .weakext. */
564 static const pseudo_typeS mips_pseudo_table
[] =
566 /* MIPS specific pseudo-ops. */
567 {"option", s_option
, 0},
568 {"set", s_mipsset
, 0},
569 {"rdata", s_change_sec
, 'r'},
570 {"sdata", s_change_sec
, 's'},
571 {"livereg", s_ignore
, 0},
572 {"abicalls", s_abicalls
, 0},
573 {"cpload", s_cpload
, 0},
574 {"cprestore", s_cprestore
, 0},
575 {"gpword", s_gpword
, 0},
576 {"cpadd", s_cpadd
, 0},
578 /* Relatively generic pseudo-ops that happen to be used on MIPS
580 {"asciiz", stringer
, 1},
581 {"bss", s_change_sec
, 'b'},
584 {"dword", s_cons
, 3},
586 /* These pseudo-ops are defined in read.c, but must be overridden
587 here for one reason or another. */
588 {"align", s_align
, 0},
590 {"data", s_change_sec
, 'd'},
591 {"double", s_float_cons
, 'd'},
592 {"float", s_float_cons
, 'f'},
593 {"globl", s_mips_globl
, 0},
594 {"global", s_mips_globl
, 0},
595 {"hword", s_cons
, 1},
600 {"short", s_cons
, 1},
601 {"single", s_float_cons
, 'f'},
602 {"text", s_change_sec
, 't'},
607 static const pseudo_typeS mips_nonecoff_pseudo_table
[] = {
608 /* These pseudo-ops should be defined by the object file format.
609 However, a.out doesn't support them, so we have versions here. */
611 {"bgnb", s_ignore
, 0},
612 {"end", s_mipsend
, 0},
613 {"endb", s_ignore
, 0},
616 {"fmask", s_ignore
, 'F'},
617 {"frame", s_ignore
, 0},
618 {"loc", s_ignore
, 0},
619 {"mask", s_ignore
, 'R'},
620 {"verstamp", s_ignore
, 0},
624 extern void pop_insert
PARAMS ((const pseudo_typeS
*));
629 pop_insert (mips_pseudo_table
);
630 if (! ECOFF_DEBUGGING
)
631 pop_insert (mips_nonecoff_pseudo_table
);
634 static char *expr_end
;
636 /* Expressions which appear in instructions. These are set by
639 static expressionS imm_expr
;
640 static expressionS offset_expr
;
642 /* Relocs associated with imm_expr and offset_expr. */
644 static bfd_reloc_code_real_type imm_reloc
;
645 static bfd_reloc_code_real_type offset_reloc
;
647 /* This is set by mips_ip if imm_reloc is an unmatched HI16_S reloc. */
649 static boolean imm_unmatched_hi
;
652 * This function is called once, at assembler startup time. It should
653 * set up all the tables, etc. that the MD part of the assembler will need.
659 register const char *retval
= NULL
;
660 register unsigned int i
= 0;
668 if (strcmp (cpu
+ (sizeof TARGET_CPU
) - 3, "el") == 0)
670 a
= xmalloc (sizeof TARGET_CPU
);
671 strcpy (a
, TARGET_CPU
);
672 a
[(sizeof TARGET_CPU
) - 3] = '\0';
676 if (strcmp (cpu
, "mips") == 0)
682 else if (strcmp (cpu
, "r6000") == 0
683 || strcmp (cpu
, "mips2") == 0)
689 else if (strcmp (cpu
, "mips64") == 0
690 || strcmp (cpu
, "r4000") == 0
691 || strcmp (cpu
, "mips3") == 0)
697 else if (strcmp (cpu
, "r4400") == 0)
703 else if (strcmp (cpu
, "mips64orion") == 0
704 || strcmp (cpu
, "r4600") == 0)
710 else if (strcmp (cpu
, "r4650") == 0)
718 else if (strcmp (cpu
, "mips64vr4300") == 0)
724 else if (strcmp (cpu
, "mips64vr4100") == 0)
732 else if (strcmp (cpu
, "r4010") == 0)
740 else if (strcmp (cpu
, "r5000") == 0
741 || strcmp (cpu
, "mips64vr5000") == 0)
747 else if (strcmp (cpu
, "r8000") == 0
748 || strcmp (cpu
, "mips4") == 0)
754 else if (strcmp (cpu
, "r10000") == 0)
760 else if (strcmp (cpu
, "mips16") == 0)
764 mips_cpu
= 0; /* FIXME */
779 if (strncmp (TARGET_CPU
, "mips16", sizeof "mips16" - 1) == 0)
794 if (mips_4650
|| mips_4010
|| mips_4100
|| mips_cpu
== 4300)
799 if (mips_cpu
== 4300)
804 if (mips_isa
< 2 && mips_trap
)
805 as_bad ("trap exception not supported at ISA 1");
810 ok
= bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, 3000);
813 ok
= bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, 6000);
816 ok
= bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, 4000);
819 ok
= bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, 8000);
823 as_warn ("Could not set architecture and machine");
825 file_mips_isa
= mips_isa
;
827 op_hash
= hash_new ();
829 for (i
= 0; i
< NUMOPCODES
;)
831 const char *name
= mips_opcodes
[i
].name
;
833 retval
= hash_insert (op_hash
, name
, (PTR
) &mips_opcodes
[i
]);
836 fprintf (stderr
, "internal error: can't hash `%s': %s\n",
837 mips_opcodes
[i
].name
, retval
);
838 as_fatal ("Broken assembler. No assembly attempted.");
842 if (mips_opcodes
[i
].pinfo
!= INSN_MACRO
843 && ((mips_opcodes
[i
].match
& mips_opcodes
[i
].mask
)
844 != mips_opcodes
[i
].match
))
846 fprintf (stderr
, "internal error: bad opcode: `%s' \"%s\"\n",
847 mips_opcodes
[i
].name
, mips_opcodes
[i
].args
);
848 as_fatal ("Broken assembler. No assembly attempted.");
852 while ((i
< NUMOPCODES
) && !strcmp (mips_opcodes
[i
].name
, name
));
855 mips16_op_hash
= hash_new ();
858 while (i
< bfd_mips16_num_opcodes
)
860 const char *name
= mips16_opcodes
[i
].name
;
862 retval
= hash_insert (mips16_op_hash
, name
, (PTR
) &mips16_opcodes
[i
]);
864 as_fatal ("internal error: can't hash `%s': %s\n",
865 mips16_opcodes
[i
].name
, retval
);
868 if (mips16_opcodes
[i
].pinfo
!= INSN_MACRO
869 && ((mips16_opcodes
[i
].match
& mips16_opcodes
[i
].mask
)
870 != mips16_opcodes
[i
].match
))
871 as_fatal ("internal error: bad opcode: `%s' \"%s\"\n",
872 mips16_opcodes
[i
].name
, mips16_opcodes
[i
].args
);
875 while (i
< bfd_mips16_num_opcodes
876 && strcmp (mips16_opcodes
[i
].name
, name
) == 0);
879 mips_no_prev_insn ();
887 /* set the default alignment for the text section (2**2) */
888 record_alignment (text_section
, 2);
890 if (USE_GLOBAL_POINTER_OPT
)
891 bfd_set_gp_size (stdoutput
, g_switch_value
);
893 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
895 /* Sections must be aligned to 16 byte boundaries. */
896 (void) bfd_set_section_alignment (stdoutput
, text_section
, 4);
897 (void) bfd_set_section_alignment (stdoutput
, data_section
, 4);
898 (void) bfd_set_section_alignment (stdoutput
, bss_section
, 4);
900 /* Create a .reginfo section for register masks and a .mdebug
901 section for debugging information. */
912 sec
= subseg_new (".reginfo", (subsegT
) 0);
914 /* The ABI says this section should be loaded so that the
915 running program can access it. */
916 (void) bfd_set_section_flags (stdoutput
, sec
,
917 (SEC_ALLOC
| SEC_LOAD
918 | SEC_READONLY
| SEC_DATA
));
919 (void) bfd_set_section_alignment (stdoutput
, sec
, 2);
922 mips_regmask_frag
= frag_more (sizeof (Elf32_External_RegInfo
));
927 /* The 64-bit ABI uses a .MIPS.options section rather than
929 sec
= subseg_new (".MIPS.options", (subsegT
) 0);
930 (void) bfd_set_section_flags (stdoutput
, sec
,
931 (SEC_ALLOC
| SEC_LOAD
932 | SEC_READONLY
| SEC_DATA
));
933 (void) bfd_set_section_alignment (stdoutput
, sec
, 3);
936 /* Set up the option header. */
938 Elf_Internal_Options opthdr
;
941 opthdr
.kind
= ODK_REGINFO
;
942 opthdr
.size
= (sizeof (Elf_External_Options
)
943 + sizeof (Elf64_External_RegInfo
));
946 f
= frag_more (sizeof (Elf_External_Options
));
947 bfd_mips_elf_swap_options_out (stdoutput
, &opthdr
,
948 (Elf_External_Options
*) f
);
950 mips_regmask_frag
= frag_more (sizeof (Elf64_External_RegInfo
));
957 sec
= subseg_new (".mdebug", (subsegT
) 0);
958 (void) bfd_set_section_flags (stdoutput
, sec
,
959 SEC_HAS_CONTENTS
| SEC_READONLY
);
960 (void) bfd_set_section_alignment (stdoutput
, sec
, 2);
963 subseg_set (seg
, subseg
);
967 if (! ECOFF_DEBUGGING
)
974 if (! ECOFF_DEBUGGING
)
982 struct mips_cl_insn insn
;
984 imm_expr
.X_op
= O_absent
;
985 imm_reloc
= BFD_RELOC_UNUSED
;
986 imm_unmatched_hi
= false;
987 offset_expr
.X_op
= O_absent
;
988 offset_reloc
= BFD_RELOC_UNUSED
;
991 mips16_ip (str
, &insn
);
993 mips_ip (str
, &insn
);
997 as_bad ("%s `%s'", insn_error
, str
);
1001 if (insn
.insn_mo
->pinfo
== INSN_MACRO
)
1004 mips16_macro (&insn
);
1010 if (imm_expr
.X_op
!= O_absent
)
1011 append_insn ((char *) NULL
, &insn
, &imm_expr
, imm_reloc
,
1013 else if (offset_expr
.X_op
!= O_absent
)
1014 append_insn ((char *) NULL
, &insn
, &offset_expr
, offset_reloc
, false);
1016 append_insn ((char *) NULL
, &insn
, NULL
, BFD_RELOC_UNUSED
, false);
1020 /* See whether instruction IP reads register REG. CLASS is the type
1024 insn_uses_reg (ip
, reg
, class)
1025 struct mips_cl_insn
*ip
;
1027 enum mips_regclass
class;
1029 if (class == MIPS16_REG
)
1032 reg
= mips16_to_32_reg_map
[reg
];
1033 class = MIPS_GR_REG
;
1036 /* Don't report on general register 0, since it never changes. */
1037 if (class == MIPS_GR_REG
&& reg
== 0)
1040 if (class == MIPS_FP_REG
)
1043 /* If we are called with either $f0 or $f1, we must check $f0.
1044 This is not optimal, because it will introduce an unnecessary
1045 NOP between "lwc1 $f0" and "swc1 $f1". To fix this we would
1046 need to distinguish reading both $f0 and $f1 or just one of
1047 them. Note that we don't have to check the other way,
1048 because there is no instruction that sets both $f0 and $f1
1049 and requires a delay. */
1050 if ((ip
->insn_mo
->pinfo
& INSN_READ_FPR_S
)
1051 && (((ip
->insn_opcode
>> OP_SH_FS
) & OP_MASK_FS
)
1052 == (reg
&~ (unsigned) 1)))
1054 if ((ip
->insn_mo
->pinfo
& INSN_READ_FPR_T
)
1055 && (((ip
->insn_opcode
>> OP_SH_FT
) & OP_MASK_FT
)
1056 == (reg
&~ (unsigned) 1)))
1061 if ((ip
->insn_mo
->pinfo
& INSN_READ_GPR_S
)
1062 && ((ip
->insn_opcode
>> OP_SH_RS
) & OP_MASK_RS
) == reg
)
1064 if ((ip
->insn_mo
->pinfo
& INSN_READ_GPR_T
)
1065 && ((ip
->insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
) == reg
)
1070 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_X
)
1071 && ((ip
->insn_opcode
>> MIPS16OP_SH_RX
) & MIPS16OP_MASK_RX
) == reg
)
1073 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_Y
)
1074 && ((ip
->insn_opcode
>> MIPS16OP_SH_RY
) & MIPS16OP_MASK_RY
) == reg
)
1076 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_Z
)
1077 && ((ip
->insn_opcode
>> MIPS16OP_SH_MOVE32Z
)
1078 & MIPS16OP_MASK_MOVE32Z
) == reg
)
1080 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_T
) && reg
== TREG
)
1082 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_SP
) && reg
== SP
)
1084 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_31
) && reg
== RA
)
1086 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_GPR_X
)
1087 && ((ip
->insn_opcode
>> MIPS16OP_SH_REGR32
)
1088 & MIPS16OP_MASK_REGR32
) == reg
)
1095 /* This function returns true if modifying a register requires a
1099 reg_needs_delay (reg
)
1102 unsigned long prev_pinfo
;
1104 prev_pinfo
= prev_insn
.insn_mo
->pinfo
;
1105 if (! mips_noreorder
1107 && ((prev_pinfo
& INSN_LOAD_COPROC_DELAY
)
1109 && (prev_pinfo
& INSN_LOAD_MEMORY_DELAY
))))
1111 /* A load from a coprocessor or from memory. All load
1112 delays delay the use of general register rt for one
1113 instruction on the r3000. The r6000 and r4000 use
1115 know (prev_pinfo
& INSN_WRITE_GPR_T
);
1116 if (reg
== ((prev_insn
.insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
))
1123 /* Output an instruction. PLACE is where to put the instruction; if
1124 it is NULL, this uses frag_more to get room. IP is the instruction
1125 information. ADDRESS_EXPR is an operand of the instruction to be
1126 used with RELOC_TYPE. */
1129 append_insn (place
, ip
, address_expr
, reloc_type
, unmatched_hi
)
1131 struct mips_cl_insn
*ip
;
1132 expressionS
*address_expr
;
1133 bfd_reloc_code_real_type reloc_type
;
1134 boolean unmatched_hi
;
1136 register unsigned long prev_pinfo
, pinfo
;
1141 prev_pinfo
= prev_insn
.insn_mo
->pinfo
;
1142 pinfo
= ip
->insn_mo
->pinfo
;
1144 if (place
== NULL
&& ! mips_noreorder
)
1146 /* If the previous insn required any delay slots, see if we need
1147 to insert a NOP or two. There are eight kinds of possible
1148 hazards, of which an instruction can have at most one type.
1149 (1) a load from memory delay
1150 (2) a load from a coprocessor delay
1151 (3) an unconditional branch delay
1152 (4) a conditional branch delay
1153 (5) a move to coprocessor register delay
1154 (6) a load coprocessor register from memory delay
1155 (7) a coprocessor condition code delay
1156 (8) a HI/LO special register delay
1158 There are a lot of optimizations we could do that we don't.
1159 In particular, we do not, in general, reorder instructions.
1160 If you use gcc with optimization, it will reorder
1161 instructions and generally do much more optimization then we
1162 do here; repeating all that work in the assembler would only
1163 benefit hand written assembly code, and does not seem worth
1166 /* This is how a NOP is emitted. */
1167 #define emit_nop() \
1169 ? md_number_to_chars (frag_more (2), 0x6500, 2) \
1170 : md_number_to_chars (frag_more (4), 0, 4))
1172 /* The previous insn might require a delay slot, depending upon
1173 the contents of the current insn. */
1176 && (((prev_pinfo
& INSN_LOAD_COPROC_DELAY
)
1177 && ! cop_interlocks
)
1179 && (prev_pinfo
& INSN_LOAD_MEMORY_DELAY
))))
1181 /* A load from a coprocessor or from memory. All load
1182 delays delay the use of general register rt for one
1183 instruction on the r3000. The r6000 and r4000 use
1185 know (prev_pinfo
& INSN_WRITE_GPR_T
);
1186 if (mips_optimize
== 0
1187 || insn_uses_reg (ip
,
1188 ((prev_insn
.insn_opcode
>> OP_SH_RT
)
1195 && (((prev_pinfo
& INSN_COPROC_MOVE_DELAY
)
1196 && ! cop_interlocks
)
1198 && (prev_pinfo
& INSN_COPROC_MEMORY_DELAY
))))
1200 /* A generic coprocessor delay. The previous instruction
1201 modified a coprocessor general or control register. If
1202 it modified a control register, we need to avoid any
1203 coprocessor instruction (this is probably not always
1204 required, but it sometimes is). If it modified a general
1205 register, we avoid using that register.
1207 On the r6000 and r4000 loading a coprocessor register
1208 from memory is interlocked, and does not require a delay.
1210 This case is not handled very well. There is no special
1211 knowledge of CP0 handling, and the coprocessors other
1212 than the floating point unit are not distinguished at
1214 if (prev_pinfo
& INSN_WRITE_FPR_T
)
1216 if (mips_optimize
== 0
1217 || insn_uses_reg (ip
,
1218 ((prev_insn
.insn_opcode
>> OP_SH_FT
)
1223 else if (prev_pinfo
& INSN_WRITE_FPR_S
)
1225 if (mips_optimize
== 0
1226 || insn_uses_reg (ip
,
1227 ((prev_insn
.insn_opcode
>> OP_SH_FS
)
1234 /* We don't know exactly what the previous instruction
1235 does. If the current instruction uses a coprocessor
1236 register, we must insert a NOP. If previous
1237 instruction may set the condition codes, and the
1238 current instruction uses them, we must insert two
1240 if (mips_optimize
== 0
1241 || ((prev_pinfo
& INSN_WRITE_COND_CODE
)
1242 && (pinfo
& INSN_READ_COND_CODE
)))
1244 else if (pinfo
& INSN_COP
)
1250 && (prev_pinfo
& INSN_WRITE_COND_CODE
)
1251 && ! cop_interlocks
)
1253 /* The previous instruction sets the coprocessor condition
1254 codes, but does not require a general coprocessor delay
1255 (this means it is a floating point comparison
1256 instruction). If this instruction uses the condition
1257 codes, we need to insert a single NOP. */
1258 if (mips_optimize
== 0
1259 || (pinfo
& INSN_READ_COND_CODE
))
1262 else if (prev_pinfo
& INSN_READ_LO
)
1264 /* The previous instruction reads the LO register; if the
1265 current instruction writes to the LO register, we must
1266 insert two NOPS. Some newer processors have interlocks. */
1268 && (mips_optimize
== 0
1269 || (pinfo
& INSN_WRITE_LO
)))
1272 else if (prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
1274 /* The previous instruction reads the HI register; if the
1275 current instruction writes to the HI register, we must
1276 insert a NOP. Some newer processors have interlocks. */
1278 && (mips_optimize
== 0
1279 || (pinfo
& INSN_WRITE_HI
)))
1283 /* There are two cases which require two intervening
1284 instructions: 1) setting the condition codes using a move to
1285 coprocessor instruction which requires a general coprocessor
1286 delay and then reading the condition codes 2) reading the HI
1287 or LO register and then writing to it (except on processors
1288 which have interlocks). If we are not already emitting a NOP
1289 instruction, we must check for these cases compared to the
1290 instruction previous to the previous instruction. */
1294 && (prev_prev_insn
.insn_mo
->pinfo
& INSN_COPROC_MOVE_DELAY
)
1295 && (prev_prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
)
1296 && (pinfo
& INSN_READ_COND_CODE
)
1297 && ! cop_interlocks
)
1298 || ((prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
)
1299 && (pinfo
& INSN_WRITE_LO
)
1301 || ((prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
1302 && (pinfo
& INSN_WRITE_HI
)
1306 /* If we are being given a nop instruction, don't bother with
1307 one of the nops we would otherwise output. This will only
1308 happen when a nop instruction is used with mips_optimize set
1310 if (nops
> 0 && ip
->insn_opcode
== (mips16
? 0x6500 : 0))
1313 /* Now emit the right number of NOP instructions. */
1317 unsigned long old_frag_offset
;
1320 old_frag
= frag_now
;
1321 old_frag_offset
= frag_now_fix ();
1323 for (i
= 0; i
< nops
; i
++)
1328 listing_prev_line ();
1329 /* We may be at the start of a variant frag. In case we
1330 are, make sure there is enough space for the frag
1331 after the frags created by listing_prev_line. The
1332 argument to frag_grow here must be at least as large
1333 as the argument to all other calls to frag_grow in
1334 this file. We don't have to worry about being in the
1335 middle of a variant frag, because the variants insert
1336 all needed nop instructions themselves. */
1340 if (insn_label
!= NULL
)
1342 assert (S_GET_SEGMENT (insn_label
) == now_seg
);
1343 insn_label
->sy_frag
= frag_now
;
1344 S_SET_VALUE (insn_label
, (valueT
) frag_now_fix ());
1347 #ifndef NO_ECOFF_DEBUGGING
1348 if (ECOFF_DEBUGGING
)
1349 ecoff_fix_loc (old_frag
, old_frag_offset
);
1354 if (reloc_type
> BFD_RELOC_UNUSED
)
1356 /* We need to set up a variant frag. */
1357 assert (mips16
&& address_expr
!= NULL
);
1358 f
= frag_var (rs_machine_dependent
, 4, 0,
1359 RELAX_MIPS16_ENCODE (reloc_type
- BFD_RELOC_UNUSED
),
1360 make_expr_symbol (address_expr
), (long) 0,
1363 else if (place
!= NULL
)
1365 else if (mips16
&& ! ip
->use_extend
&& reloc_type
!= BFD_RELOC_MIPS16_JMP
)
1370 if (address_expr
!= NULL
&& reloc_type
< BFD_RELOC_UNUSED
)
1372 if (address_expr
->X_op
== O_constant
)
1377 ip
->insn_opcode
|= address_expr
->X_add_number
;
1380 case BFD_RELOC_LO16
:
1381 ip
->insn_opcode
|= address_expr
->X_add_number
& 0xffff;
1384 case BFD_RELOC_MIPS_JMP
:
1385 ip
->insn_opcode
|= (address_expr
->X_add_number
>> 2) & 0x3ffffff;
1388 case BFD_RELOC_MIPS16_JMP
:
1390 (((address_expr
->X_add_number
& 0x7c0000) << 3)
1391 | ((address_expr
->X_add_number
& 0xf800000) >> 7)
1392 | ((address_expr
->X_add_number
& 0x3fffc) >> 2));
1395 case BFD_RELOC_16_PCREL_S2
:
1405 /* Don't generate a reloc if we are writing into a variant
1409 fixp
= fix_new_exp (frag_now
, f
- frag_now
->fr_literal
, 4,
1411 reloc_type
== BFD_RELOC_16_PCREL_S2
,
1415 struct mips_hi_fixup
*hi_fixup
;
1417 assert (reloc_type
== BFD_RELOC_HI16_S
);
1418 hi_fixup
= ((struct mips_hi_fixup
*)
1419 xmalloc (sizeof (struct mips_hi_fixup
)));
1420 hi_fixup
->fixp
= fixp
;
1421 hi_fixup
->seg
= now_seg
;
1422 hi_fixup
->next
= mips_hi_fixup_list
;
1423 mips_hi_fixup_list
= hi_fixup
;
1429 if (! mips16
|| reloc_type
== BFD_RELOC_MIPS16_JMP
)
1430 md_number_to_chars (f
, ip
->insn_opcode
, 4);
1435 md_number_to_chars (f
, 0xf000 | ip
->extend
, 2);
1438 md_number_to_chars (f
, ip
->insn_opcode
, 2);
1441 /* Update the register mask information. */
1444 if (pinfo
& INSN_WRITE_GPR_D
)
1445 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
);
1446 if ((pinfo
& (INSN_WRITE_GPR_T
| INSN_READ_GPR_T
)) != 0)
1447 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
);
1448 if (pinfo
& INSN_READ_GPR_S
)
1449 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> OP_SH_RS
) & OP_MASK_RS
);
1450 if (pinfo
& INSN_WRITE_GPR_31
)
1451 mips_gprmask
|= 1 << 31;
1452 if (pinfo
& INSN_WRITE_FPR_D
)
1453 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FD
) & OP_MASK_FD
);
1454 if ((pinfo
& (INSN_WRITE_FPR_S
| INSN_READ_FPR_S
)) != 0)
1455 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FS
) & OP_MASK_FS
);
1456 if ((pinfo
& (INSN_WRITE_FPR_T
| INSN_READ_FPR_T
)) != 0)
1457 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FT
) & OP_MASK_FT
);
1458 if ((pinfo
& INSN_READ_FPR_R
) != 0)
1459 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FR
) & OP_MASK_FR
);
1460 if (pinfo
& INSN_COP
)
1462 /* We don't keep enough information to sort these cases out. */
1464 /* Never set the bit for $0, which is always zero. */
1465 mips_gprmask
&=~ 1 << 0;
1469 if (pinfo
& (MIPS16_INSN_WRITE_X
| MIPS16_INSN_READ_X
))
1470 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_RX
)
1471 & MIPS16OP_MASK_RX
);
1472 if (pinfo
& (MIPS16_INSN_WRITE_Y
| MIPS16_INSN_READ_Y
))
1473 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_RY
)
1474 & MIPS16OP_MASK_RY
);
1475 if (pinfo
& MIPS16_INSN_WRITE_Z
)
1476 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_RZ
)
1477 & MIPS16OP_MASK_RZ
);
1478 if (pinfo
& (MIPS16_INSN_WRITE_T
| MIPS16_INSN_READ_T
))
1479 mips_gprmask
|= 1 << TREG
;
1480 if (pinfo
& (MIPS16_INSN_WRITE_SP
| MIPS16_INSN_READ_SP
))
1481 mips_gprmask
|= 1 << SP
;
1482 if (pinfo
& (MIPS16_INSN_WRITE_31
| MIPS16_INSN_READ_31
))
1483 mips_gprmask
|= 1 << RA
;
1484 if (pinfo
& MIPS16_INSN_WRITE_GPR_Y
)
1485 mips_gprmask
|= 1 << MIPS16OP_EXTRACT_REG32R (ip
->insn_opcode
);
1486 if (pinfo
& MIPS16_INSN_READ_Z
)
1487 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_MOVE32Z
)
1488 & MIPS16OP_MASK_MOVE32Z
);
1489 if (pinfo
& MIPS16_INSN_READ_GPR_X
)
1490 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_REGR32
)
1491 & MIPS16OP_MASK_REGR32
);
1494 if (place
== NULL
&& ! mips_noreorder
)
1496 /* Filling the branch delay slot is more complex. We try to
1497 switch the branch with the previous instruction, which we can
1498 do if the previous instruction does not set up a condition
1499 that the branch tests and if the branch is not itself the
1500 target of any branch. */
1501 if ((pinfo
& INSN_UNCOND_BRANCH_DELAY
)
1502 || (pinfo
& INSN_COND_BRANCH_DELAY
))
1504 if (mips_optimize
< 2
1505 /* If we have seen .set volatile or .set nomove, don't
1508 /* If we had to emit any NOP instructions, then we
1509 already know we can not swap. */
1511 /* If we don't even know the previous insn, we can not
1513 || ! prev_insn_valid
1514 /* If the previous insn is already in a branch delay
1515 slot, then we can not swap. */
1516 || prev_insn_is_delay_slot
1517 /* If the previous previous insn was in a .set
1518 noreorder, we can't swap. Actually, the MIPS
1519 assembler will swap in this situation. However, gcc
1520 configured -with-gnu-as will generate code like
1526 in which we can not swap the bne and INSN. If gcc is
1527 not configured -with-gnu-as, it does not output the
1528 .set pseudo-ops. We don't have to check
1529 prev_insn_unreordered, because prev_insn_valid will
1530 be 0 in that case. We don't want to use
1531 prev_prev_insn_valid, because we do want to be able
1532 to swap at the start of a function. */
1533 || prev_prev_insn_unreordered
1534 /* If the branch is itself the target of a branch, we
1535 can not swap. We cheat on this; all we check for is
1536 whether there is a label on this instruction. If
1537 there are any branches to anything other than a
1538 label, users must use .set noreorder. */
1539 || insn_label
!= NULL
1540 /* If the previous instruction is in a variant frag, we
1541 can not do the swap. This does not apply to the
1542 mips16, which uses variant frags for different
1545 && prev_insn_frag
->fr_type
== rs_machine_dependent
)
1546 /* If the branch reads the condition codes, we don't
1547 even try to swap, because in the sequence
1552 we can not swap, and I don't feel like handling that
1556 && (pinfo
& INSN_READ_COND_CODE
))
1557 /* We can not swap with an instruction that requires a
1558 delay slot, becase the target of the branch might
1559 interfere with that instruction. */
1563 & (INSN_LOAD_COPROC_DELAY
1564 | INSN_COPROC_MOVE_DELAY
1565 | INSN_WRITE_COND_CODE
)))
1573 & (INSN_LOAD_MEMORY_DELAY
1574 | INSN_COPROC_MEMORY_DELAY
)))
1575 /* We can not swap with a branch instruction. */
1577 & (INSN_UNCOND_BRANCH_DELAY
1578 | INSN_COND_BRANCH_DELAY
1579 | INSN_COND_BRANCH_LIKELY
))
1580 /* We do not swap with a trap instruction, since it
1581 complicates trap handlers to have the trap
1582 instruction be in a delay slot. */
1583 || (prev_pinfo
& INSN_TRAP
)
1584 /* If the branch reads a register that the previous
1585 instruction sets, we can not swap. */
1587 && (prev_pinfo
& INSN_WRITE_GPR_T
)
1588 && insn_uses_reg (ip
,
1589 ((prev_insn
.insn_opcode
>> OP_SH_RT
)
1593 && (prev_pinfo
& INSN_WRITE_GPR_D
)
1594 && insn_uses_reg (ip
,
1595 ((prev_insn
.insn_opcode
>> OP_SH_RD
)
1599 && (((prev_pinfo
& MIPS16_INSN_WRITE_X
)
1600 && insn_uses_reg (ip
,
1601 ((prev_insn
.insn_opcode
1603 & MIPS16OP_MASK_RX
),
1605 || ((prev_pinfo
& MIPS16_INSN_WRITE_Y
)
1606 && insn_uses_reg (ip
,
1607 ((prev_insn
.insn_opcode
1609 & MIPS16OP_MASK_RY
),
1611 || ((prev_pinfo
& MIPS16_INSN_WRITE_Z
)
1612 && insn_uses_reg (ip
,
1613 ((prev_insn
.insn_opcode
1615 & MIPS16OP_MASK_RZ
),
1617 || ((prev_pinfo
& MIPS16_INSN_WRITE_T
)
1618 && insn_uses_reg (ip
, TREG
, MIPS_GR_REG
))
1619 || ((prev_pinfo
& MIPS16_INSN_WRITE_31
)
1620 && insn_uses_reg (ip
, RA
, MIPS_GR_REG
))
1621 || ((prev_pinfo
& MIPS16_INSN_WRITE_GPR_Y
)
1622 && insn_uses_reg (ip
,
1623 MIPS16OP_EXTRACT_REG32R (prev_insn
.
1626 /* If the branch writes a register that the previous
1627 instruction sets, we can not swap (we know that
1628 branches write only to RD or to $31). */
1630 && (prev_pinfo
& INSN_WRITE_GPR_T
)
1631 && (((pinfo
& INSN_WRITE_GPR_D
)
1632 && (((prev_insn
.insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
)
1633 == ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)))
1634 || ((pinfo
& INSN_WRITE_GPR_31
)
1635 && (((prev_insn
.insn_opcode
>> OP_SH_RT
)
1639 && (prev_pinfo
& INSN_WRITE_GPR_D
)
1640 && (((pinfo
& INSN_WRITE_GPR_D
)
1641 && (((prev_insn
.insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)
1642 == ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)))
1643 || ((pinfo
& INSN_WRITE_GPR_31
)
1644 && (((prev_insn
.insn_opcode
>> OP_SH_RD
)
1648 && (pinfo
& MIPS16_INSN_WRITE_31
)
1649 && ((prev_pinfo
& MIPS16_INSN_WRITE_31
)
1650 || ((prev_pinfo
& MIPS16_INSN_WRITE_GPR_Y
)
1651 && (MIPS16OP_EXTRACT_REG32R (prev_insn
.insn_opcode
)
1653 /* If the branch writes a register that the previous
1654 instruction reads, we can not swap (we know that
1655 branches only write to RD or to $31). */
1657 && (pinfo
& INSN_WRITE_GPR_D
)
1658 && insn_uses_reg (&prev_insn
,
1659 ((ip
->insn_opcode
>> OP_SH_RD
)
1663 && (pinfo
& INSN_WRITE_GPR_31
)
1664 && insn_uses_reg (&prev_insn
, 31, MIPS_GR_REG
))
1666 && (pinfo
& MIPS16_INSN_WRITE_31
)
1667 && insn_uses_reg (&prev_insn
, RA
, MIPS_GR_REG
))
1668 /* If we are generating embedded PIC code, the branch
1669 might be expanded into a sequence which uses $at, so
1670 we can't swap with an instruction which reads it. */
1671 || (mips_pic
== EMBEDDED_PIC
1672 && insn_uses_reg (&prev_insn
, AT
, MIPS_GR_REG
))
1673 /* If the previous previous instruction has a load
1674 delay, and sets a register that the branch reads, we
1678 && ((prev_prev_insn
.insn_mo
->pinfo
& INSN_LOAD_COPROC_DELAY
)
1680 && (prev_prev_insn
.insn_mo
->pinfo
1681 & INSN_LOAD_MEMORY_DELAY
)))
1682 && insn_uses_reg (ip
,
1683 ((prev_prev_insn
.insn_opcode
>> OP_SH_RT
)
1686 /* If one instruction sets a condition code and the
1687 other one uses a condition code, we can not swap. */
1688 || ((pinfo
& INSN_READ_COND_CODE
)
1689 && (prev_pinfo
& INSN_WRITE_COND_CODE
))
1690 || ((pinfo
& INSN_WRITE_COND_CODE
)
1691 && (prev_pinfo
& INSN_READ_COND_CODE
))
1692 /* If the previous instruction uses the PC, we can not
1695 && (prev_pinfo
& MIPS16_INSN_READ_PC
))
1696 /* If the previous instruction was extended, we can not
1698 || (mips16
&& prev_insn_extended
)
1699 /* If the previous instruction had a fixup in mips16
1700 mode, we can not swap. This normally means that the
1701 previous instruction was a 4 byte branch anyhow. */
1702 || (mips16
&& prev_insn_fixp
))
1704 /* We could do even better for unconditional branches to
1705 portions of this object file; we could pick up the
1706 instruction at the destination, put it in the delay
1707 slot, and bump the destination address. */
1709 /* Update the previous insn information. */
1710 prev_prev_insn
= *ip
;
1711 prev_insn
.insn_mo
= &dummy_opcode
;
1715 /* It looks like we can actually do the swap. */
1721 prev_f
= prev_insn_frag
->fr_literal
+ prev_insn_where
;
1722 memcpy (temp
, prev_f
, 4);
1723 memcpy (prev_f
, f
, 4);
1724 memcpy (f
, temp
, 4);
1727 prev_insn_fixp
->fx_frag
= frag_now
;
1728 prev_insn_fixp
->fx_where
= f
- frag_now
->fr_literal
;
1732 fixp
->fx_frag
= prev_insn_frag
;
1733 fixp
->fx_where
= prev_insn_where
;
1736 else if (reloc_type
> BFD_RELOC_UNUSED
)
1741 /* We are in mips16 mode, and we have just created a
1742 variant frag. We need to extract the old
1743 instruction from the end of the previous frag,
1744 and add it to a new frag. */
1745 prev_f
= prev_insn_frag
->fr_literal
+ prev_insn_where
;
1746 memcpy (temp
, prev_f
, 2);
1747 prev_insn_frag
->fr_fix
-= 2;
1748 if (prev_insn_frag
->fr_type
== rs_machine_dependent
)
1750 assert (prev_insn_where
== prev_insn_frag
->fr_fix
);
1751 memcpy (prev_f
, prev_f
+ 2, 2);
1753 memcpy (frag_more (2), temp
, 2);
1760 assert (prev_insn_fixp
== NULL
);
1761 prev_f
= prev_insn_frag
->fr_literal
+ prev_insn_where
;
1762 memcpy (temp
, prev_f
, 2);
1763 memcpy (prev_f
, f
, 2);
1764 if (reloc_type
!= BFD_RELOC_MIPS16_JMP
)
1765 memcpy (f
, temp
, 2);
1768 memcpy (f
, f
+ 2, 2);
1769 memcpy (f
+ 2, temp
, 2);
1773 fixp
->fx_frag
= prev_insn_frag
;
1774 fixp
->fx_where
= prev_insn_where
;
1778 /* Update the previous insn information; leave prev_insn
1780 prev_prev_insn
= *ip
;
1782 prev_insn_is_delay_slot
= 1;
1784 /* If that was an unconditional branch, forget the previous
1785 insn information. */
1786 if (pinfo
& INSN_UNCOND_BRANCH_DELAY
)
1788 prev_prev_insn
.insn_mo
= &dummy_opcode
;
1789 prev_insn
.insn_mo
= &dummy_opcode
;
1792 else if (pinfo
& INSN_COND_BRANCH_LIKELY
)
1794 /* We don't yet optimize a branch likely. What we should do
1795 is look at the target, copy the instruction found there
1796 into the delay slot, and increment the branch to jump to
1797 the next instruction. */
1799 /* Update the previous insn information. */
1800 prev_prev_insn
= *ip
;
1801 prev_insn
.insn_mo
= &dummy_opcode
;
1805 /* Update the previous insn information. */
1807 prev_prev_insn
.insn_mo
= &dummy_opcode
;
1809 prev_prev_insn
= prev_insn
;
1812 /* Any time we see a branch, we always fill the delay slot
1813 immediately; since this insn is not a branch, we know it
1814 is not in a delay slot. */
1815 prev_insn_is_delay_slot
= 0;
1818 prev_prev_insn_unreordered
= prev_insn_unreordered
;
1819 prev_insn_unreordered
= 0;
1820 prev_insn_frag
= frag_now
;
1821 prev_insn_where
= f
- frag_now
->fr_literal
;
1822 prev_insn_fixp
= fixp
;
1824 prev_insn_extended
= ip
->use_extend
|| reloc_type
> BFD_RELOC_UNUSED
;
1825 prev_insn_valid
= 1;
1828 /* We just output an insn, so the next one doesn't have a label. */
1832 /* This function forgets that there was any previous instruction or
1836 mips_no_prev_insn ()
1838 prev_insn
.insn_mo
= &dummy_opcode
;
1839 prev_prev_insn
.insn_mo
= &dummy_opcode
;
1840 prev_insn_valid
= 0;
1841 prev_insn_is_delay_slot
= 0;
1842 prev_insn_unreordered
= 0;
1843 prev_insn_extended
= 0;
1844 prev_prev_insn_unreordered
= 0;
1848 /* This function must be called whenever we turn on noreorder or emit
1849 something other than instructions. It inserts any NOPS which might
1850 be needed by the previous instruction, and clears the information
1851 kept for the previous instructions. */
1856 if (! mips_noreorder
)
1863 && (! cop_interlocks
1864 && (prev_insn
.insn_mo
->pinfo
1865 & (INSN_LOAD_COPROC_DELAY
1866 | INSN_COPROC_MOVE_DELAY
1867 | INSN_WRITE_COND_CODE
))))
1869 && (prev_insn
.insn_mo
->pinfo
1874 && (prev_insn
.insn_mo
->pinfo
1875 & (INSN_LOAD_MEMORY_DELAY
1876 | INSN_COPROC_MEMORY_DELAY
))))
1881 && (! cop_interlocks
1882 && prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
))
1884 && ((prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
1885 || (prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
))))
1890 && (! cop_interlocks
1891 && prev_prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
))
1893 && ((prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
1894 || (prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
))))
1899 if (insn_label
!= NULL
)
1901 assert (S_GET_SEGMENT (insn_label
) == now_seg
);
1902 insn_label
->sy_frag
= frag_now
;
1903 S_SET_VALUE (insn_label
, (valueT
) frag_now_fix ());
1908 mips_no_prev_insn ();
1911 /* Build an instruction created by a macro expansion. This is passed
1912 a pointer to the count of instructions created so far, an
1913 expression, the name of the instruction to build, an operand format
1914 string, and corresponding arguments. */
1918 macro_build (char *place
,
1926 macro_build (place
, counter
, ep
, name
, fmt
, va_alist
)
1935 struct mips_cl_insn insn
;
1936 bfd_reloc_code_real_type r
;
1940 va_start (args
, fmt
);
1946 * If the macro is about to expand into a second instruction,
1947 * print a warning if needed. We need to pass ip as a parameter
1948 * to generate a better warning message here...
1950 if (mips_warn_about_macros
&& place
== NULL
&& *counter
== 1)
1951 as_warn ("Macro instruction expanded into multiple instructions");
1954 *counter
+= 1; /* bump instruction counter */
1958 mips16_macro_build (place
, counter
, ep
, name
, fmt
, args
);
1963 r
= BFD_RELOC_UNUSED
;
1964 insn
.insn_mo
= (struct mips_opcode
*) hash_find (op_hash
, name
);
1965 assert (insn
.insn_mo
);
1966 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
1968 while (strcmp (fmt
, insn
.insn_mo
->args
) != 0
1969 || insn
.insn_mo
->pinfo
== INSN_MACRO
1970 || ((insn
.insn_mo
->pinfo
& INSN_ISA
) == INSN_ISA2
1972 || ((insn
.insn_mo
->pinfo
& INSN_ISA
) == INSN_ISA3
1974 || ((insn
.insn_mo
->pinfo
& INSN_ISA
) == INSN_ISA4
1976 || ((insn
.insn_mo
->pinfo
& INSN_ISA
) == INSN_4650
1978 || ((insn
.insn_mo
->pinfo
& INSN_ISA
) == INSN_4010
1980 || ((insn
.insn_mo
->pinfo
& INSN_ISA
) == INSN_4100
1984 assert (insn
.insn_mo
->name
);
1985 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
1987 insn
.insn_opcode
= insn
.insn_mo
->match
;
2003 insn
.insn_opcode
|= va_arg (args
, int) << 16;
2009 insn
.insn_opcode
|= va_arg (args
, int) << 16;
2014 insn
.insn_opcode
|= va_arg (args
, int) << 11;
2019 insn
.insn_opcode
|= va_arg (args
, int) << 11;
2026 insn
.insn_opcode
|= va_arg (args
, int) << 6;
2030 insn
.insn_opcode
|= va_arg (args
, int) << 6;
2034 insn
.insn_opcode
|= va_arg (args
, int) << 6;
2041 insn
.insn_opcode
|= va_arg (args
, int) << 21;
2047 r
= (bfd_reloc_code_real_type
) va_arg (args
, int);
2048 assert (r
== BFD_RELOC_MIPS_GPREL
2049 || r
== BFD_RELOC_MIPS_LITERAL
2050 || r
== BFD_RELOC_LO16
2051 || r
== BFD_RELOC_MIPS_GOT16
2052 || r
== BFD_RELOC_MIPS_CALL16
2053 || r
== BFD_RELOC_MIPS_GOT_LO16
2054 || r
== BFD_RELOC_MIPS_CALL_LO16
2055 || (ep
->X_op
== O_subtract
2056 && now_seg
== text_section
2057 && r
== BFD_RELOC_PCREL_LO16
));
2061 r
= (bfd_reloc_code_real_type
) va_arg (args
, int);
2063 && (ep
->X_op
== O_constant
2064 || (ep
->X_op
== O_symbol
2065 && (r
== BFD_RELOC_HI16_S
2066 || r
== BFD_RELOC_HI16
2067 || r
== BFD_RELOC_MIPS_GOT_HI16
2068 || r
== BFD_RELOC_MIPS_CALL_HI16
))
2069 || (ep
->X_op
== O_subtract
2070 && now_seg
== text_section
2071 && r
== BFD_RELOC_PCREL_HI16_S
)));
2072 if (ep
->X_op
== O_constant
)
2074 insn
.insn_opcode
|= (ep
->X_add_number
>> 16) & 0xffff;
2076 r
= BFD_RELOC_UNUSED
;
2081 assert (ep
!= NULL
);
2083 * This allows macro() to pass an immediate expression for
2084 * creating short branches without creating a symbol.
2085 * Note that the expression still might come from the assembly
2086 * input, in which case the value is not checked for range nor
2087 * is a relocation entry generated (yuck).
2089 if (ep
->X_op
== O_constant
)
2091 insn
.insn_opcode
|= (ep
->X_add_number
>> 2) & 0xffff;
2095 r
= BFD_RELOC_16_PCREL_S2
;
2099 assert (ep
!= NULL
);
2100 r
= BFD_RELOC_MIPS_JMP
;
2109 assert (r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
2111 append_insn (place
, &insn
, ep
, r
, false);
2115 mips16_macro_build (place
, counter
, ep
, name
, fmt
, args
)
2123 struct mips_cl_insn insn
;
2124 bfd_reloc_code_real_type r
;
2126 r
= BFD_RELOC_UNUSED
;
2127 insn
.insn_mo
= (struct mips_opcode
*) hash_find (mips16_op_hash
, name
);
2128 assert (insn
.insn_mo
);
2129 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
2131 while (strcmp (fmt
, insn
.insn_mo
->args
) != 0
2132 || insn
.insn_mo
->pinfo
== INSN_MACRO
)
2135 assert (insn
.insn_mo
->name
);
2136 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
2139 insn
.insn_opcode
= insn
.insn_mo
->match
;
2140 insn
.use_extend
= false;
2159 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_RY
;
2164 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_RX
;
2168 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_RZ
;
2172 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_MOVE32Z
;
2182 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_REGR32
;
2189 regno
= va_arg (args
, int);
2190 regno
= ((regno
& 7) << 2) | ((regno
& 0x18) >> 3);
2191 insn
.insn_opcode
|= regno
<< MIPS16OP_SH_REG32R
;
2212 assert (ep
!= NULL
);
2214 if (ep
->X_op
!= O_constant
)
2215 r
= BFD_RELOC_UNUSED
+ c
;
2218 mips16_immed (c
, ep
->X_add_number
, false, false, false,
2219 &insn
.insn_opcode
, &insn
.use_extend
,
2222 r
= BFD_RELOC_UNUSED
;
2228 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_IMM6
;
2235 assert (r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
2237 append_insn (place
, &insn
, ep
, r
, false);
2241 * Generate a "lui" instruction.
2244 macro_build_lui (place
, counter
, ep
, regnum
)
2250 expressionS high_expr
;
2251 struct mips_cl_insn insn
;
2252 bfd_reloc_code_real_type r
;
2253 CONST
char *name
= "lui";
2254 CONST
char *fmt
= "t,u";
2262 high_expr
.X_op
= O_constant
;
2263 high_expr
.X_add_number
= ep
->X_add_number
;
2266 if (high_expr
.X_op
== O_constant
)
2268 /* we can compute the instruction now without a relocation entry */
2269 if (high_expr
.X_add_number
& 0x8000)
2270 high_expr
.X_add_number
+= 0x10000;
2271 high_expr
.X_add_number
=
2272 ((unsigned long) high_expr
.X_add_number
>> 16) & 0xffff;
2273 r
= BFD_RELOC_UNUSED
;
2277 assert (ep
->X_op
== O_symbol
);
2278 /* _gp_disp is a special case, used from s_cpload. */
2279 assert (mips_pic
== NO_PIC
2280 || strcmp (S_GET_NAME (ep
->X_add_symbol
), "_gp_disp") == 0);
2281 r
= BFD_RELOC_HI16_S
;
2285 * If the macro is about to expand into a second instruction,
2286 * print a warning if needed. We need to pass ip as a parameter
2287 * to generate a better warning message here...
2289 if (mips_warn_about_macros
&& place
== NULL
&& *counter
== 1)
2290 as_warn ("Macro instruction expanded into multiple instructions");
2293 *counter
+= 1; /* bump instruction counter */
2295 insn
.insn_mo
= (struct mips_opcode
*) hash_find (op_hash
, name
);
2296 assert (insn
.insn_mo
);
2297 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
2298 assert (strcmp (fmt
, insn
.insn_mo
->args
) == 0);
2300 insn
.insn_opcode
= insn
.insn_mo
->match
| (regnum
<< OP_SH_RT
);
2301 if (r
== BFD_RELOC_UNUSED
)
2303 insn
.insn_opcode
|= high_expr
.X_add_number
;
2304 append_insn (place
, &insn
, NULL
, r
, false);
2307 append_insn (place
, &insn
, &high_expr
, r
, false);
2311 * Generates code to set the $at register to true (one)
2312 * if reg is less than the immediate expression.
2315 set_at (counter
, reg
, unsignedp
)
2320 if (imm_expr
.X_add_number
>= -0x8000 && imm_expr
.X_add_number
< 0x8000)
2321 macro_build ((char *) NULL
, counter
, &imm_expr
,
2322 unsignedp
? "sltiu" : "slti",
2323 "t,r,j", AT
, reg
, (int) BFD_RELOC_LO16
);
2326 load_register (counter
, AT
, &imm_expr
, 0);
2327 macro_build ((char *) NULL
, counter
, NULL
,
2328 unsignedp
? "sltu" : "slt",
2329 "d,v,t", AT
, reg
, AT
);
2333 /* Warn if an expression is not a constant. */
2336 check_absolute_expr (ip
, ex
)
2337 struct mips_cl_insn
*ip
;
2340 if (ex
->X_op
!= O_constant
)
2341 as_warn ("Instruction %s requires absolute expression", ip
->insn_mo
->name
);
2344 /* Count the leading zeroes by performing a binary chop. This is a
2345 bulky bit of source, but performance is a LOT better for the
2346 majority of values than a simple loop to count the bits:
2347 for (lcnt = 0; (lcnt < 32); lcnt++)
2348 if ((v) & (1 << (31 - lcnt)))
2350 However it is not code size friendly, and the gain will drop a bit
2351 on certain cached systems.
2353 #define COUNT_TOP_ZEROES(v) \
2354 (((v) & ~0xffff) == 0 \
2355 ? ((v) & ~0xff) == 0 \
2356 ? ((v) & ~0xf) == 0 \
2357 ? ((v) & ~0x3) == 0 \
2358 ? ((v) & ~0x1) == 0 \
2363 : ((v) & ~0x7) == 0 \
2366 : ((v) & ~0x3f) == 0 \
2367 ? ((v) & ~0x1f) == 0 \
2370 : ((v) & ~0x7f) == 0 \
2373 : ((v) & ~0xfff) == 0 \
2374 ? ((v) & ~0x3ff) == 0 \
2375 ? ((v) & ~0x1ff) == 0 \
2378 : ((v) & ~0x7ff) == 0 \
2381 : ((v) & ~0x3fff) == 0 \
2382 ? ((v) & ~0x1fff) == 0 \
2385 : ((v) & ~0x7fff) == 0 \
2388 : ((v) & ~0xffffff) == 0 \
2389 ? ((v) & ~0xfffff) == 0 \
2390 ? ((v) & ~0x3ffff) == 0 \
2391 ? ((v) & ~0x1ffff) == 0 \
2394 : ((v) & ~0x7ffff) == 0 \
2397 : ((v) & ~0x3fffff) == 0 \
2398 ? ((v) & ~0x1fffff) == 0 \
2401 : ((v) & ~0x7fffff) == 0 \
2404 : ((v) & ~0xfffffff) == 0 \
2405 ? ((v) & ~0x3ffffff) == 0 \
2406 ? ((v) & ~0x1ffffff) == 0 \
2409 : ((v) & ~0x7ffffff) == 0 \
2412 : ((v) & ~0x3fffffff) == 0 \
2413 ? ((v) & ~0x1fffffff) == 0 \
2416 : ((v) & ~0x7fffffff) == 0 \
2421 * This routine generates the least number of instructions neccessary to load
2422 * an absolute expression value into a register.
2425 load_register (counter
, reg
, ep
, dbl
)
2432 expressionS hi32
, lo32
, tmp
;
2434 if (ep
->X_op
!= O_big
)
2436 assert (ep
->X_op
== O_constant
);
2437 if (ep
->X_add_number
< 0x8000
2438 && (ep
->X_add_number
>= 0
2439 || (ep
->X_add_number
>= -0x8000
2442 || sizeof (ep
->X_add_number
) > 4))))
2444 /* We can handle 16 bit signed values with an addiu to
2445 $zero. No need to ever use daddiu here, since $zero and
2446 the result are always correct in 32 bit mode. */
2447 macro_build ((char *) NULL
, counter
, ep
, "addiu", "t,r,j", reg
, 0,
2448 (int) BFD_RELOC_LO16
);
2451 else if (ep
->X_add_number
>= 0 && ep
->X_add_number
< 0x10000)
2453 /* We can handle 16 bit unsigned values with an ori to
2455 macro_build ((char *) NULL
, counter
, ep
, "ori", "t,r,i", reg
, 0,
2456 (int) BFD_RELOC_LO16
);
2459 else if ((((ep
->X_add_number
&~ (offsetT
) 0x7fffffff) == 0
2460 || ((ep
->X_add_number
&~ (offsetT
) 0x7fffffff)
2461 == ~ (offsetT
) 0x7fffffff))
2464 || sizeof (ep
->X_add_number
) > 4
2465 || (ep
->X_add_number
& 0x80000000) == 0))
2466 || ((mips_isa
< 3 || !dbl
)
2467 && (ep
->X_add_number
&~ (offsetT
) 0xffffffff) == 0))
2469 /* 32 bit values require an lui. */
2470 macro_build ((char *) NULL
, counter
, ep
, "lui", "t,u", reg
,
2471 (int) BFD_RELOC_HI16
);
2472 if ((ep
->X_add_number
& 0xffff) != 0)
2473 macro_build ((char *) NULL
, counter
, ep
, "ori", "t,r,i", reg
, reg
,
2474 (int) BFD_RELOC_LO16
);
2479 /* The value is larger than 32 bits. */
2483 as_bad ("Number larger than 32 bits");
2484 macro_build ((char *) NULL
, counter
, ep
, "addiu", "t,r,j", reg
, 0,
2485 (int) BFD_RELOC_LO16
);
2489 if (ep
->X_op
!= O_big
)
2493 hi32
.X_add_number
>>= shift
;
2494 hi32
.X_add_number
&= 0xffffffff;
2495 if ((hi32
.X_add_number
& 0x80000000) != 0)
2496 hi32
.X_add_number
|= ~ (offsetT
) 0xffffffff;
2498 lo32
.X_add_number
&= 0xffffffff;
2502 assert (ep
->X_add_number
> 2);
2503 if (ep
->X_add_number
== 3)
2504 generic_bignum
[3] = 0;
2505 else if (ep
->X_add_number
> 4)
2506 as_bad ("Number larger than 64 bits");
2507 lo32
.X_op
= O_constant
;
2508 lo32
.X_add_number
= generic_bignum
[0] + (generic_bignum
[1] << 16);
2509 hi32
.X_op
= O_constant
;
2510 hi32
.X_add_number
= generic_bignum
[2] + (generic_bignum
[3] << 16);
2513 if (hi32
.X_add_number
== 0)
2517 if (hi32
.X_add_number
== 0xffffffff)
2519 if ((lo32
.X_add_number
& 0xffff8000) == 0xffff8000)
2521 macro_build ((char *) NULL
, counter
, &lo32
, "addiu", "t,r,j", reg
, 0,
2522 (int) BFD_RELOC_LO16
);
2525 if (lo32
.X_add_number
& 0x80000000)
2527 macro_build ((char *) NULL
, counter
, &lo32
, "lui", "t,u", reg
,
2528 (int) BFD_RELOC_HI16
);
2529 macro_build ((char *) NULL
, counter
, &lo32
, "ori", "t,r,i", reg
, reg
,
2530 (int) BFD_RELOC_LO16
);
2535 /* Check for 16bit shifted constant: */
2537 tmp
.X_add_number
= hi32
.X_add_number
<< shift
| lo32
.X_add_number
;
2538 /* We know that hi32 is non-zero, so start the mask on the first
2539 bit of the hi32 value: */
2543 if ((tmp
.X_add_number
& ~((offsetT
)0xffff << shift
)) == 0)
2545 tmp
.X_op
= O_constant
;
2546 tmp
.X_add_number
>>= shift
;
2547 macro_build ((char *) NULL
, counter
, &tmp
, "ori", "t,r,i", reg
, 0,
2548 (int) BFD_RELOC_LO16
);
2549 macro_build ((char *) NULL
, counter
, NULL
,
2550 (shift
>= 32) ? "dsll32" : "dsll",
2551 "d,w,<", reg
, reg
, (shift
>= 32) ? shift
- 32 : shift
);
2555 } while (shift
<= (64 - 16));
2559 tmp
.X_add_number
= hi32
.X_add_number
<< shift
| lo32
.X_add_number
;
2560 while ((tmp
.X_add_number
& 1) == 0)
2562 tmp
.X_add_number
>>= 1;
2565 if (((tmp
.X_add_number
+ 1) & tmp
.X_add_number
) == 0) /* (power-of-2 - 1) */
2567 shift
= COUNT_TOP_ZEROES((unsigned int)hi32
.X_add_number
);
2570 tmp
.X_op
= O_constant
;
2571 tmp
.X_add_number
= (offsetT
)-1;
2572 macro_build ((char *) NULL
, counter
, &tmp
, "addiu", "t,r,j", reg
, 0,
2573 (int) BFD_RELOC_LO16
); /* set all ones */
2577 macro_build ((char *) NULL
, counter
, NULL
,
2578 (freg
>= 32) ? "dsll32" : "dsll",
2580 (freg
>= 32) ? freg
- 32 : freg
);
2582 macro_build ((char *) NULL
, counter
, NULL
, (shift
>= 32) ? "dsrl32" : "dsrl",
2583 "d,w,<", reg
, reg
, (shift
>= 32) ? shift
- 32 : shift
);
2587 load_register (counter
, reg
, &hi32
, 0);
2590 if ((lo32
.X_add_number
& 0xffff0000) == 0)
2594 macro_build ((char *) NULL
, counter
, NULL
, "dsll32", "d,w,<", reg
,
2603 if ((freg
== 0) && (lo32
.X_add_number
== 0xffffffff))
2605 macro_build ((char *) NULL
, counter
, &lo32
, "lui", "t,u", reg
,
2606 (int) BFD_RELOC_HI16
);
2607 macro_build ((char *) NULL
, counter
, NULL
, "dsrl32", "d,w,<", reg
,
2614 macro_build ((char *) NULL
, counter
, NULL
, "dsll", "d,w,<", reg
,
2619 mid16
.X_add_number
>>= 16;
2620 macro_build ((char *) NULL
, counter
, &mid16
, "ori", "t,r,i", reg
,
2621 freg
, (int) BFD_RELOC_LO16
);
2622 macro_build ((char *) NULL
, counter
, NULL
, "dsll", "d,w,<", reg
,
2626 if ((lo32
.X_add_number
& 0xffff) != 0)
2627 macro_build ((char *) NULL
, counter
, &lo32
, "ori", "t,r,i", reg
, freg
,
2628 (int) BFD_RELOC_LO16
);
2631 /* Load an address into a register. */
2634 load_address (counter
, reg
, ep
)
2641 if (ep
->X_op
!= O_constant
2642 && ep
->X_op
!= O_symbol
)
2644 as_bad ("expression too complex");
2645 ep
->X_op
= O_constant
;
2648 if (ep
->X_op
== O_constant
)
2650 load_register (counter
, reg
, ep
, 0);
2654 if (mips_pic
== NO_PIC
)
2656 /* If this is a reference to a GP relative symbol, we want
2657 addiu $reg,$gp,<sym> (BFD_RELOC_MIPS_GPREL)
2659 lui $reg,<sym> (BFD_RELOC_HI16_S)
2660 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
2661 If we have an addend, we always use the latter form. */
2662 if ((valueT
) ep
->X_add_number
>= MAX_GPREL_OFFSET
2663 || nopic_need_relax (ep
->X_add_symbol
))
2668 macro_build ((char *) NULL
, counter
, ep
,
2669 mips_isa
< 3 ? "addiu" : "daddiu",
2670 "t,r,j", reg
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
2671 p
= frag_var (rs_machine_dependent
, 8, 0,
2672 RELAX_ENCODE (4, 8, 0, 4, 0, mips_warn_about_macros
),
2673 ep
->X_add_symbol
, (long) 0, (char *) NULL
);
2675 macro_build_lui (p
, counter
, ep
, reg
);
2678 macro_build (p
, counter
, ep
,
2679 mips_isa
< 3 ? "addiu" : "daddiu",
2680 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
2682 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
2686 /* If this is a reference to an external symbol, we want
2687 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
2689 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
2691 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
2692 If there is a constant, it must be added in after. */
2693 ex
.X_add_number
= ep
->X_add_number
;
2694 ep
->X_add_number
= 0;
2696 macro_build ((char *) NULL
, counter
, ep
,
2697 mips_isa
< 3 ? "lw" : "ld",
2698 "t,o(b)", reg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
2699 macro_build ((char *) NULL
, counter
, (expressionS
*) NULL
, "nop", "");
2700 p
= frag_var (rs_machine_dependent
, 4, 0,
2701 RELAX_ENCODE (0, 4, -8, 0, 0, mips_warn_about_macros
),
2702 ep
->X_add_symbol
, (long) 0, (char *) NULL
);
2703 macro_build (p
, counter
, ep
,
2704 mips_isa
< 3 ? "addiu" : "daddiu",
2705 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
2706 if (ex
.X_add_number
!= 0)
2708 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
2709 as_bad ("PIC code offset overflow (max 16 signed bits)");
2710 ex
.X_op
= O_constant
;
2711 macro_build ((char *) NULL
, counter
, &ex
,
2712 mips_isa
< 3 ? "addiu" : "daddiu",
2713 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
2716 else if (mips_pic
== SVR4_PIC
)
2721 /* This is the large GOT case. If this is a reference to an
2722 external symbol, we want
2723 lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
2725 lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16)
2726 Otherwise, for a reference to a local symbol, we want
2727 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
2729 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
2730 If there is a constant, it must be added in after. */
2731 ex
.X_add_number
= ep
->X_add_number
;
2732 ep
->X_add_number
= 0;
2733 if (reg_needs_delay (GP
))
2738 macro_build ((char *) NULL
, counter
, ep
, "lui", "t,u", reg
,
2739 (int) BFD_RELOC_MIPS_GOT_HI16
);
2740 macro_build ((char *) NULL
, counter
, (expressionS
*) NULL
,
2741 mips_isa
< 3 ? "addu" : "daddu",
2742 "d,v,t", reg
, reg
, GP
);
2743 macro_build ((char *) NULL
, counter
, ep
,
2744 mips_isa
< 3 ? "lw" : "ld",
2745 "t,o(b)", reg
, (int) BFD_RELOC_MIPS_GOT_LO16
, reg
);
2746 p
= frag_var (rs_machine_dependent
, 12 + off
, 0,
2747 RELAX_ENCODE (12, 12 + off
, off
, 8 + off
, 0,
2748 mips_warn_about_macros
),
2749 ep
->X_add_symbol
, (long) 0, (char *) NULL
);
2752 /* We need a nop before loading from $gp. This special
2753 check is required because the lui which starts the main
2754 instruction stream does not refer to $gp, and so will not
2755 insert the nop which may be required. */
2756 macro_build (p
, counter
, (expressionS
*) NULL
, "nop", "");
2759 macro_build (p
, counter
, ep
,
2760 mips_isa
< 3 ? "lw" : "ld",
2761 "t,o(b)", reg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
2763 macro_build (p
, counter
, (expressionS
*) NULL
, "nop", "");
2765 macro_build (p
, counter
, ep
,
2766 mips_isa
< 3 ? "addiu" : "daddiu",
2767 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
2768 if (ex
.X_add_number
!= 0)
2770 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
2771 as_bad ("PIC code offset overflow (max 16 signed bits)");
2772 ex
.X_op
= O_constant
;
2773 macro_build ((char *) NULL
, counter
, &ex
,
2774 mips_isa
< 3 ? "addiu" : "daddiu",
2775 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
2778 else if (mips_pic
== EMBEDDED_PIC
)
2781 addiu $reg,$gp,<sym> (BFD_RELOC_MIPS_GPREL)
2783 macro_build ((char *) NULL
, counter
, ep
,
2784 mips_isa
< 3 ? "addiu" : "daddiu",
2785 "t,r,j", reg
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
2793 * This routine implements the seemingly endless macro or synthesized
2794 * instructions and addressing modes in the mips assembly language. Many
2795 * of these macros are simple and are similar to each other. These could
2796 * probably be handled by some kind of table or grammer aproach instead of
2797 * this verbose method. Others are not simple macros but are more like
2798 * optimizing code generation.
2799 * One interesting optimization is when several store macros appear
2800 * consecutivly that would load AT with the upper half of the same address.
2801 * The ensuing load upper instructions are ommited. This implies some kind
2802 * of global optimization. We currently only optimize within a single macro.
2803 * For many of the load and store macros if the address is specified as a
2804 * constant expression in the first 64k of memory (ie ld $2,0x4000c) we
2805 * first load register 'at' with zero and use it as the base register. The
2806 * mips assembler simply uses register $zero. Just one tiny optimization
2811 struct mips_cl_insn
*ip
;
2813 register int treg
, sreg
, dreg
, breg
;
2828 bfd_reloc_code_real_type r
;
2830 int hold_mips_optimize
;
2834 treg
= (ip
->insn_opcode
>> 16) & 0x1f;
2835 dreg
= (ip
->insn_opcode
>> 11) & 0x1f;
2836 sreg
= breg
= (ip
->insn_opcode
>> 21) & 0x1f;
2837 mask
= ip
->insn_mo
->mask
;
2839 expr1
.X_op
= O_constant
;
2840 expr1
.X_op_symbol
= NULL
;
2841 expr1
.X_add_symbol
= NULL
;
2842 expr1
.X_add_number
= 1;
2854 mips_emit_delays ();
2856 mips_any_noreorder
= 1;
2858 expr1
.X_add_number
= 8;
2859 macro_build ((char *) NULL
, &icnt
, &expr1
, "bgez", "s,p", sreg
);
2861 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
2863 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
, sreg
, 0);
2864 macro_build ((char *) NULL
, &icnt
, NULL
,
2865 dbl
? "dsub" : "sub",
2866 "d,v,t", dreg
, 0, sreg
);
2889 if (imm_expr
.X_add_number
>= -0x8000 && imm_expr
.X_add_number
< 0x8000)
2891 macro_build ((char *) NULL
, &icnt
, &imm_expr
, s
, "t,r,j", treg
, sreg
,
2892 (int) BFD_RELOC_LO16
);
2895 load_register (&icnt
, AT
, &imm_expr
, dbl
);
2896 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "d,v,t", treg
, sreg
, AT
);
2915 if (imm_expr
.X_add_number
>= 0 && imm_expr
.X_add_number
< 0x10000)
2917 if (mask
!= M_NOR_I
)
2918 macro_build ((char *) NULL
, &icnt
, &imm_expr
, s
, "t,r,i", treg
,
2919 sreg
, (int) BFD_RELOC_LO16
);
2922 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "ori", "t,r,i",
2923 treg
, sreg
, (int) BFD_RELOC_LO16
);
2924 macro_build ((char *) NULL
, &icnt
, NULL
, "nor", "d,v,t",
2930 load_register (&icnt
, AT
, &imm_expr
, 0);
2931 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "d,v,t", treg
, sreg
, AT
);
2948 if (imm_expr
.X_add_number
== 0)
2950 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "s,t,p", sreg
,
2954 load_register (&icnt
, AT
, &imm_expr
, 0);
2955 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "s,t,p", sreg
, AT
);
2963 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2964 likely
? "bgezl" : "bgez",
2970 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2971 likely
? "blezl" : "blez",
2975 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", AT
, sreg
, treg
);
2976 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2977 likely
? "beql" : "beq",
2984 /* check for > max integer */
2985 maxnum
= 0x7fffffff;
2993 if (imm_expr
.X_add_number
>= maxnum
2994 && (mips_isa
< 3 || sizeof (maxnum
) > 4))
2997 /* result is always false */
3000 as_warn ("Branch %s is always false (nop)", ip
->insn_mo
->name
);
3001 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
3005 as_warn ("Branch likely %s is always false", ip
->insn_mo
->name
);
3006 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "bnel",
3011 imm_expr
.X_add_number
++;
3015 if (mask
== M_BGEL_I
)
3017 if (imm_expr
.X_add_number
== 0)
3019 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3020 likely
? "bgezl" : "bgez",
3024 if (imm_expr
.X_add_number
== 1)
3026 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3027 likely
? "bgtzl" : "bgtz",
3031 maxnum
= 0x7fffffff;
3039 maxnum
= - maxnum
- 1;
3040 if (imm_expr
.X_add_number
<= maxnum
3041 && (mips_isa
< 3 || sizeof (maxnum
) > 4))
3044 /* result is always true */
3045 as_warn ("Branch %s is always true", ip
->insn_mo
->name
);
3046 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "b", "p");
3049 set_at (&icnt
, sreg
, 0);
3050 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3051 likely
? "beql" : "beq",
3062 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3063 likely
? "beql" : "beq",
3067 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", AT
, sreg
,
3069 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3070 likely
? "beql" : "beq",
3077 if (sreg
== 0 || imm_expr
.X_add_number
== -1)
3079 imm_expr
.X_add_number
++;
3083 if (mask
== M_BGEUL_I
)
3085 if (imm_expr
.X_add_number
== 0)
3087 if (imm_expr
.X_add_number
== 1)
3089 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3090 likely
? "bnel" : "bne",
3094 set_at (&icnt
, sreg
, 1);
3095 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3096 likely
? "beql" : "beq",
3105 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3106 likely
? "bgtzl" : "bgtz",
3112 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3113 likely
? "bltzl" : "bltz",
3117 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", AT
, treg
, sreg
);
3118 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3119 likely
? "bnel" : "bne",
3128 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3129 likely
? "bnel" : "bne",
3135 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", AT
, treg
,
3137 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3138 likely
? "bnel" : "bne",
3147 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3148 likely
? "blezl" : "blez",
3154 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3155 likely
? "bgezl" : "bgez",
3159 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", AT
, treg
, sreg
);
3160 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3161 likely
? "beql" : "beq",
3168 maxnum
= 0x7fffffff;
3176 if (imm_expr
.X_add_number
>= maxnum
3177 && (mips_isa
< 3 || sizeof (maxnum
) > 4))
3179 imm_expr
.X_add_number
++;
3183 if (mask
== M_BLTL_I
)
3185 if (imm_expr
.X_add_number
== 0)
3187 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3188 likely
? "bltzl" : "bltz",
3192 if (imm_expr
.X_add_number
== 1)
3194 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3195 likely
? "blezl" : "blez",
3199 set_at (&icnt
, sreg
, 0);
3200 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3201 likely
? "bnel" : "bne",
3210 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3211 likely
? "beql" : "beq",
3217 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", AT
, treg
,
3219 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3220 likely
? "beql" : "beq",
3227 if (sreg
== 0 || imm_expr
.X_add_number
== -1)
3229 imm_expr
.X_add_number
++;
3233 if (mask
== M_BLTUL_I
)
3235 if (imm_expr
.X_add_number
== 0)
3237 if (imm_expr
.X_add_number
== 1)
3239 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3240 likely
? "beql" : "beq",
3244 set_at (&icnt
, sreg
, 1);
3245 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3246 likely
? "bnel" : "bne",
3255 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3256 likely
? "bltzl" : "bltz",
3262 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3263 likely
? "bgtzl" : "bgtz",
3267 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", AT
, sreg
, treg
);
3268 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3269 likely
? "bnel" : "bne",
3280 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3281 likely
? "bnel" : "bne",
3285 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", AT
, sreg
,
3287 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3288 likely
? "bnel" : "bne",
3304 as_warn ("Divide by zero.");
3306 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", 0, 0);
3308 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 7);
3312 mips_emit_delays ();
3314 mips_any_noreorder
= 1;
3315 macro_build ((char *) NULL
, &icnt
, NULL
,
3316 dbl
? "ddiv" : "div",
3317 "z,s,t", sreg
, treg
);
3319 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", treg
, 0);
3322 expr1
.X_add_number
= 8;
3323 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", treg
, 0);
3324 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
3325 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 7);
3327 expr1
.X_add_number
= -1;
3328 macro_build ((char *) NULL
, &icnt
, &expr1
,
3329 dbl
? "daddiu" : "addiu",
3330 "t,r,j", AT
, 0, (int) BFD_RELOC_LO16
);
3331 expr1
.X_add_number
= mips_trap
? (dbl
? 12 : 8) : (dbl
? 20 : 16);
3332 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", treg
, AT
);
3335 expr1
.X_add_number
= 1;
3336 macro_build ((char *) NULL
, &icnt
, &expr1
, "daddiu", "t,r,j", AT
, 0,
3337 (int) BFD_RELOC_LO16
);
3338 macro_build ((char *) NULL
, &icnt
, NULL
, "dsll32", "d,w,<", AT
, AT
,
3343 expr1
.X_add_number
= 0x80000000;
3344 macro_build ((char *) NULL
, &icnt
, &expr1
, "lui", "t,u", AT
,
3345 (int) BFD_RELOC_HI16
);
3348 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", sreg
, AT
);
3351 expr1
.X_add_number
= 8;
3352 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", sreg
, AT
);
3353 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
3354 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 6);
3357 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d", dreg
);
3396 if (imm_expr
.X_add_number
== 0)
3398 as_warn ("Divide by zero.");
3400 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", 0, 0);
3402 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 7);
3405 if (imm_expr
.X_add_number
== 1)
3407 if (strcmp (s2
, "mflo") == 0)
3408 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
,
3411 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
, 0);
3414 if (imm_expr
.X_add_number
== -1
3415 && s
[strlen (s
) - 1] != 'u')
3417 if (strcmp (s2
, "mflo") == 0)
3420 macro_build ((char *) NULL
, &icnt
, NULL
, "dneg", "d,w", dreg
,
3423 macro_build ((char *) NULL
, &icnt
, NULL
, "neg", "d,w", dreg
,
3427 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
, 0);
3431 load_register (&icnt
, AT
, &imm_expr
, dbl
);
3432 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "z,s,t", sreg
, AT
);
3433 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "d", dreg
);
3452 mips_emit_delays ();
3454 mips_any_noreorder
= 1;
3455 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "z,s,t", sreg
, treg
);
3457 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", treg
, 0);
3460 expr1
.X_add_number
= 8;
3461 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", treg
, 0);
3462 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
3463 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 7);
3466 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "d", dreg
);
3472 /* Load the address of a symbol into a register. If breg is not
3473 zero, we then add a base register to it. */
3475 /* When generating embedded PIC code, we permit expressions of
3478 where bar is an address in the .text section. These are used
3479 when getting the addresses of functions. We don't permit
3480 X_add_number to be non-zero, because if the symbol is
3481 external the relaxing code needs to know that any addend is
3482 purely the offset to X_op_symbol. */
3483 if (mips_pic
== EMBEDDED_PIC
3484 && offset_expr
.X_op
== O_subtract
3485 && now_seg
== text_section
3486 && (offset_expr
.X_op_symbol
->sy_value
.X_op
== O_constant
3487 ? S_GET_SEGMENT (offset_expr
.X_op_symbol
) == text_section
3488 : (offset_expr
.X_op_symbol
->sy_value
.X_op
== O_symbol
3489 && (S_GET_SEGMENT (offset_expr
.X_op_symbol
3490 ->sy_value
.X_add_symbol
)
3493 && offset_expr
.X_add_number
== 0)
3495 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
3496 treg
, (int) BFD_RELOC_PCREL_HI16_S
);
3497 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3498 mips_isa
< 3 ? "addiu" : "daddiu",
3499 "t,r,j", treg
, treg
, (int) BFD_RELOC_PCREL_LO16
);
3503 if (offset_expr
.X_op
!= O_symbol
3504 && offset_expr
.X_op
!= O_constant
)
3506 as_bad ("expression too complex");
3507 offset_expr
.X_op
= O_constant
;
3521 if (offset_expr
.X_op
== O_constant
)
3522 load_register (&icnt
, tempreg
, &offset_expr
, dbl
);
3523 else if (mips_pic
== NO_PIC
)
3525 /* If this is a reference to an GP relative symbol, we want
3526 addiu $tempreg,$gp,<sym> (BFD_RELOC_MIPS_GPREL)
3528 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
3529 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
3530 If we have a constant, we need two instructions anyhow,
3531 so we may as well always use the latter form. */
3532 if ((valueT
) offset_expr
.X_add_number
>= MAX_GPREL_OFFSET
3533 || nopic_need_relax (offset_expr
.X_add_symbol
))
3538 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3539 mips_isa
< 3 ? "addiu" : "daddiu",
3540 "t,r,j", tempreg
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
3541 p
= frag_var (rs_machine_dependent
, 8, 0,
3542 RELAX_ENCODE (4, 8, 0, 4, 0,
3543 mips_warn_about_macros
),
3544 offset_expr
.X_add_symbol
, (long) 0,
3547 macro_build_lui (p
, &icnt
, &offset_expr
, tempreg
);
3550 macro_build (p
, &icnt
, &offset_expr
,
3551 mips_isa
< 3 ? "addiu" : "daddiu",
3552 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
3554 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
3556 /* If this is a reference to an external symbol, and there
3557 is no constant, we want
3558 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3559 For a local symbol, we want
3560 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3562 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
3564 If we have a small constant, and this is a reference to
3565 an external symbol, we want
3566 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3568 addiu $tempreg,$tempreg,<constant>
3569 For a local symbol, we want the same instruction
3570 sequence, but we output a BFD_RELOC_LO16 reloc on the
3573 If we have a large constant, and this is a reference to
3574 an external symbol, we want
3575 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3576 lui $at,<hiconstant>
3577 addiu $at,$at,<loconstant>
3578 addu $tempreg,$tempreg,$at
3579 For a local symbol, we want the same instruction
3580 sequence, but we output a BFD_RELOC_LO16 reloc on the
3581 addiu instruction. */
3582 expr1
.X_add_number
= offset_expr
.X_add_number
;
3583 offset_expr
.X_add_number
= 0;
3585 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3587 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
3588 if (expr1
.X_add_number
== 0)
3596 /* We're going to put in an addu instruction using
3597 tempreg, so we may as well insert the nop right
3599 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3603 p
= frag_var (rs_machine_dependent
, 8 - off
, 0,
3604 RELAX_ENCODE (0, 8 - off
, -4 - off
, 4 - off
, 0,
3606 ? mips_warn_about_macros
3608 offset_expr
.X_add_symbol
, (long) 0,
3612 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
3615 macro_build (p
, &icnt
, &expr1
,
3616 mips_isa
< 3 ? "addiu" : "daddiu",
3617 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
3618 /* FIXME: If breg == 0, and the next instruction uses
3619 $tempreg, then if this variant case is used an extra
3620 nop will be generated. */
3622 else if (expr1
.X_add_number
>= -0x8000
3623 && expr1
.X_add_number
< 0x8000)
3625 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3627 macro_build ((char *) NULL
, &icnt
, &expr1
,
3628 mips_isa
< 3 ? "addiu" : "daddiu",
3629 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
3630 (void) frag_var (rs_machine_dependent
, 0, 0,
3631 RELAX_ENCODE (0, 0, -12, -4, 0, 0),
3632 offset_expr
.X_add_symbol
, (long) 0,
3639 /* If we are going to add in a base register, and the
3640 target register and the base register are the same,
3641 then we are using AT as a temporary register. Since
3642 we want to load the constant into AT, we add our
3643 current AT (from the global offset table) and the
3644 register into the register now, and pretend we were
3645 not using a base register. */
3650 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3652 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3653 mips_isa
< 3 ? "addu" : "daddu",
3654 "d,v,t", treg
, AT
, breg
);
3660 /* Set mips_optimize around the lui instruction to avoid
3661 inserting an unnecessary nop after the lw. */
3662 hold_mips_optimize
= mips_optimize
;
3664 macro_build_lui ((char *) NULL
, &icnt
, &expr1
, AT
);
3665 mips_optimize
= hold_mips_optimize
;
3667 macro_build ((char *) NULL
, &icnt
, &expr1
,
3668 mips_isa
< 3 ? "addiu" : "daddiu",
3669 "t,r,j", AT
, AT
, (int) BFD_RELOC_LO16
);
3670 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3671 mips_isa
< 3 ? "addu" : "daddu",
3672 "d,v,t", tempreg
, tempreg
, AT
);
3673 (void) frag_var (rs_machine_dependent
, 0, 0,
3674 RELAX_ENCODE (0, 0, -16 + off1
, -8, 0, 0),
3675 offset_expr
.X_add_symbol
, (long) 0,
3680 else if (mips_pic
== SVR4_PIC
)
3684 /* This is the large GOT case. If this is a reference to an
3685 external symbol, and there is no constant, we want
3686 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
3687 addu $tempreg,$tempreg,$gp
3688 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
3689 For a local symbol, we want
3690 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3692 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
3694 If we have a small constant, and this is a reference to
3695 an external symbol, we want
3696 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
3697 addu $tempreg,$tempreg,$gp
3698 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
3700 addiu $tempreg,$tempreg,<constant>
3701 For a local symbol, we want
3702 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3704 addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16)
3706 If we have a large constant, and this is a reference to
3707 an external symbol, we want
3708 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
3709 addu $tempreg,$tempreg,$gp
3710 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
3711 lui $at,<hiconstant>
3712 addiu $at,$at,<loconstant>
3713 addu $tempreg,$tempreg,$at
3714 For a local symbol, we want
3715 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3716 lui $at,<hiconstant>
3717 addiu $at,$at,<loconstant> (BFD_RELOC_LO16)
3718 addu $tempreg,$tempreg,$at
3720 expr1
.X_add_number
= offset_expr
.X_add_number
;
3721 offset_expr
.X_add_number
= 0;
3723 if (reg_needs_delay (GP
))
3727 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
3728 tempreg
, (int) BFD_RELOC_MIPS_GOT_HI16
);
3729 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3730 mips_isa
< 3 ? "addu" : "daddu",
3731 "d,v,t", tempreg
, tempreg
, GP
);
3732 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3734 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT_LO16
,
3736 if (expr1
.X_add_number
== 0)
3744 /* We're going to put in an addu instruction using
3745 tempreg, so we may as well insert the nop right
3747 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3752 p
= frag_var (rs_machine_dependent
, 12 + gpdel
, 0,
3753 RELAX_ENCODE (12 + off
, 12 + gpdel
, gpdel
,
3756 ? mips_warn_about_macros
3758 offset_expr
.X_add_symbol
, (long) 0,
3761 else if (expr1
.X_add_number
>= -0x8000
3762 && expr1
.X_add_number
< 0x8000)
3764 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3766 macro_build ((char *) NULL
, &icnt
, &expr1
,
3767 mips_isa
< 3 ? "addiu" : "daddiu",
3768 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
3770 p
= frag_var (rs_machine_dependent
, 12 + gpdel
, 0,
3771 RELAX_ENCODE (20, 12 + gpdel
, gpdel
, 8 + gpdel
, 0,
3773 ? mips_warn_about_macros
3775 offset_expr
.X_add_symbol
, (long) 0,
3782 /* If we are going to add in a base register, and the
3783 target register and the base register are the same,
3784 then we are using AT as a temporary register. Since
3785 we want to load the constant into AT, we add our
3786 current AT (from the global offset table) and the
3787 register into the register now, and pretend we were
3788 not using a base register. */
3796 assert (tempreg
== AT
);
3797 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3799 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3800 mips_isa
< 3 ? "addu" : "daddu",
3801 "d,v,t", treg
, AT
, breg
);
3806 /* Set mips_optimize around the lui instruction to avoid
3807 inserting an unnecessary nop after the lw. */
3808 hold_mips_optimize
= mips_optimize
;
3810 macro_build_lui ((char *) NULL
, &icnt
, &expr1
, AT
);
3811 mips_optimize
= hold_mips_optimize
;
3813 macro_build ((char *) NULL
, &icnt
, &expr1
,
3814 mips_isa
< 3 ? "addiu" : "daddiu",
3815 "t,r,j", AT
, AT
, (int) BFD_RELOC_LO16
);
3816 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3817 mips_isa
< 3 ? "addu" : "daddu",
3818 "d,v,t", dreg
, dreg
, AT
);
3820 p
= frag_var (rs_machine_dependent
, 16 + gpdel
+ adj
, 0,
3821 RELAX_ENCODE (24 + adj
, 16 + gpdel
+ adj
, gpdel
,
3824 ? mips_warn_about_macros
3826 offset_expr
.X_add_symbol
, (long) 0,
3834 /* This is needed because this instruction uses $gp, but
3835 the first instruction on the main stream does not. */
3836 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
3839 macro_build (p
, &icnt
, &offset_expr
,
3841 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
3843 if (expr1
.X_add_number
>= -0x8000
3844 && expr1
.X_add_number
< 0x8000)
3846 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
3848 macro_build (p
, &icnt
, &expr1
,
3849 mips_isa
< 3 ? "addiu" : "daddiu",
3850 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
3851 /* FIXME: If add_number is 0, and there was no base
3852 register, the external symbol case ended with a load,
3853 so if the symbol turns out to not be external, and
3854 the next instruction uses tempreg, an unnecessary nop
3855 will be inserted. */
3861 /* We must add in the base register now, as in the
3862 external symbol case. */
3863 assert (tempreg
== AT
);
3864 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
3866 macro_build (p
, &icnt
, (expressionS
*) NULL
,
3867 mips_isa
< 3 ? "addu" : "daddu",
3868 "d,v,t", treg
, AT
, breg
);
3871 /* We set breg to 0 because we have arranged to add
3872 it in in both cases. */
3876 macro_build_lui (p
, &icnt
, &expr1
, AT
);
3878 macro_build (p
, &icnt
, &expr1
,
3879 mips_isa
< 3 ? "addiu" : "daddiu",
3880 "t,r,j", AT
, AT
, (int) BFD_RELOC_LO16
);
3882 macro_build (p
, &icnt
, (expressionS
*) NULL
,
3883 mips_isa
< 3 ? "addu" : "daddu",
3884 "d,v,t", tempreg
, tempreg
, AT
);
3888 else if (mips_pic
== EMBEDDED_PIC
)
3891 addiu $tempreg,$gp,<sym> (BFD_RELOC_MIPS_GPREL)
3893 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3894 mips_isa
< 3 ? "addiu" : "daddiu",
3895 "t,r,j", tempreg
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
3901 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3902 mips_isa
< 3 ? "addu" : "daddu",
3903 "d,v,t", treg
, tempreg
, breg
);
3911 /* The j instruction may not be used in PIC code, since it
3912 requires an absolute address. We convert it to a b
3914 if (mips_pic
== NO_PIC
)
3915 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "j", "a");
3917 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "b", "p");
3920 /* The jal instructions must be handled as macros because when
3921 generating PIC code they expand to multi-instruction
3922 sequences. Normally they are simple instructions. */
3927 if (mips_pic
== NO_PIC
3928 || mips_pic
== EMBEDDED_PIC
)
3929 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "jalr",
3931 else if (mips_pic
== SVR4_PIC
)
3933 if (sreg
!= PIC_CALL_REG
)
3934 as_warn ("MIPS PIC call to register other than $25");
3936 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "jalr",
3938 if (mips_cprestore_offset
< 0)
3939 as_warn ("No .cprestore pseudo-op used in PIC code");
3942 expr1
.X_add_number
= mips_cprestore_offset
;
3943 macro_build ((char *) NULL
, &icnt
, &expr1
,
3944 mips_isa
< 3 ? "lw" : "ld",
3945 "t,o(b)", GP
, (int) BFD_RELOC_LO16
, mips_frame_reg
);
3954 if (mips_pic
== NO_PIC
)
3955 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "jal", "a");
3956 else if (mips_pic
== SVR4_PIC
)
3958 /* If this is a reference to an external symbol, and we are
3959 using a small GOT, we want
3960 lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
3964 lw $gp,cprestore($sp)
3965 The cprestore value is set using the .cprestore
3966 pseudo-op. If we are using a big GOT, we want
3967 lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16)
3969 lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16)
3973 lw $gp,cprestore($sp)
3974 If the symbol is not external, we want
3975 lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3977 addiu $25,$25,<sym> (BFD_RELOC_LO16)
3980 lw $gp,cprestore($sp) */
3984 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3985 mips_isa
< 3 ? "lw" : "ld",
3986 "t,o(b)", PIC_CALL_REG
,
3987 (int) BFD_RELOC_MIPS_CALL16
, GP
);
3988 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3990 p
= frag_var (rs_machine_dependent
, 4, 0,
3991 RELAX_ENCODE (0, 4, -8, 0, 0, 0),
3992 offset_expr
.X_add_symbol
, (long) 0, (char *) NULL
);
3998 if (reg_needs_delay (GP
))
4002 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
4003 PIC_CALL_REG
, (int) BFD_RELOC_MIPS_CALL_HI16
);
4004 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4005 mips_isa
< 3 ? "addu" : "daddu",
4006 "d,v,t", PIC_CALL_REG
, PIC_CALL_REG
, GP
);
4007 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4008 mips_isa
< 3 ? "lw" : "ld",
4009 "t,o(b)", PIC_CALL_REG
,
4010 (int) BFD_RELOC_MIPS_CALL_LO16
, PIC_CALL_REG
);
4011 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4013 p
= frag_var (rs_machine_dependent
, 12 + gpdel
, 0,
4014 RELAX_ENCODE (16, 12 + gpdel
, gpdel
, 8 + gpdel
,
4016 offset_expr
.X_add_symbol
, (long) 0, (char *) NULL
);
4019 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4022 macro_build (p
, &icnt
, &offset_expr
,
4023 mips_isa
< 3 ? "lw" : "ld",
4024 "t,o(b)", PIC_CALL_REG
,
4025 (int) BFD_RELOC_MIPS_GOT16
, GP
);
4027 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4030 macro_build (p
, &icnt
, &offset_expr
,
4031 mips_isa
< 3 ? "addiu" : "daddiu",
4032 "t,r,j", PIC_CALL_REG
, PIC_CALL_REG
,
4033 (int) BFD_RELOC_LO16
);
4034 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4035 "jalr", "s", PIC_CALL_REG
);
4036 if (mips_cprestore_offset
< 0)
4037 as_warn ("No .cprestore pseudo-op used in PIC code");
4041 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4043 expr1
.X_add_number
= mips_cprestore_offset
;
4044 macro_build ((char *) NULL
, &icnt
, &expr1
,
4045 mips_isa
< 3 ? "lw" : "ld",
4046 "t,o(b)", GP
, (int) BFD_RELOC_LO16
,
4050 else if (mips_pic
== EMBEDDED_PIC
)
4052 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "bal", "p");
4053 /* The linker may expand the call to a longer sequence which
4054 uses $at, so we must break rather than return. */
4130 if (breg
== treg
|| coproc
|| lr
)
4199 if (mask
== M_LWC1_AB
4200 || mask
== M_SWC1_AB
4201 || mask
== M_LDC1_AB
4202 || mask
== M_SDC1_AB
4211 if (offset_expr
.X_op
!= O_constant
4212 && offset_expr
.X_op
!= O_symbol
)
4214 as_bad ("expression too complex");
4215 offset_expr
.X_op
= O_constant
;
4218 /* A constant expression in PIC code can be handled just as it
4219 is in non PIC code. */
4220 if (mips_pic
== NO_PIC
4221 || offset_expr
.X_op
== O_constant
)
4223 /* If this is a reference to a GP relative symbol, and there
4224 is no base register, we want
4225 <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL)
4226 Otherwise, if there is no base register, we want
4227 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
4228 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
4229 If we have a constant, we need two instructions anyhow,
4230 so we always use the latter form.
4232 If we have a base register, and this is a reference to a
4233 GP relative symbol, we want
4234 addu $tempreg,$breg,$gp
4235 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GPREL)
4237 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
4238 addu $tempreg,$tempreg,$breg
4239 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
4240 With a constant we always use the latter case. */
4243 if ((valueT
) offset_expr
.X_add_number
>= MAX_GPREL_OFFSET
4244 || nopic_need_relax (offset_expr
.X_add_symbol
))
4249 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
4250 treg
, (int) BFD_RELOC_MIPS_GPREL
, GP
);
4251 p
= frag_var (rs_machine_dependent
, 8, 0,
4252 RELAX_ENCODE (4, 8, 0, 4, 0,
4253 (mips_warn_about_macros
4254 || (used_at
&& mips_noat
))),
4255 offset_expr
.X_add_symbol
, (long) 0,
4259 macro_build_lui (p
, &icnt
, &offset_expr
, tempreg
);
4262 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
, treg
,
4263 (int) BFD_RELOC_LO16
, tempreg
);
4267 if ((valueT
) offset_expr
.X_add_number
>= MAX_GPREL_OFFSET
4268 || nopic_need_relax (offset_expr
.X_add_symbol
))
4273 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4274 mips_isa
< 3 ? "addu" : "daddu",
4275 "d,v,t", tempreg
, breg
, GP
);
4276 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
4277 treg
, (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
4278 p
= frag_var (rs_machine_dependent
, 12, 0,
4279 RELAX_ENCODE (8, 12, 0, 8, 0, 0),
4280 offset_expr
.X_add_symbol
, (long) 0,
4283 macro_build_lui (p
, &icnt
, &offset_expr
, tempreg
);
4286 macro_build (p
, &icnt
, (expressionS
*) NULL
,
4287 mips_isa
< 3 ? "addu" : "daddu",
4288 "d,v,t", tempreg
, tempreg
, breg
);
4291 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
, treg
,
4292 (int) BFD_RELOC_LO16
, tempreg
);
4295 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
4297 /* If this is a reference to an external symbol, we want
4298 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4300 <op> $treg,0($tempreg)
4302 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4304 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
4305 <op> $treg,0($tempreg)
4306 If there is a base register, we add it to $tempreg before
4307 the <op>. If there is a constant, we stick it in the
4308 <op> instruction. We don't handle constants larger than
4309 16 bits, because we have no way to load the upper 16 bits
4310 (actually, we could handle them for the subset of cases
4311 in which we are not using $at). */
4312 assert (offset_expr
.X_op
== O_symbol
);
4313 expr1
.X_add_number
= offset_expr
.X_add_number
;
4314 offset_expr
.X_add_number
= 0;
4315 if (expr1
.X_add_number
< -0x8000
4316 || expr1
.X_add_number
>= 0x8000)
4317 as_bad ("PIC code offset overflow (max 16 signed bits)");
4319 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4320 mips_isa
< 3 ? "lw" : "ld",
4321 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
4322 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
4323 p
= frag_var (rs_machine_dependent
, 4, 0,
4324 RELAX_ENCODE (0, 4, -8, 0, 0, 0),
4325 offset_expr
.X_add_symbol
, (long) 0,
4327 macro_build (p
, &icnt
, &offset_expr
,
4328 mips_isa
< 3 ? "addiu" : "daddiu",
4329 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
4331 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4332 mips_isa
< 3 ? "addu" : "daddu",
4333 "d,v,t", tempreg
, tempreg
, breg
);
4334 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
, treg
,
4335 (int) BFD_RELOC_LO16
, tempreg
);
4337 else if (mips_pic
== SVR4_PIC
)
4341 /* If this is a reference to an external symbol, we want
4342 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
4343 addu $tempreg,$tempreg,$gp
4344 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
4345 <op> $treg,0($tempreg)
4347 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4349 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
4350 <op> $treg,0($tempreg)
4351 If there is a base register, we add it to $tempreg before
4352 the <op>. If there is a constant, we stick it in the
4353 <op> instruction. We don't handle constants larger than
4354 16 bits, because we have no way to load the upper 16 bits
4355 (actually, we could handle them for the subset of cases
4356 in which we are not using $at). */
4357 assert (offset_expr
.X_op
== O_symbol
);
4358 expr1
.X_add_number
= offset_expr
.X_add_number
;
4359 offset_expr
.X_add_number
= 0;
4360 if (expr1
.X_add_number
< -0x8000
4361 || expr1
.X_add_number
>= 0x8000)
4362 as_bad ("PIC code offset overflow (max 16 signed bits)");
4363 if (reg_needs_delay (GP
))
4368 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
4369 tempreg
, (int) BFD_RELOC_MIPS_GOT_HI16
);
4370 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4371 mips_isa
< 3 ? "addu" : "daddu",
4372 "d,v,t", tempreg
, tempreg
, GP
);
4373 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4374 mips_isa
< 3 ? "lw" : "ld",
4375 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT_LO16
,
4377 p
= frag_var (rs_machine_dependent
, 12 + gpdel
, 0,
4378 RELAX_ENCODE (12, 12 + gpdel
, gpdel
, 8 + gpdel
, 0, 0),
4379 offset_expr
.X_add_symbol
, (long) 0, (char *) NULL
);
4382 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4385 macro_build (p
, &icnt
, &offset_expr
,
4386 mips_isa
< 3 ? "lw" : "ld",
4387 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
4389 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4391 macro_build (p
, &icnt
, &offset_expr
,
4392 mips_isa
< 3 ? "addiu" : "daddiu",
4393 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
4395 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4396 mips_isa
< 3 ? "addu" : "daddu",
4397 "d,v,t", tempreg
, tempreg
, breg
);
4398 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
, treg
,
4399 (int) BFD_RELOC_LO16
, tempreg
);
4401 else if (mips_pic
== EMBEDDED_PIC
)
4403 /* If there is no base register, we want
4404 <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL)
4405 If there is a base register, we want
4406 addu $tempreg,$breg,$gp
4407 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GPREL)
4409 assert (offset_expr
.X_op
== O_symbol
);
4412 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
4413 treg
, (int) BFD_RELOC_MIPS_GPREL
, GP
);
4418 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4419 mips_isa
< 3 ? "addu" : "daddu",
4420 "d,v,t", tempreg
, breg
, GP
);
4421 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
4422 treg
, (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
4435 load_register (&icnt
, treg
, &imm_expr
, 0);
4439 load_register (&icnt
, treg
, &imm_expr
, 1);
4443 if (imm_expr
.X_op
== O_constant
)
4445 load_register (&icnt
, AT
, &imm_expr
, 0);
4446 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4447 "mtc1", "t,G", AT
, treg
);
4452 assert (offset_expr
.X_op
== O_symbol
4453 && strcmp (segment_name (S_GET_SEGMENT
4454 (offset_expr
.X_add_symbol
)),
4456 && offset_expr
.X_add_number
== 0);
4457 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lwc1", "T,o(b)",
4458 treg
, (int) BFD_RELOC_MIPS_LITERAL
, GP
);
4463 /* We know that sym is in the .rdata section. First we get the
4464 upper 16 bits of the address. */
4465 if (mips_pic
== NO_PIC
)
4467 /* FIXME: This won't work for a 64 bit address. */
4468 macro_build_lui ((char *) NULL
, &icnt
, &offset_expr
, AT
);
4470 else if (mips_pic
== SVR4_PIC
)
4472 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4473 mips_isa
< 3 ? "lw" : "ld",
4474 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
4476 else if (mips_pic
== EMBEDDED_PIC
)
4478 /* For embedded PIC we pick up the entire address off $gp in
4479 a single instruction. */
4480 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4481 mips_isa
< 3 ? "addiu" : "daddiu",
4482 "t,r,j", AT
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
4483 offset_expr
.X_op
= O_constant
;
4484 offset_expr
.X_add_number
= 0;
4489 /* Now we load the register(s). */
4491 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "ld", "t,o(b)",
4492 treg
, (int) BFD_RELOC_LO16
, AT
);
4495 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lw", "t,o(b)",
4496 treg
, (int) BFD_RELOC_LO16
, AT
);
4499 /* FIXME: How in the world do we deal with the possible
4501 offset_expr
.X_add_number
+= 4;
4502 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lw", "t,o(b)",
4503 treg
+ 1, (int) BFD_RELOC_LO16
, AT
);
4507 /* To avoid confusion in tc_gen_reloc, we must ensure that this
4508 does not become a variant frag. */
4509 frag_wane (frag_now
);
4515 assert (offset_expr
.X_op
== O_symbol
4516 && offset_expr
.X_add_number
== 0);
4517 s
= segment_name (S_GET_SEGMENT (offset_expr
.X_add_symbol
));
4518 if (strcmp (s
, ".lit8") == 0)
4522 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "ldc1",
4523 "T,o(b)", treg
, (int) BFD_RELOC_MIPS_LITERAL
, GP
);
4527 r
= BFD_RELOC_MIPS_LITERAL
;
4532 assert (strcmp (s
, RDATA_SECTION_NAME
) == 0);
4533 if (mips_pic
== SVR4_PIC
)
4534 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4535 mips_isa
< 3 ? "lw" : "ld",
4536 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
4539 /* FIXME: This won't work for a 64 bit address. */
4540 macro_build_lui ((char *) NULL
, &icnt
, &offset_expr
, AT
);
4545 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "ldc1",
4546 "T,o(b)", treg
, (int) BFD_RELOC_LO16
, AT
);
4548 /* To avoid confusion in tc_gen_reloc, we must ensure
4549 that this does not become a variant frag. */
4550 frag_wane (frag_now
);
4561 /* Even on a big endian machine $fn comes before $fn+1. We have
4562 to adjust when loading from memory. */
4565 assert (mips_isa
< 2);
4566 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lwc1", "T,o(b)",
4567 byte_order
== LITTLE_ENDIAN
? treg
: treg
+ 1,
4569 /* FIXME: A possible overflow which I don't know how to deal
4571 offset_expr
.X_add_number
+= 4;
4572 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lwc1", "T,o(b)",
4573 byte_order
== LITTLE_ENDIAN
? treg
+ 1 : treg
,
4576 /* To avoid confusion in tc_gen_reloc, we must ensure that this
4577 does not become a variant frag. */
4578 frag_wane (frag_now
);
4587 * The MIPS assembler seems to check for X_add_number not
4588 * being double aligned and generating:
4591 * addiu at,at,%lo(foo+1)
4594 * But, the resulting address is the same after relocation so why
4595 * generate the extra instruction?
4642 if (offset_expr
.X_op
!= O_symbol
4643 && offset_expr
.X_op
!= O_constant
)
4645 as_bad ("expression too complex");
4646 offset_expr
.X_op
= O_constant
;
4649 /* Even on a big endian machine $fn comes before $fn+1. We have
4650 to adjust when loading from memory. We set coproc if we must
4651 load $fn+1 first. */
4652 if (byte_order
== LITTLE_ENDIAN
)
4655 if (mips_pic
== NO_PIC
4656 || offset_expr
.X_op
== O_constant
)
4658 /* If this is a reference to a GP relative symbol, we want
4659 <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL)
4660 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_MIPS_GPREL)
4661 If we have a base register, we use this
4663 <op> $treg,<sym>($at) (BFD_RELOC_MIPS_GPREL)
4664 <op> $treg+1,<sym>+4($at) (BFD_RELOC_MIPS_GPREL)
4665 If this is not a GP relative symbol, we want
4666 lui $at,<sym> (BFD_RELOC_HI16_S)
4667 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
4668 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
4669 If there is a base register, we add it to $at after the
4670 lui instruction. If there is a constant, we always use
4672 if ((valueT
) offset_expr
.X_add_number
>= MAX_GPREL_OFFSET
4673 || nopic_need_relax (offset_expr
.X_add_symbol
))
4692 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4693 mips_isa
< 3 ? "addu" : "daddu",
4694 "d,v,t", AT
, breg
, GP
);
4700 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
4701 coproc
? treg
+ 1 : treg
,
4702 (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
4703 offset_expr
.X_add_number
+= 4;
4705 /* Set mips_optimize to 2 to avoid inserting an
4707 hold_mips_optimize
= mips_optimize
;
4709 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
4710 coproc
? treg
: treg
+ 1,
4711 (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
4712 mips_optimize
= hold_mips_optimize
;
4714 p
= frag_var (rs_machine_dependent
, 12 + off
, 0,
4715 RELAX_ENCODE (8 + off
, 12 + off
, 0, 4 + off
, 1,
4716 used_at
&& mips_noat
),
4717 offset_expr
.X_add_symbol
, (long) 0,
4720 /* We just generated two relocs. When tc_gen_reloc
4721 handles this case, it will skip the first reloc and
4722 handle the second. The second reloc already has an
4723 extra addend of 4, which we added above. We must
4724 subtract it out, and then subtract another 4 to make
4725 the first reloc come out right. The second reloc
4726 will come out right because we are going to add 4 to
4727 offset_expr when we build its instruction below. */
4728 offset_expr
.X_add_number
-= 8;
4729 offset_expr
.X_op
= O_constant
;
4731 macro_build_lui (p
, &icnt
, &offset_expr
, AT
);
4736 macro_build (p
, &icnt
, (expressionS
*) NULL
,
4737 mips_isa
< 3 ? "addu" : "daddu",
4738 "d,v,t", AT
, breg
, AT
);
4742 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
,
4743 coproc
? treg
+ 1 : treg
,
4744 (int) BFD_RELOC_LO16
, AT
);
4747 /* FIXME: How do we handle overflow here? */
4748 offset_expr
.X_add_number
+= 4;
4749 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
,
4750 coproc
? treg
: treg
+ 1,
4751 (int) BFD_RELOC_LO16
, AT
);
4753 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
4757 /* If this is a reference to an external symbol, we want
4758 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4763 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4765 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
4766 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
4767 If there is a base register we add it to $at before the
4768 lwc1 instructions. If there is a constant we include it
4769 in the lwc1 instructions. */
4771 expr1
.X_add_number
= offset_expr
.X_add_number
;
4772 offset_expr
.X_add_number
= 0;
4773 if (expr1
.X_add_number
< -0x8000
4774 || expr1
.X_add_number
>= 0x8000 - 4)
4775 as_bad ("PIC code offset overflow (max 16 signed bits)");
4780 frag_grow (24 + off
);
4781 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4782 mips_isa
< 3 ? "lw" : "ld",
4783 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
4784 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
4786 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4787 mips_isa
< 3 ? "addu" : "daddu",
4788 "d,v,t", AT
, breg
, AT
);
4789 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
4790 coproc
? treg
+ 1 : treg
,
4791 (int) BFD_RELOC_LO16
, AT
);
4792 expr1
.X_add_number
+= 4;
4794 /* Set mips_optimize to 2 to avoid inserting an undesired
4796 hold_mips_optimize
= mips_optimize
;
4798 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
4799 coproc
? treg
: treg
+ 1,
4800 (int) BFD_RELOC_LO16
, AT
);
4801 mips_optimize
= hold_mips_optimize
;
4803 (void) frag_var (rs_machine_dependent
, 0, 0,
4804 RELAX_ENCODE (0, 0, -16 - off
, -8, 1, 0),
4805 offset_expr
.X_add_symbol
, (long) 0,
4808 else if (mips_pic
== SVR4_PIC
)
4812 /* If this is a reference to an external symbol, we want
4813 lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16)
4815 lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16)
4820 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4822 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
4823 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
4824 If there is a base register we add it to $at before the
4825 lwc1 instructions. If there is a constant we include it
4826 in the lwc1 instructions. */
4828 expr1
.X_add_number
= offset_expr
.X_add_number
;
4829 offset_expr
.X_add_number
= 0;
4830 if (expr1
.X_add_number
< -0x8000
4831 || expr1
.X_add_number
>= 0x8000 - 4)
4832 as_bad ("PIC code offset overflow (max 16 signed bits)");
4833 if (reg_needs_delay (GP
))
4842 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
4843 AT
, (int) BFD_RELOC_MIPS_GOT_HI16
);
4844 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4845 mips_isa
< 3 ? "addu" : "daddu",
4846 "d,v,t", AT
, AT
, GP
);
4847 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4848 mips_isa
< 3 ? "lw" : "ld",
4849 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT_LO16
, AT
);
4850 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
4852 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4853 mips_isa
< 3 ? "addu" : "daddu",
4854 "d,v,t", AT
, breg
, AT
);
4855 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
4856 coproc
? treg
+ 1 : treg
,
4857 (int) BFD_RELOC_LO16
, AT
);
4858 expr1
.X_add_number
+= 4;
4860 /* Set mips_optimize to 2 to avoid inserting an undesired
4862 hold_mips_optimize
= mips_optimize
;
4864 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
4865 coproc
? treg
: treg
+ 1,
4866 (int) BFD_RELOC_LO16
, AT
);
4867 mips_optimize
= hold_mips_optimize
;
4868 expr1
.X_add_number
-= 4;
4870 p
= frag_var (rs_machine_dependent
, 16 + gpdel
+ off
, 0,
4871 RELAX_ENCODE (24 + off
, 16 + gpdel
+ off
, gpdel
,
4872 8 + gpdel
+ off
, 1, 0),
4873 offset_expr
.X_add_symbol
, (long) 0,
4877 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4880 macro_build (p
, &icnt
, &offset_expr
,
4881 mips_isa
< 3 ? "lw" : "ld",
4882 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
4884 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4888 macro_build (p
, &icnt
, (expressionS
*) NULL
,
4889 mips_isa
< 3 ? "addu" : "daddu",
4890 "d,v,t", AT
, breg
, AT
);
4893 macro_build (p
, &icnt
, &expr1
, s
, fmt
,
4894 coproc
? treg
+ 1 : treg
,
4895 (int) BFD_RELOC_LO16
, AT
);
4897 expr1
.X_add_number
+= 4;
4899 /* Set mips_optimize to 2 to avoid inserting an undesired
4901 hold_mips_optimize
= mips_optimize
;
4903 macro_build (p
, &icnt
, &expr1
, s
, fmt
,
4904 coproc
? treg
: treg
+ 1,
4905 (int) BFD_RELOC_LO16
, AT
);
4906 mips_optimize
= hold_mips_optimize
;
4908 else if (mips_pic
== EMBEDDED_PIC
)
4910 /* If there is no base register, we use
4911 <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL)
4912 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_MIPS_GPREL)
4913 If we have a base register, we use
4915 <op> $treg,<sym>($at) (BFD_RELOC_MIPS_GPREL)
4916 <op> $treg+1,<sym>+4($at) (BFD_RELOC_MIPS_GPREL)
4925 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4926 mips_isa
< 3 ? "addu" : "daddu",
4927 "d,v,t", AT
, breg
, GP
);
4932 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
4933 coproc
? treg
+ 1 : treg
,
4934 (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
4935 offset_expr
.X_add_number
+= 4;
4936 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
4937 coproc
? treg
: treg
+ 1,
4938 (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
4954 assert (mips_isa
< 3);
4955 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
4956 (int) BFD_RELOC_LO16
, breg
);
4957 offset_expr
.X_add_number
+= 4;
4958 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
+ 1,
4959 (int) BFD_RELOC_LO16
, breg
);
4961 #ifdef LOSING_COMPILER
4967 as_warn ("Macro used $at after \".set noat\"");
4972 struct mips_cl_insn
*ip
;
4974 register int treg
, sreg
, dreg
, breg
;
4989 bfd_reloc_code_real_type r
;
4992 treg
= (ip
->insn_opcode
>> 16) & 0x1f;
4993 dreg
= (ip
->insn_opcode
>> 11) & 0x1f;
4994 sreg
= breg
= (ip
->insn_opcode
>> 21) & 0x1f;
4995 mask
= ip
->insn_mo
->mask
;
4997 expr1
.X_op
= O_constant
;
4998 expr1
.X_op_symbol
= NULL
;
4999 expr1
.X_add_symbol
= NULL
;
5000 expr1
.X_add_number
= 1;
5004 #endif /* LOSING_COMPILER */
5009 macro_build ((char *) NULL
, &icnt
, NULL
,
5010 dbl
? "dmultu" : "multu",
5012 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
5018 /* The MIPS assembler some times generates shifts and adds. I'm
5019 not trying to be that fancy. GCC should do this for us
5021 load_register (&icnt
, AT
, &imm_expr
, dbl
);
5022 macro_build ((char *) NULL
, &icnt
, NULL
,
5023 dbl
? "dmult" : "mult",
5025 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
5031 mips_emit_delays ();
5033 mips_any_noreorder
= 1;
5034 macro_build ((char *) NULL
, &icnt
, NULL
,
5035 dbl
? "dmult" : "mult",
5037 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
5038 macro_build ((char *) NULL
, &icnt
, NULL
,
5039 dbl
? "dsra32" : "sra",
5040 "d,w,<", dreg
, dreg
, 31);
5041 macro_build ((char *) NULL
, &icnt
, NULL
, "mfhi", "d", AT
);
5043 macro_build ((char *) NULL
, &icnt
, NULL
, "tne", "s,t", dreg
, AT
);
5046 expr1
.X_add_number
= 8;
5047 macro_build ((char *) NULL
, &icnt
, &expr1
, "beq", "s,t,p", dreg
, AT
);
5048 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
5049 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 6);
5052 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
5058 mips_emit_delays ();
5060 mips_any_noreorder
= 1;
5061 macro_build ((char *) NULL
, &icnt
, NULL
,
5062 dbl
? "dmultu" : "multu",
5064 macro_build ((char *) NULL
, &icnt
, NULL
, "mfhi", "d", AT
);
5065 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
5067 macro_build ((char *) NULL
, &icnt
, NULL
, "tne", "s,t", AT
, 0);
5070 expr1
.X_add_number
= 8;
5071 macro_build ((char *) NULL
, &icnt
, &expr1
, "beq", "s,t,p", AT
, 0);
5072 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
5073 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 6);
5079 macro_build ((char *) NULL
, &icnt
, NULL
, "subu", "d,v,t", AT
, 0, treg
);
5080 macro_build ((char *) NULL
, &icnt
, NULL
, "srlv", "d,t,s", AT
, sreg
, AT
);
5081 macro_build ((char *) NULL
, &icnt
, NULL
, "sllv", "d,t,s", dreg
, sreg
,
5083 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
5087 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", AT
, sreg
,
5088 (int) (imm_expr
.X_add_number
& 0x1f));
5089 macro_build ((char *) NULL
, &icnt
, NULL
, "srl", "d,w,<", dreg
, sreg
,
5090 (int) ((0 - imm_expr
.X_add_number
) & 0x1f));
5091 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
5095 macro_build ((char *) NULL
, &icnt
, NULL
, "subu", "d,v,t", AT
, 0, treg
);
5096 macro_build ((char *) NULL
, &icnt
, NULL
, "sllv", "d,t,s", AT
, sreg
, AT
);
5097 macro_build ((char *) NULL
, &icnt
, NULL
, "srlv", "d,t,s", dreg
, sreg
,
5099 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
5103 macro_build ((char *) NULL
, &icnt
, NULL
, "srl", "d,w,<", AT
, sreg
,
5104 (int) (imm_expr
.X_add_number
& 0x1f));
5105 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", dreg
, sreg
,
5106 (int) ((0 - imm_expr
.X_add_number
) & 0x1f));
5107 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
5111 assert (mips_isa
< 2);
5112 /* Even on a big endian machine $fn comes before $fn+1. We have
5113 to adjust when storing to memory. */
5114 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "swc1", "T,o(b)",
5115 byte_order
== LITTLE_ENDIAN
? treg
: treg
+ 1,
5116 (int) BFD_RELOC_LO16
, breg
);
5117 offset_expr
.X_add_number
+= 4;
5118 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "swc1", "T,o(b)",
5119 byte_order
== LITTLE_ENDIAN
? treg
+ 1 : treg
,
5120 (int) BFD_RELOC_LO16
, breg
);
5125 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
5126 treg
, (int) BFD_RELOC_LO16
);
5128 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
5129 sreg
, (int) BFD_RELOC_LO16
);
5132 macro_build ((char *) NULL
, &icnt
, NULL
, "xor", "d,v,t", dreg
,
5134 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
5135 dreg
, (int) BFD_RELOC_LO16
);
5140 if (imm_expr
.X_add_number
== 0)
5142 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
5143 sreg
, (int) BFD_RELOC_LO16
);
5148 as_warn ("Instruction %s: result is always false",
5150 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
, 0);
5153 if (imm_expr
.X_add_number
>= 0 && imm_expr
.X_add_number
< 0x10000)
5155 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "xori", "t,r,i", dreg
,
5156 sreg
, (int) BFD_RELOC_LO16
);
5159 else if (imm_expr
.X_add_number
> -0x8000 && imm_expr
.X_add_number
< 0)
5161 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
5162 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
5163 mips_isa
< 3 ? "addiu" : "daddiu",
5164 "t,r,j", dreg
, sreg
,
5165 (int) BFD_RELOC_LO16
);
5170 load_register (&icnt
, AT
, &imm_expr
, 0);
5171 macro_build ((char *) NULL
, &icnt
, NULL
, "xor", "d,v,t", dreg
,
5175 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
, dreg
,
5176 (int) BFD_RELOC_LO16
);
5181 case M_SGE
: /* sreg >= treg <==> not (sreg < treg) */
5187 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, sreg
, treg
);
5188 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
5189 (int) BFD_RELOC_LO16
);
5192 case M_SGE_I
: /* sreg >= I <==> not (sreg < I) */
5194 if (imm_expr
.X_add_number
>= -0x8000 && imm_expr
.X_add_number
< 0x8000)
5196 macro_build ((char *) NULL
, &icnt
, &expr1
,
5197 mask
== M_SGE_I
? "slti" : "sltiu",
5198 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
5203 load_register (&icnt
, AT
, &imm_expr
, 0);
5204 macro_build ((char *) NULL
, &icnt
, NULL
,
5205 mask
== M_SGE_I
? "slt" : "sltu",
5206 "d,v,t", dreg
, sreg
, AT
);
5209 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
5210 (int) BFD_RELOC_LO16
);
5215 case M_SGT
: /* sreg > treg <==> treg < sreg */
5221 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, treg
, sreg
);
5224 case M_SGT_I
: /* sreg > I <==> I < sreg */
5230 load_register (&icnt
, AT
, &imm_expr
, 0);
5231 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, AT
, sreg
);
5234 case M_SLE
: /* sreg <= treg <==> treg >= sreg <==> not (treg < sreg) */
5240 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, treg
, sreg
);
5241 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
5242 (int) BFD_RELOC_LO16
);
5245 case M_SLE_I
: /* sreg <= I <==> I >= sreg <==> not (I < sreg) */
5251 load_register (&icnt
, AT
, &imm_expr
, 0);
5252 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, AT
, sreg
);
5253 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
5254 (int) BFD_RELOC_LO16
);
5258 if (imm_expr
.X_add_number
>= -0x8000 && imm_expr
.X_add_number
< 0x8000)
5260 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "slti", "t,r,j",
5261 dreg
, sreg
, (int) BFD_RELOC_LO16
);
5264 load_register (&icnt
, AT
, &imm_expr
, 0);
5265 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", dreg
, sreg
, AT
);
5269 if (imm_expr
.X_add_number
>= -0x8000 && imm_expr
.X_add_number
< 0x8000)
5271 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "sltiu", "t,r,j",
5272 dreg
, sreg
, (int) BFD_RELOC_LO16
);
5275 load_register (&icnt
, AT
, &imm_expr
, 0);
5276 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, sreg
,
5282 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0,
5285 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0,
5289 macro_build ((char *) NULL
, &icnt
, NULL
, "xor", "d,v,t", dreg
,
5291 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0,
5297 if (imm_expr
.X_add_number
== 0)
5299 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0,
5305 as_warn ("Instruction %s: result is always true",
5307 macro_build ((char *) NULL
, &icnt
, &expr1
,
5308 mips_isa
< 3 ? "addiu" : "daddiu",
5309 "t,r,j", dreg
, 0, (int) BFD_RELOC_LO16
);
5312 if (imm_expr
.X_add_number
>= 0 && imm_expr
.X_add_number
< 0x10000)
5314 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "xori", "t,r,i",
5315 dreg
, sreg
, (int) BFD_RELOC_LO16
);
5318 else if (imm_expr
.X_add_number
> -0x8000 && imm_expr
.X_add_number
< 0)
5320 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
5321 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
5322 mips_isa
< 3 ? "addiu" : "daddiu",
5323 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
5328 load_register (&icnt
, AT
, &imm_expr
, 0);
5329 macro_build ((char *) NULL
, &icnt
, NULL
, "xor", "d,v,t", dreg
,
5333 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0, dreg
);
5341 if (imm_expr
.X_add_number
> -0x8000 && imm_expr
.X_add_number
<= 0x8000)
5343 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
5344 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
5345 dbl
? "daddi" : "addi",
5346 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
5349 load_register (&icnt
, AT
, &imm_expr
, dbl
);
5350 macro_build ((char *) NULL
, &icnt
, NULL
,
5351 dbl
? "dsub" : "sub",
5352 "d,v,t", dreg
, sreg
, AT
);
5358 if (imm_expr
.X_add_number
> -0x8000 && imm_expr
.X_add_number
<= 0x8000)
5360 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
5361 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
5362 dbl
? "daddiu" : "addiu",
5363 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
5366 load_register (&icnt
, AT
, &imm_expr
, dbl
);
5367 macro_build ((char *) NULL
, &icnt
, NULL
,
5368 dbl
? "dsubu" : "subu",
5369 "d,v,t", dreg
, sreg
, AT
);
5390 load_register (&icnt
, AT
, &imm_expr
, 0);
5391 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "s,t", sreg
, AT
);
5396 assert (mips_isa
< 2);
5397 sreg
= (ip
->insn_opcode
>> 11) & 0x1f; /* floating reg */
5398 dreg
= (ip
->insn_opcode
>> 06) & 0x1f; /* floating reg */
5401 * Is the double cfc1 instruction a bug in the mips assembler;
5402 * or is there a reason for it?
5404 mips_emit_delays ();
5406 mips_any_noreorder
= 1;
5407 macro_build ((char *) NULL
, &icnt
, NULL
, "cfc1", "t,G", treg
, 31);
5408 macro_build ((char *) NULL
, &icnt
, NULL
, "cfc1", "t,G", treg
, 31);
5409 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "");
5410 expr1
.X_add_number
= 3;
5411 macro_build ((char *) NULL
, &icnt
, &expr1
, "ori", "t,r,i", AT
, treg
,
5412 (int) BFD_RELOC_LO16
);
5413 expr1
.X_add_number
= 2;
5414 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", AT
, AT
,
5415 (int) BFD_RELOC_LO16
);
5416 macro_build ((char *) NULL
, &icnt
, NULL
, "ctc1", "t,G", AT
, 31);
5417 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "");
5418 macro_build ((char *) NULL
, &icnt
, NULL
,
5419 mask
== M_TRUNCWD
? "cvt.w.d" : "cvt.w.s", "D,S", dreg
, sreg
);
5420 macro_build ((char *) NULL
, &icnt
, NULL
, "ctc1", "t,G", treg
, 31);
5421 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "");
5431 if (offset_expr
.X_add_number
>= 0x7fff)
5432 as_bad ("operand overflow");
5433 /* avoid load delay */
5434 if (byte_order
== LITTLE_ENDIAN
)
5435 offset_expr
.X_add_number
+= 1;
5436 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
5437 (int) BFD_RELOC_LO16
, breg
);
5438 if (byte_order
== LITTLE_ENDIAN
)
5439 offset_expr
.X_add_number
-= 1;
5441 offset_expr
.X_add_number
+= 1;
5442 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lbu", "t,o(b)", AT
,
5443 (int) BFD_RELOC_LO16
, breg
);
5444 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", treg
, treg
, 8);
5445 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", treg
, treg
, AT
);
5458 if (offset_expr
.X_add_number
>= 0x8000 - off
)
5459 as_bad ("operand overflow");
5460 if (byte_order
== LITTLE_ENDIAN
)
5461 offset_expr
.X_add_number
+= off
;
5462 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
5463 (int) BFD_RELOC_LO16
, breg
);
5464 if (byte_order
== LITTLE_ENDIAN
)
5465 offset_expr
.X_add_number
-= off
;
5467 offset_expr
.X_add_number
+= off
;
5468 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s2
, "t,o(b)", treg
,
5469 (int) BFD_RELOC_LO16
, breg
);
5482 load_address (&icnt
, AT
, &offset_expr
);
5484 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5485 mips_isa
< 3 ? "addu" : "daddu",
5486 "d,v,t", AT
, AT
, breg
);
5487 if (byte_order
== LITTLE_ENDIAN
)
5488 expr1
.X_add_number
= off
;
5490 expr1
.X_add_number
= 0;
5491 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, "t,o(b)", treg
,
5492 (int) BFD_RELOC_LO16
, AT
);
5493 if (byte_order
== LITTLE_ENDIAN
)
5494 expr1
.X_add_number
= 0;
5496 expr1
.X_add_number
= off
;
5497 macro_build ((char *) NULL
, &icnt
, &expr1
, s2
, "t,o(b)", treg
,
5498 (int) BFD_RELOC_LO16
, AT
);
5503 load_address (&icnt
, AT
, &offset_expr
);
5505 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5506 mips_isa
< 3 ? "addu" : "daddu",
5507 "d,v,t", AT
, AT
, breg
);
5508 if (byte_order
== BIG_ENDIAN
)
5509 expr1
.X_add_number
= 0;
5510 macro_build ((char *) NULL
, &icnt
, &expr1
,
5511 mask
== M_ULH_A
? "lb" : "lbu", "t,o(b)", treg
,
5512 (int) BFD_RELOC_LO16
, AT
);
5513 if (byte_order
== BIG_ENDIAN
)
5514 expr1
.X_add_number
= 1;
5516 expr1
.X_add_number
= 0;
5517 macro_build ((char *) NULL
, &icnt
, &expr1
, "lbu", "t,o(b)", AT
,
5518 (int) BFD_RELOC_LO16
, AT
);
5519 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", treg
,
5521 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", treg
,
5526 if (offset_expr
.X_add_number
>= 0x7fff)
5527 as_bad ("operand overflow");
5528 if (byte_order
== BIG_ENDIAN
)
5529 offset_expr
.X_add_number
+= 1;
5530 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "sb", "t,o(b)", treg
,
5531 (int) BFD_RELOC_LO16
, breg
);
5532 macro_build ((char *) NULL
, &icnt
, NULL
, "srl", "d,w,<", AT
, treg
, 8);
5533 if (byte_order
== BIG_ENDIAN
)
5534 offset_expr
.X_add_number
-= 1;
5536 offset_expr
.X_add_number
+= 1;
5537 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "sb", "t,o(b)", AT
,
5538 (int) BFD_RELOC_LO16
, breg
);
5551 if (offset_expr
.X_add_number
>= 0x8000 - off
)
5552 as_bad ("operand overflow");
5553 if (byte_order
== LITTLE_ENDIAN
)
5554 offset_expr
.X_add_number
+= off
;
5555 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
5556 (int) BFD_RELOC_LO16
, breg
);
5557 if (byte_order
== LITTLE_ENDIAN
)
5558 offset_expr
.X_add_number
-= off
;
5560 offset_expr
.X_add_number
+= off
;
5561 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s2
, "t,o(b)", treg
,
5562 (int) BFD_RELOC_LO16
, breg
);
5575 load_address (&icnt
, AT
, &offset_expr
);
5577 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5578 mips_isa
< 3 ? "addu" : "daddu",
5579 "d,v,t", AT
, AT
, breg
);
5580 if (byte_order
== LITTLE_ENDIAN
)
5581 expr1
.X_add_number
= off
;
5583 expr1
.X_add_number
= 0;
5584 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, "t,o(b)", treg
,
5585 (int) BFD_RELOC_LO16
, AT
);
5586 if (byte_order
== LITTLE_ENDIAN
)
5587 expr1
.X_add_number
= 0;
5589 expr1
.X_add_number
= off
;
5590 macro_build ((char *) NULL
, &icnt
, &expr1
, s2
, "t,o(b)", treg
,
5591 (int) BFD_RELOC_LO16
, AT
);
5595 load_address (&icnt
, AT
, &offset_expr
);
5597 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5598 mips_isa
< 3 ? "addu" : "daddu",
5599 "d,v,t", AT
, AT
, breg
);
5600 if (byte_order
== LITTLE_ENDIAN
)
5601 expr1
.X_add_number
= 0;
5602 macro_build ((char *) NULL
, &icnt
, &expr1
, "sb", "t,o(b)", treg
,
5603 (int) BFD_RELOC_LO16
, AT
);
5604 macro_build ((char *) NULL
, &icnt
, NULL
, "srl", "d,w,<", treg
,
5606 if (byte_order
== LITTLE_ENDIAN
)
5607 expr1
.X_add_number
= 1;
5609 expr1
.X_add_number
= 0;
5610 macro_build ((char *) NULL
, &icnt
, &expr1
, "sb", "t,o(b)", treg
,
5611 (int) BFD_RELOC_LO16
, AT
);
5612 if (byte_order
== LITTLE_ENDIAN
)
5613 expr1
.X_add_number
= 0;
5615 expr1
.X_add_number
= 1;
5616 macro_build ((char *) NULL
, &icnt
, &expr1
, "lbu", "t,o(b)", AT
,
5617 (int) BFD_RELOC_LO16
, AT
);
5618 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", treg
,
5620 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", treg
,
5625 as_bad ("Macro %s not implemented yet", ip
->insn_mo
->name
);
5629 as_warn ("Macro used $at after \".set noat\"");
5632 /* Implement macros in mips16 mode. */
5636 struct mips_cl_insn
*ip
;
5639 int xreg
, yreg
, zreg
, tmp
;
5643 const char *s
, *s2
, *s3
;
5645 mask
= ip
->insn_mo
->mask
;
5647 xreg
= (ip
->insn_opcode
>> MIPS16OP_SH_RX
) & MIPS16OP_MASK_RX
;
5648 yreg
= (ip
->insn_opcode
>> MIPS16OP_SH_RY
) & MIPS16OP_MASK_RY
;
5649 zreg
= (ip
->insn_opcode
>> MIPS16OP_SH_RZ
) & MIPS16OP_MASK_RZ
;
5653 expr1
.X_op
= O_constant
;
5654 expr1
.X_op_symbol
= NULL
;
5655 expr1
.X_add_symbol
= NULL
;
5656 expr1
.X_add_number
= 1;
5675 mips_emit_delays ();
5677 mips_any_noreorder
= 1;
5678 macro_build ((char *) NULL
, &icnt
, NULL
,
5679 dbl
? "ddiv" : "div",
5680 "0,x,y", xreg
, yreg
);
5681 expr1
.X_add_number
= 4;
5682 macro_build ((char *) NULL
, &icnt
, &expr1
, "bnez", "x,p", yreg
);
5683 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "");
5684 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "6", 7);
5685 /* FIXME: The normal code checks for of -1 / -0x80000000 here,
5686 since that causes an overflow. We should do that as well,
5687 but I don't see how to do the comparisons without a temporary
5690 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "x", zreg
);
5709 mips_emit_delays ();
5711 mips_any_noreorder
= 1;
5712 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "0,x,y", xreg
, yreg
);
5713 expr1
.X_add_number
= 4;
5714 macro_build ((char *) NULL
, &icnt
, &expr1
, "bnez", "x,p", yreg
);
5715 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
5716 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "6", 7);
5718 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "x", zreg
);
5726 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
5727 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
5728 dbl
? "daddiu" : "addiu",
5729 "y,x,4", yreg
, xreg
);
5733 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
5734 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "addiu",
5739 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
5740 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "daddiu",
5763 goto do_reverse_branch
;
5767 goto do_reverse_branch
;
5779 goto do_reverse_branch
;
5790 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s
, "x,y",
5792 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s2
, "p");
5819 goto do_addone_branch_i
;
5824 goto do_addone_branch_i
;
5839 goto do_addone_branch_i
;
5846 ++imm_expr
.X_add_number
;
5849 macro_build ((char *) NULL
, &icnt
, &imm_expr
, s
, s3
, xreg
);
5850 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s2
, "p");
5855 /* This routine assembles an instruction into its binary format. As a
5856 side effect, it sets one of the global variables imm_reloc or
5857 offset_reloc to the type of relocation to do if one of the operands
5858 is an address expression. */
5863 struct mips_cl_insn
*ip
;
5868 struct mips_opcode
*insn
;
5871 unsigned int lastregno
= 0;
5876 for (s
= str
; islower (*s
) || (*s
>= '0' && *s
<= '3') || *s
== '6' || *s
== '.'; ++s
)
5888 as_fatal ("Unknown opcode: `%s'", str
);
5890 if ((insn
= (struct mips_opcode
*) hash_find (op_hash
, str
)) == NULL
)
5892 insn_error
= "unrecognized opcode";
5900 assert (strcmp (insn
->name
, str
) == 0);
5902 if (insn
->pinfo
== INSN_MACRO
)
5903 insn_isa
= insn
->match
;
5904 else if ((insn
->pinfo
& INSN_ISA
) == INSN_ISA2
)
5906 else if ((insn
->pinfo
& INSN_ISA
) == INSN_ISA3
)
5908 else if ((insn
->pinfo
& INSN_ISA
) == INSN_ISA4
)
5913 if (insn_isa
> mips_isa
5914 || ((insn
->pinfo
& INSN_ISA
) == INSN_4650
5916 || ((insn
->pinfo
& INSN_ISA
) == INSN_4010
5918 || ((insn
->pinfo
& INSN_ISA
) == INSN_4100
5921 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
]
5922 && strcmp (insn
->name
, insn
[1].name
) == 0)
5927 if (insn_isa
<= mips_isa
)
5928 insn_error
= "opcode not supported on this processor";
5931 static char buf
[100];
5933 sprintf (buf
, "opcode requires -mips%d or greater", insn_isa
);
5940 ip
->insn_opcode
= insn
->match
;
5941 for (args
= insn
->args
;; ++args
)
5947 case '\0': /* end of args */
5960 ip
->insn_opcode
|= lastregno
<< 21;
5965 ip
->insn_opcode
|= lastregno
<< 16;
5969 ip
->insn_opcode
|= lastregno
<< 11;
5975 /* handle optional base register.
5976 Either the base register is omitted or
5977 we must have a left paren. */
5978 /* this is dependent on the next operand specifier
5979 is a 'b' for base register */
5980 assert (args
[1] == 'b');
5984 case ')': /* these must match exactly */
5989 case '<': /* must be at least one digit */
5991 * According to the manual, if the shift amount is greater
5992 * than 31 or less than 0 the the shift amount should be
5993 * mod 32. In reality the mips assembler issues an error.
5994 * We issue a warning and mask out all but the low 5 bits.
5996 my_getExpression (&imm_expr
, s
);
5997 check_absolute_expr (ip
, &imm_expr
);
5998 if ((unsigned long) imm_expr
.X_add_number
> 31)
6000 as_warn ("Improper shift amount (%ld)",
6001 (long) imm_expr
.X_add_number
);
6002 imm_expr
.X_add_number
= imm_expr
.X_add_number
& 0x1f;
6004 ip
->insn_opcode
|= imm_expr
.X_add_number
<< 6;
6005 imm_expr
.X_op
= O_absent
;
6009 case '>': /* shift amount minus 32 */
6010 my_getExpression (&imm_expr
, s
);
6011 check_absolute_expr (ip
, &imm_expr
);
6012 if ((unsigned long) imm_expr
.X_add_number
< 32
6013 || (unsigned long) imm_expr
.X_add_number
> 63)
6015 ip
->insn_opcode
|= (imm_expr
.X_add_number
- 32) << 6;
6016 imm_expr
.X_op
= O_absent
;
6020 case 'k': /* cache code */
6021 case 'h': /* prefx code */
6022 my_getExpression (&imm_expr
, s
);
6023 check_absolute_expr (ip
, &imm_expr
);
6024 if ((unsigned long) imm_expr
.X_add_number
> 31)
6026 as_warn ("Invalid value for `%s' (%lu)",
6028 (unsigned long) imm_expr
.X_add_number
);
6029 imm_expr
.X_add_number
&= 0x1f;
6032 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_CACHE
;
6034 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_PREFX
;
6035 imm_expr
.X_op
= O_absent
;
6039 case 'c': /* break code */
6040 my_getExpression (&imm_expr
, s
);
6041 check_absolute_expr (ip
, &imm_expr
);
6042 if ((unsigned) imm_expr
.X_add_number
> 1023)
6043 as_warn ("Illegal break code (%ld)",
6044 (long) imm_expr
.X_add_number
);
6045 ip
->insn_opcode
|= imm_expr
.X_add_number
<< 16;
6046 imm_expr
.X_op
= O_absent
;
6050 case 'B': /* syscall code */
6051 my_getExpression (&imm_expr
, s
);
6052 check_absolute_expr (ip
, &imm_expr
);
6053 if ((unsigned) imm_expr
.X_add_number
> 0xfffff)
6054 as_warn ("Illegal syscall code (%ld)",
6055 (long) imm_expr
.X_add_number
);
6056 ip
->insn_opcode
|= imm_expr
.X_add_number
<< 6;
6057 imm_expr
.X_op
= O_absent
;
6061 case 'C': /* Coprocessor code */
6062 my_getExpression (&imm_expr
, s
);
6063 check_absolute_expr (ip
, &imm_expr
);
6064 if ((unsigned long) imm_expr
.X_add_number
>= (1<<25))
6066 as_warn ("Coproccesor code > 25 bits (%ld)",
6067 (long) imm_expr
.X_add_number
);
6068 imm_expr
.X_add_number
&= ((1<<25) - 1);
6070 ip
->insn_opcode
|= imm_expr
.X_add_number
;
6071 imm_expr
.X_op
= O_absent
;
6075 case 'b': /* base register */
6076 case 'd': /* destination register */
6077 case 's': /* source register */
6078 case 't': /* target register */
6079 case 'r': /* both target and source */
6080 case 'v': /* both dest and source */
6081 case 'w': /* both dest and target */
6082 case 'E': /* coprocessor target register */
6083 case 'G': /* coprocessor destination register */
6084 case 'x': /* ignore register name */
6085 case 'z': /* must be zero register */
6099 while (isdigit (*s
));
6101 as_bad ("Invalid register number (%d)", regno
);
6103 else if (*args
== 'E' || *args
== 'G')
6107 if (s
[1] == 'f' && s
[2] == 'p')
6112 else if (s
[1] == 's' && s
[2] == 'p')
6117 else if (s
[1] == 'g' && s
[2] == 'p')
6122 else if (s
[1] == 'a' && s
[2] == 't')
6127 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '0')
6132 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '1')
6144 as_warn ("Used $at without \".set noat\"");
6150 if (c
== 'r' || c
== 'v' || c
== 'w')
6157 /* 'z' only matches $0. */
6158 if (c
== 'z' && regno
!= 0)
6166 ip
->insn_opcode
|= regno
<< 21;
6170 ip
->insn_opcode
|= regno
<< 11;
6175 ip
->insn_opcode
|= regno
<< 16;
6178 /* This case exists because on the r3000 trunc
6179 expands into a macro which requires a gp
6180 register. On the r6000 or r4000 it is
6181 assembled into a single instruction which
6182 ignores the register. Thus the insn version
6183 is MIPS_ISA2 and uses 'x', and the macro
6184 version is MIPS_ISA1 and uses 't'. */
6187 /* This case is for the div instruction, which
6188 acts differently if the destination argument
6189 is $0. This only matches $0, and is checked
6190 outside the switch. */
6201 ip
->insn_opcode
|= lastregno
<< 21;
6204 ip
->insn_opcode
|= lastregno
<< 16;
6209 case 'D': /* floating point destination register */
6210 case 'S': /* floating point source register */
6211 case 'T': /* floating point target register */
6212 case 'R': /* floating point source register */
6216 if (s
[0] == '$' && s
[1] == 'f' && isdigit (s
[2]))
6226 while (isdigit (*s
));
6229 as_bad ("Invalid float register number (%d)", regno
);
6231 if ((regno
& 1) != 0
6233 && ! (strcmp (str
, "mtc1") == 0
6234 || strcmp (str
, "mfc1") == 0
6235 || strcmp (str
, "lwc1") == 0
6236 || strcmp (str
, "swc1") == 0
6237 || strcmp (str
, "l.s") == 0
6238 || strcmp (str
, "s.s") == 0))
6239 as_warn ("Float register should be even, was %d",
6247 if (c
== 'V' || c
== 'W')
6257 ip
->insn_opcode
|= regno
<< 6;
6261 ip
->insn_opcode
|= regno
<< 11;
6265 ip
->insn_opcode
|= regno
<< 16;
6268 ip
->insn_opcode
|= regno
<< 21;
6277 ip
->insn_opcode
|= lastregno
<< 11;
6280 ip
->insn_opcode
|= lastregno
<< 16;
6286 my_getExpression (&imm_expr
, s
);
6287 if (imm_expr
.X_op
!= O_big
6288 && imm_expr
.X_op
!= O_constant
)
6289 insn_error
= "absolute expression required";
6294 my_getExpression (&offset_expr
, s
);
6295 imm_reloc
= BFD_RELOC_32
;
6307 unsigned char temp
[8];
6309 unsigned int length
;
6314 /* These only appear as the last operand in an
6315 instruction, and every instruction that accepts
6316 them in any variant accepts them in all variants.
6317 This means we don't have to worry about backing out
6318 any changes if the instruction does not match.
6320 The difference between them is the size of the
6321 floating point constant and where it goes. For 'F'
6322 and 'L' the constant is 64 bits; for 'f' and 'l' it
6323 is 32 bits. Where the constant is placed is based
6324 on how the MIPS assembler does things:
6327 f -- immediate value
6330 The .lit4 and .lit8 sections are only used if
6331 permitted by the -G argument.
6333 When generating embedded PIC code, we use the
6334 .lit8 section but not the .lit4 section (we can do
6335 .lit4 inline easily; we need to put .lit8
6336 somewhere in the data segment, and using .lit8
6337 permits the linker to eventually combine identical
6340 f64
= *args
== 'F' || *args
== 'L';
6342 save_in
= input_line_pointer
;
6343 input_line_pointer
= s
;
6344 err
= md_atof (f64
? 'd' : 'f', (char *) temp
, &len
);
6346 s
= input_line_pointer
;
6347 input_line_pointer
= save_in
;
6348 if (err
!= NULL
&& *err
!= '\0')
6350 as_bad ("Bad floating point constant: %s", err
);
6351 memset (temp
, '\0', sizeof temp
);
6352 length
= f64
? 8 : 4;
6355 assert (length
== (f64
? 8 : 4));
6359 && (! USE_GLOBAL_POINTER_OPT
6360 || mips_pic
== EMBEDDED_PIC
6361 || g_switch_value
< 4)
6364 imm_expr
.X_op
= O_constant
;
6365 if (byte_order
== LITTLE_ENDIAN
)
6366 imm_expr
.X_add_number
=
6367 (((((((int) temp
[3] << 8)
6372 imm_expr
.X_add_number
=
6373 (((((((int) temp
[0] << 8)
6380 const char *newname
;
6383 /* Switch to the right section. */
6385 subseg
= now_subseg
;
6388 default: /* unused default case avoids warnings. */
6390 newname
= RDATA_SECTION_NAME
;
6391 if (USE_GLOBAL_POINTER_OPT
&& g_switch_value
>= 8)
6395 newname
= RDATA_SECTION_NAME
;
6398 assert (!USE_GLOBAL_POINTER_OPT
6399 || g_switch_value
>= 4);
6403 new_seg
= subseg_new (newname
, (subsegT
) 0);
6404 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
6405 bfd_set_section_flags (stdoutput
, new_seg
,
6410 frag_align (*args
== 'l' ? 2 : 3, 0);
6411 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
6412 record_alignment (new_seg
, 4);
6414 record_alignment (new_seg
, *args
== 'l' ? 2 : 3);
6416 as_bad ("Can't use floating point insn in this section");
6418 /* Set the argument to the current address in the
6420 offset_expr
.X_op
= O_symbol
;
6421 offset_expr
.X_add_symbol
=
6422 symbol_new ("L0\001", now_seg
,
6423 (valueT
) frag_now_fix (), frag_now
);
6424 offset_expr
.X_add_number
= 0;
6426 /* Put the floating point number into the section. */
6427 p
= frag_more ((int) length
);
6428 memcpy (p
, temp
, length
);
6430 /* Switch back to the original section. */
6431 subseg_set (seg
, subseg
);
6436 case 'i': /* 16 bit unsigned immediate */
6437 case 'j': /* 16 bit signed immediate */
6438 imm_reloc
= BFD_RELOC_LO16
;
6439 c
= my_getSmallExpression (&imm_expr
, s
);
6444 if (imm_expr
.X_op
== O_constant
)
6445 imm_expr
.X_add_number
=
6446 (imm_expr
.X_add_number
>> 16) & 0xffff;
6449 imm_reloc
= BFD_RELOC_HI16_S
;
6450 imm_unmatched_hi
= true;
6453 imm_reloc
= BFD_RELOC_HI16
;
6458 if ((c
== '\0' && imm_expr
.X_op
!= O_constant
)
6459 || ((imm_expr
.X_add_number
< 0
6460 || imm_expr
.X_add_number
>= 0x10000)
6461 && imm_expr
.X_op
== O_constant
))
6463 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
6464 !strcmp (insn
->name
, insn
[1].name
))
6466 if (imm_expr
.X_op
!= O_constant
6467 && imm_expr
.X_op
!= O_big
)
6468 insn_error
= "absolute expression required";
6470 as_bad ("16 bit expression not in range 0..65535");
6478 /* The upper bound should be 0x8000, but
6479 unfortunately the MIPS assembler accepts numbers
6480 from 0x8000 to 0xffff and sign extends them, and
6481 we want to be compatible. We only permit this
6482 extended range for an instruction which does not
6483 provide any further alternates, since those
6484 alternates may handle other cases. People should
6485 use the numbers they mean, rather than relying on
6486 a mysterious sign extension. */
6487 more
= (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
6488 strcmp (insn
->name
, insn
[1].name
) == 0);
6493 if ((c
== '\0' && imm_expr
.X_op
!= O_constant
)
6494 || ((imm_expr
.X_add_number
< -0x8000
6495 || imm_expr
.X_add_number
>= max
)
6496 && imm_expr
.X_op
== O_constant
)
6498 && imm_expr
.X_add_number
< 0
6500 && imm_expr
.X_unsigned
6501 && sizeof (imm_expr
.X_add_number
) <= 4))
6505 if (imm_expr
.X_op
!= O_constant
6506 && imm_expr
.X_op
!= O_big
)
6507 insn_error
= "absolute expression required";
6509 as_bad ("16 bit expression not in range -32768..32767");
6515 case 'o': /* 16 bit offset */
6516 c
= my_getSmallExpression (&offset_expr
, s
);
6518 /* If this value won't fit into a 16 bit offset, then go
6519 find a macro that will generate the 32 bit offset
6520 code pattern. As a special hack, we accept the
6521 difference of two local symbols as a constant. This
6522 is required to suppose embedded PIC switches, which
6523 use an instruction which looks like
6524 lw $4,$L12-$LS12($4)
6525 The problem with handling this in a more general
6526 fashion is that the macro function doesn't expect to
6527 see anything which can be handled in a single
6528 constant instruction. */
6530 && (offset_expr
.X_op
!= O_constant
6531 || offset_expr
.X_add_number
>= 0x8000
6532 || offset_expr
.X_add_number
< -0x8000)
6533 && (mips_pic
!= EMBEDDED_PIC
6534 || offset_expr
.X_op
!= O_subtract
6535 || now_seg
!= text_section
6536 || (S_GET_SEGMENT (offset_expr
.X_op_symbol
)
6540 offset_reloc
= BFD_RELOC_LO16
;
6541 if (c
== 'h' || c
== 'H')
6543 assert (offset_expr
.X_op
== O_constant
);
6544 offset_expr
.X_add_number
=
6545 (offset_expr
.X_add_number
>> 16) & 0xffff;
6550 case 'p': /* pc relative offset */
6551 offset_reloc
= BFD_RELOC_16_PCREL_S2
;
6552 my_getExpression (&offset_expr
, s
);
6556 case 'u': /* upper 16 bits */
6557 c
= my_getSmallExpression (&imm_expr
, s
);
6558 if (imm_expr
.X_op
== O_constant
6559 && (imm_expr
.X_add_number
< 0
6560 || imm_expr
.X_add_number
>= 0x10000))
6561 as_bad ("lui expression not in range 0..65535");
6562 imm_reloc
= BFD_RELOC_LO16
;
6567 if (imm_expr
.X_op
== O_constant
)
6568 imm_expr
.X_add_number
=
6569 (imm_expr
.X_add_number
>> 16) & 0xffff;
6572 imm_reloc
= BFD_RELOC_HI16_S
;
6573 imm_unmatched_hi
= true;
6576 imm_reloc
= BFD_RELOC_HI16
;
6582 case 'a': /* 26 bit address */
6583 my_getExpression (&offset_expr
, s
);
6585 offset_reloc
= BFD_RELOC_MIPS_JMP
;
6588 case 'N': /* 3 bit branch condition code */
6589 case 'M': /* 3 bit compare condition code */
6590 if (strncmp (s
, "$fcc", 4) != 0)
6600 while (isdigit (*s
));
6602 as_bad ("invalid condition code register $fcc%d", regno
);
6604 ip
->insn_opcode
|= regno
<< OP_SH_BCC
;
6606 ip
->insn_opcode
|= regno
<< OP_SH_CCC
;
6610 fprintf (stderr
, "bad char = '%c'\n", *args
);
6615 /* Args don't match. */
6616 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
6617 !strcmp (insn
->name
, insn
[1].name
))
6623 insn_error
= "illegal operands";
6628 /* This routine assembles an instruction into its binary format when
6629 assembling for the mips16. As a side effect, it sets one of the
6630 global variables imm_reloc or offset_reloc to the type of
6631 relocation to do if one of the operands is an address expression. */
6636 struct mips_cl_insn
*ip
;
6641 struct mips_opcode
*insn
;
6644 unsigned int lastregno
= 0;
6652 for (s
= str
; islower (*s
); ++s
)
6664 if (s
[1] == 't' && s
[2] == ' ')
6671 else if (s
[1] == 'e' && s
[2] == ' ')
6680 insn_error
= "unknown opcode";
6684 if ((insn
= (struct mips_opcode
*) hash_find (mips16_op_hash
, str
)) == NULL
)
6686 insn_error
= "unrecognized opcode";
6693 assert (strcmp (insn
->name
, str
) == 0);
6696 ip
->insn_opcode
= insn
->match
;
6697 ip
->use_extend
= false;
6698 imm_expr
.X_op
= O_absent
;
6699 imm_reloc
= BFD_RELOC_UNUSED
;
6700 offset_expr
.X_op
= O_absent
;
6701 offset_reloc
= BFD_RELOC_UNUSED
;
6702 for (args
= insn
->args
; 1; ++args
)
6709 /* In this switch statement we call break if we did not find
6710 a match, continue if we did find a match, or return if we
6719 /* Stuff the immediate value in now, if we can. */
6720 if (imm_expr
.X_op
== O_constant
6721 && imm_reloc
> BFD_RELOC_UNUSED
6722 && insn
->pinfo
!= INSN_MACRO
)
6724 mips16_immed (imm_reloc
- BFD_RELOC_UNUSED
,
6725 imm_expr
.X_add_number
, true, small
, ext
,
6726 &ip
->insn_opcode
, &ip
->use_extend
,
6728 imm_expr
.X_op
= O_absent
;
6729 imm_reloc
= BFD_RELOC_UNUSED
;
6743 ip
->insn_opcode
|= lastregno
<< MIPS16OP_SH_RX
;
6746 ip
->insn_opcode
|= lastregno
<< MIPS16OP_SH_RY
;
6762 ip
->insn_opcode
|= lastregno
<< MIPS16OP_SH_RX
;
6764 ip
->insn_opcode
|= lastregno
<< MIPS16OP_SH_RY
;
6791 while (isdigit (*s
));
6794 as_bad ("invalid register number (%d)", regno
);
6800 if (s
[1] == 'f' && s
[2] == 'p')
6805 else if (s
[1] == 's' && s
[2] == 'p')
6810 else if (s
[1] == 'g' && s
[2] == 'p')
6815 else if (s
[1] == 'a' && s
[2] == 't')
6820 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '0')
6825 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '1')
6838 if (c
== 'v' || c
== 'w')
6840 regno
= mips16_to_32_reg_map
[lastregno
];
6854 regno
= mips32_to_16_reg_map
[regno
];
6859 regno
= ILLEGAL_REG
;
6864 regno
= ILLEGAL_REG
;
6869 regno
= ILLEGAL_REG
;
6874 if (regno
== AT
&& ! mips_noat
)
6875 as_warn ("used $at without \".set noat\"");
6882 if (regno
== ILLEGAL_REG
)
6889 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_RX
;
6893 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_RY
;
6896 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_RZ
;
6899 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_MOVE32Z
;
6905 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_REGR32
;
6908 regno
= ((regno
& 7) << 2) | ((regno
& 0x18) >> 3);
6909 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_REG32R
;
6919 if (strncmp (s
, "$pc", 3) == 0)
6942 if (s
[0] == '$' && isdigit (s
[1]))
6944 /* Looks like a register name. */
6947 my_getExpression (&imm_expr
, s
);
6948 /* We need to relax this instruction. */
6949 imm_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
6958 /* We use offset_reloc rather than imm_reloc for the PC
6959 relative operands. This lets macros with both
6960 immediate and address operands work correctly. */
6961 if (s
[0] == '$' && isdigit (s
[1]))
6963 /* Looks like a register name. */
6966 my_getExpression (&offset_expr
, s
);
6967 /* We need to relax this instruction. */
6968 offset_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
6972 case '6': /* break code */
6973 my_getExpression (&imm_expr
, s
);
6974 check_absolute_expr (ip
, &imm_expr
);
6975 if ((unsigned long) imm_expr
.X_add_number
> 63)
6977 as_warn ("Invalid value for `%s' (%lu)",
6979 (unsigned long) imm_expr
.X_add_number
);
6980 imm_expr
.X_add_number
&= 0x3f;
6982 ip
->insn_opcode
|= imm_expr
.X_add_number
<< MIPS16OP_SH_IMM6
;
6983 imm_expr
.X_op
= O_absent
;
6987 case 'a': /* 26 bit address */
6988 my_getExpression (&offset_expr
, s
);
6990 offset_reloc
= BFD_RELOC_MIPS16_JMP
;
6991 ip
->insn_opcode
<<= 16;
6994 case 'l': /* register list for entry macro */
6995 case 'L': /* register list for exit macro */
7007 while (*s
== ' ' || *s
== ',')
7011 as_bad ("can't parse register list");
7016 while (isdigit (*s
))
7033 while (isdigit (*s
))
7040 if (reg1
== 4 && reg2
>= 4 && reg2
<= 7 && c
!= 'L')
7041 mask
|= (reg2
- 3) << 3;
7042 else if (reg1
== 16 && reg2
>= 16 && reg2
<= 17)
7043 mask
|= (reg2
- 15) << 1;
7044 else if (reg1
== 31 && reg2
== 31)
7047 as_bad ("invalid register list");
7049 ip
->insn_opcode
|= mask
<< MIPS16OP_SH_IMM6
;
7059 /* Args don't match. */
7060 if (insn
+ 1 < &mips16_opcodes
[bfd_mips16_num_opcodes
] &&
7061 strcmp (insn
->name
, insn
[1].name
) == 0)
7068 insn_error
= "illegal operands";
7074 /* This structure holds information we know about a mips16 immediate
7077 struct mips16_immed_operand
7079 /* The type code used in the argument string in the opcode table. */
7081 /* The number of bits in the short form of the opcode. */
7083 /* The number of bits in the extended form of the opcode. */
7085 /* The amount by which the short form is shifted when it is used;
7086 for example, the sw instruction has a shift count of 2. */
7088 /* The amount by which the short form is shifted when it is stored
7089 into the instruction code. */
7091 /* Non-zero if the short form is unsigned. */
7093 /* Non-zero if the extended form is unsigned. */
7095 /* Non-zero if the value is PC relative. */
7099 /* The mips16 immediate operand types. */
7101 static const struct mips16_immed_operand mips16_immed_operands
[] =
7103 { '<', 3, 5, 0, MIPS16OP_SH_RZ
, 1, 1, 0 },
7104 { '>', 3, 5, 0, MIPS16OP_SH_RX
, 1, 1, 0 },
7105 { '[', 3, 6, 0, MIPS16OP_SH_RZ
, 1, 1, 0 },
7106 { ']', 3, 6, 0, MIPS16OP_SH_RX
, 1, 1, 0 },
7107 { '4', 4, 15, 0, MIPS16OP_SH_IMM4
, 0, 0, 0 },
7108 { '5', 5, 16, 0, MIPS16OP_SH_IMM5
, 1, 0, 0 },
7109 { 'H', 5, 16, 1, MIPS16OP_SH_IMM5
, 1, 0, 0 },
7110 { 'W', 5, 16, 2, MIPS16OP_SH_IMM5
, 1, 0, 0 },
7111 { 'D', 5, 16, 3, MIPS16OP_SH_IMM5
, 1, 0, 0 },
7112 { 'j', 5, 16, 0, MIPS16OP_SH_IMM5
, 0, 0, 0 },
7113 { '8', 8, 16, 0, MIPS16OP_SH_IMM8
, 1, 0, 0 },
7114 { 'V', 8, 16, 2, MIPS16OP_SH_IMM8
, 1, 0, 0 },
7115 { 'C', 8, 16, 3, MIPS16OP_SH_IMM8
, 1, 0, 0 },
7116 { 'U', 8, 16, 0, MIPS16OP_SH_IMM8
, 1, 1, 0 },
7117 { 'k', 8, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 0 },
7118 { 'K', 8, 16, 3, MIPS16OP_SH_IMM8
, 0, 0, 0 },
7119 { 'p', 8, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 1 },
7120 { 'q', 11, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 1 },
7121 { 'A', 8, 16, 2, MIPS16OP_SH_IMM8
, 1, 0, 1 },
7122 { 'B', 5, 16, 3, MIPS16OP_SH_IMM5
, 1, 0, 1 },
7123 { 'E', 5, 16, 2, MIPS16OP_SH_IMM5
, 1, 0, 1 }
7126 #define MIPS16_NUM_IMMED \
7127 (sizeof mips16_immed_operands / sizeof mips16_immed_operands[0])
7129 /* Handle a mips16 instruction with an immediate value. This or's the
7130 small immediate value into *INSN. It sets *USE_EXTEND to indicate
7131 whether an extended value is needed; if one is needed, it sets
7132 *EXTEND to the value. The argument type is TYPE. The value is VAL.
7133 If SMALL is true, an unextended opcode was explicitly requested.
7134 If EXT is true, an extended opcode was explicitly requested. If
7135 WARN is true, warn if EXT does not match reality. */
7138 mips16_immed (type
, val
, warn
, small
, ext
, insn
, use_extend
, extend
)
7144 unsigned long *insn
;
7145 boolean
*use_extend
;
7146 unsigned short *extend
;
7148 register const struct mips16_immed_operand
*op
;
7149 int mintiny
, maxtiny
;
7152 op
= mips16_immed_operands
;
7153 while (op
->type
!= type
)
7156 assert (op
< mips16_immed_operands
+ MIPS16_NUM_IMMED
);
7161 if (type
== '<' || type
== '>' || type
== '[' || type
== ']')
7164 maxtiny
= 1 << op
->nbits
;
7169 maxtiny
= (1 << op
->nbits
) - 1;
7174 mintiny
= - (1 << (op
->nbits
- 1));
7175 maxtiny
= (1 << (op
->nbits
- 1)) - 1;
7178 /* Branch offsets have an implicit 0 in the lowest bit. */
7179 if (type
== 'p' || type
== 'q')
7182 as_bad ("branch to odd address");
7186 if ((val
& ((1 << op
->shift
) - 1)) != 0
7187 || val
< (mintiny
<< op
->shift
)
7188 || val
> (maxtiny
<< op
->shift
))
7193 if (warn
&& ext
&& ! needext
)
7194 as_warn ("extended operand requested but not required");
7195 if ((small
|| ! mips16_autoextend
) && needext
)
7196 as_bad ("invalid unextended operand value");
7198 if (small
|| (! ext
&& ! needext
))
7202 *use_extend
= false;
7203 insnval
= ((val
>> op
->shift
) & ((1 << op
->nbits
) - 1));
7204 insnval
<<= op
->op_shift
;
7209 long minext
, maxext
;
7215 maxext
= (1 << op
->extbits
) - 1;
7219 minext
= - (1 << (op
->extbits
- 1));
7220 maxext
= (1 << (op
->extbits
- 1)) - 1;
7222 if (val
< minext
|| val
> maxext
)
7223 as_bad ("operand value out of range for instruction");
7226 if (op
->extbits
== 16)
7228 extval
= ((val
>> 11) & 0x1f) | (val
& 0x7e0);
7231 else if (op
->extbits
== 15)
7233 extval
= ((val
>> 11) & 0xf) | (val
& 0x7f0);
7238 extval
= ((val
& 0x1f) << 6) | (val
& 0x20);
7242 *extend
= (unsigned short) extval
;
7251 my_getSmallExpression (ep
, str
)
7262 ((str
[1] == 'h' && str
[2] == 'i')
7263 || (str
[1] == 'H' && str
[2] == 'I')
7264 || (str
[1] == 'l' && str
[2] == 'o'))
7276 * A small expression may be followed by a base register.
7277 * Scan to the end of this operand, and then back over a possible
7278 * base register. Then scan the small expression up to that
7279 * point. (Based on code in sparc.c...)
7281 for (sp
= str
; *sp
&& *sp
!= ','; sp
++)
7283 if (sp
- 4 >= str
&& sp
[-1] == RP
)
7285 if (isdigit (sp
[-2]))
7287 for (sp
-= 3; sp
>= str
&& isdigit (*sp
); sp
--)
7289 if (*sp
== '$' && sp
> str
&& sp
[-1] == LP
)
7295 else if (sp
- 5 >= str
7298 && ((sp
[-3] == 'f' && sp
[-2] == 'p')
7299 || (sp
[-3] == 's' && sp
[-2] == 'p')
7300 || (sp
[-3] == 'g' && sp
[-2] == 'p')
7301 || (sp
[-3] == 'a' && sp
[-2] == 't')))
7307 /* no expression means zero offset */
7310 /* %xx(reg) is an error */
7311 ep
->X_op
= O_absent
;
7316 ep
->X_op
= O_constant
;
7319 ep
->X_add_symbol
= NULL
;
7320 ep
->X_op_symbol
= NULL
;
7321 ep
->X_add_number
= 0;
7326 my_getExpression (ep
, str
);
7333 my_getExpression (ep
, str
);
7334 return c
; /* => %hi or %lo encountered */
7338 my_getExpression (ep
, str
)
7344 save_in
= input_line_pointer
;
7345 input_line_pointer
= str
;
7347 expr_end
= input_line_pointer
;
7348 input_line_pointer
= save_in
;
7351 /* Turn a string in input_line_pointer into a floating point constant
7352 of type type, and store the appropriate bytes in *litP. The number
7353 of LITTLENUMS emitted is stored in *sizeP . An error message is
7354 returned, or NULL on OK. */
7357 md_atof (type
, litP
, sizeP
)
7363 LITTLENUM_TYPE words
[4];
7379 return "bad call to md_atof";
7382 t
= atof_ieee (input_line_pointer
, type
, words
);
7384 input_line_pointer
= t
;
7388 if (byte_order
== LITTLE_ENDIAN
)
7390 for (i
= prec
- 1; i
>= 0; i
--)
7392 md_number_to_chars (litP
, (valueT
) words
[i
], 2);
7398 for (i
= 0; i
< prec
; i
++)
7400 md_number_to_chars (litP
, (valueT
) words
[i
], 2);
7409 md_number_to_chars (buf
, val
, n
)
7417 number_to_chars_littleendian (buf
, val
, n
);
7421 number_to_chars_bigendian (buf
, val
, n
);
7429 CONST
char *md_shortopts
= "O::g::G:";
7431 struct option md_longopts
[] = {
7432 #define OPTION_MIPS1 (OPTION_MD_BASE + 1)
7433 {"mips0", no_argument
, NULL
, OPTION_MIPS1
},
7434 {"mips1", no_argument
, NULL
, OPTION_MIPS1
},
7435 #define OPTION_MIPS2 (OPTION_MD_BASE + 2)
7436 {"mips2", no_argument
, NULL
, OPTION_MIPS2
},
7437 #define OPTION_MIPS3 (OPTION_MD_BASE + 3)
7438 {"mips3", no_argument
, NULL
, OPTION_MIPS3
},
7439 #define OPTION_MIPS4 (OPTION_MD_BASE + 4)
7440 {"mips4", no_argument
, NULL
, OPTION_MIPS4
},
7441 #define OPTION_MCPU (OPTION_MD_BASE + 5)
7442 {"mcpu", required_argument
, NULL
, OPTION_MCPU
},
7443 #define OPTION_MEMBEDDED_PIC (OPTION_MD_BASE + 6)
7444 {"membedded-pic", no_argument
, NULL
, OPTION_MEMBEDDED_PIC
},
7445 #define OPTION_TRAP (OPTION_MD_BASE + 9)
7446 {"trap", no_argument
, NULL
, OPTION_TRAP
},
7447 {"no-break", no_argument
, NULL
, OPTION_TRAP
},
7448 #define OPTION_BREAK (OPTION_MD_BASE + 10)
7449 {"break", no_argument
, NULL
, OPTION_BREAK
},
7450 {"no-trap", no_argument
, NULL
, OPTION_BREAK
},
7451 #define OPTION_EB (OPTION_MD_BASE + 11)
7452 {"EB", no_argument
, NULL
, OPTION_EB
},
7453 #define OPTION_EL (OPTION_MD_BASE + 12)
7454 {"EL", no_argument
, NULL
, OPTION_EL
},
7455 #define OPTION_M4650 (OPTION_MD_BASE + 13)
7456 {"m4650", no_argument
, NULL
, OPTION_M4650
},
7457 #define OPTION_NO_M4650 (OPTION_MD_BASE + 14)
7458 {"no-m4650", no_argument
, NULL
, OPTION_NO_M4650
},
7459 #define OPTION_M4010 (OPTION_MD_BASE + 15)
7460 {"m4010", no_argument
, NULL
, OPTION_M4010
},
7461 #define OPTION_NO_M4010 (OPTION_MD_BASE + 16)
7462 {"no-m4010", no_argument
, NULL
, OPTION_NO_M4010
},
7463 #define OPTION_M4100 (OPTION_MD_BASE + 17)
7464 {"m4100", no_argument
, NULL
, OPTION_M4100
},
7465 #define OPTION_NO_M4100 (OPTION_MD_BASE + 18)
7466 {"no-m4100", no_argument
, NULL
, OPTION_NO_M4100
},
7467 #define OPTION_MIPS16 (OPTION_MD_BASE + 22)
7468 {"mips16", no_argument
, NULL
, OPTION_MIPS16
},
7469 #define OPTION_NO_MIPS16 (OPTION_MD_BASE + 23)
7470 {"no-mips16", no_argument
, NULL
, OPTION_NO_MIPS16
},
7472 #define OPTION_CALL_SHARED (OPTION_MD_BASE + 7)
7473 #define OPTION_NON_SHARED (OPTION_MD_BASE + 8)
7474 #define OPTION_XGOT (OPTION_MD_BASE + 19)
7475 #define OPTION_32 (OPTION_MD_BASE + 20)
7476 #define OPTION_64 (OPTION_MD_BASE + 21)
7478 {"KPIC", no_argument
, NULL
, OPTION_CALL_SHARED
},
7479 {"xgot", no_argument
, NULL
, OPTION_XGOT
},
7480 {"call_shared", no_argument
, NULL
, OPTION_CALL_SHARED
},
7481 {"non_shared", no_argument
, NULL
, OPTION_NON_SHARED
},
7482 {"32", no_argument
, NULL
, OPTION_32
},
7483 {"64", no_argument
, NULL
, OPTION_64
},
7486 {NULL
, no_argument
, NULL
, 0}
7488 size_t md_longopts_size
= sizeof(md_longopts
);
7491 md_parse_option (c
, arg
)
7506 target_big_endian
= 1;
7510 target_big_endian
= 0;
7514 if (arg
&& arg
[1] == '0')
7524 mips_debug
= atoi (arg
);
7525 /* When the MIPS assembler sees -g or -g2, it does not do
7526 optimizations which limit full symbolic debugging. We take
7527 that to be equivalent to -O0. */
7528 if (mips_debug
== 2)
7560 /* Identify the processor type */
7562 if (strcmp (p
, "default") == 0
7563 || strcmp (p
, "DEFAULT") == 0)
7569 /* We need to cope with the various "vr" prefixes for the 4300
7571 if (*p
== 'v' || *p
== 'V')
7577 if (*p
== 'r' || *p
== 'R')
7584 if (strcmp (p
, "10000") == 0
7585 || strcmp (p
, "10k") == 0
7586 || strcmp (p
, "10K") == 0)
7591 if (strcmp (p
, "2000") == 0
7592 || strcmp (p
, "2k") == 0
7593 || strcmp (p
, "2K") == 0)
7598 if (strcmp (p
, "3000") == 0
7599 || strcmp (p
, "3k") == 0
7600 || strcmp (p
, "3K") == 0)
7605 if (strcmp (p
, "4000") == 0
7606 || strcmp (p
, "4k") == 0
7607 || strcmp (p
, "4K") == 0)
7609 else if (strcmp (p
, "4100") == 0)
7615 else if (strcmp (p
, "4300") == 0)
7617 else if (strcmp (p
, "4400") == 0)
7619 else if (strcmp (p
, "4600") == 0)
7621 else if (strcmp (p
, "4650") == 0)
7627 else if (strcmp (p
, "4010") == 0)
7636 if (strcmp (p
, "5000") == 0
7637 || strcmp (p
, "5k") == 0
7638 || strcmp (p
, "5K") == 0)
7643 if (strcmp (p
, "6000") == 0
7644 || strcmp (p
, "6k") == 0
7645 || strcmp (p
, "6K") == 0)
7650 if (strcmp (p
, "8000") == 0
7651 || strcmp (p
, "8k") == 0
7652 || strcmp (p
, "8K") == 0)
7657 if (strcmp (p
, "orion") == 0)
7662 if (sv
&& mips_cpu
!= 4300 && mips_cpu
!= 4100 && mips_cpu
!= 5000)
7664 as_bad ("ignoring invalid leading 'v' in -mcpu=%s switch", arg
);
7670 as_bad ("invalid architecture -mcpu=%s", arg
);
7681 case OPTION_NO_M4650
:
7689 case OPTION_NO_M4010
:
7697 case OPTION_NO_M4100
:
7703 mips_no_prev_insn ();
7706 case OPTION_NO_MIPS16
:
7708 mips_no_prev_insn ();
7711 case OPTION_MEMBEDDED_PIC
:
7712 mips_pic
= EMBEDDED_PIC
;
7713 if (USE_GLOBAL_POINTER_OPT
&& g_switch_seen
)
7715 as_bad ("-G may not be used with embedded PIC code");
7718 g_switch_value
= 0x7fffffff;
7721 /* When generating ELF code, we permit -KPIC and -call_shared to
7722 select SVR4_PIC, and -non_shared to select no PIC. This is
7723 intended to be compatible with Irix 5. */
7724 case OPTION_CALL_SHARED
:
7725 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
7727 as_bad ("-call_shared is supported only for ELF format");
7730 mips_pic
= SVR4_PIC
;
7731 if (g_switch_seen
&& g_switch_value
!= 0)
7733 as_bad ("-G may not be used with SVR4 PIC code");
7739 case OPTION_NON_SHARED
:
7740 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
7742 as_bad ("-non_shared is supported only for ELF format");
7748 /* The -xgot option tells the assembler to use 32 offsets when
7749 accessing the got in SVR4_PIC mode. It is for Irix
7756 if (! USE_GLOBAL_POINTER_OPT
)
7758 as_bad ("-G is not supported for this configuration");
7761 else if (mips_pic
== SVR4_PIC
|| mips_pic
== EMBEDDED_PIC
)
7763 as_bad ("-G may not be used with SVR4 or embedded PIC code");
7767 g_switch_value
= atoi (arg
);
7771 /* The -32 and -64 options tell the assembler to output the 32
7772 bit or the 64 bit MIPS ELF format. */
7779 const char **list
, **l
;
7781 list
= bfd_target_list ();
7782 for (l
= list
; *l
!= NULL
; l
++)
7783 if (strcmp (*l
, "elf64-bigmips") == 0
7784 || strcmp (*l
, "elf64-littlemips") == 0)
7787 as_fatal ("No compiled in support for 64 bit object file format");
7801 md_show_usage (stream
)
7806 -membedded-pic generate embedded position independent code\n\
7807 -EB generate big endian output\n\
7808 -EL generate little endian output\n\
7809 -g, -g2 do not remove uneeded NOPs or swap branches\n\
7810 -G NUM allow referencing objects up to NUM bytes\n\
7811 implicitly with the gp register [default 8]\n");
7813 -mips1, -mcpu=r{2,3}000 generate code for r2000 and r3000\n\
7814 -mips2, -mcpu=r6000 generate code for r6000\n\
7815 -mips3, -mcpu=r4000 generate code for r4000\n\
7816 -mips4, -mcpu=r8000 generate code for r8000\n\
7817 -mcpu=vr4300 generate code for vr4300\n\
7818 -mcpu=vr4100 generate code for vr4100\n\
7819 -m4650 permit R4650 instructions\n\
7820 -no-m4650 do not permit R4650 instructions\n\
7821 -m4010 permit R4010 instructions\n\
7822 -no-m4010 do not permit R4010 instructions\n\
7823 -m4100 permit VR4100 instructions\n\
7824 -no-m4100 do not permit VR4100 instructions\n");
7826 -mips16 generate mips16 instructions\n\
7827 -no-mips16 do not generate mips16 instructions\n");
7829 -O0 remove unneeded NOPs, do not swap branches\n\
7830 -O remove unneeded NOPs and swap branches\n\
7831 --trap, --no-break trap exception on div by 0 and mult overflow\n\
7832 --break, --no-trap break exception on div by 0 and mult overflow\n");
7835 -KPIC, -call_shared generate SVR4 position independent code\n\
7836 -non_shared do not generate position independent code\n\
7837 -xgot assume a 32 bit GOT\n\
7838 -32 create 32 bit object file (default)\n\
7839 -64 create 64 bit object file\n");
7844 mips_init_after_args ()
7846 if (target_big_endian
)
7847 byte_order
= BIG_ENDIAN
;
7849 byte_order
= LITTLE_ENDIAN
;
7853 md_pcrel_from (fixP
)
7856 if (OUTPUT_FLAVOR
!= bfd_target_aout_flavour
7857 && fixP
->fx_addsy
!= (symbolS
*) NULL
7858 && ! S_IS_DEFINED (fixP
->fx_addsy
))
7860 /* This makes a branch to an undefined symbol be a branch to the
7861 current location. */
7865 /* return the address of the delay slot */
7866 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
7869 /* This is called by emit_expr via TC_CONS_FIX_NEW when creating a
7870 reloc for a cons. We could use the definition there, except that
7871 we want to handle 64 bit relocs specially. */
7874 cons_fix_new_mips (frag
, where
, nbytes
, exp
)
7877 unsigned int nbytes
;
7881 /* If we are assembling in 32 bit mode, turn an 8 byte reloc into a
7883 if (nbytes
== 8 && ! mips_64
)
7885 if (byte_order
== BIG_ENDIAN
)
7891 if (nbytes
!= 2 && nbytes
!= 4 && nbytes
!= 8)
7892 as_bad ("Unsupported reloc size %d", nbytes
);
7894 fix_new_exp (frag_now
, where
, (int) nbytes
, exp
, 0,
7897 : (nbytes
== 4 ? BFD_RELOC_32
: BFD_RELOC_64
)));
7900 /* Sort any unmatched HI16_S relocs so that they immediately precede
7901 the corresponding LO reloc. This is called before md_apply_fix and
7902 tc_gen_reloc. Unmatched HI16_S relocs can only be generated by
7903 explicit use of the %hi modifier. */
7908 struct mips_hi_fixup
*l
;
7910 for (l
= mips_hi_fixup_list
; l
!= NULL
; l
= l
->next
)
7912 segment_info_type
*seginfo
;
7915 assert (l
->fixp
->fx_r_type
== BFD_RELOC_HI16_S
);
7917 /* Check quickly whether the next fixup happens to be a matching
7919 if (l
->fixp
->fx_next
!= NULL
7920 && l
->fixp
->fx_next
->fx_r_type
== BFD_RELOC_LO16
7921 && l
->fixp
->fx_addsy
== l
->fixp
->fx_next
->fx_addsy
7922 && l
->fixp
->fx_offset
== l
->fixp
->fx_next
->fx_offset
)
7925 /* Look through the fixups for this segment for a matching %lo.
7926 When we find one, move the %hi just in front of it. We do
7927 this in two passes. In the first pass, we try to find a
7928 unique %lo. In the second pass, we permit multiple %hi
7929 relocs for a single %lo (this is a GNU extension). */
7930 seginfo
= seg_info (l
->seg
);
7931 for (pass
= 0; pass
< 2; pass
++)
7936 for (f
= seginfo
->fix_root
; f
!= NULL
; f
= f
->fx_next
)
7938 /* Check whether this is a %lo fixup which matches l->fixp. */
7939 if (f
->fx_r_type
== BFD_RELOC_LO16
7940 && f
->fx_addsy
== l
->fixp
->fx_addsy
7941 && f
->fx_offset
== l
->fixp
->fx_offset
7944 || prev
->fx_r_type
!= BFD_RELOC_HI16_S
7945 || prev
->fx_addsy
!= f
->fx_addsy
7946 || prev
->fx_offset
!= f
->fx_offset
))
7950 /* Move l->fixp before f. */
7951 for (pf
= &seginfo
->fix_root
;
7953 pf
= &(*pf
)->fx_next
)
7954 assert (*pf
!= NULL
);
7956 *pf
= l
->fixp
->fx_next
;
7958 l
->fixp
->fx_next
= f
;
7960 seginfo
->fix_root
= l
->fixp
;
7962 prev
->fx_next
= l
->fixp
;
7974 as_warn_where (l
->fixp
->fx_file
, l
->fixp
->fx_line
,
7975 "Unmatched %%hi reloc");
7980 /* When generating embedded PIC code we need to use a special
7981 relocation to represent the difference of two symbols in the .text
7982 section (switch tables use a difference of this sort). See
7983 include/coff/mips.h for details. This macro checks whether this
7984 fixup requires the special reloc. */
7985 #define SWITCH_TABLE(fixp) \
7986 ((fixp)->fx_r_type == BFD_RELOC_32 \
7987 && (fixp)->fx_addsy != NULL \
7988 && (fixp)->fx_subsy != NULL \
7989 && S_GET_SEGMENT ((fixp)->fx_addsy) == text_section \
7990 && S_GET_SEGMENT ((fixp)->fx_subsy) == text_section)
7992 /* When generating embedded PIC code we must keep all PC relative
7993 relocations, in case the linker has to relax a call. We also need
7994 to keep relocations for switch table entries. */
7998 mips_force_relocation (fixp
)
8001 return (mips_pic
== EMBEDDED_PIC
8003 || SWITCH_TABLE (fixp
)
8004 || fixp
->fx_r_type
== BFD_RELOC_PCREL_HI16_S
8005 || fixp
->fx_r_type
== BFD_RELOC_PCREL_LO16
));
8008 /* Apply a fixup to the object file. */
8011 md_apply_fix (fixP
, valueP
)
8018 assert (fixP
->fx_size
== 4
8019 || fixP
->fx_r_type
== BFD_RELOC_16
8020 || fixP
->fx_r_type
== BFD_RELOC_64
);
8023 fixP
->fx_addnumber
= value
; /* Remember value for tc_gen_reloc */
8025 if (fixP
->fx_addsy
== NULL
&& ! fixP
->fx_pcrel
)
8028 switch (fixP
->fx_r_type
)
8030 case BFD_RELOC_MIPS_JMP
:
8031 case BFD_RELOC_HI16
:
8032 case BFD_RELOC_HI16_S
:
8033 case BFD_RELOC_MIPS_GPREL
:
8034 case BFD_RELOC_MIPS_LITERAL
:
8035 case BFD_RELOC_MIPS_CALL16
:
8036 case BFD_RELOC_MIPS_GOT16
:
8037 case BFD_RELOC_MIPS_GPREL32
:
8038 case BFD_RELOC_MIPS_GOT_HI16
:
8039 case BFD_RELOC_MIPS_GOT_LO16
:
8040 case BFD_RELOC_MIPS_CALL_HI16
:
8041 case BFD_RELOC_MIPS_CALL_LO16
:
8043 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
8044 "Invalid PC relative reloc");
8045 /* Nothing needed to do. The value comes from the reloc entry */
8048 case BFD_RELOC_MIPS16_JMP
:
8049 /* We currently always generate a reloc against a symbol, which
8050 means that we don't want an addend even if the symbol is
8052 fixP
->fx_addnumber
= 0;
8055 case BFD_RELOC_PCREL_HI16_S
:
8056 /* The addend for this is tricky if it is internal, so we just
8057 do everything here rather than in bfd_perform_relocation. */
8058 if ((fixP
->fx_addsy
->bsym
->flags
& BSF_SECTION_SYM
) == 0)
8060 /* For an external symbol adjust by the address to make it
8061 pcrel_offset. We use the address of the RELLO reloc
8062 which follows this one. */
8063 value
+= (fixP
->fx_next
->fx_frag
->fr_address
8064 + fixP
->fx_next
->fx_where
);
8069 buf
= (unsigned char *) fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
8070 if (byte_order
== BIG_ENDIAN
)
8072 md_number_to_chars (buf
, value
, 2);
8075 case BFD_RELOC_PCREL_LO16
:
8076 /* The addend for this is tricky if it is internal, so we just
8077 do everything here rather than in bfd_perform_relocation. */
8078 if ((fixP
->fx_addsy
->bsym
->flags
& BSF_SECTION_SYM
) == 0)
8079 value
+= fixP
->fx_frag
->fr_address
+ fixP
->fx_where
;
8080 buf
= (unsigned char *) fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
8081 if (byte_order
== BIG_ENDIAN
)
8083 md_number_to_chars (buf
, value
, 2);
8087 /* This is handled like BFD_RELOC_32, but we output a sign
8088 extended value if we are only 32 bits. */
8090 || (mips_pic
== EMBEDDED_PIC
&& SWITCH_TABLE (fixP
)))
8092 if (8 <= sizeof (valueT
))
8093 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
,
8100 w1
= w2
= fixP
->fx_where
;
8101 if (byte_order
== BIG_ENDIAN
)
8105 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ w1
, value
, 4);
8106 if ((value
& 0x80000000) != 0)
8110 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ w2
, hiv
, 4);
8116 /* If we are deleting this reloc entry, we must fill in the
8117 value now. This can happen if we have a .word which is not
8118 resolved when it appears but is later defined. We also need
8119 to fill in the value if this is an embedded PIC switch table
8122 || (mips_pic
== EMBEDDED_PIC
&& SWITCH_TABLE (fixP
)))
8123 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
,
8128 /* If we are deleting this reloc entry, we must fill in the
8130 assert (fixP
->fx_size
== 2);
8132 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
,
8136 case BFD_RELOC_LO16
:
8137 /* When handling an embedded PIC switch statement, we can wind
8138 up deleting a LO16 reloc. See the 'o' case in mips_ip. */
8141 if (value
< -0x8000 || value
> 0x7fff)
8142 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
8143 "relocation overflow");
8144 buf
= (unsigned char *) fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
8145 if (byte_order
== BIG_ENDIAN
)
8147 md_number_to_chars (buf
, value
, 2);
8151 case BFD_RELOC_16_PCREL_S2
:
8153 * We need to save the bits in the instruction since fixup_segment()
8154 * might be deleting the relocation entry (i.e., a branch within
8155 * the current segment).
8157 /* TinyRISC can branch to odd addresses */
8158 if ((value
& (mips16
? 0x1 : 0x3)) != 0)
8159 as_warn_where (fixP
->fx_file
, fixP
->fx_line
,
8160 "Branch to odd address (%lx)", value
);
8163 /* update old instruction data */
8164 buf
= (unsigned char *) (fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
);
8168 insn
= (buf
[3] << 24) | (buf
[2] << 16) | (buf
[1] << 8) | buf
[0];
8172 insn
= (buf
[0] << 24) | (buf
[1] << 16) | (buf
[2] << 8) | buf
[3];
8180 if (value
>= -0x8000 && value
< 0x8000)
8181 insn
|= value
& 0xffff;
8184 /* The branch offset is too large. If this is an
8185 unconditional branch, and we are not generating PIC code,
8186 we can convert it to an absolute jump instruction. */
8187 if (mips_pic
== NO_PIC
8189 && fixP
->fx_frag
->fr_address
>= text_section
->vma
8190 && (fixP
->fx_frag
->fr_address
8191 < text_section
->vma
+ text_section
->_raw_size
)
8192 && ((insn
& 0xffff0000) == 0x10000000 /* beq $0,$0 */
8193 || (insn
& 0xffff0000) == 0x04010000 /* bgez $0 */
8194 || (insn
& 0xffff0000) == 0x04110000)) /* bgezal $0 */
8196 if ((insn
& 0xffff0000) == 0x04110000) /* bgezal $0 */
8197 insn
= 0x0c000000; /* jal */
8199 insn
= 0x08000000; /* j */
8200 fixP
->fx_r_type
= BFD_RELOC_MIPS_JMP
;
8202 fixP
->fx_addsy
= section_symbol (text_section
);
8203 fixP
->fx_addnumber
= (value
<< 2) + md_pcrel_from (fixP
);
8207 /* FIXME. It would be possible in principle to handle
8208 conditional branches which overflow. They could be
8209 transformed into a branch around a jump. This would
8210 require setting up variant frags for each different
8211 branch type. The native MIPS assembler attempts to
8212 handle these cases, but it appears to do it
8214 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
8215 "Relocation overflow");
8219 md_number_to_chars ((char *) buf
, (valueT
) insn
, 4);
8234 const struct mips_opcode
*p
;
8235 int treg
, sreg
, dreg
, shamt
;
8240 for (i
= 0; i
< NUMOPCODES
; ++i
)
8242 p
= &mips_opcodes
[i
];
8243 if (((oc
& p
->mask
) == p
->match
) && (p
->pinfo
!= INSN_MACRO
))
8245 printf ("%08lx %s\t", oc
, p
->name
);
8246 treg
= (oc
>> 16) & 0x1f;
8247 sreg
= (oc
>> 21) & 0x1f;
8248 dreg
= (oc
>> 11) & 0x1f;
8249 shamt
= (oc
>> 6) & 0x1f;
8251 for (args
= p
->args
;; ++args
)
8262 printf ("%c", *args
);
8266 assert (treg
== sreg
);
8267 printf ("$%d,$%d", treg
, sreg
);
8272 printf ("$%d", dreg
);
8277 printf ("$%d", treg
);
8281 printf ("0x%x", treg
);
8286 printf ("$%d", sreg
);
8290 printf ("0x%08lx", oc
& 0x1ffffff);
8302 printf ("$%d", shamt
);
8313 printf ("%08lx UNDEFINED\n", oc
);
8324 name
= input_line_pointer
;
8325 c
= get_symbol_end ();
8326 p
= (symbolS
*) symbol_find_or_make (name
);
8327 *input_line_pointer
= c
;
8331 /* Align the current frag to a given power of two. The MIPS assembler
8332 also automatically adjusts any preceding label. */
8335 mips_align (to
, fill
, label
)
8340 mips_emit_delays ();
8341 frag_align (to
, fill
);
8342 record_alignment (now_seg
, to
);
8345 assert (S_GET_SEGMENT (label
) == now_seg
);
8346 label
->sy_frag
= frag_now
;
8347 S_SET_VALUE (label
, (valueT
) frag_now_fix ());
8351 /* Align to a given power of two. .align 0 turns off the automatic
8352 alignment used by the data creating pseudo-ops. */
8359 register long temp_fill
;
8360 long max_alignment
= 15;
8364 o Note that the assembler pulls down any immediately preceeding label
8365 to the aligned address.
8366 o It's not documented but auto alignment is reinstated by
8367 a .align pseudo instruction.
8368 o Note also that after auto alignment is turned off the mips assembler
8369 issues an error on attempt to assemble an improperly aligned data item.
8374 temp
= get_absolute_expression ();
8375 if (temp
> max_alignment
)
8376 as_bad ("Alignment too large: %d. assumed.", temp
= max_alignment
);
8379 as_warn ("Alignment negative: 0 assumed.");
8382 if (*input_line_pointer
== ',')
8384 input_line_pointer
++;
8385 temp_fill
= get_absolute_expression ();
8392 mips_align (temp
, (int) temp_fill
, insn_label
);
8399 demand_empty_rest_of_line ();
8403 mips_flush_pending_output ()
8405 mips_emit_delays ();
8415 /* When generating embedded PIC code, we only use the .text, .lit8,
8416 .sdata and .sbss sections. We change the .data and .rdata
8417 pseudo-ops to use .sdata. */
8418 if (mips_pic
== EMBEDDED_PIC
8419 && (sec
== 'd' || sec
== 'r'))
8422 mips_emit_delays ();
8432 subseg_set (bss_section
, (subsegT
) get_absolute_expression ());
8433 demand_empty_rest_of_line ();
8437 if (USE_GLOBAL_POINTER_OPT
)
8439 seg
= subseg_new (RDATA_SECTION_NAME
,
8440 (subsegT
) get_absolute_expression ());
8441 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
8443 bfd_set_section_flags (stdoutput
, seg
,
8449 bfd_set_section_alignment (stdoutput
, seg
, 4);
8451 demand_empty_rest_of_line ();
8455 as_bad ("No read only data section in this object file format");
8456 demand_empty_rest_of_line ();
8462 if (USE_GLOBAL_POINTER_OPT
)
8464 seg
= subseg_new (".sdata", (subsegT
) get_absolute_expression ());
8465 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
8467 bfd_set_section_flags (stdoutput
, seg
,
8468 SEC_ALLOC
| SEC_LOAD
| SEC_RELOC
8470 bfd_set_section_alignment (stdoutput
, seg
, 4);
8472 demand_empty_rest_of_line ();
8477 as_bad ("Global pointers not supported; recompile -G 0");
8478 demand_empty_rest_of_line ();
8487 mips_enable_auto_align ()
8499 mips_emit_delays ();
8500 if (log_size
> 0 && auto_align
)
8501 mips_align (log_size
, 0, label
);
8503 cons (1 << log_size
);
8514 mips_emit_delays ();
8518 mips_align (3, 0, label
);
8520 mips_align (2, 0, label
);
8527 /* Handle .globl. We need to override it because on Irix 5 you are
8530 where foo is an undefined symbol, to mean that foo should be
8531 considered to be the address of a function. */
8542 name
= input_line_pointer
;
8543 c
= get_symbol_end ();
8544 symbolP
= symbol_find_or_make (name
);
8545 *input_line_pointer
= c
;
8548 /* On Irix 5, every global symbol that is not explicitly labelled as
8549 being a function is apparently labelled as being an object. */
8552 if (! is_end_of_line
[(unsigned char) *input_line_pointer
])
8557 secname
= input_line_pointer
;
8558 c
= get_symbol_end ();
8559 sec
= bfd_get_section_by_name (stdoutput
, secname
);
8561 as_bad ("%s: no such section", secname
);
8562 *input_line_pointer
= c
;
8564 if (sec
!= NULL
&& (sec
->flags
& SEC_CODE
) != 0)
8565 flag
= BSF_FUNCTION
;
8568 symbolP
->bsym
->flags
|= flag
;
8570 S_SET_EXTERNAL (symbolP
);
8571 demand_empty_rest_of_line ();
8581 opt
= input_line_pointer
;
8582 c
= get_symbol_end ();
8586 /* FIXME: What does this mean? */
8588 else if (strncmp (opt
, "pic", 3) == 0)
8596 mips_pic
= SVR4_PIC
;
8598 as_bad (".option pic%d not supported", i
);
8600 if (USE_GLOBAL_POINTER_OPT
&& mips_pic
== SVR4_PIC
)
8602 if (g_switch_seen
&& g_switch_value
!= 0)
8603 as_warn ("-G may not be used with SVR4 PIC code");
8605 bfd_set_gp_size (stdoutput
, 0);
8609 as_warn ("Unrecognized option \"%s\"", opt
);
8611 *input_line_pointer
= c
;
8612 demand_empty_rest_of_line ();
8619 char *name
= input_line_pointer
, ch
;
8621 while (!is_end_of_line
[(unsigned char) *input_line_pointer
])
8622 input_line_pointer
++;
8623 ch
= *input_line_pointer
;
8624 *input_line_pointer
= '\0';
8626 if (strcmp (name
, "reorder") == 0)
8630 prev_insn_unreordered
= 1;
8631 prev_prev_insn_unreordered
= 1;
8635 else if (strcmp (name
, "noreorder") == 0)
8637 mips_emit_delays ();
8639 mips_any_noreorder
= 1;
8641 else if (strcmp (name
, "at") == 0)
8645 else if (strcmp (name
, "noat") == 0)
8649 else if (strcmp (name
, "macro") == 0)
8651 mips_warn_about_macros
= 0;
8653 else if (strcmp (name
, "nomacro") == 0)
8655 if (mips_noreorder
== 0)
8656 as_bad ("`noreorder' must be set before `nomacro'");
8657 mips_warn_about_macros
= 1;
8659 else if (strcmp (name
, "move") == 0 || strcmp (name
, "novolatile") == 0)
8663 else if (strcmp (name
, "nomove") == 0 || strcmp (name
, "volatile") == 0)
8667 else if (strcmp (name
, "bopt") == 0)
8671 else if (strcmp (name
, "nobopt") == 0)
8675 else if (strcmp (name
, "mips16") == 0
8676 || strcmp (name
, "MIPS-16") == 0)
8678 else if (strcmp (name
, "nomips16") == 0
8679 || strcmp (name
, "noMIPS-16") == 0)
8681 else if (strncmp (name
, "mips", 4) == 0)
8685 /* Permit the user to change the ISA on the fly. Needless to
8686 say, misuse can cause serious problems. */
8687 isa
= atoi (name
+ 4);
8689 mips_isa
= file_mips_isa
;
8690 else if (isa
< 1 || isa
> 4)
8691 as_bad ("unknown ISA level");
8695 else if (strcmp (name
, "autoextend") == 0)
8696 mips16_autoextend
= 1;
8697 else if (strcmp (name
, "noautoextend") == 0)
8698 mips16_autoextend
= 0;
8701 as_warn ("Tried to set unrecognized symbol: %s\n", name
);
8703 *input_line_pointer
= ch
;
8704 demand_empty_rest_of_line ();
8707 /* Handle the .abicalls pseudo-op. I believe this is equivalent to
8708 .option pic2. It means to generate SVR4 PIC calls. */
8714 mips_pic
= SVR4_PIC
;
8715 if (USE_GLOBAL_POINTER_OPT
)
8717 if (g_switch_seen
&& g_switch_value
!= 0)
8718 as_warn ("-G may not be used with SVR4 PIC code");
8721 bfd_set_gp_size (stdoutput
, 0);
8722 demand_empty_rest_of_line ();
8725 /* Handle the .cpload pseudo-op. This is used when generating SVR4
8726 PIC code. It sets the $gp register for the function based on the
8727 function address, which is in the register named in the argument.
8728 This uses a relocation against _gp_disp, which is handled specially
8729 by the linker. The result is:
8730 lui $gp,%hi(_gp_disp)
8731 addiu $gp,$gp,%lo(_gp_disp)
8732 addu $gp,$gp,.cpload argument
8733 The .cpload argument is normally $25 == $t9. */
8742 /* If we are not generating SVR4 PIC code, .cpload is ignored. */
8743 if (mips_pic
!= SVR4_PIC
)
8749 /* .cpload should be a in .set noreorder section. */
8750 if (mips_noreorder
== 0)
8751 as_warn (".cpload not in noreorder section");
8754 ex
.X_add_symbol
= symbol_find_or_make ("_gp_disp");
8755 ex
.X_op_symbol
= NULL
;
8756 ex
.X_add_number
= 0;
8758 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
8759 ex
.X_add_symbol
->bsym
->flags
|= BSF_OBJECT
;
8761 macro_build_lui ((char *) NULL
, &icnt
, &ex
, GP
);
8762 macro_build ((char *) NULL
, &icnt
, &ex
, "addiu", "t,r,j", GP
, GP
,
8763 (int) BFD_RELOC_LO16
);
8765 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "addu", "d,v,t",
8766 GP
, GP
, tc_get_register (0));
8768 demand_empty_rest_of_line ();
8771 /* Handle the .cprestore pseudo-op. This stores $gp into a given
8772 offset from $sp. The offset is remembered, and after making a PIC
8773 call $gp is restored from that location. */
8776 s_cprestore (ignore
)
8782 /* If we are not generating SVR4 PIC code, .cprestore is ignored. */
8783 if (mips_pic
!= SVR4_PIC
)
8789 mips_cprestore_offset
= get_absolute_expression ();
8791 ex
.X_op
= O_constant
;
8792 ex
.X_add_symbol
= NULL
;
8793 ex
.X_op_symbol
= NULL
;
8794 ex
.X_add_number
= mips_cprestore_offset
;
8796 macro_build ((char *) NULL
, &icnt
, &ex
,
8797 mips_isa
< 3 ? "sw" : "sd",
8798 "t,o(b)", GP
, (int) BFD_RELOC_LO16
, SP
);
8800 demand_empty_rest_of_line ();
8803 /* Handle the .gpword pseudo-op. This is used when generating PIC
8804 code. It generates a 32 bit GP relative reloc. */
8814 /* When not generating PIC code, this is treated as .word. */
8815 if (mips_pic
!= SVR4_PIC
)
8822 mips_emit_delays ();
8824 mips_align (2, 0, label
);
8829 if (ex
.X_op
!= O_symbol
|| ex
.X_add_number
!= 0)
8831 as_bad ("Unsupported use of .gpword");
8832 ignore_rest_of_line ();
8836 md_number_to_chars (p
, (valueT
) 0, 4);
8837 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 4, &ex
, 0,
8838 BFD_RELOC_MIPS_GPREL32
);
8840 demand_empty_rest_of_line ();
8843 /* Handle the .cpadd pseudo-op. This is used when dealing with switch
8844 tables in SVR4 PIC code. */
8853 /* This is ignored when not generating SVR4 PIC code. */
8854 if (mips_pic
!= SVR4_PIC
)
8860 /* Add $gp to the register named as an argument. */
8861 reg
= tc_get_register (0);
8862 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
8863 mips_isa
< 3 ? "addu" : "daddu",
8864 "d,v,t", reg
, reg
, GP
);
8866 demand_empty_rest_of_line ();
8869 /* Parse a register string into a number. Called from the ECOFF code
8870 to parse .frame. The argument is non-zero if this is the frame
8871 register, so that we can record it in mips_frame_reg. */
8874 tc_get_register (frame
)
8880 if (*input_line_pointer
++ != '$')
8882 as_warn ("expected `$'");
8885 else if (isdigit ((unsigned char) *input_line_pointer
))
8887 reg
= get_absolute_expression ();
8888 if (reg
< 0 || reg
>= 32)
8890 as_warn ("Bad register number");
8896 if (strncmp (input_line_pointer
, "fp", 2) == 0)
8898 else if (strncmp (input_line_pointer
, "sp", 2) == 0)
8900 else if (strncmp (input_line_pointer
, "gp", 2) == 0)
8902 else if (strncmp (input_line_pointer
, "at", 2) == 0)
8906 as_warn ("Unrecognized register name");
8909 input_line_pointer
+= 2;
8912 mips_frame_reg
= reg
!= 0 ? reg
: SP
;
8917 md_section_align (seg
, addr
)
8921 int align
= bfd_get_section_alignment (stdoutput
, seg
);
8924 /* We don't need to align ELF sections to the full alignment.
8925 However, Irix 5 may prefer that we align them at least to a 16
8931 return ((addr
+ (1 << align
) - 1) & (-1 << align
));
8934 /* Utility routine, called from above as well. If called while the
8935 input file is still being read, it's only an approximation. (For
8936 example, a symbol may later become defined which appeared to be
8937 undefined earlier.) */
8940 nopic_need_relax (sym
)
8946 if (USE_GLOBAL_POINTER_OPT
)
8948 const char *symname
;
8951 /* Find out whether this symbol can be referenced off the GP
8952 register. It can be if it is smaller than the -G size or if
8953 it is in the .sdata or .sbss section. Certain symbols can
8954 not be referenced off the GP, although it appears as though
8956 symname
= S_GET_NAME (sym
);
8957 if (symname
!= (const char *) NULL
8958 && (strcmp (symname
, "eprol") == 0
8959 || strcmp (symname
, "etext") == 0
8960 || strcmp (symname
, "_gp") == 0
8961 || strcmp (symname
, "edata") == 0
8962 || strcmp (symname
, "_fbss") == 0
8963 || strcmp (symname
, "_fdata") == 0
8964 || strcmp (symname
, "_ftext") == 0
8965 || strcmp (symname
, "end") == 0
8966 || strcmp (symname
, "_gp_disp") == 0))
8968 else if (! S_IS_DEFINED (sym
)
8970 #ifndef NO_ECOFF_DEBUGGING
8971 || (sym
->ecoff_extern_size
!= 0
8972 && sym
->ecoff_extern_size
<= g_switch_value
)
8974 || (S_GET_VALUE (sym
) != 0
8975 && S_GET_VALUE (sym
) <= g_switch_value
)))
8979 const char *segname
;
8981 segname
= segment_name (S_GET_SEGMENT (sym
));
8982 assert (strcmp (segname
, ".lit8") != 0
8983 && strcmp (segname
, ".lit4") != 0);
8984 change
= (strcmp (segname
, ".sdata") != 0
8985 && strcmp (segname
, ".sbss") != 0);
8990 /* We are not optimizing for the GP register. */
8994 /* Given a mips16 variant frag FRAGP, return non-zero if it needs an
8995 extended opcode. SEC is the section the frag is in. */
8998 mips16_extended_frag (fragp
, sec
, stretch
)
9004 register const struct mips16_immed_operand
*op
;
9006 int mintiny
, maxtiny
;
9008 type
= RELAX_MIPS16_TYPE (fragp
->fr_subtype
);
9009 op
= mips16_immed_operands
;
9010 while (op
->type
!= type
)
9013 assert (op
< mips16_immed_operands
+ MIPS16_NUM_IMMED
);
9018 if (type
== '<' || type
== '>' || type
== '[' || type
== ']')
9021 maxtiny
= 1 << op
->nbits
;
9026 maxtiny
= (1 << op
->nbits
) - 1;
9031 mintiny
= - (1 << (op
->nbits
- 1));
9032 maxtiny
= (1 << (op
->nbits
- 1)) - 1;
9035 /* FIXME: If this is an expression symbol, this will fix its value.
9036 If the expression is actually a subtraction of two symbols in the
9037 segment being relaxed, the value will get fixed inappropriately. */
9038 val
= S_GET_VALUE (fragp
->fr_symbol
);
9040 /* When we are called, symbol values are offsets within a frag. The
9041 address of the frag has not yet been added into the value. */
9042 val
+= fragp
->fr_symbol
->sy_frag
->fr_address
;
9048 /* We won't have the section when we are called from
9049 mips_relax_frag. However, we will always have been called
9050 from md_estimate_size_before_relax first. If this is a
9051 branch to a different section, we mark it as such. If SEC is
9052 NULL, and the frag is not marked, then it must be a branch to
9053 the same section. */
9056 if (RELAX_MIPS16_LONG_BRANCH (fragp
->fr_subtype
))
9061 if (S_GET_SEGMENT (fragp
->fr_symbol
) != sec
)
9064 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
9066 /* FIXME: We should support this, and let the linker
9067 catch branches and loads that are out of range. */
9068 as_bad_where (fragp
->fr_file
, fragp
->fr_line
,
9069 "unsupported PC relative reference to different section");
9075 /* In this case, we know for sure that the symbol fragment is in
9076 the same section. If the fr_address of the symbol fragment
9077 is greater then the address of this fragment we want to add
9078 in STRETCH in order to get a better estimate of the address.
9079 This particularly matters because of the shift bits. */
9081 && fragp
->fr_symbol
->sy_frag
->fr_address
>= fragp
->fr_address
)
9085 /* Adjust stretch for any alignment frag. */
9086 for (f
= fragp
; f
!= fragp
->fr_symbol
->sy_frag
; f
= f
->fr_next
)
9089 if (f
->fr_type
== rs_align
|| f
->fr_type
== rs_align_code
)
9092 stretch
= - ((- stretch
)
9093 & ~ ((1 << (int) f
->fr_offset
) - 1));
9095 stretch
&= ~ ((1 << (int) f
->fr_offset
) - 1);
9103 addr
= fragp
->fr_address
+ fragp
->fr_fix
+ 2;
9105 /* If we are currently assuming that this frag should be
9106 extended, then the current address is two bytes higher. */
9107 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
9110 val
-= addr
& ~ ((1 << op
->shift
) - 1);
9112 /* Branch offsets have an implicit 0 in the lowest bit. */
9113 if (type
== 'p' || type
== 'q')
9116 /* If any of the shifted bits are set, we must use an extended
9117 opcode. If the address depends on the size of this
9118 instruction, this can lead to a loop, so we arrange to always
9119 use an extended opcode. */
9120 if ((val
& ((1 << op
->shift
) - 1)) != 0)
9123 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
9128 if ((val
& ((1 << op
->shift
) - 1)) != 0
9129 || val
< (mintiny
<< op
->shift
)
9130 || val
> (maxtiny
<< op
->shift
))
9136 /* Estimate the size of a frag before relaxing. Unless this is the
9137 mips16, we are not really relaxing here, and the final size is
9138 encoded in the subtype information. For the mips16, we have to
9139 decide whether we are using an extended opcode or not. */
9143 md_estimate_size_before_relax (fragp
, segtype
)
9149 if (RELAX_MIPS16_P (fragp
->fr_subtype
))
9151 if (mips16_extended_frag (fragp
, segtype
, 0))
9153 fragp
->fr_subtype
= RELAX_MIPS16_MARK_EXTENDED (fragp
->fr_subtype
);
9158 fragp
->fr_subtype
= RELAX_MIPS16_CLEAR_EXTENDED (fragp
->fr_subtype
);
9163 if (mips_pic
== NO_PIC
)
9165 change
= nopic_need_relax (fragp
->fr_symbol
);
9167 else if (mips_pic
== SVR4_PIC
)
9169 asection
*symsec
= fragp
->fr_symbol
->bsym
->section
;
9171 /* This must duplicate the test in adjust_reloc_syms. */
9172 change
= (symsec
!= &bfd_und_section
9173 && symsec
!= &bfd_abs_section
9174 && ! bfd_is_com_section (symsec
));
9181 /* Record the offset to the first reloc in the fr_opcode field.
9182 This lets md_convert_frag and tc_gen_reloc know that the code
9183 must be expanded. */
9184 fragp
->fr_opcode
= (fragp
->fr_literal
9186 - RELAX_OLD (fragp
->fr_subtype
)
9187 + RELAX_RELOC1 (fragp
->fr_subtype
));
9188 /* FIXME: This really needs as_warn_where. */
9189 if (RELAX_WARN (fragp
->fr_subtype
))
9190 as_warn ("AT used after \".set noat\" or macro used after \".set nomacro\"");
9196 return RELAX_NEW (fragp
->fr_subtype
) - RELAX_OLD (fragp
->fr_subtype
);
9199 /* Translate internal representation of relocation info to BFD target
9203 tc_gen_reloc (section
, fixp
)
9207 static arelent
*retval
[4];
9209 bfd_reloc_code_real_type code
;
9211 reloc
= retval
[0] = (arelent
*) xmalloc (sizeof (arelent
));
9214 reloc
->sym_ptr_ptr
= &fixp
->fx_addsy
->bsym
;
9215 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
9217 if (mips_pic
== EMBEDDED_PIC
9218 && SWITCH_TABLE (fixp
))
9220 /* For a switch table entry we use a special reloc. The addend
9221 is actually the difference between the reloc address and the
9223 reloc
->addend
= reloc
->address
- S_GET_VALUE (fixp
->fx_subsy
);
9224 if (OUTPUT_FLAVOR
!= bfd_target_ecoff_flavour
)
9225 as_fatal ("Double check fx_r_type in tc-mips.c:tc_gen_reloc");
9226 fixp
->fx_r_type
= BFD_RELOC_GPREL32
;
9228 else if (fixp
->fx_r_type
== BFD_RELOC_PCREL_LO16
)
9230 /* We use a special addend for an internal RELLO reloc. */
9231 if (fixp
->fx_addsy
->bsym
->flags
& BSF_SECTION_SYM
)
9232 reloc
->addend
= reloc
->address
- S_GET_VALUE (fixp
->fx_subsy
);
9234 reloc
->addend
= fixp
->fx_addnumber
+ reloc
->address
;
9236 else if (fixp
->fx_r_type
== BFD_RELOC_PCREL_HI16_S
)
9238 assert (fixp
->fx_next
!= NULL
9239 && fixp
->fx_next
->fx_r_type
== BFD_RELOC_PCREL_LO16
);
9240 /* We use a special addend for an internal RELHI reloc. The
9241 reloc is relative to the RELLO; adjust the addend
9243 if (fixp
->fx_addsy
->bsym
->flags
& BSF_SECTION_SYM
)
9244 reloc
->addend
= (fixp
->fx_next
->fx_frag
->fr_address
9245 + fixp
->fx_next
->fx_where
9246 - S_GET_VALUE (fixp
->fx_subsy
));
9248 reloc
->addend
= (fixp
->fx_addnumber
9249 + fixp
->fx_next
->fx_frag
->fr_address
9250 + fixp
->fx_next
->fx_where
);
9252 else if (fixp
->fx_pcrel
== 0)
9253 reloc
->addend
= fixp
->fx_addnumber
;
9256 if (OUTPUT_FLAVOR
!= bfd_target_aout_flavour
)
9257 /* A gruesome hack which is a result of the gruesome gas reloc
9259 reloc
->addend
= reloc
->address
;
9261 reloc
->addend
= -reloc
->address
;
9264 /* If this is a variant frag, we may need to adjust the existing
9265 reloc and generate a new one. */
9266 if (fixp
->fx_frag
->fr_opcode
!= NULL
9267 && (fixp
->fx_r_type
== BFD_RELOC_MIPS_GPREL
9268 || fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT16
9269 || fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL16
9270 || fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT_HI16
9271 || fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT_LO16
9272 || fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL_HI16
9273 || fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL_LO16
))
9277 assert (! RELAX_MIPS16_P (fixp
->fx_frag
->fr_subtype
));
9279 /* If this is not the last reloc in this frag, then we have two
9280 GPREL relocs, or a GOT_HI16/GOT_LO16 pair, or a
9281 CALL_HI16/CALL_LO16, both of which are being replaced. Let
9282 the second one handle all of them. */
9283 if (fixp
->fx_next
!= NULL
9284 && fixp
->fx_frag
== fixp
->fx_next
->fx_frag
)
9286 assert ((fixp
->fx_r_type
== BFD_RELOC_MIPS_GPREL
9287 && fixp
->fx_next
->fx_r_type
== BFD_RELOC_MIPS_GPREL
)
9288 || (fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT_HI16
9289 && (fixp
->fx_next
->fx_r_type
9290 == BFD_RELOC_MIPS_GOT_LO16
))
9291 || (fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL_HI16
9292 && (fixp
->fx_next
->fx_r_type
9293 == BFD_RELOC_MIPS_CALL_LO16
)));
9298 fixp
->fx_where
= fixp
->fx_frag
->fr_opcode
- fixp
->fx_frag
->fr_literal
;
9299 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
9300 reloc2
= retval
[1] = (arelent
*) xmalloc (sizeof (arelent
));
9302 reloc2
->sym_ptr_ptr
= &fixp
->fx_addsy
->bsym
;
9303 reloc2
->address
= (reloc
->address
9304 + (RELAX_RELOC2 (fixp
->fx_frag
->fr_subtype
)
9305 - RELAX_RELOC1 (fixp
->fx_frag
->fr_subtype
)));
9306 reloc2
->addend
= fixp
->fx_addnumber
;
9307 reloc2
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_LO16
);
9308 assert (reloc2
->howto
!= NULL
);
9310 if (RELAX_RELOC3 (fixp
->fx_frag
->fr_subtype
))
9314 reloc3
= retval
[2] = (arelent
*) xmalloc (sizeof (arelent
));
9317 reloc3
->address
+= 4;
9320 if (mips_pic
== NO_PIC
)
9322 assert (fixp
->fx_r_type
== BFD_RELOC_MIPS_GPREL
);
9323 fixp
->fx_r_type
= BFD_RELOC_HI16_S
;
9325 else if (mips_pic
== SVR4_PIC
)
9327 switch (fixp
->fx_r_type
)
9331 case BFD_RELOC_MIPS_GOT16
:
9333 case BFD_RELOC_MIPS_CALL16
:
9334 case BFD_RELOC_MIPS_GOT_LO16
:
9335 case BFD_RELOC_MIPS_CALL_LO16
:
9336 fixp
->fx_r_type
= BFD_RELOC_MIPS_GOT16
;
9344 /* Since DIFF_EXPR_OK is defined in tc-mips.h, it is possible that
9345 fixup_segment converted a non-PC relative reloc into a PC
9346 relative reloc. In such a case, we need to convert the reloc
9348 code
= fixp
->fx_r_type
;
9354 code
= BFD_RELOC_8_PCREL
;
9357 code
= BFD_RELOC_16_PCREL
;
9360 code
= BFD_RELOC_32_PCREL
;
9363 code
= BFD_RELOC_64_PCREL
;
9365 case BFD_RELOC_8_PCREL
:
9366 case BFD_RELOC_16_PCREL
:
9367 case BFD_RELOC_32_PCREL
:
9368 case BFD_RELOC_64_PCREL
:
9369 case BFD_RELOC_16_PCREL_S2
:
9370 case BFD_RELOC_PCREL_HI16_S
:
9371 case BFD_RELOC_PCREL_LO16
:
9374 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
9375 "Cannot make %s relocation PC relative",
9376 bfd_get_reloc_code_name (code
));
9380 /* To support a PC relative reloc when generating embedded PIC code
9381 for ECOFF, we use a Cygnus extension. We check for that here to
9382 make sure that we don't let such a reloc escape normally. */
9383 if (OUTPUT_FLAVOR
== bfd_target_ecoff_flavour
9384 && code
== BFD_RELOC_16_PCREL_S2
9385 && mips_pic
!= EMBEDDED_PIC
)
9386 reloc
->howto
= NULL
;
9388 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
9390 if (reloc
->howto
== NULL
)
9392 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
9393 "Can not represent %s relocation in this object file format",
9394 bfd_get_reloc_code_name (code
));
9401 /* Relax a machine dependent frag. This returns the amount by which
9402 the current size of the frag should change. */
9405 mips_relax_frag (fragp
, stretch
)
9409 if (! RELAX_MIPS16_P (fragp
->fr_subtype
))
9412 if (mips16_extended_frag (fragp
, (asection
*) NULL
, stretch
))
9414 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
9416 fragp
->fr_subtype
= RELAX_MIPS16_MARK_EXTENDED (fragp
->fr_subtype
);
9421 if (! RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
9423 fragp
->fr_subtype
= RELAX_MIPS16_CLEAR_EXTENDED (fragp
->fr_subtype
);
9430 /* Convert a machine dependent frag. */
9433 md_convert_frag (abfd
, asec
, fragp
)
9441 if (RELAX_MIPS16_P (fragp
->fr_subtype
))
9444 register const struct mips16_immed_operand
*op
;
9450 unsigned short extend
;
9452 type
= RELAX_MIPS16_TYPE (fragp
->fr_subtype
);
9453 op
= mips16_immed_operands
;
9454 while (op
->type
!= type
)
9457 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
9468 val
= S_GET_VALUE (fragp
->fr_symbol
);
9469 val
+= fragp
->fr_symbol
->sy_frag
->fr_address
;
9474 addr
= fragp
->fr_address
+ fragp
->fr_fix
+ 2;
9477 addr
&= ~ (addressT
) ((1 << op
->shift
) - 1);
9481 buf
= (bfd_byte
*) (fragp
->fr_literal
+ fragp
->fr_fix
);
9488 insn
= bfd_getl16 (buf
);
9491 insn
= bfd_getb16 (buf
);
9495 mips16_immed (type
, val
, false, small
, ext
, &insn
, &use_extend
, &extend
);
9499 md_number_to_chars (buf
, 0xf000 | extend
, 2);
9504 md_number_to_chars (buf
, insn
, 2);
9510 if (fragp
->fr_opcode
== NULL
)
9513 old
= RELAX_OLD (fragp
->fr_subtype
);
9514 new = RELAX_NEW (fragp
->fr_subtype
);
9515 fixptr
= fragp
->fr_literal
+ fragp
->fr_fix
;
9518 memcpy (fixptr
- old
, fixptr
, new);
9520 fragp
->fr_fix
+= new - old
;
9524 /* This function is called whenever a label is defined. It is used
9525 when handling branch delays; if a branch has a label, we assume we
9529 mips_define_label (sym
)
9535 S_SET_OTHER (insn_label
, STO_MIPS16
);
9539 /* Decide whether a label is local. This is called by LOCAL_LABEL.
9540 In order to work with gcc when using mips-tfile, we must keep all
9541 local labels. However, in other cases, we want to discard them,
9542 since they are useless. */
9545 mips_local_label (name
)
9548 #ifndef NO_ECOFF_DEBUGGING
9551 && ! ecoff_debugging_seen
)
9553 /* We were called with -g, but we didn't see any debugging
9554 information. That may mean that gcc is smuggling debugging
9555 information through to mips-tfile, in which case we must
9556 generate all local labels. */
9561 /* Here it's OK to discard local labels. */
9563 return name
[0] == '$';
9566 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9568 /* Some special processing for a MIPS ELF file. */
9571 mips_elf_final_processing ()
9573 /* Write out the register information. */
9578 s
.ri_gprmask
= mips_gprmask
;
9579 s
.ri_cprmask
[0] = mips_cprmask
[0];
9580 s
.ri_cprmask
[1] = mips_cprmask
[1];
9581 s
.ri_cprmask
[2] = mips_cprmask
[2];
9582 s
.ri_cprmask
[3] = mips_cprmask
[3];
9583 /* The gp_value field is set by the MIPS ELF backend. */
9585 bfd_mips_elf32_swap_reginfo_out (stdoutput
, &s
,
9586 ((Elf32_External_RegInfo
*)
9587 mips_regmask_frag
));
9591 Elf64_Internal_RegInfo s
;
9593 s
.ri_gprmask
= mips_gprmask
;
9595 s
.ri_cprmask
[0] = mips_cprmask
[0];
9596 s
.ri_cprmask
[1] = mips_cprmask
[1];
9597 s
.ri_cprmask
[2] = mips_cprmask
[2];
9598 s
.ri_cprmask
[3] = mips_cprmask
[3];
9599 /* The gp_value field is set by the MIPS ELF backend. */
9601 bfd_mips_elf64_swap_reginfo_out (stdoutput
, &s
,
9602 ((Elf64_External_RegInfo
*)
9603 mips_regmask_frag
));
9606 /* Set the MIPS ELF flag bits. FIXME: There should probably be some
9607 sort of BFD interface for this. */
9608 if (mips_any_noreorder
)
9609 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_NOREORDER
;
9610 if (mips_pic
!= NO_PIC
)
9611 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_PIC
;
9614 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */
9616 /* These functions should really be defined by the object file format,
9617 since they are related to debugging information. However, this
9618 code has to work for the a.out format, which does not define them,
9619 so we provide simple versions here. These don't actually generate
9620 any debugging information, but they do simple checking and someday
9621 somebody may make them useful. */
9625 struct loc
*loc_next
;
9626 unsigned long loc_fileno
;
9627 unsigned long loc_lineno
;
9628 unsigned long loc_offset
;
9629 unsigned short loc_delta
;
9630 unsigned short loc_count
;
9639 struct proc
*proc_next
;
9640 struct symbol
*proc_isym
;
9641 struct symbol
*proc_end
;
9642 unsigned long proc_reg_mask
;
9643 unsigned long proc_reg_offset
;
9644 unsigned long proc_fpreg_mask
;
9645 unsigned long proc_fpreg_offset
;
9646 unsigned long proc_frameoffset
;
9647 unsigned long proc_framereg
;
9648 unsigned long proc_pcreg
;
9650 struct file
*proc_file
;
9657 struct file
*file_next
;
9658 unsigned long file_fileno
;
9659 struct symbol
*file_symbol
;
9660 struct symbol
*file_end
;
9661 struct proc
*file_proc
;
9666 static struct obstack proc_frags
;
9667 static procS
*proc_lastP
;
9668 static procS
*proc_rootP
;
9669 static int numprocs
;
9674 obstack_begin (&proc_frags
, 0x2000);
9680 /* check for premature end, nesting errors, etc */
9681 if (proc_lastP
&& proc_lastP
->proc_end
== NULL
)
9682 as_warn ("missing `.end' at end of assembly");
9691 if (*input_line_pointer
== '-')
9693 ++input_line_pointer
;
9696 if (!isdigit (*input_line_pointer
))
9697 as_bad ("Expected simple number.");
9698 if (input_line_pointer
[0] == '0')
9700 if (input_line_pointer
[1] == 'x')
9702 input_line_pointer
+= 2;
9703 while (isxdigit (*input_line_pointer
))
9706 val
|= hex_value (*input_line_pointer
++);
9708 return negative
? -val
: val
;
9712 ++input_line_pointer
;
9713 while (isdigit (*input_line_pointer
))
9716 val
|= *input_line_pointer
++ - '0';
9718 return negative
? -val
: val
;
9721 if (!isdigit (*input_line_pointer
))
9723 printf (" *input_line_pointer == '%c' 0x%02x\n",
9724 *input_line_pointer
, *input_line_pointer
);
9725 as_warn ("Invalid number");
9728 while (isdigit (*input_line_pointer
))
9731 val
+= *input_line_pointer
++ - '0';
9733 return negative
? -val
: val
;
9736 /* The .file directive; just like the usual .file directive, but there
9737 is an initial number which is the ECOFF file index. */
9745 line
= get_number ();
9750 /* The .end directive. */
9758 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
9761 demand_empty_rest_of_line ();
9765 if (now_seg
!= text_section
)
9766 as_warn (".end not in text section");
9769 as_warn (".end and no .ent seen yet.");
9775 assert (S_GET_NAME (p
));
9776 if (strcmp (S_GET_NAME (p
), S_GET_NAME (proc_lastP
->proc_isym
)))
9777 as_warn (".end symbol does not match .ent symbol.");
9780 proc_lastP
->proc_end
= (symbolS
*) 1;
9783 /* The .aent and .ent directives. */
9793 symbolP
= get_symbol ();
9794 if (*input_line_pointer
== ',')
9795 input_line_pointer
++;
9797 if (isdigit (*input_line_pointer
) || *input_line_pointer
== '-')
9798 number
= get_number ();
9799 if (now_seg
!= text_section
)
9800 as_warn (".ent or .aent not in text section.");
9802 if (!aent
&& proc_lastP
&& proc_lastP
->proc_end
== NULL
)
9803 as_warn ("missing `.end'");
9807 procP
= (procS
*) obstack_alloc (&proc_frags
, sizeof (*procP
));
9808 procP
->proc_isym
= symbolP
;
9809 procP
->proc_reg_mask
= 0;
9810 procP
->proc_reg_offset
= 0;
9811 procP
->proc_fpreg_mask
= 0;
9812 procP
->proc_fpreg_offset
= 0;
9813 procP
->proc_frameoffset
= 0;
9814 procP
->proc_framereg
= 0;
9815 procP
->proc_pcreg
= 0;
9816 procP
->proc_end
= NULL
;
9817 procP
->proc_next
= NULL
;
9819 proc_lastP
->proc_next
= procP
;
9825 demand_empty_rest_of_line ();
9828 /* The .frame directive. */
9841 frame_reg
= tc_get_register (1);
9842 if (*input_line_pointer
== ',')
9843 input_line_pointer
++;
9844 frame_off
= get_absolute_expression ();
9845 if (*input_line_pointer
== ',')
9846 input_line_pointer
++;
9847 pcreg
= tc_get_register (0);
9850 assert (proc_rootP
);
9851 proc_rootP
->proc_framereg
= frame_reg
;
9852 proc_rootP
->proc_frameoffset
= frame_off
;
9853 proc_rootP
->proc_pcreg
= pcreg
;
9854 /* bob macho .frame */
9856 /* We don't have to write out a frame stab for unoptimized code. */
9857 if (!(frame_reg
== FP
&& frame_off
== 0))
9860 as_warn ("No .ent for .frame to use.");
9861 (void) sprintf (str
, "R%d;%d", frame_reg
, frame_off
);
9862 symP
= symbol_new (str
, N_VFP
, 0, frag_now
);
9863 S_SET_TYPE (symP
, N_RMASK
);
9864 S_SET_OTHER (symP
, 0);
9865 S_SET_DESC (symP
, 0);
9866 symP
->sy_forward
= proc_lastP
->proc_isym
;
9867 /* bob perhaps I should have used pseudo set */
9869 demand_empty_rest_of_line ();
9873 /* The .fmask and .mask directives. */
9880 char str
[100], *strP
;
9886 mask
= get_number ();
9887 if (*input_line_pointer
== ',')
9888 input_line_pointer
++;
9889 off
= get_absolute_expression ();
9891 /* bob only for coff */
9892 assert (proc_rootP
);
9893 if (reg_type
== 'F')
9895 proc_rootP
->proc_fpreg_mask
= mask
;
9896 proc_rootP
->proc_fpreg_offset
= off
;
9900 proc_rootP
->proc_reg_mask
= mask
;
9901 proc_rootP
->proc_reg_offset
= off
;
9904 /* bob macho .mask + .fmask */
9906 /* We don't have to write out a mask stab if no saved regs. */
9910 as_warn ("No .ent for .mask to use.");
9912 for (i
= 0; i
< 32; i
++)
9916 sprintf (strP
, "%c%d,", reg_type
, i
);
9917 strP
+= strlen (strP
);
9921 sprintf (strP
, ";%d,", off
);
9922 symP
= symbol_new (str
, N_RMASK
, 0, frag_now
);
9923 S_SET_TYPE (symP
, N_RMASK
);
9924 S_SET_OTHER (symP
, 0);
9925 S_SET_DESC (symP
, 0);
9926 symP
->sy_forward
= proc_lastP
->proc_isym
;
9927 /* bob perhaps I should have used pseudo set */
9932 /* The .loc directive. */
9943 assert (now_seg
== text_section
);
9945 lineno
= get_number ();
9946 addroff
= frag_now_fix ();
9948 symbolP
= symbol_new ("", N_SLINE
, addroff
, frag_now
);
9949 S_SET_TYPE (symbolP
, N_SLINE
);
9950 S_SET_OTHER (symbolP
, 0);
9951 S_SET_DESC (symbolP
, lineno
);
9952 symbolP
->sy_segment
= now_seg
;