1 /* tc-mips.c -- assemble code for a MIPS chip.
2 Copyright (C) 1993, 1995, 1996 Free Software Foundation, Inc.
3 Contributed by the OSF and Ralph Campbell.
4 Written by Keith Knowles and Ralph Campbell, working independently.
5 Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus
8 This file is part of GAS.
10 GAS is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 2, or (at your option)
15 GAS is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with GAS; see the file COPYING. If not, write to the Free
22 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
28 #include "libiberty.h"
39 #include "opcode/mips.h"
42 /* Clean up namespace so we can include obj-elf.h too. */
43 static int mips_output_flavor () { return OUTPUT_FLAVOR
; }
44 #undef OBJ_PROCESS_STAB
50 #undef TARGET_SYMBOL_FIELDS
52 #undef obj_frob_symbol
54 #undef obj_sec_sym_ok_for_reloc
57 /* Fix any of them that we actually care about. */
59 #define OUTPUT_FLAVOR mips_output_flavor()
66 #ifndef ECOFF_DEBUGGING
67 #define NO_ECOFF_DEBUGGING
68 #define ECOFF_DEBUGGING 0
73 static char *mips_regmask_frag
;
76 #define PIC_CALL_REG 25
84 extern int target_big_endian
;
86 /* 1 is we should use the 64 bit MIPS ELF ABI, 0 if we should use the
87 32 bit ABI. This has no meaning for ECOFF. */
90 /* The default target format to use. */
94 switch (OUTPUT_FLAVOR
)
96 case bfd_target_aout_flavour
:
97 return target_big_endian
? "a.out-mips-big" : "a.out-mips-little";
98 case bfd_target_ecoff_flavour
:
99 return target_big_endian
? "ecoff-bigmips" : "ecoff-littlemips";
100 case bfd_target_elf_flavour
:
101 return (target_big_endian
102 ? (mips_64
? "elf64-bigmips" : "elf32-bigmips")
103 : (mips_64
? "elf64-littlemips" : "elf32-littlemips"));
109 /* The name of the readonly data section. */
110 #define RDATA_SECTION_NAME (OUTPUT_FLAVOR == bfd_target_aout_flavour \
112 : OUTPUT_FLAVOR == bfd_target_ecoff_flavour \
114 : OUTPUT_FLAVOR == bfd_target_elf_flavour \
118 /* These variables are filled in with the masks of registers used.
119 The object format code reads them and puts them in the appropriate
121 unsigned long mips_gprmask
;
122 unsigned long mips_cprmask
[4];
124 /* MIPS ISA (Instruction Set Architecture) level (may be changed
125 temporarily using .set mipsN). */
126 static int mips_isa
= -1;
128 /* MIPS ISA we are using for this output file. */
129 static int file_mips_isa
;
131 /* The CPU type as a number: 2000, 3000, 4000, 4400, etc. */
132 static int mips_cpu
= -1;
134 /* Whether the 4650 instructions (mad/madu) are permitted. */
135 static int mips_4650
= -1;
137 /* Whether the 4010 instructions are permitted. */
138 static int mips_4010
= -1;
140 /* Whether the 4100 MADD16 and DMADD16 are permitted. */
141 static int mips_4100
= -1;
143 /* Whether the processor uses hardware interlocks, and thus does not
144 require nops to be inserted. */
145 static int interlocks
= -1;
147 /* MIPS PIC level. */
151 /* Do not generate PIC code. */
154 /* Generate PIC code as in Irix 4. This is not implemented, and I'm
155 not sure what it is supposed to do. */
158 /* Generate PIC code as in the SVR4 MIPS ABI. */
161 /* Generate PIC code without using a global offset table: the data
162 segment has a maximum size of 64K, all data references are off
163 the $gp register, and all text references are PC relative. This
164 is used on some embedded systems. */
168 static enum mips_pic_level mips_pic
;
170 /* 1 if we should generate 32 bit offsets from the GP register in
171 SVR4_PIC mode. Currently has no meaning in other modes. */
172 static int mips_big_got
;
174 /* 1 if trap instructions should used for overflow rather than break
176 static int mips_trap
;
178 static int mips_warn_about_macros
;
179 static int mips_noreorder
;
180 static int mips_any_noreorder
;
181 static int mips_nomove
;
182 static int mips_noat
;
183 static int mips_nobopt
;
185 /* The size of the small data section. */
186 static int g_switch_value
= 8;
187 /* Whether the -G option was used. */
188 static int g_switch_seen
= 0;
193 /* If we can determine in advance that GP optimization won't be
194 possible, we can skip the relaxation stuff that tries to produce
195 GP-relative references. This makes delay slot optimization work
198 This function can only provide a guess, but it seems to work for
199 gcc output. If it guesses wrong, the only loss should be in
200 efficiency; it shouldn't introduce any bugs.
202 I don't know if a fix is needed for the SVR4_PIC mode. I've only
203 fixed it for the non-PIC mode. KR 95/04/07 */
204 static int nopic_need_relax
PARAMS ((symbolS
*));
206 /* handle of the OPCODE hash table */
207 static struct hash_control
*op_hash
= NULL
;
209 /* This array holds the chars that always start a comment. If the
210 pre-processor is disabled, these aren't very useful */
211 const char comment_chars
[] = "#";
213 /* This array holds the chars that only start a comment at the beginning of
214 a line. If the line seems to have the form '# 123 filename'
215 .line and .file directives will appear in the pre-processed output */
216 /* Note that input_file.c hand checks for '#' at the beginning of the
217 first line of the input file. This is because the compiler outputs
218 #NO_APP at the beginning of its output. */
219 /* Also note that C style comments are always supported. */
220 const char line_comment_chars
[] = "#";
222 /* This array holds machine specific line separator characters. */
223 const char line_separator_chars
[] = "";
225 /* Chars that can be used to separate mant from exp in floating point nums */
226 const char EXP_CHARS
[] = "eE";
228 /* Chars that mean this number is a floating point constant */
231 const char FLT_CHARS
[] = "rRsSfFdDxXpP";
233 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
234 changed in read.c . Ideally it shouldn't have to know about it at all,
235 but nothing is ideal around here.
238 static char *insn_error
;
240 static int byte_order
;
242 static int auto_align
= 1;
244 /* Symbol labelling the current insn. */
245 static symbolS
*insn_label
;
247 /* When outputting SVR4 PIC code, the assembler needs to know the
248 offset in the stack frame from which to restore the $gp register.
249 This is set by the .cprestore pseudo-op, and saved in this
251 static offsetT mips_cprestore_offset
= -1;
253 /* This is the register which holds the stack frame, as set by the
254 .frame pseudo-op. This is needed to implement .cprestore. */
255 static int mips_frame_reg
= SP
;
257 /* To output NOP instructions correctly, we need to keep information
258 about the previous two instructions. */
260 /* Whether we are optimizing. The default value of 2 means to remove
261 unneeded NOPs and swap branch instructions when possible. A value
262 of 1 means to not swap branches. A value of 0 means to always
264 static int mips_optimize
= 2;
266 /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is
267 equivalent to seeing no -g option at all. */
268 static int mips_debug
= 0;
270 /* The previous instruction. */
271 static struct mips_cl_insn prev_insn
;
273 /* The instruction before prev_insn. */
274 static struct mips_cl_insn prev_prev_insn
;
276 /* If we don't want information for prev_insn or prev_prev_insn, we
277 point the insn_mo field at this dummy integer. */
278 static const struct mips_opcode dummy_opcode
= { 0 };
280 /* Non-zero if prev_insn is valid. */
281 static int prev_insn_valid
;
283 /* The frag for the previous instruction. */
284 static struct frag
*prev_insn_frag
;
286 /* The offset into prev_insn_frag for the previous instruction. */
287 static long prev_insn_where
;
289 /* The reloc for the previous instruction, if any. */
290 static fixS
*prev_insn_fixp
;
292 /* Non-zero if the previous instruction was in a delay slot. */
293 static int prev_insn_is_delay_slot
;
295 /* Non-zero if the previous instruction was in a .set noreorder. */
296 static int prev_insn_unreordered
;
298 /* Non-zero if the previous previous instruction was in a .set
300 static int prev_prev_insn_unreordered
;
302 /* For ECOFF and ELF, relocations against symbols are done in two
303 parts, with a HI relocation and a LO relocation. Each relocation
304 has only 16 bits of space to store an addend. This means that in
305 order for the linker to handle carries correctly, it must be able
306 to locate both the HI and the LO relocation. This means that the
307 relocations must appear in order in the relocation table.
309 In order to implement this, we keep track of each unmatched HI
310 relocation. We then sort them so that they immediately precede the
311 corresponding LO relocation. */
316 struct mips_hi_fixup
*next
;
319 /* The section this fixup is in. */
323 /* The list of unmatched HI relocs. */
325 static struct mips_hi_fixup
*mips_hi_fixup_list
;
327 /* Since the MIPS does not have multiple forms of PC relative
328 instructions, we do not have to do relaxing as is done on other
329 platforms. However, we do have to handle GP relative addressing
330 correctly, which turns out to be a similar problem.
332 Every macro that refers to a symbol can occur in (at least) two
333 forms, one with GP relative addressing and one without. For
334 example, loading a global variable into a register generally uses
335 a macro instruction like this:
337 If i can be addressed off the GP register (this is true if it is in
338 the .sbss or .sdata section, or if it is known to be smaller than
339 the -G argument) this will generate the following instruction:
341 This instruction will use a GPREL reloc. If i can not be addressed
342 off the GP register, the following instruction sequence will be used:
345 In this case the first instruction will have a HI16 reloc, and the
346 second reloc will have a LO16 reloc. Both relocs will be against
349 The issue here is that we may not know whether i is GP addressable
350 until after we see the instruction that uses it. Therefore, we
351 want to be able to choose the final instruction sequence only at
352 the end of the assembly. This is similar to the way other
353 platforms choose the size of a PC relative instruction only at the
356 When generating position independent code we do not use GP
357 addressing in quite the same way, but the issue still arises as
358 external symbols and local symbols must be handled differently.
360 We handle these issues by actually generating both possible
361 instruction sequences. The longer one is put in a frag_var with
362 type rs_machine_dependent. We encode what to do with the frag in
363 the subtype field. We encode (1) the number of existing bytes to
364 replace, (2) the number of new bytes to use, (3) the offset from
365 the start of the existing bytes to the first reloc we must generate
366 (that is, the offset is applied from the start of the existing
367 bytes after they are replaced by the new bytes, if any), (4) the
368 offset from the start of the existing bytes to the second reloc,
369 (5) whether a third reloc is needed (the third reloc is always four
370 bytes after the second reloc), and (6) whether to warn if this
371 variant is used (this is sometimes needed if .set nomacro or .set
372 noat is in effect). All these numbers are reasonably small.
374 Generating two instruction sequences must be handled carefully to
375 ensure that delay slots are handled correctly. Fortunately, there
376 are a limited number of cases. When the second instruction
377 sequence is generated, append_insn is directed to maintain the
378 existing delay slot information, so it continues to apply to any
379 code after the second instruction sequence. This means that the
380 second instruction sequence must not impose any requirements not
381 required by the first instruction sequence.
383 These variant frags are then handled in functions called by the
384 machine independent code. md_estimate_size_before_relax returns
385 the final size of the frag. md_convert_frag sets up the final form
386 of the frag. tc_gen_reloc adjust the first reloc and adds a second
388 #define RELAX_ENCODE(old, new, reloc1, reloc2, reloc3, warn) \
392 | (((reloc1) + 64) << 9) \
393 | (((reloc2) + 64) << 2) \
394 | ((reloc3) ? (1 << 1) : 0) \
396 #define RELAX_OLD(i) (((i) >> 24) & 0xff)
397 #define RELAX_NEW(i) (((i) >> 16) & 0xff)
398 #define RELAX_RELOC1(i) ((bfd_vma)(((i) >> 9) & 0x7f) - 64)
399 #define RELAX_RELOC2(i) ((bfd_vma)(((i) >> 2) & 0x7f) - 64)
400 #define RELAX_RELOC3(i) (((i) >> 1) & 1)
401 #define RELAX_WARN(i) ((i) & 1)
403 /* Prototypes for static functions. */
406 #define internalError() \
407 as_fatal ("internal Error, line %d, %s", __LINE__, __FILE__)
409 #define internalError() as_fatal ("MIPS internal Error");
412 static int insn_uses_reg
PARAMS ((struct mips_cl_insn
*ip
,
413 unsigned int reg
, int fpr
));
414 static int reg_needs_delay
PARAMS ((int));
415 static void append_insn
PARAMS ((char *place
,
416 struct mips_cl_insn
* ip
,
418 bfd_reloc_code_real_type r
,
420 static void mips_no_prev_insn
PARAMS ((void));
421 static void mips_emit_delays
PARAMS ((void));
423 static void macro_build
PARAMS ((char *place
, int *counter
, expressionS
* ep
,
424 const char *name
, const char *fmt
,
427 static void macro_build ();
429 static void macro_build_lui
PARAMS ((char *place
, int *counter
,
430 expressionS
* ep
, int regnum
));
431 static void set_at
PARAMS ((int *counter
, int reg
, int unsignedp
));
432 static void check_absolute_expr
PARAMS ((struct mips_cl_insn
* ip
,
434 static void load_register
PARAMS ((int *, int, expressionS
*, int));
435 static void load_address
PARAMS ((int *counter
, int reg
, expressionS
*ep
));
436 static void macro
PARAMS ((struct mips_cl_insn
* ip
));
437 #ifdef LOSING_COMPILER
438 static void macro2
PARAMS ((struct mips_cl_insn
* ip
));
440 static void mips_ip
PARAMS ((char *str
, struct mips_cl_insn
* ip
));
441 static int my_getSmallExpression
PARAMS ((expressionS
* ep
, char *str
));
442 static void my_getExpression
PARAMS ((expressionS
* ep
, char *str
));
443 static symbolS
*get_symbol
PARAMS ((void));
444 static void mips_align
PARAMS ((int to
, int fill
, symbolS
*label
));
445 static void s_align
PARAMS ((int));
446 static void s_change_sec
PARAMS ((int));
447 static void s_cons
PARAMS ((int));
448 static void s_float_cons
PARAMS ((int));
449 static void s_mips_globl
PARAMS ((int));
450 static void s_option
PARAMS ((int));
451 static void s_mipsset
PARAMS ((int));
452 static void s_abicalls
PARAMS ((int));
453 static void s_cpload
PARAMS ((int));
454 static void s_cprestore
PARAMS ((int));
455 static void s_gpword
PARAMS ((int));
456 static void s_cpadd
PARAMS ((int));
457 static void md_obj_begin
PARAMS ((void));
458 static void md_obj_end
PARAMS ((void));
459 static long get_number
PARAMS ((void));
460 static void s_ent
PARAMS ((int));
461 static void s_mipsend
PARAMS ((int));
462 static void s_file
PARAMS ((int));
466 The following pseudo-ops from the Kane and Heinrich MIPS book
467 should be defined here, but are currently unsupported: .alias,
468 .galive, .gjaldef, .gjrlive, .livereg, .noalias.
470 The following pseudo-ops from the Kane and Heinrich MIPS book are
471 specific to the type of debugging information being generated, and
472 should be defined by the object format: .aent, .begin, .bend,
473 .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp,
476 The following pseudo-ops from the Kane and Heinrich MIPS book are
477 not MIPS CPU specific, but are also not specific to the object file
478 format. This file is probably the best place to define them, but
479 they are not currently supported: .asm0, .endr, .lab, .repeat,
480 .struct, .weakext. */
482 static const pseudo_typeS mips_pseudo_table
[] =
484 /* MIPS specific pseudo-ops. */
485 {"option", s_option
, 0},
486 {"set", s_mipsset
, 0},
487 {"rdata", s_change_sec
, 'r'},
488 {"sdata", s_change_sec
, 's'},
489 {"livereg", s_ignore
, 0},
490 {"abicalls", s_abicalls
, 0},
491 {"cpload", s_cpload
, 0},
492 {"cprestore", s_cprestore
, 0},
493 {"gpword", s_gpword
, 0},
494 {"cpadd", s_cpadd
, 0},
496 /* Relatively generic pseudo-ops that happen to be used on MIPS
498 {"asciiz", stringer
, 1},
499 {"bss", s_change_sec
, 'b'},
502 {"dword", s_cons
, 3},
504 /* These pseudo-ops are defined in read.c, but must be overridden
505 here for one reason or another. */
506 {"align", s_align
, 0},
508 {"data", s_change_sec
, 'd'},
509 {"double", s_float_cons
, 'd'},
510 {"float", s_float_cons
, 'f'},
511 {"globl", s_mips_globl
, 0},
512 {"global", s_mips_globl
, 0},
513 {"hword", s_cons
, 1},
518 {"short", s_cons
, 1},
519 {"single", s_float_cons
, 'f'},
520 {"text", s_change_sec
, 't'},
525 static const pseudo_typeS mips_nonecoff_pseudo_table
[] = {
526 /* These pseudo-ops should be defined by the object file format.
527 However, a.out doesn't support them, so we have versions here. */
529 {"bgnb", s_ignore
, 0},
530 {"end", s_mipsend
, 0},
531 {"endb", s_ignore
, 0},
534 {"fmask", s_ignore
, 'F'},
535 {"frame", s_ignore
, 0},
536 {"loc", s_ignore
, 0},
537 {"mask", s_ignore
, 'R'},
538 {"verstamp", s_ignore
, 0},
542 extern void pop_insert
PARAMS ((const pseudo_typeS
*));
547 pop_insert (mips_pseudo_table
);
548 if (! ECOFF_DEBUGGING
)
549 pop_insert (mips_nonecoff_pseudo_table
);
552 static char *expr_end
;
554 /* Expressions which appear in instructions. These are set by
557 static expressionS imm_expr
;
558 static expressionS offset_expr
;
560 /* Relocs associated with imm_expr and offset_expr. */
562 static bfd_reloc_code_real_type imm_reloc
;
563 static bfd_reloc_code_real_type offset_reloc
;
565 /* This is set by mips_ip if imm_reloc is an unmatched HI16_S reloc. */
567 static boolean imm_unmatched_hi
;
570 * This function is called once, at assembler startup time. It should
571 * set up all the tables, etc. that the MD part of the assembler will need.
577 register const char *retval
= NULL
;
578 register unsigned int i
= 0;
586 if (strcmp (cpu
+ (sizeof TARGET_CPU
) - 3, "el") == 0)
588 a
= xmalloc (sizeof TARGET_CPU
);
589 strcpy (a
, TARGET_CPU
);
590 a
[(sizeof TARGET_CPU
) - 3] = '\0';
594 if (strcmp (cpu
, "mips") == 0)
600 else if (strcmp (cpu
, "r6000") == 0
601 || strcmp (cpu
, "mips2") == 0)
607 else if (strcmp (cpu
, "mips64") == 0
608 || strcmp (cpu
, "r4000") == 0
609 || strcmp (cpu
, "mips3") == 0)
615 else if (strcmp (cpu
, "r4400") == 0)
621 else if (strcmp (cpu
, "mips64orion") == 0
622 || strcmp (cpu
, "r4600") == 0)
628 else if (strcmp (cpu
, "r4650") == 0)
636 else if (strcmp (cpu
, "mips64vr4300") == 0)
642 else if (strcmp (cpu
, "mips64vr4100") == 0)
650 else if (strcmp (cpu
, "r4010") == 0)
658 else if (strcmp (cpu
, "r8000") == 0
659 || strcmp (cpu
, "mips4") == 0)
665 else if (strcmp (cpu
, "r10000") == 0)
691 if (mips_4650
|| mips_4010
|| mips_4100
)
696 if (mips_isa
< 2 && mips_trap
)
697 as_bad ("trap exception not supported at ISA 1");
702 ok
= bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, 3000);
705 ok
= bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, 6000);
708 ok
= bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, 4000);
711 ok
= bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, 8000);
715 as_warn ("Could not set architecture and machine");
717 file_mips_isa
= mips_isa
;
719 op_hash
= hash_new ();
721 for (i
= 0; i
< NUMOPCODES
;)
723 const char *name
= mips_opcodes
[i
].name
;
725 retval
= hash_insert (op_hash
, name
, (PTR
) &mips_opcodes
[i
]);
728 fprintf (stderr
, "internal error: can't hash `%s': %s\n",
729 mips_opcodes
[i
].name
, retval
);
730 as_fatal ("Broken assembler. No assembly attempted.");
734 if (mips_opcodes
[i
].pinfo
!= INSN_MACRO
735 && ((mips_opcodes
[i
].match
& mips_opcodes
[i
].mask
)
736 != mips_opcodes
[i
].match
))
738 fprintf (stderr
, "internal error: bad opcode: `%s' \"%s\"\n",
739 mips_opcodes
[i
].name
, mips_opcodes
[i
].args
);
740 as_fatal ("Broken assembler. No assembly attempted.");
744 while ((i
< NUMOPCODES
) && !strcmp (mips_opcodes
[i
].name
, name
));
747 mips_no_prev_insn ();
755 /* set the default alignment for the text section (2**2) */
756 record_alignment (text_section
, 2);
758 if (USE_GLOBAL_POINTER_OPT
)
759 bfd_set_gp_size (stdoutput
, g_switch_value
);
761 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
763 /* Sections must be aligned to 16 byte boundaries. */
764 (void) bfd_set_section_alignment (stdoutput
, text_section
, 4);
765 (void) bfd_set_section_alignment (stdoutput
, data_section
, 4);
766 (void) bfd_set_section_alignment (stdoutput
, bss_section
, 4);
768 /* Create a .reginfo section for register masks and a .mdebug
769 section for debugging information. */
780 sec
= subseg_new (".reginfo", (subsegT
) 0);
782 /* The ABI says this section should be loaded so that the
783 running program can access it. */
784 (void) bfd_set_section_flags (stdoutput
, sec
,
785 (SEC_ALLOC
| SEC_LOAD
786 | SEC_READONLY
| SEC_DATA
));
787 (void) bfd_set_section_alignment (stdoutput
, sec
, 2);
790 mips_regmask_frag
= frag_more (sizeof (Elf32_External_RegInfo
));
795 /* The 64-bit ABI uses a .MIPS.options section rather than
797 sec
= subseg_new (".MIPS.options", (subsegT
) 0);
798 (void) bfd_set_section_flags (stdoutput
, sec
,
799 (SEC_ALLOC
| SEC_LOAD
800 | SEC_READONLY
| SEC_DATA
));
801 (void) bfd_set_section_alignment (stdoutput
, sec
, 3);
804 /* Set up the option header. */
806 Elf_Internal_Options opthdr
;
809 opthdr
.kind
= ODK_REGINFO
;
810 opthdr
.size
= (sizeof (Elf_External_Options
)
811 + sizeof (Elf64_External_RegInfo
));
814 f
= frag_more (sizeof (Elf_External_Options
));
815 bfd_mips_elf_swap_options_out (stdoutput
, &opthdr
,
816 (Elf_External_Options
*) f
);
818 mips_regmask_frag
= frag_more (sizeof (Elf64_External_RegInfo
));
825 sec
= subseg_new (".mdebug", (subsegT
) 0);
826 (void) bfd_set_section_flags (stdoutput
, sec
,
827 SEC_HAS_CONTENTS
| SEC_READONLY
);
828 (void) bfd_set_section_alignment (stdoutput
, sec
, 2);
831 subseg_set (seg
, subseg
);
835 if (! ECOFF_DEBUGGING
)
842 if (! ECOFF_DEBUGGING
)
850 struct mips_cl_insn insn
;
852 imm_expr
.X_op
= O_absent
;
853 imm_reloc
= BFD_RELOC_UNUSED
;
854 imm_unmatched_hi
= false;
855 offset_expr
.X_op
= O_absent
;
856 offset_reloc
= BFD_RELOC_UNUSED
;
858 mips_ip (str
, &insn
);
861 as_bad ("%s `%s'", insn_error
, str
);
864 if (insn
.insn_mo
->pinfo
== INSN_MACRO
)
870 if (imm_expr
.X_op
!= O_absent
)
871 append_insn ((char *) NULL
, &insn
, &imm_expr
, imm_reloc
,
873 else if (offset_expr
.X_op
!= O_absent
)
874 append_insn ((char *) NULL
, &insn
, &offset_expr
, offset_reloc
, false);
876 append_insn ((char *) NULL
, &insn
, NULL
, BFD_RELOC_UNUSED
, false);
880 /* See whether instruction IP reads register REG. If FPR is non-zero,
881 REG is a floating point register. */
884 insn_uses_reg (ip
, reg
, fpr
)
885 struct mips_cl_insn
*ip
;
889 /* Don't report on general register 0, since it never changes. */
890 if (! fpr
&& reg
== 0)
895 /* If we are called with either $f0 or $f1, we must check $f0.
896 This is not optimal, because it will introduce an unnecessary
897 NOP between "lwc1 $f0" and "swc1 $f1". To fix this we would
898 need to distinguish reading both $f0 and $f1 or just one of
899 them. Note that we don't have to check the other way,
900 because there is no instruction that sets both $f0 and $f1
901 and requires a delay. */
902 if ((ip
->insn_mo
->pinfo
& INSN_READ_FPR_S
)
903 && (((ip
->insn_opcode
>> OP_SH_FS
) & OP_MASK_FS
)
904 == (reg
&~ (unsigned) 1)))
906 if ((ip
->insn_mo
->pinfo
& INSN_READ_FPR_T
)
907 && (((ip
->insn_opcode
>> OP_SH_FT
) & OP_MASK_FT
)
908 == (reg
&~ (unsigned) 1)))
913 if ((ip
->insn_mo
->pinfo
& INSN_READ_GPR_S
)
914 && ((ip
->insn_opcode
>> OP_SH_RS
) & OP_MASK_RS
) == reg
)
916 if ((ip
->insn_mo
->pinfo
& INSN_READ_GPR_T
)
917 && ((ip
->insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
) == reg
)
924 /* This function returns true if modifying a register requires a
928 reg_needs_delay (reg
)
931 unsigned long prev_pinfo
;
933 prev_pinfo
= prev_insn
.insn_mo
->pinfo
;
936 && ((prev_pinfo
& INSN_LOAD_COPROC_DELAY
)
938 && (prev_pinfo
& INSN_LOAD_MEMORY_DELAY
))))
940 /* A load from a coprocessor or from memory. All load
941 delays delay the use of general register rt for one
942 instruction on the r3000. The r6000 and r4000 use
944 know (prev_pinfo
& INSN_WRITE_GPR_T
);
945 if (reg
== ((prev_insn
.insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
))
952 /* Output an instruction. PLACE is where to put the instruction; if
953 it is NULL, this uses frag_more to get room. IP is the instruction
954 information. ADDRESS_EXPR is an operand of the instruction to be
955 used with RELOC_TYPE. */
958 append_insn (place
, ip
, address_expr
, reloc_type
, unmatched_hi
)
960 struct mips_cl_insn
*ip
;
961 expressionS
*address_expr
;
962 bfd_reloc_code_real_type reloc_type
;
963 boolean unmatched_hi
;
965 register unsigned long prev_pinfo
, pinfo
;
970 prev_pinfo
= prev_insn
.insn_mo
->pinfo
;
971 pinfo
= ip
->insn_mo
->pinfo
;
973 if (place
== NULL
&& ! mips_noreorder
)
975 /* If the previous insn required any delay slots, see if we need
976 to insert a NOP or two. There are eight kinds of possible
977 hazards, of which an instruction can have at most one type.
978 (1) a load from memory delay
979 (2) a load from a coprocessor delay
980 (3) an unconditional branch delay
981 (4) a conditional branch delay
982 (5) a move to coprocessor register delay
983 (6) a load coprocessor register from memory delay
984 (7) a coprocessor condition code delay
985 (8) a HI/LO special register delay
987 There are a lot of optimizations we could do that we don't.
988 In particular, we do not, in general, reorder instructions.
989 If you use gcc with optimization, it will reorder
990 instructions and generally do much more optimization then we
991 do here; repeating all that work in the assembler would only
992 benefit hand written assembly code, and does not seem worth
995 /* This is how a NOP is emitted. */
996 #define emit_nop() md_number_to_chars (frag_more (4), 0, 4)
998 /* The previous insn might require a delay slot, depending upon
999 the contents of the current insn. */
1001 && ((prev_pinfo
& INSN_LOAD_COPROC_DELAY
)
1003 && (prev_pinfo
& INSN_LOAD_MEMORY_DELAY
))))
1005 /* A load from a coprocessor or from memory. All load
1006 delays delay the use of general register rt for one
1007 instruction on the r3000. The r6000 and r4000 use
1009 know (prev_pinfo
& INSN_WRITE_GPR_T
);
1010 if (mips_optimize
== 0
1011 || insn_uses_reg (ip
,
1012 ((prev_insn
.insn_opcode
>> OP_SH_RT
)
1017 else if (mips_isa
< 4
1018 && ((prev_pinfo
& INSN_COPROC_MOVE_DELAY
)
1020 && (prev_pinfo
& INSN_COPROC_MEMORY_DELAY
))))
1022 /* A generic coprocessor delay. The previous instruction
1023 modified a coprocessor general or control register. If
1024 it modified a control register, we need to avoid any
1025 coprocessor instruction (this is probably not always
1026 required, but it sometimes is). If it modified a general
1027 register, we avoid using that register.
1029 On the r6000 and r4000 loading a coprocessor register
1030 from memory is interlocked, and does not require a delay.
1032 This case is not handled very well. There is no special
1033 knowledge of CP0 handling, and the coprocessors other
1034 than the floating point unit are not distinguished at
1036 if (prev_pinfo
& INSN_WRITE_FPR_T
)
1038 if (mips_optimize
== 0
1039 || insn_uses_reg (ip
,
1040 ((prev_insn
.insn_opcode
>> OP_SH_FT
)
1045 else if (prev_pinfo
& INSN_WRITE_FPR_S
)
1047 if (mips_optimize
== 0
1048 || insn_uses_reg (ip
,
1049 ((prev_insn
.insn_opcode
>> OP_SH_FS
)
1056 /* We don't know exactly what the previous instruction
1057 does. If the current instruction uses a coprocessor
1058 register, we must insert a NOP. If previous
1059 instruction may set the condition codes, and the
1060 current instruction uses them, we must insert two
1062 if (mips_optimize
== 0
1063 || ((prev_pinfo
& INSN_WRITE_COND_CODE
)
1064 && (pinfo
& INSN_READ_COND_CODE
)))
1066 else if (pinfo
& INSN_COP
)
1070 else if (mips_isa
< 4
1071 && (prev_pinfo
& INSN_WRITE_COND_CODE
))
1073 /* The previous instruction sets the coprocessor condition
1074 codes, but does not require a general coprocessor delay
1075 (this means it is a floating point comparison
1076 instruction). If this instruction uses the condition
1077 codes, we need to insert a single NOP. */
1078 if (mips_optimize
== 0
1079 || (pinfo
& INSN_READ_COND_CODE
))
1082 else if (prev_pinfo
& INSN_READ_LO
)
1084 /* The previous instruction reads the LO register; if the
1085 current instruction writes to the LO register, we must
1086 insert two NOPS. The R4650 and VR4100 have interlocks. */
1088 && (mips_optimize
== 0
1089 || (pinfo
& INSN_WRITE_LO
)))
1092 else if (prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
1094 /* The previous instruction reads the HI register; if the
1095 current instruction writes to the HI register, we must
1096 insert a NOP. The R4650 and VR4100 have interlocks. */
1098 && (mips_optimize
== 0
1099 || (pinfo
& INSN_WRITE_HI
)))
1103 /* There are two cases which require two intervening
1104 instructions: 1) setting the condition codes using a move to
1105 coprocessor instruction which requires a general coprocessor
1106 delay and then reading the condition codes 2) reading the HI
1107 or LO register and then writing to it (except on the R4650,
1108 and VR4100 which have interlocks). If we are not already
1109 emitting a NOP instruction, we must check for these cases
1110 compared to the instruction previous to the previous
1114 && (prev_prev_insn
.insn_mo
->pinfo
& INSN_COPROC_MOVE_DELAY
)
1115 && (prev_prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
)
1116 && (pinfo
& INSN_READ_COND_CODE
))
1117 || ((prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
)
1118 && (pinfo
& INSN_WRITE_LO
)
1120 || ((prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
1121 && (pinfo
& INSN_WRITE_HI
)
1125 /* If we are being given a nop instruction, don't bother with
1126 one of the nops we would otherwise output. This will only
1127 happen when a nop instruction is used with mips_optimize set
1129 if (nops
> 0 && ip
->insn_opcode
== 0)
1132 /* Now emit the right number of NOP instructions. */
1137 for (i
= 0; i
< nops
; i
++)
1141 listing_prev_line ();
1142 /* We may be at the start of a variant frag. In case we
1143 are, make sure there is enough space for the frag
1144 after the frags created by listing_prev_line. The
1145 argument to frag_grow here must be at least as large
1146 as the argument to all other calls to frag_grow in
1147 this file. We don't have to worry about being in the
1148 middle of a variant frag, because the variants insert
1149 all needed nop instructions themselves. */
1152 if (insn_label
!= NULL
)
1154 assert (S_GET_SEGMENT (insn_label
) == now_seg
);
1155 insn_label
->sy_frag
= frag_now
;
1156 S_SET_VALUE (insn_label
, (valueT
) frag_now_fix ());
1166 if (address_expr
!= NULL
)
1168 if (address_expr
->X_op
== O_constant
)
1173 ip
->insn_opcode
|= address_expr
->X_add_number
;
1176 case BFD_RELOC_LO16
:
1177 ip
->insn_opcode
|= address_expr
->X_add_number
& 0xffff;
1180 case BFD_RELOC_MIPS_JMP
:
1181 case BFD_RELOC_16_PCREL_S2
:
1190 assert (reloc_type
!= BFD_RELOC_UNUSED
);
1192 /* Don't generate a reloc if we are writing into a variant
1196 fixp
= fix_new_exp (frag_now
, f
- frag_now
->fr_literal
, 4,
1198 reloc_type
== BFD_RELOC_16_PCREL_S2
,
1202 struct mips_hi_fixup
*hi_fixup
;
1204 assert (reloc_type
== BFD_RELOC_HI16_S
);
1205 hi_fixup
= ((struct mips_hi_fixup
*)
1206 xmalloc (sizeof (struct mips_hi_fixup
)));
1207 hi_fixup
->fixp
= fixp
;
1208 hi_fixup
->seg
= now_seg
;
1209 hi_fixup
->next
= mips_hi_fixup_list
;
1210 mips_hi_fixup_list
= hi_fixup
;
1216 md_number_to_chars (f
, ip
->insn_opcode
, 4);
1218 /* Update the register mask information. */
1219 if (pinfo
& INSN_WRITE_GPR_D
)
1220 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
);
1221 if ((pinfo
& (INSN_WRITE_GPR_T
| INSN_READ_GPR_T
)) != 0)
1222 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
);
1223 if (pinfo
& INSN_READ_GPR_S
)
1224 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> OP_SH_RS
) & OP_MASK_RS
);
1225 if (pinfo
& INSN_WRITE_GPR_31
)
1226 mips_gprmask
|= 1 << 31;
1227 if (pinfo
& INSN_WRITE_FPR_D
)
1228 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FD
) & OP_MASK_FD
);
1229 if ((pinfo
& (INSN_WRITE_FPR_S
| INSN_READ_FPR_S
)) != 0)
1230 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FS
) & OP_MASK_FS
);
1231 if ((pinfo
& (INSN_WRITE_FPR_T
| INSN_READ_FPR_T
)) != 0)
1232 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FT
) & OP_MASK_FT
);
1233 if ((pinfo
& INSN_READ_FPR_R
) != 0)
1234 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FR
) & OP_MASK_FR
);
1235 if (pinfo
& INSN_COP
)
1237 /* We don't keep enough information to sort these cases out. */
1239 /* Never set the bit for $0, which is always zero. */
1240 mips_gprmask
&=~ 1 << 0;
1242 if (place
== NULL
&& ! mips_noreorder
)
1244 /* Filling the branch delay slot is more complex. We try to
1245 switch the branch with the previous instruction, which we can
1246 do if the previous instruction does not set up a condition
1247 that the branch tests and if the branch is not itself the
1248 target of any branch. */
1249 if ((pinfo
& INSN_UNCOND_BRANCH_DELAY
)
1250 || (pinfo
& INSN_COND_BRANCH_DELAY
))
1252 if (mips_optimize
< 2
1253 /* If we have seen .set volatile or .set nomove, don't
1256 /* If we had to emit any NOP instructions, then we
1257 already know we can not swap. */
1259 /* If we don't even know the previous insn, we can not
1261 || ! prev_insn_valid
1262 /* If the previous insn is already in a branch delay
1263 slot, then we can not swap. */
1264 || prev_insn_is_delay_slot
1265 /* If the previous previous insn was in a .set
1266 noreorder, we can't swap. Actually, the MIPS
1267 assembler will swap in this situation. However, gcc
1268 configured -with-gnu-as will generate code like
1274 in which we can not swap the bne and INSN. If gcc is
1275 not configured -with-gnu-as, it does not output the
1276 .set pseudo-ops. We don't have to check
1277 prev_insn_unreordered, because prev_insn_valid will
1278 be 0 in that case. We don't want to use
1279 prev_prev_insn_valid, because we do want to be able
1280 to swap at the start of a function. */
1281 || prev_prev_insn_unreordered
1282 /* If the branch is itself the target of a branch, we
1283 can not swap. We cheat on this; all we check for is
1284 whether there is a label on this instruction. If
1285 there are any branches to anything other than a
1286 label, users must use .set noreorder. */
1287 || insn_label
!= NULL
1288 /* If the previous instruction is in a variant frag, we
1289 can not do the swap. */
1290 || prev_insn_frag
->fr_type
== rs_machine_dependent
1291 /* If the branch reads the condition codes, we don't
1292 even try to swap, because in the sequence
1297 we can not swap, and I don't feel like handling that
1300 && (pinfo
& INSN_READ_COND_CODE
))
1301 /* We can not swap with an instruction that requires a
1302 delay slot, becase the target of the branch might
1303 interfere with that instruction. */
1306 & (INSN_LOAD_COPROC_DELAY
1307 | INSN_COPROC_MOVE_DELAY
1308 | INSN_WRITE_COND_CODE
)))
1315 & (INSN_LOAD_MEMORY_DELAY
1316 | INSN_COPROC_MEMORY_DELAY
)))
1317 /* We can not swap with a branch instruction. */
1319 & (INSN_UNCOND_BRANCH_DELAY
1320 | INSN_COND_BRANCH_DELAY
1321 | INSN_COND_BRANCH_LIKELY
))
1322 /* We do not swap with a trap instruction, since it
1323 complicates trap handlers to have the trap
1324 instruction be in a delay slot. */
1325 || (prev_pinfo
& INSN_TRAP
)
1326 /* If the branch reads a register that the previous
1327 instruction sets, we can not swap. */
1328 || ((prev_pinfo
& INSN_WRITE_GPR_T
)
1329 && insn_uses_reg (ip
,
1330 ((prev_insn
.insn_opcode
>> OP_SH_RT
)
1333 || ((prev_pinfo
& INSN_WRITE_GPR_D
)
1334 && insn_uses_reg (ip
,
1335 ((prev_insn
.insn_opcode
>> OP_SH_RD
)
1338 /* If the branch writes a register that the previous
1339 instruction sets, we can not swap (we know that
1340 branches write only to RD or to $31). */
1341 || ((prev_pinfo
& INSN_WRITE_GPR_T
)
1342 && (((pinfo
& INSN_WRITE_GPR_D
)
1343 && (((prev_insn
.insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
)
1344 == ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)))
1345 || ((pinfo
& INSN_WRITE_GPR_31
)
1346 && (((prev_insn
.insn_opcode
>> OP_SH_RT
)
1349 || ((prev_pinfo
& INSN_WRITE_GPR_D
)
1350 && (((pinfo
& INSN_WRITE_GPR_D
)
1351 && (((prev_insn
.insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)
1352 == ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)))
1353 || ((pinfo
& INSN_WRITE_GPR_31
)
1354 && (((prev_insn
.insn_opcode
>> OP_SH_RD
)
1357 /* If the branch writes a register that the previous
1358 instruction reads, we can not swap (we know that
1359 branches only write to RD or to $31). */
1360 || ((pinfo
& INSN_WRITE_GPR_D
)
1361 && insn_uses_reg (&prev_insn
,
1362 ((ip
->insn_opcode
>> OP_SH_RD
)
1365 || ((pinfo
& INSN_WRITE_GPR_31
)
1366 && insn_uses_reg (&prev_insn
, 31, 0))
1367 /* If we are generating embedded PIC code, the branch
1368 might be expanded into a sequence which uses $at, so
1369 we can't swap with an instruction which reads it. */
1370 || (mips_pic
== EMBEDDED_PIC
1371 && insn_uses_reg (&prev_insn
, AT
, 0))
1372 /* If the previous previous instruction has a load
1373 delay, and sets a register that the branch reads, we
1376 && ((prev_prev_insn
.insn_mo
->pinfo
& INSN_LOAD_COPROC_DELAY
)
1378 && (prev_prev_insn
.insn_mo
->pinfo
1379 & INSN_LOAD_MEMORY_DELAY
)))
1380 && insn_uses_reg (ip
,
1381 ((prev_prev_insn
.insn_opcode
>> OP_SH_RT
)
1385 /* We could do even better for unconditional branches to
1386 portions of this object file; we could pick up the
1387 instruction at the destination, put it in the delay
1388 slot, and bump the destination address. */
1390 /* Update the previous insn information. */
1391 prev_prev_insn
= *ip
;
1392 prev_insn
.insn_mo
= &dummy_opcode
;
1399 /* It looks like we can actually do the swap. */
1400 prev_f
= prev_insn_frag
->fr_literal
+ prev_insn_where
;
1401 memcpy (temp
, prev_f
, 4);
1402 memcpy (prev_f
, f
, 4);
1403 memcpy (f
, temp
, 4);
1406 prev_insn_fixp
->fx_frag
= frag_now
;
1407 prev_insn_fixp
->fx_where
= f
- frag_now
->fr_literal
;
1411 fixp
->fx_frag
= prev_insn_frag
;
1412 fixp
->fx_where
= prev_insn_where
;
1414 /* Update the previous insn information; leave prev_insn
1416 prev_prev_insn
= *ip
;
1418 prev_insn_is_delay_slot
= 1;
1420 /* If that was an unconditional branch, forget the previous
1421 insn information. */
1422 if (pinfo
& INSN_UNCOND_BRANCH_DELAY
)
1424 prev_prev_insn
.insn_mo
= &dummy_opcode
;
1425 prev_insn
.insn_mo
= &dummy_opcode
;
1428 else if (pinfo
& INSN_COND_BRANCH_LIKELY
)
1430 /* We don't yet optimize a branch likely. What we should do
1431 is look at the target, copy the instruction found there
1432 into the delay slot, and increment the branch to jump to
1433 the next instruction. */
1435 /* Update the previous insn information. */
1436 prev_prev_insn
= *ip
;
1437 prev_insn
.insn_mo
= &dummy_opcode
;
1441 /* Update the previous insn information. */
1443 prev_prev_insn
.insn_mo
= &dummy_opcode
;
1445 prev_prev_insn
= prev_insn
;
1448 /* Any time we see a branch, we always fill the delay slot
1449 immediately; since this insn is not a branch, we know it
1450 is not in a delay slot. */
1451 prev_insn_is_delay_slot
= 0;
1454 prev_prev_insn_unreordered
= prev_insn_unreordered
;
1455 prev_insn_unreordered
= 0;
1456 prev_insn_frag
= frag_now
;
1457 prev_insn_where
= f
- frag_now
->fr_literal
;
1458 prev_insn_fixp
= fixp
;
1459 prev_insn_valid
= 1;
1462 /* We just output an insn, so the next one doesn't have a label. */
1466 /* This function forgets that there was any previous instruction or
1470 mips_no_prev_insn ()
1472 prev_insn
.insn_mo
= &dummy_opcode
;
1473 prev_prev_insn
.insn_mo
= &dummy_opcode
;
1474 prev_insn_valid
= 0;
1475 prev_insn_is_delay_slot
= 0;
1476 prev_insn_unreordered
= 0;
1477 prev_prev_insn_unreordered
= 0;
1481 /* This function must be called whenever we turn on noreorder or emit
1482 something other than instructions. It inserts any NOPS which might
1483 be needed by the previous instruction, and clears the information
1484 kept for the previous instructions. */
1489 if (! mips_noreorder
)
1495 && (prev_insn
.insn_mo
->pinfo
1496 & (INSN_LOAD_COPROC_DELAY
1497 | INSN_COPROC_MOVE_DELAY
1498 | INSN_WRITE_COND_CODE
)))
1500 && (prev_insn
.insn_mo
->pinfo
1504 && (prev_insn
.insn_mo
->pinfo
1505 & (INSN_LOAD_MEMORY_DELAY
1506 | INSN_COPROC_MEMORY_DELAY
))))
1510 && (prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
))
1512 && ((prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
1513 || (prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
))))
1516 else if ((mips_isa
< 4
1517 && (prev_prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
))
1519 && ((prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
1520 || (prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
))))
1525 if (insn_label
!= NULL
)
1527 assert (S_GET_SEGMENT (insn_label
) == now_seg
);
1528 insn_label
->sy_frag
= frag_now
;
1529 S_SET_VALUE (insn_label
, (valueT
) frag_now_fix ());
1534 mips_no_prev_insn ();
1537 /* Build an instruction created by a macro expansion. This is passed
1538 a pointer to the count of instructions created so far, an
1539 expression, the name of the instruction to build, an operand format
1540 string, and corresponding arguments. */
1544 macro_build (char *place
,
1552 macro_build (place
, counter
, ep
, name
, fmt
, va_alist
)
1561 struct mips_cl_insn insn
;
1562 bfd_reloc_code_real_type r
;
1566 va_start (args
, fmt
);
1572 * If the macro is about to expand into a second instruction,
1573 * print a warning if needed. We need to pass ip as a parameter
1574 * to generate a better warning message here...
1576 if (mips_warn_about_macros
&& place
== NULL
&& *counter
== 1)
1577 as_warn ("Macro instruction expanded into multiple instructions");
1580 *counter
+= 1; /* bump instruction counter */
1582 r
= BFD_RELOC_UNUSED
;
1583 insn
.insn_mo
= (struct mips_opcode
*) hash_find (op_hash
, name
);
1584 assert (insn
.insn_mo
);
1585 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
1587 while (strcmp (fmt
, insn
.insn_mo
->args
) != 0
1588 || insn
.insn_mo
->pinfo
== INSN_MACRO
1589 || ((insn
.insn_mo
->pinfo
& INSN_ISA
) == INSN_ISA2
1591 || ((insn
.insn_mo
->pinfo
& INSN_ISA
) == INSN_ISA3
1593 || ((insn
.insn_mo
->pinfo
& INSN_ISA
) == INSN_ISA4
1595 || ((insn
.insn_mo
->pinfo
& INSN_ISA
) == INSN_4650
1597 || ((insn
.insn_mo
->pinfo
& INSN_ISA
) == INSN_4010
1599 || ((insn
.insn_mo
->pinfo
& INSN_ISA
) == INSN_4100
1603 assert (insn
.insn_mo
->name
);
1604 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
1606 insn
.insn_opcode
= insn
.insn_mo
->match
;
1622 insn
.insn_opcode
|= va_arg (args
, int) << 16;
1628 insn
.insn_opcode
|= va_arg (args
, int) << 16;
1633 insn
.insn_opcode
|= va_arg (args
, int) << 11;
1638 insn
.insn_opcode
|= va_arg (args
, int) << 11;
1645 insn
.insn_opcode
|= va_arg (args
, int) << 6;
1649 insn
.insn_opcode
|= va_arg (args
, int) << 6;
1653 insn
.insn_opcode
|= va_arg (args
, int) << 6;
1660 insn
.insn_opcode
|= va_arg (args
, int) << 21;
1666 r
= (bfd_reloc_code_real_type
) va_arg (args
, int);
1667 assert (r
== BFD_RELOC_MIPS_GPREL
1668 || r
== BFD_RELOC_MIPS_LITERAL
1669 || r
== BFD_RELOC_LO16
1670 || r
== BFD_RELOC_MIPS_GOT16
1671 || r
== BFD_RELOC_MIPS_CALL16
1672 || r
== BFD_RELOC_MIPS_GOT_LO16
1673 || r
== BFD_RELOC_MIPS_CALL_LO16
1674 || (ep
->X_op
== O_subtract
1675 && now_seg
== text_section
1676 && r
== BFD_RELOC_PCREL_LO16
));
1680 r
= (bfd_reloc_code_real_type
) va_arg (args
, int);
1682 && (ep
->X_op
== O_constant
1683 || (ep
->X_op
== O_symbol
1684 && (r
== BFD_RELOC_HI16_S
1685 || r
== BFD_RELOC_HI16
1686 || r
== BFD_RELOC_MIPS_GOT_HI16
1687 || r
== BFD_RELOC_MIPS_CALL_HI16
))
1688 || (ep
->X_op
== O_subtract
1689 && now_seg
== text_section
1690 && r
== BFD_RELOC_PCREL_HI16_S
)));
1691 if (ep
->X_op
== O_constant
)
1693 insn
.insn_opcode
|= (ep
->X_add_number
>> 16) & 0xffff;
1695 r
= BFD_RELOC_UNUSED
;
1700 assert (ep
!= NULL
);
1702 * This allows macro() to pass an immediate expression for
1703 * creating short branches without creating a symbol.
1704 * Note that the expression still might come from the assembly
1705 * input, in which case the value is not checked for range nor
1706 * is a relocation entry generated (yuck).
1708 if (ep
->X_op
== O_constant
)
1710 insn
.insn_opcode
|= (ep
->X_add_number
>> 2) & 0xffff;
1714 r
= BFD_RELOC_16_PCREL_S2
;
1718 assert (ep
!= NULL
);
1719 r
= BFD_RELOC_MIPS_JMP
;
1728 assert (r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
1730 append_insn (place
, &insn
, ep
, r
, false);
1734 * Generate a "lui" instruction.
1737 macro_build_lui (place
, counter
, ep
, regnum
)
1743 expressionS high_expr
;
1744 struct mips_cl_insn insn
;
1745 bfd_reloc_code_real_type r
;
1746 CONST
char *name
= "lui";
1747 CONST
char *fmt
= "t,u";
1753 high_expr
.X_op
= O_constant
;
1754 high_expr
.X_add_number
= ep
->X_add_number
;
1757 if (high_expr
.X_op
== O_constant
)
1759 /* we can compute the instruction now without a relocation entry */
1760 if (high_expr
.X_add_number
& 0x8000)
1761 high_expr
.X_add_number
+= 0x10000;
1762 high_expr
.X_add_number
=
1763 ((unsigned long) high_expr
.X_add_number
>> 16) & 0xffff;
1764 r
= BFD_RELOC_UNUSED
;
1768 assert (ep
->X_op
== O_symbol
);
1769 /* _gp_disp is a special case, used from s_cpload. */
1770 assert (mips_pic
== NO_PIC
1771 || strcmp (S_GET_NAME (ep
->X_add_symbol
), "_gp_disp") == 0);
1772 r
= BFD_RELOC_HI16_S
;
1776 * If the macro is about to expand into a second instruction,
1777 * print a warning if needed. We need to pass ip as a parameter
1778 * to generate a better warning message here...
1780 if (mips_warn_about_macros
&& place
== NULL
&& *counter
== 1)
1781 as_warn ("Macro instruction expanded into multiple instructions");
1784 *counter
+= 1; /* bump instruction counter */
1786 insn
.insn_mo
= (struct mips_opcode
*) hash_find (op_hash
, name
);
1787 assert (insn
.insn_mo
);
1788 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
1789 assert (strcmp (fmt
, insn
.insn_mo
->args
) == 0);
1791 insn
.insn_opcode
= insn
.insn_mo
->match
| (regnum
<< OP_SH_RT
);
1792 if (r
== BFD_RELOC_UNUSED
)
1794 insn
.insn_opcode
|= high_expr
.X_add_number
;
1795 append_insn (place
, &insn
, NULL
, r
, false);
1798 append_insn (place
, &insn
, &high_expr
, r
, false);
1802 * Generates code to set the $at register to true (one)
1803 * if reg is less than the immediate expression.
1806 set_at (counter
, reg
, unsignedp
)
1811 if (imm_expr
.X_add_number
>= -0x8000 && imm_expr
.X_add_number
< 0x8000)
1812 macro_build ((char *) NULL
, counter
, &imm_expr
,
1813 unsignedp
? "sltiu" : "slti",
1814 "t,r,j", AT
, reg
, (int) BFD_RELOC_LO16
);
1817 load_register (counter
, AT
, &imm_expr
, 0);
1818 macro_build ((char *) NULL
, counter
, NULL
,
1819 unsignedp
? "sltu" : "slt",
1820 "d,v,t", AT
, reg
, AT
);
1824 /* Warn if an expression is not a constant. */
1827 check_absolute_expr (ip
, ex
)
1828 struct mips_cl_insn
*ip
;
1831 if (ex
->X_op
!= O_constant
)
1832 as_warn ("Instruction %s requires absolute expression", ip
->insn_mo
->name
);
1836 * This routine generates the least number of instructions neccessary to load
1837 * an absolute expression value into a register.
1840 load_register (counter
, reg
, ep
, dbl
)
1847 expressionS hi32
, lo32
, tmp
;
1849 if (ep
->X_op
!= O_big
)
1851 assert (ep
->X_op
== O_constant
);
1852 if (ep
->X_add_number
< 0x8000
1853 && (ep
->X_add_number
>= 0
1854 || (ep
->X_add_number
>= -0x8000
1857 || sizeof (ep
->X_add_number
) > 4))))
1859 /* We can handle 16 bit signed values with an addiu to
1860 $zero. No need to ever use daddiu here, since $zero and
1861 the result are always correct in 32 bit mode. */
1862 macro_build ((char *) NULL
, counter
, ep
, "addiu", "t,r,j", reg
, 0,
1863 (int) BFD_RELOC_LO16
);
1866 else if (ep
->X_add_number
>= 0 && ep
->X_add_number
< 0x10000)
1868 /* We can handle 16 bit unsigned values with an ori to
1870 macro_build ((char *) NULL
, counter
, ep
, "ori", "t,r,i", reg
, 0,
1871 (int) BFD_RELOC_LO16
);
1874 else if ((((ep
->X_add_number
&~ (offsetT
) 0x7fffffff) == 0
1875 || ((ep
->X_add_number
&~ (offsetT
) 0x7fffffff)
1876 == ~ (offsetT
) 0x7fffffff))
1879 || sizeof (ep
->X_add_number
) > 4
1880 || (ep
->X_add_number
& 0x80000000) == 0))
1882 && (ep
->X_add_number
&~ 0xffffffff) == 0))
1884 /* 32 bit values require an lui. */
1885 macro_build ((char *) NULL
, counter
, ep
, "lui", "t,u", reg
,
1886 (int) BFD_RELOC_HI16
);
1887 if ((ep
->X_add_number
& 0xffff) != 0)
1888 macro_build ((char *) NULL
, counter
, ep
, "ori", "t,r,i", reg
, reg
,
1889 (int) BFD_RELOC_LO16
);
1894 /* 32 bit value with high bit set being loaded into a 64 bit
1895 register. We can't use lui, because that would
1896 incorrectly set the 32 high bits. */
1897 generic_bignum
[3] = 0;
1898 generic_bignum
[2] = 0;
1899 generic_bignum
[1] = (ep
->X_add_number
>> 16) & 0xffff;
1900 generic_bignum
[0] = ep
->X_add_number
& 0xffff;
1902 tmp
.X_add_number
= 4;
1907 /* The value is larger than 32 bits. */
1911 as_bad ("Number larger than 32 bits");
1912 macro_build ((char *) NULL
, counter
, ep
, "addiu", "t,r,j", reg
, 0,
1913 (int) BFD_RELOC_LO16
);
1917 if (ep
->X_op
!= O_big
)
1921 hi32
.X_add_number
>>= shift
;
1922 hi32
.X_add_number
&= 0xffffffff;
1923 if ((hi32
.X_add_number
& 0x80000000) != 0)
1924 hi32
.X_add_number
|= ~ (offsetT
) 0xffffffff;
1926 lo32
.X_add_number
&= 0xffffffff;
1930 assert (ep
->X_add_number
> 2);
1931 if (ep
->X_add_number
== 3)
1932 generic_bignum
[3] = 0;
1933 else if (ep
->X_add_number
> 4)
1934 as_bad ("Number larger than 64 bits");
1935 lo32
.X_op
= O_constant
;
1936 lo32
.X_add_number
= generic_bignum
[0] + (generic_bignum
[1] << 16);
1937 hi32
.X_op
= O_constant
;
1938 hi32
.X_add_number
= generic_bignum
[2] + (generic_bignum
[3] << 16);
1941 if (hi32
.X_add_number
== 0)
1945 if (hi32
.X_add_number
== 0xffffffff)
1947 if ((lo32
.X_add_number
& 0xffff8000) == 0xffff8000)
1949 macro_build ((char *) NULL
, counter
, &lo32
, "addiu", "t,r,j", reg
, 0,
1950 (int) BFD_RELOC_LO16
);
1953 if (lo32
.X_add_number
& 0x80000000)
1955 macro_build ((char *) NULL
, counter
, &lo32
, "lui", "t,u", reg
,
1956 (int) BFD_RELOC_HI16
);
1957 macro_build ((char *) NULL
, counter
, &lo32
, "ori", "t,r,i", reg
, reg
,
1958 (int) BFD_RELOC_LO16
);
1962 load_register (counter
, reg
, &hi32
, 0);
1965 if ((lo32
.X_add_number
& 0xffff0000) == 0)
1969 macro_build ((char *) NULL
, counter
, NULL
, "dsll32", "d,w,<", reg
,
1978 if ((freg
== 0) && (lo32
.X_add_number
== 0xffffffff))
1980 macro_build ((char *) NULL
, counter
, &lo32
, "lui", "t,u", reg
,
1981 (int) BFD_RELOC_HI16
);
1982 macro_build ((char *) NULL
, counter
, NULL
, "dsrl32", "d,w,<", reg
,
1989 macro_build ((char *) NULL
, counter
, NULL
, "dsll", "d,w,<", reg
,
1994 mid16
.X_add_number
>>= 16;
1995 macro_build ((char *) NULL
, counter
, &mid16
, "ori", "t,r,i", reg
,
1996 freg
, (int) BFD_RELOC_LO16
);
1997 macro_build ((char *) NULL
, counter
, NULL
, "dsll", "d,w,<", reg
,
2001 if ((lo32
.X_add_number
& 0xffff) != 0)
2002 macro_build ((char *) NULL
, counter
, &lo32
, "ori", "t,r,i", reg
, freg
,
2003 (int) BFD_RELOC_LO16
);
2006 /* Load an address into a register. */
2009 load_address (counter
, reg
, ep
)
2016 if (ep
->X_op
!= O_constant
2017 && ep
->X_op
!= O_symbol
)
2019 as_bad ("expression too complex");
2020 ep
->X_op
= O_constant
;
2023 if (ep
->X_op
== O_constant
)
2025 load_register (counter
, reg
, ep
, 0);
2029 if (mips_pic
== NO_PIC
)
2031 /* If this is a reference to a GP relative symbol, we want
2032 addiu $reg,$gp,<sym> (BFD_RELOC_MIPS_GPREL)
2034 lui $reg,<sym> (BFD_RELOC_HI16_S)
2035 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
2036 If we have an addend, we always use the latter form. */
2037 if ((valueT
) ep
->X_add_number
>= MAX_GPREL_OFFSET
2038 || nopic_need_relax (ep
->X_add_symbol
))
2043 macro_build ((char *) NULL
, counter
, ep
,
2044 mips_isa
< 3 ? "addiu" : "daddiu",
2045 "t,r,j", reg
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
2046 p
= frag_var (rs_machine_dependent
, 8, 0,
2047 RELAX_ENCODE (4, 8, 0, 4, 0, mips_warn_about_macros
),
2048 ep
->X_add_symbol
, (long) 0, (char *) NULL
);
2050 macro_build_lui (p
, counter
, ep
, reg
);
2053 macro_build (p
, counter
, ep
,
2054 mips_isa
< 3 ? "addiu" : "daddiu",
2055 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
2057 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
2061 /* If this is a reference to an external symbol, we want
2062 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
2064 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
2066 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
2067 If there is a constant, it must be added in after. */
2068 ex
.X_add_number
= ep
->X_add_number
;
2069 ep
->X_add_number
= 0;
2071 macro_build ((char *) NULL
, counter
, ep
,
2072 mips_isa
< 3 ? "lw" : "ld",
2073 "t,o(b)", reg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
2074 macro_build ((char *) NULL
, counter
, (expressionS
*) NULL
, "nop", "");
2075 p
= frag_var (rs_machine_dependent
, 4, 0,
2076 RELAX_ENCODE (0, 4, -8, 0, 0, mips_warn_about_macros
),
2077 ep
->X_add_symbol
, (long) 0, (char *) NULL
);
2078 macro_build (p
, counter
, ep
,
2079 mips_isa
< 3 ? "addiu" : "daddiu",
2080 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
2081 if (ex
.X_add_number
!= 0)
2083 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
2084 as_bad ("PIC code offset overflow (max 16 signed bits)");
2085 ex
.X_op
= O_constant
;
2086 macro_build ((char *) NULL
, counter
, &ex
,
2087 mips_isa
< 3 ? "addiu" : "daddiu",
2088 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
2091 else if (mips_pic
== SVR4_PIC
)
2096 /* This is the large GOT case. If this is a reference to an
2097 external symbol, we want
2098 lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
2100 lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16)
2101 Otherwise, for a reference to a local symbol, we want
2102 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
2104 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
2105 If there is a constant, it must be added in after. */
2106 ex
.X_add_number
= ep
->X_add_number
;
2107 ep
->X_add_number
= 0;
2108 if (reg_needs_delay (GP
))
2113 macro_build ((char *) NULL
, counter
, ep
, "lui", "t,u", reg
,
2114 (int) BFD_RELOC_MIPS_GOT_HI16
);
2115 macro_build ((char *) NULL
, counter
, (expressionS
*) NULL
,
2116 mips_isa
< 3 ? "addu" : "daddu",
2117 "d,v,t", reg
, reg
, GP
);
2118 macro_build ((char *) NULL
, counter
, ep
,
2119 mips_isa
< 3 ? "lw" : "ld",
2120 "t,o(b)", reg
, (int) BFD_RELOC_MIPS_GOT_LO16
, reg
);
2121 p
= frag_var (rs_machine_dependent
, 12 + off
, 0,
2122 RELAX_ENCODE (12, 12 + off
, off
, 8 + off
, 0,
2123 mips_warn_about_macros
),
2124 ep
->X_add_symbol
, (long) 0, (char *) NULL
);
2127 /* We need a nop before loading from $gp. This special
2128 check is required because the lui which starts the main
2129 instruction stream does not refer to $gp, and so will not
2130 insert the nop which may be required. */
2131 macro_build (p
, counter
, (expressionS
*) NULL
, "nop", "");
2134 macro_build (p
, counter
, ep
,
2135 mips_isa
< 3 ? "lw" : "ld",
2136 "t,o(b)", reg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
2138 macro_build (p
, counter
, (expressionS
*) NULL
, "nop", "");
2140 macro_build (p
, counter
, ep
,
2141 mips_isa
< 3 ? "addiu" : "daddiu",
2142 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
2143 if (ex
.X_add_number
!= 0)
2145 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
2146 as_bad ("PIC code offset overflow (max 16 signed bits)");
2147 ex
.X_op
= O_constant
;
2148 macro_build ((char *) NULL
, counter
, &ex
,
2149 mips_isa
< 3 ? "addiu" : "daddiu",
2150 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
2153 else if (mips_pic
== EMBEDDED_PIC
)
2156 addiu $reg,$gp,<sym> (BFD_RELOC_MIPS_GPREL)
2158 macro_build ((char *) NULL
, counter
, ep
,
2159 mips_isa
< 3 ? "addiu" : "daddiu",
2160 "t,r,j", reg
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
2168 * This routine implements the seemingly endless macro or synthesized
2169 * instructions and addressing modes in the mips assembly language. Many
2170 * of these macros are simple and are similar to each other. These could
2171 * probably be handled by some kind of table or grammer aproach instead of
2172 * this verbose method. Others are not simple macros but are more like
2173 * optimizing code generation.
2174 * One interesting optimization is when several store macros appear
2175 * consecutivly that would load AT with the upper half of the same address.
2176 * The ensuing load upper instructions are ommited. This implies some kind
2177 * of global optimization. We currently only optimize within a single macro.
2178 * For many of the load and store macros if the address is specified as a
2179 * constant expression in the first 64k of memory (ie ld $2,0x4000c) we
2180 * first load register 'at' with zero and use it as the base register. The
2181 * mips assembler simply uses register $zero. Just one tiny optimization
2186 struct mips_cl_insn
*ip
;
2188 register int treg
, sreg
, dreg
, breg
;
2203 bfd_reloc_code_real_type r
;
2205 int hold_mips_optimize
;
2207 treg
= (ip
->insn_opcode
>> 16) & 0x1f;
2208 dreg
= (ip
->insn_opcode
>> 11) & 0x1f;
2209 sreg
= breg
= (ip
->insn_opcode
>> 21) & 0x1f;
2210 mask
= ip
->insn_mo
->mask
;
2212 expr1
.X_op
= O_constant
;
2213 expr1
.X_op_symbol
= NULL
;
2214 expr1
.X_add_symbol
= NULL
;
2215 expr1
.X_add_number
= 1;
2227 mips_emit_delays ();
2229 mips_any_noreorder
= 1;
2231 expr1
.X_add_number
= 8;
2232 macro_build ((char *) NULL
, &icnt
, &expr1
, "bgez", "s,p", sreg
);
2234 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
2236 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
, sreg
, 0);
2237 macro_build ((char *) NULL
, &icnt
, NULL
,
2238 dbl
? "dsub" : "sub",
2239 "d,v,t", dreg
, 0, sreg
);
2262 if (imm_expr
.X_add_number
>= -0x8000 && imm_expr
.X_add_number
< 0x8000)
2264 macro_build ((char *) NULL
, &icnt
, &imm_expr
, s
, "t,r,j", treg
, sreg
,
2265 (int) BFD_RELOC_LO16
);
2268 load_register (&icnt
, AT
, &imm_expr
, dbl
);
2269 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "d,v,t", treg
, sreg
, AT
);
2288 if (imm_expr
.X_add_number
>= 0 && imm_expr
.X_add_number
< 0x10000)
2290 if (mask
!= M_NOR_I
)
2291 macro_build ((char *) NULL
, &icnt
, &imm_expr
, s
, "t,r,i", treg
,
2292 sreg
, (int) BFD_RELOC_LO16
);
2295 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "ori", "t,r,i",
2296 treg
, sreg
, (int) BFD_RELOC_LO16
);
2297 macro_build ((char *) NULL
, &icnt
, NULL
, "nor", "d,v,t",
2303 load_register (&icnt
, AT
, &imm_expr
, 0);
2304 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "d,v,t", treg
, sreg
, AT
);
2321 if (imm_expr
.X_add_number
== 0)
2323 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "s,t,p", sreg
,
2327 load_register (&icnt
, AT
, &imm_expr
, 0);
2328 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "s,t,p", sreg
, AT
);
2336 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2337 likely
? "bgezl" : "bgez",
2343 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2344 likely
? "blezl" : "blez",
2348 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", AT
, sreg
, treg
);
2349 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2350 likely
? "beql" : "beq",
2357 /* check for > max integer */
2358 maxnum
= 0x7fffffff;
2366 if (imm_expr
.X_add_number
>= maxnum
2367 && (mips_isa
< 3 || sizeof (maxnum
) > 4))
2370 /* result is always false */
2373 as_warn ("Branch %s is always false (nop)", ip
->insn_mo
->name
);
2374 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
2378 as_warn ("Branch likely %s is always false", ip
->insn_mo
->name
);
2379 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "bnel",
2384 imm_expr
.X_add_number
++;
2388 if (mask
== M_BGEL_I
)
2390 if (imm_expr
.X_add_number
== 0)
2392 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2393 likely
? "bgezl" : "bgez",
2397 if (imm_expr
.X_add_number
== 1)
2399 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2400 likely
? "bgtzl" : "bgtz",
2404 maxnum
= 0x7fffffff;
2412 maxnum
= - maxnum
- 1;
2413 if (imm_expr
.X_add_number
<= maxnum
2414 && (mips_isa
< 3 || sizeof (maxnum
) > 4))
2417 /* result is always true */
2418 as_warn ("Branch %s is always true", ip
->insn_mo
->name
);
2419 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "b", "p");
2422 set_at (&icnt
, sreg
, 0);
2423 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2424 likely
? "beql" : "beq",
2435 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2436 likely
? "beql" : "beq",
2440 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", AT
, sreg
,
2442 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2443 likely
? "beql" : "beq",
2450 if (sreg
== 0 || imm_expr
.X_add_number
== -1)
2452 imm_expr
.X_add_number
++;
2456 if (mask
== M_BGEUL_I
)
2458 if (imm_expr
.X_add_number
== 0)
2460 if (imm_expr
.X_add_number
== 1)
2462 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2463 likely
? "bnel" : "bne",
2467 set_at (&icnt
, sreg
, 1);
2468 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2469 likely
? "beql" : "beq",
2478 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2479 likely
? "bgtzl" : "bgtz",
2485 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2486 likely
? "bltzl" : "bltz",
2490 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", AT
, treg
, sreg
);
2491 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2492 likely
? "bnel" : "bne",
2501 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2502 likely
? "bnel" : "bne",
2508 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", AT
, treg
,
2510 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2511 likely
? "bnel" : "bne",
2520 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2521 likely
? "blezl" : "blez",
2527 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2528 likely
? "bgezl" : "bgez",
2532 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", AT
, treg
, sreg
);
2533 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2534 likely
? "beql" : "beq",
2541 maxnum
= 0x7fffffff;
2549 if (imm_expr
.X_add_number
>= maxnum
2550 && (mips_isa
< 3 || sizeof (maxnum
) > 4))
2552 imm_expr
.X_add_number
++;
2556 if (mask
== M_BLTL_I
)
2558 if (imm_expr
.X_add_number
== 0)
2560 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2561 likely
? "bltzl" : "bltz",
2565 if (imm_expr
.X_add_number
== 1)
2567 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2568 likely
? "blezl" : "blez",
2572 set_at (&icnt
, sreg
, 0);
2573 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2574 likely
? "bnel" : "bne",
2583 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2584 likely
? "beql" : "beq",
2590 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", AT
, treg
,
2592 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2593 likely
? "beql" : "beq",
2600 if (sreg
== 0 || imm_expr
.X_add_number
== -1)
2602 imm_expr
.X_add_number
++;
2606 if (mask
== M_BLTUL_I
)
2608 if (imm_expr
.X_add_number
== 0)
2610 if (imm_expr
.X_add_number
== 1)
2612 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2613 likely
? "beql" : "beq",
2617 set_at (&icnt
, sreg
, 1);
2618 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2619 likely
? "bnel" : "bne",
2628 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2629 likely
? "bltzl" : "bltz",
2635 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2636 likely
? "bgtzl" : "bgtz",
2640 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", AT
, sreg
, treg
);
2641 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2642 likely
? "bnel" : "bne",
2653 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2654 likely
? "bnel" : "bne",
2658 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", AT
, sreg
,
2660 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2661 likely
? "bnel" : "bne",
2677 as_warn ("Divide by zero.");
2679 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", 0, 0);
2681 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 7);
2685 mips_emit_delays ();
2687 mips_any_noreorder
= 1;
2688 macro_build ((char *) NULL
, &icnt
, NULL
,
2689 dbl
? "ddiv" : "div",
2690 "z,s,t", sreg
, treg
);
2692 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", treg
, 0);
2695 expr1
.X_add_number
= 8;
2696 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", treg
, 0);
2697 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
2698 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 7);
2700 expr1
.X_add_number
= -1;
2701 macro_build ((char *) NULL
, &icnt
, &expr1
,
2702 dbl
? "daddiu" : "addiu",
2703 "t,r,j", AT
, 0, (int) BFD_RELOC_LO16
);
2704 expr1
.X_add_number
= mips_trap
? (dbl
? 12 : 8) : (dbl
? 20 : 16);
2705 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", treg
, AT
);
2708 expr1
.X_add_number
= 1;
2709 macro_build ((char *) NULL
, &icnt
, &expr1
, "daddiu", "t,r,j", AT
, 0,
2710 (int) BFD_RELOC_LO16
);
2711 macro_build ((char *) NULL
, &icnt
, NULL
, "dsll32", "d,w,<", AT
, AT
,
2716 expr1
.X_add_number
= 0x80000000;
2717 macro_build ((char *) NULL
, &icnt
, &expr1
, "lui", "t,u", AT
,
2718 (int) BFD_RELOC_HI16
);
2721 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", sreg
, AT
);
2724 expr1
.X_add_number
= 8;
2725 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", sreg
, AT
);
2726 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
2727 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 6);
2730 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d", dreg
);
2769 if (imm_expr
.X_add_number
== 0)
2771 as_warn ("Divide by zero.");
2773 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", 0, 0);
2775 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 7);
2778 if (imm_expr
.X_add_number
== 1)
2780 if (strcmp (s2
, "mflo") == 0)
2781 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
,
2784 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
, 0);
2787 if (imm_expr
.X_add_number
== -1
2788 && s
[strlen (s
) - 1] != 'u')
2790 if (strcmp (s2
, "mflo") == 0)
2793 macro_build ((char *) NULL
, &icnt
, NULL
, "dneg", "d,w", dreg
,
2796 macro_build ((char *) NULL
, &icnt
, NULL
, "neg", "d,w", dreg
,
2800 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
, 0);
2804 load_register (&icnt
, AT
, &imm_expr
, dbl
);
2805 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "z,s,t", sreg
, AT
);
2806 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "d", dreg
);
2825 mips_emit_delays ();
2827 mips_any_noreorder
= 1;
2828 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "z,s,t", sreg
, treg
);
2830 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", treg
, 0);
2833 expr1
.X_add_number
= 8;
2834 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", treg
, 0);
2835 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
2836 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 7);
2839 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "d", dreg
);
2845 /* Load the address of a symbol into a register. If breg is not
2846 zero, we then add a base register to it. */
2848 /* When generating embedded PIC code, we permit expressions of
2851 where bar is an address in the .text section. These are used
2852 when getting the addresses of functions. We don't permit
2853 X_add_number to be non-zero, because if the symbol is
2854 external the relaxing code needs to know that any addend is
2855 purely the offset to X_op_symbol. */
2856 if (mips_pic
== EMBEDDED_PIC
2857 && offset_expr
.X_op
== O_subtract
2858 && now_seg
== text_section
2859 && (offset_expr
.X_op_symbol
->sy_value
.X_op
== O_constant
2860 ? S_GET_SEGMENT (offset_expr
.X_op_symbol
) == text_section
2861 : (offset_expr
.X_op_symbol
->sy_value
.X_op
== O_symbol
2862 && (S_GET_SEGMENT (offset_expr
.X_op_symbol
2863 ->sy_value
.X_add_symbol
)
2866 && offset_expr
.X_add_number
== 0)
2868 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
2869 treg
, (int) BFD_RELOC_PCREL_HI16_S
);
2870 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2871 mips_isa
< 3 ? "addiu" : "daddiu",
2872 "t,r,j", treg
, treg
, (int) BFD_RELOC_PCREL_LO16
);
2876 if (offset_expr
.X_op
!= O_symbol
2877 && offset_expr
.X_op
!= O_constant
)
2879 as_bad ("expression too complex");
2880 offset_expr
.X_op
= O_constant
;
2894 if (offset_expr
.X_op
== O_constant
)
2895 load_register (&icnt
, tempreg
, &offset_expr
, dbl
);
2896 else if (mips_pic
== NO_PIC
)
2898 /* If this is a reference to an GP relative symbol, we want
2899 addiu $tempreg,$gp,<sym> (BFD_RELOC_MIPS_GPREL)
2901 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
2902 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
2903 If we have a constant, we need two instructions anyhow,
2904 so we may as well always use the latter form. */
2905 if ((valueT
) offset_expr
.X_add_number
>= MAX_GPREL_OFFSET
2906 || nopic_need_relax (offset_expr
.X_add_symbol
))
2911 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2912 mips_isa
< 3 ? "addiu" : "daddiu",
2913 "t,r,j", tempreg
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
2914 p
= frag_var (rs_machine_dependent
, 8, 0,
2915 RELAX_ENCODE (4, 8, 0, 4, 0,
2916 mips_warn_about_macros
),
2917 offset_expr
.X_add_symbol
, (long) 0,
2920 macro_build_lui (p
, &icnt
, &offset_expr
, tempreg
);
2923 macro_build (p
, &icnt
, &offset_expr
,
2924 mips_isa
< 3 ? "addiu" : "daddiu",
2925 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
2927 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
2929 /* If this is a reference to an external symbol, and there
2930 is no constant, we want
2931 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
2932 For a local symbol, we want
2933 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
2935 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
2937 If we have a small constant, and this is a reference to
2938 an external symbol, we want
2939 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
2941 addiu $tempreg,$tempreg,<constant>
2942 For a local symbol, we want the same instruction
2943 sequence, but we output a BFD_RELOC_LO16 reloc on the
2946 If we have a large constant, and this is a reference to
2947 an external symbol, we want
2948 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
2949 lui $at,<hiconstant>
2950 addiu $at,$at,<loconstant>
2951 addu $tempreg,$tempreg,$at
2952 For a local symbol, we want the same instruction
2953 sequence, but we output a BFD_RELOC_LO16 reloc on the
2954 addiu instruction. */
2955 expr1
.X_add_number
= offset_expr
.X_add_number
;
2956 offset_expr
.X_add_number
= 0;
2958 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2960 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
2961 if (expr1
.X_add_number
== 0)
2969 /* We're going to put in an addu instruction using
2970 tempreg, so we may as well insert the nop right
2972 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
2976 p
= frag_var (rs_machine_dependent
, 8 - off
, 0,
2977 RELAX_ENCODE (0, 8 - off
, -4 - off
, 4 - off
, 0,
2979 ? mips_warn_about_macros
2981 offset_expr
.X_add_symbol
, (long) 0,
2985 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
2988 macro_build (p
, &icnt
, &expr1
,
2989 mips_isa
< 3 ? "addiu" : "daddiu",
2990 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
2991 /* FIXME: If breg == 0, and the next instruction uses
2992 $tempreg, then if this variant case is used an extra
2993 nop will be generated. */
2995 else if (expr1
.X_add_number
>= -0x8000
2996 && expr1
.X_add_number
< 0x8000)
2998 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3000 macro_build ((char *) NULL
, &icnt
, &expr1
,
3001 mips_isa
< 3 ? "addiu" : "daddiu",
3002 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
3003 (void) frag_var (rs_machine_dependent
, 0, 0,
3004 RELAX_ENCODE (0, 0, -12, -4, 0, 0),
3005 offset_expr
.X_add_symbol
, (long) 0,
3012 /* If we are going to add in a base register, and the
3013 target register and the base register are the same,
3014 then we are using AT as a temporary register. Since
3015 we want to load the constant into AT, we add our
3016 current AT (from the global offset table) and the
3017 register into the register now, and pretend we were
3018 not using a base register. */
3023 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3025 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3026 mips_isa
< 3 ? "addu" : "daddu",
3027 "d,v,t", treg
, AT
, breg
);
3033 /* Set mips_optimize around the lui instruction to avoid
3034 inserting an unnecessary nop after the lw. */
3035 hold_mips_optimize
= mips_optimize
;
3037 macro_build_lui ((char *) NULL
, &icnt
, &expr1
, AT
);
3038 mips_optimize
= hold_mips_optimize
;
3040 macro_build ((char *) NULL
, &icnt
, &expr1
,
3041 mips_isa
< 3 ? "addiu" : "daddiu",
3042 "t,r,j", AT
, AT
, (int) BFD_RELOC_LO16
);
3043 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3044 mips_isa
< 3 ? "addu" : "daddu",
3045 "d,v,t", tempreg
, tempreg
, AT
);
3046 (void) frag_var (rs_machine_dependent
, 0, 0,
3047 RELAX_ENCODE (0, 0, -16 + off1
, -8, 0, 0),
3048 offset_expr
.X_add_symbol
, (long) 0,
3053 else if (mips_pic
== SVR4_PIC
)
3057 /* This is the large GOT case. If this is a reference to an
3058 external symbol, and there is no constant, we want
3059 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
3060 addu $tempreg,$tempreg,$gp
3061 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
3062 For a local symbol, we want
3063 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3065 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
3067 If we have a small constant, and this is a reference to
3068 an external symbol, we want
3069 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
3070 addu $tempreg,$tempreg,$gp
3071 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
3073 addiu $tempreg,$tempreg,<constant>
3074 For a local symbol, we want
3075 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3077 addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16)
3079 If we have a large constant, and this is a reference to
3080 an external symbol, we want
3081 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
3082 addu $tempreg,$tempreg,$gp
3083 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
3084 lui $at,<hiconstant>
3085 addiu $at,$at,<loconstant>
3086 addu $tempreg,$tempreg,$at
3087 For a local symbol, we want
3088 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3089 lui $at,<hiconstant>
3090 addiu $at,$at,<loconstant> (BFD_RELOC_LO16)
3091 addu $tempreg,$tempreg,$at
3093 expr1
.X_add_number
= offset_expr
.X_add_number
;
3094 offset_expr
.X_add_number
= 0;
3096 if (reg_needs_delay (GP
))
3100 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
3101 tempreg
, (int) BFD_RELOC_MIPS_GOT_HI16
);
3102 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3103 mips_isa
< 3 ? "addu" : "daddu",
3104 "d,v,t", tempreg
, tempreg
, GP
);
3105 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3107 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT_LO16
,
3109 if (expr1
.X_add_number
== 0)
3117 /* We're going to put in an addu instruction using
3118 tempreg, so we may as well insert the nop right
3120 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3125 p
= frag_var (rs_machine_dependent
, 12 + gpdel
, 0,
3126 RELAX_ENCODE (12 + off
, 12 + gpdel
, gpdel
,
3129 ? mips_warn_about_macros
3131 offset_expr
.X_add_symbol
, (long) 0,
3134 else if (expr1
.X_add_number
>= -0x8000
3135 && expr1
.X_add_number
< 0x8000)
3137 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3139 macro_build ((char *) NULL
, &icnt
, &expr1
,
3140 mips_isa
< 3 ? "addiu" : "daddiu",
3141 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
3143 p
= frag_var (rs_machine_dependent
, 12 + gpdel
, 0,
3144 RELAX_ENCODE (20, 12 + gpdel
, gpdel
, 8 + gpdel
, 0,
3146 ? mips_warn_about_macros
3148 offset_expr
.X_add_symbol
, (long) 0,
3155 /* If we are going to add in a base register, and the
3156 target register and the base register are the same,
3157 then we are using AT as a temporary register. Since
3158 we want to load the constant into AT, we add our
3159 current AT (from the global offset table) and the
3160 register into the register now, and pretend we were
3161 not using a base register. */
3169 assert (tempreg
== AT
);
3170 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3172 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3173 mips_isa
< 3 ? "addu" : "daddu",
3174 "d,v,t", treg
, AT
, breg
);
3179 /* Set mips_optimize around the lui instruction to avoid
3180 inserting an unnecessary nop after the lw. */
3181 hold_mips_optimize
= mips_optimize
;
3183 macro_build_lui ((char *) NULL
, &icnt
, &expr1
, AT
);
3184 mips_optimize
= hold_mips_optimize
;
3186 macro_build ((char *) NULL
, &icnt
, &expr1
,
3187 mips_isa
< 3 ? "addiu" : "daddiu",
3188 "t,r,j", AT
, AT
, (int) BFD_RELOC_LO16
);
3189 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3190 mips_isa
< 3 ? "addu" : "daddu",
3191 "d,v,t", dreg
, dreg
, AT
);
3193 p
= frag_var (rs_machine_dependent
, 16 + gpdel
+ adj
, 0,
3194 RELAX_ENCODE (24 + adj
, 16 + gpdel
+ adj
, gpdel
,
3197 ? mips_warn_about_macros
3199 offset_expr
.X_add_symbol
, (long) 0,
3207 /* This is needed because this instruction uses $gp, but
3208 the first instruction on the main stream does not. */
3209 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
3212 macro_build (p
, &icnt
, &offset_expr
,
3214 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
3216 if (expr1
.X_add_number
>= -0x8000
3217 && expr1
.X_add_number
< 0x8000)
3219 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
3221 macro_build (p
, &icnt
, &expr1
,
3222 mips_isa
< 3 ? "addiu" : "daddiu",
3223 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
3224 /* FIXME: If add_number is 0, and there was no base
3225 register, the external symbol case ended with a load,
3226 so if the symbol turns out to not be external, and
3227 the next instruction uses tempreg, an unnecessary nop
3228 will be inserted. */
3234 /* We must add in the base register now, as in the
3235 external symbol case. */
3236 assert (tempreg
== AT
);
3237 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
3239 macro_build (p
, &icnt
, (expressionS
*) NULL
,
3240 mips_isa
< 3 ? "addu" : "daddu",
3241 "d,v,t", treg
, AT
, breg
);
3244 /* We set breg to 0 because we have arranged to add
3245 it in in both cases. */
3249 macro_build_lui (p
, &icnt
, &expr1
, AT
);
3251 macro_build (p
, &icnt
, &expr1
,
3252 mips_isa
< 3 ? "addiu" : "daddiu",
3253 "t,r,j", AT
, AT
, (int) BFD_RELOC_LO16
);
3255 macro_build (p
, &icnt
, (expressionS
*) NULL
,
3256 mips_isa
< 3 ? "addu" : "daddu",
3257 "d,v,t", tempreg
, tempreg
, AT
);
3261 else if (mips_pic
== EMBEDDED_PIC
)
3264 addiu $tempreg,$gp,<sym> (BFD_RELOC_MIPS_GPREL)
3266 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3267 mips_isa
< 3 ? "addiu" : "daddiu",
3268 "t,r,j", tempreg
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
3274 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3275 mips_isa
< 3 ? "addu" : "daddu",
3276 "d,v,t", treg
, tempreg
, breg
);
3284 /* The j instruction may not be used in PIC code, since it
3285 requires an absolute address. We convert it to a b
3287 if (mips_pic
== NO_PIC
)
3288 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "j", "a");
3290 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "b", "p");
3293 /* The jal instructions must be handled as macros because when
3294 generating PIC code they expand to multi-instruction
3295 sequences. Normally they are simple instructions. */
3300 if (mips_pic
== NO_PIC
3301 || mips_pic
== EMBEDDED_PIC
)
3302 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "jalr",
3304 else if (mips_pic
== SVR4_PIC
)
3306 if (sreg
!= PIC_CALL_REG
)
3307 as_warn ("MIPS PIC call to register other than $25");
3309 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "jalr",
3311 if (mips_cprestore_offset
< 0)
3312 as_warn ("No .cprestore pseudo-op used in PIC code");
3315 expr1
.X_add_number
= mips_cprestore_offset
;
3316 macro_build ((char *) NULL
, &icnt
, &expr1
,
3317 mips_isa
< 3 ? "lw" : "ld",
3318 "t,o(b)", GP
, (int) BFD_RELOC_LO16
, mips_frame_reg
);
3327 if (mips_pic
== NO_PIC
)
3328 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "jal", "a");
3329 else if (mips_pic
== SVR4_PIC
)
3331 /* If this is a reference to an external symbol, and we are
3332 using a small GOT, we want
3333 lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
3337 lw $gp,cprestore($sp)
3338 The cprestore value is set using the .cprestore
3339 pseudo-op. If we are using a big GOT, we want
3340 lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16)
3342 lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16)
3346 lw $gp,cprestore($sp)
3347 If the symbol is not external, we want
3348 lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3350 addiu $25,$25,<sym> (BFD_RELOC_LO16)
3353 lw $gp,cprestore($sp) */
3357 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3358 mips_isa
< 3 ? "lw" : "ld",
3359 "t,o(b)", PIC_CALL_REG
,
3360 (int) BFD_RELOC_MIPS_CALL16
, GP
);
3361 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3363 p
= frag_var (rs_machine_dependent
, 4, 0,
3364 RELAX_ENCODE (0, 4, -8, 0, 0, 0),
3365 offset_expr
.X_add_symbol
, (long) 0, (char *) NULL
);
3371 if (reg_needs_delay (GP
))
3375 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
3376 PIC_CALL_REG
, (int) BFD_RELOC_MIPS_CALL_HI16
);
3377 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3378 mips_isa
< 3 ? "addu" : "daddu",
3379 "d,v,t", PIC_CALL_REG
, PIC_CALL_REG
, GP
);
3380 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3381 mips_isa
< 3 ? "lw" : "ld",
3382 "t,o(b)", PIC_CALL_REG
,
3383 (int) BFD_RELOC_MIPS_CALL_LO16
, PIC_CALL_REG
);
3384 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3386 p
= frag_var (rs_machine_dependent
, 12 + gpdel
, 0,
3387 RELAX_ENCODE (16, 12 + gpdel
, gpdel
, 8 + gpdel
,
3389 offset_expr
.X_add_symbol
, (long) 0, (char *) NULL
);
3392 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
3395 macro_build (p
, &icnt
, &offset_expr
,
3396 mips_isa
< 3 ? "lw" : "ld",
3397 "t,o(b)", PIC_CALL_REG
,
3398 (int) BFD_RELOC_MIPS_GOT16
, GP
);
3400 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
3403 macro_build (p
, &icnt
, &offset_expr
,
3404 mips_isa
< 3 ? "addiu" : "daddiu",
3405 "t,r,j", PIC_CALL_REG
, PIC_CALL_REG
,
3406 (int) BFD_RELOC_LO16
);
3407 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3408 "jalr", "s", PIC_CALL_REG
);
3409 if (mips_cprestore_offset
< 0)
3410 as_warn ("No .cprestore pseudo-op used in PIC code");
3414 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3416 expr1
.X_add_number
= mips_cprestore_offset
;
3417 macro_build ((char *) NULL
, &icnt
, &expr1
,
3418 mips_isa
< 3 ? "lw" : "ld",
3419 "t,o(b)", GP
, (int) BFD_RELOC_LO16
,
3423 else if (mips_pic
== EMBEDDED_PIC
)
3425 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "bal", "p");
3426 /* The linker may expand the call to a longer sequence which
3427 uses $at, so we must break rather than return. */
3503 if (breg
== treg
|| coproc
|| lr
)
3572 if (mask
== M_LWC1_AB
3573 || mask
== M_SWC1_AB
3574 || mask
== M_LDC1_AB
3575 || mask
== M_SDC1_AB
3584 if (offset_expr
.X_op
!= O_constant
3585 && offset_expr
.X_op
!= O_symbol
)
3587 as_bad ("expression too complex");
3588 offset_expr
.X_op
= O_constant
;
3591 /* A constant expression in PIC code can be handled just as it
3592 is in non PIC code. */
3593 if (mips_pic
== NO_PIC
3594 || offset_expr
.X_op
== O_constant
)
3596 /* If this is a reference to a GP relative symbol, and there
3597 is no base register, we want
3598 <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL)
3599 Otherwise, if there is no base register, we want
3600 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
3601 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
3602 If we have a constant, we need two instructions anyhow,
3603 so we always use the latter form.
3605 If we have a base register, and this is a reference to a
3606 GP relative symbol, we want
3607 addu $tempreg,$breg,$gp
3608 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GPREL)
3610 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
3611 addu $tempreg,$tempreg,$breg
3612 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
3613 With a constant we always use the latter case. */
3616 if ((valueT
) offset_expr
.X_add_number
>= MAX_GPREL_OFFSET
3617 || nopic_need_relax (offset_expr
.X_add_symbol
))
3622 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
3623 treg
, (int) BFD_RELOC_MIPS_GPREL
, GP
);
3624 p
= frag_var (rs_machine_dependent
, 8, 0,
3625 RELAX_ENCODE (4, 8, 0, 4, 0,
3626 (mips_warn_about_macros
3627 || (used_at
&& mips_noat
))),
3628 offset_expr
.X_add_symbol
, (long) 0,
3632 macro_build_lui (p
, &icnt
, &offset_expr
, tempreg
);
3635 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
, treg
,
3636 (int) BFD_RELOC_LO16
, tempreg
);
3640 if ((valueT
) offset_expr
.X_add_number
>= MAX_GPREL_OFFSET
3641 || nopic_need_relax (offset_expr
.X_add_symbol
))
3646 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3647 mips_isa
< 3 ? "addu" : "daddu",
3648 "d,v,t", tempreg
, breg
, GP
);
3649 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
3650 treg
, (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
3651 p
= frag_var (rs_machine_dependent
, 12, 0,
3652 RELAX_ENCODE (8, 12, 0, 8, 0, 0),
3653 offset_expr
.X_add_symbol
, (long) 0,
3656 macro_build_lui (p
, &icnt
, &offset_expr
, tempreg
);
3659 macro_build (p
, &icnt
, (expressionS
*) NULL
,
3660 mips_isa
< 3 ? "addu" : "daddu",
3661 "d,v,t", tempreg
, tempreg
, breg
);
3664 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
, treg
,
3665 (int) BFD_RELOC_LO16
, tempreg
);
3668 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
3670 /* If this is a reference to an external symbol, we want
3671 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3673 <op> $treg,0($tempreg)
3675 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3677 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
3678 <op> $treg,0($tempreg)
3679 If there is a base register, we add it to $tempreg before
3680 the <op>. If there is a constant, we stick it in the
3681 <op> instruction. We don't handle constants larger than
3682 16 bits, because we have no way to load the upper 16 bits
3683 (actually, we could handle them for the subset of cases
3684 in which we are not using $at). */
3685 assert (offset_expr
.X_op
== O_symbol
);
3686 expr1
.X_add_number
= offset_expr
.X_add_number
;
3687 offset_expr
.X_add_number
= 0;
3688 if (expr1
.X_add_number
< -0x8000
3689 || expr1
.X_add_number
>= 0x8000)
3690 as_bad ("PIC code offset overflow (max 16 signed bits)");
3692 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3693 mips_isa
< 3 ? "lw" : "ld",
3694 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
3695 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
3696 p
= frag_var (rs_machine_dependent
, 4, 0,
3697 RELAX_ENCODE (0, 4, -8, 0, 0, 0),
3698 offset_expr
.X_add_symbol
, (long) 0,
3700 macro_build (p
, &icnt
, &offset_expr
,
3701 mips_isa
< 3 ? "addiu" : "daddiu",
3702 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
3704 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3705 mips_isa
< 3 ? "addu" : "daddu",
3706 "d,v,t", tempreg
, tempreg
, breg
);
3707 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
, treg
,
3708 (int) BFD_RELOC_LO16
, tempreg
);
3710 else if (mips_pic
== SVR4_PIC
)
3714 /* If this is a reference to an external symbol, we want
3715 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
3716 addu $tempreg,$tempreg,$gp
3717 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
3718 <op> $treg,0($tempreg)
3720 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3722 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
3723 <op> $treg,0($tempreg)
3724 If there is a base register, we add it to $tempreg before
3725 the <op>. If there is a constant, we stick it in the
3726 <op> instruction. We don't handle constants larger than
3727 16 bits, because we have no way to load the upper 16 bits
3728 (actually, we could handle them for the subset of cases
3729 in which we are not using $at). */
3730 assert (offset_expr
.X_op
== O_symbol
);
3731 expr1
.X_add_number
= offset_expr
.X_add_number
;
3732 offset_expr
.X_add_number
= 0;
3733 if (expr1
.X_add_number
< -0x8000
3734 || expr1
.X_add_number
>= 0x8000)
3735 as_bad ("PIC code offset overflow (max 16 signed bits)");
3736 if (reg_needs_delay (GP
))
3741 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
3742 tempreg
, (int) BFD_RELOC_MIPS_GOT_HI16
);
3743 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3744 mips_isa
< 3 ? "addu" : "daddu",
3745 "d,v,t", tempreg
, tempreg
, GP
);
3746 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3747 mips_isa
< 3 ? "lw" : "ld",
3748 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT_LO16
,
3750 p
= frag_var (rs_machine_dependent
, 12 + gpdel
, 0,
3751 RELAX_ENCODE (12, 12 + gpdel
, gpdel
, 8 + gpdel
, 0, 0),
3752 offset_expr
.X_add_symbol
, (long) 0, (char *) NULL
);
3755 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
3758 macro_build (p
, &icnt
, &offset_expr
,
3759 mips_isa
< 3 ? "lw" : "ld",
3760 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
3762 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
3764 macro_build (p
, &icnt
, &offset_expr
,
3765 mips_isa
< 3 ? "addiu" : "daddiu",
3766 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
3768 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3769 mips_isa
< 3 ? "addu" : "daddu",
3770 "d,v,t", tempreg
, tempreg
, breg
);
3771 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
, treg
,
3772 (int) BFD_RELOC_LO16
, tempreg
);
3774 else if (mips_pic
== EMBEDDED_PIC
)
3776 /* If there is no base register, we want
3777 <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL)
3778 If there is a base register, we want
3779 addu $tempreg,$breg,$gp
3780 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GPREL)
3782 assert (offset_expr
.X_op
== O_symbol
);
3785 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
3786 treg
, (int) BFD_RELOC_MIPS_GPREL
, GP
);
3791 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3792 mips_isa
< 3 ? "addu" : "daddu",
3793 "d,v,t", tempreg
, breg
, GP
);
3794 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
3795 treg
, (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
3808 load_register (&icnt
, treg
, &imm_expr
, 0);
3812 load_register (&icnt
, treg
, &imm_expr
, 1);
3816 if (imm_expr
.X_op
== O_constant
)
3818 load_register (&icnt
, AT
, &imm_expr
, 0);
3819 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3820 "mtc1", "t,G", AT
, treg
);
3825 assert (offset_expr
.X_op
== O_symbol
3826 && strcmp (segment_name (S_GET_SEGMENT
3827 (offset_expr
.X_add_symbol
)),
3829 && offset_expr
.X_add_number
== 0);
3830 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lwc1", "T,o(b)",
3831 treg
, (int) BFD_RELOC_MIPS_LITERAL
, GP
);
3836 /* We know that sym is in the .rdata section. First we get the
3837 upper 16 bits of the address. */
3838 if (mips_pic
== NO_PIC
)
3840 /* FIXME: This won't work for a 64 bit address. */
3841 macro_build_lui ((char *) NULL
, &icnt
, &offset_expr
, AT
);
3843 else if (mips_pic
== SVR4_PIC
)
3845 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3846 mips_isa
< 3 ? "lw" : "ld",
3847 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
3849 else if (mips_pic
== EMBEDDED_PIC
)
3851 /* For embedded PIC we pick up the entire address off $gp in
3852 a single instruction. */
3853 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3854 mips_isa
< 3 ? "addiu" : "daddiu",
3855 "t,r,j", AT
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
3856 offset_expr
.X_op
= O_constant
;
3857 offset_expr
.X_add_number
= 0;
3862 /* Now we load the register(s). */
3864 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "ld", "t,o(b)",
3865 treg
, (int) BFD_RELOC_LO16
, AT
);
3868 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lw", "t,o(b)",
3869 treg
, (int) BFD_RELOC_LO16
, AT
);
3872 /* FIXME: How in the world do we deal with the possible
3874 offset_expr
.X_add_number
+= 4;
3875 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lw", "t,o(b)",
3876 treg
+ 1, (int) BFD_RELOC_LO16
, AT
);
3880 /* To avoid confusion in tc_gen_reloc, we must ensure that this
3881 does not become a variant frag. */
3882 frag_wane (frag_now
);
3888 assert (offset_expr
.X_op
== O_symbol
3889 && offset_expr
.X_add_number
== 0);
3890 s
= segment_name (S_GET_SEGMENT (offset_expr
.X_add_symbol
));
3891 if (strcmp (s
, ".lit8") == 0)
3895 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "ldc1",
3896 "T,o(b)", treg
, (int) BFD_RELOC_MIPS_LITERAL
, GP
);
3900 r
= BFD_RELOC_MIPS_LITERAL
;
3905 assert (strcmp (s
, RDATA_SECTION_NAME
) == 0);
3906 if (mips_pic
== SVR4_PIC
)
3907 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3908 mips_isa
< 3 ? "lw" : "ld",
3909 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
3912 /* FIXME: This won't work for a 64 bit address. */
3913 macro_build_lui ((char *) NULL
, &icnt
, &offset_expr
, AT
);
3918 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "ldc1",
3919 "T,o(b)", treg
, (int) BFD_RELOC_LO16
, AT
);
3921 /* To avoid confusion in tc_gen_reloc, we must ensure
3922 that this does not become a variant frag. */
3923 frag_wane (frag_now
);
3934 /* Even on a big endian machine $fn comes before $fn+1. We have
3935 to adjust when loading from memory. */
3938 assert (mips_isa
< 2);
3939 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lwc1", "T,o(b)",
3940 byte_order
== LITTLE_ENDIAN
? treg
: treg
+ 1,
3942 /* FIXME: A possible overflow which I don't know how to deal
3944 offset_expr
.X_add_number
+= 4;
3945 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lwc1", "T,o(b)",
3946 byte_order
== LITTLE_ENDIAN
? treg
+ 1 : treg
,
3949 /* To avoid confusion in tc_gen_reloc, we must ensure that this
3950 does not become a variant frag. */
3951 frag_wane (frag_now
);
3960 * The MIPS assembler seems to check for X_add_number not
3961 * being double aligned and generating:
3964 * addiu at,at,%lo(foo+1)
3967 * But, the resulting address is the same after relocation so why
3968 * generate the extra instruction?
4015 if (offset_expr
.X_op
!= O_symbol
4016 && offset_expr
.X_op
!= O_constant
)
4018 as_bad ("expression too complex");
4019 offset_expr
.X_op
= O_constant
;
4022 /* Even on a big endian machine $fn comes before $fn+1. We have
4023 to adjust when loading from memory. We set coproc if we must
4024 load $fn+1 first. */
4025 if (byte_order
== LITTLE_ENDIAN
)
4028 if (mips_pic
== NO_PIC
4029 || offset_expr
.X_op
== O_constant
)
4031 /* If this is a reference to a GP relative symbol, we want
4032 <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL)
4033 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_MIPS_GPREL)
4034 If we have a base register, we use this
4036 <op> $treg,<sym>($at) (BFD_RELOC_MIPS_GPREL)
4037 <op> $treg+1,<sym>+4($at) (BFD_RELOC_MIPS_GPREL)
4038 If this is not a GP relative symbol, we want
4039 lui $at,<sym> (BFD_RELOC_HI16_S)
4040 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
4041 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
4042 If there is a base register, we add it to $at after the
4043 lui instruction. If there is a constant, we always use
4045 if ((valueT
) offset_expr
.X_add_number
>= MAX_GPREL_OFFSET
4046 || nopic_need_relax (offset_expr
.X_add_symbol
))
4065 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4066 mips_isa
< 3 ? "addu" : "daddu",
4067 "d,v,t", AT
, breg
, GP
);
4073 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
4074 coproc
? treg
+ 1 : treg
,
4075 (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
4076 offset_expr
.X_add_number
+= 4;
4078 /* Set mips_optimize to 2 to avoid inserting an
4080 hold_mips_optimize
= mips_optimize
;
4082 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
4083 coproc
? treg
: treg
+ 1,
4084 (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
4085 mips_optimize
= hold_mips_optimize
;
4087 p
= frag_var (rs_machine_dependent
, 12 + off
, 0,
4088 RELAX_ENCODE (8 + off
, 12 + off
, 0, 4 + off
, 1,
4089 used_at
&& mips_noat
),
4090 offset_expr
.X_add_symbol
, (long) 0,
4093 /* We just generated two relocs. When tc_gen_reloc
4094 handles this case, it will skip the first reloc and
4095 handle the second. The second reloc already has an
4096 extra addend of 4, which we added above. We must
4097 subtract it out, and then subtract another 4 to make
4098 the first reloc come out right. The second reloc
4099 will come out right because we are going to add 4 to
4100 offset_expr when we build its instruction below. */
4101 offset_expr
.X_add_number
-= 8;
4102 offset_expr
.X_op
= O_constant
;
4104 macro_build_lui (p
, &icnt
, &offset_expr
, AT
);
4109 macro_build (p
, &icnt
, (expressionS
*) NULL
,
4110 mips_isa
< 3 ? "addu" : "daddu",
4111 "d,v,t", AT
, breg
, AT
);
4115 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
,
4116 coproc
? treg
+ 1 : treg
,
4117 (int) BFD_RELOC_LO16
, AT
);
4120 /* FIXME: How do we handle overflow here? */
4121 offset_expr
.X_add_number
+= 4;
4122 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
,
4123 coproc
? treg
: treg
+ 1,
4124 (int) BFD_RELOC_LO16
, AT
);
4126 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
4130 /* If this is a reference to an external symbol, we want
4131 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4136 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4138 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
4139 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
4140 If there is a base register we add it to $at before the
4141 lwc1 instructions. If there is a constant we include it
4142 in the lwc1 instructions. */
4144 expr1
.X_add_number
= offset_expr
.X_add_number
;
4145 offset_expr
.X_add_number
= 0;
4146 if (expr1
.X_add_number
< -0x8000
4147 || expr1
.X_add_number
>= 0x8000 - 4)
4148 as_bad ("PIC code offset overflow (max 16 signed bits)");
4153 frag_grow (24 + off
);
4154 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4155 mips_isa
< 3 ? "lw" : "ld",
4156 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
4157 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
4159 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4160 mips_isa
< 3 ? "addu" : "daddu",
4161 "d,v,t", AT
, breg
, AT
);
4162 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
4163 coproc
? treg
+ 1 : treg
,
4164 (int) BFD_RELOC_LO16
, AT
);
4165 expr1
.X_add_number
+= 4;
4167 /* Set mips_optimize to 2 to avoid inserting an undesired
4169 hold_mips_optimize
= mips_optimize
;
4171 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
4172 coproc
? treg
: treg
+ 1,
4173 (int) BFD_RELOC_LO16
, AT
);
4174 mips_optimize
= hold_mips_optimize
;
4176 (void) frag_var (rs_machine_dependent
, 0, 0,
4177 RELAX_ENCODE (0, 0, -16 - off
, -8, 1, 0),
4178 offset_expr
.X_add_symbol
, (long) 0,
4181 else if (mips_pic
== SVR4_PIC
)
4185 /* If this is a reference to an external symbol, we want
4186 lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16)
4188 lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16)
4193 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4195 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
4196 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
4197 If there is a base register we add it to $at before the
4198 lwc1 instructions. If there is a constant we include it
4199 in the lwc1 instructions. */
4201 expr1
.X_add_number
= offset_expr
.X_add_number
;
4202 offset_expr
.X_add_number
= 0;
4203 if (expr1
.X_add_number
< -0x8000
4204 || expr1
.X_add_number
>= 0x8000 - 4)
4205 as_bad ("PIC code offset overflow (max 16 signed bits)");
4206 if (reg_needs_delay (GP
))
4215 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
4216 AT
, (int) BFD_RELOC_MIPS_GOT_HI16
);
4217 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4218 mips_isa
< 3 ? "addu" : "daddu",
4219 "d,v,t", AT
, AT
, GP
);
4220 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4221 mips_isa
< 3 ? "lw" : "ld",
4222 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT_LO16
, AT
);
4223 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
4225 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4226 mips_isa
< 3 ? "addu" : "daddu",
4227 "d,v,t", AT
, breg
, AT
);
4228 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
4229 coproc
? treg
+ 1 : treg
,
4230 (int) BFD_RELOC_LO16
, AT
);
4231 expr1
.X_add_number
+= 4;
4233 /* Set mips_optimize to 2 to avoid inserting an undesired
4235 hold_mips_optimize
= mips_optimize
;
4237 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
4238 coproc
? treg
: treg
+ 1,
4239 (int) BFD_RELOC_LO16
, AT
);
4240 mips_optimize
= hold_mips_optimize
;
4241 expr1
.X_add_number
-= 4;
4243 p
= frag_var (rs_machine_dependent
, 16 + gpdel
+ off
, 0,
4244 RELAX_ENCODE (24 + off
, 16 + gpdel
+ off
, gpdel
,
4245 8 + gpdel
+ off
, 1, 0),
4246 offset_expr
.X_add_symbol
, (long) 0,
4250 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4253 macro_build (p
, &icnt
, &offset_expr
,
4254 mips_isa
< 3 ? "lw" : "ld",
4255 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
4257 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4261 macro_build (p
, &icnt
, (expressionS
*) NULL
,
4262 mips_isa
< 3 ? "addu" : "daddu",
4263 "d,v,t", AT
, breg
, AT
);
4266 macro_build (p
, &icnt
, &expr1
, s
, fmt
,
4267 coproc
? treg
+ 1 : treg
,
4268 (int) BFD_RELOC_LO16
, AT
);
4270 expr1
.X_add_number
+= 4;
4272 /* Set mips_optimize to 2 to avoid inserting an undesired
4274 hold_mips_optimize
= mips_optimize
;
4276 macro_build (p
, &icnt
, &expr1
, s
, fmt
,
4277 coproc
? treg
: treg
+ 1,
4278 (int) BFD_RELOC_LO16
, AT
);
4279 mips_optimize
= hold_mips_optimize
;
4281 else if (mips_pic
== EMBEDDED_PIC
)
4283 /* If there is no base register, we use
4284 <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL)
4285 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_MIPS_GPREL)
4286 If we have a base register, we use
4288 <op> $treg,<sym>($at) (BFD_RELOC_MIPS_GPREL)
4289 <op> $treg+1,<sym>+4($at) (BFD_RELOC_MIPS_GPREL)
4298 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4299 mips_isa
< 3 ? "addu" : "daddu",
4300 "d,v,t", AT
, breg
, GP
);
4305 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
4306 coproc
? treg
+ 1 : treg
,
4307 (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
4308 offset_expr
.X_add_number
+= 4;
4309 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
4310 coproc
? treg
: treg
+ 1,
4311 (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
4327 assert (mips_isa
< 3);
4328 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
4329 (int) BFD_RELOC_LO16
, breg
);
4330 offset_expr
.X_add_number
+= 4;
4331 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
+ 1,
4332 (int) BFD_RELOC_LO16
, breg
);
4334 #ifdef LOSING_COMPILER
4340 as_warn ("Macro used $at after \".set noat\"");
4345 struct mips_cl_insn
*ip
;
4347 register int treg
, sreg
, dreg
, breg
;
4362 bfd_reloc_code_real_type r
;
4365 treg
= (ip
->insn_opcode
>> 16) & 0x1f;
4366 dreg
= (ip
->insn_opcode
>> 11) & 0x1f;
4367 sreg
= breg
= (ip
->insn_opcode
>> 21) & 0x1f;
4368 mask
= ip
->insn_mo
->mask
;
4370 expr1
.X_op
= O_constant
;
4371 expr1
.X_op_symbol
= NULL
;
4372 expr1
.X_add_symbol
= NULL
;
4373 expr1
.X_add_number
= 1;
4377 #endif /* LOSING_COMPILER */
4382 macro_build ((char *) NULL
, &icnt
, NULL
,
4383 dbl
? "dmultu" : "multu",
4385 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
4391 /* The MIPS assembler some times generates shifts and adds. I'm
4392 not trying to be that fancy. GCC should do this for us
4394 load_register (&icnt
, AT
, &imm_expr
, dbl
);
4395 macro_build ((char *) NULL
, &icnt
, NULL
,
4396 dbl
? "dmult" : "mult",
4398 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
4404 mips_emit_delays ();
4406 mips_any_noreorder
= 1;
4407 macro_build ((char *) NULL
, &icnt
, NULL
,
4408 dbl
? "dmult" : "mult",
4410 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
4411 macro_build ((char *) NULL
, &icnt
, NULL
,
4412 dbl
? "dsra32" : "sra",
4413 "d,w,<", dreg
, dreg
, 31);
4414 macro_build ((char *) NULL
, &icnt
, NULL
, "mfhi", "d", AT
);
4416 macro_build ((char *) NULL
, &icnt
, NULL
, "tne", "s,t", dreg
, AT
);
4419 expr1
.X_add_number
= 8;
4420 macro_build ((char *) NULL
, &icnt
, &expr1
, "beq", "s,t,p", dreg
, AT
);
4421 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
4422 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 6);
4425 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
4431 mips_emit_delays ();
4433 mips_any_noreorder
= 1;
4434 macro_build ((char *) NULL
, &icnt
, NULL
,
4435 dbl
? "dmultu" : "multu",
4437 macro_build ((char *) NULL
, &icnt
, NULL
, "mfhi", "d", AT
);
4438 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
4440 macro_build ((char *) NULL
, &icnt
, NULL
, "tne", "s,t", AT
, 0);
4443 expr1
.X_add_number
= 8;
4444 macro_build ((char *) NULL
, &icnt
, &expr1
, "beq", "s,t,p", AT
, 0);
4445 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
4446 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 6);
4452 macro_build ((char *) NULL
, &icnt
, NULL
, "subu", "d,v,t", AT
, 0, treg
);
4453 macro_build ((char *) NULL
, &icnt
, NULL
, "srlv", "d,t,s", AT
, sreg
, AT
);
4454 macro_build ((char *) NULL
, &icnt
, NULL
, "sllv", "d,t,s", dreg
, sreg
,
4456 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
4460 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", AT
, sreg
,
4461 (int) (imm_expr
.X_add_number
& 0x1f));
4462 macro_build ((char *) NULL
, &icnt
, NULL
, "srl", "d,w,<", dreg
, sreg
,
4463 (int) ((0 - imm_expr
.X_add_number
) & 0x1f));
4464 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
4468 macro_build ((char *) NULL
, &icnt
, NULL
, "subu", "d,v,t", AT
, 0, treg
);
4469 macro_build ((char *) NULL
, &icnt
, NULL
, "sllv", "d,t,s", AT
, sreg
, AT
);
4470 macro_build ((char *) NULL
, &icnt
, NULL
, "srlv", "d,t,s", dreg
, sreg
,
4472 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
4476 macro_build ((char *) NULL
, &icnt
, NULL
, "srl", "d,w,<", AT
, sreg
,
4477 (int) (imm_expr
.X_add_number
& 0x1f));
4478 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", dreg
, sreg
,
4479 (int) ((0 - imm_expr
.X_add_number
) & 0x1f));
4480 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
4484 assert (mips_isa
< 2);
4485 /* Even on a big endian machine $fn comes before $fn+1. We have
4486 to adjust when storing to memory. */
4487 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "swc1", "T,o(b)",
4488 byte_order
== LITTLE_ENDIAN
? treg
: treg
+ 1,
4489 (int) BFD_RELOC_LO16
, breg
);
4490 offset_expr
.X_add_number
+= 4;
4491 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "swc1", "T,o(b)",
4492 byte_order
== LITTLE_ENDIAN
? treg
+ 1 : treg
,
4493 (int) BFD_RELOC_LO16
, breg
);
4498 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
4499 treg
, (int) BFD_RELOC_LO16
);
4501 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
4502 sreg
, (int) BFD_RELOC_LO16
);
4505 macro_build ((char *) NULL
, &icnt
, NULL
, "xor", "d,v,t", dreg
,
4507 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
4508 dreg
, (int) BFD_RELOC_LO16
);
4513 if (imm_expr
.X_add_number
== 0)
4515 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
4516 sreg
, (int) BFD_RELOC_LO16
);
4521 as_warn ("Instruction %s: result is always false",
4523 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
, 0);
4526 if (imm_expr
.X_add_number
>= 0 && imm_expr
.X_add_number
< 0x10000)
4528 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "xori", "t,r,i", dreg
,
4529 sreg
, (int) BFD_RELOC_LO16
);
4532 else if (imm_expr
.X_add_number
> -0x8000 && imm_expr
.X_add_number
< 0)
4534 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
4535 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
4536 mips_isa
< 3 ? "addiu" : "daddiu",
4537 "t,r,j", dreg
, sreg
,
4538 (int) BFD_RELOC_LO16
);
4543 load_register (&icnt
, AT
, &imm_expr
, 0);
4544 macro_build ((char *) NULL
, &icnt
, NULL
, "xor", "d,v,t", dreg
,
4548 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
, dreg
,
4549 (int) BFD_RELOC_LO16
);
4554 case M_SGE
: /* sreg >= treg <==> not (sreg < treg) */
4560 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, sreg
, treg
);
4561 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
4562 (int) BFD_RELOC_LO16
);
4565 case M_SGE_I
: /* sreg >= I <==> not (sreg < I) */
4567 if (imm_expr
.X_add_number
>= -0x8000 && imm_expr
.X_add_number
< 0x8000)
4569 macro_build ((char *) NULL
, &icnt
, &expr1
,
4570 mask
== M_SGE_I
? "slti" : "sltiu",
4571 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
4576 load_register (&icnt
, AT
, &imm_expr
, 0);
4577 macro_build ((char *) NULL
, &icnt
, NULL
,
4578 mask
== M_SGE_I
? "slt" : "sltu",
4579 "d,v,t", dreg
, sreg
, AT
);
4582 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
4583 (int) BFD_RELOC_LO16
);
4588 case M_SGT
: /* sreg > treg <==> treg < sreg */
4594 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, treg
, sreg
);
4597 case M_SGT_I
: /* sreg > I <==> I < sreg */
4603 load_register (&icnt
, AT
, &imm_expr
, 0);
4604 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, AT
, sreg
);
4607 case M_SLE
: /* sreg <= treg <==> treg >= sreg <==> not (treg < sreg) */
4613 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, treg
, sreg
);
4614 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
4615 (int) BFD_RELOC_LO16
);
4618 case M_SLE_I
: /* sreg <= I <==> I >= sreg <==> not (I < sreg) */
4624 load_register (&icnt
, AT
, &imm_expr
, 0);
4625 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, AT
, sreg
);
4626 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
4627 (int) BFD_RELOC_LO16
);
4631 if (imm_expr
.X_add_number
>= -0x8000 && imm_expr
.X_add_number
< 0x8000)
4633 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "slti", "t,r,j",
4634 dreg
, sreg
, (int) BFD_RELOC_LO16
);
4637 load_register (&icnt
, AT
, &imm_expr
, 0);
4638 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", dreg
, sreg
, AT
);
4642 if (imm_expr
.X_add_number
>= -0x8000 && imm_expr
.X_add_number
< 0x8000)
4644 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "sltiu", "t,r,j",
4645 dreg
, sreg
, (int) BFD_RELOC_LO16
);
4648 load_register (&icnt
, AT
, &imm_expr
, 0);
4649 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, sreg
,
4655 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0,
4658 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0,
4662 macro_build ((char *) NULL
, &icnt
, NULL
, "xor", "d,v,t", dreg
,
4664 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0,
4670 if (imm_expr
.X_add_number
== 0)
4672 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0,
4678 as_warn ("Instruction %s: result is always true",
4680 macro_build ((char *) NULL
, &icnt
, &expr1
,
4681 mips_isa
< 3 ? "addiu" : "daddiu",
4682 "t,r,j", dreg
, 0, (int) BFD_RELOC_LO16
);
4685 if (imm_expr
.X_add_number
>= 0 && imm_expr
.X_add_number
< 0x10000)
4687 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "xori", "t,r,i",
4688 dreg
, sreg
, (int) BFD_RELOC_LO16
);
4691 else if (imm_expr
.X_add_number
> -0x8000 && imm_expr
.X_add_number
< 0)
4693 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
4694 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
4695 mips_isa
< 3 ? "addiu" : "daddiu",
4696 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
4701 load_register (&icnt
, AT
, &imm_expr
, 0);
4702 macro_build ((char *) NULL
, &icnt
, NULL
, "xor", "d,v,t", dreg
,
4706 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0, dreg
);
4714 if (imm_expr
.X_add_number
> -0x8000 && imm_expr
.X_add_number
<= 0x8000)
4716 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
4717 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
4718 dbl
? "daddi" : "addi",
4719 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
4722 load_register (&icnt
, AT
, &imm_expr
, dbl
);
4723 macro_build ((char *) NULL
, &icnt
, NULL
,
4724 dbl
? "dsub" : "sub",
4725 "d,v,t", dreg
, sreg
, AT
);
4731 if (imm_expr
.X_add_number
> -0x8000 && imm_expr
.X_add_number
<= 0x8000)
4733 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
4734 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
4735 dbl
? "daddiu" : "addiu",
4736 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
4739 load_register (&icnt
, AT
, &imm_expr
, dbl
);
4740 macro_build ((char *) NULL
, &icnt
, NULL
,
4741 dbl
? "dsubu" : "subu",
4742 "d,v,t", dreg
, sreg
, AT
);
4763 load_register (&icnt
, AT
, &imm_expr
, 0);
4764 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "s,t", sreg
, AT
);
4769 assert (mips_isa
< 2);
4770 sreg
= (ip
->insn_opcode
>> 11) & 0x1f; /* floating reg */
4771 dreg
= (ip
->insn_opcode
>> 06) & 0x1f; /* floating reg */
4774 * Is the double cfc1 instruction a bug in the mips assembler;
4775 * or is there a reason for it?
4777 mips_emit_delays ();
4779 mips_any_noreorder
= 1;
4780 macro_build ((char *) NULL
, &icnt
, NULL
, "cfc1", "t,G", treg
, 31);
4781 macro_build ((char *) NULL
, &icnt
, NULL
, "cfc1", "t,G", treg
, 31);
4782 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "");
4783 expr1
.X_add_number
= 3;
4784 macro_build ((char *) NULL
, &icnt
, &expr1
, "ori", "t,r,i", AT
, treg
,
4785 (int) BFD_RELOC_LO16
);
4786 expr1
.X_add_number
= 2;
4787 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", AT
, AT
,
4788 (int) BFD_RELOC_LO16
);
4789 macro_build ((char *) NULL
, &icnt
, NULL
, "ctc1", "t,G", AT
, 31);
4790 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "");
4791 macro_build ((char *) NULL
, &icnt
, NULL
,
4792 mask
== M_TRUNCWD
? "cvt.w.d" : "cvt.w.s", "D,S", dreg
, sreg
);
4793 macro_build ((char *) NULL
, &icnt
, NULL
, "ctc1", "t,G", treg
, 31);
4794 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "");
4804 if (offset_expr
.X_add_number
>= 0x7fff)
4805 as_bad ("operand overflow");
4806 /* avoid load delay */
4807 if (byte_order
== LITTLE_ENDIAN
)
4808 offset_expr
.X_add_number
+= 1;
4809 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
4810 (int) BFD_RELOC_LO16
, breg
);
4811 if (byte_order
== LITTLE_ENDIAN
)
4812 offset_expr
.X_add_number
-= 1;
4814 offset_expr
.X_add_number
+= 1;
4815 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lbu", "t,o(b)", AT
,
4816 (int) BFD_RELOC_LO16
, breg
);
4817 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", treg
, treg
, 8);
4818 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", treg
, treg
, AT
);
4831 if (offset_expr
.X_add_number
>= 0x8000 - off
)
4832 as_bad ("operand overflow");
4833 if (byte_order
== LITTLE_ENDIAN
)
4834 offset_expr
.X_add_number
+= off
;
4835 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
4836 (int) BFD_RELOC_LO16
, breg
);
4837 if (byte_order
== LITTLE_ENDIAN
)
4838 offset_expr
.X_add_number
-= off
;
4840 offset_expr
.X_add_number
+= off
;
4841 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s2
, "t,o(b)", treg
,
4842 (int) BFD_RELOC_LO16
, breg
);
4855 load_address (&icnt
, AT
, &offset_expr
);
4857 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4858 mips_isa
< 3 ? "addu" : "daddu",
4859 "d,v,t", AT
, AT
, breg
);
4860 if (byte_order
== LITTLE_ENDIAN
)
4861 expr1
.X_add_number
= off
;
4863 expr1
.X_add_number
= 0;
4864 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, "t,o(b)", treg
,
4865 (int) BFD_RELOC_LO16
, AT
);
4866 if (byte_order
== LITTLE_ENDIAN
)
4867 expr1
.X_add_number
= 0;
4869 expr1
.X_add_number
= off
;
4870 macro_build ((char *) NULL
, &icnt
, &expr1
, s2
, "t,o(b)", treg
,
4871 (int) BFD_RELOC_LO16
, AT
);
4876 load_address (&icnt
, AT
, &offset_expr
);
4878 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4879 mips_isa
< 3 ? "addu" : "daddu",
4880 "d,v,t", AT
, AT
, breg
);
4881 if (byte_order
== BIG_ENDIAN
)
4882 expr1
.X_add_number
= 0;
4883 macro_build ((char *) NULL
, &icnt
, &expr1
,
4884 mask
== M_ULH_A
? "lb" : "lbu", "t,o(b)", treg
,
4885 (int) BFD_RELOC_LO16
, AT
);
4886 if (byte_order
== BIG_ENDIAN
)
4887 expr1
.X_add_number
= 1;
4889 expr1
.X_add_number
= 0;
4890 macro_build ((char *) NULL
, &icnt
, &expr1
, "lbu", "t,o(b)", AT
,
4891 (int) BFD_RELOC_LO16
, AT
);
4892 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", treg
,
4894 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", treg
,
4899 if (offset_expr
.X_add_number
>= 0x7fff)
4900 as_bad ("operand overflow");
4901 if (byte_order
== BIG_ENDIAN
)
4902 offset_expr
.X_add_number
+= 1;
4903 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "sb", "t,o(b)", treg
,
4904 (int) BFD_RELOC_LO16
, breg
);
4905 macro_build ((char *) NULL
, &icnt
, NULL
, "srl", "d,w,<", AT
, treg
, 8);
4906 if (byte_order
== BIG_ENDIAN
)
4907 offset_expr
.X_add_number
-= 1;
4909 offset_expr
.X_add_number
+= 1;
4910 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "sb", "t,o(b)", AT
,
4911 (int) BFD_RELOC_LO16
, breg
);
4924 if (offset_expr
.X_add_number
>= 0x8000 - off
)
4925 as_bad ("operand overflow");
4926 if (byte_order
== LITTLE_ENDIAN
)
4927 offset_expr
.X_add_number
+= off
;
4928 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
4929 (int) BFD_RELOC_LO16
, breg
);
4930 if (byte_order
== LITTLE_ENDIAN
)
4931 offset_expr
.X_add_number
-= off
;
4933 offset_expr
.X_add_number
+= off
;
4934 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s2
, "t,o(b)", treg
,
4935 (int) BFD_RELOC_LO16
, breg
);
4948 load_address (&icnt
, AT
, &offset_expr
);
4950 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4951 mips_isa
< 3 ? "addu" : "daddu",
4952 "d,v,t", AT
, AT
, breg
);
4953 if (byte_order
== LITTLE_ENDIAN
)
4954 expr1
.X_add_number
= off
;
4956 expr1
.X_add_number
= 0;
4957 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, "t,o(b)", treg
,
4958 (int) BFD_RELOC_LO16
, AT
);
4959 if (byte_order
== LITTLE_ENDIAN
)
4960 expr1
.X_add_number
= 0;
4962 expr1
.X_add_number
= off
;
4963 macro_build ((char *) NULL
, &icnt
, &expr1
, s2
, "t,o(b)", treg
,
4964 (int) BFD_RELOC_LO16
, AT
);
4968 load_address (&icnt
, AT
, &offset_expr
);
4970 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4971 mips_isa
< 3 ? "addu" : "daddu",
4972 "d,v,t", AT
, AT
, breg
);
4973 if (byte_order
== LITTLE_ENDIAN
)
4974 expr1
.X_add_number
= 0;
4975 macro_build ((char *) NULL
, &icnt
, &expr1
, "sb", "t,o(b)", treg
,
4976 (int) BFD_RELOC_LO16
, AT
);
4977 macro_build ((char *) NULL
, &icnt
, NULL
, "srl", "d,w,<", treg
,
4979 if (byte_order
== LITTLE_ENDIAN
)
4980 expr1
.X_add_number
= 1;
4982 expr1
.X_add_number
= 0;
4983 macro_build ((char *) NULL
, &icnt
, &expr1
, "sb", "t,o(b)", treg
,
4984 (int) BFD_RELOC_LO16
, AT
);
4985 if (byte_order
== LITTLE_ENDIAN
)
4986 expr1
.X_add_number
= 0;
4988 expr1
.X_add_number
= 1;
4989 macro_build ((char *) NULL
, &icnt
, &expr1
, "lbu", "t,o(b)", AT
,
4990 (int) BFD_RELOC_LO16
, AT
);
4991 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", treg
,
4993 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", treg
,
4998 as_bad ("Macro %s not implemented yet", ip
->insn_mo
->name
);
5002 as_warn ("Macro used $at after \".set noat\"");
5005 /* This routine assembles an instruction into its binary format. As a
5006 side effect, it sets one of the global variables imm_reloc or
5007 offset_reloc to the type of relocation to do if one of the operands
5008 is an address expression. */
5013 struct mips_cl_insn
*ip
;
5018 struct mips_opcode
*insn
;
5021 unsigned int lastregno
= 0;
5026 for (s
= str
; islower (*s
) || (*s
>= '0' && *s
<= '3') || *s
== '6' || *s
== '.'; ++s
)
5038 as_fatal ("Unknown opcode: `%s'", str
);
5040 if ((insn
= (struct mips_opcode
*) hash_find (op_hash
, str
)) == NULL
)
5042 insn_error
= "unrecognized opcode";
5050 assert (strcmp (insn
->name
, str
) == 0);
5052 if (insn
->pinfo
== INSN_MACRO
)
5053 insn_isa
= insn
->match
;
5054 else if ((insn
->pinfo
& INSN_ISA
) == INSN_ISA2
)
5056 else if ((insn
->pinfo
& INSN_ISA
) == INSN_ISA3
)
5058 else if ((insn
->pinfo
& INSN_ISA
) == INSN_ISA4
)
5063 if (insn_isa
> mips_isa
5064 || ((insn
->pinfo
& INSN_ISA
) == INSN_4650
5066 || ((insn
->pinfo
& INSN_ISA
) == INSN_4010
5068 || ((insn
->pinfo
& INSN_ISA
) == INSN_4100
5071 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
]
5072 && strcmp (insn
->name
, insn
[1].name
) == 0)
5077 insn_error
= "opcode not supported on this processor";
5082 ip
->insn_opcode
= insn
->match
;
5083 for (args
= insn
->args
;; ++args
)
5089 case '\0': /* end of args */
5102 ip
->insn_opcode
|= lastregno
<< 21;
5107 ip
->insn_opcode
|= lastregno
<< 16;
5111 ip
->insn_opcode
|= lastregno
<< 11;
5117 /* handle optional base register.
5118 Either the base register is omitted or
5119 we must have a left paren. */
5120 /* this is dependent on the next operand specifier
5121 is a 'b' for base register */
5122 assert (args
[1] == 'b');
5126 case ')': /* these must match exactly */
5131 case '<': /* must be at least one digit */
5133 * According to the manual, if the shift amount is greater
5134 * than 31 or less than 0 the the shift amount should be
5135 * mod 32. In reality the mips assembler issues an error.
5136 * We issue a warning and mask out all but the low 5 bits.
5138 my_getExpression (&imm_expr
, s
);
5139 check_absolute_expr (ip
, &imm_expr
);
5140 if ((unsigned long) imm_expr
.X_add_number
> 31)
5142 as_warn ("Improper shift amount (%ld)",
5143 (long) imm_expr
.X_add_number
);
5144 imm_expr
.X_add_number
= imm_expr
.X_add_number
& 0x1f;
5146 ip
->insn_opcode
|= imm_expr
.X_add_number
<< 6;
5147 imm_expr
.X_op
= O_absent
;
5151 case '>': /* shift amount minus 32 */
5152 my_getExpression (&imm_expr
, s
);
5153 check_absolute_expr (ip
, &imm_expr
);
5154 if ((unsigned long) imm_expr
.X_add_number
< 32
5155 || (unsigned long) imm_expr
.X_add_number
> 63)
5157 ip
->insn_opcode
|= (imm_expr
.X_add_number
- 32) << 6;
5158 imm_expr
.X_op
= O_absent
;
5162 case 'k': /* cache code */
5163 case 'h': /* prefx code */
5164 my_getExpression (&imm_expr
, s
);
5165 check_absolute_expr (ip
, &imm_expr
);
5166 if ((unsigned long) imm_expr
.X_add_number
> 31)
5168 as_warn ("Invalid value for `%s' (%lu)",
5170 (unsigned long) imm_expr
.X_add_number
);
5171 imm_expr
.X_add_number
&= 0x1f;
5174 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_CACHE
;
5176 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_PREFX
;
5177 imm_expr
.X_op
= O_absent
;
5181 case 'c': /* break code */
5182 my_getExpression (&imm_expr
, s
);
5183 check_absolute_expr (ip
, &imm_expr
);
5184 if ((unsigned) imm_expr
.X_add_number
> 1023)
5185 as_warn ("Illegal break code (%ld)",
5186 (long) imm_expr
.X_add_number
);
5187 ip
->insn_opcode
|= imm_expr
.X_add_number
<< 16;
5188 imm_expr
.X_op
= O_absent
;
5192 case 'B': /* syscall code */
5193 my_getExpression (&imm_expr
, s
);
5194 check_absolute_expr (ip
, &imm_expr
);
5195 if ((unsigned) imm_expr
.X_add_number
> 0xfffff)
5196 as_warn ("Illegal syscall code (%ld)",
5197 (long) imm_expr
.X_add_number
);
5198 ip
->insn_opcode
|= imm_expr
.X_add_number
<< 6;
5199 imm_expr
.X_op
= O_absent
;
5203 case 'C': /* Coprocessor code */
5204 my_getExpression (&imm_expr
, s
);
5205 check_absolute_expr (ip
, &imm_expr
);
5206 if ((unsigned long) imm_expr
.X_add_number
>= (1<<25))
5208 as_warn ("Coproccesor code > 25 bits (%ld)",
5209 (long) imm_expr
.X_add_number
);
5210 imm_expr
.X_add_number
&= ((1<<25) - 1);
5212 ip
->insn_opcode
|= imm_expr
.X_add_number
;
5213 imm_expr
.X_op
= O_absent
;
5217 case 'b': /* base register */
5218 case 'd': /* destination register */
5219 case 's': /* source register */
5220 case 't': /* target register */
5221 case 'r': /* both target and source */
5222 case 'v': /* both dest and source */
5223 case 'w': /* both dest and target */
5224 case 'E': /* coprocessor target register */
5225 case 'G': /* coprocessor destination register */
5226 case 'x': /* ignore register name */
5227 case 'z': /* must be zero register */
5241 while (isdigit (*s
));
5243 as_bad ("Invalid register number (%d)", regno
);
5245 else if (*args
== 'E' || *args
== 'G')
5249 if (s
[1] == 'f' && s
[2] == 'p')
5254 else if (s
[1] == 's' && s
[2] == 'p')
5259 else if (s
[1] == 'g' && s
[2] == 'p')
5264 else if (s
[1] == 'a' && s
[2] == 't')
5269 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '0')
5274 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '1')
5286 as_warn ("Used $at without \".set noat\"");
5292 if (c
== 'r' || c
== 'v' || c
== 'w')
5299 /* 'z' only matches $0. */
5300 if (c
== 'z' && regno
!= 0)
5308 ip
->insn_opcode
|= regno
<< 21;
5312 ip
->insn_opcode
|= regno
<< 11;
5317 ip
->insn_opcode
|= regno
<< 16;
5320 /* This case exists because on the r3000 trunc
5321 expands into a macro which requires a gp
5322 register. On the r6000 or r4000 it is
5323 assembled into a single instruction which
5324 ignores the register. Thus the insn version
5325 is MIPS_ISA2 and uses 'x', and the macro
5326 version is MIPS_ISA1 and uses 't'. */
5329 /* This case is for the div instruction, which
5330 acts differently if the destination argument
5331 is $0. This only matches $0, and is checked
5332 outside the switch. */
5343 ip
->insn_opcode
|= lastregno
<< 21;
5346 ip
->insn_opcode
|= lastregno
<< 16;
5351 case 'D': /* floating point destination register */
5352 case 'S': /* floating point source register */
5353 case 'T': /* floating point target register */
5354 case 'R': /* floating point source register */
5358 if (s
[0] == '$' && s
[1] == 'f' && isdigit (s
[2]))
5368 while (isdigit (*s
));
5371 as_bad ("Invalid float register number (%d)", regno
);
5373 if ((regno
& 1) != 0
5375 && ! (strcmp (str
, "mtc1") == 0 ||
5376 strcmp (str
, "mfc1") == 0 ||
5377 strcmp (str
, "lwc1") == 0 ||
5378 strcmp (str
, "swc1") == 0))
5379 as_warn ("Float register should be even, was %d",
5387 if (c
== 'V' || c
== 'W')
5397 ip
->insn_opcode
|= regno
<< 6;
5401 ip
->insn_opcode
|= regno
<< 11;
5405 ip
->insn_opcode
|= regno
<< 16;
5408 ip
->insn_opcode
|= regno
<< 21;
5417 ip
->insn_opcode
|= lastregno
<< 11;
5420 ip
->insn_opcode
|= lastregno
<< 16;
5426 my_getExpression (&imm_expr
, s
);
5427 if (imm_expr
.X_op
!= O_big
5428 && imm_expr
.X_op
!= O_constant
)
5429 insn_error
= "absolute expression required";
5434 my_getExpression (&offset_expr
, s
);
5435 imm_reloc
= BFD_RELOC_32
;
5447 unsigned char temp
[8];
5449 unsigned int length
;
5454 /* These only appear as the last operand in an
5455 instruction, and every instruction that accepts
5456 them in any variant accepts them in all variants.
5457 This means we don't have to worry about backing out
5458 any changes if the instruction does not match.
5460 The difference between them is the size of the
5461 floating point constant and where it goes. For 'F'
5462 and 'L' the constant is 64 bits; for 'f' and 'l' it
5463 is 32 bits. Where the constant is placed is based
5464 on how the MIPS assembler does things:
5467 f -- immediate value
5470 The .lit4 and .lit8 sections are only used if
5471 permitted by the -G argument.
5473 When generating embedded PIC code, we use the
5474 .lit8 section but not the .lit4 section (we can do
5475 .lit4 inline easily; we need to put .lit8
5476 somewhere in the data segment, and using .lit8
5477 permits the linker to eventually combine identical
5480 f64
= *args
== 'F' || *args
== 'L';
5482 save_in
= input_line_pointer
;
5483 input_line_pointer
= s
;
5484 err
= md_atof (f64
? 'd' : 'f', (char *) temp
, &len
);
5486 s
= input_line_pointer
;
5487 input_line_pointer
= save_in
;
5488 if (err
!= NULL
&& *err
!= '\0')
5490 as_bad ("Bad floating point constant: %s", err
);
5491 memset (temp
, '\0', sizeof temp
);
5492 length
= f64
? 8 : 4;
5495 assert (length
== (f64
? 8 : 4));
5499 && (! USE_GLOBAL_POINTER_OPT
5500 || mips_pic
== EMBEDDED_PIC
5501 || g_switch_value
< 4)
5504 imm_expr
.X_op
= O_constant
;
5505 if (byte_order
== LITTLE_ENDIAN
)
5506 imm_expr
.X_add_number
=
5507 (((((((int) temp
[3] << 8)
5512 imm_expr
.X_add_number
=
5513 (((((((int) temp
[0] << 8)
5520 const char *newname
;
5523 /* Switch to the right section. */
5525 subseg
= now_subseg
;
5528 default: /* unused default case avoids warnings. */
5530 newname
= RDATA_SECTION_NAME
;
5531 if (USE_GLOBAL_POINTER_OPT
&& g_switch_value
>= 8)
5535 newname
= RDATA_SECTION_NAME
;
5538 assert (!USE_GLOBAL_POINTER_OPT
5539 || g_switch_value
>= 4);
5543 new_seg
= subseg_new (newname
, (subsegT
) 0);
5544 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
5545 bfd_set_section_flags (stdoutput
, new_seg
,
5550 frag_align (*args
== 'l' ? 2 : 3, 0);
5551 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
5552 record_alignment (new_seg
, 4);
5554 record_alignment (new_seg
, *args
== 'l' ? 2 : 3);
5556 as_bad ("Can't use floating point insn in this section");
5558 /* Set the argument to the current address in the
5560 offset_expr
.X_op
= O_symbol
;
5561 offset_expr
.X_add_symbol
=
5562 symbol_new ("L0\001", now_seg
,
5563 (valueT
) frag_now_fix (), frag_now
);
5564 offset_expr
.X_add_number
= 0;
5566 /* Put the floating point number into the section. */
5567 p
= frag_more ((int) length
);
5568 memcpy (p
, temp
, length
);
5570 /* Switch back to the original section. */
5571 subseg_set (seg
, subseg
);
5576 case 'i': /* 16 bit unsigned immediate */
5577 case 'j': /* 16 bit signed immediate */
5578 imm_reloc
= BFD_RELOC_LO16
;
5579 c
= my_getSmallExpression (&imm_expr
, s
);
5584 if (imm_expr
.X_op
== O_constant
)
5585 imm_expr
.X_add_number
=
5586 (imm_expr
.X_add_number
>> 16) & 0xffff;
5589 imm_reloc
= BFD_RELOC_HI16_S
;
5590 imm_unmatched_hi
= true;
5593 imm_reloc
= BFD_RELOC_HI16
;
5598 if (imm_expr
.X_op
!= O_constant
5599 || imm_expr
.X_add_number
< 0
5600 || imm_expr
.X_add_number
>= 0x10000)
5602 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
5603 !strcmp (insn
->name
, insn
[1].name
))
5605 if (imm_expr
.X_op
!= O_constant
5606 && imm_expr
.X_op
!= O_big
)
5607 insn_error
= "absolute expression required";
5609 as_bad ("16 bit expression not in range 0..65535");
5617 /* The upper bound should be 0x8000, but
5618 unfortunately the MIPS assembler accepts numbers
5619 from 0x8000 to 0xffff and sign extends them, and
5620 we want to be compatible. We only permit this
5621 extended range for an instruction which does not
5622 provide any further alternates, since those
5623 alternates may handle other cases. People should
5624 use the numbers they mean, rather than relying on
5625 a mysterious sign extension. */
5626 more
= (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
5627 strcmp (insn
->name
, insn
[1].name
) == 0);
5632 if (imm_expr
.X_op
!= O_constant
5633 || imm_expr
.X_add_number
< -0x8000
5634 || imm_expr
.X_add_number
>= max
5636 && imm_expr
.X_add_number
< 0
5638 && imm_expr
.X_unsigned
5639 && sizeof (imm_expr
.X_add_number
) <= 4))
5643 if (imm_expr
.X_op
!= O_constant
5644 && imm_expr
.X_op
!= O_big
)
5645 insn_error
= "absolute expression required";
5647 as_bad ("16 bit expression not in range -32768..32767");
5653 case 'o': /* 16 bit offset */
5654 c
= my_getSmallExpression (&offset_expr
, s
);
5656 /* If this value won't fit into a 16 bit offset, then go
5657 find a macro that will generate the 32 bit offset
5658 code pattern. As a special hack, we accept the
5659 difference of two local symbols as a constant. This
5660 is required to suppose embedded PIC switches, which
5661 use an instruction which looks like
5662 lw $4,$L12-$LS12($4)
5663 The problem with handling this in a more general
5664 fashion is that the macro function doesn't expect to
5665 see anything which can be handled in a single
5666 constant instruction. */
5668 && (offset_expr
.X_op
!= O_constant
5669 || offset_expr
.X_add_number
>= 0x8000
5670 || offset_expr
.X_add_number
< -0x8000)
5671 && (mips_pic
!= EMBEDDED_PIC
5672 || offset_expr
.X_op
!= O_subtract
5673 || now_seg
!= text_section
5674 || (S_GET_SEGMENT (offset_expr
.X_op_symbol
)
5678 offset_reloc
= BFD_RELOC_LO16
;
5679 if (c
== 'h' || c
== 'H')
5681 assert (offset_expr
.X_op
== O_constant
);
5682 offset_expr
.X_add_number
=
5683 (offset_expr
.X_add_number
>> 16) & 0xffff;
5688 case 'p': /* pc relative offset */
5689 offset_reloc
= BFD_RELOC_16_PCREL_S2
;
5690 my_getExpression (&offset_expr
, s
);
5694 case 'u': /* upper 16 bits */
5695 c
= my_getSmallExpression (&imm_expr
, s
);
5696 if (imm_expr
.X_op
== O_constant
5697 && (imm_expr
.X_add_number
< 0
5698 || imm_expr
.X_add_number
>= 0x10000))
5699 as_bad ("lui expression not in range 0..65535");
5700 imm_reloc
= BFD_RELOC_LO16
;
5705 if (imm_expr
.X_op
== O_constant
)
5706 imm_expr
.X_add_number
=
5707 (imm_expr
.X_add_number
>> 16) & 0xffff;
5710 imm_reloc
= BFD_RELOC_HI16_S
;
5711 imm_unmatched_hi
= true;
5714 imm_reloc
= BFD_RELOC_HI16
;
5720 case 'a': /* 26 bit address */
5721 my_getExpression (&offset_expr
, s
);
5723 offset_reloc
= BFD_RELOC_MIPS_JMP
;
5726 case 'N': /* 3 bit branch condition code */
5727 case 'M': /* 3 bit compare condition code */
5728 my_getExpression (&imm_expr
, s
);
5729 check_absolute_expr (ip
, &imm_expr
);
5730 if ((unsigned long) imm_expr
.X_add_number
> 7)
5732 as_warn ("Condition code > 7 (%ld)",
5733 (long) imm_expr
.X_add_number
);
5734 imm_expr
.X_add_number
&= 7;
5737 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_BCC
;
5739 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_CCC
;
5740 imm_expr
.X_op
= O_absent
;
5745 fprintf (stderr
, "bad char = '%c'\n", *args
);
5750 /* Args don't match. */
5751 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
5752 !strcmp (insn
->name
, insn
[1].name
))
5758 insn_error
= "illegal operands";
5767 my_getSmallExpression (ep
, str
)
5778 ((str
[1] == 'h' && str
[2] == 'i')
5779 || (str
[1] == 'H' && str
[2] == 'I')
5780 || (str
[1] == 'l' && str
[2] == 'o'))
5792 * A small expression may be followed by a base register.
5793 * Scan to the end of this operand, and then back over a possible
5794 * base register. Then scan the small expression up to that
5795 * point. (Based on code in sparc.c...)
5797 for (sp
= str
; *sp
&& *sp
!= ','; sp
++)
5799 if (sp
- 4 >= str
&& sp
[-1] == RP
)
5801 if (isdigit (sp
[-2]))
5803 for (sp
-= 3; sp
>= str
&& isdigit (*sp
); sp
--)
5805 if (*sp
== '$' && sp
> str
&& sp
[-1] == LP
)
5811 else if (sp
- 5 >= str
5814 && ((sp
[-3] == 'f' && sp
[-2] == 'p')
5815 || (sp
[-3] == 's' && sp
[-2] == 'p')
5816 || (sp
[-3] == 'g' && sp
[-2] == 'p')
5817 || (sp
[-3] == 'a' && sp
[-2] == 't')))
5823 /* no expression means zero offset */
5826 /* %xx(reg) is an error */
5827 ep
->X_op
= O_absent
;
5832 ep
->X_op
= O_constant
;
5835 ep
->X_add_symbol
= NULL
;
5836 ep
->X_op_symbol
= NULL
;
5837 ep
->X_add_number
= 0;
5842 my_getExpression (ep
, str
);
5849 my_getExpression (ep
, str
);
5850 return c
; /* => %hi or %lo encountered */
5854 my_getExpression (ep
, str
)
5860 save_in
= input_line_pointer
;
5861 input_line_pointer
= str
;
5863 expr_end
= input_line_pointer
;
5864 input_line_pointer
= save_in
;
5867 /* Turn a string in input_line_pointer into a floating point constant
5868 of type type, and store the appropriate bytes in *litP. The number
5869 of LITTLENUMS emitted is stored in *sizeP . An error message is
5870 returned, or NULL on OK. */
5873 md_atof (type
, litP
, sizeP
)
5879 LITTLENUM_TYPE words
[4];
5895 return "bad call to md_atof";
5898 t
= atof_ieee (input_line_pointer
, type
, words
);
5900 input_line_pointer
= t
;
5904 if (byte_order
== LITTLE_ENDIAN
)
5906 for (i
= prec
- 1; i
>= 0; i
--)
5908 md_number_to_chars (litP
, (valueT
) words
[i
], 2);
5914 for (i
= 0; i
< prec
; i
++)
5916 md_number_to_chars (litP
, (valueT
) words
[i
], 2);
5925 md_number_to_chars (buf
, val
, n
)
5933 number_to_chars_littleendian (buf
, val
, n
);
5937 number_to_chars_bigendian (buf
, val
, n
);
5945 CONST
char *md_shortopts
= "O::g::G:";
5947 struct option md_longopts
[] = {
5948 #define OPTION_MIPS1 (OPTION_MD_BASE + 1)
5949 {"mips0", no_argument
, NULL
, OPTION_MIPS1
},
5950 {"mips1", no_argument
, NULL
, OPTION_MIPS1
},
5951 #define OPTION_MIPS2 (OPTION_MD_BASE + 2)
5952 {"mips2", no_argument
, NULL
, OPTION_MIPS2
},
5953 #define OPTION_MIPS3 (OPTION_MD_BASE + 3)
5954 {"mips3", no_argument
, NULL
, OPTION_MIPS3
},
5955 #define OPTION_MIPS4 (OPTION_MD_BASE + 4)
5956 {"mips4", no_argument
, NULL
, OPTION_MIPS4
},
5957 #define OPTION_MCPU (OPTION_MD_BASE + 5)
5958 {"mcpu", required_argument
, NULL
, OPTION_MCPU
},
5959 #define OPTION_MEMBEDDED_PIC (OPTION_MD_BASE + 6)
5960 {"membedded-pic", no_argument
, NULL
, OPTION_MEMBEDDED_PIC
},
5961 #define OPTION_TRAP (OPTION_MD_BASE + 9)
5962 {"trap", no_argument
, NULL
, OPTION_TRAP
},
5963 {"no-break", no_argument
, NULL
, OPTION_TRAP
},
5964 #define OPTION_BREAK (OPTION_MD_BASE + 10)
5965 {"break", no_argument
, NULL
, OPTION_BREAK
},
5966 {"no-trap", no_argument
, NULL
, OPTION_BREAK
},
5967 #define OPTION_EB (OPTION_MD_BASE + 11)
5968 {"EB", no_argument
, NULL
, OPTION_EB
},
5969 #define OPTION_EL (OPTION_MD_BASE + 12)
5970 {"EL", no_argument
, NULL
, OPTION_EL
},
5971 #define OPTION_M4650 (OPTION_MD_BASE + 13)
5972 {"m4650", no_argument
, NULL
, OPTION_M4650
},
5973 #define OPTION_NO_M4650 (OPTION_MD_BASE + 14)
5974 {"no-m4650", no_argument
, NULL
, OPTION_NO_M4650
},
5975 #define OPTION_M4010 (OPTION_MD_BASE + 15)
5976 {"m4010", no_argument
, NULL
, OPTION_M4010
},
5977 #define OPTION_NO_M4010 (OPTION_MD_BASE + 16)
5978 {"no-m4010", no_argument
, NULL
, OPTION_NO_M4010
},
5979 #define OPTION_M4100 (OPTION_MD_BASE + 17)
5980 {"m4100", no_argument
, NULL
, OPTION_M4100
},
5981 #define OPTION_NO_M4100 (OPTION_MD_BASE + 18)
5982 {"no-m4100", no_argument
, NULL
, OPTION_NO_M4100
},
5984 #define OPTION_CALL_SHARED (OPTION_MD_BASE + 7)
5985 #define OPTION_NON_SHARED (OPTION_MD_BASE + 8)
5986 #define OPTION_XGOT (OPTION_MD_BASE + 19)
5987 #define OPTION_32 (OPTION_MD_BASE + 20)
5988 #define OPTION_64 (OPTION_MD_BASE + 21)
5990 {"KPIC", no_argument
, NULL
, OPTION_CALL_SHARED
},
5991 {"xgot", no_argument
, NULL
, OPTION_XGOT
},
5992 {"call_shared", no_argument
, NULL
, OPTION_CALL_SHARED
},
5993 {"non_shared", no_argument
, NULL
, OPTION_NON_SHARED
},
5994 {"32", no_argument
, NULL
, OPTION_32
},
5995 {"64", no_argument
, NULL
, OPTION_64
},
5998 {NULL
, no_argument
, NULL
, 0}
6000 size_t md_longopts_size
= sizeof(md_longopts
);
6003 md_parse_option (c
, arg
)
6018 target_big_endian
= 1;
6022 target_big_endian
= 0;
6026 if (arg
&& arg
[1] == '0')
6036 mips_debug
= atoi (arg
);
6037 /* When the MIPS assembler sees -g or -g2, it does not do
6038 optimizations which limit full symbolic debugging. We take
6039 that to be equivalent to -O0. */
6040 if (mips_debug
== 2)
6072 /* Identify the processor type */
6074 if (strcmp (p
, "default") == 0
6075 || strcmp (p
, "DEFAULT") == 0)
6081 /* We need to cope with the various "vr" prefixes for the 4300
6083 if (*p
== 'v' || *p
== 'V')
6089 if (*p
== 'r' || *p
== 'R')
6096 if (strcmp (p
, "10000") == 0
6097 || strcmp (p
, "10k") == 0
6098 || strcmp (p
, "10K") == 0)
6103 if (strcmp (p
, "2000") == 0
6104 || strcmp (p
, "2k") == 0
6105 || strcmp (p
, "2K") == 0)
6110 if (strcmp (p
, "3000") == 0
6111 || strcmp (p
, "3k") == 0
6112 || strcmp (p
, "3K") == 0)
6117 if (strcmp (p
, "4000") == 0
6118 || strcmp (p
, "4k") == 0
6119 || strcmp (p
, "4K") == 0)
6121 else if (strcmp (p
, "4100") == 0)
6127 else if (strcmp (p
, "4300") == 0)
6129 else if (strcmp (p
, "4400") == 0)
6131 else if (strcmp (p
, "4600") == 0)
6133 else if (strcmp (p
, "4650") == 0)
6139 else if (strcmp (p
, "4010") == 0)
6148 if (strcmp (p
, "6000") == 0
6149 || strcmp (p
, "6k") == 0
6150 || strcmp (p
, "6K") == 0)
6155 if (strcmp (p
, "8000") == 0
6156 || strcmp (p
, "8k") == 0
6157 || strcmp (p
, "8K") == 0)
6162 if (strcmp (p
, "orion") == 0)
6167 if (sv
&& mips_cpu
!= 4300 && mips_cpu
!= 4100)
6169 as_bad ("ignoring invalid leading 'v' in -mcpu=%s switch", arg
);
6175 as_bad ("invalid architecture -mcpu=%s", arg
);
6186 case OPTION_NO_M4650
:
6194 case OPTION_NO_M4010
:
6202 case OPTION_NO_M4100
:
6206 case OPTION_MEMBEDDED_PIC
:
6207 mips_pic
= EMBEDDED_PIC
;
6208 if (USE_GLOBAL_POINTER_OPT
&& g_switch_seen
)
6210 as_bad ("-G may not be used with embedded PIC code");
6213 g_switch_value
= 0x7fffffff;
6216 /* When generating ELF code, we permit -KPIC and -call_shared to
6217 select SVR4_PIC, and -non_shared to select no PIC. This is
6218 intended to be compatible with Irix 5. */
6219 case OPTION_CALL_SHARED
:
6220 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
6222 as_bad ("-call_shared is supported only for ELF format");
6225 mips_pic
= SVR4_PIC
;
6226 if (g_switch_seen
&& g_switch_value
!= 0)
6228 as_bad ("-G may not be used with SVR4 PIC code");
6234 case OPTION_NON_SHARED
:
6235 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
6237 as_bad ("-non_shared is supported only for ELF format");
6243 /* The -xgot option tells the assembler to use 32 offsets when
6244 accessing the got in SVR4_PIC mode. It is for Irix
6251 if (! USE_GLOBAL_POINTER_OPT
)
6253 as_bad ("-G is not supported for this configuration");
6256 else if (mips_pic
== SVR4_PIC
|| mips_pic
== EMBEDDED_PIC
)
6258 as_bad ("-G may not be used with SVR4 or embedded PIC code");
6262 g_switch_value
= atoi (arg
);
6266 /* The -32 and -64 options tell the assembler to output the 32
6267 bit or the 64 bit MIPS ELF format. */
6274 const char **list
, **l
;
6276 list
= bfd_target_list ();
6277 for (l
= list
; *l
!= NULL
; l
++)
6278 if (strcmp (*l
, "elf64-bigmips") == 0
6279 || strcmp (*l
, "elf64-littlemips") == 0)
6282 as_fatal ("No compiled in support for 64 bit object file format");
6296 md_show_usage (stream
)
6301 -membedded-pic generate embedded position independent code\n\
6302 -EB generate big endian output\n\
6303 -EL generate little endian output\n\
6304 -g, -g2 do not remove uneeded NOPs or swap branches\n\
6305 -G NUM allow referencing objects up to NUM bytes\n\
6306 implicitly with the gp register [default 8]\n");
6308 -mips1, -mcpu=r{2,3}000 generate code for r2000 and r3000\n\
6309 -mips2, -mcpu=r6000 generate code for r6000\n\
6310 -mips3, -mcpu=r4000 generate code for r4000\n\
6311 -mips4, -mcpu=r8000 generate code for r8000\n\
6312 -mcpu=vr4300 generate code for vr4300\n\
6313 -mcpu=vr4100 generate code for vr4100\n\
6314 -m4650 permit R4650 instructions\n\
6315 -no-m4650 do not permit R4650 instructions\n\
6316 -m4010 permit R4010 instructions\n\
6317 -no-m4010 do not permit R4010 instructions\n\
6318 -m4100 permit VR4100 instructions\n\
6319 -no-m4100 do not permit VR4100 instructions\n");
6321 -O0 remove unneeded NOPs, do not swap branches\n\
6322 -O remove unneeded NOPs and swap branches\n\
6323 --trap, --no-break trap exception on div by 0 and mult overflow\n\
6324 --break, --no-trap break exception on div by 0 and mult overflow\n");
6327 -KPIC, -call_shared generate SVR4 position independent code\n\
6328 -non_shared do not generate position independent code\n\
6329 -xgot assume a 32 bit GOT\n\
6330 -32 create 32 bit object file (default)\n\
6331 -64 create 64 bit object file\n");
6336 mips_init_after_args ()
6338 if (target_big_endian
)
6339 byte_order
= BIG_ENDIAN
;
6341 byte_order
= LITTLE_ENDIAN
;
6345 md_pcrel_from (fixP
)
6348 if (OUTPUT_FLAVOR
!= bfd_target_aout_flavour
6349 && fixP
->fx_addsy
!= (symbolS
*) NULL
6350 && ! S_IS_DEFINED (fixP
->fx_addsy
))
6352 /* This makes a branch to an undefined symbol be a branch to the
6353 current location. */
6357 /* return the address of the delay slot */
6358 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
6361 /* This is called by emit_expr via TC_CONS_FIX_NEW when creating a
6362 reloc for a cons. We could use the definition there, except that
6363 we want to handle 64 bit relocs specially. */
6366 cons_fix_new_mips (frag
, where
, nbytes
, exp
)
6369 unsigned int nbytes
;
6372 /* If we are assembling in 32 bit mode, turn an 8 byte reloc into a
6374 if (nbytes
== 8 && ! mips_64
)
6376 if (byte_order
== BIG_ENDIAN
)
6381 if (nbytes
!= 2 && nbytes
!= 4 && nbytes
!= 8)
6382 as_bad ("Unsupported reloc size %d", nbytes
);
6384 fix_new_exp (frag_now
, where
, (int) nbytes
, exp
, 0,
6387 : (nbytes
== 4 ? BFD_RELOC_32
: BFD_RELOC_64
)));
6390 /* Sort any unmatched HI16_S relocs so that they immediately precede
6391 the corresponding LO reloc. This is called before md_apply_fix and
6392 tc_gen_reloc. Unmatched HI16_S relocs can only be generated by
6393 explicit use of the %hi modifier. */
6398 struct mips_hi_fixup
*l
;
6400 for (l
= mips_hi_fixup_list
; l
!= NULL
; l
= l
->next
)
6402 segment_info_type
*seginfo
;
6405 assert (l
->fixp
->fx_r_type
== BFD_RELOC_HI16_S
);
6407 /* Check quickly whether the next fixup happens to be a matching
6409 if (l
->fixp
->fx_next
!= NULL
6410 && l
->fixp
->fx_next
->fx_r_type
== BFD_RELOC_LO16
6411 && l
->fixp
->fx_addsy
== l
->fixp
->fx_next
->fx_addsy
6412 && l
->fixp
->fx_offset
== l
->fixp
->fx_next
->fx_offset
)
6415 /* Look through the fixups for this segment for a matching %lo.
6416 When we find one, move the %hi just in front of it. We do
6417 this in two passes. In the first pass, we try to find a
6418 unique %lo. In the second pass, we permit multiple %hi
6419 relocs for a single %lo (this is a GNU extension). */
6420 seginfo
= seg_info (l
->seg
);
6421 for (pass
= 0; pass
< 2; pass
++)
6426 for (f
= seginfo
->fix_root
; f
!= NULL
; f
= f
->fx_next
)
6428 /* Check whether this is a %lo fixup which matches l->fixp. */
6429 if (f
->fx_r_type
== BFD_RELOC_LO16
6430 && f
->fx_addsy
== l
->fixp
->fx_addsy
6431 && f
->fx_offset
== l
->fixp
->fx_offset
6434 || prev
->fx_r_type
!= BFD_RELOC_HI16_S
6435 || prev
->fx_addsy
!= f
->fx_addsy
6436 || prev
->fx_offset
!= f
->fx_offset
))
6440 /* Move l->fixp before f. */
6441 for (pf
= &seginfo
->fix_root
;
6443 pf
= &(*pf
)->fx_next
)
6444 assert (*pf
!= NULL
);
6446 *pf
= l
->fixp
->fx_next
;
6448 l
->fixp
->fx_next
= f
;
6450 seginfo
->fix_root
= l
->fixp
;
6452 prev
->fx_next
= l
->fixp
;
6464 as_warn_where (l
->fixp
->fx_file
, l
->fixp
->fx_line
,
6465 "Unmatched %%hi reloc");
6470 /* When generating embedded PIC code we need to use a special
6471 relocation to represent the difference of two symbols in the .text
6472 section (switch tables use a difference of this sort). See
6473 include/coff/mips.h for details. This macro checks whether this
6474 fixup requires the special reloc. */
6475 #define SWITCH_TABLE(fixp) \
6476 ((fixp)->fx_r_type == BFD_RELOC_32 \
6477 && (fixp)->fx_addsy != NULL \
6478 && (fixp)->fx_subsy != NULL \
6479 && S_GET_SEGMENT ((fixp)->fx_addsy) == text_section \
6480 && S_GET_SEGMENT ((fixp)->fx_subsy) == text_section)
6482 /* When generating embedded PIC code we must keep all PC relative
6483 relocations, in case the linker has to relax a call. We also need
6484 to keep relocations for switch table entries. */
6488 mips_force_relocation (fixp
)
6491 return (mips_pic
== EMBEDDED_PIC
6493 || SWITCH_TABLE (fixp
)
6494 || fixp
->fx_r_type
== BFD_RELOC_PCREL_HI16_S
6495 || fixp
->fx_r_type
== BFD_RELOC_PCREL_LO16
));
6498 /* Apply a fixup to the object file. */
6501 md_apply_fix (fixP
, valueP
)
6508 assert (fixP
->fx_size
== 4 || fixP
->fx_r_type
== BFD_RELOC_16
);
6511 fixP
->fx_addnumber
= value
; /* Remember value for tc_gen_reloc */
6513 if (fixP
->fx_addsy
== NULL
&& ! fixP
->fx_pcrel
)
6516 switch (fixP
->fx_r_type
)
6518 case BFD_RELOC_MIPS_JMP
:
6519 case BFD_RELOC_HI16
:
6520 case BFD_RELOC_HI16_S
:
6521 case BFD_RELOC_MIPS_GPREL
:
6522 case BFD_RELOC_MIPS_LITERAL
:
6523 case BFD_RELOC_MIPS_CALL16
:
6524 case BFD_RELOC_MIPS_GOT16
:
6525 case BFD_RELOC_MIPS_GPREL32
:
6526 case BFD_RELOC_MIPS_GOT_HI16
:
6527 case BFD_RELOC_MIPS_GOT_LO16
:
6528 case BFD_RELOC_MIPS_CALL_HI16
:
6529 case BFD_RELOC_MIPS_CALL_LO16
:
6531 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
6532 "Invalid PC relative reloc");
6533 /* Nothing needed to do. The value comes from the reloc entry */
6536 case BFD_RELOC_PCREL_HI16_S
:
6537 /* The addend for this is tricky if it is internal, so we just
6538 do everything here rather than in bfd_perform_relocation. */
6539 if ((fixP
->fx_addsy
->bsym
->flags
& BSF_SECTION_SYM
) == 0)
6541 /* For an external symbol adjust by the address to make it
6542 pcrel_offset. We use the address of the RELLO reloc
6543 which follows this one. */
6544 value
+= (fixP
->fx_next
->fx_frag
->fr_address
6545 + fixP
->fx_next
->fx_where
);
6550 buf
= (unsigned char *) fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
6551 if (byte_order
== BIG_ENDIAN
)
6553 md_number_to_chars (buf
, value
, 2);
6556 case BFD_RELOC_PCREL_LO16
:
6557 /* The addend for this is tricky if it is internal, so we just
6558 do everything here rather than in bfd_perform_relocation. */
6559 if ((fixP
->fx_addsy
->bsym
->flags
& BSF_SECTION_SYM
) == 0)
6560 value
+= fixP
->fx_frag
->fr_address
+ fixP
->fx_where
;
6561 buf
= (unsigned char *) fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
6562 if (byte_order
== BIG_ENDIAN
)
6564 md_number_to_chars (buf
, value
, 2);
6568 /* If we are deleting this reloc entry, we must fill in the
6569 value now. This can happen if we have a .word which is not
6570 resolved when it appears but is later defined. We also need
6571 to fill in the value if this is an embedded PIC switch table
6574 || (mips_pic
== EMBEDDED_PIC
&& SWITCH_TABLE (fixP
)))
6575 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
,
6580 /* If we are deleting this reloc entry, we must fill in the
6582 assert (fixP
->fx_size
== 2);
6584 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
,
6588 case BFD_RELOC_LO16
:
6589 /* When handling an embedded PIC switch statement, we can wind
6590 up deleting a LO16 reloc. See the 'o' case in mips_ip. */
6593 if (value
< -0x8000 || value
> 0x7fff)
6594 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
6595 "relocation overflow");
6596 buf
= (unsigned char *) fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
6597 if (byte_order
== BIG_ENDIAN
)
6599 md_number_to_chars (buf
, value
, 2);
6603 case BFD_RELOC_16_PCREL_S2
:
6605 * We need to save the bits in the instruction since fixup_segment()
6606 * might be deleting the relocation entry (i.e., a branch within
6607 * the current segment).
6610 as_warn_where (fixP
->fx_file
, fixP
->fx_line
,
6611 "Branch to odd address (%lx)", value
);
6614 /* update old instruction data */
6615 buf
= (unsigned char *) (fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
);
6619 insn
= (buf
[3] << 24) | (buf
[2] << 16) | (buf
[1] << 8) | buf
[0];
6623 insn
= (buf
[0] << 24) | (buf
[1] << 16) | (buf
[2] << 8) | buf
[3];
6631 if (value
>= -0x8000 && value
< 0x8000)
6632 insn
|= value
& 0xffff;
6635 /* The branch offset is too large. If this is an
6636 unconditional branch, and we are not generating PIC code,
6637 we can convert it to an absolute jump instruction. */
6638 if (mips_pic
== NO_PIC
6640 && fixP
->fx_frag
->fr_address
>= text_section
->vma
6641 && (fixP
->fx_frag
->fr_address
6642 < text_section
->vma
+ text_section
->_raw_size
)
6643 && ((insn
& 0xffff0000) == 0x10000000 /* beq $0,$0 */
6644 || (insn
& 0xffff0000) == 0x04010000 /* bgez $0 */
6645 || (insn
& 0xffff0000) == 0x04110000)) /* bgezal $0 */
6647 if ((insn
& 0xffff0000) == 0x04110000) /* bgezal $0 */
6648 insn
= 0x0c000000; /* jal */
6650 insn
= 0x08000000; /* j */
6651 fixP
->fx_r_type
= BFD_RELOC_MIPS_JMP
;
6653 fixP
->fx_addsy
= section_symbol (text_section
);
6654 fixP
->fx_addnumber
= (value
<< 2) + md_pcrel_from (fixP
);
6658 /* FIXME. It would be possible in principle to handle
6659 conditional branches which overflow. They could be
6660 transformed into a branch around a jump. This would
6661 require setting up variant frags for each different
6662 branch type. The native MIPS assembler attempts to
6663 handle these cases, but it appears to do it
6665 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
6666 "Relocation overflow");
6670 md_number_to_chars ((char *) buf
, (valueT
) insn
, 4);
6685 const struct mips_opcode
*p
;
6686 int treg
, sreg
, dreg
, shamt
;
6691 for (i
= 0; i
< NUMOPCODES
; ++i
)
6693 p
= &mips_opcodes
[i
];
6694 if (((oc
& p
->mask
) == p
->match
) && (p
->pinfo
!= INSN_MACRO
))
6696 printf ("%08lx %s\t", oc
, p
->name
);
6697 treg
= (oc
>> 16) & 0x1f;
6698 sreg
= (oc
>> 21) & 0x1f;
6699 dreg
= (oc
>> 11) & 0x1f;
6700 shamt
= (oc
>> 6) & 0x1f;
6702 for (args
= p
->args
;; ++args
)
6713 printf ("%c", *args
);
6717 assert (treg
== sreg
);
6718 printf ("$%d,$%d", treg
, sreg
);
6723 printf ("$%d", dreg
);
6728 printf ("$%d", treg
);
6732 printf ("0x%x", treg
);
6737 printf ("$%d", sreg
);
6741 printf ("0x%08lx", oc
& 0x1ffffff);
6753 printf ("$%d", shamt
);
6764 printf ("%08lx UNDEFINED\n", oc
);
6775 name
= input_line_pointer
;
6776 c
= get_symbol_end ();
6777 p
= (symbolS
*) symbol_find_or_make (name
);
6778 *input_line_pointer
= c
;
6782 /* Align the current frag to a given power of two. The MIPS assembler
6783 also automatically adjusts any preceding label. */
6786 mips_align (to
, fill
, label
)
6791 mips_emit_delays ();
6792 frag_align (to
, fill
);
6793 record_alignment (now_seg
, to
);
6796 assert (S_GET_SEGMENT (label
) == now_seg
);
6797 label
->sy_frag
= frag_now
;
6798 S_SET_VALUE (label
, (valueT
) frag_now_fix ());
6802 /* Align to a given power of two. .align 0 turns off the automatic
6803 alignment used by the data creating pseudo-ops. */
6810 register long temp_fill
;
6811 long max_alignment
= 15;
6815 o Note that the assembler pulls down any immediately preceeding label
6816 to the aligned address.
6817 o It's not documented but auto alignment is reinstated by
6818 a .align pseudo instruction.
6819 o Note also that after auto alignment is turned off the mips assembler
6820 issues an error on attempt to assemble an improperly aligned data item.
6825 temp
= get_absolute_expression ();
6826 if (temp
> max_alignment
)
6827 as_bad ("Alignment too large: %d. assumed.", temp
= max_alignment
);
6830 as_warn ("Alignment negative: 0 assumed.");
6833 if (*input_line_pointer
== ',')
6835 input_line_pointer
++;
6836 temp_fill
= get_absolute_expression ();
6843 mips_align (temp
, (int) temp_fill
, insn_label
);
6850 demand_empty_rest_of_line ();
6854 mips_flush_pending_output ()
6856 mips_emit_delays ();
6866 /* When generating embedded PIC code, we only use the .text, .lit8,
6867 .sdata and .sbss sections. We change the .data and .rdata
6868 pseudo-ops to use .sdata. */
6869 if (mips_pic
== EMBEDDED_PIC
6870 && (sec
== 'd' || sec
== 'r'))
6873 mips_emit_delays ();
6883 subseg_set (bss_section
, (subsegT
) get_absolute_expression ());
6884 demand_empty_rest_of_line ();
6888 if (USE_GLOBAL_POINTER_OPT
)
6890 seg
= subseg_new (RDATA_SECTION_NAME
,
6891 (subsegT
) get_absolute_expression ());
6892 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
6894 bfd_set_section_flags (stdoutput
, seg
,
6900 bfd_set_section_alignment (stdoutput
, seg
, 4);
6902 demand_empty_rest_of_line ();
6906 as_bad ("No read only data section in this object file format");
6907 demand_empty_rest_of_line ();
6913 if (USE_GLOBAL_POINTER_OPT
)
6915 seg
= subseg_new (".sdata", (subsegT
) get_absolute_expression ());
6916 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
6918 bfd_set_section_flags (stdoutput
, seg
,
6919 SEC_ALLOC
| SEC_LOAD
| SEC_RELOC
6921 bfd_set_section_alignment (stdoutput
, seg
, 4);
6923 demand_empty_rest_of_line ();
6928 as_bad ("Global pointers not supported; recompile -G 0");
6929 demand_empty_rest_of_line ();
6938 mips_enable_auto_align ()
6950 mips_emit_delays ();
6951 if (log_size
> 0 && auto_align
)
6952 mips_align (log_size
, 0, label
);
6954 cons (1 << log_size
);
6965 mips_emit_delays ();
6969 mips_align (3, 0, label
);
6971 mips_align (2, 0, label
);
6978 /* Handle .globl. We need to override it because on Irix 5 you are
6981 where foo is an undefined symbol, to mean that foo should be
6982 considered to be the address of a function. */
6993 name
= input_line_pointer
;
6994 c
= get_symbol_end ();
6995 symbolP
= symbol_find_or_make (name
);
6996 *input_line_pointer
= c
;
6999 /* On Irix 5, every global symbol that is not explicitly labelled as
7000 being a function is apparently labelled as being an object. */
7003 if (! is_end_of_line
[(unsigned char) *input_line_pointer
])
7008 secname
= input_line_pointer
;
7009 c
= get_symbol_end ();
7010 sec
= bfd_get_section_by_name (stdoutput
, secname
);
7012 as_bad ("%s: no such section", secname
);
7013 *input_line_pointer
= c
;
7015 if (sec
!= NULL
&& (sec
->flags
& SEC_CODE
) != 0)
7016 flag
= BSF_FUNCTION
;
7019 symbolP
->bsym
->flags
|= flag
;
7021 S_SET_EXTERNAL (symbolP
);
7022 demand_empty_rest_of_line ();
7032 opt
= input_line_pointer
;
7033 c
= get_symbol_end ();
7037 /* FIXME: What does this mean? */
7039 else if (strncmp (opt
, "pic", 3) == 0)
7047 mips_pic
= SVR4_PIC
;
7049 as_bad (".option pic%d not supported", i
);
7051 if (USE_GLOBAL_POINTER_OPT
&& mips_pic
== SVR4_PIC
)
7053 if (g_switch_seen
&& g_switch_value
!= 0)
7054 as_warn ("-G may not be used with SVR4 PIC code");
7056 bfd_set_gp_size (stdoutput
, 0);
7060 as_warn ("Unrecognized option \"%s\"", opt
);
7062 *input_line_pointer
= c
;
7063 demand_empty_rest_of_line ();
7070 char *name
= input_line_pointer
, ch
;
7072 while (!is_end_of_line
[(unsigned char) *input_line_pointer
])
7073 input_line_pointer
++;
7074 ch
= *input_line_pointer
;
7075 *input_line_pointer
= '\0';
7077 if (strcmp (name
, "reorder") == 0)
7081 prev_insn_unreordered
= 1;
7082 prev_prev_insn_unreordered
= 1;
7086 else if (strcmp (name
, "noreorder") == 0)
7088 mips_emit_delays ();
7090 mips_any_noreorder
= 1;
7092 else if (strcmp (name
, "at") == 0)
7096 else if (strcmp (name
, "noat") == 0)
7100 else if (strcmp (name
, "macro") == 0)
7102 mips_warn_about_macros
= 0;
7104 else if (strcmp (name
, "nomacro") == 0)
7106 if (mips_noreorder
== 0)
7107 as_bad ("`noreorder' must be set before `nomacro'");
7108 mips_warn_about_macros
= 1;
7110 else if (strcmp (name
, "move") == 0 || strcmp (name
, "novolatile") == 0)
7114 else if (strcmp (name
, "nomove") == 0 || strcmp (name
, "volatile") == 0)
7118 else if (strcmp (name
, "bopt") == 0)
7122 else if (strcmp (name
, "nobopt") == 0)
7126 else if (strncmp (name
, "mips", 4) == 0)
7130 /* Permit the user to change the ISA on the fly. Needless to
7131 say, misuse can cause serious problems. */
7132 isa
= atoi (name
+ 4);
7134 mips_isa
= file_mips_isa
;
7135 else if (isa
< 1 || isa
> 4)
7136 as_bad ("unknown ISA level");
7142 as_warn ("Tried to set unrecognized symbol: %s\n", name
);
7144 *input_line_pointer
= ch
;
7145 demand_empty_rest_of_line ();
7148 /* Handle the .abicalls pseudo-op. I believe this is equivalent to
7149 .option pic2. It means to generate SVR4 PIC calls. */
7155 mips_pic
= SVR4_PIC
;
7156 if (USE_GLOBAL_POINTER_OPT
)
7158 if (g_switch_seen
&& g_switch_value
!= 0)
7159 as_warn ("-G may not be used with SVR4 PIC code");
7162 bfd_set_gp_size (stdoutput
, 0);
7163 demand_empty_rest_of_line ();
7166 /* Handle the .cpload pseudo-op. This is used when generating SVR4
7167 PIC code. It sets the $gp register for the function based on the
7168 function address, which is in the register named in the argument.
7169 This uses a relocation against _gp_disp, which is handled specially
7170 by the linker. The result is:
7171 lui $gp,%hi(_gp_disp)
7172 addiu $gp,$gp,%lo(_gp_disp)
7173 addu $gp,$gp,.cpload argument
7174 The .cpload argument is normally $25 == $t9. */
7183 /* If we are not generating SVR4 PIC code, .cpload is ignored. */
7184 if (mips_pic
!= SVR4_PIC
)
7190 /* .cpload should be a in .set noreorder section. */
7191 if (mips_noreorder
== 0)
7192 as_warn (".cpload not in noreorder section");
7195 ex
.X_add_symbol
= symbol_find_or_make ("_gp_disp");
7196 ex
.X_op_symbol
= NULL
;
7197 ex
.X_add_number
= 0;
7199 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
7200 ex
.X_add_symbol
->bsym
->flags
|= BSF_OBJECT
;
7202 macro_build_lui ((char *) NULL
, &icnt
, &ex
, GP
);
7203 macro_build ((char *) NULL
, &icnt
, &ex
, "addiu", "t,r,j", GP
, GP
,
7204 (int) BFD_RELOC_LO16
);
7206 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "addu", "d,v,t",
7207 GP
, GP
, tc_get_register (0));
7209 demand_empty_rest_of_line ();
7212 /* Handle the .cprestore pseudo-op. This stores $gp into a given
7213 offset from $sp. The offset is remembered, and after making a PIC
7214 call $gp is restored from that location. */
7217 s_cprestore (ignore
)
7223 /* If we are not generating SVR4 PIC code, .cprestore is ignored. */
7224 if (mips_pic
!= SVR4_PIC
)
7230 mips_cprestore_offset
= get_absolute_expression ();
7232 ex
.X_op
= O_constant
;
7233 ex
.X_add_symbol
= NULL
;
7234 ex
.X_op_symbol
= NULL
;
7235 ex
.X_add_number
= mips_cprestore_offset
;
7237 macro_build ((char *) NULL
, &icnt
, &ex
,
7238 mips_isa
< 3 ? "sw" : "sd",
7239 "t,o(b)", GP
, (int) BFD_RELOC_LO16
, SP
);
7241 demand_empty_rest_of_line ();
7244 /* Handle the .gpword pseudo-op. This is used when generating PIC
7245 code. It generates a 32 bit GP relative reloc. */
7255 /* When not generating PIC code, this is treated as .word. */
7256 if (mips_pic
!= SVR4_PIC
)
7263 mips_emit_delays ();
7265 mips_align (2, 0, label
);
7270 if (ex
.X_op
!= O_symbol
|| ex
.X_add_number
!= 0)
7272 as_bad ("Unsupported use of .gpword");
7273 ignore_rest_of_line ();
7277 md_number_to_chars (p
, (valueT
) 0, 4);
7278 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 4, &ex
, 0,
7279 BFD_RELOC_MIPS_GPREL32
);
7281 demand_empty_rest_of_line ();
7284 /* Handle the .cpadd pseudo-op. This is used when dealing with switch
7285 tables in SVR4 PIC code. */
7294 /* This is ignored when not generating SVR4 PIC code. */
7295 if (mips_pic
!= SVR4_PIC
)
7301 /* Add $gp to the register named as an argument. */
7302 reg
= tc_get_register (0);
7303 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
7304 mips_isa
< 3 ? "addu" : "daddu",
7305 "d,v,t", reg
, reg
, GP
);
7307 demand_empty_rest_of_line ();
7310 /* Parse a register string into a number. Called from the ECOFF code
7311 to parse .frame. The argument is non-zero if this is the frame
7312 register, so that we can record it in mips_frame_reg. */
7315 tc_get_register (frame
)
7321 if (*input_line_pointer
++ != '$')
7323 as_warn ("expected `$'");
7326 else if (isdigit ((unsigned char) *input_line_pointer
))
7328 reg
= get_absolute_expression ();
7329 if (reg
< 0 || reg
>= 32)
7331 as_warn ("Bad register number");
7337 if (strncmp (input_line_pointer
, "fp", 2) == 0)
7339 else if (strncmp (input_line_pointer
, "sp", 2) == 0)
7341 else if (strncmp (input_line_pointer
, "gp", 2) == 0)
7343 else if (strncmp (input_line_pointer
, "at", 2) == 0)
7347 as_warn ("Unrecognized register name");
7350 input_line_pointer
+= 2;
7353 mips_frame_reg
= reg
!= 0 ? reg
: SP
;
7358 md_section_align (seg
, addr
)
7362 int align
= bfd_get_section_alignment (stdoutput
, seg
);
7364 return ((addr
+ (1 << align
) - 1) & (-1 << align
));
7367 /* Utility routine, called from above as well. If called while the
7368 input file is still being read, it's only an approximation. (For
7369 example, a symbol may later become defined which appeared to be
7370 undefined earlier.) */
7373 nopic_need_relax (sym
)
7379 if (USE_GLOBAL_POINTER_OPT
)
7381 const char *symname
;
7384 /* Find out whether this symbol can be referenced off the GP
7385 register. It can be if it is smaller than the -G size or if
7386 it is in the .sdata or .sbss section. Certain symbols can
7387 not be referenced off the GP, although it appears as though
7389 symname
= S_GET_NAME (sym
);
7390 if (symname
!= (const char *) NULL
7391 && (strcmp (symname
, "eprol") == 0
7392 || strcmp (symname
, "etext") == 0
7393 || strcmp (symname
, "_gp") == 0
7394 || strcmp (symname
, "edata") == 0
7395 || strcmp (symname
, "_fbss") == 0
7396 || strcmp (symname
, "_fdata") == 0
7397 || strcmp (symname
, "_ftext") == 0
7398 || strcmp (symname
, "end") == 0
7399 || strcmp (symname
, "_gp_disp") == 0))
7401 else if (! S_IS_DEFINED (sym
)
7403 #ifndef NO_ECOFF_DEBUGGING
7404 || (sym
->ecoff_extern_size
!= 0
7405 && sym
->ecoff_extern_size
<= g_switch_value
)
7407 || (S_GET_VALUE (sym
) != 0
7408 && S_GET_VALUE (sym
) <= g_switch_value
)))
7412 const char *segname
;
7414 segname
= segment_name (S_GET_SEGMENT (sym
));
7415 assert (strcmp (segname
, ".lit8") != 0
7416 && strcmp (segname
, ".lit4") != 0);
7417 change
= (strcmp (segname
, ".sdata") != 0
7418 && strcmp (segname
, ".sbss") != 0);
7423 /* We are not optimizing for the GP register. */
7427 /* Estimate the size of a frag before relaxing. We are not really
7428 relaxing here, and the final size is encoded in the subtype
7433 md_estimate_size_before_relax (fragp
, segtype
)
7439 if (mips_pic
== NO_PIC
)
7441 change
= nopic_need_relax (fragp
->fr_symbol
);
7443 else if (mips_pic
== SVR4_PIC
)
7445 asection
*symsec
= fragp
->fr_symbol
->bsym
->section
;
7447 /* This must duplicate the test in adjust_reloc_syms. */
7448 change
= (symsec
!= &bfd_und_section
7449 && symsec
!= &bfd_abs_section
7450 && ! bfd_is_com_section (symsec
));
7457 /* Record the offset to the first reloc in the fr_opcode field.
7458 This lets md_convert_frag and tc_gen_reloc know that the code
7459 must be expanded. */
7460 fragp
->fr_opcode
= (fragp
->fr_literal
7462 - RELAX_OLD (fragp
->fr_subtype
)
7463 + RELAX_RELOC1 (fragp
->fr_subtype
));
7464 /* FIXME: This really needs as_warn_where. */
7465 if (RELAX_WARN (fragp
->fr_subtype
))
7466 as_warn ("AT used after \".set noat\" or macro used after \".set nomacro\"");
7472 return RELAX_NEW (fragp
->fr_subtype
) - RELAX_OLD (fragp
->fr_subtype
);
7475 /* Translate internal representation of relocation info to BFD target
7479 tc_gen_reloc (section
, fixp
)
7483 static arelent
*retval
[4];
7486 reloc
= retval
[0] = (arelent
*) xmalloc (sizeof (arelent
));
7489 reloc
->sym_ptr_ptr
= &fixp
->fx_addsy
->bsym
;
7490 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
7492 if (mips_pic
== EMBEDDED_PIC
7493 && SWITCH_TABLE (fixp
))
7495 /* For a switch table entry we use a special reloc. The addend
7496 is actually the difference between the reloc address and the
7498 reloc
->addend
= reloc
->address
- S_GET_VALUE (fixp
->fx_subsy
);
7499 if (OUTPUT_FLAVOR
!= bfd_target_ecoff_flavour
)
7500 as_fatal ("Double check fx_r_type in tc-mips.c:tc_gen_reloc");
7501 fixp
->fx_r_type
= BFD_RELOC_GPREL32
;
7503 else if (fixp
->fx_r_type
== BFD_RELOC_PCREL_LO16
)
7505 /* We use a special addend for an internal RELLO reloc. */
7506 if (fixp
->fx_addsy
->bsym
->flags
& BSF_SECTION_SYM
)
7507 reloc
->addend
= reloc
->address
- S_GET_VALUE (fixp
->fx_subsy
);
7509 reloc
->addend
= fixp
->fx_addnumber
+ reloc
->address
;
7511 else if (fixp
->fx_r_type
== BFD_RELOC_PCREL_HI16_S
)
7513 assert (fixp
->fx_next
!= NULL
7514 && fixp
->fx_next
->fx_r_type
== BFD_RELOC_PCREL_LO16
);
7515 /* We use a special addend for an internal RELHI reloc. The
7516 reloc is relative to the RELLO; adjust the addend
7518 if (fixp
->fx_addsy
->bsym
->flags
& BSF_SECTION_SYM
)
7519 reloc
->addend
= (fixp
->fx_next
->fx_frag
->fr_address
7520 + fixp
->fx_next
->fx_where
7521 - S_GET_VALUE (fixp
->fx_subsy
));
7523 reloc
->addend
= (fixp
->fx_addnumber
7524 + fixp
->fx_next
->fx_frag
->fr_address
7525 + fixp
->fx_next
->fx_where
);
7527 else if (fixp
->fx_pcrel
== 0)
7528 reloc
->addend
= fixp
->fx_addnumber
;
7531 if (OUTPUT_FLAVOR
!= bfd_target_aout_flavour
)
7532 /* A gruesome hack which is a result of the gruesome gas reloc
7534 reloc
->addend
= reloc
->address
;
7536 reloc
->addend
= -reloc
->address
;
7539 /* If this is a variant frag, we may need to adjust the existing
7540 reloc and generate a new one. */
7541 if (fixp
->fx_frag
->fr_opcode
!= NULL
7542 && (fixp
->fx_r_type
== BFD_RELOC_MIPS_GPREL
7543 || fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT16
7544 || fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL16
7545 || fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT_HI16
7546 || fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT_LO16
7547 || fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL_HI16
7548 || fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL_LO16
))
7552 /* If this is not the last reloc in this frag, then we have two
7553 GPREL relocs, or a GOT_HI16/GOT_LO16 pair, or a
7554 CALL_HI16/CALL_LO16, both of which are being replaced. Let
7555 the second one handle all of them. */
7556 if (fixp
->fx_next
!= NULL
7557 && fixp
->fx_frag
== fixp
->fx_next
->fx_frag
)
7559 assert ((fixp
->fx_r_type
== BFD_RELOC_MIPS_GPREL
7560 && fixp
->fx_next
->fx_r_type
== BFD_RELOC_MIPS_GPREL
)
7561 || (fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT_HI16
7562 && (fixp
->fx_next
->fx_r_type
7563 == BFD_RELOC_MIPS_GOT_LO16
))
7564 || (fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL_HI16
7565 && (fixp
->fx_next
->fx_r_type
7566 == BFD_RELOC_MIPS_CALL_LO16
)));
7571 fixp
->fx_where
= fixp
->fx_frag
->fr_opcode
- fixp
->fx_frag
->fr_literal
;
7572 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
7573 reloc2
= retval
[1] = (arelent
*) xmalloc (sizeof (arelent
));
7575 reloc2
->sym_ptr_ptr
= &fixp
->fx_addsy
->bsym
;
7576 reloc2
->address
= (reloc
->address
7577 + (RELAX_RELOC2 (fixp
->fx_frag
->fr_subtype
)
7578 - RELAX_RELOC1 (fixp
->fx_frag
->fr_subtype
)));
7579 reloc2
->addend
= fixp
->fx_addnumber
;
7580 reloc2
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_LO16
);
7581 assert (reloc2
->howto
!= NULL
);
7583 if (RELAX_RELOC3 (fixp
->fx_frag
->fr_subtype
))
7587 reloc3
= retval
[2] = (arelent
*) xmalloc (sizeof (arelent
));
7590 reloc3
->address
+= 4;
7593 if (mips_pic
== NO_PIC
)
7595 assert (fixp
->fx_r_type
== BFD_RELOC_MIPS_GPREL
);
7596 fixp
->fx_r_type
= BFD_RELOC_HI16_S
;
7598 else if (mips_pic
== SVR4_PIC
)
7600 switch (fixp
->fx_r_type
)
7604 case BFD_RELOC_MIPS_GOT16
:
7606 case BFD_RELOC_MIPS_CALL16
:
7607 case BFD_RELOC_MIPS_GOT_LO16
:
7608 case BFD_RELOC_MIPS_CALL_LO16
:
7609 fixp
->fx_r_type
= BFD_RELOC_MIPS_GOT16
;
7617 /* To support a PC relative reloc when generating embedded PIC code
7618 for ECOFF, we use a Cygnus extension. We check for that here to
7619 make sure that we don't let such a reloc escape normally. */
7620 if (OUTPUT_FLAVOR
== bfd_target_ecoff_flavour
7621 && fixp
->fx_r_type
== BFD_RELOC_16_PCREL_S2
7622 && mips_pic
!= EMBEDDED_PIC
)
7623 reloc
->howto
= NULL
;
7625 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, fixp
->fx_r_type
);
7627 if (reloc
->howto
== NULL
)
7629 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
7630 "Can not represent relocation in this object file format");
7637 /* Convert a machine dependent frag. */
7640 md_convert_frag (abfd
, asec
, fragp
)
7648 if (fragp
->fr_opcode
== NULL
)
7651 old
= RELAX_OLD (fragp
->fr_subtype
);
7652 new = RELAX_NEW (fragp
->fr_subtype
);
7653 fixptr
= fragp
->fr_literal
+ fragp
->fr_fix
;
7656 memcpy (fixptr
- old
, fixptr
, new);
7658 fragp
->fr_fix
+= new - old
;
7661 /* This function is called whenever a label is defined. It is used
7662 when handling branch delays; if a branch has a label, we assume we
7666 mips_define_label (sym
)
7672 /* Decide whether a label is local. This is called by LOCAL_LABEL.
7673 In order to work with gcc when using mips-tfile, we must keep all
7674 local labels. However, in other cases, we want to discard them,
7675 since they are useless. */
7678 mips_local_label (name
)
7681 #ifndef NO_ECOFF_DEBUGGING
7684 && ! ecoff_debugging_seen
)
7686 /* We were called with -g, but we didn't see any debugging
7687 information. That may mean that gcc is smuggling debugging
7688 information through to mips-tfile, in which case we must
7689 generate all local labels. */
7694 /* Here it's OK to discard local labels. */
7696 return name
[0] == '$';
7699 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7701 /* Some special processing for a MIPS ELF file. */
7704 mips_elf_final_processing ()
7706 /* Write out the register information. */
7711 s
.ri_gprmask
= mips_gprmask
;
7712 s
.ri_cprmask
[0] = mips_cprmask
[0];
7713 s
.ri_cprmask
[1] = mips_cprmask
[1];
7714 s
.ri_cprmask
[2] = mips_cprmask
[2];
7715 s
.ri_cprmask
[3] = mips_cprmask
[3];
7716 /* The gp_value field is set by the MIPS ELF backend. */
7718 bfd_mips_elf32_swap_reginfo_out (stdoutput
, &s
,
7719 ((Elf32_External_RegInfo
*)
7720 mips_regmask_frag
));
7724 Elf64_Internal_RegInfo s
;
7726 s
.ri_gprmask
= mips_gprmask
;
7728 s
.ri_cprmask
[0] = mips_cprmask
[0];
7729 s
.ri_cprmask
[1] = mips_cprmask
[1];
7730 s
.ri_cprmask
[2] = mips_cprmask
[2];
7731 s
.ri_cprmask
[3] = mips_cprmask
[3];
7732 /* The gp_value field is set by the MIPS ELF backend. */
7734 bfd_mips_elf64_swap_reginfo_out (stdoutput
, &s
,
7735 ((Elf64_External_RegInfo
*)
7736 mips_regmask_frag
));
7739 /* Set the MIPS ELF flag bits. FIXME: There should probably be some
7740 sort of BFD interface for this. */
7741 if (mips_any_noreorder
)
7742 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_NOREORDER
;
7743 if (mips_pic
!= NO_PIC
)
7744 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_PIC
;
7747 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */
7749 /* These functions should really be defined by the object file format,
7750 since they are related to debugging information. However, this
7751 code has to work for the a.out format, which does not define them,
7752 so we provide simple versions here. These don't actually generate
7753 any debugging information, but they do simple checking and someday
7754 somebody may make them useful. */
7758 struct loc
*loc_next
;
7759 unsigned long loc_fileno
;
7760 unsigned long loc_lineno
;
7761 unsigned long loc_offset
;
7762 unsigned short loc_delta
;
7763 unsigned short loc_count
;
7772 struct proc
*proc_next
;
7773 struct symbol
*proc_isym
;
7774 struct symbol
*proc_end
;
7775 unsigned long proc_reg_mask
;
7776 unsigned long proc_reg_offset
;
7777 unsigned long proc_fpreg_mask
;
7778 unsigned long proc_fpreg_offset
;
7779 unsigned long proc_frameoffset
;
7780 unsigned long proc_framereg
;
7781 unsigned long proc_pcreg
;
7783 struct file
*proc_file
;
7790 struct file
*file_next
;
7791 unsigned long file_fileno
;
7792 struct symbol
*file_symbol
;
7793 struct symbol
*file_end
;
7794 struct proc
*file_proc
;
7799 static struct obstack proc_frags
;
7800 static procS
*proc_lastP
;
7801 static procS
*proc_rootP
;
7802 static int numprocs
;
7807 obstack_begin (&proc_frags
, 0x2000);
7813 /* check for premature end, nesting errors, etc */
7814 if (proc_lastP
&& proc_lastP
->proc_end
== NULL
)
7815 as_warn ("missing `.end' at end of assembly");
7824 if (*input_line_pointer
== '-')
7826 ++input_line_pointer
;
7829 if (!isdigit (*input_line_pointer
))
7830 as_bad ("Expected simple number.");
7831 if (input_line_pointer
[0] == '0')
7833 if (input_line_pointer
[1] == 'x')
7835 input_line_pointer
+= 2;
7836 while (isxdigit (*input_line_pointer
))
7839 val
|= hex_value (*input_line_pointer
++);
7841 return negative
? -val
: val
;
7845 ++input_line_pointer
;
7846 while (isdigit (*input_line_pointer
))
7849 val
|= *input_line_pointer
++ - '0';
7851 return negative
? -val
: val
;
7854 if (!isdigit (*input_line_pointer
))
7856 printf (" *input_line_pointer == '%c' 0x%02x\n",
7857 *input_line_pointer
, *input_line_pointer
);
7858 as_warn ("Invalid number");
7861 while (isdigit (*input_line_pointer
))
7864 val
+= *input_line_pointer
++ - '0';
7866 return negative
? -val
: val
;
7869 /* The .file directive; just like the usual .file directive, but there
7870 is an initial number which is the ECOFF file index. */
7878 line
= get_number ();
7883 /* The .end directive. */
7891 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
7894 demand_empty_rest_of_line ();
7898 if (now_seg
!= text_section
)
7899 as_warn (".end not in text section");
7902 as_warn (".end and no .ent seen yet.");
7908 assert (S_GET_NAME (p
));
7909 if (strcmp (S_GET_NAME (p
), S_GET_NAME (proc_lastP
->proc_isym
)))
7910 as_warn (".end symbol does not match .ent symbol.");
7913 proc_lastP
->proc_end
= (symbolS
*) 1;
7916 /* The .aent and .ent directives. */
7926 symbolP
= get_symbol ();
7927 if (*input_line_pointer
== ',')
7928 input_line_pointer
++;
7930 if (isdigit (*input_line_pointer
) || *input_line_pointer
== '-')
7931 number
= get_number ();
7932 if (now_seg
!= text_section
)
7933 as_warn (".ent or .aent not in text section.");
7935 if (!aent
&& proc_lastP
&& proc_lastP
->proc_end
== NULL
)
7936 as_warn ("missing `.end'");
7940 procP
= (procS
*) obstack_alloc (&proc_frags
, sizeof (*procP
));
7941 procP
->proc_isym
= symbolP
;
7942 procP
->proc_reg_mask
= 0;
7943 procP
->proc_reg_offset
= 0;
7944 procP
->proc_fpreg_mask
= 0;
7945 procP
->proc_fpreg_offset
= 0;
7946 procP
->proc_frameoffset
= 0;
7947 procP
->proc_framereg
= 0;
7948 procP
->proc_pcreg
= 0;
7949 procP
->proc_end
= NULL
;
7950 procP
->proc_next
= NULL
;
7952 proc_lastP
->proc_next
= procP
;
7958 demand_empty_rest_of_line ();
7961 /* The .frame directive. */
7974 frame_reg
= tc_get_register (1);
7975 if (*input_line_pointer
== ',')
7976 input_line_pointer
++;
7977 frame_off
= get_absolute_expression ();
7978 if (*input_line_pointer
== ',')
7979 input_line_pointer
++;
7980 pcreg
= tc_get_register (0);
7983 assert (proc_rootP
);
7984 proc_rootP
->proc_framereg
= frame_reg
;
7985 proc_rootP
->proc_frameoffset
= frame_off
;
7986 proc_rootP
->proc_pcreg
= pcreg
;
7987 /* bob macho .frame */
7989 /* We don't have to write out a frame stab for unoptimized code. */
7990 if (!(frame_reg
== FP
&& frame_off
== 0))
7993 as_warn ("No .ent for .frame to use.");
7994 (void) sprintf (str
, "R%d;%d", frame_reg
, frame_off
);
7995 symP
= symbol_new (str
, N_VFP
, 0, frag_now
);
7996 S_SET_TYPE (symP
, N_RMASK
);
7997 S_SET_OTHER (symP
, 0);
7998 S_SET_DESC (symP
, 0);
7999 symP
->sy_forward
= proc_lastP
->proc_isym
;
8000 /* bob perhaps I should have used pseudo set */
8002 demand_empty_rest_of_line ();
8006 /* The .fmask and .mask directives. */
8013 char str
[100], *strP
;
8019 mask
= get_number ();
8020 if (*input_line_pointer
== ',')
8021 input_line_pointer
++;
8022 off
= get_absolute_expression ();
8024 /* bob only for coff */
8025 assert (proc_rootP
);
8026 if (reg_type
== 'F')
8028 proc_rootP
->proc_fpreg_mask
= mask
;
8029 proc_rootP
->proc_fpreg_offset
= off
;
8033 proc_rootP
->proc_reg_mask
= mask
;
8034 proc_rootP
->proc_reg_offset
= off
;
8037 /* bob macho .mask + .fmask */
8039 /* We don't have to write out a mask stab if no saved regs. */
8043 as_warn ("No .ent for .mask to use.");
8045 for (i
= 0; i
< 32; i
++)
8049 sprintf (strP
, "%c%d,", reg_type
, i
);
8050 strP
+= strlen (strP
);
8054 sprintf (strP
, ";%d,", off
);
8055 symP
= symbol_new (str
, N_RMASK
, 0, frag_now
);
8056 S_SET_TYPE (symP
, N_RMASK
);
8057 S_SET_OTHER (symP
, 0);
8058 S_SET_DESC (symP
, 0);
8059 symP
->sy_forward
= proc_lastP
->proc_isym
;
8060 /* bob perhaps I should have used pseudo set */
8065 /* The .loc directive. */
8076 assert (now_seg
== text_section
);
8078 lineno
= get_number ();
8079 addroff
= frag_now_fix ();
8081 symbolP
= symbol_new ("", N_SLINE
, addroff
, frag_now
);
8082 S_SET_TYPE (symbolP
, N_SLINE
);
8083 S_SET_OTHER (symbolP
, 0);
8084 S_SET_DESC (symbolP
, lineno
);
8085 symbolP
->sy_segment
= now_seg
;