1 /* tc-mips.c -- assemble code for a MIPS chip.
2 Copyright (C) 1993, 1995, 1996 Free Software Foundation, Inc.
3 Contributed by the OSF and Ralph Campbell.
4 Written by Keith Knowles and Ralph Campbell, working independently.
5 Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus
8 This file is part of GAS.
10 GAS is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 2, or (at your option)
15 GAS is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with GAS; see the file COPYING. If not, write to the Free
22 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
28 #include "libiberty.h"
39 #include "opcode/mips.h"
42 /* Clean up namespace so we can include obj-elf.h too. */
43 static int mips_output_flavor () { return OUTPUT_FLAVOR
; }
44 #undef OBJ_PROCESS_STAB
50 #undef TARGET_SYMBOL_FIELDS
52 #undef obj_frob_symbol
54 #undef obj_sec_sym_ok_for_reloc
57 /* Fix any of them that we actually care about. */
59 #define OUTPUT_FLAVOR mips_output_flavor()
66 #ifndef ECOFF_DEBUGGING
67 #define NO_ECOFF_DEBUGGING
68 #define ECOFF_DEBUGGING 0
73 static char *mips_regmask_frag
;
76 #define PIC_CALL_REG 25
84 extern int target_big_endian
;
86 /* 1 is we should use the 64 bit MIPS ELF ABI, 0 if we should use the
87 32 bit ABI. This has no meaning for ECOFF. */
90 /* The default target format to use. */
94 switch (OUTPUT_FLAVOR
)
96 case bfd_target_aout_flavour
:
97 return target_big_endian
? "a.out-mips-big" : "a.out-mips-little";
98 case bfd_target_ecoff_flavour
:
99 return target_big_endian
? "ecoff-bigmips" : "ecoff-littlemips";
100 case bfd_target_elf_flavour
:
101 return (target_big_endian
102 ? (mips_64
? "elf64-bigmips" : "elf32-bigmips")
103 : (mips_64
? "elf64-littlemips" : "elf32-littlemips"));
109 /* The name of the readonly data section. */
110 #define RDATA_SECTION_NAME (OUTPUT_FLAVOR == bfd_target_aout_flavour \
112 : OUTPUT_FLAVOR == bfd_target_ecoff_flavour \
114 : OUTPUT_FLAVOR == bfd_target_elf_flavour \
118 /* These variables are filled in with the masks of registers used.
119 The object format code reads them and puts them in the appropriate
121 unsigned long mips_gprmask
;
122 unsigned long mips_cprmask
[4];
124 /* MIPS ISA (Instruction Set Architecture) level (may be changed
125 temporarily using .set mipsN). */
126 static int mips_isa
= -1;
128 /* MIPS ISA we are using for this output file. */
129 static int file_mips_isa
;
131 /* The CPU type as a number: 2000, 3000, 4000, 4400, etc. */
132 static int mips_cpu
= -1;
134 /* Whether the 4650 instructions (mad/madu) are permitted. */
135 static int mips_4650
= -1;
137 /* Whether the 4010 instructions are permitted. */
138 static int mips_4010
= -1;
140 /* Whether the 4100 MADD16 and DMADD16 are permitted. */
141 static int mips_4100
= -1;
143 /* Whether the processor uses hardware interlocks, and thus does not
144 require nops to be inserted. */
145 static int interlocks
= -1;
147 /* MIPS PIC level. */
151 /* Do not generate PIC code. */
154 /* Generate PIC code as in Irix 4. This is not implemented, and I'm
155 not sure what it is supposed to do. */
158 /* Generate PIC code as in the SVR4 MIPS ABI. */
161 /* Generate PIC code without using a global offset table: the data
162 segment has a maximum size of 64K, all data references are off
163 the $gp register, and all text references are PC relative. This
164 is used on some embedded systems. */
168 static enum mips_pic_level mips_pic
;
170 /* 1 if we should generate 32 bit offsets from the GP register in
171 SVR4_PIC mode. Currently has no meaning in other modes. */
172 static int mips_big_got
;
174 /* 1 if trap instructions should used for overflow rather than break
176 static int mips_trap
;
178 static int mips_warn_about_macros
;
179 static int mips_noreorder
;
180 static int mips_any_noreorder
;
181 static int mips_nomove
;
182 static int mips_noat
;
183 static int mips_nobopt
;
185 /* The size of the small data section. */
186 static int g_switch_value
= 8;
187 /* Whether the -G option was used. */
188 static int g_switch_seen
= 0;
193 /* If we can determine in advance that GP optimization won't be
194 possible, we can skip the relaxation stuff that tries to produce
195 GP-relative references. This makes delay slot optimization work
198 This function can only provide a guess, but it seems to work for
199 gcc output. If it guesses wrong, the only loss should be in
200 efficiency; it shouldn't introduce any bugs.
202 I don't know if a fix is needed for the SVR4_PIC mode. I've only
203 fixed it for the non-PIC mode. KR 95/04/07 */
204 static int nopic_need_relax
PARAMS ((symbolS
*));
206 /* handle of the OPCODE hash table */
207 static struct hash_control
*op_hash
= NULL
;
209 /* This array holds the chars that always start a comment. If the
210 pre-processor is disabled, these aren't very useful */
211 const char comment_chars
[] = "#";
213 /* This array holds the chars that only start a comment at the beginning of
214 a line. If the line seems to have the form '# 123 filename'
215 .line and .file directives will appear in the pre-processed output */
216 /* Note that input_file.c hand checks for '#' at the beginning of the
217 first line of the input file. This is because the compiler outputs
218 #NO_APP at the beginning of its output. */
219 /* Also note that C style comments are always supported. */
220 const char line_comment_chars
[] = "#";
222 /* This array holds machine specific line separator characters. */
223 const char line_separator_chars
[] = "";
225 /* Chars that can be used to separate mant from exp in floating point nums */
226 const char EXP_CHARS
[] = "eE";
228 /* Chars that mean this number is a floating point constant */
231 const char FLT_CHARS
[] = "rRsSfFdDxXpP";
233 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
234 changed in read.c . Ideally it shouldn't have to know about it at all,
235 but nothing is ideal around here.
238 static char *insn_error
;
240 static int byte_order
;
242 static int auto_align
= 1;
244 /* Symbol labelling the current insn. */
245 static symbolS
*insn_label
;
247 /* When outputting SVR4 PIC code, the assembler needs to know the
248 offset in the stack frame from which to restore the $gp register.
249 This is set by the .cprestore pseudo-op, and saved in this
251 static offsetT mips_cprestore_offset
= -1;
253 /* This is the register which holds the stack frame, as set by the
254 .frame pseudo-op. This is needed to implement .cprestore. */
255 static int mips_frame_reg
= SP
;
257 /* To output NOP instructions correctly, we need to keep information
258 about the previous two instructions. */
260 /* Whether we are optimizing. The default value of 2 means to remove
261 unneeded NOPs and swap branch instructions when possible. A value
262 of 1 means to not swap branches. A value of 0 means to always
264 static int mips_optimize
= 2;
266 /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is
267 equivalent to seeing no -g option at all. */
268 static int mips_debug
= 0;
270 /* The previous instruction. */
271 static struct mips_cl_insn prev_insn
;
273 /* The instruction before prev_insn. */
274 static struct mips_cl_insn prev_prev_insn
;
276 /* If we don't want information for prev_insn or prev_prev_insn, we
277 point the insn_mo field at this dummy integer. */
278 static const struct mips_opcode dummy_opcode
= { 0 };
280 /* Non-zero if prev_insn is valid. */
281 static int prev_insn_valid
;
283 /* The frag for the previous instruction. */
284 static struct frag
*prev_insn_frag
;
286 /* The offset into prev_insn_frag for the previous instruction. */
287 static long prev_insn_where
;
289 /* The reloc for the previous instruction, if any. */
290 static fixS
*prev_insn_fixp
;
292 /* Non-zero if the previous instruction was in a delay slot. */
293 static int prev_insn_is_delay_slot
;
295 /* Non-zero if the previous instruction was in a .set noreorder. */
296 static int prev_insn_unreordered
;
298 /* Non-zero if the previous previous instruction was in a .set
300 static int prev_prev_insn_unreordered
;
302 /* For ECOFF and ELF, relocations against symbols are done in two
303 parts, with a HI relocation and a LO relocation. Each relocation
304 has only 16 bits of space to store an addend. This means that in
305 order for the linker to handle carries correctly, it must be able
306 to locate both the HI and the LO relocation. This means that the
307 relocations must appear in order in the relocation table.
309 In order to implement this, we keep track of each unmatched HI
310 relocation. We then sort them so that they immediately precede the
311 corresponding LO relocation. */
316 struct mips_hi_fixup
*next
;
319 /* The section this fixup is in. */
323 /* The list of unmatched HI relocs. */
325 static struct mips_hi_fixup
*mips_hi_fixup_list
;
327 /* Since the MIPS does not have multiple forms of PC relative
328 instructions, we do not have to do relaxing as is done on other
329 platforms. However, we do have to handle GP relative addressing
330 correctly, which turns out to be a similar problem.
332 Every macro that refers to a symbol can occur in (at least) two
333 forms, one with GP relative addressing and one without. For
334 example, loading a global variable into a register generally uses
335 a macro instruction like this:
337 If i can be addressed off the GP register (this is true if it is in
338 the .sbss or .sdata section, or if it is known to be smaller than
339 the -G argument) this will generate the following instruction:
341 This instruction will use a GPREL reloc. If i can not be addressed
342 off the GP register, the following instruction sequence will be used:
345 In this case the first instruction will have a HI16 reloc, and the
346 second reloc will have a LO16 reloc. Both relocs will be against
349 The issue here is that we may not know whether i is GP addressable
350 until after we see the instruction that uses it. Therefore, we
351 want to be able to choose the final instruction sequence only at
352 the end of the assembly. This is similar to the way other
353 platforms choose the size of a PC relative instruction only at the
356 When generating position independent code we do not use GP
357 addressing in quite the same way, but the issue still arises as
358 external symbols and local symbols must be handled differently.
360 We handle these issues by actually generating both possible
361 instruction sequences. The longer one is put in a frag_var with
362 type rs_machine_dependent. We encode what to do with the frag in
363 the subtype field. We encode (1) the number of existing bytes to
364 replace, (2) the number of new bytes to use, (3) the offset from
365 the start of the existing bytes to the first reloc we must generate
366 (that is, the offset is applied from the start of the existing
367 bytes after they are replaced by the new bytes, if any), (4) the
368 offset from the start of the existing bytes to the second reloc,
369 (5) whether a third reloc is needed (the third reloc is always four
370 bytes after the second reloc), and (6) whether to warn if this
371 variant is used (this is sometimes needed if .set nomacro or .set
372 noat is in effect). All these numbers are reasonably small.
374 Generating two instruction sequences must be handled carefully to
375 ensure that delay slots are handled correctly. Fortunately, there
376 are a limited number of cases. When the second instruction
377 sequence is generated, append_insn is directed to maintain the
378 existing delay slot information, so it continues to apply to any
379 code after the second instruction sequence. This means that the
380 second instruction sequence must not impose any requirements not
381 required by the first instruction sequence.
383 These variant frags are then handled in functions called by the
384 machine independent code. md_estimate_size_before_relax returns
385 the final size of the frag. md_convert_frag sets up the final form
386 of the frag. tc_gen_reloc adjust the first reloc and adds a second
388 #define RELAX_ENCODE(old, new, reloc1, reloc2, reloc3, warn) \
392 | (((reloc1) + 64) << 9) \
393 | (((reloc2) + 64) << 2) \
394 | ((reloc3) ? (1 << 1) : 0) \
396 #define RELAX_OLD(i) (((i) >> 24) & 0xff)
397 #define RELAX_NEW(i) (((i) >> 16) & 0xff)
398 #define RELAX_RELOC1(i) ((bfd_vma)(((i) >> 9) & 0x7f) - 64)
399 #define RELAX_RELOC2(i) ((bfd_vma)(((i) >> 2) & 0x7f) - 64)
400 #define RELAX_RELOC3(i) (((i) >> 1) & 1)
401 #define RELAX_WARN(i) ((i) & 1)
403 /* Prototypes for static functions. */
406 #define internalError() \
407 as_fatal ("internal Error, line %d, %s", __LINE__, __FILE__)
409 #define internalError() as_fatal ("MIPS internal Error");
412 static int insn_uses_reg
PARAMS ((struct mips_cl_insn
*ip
,
413 unsigned int reg
, int fpr
));
414 static int reg_needs_delay
PARAMS ((int));
415 static void append_insn
PARAMS ((char *place
,
416 struct mips_cl_insn
* ip
,
418 bfd_reloc_code_real_type r
,
420 static void mips_no_prev_insn
PARAMS ((void));
421 static void mips_emit_delays
PARAMS ((void));
423 static void macro_build
PARAMS ((char *place
, int *counter
, expressionS
* ep
,
424 const char *name
, const char *fmt
,
427 static void macro_build ();
429 static void macro_build_lui
PARAMS ((char *place
, int *counter
,
430 expressionS
* ep
, int regnum
));
431 static void set_at
PARAMS ((int *counter
, int reg
, int unsignedp
));
432 static void check_absolute_expr
PARAMS ((struct mips_cl_insn
* ip
,
434 static void load_register
PARAMS ((int *, int, expressionS
*, int));
435 static void load_address
PARAMS ((int *counter
, int reg
, expressionS
*ep
));
436 static void macro
PARAMS ((struct mips_cl_insn
* ip
));
437 #ifdef LOSING_COMPILER
438 static void macro2
PARAMS ((struct mips_cl_insn
* ip
));
440 static void mips_ip
PARAMS ((char *str
, struct mips_cl_insn
* ip
));
441 static int my_getSmallExpression
PARAMS ((expressionS
* ep
, char *str
));
442 static void my_getExpression
PARAMS ((expressionS
* ep
, char *str
));
443 static symbolS
*get_symbol
PARAMS ((void));
444 static void mips_align
PARAMS ((int to
, int fill
, symbolS
*label
));
445 static void s_align
PARAMS ((int));
446 static void s_change_sec
PARAMS ((int));
447 static void s_cons
PARAMS ((int));
448 static void s_float_cons
PARAMS ((int));
449 static void s_mips_globl
PARAMS ((int));
450 static void s_option
PARAMS ((int));
451 static void s_mipsset
PARAMS ((int));
452 static void s_abicalls
PARAMS ((int));
453 static void s_cpload
PARAMS ((int));
454 static void s_cprestore
PARAMS ((int));
455 static void s_gpword
PARAMS ((int));
456 static void s_cpadd
PARAMS ((int));
457 static void md_obj_begin
PARAMS ((void));
458 static void md_obj_end
PARAMS ((void));
459 static long get_number
PARAMS ((void));
460 static void s_ent
PARAMS ((int));
461 static void s_mipsend
PARAMS ((int));
462 static void s_file
PARAMS ((int));
466 The following pseudo-ops from the Kane and Heinrich MIPS book
467 should be defined here, but are currently unsupported: .alias,
468 .galive, .gjaldef, .gjrlive, .livereg, .noalias.
470 The following pseudo-ops from the Kane and Heinrich MIPS book are
471 specific to the type of debugging information being generated, and
472 should be defined by the object format: .aent, .begin, .bend,
473 .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp,
476 The following pseudo-ops from the Kane and Heinrich MIPS book are
477 not MIPS CPU specific, but are also not specific to the object file
478 format. This file is probably the best place to define them, but
479 they are not currently supported: .asm0, .endr, .lab, .repeat,
480 .struct, .weakext. */
482 static const pseudo_typeS mips_pseudo_table
[] =
484 /* MIPS specific pseudo-ops. */
485 {"option", s_option
, 0},
486 {"set", s_mipsset
, 0},
487 {"rdata", s_change_sec
, 'r'},
488 {"sdata", s_change_sec
, 's'},
489 {"livereg", s_ignore
, 0},
490 {"abicalls", s_abicalls
, 0},
491 {"cpload", s_cpload
, 0},
492 {"cprestore", s_cprestore
, 0},
493 {"gpword", s_gpword
, 0},
494 {"cpadd", s_cpadd
, 0},
496 /* Relatively generic pseudo-ops that happen to be used on MIPS
498 {"asciiz", stringer
, 1},
499 {"bss", s_change_sec
, 'b'},
502 {"dword", s_cons
, 3},
504 /* These pseudo-ops are defined in read.c, but must be overridden
505 here for one reason or another. */
506 {"align", s_align
, 0},
508 {"data", s_change_sec
, 'd'},
509 {"double", s_float_cons
, 'd'},
510 {"float", s_float_cons
, 'f'},
511 {"globl", s_mips_globl
, 0},
512 {"global", s_mips_globl
, 0},
513 {"hword", s_cons
, 1},
518 {"short", s_cons
, 1},
519 {"single", s_float_cons
, 'f'},
520 {"text", s_change_sec
, 't'},
525 static const pseudo_typeS mips_nonecoff_pseudo_table
[] = {
526 /* These pseudo-ops should be defined by the object file format.
527 However, a.out doesn't support them, so we have versions here. */
529 {"bgnb", s_ignore
, 0},
530 {"end", s_mipsend
, 0},
531 {"endb", s_ignore
, 0},
534 {"fmask", s_ignore
, 'F'},
535 {"frame", s_ignore
, 0},
536 {"loc", s_ignore
, 0},
537 {"mask", s_ignore
, 'R'},
538 {"verstamp", s_ignore
, 0},
542 extern void pop_insert
PARAMS ((const pseudo_typeS
*));
547 pop_insert (mips_pseudo_table
);
548 if (! ECOFF_DEBUGGING
)
549 pop_insert (mips_nonecoff_pseudo_table
);
552 static char *expr_end
;
554 /* Expressions which appear in instructions. These are set by
557 static expressionS imm_expr
;
558 static expressionS offset_expr
;
560 /* Relocs associated with imm_expr and offset_expr. */
562 static bfd_reloc_code_real_type imm_reloc
;
563 static bfd_reloc_code_real_type offset_reloc
;
565 /* This is set by mips_ip if imm_reloc is an unmatched HI16_S reloc. */
567 static boolean imm_unmatched_hi
;
570 * This function is called once, at assembler startup time. It should
571 * set up all the tables, etc. that the MD part of the assembler will need.
577 register const char *retval
= NULL
;
578 register unsigned int i
= 0;
586 if (strcmp (cpu
+ (sizeof TARGET_CPU
) - 3, "el") == 0)
588 a
= xmalloc (sizeof TARGET_CPU
);
589 strcpy (a
, TARGET_CPU
);
590 a
[(sizeof TARGET_CPU
) - 3] = '\0';
594 if (strcmp (cpu
, "mips") == 0)
600 else if (strcmp (cpu
, "r6000") == 0
601 || strcmp (cpu
, "mips2") == 0)
607 else if (strcmp (cpu
, "mips64") == 0
608 || strcmp (cpu
, "r4000") == 0
609 || strcmp (cpu
, "mips3") == 0)
615 else if (strcmp (cpu
, "r4400") == 0)
621 else if (strcmp (cpu
, "mips64orion") == 0
622 || strcmp (cpu
, "r4600") == 0)
628 else if (strcmp (cpu
, "r4650") == 0)
636 else if (strcmp (cpu
, "mips64vr4300") == 0)
642 else if (strcmp (cpu
, "mips64vr4100") == 0)
650 else if (strcmp (cpu
, "r4010") == 0)
658 else if (strcmp (cpu
, "r8000") == 0
659 || strcmp (cpu
, "mips4") == 0)
665 else if (strcmp (cpu
, "r10000") == 0)
691 if (mips_4650
|| mips_4010
|| mips_4100
)
696 if (mips_isa
< 2 && mips_trap
)
697 as_bad ("trap exception not supported at ISA 1");
702 ok
= bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, 3000);
705 ok
= bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, 6000);
708 ok
= bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, 4000);
711 ok
= bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, 8000);
715 as_warn ("Could not set architecture and machine");
717 file_mips_isa
= mips_isa
;
719 op_hash
= hash_new ();
721 for (i
= 0; i
< NUMOPCODES
;)
723 const char *name
= mips_opcodes
[i
].name
;
725 retval
= hash_insert (op_hash
, name
, (PTR
) &mips_opcodes
[i
]);
728 fprintf (stderr
, "internal error: can't hash `%s': %s\n",
729 mips_opcodes
[i
].name
, retval
);
730 as_fatal ("Broken assembler. No assembly attempted.");
734 if (mips_opcodes
[i
].pinfo
!= INSN_MACRO
735 && ((mips_opcodes
[i
].match
& mips_opcodes
[i
].mask
)
736 != mips_opcodes
[i
].match
))
738 fprintf (stderr
, "internal error: bad opcode: `%s' \"%s\"\n",
739 mips_opcodes
[i
].name
, mips_opcodes
[i
].args
);
740 as_fatal ("Broken assembler. No assembly attempted.");
744 while ((i
< NUMOPCODES
) && !strcmp (mips_opcodes
[i
].name
, name
));
747 mips_no_prev_insn ();
755 /* set the default alignment for the text section (2**2) */
756 record_alignment (text_section
, 2);
758 if (USE_GLOBAL_POINTER_OPT
)
759 bfd_set_gp_size (stdoutput
, g_switch_value
);
761 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
763 /* Sections must be aligned to 16 byte boundaries. */
764 (void) bfd_set_section_alignment (stdoutput
, text_section
, 4);
765 (void) bfd_set_section_alignment (stdoutput
, data_section
, 4);
766 (void) bfd_set_section_alignment (stdoutput
, bss_section
, 4);
768 /* Create a .reginfo section for register masks and a .mdebug
769 section for debugging information. */
777 sec
= subseg_new (".reginfo", (subsegT
) 0);
779 /* The ABI says this section should be loaded so that the
780 running program can access it. */
781 (void) bfd_set_section_flags (stdoutput
, sec
,
782 (SEC_ALLOC
| SEC_LOAD
783 | SEC_READONLY
| SEC_DATA
));
784 (void) bfd_set_section_alignment (stdoutput
, sec
, 2);
787 mips_regmask_frag
= frag_more (sizeof (Elf32_External_RegInfo
));
792 sec
= subseg_new (".mdebug", (subsegT
) 0);
793 (void) bfd_set_section_flags (stdoutput
, sec
,
794 SEC_HAS_CONTENTS
| SEC_READONLY
);
795 (void) bfd_set_section_alignment (stdoutput
, sec
, 2);
798 subseg_set (seg
, subseg
);
802 if (! ECOFF_DEBUGGING
)
809 if (! ECOFF_DEBUGGING
)
817 struct mips_cl_insn insn
;
819 imm_expr
.X_op
= O_absent
;
820 imm_reloc
= BFD_RELOC_UNUSED
;
821 imm_unmatched_hi
= false;
822 offset_expr
.X_op
= O_absent
;
823 offset_reloc
= BFD_RELOC_UNUSED
;
825 mips_ip (str
, &insn
);
828 as_bad ("%s `%s'", insn_error
, str
);
831 if (insn
.insn_mo
->pinfo
== INSN_MACRO
)
837 if (imm_expr
.X_op
!= O_absent
)
838 append_insn ((char *) NULL
, &insn
, &imm_expr
, imm_reloc
,
840 else if (offset_expr
.X_op
!= O_absent
)
841 append_insn ((char *) NULL
, &insn
, &offset_expr
, offset_reloc
, false);
843 append_insn ((char *) NULL
, &insn
, NULL
, BFD_RELOC_UNUSED
, false);
847 /* See whether instruction IP reads register REG. If FPR is non-zero,
848 REG is a floating point register. */
851 insn_uses_reg (ip
, reg
, fpr
)
852 struct mips_cl_insn
*ip
;
856 /* Don't report on general register 0, since it never changes. */
857 if (! fpr
&& reg
== 0)
862 /* If we are called with either $f0 or $f1, we must check $f0.
863 This is not optimal, because it will introduce an unnecessary
864 NOP between "lwc1 $f0" and "swc1 $f1". To fix this we would
865 need to distinguish reading both $f0 and $f1 or just one of
866 them. Note that we don't have to check the other way,
867 because there is no instruction that sets both $f0 and $f1
868 and requires a delay. */
869 if ((ip
->insn_mo
->pinfo
& INSN_READ_FPR_S
)
870 && (((ip
->insn_opcode
>> OP_SH_FS
) & OP_MASK_FS
)
871 == (reg
&~ (unsigned) 1)))
873 if ((ip
->insn_mo
->pinfo
& INSN_READ_FPR_T
)
874 && (((ip
->insn_opcode
>> OP_SH_FT
) & OP_MASK_FT
)
875 == (reg
&~ (unsigned) 1)))
880 if ((ip
->insn_mo
->pinfo
& INSN_READ_GPR_S
)
881 && ((ip
->insn_opcode
>> OP_SH_RS
) & OP_MASK_RS
) == reg
)
883 if ((ip
->insn_mo
->pinfo
& INSN_READ_GPR_T
)
884 && ((ip
->insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
) == reg
)
891 /* This function returns true if modifying a register requires a
895 reg_needs_delay (reg
)
898 unsigned long prev_pinfo
;
900 prev_pinfo
= prev_insn
.insn_mo
->pinfo
;
903 && ((prev_pinfo
& INSN_LOAD_COPROC_DELAY
)
905 && (prev_pinfo
& INSN_LOAD_MEMORY_DELAY
))))
907 /* A load from a coprocessor or from memory. All load
908 delays delay the use of general register rt for one
909 instruction on the r3000. The r6000 and r4000 use
911 know (prev_pinfo
& INSN_WRITE_GPR_T
);
912 if (reg
== ((prev_insn
.insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
))
919 /* Output an instruction. PLACE is where to put the instruction; if
920 it is NULL, this uses frag_more to get room. IP is the instruction
921 information. ADDRESS_EXPR is an operand of the instruction to be
922 used with RELOC_TYPE. */
925 append_insn (place
, ip
, address_expr
, reloc_type
, unmatched_hi
)
927 struct mips_cl_insn
*ip
;
928 expressionS
*address_expr
;
929 bfd_reloc_code_real_type reloc_type
;
930 boolean unmatched_hi
;
932 register unsigned long prev_pinfo
, pinfo
;
937 prev_pinfo
= prev_insn
.insn_mo
->pinfo
;
938 pinfo
= ip
->insn_mo
->pinfo
;
940 if (place
== NULL
&& ! mips_noreorder
)
942 /* If the previous insn required any delay slots, see if we need
943 to insert a NOP or two. There are eight kinds of possible
944 hazards, of which an instruction can have at most one type.
945 (1) a load from memory delay
946 (2) a load from a coprocessor delay
947 (3) an unconditional branch delay
948 (4) a conditional branch delay
949 (5) a move to coprocessor register delay
950 (6) a load coprocessor register from memory delay
951 (7) a coprocessor condition code delay
952 (8) a HI/LO special register delay
954 There are a lot of optimizations we could do that we don't.
955 In particular, we do not, in general, reorder instructions.
956 If you use gcc with optimization, it will reorder
957 instructions and generally do much more optimization then we
958 do here; repeating all that work in the assembler would only
959 benefit hand written assembly code, and does not seem worth
962 /* This is how a NOP is emitted. */
963 #define emit_nop() md_number_to_chars (frag_more (4), 0, 4)
965 /* The previous insn might require a delay slot, depending upon
966 the contents of the current insn. */
968 && ((prev_pinfo
& INSN_LOAD_COPROC_DELAY
)
970 && (prev_pinfo
& INSN_LOAD_MEMORY_DELAY
))))
972 /* A load from a coprocessor or from memory. All load
973 delays delay the use of general register rt for one
974 instruction on the r3000. The r6000 and r4000 use
976 know (prev_pinfo
& INSN_WRITE_GPR_T
);
977 if (mips_optimize
== 0
978 || insn_uses_reg (ip
,
979 ((prev_insn
.insn_opcode
>> OP_SH_RT
)
984 else if (mips_isa
< 4
985 && ((prev_pinfo
& INSN_COPROC_MOVE_DELAY
)
987 && (prev_pinfo
& INSN_COPROC_MEMORY_DELAY
))))
989 /* A generic coprocessor delay. The previous instruction
990 modified a coprocessor general or control register. If
991 it modified a control register, we need to avoid any
992 coprocessor instruction (this is probably not always
993 required, but it sometimes is). If it modified a general
994 register, we avoid using that register.
996 On the r6000 and r4000 loading a coprocessor register
997 from memory is interlocked, and does not require a delay.
999 This case is not handled very well. There is no special
1000 knowledge of CP0 handling, and the coprocessors other
1001 than the floating point unit are not distinguished at
1003 if (prev_pinfo
& INSN_WRITE_FPR_T
)
1005 if (mips_optimize
== 0
1006 || insn_uses_reg (ip
,
1007 ((prev_insn
.insn_opcode
>> OP_SH_FT
)
1012 else if (prev_pinfo
& INSN_WRITE_FPR_S
)
1014 if (mips_optimize
== 0
1015 || insn_uses_reg (ip
,
1016 ((prev_insn
.insn_opcode
>> OP_SH_FS
)
1023 /* We don't know exactly what the previous instruction
1024 does. If the current instruction uses a coprocessor
1025 register, we must insert a NOP. If previous
1026 instruction may set the condition codes, and the
1027 current instruction uses them, we must insert two
1029 if (mips_optimize
== 0
1030 || ((prev_pinfo
& INSN_WRITE_COND_CODE
)
1031 && (pinfo
& INSN_READ_COND_CODE
)))
1033 else if (pinfo
& INSN_COP
)
1037 else if (mips_isa
< 4
1038 && (prev_pinfo
& INSN_WRITE_COND_CODE
))
1040 /* The previous instruction sets the coprocessor condition
1041 codes, but does not require a general coprocessor delay
1042 (this means it is a floating point comparison
1043 instruction). If this instruction uses the condition
1044 codes, we need to insert a single NOP. */
1045 if (mips_optimize
== 0
1046 || (pinfo
& INSN_READ_COND_CODE
))
1049 else if (prev_pinfo
& INSN_READ_LO
)
1051 /* The previous instruction reads the LO register; if the
1052 current instruction writes to the LO register, we must
1053 insert two NOPS. The R4650 and VR4100 have interlocks. */
1055 && (mips_optimize
== 0
1056 || (pinfo
& INSN_WRITE_LO
)))
1059 else if (prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
1061 /* The previous instruction reads the HI register; if the
1062 current instruction writes to the HI register, we must
1063 insert a NOP. The R4650 and VR4100 have interlocks. */
1065 && (mips_optimize
== 0
1066 || (pinfo
& INSN_WRITE_HI
)))
1070 /* There are two cases which require two intervening
1071 instructions: 1) setting the condition codes using a move to
1072 coprocessor instruction which requires a general coprocessor
1073 delay and then reading the condition codes 2) reading the HI
1074 or LO register and then writing to it (except on the R4650,
1075 and VR4100 which have interlocks). If we are not already
1076 emitting a NOP instruction, we must check for these cases
1077 compared to the instruction previous to the previous
1081 && (prev_prev_insn
.insn_mo
->pinfo
& INSN_COPROC_MOVE_DELAY
)
1082 && (prev_prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
)
1083 && (pinfo
& INSN_READ_COND_CODE
))
1084 || ((prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
)
1085 && (pinfo
& INSN_WRITE_LO
)
1087 || ((prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
1088 && (pinfo
& INSN_WRITE_HI
)
1092 /* If we are being given a nop instruction, don't bother with
1093 one of the nops we would otherwise output. This will only
1094 happen when a nop instruction is used with mips_optimize set
1096 if (nops
> 0 && ip
->insn_opcode
== 0)
1099 /* Now emit the right number of NOP instructions. */
1104 for (i
= 0; i
< nops
; i
++)
1108 listing_prev_line ();
1109 /* We may be at the start of a variant frag. In case we
1110 are, make sure there is enough space for the frag
1111 after the frags created by listing_prev_line. The
1112 argument to frag_grow here must be at least as large
1113 as the argument to all other calls to frag_grow in
1114 this file. We don't have to worry about being in the
1115 middle of a variant frag, because the variants insert
1116 all needed nop instructions themselves. */
1119 if (insn_label
!= NULL
)
1121 assert (S_GET_SEGMENT (insn_label
) == now_seg
);
1122 insn_label
->sy_frag
= frag_now
;
1123 S_SET_VALUE (insn_label
, (valueT
) frag_now_fix ());
1133 if (address_expr
!= NULL
)
1135 if (address_expr
->X_op
== O_constant
)
1140 ip
->insn_opcode
|= address_expr
->X_add_number
;
1143 case BFD_RELOC_LO16
:
1144 ip
->insn_opcode
|= address_expr
->X_add_number
& 0xffff;
1147 case BFD_RELOC_MIPS_JMP
:
1148 case BFD_RELOC_16_PCREL_S2
:
1157 assert (reloc_type
!= BFD_RELOC_UNUSED
);
1159 /* Don't generate a reloc if we are writing into a variant
1163 fixp
= fix_new_exp (frag_now
, f
- frag_now
->fr_literal
, 4,
1165 reloc_type
== BFD_RELOC_16_PCREL_S2
,
1169 struct mips_hi_fixup
*hi_fixup
;
1171 assert (reloc_type
== BFD_RELOC_HI16_S
);
1172 hi_fixup
= ((struct mips_hi_fixup
*)
1173 xmalloc (sizeof (struct mips_hi_fixup
)));
1174 hi_fixup
->fixp
= fixp
;
1175 hi_fixup
->seg
= now_seg
;
1176 hi_fixup
->next
= mips_hi_fixup_list
;
1177 mips_hi_fixup_list
= hi_fixup
;
1183 md_number_to_chars (f
, ip
->insn_opcode
, 4);
1185 /* Update the register mask information. */
1186 if (pinfo
& INSN_WRITE_GPR_D
)
1187 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
);
1188 if ((pinfo
& (INSN_WRITE_GPR_T
| INSN_READ_GPR_T
)) != 0)
1189 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
);
1190 if (pinfo
& INSN_READ_GPR_S
)
1191 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> OP_SH_RS
) & OP_MASK_RS
);
1192 if (pinfo
& INSN_WRITE_GPR_31
)
1193 mips_gprmask
|= 1 << 31;
1194 if (pinfo
& INSN_WRITE_FPR_D
)
1195 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FD
) & OP_MASK_FD
);
1196 if ((pinfo
& (INSN_WRITE_FPR_S
| INSN_READ_FPR_S
)) != 0)
1197 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FS
) & OP_MASK_FS
);
1198 if ((pinfo
& (INSN_WRITE_FPR_T
| INSN_READ_FPR_T
)) != 0)
1199 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FT
) & OP_MASK_FT
);
1200 if ((pinfo
& INSN_READ_FPR_R
) != 0)
1201 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FR
) & OP_MASK_FR
);
1202 if (pinfo
& INSN_COP
)
1204 /* We don't keep enough information to sort these cases out. */
1206 /* Never set the bit for $0, which is always zero. */
1207 mips_gprmask
&=~ 1 << 0;
1209 if (place
== NULL
&& ! mips_noreorder
)
1211 /* Filling the branch delay slot is more complex. We try to
1212 switch the branch with the previous instruction, which we can
1213 do if the previous instruction does not set up a condition
1214 that the branch tests and if the branch is not itself the
1215 target of any branch. */
1216 if ((pinfo
& INSN_UNCOND_BRANCH_DELAY
)
1217 || (pinfo
& INSN_COND_BRANCH_DELAY
))
1219 if (mips_optimize
< 2
1220 /* If we have seen .set volatile or .set nomove, don't
1223 /* If we had to emit any NOP instructions, then we
1224 already know we can not swap. */
1226 /* If we don't even know the previous insn, we can not
1228 || ! prev_insn_valid
1229 /* If the previous insn is already in a branch delay
1230 slot, then we can not swap. */
1231 || prev_insn_is_delay_slot
1232 /* If the previous previous insn was in a .set
1233 noreorder, we can't swap. Actually, the MIPS
1234 assembler will swap in this situation. However, gcc
1235 configured -with-gnu-as will generate code like
1241 in which we can not swap the bne and INSN. If gcc is
1242 not configured -with-gnu-as, it does not output the
1243 .set pseudo-ops. We don't have to check
1244 prev_insn_unreordered, because prev_insn_valid will
1245 be 0 in that case. We don't want to use
1246 prev_prev_insn_valid, because we do want to be able
1247 to swap at the start of a function. */
1248 || prev_prev_insn_unreordered
1249 /* If the branch is itself the target of a branch, we
1250 can not swap. We cheat on this; all we check for is
1251 whether there is a label on this instruction. If
1252 there are any branches to anything other than a
1253 label, users must use .set noreorder. */
1254 || insn_label
!= NULL
1255 /* If the previous instruction is in a variant frag, we
1256 can not do the swap. */
1257 || prev_insn_frag
->fr_type
== rs_machine_dependent
1258 /* If the branch reads the condition codes, we don't
1259 even try to swap, because in the sequence
1264 we can not swap, and I don't feel like handling that
1267 && (pinfo
& INSN_READ_COND_CODE
))
1268 /* We can not swap with an instruction that requires a
1269 delay slot, becase the target of the branch might
1270 interfere with that instruction. */
1273 & (INSN_LOAD_COPROC_DELAY
1274 | INSN_COPROC_MOVE_DELAY
1275 | INSN_WRITE_COND_CODE
)))
1282 & (INSN_LOAD_MEMORY_DELAY
1283 | INSN_COPROC_MEMORY_DELAY
)))
1284 /* We can not swap with a branch instruction. */
1286 & (INSN_UNCOND_BRANCH_DELAY
1287 | INSN_COND_BRANCH_DELAY
1288 | INSN_COND_BRANCH_LIKELY
))
1289 /* We do not swap with a trap instruction, since it
1290 complicates trap handlers to have the trap
1291 instruction be in a delay slot. */
1292 || (prev_pinfo
& INSN_TRAP
)
1293 /* If the branch reads a register that the previous
1294 instruction sets, we can not swap. */
1295 || ((prev_pinfo
& INSN_WRITE_GPR_T
)
1296 && insn_uses_reg (ip
,
1297 ((prev_insn
.insn_opcode
>> OP_SH_RT
)
1300 || ((prev_pinfo
& INSN_WRITE_GPR_D
)
1301 && insn_uses_reg (ip
,
1302 ((prev_insn
.insn_opcode
>> OP_SH_RD
)
1305 /* If the branch writes a register that the previous
1306 instruction sets, we can not swap (we know that
1307 branches write only to RD or to $31). */
1308 || ((prev_pinfo
& INSN_WRITE_GPR_T
)
1309 && (((pinfo
& INSN_WRITE_GPR_D
)
1310 && (((prev_insn
.insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
)
1311 == ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)))
1312 || ((pinfo
& INSN_WRITE_GPR_31
)
1313 && (((prev_insn
.insn_opcode
>> OP_SH_RT
)
1316 || ((prev_pinfo
& INSN_WRITE_GPR_D
)
1317 && (((pinfo
& INSN_WRITE_GPR_D
)
1318 && (((prev_insn
.insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)
1319 == ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)))
1320 || ((pinfo
& INSN_WRITE_GPR_31
)
1321 && (((prev_insn
.insn_opcode
>> OP_SH_RD
)
1324 /* If the branch writes a register that the previous
1325 instruction reads, we can not swap (we know that
1326 branches only write to RD or to $31). */
1327 || ((pinfo
& INSN_WRITE_GPR_D
)
1328 && insn_uses_reg (&prev_insn
,
1329 ((ip
->insn_opcode
>> OP_SH_RD
)
1332 || ((pinfo
& INSN_WRITE_GPR_31
)
1333 && insn_uses_reg (&prev_insn
, 31, 0))
1334 /* If we are generating embedded PIC code, the branch
1335 might be expanded into a sequence which uses $at, so
1336 we can't swap with an instruction which reads it. */
1337 || (mips_pic
== EMBEDDED_PIC
1338 && insn_uses_reg (&prev_insn
, AT
, 0))
1339 /* If the previous previous instruction has a load
1340 delay, and sets a register that the branch reads, we
1343 && ((prev_prev_insn
.insn_mo
->pinfo
& INSN_LOAD_COPROC_DELAY
)
1345 && (prev_prev_insn
.insn_mo
->pinfo
1346 & INSN_LOAD_MEMORY_DELAY
)))
1347 && insn_uses_reg (ip
,
1348 ((prev_prev_insn
.insn_opcode
>> OP_SH_RT
)
1352 /* We could do even better for unconditional branches to
1353 portions of this object file; we could pick up the
1354 instruction at the destination, put it in the delay
1355 slot, and bump the destination address. */
1357 /* Update the previous insn information. */
1358 prev_prev_insn
= *ip
;
1359 prev_insn
.insn_mo
= &dummy_opcode
;
1366 /* It looks like we can actually do the swap. */
1367 prev_f
= prev_insn_frag
->fr_literal
+ prev_insn_where
;
1368 memcpy (temp
, prev_f
, 4);
1369 memcpy (prev_f
, f
, 4);
1370 memcpy (f
, temp
, 4);
1373 prev_insn_fixp
->fx_frag
= frag_now
;
1374 prev_insn_fixp
->fx_where
= f
- frag_now
->fr_literal
;
1378 fixp
->fx_frag
= prev_insn_frag
;
1379 fixp
->fx_where
= prev_insn_where
;
1381 /* Update the previous insn information; leave prev_insn
1383 prev_prev_insn
= *ip
;
1385 prev_insn_is_delay_slot
= 1;
1387 /* If that was an unconditional branch, forget the previous
1388 insn information. */
1389 if (pinfo
& INSN_UNCOND_BRANCH_DELAY
)
1391 prev_prev_insn
.insn_mo
= &dummy_opcode
;
1392 prev_insn
.insn_mo
= &dummy_opcode
;
1395 else if (pinfo
& INSN_COND_BRANCH_LIKELY
)
1397 /* We don't yet optimize a branch likely. What we should do
1398 is look at the target, copy the instruction found there
1399 into the delay slot, and increment the branch to jump to
1400 the next instruction. */
1402 /* Update the previous insn information. */
1403 prev_prev_insn
= *ip
;
1404 prev_insn
.insn_mo
= &dummy_opcode
;
1408 /* Update the previous insn information. */
1410 prev_prev_insn
.insn_mo
= &dummy_opcode
;
1412 prev_prev_insn
= prev_insn
;
1415 /* Any time we see a branch, we always fill the delay slot
1416 immediately; since this insn is not a branch, we know it
1417 is not in a delay slot. */
1418 prev_insn_is_delay_slot
= 0;
1421 prev_prev_insn_unreordered
= prev_insn_unreordered
;
1422 prev_insn_unreordered
= 0;
1423 prev_insn_frag
= frag_now
;
1424 prev_insn_where
= f
- frag_now
->fr_literal
;
1425 prev_insn_fixp
= fixp
;
1426 prev_insn_valid
= 1;
1429 /* We just output an insn, so the next one doesn't have a label. */
1433 /* This function forgets that there was any previous instruction or
1437 mips_no_prev_insn ()
1439 prev_insn
.insn_mo
= &dummy_opcode
;
1440 prev_prev_insn
.insn_mo
= &dummy_opcode
;
1441 prev_insn_valid
= 0;
1442 prev_insn_is_delay_slot
= 0;
1443 prev_insn_unreordered
= 0;
1444 prev_prev_insn_unreordered
= 0;
1448 /* This function must be called whenever we turn on noreorder or emit
1449 something other than instructions. It inserts any NOPS which might
1450 be needed by the previous instruction, and clears the information
1451 kept for the previous instructions. */
1456 if (! mips_noreorder
)
1462 && (prev_insn
.insn_mo
->pinfo
1463 & (INSN_LOAD_COPROC_DELAY
1464 | INSN_COPROC_MOVE_DELAY
1465 | INSN_WRITE_COND_CODE
)))
1467 && (prev_insn
.insn_mo
->pinfo
1471 && (prev_insn
.insn_mo
->pinfo
1472 & (INSN_LOAD_MEMORY_DELAY
1473 | INSN_COPROC_MEMORY_DELAY
))))
1477 && (prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
))
1479 && ((prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
1480 || (prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
))))
1483 else if ((mips_isa
< 4
1484 && (prev_prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
))
1486 && ((prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
1487 || (prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
))))
1492 if (insn_label
!= NULL
)
1494 assert (S_GET_SEGMENT (insn_label
) == now_seg
);
1495 insn_label
->sy_frag
= frag_now
;
1496 S_SET_VALUE (insn_label
, (valueT
) frag_now_fix ());
1501 mips_no_prev_insn ();
1504 /* Build an instruction created by a macro expansion. This is passed
1505 a pointer to the count of instructions created so far, an
1506 expression, the name of the instruction to build, an operand format
1507 string, and corresponding arguments. */
1511 macro_build (char *place
,
1519 macro_build (place
, counter
, ep
, name
, fmt
, va_alist
)
1528 struct mips_cl_insn insn
;
1529 bfd_reloc_code_real_type r
;
1533 va_start (args
, fmt
);
1539 * If the macro is about to expand into a second instruction,
1540 * print a warning if needed. We need to pass ip as a parameter
1541 * to generate a better warning message here...
1543 if (mips_warn_about_macros
&& place
== NULL
&& *counter
== 1)
1544 as_warn ("Macro instruction expanded into multiple instructions");
1547 *counter
+= 1; /* bump instruction counter */
1549 r
= BFD_RELOC_UNUSED
;
1550 insn
.insn_mo
= (struct mips_opcode
*) hash_find (op_hash
, name
);
1551 assert (insn
.insn_mo
);
1552 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
1554 while (strcmp (fmt
, insn
.insn_mo
->args
) != 0
1555 || insn
.insn_mo
->pinfo
== INSN_MACRO
1556 || ((insn
.insn_mo
->pinfo
& INSN_ISA
) == INSN_ISA2
1558 || ((insn
.insn_mo
->pinfo
& INSN_ISA
) == INSN_ISA3
1560 || ((insn
.insn_mo
->pinfo
& INSN_ISA
) == INSN_ISA4
1562 || ((insn
.insn_mo
->pinfo
& INSN_ISA
) == INSN_4650
1564 || ((insn
.insn_mo
->pinfo
& INSN_ISA
) == INSN_4010
1566 || ((insn
.insn_mo
->pinfo
& INSN_ISA
) == INSN_4100
1570 assert (insn
.insn_mo
->name
);
1571 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
1573 insn
.insn_opcode
= insn
.insn_mo
->match
;
1589 insn
.insn_opcode
|= va_arg (args
, int) << 16;
1595 insn
.insn_opcode
|= va_arg (args
, int) << 16;
1600 insn
.insn_opcode
|= va_arg (args
, int) << 11;
1605 insn
.insn_opcode
|= va_arg (args
, int) << 11;
1612 insn
.insn_opcode
|= va_arg (args
, int) << 6;
1616 insn
.insn_opcode
|= va_arg (args
, int) << 6;
1620 insn
.insn_opcode
|= va_arg (args
, int) << 6;
1627 insn
.insn_opcode
|= va_arg (args
, int) << 21;
1633 r
= (bfd_reloc_code_real_type
) va_arg (args
, int);
1634 assert (r
== BFD_RELOC_MIPS_GPREL
1635 || r
== BFD_RELOC_MIPS_LITERAL
1636 || r
== BFD_RELOC_LO16
1637 || r
== BFD_RELOC_MIPS_GOT16
1638 || r
== BFD_RELOC_MIPS_CALL16
1639 || r
== BFD_RELOC_MIPS_GOT_LO16
1640 || r
== BFD_RELOC_MIPS_CALL_LO16
1641 || (ep
->X_op
== O_subtract
1642 && now_seg
== text_section
1643 && r
== BFD_RELOC_PCREL_LO16
));
1647 r
= (bfd_reloc_code_real_type
) va_arg (args
, int);
1649 && (ep
->X_op
== O_constant
1650 || (ep
->X_op
== O_symbol
1651 && (r
== BFD_RELOC_HI16_S
1652 || r
== BFD_RELOC_HI16
1653 || r
== BFD_RELOC_MIPS_GOT_HI16
1654 || r
== BFD_RELOC_MIPS_CALL_HI16
))
1655 || (ep
->X_op
== O_subtract
1656 && now_seg
== text_section
1657 && r
== BFD_RELOC_PCREL_HI16_S
)));
1658 if (ep
->X_op
== O_constant
)
1660 insn
.insn_opcode
|= (ep
->X_add_number
>> 16) & 0xffff;
1662 r
= BFD_RELOC_UNUSED
;
1667 assert (ep
!= NULL
);
1669 * This allows macro() to pass an immediate expression for
1670 * creating short branches without creating a symbol.
1671 * Note that the expression still might come from the assembly
1672 * input, in which case the value is not checked for range nor
1673 * is a relocation entry generated (yuck).
1675 if (ep
->X_op
== O_constant
)
1677 insn
.insn_opcode
|= (ep
->X_add_number
>> 2) & 0xffff;
1681 r
= BFD_RELOC_16_PCREL_S2
;
1685 assert (ep
!= NULL
);
1686 r
= BFD_RELOC_MIPS_JMP
;
1695 assert (r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
1697 append_insn (place
, &insn
, ep
, r
, false);
1701 * Generate a "lui" instruction.
1704 macro_build_lui (place
, counter
, ep
, regnum
)
1710 expressionS high_expr
;
1711 struct mips_cl_insn insn
;
1712 bfd_reloc_code_real_type r
;
1713 CONST
char *name
= "lui";
1714 CONST
char *fmt
= "t,u";
1720 high_expr
.X_op
= O_constant
;
1721 high_expr
.X_add_number
= ep
->X_add_number
;
1724 if (high_expr
.X_op
== O_constant
)
1726 /* we can compute the instruction now without a relocation entry */
1727 if (high_expr
.X_add_number
& 0x8000)
1728 high_expr
.X_add_number
+= 0x10000;
1729 high_expr
.X_add_number
=
1730 ((unsigned long) high_expr
.X_add_number
>> 16) & 0xffff;
1731 r
= BFD_RELOC_UNUSED
;
1735 assert (ep
->X_op
== O_symbol
);
1736 /* _gp_disp is a special case, used from s_cpload. */
1737 assert (mips_pic
== NO_PIC
1738 || strcmp (S_GET_NAME (ep
->X_add_symbol
), "_gp_disp") == 0);
1739 r
= BFD_RELOC_HI16_S
;
1743 * If the macro is about to expand into a second instruction,
1744 * print a warning if needed. We need to pass ip as a parameter
1745 * to generate a better warning message here...
1747 if (mips_warn_about_macros
&& place
== NULL
&& *counter
== 1)
1748 as_warn ("Macro instruction expanded into multiple instructions");
1751 *counter
+= 1; /* bump instruction counter */
1753 insn
.insn_mo
= (struct mips_opcode
*) hash_find (op_hash
, name
);
1754 assert (insn
.insn_mo
);
1755 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
1756 assert (strcmp (fmt
, insn
.insn_mo
->args
) == 0);
1758 insn
.insn_opcode
= insn
.insn_mo
->match
| (regnum
<< OP_SH_RT
);
1759 if (r
== BFD_RELOC_UNUSED
)
1761 insn
.insn_opcode
|= high_expr
.X_add_number
;
1762 append_insn (place
, &insn
, NULL
, r
, false);
1765 append_insn (place
, &insn
, &high_expr
, r
, false);
1769 * Generates code to set the $at register to true (one)
1770 * if reg is less than the immediate expression.
1773 set_at (counter
, reg
, unsignedp
)
1778 if (imm_expr
.X_add_number
>= -0x8000 && imm_expr
.X_add_number
< 0x8000)
1779 macro_build ((char *) NULL
, counter
, &imm_expr
,
1780 unsignedp
? "sltiu" : "slti",
1781 "t,r,j", AT
, reg
, (int) BFD_RELOC_LO16
);
1784 load_register (counter
, AT
, &imm_expr
, 0);
1785 macro_build ((char *) NULL
, counter
, NULL
,
1786 unsignedp
? "sltu" : "slt",
1787 "d,v,t", AT
, reg
, AT
);
1791 /* Warn if an expression is not a constant. */
1794 check_absolute_expr (ip
, ex
)
1795 struct mips_cl_insn
*ip
;
1798 if (ex
->X_op
!= O_constant
)
1799 as_warn ("Instruction %s requires absolute expression", ip
->insn_mo
->name
);
1803 * This routine generates the least number of instructions neccessary to load
1804 * an absolute expression value into a register.
1807 load_register (counter
, reg
, ep
, dbl
)
1814 expressionS hi32
, lo32
, tmp
;
1816 if (ep
->X_op
!= O_big
)
1818 assert (ep
->X_op
== O_constant
);
1819 if (ep
->X_add_number
< 0x8000
1820 && (ep
->X_add_number
>= 0
1821 || (ep
->X_add_number
>= -0x8000
1824 || sizeof (ep
->X_add_number
) > 4))))
1826 /* We can handle 16 bit signed values with an addiu to
1827 $zero. No need to ever use daddiu here, since $zero and
1828 the result are always correct in 32 bit mode. */
1829 macro_build ((char *) NULL
, counter
, ep
, "addiu", "t,r,j", reg
, 0,
1830 (int) BFD_RELOC_LO16
);
1833 else if (ep
->X_add_number
>= 0 && ep
->X_add_number
< 0x10000)
1835 /* We can handle 16 bit unsigned values with an ori to
1837 macro_build ((char *) NULL
, counter
, ep
, "ori", "t,r,i", reg
, 0,
1838 (int) BFD_RELOC_LO16
);
1841 else if ((((ep
->X_add_number
&~ (offsetT
) 0x7fffffff) == 0
1842 || ((ep
->X_add_number
&~ (offsetT
) 0x7fffffff)
1843 == ~ (offsetT
) 0x7fffffff))
1846 || sizeof (ep
->X_add_number
) > 4
1847 || (ep
->X_add_number
& 0x80000000) == 0))
1849 && (ep
->X_add_number
&~ 0xffffffff) == 0))
1851 /* 32 bit values require an lui. */
1852 macro_build ((char *) NULL
, counter
, ep
, "lui", "t,u", reg
,
1853 (int) BFD_RELOC_HI16
);
1854 if ((ep
->X_add_number
& 0xffff) != 0)
1855 macro_build ((char *) NULL
, counter
, ep
, "ori", "t,r,i", reg
, reg
,
1856 (int) BFD_RELOC_LO16
);
1861 /* 32 bit value with high bit set being loaded into a 64 bit
1862 register. We can't use lui, because that would
1863 incorrectly set the 32 high bits. */
1864 generic_bignum
[3] = 0;
1865 generic_bignum
[2] = 0;
1866 generic_bignum
[1] = (ep
->X_add_number
>> 16) & 0xffff;
1867 generic_bignum
[0] = ep
->X_add_number
& 0xffff;
1869 tmp
.X_add_number
= 4;
1874 /* The value is larger than 32 bits. */
1878 as_bad ("Number larger than 32 bits");
1879 macro_build ((char *) NULL
, counter
, ep
, "addiu", "t,r,j", reg
, 0,
1880 (int) BFD_RELOC_LO16
);
1884 if (ep
->X_op
!= O_big
)
1888 hi32
.X_add_number
>>= shift
;
1889 hi32
.X_add_number
&= 0xffffffff;
1890 if ((hi32
.X_add_number
& 0x80000000) != 0)
1891 hi32
.X_add_number
|= ~ (offsetT
) 0xffffffff;
1893 lo32
.X_add_number
&= 0xffffffff;
1897 assert (ep
->X_add_number
> 2);
1898 if (ep
->X_add_number
== 3)
1899 generic_bignum
[3] = 0;
1900 else if (ep
->X_add_number
> 4)
1901 as_bad ("Number larger than 64 bits");
1902 lo32
.X_op
= O_constant
;
1903 lo32
.X_add_number
= generic_bignum
[0] + (generic_bignum
[1] << 16);
1904 hi32
.X_op
= O_constant
;
1905 hi32
.X_add_number
= generic_bignum
[2] + (generic_bignum
[3] << 16);
1908 if (hi32
.X_add_number
== 0)
1912 if (hi32
.X_add_number
== 0xffffffff)
1914 if ((lo32
.X_add_number
& 0xffff8000) == 0xffff8000)
1916 macro_build ((char *) NULL
, counter
, &lo32
, "addiu", "t,r,j", reg
, 0,
1917 (int) BFD_RELOC_LO16
);
1920 if (lo32
.X_add_number
& 0x80000000)
1922 macro_build ((char *) NULL
, counter
, &lo32
, "lui", "t,u", reg
,
1923 (int) BFD_RELOC_HI16
);
1924 macro_build ((char *) NULL
, counter
, &lo32
, "ori", "t,r,i", reg
, reg
,
1925 (int) BFD_RELOC_LO16
);
1929 load_register (counter
, reg
, &hi32
, 0);
1932 if ((lo32
.X_add_number
& 0xffff0000) == 0)
1936 macro_build ((char *) NULL
, counter
, NULL
, "dsll32", "d,w,<", reg
,
1945 if ((freg
== 0) && (lo32
.X_add_number
== 0xffffffff))
1947 macro_build ((char *) NULL
, counter
, &lo32
, "lui", "t,u", reg
,
1948 (int) BFD_RELOC_HI16
);
1949 macro_build ((char *) NULL
, counter
, NULL
, "dsrl32", "d,w,<", reg
,
1956 macro_build ((char *) NULL
, counter
, NULL
, "dsll", "d,w,<", reg
,
1961 mid16
.X_add_number
>>= 16;
1962 macro_build ((char *) NULL
, counter
, &mid16
, "ori", "t,r,i", reg
,
1963 freg
, (int) BFD_RELOC_LO16
);
1964 macro_build ((char *) NULL
, counter
, NULL
, "dsll", "d,w,<", reg
,
1968 if ((lo32
.X_add_number
& 0xffff) != 0)
1969 macro_build ((char *) NULL
, counter
, &lo32
, "ori", "t,r,i", reg
, freg
,
1970 (int) BFD_RELOC_LO16
);
1973 /* Load an address into a register. */
1976 load_address (counter
, reg
, ep
)
1983 if (ep
->X_op
!= O_constant
1984 && ep
->X_op
!= O_symbol
)
1986 as_bad ("expression too complex");
1987 ep
->X_op
= O_constant
;
1990 if (ep
->X_op
== O_constant
)
1992 load_register (counter
, reg
, ep
, 0);
1996 if (mips_pic
== NO_PIC
)
1998 /* If this is a reference to a GP relative symbol, we want
1999 addiu $reg,$gp,<sym> (BFD_RELOC_MIPS_GPREL)
2001 lui $reg,<sym> (BFD_RELOC_HI16_S)
2002 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
2003 If we have an addend, we always use the latter form. */
2004 if ((valueT
) ep
->X_add_number
>= MAX_GPREL_OFFSET
2005 || nopic_need_relax (ep
->X_add_symbol
))
2010 macro_build ((char *) NULL
, counter
, ep
,
2011 mips_isa
< 3 ? "addiu" : "daddiu",
2012 "t,r,j", reg
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
2013 p
= frag_var (rs_machine_dependent
, 8, 0,
2014 RELAX_ENCODE (4, 8, 0, 4, 0, mips_warn_about_macros
),
2015 ep
->X_add_symbol
, (long) 0, (char *) NULL
);
2017 macro_build_lui (p
, counter
, ep
, reg
);
2020 macro_build (p
, counter
, ep
,
2021 mips_isa
< 3 ? "addiu" : "daddiu",
2022 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
2024 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
2028 /* If this is a reference to an external symbol, we want
2029 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
2031 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
2033 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
2034 If there is a constant, it must be added in after. */
2035 ex
.X_add_number
= ep
->X_add_number
;
2036 ep
->X_add_number
= 0;
2038 macro_build ((char *) NULL
, counter
, ep
,
2039 mips_isa
< 3 ? "lw" : "ld",
2040 "t,o(b)", reg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
2041 macro_build ((char *) NULL
, counter
, (expressionS
*) NULL
, "nop", "");
2042 p
= frag_var (rs_machine_dependent
, 4, 0,
2043 RELAX_ENCODE (0, 4, -8, 0, 0, mips_warn_about_macros
),
2044 ep
->X_add_symbol
, (long) 0, (char *) NULL
);
2045 macro_build (p
, counter
, ep
,
2046 mips_isa
< 3 ? "addiu" : "daddiu",
2047 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
2048 if (ex
.X_add_number
!= 0)
2050 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
2051 as_bad ("PIC code offset overflow (max 16 signed bits)");
2052 ex
.X_op
= O_constant
;
2053 macro_build ((char *) NULL
, counter
, &ex
,
2054 mips_isa
< 3 ? "addiu" : "daddiu",
2055 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
2058 else if (mips_pic
== SVR4_PIC
)
2063 /* This is the large GOT case. If this is a reference to an
2064 external symbol, we want
2065 lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
2067 lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16)
2068 Otherwise, for a reference to a local symbol, we want
2069 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
2071 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
2072 If there is a constant, it must be added in after. */
2073 ex
.X_add_number
= ep
->X_add_number
;
2074 ep
->X_add_number
= 0;
2075 if (reg_needs_delay (GP
))
2080 macro_build ((char *) NULL
, counter
, ep
, "lui", "t,u", reg
,
2081 (int) BFD_RELOC_MIPS_GOT_HI16
);
2082 macro_build ((char *) NULL
, counter
, (expressionS
*) NULL
,
2083 mips_isa
< 3 ? "addu" : "daddu",
2084 "d,v,t", reg
, reg
, GP
);
2085 macro_build ((char *) NULL
, counter
, ep
,
2086 mips_isa
< 3 ? "lw" : "ld",
2087 "t,o(b)", reg
, (int) BFD_RELOC_MIPS_GOT_LO16
, reg
);
2088 p
= frag_var (rs_machine_dependent
, 12 + off
, 0,
2089 RELAX_ENCODE (12, 12 + off
, off
, 8 + off
, 0,
2090 mips_warn_about_macros
),
2091 ep
->X_add_symbol
, (long) 0, (char *) NULL
);
2094 /* We need a nop before loading from $gp. This special
2095 check is required because the lui which starts the main
2096 instruction stream does not refer to $gp, and so will not
2097 insert the nop which may be required. */
2098 macro_build (p
, counter
, (expressionS
*) NULL
, "nop", "");
2101 macro_build (p
, counter
, ep
,
2102 mips_isa
< 3 ? "lw" : "ld",
2103 "t,o(b)", reg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
2105 macro_build (p
, counter
, (expressionS
*) NULL
, "nop", "");
2107 macro_build (p
, counter
, ep
,
2108 mips_isa
< 3 ? "addiu" : "daddiu",
2109 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
2110 if (ex
.X_add_number
!= 0)
2112 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
2113 as_bad ("PIC code offset overflow (max 16 signed bits)");
2114 ex
.X_op
= O_constant
;
2115 macro_build ((char *) NULL
, counter
, &ex
,
2116 mips_isa
< 3 ? "addiu" : "daddiu",
2117 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
2120 else if (mips_pic
== EMBEDDED_PIC
)
2123 addiu $reg,$gp,<sym> (BFD_RELOC_MIPS_GPREL)
2125 macro_build ((char *) NULL
, counter
, ep
,
2126 mips_isa
< 3 ? "addiu" : "daddiu",
2127 "t,r,j", reg
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
2135 * This routine implements the seemingly endless macro or synthesized
2136 * instructions and addressing modes in the mips assembly language. Many
2137 * of these macros are simple and are similar to each other. These could
2138 * probably be handled by some kind of table or grammer aproach instead of
2139 * this verbose method. Others are not simple macros but are more like
2140 * optimizing code generation.
2141 * One interesting optimization is when several store macros appear
2142 * consecutivly that would load AT with the upper half of the same address.
2143 * The ensuing load upper instructions are ommited. This implies some kind
2144 * of global optimization. We currently only optimize within a single macro.
2145 * For many of the load and store macros if the address is specified as a
2146 * constant expression in the first 64k of memory (ie ld $2,0x4000c) we
2147 * first load register 'at' with zero and use it as the base register. The
2148 * mips assembler simply uses register $zero. Just one tiny optimization
2153 struct mips_cl_insn
*ip
;
2155 register int treg
, sreg
, dreg
, breg
;
2170 bfd_reloc_code_real_type r
;
2172 int hold_mips_optimize
;
2174 treg
= (ip
->insn_opcode
>> 16) & 0x1f;
2175 dreg
= (ip
->insn_opcode
>> 11) & 0x1f;
2176 sreg
= breg
= (ip
->insn_opcode
>> 21) & 0x1f;
2177 mask
= ip
->insn_mo
->mask
;
2179 expr1
.X_op
= O_constant
;
2180 expr1
.X_op_symbol
= NULL
;
2181 expr1
.X_add_symbol
= NULL
;
2182 expr1
.X_add_number
= 1;
2194 mips_emit_delays ();
2196 mips_any_noreorder
= 1;
2198 expr1
.X_add_number
= 8;
2199 macro_build ((char *) NULL
, &icnt
, &expr1
, "bgez", "s,p", sreg
);
2201 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
2203 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
, sreg
, 0);
2204 macro_build ((char *) NULL
, &icnt
, NULL
,
2205 dbl
? "dsub" : "sub",
2206 "d,v,t", dreg
, 0, sreg
);
2229 if (imm_expr
.X_add_number
>= -0x8000 && imm_expr
.X_add_number
< 0x8000)
2231 macro_build ((char *) NULL
, &icnt
, &imm_expr
, s
, "t,r,j", treg
, sreg
,
2232 (int) BFD_RELOC_LO16
);
2235 load_register (&icnt
, AT
, &imm_expr
, dbl
);
2236 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "d,v,t", treg
, sreg
, AT
);
2255 if (imm_expr
.X_add_number
>= 0 && imm_expr
.X_add_number
< 0x10000)
2257 if (mask
!= M_NOR_I
)
2258 macro_build ((char *) NULL
, &icnt
, &imm_expr
, s
, "t,r,i", treg
,
2259 sreg
, (int) BFD_RELOC_LO16
);
2262 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "ori", "t,r,i",
2263 treg
, sreg
, (int) BFD_RELOC_LO16
);
2264 macro_build ((char *) NULL
, &icnt
, NULL
, "nor", "d,v,t",
2270 load_register (&icnt
, AT
, &imm_expr
, 0);
2271 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "d,v,t", treg
, sreg
, AT
);
2288 if (imm_expr
.X_add_number
== 0)
2290 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "s,t,p", sreg
,
2294 load_register (&icnt
, AT
, &imm_expr
, 0);
2295 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "s,t,p", sreg
, AT
);
2303 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2304 likely
? "bgezl" : "bgez",
2310 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2311 likely
? "blezl" : "blez",
2315 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", AT
, sreg
, treg
);
2316 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2317 likely
? "beql" : "beq",
2324 /* check for > max integer */
2325 maxnum
= 0x7fffffff;
2333 if (imm_expr
.X_add_number
>= maxnum
2334 && (mips_isa
< 3 || sizeof (maxnum
) > 4))
2337 /* result is always false */
2340 as_warn ("Branch %s is always false (nop)", ip
->insn_mo
->name
);
2341 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
2345 as_warn ("Branch likely %s is always false", ip
->insn_mo
->name
);
2346 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "bnel",
2351 imm_expr
.X_add_number
++;
2355 if (mask
== M_BGEL_I
)
2357 if (imm_expr
.X_add_number
== 0)
2359 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2360 likely
? "bgezl" : "bgez",
2364 if (imm_expr
.X_add_number
== 1)
2366 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2367 likely
? "bgtzl" : "bgtz",
2371 maxnum
= 0x7fffffff;
2379 maxnum
= - maxnum
- 1;
2380 if (imm_expr
.X_add_number
<= maxnum
2381 && (mips_isa
< 3 || sizeof (maxnum
) > 4))
2384 /* result is always true */
2385 as_warn ("Branch %s is always true", ip
->insn_mo
->name
);
2386 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "b", "p");
2389 set_at (&icnt
, sreg
, 0);
2390 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2391 likely
? "beql" : "beq",
2402 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2403 likely
? "beql" : "beq",
2407 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", AT
, sreg
,
2409 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2410 likely
? "beql" : "beq",
2417 if (sreg
== 0 || imm_expr
.X_add_number
== -1)
2419 imm_expr
.X_add_number
++;
2423 if (mask
== M_BGEUL_I
)
2425 if (imm_expr
.X_add_number
== 0)
2427 if (imm_expr
.X_add_number
== 1)
2429 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2430 likely
? "bnel" : "bne",
2434 set_at (&icnt
, sreg
, 1);
2435 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2436 likely
? "beql" : "beq",
2445 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2446 likely
? "bgtzl" : "bgtz",
2452 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2453 likely
? "bltzl" : "bltz",
2457 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", AT
, treg
, sreg
);
2458 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2459 likely
? "bnel" : "bne",
2468 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2469 likely
? "bnel" : "bne",
2475 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", AT
, treg
,
2477 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2478 likely
? "bnel" : "bne",
2487 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2488 likely
? "blezl" : "blez",
2494 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2495 likely
? "bgezl" : "bgez",
2499 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", AT
, treg
, sreg
);
2500 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2501 likely
? "beql" : "beq",
2508 maxnum
= 0x7fffffff;
2516 if (imm_expr
.X_add_number
>= maxnum
2517 && (mips_isa
< 3 || sizeof (maxnum
) > 4))
2519 imm_expr
.X_add_number
++;
2523 if (mask
== M_BLTL_I
)
2525 if (imm_expr
.X_add_number
== 0)
2527 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2528 likely
? "bltzl" : "bltz",
2532 if (imm_expr
.X_add_number
== 1)
2534 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2535 likely
? "blezl" : "blez",
2539 set_at (&icnt
, sreg
, 0);
2540 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2541 likely
? "bnel" : "bne",
2550 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2551 likely
? "beql" : "beq",
2557 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", AT
, treg
,
2559 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2560 likely
? "beql" : "beq",
2567 if (sreg
== 0 || imm_expr
.X_add_number
== -1)
2569 imm_expr
.X_add_number
++;
2573 if (mask
== M_BLTUL_I
)
2575 if (imm_expr
.X_add_number
== 0)
2577 if (imm_expr
.X_add_number
== 1)
2579 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2580 likely
? "beql" : "beq",
2584 set_at (&icnt
, sreg
, 1);
2585 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2586 likely
? "bnel" : "bne",
2595 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2596 likely
? "bltzl" : "bltz",
2602 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2603 likely
? "bgtzl" : "bgtz",
2607 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", AT
, sreg
, treg
);
2608 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2609 likely
? "bnel" : "bne",
2620 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2621 likely
? "bnel" : "bne",
2625 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", AT
, sreg
,
2627 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2628 likely
? "bnel" : "bne",
2644 as_warn ("Divide by zero.");
2646 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", 0, 0);
2648 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 7);
2652 mips_emit_delays ();
2654 mips_any_noreorder
= 1;
2655 macro_build ((char *) NULL
, &icnt
, NULL
,
2656 dbl
? "ddiv" : "div",
2657 "z,s,t", sreg
, treg
);
2659 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", treg
, 0);
2662 expr1
.X_add_number
= 8;
2663 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", treg
, 0);
2664 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
2665 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 7);
2667 expr1
.X_add_number
= -1;
2668 macro_build ((char *) NULL
, &icnt
, &expr1
,
2669 dbl
? "daddiu" : "addiu",
2670 "t,r,j", AT
, 0, (int) BFD_RELOC_LO16
);
2671 expr1
.X_add_number
= mips_trap
? (dbl
? 12 : 8) : (dbl
? 20 : 16);
2672 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", treg
, AT
);
2675 expr1
.X_add_number
= 1;
2676 macro_build ((char *) NULL
, &icnt
, &expr1
, "daddiu", "t,r,j", AT
, 0,
2677 (int) BFD_RELOC_LO16
);
2678 macro_build ((char *) NULL
, &icnt
, NULL
, "dsll32", "d,w,<", AT
, AT
,
2683 expr1
.X_add_number
= 0x80000000;
2684 macro_build ((char *) NULL
, &icnt
, &expr1
, "lui", "t,u", AT
,
2685 (int) BFD_RELOC_HI16
);
2688 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", sreg
, AT
);
2691 expr1
.X_add_number
= 8;
2692 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", sreg
, AT
);
2693 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
2694 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 6);
2697 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d", dreg
);
2736 if (imm_expr
.X_add_number
== 0)
2738 as_warn ("Divide by zero.");
2740 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", 0, 0);
2742 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 7);
2745 if (imm_expr
.X_add_number
== 1)
2747 if (strcmp (s2
, "mflo") == 0)
2748 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
,
2751 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
, 0);
2754 if (imm_expr
.X_add_number
== -1
2755 && s
[strlen (s
) - 1] != 'u')
2757 if (strcmp (s2
, "mflo") == 0)
2760 macro_build ((char *) NULL
, &icnt
, NULL
, "dneg", "d,w", dreg
,
2763 macro_build ((char *) NULL
, &icnt
, NULL
, "neg", "d,w", dreg
,
2767 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
, 0);
2771 load_register (&icnt
, AT
, &imm_expr
, dbl
);
2772 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "z,s,t", sreg
, AT
);
2773 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "d", dreg
);
2792 mips_emit_delays ();
2794 mips_any_noreorder
= 1;
2795 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "z,s,t", sreg
, treg
);
2797 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", treg
, 0);
2800 expr1
.X_add_number
= 8;
2801 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", treg
, 0);
2802 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
2803 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 7);
2806 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "d", dreg
);
2812 /* Load the address of a symbol into a register. If breg is not
2813 zero, we then add a base register to it. */
2815 /* When generating embedded PIC code, we permit expressions of
2818 where bar is an address in the .text section. These are used
2819 when getting the addresses of functions. We don't permit
2820 X_add_number to be non-zero, because if the symbol is
2821 external the relaxing code needs to know that any addend is
2822 purely the offset to X_op_symbol. */
2823 if (mips_pic
== EMBEDDED_PIC
2824 && offset_expr
.X_op
== O_subtract
2825 && now_seg
== text_section
2826 && (offset_expr
.X_op_symbol
->sy_value
.X_op
== O_constant
2827 ? S_GET_SEGMENT (offset_expr
.X_op_symbol
) == text_section
2828 : (offset_expr
.X_op_symbol
->sy_value
.X_op
== O_symbol
2829 && (S_GET_SEGMENT (offset_expr
.X_op_symbol
2830 ->sy_value
.X_add_symbol
)
2833 && offset_expr
.X_add_number
== 0)
2835 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
2836 treg
, (int) BFD_RELOC_PCREL_HI16_S
);
2837 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2838 mips_isa
< 3 ? "addiu" : "daddiu",
2839 "t,r,j", treg
, treg
, (int) BFD_RELOC_PCREL_LO16
);
2843 if (offset_expr
.X_op
!= O_symbol
2844 && offset_expr
.X_op
!= O_constant
)
2846 as_bad ("expression too complex");
2847 offset_expr
.X_op
= O_constant
;
2861 if (offset_expr
.X_op
== O_constant
)
2862 load_register (&icnt
, tempreg
, &offset_expr
, dbl
);
2863 else if (mips_pic
== NO_PIC
)
2865 /* If this is a reference to an GP relative symbol, we want
2866 addiu $tempreg,$gp,<sym> (BFD_RELOC_MIPS_GPREL)
2868 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
2869 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
2870 If we have a constant, we need two instructions anyhow,
2871 so we may as well always use the latter form. */
2872 if ((valueT
) offset_expr
.X_add_number
>= MAX_GPREL_OFFSET
2873 || nopic_need_relax (offset_expr
.X_add_symbol
))
2878 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2879 mips_isa
< 3 ? "addiu" : "daddiu",
2880 "t,r,j", tempreg
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
2881 p
= frag_var (rs_machine_dependent
, 8, 0,
2882 RELAX_ENCODE (4, 8, 0, 4, 0,
2883 mips_warn_about_macros
),
2884 offset_expr
.X_add_symbol
, (long) 0,
2887 macro_build_lui (p
, &icnt
, &offset_expr
, tempreg
);
2890 macro_build (p
, &icnt
, &offset_expr
,
2891 mips_isa
< 3 ? "addiu" : "daddiu",
2892 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
2894 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
2896 /* If this is a reference to an external symbol, and there
2897 is no constant, we want
2898 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
2899 For a local symbol, we want
2900 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
2902 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
2904 If we have a small constant, and this is a reference to
2905 an external symbol, we want
2906 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
2908 addiu $tempreg,$tempreg,<constant>
2909 For a local symbol, we want the same instruction
2910 sequence, but we output a BFD_RELOC_LO16 reloc on the
2913 If we have a large constant, and this is a reference to
2914 an external symbol, we want
2915 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
2916 lui $at,<hiconstant>
2917 addiu $at,$at,<loconstant>
2918 addu $tempreg,$tempreg,$at
2919 For a local symbol, we want the same instruction
2920 sequence, but we output a BFD_RELOC_LO16 reloc on the
2921 addiu instruction. */
2922 expr1
.X_add_number
= offset_expr
.X_add_number
;
2923 offset_expr
.X_add_number
= 0;
2925 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2927 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
2928 if (expr1
.X_add_number
== 0)
2936 /* We're going to put in an addu instruction using
2937 tempreg, so we may as well insert the nop right
2939 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
2943 p
= frag_var (rs_machine_dependent
, 8 - off
, 0,
2944 RELAX_ENCODE (0, 8 - off
, -4 - off
, 4 - off
, 0,
2946 ? mips_warn_about_macros
2948 offset_expr
.X_add_symbol
, (long) 0,
2952 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
2955 macro_build (p
, &icnt
, &expr1
,
2956 mips_isa
< 3 ? "addiu" : "daddiu",
2957 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
2958 /* FIXME: If breg == 0, and the next instruction uses
2959 $tempreg, then if this variant case is used an extra
2960 nop will be generated. */
2962 else if (expr1
.X_add_number
>= -0x8000
2963 && expr1
.X_add_number
< 0x8000)
2965 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
2967 macro_build ((char *) NULL
, &icnt
, &expr1
,
2968 mips_isa
< 3 ? "addiu" : "daddiu",
2969 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
2970 (void) frag_var (rs_machine_dependent
, 0, 0,
2971 RELAX_ENCODE (0, 0, -12, -4, 0, 0),
2972 offset_expr
.X_add_symbol
, (long) 0,
2979 /* If we are going to add in a base register, and the
2980 target register and the base register are the same,
2981 then we are using AT as a temporary register. Since
2982 we want to load the constant into AT, we add our
2983 current AT (from the global offset table) and the
2984 register into the register now, and pretend we were
2985 not using a base register. */
2990 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
2992 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
2993 mips_isa
< 3 ? "addu" : "daddu",
2994 "d,v,t", treg
, AT
, breg
);
3000 /* Set mips_optimize around the lui instruction to avoid
3001 inserting an unnecessary nop after the lw. */
3002 hold_mips_optimize
= mips_optimize
;
3004 macro_build_lui ((char *) NULL
, &icnt
, &expr1
, AT
);
3005 mips_optimize
= hold_mips_optimize
;
3007 macro_build ((char *) NULL
, &icnt
, &expr1
,
3008 mips_isa
< 3 ? "addiu" : "daddiu",
3009 "t,r,j", AT
, AT
, (int) BFD_RELOC_LO16
);
3010 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3011 mips_isa
< 3 ? "addu" : "daddu",
3012 "d,v,t", tempreg
, tempreg
, AT
);
3013 (void) frag_var (rs_machine_dependent
, 0, 0,
3014 RELAX_ENCODE (0, 0, -16 + off1
, -8, 0, 0),
3015 offset_expr
.X_add_symbol
, (long) 0,
3020 else if (mips_pic
== SVR4_PIC
)
3024 /* This is the large GOT case. If this is a reference to an
3025 external symbol, and there is no constant, we want
3026 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
3027 addu $tempreg,$tempreg,$gp
3028 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
3029 For a local symbol, we want
3030 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3032 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
3034 If we have a small constant, and this is a reference to
3035 an external symbol, we want
3036 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
3037 addu $tempreg,$tempreg,$gp
3038 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
3040 addiu $tempreg,$tempreg,<constant>
3041 For a local symbol, we want
3042 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3044 addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16)
3046 If we have a large constant, and this is a reference to
3047 an external symbol, we want
3048 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
3049 addu $tempreg,$tempreg,$gp
3050 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
3051 lui $at,<hiconstant>
3052 addiu $at,$at,<loconstant>
3053 addu $tempreg,$tempreg,$at
3054 For a local symbol, we want
3055 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3056 lui $at,<hiconstant>
3057 addiu $at,$at,<loconstant> (BFD_RELOC_LO16)
3058 addu $tempreg,$tempreg,$at
3060 expr1
.X_add_number
= offset_expr
.X_add_number
;
3061 offset_expr
.X_add_number
= 0;
3063 if (reg_needs_delay (GP
))
3067 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
3068 tempreg
, (int) BFD_RELOC_MIPS_GOT_HI16
);
3069 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3070 mips_isa
< 3 ? "addu" : "daddu",
3071 "d,v,t", tempreg
, tempreg
, GP
);
3072 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3074 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT_LO16
,
3076 if (expr1
.X_add_number
== 0)
3084 /* We're going to put in an addu instruction using
3085 tempreg, so we may as well insert the nop right
3087 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3092 p
= frag_var (rs_machine_dependent
, 12 + gpdel
, 0,
3093 RELAX_ENCODE (12 + off
, 12 + gpdel
, gpdel
,
3096 ? mips_warn_about_macros
3098 offset_expr
.X_add_symbol
, (long) 0,
3101 else if (expr1
.X_add_number
>= -0x8000
3102 && expr1
.X_add_number
< 0x8000)
3104 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3106 macro_build ((char *) NULL
, &icnt
, &expr1
,
3107 mips_isa
< 3 ? "addiu" : "daddiu",
3108 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
3110 p
= frag_var (rs_machine_dependent
, 12 + gpdel
, 0,
3111 RELAX_ENCODE (20, 12 + gpdel
, gpdel
, 8 + gpdel
, 0,
3113 ? mips_warn_about_macros
3115 offset_expr
.X_add_symbol
, (long) 0,
3122 /* If we are going to add in a base register, and the
3123 target register and the base register are the same,
3124 then we are using AT as a temporary register. Since
3125 we want to load the constant into AT, we add our
3126 current AT (from the global offset table) and the
3127 register into the register now, and pretend we were
3128 not using a base register. */
3136 assert (tempreg
== AT
);
3137 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3139 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3140 mips_isa
< 3 ? "addu" : "daddu",
3141 "d,v,t", treg
, AT
, breg
);
3146 /* Set mips_optimize around the lui instruction to avoid
3147 inserting an unnecessary nop after the lw. */
3148 hold_mips_optimize
= mips_optimize
;
3150 macro_build_lui ((char *) NULL
, &icnt
, &expr1
, AT
);
3151 mips_optimize
= hold_mips_optimize
;
3153 macro_build ((char *) NULL
, &icnt
, &expr1
,
3154 mips_isa
< 3 ? "addiu" : "daddiu",
3155 "t,r,j", AT
, AT
, (int) BFD_RELOC_LO16
);
3156 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3157 mips_isa
< 3 ? "addu" : "daddu",
3158 "d,v,t", dreg
, dreg
, AT
);
3160 p
= frag_var (rs_machine_dependent
, 16 + gpdel
+ adj
, 0,
3161 RELAX_ENCODE (24 + adj
, 16 + gpdel
+ adj
, gpdel
,
3164 ? mips_warn_about_macros
3166 offset_expr
.X_add_symbol
, (long) 0,
3174 /* This is needed because this instruction uses $gp, but
3175 the first instruction on the main stream does not. */
3176 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
3179 macro_build (p
, &icnt
, &offset_expr
,
3181 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
3183 if (expr1
.X_add_number
>= -0x8000
3184 && expr1
.X_add_number
< 0x8000)
3186 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
3188 macro_build (p
, &icnt
, &expr1
,
3189 mips_isa
< 3 ? "addiu" : "daddiu",
3190 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
3191 /* FIXME: If add_number is 0, and there was no base
3192 register, the external symbol case ended with a load,
3193 so if the symbol turns out to not be external, and
3194 the next instruction uses tempreg, an unnecessary nop
3195 will be inserted. */
3201 /* We must add in the base register now, as in the
3202 external symbol case. */
3203 assert (tempreg
== AT
);
3204 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
3206 macro_build (p
, &icnt
, (expressionS
*) NULL
,
3207 mips_isa
< 3 ? "addu" : "daddu",
3208 "d,v,t", treg
, AT
, breg
);
3211 /* We set breg to 0 because we have arranged to add
3212 it in in both cases. */
3216 macro_build_lui (p
, &icnt
, &expr1
, AT
);
3218 macro_build (p
, &icnt
, &expr1
,
3219 mips_isa
< 3 ? "addiu" : "daddiu",
3220 "t,r,j", AT
, AT
, (int) BFD_RELOC_LO16
);
3222 macro_build (p
, &icnt
, (expressionS
*) NULL
,
3223 mips_isa
< 3 ? "addu" : "daddu",
3224 "d,v,t", tempreg
, tempreg
, AT
);
3228 else if (mips_pic
== EMBEDDED_PIC
)
3231 addiu $tempreg,$gp,<sym> (BFD_RELOC_MIPS_GPREL)
3233 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3234 mips_isa
< 3 ? "addiu" : "daddiu",
3235 "t,r,j", tempreg
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
3241 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3242 mips_isa
< 3 ? "addu" : "daddu",
3243 "d,v,t", treg
, tempreg
, breg
);
3251 /* The j instruction may not be used in PIC code, since it
3252 requires an absolute address. We convert it to a b
3254 if (mips_pic
== NO_PIC
)
3255 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "j", "a");
3257 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "b", "p");
3260 /* The jal instructions must be handled as macros because when
3261 generating PIC code they expand to multi-instruction
3262 sequences. Normally they are simple instructions. */
3267 if (mips_pic
== NO_PIC
3268 || mips_pic
== EMBEDDED_PIC
)
3269 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "jalr",
3271 else if (mips_pic
== SVR4_PIC
)
3273 if (sreg
!= PIC_CALL_REG
)
3274 as_warn ("MIPS PIC call to register other than $25");
3276 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "jalr",
3278 if (mips_cprestore_offset
< 0)
3279 as_warn ("No .cprestore pseudo-op used in PIC code");
3282 expr1
.X_add_number
= mips_cprestore_offset
;
3283 macro_build ((char *) NULL
, &icnt
, &expr1
,
3284 mips_isa
< 3 ? "lw" : "ld",
3285 "t,o(b)", GP
, (int) BFD_RELOC_LO16
, mips_frame_reg
);
3294 if (mips_pic
== NO_PIC
)
3295 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "jal", "a");
3296 else if (mips_pic
== SVR4_PIC
)
3298 /* If this is a reference to an external symbol, and we are
3299 using a small GOT, we want
3300 lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
3304 lw $gp,cprestore($sp)
3305 The cprestore value is set using the .cprestore
3306 pseudo-op. If we are using a big GOT, we want
3307 lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16)
3309 lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16)
3313 lw $gp,cprestore($sp)
3314 If the symbol is not external, we want
3315 lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3317 addiu $25,$25,<sym> (BFD_RELOC_LO16)
3320 lw $gp,cprestore($sp) */
3324 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3325 mips_isa
< 3 ? "lw" : "ld",
3326 "t,o(b)", PIC_CALL_REG
,
3327 (int) BFD_RELOC_MIPS_CALL16
, GP
);
3328 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3330 p
= frag_var (rs_machine_dependent
, 4, 0,
3331 RELAX_ENCODE (0, 4, -8, 0, 0, 0),
3332 offset_expr
.X_add_symbol
, (long) 0, (char *) NULL
);
3338 if (reg_needs_delay (GP
))
3342 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
3343 PIC_CALL_REG
, (int) BFD_RELOC_MIPS_CALL_HI16
);
3344 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3345 mips_isa
< 3 ? "addu" : "daddu",
3346 "d,v,t", PIC_CALL_REG
, PIC_CALL_REG
, GP
);
3347 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3348 mips_isa
< 3 ? "lw" : "ld",
3349 "t,o(b)", PIC_CALL_REG
,
3350 (int) BFD_RELOC_MIPS_CALL_LO16
, PIC_CALL_REG
);
3351 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3353 p
= frag_var (rs_machine_dependent
, 12 + gpdel
, 0,
3354 RELAX_ENCODE (16, 12 + gpdel
, gpdel
, 8 + gpdel
,
3356 offset_expr
.X_add_symbol
, (long) 0, (char *) NULL
);
3359 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
3362 macro_build (p
, &icnt
, &offset_expr
,
3363 mips_isa
< 3 ? "lw" : "ld",
3364 "t,o(b)", PIC_CALL_REG
,
3365 (int) BFD_RELOC_MIPS_GOT16
, GP
);
3367 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
3370 macro_build (p
, &icnt
, &offset_expr
,
3371 mips_isa
< 3 ? "addiu" : "daddiu",
3372 "t,r,j", PIC_CALL_REG
, PIC_CALL_REG
,
3373 (int) BFD_RELOC_LO16
);
3374 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3375 "jalr", "s", PIC_CALL_REG
);
3376 if (mips_cprestore_offset
< 0)
3377 as_warn ("No .cprestore pseudo-op used in PIC code");
3381 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3383 expr1
.X_add_number
= mips_cprestore_offset
;
3384 macro_build ((char *) NULL
, &icnt
, &expr1
,
3385 mips_isa
< 3 ? "lw" : "ld",
3386 "t,o(b)", GP
, (int) BFD_RELOC_LO16
,
3390 else if (mips_pic
== EMBEDDED_PIC
)
3392 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "bal", "p");
3393 /* The linker may expand the call to a longer sequence which
3394 uses $at, so we must break rather than return. */
3470 if (breg
== treg
|| coproc
|| lr
)
3539 if (mask
== M_LWC1_AB
3540 || mask
== M_SWC1_AB
3541 || mask
== M_LDC1_AB
3542 || mask
== M_SDC1_AB
3551 if (offset_expr
.X_op
!= O_constant
3552 && offset_expr
.X_op
!= O_symbol
)
3554 as_bad ("expression too complex");
3555 offset_expr
.X_op
= O_constant
;
3558 /* A constant expression in PIC code can be handled just as it
3559 is in non PIC code. */
3560 if (mips_pic
== NO_PIC
3561 || offset_expr
.X_op
== O_constant
)
3563 /* If this is a reference to a GP relative symbol, and there
3564 is no base register, we want
3565 <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL)
3566 Otherwise, if there is no base register, we want
3567 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
3568 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
3569 If we have a constant, we need two instructions anyhow,
3570 so we always use the latter form.
3572 If we have a base register, and this is a reference to a
3573 GP relative symbol, we want
3574 addu $tempreg,$breg,$gp
3575 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GPREL)
3577 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
3578 addu $tempreg,$tempreg,$breg
3579 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
3580 With a constant we always use the latter case. */
3583 if ((valueT
) offset_expr
.X_add_number
>= MAX_GPREL_OFFSET
3584 || nopic_need_relax (offset_expr
.X_add_symbol
))
3589 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
3590 treg
, (int) BFD_RELOC_MIPS_GPREL
, GP
);
3591 p
= frag_var (rs_machine_dependent
, 8, 0,
3592 RELAX_ENCODE (4, 8, 0, 4, 0,
3593 (mips_warn_about_macros
3594 || (used_at
&& mips_noat
))),
3595 offset_expr
.X_add_symbol
, (long) 0,
3599 macro_build_lui (p
, &icnt
, &offset_expr
, tempreg
);
3602 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
, treg
,
3603 (int) BFD_RELOC_LO16
, tempreg
);
3607 if ((valueT
) offset_expr
.X_add_number
>= MAX_GPREL_OFFSET
3608 || nopic_need_relax (offset_expr
.X_add_symbol
))
3613 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3614 mips_isa
< 3 ? "addu" : "daddu",
3615 "d,v,t", tempreg
, breg
, GP
);
3616 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
3617 treg
, (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
3618 p
= frag_var (rs_machine_dependent
, 12, 0,
3619 RELAX_ENCODE (8, 12, 0, 8, 0, 0),
3620 offset_expr
.X_add_symbol
, (long) 0,
3623 macro_build_lui (p
, &icnt
, &offset_expr
, tempreg
);
3626 macro_build (p
, &icnt
, (expressionS
*) NULL
,
3627 mips_isa
< 3 ? "addu" : "daddu",
3628 "d,v,t", tempreg
, tempreg
, breg
);
3631 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
, treg
,
3632 (int) BFD_RELOC_LO16
, tempreg
);
3635 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
3637 /* If this is a reference to an external symbol, we want
3638 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3640 <op> $treg,0($tempreg)
3642 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3644 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
3645 <op> $treg,0($tempreg)
3646 If there is a base register, we add it to $tempreg before
3647 the <op>. If there is a constant, we stick it in the
3648 <op> instruction. We don't handle constants larger than
3649 16 bits, because we have no way to load the upper 16 bits
3650 (actually, we could handle them for the subset of cases
3651 in which we are not using $at). */
3652 assert (offset_expr
.X_op
== O_symbol
);
3653 expr1
.X_add_number
= offset_expr
.X_add_number
;
3654 offset_expr
.X_add_number
= 0;
3655 if (expr1
.X_add_number
< -0x8000
3656 || expr1
.X_add_number
>= 0x8000)
3657 as_bad ("PIC code offset overflow (max 16 signed bits)");
3659 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3660 mips_isa
< 3 ? "lw" : "ld",
3661 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
3662 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
3663 p
= frag_var (rs_machine_dependent
, 4, 0,
3664 RELAX_ENCODE (0, 4, -8, 0, 0, 0),
3665 offset_expr
.X_add_symbol
, (long) 0,
3667 macro_build (p
, &icnt
, &offset_expr
,
3668 mips_isa
< 3 ? "addiu" : "daddiu",
3669 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
3671 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3672 mips_isa
< 3 ? "addu" : "daddu",
3673 "d,v,t", tempreg
, tempreg
, breg
);
3674 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
, treg
,
3675 (int) BFD_RELOC_LO16
, tempreg
);
3677 else if (mips_pic
== SVR4_PIC
)
3681 /* If this is a reference to an external symbol, we want
3682 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
3683 addu $tempreg,$tempreg,$gp
3684 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
3685 <op> $treg,0($tempreg)
3687 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3689 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
3690 <op> $treg,0($tempreg)
3691 If there is a base register, we add it to $tempreg before
3692 the <op>. If there is a constant, we stick it in the
3693 <op> instruction. We don't handle constants larger than
3694 16 bits, because we have no way to load the upper 16 bits
3695 (actually, we could handle them for the subset of cases
3696 in which we are not using $at). */
3697 assert (offset_expr
.X_op
== O_symbol
);
3698 expr1
.X_add_number
= offset_expr
.X_add_number
;
3699 offset_expr
.X_add_number
= 0;
3700 if (expr1
.X_add_number
< -0x8000
3701 || expr1
.X_add_number
>= 0x8000)
3702 as_bad ("PIC code offset overflow (max 16 signed bits)");
3703 if (reg_needs_delay (GP
))
3708 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
3709 tempreg
, (int) BFD_RELOC_MIPS_GOT_HI16
);
3710 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3711 mips_isa
< 3 ? "addu" : "daddu",
3712 "d,v,t", tempreg
, tempreg
, GP
);
3713 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3714 mips_isa
< 3 ? "lw" : "ld",
3715 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT_LO16
,
3717 p
= frag_var (rs_machine_dependent
, 12 + gpdel
, 0,
3718 RELAX_ENCODE (12, 12 + gpdel
, gpdel
, 8 + gpdel
, 0, 0),
3719 offset_expr
.X_add_symbol
, (long) 0, (char *) NULL
);
3722 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
3725 macro_build (p
, &icnt
, &offset_expr
,
3726 mips_isa
< 3 ? "lw" : "ld",
3727 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
3729 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
3731 macro_build (p
, &icnt
, &offset_expr
,
3732 mips_isa
< 3 ? "addiu" : "daddiu",
3733 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
3735 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3736 mips_isa
< 3 ? "addu" : "daddu",
3737 "d,v,t", tempreg
, tempreg
, breg
);
3738 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
, treg
,
3739 (int) BFD_RELOC_LO16
, tempreg
);
3741 else if (mips_pic
== EMBEDDED_PIC
)
3743 /* If there is no base register, we want
3744 <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL)
3745 If there is a base register, we want
3746 addu $tempreg,$breg,$gp
3747 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GPREL)
3749 assert (offset_expr
.X_op
== O_symbol
);
3752 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
3753 treg
, (int) BFD_RELOC_MIPS_GPREL
, GP
);
3758 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3759 mips_isa
< 3 ? "addu" : "daddu",
3760 "d,v,t", tempreg
, breg
, GP
);
3761 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
3762 treg
, (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
3775 load_register (&icnt
, treg
, &imm_expr
, 0);
3779 load_register (&icnt
, treg
, &imm_expr
, 1);
3783 if (imm_expr
.X_op
== O_constant
)
3785 load_register (&icnt
, AT
, &imm_expr
, 0);
3786 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3787 "mtc1", "t,G", AT
, treg
);
3792 assert (offset_expr
.X_op
== O_symbol
3793 && strcmp (segment_name (S_GET_SEGMENT
3794 (offset_expr
.X_add_symbol
)),
3796 && offset_expr
.X_add_number
== 0);
3797 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lwc1", "T,o(b)",
3798 treg
, (int) BFD_RELOC_MIPS_LITERAL
, GP
);
3803 /* We know that sym is in the .rdata section. First we get the
3804 upper 16 bits of the address. */
3805 if (mips_pic
== NO_PIC
)
3807 /* FIXME: This won't work for a 64 bit address. */
3808 macro_build_lui ((char *) NULL
, &icnt
, &offset_expr
, AT
);
3810 else if (mips_pic
== SVR4_PIC
)
3812 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3813 mips_isa
< 3 ? "lw" : "ld",
3814 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
3816 else if (mips_pic
== EMBEDDED_PIC
)
3818 /* For embedded PIC we pick up the entire address off $gp in
3819 a single instruction. */
3820 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3821 mips_isa
< 3 ? "addiu" : "daddiu",
3822 "t,r,j", AT
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
3823 offset_expr
.X_op
= O_constant
;
3824 offset_expr
.X_add_number
= 0;
3829 /* Now we load the register(s). */
3831 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "ld", "t,o(b)",
3832 treg
, (int) BFD_RELOC_LO16
, AT
);
3835 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lw", "t,o(b)",
3836 treg
, (int) BFD_RELOC_LO16
, AT
);
3839 /* FIXME: How in the world do we deal with the possible
3841 offset_expr
.X_add_number
+= 4;
3842 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lw", "t,o(b)",
3843 treg
+ 1, (int) BFD_RELOC_LO16
, AT
);
3847 /* To avoid confusion in tc_gen_reloc, we must ensure that this
3848 does not become a variant frag. */
3849 frag_wane (frag_now
);
3855 assert (offset_expr
.X_op
== O_symbol
3856 && offset_expr
.X_add_number
== 0);
3857 s
= segment_name (S_GET_SEGMENT (offset_expr
.X_add_symbol
));
3858 if (strcmp (s
, ".lit8") == 0)
3862 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "ldc1",
3863 "T,o(b)", treg
, (int) BFD_RELOC_MIPS_LITERAL
, GP
);
3867 r
= BFD_RELOC_MIPS_LITERAL
;
3872 assert (strcmp (s
, RDATA_SECTION_NAME
) == 0);
3873 if (mips_pic
== SVR4_PIC
)
3874 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3875 mips_isa
< 3 ? "lw" : "ld",
3876 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
3879 /* FIXME: This won't work for a 64 bit address. */
3880 macro_build_lui ((char *) NULL
, &icnt
, &offset_expr
, AT
);
3885 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "ldc1",
3886 "T,o(b)", treg
, (int) BFD_RELOC_LO16
, AT
);
3888 /* To avoid confusion in tc_gen_reloc, we must ensure
3889 that this does not become a variant frag. */
3890 frag_wane (frag_now
);
3901 /* Even on a big endian machine $fn comes before $fn+1. We have
3902 to adjust when loading from memory. */
3905 assert (mips_isa
< 2);
3906 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lwc1", "T,o(b)",
3907 byte_order
== LITTLE_ENDIAN
? treg
: treg
+ 1,
3909 /* FIXME: A possible overflow which I don't know how to deal
3911 offset_expr
.X_add_number
+= 4;
3912 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lwc1", "T,o(b)",
3913 byte_order
== LITTLE_ENDIAN
? treg
+ 1 : treg
,
3916 /* To avoid confusion in tc_gen_reloc, we must ensure that this
3917 does not become a variant frag. */
3918 frag_wane (frag_now
);
3927 * The MIPS assembler seems to check for X_add_number not
3928 * being double aligned and generating:
3931 * addiu at,at,%lo(foo+1)
3934 * But, the resulting address is the same after relocation so why
3935 * generate the extra instruction?
3982 if (offset_expr
.X_op
!= O_symbol
3983 && offset_expr
.X_op
!= O_constant
)
3985 as_bad ("expression too complex");
3986 offset_expr
.X_op
= O_constant
;
3989 /* Even on a big endian machine $fn comes before $fn+1. We have
3990 to adjust when loading from memory. We set coproc if we must
3991 load $fn+1 first. */
3992 if (byte_order
== LITTLE_ENDIAN
)
3995 if (mips_pic
== NO_PIC
3996 || offset_expr
.X_op
== O_constant
)
3998 /* If this is a reference to a GP relative symbol, we want
3999 <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL)
4000 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_MIPS_GPREL)
4001 If we have a base register, we use this
4003 <op> $treg,<sym>($at) (BFD_RELOC_MIPS_GPREL)
4004 <op> $treg+1,<sym>+4($at) (BFD_RELOC_MIPS_GPREL)
4005 If this is not a GP relative symbol, we want
4006 lui $at,<sym> (BFD_RELOC_HI16_S)
4007 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
4008 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
4009 If there is a base register, we add it to $at after the
4010 lui instruction. If there is a constant, we always use
4012 if ((valueT
) offset_expr
.X_add_number
>= MAX_GPREL_OFFSET
4013 || nopic_need_relax (offset_expr
.X_add_symbol
))
4032 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4033 mips_isa
< 3 ? "addu" : "daddu",
4034 "d,v,t", AT
, breg
, GP
);
4040 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
4041 coproc
? treg
+ 1 : treg
,
4042 (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
4043 offset_expr
.X_add_number
+= 4;
4045 /* Set mips_optimize to 2 to avoid inserting an
4047 hold_mips_optimize
= mips_optimize
;
4049 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
4050 coproc
? treg
: treg
+ 1,
4051 (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
4052 mips_optimize
= hold_mips_optimize
;
4054 p
= frag_var (rs_machine_dependent
, 12 + off
, 0,
4055 RELAX_ENCODE (8 + off
, 12 + off
, 0, 4 + off
, 1,
4056 used_at
&& mips_noat
),
4057 offset_expr
.X_add_symbol
, (long) 0,
4060 /* We just generated two relocs. When tc_gen_reloc
4061 handles this case, it will skip the first reloc and
4062 handle the second. The second reloc already has an
4063 extra addend of 4, which we added above. We must
4064 subtract it out, and then subtract another 4 to make
4065 the first reloc come out right. The second reloc
4066 will come out right because we are going to add 4 to
4067 offset_expr when we build its instruction below. */
4068 offset_expr
.X_add_number
-= 8;
4069 offset_expr
.X_op
= O_constant
;
4071 macro_build_lui (p
, &icnt
, &offset_expr
, AT
);
4076 macro_build (p
, &icnt
, (expressionS
*) NULL
,
4077 mips_isa
< 3 ? "addu" : "daddu",
4078 "d,v,t", AT
, breg
, AT
);
4082 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
,
4083 coproc
? treg
+ 1 : treg
,
4084 (int) BFD_RELOC_LO16
, AT
);
4087 /* FIXME: How do we handle overflow here? */
4088 offset_expr
.X_add_number
+= 4;
4089 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
,
4090 coproc
? treg
: treg
+ 1,
4091 (int) BFD_RELOC_LO16
, AT
);
4093 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
4097 /* If this is a reference to an external symbol, we want
4098 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4103 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4105 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
4106 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
4107 If there is a base register we add it to $at before the
4108 lwc1 instructions. If there is a constant we include it
4109 in the lwc1 instructions. */
4111 expr1
.X_add_number
= offset_expr
.X_add_number
;
4112 offset_expr
.X_add_number
= 0;
4113 if (expr1
.X_add_number
< -0x8000
4114 || expr1
.X_add_number
>= 0x8000 - 4)
4115 as_bad ("PIC code offset overflow (max 16 signed bits)");
4120 frag_grow (24 + off
);
4121 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4122 mips_isa
< 3 ? "lw" : "ld",
4123 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
4124 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
4126 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4127 mips_isa
< 3 ? "addu" : "daddu",
4128 "d,v,t", AT
, breg
, AT
);
4129 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
4130 coproc
? treg
+ 1 : treg
,
4131 (int) BFD_RELOC_LO16
, AT
);
4132 expr1
.X_add_number
+= 4;
4134 /* Set mips_optimize to 2 to avoid inserting an undesired
4136 hold_mips_optimize
= mips_optimize
;
4138 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
4139 coproc
? treg
: treg
+ 1,
4140 (int) BFD_RELOC_LO16
, AT
);
4141 mips_optimize
= hold_mips_optimize
;
4143 (void) frag_var (rs_machine_dependent
, 0, 0,
4144 RELAX_ENCODE (0, 0, -16 - off
, -8, 1, 0),
4145 offset_expr
.X_add_symbol
, (long) 0,
4148 else if (mips_pic
== SVR4_PIC
)
4152 /* If this is a reference to an external symbol, we want
4153 lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16)
4155 lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16)
4160 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4162 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
4163 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
4164 If there is a base register we add it to $at before the
4165 lwc1 instructions. If there is a constant we include it
4166 in the lwc1 instructions. */
4168 expr1
.X_add_number
= offset_expr
.X_add_number
;
4169 offset_expr
.X_add_number
= 0;
4170 if (expr1
.X_add_number
< -0x8000
4171 || expr1
.X_add_number
>= 0x8000 - 4)
4172 as_bad ("PIC code offset overflow (max 16 signed bits)");
4173 if (reg_needs_delay (GP
))
4182 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
4183 AT
, (int) BFD_RELOC_MIPS_GOT_HI16
);
4184 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4185 mips_isa
< 3 ? "addu" : "daddu",
4186 "d,v,t", AT
, AT
, GP
);
4187 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4188 mips_isa
< 3 ? "lw" : "ld",
4189 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT_LO16
, AT
);
4190 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
4192 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4193 mips_isa
< 3 ? "addu" : "daddu",
4194 "d,v,t", AT
, breg
, AT
);
4195 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
4196 coproc
? treg
+ 1 : treg
,
4197 (int) BFD_RELOC_LO16
, AT
);
4198 expr1
.X_add_number
+= 4;
4200 /* Set mips_optimize to 2 to avoid inserting an undesired
4202 hold_mips_optimize
= mips_optimize
;
4204 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
4205 coproc
? treg
: treg
+ 1,
4206 (int) BFD_RELOC_LO16
, AT
);
4207 mips_optimize
= hold_mips_optimize
;
4208 expr1
.X_add_number
-= 4;
4210 p
= frag_var (rs_machine_dependent
, 16 + gpdel
+ off
, 0,
4211 RELAX_ENCODE (24 + off
, 16 + gpdel
+ off
, gpdel
,
4212 8 + gpdel
+ off
, 1, 0),
4213 offset_expr
.X_add_symbol
, (long) 0,
4217 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4220 macro_build (p
, &icnt
, &offset_expr
,
4221 mips_isa
< 3 ? "lw" : "ld",
4222 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
4224 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4228 macro_build (p
, &icnt
, (expressionS
*) NULL
,
4229 mips_isa
< 3 ? "addu" : "daddu",
4230 "d,v,t", AT
, breg
, AT
);
4233 macro_build (p
, &icnt
, &expr1
, s
, fmt
,
4234 coproc
? treg
+ 1 : treg
,
4235 (int) BFD_RELOC_LO16
, AT
);
4237 expr1
.X_add_number
+= 4;
4239 /* Set mips_optimize to 2 to avoid inserting an undesired
4241 hold_mips_optimize
= mips_optimize
;
4243 macro_build (p
, &icnt
, &expr1
, s
, fmt
,
4244 coproc
? treg
: treg
+ 1,
4245 (int) BFD_RELOC_LO16
, AT
);
4246 mips_optimize
= hold_mips_optimize
;
4248 else if (mips_pic
== EMBEDDED_PIC
)
4250 /* If there is no base register, we use
4251 <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL)
4252 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_MIPS_GPREL)
4253 If we have a base register, we use
4255 <op> $treg,<sym>($at) (BFD_RELOC_MIPS_GPREL)
4256 <op> $treg+1,<sym>+4($at) (BFD_RELOC_MIPS_GPREL)
4265 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4266 mips_isa
< 3 ? "addu" : "daddu",
4267 "d,v,t", AT
, breg
, GP
);
4272 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
4273 coproc
? treg
+ 1 : treg
,
4274 (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
4275 offset_expr
.X_add_number
+= 4;
4276 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
4277 coproc
? treg
: treg
+ 1,
4278 (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
4294 assert (mips_isa
< 3);
4295 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
4296 (int) BFD_RELOC_LO16
, breg
);
4297 offset_expr
.X_add_number
+= 4;
4298 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
+ 1,
4299 (int) BFD_RELOC_LO16
, breg
);
4301 #ifdef LOSING_COMPILER
4307 as_warn ("Macro used $at after \".set noat\"");
4312 struct mips_cl_insn
*ip
;
4314 register int treg
, sreg
, dreg
, breg
;
4329 bfd_reloc_code_real_type r
;
4332 treg
= (ip
->insn_opcode
>> 16) & 0x1f;
4333 dreg
= (ip
->insn_opcode
>> 11) & 0x1f;
4334 sreg
= breg
= (ip
->insn_opcode
>> 21) & 0x1f;
4335 mask
= ip
->insn_mo
->mask
;
4337 expr1
.X_op
= O_constant
;
4338 expr1
.X_op_symbol
= NULL
;
4339 expr1
.X_add_symbol
= NULL
;
4340 expr1
.X_add_number
= 1;
4344 #endif /* LOSING_COMPILER */
4349 macro_build ((char *) NULL
, &icnt
, NULL
,
4350 dbl
? "dmultu" : "multu",
4352 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
4358 /* The MIPS assembler some times generates shifts and adds. I'm
4359 not trying to be that fancy. GCC should do this for us
4361 load_register (&icnt
, AT
, &imm_expr
, dbl
);
4362 macro_build ((char *) NULL
, &icnt
, NULL
,
4363 dbl
? "dmult" : "mult",
4365 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
4371 mips_emit_delays ();
4373 mips_any_noreorder
= 1;
4374 macro_build ((char *) NULL
, &icnt
, NULL
,
4375 dbl
? "dmult" : "mult",
4377 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
4378 macro_build ((char *) NULL
, &icnt
, NULL
,
4379 dbl
? "dsra32" : "sra",
4380 "d,w,<", dreg
, dreg
, 31);
4381 macro_build ((char *) NULL
, &icnt
, NULL
, "mfhi", "d", AT
);
4383 macro_build ((char *) NULL
, &icnt
, NULL
, "tne", "s,t", dreg
, AT
);
4386 expr1
.X_add_number
= 8;
4387 macro_build ((char *) NULL
, &icnt
, &expr1
, "beq", "s,t,p", dreg
, AT
);
4388 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
4389 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 6);
4392 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
4398 mips_emit_delays ();
4400 mips_any_noreorder
= 1;
4401 macro_build ((char *) NULL
, &icnt
, NULL
,
4402 dbl
? "dmultu" : "multu",
4404 macro_build ((char *) NULL
, &icnt
, NULL
, "mfhi", "d", AT
);
4405 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
4407 macro_build ((char *) NULL
, &icnt
, NULL
, "tne", "s,t", AT
, 0);
4410 expr1
.X_add_number
= 8;
4411 macro_build ((char *) NULL
, &icnt
, &expr1
, "beq", "s,t,p", AT
, 0);
4412 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
4413 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 6);
4419 macro_build ((char *) NULL
, &icnt
, NULL
, "subu", "d,v,t", AT
, 0, treg
);
4420 macro_build ((char *) NULL
, &icnt
, NULL
, "srlv", "d,t,s", AT
, sreg
, AT
);
4421 macro_build ((char *) NULL
, &icnt
, NULL
, "sllv", "d,t,s", dreg
, sreg
,
4423 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
4427 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", AT
, sreg
,
4428 (int) (imm_expr
.X_add_number
& 0x1f));
4429 macro_build ((char *) NULL
, &icnt
, NULL
, "srl", "d,w,<", dreg
, sreg
,
4430 (int) ((0 - imm_expr
.X_add_number
) & 0x1f));
4431 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
4435 macro_build ((char *) NULL
, &icnt
, NULL
, "subu", "d,v,t", AT
, 0, treg
);
4436 macro_build ((char *) NULL
, &icnt
, NULL
, "sllv", "d,t,s", AT
, sreg
, AT
);
4437 macro_build ((char *) NULL
, &icnt
, NULL
, "srlv", "d,t,s", dreg
, sreg
,
4439 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
4443 macro_build ((char *) NULL
, &icnt
, NULL
, "srl", "d,w,<", AT
, sreg
,
4444 (int) (imm_expr
.X_add_number
& 0x1f));
4445 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", dreg
, sreg
,
4446 (int) ((0 - imm_expr
.X_add_number
) & 0x1f));
4447 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
4451 assert (mips_isa
< 2);
4452 /* Even on a big endian machine $fn comes before $fn+1. We have
4453 to adjust when storing to memory. */
4454 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "swc1", "T,o(b)",
4455 byte_order
== LITTLE_ENDIAN
? treg
: treg
+ 1,
4456 (int) BFD_RELOC_LO16
, breg
);
4457 offset_expr
.X_add_number
+= 4;
4458 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "swc1", "T,o(b)",
4459 byte_order
== LITTLE_ENDIAN
? treg
+ 1 : treg
,
4460 (int) BFD_RELOC_LO16
, breg
);
4465 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
4466 treg
, (int) BFD_RELOC_LO16
);
4468 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
4469 sreg
, (int) BFD_RELOC_LO16
);
4472 macro_build ((char *) NULL
, &icnt
, NULL
, "xor", "d,v,t", dreg
,
4474 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
4475 dreg
, (int) BFD_RELOC_LO16
);
4480 if (imm_expr
.X_add_number
== 0)
4482 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
4483 sreg
, (int) BFD_RELOC_LO16
);
4488 as_warn ("Instruction %s: result is always false",
4490 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
, 0);
4493 if (imm_expr
.X_add_number
>= 0 && imm_expr
.X_add_number
< 0x10000)
4495 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "xori", "t,r,i", dreg
,
4496 sreg
, (int) BFD_RELOC_LO16
);
4499 else if (imm_expr
.X_add_number
> -0x8000 && imm_expr
.X_add_number
< 0)
4501 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
4502 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
4503 mips_isa
< 3 ? "addiu" : "daddiu",
4504 "t,r,j", dreg
, sreg
,
4505 (int) BFD_RELOC_LO16
);
4510 load_register (&icnt
, AT
, &imm_expr
, 0);
4511 macro_build ((char *) NULL
, &icnt
, NULL
, "xor", "d,v,t", dreg
,
4515 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
, dreg
,
4516 (int) BFD_RELOC_LO16
);
4521 case M_SGE
: /* sreg >= treg <==> not (sreg < treg) */
4527 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, sreg
, treg
);
4528 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
4529 (int) BFD_RELOC_LO16
);
4532 case M_SGE_I
: /* sreg >= I <==> not (sreg < I) */
4534 if (imm_expr
.X_add_number
>= -0x8000 && imm_expr
.X_add_number
< 0x8000)
4536 macro_build ((char *) NULL
, &icnt
, &expr1
,
4537 mask
== M_SGE_I
? "slti" : "sltiu",
4538 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
4543 load_register (&icnt
, AT
, &imm_expr
, 0);
4544 macro_build ((char *) NULL
, &icnt
, NULL
,
4545 mask
== M_SGE_I
? "slt" : "sltu",
4546 "d,v,t", dreg
, sreg
, AT
);
4549 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
4550 (int) BFD_RELOC_LO16
);
4555 case M_SGT
: /* sreg > treg <==> treg < sreg */
4561 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, treg
, sreg
);
4564 case M_SGT_I
: /* sreg > I <==> I < sreg */
4570 load_register (&icnt
, AT
, &imm_expr
, 0);
4571 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, AT
, sreg
);
4574 case M_SLE
: /* sreg <= treg <==> treg >= sreg <==> not (treg < sreg) */
4580 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, treg
, sreg
);
4581 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
4582 (int) BFD_RELOC_LO16
);
4585 case M_SLE_I
: /* sreg <= I <==> I >= sreg <==> not (I < sreg) */
4591 load_register (&icnt
, AT
, &imm_expr
, 0);
4592 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, AT
, sreg
);
4593 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
4594 (int) BFD_RELOC_LO16
);
4598 if (imm_expr
.X_add_number
>= -0x8000 && imm_expr
.X_add_number
< 0x8000)
4600 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "slti", "t,r,j",
4601 dreg
, sreg
, (int) BFD_RELOC_LO16
);
4604 load_register (&icnt
, AT
, &imm_expr
, 0);
4605 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", dreg
, sreg
, AT
);
4609 if (imm_expr
.X_add_number
>= -0x8000 && imm_expr
.X_add_number
< 0x8000)
4611 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "sltiu", "t,r,j",
4612 dreg
, sreg
, (int) BFD_RELOC_LO16
);
4615 load_register (&icnt
, AT
, &imm_expr
, 0);
4616 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, sreg
,
4622 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0,
4625 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0,
4629 macro_build ((char *) NULL
, &icnt
, NULL
, "xor", "d,v,t", dreg
,
4631 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0,
4637 if (imm_expr
.X_add_number
== 0)
4639 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0,
4645 as_warn ("Instruction %s: result is always true",
4647 macro_build ((char *) NULL
, &icnt
, &expr1
,
4648 mips_isa
< 3 ? "addiu" : "daddiu",
4649 "t,r,j", dreg
, 0, (int) BFD_RELOC_LO16
);
4652 if (imm_expr
.X_add_number
>= 0 && imm_expr
.X_add_number
< 0x10000)
4654 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "xori", "t,r,i",
4655 dreg
, sreg
, (int) BFD_RELOC_LO16
);
4658 else if (imm_expr
.X_add_number
> -0x8000 && imm_expr
.X_add_number
< 0)
4660 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
4661 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
4662 mips_isa
< 3 ? "addiu" : "daddiu",
4663 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
4668 load_register (&icnt
, AT
, &imm_expr
, 0);
4669 macro_build ((char *) NULL
, &icnt
, NULL
, "xor", "d,v,t", dreg
,
4673 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0, dreg
);
4681 if (imm_expr
.X_add_number
> -0x8000 && imm_expr
.X_add_number
<= 0x8000)
4683 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
4684 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
4685 dbl
? "daddi" : "addi",
4686 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
4689 load_register (&icnt
, AT
, &imm_expr
, dbl
);
4690 macro_build ((char *) NULL
, &icnt
, NULL
,
4691 dbl
? "dsub" : "sub",
4692 "d,v,t", dreg
, sreg
, AT
);
4698 if (imm_expr
.X_add_number
> -0x8000 && imm_expr
.X_add_number
<= 0x8000)
4700 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
4701 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
4702 dbl
? "daddiu" : "addiu",
4703 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
4706 load_register (&icnt
, AT
, &imm_expr
, dbl
);
4707 macro_build ((char *) NULL
, &icnt
, NULL
,
4708 dbl
? "dsubu" : "subu",
4709 "d,v,t", dreg
, sreg
, AT
);
4730 load_register (&icnt
, AT
, &imm_expr
, 0);
4731 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "s,t", sreg
, AT
);
4736 assert (mips_isa
< 2);
4737 sreg
= (ip
->insn_opcode
>> 11) & 0x1f; /* floating reg */
4738 dreg
= (ip
->insn_opcode
>> 06) & 0x1f; /* floating reg */
4741 * Is the double cfc1 instruction a bug in the mips assembler;
4742 * or is there a reason for it?
4744 mips_emit_delays ();
4746 mips_any_noreorder
= 1;
4747 macro_build ((char *) NULL
, &icnt
, NULL
, "cfc1", "t,G", treg
, 31);
4748 macro_build ((char *) NULL
, &icnt
, NULL
, "cfc1", "t,G", treg
, 31);
4749 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "");
4750 expr1
.X_add_number
= 3;
4751 macro_build ((char *) NULL
, &icnt
, &expr1
, "ori", "t,r,i", AT
, treg
,
4752 (int) BFD_RELOC_LO16
);
4753 expr1
.X_add_number
= 2;
4754 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", AT
, AT
,
4755 (int) BFD_RELOC_LO16
);
4756 macro_build ((char *) NULL
, &icnt
, NULL
, "ctc1", "t,G", AT
, 31);
4757 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "");
4758 macro_build ((char *) NULL
, &icnt
, NULL
,
4759 mask
== M_TRUNCWD
? "cvt.w.d" : "cvt.w.s", "D,S", dreg
, sreg
);
4760 macro_build ((char *) NULL
, &icnt
, NULL
, "ctc1", "t,G", treg
, 31);
4761 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "");
4771 if (offset_expr
.X_add_number
>= 0x7fff)
4772 as_bad ("operand overflow");
4773 /* avoid load delay */
4774 if (byte_order
== LITTLE_ENDIAN
)
4775 offset_expr
.X_add_number
+= 1;
4776 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
4777 (int) BFD_RELOC_LO16
, breg
);
4778 if (byte_order
== LITTLE_ENDIAN
)
4779 offset_expr
.X_add_number
-= 1;
4781 offset_expr
.X_add_number
+= 1;
4782 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lbu", "t,o(b)", AT
,
4783 (int) BFD_RELOC_LO16
, breg
);
4784 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", treg
, treg
, 8);
4785 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", treg
, treg
, AT
);
4798 if (offset_expr
.X_add_number
>= 0x8000 - off
)
4799 as_bad ("operand overflow");
4800 if (byte_order
== LITTLE_ENDIAN
)
4801 offset_expr
.X_add_number
+= off
;
4802 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
4803 (int) BFD_RELOC_LO16
, breg
);
4804 if (byte_order
== LITTLE_ENDIAN
)
4805 offset_expr
.X_add_number
-= off
;
4807 offset_expr
.X_add_number
+= off
;
4808 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s2
, "t,o(b)", treg
,
4809 (int) BFD_RELOC_LO16
, breg
);
4822 load_address (&icnt
, AT
, &offset_expr
);
4824 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4825 mips_isa
< 3 ? "addu" : "daddu",
4826 "d,v,t", AT
, AT
, breg
);
4827 if (byte_order
== LITTLE_ENDIAN
)
4828 expr1
.X_add_number
= off
;
4830 expr1
.X_add_number
= 0;
4831 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, "t,o(b)", treg
,
4832 (int) BFD_RELOC_LO16
, AT
);
4833 if (byte_order
== LITTLE_ENDIAN
)
4834 expr1
.X_add_number
= 0;
4836 expr1
.X_add_number
= off
;
4837 macro_build ((char *) NULL
, &icnt
, &expr1
, s2
, "t,o(b)", treg
,
4838 (int) BFD_RELOC_LO16
, AT
);
4843 load_address (&icnt
, AT
, &offset_expr
);
4845 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4846 mips_isa
< 3 ? "addu" : "daddu",
4847 "d,v,t", AT
, AT
, breg
);
4848 if (byte_order
== BIG_ENDIAN
)
4849 expr1
.X_add_number
= 0;
4850 macro_build ((char *) NULL
, &icnt
, &expr1
,
4851 mask
== M_ULH_A
? "lb" : "lbu", "t,o(b)", treg
,
4852 (int) BFD_RELOC_LO16
, AT
);
4853 if (byte_order
== BIG_ENDIAN
)
4854 expr1
.X_add_number
= 1;
4856 expr1
.X_add_number
= 0;
4857 macro_build ((char *) NULL
, &icnt
, &expr1
, "lbu", "t,o(b)", AT
,
4858 (int) BFD_RELOC_LO16
, AT
);
4859 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", treg
,
4861 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", treg
,
4866 if (offset_expr
.X_add_number
>= 0x7fff)
4867 as_bad ("operand overflow");
4868 if (byte_order
== BIG_ENDIAN
)
4869 offset_expr
.X_add_number
+= 1;
4870 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "sb", "t,o(b)", treg
,
4871 (int) BFD_RELOC_LO16
, breg
);
4872 macro_build ((char *) NULL
, &icnt
, NULL
, "srl", "d,w,<", AT
, treg
, 8);
4873 if (byte_order
== BIG_ENDIAN
)
4874 offset_expr
.X_add_number
-= 1;
4876 offset_expr
.X_add_number
+= 1;
4877 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "sb", "t,o(b)", AT
,
4878 (int) BFD_RELOC_LO16
, breg
);
4891 if (offset_expr
.X_add_number
>= 0x8000 - off
)
4892 as_bad ("operand overflow");
4893 if (byte_order
== LITTLE_ENDIAN
)
4894 offset_expr
.X_add_number
+= off
;
4895 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
4896 (int) BFD_RELOC_LO16
, breg
);
4897 if (byte_order
== LITTLE_ENDIAN
)
4898 offset_expr
.X_add_number
-= off
;
4900 offset_expr
.X_add_number
+= off
;
4901 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s2
, "t,o(b)", treg
,
4902 (int) BFD_RELOC_LO16
, breg
);
4915 load_address (&icnt
, AT
, &offset_expr
);
4917 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4918 mips_isa
< 3 ? "addu" : "daddu",
4919 "d,v,t", AT
, AT
, breg
);
4920 if (byte_order
== LITTLE_ENDIAN
)
4921 expr1
.X_add_number
= off
;
4923 expr1
.X_add_number
= 0;
4924 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, "t,o(b)", treg
,
4925 (int) BFD_RELOC_LO16
, AT
);
4926 if (byte_order
== LITTLE_ENDIAN
)
4927 expr1
.X_add_number
= 0;
4929 expr1
.X_add_number
= off
;
4930 macro_build ((char *) NULL
, &icnt
, &expr1
, s2
, "t,o(b)", treg
,
4931 (int) BFD_RELOC_LO16
, AT
);
4935 load_address (&icnt
, AT
, &offset_expr
);
4937 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4938 mips_isa
< 3 ? "addu" : "daddu",
4939 "d,v,t", AT
, AT
, breg
);
4940 if (byte_order
== LITTLE_ENDIAN
)
4941 expr1
.X_add_number
= 0;
4942 macro_build ((char *) NULL
, &icnt
, &expr1
, "sb", "t,o(b)", treg
,
4943 (int) BFD_RELOC_LO16
, AT
);
4944 macro_build ((char *) NULL
, &icnt
, NULL
, "srl", "d,w,<", treg
,
4946 if (byte_order
== LITTLE_ENDIAN
)
4947 expr1
.X_add_number
= 1;
4949 expr1
.X_add_number
= 0;
4950 macro_build ((char *) NULL
, &icnt
, &expr1
, "sb", "t,o(b)", treg
,
4951 (int) BFD_RELOC_LO16
, AT
);
4952 if (byte_order
== LITTLE_ENDIAN
)
4953 expr1
.X_add_number
= 0;
4955 expr1
.X_add_number
= 1;
4956 macro_build ((char *) NULL
, &icnt
, &expr1
, "lbu", "t,o(b)", AT
,
4957 (int) BFD_RELOC_LO16
, AT
);
4958 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", treg
,
4960 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", treg
,
4965 as_bad ("Macro %s not implemented yet", ip
->insn_mo
->name
);
4969 as_warn ("Macro used $at after \".set noat\"");
4972 /* This routine assembles an instruction into its binary format. As a
4973 side effect, it sets one of the global variables imm_reloc or
4974 offset_reloc to the type of relocation to do if one of the operands
4975 is an address expression. */
4980 struct mips_cl_insn
*ip
;
4985 struct mips_opcode
*insn
;
4988 unsigned int lastregno
= 0;
4993 for (s
= str
; islower (*s
) || (*s
>= '0' && *s
<= '3') || *s
== '6' || *s
== '.'; ++s
)
5005 as_fatal ("Unknown opcode: `%s'", str
);
5007 if ((insn
= (struct mips_opcode
*) hash_find (op_hash
, str
)) == NULL
)
5009 as_warn ("`%s' not in hash table.", str
);
5010 insn_error
= "ERROR: Unrecognized opcode";
5018 assert (strcmp (insn
->name
, str
) == 0);
5020 if (insn
->pinfo
== INSN_MACRO
)
5021 insn_isa
= insn
->match
;
5022 else if ((insn
->pinfo
& INSN_ISA
) == INSN_ISA2
)
5024 else if ((insn
->pinfo
& INSN_ISA
) == INSN_ISA3
)
5026 else if ((insn
->pinfo
& INSN_ISA
) == INSN_ISA4
)
5031 if (insn_isa
> mips_isa
5032 || ((insn
->pinfo
& INSN_ISA
) == INSN_4650
5034 || ((insn
->pinfo
& INSN_ISA
) == INSN_4010
5036 || ((insn
->pinfo
& INSN_ISA
) == INSN_4100
5039 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
]
5040 && strcmp (insn
->name
, insn
[1].name
) == 0)
5045 as_warn ("Instruction not supported on this processor");
5049 ip
->insn_opcode
= insn
->match
;
5050 for (args
= insn
->args
;; ++args
)
5056 case '\0': /* end of args */
5069 ip
->insn_opcode
|= lastregno
<< 21;
5074 ip
->insn_opcode
|= lastregno
<< 16;
5078 ip
->insn_opcode
|= lastregno
<< 11;
5084 /* handle optional base register.
5085 Either the base register is omitted or
5086 we must have a left paren. */
5087 /* this is dependent on the next operand specifier
5088 is a 'b' for base register */
5089 assert (args
[1] == 'b');
5093 case ')': /* these must match exactly */
5098 case '<': /* must be at least one digit */
5100 * According to the manual, if the shift amount is greater
5101 * than 31 or less than 0 the the shift amount should be
5102 * mod 32. In reality the mips assembler issues an error.
5103 * We issue a warning and mask out all but the low 5 bits.
5105 my_getExpression (&imm_expr
, s
);
5106 check_absolute_expr (ip
, &imm_expr
);
5107 if ((unsigned long) imm_expr
.X_add_number
> 31)
5109 as_warn ("Improper shift amount (%ld)",
5110 (long) imm_expr
.X_add_number
);
5111 imm_expr
.X_add_number
= imm_expr
.X_add_number
& 0x1f;
5113 ip
->insn_opcode
|= imm_expr
.X_add_number
<< 6;
5114 imm_expr
.X_op
= O_absent
;
5118 case '>': /* shift amount minus 32 */
5119 my_getExpression (&imm_expr
, s
);
5120 check_absolute_expr (ip
, &imm_expr
);
5121 if ((unsigned long) imm_expr
.X_add_number
< 32
5122 || (unsigned long) imm_expr
.X_add_number
> 63)
5124 ip
->insn_opcode
|= (imm_expr
.X_add_number
- 32) << 6;
5125 imm_expr
.X_op
= O_absent
;
5129 case 'k': /* cache code */
5130 case 'h': /* prefx code */
5131 my_getExpression (&imm_expr
, s
);
5132 check_absolute_expr (ip
, &imm_expr
);
5133 if ((unsigned long) imm_expr
.X_add_number
> 31)
5135 as_warn ("Invalid value for `%s' (%lu)",
5137 (unsigned long) imm_expr
.X_add_number
);
5138 imm_expr
.X_add_number
&= 0x1f;
5141 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_CACHE
;
5143 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_PREFX
;
5144 imm_expr
.X_op
= O_absent
;
5148 case 'c': /* break code */
5149 my_getExpression (&imm_expr
, s
);
5150 check_absolute_expr (ip
, &imm_expr
);
5151 if ((unsigned) imm_expr
.X_add_number
> 1023)
5152 as_warn ("Illegal break code (%ld)",
5153 (long) imm_expr
.X_add_number
);
5154 ip
->insn_opcode
|= imm_expr
.X_add_number
<< 16;
5155 imm_expr
.X_op
= O_absent
;
5159 case 'B': /* syscall code */
5160 my_getExpression (&imm_expr
, s
);
5161 check_absolute_expr (ip
, &imm_expr
);
5162 if ((unsigned) imm_expr
.X_add_number
> 0xfffff)
5163 as_warn ("Illegal syscall code (%ld)",
5164 (long) imm_expr
.X_add_number
);
5165 ip
->insn_opcode
|= imm_expr
.X_add_number
<< 6;
5166 imm_expr
.X_op
= O_absent
;
5170 case 'C': /* Coprocessor code */
5171 my_getExpression (&imm_expr
, s
);
5172 check_absolute_expr (ip
, &imm_expr
);
5173 if ((unsigned long) imm_expr
.X_add_number
>= (1<<25))
5175 as_warn ("Coproccesor code > 25 bits (%ld)",
5176 (long) imm_expr
.X_add_number
);
5177 imm_expr
.X_add_number
&= ((1<<25) - 1);
5179 ip
->insn_opcode
|= imm_expr
.X_add_number
;
5180 imm_expr
.X_op
= O_absent
;
5184 case 'b': /* base register */
5185 case 'd': /* destination register */
5186 case 's': /* source register */
5187 case 't': /* target register */
5188 case 'r': /* both target and source */
5189 case 'v': /* both dest and source */
5190 case 'w': /* both dest and target */
5191 case 'E': /* coprocessor target register */
5192 case 'G': /* coprocessor destination register */
5193 case 'x': /* ignore register name */
5194 case 'z': /* must be zero register */
5208 while (isdigit (*s
));
5210 as_bad ("Invalid register number (%d)", regno
);
5212 else if (*args
== 'E' || *args
== 'G')
5216 if (s
[1] == 'f' && s
[2] == 'p')
5221 else if (s
[1] == 's' && s
[2] == 'p')
5226 else if (s
[1] == 'g' && s
[2] == 'p')
5231 else if (s
[1] == 'a' && s
[2] == 't')
5236 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '0')
5241 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '1')
5249 if (regno
== AT
&& ! mips_noat
)
5250 as_warn ("Used $at without \".set noat\"");
5256 if (c
== 'r' || c
== 'v' || c
== 'w')
5263 /* 'z' only matches $0. */
5264 if (c
== 'z' && regno
!= 0)
5272 ip
->insn_opcode
|= regno
<< 21;
5276 ip
->insn_opcode
|= regno
<< 11;
5281 ip
->insn_opcode
|= regno
<< 16;
5284 /* This case exists because on the r3000 trunc
5285 expands into a macro which requires a gp
5286 register. On the r6000 or r4000 it is
5287 assembled into a single instruction which
5288 ignores the register. Thus the insn version
5289 is MIPS_ISA2 and uses 'x', and the macro
5290 version is MIPS_ISA1 and uses 't'. */
5293 /* This case is for the div instruction, which
5294 acts differently if the destination argument
5295 is $0. This only matches $0, and is checked
5296 outside the switch. */
5307 ip
->insn_opcode
|= lastregno
<< 21;
5310 ip
->insn_opcode
|= lastregno
<< 16;
5315 case 'D': /* floating point destination register */
5316 case 'S': /* floating point source register */
5317 case 'T': /* floating point target register */
5318 case 'R': /* floating point source register */
5322 if (s
[0] == '$' && s
[1] == 'f' && isdigit (s
[2]))
5332 while (isdigit (*s
));
5335 as_bad ("Invalid float register number (%d)", regno
);
5337 if ((regno
& 1) != 0
5339 && ! (strcmp (str
, "mtc1") == 0 ||
5340 strcmp (str
, "mfc1") == 0 ||
5341 strcmp (str
, "lwc1") == 0 ||
5342 strcmp (str
, "swc1") == 0))
5343 as_warn ("Float register should be even, was %d",
5351 if (c
== 'V' || c
== 'W')
5361 ip
->insn_opcode
|= regno
<< 6;
5365 ip
->insn_opcode
|= regno
<< 11;
5369 ip
->insn_opcode
|= regno
<< 16;
5372 ip
->insn_opcode
|= regno
<< 21;
5381 ip
->insn_opcode
|= lastregno
<< 11;
5384 ip
->insn_opcode
|= lastregno
<< 16;
5390 my_getExpression (&imm_expr
, s
);
5391 if (imm_expr
.X_op
!= O_big
)
5392 check_absolute_expr (ip
, &imm_expr
);
5397 my_getExpression (&offset_expr
, s
);
5398 imm_reloc
= BFD_RELOC_32
;
5410 unsigned char temp
[8];
5412 unsigned int length
;
5417 /* These only appear as the last operand in an
5418 instruction, and every instruction that accepts
5419 them in any variant accepts them in all variants.
5420 This means we don't have to worry about backing out
5421 any changes if the instruction does not match.
5423 The difference between them is the size of the
5424 floating point constant and where it goes. For 'F'
5425 and 'L' the constant is 64 bits; for 'f' and 'l' it
5426 is 32 bits. Where the constant is placed is based
5427 on how the MIPS assembler does things:
5430 f -- immediate value
5433 The .lit4 and .lit8 sections are only used if
5434 permitted by the -G argument.
5436 When generating embedded PIC code, we use the
5437 .lit8 section but not the .lit4 section (we can do
5438 .lit4 inline easily; we need to put .lit8
5439 somewhere in the data segment, and using .lit8
5440 permits the linker to eventually combine identical
5443 f64
= *args
== 'F' || *args
== 'L';
5445 save_in
= input_line_pointer
;
5446 input_line_pointer
= s
;
5447 err
= md_atof (f64
? 'd' : 'f', (char *) temp
, &len
);
5449 s
= input_line_pointer
;
5450 input_line_pointer
= save_in
;
5451 if (err
!= NULL
&& *err
!= '\0')
5453 as_bad ("Bad floating point constant: %s", err
);
5454 memset (temp
, '\0', sizeof temp
);
5455 length
= f64
? 8 : 4;
5458 assert (length
== (f64
? 8 : 4));
5462 && (! USE_GLOBAL_POINTER_OPT
5463 || mips_pic
== EMBEDDED_PIC
5464 || g_switch_value
< 4)
5467 imm_expr
.X_op
= O_constant
;
5468 if (byte_order
== LITTLE_ENDIAN
)
5469 imm_expr
.X_add_number
=
5470 (((((((int) temp
[3] << 8)
5475 imm_expr
.X_add_number
=
5476 (((((((int) temp
[0] << 8)
5483 const char *newname
;
5486 /* Switch to the right section. */
5488 subseg
= now_subseg
;
5491 default: /* unused default case avoids warnings. */
5493 newname
= RDATA_SECTION_NAME
;
5494 if (USE_GLOBAL_POINTER_OPT
&& g_switch_value
>= 8)
5498 newname
= RDATA_SECTION_NAME
;
5501 assert (!USE_GLOBAL_POINTER_OPT
5502 || g_switch_value
>= 4);
5506 new_seg
= subseg_new (newname
, (subsegT
) 0);
5507 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
5508 bfd_set_section_flags (stdoutput
, new_seg
,
5513 frag_align (*args
== 'l' ? 2 : 3, 0);
5514 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
5515 record_alignment (new_seg
, 4);
5517 record_alignment (new_seg
, *args
== 'l' ? 2 : 3);
5519 as_bad ("Can't use floating point insn in this section");
5521 /* Set the argument to the current address in the
5523 offset_expr
.X_op
= O_symbol
;
5524 offset_expr
.X_add_symbol
=
5525 symbol_new ("L0\001", now_seg
,
5526 (valueT
) frag_now_fix (), frag_now
);
5527 offset_expr
.X_add_number
= 0;
5529 /* Put the floating point number into the section. */
5530 p
= frag_more ((int) length
);
5531 memcpy (p
, temp
, length
);
5533 /* Switch back to the original section. */
5534 subseg_set (seg
, subseg
);
5539 case 'i': /* 16 bit unsigned immediate */
5540 case 'j': /* 16 bit signed immediate */
5541 imm_reloc
= BFD_RELOC_LO16
;
5542 c
= my_getSmallExpression (&imm_expr
, s
);
5547 if (imm_expr
.X_op
== O_constant
)
5548 imm_expr
.X_add_number
=
5549 (imm_expr
.X_add_number
>> 16) & 0xffff;
5552 imm_reloc
= BFD_RELOC_HI16_S
;
5553 imm_unmatched_hi
= true;
5556 imm_reloc
= BFD_RELOC_HI16
;
5559 else if (imm_expr
.X_op
!= O_big
)
5560 check_absolute_expr (ip
, &imm_expr
);
5563 if (imm_expr
.X_op
== O_big
5564 || imm_expr
.X_add_number
< 0
5565 || imm_expr
.X_add_number
>= 0x10000)
5567 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
5568 !strcmp (insn
->name
, insn
[1].name
))
5570 as_bad ("16 bit expression not in range 0..65535");
5578 /* The upper bound should be 0x8000, but
5579 unfortunately the MIPS assembler accepts numbers
5580 from 0x8000 to 0xffff and sign extends them, and
5581 we want to be compatible. We only permit this
5582 extended range for an instruction which does not
5583 provide any further alternates, since those
5584 alternates may handle other cases. People should
5585 use the numbers they mean, rather than relying on
5586 a mysterious sign extension. */
5587 more
= (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
5588 strcmp (insn
->name
, insn
[1].name
) == 0);
5593 if (imm_expr
.X_op
== O_big
5594 || imm_expr
.X_add_number
< -0x8000
5595 || imm_expr
.X_add_number
>= max
5597 && imm_expr
.X_add_number
< 0
5599 && imm_expr
.X_unsigned
5600 && sizeof (imm_expr
.X_add_number
) <= 4))
5604 as_bad ("16 bit expression not in range -32768..32767");
5610 case 'o': /* 16 bit offset */
5611 c
= my_getSmallExpression (&offset_expr
, s
);
5613 /* If this value won't fit into a 16 bit offset, then go
5614 find a macro that will generate the 32 bit offset
5615 code pattern. As a special hack, we accept the
5616 difference of two local symbols as a constant. This
5617 is required to suppose embedded PIC switches, which
5618 use an instruction which looks like
5619 lw $4,$L12-$LS12($4)
5620 The problem with handling this in a more general
5621 fashion is that the macro function doesn't expect to
5622 see anything which can be handled in a single
5623 constant instruction. */
5625 && (offset_expr
.X_op
!= O_constant
5626 || offset_expr
.X_add_number
>= 0x8000
5627 || offset_expr
.X_add_number
< -0x8000)
5628 && (mips_pic
!= EMBEDDED_PIC
5629 || offset_expr
.X_op
!= O_subtract
5630 || now_seg
!= text_section
5631 || (S_GET_SEGMENT (offset_expr
.X_op_symbol
)
5635 offset_reloc
= BFD_RELOC_LO16
;
5636 if (c
== 'h' || c
== 'H')
5638 assert (offset_expr
.X_op
== O_constant
);
5639 offset_expr
.X_add_number
=
5640 (offset_expr
.X_add_number
>> 16) & 0xffff;
5645 case 'p': /* pc relative offset */
5646 offset_reloc
= BFD_RELOC_16_PCREL_S2
;
5647 my_getExpression (&offset_expr
, s
);
5651 case 'u': /* upper 16 bits */
5652 c
= my_getSmallExpression (&imm_expr
, s
);
5653 if (imm_expr
.X_op
== O_constant
5654 && (imm_expr
.X_add_number
< 0
5655 || imm_expr
.X_add_number
>= 0x10000))
5656 as_bad ("lui expression not in range 0..65535");
5657 imm_reloc
= BFD_RELOC_LO16
;
5662 if (imm_expr
.X_op
== O_constant
)
5663 imm_expr
.X_add_number
=
5664 (imm_expr
.X_add_number
>> 16) & 0xffff;
5667 imm_reloc
= BFD_RELOC_HI16_S
;
5668 imm_unmatched_hi
= true;
5671 imm_reloc
= BFD_RELOC_HI16
;
5677 case 'a': /* 26 bit address */
5678 my_getExpression (&offset_expr
, s
);
5680 offset_reloc
= BFD_RELOC_MIPS_JMP
;
5683 case 'N': /* 3 bit branch condition code */
5684 case 'M': /* 3 bit compare condition code */
5685 my_getExpression (&imm_expr
, s
);
5686 check_absolute_expr (ip
, &imm_expr
);
5687 if ((unsigned long) imm_expr
.X_add_number
> 7)
5689 as_warn ("Condition code > 7 (%ld)",
5690 (long) imm_expr
.X_add_number
);
5691 imm_expr
.X_add_number
&= 7;
5694 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_BCC
;
5696 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_CCC
;
5697 imm_expr
.X_op
= O_absent
;
5702 fprintf (stderr
, "bad char = '%c'\n", *args
);
5707 /* Args don't match. */
5708 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
5709 !strcmp (insn
->name
, insn
[1].name
))
5715 insn_error
= "ERROR: Illegal operands";
5724 my_getSmallExpression (ep
, str
)
5735 ((str
[1] == 'h' && str
[2] == 'i')
5736 || (str
[1] == 'H' && str
[2] == 'I')
5737 || (str
[1] == 'l' && str
[2] == 'o'))
5749 * A small expression may be followed by a base register.
5750 * Scan to the end of this operand, and then back over a possible
5751 * base register. Then scan the small expression up to that
5752 * point. (Based on code in sparc.c...)
5754 for (sp
= str
; *sp
&& *sp
!= ','; sp
++)
5756 if (sp
- 4 >= str
&& sp
[-1] == RP
)
5758 if (isdigit (sp
[-2]))
5760 for (sp
-= 3; sp
>= str
&& isdigit (*sp
); sp
--)
5762 if (*sp
== '$' && sp
> str
&& sp
[-1] == LP
)
5768 else if (sp
- 5 >= str
5771 && ((sp
[-3] == 'f' && sp
[-2] == 'p')
5772 || (sp
[-3] == 's' && sp
[-2] == 'p')
5773 || (sp
[-3] == 'g' && sp
[-2] == 'p')
5774 || (sp
[-3] == 'a' && sp
[-2] == 't')))
5780 /* no expression means zero offset */
5783 /* %xx(reg) is an error */
5784 ep
->X_op
= O_absent
;
5789 ep
->X_op
= O_constant
;
5792 ep
->X_add_symbol
= NULL
;
5793 ep
->X_op_symbol
= NULL
;
5794 ep
->X_add_number
= 0;
5799 my_getExpression (ep
, str
);
5806 my_getExpression (ep
, str
);
5807 return c
; /* => %hi or %lo encountered */
5811 my_getExpression (ep
, str
)
5817 save_in
= input_line_pointer
;
5818 input_line_pointer
= str
;
5820 expr_end
= input_line_pointer
;
5821 input_line_pointer
= save_in
;
5824 /* Turn a string in input_line_pointer into a floating point constant
5825 of type type, and store the appropriate bytes in *litP. The number
5826 of LITTLENUMS emitted is stored in *sizeP . An error message is
5827 returned, or NULL on OK. */
5830 md_atof (type
, litP
, sizeP
)
5836 LITTLENUM_TYPE words
[4];
5852 return "bad call to md_atof";
5855 t
= atof_ieee (input_line_pointer
, type
, words
);
5857 input_line_pointer
= t
;
5861 if (byte_order
== LITTLE_ENDIAN
)
5863 for (i
= prec
- 1; i
>= 0; i
--)
5865 md_number_to_chars (litP
, (valueT
) words
[i
], 2);
5871 for (i
= 0; i
< prec
; i
++)
5873 md_number_to_chars (litP
, (valueT
) words
[i
], 2);
5882 md_number_to_chars (buf
, val
, n
)
5890 number_to_chars_littleendian (buf
, val
, n
);
5894 number_to_chars_bigendian (buf
, val
, n
);
5902 CONST
char *md_shortopts
= "O::g::G:";
5904 struct option md_longopts
[] = {
5905 #define OPTION_MIPS1 (OPTION_MD_BASE + 1)
5906 {"mips0", no_argument
, NULL
, OPTION_MIPS1
},
5907 {"mips1", no_argument
, NULL
, OPTION_MIPS1
},
5908 #define OPTION_MIPS2 (OPTION_MD_BASE + 2)
5909 {"mips2", no_argument
, NULL
, OPTION_MIPS2
},
5910 #define OPTION_MIPS3 (OPTION_MD_BASE + 3)
5911 {"mips3", no_argument
, NULL
, OPTION_MIPS3
},
5912 #define OPTION_MIPS4 (OPTION_MD_BASE + 4)
5913 {"mips4", no_argument
, NULL
, OPTION_MIPS4
},
5914 #define OPTION_MCPU (OPTION_MD_BASE + 5)
5915 {"mcpu", required_argument
, NULL
, OPTION_MCPU
},
5916 #define OPTION_MEMBEDDED_PIC (OPTION_MD_BASE + 6)
5917 {"membedded-pic", no_argument
, NULL
, OPTION_MEMBEDDED_PIC
},
5918 #define OPTION_TRAP (OPTION_MD_BASE + 9)
5919 {"trap", no_argument
, NULL
, OPTION_TRAP
},
5920 {"no-break", no_argument
, NULL
, OPTION_TRAP
},
5921 #define OPTION_BREAK (OPTION_MD_BASE + 10)
5922 {"break", no_argument
, NULL
, OPTION_BREAK
},
5923 {"no-trap", no_argument
, NULL
, OPTION_BREAK
},
5924 #define OPTION_EB (OPTION_MD_BASE + 11)
5925 {"EB", no_argument
, NULL
, OPTION_EB
},
5926 #define OPTION_EL (OPTION_MD_BASE + 12)
5927 {"EL", no_argument
, NULL
, OPTION_EL
},
5928 #define OPTION_M4650 (OPTION_MD_BASE + 13)
5929 {"m4650", no_argument
, NULL
, OPTION_M4650
},
5930 #define OPTION_NO_M4650 (OPTION_MD_BASE + 14)
5931 {"no-m4650", no_argument
, NULL
, OPTION_NO_M4650
},
5932 #define OPTION_M4010 (OPTION_MD_BASE + 15)
5933 {"m4010", no_argument
, NULL
, OPTION_M4010
},
5934 #define OPTION_NO_M4010 (OPTION_MD_BASE + 16)
5935 {"no-m4010", no_argument
, NULL
, OPTION_NO_M4010
},
5936 #define OPTION_M4100 (OPTION_MD_BASE + 17)
5937 {"m4100", no_argument
, NULL
, OPTION_M4100
},
5938 #define OPTION_NO_M4100 (OPTION_MD_BASE + 18)
5939 {"no-m4100", no_argument
, NULL
, OPTION_NO_M4100
},
5941 #define OPTION_CALL_SHARED (OPTION_MD_BASE + 7)
5942 #define OPTION_NON_SHARED (OPTION_MD_BASE + 8)
5943 #define OPTION_XGOT (OPTION_MD_BASE + 19)
5944 #define OPTION_32 (OPTION_MD_BASE + 20)
5945 #define OPTION_64 (OPTION_MD_BASE + 21)
5947 {"KPIC", no_argument
, NULL
, OPTION_CALL_SHARED
},
5948 {"xgot", no_argument
, NULL
, OPTION_XGOT
},
5949 {"call_shared", no_argument
, NULL
, OPTION_CALL_SHARED
},
5950 {"non_shared", no_argument
, NULL
, OPTION_NON_SHARED
},
5951 {"32", no_argument
, NULL
, OPTION_32
},
5952 {"64", no_argument
, NULL
, OPTION_64
},
5955 {NULL
, no_argument
, NULL
, 0}
5957 size_t md_longopts_size
= sizeof(md_longopts
);
5960 md_parse_option (c
, arg
)
5975 target_big_endian
= 1;
5979 target_big_endian
= 0;
5983 if (arg
&& arg
[1] == '0')
5993 mips_debug
= atoi (arg
);
5994 /* When the MIPS assembler sees -g or -g2, it does not do
5995 optimizations which limit full symbolic debugging. We take
5996 that to be equivalent to -O0. */
5997 if (mips_debug
== 2)
6029 /* Identify the processor type */
6031 if (strcmp (p
, "default") == 0
6032 || strcmp (p
, "DEFAULT") == 0)
6038 /* We need to cope with the various "vr" prefixes for the 4300
6040 if (*p
== 'v' || *p
== 'V')
6046 if (*p
== 'r' || *p
== 'R')
6053 if (strcmp (p
, "10000") == 0
6054 || strcmp (p
, "10k") == 0
6055 || strcmp (p
, "10K") == 0)
6060 if (strcmp (p
, "2000") == 0
6061 || strcmp (p
, "2k") == 0
6062 || strcmp (p
, "2K") == 0)
6067 if (strcmp (p
, "3000") == 0
6068 || strcmp (p
, "3k") == 0
6069 || strcmp (p
, "3K") == 0)
6074 if (strcmp (p
, "4000") == 0
6075 || strcmp (p
, "4k") == 0
6076 || strcmp (p
, "4K") == 0)
6078 else if (strcmp (p
, "4100") == 0)
6084 else if (strcmp (p
, "4300") == 0)
6086 else if (strcmp (p
, "4400") == 0)
6088 else if (strcmp (p
, "4600") == 0)
6090 else if (strcmp (p
, "4650") == 0)
6096 else if (strcmp (p
, "4010") == 0)
6105 if (strcmp (p
, "6000") == 0
6106 || strcmp (p
, "6k") == 0
6107 || strcmp (p
, "6K") == 0)
6112 if (strcmp (p
, "8000") == 0
6113 || strcmp (p
, "8k") == 0
6114 || strcmp (p
, "8K") == 0)
6119 if (strcmp (p
, "orion") == 0)
6124 if (sv
&& mips_cpu
!= 4300 && mips_cpu
!= 4100)
6126 as_bad ("ignoring invalid leading 'v' in -mcpu=%s switch", arg
);
6132 as_bad ("invalid architecture -mcpu=%s", arg
);
6143 case OPTION_NO_M4650
:
6151 case OPTION_NO_M4010
:
6159 case OPTION_NO_M4100
:
6163 case OPTION_MEMBEDDED_PIC
:
6164 mips_pic
= EMBEDDED_PIC
;
6165 if (USE_GLOBAL_POINTER_OPT
&& g_switch_seen
)
6167 as_bad ("-G may not be used with embedded PIC code");
6170 g_switch_value
= 0x7fffffff;
6173 /* When generating ELF code, we permit -KPIC and -call_shared to
6174 select SVR4_PIC, and -non_shared to select no PIC. This is
6175 intended to be compatible with Irix 5. */
6176 case OPTION_CALL_SHARED
:
6177 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
6179 as_bad ("-call_shared is supported only for ELF format");
6182 mips_pic
= SVR4_PIC
;
6183 if (g_switch_seen
&& g_switch_value
!= 0)
6185 as_bad ("-G may not be used with SVR4 PIC code");
6191 case OPTION_NON_SHARED
:
6192 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
6194 as_bad ("-non_shared is supported only for ELF format");
6200 /* The -xgot option tells the assembler to use 32 offsets when
6201 accessing the got in SVR4_PIC mode. It is for Irix
6208 if (! USE_GLOBAL_POINTER_OPT
)
6210 as_bad ("-G is not supported for this configuration");
6213 else if (mips_pic
== SVR4_PIC
|| mips_pic
== EMBEDDED_PIC
)
6215 as_bad ("-G may not be used with SVR4 or embedded PIC code");
6219 g_switch_value
= atoi (arg
);
6223 /* The -32 and -64 options tell the assembler to output the 32
6224 bit or the 64 bit MIPS ELF format. */
6241 md_show_usage (stream
)
6246 -membedded-pic generate embedded position independent code\n\
6247 -EB generate big endian output\n\
6248 -EL generate little endian output\n\
6249 -g, -g2 do not remove uneeded NOPs or swap branches\n\
6250 -G NUM allow referencing objects up to NUM bytes\n\
6251 implicitly with the gp register [default 8]\n");
6253 -mips1, -mcpu=r{2,3}000 generate code for r2000 and r3000\n\
6254 -mips2, -mcpu=r6000 generate code for r6000\n\
6255 -mips3, -mcpu=r4000 generate code for r4000\n\
6256 -mips4, -mcpu=r8000 generate code for r8000\n\
6257 -mcpu=vr4300 generate code for vr4300\n\
6258 -mcpu=vr4100 generate code for vr4100\n\
6259 -m4650 permit R4650 instructions\n\
6260 -no-m4650 do not permit R4650 instructions\n\
6261 -m4010 permit R4010 instructions\n\
6262 -no-m4010 do not permit R4010 instructions\n\
6263 -m4100 permit VR4100 instructions\n\
6264 -no-m4100 do not permit VR4100 instructions\n");
6266 -O0 remove unneeded NOPs, do not swap branches\n\
6267 -O remove unneeded NOPs and swap branches\n\
6268 --trap, --no-break trap exception on div by 0 and mult overflow\n\
6269 --break, --no-trap break exception on div by 0 and mult overflow\n");
6272 -KPIC, -call_shared generate SVR4 position independent code\n\
6273 -non_shared do not generate position independent code\n\
6274 -xgot assume a 32 bit GOT\n\
6275 -32 create 32 bit object file (default)\n\
6276 -64 create 64 bit object file\n");
6281 mips_init_after_args ()
6283 if (target_big_endian
)
6284 byte_order
= BIG_ENDIAN
;
6286 byte_order
= LITTLE_ENDIAN
;
6290 md_pcrel_from (fixP
)
6293 if (OUTPUT_FLAVOR
!= bfd_target_aout_flavour
6294 && fixP
->fx_addsy
!= (symbolS
*) NULL
6295 && ! S_IS_DEFINED (fixP
->fx_addsy
))
6297 /* This makes a branch to an undefined symbol be a branch to the
6298 current location. */
6302 /* return the address of the delay slot */
6303 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
6306 /* This is called by emit_expr via TC_CONS_FIX_NEW when creating a
6307 reloc for a cons. We could use the definition there, except that
6308 we want to handle 64 bit relocs specially. */
6311 cons_fix_new_mips (frag
, where
, nbytes
, exp
)
6314 unsigned int nbytes
;
6317 /* If we are assembling in 32 bit mode, turn an 8 byte reloc into a
6319 if (nbytes
== 8 && ! mips_64
)
6321 if (byte_order
== BIG_ENDIAN
)
6326 if (nbytes
!= 2 && nbytes
!= 4 && nbytes
!= 8)
6327 as_bad ("Unsupported reloc size %d", nbytes
);
6329 fix_new_exp (frag_now
, where
, (int) nbytes
, exp
, 0,
6332 : (nbytes
== 4 ? BFD_RELOC_32
: BFD_RELOC_64
)));
6335 /* Sort any unmatched HI16_S relocs so that they immediately precede
6336 the corresponding LO reloc. This is called before md_apply_fix and
6337 tc_gen_reloc. Unmatched HI16_S relocs can only be generated by
6338 explicit use of the %hi modifier. */
6343 struct mips_hi_fixup
*l
;
6345 for (l
= mips_hi_fixup_list
; l
!= NULL
; l
= l
->next
)
6347 segment_info_type
*seginfo
;
6350 assert (l
->fixp
->fx_r_type
== BFD_RELOC_HI16_S
);
6352 /* Check quickly whether the next fixup happens to be a matching
6354 if (l
->fixp
->fx_next
!= NULL
6355 && l
->fixp
->fx_next
->fx_r_type
== BFD_RELOC_LO16
6356 && l
->fixp
->fx_addsy
== l
->fixp
->fx_next
->fx_addsy
6357 && l
->fixp
->fx_offset
== l
->fixp
->fx_next
->fx_offset
)
6360 /* Look through the fixups for this segment for a matching %lo.
6361 When we find one, move the %hi just in front of it. We do
6362 this in two passes. In the first pass, we try to find a
6363 unique %lo. In the second pass, we permit multiple %hi
6364 relocs for a single %lo (this is a GNU extension). */
6365 seginfo
= seg_info (l
->seg
);
6366 for (pass
= 0; pass
< 2; pass
++)
6371 for (f
= seginfo
->fix_root
; f
!= NULL
; f
= f
->fx_next
)
6373 /* Check whether this is a %lo fixup which matches l->fixp. */
6374 if (f
->fx_r_type
== BFD_RELOC_LO16
6375 && f
->fx_addsy
== l
->fixp
->fx_addsy
6376 && f
->fx_offset
== l
->fixp
->fx_offset
6379 || prev
->fx_r_type
!= BFD_RELOC_HI16_S
6380 || prev
->fx_addsy
!= f
->fx_addsy
6381 || prev
->fx_offset
!= f
->fx_offset
))
6385 /* Move l->fixp before f. */
6386 for (pf
= &seginfo
->fix_root
;
6388 pf
= &(*pf
)->fx_next
)
6389 assert (*pf
!= NULL
);
6391 *pf
= l
->fixp
->fx_next
;
6393 l
->fixp
->fx_next
= f
;
6395 seginfo
->fix_root
= l
->fixp
;
6397 prev
->fx_next
= l
->fixp
;
6409 as_warn_where (l
->fixp
->fx_file
, l
->fixp
->fx_line
,
6410 "Unmatched %%hi reloc");
6415 /* When generating embedded PIC code we need to use a special
6416 relocation to represent the difference of two symbols in the .text
6417 section (switch tables use a difference of this sort). See
6418 include/coff/mips.h for details. This macro checks whether this
6419 fixup requires the special reloc. */
6420 #define SWITCH_TABLE(fixp) \
6421 ((fixp)->fx_r_type == BFD_RELOC_32 \
6422 && (fixp)->fx_addsy != NULL \
6423 && (fixp)->fx_subsy != NULL \
6424 && S_GET_SEGMENT ((fixp)->fx_addsy) == text_section \
6425 && S_GET_SEGMENT ((fixp)->fx_subsy) == text_section)
6427 /* When generating embedded PIC code we must keep all PC relative
6428 relocations, in case the linker has to relax a call. We also need
6429 to keep relocations for switch table entries. */
6433 mips_force_relocation (fixp
)
6436 return (mips_pic
== EMBEDDED_PIC
6438 || SWITCH_TABLE (fixp
)
6439 || fixp
->fx_r_type
== BFD_RELOC_PCREL_HI16_S
6440 || fixp
->fx_r_type
== BFD_RELOC_PCREL_LO16
));
6443 /* Apply a fixup to the object file. */
6446 md_apply_fix (fixP
, valueP
)
6453 assert (fixP
->fx_size
== 4 || fixP
->fx_r_type
== BFD_RELOC_16
);
6456 fixP
->fx_addnumber
= value
; /* Remember value for tc_gen_reloc */
6458 if (fixP
->fx_addsy
== NULL
&& ! fixP
->fx_pcrel
)
6461 switch (fixP
->fx_r_type
)
6463 case BFD_RELOC_MIPS_JMP
:
6464 case BFD_RELOC_HI16
:
6465 case BFD_RELOC_HI16_S
:
6466 case BFD_RELOC_MIPS_GPREL
:
6467 case BFD_RELOC_MIPS_LITERAL
:
6468 case BFD_RELOC_MIPS_CALL16
:
6469 case BFD_RELOC_MIPS_GOT16
:
6470 case BFD_RELOC_MIPS_GPREL32
:
6471 case BFD_RELOC_MIPS_GOT_HI16
:
6472 case BFD_RELOC_MIPS_GOT_LO16
:
6473 case BFD_RELOC_MIPS_CALL_HI16
:
6474 case BFD_RELOC_MIPS_CALL_LO16
:
6476 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
6477 "Invalid PC relative reloc");
6478 /* Nothing needed to do. The value comes from the reloc entry */
6481 case BFD_RELOC_PCREL_HI16_S
:
6482 /* The addend for this is tricky if it is internal, so we just
6483 do everything here rather than in bfd_perform_relocation. */
6484 if ((fixP
->fx_addsy
->bsym
->flags
& BSF_SECTION_SYM
) == 0)
6486 /* For an external symbol adjust by the address to make it
6487 pcrel_offset. We use the address of the RELLO reloc
6488 which follows this one. */
6489 value
+= (fixP
->fx_next
->fx_frag
->fr_address
6490 + fixP
->fx_next
->fx_where
);
6495 buf
= (unsigned char *) fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
6496 if (byte_order
== BIG_ENDIAN
)
6498 md_number_to_chars (buf
, value
, 2);
6501 case BFD_RELOC_PCREL_LO16
:
6502 /* The addend for this is tricky if it is internal, so we just
6503 do everything here rather than in bfd_perform_relocation. */
6504 if ((fixP
->fx_addsy
->bsym
->flags
& BSF_SECTION_SYM
) == 0)
6505 value
+= fixP
->fx_frag
->fr_address
+ fixP
->fx_where
;
6506 buf
= (unsigned char *) fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
6507 if (byte_order
== BIG_ENDIAN
)
6509 md_number_to_chars (buf
, value
, 2);
6513 /* If we are deleting this reloc entry, we must fill in the
6514 value now. This can happen if we have a .word which is not
6515 resolved when it appears but is later defined. We also need
6516 to fill in the value if this is an embedded PIC switch table
6519 || (mips_pic
== EMBEDDED_PIC
&& SWITCH_TABLE (fixP
)))
6520 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
,
6525 /* If we are deleting this reloc entry, we must fill in the
6527 assert (fixP
->fx_size
== 2);
6529 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
,
6533 case BFD_RELOC_LO16
:
6534 /* When handling an embedded PIC switch statement, we can wind
6535 up deleting a LO16 reloc. See the 'o' case in mips_ip. */
6538 if (value
< -0x8000 || value
> 0x7fff)
6539 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
6540 "relocation overflow");
6541 buf
= (unsigned char *) fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
6542 if (byte_order
== BIG_ENDIAN
)
6544 md_number_to_chars (buf
, value
, 2);
6548 case BFD_RELOC_16_PCREL_S2
:
6550 * We need to save the bits in the instruction since fixup_segment()
6551 * might be deleting the relocation entry (i.e., a branch within
6552 * the current segment).
6555 as_warn_where (fixP
->fx_file
, fixP
->fx_line
,
6556 "Branch to odd address (%lx)", value
);
6559 /* update old instruction data */
6560 buf
= (unsigned char *) (fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
);
6564 insn
= (buf
[3] << 24) | (buf
[2] << 16) | (buf
[1] << 8) | buf
[0];
6568 insn
= (buf
[0] << 24) | (buf
[1] << 16) | (buf
[2] << 8) | buf
[3];
6576 if (value
>= -0x8000 && value
< 0x8000)
6577 insn
|= value
& 0xffff;
6580 /* The branch offset is too large. If this is an
6581 unconditional branch, and we are not generating PIC code,
6582 we can convert it to an absolute jump instruction. */
6583 if (mips_pic
== NO_PIC
6585 && fixP
->fx_frag
->fr_address
>= text_section
->vma
6586 && (fixP
->fx_frag
->fr_address
6587 < text_section
->vma
+ text_section
->_raw_size
)
6588 && ((insn
& 0xffff0000) == 0x10000000 /* beq $0,$0 */
6589 || (insn
& 0xffff0000) == 0x04010000 /* bgez $0 */
6590 || (insn
& 0xffff0000) == 0x04110000)) /* bgezal $0 */
6592 if ((insn
& 0xffff0000) == 0x04110000) /* bgezal $0 */
6593 insn
= 0x0c000000; /* jal */
6595 insn
= 0x08000000; /* j */
6596 fixP
->fx_r_type
= BFD_RELOC_MIPS_JMP
;
6598 fixP
->fx_addsy
= section_symbol (text_section
);
6599 fixP
->fx_addnumber
= (value
<< 2) + md_pcrel_from (fixP
);
6603 /* FIXME. It would be possible in principle to handle
6604 conditional branches which overflow. They could be
6605 transformed into a branch around a jump. This would
6606 require setting up variant frags for each different
6607 branch type. The native MIPS assembler attempts to
6608 handle these cases, but it appears to do it
6610 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
6611 "Relocation overflow");
6615 md_number_to_chars ((char *) buf
, (valueT
) insn
, 4);
6630 const struct mips_opcode
*p
;
6631 int treg
, sreg
, dreg
, shamt
;
6636 for (i
= 0; i
< NUMOPCODES
; ++i
)
6638 p
= &mips_opcodes
[i
];
6639 if (((oc
& p
->mask
) == p
->match
) && (p
->pinfo
!= INSN_MACRO
))
6641 printf ("%08lx %s\t", oc
, p
->name
);
6642 treg
= (oc
>> 16) & 0x1f;
6643 sreg
= (oc
>> 21) & 0x1f;
6644 dreg
= (oc
>> 11) & 0x1f;
6645 shamt
= (oc
>> 6) & 0x1f;
6647 for (args
= p
->args
;; ++args
)
6658 printf ("%c", *args
);
6662 assert (treg
== sreg
);
6663 printf ("$%d,$%d", treg
, sreg
);
6668 printf ("$%d", dreg
);
6673 printf ("$%d", treg
);
6677 printf ("0x%x", treg
);
6682 printf ("$%d", sreg
);
6686 printf ("0x%08lx", oc
& 0x1ffffff);
6698 printf ("$%d", shamt
);
6709 printf ("%08lx UNDEFINED\n", oc
);
6720 name
= input_line_pointer
;
6721 c
= get_symbol_end ();
6722 p
= (symbolS
*) symbol_find_or_make (name
);
6723 *input_line_pointer
= c
;
6727 /* Align the current frag to a given power of two. The MIPS assembler
6728 also automatically adjusts any preceding label. */
6731 mips_align (to
, fill
, label
)
6736 mips_emit_delays ();
6737 frag_align (to
, fill
);
6738 record_alignment (now_seg
, to
);
6741 assert (S_GET_SEGMENT (label
) == now_seg
);
6742 label
->sy_frag
= frag_now
;
6743 S_SET_VALUE (label
, (valueT
) frag_now_fix ());
6747 /* Align to a given power of two. .align 0 turns off the automatic
6748 alignment used by the data creating pseudo-ops. */
6755 register long temp_fill
;
6756 long max_alignment
= 15;
6760 o Note that the assembler pulls down any immediately preceeding label
6761 to the aligned address.
6762 o It's not documented but auto alignment is reinstated by
6763 a .align pseudo instruction.
6764 o Note also that after auto alignment is turned off the mips assembler
6765 issues an error on attempt to assemble an improperly aligned data item.
6770 temp
= get_absolute_expression ();
6771 if (temp
> max_alignment
)
6772 as_bad ("Alignment too large: %d. assumed.", temp
= max_alignment
);
6775 as_warn ("Alignment negative: 0 assumed.");
6778 if (*input_line_pointer
== ',')
6780 input_line_pointer
++;
6781 temp_fill
= get_absolute_expression ();
6788 mips_align (temp
, (int) temp_fill
, insn_label
);
6795 demand_empty_rest_of_line ();
6799 mips_flush_pending_output ()
6801 mips_emit_delays ();
6811 /* When generating embedded PIC code, we only use the .text, .lit8,
6812 .sdata and .sbss sections. We change the .data and .rdata
6813 pseudo-ops to use .sdata. */
6814 if (mips_pic
== EMBEDDED_PIC
6815 && (sec
== 'd' || sec
== 'r'))
6818 mips_emit_delays ();
6828 subseg_set (bss_section
, (subsegT
) get_absolute_expression ());
6829 demand_empty_rest_of_line ();
6833 if (USE_GLOBAL_POINTER_OPT
)
6835 seg
= subseg_new (RDATA_SECTION_NAME
,
6836 (subsegT
) get_absolute_expression ());
6837 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
6839 bfd_set_section_flags (stdoutput
, seg
,
6845 bfd_set_section_alignment (stdoutput
, seg
, 4);
6847 demand_empty_rest_of_line ();
6851 as_bad ("No read only data section in this object file format");
6852 demand_empty_rest_of_line ();
6858 if (USE_GLOBAL_POINTER_OPT
)
6860 seg
= subseg_new (".sdata", (subsegT
) get_absolute_expression ());
6861 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
6863 bfd_set_section_flags (stdoutput
, seg
,
6864 SEC_ALLOC
| SEC_LOAD
| SEC_RELOC
6866 bfd_set_section_alignment (stdoutput
, seg
, 4);
6868 demand_empty_rest_of_line ();
6873 as_bad ("Global pointers not supported; recompile -G 0");
6874 demand_empty_rest_of_line ();
6883 mips_enable_auto_align ()
6895 mips_emit_delays ();
6896 if (log_size
> 0 && auto_align
)
6897 mips_align (log_size
, 0, label
);
6899 cons (1 << log_size
);
6910 mips_emit_delays ();
6914 mips_align (3, 0, label
);
6916 mips_align (2, 0, label
);
6923 /* Handle .globl. We need to override it because on Irix 5 you are
6926 where foo is an undefined symbol, to mean that foo should be
6927 considered to be the address of a function. */
6938 name
= input_line_pointer
;
6939 c
= get_symbol_end ();
6940 symbolP
= symbol_find_or_make (name
);
6941 *input_line_pointer
= c
;
6944 /* On Irix 5, every global symbol that is not explicitly labelled as
6945 being a function is apparently labelled as being an object. */
6948 if (! is_end_of_line
[(unsigned char) *input_line_pointer
])
6953 secname
= input_line_pointer
;
6954 c
= get_symbol_end ();
6955 sec
= bfd_get_section_by_name (stdoutput
, secname
);
6957 as_bad ("%s: no such section", secname
);
6958 *input_line_pointer
= c
;
6960 if (sec
!= NULL
&& (sec
->flags
& SEC_CODE
) != 0)
6961 flag
= BSF_FUNCTION
;
6964 symbolP
->bsym
->flags
|= flag
;
6966 S_SET_EXTERNAL (symbolP
);
6967 demand_empty_rest_of_line ();
6977 opt
= input_line_pointer
;
6978 c
= get_symbol_end ();
6982 /* FIXME: What does this mean? */
6984 else if (strncmp (opt
, "pic", 3) == 0)
6992 mips_pic
= SVR4_PIC
;
6994 as_bad (".option pic%d not supported", i
);
6996 if (USE_GLOBAL_POINTER_OPT
&& mips_pic
== SVR4_PIC
)
6998 if (g_switch_seen
&& g_switch_value
!= 0)
6999 as_warn ("-G may not be used with SVR4 PIC code");
7001 bfd_set_gp_size (stdoutput
, 0);
7005 as_warn ("Unrecognized option \"%s\"", opt
);
7007 *input_line_pointer
= c
;
7008 demand_empty_rest_of_line ();
7015 char *name
= input_line_pointer
, ch
;
7017 while (!is_end_of_line
[(unsigned char) *input_line_pointer
])
7018 input_line_pointer
++;
7019 ch
= *input_line_pointer
;
7020 *input_line_pointer
= '\0';
7022 if (strcmp (name
, "reorder") == 0)
7026 prev_insn_unreordered
= 1;
7027 prev_prev_insn_unreordered
= 1;
7031 else if (strcmp (name
, "noreorder") == 0)
7033 mips_emit_delays ();
7035 mips_any_noreorder
= 1;
7037 else if (strcmp (name
, "at") == 0)
7041 else if (strcmp (name
, "noat") == 0)
7045 else if (strcmp (name
, "macro") == 0)
7047 mips_warn_about_macros
= 0;
7049 else if (strcmp (name
, "nomacro") == 0)
7051 if (mips_noreorder
== 0)
7052 as_bad ("`noreorder' must be set before `nomacro'");
7053 mips_warn_about_macros
= 1;
7055 else if (strcmp (name
, "move") == 0 || strcmp (name
, "novolatile") == 0)
7059 else if (strcmp (name
, "nomove") == 0 || strcmp (name
, "volatile") == 0)
7063 else if (strcmp (name
, "bopt") == 0)
7067 else if (strcmp (name
, "nobopt") == 0)
7071 else if (strncmp (name
, "mips", 4) == 0)
7075 /* Permit the user to change the ISA on the fly. Needless to
7076 say, misuse can cause serious problems. */
7077 isa
= atoi (name
+ 4);
7079 mips_isa
= file_mips_isa
;
7080 else if (isa
< 1 || isa
> 4)
7081 as_bad ("unknown ISA level");
7087 as_warn ("Tried to set unrecognized symbol: %s\n", name
);
7089 *input_line_pointer
= ch
;
7090 demand_empty_rest_of_line ();
7093 /* Handle the .abicalls pseudo-op. I believe this is equivalent to
7094 .option pic2. It means to generate SVR4 PIC calls. */
7100 mips_pic
= SVR4_PIC
;
7101 if (USE_GLOBAL_POINTER_OPT
)
7103 if (g_switch_seen
&& g_switch_value
!= 0)
7104 as_warn ("-G may not be used with SVR4 PIC code");
7107 bfd_set_gp_size (stdoutput
, 0);
7108 demand_empty_rest_of_line ();
7111 /* Handle the .cpload pseudo-op. This is used when generating SVR4
7112 PIC code. It sets the $gp register for the function based on the
7113 function address, which is in the register named in the argument.
7114 This uses a relocation against _gp_disp, which is handled specially
7115 by the linker. The result is:
7116 lui $gp,%hi(_gp_disp)
7117 addiu $gp,$gp,%lo(_gp_disp)
7118 addu $gp,$gp,.cpload argument
7119 The .cpload argument is normally $25 == $t9. */
7128 /* If we are not generating SVR4 PIC code, .cpload is ignored. */
7129 if (mips_pic
!= SVR4_PIC
)
7135 /* .cpload should be a in .set noreorder section. */
7136 if (mips_noreorder
== 0)
7137 as_warn (".cpload not in noreorder section");
7140 ex
.X_add_symbol
= symbol_find_or_make ("_gp_disp");
7141 ex
.X_op_symbol
= NULL
;
7142 ex
.X_add_number
= 0;
7144 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
7145 ex
.X_add_symbol
->bsym
->flags
|= BSF_OBJECT
;
7147 macro_build_lui ((char *) NULL
, &icnt
, &ex
, GP
);
7148 macro_build ((char *) NULL
, &icnt
, &ex
, "addiu", "t,r,j", GP
, GP
,
7149 (int) BFD_RELOC_LO16
);
7151 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "addu", "d,v,t",
7152 GP
, GP
, tc_get_register (0));
7154 demand_empty_rest_of_line ();
7157 /* Handle the .cprestore pseudo-op. This stores $gp into a given
7158 offset from $sp. The offset is remembered, and after making a PIC
7159 call $gp is restored from that location. */
7162 s_cprestore (ignore
)
7168 /* If we are not generating SVR4 PIC code, .cprestore is ignored. */
7169 if (mips_pic
!= SVR4_PIC
)
7175 mips_cprestore_offset
= get_absolute_expression ();
7177 ex
.X_op
= O_constant
;
7178 ex
.X_add_symbol
= NULL
;
7179 ex
.X_op_symbol
= NULL
;
7180 ex
.X_add_number
= mips_cprestore_offset
;
7182 macro_build ((char *) NULL
, &icnt
, &ex
,
7183 mips_isa
< 3 ? "sw" : "sd",
7184 "t,o(b)", GP
, (int) BFD_RELOC_LO16
, SP
);
7186 demand_empty_rest_of_line ();
7189 /* Handle the .gpword pseudo-op. This is used when generating PIC
7190 code. It generates a 32 bit GP relative reloc. */
7200 /* When not generating PIC code, this is treated as .word. */
7201 if (mips_pic
!= SVR4_PIC
)
7208 mips_emit_delays ();
7210 mips_align (2, 0, label
);
7215 if (ex
.X_op
!= O_symbol
|| ex
.X_add_number
!= 0)
7217 as_bad ("Unsupported use of .gpword");
7218 ignore_rest_of_line ();
7222 md_number_to_chars (p
, (valueT
) 0, 4);
7223 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 4, &ex
, 0,
7224 BFD_RELOC_MIPS_GPREL32
);
7226 demand_empty_rest_of_line ();
7229 /* Handle the .cpadd pseudo-op. This is used when dealing with switch
7230 tables in SVR4 PIC code. */
7239 /* This is ignored when not generating SVR4 PIC code. */
7240 if (mips_pic
!= SVR4_PIC
)
7246 /* Add $gp to the register named as an argument. */
7247 reg
= tc_get_register (0);
7248 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
7249 mips_isa
< 3 ? "addu" : "daddu",
7250 "d,v,t", reg
, reg
, GP
);
7252 demand_empty_rest_of_line ();
7255 /* Parse a register string into a number. Called from the ECOFF code
7256 to parse .frame. The argument is non-zero if this is the frame
7257 register, so that we can record it in mips_frame_reg. */
7260 tc_get_register (frame
)
7266 if (*input_line_pointer
++ != '$')
7268 as_warn ("expected `$'");
7271 else if (isdigit ((unsigned char) *input_line_pointer
))
7273 reg
= get_absolute_expression ();
7274 if (reg
< 0 || reg
>= 32)
7276 as_warn ("Bad register number");
7282 if (strncmp (input_line_pointer
, "fp", 2) == 0)
7284 else if (strncmp (input_line_pointer
, "sp", 2) == 0)
7286 else if (strncmp (input_line_pointer
, "gp", 2) == 0)
7288 else if (strncmp (input_line_pointer
, "at", 2) == 0)
7292 as_warn ("Unrecognized register name");
7295 input_line_pointer
+= 2;
7298 mips_frame_reg
= reg
!= 0 ? reg
: SP
;
7303 md_section_align (seg
, addr
)
7307 int align
= bfd_get_section_alignment (stdoutput
, seg
);
7309 return ((addr
+ (1 << align
) - 1) & (-1 << align
));
7312 /* Utility routine, called from above as well. If called while the
7313 input file is still being read, it's only an approximation. (For
7314 example, a symbol may later become defined which appeared to be
7315 undefined earlier.) */
7318 nopic_need_relax (sym
)
7324 if (USE_GLOBAL_POINTER_OPT
)
7326 const char *symname
;
7329 /* Find out whether this symbol can be referenced off the GP
7330 register. It can be if it is smaller than the -G size or if
7331 it is in the .sdata or .sbss section. Certain symbols can
7332 not be referenced off the GP, although it appears as though
7334 symname
= S_GET_NAME (sym
);
7335 if (symname
!= (const char *) NULL
7336 && (strcmp (symname
, "eprol") == 0
7337 || strcmp (symname
, "etext") == 0
7338 || strcmp (symname
, "_gp") == 0
7339 || strcmp (symname
, "edata") == 0
7340 || strcmp (symname
, "_fbss") == 0
7341 || strcmp (symname
, "_fdata") == 0
7342 || strcmp (symname
, "_ftext") == 0
7343 || strcmp (symname
, "end") == 0
7344 || strcmp (symname
, "_gp_disp") == 0))
7346 else if (! S_IS_DEFINED (sym
)
7348 #ifndef NO_ECOFF_DEBUGGING
7349 || (sym
->ecoff_extern_size
!= 0
7350 && sym
->ecoff_extern_size
<= g_switch_value
)
7352 || (S_GET_VALUE (sym
) != 0
7353 && S_GET_VALUE (sym
) <= g_switch_value
)))
7357 const char *segname
;
7359 segname
= segment_name (S_GET_SEGMENT (sym
));
7360 assert (strcmp (segname
, ".lit8") != 0
7361 && strcmp (segname
, ".lit4") != 0);
7362 change
= (strcmp (segname
, ".sdata") != 0
7363 && strcmp (segname
, ".sbss") != 0);
7368 /* We are not optimizing for the GP register. */
7372 /* Estimate the size of a frag before relaxing. We are not really
7373 relaxing here, and the final size is encoded in the subtype
7378 md_estimate_size_before_relax (fragp
, segtype
)
7384 if (mips_pic
== NO_PIC
)
7386 change
= nopic_need_relax (fragp
->fr_symbol
);
7388 else if (mips_pic
== SVR4_PIC
)
7390 asection
*symsec
= fragp
->fr_symbol
->bsym
->section
;
7392 /* This must duplicate the test in adjust_reloc_syms. */
7393 change
= (symsec
!= &bfd_und_section
7394 && symsec
!= &bfd_abs_section
7395 && ! bfd_is_com_section (symsec
));
7402 /* Record the offset to the first reloc in the fr_opcode field.
7403 This lets md_convert_frag and tc_gen_reloc know that the code
7404 must be expanded. */
7405 fragp
->fr_opcode
= (fragp
->fr_literal
7407 - RELAX_OLD (fragp
->fr_subtype
)
7408 + RELAX_RELOC1 (fragp
->fr_subtype
));
7409 /* FIXME: This really needs as_warn_where. */
7410 if (RELAX_WARN (fragp
->fr_subtype
))
7411 as_warn ("AT used after \".set noat\" or macro used after \".set nomacro\"");
7417 return RELAX_NEW (fragp
->fr_subtype
) - RELAX_OLD (fragp
->fr_subtype
);
7420 /* Translate internal representation of relocation info to BFD target
7424 tc_gen_reloc (section
, fixp
)
7428 static arelent
*retval
[4];
7431 reloc
= retval
[0] = (arelent
*) xmalloc (sizeof (arelent
));
7434 reloc
->sym_ptr_ptr
= &fixp
->fx_addsy
->bsym
;
7435 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
7437 if (mips_pic
== EMBEDDED_PIC
7438 && SWITCH_TABLE (fixp
))
7440 /* For a switch table entry we use a special reloc. The addend
7441 is actually the difference between the reloc address and the
7443 reloc
->addend
= reloc
->address
- S_GET_VALUE (fixp
->fx_subsy
);
7444 if (OUTPUT_FLAVOR
!= bfd_target_ecoff_flavour
)
7445 as_fatal ("Double check fx_r_type in tc-mips.c:tc_gen_reloc");
7446 fixp
->fx_r_type
= BFD_RELOC_GPREL32
;
7448 else if (fixp
->fx_r_type
== BFD_RELOC_PCREL_LO16
)
7450 /* We use a special addend for an internal RELLO reloc. */
7451 if (fixp
->fx_addsy
->bsym
->flags
& BSF_SECTION_SYM
)
7452 reloc
->addend
= reloc
->address
- S_GET_VALUE (fixp
->fx_subsy
);
7454 reloc
->addend
= fixp
->fx_addnumber
+ reloc
->address
;
7456 else if (fixp
->fx_r_type
== BFD_RELOC_PCREL_HI16_S
)
7458 assert (fixp
->fx_next
!= NULL
7459 && fixp
->fx_next
->fx_r_type
== BFD_RELOC_PCREL_LO16
);
7460 /* We use a special addend for an internal RELHI reloc. The
7461 reloc is relative to the RELLO; adjust the addend
7463 if (fixp
->fx_addsy
->bsym
->flags
& BSF_SECTION_SYM
)
7464 reloc
->addend
= (fixp
->fx_next
->fx_frag
->fr_address
7465 + fixp
->fx_next
->fx_where
7466 - S_GET_VALUE (fixp
->fx_subsy
));
7468 reloc
->addend
= (fixp
->fx_addnumber
7469 + fixp
->fx_next
->fx_frag
->fr_address
7470 + fixp
->fx_next
->fx_where
);
7472 else if (fixp
->fx_pcrel
== 0)
7473 reloc
->addend
= fixp
->fx_addnumber
;
7476 if (OUTPUT_FLAVOR
!= bfd_target_aout_flavour
)
7477 /* A gruesome hack which is a result of the gruesome gas reloc
7479 reloc
->addend
= reloc
->address
;
7481 reloc
->addend
= -reloc
->address
;
7484 /* If this is a variant frag, we may need to adjust the existing
7485 reloc and generate a new one. */
7486 if (fixp
->fx_frag
->fr_opcode
!= NULL
7487 && (fixp
->fx_r_type
== BFD_RELOC_MIPS_GPREL
7488 || fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT16
7489 || fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL16
7490 || fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT_HI16
7491 || fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT_LO16
7492 || fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL_HI16
7493 || fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL_LO16
))
7497 /* If this is not the last reloc in this frag, then we have two
7498 GPREL relocs, or a GOT_HI16/GOT_LO16 pair, or a
7499 CALL_HI16/CALL_LO16, both of which are being replaced. Let
7500 the second one handle all of them. */
7501 if (fixp
->fx_next
!= NULL
7502 && fixp
->fx_frag
== fixp
->fx_next
->fx_frag
)
7504 assert ((fixp
->fx_r_type
== BFD_RELOC_MIPS_GPREL
7505 && fixp
->fx_next
->fx_r_type
== BFD_RELOC_MIPS_GPREL
)
7506 || (fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT_HI16
7507 && (fixp
->fx_next
->fx_r_type
7508 == BFD_RELOC_MIPS_GOT_LO16
))
7509 || (fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL_HI16
7510 && (fixp
->fx_next
->fx_r_type
7511 == BFD_RELOC_MIPS_CALL_LO16
)));
7516 fixp
->fx_where
= fixp
->fx_frag
->fr_opcode
- fixp
->fx_frag
->fr_literal
;
7517 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
7518 reloc2
= retval
[1] = (arelent
*) xmalloc (sizeof (arelent
));
7520 reloc2
->sym_ptr_ptr
= &fixp
->fx_addsy
->bsym
;
7521 reloc2
->address
= (reloc
->address
7522 + (RELAX_RELOC2 (fixp
->fx_frag
->fr_subtype
)
7523 - RELAX_RELOC1 (fixp
->fx_frag
->fr_subtype
)));
7524 reloc2
->addend
= fixp
->fx_addnumber
;
7525 reloc2
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_LO16
);
7526 assert (reloc2
->howto
!= NULL
);
7528 if (RELAX_RELOC3 (fixp
->fx_frag
->fr_subtype
))
7532 reloc3
= retval
[2] = (arelent
*) xmalloc (sizeof (arelent
));
7535 reloc3
->address
+= 4;
7538 if (mips_pic
== NO_PIC
)
7540 assert (fixp
->fx_r_type
== BFD_RELOC_MIPS_GPREL
);
7541 fixp
->fx_r_type
= BFD_RELOC_HI16_S
;
7543 else if (mips_pic
== SVR4_PIC
)
7545 switch (fixp
->fx_r_type
)
7549 case BFD_RELOC_MIPS_GOT16
:
7551 case BFD_RELOC_MIPS_CALL16
:
7552 case BFD_RELOC_MIPS_GOT_LO16
:
7553 case BFD_RELOC_MIPS_CALL_LO16
:
7554 fixp
->fx_r_type
= BFD_RELOC_MIPS_GOT16
;
7562 /* To support a PC relative reloc when generating embedded PIC code
7563 for ECOFF, we use a Cygnus extension. We check for that here to
7564 make sure that we don't let such a reloc escape normally. */
7565 if (OUTPUT_FLAVOR
== bfd_target_ecoff_flavour
7566 && fixp
->fx_r_type
== BFD_RELOC_16_PCREL_S2
7567 && mips_pic
!= EMBEDDED_PIC
)
7568 reloc
->howto
= NULL
;
7570 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, fixp
->fx_r_type
);
7572 if (reloc
->howto
== NULL
)
7574 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
7575 "Can not represent relocation in this object file format");
7582 /* Convert a machine dependent frag. */
7585 md_convert_frag (abfd
, asec
, fragp
)
7593 if (fragp
->fr_opcode
== NULL
)
7596 old
= RELAX_OLD (fragp
->fr_subtype
);
7597 new = RELAX_NEW (fragp
->fr_subtype
);
7598 fixptr
= fragp
->fr_literal
+ fragp
->fr_fix
;
7601 memcpy (fixptr
- old
, fixptr
, new);
7603 fragp
->fr_fix
+= new - old
;
7606 /* This function is called whenever a label is defined. It is used
7607 when handling branch delays; if a branch has a label, we assume we
7611 mips_define_label (sym
)
7617 /* Decide whether a label is local. This is called by LOCAL_LABEL.
7618 In order to work with gcc when using mips-tfile, we must keep all
7619 local labels. However, in other cases, we want to discard them,
7620 since they are useless. */
7623 mips_local_label (name
)
7626 #ifndef NO_ECOFF_DEBUGGING
7629 && ! ecoff_debugging_seen
)
7631 /* We were called with -g, but we didn't see any debugging
7632 information. That may mean that gcc is smuggling debugging
7633 information through to mips-tfile, in which case we must
7634 generate all local labels. */
7639 /* Here it's OK to discard local labels. */
7641 return name
[0] == '$';
7644 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7646 /* Some special processing for a MIPS ELF file. */
7649 mips_elf_final_processing ()
7653 /* Write out the .reginfo section. */
7654 s
.ri_gprmask
= mips_gprmask
;
7655 s
.ri_cprmask
[0] = mips_cprmask
[0];
7656 s
.ri_cprmask
[1] = mips_cprmask
[1];
7657 s
.ri_cprmask
[2] = mips_cprmask
[2];
7658 s
.ri_cprmask
[3] = mips_cprmask
[3];
7659 /* The gp_value field is set by the MIPS ELF backend. */
7661 bfd_mips_elf32_swap_reginfo_out (stdoutput
, &s
,
7662 ((Elf32_External_RegInfo
*)
7663 mips_regmask_frag
));
7665 /* Set the MIPS ELF flag bits. FIXME: There should probably be some
7666 sort of BFD interface for this. */
7667 if (mips_any_noreorder
)
7668 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_NOREORDER
;
7669 if (mips_pic
!= NO_PIC
)
7670 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_PIC
;
7673 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */
7675 /* These functions should really be defined by the object file format,
7676 since they are related to debugging information. However, this
7677 code has to work for the a.out format, which does not define them,
7678 so we provide simple versions here. These don't actually generate
7679 any debugging information, but they do simple checking and someday
7680 somebody may make them useful. */
7684 struct loc
*loc_next
;
7685 unsigned long loc_fileno
;
7686 unsigned long loc_lineno
;
7687 unsigned long loc_offset
;
7688 unsigned short loc_delta
;
7689 unsigned short loc_count
;
7698 struct proc
*proc_next
;
7699 struct symbol
*proc_isym
;
7700 struct symbol
*proc_end
;
7701 unsigned long proc_reg_mask
;
7702 unsigned long proc_reg_offset
;
7703 unsigned long proc_fpreg_mask
;
7704 unsigned long proc_fpreg_offset
;
7705 unsigned long proc_frameoffset
;
7706 unsigned long proc_framereg
;
7707 unsigned long proc_pcreg
;
7709 struct file
*proc_file
;
7716 struct file
*file_next
;
7717 unsigned long file_fileno
;
7718 struct symbol
*file_symbol
;
7719 struct symbol
*file_end
;
7720 struct proc
*file_proc
;
7725 static struct obstack proc_frags
;
7726 static procS
*proc_lastP
;
7727 static procS
*proc_rootP
;
7728 static int numprocs
;
7733 obstack_begin (&proc_frags
, 0x2000);
7739 /* check for premature end, nesting errors, etc */
7740 if (proc_lastP
&& proc_lastP
->proc_end
== NULL
)
7741 as_warn ("missing `.end' at end of assembly");
7750 if (*input_line_pointer
== '-')
7752 ++input_line_pointer
;
7755 if (!isdigit (*input_line_pointer
))
7756 as_bad ("Expected simple number.");
7757 if (input_line_pointer
[0] == '0')
7759 if (input_line_pointer
[1] == 'x')
7761 input_line_pointer
+= 2;
7762 while (isxdigit (*input_line_pointer
))
7765 val
|= hex_value (*input_line_pointer
++);
7767 return negative
? -val
: val
;
7771 ++input_line_pointer
;
7772 while (isdigit (*input_line_pointer
))
7775 val
|= *input_line_pointer
++ - '0';
7777 return negative
? -val
: val
;
7780 if (!isdigit (*input_line_pointer
))
7782 printf (" *input_line_pointer == '%c' 0x%02x\n",
7783 *input_line_pointer
, *input_line_pointer
);
7784 as_warn ("Invalid number");
7787 while (isdigit (*input_line_pointer
))
7790 val
+= *input_line_pointer
++ - '0';
7792 return negative
? -val
: val
;
7795 /* The .file directive; just like the usual .file directive, but there
7796 is an initial number which is the ECOFF file index. */
7804 line
= get_number ();
7809 /* The .end directive. */
7817 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
7820 demand_empty_rest_of_line ();
7824 if (now_seg
!= text_section
)
7825 as_warn (".end not in text section");
7828 as_warn (".end and no .ent seen yet.");
7834 assert (S_GET_NAME (p
));
7835 if (strcmp (S_GET_NAME (p
), S_GET_NAME (proc_lastP
->proc_isym
)))
7836 as_warn (".end symbol does not match .ent symbol.");
7839 proc_lastP
->proc_end
= (symbolS
*) 1;
7842 /* The .aent and .ent directives. */
7852 symbolP
= get_symbol ();
7853 if (*input_line_pointer
== ',')
7854 input_line_pointer
++;
7856 if (isdigit (*input_line_pointer
) || *input_line_pointer
== '-')
7857 number
= get_number ();
7858 if (now_seg
!= text_section
)
7859 as_warn (".ent or .aent not in text section.");
7861 if (!aent
&& proc_lastP
&& proc_lastP
->proc_end
== NULL
)
7862 as_warn ("missing `.end'");
7866 procP
= (procS
*) obstack_alloc (&proc_frags
, sizeof (*procP
));
7867 procP
->proc_isym
= symbolP
;
7868 procP
->proc_reg_mask
= 0;
7869 procP
->proc_reg_offset
= 0;
7870 procP
->proc_fpreg_mask
= 0;
7871 procP
->proc_fpreg_offset
= 0;
7872 procP
->proc_frameoffset
= 0;
7873 procP
->proc_framereg
= 0;
7874 procP
->proc_pcreg
= 0;
7875 procP
->proc_end
= NULL
;
7876 procP
->proc_next
= NULL
;
7878 proc_lastP
->proc_next
= procP
;
7884 demand_empty_rest_of_line ();
7887 /* The .frame directive. */
7900 frame_reg
= tc_get_register (1);
7901 if (*input_line_pointer
== ',')
7902 input_line_pointer
++;
7903 frame_off
= get_absolute_expression ();
7904 if (*input_line_pointer
== ',')
7905 input_line_pointer
++;
7906 pcreg
= tc_get_register (0);
7909 assert (proc_rootP
);
7910 proc_rootP
->proc_framereg
= frame_reg
;
7911 proc_rootP
->proc_frameoffset
= frame_off
;
7912 proc_rootP
->proc_pcreg
= pcreg
;
7913 /* bob macho .frame */
7915 /* We don't have to write out a frame stab for unoptimized code. */
7916 if (!(frame_reg
== FP
&& frame_off
== 0))
7919 as_warn ("No .ent for .frame to use.");
7920 (void) sprintf (str
, "R%d;%d", frame_reg
, frame_off
);
7921 symP
= symbol_new (str
, N_VFP
, 0, frag_now
);
7922 S_SET_TYPE (symP
, N_RMASK
);
7923 S_SET_OTHER (symP
, 0);
7924 S_SET_DESC (symP
, 0);
7925 symP
->sy_forward
= proc_lastP
->proc_isym
;
7926 /* bob perhaps I should have used pseudo set */
7928 demand_empty_rest_of_line ();
7932 /* The .fmask and .mask directives. */
7939 char str
[100], *strP
;
7945 mask
= get_number ();
7946 if (*input_line_pointer
== ',')
7947 input_line_pointer
++;
7948 off
= get_absolute_expression ();
7950 /* bob only for coff */
7951 assert (proc_rootP
);
7952 if (reg_type
== 'F')
7954 proc_rootP
->proc_fpreg_mask
= mask
;
7955 proc_rootP
->proc_fpreg_offset
= off
;
7959 proc_rootP
->proc_reg_mask
= mask
;
7960 proc_rootP
->proc_reg_offset
= off
;
7963 /* bob macho .mask + .fmask */
7965 /* We don't have to write out a mask stab if no saved regs. */
7969 as_warn ("No .ent for .mask to use.");
7971 for (i
= 0; i
< 32; i
++)
7975 sprintf (strP
, "%c%d,", reg_type
, i
);
7976 strP
+= strlen (strP
);
7980 sprintf (strP
, ";%d,", off
);
7981 symP
= symbol_new (str
, N_RMASK
, 0, frag_now
);
7982 S_SET_TYPE (symP
, N_RMASK
);
7983 S_SET_OTHER (symP
, 0);
7984 S_SET_DESC (symP
, 0);
7985 symP
->sy_forward
= proc_lastP
->proc_isym
;
7986 /* bob perhaps I should have used pseudo set */
7991 /* The .loc directive. */
8002 assert (now_seg
== text_section
);
8004 lineno
= get_number ();
8005 addroff
= frag_now_fix ();
8007 symbolP
= symbol_new ("", N_SLINE
, addroff
, frag_now
);
8008 S_SET_TYPE (symbolP
, N_SLINE
);
8009 S_SET_OTHER (symbolP
, 0);
8010 S_SET_DESC (symbolP
, lineno
);
8011 symbolP
->sy_segment
= now_seg
;