1 /* tc-mips.c -- assemble code for a MIPS chip.
2 Copyright (C) 1993 Free Software Foundation, Inc.
3 Contributed by the OSF and Ralph Campbell.
4 Written by Keith Knowles and Ralph Campbell, working independently.
5 Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus
8 This file is part of GAS.
10 GAS is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 2, or (at your option)
15 GAS is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with GAS; see the file COPYING. If not, write to
22 the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */
41 #endif /* NO_VARARGS */
42 #endif /* NO_STDARG */
44 #include "opcode/mips.h"
49 static char *mips_regmask_frag
;
53 #define PIC_CALL_REG 25
59 /* Decide whether to do GP reference optimizations based on the object
69 /* The default target format to use. */
71 #ifdef TARGET_BYTES_BIG_ENDIAN
72 #define DEFAULT_TARGET_FORMAT "a.out-mips-big"
74 #define DEFAULT_TARGET_FORMAT "a.out-mips-little"
78 #ifdef TARGET_BYTES_BIG_ENDIAN
79 #define DEFAULT_TARGET_FORMAT "ecoff-bigmips"
81 #define DEFAULT_TARGET_FORMAT "ecoff-littlemips"
83 #endif /* OBJ_ECOFF */
85 #ifdef TARGET_BYTES_BIG_ENDIAN
86 #define DEFAULT_TARGET_FORMAT "elf32-bigmips"
88 #define DEFAULT_TARGET_FORMAT "elf32-littlemips"
92 const char *mips_target_format
= DEFAULT_TARGET_FORMAT
;
94 /* The name of the readonly data section. */
96 #define RDATA_SECTION_NAME ".data"
99 #define RDATA_SECTION_NAME ".rdata"
102 #define RDATA_SECTION_NAME ".rodata"
105 /* These variables are filled in with the masks of registers used.
106 The object format code reads them and puts them in the appropriate
108 unsigned long mips_gprmask
;
109 unsigned long mips_cprmask
[4];
111 /* MIPS ISA (Instruction Set Architecture) level (may be changed
112 temporarily using .set mipsN). */
113 static int mips_isa
= -1;
115 /* MIPS ISA we are using for this output file. */
116 static int file_mips_isa
;
118 /* The CPU type as a number: 2000, 3000, 4000, 4400, etc. */
121 /* MIPS PIC level. */
125 /* Do not generate PIC code. */
128 /* Generate PIC code as in Irix 4. This is not implemented, and I'm
129 not sure what it is supposed to do. */
132 /* Generate PIC code as in the SVR4 MIPS ABI. */
135 /* Generate PIC code without using a global offset table: the data
136 segment has a maximum size of 64K, all data references are off
137 the $gp register, and all text references are PC relative. This
138 is used on some embedded systems. */
142 static enum mips_pic_level mips_pic
;
144 /* 1 if trap instructions should used for overflow rather than break
146 static int mips_trap
;
148 static int mips_warn_about_macros
;
149 static int mips_noreorder
;
150 static int mips_any_noreorder
;
151 static int mips_nomove
;
152 static int mips_noat
;
153 static int mips_nobopt
;
156 /* The size of the small data section. */
157 static int g_switch_value
= 8;
158 /* Whether the -G option was used. */
159 static int g_switch_seen
= 0;
165 /* handle of the OPCODE hash table */
166 static struct hash_control
*op_hash
= NULL
;
168 /* This array holds the chars that always start a comment. If the
169 pre-processor is disabled, these aren't very useful */
170 const char comment_chars
[] = "#";
172 /* This array holds the chars that only start a comment at the beginning of
173 a line. If the line seems to have the form '# 123 filename'
174 .line and .file directives will appear in the pre-processed output */
175 /* Note that input_file.c hand checks for '#' at the beginning of the
176 first line of the input file. This is because the compiler outputs
177 #NO_APP at the beginning of its output. */
178 /* Also note that C style comments are always supported. */
179 const char line_comment_chars
[] = "#";
181 /* This array holds machine specific line separator characters. */
182 const char line_separator_chars
[] = "";
184 /* Chars that can be used to separate mant from exp in floating point nums */
185 const char EXP_CHARS
[] = "eE";
187 /* Chars that mean this number is a floating point constant */
190 const char FLT_CHARS
[] = "rRsSfFdDxXpP";
192 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
193 changed in read.c . Ideally it shouldn't have to know about it at all,
194 but nothing is ideal around here.
197 static char *insn_error
;
199 static int byte_order
= BYTE_ORDER
;
201 static int auto_align
= 1;
203 /* Symbol labelling the current insn. */
204 static symbolS
*insn_label
;
206 /* When outputting SVR4 PIC code, the assembler needs to know the
207 offset in the stack frame from which to restore the $gp register.
208 This is set by the .cprestore pseudo-op, and saved in this
210 static offsetT mips_cprestore_offset
= -1;
212 /* This is the register which holds the stack frame, as set by the
213 .frame pseudo-op. This is needed to implement .cprestore. */
214 static int mips_frame_reg
= SP
;
216 /* To output NOP instructions correctly, we need to keep information
217 about the previous two instructions. */
219 /* Whether we are optimizing. The default value of 2 means to remove
220 unneeded NOPs and swap branch instructions when possible. A value
221 of 1 means to not swap branches. A value of 0 means to always
223 static int mips_optimize
= 2;
225 /* The previous instruction. */
226 static struct mips_cl_insn prev_insn
;
228 /* The instruction before prev_insn. */
229 static struct mips_cl_insn prev_prev_insn
;
231 /* If we don't want information for prev_insn or prev_prev_insn, we
232 point the insn_mo field at this dummy integer. */
233 static const struct mips_opcode dummy_opcode
= { 0 };
235 /* Non-zero if prev_insn is valid. */
236 static int prev_insn_valid
;
238 /* The frag for the previous instruction. */
239 static struct frag
*prev_insn_frag
;
241 /* The offset into prev_insn_frag for the previous instruction. */
242 static long prev_insn_where
;
244 /* The reloc for the previous instruction, if any. */
245 static fixS
*prev_insn_fixp
;
247 /* Non-zero if the previous instruction was in a delay slot. */
248 static int prev_insn_is_delay_slot
;
250 /* Non-zero if the previous instruction was in a .set noreorder. */
251 static int prev_insn_unreordered
;
253 /* Non-zero if the previous previous instruction was in a .set
255 static int prev_prev_insn_unreordered
;
257 /* Since the MIPS does not have multiple forms of PC relative
258 instructions, we do not have to do relaxing as is done on other
259 platforms. However, we do have to handle GP relative addressing
260 correctly, which turns out to be a similar problem.
262 Every macro that refers to a symbol can occur in (at least) two
263 forms, one with GP relative addressing and one without. For
264 example, loading a global variable into a register generally uses
265 a macro instruction like this:
267 If i can be addressed off the GP register (this is true if it is in
268 the .sbss or .sdata section, or if it is known to be smaller than
269 the -G argument) this will generate the following instruction:
271 This instruction will use a GPREL reloc. If i can not be addressed
272 off the GP register, the following instruction sequence will be used:
275 In this case the first instruction will have a HI16 reloc, and the
276 second reloc will have a LO16 reloc. Both relocs will be against
279 The issue here is that we may not know whether i is GP addressable
280 until after we see the instruction that uses it. Therefore, we
281 want to be able to choose the final instruction sequence only at
282 the end of the assembly. This is similar to the way other
283 platforms choose the size of a PC relative instruction only at the
286 When generating position independent code we do not use GP
287 addressing in quite the same way, but the issue still arises as
288 external symbols and local symbols must be handled differently.
290 We handle these issues by actually generating both possible
291 instruction sequences. The longer one is put in a frag_var with
292 type rs_machine_dependent. We encode what to do with the frag in
293 the subtype field. We encode (1) the number of existing bytes to
294 replace, (2) the number of new bytes to use, (3) the offset from
295 the start of the existing bytes to the first reloc we must generate
296 (that is, the offset is applied from the start of the existing
297 bytes after they are replaced by the new bytes, if any), (4) the
298 offset from the start of the existing bytes to the second reloc,
299 (5) whether a third reloc is needed (the third reloc is always four
300 bytes after the second reloc), and (6) whether to warn if this
301 variant is used (this is sometimes needed if .set nomacro or .set
302 noat is in effect). All these numbers are reasonably small.
304 Generating two instruction sequences must be handled carefully to
305 ensure that delay slots are handled correctly. Fortunately, there
306 are a limited number of cases. When the second instruction
307 sequence is generated, append_insn is directed to maintain the
308 existing delay slot information, so it continues to apply to any
309 code after the second instruction sequence. This means that the
310 second instruction sequence must not impose any requirements not
311 required by the first instruction sequence.
313 These variant frags are then handled in functions called by the
314 machine independent code. md_estimate_size_before_relax returns
315 the final size of the frag. md_convert_frag sets up the final form
316 of the frag. tc_gen_reloc adjust the first reloc and adds a second
318 #define RELAX_ENCODE(old, new, reloc1, reloc2, reloc3, warn) \
322 | (((reloc1) + 64) << 9) \
323 | (((reloc2) + 64) << 2) \
324 | ((reloc3) ? (1 << 1) : 0) \
326 #define RELAX_OLD(i) (((i) >> 24) & 0xff)
327 #define RELAX_NEW(i) (((i) >> 16) & 0xff)
328 #define RELAX_RELOC1(i) ((((i) >> 9) & 0x7f) - 64)
329 #define RELAX_RELOC2(i) ((((i) >> 2) & 0x7f) - 64)
330 #define RELAX_RELOC3(i) (((i) >> 1) & 1)
331 #define RELAX_WARN(i) ((i) & 1)
333 /* Prototypes for static functions. */
336 #define internalError() \
337 as_fatal ("internal Error, line %d, %s", __LINE__, __FILE__)
339 #define internalError() as_fatal ("MIPS internal Error");
342 static int insn_uses_reg
PARAMS ((struct mips_cl_insn
*ip
,
343 unsigned int reg
, int fpr
));
344 static void append_insn
PARAMS ((char *place
,
345 struct mips_cl_insn
* ip
,
347 bfd_reloc_code_real_type r
));
348 static void mips_no_prev_insn
PARAMS ((void));
349 static void mips_emit_delays
PARAMS ((void));
350 static void macro_build
PARAMS ((char *place
, int *counter
, expressionS
* ep
,
351 const char *name
, const char *fmt
,
353 static void macro_build_lui
PARAMS ((char *place
, int *counter
,
354 expressionS
* ep
, int regnum
));
355 static void set_at
PARAMS ((int *counter
, int reg
, int unsignedp
));
356 static void check_absolute_expr
PARAMS ((struct mips_cl_insn
* ip
,
358 static void load_register
PARAMS ((int *counter
, int reg
, expressionS
* ep
));
359 static void load_address
PARAMS ((int *counter
, int reg
, expressionS
*ep
));
360 static void macro
PARAMS ((struct mips_cl_insn
* ip
));
361 #ifdef LOSING_COMPILER
362 static void macro2
PARAMS ((struct mips_cl_insn
* ip
));
364 static void mips_ip
PARAMS ((char *str
, struct mips_cl_insn
* ip
));
365 static int my_getSmallExpression
PARAMS ((expressionS
* ep
, char *str
));
366 static void my_getExpression
PARAMS ((expressionS
* ep
, char *str
));
367 static symbolS
*get_symbol
PARAMS ((void));
368 static void mips_align
PARAMS ((int to
, int fill
, symbolS
*label
));
369 static void s_align
PARAMS ((int));
370 static void s_stringer
PARAMS ((int));
371 static void s_change_sec
PARAMS ((int));
372 static void s_cons
PARAMS ((int));
373 static void s_err
PARAMS ((int));
374 static void s_extern
PARAMS ((int));
375 static void s_float_cons
PARAMS ((int));
376 static void s_mips_globl
PARAMS ((int));
377 static void s_option
PARAMS ((int));
378 static void s_mipsset
PARAMS ((int));
379 static void s_mips_space
PARAMS ((int));
380 static void s_abicalls
PARAMS ((int));
381 static void s_cpload
PARAMS ((int));
382 static void s_cprestore
PARAMS ((int));
383 static void s_gpword
PARAMS ((int));
384 static void s_cpadd
PARAMS ((int));
385 #ifndef ECOFF_DEBUGGING
386 static void md_obj_begin
PARAMS ((void));
387 static void md_obj_end
PARAMS ((void));
388 static long get_number
PARAMS ((void));
389 static void s_ent
PARAMS ((int));
390 static void s_mipsend
PARAMS ((int));
391 static void s_file
PARAMS ((int));
393 static void s_frame
PARAMS ((int));
394 static void s_loc
PARAMS ((int));
395 static void s_mask
PARAMS ((char));
399 static void s_elf_section
PARAMS ((int));
404 The following pseudo-ops from the Kane and Heinrich MIPS book
405 should be defined here, but are currently unsupported: .alias,
406 .galive, .gjaldef, .gjrlive, .livereg, .noalias.
408 The following pseudo-ops from the Kane and Heinrich MIPS book are
409 specific to the type of debugging information being generated, and
410 should be defined by the object format: .aent, .begin, .bend,
411 .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp,
414 The following pseudo-ops from the Kane and Heinrich MIPS book are
415 not MIPS CPU specific, but are also not specific to the object file
416 format. This file is probably the best place to define them, but
417 they are not currently supported: .asm0, .endr, .lab, .repeat,
418 .struct, .weakext. */
420 const pseudo_typeS md_pseudo_table
[] =
422 /* MIPS specific pseudo-ops. */
423 {"option", s_option
, 0},
424 {"set", s_mipsset
, 0},
425 {"rdata", s_change_sec
, 'r'},
426 {"sdata", s_change_sec
, 's'},
427 {"livereg", s_ignore
, 0},
428 { "abicalls", s_abicalls
, 0},
429 { "cpload", s_cpload
, 0},
430 { "cprestore", s_cprestore
, 0},
431 { "gpword", s_gpword
, 0},
432 { "cpadd", s_cpadd
, 0},
434 /* Relatively generic pseudo-ops that happen to be used on MIPS
436 {"asciiz", s_stringer
, 1},
437 {"bss", s_change_sec
, 'b'},
440 {"dword", s_cons
, 3},
442 /* These pseudo-ops are defined in read.c, but must be overridden
443 here for one reason or another. */
444 {"align", s_align
, 0},
445 {"ascii", s_stringer
, 0},
446 {"asciz", s_stringer
, 1},
448 {"data", s_change_sec
, 'd'},
449 {"double", s_float_cons
, 'd'},
450 {"extern", s_extern
, 0},
451 {"float", s_float_cons
, 'f'},
452 {"globl", s_mips_globl
, 0},
453 {"global", s_mips_globl
, 0},
454 {"hword", s_cons
, 1},
459 {"short", s_cons
, 1},
460 {"single", s_float_cons
, 'f'},
461 {"space", s_mips_space
, 0},
462 {"text", s_change_sec
, 't'},
465 #ifndef ECOFF_DEBUGGING
466 /* These pseudo-ops should be defined by the object file format.
467 However, a.out doesn't support them, so we have versions here. */
469 {"bgnb", s_ignore
, 0},
470 {"end", s_mipsend
, 0},
471 {"endb", s_ignore
, 0},
474 {"fmask", s_ignore
, 'F'},
475 {"frame", s_ignore
, 0},
476 {"loc", s_ignore
, 0},
477 {"mask", s_ignore
, 'R'},
478 {"verstamp", s_ignore
, 0},
482 /* We need to tweak the ELF ".section" pseudo-op a bit. */
483 {"section", s_elf_section
, 0},
490 const relax_typeS md_relax_table
[] =
495 static char *expr_end
;
497 static expressionS imm_expr
;
498 static expressionS offset_expr
;
499 static bfd_reloc_code_real_type imm_reloc
;
500 static bfd_reloc_code_real_type offset_reloc
;
502 /* FIXME: This should be handled in a different way. */
503 extern int target_big_endian
;
506 * This function is called once, at assembler startup time. It should
507 * set up all the tables, etc. that the MD part of the assembler will need.
513 register const char *retval
= NULL
;
514 register unsigned int i
= 0;
522 if (strcmp (cpu
+ (sizeof TARGET_CPU
) - 3, "el") == 0)
524 a
= xmalloc (sizeof TARGET_CPU
);
525 strcpy (a
, TARGET_CPU
);
526 a
[(sizeof TARGET_CPU
) - 3] = '\0';
530 if (strcmp (cpu
, "mips") == 0)
535 else if (strcmp (cpu
, "r6000") == 0
536 || strcmp (cpu
, "mips2") == 0)
541 else if (strcmp (cpu
, "mips64") == 0
542 || strcmp (cpu
, "r4000") == 0
543 || strcmp (cpu
, "mips3") == 0)
548 else if (strcmp (cpu
, "r4400") == 0)
553 else if (strcmp (cpu
, "mips64orion") == 0
554 || strcmp (cpu
, "r4600") == 0)
569 if (mips_isa
< 2 && mips_trap
)
570 as_bad ("trap exception not supported at ISA 1");
575 ok
= bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, 3000);
578 ok
= bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, 6000);
581 ok
= bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, 4000);
585 as_warn ("Could not set architecture and machine");
587 file_mips_isa
= mips_isa
;
589 op_hash
= hash_new ();
591 for (i
= 0; i
< NUMOPCODES
;)
593 const char *name
= mips_opcodes
[i
].name
;
595 retval
= hash_insert (op_hash
, name
, (PTR
) &mips_opcodes
[i
]);
598 fprintf (stderr
, "internal error: can't hash `%s': %s\n",
599 mips_opcodes
[i
].name
, retval
);
600 as_fatal ("Broken assembler. No assembly attempted.");
604 if (mips_opcodes
[i
].pinfo
!= INSN_MACRO
605 && ((mips_opcodes
[i
].match
& mips_opcodes
[i
].mask
)
606 != mips_opcodes
[i
].match
))
608 fprintf (stderr
, "internal error: bad opcode: `%s' \"%s\"\n",
609 mips_opcodes
[i
].name
, mips_opcodes
[i
].args
);
610 as_fatal ("Broken assembler. No assembly attempted.");
614 while ((i
< NUMOPCODES
) && !strcmp (mips_opcodes
[i
].name
, name
));
617 mips_no_prev_insn ();
625 /* set the default alignment for the text section (2**2) */
626 record_alignment (text_section
, 2);
628 /* FIXME: This should be handled in a different way. */
629 target_big_endian
= byte_order
== BIG_ENDIAN
;
632 bfd_set_gp_size (stdoutput
, g_switch_value
);
636 /* Sections must be aligned to 16 byte boundaries. */
637 (void) bfd_set_section_alignment (stdoutput
, text_section
, 4);
638 (void) bfd_set_section_alignment (stdoutput
, data_section
, 4);
639 (void) bfd_set_section_alignment (stdoutput
, bss_section
, 4);
641 /* Create a .reginfo section for register masks and a .mdebug
642 section for debugging information. */
650 sec
= subseg_new (".reginfo", (subsegT
) 0);
652 /* The ABI says this section should be loaded so that the running
653 program can access it. */
654 (void) bfd_set_section_flags (stdoutput
, sec
,
655 (SEC_ALLOC
| SEC_LOAD
656 | SEC_READONLY
| SEC_DATA
));
657 (void) bfd_set_section_alignment (stdoutput
, sec
, 2);
659 mips_regmask_frag
= frag_more (sizeof (Elf32_External_RegInfo
));
661 #ifdef ECOFF_DEBUGGING
662 sec
= subseg_new (".mdebug", (subsegT
) 0);
663 (void) bfd_set_section_flags (stdoutput
, sec
,
664 SEC_HAS_CONTENTS
| SEC_READONLY
);
665 (void) bfd_set_section_alignment (stdoutput
, sec
, 2);
668 subseg_set (seg
, subseg
);
672 #ifndef ECOFF_DEBUGGING
680 #ifndef ECOFF_DEBUGGING
689 struct mips_cl_insn insn
;
691 imm_expr
.X_op
= O_absent
;
692 offset_expr
.X_op
= O_absent
;
694 mips_ip (str
, &insn
);
697 as_bad ("%s `%s'", insn_error
, str
);
700 if (insn
.insn_mo
->pinfo
== INSN_MACRO
)
706 if (imm_expr
.X_op
!= O_absent
)
707 append_insn ((char *) NULL
, &insn
, &imm_expr
, imm_reloc
);
708 else if (offset_expr
.X_op
!= O_absent
)
709 append_insn ((char *) NULL
, &insn
, &offset_expr
, offset_reloc
);
711 append_insn ((char *) NULL
, &insn
, NULL
, BFD_RELOC_UNUSED
);
715 /* See whether instruction IP reads register REG. If FPR is non-zero,
716 REG is a floating point register. */
719 insn_uses_reg (ip
, reg
, fpr
)
720 struct mips_cl_insn
*ip
;
724 /* Don't report on general register 0, since it never changes. */
725 if (! fpr
&& reg
== 0)
730 /* If we are called with either $f0 or $f1, we must check $f0.
731 This is not optimal, because it will introduce an unnecessary
732 NOP between "lwc1 $f0" and "swc1 $f1". To fix this we would
733 need to distinguish reading both $f0 and $f1 or just one of
734 them. Note that we don't have to check the other way,
735 because there is no instruction that sets both $f0 and $f1
736 and requires a delay. */
737 if ((ip
->insn_mo
->pinfo
& INSN_READ_FPR_S
)
738 && (((ip
->insn_opcode
>> OP_SH_FS
) & OP_MASK_FS
)
739 == (reg
&~ (unsigned) 1)))
741 if ((ip
->insn_mo
->pinfo
& INSN_READ_FPR_T
)
742 && (((ip
->insn_opcode
>> OP_SH_FT
) & OP_MASK_FT
)
743 == (reg
&~ (unsigned) 1)))
748 if ((ip
->insn_mo
->pinfo
& INSN_READ_GPR_S
)
749 && ((ip
->insn_opcode
>> OP_SH_RS
) & OP_MASK_RS
) == reg
)
751 if ((ip
->insn_mo
->pinfo
& INSN_READ_GPR_T
)
752 && ((ip
->insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
) == reg
)
759 /* Output an instruction. PLACE is where to put the instruction; if
760 it is NULL, this uses frag_more to get room. IP is the instruction
761 information. ADDRESS_EXPR is an operand of the instruction to be
762 used with RELOC_TYPE. */
765 append_insn (place
, ip
, address_expr
, reloc_type
)
767 struct mips_cl_insn
*ip
;
768 expressionS
*address_expr
;
769 bfd_reloc_code_real_type reloc_type
;
771 register unsigned long prev_pinfo
, pinfo
;
776 prev_pinfo
= prev_insn
.insn_mo
->pinfo
;
777 pinfo
= ip
->insn_mo
->pinfo
;
779 if (place
== NULL
&& ! mips_noreorder
)
781 /* If the previous insn required any delay slots, see if we need
782 to insert a NOP or two. There are eight kinds of possible
783 hazards, of which an instruction can have at most one type.
784 (1) a load from memory delay
785 (2) a load from a coprocessor delay
786 (3) an unconditional branch delay
787 (4) a conditional branch delay
788 (5) a move to coprocessor register delay
789 (6) a load coprocessor register from memory delay
790 (7) a coprocessor condition code delay
791 (8) a HI/LO special register delay
793 There are a lot of optimizations we could do that we don't.
794 In particular, we do not, in general, reorder instructions.
795 If you use gcc with optimization, it will reorder
796 instructions and generally do much more optimization then we
797 do here; repeating all that work in the assembler would only
798 benefit hand written assembly code, and does not seem worth
801 /* This is how a NOP is emitted. */
802 #define emit_nop() md_number_to_chars (frag_more (4), 0, 4)
804 /* The previous insn might require a delay slot, depending upon
805 the contents of the current insn. */
806 if ((prev_pinfo
& INSN_LOAD_COPROC_DELAY
)
808 && (prev_pinfo
& INSN_LOAD_MEMORY_DELAY
)))
810 /* A load from a coprocessor or from memory. All load
811 delays delay the use of general register rt for one
812 instruction on the r3000. The r6000 and r4000 use
814 know (prev_pinfo
& INSN_WRITE_GPR_T
);
815 if (mips_optimize
== 0
816 || insn_uses_reg (ip
,
817 ((prev_insn
.insn_opcode
>> OP_SH_RT
)
822 else if ((prev_pinfo
& INSN_COPROC_MOVE_DELAY
)
824 && (prev_pinfo
& INSN_COPROC_MEMORY_DELAY
)))
826 /* A generic coprocessor delay. The previous instruction
827 modified a coprocessor general or control register. If
828 it modified a control register, we need to avoid any
829 coprocessor instruction (this is probably not always
830 required, but it sometimes is). If it modified a general
831 register, we avoid using that register.
833 On the r6000 and r4000 loading a coprocessor register
834 from memory is interlocked, and does not require a delay.
836 This case is not handled very well. There is no special
837 knowledge of CP0 handling, and the coprocessors other
838 than the floating point unit are not distinguished at
840 if (prev_pinfo
& INSN_WRITE_FPR_T
)
842 if (mips_optimize
== 0
843 || insn_uses_reg (ip
,
844 ((prev_insn
.insn_opcode
>> OP_SH_FT
)
849 else if (prev_pinfo
& INSN_WRITE_FPR_S
)
851 if (mips_optimize
== 0
852 || insn_uses_reg (ip
,
853 ((prev_insn
.insn_opcode
>> OP_SH_FS
)
860 /* We don't know exactly what the previous instruction
861 does. If the current instruction uses a coprocessor
862 register, we must insert a NOP. If previous
863 instruction may set the condition codes, and the
864 current instruction uses them, we must insert two
866 if (mips_optimize
== 0
867 || ((prev_pinfo
& INSN_WRITE_COND_CODE
)
868 && (pinfo
& INSN_READ_COND_CODE
)))
870 else if (pinfo
& INSN_COP
)
874 else if (prev_pinfo
& INSN_WRITE_COND_CODE
)
876 /* The previous instruction sets the coprocessor condition
877 codes, but does not require a general coprocessor delay
878 (this means it is a floating point comparison
879 instruction). If this instruction uses the condition
880 codes, we need to insert a single NOP. */
881 if (mips_optimize
== 0
882 || (pinfo
& INSN_READ_COND_CODE
))
885 else if (prev_pinfo
& INSN_READ_LO
)
887 /* The previous instruction reads the LO register; if the
888 current instruction writes to the LO register, we must
890 if (mips_optimize
== 0
891 || (pinfo
& INSN_WRITE_LO
))
894 else if (prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
896 /* The previous instruction reads the HI register; if the
897 current instruction writes to the HI register, we must
899 if (mips_optimize
== 0
900 || (pinfo
& INSN_WRITE_HI
))
904 /* There are two cases which require two intervening
905 instructions: 1) setting the condition codes using a move to
906 coprocessor instruction which requires a general coprocessor
907 delay and then reading the condition codes 2) reading the HI
908 or LO register and then writing to it. If we are not already
909 emitting a NOP instruction, we must check for these cases
910 compared to the instruction previous to the previous
913 && (((prev_prev_insn
.insn_mo
->pinfo
& INSN_COPROC_MOVE_DELAY
)
914 && (prev_prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
)
915 && (pinfo
& INSN_READ_COND_CODE
))
916 || ((prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
)
917 && (pinfo
& INSN_WRITE_LO
))
918 || ((prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
919 && (pinfo
& INSN_WRITE_HI
))))
922 /* If we are being given a nop instruction, don't bother with
923 one of the nops we would otherwise output. This will only
924 happen when a nop instruction is used with mips_optimize set
926 if (nops
> 0 && ip
->insn_opcode
== 0)
929 /* Now emit the right number of NOP instructions. */
934 for (i
= 0; i
< nops
; i
++)
937 listing_prev_line ();
938 if (insn_label
!= NULL
)
940 assert (S_GET_SEGMENT (insn_label
) == now_seg
);
941 insn_label
->sy_frag
= frag_now
;
942 S_SET_VALUE (insn_label
, (valueT
) frag_now_fix ());
952 if (address_expr
!= NULL
)
954 if (address_expr
->X_op
== O_constant
)
959 ip
->insn_opcode
|= address_expr
->X_add_number
;
963 ip
->insn_opcode
|= address_expr
->X_add_number
& 0xffff;
966 case BFD_RELOC_MIPS_JMP
:
967 case BFD_RELOC_16_PCREL_S2
:
976 assert (reloc_type
!= BFD_RELOC_UNUSED
);
978 /* Don't generate a reloc if we are writing into a variant
981 fixp
= fix_new_exp (frag_now
, f
- frag_now
->fr_literal
, 4,
983 reloc_type
== BFD_RELOC_16_PCREL_S2
,
988 md_number_to_chars (f
, ip
->insn_opcode
, 4);
990 /* Update the register mask information. */
991 if (pinfo
& INSN_WRITE_GPR_D
)
992 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
);
993 if ((pinfo
& (INSN_WRITE_GPR_T
| INSN_READ_GPR_T
)) != 0)
994 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
);
995 if (pinfo
& INSN_READ_GPR_S
)
996 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> OP_SH_RS
) & OP_MASK_RS
);
997 if (pinfo
& INSN_WRITE_GPR_31
)
998 mips_gprmask
|= 1 << 31;
999 if (pinfo
& INSN_WRITE_FPR_D
)
1000 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FD
) & OP_MASK_FD
);
1001 if ((pinfo
& (INSN_WRITE_FPR_S
| INSN_READ_FPR_S
)) != 0)
1002 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FS
) & OP_MASK_FS
);
1003 if ((pinfo
& (INSN_WRITE_FPR_T
| INSN_READ_FPR_T
)) != 0)
1004 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FT
) & OP_MASK_FT
);
1005 if (pinfo
& INSN_COP
)
1007 /* We don't keep enough information to sort these cases out. */
1009 /* Never set the bit for $0, which is always zero. */
1010 mips_gprmask
&=~ 1 << 0;
1012 if (place
== NULL
&& ! mips_noreorder
)
1014 /* Filling the branch delay slot is more complex. We try to
1015 switch the branch with the previous instruction, which we can
1016 do if the previous instruction does not set up a condition
1017 that the branch tests and if the branch is not itself the
1018 target of any branch. */
1019 if ((pinfo
& INSN_UNCOND_BRANCH_DELAY
)
1020 || (pinfo
& INSN_COND_BRANCH_DELAY
))
1022 if (mips_optimize
< 2
1023 /* If we have seen .set volatile or .set nomove, don't
1026 /* If we had to emit any NOP instructions, then we
1027 already know we can not swap. */
1029 /* If we don't even know the previous insn, we can not
1031 || ! prev_insn_valid
1032 /* If the previous insn is already in a branch delay
1033 slot, then we can not swap. */
1034 || prev_insn_is_delay_slot
1035 /* If the previous previous insn was in a .set
1036 noreorder, we can't swap. Actually, the MIPS
1037 assembler will swap in this situation. However, gcc
1038 configured -with-gnu-as will generate code like
1044 in which we can not swap the bne and INSN. If gcc is
1045 not configured -with-gnu-as, it does not output the
1046 .set pseudo-ops. We don't have to check
1047 prev_insn_unreordered, because prev_insn_valid will
1048 be 0 in that case. We don't want to use
1049 prev_prev_insn_valid, because we do want to be able
1050 to swap at the start of a function. */
1051 || prev_prev_insn_unreordered
1052 /* If the branch is itself the target of a branch, we
1053 can not swap. We cheat on this; all we check for is
1054 whether there is a label on this instruction. If
1055 there are any branches to anything other than a
1056 label, users must use .set noreorder. */
1057 || insn_label
!= NULL
1058 /* If the previous instruction is in a variant frag, we
1059 can not do the swap. */
1060 || prev_insn_frag
->fr_type
== rs_machine_dependent
1061 /* If the branch reads the condition codes, we don't
1062 even try to swap, because in the sequence
1067 we can not swap, and I don't feel like handling that
1069 || (pinfo
& INSN_READ_COND_CODE
)
1070 /* We can not swap with an instruction that requires a
1071 delay slot, becase the target of the branch might
1072 interfere with that instruction. */
1074 & (INSN_LOAD_COPROC_DELAY
1075 | INSN_COPROC_MOVE_DELAY
1076 | INSN_WRITE_COND_CODE
1081 & (INSN_LOAD_MEMORY_DELAY
1082 | INSN_COPROC_MEMORY_DELAY
)))
1083 /* We can not swap with a branch instruction. */
1085 & (INSN_UNCOND_BRANCH_DELAY
1086 | INSN_COND_BRANCH_DELAY
1087 | INSN_COND_BRANCH_LIKELY
))
1088 /* We do not swap with a trap instruction, since it
1089 complicates trap handlers to have the trap
1090 instruction be in a delay slot. */
1091 || (prev_pinfo
& INSN_TRAP
)
1092 /* If the branch reads a register that the previous
1093 instruction sets, we can not swap. */
1094 || ((prev_pinfo
& INSN_WRITE_GPR_T
)
1095 && insn_uses_reg (ip
,
1096 ((prev_insn
.insn_opcode
>> OP_SH_RT
)
1099 || ((prev_pinfo
& INSN_WRITE_GPR_D
)
1100 && insn_uses_reg (ip
,
1101 ((prev_insn
.insn_opcode
>> OP_SH_RD
)
1104 /* If the branch writes a register that the previous
1105 instruction sets, we can not swap (we know that
1106 branches write only to RD or to $31). */
1107 || ((prev_pinfo
& INSN_WRITE_GPR_T
)
1108 && (((pinfo
& INSN_WRITE_GPR_D
)
1109 && (((prev_insn
.insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
)
1110 == ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)))
1111 || ((pinfo
& INSN_WRITE_GPR_31
)
1112 && (((prev_insn
.insn_opcode
>> OP_SH_RT
)
1115 || ((prev_pinfo
& INSN_WRITE_GPR_D
)
1116 && (((pinfo
& INSN_WRITE_GPR_D
)
1117 && (((prev_insn
.insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)
1118 == ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)))
1119 || ((pinfo
& INSN_WRITE_GPR_31
)
1120 && (((prev_insn
.insn_opcode
>> OP_SH_RD
)
1123 /* If the branch writes a register that the previous
1124 instruction reads, we can not swap (we know that
1125 branches only write to RD or to $31). */
1126 || ((pinfo
& INSN_WRITE_GPR_D
)
1127 && insn_uses_reg (&prev_insn
,
1128 ((ip
->insn_opcode
>> OP_SH_RD
)
1131 || ((pinfo
& INSN_WRITE_GPR_31
)
1132 && insn_uses_reg (&prev_insn
, 31, 0))
1133 /* If we are generating embedded PIC code, the branch
1134 might be expanded into a sequence which uses $at, so
1135 we can't swap with an instruction which reads it. */
1136 || (mips_pic
== EMBEDDED_PIC
1137 && insn_uses_reg (&prev_insn
, AT
, 0))
1138 /* If the previous previous instruction has a load
1139 delay, and sets a register that the branch reads, we
1141 || (((prev_prev_insn
.insn_mo
->pinfo
& INSN_LOAD_COPROC_DELAY
)
1143 && (prev_prev_insn
.insn_mo
->pinfo
1144 & INSN_LOAD_MEMORY_DELAY
)))
1145 && insn_uses_reg (ip
,
1146 ((prev_prev_insn
.insn_opcode
>> OP_SH_RT
)
1150 /* We could do even better for unconditional branches to
1151 portions of this object file; we could pick up the
1152 instruction at the destination, put it in the delay
1153 slot, and bump the destination address. */
1155 /* Update the previous insn information. */
1156 prev_prev_insn
= *ip
;
1157 prev_insn
.insn_mo
= &dummy_opcode
;
1164 /* It looks like we can actually do the swap. */
1165 prev_f
= prev_insn_frag
->fr_literal
+ prev_insn_where
;
1166 memcpy (temp
, prev_f
, 4);
1167 memcpy (prev_f
, f
, 4);
1168 memcpy (f
, temp
, 4);
1171 prev_insn_fixp
->fx_frag
= frag_now
;
1172 prev_insn_fixp
->fx_where
= f
- frag_now
->fr_literal
;
1176 fixp
->fx_frag
= prev_insn_frag
;
1177 fixp
->fx_where
= prev_insn_where
;
1179 /* Update the previous insn information; leave prev_insn
1181 prev_prev_insn
= *ip
;
1183 prev_insn_is_delay_slot
= 1;
1185 /* If that was an unconditional branch, forget the previous
1186 insn information. */
1187 if (pinfo
& INSN_UNCOND_BRANCH_DELAY
)
1189 prev_prev_insn
.insn_mo
= &dummy_opcode
;
1190 prev_insn
.insn_mo
= &dummy_opcode
;
1193 else if (pinfo
& INSN_COND_BRANCH_LIKELY
)
1195 /* We don't yet optimize a branch likely. What we should do
1196 is look at the target, copy the instruction found there
1197 into the delay slot, and increment the branch to jump to
1198 the next instruction. */
1200 /* Update the previous insn information. */
1201 prev_prev_insn
= *ip
;
1202 prev_insn
.insn_mo
= &dummy_opcode
;
1206 /* Update the previous insn information. */
1208 prev_prev_insn
.insn_mo
= &dummy_opcode
;
1210 prev_prev_insn
= prev_insn
;
1213 /* Any time we see a branch, we always fill the delay slot
1214 immediately; since this insn is not a branch, we know it
1215 is not in a delay slot. */
1216 prev_insn_is_delay_slot
= 0;
1219 prev_prev_insn_unreordered
= prev_insn_unreordered
;
1220 prev_insn_unreordered
= 0;
1221 prev_insn_frag
= frag_now
;
1222 prev_insn_where
= f
- frag_now
->fr_literal
;
1223 prev_insn_fixp
= fixp
;
1224 prev_insn_valid
= 1;
1227 /* We just output an insn, so the next one doesn't have a label. */
1231 /* This function forgets that there was any previous instruction or
1235 mips_no_prev_insn ()
1237 prev_insn
.insn_mo
= &dummy_opcode
;
1238 prev_prev_insn
.insn_mo
= &dummy_opcode
;
1239 prev_insn_valid
= 0;
1240 prev_insn_is_delay_slot
= 0;
1241 prev_insn_unreordered
= 0;
1242 prev_prev_insn_unreordered
= 0;
1246 /* This function must be called whenever we turn on noreorder or emit
1247 something other than instructions. It inserts any NOPS which might
1248 be needed by the previous instruction, and clears the information
1249 kept for the previous instructions. */
1254 if (! mips_noreorder
)
1259 if ((prev_insn
.insn_mo
->pinfo
1260 & (INSN_LOAD_COPROC_DELAY
1261 | INSN_COPROC_MOVE_DELAY
1262 | INSN_WRITE_COND_CODE
1266 && (prev_insn
.insn_mo
->pinfo
1267 & (INSN_LOAD_MEMORY_DELAY
1268 | INSN_COPROC_MEMORY_DELAY
))))
1271 if ((prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
)
1272 || (prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
1273 || (prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
))
1276 else if ((prev_prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
)
1277 || (prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
1278 || (prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
))
1283 if (insn_label
!= NULL
)
1285 assert (S_GET_SEGMENT (insn_label
) == now_seg
);
1286 insn_label
->sy_frag
= frag_now
;
1287 S_SET_VALUE (insn_label
, (valueT
) frag_now_fix ());
1292 mips_no_prev_insn ();
1295 /* Build an instruction created by a macro expansion. This is passed
1296 a pointer to the count of instructions created so far, an
1297 expression, the name of the instruction to build, an operand format
1298 string, and corresponding arguments. */
1302 macro_build (char *place
,
1308 #else /* ! defined (NO_STDARG) */
1310 macro_build (place
, counter
, ep
, name
, fmt
, va_alist
)
1317 #endif /* ! defined (NO_STDARG) */
1319 struct mips_cl_insn insn
;
1320 bfd_reloc_code_real_type r
;
1324 va_start (args
, fmt
);
1330 * If the macro is about to expand into a second instruction,
1331 * print a warning if needed. We need to pass ip as a parameter
1332 * to generate a better warning message here...
1334 if (mips_warn_about_macros
&& place
== NULL
&& *counter
== 1)
1335 as_warn ("Macro instruction expanded into multiple instructions");
1338 *counter
+= 1; /* bump instruction counter */
1340 r
= BFD_RELOC_UNUSED
;
1341 insn
.insn_mo
= (struct mips_opcode
*) hash_find (op_hash
, name
);
1342 assert (insn
.insn_mo
);
1343 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
1345 while (strcmp (fmt
, insn
.insn_mo
->args
) != 0
1346 || insn
.insn_mo
->pinfo
== INSN_MACRO
)
1349 assert (insn
.insn_mo
->name
);
1350 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
1352 insn
.insn_opcode
= insn
.insn_mo
->match
;
1368 insn
.insn_opcode
|= va_arg (args
, int) << 16;
1374 insn
.insn_opcode
|= va_arg (args
, int) << 16;
1379 insn
.insn_opcode
|= va_arg (args
, int) << 11;
1384 insn
.insn_opcode
|= va_arg (args
, int) << 11;
1391 insn
.insn_opcode
|= va_arg (args
, int) << 6;
1395 insn
.insn_opcode
|= va_arg (args
, int) << 6;
1399 insn
.insn_opcode
|= va_arg (args
, int) << 6;
1406 insn
.insn_opcode
|= va_arg (args
, int) << 21;
1412 r
= (bfd_reloc_code_real_type
) va_arg (args
, int);
1413 assert (r
== BFD_RELOC_MIPS_GPREL
1414 || r
== BFD_RELOC_MIPS_LITERAL
1415 || r
== BFD_RELOC_LO16
1416 || r
== BFD_RELOC_MIPS_GOT16
1417 || r
== BFD_RELOC_MIPS_CALL16
1418 || (ep
->X_op
== O_subtract
1419 && now_seg
== text_section
1420 && S_GET_SEGMENT (ep
->X_op_symbol
) == text_section
1421 && r
== BFD_RELOC_PCREL_LO16
));
1425 r
= (bfd_reloc_code_real_type
) va_arg (args
, int);
1427 && (ep
->X_op
== O_constant
1428 || (ep
->X_op
== O_symbol
1429 && (r
== BFD_RELOC_HI16_S
1430 || r
== BFD_RELOC_HI16
))
1431 || (ep
->X_op
== O_subtract
1432 && now_seg
== text_section
1433 && S_GET_SEGMENT (ep
->X_op_symbol
) == text_section
1434 && r
== BFD_RELOC_PCREL_HI16_S
)));
1435 if (ep
->X_op
== O_constant
)
1437 insn
.insn_opcode
|= (ep
->X_add_number
>> 16) & 0xffff;
1439 r
= BFD_RELOC_UNUSED
;
1444 assert (ep
!= NULL
);
1446 * This allows macro() to pass an immediate expression for
1447 * creating short branches without creating a symbol.
1448 * Note that the expression still might come from the assembly
1449 * input, in which case the value is not checked for range nor
1450 * is a relocation entry generated (yuck).
1452 if (ep
->X_op
== O_constant
)
1454 insn
.insn_opcode
|= (ep
->X_add_number
>> 2) & 0xffff;
1458 r
= BFD_RELOC_16_PCREL_S2
;
1462 assert (ep
!= NULL
);
1463 r
= BFD_RELOC_MIPS_JMP
;
1472 assert (r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
1474 append_insn (place
, &insn
, ep
, r
);
1478 * Generate a "lui" instruction.
1481 macro_build_lui (place
, counter
, ep
, regnum
)
1487 expressionS high_expr
;
1488 struct mips_cl_insn insn
;
1489 bfd_reloc_code_real_type r
;
1490 CONST
char *name
= "lui";
1491 CONST
char *fmt
= "t,u";
1497 high_expr
.X_op
= O_constant
;
1498 high_expr
.X_add_number
= 0;
1501 if (high_expr
.X_op
== O_constant
)
1503 /* we can compute the instruction now without a relocation entry */
1504 if (high_expr
.X_add_number
& 0x8000)
1505 high_expr
.X_add_number
+= 0x10000;
1506 high_expr
.X_add_number
=
1507 ((unsigned long) high_expr
.X_add_number
>> 16) & 0xffff;
1508 r
= BFD_RELOC_UNUSED
;
1512 assert (ep
->X_op
== O_symbol
);
1513 /* _gp_disp is a special case, used from s_cpload. */
1514 assert (mips_pic
== NO_PIC
1515 || strcmp (S_GET_NAME (ep
->X_add_symbol
), "_gp_disp") == 0);
1516 r
= BFD_RELOC_HI16_S
;
1520 * If the macro is about to expand into a second instruction,
1521 * print a warning if needed. We need to pass ip as a parameter
1522 * to generate a better warning message here...
1524 if (mips_warn_about_macros
&& place
== NULL
&& *counter
== 1)
1525 as_warn ("Macro instruction expanded into multiple instructions");
1528 *counter
+= 1; /* bump instruction counter */
1530 insn
.insn_mo
= (struct mips_opcode
*) hash_find (op_hash
, name
);
1531 assert (insn
.insn_mo
);
1532 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
1533 assert (strcmp (fmt
, insn
.insn_mo
->args
) == 0);
1535 insn
.insn_opcode
= insn
.insn_mo
->match
| (regnum
<< OP_SH_RT
);
1536 if (r
== BFD_RELOC_UNUSED
)
1538 insn
.insn_opcode
|= high_expr
.X_add_number
;
1539 append_insn (place
, &insn
, NULL
, r
);
1542 append_insn (place
, &insn
, &high_expr
, r
);
1546 * Generates code to set the $at register to true (one)
1547 * if reg is less than the immediate expression.
1550 set_at (counter
, reg
, unsignedp
)
1555 if (imm_expr
.X_add_number
>= -0x8000 && imm_expr
.X_add_number
< 0x8000)
1556 macro_build ((char *) NULL
, counter
, &imm_expr
,
1557 unsignedp
? "sltiu" : "slti",
1558 "t,r,j", AT
, reg
, (int) BFD_RELOC_LO16
);
1561 load_register (counter
, AT
, &imm_expr
);
1562 macro_build ((char *) NULL
, counter
, NULL
,
1563 unsignedp
? "sltu" : "slt",
1564 "d,v,t", AT
, reg
, AT
);
1568 /* Warn if an expression is not a constant. */
1571 check_absolute_expr (ip
, ex
)
1572 struct mips_cl_insn
*ip
;
1575 if (ex
->X_op
!= O_constant
)
1576 as_warn ("Instruction %s requires absolute expression", ip
->insn_mo
->name
);
1580 * This routine generates the least number of instructions neccessary to load
1581 * an absolute expression value into a register.
1584 load_register (counter
, reg
, ep
)
1589 assert (ep
->X_op
== O_constant
);
1590 if (ep
->X_add_number
>= -0x8000 && ep
->X_add_number
< 0x8000)
1592 /* No need to ever use daddiu here, since we are adding in
1594 macro_build ((char *) NULL
, counter
, ep
, "addiu", "t,r,j", reg
, 0,
1595 (int) BFD_RELOC_LO16
);
1597 else if (ep
->X_add_number
>= 0 && ep
->X_add_number
< 0x10000)
1598 macro_build ((char *) NULL
, counter
, ep
, "ori", "t,r,i", reg
, 0,
1599 (int) BFD_RELOC_LO16
);
1600 else if ((ep
->X_add_number
&~ (offsetT
) 0x7fffffff) == 0
1601 || ((ep
->X_add_number
&~ (offsetT
) 0x7fffffff)
1602 == ~ (offsetT
) 0x7fffffff))
1604 macro_build ((char *) NULL
, counter
, ep
, "lui", "t,u", reg
,
1605 (int) BFD_RELOC_HI16
);
1606 if ((ep
->X_add_number
& 0xffff) != 0)
1607 macro_build ((char *) NULL
, counter
, ep
, "ori", "t,r,i", reg
, reg
,
1608 (int) BFD_RELOC_LO16
);
1610 else if (mips_isa
< 3)
1612 as_bad ("Number larger than 32 bits");
1613 macro_build ((char *) NULL
, counter
, ep
, "addiu", "t,r,j", reg
, 0,
1614 (int) BFD_RELOC_LO16
);
1619 expressionS hi32
, lo32
;
1623 hi32
.X_add_number
>>= shift
;
1624 hi32
.X_add_number
&= 0xffffffff;
1625 if ((hi32
.X_add_number
& 0x80000000) != 0)
1626 hi32
.X_add_number
|= ~ (offsetT
) 0xffffffff;
1627 load_register (counter
, reg
, &hi32
);
1629 lo32
.X_add_number
&= 0xffffffff;
1630 if ((lo32
.X_add_number
& 0xffff0000) == 0)
1631 macro_build ((char *) NULL
, counter
, NULL
, "dsll32", "d,w,<", reg
,
1637 macro_build ((char *) NULL
, counter
, NULL
, "dsll", "d,w,<", reg
,
1640 mid16
.X_add_number
>>= 16;
1641 macro_build ((char *) NULL
, counter
, &mid16
, "ori", "t,r,i", reg
,
1642 reg
, (int) BFD_RELOC_LO16
);
1643 macro_build ((char *) NULL
, counter
, NULL
, "dsll", "d,w,<", reg
,
1646 if ((lo32
.X_add_number
& 0xffff) != 0)
1647 macro_build ((char *) NULL
, counter
, &lo32
, "ori", "t,r,i", reg
, reg
,
1648 (int) BFD_RELOC_LO16
);
1652 /* Load an address into a register. */
1655 load_address (counter
, reg
, ep
)
1662 if (ep
->X_op
!= O_constant
1663 && ep
->X_op
!= O_symbol
)
1665 as_bad ("expression too complex");
1666 ep
->X_op
= O_constant
;
1669 if (ep
->X_op
== O_constant
)
1671 load_register (counter
, reg
, ep
);
1675 if (mips_pic
== NO_PIC
)
1677 /* If this is a reference to a GP relative symbol, we want
1678 addiu $reg,$gp,<sym> (BFD_RELOC_MIPS_GPREL)
1680 lui $reg,<sym> (BFD_RELOC_HI16_S)
1681 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
1682 If we have an addend, we always use the latter form. */
1683 if (ep
->X_add_number
!= 0)
1688 macro_build ((char *) NULL
, counter
, ep
,
1689 mips_isa
< 3 ? "addiu" : "daddiu",
1690 "t,r,j", reg
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
1691 p
= frag_var (rs_machine_dependent
, 8, 0,
1692 RELAX_ENCODE (4, 8, -4, 0, 0, mips_warn_about_macros
),
1693 ep
->X_add_symbol
, (long) 0, (char *) NULL
);
1695 macro_build_lui (p
, counter
, ep
, reg
);
1698 macro_build (p
, counter
, ep
,
1699 mips_isa
< 3 ? "addiu" : "daddiu",
1700 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
1702 else if (mips_pic
== SVR4_PIC
)
1706 /* If this is a reference to an external symbol, we want
1707 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
1709 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
1711 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
1712 If there is a constant, it must be added in after. */
1713 ex
.X_add_number
= ep
->X_add_number
;
1714 ep
->X_add_number
= 0;
1716 macro_build ((char *) NULL
, counter
, ep
,
1717 mips_isa
< 3 ? "lw" : "ld",
1718 "t,o(b)", reg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
1719 macro_build ((char *) NULL
, counter
, (expressionS
*) NULL
, "nop", "");
1720 p
= frag_var (rs_machine_dependent
, 4, 0,
1721 RELAX_ENCODE (0, 4, -8, 0, 0, mips_warn_about_macros
),
1722 ep
->X_add_symbol
, (long) 0, (char *) NULL
);
1723 macro_build (p
, counter
, ep
,
1724 mips_isa
< 3 ? "addiu" : "daddiu",
1725 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
1726 if (ex
.X_add_number
!= 0)
1728 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
1729 as_bad ("PIC code offset overflow (max 16 signed bits)");
1730 ex
.X_op
= O_constant
;
1731 macro_build (p
, counter
, &ex
,
1732 mips_isa
< 3 ? "addiu" : "daddiu",
1733 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
1736 else if (mips_pic
== EMBEDDED_PIC
)
1739 addiu $reg,$gp,<sym> (BFD_RELOC_MIPS_GPREL)
1741 macro_build ((char *) NULL
, counter
, ep
,
1742 mips_isa
< 3 ? "addiu" : "daddiu",
1743 "t,r,j", reg
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
1751 * This routine implements the seemingly endless macro or synthesized
1752 * instructions and addressing modes in the mips assembly language. Many
1753 * of these macros are simple and are similar to each other. These could
1754 * probably be handled by some kind of table or grammer aproach instead of
1755 * this verbose method. Others are not simple macros but are more like
1756 * optimizing code generation.
1757 * One interesting optimization is when several store macros appear
1758 * consecutivly that would load AT with the upper half of the same address.
1759 * The ensuing load upper instructions are ommited. This implies some kind
1760 * of global optimization. We currently only optimize within a single macro.
1761 * For many of the load and store macros if the address is specified as a
1762 * constant expression in the first 64k of memory (ie ld $2,0x4000c) we
1763 * first load register 'at' with zero and use it as the base register. The
1764 * mips assembler simply uses register $zero. Just one tiny optimization
1769 struct mips_cl_insn
*ip
;
1771 register int treg
, sreg
, dreg
, breg
;
1784 bfd_reloc_code_real_type r
;
1786 int hold_mips_optimize
;
1788 treg
= (ip
->insn_opcode
>> 16) & 0x1f;
1789 dreg
= (ip
->insn_opcode
>> 11) & 0x1f;
1790 sreg
= breg
= (ip
->insn_opcode
>> 21) & 0x1f;
1791 mask
= ip
->insn_mo
->mask
;
1793 expr1
.X_op
= O_constant
;
1794 expr1
.X_op_symbol
= NULL
;
1795 expr1
.X_add_symbol
= NULL
;
1796 expr1
.X_add_number
= 1;
1808 mips_emit_delays ();
1810 mips_any_noreorder
= 1;
1812 expr1
.X_add_number
= 8;
1813 macro_build ((char *) NULL
, &icnt
, &expr1
, "bgez", "s,p", sreg
);
1815 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
1817 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
, sreg
, 0);
1818 macro_build ((char *) NULL
, &icnt
, NULL
,
1819 dbl
? "dsub" : "sub",
1820 "d,v,t", dreg
, 0, sreg
);
1843 if (imm_expr
.X_add_number
>= -0x8000 && imm_expr
.X_add_number
< 0x8000)
1845 macro_build ((char *) NULL
, &icnt
, &imm_expr
, s
, "t,r,j", treg
, sreg
,
1846 (int) BFD_RELOC_LO16
);
1849 load_register (&icnt
, AT
, &imm_expr
);
1850 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "d,v,t", treg
, sreg
, AT
);
1869 if (imm_expr
.X_add_number
>= 0 && imm_expr
.X_add_number
< 0x10000)
1871 if (mask
!= M_NOR_I
)
1872 macro_build ((char *) NULL
, &icnt
, &imm_expr
, s
, "t,r,i", treg
,
1873 sreg
, (int) BFD_RELOC_LO16
);
1876 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "ori", "t,r,i",
1877 treg
, sreg
, (int) BFD_RELOC_LO16
);
1878 macro_build ((char *) NULL
, &icnt
, NULL
, "nor", "d,v,t",
1884 load_register (&icnt
, AT
, &imm_expr
);
1885 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "d,v,t", treg
, sreg
, AT
);
1902 if (imm_expr
.X_add_number
== 0)
1904 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "s,t,p", sreg
,
1908 load_register (&icnt
, AT
, &imm_expr
);
1909 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "s,t,p", sreg
, AT
);
1917 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
1918 likely
? "bgezl" : "bgez",
1924 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
1925 likely
? "blezl" : "blez",
1929 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", AT
, sreg
, treg
);
1930 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
1931 likely
? "beql" : "beq",
1938 /* check for > max integer */
1939 maxnum
= 0x7fffffff;
1947 if (imm_expr
.X_add_number
>= maxnum
1948 && (mips_isa
< 3 || sizeof (maxnum
) > 4))
1951 /* result is always false */
1954 as_warn ("Branch %s is always false (nop)", ip
->insn_mo
->name
);
1955 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
1959 as_warn ("Branch likely %s is always false", ip
->insn_mo
->name
);
1960 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "bnel",
1965 imm_expr
.X_add_number
++;
1969 if (mask
== M_BGEL_I
)
1971 if (imm_expr
.X_add_number
== 0)
1973 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
1974 likely
? "bgezl" : "bgez",
1978 if (imm_expr
.X_add_number
== 1)
1980 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
1981 likely
? "bgtzl" : "bgtz",
1985 maxnum
= 0x7fffffff;
1993 maxnum
= - maxnum
- 1;
1994 if (imm_expr
.X_add_number
<= maxnum
1995 && (mips_isa
< 3 || sizeof (maxnum
) > 4))
1998 /* result is always true */
1999 as_warn ("Branch %s is always true", ip
->insn_mo
->name
);
2000 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "b", "p");
2003 set_at (&icnt
, sreg
, 0);
2004 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2005 likely
? "beql" : "beq",
2016 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2017 likely
? "beql" : "beq",
2021 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", AT
, sreg
,
2023 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2024 likely
? "beql" : "beq",
2031 if (sreg
== 0 || imm_expr
.X_add_number
== -1)
2033 imm_expr
.X_add_number
++;
2037 if (mask
== M_BGEUL_I
)
2039 if (imm_expr
.X_add_number
== 0)
2041 if (imm_expr
.X_add_number
== 1)
2043 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2044 likely
? "bnel" : "bne",
2048 set_at (&icnt
, sreg
, 1);
2049 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2050 likely
? "beql" : "beq",
2059 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2060 likely
? "bgtzl" : "bgtz",
2066 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2067 likely
? "bltzl" : "bltz",
2071 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", AT
, treg
, sreg
);
2072 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2073 likely
? "bnel" : "bne",
2082 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2083 likely
? "bnel" : "bne",
2089 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", AT
, treg
,
2091 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2092 likely
? "bnel" : "bne",
2101 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2102 likely
? "blezl" : "blez",
2108 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2109 likely
? "bgezl" : "bgez",
2113 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", AT
, treg
, sreg
);
2114 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2115 likely
? "beql" : "beq",
2122 maxnum
= 0x7fffffff;
2130 if (imm_expr
.X_add_number
>= maxnum
2131 && (mips_isa
< 3 || sizeof (maxnum
) > 4))
2133 imm_expr
.X_add_number
++;
2137 if (mask
== M_BLTL_I
)
2139 if (imm_expr
.X_add_number
== 0)
2141 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2142 likely
? "bltzl" : "bltz",
2146 if (imm_expr
.X_add_number
== 1)
2148 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2149 likely
? "blezl" : "blez",
2153 set_at (&icnt
, sreg
, 0);
2154 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2155 likely
? "bnel" : "bne",
2164 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2165 likely
? "beql" : "beq",
2171 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", AT
, treg
,
2173 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2174 likely
? "beql" : "beq",
2181 if (sreg
== 0 || imm_expr
.X_add_number
== -1)
2183 imm_expr
.X_add_number
++;
2187 if (mask
== M_BLTUL_I
)
2189 if (imm_expr
.X_add_number
== 0)
2191 if (imm_expr
.X_add_number
== 1)
2193 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2194 likely
? "beql" : "beq",
2198 set_at (&icnt
, sreg
, 1);
2199 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2200 likely
? "bnel" : "bne",
2209 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2210 likely
? "bltzl" : "bltz",
2216 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2217 likely
? "bgtzl" : "bgtz",
2221 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", AT
, sreg
, treg
);
2222 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2223 likely
? "bnel" : "bne",
2234 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2235 likely
? "bnel" : "bne",
2239 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", AT
, sreg
,
2241 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2242 likely
? "bnel" : "bne",
2258 as_warn ("Divide by zero.");
2260 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", 0, 0);
2262 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 7);
2266 mips_emit_delays ();
2268 mips_any_noreorder
= 1;
2269 macro_build ((char *) NULL
, &icnt
, NULL
,
2270 dbl
? "ddiv" : "div",
2271 "z,s,t", sreg
, treg
);
2273 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", treg
, 0);
2276 expr1
.X_add_number
= 8;
2277 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", treg
, 0);
2278 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
2279 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 7);
2281 expr1
.X_add_number
= -1;
2282 macro_build ((char *) NULL
, &icnt
, &expr1
,
2283 dbl
? "daddiu" : "addiu",
2284 "t,r,j", AT
, 0, (int) BFD_RELOC_LO16
);
2285 expr1
.X_add_number
= mips_trap
? (dbl
? 12 : 8) : (dbl
? 20 : 16);
2286 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", treg
, AT
);
2289 expr1
.X_add_number
= 1;
2290 macro_build ((char *) NULL
, &icnt
, &expr1
, "daddiu", "t,r,j", AT
, 0,
2291 (int) BFD_RELOC_LO16
);
2292 macro_build ((char *) NULL
, &icnt
, NULL
, "dsll32", "d,w,<", AT
, AT
,
2297 expr1
.X_add_number
= 0x80000000;
2298 macro_build ((char *) NULL
, &icnt
, &expr1
, "lui", "t,u", AT
,
2299 (int) BFD_RELOC_HI16
);
2302 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", sreg
, AT
);
2305 expr1
.X_add_number
= 8;
2306 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", sreg
, AT
);
2307 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
2308 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 6);
2311 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d", dreg
);
2350 if (imm_expr
.X_add_number
== 0)
2352 as_warn ("Divide by zero.");
2354 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", 0, 0);
2356 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 7);
2359 if (imm_expr
.X_add_number
== 1)
2361 if (strcmp (s2
, "mflo") == 0)
2362 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
,
2365 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
, 0);
2368 if (imm_expr
.X_add_number
== -1
2369 && s
[strlen (s
) - 1] != 'u')
2371 if (strcmp (s2
, "mflo") == 0)
2374 macro_build ((char *) NULL
, &icnt
, NULL
, "dneg", "d,w", dreg
,
2377 macro_build ((char *) NULL
, &icnt
, NULL
, "neg", "d,w", dreg
,
2381 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
, 0);
2385 load_register (&icnt
, AT
, &imm_expr
);
2386 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "z,s,t", sreg
, AT
);
2387 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "d", dreg
);
2406 mips_emit_delays ();
2408 mips_any_noreorder
= 1;
2409 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "z,s,t", sreg
, treg
);
2411 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", treg
, 0);
2414 expr1
.X_add_number
= 8;
2415 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", treg
, 0);
2416 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
2417 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 7);
2420 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "d", dreg
);
2424 /* Load the address of a symbol into a register. If breg is not
2425 zero, we then add a base register to it. */
2427 /* When generating embedded PIC code, we permit expressions of
2430 where bar is an address in the .text section. These are used
2431 when getting the addresses of functions. We don't permit
2432 X_add_number to be non-zero, because if the symbol is
2433 external the relaxing code needs to know that any addend is
2434 purely the offset to X_op_symbol. */
2435 if (mips_pic
== EMBEDDED_PIC
2436 && offset_expr
.X_op
== O_subtract
2437 && now_seg
== text_section
2438 && S_GET_SEGMENT (offset_expr
.X_op_symbol
) == text_section
2440 && offset_expr
.X_add_number
== 0)
2442 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
2443 treg
, (int) BFD_RELOC_PCREL_HI16_S
);
2444 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2445 mips_isa
< 3 ? "addiu" : "daddiu",
2446 "t,r,j", treg
, treg
, (int) BFD_RELOC_PCREL_LO16
);
2450 if (offset_expr
.X_op
!= O_symbol
2451 && offset_expr
.X_op
!= O_constant
)
2453 as_bad ("expression too complex");
2454 offset_expr
.X_op
= O_constant
;
2468 if (offset_expr
.X_op
== O_constant
)
2469 load_register (&icnt
, tempreg
, &offset_expr
);
2470 else if (mips_pic
== NO_PIC
)
2472 /* If this is a reference to an GP relative symbol, we want
2473 addiu $tempreg,$gp,<sym> (BFD_RELOC_MIPS_GPREL)
2475 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
2476 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
2477 If we have a constant, we need two instructions anyhow,
2478 so we may as well always use the latter form. */
2479 if (offset_expr
.X_add_number
!= 0)
2484 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2485 mips_isa
< 3 ? "addiu" : "daddiu",
2486 "t,r,j", tempreg
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
2487 p
= frag_var (rs_machine_dependent
, 8, 0,
2488 RELAX_ENCODE (4, 8, 0, 4, 0,
2489 mips_warn_about_macros
),
2490 offset_expr
.X_add_symbol
, (long) 0,
2493 macro_build_lui (p
, &icnt
, &offset_expr
, tempreg
);
2496 macro_build (p
, &icnt
, &offset_expr
,
2497 mips_isa
< 3 ? "addiu" : "daddiu",
2498 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
2500 else if (mips_pic
== SVR4_PIC
)
2502 /* If this is a reference to an external symbol, and there
2503 is no constant, we want
2504 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
2505 For a local symbol, we want
2506 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
2508 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
2510 If we have a small constant, and this is a reference to
2511 an external symbol, we want
2512 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
2514 addiu $tempreg,$tempreg,<constant>
2515 For a local symbol, we want the same instruction
2516 sequence, but we output a BFD_RELOC_LO16 reloc on the
2519 If we have a large constant, and this is a reference to
2520 an external symbol, we want
2521 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
2522 lui $at,<hiconstant>
2523 addiu $at,$at,<loconstant>
2524 addu $tempreg,$tempreg,$at
2525 For a local symbol, we want the same instruction
2526 sequence, but we output a BFD_RELOC_LO16 reloc on the
2527 addiu instruction. */
2528 expr1
.X_add_number
= offset_expr
.X_add_number
;
2529 offset_expr
.X_add_number
= 0;
2531 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2532 mips_isa
< 3 ? "lw" : "ld",
2533 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
2534 if (expr1
.X_add_number
== 0)
2542 /* We're going to put in an addu instruction using
2543 tempreg, so we may as well insert the nop right
2545 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
2549 p
= frag_var (rs_machine_dependent
, 8 - off
, 0,
2550 RELAX_ENCODE (0, 8 - off
, -4 - off
, 4 - off
, 0,
2552 ? mips_warn_about_macros
2554 offset_expr
.X_add_symbol
, (long) 0,
2558 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
2561 macro_build (p
, &icnt
, &expr1
,
2562 mips_isa
< 3 ? "addiu" : "daddiu",
2563 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
2564 /* FIXME: If breg == 0, and the next instruction uses
2565 $tempreg, then if this variant case is used an extra
2566 nop will be generated. */
2568 else if (expr1
.X_add_number
>= -0x8000
2569 && expr1
.X_add_number
< 0x8000)
2571 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
2573 macro_build ((char *) NULL
, &icnt
, &expr1
,
2574 mips_isa
< 3 ? "addiu" : "daddiu",
2575 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
2576 (void) frag_var (rs_machine_dependent
, 0, 0,
2577 RELAX_ENCODE (0, 0, -12, -4, 0, 0),
2578 offset_expr
.X_add_symbol
, (long) 0,
2585 /* If we are going to add in a base register, and the
2586 target register and the base register are the same,
2587 then we are using AT as a temporary register. Since
2588 we want to load the constant into AT, we add our
2589 current AT (from the global offset table) and the
2590 register into the register now, and pretend we were
2591 not using a base register. */
2596 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
2598 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
2599 mips_isa
< 3 ? "addu" : "daddu",
2600 "d,v,t", treg
, AT
, breg
);
2606 /* Set mips_optimize around the lui instruction to avoid
2607 inserting an unnecessary nop after the lw. */
2608 hold_mips_optimize
= mips_optimize
;
2610 macro_build_lui ((char *) NULL
, &icnt
, &expr1
, AT
);
2611 mips_optimize
= hold_mips_optimize
;
2613 macro_build ((char *) NULL
, &icnt
, &expr1
,
2614 mips_isa
< 3 ? "addiu" : "daddiu",
2615 "t,r,j", AT
, AT
, (int) BFD_RELOC_LO16
);
2616 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
2617 mips_isa
< 3 ? "addu" : "daddu",
2618 "d,v,t", tempreg
, tempreg
, AT
);
2619 (void) frag_var (rs_machine_dependent
, 0, 0,
2620 RELAX_ENCODE (0, 0, -16 + off1
, -8, 0, 0),
2621 offset_expr
.X_add_symbol
, (long) 0,
2626 else if (mips_pic
== EMBEDDED_PIC
)
2629 addiu $tempreg,$gp,<sym> (BFD_RELOC_MIPS_GPREL)
2631 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2632 mips_isa
< 3 ? "addiu" : "daddiu",
2633 "t,r,j", tempreg
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
2639 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
2640 mips_isa
< 3 ? "addu" : "daddu",
2641 "d,v,t", treg
, tempreg
, breg
);
2649 /* The j instruction may not be used in PIC code, since it
2650 requires an absolute address. We convert it to a b
2652 if (mips_pic
== NO_PIC
)
2653 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "j", "a");
2655 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "b", "p");
2658 /* The jal instructions must be handled as macros because when
2659 generating PIC code they expand to multi-instruction
2660 sequences. Normally they are simple instructions. */
2665 if (mips_pic
== NO_PIC
2666 || mips_pic
== EMBEDDED_PIC
)
2667 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "jalr",
2669 else if (mips_pic
== SVR4_PIC
)
2671 if (sreg
!= PIC_CALL_REG
)
2672 as_warn ("MIPS PIC call to register other than $25");
2674 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "jalr",
2676 if (mips_cprestore_offset
< 0)
2677 as_warn ("No .cprestore pseudo-op used in PIC code");
2680 expr1
.X_add_number
= mips_cprestore_offset
;
2681 macro_build ((char *) NULL
, &icnt
, &expr1
,
2682 mips_isa
< 3 ? "lw" : "ld",
2683 "t,o(b)", GP
, (int) BFD_RELOC_LO16
, mips_frame_reg
);
2692 if (mips_pic
== NO_PIC
)
2693 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "jal", "a");
2694 else if (mips_pic
== SVR4_PIC
)
2696 /* If this is a reference to an external symbol, we want
2697 lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
2701 lw $gp,cprestore($sp)
2702 The cprestore value is set using the .cprestore
2703 pseudo-op. If the symbol is not external, we want
2704 lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
2706 addiu $25,$25,<sym> (BFD_RELOC_LO16)
2709 lw $gp,cprestore($sp)
2712 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2713 mips_isa
< 3 ? "lw" : "ld",
2714 "t,o(b)", PIC_CALL_REG
,
2715 (int) BFD_RELOC_MIPS_CALL16
, GP
);
2716 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
2717 p
= frag_var (rs_machine_dependent
, 4, 0,
2718 RELAX_ENCODE (0, 4, -8, 0, 0, 0),
2719 offset_expr
.X_add_symbol
, (long) 0, (char *) NULL
);
2720 macro_build (p
, &icnt
, &offset_expr
,
2721 mips_isa
< 3 ? "addiu" : "daddiu",
2722 "t,r,j", PIC_CALL_REG
, PIC_CALL_REG
,
2723 (int) BFD_RELOC_LO16
);
2724 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
2725 "jalr", "s", PIC_CALL_REG
);
2726 if (mips_cprestore_offset
< 0)
2727 as_warn ("No .cprestore pseudo-op used in PIC code");
2731 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
2733 expr1
.X_add_number
= mips_cprestore_offset
;
2734 macro_build ((char *) NULL
, &icnt
, &expr1
,
2735 mips_isa
< 3 ? "lw" : "ld",
2736 "t,o(b)", GP
, (int) BFD_RELOC_LO16
,
2740 else if (mips_pic
== EMBEDDED_PIC
)
2742 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "bal", "p");
2743 /* The linker may expand the call to a longer sequence which
2744 uses $at, so we must break rather than return. */
2816 if (breg
== treg
|| coproc
)
2885 if (mask
== M_LWC1_AB
2886 || mask
== M_SWC1_AB
2887 || mask
== M_LDC1_AB
2888 || mask
== M_SDC1_AB
2897 if (offset_expr
.X_op
!= O_constant
2898 && offset_expr
.X_op
!= O_symbol
)
2900 as_bad ("expression too complex");
2901 offset_expr
.X_op
= O_constant
;
2904 /* A constant expression in PIC code can be handled just as it
2905 is in non PIC code. */
2906 if (mips_pic
== NO_PIC
2907 || offset_expr
.X_op
== O_constant
)
2909 /* If this is a reference to a GP relative symbol, and there
2910 is no base register, we want
2911 <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL)
2912 Otherwise, if there is no base register, we want
2913 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
2914 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
2915 If we have a constant, we need two instructions anyhow,
2916 so we always use the latter form.
2918 If we have a base register, and this is a reference to a
2919 GP relative symbol, we want
2920 addu $tempreg,$breg,$gp
2921 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GPREL)
2923 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
2924 addu $tempreg,$tempreg,$breg
2925 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
2926 With a constant we always use the latter case. */
2929 if (offset_expr
.X_add_number
!= 0)
2934 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
2935 treg
, (int) BFD_RELOC_MIPS_GPREL
, GP
);
2936 p
= frag_var (rs_machine_dependent
, 8, 0,
2937 RELAX_ENCODE (4, 8, 0, 4, 0,
2938 (mips_warn_about_macros
2939 || (used_at
&& mips_noat
))),
2940 offset_expr
.X_add_symbol
, (long) 0,
2944 macro_build_lui (p
, &icnt
, &offset_expr
, tempreg
);
2947 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
, treg
,
2948 (int) BFD_RELOC_LO16
, tempreg
);
2952 if (offset_expr
.X_add_number
!= 0)
2957 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
2958 mips_isa
< 3 ? "addu" : "daddu",
2959 "d,v,t", tempreg
, breg
, GP
);
2960 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
2961 treg
, (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
2962 p
= frag_var (rs_machine_dependent
, 12, 0,
2963 RELAX_ENCODE (8, 12, 0, 8, 0, 0),
2964 offset_expr
.X_add_symbol
, (long) 0,
2967 macro_build_lui (p
, &icnt
, &offset_expr
, tempreg
);
2970 macro_build (p
, &icnt
, (expressionS
*) NULL
,
2971 mips_isa
< 3 ? "addu" : "daddu",
2972 "d,v,t", tempreg
, tempreg
, breg
);
2975 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
, treg
,
2976 (int) BFD_RELOC_LO16
, tempreg
);
2979 else if (mips_pic
== SVR4_PIC
)
2981 /* If this is a reference to an external symbol, we want
2982 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
2984 <op> $treg,0($tempreg)
2986 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
2988 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
2989 <op> $treg,0($tempreg)
2990 If there is a base register, we add it to $tempreg before
2991 the <op>. If there is a constant, we stick it in the
2992 <op> instruction. We don't handle constants larger than
2993 16 bits, because we have no way to load the upper 16 bits
2994 (actually, we could handle them for the subset of cases
2995 in which we are not using $at). */
2996 assert (offset_expr
.X_op
== O_symbol
);
2997 expr1
.X_add_number
= offset_expr
.X_add_number
;
2998 offset_expr
.X_add_number
= 0;
2999 if (expr1
.X_add_number
< -0x8000
3000 || expr1
.X_add_number
>= 0x8000)
3001 as_bad ("PIC code offset overflow (max 16 signed bits)");
3003 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3004 mips_isa
< 3 ? "lw" : "ld",
3005 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
3006 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
3007 p
= frag_var (rs_machine_dependent
, 4, 0,
3008 RELAX_ENCODE (0, 4, -8, 0, 0, 0),
3009 offset_expr
.X_add_symbol
, (long) 0,
3011 macro_build (p
, &icnt
, &offset_expr
,
3012 mips_isa
< 3 ? "addiu" : "daddiu",
3013 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
3015 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3016 mips_isa
< 3 ? "addu" : "daddu",
3017 "d,v,t", tempreg
, tempreg
, breg
);
3018 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
, treg
,
3019 (int) BFD_RELOC_LO16
, tempreg
);
3021 else if (mips_pic
== EMBEDDED_PIC
)
3023 /* If there is no base register, we want
3024 <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL)
3025 If there is a base register, we want
3026 addu $tempreg,$breg,$gp
3027 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GPREL)
3029 assert (offset_expr
.X_op
== O_symbol
);
3032 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
3033 treg
, (int) BFD_RELOC_MIPS_GPREL
, GP
);
3038 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3039 mips_isa
< 3 ? "addu" : "daddu",
3040 "d,v,t", tempreg
, breg
, GP
);
3041 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
3042 treg
, (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
3055 load_register (&icnt
, treg
, &imm_expr
);
3059 if (imm_expr
.X_op
== O_constant
)
3061 load_register (&icnt
, AT
, &imm_expr
);
3062 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3063 "mtc1", "t,G", AT
, treg
);
3068 assert (offset_expr
.X_op
== O_symbol
3069 && strcmp (segment_name (S_GET_SEGMENT
3070 (offset_expr
.X_add_symbol
)),
3072 && offset_expr
.X_add_number
== 0);
3073 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lwc1", "T,o(b)",
3074 treg
, (int) BFD_RELOC_MIPS_LITERAL
, GP
);
3079 /* We know that sym is in the .rdata section. First we get the
3080 upper 16 bits of the address. */
3081 if (mips_pic
== NO_PIC
)
3083 /* FIXME: This won't work for a 64 bit address. */
3084 macro_build_lui ((char *) NULL
, &icnt
, &offset_expr
, AT
);
3086 else if (mips_pic
== SVR4_PIC
)
3088 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3089 mips_isa
< 3 ? "lw" : "ld",
3090 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
3092 else if (mips_pic
== EMBEDDED_PIC
)
3094 /* For embedded PIC we pick up the entire address off $gp in
3095 a single instruction. */
3096 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3097 mips_isa
< 3 ? "addiu" : "daddiu",
3098 "t,r,j", AT
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
3099 offset_expr
.X_op
= O_constant
;
3100 offset_expr
.X_add_number
= 0;
3105 /* Now we load the register(s). */
3107 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "ld", "t,o(b)",
3108 treg
, (int) BFD_RELOC_LO16
, AT
);
3111 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lw", "t,o(b)",
3112 treg
, (int) BFD_RELOC_LO16
, AT
);
3115 /* FIXME: How in the world do we deal with the possible
3117 offset_expr
.X_add_number
+= 4;
3118 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lw", "t,o(b)",
3119 treg
+ 1, (int) BFD_RELOC_LO16
, AT
);
3123 /* To avoid confusion in tc_gen_reloc, we must ensure that this
3124 does not become a variant frag. */
3125 frag_wane (frag_now
);
3131 assert (offset_expr
.X_op
== O_symbol
3132 && offset_expr
.X_add_number
== 0);
3133 s
= segment_name (S_GET_SEGMENT (offset_expr
.X_add_symbol
));
3134 if (strcmp (s
, ".lit8") == 0)
3138 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "ldc1",
3139 "T,o(b)", treg
, (int) BFD_RELOC_MIPS_LITERAL
, GP
);
3143 r
= BFD_RELOC_MIPS_LITERAL
;
3148 assert (strcmp (s
, RDATA_SECTION_NAME
) == 0);
3149 if (mips_pic
== SVR4_PIC
)
3150 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3151 mips_isa
< 3 ? "lw" : "ld",
3152 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
3155 /* FIXME: This won't work for a 64 bit address. */
3156 macro_build_lui ((char *) NULL
, &icnt
, &offset_expr
, AT
);
3161 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "ldc1",
3162 "T,o(b)", treg
, (int) BFD_RELOC_LO16
, AT
);
3171 /* Even on a big endian machine $fn comes before $fn+1. We have
3172 to adjust when loading from memory. */
3175 assert (mips_isa
< 2);
3176 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lwc1", "T,o(b)",
3177 byte_order
== LITTLE_ENDIAN
? treg
: treg
+ 1,
3179 /* FIXME: A possible overflow which I don't know how to deal
3181 offset_expr
.X_add_number
+= 4;
3182 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lwc1", "T,o(b)",
3183 byte_order
== LITTLE_ENDIAN
? treg
+ 1 : treg
,
3186 /* To avoid confusion in tc_gen_reloc, we must ensure that this
3187 does not become a variant frag. */
3188 frag_wane (frag_now
);
3197 * The MIPS assembler seems to check for X_add_number not
3198 * being double aligned and generating:
3201 * addiu at,at,%lo(foo+1)
3204 * But, the resulting address is the same after relocation so why
3205 * generate the extra instruction?
3252 if (offset_expr
.X_op
!= O_symbol
3253 && offset_expr
.X_op
!= O_constant
)
3255 as_bad ("expression too complex");
3256 offset_expr
.X_op
= O_constant
;
3259 /* Even on a big endian machine $fn comes before $fn+1. We have
3260 to adjust when loading from memory. We set coproc if we must
3261 load $fn+1 first. */
3262 if (byte_order
== LITTLE_ENDIAN
)
3265 if (mips_pic
== NO_PIC
3266 || offset_expr
.X_op
== O_constant
)
3268 /* If this is a reference to a GP relative symbol, we want
3269 <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL)
3270 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_MIPS_GPREL)
3271 If we have a base register, we use this
3273 <op> $treg,<sym>($at) (BFD_RELOC_MIPS_GPREL)
3274 <op> $treg+1,<sym>+4($at) (BFD_RELOC_MIPS_GPREL)
3275 If this is not a GP relative symbol, we want
3276 lui $at,<sym> (BFD_RELOC_HI16_S)
3277 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
3278 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
3279 If there is a base register, we add it to $at after the
3280 lui instruction. If there is a constant, we always use
3282 if (offset_expr
.X_add_number
!= 0)
3301 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3302 mips_isa
< 3 ? "addu" : "daddu",
3303 "d,v,t", AT
, breg
, GP
);
3309 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
3310 coproc
? treg
+ 1 : treg
,
3311 (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
3312 offset_expr
.X_add_number
+= 4;
3314 /* Set mips_optimize to 2 to avoid inserting an
3316 hold_mips_optimize
= mips_optimize
;
3318 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
3319 coproc
? treg
: treg
+ 1,
3320 (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
3321 mips_optimize
= hold_mips_optimize
;
3323 p
= frag_var (rs_machine_dependent
, 12 + off
, 0,
3324 RELAX_ENCODE (8 + off
, 12 + off
, 0, 4 + off
, 1,
3325 used_at
&& mips_noat
),
3326 offset_expr
.X_add_symbol
, (long) 0,
3329 /* We just generated two relocs. When tc_gen_reloc
3330 handles this case, it will skip the first reloc and
3331 handle the second. The second reloc already has an
3332 extra addend of 4, which we added above. We must
3333 subtract it out, and then subtract another 4 to make
3334 the first reloc come out right. The second reloc
3335 will come out right because we are going to add 4 to
3336 offset_expr when we build its instruction below. */
3337 offset_expr
.X_add_number
-= 8;
3338 offset_expr
.X_op
= O_constant
;
3340 macro_build_lui (p
, &icnt
, &offset_expr
, AT
);
3345 macro_build (p
, &icnt
, (expressionS
*) NULL
,
3346 mips_isa
< 3 ? "addu" : "daddu",
3347 "d,v,t", AT
, breg
, AT
);
3351 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
,
3352 coproc
? treg
+ 1 : treg
,
3353 (int) BFD_RELOC_LO16
, AT
);
3356 /* FIXME: How do we handle overflow here? */
3357 offset_expr
.X_add_number
+= 4;
3358 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
,
3359 coproc
? treg
: treg
+ 1,
3360 (int) BFD_RELOC_LO16
, AT
);
3362 else if (mips_pic
== SVR4_PIC
)
3366 /* If this is a reference to an external symbol, we want
3367 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3372 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3374 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
3375 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
3376 If there is a base register we add it to $at before the
3377 lwc1 instructions. If there is a constant we include it
3378 in the lwc1 instructions. */
3380 expr1
.X_add_number
= offset_expr
.X_add_number
;
3381 offset_expr
.X_add_number
= 0;
3382 if (expr1
.X_add_number
< -0x8000
3383 || expr1
.X_add_number
>= 0x8000 - 4)
3384 as_bad ("PIC code offset overflow (max 16 signed bits)");
3389 frag_grow (24 + off
);
3390 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3391 mips_isa
< 3 ? "lw" : "ld",
3392 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
3393 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
3395 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3396 mips_isa
< 3 ? "addu" : "daddu",
3397 "d,v,t", AT
, breg
, AT
);
3398 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
3399 coproc
? treg
+ 1 : treg
,
3400 (int) BFD_RELOC_LO16
, AT
);
3401 expr1
.X_add_number
+= 4;
3403 /* Set mips_optimize to 2 to avoid inserting an undesired
3405 hold_mips_optimize
= mips_optimize
;
3407 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
3408 coproc
? treg
: treg
+ 1,
3409 (int) BFD_RELOC_LO16
, AT
);
3410 mips_optimize
= hold_mips_optimize
;
3412 (void) frag_var (rs_machine_dependent
, 0, 0,
3413 RELAX_ENCODE (0, 0, -16 - off
, -8, 1, 0),
3414 offset_expr
.X_add_symbol
, (long) 0,
3417 else if (mips_pic
== EMBEDDED_PIC
)
3419 /* If there is no base register, we use
3420 <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL)
3421 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_MIPS_GPREL)
3422 If we have a base register, we use
3424 <op> $treg,<sym>($at) (BFD_RELOC_MIPS_GPREL)
3425 <op> $treg+1,<sym>+4($at) (BFD_RELOC_MIPS_GPREL)
3434 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3435 mips_isa
< 3 ? "addu" : "daddu",
3436 "d,v,t", AT
, breg
, GP
);
3441 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
3442 coproc
? treg
+ 1 : treg
,
3443 (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
3444 offset_expr
.X_add_number
+= 4;
3445 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
3446 coproc
? treg
: treg
+ 1,
3447 (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
3463 assert (mips_isa
< 3);
3464 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
3465 (int) BFD_RELOC_LO16
, breg
);
3466 offset_expr
.X_add_number
+= 4;
3467 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
+ 1,
3468 (int) BFD_RELOC_LO16
, breg
);
3470 #ifdef LOSING_COMPILER
3476 as_warn ("Macro used $at after \".set noat\"");
3481 struct mips_cl_insn
*ip
;
3483 register int treg
, sreg
, dreg
, breg
;
3496 bfd_reloc_code_real_type r
;
3499 treg
= (ip
->insn_opcode
>> 16) & 0x1f;
3500 dreg
= (ip
->insn_opcode
>> 11) & 0x1f;
3501 sreg
= breg
= (ip
->insn_opcode
>> 21) & 0x1f;
3502 mask
= ip
->insn_mo
->mask
;
3504 expr1
.X_op
= O_constant
;
3505 expr1
.X_op_symbol
= NULL
;
3506 expr1
.X_add_symbol
= NULL
;
3507 expr1
.X_add_number
= 1;
3511 #endif /* LOSING_COMPILER */
3516 macro_build ((char *) NULL
, &icnt
, NULL
,
3517 dbl
? "dmultu" : "multu",
3519 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
3525 /* The MIPS assembler some times generates shifts and adds. I'm
3526 not trying to be that fancy. GCC should do this for us
3528 load_register (&icnt
, AT
, &imm_expr
);
3529 macro_build ((char *) NULL
, &icnt
, NULL
,
3530 dbl
? "dmult" : "mult",
3532 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
3538 mips_emit_delays ();
3540 mips_any_noreorder
= 1;
3541 macro_build ((char *) NULL
, &icnt
, NULL
,
3542 dbl
? "dmult" : "mult",
3544 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
3545 macro_build ((char *) NULL
, &icnt
, NULL
,
3546 dbl
? "dsra32" : "sra",
3547 "d,w,<", dreg
, dreg
, 31);
3548 macro_build ((char *) NULL
, &icnt
, NULL
, "mfhi", "d", AT
);
3550 macro_build ((char *) NULL
, &icnt
, NULL
, "tne", "s,t", dreg
, AT
);
3553 expr1
.X_add_number
= 8;
3554 macro_build ((char *) NULL
, &icnt
, &expr1
, "beq", "s,t,p", dreg
, AT
);
3555 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
3556 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 6);
3559 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
3565 mips_emit_delays ();
3567 mips_any_noreorder
= 1;
3568 macro_build ((char *) NULL
, &icnt
, NULL
,
3569 dbl
? "dmultu" : "multu",
3571 macro_build ((char *) NULL
, &icnt
, NULL
, "mfhi", "d", AT
);
3572 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
3574 macro_build ((char *) NULL
, &icnt
, NULL
, "tne", "s,t", AT
, 0);
3577 expr1
.X_add_number
= 8;
3578 macro_build ((char *) NULL
, &icnt
, &expr1
, "beq", "s,t,p", AT
, 0);
3579 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
3580 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 6);
3586 macro_build ((char *) NULL
, &icnt
, NULL
, "subu", "d,v,t", AT
, 0, treg
);
3587 macro_build ((char *) NULL
, &icnt
, NULL
, "srlv", "d,t,s", AT
, sreg
, AT
);
3588 macro_build ((char *) NULL
, &icnt
, NULL
, "sllv", "d,t,s", dreg
, sreg
,
3590 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
3594 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", AT
, sreg
,
3595 imm_expr
.X_add_number
& 0x1f);
3596 macro_build ((char *) NULL
, &icnt
, NULL
, "srl", "d,w,<", dreg
, sreg
,
3597 (0 - imm_expr
.X_add_number
) & 0x1f);
3598 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
3602 macro_build ((char *) NULL
, &icnt
, NULL
, "subu", "d,v,t", AT
, 0, treg
);
3603 macro_build ((char *) NULL
, &icnt
, NULL
, "sllv", "d,t,s", AT
, sreg
, AT
);
3604 macro_build ((char *) NULL
, &icnt
, NULL
, "srlv", "d,t,s", dreg
, sreg
,
3606 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
3610 macro_build ((char *) NULL
, &icnt
, NULL
, "srl", "d,w,<", AT
, sreg
,
3611 imm_expr
.X_add_number
& 0x1f);
3612 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", dreg
, sreg
,
3613 (0 - imm_expr
.X_add_number
) & 0x1f);
3614 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
3618 assert (mips_isa
< 2);
3619 /* Even on a big endian machine $fn comes before $fn+1. We have
3620 to adjust when storing to memory. */
3621 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "swc1", "T,o(b)",
3622 byte_order
== LITTLE_ENDIAN
? treg
: treg
+ 1,
3623 (int) BFD_RELOC_LO16
, breg
);
3624 offset_expr
.X_add_number
+= 4;
3625 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "swc1", "T,o(b)",
3626 byte_order
== LITTLE_ENDIAN
? treg
+ 1 : treg
,
3627 (int) BFD_RELOC_LO16
, breg
);
3632 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
3633 treg
, (int) BFD_RELOC_LO16
);
3635 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
3636 sreg
, (int) BFD_RELOC_LO16
);
3639 macro_build ((char *) NULL
, &icnt
, NULL
, "xor", "d,v,t", dreg
,
3641 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
3642 dreg
, (int) BFD_RELOC_LO16
);
3647 if (imm_expr
.X_add_number
== 0)
3649 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
3650 sreg
, (int) BFD_RELOC_LO16
);
3655 as_warn ("Instruction %s: result is always false",
3657 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
, 0);
3660 if (imm_expr
.X_add_number
>= 0 && imm_expr
.X_add_number
< 0x10000)
3662 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "xori", "t,r,i", dreg
,
3663 sreg
, (int) BFD_RELOC_LO16
);
3666 else if (imm_expr
.X_add_number
> -0x8000 && imm_expr
.X_add_number
< 0)
3668 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
3669 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
3670 mips_isa
< 3 ? "addiu" : "daddiu",
3671 "t,r,j", dreg
, sreg
,
3672 (int) BFD_RELOC_LO16
);
3677 load_register (&icnt
, AT
, &imm_expr
);
3678 macro_build ((char *) NULL
, &icnt
, NULL
, "xor", "d,v,t", dreg
,
3682 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
, dreg
,
3683 (int) BFD_RELOC_LO16
);
3688 case M_SGE
: /* sreg >= treg <==> not (sreg < treg) */
3694 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, sreg
, treg
);
3695 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
3696 (int) BFD_RELOC_LO16
);
3699 case M_SGE_I
: /* sreg >= I <==> not (sreg < I) */
3701 if (imm_expr
.X_add_number
>= -0x8000 && imm_expr
.X_add_number
< 0x8000)
3703 macro_build ((char *) NULL
, &icnt
, &expr1
,
3704 mask
== M_SGE_I
? "slti" : "sltiu",
3705 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
3710 load_register (&icnt
, AT
, &imm_expr
);
3711 macro_build ((char *) NULL
, &icnt
, NULL
,
3712 mask
== M_SGE_I
? "slt" : "sltu",
3713 "d,v,t", dreg
, sreg
, AT
);
3716 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
3717 (int) BFD_RELOC_LO16
);
3722 case M_SGT
: /* sreg > treg <==> treg < sreg */
3728 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, treg
, sreg
);
3731 case M_SGT_I
: /* sreg > I <==> I < sreg */
3737 load_register (&icnt
, AT
, &imm_expr
);
3738 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, AT
, sreg
);
3741 case M_SLE
: /* sreg <= treg <==> treg >= sreg <==> not (treg < sreg) */
3747 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, treg
, sreg
);
3748 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
3749 (int) BFD_RELOC_LO16
);
3752 case M_SLE_I
: /* sreg <= I <==> I >= sreg <==> not (I < sreg) */
3758 load_register (&icnt
, AT
, &imm_expr
);
3759 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, AT
, sreg
);
3760 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
3761 (int) BFD_RELOC_LO16
);
3765 if (imm_expr
.X_add_number
>= -0x8000 && imm_expr
.X_add_number
< 0x8000)
3767 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "slti", "t,r,j",
3768 dreg
, sreg
, (int) BFD_RELOC_LO16
);
3771 load_register (&icnt
, AT
, &imm_expr
);
3772 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", dreg
, sreg
, AT
);
3776 if (imm_expr
.X_add_number
>= -0x8000 && imm_expr
.X_add_number
< 0x8000)
3778 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "sltiu", "t,r,j",
3779 dreg
, sreg
, (int) BFD_RELOC_LO16
);
3782 load_register (&icnt
, AT
, &imm_expr
);
3783 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, sreg
,
3789 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0,
3792 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0,
3796 macro_build ((char *) NULL
, &icnt
, NULL
, "xor", "d,v,t", dreg
,
3798 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0,
3804 if (imm_expr
.X_add_number
== 0)
3806 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0,
3812 as_warn ("Instruction %s: result is always true",
3814 macro_build ((char *) NULL
, &icnt
, &expr1
,
3815 mips_isa
< 3 ? "addiu" : "daddiu",
3816 "t,r,j", dreg
, 0, (int) BFD_RELOC_LO16
);
3819 if (imm_expr
.X_add_number
>= 0 && imm_expr
.X_add_number
< 0x10000)
3821 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "xori", "t,r,i",
3822 dreg
, sreg
, (int) BFD_RELOC_LO16
);
3825 else if (imm_expr
.X_add_number
> -0x8000 && imm_expr
.X_add_number
< 0)
3827 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
3828 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
3829 mips_isa
< 3 ? "addiu" : "daddiu",
3830 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
3835 load_register (&icnt
, AT
, &imm_expr
);
3836 macro_build ((char *) NULL
, &icnt
, NULL
, "xor", "d,v,t", dreg
,
3840 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0, dreg
);
3848 if (imm_expr
.X_add_number
> -0x8000 && imm_expr
.X_add_number
<= 0x8000)
3850 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
3851 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
3852 dbl
? "daddi" : "addi",
3853 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
3856 load_register (&icnt
, AT
, &imm_expr
);
3857 macro_build ((char *) NULL
, &icnt
, NULL
,
3858 dbl
? "dsub" : "sub",
3859 "d,v,t", dreg
, sreg
, AT
);
3865 if (imm_expr
.X_add_number
> -0x8000 && imm_expr
.X_add_number
<= 0x8000)
3867 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
3868 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
3869 dbl
? "daddiu" : "addiu",
3870 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
3873 load_register (&icnt
, AT
, &imm_expr
);
3874 macro_build ((char *) NULL
, &icnt
, NULL
,
3875 dbl
? "dsubu" : "subu",
3876 "d,v,t", dreg
, sreg
, AT
);
3897 load_register (&icnt
, AT
, &imm_expr
);
3898 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "s,t", sreg
, AT
);
3903 assert (mips_isa
< 2);
3904 sreg
= (ip
->insn_opcode
>> 11) & 0x1f; /* floating reg */
3905 dreg
= (ip
->insn_opcode
>> 06) & 0x1f; /* floating reg */
3908 * Is the double cfc1 instruction a bug in the mips assembler;
3909 * or is there a reason for it?
3911 mips_emit_delays ();
3913 mips_any_noreorder
= 1;
3914 macro_build ((char *) NULL
, &icnt
, NULL
, "cfc1", "t,G", treg
, 31);
3915 macro_build ((char *) NULL
, &icnt
, NULL
, "cfc1", "t,G", treg
, 31);
3916 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "");
3917 expr1
.X_add_number
= 3;
3918 macro_build ((char *) NULL
, &icnt
, &expr1
, "ori", "t,r,i", AT
, treg
,
3919 (int) BFD_RELOC_LO16
);
3920 expr1
.X_add_number
= 2;
3921 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", AT
, AT
,
3922 (int) BFD_RELOC_LO16
);
3923 macro_build ((char *) NULL
, &icnt
, NULL
, "ctc1", "t,G", AT
, 31);
3924 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "");
3925 macro_build ((char *) NULL
, &icnt
, NULL
,
3926 mask
== M_TRUNCWD
? "cvt.w.d" : "cvt.w.s", "D,S", dreg
, sreg
);
3927 macro_build ((char *) NULL
, &icnt
, NULL
, "ctc1", "t,G", treg
, 31);
3928 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "");
3938 if (offset_expr
.X_add_number
>= 0x7fff)
3939 as_bad ("operand overflow");
3940 /* avoid load delay */
3941 if (byte_order
== LITTLE_ENDIAN
)
3942 offset_expr
.X_add_number
+= 1;
3943 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
3944 (int) BFD_RELOC_LO16
, breg
);
3945 if (byte_order
== LITTLE_ENDIAN
)
3946 offset_expr
.X_add_number
-= 1;
3948 offset_expr
.X_add_number
+= 1;
3949 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lbu", "t,o(b)", AT
,
3950 (int) BFD_RELOC_LO16
, breg
);
3951 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", treg
, treg
, 8);
3952 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", treg
, treg
, AT
);
3956 if (offset_expr
.X_add_number
>= 0x7ffd)
3957 as_bad ("operand overflow");
3958 if (byte_order
== LITTLE_ENDIAN
)
3959 offset_expr
.X_add_number
+= 3;
3960 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lwl", "t,o(b)", treg
,
3961 (int) BFD_RELOC_LO16
, breg
);
3962 if (byte_order
== LITTLE_ENDIAN
)
3963 offset_expr
.X_add_number
-= 3;
3965 offset_expr
.X_add_number
+= 3;
3966 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lwr", "t,o(b)", treg
,
3967 (int) BFD_RELOC_LO16
, breg
);
3973 load_address (&icnt
, AT
, &offset_expr
);
3974 if (mask
== M_ULW_A
)
3976 if (byte_order
== LITTLE_ENDIAN
)
3977 expr1
.X_add_number
= 3;
3979 expr1
.X_add_number
= 0;
3980 macro_build ((char *) NULL
, &icnt
, &expr1
, "lwl", "t,o(b)", treg
,
3981 (int) BFD_RELOC_LO16
, AT
);
3982 if (byte_order
== LITTLE_ENDIAN
)
3983 expr1
.X_add_number
= 0;
3985 expr1
.X_add_number
= 3;
3986 macro_build ((char *) NULL
, &icnt
, &expr1
, "lwr", "t,o(b)", treg
,
3987 (int) BFD_RELOC_LO16
, AT
);
3991 if (byte_order
== BIG_ENDIAN
)
3992 expr1
.X_add_number
= 0;
3993 macro_build ((char *) NULL
, &icnt
, &expr1
,
3994 mask
== M_ULH_A
? "lb" : "lbu", "t,o(b)", treg
,
3995 (int) BFD_RELOC_LO16
, AT
);
3996 if (byte_order
== BIG_ENDIAN
)
3997 expr1
.X_add_number
= 1;
3999 expr1
.X_add_number
= 0;
4000 macro_build ((char *) NULL
, &icnt
, &expr1
, "lbu", "t,o(b)", AT
,
4001 (int) BFD_RELOC_LO16
, AT
);
4002 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", treg
,
4004 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", treg
,
4010 if (offset_expr
.X_add_number
>= 0x7fff)
4011 as_bad ("operand overflow");
4012 if (byte_order
== BIG_ENDIAN
)
4013 offset_expr
.X_add_number
+= 1;
4014 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "sb", "t,o(b)", treg
,
4015 (int) BFD_RELOC_LO16
, breg
);
4016 macro_build ((char *) NULL
, &icnt
, NULL
, "srl", "d,w,<", AT
, treg
, 8);
4017 if (byte_order
== BIG_ENDIAN
)
4018 offset_expr
.X_add_number
-= 1;
4020 offset_expr
.X_add_number
+= 1;
4021 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "sb", "t,o(b)", AT
,
4022 (int) BFD_RELOC_LO16
, breg
);
4026 if (offset_expr
.X_add_number
>= 0x7ffd)
4027 as_bad ("operand overflow");
4028 if (byte_order
== LITTLE_ENDIAN
)
4029 offset_expr
.X_add_number
+= 3;
4030 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "swl", "t,o(b)", treg
,
4031 (int) BFD_RELOC_LO16
, breg
);
4032 if (byte_order
== LITTLE_ENDIAN
)
4033 offset_expr
.X_add_number
-= 3;
4035 offset_expr
.X_add_number
+= 3;
4036 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "swr", "t,o(b)", treg
,
4037 (int) BFD_RELOC_LO16
, breg
);
4042 load_address (&icnt
, AT
, &offset_expr
);
4043 if (mask
== M_USW_A
)
4045 if (byte_order
== LITTLE_ENDIAN
)
4046 expr1
.X_add_number
= 3;
4048 expr1
.X_add_number
= 0;
4049 macro_build ((char *) NULL
, &icnt
, &expr1
, "swl", "t,o(b)", treg
,
4050 (int) BFD_RELOC_LO16
, AT
);
4051 if (byte_order
== LITTLE_ENDIAN
)
4052 expr1
.X_add_number
= 0;
4054 expr1
.X_add_number
= 3;
4055 macro_build ((char *) NULL
, &icnt
, &expr1
, "swr", "t,o(b)", treg
,
4056 (int) BFD_RELOC_LO16
, AT
);
4060 if (byte_order
== LITTLE_ENDIAN
)
4061 expr1
.X_add_number
= 0;
4062 macro_build ((char *) NULL
, &icnt
, &expr1
, "sb", "t,o(b)", treg
,
4063 (int) BFD_RELOC_LO16
, AT
);
4064 macro_build ((char *) NULL
, &icnt
, NULL
, "srl", "d,w,<", treg
,
4066 if (byte_order
== LITTLE_ENDIAN
)
4067 expr1
.X_add_number
= 1;
4069 expr1
.X_add_number
= 0;
4070 macro_build ((char *) NULL
, &icnt
, &expr1
, "sb", "t,o(b)", treg
,
4071 (int) BFD_RELOC_LO16
, AT
);
4072 if (byte_order
== LITTLE_ENDIAN
)
4073 expr1
.X_add_number
= 0;
4075 expr1
.X_add_number
= 1;
4076 macro_build ((char *) NULL
, &icnt
, &expr1
, "lbu", "t,o(b)", AT
,
4077 (int) BFD_RELOC_LO16
, AT
);
4078 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", treg
,
4080 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", treg
,
4086 as_bad ("Macro %s not implemented yet", ip
->insn_mo
->name
);
4090 as_warn ("Macro used $at after \".set noat\"");
4095 This routine assembles an instruction into its binary format. As a side
4096 effect it sets one of the global variables imm_reloc or offset_reloc to the
4097 type of relocation to do if one of the operands is an address expression.
4102 struct mips_cl_insn
*ip
;
4107 struct mips_opcode
*insn
;
4110 unsigned int lastregno
= 0;
4115 for (s
= str
; islower (*s
) || (*s
>= '0' && *s
<= '3') || *s
== '.'; ++s
)
4127 as_fatal ("Unknown opcode: `%s'", str
);
4129 if ((insn
= (struct mips_opcode
*) hash_find (op_hash
, str
)) == NULL
)
4131 as_warn ("`%s' not in hash table.", str
);
4132 insn_error
= "ERROR: Unrecognized opcode";
4140 assert (strcmp (insn
->name
, str
) == 0);
4142 if (insn
->pinfo
== INSN_MACRO
)
4143 insn_isa
= insn
->match
;
4144 else if (insn
->pinfo
& INSN_ISA2
)
4146 else if (insn
->pinfo
& INSN_ISA3
)
4151 if (insn_isa
> mips_isa
)
4153 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
]
4154 && strcmp (insn
->name
, insn
[1].name
) == 0)
4159 as_warn ("Instruction not supported on this processor");
4163 ip
->insn_opcode
= insn
->match
;
4164 for (args
= insn
->args
;; ++args
)
4170 case '\0': /* end of args */
4183 ip
->insn_opcode
|= lastregno
<< 21;
4188 ip
->insn_opcode
|= lastregno
<< 16;
4192 ip
->insn_opcode
|= lastregno
<< 11;
4198 /* handle optional base register.
4199 Either the base register is omitted or
4200 we must have a left paren. */
4201 /* this is dependent on the next operand specifier
4202 is a 'b' for base register */
4203 assert (args
[1] == 'b');
4207 case ')': /* these must match exactly */
4212 case '<': /* must be at least one digit */
4214 * According to the manual, if the shift amount is greater
4215 * than 31 or less than 0 the the shift amount should be
4216 * mod 32. In reality the mips assembler issues an error.
4217 * We issue a warning and mask out all but the low 5 bits.
4219 my_getExpression (&imm_expr
, s
);
4220 check_absolute_expr (ip
, &imm_expr
);
4221 if ((unsigned long) imm_expr
.X_add_number
> 31)
4223 as_warn ("Improper shift amount (%ld)",
4224 (long) imm_expr
.X_add_number
);
4225 imm_expr
.X_add_number
= imm_expr
.X_add_number
& 0x1f;
4227 ip
->insn_opcode
|= imm_expr
.X_add_number
<< 6;
4228 imm_expr
.X_op
= O_absent
;
4232 case '>': /* shift amount minus 32 */
4233 my_getExpression (&imm_expr
, s
);
4234 check_absolute_expr (ip
, &imm_expr
);
4235 if ((unsigned long) imm_expr
.X_add_number
< 32
4236 || (unsigned long) imm_expr
.X_add_number
> 63)
4238 ip
->insn_opcode
|= (imm_expr
.X_add_number
- 32) << 6;
4239 imm_expr
.X_op
= O_absent
;
4243 case 'k': /* cache code */
4244 my_getExpression (&imm_expr
, s
);
4245 check_absolute_expr (ip
, &imm_expr
);
4246 if ((unsigned long) imm_expr
.X_add_number
> 31)
4248 as_warn ("Invalid cahce opcode (%lu)",
4249 (unsigned long) imm_expr
.X_add_number
);
4250 imm_expr
.X_add_number
&= 0x1f;
4252 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_CACHE
;
4253 imm_expr
.X_op
= O_absent
;
4257 case 'c': /* break code */
4258 my_getExpression (&imm_expr
, s
);
4259 check_absolute_expr (ip
, &imm_expr
);
4260 if ((unsigned) imm_expr
.X_add_number
> 1023)
4261 as_warn ("Illegal break code (%ld)",
4262 (long) imm_expr
.X_add_number
);
4263 ip
->insn_opcode
|= imm_expr
.X_add_number
<< 16;
4264 imm_expr
.X_op
= O_absent
;
4268 case 'B': /* syscall code */
4269 my_getExpression (&imm_expr
, s
);
4270 check_absolute_expr (ip
, &imm_expr
);
4271 if ((unsigned) imm_expr
.X_add_number
> 0xfffff)
4272 as_warn ("Illegal syscall code (%ld)",
4273 (long) imm_expr
.X_add_number
);
4274 ip
->insn_opcode
|= imm_expr
.X_add_number
<< 6;
4275 imm_expr
.X_op
= O_absent
;
4279 case 'C': /* Coprocessor code */
4280 my_getExpression (&imm_expr
, s
);
4281 check_absolute_expr (ip
, &imm_expr
);
4282 if ((unsigned long) imm_expr
.X_add_number
>= (1<<25))
4284 as_warn ("Coproccesor code > 25 bits (%ld)",
4285 (long) imm_expr
.X_add_number
);
4286 imm_expr
.X_add_number
&= ((1<<25) - 1);
4288 ip
->insn_opcode
|= imm_expr
.X_add_number
;
4289 imm_expr
.X_op
= O_absent
;
4293 case 'b': /* base register */
4294 case 'd': /* destination register */
4295 case 's': /* source register */
4296 case 't': /* target register */
4297 case 'r': /* both target and source */
4298 case 'v': /* both dest and source */
4299 case 'w': /* both dest and target */
4300 case 'E': /* coprocessor target register */
4301 case 'G': /* coprocessor destination register */
4302 case 'x': /* ignore register name */
4303 case 'z': /* must be zero register */
4317 while (isdigit (*s
));
4319 as_bad ("Invalid register number (%d)", regno
);
4321 else if (*args
== 'E' || *args
== 'G')
4325 if (s
[1] == 'f' && s
[2] == 'p')
4330 else if (s
[1] == 's' && s
[2] == 'p')
4335 else if (s
[1] == 'g' && s
[2] == 'p')
4340 else if (s
[1] == 'a' && s
[2] == 't')
4348 if (regno
== AT
&& ! mips_noat
)
4349 as_warn ("Used $at without \".set noat\"");
4355 if (c
== 'r' || c
== 'v' || c
== 'w')
4362 /* 'z' only matches $0. */
4363 if (c
== 'z' && regno
!= 0)
4371 ip
->insn_opcode
|= regno
<< 21;
4375 ip
->insn_opcode
|= regno
<< 11;
4380 ip
->insn_opcode
|= regno
<< 16;
4383 /* This case exists because on the r3000 trunc
4384 expands into a macro which requires a gp
4385 register. On the r6000 or r4000 it is
4386 assembled into a single instruction which
4387 ignores the register. Thus the insn version
4388 is MIPS_ISA2 and uses 'x', and the macro
4389 version is MIPS_ISA1 and uses 't'. */
4392 /* This case is for the div instruction, which
4393 acts differently if the destination argument
4394 is $0. This only matches $0, and is checked
4395 outside the switch. */
4406 ip
->insn_opcode
|= lastregno
<< 21;
4409 ip
->insn_opcode
|= lastregno
<< 16;
4414 case 'D': /* floating point destination register */
4415 case 'S': /* floating point source register */
4416 case 'T': /* floating point target register */
4420 if (s
[0] == '$' && s
[1] == 'f' && isdigit (s
[2]))
4430 while (isdigit (*s
));
4433 as_bad ("Invalid float register number (%d)", regno
);
4435 if ((regno
& 1) != 0
4437 && ! (strcmp (str
, "mtc1") == 0 ||
4438 strcmp (str
, "mfc1") == 0 ||
4439 strcmp (str
, "lwc1") == 0 ||
4440 strcmp (str
, "swc1") == 0))
4441 as_warn ("Float register should be even, was %d",
4449 if (c
== 'V' || c
== 'W')
4459 ip
->insn_opcode
|= regno
<< 6;
4463 ip
->insn_opcode
|= regno
<< 11;
4467 ip
->insn_opcode
|= regno
<< 16;
4475 ip
->insn_opcode
|= lastregno
<< 11;
4478 ip
->insn_opcode
|= lastregno
<< 16;
4484 my_getExpression (&imm_expr
, s
);
4485 check_absolute_expr (ip
, &imm_expr
);
4490 my_getExpression (&offset_expr
, s
);
4491 imm_reloc
= BFD_RELOC_32
;
4503 unsigned char temp
[8];
4505 unsigned int length
;
4510 /* These only appear as the last operand in an
4511 instruction, and every instruction that accepts
4512 them in any variant accepts them in all variants.
4513 This means we don't have to worry about backing out
4514 any changes if the instruction does not match.
4516 The difference between them is the size of the
4517 floating point constant and where it goes. For 'F'
4518 and 'L' the constant is 64 bits; for 'f' and 'l' it
4519 is 32 bits. Where the constant is placed is based
4520 on how the MIPS assembler does things:
4523 f -- immediate value
4526 The .lit4 and .lit8 sections are only used if
4527 permitted by the -G argument.
4529 When generating embedded PIC code, we use the
4530 .lit8 section but not the .lit4 section (we can do
4531 .lit4 inline easily; we need to put .lit8
4532 somewhere in the data segment, and using .lit8
4533 permits the linker to eventually combine identical
4536 f64
= *args
== 'F' || *args
== 'L';
4538 save_in
= input_line_pointer
;
4539 input_line_pointer
= s
;
4540 err
= md_atof (f64
? 'd' : 'f', (char *) temp
, &len
);
4542 s
= input_line_pointer
;
4543 input_line_pointer
= save_in
;
4544 if (err
!= NULL
&& *err
!= '\0')
4546 as_bad ("Bad floating point constant: %s", err
);
4547 memset (temp
, '\0', sizeof temp
);
4548 length
= f64
? 8 : 4;
4551 assert (length
== (f64
? 8 : 4));
4555 && (mips_pic
== EMBEDDED_PIC
4557 || g_switch_value
< 4
4561 imm_expr
.X_op
= O_constant
;
4562 if (byte_order
== LITTLE_ENDIAN
)
4563 imm_expr
.X_add_number
=
4564 (((((((int) temp
[3] << 8)
4569 imm_expr
.X_add_number
=
4570 (((((((int) temp
[0] << 8)
4577 const char *newname
;
4580 /* Switch to the right section. */
4582 subseg
= now_subseg
;
4585 default: /* unused default case avoids warnings. */
4589 if (g_switch_value
< 8)
4590 newname
= RDATA_SECTION_NAME
;
4594 newname
= RDATA_SECTION_NAME
;
4598 assert (g_switch_value
>= 4);
4603 new_seg
= subseg_new (newname
, (subsegT
) 0);
4604 frag_align (*args
== 'l' ? 2 : 3, 0);
4606 record_alignment (new_seg
, 4);
4608 record_alignment (new_seg
, *args
== 'l' ? 2 : 3);
4611 as_bad ("Can't use floating point insn in this section");
4613 /* Set the argument to the current address in the
4615 offset_expr
.X_op
= O_symbol
;
4616 offset_expr
.X_add_symbol
=
4617 symbol_new ("L0\001", now_seg
,
4618 (valueT
) frag_now_fix (), frag_now
);
4619 offset_expr
.X_add_number
= 0;
4621 /* Put the floating point number into the section. */
4622 p
= frag_more ((int) length
);
4623 memcpy (p
, temp
, length
);
4625 /* Switch back to the original section. */
4626 subseg_set (seg
, subseg
);
4631 case 'i': /* 16 bit unsigned immediate */
4632 case 'j': /* 16 bit signed immediate */
4633 imm_reloc
= BFD_RELOC_LO16
;
4634 c
= my_getSmallExpression (&imm_expr
, s
);
4639 if (imm_expr
.X_op
== O_constant
)
4640 imm_expr
.X_add_number
=
4641 (imm_expr
.X_add_number
>> 16) & 0xffff;
4643 imm_reloc
= BFD_RELOC_HI16_S
;
4645 imm_reloc
= BFD_RELOC_HI16
;
4649 check_absolute_expr (ip
, &imm_expr
);
4652 if (imm_expr
.X_add_number
< 0
4653 || imm_expr
.X_add_number
>= 0x10000)
4655 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
4656 !strcmp (insn
->name
, insn
[1].name
))
4658 as_bad ("16 bit expression not in range 0..65535");
4666 /* The upper bound should be 0x8000, but
4667 unfortunately the MIPS assembler accepts numbers
4668 from 0x8000 to 0xffff and sign extends them, and
4669 we want to be compatible. We only permit this
4670 extended range for an instruction which does not
4671 provide any further alternates, since those
4672 alternates may handle other cases. People should
4673 use the numbers they mean, rather than relying on
4674 a mysterious sign extension. */
4675 more
= (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
4676 strcmp (insn
->name
, insn
[1].name
) == 0);
4681 if (imm_expr
.X_add_number
< -0x8000 ||
4682 imm_expr
.X_add_number
>= max
)
4686 as_bad ("16 bit expression not in range -32768..32767");
4692 case 'o': /* 16 bit offset */
4693 c
= my_getSmallExpression (&offset_expr
, s
);
4695 /* If this value won't fit into a 16 bit offset, then go
4696 find a macro that will generate the 32 bit offset
4697 code pattern. As a special hack, we accept the
4698 difference of two local symbols as a constant. This
4699 is required to suppose embedded PIC switches, which
4700 use an instruction which looks like
4701 lw $4,$L12-$LS12($4)
4702 The problem with handling this in a more general
4703 fashion is that the macro function doesn't expect to
4704 see anything which can be handled in a single
4705 constant instruction. */
4707 && (offset_expr
.X_op
!= O_constant
4708 || offset_expr
.X_add_number
>= 0x8000
4709 || offset_expr
.X_add_number
< -0x8000)
4710 && (mips_pic
!= EMBEDDED_PIC
4711 || offset_expr
.X_op
!= O_subtract
4712 || now_seg
!= text_section
4713 || (S_GET_SEGMENT (offset_expr
.X_op_symbol
)
4717 offset_reloc
= BFD_RELOC_LO16
;
4718 if (c
== 'h' || c
== 'H')
4720 assert (offset_expr
.X_op
== O_constant
);
4721 offset_expr
.X_add_number
=
4722 (offset_expr
.X_add_number
>> 16) & 0xffff;
4727 case 'p': /* pc relative offset */
4728 offset_reloc
= BFD_RELOC_16_PCREL_S2
;
4729 my_getExpression (&offset_expr
, s
);
4733 case 'u': /* upper 16 bits */
4734 c
= my_getSmallExpression (&imm_expr
, s
);
4735 if (imm_expr
.X_op
== O_constant
4736 && (imm_expr
.X_add_number
< 0
4737 || imm_expr
.X_add_number
>= 0x10000))
4738 as_bad ("lui expression not in range 0..65535");
4739 imm_reloc
= BFD_RELOC_LO16
;
4744 if (imm_expr
.X_op
== O_constant
)
4745 imm_expr
.X_add_number
=
4746 (imm_expr
.X_add_number
>> 16) & 0xffff;
4748 imm_reloc
= BFD_RELOC_HI16_S
;
4750 imm_reloc
= BFD_RELOC_HI16
;
4756 case 'a': /* 26 bit address */
4757 my_getExpression (&offset_expr
, s
);
4759 offset_reloc
= BFD_RELOC_MIPS_JMP
;
4763 fprintf (stderr
, "bad char = '%c'\n", *args
);
4768 /* Args don't match. */
4769 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
4770 !strcmp (insn
->name
, insn
[1].name
))
4776 insn_error
= "ERROR: Illegal operands";
4785 my_getSmallExpression (ep
, str
)
4796 ((str
[1] == 'h' && str
[2] == 'i')
4797 || (str
[1] == 'H' && str
[2] == 'I')
4798 || (str
[1] == 'l' && str
[2] == 'o'))
4810 * A small expression may be followed by a base register.
4811 * Scan to the end of this operand, and then back over a possible
4812 * base register. Then scan the small expression up to that
4813 * point. (Based on code in sparc.c...)
4815 for (sp
= str
; *sp
&& *sp
!= ','; sp
++)
4817 if (sp
- 4 >= str
&& sp
[-1] == RP
)
4819 if (isdigit (sp
[-2]))
4821 for (sp
-= 3; sp
>= str
&& isdigit (*sp
); sp
--)
4823 if (*sp
== '$' && sp
> str
&& sp
[-1] == LP
)
4829 else if (sp
- 5 >= str
4832 && ((sp
[-3] == 'f' && sp
[-2] == 'p')
4833 || (sp
[-3] == 's' && sp
[-2] == 'p')
4834 || (sp
[-3] == 'g' && sp
[-2] == 'p')
4835 || (sp
[-3] == 'a' && sp
[-2] == 't')))
4841 /* no expression means zero offset */
4844 /* %xx(reg) is an error */
4845 ep
->X_op
= O_absent
;
4850 ep
->X_op
= O_constant
;
4853 ep
->X_add_symbol
= NULL
;
4854 ep
->X_op_symbol
= NULL
;
4855 ep
->X_add_number
= 0;
4860 my_getExpression (ep
, str
);
4867 my_getExpression (ep
, str
);
4868 return c
; /* => %hi or %lo encountered */
4872 my_getExpression (ep
, str
)
4878 save_in
= input_line_pointer
;
4879 input_line_pointer
= str
;
4881 expr_end
= input_line_pointer
;
4882 input_line_pointer
= save_in
;
4885 /* Turn a string in input_line_pointer into a floating point constant
4886 of type type, and store the appropriate bytes in *litP. The number
4887 of LITTLENUMS emitted is stored in *sizeP . An error message is
4888 returned, or NULL on OK. */
4891 md_atof (type
, litP
, sizeP
)
4897 LITTLENUM_TYPE words
[4];
4913 return "bad call to md_atof";
4916 t
= atof_ieee (input_line_pointer
, type
, words
);
4918 input_line_pointer
= t
;
4922 if (byte_order
== LITTLE_ENDIAN
)
4924 for (i
= prec
- 1; i
>= 0; i
--)
4926 md_number_to_chars (litP
, (valueT
) words
[i
], 2);
4932 for (i
= 0; i
< prec
; i
++)
4934 md_number_to_chars (litP
, (valueT
) words
[i
], 2);
4943 md_number_to_chars (buf
, val
, n
)
4951 number_to_chars_littleendian (buf
, val
, n
);
4955 number_to_chars_bigendian (buf
, val
, n
);
4964 CONST
char *md_shortopts
= "O::g::G:";
4966 CONST
char *md_shortopts
= "O::g::";
4968 struct option md_longopts
[] = {
4969 #define OPTION_MIPS1 (OPTION_MD_BASE + 1)
4970 {"mips0", no_argument
, NULL
, OPTION_MIPS1
},
4971 {"mips1", no_argument
, NULL
, OPTION_MIPS1
},
4972 #define OPTION_MIPS2 (OPTION_MD_BASE + 2)
4973 {"mips2", no_argument
, NULL
, OPTION_MIPS2
},
4974 #define OPTION_MIPS3 (OPTION_MD_BASE + 3)
4975 {"mips3", no_argument
, NULL
, OPTION_MIPS3
},
4976 #define OPTION_MCPU (OPTION_MD_BASE + 4)
4977 {"mcpu", required_argument
, NULL
, OPTION_MCPU
},
4978 #define OPTION_MEMBEDDED_PIC (OPTION_MD_BASE + 5)
4979 {"membedded-pic", no_argument
, NULL
, OPTION_MEMBEDDED_PIC
},
4980 #define OPTION_TRAP (OPTION_MD_BASE + 8)
4981 {"trap", no_argument
, NULL
, OPTION_TRAP
},
4982 {"no-break", no_argument
, NULL
, OPTION_TRAP
},
4983 #define OPTION_BREAK (OPTION_MD_BASE + 9)
4984 {"break", no_argument
, NULL
, OPTION_BREAK
},
4985 {"no-trap", no_argument
, NULL
, OPTION_BREAK
},
4986 #define OPTION_EB (OPTION_MD_BASE + 10)
4987 {"EB", no_argument
, NULL
, OPTION_EB
},
4988 #define OPTION_EL (OPTION_MD_BASE + 11)
4989 {"EL", no_argument
, NULL
, OPTION_EL
},
4992 #define OPTION_CALL_SHARED (OPTION_MD_BASE + 6)
4993 {"KPIC", no_argument
, NULL
, OPTION_CALL_SHARED
},
4994 {"call_shared", no_argument
, NULL
, OPTION_CALL_SHARED
},
4995 #define OPTION_NON_SHARED (OPTION_MD_BASE + 7)
4996 {"non_shared", no_argument
, NULL
, OPTION_NON_SHARED
},
4999 {NULL
, no_argument
, NULL
, 0}
5001 size_t md_longopts_size
= sizeof(md_longopts
);
5004 md_parse_option (c
, arg
)
5019 byte_order
= BIG_ENDIAN
;
5021 mips_target_format
= "a.out-mips-big";
5024 mips_target_format
= "ecoff-bigmips";
5027 mips_target_format
= "elf32-bigmips";
5032 byte_order
= LITTLE_ENDIAN
;
5034 mips_target_format
= "a.out-mips-little";
5037 mips_target_format
= "ecoff-littlemips";
5040 mips_target_format
= "elf32-littlemips";
5045 if (arg
&& arg
[1] == '0')
5052 if (arg
== NULL
|| arg
[1] == '2')
5075 /* Identify the processor type */
5077 if (strcmp (p
, "default") == 0
5078 || strcmp (p
, "DEFAULT") == 0)
5082 if (*p
== 'r' || *p
== 'R')
5089 if (strcmp (p
, "2000") == 0
5090 || strcmp (p
, "2k") == 0
5091 || strcmp (p
, "2K") == 0)
5099 if (strcmp (p
, "3000") == 0
5100 || strcmp (p
, "3k") == 0
5101 || strcmp (p
, "3K") == 0)
5109 if (strcmp (p
, "4000") == 0
5110 || strcmp (p
, "4k") == 0
5111 || strcmp (p
, "4K") == 0)
5116 else if (strcmp (p
, "4400") == 0)
5121 else if (strcmp (p
, "4600") == 0)
5129 if (strcmp (p
, "6000") == 0
5130 || strcmp (p
, "6k") == 0
5131 || strcmp (p
, "6K") == 0)
5139 if (strcmp (p
, "orion") == 0)
5149 as_bad ("invalid architecture -mcpu=%s", arg
);
5156 case OPTION_MEMBEDDED_PIC
:
5157 mips_pic
= EMBEDDED_PIC
;
5161 as_bad ("-G may not be used with embedded PIC code");
5164 g_switch_value
= 0x7fffffff;
5169 /* When generating ELF code, we permit -KPIC and -call_shared to
5170 select SVR4_PIC, and -non_shared to select no PIC. This is
5171 intended to be compatible with Irix 5. */
5172 case OPTION_CALL_SHARED
:
5173 mips_pic
= SVR4_PIC
;
5174 if (g_switch_seen
&& g_switch_value
!= 0)
5176 as_bad ("-G may not be used with SVR4 PIC code");
5182 case OPTION_NON_SHARED
:
5185 #endif /* OBJ_ELF */
5189 if (mips_pic
== SVR4_PIC
|| mips_pic
== EMBEDDED_PIC
)
5191 as_bad ("-G may not be used with SVR4 or embedded PIC code");
5195 g_switch_value
= atoi (arg
);
5208 md_show_usage (stream
)
5213 -membedded-pic generate embedded position independent code\n\
5214 -EB generate big endian output\n\
5215 -EL generate little endian output\n\
5216 -g, -g2 do not remove uneeded NOPs or swap branches\n\
5217 -G NUM allow referencing objects up to NUM bytes\n\
5218 implicitly with the gp register [default 8]\n");
5220 -mips1, -mcpu=r{2,3}000 generate code for r2000 and r3000\n\
5221 -mips2, -mcpu=r6000 generate code for r6000\n\
5222 -mips3, -mcpu=r4000 generate code for r4000\n\
5223 -O0 remove unneeded NOPs, do not swap branches\n\
5224 -O remove unneeded NOPs and swap branches\n\
5225 --trap, --no-break trap exception on div by 0 and mult overflow\n\
5226 --break, --no-trap break exception on div by 0 and mult overflow\n");
5229 -KPIC, -call_shared generate SVR4 position independent code\n\
5230 -non_shared do not generate position independent code\n");
5235 md_pcrel_from (fixP
)
5239 if (fixP
->fx_addsy
!= (symbolS
*) NULL
5240 && ! S_IS_DEFINED (fixP
->fx_addsy
))
5242 /* This makes a branch to an undefined symbol be a branch to the
5243 current location. */
5248 /* return the address of the delay slot */
5249 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
5252 /* This is called by emit_expr via TC_CONS_FIX_NEW when creating a
5253 reloc for a cons. We could use the definition there, except that
5254 we want to handle 64 bit relocs specially. */
5257 cons_fix_new_mips (frag
, where
, nbytes
, exp
)
5260 unsigned int nbytes
;
5263 /* If we are assembling in 32 bit mode, turn an 8 byte reloc into a
5265 FIXME: There is no way to select anything but 32 bit mode right
5269 if (byte_order
== BIG_ENDIAN
)
5274 if (nbytes
!= 2 && nbytes
!= 4)
5275 as_bad ("Unsupported reloc size %d", nbytes
);
5277 fix_new_exp (frag_now
, where
, (int) nbytes
, exp
, 0,
5278 nbytes
== 2 ? BFD_RELOC_16
: BFD_RELOC_32
);
5281 /* When generating embedded PIC code we need to use a special
5282 relocation to represent the difference of two symbols in the .text
5283 section (switch tables use a difference of this sort). See
5284 include/coff/mips.h for details. This macro checks whether this
5285 fixup requires the special reloc. */
5286 #define SWITCH_TABLE(fixp) \
5287 ((fixp)->fx_r_type == BFD_RELOC_32 \
5288 && (fixp)->fx_addsy != NULL \
5289 && (fixp)->fx_subsy != NULL \
5290 && S_GET_SEGMENT ((fixp)->fx_addsy) == text_section \
5291 && S_GET_SEGMENT ((fixp)->fx_subsy) == text_section)
5293 /* When generating embedded PIC code we must keep all PC relative
5294 relocations, in case the linker has to relax a call. We also need
5295 to keep relocations for switch table entries. */
5299 mips_force_relocation (fixp
)
5302 return (mips_pic
== EMBEDDED_PIC
5304 || SWITCH_TABLE (fixp
)
5305 || fixp
->fx_r_type
== BFD_RELOC_PCREL_HI16_S
5306 || fixp
->fx_r_type
== BFD_RELOC_PCREL_LO16
));
5309 /* Apply a fixup to the object file. */
5312 md_apply_fix (fixP
, valueP
)
5319 assert (fixP
->fx_size
== 4);
5322 fixP
->fx_addnumber
= value
; /* Remember value for tc_gen_reloc */
5324 if (fixP
->fx_addsy
== NULL
&& ! fixP
->fx_pcrel
)
5327 switch (fixP
->fx_r_type
)
5329 case BFD_RELOC_MIPS_JMP
:
5330 case BFD_RELOC_HI16
:
5331 case BFD_RELOC_HI16_S
:
5332 case BFD_RELOC_MIPS_GPREL
:
5333 case BFD_RELOC_MIPS_LITERAL
:
5334 case BFD_RELOC_MIPS_CALL16
:
5335 case BFD_RELOC_MIPS_GOT16
:
5336 case BFD_RELOC_MIPS_GPREL32
:
5338 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
5339 "Invalid PC relative reloc");
5340 /* Nothing needed to do. The value comes from the reloc entry */
5343 case BFD_RELOC_PCREL_HI16_S
:
5344 /* The addend for this is tricky if it is internal, so we just
5345 do everything here rather than in bfd_perform_relocation. */
5346 if ((fixP
->fx_addsy
->bsym
->flags
& BSF_SECTION_SYM
) == 0)
5348 /* For an external symbol adjust by the address to make it
5349 pcrel_offset. We use the address of the RELLO reloc
5350 which follows this one. */
5351 value
+= (fixP
->fx_next
->fx_frag
->fr_address
5352 + fixP
->fx_next
->fx_where
);
5357 buf
= (unsigned char *) fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
5358 if (byte_order
== BIG_ENDIAN
)
5360 md_number_to_chars (buf
, value
, 2);
5363 case BFD_RELOC_PCREL_LO16
:
5364 /* The addend for this is tricky if it is internal, so we just
5365 do everything here rather than in bfd_perform_relocation. */
5366 if ((fixP
->fx_addsy
->bsym
->flags
& BSF_SECTION_SYM
) == 0)
5367 value
+= fixP
->fx_frag
->fr_address
+ fixP
->fx_where
;
5368 buf
= (unsigned char *) fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
5369 if (byte_order
== BIG_ENDIAN
)
5371 md_number_to_chars (buf
, value
, 2);
5375 /* If we are deleting this reloc entry, we must fill in the
5376 value now. This can happen if we have a .word which is not
5377 resolved when it appears but is later defined. We also need
5378 to fill in the value if this is an embedded PIC switch table
5381 || (mips_pic
== EMBEDDED_PIC
&& SWITCH_TABLE (fixP
)))
5382 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
,
5386 case BFD_RELOC_LO16
:
5387 /* When handling an embedded PIC switch statement, we can wind
5388 up deleting a LO16 reloc. See the 'o' case in mips_ip. */
5391 if (value
< -0x8000 || value
> 0x7fff)
5392 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
5393 "relocation overflow");
5394 buf
= (unsigned char *) fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
5395 if (byte_order
== BIG_ENDIAN
)
5397 md_number_to_chars (buf
, value
, 2);
5401 case BFD_RELOC_16_PCREL_S2
:
5403 * We need to save the bits in the instruction since fixup_segment()
5404 * might be deleting the relocation entry (i.e., a branch within
5405 * the current segment).
5408 as_warn_where (fixP
->fx_file
, fixP
->fx_line
,
5409 "Branch to odd address (%lx)", value
);
5412 /* update old instruction data */
5413 buf
= (unsigned char *) (fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
);
5417 insn
= (buf
[3] << 24) | (buf
[2] << 16) | (buf
[1] << 8) | buf
[0];
5421 insn
= (buf
[0] << 24) | (buf
[1] << 16) | (buf
[2] << 8) | buf
[3];
5429 if (value
>= -0x8000 && value
< 0x8000)
5430 insn
|= value
& 0xffff;
5433 /* The branch offset is too large. If this is an
5434 unconditional branch, and we are not generating PIC code,
5435 we can convert it to an absolute jump instruction. */
5436 if (mips_pic
== NO_PIC
5438 && fixP
->fx_frag
->fr_address
>= text_section
->vma
5439 && (fixP
->fx_frag
->fr_address
5440 < text_section
->vma
+ text_section
->_raw_size
)
5441 && ((insn
& 0xffff0000) == 0x10000000 /* beq $0,$0 */
5442 || (insn
& 0xffff0000) == 0x04010000 /* bgez $0 */
5443 || (insn
& 0xffff0000) == 0x04110000)) /* bgezal $0 */
5445 if ((insn
& 0xffff0000) == 0x04110000) /* bgezal $0 */
5446 insn
= 0x0c000000; /* jal */
5448 insn
= 0x08000000; /* j */
5449 fixP
->fx_r_type
= BFD_RELOC_MIPS_JMP
;
5451 fixP
->fx_addsy
= section_symbol (text_section
);
5452 fixP
->fx_addnumber
= (value
<< 2) + md_pcrel_from (fixP
);
5456 /* FIXME. It would be possible in principle to handle
5457 conditional branches which overflow. They could be
5458 transformed into a branch around a jump. This would
5459 require setting up variant frags for each different
5460 branch type. The native MIPS assembler attempts to
5461 handle these cases, but it appears to do it
5463 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
5464 "Relocation overflow");
5468 md_number_to_chars ((char *) buf
, (valueT
) insn
, 4);
5483 const struct mips_opcode
*p
;
5484 int treg
, sreg
, dreg
, shamt
;
5489 for (i
= 0; i
< NUMOPCODES
; ++i
)
5491 p
= &mips_opcodes
[i
];
5492 if (((oc
& p
->mask
) == p
->match
) && (p
->pinfo
!= INSN_MACRO
))
5494 printf ("%08lx %s\t", oc
, p
->name
);
5495 treg
= (oc
>> 16) & 0x1f;
5496 sreg
= (oc
>> 21) & 0x1f;
5497 dreg
= (oc
>> 11) & 0x1f;
5498 shamt
= (oc
>> 6) & 0x1f;
5500 for (args
= p
->args
;; ++args
)
5511 printf ("%c", *args
);
5515 assert (treg
== sreg
);
5516 printf ("$%d,$%d", treg
, sreg
);
5521 printf ("$%d", dreg
);
5526 printf ("$%d", treg
);
5530 printf ("0x%x", treg
);
5535 printf ("$%d", sreg
);
5539 printf ("0x%08lx", oc
& 0x1ffffff);
5551 printf ("$%d", shamt
);
5562 printf ("%08lx UNDEFINED\n", oc
);
5573 name
= input_line_pointer
;
5574 c
= get_symbol_end ();
5575 p
= (symbolS
*) symbol_find_or_make (name
);
5576 *input_line_pointer
= c
;
5580 /* Align the current frag to a given power of two. The MIPS assembler
5581 also automatically adjusts any preceding label. */
5584 mips_align (to
, fill
, label
)
5589 mips_emit_delays ();
5590 frag_align (to
, fill
);
5591 record_alignment (now_seg
, to
);
5594 assert (S_GET_SEGMENT (label
) == now_seg
);
5595 label
->sy_frag
= frag_now
;
5596 S_SET_VALUE (label
, (valueT
) frag_now_fix ());
5600 /* Align to a given power of two. .align 0 turns off the automatic
5601 alignment used by the data creating pseudo-ops. */
5608 register long temp_fill
;
5609 long max_alignment
= 15;
5613 o Note that the assembler pulls down any immediately preceeding label
5614 to the aligned address.
5615 o It's not documented but auto alignment is reinstated by
5616 a .align pseudo instruction.
5617 o Note also that after auto alignment is turned off the mips assembler
5618 issues an error on attempt to assemble an improperly aligned data item.
5623 temp
= get_absolute_expression ();
5624 if (temp
> max_alignment
)
5625 as_bad ("Alignment too large: %d. assumed.", temp
= max_alignment
);
5628 as_warn ("Alignment negative: 0 assumed.");
5631 if (*input_line_pointer
== ',')
5633 input_line_pointer
++;
5634 temp_fill
= get_absolute_expression ();
5641 mips_align (temp
, (int) temp_fill
, insn_label
);
5648 demand_empty_rest_of_line ();
5651 /* Handle .ascii and .asciiz. This just calls stringer and forgets
5652 that there was a previous instruction. */
5655 s_stringer (append_zero
)
5658 mips_emit_delays ();
5660 stringer (append_zero
);
5671 /* When generating embedded PIC code, we only use the .text, .lit8,
5672 .sdata and .sbss sections. We change the .data and .rdata
5673 pseudo-ops to use .sdata. */
5674 if (mips_pic
== EMBEDDED_PIC
5675 && (sec
== 'd' || sec
== 'r'))
5678 mips_emit_delays ();
5688 subseg_set (bss_section
, (subsegT
) get_absolute_expression ());
5689 demand_empty_rest_of_line ();
5693 seg
= subseg_new (RDATA_SECTION_NAME
,
5694 (subsegT
) get_absolute_expression ());
5696 bfd_set_section_flags (stdoutput
, seg
,
5702 bfd_set_section_alignment (stdoutput
, seg
, 4);
5704 demand_empty_rest_of_line ();
5709 seg
= subseg_new (".sdata", (subsegT
) get_absolute_expression ());
5711 bfd_set_section_flags (stdoutput
, seg
,
5712 SEC_ALLOC
| SEC_LOAD
| SEC_RELOC
| SEC_DATA
);
5713 bfd_set_section_alignment (stdoutput
, seg
, 4);
5715 demand_empty_rest_of_line ();
5717 #else /* ! defined (GPOPT) */
5718 as_bad ("Global pointers not supported; recompile -G 0");
5719 demand_empty_rest_of_line ();
5721 #endif /* ! defined (GPOPT) */
5729 /* Handle the ELF .section pseudo-op. This is a wrapper around
5736 mips_emit_delays ();
5737 obj_elf_section (x
);
5741 #endif /* OBJ_ELF */
5750 mips_emit_delays ();
5751 if (log_size
> 0 && auto_align
)
5752 mips_align (log_size
, 0, label
);
5754 cons (1 << log_size
);
5761 as_fatal ("Encountered `.err', aborting assembly");
5771 symbolP
= get_symbol ();
5772 if (*input_line_pointer
== ',')
5773 input_line_pointer
++;
5774 size
= get_absolute_expression ();
5775 S_SET_EXTERNAL (symbolP
);
5777 #ifdef ECOFF_DEBUGGING
5778 symbolP
->ecoff_extern_size
= size
;
5790 mips_emit_delays ();
5794 mips_align (3, 0, label
);
5796 mips_align (2, 0, label
);
5803 /* Handle .globl. We need to override it because on Irix 5 you are
5806 where foo is an undefined symbol, to mean that foo should be
5807 considered to be the address of a function. */
5817 name
= input_line_pointer
;
5818 c
= get_symbol_end ();
5819 symbolP
= symbol_find_or_make (name
);
5820 *input_line_pointer
= c
;
5822 if (! is_end_of_line
[(unsigned char) *input_line_pointer
])
5827 secname
= input_line_pointer
;
5828 c
= get_symbol_end ();
5829 sec
= bfd_get_section_by_name (stdoutput
, secname
);
5831 as_bad ("%s: no such section", secname
);
5832 *input_line_pointer
= c
;
5834 if (sec
!= NULL
&& (sec
->flags
& SEC_CODE
) != 0)
5835 symbolP
->bsym
->flags
|= BSF_FUNCTION
;
5838 S_SET_EXTERNAL (symbolP
);
5839 demand_empty_rest_of_line ();
5849 opt
= input_line_pointer
;
5850 c
= get_symbol_end ();
5854 /* FIXME: What does this mean? */
5856 else if (strncmp (opt
, "pic", 3) == 0)
5864 mips_pic
= SVR4_PIC
;
5866 as_bad (".option pic%d not supported", i
);
5869 if (mips_pic
== SVR4_PIC
)
5871 if (g_switch_seen
&& g_switch_value
!= 0)
5872 as_warn ("-G may not be used with SVR4 PIC code");
5874 bfd_set_gp_size (stdoutput
, 0);
5879 as_warn ("Unrecognized option \"%s\"", opt
);
5881 *input_line_pointer
= c
;
5882 demand_empty_rest_of_line ();
5889 char *name
= input_line_pointer
, ch
;
5891 while (!is_end_of_line
[(unsigned char) *input_line_pointer
])
5892 input_line_pointer
++;
5893 ch
= *input_line_pointer
;
5894 *input_line_pointer
= '\0';
5896 if (strcmp (name
, "reorder") == 0)
5900 prev_insn_unreordered
= 1;
5901 prev_prev_insn_unreordered
= 1;
5905 else if (strcmp (name
, "noreorder") == 0)
5907 mips_emit_delays ();
5909 mips_any_noreorder
= 1;
5911 else if (strcmp (name
, "at") == 0)
5915 else if (strcmp (name
, "noat") == 0)
5919 else if (strcmp (name
, "macro") == 0)
5921 mips_warn_about_macros
= 0;
5923 else if (strcmp (name
, "nomacro") == 0)
5925 if (mips_noreorder
== 0)
5926 as_bad ("`noreorder' must be set before `nomacro'");
5927 mips_warn_about_macros
= 1;
5929 else if (strcmp (name
, "move") == 0 || strcmp (name
, "novolatile") == 0)
5933 else if (strcmp (name
, "nomove") == 0 || strcmp (name
, "volatile") == 0)
5937 else if (strcmp (name
, "bopt") == 0)
5941 else if (strcmp (name
, "nobopt") == 0)
5945 else if (strncmp (name
, "mips", 4) == 0)
5949 /* Permit the user to change the ISA on the fly. Needless to
5950 say, misuse can cause serious problems. */
5951 isa
= atoi (name
+ 4);
5953 mips_isa
= file_mips_isa
;
5954 else if (isa
< 1 || isa
> 3)
5955 as_bad ("unknown ISA level");
5961 as_warn ("Tried to set unrecognized symbol: %s\n", name
);
5963 *input_line_pointer
= ch
;
5964 demand_empty_rest_of_line ();
5967 /* The same as the usual .space directive, except that we have to
5968 forget about any previous instruction. */
5971 s_mips_space (param
)
5974 mips_emit_delays ();
5979 /* Handle the .abicalls pseudo-op. I believe this is equivalent to
5980 .option pic2. It means to generate SVR4 PIC calls. */
5986 mips_pic
= SVR4_PIC
;
5988 if (g_switch_seen
&& g_switch_value
!= 0)
5989 as_warn ("-G may not be used with SVR4 PIC code");
5992 bfd_set_gp_size (stdoutput
, 0);
5993 demand_empty_rest_of_line ();
5996 /* Handle the .cpload pseudo-op. This is used when generating SVR4
5997 PIC code. It sets the $gp register for the function based on the
5998 function address, which is in the register named in the argument.
5999 This uses a relocation against _gp_disp, which is handled specially
6000 by the linker. The result is:
6001 lui $gp,%hi(_gp_disp)
6002 addiu $gp,$gp,%lo(_gp_disp)
6003 addu $gp,$gp,.cpload argument
6004 The .cpload argument is normally $25 == $t9. */
6013 /* If we are not generating SVR4 PIC code, .cpload is ignored. */
6014 if (mips_pic
!= SVR4_PIC
)
6020 /* .cpload should be a in .set noreorder section. */
6021 if (mips_noreorder
== 0)
6022 as_warn (".cpload not in noreorder section");
6025 ex
.X_add_symbol
= symbol_find_or_make ("_gp_disp");
6026 ex
.X_op_symbol
= NULL
;
6027 ex
.X_add_number
= 0;
6029 macro_build_lui ((char *) NULL
, &icnt
, &ex
, GP
);
6030 macro_build ((char *) NULL
, &icnt
, &ex
, "addiu", "t,r,j", GP
, GP
,
6031 (int) BFD_RELOC_LO16
);
6033 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "addu", "d,v,t",
6034 GP
, GP
, tc_get_register (0));
6036 demand_empty_rest_of_line ();
6039 /* Handle the .cprestore pseudo-op. This stores $gp into a given
6040 offset from $sp. The offset is remembered, and after making a PIC
6041 call $gp is restored from that location. */
6044 s_cprestore (ignore
)
6050 /* If we are not generating SVR4 PIC code, .cprestore is ignored. */
6051 if (mips_pic
!= SVR4_PIC
)
6057 mips_cprestore_offset
= get_absolute_expression ();
6059 ex
.X_op
= O_constant
;
6060 ex
.X_add_symbol
= NULL
;
6061 ex
.X_op_symbol
= NULL
;
6062 ex
.X_add_number
= mips_cprestore_offset
;
6064 macro_build ((char *) NULL
, &icnt
, &ex
,
6065 mips_isa
< 3 ? "sw" : "sd",
6066 "t,o(b)", GP
, (int) BFD_RELOC_LO16
, SP
);
6068 demand_empty_rest_of_line ();
6071 /* Handle the .gpword pseudo-op. This is used when generating PIC
6072 code. It generates a 32 bit GP relative reloc. */
6082 /* When not generating PIC code, this is treated as .word. */
6083 if (mips_pic
!= SVR4_PIC
)
6090 mips_emit_delays ();
6092 mips_align (2, 0, label
);
6097 if (ex
.X_op
!= O_symbol
|| ex
.X_add_number
!= 0)
6099 as_bad ("Unsupported use of .gpword");
6100 ignore_rest_of_line ();
6104 md_number_to_chars (p
, (valueT
) 0, 4);
6105 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 4, &ex
, 0,
6106 BFD_RELOC_MIPS_GPREL32
);
6108 demand_empty_rest_of_line ();
6111 /* Handle the .cpadd pseudo-op. This is used when dealing with switch
6112 tables in SVR4 PIC code. */
6121 /* This is ignored when not generating SVR4 PIC code. */
6122 if (mips_pic
!= SVR4_PIC
)
6128 /* Add $gp to the register named as an argument. */
6129 reg
= tc_get_register (0);
6130 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6131 mips_isa
< 3 ? "addu" : "daddu",
6132 "d,v,t", reg
, reg
, GP
);
6134 demand_empty_rest_of_line ();
6137 /* Parse a register string into a number. Called from the ECOFF code
6138 to parse .frame. The argument is non-zero if this is the frame
6139 register, so that we can record it in mips_frame_reg. */
6142 tc_get_register (frame
)
6148 if (*input_line_pointer
++ != '$')
6150 as_warn ("expected `$'");
6153 else if (isdigit ((unsigned char) *input_line_pointer
))
6155 reg
= get_absolute_expression ();
6156 if (reg
< 0 || reg
>= 32)
6158 as_warn ("Bad register number");
6164 if (strncmp (input_line_pointer
, "fp", 2) == 0)
6166 else if (strncmp (input_line_pointer
, "sp", 2) == 0)
6168 else if (strncmp (input_line_pointer
, "gp", 2) == 0)
6170 else if (strncmp (input_line_pointer
, "at", 2) == 0)
6174 as_warn ("Unrecognized register name");
6177 input_line_pointer
+= 2;
6180 mips_frame_reg
= reg
!= 0 ? reg
: SP
;
6185 md_section_align (seg
, addr
)
6189 int align
= bfd_get_section_alignment (stdoutput
, seg
);
6191 return ((addr
+ (1 << align
) - 1) & (-1 << align
));
6194 /* Estimate the size of a frag before relaxing. We are not really
6195 relaxing here, and the final size is encoded in the subtype
6200 md_estimate_size_before_relax (fragp
, segtype
)
6206 if (mips_pic
== NO_PIC
)
6209 const char *symname
;
6211 /* Find out whether this symbol can be referenced off the GP
6212 register. It can be if it is smaller than the -G size or if
6213 it is in the .sdata or .sbss section. Certain symbols can
6214 not be referenced off the GP, although it appears as though
6216 symname
= S_GET_NAME (fragp
->fr_symbol
);
6217 if (symname
!= (const char *) NULL
6218 && (strcmp (symname
, "eprol") == 0
6219 || strcmp (symname
, "etext") == 0
6220 || strcmp (symname
, "_gp") == 0
6221 || strcmp (symname
, "edata") == 0
6222 || strcmp (symname
, "_fbss") == 0
6223 || strcmp (symname
, "_fdata") == 0
6224 || strcmp (symname
, "_ftext") == 0
6225 || strcmp (symname
, "end") == 0
6226 || strcmp (symname
, "_gp_disp") == 0))
6228 else if (! S_IS_DEFINED (fragp
->fr_symbol
)
6229 && ((fragp
->fr_symbol
->ecoff_extern_size
!= 0
6230 && fragp
->fr_symbol
->ecoff_extern_size
<= g_switch_value
)
6231 || (S_GET_VALUE (fragp
->fr_symbol
) != 0
6232 && S_GET_VALUE (fragp
->fr_symbol
) <= g_switch_value
)))
6236 const char *segname
;
6238 segname
= segment_name (S_GET_SEGMENT (fragp
->fr_symbol
));
6239 assert (strcmp (segname
, ".lit8") != 0
6240 && strcmp (segname
, ".lit4") != 0);
6241 change
= (strcmp (segname
, ".sdata") != 0
6242 && strcmp (segname
, ".sbss") != 0);
6244 #else /* ! defined (GPOPT) */
6245 /* We are not optimizing for the GP register. */
6247 #endif /* ! defined (GPOPT) */
6249 else if (mips_pic
== SVR4_PIC
)
6251 asection
*symsec
= fragp
->fr_symbol
->bsym
->section
;
6253 /* This must duplicate the test in adjust_reloc_syms. */
6254 change
= (symsec
!= &bfd_und_section
6255 && symsec
!= &bfd_abs_section
6256 && ! bfd_is_com_section (symsec
));
6263 /* Record the offset to the first reloc in the fr_opcode field.
6264 This lets md_convert_frag and tc_gen_reloc know that the code
6265 must be expanded. */
6266 fragp
->fr_opcode
= (fragp
->fr_literal
6268 - RELAX_OLD (fragp
->fr_subtype
)
6269 + RELAX_RELOC1 (fragp
->fr_subtype
));
6270 /* FIXME: This really needs as_warn_where. */
6271 if (RELAX_WARN (fragp
->fr_subtype
))
6272 as_warn ("AT used after \".set noat\" or macro used after \".set nomacro\"");
6278 return RELAX_NEW (fragp
->fr_subtype
) - RELAX_OLD (fragp
->fr_subtype
);
6281 /* Translate internal representation of relocation info to BFD target
6285 tc_gen_reloc (section
, fixp
)
6289 static arelent
*retval
[4];
6292 reloc
= retval
[0] = (arelent
*) xmalloc (sizeof (arelent
));
6295 reloc
->sym_ptr_ptr
= &fixp
->fx_addsy
->bsym
;
6296 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
6298 if (mips_pic
== EMBEDDED_PIC
6299 && SWITCH_TABLE (fixp
))
6301 /* For a switch table entry we use a special reloc. The addend
6302 is actually the difference between the reloc address and the
6304 reloc
->addend
= reloc
->address
- S_GET_VALUE (fixp
->fx_subsy
);
6306 as_fatal ("Double check fx_r_type in tc-mips.c:tc_gen_reloc");
6308 fixp
->fx_r_type
= BFD_RELOC_GPREL32
;
6310 else if (fixp
->fx_r_type
== BFD_RELOC_PCREL_LO16
)
6312 /* We use a special addend for an internal RELLO reloc. */
6313 if (fixp
->fx_addsy
->bsym
->flags
& BSF_SECTION_SYM
)
6314 reloc
->addend
= reloc
->address
- S_GET_VALUE (fixp
->fx_subsy
);
6316 reloc
->addend
= fixp
->fx_addnumber
+ reloc
->address
;
6318 else if (fixp
->fx_r_type
== BFD_RELOC_PCREL_HI16_S
)
6320 assert (fixp
->fx_next
!= NULL
6321 && fixp
->fx_next
->fx_r_type
== BFD_RELOC_PCREL_LO16
);
6322 /* We use a special addend for an internal RELHI reloc. The
6323 reloc is relative to the RELLO; adjust the addend
6325 if (fixp
->fx_addsy
->bsym
->flags
& BSF_SECTION_SYM
)
6326 reloc
->addend
= (fixp
->fx_next
->fx_frag
->fr_address
6327 + fixp
->fx_next
->fx_where
6328 - S_GET_VALUE (fixp
->fx_subsy
));
6330 reloc
->addend
= (fixp
->fx_addnumber
6331 + fixp
->fx_next
->fx_frag
->fr_address
6332 + fixp
->fx_next
->fx_where
);
6334 else if (fixp
->fx_pcrel
== 0)
6335 reloc
->addend
= fixp
->fx_addnumber
;
6339 /* A gruesome hack which is a result of the gruesome gas reloc
6341 reloc
->addend
= reloc
->address
;
6343 reloc
->addend
= -reloc
->address
;
6347 /* If this is a variant frag, we may need to adjust the existing
6348 reloc and generate a new one. */
6349 if (fixp
->fx_frag
->fr_opcode
!= NULL
6350 && (fixp
->fx_r_type
== BFD_RELOC_MIPS_GPREL
6351 || fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT16
6352 || fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL16
))
6356 /* If this is not the last reloc in this frag, then we have two
6357 GPREL relocs, both of which are being replaced. Let the
6358 second one handle all of them. */
6359 if (fixp
->fx_next
!= NULL
6360 && fixp
->fx_frag
== fixp
->fx_next
->fx_frag
)
6362 assert (fixp
->fx_r_type
== BFD_RELOC_MIPS_GPREL
6363 && fixp
->fx_next
->fx_r_type
== BFD_RELOC_MIPS_GPREL
);
6368 fixp
->fx_where
= fixp
->fx_frag
->fr_opcode
- fixp
->fx_frag
->fr_literal
;
6369 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
6370 reloc2
= retval
[1] = (arelent
*) xmalloc (sizeof (arelent
));
6372 reloc2
->sym_ptr_ptr
= &fixp
->fx_addsy
->bsym
;
6373 reloc2
->address
= (reloc
->address
6374 + (RELAX_RELOC2 (fixp
->fx_frag
->fr_subtype
)
6375 - RELAX_RELOC1 (fixp
->fx_frag
->fr_subtype
)));
6376 reloc2
->addend
= fixp
->fx_addnumber
;
6377 reloc2
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_LO16
);
6378 assert (reloc2
->howto
!= NULL
);
6380 if (RELAX_RELOC3 (fixp
->fx_frag
->fr_subtype
))
6384 reloc3
= retval
[2] = (arelent
*) xmalloc (sizeof (arelent
));
6387 reloc3
->address
+= 4;
6390 if (mips_pic
== NO_PIC
)
6392 assert (fixp
->fx_r_type
== BFD_RELOC_MIPS_GPREL
);
6393 fixp
->fx_r_type
= BFD_RELOC_HI16_S
;
6395 else if (mips_pic
== SVR4_PIC
)
6397 if (fixp
->fx_r_type
!= BFD_RELOC_MIPS_GOT16
)
6399 assert (fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL16
);
6400 fixp
->fx_r_type
= BFD_RELOC_MIPS_GOT16
;
6407 /* To support a PC relative reloc when generating embedded PIC code
6408 for ECOFF, we use a Cygnus extension. We check for that here to
6409 make sure that we don't let such a reloc escape normally. */
6411 if (fixp
->fx_r_type
== BFD_RELOC_16_PCREL_S2
6412 && mips_pic
!= EMBEDDED_PIC
)
6413 reloc
->howto
= NULL
;
6416 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, fixp
->fx_r_type
);
6418 if (reloc
->howto
== NULL
)
6420 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
6421 "Can not represent relocation in this object file format");
6428 /* Convert a machine dependent frag. */
6431 md_convert_frag (abfd
, asec
, fragp
)
6439 if (fragp
->fr_opcode
== NULL
)
6442 old
= RELAX_OLD (fragp
->fr_subtype
);
6443 new = RELAX_NEW (fragp
->fr_subtype
);
6444 fixptr
= fragp
->fr_literal
+ fragp
->fr_fix
;
6447 memcpy (fixptr
- old
, fixptr
, new);
6449 fragp
->fr_fix
+= new - old
;
6452 /* This function is called whenever a label is defined. It is used
6453 when handling branch delays; if a branch has a label, we assume we
6457 mips_define_label (sym
)
6465 /* Some special processing for a MIPS ELF file. */
6468 mips_elf_final_processing ()
6472 /* Write out the .reginfo section. */
6473 s
.ri_gprmask
= mips_gprmask
;
6474 s
.ri_cprmask
[0] = mips_cprmask
[0];
6475 s
.ri_cprmask
[1] = mips_cprmask
[1];
6476 s
.ri_cprmask
[2] = mips_cprmask
[2];
6477 s
.ri_cprmask
[3] = mips_cprmask
[3];
6478 /* The gp_value field is set by the MIPS ELF backend. */
6480 bfd_mips_elf32_swap_reginfo_out (stdoutput
, &s
,
6481 ((Elf32_External_RegInfo
*)
6482 mips_regmask_frag
));
6484 /* Set the MIPS ELF flag bits. FIXME: There should probably be some
6485 sort of BFD interface for this. */
6486 if (mips_any_noreorder
)
6487 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_NOREORDER
;
6488 if (mips_pic
!= NO_PIC
)
6489 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_PIC
;
6492 #endif /* OBJ_ELF */
6494 #ifndef ECOFF_DEBUGGING
6496 /* These functions should really be defined by the object file format,
6497 since they are related to debugging information. However, this
6498 code has to work for the a.out format, which does not define them,
6499 so we provide simple versions here. These don't actually generate
6500 any debugging information, but they do simple checking and someday
6501 somebody may make them useful. */
6505 struct loc
*loc_next
;
6506 unsigned long loc_fileno
;
6507 unsigned long loc_lineno
;
6508 unsigned long loc_offset
;
6509 unsigned short loc_delta
;
6510 unsigned short loc_count
;
6519 struct proc
*proc_next
;
6520 struct symbol
*proc_isym
;
6521 struct symbol
*proc_end
;
6522 unsigned long proc_reg_mask
;
6523 unsigned long proc_reg_offset
;
6524 unsigned long proc_fpreg_mask
;
6525 unsigned long proc_fpreg_offset
;
6526 unsigned long proc_frameoffset
;
6527 unsigned long proc_framereg
;
6528 unsigned long proc_pcreg
;
6530 struct file
*proc_file
;
6537 struct file
*file_next
;
6538 unsigned long file_fileno
;
6539 struct symbol
*file_symbol
;
6540 struct symbol
*file_end
;
6541 struct proc
*file_proc
;
6546 static struct obstack proc_frags
;
6547 static procS
*proc_lastP
;
6548 static procS
*proc_rootP
;
6549 static int numprocs
;
6554 obstack_begin (&proc_frags
, 0x2000);
6560 /* check for premature end, nesting errors, etc */
6561 if (proc_lastP
&& proc_lastP
->proc_end
== NULL
)
6562 as_warn ("missing `.end' at end of assembly");
6565 extern char hex_value
[];
6573 if (*input_line_pointer
== '-')
6575 ++input_line_pointer
;
6578 if (!isdigit (*input_line_pointer
))
6579 as_bad ("Expected simple number.");
6580 if (input_line_pointer
[0] == '0')
6582 if (input_line_pointer
[1] == 'x')
6584 input_line_pointer
+= 2;
6585 while (isxdigit (*input_line_pointer
))
6588 val
|= hex_value
[(int) *input_line_pointer
++];
6590 return negative
? -val
: val
;
6594 ++input_line_pointer
;
6595 while (isdigit (*input_line_pointer
))
6598 val
|= *input_line_pointer
++ - '0';
6600 return negative
? -val
: val
;
6603 if (!isdigit (*input_line_pointer
))
6605 printf (" *input_line_pointer == '%c' 0x%02x\n",
6606 *input_line_pointer
, *input_line_pointer
);
6607 as_warn ("Invalid number");
6610 while (isdigit (*input_line_pointer
))
6613 val
+= *input_line_pointer
++ - '0';
6615 return negative
? -val
: val
;
6618 /* The .file directive; just like the usual .file directive, but there
6619 is an initial number which is the ECOFF file index. */
6627 line
= get_number ();
6632 /* The .end directive. */
6640 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
6643 demand_empty_rest_of_line ();
6647 if (now_seg
!= text_section
)
6648 as_warn (".end not in text section");
6651 as_warn (".end and no .ent seen yet.");
6657 assert (S_GET_NAME (p
));
6658 if (strcmp (S_GET_NAME (p
), S_GET_NAME (proc_lastP
->proc_isym
)))
6659 as_warn (".end symbol does not match .ent symbol.");
6662 proc_lastP
->proc_end
= (symbolS
*) 1;
6665 /* The .aent and .ent directives. */
6675 symbolP
= get_symbol ();
6676 if (*input_line_pointer
== ',')
6677 input_line_pointer
++;
6679 if (isdigit (*input_line_pointer
) || *input_line_pointer
== '-')
6680 number
= get_number ();
6681 if (now_seg
!= text_section
)
6682 as_warn (".ent or .aent not in text section.");
6684 if (!aent
&& proc_lastP
&& proc_lastP
->proc_end
== NULL
)
6685 as_warn ("missing `.end'");
6689 procP
= (procS
*) obstack_alloc (&proc_frags
, sizeof (*procP
));
6690 procP
->proc_isym
= symbolP
;
6691 procP
->proc_reg_mask
= 0;
6692 procP
->proc_reg_offset
= 0;
6693 procP
->proc_fpreg_mask
= 0;
6694 procP
->proc_fpreg_offset
= 0;
6695 procP
->proc_frameoffset
= 0;
6696 procP
->proc_framereg
= 0;
6697 procP
->proc_pcreg
= 0;
6698 procP
->proc_end
= NULL
;
6699 procP
->proc_next
= NULL
;
6701 proc_lastP
->proc_next
= procP
;
6707 demand_empty_rest_of_line ();
6710 /* The .frame directive. */
6723 frame_reg
= tc_get_register (1);
6724 if (*input_line_pointer
== ',')
6725 input_line_pointer
++;
6726 frame_off
= get_absolute_expression ();
6727 if (*input_line_pointer
== ',')
6728 input_line_pointer
++;
6729 pcreg
= tc_get_register (0);
6732 assert (proc_rootP
);
6733 proc_rootP
->proc_framereg
= frame_reg
;
6734 proc_rootP
->proc_frameoffset
= frame_off
;
6735 proc_rootP
->proc_pcreg
= pcreg
;
6736 /* bob macho .frame */
6738 /* We don't have to write out a frame stab for unoptimized code. */
6739 if (!(frame_reg
== FP
&& frame_off
== 0))
6742 as_warn ("No .ent for .frame to use.");
6743 (void) sprintf (str
, "R%d;%d", frame_reg
, frame_off
);
6744 symP
= symbol_new (str
, N_VFP
, 0, frag_now
);
6745 S_SET_TYPE (symP
, N_RMASK
);
6746 S_SET_OTHER (symP
, 0);
6747 S_SET_DESC (symP
, 0);
6748 symP
->sy_forward
= proc_lastP
->proc_isym
;
6749 /* bob perhaps I should have used pseudo set */
6751 demand_empty_rest_of_line ();
6755 /* The .fmask and .mask directives. */
6762 char str
[100], *strP
;
6768 mask
= get_number ();
6769 if (*input_line_pointer
== ',')
6770 input_line_pointer
++;
6771 off
= get_absolute_expression ();
6773 /* bob only for coff */
6774 assert (proc_rootP
);
6775 if (reg_type
== 'F')
6777 proc_rootP
->proc_fpreg_mask
= mask
;
6778 proc_rootP
->proc_fpreg_offset
= off
;
6782 proc_rootP
->proc_reg_mask
= mask
;
6783 proc_rootP
->proc_reg_offset
= off
;
6786 /* bob macho .mask + .fmask */
6788 /* We don't have to write out a mask stab if no saved regs. */
6792 as_warn ("No .ent for .mask to use.");
6794 for (i
= 0; i
< 32; i
++)
6798 sprintf (strP
, "%c%d,", reg_type
, i
);
6799 strP
+= strlen (strP
);
6803 sprintf (strP
, ";%d,", off
);
6804 symP
= symbol_new (str
, N_RMASK
, 0, frag_now
);
6805 S_SET_TYPE (symP
, N_RMASK
);
6806 S_SET_OTHER (symP
, 0);
6807 S_SET_DESC (symP
, 0);
6808 symP
->sy_forward
= proc_lastP
->proc_isym
;
6809 /* bob perhaps I should have used pseudo set */
6814 /* The .loc directive. */
6825 assert (now_seg
== text_section
);
6827 lineno
= get_number ();
6828 addroff
= obstack_next_free (&frags
) - frag_now
->fr_literal
;
6830 symbolP
= symbol_new ("", N_SLINE
, addroff
, frag_now
);
6831 S_SET_TYPE (symbolP
, N_SLINE
);
6832 S_SET_OTHER (symbolP
, 0);
6833 S_SET_DESC (symbolP
, lineno
);
6834 symbolP
->sy_segment
= now_seg
;
6838 #endif /* ! defined (ECOFF_DEBUGGING) */