1 /* tc-mips.c -- assemble code for a MIPS chip.
2 Copyright (C) 1993, 1995, 1996 Free Software Foundation, Inc.
3 Contributed by the OSF and Ralph Campbell.
4 Written by Keith Knowles and Ralph Campbell, working independently.
5 Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus
8 This file is part of GAS.
10 GAS is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 2, or (at your option)
15 GAS is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with GAS; see the file COPYING. If not, write to the Free
22 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
38 #include "opcode/mips.h"
41 /* Clean up namespace so we can include obj-elf.h too. */
42 static int mips_output_flavor () { return OUTPUT_FLAVOR
; }
43 #undef OBJ_PROCESS_STAB
49 #undef TARGET_SYMBOL_FIELDS
51 #undef obj_frob_file_after_relocs
52 #undef obj_frob_symbol
54 #undef obj_sec_sym_ok_for_reloc
57 /* Fix any of them that we actually care about. */
59 #define OUTPUT_FLAVOR mips_output_flavor()
66 #ifndef ECOFF_DEBUGGING
67 #define NO_ECOFF_DEBUGGING
68 #define ECOFF_DEBUGGING 0
73 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
74 static char *mips_regmask_frag
;
79 #define PIC_CALL_REG 25
87 #define ILLEGAL_REG (32)
89 extern int target_big_endian
;
91 /* 1 is we should use the 64 bit MIPS ELF ABI, 0 if we should use the
92 32 bit ABI. This has no meaning for ECOFF. */
95 /* The default target format to use. */
99 switch (OUTPUT_FLAVOR
)
101 case bfd_target_aout_flavour
:
102 return target_big_endian
? "a.out-mips-big" : "a.out-mips-little";
103 case bfd_target_ecoff_flavour
:
104 return target_big_endian
? "ecoff-bigmips" : "ecoff-littlemips";
105 case bfd_target_elf_flavour
:
106 return (target_big_endian
107 ? (mips_64
? "elf64-bigmips" : "elf32-bigmips")
108 : (mips_64
? "elf64-littlemips" : "elf32-littlemips"));
114 /* The name of the readonly data section. */
115 #define RDATA_SECTION_NAME (OUTPUT_FLAVOR == bfd_target_aout_flavour \
117 : OUTPUT_FLAVOR == bfd_target_ecoff_flavour \
119 : OUTPUT_FLAVOR == bfd_target_elf_flavour \
123 /* These variables are filled in with the masks of registers used.
124 The object format code reads them and puts them in the appropriate
126 unsigned long mips_gprmask
;
127 unsigned long mips_cprmask
[4];
129 /* MIPS ISA (Instruction Set Architecture) level (may be changed
130 temporarily using .set mipsN). */
131 static int mips_isa
= -1;
133 /* MIPS ISA we are using for this output file. */
134 static int file_mips_isa
;
136 /* Whether we are assembling for the mips16 processor. */
137 static int mips16
= -1;
139 /* The CPU type as a number: 2000, 3000, 4000, 4400, etc. */
140 static int mips_cpu
= -1;
142 /* Whether the 4650 instructions (mad/madu) are permitted. */
143 static int mips_4650
= -1;
145 /* Whether the 4010 instructions are permitted. */
146 static int mips_4010
= -1;
148 /* Whether the 4100 MADD16 and DMADD16 are permitted. */
149 static int mips_4100
= -1;
151 /* Whether the processor uses hardware interlocks, and thus does not
152 require nops to be inserted. */
153 static int interlocks
= -1;
155 /* As with "interlocks" this is used by hardware that has FP
156 (co-processor) interlocks. */
157 static int cop_interlocks
= -1;
159 /* MIPS PIC level. */
163 /* Do not generate PIC code. */
166 /* Generate PIC code as in Irix 4. This is not implemented, and I'm
167 not sure what it is supposed to do. */
170 /* Generate PIC code as in the SVR4 MIPS ABI. */
173 /* Generate PIC code without using a global offset table: the data
174 segment has a maximum size of 64K, all data references are off
175 the $gp register, and all text references are PC relative. This
176 is used on some embedded systems. */
180 static enum mips_pic_level mips_pic
;
182 /* 1 if we should generate 32 bit offsets from the GP register in
183 SVR4_PIC mode. Currently has no meaning in other modes. */
184 static int mips_big_got
;
186 /* 1 if trap instructions should used for overflow rather than break
188 static int mips_trap
;
190 /* 1 if we should autoextend mips16 instructions. */
191 static int mips16_autoextend
= 1;
193 static int mips_warn_about_macros
;
194 static int mips_noreorder
;
195 static int mips_any_noreorder
;
196 static int mips_nomove
;
197 static int mips_noat
;
198 static int mips_nobopt
;
200 /* The size of the small data section. */
201 static int g_switch_value
= 8;
202 /* Whether the -G option was used. */
203 static int g_switch_seen
= 0;
208 /* If we can determine in advance that GP optimization won't be
209 possible, we can skip the relaxation stuff that tries to produce
210 GP-relative references. This makes delay slot optimization work
213 This function can only provide a guess, but it seems to work for
214 gcc output. If it guesses wrong, the only loss should be in
215 efficiency; it shouldn't introduce any bugs.
217 I don't know if a fix is needed for the SVR4_PIC mode. I've only
218 fixed it for the non-PIC mode. KR 95/04/07 */
219 static int nopic_need_relax
PARAMS ((symbolS
*));
221 /* handle of the OPCODE hash table */
222 static struct hash_control
*op_hash
= NULL
;
224 /* The opcode hash table we use for the mips16. */
225 static struct hash_control
*mips16_op_hash
= NULL
;
227 /* This array holds the chars that always start a comment. If the
228 pre-processor is disabled, these aren't very useful */
229 const char comment_chars
[] = "#";
231 /* This array holds the chars that only start a comment at the beginning of
232 a line. If the line seems to have the form '# 123 filename'
233 .line and .file directives will appear in the pre-processed output */
234 /* Note that input_file.c hand checks for '#' at the beginning of the
235 first line of the input file. This is because the compiler outputs
236 #NO_APP at the beginning of its output. */
237 /* Also note that C style comments are always supported. */
238 const char line_comment_chars
[] = "#";
240 /* This array holds machine specific line separator characters. */
241 const char line_separator_chars
[] = "";
243 /* Chars that can be used to separate mant from exp in floating point nums */
244 const char EXP_CHARS
[] = "eE";
246 /* Chars that mean this number is a floating point constant */
249 const char FLT_CHARS
[] = "rRsSfFdDxXpP";
251 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
252 changed in read.c . Ideally it shouldn't have to know about it at all,
253 but nothing is ideal around here.
256 static char *insn_error
;
258 static int byte_order
;
260 static int auto_align
= 1;
262 /* Symbol labelling the current insn. */
263 static symbolS
*insn_label
;
265 /* When outputting SVR4 PIC code, the assembler needs to know the
266 offset in the stack frame from which to restore the $gp register.
267 This is set by the .cprestore pseudo-op, and saved in this
269 static offsetT mips_cprestore_offset
= -1;
271 /* This is the register which holds the stack frame, as set by the
272 .frame pseudo-op. This is needed to implement .cprestore. */
273 static int mips_frame_reg
= SP
;
275 /* To output NOP instructions correctly, we need to keep information
276 about the previous two instructions. */
278 /* Whether we are optimizing. The default value of 2 means to remove
279 unneeded NOPs and swap branch instructions when possible. A value
280 of 1 means to not swap branches. A value of 0 means to always
282 static int mips_optimize
= 2;
284 /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is
285 equivalent to seeing no -g option at all. */
286 static int mips_debug
= 0;
288 /* The previous instruction. */
289 static struct mips_cl_insn prev_insn
;
291 /* The instruction before prev_insn. */
292 static struct mips_cl_insn prev_prev_insn
;
294 /* If we don't want information for prev_insn or prev_prev_insn, we
295 point the insn_mo field at this dummy integer. */
296 static const struct mips_opcode dummy_opcode
= { 0 };
298 /* Non-zero if prev_insn is valid. */
299 static int prev_insn_valid
;
301 /* The frag for the previous instruction. */
302 static struct frag
*prev_insn_frag
;
304 /* The offset into prev_insn_frag for the previous instruction. */
305 static long prev_insn_where
;
307 /* The reloc type for the previous instruction, if any. */
308 static bfd_reloc_code_real_type prev_insn_reloc_type
;
310 /* The reloc for the previous instruction, if any. */
311 static fixS
*prev_insn_fixp
;
313 /* Non-zero if the previous instruction was in a delay slot. */
314 static int prev_insn_is_delay_slot
;
316 /* Non-zero if the previous instruction was in a .set noreorder. */
317 static int prev_insn_unreordered
;
319 /* Non-zero if the previous instruction uses an extend opcode (if
321 static int prev_insn_extended
;
323 /* Non-zero if the previous previous instruction was in a .set
325 static int prev_prev_insn_unreordered
;
327 /* For ECOFF and ELF, relocations against symbols are done in two
328 parts, with a HI relocation and a LO relocation. Each relocation
329 has only 16 bits of space to store an addend. This means that in
330 order for the linker to handle carries correctly, it must be able
331 to locate both the HI and the LO relocation. This means that the
332 relocations must appear in order in the relocation table.
334 In order to implement this, we keep track of each unmatched HI
335 relocation. We then sort them so that they immediately precede the
336 corresponding LO relocation. */
341 struct mips_hi_fixup
*next
;
344 /* The section this fixup is in. */
348 /* The list of unmatched HI relocs. */
350 static struct mips_hi_fixup
*mips_hi_fixup_list
;
352 /* Map normal MIPS register numbers to mips16 register numbers. */
354 #define X ILLEGAL_REG
355 static const int mips32_to_16_reg_map
[] =
357 X
, X
, 2, 3, 4, 5, 6, 7,
358 X
, X
, X
, X
, X
, X
, X
, X
,
359 0, 1, X
, X
, X
, X
, X
, X
,
360 X
, X
, X
, X
, X
, X
, X
, X
364 /* Map mips16 register numbers to normal MIPS register numbers. */
366 static const int mips16_to_32_reg_map
[] =
368 16, 17, 2, 3, 4, 5, 6, 7
371 /* Since the MIPS does not have multiple forms of PC relative
372 instructions, we do not have to do relaxing as is done on other
373 platforms. However, we do have to handle GP relative addressing
374 correctly, which turns out to be a similar problem.
376 Every macro that refers to a symbol can occur in (at least) two
377 forms, one with GP relative addressing and one without. For
378 example, loading a global variable into a register generally uses
379 a macro instruction like this:
381 If i can be addressed off the GP register (this is true if it is in
382 the .sbss or .sdata section, or if it is known to be smaller than
383 the -G argument) this will generate the following instruction:
385 This instruction will use a GPREL reloc. If i can not be addressed
386 off the GP register, the following instruction sequence will be used:
389 In this case the first instruction will have a HI16 reloc, and the
390 second reloc will have a LO16 reloc. Both relocs will be against
393 The issue here is that we may not know whether i is GP addressable
394 until after we see the instruction that uses it. Therefore, we
395 want to be able to choose the final instruction sequence only at
396 the end of the assembly. This is similar to the way other
397 platforms choose the size of a PC relative instruction only at the
400 When generating position independent code we do not use GP
401 addressing in quite the same way, but the issue still arises as
402 external symbols and local symbols must be handled differently.
404 We handle these issues by actually generating both possible
405 instruction sequences. The longer one is put in a frag_var with
406 type rs_machine_dependent. We encode what to do with the frag in
407 the subtype field. We encode (1) the number of existing bytes to
408 replace, (2) the number of new bytes to use, (3) the offset from
409 the start of the existing bytes to the first reloc we must generate
410 (that is, the offset is applied from the start of the existing
411 bytes after they are replaced by the new bytes, if any), (4) the
412 offset from the start of the existing bytes to the second reloc,
413 (5) whether a third reloc is needed (the third reloc is always four
414 bytes after the second reloc), and (6) whether to warn if this
415 variant is used (this is sometimes needed if .set nomacro or .set
416 noat is in effect). All these numbers are reasonably small.
418 Generating two instruction sequences must be handled carefully to
419 ensure that delay slots are handled correctly. Fortunately, there
420 are a limited number of cases. When the second instruction
421 sequence is generated, append_insn is directed to maintain the
422 existing delay slot information, so it continues to apply to any
423 code after the second instruction sequence. This means that the
424 second instruction sequence must not impose any requirements not
425 required by the first instruction sequence.
427 These variant frags are then handled in functions called by the
428 machine independent code. md_estimate_size_before_relax returns
429 the final size of the frag. md_convert_frag sets up the final form
430 of the frag. tc_gen_reloc adjust the first reloc and adds a second
432 #define RELAX_ENCODE(old, new, reloc1, reloc2, reloc3, warn) \
436 | (((reloc1) + 64) << 9) \
437 | (((reloc2) + 64) << 2) \
438 | ((reloc3) ? (1 << 1) : 0) \
440 #define RELAX_OLD(i) (((i) >> 23) & 0x7f)
441 #define RELAX_NEW(i) (((i) >> 16) & 0x7f)
442 #define RELAX_RELOC1(i) ((bfd_vma)(((i) >> 9) & 0x7f) - 64)
443 #define RELAX_RELOC2(i) ((bfd_vma)(((i) >> 2) & 0x7f) - 64)
444 #define RELAX_RELOC3(i) (((i) >> 1) & 1)
445 #define RELAX_WARN(i) ((i) & 1)
447 /* For mips16 code, we use an entirely different form of relaxation.
448 mips16 supports two versions of most instructions which take
449 immediate values: a small one which takes some small value, and a
450 larger one which takes a 16 bit value. Since branches also follow
451 this pattern, relaxing these values is required.
453 We can assemble both mips16 and normal MIPS code in a single
454 object. Therefore, we need to support this type of relaxation at
455 the same time that we support the relaxation described above. We
456 use the high bit of the subtype field to distinguish these cases.
458 The information we store for this type of relaxation is the
459 argument code found in the opcode file for this relocation, whether
460 the user explicitly requested a small or extended form, and whether
461 the relocation is in a jump or jal delay slot. That tells us the
462 size of the value, and how it should be stored. We also store
463 whether the fragment is considered to be extended or not. We also
464 store whether this is known to be a branch to a different section,
465 whether we have tried to relax this frag yet, and whether we have
466 ever extended a PC relative fragment because of a shift count. */
467 #define RELAX_MIPS16_ENCODE(type, small, ext, dslot, jal_dslot) \
470 | ((small) ? 0x100 : 0) \
471 | ((ext) ? 0x200 : 0) \
472 | ((dslot) ? 0x400 : 0) \
473 | ((jal_dslot) ? 0x800 : 0))
474 #define RELAX_MIPS16_P(i) (((i) & 0x80000000) != 0)
475 #define RELAX_MIPS16_TYPE(i) ((i) & 0xff)
476 #define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x100) != 0)
477 #define RELAX_MIPS16_USER_EXT(i) (((i) & 0x200) != 0)
478 #define RELAX_MIPS16_DSLOT(i) (((i) & 0x400) != 0)
479 #define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x800) != 0)
480 #define RELAX_MIPS16_EXTENDED(i) (((i) & 0x1000) != 0)
481 #define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x1000)
482 #define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) &~ 0x1000)
483 #define RELAX_MIPS16_LONG_BRANCH(i) (((i) & 0x2000) != 0)
484 #define RELAX_MIPS16_MARK_LONG_BRANCH(i) ((i) | 0x2000)
485 #define RELAX_MIPS16_CLEAR_LONG_BRANCH(i) ((i) &~ 0x2000)
487 /* Prototypes for static functions. */
490 #define internalError() \
491 as_fatal ("internal Error, line %d, %s", __LINE__, __FILE__)
493 #define internalError() as_fatal ("MIPS internal Error");
496 enum mips_regclass
{ MIPS_GR_REG
, MIPS_FP_REG
, MIPS16_REG
};
498 static int insn_uses_reg
PARAMS ((struct mips_cl_insn
*ip
,
499 unsigned int reg
, enum mips_regclass
class));
500 static int reg_needs_delay
PARAMS ((int));
501 static void append_insn
PARAMS ((char *place
,
502 struct mips_cl_insn
* ip
,
504 bfd_reloc_code_real_type r
,
506 static void mips_no_prev_insn
PARAMS ((void));
507 static void mips_emit_delays
PARAMS ((void));
509 static void macro_build
PARAMS ((char *place
, int *counter
, expressionS
* ep
,
510 const char *name
, const char *fmt
,
513 static void macro_build ();
515 static void mips16_macro_build
PARAMS ((char *, int *, expressionS
*,
516 const char *, const char *,
518 static void macro_build_lui
PARAMS ((char *place
, int *counter
,
519 expressionS
* ep
, int regnum
));
520 static void set_at
PARAMS ((int *counter
, int reg
, int unsignedp
));
521 static void check_absolute_expr
PARAMS ((struct mips_cl_insn
* ip
,
523 static void load_register
PARAMS ((int *, int, expressionS
*, int));
524 static void load_address
PARAMS ((int *counter
, int reg
, expressionS
*ep
));
525 static void macro
PARAMS ((struct mips_cl_insn
* ip
));
526 static void mips16_macro
PARAMS ((struct mips_cl_insn
* ip
));
527 #ifdef LOSING_COMPILER
528 static void macro2
PARAMS ((struct mips_cl_insn
* ip
));
530 static void mips_ip
PARAMS ((char *str
, struct mips_cl_insn
* ip
));
531 static void mips16_ip
PARAMS ((char *str
, struct mips_cl_insn
* ip
));
532 static void mips16_immed
PARAMS ((char *, unsigned int, int, offsetT
, boolean
,
533 boolean
, boolean
, unsigned long *,
534 boolean
*, unsigned short *));
535 static int my_getSmallExpression
PARAMS ((expressionS
* ep
, char *str
));
536 static void my_getExpression
PARAMS ((expressionS
* ep
, char *str
));
537 static symbolS
*get_symbol
PARAMS ((void));
538 static void mips_align
PARAMS ((int to
, int fill
, symbolS
*label
));
539 static void s_align
PARAMS ((int));
540 static void s_change_sec
PARAMS ((int));
541 static void s_cons
PARAMS ((int));
542 static void s_float_cons
PARAMS ((int));
543 static void s_mips_globl
PARAMS ((int));
544 static void s_option
PARAMS ((int));
545 static void s_mipsset
PARAMS ((int));
546 static void s_abicalls
PARAMS ((int));
547 static void s_cpload
PARAMS ((int));
548 static void s_cprestore
PARAMS ((int));
549 static void s_gpword
PARAMS ((int));
550 static void s_cpadd
PARAMS ((int));
551 static void md_obj_begin
PARAMS ((void));
552 static void md_obj_end
PARAMS ((void));
553 static long get_number
PARAMS ((void));
554 static void s_ent
PARAMS ((int));
555 static void s_mipsend
PARAMS ((int));
556 static void s_file
PARAMS ((int));
557 static int mips16_extended_frag
PARAMS ((fragS
*, asection
*, long));
561 The following pseudo-ops from the Kane and Heinrich MIPS book
562 should be defined here, but are currently unsupported: .alias,
563 .galive, .gjaldef, .gjrlive, .livereg, .noalias.
565 The following pseudo-ops from the Kane and Heinrich MIPS book are
566 specific to the type of debugging information being generated, and
567 should be defined by the object format: .aent, .begin, .bend,
568 .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp,
571 The following pseudo-ops from the Kane and Heinrich MIPS book are
572 not MIPS CPU specific, but are also not specific to the object file
573 format. This file is probably the best place to define them, but
574 they are not currently supported: .asm0, .endr, .lab, .repeat,
575 .struct, .weakext. */
577 static const pseudo_typeS mips_pseudo_table
[] =
579 /* MIPS specific pseudo-ops. */
580 {"option", s_option
, 0},
581 {"set", s_mipsset
, 0},
582 {"rdata", s_change_sec
, 'r'},
583 {"sdata", s_change_sec
, 's'},
584 {"livereg", s_ignore
, 0},
585 {"abicalls", s_abicalls
, 0},
586 {"cpload", s_cpload
, 0},
587 {"cprestore", s_cprestore
, 0},
588 {"gpword", s_gpword
, 0},
589 {"cpadd", s_cpadd
, 0},
591 /* Relatively generic pseudo-ops that happen to be used on MIPS
593 {"asciiz", stringer
, 1},
594 {"bss", s_change_sec
, 'b'},
597 {"dword", s_cons
, 3},
599 /* These pseudo-ops are defined in read.c, but must be overridden
600 here for one reason or another. */
601 {"align", s_align
, 0},
603 {"data", s_change_sec
, 'd'},
604 {"double", s_float_cons
, 'd'},
605 {"float", s_float_cons
, 'f'},
606 {"globl", s_mips_globl
, 0},
607 {"global", s_mips_globl
, 0},
608 {"hword", s_cons
, 1},
613 {"short", s_cons
, 1},
614 {"single", s_float_cons
, 'f'},
615 {"text", s_change_sec
, 't'},
620 static const pseudo_typeS mips_nonecoff_pseudo_table
[] = {
621 /* These pseudo-ops should be defined by the object file format.
622 However, a.out doesn't support them, so we have versions here. */
624 {"bgnb", s_ignore
, 0},
625 {"end", s_mipsend
, 0},
626 {"endb", s_ignore
, 0},
629 {"fmask", s_ignore
, 'F'},
630 {"frame", s_ignore
, 0},
631 {"loc", s_ignore
, 0},
632 {"mask", s_ignore
, 'R'},
633 {"verstamp", s_ignore
, 0},
637 extern void pop_insert
PARAMS ((const pseudo_typeS
*));
642 pop_insert (mips_pseudo_table
);
643 if (! ECOFF_DEBUGGING
)
644 pop_insert (mips_nonecoff_pseudo_table
);
647 static char *expr_end
;
649 /* Expressions which appear in instructions. These are set by
652 static expressionS imm_expr
;
653 static expressionS offset_expr
;
655 /* Relocs associated with imm_expr and offset_expr. */
657 static bfd_reloc_code_real_type imm_reloc
;
658 static bfd_reloc_code_real_type offset_reloc
;
660 /* This is set by mips_ip if imm_reloc is an unmatched HI16_S reloc. */
662 static boolean imm_unmatched_hi
;
664 /* These are set by mips16_ip if an explicit extension is used. */
666 static boolean mips16_small
, mips16_ext
;
669 * This function is called once, at assembler startup time. It should
670 * set up all the tables, etc. that the MD part of the assembler will need.
676 register const char *retval
= NULL
;
677 register unsigned int i
= 0;
685 if (strcmp (cpu
+ (sizeof TARGET_CPU
) - 3, "el") == 0)
687 a
= xmalloc (sizeof TARGET_CPU
);
688 strcpy (a
, TARGET_CPU
);
689 a
[(sizeof TARGET_CPU
) - 3] = '\0';
693 if (strcmp (cpu
, "mips") == 0)
699 else if (strcmp (cpu
, "r6000") == 0
700 || strcmp (cpu
, "mips2") == 0)
706 else if (strcmp (cpu
, "mips64") == 0
707 || strcmp (cpu
, "r4000") == 0
708 || strcmp (cpu
, "mips3") == 0)
714 else if (strcmp (cpu
, "r4400") == 0)
720 else if (strcmp (cpu
, "mips64orion") == 0
721 || strcmp (cpu
, "r4600") == 0)
727 else if (strcmp (cpu
, "r4650") == 0)
735 else if (strcmp (cpu
, "mips64vr4300") == 0)
741 else if (strcmp (cpu
, "mips64vr4100") == 0)
749 else if (strcmp (cpu
, "r4010") == 0)
757 else if (strcmp (cpu
, "r5000") == 0
758 || strcmp (cpu
, "mips64vr5000") == 0)
764 else if (strcmp (cpu
, "r8000") == 0
765 || strcmp (cpu
, "mips4") == 0)
771 else if (strcmp (cpu
, "r10000") == 0)
777 else if (strcmp (cpu
, "mips16") == 0)
781 mips_cpu
= 0; /* FIXME */
796 if (strncmp (TARGET_CPU
, "mips16", sizeof "mips16" - 1) == 0)
811 if (mips_4650
|| mips_4010
|| mips_4100
|| mips_cpu
== 4300)
816 if (mips_cpu
== 4300)
821 if (mips_isa
< 2 && mips_trap
)
822 as_bad ("trap exception not supported at ISA 1");
827 ok
= bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, 3000);
830 ok
= bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, 6000);
833 ok
= bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, 4000);
836 ok
= bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, 8000);
840 as_warn ("Could not set architecture and machine");
842 file_mips_isa
= mips_isa
;
844 op_hash
= hash_new ();
846 for (i
= 0; i
< NUMOPCODES
;)
848 const char *name
= mips_opcodes
[i
].name
;
850 retval
= hash_insert (op_hash
, name
, (PTR
) &mips_opcodes
[i
]);
853 fprintf (stderr
, "internal error: can't hash `%s': %s\n",
854 mips_opcodes
[i
].name
, retval
);
855 as_fatal ("Broken assembler. No assembly attempted.");
859 if (mips_opcodes
[i
].pinfo
!= INSN_MACRO
860 && ((mips_opcodes
[i
].match
& mips_opcodes
[i
].mask
)
861 != mips_opcodes
[i
].match
))
863 fprintf (stderr
, "internal error: bad opcode: `%s' \"%s\"\n",
864 mips_opcodes
[i
].name
, mips_opcodes
[i
].args
);
865 as_fatal ("Broken assembler. No assembly attempted.");
869 while ((i
< NUMOPCODES
) && !strcmp (mips_opcodes
[i
].name
, name
));
872 mips16_op_hash
= hash_new ();
875 while (i
< bfd_mips16_num_opcodes
)
877 const char *name
= mips16_opcodes
[i
].name
;
879 retval
= hash_insert (mips16_op_hash
, name
, (PTR
) &mips16_opcodes
[i
]);
881 as_fatal ("internal error: can't hash `%s': %s\n",
882 mips16_opcodes
[i
].name
, retval
);
885 if (mips16_opcodes
[i
].pinfo
!= INSN_MACRO
886 && ((mips16_opcodes
[i
].match
& mips16_opcodes
[i
].mask
)
887 != mips16_opcodes
[i
].match
))
888 as_fatal ("internal error: bad opcode: `%s' \"%s\"\n",
889 mips16_opcodes
[i
].name
, mips16_opcodes
[i
].args
);
892 while (i
< bfd_mips16_num_opcodes
893 && strcmp (mips16_opcodes
[i
].name
, name
) == 0);
896 mips_no_prev_insn ();
904 /* set the default alignment for the text section (2**2) */
905 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
906 record_alignment (text_section
, 2);
908 if (USE_GLOBAL_POINTER_OPT
)
909 bfd_set_gp_size (stdoutput
, g_switch_value
);
911 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
913 /* On a native system, sections must be aligned to 16 byte
914 boundaries. When configured for an embedded ELF target, we
916 if (strcmp (TARGET_OS
, "elf") != 0)
918 (void) bfd_set_section_alignment (stdoutput
, text_section
, 4);
919 (void) bfd_set_section_alignment (stdoutput
, data_section
, 4);
920 (void) bfd_set_section_alignment (stdoutput
, bss_section
, 4);
923 /* Create a .reginfo section for register masks and a .mdebug
924 section for debugging information. */
935 sec
= subseg_new (".reginfo", (subsegT
) 0);
937 /* The ABI says this section should be loaded so that the
938 running program can access it. */
939 (void) bfd_set_section_flags (stdoutput
, sec
,
940 (SEC_ALLOC
| SEC_LOAD
941 | SEC_READONLY
| SEC_DATA
));
942 (void) bfd_set_section_alignment (stdoutput
, sec
, 2);
945 mips_regmask_frag
= frag_more (sizeof (Elf32_External_RegInfo
));
950 /* The 64-bit ABI uses a .MIPS.options section rather than
952 sec
= subseg_new (".MIPS.options", (subsegT
) 0);
953 (void) bfd_set_section_flags (stdoutput
, sec
,
954 (SEC_ALLOC
| SEC_LOAD
955 | SEC_READONLY
| SEC_DATA
));
956 (void) bfd_set_section_alignment (stdoutput
, sec
, 3);
959 /* Set up the option header. */
961 Elf_Internal_Options opthdr
;
964 opthdr
.kind
= ODK_REGINFO
;
965 opthdr
.size
= (sizeof (Elf_External_Options
)
966 + sizeof (Elf64_External_RegInfo
));
969 f
= frag_more (sizeof (Elf_External_Options
));
970 bfd_mips_elf_swap_options_out (stdoutput
, &opthdr
,
971 (Elf_External_Options
*) f
);
973 mips_regmask_frag
= frag_more (sizeof (Elf64_External_RegInfo
));
980 sec
= subseg_new (".mdebug", (subsegT
) 0);
981 (void) bfd_set_section_flags (stdoutput
, sec
,
982 SEC_HAS_CONTENTS
| SEC_READONLY
);
983 (void) bfd_set_section_alignment (stdoutput
, sec
, 2);
986 subseg_set (seg
, subseg
);
990 if (! ECOFF_DEBUGGING
)
997 if (! ECOFF_DEBUGGING
)
1005 struct mips_cl_insn insn
;
1007 imm_expr
.X_op
= O_absent
;
1008 imm_reloc
= BFD_RELOC_UNUSED
;
1009 imm_unmatched_hi
= false;
1010 offset_expr
.X_op
= O_absent
;
1011 offset_reloc
= BFD_RELOC_UNUSED
;
1014 mips16_ip (str
, &insn
);
1016 mips_ip (str
, &insn
);
1020 as_bad ("%s `%s'", insn_error
, str
);
1024 if (insn
.insn_mo
->pinfo
== INSN_MACRO
)
1027 mips16_macro (&insn
);
1033 if (imm_expr
.X_op
!= O_absent
)
1034 append_insn ((char *) NULL
, &insn
, &imm_expr
, imm_reloc
,
1036 else if (offset_expr
.X_op
!= O_absent
)
1037 append_insn ((char *) NULL
, &insn
, &offset_expr
, offset_reloc
, false);
1039 append_insn ((char *) NULL
, &insn
, NULL
, BFD_RELOC_UNUSED
, false);
1043 /* See whether instruction IP reads register REG. CLASS is the type
1047 insn_uses_reg (ip
, reg
, class)
1048 struct mips_cl_insn
*ip
;
1050 enum mips_regclass
class;
1052 if (class == MIPS16_REG
)
1055 reg
= mips16_to_32_reg_map
[reg
];
1056 class = MIPS_GR_REG
;
1059 /* Don't report on general register 0, since it never changes. */
1060 if (class == MIPS_GR_REG
&& reg
== 0)
1063 if (class == MIPS_FP_REG
)
1066 /* If we are called with either $f0 or $f1, we must check $f0.
1067 This is not optimal, because it will introduce an unnecessary
1068 NOP between "lwc1 $f0" and "swc1 $f1". To fix this we would
1069 need to distinguish reading both $f0 and $f1 or just one of
1070 them. Note that we don't have to check the other way,
1071 because there is no instruction that sets both $f0 and $f1
1072 and requires a delay. */
1073 if ((ip
->insn_mo
->pinfo
& INSN_READ_FPR_S
)
1074 && (((ip
->insn_opcode
>> OP_SH_FS
) & OP_MASK_FS
)
1075 == (reg
&~ (unsigned) 1)))
1077 if ((ip
->insn_mo
->pinfo
& INSN_READ_FPR_T
)
1078 && (((ip
->insn_opcode
>> OP_SH_FT
) & OP_MASK_FT
)
1079 == (reg
&~ (unsigned) 1)))
1084 if ((ip
->insn_mo
->pinfo
& INSN_READ_GPR_S
)
1085 && ((ip
->insn_opcode
>> OP_SH_RS
) & OP_MASK_RS
) == reg
)
1087 if ((ip
->insn_mo
->pinfo
& INSN_READ_GPR_T
)
1088 && ((ip
->insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
) == reg
)
1093 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_X
)
1094 && ((ip
->insn_opcode
>> MIPS16OP_SH_RX
) & MIPS16OP_MASK_RX
) == reg
)
1096 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_Y
)
1097 && ((ip
->insn_opcode
>> MIPS16OP_SH_RY
) & MIPS16OP_MASK_RY
) == reg
)
1099 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_Z
)
1100 && ((ip
->insn_opcode
>> MIPS16OP_SH_MOVE32Z
)
1101 & MIPS16OP_MASK_MOVE32Z
) == reg
)
1103 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_T
) && reg
== TREG
)
1105 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_SP
) && reg
== SP
)
1107 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_31
) && reg
== RA
)
1109 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_GPR_X
)
1110 && ((ip
->insn_opcode
>> MIPS16OP_SH_REGR32
)
1111 & MIPS16OP_MASK_REGR32
) == reg
)
1118 /* This function returns true if modifying a register requires a
1122 reg_needs_delay (reg
)
1125 unsigned long prev_pinfo
;
1127 prev_pinfo
= prev_insn
.insn_mo
->pinfo
;
1128 if (! mips_noreorder
1130 && ((prev_pinfo
& INSN_LOAD_COPROC_DELAY
)
1132 && (prev_pinfo
& INSN_LOAD_MEMORY_DELAY
))))
1134 /* A load from a coprocessor or from memory. All load
1135 delays delay the use of general register rt for one
1136 instruction on the r3000. The r6000 and r4000 use
1138 know (prev_pinfo
& INSN_WRITE_GPR_T
);
1139 if (reg
== ((prev_insn
.insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
))
1146 /* Output an instruction. PLACE is where to put the instruction; if
1147 it is NULL, this uses frag_more to get room. IP is the instruction
1148 information. ADDRESS_EXPR is an operand of the instruction to be
1149 used with RELOC_TYPE. */
1152 append_insn (place
, ip
, address_expr
, reloc_type
, unmatched_hi
)
1154 struct mips_cl_insn
*ip
;
1155 expressionS
*address_expr
;
1156 bfd_reloc_code_real_type reloc_type
;
1157 boolean unmatched_hi
;
1159 register unsigned long prev_pinfo
, pinfo
;
1164 /* Make sure the section will be aligned appropriately. Note that
1165 we do not insert an alignment directive; it remains the user's
1166 responsibility to align instructions if necessary. Here we only
1167 ensure that the section will have the right default alignment, so
1168 that the right thing will happen if no alignment directive is
1171 record_alignment (now_seg
, 1);
1173 record_alignment (now_seg
, 2);
1175 prev_pinfo
= prev_insn
.insn_mo
->pinfo
;
1176 pinfo
= ip
->insn_mo
->pinfo
;
1178 if (place
== NULL
&& ! mips_noreorder
)
1180 /* If the previous insn required any delay slots, see if we need
1181 to insert a NOP or two. There are eight kinds of possible
1182 hazards, of which an instruction can have at most one type.
1183 (1) a load from memory delay
1184 (2) a load from a coprocessor delay
1185 (3) an unconditional branch delay
1186 (4) a conditional branch delay
1187 (5) a move to coprocessor register delay
1188 (6) a load coprocessor register from memory delay
1189 (7) a coprocessor condition code delay
1190 (8) a HI/LO special register delay
1192 There are a lot of optimizations we could do that we don't.
1193 In particular, we do not, in general, reorder instructions.
1194 If you use gcc with optimization, it will reorder
1195 instructions and generally do much more optimization then we
1196 do here; repeating all that work in the assembler would only
1197 benefit hand written assembly code, and does not seem worth
1200 /* This is how a NOP is emitted. */
1201 #define emit_nop() \
1203 ? md_number_to_chars (frag_more (2), 0x6500, 2) \
1204 : md_number_to_chars (frag_more (4), 0, 4))
1206 /* The previous insn might require a delay slot, depending upon
1207 the contents of the current insn. */
1210 && (((prev_pinfo
& INSN_LOAD_COPROC_DELAY
)
1211 && ! cop_interlocks
)
1213 && (prev_pinfo
& INSN_LOAD_MEMORY_DELAY
))))
1215 /* A load from a coprocessor or from memory. All load
1216 delays delay the use of general register rt for one
1217 instruction on the r3000. The r6000 and r4000 use
1219 know (prev_pinfo
& INSN_WRITE_GPR_T
);
1220 if (mips_optimize
== 0
1221 || insn_uses_reg (ip
,
1222 ((prev_insn
.insn_opcode
>> OP_SH_RT
)
1229 && (((prev_pinfo
& INSN_COPROC_MOVE_DELAY
)
1230 && ! cop_interlocks
)
1232 && (prev_pinfo
& INSN_COPROC_MEMORY_DELAY
))))
1234 /* A generic coprocessor delay. The previous instruction
1235 modified a coprocessor general or control register. If
1236 it modified a control register, we need to avoid any
1237 coprocessor instruction (this is probably not always
1238 required, but it sometimes is). If it modified a general
1239 register, we avoid using that register.
1241 On the r6000 and r4000 loading a coprocessor register
1242 from memory is interlocked, and does not require a delay.
1244 This case is not handled very well. There is no special
1245 knowledge of CP0 handling, and the coprocessors other
1246 than the floating point unit are not distinguished at
1248 if (prev_pinfo
& INSN_WRITE_FPR_T
)
1250 if (mips_optimize
== 0
1251 || insn_uses_reg (ip
,
1252 ((prev_insn
.insn_opcode
>> OP_SH_FT
)
1257 else if (prev_pinfo
& INSN_WRITE_FPR_S
)
1259 if (mips_optimize
== 0
1260 || insn_uses_reg (ip
,
1261 ((prev_insn
.insn_opcode
>> OP_SH_FS
)
1268 /* We don't know exactly what the previous instruction
1269 does. If the current instruction uses a coprocessor
1270 register, we must insert a NOP. If previous
1271 instruction may set the condition codes, and the
1272 current instruction uses them, we must insert two
1274 if (mips_optimize
== 0
1275 || ((prev_pinfo
& INSN_WRITE_COND_CODE
)
1276 && (pinfo
& INSN_READ_COND_CODE
)))
1278 else if (pinfo
& INSN_COP
)
1284 && (prev_pinfo
& INSN_WRITE_COND_CODE
)
1285 && ! cop_interlocks
)
1287 /* The previous instruction sets the coprocessor condition
1288 codes, but does not require a general coprocessor delay
1289 (this means it is a floating point comparison
1290 instruction). If this instruction uses the condition
1291 codes, we need to insert a single NOP. */
1292 if (mips_optimize
== 0
1293 || (pinfo
& INSN_READ_COND_CODE
))
1296 else if (prev_pinfo
& INSN_READ_LO
)
1298 /* The previous instruction reads the LO register; if the
1299 current instruction writes to the LO register, we must
1300 insert two NOPS. Some newer processors have interlocks. */
1302 && (mips_optimize
== 0
1303 || (pinfo
& INSN_WRITE_LO
)))
1306 else if (prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
1308 /* The previous instruction reads the HI register; if the
1309 current instruction writes to the HI register, we must
1310 insert a NOP. Some newer processors have interlocks. */
1312 && (mips_optimize
== 0
1313 || (pinfo
& INSN_WRITE_HI
)))
1317 /* There are two cases which require two intervening
1318 instructions: 1) setting the condition codes using a move to
1319 coprocessor instruction which requires a general coprocessor
1320 delay and then reading the condition codes 2) reading the HI
1321 or LO register and then writing to it (except on processors
1322 which have interlocks). If we are not already emitting a NOP
1323 instruction, we must check for these cases compared to the
1324 instruction previous to the previous instruction. */
1328 && (prev_prev_insn
.insn_mo
->pinfo
& INSN_COPROC_MOVE_DELAY
)
1329 && (prev_prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
)
1330 && (pinfo
& INSN_READ_COND_CODE
)
1331 && ! cop_interlocks
)
1332 || ((prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
)
1333 && (pinfo
& INSN_WRITE_LO
)
1335 || ((prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
1336 && (pinfo
& INSN_WRITE_HI
)
1340 /* If we are being given a nop instruction, don't bother with
1341 one of the nops we would otherwise output. This will only
1342 happen when a nop instruction is used with mips_optimize set
1344 if (nops
> 0 && ip
->insn_opcode
== (mips16
? 0x6500 : 0))
1347 /* Now emit the right number of NOP instructions. */
1351 unsigned long old_frag_offset
;
1354 old_frag
= frag_now
;
1355 old_frag_offset
= frag_now_fix ();
1357 for (i
= 0; i
< nops
; i
++)
1362 listing_prev_line ();
1363 /* We may be at the start of a variant frag. In case we
1364 are, make sure there is enough space for the frag
1365 after the frags created by listing_prev_line. The
1366 argument to frag_grow here must be at least as large
1367 as the argument to all other calls to frag_grow in
1368 this file. We don't have to worry about being in the
1369 middle of a variant frag, because the variants insert
1370 all needed nop instructions themselves. */
1374 if (insn_label
!= NULL
)
1376 assert (S_GET_SEGMENT (insn_label
) == now_seg
);
1377 insn_label
->sy_frag
= frag_now
;
1378 S_SET_VALUE (insn_label
, (valueT
) frag_now_fix ());
1381 #ifndef NO_ECOFF_DEBUGGING
1382 if (ECOFF_DEBUGGING
)
1383 ecoff_fix_loc (old_frag
, old_frag_offset
);
1388 if (reloc_type
> BFD_RELOC_UNUSED
)
1390 /* We need to set up a variant frag. */
1391 assert (mips16
&& address_expr
!= NULL
);
1392 f
= frag_var (rs_machine_dependent
, 4, 0,
1393 RELAX_MIPS16_ENCODE (reloc_type
- BFD_RELOC_UNUSED
,
1394 mips16_small
, mips16_ext
,
1396 & INSN_UNCOND_BRANCH_DELAY
),
1397 (prev_insn_reloc_type
1398 == BFD_RELOC_MIPS16_JMP
)),
1399 make_expr_symbol (address_expr
), (long) 0,
1402 else if (place
!= NULL
)
1404 else if (mips16
&& ! ip
->use_extend
&& reloc_type
!= BFD_RELOC_MIPS16_JMP
)
1406 /* Make sure there is enough room to swap this instruction with
1407 a following jump instruction. */
1414 if (address_expr
!= NULL
&& reloc_type
< BFD_RELOC_UNUSED
)
1416 if (address_expr
->X_op
== O_constant
)
1421 ip
->insn_opcode
|= address_expr
->X_add_number
;
1424 case BFD_RELOC_LO16
:
1425 ip
->insn_opcode
|= address_expr
->X_add_number
& 0xffff;
1428 case BFD_RELOC_MIPS_JMP
:
1429 ip
->insn_opcode
|= (address_expr
->X_add_number
>> 2) & 0x3ffffff;
1432 case BFD_RELOC_MIPS16_JMP
:
1434 (((address_expr
->X_add_number
& 0x7c0000) << 3)
1435 | ((address_expr
->X_add_number
& 0xf800000) >> 7)
1436 | ((address_expr
->X_add_number
& 0x3fffc) >> 2));
1439 case BFD_RELOC_16_PCREL_S2
:
1449 /* Don't generate a reloc if we are writing into a variant
1453 fixp
= fix_new_exp (frag_now
, f
- frag_now
->fr_literal
, 4,
1455 reloc_type
== BFD_RELOC_16_PCREL_S2
,
1459 struct mips_hi_fixup
*hi_fixup
;
1461 assert (reloc_type
== BFD_RELOC_HI16_S
);
1462 hi_fixup
= ((struct mips_hi_fixup
*)
1463 xmalloc (sizeof (struct mips_hi_fixup
)));
1464 hi_fixup
->fixp
= fixp
;
1465 hi_fixup
->seg
= now_seg
;
1466 hi_fixup
->next
= mips_hi_fixup_list
;
1467 mips_hi_fixup_list
= hi_fixup
;
1473 if (! mips16
|| reloc_type
== BFD_RELOC_MIPS16_JMP
)
1474 md_number_to_chars (f
, ip
->insn_opcode
, 4);
1479 md_number_to_chars (f
, 0xf000 | ip
->extend
, 2);
1482 md_number_to_chars (f
, ip
->insn_opcode
, 2);
1485 /* Update the register mask information. */
1488 if (pinfo
& INSN_WRITE_GPR_D
)
1489 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
);
1490 if ((pinfo
& (INSN_WRITE_GPR_T
| INSN_READ_GPR_T
)) != 0)
1491 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
);
1492 if (pinfo
& INSN_READ_GPR_S
)
1493 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> OP_SH_RS
) & OP_MASK_RS
);
1494 if (pinfo
& INSN_WRITE_GPR_31
)
1495 mips_gprmask
|= 1 << 31;
1496 if (pinfo
& INSN_WRITE_FPR_D
)
1497 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FD
) & OP_MASK_FD
);
1498 if ((pinfo
& (INSN_WRITE_FPR_S
| INSN_READ_FPR_S
)) != 0)
1499 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FS
) & OP_MASK_FS
);
1500 if ((pinfo
& (INSN_WRITE_FPR_T
| INSN_READ_FPR_T
)) != 0)
1501 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FT
) & OP_MASK_FT
);
1502 if ((pinfo
& INSN_READ_FPR_R
) != 0)
1503 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FR
) & OP_MASK_FR
);
1504 if (pinfo
& INSN_COP
)
1506 /* We don't keep enough information to sort these cases out. */
1508 /* Never set the bit for $0, which is always zero. */
1509 mips_gprmask
&=~ 1 << 0;
1513 if (pinfo
& (MIPS16_INSN_WRITE_X
| MIPS16_INSN_READ_X
))
1514 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_RX
)
1515 & MIPS16OP_MASK_RX
);
1516 if (pinfo
& (MIPS16_INSN_WRITE_Y
| MIPS16_INSN_READ_Y
))
1517 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_RY
)
1518 & MIPS16OP_MASK_RY
);
1519 if (pinfo
& MIPS16_INSN_WRITE_Z
)
1520 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_RZ
)
1521 & MIPS16OP_MASK_RZ
);
1522 if (pinfo
& (MIPS16_INSN_WRITE_T
| MIPS16_INSN_READ_T
))
1523 mips_gprmask
|= 1 << TREG
;
1524 if (pinfo
& (MIPS16_INSN_WRITE_SP
| MIPS16_INSN_READ_SP
))
1525 mips_gprmask
|= 1 << SP
;
1526 if (pinfo
& (MIPS16_INSN_WRITE_31
| MIPS16_INSN_READ_31
))
1527 mips_gprmask
|= 1 << RA
;
1528 if (pinfo
& MIPS16_INSN_WRITE_GPR_Y
)
1529 mips_gprmask
|= 1 << MIPS16OP_EXTRACT_REG32R (ip
->insn_opcode
);
1530 if (pinfo
& MIPS16_INSN_READ_Z
)
1531 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_MOVE32Z
)
1532 & MIPS16OP_MASK_MOVE32Z
);
1533 if (pinfo
& MIPS16_INSN_READ_GPR_X
)
1534 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_REGR32
)
1535 & MIPS16OP_MASK_REGR32
);
1538 if (place
== NULL
&& ! mips_noreorder
)
1540 /* Filling the branch delay slot is more complex. We try to
1541 switch the branch with the previous instruction, which we can
1542 do if the previous instruction does not set up a condition
1543 that the branch tests and if the branch is not itself the
1544 target of any branch. */
1545 if ((pinfo
& INSN_UNCOND_BRANCH_DELAY
)
1546 || (pinfo
& INSN_COND_BRANCH_DELAY
))
1548 if (mips_optimize
< 2
1549 /* If we have seen .set volatile or .set nomove, don't
1552 /* If we had to emit any NOP instructions, then we
1553 already know we can not swap. */
1555 /* If we don't even know the previous insn, we can not
1557 || ! prev_insn_valid
1558 /* If the previous insn is already in a branch delay
1559 slot, then we can not swap. */
1560 || prev_insn_is_delay_slot
1561 /* If the previous previous insn was in a .set
1562 noreorder, we can't swap. Actually, the MIPS
1563 assembler will swap in this situation. However, gcc
1564 configured -with-gnu-as will generate code like
1570 in which we can not swap the bne and INSN. If gcc is
1571 not configured -with-gnu-as, it does not output the
1572 .set pseudo-ops. We don't have to check
1573 prev_insn_unreordered, because prev_insn_valid will
1574 be 0 in that case. We don't want to use
1575 prev_prev_insn_valid, because we do want to be able
1576 to swap at the start of a function. */
1577 || prev_prev_insn_unreordered
1578 /* If the branch is itself the target of a branch, we
1579 can not swap. We cheat on this; all we check for is
1580 whether there is a label on this instruction. If
1581 there are any branches to anything other than a
1582 label, users must use .set noreorder. */
1583 || insn_label
!= NULL
1584 /* If the previous instruction is in a variant frag, we
1585 can not do the swap. This does not apply to the
1586 mips16, which uses variant frags for different
1589 && prev_insn_frag
->fr_type
== rs_machine_dependent
)
1590 /* If the branch reads the condition codes, we don't
1591 even try to swap, because in the sequence
1596 we can not swap, and I don't feel like handling that
1600 && (pinfo
& INSN_READ_COND_CODE
))
1601 /* We can not swap with an instruction that requires a
1602 delay slot, becase the target of the branch might
1603 interfere with that instruction. */
1607 & (INSN_LOAD_COPROC_DELAY
1608 | INSN_COPROC_MOVE_DELAY
1609 | INSN_WRITE_COND_CODE
)))
1617 & (INSN_LOAD_MEMORY_DELAY
1618 | INSN_COPROC_MEMORY_DELAY
)))
1619 /* We can not swap with a branch instruction. */
1621 & (INSN_UNCOND_BRANCH_DELAY
1622 | INSN_COND_BRANCH_DELAY
1623 | INSN_COND_BRANCH_LIKELY
))
1624 /* We do not swap with a trap instruction, since it
1625 complicates trap handlers to have the trap
1626 instruction be in a delay slot. */
1627 || (prev_pinfo
& INSN_TRAP
)
1628 /* If the branch reads a register that the previous
1629 instruction sets, we can not swap. */
1631 && (prev_pinfo
& INSN_WRITE_GPR_T
)
1632 && insn_uses_reg (ip
,
1633 ((prev_insn
.insn_opcode
>> OP_SH_RT
)
1637 && (prev_pinfo
& INSN_WRITE_GPR_D
)
1638 && insn_uses_reg (ip
,
1639 ((prev_insn
.insn_opcode
>> OP_SH_RD
)
1643 && (((prev_pinfo
& MIPS16_INSN_WRITE_X
)
1644 && insn_uses_reg (ip
,
1645 ((prev_insn
.insn_opcode
1647 & MIPS16OP_MASK_RX
),
1649 || ((prev_pinfo
& MIPS16_INSN_WRITE_Y
)
1650 && insn_uses_reg (ip
,
1651 ((prev_insn
.insn_opcode
1653 & MIPS16OP_MASK_RY
),
1655 || ((prev_pinfo
& MIPS16_INSN_WRITE_Z
)
1656 && insn_uses_reg (ip
,
1657 ((prev_insn
.insn_opcode
1659 & MIPS16OP_MASK_RZ
),
1661 || ((prev_pinfo
& MIPS16_INSN_WRITE_T
)
1662 && insn_uses_reg (ip
, TREG
, MIPS_GR_REG
))
1663 || ((prev_pinfo
& MIPS16_INSN_WRITE_31
)
1664 && insn_uses_reg (ip
, RA
, MIPS_GR_REG
))
1665 || ((prev_pinfo
& MIPS16_INSN_WRITE_GPR_Y
)
1666 && insn_uses_reg (ip
,
1667 MIPS16OP_EXTRACT_REG32R (prev_insn
.
1670 /* If the branch writes a register that the previous
1671 instruction sets, we can not swap (we know that
1672 branches write only to RD or to $31). */
1674 && (prev_pinfo
& INSN_WRITE_GPR_T
)
1675 && (((pinfo
& INSN_WRITE_GPR_D
)
1676 && (((prev_insn
.insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
)
1677 == ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)))
1678 || ((pinfo
& INSN_WRITE_GPR_31
)
1679 && (((prev_insn
.insn_opcode
>> OP_SH_RT
)
1683 && (prev_pinfo
& INSN_WRITE_GPR_D
)
1684 && (((pinfo
& INSN_WRITE_GPR_D
)
1685 && (((prev_insn
.insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)
1686 == ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)))
1687 || ((pinfo
& INSN_WRITE_GPR_31
)
1688 && (((prev_insn
.insn_opcode
>> OP_SH_RD
)
1692 && (pinfo
& MIPS16_INSN_WRITE_31
)
1693 && ((prev_pinfo
& MIPS16_INSN_WRITE_31
)
1694 || ((prev_pinfo
& MIPS16_INSN_WRITE_GPR_Y
)
1695 && (MIPS16OP_EXTRACT_REG32R (prev_insn
.insn_opcode
)
1697 /* If the branch writes a register that the previous
1698 instruction reads, we can not swap (we know that
1699 branches only write to RD or to $31). */
1701 && (pinfo
& INSN_WRITE_GPR_D
)
1702 && insn_uses_reg (&prev_insn
,
1703 ((ip
->insn_opcode
>> OP_SH_RD
)
1707 && (pinfo
& INSN_WRITE_GPR_31
)
1708 && insn_uses_reg (&prev_insn
, 31, MIPS_GR_REG
))
1710 && (pinfo
& MIPS16_INSN_WRITE_31
)
1711 && insn_uses_reg (&prev_insn
, RA
, MIPS_GR_REG
))
1712 /* If we are generating embedded PIC code, the branch
1713 might be expanded into a sequence which uses $at, so
1714 we can't swap with an instruction which reads it. */
1715 || (mips_pic
== EMBEDDED_PIC
1716 && insn_uses_reg (&prev_insn
, AT
, MIPS_GR_REG
))
1717 /* If the previous previous instruction has a load
1718 delay, and sets a register that the branch reads, we
1722 && ((prev_prev_insn
.insn_mo
->pinfo
& INSN_LOAD_COPROC_DELAY
)
1724 && (prev_prev_insn
.insn_mo
->pinfo
1725 & INSN_LOAD_MEMORY_DELAY
)))
1726 && insn_uses_reg (ip
,
1727 ((prev_prev_insn
.insn_opcode
>> OP_SH_RT
)
1730 /* If one instruction sets a condition code and the
1731 other one uses a condition code, we can not swap. */
1732 || ((pinfo
& INSN_READ_COND_CODE
)
1733 && (prev_pinfo
& INSN_WRITE_COND_CODE
))
1734 || ((pinfo
& INSN_WRITE_COND_CODE
)
1735 && (prev_pinfo
& INSN_READ_COND_CODE
))
1736 /* If the previous instruction uses the PC, we can not
1739 && (prev_pinfo
& MIPS16_INSN_READ_PC
))
1740 /* If the previous instruction was extended, we can not
1742 || (mips16
&& prev_insn_extended
)
1743 /* If the previous instruction had a fixup in mips16
1744 mode, we can not swap. This normally means that the
1745 previous instruction was a 4 byte branch anyhow. */
1746 || (mips16
&& prev_insn_fixp
))
1748 /* We could do even better for unconditional branches to
1749 portions of this object file; we could pick up the
1750 instruction at the destination, put it in the delay
1751 slot, and bump the destination address. */
1753 /* Update the previous insn information. */
1754 prev_prev_insn
= *ip
;
1755 prev_insn
.insn_mo
= &dummy_opcode
;
1759 /* It looks like we can actually do the swap. */
1765 prev_f
= prev_insn_frag
->fr_literal
+ prev_insn_where
;
1766 memcpy (temp
, prev_f
, 4);
1767 memcpy (prev_f
, f
, 4);
1768 memcpy (f
, temp
, 4);
1771 prev_insn_fixp
->fx_frag
= frag_now
;
1772 prev_insn_fixp
->fx_where
= f
- frag_now
->fr_literal
;
1776 fixp
->fx_frag
= prev_insn_frag
;
1777 fixp
->fx_where
= prev_insn_where
;
1780 else if (reloc_type
> BFD_RELOC_UNUSED
)
1785 /* We are in mips16 mode, and we have just created a
1786 variant frag. We need to extract the old
1787 instruction from the end of the previous frag,
1788 and add it to a new frag. */
1789 prev_f
= prev_insn_frag
->fr_literal
+ prev_insn_where
;
1790 memcpy (temp
, prev_f
, 2);
1791 prev_insn_frag
->fr_fix
-= 2;
1792 if (prev_insn_frag
->fr_type
== rs_machine_dependent
)
1794 assert (prev_insn_where
== prev_insn_frag
->fr_fix
);
1795 memcpy (prev_f
, prev_f
+ 2, 2);
1797 memcpy (frag_more (2), temp
, 2);
1804 assert (prev_insn_fixp
== NULL
);
1805 prev_f
= prev_insn_frag
->fr_literal
+ prev_insn_where
;
1806 memcpy (temp
, prev_f
, 2);
1807 memcpy (prev_f
, f
, 2);
1808 if (reloc_type
!= BFD_RELOC_MIPS16_JMP
)
1809 memcpy (f
, temp
, 2);
1812 memcpy (f
, f
+ 2, 2);
1813 memcpy (f
+ 2, temp
, 2);
1817 fixp
->fx_frag
= prev_insn_frag
;
1818 fixp
->fx_where
= prev_insn_where
;
1822 /* Update the previous insn information; leave prev_insn
1824 prev_prev_insn
= *ip
;
1826 prev_insn_is_delay_slot
= 1;
1828 /* If that was an unconditional branch, forget the previous
1829 insn information. */
1830 if (pinfo
& INSN_UNCOND_BRANCH_DELAY
)
1832 prev_prev_insn
.insn_mo
= &dummy_opcode
;
1833 prev_insn
.insn_mo
= &dummy_opcode
;
1836 prev_insn_fixp
= NULL
;
1837 prev_insn_reloc_type
= BFD_RELOC_UNUSED
;
1838 prev_insn_extended
= 0;
1840 else if (pinfo
& INSN_COND_BRANCH_LIKELY
)
1842 /* We don't yet optimize a branch likely. What we should do
1843 is look at the target, copy the instruction found there
1844 into the delay slot, and increment the branch to jump to
1845 the next instruction. */
1847 /* Update the previous insn information. */
1848 prev_prev_insn
= *ip
;
1849 prev_insn
.insn_mo
= &dummy_opcode
;
1850 prev_insn_fixp
= NULL
;
1851 prev_insn_reloc_type
= BFD_RELOC_UNUSED
;
1852 prev_insn_extended
= 0;
1856 /* Update the previous insn information. */
1858 prev_prev_insn
.insn_mo
= &dummy_opcode
;
1860 prev_prev_insn
= prev_insn
;
1863 /* Any time we see a branch, we always fill the delay slot
1864 immediately; since this insn is not a branch, we know it
1865 is not in a delay slot. */
1866 prev_insn_is_delay_slot
= 0;
1868 prev_insn_fixp
= fixp
;
1869 prev_insn_reloc_type
= reloc_type
;
1871 prev_insn_extended
= (ip
->use_extend
1872 || reloc_type
> BFD_RELOC_UNUSED
);
1875 prev_prev_insn_unreordered
= prev_insn_unreordered
;
1876 prev_insn_unreordered
= 0;
1877 prev_insn_frag
= frag_now
;
1878 prev_insn_where
= f
- frag_now
->fr_literal
;
1879 prev_insn_valid
= 1;
1883 /* We need to record a bit of uninformation even when we are not
1884 reordering, in order to determine the base address for mips16
1885 PC relative relocs. */
1887 prev_insn_reloc_type
= reloc_type
;
1890 /* We just output an insn, so the next one doesn't have a label. */
1894 /* This function forgets that there was any previous instruction or
1898 mips_no_prev_insn ()
1900 prev_insn
.insn_mo
= &dummy_opcode
;
1901 prev_prev_insn
.insn_mo
= &dummy_opcode
;
1902 prev_insn_valid
= 0;
1903 prev_insn_is_delay_slot
= 0;
1904 prev_insn_unreordered
= 0;
1905 prev_insn_extended
= 0;
1906 prev_insn_reloc_type
= BFD_RELOC_UNUSED
;
1907 prev_prev_insn_unreordered
= 0;
1911 /* This function must be called whenever we turn on noreorder or emit
1912 something other than instructions. It inserts any NOPS which might
1913 be needed by the previous instruction, and clears the information
1914 kept for the previous instructions. */
1919 if (! mips_noreorder
)
1926 && (! cop_interlocks
1927 && (prev_insn
.insn_mo
->pinfo
1928 & (INSN_LOAD_COPROC_DELAY
1929 | INSN_COPROC_MOVE_DELAY
1930 | INSN_WRITE_COND_CODE
))))
1932 && (prev_insn
.insn_mo
->pinfo
1937 && (prev_insn
.insn_mo
->pinfo
1938 & (INSN_LOAD_MEMORY_DELAY
1939 | INSN_COPROC_MEMORY_DELAY
))))
1944 && (! cop_interlocks
1945 && prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
))
1947 && ((prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
1948 || (prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
))))
1953 && (! cop_interlocks
1954 && prev_prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
))
1956 && ((prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
1957 || (prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
))))
1962 if (insn_label
!= NULL
)
1964 assert (S_GET_SEGMENT (insn_label
) == now_seg
);
1965 insn_label
->sy_frag
= frag_now
;
1966 S_SET_VALUE (insn_label
, (valueT
) frag_now_fix ());
1971 mips_no_prev_insn ();
1974 /* Build an instruction created by a macro expansion. This is passed
1975 a pointer to the count of instructions created so far, an
1976 expression, the name of the instruction to build, an operand format
1977 string, and corresponding arguments. */
1981 macro_build (char *place
,
1989 macro_build (place
, counter
, ep
, name
, fmt
, va_alist
)
1998 struct mips_cl_insn insn
;
1999 bfd_reloc_code_real_type r
;
2003 va_start (args
, fmt
);
2009 * If the macro is about to expand into a second instruction,
2010 * print a warning if needed. We need to pass ip as a parameter
2011 * to generate a better warning message here...
2013 if (mips_warn_about_macros
&& place
== NULL
&& *counter
== 1)
2014 as_warn ("Macro instruction expanded into multiple instructions");
2017 *counter
+= 1; /* bump instruction counter */
2021 mips16_macro_build (place
, counter
, ep
, name
, fmt
, args
);
2026 r
= BFD_RELOC_UNUSED
;
2027 insn
.insn_mo
= (struct mips_opcode
*) hash_find (op_hash
, name
);
2028 assert (insn
.insn_mo
);
2029 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
2031 while (strcmp (fmt
, insn
.insn_mo
->args
) != 0
2032 || insn
.insn_mo
->pinfo
== INSN_MACRO
2033 || ((insn
.insn_mo
->pinfo
& INSN_ISA
) == INSN_ISA2
2035 || ((insn
.insn_mo
->pinfo
& INSN_ISA
) == INSN_ISA3
2037 || ((insn
.insn_mo
->pinfo
& INSN_ISA
) == INSN_ISA4
2039 || ((insn
.insn_mo
->pinfo
& INSN_ISA
) == INSN_4650
2041 || ((insn
.insn_mo
->pinfo
& INSN_ISA
) == INSN_4010
2043 || ((insn
.insn_mo
->pinfo
& INSN_ISA
) == INSN_4100
2047 assert (insn
.insn_mo
->name
);
2048 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
2050 insn
.insn_opcode
= insn
.insn_mo
->match
;
2066 insn
.insn_opcode
|= va_arg (args
, int) << 16;
2072 insn
.insn_opcode
|= va_arg (args
, int) << 16;
2077 insn
.insn_opcode
|= va_arg (args
, int) << 11;
2082 insn
.insn_opcode
|= va_arg (args
, int) << 11;
2089 insn
.insn_opcode
|= va_arg (args
, int) << 6;
2093 insn
.insn_opcode
|= va_arg (args
, int) << 6;
2097 insn
.insn_opcode
|= va_arg (args
, int) << 6;
2104 insn
.insn_opcode
|= va_arg (args
, int) << 21;
2110 r
= (bfd_reloc_code_real_type
) va_arg (args
, int);
2111 assert (r
== BFD_RELOC_MIPS_GPREL
2112 || r
== BFD_RELOC_MIPS_LITERAL
2113 || r
== BFD_RELOC_LO16
2114 || r
== BFD_RELOC_MIPS_GOT16
2115 || r
== BFD_RELOC_MIPS_CALL16
2116 || r
== BFD_RELOC_MIPS_GOT_LO16
2117 || r
== BFD_RELOC_MIPS_CALL_LO16
2118 || (ep
->X_op
== O_subtract
2119 && now_seg
== text_section
2120 && r
== BFD_RELOC_PCREL_LO16
));
2124 r
= (bfd_reloc_code_real_type
) va_arg (args
, int);
2126 && (ep
->X_op
== O_constant
2127 || (ep
->X_op
== O_symbol
2128 && (r
== BFD_RELOC_HI16_S
2129 || r
== BFD_RELOC_HI16
2130 || r
== BFD_RELOC_MIPS_GOT_HI16
2131 || r
== BFD_RELOC_MIPS_CALL_HI16
))
2132 || (ep
->X_op
== O_subtract
2133 && now_seg
== text_section
2134 && r
== BFD_RELOC_PCREL_HI16_S
)));
2135 if (ep
->X_op
== O_constant
)
2137 insn
.insn_opcode
|= (ep
->X_add_number
>> 16) & 0xffff;
2139 r
= BFD_RELOC_UNUSED
;
2144 assert (ep
!= NULL
);
2146 * This allows macro() to pass an immediate expression for
2147 * creating short branches without creating a symbol.
2148 * Note that the expression still might come from the assembly
2149 * input, in which case the value is not checked for range nor
2150 * is a relocation entry generated (yuck).
2152 if (ep
->X_op
== O_constant
)
2154 insn
.insn_opcode
|= (ep
->X_add_number
>> 2) & 0xffff;
2158 r
= BFD_RELOC_16_PCREL_S2
;
2162 assert (ep
!= NULL
);
2163 r
= BFD_RELOC_MIPS_JMP
;
2172 assert (r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
2174 append_insn (place
, &insn
, ep
, r
, false);
2178 mips16_macro_build (place
, counter
, ep
, name
, fmt
, args
)
2186 struct mips_cl_insn insn
;
2187 bfd_reloc_code_real_type r
;
2189 r
= BFD_RELOC_UNUSED
;
2190 insn
.insn_mo
= (struct mips_opcode
*) hash_find (mips16_op_hash
, name
);
2191 assert (insn
.insn_mo
);
2192 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
2194 while (strcmp (fmt
, insn
.insn_mo
->args
) != 0
2195 || insn
.insn_mo
->pinfo
== INSN_MACRO
)
2198 assert (insn
.insn_mo
->name
);
2199 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
2202 insn
.insn_opcode
= insn
.insn_mo
->match
;
2203 insn
.use_extend
= false;
2222 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_RY
;
2227 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_RX
;
2231 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_RZ
;
2235 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_MOVE32Z
;
2245 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_REGR32
;
2252 regno
= va_arg (args
, int);
2253 regno
= ((regno
& 7) << 2) | ((regno
& 0x18) >> 3);
2254 insn
.insn_opcode
|= regno
<< MIPS16OP_SH_REG32R
;
2275 assert (ep
!= NULL
);
2277 if (ep
->X_op
!= O_constant
)
2278 r
= BFD_RELOC_UNUSED
+ c
;
2281 mips16_immed ((char *) NULL
, 0, c
, ep
->X_add_number
, false,
2282 false, false, &insn
.insn_opcode
,
2283 &insn
.use_extend
, &insn
.extend
);
2285 r
= BFD_RELOC_UNUSED
;
2291 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_IMM6
;
2298 assert (r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
2300 append_insn (place
, &insn
, ep
, r
, false);
2304 * Generate a "lui" instruction.
2307 macro_build_lui (place
, counter
, ep
, regnum
)
2313 expressionS high_expr
;
2314 struct mips_cl_insn insn
;
2315 bfd_reloc_code_real_type r
;
2316 CONST
char *name
= "lui";
2317 CONST
char *fmt
= "t,u";
2325 high_expr
.X_op
= O_constant
;
2326 high_expr
.X_add_number
= ep
->X_add_number
;
2329 if (high_expr
.X_op
== O_constant
)
2331 /* we can compute the instruction now without a relocation entry */
2332 if (high_expr
.X_add_number
& 0x8000)
2333 high_expr
.X_add_number
+= 0x10000;
2334 high_expr
.X_add_number
=
2335 ((unsigned long) high_expr
.X_add_number
>> 16) & 0xffff;
2336 r
= BFD_RELOC_UNUSED
;
2340 assert (ep
->X_op
== O_symbol
);
2341 /* _gp_disp is a special case, used from s_cpload. */
2342 assert (mips_pic
== NO_PIC
2343 || strcmp (S_GET_NAME (ep
->X_add_symbol
), "_gp_disp") == 0);
2344 r
= BFD_RELOC_HI16_S
;
2348 * If the macro is about to expand into a second instruction,
2349 * print a warning if needed. We need to pass ip as a parameter
2350 * to generate a better warning message here...
2352 if (mips_warn_about_macros
&& place
== NULL
&& *counter
== 1)
2353 as_warn ("Macro instruction expanded into multiple instructions");
2356 *counter
+= 1; /* bump instruction counter */
2358 insn
.insn_mo
= (struct mips_opcode
*) hash_find (op_hash
, name
);
2359 assert (insn
.insn_mo
);
2360 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
2361 assert (strcmp (fmt
, insn
.insn_mo
->args
) == 0);
2363 insn
.insn_opcode
= insn
.insn_mo
->match
| (regnum
<< OP_SH_RT
);
2364 if (r
== BFD_RELOC_UNUSED
)
2366 insn
.insn_opcode
|= high_expr
.X_add_number
;
2367 append_insn (place
, &insn
, NULL
, r
, false);
2370 append_insn (place
, &insn
, &high_expr
, r
, false);
2374 * Generates code to set the $at register to true (one)
2375 * if reg is less than the immediate expression.
2378 set_at (counter
, reg
, unsignedp
)
2383 if (imm_expr
.X_add_number
>= -0x8000 && imm_expr
.X_add_number
< 0x8000)
2384 macro_build ((char *) NULL
, counter
, &imm_expr
,
2385 unsignedp
? "sltiu" : "slti",
2386 "t,r,j", AT
, reg
, (int) BFD_RELOC_LO16
);
2389 load_register (counter
, AT
, &imm_expr
, 0);
2390 macro_build ((char *) NULL
, counter
, NULL
,
2391 unsignedp
? "sltu" : "slt",
2392 "d,v,t", AT
, reg
, AT
);
2396 /* Warn if an expression is not a constant. */
2399 check_absolute_expr (ip
, ex
)
2400 struct mips_cl_insn
*ip
;
2403 if (ex
->X_op
!= O_constant
)
2404 as_warn ("Instruction %s requires absolute expression", ip
->insn_mo
->name
);
2407 /* Count the leading zeroes by performing a binary chop. This is a
2408 bulky bit of source, but performance is a LOT better for the
2409 majority of values than a simple loop to count the bits:
2410 for (lcnt = 0; (lcnt < 32); lcnt++)
2411 if ((v) & (1 << (31 - lcnt)))
2413 However it is not code size friendly, and the gain will drop a bit
2414 on certain cached systems.
2416 #define COUNT_TOP_ZEROES(v) \
2417 (((v) & ~0xffff) == 0 \
2418 ? ((v) & ~0xff) == 0 \
2419 ? ((v) & ~0xf) == 0 \
2420 ? ((v) & ~0x3) == 0 \
2421 ? ((v) & ~0x1) == 0 \
2426 : ((v) & ~0x7) == 0 \
2429 : ((v) & ~0x3f) == 0 \
2430 ? ((v) & ~0x1f) == 0 \
2433 : ((v) & ~0x7f) == 0 \
2436 : ((v) & ~0xfff) == 0 \
2437 ? ((v) & ~0x3ff) == 0 \
2438 ? ((v) & ~0x1ff) == 0 \
2441 : ((v) & ~0x7ff) == 0 \
2444 : ((v) & ~0x3fff) == 0 \
2445 ? ((v) & ~0x1fff) == 0 \
2448 : ((v) & ~0x7fff) == 0 \
2451 : ((v) & ~0xffffff) == 0 \
2452 ? ((v) & ~0xfffff) == 0 \
2453 ? ((v) & ~0x3ffff) == 0 \
2454 ? ((v) & ~0x1ffff) == 0 \
2457 : ((v) & ~0x7ffff) == 0 \
2460 : ((v) & ~0x3fffff) == 0 \
2461 ? ((v) & ~0x1fffff) == 0 \
2464 : ((v) & ~0x7fffff) == 0 \
2467 : ((v) & ~0xfffffff) == 0 \
2468 ? ((v) & ~0x3ffffff) == 0 \
2469 ? ((v) & ~0x1ffffff) == 0 \
2472 : ((v) & ~0x7ffffff) == 0 \
2475 : ((v) & ~0x3fffffff) == 0 \
2476 ? ((v) & ~0x1fffffff) == 0 \
2479 : ((v) & ~0x7fffffff) == 0 \
2484 * This routine generates the least number of instructions neccessary to load
2485 * an absolute expression value into a register.
2488 load_register (counter
, reg
, ep
, dbl
)
2495 expressionS hi32
, lo32
, tmp
;
2497 if (ep
->X_op
!= O_big
)
2499 assert (ep
->X_op
== O_constant
);
2500 if (ep
->X_add_number
< 0x8000
2501 && (ep
->X_add_number
>= 0
2502 || (ep
->X_add_number
>= -0x8000
2505 || sizeof (ep
->X_add_number
) > 4))))
2507 /* We can handle 16 bit signed values with an addiu to
2508 $zero. No need to ever use daddiu here, since $zero and
2509 the result are always correct in 32 bit mode. */
2510 macro_build ((char *) NULL
, counter
, ep
, "addiu", "t,r,j", reg
, 0,
2511 (int) BFD_RELOC_LO16
);
2514 else if (ep
->X_add_number
>= 0 && ep
->X_add_number
< 0x10000)
2516 /* We can handle 16 bit unsigned values with an ori to
2518 macro_build ((char *) NULL
, counter
, ep
, "ori", "t,r,i", reg
, 0,
2519 (int) BFD_RELOC_LO16
);
2522 else if ((((ep
->X_add_number
&~ (offsetT
) 0x7fffffff) == 0
2523 || ((ep
->X_add_number
&~ (offsetT
) 0x7fffffff)
2524 == ~ (offsetT
) 0x7fffffff))
2527 || sizeof (ep
->X_add_number
) > 4
2528 || (ep
->X_add_number
& 0x80000000) == 0))
2529 || ((mips_isa
< 3 || !dbl
)
2530 && (ep
->X_add_number
&~ (offsetT
) 0xffffffff) == 0))
2532 /* 32 bit values require an lui. */
2533 macro_build ((char *) NULL
, counter
, ep
, "lui", "t,u", reg
,
2534 (int) BFD_RELOC_HI16
);
2535 if ((ep
->X_add_number
& 0xffff) != 0)
2536 macro_build ((char *) NULL
, counter
, ep
, "ori", "t,r,i", reg
, reg
,
2537 (int) BFD_RELOC_LO16
);
2542 /* The value is larger than 32 bits. */
2546 as_bad ("Number larger than 32 bits");
2547 macro_build ((char *) NULL
, counter
, ep
, "addiu", "t,r,j", reg
, 0,
2548 (int) BFD_RELOC_LO16
);
2552 if (ep
->X_op
!= O_big
)
2556 hi32
.X_add_number
>>= shift
;
2557 hi32
.X_add_number
&= 0xffffffff;
2558 if ((hi32
.X_add_number
& 0x80000000) != 0)
2559 hi32
.X_add_number
|= ~ (offsetT
) 0xffffffff;
2561 lo32
.X_add_number
&= 0xffffffff;
2565 assert (ep
->X_add_number
> 2);
2566 if (ep
->X_add_number
== 3)
2567 generic_bignum
[3] = 0;
2568 else if (ep
->X_add_number
> 4)
2569 as_bad ("Number larger than 64 bits");
2570 lo32
.X_op
= O_constant
;
2571 lo32
.X_add_number
= generic_bignum
[0] + (generic_bignum
[1] << 16);
2572 hi32
.X_op
= O_constant
;
2573 hi32
.X_add_number
= generic_bignum
[2] + (generic_bignum
[3] << 16);
2576 if (hi32
.X_add_number
== 0)
2580 if (hi32
.X_add_number
== 0xffffffff)
2582 if ((lo32
.X_add_number
& 0xffff8000) == 0xffff8000)
2584 macro_build ((char *) NULL
, counter
, &lo32
, "addiu", "t,r,j", reg
, 0,
2585 (int) BFD_RELOC_LO16
);
2588 if (lo32
.X_add_number
& 0x80000000)
2590 macro_build ((char *) NULL
, counter
, &lo32
, "lui", "t,u", reg
,
2591 (int) BFD_RELOC_HI16
);
2592 macro_build ((char *) NULL
, counter
, &lo32
, "ori", "t,r,i", reg
, reg
,
2593 (int) BFD_RELOC_LO16
);
2598 /* Check for 16bit shifted constant: */
2600 tmp
.X_add_number
= hi32
.X_add_number
<< shift
| lo32
.X_add_number
;
2601 /* We know that hi32 is non-zero, so start the mask on the first
2602 bit of the hi32 value: */
2606 if ((tmp
.X_add_number
& ~((offsetT
)0xffff << shift
)) == 0)
2608 tmp
.X_op
= O_constant
;
2609 tmp
.X_add_number
>>= shift
;
2610 macro_build ((char *) NULL
, counter
, &tmp
, "ori", "t,r,i", reg
, 0,
2611 (int) BFD_RELOC_LO16
);
2612 macro_build ((char *) NULL
, counter
, NULL
,
2613 (shift
>= 32) ? "dsll32" : "dsll",
2614 "d,w,<", reg
, reg
, (shift
>= 32) ? shift
- 32 : shift
);
2618 } while (shift
<= (64 - 16));
2622 tmp
.X_add_number
= hi32
.X_add_number
<< shift
| lo32
.X_add_number
;
2623 while ((tmp
.X_add_number
& 1) == 0)
2625 tmp
.X_add_number
>>= 1;
2628 if (((tmp
.X_add_number
+ 1) & tmp
.X_add_number
) == 0) /* (power-of-2 - 1) */
2630 shift
= COUNT_TOP_ZEROES((unsigned int)hi32
.X_add_number
);
2633 tmp
.X_op
= O_constant
;
2634 tmp
.X_add_number
= (offsetT
)-1;
2635 macro_build ((char *) NULL
, counter
, &tmp
, "addiu", "t,r,j", reg
, 0,
2636 (int) BFD_RELOC_LO16
); /* set all ones */
2640 macro_build ((char *) NULL
, counter
, NULL
,
2641 (freg
>= 32) ? "dsll32" : "dsll",
2643 (freg
>= 32) ? freg
- 32 : freg
);
2645 macro_build ((char *) NULL
, counter
, NULL
, (shift
>= 32) ? "dsrl32" : "dsrl",
2646 "d,w,<", reg
, reg
, (shift
>= 32) ? shift
- 32 : shift
);
2650 load_register (counter
, reg
, &hi32
, 0);
2653 if ((lo32
.X_add_number
& 0xffff0000) == 0)
2657 macro_build ((char *) NULL
, counter
, NULL
, "dsll32", "d,w,<", reg
,
2666 if ((freg
== 0) && (lo32
.X_add_number
== 0xffffffff))
2668 macro_build ((char *) NULL
, counter
, &lo32
, "lui", "t,u", reg
,
2669 (int) BFD_RELOC_HI16
);
2670 macro_build ((char *) NULL
, counter
, NULL
, "dsrl32", "d,w,<", reg
,
2677 macro_build ((char *) NULL
, counter
, NULL
, "dsll", "d,w,<", reg
,
2682 mid16
.X_add_number
>>= 16;
2683 macro_build ((char *) NULL
, counter
, &mid16
, "ori", "t,r,i", reg
,
2684 freg
, (int) BFD_RELOC_LO16
);
2685 macro_build ((char *) NULL
, counter
, NULL
, "dsll", "d,w,<", reg
,
2689 if ((lo32
.X_add_number
& 0xffff) != 0)
2690 macro_build ((char *) NULL
, counter
, &lo32
, "ori", "t,r,i", reg
, freg
,
2691 (int) BFD_RELOC_LO16
);
2694 /* Load an address into a register. */
2697 load_address (counter
, reg
, ep
)
2704 if (ep
->X_op
!= O_constant
2705 && ep
->X_op
!= O_symbol
)
2707 as_bad ("expression too complex");
2708 ep
->X_op
= O_constant
;
2711 if (ep
->X_op
== O_constant
)
2713 load_register (counter
, reg
, ep
, 0);
2717 if (mips_pic
== NO_PIC
)
2719 /* If this is a reference to a GP relative symbol, we want
2720 addiu $reg,$gp,<sym> (BFD_RELOC_MIPS_GPREL)
2722 lui $reg,<sym> (BFD_RELOC_HI16_S)
2723 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
2724 If we have an addend, we always use the latter form. */
2725 if ((valueT
) ep
->X_add_number
>= MAX_GPREL_OFFSET
2726 || nopic_need_relax (ep
->X_add_symbol
))
2731 macro_build ((char *) NULL
, counter
, ep
,
2732 mips_isa
< 3 ? "addiu" : "daddiu",
2733 "t,r,j", reg
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
2734 p
= frag_var (rs_machine_dependent
, 8, 0,
2735 RELAX_ENCODE (4, 8, 0, 4, 0, mips_warn_about_macros
),
2736 ep
->X_add_symbol
, (long) 0, (char *) NULL
);
2738 macro_build_lui (p
, counter
, ep
, reg
);
2741 macro_build (p
, counter
, ep
,
2742 mips_isa
< 3 ? "addiu" : "daddiu",
2743 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
2745 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
2749 /* If this is a reference to an external symbol, we want
2750 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
2752 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
2754 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
2755 If there is a constant, it must be added in after. */
2756 ex
.X_add_number
= ep
->X_add_number
;
2757 ep
->X_add_number
= 0;
2759 macro_build ((char *) NULL
, counter
, ep
,
2760 mips_isa
< 3 ? "lw" : "ld",
2761 "t,o(b)", reg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
2762 macro_build ((char *) NULL
, counter
, (expressionS
*) NULL
, "nop", "");
2763 p
= frag_var (rs_machine_dependent
, 4, 0,
2764 RELAX_ENCODE (0, 4, -8, 0, 0, mips_warn_about_macros
),
2765 ep
->X_add_symbol
, (long) 0, (char *) NULL
);
2766 macro_build (p
, counter
, ep
,
2767 mips_isa
< 3 ? "addiu" : "daddiu",
2768 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
2769 if (ex
.X_add_number
!= 0)
2771 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
2772 as_bad ("PIC code offset overflow (max 16 signed bits)");
2773 ex
.X_op
= O_constant
;
2774 macro_build ((char *) NULL
, counter
, &ex
,
2775 mips_isa
< 3 ? "addiu" : "daddiu",
2776 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
2779 else if (mips_pic
== SVR4_PIC
)
2784 /* This is the large GOT case. If this is a reference to an
2785 external symbol, we want
2786 lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
2788 lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16)
2789 Otherwise, for a reference to a local symbol, we want
2790 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
2792 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
2793 If there is a constant, it must be added in after. */
2794 ex
.X_add_number
= ep
->X_add_number
;
2795 ep
->X_add_number
= 0;
2796 if (reg_needs_delay (GP
))
2801 macro_build ((char *) NULL
, counter
, ep
, "lui", "t,u", reg
,
2802 (int) BFD_RELOC_MIPS_GOT_HI16
);
2803 macro_build ((char *) NULL
, counter
, (expressionS
*) NULL
,
2804 mips_isa
< 3 ? "addu" : "daddu",
2805 "d,v,t", reg
, reg
, GP
);
2806 macro_build ((char *) NULL
, counter
, ep
,
2807 mips_isa
< 3 ? "lw" : "ld",
2808 "t,o(b)", reg
, (int) BFD_RELOC_MIPS_GOT_LO16
, reg
);
2809 p
= frag_var (rs_machine_dependent
, 12 + off
, 0,
2810 RELAX_ENCODE (12, 12 + off
, off
, 8 + off
, 0,
2811 mips_warn_about_macros
),
2812 ep
->X_add_symbol
, (long) 0, (char *) NULL
);
2815 /* We need a nop before loading from $gp. This special
2816 check is required because the lui which starts the main
2817 instruction stream does not refer to $gp, and so will not
2818 insert the nop which may be required. */
2819 macro_build (p
, counter
, (expressionS
*) NULL
, "nop", "");
2822 macro_build (p
, counter
, ep
,
2823 mips_isa
< 3 ? "lw" : "ld",
2824 "t,o(b)", reg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
2826 macro_build (p
, counter
, (expressionS
*) NULL
, "nop", "");
2828 macro_build (p
, counter
, ep
,
2829 mips_isa
< 3 ? "addiu" : "daddiu",
2830 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
2831 if (ex
.X_add_number
!= 0)
2833 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
2834 as_bad ("PIC code offset overflow (max 16 signed bits)");
2835 ex
.X_op
= O_constant
;
2836 macro_build ((char *) NULL
, counter
, &ex
,
2837 mips_isa
< 3 ? "addiu" : "daddiu",
2838 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
2841 else if (mips_pic
== EMBEDDED_PIC
)
2844 addiu $reg,$gp,<sym> (BFD_RELOC_MIPS_GPREL)
2846 macro_build ((char *) NULL
, counter
, ep
,
2847 mips_isa
< 3 ? "addiu" : "daddiu",
2848 "t,r,j", reg
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
2856 * This routine implements the seemingly endless macro or synthesized
2857 * instructions and addressing modes in the mips assembly language. Many
2858 * of these macros are simple and are similar to each other. These could
2859 * probably be handled by some kind of table or grammer aproach instead of
2860 * this verbose method. Others are not simple macros but are more like
2861 * optimizing code generation.
2862 * One interesting optimization is when several store macros appear
2863 * consecutivly that would load AT with the upper half of the same address.
2864 * The ensuing load upper instructions are ommited. This implies some kind
2865 * of global optimization. We currently only optimize within a single macro.
2866 * For many of the load and store macros if the address is specified as a
2867 * constant expression in the first 64k of memory (ie ld $2,0x4000c) we
2868 * first load register 'at' with zero and use it as the base register. The
2869 * mips assembler simply uses register $zero. Just one tiny optimization
2874 struct mips_cl_insn
*ip
;
2876 register int treg
, sreg
, dreg
, breg
;
2891 bfd_reloc_code_real_type r
;
2893 int hold_mips_optimize
;
2897 treg
= (ip
->insn_opcode
>> 16) & 0x1f;
2898 dreg
= (ip
->insn_opcode
>> 11) & 0x1f;
2899 sreg
= breg
= (ip
->insn_opcode
>> 21) & 0x1f;
2900 mask
= ip
->insn_mo
->mask
;
2902 expr1
.X_op
= O_constant
;
2903 expr1
.X_op_symbol
= NULL
;
2904 expr1
.X_add_symbol
= NULL
;
2905 expr1
.X_add_number
= 1;
2917 mips_emit_delays ();
2919 mips_any_noreorder
= 1;
2921 expr1
.X_add_number
= 8;
2922 macro_build ((char *) NULL
, &icnt
, &expr1
, "bgez", "s,p", sreg
);
2924 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
2926 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
, sreg
, 0);
2927 macro_build ((char *) NULL
, &icnt
, NULL
,
2928 dbl
? "dsub" : "sub",
2929 "d,v,t", dreg
, 0, sreg
);
2952 if (imm_expr
.X_add_number
>= -0x8000 && imm_expr
.X_add_number
< 0x8000)
2954 macro_build ((char *) NULL
, &icnt
, &imm_expr
, s
, "t,r,j", treg
, sreg
,
2955 (int) BFD_RELOC_LO16
);
2958 load_register (&icnt
, AT
, &imm_expr
, dbl
);
2959 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "d,v,t", treg
, sreg
, AT
);
2978 if (imm_expr
.X_add_number
>= 0 && imm_expr
.X_add_number
< 0x10000)
2980 if (mask
!= M_NOR_I
)
2981 macro_build ((char *) NULL
, &icnt
, &imm_expr
, s
, "t,r,i", treg
,
2982 sreg
, (int) BFD_RELOC_LO16
);
2985 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "ori", "t,r,i",
2986 treg
, sreg
, (int) BFD_RELOC_LO16
);
2987 macro_build ((char *) NULL
, &icnt
, NULL
, "nor", "d,v,t",
2993 load_register (&icnt
, AT
, &imm_expr
, 0);
2994 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "d,v,t", treg
, sreg
, AT
);
3011 if (imm_expr
.X_add_number
== 0)
3013 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "s,t,p", sreg
,
3017 load_register (&icnt
, AT
, &imm_expr
, 0);
3018 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "s,t,p", sreg
, AT
);
3026 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3027 likely
? "bgezl" : "bgez",
3033 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3034 likely
? "blezl" : "blez",
3038 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", AT
, sreg
, treg
);
3039 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3040 likely
? "beql" : "beq",
3047 /* check for > max integer */
3048 maxnum
= 0x7fffffff;
3056 if (imm_expr
.X_add_number
>= maxnum
3057 && (mips_isa
< 3 || sizeof (maxnum
) > 4))
3060 /* result is always false */
3063 as_warn ("Branch %s is always false (nop)", ip
->insn_mo
->name
);
3064 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
3068 as_warn ("Branch likely %s is always false", ip
->insn_mo
->name
);
3069 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "bnel",
3074 imm_expr
.X_add_number
++;
3078 if (mask
== M_BGEL_I
)
3080 if (imm_expr
.X_add_number
== 0)
3082 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3083 likely
? "bgezl" : "bgez",
3087 if (imm_expr
.X_add_number
== 1)
3089 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3090 likely
? "bgtzl" : "bgtz",
3094 maxnum
= 0x7fffffff;
3102 maxnum
= - maxnum
- 1;
3103 if (imm_expr
.X_add_number
<= maxnum
3104 && (mips_isa
< 3 || sizeof (maxnum
) > 4))
3107 /* result is always true */
3108 as_warn ("Branch %s is always true", ip
->insn_mo
->name
);
3109 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "b", "p");
3112 set_at (&icnt
, sreg
, 0);
3113 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3114 likely
? "beql" : "beq",
3125 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3126 likely
? "beql" : "beq",
3130 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", AT
, sreg
,
3132 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3133 likely
? "beql" : "beq",
3140 if (sreg
== 0 || imm_expr
.X_add_number
== -1)
3142 imm_expr
.X_add_number
++;
3146 if (mask
== M_BGEUL_I
)
3148 if (imm_expr
.X_add_number
== 0)
3150 if (imm_expr
.X_add_number
== 1)
3152 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3153 likely
? "bnel" : "bne",
3157 set_at (&icnt
, sreg
, 1);
3158 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3159 likely
? "beql" : "beq",
3168 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3169 likely
? "bgtzl" : "bgtz",
3175 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3176 likely
? "bltzl" : "bltz",
3180 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", AT
, treg
, sreg
);
3181 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3182 likely
? "bnel" : "bne",
3191 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3192 likely
? "bnel" : "bne",
3198 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", AT
, treg
,
3200 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3201 likely
? "bnel" : "bne",
3210 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3211 likely
? "blezl" : "blez",
3217 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3218 likely
? "bgezl" : "bgez",
3222 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", AT
, treg
, sreg
);
3223 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3224 likely
? "beql" : "beq",
3231 maxnum
= 0x7fffffff;
3239 if (imm_expr
.X_add_number
>= maxnum
3240 && (mips_isa
< 3 || sizeof (maxnum
) > 4))
3242 imm_expr
.X_add_number
++;
3246 if (mask
== M_BLTL_I
)
3248 if (imm_expr
.X_add_number
== 0)
3250 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3251 likely
? "bltzl" : "bltz",
3255 if (imm_expr
.X_add_number
== 1)
3257 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3258 likely
? "blezl" : "blez",
3262 set_at (&icnt
, sreg
, 0);
3263 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3264 likely
? "bnel" : "bne",
3273 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3274 likely
? "beql" : "beq",
3280 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", AT
, treg
,
3282 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3283 likely
? "beql" : "beq",
3290 if (sreg
== 0 || imm_expr
.X_add_number
== -1)
3292 imm_expr
.X_add_number
++;
3296 if (mask
== M_BLTUL_I
)
3298 if (imm_expr
.X_add_number
== 0)
3300 if (imm_expr
.X_add_number
== 1)
3302 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3303 likely
? "beql" : "beq",
3307 set_at (&icnt
, sreg
, 1);
3308 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3309 likely
? "bnel" : "bne",
3318 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3319 likely
? "bltzl" : "bltz",
3325 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3326 likely
? "bgtzl" : "bgtz",
3330 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", AT
, sreg
, treg
);
3331 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3332 likely
? "bnel" : "bne",
3343 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3344 likely
? "bnel" : "bne",
3348 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", AT
, sreg
,
3350 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3351 likely
? "bnel" : "bne",
3367 as_warn ("Divide by zero.");
3369 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", 0, 0);
3371 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 7);
3375 mips_emit_delays ();
3377 mips_any_noreorder
= 1;
3378 macro_build ((char *) NULL
, &icnt
, NULL
,
3379 dbl
? "ddiv" : "div",
3380 "z,s,t", sreg
, treg
);
3382 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", treg
, 0);
3385 expr1
.X_add_number
= 8;
3386 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", treg
, 0);
3387 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
3388 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 7);
3390 expr1
.X_add_number
= -1;
3391 macro_build ((char *) NULL
, &icnt
, &expr1
,
3392 dbl
? "daddiu" : "addiu",
3393 "t,r,j", AT
, 0, (int) BFD_RELOC_LO16
);
3394 expr1
.X_add_number
= mips_trap
? (dbl
? 12 : 8) : (dbl
? 20 : 16);
3395 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", treg
, AT
);
3398 expr1
.X_add_number
= 1;
3399 macro_build ((char *) NULL
, &icnt
, &expr1
, "daddiu", "t,r,j", AT
, 0,
3400 (int) BFD_RELOC_LO16
);
3401 macro_build ((char *) NULL
, &icnt
, NULL
, "dsll32", "d,w,<", AT
, AT
,
3406 expr1
.X_add_number
= 0x80000000;
3407 macro_build ((char *) NULL
, &icnt
, &expr1
, "lui", "t,u", AT
,
3408 (int) BFD_RELOC_HI16
);
3411 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", sreg
, AT
);
3414 expr1
.X_add_number
= 8;
3415 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", sreg
, AT
);
3416 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
3417 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 6);
3420 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d", dreg
);
3459 if (imm_expr
.X_add_number
== 0)
3461 as_warn ("Divide by zero.");
3463 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", 0, 0);
3465 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 7);
3468 if (imm_expr
.X_add_number
== 1)
3470 if (strcmp (s2
, "mflo") == 0)
3471 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
,
3474 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
, 0);
3477 if (imm_expr
.X_add_number
== -1
3478 && s
[strlen (s
) - 1] != 'u')
3480 if (strcmp (s2
, "mflo") == 0)
3483 macro_build ((char *) NULL
, &icnt
, NULL
, "dneg", "d,w", dreg
,
3486 macro_build ((char *) NULL
, &icnt
, NULL
, "neg", "d,w", dreg
,
3490 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
, 0);
3494 load_register (&icnt
, AT
, &imm_expr
, dbl
);
3495 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "z,s,t", sreg
, AT
);
3496 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "d", dreg
);
3515 mips_emit_delays ();
3517 mips_any_noreorder
= 1;
3518 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "z,s,t", sreg
, treg
);
3520 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", treg
, 0);
3523 expr1
.X_add_number
= 8;
3524 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", treg
, 0);
3525 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
3526 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 7);
3529 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "d", dreg
);
3535 /* Load the address of a symbol into a register. If breg is not
3536 zero, we then add a base register to it. */
3538 /* When generating embedded PIC code, we permit expressions of
3541 where bar is an address in the .text section. These are used
3542 when getting the addresses of functions. We don't permit
3543 X_add_number to be non-zero, because if the symbol is
3544 external the relaxing code needs to know that any addend is
3545 purely the offset to X_op_symbol. */
3546 if (mips_pic
== EMBEDDED_PIC
3547 && offset_expr
.X_op
== O_subtract
3548 && now_seg
== text_section
3549 && (offset_expr
.X_op_symbol
->sy_value
.X_op
== O_constant
3550 ? S_GET_SEGMENT (offset_expr
.X_op_symbol
) == text_section
3551 : (offset_expr
.X_op_symbol
->sy_value
.X_op
== O_symbol
3552 && (S_GET_SEGMENT (offset_expr
.X_op_symbol
3553 ->sy_value
.X_add_symbol
)
3556 && offset_expr
.X_add_number
== 0)
3558 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
3559 treg
, (int) BFD_RELOC_PCREL_HI16_S
);
3560 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3561 mips_isa
< 3 ? "addiu" : "daddiu",
3562 "t,r,j", treg
, treg
, (int) BFD_RELOC_PCREL_LO16
);
3566 if (offset_expr
.X_op
!= O_symbol
3567 && offset_expr
.X_op
!= O_constant
)
3569 as_bad ("expression too complex");
3570 offset_expr
.X_op
= O_constant
;
3584 if (offset_expr
.X_op
== O_constant
)
3585 load_register (&icnt
, tempreg
, &offset_expr
, dbl
);
3586 else if (mips_pic
== NO_PIC
)
3588 /* If this is a reference to an GP relative symbol, we want
3589 addiu $tempreg,$gp,<sym> (BFD_RELOC_MIPS_GPREL)
3591 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
3592 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
3593 If we have a constant, we need two instructions anyhow,
3594 so we may as well always use the latter form. */
3595 if ((valueT
) offset_expr
.X_add_number
>= MAX_GPREL_OFFSET
3596 || nopic_need_relax (offset_expr
.X_add_symbol
))
3601 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3602 mips_isa
< 3 ? "addiu" : "daddiu",
3603 "t,r,j", tempreg
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
3604 p
= frag_var (rs_machine_dependent
, 8, 0,
3605 RELAX_ENCODE (4, 8, 0, 4, 0,
3606 mips_warn_about_macros
),
3607 offset_expr
.X_add_symbol
, (long) 0,
3610 macro_build_lui (p
, &icnt
, &offset_expr
, tempreg
);
3613 macro_build (p
, &icnt
, &offset_expr
,
3614 mips_isa
< 3 ? "addiu" : "daddiu",
3615 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
3617 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
3619 /* If this is a reference to an external symbol, and there
3620 is no constant, we want
3621 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3622 For a local symbol, we want
3623 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3625 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
3627 If we have a small constant, and this is a reference to
3628 an external symbol, we want
3629 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3631 addiu $tempreg,$tempreg,<constant>
3632 For a local symbol, we want the same instruction
3633 sequence, but we output a BFD_RELOC_LO16 reloc on the
3636 If we have a large constant, and this is a reference to
3637 an external symbol, we want
3638 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3639 lui $at,<hiconstant>
3640 addiu $at,$at,<loconstant>
3641 addu $tempreg,$tempreg,$at
3642 For a local symbol, we want the same instruction
3643 sequence, but we output a BFD_RELOC_LO16 reloc on the
3644 addiu instruction. */
3645 expr1
.X_add_number
= offset_expr
.X_add_number
;
3646 offset_expr
.X_add_number
= 0;
3648 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3650 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
3651 if (expr1
.X_add_number
== 0)
3659 /* We're going to put in an addu instruction using
3660 tempreg, so we may as well insert the nop right
3662 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3666 p
= frag_var (rs_machine_dependent
, 8 - off
, 0,
3667 RELAX_ENCODE (0, 8 - off
, -4 - off
, 4 - off
, 0,
3669 ? mips_warn_about_macros
3671 offset_expr
.X_add_symbol
, (long) 0,
3675 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
3678 macro_build (p
, &icnt
, &expr1
,
3679 mips_isa
< 3 ? "addiu" : "daddiu",
3680 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
3681 /* FIXME: If breg == 0, and the next instruction uses
3682 $tempreg, then if this variant case is used an extra
3683 nop will be generated. */
3685 else if (expr1
.X_add_number
>= -0x8000
3686 && expr1
.X_add_number
< 0x8000)
3688 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3690 macro_build ((char *) NULL
, &icnt
, &expr1
,
3691 mips_isa
< 3 ? "addiu" : "daddiu",
3692 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
3693 (void) frag_var (rs_machine_dependent
, 0, 0,
3694 RELAX_ENCODE (0, 0, -12, -4, 0, 0),
3695 offset_expr
.X_add_symbol
, (long) 0,
3702 /* If we are going to add in a base register, and the
3703 target register and the base register are the same,
3704 then we are using AT as a temporary register. Since
3705 we want to load the constant into AT, we add our
3706 current AT (from the global offset table) and the
3707 register into the register now, and pretend we were
3708 not using a base register. */
3713 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3715 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3716 mips_isa
< 3 ? "addu" : "daddu",
3717 "d,v,t", treg
, AT
, breg
);
3723 /* Set mips_optimize around the lui instruction to avoid
3724 inserting an unnecessary nop after the lw. */
3725 hold_mips_optimize
= mips_optimize
;
3727 macro_build_lui ((char *) NULL
, &icnt
, &expr1
, AT
);
3728 mips_optimize
= hold_mips_optimize
;
3730 macro_build ((char *) NULL
, &icnt
, &expr1
,
3731 mips_isa
< 3 ? "addiu" : "daddiu",
3732 "t,r,j", AT
, AT
, (int) BFD_RELOC_LO16
);
3733 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3734 mips_isa
< 3 ? "addu" : "daddu",
3735 "d,v,t", tempreg
, tempreg
, AT
);
3736 (void) frag_var (rs_machine_dependent
, 0, 0,
3737 RELAX_ENCODE (0, 0, -16 + off1
, -8, 0, 0),
3738 offset_expr
.X_add_symbol
, (long) 0,
3743 else if (mips_pic
== SVR4_PIC
)
3747 /* This is the large GOT case. If this is a reference to an
3748 external symbol, and there is no constant, we want
3749 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
3750 addu $tempreg,$tempreg,$gp
3751 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
3752 For a local symbol, we want
3753 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3755 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
3757 If we have a small constant, and this is a reference to
3758 an external symbol, we want
3759 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
3760 addu $tempreg,$tempreg,$gp
3761 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
3763 addiu $tempreg,$tempreg,<constant>
3764 For a local symbol, we want
3765 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3767 addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16)
3769 If we have a large constant, and this is a reference to
3770 an external symbol, we want
3771 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
3772 addu $tempreg,$tempreg,$gp
3773 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
3774 lui $at,<hiconstant>
3775 addiu $at,$at,<loconstant>
3776 addu $tempreg,$tempreg,$at
3777 For a local symbol, we want
3778 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3779 lui $at,<hiconstant>
3780 addiu $at,$at,<loconstant> (BFD_RELOC_LO16)
3781 addu $tempreg,$tempreg,$at
3783 expr1
.X_add_number
= offset_expr
.X_add_number
;
3784 offset_expr
.X_add_number
= 0;
3786 if (reg_needs_delay (GP
))
3790 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
3791 tempreg
, (int) BFD_RELOC_MIPS_GOT_HI16
);
3792 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3793 mips_isa
< 3 ? "addu" : "daddu",
3794 "d,v,t", tempreg
, tempreg
, GP
);
3795 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3797 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT_LO16
,
3799 if (expr1
.X_add_number
== 0)
3807 /* We're going to put in an addu instruction using
3808 tempreg, so we may as well insert the nop right
3810 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3815 p
= frag_var (rs_machine_dependent
, 12 + gpdel
, 0,
3816 RELAX_ENCODE (12 + off
, 12 + gpdel
, gpdel
,
3819 ? mips_warn_about_macros
3821 offset_expr
.X_add_symbol
, (long) 0,
3824 else if (expr1
.X_add_number
>= -0x8000
3825 && expr1
.X_add_number
< 0x8000)
3827 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3829 macro_build ((char *) NULL
, &icnt
, &expr1
,
3830 mips_isa
< 3 ? "addiu" : "daddiu",
3831 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
3833 p
= frag_var (rs_machine_dependent
, 12 + gpdel
, 0,
3834 RELAX_ENCODE (20, 12 + gpdel
, gpdel
, 8 + gpdel
, 0,
3836 ? mips_warn_about_macros
3838 offset_expr
.X_add_symbol
, (long) 0,
3845 /* If we are going to add in a base register, and the
3846 target register and the base register are the same,
3847 then we are using AT as a temporary register. Since
3848 we want to load the constant into AT, we add our
3849 current AT (from the global offset table) and the
3850 register into the register now, and pretend we were
3851 not using a base register. */
3859 assert (tempreg
== AT
);
3860 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3862 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3863 mips_isa
< 3 ? "addu" : "daddu",
3864 "d,v,t", treg
, AT
, breg
);
3869 /* Set mips_optimize around the lui instruction to avoid
3870 inserting an unnecessary nop after the lw. */
3871 hold_mips_optimize
= mips_optimize
;
3873 macro_build_lui ((char *) NULL
, &icnt
, &expr1
, AT
);
3874 mips_optimize
= hold_mips_optimize
;
3876 macro_build ((char *) NULL
, &icnt
, &expr1
,
3877 mips_isa
< 3 ? "addiu" : "daddiu",
3878 "t,r,j", AT
, AT
, (int) BFD_RELOC_LO16
);
3879 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3880 mips_isa
< 3 ? "addu" : "daddu",
3881 "d,v,t", dreg
, dreg
, AT
);
3883 p
= frag_var (rs_machine_dependent
, 16 + gpdel
+ adj
, 0,
3884 RELAX_ENCODE (24 + adj
, 16 + gpdel
+ adj
, gpdel
,
3887 ? mips_warn_about_macros
3889 offset_expr
.X_add_symbol
, (long) 0,
3897 /* This is needed because this instruction uses $gp, but
3898 the first instruction on the main stream does not. */
3899 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
3902 macro_build (p
, &icnt
, &offset_expr
,
3904 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
3906 if (expr1
.X_add_number
>= -0x8000
3907 && expr1
.X_add_number
< 0x8000)
3909 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
3911 macro_build (p
, &icnt
, &expr1
,
3912 mips_isa
< 3 ? "addiu" : "daddiu",
3913 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
3914 /* FIXME: If add_number is 0, and there was no base
3915 register, the external symbol case ended with a load,
3916 so if the symbol turns out to not be external, and
3917 the next instruction uses tempreg, an unnecessary nop
3918 will be inserted. */
3924 /* We must add in the base register now, as in the
3925 external symbol case. */
3926 assert (tempreg
== AT
);
3927 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
3929 macro_build (p
, &icnt
, (expressionS
*) NULL
,
3930 mips_isa
< 3 ? "addu" : "daddu",
3931 "d,v,t", treg
, AT
, breg
);
3934 /* We set breg to 0 because we have arranged to add
3935 it in in both cases. */
3939 macro_build_lui (p
, &icnt
, &expr1
, AT
);
3941 macro_build (p
, &icnt
, &expr1
,
3942 mips_isa
< 3 ? "addiu" : "daddiu",
3943 "t,r,j", AT
, AT
, (int) BFD_RELOC_LO16
);
3945 macro_build (p
, &icnt
, (expressionS
*) NULL
,
3946 mips_isa
< 3 ? "addu" : "daddu",
3947 "d,v,t", tempreg
, tempreg
, AT
);
3951 else if (mips_pic
== EMBEDDED_PIC
)
3954 addiu $tempreg,$gp,<sym> (BFD_RELOC_MIPS_GPREL)
3956 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3957 mips_isa
< 3 ? "addiu" : "daddiu",
3958 "t,r,j", tempreg
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
3964 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3965 mips_isa
< 3 ? "addu" : "daddu",
3966 "d,v,t", treg
, tempreg
, breg
);
3974 /* The j instruction may not be used in PIC code, since it
3975 requires an absolute address. We convert it to a b
3977 if (mips_pic
== NO_PIC
)
3978 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "j", "a");
3980 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "b", "p");
3983 /* The jal instructions must be handled as macros because when
3984 generating PIC code they expand to multi-instruction
3985 sequences. Normally they are simple instructions. */
3990 if (mips_pic
== NO_PIC
3991 || mips_pic
== EMBEDDED_PIC
)
3992 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "jalr",
3994 else if (mips_pic
== SVR4_PIC
)
3996 if (sreg
!= PIC_CALL_REG
)
3997 as_warn ("MIPS PIC call to register other than $25");
3999 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "jalr",
4001 if (mips_cprestore_offset
< 0)
4002 as_warn ("No .cprestore pseudo-op used in PIC code");
4005 expr1
.X_add_number
= mips_cprestore_offset
;
4006 macro_build ((char *) NULL
, &icnt
, &expr1
,
4007 mips_isa
< 3 ? "lw" : "ld",
4008 "t,o(b)", GP
, (int) BFD_RELOC_LO16
, mips_frame_reg
);
4017 if (mips_pic
== NO_PIC
)
4018 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "jal", "a");
4019 else if (mips_pic
== SVR4_PIC
)
4021 /* If this is a reference to an external symbol, and we are
4022 using a small GOT, we want
4023 lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
4027 lw $gp,cprestore($sp)
4028 The cprestore value is set using the .cprestore
4029 pseudo-op. If we are using a big GOT, we want
4030 lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16)
4032 lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16)
4036 lw $gp,cprestore($sp)
4037 If the symbol is not external, we want
4038 lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4040 addiu $25,$25,<sym> (BFD_RELOC_LO16)
4043 lw $gp,cprestore($sp) */
4047 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4048 mips_isa
< 3 ? "lw" : "ld",
4049 "t,o(b)", PIC_CALL_REG
,
4050 (int) BFD_RELOC_MIPS_CALL16
, GP
);
4051 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4053 p
= frag_var (rs_machine_dependent
, 4, 0,
4054 RELAX_ENCODE (0, 4, -8, 0, 0, 0),
4055 offset_expr
.X_add_symbol
, (long) 0, (char *) NULL
);
4061 if (reg_needs_delay (GP
))
4065 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
4066 PIC_CALL_REG
, (int) BFD_RELOC_MIPS_CALL_HI16
);
4067 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4068 mips_isa
< 3 ? "addu" : "daddu",
4069 "d,v,t", PIC_CALL_REG
, PIC_CALL_REG
, GP
);
4070 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4071 mips_isa
< 3 ? "lw" : "ld",
4072 "t,o(b)", PIC_CALL_REG
,
4073 (int) BFD_RELOC_MIPS_CALL_LO16
, PIC_CALL_REG
);
4074 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4076 p
= frag_var (rs_machine_dependent
, 12 + gpdel
, 0,
4077 RELAX_ENCODE (16, 12 + gpdel
, gpdel
, 8 + gpdel
,
4079 offset_expr
.X_add_symbol
, (long) 0, (char *) NULL
);
4082 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4085 macro_build (p
, &icnt
, &offset_expr
,
4086 mips_isa
< 3 ? "lw" : "ld",
4087 "t,o(b)", PIC_CALL_REG
,
4088 (int) BFD_RELOC_MIPS_GOT16
, GP
);
4090 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4093 macro_build (p
, &icnt
, &offset_expr
,
4094 mips_isa
< 3 ? "addiu" : "daddiu",
4095 "t,r,j", PIC_CALL_REG
, PIC_CALL_REG
,
4096 (int) BFD_RELOC_LO16
);
4097 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4098 "jalr", "s", PIC_CALL_REG
);
4099 if (mips_cprestore_offset
< 0)
4100 as_warn ("No .cprestore pseudo-op used in PIC code");
4104 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4106 expr1
.X_add_number
= mips_cprestore_offset
;
4107 macro_build ((char *) NULL
, &icnt
, &expr1
,
4108 mips_isa
< 3 ? "lw" : "ld",
4109 "t,o(b)", GP
, (int) BFD_RELOC_LO16
,
4113 else if (mips_pic
== EMBEDDED_PIC
)
4115 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "bal", "p");
4116 /* The linker may expand the call to a longer sequence which
4117 uses $at, so we must break rather than return. */
4193 if (breg
== treg
|| coproc
|| lr
)
4262 if (mask
== M_LWC1_AB
4263 || mask
== M_SWC1_AB
4264 || mask
== M_LDC1_AB
4265 || mask
== M_SDC1_AB
4274 if (offset_expr
.X_op
!= O_constant
4275 && offset_expr
.X_op
!= O_symbol
)
4277 as_bad ("expression too complex");
4278 offset_expr
.X_op
= O_constant
;
4281 /* A constant expression in PIC code can be handled just as it
4282 is in non PIC code. */
4283 if (mips_pic
== NO_PIC
4284 || offset_expr
.X_op
== O_constant
)
4286 /* If this is a reference to a GP relative symbol, and there
4287 is no base register, we want
4288 <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL)
4289 Otherwise, if there is no base register, we want
4290 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
4291 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
4292 If we have a constant, we need two instructions anyhow,
4293 so we always use the latter form.
4295 If we have a base register, and this is a reference to a
4296 GP relative symbol, we want
4297 addu $tempreg,$breg,$gp
4298 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GPREL)
4300 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
4301 addu $tempreg,$tempreg,$breg
4302 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
4303 With a constant we always use the latter case. */
4306 if ((valueT
) offset_expr
.X_add_number
>= MAX_GPREL_OFFSET
4307 || nopic_need_relax (offset_expr
.X_add_symbol
))
4312 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
4313 treg
, (int) BFD_RELOC_MIPS_GPREL
, GP
);
4314 p
= frag_var (rs_machine_dependent
, 8, 0,
4315 RELAX_ENCODE (4, 8, 0, 4, 0,
4316 (mips_warn_about_macros
4317 || (used_at
&& mips_noat
))),
4318 offset_expr
.X_add_symbol
, (long) 0,
4322 macro_build_lui (p
, &icnt
, &offset_expr
, tempreg
);
4325 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
, treg
,
4326 (int) BFD_RELOC_LO16
, tempreg
);
4330 if ((valueT
) offset_expr
.X_add_number
>= MAX_GPREL_OFFSET
4331 || nopic_need_relax (offset_expr
.X_add_symbol
))
4336 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4337 mips_isa
< 3 ? "addu" : "daddu",
4338 "d,v,t", tempreg
, breg
, GP
);
4339 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
4340 treg
, (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
4341 p
= frag_var (rs_machine_dependent
, 12, 0,
4342 RELAX_ENCODE (8, 12, 0, 8, 0, 0),
4343 offset_expr
.X_add_symbol
, (long) 0,
4346 macro_build_lui (p
, &icnt
, &offset_expr
, tempreg
);
4349 macro_build (p
, &icnt
, (expressionS
*) NULL
,
4350 mips_isa
< 3 ? "addu" : "daddu",
4351 "d,v,t", tempreg
, tempreg
, breg
);
4354 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
, treg
,
4355 (int) BFD_RELOC_LO16
, tempreg
);
4358 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
4360 /* If this is a reference to an external symbol, we want
4361 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4363 <op> $treg,0($tempreg)
4365 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4367 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
4368 <op> $treg,0($tempreg)
4369 If there is a base register, we add it to $tempreg before
4370 the <op>. If there is a constant, we stick it in the
4371 <op> instruction. We don't handle constants larger than
4372 16 bits, because we have no way to load the upper 16 bits
4373 (actually, we could handle them for the subset of cases
4374 in which we are not using $at). */
4375 assert (offset_expr
.X_op
== O_symbol
);
4376 expr1
.X_add_number
= offset_expr
.X_add_number
;
4377 offset_expr
.X_add_number
= 0;
4378 if (expr1
.X_add_number
< -0x8000
4379 || expr1
.X_add_number
>= 0x8000)
4380 as_bad ("PIC code offset overflow (max 16 signed bits)");
4382 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4383 mips_isa
< 3 ? "lw" : "ld",
4384 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
4385 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
4386 p
= frag_var (rs_machine_dependent
, 4, 0,
4387 RELAX_ENCODE (0, 4, -8, 0, 0, 0),
4388 offset_expr
.X_add_symbol
, (long) 0,
4390 macro_build (p
, &icnt
, &offset_expr
,
4391 mips_isa
< 3 ? "addiu" : "daddiu",
4392 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
4394 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4395 mips_isa
< 3 ? "addu" : "daddu",
4396 "d,v,t", tempreg
, tempreg
, breg
);
4397 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
, treg
,
4398 (int) BFD_RELOC_LO16
, tempreg
);
4400 else if (mips_pic
== SVR4_PIC
)
4404 /* If this is a reference to an external symbol, we want
4405 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
4406 addu $tempreg,$tempreg,$gp
4407 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
4408 <op> $treg,0($tempreg)
4410 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4412 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
4413 <op> $treg,0($tempreg)
4414 If there is a base register, we add it to $tempreg before
4415 the <op>. If there is a constant, we stick it in the
4416 <op> instruction. We don't handle constants larger than
4417 16 bits, because we have no way to load the upper 16 bits
4418 (actually, we could handle them for the subset of cases
4419 in which we are not using $at). */
4420 assert (offset_expr
.X_op
== O_symbol
);
4421 expr1
.X_add_number
= offset_expr
.X_add_number
;
4422 offset_expr
.X_add_number
= 0;
4423 if (expr1
.X_add_number
< -0x8000
4424 || expr1
.X_add_number
>= 0x8000)
4425 as_bad ("PIC code offset overflow (max 16 signed bits)");
4426 if (reg_needs_delay (GP
))
4431 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
4432 tempreg
, (int) BFD_RELOC_MIPS_GOT_HI16
);
4433 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4434 mips_isa
< 3 ? "addu" : "daddu",
4435 "d,v,t", tempreg
, tempreg
, GP
);
4436 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4437 mips_isa
< 3 ? "lw" : "ld",
4438 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT_LO16
,
4440 p
= frag_var (rs_machine_dependent
, 12 + gpdel
, 0,
4441 RELAX_ENCODE (12, 12 + gpdel
, gpdel
, 8 + gpdel
, 0, 0),
4442 offset_expr
.X_add_symbol
, (long) 0, (char *) NULL
);
4445 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4448 macro_build (p
, &icnt
, &offset_expr
,
4449 mips_isa
< 3 ? "lw" : "ld",
4450 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
4452 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4454 macro_build (p
, &icnt
, &offset_expr
,
4455 mips_isa
< 3 ? "addiu" : "daddiu",
4456 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
4458 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4459 mips_isa
< 3 ? "addu" : "daddu",
4460 "d,v,t", tempreg
, tempreg
, breg
);
4461 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
, treg
,
4462 (int) BFD_RELOC_LO16
, tempreg
);
4464 else if (mips_pic
== EMBEDDED_PIC
)
4466 /* If there is no base register, we want
4467 <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL)
4468 If there is a base register, we want
4469 addu $tempreg,$breg,$gp
4470 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GPREL)
4472 assert (offset_expr
.X_op
== O_symbol
);
4475 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
4476 treg
, (int) BFD_RELOC_MIPS_GPREL
, GP
);
4481 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4482 mips_isa
< 3 ? "addu" : "daddu",
4483 "d,v,t", tempreg
, breg
, GP
);
4484 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
4485 treg
, (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
4498 load_register (&icnt
, treg
, &imm_expr
, 0);
4502 load_register (&icnt
, treg
, &imm_expr
, 1);
4506 if (imm_expr
.X_op
== O_constant
)
4508 load_register (&icnt
, AT
, &imm_expr
, 0);
4509 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4510 "mtc1", "t,G", AT
, treg
);
4515 assert (offset_expr
.X_op
== O_symbol
4516 && strcmp (segment_name (S_GET_SEGMENT
4517 (offset_expr
.X_add_symbol
)),
4519 && offset_expr
.X_add_number
== 0);
4520 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lwc1", "T,o(b)",
4521 treg
, (int) BFD_RELOC_MIPS_LITERAL
, GP
);
4526 /* We know that sym is in the .rdata section. First we get the
4527 upper 16 bits of the address. */
4528 if (mips_pic
== NO_PIC
)
4530 /* FIXME: This won't work for a 64 bit address. */
4531 macro_build_lui ((char *) NULL
, &icnt
, &offset_expr
, AT
);
4533 else if (mips_pic
== SVR4_PIC
)
4535 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4536 mips_isa
< 3 ? "lw" : "ld",
4537 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
4539 else if (mips_pic
== EMBEDDED_PIC
)
4541 /* For embedded PIC we pick up the entire address off $gp in
4542 a single instruction. */
4543 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4544 mips_isa
< 3 ? "addiu" : "daddiu",
4545 "t,r,j", AT
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
4546 offset_expr
.X_op
= O_constant
;
4547 offset_expr
.X_add_number
= 0;
4552 /* Now we load the register(s). */
4554 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "ld", "t,o(b)",
4555 treg
, (int) BFD_RELOC_LO16
, AT
);
4558 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lw", "t,o(b)",
4559 treg
, (int) BFD_RELOC_LO16
, AT
);
4562 /* FIXME: How in the world do we deal with the possible
4564 offset_expr
.X_add_number
+= 4;
4565 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lw", "t,o(b)",
4566 treg
+ 1, (int) BFD_RELOC_LO16
, AT
);
4570 /* To avoid confusion in tc_gen_reloc, we must ensure that this
4571 does not become a variant frag. */
4572 frag_wane (frag_now
);
4578 assert (offset_expr
.X_op
== O_symbol
4579 && offset_expr
.X_add_number
== 0);
4580 s
= segment_name (S_GET_SEGMENT (offset_expr
.X_add_symbol
));
4581 if (strcmp (s
, ".lit8") == 0)
4585 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "ldc1",
4586 "T,o(b)", treg
, (int) BFD_RELOC_MIPS_LITERAL
, GP
);
4590 r
= BFD_RELOC_MIPS_LITERAL
;
4595 assert (strcmp (s
, RDATA_SECTION_NAME
) == 0);
4596 if (mips_pic
== SVR4_PIC
)
4597 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4598 mips_isa
< 3 ? "lw" : "ld",
4599 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
4602 /* FIXME: This won't work for a 64 bit address. */
4603 macro_build_lui ((char *) NULL
, &icnt
, &offset_expr
, AT
);
4608 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "ldc1",
4609 "T,o(b)", treg
, (int) BFD_RELOC_LO16
, AT
);
4611 /* To avoid confusion in tc_gen_reloc, we must ensure
4612 that this does not become a variant frag. */
4613 frag_wane (frag_now
);
4624 /* Even on a big endian machine $fn comes before $fn+1. We have
4625 to adjust when loading from memory. */
4628 assert (mips_isa
< 2);
4629 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lwc1", "T,o(b)",
4630 byte_order
== LITTLE_ENDIAN
? treg
: treg
+ 1,
4632 /* FIXME: A possible overflow which I don't know how to deal
4634 offset_expr
.X_add_number
+= 4;
4635 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lwc1", "T,o(b)",
4636 byte_order
== LITTLE_ENDIAN
? treg
+ 1 : treg
,
4639 /* To avoid confusion in tc_gen_reloc, we must ensure that this
4640 does not become a variant frag. */
4641 frag_wane (frag_now
);
4650 * The MIPS assembler seems to check for X_add_number not
4651 * being double aligned and generating:
4654 * addiu at,at,%lo(foo+1)
4657 * But, the resulting address is the same after relocation so why
4658 * generate the extra instruction?
4705 if (offset_expr
.X_op
!= O_symbol
4706 && offset_expr
.X_op
!= O_constant
)
4708 as_bad ("expression too complex");
4709 offset_expr
.X_op
= O_constant
;
4712 /* Even on a big endian machine $fn comes before $fn+1. We have
4713 to adjust when loading from memory. We set coproc if we must
4714 load $fn+1 first. */
4715 if (byte_order
== LITTLE_ENDIAN
)
4718 if (mips_pic
== NO_PIC
4719 || offset_expr
.X_op
== O_constant
)
4721 /* If this is a reference to a GP relative symbol, we want
4722 <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL)
4723 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_MIPS_GPREL)
4724 If we have a base register, we use this
4726 <op> $treg,<sym>($at) (BFD_RELOC_MIPS_GPREL)
4727 <op> $treg+1,<sym>+4($at) (BFD_RELOC_MIPS_GPREL)
4728 If this is not a GP relative symbol, we want
4729 lui $at,<sym> (BFD_RELOC_HI16_S)
4730 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
4731 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
4732 If there is a base register, we add it to $at after the
4733 lui instruction. If there is a constant, we always use
4735 if ((valueT
) offset_expr
.X_add_number
>= MAX_GPREL_OFFSET
4736 || nopic_need_relax (offset_expr
.X_add_symbol
))
4755 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4756 mips_isa
< 3 ? "addu" : "daddu",
4757 "d,v,t", AT
, breg
, GP
);
4763 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
4764 coproc
? treg
+ 1 : treg
,
4765 (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
4766 offset_expr
.X_add_number
+= 4;
4768 /* Set mips_optimize to 2 to avoid inserting an
4770 hold_mips_optimize
= mips_optimize
;
4772 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
4773 coproc
? treg
: treg
+ 1,
4774 (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
4775 mips_optimize
= hold_mips_optimize
;
4777 p
= frag_var (rs_machine_dependent
, 12 + off
, 0,
4778 RELAX_ENCODE (8 + off
, 12 + off
, 0, 4 + off
, 1,
4779 used_at
&& mips_noat
),
4780 offset_expr
.X_add_symbol
, (long) 0,
4783 /* We just generated two relocs. When tc_gen_reloc
4784 handles this case, it will skip the first reloc and
4785 handle the second. The second reloc already has an
4786 extra addend of 4, which we added above. We must
4787 subtract it out, and then subtract another 4 to make
4788 the first reloc come out right. The second reloc
4789 will come out right because we are going to add 4 to
4790 offset_expr when we build its instruction below. */
4791 offset_expr
.X_add_number
-= 8;
4792 offset_expr
.X_op
= O_constant
;
4794 macro_build_lui (p
, &icnt
, &offset_expr
, AT
);
4799 macro_build (p
, &icnt
, (expressionS
*) NULL
,
4800 mips_isa
< 3 ? "addu" : "daddu",
4801 "d,v,t", AT
, breg
, AT
);
4805 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
,
4806 coproc
? treg
+ 1 : treg
,
4807 (int) BFD_RELOC_LO16
, AT
);
4810 /* FIXME: How do we handle overflow here? */
4811 offset_expr
.X_add_number
+= 4;
4812 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
,
4813 coproc
? treg
: treg
+ 1,
4814 (int) BFD_RELOC_LO16
, AT
);
4816 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
4820 /* If this is a reference to an external symbol, we want
4821 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4826 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4828 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
4829 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
4830 If there is a base register we add it to $at before the
4831 lwc1 instructions. If there is a constant we include it
4832 in the lwc1 instructions. */
4834 expr1
.X_add_number
= offset_expr
.X_add_number
;
4835 offset_expr
.X_add_number
= 0;
4836 if (expr1
.X_add_number
< -0x8000
4837 || expr1
.X_add_number
>= 0x8000 - 4)
4838 as_bad ("PIC code offset overflow (max 16 signed bits)");
4843 frag_grow (24 + off
);
4844 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4845 mips_isa
< 3 ? "lw" : "ld",
4846 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
4847 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
4849 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4850 mips_isa
< 3 ? "addu" : "daddu",
4851 "d,v,t", AT
, breg
, AT
);
4852 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
4853 coproc
? treg
+ 1 : treg
,
4854 (int) BFD_RELOC_LO16
, AT
);
4855 expr1
.X_add_number
+= 4;
4857 /* Set mips_optimize to 2 to avoid inserting an undesired
4859 hold_mips_optimize
= mips_optimize
;
4861 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
4862 coproc
? treg
: treg
+ 1,
4863 (int) BFD_RELOC_LO16
, AT
);
4864 mips_optimize
= hold_mips_optimize
;
4866 (void) frag_var (rs_machine_dependent
, 0, 0,
4867 RELAX_ENCODE (0, 0, -16 - off
, -8, 1, 0),
4868 offset_expr
.X_add_symbol
, (long) 0,
4871 else if (mips_pic
== SVR4_PIC
)
4875 /* If this is a reference to an external symbol, we want
4876 lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16)
4878 lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16)
4883 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4885 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
4886 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
4887 If there is a base register we add it to $at before the
4888 lwc1 instructions. If there is a constant we include it
4889 in the lwc1 instructions. */
4891 expr1
.X_add_number
= offset_expr
.X_add_number
;
4892 offset_expr
.X_add_number
= 0;
4893 if (expr1
.X_add_number
< -0x8000
4894 || expr1
.X_add_number
>= 0x8000 - 4)
4895 as_bad ("PIC code offset overflow (max 16 signed bits)");
4896 if (reg_needs_delay (GP
))
4905 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
4906 AT
, (int) BFD_RELOC_MIPS_GOT_HI16
);
4907 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4908 mips_isa
< 3 ? "addu" : "daddu",
4909 "d,v,t", AT
, AT
, GP
);
4910 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4911 mips_isa
< 3 ? "lw" : "ld",
4912 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT_LO16
, AT
);
4913 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
4915 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4916 mips_isa
< 3 ? "addu" : "daddu",
4917 "d,v,t", AT
, breg
, AT
);
4918 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
4919 coproc
? treg
+ 1 : treg
,
4920 (int) BFD_RELOC_LO16
, AT
);
4921 expr1
.X_add_number
+= 4;
4923 /* Set mips_optimize to 2 to avoid inserting an undesired
4925 hold_mips_optimize
= mips_optimize
;
4927 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
4928 coproc
? treg
: treg
+ 1,
4929 (int) BFD_RELOC_LO16
, AT
);
4930 mips_optimize
= hold_mips_optimize
;
4931 expr1
.X_add_number
-= 4;
4933 p
= frag_var (rs_machine_dependent
, 16 + gpdel
+ off
, 0,
4934 RELAX_ENCODE (24 + off
, 16 + gpdel
+ off
, gpdel
,
4935 8 + gpdel
+ off
, 1, 0),
4936 offset_expr
.X_add_symbol
, (long) 0,
4940 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4943 macro_build (p
, &icnt
, &offset_expr
,
4944 mips_isa
< 3 ? "lw" : "ld",
4945 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
4947 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4951 macro_build (p
, &icnt
, (expressionS
*) NULL
,
4952 mips_isa
< 3 ? "addu" : "daddu",
4953 "d,v,t", AT
, breg
, AT
);
4956 macro_build (p
, &icnt
, &expr1
, s
, fmt
,
4957 coproc
? treg
+ 1 : treg
,
4958 (int) BFD_RELOC_LO16
, AT
);
4960 expr1
.X_add_number
+= 4;
4962 /* Set mips_optimize to 2 to avoid inserting an undesired
4964 hold_mips_optimize
= mips_optimize
;
4966 macro_build (p
, &icnt
, &expr1
, s
, fmt
,
4967 coproc
? treg
: treg
+ 1,
4968 (int) BFD_RELOC_LO16
, AT
);
4969 mips_optimize
= hold_mips_optimize
;
4971 else if (mips_pic
== EMBEDDED_PIC
)
4973 /* If there is no base register, we use
4974 <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL)
4975 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_MIPS_GPREL)
4976 If we have a base register, we use
4978 <op> $treg,<sym>($at) (BFD_RELOC_MIPS_GPREL)
4979 <op> $treg+1,<sym>+4($at) (BFD_RELOC_MIPS_GPREL)
4988 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4989 mips_isa
< 3 ? "addu" : "daddu",
4990 "d,v,t", AT
, breg
, GP
);
4995 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
4996 coproc
? treg
+ 1 : treg
,
4997 (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
4998 offset_expr
.X_add_number
+= 4;
4999 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
5000 coproc
? treg
: treg
+ 1,
5001 (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
5017 assert (mips_isa
< 3);
5018 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
5019 (int) BFD_RELOC_LO16
, breg
);
5020 offset_expr
.X_add_number
+= 4;
5021 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
+ 1,
5022 (int) BFD_RELOC_LO16
, breg
);
5024 #ifdef LOSING_COMPILER
5030 as_warn ("Macro used $at after \".set noat\"");
5035 struct mips_cl_insn
*ip
;
5037 register int treg
, sreg
, dreg
, breg
;
5052 bfd_reloc_code_real_type r
;
5055 treg
= (ip
->insn_opcode
>> 16) & 0x1f;
5056 dreg
= (ip
->insn_opcode
>> 11) & 0x1f;
5057 sreg
= breg
= (ip
->insn_opcode
>> 21) & 0x1f;
5058 mask
= ip
->insn_mo
->mask
;
5060 expr1
.X_op
= O_constant
;
5061 expr1
.X_op_symbol
= NULL
;
5062 expr1
.X_add_symbol
= NULL
;
5063 expr1
.X_add_number
= 1;
5067 #endif /* LOSING_COMPILER */
5072 macro_build ((char *) NULL
, &icnt
, NULL
,
5073 dbl
? "dmultu" : "multu",
5075 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
5081 /* The MIPS assembler some times generates shifts and adds. I'm
5082 not trying to be that fancy. GCC should do this for us
5084 load_register (&icnt
, AT
, &imm_expr
, dbl
);
5085 macro_build ((char *) NULL
, &icnt
, NULL
,
5086 dbl
? "dmult" : "mult",
5088 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
5094 mips_emit_delays ();
5096 mips_any_noreorder
= 1;
5097 macro_build ((char *) NULL
, &icnt
, NULL
,
5098 dbl
? "dmult" : "mult",
5100 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
5101 macro_build ((char *) NULL
, &icnt
, NULL
,
5102 dbl
? "dsra32" : "sra",
5103 "d,w,<", dreg
, dreg
, 31);
5104 macro_build ((char *) NULL
, &icnt
, NULL
, "mfhi", "d", AT
);
5106 macro_build ((char *) NULL
, &icnt
, NULL
, "tne", "s,t", dreg
, AT
);
5109 expr1
.X_add_number
= 8;
5110 macro_build ((char *) NULL
, &icnt
, &expr1
, "beq", "s,t,p", dreg
, AT
);
5111 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
5112 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 6);
5115 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
5121 mips_emit_delays ();
5123 mips_any_noreorder
= 1;
5124 macro_build ((char *) NULL
, &icnt
, NULL
,
5125 dbl
? "dmultu" : "multu",
5127 macro_build ((char *) NULL
, &icnt
, NULL
, "mfhi", "d", AT
);
5128 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
5130 macro_build ((char *) NULL
, &icnt
, NULL
, "tne", "s,t", AT
, 0);
5133 expr1
.X_add_number
= 8;
5134 macro_build ((char *) NULL
, &icnt
, &expr1
, "beq", "s,t,p", AT
, 0);
5135 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
5136 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 6);
5142 macro_build ((char *) NULL
, &icnt
, NULL
, "subu", "d,v,t", AT
, 0, treg
);
5143 macro_build ((char *) NULL
, &icnt
, NULL
, "srlv", "d,t,s", AT
, sreg
, AT
);
5144 macro_build ((char *) NULL
, &icnt
, NULL
, "sllv", "d,t,s", dreg
, sreg
,
5146 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
5150 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", AT
, sreg
,
5151 (int) (imm_expr
.X_add_number
& 0x1f));
5152 macro_build ((char *) NULL
, &icnt
, NULL
, "srl", "d,w,<", dreg
, sreg
,
5153 (int) ((0 - imm_expr
.X_add_number
) & 0x1f));
5154 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
5158 macro_build ((char *) NULL
, &icnt
, NULL
, "subu", "d,v,t", AT
, 0, treg
);
5159 macro_build ((char *) NULL
, &icnt
, NULL
, "sllv", "d,t,s", AT
, sreg
, AT
);
5160 macro_build ((char *) NULL
, &icnt
, NULL
, "srlv", "d,t,s", dreg
, sreg
,
5162 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
5166 macro_build ((char *) NULL
, &icnt
, NULL
, "srl", "d,w,<", AT
, sreg
,
5167 (int) (imm_expr
.X_add_number
& 0x1f));
5168 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", dreg
, sreg
,
5169 (int) ((0 - imm_expr
.X_add_number
) & 0x1f));
5170 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
5174 assert (mips_isa
< 2);
5175 /* Even on a big endian machine $fn comes before $fn+1. We have
5176 to adjust when storing to memory. */
5177 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "swc1", "T,o(b)",
5178 byte_order
== LITTLE_ENDIAN
? treg
: treg
+ 1,
5179 (int) BFD_RELOC_LO16
, breg
);
5180 offset_expr
.X_add_number
+= 4;
5181 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "swc1", "T,o(b)",
5182 byte_order
== LITTLE_ENDIAN
? treg
+ 1 : treg
,
5183 (int) BFD_RELOC_LO16
, breg
);
5188 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
5189 treg
, (int) BFD_RELOC_LO16
);
5191 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
5192 sreg
, (int) BFD_RELOC_LO16
);
5195 macro_build ((char *) NULL
, &icnt
, NULL
, "xor", "d,v,t", dreg
,
5197 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
5198 dreg
, (int) BFD_RELOC_LO16
);
5203 if (imm_expr
.X_add_number
== 0)
5205 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
5206 sreg
, (int) BFD_RELOC_LO16
);
5211 as_warn ("Instruction %s: result is always false",
5213 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
, 0);
5216 if (imm_expr
.X_add_number
>= 0 && imm_expr
.X_add_number
< 0x10000)
5218 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "xori", "t,r,i", dreg
,
5219 sreg
, (int) BFD_RELOC_LO16
);
5222 else if (imm_expr
.X_add_number
> -0x8000 && imm_expr
.X_add_number
< 0)
5224 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
5225 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
5226 mips_isa
< 3 ? "addiu" : "daddiu",
5227 "t,r,j", dreg
, sreg
,
5228 (int) BFD_RELOC_LO16
);
5233 load_register (&icnt
, AT
, &imm_expr
, 0);
5234 macro_build ((char *) NULL
, &icnt
, NULL
, "xor", "d,v,t", dreg
,
5238 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
, dreg
,
5239 (int) BFD_RELOC_LO16
);
5244 case M_SGE
: /* sreg >= treg <==> not (sreg < treg) */
5250 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, sreg
, treg
);
5251 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
5252 (int) BFD_RELOC_LO16
);
5255 case M_SGE_I
: /* sreg >= I <==> not (sreg < I) */
5257 if (imm_expr
.X_add_number
>= -0x8000 && imm_expr
.X_add_number
< 0x8000)
5259 macro_build ((char *) NULL
, &icnt
, &expr1
,
5260 mask
== M_SGE_I
? "slti" : "sltiu",
5261 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
5266 load_register (&icnt
, AT
, &imm_expr
, 0);
5267 macro_build ((char *) NULL
, &icnt
, NULL
,
5268 mask
== M_SGE_I
? "slt" : "sltu",
5269 "d,v,t", dreg
, sreg
, AT
);
5272 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
5273 (int) BFD_RELOC_LO16
);
5278 case M_SGT
: /* sreg > treg <==> treg < sreg */
5284 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, treg
, sreg
);
5287 case M_SGT_I
: /* sreg > I <==> I < sreg */
5293 load_register (&icnt
, AT
, &imm_expr
, 0);
5294 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, AT
, sreg
);
5297 case M_SLE
: /* sreg <= treg <==> treg >= sreg <==> not (treg < sreg) */
5303 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, treg
, sreg
);
5304 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
5305 (int) BFD_RELOC_LO16
);
5308 case M_SLE_I
: /* sreg <= I <==> I >= sreg <==> not (I < sreg) */
5314 load_register (&icnt
, AT
, &imm_expr
, 0);
5315 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, AT
, sreg
);
5316 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
5317 (int) BFD_RELOC_LO16
);
5321 if (imm_expr
.X_add_number
>= -0x8000 && imm_expr
.X_add_number
< 0x8000)
5323 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "slti", "t,r,j",
5324 dreg
, sreg
, (int) BFD_RELOC_LO16
);
5327 load_register (&icnt
, AT
, &imm_expr
, 0);
5328 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", dreg
, sreg
, AT
);
5332 if (imm_expr
.X_add_number
>= -0x8000 && imm_expr
.X_add_number
< 0x8000)
5334 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "sltiu", "t,r,j",
5335 dreg
, sreg
, (int) BFD_RELOC_LO16
);
5338 load_register (&icnt
, AT
, &imm_expr
, 0);
5339 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, sreg
,
5345 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0,
5348 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0,
5352 macro_build ((char *) NULL
, &icnt
, NULL
, "xor", "d,v,t", dreg
,
5354 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0,
5360 if (imm_expr
.X_add_number
== 0)
5362 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0,
5368 as_warn ("Instruction %s: result is always true",
5370 macro_build ((char *) NULL
, &icnt
, &expr1
,
5371 mips_isa
< 3 ? "addiu" : "daddiu",
5372 "t,r,j", dreg
, 0, (int) BFD_RELOC_LO16
);
5375 if (imm_expr
.X_add_number
>= 0 && imm_expr
.X_add_number
< 0x10000)
5377 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "xori", "t,r,i",
5378 dreg
, sreg
, (int) BFD_RELOC_LO16
);
5381 else if (imm_expr
.X_add_number
> -0x8000 && imm_expr
.X_add_number
< 0)
5383 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
5384 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
5385 mips_isa
< 3 ? "addiu" : "daddiu",
5386 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
5391 load_register (&icnt
, AT
, &imm_expr
, 0);
5392 macro_build ((char *) NULL
, &icnt
, NULL
, "xor", "d,v,t", dreg
,
5396 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0, dreg
);
5404 if (imm_expr
.X_add_number
> -0x8000 && imm_expr
.X_add_number
<= 0x8000)
5406 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
5407 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
5408 dbl
? "daddi" : "addi",
5409 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
5412 load_register (&icnt
, AT
, &imm_expr
, dbl
);
5413 macro_build ((char *) NULL
, &icnt
, NULL
,
5414 dbl
? "dsub" : "sub",
5415 "d,v,t", dreg
, sreg
, AT
);
5421 if (imm_expr
.X_add_number
> -0x8000 && imm_expr
.X_add_number
<= 0x8000)
5423 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
5424 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
5425 dbl
? "daddiu" : "addiu",
5426 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
5429 load_register (&icnt
, AT
, &imm_expr
, dbl
);
5430 macro_build ((char *) NULL
, &icnt
, NULL
,
5431 dbl
? "dsubu" : "subu",
5432 "d,v,t", dreg
, sreg
, AT
);
5453 load_register (&icnt
, AT
, &imm_expr
, 0);
5454 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "s,t", sreg
, AT
);
5459 assert (mips_isa
< 2);
5460 sreg
= (ip
->insn_opcode
>> 11) & 0x1f; /* floating reg */
5461 dreg
= (ip
->insn_opcode
>> 06) & 0x1f; /* floating reg */
5464 * Is the double cfc1 instruction a bug in the mips assembler;
5465 * or is there a reason for it?
5467 mips_emit_delays ();
5469 mips_any_noreorder
= 1;
5470 macro_build ((char *) NULL
, &icnt
, NULL
, "cfc1", "t,G", treg
, 31);
5471 macro_build ((char *) NULL
, &icnt
, NULL
, "cfc1", "t,G", treg
, 31);
5472 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "");
5473 expr1
.X_add_number
= 3;
5474 macro_build ((char *) NULL
, &icnt
, &expr1
, "ori", "t,r,i", AT
, treg
,
5475 (int) BFD_RELOC_LO16
);
5476 expr1
.X_add_number
= 2;
5477 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", AT
, AT
,
5478 (int) BFD_RELOC_LO16
);
5479 macro_build ((char *) NULL
, &icnt
, NULL
, "ctc1", "t,G", AT
, 31);
5480 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "");
5481 macro_build ((char *) NULL
, &icnt
, NULL
,
5482 mask
== M_TRUNCWD
? "cvt.w.d" : "cvt.w.s", "D,S", dreg
, sreg
);
5483 macro_build ((char *) NULL
, &icnt
, NULL
, "ctc1", "t,G", treg
, 31);
5484 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "");
5494 if (offset_expr
.X_add_number
>= 0x7fff)
5495 as_bad ("operand overflow");
5496 /* avoid load delay */
5497 if (byte_order
== LITTLE_ENDIAN
)
5498 offset_expr
.X_add_number
+= 1;
5499 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
5500 (int) BFD_RELOC_LO16
, breg
);
5501 if (byte_order
== LITTLE_ENDIAN
)
5502 offset_expr
.X_add_number
-= 1;
5504 offset_expr
.X_add_number
+= 1;
5505 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lbu", "t,o(b)", AT
,
5506 (int) BFD_RELOC_LO16
, breg
);
5507 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", treg
, treg
, 8);
5508 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", treg
, treg
, AT
);
5521 if (offset_expr
.X_add_number
>= 0x8000 - off
)
5522 as_bad ("operand overflow");
5523 if (byte_order
== LITTLE_ENDIAN
)
5524 offset_expr
.X_add_number
+= off
;
5525 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
5526 (int) BFD_RELOC_LO16
, breg
);
5527 if (byte_order
== LITTLE_ENDIAN
)
5528 offset_expr
.X_add_number
-= off
;
5530 offset_expr
.X_add_number
+= off
;
5531 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s2
, "t,o(b)", treg
,
5532 (int) BFD_RELOC_LO16
, breg
);
5545 load_address (&icnt
, AT
, &offset_expr
);
5547 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5548 mips_isa
< 3 ? "addu" : "daddu",
5549 "d,v,t", AT
, AT
, breg
);
5550 if (byte_order
== LITTLE_ENDIAN
)
5551 expr1
.X_add_number
= off
;
5553 expr1
.X_add_number
= 0;
5554 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, "t,o(b)", treg
,
5555 (int) BFD_RELOC_LO16
, AT
);
5556 if (byte_order
== LITTLE_ENDIAN
)
5557 expr1
.X_add_number
= 0;
5559 expr1
.X_add_number
= off
;
5560 macro_build ((char *) NULL
, &icnt
, &expr1
, s2
, "t,o(b)", treg
,
5561 (int) BFD_RELOC_LO16
, AT
);
5566 load_address (&icnt
, AT
, &offset_expr
);
5568 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5569 mips_isa
< 3 ? "addu" : "daddu",
5570 "d,v,t", AT
, AT
, breg
);
5571 if (byte_order
== BIG_ENDIAN
)
5572 expr1
.X_add_number
= 0;
5573 macro_build ((char *) NULL
, &icnt
, &expr1
,
5574 mask
== M_ULH_A
? "lb" : "lbu", "t,o(b)", treg
,
5575 (int) BFD_RELOC_LO16
, AT
);
5576 if (byte_order
== BIG_ENDIAN
)
5577 expr1
.X_add_number
= 1;
5579 expr1
.X_add_number
= 0;
5580 macro_build ((char *) NULL
, &icnt
, &expr1
, "lbu", "t,o(b)", AT
,
5581 (int) BFD_RELOC_LO16
, AT
);
5582 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", treg
,
5584 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", treg
,
5589 if (offset_expr
.X_add_number
>= 0x7fff)
5590 as_bad ("operand overflow");
5591 if (byte_order
== BIG_ENDIAN
)
5592 offset_expr
.X_add_number
+= 1;
5593 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "sb", "t,o(b)", treg
,
5594 (int) BFD_RELOC_LO16
, breg
);
5595 macro_build ((char *) NULL
, &icnt
, NULL
, "srl", "d,w,<", AT
, treg
, 8);
5596 if (byte_order
== BIG_ENDIAN
)
5597 offset_expr
.X_add_number
-= 1;
5599 offset_expr
.X_add_number
+= 1;
5600 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "sb", "t,o(b)", AT
,
5601 (int) BFD_RELOC_LO16
, breg
);
5614 if (offset_expr
.X_add_number
>= 0x8000 - off
)
5615 as_bad ("operand overflow");
5616 if (byte_order
== LITTLE_ENDIAN
)
5617 offset_expr
.X_add_number
+= off
;
5618 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
5619 (int) BFD_RELOC_LO16
, breg
);
5620 if (byte_order
== LITTLE_ENDIAN
)
5621 offset_expr
.X_add_number
-= off
;
5623 offset_expr
.X_add_number
+= off
;
5624 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s2
, "t,o(b)", treg
,
5625 (int) BFD_RELOC_LO16
, breg
);
5638 load_address (&icnt
, AT
, &offset_expr
);
5640 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5641 mips_isa
< 3 ? "addu" : "daddu",
5642 "d,v,t", AT
, AT
, breg
);
5643 if (byte_order
== LITTLE_ENDIAN
)
5644 expr1
.X_add_number
= off
;
5646 expr1
.X_add_number
= 0;
5647 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, "t,o(b)", treg
,
5648 (int) BFD_RELOC_LO16
, AT
);
5649 if (byte_order
== LITTLE_ENDIAN
)
5650 expr1
.X_add_number
= 0;
5652 expr1
.X_add_number
= off
;
5653 macro_build ((char *) NULL
, &icnt
, &expr1
, s2
, "t,o(b)", treg
,
5654 (int) BFD_RELOC_LO16
, AT
);
5658 load_address (&icnt
, AT
, &offset_expr
);
5660 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5661 mips_isa
< 3 ? "addu" : "daddu",
5662 "d,v,t", AT
, AT
, breg
);
5663 if (byte_order
== LITTLE_ENDIAN
)
5664 expr1
.X_add_number
= 0;
5665 macro_build ((char *) NULL
, &icnt
, &expr1
, "sb", "t,o(b)", treg
,
5666 (int) BFD_RELOC_LO16
, AT
);
5667 macro_build ((char *) NULL
, &icnt
, NULL
, "srl", "d,w,<", treg
,
5669 if (byte_order
== LITTLE_ENDIAN
)
5670 expr1
.X_add_number
= 1;
5672 expr1
.X_add_number
= 0;
5673 macro_build ((char *) NULL
, &icnt
, &expr1
, "sb", "t,o(b)", treg
,
5674 (int) BFD_RELOC_LO16
, AT
);
5675 if (byte_order
== LITTLE_ENDIAN
)
5676 expr1
.X_add_number
= 0;
5678 expr1
.X_add_number
= 1;
5679 macro_build ((char *) NULL
, &icnt
, &expr1
, "lbu", "t,o(b)", AT
,
5680 (int) BFD_RELOC_LO16
, AT
);
5681 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", treg
,
5683 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", treg
,
5688 as_bad ("Macro %s not implemented yet", ip
->insn_mo
->name
);
5692 as_warn ("Macro used $at after \".set noat\"");
5695 /* Implement macros in mips16 mode. */
5699 struct mips_cl_insn
*ip
;
5702 int xreg
, yreg
, zreg
, tmp
;
5706 const char *s
, *s2
, *s3
;
5708 mask
= ip
->insn_mo
->mask
;
5710 xreg
= (ip
->insn_opcode
>> MIPS16OP_SH_RX
) & MIPS16OP_MASK_RX
;
5711 yreg
= (ip
->insn_opcode
>> MIPS16OP_SH_RY
) & MIPS16OP_MASK_RY
;
5712 zreg
= (ip
->insn_opcode
>> MIPS16OP_SH_RZ
) & MIPS16OP_MASK_RZ
;
5716 expr1
.X_op
= O_constant
;
5717 expr1
.X_op_symbol
= NULL
;
5718 expr1
.X_add_symbol
= NULL
;
5719 expr1
.X_add_number
= 1;
5738 mips_emit_delays ();
5740 mips_any_noreorder
= 1;
5741 macro_build ((char *) NULL
, &icnt
, NULL
,
5742 dbl
? "ddiv" : "div",
5743 "0,x,y", xreg
, yreg
);
5744 expr1
.X_add_number
= 2;
5745 macro_build ((char *) NULL
, &icnt
, &expr1
, "bnez", "x,p", yreg
);
5746 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "6", 7);
5747 /* FIXME: The normal code checks for of -1 / -0x80000000 here,
5748 since that causes an overflow. We should do that as well,
5749 but I don't see how to do the comparisons without a temporary
5752 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "x", zreg
);
5771 mips_emit_delays ();
5773 mips_any_noreorder
= 1;
5774 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "0,x,y", xreg
, yreg
);
5775 expr1
.X_add_number
= 2;
5776 macro_build ((char *) NULL
, &icnt
, &expr1
, "bnez", "x,p", yreg
);
5777 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "6", 7);
5779 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "x", zreg
);
5787 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
5788 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
5789 dbl
? "daddiu" : "addiu",
5790 "y,x,4", yreg
, xreg
);
5794 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
5795 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "addiu",
5800 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
5801 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "daddiu",
5824 goto do_reverse_branch
;
5828 goto do_reverse_branch
;
5840 goto do_reverse_branch
;
5851 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s
, "x,y",
5853 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s2
, "p");
5880 goto do_addone_branch_i
;
5885 goto do_addone_branch_i
;
5900 goto do_addone_branch_i
;
5907 ++imm_expr
.X_add_number
;
5910 macro_build ((char *) NULL
, &icnt
, &imm_expr
, s
, s3
, xreg
);
5911 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s2
, "p");
5916 /* This routine assembles an instruction into its binary format. As a
5917 side effect, it sets one of the global variables imm_reloc or
5918 offset_reloc to the type of relocation to do if one of the operands
5919 is an address expression. */
5924 struct mips_cl_insn
*ip
;
5929 struct mips_opcode
*insn
;
5932 unsigned int lastregno
= 0;
5937 for (s
= str
; islower (*s
) || (*s
>= '0' && *s
<= '3') || *s
== '6' || *s
== '.'; ++s
)
5949 as_fatal ("Unknown opcode: `%s'", str
);
5951 if ((insn
= (struct mips_opcode
*) hash_find (op_hash
, str
)) == NULL
)
5953 insn_error
= "unrecognized opcode";
5961 assert (strcmp (insn
->name
, str
) == 0);
5963 if (insn
->pinfo
== INSN_MACRO
)
5964 insn_isa
= insn
->match
;
5965 else if ((insn
->pinfo
& INSN_ISA
) == INSN_ISA2
)
5967 else if ((insn
->pinfo
& INSN_ISA
) == INSN_ISA3
)
5969 else if ((insn
->pinfo
& INSN_ISA
) == INSN_ISA4
)
5974 if (insn_isa
> mips_isa
5975 || ((insn
->pinfo
& INSN_ISA
) == INSN_4650
5977 || ((insn
->pinfo
& INSN_ISA
) == INSN_4010
5979 || ((insn
->pinfo
& INSN_ISA
) == INSN_4100
5982 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
]
5983 && strcmp (insn
->name
, insn
[1].name
) == 0)
5988 if (insn_isa
<= mips_isa
)
5989 insn_error
= "opcode not supported on this processor";
5992 static char buf
[100];
5994 sprintf (buf
, "opcode requires -mips%d or greater", insn_isa
);
6001 ip
->insn_opcode
= insn
->match
;
6002 for (args
= insn
->args
;; ++args
)
6008 case '\0': /* end of args */
6021 ip
->insn_opcode
|= lastregno
<< 21;
6026 ip
->insn_opcode
|= lastregno
<< 16;
6030 ip
->insn_opcode
|= lastregno
<< 11;
6036 /* handle optional base register.
6037 Either the base register is omitted or
6038 we must have a left paren. */
6039 /* this is dependent on the next operand specifier
6040 is a 'b' for base register */
6041 assert (args
[1] == 'b');
6045 case ')': /* these must match exactly */
6050 case '<': /* must be at least one digit */
6052 * According to the manual, if the shift amount is greater
6053 * than 31 or less than 0 the the shift amount should be
6054 * mod 32. In reality the mips assembler issues an error.
6055 * We issue a warning and mask out all but the low 5 bits.
6057 my_getExpression (&imm_expr
, s
);
6058 check_absolute_expr (ip
, &imm_expr
);
6059 if ((unsigned long) imm_expr
.X_add_number
> 31)
6061 as_warn ("Improper shift amount (%ld)",
6062 (long) imm_expr
.X_add_number
);
6063 imm_expr
.X_add_number
= imm_expr
.X_add_number
& 0x1f;
6065 ip
->insn_opcode
|= imm_expr
.X_add_number
<< 6;
6066 imm_expr
.X_op
= O_absent
;
6070 case '>': /* shift amount minus 32 */
6071 my_getExpression (&imm_expr
, s
);
6072 check_absolute_expr (ip
, &imm_expr
);
6073 if ((unsigned long) imm_expr
.X_add_number
< 32
6074 || (unsigned long) imm_expr
.X_add_number
> 63)
6076 ip
->insn_opcode
|= (imm_expr
.X_add_number
- 32) << 6;
6077 imm_expr
.X_op
= O_absent
;
6081 case 'k': /* cache code */
6082 case 'h': /* prefx code */
6083 my_getExpression (&imm_expr
, s
);
6084 check_absolute_expr (ip
, &imm_expr
);
6085 if ((unsigned long) imm_expr
.X_add_number
> 31)
6087 as_warn ("Invalid value for `%s' (%lu)",
6089 (unsigned long) imm_expr
.X_add_number
);
6090 imm_expr
.X_add_number
&= 0x1f;
6093 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_CACHE
;
6095 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_PREFX
;
6096 imm_expr
.X_op
= O_absent
;
6100 case 'c': /* break code */
6101 my_getExpression (&imm_expr
, s
);
6102 check_absolute_expr (ip
, &imm_expr
);
6103 if ((unsigned) imm_expr
.X_add_number
> 1023)
6104 as_warn ("Illegal break code (%ld)",
6105 (long) imm_expr
.X_add_number
);
6106 ip
->insn_opcode
|= imm_expr
.X_add_number
<< 16;
6107 imm_expr
.X_op
= O_absent
;
6111 case 'B': /* syscall code */
6112 my_getExpression (&imm_expr
, s
);
6113 check_absolute_expr (ip
, &imm_expr
);
6114 if ((unsigned) imm_expr
.X_add_number
> 0xfffff)
6115 as_warn ("Illegal syscall code (%ld)",
6116 (long) imm_expr
.X_add_number
);
6117 ip
->insn_opcode
|= imm_expr
.X_add_number
<< 6;
6118 imm_expr
.X_op
= O_absent
;
6122 case 'C': /* Coprocessor code */
6123 my_getExpression (&imm_expr
, s
);
6124 check_absolute_expr (ip
, &imm_expr
);
6125 if ((unsigned long) imm_expr
.X_add_number
>= (1<<25))
6127 as_warn ("Coproccesor code > 25 bits (%ld)",
6128 (long) imm_expr
.X_add_number
);
6129 imm_expr
.X_add_number
&= ((1<<25) - 1);
6131 ip
->insn_opcode
|= imm_expr
.X_add_number
;
6132 imm_expr
.X_op
= O_absent
;
6136 case 'b': /* base register */
6137 case 'd': /* destination register */
6138 case 's': /* source register */
6139 case 't': /* target register */
6140 case 'r': /* both target and source */
6141 case 'v': /* both dest and source */
6142 case 'w': /* both dest and target */
6143 case 'E': /* coprocessor target register */
6144 case 'G': /* coprocessor destination register */
6145 case 'x': /* ignore register name */
6146 case 'z': /* must be zero register */
6160 while (isdigit (*s
));
6162 as_bad ("Invalid register number (%d)", regno
);
6164 else if (*args
== 'E' || *args
== 'G')
6168 if (s
[1] == 'f' && s
[2] == 'p')
6173 else if (s
[1] == 's' && s
[2] == 'p')
6178 else if (s
[1] == 'g' && s
[2] == 'p')
6183 else if (s
[1] == 'a' && s
[2] == 't')
6188 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '0')
6193 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '1')
6205 as_warn ("Used $at without \".set noat\"");
6211 if (c
== 'r' || c
== 'v' || c
== 'w')
6218 /* 'z' only matches $0. */
6219 if (c
== 'z' && regno
!= 0)
6227 ip
->insn_opcode
|= regno
<< 21;
6231 ip
->insn_opcode
|= regno
<< 11;
6236 ip
->insn_opcode
|= regno
<< 16;
6239 /* This case exists because on the r3000 trunc
6240 expands into a macro which requires a gp
6241 register. On the r6000 or r4000 it is
6242 assembled into a single instruction which
6243 ignores the register. Thus the insn version
6244 is MIPS_ISA2 and uses 'x', and the macro
6245 version is MIPS_ISA1 and uses 't'. */
6248 /* This case is for the div instruction, which
6249 acts differently if the destination argument
6250 is $0. This only matches $0, and is checked
6251 outside the switch. */
6262 ip
->insn_opcode
|= lastregno
<< 21;
6265 ip
->insn_opcode
|= lastregno
<< 16;
6270 case 'D': /* floating point destination register */
6271 case 'S': /* floating point source register */
6272 case 'T': /* floating point target register */
6273 case 'R': /* floating point source register */
6277 if (s
[0] == '$' && s
[1] == 'f' && isdigit (s
[2]))
6287 while (isdigit (*s
));
6290 as_bad ("Invalid float register number (%d)", regno
);
6292 if ((regno
& 1) != 0
6294 && ! (strcmp (str
, "mtc1") == 0
6295 || strcmp (str
, "mfc1") == 0
6296 || strcmp (str
, "lwc1") == 0
6297 || strcmp (str
, "swc1") == 0
6298 || strcmp (str
, "l.s") == 0
6299 || strcmp (str
, "s.s") == 0))
6300 as_warn ("Float register should be even, was %d",
6308 if (c
== 'V' || c
== 'W')
6318 ip
->insn_opcode
|= regno
<< 6;
6322 ip
->insn_opcode
|= regno
<< 11;
6326 ip
->insn_opcode
|= regno
<< 16;
6329 ip
->insn_opcode
|= regno
<< 21;
6338 ip
->insn_opcode
|= lastregno
<< 11;
6341 ip
->insn_opcode
|= lastregno
<< 16;
6347 my_getExpression (&imm_expr
, s
);
6348 if (imm_expr
.X_op
!= O_big
6349 && imm_expr
.X_op
!= O_constant
)
6350 insn_error
= "absolute expression required";
6355 my_getExpression (&offset_expr
, s
);
6356 imm_reloc
= BFD_RELOC_32
;
6368 unsigned char temp
[8];
6370 unsigned int length
;
6375 /* These only appear as the last operand in an
6376 instruction, and every instruction that accepts
6377 them in any variant accepts them in all variants.
6378 This means we don't have to worry about backing out
6379 any changes if the instruction does not match.
6381 The difference between them is the size of the
6382 floating point constant and where it goes. For 'F'
6383 and 'L' the constant is 64 bits; for 'f' and 'l' it
6384 is 32 bits. Where the constant is placed is based
6385 on how the MIPS assembler does things:
6388 f -- immediate value
6391 The .lit4 and .lit8 sections are only used if
6392 permitted by the -G argument.
6394 When generating embedded PIC code, we use the
6395 .lit8 section but not the .lit4 section (we can do
6396 .lit4 inline easily; we need to put .lit8
6397 somewhere in the data segment, and using .lit8
6398 permits the linker to eventually combine identical
6401 f64
= *args
== 'F' || *args
== 'L';
6403 save_in
= input_line_pointer
;
6404 input_line_pointer
= s
;
6405 err
= md_atof (f64
? 'd' : 'f', (char *) temp
, &len
);
6407 s
= input_line_pointer
;
6408 input_line_pointer
= save_in
;
6409 if (err
!= NULL
&& *err
!= '\0')
6411 as_bad ("Bad floating point constant: %s", err
);
6412 memset (temp
, '\0', sizeof temp
);
6413 length
= f64
? 8 : 4;
6416 assert (length
== (f64
? 8 : 4));
6420 && (! USE_GLOBAL_POINTER_OPT
6421 || mips_pic
== EMBEDDED_PIC
6422 || g_switch_value
< 4)
6425 imm_expr
.X_op
= O_constant
;
6426 if (byte_order
== LITTLE_ENDIAN
)
6427 imm_expr
.X_add_number
=
6428 (((((((int) temp
[3] << 8)
6433 imm_expr
.X_add_number
=
6434 (((((((int) temp
[0] << 8)
6441 const char *newname
;
6444 /* Switch to the right section. */
6446 subseg
= now_subseg
;
6449 default: /* unused default case avoids warnings. */
6451 newname
= RDATA_SECTION_NAME
;
6452 if (USE_GLOBAL_POINTER_OPT
&& g_switch_value
>= 8)
6456 newname
= RDATA_SECTION_NAME
;
6459 assert (!USE_GLOBAL_POINTER_OPT
6460 || g_switch_value
>= 4);
6464 new_seg
= subseg_new (newname
, (subsegT
) 0);
6465 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
6466 bfd_set_section_flags (stdoutput
, new_seg
,
6471 frag_align (*args
== 'l' ? 2 : 3, 0);
6472 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
6473 record_alignment (new_seg
, 4);
6475 record_alignment (new_seg
, *args
== 'l' ? 2 : 3);
6477 as_bad ("Can't use floating point insn in this section");
6479 /* Set the argument to the current address in the
6481 offset_expr
.X_op
= O_symbol
;
6482 offset_expr
.X_add_symbol
=
6483 symbol_new ("L0\001", now_seg
,
6484 (valueT
) frag_now_fix (), frag_now
);
6485 offset_expr
.X_add_number
= 0;
6487 /* Put the floating point number into the section. */
6488 p
= frag_more ((int) length
);
6489 memcpy (p
, temp
, length
);
6491 /* Switch back to the original section. */
6492 subseg_set (seg
, subseg
);
6497 case 'i': /* 16 bit unsigned immediate */
6498 case 'j': /* 16 bit signed immediate */
6499 imm_reloc
= BFD_RELOC_LO16
;
6500 c
= my_getSmallExpression (&imm_expr
, s
);
6505 if (imm_expr
.X_op
== O_constant
)
6506 imm_expr
.X_add_number
=
6507 (imm_expr
.X_add_number
>> 16) & 0xffff;
6510 imm_reloc
= BFD_RELOC_HI16_S
;
6511 imm_unmatched_hi
= true;
6514 imm_reloc
= BFD_RELOC_HI16
;
6519 if ((c
== '\0' && imm_expr
.X_op
!= O_constant
)
6520 || ((imm_expr
.X_add_number
< 0
6521 || imm_expr
.X_add_number
>= 0x10000)
6522 && imm_expr
.X_op
== O_constant
))
6524 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
6525 !strcmp (insn
->name
, insn
[1].name
))
6527 if (imm_expr
.X_op
!= O_constant
6528 && imm_expr
.X_op
!= O_big
)
6529 insn_error
= "absolute expression required";
6531 as_bad ("16 bit expression not in range 0..65535");
6539 /* The upper bound should be 0x8000, but
6540 unfortunately the MIPS assembler accepts numbers
6541 from 0x8000 to 0xffff and sign extends them, and
6542 we want to be compatible. We only permit this
6543 extended range for an instruction which does not
6544 provide any further alternates, since those
6545 alternates may handle other cases. People should
6546 use the numbers they mean, rather than relying on
6547 a mysterious sign extension. */
6548 more
= (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
6549 strcmp (insn
->name
, insn
[1].name
) == 0);
6554 if ((c
== '\0' && imm_expr
.X_op
!= O_constant
)
6555 || ((imm_expr
.X_add_number
< -0x8000
6556 || imm_expr
.X_add_number
>= max
)
6557 && imm_expr
.X_op
== O_constant
)
6559 && imm_expr
.X_add_number
< 0
6561 && imm_expr
.X_unsigned
6562 && sizeof (imm_expr
.X_add_number
) <= 4))
6566 if (imm_expr
.X_op
!= O_constant
6567 && imm_expr
.X_op
!= O_big
)
6568 insn_error
= "absolute expression required";
6570 as_bad ("16 bit expression not in range -32768..32767");
6576 case 'o': /* 16 bit offset */
6577 c
= my_getSmallExpression (&offset_expr
, s
);
6579 /* If this value won't fit into a 16 bit offset, then go
6580 find a macro that will generate the 32 bit offset
6581 code pattern. As a special hack, we accept the
6582 difference of two local symbols as a constant. This
6583 is required to suppose embedded PIC switches, which
6584 use an instruction which looks like
6585 lw $4,$L12-$LS12($4)
6586 The problem with handling this in a more general
6587 fashion is that the macro function doesn't expect to
6588 see anything which can be handled in a single
6589 constant instruction. */
6591 && (offset_expr
.X_op
!= O_constant
6592 || offset_expr
.X_add_number
>= 0x8000
6593 || offset_expr
.X_add_number
< -0x8000)
6594 && (mips_pic
!= EMBEDDED_PIC
6595 || offset_expr
.X_op
!= O_subtract
6596 || now_seg
!= text_section
6597 || (S_GET_SEGMENT (offset_expr
.X_op_symbol
)
6601 offset_reloc
= BFD_RELOC_LO16
;
6602 if (c
== 'h' || c
== 'H')
6604 assert (offset_expr
.X_op
== O_constant
);
6605 offset_expr
.X_add_number
=
6606 (offset_expr
.X_add_number
>> 16) & 0xffff;
6611 case 'p': /* pc relative offset */
6612 offset_reloc
= BFD_RELOC_16_PCREL_S2
;
6613 my_getExpression (&offset_expr
, s
);
6617 case 'u': /* upper 16 bits */
6618 c
= my_getSmallExpression (&imm_expr
, s
);
6619 if (imm_expr
.X_op
== O_constant
6620 && (imm_expr
.X_add_number
< 0
6621 || imm_expr
.X_add_number
>= 0x10000))
6622 as_bad ("lui expression not in range 0..65535");
6623 imm_reloc
= BFD_RELOC_LO16
;
6628 if (imm_expr
.X_op
== O_constant
)
6629 imm_expr
.X_add_number
=
6630 (imm_expr
.X_add_number
>> 16) & 0xffff;
6633 imm_reloc
= BFD_RELOC_HI16_S
;
6634 imm_unmatched_hi
= true;
6637 imm_reloc
= BFD_RELOC_HI16
;
6643 case 'a': /* 26 bit address */
6644 my_getExpression (&offset_expr
, s
);
6646 offset_reloc
= BFD_RELOC_MIPS_JMP
;
6649 case 'N': /* 3 bit branch condition code */
6650 case 'M': /* 3 bit compare condition code */
6651 if (strncmp (s
, "$fcc", 4) != 0)
6661 while (isdigit (*s
));
6663 as_bad ("invalid condition code register $fcc%d", regno
);
6665 ip
->insn_opcode
|= regno
<< OP_SH_BCC
;
6667 ip
->insn_opcode
|= regno
<< OP_SH_CCC
;
6671 fprintf (stderr
, "bad char = '%c'\n", *args
);
6676 /* Args don't match. */
6677 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
6678 !strcmp (insn
->name
, insn
[1].name
))
6684 insn_error
= "illegal operands";
6689 /* This routine assembles an instruction into its binary format when
6690 assembling for the mips16. As a side effect, it sets one of the
6691 global variables imm_reloc or offset_reloc to the type of
6692 relocation to do if one of the operands is an address expression.
6693 It also sets mips16_small and mips16_ext if the user explicitly
6694 requested a small or extended instruction. */
6699 struct mips_cl_insn
*ip
;
6703 struct mips_opcode
*insn
;
6706 unsigned int lastregno
= 0;
6711 mips16_small
= false;
6714 for (s
= str
; islower (*s
); ++s
)
6726 if (s
[1] == 't' && s
[2] == ' ')
6729 mips16_small
= true;
6733 else if (s
[1] == 'e' && s
[2] == ' ')
6742 insn_error
= "unknown opcode";
6746 if (! mips16_autoextend
&& ! mips16_ext
)
6747 mips16_small
= true;
6749 if ((insn
= (struct mips_opcode
*) hash_find (mips16_op_hash
, str
)) == NULL
)
6751 insn_error
= "unrecognized opcode";
6758 assert (strcmp (insn
->name
, str
) == 0);
6761 ip
->insn_opcode
= insn
->match
;
6762 ip
->use_extend
= false;
6763 imm_expr
.X_op
= O_absent
;
6764 imm_reloc
= BFD_RELOC_UNUSED
;
6765 offset_expr
.X_op
= O_absent
;
6766 offset_reloc
= BFD_RELOC_UNUSED
;
6767 for (args
= insn
->args
; 1; ++args
)
6774 /* In this switch statement we call break if we did not find
6775 a match, continue if we did find a match, or return if we
6784 /* Stuff the immediate value in now, if we can. */
6785 if (imm_expr
.X_op
== O_constant
6786 && imm_reloc
> BFD_RELOC_UNUSED
6787 && insn
->pinfo
!= INSN_MACRO
)
6789 mips16_immed ((char *) NULL
, 0,
6790 imm_reloc
- BFD_RELOC_UNUSED
,
6791 imm_expr
.X_add_number
, true, mips16_small
,
6792 mips16_ext
, &ip
->insn_opcode
,
6793 &ip
->use_extend
, &ip
->extend
);
6794 imm_expr
.X_op
= O_absent
;
6795 imm_reloc
= BFD_RELOC_UNUSED
;
6809 ip
->insn_opcode
|= lastregno
<< MIPS16OP_SH_RX
;
6812 ip
->insn_opcode
|= lastregno
<< MIPS16OP_SH_RY
;
6828 ip
->insn_opcode
|= lastregno
<< MIPS16OP_SH_RX
;
6830 ip
->insn_opcode
|= lastregno
<< MIPS16OP_SH_RY
;
6857 while (isdigit (*s
));
6860 as_bad ("invalid register number (%d)", regno
);
6866 if (s
[1] == 'f' && s
[2] == 'p')
6871 else if (s
[1] == 's' && s
[2] == 'p')
6876 else if (s
[1] == 'g' && s
[2] == 'p')
6881 else if (s
[1] == 'a' && s
[2] == 't')
6886 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '0')
6891 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '1')
6904 if (c
== 'v' || c
== 'w')
6906 regno
= mips16_to_32_reg_map
[lastregno
];
6920 regno
= mips32_to_16_reg_map
[regno
];
6925 regno
= ILLEGAL_REG
;
6930 regno
= ILLEGAL_REG
;
6935 regno
= ILLEGAL_REG
;
6940 if (regno
== AT
&& ! mips_noat
)
6941 as_warn ("used $at without \".set noat\"");
6948 if (regno
== ILLEGAL_REG
)
6955 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_RX
;
6959 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_RY
;
6962 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_RZ
;
6965 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_MOVE32Z
;
6971 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_REGR32
;
6974 regno
= ((regno
& 7) << 2) | ((regno
& 0x18) >> 3);
6975 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_REG32R
;
6985 if (strncmp (s
, "$pc", 3) == 0)
7008 if (s
[0] == '$' && isdigit (s
[1]))
7010 /* Looks like a register name. */
7013 my_getExpression (&imm_expr
, s
);
7014 /* We need to relax this instruction. */
7015 imm_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
7024 /* We use offset_reloc rather than imm_reloc for the PC
7025 relative operands. This lets macros with both
7026 immediate and address operands work correctly. */
7027 if (s
[0] == '$' && isdigit (s
[1]))
7029 /* Looks like a register name. */
7032 my_getExpression (&offset_expr
, s
);
7033 /* We need to relax this instruction. */
7034 offset_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
7038 case '6': /* break code */
7039 my_getExpression (&imm_expr
, s
);
7040 check_absolute_expr (ip
, &imm_expr
);
7041 if ((unsigned long) imm_expr
.X_add_number
> 63)
7043 as_warn ("Invalid value for `%s' (%lu)",
7045 (unsigned long) imm_expr
.X_add_number
);
7046 imm_expr
.X_add_number
&= 0x3f;
7048 ip
->insn_opcode
|= imm_expr
.X_add_number
<< MIPS16OP_SH_IMM6
;
7049 imm_expr
.X_op
= O_absent
;
7053 case 'a': /* 26 bit address */
7054 my_getExpression (&offset_expr
, s
);
7056 offset_reloc
= BFD_RELOC_MIPS16_JMP
;
7057 ip
->insn_opcode
<<= 16;
7060 case 'l': /* register list for entry macro */
7061 case 'L': /* register list for exit macro */
7073 while (*s
== ' ' || *s
== ',')
7077 as_bad ("can't parse register list");
7082 while (isdigit (*s
))
7099 while (isdigit (*s
))
7106 if (reg1
== 4 && reg2
>= 4 && reg2
<= 7 && c
!= 'L')
7107 mask
|= (reg2
- 3) << 3;
7108 else if (reg1
== 16 && reg2
>= 16 && reg2
<= 17)
7109 mask
|= (reg2
- 15) << 1;
7110 else if (reg1
== 31 && reg2
== 31)
7113 as_bad ("invalid register list");
7115 ip
->insn_opcode
|= mask
<< MIPS16OP_SH_IMM6
;
7125 /* Args don't match. */
7126 if (insn
+ 1 < &mips16_opcodes
[bfd_mips16_num_opcodes
] &&
7127 strcmp (insn
->name
, insn
[1].name
) == 0)
7134 insn_error
= "illegal operands";
7140 /* This structure holds information we know about a mips16 immediate
7143 struct mips16_immed_operand
7145 /* The type code used in the argument string in the opcode table. */
7147 /* The number of bits in the short form of the opcode. */
7149 /* The number of bits in the extended form of the opcode. */
7151 /* The amount by which the short form is shifted when it is used;
7152 for example, the sw instruction has a shift count of 2. */
7154 /* The amount by which the short form is shifted when it is stored
7155 into the instruction code. */
7157 /* Non-zero if the short form is unsigned. */
7159 /* Non-zero if the extended form is unsigned. */
7161 /* Non-zero if the value is PC relative. */
7165 /* The mips16 immediate operand types. */
7167 static const struct mips16_immed_operand mips16_immed_operands
[] =
7169 { '<', 3, 5, 0, MIPS16OP_SH_RZ
, 1, 1, 0 },
7170 { '>', 3, 5, 0, MIPS16OP_SH_RX
, 1, 1, 0 },
7171 { '[', 3, 6, 0, MIPS16OP_SH_RZ
, 1, 1, 0 },
7172 { ']', 3, 6, 0, MIPS16OP_SH_RX
, 1, 1, 0 },
7173 { '4', 4, 15, 0, MIPS16OP_SH_IMM4
, 0, 0, 0 },
7174 { '5', 5, 16, 0, MIPS16OP_SH_IMM5
, 1, 0, 0 },
7175 { 'H', 5, 16, 1, MIPS16OP_SH_IMM5
, 1, 0, 0 },
7176 { 'W', 5, 16, 2, MIPS16OP_SH_IMM5
, 1, 0, 0 },
7177 { 'D', 5, 16, 3, MIPS16OP_SH_IMM5
, 1, 0, 0 },
7178 { 'j', 5, 16, 0, MIPS16OP_SH_IMM5
, 0, 0, 0 },
7179 { '8', 8, 16, 0, MIPS16OP_SH_IMM8
, 1, 0, 0 },
7180 { 'V', 8, 16, 2, MIPS16OP_SH_IMM8
, 1, 0, 0 },
7181 { 'C', 8, 16, 3, MIPS16OP_SH_IMM8
, 1, 0, 0 },
7182 { 'U', 8, 16, 0, MIPS16OP_SH_IMM8
, 1, 1, 0 },
7183 { 'k', 8, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 0 },
7184 { 'K', 8, 16, 3, MIPS16OP_SH_IMM8
, 0, 0, 0 },
7185 { 'p', 8, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 1 },
7186 { 'q', 11, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 1 },
7187 { 'A', 8, 16, 2, MIPS16OP_SH_IMM8
, 1, 0, 1 },
7188 { 'B', 5, 16, 3, MIPS16OP_SH_IMM5
, 1, 0, 1 },
7189 { 'E', 5, 16, 2, MIPS16OP_SH_IMM5
, 1, 0, 1 }
7192 #define MIPS16_NUM_IMMED \
7193 (sizeof mips16_immed_operands / sizeof mips16_immed_operands[0])
7195 /* Handle a mips16 instruction with an immediate value. This or's the
7196 small immediate value into *INSN. It sets *USE_EXTEND to indicate
7197 whether an extended value is needed; if one is needed, it sets
7198 *EXTEND to the value. The argument type is TYPE. The value is VAL.
7199 If SMALL is true, an unextended opcode was explicitly requested.
7200 If EXT is true, an extended opcode was explicitly requested. If
7201 WARN is true, warn if EXT does not match reality. */
7204 mips16_immed (file
, line
, type
, val
, warn
, small
, ext
, insn
, use_extend
,
7213 unsigned long *insn
;
7214 boolean
*use_extend
;
7215 unsigned short *extend
;
7217 register const struct mips16_immed_operand
*op
;
7218 int mintiny
, maxtiny
;
7221 op
= mips16_immed_operands
;
7222 while (op
->type
!= type
)
7225 assert (op
< mips16_immed_operands
+ MIPS16_NUM_IMMED
);
7230 if (type
== '<' || type
== '>' || type
== '[' || type
== ']')
7233 maxtiny
= 1 << op
->nbits
;
7238 maxtiny
= (1 << op
->nbits
) - 1;
7243 mintiny
= - (1 << (op
->nbits
- 1));
7244 maxtiny
= (1 << (op
->nbits
- 1)) - 1;
7247 /* Branch offsets have an implicit 0 in the lowest bit. */
7248 if (type
== 'p' || type
== 'q')
7251 as_bad_where (file
, line
, "branch to odd address");
7255 if ((val
& ((1 << op
->shift
) - 1)) != 0
7256 || val
< (mintiny
<< op
->shift
)
7257 || val
> (maxtiny
<< op
->shift
))
7262 if (warn
&& ext
&& ! needext
)
7263 as_warn_where (file
, line
, "extended operand requested but not required");
7264 if (small
&& needext
)
7265 as_bad_where (file
, line
, "invalid unextended operand value");
7267 if (small
|| (! ext
&& ! needext
))
7271 *use_extend
= false;
7272 insnval
= ((val
>> op
->shift
) & ((1 << op
->nbits
) - 1));
7273 insnval
<<= op
->op_shift
;
7278 long minext
, maxext
;
7284 maxext
= (1 << op
->extbits
) - 1;
7288 minext
= - (1 << (op
->extbits
- 1));
7289 maxext
= (1 << (op
->extbits
- 1)) - 1;
7291 if (val
< minext
|| val
> maxext
)
7292 as_bad_where (file
, line
,
7293 "operand value out of range for instruction");
7296 if (op
->extbits
== 16)
7298 extval
= ((val
>> 11) & 0x1f) | (val
& 0x7e0);
7301 else if (op
->extbits
== 15)
7303 extval
= ((val
>> 11) & 0xf) | (val
& 0x7f0);
7308 extval
= ((val
& 0x1f) << 6) | (val
& 0x20);
7312 *extend
= (unsigned short) extval
;
7321 my_getSmallExpression (ep
, str
)
7332 ((str
[1] == 'h' && str
[2] == 'i')
7333 || (str
[1] == 'H' && str
[2] == 'I')
7334 || (str
[1] == 'l' && str
[2] == 'o'))
7346 * A small expression may be followed by a base register.
7347 * Scan to the end of this operand, and then back over a possible
7348 * base register. Then scan the small expression up to that
7349 * point. (Based on code in sparc.c...)
7351 for (sp
= str
; *sp
&& *sp
!= ','; sp
++)
7353 if (sp
- 4 >= str
&& sp
[-1] == RP
)
7355 if (isdigit (sp
[-2]))
7357 for (sp
-= 3; sp
>= str
&& isdigit (*sp
); sp
--)
7359 if (*sp
== '$' && sp
> str
&& sp
[-1] == LP
)
7365 else if (sp
- 5 >= str
7368 && ((sp
[-3] == 'f' && sp
[-2] == 'p')
7369 || (sp
[-3] == 's' && sp
[-2] == 'p')
7370 || (sp
[-3] == 'g' && sp
[-2] == 'p')
7371 || (sp
[-3] == 'a' && sp
[-2] == 't')))
7377 /* no expression means zero offset */
7380 /* %xx(reg) is an error */
7381 ep
->X_op
= O_absent
;
7386 ep
->X_op
= O_constant
;
7389 ep
->X_add_symbol
= NULL
;
7390 ep
->X_op_symbol
= NULL
;
7391 ep
->X_add_number
= 0;
7396 my_getExpression (ep
, str
);
7403 my_getExpression (ep
, str
);
7404 return c
; /* => %hi or %lo encountered */
7408 my_getExpression (ep
, str
)
7414 save_in
= input_line_pointer
;
7415 input_line_pointer
= str
;
7417 expr_end
= input_line_pointer
;
7418 input_line_pointer
= save_in
;
7421 /* Turn a string in input_line_pointer into a floating point constant
7422 of type type, and store the appropriate bytes in *litP. The number
7423 of LITTLENUMS emitted is stored in *sizeP . An error message is
7424 returned, or NULL on OK. */
7427 md_atof (type
, litP
, sizeP
)
7433 LITTLENUM_TYPE words
[4];
7449 return "bad call to md_atof";
7452 t
= atof_ieee (input_line_pointer
, type
, words
);
7454 input_line_pointer
= t
;
7458 if (byte_order
== LITTLE_ENDIAN
)
7460 for (i
= prec
- 1; i
>= 0; i
--)
7462 md_number_to_chars (litP
, (valueT
) words
[i
], 2);
7468 for (i
= 0; i
< prec
; i
++)
7470 md_number_to_chars (litP
, (valueT
) words
[i
], 2);
7479 md_number_to_chars (buf
, val
, n
)
7487 number_to_chars_littleendian (buf
, val
, n
);
7491 number_to_chars_bigendian (buf
, val
, n
);
7499 CONST
char *md_shortopts
= "O::g::G:";
7501 struct option md_longopts
[] = {
7502 #define OPTION_MIPS1 (OPTION_MD_BASE + 1)
7503 {"mips0", no_argument
, NULL
, OPTION_MIPS1
},
7504 {"mips1", no_argument
, NULL
, OPTION_MIPS1
},
7505 #define OPTION_MIPS2 (OPTION_MD_BASE + 2)
7506 {"mips2", no_argument
, NULL
, OPTION_MIPS2
},
7507 #define OPTION_MIPS3 (OPTION_MD_BASE + 3)
7508 {"mips3", no_argument
, NULL
, OPTION_MIPS3
},
7509 #define OPTION_MIPS4 (OPTION_MD_BASE + 4)
7510 {"mips4", no_argument
, NULL
, OPTION_MIPS4
},
7511 #define OPTION_MCPU (OPTION_MD_BASE + 5)
7512 {"mcpu", required_argument
, NULL
, OPTION_MCPU
},
7513 #define OPTION_MEMBEDDED_PIC (OPTION_MD_BASE + 6)
7514 {"membedded-pic", no_argument
, NULL
, OPTION_MEMBEDDED_PIC
},
7515 #define OPTION_TRAP (OPTION_MD_BASE + 9)
7516 {"trap", no_argument
, NULL
, OPTION_TRAP
},
7517 {"no-break", no_argument
, NULL
, OPTION_TRAP
},
7518 #define OPTION_BREAK (OPTION_MD_BASE + 10)
7519 {"break", no_argument
, NULL
, OPTION_BREAK
},
7520 {"no-trap", no_argument
, NULL
, OPTION_BREAK
},
7521 #define OPTION_EB (OPTION_MD_BASE + 11)
7522 {"EB", no_argument
, NULL
, OPTION_EB
},
7523 #define OPTION_EL (OPTION_MD_BASE + 12)
7524 {"EL", no_argument
, NULL
, OPTION_EL
},
7525 #define OPTION_M4650 (OPTION_MD_BASE + 13)
7526 {"m4650", no_argument
, NULL
, OPTION_M4650
},
7527 #define OPTION_NO_M4650 (OPTION_MD_BASE + 14)
7528 {"no-m4650", no_argument
, NULL
, OPTION_NO_M4650
},
7529 #define OPTION_M4010 (OPTION_MD_BASE + 15)
7530 {"m4010", no_argument
, NULL
, OPTION_M4010
},
7531 #define OPTION_NO_M4010 (OPTION_MD_BASE + 16)
7532 {"no-m4010", no_argument
, NULL
, OPTION_NO_M4010
},
7533 #define OPTION_M4100 (OPTION_MD_BASE + 17)
7534 {"m4100", no_argument
, NULL
, OPTION_M4100
},
7535 #define OPTION_NO_M4100 (OPTION_MD_BASE + 18)
7536 {"no-m4100", no_argument
, NULL
, OPTION_NO_M4100
},
7537 #define OPTION_MIPS16 (OPTION_MD_BASE + 22)
7538 {"mips16", no_argument
, NULL
, OPTION_MIPS16
},
7539 #define OPTION_NO_MIPS16 (OPTION_MD_BASE + 23)
7540 {"no-mips16", no_argument
, NULL
, OPTION_NO_MIPS16
},
7542 #define OPTION_CALL_SHARED (OPTION_MD_BASE + 7)
7543 #define OPTION_NON_SHARED (OPTION_MD_BASE + 8)
7544 #define OPTION_XGOT (OPTION_MD_BASE + 19)
7545 #define OPTION_32 (OPTION_MD_BASE + 20)
7546 #define OPTION_64 (OPTION_MD_BASE + 21)
7548 {"KPIC", no_argument
, NULL
, OPTION_CALL_SHARED
},
7549 {"xgot", no_argument
, NULL
, OPTION_XGOT
},
7550 {"call_shared", no_argument
, NULL
, OPTION_CALL_SHARED
},
7551 {"non_shared", no_argument
, NULL
, OPTION_NON_SHARED
},
7552 {"32", no_argument
, NULL
, OPTION_32
},
7553 {"64", no_argument
, NULL
, OPTION_64
},
7556 {NULL
, no_argument
, NULL
, 0}
7558 size_t md_longopts_size
= sizeof(md_longopts
);
7561 md_parse_option (c
, arg
)
7576 target_big_endian
= 1;
7580 target_big_endian
= 0;
7584 if (arg
&& arg
[1] == '0')
7594 mips_debug
= atoi (arg
);
7595 /* When the MIPS assembler sees -g or -g2, it does not do
7596 optimizations which limit full symbolic debugging. We take
7597 that to be equivalent to -O0. */
7598 if (mips_debug
== 2)
7630 /* Identify the processor type */
7632 if (strcmp (p
, "default") == 0
7633 || strcmp (p
, "DEFAULT") == 0)
7639 /* We need to cope with the various "vr" prefixes for the 4300
7641 if (*p
== 'v' || *p
== 'V')
7647 if (*p
== 'r' || *p
== 'R')
7654 if (strcmp (p
, "10000") == 0
7655 || strcmp (p
, "10k") == 0
7656 || strcmp (p
, "10K") == 0)
7661 if (strcmp (p
, "2000") == 0
7662 || strcmp (p
, "2k") == 0
7663 || strcmp (p
, "2K") == 0)
7668 if (strcmp (p
, "3000") == 0
7669 || strcmp (p
, "3k") == 0
7670 || strcmp (p
, "3K") == 0)
7675 if (strcmp (p
, "4000") == 0
7676 || strcmp (p
, "4k") == 0
7677 || strcmp (p
, "4K") == 0)
7679 else if (strcmp (p
, "4100") == 0)
7685 else if (strcmp (p
, "4300") == 0)
7687 else if (strcmp (p
, "4400") == 0)
7689 else if (strcmp (p
, "4600") == 0)
7691 else if (strcmp (p
, "4650") == 0)
7697 else if (strcmp (p
, "4010") == 0)
7706 if (strcmp (p
, "5000") == 0
7707 || strcmp (p
, "5k") == 0
7708 || strcmp (p
, "5K") == 0)
7713 if (strcmp (p
, "6000") == 0
7714 || strcmp (p
, "6k") == 0
7715 || strcmp (p
, "6K") == 0)
7720 if (strcmp (p
, "8000") == 0
7721 || strcmp (p
, "8k") == 0
7722 || strcmp (p
, "8K") == 0)
7727 if (strcmp (p
, "orion") == 0)
7732 if (sv
&& mips_cpu
!= 4300 && mips_cpu
!= 4100 && mips_cpu
!= 5000)
7734 as_bad ("ignoring invalid leading 'v' in -mcpu=%s switch", arg
);
7740 as_bad ("invalid architecture -mcpu=%s", arg
);
7751 case OPTION_NO_M4650
:
7759 case OPTION_NO_M4010
:
7767 case OPTION_NO_M4100
:
7773 mips_no_prev_insn ();
7776 case OPTION_NO_MIPS16
:
7778 mips_no_prev_insn ();
7781 case OPTION_MEMBEDDED_PIC
:
7782 mips_pic
= EMBEDDED_PIC
;
7783 if (USE_GLOBAL_POINTER_OPT
&& g_switch_seen
)
7785 as_bad ("-G may not be used with embedded PIC code");
7788 g_switch_value
= 0x7fffffff;
7791 /* When generating ELF code, we permit -KPIC and -call_shared to
7792 select SVR4_PIC, and -non_shared to select no PIC. This is
7793 intended to be compatible with Irix 5. */
7794 case OPTION_CALL_SHARED
:
7795 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
7797 as_bad ("-call_shared is supported only for ELF format");
7800 mips_pic
= SVR4_PIC
;
7801 if (g_switch_seen
&& g_switch_value
!= 0)
7803 as_bad ("-G may not be used with SVR4 PIC code");
7809 case OPTION_NON_SHARED
:
7810 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
7812 as_bad ("-non_shared is supported only for ELF format");
7818 /* The -xgot option tells the assembler to use 32 offsets when
7819 accessing the got in SVR4_PIC mode. It is for Irix
7826 if (! USE_GLOBAL_POINTER_OPT
)
7828 as_bad ("-G is not supported for this configuration");
7831 else if (mips_pic
== SVR4_PIC
|| mips_pic
== EMBEDDED_PIC
)
7833 as_bad ("-G may not be used with SVR4 or embedded PIC code");
7837 g_switch_value
= atoi (arg
);
7841 /* The -32 and -64 options tell the assembler to output the 32
7842 bit or the 64 bit MIPS ELF format. */
7849 const char **list
, **l
;
7851 list
= bfd_target_list ();
7852 for (l
= list
; *l
!= NULL
; l
++)
7853 if (strcmp (*l
, "elf64-bigmips") == 0
7854 || strcmp (*l
, "elf64-littlemips") == 0)
7857 as_fatal ("No compiled in support for 64 bit object file format");
7871 md_show_usage (stream
)
7876 -membedded-pic generate embedded position independent code\n\
7877 -EB generate big endian output\n\
7878 -EL generate little endian output\n\
7879 -g, -g2 do not remove uneeded NOPs or swap branches\n\
7880 -G NUM allow referencing objects up to NUM bytes\n\
7881 implicitly with the gp register [default 8]\n");
7883 -mips1, -mcpu=r{2,3}000 generate code for r2000 and r3000\n\
7884 -mips2, -mcpu=r6000 generate code for r6000\n\
7885 -mips3, -mcpu=r4000 generate code for r4000\n\
7886 -mips4, -mcpu=r8000 generate code for r8000\n\
7887 -mcpu=vr4300 generate code for vr4300\n\
7888 -mcpu=vr4100 generate code for vr4100\n\
7889 -m4650 permit R4650 instructions\n\
7890 -no-m4650 do not permit R4650 instructions\n\
7891 -m4010 permit R4010 instructions\n\
7892 -no-m4010 do not permit R4010 instructions\n\
7893 -m4100 permit VR4100 instructions\n\
7894 -no-m4100 do not permit VR4100 instructions\n");
7896 -mips16 generate mips16 instructions\n\
7897 -no-mips16 do not generate mips16 instructions\n");
7899 -O0 remove unneeded NOPs, do not swap branches\n\
7900 -O remove unneeded NOPs and swap branches\n\
7901 --trap, --no-break trap exception on div by 0 and mult overflow\n\
7902 --break, --no-trap break exception on div by 0 and mult overflow\n");
7905 -KPIC, -call_shared generate SVR4 position independent code\n\
7906 -non_shared do not generate position independent code\n\
7907 -xgot assume a 32 bit GOT\n\
7908 -32 create 32 bit object file (default)\n\
7909 -64 create 64 bit object file\n");
7914 mips_init_after_args ()
7916 if (target_big_endian
)
7917 byte_order
= BIG_ENDIAN
;
7919 byte_order
= LITTLE_ENDIAN
;
7923 md_pcrel_from (fixP
)
7926 if (OUTPUT_FLAVOR
!= bfd_target_aout_flavour
7927 && fixP
->fx_addsy
!= (symbolS
*) NULL
7928 && ! S_IS_DEFINED (fixP
->fx_addsy
))
7930 /* This makes a branch to an undefined symbol be a branch to the
7931 current location. */
7935 /* return the address of the delay slot */
7936 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
7939 /* This is called by emit_expr via TC_CONS_FIX_NEW when creating a
7940 reloc for a cons. We could use the definition there, except that
7941 we want to handle 64 bit relocs specially. */
7944 cons_fix_new_mips (frag
, where
, nbytes
, exp
)
7947 unsigned int nbytes
;
7951 /* If we are assembling in 32 bit mode, turn an 8 byte reloc into a
7953 if (nbytes
== 8 && ! mips_64
)
7955 if (byte_order
== BIG_ENDIAN
)
7961 if (nbytes
!= 2 && nbytes
!= 4 && nbytes
!= 8)
7962 as_bad ("Unsupported reloc size %d", nbytes
);
7964 fix_new_exp (frag_now
, where
, (int) nbytes
, exp
, 0,
7967 : (nbytes
== 4 ? BFD_RELOC_32
: BFD_RELOC_64
)));
7970 /* Sort any unmatched HI16_S relocs so that they immediately precede
7971 the corresponding LO reloc. This is called before md_apply_fix and
7972 tc_gen_reloc. Unmatched HI16_S relocs can only be generated by
7973 explicit use of the %hi modifier. */
7978 struct mips_hi_fixup
*l
;
7980 for (l
= mips_hi_fixup_list
; l
!= NULL
; l
= l
->next
)
7982 segment_info_type
*seginfo
;
7985 assert (l
->fixp
->fx_r_type
== BFD_RELOC_HI16_S
);
7987 /* Check quickly whether the next fixup happens to be a matching
7989 if (l
->fixp
->fx_next
!= NULL
7990 && l
->fixp
->fx_next
->fx_r_type
== BFD_RELOC_LO16
7991 && l
->fixp
->fx_addsy
== l
->fixp
->fx_next
->fx_addsy
7992 && l
->fixp
->fx_offset
== l
->fixp
->fx_next
->fx_offset
)
7995 /* Look through the fixups for this segment for a matching %lo.
7996 When we find one, move the %hi just in front of it. We do
7997 this in two passes. In the first pass, we try to find a
7998 unique %lo. In the second pass, we permit multiple %hi
7999 relocs for a single %lo (this is a GNU extension). */
8000 seginfo
= seg_info (l
->seg
);
8001 for (pass
= 0; pass
< 2; pass
++)
8006 for (f
= seginfo
->fix_root
; f
!= NULL
; f
= f
->fx_next
)
8008 /* Check whether this is a %lo fixup which matches l->fixp. */
8009 if (f
->fx_r_type
== BFD_RELOC_LO16
8010 && f
->fx_addsy
== l
->fixp
->fx_addsy
8011 && f
->fx_offset
== l
->fixp
->fx_offset
8014 || prev
->fx_r_type
!= BFD_RELOC_HI16_S
8015 || prev
->fx_addsy
!= f
->fx_addsy
8016 || prev
->fx_offset
!= f
->fx_offset
))
8020 /* Move l->fixp before f. */
8021 for (pf
= &seginfo
->fix_root
;
8023 pf
= &(*pf
)->fx_next
)
8024 assert (*pf
!= NULL
);
8026 *pf
= l
->fixp
->fx_next
;
8028 l
->fixp
->fx_next
= f
;
8030 seginfo
->fix_root
= l
->fixp
;
8032 prev
->fx_next
= l
->fixp
;
8044 as_warn_where (l
->fixp
->fx_file
, l
->fixp
->fx_line
,
8045 "Unmatched %%hi reloc");
8050 /* When generating embedded PIC code we need to use a special
8051 relocation to represent the difference of two symbols in the .text
8052 section (switch tables use a difference of this sort). See
8053 include/coff/mips.h for details. This macro checks whether this
8054 fixup requires the special reloc. */
8055 #define SWITCH_TABLE(fixp) \
8056 ((fixp)->fx_r_type == BFD_RELOC_32 \
8057 && (fixp)->fx_addsy != NULL \
8058 && (fixp)->fx_subsy != NULL \
8059 && S_GET_SEGMENT ((fixp)->fx_addsy) == text_section \
8060 && S_GET_SEGMENT ((fixp)->fx_subsy) == text_section)
8062 /* When generating embedded PIC code we must keep all PC relative
8063 relocations, in case the linker has to relax a call. We also need
8064 to keep relocations for switch table entries. */
8068 mips_force_relocation (fixp
)
8071 return (mips_pic
== EMBEDDED_PIC
8073 || SWITCH_TABLE (fixp
)
8074 || fixp
->fx_r_type
== BFD_RELOC_PCREL_HI16_S
8075 || fixp
->fx_r_type
== BFD_RELOC_PCREL_LO16
));
8078 /* Apply a fixup to the object file. */
8081 md_apply_fix (fixP
, valueP
)
8088 assert (fixP
->fx_size
== 4
8089 || fixP
->fx_r_type
== BFD_RELOC_16
8090 || fixP
->fx_r_type
== BFD_RELOC_64
);
8093 fixP
->fx_addnumber
= value
; /* Remember value for tc_gen_reloc */
8095 if (fixP
->fx_addsy
== NULL
&& ! fixP
->fx_pcrel
)
8098 switch (fixP
->fx_r_type
)
8100 case BFD_RELOC_MIPS_JMP
:
8101 case BFD_RELOC_HI16
:
8102 case BFD_RELOC_HI16_S
:
8103 case BFD_RELOC_MIPS_GPREL
:
8104 case BFD_RELOC_MIPS_LITERAL
:
8105 case BFD_RELOC_MIPS_CALL16
:
8106 case BFD_RELOC_MIPS_GOT16
:
8107 case BFD_RELOC_MIPS_GPREL32
:
8108 case BFD_RELOC_MIPS_GOT_HI16
:
8109 case BFD_RELOC_MIPS_GOT_LO16
:
8110 case BFD_RELOC_MIPS_CALL_HI16
:
8111 case BFD_RELOC_MIPS_CALL_LO16
:
8113 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
8114 "Invalid PC relative reloc");
8115 /* Nothing needed to do. The value comes from the reloc entry */
8118 case BFD_RELOC_MIPS16_JMP
:
8119 /* We currently always generate a reloc against a symbol, which
8120 means that we don't want an addend even if the symbol is
8122 fixP
->fx_addnumber
= 0;
8125 case BFD_RELOC_PCREL_HI16_S
:
8126 /* The addend for this is tricky if it is internal, so we just
8127 do everything here rather than in bfd_perform_relocation. */
8128 if ((fixP
->fx_addsy
->bsym
->flags
& BSF_SECTION_SYM
) == 0)
8130 /* For an external symbol adjust by the address to make it
8131 pcrel_offset. We use the address of the RELLO reloc
8132 which follows this one. */
8133 value
+= (fixP
->fx_next
->fx_frag
->fr_address
8134 + fixP
->fx_next
->fx_where
);
8139 buf
= (unsigned char *) fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
8140 if (byte_order
== BIG_ENDIAN
)
8142 md_number_to_chars (buf
, value
, 2);
8145 case BFD_RELOC_PCREL_LO16
:
8146 /* The addend for this is tricky if it is internal, so we just
8147 do everything here rather than in bfd_perform_relocation. */
8148 if ((fixP
->fx_addsy
->bsym
->flags
& BSF_SECTION_SYM
) == 0)
8149 value
+= fixP
->fx_frag
->fr_address
+ fixP
->fx_where
;
8150 buf
= (unsigned char *) fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
8151 if (byte_order
== BIG_ENDIAN
)
8153 md_number_to_chars (buf
, value
, 2);
8157 /* This is handled like BFD_RELOC_32, but we output a sign
8158 extended value if we are only 32 bits. */
8160 || (mips_pic
== EMBEDDED_PIC
&& SWITCH_TABLE (fixP
)))
8162 if (8 <= sizeof (valueT
))
8163 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
,
8170 w1
= w2
= fixP
->fx_where
;
8171 if (byte_order
== BIG_ENDIAN
)
8175 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ w1
, value
, 4);
8176 if ((value
& 0x80000000) != 0)
8180 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ w2
, hiv
, 4);
8186 /* If we are deleting this reloc entry, we must fill in the
8187 value now. This can happen if we have a .word which is not
8188 resolved when it appears but is later defined. We also need
8189 to fill in the value if this is an embedded PIC switch table
8192 || (mips_pic
== EMBEDDED_PIC
&& SWITCH_TABLE (fixP
)))
8193 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
,
8198 /* If we are deleting this reloc entry, we must fill in the
8200 assert (fixP
->fx_size
== 2);
8202 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
,
8206 case BFD_RELOC_LO16
:
8207 /* When handling an embedded PIC switch statement, we can wind
8208 up deleting a LO16 reloc. See the 'o' case in mips_ip. */
8211 if (value
< -0x8000 || value
> 0x7fff)
8212 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
8213 "relocation overflow");
8214 buf
= (unsigned char *) fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
8215 if (byte_order
== BIG_ENDIAN
)
8217 md_number_to_chars (buf
, value
, 2);
8221 case BFD_RELOC_16_PCREL_S2
:
8223 * We need to save the bits in the instruction since fixup_segment()
8224 * might be deleting the relocation entry (i.e., a branch within
8225 * the current segment).
8227 /* TinyRISC can branch to odd addresses */
8228 if ((value
& (mips16
? 0x1 : 0x3)) != 0)
8229 as_warn_where (fixP
->fx_file
, fixP
->fx_line
,
8230 "Branch to odd address (%lx)", value
);
8233 /* update old instruction data */
8234 buf
= (unsigned char *) (fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
);
8238 insn
= (buf
[3] << 24) | (buf
[2] << 16) | (buf
[1] << 8) | buf
[0];
8242 insn
= (buf
[0] << 24) | (buf
[1] << 16) | (buf
[2] << 8) | buf
[3];
8250 if (value
>= -0x8000 && value
< 0x8000)
8251 insn
|= value
& 0xffff;
8254 /* The branch offset is too large. If this is an
8255 unconditional branch, and we are not generating PIC code,
8256 we can convert it to an absolute jump instruction. */
8257 if (mips_pic
== NO_PIC
8259 && fixP
->fx_frag
->fr_address
>= text_section
->vma
8260 && (fixP
->fx_frag
->fr_address
8261 < text_section
->vma
+ text_section
->_raw_size
)
8262 && ((insn
& 0xffff0000) == 0x10000000 /* beq $0,$0 */
8263 || (insn
& 0xffff0000) == 0x04010000 /* bgez $0 */
8264 || (insn
& 0xffff0000) == 0x04110000)) /* bgezal $0 */
8266 if ((insn
& 0xffff0000) == 0x04110000) /* bgezal $0 */
8267 insn
= 0x0c000000; /* jal */
8269 insn
= 0x08000000; /* j */
8270 fixP
->fx_r_type
= BFD_RELOC_MIPS_JMP
;
8272 fixP
->fx_addsy
= section_symbol (text_section
);
8273 fixP
->fx_addnumber
= (value
<< 2) + md_pcrel_from (fixP
);
8277 /* FIXME. It would be possible in principle to handle
8278 conditional branches which overflow. They could be
8279 transformed into a branch around a jump. This would
8280 require setting up variant frags for each different
8281 branch type. The native MIPS assembler attempts to
8282 handle these cases, but it appears to do it
8284 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
8285 "Relocation overflow");
8289 md_number_to_chars ((char *) buf
, (valueT
) insn
, 4);
8304 const struct mips_opcode
*p
;
8305 int treg
, sreg
, dreg
, shamt
;
8310 for (i
= 0; i
< NUMOPCODES
; ++i
)
8312 p
= &mips_opcodes
[i
];
8313 if (((oc
& p
->mask
) == p
->match
) && (p
->pinfo
!= INSN_MACRO
))
8315 printf ("%08lx %s\t", oc
, p
->name
);
8316 treg
= (oc
>> 16) & 0x1f;
8317 sreg
= (oc
>> 21) & 0x1f;
8318 dreg
= (oc
>> 11) & 0x1f;
8319 shamt
= (oc
>> 6) & 0x1f;
8321 for (args
= p
->args
;; ++args
)
8332 printf ("%c", *args
);
8336 assert (treg
== sreg
);
8337 printf ("$%d,$%d", treg
, sreg
);
8342 printf ("$%d", dreg
);
8347 printf ("$%d", treg
);
8351 printf ("0x%x", treg
);
8356 printf ("$%d", sreg
);
8360 printf ("0x%08lx", oc
& 0x1ffffff);
8372 printf ("$%d", shamt
);
8383 printf ("%08lx UNDEFINED\n", oc
);
8394 name
= input_line_pointer
;
8395 c
= get_symbol_end ();
8396 p
= (symbolS
*) symbol_find_or_make (name
);
8397 *input_line_pointer
= c
;
8401 /* Align the current frag to a given power of two. The MIPS assembler
8402 also automatically adjusts any preceding label. */
8405 mips_align (to
, fill
, label
)
8410 mips_emit_delays ();
8411 frag_align (to
, fill
);
8412 record_alignment (now_seg
, to
);
8415 assert (S_GET_SEGMENT (label
) == now_seg
);
8416 label
->sy_frag
= frag_now
;
8417 S_SET_VALUE (label
, (valueT
) frag_now_fix ());
8421 /* Align to a given power of two. .align 0 turns off the automatic
8422 alignment used by the data creating pseudo-ops. */
8429 register long temp_fill
;
8430 long max_alignment
= 15;
8434 o Note that the assembler pulls down any immediately preceeding label
8435 to the aligned address.
8436 o It's not documented but auto alignment is reinstated by
8437 a .align pseudo instruction.
8438 o Note also that after auto alignment is turned off the mips assembler
8439 issues an error on attempt to assemble an improperly aligned data item.
8444 temp
= get_absolute_expression ();
8445 if (temp
> max_alignment
)
8446 as_bad ("Alignment too large: %d. assumed.", temp
= max_alignment
);
8449 as_warn ("Alignment negative: 0 assumed.");
8452 if (*input_line_pointer
== ',')
8454 input_line_pointer
++;
8455 temp_fill
= get_absolute_expression ();
8462 mips_align (temp
, (int) temp_fill
, insn_label
);
8469 demand_empty_rest_of_line ();
8473 mips_flush_pending_output ()
8475 mips_emit_delays ();
8485 /* When generating embedded PIC code, we only use the .text, .lit8,
8486 .sdata and .sbss sections. We change the .data and .rdata
8487 pseudo-ops to use .sdata. */
8488 if (mips_pic
== EMBEDDED_PIC
8489 && (sec
== 'd' || sec
== 'r'))
8492 mips_emit_delays ();
8502 subseg_set (bss_section
, (subsegT
) get_absolute_expression ());
8503 demand_empty_rest_of_line ();
8507 if (USE_GLOBAL_POINTER_OPT
)
8509 seg
= subseg_new (RDATA_SECTION_NAME
,
8510 (subsegT
) get_absolute_expression ());
8511 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
8513 bfd_set_section_flags (stdoutput
, seg
,
8519 if (strcmp (TARGET_OS
, "elf") != 0)
8520 bfd_set_section_alignment (stdoutput
, seg
, 4);
8522 demand_empty_rest_of_line ();
8526 as_bad ("No read only data section in this object file format");
8527 demand_empty_rest_of_line ();
8533 if (USE_GLOBAL_POINTER_OPT
)
8535 seg
= subseg_new (".sdata", (subsegT
) get_absolute_expression ());
8536 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
8538 bfd_set_section_flags (stdoutput
, seg
,
8539 SEC_ALLOC
| SEC_LOAD
| SEC_RELOC
8541 if (strcmp (TARGET_OS
, "elf") != 0)
8542 bfd_set_section_alignment (stdoutput
, seg
, 4);
8544 demand_empty_rest_of_line ();
8549 as_bad ("Global pointers not supported; recompile -G 0");
8550 demand_empty_rest_of_line ();
8559 mips_enable_auto_align ()
8571 mips_emit_delays ();
8572 if (log_size
> 0 && auto_align
)
8573 mips_align (log_size
, 0, label
);
8575 cons (1 << log_size
);
8586 mips_emit_delays ();
8590 mips_align (3, 0, label
);
8592 mips_align (2, 0, label
);
8599 /* Handle .globl. We need to override it because on Irix 5 you are
8602 where foo is an undefined symbol, to mean that foo should be
8603 considered to be the address of a function. */
8614 name
= input_line_pointer
;
8615 c
= get_symbol_end ();
8616 symbolP
= symbol_find_or_make (name
);
8617 *input_line_pointer
= c
;
8620 /* On Irix 5, every global symbol that is not explicitly labelled as
8621 being a function is apparently labelled as being an object. */
8624 if (! is_end_of_line
[(unsigned char) *input_line_pointer
])
8629 secname
= input_line_pointer
;
8630 c
= get_symbol_end ();
8631 sec
= bfd_get_section_by_name (stdoutput
, secname
);
8633 as_bad ("%s: no such section", secname
);
8634 *input_line_pointer
= c
;
8636 if (sec
!= NULL
&& (sec
->flags
& SEC_CODE
) != 0)
8637 flag
= BSF_FUNCTION
;
8640 symbolP
->bsym
->flags
|= flag
;
8642 S_SET_EXTERNAL (symbolP
);
8643 demand_empty_rest_of_line ();
8653 opt
= input_line_pointer
;
8654 c
= get_symbol_end ();
8658 /* FIXME: What does this mean? */
8660 else if (strncmp (opt
, "pic", 3) == 0)
8668 mips_pic
= SVR4_PIC
;
8670 as_bad (".option pic%d not supported", i
);
8672 if (USE_GLOBAL_POINTER_OPT
&& mips_pic
== SVR4_PIC
)
8674 if (g_switch_seen
&& g_switch_value
!= 0)
8675 as_warn ("-G may not be used with SVR4 PIC code");
8677 bfd_set_gp_size (stdoutput
, 0);
8681 as_warn ("Unrecognized option \"%s\"", opt
);
8683 *input_line_pointer
= c
;
8684 demand_empty_rest_of_line ();
8691 char *name
= input_line_pointer
, ch
;
8693 while (!is_end_of_line
[(unsigned char) *input_line_pointer
])
8694 input_line_pointer
++;
8695 ch
= *input_line_pointer
;
8696 *input_line_pointer
= '\0';
8698 if (strcmp (name
, "reorder") == 0)
8702 prev_insn_unreordered
= 1;
8703 prev_prev_insn_unreordered
= 1;
8707 else if (strcmp (name
, "noreorder") == 0)
8709 mips_emit_delays ();
8711 mips_any_noreorder
= 1;
8713 else if (strcmp (name
, "at") == 0)
8717 else if (strcmp (name
, "noat") == 0)
8721 else if (strcmp (name
, "macro") == 0)
8723 mips_warn_about_macros
= 0;
8725 else if (strcmp (name
, "nomacro") == 0)
8727 if (mips_noreorder
== 0)
8728 as_bad ("`noreorder' must be set before `nomacro'");
8729 mips_warn_about_macros
= 1;
8731 else if (strcmp (name
, "move") == 0 || strcmp (name
, "novolatile") == 0)
8735 else if (strcmp (name
, "nomove") == 0 || strcmp (name
, "volatile") == 0)
8739 else if (strcmp (name
, "bopt") == 0)
8743 else if (strcmp (name
, "nobopt") == 0)
8747 else if (strcmp (name
, "mips16") == 0
8748 || strcmp (name
, "MIPS-16") == 0)
8750 else if (strcmp (name
, "nomips16") == 0
8751 || strcmp (name
, "noMIPS-16") == 0)
8753 else if (strncmp (name
, "mips", 4) == 0)
8757 /* Permit the user to change the ISA on the fly. Needless to
8758 say, misuse can cause serious problems. */
8759 isa
= atoi (name
+ 4);
8761 mips_isa
= file_mips_isa
;
8762 else if (isa
< 1 || isa
> 4)
8763 as_bad ("unknown ISA level");
8767 else if (strcmp (name
, "autoextend") == 0)
8768 mips16_autoextend
= 1;
8769 else if (strcmp (name
, "noautoextend") == 0)
8770 mips16_autoextend
= 0;
8773 as_warn ("Tried to set unrecognized symbol: %s\n", name
);
8775 *input_line_pointer
= ch
;
8776 demand_empty_rest_of_line ();
8779 /* Handle the .abicalls pseudo-op. I believe this is equivalent to
8780 .option pic2. It means to generate SVR4 PIC calls. */
8786 mips_pic
= SVR4_PIC
;
8787 if (USE_GLOBAL_POINTER_OPT
)
8789 if (g_switch_seen
&& g_switch_value
!= 0)
8790 as_warn ("-G may not be used with SVR4 PIC code");
8793 bfd_set_gp_size (stdoutput
, 0);
8794 demand_empty_rest_of_line ();
8797 /* Handle the .cpload pseudo-op. This is used when generating SVR4
8798 PIC code. It sets the $gp register for the function based on the
8799 function address, which is in the register named in the argument.
8800 This uses a relocation against _gp_disp, which is handled specially
8801 by the linker. The result is:
8802 lui $gp,%hi(_gp_disp)
8803 addiu $gp,$gp,%lo(_gp_disp)
8804 addu $gp,$gp,.cpload argument
8805 The .cpload argument is normally $25 == $t9. */
8814 /* If we are not generating SVR4 PIC code, .cpload is ignored. */
8815 if (mips_pic
!= SVR4_PIC
)
8821 /* .cpload should be a in .set noreorder section. */
8822 if (mips_noreorder
== 0)
8823 as_warn (".cpload not in noreorder section");
8826 ex
.X_add_symbol
= symbol_find_or_make ("_gp_disp");
8827 ex
.X_op_symbol
= NULL
;
8828 ex
.X_add_number
= 0;
8830 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
8831 ex
.X_add_symbol
->bsym
->flags
|= BSF_OBJECT
;
8833 macro_build_lui ((char *) NULL
, &icnt
, &ex
, GP
);
8834 macro_build ((char *) NULL
, &icnt
, &ex
, "addiu", "t,r,j", GP
, GP
,
8835 (int) BFD_RELOC_LO16
);
8837 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "addu", "d,v,t",
8838 GP
, GP
, tc_get_register (0));
8840 demand_empty_rest_of_line ();
8843 /* Handle the .cprestore pseudo-op. This stores $gp into a given
8844 offset from $sp. The offset is remembered, and after making a PIC
8845 call $gp is restored from that location. */
8848 s_cprestore (ignore
)
8854 /* If we are not generating SVR4 PIC code, .cprestore is ignored. */
8855 if (mips_pic
!= SVR4_PIC
)
8861 mips_cprestore_offset
= get_absolute_expression ();
8863 ex
.X_op
= O_constant
;
8864 ex
.X_add_symbol
= NULL
;
8865 ex
.X_op_symbol
= NULL
;
8866 ex
.X_add_number
= mips_cprestore_offset
;
8868 macro_build ((char *) NULL
, &icnt
, &ex
,
8869 mips_isa
< 3 ? "sw" : "sd",
8870 "t,o(b)", GP
, (int) BFD_RELOC_LO16
, SP
);
8872 demand_empty_rest_of_line ();
8875 /* Handle the .gpword pseudo-op. This is used when generating PIC
8876 code. It generates a 32 bit GP relative reloc. */
8886 /* When not generating PIC code, this is treated as .word. */
8887 if (mips_pic
!= SVR4_PIC
)
8894 mips_emit_delays ();
8896 mips_align (2, 0, label
);
8901 if (ex
.X_op
!= O_symbol
|| ex
.X_add_number
!= 0)
8903 as_bad ("Unsupported use of .gpword");
8904 ignore_rest_of_line ();
8908 md_number_to_chars (p
, (valueT
) 0, 4);
8909 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 4, &ex
, 0,
8910 BFD_RELOC_MIPS_GPREL32
);
8912 demand_empty_rest_of_line ();
8915 /* Handle the .cpadd pseudo-op. This is used when dealing with switch
8916 tables in SVR4 PIC code. */
8925 /* This is ignored when not generating SVR4 PIC code. */
8926 if (mips_pic
!= SVR4_PIC
)
8932 /* Add $gp to the register named as an argument. */
8933 reg
= tc_get_register (0);
8934 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
8935 mips_isa
< 3 ? "addu" : "daddu",
8936 "d,v,t", reg
, reg
, GP
);
8938 demand_empty_rest_of_line ();
8941 /* Parse a register string into a number. Called from the ECOFF code
8942 to parse .frame. The argument is non-zero if this is the frame
8943 register, so that we can record it in mips_frame_reg. */
8946 tc_get_register (frame
)
8952 if (*input_line_pointer
++ != '$')
8954 as_warn ("expected `$'");
8957 else if (isdigit ((unsigned char) *input_line_pointer
))
8959 reg
= get_absolute_expression ();
8960 if (reg
< 0 || reg
>= 32)
8962 as_warn ("Bad register number");
8968 if (strncmp (input_line_pointer
, "fp", 2) == 0)
8970 else if (strncmp (input_line_pointer
, "sp", 2) == 0)
8972 else if (strncmp (input_line_pointer
, "gp", 2) == 0)
8974 else if (strncmp (input_line_pointer
, "at", 2) == 0)
8978 as_warn ("Unrecognized register name");
8981 input_line_pointer
+= 2;
8984 mips_frame_reg
= reg
!= 0 ? reg
: SP
;
8989 md_section_align (seg
, addr
)
8993 int align
= bfd_get_section_alignment (stdoutput
, seg
);
8996 /* We don't need to align ELF sections to the full alignment.
8997 However, Irix 5 may prefer that we align them at least to a 16
8998 byte boundary. We don't bother to align the sections if we are
8999 targeted for an embedded system. */
9000 if (strcmp (TARGET_OS
, "elf") == 0)
9006 return ((addr
+ (1 << align
) - 1) & (-1 << align
));
9009 /* Utility routine, called from above as well. If called while the
9010 input file is still being read, it's only an approximation. (For
9011 example, a symbol may later become defined which appeared to be
9012 undefined earlier.) */
9015 nopic_need_relax (sym
)
9021 if (USE_GLOBAL_POINTER_OPT
)
9023 const char *symname
;
9026 /* Find out whether this symbol can be referenced off the GP
9027 register. It can be if it is smaller than the -G size or if
9028 it is in the .sdata or .sbss section. Certain symbols can
9029 not be referenced off the GP, although it appears as though
9031 symname
= S_GET_NAME (sym
);
9032 if (symname
!= (const char *) NULL
9033 && (strcmp (symname
, "eprol") == 0
9034 || strcmp (symname
, "etext") == 0
9035 || strcmp (symname
, "_gp") == 0
9036 || strcmp (symname
, "edata") == 0
9037 || strcmp (symname
, "_fbss") == 0
9038 || strcmp (symname
, "_fdata") == 0
9039 || strcmp (symname
, "_ftext") == 0
9040 || strcmp (symname
, "end") == 0
9041 || strcmp (symname
, "_gp_disp") == 0))
9043 else if (! S_IS_DEFINED (sym
)
9045 #ifndef NO_ECOFF_DEBUGGING
9046 || (sym
->ecoff_extern_size
!= 0
9047 && sym
->ecoff_extern_size
<= g_switch_value
)
9049 || (S_GET_VALUE (sym
) != 0
9050 && S_GET_VALUE (sym
) <= g_switch_value
)))
9054 const char *segname
;
9056 segname
= segment_name (S_GET_SEGMENT (sym
));
9057 assert (strcmp (segname
, ".lit8") != 0
9058 && strcmp (segname
, ".lit4") != 0);
9059 change
= (strcmp (segname
, ".sdata") != 0
9060 && strcmp (segname
, ".sbss") != 0);
9065 /* We are not optimizing for the GP register. */
9069 /* Given a mips16 variant frag FRAGP, return non-zero if it needs an
9070 extended opcode. SEC is the section the frag is in. */
9073 mips16_extended_frag (fragp
, sec
, stretch
)
9079 register const struct mips16_immed_operand
*op
;
9081 int mintiny
, maxtiny
;
9084 if (RELAX_MIPS16_USER_SMALL (fragp
->fr_subtype
))
9086 if (RELAX_MIPS16_USER_EXT (fragp
->fr_subtype
))
9089 type
= RELAX_MIPS16_TYPE (fragp
->fr_subtype
);
9090 op
= mips16_immed_operands
;
9091 while (op
->type
!= type
)
9094 assert (op
< mips16_immed_operands
+ MIPS16_NUM_IMMED
);
9099 if (type
== '<' || type
== '>' || type
== '[' || type
== ']')
9102 maxtiny
= 1 << op
->nbits
;
9107 maxtiny
= (1 << op
->nbits
) - 1;
9112 mintiny
= - (1 << (op
->nbits
- 1));
9113 maxtiny
= (1 << (op
->nbits
- 1)) - 1;
9116 /* We can't call S_GET_VALUE here, because we don't want to lock in
9117 a particular frag address. */
9118 if (fragp
->fr_symbol
->sy_value
.X_op
== O_constant
)
9120 val
= (fragp
->fr_symbol
->sy_value
.X_add_number
9121 + fragp
->fr_symbol
->sy_frag
->fr_address
);
9122 symsec
= S_GET_SEGMENT (fragp
->fr_symbol
);
9124 else if (fragp
->fr_symbol
->sy_value
.X_op
== O_symbol
9125 && (fragp
->fr_symbol
->sy_value
.X_add_symbol
->sy_value
.X_op
9128 val
= (fragp
->fr_symbol
->sy_value
.X_add_symbol
->sy_value
.X_add_number
9129 + fragp
->fr_symbol
->sy_value
.X_add_symbol
->sy_frag
->fr_address
9130 + fragp
->fr_symbol
->sy_value
.X_add_number
9131 + fragp
->fr_symbol
->sy_frag
->fr_address
);
9132 symsec
= S_GET_SEGMENT (fragp
->fr_symbol
->sy_value
.X_add_symbol
);
9141 /* We won't have the section when we are called from
9142 mips_relax_frag. However, we will always have been called
9143 from md_estimate_size_before_relax first. If this is a
9144 branch to a different section, we mark it as such. If SEC is
9145 NULL, and the frag is not marked, then it must be a branch to
9146 the same section. */
9149 if (RELAX_MIPS16_LONG_BRANCH (fragp
->fr_subtype
))
9157 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
9159 /* FIXME: We should support this, and let the linker
9160 catch branches and loads that are out of range. */
9161 as_bad_where (fragp
->fr_file
, fragp
->fr_line
,
9162 "unsupported PC relative reference to different section");
9168 /* In this case, we know for sure that the symbol fragment is in
9169 the same section. If the fr_address of the symbol fragment
9170 is greater then the address of this fragment we want to add
9171 in STRETCH in order to get a better estimate of the address.
9172 This particularly matters because of the shift bits. */
9174 && fragp
->fr_symbol
->sy_frag
->fr_address
>= fragp
->fr_address
)
9178 /* Adjust stretch for any alignment frag. */
9179 for (f
= fragp
; f
!= fragp
->fr_symbol
->sy_frag
; f
= f
->fr_next
)
9182 if (f
->fr_type
== rs_align
|| f
->fr_type
== rs_align_code
)
9185 stretch
= - ((- stretch
)
9186 & ~ ((1 << (int) f
->fr_offset
) - 1));
9188 stretch
&= ~ ((1 << (int) f
->fr_offset
) - 1);
9196 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
9198 /* The base address rules are complicated. The base address of
9199 a branch is the following instruction. The base address of a
9200 PC relative load or add is the instruction itself, but if it
9201 is extended add 2, and if it is in a delay slot (in which
9202 case it can not be extended) use the address of the
9203 instruction whose delay slot it is in. */
9204 if (type
== 'p' || type
== 'q')
9206 else if (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
))
9208 else if (RELAX_MIPS16_DSLOT (fragp
->fr_subtype
))
9211 /* If we are currently assuming that this frag should be
9212 extended, then the current address is two bytes higher. */
9213 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
9216 val
-= addr
& ~ ((1 << op
->shift
) - 1);
9218 /* Branch offsets have an implicit 0 in the lowest bit. */
9219 if (type
== 'p' || type
== 'q')
9222 /* If any of the shifted bits are set, we must use an extended
9223 opcode. If the address depends on the size of this
9224 instruction, this can lead to a loop, so we arrange to always
9225 use an extended opcode. We only check this when we are in
9226 the main relaxation loop, when SEC is NULL. */
9227 if ((val
& ((1 << op
->shift
) - 1)) != 0 && sec
== NULL
)
9230 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
9234 /* If we are about to mark a frag as extended because the value
9235 is precisely maxtiny + 1, then there is a chance of an
9236 infinite loop as in the following code:
9241 In this case when the la is extended, foo is 0x3fc bytes
9242 away, so the la can be shrunk, but then foo is 0x400 away, so
9243 the la must be extended. To avoid this loop, we mark the
9244 frag as extended if it was small, and is about to become
9245 extended with a value of maxtiny + 1. */
9246 if (val
== ((maxtiny
+ 1) << op
->shift
)
9247 && ! RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
)
9251 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
9255 else if (symsec
!= absolute_section
&& sec
!= NULL
)
9256 as_bad_where (fragp
->fr_file
, fragp
->fr_line
, "unsupported relocation");
9258 if ((val
& ((1 << op
->shift
) - 1)) != 0
9259 || val
< (mintiny
<< op
->shift
)
9260 || val
> (maxtiny
<< op
->shift
))
9266 /* Estimate the size of a frag before relaxing. Unless this is the
9267 mips16, we are not really relaxing here, and the final size is
9268 encoded in the subtype information. For the mips16, we have to
9269 decide whether we are using an extended opcode or not. */
9273 md_estimate_size_before_relax (fragp
, segtype
)
9279 if (RELAX_MIPS16_P (fragp
->fr_subtype
))
9281 if (mips16_extended_frag (fragp
, segtype
, 0))
9283 fragp
->fr_subtype
= RELAX_MIPS16_MARK_EXTENDED (fragp
->fr_subtype
);
9288 fragp
->fr_subtype
= RELAX_MIPS16_CLEAR_EXTENDED (fragp
->fr_subtype
);
9293 if (mips_pic
== NO_PIC
)
9295 change
= nopic_need_relax (fragp
->fr_symbol
);
9297 else if (mips_pic
== SVR4_PIC
)
9299 asection
*symsec
= fragp
->fr_symbol
->bsym
->section
;
9301 /* This must duplicate the test in adjust_reloc_syms. */
9302 change
= (symsec
!= &bfd_und_section
9303 && symsec
!= &bfd_abs_section
9304 && ! bfd_is_com_section (symsec
));
9311 /* Record the offset to the first reloc in the fr_opcode field.
9312 This lets md_convert_frag and tc_gen_reloc know that the code
9313 must be expanded. */
9314 fragp
->fr_opcode
= (fragp
->fr_literal
9316 - RELAX_OLD (fragp
->fr_subtype
)
9317 + RELAX_RELOC1 (fragp
->fr_subtype
));
9318 /* FIXME: This really needs as_warn_where. */
9319 if (RELAX_WARN (fragp
->fr_subtype
))
9320 as_warn ("AT used after \".set noat\" or macro used after \".set nomacro\"");
9326 return RELAX_NEW (fragp
->fr_subtype
) - RELAX_OLD (fragp
->fr_subtype
);
9329 /* Translate internal representation of relocation info to BFD target
9333 tc_gen_reloc (section
, fixp
)
9337 static arelent
*retval
[4];
9339 bfd_reloc_code_real_type code
;
9341 reloc
= retval
[0] = (arelent
*) xmalloc (sizeof (arelent
));
9344 reloc
->sym_ptr_ptr
= &fixp
->fx_addsy
->bsym
;
9345 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
9347 if (mips_pic
== EMBEDDED_PIC
9348 && SWITCH_TABLE (fixp
))
9350 /* For a switch table entry we use a special reloc. The addend
9351 is actually the difference between the reloc address and the
9353 reloc
->addend
= reloc
->address
- S_GET_VALUE (fixp
->fx_subsy
);
9354 if (OUTPUT_FLAVOR
!= bfd_target_ecoff_flavour
)
9355 as_fatal ("Double check fx_r_type in tc-mips.c:tc_gen_reloc");
9356 fixp
->fx_r_type
= BFD_RELOC_GPREL32
;
9358 else if (fixp
->fx_r_type
== BFD_RELOC_PCREL_LO16
)
9360 /* We use a special addend for an internal RELLO reloc. */
9361 if (fixp
->fx_addsy
->bsym
->flags
& BSF_SECTION_SYM
)
9362 reloc
->addend
= reloc
->address
- S_GET_VALUE (fixp
->fx_subsy
);
9364 reloc
->addend
= fixp
->fx_addnumber
+ reloc
->address
;
9366 else if (fixp
->fx_r_type
== BFD_RELOC_PCREL_HI16_S
)
9368 assert (fixp
->fx_next
!= NULL
9369 && fixp
->fx_next
->fx_r_type
== BFD_RELOC_PCREL_LO16
);
9370 /* We use a special addend for an internal RELHI reloc. The
9371 reloc is relative to the RELLO; adjust the addend
9373 if (fixp
->fx_addsy
->bsym
->flags
& BSF_SECTION_SYM
)
9374 reloc
->addend
= (fixp
->fx_next
->fx_frag
->fr_address
9375 + fixp
->fx_next
->fx_where
9376 - S_GET_VALUE (fixp
->fx_subsy
));
9378 reloc
->addend
= (fixp
->fx_addnumber
9379 + fixp
->fx_next
->fx_frag
->fr_address
9380 + fixp
->fx_next
->fx_where
);
9382 else if (fixp
->fx_pcrel
== 0)
9383 reloc
->addend
= fixp
->fx_addnumber
;
9386 if (OUTPUT_FLAVOR
!= bfd_target_aout_flavour
)
9387 /* A gruesome hack which is a result of the gruesome gas reloc
9389 reloc
->addend
= reloc
->address
;
9391 reloc
->addend
= -reloc
->address
;
9394 /* If this is a variant frag, we may need to adjust the existing
9395 reloc and generate a new one. */
9396 if (fixp
->fx_frag
->fr_opcode
!= NULL
9397 && (fixp
->fx_r_type
== BFD_RELOC_MIPS_GPREL
9398 || fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT16
9399 || fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL16
9400 || fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT_HI16
9401 || fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT_LO16
9402 || fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL_HI16
9403 || fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL_LO16
))
9407 assert (! RELAX_MIPS16_P (fixp
->fx_frag
->fr_subtype
));
9409 /* If this is not the last reloc in this frag, then we have two
9410 GPREL relocs, or a GOT_HI16/GOT_LO16 pair, or a
9411 CALL_HI16/CALL_LO16, both of which are being replaced. Let
9412 the second one handle all of them. */
9413 if (fixp
->fx_next
!= NULL
9414 && fixp
->fx_frag
== fixp
->fx_next
->fx_frag
)
9416 assert ((fixp
->fx_r_type
== BFD_RELOC_MIPS_GPREL
9417 && fixp
->fx_next
->fx_r_type
== BFD_RELOC_MIPS_GPREL
)
9418 || (fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT_HI16
9419 && (fixp
->fx_next
->fx_r_type
9420 == BFD_RELOC_MIPS_GOT_LO16
))
9421 || (fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL_HI16
9422 && (fixp
->fx_next
->fx_r_type
9423 == BFD_RELOC_MIPS_CALL_LO16
)));
9428 fixp
->fx_where
= fixp
->fx_frag
->fr_opcode
- fixp
->fx_frag
->fr_literal
;
9429 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
9430 reloc2
= retval
[1] = (arelent
*) xmalloc (sizeof (arelent
));
9432 reloc2
->sym_ptr_ptr
= &fixp
->fx_addsy
->bsym
;
9433 reloc2
->address
= (reloc
->address
9434 + (RELAX_RELOC2 (fixp
->fx_frag
->fr_subtype
)
9435 - RELAX_RELOC1 (fixp
->fx_frag
->fr_subtype
)));
9436 reloc2
->addend
= fixp
->fx_addnumber
;
9437 reloc2
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_LO16
);
9438 assert (reloc2
->howto
!= NULL
);
9440 if (RELAX_RELOC3 (fixp
->fx_frag
->fr_subtype
))
9444 reloc3
= retval
[2] = (arelent
*) xmalloc (sizeof (arelent
));
9447 reloc3
->address
+= 4;
9450 if (mips_pic
== NO_PIC
)
9452 assert (fixp
->fx_r_type
== BFD_RELOC_MIPS_GPREL
);
9453 fixp
->fx_r_type
= BFD_RELOC_HI16_S
;
9455 else if (mips_pic
== SVR4_PIC
)
9457 switch (fixp
->fx_r_type
)
9461 case BFD_RELOC_MIPS_GOT16
:
9463 case BFD_RELOC_MIPS_CALL16
:
9464 case BFD_RELOC_MIPS_GOT_LO16
:
9465 case BFD_RELOC_MIPS_CALL_LO16
:
9466 fixp
->fx_r_type
= BFD_RELOC_MIPS_GOT16
;
9474 /* Since DIFF_EXPR_OK is defined in tc-mips.h, it is possible that
9475 fixup_segment converted a non-PC relative reloc into a PC
9476 relative reloc. In such a case, we need to convert the reloc
9478 code
= fixp
->fx_r_type
;
9484 code
= BFD_RELOC_8_PCREL
;
9487 code
= BFD_RELOC_16_PCREL
;
9490 code
= BFD_RELOC_32_PCREL
;
9493 code
= BFD_RELOC_64_PCREL
;
9495 case BFD_RELOC_8_PCREL
:
9496 case BFD_RELOC_16_PCREL
:
9497 case BFD_RELOC_32_PCREL
:
9498 case BFD_RELOC_64_PCREL
:
9499 case BFD_RELOC_16_PCREL_S2
:
9500 case BFD_RELOC_PCREL_HI16_S
:
9501 case BFD_RELOC_PCREL_LO16
:
9504 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
9505 "Cannot make %s relocation PC relative",
9506 bfd_get_reloc_code_name (code
));
9510 /* To support a PC relative reloc when generating embedded PIC code
9511 for ECOFF, we use a Cygnus extension. We check for that here to
9512 make sure that we don't let such a reloc escape normally. */
9513 if (OUTPUT_FLAVOR
== bfd_target_ecoff_flavour
9514 && code
== BFD_RELOC_16_PCREL_S2
9515 && mips_pic
!= EMBEDDED_PIC
)
9516 reloc
->howto
= NULL
;
9518 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
9520 if (reloc
->howto
== NULL
)
9522 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
9523 "Can not represent %s relocation in this object file format",
9524 bfd_get_reloc_code_name (code
));
9531 /* Relax a machine dependent frag. This returns the amount by which
9532 the current size of the frag should change. */
9535 mips_relax_frag (fragp
, stretch
)
9539 if (! RELAX_MIPS16_P (fragp
->fr_subtype
))
9542 if (mips16_extended_frag (fragp
, (asection
*) NULL
, stretch
))
9544 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
9546 fragp
->fr_subtype
= RELAX_MIPS16_MARK_EXTENDED (fragp
->fr_subtype
);
9551 if (! RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
9553 fragp
->fr_subtype
= RELAX_MIPS16_CLEAR_EXTENDED (fragp
->fr_subtype
);
9560 /* Convert a machine dependent frag. */
9563 md_convert_frag (abfd
, asec
, fragp
)
9571 if (RELAX_MIPS16_P (fragp
->fr_subtype
))
9574 register const struct mips16_immed_operand
*op
;
9580 unsigned short extend
;
9582 type
= RELAX_MIPS16_TYPE (fragp
->fr_subtype
);
9583 op
= mips16_immed_operands
;
9584 while (op
->type
!= type
)
9587 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
9598 resolve_symbol_value (fragp
->fr_symbol
);
9599 val
= S_GET_VALUE (fragp
->fr_symbol
);
9604 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
9606 /* The rules for the base address of a PC relative reloc are
9607 complicated; see mips16_extended_frag. */
9608 if (type
== 'p' || type
== 'q')
9610 else if (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
))
9612 else if (RELAX_MIPS16_DSLOT (fragp
->fr_subtype
))
9617 addr
&= ~ (addressT
) ((1 << op
->shift
) - 1);
9620 /* Make sure the section winds up with the alignment we have
9623 record_alignment (asec
, op
->shift
);
9626 buf
= (bfd_byte
*) (fragp
->fr_literal
+ fragp
->fr_fix
);
9633 insn
= bfd_getl16 (buf
);
9636 insn
= bfd_getb16 (buf
);
9640 mips16_immed (fragp
->fr_file
, fragp
->fr_line
, type
, val
, false, small
,
9641 ext
, &insn
, &use_extend
, &extend
);
9645 md_number_to_chars (buf
, 0xf000 | extend
, 2);
9650 md_number_to_chars (buf
, insn
, 2);
9656 if (fragp
->fr_opcode
== NULL
)
9659 old
= RELAX_OLD (fragp
->fr_subtype
);
9660 new = RELAX_NEW (fragp
->fr_subtype
);
9661 fixptr
= fragp
->fr_literal
+ fragp
->fr_fix
;
9664 memcpy (fixptr
- old
, fixptr
, new);
9666 fragp
->fr_fix
+= new - old
;
9670 /* This function is called whenever a label is defined. It is used
9671 when handling branch delays; if a branch has a label, we assume we
9675 mips_define_label (sym
)
9681 S_SET_OTHER (insn_label
, STO_MIPS16
);
9685 /* Decide whether a label is local. This is called by LOCAL_LABEL.
9686 In order to work with gcc when using mips-tfile, we must keep all
9687 local labels. However, in other cases, we want to discard them,
9688 since they are useless. */
9691 mips_local_label (name
)
9694 #ifndef NO_ECOFF_DEBUGGING
9697 && ! ecoff_debugging_seen
)
9699 /* We were called with -g, but we didn't see any debugging
9700 information. That may mean that gcc is smuggling debugging
9701 information through to mips-tfile, in which case we must
9702 generate all local labels. */
9707 /* Here it's OK to discard local labels. */
9709 return name
[0] == '$';
9712 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9714 /* Some special processing for a MIPS ELF file. */
9717 mips_elf_final_processing ()
9719 /* Write out the register information. */
9724 s
.ri_gprmask
= mips_gprmask
;
9725 s
.ri_cprmask
[0] = mips_cprmask
[0];
9726 s
.ri_cprmask
[1] = mips_cprmask
[1];
9727 s
.ri_cprmask
[2] = mips_cprmask
[2];
9728 s
.ri_cprmask
[3] = mips_cprmask
[3];
9729 /* The gp_value field is set by the MIPS ELF backend. */
9731 bfd_mips_elf32_swap_reginfo_out (stdoutput
, &s
,
9732 ((Elf32_External_RegInfo
*)
9733 mips_regmask_frag
));
9737 Elf64_Internal_RegInfo s
;
9739 s
.ri_gprmask
= mips_gprmask
;
9741 s
.ri_cprmask
[0] = mips_cprmask
[0];
9742 s
.ri_cprmask
[1] = mips_cprmask
[1];
9743 s
.ri_cprmask
[2] = mips_cprmask
[2];
9744 s
.ri_cprmask
[3] = mips_cprmask
[3];
9745 /* The gp_value field is set by the MIPS ELF backend. */
9747 bfd_mips_elf64_swap_reginfo_out (stdoutput
, &s
,
9748 ((Elf64_External_RegInfo
*)
9749 mips_regmask_frag
));
9752 /* Set the MIPS ELF flag bits. FIXME: There should probably be some
9753 sort of BFD interface for this. */
9754 if (mips_any_noreorder
)
9755 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_NOREORDER
;
9756 if (mips_pic
!= NO_PIC
)
9757 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_PIC
;
9760 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */
9762 /* These functions should really be defined by the object file format,
9763 since they are related to debugging information. However, this
9764 code has to work for the a.out format, which does not define them,
9765 so we provide simple versions here. These don't actually generate
9766 any debugging information, but they do simple checking and someday
9767 somebody may make them useful. */
9771 struct loc
*loc_next
;
9772 unsigned long loc_fileno
;
9773 unsigned long loc_lineno
;
9774 unsigned long loc_offset
;
9775 unsigned short loc_delta
;
9776 unsigned short loc_count
;
9785 struct proc
*proc_next
;
9786 struct symbol
*proc_isym
;
9787 struct symbol
*proc_end
;
9788 unsigned long proc_reg_mask
;
9789 unsigned long proc_reg_offset
;
9790 unsigned long proc_fpreg_mask
;
9791 unsigned long proc_fpreg_offset
;
9792 unsigned long proc_frameoffset
;
9793 unsigned long proc_framereg
;
9794 unsigned long proc_pcreg
;
9796 struct file
*proc_file
;
9803 struct file
*file_next
;
9804 unsigned long file_fileno
;
9805 struct symbol
*file_symbol
;
9806 struct symbol
*file_end
;
9807 struct proc
*file_proc
;
9812 static struct obstack proc_frags
;
9813 static procS
*proc_lastP
;
9814 static procS
*proc_rootP
;
9815 static int numprocs
;
9820 obstack_begin (&proc_frags
, 0x2000);
9826 /* check for premature end, nesting errors, etc */
9827 if (proc_lastP
&& proc_lastP
->proc_end
== NULL
)
9828 as_warn ("missing `.end' at end of assembly");
9837 if (*input_line_pointer
== '-')
9839 ++input_line_pointer
;
9842 if (!isdigit (*input_line_pointer
))
9843 as_bad ("Expected simple number.");
9844 if (input_line_pointer
[0] == '0')
9846 if (input_line_pointer
[1] == 'x')
9848 input_line_pointer
+= 2;
9849 while (isxdigit (*input_line_pointer
))
9852 val
|= hex_value (*input_line_pointer
++);
9854 return negative
? -val
: val
;
9858 ++input_line_pointer
;
9859 while (isdigit (*input_line_pointer
))
9862 val
|= *input_line_pointer
++ - '0';
9864 return negative
? -val
: val
;
9867 if (!isdigit (*input_line_pointer
))
9869 printf (" *input_line_pointer == '%c' 0x%02x\n",
9870 *input_line_pointer
, *input_line_pointer
);
9871 as_warn ("Invalid number");
9874 while (isdigit (*input_line_pointer
))
9877 val
+= *input_line_pointer
++ - '0';
9879 return negative
? -val
: val
;
9882 /* The .file directive; just like the usual .file directive, but there
9883 is an initial number which is the ECOFF file index. */
9891 line
= get_number ();
9896 /* The .end directive. */
9904 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
9907 demand_empty_rest_of_line ();
9911 if (now_seg
!= text_section
)
9912 as_warn (".end not in text section");
9915 as_warn (".end and no .ent seen yet.");
9921 assert (S_GET_NAME (p
));
9922 if (strcmp (S_GET_NAME (p
), S_GET_NAME (proc_lastP
->proc_isym
)))
9923 as_warn (".end symbol does not match .ent symbol.");
9926 proc_lastP
->proc_end
= (symbolS
*) 1;
9929 /* The .aent and .ent directives. */
9939 symbolP
= get_symbol ();
9940 if (*input_line_pointer
== ',')
9941 input_line_pointer
++;
9943 if (isdigit (*input_line_pointer
) || *input_line_pointer
== '-')
9944 number
= get_number ();
9945 if (now_seg
!= text_section
)
9946 as_warn (".ent or .aent not in text section.");
9948 if (!aent
&& proc_lastP
&& proc_lastP
->proc_end
== NULL
)
9949 as_warn ("missing `.end'");
9953 procP
= (procS
*) obstack_alloc (&proc_frags
, sizeof (*procP
));
9954 procP
->proc_isym
= symbolP
;
9955 procP
->proc_reg_mask
= 0;
9956 procP
->proc_reg_offset
= 0;
9957 procP
->proc_fpreg_mask
= 0;
9958 procP
->proc_fpreg_offset
= 0;
9959 procP
->proc_frameoffset
= 0;
9960 procP
->proc_framereg
= 0;
9961 procP
->proc_pcreg
= 0;
9962 procP
->proc_end
= NULL
;
9963 procP
->proc_next
= NULL
;
9965 proc_lastP
->proc_next
= procP
;
9971 demand_empty_rest_of_line ();
9974 /* The .frame directive. */
9987 frame_reg
= tc_get_register (1);
9988 if (*input_line_pointer
== ',')
9989 input_line_pointer
++;
9990 frame_off
= get_absolute_expression ();
9991 if (*input_line_pointer
== ',')
9992 input_line_pointer
++;
9993 pcreg
= tc_get_register (0);
9996 assert (proc_rootP
);
9997 proc_rootP
->proc_framereg
= frame_reg
;
9998 proc_rootP
->proc_frameoffset
= frame_off
;
9999 proc_rootP
->proc_pcreg
= pcreg
;
10000 /* bob macho .frame */
10002 /* We don't have to write out a frame stab for unoptimized code. */
10003 if (!(frame_reg
== FP
&& frame_off
== 0))
10006 as_warn ("No .ent for .frame to use.");
10007 (void) sprintf (str
, "R%d;%d", frame_reg
, frame_off
);
10008 symP
= symbol_new (str
, N_VFP
, 0, frag_now
);
10009 S_SET_TYPE (symP
, N_RMASK
);
10010 S_SET_OTHER (symP
, 0);
10011 S_SET_DESC (symP
, 0);
10012 symP
->sy_forward
= proc_lastP
->proc_isym
;
10013 /* bob perhaps I should have used pseudo set */
10015 demand_empty_rest_of_line ();
10019 /* The .fmask and .mask directives. */
10026 char str
[100], *strP
;
10032 mask
= get_number ();
10033 if (*input_line_pointer
== ',')
10034 input_line_pointer
++;
10035 off
= get_absolute_expression ();
10037 /* bob only for coff */
10038 assert (proc_rootP
);
10039 if (reg_type
== 'F')
10041 proc_rootP
->proc_fpreg_mask
= mask
;
10042 proc_rootP
->proc_fpreg_offset
= off
;
10046 proc_rootP
->proc_reg_mask
= mask
;
10047 proc_rootP
->proc_reg_offset
= off
;
10050 /* bob macho .mask + .fmask */
10052 /* We don't have to write out a mask stab if no saved regs. */
10056 as_warn ("No .ent for .mask to use.");
10058 for (i
= 0; i
< 32; i
++)
10062 sprintf (strP
, "%c%d,", reg_type
, i
);
10063 strP
+= strlen (strP
);
10067 sprintf (strP
, ";%d,", off
);
10068 symP
= symbol_new (str
, N_RMASK
, 0, frag_now
);
10069 S_SET_TYPE (symP
, N_RMASK
);
10070 S_SET_OTHER (symP
, 0);
10071 S_SET_DESC (symP
, 0);
10072 symP
->sy_forward
= proc_lastP
->proc_isym
;
10073 /* bob perhaps I should have used pseudo set */
10078 /* The .loc directive. */
10089 assert (now_seg
== text_section
);
10091 lineno
= get_number ();
10092 addroff
= frag_now_fix ();
10094 symbolP
= symbol_new ("", N_SLINE
, addroff
, frag_now
);
10095 S_SET_TYPE (symbolP
, N_SLINE
);
10096 S_SET_OTHER (symbolP
, 0);
10097 S_SET_DESC (symbolP
, lineno
);
10098 symbolP
->sy_segment
= now_seg
;