1 /* tc-mips.c -- assemble code for a MIPS chip.
2 Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001
3 Free Software Foundation, Inc.
4 Contributed by the OSF and Ralph Campbell.
5 Written by Keith Knowles and Ralph Campbell, working independently.
6 Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus
9 This file is part of GAS.
11 GAS is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 2, or (at your option)
16 GAS is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
21 You should have received a copy of the GNU General Public License
22 along with GAS; see the file COPYING. If not, write to the Free
23 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
39 #include "opcode/mips.h"
43 #define DBG(x) printf x
49 /* Clean up namespace so we can include obj-elf.h too. */
50 static int mips_output_flavor
PARAMS ((void));
51 static int mips_output_flavor () { return OUTPUT_FLAVOR
; }
52 #undef OBJ_PROCESS_STAB
59 #undef obj_frob_file_after_relocs
60 #undef obj_frob_symbol
62 #undef obj_sec_sym_ok_for_reloc
63 #undef OBJ_COPY_SYMBOL_ATTRIBUTES
66 /* Fix any of them that we actually care about. */
68 #define OUTPUT_FLAVOR mips_output_flavor()
75 #ifndef ECOFF_DEBUGGING
76 #define NO_ECOFF_DEBUGGING
77 #define ECOFF_DEBUGGING 0
82 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
83 static char *mips_regmask_frag
;
88 #define PIC_CALL_REG 25
96 #define ILLEGAL_REG (32)
98 /* Allow override of standard little-endian ECOFF format. */
100 #ifndef ECOFF_LITTLE_FORMAT
101 #define ECOFF_LITTLE_FORMAT "ecoff-littlemips"
104 extern int target_big_endian
;
106 /* 1 is we should use the 64 bit MIPS ELF ABI, 0 if we should use the
107 32 bit ABI. This has no meaning for ECOFF.
108 Note that the default is always 32 bit, even if "configured" for
109 64 bit [e.g. --target=mips64-elf]. */
112 /* The default target format to use. */
115 mips_target_format ()
117 switch (OUTPUT_FLAVOR
)
119 case bfd_target_aout_flavour
:
120 return target_big_endian
? "a.out-mips-big" : "a.out-mips-little";
121 case bfd_target_ecoff_flavour
:
122 return target_big_endian
? "ecoff-bigmips" : ECOFF_LITTLE_FORMAT
;
123 case bfd_target_coff_flavour
:
125 case bfd_target_elf_flavour
:
127 /* This is traditional mips */
128 return (target_big_endian
129 ? (mips_64
? "elf64-tradbigmips" : "elf32-tradbigmips")
130 : (mips_64
? "elf64-tradlittlemips" : "elf32-tradlittlemips"));
132 return (target_big_endian
133 ? (mips_64
? "elf64-bigmips" : "elf32-bigmips")
134 : (mips_64
? "elf64-littlemips" : "elf32-littlemips"));
142 /* The name of the readonly data section. */
143 #define RDATA_SECTION_NAME (OUTPUT_FLAVOR == bfd_target_aout_flavour \
145 : OUTPUT_FLAVOR == bfd_target_ecoff_flavour \
147 : OUTPUT_FLAVOR == bfd_target_coff_flavour \
149 : OUTPUT_FLAVOR == bfd_target_elf_flavour \
153 /* This is the set of options which may be modified by the .set
154 pseudo-op. We use a struct so that .set push and .set pop are more
157 struct mips_set_options
159 /* MIPS ISA (Instruction Set Architecture) level. This is set to -1
160 if it has not been initialized. Changed by `.set mipsN', and the
161 -mipsN command line option, and the default CPU. */
163 /* Whether we are assembling for the mips16 processor. 0 if we are
164 not, 1 if we are, and -1 if the value has not been initialized.
165 Changed by `.set mips16' and `.set nomips16', and the -mips16 and
166 -nomips16 command line options, and the default CPU. */
168 /* Non-zero if we should not reorder instructions. Changed by `.set
169 reorder' and `.set noreorder'. */
171 /* Non-zero if we should not permit the $at ($1) register to be used
172 in instructions. Changed by `.set at' and `.set noat'. */
174 /* Non-zero if we should warn when a macro instruction expands into
175 more than one machine instruction. Changed by `.set nomacro' and
177 int warn_about_macros
;
178 /* Non-zero if we should not move instructions. Changed by `.set
179 move', `.set volatile', `.set nomove', and `.set novolatile'. */
181 /* Non-zero if we should not optimize branches by moving the target
182 of the branch into the delay slot. Actually, we don't perform
183 this optimization anyhow. Changed by `.set bopt' and `.set
186 /* Non-zero if we should not autoextend mips16 instructions.
187 Changed by `.set autoextend' and `.set noautoextend'. */
191 /* This is the struct we use to hold the current set of options. Note
192 that we must set the isa field to ISA_UNKNOWN and the mips16 field to
193 -1 to indicate that they have not been initialized. */
195 static struct mips_set_options mips_opts
=
197 ISA_UNKNOWN
, -1, 0, 0, 0, 0, 0, 0
200 /* These variables are filled in with the masks of registers used.
201 The object format code reads them and puts them in the appropriate
203 unsigned long mips_gprmask
;
204 unsigned long mips_cprmask
[4];
206 /* MIPS ISA we are using for this output file. */
207 static int file_mips_isa
= ISA_UNKNOWN
;
209 /* The argument of the -mcpu= flag. Historical for code generation. */
210 static int mips_cpu
= CPU_UNKNOWN
;
212 /* The argument of the -march= flag. The architecture we are assembling. */
213 static int mips_arch
= CPU_UNKNOWN
;
215 /* The argument of the -mtune= flag. The architecture for which we
217 static int mips_tune
= CPU_UNKNOWN
;
219 /* The argument of the -mabi= flag. */
220 static char * mips_abi_string
= NULL
;
222 /* Whether we should mark the file EABI64 or EABI32. */
223 static int mips_eabi64
= 0;
225 /* If they asked for mips1 or mips2 and a cpu that is
226 mips3 or greater, then mark the object file 32BITMODE. */
227 static int mips_32bitmode
= 0;
229 /* True if -mgp32 was passed. */
230 static int mips_gp32
= 0;
232 /* True if -mfp32 was passed. */
233 static int mips_fp32
= 0;
235 /* True if the selected ABI is defined for 32-bit registers only. */
236 static int mips_32bit_abi
= 0;
238 /* Some ISA's have delay slots for instructions which read or write
239 from a coprocessor (eg. mips1-mips3); some don't (eg mips4).
240 Return true if instructions marked INSN_LOAD_COPROC_DELAY,
241 INSN_COPROC_MOVE_DELAY, or INSN_WRITE_COND_CODE actually have a
242 delay slot in this ISA. The uses of this macro assume that any
243 ISA that has delay slots for one of these, has them for all. They
244 also assume that ISAs which don't have delays for these insns, don't
245 have delays for the INSN_LOAD_MEMORY_DELAY instructions either. */
246 #define ISA_HAS_COPROC_DELAYS(ISA) ( \
248 || (ISA) == ISA_MIPS2 \
249 || (ISA) == ISA_MIPS3 \
252 /* Return true if ISA supports 64 bit gp register instructions. */
253 #define ISA_HAS_64BIT_REGS(ISA) ( \
255 || (ISA) == ISA_MIPS4 \
256 || (ISA) == ISA_MIPS5 \
257 || (ISA) == ISA_MIPS64 \
260 #define HAVE_32BIT_GPRS \
263 || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
265 #define HAVE_32BIT_FPRS \
268 || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
270 #define HAVE_64BIT_GPRS (! HAVE_32BIT_GPRS)
271 #define HAVE_64BIT_FPRS (! HAVE_32BIT_FPRS)
273 #define HAVE_32BIT_ADDRESSES \
275 || bfd_arch_bits_per_address (stdoutput) == 32)
277 /* Whether the processor uses hardware interlocks to protect
278 reads from the HI and LO registers, and thus does not
279 require nops to be inserted. */
281 #define hilo_interlocks (mips_arch == CPU_R4010 \
284 /* Whether the processor uses hardware interlocks to protect reads
285 from the GPRs, and thus does not require nops to be inserted. */
286 #define gpr_interlocks \
287 (mips_opts.isa != ISA_MIPS1 \
288 || mips_arch == CPU_R3900)
290 /* As with other "interlocks" this is used by hardware that has FP
291 (co-processor) interlocks. */
292 /* Itbl support may require additional care here. */
293 #define cop_interlocks (mips_arch == CPU_R4300 \
296 /* Is this a mfhi or mflo instruction? */
297 #define MF_HILO_INSN(PINFO) \
298 ((PINFO & INSN_READ_HI) || (PINFO & INSN_READ_LO))
300 /* MIPS PIC level. */
304 /* Do not generate PIC code. */
307 /* Generate PIC code as in Irix 4. This is not implemented, and I'm
308 not sure what it is supposed to do. */
311 /* Generate PIC code as in the SVR4 MIPS ABI. */
314 /* Generate PIC code without using a global offset table: the data
315 segment has a maximum size of 64K, all data references are off
316 the $gp register, and all text references are PC relative. This
317 is used on some embedded systems. */
321 static enum mips_pic_level mips_pic
;
323 /* Warn about all NOPS that the assembler generates. */
324 static int warn_nops
= 0;
326 /* 1 if we should generate 32 bit offsets from the GP register in
327 SVR4_PIC mode. Currently has no meaning in other modes. */
328 static int mips_big_got
;
330 /* 1 if trap instructions should used for overflow rather than break
332 static int mips_trap
;
334 /* 1 if double width floating point constants should not be constructed
335 by a assembling two single width halves into two single width floating
336 point registers which just happen to alias the double width destination
337 register. On some architectures this aliasing can be disabled by a bit
338 in the status register, and the setting of this bit cannot be determined
339 automatically at assemble time. */
340 static int mips_disable_float_construction
;
342 /* Non-zero if any .set noreorder directives were used. */
344 static int mips_any_noreorder
;
346 /* Non-zero if nops should be inserted when the register referenced in
347 an mfhi/mflo instruction is read in the next two instructions. */
348 static int mips_7000_hilo_fix
;
350 /* The size of the small data section. */
351 static unsigned int g_switch_value
= 8;
352 /* Whether the -G option was used. */
353 static int g_switch_seen
= 0;
358 /* If we can determine in advance that GP optimization won't be
359 possible, we can skip the relaxation stuff that tries to produce
360 GP-relative references. This makes delay slot optimization work
363 This function can only provide a guess, but it seems to work for
364 gcc output. It needs to guess right for gcc, otherwise gcc
365 will put what it thinks is a GP-relative instruction in a branch
368 I don't know if a fix is needed for the SVR4_PIC mode. I've only
369 fixed it for the non-PIC mode. KR 95/04/07 */
370 static int nopic_need_relax
PARAMS ((symbolS
*, int));
372 /* handle of the OPCODE hash table */
373 static struct hash_control
*op_hash
= NULL
;
375 /* The opcode hash table we use for the mips16. */
376 static struct hash_control
*mips16_op_hash
= NULL
;
378 /* This array holds the chars that always start a comment. If the
379 pre-processor is disabled, these aren't very useful */
380 const char comment_chars
[] = "#";
382 /* This array holds the chars that only start a comment at the beginning of
383 a line. If the line seems to have the form '# 123 filename'
384 .line and .file directives will appear in the pre-processed output */
385 /* Note that input_file.c hand checks for '#' at the beginning of the
386 first line of the input file. This is because the compiler outputs
387 #NO_APP at the beginning of its output. */
388 /* Also note that C style comments are always supported. */
389 const char line_comment_chars
[] = "#";
391 /* This array holds machine specific line separator characters. */
392 const char line_separator_chars
[] = ";";
394 /* Chars that can be used to separate mant from exp in floating point nums */
395 const char EXP_CHARS
[] = "eE";
397 /* Chars that mean this number is a floating point constant */
400 const char FLT_CHARS
[] = "rRsSfFdDxXpP";
402 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
403 changed in read.c . Ideally it shouldn't have to know about it at all,
404 but nothing is ideal around here.
407 static char *insn_error
;
409 static int auto_align
= 1;
411 /* When outputting SVR4 PIC code, the assembler needs to know the
412 offset in the stack frame from which to restore the $gp register.
413 This is set by the .cprestore pseudo-op, and saved in this
415 static offsetT mips_cprestore_offset
= -1;
417 /* This is the register which holds the stack frame, as set by the
418 .frame pseudo-op. This is needed to implement .cprestore. */
419 static int mips_frame_reg
= SP
;
421 /* To output NOP instructions correctly, we need to keep information
422 about the previous two instructions. */
424 /* Whether we are optimizing. The default value of 2 means to remove
425 unneeded NOPs and swap branch instructions when possible. A value
426 of 1 means to not swap branches. A value of 0 means to always
428 static int mips_optimize
= 2;
430 /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is
431 equivalent to seeing no -g option at all. */
432 static int mips_debug
= 0;
434 /* The previous instruction. */
435 static struct mips_cl_insn prev_insn
;
437 /* The instruction before prev_insn. */
438 static struct mips_cl_insn prev_prev_insn
;
440 /* If we don't want information for prev_insn or prev_prev_insn, we
441 point the insn_mo field at this dummy integer. */
442 static const struct mips_opcode dummy_opcode
= { NULL
, NULL
, 0, 0, 0, 0 };
444 /* Non-zero if prev_insn is valid. */
445 static int prev_insn_valid
;
447 /* The frag for the previous instruction. */
448 static struct frag
*prev_insn_frag
;
450 /* The offset into prev_insn_frag for the previous instruction. */
451 static long prev_insn_where
;
453 /* The reloc type for the previous instruction, if any. */
454 static bfd_reloc_code_real_type prev_insn_reloc_type
;
456 /* The reloc for the previous instruction, if any. */
457 static fixS
*prev_insn_fixp
;
459 /* Non-zero if the previous instruction was in a delay slot. */
460 static int prev_insn_is_delay_slot
;
462 /* Non-zero if the previous instruction was in a .set noreorder. */
463 static int prev_insn_unreordered
;
465 /* Non-zero if the previous instruction uses an extend opcode (if
467 static int prev_insn_extended
;
469 /* Non-zero if the previous previous instruction was in a .set
471 static int prev_prev_insn_unreordered
;
473 /* If this is set, it points to a frag holding nop instructions which
474 were inserted before the start of a noreorder section. If those
475 nops turn out to be unnecessary, the size of the frag can be
477 static fragS
*prev_nop_frag
;
479 /* The number of nop instructions we created in prev_nop_frag. */
480 static int prev_nop_frag_holds
;
482 /* The number of nop instructions that we know we need in
484 static int prev_nop_frag_required
;
486 /* The number of instructions we've seen since prev_nop_frag. */
487 static int prev_nop_frag_since
;
489 /* For ECOFF and ELF, relocations against symbols are done in two
490 parts, with a HI relocation and a LO relocation. Each relocation
491 has only 16 bits of space to store an addend. This means that in
492 order for the linker to handle carries correctly, it must be able
493 to locate both the HI and the LO relocation. This means that the
494 relocations must appear in order in the relocation table.
496 In order to implement this, we keep track of each unmatched HI
497 relocation. We then sort them so that they immediately precede the
498 corresponding LO relocation. */
503 struct mips_hi_fixup
*next
;
506 /* The section this fixup is in. */
510 /* The list of unmatched HI relocs. */
512 static struct mips_hi_fixup
*mips_hi_fixup_list
;
514 /* Map normal MIPS register numbers to mips16 register numbers. */
516 #define X ILLEGAL_REG
517 static const int mips32_to_16_reg_map
[] =
519 X
, X
, 2, 3, 4, 5, 6, 7,
520 X
, X
, X
, X
, X
, X
, X
, X
,
521 0, 1, X
, X
, X
, X
, X
, X
,
522 X
, X
, X
, X
, X
, X
, X
, X
526 /* Map mips16 register numbers to normal MIPS register numbers. */
528 static const unsigned int mips16_to_32_reg_map
[] =
530 16, 17, 2, 3, 4, 5, 6, 7
533 /* Since the MIPS does not have multiple forms of PC relative
534 instructions, we do not have to do relaxing as is done on other
535 platforms. However, we do have to handle GP relative addressing
536 correctly, which turns out to be a similar problem.
538 Every macro that refers to a symbol can occur in (at least) two
539 forms, one with GP relative addressing and one without. For
540 example, loading a global variable into a register generally uses
541 a macro instruction like this:
543 If i can be addressed off the GP register (this is true if it is in
544 the .sbss or .sdata section, or if it is known to be smaller than
545 the -G argument) this will generate the following instruction:
547 This instruction will use a GPREL reloc. If i can not be addressed
548 off the GP register, the following instruction sequence will be used:
551 In this case the first instruction will have a HI16 reloc, and the
552 second reloc will have a LO16 reloc. Both relocs will be against
555 The issue here is that we may not know whether i is GP addressable
556 until after we see the instruction that uses it. Therefore, we
557 want to be able to choose the final instruction sequence only at
558 the end of the assembly. This is similar to the way other
559 platforms choose the size of a PC relative instruction only at the
562 When generating position independent code we do not use GP
563 addressing in quite the same way, but the issue still arises as
564 external symbols and local symbols must be handled differently.
566 We handle these issues by actually generating both possible
567 instruction sequences. The longer one is put in a frag_var with
568 type rs_machine_dependent. We encode what to do with the frag in
569 the subtype field. We encode (1) the number of existing bytes to
570 replace, (2) the number of new bytes to use, (3) the offset from
571 the start of the existing bytes to the first reloc we must generate
572 (that is, the offset is applied from the start of the existing
573 bytes after they are replaced by the new bytes, if any), (4) the
574 offset from the start of the existing bytes to the second reloc,
575 (5) whether a third reloc is needed (the third reloc is always four
576 bytes after the second reloc), and (6) whether to warn if this
577 variant is used (this is sometimes needed if .set nomacro or .set
578 noat is in effect). All these numbers are reasonably small.
580 Generating two instruction sequences must be handled carefully to
581 ensure that delay slots are handled correctly. Fortunately, there
582 are a limited number of cases. When the second instruction
583 sequence is generated, append_insn is directed to maintain the
584 existing delay slot information, so it continues to apply to any
585 code after the second instruction sequence. This means that the
586 second instruction sequence must not impose any requirements not
587 required by the first instruction sequence.
589 These variant frags are then handled in functions called by the
590 machine independent code. md_estimate_size_before_relax returns
591 the final size of the frag. md_convert_frag sets up the final form
592 of the frag. tc_gen_reloc adjust the first reloc and adds a second
594 #define RELAX_ENCODE(old, new, reloc1, reloc2, reloc3, warn) \
598 | (((reloc1) + 64) << 9) \
599 | (((reloc2) + 64) << 2) \
600 | ((reloc3) ? (1 << 1) : 0) \
602 #define RELAX_OLD(i) (((i) >> 23) & 0x7f)
603 #define RELAX_NEW(i) (((i) >> 16) & 0x7f)
604 #define RELAX_RELOC1(i) ((valueT) (((i) >> 9) & 0x7f) - 64)
605 #define RELAX_RELOC2(i) ((valueT) (((i) >> 2) & 0x7f) - 64)
606 #define RELAX_RELOC3(i) (((i) >> 1) & 1)
607 #define RELAX_WARN(i) ((i) & 1)
609 /* For mips16 code, we use an entirely different form of relaxation.
610 mips16 supports two versions of most instructions which take
611 immediate values: a small one which takes some small value, and a
612 larger one which takes a 16 bit value. Since branches also follow
613 this pattern, relaxing these values is required.
615 We can assemble both mips16 and normal MIPS code in a single
616 object. Therefore, we need to support this type of relaxation at
617 the same time that we support the relaxation described above. We
618 use the high bit of the subtype field to distinguish these cases.
620 The information we store for this type of relaxation is the
621 argument code found in the opcode file for this relocation, whether
622 the user explicitly requested a small or extended form, and whether
623 the relocation is in a jump or jal delay slot. That tells us the
624 size of the value, and how it should be stored. We also store
625 whether the fragment is considered to be extended or not. We also
626 store whether this is known to be a branch to a different section,
627 whether we have tried to relax this frag yet, and whether we have
628 ever extended a PC relative fragment because of a shift count. */
629 #define RELAX_MIPS16_ENCODE(type, small, ext, dslot, jal_dslot) \
632 | ((small) ? 0x100 : 0) \
633 | ((ext) ? 0x200 : 0) \
634 | ((dslot) ? 0x400 : 0) \
635 | ((jal_dslot) ? 0x800 : 0))
636 #define RELAX_MIPS16_P(i) (((i) & 0x80000000) != 0)
637 #define RELAX_MIPS16_TYPE(i) ((i) & 0xff)
638 #define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x100) != 0)
639 #define RELAX_MIPS16_USER_EXT(i) (((i) & 0x200) != 0)
640 #define RELAX_MIPS16_DSLOT(i) (((i) & 0x400) != 0)
641 #define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x800) != 0)
642 #define RELAX_MIPS16_EXTENDED(i) (((i) & 0x1000) != 0)
643 #define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x1000)
644 #define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) &~ 0x1000)
645 #define RELAX_MIPS16_LONG_BRANCH(i) (((i) & 0x2000) != 0)
646 #define RELAX_MIPS16_MARK_LONG_BRANCH(i) ((i) | 0x2000)
647 #define RELAX_MIPS16_CLEAR_LONG_BRANCH(i) ((i) &~ 0x2000)
649 /* Prototypes for static functions. */
652 #define internalError() \
653 as_fatal (_("internal Error, line %d, %s"), __LINE__, __FILE__)
655 #define internalError() as_fatal (_("MIPS internal Error"));
658 enum mips_regclass
{ MIPS_GR_REG
, MIPS_FP_REG
, MIPS16_REG
};
660 static int insn_uses_reg
PARAMS ((struct mips_cl_insn
*ip
,
661 unsigned int reg
, enum mips_regclass
class));
662 static int reg_needs_delay
PARAMS ((unsigned int));
663 static void mips16_mark_labels
PARAMS ((void));
664 static void append_insn
PARAMS ((char *place
,
665 struct mips_cl_insn
* ip
,
667 bfd_reloc_code_real_type r
,
669 static void mips_no_prev_insn
PARAMS ((int));
670 static void mips_emit_delays
PARAMS ((boolean
));
672 static void macro_build
PARAMS ((char *place
, int *counter
, expressionS
* ep
,
673 const char *name
, const char *fmt
,
676 static void macro_build ();
678 static void mips16_macro_build
PARAMS ((char *, int *, expressionS
*,
679 const char *, const char *,
681 static void macro_build_lui
PARAMS ((char *place
, int *counter
,
682 expressionS
* ep
, int regnum
));
683 static void set_at
PARAMS ((int *counter
, int reg
, int unsignedp
));
684 static void check_absolute_expr
PARAMS ((struct mips_cl_insn
* ip
,
686 static void load_register
PARAMS ((int *, int, expressionS
*, int));
687 static void load_address
PARAMS ((int *counter
, int reg
, expressionS
*ep
));
688 static void move_register
PARAMS ((int *, int, int));
689 static void macro
PARAMS ((struct mips_cl_insn
* ip
));
690 static void mips16_macro
PARAMS ((struct mips_cl_insn
* ip
));
691 #ifdef LOSING_COMPILER
692 static void macro2
PARAMS ((struct mips_cl_insn
* ip
));
694 static void mips_ip
PARAMS ((char *str
, struct mips_cl_insn
* ip
));
695 static void mips16_ip
PARAMS ((char *str
, struct mips_cl_insn
* ip
));
696 static void mips16_immed
PARAMS ((char *, unsigned int, int, offsetT
, boolean
,
697 boolean
, boolean
, unsigned long *,
698 boolean
*, unsigned short *));
699 static int my_getSmallExpression
PARAMS ((expressionS
* ep
, char *str
));
700 static void my_getExpression
PARAMS ((expressionS
* ep
, char *str
));
701 static symbolS
*get_symbol
PARAMS ((void));
702 static void mips_align
PARAMS ((int to
, int fill
, symbolS
*label
));
703 static void s_align
PARAMS ((int));
704 static void s_change_sec
PARAMS ((int));
705 static void s_cons
PARAMS ((int));
706 static void s_float_cons
PARAMS ((int));
707 static void s_mips_globl
PARAMS ((int));
708 static void s_option
PARAMS ((int));
709 static void s_mipsset
PARAMS ((int));
710 static void s_abicalls
PARAMS ((int));
711 static void s_cpload
PARAMS ((int));
712 static void s_cprestore
PARAMS ((int));
713 static void s_gpword
PARAMS ((int));
714 static void s_cpadd
PARAMS ((int));
715 static void s_insn
PARAMS ((int));
716 static void md_obj_begin
PARAMS ((void));
717 static void md_obj_end
PARAMS ((void));
718 static long get_number
PARAMS ((void));
719 static void s_mips_ent
PARAMS ((int));
720 static void s_mips_end
PARAMS ((int));
721 static void s_mips_frame
PARAMS ((int));
722 static void s_mips_mask
PARAMS ((int));
723 static void s_mips_stab
PARAMS ((int));
724 static void s_mips_weakext
PARAMS ((int));
725 static void s_file
PARAMS ((int));
726 static int mips16_extended_frag
PARAMS ((fragS
*, asection
*, long));
727 static const char *mips_isa_to_str
PARAMS ((int));
728 static const char *mips_cpu_to_str
PARAMS ((int));
729 static int validate_mips_insn
PARAMS ((const struct mips_opcode
*));
731 /* Table and functions used to map between CPU/ISA names, and
732 ISA levels, and CPU numbers. */
736 const char *name
; /* CPU or ISA name. */
737 int is_isa
; /* Is this an ISA? (If 0, a CPU.) */
738 int isa
; /* ISA level. */
739 int cpu
; /* CPU number (default CPU if ISA). */
742 static const struct mips_cpu_info
*mips_cpu_info_from_name
PARAMS ((const char *));
743 static const struct mips_cpu_info
*mips_cpu_info_from_isa
PARAMS ((int));
744 static const struct mips_cpu_info
*mips_cpu_info_from_cpu
PARAMS ((int));
748 The following pseudo-ops from the Kane and Heinrich MIPS book
749 should be defined here, but are currently unsupported: .alias,
750 .galive, .gjaldef, .gjrlive, .livereg, .noalias.
752 The following pseudo-ops from the Kane and Heinrich MIPS book are
753 specific to the type of debugging information being generated, and
754 should be defined by the object format: .aent, .begin, .bend,
755 .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp,
758 The following pseudo-ops from the Kane and Heinrich MIPS book are
759 not MIPS CPU specific, but are also not specific to the object file
760 format. This file is probably the best place to define them, but
761 they are not currently supported: .asm0, .endr, .lab, .repeat,
764 static const pseudo_typeS mips_pseudo_table
[] =
766 /* MIPS specific pseudo-ops. */
767 {"option", s_option
, 0},
768 {"set", s_mipsset
, 0},
769 {"rdata", s_change_sec
, 'r'},
770 {"sdata", s_change_sec
, 's'},
771 {"livereg", s_ignore
, 0},
772 {"abicalls", s_abicalls
, 0},
773 {"cpload", s_cpload
, 0},
774 {"cprestore", s_cprestore
, 0},
775 {"gpword", s_gpword
, 0},
776 {"cpadd", s_cpadd
, 0},
779 /* Relatively generic pseudo-ops that happen to be used on MIPS
781 {"asciiz", stringer
, 1},
782 {"bss", s_change_sec
, 'b'},
785 {"dword", s_cons
, 3},
786 {"weakext", s_mips_weakext
, 0},
788 /* These pseudo-ops are defined in read.c, but must be overridden
789 here for one reason or another. */
790 {"align", s_align
, 0},
792 {"data", s_change_sec
, 'd'},
793 {"double", s_float_cons
, 'd'},
794 {"float", s_float_cons
, 'f'},
795 {"globl", s_mips_globl
, 0},
796 {"global", s_mips_globl
, 0},
797 {"hword", s_cons
, 1},
802 {"short", s_cons
, 1},
803 {"single", s_float_cons
, 'f'},
804 {"stabn", s_mips_stab
, 'n'},
805 {"text", s_change_sec
, 't'},
808 #ifdef MIPS_STABS_ELF
809 { "extern", ecoff_directive_extern
, 0},
815 static const pseudo_typeS mips_nonecoff_pseudo_table
[] =
817 /* These pseudo-ops should be defined by the object file format.
818 However, a.out doesn't support them, so we have versions here. */
819 {"aent", s_mips_ent
, 1},
820 {"bgnb", s_ignore
, 0},
821 {"end", s_mips_end
, 0},
822 {"endb", s_ignore
, 0},
823 {"ent", s_mips_ent
, 0},
825 {"fmask", s_mips_mask
, 'F'},
826 {"frame", s_mips_frame
, 0},
827 {"loc", s_ignore
, 0},
828 {"mask", s_mips_mask
, 'R'},
829 {"verstamp", s_ignore
, 0},
833 extern void pop_insert
PARAMS ((const pseudo_typeS
*));
838 pop_insert (mips_pseudo_table
);
839 if (! ECOFF_DEBUGGING
)
840 pop_insert (mips_nonecoff_pseudo_table
);
843 /* Symbols labelling the current insn. */
845 struct insn_label_list
847 struct insn_label_list
*next
;
851 static struct insn_label_list
*insn_labels
;
852 static struct insn_label_list
*free_insn_labels
;
854 static void mips_clear_insn_labels
PARAMS ((void));
857 mips_clear_insn_labels ()
859 register struct insn_label_list
**pl
;
861 for (pl
= &free_insn_labels
; *pl
!= NULL
; pl
= &(*pl
)->next
)
867 static char *expr_end
;
869 /* Expressions which appear in instructions. These are set by
872 static expressionS imm_expr
;
873 static expressionS offset_expr
;
875 /* Relocs associated with imm_expr and offset_expr. */
877 static bfd_reloc_code_real_type imm_reloc
;
878 static bfd_reloc_code_real_type offset_reloc
;
880 /* This is set by mips_ip if imm_reloc is an unmatched HI16_S reloc. */
882 static boolean imm_unmatched_hi
;
884 /* These are set by mips16_ip if an explicit extension is used. */
886 static boolean mips16_small
, mips16_ext
;
888 #ifdef MIPS_STABS_ELF
889 /* The pdr segment for per procedure frame/regmask info */
895 mips_isa_to_str (isa
)
898 const struct mips_cpu_info
*ci
;
901 ci
= mips_cpu_info_from_isa (isa
);
905 sprintf (s
, "ISA#%d", isa
);
910 mips_cpu_to_str (cpu
)
913 const struct mips_cpu_info
*ci
;
916 ci
= mips_cpu_info_from_cpu (cpu
);
920 sprintf (s
, "CPU#%d", cpu
);
924 /* This function is called once, at assembler startup time. It should
925 set up all the tables, etc. that the MD part of the assembler will need. */
930 register const char *retval
= NULL
;
935 int mips_isa_from_cpu
;
936 int target_cpu_had_mips16
= 0;
937 const struct mips_cpu_info
*ci
;
939 /* GP relative stuff not working for PE */
940 if (strncmp (TARGET_OS
, "pe", 2) == 0
941 && g_switch_value
!= 0)
944 as_bad (_("-G not supported in this configuration."));
949 if (strcmp (cpu
+ (sizeof TARGET_CPU
) - 3, "el") == 0)
951 a
= xmalloc (sizeof TARGET_CPU
);
952 strcpy (a
, TARGET_CPU
);
953 a
[(sizeof TARGET_CPU
) - 3] = '\0';
957 if (strncmp (cpu
, "mips16", sizeof "mips16" - 1) == 0)
959 target_cpu_had_mips16
= 1;
960 cpu
+= sizeof "mips16" - 1;
963 if (mips_opts
.mips16
< 0)
964 mips_opts
.mips16
= target_cpu_had_mips16
;
966 /* Backward compatibility for historic -mcpu= option. Check for
967 incompatible options, warn if -mcpu is used. */
968 if (mips_cpu
!= CPU_UNKNOWN
969 && mips_arch
!= CPU_UNKNOWN
970 && mips_cpu
!= mips_arch
)
972 as_fatal (_("The -mcpu option can't be used together with -march. "
973 "Use -mtune instead of -mcpu."));
976 if (mips_cpu
!= CPU_UNKNOWN
977 && mips_tune
!= CPU_UNKNOWN
978 && mips_cpu
!= mips_tune
)
980 as_fatal (_("The -mcpu option can't be used together with -mtune. "
981 "Use -march instead of -mcpu."));
984 if (mips_arch
== CPU_UNKNOWN
&& mips_cpu
!= CPU_UNKNOWN
)
986 ci
= mips_cpu_info_from_cpu (mips_cpu
);
989 as_warn (_("The -mcpu option is deprecated. Please use -march and "
993 /* At this point, mips_arch will either be CPU_UNKNOWN if no ARCH was
994 specified on the command line, or some other value if one was.
995 Similarly, mips_opts.isa will be ISA_UNKNOWN if not specified on
996 the command line, or will be set otherwise if one was. */
997 if (mips_arch
!= CPU_UNKNOWN
&& mips_opts
.isa
!= ISA_UNKNOWN
)
999 /* We have it all. There's nothing to do. */
1001 else if (mips_arch
!= CPU_UNKNOWN
&& mips_opts
.isa
== ISA_UNKNOWN
)
1003 /* We have ARCH, we need ISA. */
1004 ci
= mips_cpu_info_from_cpu (mips_arch
);
1005 assert (ci
!= NULL
);
1006 mips_opts
.isa
= ci
->isa
;
1008 else if (mips_arch
== CPU_UNKNOWN
&& mips_opts
.isa
!= ISA_UNKNOWN
)
1010 /* We have ISA, we need default ARCH. */
1011 ci
= mips_cpu_info_from_isa (mips_opts
.isa
);
1012 assert (ci
!= NULL
);
1013 mips_arch
= ci
->cpu
;
1017 /* We need to set both ISA and ARCH from target cpu. */
1018 ci
= mips_cpu_info_from_name (cpu
);
1020 ci
= mips_cpu_info_from_cpu (CPU_R3000
);
1021 assert (ci
!= NULL
);
1022 mips_opts
.isa
= ci
->isa
;
1023 mips_arch
= ci
->cpu
;
1026 if (mips_tune
== CPU_UNKNOWN
)
1027 mips_tune
= mips_arch
;
1029 ci
= mips_cpu_info_from_cpu (mips_arch
);
1030 assert (ci
!= NULL
);
1031 mips_isa_from_cpu
= ci
->isa
;
1033 /* End of TARGET_CPU processing, get rid of malloced memory
1042 if (mips_opts
.isa
== ISA_MIPS1
&& mips_trap
)
1043 as_bad (_("trap exception not supported at ISA 1"));
1045 /* Set the EABI kind based on the ISA before the user gets
1046 to change the ISA with directives. This isn't really
1047 the best, but then neither is basing the abi on the isa. */
1048 if (ISA_HAS_64BIT_REGS (mips_opts
.isa
)
1050 && 0 == strcmp (mips_abi_string
, "eabi"))
1053 /* If they asked for mips1 or mips2 and a cpu that is
1054 mips3 or greater, then mark the object file 32BITMODE. */
1055 if (mips_isa_from_cpu
!= ISA_UNKNOWN
1056 && ! ISA_HAS_64BIT_REGS (mips_opts
.isa
)
1057 && ISA_HAS_64BIT_REGS (mips_isa_from_cpu
))
1060 if (! bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, mips_arch
))
1061 as_warn (_("Could not set architecture and machine"));
1063 file_mips_isa
= mips_opts
.isa
;
1065 op_hash
= hash_new ();
1067 for (i
= 0; i
< NUMOPCODES
;)
1069 const char *name
= mips_opcodes
[i
].name
;
1071 retval
= hash_insert (op_hash
, name
, (PTR
) &mips_opcodes
[i
]);
1074 fprintf (stderr
, _("internal error: can't hash `%s': %s\n"),
1075 mips_opcodes
[i
].name
, retval
);
1076 /* Probably a memory allocation problem? Give up now. */
1077 as_fatal (_("Broken assembler. No assembly attempted."));
1081 if (mips_opcodes
[i
].pinfo
!= INSN_MACRO
)
1083 if (!validate_mips_insn (&mips_opcodes
[i
]))
1088 while ((i
< NUMOPCODES
) && !strcmp (mips_opcodes
[i
].name
, name
));
1091 mips16_op_hash
= hash_new ();
1094 while (i
< bfd_mips16_num_opcodes
)
1096 const char *name
= mips16_opcodes
[i
].name
;
1098 retval
= hash_insert (mips16_op_hash
, name
, (PTR
) &mips16_opcodes
[i
]);
1100 as_fatal (_("internal: can't hash `%s': %s"),
1101 mips16_opcodes
[i
].name
, retval
);
1104 if (mips16_opcodes
[i
].pinfo
!= INSN_MACRO
1105 && ((mips16_opcodes
[i
].match
& mips16_opcodes
[i
].mask
)
1106 != mips16_opcodes
[i
].match
))
1108 fprintf (stderr
, _("internal error: bad mips16 opcode: %s %s\n"),
1109 mips16_opcodes
[i
].name
, mips16_opcodes
[i
].args
);
1114 while (i
< bfd_mips16_num_opcodes
1115 && strcmp (mips16_opcodes
[i
].name
, name
) == 0);
1119 as_fatal (_("Broken assembler. No assembly attempted."));
1121 /* We add all the general register names to the symbol table. This
1122 helps us detect invalid uses of them. */
1123 for (i
= 0; i
< 32; i
++)
1127 sprintf (buf
, "$%d", i
);
1128 symbol_table_insert (symbol_new (buf
, reg_section
, i
,
1129 &zero_address_frag
));
1131 symbol_table_insert (symbol_new ("$fp", reg_section
, FP
,
1132 &zero_address_frag
));
1133 symbol_table_insert (symbol_new ("$sp", reg_section
, SP
,
1134 &zero_address_frag
));
1135 symbol_table_insert (symbol_new ("$gp", reg_section
, GP
,
1136 &zero_address_frag
));
1137 symbol_table_insert (symbol_new ("$at", reg_section
, AT
,
1138 &zero_address_frag
));
1139 symbol_table_insert (symbol_new ("$kt0", reg_section
, KT0
,
1140 &zero_address_frag
));
1141 symbol_table_insert (symbol_new ("$kt1", reg_section
, KT1
,
1142 &zero_address_frag
));
1143 symbol_table_insert (symbol_new ("$pc", reg_section
, -1,
1144 &zero_address_frag
));
1146 mips_no_prev_insn (false);
1149 mips_cprmask
[0] = 0;
1150 mips_cprmask
[1] = 0;
1151 mips_cprmask
[2] = 0;
1152 mips_cprmask
[3] = 0;
1154 /* set the default alignment for the text section (2**2) */
1155 record_alignment (text_section
, 2);
1157 if (USE_GLOBAL_POINTER_OPT
)
1158 bfd_set_gp_size (stdoutput
, g_switch_value
);
1160 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
1162 /* On a native system, sections must be aligned to 16 byte
1163 boundaries. When configured for an embedded ELF target, we
1165 if (strcmp (TARGET_OS
, "elf") != 0)
1167 (void) bfd_set_section_alignment (stdoutput
, text_section
, 4);
1168 (void) bfd_set_section_alignment (stdoutput
, data_section
, 4);
1169 (void) bfd_set_section_alignment (stdoutput
, bss_section
, 4);
1172 /* Create a .reginfo section for register masks and a .mdebug
1173 section for debugging information. */
1181 subseg
= now_subseg
;
1183 /* The ABI says this section should be loaded so that the
1184 running program can access it. However, we don't load it
1185 if we are configured for an embedded target */
1186 flags
= SEC_READONLY
| SEC_DATA
;
1187 if (strcmp (TARGET_OS
, "elf") != 0)
1188 flags
|= SEC_ALLOC
| SEC_LOAD
;
1192 sec
= subseg_new (".reginfo", (subsegT
) 0);
1194 (void) bfd_set_section_flags (stdoutput
, sec
, flags
);
1195 (void) bfd_set_section_alignment (stdoutput
, sec
, 2);
1198 mips_regmask_frag
= frag_more (sizeof (Elf32_External_RegInfo
));
1203 /* The 64-bit ABI uses a .MIPS.options section rather than
1204 .reginfo section. */
1205 sec
= subseg_new (".MIPS.options", (subsegT
) 0);
1206 (void) bfd_set_section_flags (stdoutput
, sec
, flags
);
1207 (void) bfd_set_section_alignment (stdoutput
, sec
, 3);
1210 /* Set up the option header. */
1212 Elf_Internal_Options opthdr
;
1215 opthdr
.kind
= ODK_REGINFO
;
1216 opthdr
.size
= (sizeof (Elf_External_Options
)
1217 + sizeof (Elf64_External_RegInfo
));
1220 f
= frag_more (sizeof (Elf_External_Options
));
1221 bfd_mips_elf_swap_options_out (stdoutput
, &opthdr
,
1222 (Elf_External_Options
*) f
);
1224 mips_regmask_frag
= frag_more (sizeof (Elf64_External_RegInfo
));
1229 if (ECOFF_DEBUGGING
)
1231 sec
= subseg_new (".mdebug", (subsegT
) 0);
1232 (void) bfd_set_section_flags (stdoutput
, sec
,
1233 SEC_HAS_CONTENTS
| SEC_READONLY
);
1234 (void) bfd_set_section_alignment (stdoutput
, sec
, 2);
1237 #ifdef MIPS_STABS_ELF
1238 pdr_seg
= subseg_new (".pdr", (subsegT
) 0);
1239 (void) bfd_set_section_flags (stdoutput
, pdr_seg
,
1240 SEC_READONLY
| SEC_RELOC
| SEC_DEBUGGING
);
1241 (void) bfd_set_section_alignment (stdoutput
, pdr_seg
, 2);
1244 subseg_set (seg
, subseg
);
1248 if (! ECOFF_DEBUGGING
)
1255 if (! ECOFF_DEBUGGING
)
1263 struct mips_cl_insn insn
;
1265 imm_expr
.X_op
= O_absent
;
1266 imm_reloc
= BFD_RELOC_UNUSED
;
1267 imm_unmatched_hi
= false;
1268 offset_expr
.X_op
= O_absent
;
1269 offset_reloc
= BFD_RELOC_UNUSED
;
1271 if (mips_opts
.mips16
)
1272 mips16_ip (str
, &insn
);
1275 mips_ip (str
, &insn
);
1276 DBG ((_("returned from mips_ip(%s) insn_opcode = 0x%x\n"),
1277 str
, insn
.insn_opcode
));
1282 as_bad ("%s `%s'", insn_error
, str
);
1286 if (insn
.insn_mo
->pinfo
== INSN_MACRO
)
1288 if (mips_opts
.mips16
)
1289 mips16_macro (&insn
);
1295 if (imm_expr
.X_op
!= O_absent
)
1296 append_insn ((char *) NULL
, &insn
, &imm_expr
, imm_reloc
,
1298 else if (offset_expr
.X_op
!= O_absent
)
1299 append_insn ((char *) NULL
, &insn
, &offset_expr
, offset_reloc
, false);
1301 append_insn ((char *) NULL
, &insn
, NULL
, BFD_RELOC_UNUSED
, false);
1305 /* See whether instruction IP reads register REG. CLASS is the type
1309 insn_uses_reg (ip
, reg
, class)
1310 struct mips_cl_insn
*ip
;
1312 enum mips_regclass
class;
1314 if (class == MIPS16_REG
)
1316 assert (mips_opts
.mips16
);
1317 reg
= mips16_to_32_reg_map
[reg
];
1318 class = MIPS_GR_REG
;
1321 /* Don't report on general register 0, since it never changes. */
1322 if (class == MIPS_GR_REG
&& reg
== 0)
1325 if (class == MIPS_FP_REG
)
1327 assert (! mips_opts
.mips16
);
1328 /* If we are called with either $f0 or $f1, we must check $f0.
1329 This is not optimal, because it will introduce an unnecessary
1330 NOP between "lwc1 $f0" and "swc1 $f1". To fix this we would
1331 need to distinguish reading both $f0 and $f1 or just one of
1332 them. Note that we don't have to check the other way,
1333 because there is no instruction that sets both $f0 and $f1
1334 and requires a delay. */
1335 if ((ip
->insn_mo
->pinfo
& INSN_READ_FPR_S
)
1336 && ((((ip
->insn_opcode
>> OP_SH_FS
) & OP_MASK_FS
) &~(unsigned)1)
1337 == (reg
&~ (unsigned) 1)))
1339 if ((ip
->insn_mo
->pinfo
& INSN_READ_FPR_T
)
1340 && ((((ip
->insn_opcode
>> OP_SH_FT
) & OP_MASK_FT
) &~(unsigned)1)
1341 == (reg
&~ (unsigned) 1)))
1344 else if (! mips_opts
.mips16
)
1346 if ((ip
->insn_mo
->pinfo
& INSN_READ_GPR_S
)
1347 && ((ip
->insn_opcode
>> OP_SH_RS
) & OP_MASK_RS
) == reg
)
1349 if ((ip
->insn_mo
->pinfo
& INSN_READ_GPR_T
)
1350 && ((ip
->insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
) == reg
)
1355 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_X
)
1356 && (mips16_to_32_reg_map
[((ip
->insn_opcode
>> MIPS16OP_SH_RX
)
1357 & MIPS16OP_MASK_RX
)]
1360 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_Y
)
1361 && (mips16_to_32_reg_map
[((ip
->insn_opcode
>> MIPS16OP_SH_RY
)
1362 & MIPS16OP_MASK_RY
)]
1365 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_Z
)
1366 && (mips16_to_32_reg_map
[((ip
->insn_opcode
>> MIPS16OP_SH_MOVE32Z
)
1367 & MIPS16OP_MASK_MOVE32Z
)]
1370 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_T
) && reg
== TREG
)
1372 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_SP
) && reg
== SP
)
1374 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_31
) && reg
== RA
)
1376 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_GPR_X
)
1377 && ((ip
->insn_opcode
>> MIPS16OP_SH_REGR32
)
1378 & MIPS16OP_MASK_REGR32
) == reg
)
1385 /* This function returns true if modifying a register requires a
1389 reg_needs_delay (reg
)
1392 unsigned long prev_pinfo
;
1394 prev_pinfo
= prev_insn
.insn_mo
->pinfo
;
1395 if (! mips_opts
.noreorder
1396 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
1397 && ((prev_pinfo
& INSN_LOAD_COPROC_DELAY
)
1398 || (! gpr_interlocks
1399 && (prev_pinfo
& INSN_LOAD_MEMORY_DELAY
))))
1401 /* A load from a coprocessor or from memory. All load
1402 delays delay the use of general register rt for one
1403 instruction on the r3000. The r6000 and r4000 use
1405 /* Itbl support may require additional care here. */
1406 know (prev_pinfo
& INSN_WRITE_GPR_T
);
1407 if (reg
== ((prev_insn
.insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
))
1414 /* Mark instruction labels in mips16 mode. This permits the linker to
1415 handle them specially, such as generating jalx instructions when
1416 needed. We also make them odd for the duration of the assembly, in
1417 order to generate the right sort of code. We will make them even
1418 in the adjust_symtab routine, while leaving them marked. This is
1419 convenient for the debugger and the disassembler. The linker knows
1420 to make them odd again. */
1423 mips16_mark_labels ()
1425 if (mips_opts
.mips16
)
1427 struct insn_label_list
*l
;
1430 for (l
= insn_labels
; l
!= NULL
; l
= l
->next
)
1433 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
1434 S_SET_OTHER (l
->label
, STO_MIPS16
);
1436 val
= S_GET_VALUE (l
->label
);
1438 S_SET_VALUE (l
->label
, val
+ 1);
1443 /* Output an instruction. PLACE is where to put the instruction; if
1444 it is NULL, this uses frag_more to get room. IP is the instruction
1445 information. ADDRESS_EXPR is an operand of the instruction to be
1446 used with RELOC_TYPE. */
1449 append_insn (place
, ip
, address_expr
, reloc_type
, unmatched_hi
)
1451 struct mips_cl_insn
*ip
;
1452 expressionS
*address_expr
;
1453 bfd_reloc_code_real_type reloc_type
;
1454 boolean unmatched_hi
;
1456 register unsigned long prev_pinfo
, pinfo
;
1461 /* Mark instruction labels in mips16 mode. */
1462 if (mips_opts
.mips16
)
1463 mips16_mark_labels ();
1465 prev_pinfo
= prev_insn
.insn_mo
->pinfo
;
1466 pinfo
= ip
->insn_mo
->pinfo
;
1468 if (place
== NULL
&& (! mips_opts
.noreorder
|| prev_nop_frag
!= NULL
))
1472 /* If the previous insn required any delay slots, see if we need
1473 to insert a NOP or two. There are eight kinds of possible
1474 hazards, of which an instruction can have at most one type.
1475 (1) a load from memory delay
1476 (2) a load from a coprocessor delay
1477 (3) an unconditional branch delay
1478 (4) a conditional branch delay
1479 (5) a move to coprocessor register delay
1480 (6) a load coprocessor register from memory delay
1481 (7) a coprocessor condition code delay
1482 (8) a HI/LO special register delay
1484 There are a lot of optimizations we could do that we don't.
1485 In particular, we do not, in general, reorder instructions.
1486 If you use gcc with optimization, it will reorder
1487 instructions and generally do much more optimization then we
1488 do here; repeating all that work in the assembler would only
1489 benefit hand written assembly code, and does not seem worth
1492 /* This is how a NOP is emitted. */
1493 #define emit_nop() \
1495 ? md_number_to_chars (frag_more (2), 0x6500, 2) \
1496 : md_number_to_chars (frag_more (4), 0, 4))
1498 /* The previous insn might require a delay slot, depending upon
1499 the contents of the current insn. */
1500 if (! mips_opts
.mips16
1501 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
1502 && (((prev_pinfo
& INSN_LOAD_COPROC_DELAY
)
1503 && ! cop_interlocks
)
1504 || (! gpr_interlocks
1505 && (prev_pinfo
& INSN_LOAD_MEMORY_DELAY
))))
1507 /* A load from a coprocessor or from memory. All load
1508 delays delay the use of general register rt for one
1509 instruction on the r3000. The r6000 and r4000 use
1511 /* Itbl support may require additional care here. */
1512 know (prev_pinfo
& INSN_WRITE_GPR_T
);
1513 if (mips_optimize
== 0
1514 || insn_uses_reg (ip
,
1515 ((prev_insn
.insn_opcode
>> OP_SH_RT
)
1520 else if (! mips_opts
.mips16
1521 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
1522 && (((prev_pinfo
& INSN_COPROC_MOVE_DELAY
)
1523 && ! cop_interlocks
)
1524 || (mips_opts
.isa
== ISA_MIPS1
1525 && (prev_pinfo
& INSN_COPROC_MEMORY_DELAY
))))
1527 /* A generic coprocessor delay. The previous instruction
1528 modified a coprocessor general or control register. If
1529 it modified a control register, we need to avoid any
1530 coprocessor instruction (this is probably not always
1531 required, but it sometimes is). If it modified a general
1532 register, we avoid using that register.
1534 On the r6000 and r4000 loading a coprocessor register
1535 from memory is interlocked, and does not require a delay.
1537 This case is not handled very well. There is no special
1538 knowledge of CP0 handling, and the coprocessors other
1539 than the floating point unit are not distinguished at
1541 /* Itbl support may require additional care here. FIXME!
1542 Need to modify this to include knowledge about
1543 user specified delays! */
1544 if (prev_pinfo
& INSN_WRITE_FPR_T
)
1546 if (mips_optimize
== 0
1547 || insn_uses_reg (ip
,
1548 ((prev_insn
.insn_opcode
>> OP_SH_FT
)
1553 else if (prev_pinfo
& INSN_WRITE_FPR_S
)
1555 if (mips_optimize
== 0
1556 || insn_uses_reg (ip
,
1557 ((prev_insn
.insn_opcode
>> OP_SH_FS
)
1564 /* We don't know exactly what the previous instruction
1565 does. If the current instruction uses a coprocessor
1566 register, we must insert a NOP. If previous
1567 instruction may set the condition codes, and the
1568 current instruction uses them, we must insert two
1570 /* Itbl support may require additional care here. */
1571 if (mips_optimize
== 0
1572 || ((prev_pinfo
& INSN_WRITE_COND_CODE
)
1573 && (pinfo
& INSN_READ_COND_CODE
)))
1575 else if (pinfo
& INSN_COP
)
1579 else if (! mips_opts
.mips16
1580 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
1581 && (prev_pinfo
& INSN_WRITE_COND_CODE
)
1582 && ! cop_interlocks
)
1584 /* The previous instruction sets the coprocessor condition
1585 codes, but does not require a general coprocessor delay
1586 (this means it is a floating point comparison
1587 instruction). If this instruction uses the condition
1588 codes, we need to insert a single NOP. */
1589 /* Itbl support may require additional care here. */
1590 if (mips_optimize
== 0
1591 || (pinfo
& INSN_READ_COND_CODE
))
1595 /* If we're fixing up mfhi/mflo for the r7000 and the
1596 previous insn was an mfhi/mflo and the current insn
1597 reads the register that the mfhi/mflo wrote to, then
1600 else if (mips_7000_hilo_fix
1601 && MF_HILO_INSN (prev_pinfo
)
1602 && insn_uses_reg (ip
, ((prev_insn
.insn_opcode
>> OP_SH_RD
)
1609 /* If we're fixing up mfhi/mflo for the r7000 and the
1610 2nd previous insn was an mfhi/mflo and the current insn
1611 reads the register that the mfhi/mflo wrote to, then
1614 else if (mips_7000_hilo_fix
1615 && MF_HILO_INSN (prev_prev_insn
.insn_opcode
)
1616 && insn_uses_reg (ip
, ((prev_prev_insn
.insn_opcode
>> OP_SH_RD
)
1624 else if (prev_pinfo
& INSN_READ_LO
)
1626 /* The previous instruction reads the LO register; if the
1627 current instruction writes to the LO register, we must
1628 insert two NOPS. Some newer processors have interlocks.
1629 Also the tx39's multiply instructions can be exectuted
1630 immediatly after a read from HI/LO (without the delay),
1631 though the tx39's divide insns still do require the
1633 if (! (hilo_interlocks
1634 || (mips_tune
== CPU_R3900
&& (pinfo
& INSN_MULT
)))
1635 && (mips_optimize
== 0
1636 || (pinfo
& INSN_WRITE_LO
)))
1638 /* Most mips16 branch insns don't have a delay slot.
1639 If a read from LO is immediately followed by a branch
1640 to a write to LO we have a read followed by a write
1641 less than 2 insns away. We assume the target of
1642 a branch might be a write to LO, and insert a nop
1643 between a read and an immediately following branch. */
1644 else if (mips_opts
.mips16
1645 && (mips_optimize
== 0
1646 || (pinfo
& MIPS16_INSN_BRANCH
)))
1649 else if (prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
1651 /* The previous instruction reads the HI register; if the
1652 current instruction writes to the HI register, we must
1653 insert a NOP. Some newer processors have interlocks.
1654 Also the note tx39's multiply above. */
1655 if (! (hilo_interlocks
1656 || (mips_tune
== CPU_R3900
&& (pinfo
& INSN_MULT
)))
1657 && (mips_optimize
== 0
1658 || (pinfo
& INSN_WRITE_HI
)))
1660 /* Most mips16 branch insns don't have a delay slot.
1661 If a read from HI is immediately followed by a branch
1662 to a write to HI we have a read followed by a write
1663 less than 2 insns away. We assume the target of
1664 a branch might be a write to HI, and insert a nop
1665 between a read and an immediately following branch. */
1666 else if (mips_opts
.mips16
1667 && (mips_optimize
== 0
1668 || (pinfo
& MIPS16_INSN_BRANCH
)))
1672 /* If the previous instruction was in a noreorder section, then
1673 we don't want to insert the nop after all. */
1674 /* Itbl support may require additional care here. */
1675 if (prev_insn_unreordered
)
1678 /* There are two cases which require two intervening
1679 instructions: 1) setting the condition codes using a move to
1680 coprocessor instruction which requires a general coprocessor
1681 delay and then reading the condition codes 2) reading the HI
1682 or LO register and then writing to it (except on processors
1683 which have interlocks). If we are not already emitting a NOP
1684 instruction, we must check for these cases compared to the
1685 instruction previous to the previous instruction. */
1686 if ((! mips_opts
.mips16
1687 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
1688 && (prev_prev_insn
.insn_mo
->pinfo
& INSN_COPROC_MOVE_DELAY
)
1689 && (prev_prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
)
1690 && (pinfo
& INSN_READ_COND_CODE
)
1691 && ! cop_interlocks
)
1692 || ((prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
)
1693 && (pinfo
& INSN_WRITE_LO
)
1694 && ! (hilo_interlocks
1695 || (mips_tune
== CPU_R3900
&& (pinfo
& INSN_MULT
))))
1696 || ((prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
1697 && (pinfo
& INSN_WRITE_HI
)
1698 && ! (hilo_interlocks
1699 || (mips_tune
== CPU_R3900
&& (pinfo
& INSN_MULT
)))))
1704 if (prev_prev_insn_unreordered
)
1707 if (prev_prev_nop
&& nops
== 0)
1710 /* If we are being given a nop instruction, don't bother with
1711 one of the nops we would otherwise output. This will only
1712 happen when a nop instruction is used with mips_optimize set
1715 && ! mips_opts
.noreorder
1716 && ip
->insn_opcode
== (unsigned) (mips_opts
.mips16
? 0x6500 : 0))
1719 /* Now emit the right number of NOP instructions. */
1720 if (nops
> 0 && ! mips_opts
.noreorder
)
1723 unsigned long old_frag_offset
;
1725 struct insn_label_list
*l
;
1727 old_frag
= frag_now
;
1728 old_frag_offset
= frag_now_fix ();
1730 for (i
= 0; i
< nops
; i
++)
1735 listing_prev_line ();
1736 /* We may be at the start of a variant frag. In case we
1737 are, make sure there is enough space for the frag
1738 after the frags created by listing_prev_line. The
1739 argument to frag_grow here must be at least as large
1740 as the argument to all other calls to frag_grow in
1741 this file. We don't have to worry about being in the
1742 middle of a variant frag, because the variants insert
1743 all needed nop instructions themselves. */
1747 for (l
= insn_labels
; l
!= NULL
; l
= l
->next
)
1751 assert (S_GET_SEGMENT (l
->label
) == now_seg
);
1752 symbol_set_frag (l
->label
, frag_now
);
1753 val
= (valueT
) frag_now_fix ();
1754 /* mips16 text labels are stored as odd. */
1755 if (mips_opts
.mips16
)
1757 S_SET_VALUE (l
->label
, val
);
1760 #ifndef NO_ECOFF_DEBUGGING
1761 if (ECOFF_DEBUGGING
)
1762 ecoff_fix_loc (old_frag
, old_frag_offset
);
1765 else if (prev_nop_frag
!= NULL
)
1767 /* We have a frag holding nops we may be able to remove. If
1768 we don't need any nops, we can decrease the size of
1769 prev_nop_frag by the size of one instruction. If we do
1770 need some nops, we count them in prev_nops_required. */
1771 if (prev_nop_frag_since
== 0)
1775 prev_nop_frag
->fr_fix
-= mips_opts
.mips16
? 2 : 4;
1776 --prev_nop_frag_holds
;
1779 prev_nop_frag_required
+= nops
;
1783 if (prev_prev_nop
== 0)
1785 prev_nop_frag
->fr_fix
-= mips_opts
.mips16
? 2 : 4;
1786 --prev_nop_frag_holds
;
1789 ++prev_nop_frag_required
;
1792 if (prev_nop_frag_holds
<= prev_nop_frag_required
)
1793 prev_nop_frag
= NULL
;
1795 ++prev_nop_frag_since
;
1797 /* Sanity check: by the time we reach the second instruction
1798 after prev_nop_frag, we should have used up all the nops
1799 one way or another. */
1800 assert (prev_nop_frag_since
<= 1 || prev_nop_frag
== NULL
);
1804 if (reloc_type
> BFD_RELOC_UNUSED
)
1806 /* We need to set up a variant frag. */
1807 assert (mips_opts
.mips16
&& address_expr
!= NULL
);
1808 f
= frag_var (rs_machine_dependent
, 4, 0,
1809 RELAX_MIPS16_ENCODE (reloc_type
- BFD_RELOC_UNUSED
,
1810 mips16_small
, mips16_ext
,
1812 & INSN_UNCOND_BRANCH_DELAY
),
1813 (prev_insn_reloc_type
1814 == BFD_RELOC_MIPS16_JMP
)),
1815 make_expr_symbol (address_expr
), (offsetT
) 0,
1818 else if (place
!= NULL
)
1820 else if (mips_opts
.mips16
1822 && reloc_type
!= BFD_RELOC_MIPS16_JMP
)
1824 /* Make sure there is enough room to swap this instruction with
1825 a following jump instruction. */
1831 if (mips_opts
.mips16
1832 && mips_opts
.noreorder
1833 && (prev_pinfo
& INSN_UNCOND_BRANCH_DELAY
) != 0)
1834 as_warn (_("extended instruction in delay slot"));
1840 if (address_expr
!= NULL
&& reloc_type
< BFD_RELOC_UNUSED
)
1842 if (address_expr
->X_op
== O_constant
)
1847 ip
->insn_opcode
|= address_expr
->X_add_number
;
1850 case BFD_RELOC_LO16
:
1851 ip
->insn_opcode
|= address_expr
->X_add_number
& 0xffff;
1854 case BFD_RELOC_MIPS_JMP
:
1855 if ((address_expr
->X_add_number
& 3) != 0)
1856 as_bad (_("jump to misaligned address (0x%lx)"),
1857 (unsigned long) address_expr
->X_add_number
);
1858 ip
->insn_opcode
|= (address_expr
->X_add_number
>> 2) & 0x3ffffff;
1861 case BFD_RELOC_MIPS16_JMP
:
1862 if ((address_expr
->X_add_number
& 3) != 0)
1863 as_bad (_("jump to misaligned address (0x%lx)"),
1864 (unsigned long) address_expr
->X_add_number
);
1866 (((address_expr
->X_add_number
& 0x7c0000) << 3)
1867 | ((address_expr
->X_add_number
& 0xf800000) >> 7)
1868 | ((address_expr
->X_add_number
& 0x3fffc) >> 2));
1871 case BFD_RELOC_16_PCREL_S2
:
1881 /* Don't generate a reloc if we are writing into a variant
1885 fixp
= fix_new_exp (frag_now
, f
- frag_now
->fr_literal
, 4,
1887 reloc_type
== BFD_RELOC_16_PCREL_S2
,
1891 struct mips_hi_fixup
*hi_fixup
;
1893 assert (reloc_type
== BFD_RELOC_HI16_S
);
1894 hi_fixup
= ((struct mips_hi_fixup
*)
1895 xmalloc (sizeof (struct mips_hi_fixup
)));
1896 hi_fixup
->fixp
= fixp
;
1897 hi_fixup
->seg
= now_seg
;
1898 hi_fixup
->next
= mips_hi_fixup_list
;
1899 mips_hi_fixup_list
= hi_fixup
;
1905 if (! mips_opts
.mips16
)
1906 md_number_to_chars (f
, ip
->insn_opcode
, 4);
1907 else if (reloc_type
== BFD_RELOC_MIPS16_JMP
)
1909 md_number_to_chars (f
, ip
->insn_opcode
>> 16, 2);
1910 md_number_to_chars (f
+ 2, ip
->insn_opcode
& 0xffff, 2);
1916 md_number_to_chars (f
, 0xf000 | ip
->extend
, 2);
1919 md_number_to_chars (f
, ip
->insn_opcode
, 2);
1922 /* Update the register mask information. */
1923 if (! mips_opts
.mips16
)
1925 if (pinfo
& INSN_WRITE_GPR_D
)
1926 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
);
1927 if ((pinfo
& (INSN_WRITE_GPR_T
| INSN_READ_GPR_T
)) != 0)
1928 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
);
1929 if (pinfo
& INSN_READ_GPR_S
)
1930 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> OP_SH_RS
) & OP_MASK_RS
);
1931 if (pinfo
& INSN_WRITE_GPR_31
)
1932 mips_gprmask
|= 1 << 31;
1933 if (pinfo
& INSN_WRITE_FPR_D
)
1934 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FD
) & OP_MASK_FD
);
1935 if ((pinfo
& (INSN_WRITE_FPR_S
| INSN_READ_FPR_S
)) != 0)
1936 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FS
) & OP_MASK_FS
);
1937 if ((pinfo
& (INSN_WRITE_FPR_T
| INSN_READ_FPR_T
)) != 0)
1938 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FT
) & OP_MASK_FT
);
1939 if ((pinfo
& INSN_READ_FPR_R
) != 0)
1940 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FR
) & OP_MASK_FR
);
1941 if (pinfo
& INSN_COP
)
1943 /* We don't keep enough information to sort these cases out.
1944 The itbl support does keep this information however, although
1945 we currently don't support itbl fprmats as part of the cop
1946 instruction. May want to add this support in the future. */
1948 /* Never set the bit for $0, which is always zero. */
1949 mips_gprmask
&= ~1 << 0;
1953 if (pinfo
& (MIPS16_INSN_WRITE_X
| MIPS16_INSN_READ_X
))
1954 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_RX
)
1955 & MIPS16OP_MASK_RX
);
1956 if (pinfo
& (MIPS16_INSN_WRITE_Y
| MIPS16_INSN_READ_Y
))
1957 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_RY
)
1958 & MIPS16OP_MASK_RY
);
1959 if (pinfo
& MIPS16_INSN_WRITE_Z
)
1960 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_RZ
)
1961 & MIPS16OP_MASK_RZ
);
1962 if (pinfo
& (MIPS16_INSN_WRITE_T
| MIPS16_INSN_READ_T
))
1963 mips_gprmask
|= 1 << TREG
;
1964 if (pinfo
& (MIPS16_INSN_WRITE_SP
| MIPS16_INSN_READ_SP
))
1965 mips_gprmask
|= 1 << SP
;
1966 if (pinfo
& (MIPS16_INSN_WRITE_31
| MIPS16_INSN_READ_31
))
1967 mips_gprmask
|= 1 << RA
;
1968 if (pinfo
& MIPS16_INSN_WRITE_GPR_Y
)
1969 mips_gprmask
|= 1 << MIPS16OP_EXTRACT_REG32R (ip
->insn_opcode
);
1970 if (pinfo
& MIPS16_INSN_READ_Z
)
1971 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_MOVE32Z
)
1972 & MIPS16OP_MASK_MOVE32Z
);
1973 if (pinfo
& MIPS16_INSN_READ_GPR_X
)
1974 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_REGR32
)
1975 & MIPS16OP_MASK_REGR32
);
1978 if (place
== NULL
&& ! mips_opts
.noreorder
)
1980 /* Filling the branch delay slot is more complex. We try to
1981 switch the branch with the previous instruction, which we can
1982 do if the previous instruction does not set up a condition
1983 that the branch tests and if the branch is not itself the
1984 target of any branch. */
1985 if ((pinfo
& INSN_UNCOND_BRANCH_DELAY
)
1986 || (pinfo
& INSN_COND_BRANCH_DELAY
))
1988 if (mips_optimize
< 2
1989 /* If we have seen .set volatile or .set nomove, don't
1991 || mips_opts
.nomove
!= 0
1992 /* If we had to emit any NOP instructions, then we
1993 already know we can not swap. */
1995 /* If we don't even know the previous insn, we can not
1997 || ! prev_insn_valid
1998 /* If the previous insn is already in a branch delay
1999 slot, then we can not swap. */
2000 || prev_insn_is_delay_slot
2001 /* If the previous previous insn was in a .set
2002 noreorder, we can't swap. Actually, the MIPS
2003 assembler will swap in this situation. However, gcc
2004 configured -with-gnu-as will generate code like
2010 in which we can not swap the bne and INSN. If gcc is
2011 not configured -with-gnu-as, it does not output the
2012 .set pseudo-ops. We don't have to check
2013 prev_insn_unreordered, because prev_insn_valid will
2014 be 0 in that case. We don't want to use
2015 prev_prev_insn_valid, because we do want to be able
2016 to swap at the start of a function. */
2017 || prev_prev_insn_unreordered
2018 /* If the branch is itself the target of a branch, we
2019 can not swap. We cheat on this; all we check for is
2020 whether there is a label on this instruction. If
2021 there are any branches to anything other than a
2022 label, users must use .set noreorder. */
2023 || insn_labels
!= NULL
2024 /* If the previous instruction is in a variant frag, we
2025 can not do the swap. This does not apply to the
2026 mips16, which uses variant frags for different
2028 || (! mips_opts
.mips16
2029 && prev_insn_frag
->fr_type
== rs_machine_dependent
)
2030 /* If the branch reads the condition codes, we don't
2031 even try to swap, because in the sequence
2036 we can not swap, and I don't feel like handling that
2038 || (! mips_opts
.mips16
2039 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
2040 && (pinfo
& INSN_READ_COND_CODE
))
2041 /* We can not swap with an instruction that requires a
2042 delay slot, becase the target of the branch might
2043 interfere with that instruction. */
2044 || (! mips_opts
.mips16
2045 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
2047 /* Itbl support may require additional care here. */
2048 & (INSN_LOAD_COPROC_DELAY
2049 | INSN_COPROC_MOVE_DELAY
2050 | INSN_WRITE_COND_CODE
)))
2051 || (! (hilo_interlocks
2052 || (mips_tune
== CPU_R3900
&& (pinfo
& INSN_MULT
)))
2056 || (! mips_opts
.mips16
2058 && (prev_pinfo
& INSN_LOAD_MEMORY_DELAY
))
2059 || (! mips_opts
.mips16
2060 && mips_opts
.isa
== ISA_MIPS1
2061 /* Itbl support may require additional care here. */
2062 && (prev_pinfo
& INSN_COPROC_MEMORY_DELAY
))
2063 /* We can not swap with a branch instruction. */
2065 & (INSN_UNCOND_BRANCH_DELAY
2066 | INSN_COND_BRANCH_DELAY
2067 | INSN_COND_BRANCH_LIKELY
))
2068 /* We do not swap with a trap instruction, since it
2069 complicates trap handlers to have the trap
2070 instruction be in a delay slot. */
2071 || (prev_pinfo
& INSN_TRAP
)
2072 /* If the branch reads a register that the previous
2073 instruction sets, we can not swap. */
2074 || (! mips_opts
.mips16
2075 && (prev_pinfo
& INSN_WRITE_GPR_T
)
2076 && insn_uses_reg (ip
,
2077 ((prev_insn
.insn_opcode
>> OP_SH_RT
)
2080 || (! mips_opts
.mips16
2081 && (prev_pinfo
& INSN_WRITE_GPR_D
)
2082 && insn_uses_reg (ip
,
2083 ((prev_insn
.insn_opcode
>> OP_SH_RD
)
2086 || (mips_opts
.mips16
2087 && (((prev_pinfo
& MIPS16_INSN_WRITE_X
)
2088 && insn_uses_reg (ip
,
2089 ((prev_insn
.insn_opcode
2091 & MIPS16OP_MASK_RX
),
2093 || ((prev_pinfo
& MIPS16_INSN_WRITE_Y
)
2094 && insn_uses_reg (ip
,
2095 ((prev_insn
.insn_opcode
2097 & MIPS16OP_MASK_RY
),
2099 || ((prev_pinfo
& MIPS16_INSN_WRITE_Z
)
2100 && insn_uses_reg (ip
,
2101 ((prev_insn
.insn_opcode
2103 & MIPS16OP_MASK_RZ
),
2105 || ((prev_pinfo
& MIPS16_INSN_WRITE_T
)
2106 && insn_uses_reg (ip
, TREG
, MIPS_GR_REG
))
2107 || ((prev_pinfo
& MIPS16_INSN_WRITE_31
)
2108 && insn_uses_reg (ip
, RA
, MIPS_GR_REG
))
2109 || ((prev_pinfo
& MIPS16_INSN_WRITE_GPR_Y
)
2110 && insn_uses_reg (ip
,
2111 MIPS16OP_EXTRACT_REG32R (prev_insn
.
2114 /* If the branch writes a register that the previous
2115 instruction sets, we can not swap (we know that
2116 branches write only to RD or to $31). */
2117 || (! mips_opts
.mips16
2118 && (prev_pinfo
& INSN_WRITE_GPR_T
)
2119 && (((pinfo
& INSN_WRITE_GPR_D
)
2120 && (((prev_insn
.insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
)
2121 == ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)))
2122 || ((pinfo
& INSN_WRITE_GPR_31
)
2123 && (((prev_insn
.insn_opcode
>> OP_SH_RT
)
2126 || (! mips_opts
.mips16
2127 && (prev_pinfo
& INSN_WRITE_GPR_D
)
2128 && (((pinfo
& INSN_WRITE_GPR_D
)
2129 && (((prev_insn
.insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)
2130 == ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)))
2131 || ((pinfo
& INSN_WRITE_GPR_31
)
2132 && (((prev_insn
.insn_opcode
>> OP_SH_RD
)
2135 || (mips_opts
.mips16
2136 && (pinfo
& MIPS16_INSN_WRITE_31
)
2137 && ((prev_pinfo
& MIPS16_INSN_WRITE_31
)
2138 || ((prev_pinfo
& MIPS16_INSN_WRITE_GPR_Y
)
2139 && (MIPS16OP_EXTRACT_REG32R (prev_insn
.insn_opcode
)
2141 /* If the branch writes a register that the previous
2142 instruction reads, we can not swap (we know that
2143 branches only write to RD or to $31). */
2144 || (! mips_opts
.mips16
2145 && (pinfo
& INSN_WRITE_GPR_D
)
2146 && insn_uses_reg (&prev_insn
,
2147 ((ip
->insn_opcode
>> OP_SH_RD
)
2150 || (! mips_opts
.mips16
2151 && (pinfo
& INSN_WRITE_GPR_31
)
2152 && insn_uses_reg (&prev_insn
, 31, MIPS_GR_REG
))
2153 || (mips_opts
.mips16
2154 && (pinfo
& MIPS16_INSN_WRITE_31
)
2155 && insn_uses_reg (&prev_insn
, RA
, MIPS_GR_REG
))
2156 /* If we are generating embedded PIC code, the branch
2157 might be expanded into a sequence which uses $at, so
2158 we can't swap with an instruction which reads it. */
2159 || (mips_pic
== EMBEDDED_PIC
2160 && insn_uses_reg (&prev_insn
, AT
, MIPS_GR_REG
))
2161 /* If the previous previous instruction has a load
2162 delay, and sets a register that the branch reads, we
2164 || (! mips_opts
.mips16
2165 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
2166 /* Itbl support may require additional care here. */
2167 && ((prev_prev_insn
.insn_mo
->pinfo
& INSN_LOAD_COPROC_DELAY
)
2168 || (! gpr_interlocks
2169 && (prev_prev_insn
.insn_mo
->pinfo
2170 & INSN_LOAD_MEMORY_DELAY
)))
2171 && insn_uses_reg (ip
,
2172 ((prev_prev_insn
.insn_opcode
>> OP_SH_RT
)
2175 /* If one instruction sets a condition code and the
2176 other one uses a condition code, we can not swap. */
2177 || ((pinfo
& INSN_READ_COND_CODE
)
2178 && (prev_pinfo
& INSN_WRITE_COND_CODE
))
2179 || ((pinfo
& INSN_WRITE_COND_CODE
)
2180 && (prev_pinfo
& INSN_READ_COND_CODE
))
2181 /* If the previous instruction uses the PC, we can not
2183 || (mips_opts
.mips16
2184 && (prev_pinfo
& MIPS16_INSN_READ_PC
))
2185 /* If the previous instruction was extended, we can not
2187 || (mips_opts
.mips16
&& prev_insn_extended
)
2188 /* If the previous instruction had a fixup in mips16
2189 mode, we can not swap. This normally means that the
2190 previous instruction was a 4 byte branch anyhow. */
2191 || (mips_opts
.mips16
&& prev_insn_fixp
)
2192 /* If the previous instruction is a sync, sync.l, or
2193 sync.p, we can not swap. */
2194 || (prev_pinfo
& INSN_SYNC
))
2196 /* We could do even better for unconditional branches to
2197 portions of this object file; we could pick up the
2198 instruction at the destination, put it in the delay
2199 slot, and bump the destination address. */
2201 /* Update the previous insn information. */
2202 prev_prev_insn
= *ip
;
2203 prev_insn
.insn_mo
= &dummy_opcode
;
2207 /* It looks like we can actually do the swap. */
2208 if (! mips_opts
.mips16
)
2213 prev_f
= prev_insn_frag
->fr_literal
+ prev_insn_where
;
2214 memcpy (temp
, prev_f
, 4);
2215 memcpy (prev_f
, f
, 4);
2216 memcpy (f
, temp
, 4);
2219 prev_insn_fixp
->fx_frag
= frag_now
;
2220 prev_insn_fixp
->fx_where
= f
- frag_now
->fr_literal
;
2224 fixp
->fx_frag
= prev_insn_frag
;
2225 fixp
->fx_where
= prev_insn_where
;
2233 assert (prev_insn_fixp
== NULL
);
2234 prev_f
= prev_insn_frag
->fr_literal
+ prev_insn_where
;
2235 memcpy (temp
, prev_f
, 2);
2236 memcpy (prev_f
, f
, 2);
2237 if (reloc_type
!= BFD_RELOC_MIPS16_JMP
)
2239 assert (reloc_type
== BFD_RELOC_UNUSED
);
2240 memcpy (f
, temp
, 2);
2244 memcpy (f
, f
+ 2, 2);
2245 memcpy (f
+ 2, temp
, 2);
2249 fixp
->fx_frag
= prev_insn_frag
;
2250 fixp
->fx_where
= prev_insn_where
;
2254 /* Update the previous insn information; leave prev_insn
2256 prev_prev_insn
= *ip
;
2258 prev_insn_is_delay_slot
= 1;
2260 /* If that was an unconditional branch, forget the previous
2261 insn information. */
2262 if (pinfo
& INSN_UNCOND_BRANCH_DELAY
)
2264 prev_prev_insn
.insn_mo
= &dummy_opcode
;
2265 prev_insn
.insn_mo
= &dummy_opcode
;
2268 prev_insn_fixp
= NULL
;
2269 prev_insn_reloc_type
= BFD_RELOC_UNUSED
;
2270 prev_insn_extended
= 0;
2272 else if (pinfo
& INSN_COND_BRANCH_LIKELY
)
2274 /* We don't yet optimize a branch likely. What we should do
2275 is look at the target, copy the instruction found there
2276 into the delay slot, and increment the branch to jump to
2277 the next instruction. */
2279 /* Update the previous insn information. */
2280 prev_prev_insn
= *ip
;
2281 prev_insn
.insn_mo
= &dummy_opcode
;
2282 prev_insn_fixp
= NULL
;
2283 prev_insn_reloc_type
= BFD_RELOC_UNUSED
;
2284 prev_insn_extended
= 0;
2288 /* Update the previous insn information. */
2290 prev_prev_insn
.insn_mo
= &dummy_opcode
;
2292 prev_prev_insn
= prev_insn
;
2295 /* Any time we see a branch, we always fill the delay slot
2296 immediately; since this insn is not a branch, we know it
2297 is not in a delay slot. */
2298 prev_insn_is_delay_slot
= 0;
2300 prev_insn_fixp
= fixp
;
2301 prev_insn_reloc_type
= reloc_type
;
2302 if (mips_opts
.mips16
)
2303 prev_insn_extended
= (ip
->use_extend
2304 || reloc_type
> BFD_RELOC_UNUSED
);
2307 prev_prev_insn_unreordered
= prev_insn_unreordered
;
2308 prev_insn_unreordered
= 0;
2309 prev_insn_frag
= frag_now
;
2310 prev_insn_where
= f
- frag_now
->fr_literal
;
2311 prev_insn_valid
= 1;
2313 else if (place
== NULL
)
2315 /* We need to record a bit of information even when we are not
2316 reordering, in order to determine the base address for mips16
2317 PC relative relocs. */
2318 prev_prev_insn
= prev_insn
;
2320 prev_insn_reloc_type
= reloc_type
;
2321 prev_prev_insn_unreordered
= prev_insn_unreordered
;
2322 prev_insn_unreordered
= 1;
2325 /* We just output an insn, so the next one doesn't have a label. */
2326 mips_clear_insn_labels ();
2328 /* We must ensure that a fixup associated with an unmatched %hi
2329 reloc does not become a variant frag. Otherwise, the
2330 rearrangement of %hi relocs in frob_file may confuse
2334 frag_wane (frag_now
);
2339 /* This function forgets that there was any previous instruction or
2340 label. If PRESERVE is non-zero, it remembers enough information to
2341 know whether nops are needed before a noreorder section. */
2344 mips_no_prev_insn (preserve
)
2349 prev_insn
.insn_mo
= &dummy_opcode
;
2350 prev_prev_insn
.insn_mo
= &dummy_opcode
;
2351 prev_nop_frag
= NULL
;
2352 prev_nop_frag_holds
= 0;
2353 prev_nop_frag_required
= 0;
2354 prev_nop_frag_since
= 0;
2356 prev_insn_valid
= 0;
2357 prev_insn_is_delay_slot
= 0;
2358 prev_insn_unreordered
= 0;
2359 prev_insn_extended
= 0;
2360 prev_insn_reloc_type
= BFD_RELOC_UNUSED
;
2361 prev_prev_insn_unreordered
= 0;
2362 mips_clear_insn_labels ();
2365 /* This function must be called whenever we turn on noreorder or emit
2366 something other than instructions. It inserts any NOPS which might
2367 be needed by the previous instruction, and clears the information
2368 kept for the previous instructions. The INSNS parameter is true if
2369 instructions are to follow. */
2372 mips_emit_delays (insns
)
2375 if (! mips_opts
.noreorder
)
2380 if ((! mips_opts
.mips16
2381 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
2382 && (! cop_interlocks
2383 && (prev_insn
.insn_mo
->pinfo
2384 & (INSN_LOAD_COPROC_DELAY
2385 | INSN_COPROC_MOVE_DELAY
2386 | INSN_WRITE_COND_CODE
))))
2387 || (! hilo_interlocks
2388 && (prev_insn
.insn_mo
->pinfo
2391 || (! mips_opts
.mips16
2393 && (prev_insn
.insn_mo
->pinfo
2394 & INSN_LOAD_MEMORY_DELAY
))
2395 || (! mips_opts
.mips16
2396 && mips_opts
.isa
== ISA_MIPS1
2397 && (prev_insn
.insn_mo
->pinfo
2398 & INSN_COPROC_MEMORY_DELAY
)))
2400 /* Itbl support may require additional care here. */
2402 if ((! mips_opts
.mips16
2403 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
2404 && (! cop_interlocks
2405 && prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
))
2406 || (! hilo_interlocks
2407 && ((prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
2408 || (prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
))))
2411 if (prev_insn_unreordered
)
2414 else if ((! mips_opts
.mips16
2415 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
2416 && (! cop_interlocks
2417 && prev_prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
))
2418 || (! hilo_interlocks
2419 && ((prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
2420 || (prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
))))
2422 /* Itbl support may require additional care here. */
2423 if (! prev_prev_insn_unreordered
)
2429 struct insn_label_list
*l
;
2433 /* Record the frag which holds the nop instructions, so
2434 that we can remove them if we don't need them. */
2435 frag_grow (mips_opts
.mips16
? nops
* 2 : nops
* 4);
2436 prev_nop_frag
= frag_now
;
2437 prev_nop_frag_holds
= nops
;
2438 prev_nop_frag_required
= 0;
2439 prev_nop_frag_since
= 0;
2442 for (; nops
> 0; --nops
)
2447 /* Move on to a new frag, so that it is safe to simply
2448 decrease the size of prev_nop_frag. */
2449 frag_wane (frag_now
);
2453 for (l
= insn_labels
; l
!= NULL
; l
= l
->next
)
2457 assert (S_GET_SEGMENT (l
->label
) == now_seg
);
2458 symbol_set_frag (l
->label
, frag_now
);
2459 val
= (valueT
) frag_now_fix ();
2460 /* mips16 text labels are stored as odd. */
2461 if (mips_opts
.mips16
)
2463 S_SET_VALUE (l
->label
, val
);
2468 /* Mark instruction labels in mips16 mode. */
2469 if (mips_opts
.mips16
&& insns
)
2470 mips16_mark_labels ();
2472 mips_no_prev_insn (insns
);
2475 /* Build an instruction created by a macro expansion. This is passed
2476 a pointer to the count of instructions created so far, an
2477 expression, the name of the instruction to build, an operand format
2478 string, and corresponding arguments. */
2482 macro_build (char *place
,
2490 macro_build (place
, counter
, ep
, name
, fmt
, va_alist
)
2499 struct mips_cl_insn insn
;
2500 bfd_reloc_code_real_type r
;
2504 va_start (args
, fmt
);
2510 * If the macro is about to expand into a second instruction,
2511 * print a warning if needed. We need to pass ip as a parameter
2512 * to generate a better warning message here...
2514 if (mips_opts
.warn_about_macros
&& place
== NULL
&& *counter
== 1)
2515 as_warn (_("Macro instruction expanded into multiple instructions"));
2518 *counter
+= 1; /* bump instruction counter */
2520 if (mips_opts
.mips16
)
2522 mips16_macro_build (place
, counter
, ep
, name
, fmt
, args
);
2527 r
= BFD_RELOC_UNUSED
;
2528 insn
.insn_mo
= (struct mips_opcode
*) hash_find (op_hash
, name
);
2529 assert (insn
.insn_mo
);
2530 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
2532 /* Search until we get a match for NAME. */
2535 if (strcmp (fmt
, insn
.insn_mo
->args
) == 0
2536 && insn
.insn_mo
->pinfo
!= INSN_MACRO
2537 && OPCODE_IS_MEMBER (insn
.insn_mo
, mips_opts
.isa
, mips_arch
)
2538 && (mips_arch
!= CPU_R4650
|| (insn
.insn_mo
->pinfo
& FP_D
) == 0))
2542 assert (insn
.insn_mo
->name
);
2543 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
2546 insn
.insn_opcode
= insn
.insn_mo
->match
;
2562 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_RT
;
2566 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_CODE
;
2571 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_FT
;
2576 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_RD
;
2581 int tmp
= va_arg (args
, int);
2583 insn
.insn_opcode
|= tmp
<< OP_SH_RT
;
2584 insn
.insn_opcode
|= tmp
<< OP_SH_RD
;
2590 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_FS
;
2597 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_SHAMT
;
2601 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_FD
;
2605 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_CODE20
;
2609 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_CODE19
;
2613 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_CODE2
;
2620 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_RS
;
2626 r
= (bfd_reloc_code_real_type
) va_arg (args
, int);
2627 assert (r
== BFD_RELOC_MIPS_GPREL
2628 || r
== BFD_RELOC_MIPS_LITERAL
2629 || r
== BFD_RELOC_LO16
2630 || r
== BFD_RELOC_MIPS_GOT16
2631 || r
== BFD_RELOC_MIPS_CALL16
2632 || r
== BFD_RELOC_MIPS_GOT_LO16
2633 || r
== BFD_RELOC_MIPS_CALL_LO16
2634 || (ep
->X_op
== O_subtract
2635 && r
== BFD_RELOC_PCREL_LO16
));
2639 r
= (bfd_reloc_code_real_type
) va_arg (args
, int);
2641 && (ep
->X_op
== O_constant
2642 || (ep
->X_op
== O_symbol
2643 && (r
== BFD_RELOC_HI16_S
2644 || r
== BFD_RELOC_HI16
2645 || r
== BFD_RELOC_MIPS_GOT_HI16
2646 || r
== BFD_RELOC_MIPS_CALL_HI16
))
2647 || (ep
->X_op
== O_subtract
2648 && r
== BFD_RELOC_PCREL_HI16_S
)));
2649 if (ep
->X_op
== O_constant
)
2651 insn
.insn_opcode
|= (ep
->X_add_number
>> 16) & 0xffff;
2653 r
= BFD_RELOC_UNUSED
;
2658 assert (ep
!= NULL
);
2660 * This allows macro() to pass an immediate expression for
2661 * creating short branches without creating a symbol.
2662 * Note that the expression still might come from the assembly
2663 * input, in which case the value is not checked for range nor
2664 * is a relocation entry generated (yuck).
2666 if (ep
->X_op
== O_constant
)
2668 insn
.insn_opcode
|= (ep
->X_add_number
>> 2) & 0xffff;
2672 r
= BFD_RELOC_16_PCREL_S2
;
2676 assert (ep
!= NULL
);
2677 r
= BFD_RELOC_MIPS_JMP
;
2681 insn
.insn_opcode
|= va_arg (args
, unsigned long);
2690 assert (r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
2692 append_insn (place
, &insn
, ep
, r
, false);
2696 mips16_macro_build (place
, counter
, ep
, name
, fmt
, args
)
2698 int *counter ATTRIBUTE_UNUSED
;
2704 struct mips_cl_insn insn
;
2705 bfd_reloc_code_real_type r
;
2707 r
= BFD_RELOC_UNUSED
;
2708 insn
.insn_mo
= (struct mips_opcode
*) hash_find (mips16_op_hash
, name
);
2709 assert (insn
.insn_mo
);
2710 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
2712 while (strcmp (fmt
, insn
.insn_mo
->args
) != 0
2713 || insn
.insn_mo
->pinfo
== INSN_MACRO
)
2716 assert (insn
.insn_mo
->name
);
2717 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
2720 insn
.insn_opcode
= insn
.insn_mo
->match
;
2721 insn
.use_extend
= false;
2740 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_RY
;
2745 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_RX
;
2749 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_RZ
;
2753 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_MOVE32Z
;
2763 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_REGR32
;
2770 regno
= va_arg (args
, int);
2771 regno
= ((regno
& 7) << 2) | ((regno
& 0x18) >> 3);
2772 insn
.insn_opcode
|= regno
<< MIPS16OP_SH_REG32R
;
2793 assert (ep
!= NULL
);
2795 if (ep
->X_op
!= O_constant
)
2796 r
= BFD_RELOC_UNUSED
+ c
;
2799 mips16_immed ((char *) NULL
, 0, c
, ep
->X_add_number
, false,
2800 false, false, &insn
.insn_opcode
,
2801 &insn
.use_extend
, &insn
.extend
);
2803 r
= BFD_RELOC_UNUSED
;
2809 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_IMM6
;
2816 assert (r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
2818 append_insn (place
, &insn
, ep
, r
, false);
2822 * Generate a "lui" instruction.
2825 macro_build_lui (place
, counter
, ep
, regnum
)
2831 expressionS high_expr
;
2832 struct mips_cl_insn insn
;
2833 bfd_reloc_code_real_type r
;
2834 CONST
char *name
= "lui";
2835 CONST
char *fmt
= "t,u";
2837 assert (! mips_opts
.mips16
);
2843 high_expr
.X_op
= O_constant
;
2844 high_expr
.X_add_number
= ep
->X_add_number
;
2847 if (high_expr
.X_op
== O_constant
)
2849 /* we can compute the instruction now without a relocation entry */
2850 if (high_expr
.X_add_number
& 0x8000)
2851 high_expr
.X_add_number
+= 0x10000;
2852 high_expr
.X_add_number
=
2853 ((unsigned long) high_expr
.X_add_number
>> 16) & 0xffff;
2854 r
= BFD_RELOC_UNUSED
;
2858 assert (ep
->X_op
== O_symbol
);
2859 /* _gp_disp is a special case, used from s_cpload. */
2860 assert (mips_pic
== NO_PIC
2861 || strcmp (S_GET_NAME (ep
->X_add_symbol
), "_gp_disp") == 0);
2862 r
= BFD_RELOC_HI16_S
;
2866 * If the macro is about to expand into a second instruction,
2867 * print a warning if needed. We need to pass ip as a parameter
2868 * to generate a better warning message here...
2870 if (mips_opts
.warn_about_macros
&& place
== NULL
&& *counter
== 1)
2871 as_warn (_("Macro instruction expanded into multiple instructions"));
2874 *counter
+= 1; /* bump instruction counter */
2876 insn
.insn_mo
= (struct mips_opcode
*) hash_find (op_hash
, name
);
2877 assert (insn
.insn_mo
);
2878 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
2879 assert (strcmp (fmt
, insn
.insn_mo
->args
) == 0);
2881 insn
.insn_opcode
= insn
.insn_mo
->match
| (regnum
<< OP_SH_RT
);
2882 if (r
== BFD_RELOC_UNUSED
)
2884 insn
.insn_opcode
|= high_expr
.X_add_number
;
2885 append_insn (place
, &insn
, NULL
, r
, false);
2888 append_insn (place
, &insn
, &high_expr
, r
, false);
2892 * Generates code to set the $at register to true (one)
2893 * if reg is less than the immediate expression.
2896 set_at (counter
, reg
, unsignedp
)
2901 if (imm_expr
.X_op
== O_constant
2902 && imm_expr
.X_add_number
>= -0x8000
2903 && imm_expr
.X_add_number
< 0x8000)
2904 macro_build ((char *) NULL
, counter
, &imm_expr
,
2905 unsignedp
? "sltiu" : "slti",
2906 "t,r,j", AT
, reg
, (int) BFD_RELOC_LO16
);
2909 load_register (counter
, AT
, &imm_expr
, 0);
2910 macro_build ((char *) NULL
, counter
, NULL
,
2911 unsignedp
? "sltu" : "slt",
2912 "d,v,t", AT
, reg
, AT
);
2916 /* Warn if an expression is not a constant. */
2919 check_absolute_expr (ip
, ex
)
2920 struct mips_cl_insn
*ip
;
2923 if (ex
->X_op
== O_big
)
2924 as_bad (_("unsupported large constant"));
2925 else if (ex
->X_op
!= O_constant
)
2926 as_bad (_("Instruction %s requires absolute expression"), ip
->insn_mo
->name
);
2929 /* Count the leading zeroes by performing a binary chop. This is a
2930 bulky bit of source, but performance is a LOT better for the
2931 majority of values than a simple loop to count the bits:
2932 for (lcnt = 0; (lcnt < 32); lcnt++)
2933 if ((v) & (1 << (31 - lcnt)))
2935 However it is not code size friendly, and the gain will drop a bit
2936 on certain cached systems.
2938 #define COUNT_TOP_ZEROES(v) \
2939 (((v) & ~0xffff) == 0 \
2940 ? ((v) & ~0xff) == 0 \
2941 ? ((v) & ~0xf) == 0 \
2942 ? ((v) & ~0x3) == 0 \
2943 ? ((v) & ~0x1) == 0 \
2948 : ((v) & ~0x7) == 0 \
2951 : ((v) & ~0x3f) == 0 \
2952 ? ((v) & ~0x1f) == 0 \
2955 : ((v) & ~0x7f) == 0 \
2958 : ((v) & ~0xfff) == 0 \
2959 ? ((v) & ~0x3ff) == 0 \
2960 ? ((v) & ~0x1ff) == 0 \
2963 : ((v) & ~0x7ff) == 0 \
2966 : ((v) & ~0x3fff) == 0 \
2967 ? ((v) & ~0x1fff) == 0 \
2970 : ((v) & ~0x7fff) == 0 \
2973 : ((v) & ~0xffffff) == 0 \
2974 ? ((v) & ~0xfffff) == 0 \
2975 ? ((v) & ~0x3ffff) == 0 \
2976 ? ((v) & ~0x1ffff) == 0 \
2979 : ((v) & ~0x7ffff) == 0 \
2982 : ((v) & ~0x3fffff) == 0 \
2983 ? ((v) & ~0x1fffff) == 0 \
2986 : ((v) & ~0x7fffff) == 0 \
2989 : ((v) & ~0xfffffff) == 0 \
2990 ? ((v) & ~0x3ffffff) == 0 \
2991 ? ((v) & ~0x1ffffff) == 0 \
2994 : ((v) & ~0x7ffffff) == 0 \
2997 : ((v) & ~0x3fffffff) == 0 \
2998 ? ((v) & ~0x1fffffff) == 0 \
3001 : ((v) & ~0x7fffffff) == 0 \
3006 * This routine generates the least number of instructions neccessary to load
3007 * an absolute expression value into a register.
3010 load_register (counter
, reg
, ep
, dbl
)
3017 expressionS hi32
, lo32
;
3019 if (ep
->X_op
!= O_big
)
3021 assert (ep
->X_op
== O_constant
);
3022 if (ep
->X_add_number
< 0x8000
3023 && (ep
->X_add_number
>= 0
3024 || (ep
->X_add_number
>= -0x8000
3027 || sizeof (ep
->X_add_number
) > 4))))
3029 /* We can handle 16 bit signed values with an addiu to
3030 $zero. No need to ever use daddiu here, since $zero and
3031 the result are always correct in 32 bit mode. */
3032 macro_build ((char *) NULL
, counter
, ep
, "addiu", "t,r,j", reg
, 0,
3033 (int) BFD_RELOC_LO16
);
3036 else if (ep
->X_add_number
>= 0 && ep
->X_add_number
< 0x10000)
3038 /* We can handle 16 bit unsigned values with an ori to
3040 macro_build ((char *) NULL
, counter
, ep
, "ori", "t,r,i", reg
, 0,
3041 (int) BFD_RELOC_LO16
);
3044 else if ((((ep
->X_add_number
&~ (offsetT
) 0x7fffffff) == 0
3045 || ((ep
->X_add_number
&~ (offsetT
) 0x7fffffff)
3046 == ~ (offsetT
) 0x7fffffff))
3049 || sizeof (ep
->X_add_number
) > 4
3050 || (ep
->X_add_number
& 0x80000000) == 0))
3051 || ((HAVE_32BIT_GPRS
|| ! dbl
)
3052 && (ep
->X_add_number
&~ (offsetT
) 0xffffffff) == 0)
3055 && ((ep
->X_add_number
&~ (offsetT
) 0xffffffff)
3056 == ~ (offsetT
) 0xffffffff)))
3058 /* 32 bit values require an lui. */
3059 macro_build ((char *) NULL
, counter
, ep
, "lui", "t,u", reg
,
3060 (int) BFD_RELOC_HI16
);
3061 if ((ep
->X_add_number
& 0xffff) != 0)
3062 macro_build ((char *) NULL
, counter
, ep
, "ori", "t,r,i", reg
, reg
,
3063 (int) BFD_RELOC_LO16
);
3068 /* The value is larger than 32 bits. */
3070 if (HAVE_32BIT_GPRS
)
3072 as_bad (_("Number larger than 32 bits"));
3073 macro_build ((char *) NULL
, counter
, ep
, "addiu", "t,r,j", reg
, 0,
3074 (int) BFD_RELOC_LO16
);
3078 if (ep
->X_op
!= O_big
)
3081 hi32
.X_add_number
= (valueT
) hi32
.X_add_number
>> 16;
3082 hi32
.X_add_number
= (valueT
) hi32
.X_add_number
>> 16;
3083 hi32
.X_add_number
&= 0xffffffff;
3085 lo32
.X_add_number
&= 0xffffffff;
3089 assert (ep
->X_add_number
> 2);
3090 if (ep
->X_add_number
== 3)
3091 generic_bignum
[3] = 0;
3092 else if (ep
->X_add_number
> 4)
3093 as_bad (_("Number larger than 64 bits"));
3094 lo32
.X_op
= O_constant
;
3095 lo32
.X_add_number
= generic_bignum
[0] + (generic_bignum
[1] << 16);
3096 hi32
.X_op
= O_constant
;
3097 hi32
.X_add_number
= generic_bignum
[2] + (generic_bignum
[3] << 16);
3100 if (hi32
.X_add_number
== 0)
3105 unsigned long hi
, lo
;
3107 if (hi32
.X_add_number
== 0xffffffff)
3109 if ((lo32
.X_add_number
& 0xffff8000) == 0xffff8000)
3111 macro_build ((char *) NULL
, counter
, &lo32
, "addiu", "t,r,j",
3112 reg
, 0, (int) BFD_RELOC_LO16
);
3115 if (lo32
.X_add_number
& 0x80000000)
3117 macro_build ((char *) NULL
, counter
, &lo32
, "lui", "t,u", reg
,
3118 (int) BFD_RELOC_HI16
);
3119 if (lo32
.X_add_number
& 0xffff)
3120 macro_build ((char *) NULL
, counter
, &lo32
, "ori", "t,r,i",
3121 reg
, reg
, (int) BFD_RELOC_LO16
);
3126 /* Check for 16bit shifted constant. We know that hi32 is
3127 non-zero, so start the mask on the first bit of the hi32
3132 unsigned long himask
, lomask
;
3136 himask
= 0xffff >> (32 - shift
);
3137 lomask
= (0xffff << shift
) & 0xffffffff;
3141 himask
= 0xffff << (shift
- 32);
3144 if ((hi32
.X_add_number
& ~(offsetT
) himask
) == 0
3145 && (lo32
.X_add_number
& ~(offsetT
) lomask
) == 0)
3149 tmp
.X_op
= O_constant
;
3151 tmp
.X_add_number
= ((hi32
.X_add_number
<< (32 - shift
))
3152 | (lo32
.X_add_number
>> shift
));
3154 tmp
.X_add_number
= hi32
.X_add_number
>> (shift
- 32);
3155 macro_build ((char *) NULL
, counter
, &tmp
,
3156 "ori", "t,r,i", reg
, 0,
3157 (int) BFD_RELOC_LO16
);
3158 macro_build ((char *) NULL
, counter
, NULL
,
3159 (shift
>= 32) ? "dsll32" : "dsll",
3161 (shift
>= 32) ? shift
- 32 : shift
);
3166 while (shift
<= (64 - 16));
3168 /* Find the bit number of the lowest one bit, and store the
3169 shifted value in hi/lo. */
3170 hi
= (unsigned long) (hi32
.X_add_number
& 0xffffffff);
3171 lo
= (unsigned long) (lo32
.X_add_number
& 0xffffffff);
3175 while ((lo
& 1) == 0)
3180 lo
|= (hi
& (((unsigned long) 1 << bit
) - 1)) << (32 - bit
);
3186 while ((hi
& 1) == 0)
3195 /* Optimize if the shifted value is a (power of 2) - 1. */
3196 if ((hi
== 0 && ((lo
+ 1) & lo
) == 0)
3197 || (lo
== 0xffffffff && ((hi
+ 1) & hi
) == 0))
3199 shift
= COUNT_TOP_ZEROES ((unsigned int) hi32
.X_add_number
);
3204 /* This instruction will set the register to be all
3206 tmp
.X_op
= O_constant
;
3207 tmp
.X_add_number
= (offsetT
) -1;
3208 macro_build ((char *) NULL
, counter
, &tmp
, "addiu", "t,r,j",
3209 reg
, 0, (int) BFD_RELOC_LO16
);
3213 macro_build ((char *) NULL
, counter
, NULL
,
3214 (bit
>= 32) ? "dsll32" : "dsll",
3216 (bit
>= 32) ? bit
- 32 : bit
);
3218 macro_build ((char *) NULL
, counter
, NULL
,
3219 (shift
>= 32) ? "dsrl32" : "dsrl",
3221 (shift
>= 32) ? shift
- 32 : shift
);
3226 /* Sign extend hi32 before calling load_register, because we can
3227 generally get better code when we load a sign extended value. */
3228 if ((hi32
.X_add_number
& 0x80000000) != 0)
3229 hi32
.X_add_number
|= ~(offsetT
) 0xffffffff;
3230 load_register (counter
, reg
, &hi32
, 0);
3233 if ((lo32
.X_add_number
& 0xffff0000) == 0)
3237 macro_build ((char *) NULL
, counter
, NULL
, "dsll32", "d,w,<", reg
,
3246 if ((freg
== 0) && (lo32
.X_add_number
== 0xffffffff))
3248 macro_build ((char *) NULL
, counter
, &lo32
, "lui", "t,u", reg
,
3249 (int) BFD_RELOC_HI16
);
3250 macro_build ((char *) NULL
, counter
, NULL
, "dsrl32", "d,w,<", reg
,
3257 macro_build ((char *) NULL
, counter
, NULL
, "dsll", "d,w,<", reg
,
3262 mid16
.X_add_number
>>= 16;
3263 macro_build ((char *) NULL
, counter
, &mid16
, "ori", "t,r,i", reg
,
3264 freg
, (int) BFD_RELOC_LO16
);
3265 macro_build ((char *) NULL
, counter
, NULL
, "dsll", "d,w,<", reg
,
3269 if ((lo32
.X_add_number
& 0xffff) != 0)
3270 macro_build ((char *) NULL
, counter
, &lo32
, "ori", "t,r,i", reg
, freg
,
3271 (int) BFD_RELOC_LO16
);
3274 /* Load an address into a register. */
3277 load_address (counter
, reg
, ep
)
3284 if (ep
->X_op
!= O_constant
3285 && ep
->X_op
!= O_symbol
)
3287 as_bad (_("expression too complex"));
3288 ep
->X_op
= O_constant
;
3291 if (ep
->X_op
== O_constant
)
3293 load_register (counter
, reg
, ep
, 0);
3297 if (mips_pic
== NO_PIC
)
3299 /* If this is a reference to a GP relative symbol, we want
3300 addiu $reg,$gp,<sym> (BFD_RELOC_MIPS_GPREL)
3302 lui $reg,<sym> (BFD_RELOC_HI16_S)
3303 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
3304 If we have an addend, we always use the latter form. */
3305 if ((valueT
) ep
->X_add_number
>= MAX_GPREL_OFFSET
3306 || nopic_need_relax (ep
->X_add_symbol
, 1))
3311 macro_build ((char *) NULL
, counter
, ep
,
3312 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
3313 "t,r,j", reg
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
3314 p
= frag_var (rs_machine_dependent
, 8, 0,
3315 RELAX_ENCODE (4, 8, 0, 4, 0,
3316 mips_opts
.warn_about_macros
),
3317 ep
->X_add_symbol
, (offsetT
) 0, (char *) NULL
);
3319 macro_build_lui (p
, counter
, ep
, reg
);
3322 macro_build (p
, counter
, ep
,
3323 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
3324 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
3326 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
3330 /* If this is a reference to an external symbol, we want
3331 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3333 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3335 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
3336 If there is a constant, it must be added in after. */
3337 ex
.X_add_number
= ep
->X_add_number
;
3338 ep
->X_add_number
= 0;
3340 macro_build ((char *) NULL
, counter
, ep
,
3341 HAVE_32BIT_ADDRESSES
? "lw" : "ld",
3342 "t,o(b)", reg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
3343 macro_build ((char *) NULL
, counter
, (expressionS
*) NULL
, "nop", "");
3344 p
= frag_var (rs_machine_dependent
, 4, 0,
3345 RELAX_ENCODE (0, 4, -8, 0, 0, mips_opts
.warn_about_macros
),
3346 ep
->X_add_symbol
, (offsetT
) 0, (char *) NULL
);
3347 macro_build (p
, counter
, ep
,
3348 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
3349 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
3350 if (ex
.X_add_number
!= 0)
3352 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
3353 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
3354 ex
.X_op
= O_constant
;
3355 macro_build ((char *) NULL
, counter
, &ex
,
3356 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
3357 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
3360 else if (mips_pic
== SVR4_PIC
)
3365 /* This is the large GOT case. If this is a reference to an
3366 external symbol, we want
3367 lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
3369 lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16)
3370 Otherwise, for a reference to a local symbol, we want
3371 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3373 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
3374 If there is a constant, it must be added in after. */
3375 ex
.X_add_number
= ep
->X_add_number
;
3376 ep
->X_add_number
= 0;
3377 if (reg_needs_delay (GP
))
3382 macro_build ((char *) NULL
, counter
, ep
, "lui", "t,u", reg
,
3383 (int) BFD_RELOC_MIPS_GOT_HI16
);
3384 macro_build ((char *) NULL
, counter
, (expressionS
*) NULL
,
3385 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
3386 "d,v,t", reg
, reg
, GP
);
3387 macro_build ((char *) NULL
, counter
, ep
,
3388 HAVE_32BIT_ADDRESSES
? "lw" : "ld",
3389 "t,o(b)", reg
, (int) BFD_RELOC_MIPS_GOT_LO16
, reg
);
3390 p
= frag_var (rs_machine_dependent
, 12 + off
, 0,
3391 RELAX_ENCODE (12, 12 + off
, off
, 8 + off
, 0,
3392 mips_opts
.warn_about_macros
),
3393 ep
->X_add_symbol
, (offsetT
) 0, (char *) NULL
);
3396 /* We need a nop before loading from $gp. This special
3397 check is required because the lui which starts the main
3398 instruction stream does not refer to $gp, and so will not
3399 insert the nop which may be required. */
3400 macro_build (p
, counter
, (expressionS
*) NULL
, "nop", "");
3403 macro_build (p
, counter
, ep
, HAVE_32BIT_ADDRESSES
? "lw" : "ld",
3404 "t,o(b)", reg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
3406 macro_build (p
, counter
, (expressionS
*) NULL
, "nop", "");
3408 macro_build (p
, counter
, ep
, HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
3409 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
3410 if (ex
.X_add_number
!= 0)
3412 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
3413 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
3414 ex
.X_op
= O_constant
;
3415 macro_build ((char *) NULL
, counter
, &ex
,
3416 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
3417 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
3420 else if (mips_pic
== EMBEDDED_PIC
)
3423 addiu $reg,$gp,<sym> (BFD_RELOC_MIPS_GPREL)
3425 macro_build ((char *) NULL
, counter
, ep
,
3426 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
3427 "t,r,j", reg
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
3433 /* Move the contents of register SOURCE into register DEST. */
3436 move_register (counter
, dest
, source
)
3441 macro_build ((char *) NULL
, counter
, (expressionS
*) NULL
,
3442 HAVE_32BIT_GPRS
? "addu" : "daddu",
3443 "d,v,t", dest
, source
, 0);
3448 * This routine implements the seemingly endless macro or synthesized
3449 * instructions and addressing modes in the mips assembly language. Many
3450 * of these macros are simple and are similar to each other. These could
3451 * probably be handled by some kind of table or grammer aproach instead of
3452 * this verbose method. Others are not simple macros but are more like
3453 * optimizing code generation.
3454 * One interesting optimization is when several store macros appear
3455 * consecutivly that would load AT with the upper half of the same address.
3456 * The ensuing load upper instructions are ommited. This implies some kind
3457 * of global optimization. We currently only optimize within a single macro.
3458 * For many of the load and store macros if the address is specified as a
3459 * constant expression in the first 64k of memory (ie ld $2,0x4000c) we
3460 * first load register 'at' with zero and use it as the base register. The
3461 * mips assembler simply uses register $zero. Just one tiny optimization
3466 struct mips_cl_insn
*ip
;
3468 register int treg
, sreg
, dreg
, breg
;
3484 bfd_reloc_code_real_type r
;
3486 int hold_mips_optimize
;
3488 assert (! mips_opts
.mips16
);
3490 treg
= (ip
->insn_opcode
>> 16) & 0x1f;
3491 dreg
= (ip
->insn_opcode
>> 11) & 0x1f;
3492 sreg
= breg
= (ip
->insn_opcode
>> 21) & 0x1f;
3493 mask
= ip
->insn_mo
->mask
;
3495 expr1
.X_op
= O_constant
;
3496 expr1
.X_op_symbol
= NULL
;
3497 expr1
.X_add_symbol
= NULL
;
3498 expr1
.X_add_number
= 1;
3510 mips_emit_delays (true);
3511 ++mips_opts
.noreorder
;
3512 mips_any_noreorder
= 1;
3514 expr1
.X_add_number
= 8;
3515 macro_build ((char *) NULL
, &icnt
, &expr1
, "bgez", "s,p", sreg
);
3517 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
3519 move_register (&icnt
, dreg
, sreg
);
3520 macro_build ((char *) NULL
, &icnt
, NULL
,
3521 dbl
? "dsub" : "sub", "d,v,t", dreg
, 0, sreg
);
3523 --mips_opts
.noreorder
;
3544 if (imm_expr
.X_op
== O_constant
3545 && imm_expr
.X_add_number
>= -0x8000
3546 && imm_expr
.X_add_number
< 0x8000)
3548 macro_build ((char *) NULL
, &icnt
, &imm_expr
, s
, "t,r,j", treg
, sreg
,
3549 (int) BFD_RELOC_LO16
);
3552 load_register (&icnt
, AT
, &imm_expr
, dbl
);
3553 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "d,v,t", treg
, sreg
, AT
);
3572 if (imm_expr
.X_op
== O_constant
3573 && imm_expr
.X_add_number
>= 0
3574 && imm_expr
.X_add_number
< 0x10000)
3576 if (mask
!= M_NOR_I
)
3577 macro_build ((char *) NULL
, &icnt
, &imm_expr
, s
, "t,r,i", treg
,
3578 sreg
, (int) BFD_RELOC_LO16
);
3581 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "ori", "t,r,i",
3582 treg
, sreg
, (int) BFD_RELOC_LO16
);
3583 macro_build ((char *) NULL
, &icnt
, NULL
, "nor", "d,v,t",
3589 load_register (&icnt
, AT
, &imm_expr
, 0);
3590 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "d,v,t", treg
, sreg
, AT
);
3607 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
3609 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "s,t,p", sreg
,
3613 load_register (&icnt
, AT
, &imm_expr
, 0);
3614 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "s,t,p", sreg
, AT
);
3622 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3623 likely
? "bgezl" : "bgez",
3629 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3630 likely
? "blezl" : "blez",
3634 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", AT
, sreg
, treg
);
3635 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3636 likely
? "beql" : "beq", "s,t,p", AT
, 0);
3642 /* check for > max integer */
3643 maxnum
= 0x7fffffff;
3644 if (HAVE_64BIT_GPRS
&& sizeof (maxnum
) > 4)
3651 if (imm_expr
.X_op
== O_constant
3652 && imm_expr
.X_add_number
>= maxnum
3653 && (HAVE_32BIT_GPRS
|| sizeof (maxnum
) > 4))
3656 /* result is always false */
3660 as_warn (_("Branch %s is always false (nop)"),
3662 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
3667 as_warn (_("Branch likely %s is always false"),
3669 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "bnel",
3674 if (imm_expr
.X_op
!= O_constant
)
3675 as_bad (_("Unsupported large constant"));
3676 imm_expr
.X_add_number
++;
3680 if (mask
== M_BGEL_I
)
3682 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
3684 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3685 likely
? "bgezl" : "bgez", "s,p", sreg
);
3688 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
3690 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3691 likely
? "bgtzl" : "bgtz", "s,p", sreg
);
3694 maxnum
= 0x7fffffff;
3695 if (HAVE_64BIT_GPRS
&& sizeof (maxnum
) > 4)
3702 maxnum
= - maxnum
- 1;
3703 if (imm_expr
.X_op
== O_constant
3704 && imm_expr
.X_add_number
<= maxnum
3705 && (HAVE_32BIT_GPRS
|| sizeof (maxnum
) > 4))
3708 /* result is always true */
3709 as_warn (_("Branch %s is always true"), ip
->insn_mo
->name
);
3710 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "b", "p");
3713 set_at (&icnt
, sreg
, 0);
3714 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3715 likely
? "beql" : "beq", "s,t,p", AT
, 0);
3725 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3726 likely
? "beql" : "beq", "s,t,p", 0, treg
);
3729 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", AT
, sreg
,
3731 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3732 likely
? "beql" : "beq", "s,t,p", AT
, 0);
3740 && imm_expr
.X_op
== O_constant
3741 && imm_expr
.X_add_number
== 0xffffffff))
3743 if (imm_expr
.X_op
!= O_constant
)
3744 as_bad (_("Unsupported large constant"));
3745 imm_expr
.X_add_number
++;
3749 if (mask
== M_BGEUL_I
)
3751 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
3753 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
3755 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3756 likely
? "bnel" : "bne", "s,t,p", sreg
, 0);
3759 set_at (&icnt
, sreg
, 1);
3760 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3761 likely
? "beql" : "beq", "s,t,p", AT
, 0);
3769 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3770 likely
? "bgtzl" : "bgtz", "s,p", sreg
);
3775 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3776 likely
? "bltzl" : "bltz", "s,p", treg
);
3779 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", AT
, treg
, sreg
);
3780 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3781 likely
? "bnel" : "bne", "s,t,p", AT
, 0);
3789 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3790 likely
? "bnel" : "bne", "s,t,p", sreg
, 0);
3795 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", AT
, treg
,
3797 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3798 likely
? "bnel" : "bne", "s,t,p", AT
, 0);
3806 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3807 likely
? "blezl" : "blez", "s,p", sreg
);
3812 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3813 likely
? "bgezl" : "bgez", "s,p", treg
);
3816 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", AT
, treg
, sreg
);
3817 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3818 likely
? "beql" : "beq", "s,t,p", AT
, 0);
3824 maxnum
= 0x7fffffff;
3825 if (HAVE_64BIT_GPRS
&& sizeof (maxnum
) > 4)
3832 if (imm_expr
.X_op
== O_constant
3833 && imm_expr
.X_add_number
>= maxnum
3834 && (HAVE_32BIT_GPRS
|| sizeof (maxnum
) > 4))
3836 if (imm_expr
.X_op
!= O_constant
)
3837 as_bad (_("Unsupported large constant"));
3838 imm_expr
.X_add_number
++;
3842 if (mask
== M_BLTL_I
)
3844 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
3846 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3847 likely
? "bltzl" : "bltz", "s,p", sreg
);
3850 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
3852 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3853 likely
? "blezl" : "blez", "s,p", sreg
);
3856 set_at (&icnt
, sreg
, 0);
3857 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3858 likely
? "bnel" : "bne", "s,t,p", AT
, 0);
3866 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3867 likely
? "beql" : "beq", "s,t,p", sreg
, 0);
3872 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", AT
, treg
,
3874 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3875 likely
? "beql" : "beq", "s,t,p", AT
, 0);
3883 && imm_expr
.X_op
== O_constant
3884 && imm_expr
.X_add_number
== 0xffffffff))
3886 if (imm_expr
.X_op
!= O_constant
)
3887 as_bad (_("Unsupported large constant"));
3888 imm_expr
.X_add_number
++;
3892 if (mask
== M_BLTUL_I
)
3894 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
3896 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
3898 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3899 likely
? "beql" : "beq",
3903 set_at (&icnt
, sreg
, 1);
3904 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3905 likely
? "bnel" : "bne", "s,t,p", AT
, 0);
3913 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3914 likely
? "bltzl" : "bltz", "s,p", sreg
);
3919 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3920 likely
? "bgtzl" : "bgtz", "s,p", treg
);
3923 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", AT
, sreg
, treg
);
3924 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3925 likely
? "bnel" : "bne", "s,t,p", AT
, 0);
3935 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3936 likely
? "bnel" : "bne", "s,t,p", 0, treg
);
3939 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", AT
, sreg
,
3941 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3942 likely
? "bnel" : "bne", "s,t,p", AT
, 0);
3957 as_warn (_("Divide by zero."));
3959 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", 0, 0);
3961 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 7);
3965 mips_emit_delays (true);
3966 ++mips_opts
.noreorder
;
3967 mips_any_noreorder
= 1;
3970 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", treg
, 0);
3971 macro_build ((char *) NULL
, &icnt
, NULL
,
3972 dbl
? "ddiv" : "div", "z,s,t", sreg
, treg
);
3976 expr1
.X_add_number
= 8;
3977 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", treg
, 0);
3978 macro_build ((char *) NULL
, &icnt
, NULL
,
3979 dbl
? "ddiv" : "div", "z,s,t", sreg
, treg
);
3980 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 7);
3982 expr1
.X_add_number
= -1;
3983 macro_build ((char *) NULL
, &icnt
, &expr1
,
3984 dbl
? "daddiu" : "addiu",
3985 "t,r,j", AT
, 0, (int) BFD_RELOC_LO16
);
3986 expr1
.X_add_number
= mips_trap
? (dbl
? 12 : 8) : (dbl
? 20 : 16);
3987 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", treg
, AT
);
3990 expr1
.X_add_number
= 1;
3991 macro_build ((char *) NULL
, &icnt
, &expr1
, "daddiu", "t,r,j", AT
, 0,
3992 (int) BFD_RELOC_LO16
);
3993 macro_build ((char *) NULL
, &icnt
, NULL
, "dsll32", "d,w,<", AT
, AT
,
3998 expr1
.X_add_number
= 0x80000000;
3999 macro_build ((char *) NULL
, &icnt
, &expr1
, "lui", "t,u", AT
,
4000 (int) BFD_RELOC_HI16
);
4004 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", sreg
, AT
);
4005 /* We want to close the noreorder block as soon as possible, so
4006 that later insns are available for delay slot filling. */
4007 --mips_opts
.noreorder
;
4011 expr1
.X_add_number
= 8;
4012 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", sreg
, AT
);
4013 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
4015 /* We want to close the noreorder block as soon as possible, so
4016 that later insns are available for delay slot filling. */
4017 --mips_opts
.noreorder
;
4019 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 6);
4021 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d", dreg
);
4060 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
4062 as_warn (_("Divide by zero."));
4064 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", 0, 0);
4066 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 7);
4069 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
4071 if (strcmp (s2
, "mflo") == 0)
4072 move_register (&icnt
, dreg
, sreg
);
4074 move_register (&icnt
, dreg
, 0);
4077 if (imm_expr
.X_op
== O_constant
4078 && imm_expr
.X_add_number
== -1
4079 && s
[strlen (s
) - 1] != 'u')
4081 if (strcmp (s2
, "mflo") == 0)
4083 macro_build ((char *) NULL
, &icnt
, NULL
, dbl
? "dneg" : "neg",
4087 move_register (&icnt
, dreg
, 0);
4091 load_register (&icnt
, AT
, &imm_expr
, dbl
);
4092 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "z,s,t", sreg
, AT
);
4093 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "d", dreg
);
4112 mips_emit_delays (true);
4113 ++mips_opts
.noreorder
;
4114 mips_any_noreorder
= 1;
4117 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", treg
, 0);
4118 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "z,s,t", sreg
, treg
);
4119 /* We want to close the noreorder block as soon as possible, so
4120 that later insns are available for delay slot filling. */
4121 --mips_opts
.noreorder
;
4125 expr1
.X_add_number
= 8;
4126 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", treg
, 0);
4127 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "z,s,t", sreg
, treg
);
4129 /* We want to close the noreorder block as soon as possible, so
4130 that later insns are available for delay slot filling. */
4131 --mips_opts
.noreorder
;
4132 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 7);
4134 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "d", dreg
);
4140 /* Load the address of a symbol into a register. If breg is not
4141 zero, we then add a base register to it. */
4143 /* When generating embedded PIC code, we permit expressions of
4146 where bar is an address in the current section. These are used
4147 when getting the addresses of functions. We don't permit
4148 X_add_number to be non-zero, because if the symbol is
4149 external the relaxing code needs to know that any addend is
4150 purely the offset to X_op_symbol. */
4151 if (mips_pic
== EMBEDDED_PIC
4152 && offset_expr
.X_op
== O_subtract
4153 && (symbol_constant_p (offset_expr
.X_op_symbol
)
4154 ? S_GET_SEGMENT (offset_expr
.X_op_symbol
) == now_seg
4155 : (symbol_equated_p (offset_expr
.X_op_symbol
)
4157 (symbol_get_value_expression (offset_expr
.X_op_symbol
)
4161 && (offset_expr
.X_add_number
== 0
4162 || OUTPUT_FLAVOR
== bfd_target_elf_flavour
))
4164 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
4165 treg
, (int) BFD_RELOC_PCREL_HI16_S
);
4166 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4167 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
4168 "t,r,j", treg
, treg
, (int) BFD_RELOC_PCREL_LO16
);
4172 if (offset_expr
.X_op
!= O_symbol
4173 && offset_expr
.X_op
!= O_constant
)
4175 as_bad (_("expression too complex"));
4176 offset_expr
.X_op
= O_constant
;
4190 if (offset_expr
.X_op
== O_constant
)
4191 load_register (&icnt
, tempreg
, &offset_expr
, dbl
);
4192 else if (mips_pic
== NO_PIC
)
4194 /* If this is a reference to an GP relative symbol, we want
4195 addiu $tempreg,$gp,<sym> (BFD_RELOC_MIPS_GPREL)
4197 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
4198 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
4199 If we have a constant, we need two instructions anyhow,
4200 so we may as well always use the latter form. */
4201 if ((valueT
) offset_expr
.X_add_number
>= MAX_GPREL_OFFSET
4202 || nopic_need_relax (offset_expr
.X_add_symbol
, 1))
4207 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4208 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
4209 "t,r,j", tempreg
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
4210 p
= frag_var (rs_machine_dependent
, 8, 0,
4211 RELAX_ENCODE (4, 8, 0, 4, 0,
4212 mips_opts
.warn_about_macros
),
4213 offset_expr
.X_add_symbol
, (offsetT
) 0,
4216 macro_build_lui (p
, &icnt
, &offset_expr
, tempreg
);
4219 macro_build (p
, &icnt
, &offset_expr
,
4220 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
4221 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
4223 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
4225 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT16
;
4227 /* If this is a reference to an external symbol, and there
4228 is no constant, we want
4229 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4230 or if tempreg is PIC_CALL_REG
4231 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
4232 For a local symbol, we want
4233 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4235 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
4237 If we have a small constant, and this is a reference to
4238 an external symbol, we want
4239 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4241 addiu $tempreg,$tempreg,<constant>
4242 For a local symbol, we want the same instruction
4243 sequence, but we output a BFD_RELOC_LO16 reloc on the
4246 If we have a large constant, and this is a reference to
4247 an external symbol, we want
4248 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4249 lui $at,<hiconstant>
4250 addiu $at,$at,<loconstant>
4251 addu $tempreg,$tempreg,$at
4252 For a local symbol, we want the same instruction
4253 sequence, but we output a BFD_RELOC_LO16 reloc on the
4254 addiu instruction. */
4255 expr1
.X_add_number
= offset_expr
.X_add_number
;
4256 offset_expr
.X_add_number
= 0;
4258 if (expr1
.X_add_number
== 0 && tempreg
== PIC_CALL_REG
)
4259 lw_reloc_type
= (int) BFD_RELOC_MIPS_CALL16
;
4260 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4262 "t,o(b)", tempreg
, lw_reloc_type
, GP
);
4263 if (expr1
.X_add_number
== 0)
4271 /* We're going to put in an addu instruction using
4272 tempreg, so we may as well insert the nop right
4274 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4278 p
= frag_var (rs_machine_dependent
, 8 - off
, 0,
4279 RELAX_ENCODE (0, 8 - off
, -4 - off
, 4 - off
, 0,
4281 ? mips_opts
.warn_about_macros
4283 offset_expr
.X_add_symbol
, (offsetT
) 0,
4287 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4290 macro_build (p
, &icnt
, &expr1
,
4291 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
4292 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
4293 /* FIXME: If breg == 0, and the next instruction uses
4294 $tempreg, then if this variant case is used an extra
4295 nop will be generated. */
4297 else if (expr1
.X_add_number
>= -0x8000
4298 && expr1
.X_add_number
< 0x8000)
4300 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4302 macro_build ((char *) NULL
, &icnt
, &expr1
,
4303 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
4304 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
4305 (void) frag_var (rs_machine_dependent
, 0, 0,
4306 RELAX_ENCODE (0, 0, -12, -4, 0, 0),
4307 offset_expr
.X_add_symbol
, (offsetT
) 0,
4314 /* If we are going to add in a base register, and the
4315 target register and the base register are the same,
4316 then we are using AT as a temporary register. Since
4317 we want to load the constant into AT, we add our
4318 current AT (from the global offset table) and the
4319 register into the register now, and pretend we were
4320 not using a base register. */
4325 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4327 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4328 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
4329 "d,v,t", treg
, AT
, breg
);
4335 /* Set mips_optimize around the lui instruction to avoid
4336 inserting an unnecessary nop after the lw. */
4337 hold_mips_optimize
= mips_optimize
;
4339 macro_build_lui ((char *) NULL
, &icnt
, &expr1
, AT
);
4340 mips_optimize
= hold_mips_optimize
;
4342 macro_build ((char *) NULL
, &icnt
, &expr1
,
4343 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
4344 "t,r,j", AT
, AT
, (int) BFD_RELOC_LO16
);
4345 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4346 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
4347 "d,v,t", tempreg
, tempreg
, AT
);
4348 (void) frag_var (rs_machine_dependent
, 0, 0,
4349 RELAX_ENCODE (0, 0, -16 + off1
, -8, 0, 0),
4350 offset_expr
.X_add_symbol
, (offsetT
) 0,
4355 else if (mips_pic
== SVR4_PIC
)
4358 int lui_reloc_type
= (int) BFD_RELOC_MIPS_GOT_HI16
;
4359 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT_LO16
;
4361 /* This is the large GOT case. If this is a reference to an
4362 external symbol, and there is no constant, we want
4363 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
4364 addu $tempreg,$tempreg,$gp
4365 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
4366 or if tempreg is PIC_CALL_REG
4367 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
4368 addu $tempreg,$tempreg,$gp
4369 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
4370 For a local symbol, we want
4371 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4373 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
4375 If we have a small constant, and this is a reference to
4376 an external symbol, we want
4377 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
4378 addu $tempreg,$tempreg,$gp
4379 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
4381 addiu $tempreg,$tempreg,<constant>
4382 For a local symbol, we want
4383 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4385 addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16)
4387 If we have a large constant, and this is a reference to
4388 an external symbol, we want
4389 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
4390 addu $tempreg,$tempreg,$gp
4391 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
4392 lui $at,<hiconstant>
4393 addiu $at,$at,<loconstant>
4394 addu $tempreg,$tempreg,$at
4395 For a local symbol, we want
4396 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4397 lui $at,<hiconstant>
4398 addiu $at,$at,<loconstant> (BFD_RELOC_LO16)
4399 addu $tempreg,$tempreg,$at
4401 expr1
.X_add_number
= offset_expr
.X_add_number
;
4402 offset_expr
.X_add_number
= 0;
4404 if (reg_needs_delay (GP
))
4408 if (expr1
.X_add_number
== 0 && tempreg
== PIC_CALL_REG
)
4410 lui_reloc_type
= (int) BFD_RELOC_MIPS_CALL_HI16
;
4411 lw_reloc_type
= (int) BFD_RELOC_MIPS_CALL_LO16
;
4413 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
4414 tempreg
, lui_reloc_type
);
4415 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4416 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
4417 "d,v,t", tempreg
, tempreg
, GP
);
4418 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4420 "t,o(b)", tempreg
, lw_reloc_type
, tempreg
);
4421 if (expr1
.X_add_number
== 0)
4429 /* We're going to put in an addu instruction using
4430 tempreg, so we may as well insert the nop right
4432 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4437 p
= frag_var (rs_machine_dependent
, 12 + gpdel
, 0,
4438 RELAX_ENCODE (12 + off
, 12 + gpdel
, gpdel
,
4441 ? mips_opts
.warn_about_macros
4443 offset_expr
.X_add_symbol
, (offsetT
) 0,
4446 else if (expr1
.X_add_number
>= -0x8000
4447 && expr1
.X_add_number
< 0x8000)
4449 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4451 macro_build ((char *) NULL
, &icnt
, &expr1
,
4452 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
4453 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
4455 p
= frag_var (rs_machine_dependent
, 12 + gpdel
, 0,
4456 RELAX_ENCODE (20, 12 + gpdel
, gpdel
, 8 + gpdel
, 0,
4458 ? mips_opts
.warn_about_macros
4460 offset_expr
.X_add_symbol
, (offsetT
) 0,
4467 /* If we are going to add in a base register, and the
4468 target register and the base register are the same,
4469 then we are using AT as a temporary register. Since
4470 we want to load the constant into AT, we add our
4471 current AT (from the global offset table) and the
4472 register into the register now, and pretend we were
4473 not using a base register. */
4481 assert (tempreg
== AT
);
4482 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4484 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4485 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
4486 "d,v,t", treg
, AT
, breg
);
4491 /* Set mips_optimize around the lui instruction to avoid
4492 inserting an unnecessary nop after the lw. */
4493 hold_mips_optimize
= mips_optimize
;
4495 macro_build_lui ((char *) NULL
, &icnt
, &expr1
, AT
);
4496 mips_optimize
= hold_mips_optimize
;
4498 macro_build ((char *) NULL
, &icnt
, &expr1
,
4499 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
4500 "t,r,j", AT
, AT
, (int) BFD_RELOC_LO16
);
4501 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4502 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
4503 "d,v,t", dreg
, dreg
, AT
);
4505 p
= frag_var (rs_machine_dependent
, 16 + gpdel
+ adj
, 0,
4506 RELAX_ENCODE (24 + adj
, 16 + gpdel
+ adj
, gpdel
,
4509 ? mips_opts
.warn_about_macros
4511 offset_expr
.X_add_symbol
, (offsetT
) 0,
4519 /* This is needed because this instruction uses $gp, but
4520 the first instruction on the main stream does not. */
4521 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4524 macro_build (p
, &icnt
, &offset_expr
,
4526 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
4528 if (expr1
.X_add_number
>= -0x8000
4529 && expr1
.X_add_number
< 0x8000)
4531 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4533 macro_build (p
, &icnt
, &expr1
,
4534 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
4535 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
4536 /* FIXME: If add_number is 0, and there was no base
4537 register, the external symbol case ended with a load,
4538 so if the symbol turns out to not be external, and
4539 the next instruction uses tempreg, an unnecessary nop
4540 will be inserted. */
4546 /* We must add in the base register now, as in the
4547 external symbol case. */
4548 assert (tempreg
== AT
);
4549 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4551 macro_build (p
, &icnt
, (expressionS
*) NULL
,
4552 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
4553 "d,v,t", treg
, AT
, breg
);
4556 /* We set breg to 0 because we have arranged to add
4557 it in in both cases. */
4561 macro_build_lui (p
, &icnt
, &expr1
, AT
);
4563 macro_build (p
, &icnt
, &expr1
,
4564 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
4565 "t,r,j", AT
, AT
, (int) BFD_RELOC_LO16
);
4567 macro_build (p
, &icnt
, (expressionS
*) NULL
,
4568 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
4569 "d,v,t", tempreg
, tempreg
, AT
);
4573 else if (mips_pic
== EMBEDDED_PIC
)
4576 addiu $tempreg,$gp,<sym> (BFD_RELOC_MIPS_GPREL)
4578 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4579 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
4580 "t,r,j", tempreg
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
4586 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4587 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
4588 "d,v,t", treg
, tempreg
, breg
);
4596 /* The j instruction may not be used in PIC code, since it
4597 requires an absolute address. We convert it to a b
4599 if (mips_pic
== NO_PIC
)
4600 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "j", "a");
4602 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "b", "p");
4605 /* The jal instructions must be handled as macros because when
4606 generating PIC code they expand to multi-instruction
4607 sequences. Normally they are simple instructions. */
4612 if (mips_pic
== NO_PIC
4613 || mips_pic
== EMBEDDED_PIC
)
4614 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "jalr",
4616 else if (mips_pic
== SVR4_PIC
)
4618 if (sreg
!= PIC_CALL_REG
)
4619 as_warn (_("MIPS PIC call to register other than $25"));
4621 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "jalr",
4623 if (mips_cprestore_offset
< 0)
4624 as_warn (_("No .cprestore pseudo-op used in PIC code"));
4627 expr1
.X_add_number
= mips_cprestore_offset
;
4628 macro_build ((char *) NULL
, &icnt
, &expr1
,
4629 HAVE_32BIT_ADDRESSES
? "lw" : "ld",
4630 "t,o(b)", GP
, (int) BFD_RELOC_LO16
, mips_frame_reg
);
4639 if (mips_pic
== NO_PIC
)
4640 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "jal", "a");
4641 else if (mips_pic
== SVR4_PIC
)
4643 /* If this is a reference to an external symbol, and we are
4644 using a small GOT, we want
4645 lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
4649 lw $gp,cprestore($sp)
4650 The cprestore value is set using the .cprestore
4651 pseudo-op. If we are using a big GOT, we want
4652 lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16)
4654 lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16)
4658 lw $gp,cprestore($sp)
4659 If the symbol is not external, we want
4660 lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4662 addiu $25,$25,<sym> (BFD_RELOC_LO16)
4665 lw $gp,cprestore($sp) */
4669 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4670 HAVE_32BIT_ADDRESSES
? "lw" : "ld",
4671 "t,o(b)", PIC_CALL_REG
,
4672 (int) BFD_RELOC_MIPS_CALL16
, GP
);
4673 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4675 p
= frag_var (rs_machine_dependent
, 4, 0,
4676 RELAX_ENCODE (0, 4, -8, 0, 0, 0),
4677 offset_expr
.X_add_symbol
, (offsetT
) 0,
4684 if (reg_needs_delay (GP
))
4688 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
4689 PIC_CALL_REG
, (int) BFD_RELOC_MIPS_CALL_HI16
);
4690 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4691 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
4692 "d,v,t", PIC_CALL_REG
, PIC_CALL_REG
, GP
);
4693 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4694 HAVE_32BIT_ADDRESSES
? "lw" : "ld",
4695 "t,o(b)", PIC_CALL_REG
,
4696 (int) BFD_RELOC_MIPS_CALL_LO16
, PIC_CALL_REG
);
4697 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4699 p
= frag_var (rs_machine_dependent
, 12 + gpdel
, 0,
4700 RELAX_ENCODE (16, 12 + gpdel
, gpdel
, 8 + gpdel
,
4702 offset_expr
.X_add_symbol
, (offsetT
) 0,
4706 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4709 macro_build (p
, &icnt
, &offset_expr
,
4710 HAVE_32BIT_ADDRESSES
? "lw" : "ld",
4711 "t,o(b)", PIC_CALL_REG
,
4712 (int) BFD_RELOC_MIPS_GOT16
, GP
);
4714 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4717 macro_build (p
, &icnt
, &offset_expr
,
4718 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
4719 "t,r,j", PIC_CALL_REG
, PIC_CALL_REG
,
4720 (int) BFD_RELOC_LO16
);
4721 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4722 "jalr", "s", PIC_CALL_REG
);
4723 if (mips_cprestore_offset
< 0)
4724 as_warn (_("No .cprestore pseudo-op used in PIC code"));
4727 if (mips_opts
.noreorder
)
4728 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4730 expr1
.X_add_number
= mips_cprestore_offset
;
4731 macro_build ((char *) NULL
, &icnt
, &expr1
,
4732 HAVE_32BIT_ADDRESSES
? "lw" : "ld",
4733 "t,o(b)", GP
, (int) BFD_RELOC_LO16
,
4737 else if (mips_pic
== EMBEDDED_PIC
)
4739 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "bal", "p");
4740 /* The linker may expand the call to a longer sequence which
4741 uses $at, so we must break rather than return. */
4766 /* Itbl support may require additional care here. */
4771 /* Itbl support may require additional care here. */
4776 /* Itbl support may require additional care here. */
4781 /* Itbl support may require additional care here. */
4793 if (mips_arch
== CPU_R4650
)
4795 as_bad (_("opcode not supported on this processor"));
4799 /* Itbl support may require additional care here. */
4804 /* Itbl support may require additional care here. */
4809 /* Itbl support may require additional care here. */
4829 if (breg
== treg
|| coproc
|| lr
)
4851 /* Itbl support may require additional care here. */
4856 /* Itbl support may require additional care here. */
4861 /* Itbl support may require additional care here. */
4866 /* Itbl support may require additional care here. */
4882 if (mips_arch
== CPU_R4650
)
4884 as_bad (_("opcode not supported on this processor"));
4889 /* Itbl support may require additional care here. */
4893 /* Itbl support may require additional care here. */
4898 /* Itbl support may require additional care here. */
4910 /* Itbl support may require additional care here. */
4911 if (mask
== M_LWC1_AB
4912 || mask
== M_SWC1_AB
4913 || mask
== M_LDC1_AB
4914 || mask
== M_SDC1_AB
4923 if (offset_expr
.X_op
!= O_constant
4924 && offset_expr
.X_op
!= O_symbol
)
4926 as_bad (_("expression too complex"));
4927 offset_expr
.X_op
= O_constant
;
4930 /* A constant expression in PIC code can be handled just as it
4931 is in non PIC code. */
4932 if (mips_pic
== NO_PIC
4933 || offset_expr
.X_op
== O_constant
)
4935 /* If this is a reference to a GP relative symbol, and there
4936 is no base register, we want
4937 <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL)
4938 Otherwise, if there is no base register, we want
4939 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
4940 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
4941 If we have a constant, we need two instructions anyhow,
4942 so we always use the latter form.
4944 If we have a base register, and this is a reference to a
4945 GP relative symbol, we want
4946 addu $tempreg,$breg,$gp
4947 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GPREL)
4949 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
4950 addu $tempreg,$tempreg,$breg
4951 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
4952 With a constant we always use the latter case. */
4955 if ((valueT
) offset_expr
.X_add_number
>= MAX_GPREL_OFFSET
4956 || nopic_need_relax (offset_expr
.X_add_symbol
, 1))
4961 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
4962 treg
, (int) BFD_RELOC_MIPS_GPREL
, GP
);
4963 p
= frag_var (rs_machine_dependent
, 8, 0,
4964 RELAX_ENCODE (4, 8, 0, 4, 0,
4965 (mips_opts
.warn_about_macros
4967 && mips_opts
.noat
))),
4968 offset_expr
.X_add_symbol
, (offsetT
) 0,
4972 macro_build_lui (p
, &icnt
, &offset_expr
, tempreg
);
4975 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
, treg
,
4976 (int) BFD_RELOC_LO16
, tempreg
);
4980 if ((valueT
) offset_expr
.X_add_number
>= MAX_GPREL_OFFSET
4981 || nopic_need_relax (offset_expr
.X_add_symbol
, 1))
4986 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4987 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
4988 "d,v,t", tempreg
, breg
, GP
);
4989 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
4990 treg
, (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
4991 p
= frag_var (rs_machine_dependent
, 12, 0,
4992 RELAX_ENCODE (8, 12, 0, 8, 0, 0),
4993 offset_expr
.X_add_symbol
, (offsetT
) 0,
4996 macro_build_lui (p
, &icnt
, &offset_expr
, tempreg
);
4999 macro_build (p
, &icnt
, (expressionS
*) NULL
,
5000 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
5001 "d,v,t", tempreg
, tempreg
, breg
);
5004 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
, treg
,
5005 (int) BFD_RELOC_LO16
, tempreg
);
5008 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
5010 /* If this is a reference to an external symbol, we want
5011 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5013 <op> $treg,0($tempreg)
5015 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5017 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
5018 <op> $treg,0($tempreg)
5019 If there is a base register, we add it to $tempreg before
5020 the <op>. If there is a constant, we stick it in the
5021 <op> instruction. We don't handle constants larger than
5022 16 bits, because we have no way to load the upper 16 bits
5023 (actually, we could handle them for the subset of cases
5024 in which we are not using $at). */
5025 assert (offset_expr
.X_op
== O_symbol
);
5026 expr1
.X_add_number
= offset_expr
.X_add_number
;
5027 offset_expr
.X_add_number
= 0;
5028 if (expr1
.X_add_number
< -0x8000
5029 || expr1
.X_add_number
>= 0x8000)
5030 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
5032 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5033 HAVE_32BIT_ADDRESSES
? "lw" : "ld",
5034 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
5035 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
5036 p
= frag_var (rs_machine_dependent
, 4, 0,
5037 RELAX_ENCODE (0, 4, -8, 0, 0, 0),
5038 offset_expr
.X_add_symbol
, (offsetT
) 0,
5040 macro_build (p
, &icnt
, &offset_expr
,
5041 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
5042 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
5044 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5045 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
5046 "d,v,t", tempreg
, tempreg
, breg
);
5047 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
, treg
,
5048 (int) BFD_RELOC_LO16
, tempreg
);
5050 else if (mips_pic
== SVR4_PIC
)
5054 /* If this is a reference to an external symbol, we want
5055 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5056 addu $tempreg,$tempreg,$gp
5057 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5058 <op> $treg,0($tempreg)
5060 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5062 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
5063 <op> $treg,0($tempreg)
5064 If there is a base register, we add it to $tempreg before
5065 the <op>. If there is a constant, we stick it in the
5066 <op> instruction. We don't handle constants larger than
5067 16 bits, because we have no way to load the upper 16 bits
5068 (actually, we could handle them for the subset of cases
5069 in which we are not using $at). */
5070 assert (offset_expr
.X_op
== O_symbol
);
5071 expr1
.X_add_number
= offset_expr
.X_add_number
;
5072 offset_expr
.X_add_number
= 0;
5073 if (expr1
.X_add_number
< -0x8000
5074 || expr1
.X_add_number
>= 0x8000)
5075 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
5076 if (reg_needs_delay (GP
))
5081 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
5082 tempreg
, (int) BFD_RELOC_MIPS_GOT_HI16
);
5083 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5084 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
5085 "d,v,t", tempreg
, tempreg
, GP
);
5086 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5087 HAVE_32BIT_ADDRESSES
? "lw" : "ld",
5088 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT_LO16
,
5090 p
= frag_var (rs_machine_dependent
, 12 + gpdel
, 0,
5091 RELAX_ENCODE (12, 12 + gpdel
, gpdel
, 8 + gpdel
, 0, 0),
5092 offset_expr
.X_add_symbol
, (offsetT
) 0, (char *) NULL
);
5095 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
5098 macro_build (p
, &icnt
, &offset_expr
,
5099 HAVE_32BIT_ADDRESSES
? "lw" : "ld",
5100 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
5102 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
5104 macro_build (p
, &icnt
, &offset_expr
,
5105 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
5106 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
5108 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5109 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
5110 "d,v,t", tempreg
, tempreg
, breg
);
5111 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
, treg
,
5112 (int) BFD_RELOC_LO16
, tempreg
);
5114 else if (mips_pic
== EMBEDDED_PIC
)
5116 /* If there is no base register, we want
5117 <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL)
5118 If there is a base register, we want
5119 addu $tempreg,$breg,$gp
5120 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GPREL)
5122 assert (offset_expr
.X_op
== O_symbol
);
5125 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
5126 treg
, (int) BFD_RELOC_MIPS_GPREL
, GP
);
5131 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5132 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
5133 "d,v,t", tempreg
, breg
, GP
);
5134 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
5135 treg
, (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
5148 load_register (&icnt
, treg
, &imm_expr
, 0);
5152 load_register (&icnt
, treg
, &imm_expr
, 1);
5156 if (imm_expr
.X_op
== O_constant
)
5158 load_register (&icnt
, AT
, &imm_expr
, 0);
5159 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5160 "mtc1", "t,G", AT
, treg
);
5165 assert (offset_expr
.X_op
== O_symbol
5166 && strcmp (segment_name (S_GET_SEGMENT
5167 (offset_expr
.X_add_symbol
)),
5169 && offset_expr
.X_add_number
== 0);
5170 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lwc1", "T,o(b)",
5171 treg
, (int) BFD_RELOC_MIPS_LITERAL
, GP
);
5176 /* Check if we have a constant in IMM_EXPR. If the GPRs are 64 bits
5177 wide, IMM_EXPR is the entire value. Otherwise IMM_EXPR is the high
5178 order 32 bits of the value and the low order 32 bits are either
5179 zero or in OFFSET_EXPR. */
5180 if (imm_expr
.X_op
== O_constant
|| imm_expr
.X_op
== O_big
)
5182 if (HAVE_64BIT_GPRS
)
5183 load_register (&icnt
, treg
, &imm_expr
, 1);
5188 if (target_big_endian
)
5200 load_register (&icnt
, hreg
, &imm_expr
, 0);
5203 if (offset_expr
.X_op
== O_absent
)
5204 move_register (&icnt
, lreg
, 0);
5207 assert (offset_expr
.X_op
== O_constant
);
5208 load_register (&icnt
, lreg
, &offset_expr
, 0);
5215 /* We know that sym is in the .rdata section. First we get the
5216 upper 16 bits of the address. */
5217 if (mips_pic
== NO_PIC
)
5219 /* FIXME: This won't work for a 64 bit address. */
5220 macro_build_lui ((char *) NULL
, &icnt
, &offset_expr
, AT
);
5222 else if (mips_pic
== SVR4_PIC
)
5224 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5225 HAVE_32BIT_ADDRESSES
? "lw" : "ld",
5226 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
5228 else if (mips_pic
== EMBEDDED_PIC
)
5230 /* For embedded PIC we pick up the entire address off $gp in
5231 a single instruction. */
5232 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5233 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
5234 "t,r,j", AT
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
5235 offset_expr
.X_op
= O_constant
;
5236 offset_expr
.X_add_number
= 0;
5241 /* Now we load the register(s). */
5242 if (HAVE_64BIT_GPRS
)
5243 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "ld", "t,o(b)",
5244 treg
, (int) BFD_RELOC_LO16
, AT
);
5247 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lw", "t,o(b)",
5248 treg
, (int) BFD_RELOC_LO16
, AT
);
5251 /* FIXME: How in the world do we deal with the possible
5253 offset_expr
.X_add_number
+= 4;
5254 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lw", "t,o(b)",
5255 treg
+ 1, (int) BFD_RELOC_LO16
, AT
);
5259 /* To avoid confusion in tc_gen_reloc, we must ensure that this
5260 does not become a variant frag. */
5261 frag_wane (frag_now
);
5267 /* Check if we have a constant in IMM_EXPR. If the FPRs are 64 bits
5268 wide, IMM_EXPR is the entire value and the GPRs are known to be 64
5269 bits wide as well. Otherwise IMM_EXPR is the high order 32 bits of
5270 the value and the low order 32 bits are either zero or in
5272 if (imm_expr
.X_op
== O_constant
|| imm_expr
.X_op
== O_big
)
5274 load_register (&icnt
, AT
, &imm_expr
, HAVE_64BIT_FPRS
);
5275 if (HAVE_64BIT_FPRS
)
5277 assert (HAVE_64BIT_GPRS
);
5278 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5279 "dmtc1", "t,S", AT
, treg
);
5283 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5284 "mtc1", "t,G", AT
, treg
+ 1);
5285 if (offset_expr
.X_op
== O_absent
)
5286 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5287 "mtc1", "t,G", 0, treg
);
5290 assert (offset_expr
.X_op
== O_constant
);
5291 load_register (&icnt
, AT
, &offset_expr
, 0);
5292 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5293 "mtc1", "t,G", AT
, treg
);
5299 assert (offset_expr
.X_op
== O_symbol
5300 && offset_expr
.X_add_number
== 0);
5301 s
= segment_name (S_GET_SEGMENT (offset_expr
.X_add_symbol
));
5302 if (strcmp (s
, ".lit8") == 0)
5304 if (mips_opts
.isa
!= ISA_MIPS1
)
5306 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "ldc1",
5307 "T,o(b)", treg
, (int) BFD_RELOC_MIPS_LITERAL
, GP
);
5311 r
= BFD_RELOC_MIPS_LITERAL
;
5316 assert (strcmp (s
, RDATA_SECTION_NAME
) == 0);
5317 if (mips_pic
== SVR4_PIC
)
5318 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5319 HAVE_32BIT_ADDRESSES
? "lw" : "ld",
5320 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
5323 /* FIXME: This won't work for a 64 bit address. */
5324 macro_build_lui ((char *) NULL
, &icnt
, &offset_expr
, AT
);
5327 if (mips_opts
.isa
!= ISA_MIPS1
)
5329 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "ldc1",
5330 "T,o(b)", treg
, (int) BFD_RELOC_LO16
, AT
);
5332 /* To avoid confusion in tc_gen_reloc, we must ensure
5333 that this does not become a variant frag. */
5334 frag_wane (frag_now
);
5345 if (mips_arch
== CPU_R4650
)
5347 as_bad (_("opcode not supported on this processor"));
5350 /* Even on a big endian machine $fn comes before $fn+1. We have
5351 to adjust when loading from memory. */
5354 assert (mips_opts
.isa
== ISA_MIPS1
);
5355 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lwc1", "T,o(b)",
5356 target_big_endian
? treg
+ 1 : treg
,
5358 /* FIXME: A possible overflow which I don't know how to deal
5360 offset_expr
.X_add_number
+= 4;
5361 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lwc1", "T,o(b)",
5362 target_big_endian
? treg
: treg
+ 1,
5365 /* To avoid confusion in tc_gen_reloc, we must ensure that this
5366 does not become a variant frag. */
5367 frag_wane (frag_now
);
5376 * The MIPS assembler seems to check for X_add_number not
5377 * being double aligned and generating:
5380 * addiu at,at,%lo(foo+1)
5383 * But, the resulting address is the same after relocation so why
5384 * generate the extra instruction?
5386 if (mips_arch
== CPU_R4650
)
5388 as_bad (_("opcode not supported on this processor"));
5391 /* Itbl support may require additional care here. */
5393 if (mips_opts
.isa
!= ISA_MIPS1
)
5404 if (mips_arch
== CPU_R4650
)
5406 as_bad (_("opcode not supported on this processor"));
5410 if (mips_opts
.isa
!= ISA_MIPS1
)
5418 /* Itbl support may require additional care here. */
5423 if (HAVE_64BIT_GPRS
)
5434 if (HAVE_64BIT_GPRS
)
5444 if (offset_expr
.X_op
!= O_symbol
5445 && offset_expr
.X_op
!= O_constant
)
5447 as_bad (_("expression too complex"));
5448 offset_expr
.X_op
= O_constant
;
5451 /* Even on a big endian machine $fn comes before $fn+1. We have
5452 to adjust when loading from memory. We set coproc if we must
5453 load $fn+1 first. */
5454 /* Itbl support may require additional care here. */
5455 if (! target_big_endian
)
5458 if (mips_pic
== NO_PIC
5459 || offset_expr
.X_op
== O_constant
)
5461 /* If this is a reference to a GP relative symbol, we want
5462 <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL)
5463 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_MIPS_GPREL)
5464 If we have a base register, we use this
5466 <op> $treg,<sym>($at) (BFD_RELOC_MIPS_GPREL)
5467 <op> $treg+1,<sym>+4($at) (BFD_RELOC_MIPS_GPREL)
5468 If this is not a GP relative symbol, we want
5469 lui $at,<sym> (BFD_RELOC_HI16_S)
5470 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
5471 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
5472 If there is a base register, we add it to $at after the
5473 lui instruction. If there is a constant, we always use
5475 if ((valueT
) offset_expr
.X_add_number
>= MAX_GPREL_OFFSET
5476 || nopic_need_relax (offset_expr
.X_add_symbol
, 1))
5495 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5496 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
5497 "d,v,t", AT
, breg
, GP
);
5503 /* Itbl support may require additional care here. */
5504 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
5505 coproc
? treg
+ 1 : treg
,
5506 (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
5507 offset_expr
.X_add_number
+= 4;
5509 /* Set mips_optimize to 2 to avoid inserting an
5511 hold_mips_optimize
= mips_optimize
;
5513 /* Itbl support may require additional care here. */
5514 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
5515 coproc
? treg
: treg
+ 1,
5516 (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
5517 mips_optimize
= hold_mips_optimize
;
5519 p
= frag_var (rs_machine_dependent
, 12 + off
, 0,
5520 RELAX_ENCODE (8 + off
, 12 + off
, 0, 4 + off
, 1,
5521 used_at
&& mips_opts
.noat
),
5522 offset_expr
.X_add_symbol
, (offsetT
) 0,
5525 /* We just generated two relocs. When tc_gen_reloc
5526 handles this case, it will skip the first reloc and
5527 handle the second. The second reloc already has an
5528 extra addend of 4, which we added above. We must
5529 subtract it out, and then subtract another 4 to make
5530 the first reloc come out right. The second reloc
5531 will come out right because we are going to add 4 to
5532 offset_expr when we build its instruction below.
5534 If we have a symbol, then we don't want to include
5535 the offset, because it will wind up being included
5536 when we generate the reloc. */
5538 if (offset_expr
.X_op
== O_constant
)
5539 offset_expr
.X_add_number
-= 8;
5542 offset_expr
.X_add_number
= -4;
5543 offset_expr
.X_op
= O_constant
;
5546 macro_build_lui (p
, &icnt
, &offset_expr
, AT
);
5551 macro_build (p
, &icnt
, (expressionS
*) NULL
,
5552 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
5553 "d,v,t", AT
, breg
, AT
);
5557 /* Itbl support may require additional care here. */
5558 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
,
5559 coproc
? treg
+ 1 : treg
,
5560 (int) BFD_RELOC_LO16
, AT
);
5563 /* FIXME: How do we handle overflow here? */
5564 offset_expr
.X_add_number
+= 4;
5565 /* Itbl support may require additional care here. */
5566 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
,
5567 coproc
? treg
: treg
+ 1,
5568 (int) BFD_RELOC_LO16
, AT
);
5570 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
5574 /* If this is a reference to an external symbol, we want
5575 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5580 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5582 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
5583 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
5584 If there is a base register we add it to $at before the
5585 lwc1 instructions. If there is a constant we include it
5586 in the lwc1 instructions. */
5588 expr1
.X_add_number
= offset_expr
.X_add_number
;
5589 offset_expr
.X_add_number
= 0;
5590 if (expr1
.X_add_number
< -0x8000
5591 || expr1
.X_add_number
>= 0x8000 - 4)
5592 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
5597 frag_grow (24 + off
);
5598 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5599 HAVE_32BIT_ADDRESSES
? "lw" : "ld",
5600 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
5601 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
5603 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5604 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
5605 "d,v,t", AT
, breg
, AT
);
5606 /* Itbl support may require additional care here. */
5607 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
5608 coproc
? treg
+ 1 : treg
,
5609 (int) BFD_RELOC_LO16
, AT
);
5610 expr1
.X_add_number
+= 4;
5612 /* Set mips_optimize to 2 to avoid inserting an undesired
5614 hold_mips_optimize
= mips_optimize
;
5616 /* Itbl support may require additional care here. */
5617 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
5618 coproc
? treg
: treg
+ 1,
5619 (int) BFD_RELOC_LO16
, AT
);
5620 mips_optimize
= hold_mips_optimize
;
5622 (void) frag_var (rs_machine_dependent
, 0, 0,
5623 RELAX_ENCODE (0, 0, -16 - off
, -8, 1, 0),
5624 offset_expr
.X_add_symbol
, (offsetT
) 0,
5627 else if (mips_pic
== SVR4_PIC
)
5631 /* If this is a reference to an external symbol, we want
5632 lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5634 lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16)
5639 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5641 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
5642 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
5643 If there is a base register we add it to $at before the
5644 lwc1 instructions. If there is a constant we include it
5645 in the lwc1 instructions. */
5647 expr1
.X_add_number
= offset_expr
.X_add_number
;
5648 offset_expr
.X_add_number
= 0;
5649 if (expr1
.X_add_number
< -0x8000
5650 || expr1
.X_add_number
>= 0x8000 - 4)
5651 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
5652 if (reg_needs_delay (GP
))
5661 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
5662 AT
, (int) BFD_RELOC_MIPS_GOT_HI16
);
5663 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5664 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
5665 "d,v,t", AT
, AT
, GP
);
5666 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5667 HAVE_32BIT_ADDRESSES
? "lw" : "ld",
5668 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT_LO16
, AT
);
5669 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
5671 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5672 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
5673 "d,v,t", AT
, breg
, AT
);
5674 /* Itbl support may require additional care here. */
5675 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
5676 coproc
? treg
+ 1 : treg
,
5677 (int) BFD_RELOC_LO16
, AT
);
5678 expr1
.X_add_number
+= 4;
5680 /* Set mips_optimize to 2 to avoid inserting an undesired
5682 hold_mips_optimize
= mips_optimize
;
5684 /* Itbl support may require additional care here. */
5685 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
5686 coproc
? treg
: treg
+ 1,
5687 (int) BFD_RELOC_LO16
, AT
);
5688 mips_optimize
= hold_mips_optimize
;
5689 expr1
.X_add_number
-= 4;
5691 p
= frag_var (rs_machine_dependent
, 16 + gpdel
+ off
, 0,
5692 RELAX_ENCODE (24 + off
, 16 + gpdel
+ off
, gpdel
,
5693 8 + gpdel
+ off
, 1, 0),
5694 offset_expr
.X_add_symbol
, (offsetT
) 0,
5698 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
5701 macro_build (p
, &icnt
, &offset_expr
,
5702 HAVE_32BIT_ADDRESSES
? "lw" : "ld",
5703 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
5705 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
5709 macro_build (p
, &icnt
, (expressionS
*) NULL
,
5710 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
5711 "d,v,t", AT
, breg
, AT
);
5714 /* Itbl support may require additional care here. */
5715 macro_build (p
, &icnt
, &expr1
, s
, fmt
,
5716 coproc
? treg
+ 1 : treg
,
5717 (int) BFD_RELOC_LO16
, AT
);
5719 expr1
.X_add_number
+= 4;
5721 /* Set mips_optimize to 2 to avoid inserting an undesired
5723 hold_mips_optimize
= mips_optimize
;
5725 /* Itbl support may require additional care here. */
5726 macro_build (p
, &icnt
, &expr1
, s
, fmt
,
5727 coproc
? treg
: treg
+ 1,
5728 (int) BFD_RELOC_LO16
, AT
);
5729 mips_optimize
= hold_mips_optimize
;
5731 else if (mips_pic
== EMBEDDED_PIC
)
5733 /* If there is no base register, we use
5734 <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL)
5735 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_MIPS_GPREL)
5736 If we have a base register, we use
5738 <op> $treg,<sym>($at) (BFD_RELOC_MIPS_GPREL)
5739 <op> $treg+1,<sym>+4($at) (BFD_RELOC_MIPS_GPREL)
5748 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5749 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
5750 "d,v,t", AT
, breg
, GP
);
5755 /* Itbl support may require additional care here. */
5756 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
5757 coproc
? treg
+ 1 : treg
,
5758 (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
5759 offset_expr
.X_add_number
+= 4;
5760 /* Itbl support may require additional care here. */
5761 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
5762 coproc
? treg
: treg
+ 1,
5763 (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
5779 assert (HAVE_32BIT_ADDRESSES
);
5780 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
5781 (int) BFD_RELOC_LO16
, breg
);
5782 offset_expr
.X_add_number
+= 4;
5783 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
+ 1,
5784 (int) BFD_RELOC_LO16
, breg
);
5787 /* New code added to support COPZ instructions.
5788 This code builds table entries out of the macros in mip_opcodes.
5789 R4000 uses interlocks to handle coproc delays.
5790 Other chips (like the R3000) require nops to be inserted for delays.
5792 FIXME: Currently, we require that the user handle delays.
5793 In order to fill delay slots for non-interlocked chips,
5794 we must have a way to specify delays based on the coprocessor.
5795 Eg. 4 cycles if load coproc reg from memory, 1 if in cache, etc.
5796 What are the side-effects of the cop instruction?
5797 What cache support might we have and what are its effects?
5798 Both coprocessor & memory require delays. how long???
5799 What registers are read/set/modified?
5801 If an itbl is provided to interpret cop instructions,
5802 this knowledge can be encoded in the itbl spec. */
5816 /* For now we just do C (same as Cz). The parameter will be
5817 stored in insn_opcode by mips_ip. */
5818 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s
, "C",
5823 move_register (&icnt
, dreg
, sreg
);
5826 #ifdef LOSING_COMPILER
5828 /* Try and see if this is a new itbl instruction.
5829 This code builds table entries out of the macros in mip_opcodes.
5830 FIXME: For now we just assemble the expression and pass it's
5831 value along as a 32-bit immediate.
5832 We may want to have the assembler assemble this value,
5833 so that we gain the assembler's knowledge of delay slots,
5835 Would it be more efficient to use mask (id) here? */
5836 if (itbl_have_entries
5837 && (immed_expr
= itbl_assemble (ip
->insn_mo
->name
, "")))
5839 s
= ip
->insn_mo
->name
;
5841 coproc
= ITBL_DECODE_PNUM (immed_expr
);;
5842 macro_build ((char *) NULL
, &icnt
, &immed_expr
, s
, "C");
5849 as_warn (_("Macro used $at after \".set noat\""));
5854 struct mips_cl_insn
*ip
;
5856 register int treg
, sreg
, dreg
, breg
;
5872 bfd_reloc_code_real_type r
;
5875 treg
= (ip
->insn_opcode
>> 16) & 0x1f;
5876 dreg
= (ip
->insn_opcode
>> 11) & 0x1f;
5877 sreg
= breg
= (ip
->insn_opcode
>> 21) & 0x1f;
5878 mask
= ip
->insn_mo
->mask
;
5880 expr1
.X_op
= O_constant
;
5881 expr1
.X_op_symbol
= NULL
;
5882 expr1
.X_add_symbol
= NULL
;
5883 expr1
.X_add_number
= 1;
5887 #endif /* LOSING_COMPILER */
5892 macro_build ((char *) NULL
, &icnt
, NULL
,
5893 dbl
? "dmultu" : "multu",
5895 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
5901 /* The MIPS assembler some times generates shifts and adds. I'm
5902 not trying to be that fancy. GCC should do this for us
5904 load_register (&icnt
, AT
, &imm_expr
, dbl
);
5905 macro_build ((char *) NULL
, &icnt
, NULL
,
5906 dbl
? "dmult" : "mult", "s,t", sreg
, AT
);
5907 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
5920 mips_emit_delays (true);
5921 ++mips_opts
.noreorder
;
5922 mips_any_noreorder
= 1;
5924 load_register (&icnt
, AT
, &imm_expr
, dbl
);
5925 macro_build ((char *) NULL
, &icnt
, NULL
,
5926 dbl
? "dmult" : "mult", "s,t", sreg
, imm
? AT
: treg
);
5927 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
5928 macro_build ((char *) NULL
, &icnt
, NULL
,
5929 dbl
? "dsra32" : "sra", "d,w,<", dreg
, dreg
, 31);
5930 macro_build ((char *) NULL
, &icnt
, NULL
, "mfhi", "d", AT
);
5932 macro_build ((char *) NULL
, &icnt
, NULL
, "tne", "s,t", dreg
, AT
);
5935 expr1
.X_add_number
= 8;
5936 macro_build ((char *) NULL
, &icnt
, &expr1
, "beq", "s,t,p", dreg
, AT
);
5937 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
5938 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 6);
5940 --mips_opts
.noreorder
;
5941 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
5954 mips_emit_delays (true);
5955 ++mips_opts
.noreorder
;
5956 mips_any_noreorder
= 1;
5958 load_register (&icnt
, AT
, &imm_expr
, dbl
);
5959 macro_build ((char *) NULL
, &icnt
, NULL
,
5960 dbl
? "dmultu" : "multu",
5961 "s,t", sreg
, imm
? AT
: treg
);
5962 macro_build ((char *) NULL
, &icnt
, NULL
, "mfhi", "d", AT
);
5963 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
5965 macro_build ((char *) NULL
, &icnt
, NULL
, "tne", "s,t", AT
, 0);
5968 expr1
.X_add_number
= 8;
5969 macro_build ((char *) NULL
, &icnt
, &expr1
, "beq", "s,t,p", AT
, 0);
5970 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
5971 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 6);
5973 --mips_opts
.noreorder
;
5977 macro_build ((char *) NULL
, &icnt
, NULL
, "subu", "d,v,t", AT
, 0, treg
);
5978 macro_build ((char *) NULL
, &icnt
, NULL
, "srlv", "d,t,s", AT
, sreg
, AT
);
5979 macro_build ((char *) NULL
, &icnt
, NULL
, "sllv", "d,t,s", dreg
, sreg
,
5981 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
5985 if (imm_expr
.X_op
!= O_constant
)
5986 as_bad (_("rotate count too large"));
5987 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", AT
, sreg
,
5988 (int) (imm_expr
.X_add_number
& 0x1f));
5989 macro_build ((char *) NULL
, &icnt
, NULL
, "srl", "d,w,<", dreg
, sreg
,
5990 (int) ((0 - imm_expr
.X_add_number
) & 0x1f));
5991 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
5995 macro_build ((char *) NULL
, &icnt
, NULL
, "subu", "d,v,t", AT
, 0, treg
);
5996 macro_build ((char *) NULL
, &icnt
, NULL
, "sllv", "d,t,s", AT
, sreg
, AT
);
5997 macro_build ((char *) NULL
, &icnt
, NULL
, "srlv", "d,t,s", dreg
, sreg
,
5999 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
6003 if (imm_expr
.X_op
!= O_constant
)
6004 as_bad (_("rotate count too large"));
6005 macro_build ((char *) NULL
, &icnt
, NULL
, "srl", "d,w,<", AT
, sreg
,
6006 (int) (imm_expr
.X_add_number
& 0x1f));
6007 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", dreg
, sreg
,
6008 (int) ((0 - imm_expr
.X_add_number
) & 0x1f));
6009 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
6013 if (mips_arch
== CPU_R4650
)
6015 as_bad (_("opcode not supported on this processor"));
6018 assert (mips_opts
.isa
== ISA_MIPS1
);
6019 /* Even on a big endian machine $fn comes before $fn+1. We have
6020 to adjust when storing to memory. */
6021 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "swc1", "T,o(b)",
6022 target_big_endian
? treg
+ 1 : treg
,
6023 (int) BFD_RELOC_LO16
, breg
);
6024 offset_expr
.X_add_number
+= 4;
6025 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "swc1", "T,o(b)",
6026 target_big_endian
? treg
: treg
+ 1,
6027 (int) BFD_RELOC_LO16
, breg
);
6032 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
6033 treg
, (int) BFD_RELOC_LO16
);
6035 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
6036 sreg
, (int) BFD_RELOC_LO16
);
6039 macro_build ((char *) NULL
, &icnt
, NULL
, "xor", "d,v,t", dreg
,
6041 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
6042 dreg
, (int) BFD_RELOC_LO16
);
6047 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
6049 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
6050 sreg
, (int) BFD_RELOC_LO16
);
6055 as_warn (_("Instruction %s: result is always false"),
6057 move_register (&icnt
, dreg
, 0);
6060 if (imm_expr
.X_op
== O_constant
6061 && imm_expr
.X_add_number
>= 0
6062 && imm_expr
.X_add_number
< 0x10000)
6064 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "xori", "t,r,i", dreg
,
6065 sreg
, (int) BFD_RELOC_LO16
);
6068 else if (imm_expr
.X_op
== O_constant
6069 && imm_expr
.X_add_number
> -0x8000
6070 && imm_expr
.X_add_number
< 0)
6072 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
6073 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
6074 HAVE_32BIT_GPRS
? "addiu" : "daddiu",
6075 "t,r,j", dreg
, sreg
,
6076 (int) BFD_RELOC_LO16
);
6081 load_register (&icnt
, AT
, &imm_expr
, 0);
6082 macro_build ((char *) NULL
, &icnt
, NULL
, "xor", "d,v,t", dreg
,
6086 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
, dreg
,
6087 (int) BFD_RELOC_LO16
);
6092 case M_SGE
: /* sreg >= treg <==> not (sreg < treg) */
6098 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, sreg
, treg
);
6099 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
6100 (int) BFD_RELOC_LO16
);
6103 case M_SGE_I
: /* sreg >= I <==> not (sreg < I) */
6105 if (imm_expr
.X_op
== O_constant
6106 && imm_expr
.X_add_number
>= -0x8000
6107 && imm_expr
.X_add_number
< 0x8000)
6109 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
6110 mask
== M_SGE_I
? "slti" : "sltiu",
6111 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
6116 load_register (&icnt
, AT
, &imm_expr
, 0);
6117 macro_build ((char *) NULL
, &icnt
, NULL
,
6118 mask
== M_SGE_I
? "slt" : "sltu",
6119 "d,v,t", dreg
, sreg
, AT
);
6122 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
6123 (int) BFD_RELOC_LO16
);
6128 case M_SGT
: /* sreg > treg <==> treg < sreg */
6134 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, treg
, sreg
);
6137 case M_SGT_I
: /* sreg > I <==> I < sreg */
6143 load_register (&icnt
, AT
, &imm_expr
, 0);
6144 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, AT
, sreg
);
6147 case M_SLE
: /* sreg <= treg <==> treg >= sreg <==> not (treg < sreg) */
6153 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, treg
, sreg
);
6154 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
6155 (int) BFD_RELOC_LO16
);
6158 case M_SLE_I
: /* sreg <= I <==> I >= sreg <==> not (I < sreg) */
6164 load_register (&icnt
, AT
, &imm_expr
, 0);
6165 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, AT
, sreg
);
6166 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
6167 (int) BFD_RELOC_LO16
);
6171 if (imm_expr
.X_op
== O_constant
6172 && imm_expr
.X_add_number
>= -0x8000
6173 && imm_expr
.X_add_number
< 0x8000)
6175 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "slti", "t,r,j",
6176 dreg
, sreg
, (int) BFD_RELOC_LO16
);
6179 load_register (&icnt
, AT
, &imm_expr
, 0);
6180 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", dreg
, sreg
, AT
);
6184 if (imm_expr
.X_op
== O_constant
6185 && imm_expr
.X_add_number
>= -0x8000
6186 && imm_expr
.X_add_number
< 0x8000)
6188 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "sltiu", "t,r,j",
6189 dreg
, sreg
, (int) BFD_RELOC_LO16
);
6192 load_register (&icnt
, AT
, &imm_expr
, 0);
6193 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, sreg
,
6199 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0,
6202 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0,
6206 macro_build ((char *) NULL
, &icnt
, NULL
, "xor", "d,v,t", dreg
,
6208 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0,
6214 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
6216 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0,
6222 as_warn (_("Instruction %s: result is always true"),
6224 macro_build ((char *) NULL
, &icnt
, &expr1
,
6225 HAVE_32BIT_GPRS
? "addiu" : "daddiu",
6226 "t,r,j", dreg
, 0, (int) BFD_RELOC_LO16
);
6229 if (imm_expr
.X_op
== O_constant
6230 && imm_expr
.X_add_number
>= 0
6231 && imm_expr
.X_add_number
< 0x10000)
6233 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "xori", "t,r,i",
6234 dreg
, sreg
, (int) BFD_RELOC_LO16
);
6237 else if (imm_expr
.X_op
== O_constant
6238 && imm_expr
.X_add_number
> -0x8000
6239 && imm_expr
.X_add_number
< 0)
6241 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
6242 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
6243 HAVE_32BIT_GPRS
? "addiu" : "daddiu",
6244 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
6249 load_register (&icnt
, AT
, &imm_expr
, 0);
6250 macro_build ((char *) NULL
, &icnt
, NULL
, "xor", "d,v,t", dreg
,
6254 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0, dreg
);
6262 if (imm_expr
.X_op
== O_constant
6263 && imm_expr
.X_add_number
> -0x8000
6264 && imm_expr
.X_add_number
<= 0x8000)
6266 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
6267 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
6268 dbl
? "daddi" : "addi",
6269 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
6272 load_register (&icnt
, AT
, &imm_expr
, dbl
);
6273 macro_build ((char *) NULL
, &icnt
, NULL
,
6274 dbl
? "dsub" : "sub", "d,v,t", dreg
, sreg
, AT
);
6280 if (imm_expr
.X_op
== O_constant
6281 && imm_expr
.X_add_number
> -0x8000
6282 && imm_expr
.X_add_number
<= 0x8000)
6284 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
6285 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
6286 dbl
? "daddiu" : "addiu",
6287 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
6290 load_register (&icnt
, AT
, &imm_expr
, dbl
);
6291 macro_build ((char *) NULL
, &icnt
, NULL
,
6292 dbl
? "dsubu" : "subu", "d,v,t", dreg
, sreg
, AT
);
6313 load_register (&icnt
, AT
, &imm_expr
, 0);
6314 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "s,t", sreg
, AT
);
6319 assert (mips_opts
.isa
== ISA_MIPS1
);
6320 sreg
= (ip
->insn_opcode
>> 11) & 0x1f; /* floating reg */
6321 dreg
= (ip
->insn_opcode
>> 06) & 0x1f; /* floating reg */
6324 * Is the double cfc1 instruction a bug in the mips assembler;
6325 * or is there a reason for it?
6327 mips_emit_delays (true);
6328 ++mips_opts
.noreorder
;
6329 mips_any_noreorder
= 1;
6330 macro_build ((char *) NULL
, &icnt
, NULL
, "cfc1", "t,G", treg
, 31);
6331 macro_build ((char *) NULL
, &icnt
, NULL
, "cfc1", "t,G", treg
, 31);
6332 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "");
6333 expr1
.X_add_number
= 3;
6334 macro_build ((char *) NULL
, &icnt
, &expr1
, "ori", "t,r,i", AT
, treg
,
6335 (int) BFD_RELOC_LO16
);
6336 expr1
.X_add_number
= 2;
6337 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", AT
, AT
,
6338 (int) BFD_RELOC_LO16
);
6339 macro_build ((char *) NULL
, &icnt
, NULL
, "ctc1", "t,G", AT
, 31);
6340 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "");
6341 macro_build ((char *) NULL
, &icnt
, NULL
,
6342 mask
== M_TRUNCWD
? "cvt.w.d" : "cvt.w.s", "D,S", dreg
, sreg
);
6343 macro_build ((char *) NULL
, &icnt
, NULL
, "ctc1", "t,G", treg
, 31);
6344 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "");
6345 --mips_opts
.noreorder
;
6354 if (offset_expr
.X_add_number
>= 0x7fff)
6355 as_bad (_("operand overflow"));
6356 /* avoid load delay */
6357 if (! target_big_endian
)
6358 offset_expr
.X_add_number
+= 1;
6359 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
6360 (int) BFD_RELOC_LO16
, breg
);
6361 if (! target_big_endian
)
6362 offset_expr
.X_add_number
-= 1;
6364 offset_expr
.X_add_number
+= 1;
6365 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lbu", "t,o(b)", AT
,
6366 (int) BFD_RELOC_LO16
, breg
);
6367 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", treg
, treg
, 8);
6368 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", treg
, treg
, AT
);
6381 if (offset_expr
.X_add_number
>= 0x8000 - off
)
6382 as_bad (_("operand overflow"));
6383 if (! target_big_endian
)
6384 offset_expr
.X_add_number
+= off
;
6385 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
6386 (int) BFD_RELOC_LO16
, breg
);
6387 if (! target_big_endian
)
6388 offset_expr
.X_add_number
-= off
;
6390 offset_expr
.X_add_number
+= off
;
6391 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s2
, "t,o(b)", treg
,
6392 (int) BFD_RELOC_LO16
, breg
);
6405 load_address (&icnt
, AT
, &offset_expr
);
6407 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6408 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
6409 "d,v,t", AT
, AT
, breg
);
6410 if (! target_big_endian
)
6411 expr1
.X_add_number
= off
;
6413 expr1
.X_add_number
= 0;
6414 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, "t,o(b)", treg
,
6415 (int) BFD_RELOC_LO16
, AT
);
6416 if (! target_big_endian
)
6417 expr1
.X_add_number
= 0;
6419 expr1
.X_add_number
= off
;
6420 macro_build ((char *) NULL
, &icnt
, &expr1
, s2
, "t,o(b)", treg
,
6421 (int) BFD_RELOC_LO16
, AT
);
6426 load_address (&icnt
, AT
, &offset_expr
);
6428 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6429 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
6430 "d,v,t", AT
, AT
, breg
);
6431 if (target_big_endian
)
6432 expr1
.X_add_number
= 0;
6433 macro_build ((char *) NULL
, &icnt
, &expr1
,
6434 mask
== M_ULH_A
? "lb" : "lbu", "t,o(b)", treg
,
6435 (int) BFD_RELOC_LO16
, AT
);
6436 if (target_big_endian
)
6437 expr1
.X_add_number
= 1;
6439 expr1
.X_add_number
= 0;
6440 macro_build ((char *) NULL
, &icnt
, &expr1
, "lbu", "t,o(b)", AT
,
6441 (int) BFD_RELOC_LO16
, AT
);
6442 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", treg
,
6444 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", treg
,
6449 if (offset_expr
.X_add_number
>= 0x7fff)
6450 as_bad (_("operand overflow"));
6451 if (target_big_endian
)
6452 offset_expr
.X_add_number
+= 1;
6453 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "sb", "t,o(b)", treg
,
6454 (int) BFD_RELOC_LO16
, breg
);
6455 macro_build ((char *) NULL
, &icnt
, NULL
, "srl", "d,w,<", AT
, treg
, 8);
6456 if (target_big_endian
)
6457 offset_expr
.X_add_number
-= 1;
6459 offset_expr
.X_add_number
+= 1;
6460 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "sb", "t,o(b)", AT
,
6461 (int) BFD_RELOC_LO16
, breg
);
6474 if (offset_expr
.X_add_number
>= 0x8000 - off
)
6475 as_bad (_("operand overflow"));
6476 if (! target_big_endian
)
6477 offset_expr
.X_add_number
+= off
;
6478 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
6479 (int) BFD_RELOC_LO16
, breg
);
6480 if (! target_big_endian
)
6481 offset_expr
.X_add_number
-= off
;
6483 offset_expr
.X_add_number
+= off
;
6484 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s2
, "t,o(b)", treg
,
6485 (int) BFD_RELOC_LO16
, breg
);
6498 load_address (&icnt
, AT
, &offset_expr
);
6500 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6501 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
6502 "d,v,t", AT
, AT
, breg
);
6503 if (! target_big_endian
)
6504 expr1
.X_add_number
= off
;
6506 expr1
.X_add_number
= 0;
6507 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, "t,o(b)", treg
,
6508 (int) BFD_RELOC_LO16
, AT
);
6509 if (! target_big_endian
)
6510 expr1
.X_add_number
= 0;
6512 expr1
.X_add_number
= off
;
6513 macro_build ((char *) NULL
, &icnt
, &expr1
, s2
, "t,o(b)", treg
,
6514 (int) BFD_RELOC_LO16
, AT
);
6518 load_address (&icnt
, AT
, &offset_expr
);
6520 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6521 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
6522 "d,v,t", AT
, AT
, breg
);
6523 if (! target_big_endian
)
6524 expr1
.X_add_number
= 0;
6525 macro_build ((char *) NULL
, &icnt
, &expr1
, "sb", "t,o(b)", treg
,
6526 (int) BFD_RELOC_LO16
, AT
);
6527 macro_build ((char *) NULL
, &icnt
, NULL
, "srl", "d,w,<", treg
,
6529 if (! target_big_endian
)
6530 expr1
.X_add_number
= 1;
6532 expr1
.X_add_number
= 0;
6533 macro_build ((char *) NULL
, &icnt
, &expr1
, "sb", "t,o(b)", treg
,
6534 (int) BFD_RELOC_LO16
, AT
);
6535 if (! target_big_endian
)
6536 expr1
.X_add_number
= 0;
6538 expr1
.X_add_number
= 1;
6539 macro_build ((char *) NULL
, &icnt
, &expr1
, "lbu", "t,o(b)", AT
,
6540 (int) BFD_RELOC_LO16
, AT
);
6541 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", treg
,
6543 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", treg
,
6548 /* FIXME: Check if this is one of the itbl macros, since they
6549 are added dynamically. */
6550 as_bad (_("Macro %s not implemented yet"), ip
->insn_mo
->name
);
6554 as_warn (_("Macro used $at after \".set noat\""));
6557 /* Implement macros in mips16 mode. */
6561 struct mips_cl_insn
*ip
;
6564 int xreg
, yreg
, zreg
, tmp
;
6568 const char *s
, *s2
, *s3
;
6570 mask
= ip
->insn_mo
->mask
;
6572 xreg
= (ip
->insn_opcode
>> MIPS16OP_SH_RX
) & MIPS16OP_MASK_RX
;
6573 yreg
= (ip
->insn_opcode
>> MIPS16OP_SH_RY
) & MIPS16OP_MASK_RY
;
6574 zreg
= (ip
->insn_opcode
>> MIPS16OP_SH_RZ
) & MIPS16OP_MASK_RZ
;
6578 expr1
.X_op
= O_constant
;
6579 expr1
.X_op_symbol
= NULL
;
6580 expr1
.X_add_symbol
= NULL
;
6581 expr1
.X_add_number
= 1;
6600 mips_emit_delays (true);
6601 ++mips_opts
.noreorder
;
6602 mips_any_noreorder
= 1;
6603 macro_build ((char *) NULL
, &icnt
, NULL
,
6604 dbl
? "ddiv" : "div",
6605 "0,x,y", xreg
, yreg
);
6606 expr1
.X_add_number
= 2;
6607 macro_build ((char *) NULL
, &icnt
, &expr1
, "bnez", "x,p", yreg
);
6608 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "6", 7);
6610 /* FIXME: The normal code checks for of -1 / -0x80000000 here,
6611 since that causes an overflow. We should do that as well,
6612 but I don't see how to do the comparisons without a temporary
6614 --mips_opts
.noreorder
;
6615 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "x", zreg
);
6634 mips_emit_delays (true);
6635 ++mips_opts
.noreorder
;
6636 mips_any_noreorder
= 1;
6637 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "0,x,y", xreg
, yreg
);
6638 expr1
.X_add_number
= 2;
6639 macro_build ((char *) NULL
, &icnt
, &expr1
, "bnez", "x,p", yreg
);
6640 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "6", 7);
6641 --mips_opts
.noreorder
;
6642 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "x", zreg
);
6648 macro_build ((char *) NULL
, &icnt
, NULL
,
6649 dbl
? "dmultu" : "multu", "x,y", xreg
, yreg
);
6650 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "x", zreg
);
6658 if (imm_expr
.X_op
!= O_constant
)
6659 as_bad (_("Unsupported large constant"));
6660 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
6661 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
6662 dbl
? "daddiu" : "addiu", "y,x,4", yreg
, xreg
);
6666 if (imm_expr
.X_op
!= O_constant
)
6667 as_bad (_("Unsupported large constant"));
6668 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
6669 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "addiu",
6674 if (imm_expr
.X_op
!= O_constant
)
6675 as_bad (_("Unsupported large constant"));
6676 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
6677 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "daddiu",
6700 goto do_reverse_branch
;
6704 goto do_reverse_branch
;
6716 goto do_reverse_branch
;
6727 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s
, "x,y",
6729 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s2
, "p");
6756 goto do_addone_branch_i
;
6761 goto do_addone_branch_i
;
6776 goto do_addone_branch_i
;
6783 if (imm_expr
.X_op
!= O_constant
)
6784 as_bad (_("Unsupported large constant"));
6785 ++imm_expr
.X_add_number
;
6788 macro_build ((char *) NULL
, &icnt
, &imm_expr
, s
, s3
, xreg
);
6789 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s2
, "p");
6793 expr1
.X_add_number
= 0;
6794 macro_build ((char *) NULL
, &icnt
, &expr1
, "slti", "x,8", yreg
);
6796 move_register (&icnt
, xreg
, yreg
);
6797 expr1
.X_add_number
= 2;
6798 macro_build ((char *) NULL
, &icnt
, &expr1
, "bteqz", "p");
6799 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6800 "neg", "x,w", xreg
, xreg
);
6804 /* For consistency checking, verify that all bits are specified either
6805 by the match/mask part of the instruction definition, or by the
6808 validate_mips_insn (opc
)
6809 const struct mips_opcode
*opc
;
6811 const char *p
= opc
->args
;
6813 unsigned long used_bits
= opc
->mask
;
6815 if ((used_bits
& opc
->match
) != opc
->match
)
6817 as_bad (_("internal: bad mips opcode (mask error): %s %s"),
6818 opc
->name
, opc
->args
);
6821 #define USE_BITS(mask,shift) (used_bits |= ((mask) << (shift)))
6828 case '<': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
6829 case '>': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
6831 case 'B': USE_BITS (OP_MASK_CODE20
, OP_SH_CODE20
); break;
6832 case 'C': USE_BITS (OP_MASK_COPZ
, OP_SH_COPZ
); break;
6833 case 'D': USE_BITS (OP_MASK_FD
, OP_SH_FD
); break;
6834 case 'E': USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
6836 case 'G': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
6837 case 'H': USE_BITS (OP_MASK_SEL
, OP_SH_SEL
); break;
6839 case 'J': USE_BITS (OP_MASK_CODE19
, OP_SH_CODE19
); break;
6841 case 'M': USE_BITS (OP_MASK_CCC
, OP_SH_CCC
); break;
6842 case 'N': USE_BITS (OP_MASK_BCC
, OP_SH_BCC
); break;
6843 case 'R': USE_BITS (OP_MASK_FR
, OP_SH_FR
); break;
6844 case 'S': USE_BITS (OP_MASK_FS
, OP_SH_FS
); break;
6845 case 'T': USE_BITS (OP_MASK_FT
, OP_SH_FT
); break;
6846 case 'V': USE_BITS (OP_MASK_FS
, OP_SH_FS
); break;
6847 case 'W': USE_BITS (OP_MASK_FT
, OP_SH_FT
); break;
6848 case 'a': USE_BITS (OP_MASK_TARGET
, OP_SH_TARGET
); break;
6849 case 'b': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
6850 case 'c': USE_BITS (OP_MASK_CODE
, OP_SH_CODE
); break;
6851 case 'd': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
6853 case 'h': USE_BITS (OP_MASK_PREFX
, OP_SH_PREFX
); break;
6854 case 'i': USE_BITS (OP_MASK_IMMEDIATE
, OP_SH_IMMEDIATE
); break;
6855 case 'j': USE_BITS (OP_MASK_DELTA
, OP_SH_DELTA
); break;
6856 case 'k': USE_BITS (OP_MASK_CACHE
, OP_SH_CACHE
); break;
6858 case 'o': USE_BITS (OP_MASK_DELTA
, OP_SH_DELTA
); break;
6859 case 'p': USE_BITS (OP_MASK_DELTA
, OP_SH_DELTA
); break;
6860 case 'q': USE_BITS (OP_MASK_CODE2
, OP_SH_CODE2
); break;
6861 case 'r': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
6862 case 's': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
6863 case 't': USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
6864 case 'u': USE_BITS (OP_MASK_IMMEDIATE
, OP_SH_IMMEDIATE
); break;
6865 case 'v': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
6866 case 'w': USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
6869 case 'P': USE_BITS (OP_MASK_PERFREG
, OP_SH_PERFREG
); break;
6870 case 'U': USE_BITS (OP_MASK_RD
, OP_SH_RD
);
6871 USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
6873 as_bad (_("internal: bad mips opcode (unknown operand type `%c'): %s %s"),
6874 c
, opc
->name
, opc
->args
);
6878 if (used_bits
!= 0xffffffff)
6880 as_bad (_("internal: bad mips opcode (bits 0x%lx undefined): %s %s"),
6881 ~used_bits
& 0xffffffff, opc
->name
, opc
->args
);
6887 /* This routine assembles an instruction into its binary format. As a
6888 side effect, it sets one of the global variables imm_reloc or
6889 offset_reloc to the type of relocation to do if one of the operands
6890 is an address expression. */
6895 struct mips_cl_insn
*ip
;
6900 struct mips_opcode
*insn
;
6903 unsigned int lastregno
= 0;
6906 int full_opcode_match
= 1;
6910 /* If the instruction contains a '.', we first try to match an instruction
6911 including the '.'. Then we try again without the '.'. */
6913 for (s
= str
; *s
!= '\0' && !isspace ((unsigned char) *s
); ++s
)
6916 /* If we stopped on whitespace, then replace the whitespace with null for
6917 the call to hash_find. Save the character we replaced just in case we
6918 have to re-parse the instruction. */
6919 if (isspace ((unsigned char) *s
))
6925 insn
= (struct mips_opcode
*) hash_find (op_hash
, str
);
6927 /* If we didn't find the instruction in the opcode table, try again, but
6928 this time with just the instruction up to, but not including the
6932 /* Restore the character we overwrite above (if any). */
6936 /* Scan up to the first '.' or whitespace. */
6937 for (s
= str
; *s
!= '\0' && *s
!= '.' && !isspace ((unsigned char) *s
); ++s
)
6940 /* If we did not find a '.', then we can quit now. */
6943 insn_error
= "unrecognized opcode";
6947 /* Lookup the instruction in the hash table. */
6949 if ((insn
= (struct mips_opcode
*) hash_find (op_hash
, str
)) == NULL
)
6951 insn_error
= "unrecognized opcode";
6955 full_opcode_match
= 0;
6963 assert (strcmp (insn
->name
, str
) == 0);
6965 if (OPCODE_IS_MEMBER (insn
, mips_opts
.isa
, mips_arch
))
6970 if (insn
->pinfo
!= INSN_MACRO
)
6972 if (mips_arch
== CPU_R4650
&& (insn
->pinfo
& FP_D
) != 0)
6978 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
]
6979 && strcmp (insn
->name
, insn
[1].name
) == 0)
6988 static char buf
[100];
6990 _("opcode not supported on this processor: %s (%s)"),
6991 mips_cpu_to_str (mips_arch
),
6992 mips_isa_to_str (mips_opts
.isa
));
7003 ip
->insn_opcode
= insn
->match
;
7005 for (args
= insn
->args
;; ++args
)
7011 case '\0': /* end of args */
7024 ip
->insn_opcode
|= lastregno
<< OP_SH_RS
;
7028 ip
->insn_opcode
|= lastregno
<< OP_SH_RT
;
7032 ip
->insn_opcode
|= lastregno
<< OP_SH_FT
;
7036 ip
->insn_opcode
|= lastregno
<< OP_SH_FS
;
7042 /* Handle optional base register.
7043 Either the base register is omitted or
7044 we must have a left paren. */
7045 /* This is dependent on the next operand specifier
7046 is a base register specification. */
7047 assert (args
[1] == 'b' || args
[1] == '5'
7048 || args
[1] == '-' || args
[1] == '4');
7052 case ')': /* these must match exactly */
7057 case '<': /* must be at least one digit */
7059 * According to the manual, if the shift amount is greater
7060 * than 31 or less than 0 the the shift amount should be
7061 * mod 32. In reality the mips assembler issues an error.
7062 * We issue a warning and mask out all but the low 5 bits.
7064 my_getExpression (&imm_expr
, s
);
7065 check_absolute_expr (ip
, &imm_expr
);
7066 if ((unsigned long) imm_expr
.X_add_number
> 31)
7068 as_warn (_("Improper shift amount (%ld)"),
7069 (long) imm_expr
.X_add_number
);
7070 imm_expr
.X_add_number
&= OP_MASK_SHAMT
;
7072 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_SHAMT
;
7073 imm_expr
.X_op
= O_absent
;
7077 case '>': /* shift amount minus 32 */
7078 my_getExpression (&imm_expr
, s
);
7079 check_absolute_expr (ip
, &imm_expr
);
7080 if ((unsigned long) imm_expr
.X_add_number
< 32
7081 || (unsigned long) imm_expr
.X_add_number
> 63)
7083 ip
->insn_opcode
|= (imm_expr
.X_add_number
- 32) << OP_SH_SHAMT
;
7084 imm_expr
.X_op
= O_absent
;
7088 case 'k': /* cache code */
7089 case 'h': /* prefx code */
7090 my_getExpression (&imm_expr
, s
);
7091 check_absolute_expr (ip
, &imm_expr
);
7092 if ((unsigned long) imm_expr
.X_add_number
> 31)
7094 as_warn (_("Invalid value for `%s' (%lu)"),
7096 (unsigned long) imm_expr
.X_add_number
);
7097 imm_expr
.X_add_number
&= 0x1f;
7100 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_CACHE
;
7102 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_PREFX
;
7103 imm_expr
.X_op
= O_absent
;
7107 case 'c': /* break code */
7108 my_getExpression (&imm_expr
, s
);
7109 check_absolute_expr (ip
, &imm_expr
);
7110 if ((unsigned) imm_expr
.X_add_number
> 1023)
7112 as_warn (_("Illegal break code (%ld)"),
7113 (long) imm_expr
.X_add_number
);
7114 imm_expr
.X_add_number
&= OP_MASK_CODE
;
7116 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_CODE
;
7117 imm_expr
.X_op
= O_absent
;
7121 case 'q': /* lower break code */
7122 my_getExpression (&imm_expr
, s
);
7123 check_absolute_expr (ip
, &imm_expr
);
7124 if ((unsigned) imm_expr
.X_add_number
> 1023)
7126 as_warn (_("Illegal lower break code (%ld)"),
7127 (long) imm_expr
.X_add_number
);
7128 imm_expr
.X_add_number
&= OP_MASK_CODE2
;
7130 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_CODE2
;
7131 imm_expr
.X_op
= O_absent
;
7135 case 'B': /* 20-bit syscall/break code. */
7136 my_getExpression (&imm_expr
, s
);
7137 check_absolute_expr (ip
, &imm_expr
);
7138 if ((unsigned) imm_expr
.X_add_number
> OP_MASK_CODE20
)
7139 as_warn (_("Illegal 20-bit code (%ld)"),
7140 (long) imm_expr
.X_add_number
);
7141 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_CODE20
;
7142 imm_expr
.X_op
= O_absent
;
7146 case 'C': /* Coprocessor code */
7147 my_getExpression (&imm_expr
, s
);
7148 check_absolute_expr (ip
, &imm_expr
);
7149 if ((unsigned long) imm_expr
.X_add_number
>= (1<<25))
7151 as_warn (_("Coproccesor code > 25 bits (%ld)"),
7152 (long) imm_expr
.X_add_number
);
7153 imm_expr
.X_add_number
&= ((1<<25) - 1);
7155 ip
->insn_opcode
|= imm_expr
.X_add_number
;
7156 imm_expr
.X_op
= O_absent
;
7160 case 'J': /* 19-bit wait code. */
7161 my_getExpression (&imm_expr
, s
);
7162 check_absolute_expr (ip
, &imm_expr
);
7163 if ((unsigned) imm_expr
.X_add_number
> OP_MASK_CODE19
)
7164 as_warn (_("Illegal 19-bit code (%ld)"),
7165 (long) imm_expr
.X_add_number
);
7166 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_CODE19
;
7167 imm_expr
.X_op
= O_absent
;
7171 case 'P': /* Performance register */
7172 my_getExpression (&imm_expr
, s
);
7173 check_absolute_expr (ip
, &imm_expr
);
7174 if (imm_expr
.X_add_number
!= 0 && imm_expr
.X_add_number
!= 1)
7176 as_warn (_("Invalid performance register (%ld)"),
7177 (long) imm_expr
.X_add_number
);
7178 imm_expr
.X_add_number
&= OP_MASK_PERFREG
;
7180 ip
->insn_opcode
|= (imm_expr
.X_add_number
<< OP_SH_PERFREG
);
7181 imm_expr
.X_op
= O_absent
;
7185 case 'b': /* base register */
7186 case 'd': /* destination register */
7187 case 's': /* source register */
7188 case 't': /* target register */
7189 case 'r': /* both target and source */
7190 case 'v': /* both dest and source */
7191 case 'w': /* both dest and target */
7192 case 'E': /* coprocessor target register */
7193 case 'G': /* coprocessor destination register */
7194 case 'x': /* ignore register name */
7195 case 'z': /* must be zero register */
7196 case 'U': /* destination register (clo/clz). */
7201 if (isdigit ((unsigned char) s
[1]))
7211 while (isdigit ((unsigned char) *s
));
7213 as_bad (_("Invalid register number (%d)"), regno
);
7215 else if (*args
== 'E' || *args
== 'G')
7219 if (s
[1] == 'f' && s
[2] == 'p')
7224 else if (s
[1] == 's' && s
[2] == 'p')
7229 else if (s
[1] == 'g' && s
[2] == 'p')
7234 else if (s
[1] == 'a' && s
[2] == 't')
7239 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '0')
7244 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '1')
7249 else if (itbl_have_entries
)
7254 p
= s
+ 1; /* advance past '$' */
7255 n
= itbl_get_field (&p
); /* n is name */
7257 /* See if this is a register defined in an
7259 if (itbl_get_reg_val (n
, &r
))
7261 /* Get_field advances to the start of
7262 the next field, so we need to back
7263 rack to the end of the last field. */
7267 s
= strchr (s
, '\0');
7280 as_warn (_("Used $at without \".set noat\""));
7286 if (c
== 'r' || c
== 'v' || c
== 'w')
7293 /* 'z' only matches $0. */
7294 if (c
== 'z' && regno
!= 0)
7297 /* Now that we have assembled one operand, we use the args string
7298 * to figure out where it goes in the instruction. */
7305 ip
->insn_opcode
|= regno
<< OP_SH_RS
;
7309 ip
->insn_opcode
|= regno
<< OP_SH_RD
;
7312 ip
->insn_opcode
|= regno
<< OP_SH_RD
;
7313 ip
->insn_opcode
|= regno
<< OP_SH_RT
;
7318 ip
->insn_opcode
|= regno
<< OP_SH_RT
;
7321 /* This case exists because on the r3000 trunc
7322 expands into a macro which requires a gp
7323 register. On the r6000 or r4000 it is
7324 assembled into a single instruction which
7325 ignores the register. Thus the insn version
7326 is MIPS_ISA2 and uses 'x', and the macro
7327 version is MIPS_ISA1 and uses 't'. */
7330 /* This case is for the div instruction, which
7331 acts differently if the destination argument
7332 is $0. This only matches $0, and is checked
7333 outside the switch. */
7336 /* Itbl operand; not yet implemented. FIXME ?? */
7338 /* What about all other operands like 'i', which
7339 can be specified in the opcode table? */
7349 ip
->insn_opcode
|= lastregno
<< OP_SH_RS
;
7352 ip
->insn_opcode
|= lastregno
<< OP_SH_RT
;
7357 case 'D': /* floating point destination register */
7358 case 'S': /* floating point source register */
7359 case 'T': /* floating point target register */
7360 case 'R': /* floating point source register */
7364 if (s
[0] == '$' && s
[1] == 'f' && isdigit ((unsigned char) s
[2]))
7374 while (isdigit ((unsigned char) *s
));
7377 as_bad (_("Invalid float register number (%d)"), regno
);
7379 if ((regno
& 1) != 0
7381 && ! (strcmp (str
, "mtc1") == 0
7382 || strcmp (str
, "mfc1") == 0
7383 || strcmp (str
, "lwc1") == 0
7384 || strcmp (str
, "swc1") == 0
7385 || strcmp (str
, "l.s") == 0
7386 || strcmp (str
, "s.s") == 0))
7387 as_warn (_("Float register should be even, was %d"),
7395 if (c
== 'V' || c
== 'W')
7405 ip
->insn_opcode
|= regno
<< OP_SH_FD
;
7409 ip
->insn_opcode
|= regno
<< OP_SH_FS
;
7413 ip
->insn_opcode
|= regno
<< OP_SH_FT
;
7416 ip
->insn_opcode
|= regno
<< OP_SH_FR
;
7426 ip
->insn_opcode
|= lastregno
<< OP_SH_FS
;
7429 ip
->insn_opcode
|= lastregno
<< OP_SH_FT
;
7435 my_getExpression (&imm_expr
, s
);
7436 if (imm_expr
.X_op
!= O_big
7437 && imm_expr
.X_op
!= O_constant
)
7438 insn_error
= _("absolute expression required");
7443 my_getExpression (&offset_expr
, s
);
7444 imm_reloc
= BFD_RELOC_32
;
7457 unsigned char temp
[8];
7459 unsigned int length
;
7464 /* These only appear as the last operand in an
7465 instruction, and every instruction that accepts
7466 them in any variant accepts them in all variants.
7467 This means we don't have to worry about backing out
7468 any changes if the instruction does not match.
7470 The difference between them is the size of the
7471 floating point constant and where it goes. For 'F'
7472 and 'L' the constant is 64 bits; for 'f' and 'l' it
7473 is 32 bits. Where the constant is placed is based
7474 on how the MIPS assembler does things:
7477 f -- immediate value
7480 The .lit4 and .lit8 sections are only used if
7481 permitted by the -G argument.
7483 When generating embedded PIC code, we use the
7484 .lit8 section but not the .lit4 section (we can do
7485 .lit4 inline easily; we need to put .lit8
7486 somewhere in the data segment, and using .lit8
7487 permits the linker to eventually combine identical
7490 The code below needs to know whether the target register
7491 is 32 or 64 bits wide. It relies on the fact 'f' and
7492 'F' are used with GPR-based instructions and 'l' and
7493 'L' are used with FPR-based instructions. */
7495 f64
= *args
== 'F' || *args
== 'L';
7496 using_gprs
= *args
== 'F' || *args
== 'f';
7498 save_in
= input_line_pointer
;
7499 input_line_pointer
= s
;
7500 err
= md_atof (f64
? 'd' : 'f', (char *) temp
, &len
);
7502 s
= input_line_pointer
;
7503 input_line_pointer
= save_in
;
7504 if (err
!= NULL
&& *err
!= '\0')
7506 as_bad (_("Bad floating point constant: %s"), err
);
7507 memset (temp
, '\0', sizeof temp
);
7508 length
= f64
? 8 : 4;
7511 assert (length
== (unsigned) (f64
? 8 : 4));
7515 && (! USE_GLOBAL_POINTER_OPT
7516 || mips_pic
== EMBEDDED_PIC
7517 || g_switch_value
< 4
7518 || (temp
[0] == 0 && temp
[1] == 0)
7519 || (temp
[2] == 0 && temp
[3] == 0))))
7521 imm_expr
.X_op
= O_constant
;
7522 if (! target_big_endian
)
7523 imm_expr
.X_add_number
= bfd_getl32 (temp
);
7525 imm_expr
.X_add_number
= bfd_getb32 (temp
);
7528 && ! mips_disable_float_construction
7529 /* Constants can only be constructed in GPRs and
7530 copied to FPRs if the GPRs are at least as wide
7531 as the FPRs. Force the constant into memory if
7532 we are using 64-bit FPRs but the GPRs are only
7535 || ! (HAVE_64BIT_FPRS
&& HAVE_32BIT_GPRS
))
7536 && ((temp
[0] == 0 && temp
[1] == 0)
7537 || (temp
[2] == 0 && temp
[3] == 0))
7538 && ((temp
[4] == 0 && temp
[5] == 0)
7539 || (temp
[6] == 0 && temp
[7] == 0)))
7541 /* The value is simple enough to load with a couple of
7542 instructions. If using 32-bit registers, set
7543 imm_expr to the high order 32 bits and offset_expr to
7544 the low order 32 bits. Otherwise, set imm_expr to
7545 the entire 64 bit constant. */
7546 if (using_gprs
? HAVE_32BIT_GPRS
: HAVE_32BIT_FPRS
)
7548 imm_expr
.X_op
= O_constant
;
7549 offset_expr
.X_op
= O_constant
;
7550 if (! target_big_endian
)
7552 imm_expr
.X_add_number
= bfd_getl32 (temp
+ 4);
7553 offset_expr
.X_add_number
= bfd_getl32 (temp
);
7557 imm_expr
.X_add_number
= bfd_getb32 (temp
);
7558 offset_expr
.X_add_number
= bfd_getb32 (temp
+ 4);
7560 if (offset_expr
.X_add_number
== 0)
7561 offset_expr
.X_op
= O_absent
;
7563 else if (sizeof (imm_expr
.X_add_number
) > 4)
7565 imm_expr
.X_op
= O_constant
;
7566 if (! target_big_endian
)
7567 imm_expr
.X_add_number
= bfd_getl64 (temp
);
7569 imm_expr
.X_add_number
= bfd_getb64 (temp
);
7573 imm_expr
.X_op
= O_big
;
7574 imm_expr
.X_add_number
= 4;
7575 if (! target_big_endian
)
7577 generic_bignum
[0] = bfd_getl16 (temp
);
7578 generic_bignum
[1] = bfd_getl16 (temp
+ 2);
7579 generic_bignum
[2] = bfd_getl16 (temp
+ 4);
7580 generic_bignum
[3] = bfd_getl16 (temp
+ 6);
7584 generic_bignum
[0] = bfd_getb16 (temp
+ 6);
7585 generic_bignum
[1] = bfd_getb16 (temp
+ 4);
7586 generic_bignum
[2] = bfd_getb16 (temp
+ 2);
7587 generic_bignum
[3] = bfd_getb16 (temp
);
7593 const char *newname
;
7596 /* Switch to the right section. */
7598 subseg
= now_subseg
;
7601 default: /* unused default case avoids warnings. */
7603 newname
= RDATA_SECTION_NAME
;
7604 if ((USE_GLOBAL_POINTER_OPT
&& g_switch_value
>= 8)
7605 || mips_pic
== EMBEDDED_PIC
)
7609 if (mips_pic
== EMBEDDED_PIC
)
7612 newname
= RDATA_SECTION_NAME
;
7615 assert (!USE_GLOBAL_POINTER_OPT
7616 || g_switch_value
>= 4);
7620 new_seg
= subseg_new (newname
, (subsegT
) 0);
7621 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
7622 bfd_set_section_flags (stdoutput
, new_seg
,
7627 frag_align (*args
== 'l' ? 2 : 3, 0, 0);
7628 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
7629 && strcmp (TARGET_OS
, "elf") != 0)
7630 record_alignment (new_seg
, 4);
7632 record_alignment (new_seg
, *args
== 'l' ? 2 : 3);
7634 as_bad (_("Can't use floating point insn in this section"));
7636 /* Set the argument to the current address in the
7638 offset_expr
.X_op
= O_symbol
;
7639 offset_expr
.X_add_symbol
=
7640 symbol_new ("L0\001", now_seg
,
7641 (valueT
) frag_now_fix (), frag_now
);
7642 offset_expr
.X_add_number
= 0;
7644 /* Put the floating point number into the section. */
7645 p
= frag_more ((int) length
);
7646 memcpy (p
, temp
, length
);
7648 /* Switch back to the original section. */
7649 subseg_set (seg
, subseg
);
7654 case 'i': /* 16 bit unsigned immediate */
7655 case 'j': /* 16 bit signed immediate */
7656 imm_reloc
= BFD_RELOC_LO16
;
7657 c
= my_getSmallExpression (&imm_expr
, s
);
7662 if (imm_expr
.X_op
== O_constant
)
7663 imm_expr
.X_add_number
=
7664 (imm_expr
.X_add_number
>> 16) & 0xffff;
7667 imm_reloc
= BFD_RELOC_HI16_S
;
7668 imm_unmatched_hi
= true;
7671 imm_reloc
= BFD_RELOC_HI16
;
7673 else if (imm_expr
.X_op
== O_constant
)
7674 imm_expr
.X_add_number
&= 0xffff;
7678 if ((c
== '\0' && imm_expr
.X_op
!= O_constant
)
7679 || ((imm_expr
.X_add_number
< 0
7680 || imm_expr
.X_add_number
>= 0x10000)
7681 && imm_expr
.X_op
== O_constant
))
7683 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
7684 !strcmp (insn
->name
, insn
[1].name
))
7686 if (imm_expr
.X_op
== O_constant
7687 || imm_expr
.X_op
== O_big
)
7688 as_bad (_("16 bit expression not in range 0..65535"));
7696 /* The upper bound should be 0x8000, but
7697 unfortunately the MIPS assembler accepts numbers
7698 from 0x8000 to 0xffff and sign extends them, and
7699 we want to be compatible. We only permit this
7700 extended range for an instruction which does not
7701 provide any further alternates, since those
7702 alternates may handle other cases. People should
7703 use the numbers they mean, rather than relying on
7704 a mysterious sign extension. */
7705 more
= (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
7706 strcmp (insn
->name
, insn
[1].name
) == 0);
7711 if ((c
== '\0' && imm_expr
.X_op
!= O_constant
)
7712 || ((imm_expr
.X_add_number
< -0x8000
7713 || imm_expr
.X_add_number
>= max
)
7714 && imm_expr
.X_op
== O_constant
)
7716 && imm_expr
.X_add_number
< 0
7718 && imm_expr
.X_unsigned
7719 && sizeof (imm_expr
.X_add_number
) <= 4))
7723 if (imm_expr
.X_op
== O_constant
7724 || imm_expr
.X_op
== O_big
)
7725 as_bad (_("16 bit expression not in range -32768..32767"));
7731 case 'o': /* 16 bit offset */
7732 c
= my_getSmallExpression (&offset_expr
, s
);
7734 /* If this value won't fit into a 16 bit offset, then go
7735 find a macro that will generate the 32 bit offset
7736 code pattern. As a special hack, we accept the
7737 difference of two local symbols as a constant. This
7738 is required to suppose embedded PIC switches, which
7739 use an instruction which looks like
7740 lw $4,$L12-$LS12($4)
7741 The problem with handling this in a more general
7742 fashion is that the macro function doesn't expect to
7743 see anything which can be handled in a single
7744 constant instruction. */
7746 && (offset_expr
.X_op
!= O_constant
7747 || offset_expr
.X_add_number
>= 0x8000
7748 || offset_expr
.X_add_number
< -0x8000)
7749 && (mips_pic
!= EMBEDDED_PIC
7750 || offset_expr
.X_op
!= O_subtract
7751 || (S_GET_SEGMENT (offset_expr
.X_add_symbol
)
7752 != S_GET_SEGMENT (offset_expr
.X_op_symbol
))))
7755 if (c
== 'h' || c
== 'H')
7757 if (offset_expr
.X_op
!= O_constant
)
7759 offset_expr
.X_add_number
=
7760 (offset_expr
.X_add_number
>> 16) & 0xffff;
7762 offset_reloc
= BFD_RELOC_LO16
;
7766 case 'p': /* pc relative offset */
7767 offset_reloc
= BFD_RELOC_16_PCREL_S2
;
7768 my_getExpression (&offset_expr
, s
);
7772 case 'u': /* upper 16 bits */
7773 c
= my_getSmallExpression (&imm_expr
, s
);
7774 imm_reloc
= BFD_RELOC_LO16
;
7779 if (imm_expr
.X_op
== O_constant
)
7780 imm_expr
.X_add_number
=
7781 (imm_expr
.X_add_number
>> 16) & 0xffff;
7784 imm_reloc
= BFD_RELOC_HI16_S
;
7785 imm_unmatched_hi
= true;
7788 imm_reloc
= BFD_RELOC_HI16
;
7790 else if (imm_expr
.X_op
== O_constant
)
7791 imm_expr
.X_add_number
&= 0xffff;
7793 if (imm_expr
.X_op
== O_constant
7794 && (imm_expr
.X_add_number
< 0
7795 || imm_expr
.X_add_number
>= 0x10000))
7796 as_bad (_("lui expression not in range 0..65535"));
7800 case 'a': /* 26 bit address */
7801 my_getExpression (&offset_expr
, s
);
7803 offset_reloc
= BFD_RELOC_MIPS_JMP
;
7806 case 'N': /* 3 bit branch condition code */
7807 case 'M': /* 3 bit compare condition code */
7808 if (strncmp (s
, "$fcc", 4) != 0)
7818 while (isdigit ((unsigned char) *s
));
7820 as_bad (_("invalid condition code register $fcc%d"), regno
);
7822 ip
->insn_opcode
|= regno
<< OP_SH_BCC
;
7824 ip
->insn_opcode
|= regno
<< OP_SH_CCC
;
7828 if (s
[0] == '0' && (s
[1] == 'x' || s
[1] == 'X'))
7830 if (isdigit ((unsigned char) *s
))
7839 while (isdigit ((unsigned char) *s
));
7842 c
= 8; /* Invalid sel value. */
7845 as_bad (_("invalid coprocessor sub-selection value (0-7)"));
7846 ip
->insn_opcode
|= c
;
7850 as_bad (_("bad char = '%c'\n"), *args
);
7855 /* Args don't match. */
7856 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
7857 !strcmp (insn
->name
, insn
[1].name
))
7861 insn_error
= _("illegal operands");
7866 insn_error
= _("illegal operands");
7871 /* This routine assembles an instruction into its binary format when
7872 assembling for the mips16. As a side effect, it sets one of the
7873 global variables imm_reloc or offset_reloc to the type of
7874 relocation to do if one of the operands is an address expression.
7875 It also sets mips16_small and mips16_ext if the user explicitly
7876 requested a small or extended instruction. */
7881 struct mips_cl_insn
*ip
;
7885 struct mips_opcode
*insn
;
7888 unsigned int lastregno
= 0;
7893 mips16_small
= false;
7896 for (s
= str
; islower ((unsigned char) *s
); ++s
)
7908 if (s
[1] == 't' && s
[2] == ' ')
7911 mips16_small
= true;
7915 else if (s
[1] == 'e' && s
[2] == ' ')
7924 insn_error
= _("unknown opcode");
7928 if (mips_opts
.noautoextend
&& ! mips16_ext
)
7929 mips16_small
= true;
7931 if ((insn
= (struct mips_opcode
*) hash_find (mips16_op_hash
, str
)) == NULL
)
7933 insn_error
= _("unrecognized opcode");
7940 assert (strcmp (insn
->name
, str
) == 0);
7943 ip
->insn_opcode
= insn
->match
;
7944 ip
->use_extend
= false;
7945 imm_expr
.X_op
= O_absent
;
7946 imm_reloc
= BFD_RELOC_UNUSED
;
7947 offset_expr
.X_op
= O_absent
;
7948 offset_reloc
= BFD_RELOC_UNUSED
;
7949 for (args
= insn
->args
; 1; ++args
)
7956 /* In this switch statement we call break if we did not find
7957 a match, continue if we did find a match, or return if we
7966 /* Stuff the immediate value in now, if we can. */
7967 if (imm_expr
.X_op
== O_constant
7968 && imm_reloc
> BFD_RELOC_UNUSED
7969 && insn
->pinfo
!= INSN_MACRO
)
7971 mips16_immed ((char *) NULL
, 0,
7972 imm_reloc
- BFD_RELOC_UNUSED
,
7973 imm_expr
.X_add_number
, true, mips16_small
,
7974 mips16_ext
, &ip
->insn_opcode
,
7975 &ip
->use_extend
, &ip
->extend
);
7976 imm_expr
.X_op
= O_absent
;
7977 imm_reloc
= BFD_RELOC_UNUSED
;
7991 ip
->insn_opcode
|= lastregno
<< MIPS16OP_SH_RX
;
7994 ip
->insn_opcode
|= lastregno
<< MIPS16OP_SH_RY
;
8010 ip
->insn_opcode
|= lastregno
<< MIPS16OP_SH_RX
;
8012 ip
->insn_opcode
|= lastregno
<< MIPS16OP_SH_RY
;
8029 if (isdigit ((unsigned char) s
[1]))
8039 while (isdigit ((unsigned char) *s
));
8042 as_bad (_("invalid register number (%d)"), regno
);
8048 if (s
[1] == 'f' && s
[2] == 'p')
8053 else if (s
[1] == 's' && s
[2] == 'p')
8058 else if (s
[1] == 'g' && s
[2] == 'p')
8063 else if (s
[1] == 'a' && s
[2] == 't')
8068 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '0')
8073 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '1')
8086 if (c
== 'v' || c
== 'w')
8088 regno
= mips16_to_32_reg_map
[lastregno
];
8102 regno
= mips32_to_16_reg_map
[regno
];
8107 regno
= ILLEGAL_REG
;
8112 regno
= ILLEGAL_REG
;
8117 regno
= ILLEGAL_REG
;
8122 if (regno
== AT
&& ! mips_opts
.noat
)
8123 as_warn (_("used $at without \".set noat\""));
8130 if (regno
== ILLEGAL_REG
)
8137 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_RX
;
8141 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_RY
;
8144 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_RZ
;
8147 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_MOVE32Z
;
8153 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_REGR32
;
8156 regno
= ((regno
& 7) << 2) | ((regno
& 0x18) >> 3);
8157 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_REG32R
;
8167 if (strncmp (s
, "$pc", 3) == 0)
8191 && strncmp (s
+ 1, "gprel(", sizeof "gprel(" - 1) == 0)
8193 /* This is %gprel(SYMBOL). We need to read SYMBOL,
8194 and generate the appropriate reloc. If the text
8195 inside %gprel is not a symbol name with an
8196 optional offset, then we generate a normal reloc
8197 and will probably fail later. */
8198 my_getExpression (&imm_expr
, s
+ sizeof "%gprel" - 1);
8199 if (imm_expr
.X_op
== O_symbol
)
8202 imm_reloc
= BFD_RELOC_MIPS16_GPREL
;
8204 ip
->use_extend
= true;
8211 /* Just pick up a normal expression. */
8212 my_getExpression (&imm_expr
, s
);
8215 if (imm_expr
.X_op
== O_register
)
8217 /* What we thought was an expression turned out to
8220 if (s
[0] == '(' && args
[1] == '(')
8222 /* It looks like the expression was omitted
8223 before a register indirection, which means
8224 that the expression is implicitly zero. We
8225 still set up imm_expr, so that we handle
8226 explicit extensions correctly. */
8227 imm_expr
.X_op
= O_constant
;
8228 imm_expr
.X_add_number
= 0;
8229 imm_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
8236 /* We need to relax this instruction. */
8237 imm_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
8246 /* We use offset_reloc rather than imm_reloc for the PC
8247 relative operands. This lets macros with both
8248 immediate and address operands work correctly. */
8249 my_getExpression (&offset_expr
, s
);
8251 if (offset_expr
.X_op
== O_register
)
8254 /* We need to relax this instruction. */
8255 offset_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
8259 case '6': /* break code */
8260 my_getExpression (&imm_expr
, s
);
8261 check_absolute_expr (ip
, &imm_expr
);
8262 if ((unsigned long) imm_expr
.X_add_number
> 63)
8264 as_warn (_("Invalid value for `%s' (%lu)"),
8266 (unsigned long) imm_expr
.X_add_number
);
8267 imm_expr
.X_add_number
&= 0x3f;
8269 ip
->insn_opcode
|= imm_expr
.X_add_number
<< MIPS16OP_SH_IMM6
;
8270 imm_expr
.X_op
= O_absent
;
8274 case 'a': /* 26 bit address */
8275 my_getExpression (&offset_expr
, s
);
8277 offset_reloc
= BFD_RELOC_MIPS16_JMP
;
8278 ip
->insn_opcode
<<= 16;
8281 case 'l': /* register list for entry macro */
8282 case 'L': /* register list for exit macro */
8292 int freg
, reg1
, reg2
;
8294 while (*s
== ' ' || *s
== ',')
8298 as_bad (_("can't parse register list"));
8310 while (isdigit ((unsigned char) *s
))
8332 as_bad (_("invalid register list"));
8337 while (isdigit ((unsigned char) *s
))
8344 if (freg
&& reg1
== 0 && reg2
== 0 && c
== 'L')
8349 else if (freg
&& reg1
== 0 && reg2
== 1 && c
== 'L')
8354 else if (reg1
== 4 && reg2
>= 4 && reg2
<= 7 && c
!= 'L')
8355 mask
|= (reg2
- 3) << 3;
8356 else if (reg1
== 16 && reg2
>= 16 && reg2
<= 17)
8357 mask
|= (reg2
- 15) << 1;
8358 else if (reg1
== 31 && reg2
== 31)
8362 as_bad (_("invalid register list"));
8366 /* The mask is filled in in the opcode table for the
8367 benefit of the disassembler. We remove it before
8368 applying the actual mask. */
8369 ip
->insn_opcode
&= ~ ((7 << 3) << MIPS16OP_SH_IMM6
);
8370 ip
->insn_opcode
|= mask
<< MIPS16OP_SH_IMM6
;
8374 case 'e': /* extend code */
8375 my_getExpression (&imm_expr
, s
);
8376 check_absolute_expr (ip
, &imm_expr
);
8377 if ((unsigned long) imm_expr
.X_add_number
> 0x7ff)
8379 as_warn (_("Invalid value for `%s' (%lu)"),
8381 (unsigned long) imm_expr
.X_add_number
);
8382 imm_expr
.X_add_number
&= 0x7ff;
8384 ip
->insn_opcode
|= imm_expr
.X_add_number
;
8385 imm_expr
.X_op
= O_absent
;
8395 /* Args don't match. */
8396 if (insn
+ 1 < &mips16_opcodes
[bfd_mips16_num_opcodes
] &&
8397 strcmp (insn
->name
, insn
[1].name
) == 0)
8404 insn_error
= _("illegal operands");
8410 /* This structure holds information we know about a mips16 immediate
8413 struct mips16_immed_operand
8415 /* The type code used in the argument string in the opcode table. */
8417 /* The number of bits in the short form of the opcode. */
8419 /* The number of bits in the extended form of the opcode. */
8421 /* The amount by which the short form is shifted when it is used;
8422 for example, the sw instruction has a shift count of 2. */
8424 /* The amount by which the short form is shifted when it is stored
8425 into the instruction code. */
8427 /* Non-zero if the short form is unsigned. */
8429 /* Non-zero if the extended form is unsigned. */
8431 /* Non-zero if the value is PC relative. */
8435 /* The mips16 immediate operand types. */
8437 static const struct mips16_immed_operand mips16_immed_operands
[] =
8439 { '<', 3, 5, 0, MIPS16OP_SH_RZ
, 1, 1, 0 },
8440 { '>', 3, 5, 0, MIPS16OP_SH_RX
, 1, 1, 0 },
8441 { '[', 3, 6, 0, MIPS16OP_SH_RZ
, 1, 1, 0 },
8442 { ']', 3, 6, 0, MIPS16OP_SH_RX
, 1, 1, 0 },
8443 { '4', 4, 15, 0, MIPS16OP_SH_IMM4
, 0, 0, 0 },
8444 { '5', 5, 16, 0, MIPS16OP_SH_IMM5
, 1, 0, 0 },
8445 { 'H', 5, 16, 1, MIPS16OP_SH_IMM5
, 1, 0, 0 },
8446 { 'W', 5, 16, 2, MIPS16OP_SH_IMM5
, 1, 0, 0 },
8447 { 'D', 5, 16, 3, MIPS16OP_SH_IMM5
, 1, 0, 0 },
8448 { 'j', 5, 16, 0, MIPS16OP_SH_IMM5
, 0, 0, 0 },
8449 { '8', 8, 16, 0, MIPS16OP_SH_IMM8
, 1, 0, 0 },
8450 { 'V', 8, 16, 2, MIPS16OP_SH_IMM8
, 1, 0, 0 },
8451 { 'C', 8, 16, 3, MIPS16OP_SH_IMM8
, 1, 0, 0 },
8452 { 'U', 8, 16, 0, MIPS16OP_SH_IMM8
, 1, 1, 0 },
8453 { 'k', 8, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 0 },
8454 { 'K', 8, 16, 3, MIPS16OP_SH_IMM8
, 0, 0, 0 },
8455 { 'p', 8, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 1 },
8456 { 'q', 11, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 1 },
8457 { 'A', 8, 16, 2, MIPS16OP_SH_IMM8
, 1, 0, 1 },
8458 { 'B', 5, 16, 3, MIPS16OP_SH_IMM5
, 1, 0, 1 },
8459 { 'E', 5, 16, 2, MIPS16OP_SH_IMM5
, 1, 0, 1 }
8462 #define MIPS16_NUM_IMMED \
8463 (sizeof mips16_immed_operands / sizeof mips16_immed_operands[0])
8465 /* Handle a mips16 instruction with an immediate value. This or's the
8466 small immediate value into *INSN. It sets *USE_EXTEND to indicate
8467 whether an extended value is needed; if one is needed, it sets
8468 *EXTEND to the value. The argument type is TYPE. The value is VAL.
8469 If SMALL is true, an unextended opcode was explicitly requested.
8470 If EXT is true, an extended opcode was explicitly requested. If
8471 WARN is true, warn if EXT does not match reality. */
8474 mips16_immed (file
, line
, type
, val
, warn
, small
, ext
, insn
, use_extend
,
8483 unsigned long *insn
;
8484 boolean
*use_extend
;
8485 unsigned short *extend
;
8487 register const struct mips16_immed_operand
*op
;
8488 int mintiny
, maxtiny
;
8491 op
= mips16_immed_operands
;
8492 while (op
->type
!= type
)
8495 assert (op
< mips16_immed_operands
+ MIPS16_NUM_IMMED
);
8500 if (type
== '<' || type
== '>' || type
== '[' || type
== ']')
8503 maxtiny
= 1 << op
->nbits
;
8508 maxtiny
= (1 << op
->nbits
) - 1;
8513 mintiny
= - (1 << (op
->nbits
- 1));
8514 maxtiny
= (1 << (op
->nbits
- 1)) - 1;
8517 /* Branch offsets have an implicit 0 in the lowest bit. */
8518 if (type
== 'p' || type
== 'q')
8521 if ((val
& ((1 << op
->shift
) - 1)) != 0
8522 || val
< (mintiny
<< op
->shift
)
8523 || val
> (maxtiny
<< op
->shift
))
8528 if (warn
&& ext
&& ! needext
)
8529 as_warn_where (file
, line
,
8530 _("extended operand requested but not required"));
8531 if (small
&& needext
)
8532 as_bad_where (file
, line
, _("invalid unextended operand value"));
8534 if (small
|| (! ext
&& ! needext
))
8538 *use_extend
= false;
8539 insnval
= ((val
>> op
->shift
) & ((1 << op
->nbits
) - 1));
8540 insnval
<<= op
->op_shift
;
8545 long minext
, maxext
;
8551 maxext
= (1 << op
->extbits
) - 1;
8555 minext
= - (1 << (op
->extbits
- 1));
8556 maxext
= (1 << (op
->extbits
- 1)) - 1;
8558 if (val
< minext
|| val
> maxext
)
8559 as_bad_where (file
, line
,
8560 _("operand value out of range for instruction"));
8563 if (op
->extbits
== 16)
8565 extval
= ((val
>> 11) & 0x1f) | (val
& 0x7e0);
8568 else if (op
->extbits
== 15)
8570 extval
= ((val
>> 11) & 0xf) | (val
& 0x7f0);
8575 extval
= ((val
& 0x1f) << 6) | (val
& 0x20);
8579 *extend
= (unsigned short) extval
;
8588 my_getSmallExpression (ep
, str
)
8599 ((str
[1] == 'h' && str
[2] == 'i')
8600 || (str
[1] == 'H' && str
[2] == 'I')
8601 || (str
[1] == 'l' && str
[2] == 'o'))
8613 * A small expression may be followed by a base register.
8614 * Scan to the end of this operand, and then back over a possible
8615 * base register. Then scan the small expression up to that
8616 * point. (Based on code in sparc.c...)
8618 for (sp
= str
; *sp
&& *sp
!= ','; sp
++)
8620 if (sp
- 4 >= str
&& sp
[-1] == RP
)
8622 if (isdigit ((unsigned char) sp
[-2]))
8624 for (sp
-= 3; sp
>= str
&& isdigit ((unsigned char) *sp
); sp
--)
8626 if (*sp
== '$' && sp
> str
&& sp
[-1] == LP
)
8632 else if (sp
- 5 >= str
8635 && ((sp
[-3] == 'f' && sp
[-2] == 'p')
8636 || (sp
[-3] == 's' && sp
[-2] == 'p')
8637 || (sp
[-3] == 'g' && sp
[-2] == 'p')
8638 || (sp
[-3] == 'a' && sp
[-2] == 't')))
8644 /* no expression means zero offset */
8647 /* %xx(reg) is an error */
8648 ep
->X_op
= O_absent
;
8653 ep
->X_op
= O_constant
;
8656 ep
->X_add_symbol
= NULL
;
8657 ep
->X_op_symbol
= NULL
;
8658 ep
->X_add_number
= 0;
8663 my_getExpression (ep
, str
);
8670 my_getExpression (ep
, str
);
8671 return c
; /* => %hi or %lo encountered */
8675 my_getExpression (ep
, str
)
8682 save_in
= input_line_pointer
;
8683 input_line_pointer
= str
;
8685 expr_end
= input_line_pointer
;
8686 input_line_pointer
= save_in
;
8688 /* If we are in mips16 mode, and this is an expression based on `.',
8689 then we bump the value of the symbol by 1 since that is how other
8690 text symbols are handled. We don't bother to handle complex
8691 expressions, just `.' plus or minus a constant. */
8692 if (mips_opts
.mips16
8693 && ep
->X_op
== O_symbol
8694 && strcmp (S_GET_NAME (ep
->X_add_symbol
), FAKE_LABEL_NAME
) == 0
8695 && S_GET_SEGMENT (ep
->X_add_symbol
) == now_seg
8696 && symbol_get_frag (ep
->X_add_symbol
) == frag_now
8697 && symbol_constant_p (ep
->X_add_symbol
)
8698 && (val
= S_GET_VALUE (ep
->X_add_symbol
)) == frag_now_fix ())
8699 S_SET_VALUE (ep
->X_add_symbol
, val
+ 1);
8702 /* Turn a string in input_line_pointer into a floating point constant
8703 of type TYPE, and store the appropriate bytes in *LITP. The number
8704 of LITTLENUMS emitted is stored in *SIZEP. An error message is
8705 returned, or NULL on OK. */
8708 md_atof (type
, litP
, sizeP
)
8714 LITTLENUM_TYPE words
[4];
8730 return _("bad call to md_atof");
8733 t
= atof_ieee (input_line_pointer
, type
, words
);
8735 input_line_pointer
= t
;
8739 if (! target_big_endian
)
8741 for (i
= prec
- 1; i
>= 0; i
--)
8743 md_number_to_chars (litP
, (valueT
) words
[i
], 2);
8749 for (i
= 0; i
< prec
; i
++)
8751 md_number_to_chars (litP
, (valueT
) words
[i
], 2);
8760 md_number_to_chars (buf
, val
, n
)
8765 if (target_big_endian
)
8766 number_to_chars_bigendian (buf
, val
, n
);
8768 number_to_chars_littleendian (buf
, val
, n
);
8771 CONST
char *md_shortopts
= "nO::g::G:";
8773 struct option md_longopts
[] =
8775 #define OPTION_MIPS1 (OPTION_MD_BASE + 1)
8776 {"mips0", no_argument
, NULL
, OPTION_MIPS1
},
8777 {"mips1", no_argument
, NULL
, OPTION_MIPS1
},
8778 #define OPTION_MIPS2 (OPTION_MD_BASE + 2)
8779 {"mips2", no_argument
, NULL
, OPTION_MIPS2
},
8780 #define OPTION_MIPS3 (OPTION_MD_BASE + 3)
8781 {"mips3", no_argument
, NULL
, OPTION_MIPS3
},
8782 #define OPTION_MIPS4 (OPTION_MD_BASE + 4)
8783 {"mips4", no_argument
, NULL
, OPTION_MIPS4
},
8784 #define OPTION_MCPU (OPTION_MD_BASE + 5)
8785 {"mcpu", required_argument
, NULL
, OPTION_MCPU
},
8786 #define OPTION_MEMBEDDED_PIC (OPTION_MD_BASE + 6)
8787 {"membedded-pic", no_argument
, NULL
, OPTION_MEMBEDDED_PIC
},
8788 #define OPTION_TRAP (OPTION_MD_BASE + 7)
8789 {"trap", no_argument
, NULL
, OPTION_TRAP
},
8790 {"no-break", no_argument
, NULL
, OPTION_TRAP
},
8791 #define OPTION_BREAK (OPTION_MD_BASE + 8)
8792 {"break", no_argument
, NULL
, OPTION_BREAK
},
8793 {"no-trap", no_argument
, NULL
, OPTION_BREAK
},
8794 #define OPTION_EB (OPTION_MD_BASE + 9)
8795 {"EB", no_argument
, NULL
, OPTION_EB
},
8796 #define OPTION_EL (OPTION_MD_BASE + 10)
8797 {"EL", no_argument
, NULL
, OPTION_EL
},
8798 #define OPTION_M4650 (OPTION_MD_BASE + 11)
8799 {"m4650", no_argument
, NULL
, OPTION_M4650
},
8800 #define OPTION_NO_M4650 (OPTION_MD_BASE + 12)
8801 {"no-m4650", no_argument
, NULL
, OPTION_NO_M4650
},
8802 #define OPTION_M4010 (OPTION_MD_BASE + 13)
8803 {"m4010", no_argument
, NULL
, OPTION_M4010
},
8804 #define OPTION_NO_M4010 (OPTION_MD_BASE + 14)
8805 {"no-m4010", no_argument
, NULL
, OPTION_NO_M4010
},
8806 #define OPTION_M4100 (OPTION_MD_BASE + 15)
8807 {"m4100", no_argument
, NULL
, OPTION_M4100
},
8808 #define OPTION_NO_M4100 (OPTION_MD_BASE + 16)
8809 {"no-m4100", no_argument
, NULL
, OPTION_NO_M4100
},
8810 #define OPTION_MIPS16 (OPTION_MD_BASE + 17)
8811 {"mips16", no_argument
, NULL
, OPTION_MIPS16
},
8812 #define OPTION_NO_MIPS16 (OPTION_MD_BASE + 18)
8813 {"no-mips16", no_argument
, NULL
, OPTION_NO_MIPS16
},
8814 #define OPTION_M3900 (OPTION_MD_BASE + 19)
8815 {"m3900", no_argument
, NULL
, OPTION_M3900
},
8816 #define OPTION_NO_M3900 (OPTION_MD_BASE + 20)
8817 {"no-m3900", no_argument
, NULL
, OPTION_NO_M3900
},
8818 #define OPTION_MABI (OPTION_MD_BASE + 21)
8819 {"mabi", required_argument
, NULL
, OPTION_MABI
},
8820 #define OPTION_M7000_HILO_FIX (OPTION_MD_BASE + 22)
8821 {"mfix7000", no_argument
, NULL
, OPTION_M7000_HILO_FIX
},
8822 #define OPTION_NO_M7000_HILO_FIX (OPTION_MD_BASE + 23)
8823 {"no-fix-7000", no_argument
, NULL
, OPTION_NO_M7000_HILO_FIX
},
8824 #define OPTION_GP32 (OPTION_MD_BASE + 24)
8825 {"mgp32", no_argument
, NULL
, OPTION_GP32
},
8826 #define OPTION_GP64 (OPTION_MD_BASE + 25)
8827 {"mgp64", no_argument
, NULL
, OPTION_GP64
},
8828 #define OPTION_CONSTRUCT_FLOATS (OPTION_MD_BASE + 26)
8829 {"construct-floats", no_argument
, NULL
, OPTION_CONSTRUCT_FLOATS
},
8830 #define OPTION_NO_CONSTRUCT_FLOATS (OPTION_MD_BASE + 27)
8831 {"no-construct-floats", no_argument
, NULL
, OPTION_NO_CONSTRUCT_FLOATS
},
8832 #define OPTION_MIPS32 (OPTION_MD_BASE + 28)
8833 {"mips32", no_argument
, NULL
, OPTION_MIPS32
},
8834 #define OPTION_MIPS5 (OPTION_MD_BASE + 29)
8835 {"mips5", no_argument
, NULL
, OPTION_MIPS5
},
8836 #define OPTION_MIPS64 (OPTION_MD_BASE + 30)
8837 {"mips64", no_argument
, NULL
, OPTION_MIPS64
},
8838 #define OPTION_MARCH (OPTION_MD_BASE + 31)
8839 {"march", required_argument
, NULL
, OPTION_MARCH
},
8840 #define OPTION_MTUNE (OPTION_MD_BASE + 32)
8841 {"mtune", required_argument
, NULL
, OPTION_MTUNE
},
8842 #define OPTION_FP32 (OPTION_MD_BASE + 33)
8843 {"mfp32", no_argument
, NULL
, OPTION_FP32
},
8845 #define OPTION_ELF_BASE (OPTION_MD_BASE + 35)
8846 #define OPTION_CALL_SHARED (OPTION_ELF_BASE + 0)
8847 #define OPTION_NON_SHARED (OPTION_ELF_BASE + 1)
8848 #define OPTION_XGOT (OPTION_ELF_BASE + 2)
8849 #define OPTION_32 (OPTION_ELF_BASE + 3)
8850 #define OPTION_64 (OPTION_ELF_BASE + 4)
8851 {"KPIC", no_argument
, NULL
, OPTION_CALL_SHARED
},
8852 {"call_shared", no_argument
, NULL
, OPTION_CALL_SHARED
},
8853 {"non_shared", no_argument
, NULL
, OPTION_NON_SHARED
},
8854 {"xgot", no_argument
, NULL
, OPTION_XGOT
},
8855 {"32", no_argument
, NULL
, OPTION_32
},
8856 {"64", no_argument
, NULL
, OPTION_64
},
8859 {NULL
, no_argument
, NULL
, 0}
8861 size_t md_longopts_size
= sizeof (md_longopts
);
8864 md_parse_option (c
, arg
)
8870 case OPTION_CONSTRUCT_FLOATS
:
8871 mips_disable_float_construction
= 0;
8874 case OPTION_NO_CONSTRUCT_FLOATS
:
8875 mips_disable_float_construction
= 1;
8887 target_big_endian
= 1;
8891 target_big_endian
= 0;
8899 if (arg
&& arg
[1] == '0')
8909 mips_debug
= atoi (arg
);
8910 /* When the MIPS assembler sees -g or -g2, it does not do
8911 optimizations which limit full symbolic debugging. We take
8912 that to be equivalent to -O0. */
8913 if (mips_debug
== 2)
8918 mips_opts
.isa
= ISA_MIPS1
;
8922 mips_opts
.isa
= ISA_MIPS2
;
8926 mips_opts
.isa
= ISA_MIPS3
;
8930 mips_opts
.isa
= ISA_MIPS4
;
8934 mips_opts
.isa
= ISA_MIPS5
;
8938 mips_opts
.isa
= ISA_MIPS32
;
8942 mips_opts
.isa
= ISA_MIPS64
;
8949 int cpu
= CPU_UNKNOWN
;
8951 /* Identify the processor type. */
8952 if (strcasecmp (arg
, "default") != 0)
8954 const struct mips_cpu_info
*ci
;
8956 ci
= mips_cpu_info_from_name (arg
);
8957 if (ci
== NULL
|| ci
->is_isa
)
8962 as_fatal (_("invalid architecture -mtune=%s"), arg
);
8965 as_fatal (_("invalid architecture -march=%s"), arg
);
8968 as_fatal (_("invalid architecture -mcpu=%s"), arg
);
8979 if (mips_tune
!= CPU_UNKNOWN
&& mips_tune
!= cpu
)
8980 as_warn(_("A different -mtune= was already specified, is now "
8985 if (mips_arch
!= CPU_UNKNOWN
&& mips_arch
!= cpu
)
8986 as_warn(_("A different -march= was already specified, is now "
8991 if (mips_cpu
!= CPU_UNKNOWN
&& mips_cpu
!= cpu
)
8992 as_warn(_("A different -mcpu= was already specified, is now "
9000 if ((mips_arch
!= CPU_UNKNOWN
&& mips_arch
!= CPU_R4650
)
9001 || (mips_tune
!= CPU_UNKNOWN
&& mips_tune
!= CPU_R4650
))
9002 as_warn(_("A different -march= or -mtune= was already specified, "
9004 mips_arch
= CPU_R4650
;
9005 mips_tune
= CPU_R4650
;
9008 case OPTION_NO_M4650
:
9012 if ((mips_arch
!= CPU_UNKNOWN
&& mips_arch
!= CPU_R4010
)
9013 || (mips_tune
!= CPU_UNKNOWN
&& mips_tune
!= CPU_R4010
))
9014 as_warn(_("A different -march= or -mtune= was already specified, "
9016 mips_arch
= CPU_R4010
;
9017 mips_tune
= CPU_R4010
;
9020 case OPTION_NO_M4010
:
9024 if ((mips_arch
!= CPU_UNKNOWN
&& mips_arch
!= CPU_VR4100
)
9025 || (mips_tune
!= CPU_UNKNOWN
&& mips_tune
!= CPU_VR4100
))
9026 as_warn(_("A different -march= or -mtune= was already specified, "
9028 mips_arch
= CPU_VR4100
;
9029 mips_tune
= CPU_VR4100
;
9032 case OPTION_NO_M4100
:
9036 if ((mips_arch
!= CPU_UNKNOWN
&& mips_arch
!= CPU_R3900
)
9037 || (mips_tune
!= CPU_UNKNOWN
&& mips_tune
!= CPU_R3900
))
9038 as_warn(_("A different -march= or -mtune= was already specified, "
9040 mips_arch
= CPU_R3900
;
9041 mips_tune
= CPU_R3900
;
9044 case OPTION_NO_M3900
:
9048 mips_opts
.mips16
= 1;
9049 mips_no_prev_insn (false);
9052 case OPTION_NO_MIPS16
:
9053 mips_opts
.mips16
= 0;
9054 mips_no_prev_insn (false);
9057 case OPTION_MEMBEDDED_PIC
:
9058 mips_pic
= EMBEDDED_PIC
;
9059 if (USE_GLOBAL_POINTER_OPT
&& g_switch_seen
)
9061 as_bad (_("-G may not be used with embedded PIC code"));
9064 g_switch_value
= 0x7fffffff;
9068 /* When generating ELF code, we permit -KPIC and -call_shared to
9069 select SVR4_PIC, and -non_shared to select no PIC. This is
9070 intended to be compatible with Irix 5. */
9071 case OPTION_CALL_SHARED
:
9072 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
9074 as_bad (_("-call_shared is supported only for ELF format"));
9077 mips_pic
= SVR4_PIC
;
9078 if (g_switch_seen
&& g_switch_value
!= 0)
9080 as_bad (_("-G may not be used with SVR4 PIC code"));
9086 case OPTION_NON_SHARED
:
9087 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
9089 as_bad (_("-non_shared is supported only for ELF format"));
9095 /* The -xgot option tells the assembler to use 32 offsets when
9096 accessing the got in SVR4_PIC mode. It is for Irix
9101 #endif /* OBJ_ELF */
9104 if (! USE_GLOBAL_POINTER_OPT
)
9106 as_bad (_("-G is not supported for this configuration"));
9109 else if (mips_pic
== SVR4_PIC
|| mips_pic
== EMBEDDED_PIC
)
9111 as_bad (_("-G may not be used with SVR4 or embedded PIC code"));
9115 g_switch_value
= atoi (arg
);
9120 /* The -32 and -64 options tell the assembler to output the 32
9121 bit or the 64 bit MIPS ELF format. */
9128 const char **list
, **l
;
9130 list
= bfd_target_list ();
9131 for (l
= list
; *l
!= NULL
; l
++)
9132 if (strcmp (*l
, "elf64-bigmips") == 0
9133 || strcmp (*l
, "elf64-littlemips") == 0
9134 || strcmp (*l
, "elf64-tradbigmips") == 0
9135 || strcmp (*l
, "elf64-tradlittlemips") == 0)
9138 as_fatal (_("No compiled in support for 64 bit object file format"));
9143 #endif /* OBJ_ELF */
9149 /* We deliberately don't allow "-gp32" to set the MIPS_32BITMODE
9150 flag in object files because to do so would make it
9151 impossible to link with libraries compiled without "-gp32".
9152 This is unnecessarily restrictive.
9154 We could solve this problem by adding "-gp32" multilibs to
9155 gcc, but to set this flag before gcc is built with such
9156 multilibs will break too many systems. */
9176 if (strcmp (arg
, "32") == 0
9177 || strcmp (arg
, "n32") == 0
9178 || strcmp (arg
, "64") == 0
9179 || strcmp (arg
, "o64") == 0
9180 || strcmp (arg
, "eabi") == 0)
9182 mips_abi_string
= arg
;
9183 mips_32bit_abi
= (strcmp (arg
, "32") == 0);
9187 case OPTION_M7000_HILO_FIX
:
9188 mips_7000_hilo_fix
= true;
9191 case OPTION_NO_M7000_HILO_FIX
:
9192 mips_7000_hilo_fix
= false;
9203 show (stream
, string
, col_p
, first_p
)
9211 fprintf (stream
, "%24s", "");
9216 fprintf (stream
, ", ");
9220 if (*col_p
+ strlen (string
) > 72)
9222 fprintf (stream
, "\n%24s", "");
9226 fprintf (stream
, "%s", string
);
9227 *col_p
+= strlen (string
);
9233 md_show_usage (stream
)
9238 fprintf (stream
, _("\
9240 -membedded-pic generate embedded position independent code\n\
9241 -EB generate big endian output\n\
9242 -EL generate little endian output\n\
9243 -g, -g2 do not remove unneeded NOPs or swap branches\n\
9244 -G NUM allow referencing objects up to NUM bytes\n\
9245 implicitly with the gp register [default 8]\n"));
9246 fprintf (stream
, _("\
9247 -mips1 generate MIPS ISA I instructions\n\
9248 -mips2 generate MIPS ISA II instructions\n\
9249 -mips3 generate MIPS ISA III instructions\n\
9250 -mips4 generate MIPS ISA IV instructions\n\
9251 -mips5 generate MIPS ISA V instructions\n\
9252 -mips32 generate MIPS32 ISA instructions\n\
9253 -mips64 generate MIPS64 ISA instructions\n\
9254 -march=CPU/-mtune=CPU generate code/schedule for CPU, where CPU is one of:\n"));
9258 show (stream
, "2000", &column
, &first
);
9259 show (stream
, "3000", &column
, &first
);
9260 show (stream
, "3900", &column
, &first
);
9261 show (stream
, "4000", &column
, &first
);
9262 show (stream
, "4010", &column
, &first
);
9263 show (stream
, "4100", &column
, &first
);
9264 show (stream
, "4111", &column
, &first
);
9265 show (stream
, "4300", &column
, &first
);
9266 show (stream
, "4400", &column
, &first
);
9267 show (stream
, "4600", &column
, &first
);
9268 show (stream
, "4650", &column
, &first
);
9269 show (stream
, "5000", &column
, &first
);
9270 show (stream
, "5200", &column
, &first
);
9271 show (stream
, "5230", &column
, &first
);
9272 show (stream
, "5231", &column
, &first
);
9273 show (stream
, "5261", &column
, &first
);
9274 show (stream
, "5721", &column
, &first
);
9275 show (stream
, "6000", &column
, &first
);
9276 show (stream
, "8000", &column
, &first
);
9277 show (stream
, "10000", &column
, &first
);
9278 show (stream
, "12000", &column
, &first
);
9279 show (stream
, "mips32-4k", &column
, &first
);
9280 show (stream
, "sb-1", &column
, &first
);
9281 fputc ('\n', stream
);
9283 fprintf (stream
, _("\
9284 -mCPU equivalent to -march=CPU -mtune=CPU. Deprecated.\n\
9285 -no-mCPU don't generate code specific to CPU.\n\
9286 For -mCPU and -no-mCPU, CPU must be one of:\n"));
9290 show (stream
, "3900", &column
, &first
);
9291 show (stream
, "4010", &column
, &first
);
9292 show (stream
, "4100", &column
, &first
);
9293 show (stream
, "4650", &column
, &first
);
9294 fputc ('\n', stream
);
9296 fprintf (stream
, _("\
9297 -mips16 generate mips16 instructions\n\
9298 -no-mips16 do not generate mips16 instructions\n"));
9299 fprintf (stream
, _("\
9300 -mgp32 use 32-bit GPRs, regardless of the chosen ISA\n\
9301 -mfp32 use 32-bit FPRs, regardless of the chosen ISA\n\
9302 -O0 remove unneeded NOPs, do not swap branches\n\
9303 -O remove unneeded NOPs and swap branches\n\
9304 -n warn about NOPs generated from macros\n\
9305 --[no-]construct-floats [dis]allow floating point values to be constructed\n\
9306 --trap, --no-break trap exception on div by 0 and mult overflow\n\
9307 --break, --no-trap break exception on div by 0 and mult overflow\n"));
9309 fprintf (stream
, _("\
9310 -KPIC, -call_shared generate SVR4 position independent code\n\
9311 -non_shared do not generate position independent code\n\
9312 -xgot assume a 32 bit GOT\n\
9313 -32 create 32 bit object file (default)\n\
9314 -64 create 64 bit object file\n"));
9319 mips_init_after_args ()
9321 /* initialize opcodes */
9322 bfd_mips_num_opcodes
= bfd_mips_num_builtin_opcodes
;
9323 mips_opcodes
= (struct mips_opcode
*) mips_builtin_opcodes
;
9327 md_pcrel_from (fixP
)
9330 if (OUTPUT_FLAVOR
!= bfd_target_aout_flavour
9331 && fixP
->fx_addsy
!= (symbolS
*) NULL
9332 && ! S_IS_DEFINED (fixP
->fx_addsy
))
9334 /* This makes a branch to an undefined symbol be a branch to the
9335 current location. */
9339 /* return the address of the delay slot */
9340 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
9343 /* This is called before the symbol table is processed. In order to
9344 work with gcc when using mips-tfile, we must keep all local labels.
9345 However, in other cases, we want to discard them. If we were
9346 called with -g, but we didn't see any debugging information, it may
9347 mean that gcc is smuggling debugging information through to
9348 mips-tfile, in which case we must generate all local labels. */
9351 mips_frob_file_before_adjust ()
9353 #ifndef NO_ECOFF_DEBUGGING
9356 && ! ecoff_debugging_seen
)
9357 flag_keep_locals
= 1;
9361 /* Sort any unmatched HI16_S relocs so that they immediately precede
9362 the corresponding LO reloc. This is called before md_apply_fix and
9363 tc_gen_reloc. Unmatched HI16_S relocs can only be generated by
9364 explicit use of the %hi modifier. */
9369 struct mips_hi_fixup
*l
;
9371 for (l
= mips_hi_fixup_list
; l
!= NULL
; l
= l
->next
)
9373 segment_info_type
*seginfo
;
9376 assert (l
->fixp
->fx_r_type
== BFD_RELOC_HI16_S
);
9378 /* Check quickly whether the next fixup happens to be a matching
9380 if (l
->fixp
->fx_next
!= NULL
9381 && l
->fixp
->fx_next
->fx_r_type
== BFD_RELOC_LO16
9382 && l
->fixp
->fx_addsy
== l
->fixp
->fx_next
->fx_addsy
9383 && l
->fixp
->fx_offset
== l
->fixp
->fx_next
->fx_offset
)
9386 /* Look through the fixups for this segment for a matching %lo.
9387 When we find one, move the %hi just in front of it. We do
9388 this in two passes. In the first pass, we try to find a
9389 unique %lo. In the second pass, we permit multiple %hi
9390 relocs for a single %lo (this is a GNU extension). */
9391 seginfo
= seg_info (l
->seg
);
9392 for (pass
= 0; pass
< 2; pass
++)
9397 for (f
= seginfo
->fix_root
; f
!= NULL
; f
= f
->fx_next
)
9399 /* Check whether this is a %lo fixup which matches l->fixp. */
9400 if (f
->fx_r_type
== BFD_RELOC_LO16
9401 && f
->fx_addsy
== l
->fixp
->fx_addsy
9402 && f
->fx_offset
== l
->fixp
->fx_offset
9405 || prev
->fx_r_type
!= BFD_RELOC_HI16_S
9406 || prev
->fx_addsy
!= f
->fx_addsy
9407 || prev
->fx_offset
!= f
->fx_offset
))
9411 /* Move l->fixp before f. */
9412 for (pf
= &seginfo
->fix_root
;
9414 pf
= &(*pf
)->fx_next
)
9415 assert (*pf
!= NULL
);
9417 *pf
= l
->fixp
->fx_next
;
9419 l
->fixp
->fx_next
= f
;
9421 seginfo
->fix_root
= l
->fixp
;
9423 prev
->fx_next
= l
->fixp
;
9434 #if 0 /* GCC code motion plus incomplete dead code elimination
9435 can leave a %hi without a %lo. */
9437 as_warn_where (l
->fixp
->fx_file
, l
->fixp
->fx_line
,
9438 _("Unmatched %%hi reloc"));
9444 /* When generating embedded PIC code we need to use a special
9445 relocation to represent the difference of two symbols in the .text
9446 section (switch tables use a difference of this sort). See
9447 include/coff/mips.h for details. This macro checks whether this
9448 fixup requires the special reloc. */
9449 #define SWITCH_TABLE(fixp) \
9450 ((fixp)->fx_r_type == BFD_RELOC_32 \
9451 && OUTPUT_FLAVOR != bfd_target_elf_flavour \
9452 && (fixp)->fx_addsy != NULL \
9453 && (fixp)->fx_subsy != NULL \
9454 && S_GET_SEGMENT ((fixp)->fx_addsy) == text_section \
9455 && S_GET_SEGMENT ((fixp)->fx_subsy) == text_section)
9457 /* When generating embedded PIC code we must keep all PC relative
9458 relocations, in case the linker has to relax a call. We also need
9459 to keep relocations for switch table entries. */
9462 mips_force_relocation (fixp
)
9465 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
9466 || fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
9469 return (mips_pic
== EMBEDDED_PIC
9471 || SWITCH_TABLE (fixp
)
9472 || fixp
->fx_r_type
== BFD_RELOC_PCREL_HI16_S
9473 || fixp
->fx_r_type
== BFD_RELOC_PCREL_LO16
));
9476 /* Apply a fixup to the object file. */
9479 md_apply_fix (fixP
, valueP
)
9487 assert (fixP
->fx_size
== 4
9488 || fixP
->fx_r_type
== BFD_RELOC_16
9489 || fixP
->fx_r_type
== BFD_RELOC_64
9490 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
9491 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
);
9495 /* If we aren't adjusting this fixup to be against the section
9496 symbol, we need to adjust the value. */
9498 if (fixP
->fx_addsy
!= NULL
&& OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
9500 if (S_GET_OTHER (fixP
->fx_addsy
) == STO_MIPS16
9501 || ((S_IS_WEAK (fixP
->fx_addsy
)
9502 || S_IS_EXTERN (fixP
->fx_addsy
))
9503 && !S_IS_COMMON (fixP
->fx_addsy
))
9504 || (symbol_used_in_reloc_p (fixP
->fx_addsy
)
9505 && (((bfd_get_section_flags (stdoutput
,
9506 S_GET_SEGMENT (fixP
->fx_addsy
))
9507 & SEC_LINK_ONCE
) != 0)
9508 || !strncmp (segment_name (S_GET_SEGMENT (fixP
->fx_addsy
)),
9510 sizeof (".gnu.linkonce") - 1))))
9513 valueT symval
= S_GET_VALUE (fixP
->fx_addsy
);
9517 && fixP
->fx_r_type
!= BFD_RELOC_MIPS_GPREL
)
9519 /* In this case, the bfd_install_relocation routine will
9520 incorrectly add the symbol value back in. We just want
9521 the addend to appear in the object file. */
9524 /* Make sure the addend is still non-zero. If it became zero
9525 after the last operation, set it to a spurious value and
9526 subtract the same value from the object file's contents. */
9531 /* The in-place addends for LO16 relocations are signed;
9532 leave the matching HI16 in-place addends as zero. */
9533 if (fixP
->fx_r_type
!= BFD_RELOC_HI16_S
)
9535 reloc_howto_type
*howto
;
9536 bfd_vma contents
, mask
, field
;
9538 howto
= bfd_reloc_type_lookup (stdoutput
,
9541 contents
= bfd_get_bits (fixP
->fx_frag
->fr_literal
9546 /* MASK has bits set where the relocation should go.
9547 FIELD is -value, shifted into the appropriate place
9548 for this relocation. */
9549 mask
= 1 << (howto
->bitsize
- 1);
9550 mask
= (((mask
- 1) << 1) | 1) << howto
->bitpos
;
9551 field
= (-value
>> howto
->rightshift
) << howto
->bitpos
;
9553 bfd_put_bits ((field
& mask
) | (contents
& ~mask
),
9554 fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
,
9562 /* This code was generated using trial and error and so is
9563 fragile and not trustworthy. If you change it, you should
9564 rerun the elf-rel, elf-rel2, and empic testcases and ensure
9566 if (fixP
->fx_pcrel
|| fixP
->fx_subsy
!= NULL
)
9568 value
+= fixP
->fx_frag
->fr_address
+ fixP
->fx_where
;
9570 /* BFD's REL handling, for MIPS, is _very_ weird.
9571 This gives the right results, but it can't possibly
9572 be the way things are supposed to work. */
9573 if (fixP
->fx_r_type
!= BFD_RELOC_16_PCREL_S2
9574 || S_GET_SEGMENT (fixP
->fx_addsy
) != undefined_section
)
9575 value
+= fixP
->fx_frag
->fr_address
+ fixP
->fx_where
;
9580 fixP
->fx_addnumber
= value
; /* Remember value for tc_gen_reloc */
9582 if (fixP
->fx_addsy
== NULL
&& ! fixP
->fx_pcrel
)
9585 switch (fixP
->fx_r_type
)
9587 case BFD_RELOC_MIPS_JMP
:
9588 case BFD_RELOC_HI16
:
9589 case BFD_RELOC_HI16_S
:
9590 case BFD_RELOC_MIPS_GPREL
:
9591 case BFD_RELOC_MIPS_LITERAL
:
9592 case BFD_RELOC_MIPS_CALL16
:
9593 case BFD_RELOC_MIPS_GOT16
:
9594 case BFD_RELOC_MIPS_GPREL32
:
9595 case BFD_RELOC_MIPS_GOT_HI16
:
9596 case BFD_RELOC_MIPS_GOT_LO16
:
9597 case BFD_RELOC_MIPS_CALL_HI16
:
9598 case BFD_RELOC_MIPS_CALL_LO16
:
9599 case BFD_RELOC_MIPS16_GPREL
:
9601 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
9602 _("Invalid PC relative reloc"));
9603 /* Nothing needed to do. The value comes from the reloc entry */
9606 case BFD_RELOC_MIPS16_JMP
:
9607 /* We currently always generate a reloc against a symbol, which
9608 means that we don't want an addend even if the symbol is
9610 fixP
->fx_addnumber
= 0;
9613 case BFD_RELOC_PCREL_HI16_S
:
9614 /* The addend for this is tricky if it is internal, so we just
9615 do everything here rather than in bfd_install_relocation. */
9616 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
9621 && (symbol_get_bfdsym (fixP
->fx_addsy
)->flags
& BSF_SECTION_SYM
) == 0)
9623 /* For an external symbol adjust by the address to make it
9624 pcrel_offset. We use the address of the RELLO reloc
9625 which follows this one. */
9626 value
+= (fixP
->fx_next
->fx_frag
->fr_address
9627 + fixP
->fx_next
->fx_where
);
9632 buf
= (unsigned char *) fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
9633 if (target_big_endian
)
9635 md_number_to_chars (buf
, value
, 2);
9638 case BFD_RELOC_PCREL_LO16
:
9639 /* The addend for this is tricky if it is internal, so we just
9640 do everything here rather than in bfd_install_relocation. */
9641 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
9646 && (symbol_get_bfdsym (fixP
->fx_addsy
)->flags
& BSF_SECTION_SYM
) == 0)
9647 value
+= fixP
->fx_frag
->fr_address
+ fixP
->fx_where
;
9648 buf
= (unsigned char *) fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
9649 if (target_big_endian
)
9651 md_number_to_chars (buf
, value
, 2);
9655 /* This is handled like BFD_RELOC_32, but we output a sign
9656 extended value if we are only 32 bits. */
9658 || (mips_pic
== EMBEDDED_PIC
&& SWITCH_TABLE (fixP
)))
9660 if (8 <= sizeof (valueT
))
9661 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
,
9668 w1
= w2
= fixP
->fx_where
;
9669 if (target_big_endian
)
9673 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ w1
, value
, 4);
9674 if ((value
& 0x80000000) != 0)
9678 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ w2
, hiv
, 4);
9685 /* If we are deleting this reloc entry, we must fill in the
9686 value now. This can happen if we have a .word which is not
9687 resolved when it appears but is later defined. We also need
9688 to fill in the value if this is an embedded PIC switch table
9691 || (mips_pic
== EMBEDDED_PIC
&& SWITCH_TABLE (fixP
)))
9692 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
,
9697 /* If we are deleting this reloc entry, we must fill in the
9699 assert (fixP
->fx_size
== 2);
9701 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
,
9705 case BFD_RELOC_LO16
:
9706 /* When handling an embedded PIC switch statement, we can wind
9707 up deleting a LO16 reloc. See the 'o' case in mips_ip. */
9710 if (value
+ 0x8000 > 0xffff)
9711 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
9712 _("relocation overflow"));
9713 buf
= (unsigned char *) fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
9714 if (target_big_endian
)
9716 md_number_to_chars (buf
, value
, 2);
9720 case BFD_RELOC_16_PCREL_S2
:
9722 * We need to save the bits in the instruction since fixup_segment()
9723 * might be deleting the relocation entry (i.e., a branch within
9724 * the current segment).
9726 if ((value
& 0x3) != 0)
9727 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
9728 _("Branch to odd address (%lx)"), (long) value
);
9730 if (!fixP
->fx_done
&& value
!= 0)
9732 /* If 'value' is zero, the remaining reloc code won't actually
9733 do the store, so it must be done here. This is probably
9736 value
-= fixP
->fx_frag
->fr_address
+ fixP
->fx_where
;
9738 value
= (offsetT
) value
>> 2;
9740 /* update old instruction data */
9741 buf
= (unsigned char *) (fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
);
9742 if (target_big_endian
)
9743 insn
= (buf
[0] << 24) | (buf
[1] << 16) | (buf
[2] << 8) | buf
[3];
9745 insn
= (buf
[3] << 24) | (buf
[2] << 16) | (buf
[1] << 8) | buf
[0];
9747 if (value
+ 0x8000 <= 0xffff)
9748 insn
|= value
& 0xffff;
9751 /* The branch offset is too large. If this is an
9752 unconditional branch, and we are not generating PIC code,
9753 we can convert it to an absolute jump instruction. */
9754 if (mips_pic
== NO_PIC
9756 && fixP
->fx_frag
->fr_address
>= text_section
->vma
9757 && (fixP
->fx_frag
->fr_address
9758 < text_section
->vma
+ text_section
->_raw_size
)
9759 && ((insn
& 0xffff0000) == 0x10000000 /* beq $0,$0 */
9760 || (insn
& 0xffff0000) == 0x04010000 /* bgez $0 */
9761 || (insn
& 0xffff0000) == 0x04110000)) /* bgezal $0 */
9763 if ((insn
& 0xffff0000) == 0x04110000) /* bgezal $0 */
9764 insn
= 0x0c000000; /* jal */
9766 insn
= 0x08000000; /* j */
9767 fixP
->fx_r_type
= BFD_RELOC_MIPS_JMP
;
9769 fixP
->fx_addsy
= section_symbol (text_section
);
9770 fixP
->fx_addnumber
= (value
<< 2) + md_pcrel_from (fixP
);
9774 /* FIXME. It would be possible in principle to handle
9775 conditional branches which overflow. They could be
9776 transformed into a branch around a jump. This would
9777 require setting up variant frags for each different
9778 branch type. The native MIPS assembler attempts to
9779 handle these cases, but it appears to do it
9781 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
9782 _("Branch out of range"));
9786 md_number_to_chars ((char *) buf
, (valueT
) insn
, 4);
9789 case BFD_RELOC_VTABLE_INHERIT
:
9792 && !S_IS_DEFINED (fixP
->fx_addsy
)
9793 && !S_IS_WEAK (fixP
->fx_addsy
))
9794 S_SET_WEAK (fixP
->fx_addsy
);
9797 case BFD_RELOC_VTABLE_ENTRY
:
9813 const struct mips_opcode
*p
;
9814 int treg
, sreg
, dreg
, shamt
;
9819 for (i
= 0; i
< NUMOPCODES
; ++i
)
9821 p
= &mips_opcodes
[i
];
9822 if (((oc
& p
->mask
) == p
->match
) && (p
->pinfo
!= INSN_MACRO
))
9824 printf ("%08lx %s\t", oc
, p
->name
);
9825 treg
= (oc
>> 16) & 0x1f;
9826 sreg
= (oc
>> 21) & 0x1f;
9827 dreg
= (oc
>> 11) & 0x1f;
9828 shamt
= (oc
>> 6) & 0x1f;
9830 for (args
= p
->args
;; ++args
)
9841 printf ("%c", *args
);
9845 assert (treg
== sreg
);
9846 printf ("$%d,$%d", treg
, sreg
);
9851 printf ("$%d", dreg
);
9856 printf ("$%d", treg
);
9860 printf ("0x%x", treg
);
9865 printf ("$%d", sreg
);
9869 printf ("0x%08lx", oc
& 0x1ffffff);
9881 printf ("$%d", shamt
);
9892 printf (_("%08lx UNDEFINED\n"), oc
);
9903 name
= input_line_pointer
;
9904 c
= get_symbol_end ();
9905 p
= (symbolS
*) symbol_find_or_make (name
);
9906 *input_line_pointer
= c
;
9910 /* Align the current frag to a given power of two. The MIPS assembler
9911 also automatically adjusts any preceding label. */
9914 mips_align (to
, fill
, label
)
9919 mips_emit_delays (false);
9920 frag_align (to
, fill
, 0);
9921 record_alignment (now_seg
, to
);
9924 assert (S_GET_SEGMENT (label
) == now_seg
);
9925 symbol_set_frag (label
, frag_now
);
9926 S_SET_VALUE (label
, (valueT
) frag_now_fix ());
9930 /* Align to a given power of two. .align 0 turns off the automatic
9931 alignment used by the data creating pseudo-ops. */
9935 int x ATTRIBUTE_UNUSED
;
9938 register long temp_fill
;
9939 long max_alignment
= 15;
9943 o Note that the assembler pulls down any immediately preceeding label
9944 to the aligned address.
9945 o It's not documented but auto alignment is reinstated by
9946 a .align pseudo instruction.
9947 o Note also that after auto alignment is turned off the mips assembler
9948 issues an error on attempt to assemble an improperly aligned data item.
9953 temp
= get_absolute_expression ();
9954 if (temp
> max_alignment
)
9955 as_bad (_("Alignment too large: %d. assumed."), temp
= max_alignment
);
9958 as_warn (_("Alignment negative: 0 assumed."));
9961 if (*input_line_pointer
== ',')
9963 input_line_pointer
++;
9964 temp_fill
= get_absolute_expression ();
9971 mips_align (temp
, (int) temp_fill
,
9972 insn_labels
!= NULL
? insn_labels
->label
: NULL
);
9979 demand_empty_rest_of_line ();
9983 mips_flush_pending_output ()
9985 mips_emit_delays (false);
9986 mips_clear_insn_labels ();
9995 /* When generating embedded PIC code, we only use the .text, .lit8,
9996 .sdata and .sbss sections. We change the .data and .rdata
9997 pseudo-ops to use .sdata. */
9998 if (mips_pic
== EMBEDDED_PIC
9999 && (sec
== 'd' || sec
== 'r'))
10003 /* The ELF backend needs to know that we are changing sections, so
10004 that .previous works correctly. We could do something like check
10005 for a obj_section_change_hook macro, but that might be confusing
10006 as it would not be appropriate to use it in the section changing
10007 functions in read.c, since obj-elf.c intercepts those. FIXME:
10008 This should be cleaner, somehow. */
10009 obj_elf_section_change_hook ();
10012 mips_emit_delays (false);
10022 subseg_set (bss_section
, (subsegT
) get_absolute_expression ());
10023 demand_empty_rest_of_line ();
10027 if (USE_GLOBAL_POINTER_OPT
)
10029 seg
= subseg_new (RDATA_SECTION_NAME
,
10030 (subsegT
) get_absolute_expression ());
10031 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
10033 bfd_set_section_flags (stdoutput
, seg
,
10039 if (strcmp (TARGET_OS
, "elf") != 0)
10040 record_alignment (seg
, 4);
10042 demand_empty_rest_of_line ();
10046 as_bad (_("No read only data section in this object file format"));
10047 demand_empty_rest_of_line ();
10053 if (USE_GLOBAL_POINTER_OPT
)
10055 seg
= subseg_new (".sdata", (subsegT
) get_absolute_expression ());
10056 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
10058 bfd_set_section_flags (stdoutput
, seg
,
10059 SEC_ALLOC
| SEC_LOAD
| SEC_RELOC
10061 if (strcmp (TARGET_OS
, "elf") != 0)
10062 record_alignment (seg
, 4);
10064 demand_empty_rest_of_line ();
10069 as_bad (_("Global pointers not supported; recompile -G 0"));
10070 demand_empty_rest_of_line ();
10079 mips_enable_auto_align ()
10090 label
= insn_labels
!= NULL
? insn_labels
->label
: NULL
;
10091 mips_emit_delays (false);
10092 if (log_size
> 0 && auto_align
)
10093 mips_align (log_size
, 0, label
);
10094 mips_clear_insn_labels ();
10095 cons (1 << log_size
);
10099 s_float_cons (type
)
10104 label
= insn_labels
!= NULL
? insn_labels
->label
: NULL
;
10106 mips_emit_delays (false);
10111 mips_align (3, 0, label
);
10113 mips_align (2, 0, label
);
10116 mips_clear_insn_labels ();
10121 /* Handle .globl. We need to override it because on Irix 5 you are
10124 where foo is an undefined symbol, to mean that foo should be
10125 considered to be the address of a function. */
10129 int x ATTRIBUTE_UNUSED
;
10136 name
= input_line_pointer
;
10137 c
= get_symbol_end ();
10138 symbolP
= symbol_find_or_make (name
);
10139 *input_line_pointer
= c
;
10140 SKIP_WHITESPACE ();
10142 /* On Irix 5, every global symbol that is not explicitly labelled as
10143 being a function is apparently labelled as being an object. */
10146 if (! is_end_of_line
[(unsigned char) *input_line_pointer
])
10151 secname
= input_line_pointer
;
10152 c
= get_symbol_end ();
10153 sec
= bfd_get_section_by_name (stdoutput
, secname
);
10155 as_bad (_("%s: no such section"), secname
);
10156 *input_line_pointer
= c
;
10158 if (sec
!= NULL
&& (sec
->flags
& SEC_CODE
) != 0)
10159 flag
= BSF_FUNCTION
;
10162 symbol_get_bfdsym (symbolP
)->flags
|= flag
;
10164 S_SET_EXTERNAL (symbolP
);
10165 demand_empty_rest_of_line ();
10170 int x ATTRIBUTE_UNUSED
;
10175 opt
= input_line_pointer
;
10176 c
= get_symbol_end ();
10180 /* FIXME: What does this mean? */
10182 else if (strncmp (opt
, "pic", 3) == 0)
10186 i
= atoi (opt
+ 3);
10190 mips_pic
= SVR4_PIC
;
10192 as_bad (_(".option pic%d not supported"), i
);
10194 if (USE_GLOBAL_POINTER_OPT
&& mips_pic
== SVR4_PIC
)
10196 if (g_switch_seen
&& g_switch_value
!= 0)
10197 as_warn (_("-G may not be used with SVR4 PIC code"));
10198 g_switch_value
= 0;
10199 bfd_set_gp_size (stdoutput
, 0);
10203 as_warn (_("Unrecognized option \"%s\""), opt
);
10205 *input_line_pointer
= c
;
10206 demand_empty_rest_of_line ();
10209 /* This structure is used to hold a stack of .set values. */
10211 struct mips_option_stack
10213 struct mips_option_stack
*next
;
10214 struct mips_set_options options
;
10217 static struct mips_option_stack
*mips_opts_stack
;
10219 /* Handle the .set pseudo-op. */
10223 int x ATTRIBUTE_UNUSED
;
10225 char *name
= input_line_pointer
, ch
;
10227 while (!is_end_of_line
[(unsigned char) *input_line_pointer
])
10228 input_line_pointer
++;
10229 ch
= *input_line_pointer
;
10230 *input_line_pointer
= '\0';
10232 if (strcmp (name
, "reorder") == 0)
10234 if (mips_opts
.noreorder
&& prev_nop_frag
!= NULL
)
10236 /* If we still have pending nops, we can discard them. The
10237 usual nop handling will insert any that are still
10239 prev_nop_frag
->fr_fix
-= (prev_nop_frag_holds
10240 * (mips_opts
.mips16
? 2 : 4));
10241 prev_nop_frag
= NULL
;
10243 mips_opts
.noreorder
= 0;
10245 else if (strcmp (name
, "noreorder") == 0)
10247 mips_emit_delays (true);
10248 mips_opts
.noreorder
= 1;
10249 mips_any_noreorder
= 1;
10251 else if (strcmp (name
, "at") == 0)
10253 mips_opts
.noat
= 0;
10255 else if (strcmp (name
, "noat") == 0)
10257 mips_opts
.noat
= 1;
10259 else if (strcmp (name
, "macro") == 0)
10261 mips_opts
.warn_about_macros
= 0;
10263 else if (strcmp (name
, "nomacro") == 0)
10265 if (mips_opts
.noreorder
== 0)
10266 as_bad (_("`noreorder' must be set before `nomacro'"));
10267 mips_opts
.warn_about_macros
= 1;
10269 else if (strcmp (name
, "move") == 0 || strcmp (name
, "novolatile") == 0)
10271 mips_opts
.nomove
= 0;
10273 else if (strcmp (name
, "nomove") == 0 || strcmp (name
, "volatile") == 0)
10275 mips_opts
.nomove
= 1;
10277 else if (strcmp (name
, "bopt") == 0)
10279 mips_opts
.nobopt
= 0;
10281 else if (strcmp (name
, "nobopt") == 0)
10283 mips_opts
.nobopt
= 1;
10285 else if (strcmp (name
, "mips16") == 0
10286 || strcmp (name
, "MIPS-16") == 0)
10287 mips_opts
.mips16
= 1;
10288 else if (strcmp (name
, "nomips16") == 0
10289 || strcmp (name
, "noMIPS-16") == 0)
10290 mips_opts
.mips16
= 0;
10291 else if (strncmp (name
, "mips", 4) == 0)
10295 /* Permit the user to change the ISA on the fly. Needless to
10296 say, misuse can cause serious problems. */
10297 isa
= atoi (name
+ 4);
10300 case 0: mips_opts
.isa
= file_mips_isa
; break;
10301 case 1: mips_opts
.isa
= ISA_MIPS1
; break;
10302 case 2: mips_opts
.isa
= ISA_MIPS2
; break;
10303 case 3: mips_opts
.isa
= ISA_MIPS3
; break;
10304 case 4: mips_opts
.isa
= ISA_MIPS4
; break;
10305 case 5: mips_opts
.isa
= ISA_MIPS5
; break;
10306 case 32: mips_opts
.isa
= ISA_MIPS32
; break;
10307 case 64: mips_opts
.isa
= ISA_MIPS64
; break;
10308 default: as_bad (_("unknown ISA level")); break;
10311 else if (strcmp (name
, "autoextend") == 0)
10312 mips_opts
.noautoextend
= 0;
10313 else if (strcmp (name
, "noautoextend") == 0)
10314 mips_opts
.noautoextend
= 1;
10315 else if (strcmp (name
, "push") == 0)
10317 struct mips_option_stack
*s
;
10319 s
= (struct mips_option_stack
*) xmalloc (sizeof *s
);
10320 s
->next
= mips_opts_stack
;
10321 s
->options
= mips_opts
;
10322 mips_opts_stack
= s
;
10324 else if (strcmp (name
, "pop") == 0)
10326 struct mips_option_stack
*s
;
10328 s
= mips_opts_stack
;
10330 as_bad (_(".set pop with no .set push"));
10333 /* If we're changing the reorder mode we need to handle
10334 delay slots correctly. */
10335 if (s
->options
.noreorder
&& ! mips_opts
.noreorder
)
10336 mips_emit_delays (true);
10337 else if (! s
->options
.noreorder
&& mips_opts
.noreorder
)
10339 if (prev_nop_frag
!= NULL
)
10341 prev_nop_frag
->fr_fix
-= (prev_nop_frag_holds
10342 * (mips_opts
.mips16
? 2 : 4));
10343 prev_nop_frag
= NULL
;
10347 mips_opts
= s
->options
;
10348 mips_opts_stack
= s
->next
;
10354 as_warn (_("Tried to set unrecognized symbol: %s\n"), name
);
10356 *input_line_pointer
= ch
;
10357 demand_empty_rest_of_line ();
10360 /* Handle the .abicalls pseudo-op. I believe this is equivalent to
10361 .option pic2. It means to generate SVR4 PIC calls. */
10364 s_abicalls (ignore
)
10365 int ignore ATTRIBUTE_UNUSED
;
10367 mips_pic
= SVR4_PIC
;
10368 if (USE_GLOBAL_POINTER_OPT
)
10370 if (g_switch_seen
&& g_switch_value
!= 0)
10371 as_warn (_("-G may not be used with SVR4 PIC code"));
10372 g_switch_value
= 0;
10374 bfd_set_gp_size (stdoutput
, 0);
10375 demand_empty_rest_of_line ();
10378 /* Handle the .cpload pseudo-op. This is used when generating SVR4
10379 PIC code. It sets the $gp register for the function based on the
10380 function address, which is in the register named in the argument.
10381 This uses a relocation against _gp_disp, which is handled specially
10382 by the linker. The result is:
10383 lui $gp,%hi(_gp_disp)
10384 addiu $gp,$gp,%lo(_gp_disp)
10385 addu $gp,$gp,.cpload argument
10386 The .cpload argument is normally $25 == $t9. */
10390 int ignore ATTRIBUTE_UNUSED
;
10395 /* If we are not generating SVR4 PIC code, .cpload is ignored. */
10396 if (mips_pic
!= SVR4_PIC
)
10402 /* .cpload should be a in .set noreorder section. */
10403 if (mips_opts
.noreorder
== 0)
10404 as_warn (_(".cpload not in noreorder section"));
10406 ex
.X_op
= O_symbol
;
10407 ex
.X_add_symbol
= symbol_find_or_make ("_gp_disp");
10408 ex
.X_op_symbol
= NULL
;
10409 ex
.X_add_number
= 0;
10411 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
10412 symbol_get_bfdsym (ex
.X_add_symbol
)->flags
|= BSF_OBJECT
;
10414 macro_build_lui ((char *) NULL
, &icnt
, &ex
, GP
);
10415 macro_build ((char *) NULL
, &icnt
, &ex
, "addiu", "t,r,j", GP
, GP
,
10416 (int) BFD_RELOC_LO16
);
10418 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "addu", "d,v,t",
10419 GP
, GP
, tc_get_register (0));
10421 demand_empty_rest_of_line ();
10424 /* Handle the .cprestore pseudo-op. This stores $gp into a given
10425 offset from $sp. The offset is remembered, and after making a PIC
10426 call $gp is restored from that location. */
10429 s_cprestore (ignore
)
10430 int ignore ATTRIBUTE_UNUSED
;
10435 /* If we are not generating SVR4 PIC code, .cprestore is ignored. */
10436 if (mips_pic
!= SVR4_PIC
)
10442 mips_cprestore_offset
= get_absolute_expression ();
10444 ex
.X_op
= O_constant
;
10445 ex
.X_add_symbol
= NULL
;
10446 ex
.X_op_symbol
= NULL
;
10447 ex
.X_add_number
= mips_cprestore_offset
;
10449 macro_build ((char *) NULL
, &icnt
, &ex
,
10450 HAVE_32BIT_ADDRESSES
? "sw" : "sd",
10451 "t,o(b)", GP
, (int) BFD_RELOC_LO16
, SP
);
10453 demand_empty_rest_of_line ();
10456 /* Handle the .gpword pseudo-op. This is used when generating PIC
10457 code. It generates a 32 bit GP relative reloc. */
10461 int ignore ATTRIBUTE_UNUSED
;
10467 /* When not generating PIC code, this is treated as .word. */
10468 if (mips_pic
!= SVR4_PIC
)
10474 label
= insn_labels
!= NULL
? insn_labels
->label
: NULL
;
10475 mips_emit_delays (true);
10477 mips_align (2, 0, label
);
10478 mips_clear_insn_labels ();
10482 if (ex
.X_op
!= O_symbol
|| ex
.X_add_number
!= 0)
10484 as_bad (_("Unsupported use of .gpword"));
10485 ignore_rest_of_line ();
10489 md_number_to_chars (p
, (valueT
) 0, 4);
10490 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 4, &ex
, 0,
10491 BFD_RELOC_MIPS_GPREL32
);
10493 demand_empty_rest_of_line ();
10496 /* Handle the .cpadd pseudo-op. This is used when dealing with switch
10497 tables in SVR4 PIC code. */
10501 int ignore ATTRIBUTE_UNUSED
;
10506 /* This is ignored when not generating SVR4 PIC code. */
10507 if (mips_pic
!= SVR4_PIC
)
10513 /* Add $gp to the register named as an argument. */
10514 reg
= tc_get_register (0);
10515 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
10516 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
10517 "d,v,t", reg
, reg
, GP
);
10519 demand_empty_rest_of_line ();
10522 /* Handle the .insn pseudo-op. This marks instruction labels in
10523 mips16 mode. This permits the linker to handle them specially,
10524 such as generating jalx instructions when needed. We also make
10525 them odd for the duration of the assembly, in order to generate the
10526 right sort of code. We will make them even in the adjust_symtab
10527 routine, while leaving them marked. This is convenient for the
10528 debugger and the disassembler. The linker knows to make them odd
10533 int ignore ATTRIBUTE_UNUSED
;
10535 if (mips_opts
.mips16
)
10536 mips16_mark_labels ();
10538 demand_empty_rest_of_line ();
10541 /* Handle a .stabn directive. We need these in order to mark a label
10542 as being a mips16 text label correctly. Sometimes the compiler
10543 will emit a label, followed by a .stabn, and then switch sections.
10544 If the label and .stabn are in mips16 mode, then the label is
10545 really a mips16 text label. */
10551 if (type
== 'n' && mips_opts
.mips16
)
10552 mips16_mark_labels ();
10557 /* Handle the .weakext pseudo-op as defined in Kane and Heinrich.
10561 s_mips_weakext (ignore
)
10562 int ignore ATTRIBUTE_UNUSED
;
10569 name
= input_line_pointer
;
10570 c
= get_symbol_end ();
10571 symbolP
= symbol_find_or_make (name
);
10572 S_SET_WEAK (symbolP
);
10573 *input_line_pointer
= c
;
10575 SKIP_WHITESPACE ();
10577 if (! is_end_of_line
[(unsigned char) *input_line_pointer
])
10579 if (S_IS_DEFINED (symbolP
))
10581 as_bad ("Ignoring attempt to redefine symbol `%s'.",
10582 S_GET_NAME (symbolP
));
10583 ignore_rest_of_line ();
10587 if (*input_line_pointer
== ',')
10589 ++input_line_pointer
;
10590 SKIP_WHITESPACE ();
10594 if (exp
.X_op
!= O_symbol
)
10596 as_bad ("bad .weakext directive");
10597 ignore_rest_of_line();
10600 symbol_set_value_expression (symbolP
, &exp
);
10603 demand_empty_rest_of_line ();
10606 /* Parse a register string into a number. Called from the ECOFF code
10607 to parse .frame. The argument is non-zero if this is the frame
10608 register, so that we can record it in mips_frame_reg. */
10611 tc_get_register (frame
)
10616 SKIP_WHITESPACE ();
10617 if (*input_line_pointer
++ != '$')
10619 as_warn (_("expected `$'"));
10622 else if (isdigit ((unsigned char) *input_line_pointer
))
10624 reg
= get_absolute_expression ();
10625 if (reg
< 0 || reg
>= 32)
10627 as_warn (_("Bad register number"));
10633 if (strncmp (input_line_pointer
, "fp", 2) == 0)
10635 else if (strncmp (input_line_pointer
, "sp", 2) == 0)
10637 else if (strncmp (input_line_pointer
, "gp", 2) == 0)
10639 else if (strncmp (input_line_pointer
, "at", 2) == 0)
10643 as_warn (_("Unrecognized register name"));
10646 input_line_pointer
+= 2;
10649 mips_frame_reg
= reg
!= 0 ? reg
: SP
;
10654 md_section_align (seg
, addr
)
10658 int align
= bfd_get_section_alignment (stdoutput
, seg
);
10661 /* We don't need to align ELF sections to the full alignment.
10662 However, Irix 5 may prefer that we align them at least to a 16
10663 byte boundary. We don't bother to align the sections if we are
10664 targeted for an embedded system. */
10665 if (strcmp (TARGET_OS
, "elf") == 0)
10671 return ((addr
+ (1 << align
) - 1) & (-1 << align
));
10674 /* Utility routine, called from above as well. If called while the
10675 input file is still being read, it's only an approximation. (For
10676 example, a symbol may later become defined which appeared to be
10677 undefined earlier.) */
10680 nopic_need_relax (sym
, before_relaxing
)
10682 int before_relaxing
;
10687 if (USE_GLOBAL_POINTER_OPT
)
10689 const char *symname
;
10692 /* Find out whether this symbol can be referenced off the GP
10693 register. It can be if it is smaller than the -G size or if
10694 it is in the .sdata or .sbss section. Certain symbols can
10695 not be referenced off the GP, although it appears as though
10697 symname
= S_GET_NAME (sym
);
10698 if (symname
!= (const char *) NULL
10699 && (strcmp (symname
, "eprol") == 0
10700 || strcmp (symname
, "etext") == 0
10701 || strcmp (symname
, "_gp") == 0
10702 || strcmp (symname
, "edata") == 0
10703 || strcmp (symname
, "_fbss") == 0
10704 || strcmp (symname
, "_fdata") == 0
10705 || strcmp (symname
, "_ftext") == 0
10706 || strcmp (symname
, "end") == 0
10707 || strcmp (symname
, "_gp_disp") == 0))
10709 else if ((! S_IS_DEFINED (sym
) || S_IS_COMMON (sym
))
10711 #ifndef NO_ECOFF_DEBUGGING
10712 || (symbol_get_obj (sym
)->ecoff_extern_size
!= 0
10713 && (symbol_get_obj (sym
)->ecoff_extern_size
10714 <= g_switch_value
))
10716 /* We must defer this decision until after the whole
10717 file has been read, since there might be a .extern
10718 after the first use of this symbol. */
10719 || (before_relaxing
10720 #ifndef NO_ECOFF_DEBUGGING
10721 && symbol_get_obj (sym
)->ecoff_extern_size
== 0
10723 && S_GET_VALUE (sym
) == 0)
10724 || (S_GET_VALUE (sym
) != 0
10725 && S_GET_VALUE (sym
) <= g_switch_value
)))
10729 const char *segname
;
10731 segname
= segment_name (S_GET_SEGMENT (sym
));
10732 assert (strcmp (segname
, ".lit8") != 0
10733 && strcmp (segname
, ".lit4") != 0);
10734 change
= (strcmp (segname
, ".sdata") != 0
10735 && strcmp (segname
, ".sbss") != 0
10736 && strncmp (segname
, ".sdata.", 7) != 0
10737 && strncmp (segname
, ".gnu.linkonce.s.", 16) != 0);
10742 /* We are not optimizing for the GP register. */
10746 /* Given a mips16 variant frag FRAGP, return non-zero if it needs an
10747 extended opcode. SEC is the section the frag is in. */
10750 mips16_extended_frag (fragp
, sec
, stretch
)
10756 register const struct mips16_immed_operand
*op
;
10758 int mintiny
, maxtiny
;
10762 if (RELAX_MIPS16_USER_SMALL (fragp
->fr_subtype
))
10764 if (RELAX_MIPS16_USER_EXT (fragp
->fr_subtype
))
10767 type
= RELAX_MIPS16_TYPE (fragp
->fr_subtype
);
10768 op
= mips16_immed_operands
;
10769 while (op
->type
!= type
)
10772 assert (op
< mips16_immed_operands
+ MIPS16_NUM_IMMED
);
10777 if (type
== '<' || type
== '>' || type
== '[' || type
== ']')
10780 maxtiny
= 1 << op
->nbits
;
10785 maxtiny
= (1 << op
->nbits
) - 1;
10790 mintiny
= - (1 << (op
->nbits
- 1));
10791 maxtiny
= (1 << (op
->nbits
- 1)) - 1;
10794 sym_frag
= symbol_get_frag (fragp
->fr_symbol
);
10795 val
= S_GET_VALUE (fragp
->fr_symbol
);
10796 symsec
= S_GET_SEGMENT (fragp
->fr_symbol
);
10802 /* We won't have the section when we are called from
10803 mips_relax_frag. However, we will always have been called
10804 from md_estimate_size_before_relax first. If this is a
10805 branch to a different section, we mark it as such. If SEC is
10806 NULL, and the frag is not marked, then it must be a branch to
10807 the same section. */
10810 if (RELAX_MIPS16_LONG_BRANCH (fragp
->fr_subtype
))
10815 /* Must have been called from md_estimate_size_before_relax. */
10818 fragp
->fr_subtype
=
10819 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
10821 /* FIXME: We should support this, and let the linker
10822 catch branches and loads that are out of range. */
10823 as_bad_where (fragp
->fr_file
, fragp
->fr_line
,
10824 _("unsupported PC relative reference to different section"));
10828 if (fragp
!= sym_frag
&& sym_frag
->fr_address
== 0)
10829 /* Assume non-extended on the first relaxation pass.
10830 The address we have calculated will be bogus if this is
10831 a forward branch to another frag, as the forward frag
10832 will have fr_address == 0. */
10836 /* In this case, we know for sure that the symbol fragment is in
10837 the same section. If the relax_marker of the symbol fragment
10838 differs from the relax_marker of this fragment, we have not
10839 yet adjusted the symbol fragment fr_address. We want to add
10840 in STRETCH in order to get a better estimate of the address.
10841 This particularly matters because of the shift bits. */
10843 && sym_frag
->relax_marker
!= fragp
->relax_marker
)
10847 /* Adjust stretch for any alignment frag. Note that if have
10848 been expanding the earlier code, the symbol may be
10849 defined in what appears to be an earlier frag. FIXME:
10850 This doesn't handle the fr_subtype field, which specifies
10851 a maximum number of bytes to skip when doing an
10853 for (f
= fragp
; f
!= NULL
&& f
!= sym_frag
; f
= f
->fr_next
)
10855 if (f
->fr_type
== rs_align
|| f
->fr_type
== rs_align_code
)
10858 stretch
= - ((- stretch
)
10859 & ~ ((1 << (int) f
->fr_offset
) - 1));
10861 stretch
&= ~ ((1 << (int) f
->fr_offset
) - 1);
10870 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
10872 /* The base address rules are complicated. The base address of
10873 a branch is the following instruction. The base address of a
10874 PC relative load or add is the instruction itself, but if it
10875 is in a delay slot (in which case it can not be extended) use
10876 the address of the instruction whose delay slot it is in. */
10877 if (type
== 'p' || type
== 'q')
10881 /* If we are currently assuming that this frag should be
10882 extended, then, the current address is two bytes
10884 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
10887 /* Ignore the low bit in the target, since it will be set
10888 for a text label. */
10889 if ((val
& 1) != 0)
10892 else if (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
))
10894 else if (RELAX_MIPS16_DSLOT (fragp
->fr_subtype
))
10897 val
-= addr
& ~ ((1 << op
->shift
) - 1);
10899 /* Branch offsets have an implicit 0 in the lowest bit. */
10900 if (type
== 'p' || type
== 'q')
10903 /* If any of the shifted bits are set, we must use an extended
10904 opcode. If the address depends on the size of this
10905 instruction, this can lead to a loop, so we arrange to always
10906 use an extended opcode. We only check this when we are in
10907 the main relaxation loop, when SEC is NULL. */
10908 if ((val
& ((1 << op
->shift
) - 1)) != 0 && sec
== NULL
)
10910 fragp
->fr_subtype
=
10911 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
10915 /* If we are about to mark a frag as extended because the value
10916 is precisely maxtiny + 1, then there is a chance of an
10917 infinite loop as in the following code:
10922 In this case when the la is extended, foo is 0x3fc bytes
10923 away, so the la can be shrunk, but then foo is 0x400 away, so
10924 the la must be extended. To avoid this loop, we mark the
10925 frag as extended if it was small, and is about to become
10926 extended with a value of maxtiny + 1. */
10927 if (val
== ((maxtiny
+ 1) << op
->shift
)
10928 && ! RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
)
10931 fragp
->fr_subtype
=
10932 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
10936 else if (symsec
!= absolute_section
&& sec
!= NULL
)
10937 as_bad_where (fragp
->fr_file
, fragp
->fr_line
, _("unsupported relocation"));
10939 if ((val
& ((1 << op
->shift
) - 1)) != 0
10940 || val
< (mintiny
<< op
->shift
)
10941 || val
> (maxtiny
<< op
->shift
))
10947 /* Estimate the size of a frag before relaxing. Unless this is the
10948 mips16, we are not really relaxing here, and the final size is
10949 encoded in the subtype information. For the mips16, we have to
10950 decide whether we are using an extended opcode or not. */
10953 md_estimate_size_before_relax (fragp
, segtype
)
10958 boolean linkonce
= false;
10960 if (RELAX_MIPS16_P (fragp
->fr_subtype
))
10962 if (mips16_extended_frag (fragp
, segtype
, 0))
10964 fragp
->fr_subtype
= RELAX_MIPS16_MARK_EXTENDED (fragp
->fr_subtype
);
10969 fragp
->fr_subtype
= RELAX_MIPS16_CLEAR_EXTENDED (fragp
->fr_subtype
);
10974 if (mips_pic
== NO_PIC
)
10976 change
= nopic_need_relax (fragp
->fr_symbol
, 0);
10978 else if (mips_pic
== SVR4_PIC
)
10983 sym
= fragp
->fr_symbol
;
10985 /* Handle the case of a symbol equated to another symbol. */
10986 while (symbol_equated_p (sym
)
10987 && (! S_IS_DEFINED (sym
) || S_IS_COMMON (sym
)))
10991 /* It's possible to get a loop here in a badly written
10993 n
= symbol_get_value_expression (sym
)->X_add_symbol
;
10999 symsec
= S_GET_SEGMENT (sym
);
11001 /* duplicate the test for LINK_ONCE sections as in adjust_reloc_syms */
11002 if (symsec
!= segtype
&& ! S_IS_LOCAL (sym
))
11004 if ((bfd_get_section_flags (stdoutput
, symsec
) & SEC_LINK_ONCE
)
11008 /* The GNU toolchain uses an extension for ELF: a section
11009 beginning with the magic string .gnu.linkonce is a linkonce
11011 if (strncmp (segment_name (symsec
), ".gnu.linkonce",
11012 sizeof ".gnu.linkonce" - 1) == 0)
11016 /* This must duplicate the test in adjust_reloc_syms. */
11017 change
= (symsec
!= &bfd_und_section
11018 && symsec
!= &bfd_abs_section
11019 && ! bfd_is_com_section (symsec
)
11022 /* A global or weak symbol is treated as external. */
11023 && (OUTPUT_FLAVOR
== bfd_target_elf_flavour
11024 && ! (S_IS_EXTERN (sym
) || S_IS_WEAK (sym
)))
11033 /* Record the offset to the first reloc in the fr_opcode field.
11034 This lets md_convert_frag and tc_gen_reloc know that the code
11035 must be expanded. */
11036 fragp
->fr_opcode
= (fragp
->fr_literal
11038 - RELAX_OLD (fragp
->fr_subtype
)
11039 + RELAX_RELOC1 (fragp
->fr_subtype
));
11040 /* FIXME: This really needs as_warn_where. */
11041 if (RELAX_WARN (fragp
->fr_subtype
))
11042 as_warn (_("AT used after \".set noat\" or macro used after "
11043 "\".set nomacro\""));
11045 return RELAX_NEW (fragp
->fr_subtype
) - RELAX_OLD (fragp
->fr_subtype
);
11051 /* This is called to see whether a reloc against a defined symbol
11052 should be converted into a reloc against a section. Don't adjust
11053 MIPS16 jump relocations, so we don't have to worry about the format
11054 of the offset in the .o file. Don't adjust relocations against
11055 mips16 symbols, so that the linker can find them if it needs to set
11059 mips_fix_adjustable (fixp
)
11063 /* Prevent all adjustments to global symbols. */
11064 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
11065 && (S_IS_EXTERN (fixp
->fx_addsy
) || S_IS_WEAK (fixp
->fx_addsy
)))
11068 if (fixp
->fx_r_type
== BFD_RELOC_MIPS16_JMP
)
11070 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
11071 || fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
11073 if (fixp
->fx_addsy
== NULL
)
11076 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
11077 && S_GET_OTHER (fixp
->fx_addsy
) == STO_MIPS16
11078 && fixp
->fx_subsy
== NULL
)
11084 /* Translate internal representation of relocation info to BFD target
11088 tc_gen_reloc (section
, fixp
)
11089 asection
*section ATTRIBUTE_UNUSED
;
11092 static arelent
*retval
[4];
11094 bfd_reloc_code_real_type code
;
11096 reloc
= retval
[0] = (arelent
*) xmalloc (sizeof (arelent
));
11099 reloc
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
11100 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
11101 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
11103 if (mips_pic
== EMBEDDED_PIC
11104 && SWITCH_TABLE (fixp
))
11106 /* For a switch table entry we use a special reloc. The addend
11107 is actually the difference between the reloc address and the
11109 reloc
->addend
= reloc
->address
- S_GET_VALUE (fixp
->fx_subsy
);
11110 if (OUTPUT_FLAVOR
!= bfd_target_ecoff_flavour
)
11111 as_fatal (_("Double check fx_r_type in tc-mips.c:tc_gen_reloc"));
11112 fixp
->fx_r_type
= BFD_RELOC_GPREL32
;
11114 else if (fixp
->fx_pcrel
== 0 || OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
11115 reloc
->addend
= fixp
->fx_addnumber
;
11116 else if (fixp
->fx_r_type
== BFD_RELOC_PCREL_LO16
)
11118 /* We use a special addend for an internal RELLO reloc. */
11119 if (symbol_section_p (fixp
->fx_addsy
))
11120 reloc
->addend
= reloc
->address
- S_GET_VALUE (fixp
->fx_subsy
);
11122 reloc
->addend
= fixp
->fx_addnumber
+ reloc
->address
;
11124 else if (fixp
->fx_r_type
== BFD_RELOC_PCREL_HI16_S
)
11126 assert (fixp
->fx_next
!= NULL
11127 && fixp
->fx_next
->fx_r_type
== BFD_RELOC_PCREL_LO16
);
11128 /* We use a special addend for an internal RELHI reloc. The
11129 reloc is relative to the RELLO; adjust the addend
11131 if (symbol_section_p (fixp
->fx_addsy
))
11132 reloc
->addend
= (fixp
->fx_next
->fx_frag
->fr_address
11133 + fixp
->fx_next
->fx_where
11134 - S_GET_VALUE (fixp
->fx_subsy
));
11136 reloc
->addend
= (fixp
->fx_addnumber
11137 + fixp
->fx_next
->fx_frag
->fr_address
11138 + fixp
->fx_next
->fx_where
);
11142 if (OUTPUT_FLAVOR
!= bfd_target_aout_flavour
)
11143 /* A gruesome hack which is a result of the gruesome gas reloc
11145 reloc
->addend
= reloc
->address
;
11147 reloc
->addend
= -reloc
->address
;
11150 /* If this is a variant frag, we may need to adjust the existing
11151 reloc and generate a new one. */
11152 if (fixp
->fx_frag
->fr_opcode
!= NULL
11153 && (fixp
->fx_r_type
== BFD_RELOC_MIPS_GPREL
11154 || fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT16
11155 || fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL16
11156 || fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT_HI16
11157 || fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT_LO16
11158 || fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL_HI16
11159 || fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL_LO16
))
11163 assert (! RELAX_MIPS16_P (fixp
->fx_frag
->fr_subtype
));
11165 /* If this is not the last reloc in this frag, then we have two
11166 GPREL relocs, or a GOT_HI16/GOT_LO16 pair, or a
11167 CALL_HI16/CALL_LO16, both of which are being replaced. Let
11168 the second one handle all of them. */
11169 if (fixp
->fx_next
!= NULL
11170 && fixp
->fx_frag
== fixp
->fx_next
->fx_frag
)
11172 assert ((fixp
->fx_r_type
== BFD_RELOC_MIPS_GPREL
11173 && fixp
->fx_next
->fx_r_type
== BFD_RELOC_MIPS_GPREL
)
11174 || (fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT_HI16
11175 && (fixp
->fx_next
->fx_r_type
11176 == BFD_RELOC_MIPS_GOT_LO16
))
11177 || (fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL_HI16
11178 && (fixp
->fx_next
->fx_r_type
11179 == BFD_RELOC_MIPS_CALL_LO16
)));
11184 fixp
->fx_where
= fixp
->fx_frag
->fr_opcode
- fixp
->fx_frag
->fr_literal
;
11185 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
11186 reloc2
= retval
[1] = (arelent
*) xmalloc (sizeof (arelent
));
11188 reloc2
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
11189 *reloc2
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
11190 reloc2
->address
= (reloc
->address
11191 + (RELAX_RELOC2 (fixp
->fx_frag
->fr_subtype
)
11192 - RELAX_RELOC1 (fixp
->fx_frag
->fr_subtype
)));
11193 reloc2
->addend
= fixp
->fx_addnumber
;
11194 reloc2
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_LO16
);
11195 assert (reloc2
->howto
!= NULL
);
11197 if (RELAX_RELOC3 (fixp
->fx_frag
->fr_subtype
))
11201 reloc3
= retval
[2] = (arelent
*) xmalloc (sizeof (arelent
));
11204 reloc3
->address
+= 4;
11207 if (mips_pic
== NO_PIC
)
11209 assert (fixp
->fx_r_type
== BFD_RELOC_MIPS_GPREL
);
11210 fixp
->fx_r_type
= BFD_RELOC_HI16_S
;
11212 else if (mips_pic
== SVR4_PIC
)
11214 switch (fixp
->fx_r_type
)
11218 case BFD_RELOC_MIPS_GOT16
:
11220 case BFD_RELOC_MIPS_CALL16
:
11221 case BFD_RELOC_MIPS_GOT_LO16
:
11222 case BFD_RELOC_MIPS_CALL_LO16
:
11223 fixp
->fx_r_type
= BFD_RELOC_MIPS_GOT16
;
11231 /* Since MIPS ELF uses Rel instead of Rela, encode the vtable entry
11232 to be used in the relocation's section offset. */
11233 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
11235 reloc
->address
= reloc
->addend
;
11239 /* Since DIFF_EXPR_OK is defined in tc-mips.h, it is possible that
11240 fixup_segment converted a non-PC relative reloc into a PC
11241 relative reloc. In such a case, we need to convert the reloc
11243 code
= fixp
->fx_r_type
;
11244 if (fixp
->fx_pcrel
)
11249 code
= BFD_RELOC_8_PCREL
;
11252 code
= BFD_RELOC_16_PCREL
;
11255 code
= BFD_RELOC_32_PCREL
;
11258 code
= BFD_RELOC_64_PCREL
;
11260 case BFD_RELOC_8_PCREL
:
11261 case BFD_RELOC_16_PCREL
:
11262 case BFD_RELOC_32_PCREL
:
11263 case BFD_RELOC_64_PCREL
:
11264 case BFD_RELOC_16_PCREL_S2
:
11265 case BFD_RELOC_PCREL_HI16_S
:
11266 case BFD_RELOC_PCREL_LO16
:
11269 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
11270 _("Cannot make %s relocation PC relative"),
11271 bfd_get_reloc_code_name (code
));
11275 /* To support a PC relative reloc when generating embedded PIC code
11276 for ECOFF, we use a Cygnus extension. We check for that here to
11277 make sure that we don't let such a reloc escape normally. */
11278 if ((OUTPUT_FLAVOR
== bfd_target_ecoff_flavour
11279 || OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
11280 && code
== BFD_RELOC_16_PCREL_S2
11281 && mips_pic
!= EMBEDDED_PIC
)
11282 reloc
->howto
= NULL
;
11284 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
11286 if (reloc
->howto
== NULL
)
11288 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
11289 _("Can not represent %s relocation in this object file format"),
11290 bfd_get_reloc_code_name (code
));
11297 /* Relax a machine dependent frag. This returns the amount by which
11298 the current size of the frag should change. */
11301 mips_relax_frag (fragp
, stretch
)
11305 if (! RELAX_MIPS16_P (fragp
->fr_subtype
))
11308 if (mips16_extended_frag (fragp
, (asection
*) NULL
, stretch
))
11310 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
11312 fragp
->fr_subtype
= RELAX_MIPS16_MARK_EXTENDED (fragp
->fr_subtype
);
11317 if (! RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
11319 fragp
->fr_subtype
= RELAX_MIPS16_CLEAR_EXTENDED (fragp
->fr_subtype
);
11326 /* Convert a machine dependent frag. */
11329 md_convert_frag (abfd
, asec
, fragp
)
11330 bfd
*abfd ATTRIBUTE_UNUSED
;
11337 if (RELAX_MIPS16_P (fragp
->fr_subtype
))
11340 register const struct mips16_immed_operand
*op
;
11341 boolean small
, ext
;
11344 unsigned long insn
;
11345 boolean use_extend
;
11346 unsigned short extend
;
11348 type
= RELAX_MIPS16_TYPE (fragp
->fr_subtype
);
11349 op
= mips16_immed_operands
;
11350 while (op
->type
!= type
)
11353 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
11364 resolve_symbol_value (fragp
->fr_symbol
);
11365 val
= S_GET_VALUE (fragp
->fr_symbol
);
11370 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
11372 /* The rules for the base address of a PC relative reloc are
11373 complicated; see mips16_extended_frag. */
11374 if (type
== 'p' || type
== 'q')
11379 /* Ignore the low bit in the target, since it will be
11380 set for a text label. */
11381 if ((val
& 1) != 0)
11384 else if (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
))
11386 else if (RELAX_MIPS16_DSLOT (fragp
->fr_subtype
))
11389 addr
&= ~ (addressT
) ((1 << op
->shift
) - 1);
11392 /* Make sure the section winds up with the alignment we have
11395 record_alignment (asec
, op
->shift
);
11399 && (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
)
11400 || RELAX_MIPS16_DSLOT (fragp
->fr_subtype
)))
11401 as_warn_where (fragp
->fr_file
, fragp
->fr_line
,
11402 _("extended instruction in delay slot"));
11404 buf
= (bfd_byte
*) (fragp
->fr_literal
+ fragp
->fr_fix
);
11406 if (target_big_endian
)
11407 insn
= bfd_getb16 (buf
);
11409 insn
= bfd_getl16 (buf
);
11411 mips16_immed (fragp
->fr_file
, fragp
->fr_line
, type
, val
,
11412 RELAX_MIPS16_USER_EXT (fragp
->fr_subtype
),
11413 small
, ext
, &insn
, &use_extend
, &extend
);
11417 md_number_to_chars (buf
, 0xf000 | extend
, 2);
11418 fragp
->fr_fix
+= 2;
11422 md_number_to_chars (buf
, insn
, 2);
11423 fragp
->fr_fix
+= 2;
11428 if (fragp
->fr_opcode
== NULL
)
11431 old
= RELAX_OLD (fragp
->fr_subtype
);
11432 new = RELAX_NEW (fragp
->fr_subtype
);
11433 fixptr
= fragp
->fr_literal
+ fragp
->fr_fix
;
11436 memcpy (fixptr
- old
, fixptr
, new);
11438 fragp
->fr_fix
+= new - old
;
11444 /* This function is called after the relocs have been generated.
11445 We've been storing mips16 text labels as odd. Here we convert them
11446 back to even for the convenience of the debugger. */
11449 mips_frob_file_after_relocs ()
11452 unsigned int count
, i
;
11454 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
11457 syms
= bfd_get_outsymbols (stdoutput
);
11458 count
= bfd_get_symcount (stdoutput
);
11459 for (i
= 0; i
< count
; i
++, syms
++)
11461 if (elf_symbol (*syms
)->internal_elf_sym
.st_other
== STO_MIPS16
11462 && ((*syms
)->value
& 1) != 0)
11464 (*syms
)->value
&= ~1;
11465 /* If the symbol has an odd size, it was probably computed
11466 incorrectly, so adjust that as well. */
11467 if ((elf_symbol (*syms
)->internal_elf_sym
.st_size
& 1) != 0)
11468 ++elf_symbol (*syms
)->internal_elf_sym
.st_size
;
11475 /* This function is called whenever a label is defined. It is used
11476 when handling branch delays; if a branch has a label, we assume we
11477 can not move it. */
11480 mips_define_label (sym
)
11483 struct insn_label_list
*l
;
11485 if (free_insn_labels
== NULL
)
11486 l
= (struct insn_label_list
*) xmalloc (sizeof *l
);
11489 l
= free_insn_labels
;
11490 free_insn_labels
= l
->next
;
11494 l
->next
= insn_labels
;
11498 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11500 /* Some special processing for a MIPS ELF file. */
11503 mips_elf_final_processing ()
11505 /* Write out the register information. */
11510 s
.ri_gprmask
= mips_gprmask
;
11511 s
.ri_cprmask
[0] = mips_cprmask
[0];
11512 s
.ri_cprmask
[1] = mips_cprmask
[1];
11513 s
.ri_cprmask
[2] = mips_cprmask
[2];
11514 s
.ri_cprmask
[3] = mips_cprmask
[3];
11515 /* The gp_value field is set by the MIPS ELF backend. */
11517 bfd_mips_elf32_swap_reginfo_out (stdoutput
, &s
,
11518 ((Elf32_External_RegInfo
*)
11519 mips_regmask_frag
));
11523 Elf64_Internal_RegInfo s
;
11525 s
.ri_gprmask
= mips_gprmask
;
11527 s
.ri_cprmask
[0] = mips_cprmask
[0];
11528 s
.ri_cprmask
[1] = mips_cprmask
[1];
11529 s
.ri_cprmask
[2] = mips_cprmask
[2];
11530 s
.ri_cprmask
[3] = mips_cprmask
[3];
11531 /* The gp_value field is set by the MIPS ELF backend. */
11533 bfd_mips_elf64_swap_reginfo_out (stdoutput
, &s
,
11534 ((Elf64_External_RegInfo
*)
11535 mips_regmask_frag
));
11538 /* Set the MIPS ELF flag bits. FIXME: There should probably be some
11539 sort of BFD interface for this. */
11540 if (mips_any_noreorder
)
11541 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_NOREORDER
;
11542 if (mips_pic
!= NO_PIC
)
11543 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_PIC
;
11545 /* Set the MIPS ELF ABI flags. */
11546 if (mips_abi_string
== NULL
)
11548 else if (strcmp (mips_abi_string
, "32") == 0)
11549 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_O32
;
11550 else if (strcmp (mips_abi_string
, "o64") == 0)
11551 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_O64
;
11552 else if (strcmp (mips_abi_string
, "eabi") == 0)
11555 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_EABI64
;
11557 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_EABI32
;
11559 else if (strcmp (mips_abi_string
, "n32") == 0)
11560 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ABI2
;
11562 /* Nothing to do for "64". */
11564 if (mips_32bitmode
)
11565 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_32BITMODE
;
11568 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */
11570 typedef struct proc
{
11572 unsigned long reg_mask
;
11573 unsigned long reg_offset
;
11574 unsigned long fpreg_mask
;
11575 unsigned long fpreg_offset
;
11576 unsigned long frame_offset
;
11577 unsigned long frame_reg
;
11578 unsigned long pc_reg
;
11581 static procS cur_proc
;
11582 static procS
*cur_proc_ptr
;
11583 static int numprocs
;
11585 /* Fill in an rs_align_code fragment. */
11588 mips_handle_align (fragp
)
11591 if (fragp
->fr_type
!= rs_align_code
)
11594 if (mips_opts
.mips16
)
11596 static const unsigned char be_nop
[] = { 0x65, 0x00 };
11597 static const unsigned char le_nop
[] = { 0x00, 0x65 };
11602 bytes
= fragp
->fr_next
->fr_address
- fragp
->fr_address
- fragp
->fr_fix
;
11603 p
= fragp
->fr_literal
+ fragp
->fr_fix
;
11608 fragp
->fr_fix
+= 1;
11611 memcpy (p
, (target_big_endian
? be_nop
: le_nop
), 2);
11615 /* For mips32, a nop is a zero, which we trivially get by doing nothing. */
11626 /* check for premature end, nesting errors, etc */
11628 as_warn (_("missing .end at end of assembly"));
11637 if (*input_line_pointer
== '-')
11639 ++input_line_pointer
;
11642 if (!isdigit ((unsigned char) *input_line_pointer
))
11643 as_bad (_("Expected simple number."));
11644 if (input_line_pointer
[0] == '0')
11646 if (input_line_pointer
[1] == 'x')
11648 input_line_pointer
+= 2;
11649 while (isxdigit ((unsigned char) *input_line_pointer
))
11652 val
|= hex_value (*input_line_pointer
++);
11654 return negative
? -val
: val
;
11658 ++input_line_pointer
;
11659 while (isdigit ((unsigned char) *input_line_pointer
))
11662 val
|= *input_line_pointer
++ - '0';
11664 return negative
? -val
: val
;
11667 if (!isdigit ((unsigned char) *input_line_pointer
))
11669 printf (_(" *input_line_pointer == '%c' 0x%02x\n"),
11670 *input_line_pointer
, *input_line_pointer
);
11671 as_warn (_("Invalid number"));
11674 while (isdigit ((unsigned char) *input_line_pointer
))
11677 val
+= *input_line_pointer
++ - '0';
11679 return negative
? -val
: val
;
11682 /* The .file directive; just like the usual .file directive, but there
11683 is an initial number which is the ECOFF file index. */
11687 int x ATTRIBUTE_UNUSED
;
11691 line
= get_number ();
11695 /* The .end directive. */
11699 int x ATTRIBUTE_UNUSED
;
11704 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
11707 demand_empty_rest_of_line ();
11712 #ifdef BFD_ASSEMBLER
11713 if ((bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) != 0)
11718 if (now_seg
!= data_section
&& now_seg
!= bss_section
)
11725 as_warn (_(".end not in text section"));
11729 as_warn (_(".end directive without a preceding .ent directive."));
11730 demand_empty_rest_of_line ();
11736 assert (S_GET_NAME (p
));
11737 if (strcmp (S_GET_NAME (p
), S_GET_NAME (cur_proc_ptr
->isym
)))
11738 as_warn (_(".end symbol does not match .ent symbol."));
11741 as_warn (_(".end directive missing or unknown symbol"));
11743 #ifdef MIPS_STABS_ELF
11745 segT saved_seg
= now_seg
;
11746 subsegT saved_subseg
= now_subseg
;
11751 dot
= frag_now_fix ();
11753 #ifdef md_flush_pending_output
11754 md_flush_pending_output ();
11758 subseg_set (pdr_seg
, 0);
11760 /* Write the symbol. */
11761 exp
.X_op
= O_symbol
;
11762 exp
.X_add_symbol
= p
;
11763 exp
.X_add_number
= 0;
11764 emit_expr (&exp
, 4);
11766 fragp
= frag_more (7 * 4);
11768 md_number_to_chars (fragp
, (valueT
) cur_proc_ptr
->reg_mask
, 4);
11769 md_number_to_chars (fragp
+ 4, (valueT
) cur_proc_ptr
->reg_offset
, 4);
11770 md_number_to_chars (fragp
+ 8, (valueT
) cur_proc_ptr
->fpreg_mask
, 4);
11771 md_number_to_chars (fragp
+ 12, (valueT
) cur_proc_ptr
->fpreg_offset
, 4);
11772 md_number_to_chars (fragp
+ 16, (valueT
) cur_proc_ptr
->frame_offset
, 4);
11773 md_number_to_chars (fragp
+ 20, (valueT
) cur_proc_ptr
->frame_reg
, 4);
11774 md_number_to_chars (fragp
+ 24, (valueT
) cur_proc_ptr
->pc_reg
, 4);
11776 subseg_set (saved_seg
, saved_subseg
);
11780 cur_proc_ptr
= NULL
;
11783 /* The .aent and .ent directives. */
11793 symbolP
= get_symbol ();
11794 if (*input_line_pointer
== ',')
11795 input_line_pointer
++;
11796 SKIP_WHITESPACE ();
11797 if (isdigit ((unsigned char) *input_line_pointer
)
11798 || *input_line_pointer
== '-')
11799 number
= get_number ();
11801 #ifdef BFD_ASSEMBLER
11802 if ((bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) != 0)
11807 if (now_seg
!= data_section
&& now_seg
!= bss_section
)
11814 as_warn (_(".ent or .aent not in text section."));
11816 if (!aent
&& cur_proc_ptr
)
11817 as_warn (_("missing .end"));
11821 cur_proc_ptr
= &cur_proc
;
11822 memset (cur_proc_ptr
, '\0', sizeof (procS
));
11824 cur_proc_ptr
->isym
= symbolP
;
11826 symbol_get_bfdsym (symbolP
)->flags
|= BSF_FUNCTION
;
11831 demand_empty_rest_of_line ();
11834 /* The .frame directive. If the mdebug section is present (IRIX 5 native)
11835 then ecoff.c (ecoff_directive_frame) is used. For embedded targets,
11836 s_mips_frame is used so that we can set the PDR information correctly.
11837 We can't use the ecoff routines because they make reference to the ecoff
11838 symbol table (in the mdebug section). */
11841 s_mips_frame (ignore
)
11842 int ignore ATTRIBUTE_UNUSED
;
11844 #ifdef MIPS_STABS_ELF
11848 if (cur_proc_ptr
== (procS
*) NULL
)
11850 as_warn (_(".frame outside of .ent"));
11851 demand_empty_rest_of_line ();
11855 cur_proc_ptr
->frame_reg
= tc_get_register (1);
11857 SKIP_WHITESPACE ();
11858 if (*input_line_pointer
++ != ','
11859 || get_absolute_expression_and_terminator (&val
) != ',')
11861 as_warn (_("Bad .frame directive"));
11862 --input_line_pointer
;
11863 demand_empty_rest_of_line ();
11867 cur_proc_ptr
->frame_offset
= val
;
11868 cur_proc_ptr
->pc_reg
= tc_get_register (0);
11870 demand_empty_rest_of_line ();
11873 #endif /* MIPS_STABS_ELF */
11876 /* The .fmask and .mask directives. If the mdebug section is present
11877 (IRIX 5 native) then ecoff.c (ecoff_directive_mask) is used. For
11878 embedded targets, s_mips_mask is used so that we can set the PDR
11879 information correctly. We can't use the ecoff routines because they
11880 make reference to the ecoff symbol table (in the mdebug section). */
11883 s_mips_mask (reg_type
)
11886 #ifdef MIPS_STABS_ELF
11889 if (cur_proc_ptr
== (procS
*) NULL
)
11891 as_warn (_(".mask/.fmask outside of .ent"));
11892 demand_empty_rest_of_line ();
11896 if (get_absolute_expression_and_terminator (&mask
) != ',')
11898 as_warn (_("Bad .mask/.fmask directive"));
11899 --input_line_pointer
;
11900 demand_empty_rest_of_line ();
11904 off
= get_absolute_expression ();
11906 if (reg_type
== 'F')
11908 cur_proc_ptr
->fpreg_mask
= mask
;
11909 cur_proc_ptr
->fpreg_offset
= off
;
11913 cur_proc_ptr
->reg_mask
= mask
;
11914 cur_proc_ptr
->reg_offset
= off
;
11917 demand_empty_rest_of_line ();
11919 s_ignore (reg_type
);
11920 #endif /* MIPS_STABS_ELF */
11923 /* The .loc directive. */
11934 assert (now_seg
== text_section
);
11936 lineno
= get_number ();
11937 addroff
= frag_now_fix ();
11939 symbolP
= symbol_new ("", N_SLINE
, addroff
, frag_now
);
11940 S_SET_TYPE (symbolP
, N_SLINE
);
11941 S_SET_OTHER (symbolP
, 0);
11942 S_SET_DESC (symbolP
, lineno
);
11943 symbolP
->sy_segment
= now_seg
;
11947 /* CPU name/ISA/number mapping table.
11949 Entries are grouped by type. The first matching CPU or ISA entry
11950 gets chosen by CPU or ISA, so it should be the 'canonical' name
11951 for that type. Entries after that within the type are sorted
11954 Case is ignored in comparison, so put the canonical entry in the
11955 appropriate case but everything else in lower case to ease eye pain. */
11956 static const struct mips_cpu_info mips_cpu_info_table
[] =
11959 { "MIPS1", 1, ISA_MIPS1
, CPU_R3000
, },
11960 { "mips", 1, ISA_MIPS1
, CPU_R3000
, },
11963 { "MIPS2", 1, ISA_MIPS2
, CPU_R6000
, },
11966 { "MIPS3", 1, ISA_MIPS3
, CPU_R4000
, },
11969 { "MIPS4", 1, ISA_MIPS4
, CPU_R8000
, },
11972 { "MIPS5", 1, ISA_MIPS5
, CPU_MIPS5
, },
11973 { "Generic-MIPS5", 0, ISA_MIPS5
, CPU_MIPS5
, },
11976 { "MIPS32", 1, ISA_MIPS32
, CPU_MIPS32
, },
11977 { "Generic-MIPS32", 0, ISA_MIPS32
, CPU_MIPS32
, },
11980 /* XXX for now, MIPS64 -> MIPS3 because of history */
11981 { "MIPS64", 1, ISA_MIPS3
, CPU_R4000
}, /* XXX! */
11984 { "MIPS64", 1, ISA_MIPS64
, CPU_MIPS64
},
11986 { "mips64isa", 1, ISA_MIPS64
, CPU_MIPS64
},
11987 { "Generic-MIPS64", 0, ISA_MIPS64
, CPU_MIPS64
, },
11990 { "R2000", 0, ISA_MIPS1
, CPU_R2000
, },
11991 { "2000", 0, ISA_MIPS1
, CPU_R2000
, },
11992 { "2k", 0, ISA_MIPS1
, CPU_R2000
, },
11993 { "r2k", 0, ISA_MIPS1
, CPU_R2000
, },
11996 { "R3000", 0, ISA_MIPS1
, CPU_R3000
, },
11997 { "3000", 0, ISA_MIPS1
, CPU_R3000
, },
11998 { "3k", 0, ISA_MIPS1
, CPU_R3000
, },
11999 { "r3k", 0, ISA_MIPS1
, CPU_R3000
, },
12002 { "R3900", 0, ISA_MIPS1
, CPU_R3900
, },
12003 { "3900", 0, ISA_MIPS1
, CPU_R3900
, },
12004 { "mipstx39", 0, ISA_MIPS1
, CPU_R3900
, },
12007 { "R4000", 0, ISA_MIPS3
, CPU_R4000
, },
12008 { "4000", 0, ISA_MIPS3
, CPU_R4000
, },
12009 { "4k", 0, ISA_MIPS3
, CPU_R4000
, }, /* beware */
12010 { "r4k", 0, ISA_MIPS3
, CPU_R4000
, },
12013 { "R4010", 0, ISA_MIPS2
, CPU_R4010
, },
12014 { "4010", 0, ISA_MIPS2
, CPU_R4010
, },
12017 { "R4400", 0, ISA_MIPS3
, CPU_R4400
, },
12018 { "4400", 0, ISA_MIPS3
, CPU_R4400
, },
12021 { "R4600", 0, ISA_MIPS3
, CPU_R4600
, },
12022 { "4600", 0, ISA_MIPS3
, CPU_R4600
, },
12023 { "mips64orion", 0, ISA_MIPS3
, CPU_R4600
, },
12024 { "orion", 0, ISA_MIPS3
, CPU_R4600
, },
12027 { "R4650", 0, ISA_MIPS3
, CPU_R4650
, },
12028 { "4650", 0, ISA_MIPS3
, CPU_R4650
, },
12031 { "R6000", 0, ISA_MIPS2
, CPU_R6000
, },
12032 { "6000", 0, ISA_MIPS2
, CPU_R6000
, },
12033 { "6k", 0, ISA_MIPS2
, CPU_R6000
, },
12034 { "r6k", 0, ISA_MIPS2
, CPU_R6000
, },
12037 { "R8000", 0, ISA_MIPS4
, CPU_R8000
, },
12038 { "8000", 0, ISA_MIPS4
, CPU_R8000
, },
12039 { "8k", 0, ISA_MIPS4
, CPU_R8000
, },
12040 { "r8k", 0, ISA_MIPS4
, CPU_R8000
, },
12043 { "R10000", 0, ISA_MIPS4
, CPU_R10000
, },
12044 { "10000", 0, ISA_MIPS4
, CPU_R10000
, },
12045 { "10k", 0, ISA_MIPS4
, CPU_R10000
, },
12046 { "r10k", 0, ISA_MIPS4
, CPU_R10000
, },
12049 { "R12000", 0, ISA_MIPS4
, CPU_R12000
, },
12050 { "12000", 0, ISA_MIPS4
, CPU_R12000
, },
12051 { "12k", 0, ISA_MIPS4
, CPU_R12000
, },
12052 { "r12k", 0, ISA_MIPS4
, CPU_R12000
, },
12055 { "VR4100", 0, ISA_MIPS3
, CPU_VR4100
, },
12056 { "4100", 0, ISA_MIPS3
, CPU_VR4100
, },
12057 { "mips64vr4100", 0, ISA_MIPS3
, CPU_VR4100
, },
12058 { "r4100", 0, ISA_MIPS3
, CPU_VR4100
, },
12061 { "VR4111", 0, ISA_MIPS3
, CPU_R4111
, },
12062 { "4111", 0, ISA_MIPS3
, CPU_R4111
, },
12063 { "mips64vr4111", 0, ISA_MIPS3
, CPU_R4111
, },
12064 { "r4111", 0, ISA_MIPS3
, CPU_R4111
, },
12067 { "VR4300", 0, ISA_MIPS3
, CPU_R4300
, },
12068 { "4300", 0, ISA_MIPS3
, CPU_R4300
, },
12069 { "mips64vr4300", 0, ISA_MIPS3
, CPU_R4300
, },
12070 { "r4300", 0, ISA_MIPS3
, CPU_R4300
, },
12073 { "VR5000", 0, ISA_MIPS4
, CPU_R5000
, },
12074 { "5000", 0, ISA_MIPS4
, CPU_R5000
, },
12075 { "5k", 0, ISA_MIPS4
, CPU_R5000
, },
12076 { "mips64vr5000", 0, ISA_MIPS4
, CPU_R5000
, },
12077 { "r5000", 0, ISA_MIPS4
, CPU_R5000
, },
12078 { "r5200", 0, ISA_MIPS4
, CPU_R5000
, },
12079 { "rm5200", 0, ISA_MIPS4
, CPU_R5000
, },
12080 { "r5230", 0, ISA_MIPS4
, CPU_R5000
, },
12081 { "rm5230", 0, ISA_MIPS4
, CPU_R5000
, },
12082 { "r5231", 0, ISA_MIPS4
, CPU_R5000
, },
12083 { "rm5231", 0, ISA_MIPS4
, CPU_R5000
, },
12084 { "r5261", 0, ISA_MIPS4
, CPU_R5000
, },
12085 { "rm5261", 0, ISA_MIPS4
, CPU_R5000
, },
12086 { "r5721", 0, ISA_MIPS4
, CPU_R5000
, },
12087 { "rm5721", 0, ISA_MIPS4
, CPU_R5000
, },
12088 { "r5k", 0, ISA_MIPS4
, CPU_R5000
, },
12089 { "r7000", 0, ISA_MIPS4
, CPU_R5000
, },
12091 /* MIPS32 4K CPU */
12092 { "MIPS32-4K", 0, ISA_MIPS32
, CPU_MIPS32_4K
, },
12093 { "4kc", 0, ISA_MIPS32
, CPU_MIPS32_4K
, },
12094 { "4km", 0, ISA_MIPS32
, CPU_MIPS32_4K
, },
12095 { "4kp", 0, ISA_MIPS32
, CPU_MIPS32_4K
, },
12096 { "mips32-4kc", 0, ISA_MIPS32
, CPU_MIPS32_4K
, },
12097 { "mips32-4km", 0, ISA_MIPS32
, CPU_MIPS32_4K
, },
12098 { "mips32-4kp", 0, ISA_MIPS32
, CPU_MIPS32_4K
, },
12100 /* SiByte SB-1 CPU */
12101 { "SB-1", 0, ISA_MIPS64
, CPU_SB1
, },
12102 { "sb-1250", 0, ISA_MIPS64
, CPU_SB1
, },
12103 { "sb1", 0, ISA_MIPS64
, CPU_SB1
, },
12104 { "sb1250", 0, ISA_MIPS64
, CPU_SB1
, },
12107 { NULL
, 0, 0, 0, },
12110 static const struct mips_cpu_info
*
12111 mips_cpu_info_from_name (name
)
12116 for (i
= 0; mips_cpu_info_table
[i
].name
!= NULL
; i
++)
12117 if (strcasecmp (name
, mips_cpu_info_table
[i
].name
) == 0)
12118 return (&mips_cpu_info_table
[i
]);
12123 static const struct mips_cpu_info
*
12124 mips_cpu_info_from_isa (isa
)
12129 for (i
= 0; mips_cpu_info_table
[i
].name
!= NULL
; i
++)
12130 if (mips_cpu_info_table
[i
].is_isa
12131 && isa
== mips_cpu_info_table
[i
].isa
)
12132 return (&mips_cpu_info_table
[i
]);
12137 static const struct mips_cpu_info
*
12138 mips_cpu_info_from_cpu (cpu
)
12143 for (i
= 0; mips_cpu_info_table
[i
].name
!= NULL
; i
++)
12144 if (!mips_cpu_info_table
[i
].is_isa
12145 && cpu
== mips_cpu_info_table
[i
].cpu
)
12146 return (&mips_cpu_info_table
[i
]);