1 /* tc-mips.c -- assemble code for a MIPS chip.
2 Copyright (C) 1993 Free Software Foundation, Inc.
3 Contributed by the OSF and Ralph Campbell.
4 Written by Keith Knowles and Ralph Campbell, working independently.
5 Modified for ECOFF support by Ian Lance Taylor of Cygnus Support.
7 This file is part of GAS.
9 GAS is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2, or (at your option)
14 GAS is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with GAS; see the file COPYING. If not, write to
21 the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */
38 #endif /* NO_VARARGS */
39 #endif /* NO_STDARG */
41 #include "opcode/mips.h"
47 static int mips_warn_about_macros
;
48 static int mips_noreorder
;
49 static int mips_nomove
;
51 static int mips_nobopt
;
54 /* The size of the small data section. */
55 static int g_switch_value
= 8;
61 /* handle of the OPCODE hash table */
62 static struct hash_control
*op_hash
= NULL
;
64 /* This array holds the chars that always start a comment. If the
65 pre-processor is disabled, these aren't very useful */
66 const char comment_chars
[] = "#";
68 /* This array holds the chars that only start a comment at the beginning of
69 a line. If the line seems to have the form '# 123 filename'
70 .line and .file directives will appear in the pre-processed output */
71 /* Note that input_file.c hand checks for '#' at the beginning of the
72 first line of the input file. This is because the compiler outputs
73 #NO_APP at the beginning of its output. */
74 /* Also note that C style comments are always supported. */
75 const char line_comment_chars
[] = "#";
77 /* This array holds machine specific line separator characters. */
78 const char line_separator_chars
[] = "";
80 /* Chars that can be used to separate mant from exp in floating point nums */
81 const char EXP_CHARS
[] = "eE";
83 /* Chars that mean this number is a floating point constant */
86 const char FLT_CHARS
[] = "rRsSfFdDxXpP";
88 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
89 changed in read.c . Ideally it shouldn't have to know about it at all,
90 but nothing is ideal around here.
93 static char *insn_error
;
95 static int byte_order
= BYTE_ORDER
;
97 static int auto_align
= 1;
99 /* Symbol labelling the current insn. */
100 static symbolS
*insn_label
;
102 /* To output NOP instructions correctly, we need to keep information
103 about the previous two instructions. */
105 /* The previous instruction. */
106 static struct mips_cl_insn prev_insn
;
108 /* The instruction before prev_insn. */
109 static struct mips_cl_insn prev_prev_insn
;
111 /* If we don't want information for prev_insn or prev_prev_insn, we
112 point the insn_mo field at this dummy integer. */
113 static const struct mips_opcode dummy_opcode
= { 0 };
115 /* Non-zero if prev_insn is valid. */
116 static int prev_insn_valid
;
118 /* The frag for the previous instruction. */
119 static struct frag
*prev_insn_frag
;
121 /* The offset into prev_insn_frag for the previous instruction. */
122 static long prev_insn_where
;
124 /* The reloc for the previous instruction, if any. */
125 static fixS
*prev_insn_fixp
;
127 /* Non-zero if the previous instruction was in a delay slot. */
128 static int prev_insn_is_delay_slot
;
130 /* Prototypes for static functions. */
133 #define internalError() \
134 as_fatal ("internal Error, line %d, %s", __LINE__, __FILE__)
136 #define internalError() as_fatal ("MIPS internal Error");
139 static int insn_uses_reg
PARAMS ((struct mips_cl_insn
*ip
,
141 static void append_insn
PARAMS ((struct mips_cl_insn
* ip
,
143 bfd_reloc_code_real_type r
));
144 static void mips_no_prev_insn
PARAMS ((void));
145 static void mips_emit_delays
PARAMS ((void));
146 static int gp_reference
PARAMS ((expressionS
* ep
));
147 static void macro_build
PARAMS ((int *counter
, expressionS
* ep
,
148 const char *name
, const char *fmt
,
150 static void macro_build_lui
PARAMS ((int *counter
, expressionS
* ep
,
152 static void set_at
PARAMS ((int *counter
, int reg
));
153 static void set_at_unsigned
PARAMS ((int *counter
, int reg
));
154 static void check_absolute_expr
PARAMS ((struct mips_cl_insn
* ip
,
155 expressionS
* expr
));
156 static void load_register
PARAMS ((int *counter
,
157 struct mips_cl_insn
* ip
,
158 int reg
, expressionS
* ep
));
159 static void macro
PARAMS ((struct mips_cl_insn
* ip
));
160 static void mips_ip
PARAMS ((char *str
, struct mips_cl_insn
* ip
));
161 static int my_getSmallExpression
PARAMS ((expressionS
* ep
, char *str
));
162 static void my_getExpression
PARAMS ((expressionS
* ep
, char *str
));
163 static symbolS
*get_symbol
PARAMS ((void));
164 static long get_optional_absolute_expression
PARAMS ((void));
165 static void mips_align
PARAMS ((int to
, int fill
));
166 static void s_align
PARAMS ((int));
167 static void s_stringer
PARAMS ((int));
168 static void s_change_sec
PARAMS ((int));
169 static void s_cons
PARAMS ((int));
170 static void s_err
PARAMS ((int));
171 static void s_extern
PARAMS ((int));
172 static void s_float_cons
PARAMS ((int));
173 static void s_option
PARAMS ((int));
174 static void s_mipsset
PARAMS ((int));
175 static void s_mips_space
PARAMS ((int));
177 static void md_obj_begin
PARAMS ((void));
178 static void md_obj_end
PARAMS ((void));
179 static long get_number
PARAMS ((void));
180 static void s_ent
PARAMS ((int));
181 static void s_mipsend
PARAMS ((int));
182 static void s_file
PARAMS ((int));
183 static void s_frame
PARAMS ((int));
184 static void s_loc
PARAMS ((int));
185 static void s_mask
PARAMS ((char));
190 The following pseudo-ops from the Kane and Heinrich MIPS book
191 should be defined here, but are currently unsupported: .alias,
192 .galive, .gjaldef, .gjrlive, .livereg, .noalias.
194 The following pseudo-ops from the Kane and Heinrich MIPS book are
195 specific to the type of debugging information being generated, and
196 should be defined by the object format: .aent, .begin, .bend,
197 .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp,
200 The following pseudo-ops from the Kane and Heinrich MIPS book are
201 not MIPS CPU specific, but are also not specific to the object file
202 format. This file is probably the best place to define them, but
203 they are not currently supported: .asm0, .endr, .lab, .repeat,
204 .struct, .weakext. */
206 const pseudo_typeS md_pseudo_table
[] =
208 /* MIPS specific pseudo-ops. */
209 {"option", s_option
, 0},
210 {"set", s_mipsset
, 0},
211 {"rdata", s_change_sec
, 'r',},
212 {"sdata", s_change_sec
, 's',},
214 /* Relatively generic pseudo-ops that happen to be used on MIPS
216 {"asciiz", s_stringer
, 1},
217 {"bss", s_change_sec
, 'b'},
221 /* These pseudo-ops are defined in read.c, but must be overridden
222 here for one reason or another. */
223 {"align", s_align
, 0},
224 {"ascii", s_stringer
, 0},
225 {"asciz", s_stringer
, 1},
227 {"data", s_change_sec
, 'd'},
228 {"double", s_float_cons
, 'd'},
229 {"extern", s_extern
, 0},
230 {"float", s_float_cons
, 'f'},
231 {"space", s_mips_space
, 0},
232 {"text", s_change_sec
, 't'},
236 /* These pseudo-ops should be defined by the object file format.
237 However, ECOFF is the only format which currently defines them,
238 so we have versions here for a.out. */
240 {"end", s_mipsend
, 0},
243 {"fmask", s_ignore
, 'F'},
244 {"frame", s_ignore
, 0},
245 {"loc", s_ignore
, 0},
246 {"mask", s_ignore
, 'R'},
247 {"verstamp", s_ignore
, 0},
254 const relax_typeS md_relax_table
[] =
260 static char *expr_end
;
262 static expressionS imm_expr
;
263 static expressionS offset_expr
;
264 static bfd_reloc_code_real_type imm_reloc
;
265 static bfd_reloc_code_real_type offset_reloc
;
268 * This function is called once, at assembler startup time. It should
269 * set up all the tables, etc. that the MD part of the assembler will need.
274 register char *retval
= NULL
;
275 register unsigned int i
= 0;
277 if ((op_hash
= hash_new ()) == NULL
)
279 as_fatal ("Virtual memory exhausted");
281 for (i
= 0; i
< NUMOPCODES
;)
283 const char *name
= mips_opcodes
[i
].name
;
285 retval
= hash_insert (op_hash
, name
, &mips_opcodes
[i
]);
286 if (retval
!= NULL
&& *retval
!= '\0')
288 fprintf (stderr
, "internal error: can't hash `%s': %s\n",
289 mips_opcodes
[i
].name
, retval
);
290 as_fatal ("Broken assembler. No assembly attempted.");
294 if ((mips_opcodes
[i
].match
& mips_opcodes
[i
].mask
) !=
295 mips_opcodes
[i
].match
)
297 fprintf (stderr
, "internal error: bad opcode: `%s' \"%s\"\n",
298 mips_opcodes
[i
].name
, mips_opcodes
[i
].args
);
299 as_fatal ("Broken assembler. No assembly attempted.");
303 while ((i
< NUMOPCODES
) && !strcmp (mips_opcodes
[i
].name
, name
));
306 mips_no_prev_insn ();
325 struct mips_cl_insn insn
;
330 /* set the default alignment for the text section (2**2) */
331 /* This should go in md_begin but text_section isn't initialized then */
332 record_alignment (text_section
, 2);
334 bfd_set_gp_size (stdoutput
, g_switch_value
);
339 imm_expr
.X_seg
= absent_section
;
340 offset_expr
.X_seg
= absent_section
;
342 mips_ip (str
, &insn
);
345 as_bad ("%s `%s'", insn_error
, str
);
348 if (insn
.insn_mo
->pinfo
== INSN_MACRO
)
354 if (imm_expr
.X_seg
!= absent_section
)
355 append_insn (&insn
, &imm_expr
, imm_reloc
);
356 else if (offset_expr
.X_seg
!= absent_section
)
357 append_insn (&insn
, &offset_expr
, offset_reloc
);
359 append_insn (&insn
, NULL
, BFD_RELOC_UNUSED
);
363 /* See whether instruction IP reads register REG. If FPR is non-zero,
364 REG is a floating point register. */
367 insn_uses_reg (ip
, reg
, fpr
)
368 struct mips_cl_insn
*ip
;
372 /* Don't report on general register 0, since it never changes. */
373 if (! fpr
&& reg
== 0)
378 /* If we are called with either $f0 or $f1, we must check $f0.
379 This is not optimal, because it will introduce an unnecessary
380 NOP between "lwc1 $f0" and "swc1 $f1". To fix this we would
381 need to distinguish reading both $f0 and $f1 or just one of
382 them. Note that we don't have to check the other way,
383 because there is no instruction that sets both $f0 and $f1
384 and requires a delay. */
385 if ((ip
->insn_mo
->pinfo
& INSN_READ_FPR_S
)
386 && ((ip
->insn_opcode
>> OP_SH_FS
) & OP_MASK_FS
) == (reg
&~ 1))
388 if ((ip
->insn_mo
->pinfo
& INSN_READ_FPR_T
)
389 && ((ip
->insn_opcode
>> OP_SH_FT
) & OP_MASK_FT
) == (reg
&~ 1))
394 if ((ip
->insn_mo
->pinfo
& INSN_READ_GPR_S
)
395 && ((ip
->insn_opcode
>> OP_SH_RS
) & OP_MASK_RS
) == reg
)
397 if ((ip
->insn_mo
->pinfo
& INSN_READ_GPR_T
)
398 && ((ip
->insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
) == reg
)
405 #define ALIGN_ERR "Attempt to assemble instruction onto non word boundary."
406 #define ALIGN_ERR2 "GAS doesn't do implicit alignment; use .align directive."
410 * Output an instruction.
413 append_insn (ip
, address_expr
, reloc_type
)
414 struct mips_cl_insn
*ip
;
415 expressionS
*address_expr
;
416 bfd_reloc_code_real_type reloc_type
;
422 if (! mips_noreorder
)
424 /* If the previous insn required any delay slots, see if we need
425 to insert a NOP or two. There are six kinds of possible
426 hazards, of which an instruction can have at most one type.
428 (2) an unconditional branch delay
429 (3) a conditional branch delay
430 (4) a generic coprocessor delay
431 (5) a coprocessor condition code delay
432 (6) a HI/LO special register delay
434 There are a lot of optimizations we could do that we don't.
435 In particular, we do not, in general, reorder instructions.
436 If you use gcc with optimization, it will reorder
437 instructions and generally do much more optimization then we
438 do here; repeating all that work in the assembler would only
439 benefit hand written assembly code, and does not seem worth
442 /* This is how a NOP is emitted. */
443 #define emit_nop() md_number_to_chars (frag_more (4), 0, 4)
445 /* The previous insn might require a delay slot, depending upon
446 the contents of the current insn. */
447 if (prev_insn
.insn_mo
->pinfo
& INSN_LOAD_DELAY
)
449 /* A load delay. All load delays delay the use of general
450 register rt for one instruction. */
451 know (prev_insn
.insn_mo
->pinfo
& INSN_WRITE_GPR_T
);
452 if (insn_uses_reg (ip
,
453 (prev_insn
.insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
,
457 else if (prev_insn
.insn_mo
->pinfo
& INSN_COPROC_DELAY
)
459 /* A generic coprocessor delay. The previous instruction
460 modified a coprocessor general or control register. If
461 it modified a control register, we need to avoid any
462 coprocessor instruction (this is probably not always
463 required, but it sometimes is). If it modified a general
464 register, we avoid using that register.
466 This case is not handled very well. There is no special
467 knowledge of CP0 handling, and the coprocessors other
468 than the floating point unit are not distinguished at
470 if (prev_insn
.insn_mo
->pinfo
& INSN_WRITE_FPR_T
)
472 if (insn_uses_reg (ip
,
473 ((prev_insn
.insn_opcode
>> OP_SH_RT
)
478 else if (prev_insn
.insn_mo
->pinfo
& INSN_WRITE_FPR_D
)
480 if (insn_uses_reg (ip
,
481 ((prev_insn
.insn_opcode
>> OP_SH_RD
)
488 /* We don't know exactly what the previous instruction
489 does. If the current instruction uses a coprocessor
490 register, we must insert a NOP. If previous
491 instruction may set the condition codes, and the
492 current instruction uses them, we must insert two
494 if ((prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
)
495 && (ip
->insn_mo
->pinfo
& INSN_READ_COND_CODE
))
497 else if (ip
->insn_mo
->pinfo
& INSN_COP
)
501 else if (prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
)
503 /* The previous instruction sets the coprocessor condition
504 codes, but does not require a general coprocessor delay
505 (this means it is a floating point comparison
506 instruction). If this instruction uses the condition
507 codes, we need to insert a single NOP. */
508 if (ip
->insn_mo
->pinfo
& INSN_READ_COND_CODE
)
511 else if (prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
)
513 /* The previous instruction reads the LO register; if the
514 current instruction writes to the LO register, we must
516 if (ip
->insn_mo
->pinfo
& INSN_WRITE_LO
)
519 else if (prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
521 /* The previous instruction reads the HI register; if the
522 current instruction writes to the HI register, we must
524 if (ip
->insn_mo
->pinfo
& INSN_WRITE_HI
)
528 /* There are two cases which require two intervening
529 instructions: 1) setting the condition codes using a move to
530 coprocessor instruction which requires a general coprocessor
531 delay and then reading the condition codes 2) reading the HI
532 or LO register and then writing to it. If we are not already
533 emitting a NOP instruction, we must check for these cases
534 compared to the instruction previous to the previous
537 && (((prev_prev_insn
.insn_mo
->pinfo
& INSN_COPROC_DELAY
)
538 && (prev_prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
)
539 && (ip
->insn_mo
->pinfo
& INSN_READ_COND_CODE
))
540 || ((prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
)
541 && (ip
->insn_mo
->pinfo
& INSN_WRITE_LO
))
542 || ((prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
543 && (ip
->insn_mo
->pinfo
& INSN_WRITE_HI
))))
546 /* Now emit the right number of NOP instructions. */
552 if (insn_label
!= NULL
)
554 assert (S_GET_SEGMENT (insn_label
) == now_seg
);
555 insn_label
->sy_frag
= frag_now
;
556 S_SET_VALUE (insn_label
, frag_now_fix ());
563 /* This is testing the address of the frag, not the alignment of
564 the instruction in the current section. */
572 if (address_expr
!= NULL
)
574 if (address_expr
->X_seg
== &bfd_abs_section
)
579 ip
->insn_opcode
|= address_expr
->X_add_number
;
583 ip
->insn_opcode
|= address_expr
->X_add_number
& 0xffff;
586 case BFD_RELOC_MIPS_JMP
:
587 case BFD_RELOC_16_PCREL_S2
:
596 assert (reloc_type
!= BFD_RELOC_UNUSED
);
598 fixp
= fix_new (frag_now
, f
- frag_now
->fr_literal
, 4,
599 address_expr
->X_add_symbol
,
600 address_expr
->X_subtract_symbol
,
601 address_expr
->X_add_number
,
602 reloc_type
== BFD_RELOC_16_PCREL_S2
,
607 md_number_to_chars (f
, ip
->insn_opcode
, 4);
609 if (! mips_noreorder
)
611 /* Filling the branch delay slot is more complex. We try to
612 switch the branch with the previous instruction, which we can
613 do if the previous instruction does not set up a condition
614 that the branch tests and if the branch is not itself the
615 target of any branch. */
616 if ((ip
->insn_mo
->pinfo
& INSN_UNCOND_BRANCH_DELAY
)
617 || (ip
->insn_mo
->pinfo
& INSN_COND_BRANCH_DELAY
))
619 /* If we had to emit any NOP instructions, then we already
620 know we can not swap. */
622 /* If we don't even know the previous insn, we can not
625 /* If the previous insn is already in a branch delay
626 slot, then we can not swap. */
627 || prev_insn_is_delay_slot
628 /* If the branch is itself the target of a branch, we
629 can not swap. We cheat on this; all we check for is
630 whether there is a label on this instruction. If
631 there are any branches to anything other than a
632 label, users must use .set noreorder. */
633 || insn_label
!= NULL
634 /* If the branch reads the condition codes, we don't
635 even try to swap, because in the sequence
640 we can not swap, and I don't feel like handling that
642 || (ip
->insn_mo
->pinfo
& INSN_READ_COND_CODE
)
643 /* We can not swap with an instruction that requires a
644 delay slot, becase the target of the branch might
645 interfere with that instruction. */
646 || (prev_insn
.insn_mo
->pinfo
649 | INSN_WRITE_COND_CODE
652 /* We can not swap with a branch instruction. */
653 || (prev_insn
.insn_mo
->pinfo
654 & (INSN_UNCOND_BRANCH_DELAY
| INSN_COND_BRANCH_DELAY
))
655 /* If the branch reads a register that the previous
656 instruction sets, we can not swap. */
657 || ((prev_insn
.insn_mo
->pinfo
& INSN_WRITE_GPR_T
)
658 && insn_uses_reg (ip
,
659 ((prev_insn
.insn_opcode
>> OP_SH_RT
)
662 || ((prev_insn
.insn_mo
->pinfo
& INSN_WRITE_GPR_D
)
663 && insn_uses_reg (ip
,
664 ((prev_insn
.insn_opcode
>> OP_SH_RD
)
667 /* If the branch writes a register that the previous
668 instruction reads, we can not swap (we know that
669 branches only write to RD or to $31). */
670 || ((ip
->insn_mo
->pinfo
& INSN_WRITE_GPR_D
)
671 && insn_uses_reg (&prev_insn
,
672 ((ip
->insn_opcode
>> OP_SH_RD
)
675 || ((ip
->insn_mo
->pinfo
& INSN_WRITE_GPR_31
)
676 && insn_uses_reg (&prev_insn
, 31, 0))
677 /* If the previous previous instruction has a load
678 delay, and sets a register that the branch reads, we
680 || ((prev_prev_insn
.insn_mo
->pinfo
& INSN_LOAD_DELAY
)
681 && insn_uses_reg (ip
,
682 ((prev_prev_insn
.insn_opcode
>> OP_SH_RT
)
686 /* We could do even better for unconditional branches to
687 portions of this object file; we could pick up the
688 instruction at the destination, put it in the delay
689 slot, and bump the destination address. */
691 /* Update the previous insn information. */
692 prev_prev_insn
= *ip
;
693 prev_insn
.insn_mo
= &dummy_opcode
;
700 /* It looks like we can actually do the swap. */
701 prev_f
= prev_insn_frag
->fr_literal
+ prev_insn_where
;
702 memcpy (temp
, prev_f
, 4);
703 memcpy (prev_f
, f
, 4);
707 prev_insn_fixp
->fx_frag
= frag_now
;
708 prev_insn_fixp
->fx_where
= f
- frag_now
->fr_literal
;
712 fixp
->fx_frag
= prev_insn_frag
;
713 fixp
->fx_where
= prev_insn_where
;
715 /* Update the previous insn information; leave prev_insn
717 prev_prev_insn
= *ip
;
719 prev_insn_is_delay_slot
= 1;
721 /* If that was an unconditional branch, forget the previous
723 if (ip
->insn_mo
->pinfo
& INSN_UNCOND_BRANCH_DELAY
)
725 prev_prev_insn
.insn_mo
= &dummy_opcode
;
726 prev_insn
.insn_mo
= &dummy_opcode
;
731 /* Update the previous insn information. */
733 prev_prev_insn
.insn_mo
= &dummy_opcode
;
735 prev_prev_insn
= prev_insn
;
738 /* Any time we see a branch, we always fill the delay slot
739 immediately; since this insn is not a branch, we know it
740 is not in a delay slot. */
741 prev_insn_is_delay_slot
= 0;
744 prev_insn_frag
= frag_now
;
745 prev_insn_where
= f
- frag_now
->fr_literal
;
746 prev_insn_fixp
= fixp
;
750 /* We just output an insn, so the next one doesn't have a label. */
754 /* This function forgets that there was any previous instruction or
760 prev_insn
.insn_mo
= &dummy_opcode
;
761 prev_prev_insn
.insn_mo
= &dummy_opcode
;
763 prev_insn_is_delay_slot
= 0;
767 /* This function must be called whenever we turn on noreorder or emit
768 something other than instructions. It inserts any NOPS which might
769 be needed by the previous instruction, and clears the information
770 kept for the previous instructions. */
775 if (! mips_noreorder
)
780 if (prev_insn
.insn_mo
->pinfo
& ANY_DELAY
)
783 if ((prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
)
784 || (prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
785 || (prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
))
788 else if ((prev_prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
)
789 || (prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
790 || (prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
))
795 if (insn_label
!= NULL
)
797 assert (S_GET_SEGMENT (insn_label
) == now_seg
);
798 insn_label
->sy_frag
= frag_now
;
799 S_SET_VALUE (insn_label
, frag_now_fix ());
802 mips_no_prev_insn ();
806 /* Return 1 if an expression can be accessed via the GP register. */
817 sym
= ep
->X_add_symbol
;
818 if (sym
== (symbolS
*) NULL
819 || ep
->X_subtract_symbol
!= (symbolS
*) NULL
)
822 /* Certain symbols can not be referenced off the GP, although it
823 appears as though they can. */
824 symname
= S_GET_NAME (sym
);
825 if (symname
!= (const char *) NULL
826 && (strcmp (symname
, "eprol") == 0
827 || strcmp (symname
, "etext") == 0
828 || strcmp (symname
, "_gp") == 0
829 || strcmp (symname
, "edata") == 0
830 || strcmp (symname
, "_fbss") == 0
831 || strcmp (symname
, "_fdata") == 0
832 || strcmp (symname
, "_ftext") == 0
833 || strcmp (symname
, "end") == 0))
835 if (! S_IS_DEFINED (sym
)
836 && S_GET_VALUE (sym
) != 0
837 && S_GET_VALUE (sym
) <= g_switch_value
)
839 segname
= segment_name (S_GET_SEGMENT (ep
->X_add_symbol
));
840 return (strcmp (segname
, ".sdata") == 0
841 || strcmp (segname
, ".sbss") == 0);
842 #else /* ! defined (OBJ_ECOFF) */
843 /* The GP register is only used for ECOFF. */
845 #endif /* ! defined (OBJ_ECOFF) */
848 /* Build an instruction created by a macro expansion. This is passed
849 a pointer to the count of instructions created so far, an
850 expression, the name of the instruction to build, an operand format
851 string, and corresponding arguments. */
855 macro_build (int *counter
,
860 #else /* ! defined (NO_STDARG) */
862 macro_build (counter
, ep
, name
, fmt
, va_alist
)
868 #endif /* ! defined (NO_STDARG) */
870 struct mips_cl_insn insn
;
871 bfd_reloc_code_real_type r
;
875 va_start (args
, fmt
);
881 * If the macro is about to expand into a second instruction,
882 * print a warning if needed. We need to pass ip as a parameter
883 * to generate a better warning message here...
885 if (mips_warn_about_macros
&& *counter
== 1)
886 as_warn ("Macro instruction expanded into multiple instructions");
888 *counter
+= 1; /* bump instruction counter */
890 r
= BFD_RELOC_UNUSED
;
891 insn
.insn_mo
= (struct mips_opcode
*) hash_find (op_hash
, name
);
892 assert (insn
.insn_mo
);
893 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
895 while (strcmp (fmt
, insn
.insn_mo
->args
) != 0)
898 assert (insn
.insn_mo
->name
);
899 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
901 assert (insn
.insn_mo
->pinfo
!= INSN_MACRO
);
902 insn
.insn_opcode
= insn
.insn_mo
->match
;
918 insn
.insn_opcode
|= va_arg (args
, int) << 16;
924 insn
.insn_opcode
|= va_arg (args
, int) << 16;
929 insn
.insn_opcode
|= va_arg (args
, int) << 11;
934 insn
.insn_opcode
|= va_arg (args
, int) << 11;
938 insn
.insn_opcode
|= va_arg (args
, int) << 6;
942 insn
.insn_opcode
|= va_arg (args
, int) << 6;
946 insn
.insn_opcode
|= va_arg (args
, int) << 6;
953 insn
.insn_opcode
|= va_arg (args
, int) << 21;
965 * This allows macro() to pass an immediate expression for
966 * creating short branches without creating a symbol.
967 * Note that the expression still might come from the assembly
968 * input, in which case the value is not checked for range nor
969 * is a relocation entry generated (yuck).
971 if (ep
->X_add_symbol
== NULL
&& ep
->X_seg
== &bfd_abs_section
)
973 insn
.insn_opcode
|= (ep
->X_add_number
>> 2) & 0xffff;
977 r
= BFD_RELOC_16_PCREL_S2
;
986 assert (r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
988 /* Use GP relative addressing if possible. */
989 if (r
== BFD_RELOC_LO16
990 && gp_reference (ep
))
991 r
= BFD_RELOC_MIPS_GPREL
;
993 append_insn (&insn
, ep
, r
);
997 * Generate a "lui" instruction.
1000 macro_build_lui (counter
, ep
, regnum
)
1005 expressionS high_expr
;
1006 struct mips_cl_insn insn
;
1007 bfd_reloc_code_real_type r
;
1008 CONST
char *name
= "lui";
1009 CONST
char *fmt
= "t,u";
1013 if (high_expr
.X_seg
== &bfd_abs_section
)
1015 /* we can compute the instruction now without a relocation entry */
1016 if (high_expr
.X_add_number
& 0x8000)
1017 high_expr
.X_add_number
+= 0x10000;
1018 high_expr
.X_add_number
=
1019 ((unsigned long) high_expr
.X_add_number
>> 16) & 0xffff;
1020 r
= BFD_RELOC_UNUSED
;
1023 r
= BFD_RELOC_HI16_S
;
1026 * If the macro is about to expand into a second instruction,
1027 * print a warning if needed. We need to pass ip as a parameter
1028 * to generate a better warning message here...
1030 if (mips_warn_about_macros
&& *counter
== 1)
1031 as_warn ("Macro instruction expanded into multiple instructions");
1033 *counter
+= 1; /* bump instruction counter */
1035 insn
.insn_mo
= (struct mips_opcode
*) hash_find (op_hash
, name
);
1036 assert (insn
.insn_mo
);
1037 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
1038 assert (strcmp (fmt
, insn
.insn_mo
->args
) == 0);
1040 insn
.insn_opcode
= insn
.insn_mo
->match
| (regnum
<< 16);
1041 if (r
== BFD_RELOC_UNUSED
)
1043 insn
.insn_opcode
|= high_expr
.X_add_number
;
1044 append_insn (&insn
, NULL
, r
);
1047 append_insn (&insn
, &high_expr
, r
);
1051 * Generates code to set the $at register to true (one)
1052 * if reg is less than the immediate expression.
1055 set_at (counter
, reg
)
1060 switch (imm_expr
.X_add_number
& 0xffff8000)
1064 macro_build (counter
, &imm_expr
, "slti", "t,r,j", AT
, reg
);
1068 macro_build (counter
, &imm_expr
, "ori", "t,r,i", AT
, 0);
1072 macro_build_lui (counter
, &imm_expr
, AT
);
1073 if (imm_expr
.X_add_number
& 0xffff)
1074 macro_build (counter
, &imm_expr
, "addiu", "t,r,j", AT
, AT
);
1076 macro_build (counter
, NULL
, "slt", "d,v,t", AT
, reg
, AT
);
1079 /* set_at_unsigned()
1080 * Generates code to set the $at register to true (one)
1081 * if reg is less than the immediate expression.
1082 * Unsigned comparison is perfomed.
1085 set_at_unsigned (counter
, reg
)
1090 switch (imm_expr
.X_add_number
& 0xffff8000)
1094 macro_build (counter
, &imm_expr
, "sltiu", "t,r,j", AT
, reg
);
1098 macro_build (counter
, &imm_expr
, "ori", "t,r,i", AT
, 0);
1102 macro_build_lui (counter
, &imm_expr
, AT
);
1103 if (imm_expr
.X_add_number
& 0xffff)
1104 macro_build (counter
, &imm_expr
, "addiu", "t,r,j", AT
, AT
);
1106 macro_build (counter
, NULL
, "sltu", "d,v,t", AT
, reg
, AT
);
1110 check_absolute_expr (ip
, expr
)
1111 struct mips_cl_insn
*ip
;
1115 if (expr
->X_seg
!= &bfd_abs_section
)
1116 as_warn ("Instruction %s requires absolute expression", ip
->insn_mo
->name
);
1120 * This routine generates the least number of instructions neccessary to load
1121 * an absolute expression value into a register.
1124 load_register (counter
, ip
, reg
, ep
)
1126 struct mips_cl_insn
*ip
;
1130 switch (ep
->X_add_number
& 0xffff8000)
1134 macro_build (counter
, ep
, "addiu", "t,r,j", reg
, 0);
1138 macro_build (counter
, ep
, "ori", "t,r,i", reg
, 0);
1142 macro_build_lui (counter
, ep
, reg
);
1143 if (ep
->X_add_number
& 0xffff)
1144 macro_build (counter
, ep
, "addiu", "t,r,j", reg
, reg
);
1151 * This routine implements the seemingly endless macro or synthesized
1152 * instructions and addressing modes in the mips assembly language. Many
1153 * of these macros are simple and are similar to each other. These could
1154 * probably be handled by some kind of table or grammer aproach instead of
1155 * this verbose method. Others are not simple macros but are more like
1156 * optimizing code generation.
1157 * One interesting optimization is when several store macros appear
1158 * consecutivly that would load AT with the upper half of the same address.
1159 * The ensuing load upper instructions are ommited. This implies some kind
1160 * of global optimization. We currently only optimize within a single macro.
1161 * For many of the load and store macros if the address is specified as a
1162 * constant expression in the first 64k of memory (ie ld $2,0x4000c) we
1163 * first load register 'at' with zero and use it as the base register. The
1164 * mips assembler simply uses register $zero. Just one tiny optimization
1169 struct mips_cl_insn
*ip
;
1171 register int treg
, sreg
, dreg
, breg
;
1180 treg
= (ip
->insn_opcode
>> 16) & 0x1f;
1181 dreg
= (ip
->insn_opcode
>> 11) & 0x1f;
1182 sreg
= breg
= (ip
->insn_opcode
>> 21) & 0x1f;
1183 mask
= ip
->insn_mo
->mask
;
1185 expr1
.X_seg
= &bfd_abs_section
;
1186 expr1
.X_subtract_symbol
= NULL
;
1187 expr1
.X_add_symbol
= NULL
;
1188 expr1
.X_add_number
= 1;
1195 Note: mips algorithm requires the move in the delay slot.
1196 <main>: bgez $a0,0x4001bc <main+12>
1197 <main+4>: move v0,$a0
1198 <main+8>: sub v0,$zero,$a0
1202 mips_emit_delays ();
1205 expr1
.X_add_number
= 8;
1206 macro_build (&icnt
, &expr1
, "bgez", "s,p", sreg
);
1207 macro_build (&icnt
, NULL
, "move", "d,s", dreg
, sreg
, 0);
1208 macro_build (&icnt
, NULL
, mask
== M_ABS
? "sub" : "subu", "d,v,t",
1216 switch (imm_expr
.X_add_number
& 0xffff8000)
1220 macro_build (&icnt
, &imm_expr
,
1221 mask
== M_ADD_I
? "addi" : "addiu", "t,r,j", treg
, sreg
);
1225 macro_build (&icnt
, &imm_expr
, "ori", "t,r,i", AT
, 0);
1229 macro_build_lui (&icnt
, &imm_expr
, AT
);
1230 if (imm_expr
.X_add_number
& 0xffff)
1231 macro_build (&icnt
, &imm_expr
, "addiu", "t,r,j", AT
, AT
);
1234 macro_build (&icnt
, NULL
,
1235 mask
== M_ADD_I
? "add" : "addu", "d,v,t", treg
, sreg
, AT
);
1242 switch (imm_expr
.X_add_number
& 0xffff8000)
1249 macro_build (&icnt
, &imm_expr
, "andi", "t,r,i", treg
, sreg
);
1252 macro_build (&icnt
, &imm_expr
, "ori", "t,r,i", treg
, sreg
);
1255 macro_build (&icnt
, &imm_expr
, "ori", "t,r,i", treg
, sreg
);
1256 macro_build (&icnt
, &imm_expr
, "nor", "d,v,t", treg
, treg
, 0);
1259 macro_build (&icnt
, &imm_expr
, "xori", "t,r,i", treg
, sreg
);
1266 macro_build (&icnt
, &imm_expr
, "addiu", "t,r,j", AT
, 0);
1270 macro_build_lui (&icnt
, &imm_expr
, AT
);
1271 if (imm_expr
.X_add_number
& 0xffff)
1272 macro_build (&icnt
, &imm_expr
, "addiu", "t,r,j", AT
, AT
);
1277 macro_build (&icnt
, NULL
, "and", "d,v,t", treg
, sreg
, AT
);
1280 macro_build (&icnt
, NULL
, "or", "d,v,t", treg
, sreg
, AT
);
1283 macro_build (&icnt
, NULL
, "nor", "d,v,t", treg
, sreg
, AT
);
1286 macro_build (&icnt
, NULL
, "xor", "d,v,t", treg
, sreg
, AT
);
1295 if (imm_expr
.X_add_number
== 0)
1297 macro_build (&icnt
, &offset_expr
, mask
== M_BEQ_I
? "beq" : "bne",
1301 load_register (&icnt
, ip
, AT
, &imm_expr
);
1302 macro_build (&icnt
, &offset_expr
, mask
== M_BEQ_I
? "beq" : "bne",
1309 macro_build (&icnt
, &offset_expr
, "bgez", "s,p", sreg
);
1314 macro_build (&icnt
, &offset_expr
, "blez", "s,p", treg
);
1317 macro_build (&icnt
, NULL
, "slt", "d,v,t", AT
, sreg
, treg
);
1318 macro_build (&icnt
, &offset_expr
, "beq", "s,t,p", AT
, 0);
1322 /* check for > max integer */
1323 if (imm_expr
.X_add_number
== 0x7fffffff)
1326 /* result is always false */
1327 as_warn ("Branch %s is always false (nop)", ip
->insn_mo
->name
);
1328 macro_build (&icnt
, NULL
, "nop", "", 0);
1331 imm_expr
.X_add_number
++;
1335 if (imm_expr
.X_add_number
== 0)
1337 macro_build (&icnt
, &offset_expr
, "bgez", "s,p", sreg
);
1340 if (imm_expr
.X_add_number
== 1)
1342 macro_build (&icnt
, &offset_expr
, "bgtz", "s,p", sreg
);
1345 if (imm_expr
.X_add_number
== 0x80000000)
1348 /* result is always true */
1349 as_warn ("Branch %s is always true", ip
->insn_mo
->name
);
1350 macro_build (&icnt
, &offset_expr
, "b", "p");
1353 set_at (&icnt
, sreg
);
1354 macro_build (&icnt
, &offset_expr
, "beq", "s,t,p", AT
, 0);
1362 macro_build (&icnt
, &offset_expr
, "beq", "s,t,p", 0, treg
);
1365 macro_build (&icnt
, NULL
, "sltu", "d,v,t", AT
, sreg
, treg
);
1366 macro_build (&icnt
, &offset_expr
, "beq", "s,t,p", AT
, 0);
1370 if (sreg
== 0 || imm_expr
.X_add_number
== 0xffffffff)
1372 imm_expr
.X_add_number
++;
1376 if (imm_expr
.X_add_number
== 0)
1378 if (imm_expr
.X_add_number
== 1)
1380 macro_build (&icnt
, &offset_expr
, "bne", "s,t,p", sreg
, 0);
1383 set_at_unsigned (&icnt
, sreg
);
1384 macro_build (&icnt
, &offset_expr
, "beq", "s,t,p", AT
, 0);
1390 macro_build (&icnt
, &offset_expr
, "bgtz", "s,p", sreg
);
1395 macro_build (&icnt
, &offset_expr
, "bltz", "s,p", treg
);
1398 macro_build (&icnt
, NULL
, "slt", "d,v,t", AT
, treg
, sreg
);
1399 macro_build (&icnt
, &offset_expr
, "bne", "s,t,p", AT
, 0);
1405 macro_build (&icnt
, &offset_expr
, "bne", "s,t,p", sreg
, 0);
1410 macro_build (&icnt
, NULL
, "sltu", "d,v,t", AT
, treg
, sreg
);
1411 macro_build (&icnt
, &offset_expr
, "bne", "s,t,p", AT
, 0);
1417 macro_build (&icnt
, &offset_expr
, "blez", "s,p", sreg
);
1422 macro_build (&icnt
, &offset_expr
, "bgez", "s,p", treg
);
1425 macro_build (&icnt
, NULL
, "slt", "d,v,t", AT
, treg
, sreg
);
1426 macro_build (&icnt
, &offset_expr
, "beq", "s,t,p", AT
, 0);
1430 if (imm_expr
.X_add_number
== 0x7fffffff)
1432 imm_expr
.X_add_number
++;
1436 if (imm_expr
.X_add_number
== 0)
1438 macro_build (&icnt
, &offset_expr
, "bltz", "s,p", sreg
);
1441 if (imm_expr
.X_add_number
== 1)
1443 macro_build (&icnt
, &offset_expr
, "blez", "s,p", sreg
);
1446 set_at (&icnt
, sreg
);
1447 macro_build (&icnt
, &offset_expr
, "bne", "s,t,p", AT
, 0);
1453 macro_build (&icnt
, &offset_expr
, "beq", "s,t,p", sreg
, 0);
1458 macro_build (&icnt
, NULL
, "sltu", "d,v,t", AT
, treg
, sreg
);
1459 macro_build (&icnt
, &offset_expr
, "beq", "s,t,p", AT
, 0);
1463 if (sreg
== 0 || imm_expr
.X_add_number
== 0xffffffff)
1465 imm_expr
.X_add_number
++;
1469 if (imm_expr
.X_add_number
== 0)
1471 if (imm_expr
.X_add_number
== 1)
1473 macro_build (&icnt
, &offset_expr
, "beq", "s,t,p", sreg
, 0);
1476 set_at_unsigned (&icnt
, sreg
);
1477 macro_build (&icnt
, &offset_expr
, "bne", "s,t,p", AT
, 0);
1483 macro_build (&icnt
, &offset_expr
, "bltz", "s,p", sreg
);
1488 macro_build (&icnt
, &offset_expr
, "bgtz", "s,p", treg
);
1491 macro_build (&icnt
, NULL
, "slt", "d,v,t", AT
, sreg
, treg
);
1492 macro_build (&icnt
, &offset_expr
, "bne", "s,t,p", AT
, 0);
1500 macro_build (&icnt
, &offset_expr
, "bne", "s,t,p", 0, treg
);
1503 macro_build (&icnt
, NULL
, "sltu", "d,v,t", AT
, sreg
, treg
);
1504 macro_build (&icnt
, &offset_expr
, "bne", "s,t,p", AT
, 0);
1511 as_warn ("Divide by zero.");
1512 macro_build (&icnt
, NULL
, "break", "c", 7);
1516 mips_emit_delays ();
1518 macro_build (&icnt
, NULL
, "div", "s,t", sreg
, treg
);
1519 expr1
.X_add_number
= 8;
1520 macro_build (&icnt
, &expr1
, "bne", "s,t,p", treg
, 0);
1521 macro_build (&icnt
, NULL
, "nop", "", 0);
1522 macro_build (&icnt
, NULL
, "break", "c", 7);
1523 expr1
.X_add_number
= -1;
1524 macro_build (&icnt
, &expr1
, "addiu", "t,r,j", AT
, 0);
1525 expr1
.X_add_number
= 16;
1526 macro_build (&icnt
, &expr1
, "bne", "s,t,p", treg
, AT
);
1527 expr1
.X_add_number
= 0x80000000;
1528 macro_build_lui (&icnt
, &expr1
, AT
);
1529 expr1
.X_add_number
= 8;
1530 macro_build (&icnt
, &expr1
, "bne", "s,t,p", sreg
, AT
);
1531 macro_build (&icnt
, NULL
, "nop", "", 0);
1532 macro_build (&icnt
, NULL
, "break", "c", 6);
1534 macro_build (&icnt
, NULL
, mask
== M_DIV_3
? "mflo" : "mfhi", "d", dreg
);
1535 /* with reorder on there will be two implicit nop instructions here. */
1542 if (imm_expr
.X_add_number
== 0)
1544 as_warn ("Divide by zero.");
1545 macro_build (&icnt
, NULL
, "break", "c", 7);
1548 if (imm_expr
.X_add_number
== 1)
1550 if (mask
== (int) M_DIV_3I
|| mask
== (int) M_DIVU_3I
)
1551 macro_build (&icnt
, NULL
, "move", "d,s", dreg
, sreg
);
1553 macro_build (&icnt
, NULL
, "move", "d,s", dreg
, 0);
1557 load_register (&icnt
, ip
, AT
, &imm_expr
);
1558 if (mask
== (int) M_DIV_3I
|| mask
== (int) M_REM_3I
)
1559 macro_build (&icnt
, NULL
, "div", "s,t", sreg
, AT
);
1561 macro_build (&icnt
, NULL
, "divu", "s,t", sreg
, AT
);
1563 if (mask
== (int) M_DIV_3I
|| mask
== (int) M_DIVU_3I
)
1564 macro_build (&icnt
, NULL
, "mflo", "d", dreg
);
1566 macro_build (&icnt
, NULL
, "mfhi", "d", dreg
);
1567 /* two implicit nop's required for mflo or mfhi */
1572 mips_emit_delays ();
1574 macro_build (&icnt
, NULL
, "divu", "s,t", sreg
, treg
);
1575 expr1
.X_add_number
= 8;
1576 macro_build (&icnt
, &expr1
, "bne", "s,t,p", treg
, 0);
1577 macro_build (&icnt
, NULL
, "nop", "", 0);
1578 macro_build (&icnt
, NULL
, "break", "c", 7);
1580 macro_build (&icnt
, NULL
, mask
== M_DIVU_3
? "mflo" : "mfhi", "d", dreg
);
1581 /* with reorder on there will be two implicit nop instructions here. */
1585 if (offset_expr
.X_seg
== &bfd_abs_section
)
1587 load_register (&icnt
, ip
, treg
, &offset_expr
);
1590 if (gp_reference (&offset_expr
))
1591 macro_build (&icnt
, &offset_expr
, "addiu", "t,r,j", treg
, GP
);
1594 macro_build_lui (&icnt
, &offset_expr
, treg
);
1595 macro_build (&icnt
, &offset_expr
, "addiu", "t,r,j", treg
, treg
);
1600 tempreg
= (breg
== treg
) ? AT
: treg
;
1601 if (offset_expr
.X_seg
== &bfd_abs_section
)
1602 load_register (&icnt
, ip
, tempreg
, &offset_expr
);
1603 else if (gp_reference (&offset_expr
))
1604 macro_build (&icnt
, &offset_expr
, "addiu", "t,r,j", tempreg
, GP
);
1607 macro_build_lui (&icnt
, &offset_expr
, tempreg
);
1608 macro_build (&icnt
, &offset_expr
, "addiu", "t,r,j", tempreg
, tempreg
);
1611 macro_build (&icnt
, NULL
, "addu", "d,v,t", treg
, tempreg
, breg
);
1649 if (breg
== treg
|| mask
== M_LWC1_AB
)
1690 if (mask
== M_LWC1_AB
|| mask
== M_SWC1_AB
)
1694 if (gp_reference (&offset_expr
))
1698 macro_build (&icnt
, &offset_expr
, s
, fmt
, treg
, GP
);
1701 macro_build (&icnt
, (expressionS
*) NULL
, "addu", "d,v,t",
1706 macro_build_lui (&icnt
, &offset_expr
, tempreg
);
1708 macro_build (&icnt
, NULL
, "addu", "d,v,t", tempreg
, tempreg
, breg
);
1710 macro_build (&icnt
, &offset_expr
, s
, fmt
, treg
, tempreg
);
1716 load_register (&icnt
, ip
, treg
, &imm_expr
);
1721 0x400370 <main>: lui $at,%hi(foo)
1722 0x400374 <main+4>: lw $v0,%lo(foo)($at)
1723 0x400378 <main+8>: lw $v1,%lo(foo+4)($at)
1728 /* FIXME: I don't think this is used at present, because the 'F'
1729 format character is not supported. When this is supported,
1730 it should use the GP register. */
1731 macro_build_lui (&icnt
, &offset_expr
, AT
);
1732 macro_build (&icnt
, &offset_expr
, "lw", "t,o(b)", treg
, AT
);
1733 offset_expr
.X_add_number
= 4;
1734 macro_build (&icnt
, &offset_expr
, "lw", "t,o(b)", treg
+ 1, AT
);
1739 0x4003a0 <main>: lwc1 $f0,-32752($gp)
1740 0x4003a4 <main+4>: lwc1 $f1,-32748($gp)
1741 0x4003a8 <main+8>: nop
1743 /* FIXME: This is nonsense. It isn't used anyhow. */
1744 sreg
= (ip
->insn_opcode
>> 11) & 0x1f; /* Fs reg */
1745 macro_build (&icnt
, &offset_expr
, "lwc1", "T,o(b)", treg
, AT
);
1746 offset_expr
.X_add_number
= 4;
1747 macro_build (&icnt
, &offset_expr
, "lwc1", "T,o(b)", treg
+ 1, AT
);
1751 /* Even on a big endian machine $fn comes before $fn+1. We have
1752 to adjust when loading from memory. */
1753 macro_build (&icnt
, &offset_expr
, "lwc1", "T,o(b)",
1754 byte_order
== LITTLE_ENDIAN
? treg
: treg
+ 1,
1756 offset_expr
.X_add_number
+= 4;
1757 macro_build (&icnt
, &offset_expr
, "lwc1", "T,o(b)",
1758 byte_order
== LITTLE_ENDIAN
? treg
+ 1 : treg
,
1764 * The MIPS assembler seems to check for X_add_number not
1765 * being double aligned and generating:
1768 * addiu at,at,%lo(foo+1)
1771 * But, the resulting address is the same after relocation so why
1772 * generate the extra instruction?
1774 if (gp_reference (&offset_expr
))
1780 macro_build (&icnt
, &offset_expr
, "addu", "d,v,t", AT
, breg
, GP
);
1786 macro_build_lui (&icnt
, &offset_expr
, AT
);
1788 macro_build (&icnt
, NULL
, "addu", "d,v,t", AT
, AT
, breg
);
1791 /* Even on a big endian machine $fn comes before $fn+1. We have
1792 to adjust when loading from memory. */
1793 macro_build (&icnt
, &offset_expr
, "lwc1", "T,o(b)",
1794 byte_order
== LITTLE_ENDIAN
? treg
: treg
+ 1,
1796 offset_expr
.X_add_number
+= 4;
1797 macro_build (&icnt
, &offset_expr
, "lwc1", "T,o(b)",
1798 byte_order
== LITTLE_ENDIAN
? treg
+ 1 : treg
,
1810 macro_build (&icnt
, &offset_expr
, s
, "t,o(b)", treg
, breg
);
1811 offset_expr
.X_add_number
= 4;
1812 macro_build (&icnt
, &offset_expr
, s
, "t,o(b)", treg
+ 1, breg
);
1833 if (gp_reference (&offset_expr
))
1841 macro_build (&icnt
, (expressionS
*) NULL
, "addu", "d,v,t",
1846 macro_build_lui (&icnt
, &offset_expr
, tempreg
);
1848 macro_build (&icnt
, NULL
, "addu", "d,v,t", tempreg
, tempreg
, breg
);
1850 macro_build (&icnt
, &offset_expr
, s
, "t,o(b)", treg
, tempreg
);
1851 offset_expr
.X_add_number
+= 4;
1852 macro_build (&icnt
, &offset_expr
, s
, "t,o(b)", treg
+ 1, tempreg
);
1858 macro_build (&icnt
, NULL
, "multu", "s,t", sreg
, treg
);
1859 macro_build (&icnt
, NULL
, "mflo", "d", dreg
);
1860 /* two implicit nop's required for mflo */
1865 * The mips assembler some times generates shifts and adds.
1866 * Im not trying to be that fancy. GCC should do this for us
1869 load_register (&icnt
, ip
, AT
, &imm_expr
);
1870 macro_build (&icnt
, NULL
, "mult", "s,t", sreg
, AT
);
1871 macro_build (&icnt
, NULL
, "mflo", "d", dreg
);
1872 /* two implicit nop's required for mflo */
1876 macro_build (&icnt
, NULL
, "subu", "d,v,t", AT
, 0, treg
);
1877 macro_build (&icnt
, NULL
, "srlv", "d,t,s", AT
, sreg
, AT
);
1878 macro_build (&icnt
, NULL
, "sllv", "d,t,s", dreg
, sreg
, treg
);
1879 macro_build (&icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
1883 macro_build (&icnt
, NULL
, "sll", "d,w,<", AT
, sreg
,
1884 imm_expr
.X_add_number
& 0x1f);
1885 macro_build (&icnt
, NULL
, "srl", "d,w,<", dreg
, sreg
,
1886 (0 - imm_expr
.X_add_number
) & 0x1f);
1887 macro_build (&icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
1891 macro_build (&icnt
, NULL
, "subu", "d,v,t", AT
, 0, treg
);
1892 macro_build (&icnt
, NULL
, "sllv", "d,t,s", AT
, sreg
, AT
);
1893 macro_build (&icnt
, NULL
, "srlv", "d,t,s", dreg
, sreg
, treg
);
1894 macro_build (&icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
1898 macro_build (&icnt
, NULL
, "srl", "d,w,<", AT
, sreg
,
1899 imm_expr
.X_add_number
& 0x1f);
1900 macro_build (&icnt
, NULL
, "sll", "d,w,<", dreg
, sreg
,
1901 (0 - imm_expr
.X_add_number
) & 0x1f);
1902 macro_build (&icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
1906 /* Even on a big endian machine $fn comes before $fn+1. We have
1907 to adjust when storing to memory. */
1908 macro_build (&icnt
, &offset_expr
, "swc1", "T,o(b)",
1909 byte_order
== LITTLE_ENDIAN
? treg
: treg
+ 1,
1911 offset_expr
.X_add_number
+= 4;
1912 macro_build (&icnt
, &offset_expr
, "swc1", "T,o(b)",
1913 byte_order
== LITTLE_ENDIAN
? treg
+ 1 : treg
,
1918 if (gp_reference (&offset_expr
))
1924 macro_build (&icnt
, (expressionS
*) NULL
, "addu", "d,v,t",
1931 macro_build_lui (&icnt
, &offset_expr
, AT
);
1933 macro_build (&icnt
, NULL
, "addu", "d,v,t", AT
, AT
, breg
);
1936 /* Even on a big endian machine $fn comes before $fn+1. We have
1937 to adjust when storing to memory. */
1938 macro_build (&icnt
, &offset_expr
, "swc1", "T,o(b)",
1939 byte_order
== LITTLE_ENDIAN
? treg
: treg
+ 1,
1941 offset_expr
.X_add_number
+= 4;
1942 macro_build (&icnt
, &offset_expr
, "swc1", "T,o(b)",
1943 byte_order
== LITTLE_ENDIAN
? treg
+ 1 : treg
,
1951 macro_build (&icnt
, &expr1
, "sltiu", "t,r,j", dreg
, treg
);
1953 macro_build (&icnt
, &expr1
, "sltiu", "t,r,j", dreg
, sreg
);
1956 macro_build (&icnt
, NULL
, "xor", "d,v,t", dreg
, sreg
, treg
);
1957 macro_build (&icnt
, &expr1
, "sltiu", "t,r,j", dreg
, dreg
);
1962 if (imm_expr
.X_add_number
== 0)
1964 macro_build (&icnt
, &expr1
, "sltiu", "t,r,j", dreg
, sreg
);
1969 as_warn ("Instruction %s: result is always false",
1971 macro_build (&icnt
, NULL
, "move", "d,s", dreg
, 0);
1974 switch (imm_expr
.X_add_number
& 0xffff8000)
1978 macro_build (&icnt
, &imm_expr
, "xori", "t,r,i", dreg
, sreg
);
1983 if (imm_expr
.X_add_number
!= -32768)
1985 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
1986 macro_build (&icnt
, &imm_expr
, "addiu", "t,r,j", dreg
, sreg
);
1993 macro_build_lui (&icnt
, &imm_expr
, AT
);
1994 if (imm_expr
.X_add_number
& 0xffff)
1995 macro_build (&icnt
, &imm_expr
, "addiu", "t,r,j", AT
, AT
);
1996 macro_build (&icnt
, NULL
, "xor", "d,v,t", dreg
, sreg
, AT
);
1999 macro_build (&icnt
, &expr1
, "sltiu", "t,r,j", dreg
, dreg
);
2004 case M_SGE
: /* sreg >= treg <==> not (sreg < treg) */
2010 macro_build (&icnt
, NULL
, s
, "d,v,t", dreg
, sreg
, treg
);
2011 macro_build (&icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
);
2014 case M_SGE_I
: /* sreg >= I <==> not (sreg < I) */
2016 if (imm_expr
.X_add_number
< 32768 && imm_expr
.X_add_number
> -32769)
2018 macro_build (&icnt
, &expr1
,
2019 mask
== M_SGE_I
? "slti" : "sltiu", "t,r,j", dreg
, sreg
);
2024 load_register (&icnt
, ip
, AT
, &imm_expr
);
2025 macro_build (&icnt
, NULL
,
2026 mask
== M_SGE_I
? "slt" : "sltu", "d,v,t", dreg
, sreg
, AT
);
2029 macro_build (&icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
);
2034 case M_SGT
: /* sreg > treg <==> treg < sreg */
2040 macro_build (&icnt
, NULL
, s
, "d,v,t", dreg
, treg
, sreg
);
2043 case M_SGT_I
: /* sreg > I <==> I < sreg */
2049 load_register (&icnt
, ip
, AT
, &imm_expr
);
2050 macro_build (&icnt
, NULL
, s
, "d,v,t", dreg
, AT
, sreg
);
2053 case M_SLE
: /* sreg <= treg <==> treg >= sreg <==> not (treg < sreg) */
2059 macro_build (&icnt
, NULL
, s
, "d,v,t", dreg
, treg
, sreg
);
2060 macro_build (&icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
);
2063 case M_SLE_I
: /* sreg <= I <==> I >= sreg <==> not (I < sreg) */
2069 load_register (&icnt
, ip
, AT
, &imm_expr
);
2070 macro_build (&icnt
, NULL
, s
, "d,v,t", dreg
, AT
, sreg
);
2071 macro_build (&icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
);
2075 if (imm_expr
.X_add_number
< 32768 && imm_expr
.X_add_number
> -32769)
2077 macro_build (&icnt
, &imm_expr
, "slti", "t,r,j", dreg
, sreg
);
2080 load_register (&icnt
, ip
, AT
, &imm_expr
);
2081 macro_build (&icnt
, NULL
, "slt", "d,v,t", dreg
, sreg
, AT
);
2085 if (imm_expr
.X_add_number
< 32768 && imm_expr
.X_add_number
> -32769)
2087 macro_build (&icnt
, &imm_expr
, "sltiu", "t,r,j", dreg
, sreg
);
2090 load_register (&icnt
, ip
, AT
, &imm_expr
);
2091 macro_build (&icnt
, NULL
, "sltu", "d,v,t", dreg
, sreg
, AT
);
2096 macro_build (&icnt
, NULL
, "sltu", "d,v,t", dreg
, 0, treg
);
2098 macro_build (&icnt
, NULL
, "sltu", "d,v,t", dreg
, 0, sreg
);
2101 macro_build (&icnt
, NULL
, "xor", "d,v,t", dreg
, sreg
, treg
);
2102 macro_build (&icnt
, NULL
, "sltu", "d,v,t", dreg
, 0, dreg
);
2107 if (imm_expr
.X_add_number
== 0)
2109 macro_build (&icnt
, NULL
, "sltu", "d,v,t", dreg
, 0, sreg
);
2114 as_warn ("Instruction %s: result is always true",
2116 macro_build (&icnt
, &expr1
, "addiu", "t,r,j", dreg
, 0);
2119 switch (imm_expr
.X_add_number
& 0xffff8000)
2123 macro_build (&icnt
, &imm_expr
, "xori", "t,r,i", dreg
, sreg
);
2128 if (imm_expr
.X_add_number
!= -32768)
2130 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
2131 macro_build (&icnt
, &imm_expr
, "addiu", "t,r,j", dreg
, sreg
);
2138 macro_build_lui (&icnt
, &imm_expr
, AT
);
2139 if (imm_expr
.X_add_number
& 0xffff)
2140 macro_build (&icnt
, &imm_expr
, "addiu", "t,r,j", AT
, AT
);
2141 macro_build (&icnt
, NULL
, "xor", "d,v,t", dreg
, sreg
, AT
);
2144 macro_build (&icnt
, NULL
, "sltu", "d,v,t", dreg
, 0, dreg
);
2150 if (imm_expr
.X_add_number
< 32768 && imm_expr
.X_add_number
> -32768)
2152 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
2153 macro_build (&icnt
, &imm_expr
, "addi", "t,r,j", dreg
, sreg
);
2156 load_register (&icnt
, ip
, AT
, &imm_expr
);
2157 macro_build (&icnt
, NULL
, "sub", "d,v,t", dreg
, sreg
, AT
);
2161 if (imm_expr
.X_add_number
< 32768 && imm_expr
.X_add_number
> -32768)
2163 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
2164 macro_build (&icnt
, &imm_expr
, "addiu", "t,r,j", dreg
, sreg
);
2167 load_register (&icnt
, ip
, AT
, &imm_expr
);
2168 macro_build (&icnt
, NULL
, "subu", "d,v,t", dreg
, sreg
, AT
);
2173 sreg
= (ip
->insn_opcode
>> 11) & 0x1f; /* floating reg */
2174 dreg
= (ip
->insn_opcode
>> 06) & 0x1f; /* floating reg */
2177 * Is the double cfc1 instruction a bug in the mips assembler;
2178 * or is there a reason for it?
2180 mips_emit_delays ();
2182 macro_build (&icnt
, NULL
, "cfc1", "t,G", treg
, 31);
2183 macro_build (&icnt
, NULL
, "cfc1", "t,G", treg
, 31);
2184 macro_build (&icnt
, NULL
, "nop", "");
2185 expr1
.X_add_number
= 3;
2186 macro_build (&icnt
, &expr1
, "ori", "t,r,i", AT
, treg
);
2187 expr1
.X_add_number
= 2;
2188 macro_build (&icnt
, &expr1
, "xori", "t,r,i", AT
, AT
);
2189 macro_build (&icnt
, NULL
, "ctc1", "t,G", AT
, 31);
2190 macro_build (&icnt
, NULL
, "nop", "");
2191 macro_build (&icnt
, NULL
,
2192 mask
== M_TRUNCWD
? "cvt.w.d" : "cvt.w.s", "D,S", dreg
, sreg
);
2193 macro_build (&icnt
, NULL
, "ctc1", "t,G", treg
, 31);
2194 macro_build (&icnt
, NULL
, "nop", "");
2204 /* avoid load delay */
2205 offset_expr
.X_add_number
+= 1;
2206 macro_build (&icnt
, &offset_expr
, s
, "t,o(b)", treg
, breg
);
2207 offset_expr
.X_add_number
-= 1;
2208 macro_build (&icnt
, &offset_expr
, "lbu", "t,o(b)", AT
, breg
);
2209 macro_build (&icnt
, NULL
, "sll", "d,w,<", treg
, treg
, 8);
2210 macro_build (&icnt
, NULL
, "or", "d,v,t", treg
, treg
, AT
);
2214 /* does this work on a big endian machine? */
2215 offset_expr
.X_add_number
+= 3;
2216 macro_build (&icnt
, &offset_expr
, "lwl", "t,o(b)", treg
, breg
);
2217 offset_expr
.X_add_number
-= 3;
2218 macro_build (&icnt
, &offset_expr
, "lwr", "t,o(b)", treg
, breg
);
2224 if (offset_expr
.X_seg
== &bfd_abs_section
)
2225 load_register (&icnt
, ip
, AT
, &offset_expr
);
2226 else if (gp_reference (&offset_expr
))
2227 macro_build (&icnt
, &offset_expr
, "addiu", "t,r,j", AT
, GP
);
2230 macro_build_lui (&icnt
, &offset_expr
, AT
);
2231 macro_build (&icnt
, &offset_expr
, "addiu", "t,r,j", AT
, AT
);
2233 if (mask
== M_ULW_A
)
2235 expr1
.X_add_number
= 3;
2236 macro_build (&icnt
, &expr1
, "lwl", "t,o(b)", treg
, AT
);
2237 imm_expr
.X_add_number
= 0;
2238 macro_build (&icnt
, &expr1
, "lwr", "t,o(b)", treg
, AT
);
2242 macro_build (&icnt
, &expr1
,
2243 mask
== M_ULH_A
? "lb" : "lbu", "t,o(b)", treg
, AT
);
2244 imm_expr
.X_add_number
= 0;
2245 macro_build (&icnt
, &expr1
, "lbu", "t,o(b)", AT
, AT
);
2246 macro_build (&icnt
, NULL
, "sll", "d,w,<", treg
, treg
, 8);
2247 macro_build (&icnt
, NULL
, "or", "d,v,t", treg
, treg
, AT
);
2252 macro_build (&icnt
, &offset_expr
, "sb", "t,o(b)", treg
, breg
);
2253 macro_build (&icnt
, NULL
, "srl", "d,w,<", AT
, treg
, 8);
2254 offset_expr
.X_add_number
+= 1;
2255 macro_build (&icnt
, &offset_expr
, "sb", "t,o(b)", AT
, breg
);
2259 offset_expr
.X_add_number
+= 3;
2260 macro_build (&icnt
, &offset_expr
, "swl", "t,o(b)", treg
, breg
);
2261 offset_expr
.X_add_number
-= 3;
2262 macro_build (&icnt
, &offset_expr
, "swr", "t,o(b)", treg
, breg
);
2267 if (offset_expr
.X_seg
== &bfd_abs_section
)
2268 load_register (&icnt
, ip
, AT
, &offset_expr
);
2269 else if (gp_reference (&offset_expr
))
2270 macro_build (&icnt
, &offset_expr
, "addiu", "t,r,j", AT
, GP
);
2273 macro_build_lui (&icnt
, &offset_expr
, AT
);
2274 macro_build (&icnt
, &offset_expr
, "addiu", "t,r,j", AT
, AT
);
2276 if (mask
== M_USW_A
)
2278 expr1
.X_add_number
= 3;
2279 macro_build (&icnt
, &expr1
, "swl", "t,o(b)", treg
, AT
);
2280 expr1
.X_add_number
= 0;
2281 macro_build (&icnt
, &expr1
, "swr", "t,o(b)", treg
, AT
);
2285 expr1
.X_add_number
= 0;
2286 macro_build (&icnt
, &expr1
, "sb", "t,o(b)", treg
, AT
);
2287 macro_build (&icnt
, NULL
, "srl", "d,w,<", treg
, treg
, 8);
2288 expr1
.X_add_number
= 1;
2289 macro_build (&icnt
, &expr1
, "sb", "t,o(b)", treg
, AT
);
2290 expr1
.X_add_number
= 0;
2291 macro_build (&icnt
, &expr1
, "lbu", "t,o(b)", AT
, AT
);
2292 macro_build (&icnt
, NULL
, "sll", "d,w,<", treg
, treg
, 8);
2293 macro_build (&icnt
, NULL
, "or", "d,v,t", treg
, treg
, AT
);
2298 as_bad ("Macro %s not implemented yet", ip
->insn_mo
->name
);
2301 as_warn ("Macro used $at after \".set noat\"");
2306 This routine assembles an instruction into its binary format. As a side
2307 effect it sets one of the global variables imm_reloc or offset_reloc to the
2308 type of relocation to do if one of the operands is an address expression.
2313 struct mips_cl_insn
*ip
;
2318 struct mips_opcode
*insn
;
2321 unsigned int lastregno
= 0;
2326 for (s
= str
; islower (*s
) || (*s
>= '0' && *s
<= '3') || *s
== '.'; ++s
)
2338 as_warn ("Unknown opcode: `%s'", str
);
2341 if ((insn
= (struct mips_opcode
*) hash_find (op_hash
, str
)) == NULL
)
2343 as_warn ("`%s' not in hash table.", str
);
2344 insn_error
= "ERROR: Unrecognized opcode";
2350 assert (strcmp (insn
->name
, str
) == 0);
2352 ip
->insn_opcode
= insn
->match
;
2353 for (args
= insn
->args
;; ++args
)
2359 case '\0': /* end of args */
2372 ip
->insn_opcode
|= lastregno
<< 21;
2377 ip
->insn_opcode
|= lastregno
<< 16;
2381 ip
->insn_opcode
|= lastregno
<< 11;
2387 /* handle optional base register.
2388 Either the base register is omitted or
2389 we must have a left paren. */
2390 /* this is dependent on the next operand specifier
2391 is a 'b' for base register */
2392 assert (args
[1] == 'b');
2396 case ')': /* these must match exactly */
2401 case '<': /* must be at least one digit */
2403 * According to the manual, if the shift amount is greater
2404 * than 31 or less than 0 the the shift amount should be
2405 * mod 32. In reality the mips assembler issues an error.
2406 * We issue a warning and do the mod.
2408 my_getExpression (&imm_expr
, s
);
2409 check_absolute_expr (ip
, &imm_expr
);
2410 if ((unsigned long) imm_expr
.X_add_number
> 31)
2412 as_warn ("Improper shift amount (%d)",
2413 imm_expr
.X_add_number
);
2414 imm_expr
.X_add_number
= imm_expr
.X_add_number
% 32;
2416 ip
->insn_opcode
|= imm_expr
.X_add_number
<< 6;
2417 imm_expr
.X_seg
= absent_section
;
2421 case 'c': /* break code */
2422 my_getExpression (&imm_expr
, s
);
2423 check_absolute_expr (ip
, &imm_expr
);
2424 if ((unsigned) imm_expr
.X_add_number
> 1023)
2425 as_warn ("Illegal break code (%d)", imm_expr
.X_add_number
);
2426 ip
->insn_opcode
|= imm_expr
.X_add_number
<< 16;
2427 imm_expr
.X_seg
= absent_section
;
2431 case 'B': /* syscall code */
2432 my_getExpression (&imm_expr
, s
);
2433 check_absolute_expr (ip
, &imm_expr
);
2434 if ((unsigned) imm_expr
.X_add_number
> 0xfffff)
2435 as_warn ("Illegal syscall code (%d)", imm_expr
.X_add_number
);
2436 ip
->insn_opcode
|= imm_expr
.X_add_number
<< 6;
2437 imm_expr
.X_seg
= absent_section
;
2441 case 'b': /* base register */
2442 case 'd': /* destination register */
2443 case 's': /* source register */
2444 case 't': /* target register */
2445 case 'r': /* both target and source */
2446 case 'v': /* both dest and source */
2447 case 'w': /* both dest and target */
2448 case 'E': /* coprocessor target register */
2449 case 'G': /* coprocessor destination register */
2463 while (isdigit (*s
));
2465 else if (s
[1] == 'f' && s
[2] == 'p')
2470 else if (s
[1] == 's' && s
[2] == 'p')
2475 else if (s
[1] == 'g' && s
[2] == 'p')
2480 else if (s
[1] == 'a' && s
[2] == 't')
2488 as_bad ("Invalid register number (%d)", regno
);
2489 if (regno
== AT
&& !mips_noat
)
2490 as_warn ("Used $at without \".set noat\"");
2496 if (c
== 'r' || c
== 'v' || c
== 'w')
2509 ip
->insn_opcode
|= regno
<< 21;
2513 ip
->insn_opcode
|= regno
<< 11;
2518 ip
->insn_opcode
|= regno
<< 16;
2528 ip
->insn_opcode
|= lastregno
<< 21;
2531 ip
->insn_opcode
|= lastregno
<< 16;
2536 case 'D': /* floating point destination register */
2537 case 'S': /* floating point source register */
2538 case 'T': /* floating point target register */
2542 if (s
[0] == '$' && s
[1] == 'f' && isdigit (s
[2]))
2552 while (isdigit (*s
));
2555 as_bad ("Invalid float register number (%d)", regno
);
2558 !(strcmp (str
, "mtc1") == 0 ||
2559 strcmp (str
, "mfc1") == 0 ||
2560 strcmp (str
, "lwc1") == 0 ||
2561 strcmp (str
, "swc1") == 0))
2562 as_warn ("Float register should be even, was %d",
2570 if (c
== 'V' || c
== 'W')
2580 ip
->insn_opcode
|= regno
<< 6;
2584 ip
->insn_opcode
|= regno
<< 11;
2588 ip
->insn_opcode
|= regno
<< 16;
2596 ip
->insn_opcode
|= lastregno
<< 11;
2599 ip
->insn_opcode
|= lastregno
<< 16;
2605 my_getExpression (&imm_expr
, s
);
2606 check_absolute_expr (ip
, &imm_expr
);
2611 my_getExpression (&offset_expr
, s
);
2612 imm_reloc
= BFD_RELOC_32
;
2617 as_bad ("Floating point constants only implemented for pseudo ops.");
2620 case 'i': /* 16 bit unsigned immediate */
2621 case 'j': /* 16 bit signed immediate */
2622 imm_reloc
= BFD_RELOC_LO16
;
2623 c
= my_getSmallExpression (&imm_expr
, s
);
2628 if (imm_expr
.X_seg
== &bfd_abs_section
)
2629 imm_expr
.X_add_number
=
2630 (imm_expr
.X_add_number
>> 16) & 0xffff;
2632 imm_reloc
= BFD_RELOC_HI16_S
;
2634 imm_reloc
= BFD_RELOC_HI16
;
2638 check_absolute_expr (ip
, &imm_expr
);
2641 if ((unsigned long) imm_expr
.X_add_number
> 65535)
2643 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
2644 !strcmp (insn
->name
, insn
[1].name
))
2646 as_bad ("16 bit expression not in range 0..65535");
2651 if (imm_expr
.X_add_number
< -32768 ||
2652 imm_expr
.X_add_number
> 32767)
2654 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
2655 !strcmp (insn
->name
, insn
[1].name
))
2657 as_bad ("16 bit expression not in range -32768..32767");
2663 case 'o': /* 16 bit offset */
2664 c
= my_getSmallExpression (&offset_expr
, s
);
2666 * If this value won't fit into a 16 bit offset, then
2667 * go find a macro that will generate the 32 bit offset
2670 if ((offset_expr
.X_add_symbol
2671 && offset_expr
.X_seg
!= &bfd_abs_section
)
2672 || offset_expr
.X_subtract_symbol
2673 || offset_expr
.X_add_number
> 32767
2674 || offset_expr
.X_add_number
< -32768)
2677 offset_reloc
= BFD_RELOC_LO16
;
2678 if (c
== 'h' || c
== 'H')
2679 offset_expr
.X_add_number
=
2680 (offset_expr
.X_add_number
>> 16) & 0xffff;
2684 case 'p': /* pc relative offset */
2685 offset_reloc
= BFD_RELOC_16_PCREL_S2
;
2686 my_getExpression (&offset_expr
, s
);
2690 case 'u': /* upper 16 bits */
2691 c
= my_getSmallExpression (&imm_expr
, s
);
2692 if ((unsigned long) imm_expr
.X_add_number
> 65535)
2693 as_bad ("lui expression not in range 0..65535");
2694 imm_reloc
= BFD_RELOC_LO16
;
2699 if (imm_expr
.X_seg
== &bfd_abs_section
)
2700 imm_expr
.X_add_number
=
2701 (imm_expr
.X_add_number
>> 16) & 0xffff;
2703 imm_reloc
= BFD_RELOC_HI16_S
;
2705 imm_reloc
= BFD_RELOC_HI16
;
2711 case 'a': /* 26 bit address */
2712 my_getExpression (&offset_expr
, s
);
2714 offset_reloc
= BFD_RELOC_MIPS_JMP
;
2718 fprintf (stderr
, "bad char = '%c'\n", *args
);
2723 /* Args don't match. */
2724 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
2725 !strcmp (insn
->name
, insn
[1].name
))
2731 insn_error
= "ERROR: Illegal operands";
2740 my_getSmallExpression (ep
, str
)
2751 ((str
[1] == 'h' && str
[2] == 'i')
2752 || (str
[1] == 'H' && str
[2] == 'I')
2753 || (str
[1] == 'l' && str
[2] == 'o'))
2765 * A small expression may be followed by a base register.
2766 * Scan to the end of this operand, and then back over a possible
2767 * base register. Then scan the small expression up to that
2768 * point. (Based on code in sparc.c...)
2770 for (sp
= str
; *sp
&& *sp
!= ','; sp
++)
2772 if (sp
- 4 >= str
&& sp
[-1] == RP
)
2774 if (isdigit (sp
[-2]))
2776 for (sp
-= 3; sp
>= str
&& isdigit (*sp
); sp
--)
2778 if (*sp
== '$' && sp
> str
&& sp
[-1] == LP
)
2784 else if (sp
- 5 >= str
2787 && ((sp
[-3] == 'f' && sp
[-2] == 'p')
2788 || (sp
[-3] == 's' && sp
[-2] == 'p')
2789 || (sp
[-3] == 'g' && sp
[-2] == 'p')
2790 || (sp
[-3] == 'a' && sp
[-2] == 't')))
2796 /* no expression means zero offset */
2799 /* %xx(reg) is an error */
2800 ep
->X_seg
= absent_section
;
2805 ep
->X_seg
= &bfd_abs_section
;
2808 ep
->X_add_symbol
= NULL
;
2809 ep
->X_subtract_symbol
= NULL
;
2810 ep
->X_add_number
= 0;
2815 my_getExpression (ep
, str
);
2822 my_getExpression (ep
, str
);
2823 return c
; /* => %hi or %lo encountered */
2827 my_getExpression (ep
, str
)
2834 save_in
= input_line_pointer
;
2835 input_line_pointer
= str
;
2836 seg
= expression (ep
);
2837 expr_end
= input_line_pointer
;
2838 input_line_pointer
= save_in
;
2841 /* Turn a string in input_line_pointer into a floating point constant
2842 of type type, and store the appropriate bytes in *litP. The number
2843 of LITTLENUMS emitted is stored in *sizeP . An error message is
2844 returned, or NULL on OK. */
2847 md_atof (type
, litP
, sizeP
)
2853 LITTLENUM_TYPE words
[4];
2869 return "bad call to md_atof";
2872 t
= atof_ieee (input_line_pointer
, type
, words
);
2874 input_line_pointer
= t
;
2878 if (byte_order
== LITTLE_ENDIAN
)
2880 for (i
= prec
- 1; i
>= 0; i
--)
2882 md_number_to_chars (litP
, (valueT
) words
[i
], 2);
2888 for (i
= 0; i
< prec
; i
++)
2890 md_number_to_chars (litP
, (valueT
) words
[i
], 2);
2899 md_number_to_chars (buf
, val
, n
)
2951 md_parse_option (argP
, cntP
, vecP
)
2956 /* Accept -nocpp but ignore it. */
2957 if (!strcmp (*argP
, "nocpp"))
2963 if (strcmp (*argP
, "EL") == 0
2964 || strcmp (*argP
, "EB") == 0)
2966 /* FIXME: This breaks -L -EL. */
2975 if ((*argP
)[1] != '\0')
2976 g_switch_value
= atoi (*argP
+ 1);
2979 **vecP
= (char *) NULL
;
2982 g_switch_value
= atoi (**vecP
);
2985 as_warn ("Number expected after -G");
2990 return 1; /* pretend you parsed the character */
2994 md_pcrel_from (fixP
)
2997 /* return the address of the delay slot */
2998 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
3002 md_apply_fix (fixP
, valueP
)
3009 assert (fixP
->fx_size
== 4);
3012 fixP
->fx_addnumber
= value
; /* Remember value for tc_gen_reloc */
3014 switch (fixP
->fx_r_type
)
3017 case BFD_RELOC_MIPS_JMP
:
3018 case BFD_RELOC_HI16
:
3019 case BFD_RELOC_HI16_S
:
3020 case BFD_RELOC_LO16
:
3021 case BFD_RELOC_MIPS_GPREL
:
3022 /* Nothing needed to do. The value comes from the reloc entry */
3025 case BFD_RELOC_16_PCREL_S2
:
3027 * We need to save the bits in the instruction since fixup_segment()
3028 * might be deleting the relocation entry (i.e., a branch within
3029 * the current segment).
3032 as_warn ("Branch to odd address (%x)", value
);
3034 if ((value
& ~0xFFFF) && (value
& ~0xFFFF) != (-1 & ~0xFFFF))
3035 as_bad ("Relocation overflow");
3037 /* update old instruction data */
3038 buf
= (unsigned char *) (fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
);
3042 insn
= (buf
[3] << 24) | (buf
[2] << 16) | (buf
[1] << 8) | buf
[0];
3046 insn
= (buf
[0] << 24) | (buf
[1] << 16) | (buf
[2] << 8) | buf
[3];
3053 insn
|= value
& 0xFFFF;
3054 md_number_to_chars ((char *) buf
, insn
, 4);
3068 const struct mips_opcode
*p
;
3069 int treg
, sreg
, dreg
, shamt
;
3074 for (i
= 0; i
< NUMOPCODES
; ++i
)
3076 p
= &mips_opcodes
[i
];
3077 if (((oc
& p
->mask
) == p
->match
) && (p
->pinfo
!= INSN_MACRO
))
3079 printf ("%08lx %s\t", oc
, p
->name
);
3080 treg
= (oc
>> 16) & 0x1f;
3081 sreg
= (oc
>> 21) & 0x1f;
3082 dreg
= (oc
>> 11) & 0x1f;
3083 shamt
= (oc
>> 6) & 0x1f;
3085 for (args
= p
->args
;; ++args
)
3096 printf ("%c", *args
);
3100 assert (treg
== sreg
);
3101 printf ("$%d,$%d", treg
, sreg
);
3106 printf ("$%d", dreg
);
3111 printf ("$%d", treg
);
3116 printf ("$%d", sreg
);
3120 printf ("0x%08lx", oc
& 0x1ffffff);
3131 printf ("$%d", shamt
);
3142 printf ("%08lx UNDEFINED\n", oc
);
3153 name
= input_line_pointer
;
3154 c
= get_symbol_end ();
3155 p
= (symbolS
*) symbol_find_or_make (name
);
3156 *input_line_pointer
= c
;
3161 get_optional_absolute_expression ()
3166 s
= expression (&exp
);
3167 if (!(s
== &bfd_abs_section
|| s
== big_section
|| s
== absent_section
))
3169 as_bad ("Bad Absolute Expression.");
3171 return exp
.X_add_number
;
3174 /* Align the current frag to a given power of two. The MIPS assembler
3175 also automatically adjusts any preceding label. */
3178 mips_align (to
, fill
)
3182 mips_emit_delays ();
3183 frag_align (to
, fill
);
3184 record_alignment (now_seg
, to
);
3185 if (insn_label
!= NULL
)
3187 assert (S_GET_SEGMENT (insn_label
) == now_seg
);
3188 insn_label
->sy_frag
= frag_now
;
3189 S_SET_VALUE (insn_label
, frag_now_fix ());
3193 /* Align to a given power of two. .align 0 turns off the automatic
3194 alignment used by the data creating pseudo-ops. */
3201 register long temp_fill
;
3202 long max_alignment
= 15;
3206 o Note that the assembler pulls down any immediately preceeding label
3207 to the aligned address.
3208 o It's not documented but auto alignment is reinstated by
3209 a .align pseudo instruction.
3210 o Note also that after auto alignment is turned off the mips assembler
3211 issues an error on attempt to assemble an improperly aligned data item.
3216 temp
= get_absolute_expression ();
3217 if (temp
> max_alignment
)
3218 as_bad ("Alignment too large: %d. assumed.", temp
= max_alignment
);
3221 as_warn ("Alignment negative: 0 assumed.");
3224 if (*input_line_pointer
== ',')
3226 input_line_pointer
++;
3227 temp_fill
= get_absolute_expression ();
3234 mips_align (temp
, (int) temp_fill
);
3241 demand_empty_rest_of_line ();
3244 /* Handle .ascii and .asciiz. This just calls stringer and forgets
3245 that there was a previous instruction. */
3248 s_stringer (append_zero
)
3251 mips_emit_delays ();
3252 stringer (append_zero
);
3261 mips_emit_delays ();
3270 subseg_new (".rdata", (subsegT
) get_absolute_expression ());
3271 demand_empty_rest_of_line ();
3280 #ifdef BFD_ASSEMBLER
3281 subseg_set (bss_section
, (subsegT
) get_absolute_expression ());
3283 subseg_new (bss_section
, (subsegT
) get_absolute_expression ());
3285 demand_empty_rest_of_line ();
3289 subseg_new (".sdata", (subsegT
) get_absolute_expression ());
3290 demand_empty_rest_of_line ();
3293 as_bad ("Global pointers not supported; recompile -G 0");
3294 demand_empty_rest_of_line ();
3305 mips_emit_delays ();
3306 if (log_size
> 0 && auto_align
)
3307 mips_align (log_size
, 0);
3308 cons (1 << log_size
);
3315 as_fatal ("Encountered `.err', aborting assembly");
3325 symbolP
= get_symbol ();
3326 if (*input_line_pointer
== ',')
3327 input_line_pointer
++;
3328 size
= get_optional_absolute_expression ();
3329 S_SET_VALUE (symbolP
, size
);
3330 S_SET_EXTERNAL (symbolP
);
3333 /* ECOFF needs to distinguish a .comm symbol from a .extern symbol,
3334 so we use an additional ECOFF specific field. */
3335 symbolP
->ecoff_undefined
= 1;
3343 mips_emit_delays ();
3358 if (strcmp (input_line_pointer
, "O1") != 0
3359 && strcmp (input_line_pointer
, "O2") != 0)
3360 as_warn ("Unrecognized option");
3361 demand_empty_rest_of_line ();
3368 char *name
= input_line_pointer
, ch
;
3370 while (!is_end_of_line
[(unsigned char) *input_line_pointer
])
3371 input_line_pointer
++;
3372 ch
= *input_line_pointer
;
3373 *input_line_pointer
= '\0';
3375 if (strcmp (name
, "reorder") == 0)
3379 else if (strcmp (name
, "noreorder") == 0)
3381 mips_emit_delays ();
3384 else if (strcmp (name
, "at") == 0)
3388 else if (strcmp (name
, "noat") == 0)
3392 else if (strcmp (name
, "macro") == 0)
3394 mips_warn_about_macros
= 0;
3396 else if (strcmp (name
, "nomacro") == 0)
3398 if (mips_noreorder
== 0)
3399 as_bad ("`noreorder' must be set before `nomacro'");
3400 mips_warn_about_macros
= 1;
3402 else if (strcmp (name
, "move") == 0 || strcmp (name
, "novolatile") == 0)
3406 else if (strcmp (name
, "nomove") == 0 || strcmp (name
, "volatile") == 0)
3410 else if (strcmp (name
, "bopt") == 0)
3414 else if (strcmp (name
, "nobopt") == 0)
3420 as_warn ("Tried to set unrecognized symbol: %s\n", name
);
3422 *input_line_pointer
= ch
;
3423 demand_empty_rest_of_line ();
3426 /* The same as the usual .space directive, except that we have to
3427 forget about any previous instruction. */
3430 s_mips_space (param
)
3433 mips_emit_delays ();
3443 if (*input_line_pointer
++ != '$')
3445 as_warn ("expected `$'");
3448 if (isdigit ((unsigned char) *input_line_pointer
))
3450 reg
= get_absolute_expression ();
3451 if (reg
< 0 || reg
>= 32)
3453 as_warn ("Bad register number");
3459 if (strncmp (input_line_pointer
, "fp", 2) == 0)
3461 else if (strncmp (input_line_pointer
, "sp", 2) == 0)
3463 else if (strncmp (input_line_pointer
, "gp", 2) == 0)
3465 else if (strncmp (input_line_pointer
, "at", 2) == 0)
3469 as_warn ("Unrecognized register name");
3472 input_line_pointer
+= 2;
3478 * Translate internal representation of relocation info to BFD target format.
3481 tc_gen_reloc (section
, fixp
)
3487 reloc
= (arelent
*) xmalloc (sizeof (arelent
));
3488 assert (reloc
!= 0);
3490 reloc
->sym_ptr_ptr
= &fixp
->fx_addsy
->bsym
;
3491 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
3492 if (fixp
->fx_pcrel
== 0)
3493 reloc
->addend
= fixp
->fx_addnumber
;
3498 reloc
->addend
= -reloc
->address
;
3500 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, fixp
->fx_r_type
);
3501 assert (reloc
->howto
!= 0);
3506 /* should never be called */
3508 md_section_align (seg
, addr
)
3512 int align
= bfd_get_section_alignment (stdoutput
, seg
);
3514 return ((addr
+ (1 << align
) - 1) & (-1 << align
));
3518 md_estimate_size_before_relax (fragP
, segtype
)
3522 as_fatal ("md_estimate_size_before_relax");
3524 } /* md_estimate_size_before_relax() */
3526 /* This function is called whenever a label is defined. It is used
3527 when handling branch delays; if a branch has a label, we assume we
3531 mips_define_label (sym
)
3539 /* These functions should really be defined by the object file format,
3540 since they are related to debugging information. However, this
3541 code has to work for the a.out format, which does not define them,
3542 so we provide simple versions here. These don't actually generate
3543 any debugging information, but they do simple checking and someday
3544 somebody may make them useful. */
3548 struct loc
*loc_next
;
3549 unsigned long loc_fileno
;
3550 unsigned long loc_lineno
;
3551 unsigned long loc_offset
;
3552 unsigned short loc_delta
;
3553 unsigned short loc_count
;
3562 struct proc
*proc_next
;
3563 struct symbol
*proc_isym
;
3564 struct symbol
*proc_end
;
3565 unsigned long proc_reg_mask
;
3566 unsigned long proc_reg_offset
;
3567 unsigned long proc_fpreg_mask
;
3568 unsigned long proc_fpreg_offset
;
3569 unsigned long proc_frameoffset
;
3570 unsigned long proc_framereg
;
3571 unsigned long proc_pcreg
;
3573 struct file
*proc_file
;
3580 struct file
*file_next
;
3581 unsigned long file_fileno
;
3582 struct symbol
*file_symbol
;
3583 struct symbol
*file_end
;
3584 struct proc
*file_proc
;
3589 static struct obstack proc_frags
;
3590 static procS
*proc_lastP
;
3591 static procS
*proc_rootP
;
3592 static int numprocs
;
3597 obstack_begin (&proc_frags
, 0x2000);
3603 /* check for premature end, nesting errors, etc */
3604 if (proc_lastP
&& proc_lastP
->proc_end
== NULL
)
3605 as_warn ("missing `.end' at end of assembly");
3608 extern char hex_value
[];
3616 if (*input_line_pointer
== '-')
3618 ++input_line_pointer
;
3621 if (!isdigit (*input_line_pointer
))
3622 as_bad ("Expected simple number.");
3623 if (input_line_pointer
[0] == '0')
3625 if (input_line_pointer
[1] == 'x')
3627 input_line_pointer
+= 2;
3628 while (isxdigit (*input_line_pointer
))
3631 val
|= hex_value
[(int) *input_line_pointer
++];
3633 return negative
? -val
: val
;
3637 ++input_line_pointer
;
3638 while (isdigit (*input_line_pointer
))
3641 val
|= *input_line_pointer
++ - '0';
3643 return negative
? -val
: val
;
3646 if (!isdigit (*input_line_pointer
))
3648 printf (" *input_line_pointer == '%c' 0x%02x\n",
3649 *input_line_pointer
, *input_line_pointer
);
3650 as_warn ("Invalid number");
3653 while (isdigit (*input_line_pointer
))
3656 val
+= *input_line_pointer
++ - '0';
3658 return negative
? -val
: val
;
3661 /* The .file directive; just like the usual .file directive, but there
3662 is an initial number which is the ECOFF file index. */
3670 line
= get_number ();
3675 /* The .end directive. */
3683 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
3686 demand_empty_rest_of_line ();
3690 if (now_seg
!= text_section
)
3691 as_warn (".end not in text section");
3694 as_warn (".end and no .ent seen yet.");
3700 assert (S_GET_NAME (p
));
3701 if (strcmp (S_GET_NAME (p
), S_GET_NAME (proc_lastP
->proc_isym
)))
3702 as_warn (".end symbol does not match .ent symbol.");
3705 proc_lastP
->proc_end
= (symbolS
*) 1;
3708 /* The .aent and .ent directives. */
3718 symbolP
= get_symbol ();
3719 if (*input_line_pointer
== ',')
3720 input_line_pointer
++;
3721 if (isdigit (*input_line_pointer
) || *input_line_pointer
== '-')
3722 number
= get_number ();
3723 if (now_seg
!= text_section
)
3724 as_warn (".ent or .aent not in text section.");
3726 if (!aent
&& proc_lastP
&& proc_lastP
->proc_end
== NULL
)
3727 as_warn ("missing `.end'");
3731 procP
= (procS
*) obstack_alloc (&proc_frags
, sizeof (*procP
));
3732 procP
->proc_isym
= symbolP
;
3733 procP
->proc_reg_mask
= 0;
3734 procP
->proc_reg_offset
= 0;
3735 procP
->proc_fpreg_mask
= 0;
3736 procP
->proc_fpreg_offset
= 0;
3737 procP
->proc_frameoffset
= 0;
3738 procP
->proc_framereg
= 0;
3739 procP
->proc_pcreg
= 0;
3740 procP
->proc_end
= NULL
;
3741 procP
->proc_next
= NULL
;
3743 proc_lastP
->proc_next
= procP
;
3749 demand_empty_rest_of_line ();
3752 /* The .frame directive. */
3765 frame_reg
= tc_get_register ();
3766 if (*input_line_pointer
== ',')
3767 input_line_pointer
++;
3768 frame_off
= get_optional_absolute_expression ();
3769 if (*input_line_pointer
== ',')
3770 input_line_pointer
++;
3771 pcreg
= tc_get_register ();
3774 assert (proc_rootP
);
3775 proc_rootP
->proc_framereg
= frame_reg
;
3776 proc_rootP
->proc_frameoffset
= frame_off
;
3777 proc_rootP
->proc_pcreg
= pcreg
;
3778 /* bob macho .frame */
3780 /* We don't have to write out a frame stab for unoptimized code. */
3781 if (!(frame_reg
== 30 && frame_off
== 0))
3784 as_warn ("No .ent for .frame to use.");
3785 (void) sprintf (str
, "R%d;%d", frame_reg
, frame_off
);
3786 symP
= symbol_new (str
, N_VFP
, 0, frag_now
);
3787 S_SET_TYPE (symP
, N_RMASK
);
3788 S_SET_OTHER (symP
, 0);
3789 S_SET_DESC (symP
, 0);
3790 symP
->sy_forward
= proc_lastP
->proc_isym
;
3791 /* bob perhaps I should have used pseudo set */
3793 demand_empty_rest_of_line ();
3797 /* The .fmask and .mask directives. */
3804 char str
[100], *strP
;
3810 mask
= get_number ();
3811 if (*input_line_pointer
== ',')
3812 input_line_pointer
++;
3813 off
= get_absolute_expression ();
3815 /* bob only for coff */
3816 assert (proc_rootP
);
3817 if (reg_type
== 'F')
3819 proc_rootP
->proc_fpreg_mask
= mask
;
3820 proc_rootP
->proc_fpreg_offset
= off
;
3824 proc_rootP
->proc_reg_mask
= mask
;
3825 proc_rootP
->proc_reg_offset
= off
;
3828 /* bob macho .mask + .fmask */
3830 /* We don't have to write out a mask stab if no saved regs. */
3834 as_warn ("No .ent for .mask to use.");
3836 for (i
= 0; i
< 32; i
++)
3840 sprintf (strP
, "%c%d,", reg_type
, i
);
3841 strP
+= strlen (strP
);
3845 sprintf (strP
, ";%d,", off
);
3846 symP
= symbol_new (str
, N_RMASK
, 0, frag_now
);
3847 S_SET_TYPE (symP
, N_RMASK
);
3848 S_SET_OTHER (symP
, 0);
3849 S_SET_DESC (symP
, 0);
3850 symP
->sy_forward
= proc_lastP
->proc_isym
;
3851 /* bob perhaps I should have used pseudo set */
3856 /* The .loc directive. */
3867 assert (now_seg
== text_section
);
3869 lineno
= get_number ();
3870 addroff
= obstack_next_free (&frags
) - frag_now
->fr_literal
;
3872 symbolP
= symbol_new ("", N_SLINE
, addroff
, frag_now
);
3873 S_SET_TYPE (symbolP
, N_SLINE
);
3874 S_SET_OTHER (symbolP
, 0);
3875 S_SET_DESC (symbolP
, lineno
);
3876 symbolP
->sy_segment
= now_seg
;
3880 #endif /* ! defined (OBJ_ECOFF) */