1 /* tc-mips.c -- assemble code for a MIPS chip.
2 Copyright (C) 1993, 1995, 1996 Free Software Foundation, Inc.
3 Contributed by the OSF and Ralph Campbell.
4 Written by Keith Knowles and Ralph Campbell, working independently.
5 Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus
8 This file is part of GAS.
10 GAS is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 2, or (at your option)
15 GAS is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with GAS; see the file COPYING. If not, write to the Free
22 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
38 #include "opcode/mips.h"
41 /* Clean up namespace so we can include obj-elf.h too. */
42 static int mips_output_flavor () { return OUTPUT_FLAVOR
; }
43 #undef OBJ_PROCESS_STAB
49 #undef TARGET_SYMBOL_FIELDS
51 #undef obj_frob_symbol
53 #undef obj_sec_sym_ok_for_reloc
56 /* Fix any of them that we actually care about. */
58 #define OUTPUT_FLAVOR mips_output_flavor()
65 #ifndef ECOFF_DEBUGGING
66 #define NO_ECOFF_DEBUGGING
67 #define ECOFF_DEBUGGING 0
72 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
73 static char *mips_regmask_frag
;
77 #define PIC_CALL_REG 25
85 extern int target_big_endian
;
87 /* 1 is we should use the 64 bit MIPS ELF ABI, 0 if we should use the
88 32 bit ABI. This has no meaning for ECOFF. */
91 /* The default target format to use. */
95 switch (OUTPUT_FLAVOR
)
97 case bfd_target_aout_flavour
:
98 return target_big_endian
? "a.out-mips-big" : "a.out-mips-little";
99 case bfd_target_ecoff_flavour
:
100 return target_big_endian
? "ecoff-bigmips" : "ecoff-littlemips";
101 case bfd_target_elf_flavour
:
102 return (target_big_endian
103 ? (mips_64
? "elf64-bigmips" : "elf32-bigmips")
104 : (mips_64
? "elf64-littlemips" : "elf32-littlemips"));
110 /* The name of the readonly data section. */
111 #define RDATA_SECTION_NAME (OUTPUT_FLAVOR == bfd_target_aout_flavour \
113 : OUTPUT_FLAVOR == bfd_target_ecoff_flavour \
115 : OUTPUT_FLAVOR == bfd_target_elf_flavour \
119 /* These variables are filled in with the masks of registers used.
120 The object format code reads them and puts them in the appropriate
122 unsigned long mips_gprmask
;
123 unsigned long mips_cprmask
[4];
125 /* MIPS ISA (Instruction Set Architecture) level (may be changed
126 temporarily using .set mipsN). */
127 static int mips_isa
= -1;
129 /* MIPS ISA we are using for this output file. */
130 static int file_mips_isa
;
132 /* The CPU type as a number: 2000, 3000, 4000, 4400, etc. */
133 static int mips_cpu
= -1;
135 /* Whether the 4650 instructions (mad/madu) are permitted. */
136 static int mips_4650
= -1;
138 /* Whether the 4010 instructions are permitted. */
139 static int mips_4010
= -1;
141 /* Whether the 4100 MADD16 and DMADD16 are permitted. */
142 static int mips_4100
= -1;
144 /* Whether the processor uses hardware interlocks, and thus does not
145 require nops to be inserted. */
146 static int interlocks
= -1;
148 /* As with "interlocks" this is used by hardware that has FP
149 (co-processor) interlocks. */
150 static int cop_interlocks
= -1;
152 /* MIPS PIC level. */
156 /* Do not generate PIC code. */
159 /* Generate PIC code as in Irix 4. This is not implemented, and I'm
160 not sure what it is supposed to do. */
163 /* Generate PIC code as in the SVR4 MIPS ABI. */
166 /* Generate PIC code without using a global offset table: the data
167 segment has a maximum size of 64K, all data references are off
168 the $gp register, and all text references are PC relative. This
169 is used on some embedded systems. */
173 static enum mips_pic_level mips_pic
;
175 /* 1 if we should generate 32 bit offsets from the GP register in
176 SVR4_PIC mode. Currently has no meaning in other modes. */
177 static int mips_big_got
;
179 /* 1 if trap instructions should used for overflow rather than break
181 static int mips_trap
;
183 static int mips_warn_about_macros
;
184 static int mips_noreorder
;
185 static int mips_any_noreorder
;
186 static int mips_nomove
;
187 static int mips_noat
;
188 static int mips_nobopt
;
190 /* The size of the small data section. */
191 static int g_switch_value
= 8;
192 /* Whether the -G option was used. */
193 static int g_switch_seen
= 0;
198 /* If we can determine in advance that GP optimization won't be
199 possible, we can skip the relaxation stuff that tries to produce
200 GP-relative references. This makes delay slot optimization work
203 This function can only provide a guess, but it seems to work for
204 gcc output. If it guesses wrong, the only loss should be in
205 efficiency; it shouldn't introduce any bugs.
207 I don't know if a fix is needed for the SVR4_PIC mode. I've only
208 fixed it for the non-PIC mode. KR 95/04/07 */
209 static int nopic_need_relax
PARAMS ((symbolS
*));
211 /* handle of the OPCODE hash table */
212 static struct hash_control
*op_hash
= NULL
;
214 /* This array holds the chars that always start a comment. If the
215 pre-processor is disabled, these aren't very useful */
216 const char comment_chars
[] = "#";
218 /* This array holds the chars that only start a comment at the beginning of
219 a line. If the line seems to have the form '# 123 filename'
220 .line and .file directives will appear in the pre-processed output */
221 /* Note that input_file.c hand checks for '#' at the beginning of the
222 first line of the input file. This is because the compiler outputs
223 #NO_APP at the beginning of its output. */
224 /* Also note that C style comments are always supported. */
225 const char line_comment_chars
[] = "#";
227 /* This array holds machine specific line separator characters. */
228 const char line_separator_chars
[] = "";
230 /* Chars that can be used to separate mant from exp in floating point nums */
231 const char EXP_CHARS
[] = "eE";
233 /* Chars that mean this number is a floating point constant */
236 const char FLT_CHARS
[] = "rRsSfFdDxXpP";
238 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
239 changed in read.c . Ideally it shouldn't have to know about it at all,
240 but nothing is ideal around here.
243 static char *insn_error
;
245 static int byte_order
;
247 static int auto_align
= 1;
249 /* Symbol labelling the current insn. */
250 static symbolS
*insn_label
;
252 /* When outputting SVR4 PIC code, the assembler needs to know the
253 offset in the stack frame from which to restore the $gp register.
254 This is set by the .cprestore pseudo-op, and saved in this
256 static offsetT mips_cprestore_offset
= -1;
258 /* This is the register which holds the stack frame, as set by the
259 .frame pseudo-op. This is needed to implement .cprestore. */
260 static int mips_frame_reg
= SP
;
262 /* To output NOP instructions correctly, we need to keep information
263 about the previous two instructions. */
265 /* Whether we are optimizing. The default value of 2 means to remove
266 unneeded NOPs and swap branch instructions when possible. A value
267 of 1 means to not swap branches. A value of 0 means to always
269 static int mips_optimize
= 2;
271 /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is
272 equivalent to seeing no -g option at all. */
273 static int mips_debug
= 0;
275 /* The previous instruction. */
276 static struct mips_cl_insn prev_insn
;
278 /* The instruction before prev_insn. */
279 static struct mips_cl_insn prev_prev_insn
;
281 /* If we don't want information for prev_insn or prev_prev_insn, we
282 point the insn_mo field at this dummy integer. */
283 static const struct mips_opcode dummy_opcode
= { 0 };
285 /* Non-zero if prev_insn is valid. */
286 static int prev_insn_valid
;
288 /* The frag for the previous instruction. */
289 static struct frag
*prev_insn_frag
;
291 /* The offset into prev_insn_frag for the previous instruction. */
292 static long prev_insn_where
;
294 /* The reloc for the previous instruction, if any. */
295 static fixS
*prev_insn_fixp
;
297 /* Non-zero if the previous instruction was in a delay slot. */
298 static int prev_insn_is_delay_slot
;
300 /* Non-zero if the previous instruction was in a .set noreorder. */
301 static int prev_insn_unreordered
;
303 /* Non-zero if the previous previous instruction was in a .set
305 static int prev_prev_insn_unreordered
;
307 /* For ECOFF and ELF, relocations against symbols are done in two
308 parts, with a HI relocation and a LO relocation. Each relocation
309 has only 16 bits of space to store an addend. This means that in
310 order for the linker to handle carries correctly, it must be able
311 to locate both the HI and the LO relocation. This means that the
312 relocations must appear in order in the relocation table.
314 In order to implement this, we keep track of each unmatched HI
315 relocation. We then sort them so that they immediately precede the
316 corresponding LO relocation. */
321 struct mips_hi_fixup
*next
;
324 /* The section this fixup is in. */
328 /* The list of unmatched HI relocs. */
330 static struct mips_hi_fixup
*mips_hi_fixup_list
;
332 /* Since the MIPS does not have multiple forms of PC relative
333 instructions, we do not have to do relaxing as is done on other
334 platforms. However, we do have to handle GP relative addressing
335 correctly, which turns out to be a similar problem.
337 Every macro that refers to a symbol can occur in (at least) two
338 forms, one with GP relative addressing and one without. For
339 example, loading a global variable into a register generally uses
340 a macro instruction like this:
342 If i can be addressed off the GP register (this is true if it is in
343 the .sbss or .sdata section, or if it is known to be smaller than
344 the -G argument) this will generate the following instruction:
346 This instruction will use a GPREL reloc. If i can not be addressed
347 off the GP register, the following instruction sequence will be used:
350 In this case the first instruction will have a HI16 reloc, and the
351 second reloc will have a LO16 reloc. Both relocs will be against
354 The issue here is that we may not know whether i is GP addressable
355 until after we see the instruction that uses it. Therefore, we
356 want to be able to choose the final instruction sequence only at
357 the end of the assembly. This is similar to the way other
358 platforms choose the size of a PC relative instruction only at the
361 When generating position independent code we do not use GP
362 addressing in quite the same way, but the issue still arises as
363 external symbols and local symbols must be handled differently.
365 We handle these issues by actually generating both possible
366 instruction sequences. The longer one is put in a frag_var with
367 type rs_machine_dependent. We encode what to do with the frag in
368 the subtype field. We encode (1) the number of existing bytes to
369 replace, (2) the number of new bytes to use, (3) the offset from
370 the start of the existing bytes to the first reloc we must generate
371 (that is, the offset is applied from the start of the existing
372 bytes after they are replaced by the new bytes, if any), (4) the
373 offset from the start of the existing bytes to the second reloc,
374 (5) whether a third reloc is needed (the third reloc is always four
375 bytes after the second reloc), and (6) whether to warn if this
376 variant is used (this is sometimes needed if .set nomacro or .set
377 noat is in effect). All these numbers are reasonably small.
379 Generating two instruction sequences must be handled carefully to
380 ensure that delay slots are handled correctly. Fortunately, there
381 are a limited number of cases. When the second instruction
382 sequence is generated, append_insn is directed to maintain the
383 existing delay slot information, so it continues to apply to any
384 code after the second instruction sequence. This means that the
385 second instruction sequence must not impose any requirements not
386 required by the first instruction sequence.
388 These variant frags are then handled in functions called by the
389 machine independent code. md_estimate_size_before_relax returns
390 the final size of the frag. md_convert_frag sets up the final form
391 of the frag. tc_gen_reloc adjust the first reloc and adds a second
393 #define RELAX_ENCODE(old, new, reloc1, reloc2, reloc3, warn) \
397 | (((reloc1) + 64) << 9) \
398 | (((reloc2) + 64) << 2) \
399 | ((reloc3) ? (1 << 1) : 0) \
401 #define RELAX_OLD(i) (((i) >> 24) & 0xff)
402 #define RELAX_NEW(i) (((i) >> 16) & 0xff)
403 #define RELAX_RELOC1(i) ((bfd_vma)(((i) >> 9) & 0x7f) - 64)
404 #define RELAX_RELOC2(i) ((bfd_vma)(((i) >> 2) & 0x7f) - 64)
405 #define RELAX_RELOC3(i) (((i) >> 1) & 1)
406 #define RELAX_WARN(i) ((i) & 1)
408 /* Prototypes for static functions. */
411 #define internalError() \
412 as_fatal ("internal Error, line %d, %s", __LINE__, __FILE__)
414 #define internalError() as_fatal ("MIPS internal Error");
417 static int insn_uses_reg
PARAMS ((struct mips_cl_insn
*ip
,
418 unsigned int reg
, int fpr
));
419 static int reg_needs_delay
PARAMS ((int));
420 static void append_insn
PARAMS ((char *place
,
421 struct mips_cl_insn
* ip
,
423 bfd_reloc_code_real_type r
,
425 static void mips_no_prev_insn
PARAMS ((void));
426 static void mips_emit_delays
PARAMS ((void));
428 static void macro_build
PARAMS ((char *place
, int *counter
, expressionS
* ep
,
429 const char *name
, const char *fmt
,
432 static void macro_build ();
434 static void macro_build_lui
PARAMS ((char *place
, int *counter
,
435 expressionS
* ep
, int regnum
));
436 static void set_at
PARAMS ((int *counter
, int reg
, int unsignedp
));
437 static void check_absolute_expr
PARAMS ((struct mips_cl_insn
* ip
,
439 static void load_register
PARAMS ((int *, int, expressionS
*, int));
440 static void load_address
PARAMS ((int *counter
, int reg
, expressionS
*ep
));
441 static void macro
PARAMS ((struct mips_cl_insn
* ip
));
442 #ifdef LOSING_COMPILER
443 static void macro2
PARAMS ((struct mips_cl_insn
* ip
));
445 static void mips_ip
PARAMS ((char *str
, struct mips_cl_insn
* ip
));
446 static int my_getSmallExpression
PARAMS ((expressionS
* ep
, char *str
));
447 static void my_getExpression
PARAMS ((expressionS
* ep
, char *str
));
448 static symbolS
*get_symbol
PARAMS ((void));
449 static void mips_align
PARAMS ((int to
, int fill
, symbolS
*label
));
450 static void s_align
PARAMS ((int));
451 static void s_change_sec
PARAMS ((int));
452 static void s_cons
PARAMS ((int));
453 static void s_float_cons
PARAMS ((int));
454 static void s_mips_globl
PARAMS ((int));
455 static void s_option
PARAMS ((int));
456 static void s_mipsset
PARAMS ((int));
457 static void s_abicalls
PARAMS ((int));
458 static void s_cpload
PARAMS ((int));
459 static void s_cprestore
PARAMS ((int));
460 static void s_gpword
PARAMS ((int));
461 static void s_cpadd
PARAMS ((int));
462 static void md_obj_begin
PARAMS ((void));
463 static void md_obj_end
PARAMS ((void));
464 static long get_number
PARAMS ((void));
465 static void s_ent
PARAMS ((int));
466 static void s_mipsend
PARAMS ((int));
467 static void s_file
PARAMS ((int));
471 The following pseudo-ops from the Kane and Heinrich MIPS book
472 should be defined here, but are currently unsupported: .alias,
473 .galive, .gjaldef, .gjrlive, .livereg, .noalias.
475 The following pseudo-ops from the Kane and Heinrich MIPS book are
476 specific to the type of debugging information being generated, and
477 should be defined by the object format: .aent, .begin, .bend,
478 .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp,
481 The following pseudo-ops from the Kane and Heinrich MIPS book are
482 not MIPS CPU specific, but are also not specific to the object file
483 format. This file is probably the best place to define them, but
484 they are not currently supported: .asm0, .endr, .lab, .repeat,
485 .struct, .weakext. */
487 static const pseudo_typeS mips_pseudo_table
[] =
489 /* MIPS specific pseudo-ops. */
490 {"option", s_option
, 0},
491 {"set", s_mipsset
, 0},
492 {"rdata", s_change_sec
, 'r'},
493 {"sdata", s_change_sec
, 's'},
494 {"livereg", s_ignore
, 0},
495 {"abicalls", s_abicalls
, 0},
496 {"cpload", s_cpload
, 0},
497 {"cprestore", s_cprestore
, 0},
498 {"gpword", s_gpword
, 0},
499 {"cpadd", s_cpadd
, 0},
501 /* Relatively generic pseudo-ops that happen to be used on MIPS
503 {"asciiz", stringer
, 1},
504 {"bss", s_change_sec
, 'b'},
507 {"dword", s_cons
, 3},
509 /* These pseudo-ops are defined in read.c, but must be overridden
510 here for one reason or another. */
511 {"align", s_align
, 0},
513 {"data", s_change_sec
, 'd'},
514 {"double", s_float_cons
, 'd'},
515 {"float", s_float_cons
, 'f'},
516 {"globl", s_mips_globl
, 0},
517 {"global", s_mips_globl
, 0},
518 {"hword", s_cons
, 1},
523 {"short", s_cons
, 1},
524 {"single", s_float_cons
, 'f'},
525 {"text", s_change_sec
, 't'},
530 static const pseudo_typeS mips_nonecoff_pseudo_table
[] = {
531 /* These pseudo-ops should be defined by the object file format.
532 However, a.out doesn't support them, so we have versions here. */
534 {"bgnb", s_ignore
, 0},
535 {"end", s_mipsend
, 0},
536 {"endb", s_ignore
, 0},
539 {"fmask", s_ignore
, 'F'},
540 {"frame", s_ignore
, 0},
541 {"loc", s_ignore
, 0},
542 {"mask", s_ignore
, 'R'},
543 {"verstamp", s_ignore
, 0},
547 extern void pop_insert
PARAMS ((const pseudo_typeS
*));
552 pop_insert (mips_pseudo_table
);
553 if (! ECOFF_DEBUGGING
)
554 pop_insert (mips_nonecoff_pseudo_table
);
557 static char *expr_end
;
559 /* Expressions which appear in instructions. These are set by
562 static expressionS imm_expr
;
563 static expressionS offset_expr
;
565 /* Relocs associated with imm_expr and offset_expr. */
567 static bfd_reloc_code_real_type imm_reloc
;
568 static bfd_reloc_code_real_type offset_reloc
;
570 /* This is set by mips_ip if imm_reloc is an unmatched HI16_S reloc. */
572 static boolean imm_unmatched_hi
;
575 * This function is called once, at assembler startup time. It should
576 * set up all the tables, etc. that the MD part of the assembler will need.
582 register const char *retval
= NULL
;
583 register unsigned int i
= 0;
591 if (strcmp (cpu
+ (sizeof TARGET_CPU
) - 3, "el") == 0)
593 a
= xmalloc (sizeof TARGET_CPU
);
594 strcpy (a
, TARGET_CPU
);
595 a
[(sizeof TARGET_CPU
) - 3] = '\0';
599 if (strcmp (cpu
, "mips") == 0)
605 else if (strcmp (cpu
, "r6000") == 0
606 || strcmp (cpu
, "mips2") == 0)
612 else if (strcmp (cpu
, "mips64") == 0
613 || strcmp (cpu
, "r4000") == 0
614 || strcmp (cpu
, "mips3") == 0)
620 else if (strcmp (cpu
, "r4400") == 0)
626 else if (strcmp (cpu
, "mips64orion") == 0
627 || strcmp (cpu
, "r4600") == 0)
633 else if (strcmp (cpu
, "r4650") == 0)
641 else if (strcmp (cpu
, "mips64vr4300") == 0)
647 else if (strcmp (cpu
, "mips64vr4100") == 0)
655 else if (strcmp (cpu
, "r4010") == 0)
663 else if (strcmp (cpu
, "r5000") == 0
664 || strcmp (cpu
, "mips64vr5000") == 0)
670 else if (strcmp (cpu
, "r8000") == 0
671 || strcmp (cpu
, "mips4") == 0)
677 else if (strcmp (cpu
, "r10000") == 0)
703 if (mips_4650
|| mips_4010
|| mips_4100
|| mips_cpu
== 4300)
708 if (mips_cpu
== 4300)
713 if (mips_isa
< 2 && mips_trap
)
714 as_bad ("trap exception not supported at ISA 1");
719 ok
= bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, 3000);
722 ok
= bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, 6000);
725 ok
= bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, 4000);
728 ok
= bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, 8000);
732 as_warn ("Could not set architecture and machine");
734 file_mips_isa
= mips_isa
;
736 op_hash
= hash_new ();
738 for (i
= 0; i
< NUMOPCODES
;)
740 const char *name
= mips_opcodes
[i
].name
;
742 retval
= hash_insert (op_hash
, name
, (PTR
) &mips_opcodes
[i
]);
745 fprintf (stderr
, "internal error: can't hash `%s': %s\n",
746 mips_opcodes
[i
].name
, retval
);
747 as_fatal ("Broken assembler. No assembly attempted.");
751 if (mips_opcodes
[i
].pinfo
!= INSN_MACRO
752 && ((mips_opcodes
[i
].match
& mips_opcodes
[i
].mask
)
753 != mips_opcodes
[i
].match
))
755 fprintf (stderr
, "internal error: bad opcode: `%s' \"%s\"\n",
756 mips_opcodes
[i
].name
, mips_opcodes
[i
].args
);
757 as_fatal ("Broken assembler. No assembly attempted.");
761 while ((i
< NUMOPCODES
) && !strcmp (mips_opcodes
[i
].name
, name
));
764 mips_no_prev_insn ();
772 /* set the default alignment for the text section (2**2) */
773 record_alignment (text_section
, 2);
775 if (USE_GLOBAL_POINTER_OPT
)
776 bfd_set_gp_size (stdoutput
, g_switch_value
);
778 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
780 /* Sections must be aligned to 16 byte boundaries. */
781 (void) bfd_set_section_alignment (stdoutput
, text_section
, 4);
782 (void) bfd_set_section_alignment (stdoutput
, data_section
, 4);
783 (void) bfd_set_section_alignment (stdoutput
, bss_section
, 4);
785 /* Create a .reginfo section for register masks and a .mdebug
786 section for debugging information. */
797 sec
= subseg_new (".reginfo", (subsegT
) 0);
799 /* The ABI says this section should be loaded so that the
800 running program can access it. */
801 (void) bfd_set_section_flags (stdoutput
, sec
,
802 (SEC_ALLOC
| SEC_LOAD
803 | SEC_READONLY
| SEC_DATA
));
804 (void) bfd_set_section_alignment (stdoutput
, sec
, 2);
807 mips_regmask_frag
= frag_more (sizeof (Elf32_External_RegInfo
));
812 /* The 64-bit ABI uses a .MIPS.options section rather than
814 sec
= subseg_new (".MIPS.options", (subsegT
) 0);
815 (void) bfd_set_section_flags (stdoutput
, sec
,
816 (SEC_ALLOC
| SEC_LOAD
817 | SEC_READONLY
| SEC_DATA
));
818 (void) bfd_set_section_alignment (stdoutput
, sec
, 3);
821 /* Set up the option header. */
823 Elf_Internal_Options opthdr
;
826 opthdr
.kind
= ODK_REGINFO
;
827 opthdr
.size
= (sizeof (Elf_External_Options
)
828 + sizeof (Elf64_External_RegInfo
));
831 f
= frag_more (sizeof (Elf_External_Options
));
832 bfd_mips_elf_swap_options_out (stdoutput
, &opthdr
,
833 (Elf_External_Options
*) f
);
835 mips_regmask_frag
= frag_more (sizeof (Elf64_External_RegInfo
));
842 sec
= subseg_new (".mdebug", (subsegT
) 0);
843 (void) bfd_set_section_flags (stdoutput
, sec
,
844 SEC_HAS_CONTENTS
| SEC_READONLY
);
845 (void) bfd_set_section_alignment (stdoutput
, sec
, 2);
848 subseg_set (seg
, subseg
);
852 if (! ECOFF_DEBUGGING
)
859 if (! ECOFF_DEBUGGING
)
867 struct mips_cl_insn insn
;
869 imm_expr
.X_op
= O_absent
;
870 imm_reloc
= BFD_RELOC_UNUSED
;
871 imm_unmatched_hi
= false;
872 offset_expr
.X_op
= O_absent
;
873 offset_reloc
= BFD_RELOC_UNUSED
;
875 mips_ip (str
, &insn
);
878 as_bad ("%s `%s'", insn_error
, str
);
881 if (insn
.insn_mo
->pinfo
== INSN_MACRO
)
887 if (imm_expr
.X_op
!= O_absent
)
888 append_insn ((char *) NULL
, &insn
, &imm_expr
, imm_reloc
,
890 else if (offset_expr
.X_op
!= O_absent
)
891 append_insn ((char *) NULL
, &insn
, &offset_expr
, offset_reloc
, false);
893 append_insn ((char *) NULL
, &insn
, NULL
, BFD_RELOC_UNUSED
, false);
897 /* See whether instruction IP reads register REG. If FPR is non-zero,
898 REG is a floating point register. */
901 insn_uses_reg (ip
, reg
, fpr
)
902 struct mips_cl_insn
*ip
;
906 /* Don't report on general register 0, since it never changes. */
907 if (! fpr
&& reg
== 0)
912 /* If we are called with either $f0 or $f1, we must check $f0.
913 This is not optimal, because it will introduce an unnecessary
914 NOP between "lwc1 $f0" and "swc1 $f1". To fix this we would
915 need to distinguish reading both $f0 and $f1 or just one of
916 them. Note that we don't have to check the other way,
917 because there is no instruction that sets both $f0 and $f1
918 and requires a delay. */
919 if ((ip
->insn_mo
->pinfo
& INSN_READ_FPR_S
)
920 && (((ip
->insn_opcode
>> OP_SH_FS
) & OP_MASK_FS
)
921 == (reg
&~ (unsigned) 1)))
923 if ((ip
->insn_mo
->pinfo
& INSN_READ_FPR_T
)
924 && (((ip
->insn_opcode
>> OP_SH_FT
) & OP_MASK_FT
)
925 == (reg
&~ (unsigned) 1)))
930 if ((ip
->insn_mo
->pinfo
& INSN_READ_GPR_S
)
931 && ((ip
->insn_opcode
>> OP_SH_RS
) & OP_MASK_RS
) == reg
)
933 if ((ip
->insn_mo
->pinfo
& INSN_READ_GPR_T
)
934 && ((ip
->insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
) == reg
)
941 /* This function returns true if modifying a register requires a
945 reg_needs_delay (reg
)
948 unsigned long prev_pinfo
;
950 prev_pinfo
= prev_insn
.insn_mo
->pinfo
;
953 && ((prev_pinfo
& INSN_LOAD_COPROC_DELAY
)
955 && (prev_pinfo
& INSN_LOAD_MEMORY_DELAY
))))
957 /* A load from a coprocessor or from memory. All load
958 delays delay the use of general register rt for one
959 instruction on the r3000. The r6000 and r4000 use
961 know (prev_pinfo
& INSN_WRITE_GPR_T
);
962 if (reg
== ((prev_insn
.insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
))
969 /* Output an instruction. PLACE is where to put the instruction; if
970 it is NULL, this uses frag_more to get room. IP is the instruction
971 information. ADDRESS_EXPR is an operand of the instruction to be
972 used with RELOC_TYPE. */
975 append_insn (place
, ip
, address_expr
, reloc_type
, unmatched_hi
)
977 struct mips_cl_insn
*ip
;
978 expressionS
*address_expr
;
979 bfd_reloc_code_real_type reloc_type
;
980 boolean unmatched_hi
;
982 register unsigned long prev_pinfo
, pinfo
;
987 prev_pinfo
= prev_insn
.insn_mo
->pinfo
;
988 pinfo
= ip
->insn_mo
->pinfo
;
990 if (place
== NULL
&& ! mips_noreorder
)
992 /* If the previous insn required any delay slots, see if we need
993 to insert a NOP or two. There are eight kinds of possible
994 hazards, of which an instruction can have at most one type.
995 (1) a load from memory delay
996 (2) a load from a coprocessor delay
997 (3) an unconditional branch delay
998 (4) a conditional branch delay
999 (5) a move to coprocessor register delay
1000 (6) a load coprocessor register from memory delay
1001 (7) a coprocessor condition code delay
1002 (8) a HI/LO special register delay
1004 There are a lot of optimizations we could do that we don't.
1005 In particular, we do not, in general, reorder instructions.
1006 If you use gcc with optimization, it will reorder
1007 instructions and generally do much more optimization then we
1008 do here; repeating all that work in the assembler would only
1009 benefit hand written assembly code, and does not seem worth
1012 /* This is how a NOP is emitted. */
1013 #define emit_nop() md_number_to_chars (frag_more (4), 0, 4)
1015 /* The previous insn might require a delay slot, depending upon
1016 the contents of the current insn. */
1018 && (((prev_pinfo
& INSN_LOAD_COPROC_DELAY
)
1019 && ! cop_interlocks
)
1021 && (prev_pinfo
& INSN_LOAD_MEMORY_DELAY
))))
1023 /* A load from a coprocessor or from memory. All load
1024 delays delay the use of general register rt for one
1025 instruction on the r3000. The r6000 and r4000 use
1027 know (prev_pinfo
& INSN_WRITE_GPR_T
);
1028 if (mips_optimize
== 0
1029 || insn_uses_reg (ip
,
1030 ((prev_insn
.insn_opcode
>> OP_SH_RT
)
1035 else if (mips_isa
< 4
1036 && (((prev_pinfo
& INSN_COPROC_MOVE_DELAY
)
1037 && ! cop_interlocks
)
1039 && (prev_pinfo
& INSN_COPROC_MEMORY_DELAY
))))
1041 /* A generic coprocessor delay. The previous instruction
1042 modified a coprocessor general or control register. If
1043 it modified a control register, we need to avoid any
1044 coprocessor instruction (this is probably not always
1045 required, but it sometimes is). If it modified a general
1046 register, we avoid using that register.
1048 On the r6000 and r4000 loading a coprocessor register
1049 from memory is interlocked, and does not require a delay.
1051 This case is not handled very well. There is no special
1052 knowledge of CP0 handling, and the coprocessors other
1053 than the floating point unit are not distinguished at
1055 if (prev_pinfo
& INSN_WRITE_FPR_T
)
1057 if (mips_optimize
== 0
1058 || insn_uses_reg (ip
,
1059 ((prev_insn
.insn_opcode
>> OP_SH_FT
)
1064 else if (prev_pinfo
& INSN_WRITE_FPR_S
)
1066 if (mips_optimize
== 0
1067 || insn_uses_reg (ip
,
1068 ((prev_insn
.insn_opcode
>> OP_SH_FS
)
1075 /* We don't know exactly what the previous instruction
1076 does. If the current instruction uses a coprocessor
1077 register, we must insert a NOP. If previous
1078 instruction may set the condition codes, and the
1079 current instruction uses them, we must insert two
1081 if (mips_optimize
== 0
1082 || ((prev_pinfo
& INSN_WRITE_COND_CODE
)
1083 && (pinfo
& INSN_READ_COND_CODE
)))
1085 else if (pinfo
& INSN_COP
)
1089 else if (mips_isa
< 4
1090 && (prev_pinfo
& INSN_WRITE_COND_CODE
)
1091 && ! cop_interlocks
)
1093 /* The previous instruction sets the coprocessor condition
1094 codes, but does not require a general coprocessor delay
1095 (this means it is a floating point comparison
1096 instruction). If this instruction uses the condition
1097 codes, we need to insert a single NOP. */
1098 if (mips_optimize
== 0
1099 || (pinfo
& INSN_READ_COND_CODE
))
1102 else if (prev_pinfo
& INSN_READ_LO
)
1104 /* The previous instruction reads the LO register; if the
1105 current instruction writes to the LO register, we must
1106 insert two NOPS. Some newer processors have interlocks. */
1108 && (mips_optimize
== 0
1109 || (pinfo
& INSN_WRITE_LO
)))
1112 else if (prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
1114 /* The previous instruction reads the HI register; if the
1115 current instruction writes to the HI register, we must
1116 insert a NOP. Some newer processors have interlocks. */
1118 && (mips_optimize
== 0
1119 || (pinfo
& INSN_WRITE_HI
)))
1123 /* There are two cases which require two intervening
1124 instructions: 1) setting the condition codes using a move to
1125 coprocessor instruction which requires a general coprocessor
1126 delay and then reading the condition codes 2) reading the HI
1127 or LO register and then writing to it (except on processors
1128 which have interlocks). If we are not already emitting a NOP
1129 instruction, we must check for these cases compared to the
1130 instruction previous to the previous instruction. */
1133 && (prev_prev_insn
.insn_mo
->pinfo
& INSN_COPROC_MOVE_DELAY
)
1134 && (prev_prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
)
1135 && (pinfo
& INSN_READ_COND_CODE
)
1136 && ! cop_interlocks
)
1137 || ((prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
)
1138 && (pinfo
& INSN_WRITE_LO
)
1140 || ((prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
1141 && (pinfo
& INSN_WRITE_HI
)
1145 /* If we are being given a nop instruction, don't bother with
1146 one of the nops we would otherwise output. This will only
1147 happen when a nop instruction is used with mips_optimize set
1149 if (nops
> 0 && ip
->insn_opcode
== 0)
1152 /* Now emit the right number of NOP instructions. */
1156 unsigned long old_frag_offset
;
1159 old_frag
= frag_now
;
1160 old_frag_offset
= frag_now_fix ();
1162 for (i
= 0; i
< nops
; i
++)
1167 listing_prev_line ();
1168 /* We may be at the start of a variant frag. In case we
1169 are, make sure there is enough space for the frag
1170 after the frags created by listing_prev_line. The
1171 argument to frag_grow here must be at least as large
1172 as the argument to all other calls to frag_grow in
1173 this file. We don't have to worry about being in the
1174 middle of a variant frag, because the variants insert
1175 all needed nop instructions themselves. */
1179 if (insn_label
!= NULL
)
1181 assert (S_GET_SEGMENT (insn_label
) == now_seg
);
1182 insn_label
->sy_frag
= frag_now
;
1183 S_SET_VALUE (insn_label
, (valueT
) frag_now_fix ());
1186 #ifndef NO_ECOFF_DEBUGGING
1187 if (ECOFF_DEBUGGING
)
1188 ecoff_fix_loc (old_frag
, old_frag_offset
);
1198 if (address_expr
!= NULL
)
1200 if (address_expr
->X_op
== O_constant
)
1205 ip
->insn_opcode
|= address_expr
->X_add_number
;
1208 case BFD_RELOC_LO16
:
1209 ip
->insn_opcode
|= address_expr
->X_add_number
& 0xffff;
1212 case BFD_RELOC_MIPS_JMP
:
1213 ip
->insn_opcode
|= (address_expr
->X_add_number
>> 2) & 0x3ffffff;
1216 case BFD_RELOC_16_PCREL_S2
:
1225 assert (reloc_type
!= BFD_RELOC_UNUSED
);
1227 /* Don't generate a reloc if we are writing into a variant
1231 fixp
= fix_new_exp (frag_now
, f
- frag_now
->fr_literal
, 4,
1233 reloc_type
== BFD_RELOC_16_PCREL_S2
,
1237 struct mips_hi_fixup
*hi_fixup
;
1239 assert (reloc_type
== BFD_RELOC_HI16_S
);
1240 hi_fixup
= ((struct mips_hi_fixup
*)
1241 xmalloc (sizeof (struct mips_hi_fixup
)));
1242 hi_fixup
->fixp
= fixp
;
1243 hi_fixup
->seg
= now_seg
;
1244 hi_fixup
->next
= mips_hi_fixup_list
;
1245 mips_hi_fixup_list
= hi_fixup
;
1251 md_number_to_chars (f
, ip
->insn_opcode
, 4);
1253 /* Update the register mask information. */
1254 if (pinfo
& INSN_WRITE_GPR_D
)
1255 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
);
1256 if ((pinfo
& (INSN_WRITE_GPR_T
| INSN_READ_GPR_T
)) != 0)
1257 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
);
1258 if (pinfo
& INSN_READ_GPR_S
)
1259 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> OP_SH_RS
) & OP_MASK_RS
);
1260 if (pinfo
& INSN_WRITE_GPR_31
)
1261 mips_gprmask
|= 1 << 31;
1262 if (pinfo
& INSN_WRITE_FPR_D
)
1263 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FD
) & OP_MASK_FD
);
1264 if ((pinfo
& (INSN_WRITE_FPR_S
| INSN_READ_FPR_S
)) != 0)
1265 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FS
) & OP_MASK_FS
);
1266 if ((pinfo
& (INSN_WRITE_FPR_T
| INSN_READ_FPR_T
)) != 0)
1267 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FT
) & OP_MASK_FT
);
1268 if ((pinfo
& INSN_READ_FPR_R
) != 0)
1269 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FR
) & OP_MASK_FR
);
1270 if (pinfo
& INSN_COP
)
1272 /* We don't keep enough information to sort these cases out. */
1274 /* Never set the bit for $0, which is always zero. */
1275 mips_gprmask
&=~ 1 << 0;
1277 if (place
== NULL
&& ! mips_noreorder
)
1279 /* Filling the branch delay slot is more complex. We try to
1280 switch the branch with the previous instruction, which we can
1281 do if the previous instruction does not set up a condition
1282 that the branch tests and if the branch is not itself the
1283 target of any branch. */
1284 if ((pinfo
& INSN_UNCOND_BRANCH_DELAY
)
1285 || (pinfo
& INSN_COND_BRANCH_DELAY
))
1287 if (mips_optimize
< 2
1288 /* If we have seen .set volatile or .set nomove, don't
1291 /* If we had to emit any NOP instructions, then we
1292 already know we can not swap. */
1294 /* If we don't even know the previous insn, we can not
1296 || ! prev_insn_valid
1297 /* If the previous insn is already in a branch delay
1298 slot, then we can not swap. */
1299 || prev_insn_is_delay_slot
1300 /* If the previous previous insn was in a .set
1301 noreorder, we can't swap. Actually, the MIPS
1302 assembler will swap in this situation. However, gcc
1303 configured -with-gnu-as will generate code like
1309 in which we can not swap the bne and INSN. If gcc is
1310 not configured -with-gnu-as, it does not output the
1311 .set pseudo-ops. We don't have to check
1312 prev_insn_unreordered, because prev_insn_valid will
1313 be 0 in that case. We don't want to use
1314 prev_prev_insn_valid, because we do want to be able
1315 to swap at the start of a function. */
1316 || prev_prev_insn_unreordered
1317 /* If the branch is itself the target of a branch, we
1318 can not swap. We cheat on this; all we check for is
1319 whether there is a label on this instruction. If
1320 there are any branches to anything other than a
1321 label, users must use .set noreorder. */
1322 || insn_label
!= NULL
1323 /* If the previous instruction is in a variant frag, we
1324 can not do the swap. */
1325 || prev_insn_frag
->fr_type
== rs_machine_dependent
1326 /* If the branch reads the condition codes, we don't
1327 even try to swap, because in the sequence
1332 we can not swap, and I don't feel like handling that
1335 && (pinfo
& INSN_READ_COND_CODE
))
1336 /* We can not swap with an instruction that requires a
1337 delay slot, becase the target of the branch might
1338 interfere with that instruction. */
1341 & (INSN_LOAD_COPROC_DELAY
1342 | INSN_COPROC_MOVE_DELAY
1343 | INSN_WRITE_COND_CODE
)))
1350 & (INSN_LOAD_MEMORY_DELAY
1351 | INSN_COPROC_MEMORY_DELAY
)))
1352 /* We can not swap with a branch instruction. */
1354 & (INSN_UNCOND_BRANCH_DELAY
1355 | INSN_COND_BRANCH_DELAY
1356 | INSN_COND_BRANCH_LIKELY
))
1357 /* We do not swap with a trap instruction, since it
1358 complicates trap handlers to have the trap
1359 instruction be in a delay slot. */
1360 || (prev_pinfo
& INSN_TRAP
)
1361 /* If the branch reads a register that the previous
1362 instruction sets, we can not swap. */
1363 || ((prev_pinfo
& INSN_WRITE_GPR_T
)
1364 && insn_uses_reg (ip
,
1365 ((prev_insn
.insn_opcode
>> OP_SH_RT
)
1368 || ((prev_pinfo
& INSN_WRITE_GPR_D
)
1369 && insn_uses_reg (ip
,
1370 ((prev_insn
.insn_opcode
>> OP_SH_RD
)
1373 /* If the branch writes a register that the previous
1374 instruction sets, we can not swap (we know that
1375 branches write only to RD or to $31). */
1376 || ((prev_pinfo
& INSN_WRITE_GPR_T
)
1377 && (((pinfo
& INSN_WRITE_GPR_D
)
1378 && (((prev_insn
.insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
)
1379 == ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)))
1380 || ((pinfo
& INSN_WRITE_GPR_31
)
1381 && (((prev_insn
.insn_opcode
>> OP_SH_RT
)
1384 || ((prev_pinfo
& INSN_WRITE_GPR_D
)
1385 && (((pinfo
& INSN_WRITE_GPR_D
)
1386 && (((prev_insn
.insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)
1387 == ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)))
1388 || ((pinfo
& INSN_WRITE_GPR_31
)
1389 && (((prev_insn
.insn_opcode
>> OP_SH_RD
)
1392 /* If the branch writes a register that the previous
1393 instruction reads, we can not swap (we know that
1394 branches only write to RD or to $31). */
1395 || ((pinfo
& INSN_WRITE_GPR_D
)
1396 && insn_uses_reg (&prev_insn
,
1397 ((ip
->insn_opcode
>> OP_SH_RD
)
1400 || ((pinfo
& INSN_WRITE_GPR_31
)
1401 && insn_uses_reg (&prev_insn
, 31, 0))
1402 /* If we are generating embedded PIC code, the branch
1403 might be expanded into a sequence which uses $at, so
1404 we can't swap with an instruction which reads it. */
1405 || (mips_pic
== EMBEDDED_PIC
1406 && insn_uses_reg (&prev_insn
, AT
, 0))
1407 /* If the previous previous instruction has a load
1408 delay, and sets a register that the branch reads, we
1411 && ((prev_prev_insn
.insn_mo
->pinfo
& INSN_LOAD_COPROC_DELAY
)
1413 && (prev_prev_insn
.insn_mo
->pinfo
1414 & INSN_LOAD_MEMORY_DELAY
)))
1415 && insn_uses_reg (ip
,
1416 ((prev_prev_insn
.insn_opcode
>> OP_SH_RT
)
1419 /* If one instruction sets a condition code and the
1420 other one uses a condition code, we can not swap. */
1421 || ((pinfo
& INSN_READ_COND_CODE
)
1422 && (prev_pinfo
& INSN_WRITE_COND_CODE
))
1423 || ((pinfo
& INSN_WRITE_COND_CODE
)
1424 && (prev_pinfo
& INSN_READ_COND_CODE
)))
1426 /* We could do even better for unconditional branches to
1427 portions of this object file; we could pick up the
1428 instruction at the destination, put it in the delay
1429 slot, and bump the destination address. */
1431 /* Update the previous insn information. */
1432 prev_prev_insn
= *ip
;
1433 prev_insn
.insn_mo
= &dummy_opcode
;
1440 /* It looks like we can actually do the swap. */
1441 prev_f
= prev_insn_frag
->fr_literal
+ prev_insn_where
;
1442 memcpy (temp
, prev_f
, 4);
1443 memcpy (prev_f
, f
, 4);
1444 memcpy (f
, temp
, 4);
1447 prev_insn_fixp
->fx_frag
= frag_now
;
1448 prev_insn_fixp
->fx_where
= f
- frag_now
->fr_literal
;
1452 fixp
->fx_frag
= prev_insn_frag
;
1453 fixp
->fx_where
= prev_insn_where
;
1455 /* Update the previous insn information; leave prev_insn
1457 prev_prev_insn
= *ip
;
1459 prev_insn_is_delay_slot
= 1;
1461 /* If that was an unconditional branch, forget the previous
1462 insn information. */
1463 if (pinfo
& INSN_UNCOND_BRANCH_DELAY
)
1465 prev_prev_insn
.insn_mo
= &dummy_opcode
;
1466 prev_insn
.insn_mo
= &dummy_opcode
;
1469 else if (pinfo
& INSN_COND_BRANCH_LIKELY
)
1471 /* We don't yet optimize a branch likely. What we should do
1472 is look at the target, copy the instruction found there
1473 into the delay slot, and increment the branch to jump to
1474 the next instruction. */
1476 /* Update the previous insn information. */
1477 prev_prev_insn
= *ip
;
1478 prev_insn
.insn_mo
= &dummy_opcode
;
1482 /* Update the previous insn information. */
1484 prev_prev_insn
.insn_mo
= &dummy_opcode
;
1486 prev_prev_insn
= prev_insn
;
1489 /* Any time we see a branch, we always fill the delay slot
1490 immediately; since this insn is not a branch, we know it
1491 is not in a delay slot. */
1492 prev_insn_is_delay_slot
= 0;
1495 prev_prev_insn_unreordered
= prev_insn_unreordered
;
1496 prev_insn_unreordered
= 0;
1497 prev_insn_frag
= frag_now
;
1498 prev_insn_where
= f
- frag_now
->fr_literal
;
1499 prev_insn_fixp
= fixp
;
1500 prev_insn_valid
= 1;
1503 /* We just output an insn, so the next one doesn't have a label. */
1507 /* This function forgets that there was any previous instruction or
1511 mips_no_prev_insn ()
1513 prev_insn
.insn_mo
= &dummy_opcode
;
1514 prev_prev_insn
.insn_mo
= &dummy_opcode
;
1515 prev_insn_valid
= 0;
1516 prev_insn_is_delay_slot
= 0;
1517 prev_insn_unreordered
= 0;
1518 prev_prev_insn_unreordered
= 0;
1522 /* This function must be called whenever we turn on noreorder or emit
1523 something other than instructions. It inserts any NOPS which might
1524 be needed by the previous instruction, and clears the information
1525 kept for the previous instructions. */
1530 if (! mips_noreorder
)
1536 && (! cop_interlocks
1537 && (prev_insn
.insn_mo
->pinfo
1538 & (INSN_LOAD_COPROC_DELAY
1539 | INSN_COPROC_MOVE_DELAY
1540 | INSN_WRITE_COND_CODE
))))
1542 && (prev_insn
.insn_mo
->pinfo
1546 && (prev_insn
.insn_mo
->pinfo
1547 & (INSN_LOAD_MEMORY_DELAY
1548 | INSN_COPROC_MEMORY_DELAY
))))
1552 && (! cop_interlocks
1553 && prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
))
1555 && ((prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
1556 || (prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
))))
1559 else if ((mips_isa
< 4
1560 && (! cop_interlocks
1561 && prev_prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
))
1563 && ((prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
1564 || (prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
))))
1569 if (insn_label
!= NULL
)
1571 assert (S_GET_SEGMENT (insn_label
) == now_seg
);
1572 insn_label
->sy_frag
= frag_now
;
1573 S_SET_VALUE (insn_label
, (valueT
) frag_now_fix ());
1578 mips_no_prev_insn ();
1581 /* Build an instruction created by a macro expansion. This is passed
1582 a pointer to the count of instructions created so far, an
1583 expression, the name of the instruction to build, an operand format
1584 string, and corresponding arguments. */
1588 macro_build (char *place
,
1596 macro_build (place
, counter
, ep
, name
, fmt
, va_alist
)
1605 struct mips_cl_insn insn
;
1606 bfd_reloc_code_real_type r
;
1610 va_start (args
, fmt
);
1616 * If the macro is about to expand into a second instruction,
1617 * print a warning if needed. We need to pass ip as a parameter
1618 * to generate a better warning message here...
1620 if (mips_warn_about_macros
&& place
== NULL
&& *counter
== 1)
1621 as_warn ("Macro instruction expanded into multiple instructions");
1624 *counter
+= 1; /* bump instruction counter */
1626 r
= BFD_RELOC_UNUSED
;
1627 insn
.insn_mo
= (struct mips_opcode
*) hash_find (op_hash
, name
);
1628 assert (insn
.insn_mo
);
1629 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
1631 while (strcmp (fmt
, insn
.insn_mo
->args
) != 0
1632 || insn
.insn_mo
->pinfo
== INSN_MACRO
1633 || ((insn
.insn_mo
->pinfo
& INSN_ISA
) == INSN_ISA2
1635 || ((insn
.insn_mo
->pinfo
& INSN_ISA
) == INSN_ISA3
1637 || ((insn
.insn_mo
->pinfo
& INSN_ISA
) == INSN_ISA4
1639 || ((insn
.insn_mo
->pinfo
& INSN_ISA
) == INSN_4650
1641 || ((insn
.insn_mo
->pinfo
& INSN_ISA
) == INSN_4010
1643 || ((insn
.insn_mo
->pinfo
& INSN_ISA
) == INSN_4100
1647 assert (insn
.insn_mo
->name
);
1648 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
1650 insn
.insn_opcode
= insn
.insn_mo
->match
;
1666 insn
.insn_opcode
|= va_arg (args
, int) << 16;
1672 insn
.insn_opcode
|= va_arg (args
, int) << 16;
1677 insn
.insn_opcode
|= va_arg (args
, int) << 11;
1682 insn
.insn_opcode
|= va_arg (args
, int) << 11;
1689 insn
.insn_opcode
|= va_arg (args
, int) << 6;
1693 insn
.insn_opcode
|= va_arg (args
, int) << 6;
1697 insn
.insn_opcode
|= va_arg (args
, int) << 6;
1704 insn
.insn_opcode
|= va_arg (args
, int) << 21;
1710 r
= (bfd_reloc_code_real_type
) va_arg (args
, int);
1711 assert (r
== BFD_RELOC_MIPS_GPREL
1712 || r
== BFD_RELOC_MIPS_LITERAL
1713 || r
== BFD_RELOC_LO16
1714 || r
== BFD_RELOC_MIPS_GOT16
1715 || r
== BFD_RELOC_MIPS_CALL16
1716 || r
== BFD_RELOC_MIPS_GOT_LO16
1717 || r
== BFD_RELOC_MIPS_CALL_LO16
1718 || (ep
->X_op
== O_subtract
1719 && now_seg
== text_section
1720 && r
== BFD_RELOC_PCREL_LO16
));
1724 r
= (bfd_reloc_code_real_type
) va_arg (args
, int);
1726 && (ep
->X_op
== O_constant
1727 || (ep
->X_op
== O_symbol
1728 && (r
== BFD_RELOC_HI16_S
1729 || r
== BFD_RELOC_HI16
1730 || r
== BFD_RELOC_MIPS_GOT_HI16
1731 || r
== BFD_RELOC_MIPS_CALL_HI16
))
1732 || (ep
->X_op
== O_subtract
1733 && now_seg
== text_section
1734 && r
== BFD_RELOC_PCREL_HI16_S
)));
1735 if (ep
->X_op
== O_constant
)
1737 insn
.insn_opcode
|= (ep
->X_add_number
>> 16) & 0xffff;
1739 r
= BFD_RELOC_UNUSED
;
1744 assert (ep
!= NULL
);
1746 * This allows macro() to pass an immediate expression for
1747 * creating short branches without creating a symbol.
1748 * Note that the expression still might come from the assembly
1749 * input, in which case the value is not checked for range nor
1750 * is a relocation entry generated (yuck).
1752 if (ep
->X_op
== O_constant
)
1754 insn
.insn_opcode
|= (ep
->X_add_number
>> 2) & 0xffff;
1758 r
= BFD_RELOC_16_PCREL_S2
;
1762 assert (ep
!= NULL
);
1763 r
= BFD_RELOC_MIPS_JMP
;
1772 assert (r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
1774 append_insn (place
, &insn
, ep
, r
, false);
1778 * Generate a "lui" instruction.
1781 macro_build_lui (place
, counter
, ep
, regnum
)
1787 expressionS high_expr
;
1788 struct mips_cl_insn insn
;
1789 bfd_reloc_code_real_type r
;
1790 CONST
char *name
= "lui";
1791 CONST
char *fmt
= "t,u";
1797 high_expr
.X_op
= O_constant
;
1798 high_expr
.X_add_number
= ep
->X_add_number
;
1801 if (high_expr
.X_op
== O_constant
)
1803 /* we can compute the instruction now without a relocation entry */
1804 if (high_expr
.X_add_number
& 0x8000)
1805 high_expr
.X_add_number
+= 0x10000;
1806 high_expr
.X_add_number
=
1807 ((unsigned long) high_expr
.X_add_number
>> 16) & 0xffff;
1808 r
= BFD_RELOC_UNUSED
;
1812 assert (ep
->X_op
== O_symbol
);
1813 /* _gp_disp is a special case, used from s_cpload. */
1814 assert (mips_pic
== NO_PIC
1815 || strcmp (S_GET_NAME (ep
->X_add_symbol
), "_gp_disp") == 0);
1816 r
= BFD_RELOC_HI16_S
;
1820 * If the macro is about to expand into a second instruction,
1821 * print a warning if needed. We need to pass ip as a parameter
1822 * to generate a better warning message here...
1824 if (mips_warn_about_macros
&& place
== NULL
&& *counter
== 1)
1825 as_warn ("Macro instruction expanded into multiple instructions");
1828 *counter
+= 1; /* bump instruction counter */
1830 insn
.insn_mo
= (struct mips_opcode
*) hash_find (op_hash
, name
);
1831 assert (insn
.insn_mo
);
1832 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
1833 assert (strcmp (fmt
, insn
.insn_mo
->args
) == 0);
1835 insn
.insn_opcode
= insn
.insn_mo
->match
| (regnum
<< OP_SH_RT
);
1836 if (r
== BFD_RELOC_UNUSED
)
1838 insn
.insn_opcode
|= high_expr
.X_add_number
;
1839 append_insn (place
, &insn
, NULL
, r
, false);
1842 append_insn (place
, &insn
, &high_expr
, r
, false);
1846 * Generates code to set the $at register to true (one)
1847 * if reg is less than the immediate expression.
1850 set_at (counter
, reg
, unsignedp
)
1855 if (imm_expr
.X_add_number
>= -0x8000 && imm_expr
.X_add_number
< 0x8000)
1856 macro_build ((char *) NULL
, counter
, &imm_expr
,
1857 unsignedp
? "sltiu" : "slti",
1858 "t,r,j", AT
, reg
, (int) BFD_RELOC_LO16
);
1861 load_register (counter
, AT
, &imm_expr
, 0);
1862 macro_build ((char *) NULL
, counter
, NULL
,
1863 unsignedp
? "sltu" : "slt",
1864 "d,v,t", AT
, reg
, AT
);
1868 /* Warn if an expression is not a constant. */
1871 check_absolute_expr (ip
, ex
)
1872 struct mips_cl_insn
*ip
;
1875 if (ex
->X_op
!= O_constant
)
1876 as_warn ("Instruction %s requires absolute expression", ip
->insn_mo
->name
);
1879 /* Count the leading zeroes by performing a binary chop. This is a
1880 bulky bit of source, but performance is a LOT better for the
1881 majority of values than a simple loop to count the bits:
1882 for (lcnt = 0; (lcnt < 32); lcnt++)
1883 if ((v) & (1 << (31 - lcnt)))
1885 However it is not code size friendly, and the gain will drop a bit
1886 on certain cached systems.
1888 #define COUNT_TOP_ZEROES(v) \
1889 (((v) & ~0xffff) == 0 \
1890 ? ((v) & ~0xff) == 0 \
1891 ? ((v) & ~0xf) == 0 \
1892 ? ((v) & ~0x3) == 0 \
1893 ? ((v) & ~0x1) == 0 \
1898 : ((v) & ~0x7) == 0 \
1901 : ((v) & ~0x3f) == 0 \
1902 ? ((v) & ~0x1f) == 0 \
1905 : ((v) & ~0x7f) == 0 \
1908 : ((v) & ~0xfff) == 0 \
1909 ? ((v) & ~0x3ff) == 0 \
1910 ? ((v) & ~0x1ff) == 0 \
1913 : ((v) & ~0x7ff) == 0 \
1916 : ((v) & ~0x3fff) == 0 \
1917 ? ((v) & ~0x1fff) == 0 \
1920 : ((v) & ~0x7fff) == 0 \
1923 : ((v) & ~0xffffff) == 0 \
1924 ? ((v) & ~0xfffff) == 0 \
1925 ? ((v) & ~0x3ffff) == 0 \
1926 ? ((v) & ~0x1ffff) == 0 \
1929 : ((v) & ~0x7ffff) == 0 \
1932 : ((v) & ~0x3fffff) == 0 \
1933 ? ((v) & ~0x1fffff) == 0 \
1936 : ((v) & ~0x7fffff) == 0 \
1939 : ((v) & ~0xfffffff) == 0 \
1940 ? ((v) & ~0x3ffffff) == 0 \
1941 ? ((v) & ~0x1ffffff) == 0 \
1944 : ((v) & ~0x7ffffff) == 0 \
1947 : ((v) & ~0x3fffffff) == 0 \
1948 ? ((v) & ~0x1fffffff) == 0 \
1951 : ((v) & ~0x7fffffff) == 0 \
1956 * This routine generates the least number of instructions neccessary to load
1957 * an absolute expression value into a register.
1960 load_register (counter
, reg
, ep
, dbl
)
1967 expressionS hi32
, lo32
, tmp
;
1969 if (ep
->X_op
!= O_big
)
1971 assert (ep
->X_op
== O_constant
);
1972 if (ep
->X_add_number
< 0x8000
1973 && (ep
->X_add_number
>= 0
1974 || (ep
->X_add_number
>= -0x8000
1977 || sizeof (ep
->X_add_number
) > 4))))
1979 /* We can handle 16 bit signed values with an addiu to
1980 $zero. No need to ever use daddiu here, since $zero and
1981 the result are always correct in 32 bit mode. */
1982 macro_build ((char *) NULL
, counter
, ep
, "addiu", "t,r,j", reg
, 0,
1983 (int) BFD_RELOC_LO16
);
1986 else if (ep
->X_add_number
>= 0 && ep
->X_add_number
< 0x10000)
1988 /* We can handle 16 bit unsigned values with an ori to
1990 macro_build ((char *) NULL
, counter
, ep
, "ori", "t,r,i", reg
, 0,
1991 (int) BFD_RELOC_LO16
);
1994 else if ((((ep
->X_add_number
&~ (offsetT
) 0x7fffffff) == 0
1995 || ((ep
->X_add_number
&~ (offsetT
) 0x7fffffff)
1996 == ~ (offsetT
) 0x7fffffff))
1999 || sizeof (ep
->X_add_number
) > 4
2000 || (ep
->X_add_number
& 0x80000000) == 0))
2001 || ((mips_isa
< 3 || !dbl
)
2002 && (ep
->X_add_number
&~ (offsetT
) 0xffffffff) == 0))
2004 /* 32 bit values require an lui. */
2005 macro_build ((char *) NULL
, counter
, ep
, "lui", "t,u", reg
,
2006 (int) BFD_RELOC_HI16
);
2007 if ((ep
->X_add_number
& 0xffff) != 0)
2008 macro_build ((char *) NULL
, counter
, ep
, "ori", "t,r,i", reg
, reg
,
2009 (int) BFD_RELOC_LO16
);
2014 /* The value is larger than 32 bits. */
2018 as_bad ("Number larger than 32 bits");
2019 macro_build ((char *) NULL
, counter
, ep
, "addiu", "t,r,j", reg
, 0,
2020 (int) BFD_RELOC_LO16
);
2024 if (ep
->X_op
!= O_big
)
2028 hi32
.X_add_number
>>= shift
;
2029 hi32
.X_add_number
&= 0xffffffff;
2030 if ((hi32
.X_add_number
& 0x80000000) != 0)
2031 hi32
.X_add_number
|= ~ (offsetT
) 0xffffffff;
2033 lo32
.X_add_number
&= 0xffffffff;
2037 assert (ep
->X_add_number
> 2);
2038 if (ep
->X_add_number
== 3)
2039 generic_bignum
[3] = 0;
2040 else if (ep
->X_add_number
> 4)
2041 as_bad ("Number larger than 64 bits");
2042 lo32
.X_op
= O_constant
;
2043 lo32
.X_add_number
= generic_bignum
[0] + (generic_bignum
[1] << 16);
2044 hi32
.X_op
= O_constant
;
2045 hi32
.X_add_number
= generic_bignum
[2] + (generic_bignum
[3] << 16);
2048 if (hi32
.X_add_number
== 0)
2052 if (hi32
.X_add_number
== 0xffffffff)
2054 if ((lo32
.X_add_number
& 0xffff8000) == 0xffff8000)
2056 macro_build ((char *) NULL
, counter
, &lo32
, "addiu", "t,r,j", reg
, 0,
2057 (int) BFD_RELOC_LO16
);
2060 if (lo32
.X_add_number
& 0x80000000)
2062 macro_build ((char *) NULL
, counter
, &lo32
, "lui", "t,u", reg
,
2063 (int) BFD_RELOC_HI16
);
2064 macro_build ((char *) NULL
, counter
, &lo32
, "ori", "t,r,i", reg
, reg
,
2065 (int) BFD_RELOC_LO16
);
2070 /* Check for 16bit shifted constant: */
2072 tmp
.X_add_number
= hi32
.X_add_number
<< shift
| lo32
.X_add_number
;
2073 /* We know that hi32 is non-zero, so start the mask on the first
2074 bit of the hi32 value: */
2078 if ((tmp
.X_add_number
& ~((offsetT
)0xffff << shift
)) == 0)
2080 tmp
.X_op
= O_constant
;
2081 tmp
.X_add_number
>>= shift
;
2082 macro_build ((char *) NULL
, counter
, &tmp
, "ori", "t,r,i", reg
, 0,
2083 (int) BFD_RELOC_LO16
);
2084 macro_build ((char *) NULL
, counter
, NULL
,
2085 (shift
>= 32) ? "dsll32" : "dsll",
2086 "d,w,<", reg
, reg
, (shift
>= 32) ? shift
- 32 : shift
);
2090 } while (shift
<= (64 - 16));
2094 tmp
.X_add_number
= hi32
.X_add_number
<< shift
| lo32
.X_add_number
;
2095 while ((tmp
.X_add_number
& 1) == 0)
2097 tmp
.X_add_number
>>= 1;
2100 if (((tmp
.X_add_number
+ 1) & tmp
.X_add_number
) == 0) /* (power-of-2 - 1) */
2102 shift
= COUNT_TOP_ZEROES((unsigned int)hi32
.X_add_number
);
2105 tmp
.X_op
= O_constant
;
2106 tmp
.X_add_number
= (offsetT
)-1;
2107 macro_build ((char *) NULL
, counter
, &tmp
, "addiu", "t,r,j", reg
, 0,
2108 (int) BFD_RELOC_LO16
); /* set all ones */
2112 macro_build ((char *) NULL
, counter
, NULL
,
2113 (freg
>= 32) ? "dsll32" : "dsll",
2115 (freg
>= 32) ? freg
- 32 : freg
);
2117 macro_build ((char *) NULL
, counter
, NULL
, (shift
>= 32) ? "dsrl32" : "dsrl",
2118 "d,w,<", reg
, reg
, (shift
>= 32) ? shift
- 32 : shift
);
2122 load_register (counter
, reg
, &hi32
, 0);
2125 if ((lo32
.X_add_number
& 0xffff0000) == 0)
2129 macro_build ((char *) NULL
, counter
, NULL
, "dsll32", "d,w,<", reg
,
2138 if ((freg
== 0) && (lo32
.X_add_number
== 0xffffffff))
2140 macro_build ((char *) NULL
, counter
, &lo32
, "lui", "t,u", reg
,
2141 (int) BFD_RELOC_HI16
);
2142 macro_build ((char *) NULL
, counter
, NULL
, "dsrl32", "d,w,<", reg
,
2149 macro_build ((char *) NULL
, counter
, NULL
, "dsll", "d,w,<", reg
,
2154 mid16
.X_add_number
>>= 16;
2155 macro_build ((char *) NULL
, counter
, &mid16
, "ori", "t,r,i", reg
,
2156 freg
, (int) BFD_RELOC_LO16
);
2157 macro_build ((char *) NULL
, counter
, NULL
, "dsll", "d,w,<", reg
,
2161 if ((lo32
.X_add_number
& 0xffff) != 0)
2162 macro_build ((char *) NULL
, counter
, &lo32
, "ori", "t,r,i", reg
, freg
,
2163 (int) BFD_RELOC_LO16
);
2166 /* Load an address into a register. */
2169 load_address (counter
, reg
, ep
)
2176 if (ep
->X_op
!= O_constant
2177 && ep
->X_op
!= O_symbol
)
2179 as_bad ("expression too complex");
2180 ep
->X_op
= O_constant
;
2183 if (ep
->X_op
== O_constant
)
2185 load_register (counter
, reg
, ep
, 0);
2189 if (mips_pic
== NO_PIC
)
2191 /* If this is a reference to a GP relative symbol, we want
2192 addiu $reg,$gp,<sym> (BFD_RELOC_MIPS_GPREL)
2194 lui $reg,<sym> (BFD_RELOC_HI16_S)
2195 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
2196 If we have an addend, we always use the latter form. */
2197 if ((valueT
) ep
->X_add_number
>= MAX_GPREL_OFFSET
2198 || nopic_need_relax (ep
->X_add_symbol
))
2203 macro_build ((char *) NULL
, counter
, ep
,
2204 mips_isa
< 3 ? "addiu" : "daddiu",
2205 "t,r,j", reg
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
2206 p
= frag_var (rs_machine_dependent
, 8, 0,
2207 RELAX_ENCODE (4, 8, 0, 4, 0, mips_warn_about_macros
),
2208 ep
->X_add_symbol
, (long) 0, (char *) NULL
);
2210 macro_build_lui (p
, counter
, ep
, reg
);
2213 macro_build (p
, counter
, ep
,
2214 mips_isa
< 3 ? "addiu" : "daddiu",
2215 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
2217 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
2221 /* If this is a reference to an external symbol, we want
2222 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
2224 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
2226 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
2227 If there is a constant, it must be added in after. */
2228 ex
.X_add_number
= ep
->X_add_number
;
2229 ep
->X_add_number
= 0;
2231 macro_build ((char *) NULL
, counter
, ep
,
2232 mips_isa
< 3 ? "lw" : "ld",
2233 "t,o(b)", reg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
2234 macro_build ((char *) NULL
, counter
, (expressionS
*) NULL
, "nop", "");
2235 p
= frag_var (rs_machine_dependent
, 4, 0,
2236 RELAX_ENCODE (0, 4, -8, 0, 0, mips_warn_about_macros
),
2237 ep
->X_add_symbol
, (long) 0, (char *) NULL
);
2238 macro_build (p
, counter
, ep
,
2239 mips_isa
< 3 ? "addiu" : "daddiu",
2240 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
2241 if (ex
.X_add_number
!= 0)
2243 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
2244 as_bad ("PIC code offset overflow (max 16 signed bits)");
2245 ex
.X_op
= O_constant
;
2246 macro_build ((char *) NULL
, counter
, &ex
,
2247 mips_isa
< 3 ? "addiu" : "daddiu",
2248 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
2251 else if (mips_pic
== SVR4_PIC
)
2256 /* This is the large GOT case. If this is a reference to an
2257 external symbol, we want
2258 lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
2260 lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16)
2261 Otherwise, for a reference to a local symbol, we want
2262 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
2264 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
2265 If there is a constant, it must be added in after. */
2266 ex
.X_add_number
= ep
->X_add_number
;
2267 ep
->X_add_number
= 0;
2268 if (reg_needs_delay (GP
))
2273 macro_build ((char *) NULL
, counter
, ep
, "lui", "t,u", reg
,
2274 (int) BFD_RELOC_MIPS_GOT_HI16
);
2275 macro_build ((char *) NULL
, counter
, (expressionS
*) NULL
,
2276 mips_isa
< 3 ? "addu" : "daddu",
2277 "d,v,t", reg
, reg
, GP
);
2278 macro_build ((char *) NULL
, counter
, ep
,
2279 mips_isa
< 3 ? "lw" : "ld",
2280 "t,o(b)", reg
, (int) BFD_RELOC_MIPS_GOT_LO16
, reg
);
2281 p
= frag_var (rs_machine_dependent
, 12 + off
, 0,
2282 RELAX_ENCODE (12, 12 + off
, off
, 8 + off
, 0,
2283 mips_warn_about_macros
),
2284 ep
->X_add_symbol
, (long) 0, (char *) NULL
);
2287 /* We need a nop before loading from $gp. This special
2288 check is required because the lui which starts the main
2289 instruction stream does not refer to $gp, and so will not
2290 insert the nop which may be required. */
2291 macro_build (p
, counter
, (expressionS
*) NULL
, "nop", "");
2294 macro_build (p
, counter
, ep
,
2295 mips_isa
< 3 ? "lw" : "ld",
2296 "t,o(b)", reg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
2298 macro_build (p
, counter
, (expressionS
*) NULL
, "nop", "");
2300 macro_build (p
, counter
, ep
,
2301 mips_isa
< 3 ? "addiu" : "daddiu",
2302 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
2303 if (ex
.X_add_number
!= 0)
2305 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
2306 as_bad ("PIC code offset overflow (max 16 signed bits)");
2307 ex
.X_op
= O_constant
;
2308 macro_build ((char *) NULL
, counter
, &ex
,
2309 mips_isa
< 3 ? "addiu" : "daddiu",
2310 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
2313 else if (mips_pic
== EMBEDDED_PIC
)
2316 addiu $reg,$gp,<sym> (BFD_RELOC_MIPS_GPREL)
2318 macro_build ((char *) NULL
, counter
, ep
,
2319 mips_isa
< 3 ? "addiu" : "daddiu",
2320 "t,r,j", reg
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
2328 * This routine implements the seemingly endless macro or synthesized
2329 * instructions and addressing modes in the mips assembly language. Many
2330 * of these macros are simple and are similar to each other. These could
2331 * probably be handled by some kind of table or grammer aproach instead of
2332 * this verbose method. Others are not simple macros but are more like
2333 * optimizing code generation.
2334 * One interesting optimization is when several store macros appear
2335 * consecutivly that would load AT with the upper half of the same address.
2336 * The ensuing load upper instructions are ommited. This implies some kind
2337 * of global optimization. We currently only optimize within a single macro.
2338 * For many of the load and store macros if the address is specified as a
2339 * constant expression in the first 64k of memory (ie ld $2,0x4000c) we
2340 * first load register 'at' with zero and use it as the base register. The
2341 * mips assembler simply uses register $zero. Just one tiny optimization
2346 struct mips_cl_insn
*ip
;
2348 register int treg
, sreg
, dreg
, breg
;
2363 bfd_reloc_code_real_type r
;
2365 int hold_mips_optimize
;
2367 treg
= (ip
->insn_opcode
>> 16) & 0x1f;
2368 dreg
= (ip
->insn_opcode
>> 11) & 0x1f;
2369 sreg
= breg
= (ip
->insn_opcode
>> 21) & 0x1f;
2370 mask
= ip
->insn_mo
->mask
;
2372 expr1
.X_op
= O_constant
;
2373 expr1
.X_op_symbol
= NULL
;
2374 expr1
.X_add_symbol
= NULL
;
2375 expr1
.X_add_number
= 1;
2387 mips_emit_delays ();
2389 mips_any_noreorder
= 1;
2391 expr1
.X_add_number
= 8;
2392 macro_build ((char *) NULL
, &icnt
, &expr1
, "bgez", "s,p", sreg
);
2394 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
2396 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
, sreg
, 0);
2397 macro_build ((char *) NULL
, &icnt
, NULL
,
2398 dbl
? "dsub" : "sub",
2399 "d,v,t", dreg
, 0, sreg
);
2422 if (imm_expr
.X_add_number
>= -0x8000 && imm_expr
.X_add_number
< 0x8000)
2424 macro_build ((char *) NULL
, &icnt
, &imm_expr
, s
, "t,r,j", treg
, sreg
,
2425 (int) BFD_RELOC_LO16
);
2428 load_register (&icnt
, AT
, &imm_expr
, dbl
);
2429 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "d,v,t", treg
, sreg
, AT
);
2448 if (imm_expr
.X_add_number
>= 0 && imm_expr
.X_add_number
< 0x10000)
2450 if (mask
!= M_NOR_I
)
2451 macro_build ((char *) NULL
, &icnt
, &imm_expr
, s
, "t,r,i", treg
,
2452 sreg
, (int) BFD_RELOC_LO16
);
2455 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "ori", "t,r,i",
2456 treg
, sreg
, (int) BFD_RELOC_LO16
);
2457 macro_build ((char *) NULL
, &icnt
, NULL
, "nor", "d,v,t",
2463 load_register (&icnt
, AT
, &imm_expr
, 0);
2464 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "d,v,t", treg
, sreg
, AT
);
2481 if (imm_expr
.X_add_number
== 0)
2483 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "s,t,p", sreg
,
2487 load_register (&icnt
, AT
, &imm_expr
, 0);
2488 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "s,t,p", sreg
, AT
);
2496 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2497 likely
? "bgezl" : "bgez",
2503 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2504 likely
? "blezl" : "blez",
2508 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", AT
, sreg
, treg
);
2509 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2510 likely
? "beql" : "beq",
2517 /* check for > max integer */
2518 maxnum
= 0x7fffffff;
2526 if (imm_expr
.X_add_number
>= maxnum
2527 && (mips_isa
< 3 || sizeof (maxnum
) > 4))
2530 /* result is always false */
2533 as_warn ("Branch %s is always false (nop)", ip
->insn_mo
->name
);
2534 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
2538 as_warn ("Branch likely %s is always false", ip
->insn_mo
->name
);
2539 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "bnel",
2544 imm_expr
.X_add_number
++;
2548 if (mask
== M_BGEL_I
)
2550 if (imm_expr
.X_add_number
== 0)
2552 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2553 likely
? "bgezl" : "bgez",
2557 if (imm_expr
.X_add_number
== 1)
2559 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2560 likely
? "bgtzl" : "bgtz",
2564 maxnum
= 0x7fffffff;
2572 maxnum
= - maxnum
- 1;
2573 if (imm_expr
.X_add_number
<= maxnum
2574 && (mips_isa
< 3 || sizeof (maxnum
) > 4))
2577 /* result is always true */
2578 as_warn ("Branch %s is always true", ip
->insn_mo
->name
);
2579 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "b", "p");
2582 set_at (&icnt
, sreg
, 0);
2583 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2584 likely
? "beql" : "beq",
2595 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2596 likely
? "beql" : "beq",
2600 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", AT
, sreg
,
2602 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2603 likely
? "beql" : "beq",
2610 if (sreg
== 0 || imm_expr
.X_add_number
== -1)
2612 imm_expr
.X_add_number
++;
2616 if (mask
== M_BGEUL_I
)
2618 if (imm_expr
.X_add_number
== 0)
2620 if (imm_expr
.X_add_number
== 1)
2622 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2623 likely
? "bnel" : "bne",
2627 set_at (&icnt
, sreg
, 1);
2628 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2629 likely
? "beql" : "beq",
2638 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2639 likely
? "bgtzl" : "bgtz",
2645 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2646 likely
? "bltzl" : "bltz",
2650 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", AT
, treg
, sreg
);
2651 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2652 likely
? "bnel" : "bne",
2661 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2662 likely
? "bnel" : "bne",
2668 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", AT
, treg
,
2670 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2671 likely
? "bnel" : "bne",
2680 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2681 likely
? "blezl" : "blez",
2687 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2688 likely
? "bgezl" : "bgez",
2692 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", AT
, treg
, sreg
);
2693 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2694 likely
? "beql" : "beq",
2701 maxnum
= 0x7fffffff;
2709 if (imm_expr
.X_add_number
>= maxnum
2710 && (mips_isa
< 3 || sizeof (maxnum
) > 4))
2712 imm_expr
.X_add_number
++;
2716 if (mask
== M_BLTL_I
)
2718 if (imm_expr
.X_add_number
== 0)
2720 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2721 likely
? "bltzl" : "bltz",
2725 if (imm_expr
.X_add_number
== 1)
2727 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2728 likely
? "blezl" : "blez",
2732 set_at (&icnt
, sreg
, 0);
2733 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2734 likely
? "bnel" : "bne",
2743 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2744 likely
? "beql" : "beq",
2750 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", AT
, treg
,
2752 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2753 likely
? "beql" : "beq",
2760 if (sreg
== 0 || imm_expr
.X_add_number
== -1)
2762 imm_expr
.X_add_number
++;
2766 if (mask
== M_BLTUL_I
)
2768 if (imm_expr
.X_add_number
== 0)
2770 if (imm_expr
.X_add_number
== 1)
2772 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2773 likely
? "beql" : "beq",
2777 set_at (&icnt
, sreg
, 1);
2778 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2779 likely
? "bnel" : "bne",
2788 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2789 likely
? "bltzl" : "bltz",
2795 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2796 likely
? "bgtzl" : "bgtz",
2800 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", AT
, sreg
, treg
);
2801 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2802 likely
? "bnel" : "bne",
2813 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2814 likely
? "bnel" : "bne",
2818 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", AT
, sreg
,
2820 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2821 likely
? "bnel" : "bne",
2837 as_warn ("Divide by zero.");
2839 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", 0, 0);
2841 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 7);
2845 mips_emit_delays ();
2847 mips_any_noreorder
= 1;
2848 macro_build ((char *) NULL
, &icnt
, NULL
,
2849 dbl
? "ddiv" : "div",
2850 "z,s,t", sreg
, treg
);
2852 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", treg
, 0);
2855 expr1
.X_add_number
= 8;
2856 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", treg
, 0);
2857 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
2858 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 7);
2860 expr1
.X_add_number
= -1;
2861 macro_build ((char *) NULL
, &icnt
, &expr1
,
2862 dbl
? "daddiu" : "addiu",
2863 "t,r,j", AT
, 0, (int) BFD_RELOC_LO16
);
2864 expr1
.X_add_number
= mips_trap
? (dbl
? 12 : 8) : (dbl
? 20 : 16);
2865 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", treg
, AT
);
2868 expr1
.X_add_number
= 1;
2869 macro_build ((char *) NULL
, &icnt
, &expr1
, "daddiu", "t,r,j", AT
, 0,
2870 (int) BFD_RELOC_LO16
);
2871 macro_build ((char *) NULL
, &icnt
, NULL
, "dsll32", "d,w,<", AT
, AT
,
2876 expr1
.X_add_number
= 0x80000000;
2877 macro_build ((char *) NULL
, &icnt
, &expr1
, "lui", "t,u", AT
,
2878 (int) BFD_RELOC_HI16
);
2881 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", sreg
, AT
);
2884 expr1
.X_add_number
= 8;
2885 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", sreg
, AT
);
2886 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
2887 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 6);
2890 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d", dreg
);
2929 if (imm_expr
.X_add_number
== 0)
2931 as_warn ("Divide by zero.");
2933 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", 0, 0);
2935 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 7);
2938 if (imm_expr
.X_add_number
== 1)
2940 if (strcmp (s2
, "mflo") == 0)
2941 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
,
2944 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
, 0);
2947 if (imm_expr
.X_add_number
== -1
2948 && s
[strlen (s
) - 1] != 'u')
2950 if (strcmp (s2
, "mflo") == 0)
2953 macro_build ((char *) NULL
, &icnt
, NULL
, "dneg", "d,w", dreg
,
2956 macro_build ((char *) NULL
, &icnt
, NULL
, "neg", "d,w", dreg
,
2960 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
, 0);
2964 load_register (&icnt
, AT
, &imm_expr
, dbl
);
2965 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "z,s,t", sreg
, AT
);
2966 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "d", dreg
);
2985 mips_emit_delays ();
2987 mips_any_noreorder
= 1;
2988 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "z,s,t", sreg
, treg
);
2990 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", treg
, 0);
2993 expr1
.X_add_number
= 8;
2994 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", treg
, 0);
2995 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
2996 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 7);
2999 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "d", dreg
);
3005 /* Load the address of a symbol into a register. If breg is not
3006 zero, we then add a base register to it. */
3008 /* When generating embedded PIC code, we permit expressions of
3011 where bar is an address in the .text section. These are used
3012 when getting the addresses of functions. We don't permit
3013 X_add_number to be non-zero, because if the symbol is
3014 external the relaxing code needs to know that any addend is
3015 purely the offset to X_op_symbol. */
3016 if (mips_pic
== EMBEDDED_PIC
3017 && offset_expr
.X_op
== O_subtract
3018 && now_seg
== text_section
3019 && (offset_expr
.X_op_symbol
->sy_value
.X_op
== O_constant
3020 ? S_GET_SEGMENT (offset_expr
.X_op_symbol
) == text_section
3021 : (offset_expr
.X_op_symbol
->sy_value
.X_op
== O_symbol
3022 && (S_GET_SEGMENT (offset_expr
.X_op_symbol
3023 ->sy_value
.X_add_symbol
)
3026 && offset_expr
.X_add_number
== 0)
3028 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
3029 treg
, (int) BFD_RELOC_PCREL_HI16_S
);
3030 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3031 mips_isa
< 3 ? "addiu" : "daddiu",
3032 "t,r,j", treg
, treg
, (int) BFD_RELOC_PCREL_LO16
);
3036 if (offset_expr
.X_op
!= O_symbol
3037 && offset_expr
.X_op
!= O_constant
)
3039 as_bad ("expression too complex");
3040 offset_expr
.X_op
= O_constant
;
3054 if (offset_expr
.X_op
== O_constant
)
3055 load_register (&icnt
, tempreg
, &offset_expr
, dbl
);
3056 else if (mips_pic
== NO_PIC
)
3058 /* If this is a reference to an GP relative symbol, we want
3059 addiu $tempreg,$gp,<sym> (BFD_RELOC_MIPS_GPREL)
3061 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
3062 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
3063 If we have a constant, we need two instructions anyhow,
3064 so we may as well always use the latter form. */
3065 if ((valueT
) offset_expr
.X_add_number
>= MAX_GPREL_OFFSET
3066 || nopic_need_relax (offset_expr
.X_add_symbol
))
3071 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3072 mips_isa
< 3 ? "addiu" : "daddiu",
3073 "t,r,j", tempreg
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
3074 p
= frag_var (rs_machine_dependent
, 8, 0,
3075 RELAX_ENCODE (4, 8, 0, 4, 0,
3076 mips_warn_about_macros
),
3077 offset_expr
.X_add_symbol
, (long) 0,
3080 macro_build_lui (p
, &icnt
, &offset_expr
, tempreg
);
3083 macro_build (p
, &icnt
, &offset_expr
,
3084 mips_isa
< 3 ? "addiu" : "daddiu",
3085 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
3087 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
3089 /* If this is a reference to an external symbol, and there
3090 is no constant, we want
3091 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3092 For a local symbol, we want
3093 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3095 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
3097 If we have a small constant, and this is a reference to
3098 an external symbol, we want
3099 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3101 addiu $tempreg,$tempreg,<constant>
3102 For a local symbol, we want the same instruction
3103 sequence, but we output a BFD_RELOC_LO16 reloc on the
3106 If we have a large constant, and this is a reference to
3107 an external symbol, we want
3108 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3109 lui $at,<hiconstant>
3110 addiu $at,$at,<loconstant>
3111 addu $tempreg,$tempreg,$at
3112 For a local symbol, we want the same instruction
3113 sequence, but we output a BFD_RELOC_LO16 reloc on the
3114 addiu instruction. */
3115 expr1
.X_add_number
= offset_expr
.X_add_number
;
3116 offset_expr
.X_add_number
= 0;
3118 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3120 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
3121 if (expr1
.X_add_number
== 0)
3129 /* We're going to put in an addu instruction using
3130 tempreg, so we may as well insert the nop right
3132 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3136 p
= frag_var (rs_machine_dependent
, 8 - off
, 0,
3137 RELAX_ENCODE (0, 8 - off
, -4 - off
, 4 - off
, 0,
3139 ? mips_warn_about_macros
3141 offset_expr
.X_add_symbol
, (long) 0,
3145 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
3148 macro_build (p
, &icnt
, &expr1
,
3149 mips_isa
< 3 ? "addiu" : "daddiu",
3150 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
3151 /* FIXME: If breg == 0, and the next instruction uses
3152 $tempreg, then if this variant case is used an extra
3153 nop will be generated. */
3155 else if (expr1
.X_add_number
>= -0x8000
3156 && expr1
.X_add_number
< 0x8000)
3158 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3160 macro_build ((char *) NULL
, &icnt
, &expr1
,
3161 mips_isa
< 3 ? "addiu" : "daddiu",
3162 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
3163 (void) frag_var (rs_machine_dependent
, 0, 0,
3164 RELAX_ENCODE (0, 0, -12, -4, 0, 0),
3165 offset_expr
.X_add_symbol
, (long) 0,
3172 /* If we are going to add in a base register, and the
3173 target register and the base register are the same,
3174 then we are using AT as a temporary register. Since
3175 we want to load the constant into AT, we add our
3176 current AT (from the global offset table) and the
3177 register into the register now, and pretend we were
3178 not using a base register. */
3183 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3185 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3186 mips_isa
< 3 ? "addu" : "daddu",
3187 "d,v,t", treg
, AT
, breg
);
3193 /* Set mips_optimize around the lui instruction to avoid
3194 inserting an unnecessary nop after the lw. */
3195 hold_mips_optimize
= mips_optimize
;
3197 macro_build_lui ((char *) NULL
, &icnt
, &expr1
, AT
);
3198 mips_optimize
= hold_mips_optimize
;
3200 macro_build ((char *) NULL
, &icnt
, &expr1
,
3201 mips_isa
< 3 ? "addiu" : "daddiu",
3202 "t,r,j", AT
, AT
, (int) BFD_RELOC_LO16
);
3203 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3204 mips_isa
< 3 ? "addu" : "daddu",
3205 "d,v,t", tempreg
, tempreg
, AT
);
3206 (void) frag_var (rs_machine_dependent
, 0, 0,
3207 RELAX_ENCODE (0, 0, -16 + off1
, -8, 0, 0),
3208 offset_expr
.X_add_symbol
, (long) 0,
3213 else if (mips_pic
== SVR4_PIC
)
3217 /* This is the large GOT case. If this is a reference to an
3218 external symbol, and there is no constant, we want
3219 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
3220 addu $tempreg,$tempreg,$gp
3221 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
3222 For a local symbol, we want
3223 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3225 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
3227 If we have a small constant, and this is a reference to
3228 an external symbol, we want
3229 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
3230 addu $tempreg,$tempreg,$gp
3231 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
3233 addiu $tempreg,$tempreg,<constant>
3234 For a local symbol, we want
3235 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3237 addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16)
3239 If we have a large constant, and this is a reference to
3240 an external symbol, we want
3241 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
3242 addu $tempreg,$tempreg,$gp
3243 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
3244 lui $at,<hiconstant>
3245 addiu $at,$at,<loconstant>
3246 addu $tempreg,$tempreg,$at
3247 For a local symbol, we want
3248 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3249 lui $at,<hiconstant>
3250 addiu $at,$at,<loconstant> (BFD_RELOC_LO16)
3251 addu $tempreg,$tempreg,$at
3253 expr1
.X_add_number
= offset_expr
.X_add_number
;
3254 offset_expr
.X_add_number
= 0;
3256 if (reg_needs_delay (GP
))
3260 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
3261 tempreg
, (int) BFD_RELOC_MIPS_GOT_HI16
);
3262 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3263 mips_isa
< 3 ? "addu" : "daddu",
3264 "d,v,t", tempreg
, tempreg
, GP
);
3265 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3267 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT_LO16
,
3269 if (expr1
.X_add_number
== 0)
3277 /* We're going to put in an addu instruction using
3278 tempreg, so we may as well insert the nop right
3280 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3285 p
= frag_var (rs_machine_dependent
, 12 + gpdel
, 0,
3286 RELAX_ENCODE (12 + off
, 12 + gpdel
, gpdel
,
3289 ? mips_warn_about_macros
3291 offset_expr
.X_add_symbol
, (long) 0,
3294 else if (expr1
.X_add_number
>= -0x8000
3295 && expr1
.X_add_number
< 0x8000)
3297 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3299 macro_build ((char *) NULL
, &icnt
, &expr1
,
3300 mips_isa
< 3 ? "addiu" : "daddiu",
3301 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
3303 p
= frag_var (rs_machine_dependent
, 12 + gpdel
, 0,
3304 RELAX_ENCODE (20, 12 + gpdel
, gpdel
, 8 + gpdel
, 0,
3306 ? mips_warn_about_macros
3308 offset_expr
.X_add_symbol
, (long) 0,
3315 /* If we are going to add in a base register, and the
3316 target register and the base register are the same,
3317 then we are using AT as a temporary register. Since
3318 we want to load the constant into AT, we add our
3319 current AT (from the global offset table) and the
3320 register into the register now, and pretend we were
3321 not using a base register. */
3329 assert (tempreg
== AT
);
3330 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3332 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3333 mips_isa
< 3 ? "addu" : "daddu",
3334 "d,v,t", treg
, AT
, breg
);
3339 /* Set mips_optimize around the lui instruction to avoid
3340 inserting an unnecessary nop after the lw. */
3341 hold_mips_optimize
= mips_optimize
;
3343 macro_build_lui ((char *) NULL
, &icnt
, &expr1
, AT
);
3344 mips_optimize
= hold_mips_optimize
;
3346 macro_build ((char *) NULL
, &icnt
, &expr1
,
3347 mips_isa
< 3 ? "addiu" : "daddiu",
3348 "t,r,j", AT
, AT
, (int) BFD_RELOC_LO16
);
3349 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3350 mips_isa
< 3 ? "addu" : "daddu",
3351 "d,v,t", dreg
, dreg
, AT
);
3353 p
= frag_var (rs_machine_dependent
, 16 + gpdel
+ adj
, 0,
3354 RELAX_ENCODE (24 + adj
, 16 + gpdel
+ adj
, gpdel
,
3357 ? mips_warn_about_macros
3359 offset_expr
.X_add_symbol
, (long) 0,
3367 /* This is needed because this instruction uses $gp, but
3368 the first instruction on the main stream does not. */
3369 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
3372 macro_build (p
, &icnt
, &offset_expr
,
3374 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
3376 if (expr1
.X_add_number
>= -0x8000
3377 && expr1
.X_add_number
< 0x8000)
3379 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
3381 macro_build (p
, &icnt
, &expr1
,
3382 mips_isa
< 3 ? "addiu" : "daddiu",
3383 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
3384 /* FIXME: If add_number is 0, and there was no base
3385 register, the external symbol case ended with a load,
3386 so if the symbol turns out to not be external, and
3387 the next instruction uses tempreg, an unnecessary nop
3388 will be inserted. */
3394 /* We must add in the base register now, as in the
3395 external symbol case. */
3396 assert (tempreg
== AT
);
3397 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
3399 macro_build (p
, &icnt
, (expressionS
*) NULL
,
3400 mips_isa
< 3 ? "addu" : "daddu",
3401 "d,v,t", treg
, AT
, breg
);
3404 /* We set breg to 0 because we have arranged to add
3405 it in in both cases. */
3409 macro_build_lui (p
, &icnt
, &expr1
, AT
);
3411 macro_build (p
, &icnt
, &expr1
,
3412 mips_isa
< 3 ? "addiu" : "daddiu",
3413 "t,r,j", AT
, AT
, (int) BFD_RELOC_LO16
);
3415 macro_build (p
, &icnt
, (expressionS
*) NULL
,
3416 mips_isa
< 3 ? "addu" : "daddu",
3417 "d,v,t", tempreg
, tempreg
, AT
);
3421 else if (mips_pic
== EMBEDDED_PIC
)
3424 addiu $tempreg,$gp,<sym> (BFD_RELOC_MIPS_GPREL)
3426 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3427 mips_isa
< 3 ? "addiu" : "daddiu",
3428 "t,r,j", tempreg
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
3434 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3435 mips_isa
< 3 ? "addu" : "daddu",
3436 "d,v,t", treg
, tempreg
, breg
);
3444 /* The j instruction may not be used in PIC code, since it
3445 requires an absolute address. We convert it to a b
3447 if (mips_pic
== NO_PIC
)
3448 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "j", "a");
3450 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "b", "p");
3453 /* The jal instructions must be handled as macros because when
3454 generating PIC code they expand to multi-instruction
3455 sequences. Normally they are simple instructions. */
3460 if (mips_pic
== NO_PIC
3461 || mips_pic
== EMBEDDED_PIC
)
3462 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "jalr",
3464 else if (mips_pic
== SVR4_PIC
)
3466 if (sreg
!= PIC_CALL_REG
)
3467 as_warn ("MIPS PIC call to register other than $25");
3469 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "jalr",
3471 if (mips_cprestore_offset
< 0)
3472 as_warn ("No .cprestore pseudo-op used in PIC code");
3475 expr1
.X_add_number
= mips_cprestore_offset
;
3476 macro_build ((char *) NULL
, &icnt
, &expr1
,
3477 mips_isa
< 3 ? "lw" : "ld",
3478 "t,o(b)", GP
, (int) BFD_RELOC_LO16
, mips_frame_reg
);
3487 if (mips_pic
== NO_PIC
)
3488 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "jal", "a");
3489 else if (mips_pic
== SVR4_PIC
)
3491 /* If this is a reference to an external symbol, and we are
3492 using a small GOT, we want
3493 lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
3497 lw $gp,cprestore($sp)
3498 The cprestore value is set using the .cprestore
3499 pseudo-op. If we are using a big GOT, we want
3500 lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16)
3502 lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16)
3506 lw $gp,cprestore($sp)
3507 If the symbol is not external, we want
3508 lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3510 addiu $25,$25,<sym> (BFD_RELOC_LO16)
3513 lw $gp,cprestore($sp) */
3517 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3518 mips_isa
< 3 ? "lw" : "ld",
3519 "t,o(b)", PIC_CALL_REG
,
3520 (int) BFD_RELOC_MIPS_CALL16
, GP
);
3521 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3523 p
= frag_var (rs_machine_dependent
, 4, 0,
3524 RELAX_ENCODE (0, 4, -8, 0, 0, 0),
3525 offset_expr
.X_add_symbol
, (long) 0, (char *) NULL
);
3531 if (reg_needs_delay (GP
))
3535 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
3536 PIC_CALL_REG
, (int) BFD_RELOC_MIPS_CALL_HI16
);
3537 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3538 mips_isa
< 3 ? "addu" : "daddu",
3539 "d,v,t", PIC_CALL_REG
, PIC_CALL_REG
, GP
);
3540 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3541 mips_isa
< 3 ? "lw" : "ld",
3542 "t,o(b)", PIC_CALL_REG
,
3543 (int) BFD_RELOC_MIPS_CALL_LO16
, PIC_CALL_REG
);
3544 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3546 p
= frag_var (rs_machine_dependent
, 12 + gpdel
, 0,
3547 RELAX_ENCODE (16, 12 + gpdel
, gpdel
, 8 + gpdel
,
3549 offset_expr
.X_add_symbol
, (long) 0, (char *) NULL
);
3552 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
3555 macro_build (p
, &icnt
, &offset_expr
,
3556 mips_isa
< 3 ? "lw" : "ld",
3557 "t,o(b)", PIC_CALL_REG
,
3558 (int) BFD_RELOC_MIPS_GOT16
, GP
);
3560 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
3563 macro_build (p
, &icnt
, &offset_expr
,
3564 mips_isa
< 3 ? "addiu" : "daddiu",
3565 "t,r,j", PIC_CALL_REG
, PIC_CALL_REG
,
3566 (int) BFD_RELOC_LO16
);
3567 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3568 "jalr", "s", PIC_CALL_REG
);
3569 if (mips_cprestore_offset
< 0)
3570 as_warn ("No .cprestore pseudo-op used in PIC code");
3574 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3576 expr1
.X_add_number
= mips_cprestore_offset
;
3577 macro_build ((char *) NULL
, &icnt
, &expr1
,
3578 mips_isa
< 3 ? "lw" : "ld",
3579 "t,o(b)", GP
, (int) BFD_RELOC_LO16
,
3583 else if (mips_pic
== EMBEDDED_PIC
)
3585 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "bal", "p");
3586 /* The linker may expand the call to a longer sequence which
3587 uses $at, so we must break rather than return. */
3663 if (breg
== treg
|| coproc
|| lr
)
3732 if (mask
== M_LWC1_AB
3733 || mask
== M_SWC1_AB
3734 || mask
== M_LDC1_AB
3735 || mask
== M_SDC1_AB
3744 if (offset_expr
.X_op
!= O_constant
3745 && offset_expr
.X_op
!= O_symbol
)
3747 as_bad ("expression too complex");
3748 offset_expr
.X_op
= O_constant
;
3751 /* A constant expression in PIC code can be handled just as it
3752 is in non PIC code. */
3753 if (mips_pic
== NO_PIC
3754 || offset_expr
.X_op
== O_constant
)
3756 /* If this is a reference to a GP relative symbol, and there
3757 is no base register, we want
3758 <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL)
3759 Otherwise, if there is no base register, we want
3760 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
3761 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
3762 If we have a constant, we need two instructions anyhow,
3763 so we always use the latter form.
3765 If we have a base register, and this is a reference to a
3766 GP relative symbol, we want
3767 addu $tempreg,$breg,$gp
3768 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GPREL)
3770 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
3771 addu $tempreg,$tempreg,$breg
3772 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
3773 With a constant we always use the latter case. */
3776 if ((valueT
) offset_expr
.X_add_number
>= MAX_GPREL_OFFSET
3777 || nopic_need_relax (offset_expr
.X_add_symbol
))
3782 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
3783 treg
, (int) BFD_RELOC_MIPS_GPREL
, GP
);
3784 p
= frag_var (rs_machine_dependent
, 8, 0,
3785 RELAX_ENCODE (4, 8, 0, 4, 0,
3786 (mips_warn_about_macros
3787 || (used_at
&& mips_noat
))),
3788 offset_expr
.X_add_symbol
, (long) 0,
3792 macro_build_lui (p
, &icnt
, &offset_expr
, tempreg
);
3795 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
, treg
,
3796 (int) BFD_RELOC_LO16
, tempreg
);
3800 if ((valueT
) offset_expr
.X_add_number
>= MAX_GPREL_OFFSET
3801 || nopic_need_relax (offset_expr
.X_add_symbol
))
3806 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3807 mips_isa
< 3 ? "addu" : "daddu",
3808 "d,v,t", tempreg
, breg
, GP
);
3809 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
3810 treg
, (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
3811 p
= frag_var (rs_machine_dependent
, 12, 0,
3812 RELAX_ENCODE (8, 12, 0, 8, 0, 0),
3813 offset_expr
.X_add_symbol
, (long) 0,
3816 macro_build_lui (p
, &icnt
, &offset_expr
, tempreg
);
3819 macro_build (p
, &icnt
, (expressionS
*) NULL
,
3820 mips_isa
< 3 ? "addu" : "daddu",
3821 "d,v,t", tempreg
, tempreg
, breg
);
3824 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
, treg
,
3825 (int) BFD_RELOC_LO16
, tempreg
);
3828 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
3830 /* If this is a reference to an external symbol, we want
3831 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3833 <op> $treg,0($tempreg)
3835 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3837 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
3838 <op> $treg,0($tempreg)
3839 If there is a base register, we add it to $tempreg before
3840 the <op>. If there is a constant, we stick it in the
3841 <op> instruction. We don't handle constants larger than
3842 16 bits, because we have no way to load the upper 16 bits
3843 (actually, we could handle them for the subset of cases
3844 in which we are not using $at). */
3845 assert (offset_expr
.X_op
== O_symbol
);
3846 expr1
.X_add_number
= offset_expr
.X_add_number
;
3847 offset_expr
.X_add_number
= 0;
3848 if (expr1
.X_add_number
< -0x8000
3849 || expr1
.X_add_number
>= 0x8000)
3850 as_bad ("PIC code offset overflow (max 16 signed bits)");
3852 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3853 mips_isa
< 3 ? "lw" : "ld",
3854 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
3855 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
3856 p
= frag_var (rs_machine_dependent
, 4, 0,
3857 RELAX_ENCODE (0, 4, -8, 0, 0, 0),
3858 offset_expr
.X_add_symbol
, (long) 0,
3860 macro_build (p
, &icnt
, &offset_expr
,
3861 mips_isa
< 3 ? "addiu" : "daddiu",
3862 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
3864 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3865 mips_isa
< 3 ? "addu" : "daddu",
3866 "d,v,t", tempreg
, tempreg
, breg
);
3867 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
, treg
,
3868 (int) BFD_RELOC_LO16
, tempreg
);
3870 else if (mips_pic
== SVR4_PIC
)
3874 /* If this is a reference to an external symbol, we want
3875 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
3876 addu $tempreg,$tempreg,$gp
3877 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
3878 <op> $treg,0($tempreg)
3880 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3882 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
3883 <op> $treg,0($tempreg)
3884 If there is a base register, we add it to $tempreg before
3885 the <op>. If there is a constant, we stick it in the
3886 <op> instruction. We don't handle constants larger than
3887 16 bits, because we have no way to load the upper 16 bits
3888 (actually, we could handle them for the subset of cases
3889 in which we are not using $at). */
3890 assert (offset_expr
.X_op
== O_symbol
);
3891 expr1
.X_add_number
= offset_expr
.X_add_number
;
3892 offset_expr
.X_add_number
= 0;
3893 if (expr1
.X_add_number
< -0x8000
3894 || expr1
.X_add_number
>= 0x8000)
3895 as_bad ("PIC code offset overflow (max 16 signed bits)");
3896 if (reg_needs_delay (GP
))
3901 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
3902 tempreg
, (int) BFD_RELOC_MIPS_GOT_HI16
);
3903 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3904 mips_isa
< 3 ? "addu" : "daddu",
3905 "d,v,t", tempreg
, tempreg
, GP
);
3906 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3907 mips_isa
< 3 ? "lw" : "ld",
3908 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT_LO16
,
3910 p
= frag_var (rs_machine_dependent
, 12 + gpdel
, 0,
3911 RELAX_ENCODE (12, 12 + gpdel
, gpdel
, 8 + gpdel
, 0, 0),
3912 offset_expr
.X_add_symbol
, (long) 0, (char *) NULL
);
3915 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
3918 macro_build (p
, &icnt
, &offset_expr
,
3919 mips_isa
< 3 ? "lw" : "ld",
3920 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
3922 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
3924 macro_build (p
, &icnt
, &offset_expr
,
3925 mips_isa
< 3 ? "addiu" : "daddiu",
3926 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
3928 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3929 mips_isa
< 3 ? "addu" : "daddu",
3930 "d,v,t", tempreg
, tempreg
, breg
);
3931 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
, treg
,
3932 (int) BFD_RELOC_LO16
, tempreg
);
3934 else if (mips_pic
== EMBEDDED_PIC
)
3936 /* If there is no base register, we want
3937 <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL)
3938 If there is a base register, we want
3939 addu $tempreg,$breg,$gp
3940 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GPREL)
3942 assert (offset_expr
.X_op
== O_symbol
);
3945 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
3946 treg
, (int) BFD_RELOC_MIPS_GPREL
, GP
);
3951 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3952 mips_isa
< 3 ? "addu" : "daddu",
3953 "d,v,t", tempreg
, breg
, GP
);
3954 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
3955 treg
, (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
3968 load_register (&icnt
, treg
, &imm_expr
, 0);
3972 load_register (&icnt
, treg
, &imm_expr
, 1);
3976 if (imm_expr
.X_op
== O_constant
)
3978 load_register (&icnt
, AT
, &imm_expr
, 0);
3979 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3980 "mtc1", "t,G", AT
, treg
);
3985 assert (offset_expr
.X_op
== O_symbol
3986 && strcmp (segment_name (S_GET_SEGMENT
3987 (offset_expr
.X_add_symbol
)),
3989 && offset_expr
.X_add_number
== 0);
3990 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lwc1", "T,o(b)",
3991 treg
, (int) BFD_RELOC_MIPS_LITERAL
, GP
);
3996 /* We know that sym is in the .rdata section. First we get the
3997 upper 16 bits of the address. */
3998 if (mips_pic
== NO_PIC
)
4000 /* FIXME: This won't work for a 64 bit address. */
4001 macro_build_lui ((char *) NULL
, &icnt
, &offset_expr
, AT
);
4003 else if (mips_pic
== SVR4_PIC
)
4005 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4006 mips_isa
< 3 ? "lw" : "ld",
4007 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
4009 else if (mips_pic
== EMBEDDED_PIC
)
4011 /* For embedded PIC we pick up the entire address off $gp in
4012 a single instruction. */
4013 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4014 mips_isa
< 3 ? "addiu" : "daddiu",
4015 "t,r,j", AT
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
4016 offset_expr
.X_op
= O_constant
;
4017 offset_expr
.X_add_number
= 0;
4022 /* Now we load the register(s). */
4024 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "ld", "t,o(b)",
4025 treg
, (int) BFD_RELOC_LO16
, AT
);
4028 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lw", "t,o(b)",
4029 treg
, (int) BFD_RELOC_LO16
, AT
);
4032 /* FIXME: How in the world do we deal with the possible
4034 offset_expr
.X_add_number
+= 4;
4035 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lw", "t,o(b)",
4036 treg
+ 1, (int) BFD_RELOC_LO16
, AT
);
4040 /* To avoid confusion in tc_gen_reloc, we must ensure that this
4041 does not become a variant frag. */
4042 frag_wane (frag_now
);
4048 assert (offset_expr
.X_op
== O_symbol
4049 && offset_expr
.X_add_number
== 0);
4050 s
= segment_name (S_GET_SEGMENT (offset_expr
.X_add_symbol
));
4051 if (strcmp (s
, ".lit8") == 0)
4055 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "ldc1",
4056 "T,o(b)", treg
, (int) BFD_RELOC_MIPS_LITERAL
, GP
);
4060 r
= BFD_RELOC_MIPS_LITERAL
;
4065 assert (strcmp (s
, RDATA_SECTION_NAME
) == 0);
4066 if (mips_pic
== SVR4_PIC
)
4067 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4068 mips_isa
< 3 ? "lw" : "ld",
4069 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
4072 /* FIXME: This won't work for a 64 bit address. */
4073 macro_build_lui ((char *) NULL
, &icnt
, &offset_expr
, AT
);
4078 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "ldc1",
4079 "T,o(b)", treg
, (int) BFD_RELOC_LO16
, AT
);
4081 /* To avoid confusion in tc_gen_reloc, we must ensure
4082 that this does not become a variant frag. */
4083 frag_wane (frag_now
);
4094 /* Even on a big endian machine $fn comes before $fn+1. We have
4095 to adjust when loading from memory. */
4098 assert (mips_isa
< 2);
4099 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lwc1", "T,o(b)",
4100 byte_order
== LITTLE_ENDIAN
? treg
: treg
+ 1,
4102 /* FIXME: A possible overflow which I don't know how to deal
4104 offset_expr
.X_add_number
+= 4;
4105 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lwc1", "T,o(b)",
4106 byte_order
== LITTLE_ENDIAN
? treg
+ 1 : treg
,
4109 /* To avoid confusion in tc_gen_reloc, we must ensure that this
4110 does not become a variant frag. */
4111 frag_wane (frag_now
);
4120 * The MIPS assembler seems to check for X_add_number not
4121 * being double aligned and generating:
4124 * addiu at,at,%lo(foo+1)
4127 * But, the resulting address is the same after relocation so why
4128 * generate the extra instruction?
4175 if (offset_expr
.X_op
!= O_symbol
4176 && offset_expr
.X_op
!= O_constant
)
4178 as_bad ("expression too complex");
4179 offset_expr
.X_op
= O_constant
;
4182 /* Even on a big endian machine $fn comes before $fn+1. We have
4183 to adjust when loading from memory. We set coproc if we must
4184 load $fn+1 first. */
4185 if (byte_order
== LITTLE_ENDIAN
)
4188 if (mips_pic
== NO_PIC
4189 || offset_expr
.X_op
== O_constant
)
4191 /* If this is a reference to a GP relative symbol, we want
4192 <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL)
4193 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_MIPS_GPREL)
4194 If we have a base register, we use this
4196 <op> $treg,<sym>($at) (BFD_RELOC_MIPS_GPREL)
4197 <op> $treg+1,<sym>+4($at) (BFD_RELOC_MIPS_GPREL)
4198 If this is not a GP relative symbol, we want
4199 lui $at,<sym> (BFD_RELOC_HI16_S)
4200 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
4201 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
4202 If there is a base register, we add it to $at after the
4203 lui instruction. If there is a constant, we always use
4205 if ((valueT
) offset_expr
.X_add_number
>= MAX_GPREL_OFFSET
4206 || nopic_need_relax (offset_expr
.X_add_symbol
))
4225 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4226 mips_isa
< 3 ? "addu" : "daddu",
4227 "d,v,t", AT
, breg
, GP
);
4233 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
4234 coproc
? treg
+ 1 : treg
,
4235 (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
4236 offset_expr
.X_add_number
+= 4;
4238 /* Set mips_optimize to 2 to avoid inserting an
4240 hold_mips_optimize
= mips_optimize
;
4242 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
4243 coproc
? treg
: treg
+ 1,
4244 (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
4245 mips_optimize
= hold_mips_optimize
;
4247 p
= frag_var (rs_machine_dependent
, 12 + off
, 0,
4248 RELAX_ENCODE (8 + off
, 12 + off
, 0, 4 + off
, 1,
4249 used_at
&& mips_noat
),
4250 offset_expr
.X_add_symbol
, (long) 0,
4253 /* We just generated two relocs. When tc_gen_reloc
4254 handles this case, it will skip the first reloc and
4255 handle the second. The second reloc already has an
4256 extra addend of 4, which we added above. We must
4257 subtract it out, and then subtract another 4 to make
4258 the first reloc come out right. The second reloc
4259 will come out right because we are going to add 4 to
4260 offset_expr when we build its instruction below. */
4261 offset_expr
.X_add_number
-= 8;
4262 offset_expr
.X_op
= O_constant
;
4264 macro_build_lui (p
, &icnt
, &offset_expr
, AT
);
4269 macro_build (p
, &icnt
, (expressionS
*) NULL
,
4270 mips_isa
< 3 ? "addu" : "daddu",
4271 "d,v,t", AT
, breg
, AT
);
4275 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
,
4276 coproc
? treg
+ 1 : treg
,
4277 (int) BFD_RELOC_LO16
, AT
);
4280 /* FIXME: How do we handle overflow here? */
4281 offset_expr
.X_add_number
+= 4;
4282 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
,
4283 coproc
? treg
: treg
+ 1,
4284 (int) BFD_RELOC_LO16
, AT
);
4286 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
4290 /* If this is a reference to an external symbol, we want
4291 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4296 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4298 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
4299 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
4300 If there is a base register we add it to $at before the
4301 lwc1 instructions. If there is a constant we include it
4302 in the lwc1 instructions. */
4304 expr1
.X_add_number
= offset_expr
.X_add_number
;
4305 offset_expr
.X_add_number
= 0;
4306 if (expr1
.X_add_number
< -0x8000
4307 || expr1
.X_add_number
>= 0x8000 - 4)
4308 as_bad ("PIC code offset overflow (max 16 signed bits)");
4313 frag_grow (24 + off
);
4314 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4315 mips_isa
< 3 ? "lw" : "ld",
4316 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
4317 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
4319 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4320 mips_isa
< 3 ? "addu" : "daddu",
4321 "d,v,t", AT
, breg
, AT
);
4322 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
4323 coproc
? treg
+ 1 : treg
,
4324 (int) BFD_RELOC_LO16
, AT
);
4325 expr1
.X_add_number
+= 4;
4327 /* Set mips_optimize to 2 to avoid inserting an undesired
4329 hold_mips_optimize
= mips_optimize
;
4331 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
4332 coproc
? treg
: treg
+ 1,
4333 (int) BFD_RELOC_LO16
, AT
);
4334 mips_optimize
= hold_mips_optimize
;
4336 (void) frag_var (rs_machine_dependent
, 0, 0,
4337 RELAX_ENCODE (0, 0, -16 - off
, -8, 1, 0),
4338 offset_expr
.X_add_symbol
, (long) 0,
4341 else if (mips_pic
== SVR4_PIC
)
4345 /* If this is a reference to an external symbol, we want
4346 lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16)
4348 lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16)
4353 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4355 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
4356 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
4357 If there is a base register we add it to $at before the
4358 lwc1 instructions. If there is a constant we include it
4359 in the lwc1 instructions. */
4361 expr1
.X_add_number
= offset_expr
.X_add_number
;
4362 offset_expr
.X_add_number
= 0;
4363 if (expr1
.X_add_number
< -0x8000
4364 || expr1
.X_add_number
>= 0x8000 - 4)
4365 as_bad ("PIC code offset overflow (max 16 signed bits)");
4366 if (reg_needs_delay (GP
))
4375 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
4376 AT
, (int) BFD_RELOC_MIPS_GOT_HI16
);
4377 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4378 mips_isa
< 3 ? "addu" : "daddu",
4379 "d,v,t", AT
, AT
, GP
);
4380 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4381 mips_isa
< 3 ? "lw" : "ld",
4382 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT_LO16
, AT
);
4383 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
4385 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4386 mips_isa
< 3 ? "addu" : "daddu",
4387 "d,v,t", AT
, breg
, AT
);
4388 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
4389 coproc
? treg
+ 1 : treg
,
4390 (int) BFD_RELOC_LO16
, AT
);
4391 expr1
.X_add_number
+= 4;
4393 /* Set mips_optimize to 2 to avoid inserting an undesired
4395 hold_mips_optimize
= mips_optimize
;
4397 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
4398 coproc
? treg
: treg
+ 1,
4399 (int) BFD_RELOC_LO16
, AT
);
4400 mips_optimize
= hold_mips_optimize
;
4401 expr1
.X_add_number
-= 4;
4403 p
= frag_var (rs_machine_dependent
, 16 + gpdel
+ off
, 0,
4404 RELAX_ENCODE (24 + off
, 16 + gpdel
+ off
, gpdel
,
4405 8 + gpdel
+ off
, 1, 0),
4406 offset_expr
.X_add_symbol
, (long) 0,
4410 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4413 macro_build (p
, &icnt
, &offset_expr
,
4414 mips_isa
< 3 ? "lw" : "ld",
4415 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
4417 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4421 macro_build (p
, &icnt
, (expressionS
*) NULL
,
4422 mips_isa
< 3 ? "addu" : "daddu",
4423 "d,v,t", AT
, breg
, AT
);
4426 macro_build (p
, &icnt
, &expr1
, s
, fmt
,
4427 coproc
? treg
+ 1 : treg
,
4428 (int) BFD_RELOC_LO16
, AT
);
4430 expr1
.X_add_number
+= 4;
4432 /* Set mips_optimize to 2 to avoid inserting an undesired
4434 hold_mips_optimize
= mips_optimize
;
4436 macro_build (p
, &icnt
, &expr1
, s
, fmt
,
4437 coproc
? treg
: treg
+ 1,
4438 (int) BFD_RELOC_LO16
, AT
);
4439 mips_optimize
= hold_mips_optimize
;
4441 else if (mips_pic
== EMBEDDED_PIC
)
4443 /* If there is no base register, we use
4444 <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL)
4445 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_MIPS_GPREL)
4446 If we have a base register, we use
4448 <op> $treg,<sym>($at) (BFD_RELOC_MIPS_GPREL)
4449 <op> $treg+1,<sym>+4($at) (BFD_RELOC_MIPS_GPREL)
4458 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4459 mips_isa
< 3 ? "addu" : "daddu",
4460 "d,v,t", AT
, breg
, GP
);
4465 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
4466 coproc
? treg
+ 1 : treg
,
4467 (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
4468 offset_expr
.X_add_number
+= 4;
4469 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
4470 coproc
? treg
: treg
+ 1,
4471 (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
4487 assert (mips_isa
< 3);
4488 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
4489 (int) BFD_RELOC_LO16
, breg
);
4490 offset_expr
.X_add_number
+= 4;
4491 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
+ 1,
4492 (int) BFD_RELOC_LO16
, breg
);
4494 #ifdef LOSING_COMPILER
4500 as_warn ("Macro used $at after \".set noat\"");
4505 struct mips_cl_insn
*ip
;
4507 register int treg
, sreg
, dreg
, breg
;
4522 bfd_reloc_code_real_type r
;
4525 treg
= (ip
->insn_opcode
>> 16) & 0x1f;
4526 dreg
= (ip
->insn_opcode
>> 11) & 0x1f;
4527 sreg
= breg
= (ip
->insn_opcode
>> 21) & 0x1f;
4528 mask
= ip
->insn_mo
->mask
;
4530 expr1
.X_op
= O_constant
;
4531 expr1
.X_op_symbol
= NULL
;
4532 expr1
.X_add_symbol
= NULL
;
4533 expr1
.X_add_number
= 1;
4537 #endif /* LOSING_COMPILER */
4542 macro_build ((char *) NULL
, &icnt
, NULL
,
4543 dbl
? "dmultu" : "multu",
4545 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
4551 /* The MIPS assembler some times generates shifts and adds. I'm
4552 not trying to be that fancy. GCC should do this for us
4554 load_register (&icnt
, AT
, &imm_expr
, dbl
);
4555 macro_build ((char *) NULL
, &icnt
, NULL
,
4556 dbl
? "dmult" : "mult",
4558 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
4564 mips_emit_delays ();
4566 mips_any_noreorder
= 1;
4567 macro_build ((char *) NULL
, &icnt
, NULL
,
4568 dbl
? "dmult" : "mult",
4570 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
4571 macro_build ((char *) NULL
, &icnt
, NULL
,
4572 dbl
? "dsra32" : "sra",
4573 "d,w,<", dreg
, dreg
, 31);
4574 macro_build ((char *) NULL
, &icnt
, NULL
, "mfhi", "d", AT
);
4576 macro_build ((char *) NULL
, &icnt
, NULL
, "tne", "s,t", dreg
, AT
);
4579 expr1
.X_add_number
= 8;
4580 macro_build ((char *) NULL
, &icnt
, &expr1
, "beq", "s,t,p", dreg
, AT
);
4581 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
4582 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 6);
4585 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
4591 mips_emit_delays ();
4593 mips_any_noreorder
= 1;
4594 macro_build ((char *) NULL
, &icnt
, NULL
,
4595 dbl
? "dmultu" : "multu",
4597 macro_build ((char *) NULL
, &icnt
, NULL
, "mfhi", "d", AT
);
4598 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
4600 macro_build ((char *) NULL
, &icnt
, NULL
, "tne", "s,t", AT
, 0);
4603 expr1
.X_add_number
= 8;
4604 macro_build ((char *) NULL
, &icnt
, &expr1
, "beq", "s,t,p", AT
, 0);
4605 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
4606 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 6);
4612 macro_build ((char *) NULL
, &icnt
, NULL
, "subu", "d,v,t", AT
, 0, treg
);
4613 macro_build ((char *) NULL
, &icnt
, NULL
, "srlv", "d,t,s", AT
, sreg
, AT
);
4614 macro_build ((char *) NULL
, &icnt
, NULL
, "sllv", "d,t,s", dreg
, sreg
,
4616 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
4620 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", AT
, sreg
,
4621 (int) (imm_expr
.X_add_number
& 0x1f));
4622 macro_build ((char *) NULL
, &icnt
, NULL
, "srl", "d,w,<", dreg
, sreg
,
4623 (int) ((0 - imm_expr
.X_add_number
) & 0x1f));
4624 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
4628 macro_build ((char *) NULL
, &icnt
, NULL
, "subu", "d,v,t", AT
, 0, treg
);
4629 macro_build ((char *) NULL
, &icnt
, NULL
, "sllv", "d,t,s", AT
, sreg
, AT
);
4630 macro_build ((char *) NULL
, &icnt
, NULL
, "srlv", "d,t,s", dreg
, sreg
,
4632 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
4636 macro_build ((char *) NULL
, &icnt
, NULL
, "srl", "d,w,<", AT
, sreg
,
4637 (int) (imm_expr
.X_add_number
& 0x1f));
4638 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", dreg
, sreg
,
4639 (int) ((0 - imm_expr
.X_add_number
) & 0x1f));
4640 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
4644 assert (mips_isa
< 2);
4645 /* Even on a big endian machine $fn comes before $fn+1. We have
4646 to adjust when storing to memory. */
4647 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "swc1", "T,o(b)",
4648 byte_order
== LITTLE_ENDIAN
? treg
: treg
+ 1,
4649 (int) BFD_RELOC_LO16
, breg
);
4650 offset_expr
.X_add_number
+= 4;
4651 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "swc1", "T,o(b)",
4652 byte_order
== LITTLE_ENDIAN
? treg
+ 1 : treg
,
4653 (int) BFD_RELOC_LO16
, breg
);
4658 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
4659 treg
, (int) BFD_RELOC_LO16
);
4661 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
4662 sreg
, (int) BFD_RELOC_LO16
);
4665 macro_build ((char *) NULL
, &icnt
, NULL
, "xor", "d,v,t", dreg
,
4667 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
4668 dreg
, (int) BFD_RELOC_LO16
);
4673 if (imm_expr
.X_add_number
== 0)
4675 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
4676 sreg
, (int) BFD_RELOC_LO16
);
4681 as_warn ("Instruction %s: result is always false",
4683 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
, 0);
4686 if (imm_expr
.X_add_number
>= 0 && imm_expr
.X_add_number
< 0x10000)
4688 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "xori", "t,r,i", dreg
,
4689 sreg
, (int) BFD_RELOC_LO16
);
4692 else if (imm_expr
.X_add_number
> -0x8000 && imm_expr
.X_add_number
< 0)
4694 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
4695 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
4696 mips_isa
< 3 ? "addiu" : "daddiu",
4697 "t,r,j", dreg
, sreg
,
4698 (int) BFD_RELOC_LO16
);
4703 load_register (&icnt
, AT
, &imm_expr
, 0);
4704 macro_build ((char *) NULL
, &icnt
, NULL
, "xor", "d,v,t", dreg
,
4708 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
, dreg
,
4709 (int) BFD_RELOC_LO16
);
4714 case M_SGE
: /* sreg >= treg <==> not (sreg < treg) */
4720 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, sreg
, treg
);
4721 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
4722 (int) BFD_RELOC_LO16
);
4725 case M_SGE_I
: /* sreg >= I <==> not (sreg < I) */
4727 if (imm_expr
.X_add_number
>= -0x8000 && imm_expr
.X_add_number
< 0x8000)
4729 macro_build ((char *) NULL
, &icnt
, &expr1
,
4730 mask
== M_SGE_I
? "slti" : "sltiu",
4731 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
4736 load_register (&icnt
, AT
, &imm_expr
, 0);
4737 macro_build ((char *) NULL
, &icnt
, NULL
,
4738 mask
== M_SGE_I
? "slt" : "sltu",
4739 "d,v,t", dreg
, sreg
, AT
);
4742 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
4743 (int) BFD_RELOC_LO16
);
4748 case M_SGT
: /* sreg > treg <==> treg < sreg */
4754 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, treg
, sreg
);
4757 case M_SGT_I
: /* sreg > I <==> I < sreg */
4763 load_register (&icnt
, AT
, &imm_expr
, 0);
4764 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, AT
, sreg
);
4767 case M_SLE
: /* sreg <= treg <==> treg >= sreg <==> not (treg < sreg) */
4773 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, treg
, sreg
);
4774 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
4775 (int) BFD_RELOC_LO16
);
4778 case M_SLE_I
: /* sreg <= I <==> I >= sreg <==> not (I < sreg) */
4784 load_register (&icnt
, AT
, &imm_expr
, 0);
4785 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, AT
, sreg
);
4786 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
4787 (int) BFD_RELOC_LO16
);
4791 if (imm_expr
.X_add_number
>= -0x8000 && imm_expr
.X_add_number
< 0x8000)
4793 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "slti", "t,r,j",
4794 dreg
, sreg
, (int) BFD_RELOC_LO16
);
4797 load_register (&icnt
, AT
, &imm_expr
, 0);
4798 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", dreg
, sreg
, AT
);
4802 if (imm_expr
.X_add_number
>= -0x8000 && imm_expr
.X_add_number
< 0x8000)
4804 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "sltiu", "t,r,j",
4805 dreg
, sreg
, (int) BFD_RELOC_LO16
);
4808 load_register (&icnt
, AT
, &imm_expr
, 0);
4809 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, sreg
,
4815 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0,
4818 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0,
4822 macro_build ((char *) NULL
, &icnt
, NULL
, "xor", "d,v,t", dreg
,
4824 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0,
4830 if (imm_expr
.X_add_number
== 0)
4832 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0,
4838 as_warn ("Instruction %s: result is always true",
4840 macro_build ((char *) NULL
, &icnt
, &expr1
,
4841 mips_isa
< 3 ? "addiu" : "daddiu",
4842 "t,r,j", dreg
, 0, (int) BFD_RELOC_LO16
);
4845 if (imm_expr
.X_add_number
>= 0 && imm_expr
.X_add_number
< 0x10000)
4847 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "xori", "t,r,i",
4848 dreg
, sreg
, (int) BFD_RELOC_LO16
);
4851 else if (imm_expr
.X_add_number
> -0x8000 && imm_expr
.X_add_number
< 0)
4853 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
4854 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
4855 mips_isa
< 3 ? "addiu" : "daddiu",
4856 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
4861 load_register (&icnt
, AT
, &imm_expr
, 0);
4862 macro_build ((char *) NULL
, &icnt
, NULL
, "xor", "d,v,t", dreg
,
4866 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0, dreg
);
4874 if (imm_expr
.X_add_number
> -0x8000 && imm_expr
.X_add_number
<= 0x8000)
4876 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
4877 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
4878 dbl
? "daddi" : "addi",
4879 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
4882 load_register (&icnt
, AT
, &imm_expr
, dbl
);
4883 macro_build ((char *) NULL
, &icnt
, NULL
,
4884 dbl
? "dsub" : "sub",
4885 "d,v,t", dreg
, sreg
, AT
);
4891 if (imm_expr
.X_add_number
> -0x8000 && imm_expr
.X_add_number
<= 0x8000)
4893 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
4894 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
4895 dbl
? "daddiu" : "addiu",
4896 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
4899 load_register (&icnt
, AT
, &imm_expr
, dbl
);
4900 macro_build ((char *) NULL
, &icnt
, NULL
,
4901 dbl
? "dsubu" : "subu",
4902 "d,v,t", dreg
, sreg
, AT
);
4923 load_register (&icnt
, AT
, &imm_expr
, 0);
4924 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "s,t", sreg
, AT
);
4929 assert (mips_isa
< 2);
4930 sreg
= (ip
->insn_opcode
>> 11) & 0x1f; /* floating reg */
4931 dreg
= (ip
->insn_opcode
>> 06) & 0x1f; /* floating reg */
4934 * Is the double cfc1 instruction a bug in the mips assembler;
4935 * or is there a reason for it?
4937 mips_emit_delays ();
4939 mips_any_noreorder
= 1;
4940 macro_build ((char *) NULL
, &icnt
, NULL
, "cfc1", "t,G", treg
, 31);
4941 macro_build ((char *) NULL
, &icnt
, NULL
, "cfc1", "t,G", treg
, 31);
4942 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "");
4943 expr1
.X_add_number
= 3;
4944 macro_build ((char *) NULL
, &icnt
, &expr1
, "ori", "t,r,i", AT
, treg
,
4945 (int) BFD_RELOC_LO16
);
4946 expr1
.X_add_number
= 2;
4947 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", AT
, AT
,
4948 (int) BFD_RELOC_LO16
);
4949 macro_build ((char *) NULL
, &icnt
, NULL
, "ctc1", "t,G", AT
, 31);
4950 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "");
4951 macro_build ((char *) NULL
, &icnt
, NULL
,
4952 mask
== M_TRUNCWD
? "cvt.w.d" : "cvt.w.s", "D,S", dreg
, sreg
);
4953 macro_build ((char *) NULL
, &icnt
, NULL
, "ctc1", "t,G", treg
, 31);
4954 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "");
4964 if (offset_expr
.X_add_number
>= 0x7fff)
4965 as_bad ("operand overflow");
4966 /* avoid load delay */
4967 if (byte_order
== LITTLE_ENDIAN
)
4968 offset_expr
.X_add_number
+= 1;
4969 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
4970 (int) BFD_RELOC_LO16
, breg
);
4971 if (byte_order
== LITTLE_ENDIAN
)
4972 offset_expr
.X_add_number
-= 1;
4974 offset_expr
.X_add_number
+= 1;
4975 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lbu", "t,o(b)", AT
,
4976 (int) BFD_RELOC_LO16
, breg
);
4977 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", treg
, treg
, 8);
4978 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", treg
, treg
, AT
);
4991 if (offset_expr
.X_add_number
>= 0x8000 - off
)
4992 as_bad ("operand overflow");
4993 if (byte_order
== LITTLE_ENDIAN
)
4994 offset_expr
.X_add_number
+= off
;
4995 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
4996 (int) BFD_RELOC_LO16
, breg
);
4997 if (byte_order
== LITTLE_ENDIAN
)
4998 offset_expr
.X_add_number
-= off
;
5000 offset_expr
.X_add_number
+= off
;
5001 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s2
, "t,o(b)", treg
,
5002 (int) BFD_RELOC_LO16
, breg
);
5015 load_address (&icnt
, AT
, &offset_expr
);
5017 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5018 mips_isa
< 3 ? "addu" : "daddu",
5019 "d,v,t", AT
, AT
, breg
);
5020 if (byte_order
== LITTLE_ENDIAN
)
5021 expr1
.X_add_number
= off
;
5023 expr1
.X_add_number
= 0;
5024 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, "t,o(b)", treg
,
5025 (int) BFD_RELOC_LO16
, AT
);
5026 if (byte_order
== LITTLE_ENDIAN
)
5027 expr1
.X_add_number
= 0;
5029 expr1
.X_add_number
= off
;
5030 macro_build ((char *) NULL
, &icnt
, &expr1
, s2
, "t,o(b)", treg
,
5031 (int) BFD_RELOC_LO16
, AT
);
5036 load_address (&icnt
, AT
, &offset_expr
);
5038 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5039 mips_isa
< 3 ? "addu" : "daddu",
5040 "d,v,t", AT
, AT
, breg
);
5041 if (byte_order
== BIG_ENDIAN
)
5042 expr1
.X_add_number
= 0;
5043 macro_build ((char *) NULL
, &icnt
, &expr1
,
5044 mask
== M_ULH_A
? "lb" : "lbu", "t,o(b)", treg
,
5045 (int) BFD_RELOC_LO16
, AT
);
5046 if (byte_order
== BIG_ENDIAN
)
5047 expr1
.X_add_number
= 1;
5049 expr1
.X_add_number
= 0;
5050 macro_build ((char *) NULL
, &icnt
, &expr1
, "lbu", "t,o(b)", AT
,
5051 (int) BFD_RELOC_LO16
, AT
);
5052 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", treg
,
5054 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", treg
,
5059 if (offset_expr
.X_add_number
>= 0x7fff)
5060 as_bad ("operand overflow");
5061 if (byte_order
== BIG_ENDIAN
)
5062 offset_expr
.X_add_number
+= 1;
5063 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "sb", "t,o(b)", treg
,
5064 (int) BFD_RELOC_LO16
, breg
);
5065 macro_build ((char *) NULL
, &icnt
, NULL
, "srl", "d,w,<", AT
, treg
, 8);
5066 if (byte_order
== BIG_ENDIAN
)
5067 offset_expr
.X_add_number
-= 1;
5069 offset_expr
.X_add_number
+= 1;
5070 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "sb", "t,o(b)", AT
,
5071 (int) BFD_RELOC_LO16
, breg
);
5084 if (offset_expr
.X_add_number
>= 0x8000 - off
)
5085 as_bad ("operand overflow");
5086 if (byte_order
== LITTLE_ENDIAN
)
5087 offset_expr
.X_add_number
+= off
;
5088 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
5089 (int) BFD_RELOC_LO16
, breg
);
5090 if (byte_order
== LITTLE_ENDIAN
)
5091 offset_expr
.X_add_number
-= off
;
5093 offset_expr
.X_add_number
+= off
;
5094 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s2
, "t,o(b)", treg
,
5095 (int) BFD_RELOC_LO16
, breg
);
5108 load_address (&icnt
, AT
, &offset_expr
);
5110 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5111 mips_isa
< 3 ? "addu" : "daddu",
5112 "d,v,t", AT
, AT
, breg
);
5113 if (byte_order
== LITTLE_ENDIAN
)
5114 expr1
.X_add_number
= off
;
5116 expr1
.X_add_number
= 0;
5117 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, "t,o(b)", treg
,
5118 (int) BFD_RELOC_LO16
, AT
);
5119 if (byte_order
== LITTLE_ENDIAN
)
5120 expr1
.X_add_number
= 0;
5122 expr1
.X_add_number
= off
;
5123 macro_build ((char *) NULL
, &icnt
, &expr1
, s2
, "t,o(b)", treg
,
5124 (int) BFD_RELOC_LO16
, AT
);
5128 load_address (&icnt
, AT
, &offset_expr
);
5130 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5131 mips_isa
< 3 ? "addu" : "daddu",
5132 "d,v,t", AT
, AT
, breg
);
5133 if (byte_order
== LITTLE_ENDIAN
)
5134 expr1
.X_add_number
= 0;
5135 macro_build ((char *) NULL
, &icnt
, &expr1
, "sb", "t,o(b)", treg
,
5136 (int) BFD_RELOC_LO16
, AT
);
5137 macro_build ((char *) NULL
, &icnt
, NULL
, "srl", "d,w,<", treg
,
5139 if (byte_order
== LITTLE_ENDIAN
)
5140 expr1
.X_add_number
= 1;
5142 expr1
.X_add_number
= 0;
5143 macro_build ((char *) NULL
, &icnt
, &expr1
, "sb", "t,o(b)", treg
,
5144 (int) BFD_RELOC_LO16
, AT
);
5145 if (byte_order
== LITTLE_ENDIAN
)
5146 expr1
.X_add_number
= 0;
5148 expr1
.X_add_number
= 1;
5149 macro_build ((char *) NULL
, &icnt
, &expr1
, "lbu", "t,o(b)", AT
,
5150 (int) BFD_RELOC_LO16
, AT
);
5151 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", treg
,
5153 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", treg
,
5158 as_bad ("Macro %s not implemented yet", ip
->insn_mo
->name
);
5162 as_warn ("Macro used $at after \".set noat\"");
5165 /* This routine assembles an instruction into its binary format. As a
5166 side effect, it sets one of the global variables imm_reloc or
5167 offset_reloc to the type of relocation to do if one of the operands
5168 is an address expression. */
5173 struct mips_cl_insn
*ip
;
5178 struct mips_opcode
*insn
;
5181 unsigned int lastregno
= 0;
5186 for (s
= str
; islower (*s
) || (*s
>= '0' && *s
<= '3') || *s
== '6' || *s
== '.'; ++s
)
5198 as_fatal ("Unknown opcode: `%s'", str
);
5200 if ((insn
= (struct mips_opcode
*) hash_find (op_hash
, str
)) == NULL
)
5202 insn_error
= "unrecognized opcode";
5210 assert (strcmp (insn
->name
, str
) == 0);
5212 if (insn
->pinfo
== INSN_MACRO
)
5213 insn_isa
= insn
->match
;
5214 else if ((insn
->pinfo
& INSN_ISA
) == INSN_ISA2
)
5216 else if ((insn
->pinfo
& INSN_ISA
) == INSN_ISA3
)
5218 else if ((insn
->pinfo
& INSN_ISA
) == INSN_ISA4
)
5223 if (insn_isa
> mips_isa
5224 || ((insn
->pinfo
& INSN_ISA
) == INSN_4650
5226 || ((insn
->pinfo
& INSN_ISA
) == INSN_4010
5228 || ((insn
->pinfo
& INSN_ISA
) == INSN_4100
5231 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
]
5232 && strcmp (insn
->name
, insn
[1].name
) == 0)
5237 if (insn_isa
<= mips_isa
)
5238 insn_error
= "opcode not supported on this processor";
5241 static char buf
[100];
5243 sprintf (buf
, "opcode requires -mips%d or greater", insn_isa
);
5250 ip
->insn_opcode
= insn
->match
;
5251 for (args
= insn
->args
;; ++args
)
5257 case '\0': /* end of args */
5270 ip
->insn_opcode
|= lastregno
<< 21;
5275 ip
->insn_opcode
|= lastregno
<< 16;
5279 ip
->insn_opcode
|= lastregno
<< 11;
5285 /* handle optional base register.
5286 Either the base register is omitted or
5287 we must have a left paren. */
5288 /* this is dependent on the next operand specifier
5289 is a 'b' for base register */
5290 assert (args
[1] == 'b');
5294 case ')': /* these must match exactly */
5299 case '<': /* must be at least one digit */
5301 * According to the manual, if the shift amount is greater
5302 * than 31 or less than 0 the the shift amount should be
5303 * mod 32. In reality the mips assembler issues an error.
5304 * We issue a warning and mask out all but the low 5 bits.
5306 my_getExpression (&imm_expr
, s
);
5307 check_absolute_expr (ip
, &imm_expr
);
5308 if ((unsigned long) imm_expr
.X_add_number
> 31)
5310 as_warn ("Improper shift amount (%ld)",
5311 (long) imm_expr
.X_add_number
);
5312 imm_expr
.X_add_number
= imm_expr
.X_add_number
& 0x1f;
5314 ip
->insn_opcode
|= imm_expr
.X_add_number
<< 6;
5315 imm_expr
.X_op
= O_absent
;
5319 case '>': /* shift amount minus 32 */
5320 my_getExpression (&imm_expr
, s
);
5321 check_absolute_expr (ip
, &imm_expr
);
5322 if ((unsigned long) imm_expr
.X_add_number
< 32
5323 || (unsigned long) imm_expr
.X_add_number
> 63)
5325 ip
->insn_opcode
|= (imm_expr
.X_add_number
- 32) << 6;
5326 imm_expr
.X_op
= O_absent
;
5330 case 'k': /* cache code */
5331 case 'h': /* prefx code */
5332 my_getExpression (&imm_expr
, s
);
5333 check_absolute_expr (ip
, &imm_expr
);
5334 if ((unsigned long) imm_expr
.X_add_number
> 31)
5336 as_warn ("Invalid value for `%s' (%lu)",
5338 (unsigned long) imm_expr
.X_add_number
);
5339 imm_expr
.X_add_number
&= 0x1f;
5342 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_CACHE
;
5344 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_PREFX
;
5345 imm_expr
.X_op
= O_absent
;
5349 case 'c': /* break code */
5350 my_getExpression (&imm_expr
, s
);
5351 check_absolute_expr (ip
, &imm_expr
);
5352 if ((unsigned) imm_expr
.X_add_number
> 1023)
5353 as_warn ("Illegal break code (%ld)",
5354 (long) imm_expr
.X_add_number
);
5355 ip
->insn_opcode
|= imm_expr
.X_add_number
<< 16;
5356 imm_expr
.X_op
= O_absent
;
5360 case 'B': /* syscall code */
5361 my_getExpression (&imm_expr
, s
);
5362 check_absolute_expr (ip
, &imm_expr
);
5363 if ((unsigned) imm_expr
.X_add_number
> 0xfffff)
5364 as_warn ("Illegal syscall code (%ld)",
5365 (long) imm_expr
.X_add_number
);
5366 ip
->insn_opcode
|= imm_expr
.X_add_number
<< 6;
5367 imm_expr
.X_op
= O_absent
;
5371 case 'C': /* Coprocessor code */
5372 my_getExpression (&imm_expr
, s
);
5373 check_absolute_expr (ip
, &imm_expr
);
5374 if ((unsigned long) imm_expr
.X_add_number
>= (1<<25))
5376 as_warn ("Coproccesor code > 25 bits (%ld)",
5377 (long) imm_expr
.X_add_number
);
5378 imm_expr
.X_add_number
&= ((1<<25) - 1);
5380 ip
->insn_opcode
|= imm_expr
.X_add_number
;
5381 imm_expr
.X_op
= O_absent
;
5385 case 'b': /* base register */
5386 case 'd': /* destination register */
5387 case 's': /* source register */
5388 case 't': /* target register */
5389 case 'r': /* both target and source */
5390 case 'v': /* both dest and source */
5391 case 'w': /* both dest and target */
5392 case 'E': /* coprocessor target register */
5393 case 'G': /* coprocessor destination register */
5394 case 'x': /* ignore register name */
5395 case 'z': /* must be zero register */
5409 while (isdigit (*s
));
5411 as_bad ("Invalid register number (%d)", regno
);
5413 else if (*args
== 'E' || *args
== 'G')
5417 if (s
[1] == 'f' && s
[2] == 'p')
5422 else if (s
[1] == 's' && s
[2] == 'p')
5427 else if (s
[1] == 'g' && s
[2] == 'p')
5432 else if (s
[1] == 'a' && s
[2] == 't')
5437 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '0')
5442 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '1')
5454 as_warn ("Used $at without \".set noat\"");
5460 if (c
== 'r' || c
== 'v' || c
== 'w')
5467 /* 'z' only matches $0. */
5468 if (c
== 'z' && regno
!= 0)
5476 ip
->insn_opcode
|= regno
<< 21;
5480 ip
->insn_opcode
|= regno
<< 11;
5485 ip
->insn_opcode
|= regno
<< 16;
5488 /* This case exists because on the r3000 trunc
5489 expands into a macro which requires a gp
5490 register. On the r6000 or r4000 it is
5491 assembled into a single instruction which
5492 ignores the register. Thus the insn version
5493 is MIPS_ISA2 and uses 'x', and the macro
5494 version is MIPS_ISA1 and uses 't'. */
5497 /* This case is for the div instruction, which
5498 acts differently if the destination argument
5499 is $0. This only matches $0, and is checked
5500 outside the switch. */
5511 ip
->insn_opcode
|= lastregno
<< 21;
5514 ip
->insn_opcode
|= lastregno
<< 16;
5519 case 'D': /* floating point destination register */
5520 case 'S': /* floating point source register */
5521 case 'T': /* floating point target register */
5522 case 'R': /* floating point source register */
5526 if (s
[0] == '$' && s
[1] == 'f' && isdigit (s
[2]))
5536 while (isdigit (*s
));
5539 as_bad ("Invalid float register number (%d)", regno
);
5541 if ((regno
& 1) != 0
5543 && ! (strcmp (str
, "mtc1") == 0
5544 || strcmp (str
, "mfc1") == 0
5545 || strcmp (str
, "lwc1") == 0
5546 || strcmp (str
, "swc1") == 0
5547 || strcmp (str
, "l.s") == 0
5548 || strcmp (str
, "s.s") == 0))
5549 as_warn ("Float register should be even, was %d",
5557 if (c
== 'V' || c
== 'W')
5567 ip
->insn_opcode
|= regno
<< 6;
5571 ip
->insn_opcode
|= regno
<< 11;
5575 ip
->insn_opcode
|= regno
<< 16;
5578 ip
->insn_opcode
|= regno
<< 21;
5587 ip
->insn_opcode
|= lastregno
<< 11;
5590 ip
->insn_opcode
|= lastregno
<< 16;
5596 my_getExpression (&imm_expr
, s
);
5597 if (imm_expr
.X_op
!= O_big
5598 && imm_expr
.X_op
!= O_constant
)
5599 insn_error
= "absolute expression required";
5604 my_getExpression (&offset_expr
, s
);
5605 imm_reloc
= BFD_RELOC_32
;
5617 unsigned char temp
[8];
5619 unsigned int length
;
5624 /* These only appear as the last operand in an
5625 instruction, and every instruction that accepts
5626 them in any variant accepts them in all variants.
5627 This means we don't have to worry about backing out
5628 any changes if the instruction does not match.
5630 The difference between them is the size of the
5631 floating point constant and where it goes. For 'F'
5632 and 'L' the constant is 64 bits; for 'f' and 'l' it
5633 is 32 bits. Where the constant is placed is based
5634 on how the MIPS assembler does things:
5637 f -- immediate value
5640 The .lit4 and .lit8 sections are only used if
5641 permitted by the -G argument.
5643 When generating embedded PIC code, we use the
5644 .lit8 section but not the .lit4 section (we can do
5645 .lit4 inline easily; we need to put .lit8
5646 somewhere in the data segment, and using .lit8
5647 permits the linker to eventually combine identical
5650 f64
= *args
== 'F' || *args
== 'L';
5652 save_in
= input_line_pointer
;
5653 input_line_pointer
= s
;
5654 err
= md_atof (f64
? 'd' : 'f', (char *) temp
, &len
);
5656 s
= input_line_pointer
;
5657 input_line_pointer
= save_in
;
5658 if (err
!= NULL
&& *err
!= '\0')
5660 as_bad ("Bad floating point constant: %s", err
);
5661 memset (temp
, '\0', sizeof temp
);
5662 length
= f64
? 8 : 4;
5665 assert (length
== (f64
? 8 : 4));
5669 && (! USE_GLOBAL_POINTER_OPT
5670 || mips_pic
== EMBEDDED_PIC
5671 || g_switch_value
< 4)
5674 imm_expr
.X_op
= O_constant
;
5675 if (byte_order
== LITTLE_ENDIAN
)
5676 imm_expr
.X_add_number
=
5677 (((((((int) temp
[3] << 8)
5682 imm_expr
.X_add_number
=
5683 (((((((int) temp
[0] << 8)
5690 const char *newname
;
5693 /* Switch to the right section. */
5695 subseg
= now_subseg
;
5698 default: /* unused default case avoids warnings. */
5700 newname
= RDATA_SECTION_NAME
;
5701 if (USE_GLOBAL_POINTER_OPT
&& g_switch_value
>= 8)
5705 newname
= RDATA_SECTION_NAME
;
5708 assert (!USE_GLOBAL_POINTER_OPT
5709 || g_switch_value
>= 4);
5713 new_seg
= subseg_new (newname
, (subsegT
) 0);
5714 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
5715 bfd_set_section_flags (stdoutput
, new_seg
,
5720 frag_align (*args
== 'l' ? 2 : 3, 0);
5721 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
5722 record_alignment (new_seg
, 4);
5724 record_alignment (new_seg
, *args
== 'l' ? 2 : 3);
5726 as_bad ("Can't use floating point insn in this section");
5728 /* Set the argument to the current address in the
5730 offset_expr
.X_op
= O_symbol
;
5731 offset_expr
.X_add_symbol
=
5732 symbol_new ("L0\001", now_seg
,
5733 (valueT
) frag_now_fix (), frag_now
);
5734 offset_expr
.X_add_number
= 0;
5736 /* Put the floating point number into the section. */
5737 p
= frag_more ((int) length
);
5738 memcpy (p
, temp
, length
);
5740 /* Switch back to the original section. */
5741 subseg_set (seg
, subseg
);
5746 case 'i': /* 16 bit unsigned immediate */
5747 case 'j': /* 16 bit signed immediate */
5748 imm_reloc
= BFD_RELOC_LO16
;
5749 c
= my_getSmallExpression (&imm_expr
, s
);
5754 if (imm_expr
.X_op
== O_constant
)
5755 imm_expr
.X_add_number
=
5756 (imm_expr
.X_add_number
>> 16) & 0xffff;
5759 imm_reloc
= BFD_RELOC_HI16_S
;
5760 imm_unmatched_hi
= true;
5763 imm_reloc
= BFD_RELOC_HI16
;
5768 if ((c
== '\0' && imm_expr
.X_op
!= O_constant
)
5769 || ((imm_expr
.X_add_number
< 0
5770 || imm_expr
.X_add_number
>= 0x10000)
5771 && imm_expr
.X_op
== O_constant
))
5773 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
5774 !strcmp (insn
->name
, insn
[1].name
))
5776 if (imm_expr
.X_op
!= O_constant
5777 && imm_expr
.X_op
!= O_big
)
5778 insn_error
= "absolute expression required";
5780 as_bad ("16 bit expression not in range 0..65535");
5788 /* The upper bound should be 0x8000, but
5789 unfortunately the MIPS assembler accepts numbers
5790 from 0x8000 to 0xffff and sign extends them, and
5791 we want to be compatible. We only permit this
5792 extended range for an instruction which does not
5793 provide any further alternates, since those
5794 alternates may handle other cases. People should
5795 use the numbers they mean, rather than relying on
5796 a mysterious sign extension. */
5797 more
= (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
5798 strcmp (insn
->name
, insn
[1].name
) == 0);
5803 if ((c
== '\0' && imm_expr
.X_op
!= O_constant
)
5804 || ((imm_expr
.X_add_number
< -0x8000
5805 || imm_expr
.X_add_number
>= max
)
5806 && imm_expr
.X_op
== O_constant
)
5808 && imm_expr
.X_add_number
< 0
5810 && imm_expr
.X_unsigned
5811 && sizeof (imm_expr
.X_add_number
) <= 4))
5815 if (imm_expr
.X_op
!= O_constant
5816 && imm_expr
.X_op
!= O_big
)
5817 insn_error
= "absolute expression required";
5819 as_bad ("16 bit expression not in range -32768..32767");
5825 case 'o': /* 16 bit offset */
5826 c
= my_getSmallExpression (&offset_expr
, s
);
5828 /* If this value won't fit into a 16 bit offset, then go
5829 find a macro that will generate the 32 bit offset
5830 code pattern. As a special hack, we accept the
5831 difference of two local symbols as a constant. This
5832 is required to suppose embedded PIC switches, which
5833 use an instruction which looks like
5834 lw $4,$L12-$LS12($4)
5835 The problem with handling this in a more general
5836 fashion is that the macro function doesn't expect to
5837 see anything which can be handled in a single
5838 constant instruction. */
5840 && (offset_expr
.X_op
!= O_constant
5841 || offset_expr
.X_add_number
>= 0x8000
5842 || offset_expr
.X_add_number
< -0x8000)
5843 && (mips_pic
!= EMBEDDED_PIC
5844 || offset_expr
.X_op
!= O_subtract
5845 || now_seg
!= text_section
5846 || (S_GET_SEGMENT (offset_expr
.X_op_symbol
)
5850 offset_reloc
= BFD_RELOC_LO16
;
5851 if (c
== 'h' || c
== 'H')
5853 assert (offset_expr
.X_op
== O_constant
);
5854 offset_expr
.X_add_number
=
5855 (offset_expr
.X_add_number
>> 16) & 0xffff;
5860 case 'p': /* pc relative offset */
5861 offset_reloc
= BFD_RELOC_16_PCREL_S2
;
5862 my_getExpression (&offset_expr
, s
);
5866 case 'u': /* upper 16 bits */
5867 c
= my_getSmallExpression (&imm_expr
, s
);
5868 if (imm_expr
.X_op
== O_constant
5869 && (imm_expr
.X_add_number
< 0
5870 || imm_expr
.X_add_number
>= 0x10000))
5871 as_bad ("lui expression not in range 0..65535");
5872 imm_reloc
= BFD_RELOC_LO16
;
5877 if (imm_expr
.X_op
== O_constant
)
5878 imm_expr
.X_add_number
=
5879 (imm_expr
.X_add_number
>> 16) & 0xffff;
5882 imm_reloc
= BFD_RELOC_HI16_S
;
5883 imm_unmatched_hi
= true;
5886 imm_reloc
= BFD_RELOC_HI16
;
5892 case 'a': /* 26 bit address */
5893 my_getExpression (&offset_expr
, s
);
5895 offset_reloc
= BFD_RELOC_MIPS_JMP
;
5898 case 'N': /* 3 bit branch condition code */
5899 case 'M': /* 3 bit compare condition code */
5900 if (strncmp (s
, "$fcc", 4) != 0)
5910 while (isdigit (*s
));
5912 as_bad ("invalid condition code register $fcc%d", regno
);
5914 ip
->insn_opcode
|= regno
<< OP_SH_BCC
;
5916 ip
->insn_opcode
|= regno
<< OP_SH_CCC
;
5920 fprintf (stderr
, "bad char = '%c'\n", *args
);
5925 /* Args don't match. */
5926 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
5927 !strcmp (insn
->name
, insn
[1].name
))
5933 insn_error
= "illegal operands";
5942 my_getSmallExpression (ep
, str
)
5953 ((str
[1] == 'h' && str
[2] == 'i')
5954 || (str
[1] == 'H' && str
[2] == 'I')
5955 || (str
[1] == 'l' && str
[2] == 'o'))
5967 * A small expression may be followed by a base register.
5968 * Scan to the end of this operand, and then back over a possible
5969 * base register. Then scan the small expression up to that
5970 * point. (Based on code in sparc.c...)
5972 for (sp
= str
; *sp
&& *sp
!= ','; sp
++)
5974 if (sp
- 4 >= str
&& sp
[-1] == RP
)
5976 if (isdigit (sp
[-2]))
5978 for (sp
-= 3; sp
>= str
&& isdigit (*sp
); sp
--)
5980 if (*sp
== '$' && sp
> str
&& sp
[-1] == LP
)
5986 else if (sp
- 5 >= str
5989 && ((sp
[-3] == 'f' && sp
[-2] == 'p')
5990 || (sp
[-3] == 's' && sp
[-2] == 'p')
5991 || (sp
[-3] == 'g' && sp
[-2] == 'p')
5992 || (sp
[-3] == 'a' && sp
[-2] == 't')))
5998 /* no expression means zero offset */
6001 /* %xx(reg) is an error */
6002 ep
->X_op
= O_absent
;
6007 ep
->X_op
= O_constant
;
6010 ep
->X_add_symbol
= NULL
;
6011 ep
->X_op_symbol
= NULL
;
6012 ep
->X_add_number
= 0;
6017 my_getExpression (ep
, str
);
6024 my_getExpression (ep
, str
);
6025 return c
; /* => %hi or %lo encountered */
6029 my_getExpression (ep
, str
)
6035 save_in
= input_line_pointer
;
6036 input_line_pointer
= str
;
6038 expr_end
= input_line_pointer
;
6039 input_line_pointer
= save_in
;
6042 /* Turn a string in input_line_pointer into a floating point constant
6043 of type type, and store the appropriate bytes in *litP. The number
6044 of LITTLENUMS emitted is stored in *sizeP . An error message is
6045 returned, or NULL on OK. */
6048 md_atof (type
, litP
, sizeP
)
6054 LITTLENUM_TYPE words
[4];
6070 return "bad call to md_atof";
6073 t
= atof_ieee (input_line_pointer
, type
, words
);
6075 input_line_pointer
= t
;
6079 if (byte_order
== LITTLE_ENDIAN
)
6081 for (i
= prec
- 1; i
>= 0; i
--)
6083 md_number_to_chars (litP
, (valueT
) words
[i
], 2);
6089 for (i
= 0; i
< prec
; i
++)
6091 md_number_to_chars (litP
, (valueT
) words
[i
], 2);
6100 md_number_to_chars (buf
, val
, n
)
6108 number_to_chars_littleendian (buf
, val
, n
);
6112 number_to_chars_bigendian (buf
, val
, n
);
6120 CONST
char *md_shortopts
= "O::g::G:";
6122 struct option md_longopts
[] = {
6123 #define OPTION_MIPS1 (OPTION_MD_BASE + 1)
6124 {"mips0", no_argument
, NULL
, OPTION_MIPS1
},
6125 {"mips1", no_argument
, NULL
, OPTION_MIPS1
},
6126 #define OPTION_MIPS2 (OPTION_MD_BASE + 2)
6127 {"mips2", no_argument
, NULL
, OPTION_MIPS2
},
6128 #define OPTION_MIPS3 (OPTION_MD_BASE + 3)
6129 {"mips3", no_argument
, NULL
, OPTION_MIPS3
},
6130 #define OPTION_MIPS4 (OPTION_MD_BASE + 4)
6131 {"mips4", no_argument
, NULL
, OPTION_MIPS4
},
6132 #define OPTION_MCPU (OPTION_MD_BASE + 5)
6133 {"mcpu", required_argument
, NULL
, OPTION_MCPU
},
6134 #define OPTION_MEMBEDDED_PIC (OPTION_MD_BASE + 6)
6135 {"membedded-pic", no_argument
, NULL
, OPTION_MEMBEDDED_PIC
},
6136 #define OPTION_TRAP (OPTION_MD_BASE + 9)
6137 {"trap", no_argument
, NULL
, OPTION_TRAP
},
6138 {"no-break", no_argument
, NULL
, OPTION_TRAP
},
6139 #define OPTION_BREAK (OPTION_MD_BASE + 10)
6140 {"break", no_argument
, NULL
, OPTION_BREAK
},
6141 {"no-trap", no_argument
, NULL
, OPTION_BREAK
},
6142 #define OPTION_EB (OPTION_MD_BASE + 11)
6143 {"EB", no_argument
, NULL
, OPTION_EB
},
6144 #define OPTION_EL (OPTION_MD_BASE + 12)
6145 {"EL", no_argument
, NULL
, OPTION_EL
},
6146 #define OPTION_M4650 (OPTION_MD_BASE + 13)
6147 {"m4650", no_argument
, NULL
, OPTION_M4650
},
6148 #define OPTION_NO_M4650 (OPTION_MD_BASE + 14)
6149 {"no-m4650", no_argument
, NULL
, OPTION_NO_M4650
},
6150 #define OPTION_M4010 (OPTION_MD_BASE + 15)
6151 {"m4010", no_argument
, NULL
, OPTION_M4010
},
6152 #define OPTION_NO_M4010 (OPTION_MD_BASE + 16)
6153 {"no-m4010", no_argument
, NULL
, OPTION_NO_M4010
},
6154 #define OPTION_M4100 (OPTION_MD_BASE + 17)
6155 {"m4100", no_argument
, NULL
, OPTION_M4100
},
6156 #define OPTION_NO_M4100 (OPTION_MD_BASE + 18)
6157 {"no-m4100", no_argument
, NULL
, OPTION_NO_M4100
},
6159 #define OPTION_CALL_SHARED (OPTION_MD_BASE + 7)
6160 #define OPTION_NON_SHARED (OPTION_MD_BASE + 8)
6161 #define OPTION_XGOT (OPTION_MD_BASE + 19)
6162 #define OPTION_32 (OPTION_MD_BASE + 20)
6163 #define OPTION_64 (OPTION_MD_BASE + 21)
6165 {"KPIC", no_argument
, NULL
, OPTION_CALL_SHARED
},
6166 {"xgot", no_argument
, NULL
, OPTION_XGOT
},
6167 {"call_shared", no_argument
, NULL
, OPTION_CALL_SHARED
},
6168 {"non_shared", no_argument
, NULL
, OPTION_NON_SHARED
},
6169 {"32", no_argument
, NULL
, OPTION_32
},
6170 {"64", no_argument
, NULL
, OPTION_64
},
6173 {NULL
, no_argument
, NULL
, 0}
6175 size_t md_longopts_size
= sizeof(md_longopts
);
6178 md_parse_option (c
, arg
)
6193 target_big_endian
= 1;
6197 target_big_endian
= 0;
6201 if (arg
&& arg
[1] == '0')
6211 mips_debug
= atoi (arg
);
6212 /* When the MIPS assembler sees -g or -g2, it does not do
6213 optimizations which limit full symbolic debugging. We take
6214 that to be equivalent to -O0. */
6215 if (mips_debug
== 2)
6247 /* Identify the processor type */
6249 if (strcmp (p
, "default") == 0
6250 || strcmp (p
, "DEFAULT") == 0)
6256 /* We need to cope with the various "vr" prefixes for the 4300
6258 if (*p
== 'v' || *p
== 'V')
6264 if (*p
== 'r' || *p
== 'R')
6271 if (strcmp (p
, "10000") == 0
6272 || strcmp (p
, "10k") == 0
6273 || strcmp (p
, "10K") == 0)
6278 if (strcmp (p
, "2000") == 0
6279 || strcmp (p
, "2k") == 0
6280 || strcmp (p
, "2K") == 0)
6285 if (strcmp (p
, "3000") == 0
6286 || strcmp (p
, "3k") == 0
6287 || strcmp (p
, "3K") == 0)
6292 if (strcmp (p
, "4000") == 0
6293 || strcmp (p
, "4k") == 0
6294 || strcmp (p
, "4K") == 0)
6296 else if (strcmp (p
, "4100") == 0)
6302 else if (strcmp (p
, "4300") == 0)
6304 else if (strcmp (p
, "4400") == 0)
6306 else if (strcmp (p
, "4600") == 0)
6308 else if (strcmp (p
, "4650") == 0)
6314 else if (strcmp (p
, "4010") == 0)
6323 if (strcmp (p
, "5000") == 0
6324 || strcmp (p
, "5k") == 0
6325 || strcmp (p
, "5K") == 0)
6330 if (strcmp (p
, "6000") == 0
6331 || strcmp (p
, "6k") == 0
6332 || strcmp (p
, "6K") == 0)
6337 if (strcmp (p
, "8000") == 0
6338 || strcmp (p
, "8k") == 0
6339 || strcmp (p
, "8K") == 0)
6344 if (strcmp (p
, "orion") == 0)
6349 if (sv
&& mips_cpu
!= 4300 && mips_cpu
!= 4100 && mips_cpu
!= 5000)
6351 as_bad ("ignoring invalid leading 'v' in -mcpu=%s switch", arg
);
6357 as_bad ("invalid architecture -mcpu=%s", arg
);
6368 case OPTION_NO_M4650
:
6376 case OPTION_NO_M4010
:
6384 case OPTION_NO_M4100
:
6388 case OPTION_MEMBEDDED_PIC
:
6389 mips_pic
= EMBEDDED_PIC
;
6390 if (USE_GLOBAL_POINTER_OPT
&& g_switch_seen
)
6392 as_bad ("-G may not be used with embedded PIC code");
6395 g_switch_value
= 0x7fffffff;
6398 /* When generating ELF code, we permit -KPIC and -call_shared to
6399 select SVR4_PIC, and -non_shared to select no PIC. This is
6400 intended to be compatible with Irix 5. */
6401 case OPTION_CALL_SHARED
:
6402 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
6404 as_bad ("-call_shared is supported only for ELF format");
6407 mips_pic
= SVR4_PIC
;
6408 if (g_switch_seen
&& g_switch_value
!= 0)
6410 as_bad ("-G may not be used with SVR4 PIC code");
6416 case OPTION_NON_SHARED
:
6417 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
6419 as_bad ("-non_shared is supported only for ELF format");
6425 /* The -xgot option tells the assembler to use 32 offsets when
6426 accessing the got in SVR4_PIC mode. It is for Irix
6433 if (! USE_GLOBAL_POINTER_OPT
)
6435 as_bad ("-G is not supported for this configuration");
6438 else if (mips_pic
== SVR4_PIC
|| mips_pic
== EMBEDDED_PIC
)
6440 as_bad ("-G may not be used with SVR4 or embedded PIC code");
6444 g_switch_value
= atoi (arg
);
6448 /* The -32 and -64 options tell the assembler to output the 32
6449 bit or the 64 bit MIPS ELF format. */
6456 const char **list
, **l
;
6458 list
= bfd_target_list ();
6459 for (l
= list
; *l
!= NULL
; l
++)
6460 if (strcmp (*l
, "elf64-bigmips") == 0
6461 || strcmp (*l
, "elf64-littlemips") == 0)
6464 as_fatal ("No compiled in support for 64 bit object file format");
6478 md_show_usage (stream
)
6483 -membedded-pic generate embedded position independent code\n\
6484 -EB generate big endian output\n\
6485 -EL generate little endian output\n\
6486 -g, -g2 do not remove uneeded NOPs or swap branches\n\
6487 -G NUM allow referencing objects up to NUM bytes\n\
6488 implicitly with the gp register [default 8]\n");
6490 -mips1, -mcpu=r{2,3}000 generate code for r2000 and r3000\n\
6491 -mips2, -mcpu=r6000 generate code for r6000\n\
6492 -mips3, -mcpu=r4000 generate code for r4000\n\
6493 -mips4, -mcpu=r8000 generate code for r8000\n\
6494 -mcpu=vr4300 generate code for vr4300\n\
6495 -mcpu=vr4100 generate code for vr4100\n\
6496 -m4650 permit R4650 instructions\n\
6497 -no-m4650 do not permit R4650 instructions\n\
6498 -m4010 permit R4010 instructions\n\
6499 -no-m4010 do not permit R4010 instructions\n\
6500 -m4100 permit VR4100 instructions\n\
6501 -no-m4100 do not permit VR4100 instructions\n");
6503 -O0 remove unneeded NOPs, do not swap branches\n\
6504 -O remove unneeded NOPs and swap branches\n\
6505 --trap, --no-break trap exception on div by 0 and mult overflow\n\
6506 --break, --no-trap break exception on div by 0 and mult overflow\n");
6509 -KPIC, -call_shared generate SVR4 position independent code\n\
6510 -non_shared do not generate position independent code\n\
6511 -xgot assume a 32 bit GOT\n\
6512 -32 create 32 bit object file (default)\n\
6513 -64 create 64 bit object file\n");
6518 mips_init_after_args ()
6520 if (target_big_endian
)
6521 byte_order
= BIG_ENDIAN
;
6523 byte_order
= LITTLE_ENDIAN
;
6527 md_pcrel_from (fixP
)
6530 if (OUTPUT_FLAVOR
!= bfd_target_aout_flavour
6531 && fixP
->fx_addsy
!= (symbolS
*) NULL
6532 && ! S_IS_DEFINED (fixP
->fx_addsy
))
6534 /* This makes a branch to an undefined symbol be a branch to the
6535 current location. */
6539 /* return the address of the delay slot */
6540 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
6543 /* This is called by emit_expr via TC_CONS_FIX_NEW when creating a
6544 reloc for a cons. We could use the definition there, except that
6545 we want to handle 64 bit relocs specially. */
6548 cons_fix_new_mips (frag
, where
, nbytes
, exp
)
6551 unsigned int nbytes
;
6555 /* If we are assembling in 32 bit mode, turn an 8 byte reloc into a
6557 if (nbytes
== 8 && ! mips_64
)
6559 if (byte_order
== BIG_ENDIAN
)
6565 if (nbytes
!= 2 && nbytes
!= 4 && nbytes
!= 8)
6566 as_bad ("Unsupported reloc size %d", nbytes
);
6568 fix_new_exp (frag_now
, where
, (int) nbytes
, exp
, 0,
6571 : (nbytes
== 4 ? BFD_RELOC_32
: BFD_RELOC_64
)));
6574 /* Sort any unmatched HI16_S relocs so that they immediately precede
6575 the corresponding LO reloc. This is called before md_apply_fix and
6576 tc_gen_reloc. Unmatched HI16_S relocs can only be generated by
6577 explicit use of the %hi modifier. */
6582 struct mips_hi_fixup
*l
;
6584 for (l
= mips_hi_fixup_list
; l
!= NULL
; l
= l
->next
)
6586 segment_info_type
*seginfo
;
6589 assert (l
->fixp
->fx_r_type
== BFD_RELOC_HI16_S
);
6591 /* Check quickly whether the next fixup happens to be a matching
6593 if (l
->fixp
->fx_next
!= NULL
6594 && l
->fixp
->fx_next
->fx_r_type
== BFD_RELOC_LO16
6595 && l
->fixp
->fx_addsy
== l
->fixp
->fx_next
->fx_addsy
6596 && l
->fixp
->fx_offset
== l
->fixp
->fx_next
->fx_offset
)
6599 /* Look through the fixups for this segment for a matching %lo.
6600 When we find one, move the %hi just in front of it. We do
6601 this in two passes. In the first pass, we try to find a
6602 unique %lo. In the second pass, we permit multiple %hi
6603 relocs for a single %lo (this is a GNU extension). */
6604 seginfo
= seg_info (l
->seg
);
6605 for (pass
= 0; pass
< 2; pass
++)
6610 for (f
= seginfo
->fix_root
; f
!= NULL
; f
= f
->fx_next
)
6612 /* Check whether this is a %lo fixup which matches l->fixp. */
6613 if (f
->fx_r_type
== BFD_RELOC_LO16
6614 && f
->fx_addsy
== l
->fixp
->fx_addsy
6615 && f
->fx_offset
== l
->fixp
->fx_offset
6618 || prev
->fx_r_type
!= BFD_RELOC_HI16_S
6619 || prev
->fx_addsy
!= f
->fx_addsy
6620 || prev
->fx_offset
!= f
->fx_offset
))
6624 /* Move l->fixp before f. */
6625 for (pf
= &seginfo
->fix_root
;
6627 pf
= &(*pf
)->fx_next
)
6628 assert (*pf
!= NULL
);
6630 *pf
= l
->fixp
->fx_next
;
6632 l
->fixp
->fx_next
= f
;
6634 seginfo
->fix_root
= l
->fixp
;
6636 prev
->fx_next
= l
->fixp
;
6648 as_warn_where (l
->fixp
->fx_file
, l
->fixp
->fx_line
,
6649 "Unmatched %%hi reloc");
6654 /* When generating embedded PIC code we need to use a special
6655 relocation to represent the difference of two symbols in the .text
6656 section (switch tables use a difference of this sort). See
6657 include/coff/mips.h for details. This macro checks whether this
6658 fixup requires the special reloc. */
6659 #define SWITCH_TABLE(fixp) \
6660 ((fixp)->fx_r_type == BFD_RELOC_32 \
6661 && (fixp)->fx_addsy != NULL \
6662 && (fixp)->fx_subsy != NULL \
6663 && S_GET_SEGMENT ((fixp)->fx_addsy) == text_section \
6664 && S_GET_SEGMENT ((fixp)->fx_subsy) == text_section)
6666 /* When generating embedded PIC code we must keep all PC relative
6667 relocations, in case the linker has to relax a call. We also need
6668 to keep relocations for switch table entries. */
6672 mips_force_relocation (fixp
)
6675 return (mips_pic
== EMBEDDED_PIC
6677 || SWITCH_TABLE (fixp
)
6678 || fixp
->fx_r_type
== BFD_RELOC_PCREL_HI16_S
6679 || fixp
->fx_r_type
== BFD_RELOC_PCREL_LO16
));
6682 /* Apply a fixup to the object file. */
6685 md_apply_fix (fixP
, valueP
)
6692 assert (fixP
->fx_size
== 4
6693 || fixP
->fx_r_type
== BFD_RELOC_16
6694 || fixP
->fx_r_type
== BFD_RELOC_64
);
6697 fixP
->fx_addnumber
= value
; /* Remember value for tc_gen_reloc */
6699 if (fixP
->fx_addsy
== NULL
&& ! fixP
->fx_pcrel
)
6702 switch (fixP
->fx_r_type
)
6704 case BFD_RELOC_MIPS_JMP
:
6705 case BFD_RELOC_HI16
:
6706 case BFD_RELOC_HI16_S
:
6707 case BFD_RELOC_MIPS_GPREL
:
6708 case BFD_RELOC_MIPS_LITERAL
:
6709 case BFD_RELOC_MIPS_CALL16
:
6710 case BFD_RELOC_MIPS_GOT16
:
6711 case BFD_RELOC_MIPS_GPREL32
:
6712 case BFD_RELOC_MIPS_GOT_HI16
:
6713 case BFD_RELOC_MIPS_GOT_LO16
:
6714 case BFD_RELOC_MIPS_CALL_HI16
:
6715 case BFD_RELOC_MIPS_CALL_LO16
:
6717 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
6718 "Invalid PC relative reloc");
6719 /* Nothing needed to do. The value comes from the reloc entry */
6722 case BFD_RELOC_PCREL_HI16_S
:
6723 /* The addend for this is tricky if it is internal, so we just
6724 do everything here rather than in bfd_perform_relocation. */
6725 if ((fixP
->fx_addsy
->bsym
->flags
& BSF_SECTION_SYM
) == 0)
6727 /* For an external symbol adjust by the address to make it
6728 pcrel_offset. We use the address of the RELLO reloc
6729 which follows this one. */
6730 value
+= (fixP
->fx_next
->fx_frag
->fr_address
6731 + fixP
->fx_next
->fx_where
);
6736 buf
= (unsigned char *) fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
6737 if (byte_order
== BIG_ENDIAN
)
6739 md_number_to_chars (buf
, value
, 2);
6742 case BFD_RELOC_PCREL_LO16
:
6743 /* The addend for this is tricky if it is internal, so we just
6744 do everything here rather than in bfd_perform_relocation. */
6745 if ((fixP
->fx_addsy
->bsym
->flags
& BSF_SECTION_SYM
) == 0)
6746 value
+= fixP
->fx_frag
->fr_address
+ fixP
->fx_where
;
6747 buf
= (unsigned char *) fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
6748 if (byte_order
== BIG_ENDIAN
)
6750 md_number_to_chars (buf
, value
, 2);
6754 /* This is handled like BFD_RELOC_32, but we output a sign
6755 extended value if we are only 32 bits. */
6757 || (mips_pic
== EMBEDDED_PIC
&& SWITCH_TABLE (fixP
)))
6759 if (8 <= sizeof (valueT
))
6760 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
,
6767 w1
= w2
= fixP
->fx_where
;
6768 if (byte_order
== BIG_ENDIAN
)
6772 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ w1
, value
, 4);
6773 if ((value
& 0x80000000) != 0)
6777 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ w2
, hiv
, 4);
6783 /* If we are deleting this reloc entry, we must fill in the
6784 value now. This can happen if we have a .word which is not
6785 resolved when it appears but is later defined. We also need
6786 to fill in the value if this is an embedded PIC switch table
6789 || (mips_pic
== EMBEDDED_PIC
&& SWITCH_TABLE (fixP
)))
6790 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
,
6795 /* If we are deleting this reloc entry, we must fill in the
6797 assert (fixP
->fx_size
== 2);
6799 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
,
6803 case BFD_RELOC_LO16
:
6804 /* When handling an embedded PIC switch statement, we can wind
6805 up deleting a LO16 reloc. See the 'o' case in mips_ip. */
6808 if (value
< -0x8000 || value
> 0x7fff)
6809 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
6810 "relocation overflow");
6811 buf
= (unsigned char *) fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
6812 if (byte_order
== BIG_ENDIAN
)
6814 md_number_to_chars (buf
, value
, 2);
6818 case BFD_RELOC_16_PCREL_S2
:
6820 * We need to save the bits in the instruction since fixup_segment()
6821 * might be deleting the relocation entry (i.e., a branch within
6822 * the current segment).
6825 as_warn_where (fixP
->fx_file
, fixP
->fx_line
,
6826 "Branch to odd address (%lx)", value
);
6829 /* update old instruction data */
6830 buf
= (unsigned char *) (fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
);
6834 insn
= (buf
[3] << 24) | (buf
[2] << 16) | (buf
[1] << 8) | buf
[0];
6838 insn
= (buf
[0] << 24) | (buf
[1] << 16) | (buf
[2] << 8) | buf
[3];
6846 if (value
>= -0x8000 && value
< 0x8000)
6847 insn
|= value
& 0xffff;
6850 /* The branch offset is too large. If this is an
6851 unconditional branch, and we are not generating PIC code,
6852 we can convert it to an absolute jump instruction. */
6853 if (mips_pic
== NO_PIC
6855 && fixP
->fx_frag
->fr_address
>= text_section
->vma
6856 && (fixP
->fx_frag
->fr_address
6857 < text_section
->vma
+ text_section
->_raw_size
)
6858 && ((insn
& 0xffff0000) == 0x10000000 /* beq $0,$0 */
6859 || (insn
& 0xffff0000) == 0x04010000 /* bgez $0 */
6860 || (insn
& 0xffff0000) == 0x04110000)) /* bgezal $0 */
6862 if ((insn
& 0xffff0000) == 0x04110000) /* bgezal $0 */
6863 insn
= 0x0c000000; /* jal */
6865 insn
= 0x08000000; /* j */
6866 fixP
->fx_r_type
= BFD_RELOC_MIPS_JMP
;
6868 fixP
->fx_addsy
= section_symbol (text_section
);
6869 fixP
->fx_addnumber
= (value
<< 2) + md_pcrel_from (fixP
);
6873 /* FIXME. It would be possible in principle to handle
6874 conditional branches which overflow. They could be
6875 transformed into a branch around a jump. This would
6876 require setting up variant frags for each different
6877 branch type. The native MIPS assembler attempts to
6878 handle these cases, but it appears to do it
6880 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
6881 "Relocation overflow");
6885 md_number_to_chars ((char *) buf
, (valueT
) insn
, 4);
6900 const struct mips_opcode
*p
;
6901 int treg
, sreg
, dreg
, shamt
;
6906 for (i
= 0; i
< NUMOPCODES
; ++i
)
6908 p
= &mips_opcodes
[i
];
6909 if (((oc
& p
->mask
) == p
->match
) && (p
->pinfo
!= INSN_MACRO
))
6911 printf ("%08lx %s\t", oc
, p
->name
);
6912 treg
= (oc
>> 16) & 0x1f;
6913 sreg
= (oc
>> 21) & 0x1f;
6914 dreg
= (oc
>> 11) & 0x1f;
6915 shamt
= (oc
>> 6) & 0x1f;
6917 for (args
= p
->args
;; ++args
)
6928 printf ("%c", *args
);
6932 assert (treg
== sreg
);
6933 printf ("$%d,$%d", treg
, sreg
);
6938 printf ("$%d", dreg
);
6943 printf ("$%d", treg
);
6947 printf ("0x%x", treg
);
6952 printf ("$%d", sreg
);
6956 printf ("0x%08lx", oc
& 0x1ffffff);
6968 printf ("$%d", shamt
);
6979 printf ("%08lx UNDEFINED\n", oc
);
6990 name
= input_line_pointer
;
6991 c
= get_symbol_end ();
6992 p
= (symbolS
*) symbol_find_or_make (name
);
6993 *input_line_pointer
= c
;
6997 /* Align the current frag to a given power of two. The MIPS assembler
6998 also automatically adjusts any preceding label. */
7001 mips_align (to
, fill
, label
)
7006 mips_emit_delays ();
7007 frag_align (to
, fill
);
7008 record_alignment (now_seg
, to
);
7011 assert (S_GET_SEGMENT (label
) == now_seg
);
7012 label
->sy_frag
= frag_now
;
7013 S_SET_VALUE (label
, (valueT
) frag_now_fix ());
7017 /* Align to a given power of two. .align 0 turns off the automatic
7018 alignment used by the data creating pseudo-ops. */
7025 register long temp_fill
;
7026 long max_alignment
= 15;
7030 o Note that the assembler pulls down any immediately preceeding label
7031 to the aligned address.
7032 o It's not documented but auto alignment is reinstated by
7033 a .align pseudo instruction.
7034 o Note also that after auto alignment is turned off the mips assembler
7035 issues an error on attempt to assemble an improperly aligned data item.
7040 temp
= get_absolute_expression ();
7041 if (temp
> max_alignment
)
7042 as_bad ("Alignment too large: %d. assumed.", temp
= max_alignment
);
7045 as_warn ("Alignment negative: 0 assumed.");
7048 if (*input_line_pointer
== ',')
7050 input_line_pointer
++;
7051 temp_fill
= get_absolute_expression ();
7058 mips_align (temp
, (int) temp_fill
, insn_label
);
7065 demand_empty_rest_of_line ();
7069 mips_flush_pending_output ()
7071 mips_emit_delays ();
7081 /* When generating embedded PIC code, we only use the .text, .lit8,
7082 .sdata and .sbss sections. We change the .data and .rdata
7083 pseudo-ops to use .sdata. */
7084 if (mips_pic
== EMBEDDED_PIC
7085 && (sec
== 'd' || sec
== 'r'))
7088 mips_emit_delays ();
7098 subseg_set (bss_section
, (subsegT
) get_absolute_expression ());
7099 demand_empty_rest_of_line ();
7103 if (USE_GLOBAL_POINTER_OPT
)
7105 seg
= subseg_new (RDATA_SECTION_NAME
,
7106 (subsegT
) get_absolute_expression ());
7107 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
7109 bfd_set_section_flags (stdoutput
, seg
,
7115 bfd_set_section_alignment (stdoutput
, seg
, 4);
7117 demand_empty_rest_of_line ();
7121 as_bad ("No read only data section in this object file format");
7122 demand_empty_rest_of_line ();
7128 if (USE_GLOBAL_POINTER_OPT
)
7130 seg
= subseg_new (".sdata", (subsegT
) get_absolute_expression ());
7131 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
7133 bfd_set_section_flags (stdoutput
, seg
,
7134 SEC_ALLOC
| SEC_LOAD
| SEC_RELOC
7136 bfd_set_section_alignment (stdoutput
, seg
, 4);
7138 demand_empty_rest_of_line ();
7143 as_bad ("Global pointers not supported; recompile -G 0");
7144 demand_empty_rest_of_line ();
7153 mips_enable_auto_align ()
7165 mips_emit_delays ();
7166 if (log_size
> 0 && auto_align
)
7167 mips_align (log_size
, 0, label
);
7169 cons (1 << log_size
);
7180 mips_emit_delays ();
7184 mips_align (3, 0, label
);
7186 mips_align (2, 0, label
);
7193 /* Handle .globl. We need to override it because on Irix 5 you are
7196 where foo is an undefined symbol, to mean that foo should be
7197 considered to be the address of a function. */
7208 name
= input_line_pointer
;
7209 c
= get_symbol_end ();
7210 symbolP
= symbol_find_or_make (name
);
7211 *input_line_pointer
= c
;
7214 /* On Irix 5, every global symbol that is not explicitly labelled as
7215 being a function is apparently labelled as being an object. */
7218 if (! is_end_of_line
[(unsigned char) *input_line_pointer
])
7223 secname
= input_line_pointer
;
7224 c
= get_symbol_end ();
7225 sec
= bfd_get_section_by_name (stdoutput
, secname
);
7227 as_bad ("%s: no such section", secname
);
7228 *input_line_pointer
= c
;
7230 if (sec
!= NULL
&& (sec
->flags
& SEC_CODE
) != 0)
7231 flag
= BSF_FUNCTION
;
7234 symbolP
->bsym
->flags
|= flag
;
7236 S_SET_EXTERNAL (symbolP
);
7237 demand_empty_rest_of_line ();
7247 opt
= input_line_pointer
;
7248 c
= get_symbol_end ();
7252 /* FIXME: What does this mean? */
7254 else if (strncmp (opt
, "pic", 3) == 0)
7262 mips_pic
= SVR4_PIC
;
7264 as_bad (".option pic%d not supported", i
);
7266 if (USE_GLOBAL_POINTER_OPT
&& mips_pic
== SVR4_PIC
)
7268 if (g_switch_seen
&& g_switch_value
!= 0)
7269 as_warn ("-G may not be used with SVR4 PIC code");
7271 bfd_set_gp_size (stdoutput
, 0);
7275 as_warn ("Unrecognized option \"%s\"", opt
);
7277 *input_line_pointer
= c
;
7278 demand_empty_rest_of_line ();
7285 char *name
= input_line_pointer
, ch
;
7287 while (!is_end_of_line
[(unsigned char) *input_line_pointer
])
7288 input_line_pointer
++;
7289 ch
= *input_line_pointer
;
7290 *input_line_pointer
= '\0';
7292 if (strcmp (name
, "reorder") == 0)
7296 prev_insn_unreordered
= 1;
7297 prev_prev_insn_unreordered
= 1;
7301 else if (strcmp (name
, "noreorder") == 0)
7303 mips_emit_delays ();
7305 mips_any_noreorder
= 1;
7307 else if (strcmp (name
, "at") == 0)
7311 else if (strcmp (name
, "noat") == 0)
7315 else if (strcmp (name
, "macro") == 0)
7317 mips_warn_about_macros
= 0;
7319 else if (strcmp (name
, "nomacro") == 0)
7321 if (mips_noreorder
== 0)
7322 as_bad ("`noreorder' must be set before `nomacro'");
7323 mips_warn_about_macros
= 1;
7325 else if (strcmp (name
, "move") == 0 || strcmp (name
, "novolatile") == 0)
7329 else if (strcmp (name
, "nomove") == 0 || strcmp (name
, "volatile") == 0)
7333 else if (strcmp (name
, "bopt") == 0)
7337 else if (strcmp (name
, "nobopt") == 0)
7341 else if (strncmp (name
, "mips", 4) == 0)
7345 /* Permit the user to change the ISA on the fly. Needless to
7346 say, misuse can cause serious problems. */
7347 isa
= atoi (name
+ 4);
7349 mips_isa
= file_mips_isa
;
7350 else if (isa
< 1 || isa
> 4)
7351 as_bad ("unknown ISA level");
7357 as_warn ("Tried to set unrecognized symbol: %s\n", name
);
7359 *input_line_pointer
= ch
;
7360 demand_empty_rest_of_line ();
7363 /* Handle the .abicalls pseudo-op. I believe this is equivalent to
7364 .option pic2. It means to generate SVR4 PIC calls. */
7370 mips_pic
= SVR4_PIC
;
7371 if (USE_GLOBAL_POINTER_OPT
)
7373 if (g_switch_seen
&& g_switch_value
!= 0)
7374 as_warn ("-G may not be used with SVR4 PIC code");
7377 bfd_set_gp_size (stdoutput
, 0);
7378 demand_empty_rest_of_line ();
7381 /* Handle the .cpload pseudo-op. This is used when generating SVR4
7382 PIC code. It sets the $gp register for the function based on the
7383 function address, which is in the register named in the argument.
7384 This uses a relocation against _gp_disp, which is handled specially
7385 by the linker. The result is:
7386 lui $gp,%hi(_gp_disp)
7387 addiu $gp,$gp,%lo(_gp_disp)
7388 addu $gp,$gp,.cpload argument
7389 The .cpload argument is normally $25 == $t9. */
7398 /* If we are not generating SVR4 PIC code, .cpload is ignored. */
7399 if (mips_pic
!= SVR4_PIC
)
7405 /* .cpload should be a in .set noreorder section. */
7406 if (mips_noreorder
== 0)
7407 as_warn (".cpload not in noreorder section");
7410 ex
.X_add_symbol
= symbol_find_or_make ("_gp_disp");
7411 ex
.X_op_symbol
= NULL
;
7412 ex
.X_add_number
= 0;
7414 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
7415 ex
.X_add_symbol
->bsym
->flags
|= BSF_OBJECT
;
7417 macro_build_lui ((char *) NULL
, &icnt
, &ex
, GP
);
7418 macro_build ((char *) NULL
, &icnt
, &ex
, "addiu", "t,r,j", GP
, GP
,
7419 (int) BFD_RELOC_LO16
);
7421 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "addu", "d,v,t",
7422 GP
, GP
, tc_get_register (0));
7424 demand_empty_rest_of_line ();
7427 /* Handle the .cprestore pseudo-op. This stores $gp into a given
7428 offset from $sp. The offset is remembered, and after making a PIC
7429 call $gp is restored from that location. */
7432 s_cprestore (ignore
)
7438 /* If we are not generating SVR4 PIC code, .cprestore is ignored. */
7439 if (mips_pic
!= SVR4_PIC
)
7445 mips_cprestore_offset
= get_absolute_expression ();
7447 ex
.X_op
= O_constant
;
7448 ex
.X_add_symbol
= NULL
;
7449 ex
.X_op_symbol
= NULL
;
7450 ex
.X_add_number
= mips_cprestore_offset
;
7452 macro_build ((char *) NULL
, &icnt
, &ex
,
7453 mips_isa
< 3 ? "sw" : "sd",
7454 "t,o(b)", GP
, (int) BFD_RELOC_LO16
, SP
);
7456 demand_empty_rest_of_line ();
7459 /* Handle the .gpword pseudo-op. This is used when generating PIC
7460 code. It generates a 32 bit GP relative reloc. */
7470 /* When not generating PIC code, this is treated as .word. */
7471 if (mips_pic
!= SVR4_PIC
)
7478 mips_emit_delays ();
7480 mips_align (2, 0, label
);
7485 if (ex
.X_op
!= O_symbol
|| ex
.X_add_number
!= 0)
7487 as_bad ("Unsupported use of .gpword");
7488 ignore_rest_of_line ();
7492 md_number_to_chars (p
, (valueT
) 0, 4);
7493 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 4, &ex
, 0,
7494 BFD_RELOC_MIPS_GPREL32
);
7496 demand_empty_rest_of_line ();
7499 /* Handle the .cpadd pseudo-op. This is used when dealing with switch
7500 tables in SVR4 PIC code. */
7509 /* This is ignored when not generating SVR4 PIC code. */
7510 if (mips_pic
!= SVR4_PIC
)
7516 /* Add $gp to the register named as an argument. */
7517 reg
= tc_get_register (0);
7518 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
7519 mips_isa
< 3 ? "addu" : "daddu",
7520 "d,v,t", reg
, reg
, GP
);
7522 demand_empty_rest_of_line ();
7525 /* Parse a register string into a number. Called from the ECOFF code
7526 to parse .frame. The argument is non-zero if this is the frame
7527 register, so that we can record it in mips_frame_reg. */
7530 tc_get_register (frame
)
7536 if (*input_line_pointer
++ != '$')
7538 as_warn ("expected `$'");
7541 else if (isdigit ((unsigned char) *input_line_pointer
))
7543 reg
= get_absolute_expression ();
7544 if (reg
< 0 || reg
>= 32)
7546 as_warn ("Bad register number");
7552 if (strncmp (input_line_pointer
, "fp", 2) == 0)
7554 else if (strncmp (input_line_pointer
, "sp", 2) == 0)
7556 else if (strncmp (input_line_pointer
, "gp", 2) == 0)
7558 else if (strncmp (input_line_pointer
, "at", 2) == 0)
7562 as_warn ("Unrecognized register name");
7565 input_line_pointer
+= 2;
7568 mips_frame_reg
= reg
!= 0 ? reg
: SP
;
7573 md_section_align (seg
, addr
)
7577 int align
= bfd_get_section_alignment (stdoutput
, seg
);
7580 /* We don't need to align ELF sections to the full alignment.
7581 However, Irix 5 may prefer that we align them at least to a 16
7587 return ((addr
+ (1 << align
) - 1) & (-1 << align
));
7590 /* Utility routine, called from above as well. If called while the
7591 input file is still being read, it's only an approximation. (For
7592 example, a symbol may later become defined which appeared to be
7593 undefined earlier.) */
7596 nopic_need_relax (sym
)
7602 if (USE_GLOBAL_POINTER_OPT
)
7604 const char *symname
;
7607 /* Find out whether this symbol can be referenced off the GP
7608 register. It can be if it is smaller than the -G size or if
7609 it is in the .sdata or .sbss section. Certain symbols can
7610 not be referenced off the GP, although it appears as though
7612 symname
= S_GET_NAME (sym
);
7613 if (symname
!= (const char *) NULL
7614 && (strcmp (symname
, "eprol") == 0
7615 || strcmp (symname
, "etext") == 0
7616 || strcmp (symname
, "_gp") == 0
7617 || strcmp (symname
, "edata") == 0
7618 || strcmp (symname
, "_fbss") == 0
7619 || strcmp (symname
, "_fdata") == 0
7620 || strcmp (symname
, "_ftext") == 0
7621 || strcmp (symname
, "end") == 0
7622 || strcmp (symname
, "_gp_disp") == 0))
7624 else if (! S_IS_DEFINED (sym
)
7626 #ifndef NO_ECOFF_DEBUGGING
7627 || (sym
->ecoff_extern_size
!= 0
7628 && sym
->ecoff_extern_size
<= g_switch_value
)
7630 || (S_GET_VALUE (sym
) != 0
7631 && S_GET_VALUE (sym
) <= g_switch_value
)))
7635 const char *segname
;
7637 segname
= segment_name (S_GET_SEGMENT (sym
));
7638 assert (strcmp (segname
, ".lit8") != 0
7639 && strcmp (segname
, ".lit4") != 0);
7640 change
= (strcmp (segname
, ".sdata") != 0
7641 && strcmp (segname
, ".sbss") != 0);
7646 /* We are not optimizing for the GP register. */
7650 /* Estimate the size of a frag before relaxing. We are not really
7651 relaxing here, and the final size is encoded in the subtype
7656 md_estimate_size_before_relax (fragp
, segtype
)
7662 if (mips_pic
== NO_PIC
)
7664 change
= nopic_need_relax (fragp
->fr_symbol
);
7666 else if (mips_pic
== SVR4_PIC
)
7668 asection
*symsec
= fragp
->fr_symbol
->bsym
->section
;
7670 /* This must duplicate the test in adjust_reloc_syms. */
7671 change
= (symsec
!= &bfd_und_section
7672 && symsec
!= &bfd_abs_section
7673 && ! bfd_is_com_section (symsec
));
7680 /* Record the offset to the first reloc in the fr_opcode field.
7681 This lets md_convert_frag and tc_gen_reloc know that the code
7682 must be expanded. */
7683 fragp
->fr_opcode
= (fragp
->fr_literal
7685 - RELAX_OLD (fragp
->fr_subtype
)
7686 + RELAX_RELOC1 (fragp
->fr_subtype
));
7687 /* FIXME: This really needs as_warn_where. */
7688 if (RELAX_WARN (fragp
->fr_subtype
))
7689 as_warn ("AT used after \".set noat\" or macro used after \".set nomacro\"");
7695 return RELAX_NEW (fragp
->fr_subtype
) - RELAX_OLD (fragp
->fr_subtype
);
7698 /* Translate internal representation of relocation info to BFD target
7702 tc_gen_reloc (section
, fixp
)
7706 static arelent
*retval
[4];
7708 bfd_reloc_code_real_type code
;
7710 reloc
= retval
[0] = (arelent
*) xmalloc (sizeof (arelent
));
7713 reloc
->sym_ptr_ptr
= &fixp
->fx_addsy
->bsym
;
7714 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
7716 if (mips_pic
== EMBEDDED_PIC
7717 && SWITCH_TABLE (fixp
))
7719 /* For a switch table entry we use a special reloc. The addend
7720 is actually the difference between the reloc address and the
7722 reloc
->addend
= reloc
->address
- S_GET_VALUE (fixp
->fx_subsy
);
7723 if (OUTPUT_FLAVOR
!= bfd_target_ecoff_flavour
)
7724 as_fatal ("Double check fx_r_type in tc-mips.c:tc_gen_reloc");
7725 fixp
->fx_r_type
= BFD_RELOC_GPREL32
;
7727 else if (fixp
->fx_r_type
== BFD_RELOC_PCREL_LO16
)
7729 /* We use a special addend for an internal RELLO reloc. */
7730 if (fixp
->fx_addsy
->bsym
->flags
& BSF_SECTION_SYM
)
7731 reloc
->addend
= reloc
->address
- S_GET_VALUE (fixp
->fx_subsy
);
7733 reloc
->addend
= fixp
->fx_addnumber
+ reloc
->address
;
7735 else if (fixp
->fx_r_type
== BFD_RELOC_PCREL_HI16_S
)
7737 assert (fixp
->fx_next
!= NULL
7738 && fixp
->fx_next
->fx_r_type
== BFD_RELOC_PCREL_LO16
);
7739 /* We use a special addend for an internal RELHI reloc. The
7740 reloc is relative to the RELLO; adjust the addend
7742 if (fixp
->fx_addsy
->bsym
->flags
& BSF_SECTION_SYM
)
7743 reloc
->addend
= (fixp
->fx_next
->fx_frag
->fr_address
7744 + fixp
->fx_next
->fx_where
7745 - S_GET_VALUE (fixp
->fx_subsy
));
7747 reloc
->addend
= (fixp
->fx_addnumber
7748 + fixp
->fx_next
->fx_frag
->fr_address
7749 + fixp
->fx_next
->fx_where
);
7751 else if (fixp
->fx_pcrel
== 0)
7752 reloc
->addend
= fixp
->fx_addnumber
;
7755 if (OUTPUT_FLAVOR
!= bfd_target_aout_flavour
)
7756 /* A gruesome hack which is a result of the gruesome gas reloc
7758 reloc
->addend
= reloc
->address
;
7760 reloc
->addend
= -reloc
->address
;
7763 /* If this is a variant frag, we may need to adjust the existing
7764 reloc and generate a new one. */
7765 if (fixp
->fx_frag
->fr_opcode
!= NULL
7766 && (fixp
->fx_r_type
== BFD_RELOC_MIPS_GPREL
7767 || fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT16
7768 || fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL16
7769 || fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT_HI16
7770 || fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT_LO16
7771 || fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL_HI16
7772 || fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL_LO16
))
7776 /* If this is not the last reloc in this frag, then we have two
7777 GPREL relocs, or a GOT_HI16/GOT_LO16 pair, or a
7778 CALL_HI16/CALL_LO16, both of which are being replaced. Let
7779 the second one handle all of them. */
7780 if (fixp
->fx_next
!= NULL
7781 && fixp
->fx_frag
== fixp
->fx_next
->fx_frag
)
7783 assert ((fixp
->fx_r_type
== BFD_RELOC_MIPS_GPREL
7784 && fixp
->fx_next
->fx_r_type
== BFD_RELOC_MIPS_GPREL
)
7785 || (fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT_HI16
7786 && (fixp
->fx_next
->fx_r_type
7787 == BFD_RELOC_MIPS_GOT_LO16
))
7788 || (fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL_HI16
7789 && (fixp
->fx_next
->fx_r_type
7790 == BFD_RELOC_MIPS_CALL_LO16
)));
7795 fixp
->fx_where
= fixp
->fx_frag
->fr_opcode
- fixp
->fx_frag
->fr_literal
;
7796 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
7797 reloc2
= retval
[1] = (arelent
*) xmalloc (sizeof (arelent
));
7799 reloc2
->sym_ptr_ptr
= &fixp
->fx_addsy
->bsym
;
7800 reloc2
->address
= (reloc
->address
7801 + (RELAX_RELOC2 (fixp
->fx_frag
->fr_subtype
)
7802 - RELAX_RELOC1 (fixp
->fx_frag
->fr_subtype
)));
7803 reloc2
->addend
= fixp
->fx_addnumber
;
7804 reloc2
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_LO16
);
7805 assert (reloc2
->howto
!= NULL
);
7807 if (RELAX_RELOC3 (fixp
->fx_frag
->fr_subtype
))
7811 reloc3
= retval
[2] = (arelent
*) xmalloc (sizeof (arelent
));
7814 reloc3
->address
+= 4;
7817 if (mips_pic
== NO_PIC
)
7819 assert (fixp
->fx_r_type
== BFD_RELOC_MIPS_GPREL
);
7820 fixp
->fx_r_type
= BFD_RELOC_HI16_S
;
7822 else if (mips_pic
== SVR4_PIC
)
7824 switch (fixp
->fx_r_type
)
7828 case BFD_RELOC_MIPS_GOT16
:
7830 case BFD_RELOC_MIPS_CALL16
:
7831 case BFD_RELOC_MIPS_GOT_LO16
:
7832 case BFD_RELOC_MIPS_CALL_LO16
:
7833 fixp
->fx_r_type
= BFD_RELOC_MIPS_GOT16
;
7841 /* Since DIFF_EXPR_OK is defined in tc-mips.h, it is possible that
7842 fixup_segment converted a non-PC relative reloc into a PC
7843 relative reloc. In such a case, we need to convert the reloc
7845 code
= fixp
->fx_r_type
;
7851 code
= BFD_RELOC_8_PCREL
;
7854 code
= BFD_RELOC_16_PCREL
;
7857 code
= BFD_RELOC_32_PCREL
;
7860 code
= BFD_RELOC_64_PCREL
;
7862 case BFD_RELOC_8_PCREL
:
7863 case BFD_RELOC_16_PCREL
:
7864 case BFD_RELOC_32_PCREL
:
7865 case BFD_RELOC_64_PCREL
:
7866 case BFD_RELOC_16_PCREL_S2
:
7867 case BFD_RELOC_PCREL_HI16_S
:
7868 case BFD_RELOC_PCREL_LO16
:
7871 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
7872 "Cannot make %s relocation PC relative",
7873 bfd_get_reloc_code_name (code
));
7877 /* To support a PC relative reloc when generating embedded PIC code
7878 for ECOFF, we use a Cygnus extension. We check for that here to
7879 make sure that we don't let such a reloc escape normally. */
7880 if (OUTPUT_FLAVOR
== bfd_target_ecoff_flavour
7881 && code
== BFD_RELOC_16_PCREL_S2
7882 && mips_pic
!= EMBEDDED_PIC
)
7883 reloc
->howto
= NULL
;
7885 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
7887 if (reloc
->howto
== NULL
)
7889 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
7890 "Can not represent %s relocation in this object file format",
7891 bfd_get_reloc_code_name (code
));
7898 /* Convert a machine dependent frag. */
7901 md_convert_frag (abfd
, asec
, fragp
)
7909 if (fragp
->fr_opcode
== NULL
)
7912 old
= RELAX_OLD (fragp
->fr_subtype
);
7913 new = RELAX_NEW (fragp
->fr_subtype
);
7914 fixptr
= fragp
->fr_literal
+ fragp
->fr_fix
;
7917 memcpy (fixptr
- old
, fixptr
, new);
7919 fragp
->fr_fix
+= new - old
;
7922 /* This function is called whenever a label is defined. It is used
7923 when handling branch delays; if a branch has a label, we assume we
7927 mips_define_label (sym
)
7933 /* Decide whether a label is local. This is called by LOCAL_LABEL.
7934 In order to work with gcc when using mips-tfile, we must keep all
7935 local labels. However, in other cases, we want to discard them,
7936 since they are useless. */
7939 mips_local_label (name
)
7942 #ifndef NO_ECOFF_DEBUGGING
7945 && ! ecoff_debugging_seen
)
7947 /* We were called with -g, but we didn't see any debugging
7948 information. That may mean that gcc is smuggling debugging
7949 information through to mips-tfile, in which case we must
7950 generate all local labels. */
7955 /* Here it's OK to discard local labels. */
7957 return name
[0] == '$';
7960 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7962 /* Some special processing for a MIPS ELF file. */
7965 mips_elf_final_processing ()
7967 /* Write out the register information. */
7972 s
.ri_gprmask
= mips_gprmask
;
7973 s
.ri_cprmask
[0] = mips_cprmask
[0];
7974 s
.ri_cprmask
[1] = mips_cprmask
[1];
7975 s
.ri_cprmask
[2] = mips_cprmask
[2];
7976 s
.ri_cprmask
[3] = mips_cprmask
[3];
7977 /* The gp_value field is set by the MIPS ELF backend. */
7979 bfd_mips_elf32_swap_reginfo_out (stdoutput
, &s
,
7980 ((Elf32_External_RegInfo
*)
7981 mips_regmask_frag
));
7985 Elf64_Internal_RegInfo s
;
7987 s
.ri_gprmask
= mips_gprmask
;
7989 s
.ri_cprmask
[0] = mips_cprmask
[0];
7990 s
.ri_cprmask
[1] = mips_cprmask
[1];
7991 s
.ri_cprmask
[2] = mips_cprmask
[2];
7992 s
.ri_cprmask
[3] = mips_cprmask
[3];
7993 /* The gp_value field is set by the MIPS ELF backend. */
7995 bfd_mips_elf64_swap_reginfo_out (stdoutput
, &s
,
7996 ((Elf64_External_RegInfo
*)
7997 mips_regmask_frag
));
8000 /* Set the MIPS ELF flag bits. FIXME: There should probably be some
8001 sort of BFD interface for this. */
8002 if (mips_any_noreorder
)
8003 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_NOREORDER
;
8004 if (mips_pic
!= NO_PIC
)
8005 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_PIC
;
8008 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */
8010 /* These functions should really be defined by the object file format,
8011 since they are related to debugging information. However, this
8012 code has to work for the a.out format, which does not define them,
8013 so we provide simple versions here. These don't actually generate
8014 any debugging information, but they do simple checking and someday
8015 somebody may make them useful. */
8019 struct loc
*loc_next
;
8020 unsigned long loc_fileno
;
8021 unsigned long loc_lineno
;
8022 unsigned long loc_offset
;
8023 unsigned short loc_delta
;
8024 unsigned short loc_count
;
8033 struct proc
*proc_next
;
8034 struct symbol
*proc_isym
;
8035 struct symbol
*proc_end
;
8036 unsigned long proc_reg_mask
;
8037 unsigned long proc_reg_offset
;
8038 unsigned long proc_fpreg_mask
;
8039 unsigned long proc_fpreg_offset
;
8040 unsigned long proc_frameoffset
;
8041 unsigned long proc_framereg
;
8042 unsigned long proc_pcreg
;
8044 struct file
*proc_file
;
8051 struct file
*file_next
;
8052 unsigned long file_fileno
;
8053 struct symbol
*file_symbol
;
8054 struct symbol
*file_end
;
8055 struct proc
*file_proc
;
8060 static struct obstack proc_frags
;
8061 static procS
*proc_lastP
;
8062 static procS
*proc_rootP
;
8063 static int numprocs
;
8068 obstack_begin (&proc_frags
, 0x2000);
8074 /* check for premature end, nesting errors, etc */
8075 if (proc_lastP
&& proc_lastP
->proc_end
== NULL
)
8076 as_warn ("missing `.end' at end of assembly");
8085 if (*input_line_pointer
== '-')
8087 ++input_line_pointer
;
8090 if (!isdigit (*input_line_pointer
))
8091 as_bad ("Expected simple number.");
8092 if (input_line_pointer
[0] == '0')
8094 if (input_line_pointer
[1] == 'x')
8096 input_line_pointer
+= 2;
8097 while (isxdigit (*input_line_pointer
))
8100 val
|= hex_value (*input_line_pointer
++);
8102 return negative
? -val
: val
;
8106 ++input_line_pointer
;
8107 while (isdigit (*input_line_pointer
))
8110 val
|= *input_line_pointer
++ - '0';
8112 return negative
? -val
: val
;
8115 if (!isdigit (*input_line_pointer
))
8117 printf (" *input_line_pointer == '%c' 0x%02x\n",
8118 *input_line_pointer
, *input_line_pointer
);
8119 as_warn ("Invalid number");
8122 while (isdigit (*input_line_pointer
))
8125 val
+= *input_line_pointer
++ - '0';
8127 return negative
? -val
: val
;
8130 /* The .file directive; just like the usual .file directive, but there
8131 is an initial number which is the ECOFF file index. */
8139 line
= get_number ();
8144 /* The .end directive. */
8152 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
8155 demand_empty_rest_of_line ();
8159 if (now_seg
!= text_section
)
8160 as_warn (".end not in text section");
8163 as_warn (".end and no .ent seen yet.");
8169 assert (S_GET_NAME (p
));
8170 if (strcmp (S_GET_NAME (p
), S_GET_NAME (proc_lastP
->proc_isym
)))
8171 as_warn (".end symbol does not match .ent symbol.");
8174 proc_lastP
->proc_end
= (symbolS
*) 1;
8177 /* The .aent and .ent directives. */
8187 symbolP
= get_symbol ();
8188 if (*input_line_pointer
== ',')
8189 input_line_pointer
++;
8191 if (isdigit (*input_line_pointer
) || *input_line_pointer
== '-')
8192 number
= get_number ();
8193 if (now_seg
!= text_section
)
8194 as_warn (".ent or .aent not in text section.");
8196 if (!aent
&& proc_lastP
&& proc_lastP
->proc_end
== NULL
)
8197 as_warn ("missing `.end'");
8201 procP
= (procS
*) obstack_alloc (&proc_frags
, sizeof (*procP
));
8202 procP
->proc_isym
= symbolP
;
8203 procP
->proc_reg_mask
= 0;
8204 procP
->proc_reg_offset
= 0;
8205 procP
->proc_fpreg_mask
= 0;
8206 procP
->proc_fpreg_offset
= 0;
8207 procP
->proc_frameoffset
= 0;
8208 procP
->proc_framereg
= 0;
8209 procP
->proc_pcreg
= 0;
8210 procP
->proc_end
= NULL
;
8211 procP
->proc_next
= NULL
;
8213 proc_lastP
->proc_next
= procP
;
8219 demand_empty_rest_of_line ();
8222 /* The .frame directive. */
8235 frame_reg
= tc_get_register (1);
8236 if (*input_line_pointer
== ',')
8237 input_line_pointer
++;
8238 frame_off
= get_absolute_expression ();
8239 if (*input_line_pointer
== ',')
8240 input_line_pointer
++;
8241 pcreg
= tc_get_register (0);
8244 assert (proc_rootP
);
8245 proc_rootP
->proc_framereg
= frame_reg
;
8246 proc_rootP
->proc_frameoffset
= frame_off
;
8247 proc_rootP
->proc_pcreg
= pcreg
;
8248 /* bob macho .frame */
8250 /* We don't have to write out a frame stab for unoptimized code. */
8251 if (!(frame_reg
== FP
&& frame_off
== 0))
8254 as_warn ("No .ent for .frame to use.");
8255 (void) sprintf (str
, "R%d;%d", frame_reg
, frame_off
);
8256 symP
= symbol_new (str
, N_VFP
, 0, frag_now
);
8257 S_SET_TYPE (symP
, N_RMASK
);
8258 S_SET_OTHER (symP
, 0);
8259 S_SET_DESC (symP
, 0);
8260 symP
->sy_forward
= proc_lastP
->proc_isym
;
8261 /* bob perhaps I should have used pseudo set */
8263 demand_empty_rest_of_line ();
8267 /* The .fmask and .mask directives. */
8274 char str
[100], *strP
;
8280 mask
= get_number ();
8281 if (*input_line_pointer
== ',')
8282 input_line_pointer
++;
8283 off
= get_absolute_expression ();
8285 /* bob only for coff */
8286 assert (proc_rootP
);
8287 if (reg_type
== 'F')
8289 proc_rootP
->proc_fpreg_mask
= mask
;
8290 proc_rootP
->proc_fpreg_offset
= off
;
8294 proc_rootP
->proc_reg_mask
= mask
;
8295 proc_rootP
->proc_reg_offset
= off
;
8298 /* bob macho .mask + .fmask */
8300 /* We don't have to write out a mask stab if no saved regs. */
8304 as_warn ("No .ent for .mask to use.");
8306 for (i
= 0; i
< 32; i
++)
8310 sprintf (strP
, "%c%d,", reg_type
, i
);
8311 strP
+= strlen (strP
);
8315 sprintf (strP
, ";%d,", off
);
8316 symP
= symbol_new (str
, N_RMASK
, 0, frag_now
);
8317 S_SET_TYPE (symP
, N_RMASK
);
8318 S_SET_OTHER (symP
, 0);
8319 S_SET_DESC (symP
, 0);
8320 symP
->sy_forward
= proc_lastP
->proc_isym
;
8321 /* bob perhaps I should have used pseudo set */
8326 /* The .loc directive. */
8337 assert (now_seg
== text_section
);
8339 lineno
= get_number ();
8340 addroff
= frag_now_fix ();
8342 symbolP
= symbol_new ("", N_SLINE
, addroff
, frag_now
);
8343 S_SET_TYPE (symbolP
, N_SLINE
);
8344 S_SET_OTHER (symbolP
, 0);
8345 S_SET_DESC (symbolP
, lineno
);
8346 symbolP
->sy_segment
= now_seg
;