1 /* tc-mips.c -- assemble code for a MIPS chip.
2 Copyright (C) 1993, 1994, 1995, 1996, 1997 Free Software Foundation, Inc.
3 Contributed by the OSF and Ralph Campbell.
4 Written by Keith Knowles and Ralph Campbell, working independently.
5 Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus
8 This file is part of GAS.
10 GAS is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 2, or (at your option)
15 GAS is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with GAS; see the file COPYING. If not, write to the Free
22 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
38 #include "opcode/mips.h"
41 /* Clean up namespace so we can include obj-elf.h too. */
42 static int mips_output_flavor () { return OUTPUT_FLAVOR
; }
43 #undef OBJ_PROCESS_STAB
49 #undef TARGET_SYMBOL_FIELDS
51 #undef obj_frob_file_after_relocs
52 #undef obj_frob_symbol
54 #undef obj_sec_sym_ok_for_reloc
57 /* Fix any of them that we actually care about. */
59 #define OUTPUT_FLAVOR mips_output_flavor()
66 #ifndef ECOFF_DEBUGGING
67 #define NO_ECOFF_DEBUGGING
68 #define ECOFF_DEBUGGING 0
73 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
74 static char *mips_regmask_frag
;
79 #define PIC_CALL_REG 25
87 #define ILLEGAL_REG (32)
89 extern int target_big_endian
;
91 /* 1 is we should use the 64 bit MIPS ELF ABI, 0 if we should use the
92 32 bit ABI. This has no meaning for ECOFF. */
95 /* The default target format to use. */
99 switch (OUTPUT_FLAVOR
)
101 case bfd_target_aout_flavour
:
102 return target_big_endian
? "a.out-mips-big" : "a.out-mips-little";
103 case bfd_target_ecoff_flavour
:
104 return target_big_endian
? "ecoff-bigmips" : "ecoff-littlemips";
105 case bfd_target_elf_flavour
:
106 return (target_big_endian
107 ? (mips_64
? "elf64-bigmips" : "elf32-bigmips")
108 : (mips_64
? "elf64-littlemips" : "elf32-littlemips"));
114 /* The name of the readonly data section. */
115 #define RDATA_SECTION_NAME (OUTPUT_FLAVOR == bfd_target_aout_flavour \
117 : OUTPUT_FLAVOR == bfd_target_ecoff_flavour \
119 : OUTPUT_FLAVOR == bfd_target_elf_flavour \
123 /* These variables are filled in with the masks of registers used.
124 The object format code reads them and puts them in the appropriate
126 unsigned long mips_gprmask
;
127 unsigned long mips_cprmask
[4];
129 /* MIPS ISA (Instruction Set Architecture) level (may be changed
130 temporarily using .set mipsN). */
131 static int mips_isa
= -1;
133 /* MIPS ISA we are using for this output file. */
134 static int file_mips_isa
;
136 /* Whether we are assembling for the mips16 processor. */
137 static int mips16
= -1;
139 /* The CPU type as a number: 2000, 3000, 4000, 4400, etc. */
140 static int mips_cpu
= -1;
142 /* Whether the 4650 instructions (mad/madu) are permitted. */
143 static int mips_4650
= -1;
145 /* Whether the 4010 instructions are permitted. */
146 static int mips_4010
= -1;
148 /* Whether the 4100 MADD16 and DMADD16 are permitted. */
149 static int mips_4100
= -1;
151 /* Whether the processor uses hardware interlocks, and thus does not
152 require nops to be inserted. */
153 static int interlocks
= -1;
155 /* As with "interlocks" this is used by hardware that has FP
156 (co-processor) interlocks. */
157 static int cop_interlocks
= -1;
159 /* MIPS PIC level. */
163 /* Do not generate PIC code. */
166 /* Generate PIC code as in Irix 4. This is not implemented, and I'm
167 not sure what it is supposed to do. */
170 /* Generate PIC code as in the SVR4 MIPS ABI. */
173 /* Generate PIC code without using a global offset table: the data
174 segment has a maximum size of 64K, all data references are off
175 the $gp register, and all text references are PC relative. This
176 is used on some embedded systems. */
180 static enum mips_pic_level mips_pic
;
182 /* 1 if we should generate 32 bit offsets from the GP register in
183 SVR4_PIC mode. Currently has no meaning in other modes. */
184 static int mips_big_got
;
186 /* 1 if trap instructions should used for overflow rather than break
188 static int mips_trap
;
190 /* 1 if we should autoextend mips16 instructions. */
191 static int mips16_autoextend
= 1;
193 static int mips_warn_about_macros
;
194 static int mips_noreorder
;
195 static int mips_any_noreorder
;
196 static int mips_nomove
;
197 static int mips_noat
;
198 static int mips_nobopt
;
200 /* The size of the small data section. */
201 static int g_switch_value
= 8;
202 /* Whether the -G option was used. */
203 static int g_switch_seen
= 0;
208 /* If we can determine in advance that GP optimization won't be
209 possible, we can skip the relaxation stuff that tries to produce
210 GP-relative references. This makes delay slot optimization work
213 This function can only provide a guess, but it seems to work for
214 gcc output. If it guesses wrong, the only loss should be in
215 efficiency; it shouldn't introduce any bugs.
217 I don't know if a fix is needed for the SVR4_PIC mode. I've only
218 fixed it for the non-PIC mode. KR 95/04/07 */
219 static int nopic_need_relax
PARAMS ((symbolS
*));
221 /* handle of the OPCODE hash table */
222 static struct hash_control
*op_hash
= NULL
;
224 /* The opcode hash table we use for the mips16. */
225 static struct hash_control
*mips16_op_hash
= NULL
;
227 /* This array holds the chars that always start a comment. If the
228 pre-processor is disabled, these aren't very useful */
229 const char comment_chars
[] = "#";
231 /* This array holds the chars that only start a comment at the beginning of
232 a line. If the line seems to have the form '# 123 filename'
233 .line and .file directives will appear in the pre-processed output */
234 /* Note that input_file.c hand checks for '#' at the beginning of the
235 first line of the input file. This is because the compiler outputs
236 #NO_APP at the beginning of its output. */
237 /* Also note that C style comments are always supported. */
238 const char line_comment_chars
[] = "#";
240 /* This array holds machine specific line separator characters. */
241 const char line_separator_chars
[] = "";
243 /* Chars that can be used to separate mant from exp in floating point nums */
244 const char EXP_CHARS
[] = "eE";
246 /* Chars that mean this number is a floating point constant */
249 const char FLT_CHARS
[] = "rRsSfFdDxXpP";
251 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
252 changed in read.c . Ideally it shouldn't have to know about it at all,
253 but nothing is ideal around here.
256 static char *insn_error
;
258 static int auto_align
= 1;
260 /* When outputting SVR4 PIC code, the assembler needs to know the
261 offset in the stack frame from which to restore the $gp register.
262 This is set by the .cprestore pseudo-op, and saved in this
264 static offsetT mips_cprestore_offset
= -1;
266 /* This is the register which holds the stack frame, as set by the
267 .frame pseudo-op. This is needed to implement .cprestore. */
268 static int mips_frame_reg
= SP
;
270 /* To output NOP instructions correctly, we need to keep information
271 about the previous two instructions. */
273 /* Whether we are optimizing. The default value of 2 means to remove
274 unneeded NOPs and swap branch instructions when possible. A value
275 of 1 means to not swap branches. A value of 0 means to always
277 static int mips_optimize
= 2;
279 /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is
280 equivalent to seeing no -g option at all. */
281 static int mips_debug
= 0;
283 /* The previous instruction. */
284 static struct mips_cl_insn prev_insn
;
286 /* The instruction before prev_insn. */
287 static struct mips_cl_insn prev_prev_insn
;
289 /* If we don't want information for prev_insn or prev_prev_insn, we
290 point the insn_mo field at this dummy integer. */
291 static const struct mips_opcode dummy_opcode
= { 0 };
293 /* Non-zero if prev_insn is valid. */
294 static int prev_insn_valid
;
296 /* The frag for the previous instruction. */
297 static struct frag
*prev_insn_frag
;
299 /* The offset into prev_insn_frag for the previous instruction. */
300 static long prev_insn_where
;
302 /* The reloc type for the previous instruction, if any. */
303 static bfd_reloc_code_real_type prev_insn_reloc_type
;
305 /* The reloc for the previous instruction, if any. */
306 static fixS
*prev_insn_fixp
;
308 /* Non-zero if the previous instruction was in a delay slot. */
309 static int prev_insn_is_delay_slot
;
311 /* Non-zero if the previous instruction was in a .set noreorder. */
312 static int prev_insn_unreordered
;
314 /* Non-zero if the previous instruction uses an extend opcode (if
316 static int prev_insn_extended
;
318 /* Non-zero if the previous previous instruction was in a .set
320 static int prev_prev_insn_unreordered
;
322 /* For ECOFF and ELF, relocations against symbols are done in two
323 parts, with a HI relocation and a LO relocation. Each relocation
324 has only 16 bits of space to store an addend. This means that in
325 order for the linker to handle carries correctly, it must be able
326 to locate both the HI and the LO relocation. This means that the
327 relocations must appear in order in the relocation table.
329 In order to implement this, we keep track of each unmatched HI
330 relocation. We then sort them so that they immediately precede the
331 corresponding LO relocation. */
336 struct mips_hi_fixup
*next
;
339 /* The section this fixup is in. */
343 /* The list of unmatched HI relocs. */
345 static struct mips_hi_fixup
*mips_hi_fixup_list
;
347 /* Map normal MIPS register numbers to mips16 register numbers. */
349 #define X ILLEGAL_REG
350 static const int mips32_to_16_reg_map
[] =
352 X
, X
, 2, 3, 4, 5, 6, 7,
353 X
, X
, X
, X
, X
, X
, X
, X
,
354 0, 1, X
, X
, X
, X
, X
, X
,
355 X
, X
, X
, X
, X
, X
, X
, X
359 /* Map mips16 register numbers to normal MIPS register numbers. */
361 static const int mips16_to_32_reg_map
[] =
363 16, 17, 2, 3, 4, 5, 6, 7
366 /* Since the MIPS does not have multiple forms of PC relative
367 instructions, we do not have to do relaxing as is done on other
368 platforms. However, we do have to handle GP relative addressing
369 correctly, which turns out to be a similar problem.
371 Every macro that refers to a symbol can occur in (at least) two
372 forms, one with GP relative addressing and one without. For
373 example, loading a global variable into a register generally uses
374 a macro instruction like this:
376 If i can be addressed off the GP register (this is true if it is in
377 the .sbss or .sdata section, or if it is known to be smaller than
378 the -G argument) this will generate the following instruction:
380 This instruction will use a GPREL reloc. If i can not be addressed
381 off the GP register, the following instruction sequence will be used:
384 In this case the first instruction will have a HI16 reloc, and the
385 second reloc will have a LO16 reloc. Both relocs will be against
388 The issue here is that we may not know whether i is GP addressable
389 until after we see the instruction that uses it. Therefore, we
390 want to be able to choose the final instruction sequence only at
391 the end of the assembly. This is similar to the way other
392 platforms choose the size of a PC relative instruction only at the
395 When generating position independent code we do not use GP
396 addressing in quite the same way, but the issue still arises as
397 external symbols and local symbols must be handled differently.
399 We handle these issues by actually generating both possible
400 instruction sequences. The longer one is put in a frag_var with
401 type rs_machine_dependent. We encode what to do with the frag in
402 the subtype field. We encode (1) the number of existing bytes to
403 replace, (2) the number of new bytes to use, (3) the offset from
404 the start of the existing bytes to the first reloc we must generate
405 (that is, the offset is applied from the start of the existing
406 bytes after they are replaced by the new bytes, if any), (4) the
407 offset from the start of the existing bytes to the second reloc,
408 (5) whether a third reloc is needed (the third reloc is always four
409 bytes after the second reloc), and (6) whether to warn if this
410 variant is used (this is sometimes needed if .set nomacro or .set
411 noat is in effect). All these numbers are reasonably small.
413 Generating two instruction sequences must be handled carefully to
414 ensure that delay slots are handled correctly. Fortunately, there
415 are a limited number of cases. When the second instruction
416 sequence is generated, append_insn is directed to maintain the
417 existing delay slot information, so it continues to apply to any
418 code after the second instruction sequence. This means that the
419 second instruction sequence must not impose any requirements not
420 required by the first instruction sequence.
422 These variant frags are then handled in functions called by the
423 machine independent code. md_estimate_size_before_relax returns
424 the final size of the frag. md_convert_frag sets up the final form
425 of the frag. tc_gen_reloc adjust the first reloc and adds a second
427 #define RELAX_ENCODE(old, new, reloc1, reloc2, reloc3, warn) \
431 | (((reloc1) + 64) << 9) \
432 | (((reloc2) + 64) << 2) \
433 | ((reloc3) ? (1 << 1) : 0) \
435 #define RELAX_OLD(i) (((i) >> 23) & 0x7f)
436 #define RELAX_NEW(i) (((i) >> 16) & 0x7f)
437 #define RELAX_RELOC1(i) ((bfd_vma)(((i) >> 9) & 0x7f) - 64)
438 #define RELAX_RELOC2(i) ((bfd_vma)(((i) >> 2) & 0x7f) - 64)
439 #define RELAX_RELOC3(i) (((i) >> 1) & 1)
440 #define RELAX_WARN(i) ((i) & 1)
442 /* For mips16 code, we use an entirely different form of relaxation.
443 mips16 supports two versions of most instructions which take
444 immediate values: a small one which takes some small value, and a
445 larger one which takes a 16 bit value. Since branches also follow
446 this pattern, relaxing these values is required.
448 We can assemble both mips16 and normal MIPS code in a single
449 object. Therefore, we need to support this type of relaxation at
450 the same time that we support the relaxation described above. We
451 use the high bit of the subtype field to distinguish these cases.
453 The information we store for this type of relaxation is the
454 argument code found in the opcode file for this relocation, whether
455 the user explicitly requested a small or extended form, and whether
456 the relocation is in a jump or jal delay slot. That tells us the
457 size of the value, and how it should be stored. We also store
458 whether the fragment is considered to be extended or not. We also
459 store whether this is known to be a branch to a different section,
460 whether we have tried to relax this frag yet, and whether we have
461 ever extended a PC relative fragment because of a shift count. */
462 #define RELAX_MIPS16_ENCODE(type, small, ext, dslot, jal_dslot) \
465 | ((small) ? 0x100 : 0) \
466 | ((ext) ? 0x200 : 0) \
467 | ((dslot) ? 0x400 : 0) \
468 | ((jal_dslot) ? 0x800 : 0))
469 #define RELAX_MIPS16_P(i) (((i) & 0x80000000) != 0)
470 #define RELAX_MIPS16_TYPE(i) ((i) & 0xff)
471 #define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x100) != 0)
472 #define RELAX_MIPS16_USER_EXT(i) (((i) & 0x200) != 0)
473 #define RELAX_MIPS16_DSLOT(i) (((i) & 0x400) != 0)
474 #define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x800) != 0)
475 #define RELAX_MIPS16_EXTENDED(i) (((i) & 0x1000) != 0)
476 #define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x1000)
477 #define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) &~ 0x1000)
478 #define RELAX_MIPS16_LONG_BRANCH(i) (((i) & 0x2000) != 0)
479 #define RELAX_MIPS16_MARK_LONG_BRANCH(i) ((i) | 0x2000)
480 #define RELAX_MIPS16_CLEAR_LONG_BRANCH(i) ((i) &~ 0x2000)
482 /* Prototypes for static functions. */
485 #define internalError() \
486 as_fatal ("internal Error, line %d, %s", __LINE__, __FILE__)
488 #define internalError() as_fatal ("MIPS internal Error");
491 enum mips_regclass
{ MIPS_GR_REG
, MIPS_FP_REG
, MIPS16_REG
};
493 static int insn_uses_reg
PARAMS ((struct mips_cl_insn
*ip
,
494 unsigned int reg
, enum mips_regclass
class));
495 static int reg_needs_delay
PARAMS ((int));
496 static void append_insn
PARAMS ((char *place
,
497 struct mips_cl_insn
* ip
,
499 bfd_reloc_code_real_type r
,
501 static void mips_no_prev_insn
PARAMS ((void));
502 static void mips_emit_delays
PARAMS ((boolean
));
504 static void macro_build
PARAMS ((char *place
, int *counter
, expressionS
* ep
,
505 const char *name
, const char *fmt
,
508 static void macro_build ();
510 static void mips16_macro_build
PARAMS ((char *, int *, expressionS
*,
511 const char *, const char *,
513 static void macro_build_lui
PARAMS ((char *place
, int *counter
,
514 expressionS
* ep
, int regnum
));
515 static void set_at
PARAMS ((int *counter
, int reg
, int unsignedp
));
516 static void check_absolute_expr
PARAMS ((struct mips_cl_insn
* ip
,
518 static void load_register
PARAMS ((int *, int, expressionS
*, int));
519 static void load_address
PARAMS ((int *counter
, int reg
, expressionS
*ep
));
520 static void macro
PARAMS ((struct mips_cl_insn
* ip
));
521 static void mips16_macro
PARAMS ((struct mips_cl_insn
* ip
));
522 #ifdef LOSING_COMPILER
523 static void macro2
PARAMS ((struct mips_cl_insn
* ip
));
525 static void mips_ip
PARAMS ((char *str
, struct mips_cl_insn
* ip
));
526 static void mips16_ip
PARAMS ((char *str
, struct mips_cl_insn
* ip
));
527 static void mips16_immed
PARAMS ((char *, unsigned int, int, offsetT
, boolean
,
528 boolean
, boolean
, unsigned long *,
529 boolean
*, unsigned short *));
530 static int my_getSmallExpression
PARAMS ((expressionS
* ep
, char *str
));
531 static void my_getExpression
PARAMS ((expressionS
* ep
, char *str
));
532 static symbolS
*get_symbol
PARAMS ((void));
533 static void mips_align
PARAMS ((int to
, int fill
, symbolS
*label
));
534 static void s_align
PARAMS ((int));
535 static void s_change_sec
PARAMS ((int));
536 static void s_cons
PARAMS ((int));
537 static void s_float_cons
PARAMS ((int));
538 static void s_mips_globl
PARAMS ((int));
539 static void s_option
PARAMS ((int));
540 static void s_mipsset
PARAMS ((int));
541 static void s_abicalls
PARAMS ((int));
542 static void s_cpload
PARAMS ((int));
543 static void s_cprestore
PARAMS ((int));
544 static void s_gpword
PARAMS ((int));
545 static void s_cpadd
PARAMS ((int));
546 static void md_obj_begin
PARAMS ((void));
547 static void md_obj_end
PARAMS ((void));
548 static long get_number
PARAMS ((void));
549 static void s_ent
PARAMS ((int));
550 static void s_mipsend
PARAMS ((int));
551 static void s_file
PARAMS ((int));
552 static int mips16_extended_frag
PARAMS ((fragS
*, asection
*, long));
556 The following pseudo-ops from the Kane and Heinrich MIPS book
557 should be defined here, but are currently unsupported: .alias,
558 .galive, .gjaldef, .gjrlive, .livereg, .noalias.
560 The following pseudo-ops from the Kane and Heinrich MIPS book are
561 specific to the type of debugging information being generated, and
562 should be defined by the object format: .aent, .begin, .bend,
563 .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp,
566 The following pseudo-ops from the Kane and Heinrich MIPS book are
567 not MIPS CPU specific, but are also not specific to the object file
568 format. This file is probably the best place to define them, but
569 they are not currently supported: .asm0, .endr, .lab, .repeat,
570 .struct, .weakext. */
572 static const pseudo_typeS mips_pseudo_table
[] =
574 /* MIPS specific pseudo-ops. */
575 {"option", s_option
, 0},
576 {"set", s_mipsset
, 0},
577 {"rdata", s_change_sec
, 'r'},
578 {"sdata", s_change_sec
, 's'},
579 {"livereg", s_ignore
, 0},
580 {"abicalls", s_abicalls
, 0},
581 {"cpload", s_cpload
, 0},
582 {"cprestore", s_cprestore
, 0},
583 {"gpword", s_gpword
, 0},
584 {"cpadd", s_cpadd
, 0},
586 /* Relatively generic pseudo-ops that happen to be used on MIPS
588 {"asciiz", stringer
, 1},
589 {"bss", s_change_sec
, 'b'},
592 {"dword", s_cons
, 3},
594 /* These pseudo-ops are defined in read.c, but must be overridden
595 here for one reason or another. */
596 {"align", s_align
, 0},
598 {"data", s_change_sec
, 'd'},
599 {"double", s_float_cons
, 'd'},
600 {"float", s_float_cons
, 'f'},
601 {"globl", s_mips_globl
, 0},
602 {"global", s_mips_globl
, 0},
603 {"hword", s_cons
, 1},
608 {"short", s_cons
, 1},
609 {"single", s_float_cons
, 'f'},
610 {"text", s_change_sec
, 't'},
615 static const pseudo_typeS mips_nonecoff_pseudo_table
[] = {
616 /* These pseudo-ops should be defined by the object file format.
617 However, a.out doesn't support them, so we have versions here. */
619 {"bgnb", s_ignore
, 0},
620 {"end", s_mipsend
, 0},
621 {"endb", s_ignore
, 0},
624 {"fmask", s_ignore
, 'F'},
625 {"frame", s_ignore
, 0},
626 {"loc", s_ignore
, 0},
627 {"mask", s_ignore
, 'R'},
628 {"verstamp", s_ignore
, 0},
632 extern void pop_insert
PARAMS ((const pseudo_typeS
*));
637 pop_insert (mips_pseudo_table
);
638 if (! ECOFF_DEBUGGING
)
639 pop_insert (mips_nonecoff_pseudo_table
);
642 /* Symbols labelling the current insn. */
644 struct insn_label_list
646 struct insn_label_list
*next
;
650 static struct insn_label_list
*insn_labels
;
651 static struct insn_label_list
*free_insn_labels
;
653 static void mips_clear_insn_labels
PARAMS ((void));
656 mips_clear_insn_labels ()
658 register struct insn_label_list
**pl
;
660 for (pl
= &free_insn_labels
; *pl
!= NULL
; pl
= &(*pl
)->next
)
666 static char *expr_end
;
668 /* Expressions which appear in instructions. These are set by
671 static expressionS imm_expr
;
672 static expressionS offset_expr
;
674 /* Relocs associated with imm_expr and offset_expr. */
676 static bfd_reloc_code_real_type imm_reloc
;
677 static bfd_reloc_code_real_type offset_reloc
;
679 /* This is set by mips_ip if imm_reloc is an unmatched HI16_S reloc. */
681 static boolean imm_unmatched_hi
;
683 /* These are set by mips16_ip if an explicit extension is used. */
685 static boolean mips16_small
, mips16_ext
;
688 * This function is called once, at assembler startup time. It should
689 * set up all the tables, etc. that the MD part of the assembler will need.
695 register const char *retval
= NULL
;
696 register unsigned int i
= 0;
704 if (strcmp (cpu
+ (sizeof TARGET_CPU
) - 3, "el") == 0)
706 a
= xmalloc (sizeof TARGET_CPU
);
707 strcpy (a
, TARGET_CPU
);
708 a
[(sizeof TARGET_CPU
) - 3] = '\0';
712 if (strcmp (cpu
, "mips") == 0)
718 else if (strcmp (cpu
, "r6000") == 0
719 || strcmp (cpu
, "mips2") == 0)
725 else if (strcmp (cpu
, "mips64") == 0
726 || strcmp (cpu
, "r4000") == 0
727 || strcmp (cpu
, "mips3") == 0)
733 else if (strcmp (cpu
, "r4400") == 0)
739 else if (strcmp (cpu
, "mips64orion") == 0
740 || strcmp (cpu
, "r4600") == 0)
746 else if (strcmp (cpu
, "r4650") == 0)
754 else if (strcmp (cpu
, "mips64vr4300") == 0)
760 else if (strcmp (cpu
, "mips64vr4100") == 0)
768 else if (strcmp (cpu
, "r4010") == 0)
776 else if (strcmp (cpu
, "r5000") == 0
777 || strcmp (cpu
, "mips64vr5000") == 0)
783 else if (strcmp (cpu
, "r8000") == 0
784 || strcmp (cpu
, "mips4") == 0)
790 else if (strcmp (cpu
, "r10000") == 0)
796 else if (strcmp (cpu
, "mips16") == 0)
800 mips_cpu
= 0; /* FIXME */
815 if (strncmp (TARGET_CPU
, "mips16", sizeof "mips16" - 1) == 0)
830 if (mips_4010
|| mips_4100
|| mips_cpu
== 4300)
835 if (mips_cpu
== 4300)
840 if (mips_isa
< 2 && mips_trap
)
841 as_bad ("trap exception not supported at ISA 1");
846 ok
= bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, 3000);
849 ok
= bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, 6000);
852 ok
= bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, 4000);
855 ok
= bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, 8000);
859 as_warn ("Could not set architecture and machine");
861 file_mips_isa
= mips_isa
;
863 op_hash
= hash_new ();
865 for (i
= 0; i
< NUMOPCODES
;)
867 const char *name
= mips_opcodes
[i
].name
;
869 retval
= hash_insert (op_hash
, name
, (PTR
) &mips_opcodes
[i
]);
872 fprintf (stderr
, "internal error: can't hash `%s': %s\n",
873 mips_opcodes
[i
].name
, retval
);
874 as_fatal ("Broken assembler. No assembly attempted.");
878 if (mips_opcodes
[i
].pinfo
!= INSN_MACRO
879 && ((mips_opcodes
[i
].match
& mips_opcodes
[i
].mask
)
880 != mips_opcodes
[i
].match
))
882 fprintf (stderr
, "internal error: bad opcode: `%s' \"%s\"\n",
883 mips_opcodes
[i
].name
, mips_opcodes
[i
].args
);
884 as_fatal ("Broken assembler. No assembly attempted.");
888 while ((i
< NUMOPCODES
) && !strcmp (mips_opcodes
[i
].name
, name
));
891 mips16_op_hash
= hash_new ();
894 while (i
< bfd_mips16_num_opcodes
)
896 const char *name
= mips16_opcodes
[i
].name
;
898 retval
= hash_insert (mips16_op_hash
, name
, (PTR
) &mips16_opcodes
[i
]);
900 as_fatal ("internal error: can't hash `%s': %s\n",
901 mips16_opcodes
[i
].name
, retval
);
904 if (mips16_opcodes
[i
].pinfo
!= INSN_MACRO
905 && ((mips16_opcodes
[i
].match
& mips16_opcodes
[i
].mask
)
906 != mips16_opcodes
[i
].match
))
907 as_fatal ("internal error: bad opcode: `%s' \"%s\"\n",
908 mips16_opcodes
[i
].name
, mips16_opcodes
[i
].args
);
911 while (i
< bfd_mips16_num_opcodes
912 && strcmp (mips16_opcodes
[i
].name
, name
) == 0);
915 mips_no_prev_insn ();
923 /* set the default alignment for the text section (2**2) */
924 record_alignment (text_section
, 2);
926 if (USE_GLOBAL_POINTER_OPT
)
927 bfd_set_gp_size (stdoutput
, g_switch_value
);
929 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
931 /* On a native system, sections must be aligned to 16 byte
932 boundaries. When configured for an embedded ELF target, we
934 if (strcmp (TARGET_OS
, "elf") != 0)
936 (void) bfd_set_section_alignment (stdoutput
, text_section
, 4);
937 (void) bfd_set_section_alignment (stdoutput
, data_section
, 4);
938 (void) bfd_set_section_alignment (stdoutput
, bss_section
, 4);
941 /* Create a .reginfo section for register masks and a .mdebug
942 section for debugging information. */
953 sec
= subseg_new (".reginfo", (subsegT
) 0);
955 /* The ABI says this section should be loaded so that the
956 running program can access it. */
957 (void) bfd_set_section_flags (stdoutput
, sec
,
958 (SEC_ALLOC
| SEC_LOAD
959 | SEC_READONLY
| SEC_DATA
));
960 (void) bfd_set_section_alignment (stdoutput
, sec
, 2);
963 mips_regmask_frag
= frag_more (sizeof (Elf32_External_RegInfo
));
968 /* The 64-bit ABI uses a .MIPS.options section rather than
970 sec
= subseg_new (".MIPS.options", (subsegT
) 0);
971 (void) bfd_set_section_flags (stdoutput
, sec
,
972 (SEC_ALLOC
| SEC_LOAD
973 | SEC_READONLY
| SEC_DATA
));
974 (void) bfd_set_section_alignment (stdoutput
, sec
, 3);
977 /* Set up the option header. */
979 Elf_Internal_Options opthdr
;
982 opthdr
.kind
= ODK_REGINFO
;
983 opthdr
.size
= (sizeof (Elf_External_Options
)
984 + sizeof (Elf64_External_RegInfo
));
987 f
= frag_more (sizeof (Elf_External_Options
));
988 bfd_mips_elf_swap_options_out (stdoutput
, &opthdr
,
989 (Elf_External_Options
*) f
);
991 mips_regmask_frag
= frag_more (sizeof (Elf64_External_RegInfo
));
998 sec
= subseg_new (".mdebug", (subsegT
) 0);
999 (void) bfd_set_section_flags (stdoutput
, sec
,
1000 SEC_HAS_CONTENTS
| SEC_READONLY
);
1001 (void) bfd_set_section_alignment (stdoutput
, sec
, 2);
1004 subseg_set (seg
, subseg
);
1008 if (! ECOFF_DEBUGGING
)
1015 if (! ECOFF_DEBUGGING
)
1023 struct mips_cl_insn insn
;
1025 imm_expr
.X_op
= O_absent
;
1026 imm_reloc
= BFD_RELOC_UNUSED
;
1027 imm_unmatched_hi
= false;
1028 offset_expr
.X_op
= O_absent
;
1029 offset_reloc
= BFD_RELOC_UNUSED
;
1032 mips16_ip (str
, &insn
);
1034 mips_ip (str
, &insn
);
1038 as_bad ("%s `%s'", insn_error
, str
);
1042 if (insn
.insn_mo
->pinfo
== INSN_MACRO
)
1045 mips16_macro (&insn
);
1051 if (imm_expr
.X_op
!= O_absent
)
1052 append_insn ((char *) NULL
, &insn
, &imm_expr
, imm_reloc
,
1054 else if (offset_expr
.X_op
!= O_absent
)
1055 append_insn ((char *) NULL
, &insn
, &offset_expr
, offset_reloc
, false);
1057 append_insn ((char *) NULL
, &insn
, NULL
, BFD_RELOC_UNUSED
, false);
1061 /* See whether instruction IP reads register REG. CLASS is the type
1065 insn_uses_reg (ip
, reg
, class)
1066 struct mips_cl_insn
*ip
;
1068 enum mips_regclass
class;
1070 if (class == MIPS16_REG
)
1073 reg
= mips16_to_32_reg_map
[reg
];
1074 class = MIPS_GR_REG
;
1077 /* Don't report on general register 0, since it never changes. */
1078 if (class == MIPS_GR_REG
&& reg
== 0)
1081 if (class == MIPS_FP_REG
)
1084 /* If we are called with either $f0 or $f1, we must check $f0.
1085 This is not optimal, because it will introduce an unnecessary
1086 NOP between "lwc1 $f0" and "swc1 $f1". To fix this we would
1087 need to distinguish reading both $f0 and $f1 or just one of
1088 them. Note that we don't have to check the other way,
1089 because there is no instruction that sets both $f0 and $f1
1090 and requires a delay. */
1091 if ((ip
->insn_mo
->pinfo
& INSN_READ_FPR_S
)
1092 && (((ip
->insn_opcode
>> OP_SH_FS
) & OP_MASK_FS
)
1093 == (reg
&~ (unsigned) 1)))
1095 if ((ip
->insn_mo
->pinfo
& INSN_READ_FPR_T
)
1096 && (((ip
->insn_opcode
>> OP_SH_FT
) & OP_MASK_FT
)
1097 == (reg
&~ (unsigned) 1)))
1102 if ((ip
->insn_mo
->pinfo
& INSN_READ_GPR_S
)
1103 && ((ip
->insn_opcode
>> OP_SH_RS
) & OP_MASK_RS
) == reg
)
1105 if ((ip
->insn_mo
->pinfo
& INSN_READ_GPR_T
)
1106 && ((ip
->insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
) == reg
)
1111 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_X
)
1112 && ((ip
->insn_opcode
>> MIPS16OP_SH_RX
) & MIPS16OP_MASK_RX
) == reg
)
1114 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_Y
)
1115 && ((ip
->insn_opcode
>> MIPS16OP_SH_RY
) & MIPS16OP_MASK_RY
) == reg
)
1117 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_Z
)
1118 && ((ip
->insn_opcode
>> MIPS16OP_SH_MOVE32Z
)
1119 & MIPS16OP_MASK_MOVE32Z
) == reg
)
1121 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_T
) && reg
== TREG
)
1123 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_SP
) && reg
== SP
)
1125 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_31
) && reg
== RA
)
1127 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_GPR_X
)
1128 && ((ip
->insn_opcode
>> MIPS16OP_SH_REGR32
)
1129 & MIPS16OP_MASK_REGR32
) == reg
)
1136 /* This function returns true if modifying a register requires a
1140 reg_needs_delay (reg
)
1143 unsigned long prev_pinfo
;
1145 prev_pinfo
= prev_insn
.insn_mo
->pinfo
;
1146 if (! mips_noreorder
1148 && ((prev_pinfo
& INSN_LOAD_COPROC_DELAY
)
1150 && (prev_pinfo
& INSN_LOAD_MEMORY_DELAY
))))
1152 /* A load from a coprocessor or from memory. All load
1153 delays delay the use of general register rt for one
1154 instruction on the r3000. The r6000 and r4000 use
1156 know (prev_pinfo
& INSN_WRITE_GPR_T
);
1157 if (reg
== ((prev_insn
.insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
))
1164 /* Output an instruction. PLACE is where to put the instruction; if
1165 it is NULL, this uses frag_more to get room. IP is the instruction
1166 information. ADDRESS_EXPR is an operand of the instruction to be
1167 used with RELOC_TYPE. */
1170 append_insn (place
, ip
, address_expr
, reloc_type
, unmatched_hi
)
1172 struct mips_cl_insn
*ip
;
1173 expressionS
*address_expr
;
1174 bfd_reloc_code_real_type reloc_type
;
1175 boolean unmatched_hi
;
1177 register unsigned long prev_pinfo
, pinfo
;
1182 /* Mark instruction labels in mips16 mode. This permits the linker
1183 to handle them specially, such as generating jalx instructions
1184 when needed. We also make them odd for the duration of the
1185 assembly, in order to generate the right sort of code. We will
1186 make them even in the adjust_symtab routine, while leaving them
1187 marked. This is convenient for the debugger and the
1188 disassembler. The linker knows to make them odd again. */
1191 struct insn_label_list
*l
;
1193 for (l
= insn_labels
; l
!= NULL
; l
= l
->next
)
1196 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
1197 S_SET_OTHER (l
->label
, STO_MIPS16
);
1199 ++l
->label
->sy_value
.X_add_number
;
1203 prev_pinfo
= prev_insn
.insn_mo
->pinfo
;
1204 pinfo
= ip
->insn_mo
->pinfo
;
1206 if (place
== NULL
&& ! mips_noreorder
)
1208 /* If the previous insn required any delay slots, see if we need
1209 to insert a NOP or two. There are eight kinds of possible
1210 hazards, of which an instruction can have at most one type.
1211 (1) a load from memory delay
1212 (2) a load from a coprocessor delay
1213 (3) an unconditional branch delay
1214 (4) a conditional branch delay
1215 (5) a move to coprocessor register delay
1216 (6) a load coprocessor register from memory delay
1217 (7) a coprocessor condition code delay
1218 (8) a HI/LO special register delay
1220 There are a lot of optimizations we could do that we don't.
1221 In particular, we do not, in general, reorder instructions.
1222 If you use gcc with optimization, it will reorder
1223 instructions and generally do much more optimization then we
1224 do here; repeating all that work in the assembler would only
1225 benefit hand written assembly code, and does not seem worth
1228 /* This is how a NOP is emitted. */
1229 #define emit_nop() \
1231 ? md_number_to_chars (frag_more (2), 0x6500, 2) \
1232 : md_number_to_chars (frag_more (4), 0, 4))
1234 /* The previous insn might require a delay slot, depending upon
1235 the contents of the current insn. */
1238 && (((prev_pinfo
& INSN_LOAD_COPROC_DELAY
)
1239 && ! cop_interlocks
)
1241 && (prev_pinfo
& INSN_LOAD_MEMORY_DELAY
))))
1243 /* A load from a coprocessor or from memory. All load
1244 delays delay the use of general register rt for one
1245 instruction on the r3000. The r6000 and r4000 use
1247 know (prev_pinfo
& INSN_WRITE_GPR_T
);
1248 if (mips_optimize
== 0
1249 || insn_uses_reg (ip
,
1250 ((prev_insn
.insn_opcode
>> OP_SH_RT
)
1257 && (((prev_pinfo
& INSN_COPROC_MOVE_DELAY
)
1258 && ! cop_interlocks
)
1260 && (prev_pinfo
& INSN_COPROC_MEMORY_DELAY
))))
1262 /* A generic coprocessor delay. The previous instruction
1263 modified a coprocessor general or control register. If
1264 it modified a control register, we need to avoid any
1265 coprocessor instruction (this is probably not always
1266 required, but it sometimes is). If it modified a general
1267 register, we avoid using that register.
1269 On the r6000 and r4000 loading a coprocessor register
1270 from memory is interlocked, and does not require a delay.
1272 This case is not handled very well. There is no special
1273 knowledge of CP0 handling, and the coprocessors other
1274 than the floating point unit are not distinguished at
1276 if (prev_pinfo
& INSN_WRITE_FPR_T
)
1278 if (mips_optimize
== 0
1279 || insn_uses_reg (ip
,
1280 ((prev_insn
.insn_opcode
>> OP_SH_FT
)
1285 else if (prev_pinfo
& INSN_WRITE_FPR_S
)
1287 if (mips_optimize
== 0
1288 || insn_uses_reg (ip
,
1289 ((prev_insn
.insn_opcode
>> OP_SH_FS
)
1296 /* We don't know exactly what the previous instruction
1297 does. If the current instruction uses a coprocessor
1298 register, we must insert a NOP. If previous
1299 instruction may set the condition codes, and the
1300 current instruction uses them, we must insert two
1302 if (mips_optimize
== 0
1303 || ((prev_pinfo
& INSN_WRITE_COND_CODE
)
1304 && (pinfo
& INSN_READ_COND_CODE
)))
1306 else if (pinfo
& INSN_COP
)
1312 && (prev_pinfo
& INSN_WRITE_COND_CODE
)
1313 && ! cop_interlocks
)
1315 /* The previous instruction sets the coprocessor condition
1316 codes, but does not require a general coprocessor delay
1317 (this means it is a floating point comparison
1318 instruction). If this instruction uses the condition
1319 codes, we need to insert a single NOP. */
1320 if (mips_optimize
== 0
1321 || (pinfo
& INSN_READ_COND_CODE
))
1324 else if (prev_pinfo
& INSN_READ_LO
)
1326 /* The previous instruction reads the LO register; if the
1327 current instruction writes to the LO register, we must
1328 insert two NOPS. Some newer processors have interlocks. */
1330 && (mips_optimize
== 0
1331 || (pinfo
& INSN_WRITE_LO
)))
1334 else if (prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
1336 /* The previous instruction reads the HI register; if the
1337 current instruction writes to the HI register, we must
1338 insert a NOP. Some newer processors have interlocks. */
1340 && (mips_optimize
== 0
1341 || (pinfo
& INSN_WRITE_HI
)))
1345 /* There are two cases which require two intervening
1346 instructions: 1) setting the condition codes using a move to
1347 coprocessor instruction which requires a general coprocessor
1348 delay and then reading the condition codes 2) reading the HI
1349 or LO register and then writing to it (except on processors
1350 which have interlocks). If we are not already emitting a NOP
1351 instruction, we must check for these cases compared to the
1352 instruction previous to the previous instruction. */
1356 && (prev_prev_insn
.insn_mo
->pinfo
& INSN_COPROC_MOVE_DELAY
)
1357 && (prev_prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
)
1358 && (pinfo
& INSN_READ_COND_CODE
)
1359 && ! cop_interlocks
)
1360 || ((prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
)
1361 && (pinfo
& INSN_WRITE_LO
)
1363 || ((prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
1364 && (pinfo
& INSN_WRITE_HI
)
1368 /* If we are being given a nop instruction, don't bother with
1369 one of the nops we would otherwise output. This will only
1370 happen when a nop instruction is used with mips_optimize set
1372 if (nops
> 0 && ip
->insn_opcode
== (mips16
? 0x6500 : 0))
1375 /* Now emit the right number of NOP instructions. */
1379 unsigned long old_frag_offset
;
1381 struct insn_label_list
*l
;
1383 old_frag
= frag_now
;
1384 old_frag_offset
= frag_now_fix ();
1386 for (i
= 0; i
< nops
; i
++)
1391 listing_prev_line ();
1392 /* We may be at the start of a variant frag. In case we
1393 are, make sure there is enough space for the frag
1394 after the frags created by listing_prev_line. The
1395 argument to frag_grow here must be at least as large
1396 as the argument to all other calls to frag_grow in
1397 this file. We don't have to worry about being in the
1398 middle of a variant frag, because the variants insert
1399 all needed nop instructions themselves. */
1403 for (l
= insn_labels
; l
!= NULL
; l
= l
->next
)
1405 assert (S_GET_SEGMENT (l
->label
) == now_seg
);
1406 l
->label
->sy_frag
= frag_now
;
1407 S_SET_VALUE (l
->label
, (valueT
) frag_now_fix ());
1408 /* mips16 text labels are stored as odd. */
1410 ++l
->label
->sy_value
.X_add_number
;
1413 #ifndef NO_ECOFF_DEBUGGING
1414 if (ECOFF_DEBUGGING
)
1415 ecoff_fix_loc (old_frag
, old_frag_offset
);
1420 if (reloc_type
> BFD_RELOC_UNUSED
)
1422 /* We need to set up a variant frag. */
1423 assert (mips16
&& address_expr
!= NULL
);
1424 f
= frag_var (rs_machine_dependent
, 4, 0,
1425 RELAX_MIPS16_ENCODE (reloc_type
- BFD_RELOC_UNUSED
,
1426 mips16_small
, mips16_ext
,
1428 & INSN_UNCOND_BRANCH_DELAY
),
1429 (prev_insn_reloc_type
1430 == BFD_RELOC_MIPS16_JMP
)),
1431 make_expr_symbol (address_expr
), (long) 0,
1434 else if (place
!= NULL
)
1436 else if (mips16
&& ! ip
->use_extend
&& reloc_type
!= BFD_RELOC_MIPS16_JMP
)
1438 /* Make sure there is enough room to swap this instruction with
1439 a following jump instruction. */
1446 if (address_expr
!= NULL
&& reloc_type
< BFD_RELOC_UNUSED
)
1448 if (address_expr
->X_op
== O_constant
)
1453 ip
->insn_opcode
|= address_expr
->X_add_number
;
1456 case BFD_RELOC_LO16
:
1457 ip
->insn_opcode
|= address_expr
->X_add_number
& 0xffff;
1460 case BFD_RELOC_MIPS_JMP
:
1461 ip
->insn_opcode
|= (address_expr
->X_add_number
>> 2) & 0x3ffffff;
1464 case BFD_RELOC_MIPS16_JMP
:
1466 (((address_expr
->X_add_number
& 0x7c0000) << 3)
1467 | ((address_expr
->X_add_number
& 0xf800000) >> 7)
1468 | ((address_expr
->X_add_number
& 0x3fffc) >> 2));
1471 case BFD_RELOC_16_PCREL_S2
:
1481 /* Don't generate a reloc if we are writing into a variant
1485 fixp
= fix_new_exp (frag_now
, f
- frag_now
->fr_literal
, 4,
1487 reloc_type
== BFD_RELOC_16_PCREL_S2
,
1491 struct mips_hi_fixup
*hi_fixup
;
1493 assert (reloc_type
== BFD_RELOC_HI16_S
);
1494 hi_fixup
= ((struct mips_hi_fixup
*)
1495 xmalloc (sizeof (struct mips_hi_fixup
)));
1496 hi_fixup
->fixp
= fixp
;
1497 hi_fixup
->seg
= now_seg
;
1498 hi_fixup
->next
= mips_hi_fixup_list
;
1499 mips_hi_fixup_list
= hi_fixup
;
1505 if (! mips16
|| reloc_type
== BFD_RELOC_MIPS16_JMP
)
1506 md_number_to_chars (f
, ip
->insn_opcode
, 4);
1511 md_number_to_chars (f
, 0xf000 | ip
->extend
, 2);
1514 md_number_to_chars (f
, ip
->insn_opcode
, 2);
1517 /* Update the register mask information. */
1520 if (pinfo
& INSN_WRITE_GPR_D
)
1521 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
);
1522 if ((pinfo
& (INSN_WRITE_GPR_T
| INSN_READ_GPR_T
)) != 0)
1523 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
);
1524 if (pinfo
& INSN_READ_GPR_S
)
1525 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> OP_SH_RS
) & OP_MASK_RS
);
1526 if (pinfo
& INSN_WRITE_GPR_31
)
1527 mips_gprmask
|= 1 << 31;
1528 if (pinfo
& INSN_WRITE_FPR_D
)
1529 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FD
) & OP_MASK_FD
);
1530 if ((pinfo
& (INSN_WRITE_FPR_S
| INSN_READ_FPR_S
)) != 0)
1531 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FS
) & OP_MASK_FS
);
1532 if ((pinfo
& (INSN_WRITE_FPR_T
| INSN_READ_FPR_T
)) != 0)
1533 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FT
) & OP_MASK_FT
);
1534 if ((pinfo
& INSN_READ_FPR_R
) != 0)
1535 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FR
) & OP_MASK_FR
);
1536 if (pinfo
& INSN_COP
)
1538 /* We don't keep enough information to sort these cases out. */
1540 /* Never set the bit for $0, which is always zero. */
1541 mips_gprmask
&=~ 1 << 0;
1545 if (pinfo
& (MIPS16_INSN_WRITE_X
| MIPS16_INSN_READ_X
))
1546 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_RX
)
1547 & MIPS16OP_MASK_RX
);
1548 if (pinfo
& (MIPS16_INSN_WRITE_Y
| MIPS16_INSN_READ_Y
))
1549 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_RY
)
1550 & MIPS16OP_MASK_RY
);
1551 if (pinfo
& MIPS16_INSN_WRITE_Z
)
1552 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_RZ
)
1553 & MIPS16OP_MASK_RZ
);
1554 if (pinfo
& (MIPS16_INSN_WRITE_T
| MIPS16_INSN_READ_T
))
1555 mips_gprmask
|= 1 << TREG
;
1556 if (pinfo
& (MIPS16_INSN_WRITE_SP
| MIPS16_INSN_READ_SP
))
1557 mips_gprmask
|= 1 << SP
;
1558 if (pinfo
& (MIPS16_INSN_WRITE_31
| MIPS16_INSN_READ_31
))
1559 mips_gprmask
|= 1 << RA
;
1560 if (pinfo
& MIPS16_INSN_WRITE_GPR_Y
)
1561 mips_gprmask
|= 1 << MIPS16OP_EXTRACT_REG32R (ip
->insn_opcode
);
1562 if (pinfo
& MIPS16_INSN_READ_Z
)
1563 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_MOVE32Z
)
1564 & MIPS16OP_MASK_MOVE32Z
);
1565 if (pinfo
& MIPS16_INSN_READ_GPR_X
)
1566 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_REGR32
)
1567 & MIPS16OP_MASK_REGR32
);
1570 if (place
== NULL
&& ! mips_noreorder
)
1572 /* Filling the branch delay slot is more complex. We try to
1573 switch the branch with the previous instruction, which we can
1574 do if the previous instruction does not set up a condition
1575 that the branch tests and if the branch is not itself the
1576 target of any branch. */
1577 if ((pinfo
& INSN_UNCOND_BRANCH_DELAY
)
1578 || (pinfo
& INSN_COND_BRANCH_DELAY
))
1580 if (mips_optimize
< 2
1581 /* If we have seen .set volatile or .set nomove, don't
1584 /* If we had to emit any NOP instructions, then we
1585 already know we can not swap. */
1587 /* If we don't even know the previous insn, we can not
1589 || ! prev_insn_valid
1590 /* If the previous insn is already in a branch delay
1591 slot, then we can not swap. */
1592 || prev_insn_is_delay_slot
1593 /* If the previous previous insn was in a .set
1594 noreorder, we can't swap. Actually, the MIPS
1595 assembler will swap in this situation. However, gcc
1596 configured -with-gnu-as will generate code like
1602 in which we can not swap the bne and INSN. If gcc is
1603 not configured -with-gnu-as, it does not output the
1604 .set pseudo-ops. We don't have to check
1605 prev_insn_unreordered, because prev_insn_valid will
1606 be 0 in that case. We don't want to use
1607 prev_prev_insn_valid, because we do want to be able
1608 to swap at the start of a function. */
1609 || prev_prev_insn_unreordered
1610 /* If the branch is itself the target of a branch, we
1611 can not swap. We cheat on this; all we check for is
1612 whether there is a label on this instruction. If
1613 there are any branches to anything other than a
1614 label, users must use .set noreorder. */
1615 || insn_labels
!= NULL
1616 /* If the previous instruction is in a variant frag, we
1617 can not do the swap. This does not apply to the
1618 mips16, which uses variant frags for different
1621 && prev_insn_frag
->fr_type
== rs_machine_dependent
)
1622 /* If the branch reads the condition codes, we don't
1623 even try to swap, because in the sequence
1628 we can not swap, and I don't feel like handling that
1632 && (pinfo
& INSN_READ_COND_CODE
))
1633 /* We can not swap with an instruction that requires a
1634 delay slot, becase the target of the branch might
1635 interfere with that instruction. */
1639 & (INSN_LOAD_COPROC_DELAY
1640 | INSN_COPROC_MOVE_DELAY
1641 | INSN_WRITE_COND_CODE
)))
1649 & (INSN_LOAD_MEMORY_DELAY
1650 | INSN_COPROC_MEMORY_DELAY
)))
1651 /* We can not swap with a branch instruction. */
1653 & (INSN_UNCOND_BRANCH_DELAY
1654 | INSN_COND_BRANCH_DELAY
1655 | INSN_COND_BRANCH_LIKELY
))
1656 /* We do not swap with a trap instruction, since it
1657 complicates trap handlers to have the trap
1658 instruction be in a delay slot. */
1659 || (prev_pinfo
& INSN_TRAP
)
1660 /* If the branch reads a register that the previous
1661 instruction sets, we can not swap. */
1663 && (prev_pinfo
& INSN_WRITE_GPR_T
)
1664 && insn_uses_reg (ip
,
1665 ((prev_insn
.insn_opcode
>> OP_SH_RT
)
1669 && (prev_pinfo
& INSN_WRITE_GPR_D
)
1670 && insn_uses_reg (ip
,
1671 ((prev_insn
.insn_opcode
>> OP_SH_RD
)
1675 && (((prev_pinfo
& MIPS16_INSN_WRITE_X
)
1676 && insn_uses_reg (ip
,
1677 ((prev_insn
.insn_opcode
1679 & MIPS16OP_MASK_RX
),
1681 || ((prev_pinfo
& MIPS16_INSN_WRITE_Y
)
1682 && insn_uses_reg (ip
,
1683 ((prev_insn
.insn_opcode
1685 & MIPS16OP_MASK_RY
),
1687 || ((prev_pinfo
& MIPS16_INSN_WRITE_Z
)
1688 && insn_uses_reg (ip
,
1689 ((prev_insn
.insn_opcode
1691 & MIPS16OP_MASK_RZ
),
1693 || ((prev_pinfo
& MIPS16_INSN_WRITE_T
)
1694 && insn_uses_reg (ip
, TREG
, MIPS_GR_REG
))
1695 || ((prev_pinfo
& MIPS16_INSN_WRITE_31
)
1696 && insn_uses_reg (ip
, RA
, MIPS_GR_REG
))
1697 || ((prev_pinfo
& MIPS16_INSN_WRITE_GPR_Y
)
1698 && insn_uses_reg (ip
,
1699 MIPS16OP_EXTRACT_REG32R (prev_insn
.
1702 /* If the branch writes a register that the previous
1703 instruction sets, we can not swap (we know that
1704 branches write only to RD or to $31). */
1706 && (prev_pinfo
& INSN_WRITE_GPR_T
)
1707 && (((pinfo
& INSN_WRITE_GPR_D
)
1708 && (((prev_insn
.insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
)
1709 == ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)))
1710 || ((pinfo
& INSN_WRITE_GPR_31
)
1711 && (((prev_insn
.insn_opcode
>> OP_SH_RT
)
1715 && (prev_pinfo
& INSN_WRITE_GPR_D
)
1716 && (((pinfo
& INSN_WRITE_GPR_D
)
1717 && (((prev_insn
.insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)
1718 == ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)))
1719 || ((pinfo
& INSN_WRITE_GPR_31
)
1720 && (((prev_insn
.insn_opcode
>> OP_SH_RD
)
1724 && (pinfo
& MIPS16_INSN_WRITE_31
)
1725 && ((prev_pinfo
& MIPS16_INSN_WRITE_31
)
1726 || ((prev_pinfo
& MIPS16_INSN_WRITE_GPR_Y
)
1727 && (MIPS16OP_EXTRACT_REG32R (prev_insn
.insn_opcode
)
1729 /* If the branch writes a register that the previous
1730 instruction reads, we can not swap (we know that
1731 branches only write to RD or to $31). */
1733 && (pinfo
& INSN_WRITE_GPR_D
)
1734 && insn_uses_reg (&prev_insn
,
1735 ((ip
->insn_opcode
>> OP_SH_RD
)
1739 && (pinfo
& INSN_WRITE_GPR_31
)
1740 && insn_uses_reg (&prev_insn
, 31, MIPS_GR_REG
))
1742 && (pinfo
& MIPS16_INSN_WRITE_31
)
1743 && insn_uses_reg (&prev_insn
, RA
, MIPS_GR_REG
))
1744 /* If we are generating embedded PIC code, the branch
1745 might be expanded into a sequence which uses $at, so
1746 we can't swap with an instruction which reads it. */
1747 || (mips_pic
== EMBEDDED_PIC
1748 && insn_uses_reg (&prev_insn
, AT
, MIPS_GR_REG
))
1749 /* If the previous previous instruction has a load
1750 delay, and sets a register that the branch reads, we
1754 && ((prev_prev_insn
.insn_mo
->pinfo
& INSN_LOAD_COPROC_DELAY
)
1756 && (prev_prev_insn
.insn_mo
->pinfo
1757 & INSN_LOAD_MEMORY_DELAY
)))
1758 && insn_uses_reg (ip
,
1759 ((prev_prev_insn
.insn_opcode
>> OP_SH_RT
)
1762 /* If one instruction sets a condition code and the
1763 other one uses a condition code, we can not swap. */
1764 || ((pinfo
& INSN_READ_COND_CODE
)
1765 && (prev_pinfo
& INSN_WRITE_COND_CODE
))
1766 || ((pinfo
& INSN_WRITE_COND_CODE
)
1767 && (prev_pinfo
& INSN_READ_COND_CODE
))
1768 /* If the previous instruction uses the PC, we can not
1771 && (prev_pinfo
& MIPS16_INSN_READ_PC
))
1772 /* If the previous instruction was extended, we can not
1774 || (mips16
&& prev_insn_extended
)
1775 /* If the previous instruction had a fixup in mips16
1776 mode, we can not swap. This normally means that the
1777 previous instruction was a 4 byte branch anyhow. */
1778 || (mips16
&& prev_insn_fixp
))
1780 /* We could do even better for unconditional branches to
1781 portions of this object file; we could pick up the
1782 instruction at the destination, put it in the delay
1783 slot, and bump the destination address. */
1785 /* Update the previous insn information. */
1786 prev_prev_insn
= *ip
;
1787 prev_insn
.insn_mo
= &dummy_opcode
;
1791 /* It looks like we can actually do the swap. */
1797 prev_f
= prev_insn_frag
->fr_literal
+ prev_insn_where
;
1798 memcpy (temp
, prev_f
, 4);
1799 memcpy (prev_f
, f
, 4);
1800 memcpy (f
, temp
, 4);
1803 prev_insn_fixp
->fx_frag
= frag_now
;
1804 prev_insn_fixp
->fx_where
= f
- frag_now
->fr_literal
;
1808 fixp
->fx_frag
= prev_insn_frag
;
1809 fixp
->fx_where
= prev_insn_where
;
1812 else if (reloc_type
> BFD_RELOC_UNUSED
)
1817 /* We are in mips16 mode, and we have just created a
1818 variant frag. We need to extract the old
1819 instruction from the end of the previous frag,
1820 and add it to a new frag. */
1821 prev_f
= prev_insn_frag
->fr_literal
+ prev_insn_where
;
1822 memcpy (temp
, prev_f
, 2);
1823 prev_insn_frag
->fr_fix
-= 2;
1824 if (prev_insn_frag
->fr_type
== rs_machine_dependent
)
1826 assert (prev_insn_where
== prev_insn_frag
->fr_fix
);
1827 memcpy (prev_f
, prev_f
+ 2, 2);
1829 memcpy (frag_more (2), temp
, 2);
1836 assert (prev_insn_fixp
== NULL
);
1837 prev_f
= prev_insn_frag
->fr_literal
+ prev_insn_where
;
1838 memcpy (temp
, prev_f
, 2);
1839 memcpy (prev_f
, f
, 2);
1840 if (reloc_type
!= BFD_RELOC_MIPS16_JMP
)
1841 memcpy (f
, temp
, 2);
1844 memcpy (f
, f
+ 2, 2);
1845 memcpy (f
+ 2, temp
, 2);
1849 fixp
->fx_frag
= prev_insn_frag
;
1850 fixp
->fx_where
= prev_insn_where
;
1854 /* Update the previous insn information; leave prev_insn
1856 prev_prev_insn
= *ip
;
1858 prev_insn_is_delay_slot
= 1;
1860 /* If that was an unconditional branch, forget the previous
1861 insn information. */
1862 if (pinfo
& INSN_UNCOND_BRANCH_DELAY
)
1864 prev_prev_insn
.insn_mo
= &dummy_opcode
;
1865 prev_insn
.insn_mo
= &dummy_opcode
;
1868 prev_insn_fixp
= NULL
;
1869 prev_insn_reloc_type
= BFD_RELOC_UNUSED
;
1870 prev_insn_extended
= 0;
1872 else if (pinfo
& INSN_COND_BRANCH_LIKELY
)
1874 /* We don't yet optimize a branch likely. What we should do
1875 is look at the target, copy the instruction found there
1876 into the delay slot, and increment the branch to jump to
1877 the next instruction. */
1879 /* Update the previous insn information. */
1880 prev_prev_insn
= *ip
;
1881 prev_insn
.insn_mo
= &dummy_opcode
;
1882 prev_insn_fixp
= NULL
;
1883 prev_insn_reloc_type
= BFD_RELOC_UNUSED
;
1884 prev_insn_extended
= 0;
1888 /* Update the previous insn information. */
1890 prev_prev_insn
.insn_mo
= &dummy_opcode
;
1892 prev_prev_insn
= prev_insn
;
1895 /* Any time we see a branch, we always fill the delay slot
1896 immediately; since this insn is not a branch, we know it
1897 is not in a delay slot. */
1898 prev_insn_is_delay_slot
= 0;
1900 prev_insn_fixp
= fixp
;
1901 prev_insn_reloc_type
= reloc_type
;
1903 prev_insn_extended
= (ip
->use_extend
1904 || reloc_type
> BFD_RELOC_UNUSED
);
1907 prev_prev_insn_unreordered
= prev_insn_unreordered
;
1908 prev_insn_unreordered
= 0;
1909 prev_insn_frag
= frag_now
;
1910 prev_insn_where
= f
- frag_now
->fr_literal
;
1911 prev_insn_valid
= 1;
1913 else if (place
== NULL
)
1915 /* We need to record a bit of information even when we are not
1916 reordering, in order to determine the base address for mips16
1917 PC relative relocs. */
1919 prev_insn_reloc_type
= reloc_type
;
1922 /* We just output an insn, so the next one doesn't have a label. */
1923 mips_clear_insn_labels ();
1926 /* This function forgets that there was any previous instruction or
1930 mips_no_prev_insn ()
1932 prev_insn
.insn_mo
= &dummy_opcode
;
1933 prev_prev_insn
.insn_mo
= &dummy_opcode
;
1934 prev_insn_valid
= 0;
1935 prev_insn_is_delay_slot
= 0;
1936 prev_insn_unreordered
= 0;
1937 prev_insn_extended
= 0;
1938 prev_insn_reloc_type
= BFD_RELOC_UNUSED
;
1939 prev_prev_insn_unreordered
= 0;
1940 mips_clear_insn_labels ();
1943 /* This function must be called whenever we turn on noreorder or emit
1944 something other than instructions. It inserts any NOPS which might
1945 be needed by the previous instruction, and clears the information
1946 kept for the previous instructions. The INSNS parameter is true if
1947 instructions are to follow. */
1950 mips_emit_delays (insns
)
1953 if (! mips_noreorder
)
1960 && (! cop_interlocks
1961 && (prev_insn
.insn_mo
->pinfo
1962 & (INSN_LOAD_COPROC_DELAY
1963 | INSN_COPROC_MOVE_DELAY
1964 | INSN_WRITE_COND_CODE
))))
1966 && (prev_insn
.insn_mo
->pinfo
1971 && (prev_insn
.insn_mo
->pinfo
1972 & (INSN_LOAD_MEMORY_DELAY
1973 | INSN_COPROC_MEMORY_DELAY
))))
1978 && (! cop_interlocks
1979 && prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
))
1981 && ((prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
1982 || (prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
))))
1987 && (! cop_interlocks
1988 && prev_prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
))
1990 && ((prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
1991 || (prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
))))
1995 struct insn_label_list
*l
;
1998 for (l
= insn_labels
; l
!= NULL
; l
= l
->next
)
2000 assert (S_GET_SEGMENT (l
->label
) == now_seg
);
2001 l
->label
->sy_frag
= frag_now
;
2002 S_SET_VALUE (l
->label
, (valueT
) frag_now_fix ());
2003 /* mips16 text labels are stored as odd. */
2005 ++l
->label
->sy_value
.X_add_number
;
2010 /* Mark instruction labels in mips16 mode. This permits the linker
2011 to handle them specially, such as generating jalx instructions
2012 when needed. We also make them odd for the duration of the
2013 assembly, in order to generate the right sort of code. We will
2014 make them even in the adjust_symtab routine, while leaving them
2015 marked. This is convenient for the debugger and the
2016 disassembler. The linker knows to make them odd again. */
2017 if (mips16
&& insns
)
2019 struct insn_label_list
*l
;
2021 for (l
= insn_labels
; l
!= NULL
; l
= l
->next
)
2024 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
2025 S_SET_OTHER (l
->label
, STO_MIPS16
);
2027 if ((l
->label
->sy_value
.X_add_number
& 1) == 0)
2028 ++l
->label
->sy_value
.X_add_number
;
2032 mips_no_prev_insn ();
2035 /* Build an instruction created by a macro expansion. This is passed
2036 a pointer to the count of instructions created so far, an
2037 expression, the name of the instruction to build, an operand format
2038 string, and corresponding arguments. */
2042 macro_build (char *place
,
2050 macro_build (place
, counter
, ep
, name
, fmt
, va_alist
)
2059 struct mips_cl_insn insn
;
2060 bfd_reloc_code_real_type r
;
2064 va_start (args
, fmt
);
2070 * If the macro is about to expand into a second instruction,
2071 * print a warning if needed. We need to pass ip as a parameter
2072 * to generate a better warning message here...
2074 if (mips_warn_about_macros
&& place
== NULL
&& *counter
== 1)
2075 as_warn ("Macro instruction expanded into multiple instructions");
2078 *counter
+= 1; /* bump instruction counter */
2082 mips16_macro_build (place
, counter
, ep
, name
, fmt
, args
);
2087 r
= BFD_RELOC_UNUSED
;
2088 insn
.insn_mo
= (struct mips_opcode
*) hash_find (op_hash
, name
);
2089 assert (insn
.insn_mo
);
2090 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
2092 while (strcmp (fmt
, insn
.insn_mo
->args
) != 0
2093 || insn
.insn_mo
->pinfo
== INSN_MACRO
2094 || ((insn
.insn_mo
->pinfo
& INSN_ISA
) == INSN_ISA2
2096 || ((insn
.insn_mo
->pinfo
& INSN_ISA
) == INSN_ISA3
2098 || ((insn
.insn_mo
->pinfo
& INSN_ISA
) == INSN_ISA4
2100 || ((insn
.insn_mo
->pinfo
& INSN_ISA
) == INSN_4650
2102 || ((insn
.insn_mo
->pinfo
& INSN_ISA
) == INSN_4010
2104 || ((insn
.insn_mo
->pinfo
& INSN_ISA
) == INSN_4100
2108 assert (insn
.insn_mo
->name
);
2109 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
2111 insn
.insn_opcode
= insn
.insn_mo
->match
;
2127 insn
.insn_opcode
|= va_arg (args
, int) << 16;
2133 insn
.insn_opcode
|= va_arg (args
, int) << 16;
2138 insn
.insn_opcode
|= va_arg (args
, int) << 11;
2143 insn
.insn_opcode
|= va_arg (args
, int) << 11;
2150 insn
.insn_opcode
|= va_arg (args
, int) << 6;
2154 insn
.insn_opcode
|= va_arg (args
, int) << 6;
2158 insn
.insn_opcode
|= va_arg (args
, int) << 6;
2165 insn
.insn_opcode
|= va_arg (args
, int) << 21;
2171 r
= (bfd_reloc_code_real_type
) va_arg (args
, int);
2172 assert (r
== BFD_RELOC_MIPS_GPREL
2173 || r
== BFD_RELOC_MIPS_LITERAL
2174 || r
== BFD_RELOC_LO16
2175 || r
== BFD_RELOC_MIPS_GOT16
2176 || r
== BFD_RELOC_MIPS_CALL16
2177 || r
== BFD_RELOC_MIPS_GOT_LO16
2178 || r
== BFD_RELOC_MIPS_CALL_LO16
2179 || (ep
->X_op
== O_subtract
2180 && now_seg
== text_section
2181 && r
== BFD_RELOC_PCREL_LO16
));
2185 r
= (bfd_reloc_code_real_type
) va_arg (args
, int);
2187 && (ep
->X_op
== O_constant
2188 || (ep
->X_op
== O_symbol
2189 && (r
== BFD_RELOC_HI16_S
2190 || r
== BFD_RELOC_HI16
2191 || r
== BFD_RELOC_MIPS_GOT_HI16
2192 || r
== BFD_RELOC_MIPS_CALL_HI16
))
2193 || (ep
->X_op
== O_subtract
2194 && now_seg
== text_section
2195 && r
== BFD_RELOC_PCREL_HI16_S
)));
2196 if (ep
->X_op
== O_constant
)
2198 insn
.insn_opcode
|= (ep
->X_add_number
>> 16) & 0xffff;
2200 r
= BFD_RELOC_UNUSED
;
2205 assert (ep
!= NULL
);
2207 * This allows macro() to pass an immediate expression for
2208 * creating short branches without creating a symbol.
2209 * Note that the expression still might come from the assembly
2210 * input, in which case the value is not checked for range nor
2211 * is a relocation entry generated (yuck).
2213 if (ep
->X_op
== O_constant
)
2215 insn
.insn_opcode
|= (ep
->X_add_number
>> 2) & 0xffff;
2219 r
= BFD_RELOC_16_PCREL_S2
;
2223 assert (ep
!= NULL
);
2224 r
= BFD_RELOC_MIPS_JMP
;
2233 assert (r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
2235 append_insn (place
, &insn
, ep
, r
, false);
2239 mips16_macro_build (place
, counter
, ep
, name
, fmt
, args
)
2247 struct mips_cl_insn insn
;
2248 bfd_reloc_code_real_type r
;
2250 r
= BFD_RELOC_UNUSED
;
2251 insn
.insn_mo
= (struct mips_opcode
*) hash_find (mips16_op_hash
, name
);
2252 assert (insn
.insn_mo
);
2253 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
2255 while (strcmp (fmt
, insn
.insn_mo
->args
) != 0
2256 || insn
.insn_mo
->pinfo
== INSN_MACRO
)
2259 assert (insn
.insn_mo
->name
);
2260 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
2263 insn
.insn_opcode
= insn
.insn_mo
->match
;
2264 insn
.use_extend
= false;
2283 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_RY
;
2288 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_RX
;
2292 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_RZ
;
2296 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_MOVE32Z
;
2306 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_REGR32
;
2313 regno
= va_arg (args
, int);
2314 regno
= ((regno
& 7) << 2) | ((regno
& 0x18) >> 3);
2315 insn
.insn_opcode
|= regno
<< MIPS16OP_SH_REG32R
;
2336 assert (ep
!= NULL
);
2338 if (ep
->X_op
!= O_constant
)
2339 r
= BFD_RELOC_UNUSED
+ c
;
2342 mips16_immed ((char *) NULL
, 0, c
, ep
->X_add_number
, false,
2343 false, false, &insn
.insn_opcode
,
2344 &insn
.use_extend
, &insn
.extend
);
2346 r
= BFD_RELOC_UNUSED
;
2352 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_IMM6
;
2359 assert (r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
2361 append_insn (place
, &insn
, ep
, r
, false);
2365 * Generate a "lui" instruction.
2368 macro_build_lui (place
, counter
, ep
, regnum
)
2374 expressionS high_expr
;
2375 struct mips_cl_insn insn
;
2376 bfd_reloc_code_real_type r
;
2377 CONST
char *name
= "lui";
2378 CONST
char *fmt
= "t,u";
2386 high_expr
.X_op
= O_constant
;
2387 high_expr
.X_add_number
= ep
->X_add_number
;
2390 if (high_expr
.X_op
== O_constant
)
2392 /* we can compute the instruction now without a relocation entry */
2393 if (high_expr
.X_add_number
& 0x8000)
2394 high_expr
.X_add_number
+= 0x10000;
2395 high_expr
.X_add_number
=
2396 ((unsigned long) high_expr
.X_add_number
>> 16) & 0xffff;
2397 r
= BFD_RELOC_UNUSED
;
2401 assert (ep
->X_op
== O_symbol
);
2402 /* _gp_disp is a special case, used from s_cpload. */
2403 assert (mips_pic
== NO_PIC
2404 || strcmp (S_GET_NAME (ep
->X_add_symbol
), "_gp_disp") == 0);
2405 r
= BFD_RELOC_HI16_S
;
2409 * If the macro is about to expand into a second instruction,
2410 * print a warning if needed. We need to pass ip as a parameter
2411 * to generate a better warning message here...
2413 if (mips_warn_about_macros
&& place
== NULL
&& *counter
== 1)
2414 as_warn ("Macro instruction expanded into multiple instructions");
2417 *counter
+= 1; /* bump instruction counter */
2419 insn
.insn_mo
= (struct mips_opcode
*) hash_find (op_hash
, name
);
2420 assert (insn
.insn_mo
);
2421 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
2422 assert (strcmp (fmt
, insn
.insn_mo
->args
) == 0);
2424 insn
.insn_opcode
= insn
.insn_mo
->match
| (regnum
<< OP_SH_RT
);
2425 if (r
== BFD_RELOC_UNUSED
)
2427 insn
.insn_opcode
|= high_expr
.X_add_number
;
2428 append_insn (place
, &insn
, NULL
, r
, false);
2431 append_insn (place
, &insn
, &high_expr
, r
, false);
2435 * Generates code to set the $at register to true (one)
2436 * if reg is less than the immediate expression.
2439 set_at (counter
, reg
, unsignedp
)
2444 if (imm_expr
.X_add_number
>= -0x8000 && imm_expr
.X_add_number
< 0x8000)
2445 macro_build ((char *) NULL
, counter
, &imm_expr
,
2446 unsignedp
? "sltiu" : "slti",
2447 "t,r,j", AT
, reg
, (int) BFD_RELOC_LO16
);
2450 load_register (counter
, AT
, &imm_expr
, 0);
2451 macro_build ((char *) NULL
, counter
, NULL
,
2452 unsignedp
? "sltu" : "slt",
2453 "d,v,t", AT
, reg
, AT
);
2457 /* Warn if an expression is not a constant. */
2460 check_absolute_expr (ip
, ex
)
2461 struct mips_cl_insn
*ip
;
2464 if (ex
->X_op
!= O_constant
)
2465 as_warn ("Instruction %s requires absolute expression", ip
->insn_mo
->name
);
2468 /* Count the leading zeroes by performing a binary chop. This is a
2469 bulky bit of source, but performance is a LOT better for the
2470 majority of values than a simple loop to count the bits:
2471 for (lcnt = 0; (lcnt < 32); lcnt++)
2472 if ((v) & (1 << (31 - lcnt)))
2474 However it is not code size friendly, and the gain will drop a bit
2475 on certain cached systems.
2477 #define COUNT_TOP_ZEROES(v) \
2478 (((v) & ~0xffff) == 0 \
2479 ? ((v) & ~0xff) == 0 \
2480 ? ((v) & ~0xf) == 0 \
2481 ? ((v) & ~0x3) == 0 \
2482 ? ((v) & ~0x1) == 0 \
2487 : ((v) & ~0x7) == 0 \
2490 : ((v) & ~0x3f) == 0 \
2491 ? ((v) & ~0x1f) == 0 \
2494 : ((v) & ~0x7f) == 0 \
2497 : ((v) & ~0xfff) == 0 \
2498 ? ((v) & ~0x3ff) == 0 \
2499 ? ((v) & ~0x1ff) == 0 \
2502 : ((v) & ~0x7ff) == 0 \
2505 : ((v) & ~0x3fff) == 0 \
2506 ? ((v) & ~0x1fff) == 0 \
2509 : ((v) & ~0x7fff) == 0 \
2512 : ((v) & ~0xffffff) == 0 \
2513 ? ((v) & ~0xfffff) == 0 \
2514 ? ((v) & ~0x3ffff) == 0 \
2515 ? ((v) & ~0x1ffff) == 0 \
2518 : ((v) & ~0x7ffff) == 0 \
2521 : ((v) & ~0x3fffff) == 0 \
2522 ? ((v) & ~0x1fffff) == 0 \
2525 : ((v) & ~0x7fffff) == 0 \
2528 : ((v) & ~0xfffffff) == 0 \
2529 ? ((v) & ~0x3ffffff) == 0 \
2530 ? ((v) & ~0x1ffffff) == 0 \
2533 : ((v) & ~0x7ffffff) == 0 \
2536 : ((v) & ~0x3fffffff) == 0 \
2537 ? ((v) & ~0x1fffffff) == 0 \
2540 : ((v) & ~0x7fffffff) == 0 \
2545 * This routine generates the least number of instructions neccessary to load
2546 * an absolute expression value into a register.
2549 load_register (counter
, reg
, ep
, dbl
)
2556 expressionS hi32
, lo32
;
2558 if (ep
->X_op
!= O_big
)
2560 assert (ep
->X_op
== O_constant
);
2561 if (ep
->X_add_number
< 0x8000
2562 && (ep
->X_add_number
>= 0
2563 || (ep
->X_add_number
>= -0x8000
2566 || sizeof (ep
->X_add_number
) > 4))))
2568 /* We can handle 16 bit signed values with an addiu to
2569 $zero. No need to ever use daddiu here, since $zero and
2570 the result are always correct in 32 bit mode. */
2571 macro_build ((char *) NULL
, counter
, ep
, "addiu", "t,r,j", reg
, 0,
2572 (int) BFD_RELOC_LO16
);
2575 else if (ep
->X_add_number
>= 0 && ep
->X_add_number
< 0x10000)
2577 /* We can handle 16 bit unsigned values with an ori to
2579 macro_build ((char *) NULL
, counter
, ep
, "ori", "t,r,i", reg
, 0,
2580 (int) BFD_RELOC_LO16
);
2583 else if ((((ep
->X_add_number
&~ (offsetT
) 0x7fffffff) == 0
2584 || ((ep
->X_add_number
&~ (offsetT
) 0x7fffffff)
2585 == ~ (offsetT
) 0x7fffffff))
2588 || sizeof (ep
->X_add_number
) > 4
2589 || (ep
->X_add_number
& 0x80000000) == 0))
2590 || ((mips_isa
< 3 || !dbl
)
2591 && (ep
->X_add_number
&~ (offsetT
) 0xffffffff) == 0))
2593 /* 32 bit values require an lui. */
2594 macro_build ((char *) NULL
, counter
, ep
, "lui", "t,u", reg
,
2595 (int) BFD_RELOC_HI16
);
2596 if ((ep
->X_add_number
& 0xffff) != 0)
2597 macro_build ((char *) NULL
, counter
, ep
, "ori", "t,r,i", reg
, reg
,
2598 (int) BFD_RELOC_LO16
);
2603 /* The value is larger than 32 bits. */
2607 as_bad ("Number larger than 32 bits");
2608 macro_build ((char *) NULL
, counter
, ep
, "addiu", "t,r,j", reg
, 0,
2609 (int) BFD_RELOC_LO16
);
2613 if (ep
->X_op
!= O_big
)
2616 hi32
.X_add_number
= (valueT
) hi32
.X_add_number
>> 16;
2617 hi32
.X_add_number
= (valueT
) hi32
.X_add_number
>> 16;
2618 hi32
.X_add_number
&= 0xffffffff;
2620 lo32
.X_add_number
&= 0xffffffff;
2624 assert (ep
->X_add_number
> 2);
2625 if (ep
->X_add_number
== 3)
2626 generic_bignum
[3] = 0;
2627 else if (ep
->X_add_number
> 4)
2628 as_bad ("Number larger than 64 bits");
2629 lo32
.X_op
= O_constant
;
2630 lo32
.X_add_number
= generic_bignum
[0] + (generic_bignum
[1] << 16);
2631 hi32
.X_op
= O_constant
;
2632 hi32
.X_add_number
= generic_bignum
[2] + (generic_bignum
[3] << 16);
2635 if (hi32
.X_add_number
== 0)
2640 unsigned long hi
, lo
;
2642 if (hi32
.X_add_number
== 0xffffffff)
2644 if ((lo32
.X_add_number
& 0xffff8000) == 0xffff8000)
2646 macro_build ((char *) NULL
, counter
, &lo32
, "addiu", "t,r,j",
2647 reg
, 0, (int) BFD_RELOC_LO16
);
2650 if (lo32
.X_add_number
& 0x80000000)
2652 macro_build ((char *) NULL
, counter
, &lo32
, "lui", "t,u", reg
,
2653 (int) BFD_RELOC_HI16
);
2654 if (lo32
.X_add_number
& 0xffff)
2655 macro_build ((char *) NULL
, counter
, &lo32
, "ori", "t,r,i",
2656 reg
, reg
, (int) BFD_RELOC_LO16
);
2661 /* Check for 16bit shifted constant. We know that hi32 is
2662 non-zero, so start the mask on the first bit of the hi32
2667 unsigned long himask
, lomask
;
2671 himask
= 0xffff >> (32 - shift
);
2672 lomask
= (0xffff << shift
) & 0xffffffff;
2676 himask
= 0xffff << (shift
- 32);
2679 if ((hi32
.X_add_number
& ~ (offsetT
) himask
) == 0
2680 && (lo32
.X_add_number
& ~ (offsetT
) lomask
) == 0)
2684 tmp
.X_op
= O_constant
;
2686 tmp
.X_add_number
= ((hi32
.X_add_number
<< (32 - shift
))
2687 | (lo32
.X_add_number
>> shift
));
2689 tmp
.X_add_number
= hi32
.X_add_number
>> (shift
- 32);
2690 macro_build ((char *) NULL
, counter
, &tmp
, "ori", "t,r,i", reg
, 0,
2691 (int) BFD_RELOC_LO16
);
2692 macro_build ((char *) NULL
, counter
, NULL
,
2693 (shift
>= 32) ? "dsll32" : "dsll",
2695 (shift
>= 32) ? shift
- 32 : shift
);
2699 } while (shift
<= (64 - 16));
2701 /* Find the bit number of the lowest one bit, and store the
2702 shifted value in hi/lo. */
2703 hi
= (unsigned long) (hi32
.X_add_number
& 0xffffffff);
2704 lo
= (unsigned long) (lo32
.X_add_number
& 0xffffffff);
2708 while ((lo
& 1) == 0)
2713 lo
|= (hi
& (((unsigned long) 1 << bit
) - 1)) << (32 - bit
);
2719 while ((hi
& 1) == 0)
2728 /* Optimize if the shifted value is a (power of 2) - 1. */
2729 if ((hi
== 0 && ((lo
+ 1) & lo
) == 0)
2730 || (lo
== 0xffffffff && ((hi
+ 1) & hi
) == 0))
2732 shift
= COUNT_TOP_ZEROES ((unsigned int) hi32
.X_add_number
);
2737 /* This instruction will set the register to be all
2739 tmp
.X_op
= O_constant
;
2740 tmp
.X_add_number
= (offsetT
) -1;
2741 macro_build ((char *) NULL
, counter
, &tmp
, "addiu", "t,r,j",
2742 reg
, 0, (int) BFD_RELOC_LO16
);
2746 macro_build ((char *) NULL
, counter
, NULL
,
2747 (bit
>= 32) ? "dsll32" : "dsll",
2749 (bit
>= 32) ? bit
- 32 : bit
);
2751 macro_build ((char *) NULL
, counter
, NULL
,
2752 (shift
>= 32) ? "dsrl32" : "dsrl",
2754 (shift
>= 32) ? shift
- 32 : shift
);
2759 /* Sign extend hi32 before calling load_register, because we can
2760 generally get better code when we load a sign extended value. */
2761 if ((hi32
.X_add_number
& 0x80000000) != 0)
2762 hi32
.X_add_number
|= ~ (offsetT
) 0xffffffff;
2763 load_register (counter
, reg
, &hi32
, 0);
2766 if ((lo32
.X_add_number
& 0xffff0000) == 0)
2770 macro_build ((char *) NULL
, counter
, NULL
, "dsll32", "d,w,<", reg
,
2779 if ((freg
== 0) && (lo32
.X_add_number
== 0xffffffff))
2781 macro_build ((char *) NULL
, counter
, &lo32
, "lui", "t,u", reg
,
2782 (int) BFD_RELOC_HI16
);
2783 macro_build ((char *) NULL
, counter
, NULL
, "dsrl32", "d,w,<", reg
,
2790 macro_build ((char *) NULL
, counter
, NULL
, "dsll", "d,w,<", reg
,
2795 mid16
.X_add_number
>>= 16;
2796 macro_build ((char *) NULL
, counter
, &mid16
, "ori", "t,r,i", reg
,
2797 freg
, (int) BFD_RELOC_LO16
);
2798 macro_build ((char *) NULL
, counter
, NULL
, "dsll", "d,w,<", reg
,
2802 if ((lo32
.X_add_number
& 0xffff) != 0)
2803 macro_build ((char *) NULL
, counter
, &lo32
, "ori", "t,r,i", reg
, freg
,
2804 (int) BFD_RELOC_LO16
);
2807 /* Load an address into a register. */
2810 load_address (counter
, reg
, ep
)
2817 if (ep
->X_op
!= O_constant
2818 && ep
->X_op
!= O_symbol
)
2820 as_bad ("expression too complex");
2821 ep
->X_op
= O_constant
;
2824 if (ep
->X_op
== O_constant
)
2826 load_register (counter
, reg
, ep
, 0);
2830 if (mips_pic
== NO_PIC
)
2832 /* If this is a reference to a GP relative symbol, we want
2833 addiu $reg,$gp,<sym> (BFD_RELOC_MIPS_GPREL)
2835 lui $reg,<sym> (BFD_RELOC_HI16_S)
2836 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
2837 If we have an addend, we always use the latter form. */
2838 if ((valueT
) ep
->X_add_number
>= MAX_GPREL_OFFSET
2839 || nopic_need_relax (ep
->X_add_symbol
))
2844 macro_build ((char *) NULL
, counter
, ep
,
2845 mips_isa
< 3 ? "addiu" : "daddiu",
2846 "t,r,j", reg
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
2847 p
= frag_var (rs_machine_dependent
, 8, 0,
2848 RELAX_ENCODE (4, 8, 0, 4, 0, mips_warn_about_macros
),
2849 ep
->X_add_symbol
, (long) 0, (char *) NULL
);
2851 macro_build_lui (p
, counter
, ep
, reg
);
2854 macro_build (p
, counter
, ep
,
2855 mips_isa
< 3 ? "addiu" : "daddiu",
2856 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
2858 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
2862 /* If this is a reference to an external symbol, we want
2863 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
2865 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
2867 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
2868 If there is a constant, it must be added in after. */
2869 ex
.X_add_number
= ep
->X_add_number
;
2870 ep
->X_add_number
= 0;
2872 macro_build ((char *) NULL
, counter
, ep
,
2873 mips_isa
< 3 ? "lw" : "ld",
2874 "t,o(b)", reg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
2875 macro_build ((char *) NULL
, counter
, (expressionS
*) NULL
, "nop", "");
2876 p
= frag_var (rs_machine_dependent
, 4, 0,
2877 RELAX_ENCODE (0, 4, -8, 0, 0, mips_warn_about_macros
),
2878 ep
->X_add_symbol
, (long) 0, (char *) NULL
);
2879 macro_build (p
, counter
, ep
,
2880 mips_isa
< 3 ? "addiu" : "daddiu",
2881 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
2882 if (ex
.X_add_number
!= 0)
2884 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
2885 as_bad ("PIC code offset overflow (max 16 signed bits)");
2886 ex
.X_op
= O_constant
;
2887 macro_build ((char *) NULL
, counter
, &ex
,
2888 mips_isa
< 3 ? "addiu" : "daddiu",
2889 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
2892 else if (mips_pic
== SVR4_PIC
)
2897 /* This is the large GOT case. If this is a reference to an
2898 external symbol, we want
2899 lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
2901 lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16)
2902 Otherwise, for a reference to a local symbol, we want
2903 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
2905 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
2906 If there is a constant, it must be added in after. */
2907 ex
.X_add_number
= ep
->X_add_number
;
2908 ep
->X_add_number
= 0;
2909 if (reg_needs_delay (GP
))
2914 macro_build ((char *) NULL
, counter
, ep
, "lui", "t,u", reg
,
2915 (int) BFD_RELOC_MIPS_GOT_HI16
);
2916 macro_build ((char *) NULL
, counter
, (expressionS
*) NULL
,
2917 mips_isa
< 3 ? "addu" : "daddu",
2918 "d,v,t", reg
, reg
, GP
);
2919 macro_build ((char *) NULL
, counter
, ep
,
2920 mips_isa
< 3 ? "lw" : "ld",
2921 "t,o(b)", reg
, (int) BFD_RELOC_MIPS_GOT_LO16
, reg
);
2922 p
= frag_var (rs_machine_dependent
, 12 + off
, 0,
2923 RELAX_ENCODE (12, 12 + off
, off
, 8 + off
, 0,
2924 mips_warn_about_macros
),
2925 ep
->X_add_symbol
, (long) 0, (char *) NULL
);
2928 /* We need a nop before loading from $gp. This special
2929 check is required because the lui which starts the main
2930 instruction stream does not refer to $gp, and so will not
2931 insert the nop which may be required. */
2932 macro_build (p
, counter
, (expressionS
*) NULL
, "nop", "");
2935 macro_build (p
, counter
, ep
,
2936 mips_isa
< 3 ? "lw" : "ld",
2937 "t,o(b)", reg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
2939 macro_build (p
, counter
, (expressionS
*) NULL
, "nop", "");
2941 macro_build (p
, counter
, ep
,
2942 mips_isa
< 3 ? "addiu" : "daddiu",
2943 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
2944 if (ex
.X_add_number
!= 0)
2946 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
2947 as_bad ("PIC code offset overflow (max 16 signed bits)");
2948 ex
.X_op
= O_constant
;
2949 macro_build ((char *) NULL
, counter
, &ex
,
2950 mips_isa
< 3 ? "addiu" : "daddiu",
2951 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
2954 else if (mips_pic
== EMBEDDED_PIC
)
2957 addiu $reg,$gp,<sym> (BFD_RELOC_MIPS_GPREL)
2959 macro_build ((char *) NULL
, counter
, ep
,
2960 mips_isa
< 3 ? "addiu" : "daddiu",
2961 "t,r,j", reg
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
2969 * This routine implements the seemingly endless macro or synthesized
2970 * instructions and addressing modes in the mips assembly language. Many
2971 * of these macros are simple and are similar to each other. These could
2972 * probably be handled by some kind of table or grammer aproach instead of
2973 * this verbose method. Others are not simple macros but are more like
2974 * optimizing code generation.
2975 * One interesting optimization is when several store macros appear
2976 * consecutivly that would load AT with the upper half of the same address.
2977 * The ensuing load upper instructions are ommited. This implies some kind
2978 * of global optimization. We currently only optimize within a single macro.
2979 * For many of the load and store macros if the address is specified as a
2980 * constant expression in the first 64k of memory (ie ld $2,0x4000c) we
2981 * first load register 'at' with zero and use it as the base register. The
2982 * mips assembler simply uses register $zero. Just one tiny optimization
2987 struct mips_cl_insn
*ip
;
2989 register int treg
, sreg
, dreg
, breg
;
3004 bfd_reloc_code_real_type r
;
3006 int hold_mips_optimize
;
3010 treg
= (ip
->insn_opcode
>> 16) & 0x1f;
3011 dreg
= (ip
->insn_opcode
>> 11) & 0x1f;
3012 sreg
= breg
= (ip
->insn_opcode
>> 21) & 0x1f;
3013 mask
= ip
->insn_mo
->mask
;
3015 expr1
.X_op
= O_constant
;
3016 expr1
.X_op_symbol
= NULL
;
3017 expr1
.X_add_symbol
= NULL
;
3018 expr1
.X_add_number
= 1;
3030 mips_emit_delays (true);
3032 mips_any_noreorder
= 1;
3034 expr1
.X_add_number
= 8;
3035 macro_build ((char *) NULL
, &icnt
, &expr1
, "bgez", "s,p", sreg
);
3037 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
3039 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
, sreg
, 0);
3040 macro_build ((char *) NULL
, &icnt
, NULL
,
3041 dbl
? "dsub" : "sub",
3042 "d,v,t", dreg
, 0, sreg
);
3065 if (imm_expr
.X_add_number
>= -0x8000 && imm_expr
.X_add_number
< 0x8000)
3067 macro_build ((char *) NULL
, &icnt
, &imm_expr
, s
, "t,r,j", treg
, sreg
,
3068 (int) BFD_RELOC_LO16
);
3071 load_register (&icnt
, AT
, &imm_expr
, dbl
);
3072 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "d,v,t", treg
, sreg
, AT
);
3091 if (imm_expr
.X_add_number
>= 0 && imm_expr
.X_add_number
< 0x10000)
3093 if (mask
!= M_NOR_I
)
3094 macro_build ((char *) NULL
, &icnt
, &imm_expr
, s
, "t,r,i", treg
,
3095 sreg
, (int) BFD_RELOC_LO16
);
3098 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "ori", "t,r,i",
3099 treg
, sreg
, (int) BFD_RELOC_LO16
);
3100 macro_build ((char *) NULL
, &icnt
, NULL
, "nor", "d,v,t",
3106 load_register (&icnt
, AT
, &imm_expr
, 0);
3107 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "d,v,t", treg
, sreg
, AT
);
3124 if (imm_expr
.X_add_number
== 0)
3126 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "s,t,p", sreg
,
3130 load_register (&icnt
, AT
, &imm_expr
, 0);
3131 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "s,t,p", sreg
, AT
);
3139 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3140 likely
? "bgezl" : "bgez",
3146 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3147 likely
? "blezl" : "blez",
3151 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", AT
, sreg
, treg
);
3152 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3153 likely
? "beql" : "beq",
3160 /* check for > max integer */
3161 maxnum
= 0x7fffffff;
3169 if (imm_expr
.X_add_number
>= maxnum
3170 && (mips_isa
< 3 || sizeof (maxnum
) > 4))
3173 /* result is always false */
3176 as_warn ("Branch %s is always false (nop)", ip
->insn_mo
->name
);
3177 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
3181 as_warn ("Branch likely %s is always false", ip
->insn_mo
->name
);
3182 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "bnel",
3187 imm_expr
.X_add_number
++;
3191 if (mask
== M_BGEL_I
)
3193 if (imm_expr
.X_add_number
== 0)
3195 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3196 likely
? "bgezl" : "bgez",
3200 if (imm_expr
.X_add_number
== 1)
3202 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3203 likely
? "bgtzl" : "bgtz",
3207 maxnum
= 0x7fffffff;
3215 maxnum
= - maxnum
- 1;
3216 if (imm_expr
.X_add_number
<= maxnum
3217 && (mips_isa
< 3 || sizeof (maxnum
) > 4))
3220 /* result is always true */
3221 as_warn ("Branch %s is always true", ip
->insn_mo
->name
);
3222 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "b", "p");
3225 set_at (&icnt
, sreg
, 0);
3226 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3227 likely
? "beql" : "beq",
3238 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3239 likely
? "beql" : "beq",
3243 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", AT
, sreg
,
3245 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3246 likely
? "beql" : "beq",
3253 if (sreg
== 0 || imm_expr
.X_add_number
== -1)
3255 imm_expr
.X_add_number
++;
3259 if (mask
== M_BGEUL_I
)
3261 if (imm_expr
.X_add_number
== 0)
3263 if (imm_expr
.X_add_number
== 1)
3265 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3266 likely
? "bnel" : "bne",
3270 set_at (&icnt
, sreg
, 1);
3271 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3272 likely
? "beql" : "beq",
3281 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3282 likely
? "bgtzl" : "bgtz",
3288 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3289 likely
? "bltzl" : "bltz",
3293 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", AT
, treg
, sreg
);
3294 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3295 likely
? "bnel" : "bne",
3304 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3305 likely
? "bnel" : "bne",
3311 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", AT
, treg
,
3313 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3314 likely
? "bnel" : "bne",
3323 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3324 likely
? "blezl" : "blez",
3330 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3331 likely
? "bgezl" : "bgez",
3335 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", AT
, treg
, sreg
);
3336 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3337 likely
? "beql" : "beq",
3344 maxnum
= 0x7fffffff;
3352 if (imm_expr
.X_add_number
>= maxnum
3353 && (mips_isa
< 3 || sizeof (maxnum
) > 4))
3355 imm_expr
.X_add_number
++;
3359 if (mask
== M_BLTL_I
)
3361 if (imm_expr
.X_add_number
== 0)
3363 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3364 likely
? "bltzl" : "bltz",
3368 if (imm_expr
.X_add_number
== 1)
3370 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3371 likely
? "blezl" : "blez",
3375 set_at (&icnt
, sreg
, 0);
3376 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3377 likely
? "bnel" : "bne",
3386 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3387 likely
? "beql" : "beq",
3393 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", AT
, treg
,
3395 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3396 likely
? "beql" : "beq",
3403 if (sreg
== 0 || imm_expr
.X_add_number
== -1)
3405 imm_expr
.X_add_number
++;
3409 if (mask
== M_BLTUL_I
)
3411 if (imm_expr
.X_add_number
== 0)
3413 if (imm_expr
.X_add_number
== 1)
3415 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3416 likely
? "beql" : "beq",
3420 set_at (&icnt
, sreg
, 1);
3421 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3422 likely
? "bnel" : "bne",
3431 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3432 likely
? "bltzl" : "bltz",
3438 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3439 likely
? "bgtzl" : "bgtz",
3443 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", AT
, sreg
, treg
);
3444 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3445 likely
? "bnel" : "bne",
3456 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3457 likely
? "bnel" : "bne",
3461 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", AT
, sreg
,
3463 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3464 likely
? "bnel" : "bne",
3480 as_warn ("Divide by zero.");
3482 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", 0, 0);
3484 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 7);
3488 mips_emit_delays (true);
3490 mips_any_noreorder
= 1;
3491 macro_build ((char *) NULL
, &icnt
, NULL
,
3492 dbl
? "ddiv" : "div",
3493 "z,s,t", sreg
, treg
);
3495 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", treg
, 0);
3498 expr1
.X_add_number
= 8;
3499 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", treg
, 0);
3500 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
3501 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 7);
3503 expr1
.X_add_number
= -1;
3504 macro_build ((char *) NULL
, &icnt
, &expr1
,
3505 dbl
? "daddiu" : "addiu",
3506 "t,r,j", AT
, 0, (int) BFD_RELOC_LO16
);
3507 expr1
.X_add_number
= mips_trap
? (dbl
? 12 : 8) : (dbl
? 20 : 16);
3508 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", treg
, AT
);
3511 expr1
.X_add_number
= 1;
3512 macro_build ((char *) NULL
, &icnt
, &expr1
, "daddiu", "t,r,j", AT
, 0,
3513 (int) BFD_RELOC_LO16
);
3514 macro_build ((char *) NULL
, &icnt
, NULL
, "dsll32", "d,w,<", AT
, AT
,
3519 expr1
.X_add_number
= 0x80000000;
3520 macro_build ((char *) NULL
, &icnt
, &expr1
, "lui", "t,u", AT
,
3521 (int) BFD_RELOC_HI16
);
3524 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", sreg
, AT
);
3527 expr1
.X_add_number
= 8;
3528 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", sreg
, AT
);
3529 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
3530 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 6);
3533 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d", dreg
);
3572 if (imm_expr
.X_add_number
== 0)
3574 as_warn ("Divide by zero.");
3576 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", 0, 0);
3578 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 7);
3581 if (imm_expr
.X_add_number
== 1)
3583 if (strcmp (s2
, "mflo") == 0)
3584 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
,
3587 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
, 0);
3590 if (imm_expr
.X_add_number
== -1
3591 && s
[strlen (s
) - 1] != 'u')
3593 if (strcmp (s2
, "mflo") == 0)
3596 macro_build ((char *) NULL
, &icnt
, NULL
, "dneg", "d,w", dreg
,
3599 macro_build ((char *) NULL
, &icnt
, NULL
, "neg", "d,w", dreg
,
3603 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
, 0);
3607 load_register (&icnt
, AT
, &imm_expr
, dbl
);
3608 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "z,s,t", sreg
, AT
);
3609 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "d", dreg
);
3628 mips_emit_delays (true);
3630 mips_any_noreorder
= 1;
3631 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "z,s,t", sreg
, treg
);
3633 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", treg
, 0);
3636 expr1
.X_add_number
= 8;
3637 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", treg
, 0);
3638 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
3639 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 7);
3642 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "d", dreg
);
3648 /* Load the address of a symbol into a register. If breg is not
3649 zero, we then add a base register to it. */
3651 /* When generating embedded PIC code, we permit expressions of
3654 where bar is an address in the .text section. These are used
3655 when getting the addresses of functions. We don't permit
3656 X_add_number to be non-zero, because if the symbol is
3657 external the relaxing code needs to know that any addend is
3658 purely the offset to X_op_symbol. */
3659 if (mips_pic
== EMBEDDED_PIC
3660 && offset_expr
.X_op
== O_subtract
3661 && now_seg
== text_section
3662 && (offset_expr
.X_op_symbol
->sy_value
.X_op
== O_constant
3663 ? S_GET_SEGMENT (offset_expr
.X_op_symbol
) == text_section
3664 : (offset_expr
.X_op_symbol
->sy_value
.X_op
== O_symbol
3665 && (S_GET_SEGMENT (offset_expr
.X_op_symbol
3666 ->sy_value
.X_add_symbol
)
3669 && offset_expr
.X_add_number
== 0)
3671 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
3672 treg
, (int) BFD_RELOC_PCREL_HI16_S
);
3673 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3674 mips_isa
< 3 ? "addiu" : "daddiu",
3675 "t,r,j", treg
, treg
, (int) BFD_RELOC_PCREL_LO16
);
3679 if (offset_expr
.X_op
!= O_symbol
3680 && offset_expr
.X_op
!= O_constant
)
3682 as_bad ("expression too complex");
3683 offset_expr
.X_op
= O_constant
;
3697 if (offset_expr
.X_op
== O_constant
)
3698 load_register (&icnt
, tempreg
, &offset_expr
, dbl
);
3699 else if (mips_pic
== NO_PIC
)
3701 /* If this is a reference to an GP relative symbol, we want
3702 addiu $tempreg,$gp,<sym> (BFD_RELOC_MIPS_GPREL)
3704 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
3705 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
3706 If we have a constant, we need two instructions anyhow,
3707 so we may as well always use the latter form. */
3708 if ((valueT
) offset_expr
.X_add_number
>= MAX_GPREL_OFFSET
3709 || nopic_need_relax (offset_expr
.X_add_symbol
))
3714 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3715 mips_isa
< 3 ? "addiu" : "daddiu",
3716 "t,r,j", tempreg
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
3717 p
= frag_var (rs_machine_dependent
, 8, 0,
3718 RELAX_ENCODE (4, 8, 0, 4, 0,
3719 mips_warn_about_macros
),
3720 offset_expr
.X_add_symbol
, (long) 0,
3723 macro_build_lui (p
, &icnt
, &offset_expr
, tempreg
);
3726 macro_build (p
, &icnt
, &offset_expr
,
3727 mips_isa
< 3 ? "addiu" : "daddiu",
3728 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
3730 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
3732 /* If this is a reference to an external symbol, and there
3733 is no constant, we want
3734 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3735 For a local symbol, we want
3736 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3738 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
3740 If we have a small constant, and this is a reference to
3741 an external symbol, we want
3742 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3744 addiu $tempreg,$tempreg,<constant>
3745 For a local symbol, we want the same instruction
3746 sequence, but we output a BFD_RELOC_LO16 reloc on the
3749 If we have a large constant, and this is a reference to
3750 an external symbol, we want
3751 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3752 lui $at,<hiconstant>
3753 addiu $at,$at,<loconstant>
3754 addu $tempreg,$tempreg,$at
3755 For a local symbol, we want the same instruction
3756 sequence, but we output a BFD_RELOC_LO16 reloc on the
3757 addiu instruction. */
3758 expr1
.X_add_number
= offset_expr
.X_add_number
;
3759 offset_expr
.X_add_number
= 0;
3761 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3763 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
3764 if (expr1
.X_add_number
== 0)
3772 /* We're going to put in an addu instruction using
3773 tempreg, so we may as well insert the nop right
3775 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3779 p
= frag_var (rs_machine_dependent
, 8 - off
, 0,
3780 RELAX_ENCODE (0, 8 - off
, -4 - off
, 4 - off
, 0,
3782 ? mips_warn_about_macros
3784 offset_expr
.X_add_symbol
, (long) 0,
3788 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
3791 macro_build (p
, &icnt
, &expr1
,
3792 mips_isa
< 3 ? "addiu" : "daddiu",
3793 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
3794 /* FIXME: If breg == 0, and the next instruction uses
3795 $tempreg, then if this variant case is used an extra
3796 nop will be generated. */
3798 else if (expr1
.X_add_number
>= -0x8000
3799 && expr1
.X_add_number
< 0x8000)
3801 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3803 macro_build ((char *) NULL
, &icnt
, &expr1
,
3804 mips_isa
< 3 ? "addiu" : "daddiu",
3805 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
3806 (void) frag_var (rs_machine_dependent
, 0, 0,
3807 RELAX_ENCODE (0, 0, -12, -4, 0, 0),
3808 offset_expr
.X_add_symbol
, (long) 0,
3815 /* If we are going to add in a base register, and the
3816 target register and the base register are the same,
3817 then we are using AT as a temporary register. Since
3818 we want to load the constant into AT, we add our
3819 current AT (from the global offset table) and the
3820 register into the register now, and pretend we were
3821 not using a base register. */
3826 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3828 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3829 mips_isa
< 3 ? "addu" : "daddu",
3830 "d,v,t", treg
, AT
, breg
);
3836 /* Set mips_optimize around the lui instruction to avoid
3837 inserting an unnecessary nop after the lw. */
3838 hold_mips_optimize
= mips_optimize
;
3840 macro_build_lui ((char *) NULL
, &icnt
, &expr1
, AT
);
3841 mips_optimize
= hold_mips_optimize
;
3843 macro_build ((char *) NULL
, &icnt
, &expr1
,
3844 mips_isa
< 3 ? "addiu" : "daddiu",
3845 "t,r,j", AT
, AT
, (int) BFD_RELOC_LO16
);
3846 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3847 mips_isa
< 3 ? "addu" : "daddu",
3848 "d,v,t", tempreg
, tempreg
, AT
);
3849 (void) frag_var (rs_machine_dependent
, 0, 0,
3850 RELAX_ENCODE (0, 0, -16 + off1
, -8, 0, 0),
3851 offset_expr
.X_add_symbol
, (long) 0,
3856 else if (mips_pic
== SVR4_PIC
)
3860 /* This is the large GOT case. If this is a reference to an
3861 external symbol, and there is no constant, we want
3862 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
3863 addu $tempreg,$tempreg,$gp
3864 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
3865 For a local symbol, we want
3866 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3868 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
3870 If we have a small constant, and this is a reference to
3871 an external symbol, we want
3872 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
3873 addu $tempreg,$tempreg,$gp
3874 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
3876 addiu $tempreg,$tempreg,<constant>
3877 For a local symbol, we want
3878 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3880 addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16)
3882 If we have a large constant, and this is a reference to
3883 an external symbol, we want
3884 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
3885 addu $tempreg,$tempreg,$gp
3886 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
3887 lui $at,<hiconstant>
3888 addiu $at,$at,<loconstant>
3889 addu $tempreg,$tempreg,$at
3890 For a local symbol, we want
3891 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3892 lui $at,<hiconstant>
3893 addiu $at,$at,<loconstant> (BFD_RELOC_LO16)
3894 addu $tempreg,$tempreg,$at
3896 expr1
.X_add_number
= offset_expr
.X_add_number
;
3897 offset_expr
.X_add_number
= 0;
3899 if (reg_needs_delay (GP
))
3903 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
3904 tempreg
, (int) BFD_RELOC_MIPS_GOT_HI16
);
3905 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3906 mips_isa
< 3 ? "addu" : "daddu",
3907 "d,v,t", tempreg
, tempreg
, GP
);
3908 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3910 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT_LO16
,
3912 if (expr1
.X_add_number
== 0)
3920 /* We're going to put in an addu instruction using
3921 tempreg, so we may as well insert the nop right
3923 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3928 p
= frag_var (rs_machine_dependent
, 12 + gpdel
, 0,
3929 RELAX_ENCODE (12 + off
, 12 + gpdel
, gpdel
,
3932 ? mips_warn_about_macros
3934 offset_expr
.X_add_symbol
, (long) 0,
3937 else if (expr1
.X_add_number
>= -0x8000
3938 && expr1
.X_add_number
< 0x8000)
3940 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3942 macro_build ((char *) NULL
, &icnt
, &expr1
,
3943 mips_isa
< 3 ? "addiu" : "daddiu",
3944 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
3946 p
= frag_var (rs_machine_dependent
, 12 + gpdel
, 0,
3947 RELAX_ENCODE (20, 12 + gpdel
, gpdel
, 8 + gpdel
, 0,
3949 ? mips_warn_about_macros
3951 offset_expr
.X_add_symbol
, (long) 0,
3958 /* If we are going to add in a base register, and the
3959 target register and the base register are the same,
3960 then we are using AT as a temporary register. Since
3961 we want to load the constant into AT, we add our
3962 current AT (from the global offset table) and the
3963 register into the register now, and pretend we were
3964 not using a base register. */
3972 assert (tempreg
== AT
);
3973 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3975 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3976 mips_isa
< 3 ? "addu" : "daddu",
3977 "d,v,t", treg
, AT
, breg
);
3982 /* Set mips_optimize around the lui instruction to avoid
3983 inserting an unnecessary nop after the lw. */
3984 hold_mips_optimize
= mips_optimize
;
3986 macro_build_lui ((char *) NULL
, &icnt
, &expr1
, AT
);
3987 mips_optimize
= hold_mips_optimize
;
3989 macro_build ((char *) NULL
, &icnt
, &expr1
,
3990 mips_isa
< 3 ? "addiu" : "daddiu",
3991 "t,r,j", AT
, AT
, (int) BFD_RELOC_LO16
);
3992 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3993 mips_isa
< 3 ? "addu" : "daddu",
3994 "d,v,t", dreg
, dreg
, AT
);
3996 p
= frag_var (rs_machine_dependent
, 16 + gpdel
+ adj
, 0,
3997 RELAX_ENCODE (24 + adj
, 16 + gpdel
+ adj
, gpdel
,
4000 ? mips_warn_about_macros
4002 offset_expr
.X_add_symbol
, (long) 0,
4010 /* This is needed because this instruction uses $gp, but
4011 the first instruction on the main stream does not. */
4012 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4015 macro_build (p
, &icnt
, &offset_expr
,
4017 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
4019 if (expr1
.X_add_number
>= -0x8000
4020 && expr1
.X_add_number
< 0x8000)
4022 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4024 macro_build (p
, &icnt
, &expr1
,
4025 mips_isa
< 3 ? "addiu" : "daddiu",
4026 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
4027 /* FIXME: If add_number is 0, and there was no base
4028 register, the external symbol case ended with a load,
4029 so if the symbol turns out to not be external, and
4030 the next instruction uses tempreg, an unnecessary nop
4031 will be inserted. */
4037 /* We must add in the base register now, as in the
4038 external symbol case. */
4039 assert (tempreg
== AT
);
4040 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4042 macro_build (p
, &icnt
, (expressionS
*) NULL
,
4043 mips_isa
< 3 ? "addu" : "daddu",
4044 "d,v,t", treg
, AT
, breg
);
4047 /* We set breg to 0 because we have arranged to add
4048 it in in both cases. */
4052 macro_build_lui (p
, &icnt
, &expr1
, AT
);
4054 macro_build (p
, &icnt
, &expr1
,
4055 mips_isa
< 3 ? "addiu" : "daddiu",
4056 "t,r,j", AT
, AT
, (int) BFD_RELOC_LO16
);
4058 macro_build (p
, &icnt
, (expressionS
*) NULL
,
4059 mips_isa
< 3 ? "addu" : "daddu",
4060 "d,v,t", tempreg
, tempreg
, AT
);
4064 else if (mips_pic
== EMBEDDED_PIC
)
4067 addiu $tempreg,$gp,<sym> (BFD_RELOC_MIPS_GPREL)
4069 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4070 mips_isa
< 3 ? "addiu" : "daddiu",
4071 "t,r,j", tempreg
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
4077 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4078 mips_isa
< 3 ? "addu" : "daddu",
4079 "d,v,t", treg
, tempreg
, breg
);
4087 /* The j instruction may not be used in PIC code, since it
4088 requires an absolute address. We convert it to a b
4090 if (mips_pic
== NO_PIC
)
4091 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "j", "a");
4093 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "b", "p");
4096 /* The jal instructions must be handled as macros because when
4097 generating PIC code they expand to multi-instruction
4098 sequences. Normally they are simple instructions. */
4103 if (mips_pic
== NO_PIC
4104 || mips_pic
== EMBEDDED_PIC
)
4105 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "jalr",
4107 else if (mips_pic
== SVR4_PIC
)
4109 if (sreg
!= PIC_CALL_REG
)
4110 as_warn ("MIPS PIC call to register other than $25");
4112 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "jalr",
4114 if (mips_cprestore_offset
< 0)
4115 as_warn ("No .cprestore pseudo-op used in PIC code");
4118 expr1
.X_add_number
= mips_cprestore_offset
;
4119 macro_build ((char *) NULL
, &icnt
, &expr1
,
4120 mips_isa
< 3 ? "lw" : "ld",
4121 "t,o(b)", GP
, (int) BFD_RELOC_LO16
, mips_frame_reg
);
4130 if (mips_pic
== NO_PIC
)
4131 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "jal", "a");
4132 else if (mips_pic
== SVR4_PIC
)
4134 /* If this is a reference to an external symbol, and we are
4135 using a small GOT, we want
4136 lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
4140 lw $gp,cprestore($sp)
4141 The cprestore value is set using the .cprestore
4142 pseudo-op. If we are using a big GOT, we want
4143 lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16)
4145 lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16)
4149 lw $gp,cprestore($sp)
4150 If the symbol is not external, we want
4151 lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4153 addiu $25,$25,<sym> (BFD_RELOC_LO16)
4156 lw $gp,cprestore($sp) */
4160 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4161 mips_isa
< 3 ? "lw" : "ld",
4162 "t,o(b)", PIC_CALL_REG
,
4163 (int) BFD_RELOC_MIPS_CALL16
, GP
);
4164 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4166 p
= frag_var (rs_machine_dependent
, 4, 0,
4167 RELAX_ENCODE (0, 4, -8, 0, 0, 0),
4168 offset_expr
.X_add_symbol
, (long) 0, (char *) NULL
);
4174 if (reg_needs_delay (GP
))
4178 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
4179 PIC_CALL_REG
, (int) BFD_RELOC_MIPS_CALL_HI16
);
4180 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4181 mips_isa
< 3 ? "addu" : "daddu",
4182 "d,v,t", PIC_CALL_REG
, PIC_CALL_REG
, GP
);
4183 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4184 mips_isa
< 3 ? "lw" : "ld",
4185 "t,o(b)", PIC_CALL_REG
,
4186 (int) BFD_RELOC_MIPS_CALL_LO16
, PIC_CALL_REG
);
4187 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4189 p
= frag_var (rs_machine_dependent
, 12 + gpdel
, 0,
4190 RELAX_ENCODE (16, 12 + gpdel
, gpdel
, 8 + gpdel
,
4192 offset_expr
.X_add_symbol
, (long) 0, (char *) NULL
);
4195 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4198 macro_build (p
, &icnt
, &offset_expr
,
4199 mips_isa
< 3 ? "lw" : "ld",
4200 "t,o(b)", PIC_CALL_REG
,
4201 (int) BFD_RELOC_MIPS_GOT16
, GP
);
4203 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4206 macro_build (p
, &icnt
, &offset_expr
,
4207 mips_isa
< 3 ? "addiu" : "daddiu",
4208 "t,r,j", PIC_CALL_REG
, PIC_CALL_REG
,
4209 (int) BFD_RELOC_LO16
);
4210 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4211 "jalr", "s", PIC_CALL_REG
);
4212 if (mips_cprestore_offset
< 0)
4213 as_warn ("No .cprestore pseudo-op used in PIC code");
4217 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4219 expr1
.X_add_number
= mips_cprestore_offset
;
4220 macro_build ((char *) NULL
, &icnt
, &expr1
,
4221 mips_isa
< 3 ? "lw" : "ld",
4222 "t,o(b)", GP
, (int) BFD_RELOC_LO16
,
4226 else if (mips_pic
== EMBEDDED_PIC
)
4228 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "bal", "p");
4229 /* The linker may expand the call to a longer sequence which
4230 uses $at, so we must break rather than return. */
4306 if (breg
== treg
|| coproc
|| lr
)
4375 if (mask
== M_LWC1_AB
4376 || mask
== M_SWC1_AB
4377 || mask
== M_LDC1_AB
4378 || mask
== M_SDC1_AB
4387 if (offset_expr
.X_op
!= O_constant
4388 && offset_expr
.X_op
!= O_symbol
)
4390 as_bad ("expression too complex");
4391 offset_expr
.X_op
= O_constant
;
4394 /* A constant expression in PIC code can be handled just as it
4395 is in non PIC code. */
4396 if (mips_pic
== NO_PIC
4397 || offset_expr
.X_op
== O_constant
)
4399 /* If this is a reference to a GP relative symbol, and there
4400 is no base register, we want
4401 <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL)
4402 Otherwise, if there is no base register, we want
4403 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
4404 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
4405 If we have a constant, we need two instructions anyhow,
4406 so we always use the latter form.
4408 If we have a base register, and this is a reference to a
4409 GP relative symbol, we want
4410 addu $tempreg,$breg,$gp
4411 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GPREL)
4413 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
4414 addu $tempreg,$tempreg,$breg
4415 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
4416 With a constant we always use the latter case. */
4419 if ((valueT
) offset_expr
.X_add_number
>= MAX_GPREL_OFFSET
4420 || nopic_need_relax (offset_expr
.X_add_symbol
))
4425 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
4426 treg
, (int) BFD_RELOC_MIPS_GPREL
, GP
);
4427 p
= frag_var (rs_machine_dependent
, 8, 0,
4428 RELAX_ENCODE (4, 8, 0, 4, 0,
4429 (mips_warn_about_macros
4430 || (used_at
&& mips_noat
))),
4431 offset_expr
.X_add_symbol
, (long) 0,
4435 macro_build_lui (p
, &icnt
, &offset_expr
, tempreg
);
4438 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
, treg
,
4439 (int) BFD_RELOC_LO16
, tempreg
);
4443 if ((valueT
) offset_expr
.X_add_number
>= MAX_GPREL_OFFSET
4444 || nopic_need_relax (offset_expr
.X_add_symbol
))
4449 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4450 mips_isa
< 3 ? "addu" : "daddu",
4451 "d,v,t", tempreg
, breg
, GP
);
4452 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
4453 treg
, (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
4454 p
= frag_var (rs_machine_dependent
, 12, 0,
4455 RELAX_ENCODE (8, 12, 0, 8, 0, 0),
4456 offset_expr
.X_add_symbol
, (long) 0,
4459 macro_build_lui (p
, &icnt
, &offset_expr
, tempreg
);
4462 macro_build (p
, &icnt
, (expressionS
*) NULL
,
4463 mips_isa
< 3 ? "addu" : "daddu",
4464 "d,v,t", tempreg
, tempreg
, breg
);
4467 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
, treg
,
4468 (int) BFD_RELOC_LO16
, tempreg
);
4471 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
4473 /* If this is a reference to an external symbol, we want
4474 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4476 <op> $treg,0($tempreg)
4478 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4480 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
4481 <op> $treg,0($tempreg)
4482 If there is a base register, we add it to $tempreg before
4483 the <op>. If there is a constant, we stick it in the
4484 <op> instruction. We don't handle constants larger than
4485 16 bits, because we have no way to load the upper 16 bits
4486 (actually, we could handle them for the subset of cases
4487 in which we are not using $at). */
4488 assert (offset_expr
.X_op
== O_symbol
);
4489 expr1
.X_add_number
= offset_expr
.X_add_number
;
4490 offset_expr
.X_add_number
= 0;
4491 if (expr1
.X_add_number
< -0x8000
4492 || expr1
.X_add_number
>= 0x8000)
4493 as_bad ("PIC code offset overflow (max 16 signed bits)");
4495 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4496 mips_isa
< 3 ? "lw" : "ld",
4497 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
4498 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
4499 p
= frag_var (rs_machine_dependent
, 4, 0,
4500 RELAX_ENCODE (0, 4, -8, 0, 0, 0),
4501 offset_expr
.X_add_symbol
, (long) 0,
4503 macro_build (p
, &icnt
, &offset_expr
,
4504 mips_isa
< 3 ? "addiu" : "daddiu",
4505 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
4507 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4508 mips_isa
< 3 ? "addu" : "daddu",
4509 "d,v,t", tempreg
, tempreg
, breg
);
4510 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
, treg
,
4511 (int) BFD_RELOC_LO16
, tempreg
);
4513 else if (mips_pic
== SVR4_PIC
)
4517 /* If this is a reference to an external symbol, we want
4518 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
4519 addu $tempreg,$tempreg,$gp
4520 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
4521 <op> $treg,0($tempreg)
4523 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4525 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
4526 <op> $treg,0($tempreg)
4527 If there is a base register, we add it to $tempreg before
4528 the <op>. If there is a constant, we stick it in the
4529 <op> instruction. We don't handle constants larger than
4530 16 bits, because we have no way to load the upper 16 bits
4531 (actually, we could handle them for the subset of cases
4532 in which we are not using $at). */
4533 assert (offset_expr
.X_op
== O_symbol
);
4534 expr1
.X_add_number
= offset_expr
.X_add_number
;
4535 offset_expr
.X_add_number
= 0;
4536 if (expr1
.X_add_number
< -0x8000
4537 || expr1
.X_add_number
>= 0x8000)
4538 as_bad ("PIC code offset overflow (max 16 signed bits)");
4539 if (reg_needs_delay (GP
))
4544 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
4545 tempreg
, (int) BFD_RELOC_MIPS_GOT_HI16
);
4546 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4547 mips_isa
< 3 ? "addu" : "daddu",
4548 "d,v,t", tempreg
, tempreg
, GP
);
4549 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4550 mips_isa
< 3 ? "lw" : "ld",
4551 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT_LO16
,
4553 p
= frag_var (rs_machine_dependent
, 12 + gpdel
, 0,
4554 RELAX_ENCODE (12, 12 + gpdel
, gpdel
, 8 + gpdel
, 0, 0),
4555 offset_expr
.X_add_symbol
, (long) 0, (char *) NULL
);
4558 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4561 macro_build (p
, &icnt
, &offset_expr
,
4562 mips_isa
< 3 ? "lw" : "ld",
4563 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
4565 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4567 macro_build (p
, &icnt
, &offset_expr
,
4568 mips_isa
< 3 ? "addiu" : "daddiu",
4569 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
4571 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4572 mips_isa
< 3 ? "addu" : "daddu",
4573 "d,v,t", tempreg
, tempreg
, breg
);
4574 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
, treg
,
4575 (int) BFD_RELOC_LO16
, tempreg
);
4577 else if (mips_pic
== EMBEDDED_PIC
)
4579 /* If there is no base register, we want
4580 <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL)
4581 If there is a base register, we want
4582 addu $tempreg,$breg,$gp
4583 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GPREL)
4585 assert (offset_expr
.X_op
== O_symbol
);
4588 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
4589 treg
, (int) BFD_RELOC_MIPS_GPREL
, GP
);
4594 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4595 mips_isa
< 3 ? "addu" : "daddu",
4596 "d,v,t", tempreg
, breg
, GP
);
4597 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
4598 treg
, (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
4611 load_register (&icnt
, treg
, &imm_expr
, 0);
4615 load_register (&icnt
, treg
, &imm_expr
, 1);
4619 if (imm_expr
.X_op
== O_constant
)
4621 load_register (&icnt
, AT
, &imm_expr
, 0);
4622 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4623 "mtc1", "t,G", AT
, treg
);
4628 assert (offset_expr
.X_op
== O_symbol
4629 && strcmp (segment_name (S_GET_SEGMENT
4630 (offset_expr
.X_add_symbol
)),
4632 && offset_expr
.X_add_number
== 0);
4633 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lwc1", "T,o(b)",
4634 treg
, (int) BFD_RELOC_MIPS_LITERAL
, GP
);
4639 /* We know that sym is in the .rdata section. First we get the
4640 upper 16 bits of the address. */
4641 if (mips_pic
== NO_PIC
)
4643 /* FIXME: This won't work for a 64 bit address. */
4644 macro_build_lui ((char *) NULL
, &icnt
, &offset_expr
, AT
);
4646 else if (mips_pic
== SVR4_PIC
)
4648 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4649 mips_isa
< 3 ? "lw" : "ld",
4650 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
4652 else if (mips_pic
== EMBEDDED_PIC
)
4654 /* For embedded PIC we pick up the entire address off $gp in
4655 a single instruction. */
4656 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4657 mips_isa
< 3 ? "addiu" : "daddiu",
4658 "t,r,j", AT
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
4659 offset_expr
.X_op
= O_constant
;
4660 offset_expr
.X_add_number
= 0;
4665 /* Now we load the register(s). */
4667 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "ld", "t,o(b)",
4668 treg
, (int) BFD_RELOC_LO16
, AT
);
4671 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lw", "t,o(b)",
4672 treg
, (int) BFD_RELOC_LO16
, AT
);
4675 /* FIXME: How in the world do we deal with the possible
4677 offset_expr
.X_add_number
+= 4;
4678 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lw", "t,o(b)",
4679 treg
+ 1, (int) BFD_RELOC_LO16
, AT
);
4683 /* To avoid confusion in tc_gen_reloc, we must ensure that this
4684 does not become a variant frag. */
4685 frag_wane (frag_now
);
4691 assert (offset_expr
.X_op
== O_symbol
4692 && offset_expr
.X_add_number
== 0);
4693 s
= segment_name (S_GET_SEGMENT (offset_expr
.X_add_symbol
));
4694 if (strcmp (s
, ".lit8") == 0)
4698 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "ldc1",
4699 "T,o(b)", treg
, (int) BFD_RELOC_MIPS_LITERAL
, GP
);
4703 r
= BFD_RELOC_MIPS_LITERAL
;
4708 assert (strcmp (s
, RDATA_SECTION_NAME
) == 0);
4709 if (mips_pic
== SVR4_PIC
)
4710 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4711 mips_isa
< 3 ? "lw" : "ld",
4712 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
4715 /* FIXME: This won't work for a 64 bit address. */
4716 macro_build_lui ((char *) NULL
, &icnt
, &offset_expr
, AT
);
4721 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "ldc1",
4722 "T,o(b)", treg
, (int) BFD_RELOC_LO16
, AT
);
4724 /* To avoid confusion in tc_gen_reloc, we must ensure
4725 that this does not become a variant frag. */
4726 frag_wane (frag_now
);
4737 /* Even on a big endian machine $fn comes before $fn+1. We have
4738 to adjust when loading from memory. */
4741 assert (mips_isa
< 2);
4742 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lwc1", "T,o(b)",
4743 target_big_endian
? treg
+ 1 : treg
,
4745 /* FIXME: A possible overflow which I don't know how to deal
4747 offset_expr
.X_add_number
+= 4;
4748 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lwc1", "T,o(b)",
4749 target_big_endian
? treg
: treg
+ 1,
4752 /* To avoid confusion in tc_gen_reloc, we must ensure that this
4753 does not become a variant frag. */
4754 frag_wane (frag_now
);
4763 * The MIPS assembler seems to check for X_add_number not
4764 * being double aligned and generating:
4767 * addiu at,at,%lo(foo+1)
4770 * But, the resulting address is the same after relocation so why
4771 * generate the extra instruction?
4818 if (offset_expr
.X_op
!= O_symbol
4819 && offset_expr
.X_op
!= O_constant
)
4821 as_bad ("expression too complex");
4822 offset_expr
.X_op
= O_constant
;
4825 /* Even on a big endian machine $fn comes before $fn+1. We have
4826 to adjust when loading from memory. We set coproc if we must
4827 load $fn+1 first. */
4828 if (! target_big_endian
)
4831 if (mips_pic
== NO_PIC
4832 || offset_expr
.X_op
== O_constant
)
4834 /* If this is a reference to a GP relative symbol, we want
4835 <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL)
4836 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_MIPS_GPREL)
4837 If we have a base register, we use this
4839 <op> $treg,<sym>($at) (BFD_RELOC_MIPS_GPREL)
4840 <op> $treg+1,<sym>+4($at) (BFD_RELOC_MIPS_GPREL)
4841 If this is not a GP relative symbol, we want
4842 lui $at,<sym> (BFD_RELOC_HI16_S)
4843 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
4844 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
4845 If there is a base register, we add it to $at after the
4846 lui instruction. If there is a constant, we always use
4848 if ((valueT
) offset_expr
.X_add_number
>= MAX_GPREL_OFFSET
4849 || nopic_need_relax (offset_expr
.X_add_symbol
))
4868 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4869 mips_isa
< 3 ? "addu" : "daddu",
4870 "d,v,t", AT
, breg
, GP
);
4876 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
4877 coproc
? treg
+ 1 : treg
,
4878 (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
4879 offset_expr
.X_add_number
+= 4;
4881 /* Set mips_optimize to 2 to avoid inserting an
4883 hold_mips_optimize
= mips_optimize
;
4885 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
4886 coproc
? treg
: treg
+ 1,
4887 (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
4888 mips_optimize
= hold_mips_optimize
;
4890 p
= frag_var (rs_machine_dependent
, 12 + off
, 0,
4891 RELAX_ENCODE (8 + off
, 12 + off
, 0, 4 + off
, 1,
4892 used_at
&& mips_noat
),
4893 offset_expr
.X_add_symbol
, (long) 0,
4896 /* We just generated two relocs. When tc_gen_reloc
4897 handles this case, it will skip the first reloc and
4898 handle the second. The second reloc already has an
4899 extra addend of 4, which we added above. We must
4900 subtract it out, and then subtract another 4 to make
4901 the first reloc come out right. The second reloc
4902 will come out right because we are going to add 4 to
4903 offset_expr when we build its instruction below. */
4904 offset_expr
.X_add_number
-= 8;
4905 offset_expr
.X_op
= O_constant
;
4907 macro_build_lui (p
, &icnt
, &offset_expr
, AT
);
4912 macro_build (p
, &icnt
, (expressionS
*) NULL
,
4913 mips_isa
< 3 ? "addu" : "daddu",
4914 "d,v,t", AT
, breg
, AT
);
4918 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
,
4919 coproc
? treg
+ 1 : treg
,
4920 (int) BFD_RELOC_LO16
, AT
);
4923 /* FIXME: How do we handle overflow here? */
4924 offset_expr
.X_add_number
+= 4;
4925 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
,
4926 coproc
? treg
: treg
+ 1,
4927 (int) BFD_RELOC_LO16
, AT
);
4929 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
4933 /* If this is a reference to an external symbol, we want
4934 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4939 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4941 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
4942 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
4943 If there is a base register we add it to $at before the
4944 lwc1 instructions. If there is a constant we include it
4945 in the lwc1 instructions. */
4947 expr1
.X_add_number
= offset_expr
.X_add_number
;
4948 offset_expr
.X_add_number
= 0;
4949 if (expr1
.X_add_number
< -0x8000
4950 || expr1
.X_add_number
>= 0x8000 - 4)
4951 as_bad ("PIC code offset overflow (max 16 signed bits)");
4956 frag_grow (24 + off
);
4957 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4958 mips_isa
< 3 ? "lw" : "ld",
4959 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
4960 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
4962 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4963 mips_isa
< 3 ? "addu" : "daddu",
4964 "d,v,t", AT
, breg
, AT
);
4965 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
4966 coproc
? treg
+ 1 : treg
,
4967 (int) BFD_RELOC_LO16
, AT
);
4968 expr1
.X_add_number
+= 4;
4970 /* Set mips_optimize to 2 to avoid inserting an undesired
4972 hold_mips_optimize
= mips_optimize
;
4974 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
4975 coproc
? treg
: treg
+ 1,
4976 (int) BFD_RELOC_LO16
, AT
);
4977 mips_optimize
= hold_mips_optimize
;
4979 (void) frag_var (rs_machine_dependent
, 0, 0,
4980 RELAX_ENCODE (0, 0, -16 - off
, -8, 1, 0),
4981 offset_expr
.X_add_symbol
, (long) 0,
4984 else if (mips_pic
== SVR4_PIC
)
4988 /* If this is a reference to an external symbol, we want
4989 lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16)
4991 lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16)
4996 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4998 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
4999 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
5000 If there is a base register we add it to $at before the
5001 lwc1 instructions. If there is a constant we include it
5002 in the lwc1 instructions. */
5004 expr1
.X_add_number
= offset_expr
.X_add_number
;
5005 offset_expr
.X_add_number
= 0;
5006 if (expr1
.X_add_number
< -0x8000
5007 || expr1
.X_add_number
>= 0x8000 - 4)
5008 as_bad ("PIC code offset overflow (max 16 signed bits)");
5009 if (reg_needs_delay (GP
))
5018 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
5019 AT
, (int) BFD_RELOC_MIPS_GOT_HI16
);
5020 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5021 mips_isa
< 3 ? "addu" : "daddu",
5022 "d,v,t", AT
, AT
, GP
);
5023 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5024 mips_isa
< 3 ? "lw" : "ld",
5025 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT_LO16
, AT
);
5026 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
5028 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5029 mips_isa
< 3 ? "addu" : "daddu",
5030 "d,v,t", AT
, breg
, AT
);
5031 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
5032 coproc
? treg
+ 1 : treg
,
5033 (int) BFD_RELOC_LO16
, AT
);
5034 expr1
.X_add_number
+= 4;
5036 /* Set mips_optimize to 2 to avoid inserting an undesired
5038 hold_mips_optimize
= mips_optimize
;
5040 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
5041 coproc
? treg
: treg
+ 1,
5042 (int) BFD_RELOC_LO16
, AT
);
5043 mips_optimize
= hold_mips_optimize
;
5044 expr1
.X_add_number
-= 4;
5046 p
= frag_var (rs_machine_dependent
, 16 + gpdel
+ off
, 0,
5047 RELAX_ENCODE (24 + off
, 16 + gpdel
+ off
, gpdel
,
5048 8 + gpdel
+ off
, 1, 0),
5049 offset_expr
.X_add_symbol
, (long) 0,
5053 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
5056 macro_build (p
, &icnt
, &offset_expr
,
5057 mips_isa
< 3 ? "lw" : "ld",
5058 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
5060 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
5064 macro_build (p
, &icnt
, (expressionS
*) NULL
,
5065 mips_isa
< 3 ? "addu" : "daddu",
5066 "d,v,t", AT
, breg
, AT
);
5069 macro_build (p
, &icnt
, &expr1
, s
, fmt
,
5070 coproc
? treg
+ 1 : treg
,
5071 (int) BFD_RELOC_LO16
, AT
);
5073 expr1
.X_add_number
+= 4;
5075 /* Set mips_optimize to 2 to avoid inserting an undesired
5077 hold_mips_optimize
= mips_optimize
;
5079 macro_build (p
, &icnt
, &expr1
, s
, fmt
,
5080 coproc
? treg
: treg
+ 1,
5081 (int) BFD_RELOC_LO16
, AT
);
5082 mips_optimize
= hold_mips_optimize
;
5084 else if (mips_pic
== EMBEDDED_PIC
)
5086 /* If there is no base register, we use
5087 <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL)
5088 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_MIPS_GPREL)
5089 If we have a base register, we use
5091 <op> $treg,<sym>($at) (BFD_RELOC_MIPS_GPREL)
5092 <op> $treg+1,<sym>+4($at) (BFD_RELOC_MIPS_GPREL)
5101 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5102 mips_isa
< 3 ? "addu" : "daddu",
5103 "d,v,t", AT
, breg
, GP
);
5108 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
5109 coproc
? treg
+ 1 : treg
,
5110 (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
5111 offset_expr
.X_add_number
+= 4;
5112 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
5113 coproc
? treg
: treg
+ 1,
5114 (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
5130 assert (mips_isa
< 3);
5131 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
5132 (int) BFD_RELOC_LO16
, breg
);
5133 offset_expr
.X_add_number
+= 4;
5134 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
+ 1,
5135 (int) BFD_RELOC_LO16
, breg
);
5137 #ifdef LOSING_COMPILER
5143 as_warn ("Macro used $at after \".set noat\"");
5148 struct mips_cl_insn
*ip
;
5150 register int treg
, sreg
, dreg
, breg
;
5165 bfd_reloc_code_real_type r
;
5168 treg
= (ip
->insn_opcode
>> 16) & 0x1f;
5169 dreg
= (ip
->insn_opcode
>> 11) & 0x1f;
5170 sreg
= breg
= (ip
->insn_opcode
>> 21) & 0x1f;
5171 mask
= ip
->insn_mo
->mask
;
5173 expr1
.X_op
= O_constant
;
5174 expr1
.X_op_symbol
= NULL
;
5175 expr1
.X_add_symbol
= NULL
;
5176 expr1
.X_add_number
= 1;
5180 #endif /* LOSING_COMPILER */
5185 macro_build ((char *) NULL
, &icnt
, NULL
,
5186 dbl
? "dmultu" : "multu",
5188 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
5194 /* The MIPS assembler some times generates shifts and adds. I'm
5195 not trying to be that fancy. GCC should do this for us
5197 load_register (&icnt
, AT
, &imm_expr
, dbl
);
5198 macro_build ((char *) NULL
, &icnt
, NULL
,
5199 dbl
? "dmult" : "mult",
5201 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
5207 mips_emit_delays (true);
5209 mips_any_noreorder
= 1;
5210 macro_build ((char *) NULL
, &icnt
, NULL
,
5211 dbl
? "dmult" : "mult",
5213 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
5214 macro_build ((char *) NULL
, &icnt
, NULL
,
5215 dbl
? "dsra32" : "sra",
5216 "d,w,<", dreg
, dreg
, 31);
5217 macro_build ((char *) NULL
, &icnt
, NULL
, "mfhi", "d", AT
);
5219 macro_build ((char *) NULL
, &icnt
, NULL
, "tne", "s,t", dreg
, AT
);
5222 expr1
.X_add_number
= 8;
5223 macro_build ((char *) NULL
, &icnt
, &expr1
, "beq", "s,t,p", dreg
, AT
);
5224 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
5225 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 6);
5228 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
5234 mips_emit_delays (true);
5236 mips_any_noreorder
= 1;
5237 macro_build ((char *) NULL
, &icnt
, NULL
,
5238 dbl
? "dmultu" : "multu",
5240 macro_build ((char *) NULL
, &icnt
, NULL
, "mfhi", "d", AT
);
5241 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
5243 macro_build ((char *) NULL
, &icnt
, NULL
, "tne", "s,t", AT
, 0);
5246 expr1
.X_add_number
= 8;
5247 macro_build ((char *) NULL
, &icnt
, &expr1
, "beq", "s,t,p", AT
, 0);
5248 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
5249 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 6);
5255 macro_build ((char *) NULL
, &icnt
, NULL
, "subu", "d,v,t", AT
, 0, treg
);
5256 macro_build ((char *) NULL
, &icnt
, NULL
, "srlv", "d,t,s", AT
, sreg
, AT
);
5257 macro_build ((char *) NULL
, &icnt
, NULL
, "sllv", "d,t,s", dreg
, sreg
,
5259 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
5263 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", AT
, sreg
,
5264 (int) (imm_expr
.X_add_number
& 0x1f));
5265 macro_build ((char *) NULL
, &icnt
, NULL
, "srl", "d,w,<", dreg
, sreg
,
5266 (int) ((0 - imm_expr
.X_add_number
) & 0x1f));
5267 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
5271 macro_build ((char *) NULL
, &icnt
, NULL
, "subu", "d,v,t", AT
, 0, treg
);
5272 macro_build ((char *) NULL
, &icnt
, NULL
, "sllv", "d,t,s", AT
, sreg
, AT
);
5273 macro_build ((char *) NULL
, &icnt
, NULL
, "srlv", "d,t,s", dreg
, sreg
,
5275 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
5279 macro_build ((char *) NULL
, &icnt
, NULL
, "srl", "d,w,<", AT
, sreg
,
5280 (int) (imm_expr
.X_add_number
& 0x1f));
5281 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", dreg
, sreg
,
5282 (int) ((0 - imm_expr
.X_add_number
) & 0x1f));
5283 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
5287 assert (mips_isa
< 2);
5288 /* Even on a big endian machine $fn comes before $fn+1. We have
5289 to adjust when storing to memory. */
5290 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "swc1", "T,o(b)",
5291 target_big_endian
? treg
+ 1 : treg
,
5292 (int) BFD_RELOC_LO16
, breg
);
5293 offset_expr
.X_add_number
+= 4;
5294 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "swc1", "T,o(b)",
5295 target_big_endian
? treg
: treg
+ 1,
5296 (int) BFD_RELOC_LO16
, breg
);
5301 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
5302 treg
, (int) BFD_RELOC_LO16
);
5304 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
5305 sreg
, (int) BFD_RELOC_LO16
);
5308 macro_build ((char *) NULL
, &icnt
, NULL
, "xor", "d,v,t", dreg
,
5310 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
5311 dreg
, (int) BFD_RELOC_LO16
);
5316 if (imm_expr
.X_add_number
== 0)
5318 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
5319 sreg
, (int) BFD_RELOC_LO16
);
5324 as_warn ("Instruction %s: result is always false",
5326 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
, 0);
5329 if (imm_expr
.X_add_number
>= 0 && imm_expr
.X_add_number
< 0x10000)
5331 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "xori", "t,r,i", dreg
,
5332 sreg
, (int) BFD_RELOC_LO16
);
5335 else if (imm_expr
.X_add_number
> -0x8000 && imm_expr
.X_add_number
< 0)
5337 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
5338 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
5339 mips_isa
< 3 ? "addiu" : "daddiu",
5340 "t,r,j", dreg
, sreg
,
5341 (int) BFD_RELOC_LO16
);
5346 load_register (&icnt
, AT
, &imm_expr
, 0);
5347 macro_build ((char *) NULL
, &icnt
, NULL
, "xor", "d,v,t", dreg
,
5351 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
, dreg
,
5352 (int) BFD_RELOC_LO16
);
5357 case M_SGE
: /* sreg >= treg <==> not (sreg < treg) */
5363 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, sreg
, treg
);
5364 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
5365 (int) BFD_RELOC_LO16
);
5368 case M_SGE_I
: /* sreg >= I <==> not (sreg < I) */
5370 if (imm_expr
.X_add_number
>= -0x8000 && imm_expr
.X_add_number
< 0x8000)
5372 macro_build ((char *) NULL
, &icnt
, &expr1
,
5373 mask
== M_SGE_I
? "slti" : "sltiu",
5374 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
5379 load_register (&icnt
, AT
, &imm_expr
, 0);
5380 macro_build ((char *) NULL
, &icnt
, NULL
,
5381 mask
== M_SGE_I
? "slt" : "sltu",
5382 "d,v,t", dreg
, sreg
, AT
);
5385 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
5386 (int) BFD_RELOC_LO16
);
5391 case M_SGT
: /* sreg > treg <==> treg < sreg */
5397 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, treg
, sreg
);
5400 case M_SGT_I
: /* sreg > I <==> I < sreg */
5406 load_register (&icnt
, AT
, &imm_expr
, 0);
5407 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, AT
, sreg
);
5410 case M_SLE
: /* sreg <= treg <==> treg >= sreg <==> not (treg < sreg) */
5416 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, treg
, sreg
);
5417 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
5418 (int) BFD_RELOC_LO16
);
5421 case M_SLE_I
: /* sreg <= I <==> I >= sreg <==> not (I < sreg) */
5427 load_register (&icnt
, AT
, &imm_expr
, 0);
5428 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, AT
, sreg
);
5429 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
5430 (int) BFD_RELOC_LO16
);
5434 if (imm_expr
.X_add_number
>= -0x8000 && imm_expr
.X_add_number
< 0x8000)
5436 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "slti", "t,r,j",
5437 dreg
, sreg
, (int) BFD_RELOC_LO16
);
5440 load_register (&icnt
, AT
, &imm_expr
, 0);
5441 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", dreg
, sreg
, AT
);
5445 if (imm_expr
.X_add_number
>= -0x8000 && imm_expr
.X_add_number
< 0x8000)
5447 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "sltiu", "t,r,j",
5448 dreg
, sreg
, (int) BFD_RELOC_LO16
);
5451 load_register (&icnt
, AT
, &imm_expr
, 0);
5452 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, sreg
,
5458 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0,
5461 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0,
5465 macro_build ((char *) NULL
, &icnt
, NULL
, "xor", "d,v,t", dreg
,
5467 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0,
5473 if (imm_expr
.X_add_number
== 0)
5475 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0,
5481 as_warn ("Instruction %s: result is always true",
5483 macro_build ((char *) NULL
, &icnt
, &expr1
,
5484 mips_isa
< 3 ? "addiu" : "daddiu",
5485 "t,r,j", dreg
, 0, (int) BFD_RELOC_LO16
);
5488 if (imm_expr
.X_add_number
>= 0 && imm_expr
.X_add_number
< 0x10000)
5490 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "xori", "t,r,i",
5491 dreg
, sreg
, (int) BFD_RELOC_LO16
);
5494 else if (imm_expr
.X_add_number
> -0x8000 && imm_expr
.X_add_number
< 0)
5496 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
5497 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
5498 mips_isa
< 3 ? "addiu" : "daddiu",
5499 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
5504 load_register (&icnt
, AT
, &imm_expr
, 0);
5505 macro_build ((char *) NULL
, &icnt
, NULL
, "xor", "d,v,t", dreg
,
5509 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0, dreg
);
5517 if (imm_expr
.X_add_number
> -0x8000 && imm_expr
.X_add_number
<= 0x8000)
5519 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
5520 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
5521 dbl
? "daddi" : "addi",
5522 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
5525 load_register (&icnt
, AT
, &imm_expr
, dbl
);
5526 macro_build ((char *) NULL
, &icnt
, NULL
,
5527 dbl
? "dsub" : "sub",
5528 "d,v,t", dreg
, sreg
, AT
);
5534 if (imm_expr
.X_add_number
> -0x8000 && imm_expr
.X_add_number
<= 0x8000)
5536 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
5537 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
5538 dbl
? "daddiu" : "addiu",
5539 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
5542 load_register (&icnt
, AT
, &imm_expr
, dbl
);
5543 macro_build ((char *) NULL
, &icnt
, NULL
,
5544 dbl
? "dsubu" : "subu",
5545 "d,v,t", dreg
, sreg
, AT
);
5566 load_register (&icnt
, AT
, &imm_expr
, 0);
5567 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "s,t", sreg
, AT
);
5572 assert (mips_isa
< 2);
5573 sreg
= (ip
->insn_opcode
>> 11) & 0x1f; /* floating reg */
5574 dreg
= (ip
->insn_opcode
>> 06) & 0x1f; /* floating reg */
5577 * Is the double cfc1 instruction a bug in the mips assembler;
5578 * or is there a reason for it?
5580 mips_emit_delays (true);
5582 mips_any_noreorder
= 1;
5583 macro_build ((char *) NULL
, &icnt
, NULL
, "cfc1", "t,G", treg
, 31);
5584 macro_build ((char *) NULL
, &icnt
, NULL
, "cfc1", "t,G", treg
, 31);
5585 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "");
5586 expr1
.X_add_number
= 3;
5587 macro_build ((char *) NULL
, &icnt
, &expr1
, "ori", "t,r,i", AT
, treg
,
5588 (int) BFD_RELOC_LO16
);
5589 expr1
.X_add_number
= 2;
5590 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", AT
, AT
,
5591 (int) BFD_RELOC_LO16
);
5592 macro_build ((char *) NULL
, &icnt
, NULL
, "ctc1", "t,G", AT
, 31);
5593 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "");
5594 macro_build ((char *) NULL
, &icnt
, NULL
,
5595 mask
== M_TRUNCWD
? "cvt.w.d" : "cvt.w.s", "D,S", dreg
, sreg
);
5596 macro_build ((char *) NULL
, &icnt
, NULL
, "ctc1", "t,G", treg
, 31);
5597 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "");
5607 if (offset_expr
.X_add_number
>= 0x7fff)
5608 as_bad ("operand overflow");
5609 /* avoid load delay */
5610 if (! target_big_endian
)
5611 offset_expr
.X_add_number
+= 1;
5612 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
5613 (int) BFD_RELOC_LO16
, breg
);
5614 if (! target_big_endian
)
5615 offset_expr
.X_add_number
-= 1;
5617 offset_expr
.X_add_number
+= 1;
5618 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lbu", "t,o(b)", AT
,
5619 (int) BFD_RELOC_LO16
, breg
);
5620 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", treg
, treg
, 8);
5621 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", treg
, treg
, AT
);
5634 if (offset_expr
.X_add_number
>= 0x8000 - off
)
5635 as_bad ("operand overflow");
5636 if (! target_big_endian
)
5637 offset_expr
.X_add_number
+= off
;
5638 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
5639 (int) BFD_RELOC_LO16
, breg
);
5640 if (! target_big_endian
)
5641 offset_expr
.X_add_number
-= off
;
5643 offset_expr
.X_add_number
+= off
;
5644 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s2
, "t,o(b)", treg
,
5645 (int) BFD_RELOC_LO16
, breg
);
5658 load_address (&icnt
, AT
, &offset_expr
);
5660 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5661 mips_isa
< 3 ? "addu" : "daddu",
5662 "d,v,t", AT
, AT
, breg
);
5663 if (! target_big_endian
)
5664 expr1
.X_add_number
= off
;
5666 expr1
.X_add_number
= 0;
5667 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, "t,o(b)", treg
,
5668 (int) BFD_RELOC_LO16
, AT
);
5669 if (! target_big_endian
)
5670 expr1
.X_add_number
= 0;
5672 expr1
.X_add_number
= off
;
5673 macro_build ((char *) NULL
, &icnt
, &expr1
, s2
, "t,o(b)", treg
,
5674 (int) BFD_RELOC_LO16
, AT
);
5679 load_address (&icnt
, AT
, &offset_expr
);
5681 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5682 mips_isa
< 3 ? "addu" : "daddu",
5683 "d,v,t", AT
, AT
, breg
);
5684 if (target_big_endian
)
5685 expr1
.X_add_number
= 0;
5686 macro_build ((char *) NULL
, &icnt
, &expr1
,
5687 mask
== M_ULH_A
? "lb" : "lbu", "t,o(b)", treg
,
5688 (int) BFD_RELOC_LO16
, AT
);
5689 if (target_big_endian
)
5690 expr1
.X_add_number
= 1;
5692 expr1
.X_add_number
= 0;
5693 macro_build ((char *) NULL
, &icnt
, &expr1
, "lbu", "t,o(b)", AT
,
5694 (int) BFD_RELOC_LO16
, AT
);
5695 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", treg
,
5697 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", treg
,
5702 if (offset_expr
.X_add_number
>= 0x7fff)
5703 as_bad ("operand overflow");
5704 if (target_big_endian
)
5705 offset_expr
.X_add_number
+= 1;
5706 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "sb", "t,o(b)", treg
,
5707 (int) BFD_RELOC_LO16
, breg
);
5708 macro_build ((char *) NULL
, &icnt
, NULL
, "srl", "d,w,<", AT
, treg
, 8);
5709 if (target_big_endian
)
5710 offset_expr
.X_add_number
-= 1;
5712 offset_expr
.X_add_number
+= 1;
5713 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "sb", "t,o(b)", AT
,
5714 (int) BFD_RELOC_LO16
, breg
);
5727 if (offset_expr
.X_add_number
>= 0x8000 - off
)
5728 as_bad ("operand overflow");
5729 if (! target_big_endian
)
5730 offset_expr
.X_add_number
+= off
;
5731 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
5732 (int) BFD_RELOC_LO16
, breg
);
5733 if (! target_big_endian
)
5734 offset_expr
.X_add_number
-= off
;
5736 offset_expr
.X_add_number
+= off
;
5737 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s2
, "t,o(b)", treg
,
5738 (int) BFD_RELOC_LO16
, breg
);
5751 load_address (&icnt
, AT
, &offset_expr
);
5753 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5754 mips_isa
< 3 ? "addu" : "daddu",
5755 "d,v,t", AT
, AT
, breg
);
5756 if (! target_big_endian
)
5757 expr1
.X_add_number
= off
;
5759 expr1
.X_add_number
= 0;
5760 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, "t,o(b)", treg
,
5761 (int) BFD_RELOC_LO16
, AT
);
5762 if (! target_big_endian
)
5763 expr1
.X_add_number
= 0;
5765 expr1
.X_add_number
= off
;
5766 macro_build ((char *) NULL
, &icnt
, &expr1
, s2
, "t,o(b)", treg
,
5767 (int) BFD_RELOC_LO16
, AT
);
5771 load_address (&icnt
, AT
, &offset_expr
);
5773 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5774 mips_isa
< 3 ? "addu" : "daddu",
5775 "d,v,t", AT
, AT
, breg
);
5776 if (! target_big_endian
)
5777 expr1
.X_add_number
= 0;
5778 macro_build ((char *) NULL
, &icnt
, &expr1
, "sb", "t,o(b)", treg
,
5779 (int) BFD_RELOC_LO16
, AT
);
5780 macro_build ((char *) NULL
, &icnt
, NULL
, "srl", "d,w,<", treg
,
5782 if (! target_big_endian
)
5783 expr1
.X_add_number
= 1;
5785 expr1
.X_add_number
= 0;
5786 macro_build ((char *) NULL
, &icnt
, &expr1
, "sb", "t,o(b)", treg
,
5787 (int) BFD_RELOC_LO16
, AT
);
5788 if (! target_big_endian
)
5789 expr1
.X_add_number
= 0;
5791 expr1
.X_add_number
= 1;
5792 macro_build ((char *) NULL
, &icnt
, &expr1
, "lbu", "t,o(b)", AT
,
5793 (int) BFD_RELOC_LO16
, AT
);
5794 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", treg
,
5796 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", treg
,
5801 as_bad ("Macro %s not implemented yet", ip
->insn_mo
->name
);
5805 as_warn ("Macro used $at after \".set noat\"");
5808 /* Implement macros in mips16 mode. */
5812 struct mips_cl_insn
*ip
;
5815 int xreg
, yreg
, zreg
, tmp
;
5819 const char *s
, *s2
, *s3
;
5821 mask
= ip
->insn_mo
->mask
;
5823 xreg
= (ip
->insn_opcode
>> MIPS16OP_SH_RX
) & MIPS16OP_MASK_RX
;
5824 yreg
= (ip
->insn_opcode
>> MIPS16OP_SH_RY
) & MIPS16OP_MASK_RY
;
5825 zreg
= (ip
->insn_opcode
>> MIPS16OP_SH_RZ
) & MIPS16OP_MASK_RZ
;
5829 expr1
.X_op
= O_constant
;
5830 expr1
.X_op_symbol
= NULL
;
5831 expr1
.X_add_symbol
= NULL
;
5832 expr1
.X_add_number
= 1;
5851 mips_emit_delays (true);
5853 mips_any_noreorder
= 1;
5854 macro_build ((char *) NULL
, &icnt
, NULL
,
5855 dbl
? "ddiv" : "div",
5856 "0,x,y", xreg
, yreg
);
5857 expr1
.X_add_number
= 2;
5858 macro_build ((char *) NULL
, &icnt
, &expr1
, "bnez", "x,p", yreg
);
5859 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "6", 7);
5860 /* FIXME: The normal code checks for of -1 / -0x80000000 here,
5861 since that causes an overflow. We should do that as well,
5862 but I don't see how to do the comparisons without a temporary
5865 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "x", zreg
);
5884 mips_emit_delays (true);
5886 mips_any_noreorder
= 1;
5887 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "0,x,y", xreg
, yreg
);
5888 expr1
.X_add_number
= 2;
5889 macro_build ((char *) NULL
, &icnt
, &expr1
, "bnez", "x,p", yreg
);
5890 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "6", 7);
5892 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "x", zreg
);
5900 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
5901 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
5902 dbl
? "daddiu" : "addiu",
5903 "y,x,4", yreg
, xreg
);
5907 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
5908 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "addiu",
5913 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
5914 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "daddiu",
5937 goto do_reverse_branch
;
5941 goto do_reverse_branch
;
5953 goto do_reverse_branch
;
5964 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s
, "x,y",
5966 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s2
, "p");
5993 goto do_addone_branch_i
;
5998 goto do_addone_branch_i
;
6013 goto do_addone_branch_i
;
6020 ++imm_expr
.X_add_number
;
6023 macro_build ((char *) NULL
, &icnt
, &imm_expr
, s
, s3
, xreg
);
6024 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s2
, "p");
6028 expr1
.X_add_number
= 0;
6029 macro_build ((char *) NULL
, &icnt
, &expr1
, "slti", "x,8", yreg
);
6031 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6032 "move", "y,X", xreg
, yreg
);
6033 expr1
.X_add_number
= 2;
6034 macro_build ((char *) NULL
, &icnt
, &expr1
, "bteqz", "p");
6035 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6036 "neg", "x,w", xreg
, xreg
);
6040 /* This routine assembles an instruction into its binary format. As a
6041 side effect, it sets one of the global variables imm_reloc or
6042 offset_reloc to the type of relocation to do if one of the operands
6043 is an address expression. */
6048 struct mips_cl_insn
*ip
;
6053 struct mips_opcode
*insn
;
6056 unsigned int lastregno
= 0;
6061 for (s
= str
; islower (*s
) || (*s
>= '0' && *s
<= '3') || *s
== '6' || *s
== '.'; ++s
)
6073 as_fatal ("Unknown opcode: `%s'", str
);
6075 if ((insn
= (struct mips_opcode
*) hash_find (op_hash
, str
)) == NULL
)
6077 insn_error
= "unrecognized opcode";
6085 assert (strcmp (insn
->name
, str
) == 0);
6087 if (insn
->pinfo
== INSN_MACRO
)
6088 insn_isa
= insn
->match
;
6089 else if ((insn
->pinfo
& INSN_ISA
) == INSN_ISA2
)
6091 else if ((insn
->pinfo
& INSN_ISA
) == INSN_ISA3
)
6093 else if ((insn
->pinfo
& INSN_ISA
) == INSN_ISA4
)
6098 if (insn_isa
> mips_isa
6099 || ((insn
->pinfo
& INSN_ISA
) == INSN_4650
6101 || ((insn
->pinfo
& INSN_ISA
) == INSN_4010
6103 || ((insn
->pinfo
& INSN_ISA
) == INSN_4100
6106 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
]
6107 && strcmp (insn
->name
, insn
[1].name
) == 0)
6112 if (insn_isa
<= mips_isa
)
6113 insn_error
= "opcode not supported on this processor";
6116 static char buf
[100];
6118 sprintf (buf
, "opcode requires -mips%d or greater", insn_isa
);
6125 ip
->insn_opcode
= insn
->match
;
6126 for (args
= insn
->args
;; ++args
)
6132 case '\0': /* end of args */
6145 ip
->insn_opcode
|= lastregno
<< 21;
6150 ip
->insn_opcode
|= lastregno
<< 16;
6154 ip
->insn_opcode
|= lastregno
<< 11;
6160 /* handle optional base register.
6161 Either the base register is omitted or
6162 we must have a left paren. */
6163 /* this is dependent on the next operand specifier
6164 is a 'b' for base register */
6165 assert (args
[1] == 'b');
6169 case ')': /* these must match exactly */
6174 case '<': /* must be at least one digit */
6176 * According to the manual, if the shift amount is greater
6177 * than 31 or less than 0 the the shift amount should be
6178 * mod 32. In reality the mips assembler issues an error.
6179 * We issue a warning and mask out all but the low 5 bits.
6181 my_getExpression (&imm_expr
, s
);
6182 check_absolute_expr (ip
, &imm_expr
);
6183 if ((unsigned long) imm_expr
.X_add_number
> 31)
6185 as_warn ("Improper shift amount (%ld)",
6186 (long) imm_expr
.X_add_number
);
6187 imm_expr
.X_add_number
= imm_expr
.X_add_number
& 0x1f;
6189 ip
->insn_opcode
|= imm_expr
.X_add_number
<< 6;
6190 imm_expr
.X_op
= O_absent
;
6194 case '>': /* shift amount minus 32 */
6195 my_getExpression (&imm_expr
, s
);
6196 check_absolute_expr (ip
, &imm_expr
);
6197 if ((unsigned long) imm_expr
.X_add_number
< 32
6198 || (unsigned long) imm_expr
.X_add_number
> 63)
6200 ip
->insn_opcode
|= (imm_expr
.X_add_number
- 32) << 6;
6201 imm_expr
.X_op
= O_absent
;
6205 case 'k': /* cache code */
6206 case 'h': /* prefx code */
6207 my_getExpression (&imm_expr
, s
);
6208 check_absolute_expr (ip
, &imm_expr
);
6209 if ((unsigned long) imm_expr
.X_add_number
> 31)
6211 as_warn ("Invalid value for `%s' (%lu)",
6213 (unsigned long) imm_expr
.X_add_number
);
6214 imm_expr
.X_add_number
&= 0x1f;
6217 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_CACHE
;
6219 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_PREFX
;
6220 imm_expr
.X_op
= O_absent
;
6224 case 'c': /* break code */
6225 my_getExpression (&imm_expr
, s
);
6226 check_absolute_expr (ip
, &imm_expr
);
6227 if ((unsigned) imm_expr
.X_add_number
> 1023)
6228 as_warn ("Illegal break code (%ld)",
6229 (long) imm_expr
.X_add_number
);
6230 ip
->insn_opcode
|= imm_expr
.X_add_number
<< 16;
6231 imm_expr
.X_op
= O_absent
;
6235 case 'B': /* syscall code */
6236 my_getExpression (&imm_expr
, s
);
6237 check_absolute_expr (ip
, &imm_expr
);
6238 if ((unsigned) imm_expr
.X_add_number
> 0xfffff)
6239 as_warn ("Illegal syscall code (%ld)",
6240 (long) imm_expr
.X_add_number
);
6241 ip
->insn_opcode
|= imm_expr
.X_add_number
<< 6;
6242 imm_expr
.X_op
= O_absent
;
6246 case 'C': /* Coprocessor code */
6247 my_getExpression (&imm_expr
, s
);
6248 check_absolute_expr (ip
, &imm_expr
);
6249 if ((unsigned long) imm_expr
.X_add_number
>= (1<<25))
6251 as_warn ("Coproccesor code > 25 bits (%ld)",
6252 (long) imm_expr
.X_add_number
);
6253 imm_expr
.X_add_number
&= ((1<<25) - 1);
6255 ip
->insn_opcode
|= imm_expr
.X_add_number
;
6256 imm_expr
.X_op
= O_absent
;
6260 case 'b': /* base register */
6261 case 'd': /* destination register */
6262 case 's': /* source register */
6263 case 't': /* target register */
6264 case 'r': /* both target and source */
6265 case 'v': /* both dest and source */
6266 case 'w': /* both dest and target */
6267 case 'E': /* coprocessor target register */
6268 case 'G': /* coprocessor destination register */
6269 case 'x': /* ignore register name */
6270 case 'z': /* must be zero register */
6284 while (isdigit (*s
));
6286 as_bad ("Invalid register number (%d)", regno
);
6288 else if (*args
== 'E' || *args
== 'G')
6292 if (s
[1] == 'f' && s
[2] == 'p')
6297 else if (s
[1] == 's' && s
[2] == 'p')
6302 else if (s
[1] == 'g' && s
[2] == 'p')
6307 else if (s
[1] == 'a' && s
[2] == 't')
6312 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '0')
6317 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '1')
6329 as_warn ("Used $at without \".set noat\"");
6335 if (c
== 'r' || c
== 'v' || c
== 'w')
6342 /* 'z' only matches $0. */
6343 if (c
== 'z' && regno
!= 0)
6351 ip
->insn_opcode
|= regno
<< 21;
6355 ip
->insn_opcode
|= regno
<< 11;
6360 ip
->insn_opcode
|= regno
<< 16;
6363 /* This case exists because on the r3000 trunc
6364 expands into a macro which requires a gp
6365 register. On the r6000 or r4000 it is
6366 assembled into a single instruction which
6367 ignores the register. Thus the insn version
6368 is MIPS_ISA2 and uses 'x', and the macro
6369 version is MIPS_ISA1 and uses 't'. */
6372 /* This case is for the div instruction, which
6373 acts differently if the destination argument
6374 is $0. This only matches $0, and is checked
6375 outside the switch. */
6386 ip
->insn_opcode
|= lastregno
<< 21;
6389 ip
->insn_opcode
|= lastregno
<< 16;
6394 case 'D': /* floating point destination register */
6395 case 'S': /* floating point source register */
6396 case 'T': /* floating point target register */
6397 case 'R': /* floating point source register */
6401 if (s
[0] == '$' && s
[1] == 'f' && isdigit (s
[2]))
6411 while (isdigit (*s
));
6414 as_bad ("Invalid float register number (%d)", regno
);
6416 if ((regno
& 1) != 0
6418 && ! (strcmp (str
, "mtc1") == 0
6419 || strcmp (str
, "mfc1") == 0
6420 || strcmp (str
, "lwc1") == 0
6421 || strcmp (str
, "swc1") == 0
6422 || strcmp (str
, "l.s") == 0
6423 || strcmp (str
, "s.s") == 0))
6424 as_warn ("Float register should be even, was %d",
6432 if (c
== 'V' || c
== 'W')
6442 ip
->insn_opcode
|= regno
<< 6;
6446 ip
->insn_opcode
|= regno
<< 11;
6450 ip
->insn_opcode
|= regno
<< 16;
6453 ip
->insn_opcode
|= regno
<< 21;
6462 ip
->insn_opcode
|= lastregno
<< 11;
6465 ip
->insn_opcode
|= lastregno
<< 16;
6471 my_getExpression (&imm_expr
, s
);
6472 if (imm_expr
.X_op
!= O_big
6473 && imm_expr
.X_op
!= O_constant
)
6474 insn_error
= "absolute expression required";
6479 my_getExpression (&offset_expr
, s
);
6480 imm_reloc
= BFD_RELOC_32
;
6492 unsigned char temp
[8];
6494 unsigned int length
;
6499 /* These only appear as the last operand in an
6500 instruction, and every instruction that accepts
6501 them in any variant accepts them in all variants.
6502 This means we don't have to worry about backing out
6503 any changes if the instruction does not match.
6505 The difference between them is the size of the
6506 floating point constant and where it goes. For 'F'
6507 and 'L' the constant is 64 bits; for 'f' and 'l' it
6508 is 32 bits. Where the constant is placed is based
6509 on how the MIPS assembler does things:
6512 f -- immediate value
6515 The .lit4 and .lit8 sections are only used if
6516 permitted by the -G argument.
6518 When generating embedded PIC code, we use the
6519 .lit8 section but not the .lit4 section (we can do
6520 .lit4 inline easily; we need to put .lit8
6521 somewhere in the data segment, and using .lit8
6522 permits the linker to eventually combine identical
6525 f64
= *args
== 'F' || *args
== 'L';
6527 save_in
= input_line_pointer
;
6528 input_line_pointer
= s
;
6529 err
= md_atof (f64
? 'd' : 'f', (char *) temp
, &len
);
6531 s
= input_line_pointer
;
6532 input_line_pointer
= save_in
;
6533 if (err
!= NULL
&& *err
!= '\0')
6535 as_bad ("Bad floating point constant: %s", err
);
6536 memset (temp
, '\0', sizeof temp
);
6537 length
= f64
? 8 : 4;
6540 assert (length
== (f64
? 8 : 4));
6544 && (! USE_GLOBAL_POINTER_OPT
6545 || mips_pic
== EMBEDDED_PIC
6546 || g_switch_value
< 4)
6549 imm_expr
.X_op
= O_constant
;
6550 if (! target_big_endian
)
6551 imm_expr
.X_add_number
=
6552 (((((((int) temp
[3] << 8)
6557 imm_expr
.X_add_number
=
6558 (((((((int) temp
[0] << 8)
6565 const char *newname
;
6568 /* Switch to the right section. */
6570 subseg
= now_subseg
;
6573 default: /* unused default case avoids warnings. */
6575 newname
= RDATA_SECTION_NAME
;
6576 if (USE_GLOBAL_POINTER_OPT
&& g_switch_value
>= 8)
6580 newname
= RDATA_SECTION_NAME
;
6583 assert (!USE_GLOBAL_POINTER_OPT
6584 || g_switch_value
>= 4);
6588 new_seg
= subseg_new (newname
, (subsegT
) 0);
6589 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
6590 bfd_set_section_flags (stdoutput
, new_seg
,
6595 frag_align (*args
== 'l' ? 2 : 3, 0);
6596 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
6597 record_alignment (new_seg
, 4);
6599 record_alignment (new_seg
, *args
== 'l' ? 2 : 3);
6601 as_bad ("Can't use floating point insn in this section");
6603 /* Set the argument to the current address in the
6605 offset_expr
.X_op
= O_symbol
;
6606 offset_expr
.X_add_symbol
=
6607 symbol_new ("L0\001", now_seg
,
6608 (valueT
) frag_now_fix (), frag_now
);
6609 offset_expr
.X_add_number
= 0;
6611 /* Put the floating point number into the section. */
6612 p
= frag_more ((int) length
);
6613 memcpy (p
, temp
, length
);
6615 /* Switch back to the original section. */
6616 subseg_set (seg
, subseg
);
6621 case 'i': /* 16 bit unsigned immediate */
6622 case 'j': /* 16 bit signed immediate */
6623 imm_reloc
= BFD_RELOC_LO16
;
6624 c
= my_getSmallExpression (&imm_expr
, s
);
6629 if (imm_expr
.X_op
== O_constant
)
6630 imm_expr
.X_add_number
=
6631 (imm_expr
.X_add_number
>> 16) & 0xffff;
6634 imm_reloc
= BFD_RELOC_HI16_S
;
6635 imm_unmatched_hi
= true;
6638 imm_reloc
= BFD_RELOC_HI16
;
6643 if ((c
== '\0' && imm_expr
.X_op
!= O_constant
)
6644 || ((imm_expr
.X_add_number
< 0
6645 || imm_expr
.X_add_number
>= 0x10000)
6646 && imm_expr
.X_op
== O_constant
))
6648 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
6649 !strcmp (insn
->name
, insn
[1].name
))
6651 if (imm_expr
.X_op
!= O_constant
6652 && imm_expr
.X_op
!= O_big
)
6653 insn_error
= "absolute expression required";
6655 as_bad ("16 bit expression not in range 0..65535");
6663 /* The upper bound should be 0x8000, but
6664 unfortunately the MIPS assembler accepts numbers
6665 from 0x8000 to 0xffff and sign extends them, and
6666 we want to be compatible. We only permit this
6667 extended range for an instruction which does not
6668 provide any further alternates, since those
6669 alternates may handle other cases. People should
6670 use the numbers they mean, rather than relying on
6671 a mysterious sign extension. */
6672 more
= (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
6673 strcmp (insn
->name
, insn
[1].name
) == 0);
6678 if ((c
== '\0' && imm_expr
.X_op
!= O_constant
)
6679 || ((imm_expr
.X_add_number
< -0x8000
6680 || imm_expr
.X_add_number
>= max
)
6681 && imm_expr
.X_op
== O_constant
)
6683 && imm_expr
.X_add_number
< 0
6685 && imm_expr
.X_unsigned
6686 && sizeof (imm_expr
.X_add_number
) <= 4))
6690 if (imm_expr
.X_op
!= O_constant
6691 && imm_expr
.X_op
!= O_big
)
6692 insn_error
= "absolute expression required";
6694 as_bad ("16 bit expression not in range -32768..32767");
6700 case 'o': /* 16 bit offset */
6701 c
= my_getSmallExpression (&offset_expr
, s
);
6703 /* If this value won't fit into a 16 bit offset, then go
6704 find a macro that will generate the 32 bit offset
6705 code pattern. As a special hack, we accept the
6706 difference of two local symbols as a constant. This
6707 is required to suppose embedded PIC switches, which
6708 use an instruction which looks like
6709 lw $4,$L12-$LS12($4)
6710 The problem with handling this in a more general
6711 fashion is that the macro function doesn't expect to
6712 see anything which can be handled in a single
6713 constant instruction. */
6715 && (offset_expr
.X_op
!= O_constant
6716 || offset_expr
.X_add_number
>= 0x8000
6717 || offset_expr
.X_add_number
< -0x8000)
6718 && (mips_pic
!= EMBEDDED_PIC
6719 || offset_expr
.X_op
!= O_subtract
6720 || now_seg
!= text_section
6721 || (S_GET_SEGMENT (offset_expr
.X_op_symbol
)
6725 offset_reloc
= BFD_RELOC_LO16
;
6726 if (c
== 'h' || c
== 'H')
6728 assert (offset_expr
.X_op
== O_constant
);
6729 offset_expr
.X_add_number
=
6730 (offset_expr
.X_add_number
>> 16) & 0xffff;
6735 case 'p': /* pc relative offset */
6736 offset_reloc
= BFD_RELOC_16_PCREL_S2
;
6737 my_getExpression (&offset_expr
, s
);
6741 case 'u': /* upper 16 bits */
6742 c
= my_getSmallExpression (&imm_expr
, s
);
6743 if (imm_expr
.X_op
== O_constant
6744 && (imm_expr
.X_add_number
< 0
6745 || imm_expr
.X_add_number
>= 0x10000))
6746 as_bad ("lui expression not in range 0..65535");
6747 imm_reloc
= BFD_RELOC_LO16
;
6752 if (imm_expr
.X_op
== O_constant
)
6753 imm_expr
.X_add_number
=
6754 (imm_expr
.X_add_number
>> 16) & 0xffff;
6757 imm_reloc
= BFD_RELOC_HI16_S
;
6758 imm_unmatched_hi
= true;
6761 imm_reloc
= BFD_RELOC_HI16
;
6767 case 'a': /* 26 bit address */
6768 my_getExpression (&offset_expr
, s
);
6770 offset_reloc
= BFD_RELOC_MIPS_JMP
;
6773 case 'N': /* 3 bit branch condition code */
6774 case 'M': /* 3 bit compare condition code */
6775 if (strncmp (s
, "$fcc", 4) != 0)
6785 while (isdigit (*s
));
6787 as_bad ("invalid condition code register $fcc%d", regno
);
6789 ip
->insn_opcode
|= regno
<< OP_SH_BCC
;
6791 ip
->insn_opcode
|= regno
<< OP_SH_CCC
;
6795 fprintf (stderr
, "bad char = '%c'\n", *args
);
6800 /* Args don't match. */
6801 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
6802 !strcmp (insn
->name
, insn
[1].name
))
6808 insn_error
= "illegal operands";
6813 /* This routine assembles an instruction into its binary format when
6814 assembling for the mips16. As a side effect, it sets one of the
6815 global variables imm_reloc or offset_reloc to the type of
6816 relocation to do if one of the operands is an address expression.
6817 It also sets mips16_small and mips16_ext if the user explicitly
6818 requested a small or extended instruction. */
6823 struct mips_cl_insn
*ip
;
6827 struct mips_opcode
*insn
;
6830 unsigned int lastregno
= 0;
6835 mips16_small
= false;
6838 for (s
= str
; islower (*s
); ++s
)
6850 if (s
[1] == 't' && s
[2] == ' ')
6853 mips16_small
= true;
6857 else if (s
[1] == 'e' && s
[2] == ' ')
6866 insn_error
= "unknown opcode";
6870 if (! mips16_autoextend
&& ! mips16_ext
)
6871 mips16_small
= true;
6873 if ((insn
= (struct mips_opcode
*) hash_find (mips16_op_hash
, str
)) == NULL
)
6875 insn_error
= "unrecognized opcode";
6882 assert (strcmp (insn
->name
, str
) == 0);
6885 ip
->insn_opcode
= insn
->match
;
6886 ip
->use_extend
= false;
6887 imm_expr
.X_op
= O_absent
;
6888 imm_reloc
= BFD_RELOC_UNUSED
;
6889 offset_expr
.X_op
= O_absent
;
6890 offset_reloc
= BFD_RELOC_UNUSED
;
6891 for (args
= insn
->args
; 1; ++args
)
6898 /* In this switch statement we call break if we did not find
6899 a match, continue if we did find a match, or return if we
6908 /* Stuff the immediate value in now, if we can. */
6909 if (imm_expr
.X_op
== O_constant
6910 && imm_reloc
> BFD_RELOC_UNUSED
6911 && insn
->pinfo
!= INSN_MACRO
)
6913 mips16_immed ((char *) NULL
, 0,
6914 imm_reloc
- BFD_RELOC_UNUSED
,
6915 imm_expr
.X_add_number
, true, mips16_small
,
6916 mips16_ext
, &ip
->insn_opcode
,
6917 &ip
->use_extend
, &ip
->extend
);
6918 imm_expr
.X_op
= O_absent
;
6919 imm_reloc
= BFD_RELOC_UNUSED
;
6933 ip
->insn_opcode
|= lastregno
<< MIPS16OP_SH_RX
;
6936 ip
->insn_opcode
|= lastregno
<< MIPS16OP_SH_RY
;
6952 ip
->insn_opcode
|= lastregno
<< MIPS16OP_SH_RX
;
6954 ip
->insn_opcode
|= lastregno
<< MIPS16OP_SH_RY
;
6981 while (isdigit (*s
));
6984 as_bad ("invalid register number (%d)", regno
);
6990 if (s
[1] == 'f' && s
[2] == 'p')
6995 else if (s
[1] == 's' && s
[2] == 'p')
7000 else if (s
[1] == 'g' && s
[2] == 'p')
7005 else if (s
[1] == 'a' && s
[2] == 't')
7010 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '0')
7015 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '1')
7028 if (c
== 'v' || c
== 'w')
7030 regno
= mips16_to_32_reg_map
[lastregno
];
7044 regno
= mips32_to_16_reg_map
[regno
];
7049 regno
= ILLEGAL_REG
;
7054 regno
= ILLEGAL_REG
;
7059 regno
= ILLEGAL_REG
;
7064 if (regno
== AT
&& ! mips_noat
)
7065 as_warn ("used $at without \".set noat\"");
7072 if (regno
== ILLEGAL_REG
)
7079 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_RX
;
7083 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_RY
;
7086 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_RZ
;
7089 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_MOVE32Z
;
7095 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_REGR32
;
7098 regno
= ((regno
& 7) << 2) | ((regno
& 0x18) >> 3);
7099 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_REG32R
;
7109 if (strncmp (s
, "$pc", 3) == 0)
7132 if (s
[0] == '$' && isdigit (s
[1]))
7134 /* Looks like a register name. */
7142 /* It looks like the expression was omitted before a
7143 register indirection, which means that the
7144 expression is implicitly zero. */
7148 my_getExpression (&imm_expr
, s
);
7149 /* We need to relax this instruction. */
7150 imm_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
7159 /* We use offset_reloc rather than imm_reloc for the PC
7160 relative operands. This lets macros with both
7161 immediate and address operands work correctly. */
7162 if (s
[0] == '$' && isdigit (s
[1]))
7164 /* Looks like a register name. */
7167 my_getExpression (&offset_expr
, s
);
7168 /* We need to relax this instruction. */
7169 offset_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
7173 case '6': /* break code */
7174 my_getExpression (&imm_expr
, s
);
7175 check_absolute_expr (ip
, &imm_expr
);
7176 if ((unsigned long) imm_expr
.X_add_number
> 63)
7178 as_warn ("Invalid value for `%s' (%lu)",
7180 (unsigned long) imm_expr
.X_add_number
);
7181 imm_expr
.X_add_number
&= 0x3f;
7183 ip
->insn_opcode
|= imm_expr
.X_add_number
<< MIPS16OP_SH_IMM6
;
7184 imm_expr
.X_op
= O_absent
;
7188 case 'a': /* 26 bit address */
7189 my_getExpression (&offset_expr
, s
);
7191 offset_reloc
= BFD_RELOC_MIPS16_JMP
;
7192 ip
->insn_opcode
<<= 16;
7195 case 'l': /* register list for entry macro */
7196 case 'L': /* register list for exit macro */
7208 while (*s
== ' ' || *s
== ',')
7212 as_bad ("can't parse register list");
7217 while (isdigit (*s
))
7234 while (isdigit (*s
))
7241 if (reg1
== 4 && reg2
>= 4 && reg2
<= 7 && c
!= 'L')
7242 mask
|= (reg2
- 3) << 3;
7243 else if (reg1
== 16 && reg2
>= 16 && reg2
<= 17)
7244 mask
|= (reg2
- 15) << 1;
7245 else if (reg1
== 31 && reg2
== 31)
7248 as_bad ("invalid register list");
7250 ip
->insn_opcode
|= mask
<< MIPS16OP_SH_IMM6
;
7260 /* Args don't match. */
7261 if (insn
+ 1 < &mips16_opcodes
[bfd_mips16_num_opcodes
] &&
7262 strcmp (insn
->name
, insn
[1].name
) == 0)
7269 insn_error
= "illegal operands";
7275 /* This structure holds information we know about a mips16 immediate
7278 struct mips16_immed_operand
7280 /* The type code used in the argument string in the opcode table. */
7282 /* The number of bits in the short form of the opcode. */
7284 /* The number of bits in the extended form of the opcode. */
7286 /* The amount by which the short form is shifted when it is used;
7287 for example, the sw instruction has a shift count of 2. */
7289 /* The amount by which the short form is shifted when it is stored
7290 into the instruction code. */
7292 /* Non-zero if the short form is unsigned. */
7294 /* Non-zero if the extended form is unsigned. */
7296 /* Non-zero if the value is PC relative. */
7300 /* The mips16 immediate operand types. */
7302 static const struct mips16_immed_operand mips16_immed_operands
[] =
7304 { '<', 3, 5, 0, MIPS16OP_SH_RZ
, 1, 1, 0 },
7305 { '>', 3, 5, 0, MIPS16OP_SH_RX
, 1, 1, 0 },
7306 { '[', 3, 6, 0, MIPS16OP_SH_RZ
, 1, 1, 0 },
7307 { ']', 3, 6, 0, MIPS16OP_SH_RX
, 1, 1, 0 },
7308 { '4', 4, 15, 0, MIPS16OP_SH_IMM4
, 0, 0, 0 },
7309 { '5', 5, 16, 0, MIPS16OP_SH_IMM5
, 1, 0, 0 },
7310 { 'H', 5, 16, 1, MIPS16OP_SH_IMM5
, 1, 0, 0 },
7311 { 'W', 5, 16, 2, MIPS16OP_SH_IMM5
, 1, 0, 0 },
7312 { 'D', 5, 16, 3, MIPS16OP_SH_IMM5
, 1, 0, 0 },
7313 { 'j', 5, 16, 0, MIPS16OP_SH_IMM5
, 0, 0, 0 },
7314 { '8', 8, 16, 0, MIPS16OP_SH_IMM8
, 1, 0, 0 },
7315 { 'V', 8, 16, 2, MIPS16OP_SH_IMM8
, 1, 0, 0 },
7316 { 'C', 8, 16, 3, MIPS16OP_SH_IMM8
, 1, 0, 0 },
7317 { 'U', 8, 16, 0, MIPS16OP_SH_IMM8
, 1, 1, 0 },
7318 { 'k', 8, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 0 },
7319 { 'K', 8, 16, 3, MIPS16OP_SH_IMM8
, 0, 0, 0 },
7320 { 'p', 8, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 1 },
7321 { 'q', 11, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 1 },
7322 { 'A', 8, 16, 2, MIPS16OP_SH_IMM8
, 1, 0, 1 },
7323 { 'B', 5, 16, 3, MIPS16OP_SH_IMM5
, 1, 0, 1 },
7324 { 'E', 5, 16, 2, MIPS16OP_SH_IMM5
, 1, 0, 1 }
7327 #define MIPS16_NUM_IMMED \
7328 (sizeof mips16_immed_operands / sizeof mips16_immed_operands[0])
7330 /* Handle a mips16 instruction with an immediate value. This or's the
7331 small immediate value into *INSN. It sets *USE_EXTEND to indicate
7332 whether an extended value is needed; if one is needed, it sets
7333 *EXTEND to the value. The argument type is TYPE. The value is VAL.
7334 If SMALL is true, an unextended opcode was explicitly requested.
7335 If EXT is true, an extended opcode was explicitly requested. If
7336 WARN is true, warn if EXT does not match reality. */
7339 mips16_immed (file
, line
, type
, val
, warn
, small
, ext
, insn
, use_extend
,
7348 unsigned long *insn
;
7349 boolean
*use_extend
;
7350 unsigned short *extend
;
7352 register const struct mips16_immed_operand
*op
;
7353 int mintiny
, maxtiny
;
7356 op
= mips16_immed_operands
;
7357 while (op
->type
!= type
)
7360 assert (op
< mips16_immed_operands
+ MIPS16_NUM_IMMED
);
7365 if (type
== '<' || type
== '>' || type
== '[' || type
== ']')
7368 maxtiny
= 1 << op
->nbits
;
7373 maxtiny
= (1 << op
->nbits
) - 1;
7378 mintiny
= - (1 << (op
->nbits
- 1));
7379 maxtiny
= (1 << (op
->nbits
- 1)) - 1;
7382 /* Branch offsets have an implicit 0 in the lowest bit. */
7383 if (type
== 'p' || type
== 'q')
7386 if ((val
& ((1 << op
->shift
) - 1)) != 0
7387 || val
< (mintiny
<< op
->shift
)
7388 || val
> (maxtiny
<< op
->shift
))
7393 if (warn
&& ext
&& ! needext
)
7394 as_warn_where (file
, line
, "extended operand requested but not required");
7395 if (small
&& needext
)
7396 as_bad_where (file
, line
, "invalid unextended operand value");
7398 if (small
|| (! ext
&& ! needext
))
7402 *use_extend
= false;
7403 insnval
= ((val
>> op
->shift
) & ((1 << op
->nbits
) - 1));
7404 insnval
<<= op
->op_shift
;
7409 long minext
, maxext
;
7415 maxext
= (1 << op
->extbits
) - 1;
7419 minext
= - (1 << (op
->extbits
- 1));
7420 maxext
= (1 << (op
->extbits
- 1)) - 1;
7422 if (val
< minext
|| val
> maxext
)
7423 as_bad_where (file
, line
,
7424 "operand value out of range for instruction");
7427 if (op
->extbits
== 16)
7429 extval
= ((val
>> 11) & 0x1f) | (val
& 0x7e0);
7432 else if (op
->extbits
== 15)
7434 extval
= ((val
>> 11) & 0xf) | (val
& 0x7f0);
7439 extval
= ((val
& 0x1f) << 6) | (val
& 0x20);
7443 *extend
= (unsigned short) extval
;
7452 my_getSmallExpression (ep
, str
)
7463 ((str
[1] == 'h' && str
[2] == 'i')
7464 || (str
[1] == 'H' && str
[2] == 'I')
7465 || (str
[1] == 'l' && str
[2] == 'o'))
7477 * A small expression may be followed by a base register.
7478 * Scan to the end of this operand, and then back over a possible
7479 * base register. Then scan the small expression up to that
7480 * point. (Based on code in sparc.c...)
7482 for (sp
= str
; *sp
&& *sp
!= ','; sp
++)
7484 if (sp
- 4 >= str
&& sp
[-1] == RP
)
7486 if (isdigit (sp
[-2]))
7488 for (sp
-= 3; sp
>= str
&& isdigit (*sp
); sp
--)
7490 if (*sp
== '$' && sp
> str
&& sp
[-1] == LP
)
7496 else if (sp
- 5 >= str
7499 && ((sp
[-3] == 'f' && sp
[-2] == 'p')
7500 || (sp
[-3] == 's' && sp
[-2] == 'p')
7501 || (sp
[-3] == 'g' && sp
[-2] == 'p')
7502 || (sp
[-3] == 'a' && sp
[-2] == 't')))
7508 /* no expression means zero offset */
7511 /* %xx(reg) is an error */
7512 ep
->X_op
= O_absent
;
7517 ep
->X_op
= O_constant
;
7520 ep
->X_add_symbol
= NULL
;
7521 ep
->X_op_symbol
= NULL
;
7522 ep
->X_add_number
= 0;
7527 my_getExpression (ep
, str
);
7534 my_getExpression (ep
, str
);
7535 return c
; /* => %hi or %lo encountered */
7539 my_getExpression (ep
, str
)
7545 save_in
= input_line_pointer
;
7546 input_line_pointer
= str
;
7548 expr_end
= input_line_pointer
;
7549 input_line_pointer
= save_in
;
7552 /* Turn a string in input_line_pointer into a floating point constant
7553 of type type, and store the appropriate bytes in *litP. The number
7554 of LITTLENUMS emitted is stored in *sizeP . An error message is
7555 returned, or NULL on OK. */
7558 md_atof (type
, litP
, sizeP
)
7564 LITTLENUM_TYPE words
[4];
7580 return "bad call to md_atof";
7583 t
= atof_ieee (input_line_pointer
, type
, words
);
7585 input_line_pointer
= t
;
7589 if (! target_big_endian
)
7591 for (i
= prec
- 1; i
>= 0; i
--)
7593 md_number_to_chars (litP
, (valueT
) words
[i
], 2);
7599 for (i
= 0; i
< prec
; i
++)
7601 md_number_to_chars (litP
, (valueT
) words
[i
], 2);
7610 md_number_to_chars (buf
, val
, n
)
7615 if (target_big_endian
)
7616 number_to_chars_bigendian (buf
, val
, n
);
7618 number_to_chars_littleendian (buf
, val
, n
);
7621 CONST
char *md_shortopts
= "O::g::G:";
7623 struct option md_longopts
[] = {
7624 #define OPTION_MIPS1 (OPTION_MD_BASE + 1)
7625 {"mips0", no_argument
, NULL
, OPTION_MIPS1
},
7626 {"mips1", no_argument
, NULL
, OPTION_MIPS1
},
7627 #define OPTION_MIPS2 (OPTION_MD_BASE + 2)
7628 {"mips2", no_argument
, NULL
, OPTION_MIPS2
},
7629 #define OPTION_MIPS3 (OPTION_MD_BASE + 3)
7630 {"mips3", no_argument
, NULL
, OPTION_MIPS3
},
7631 #define OPTION_MIPS4 (OPTION_MD_BASE + 4)
7632 {"mips4", no_argument
, NULL
, OPTION_MIPS4
},
7633 #define OPTION_MCPU (OPTION_MD_BASE + 5)
7634 {"mcpu", required_argument
, NULL
, OPTION_MCPU
},
7635 #define OPTION_MEMBEDDED_PIC (OPTION_MD_BASE + 6)
7636 {"membedded-pic", no_argument
, NULL
, OPTION_MEMBEDDED_PIC
},
7637 #define OPTION_TRAP (OPTION_MD_BASE + 9)
7638 {"trap", no_argument
, NULL
, OPTION_TRAP
},
7639 {"no-break", no_argument
, NULL
, OPTION_TRAP
},
7640 #define OPTION_BREAK (OPTION_MD_BASE + 10)
7641 {"break", no_argument
, NULL
, OPTION_BREAK
},
7642 {"no-trap", no_argument
, NULL
, OPTION_BREAK
},
7643 #define OPTION_EB (OPTION_MD_BASE + 11)
7644 {"EB", no_argument
, NULL
, OPTION_EB
},
7645 #define OPTION_EL (OPTION_MD_BASE + 12)
7646 {"EL", no_argument
, NULL
, OPTION_EL
},
7647 #define OPTION_M4650 (OPTION_MD_BASE + 13)
7648 {"m4650", no_argument
, NULL
, OPTION_M4650
},
7649 #define OPTION_NO_M4650 (OPTION_MD_BASE + 14)
7650 {"no-m4650", no_argument
, NULL
, OPTION_NO_M4650
},
7651 #define OPTION_M4010 (OPTION_MD_BASE + 15)
7652 {"m4010", no_argument
, NULL
, OPTION_M4010
},
7653 #define OPTION_NO_M4010 (OPTION_MD_BASE + 16)
7654 {"no-m4010", no_argument
, NULL
, OPTION_NO_M4010
},
7655 #define OPTION_M4100 (OPTION_MD_BASE + 17)
7656 {"m4100", no_argument
, NULL
, OPTION_M4100
},
7657 #define OPTION_NO_M4100 (OPTION_MD_BASE + 18)
7658 {"no-m4100", no_argument
, NULL
, OPTION_NO_M4100
},
7659 #define OPTION_MIPS16 (OPTION_MD_BASE + 22)
7660 {"mips16", no_argument
, NULL
, OPTION_MIPS16
},
7661 #define OPTION_NO_MIPS16 (OPTION_MD_BASE + 23)
7662 {"no-mips16", no_argument
, NULL
, OPTION_NO_MIPS16
},
7664 #define OPTION_CALL_SHARED (OPTION_MD_BASE + 7)
7665 #define OPTION_NON_SHARED (OPTION_MD_BASE + 8)
7666 #define OPTION_XGOT (OPTION_MD_BASE + 19)
7667 #define OPTION_32 (OPTION_MD_BASE + 20)
7668 #define OPTION_64 (OPTION_MD_BASE + 21)
7670 {"KPIC", no_argument
, NULL
, OPTION_CALL_SHARED
},
7671 {"xgot", no_argument
, NULL
, OPTION_XGOT
},
7672 {"call_shared", no_argument
, NULL
, OPTION_CALL_SHARED
},
7673 {"non_shared", no_argument
, NULL
, OPTION_NON_SHARED
},
7674 {"32", no_argument
, NULL
, OPTION_32
},
7675 {"64", no_argument
, NULL
, OPTION_64
},
7678 {NULL
, no_argument
, NULL
, 0}
7680 size_t md_longopts_size
= sizeof(md_longopts
);
7683 md_parse_option (c
, arg
)
7698 target_big_endian
= 1;
7702 target_big_endian
= 0;
7706 if (arg
&& arg
[1] == '0')
7716 mips_debug
= atoi (arg
);
7717 /* When the MIPS assembler sees -g or -g2, it does not do
7718 optimizations which limit full symbolic debugging. We take
7719 that to be equivalent to -O0. */
7720 if (mips_debug
== 2)
7752 /* Identify the processor type */
7754 if (strcmp (p
, "default") == 0
7755 || strcmp (p
, "DEFAULT") == 0)
7761 /* We need to cope with the various "vr" prefixes for the 4300
7763 if (*p
== 'v' || *p
== 'V')
7769 if (*p
== 'r' || *p
== 'R')
7776 if (strcmp (p
, "10000") == 0
7777 || strcmp (p
, "10k") == 0
7778 || strcmp (p
, "10K") == 0)
7783 if (strcmp (p
, "2000") == 0
7784 || strcmp (p
, "2k") == 0
7785 || strcmp (p
, "2K") == 0)
7790 if (strcmp (p
, "3000") == 0
7791 || strcmp (p
, "3k") == 0
7792 || strcmp (p
, "3K") == 0)
7797 if (strcmp (p
, "4000") == 0
7798 || strcmp (p
, "4k") == 0
7799 || strcmp (p
, "4K") == 0)
7801 else if (strcmp (p
, "4100") == 0)
7807 else if (strcmp (p
, "4300") == 0)
7809 else if (strcmp (p
, "4400") == 0)
7811 else if (strcmp (p
, "4600") == 0)
7813 else if (strcmp (p
, "4650") == 0)
7819 else if (strcmp (p
, "4010") == 0)
7828 if (strcmp (p
, "5000") == 0
7829 || strcmp (p
, "5k") == 0
7830 || strcmp (p
, "5K") == 0)
7835 if (strcmp (p
, "6000") == 0
7836 || strcmp (p
, "6k") == 0
7837 || strcmp (p
, "6K") == 0)
7842 if (strcmp (p
, "8000") == 0
7843 || strcmp (p
, "8k") == 0
7844 || strcmp (p
, "8K") == 0)
7849 if (strcmp (p
, "orion") == 0)
7854 if (sv
&& mips_cpu
!= 4300 && mips_cpu
!= 4100 && mips_cpu
!= 5000)
7856 as_bad ("ignoring invalid leading 'v' in -mcpu=%s switch", arg
);
7862 as_bad ("invalid architecture -mcpu=%s", arg
);
7873 case OPTION_NO_M4650
:
7881 case OPTION_NO_M4010
:
7889 case OPTION_NO_M4100
:
7895 mips_no_prev_insn ();
7898 case OPTION_NO_MIPS16
:
7900 mips_no_prev_insn ();
7903 case OPTION_MEMBEDDED_PIC
:
7904 mips_pic
= EMBEDDED_PIC
;
7905 if (USE_GLOBAL_POINTER_OPT
&& g_switch_seen
)
7907 as_bad ("-G may not be used with embedded PIC code");
7910 g_switch_value
= 0x7fffffff;
7913 /* When generating ELF code, we permit -KPIC and -call_shared to
7914 select SVR4_PIC, and -non_shared to select no PIC. This is
7915 intended to be compatible with Irix 5. */
7916 case OPTION_CALL_SHARED
:
7917 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
7919 as_bad ("-call_shared is supported only for ELF format");
7922 mips_pic
= SVR4_PIC
;
7923 if (g_switch_seen
&& g_switch_value
!= 0)
7925 as_bad ("-G may not be used with SVR4 PIC code");
7931 case OPTION_NON_SHARED
:
7932 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
7934 as_bad ("-non_shared is supported only for ELF format");
7940 /* The -xgot option tells the assembler to use 32 offsets when
7941 accessing the got in SVR4_PIC mode. It is for Irix
7948 if (! USE_GLOBAL_POINTER_OPT
)
7950 as_bad ("-G is not supported for this configuration");
7953 else if (mips_pic
== SVR4_PIC
|| mips_pic
== EMBEDDED_PIC
)
7955 as_bad ("-G may not be used with SVR4 or embedded PIC code");
7959 g_switch_value
= atoi (arg
);
7963 /* The -32 and -64 options tell the assembler to output the 32
7964 bit or the 64 bit MIPS ELF format. */
7971 const char **list
, **l
;
7973 list
= bfd_target_list ();
7974 for (l
= list
; *l
!= NULL
; l
++)
7975 if (strcmp (*l
, "elf64-bigmips") == 0
7976 || strcmp (*l
, "elf64-littlemips") == 0)
7979 as_fatal ("No compiled in support for 64 bit object file format");
7993 md_show_usage (stream
)
7998 -membedded-pic generate embedded position independent code\n\
7999 -EB generate big endian output\n\
8000 -EL generate little endian output\n\
8001 -g, -g2 do not remove uneeded NOPs or swap branches\n\
8002 -G NUM allow referencing objects up to NUM bytes\n\
8003 implicitly with the gp register [default 8]\n");
8005 -mips1, -mcpu=r{2,3}000 generate code for r2000 and r3000\n\
8006 -mips2, -mcpu=r6000 generate code for r6000\n\
8007 -mips3, -mcpu=r4000 generate code for r4000\n\
8008 -mips4, -mcpu=r8000 generate code for r8000\n\
8009 -mcpu=vr4300 generate code for vr4300\n\
8010 -mcpu=vr4100 generate code for vr4100\n\
8011 -m4650 permit R4650 instructions\n\
8012 -no-m4650 do not permit R4650 instructions\n\
8013 -m4010 permit R4010 instructions\n\
8014 -no-m4010 do not permit R4010 instructions\n\
8015 -m4100 permit VR4100 instructions\n\
8016 -no-m4100 do not permit VR4100 instructions\n");
8018 -mips16 generate mips16 instructions\n\
8019 -no-mips16 do not generate mips16 instructions\n");
8021 -O0 remove unneeded NOPs, do not swap branches\n\
8022 -O remove unneeded NOPs and swap branches\n\
8023 --trap, --no-break trap exception on div by 0 and mult overflow\n\
8024 --break, --no-trap break exception on div by 0 and mult overflow\n");
8027 -KPIC, -call_shared generate SVR4 position independent code\n\
8028 -non_shared do not generate position independent code\n\
8029 -xgot assume a 32 bit GOT\n\
8030 -32 create 32 bit object file (default)\n\
8031 -64 create 64 bit object file\n");
8036 md_pcrel_from (fixP
)
8039 if (OUTPUT_FLAVOR
!= bfd_target_aout_flavour
8040 && fixP
->fx_addsy
!= (symbolS
*) NULL
8041 && ! S_IS_DEFINED (fixP
->fx_addsy
))
8043 /* This makes a branch to an undefined symbol be a branch to the
8044 current location. */
8048 /* return the address of the delay slot */
8049 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
8052 /* This is called by emit_expr via TC_CONS_FIX_NEW when creating a
8053 reloc for a cons. We could use the definition there, except that
8054 we want to handle 64 bit relocs specially. */
8057 cons_fix_new_mips (frag
, where
, nbytes
, exp
)
8060 unsigned int nbytes
;
8064 /* If we are assembling in 32 bit mode, turn an 8 byte reloc into a
8066 if (nbytes
== 8 && ! mips_64
)
8068 if (target_big_endian
)
8074 if (nbytes
!= 2 && nbytes
!= 4 && nbytes
!= 8)
8075 as_bad ("Unsupported reloc size %d", nbytes
);
8077 fix_new_exp (frag_now
, where
, (int) nbytes
, exp
, 0,
8080 : (nbytes
== 4 ? BFD_RELOC_32
: BFD_RELOC_64
)));
8083 /* Sort any unmatched HI16_S relocs so that they immediately precede
8084 the corresponding LO reloc. This is called before md_apply_fix and
8085 tc_gen_reloc. Unmatched HI16_S relocs can only be generated by
8086 explicit use of the %hi modifier. */
8091 struct mips_hi_fixup
*l
;
8093 for (l
= mips_hi_fixup_list
; l
!= NULL
; l
= l
->next
)
8095 segment_info_type
*seginfo
;
8098 assert (l
->fixp
->fx_r_type
== BFD_RELOC_HI16_S
);
8100 /* Check quickly whether the next fixup happens to be a matching
8102 if (l
->fixp
->fx_next
!= NULL
8103 && l
->fixp
->fx_next
->fx_r_type
== BFD_RELOC_LO16
8104 && l
->fixp
->fx_addsy
== l
->fixp
->fx_next
->fx_addsy
8105 && l
->fixp
->fx_offset
== l
->fixp
->fx_next
->fx_offset
)
8108 /* Look through the fixups for this segment for a matching %lo.
8109 When we find one, move the %hi just in front of it. We do
8110 this in two passes. In the first pass, we try to find a
8111 unique %lo. In the second pass, we permit multiple %hi
8112 relocs for a single %lo (this is a GNU extension). */
8113 seginfo
= seg_info (l
->seg
);
8114 for (pass
= 0; pass
< 2; pass
++)
8119 for (f
= seginfo
->fix_root
; f
!= NULL
; f
= f
->fx_next
)
8121 /* Check whether this is a %lo fixup which matches l->fixp. */
8122 if (f
->fx_r_type
== BFD_RELOC_LO16
8123 && f
->fx_addsy
== l
->fixp
->fx_addsy
8124 && f
->fx_offset
== l
->fixp
->fx_offset
8127 || prev
->fx_r_type
!= BFD_RELOC_HI16_S
8128 || prev
->fx_addsy
!= f
->fx_addsy
8129 || prev
->fx_offset
!= f
->fx_offset
))
8133 /* Move l->fixp before f. */
8134 for (pf
= &seginfo
->fix_root
;
8136 pf
= &(*pf
)->fx_next
)
8137 assert (*pf
!= NULL
);
8139 *pf
= l
->fixp
->fx_next
;
8141 l
->fixp
->fx_next
= f
;
8143 seginfo
->fix_root
= l
->fixp
;
8145 prev
->fx_next
= l
->fixp
;
8157 as_warn_where (l
->fixp
->fx_file
, l
->fixp
->fx_line
,
8158 "Unmatched %%hi reloc");
8163 /* When generating embedded PIC code we need to use a special
8164 relocation to represent the difference of two symbols in the .text
8165 section (switch tables use a difference of this sort). See
8166 include/coff/mips.h for details. This macro checks whether this
8167 fixup requires the special reloc. */
8168 #define SWITCH_TABLE(fixp) \
8169 ((fixp)->fx_r_type == BFD_RELOC_32 \
8170 && (fixp)->fx_addsy != NULL \
8171 && (fixp)->fx_subsy != NULL \
8172 && S_GET_SEGMENT ((fixp)->fx_addsy) == text_section \
8173 && S_GET_SEGMENT ((fixp)->fx_subsy) == text_section)
8175 /* When generating embedded PIC code we must keep all PC relative
8176 relocations, in case the linker has to relax a call. We also need
8177 to keep relocations for switch table entries. */
8181 mips_force_relocation (fixp
)
8184 return (mips_pic
== EMBEDDED_PIC
8186 || SWITCH_TABLE (fixp
)
8187 || fixp
->fx_r_type
== BFD_RELOC_PCREL_HI16_S
8188 || fixp
->fx_r_type
== BFD_RELOC_PCREL_LO16
));
8191 /* Apply a fixup to the object file. */
8194 md_apply_fix (fixP
, valueP
)
8201 assert (fixP
->fx_size
== 4
8202 || fixP
->fx_r_type
== BFD_RELOC_16
8203 || fixP
->fx_r_type
== BFD_RELOC_64
);
8206 fixP
->fx_addnumber
= value
; /* Remember value for tc_gen_reloc */
8208 if (fixP
->fx_addsy
== NULL
&& ! fixP
->fx_pcrel
)
8211 switch (fixP
->fx_r_type
)
8213 case BFD_RELOC_MIPS_JMP
:
8214 case BFD_RELOC_HI16
:
8215 case BFD_RELOC_HI16_S
:
8216 case BFD_RELOC_MIPS_GPREL
:
8217 case BFD_RELOC_MIPS_LITERAL
:
8218 case BFD_RELOC_MIPS_CALL16
:
8219 case BFD_RELOC_MIPS_GOT16
:
8220 case BFD_RELOC_MIPS_GPREL32
:
8221 case BFD_RELOC_MIPS_GOT_HI16
:
8222 case BFD_RELOC_MIPS_GOT_LO16
:
8223 case BFD_RELOC_MIPS_CALL_HI16
:
8224 case BFD_RELOC_MIPS_CALL_LO16
:
8226 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
8227 "Invalid PC relative reloc");
8228 /* Nothing needed to do. The value comes from the reloc entry */
8231 case BFD_RELOC_MIPS16_JMP
:
8232 /* We currently always generate a reloc against a symbol, which
8233 means that we don't want an addend even if the symbol is
8235 fixP
->fx_addnumber
= 0;
8238 case BFD_RELOC_PCREL_HI16_S
:
8239 /* The addend for this is tricky if it is internal, so we just
8240 do everything here rather than in bfd_perform_relocation. */
8241 if ((fixP
->fx_addsy
->bsym
->flags
& BSF_SECTION_SYM
) == 0)
8243 /* For an external symbol adjust by the address to make it
8244 pcrel_offset. We use the address of the RELLO reloc
8245 which follows this one. */
8246 value
+= (fixP
->fx_next
->fx_frag
->fr_address
8247 + fixP
->fx_next
->fx_where
);
8252 buf
= (unsigned char *) fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
8253 if (target_big_endian
)
8255 md_number_to_chars (buf
, value
, 2);
8258 case BFD_RELOC_PCREL_LO16
:
8259 /* The addend for this is tricky if it is internal, so we just
8260 do everything here rather than in bfd_perform_relocation. */
8261 if ((fixP
->fx_addsy
->bsym
->flags
& BSF_SECTION_SYM
) == 0)
8262 value
+= fixP
->fx_frag
->fr_address
+ fixP
->fx_where
;
8263 buf
= (unsigned char *) fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
8264 if (target_big_endian
)
8266 md_number_to_chars (buf
, value
, 2);
8270 /* This is handled like BFD_RELOC_32, but we output a sign
8271 extended value if we are only 32 bits. */
8273 || (mips_pic
== EMBEDDED_PIC
&& SWITCH_TABLE (fixP
)))
8275 if (8 <= sizeof (valueT
))
8276 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
,
8283 w1
= w2
= fixP
->fx_where
;
8284 if (target_big_endian
)
8288 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ w1
, value
, 4);
8289 if ((value
& 0x80000000) != 0)
8293 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ w2
, hiv
, 4);
8299 /* If we are deleting this reloc entry, we must fill in the
8300 value now. This can happen if we have a .word which is not
8301 resolved when it appears but is later defined. We also need
8302 to fill in the value if this is an embedded PIC switch table
8305 || (mips_pic
== EMBEDDED_PIC
&& SWITCH_TABLE (fixP
)))
8306 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
,
8311 /* If we are deleting this reloc entry, we must fill in the
8313 assert (fixP
->fx_size
== 2);
8315 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
,
8319 case BFD_RELOC_LO16
:
8320 /* When handling an embedded PIC switch statement, we can wind
8321 up deleting a LO16 reloc. See the 'o' case in mips_ip. */
8324 if (value
< -0x8000 || value
> 0x7fff)
8325 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
8326 "relocation overflow");
8327 buf
= (unsigned char *) fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
8328 if (target_big_endian
)
8330 md_number_to_chars (buf
, value
, 2);
8334 case BFD_RELOC_16_PCREL_S2
:
8336 * We need to save the bits in the instruction since fixup_segment()
8337 * might be deleting the relocation entry (i.e., a branch within
8338 * the current segment).
8340 if ((value
& 0x3) != 0)
8341 as_warn_where (fixP
->fx_file
, fixP
->fx_line
,
8342 "Branch to odd address (%lx)", value
);
8345 /* update old instruction data */
8346 buf
= (unsigned char *) (fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
);
8347 if (target_big_endian
)
8348 insn
= (buf
[0] << 24) | (buf
[1] << 16) | (buf
[2] << 8) | buf
[3];
8350 insn
= (buf
[3] << 24) | (buf
[2] << 16) | (buf
[1] << 8) | buf
[0];
8352 if (value
>= -0x8000 && value
< 0x8000)
8353 insn
|= value
& 0xffff;
8356 /* The branch offset is too large. If this is an
8357 unconditional branch, and we are not generating PIC code,
8358 we can convert it to an absolute jump instruction. */
8359 if (mips_pic
== NO_PIC
8361 && fixP
->fx_frag
->fr_address
>= text_section
->vma
8362 && (fixP
->fx_frag
->fr_address
8363 < text_section
->vma
+ text_section
->_raw_size
)
8364 && ((insn
& 0xffff0000) == 0x10000000 /* beq $0,$0 */
8365 || (insn
& 0xffff0000) == 0x04010000 /* bgez $0 */
8366 || (insn
& 0xffff0000) == 0x04110000)) /* bgezal $0 */
8368 if ((insn
& 0xffff0000) == 0x04110000) /* bgezal $0 */
8369 insn
= 0x0c000000; /* jal */
8371 insn
= 0x08000000; /* j */
8372 fixP
->fx_r_type
= BFD_RELOC_MIPS_JMP
;
8374 fixP
->fx_addsy
= section_symbol (text_section
);
8375 fixP
->fx_addnumber
= (value
<< 2) + md_pcrel_from (fixP
);
8379 /* FIXME. It would be possible in principle to handle
8380 conditional branches which overflow. They could be
8381 transformed into a branch around a jump. This would
8382 require setting up variant frags for each different
8383 branch type. The native MIPS assembler attempts to
8384 handle these cases, but it appears to do it
8386 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
8387 "Relocation overflow");
8391 md_number_to_chars ((char *) buf
, (valueT
) insn
, 4);
8406 const struct mips_opcode
*p
;
8407 int treg
, sreg
, dreg
, shamt
;
8412 for (i
= 0; i
< NUMOPCODES
; ++i
)
8414 p
= &mips_opcodes
[i
];
8415 if (((oc
& p
->mask
) == p
->match
) && (p
->pinfo
!= INSN_MACRO
))
8417 printf ("%08lx %s\t", oc
, p
->name
);
8418 treg
= (oc
>> 16) & 0x1f;
8419 sreg
= (oc
>> 21) & 0x1f;
8420 dreg
= (oc
>> 11) & 0x1f;
8421 shamt
= (oc
>> 6) & 0x1f;
8423 for (args
= p
->args
;; ++args
)
8434 printf ("%c", *args
);
8438 assert (treg
== sreg
);
8439 printf ("$%d,$%d", treg
, sreg
);
8444 printf ("$%d", dreg
);
8449 printf ("$%d", treg
);
8453 printf ("0x%x", treg
);
8458 printf ("$%d", sreg
);
8462 printf ("0x%08lx", oc
& 0x1ffffff);
8474 printf ("$%d", shamt
);
8485 printf ("%08lx UNDEFINED\n", oc
);
8496 name
= input_line_pointer
;
8497 c
= get_symbol_end ();
8498 p
= (symbolS
*) symbol_find_or_make (name
);
8499 *input_line_pointer
= c
;
8503 /* Align the current frag to a given power of two. The MIPS assembler
8504 also automatically adjusts any preceding label. */
8507 mips_align (to
, fill
, label
)
8512 mips_emit_delays (false);
8513 frag_align (to
, fill
);
8514 record_alignment (now_seg
, to
);
8517 assert (S_GET_SEGMENT (label
) == now_seg
);
8518 label
->sy_frag
= frag_now
;
8519 S_SET_VALUE (label
, (valueT
) frag_now_fix ());
8523 /* Align to a given power of two. .align 0 turns off the automatic
8524 alignment used by the data creating pseudo-ops. */
8531 register long temp_fill
;
8532 long max_alignment
= 15;
8536 o Note that the assembler pulls down any immediately preceeding label
8537 to the aligned address.
8538 o It's not documented but auto alignment is reinstated by
8539 a .align pseudo instruction.
8540 o Note also that after auto alignment is turned off the mips assembler
8541 issues an error on attempt to assemble an improperly aligned data item.
8546 temp
= get_absolute_expression ();
8547 if (temp
> max_alignment
)
8548 as_bad ("Alignment too large: %d. assumed.", temp
= max_alignment
);
8551 as_warn ("Alignment negative: 0 assumed.");
8554 if (*input_line_pointer
== ',')
8556 input_line_pointer
++;
8557 temp_fill
= get_absolute_expression ();
8564 mips_align (temp
, (int) temp_fill
,
8565 insn_labels
!= NULL
? insn_labels
->label
: NULL
);
8572 demand_empty_rest_of_line ();
8576 mips_flush_pending_output ()
8578 mips_emit_delays (false);
8579 mips_clear_insn_labels ();
8588 /* When generating embedded PIC code, we only use the .text, .lit8,
8589 .sdata and .sbss sections. We change the .data and .rdata
8590 pseudo-ops to use .sdata. */
8591 if (mips_pic
== EMBEDDED_PIC
8592 && (sec
== 'd' || sec
== 'r'))
8595 mips_emit_delays (false);
8605 subseg_set (bss_section
, (subsegT
) get_absolute_expression ());
8606 demand_empty_rest_of_line ();
8610 if (USE_GLOBAL_POINTER_OPT
)
8612 seg
= subseg_new (RDATA_SECTION_NAME
,
8613 (subsegT
) get_absolute_expression ());
8614 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
8616 bfd_set_section_flags (stdoutput
, seg
,
8622 if (strcmp (TARGET_OS
, "elf") != 0)
8623 bfd_set_section_alignment (stdoutput
, seg
, 4);
8625 demand_empty_rest_of_line ();
8629 as_bad ("No read only data section in this object file format");
8630 demand_empty_rest_of_line ();
8636 if (USE_GLOBAL_POINTER_OPT
)
8638 seg
= subseg_new (".sdata", (subsegT
) get_absolute_expression ());
8639 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
8641 bfd_set_section_flags (stdoutput
, seg
,
8642 SEC_ALLOC
| SEC_LOAD
| SEC_RELOC
8644 if (strcmp (TARGET_OS
, "elf") != 0)
8645 bfd_set_section_alignment (stdoutput
, seg
, 4);
8647 demand_empty_rest_of_line ();
8652 as_bad ("Global pointers not supported; recompile -G 0");
8653 demand_empty_rest_of_line ();
8662 mips_enable_auto_align ()
8673 label
= insn_labels
!= NULL
? insn_labels
->label
: NULL
;
8674 mips_emit_delays (false);
8675 if (log_size
> 0 && auto_align
)
8676 mips_align (log_size
, 0, label
);
8677 mips_clear_insn_labels ();
8678 cons (1 << log_size
);
8687 label
= insn_labels
!= NULL
? insn_labels
->label
: NULL
;
8689 mips_emit_delays (false);
8693 mips_align (3, 0, label
);
8695 mips_align (2, 0, label
);
8697 mips_clear_insn_labels ();
8702 /* Handle .globl. We need to override it because on Irix 5 you are
8705 where foo is an undefined symbol, to mean that foo should be
8706 considered to be the address of a function. */
8717 name
= input_line_pointer
;
8718 c
= get_symbol_end ();
8719 symbolP
= symbol_find_or_make (name
);
8720 *input_line_pointer
= c
;
8723 /* On Irix 5, every global symbol that is not explicitly labelled as
8724 being a function is apparently labelled as being an object. */
8727 if (! is_end_of_line
[(unsigned char) *input_line_pointer
])
8732 secname
= input_line_pointer
;
8733 c
= get_symbol_end ();
8734 sec
= bfd_get_section_by_name (stdoutput
, secname
);
8736 as_bad ("%s: no such section", secname
);
8737 *input_line_pointer
= c
;
8739 if (sec
!= NULL
&& (sec
->flags
& SEC_CODE
) != 0)
8740 flag
= BSF_FUNCTION
;
8743 symbolP
->bsym
->flags
|= flag
;
8745 S_SET_EXTERNAL (symbolP
);
8746 demand_empty_rest_of_line ();
8756 opt
= input_line_pointer
;
8757 c
= get_symbol_end ();
8761 /* FIXME: What does this mean? */
8763 else if (strncmp (opt
, "pic", 3) == 0)
8771 mips_pic
= SVR4_PIC
;
8773 as_bad (".option pic%d not supported", i
);
8775 if (USE_GLOBAL_POINTER_OPT
&& mips_pic
== SVR4_PIC
)
8777 if (g_switch_seen
&& g_switch_value
!= 0)
8778 as_warn ("-G may not be used with SVR4 PIC code");
8780 bfd_set_gp_size (stdoutput
, 0);
8784 as_warn ("Unrecognized option \"%s\"", opt
);
8786 *input_line_pointer
= c
;
8787 demand_empty_rest_of_line ();
8794 char *name
= input_line_pointer
, ch
;
8796 while (!is_end_of_line
[(unsigned char) *input_line_pointer
])
8797 input_line_pointer
++;
8798 ch
= *input_line_pointer
;
8799 *input_line_pointer
= '\0';
8801 if (strcmp (name
, "reorder") == 0)
8805 prev_insn_unreordered
= 1;
8806 prev_prev_insn_unreordered
= 1;
8810 else if (strcmp (name
, "noreorder") == 0)
8812 mips_emit_delays (true);
8814 mips_any_noreorder
= 1;
8816 else if (strcmp (name
, "at") == 0)
8820 else if (strcmp (name
, "noat") == 0)
8824 else if (strcmp (name
, "macro") == 0)
8826 mips_warn_about_macros
= 0;
8828 else if (strcmp (name
, "nomacro") == 0)
8830 if (mips_noreorder
== 0)
8831 as_bad ("`noreorder' must be set before `nomacro'");
8832 mips_warn_about_macros
= 1;
8834 else if (strcmp (name
, "move") == 0 || strcmp (name
, "novolatile") == 0)
8838 else if (strcmp (name
, "nomove") == 0 || strcmp (name
, "volatile") == 0)
8842 else if (strcmp (name
, "bopt") == 0)
8846 else if (strcmp (name
, "nobopt") == 0)
8850 else if (strcmp (name
, "mips16") == 0
8851 || strcmp (name
, "MIPS-16") == 0)
8853 else if (strcmp (name
, "nomips16") == 0
8854 || strcmp (name
, "noMIPS-16") == 0)
8856 else if (strncmp (name
, "mips", 4) == 0)
8860 /* Permit the user to change the ISA on the fly. Needless to
8861 say, misuse can cause serious problems. */
8862 isa
= atoi (name
+ 4);
8864 mips_isa
= file_mips_isa
;
8865 else if (isa
< 1 || isa
> 4)
8866 as_bad ("unknown ISA level");
8870 else if (strcmp (name
, "autoextend") == 0)
8871 mips16_autoextend
= 1;
8872 else if (strcmp (name
, "noautoextend") == 0)
8873 mips16_autoextend
= 0;
8876 as_warn ("Tried to set unrecognized symbol: %s\n", name
);
8878 *input_line_pointer
= ch
;
8879 demand_empty_rest_of_line ();
8882 /* Handle the .abicalls pseudo-op. I believe this is equivalent to
8883 .option pic2. It means to generate SVR4 PIC calls. */
8889 mips_pic
= SVR4_PIC
;
8890 if (USE_GLOBAL_POINTER_OPT
)
8892 if (g_switch_seen
&& g_switch_value
!= 0)
8893 as_warn ("-G may not be used with SVR4 PIC code");
8896 bfd_set_gp_size (stdoutput
, 0);
8897 demand_empty_rest_of_line ();
8900 /* Handle the .cpload pseudo-op. This is used when generating SVR4
8901 PIC code. It sets the $gp register for the function based on the
8902 function address, which is in the register named in the argument.
8903 This uses a relocation against _gp_disp, which is handled specially
8904 by the linker. The result is:
8905 lui $gp,%hi(_gp_disp)
8906 addiu $gp,$gp,%lo(_gp_disp)
8907 addu $gp,$gp,.cpload argument
8908 The .cpload argument is normally $25 == $t9. */
8917 /* If we are not generating SVR4 PIC code, .cpload is ignored. */
8918 if (mips_pic
!= SVR4_PIC
)
8924 /* .cpload should be a in .set noreorder section. */
8925 if (mips_noreorder
== 0)
8926 as_warn (".cpload not in noreorder section");
8929 ex
.X_add_symbol
= symbol_find_or_make ("_gp_disp");
8930 ex
.X_op_symbol
= NULL
;
8931 ex
.X_add_number
= 0;
8933 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
8934 ex
.X_add_symbol
->bsym
->flags
|= BSF_OBJECT
;
8936 macro_build_lui ((char *) NULL
, &icnt
, &ex
, GP
);
8937 macro_build ((char *) NULL
, &icnt
, &ex
, "addiu", "t,r,j", GP
, GP
,
8938 (int) BFD_RELOC_LO16
);
8940 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "addu", "d,v,t",
8941 GP
, GP
, tc_get_register (0));
8943 demand_empty_rest_of_line ();
8946 /* Handle the .cprestore pseudo-op. This stores $gp into a given
8947 offset from $sp. The offset is remembered, and after making a PIC
8948 call $gp is restored from that location. */
8951 s_cprestore (ignore
)
8957 /* If we are not generating SVR4 PIC code, .cprestore is ignored. */
8958 if (mips_pic
!= SVR4_PIC
)
8964 mips_cprestore_offset
= get_absolute_expression ();
8966 ex
.X_op
= O_constant
;
8967 ex
.X_add_symbol
= NULL
;
8968 ex
.X_op_symbol
= NULL
;
8969 ex
.X_add_number
= mips_cprestore_offset
;
8971 macro_build ((char *) NULL
, &icnt
, &ex
,
8972 mips_isa
< 3 ? "sw" : "sd",
8973 "t,o(b)", GP
, (int) BFD_RELOC_LO16
, SP
);
8975 demand_empty_rest_of_line ();
8978 /* Handle the .gpword pseudo-op. This is used when generating PIC
8979 code. It generates a 32 bit GP relative reloc. */
8989 /* When not generating PIC code, this is treated as .word. */
8990 if (mips_pic
!= SVR4_PIC
)
8996 label
= insn_labels
!= NULL
? insn_labels
->label
: NULL
;
8997 mips_emit_delays (true);
8999 mips_align (2, 0, label
);
9000 mips_clear_insn_labels ();
9004 if (ex
.X_op
!= O_symbol
|| ex
.X_add_number
!= 0)
9006 as_bad ("Unsupported use of .gpword");
9007 ignore_rest_of_line ();
9011 md_number_to_chars (p
, (valueT
) 0, 4);
9012 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 4, &ex
, 0,
9013 BFD_RELOC_MIPS_GPREL32
);
9015 demand_empty_rest_of_line ();
9018 /* Handle the .cpadd pseudo-op. This is used when dealing with switch
9019 tables in SVR4 PIC code. */
9028 /* This is ignored when not generating SVR4 PIC code. */
9029 if (mips_pic
!= SVR4_PIC
)
9035 /* Add $gp to the register named as an argument. */
9036 reg
= tc_get_register (0);
9037 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
9038 mips_isa
< 3 ? "addu" : "daddu",
9039 "d,v,t", reg
, reg
, GP
);
9041 demand_empty_rest_of_line ();
9044 /* Parse a register string into a number. Called from the ECOFF code
9045 to parse .frame. The argument is non-zero if this is the frame
9046 register, so that we can record it in mips_frame_reg. */
9049 tc_get_register (frame
)
9055 if (*input_line_pointer
++ != '$')
9057 as_warn ("expected `$'");
9060 else if (isdigit ((unsigned char) *input_line_pointer
))
9062 reg
= get_absolute_expression ();
9063 if (reg
< 0 || reg
>= 32)
9065 as_warn ("Bad register number");
9071 if (strncmp (input_line_pointer
, "fp", 2) == 0)
9073 else if (strncmp (input_line_pointer
, "sp", 2) == 0)
9075 else if (strncmp (input_line_pointer
, "gp", 2) == 0)
9077 else if (strncmp (input_line_pointer
, "at", 2) == 0)
9081 as_warn ("Unrecognized register name");
9084 input_line_pointer
+= 2;
9087 mips_frame_reg
= reg
!= 0 ? reg
: SP
;
9092 md_section_align (seg
, addr
)
9096 int align
= bfd_get_section_alignment (stdoutput
, seg
);
9099 /* We don't need to align ELF sections to the full alignment.
9100 However, Irix 5 may prefer that we align them at least to a 16
9101 byte boundary. We don't bother to align the sections if we are
9102 targeted for an embedded system. */
9103 if (strcmp (TARGET_OS
, "elf") == 0)
9109 return ((addr
+ (1 << align
) - 1) & (-1 << align
));
9112 /* Utility routine, called from above as well. If called while the
9113 input file is still being read, it's only an approximation. (For
9114 example, a symbol may later become defined which appeared to be
9115 undefined earlier.) */
9118 nopic_need_relax (sym
)
9124 if (USE_GLOBAL_POINTER_OPT
)
9126 const char *symname
;
9129 /* Find out whether this symbol can be referenced off the GP
9130 register. It can be if it is smaller than the -G size or if
9131 it is in the .sdata or .sbss section. Certain symbols can
9132 not be referenced off the GP, although it appears as though
9134 symname
= S_GET_NAME (sym
);
9135 if (symname
!= (const char *) NULL
9136 && (strcmp (symname
, "eprol") == 0
9137 || strcmp (symname
, "etext") == 0
9138 || strcmp (symname
, "_gp") == 0
9139 || strcmp (symname
, "edata") == 0
9140 || strcmp (symname
, "_fbss") == 0
9141 || strcmp (symname
, "_fdata") == 0
9142 || strcmp (symname
, "_ftext") == 0
9143 || strcmp (symname
, "end") == 0
9144 || strcmp (symname
, "_gp_disp") == 0))
9146 else if (! S_IS_DEFINED (sym
)
9148 #ifndef NO_ECOFF_DEBUGGING
9149 || (sym
->ecoff_extern_size
!= 0
9150 && sym
->ecoff_extern_size
<= g_switch_value
)
9152 || (S_GET_VALUE (sym
) != 0
9153 && S_GET_VALUE (sym
) <= g_switch_value
)))
9157 const char *segname
;
9159 segname
= segment_name (S_GET_SEGMENT (sym
));
9160 assert (strcmp (segname
, ".lit8") != 0
9161 && strcmp (segname
, ".lit4") != 0);
9162 change
= (strcmp (segname
, ".sdata") != 0
9163 && strcmp (segname
, ".sbss") != 0);
9168 /* We are not optimizing for the GP register. */
9172 /* Given a mips16 variant frag FRAGP, return non-zero if it needs an
9173 extended opcode. SEC is the section the frag is in. */
9176 mips16_extended_frag (fragp
, sec
, stretch
)
9182 register const struct mips16_immed_operand
*op
;
9184 int mintiny
, maxtiny
;
9187 if (RELAX_MIPS16_USER_SMALL (fragp
->fr_subtype
))
9189 if (RELAX_MIPS16_USER_EXT (fragp
->fr_subtype
))
9192 type
= RELAX_MIPS16_TYPE (fragp
->fr_subtype
);
9193 op
= mips16_immed_operands
;
9194 while (op
->type
!= type
)
9197 assert (op
< mips16_immed_operands
+ MIPS16_NUM_IMMED
);
9202 if (type
== '<' || type
== '>' || type
== '[' || type
== ']')
9205 maxtiny
= 1 << op
->nbits
;
9210 maxtiny
= (1 << op
->nbits
) - 1;
9215 mintiny
= - (1 << (op
->nbits
- 1));
9216 maxtiny
= (1 << (op
->nbits
- 1)) - 1;
9219 /* We can't call S_GET_VALUE here, because we don't want to lock in
9220 a particular frag address. */
9221 if (fragp
->fr_symbol
->sy_value
.X_op
== O_constant
)
9223 val
= (fragp
->fr_symbol
->sy_value
.X_add_number
9224 + fragp
->fr_symbol
->sy_frag
->fr_address
);
9225 symsec
= S_GET_SEGMENT (fragp
->fr_symbol
);
9227 else if (fragp
->fr_symbol
->sy_value
.X_op
== O_symbol
9228 && (fragp
->fr_symbol
->sy_value
.X_add_symbol
->sy_value
.X_op
9231 val
= (fragp
->fr_symbol
->sy_value
.X_add_symbol
->sy_value
.X_add_number
9232 + fragp
->fr_symbol
->sy_value
.X_add_symbol
->sy_frag
->fr_address
9233 + fragp
->fr_symbol
->sy_value
.X_add_number
9234 + fragp
->fr_symbol
->sy_frag
->fr_address
);
9235 symsec
= S_GET_SEGMENT (fragp
->fr_symbol
->sy_value
.X_add_symbol
);
9244 /* We won't have the section when we are called from
9245 mips_relax_frag. However, we will always have been called
9246 from md_estimate_size_before_relax first. If this is a
9247 branch to a different section, we mark it as such. If SEC is
9248 NULL, and the frag is not marked, then it must be a branch to
9249 the same section. */
9252 if (RELAX_MIPS16_LONG_BRANCH (fragp
->fr_subtype
))
9260 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
9262 /* FIXME: We should support this, and let the linker
9263 catch branches and loads that are out of range. */
9264 as_bad_where (fragp
->fr_file
, fragp
->fr_line
,
9265 "unsupported PC relative reference to different section");
9271 /* In this case, we know for sure that the symbol fragment is in
9272 the same section. If the fr_address of the symbol fragment
9273 is greater then the address of this fragment we want to add
9274 in STRETCH in order to get a better estimate of the address.
9275 This particularly matters because of the shift bits. */
9277 && fragp
->fr_symbol
->sy_frag
->fr_address
>= fragp
->fr_address
)
9281 /* Adjust stretch for any alignment frag. */
9282 for (f
= fragp
; f
!= fragp
->fr_symbol
->sy_frag
; f
= f
->fr_next
)
9285 if (f
->fr_type
== rs_align
|| f
->fr_type
== rs_align_code
)
9288 stretch
= - ((- stretch
)
9289 & ~ ((1 << (int) f
->fr_offset
) - 1));
9291 stretch
&= ~ ((1 << (int) f
->fr_offset
) - 1);
9299 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
9301 /* The base address rules are complicated. The base address of
9302 a branch is the following instruction. The base address of a
9303 PC relative load or add is the instruction itself, but if it
9304 is extended add 2, and if it is in a delay slot (in which
9305 case it can not be extended) use the address of the
9306 instruction whose delay slot it is in. */
9307 if (type
== 'p' || type
== 'q')
9310 /* Ignore the low bit in the target, since it will be set
9311 for a text label. */
9315 else if (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
))
9317 else if (RELAX_MIPS16_DSLOT (fragp
->fr_subtype
))
9320 /* If we are currently assuming that this frag should be
9321 extended, then the current address is two bytes higher. */
9322 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
9325 val
-= addr
& ~ ((1 << op
->shift
) - 1);
9327 /* Branch offsets have an implicit 0 in the lowest bit. */
9328 if (type
== 'p' || type
== 'q')
9331 /* If any of the shifted bits are set, we must use an extended
9332 opcode. If the address depends on the size of this
9333 instruction, this can lead to a loop, so we arrange to always
9334 use an extended opcode. We only check this when we are in
9335 the main relaxation loop, when SEC is NULL. */
9336 if ((val
& ((1 << op
->shift
) - 1)) != 0 && sec
== NULL
)
9339 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
9343 /* If we are about to mark a frag as extended because the value
9344 is precisely maxtiny + 1, then there is a chance of an
9345 infinite loop as in the following code:
9350 In this case when the la is extended, foo is 0x3fc bytes
9351 away, so the la can be shrunk, but then foo is 0x400 away, so
9352 the la must be extended. To avoid this loop, we mark the
9353 frag as extended if it was small, and is about to become
9354 extended with a value of maxtiny + 1. */
9355 if (val
== ((maxtiny
+ 1) << op
->shift
)
9356 && ! RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
)
9360 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
9364 else if (symsec
!= absolute_section
&& sec
!= NULL
)
9365 as_bad_where (fragp
->fr_file
, fragp
->fr_line
, "unsupported relocation");
9367 if ((val
& ((1 << op
->shift
) - 1)) != 0
9368 || val
< (mintiny
<< op
->shift
)
9369 || val
> (maxtiny
<< op
->shift
))
9375 /* Estimate the size of a frag before relaxing. Unless this is the
9376 mips16, we are not really relaxing here, and the final size is
9377 encoded in the subtype information. For the mips16, we have to
9378 decide whether we are using an extended opcode or not. */
9382 md_estimate_size_before_relax (fragp
, segtype
)
9388 if (RELAX_MIPS16_P (fragp
->fr_subtype
))
9390 if (mips16_extended_frag (fragp
, segtype
, 0))
9392 fragp
->fr_subtype
= RELAX_MIPS16_MARK_EXTENDED (fragp
->fr_subtype
);
9397 fragp
->fr_subtype
= RELAX_MIPS16_CLEAR_EXTENDED (fragp
->fr_subtype
);
9402 if (mips_pic
== NO_PIC
)
9404 change
= nopic_need_relax (fragp
->fr_symbol
);
9406 else if (mips_pic
== SVR4_PIC
)
9408 asection
*symsec
= fragp
->fr_symbol
->bsym
->section
;
9410 /* This must duplicate the test in adjust_reloc_syms. */
9411 change
= (symsec
!= &bfd_und_section
9412 && symsec
!= &bfd_abs_section
9413 && ! bfd_is_com_section (symsec
));
9420 /* Record the offset to the first reloc in the fr_opcode field.
9421 This lets md_convert_frag and tc_gen_reloc know that the code
9422 must be expanded. */
9423 fragp
->fr_opcode
= (fragp
->fr_literal
9425 - RELAX_OLD (fragp
->fr_subtype
)
9426 + RELAX_RELOC1 (fragp
->fr_subtype
));
9427 /* FIXME: This really needs as_warn_where. */
9428 if (RELAX_WARN (fragp
->fr_subtype
))
9429 as_warn ("AT used after \".set noat\" or macro used after \".set nomacro\"");
9435 return RELAX_NEW (fragp
->fr_subtype
) - RELAX_OLD (fragp
->fr_subtype
);
9438 /* Translate internal representation of relocation info to BFD target
9442 tc_gen_reloc (section
, fixp
)
9446 static arelent
*retval
[4];
9448 bfd_reloc_code_real_type code
;
9450 reloc
= retval
[0] = (arelent
*) xmalloc (sizeof (arelent
));
9453 reloc
->sym_ptr_ptr
= &fixp
->fx_addsy
->bsym
;
9454 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
9456 if (mips_pic
== EMBEDDED_PIC
9457 && SWITCH_TABLE (fixp
))
9459 /* For a switch table entry we use a special reloc. The addend
9460 is actually the difference between the reloc address and the
9462 reloc
->addend
= reloc
->address
- S_GET_VALUE (fixp
->fx_subsy
);
9463 if (OUTPUT_FLAVOR
!= bfd_target_ecoff_flavour
)
9464 as_fatal ("Double check fx_r_type in tc-mips.c:tc_gen_reloc");
9465 fixp
->fx_r_type
= BFD_RELOC_GPREL32
;
9467 else if (fixp
->fx_r_type
== BFD_RELOC_PCREL_LO16
)
9469 /* We use a special addend for an internal RELLO reloc. */
9470 if (fixp
->fx_addsy
->bsym
->flags
& BSF_SECTION_SYM
)
9471 reloc
->addend
= reloc
->address
- S_GET_VALUE (fixp
->fx_subsy
);
9473 reloc
->addend
= fixp
->fx_addnumber
+ reloc
->address
;
9475 else if (fixp
->fx_r_type
== BFD_RELOC_PCREL_HI16_S
)
9477 assert (fixp
->fx_next
!= NULL
9478 && fixp
->fx_next
->fx_r_type
== BFD_RELOC_PCREL_LO16
);
9479 /* We use a special addend for an internal RELHI reloc. The
9480 reloc is relative to the RELLO; adjust the addend
9482 if (fixp
->fx_addsy
->bsym
->flags
& BSF_SECTION_SYM
)
9483 reloc
->addend
= (fixp
->fx_next
->fx_frag
->fr_address
9484 + fixp
->fx_next
->fx_where
9485 - S_GET_VALUE (fixp
->fx_subsy
));
9487 reloc
->addend
= (fixp
->fx_addnumber
9488 + fixp
->fx_next
->fx_frag
->fr_address
9489 + fixp
->fx_next
->fx_where
);
9491 else if (fixp
->fx_pcrel
== 0)
9492 reloc
->addend
= fixp
->fx_addnumber
;
9495 if (OUTPUT_FLAVOR
!= bfd_target_aout_flavour
)
9496 /* A gruesome hack which is a result of the gruesome gas reloc
9498 reloc
->addend
= reloc
->address
;
9500 reloc
->addend
= -reloc
->address
;
9503 /* If this is a variant frag, we may need to adjust the existing
9504 reloc and generate a new one. */
9505 if (fixp
->fx_frag
->fr_opcode
!= NULL
9506 && (fixp
->fx_r_type
== BFD_RELOC_MIPS_GPREL
9507 || fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT16
9508 || fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL16
9509 || fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT_HI16
9510 || fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT_LO16
9511 || fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL_HI16
9512 || fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL_LO16
))
9516 assert (! RELAX_MIPS16_P (fixp
->fx_frag
->fr_subtype
));
9518 /* If this is not the last reloc in this frag, then we have two
9519 GPREL relocs, or a GOT_HI16/GOT_LO16 pair, or a
9520 CALL_HI16/CALL_LO16, both of which are being replaced. Let
9521 the second one handle all of them. */
9522 if (fixp
->fx_next
!= NULL
9523 && fixp
->fx_frag
== fixp
->fx_next
->fx_frag
)
9525 assert ((fixp
->fx_r_type
== BFD_RELOC_MIPS_GPREL
9526 && fixp
->fx_next
->fx_r_type
== BFD_RELOC_MIPS_GPREL
)
9527 || (fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT_HI16
9528 && (fixp
->fx_next
->fx_r_type
9529 == BFD_RELOC_MIPS_GOT_LO16
))
9530 || (fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL_HI16
9531 && (fixp
->fx_next
->fx_r_type
9532 == BFD_RELOC_MIPS_CALL_LO16
)));
9537 fixp
->fx_where
= fixp
->fx_frag
->fr_opcode
- fixp
->fx_frag
->fr_literal
;
9538 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
9539 reloc2
= retval
[1] = (arelent
*) xmalloc (sizeof (arelent
));
9541 reloc2
->sym_ptr_ptr
= &fixp
->fx_addsy
->bsym
;
9542 reloc2
->address
= (reloc
->address
9543 + (RELAX_RELOC2 (fixp
->fx_frag
->fr_subtype
)
9544 - RELAX_RELOC1 (fixp
->fx_frag
->fr_subtype
)));
9545 reloc2
->addend
= fixp
->fx_addnumber
;
9546 reloc2
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_LO16
);
9547 assert (reloc2
->howto
!= NULL
);
9549 if (RELAX_RELOC3 (fixp
->fx_frag
->fr_subtype
))
9553 reloc3
= retval
[2] = (arelent
*) xmalloc (sizeof (arelent
));
9556 reloc3
->address
+= 4;
9559 if (mips_pic
== NO_PIC
)
9561 assert (fixp
->fx_r_type
== BFD_RELOC_MIPS_GPREL
);
9562 fixp
->fx_r_type
= BFD_RELOC_HI16_S
;
9564 else if (mips_pic
== SVR4_PIC
)
9566 switch (fixp
->fx_r_type
)
9570 case BFD_RELOC_MIPS_GOT16
:
9572 case BFD_RELOC_MIPS_CALL16
:
9573 case BFD_RELOC_MIPS_GOT_LO16
:
9574 case BFD_RELOC_MIPS_CALL_LO16
:
9575 fixp
->fx_r_type
= BFD_RELOC_MIPS_GOT16
;
9583 /* Since DIFF_EXPR_OK is defined in tc-mips.h, it is possible that
9584 fixup_segment converted a non-PC relative reloc into a PC
9585 relative reloc. In such a case, we need to convert the reloc
9587 code
= fixp
->fx_r_type
;
9593 code
= BFD_RELOC_8_PCREL
;
9596 code
= BFD_RELOC_16_PCREL
;
9599 code
= BFD_RELOC_32_PCREL
;
9602 code
= BFD_RELOC_64_PCREL
;
9604 case BFD_RELOC_8_PCREL
:
9605 case BFD_RELOC_16_PCREL
:
9606 case BFD_RELOC_32_PCREL
:
9607 case BFD_RELOC_64_PCREL
:
9608 case BFD_RELOC_16_PCREL_S2
:
9609 case BFD_RELOC_PCREL_HI16_S
:
9610 case BFD_RELOC_PCREL_LO16
:
9613 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
9614 "Cannot make %s relocation PC relative",
9615 bfd_get_reloc_code_name (code
));
9619 /* To support a PC relative reloc when generating embedded PIC code
9620 for ECOFF, we use a Cygnus extension. We check for that here to
9621 make sure that we don't let such a reloc escape normally. */
9622 if (OUTPUT_FLAVOR
== bfd_target_ecoff_flavour
9623 && code
== BFD_RELOC_16_PCREL_S2
9624 && mips_pic
!= EMBEDDED_PIC
)
9625 reloc
->howto
= NULL
;
9627 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
9629 if (reloc
->howto
== NULL
)
9631 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
9632 "Can not represent %s relocation in this object file format",
9633 bfd_get_reloc_code_name (code
));
9640 /* Relax a machine dependent frag. This returns the amount by which
9641 the current size of the frag should change. */
9644 mips_relax_frag (fragp
, stretch
)
9648 if (! RELAX_MIPS16_P (fragp
->fr_subtype
))
9651 if (mips16_extended_frag (fragp
, (asection
*) NULL
, stretch
))
9653 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
9655 fragp
->fr_subtype
= RELAX_MIPS16_MARK_EXTENDED (fragp
->fr_subtype
);
9660 if (! RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
9662 fragp
->fr_subtype
= RELAX_MIPS16_CLEAR_EXTENDED (fragp
->fr_subtype
);
9669 /* Convert a machine dependent frag. */
9672 md_convert_frag (abfd
, asec
, fragp
)
9680 if (RELAX_MIPS16_P (fragp
->fr_subtype
))
9683 register const struct mips16_immed_operand
*op
;
9689 unsigned short extend
;
9691 type
= RELAX_MIPS16_TYPE (fragp
->fr_subtype
);
9692 op
= mips16_immed_operands
;
9693 while (op
->type
!= type
)
9696 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
9707 resolve_symbol_value (fragp
->fr_symbol
);
9708 val
= S_GET_VALUE (fragp
->fr_symbol
);
9713 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
9715 /* The rules for the base address of a PC relative reloc are
9716 complicated; see mips16_extended_frag. */
9717 if (type
== 'p' || type
== 'q')
9720 /* Ignore the low bit in the target, since it will be
9721 set for a text label. */
9725 else if (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
))
9727 else if (RELAX_MIPS16_DSLOT (fragp
->fr_subtype
))
9732 addr
&= ~ (addressT
) ((1 << op
->shift
) - 1);
9735 /* Make sure the section winds up with the alignment we have
9738 record_alignment (asec
, op
->shift
);
9741 buf
= (bfd_byte
*) (fragp
->fr_literal
+ fragp
->fr_fix
);
9743 if (target_big_endian
)
9744 insn
= bfd_getb16 (buf
);
9746 insn
= bfd_getl16 (buf
);
9748 mips16_immed (fragp
->fr_file
, fragp
->fr_line
, type
, val
, false, small
,
9749 ext
, &insn
, &use_extend
, &extend
);
9753 md_number_to_chars (buf
, 0xf000 | extend
, 2);
9758 md_number_to_chars (buf
, insn
, 2);
9764 if (fragp
->fr_opcode
== NULL
)
9767 old
= RELAX_OLD (fragp
->fr_subtype
);
9768 new = RELAX_NEW (fragp
->fr_subtype
);
9769 fixptr
= fragp
->fr_literal
+ fragp
->fr_fix
;
9772 memcpy (fixptr
- old
, fixptr
, new);
9774 fragp
->fr_fix
+= new - old
;
9780 /* This function is called after the relocs have been generated.
9781 We've been storing mips16 text labels as odd. Here we convert them
9782 back to even for the convenience of the debugger. */
9785 mips_frob_file_after_relocs ()
9788 unsigned int count
, i
;
9790 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
9793 syms
= bfd_get_outsymbols (stdoutput
);
9794 count
= bfd_get_symcount (stdoutput
);
9795 for (i
= 0; i
< count
; i
++, syms
++)
9797 if (elf_symbol (*syms
)->internal_elf_sym
.st_other
== STO_MIPS16
9798 && ((*syms
)->value
& 1) != 0)
9800 (*syms
)->value
&= ~1;
9801 /* If the symbol has an odd size, it was probably computed
9802 incorrectly, so adjust that as well. */
9803 if ((elf_symbol (*syms
)->internal_elf_sym
.st_size
& 1) != 0)
9804 ++elf_symbol (*syms
)->internal_elf_sym
.st_size
;
9811 /* This function is called whenever a label is defined. It is used
9812 when handling branch delays; if a branch has a label, we assume we
9816 mips_define_label (sym
)
9819 struct insn_label_list
*l
;
9821 if (free_insn_labels
== NULL
)
9822 l
= (struct insn_label_list
*) xmalloc (sizeof *l
);
9825 l
= free_insn_labels
;
9826 free_insn_labels
= l
->next
;
9830 l
->next
= insn_labels
;
9834 /* Decide whether a label is local. This is called by LOCAL_LABEL.
9835 In order to work with gcc when using mips-tfile, we must keep all
9836 local labels. However, in other cases, we want to discard them,
9837 since they are useless. */
9840 mips_local_label (name
)
9843 #ifndef NO_ECOFF_DEBUGGING
9846 && ! ecoff_debugging_seen
)
9848 /* We were called with -g, but we didn't see any debugging
9849 information. That may mean that gcc is smuggling debugging
9850 information through to mips-tfile, in which case we must
9851 generate all local labels. */
9856 /* Here it's OK to discard local labels. */
9858 return name
[0] == '$';
9861 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9863 /* Some special processing for a MIPS ELF file. */
9866 mips_elf_final_processing ()
9868 /* Write out the register information. */
9873 s
.ri_gprmask
= mips_gprmask
;
9874 s
.ri_cprmask
[0] = mips_cprmask
[0];
9875 s
.ri_cprmask
[1] = mips_cprmask
[1];
9876 s
.ri_cprmask
[2] = mips_cprmask
[2];
9877 s
.ri_cprmask
[3] = mips_cprmask
[3];
9878 /* The gp_value field is set by the MIPS ELF backend. */
9880 bfd_mips_elf32_swap_reginfo_out (stdoutput
, &s
,
9881 ((Elf32_External_RegInfo
*)
9882 mips_regmask_frag
));
9886 Elf64_Internal_RegInfo s
;
9888 s
.ri_gprmask
= mips_gprmask
;
9890 s
.ri_cprmask
[0] = mips_cprmask
[0];
9891 s
.ri_cprmask
[1] = mips_cprmask
[1];
9892 s
.ri_cprmask
[2] = mips_cprmask
[2];
9893 s
.ri_cprmask
[3] = mips_cprmask
[3];
9894 /* The gp_value field is set by the MIPS ELF backend. */
9896 bfd_mips_elf64_swap_reginfo_out (stdoutput
, &s
,
9897 ((Elf64_External_RegInfo
*)
9898 mips_regmask_frag
));
9901 /* Set the MIPS ELF flag bits. FIXME: There should probably be some
9902 sort of BFD interface for this. */
9903 if (mips_any_noreorder
)
9904 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_NOREORDER
;
9905 if (mips_pic
!= NO_PIC
)
9906 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_PIC
;
9909 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */
9911 /* These functions should really be defined by the object file format,
9912 since they are related to debugging information. However, this
9913 code has to work for the a.out format, which does not define them,
9914 so we provide simple versions here. These don't actually generate
9915 any debugging information, but they do simple checking and someday
9916 somebody may make them useful. */
9920 struct loc
*loc_next
;
9921 unsigned long loc_fileno
;
9922 unsigned long loc_lineno
;
9923 unsigned long loc_offset
;
9924 unsigned short loc_delta
;
9925 unsigned short loc_count
;
9934 struct proc
*proc_next
;
9935 struct symbol
*proc_isym
;
9936 struct symbol
*proc_end
;
9937 unsigned long proc_reg_mask
;
9938 unsigned long proc_reg_offset
;
9939 unsigned long proc_fpreg_mask
;
9940 unsigned long proc_fpreg_offset
;
9941 unsigned long proc_frameoffset
;
9942 unsigned long proc_framereg
;
9943 unsigned long proc_pcreg
;
9945 struct file
*proc_file
;
9952 struct file
*file_next
;
9953 unsigned long file_fileno
;
9954 struct symbol
*file_symbol
;
9955 struct symbol
*file_end
;
9956 struct proc
*file_proc
;
9961 static struct obstack proc_frags
;
9962 static procS
*proc_lastP
;
9963 static procS
*proc_rootP
;
9964 static int numprocs
;
9969 obstack_begin (&proc_frags
, 0x2000);
9975 /* check for premature end, nesting errors, etc */
9976 if (proc_lastP
&& proc_lastP
->proc_end
== NULL
)
9977 as_warn ("missing `.end' at end of assembly");
9986 if (*input_line_pointer
== '-')
9988 ++input_line_pointer
;
9991 if (!isdigit (*input_line_pointer
))
9992 as_bad ("Expected simple number.");
9993 if (input_line_pointer
[0] == '0')
9995 if (input_line_pointer
[1] == 'x')
9997 input_line_pointer
+= 2;
9998 while (isxdigit (*input_line_pointer
))
10001 val
|= hex_value (*input_line_pointer
++);
10003 return negative
? -val
: val
;
10007 ++input_line_pointer
;
10008 while (isdigit (*input_line_pointer
))
10011 val
|= *input_line_pointer
++ - '0';
10013 return negative
? -val
: val
;
10016 if (!isdigit (*input_line_pointer
))
10018 printf (" *input_line_pointer == '%c' 0x%02x\n",
10019 *input_line_pointer
, *input_line_pointer
);
10020 as_warn ("Invalid number");
10023 while (isdigit (*input_line_pointer
))
10026 val
+= *input_line_pointer
++ - '0';
10028 return negative
? -val
: val
;
10031 /* The .file directive; just like the usual .file directive, but there
10032 is an initial number which is the ECOFF file index. */
10040 line
= get_number ();
10045 /* The .end directive. */
10053 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
10056 demand_empty_rest_of_line ();
10060 if (now_seg
!= text_section
)
10061 as_warn (".end not in text section");
10064 as_warn (".end and no .ent seen yet.");
10070 assert (S_GET_NAME (p
));
10071 if (strcmp (S_GET_NAME (p
), S_GET_NAME (proc_lastP
->proc_isym
)))
10072 as_warn (".end symbol does not match .ent symbol.");
10075 proc_lastP
->proc_end
= (symbolS
*) 1;
10078 /* The .aent and .ent directives. */
10088 symbolP
= get_symbol ();
10089 if (*input_line_pointer
== ',')
10090 input_line_pointer
++;
10091 SKIP_WHITESPACE ();
10092 if (isdigit (*input_line_pointer
) || *input_line_pointer
== '-')
10093 number
= get_number ();
10094 if (now_seg
!= text_section
)
10095 as_warn (".ent or .aent not in text section.");
10097 if (!aent
&& proc_lastP
&& proc_lastP
->proc_end
== NULL
)
10098 as_warn ("missing `.end'");
10102 procP
= (procS
*) obstack_alloc (&proc_frags
, sizeof (*procP
));
10103 procP
->proc_isym
= symbolP
;
10104 procP
->proc_reg_mask
= 0;
10105 procP
->proc_reg_offset
= 0;
10106 procP
->proc_fpreg_mask
= 0;
10107 procP
->proc_fpreg_offset
= 0;
10108 procP
->proc_frameoffset
= 0;
10109 procP
->proc_framereg
= 0;
10110 procP
->proc_pcreg
= 0;
10111 procP
->proc_end
= NULL
;
10112 procP
->proc_next
= NULL
;
10114 proc_lastP
->proc_next
= procP
;
10116 proc_rootP
= procP
;
10117 proc_lastP
= procP
;
10120 demand_empty_rest_of_line ();
10123 /* The .frame directive. */
10136 frame_reg
= tc_get_register (1);
10137 if (*input_line_pointer
== ',')
10138 input_line_pointer
++;
10139 frame_off
= get_absolute_expression ();
10140 if (*input_line_pointer
== ',')
10141 input_line_pointer
++;
10142 pcreg
= tc_get_register (0);
10144 /* bob third eye */
10145 assert (proc_rootP
);
10146 proc_rootP
->proc_framereg
= frame_reg
;
10147 proc_rootP
->proc_frameoffset
= frame_off
;
10148 proc_rootP
->proc_pcreg
= pcreg
;
10149 /* bob macho .frame */
10151 /* We don't have to write out a frame stab for unoptimized code. */
10152 if (!(frame_reg
== FP
&& frame_off
== 0))
10155 as_warn ("No .ent for .frame to use.");
10156 (void) sprintf (str
, "R%d;%d", frame_reg
, frame_off
);
10157 symP
= symbol_new (str
, N_VFP
, 0, frag_now
);
10158 S_SET_TYPE (symP
, N_RMASK
);
10159 S_SET_OTHER (symP
, 0);
10160 S_SET_DESC (symP
, 0);
10161 symP
->sy_forward
= proc_lastP
->proc_isym
;
10162 /* bob perhaps I should have used pseudo set */
10164 demand_empty_rest_of_line ();
10168 /* The .fmask and .mask directives. */
10175 char str
[100], *strP
;
10181 mask
= get_number ();
10182 if (*input_line_pointer
== ',')
10183 input_line_pointer
++;
10184 off
= get_absolute_expression ();
10186 /* bob only for coff */
10187 assert (proc_rootP
);
10188 if (reg_type
== 'F')
10190 proc_rootP
->proc_fpreg_mask
= mask
;
10191 proc_rootP
->proc_fpreg_offset
= off
;
10195 proc_rootP
->proc_reg_mask
= mask
;
10196 proc_rootP
->proc_reg_offset
= off
;
10199 /* bob macho .mask + .fmask */
10201 /* We don't have to write out a mask stab if no saved regs. */
10205 as_warn ("No .ent for .mask to use.");
10207 for (i
= 0; i
< 32; i
++)
10211 sprintf (strP
, "%c%d,", reg_type
, i
);
10212 strP
+= strlen (strP
);
10216 sprintf (strP
, ";%d,", off
);
10217 symP
= symbol_new (str
, N_RMASK
, 0, frag_now
);
10218 S_SET_TYPE (symP
, N_RMASK
);
10219 S_SET_OTHER (symP
, 0);
10220 S_SET_DESC (symP
, 0);
10221 symP
->sy_forward
= proc_lastP
->proc_isym
;
10222 /* bob perhaps I should have used pseudo set */
10227 /* The .loc directive. */
10238 assert (now_seg
== text_section
);
10240 lineno
= get_number ();
10241 addroff
= frag_now_fix ();
10243 symbolP
= symbol_new ("", N_SLINE
, addroff
, frag_now
);
10244 S_SET_TYPE (symbolP
, N_SLINE
);
10245 S_SET_OTHER (symbolP
, 0);
10246 S_SET_DESC (symbolP
, lineno
);
10247 symbolP
->sy_segment
= now_seg
;