1 /* tc-mips.c -- assemble code for a MIPS chip.
2 Copyright (C) 1993, 1995 Free Software Foundation, Inc.
3 Contributed by the OSF and Ralph Campbell.
4 Written by Keith Knowles and Ralph Campbell, working independently.
5 Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus
8 This file is part of GAS.
10 GAS is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 2, or (at your option)
15 GAS is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with GAS; see the file COPYING. If not, write to
22 the Free Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
27 #include "libiberty.h"
38 #include "opcode/mips.h"
41 /* Clean up namespace so we can include obj-elf.h too. */
42 static int mips_output_flavor () { return OUTPUT_FLAVOR
; }
43 #undef OBJ_PROCESS_STAB
49 #undef TARGET_SYMBOL_FIELDS
51 #undef obj_frob_symbol
53 #undef obj_sec_sym_ok_for_reloc
56 /* Fix any of them that we actually care about. */
58 #define OUTPUT_FLAVOR mips_output_flavor()
65 #ifndef ECOFF_DEBUGGING
66 #define NO_ECOFF_DEBUGGING
67 #define ECOFF_DEBUGGING 0
72 static char *mips_regmask_frag
;
75 #define PIC_CALL_REG 25
83 extern int target_big_endian
;
85 /* The default target format to use. */
89 switch (OUTPUT_FLAVOR
)
91 case bfd_target_aout_flavour
:
92 return target_big_endian
? "a.out-mips-big" : "a.out-mips-little";
93 case bfd_target_ecoff_flavour
:
94 return target_big_endian
? "ecoff-bigmips" : "ecoff-littlemips";
95 case bfd_target_elf_flavour
:
96 return target_big_endian
? "elf32-bigmips" : "elf32-littlemips";
102 /* The name of the readonly data section. */
103 #define RDATA_SECTION_NAME (OUTPUT_FLAVOR == bfd_target_aout_flavour \
105 : OUTPUT_FLAVOR == bfd_target_ecoff_flavour \
107 : OUTPUT_FLAVOR == bfd_target_elf_flavour \
111 /* These variables are filled in with the masks of registers used.
112 The object format code reads them and puts them in the appropriate
114 unsigned long mips_gprmask
;
115 unsigned long mips_cprmask
[4];
117 /* MIPS ISA (Instruction Set Architecture) level (may be changed
118 temporarily using .set mipsN). */
119 static int mips_isa
= -1;
121 /* MIPS ISA we are using for this output file. */
122 static int file_mips_isa
;
124 /* The CPU type as a number: 2000, 3000, 4000, 4400, etc. */
125 static int mips_cpu
= -1;
127 /* Whether the 4650 instructions (mad/madu) are permitted. */
128 static int mips_4650
= -1;
130 /* Whether the 4010 instructions are permitted. */
131 static int mips_4010
= -1;
133 /* Whether the 4100 MADD16 and DMADD16 are permitted. */
134 static int mips_4100
= -1;
136 /* Whether the processor uses hardware interlocks, and thus does not
137 require nops to be inserted. */
138 static int interlocks
= -1;
140 /* MIPS PIC level. */
144 /* Do not generate PIC code. */
147 /* Generate PIC code as in Irix 4. This is not implemented, and I'm
148 not sure what it is supposed to do. */
151 /* Generate PIC code as in the SVR4 MIPS ABI. */
154 /* Generate PIC code without using a global offset table: the data
155 segment has a maximum size of 64K, all data references are off
156 the $gp register, and all text references are PC relative. This
157 is used on some embedded systems. */
161 static enum mips_pic_level mips_pic
;
163 /* 1 if trap instructions should used for overflow rather than break
165 static int mips_trap
;
167 static int mips_warn_about_macros
;
168 static int mips_noreorder
;
169 static int mips_any_noreorder
;
170 static int mips_nomove
;
171 static int mips_noat
;
172 static int mips_nobopt
;
174 /* The size of the small data section. */
175 static int g_switch_value
= 8;
176 /* Whether the -G option was used. */
177 static int g_switch_seen
= 0;
182 /* If we can determine in advance that GP optimization won't be
183 possible, we can skip the relaxation stuff that tries to produce
184 GP-relative references. This makes delay slot optimization work
187 This function can only provide a guess, but it seems to work for
188 gcc output. If it guesses wrong, the only loss should be in
189 efficiency; it shouldn't introduce any bugs.
191 I don't know if a fix is needed for the SVR4_PIC mode. I've only
192 fixed it for the non-PIC mode. KR 95/04/07 */
193 static int nopic_need_relax
PARAMS ((symbolS
*));
195 /* handle of the OPCODE hash table */
196 static struct hash_control
*op_hash
= NULL
;
198 /* This array holds the chars that always start a comment. If the
199 pre-processor is disabled, these aren't very useful */
200 const char comment_chars
[] = "#";
202 /* This array holds the chars that only start a comment at the beginning of
203 a line. If the line seems to have the form '# 123 filename'
204 .line and .file directives will appear in the pre-processed output */
205 /* Note that input_file.c hand checks for '#' at the beginning of the
206 first line of the input file. This is because the compiler outputs
207 #NO_APP at the beginning of its output. */
208 /* Also note that C style comments are always supported. */
209 const char line_comment_chars
[] = "#";
211 /* This array holds machine specific line separator characters. */
212 const char line_separator_chars
[] = "";
214 /* Chars that can be used to separate mant from exp in floating point nums */
215 const char EXP_CHARS
[] = "eE";
217 /* Chars that mean this number is a floating point constant */
220 const char FLT_CHARS
[] = "rRsSfFdDxXpP";
222 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
223 changed in read.c . Ideally it shouldn't have to know about it at all,
224 but nothing is ideal around here.
227 static char *insn_error
;
229 static int byte_order
;
231 static int auto_align
= 1;
233 /* Symbol labelling the current insn. */
234 static symbolS
*insn_label
;
236 /* When outputting SVR4 PIC code, the assembler needs to know the
237 offset in the stack frame from which to restore the $gp register.
238 This is set by the .cprestore pseudo-op, and saved in this
240 static offsetT mips_cprestore_offset
= -1;
242 /* This is the register which holds the stack frame, as set by the
243 .frame pseudo-op. This is needed to implement .cprestore. */
244 static int mips_frame_reg
= SP
;
246 /* To output NOP instructions correctly, we need to keep information
247 about the previous two instructions. */
249 /* Whether we are optimizing. The default value of 2 means to remove
250 unneeded NOPs and swap branch instructions when possible. A value
251 of 1 means to not swap branches. A value of 0 means to always
253 static int mips_optimize
= 2;
255 /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is
256 equivalent to seeing no -g option at all. */
257 static int mips_debug
= 0;
259 /* The previous instruction. */
260 static struct mips_cl_insn prev_insn
;
262 /* The instruction before prev_insn. */
263 static struct mips_cl_insn prev_prev_insn
;
265 /* If we don't want information for prev_insn or prev_prev_insn, we
266 point the insn_mo field at this dummy integer. */
267 static const struct mips_opcode dummy_opcode
= { 0 };
269 /* Non-zero if prev_insn is valid. */
270 static int prev_insn_valid
;
272 /* The frag for the previous instruction. */
273 static struct frag
*prev_insn_frag
;
275 /* The offset into prev_insn_frag for the previous instruction. */
276 static long prev_insn_where
;
278 /* The reloc for the previous instruction, if any. */
279 static fixS
*prev_insn_fixp
;
281 /* Non-zero if the previous instruction was in a delay slot. */
282 static int prev_insn_is_delay_slot
;
284 /* Non-zero if the previous instruction was in a .set noreorder. */
285 static int prev_insn_unreordered
;
287 /* Non-zero if the previous previous instruction was in a .set
289 static int prev_prev_insn_unreordered
;
291 /* Since the MIPS does not have multiple forms of PC relative
292 instructions, we do not have to do relaxing as is done on other
293 platforms. However, we do have to handle GP relative addressing
294 correctly, which turns out to be a similar problem.
296 Every macro that refers to a symbol can occur in (at least) two
297 forms, one with GP relative addressing and one without. For
298 example, loading a global variable into a register generally uses
299 a macro instruction like this:
301 If i can be addressed off the GP register (this is true if it is in
302 the .sbss or .sdata section, or if it is known to be smaller than
303 the -G argument) this will generate the following instruction:
305 This instruction will use a GPREL reloc. If i can not be addressed
306 off the GP register, the following instruction sequence will be used:
309 In this case the first instruction will have a HI16 reloc, and the
310 second reloc will have a LO16 reloc. Both relocs will be against
313 The issue here is that we may not know whether i is GP addressable
314 until after we see the instruction that uses it. Therefore, we
315 want to be able to choose the final instruction sequence only at
316 the end of the assembly. This is similar to the way other
317 platforms choose the size of a PC relative instruction only at the
320 When generating position independent code we do not use GP
321 addressing in quite the same way, but the issue still arises as
322 external symbols and local symbols must be handled differently.
324 We handle these issues by actually generating both possible
325 instruction sequences. The longer one is put in a frag_var with
326 type rs_machine_dependent. We encode what to do with the frag in
327 the subtype field. We encode (1) the number of existing bytes to
328 replace, (2) the number of new bytes to use, (3) the offset from
329 the start of the existing bytes to the first reloc we must generate
330 (that is, the offset is applied from the start of the existing
331 bytes after they are replaced by the new bytes, if any), (4) the
332 offset from the start of the existing bytes to the second reloc,
333 (5) whether a third reloc is needed (the third reloc is always four
334 bytes after the second reloc), and (6) whether to warn if this
335 variant is used (this is sometimes needed if .set nomacro or .set
336 noat is in effect). All these numbers are reasonably small.
338 Generating two instruction sequences must be handled carefully to
339 ensure that delay slots are handled correctly. Fortunately, there
340 are a limited number of cases. When the second instruction
341 sequence is generated, append_insn is directed to maintain the
342 existing delay slot information, so it continues to apply to any
343 code after the second instruction sequence. This means that the
344 second instruction sequence must not impose any requirements not
345 required by the first instruction sequence.
347 These variant frags are then handled in functions called by the
348 machine independent code. md_estimate_size_before_relax returns
349 the final size of the frag. md_convert_frag sets up the final form
350 of the frag. tc_gen_reloc adjust the first reloc and adds a second
352 #define RELAX_ENCODE(old, new, reloc1, reloc2, reloc3, warn) \
356 | (((reloc1) + 64) << 9) \
357 | (((reloc2) + 64) << 2) \
358 | ((reloc3) ? (1 << 1) : 0) \
360 #define RELAX_OLD(i) (((i) >> 24) & 0xff)
361 #define RELAX_NEW(i) (((i) >> 16) & 0xff)
362 #define RELAX_RELOC1(i) ((bfd_vma)(((i) >> 9) & 0x7f) - 64)
363 #define RELAX_RELOC2(i) ((bfd_vma)(((i) >> 2) & 0x7f) - 64)
364 #define RELAX_RELOC3(i) (((i) >> 1) & 1)
365 #define RELAX_WARN(i) ((i) & 1)
367 /* Prototypes for static functions. */
370 #define internalError() \
371 as_fatal ("internal Error, line %d, %s", __LINE__, __FILE__)
373 #define internalError() as_fatal ("MIPS internal Error");
376 static int insn_uses_reg
PARAMS ((struct mips_cl_insn
*ip
,
377 unsigned int reg
, int fpr
));
378 static void append_insn
PARAMS ((char *place
,
379 struct mips_cl_insn
* ip
,
381 bfd_reloc_code_real_type r
));
382 static void mips_no_prev_insn
PARAMS ((void));
383 static void mips_emit_delays
PARAMS ((void));
385 static void macro_build
PARAMS ((char *place
, int *counter
, expressionS
* ep
,
386 const char *name
, const char *fmt
,
389 static void macro_build ();
391 static void macro_build_lui
PARAMS ((char *place
, int *counter
,
392 expressionS
* ep
, int regnum
));
393 static void set_at
PARAMS ((int *counter
, int reg
, int unsignedp
));
394 static void check_absolute_expr
PARAMS ((struct mips_cl_insn
* ip
,
396 static void load_register
PARAMS ((int *, int, expressionS
*, int));
397 static void load_address
PARAMS ((int *counter
, int reg
, expressionS
*ep
));
398 static void macro
PARAMS ((struct mips_cl_insn
* ip
));
399 #ifdef LOSING_COMPILER
400 static void macro2
PARAMS ((struct mips_cl_insn
* ip
));
402 static void mips_ip
PARAMS ((char *str
, struct mips_cl_insn
* ip
));
403 static int my_getSmallExpression
PARAMS ((expressionS
* ep
, char *str
));
404 static void my_getExpression
PARAMS ((expressionS
* ep
, char *str
));
405 static symbolS
*get_symbol
PARAMS ((void));
406 static void mips_align
PARAMS ((int to
, int fill
, symbolS
*label
));
407 static void s_align
PARAMS ((int));
408 static void s_change_sec
PARAMS ((int));
409 static void s_cons
PARAMS ((int));
410 static void s_err
PARAMS ((int));
411 static void s_extern
PARAMS ((int));
412 static void s_float_cons
PARAMS ((int));
413 static void s_mips_globl
PARAMS ((int));
414 static void s_option
PARAMS ((int));
415 static void s_mipsset
PARAMS ((int));
416 static void s_abicalls
PARAMS ((int));
417 static void s_cpload
PARAMS ((int));
418 static void s_cprestore
PARAMS ((int));
419 static void s_gpword
PARAMS ((int));
420 static void s_cpadd
PARAMS ((int));
421 static void md_obj_begin
PARAMS ((void));
422 static void md_obj_end
PARAMS ((void));
423 static long get_number
PARAMS ((void));
424 static void s_ent
PARAMS ((int));
425 static void s_mipsend
PARAMS ((int));
426 static void s_file
PARAMS ((int));
430 The following pseudo-ops from the Kane and Heinrich MIPS book
431 should be defined here, but are currently unsupported: .alias,
432 .galive, .gjaldef, .gjrlive, .livereg, .noalias.
434 The following pseudo-ops from the Kane and Heinrich MIPS book are
435 specific to the type of debugging information being generated, and
436 should be defined by the object format: .aent, .begin, .bend,
437 .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp,
440 The following pseudo-ops from the Kane and Heinrich MIPS book are
441 not MIPS CPU specific, but are also not specific to the object file
442 format. This file is probably the best place to define them, but
443 they are not currently supported: .asm0, .endr, .lab, .repeat,
444 .struct, .weakext. */
446 static const pseudo_typeS mips_pseudo_table
[] =
448 /* MIPS specific pseudo-ops. */
449 {"option", s_option
, 0},
450 {"set", s_mipsset
, 0},
451 {"rdata", s_change_sec
, 'r'},
452 {"sdata", s_change_sec
, 's'},
453 {"livereg", s_ignore
, 0},
454 {"abicalls", s_abicalls
, 0},
455 {"cpload", s_cpload
, 0},
456 {"cprestore", s_cprestore
, 0},
457 {"gpword", s_gpword
, 0},
458 {"cpadd", s_cpadd
, 0},
460 /* Relatively generic pseudo-ops that happen to be used on MIPS
462 {"asciiz", stringer
, 1},
463 {"bss", s_change_sec
, 'b'},
466 {"dword", s_cons
, 3},
468 /* These pseudo-ops are defined in read.c, but must be overridden
469 here for one reason or another. */
470 {"align", s_align
, 0},
472 {"data", s_change_sec
, 'd'},
473 {"double", s_float_cons
, 'd'},
474 {"extern", s_extern
, 0},
475 {"float", s_float_cons
, 'f'},
476 {"globl", s_mips_globl
, 0},
477 {"global", s_mips_globl
, 0},
478 {"hword", s_cons
, 1},
483 {"short", s_cons
, 1},
484 {"single", s_float_cons
, 'f'},
485 {"text", s_change_sec
, 't'},
490 static const pseudo_typeS mips_nonecoff_pseudo_table
[] = {
491 /* These pseudo-ops should be defined by the object file format.
492 However, a.out doesn't support them, so we have versions here. */
494 {"bgnb", s_ignore
, 0},
495 {"end", s_mipsend
, 0},
496 {"endb", s_ignore
, 0},
499 {"fmask", s_ignore
, 'F'},
500 {"frame", s_ignore
, 0},
501 {"loc", s_ignore
, 0},
502 {"mask", s_ignore
, 'R'},
503 {"verstamp", s_ignore
, 0},
507 extern void pop_insert
PARAMS ((const pseudo_typeS
*));
512 pop_insert (mips_pseudo_table
);
513 if (! ECOFF_DEBUGGING
)
514 pop_insert (mips_nonecoff_pseudo_table
);
517 static char *expr_end
;
519 static expressionS imm_expr
;
520 static expressionS offset_expr
;
521 static bfd_reloc_code_real_type imm_reloc
;
522 static bfd_reloc_code_real_type offset_reloc
;
525 * This function is called once, at assembler startup time. It should
526 * set up all the tables, etc. that the MD part of the assembler will need.
532 register const char *retval
= NULL
;
533 register unsigned int i
= 0;
541 if (strcmp (cpu
+ (sizeof TARGET_CPU
) - 3, "el") == 0)
543 a
= xmalloc (sizeof TARGET_CPU
);
544 strcpy (a
, TARGET_CPU
);
545 a
[(sizeof TARGET_CPU
) - 3] = '\0';
549 if (strcmp (cpu
, "mips") == 0)
555 else if (strcmp (cpu
, "r6000") == 0
556 || strcmp (cpu
, "mips2") == 0)
562 else if (strcmp (cpu
, "mips64") == 0
563 || strcmp (cpu
, "r4000") == 0
564 || strcmp (cpu
, "mips3") == 0)
570 else if (strcmp (cpu
, "r4400") == 0)
576 else if (strcmp (cpu
, "mips64orion") == 0
577 || strcmp (cpu
, "r4600") == 0)
583 else if (strcmp (cpu
, "r4650") == 0)
591 else if (strcmp (cpu
, "mips64vr4300") == 0)
597 else if (strcmp (cpu
, "mips64vr4100") == 0)
605 else if (strcmp (cpu
, "r4010") == 0)
613 else if (strcmp (cpu
, "r8000") == 0
614 || strcmp (cpu
, "mips4") == 0)
620 else if (strcmp (cpu
, "r10000") == 0)
646 if (mips_4650
|| mips_4010
|| mips_4100
)
651 if (mips_isa
< 2 && mips_trap
)
652 as_bad ("trap exception not supported at ISA 1");
657 ok
= bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, 3000);
660 ok
= bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, 6000);
663 ok
= bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, 4000);
666 ok
= bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, 8000);
670 as_warn ("Could not set architecture and machine");
672 file_mips_isa
= mips_isa
;
674 op_hash
= hash_new ();
676 for (i
= 0; i
< NUMOPCODES
;)
678 const char *name
= mips_opcodes
[i
].name
;
680 retval
= hash_insert (op_hash
, name
, (PTR
) &mips_opcodes
[i
]);
683 fprintf (stderr
, "internal error: can't hash `%s': %s\n",
684 mips_opcodes
[i
].name
, retval
);
685 as_fatal ("Broken assembler. No assembly attempted.");
689 if (mips_opcodes
[i
].pinfo
!= INSN_MACRO
690 && ((mips_opcodes
[i
].match
& mips_opcodes
[i
].mask
)
691 != mips_opcodes
[i
].match
))
693 fprintf (stderr
, "internal error: bad opcode: `%s' \"%s\"\n",
694 mips_opcodes
[i
].name
, mips_opcodes
[i
].args
);
695 as_fatal ("Broken assembler. No assembly attempted.");
699 while ((i
< NUMOPCODES
) && !strcmp (mips_opcodes
[i
].name
, name
));
702 mips_no_prev_insn ();
710 /* set the default alignment for the text section (2**2) */
711 record_alignment (text_section
, 2);
713 if (USE_GLOBAL_POINTER_OPT
)
714 bfd_set_gp_size (stdoutput
, g_switch_value
);
716 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
718 /* Sections must be aligned to 16 byte boundaries. */
719 (void) bfd_set_section_alignment (stdoutput
, text_section
, 4);
720 (void) bfd_set_section_alignment (stdoutput
, data_section
, 4);
721 (void) bfd_set_section_alignment (stdoutput
, bss_section
, 4);
723 /* Create a .reginfo section for register masks and a .mdebug
724 section for debugging information. */
732 sec
= subseg_new (".reginfo", (subsegT
) 0);
734 /* The ABI says this section should be loaded so that the
735 running program can access it. */
736 (void) bfd_set_section_flags (stdoutput
, sec
,
737 (SEC_ALLOC
| SEC_LOAD
738 | SEC_READONLY
| SEC_DATA
));
739 (void) bfd_set_section_alignment (stdoutput
, sec
, 2);
742 mips_regmask_frag
= frag_more (sizeof (Elf32_External_RegInfo
));
747 sec
= subseg_new (".mdebug", (subsegT
) 0);
748 (void) bfd_set_section_flags (stdoutput
, sec
,
749 SEC_HAS_CONTENTS
| SEC_READONLY
);
750 (void) bfd_set_section_alignment (stdoutput
, sec
, 2);
753 subseg_set (seg
, subseg
);
757 if (! ECOFF_DEBUGGING
)
764 if (! ECOFF_DEBUGGING
)
772 struct mips_cl_insn insn
;
774 imm_expr
.X_op
= O_absent
;
775 offset_expr
.X_op
= O_absent
;
777 mips_ip (str
, &insn
);
780 as_bad ("%s `%s'", insn_error
, str
);
783 if (insn
.insn_mo
->pinfo
== INSN_MACRO
)
789 if (imm_expr
.X_op
!= O_absent
)
790 append_insn ((char *) NULL
, &insn
, &imm_expr
, imm_reloc
);
791 else if (offset_expr
.X_op
!= O_absent
)
792 append_insn ((char *) NULL
, &insn
, &offset_expr
, offset_reloc
);
794 append_insn ((char *) NULL
, &insn
, NULL
, BFD_RELOC_UNUSED
);
798 /* See whether instruction IP reads register REG. If FPR is non-zero,
799 REG is a floating point register. */
802 insn_uses_reg (ip
, reg
, fpr
)
803 struct mips_cl_insn
*ip
;
807 /* Don't report on general register 0, since it never changes. */
808 if (! fpr
&& reg
== 0)
813 /* If we are called with either $f0 or $f1, we must check $f0.
814 This is not optimal, because it will introduce an unnecessary
815 NOP between "lwc1 $f0" and "swc1 $f1". To fix this we would
816 need to distinguish reading both $f0 and $f1 or just one of
817 them. Note that we don't have to check the other way,
818 because there is no instruction that sets both $f0 and $f1
819 and requires a delay. */
820 if ((ip
->insn_mo
->pinfo
& INSN_READ_FPR_S
)
821 && (((ip
->insn_opcode
>> OP_SH_FS
) & OP_MASK_FS
)
822 == (reg
&~ (unsigned) 1)))
824 if ((ip
->insn_mo
->pinfo
& INSN_READ_FPR_T
)
825 && (((ip
->insn_opcode
>> OP_SH_FT
) & OP_MASK_FT
)
826 == (reg
&~ (unsigned) 1)))
831 if ((ip
->insn_mo
->pinfo
& INSN_READ_GPR_S
)
832 && ((ip
->insn_opcode
>> OP_SH_RS
) & OP_MASK_RS
) == reg
)
834 if ((ip
->insn_mo
->pinfo
& INSN_READ_GPR_T
)
835 && ((ip
->insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
) == reg
)
842 /* Output an instruction. PLACE is where to put the instruction; if
843 it is NULL, this uses frag_more to get room. IP is the instruction
844 information. ADDRESS_EXPR is an operand of the instruction to be
845 used with RELOC_TYPE. */
848 append_insn (place
, ip
, address_expr
, reloc_type
)
850 struct mips_cl_insn
*ip
;
851 expressionS
*address_expr
;
852 bfd_reloc_code_real_type reloc_type
;
854 register unsigned long prev_pinfo
, pinfo
;
859 prev_pinfo
= prev_insn
.insn_mo
->pinfo
;
860 pinfo
= ip
->insn_mo
->pinfo
;
862 if (place
== NULL
&& ! mips_noreorder
)
864 /* If the previous insn required any delay slots, see if we need
865 to insert a NOP or two. There are eight kinds of possible
866 hazards, of which an instruction can have at most one type.
867 (1) a load from memory delay
868 (2) a load from a coprocessor delay
869 (3) an unconditional branch delay
870 (4) a conditional branch delay
871 (5) a move to coprocessor register delay
872 (6) a load coprocessor register from memory delay
873 (7) a coprocessor condition code delay
874 (8) a HI/LO special register delay
876 There are a lot of optimizations we could do that we don't.
877 In particular, we do not, in general, reorder instructions.
878 If you use gcc with optimization, it will reorder
879 instructions and generally do much more optimization then we
880 do here; repeating all that work in the assembler would only
881 benefit hand written assembly code, and does not seem worth
884 /* This is how a NOP is emitted. */
885 #define emit_nop() md_number_to_chars (frag_more (4), 0, 4)
887 /* The previous insn might require a delay slot, depending upon
888 the contents of the current insn. */
890 && ((prev_pinfo
& INSN_LOAD_COPROC_DELAY
)
892 && (prev_pinfo
& INSN_LOAD_MEMORY_DELAY
))))
894 /* A load from a coprocessor or from memory. All load
895 delays delay the use of general register rt for one
896 instruction on the r3000. The r6000 and r4000 use
898 know (prev_pinfo
& INSN_WRITE_GPR_T
);
899 if (mips_optimize
== 0
900 || insn_uses_reg (ip
,
901 ((prev_insn
.insn_opcode
>> OP_SH_RT
)
906 else if (mips_isa
< 4
907 && ((prev_pinfo
& INSN_COPROC_MOVE_DELAY
)
909 && (prev_pinfo
& INSN_COPROC_MEMORY_DELAY
))))
911 /* A generic coprocessor delay. The previous instruction
912 modified a coprocessor general or control register. If
913 it modified a control register, we need to avoid any
914 coprocessor instruction (this is probably not always
915 required, but it sometimes is). If it modified a general
916 register, we avoid using that register.
918 On the r6000 and r4000 loading a coprocessor register
919 from memory is interlocked, and does not require a delay.
921 This case is not handled very well. There is no special
922 knowledge of CP0 handling, and the coprocessors other
923 than the floating point unit are not distinguished at
925 if (prev_pinfo
& INSN_WRITE_FPR_T
)
927 if (mips_optimize
== 0
928 || insn_uses_reg (ip
,
929 ((prev_insn
.insn_opcode
>> OP_SH_FT
)
934 else if (prev_pinfo
& INSN_WRITE_FPR_S
)
936 if (mips_optimize
== 0
937 || insn_uses_reg (ip
,
938 ((prev_insn
.insn_opcode
>> OP_SH_FS
)
945 /* We don't know exactly what the previous instruction
946 does. If the current instruction uses a coprocessor
947 register, we must insert a NOP. If previous
948 instruction may set the condition codes, and the
949 current instruction uses them, we must insert two
951 if (mips_optimize
== 0
952 || ((prev_pinfo
& INSN_WRITE_COND_CODE
)
953 && (pinfo
& INSN_READ_COND_CODE
)))
955 else if (pinfo
& INSN_COP
)
959 else if (mips_isa
< 4
960 && (prev_pinfo
& INSN_WRITE_COND_CODE
))
962 /* The previous instruction sets the coprocessor condition
963 codes, but does not require a general coprocessor delay
964 (this means it is a floating point comparison
965 instruction). If this instruction uses the condition
966 codes, we need to insert a single NOP. */
967 if (mips_optimize
== 0
968 || (pinfo
& INSN_READ_COND_CODE
))
971 else if (prev_pinfo
& INSN_READ_LO
)
973 /* The previous instruction reads the LO register; if the
974 current instruction writes to the LO register, we must
975 insert two NOPS. The R4650 and VR4100 have interlocks. */
977 && (mips_optimize
== 0
978 || (pinfo
& INSN_WRITE_LO
)))
981 else if (prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
983 /* The previous instruction reads the HI register; if the
984 current instruction writes to the HI register, we must
985 insert a NOP. The R4650 and VR4100 have interlocks. */
987 && (mips_optimize
== 0
988 || (pinfo
& INSN_WRITE_HI
)))
992 /* There are two cases which require two intervening
993 instructions: 1) setting the condition codes using a move to
994 coprocessor instruction which requires a general coprocessor
995 delay and then reading the condition codes 2) reading the HI
996 or LO register and then writing to it (except on the R4650,
997 and VR4100 which have interlocks). If we are not already
998 emitting a NOP instruction, we must check for these cases
999 compared to the instruction previous to the previous
1003 && (prev_prev_insn
.insn_mo
->pinfo
& INSN_COPROC_MOVE_DELAY
)
1004 && (prev_prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
)
1005 && (pinfo
& INSN_READ_COND_CODE
))
1006 || ((prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
)
1007 && (pinfo
& INSN_WRITE_LO
)
1009 || ((prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
1010 && (pinfo
& INSN_WRITE_HI
)
1014 /* If we are being given a nop instruction, don't bother with
1015 one of the nops we would otherwise output. This will only
1016 happen when a nop instruction is used with mips_optimize set
1018 if (nops
> 0 && ip
->insn_opcode
== 0)
1021 /* Now emit the right number of NOP instructions. */
1026 for (i
= 0; i
< nops
; i
++)
1030 listing_prev_line ();
1031 /* We may be at the start of a variant frag. In case we
1032 are, make sure there is enough space for the frag
1033 after the frags created by listing_prev_line. The
1034 argument to frag_grow here must be at least as large
1035 as the argument to all other calls to frag_grow in
1036 this file. We don't have to worry about being in the
1037 middle of a variant frag, because the variants insert
1038 all needed nop instructions themselves. */
1041 if (insn_label
!= NULL
)
1043 assert (S_GET_SEGMENT (insn_label
) == now_seg
);
1044 insn_label
->sy_frag
= frag_now
;
1045 S_SET_VALUE (insn_label
, (valueT
) frag_now_fix ());
1055 if (address_expr
!= NULL
)
1057 if (address_expr
->X_op
== O_constant
)
1062 ip
->insn_opcode
|= address_expr
->X_add_number
;
1065 case BFD_RELOC_LO16
:
1066 ip
->insn_opcode
|= address_expr
->X_add_number
& 0xffff;
1069 case BFD_RELOC_MIPS_JMP
:
1070 case BFD_RELOC_16_PCREL_S2
:
1079 assert (reloc_type
!= BFD_RELOC_UNUSED
);
1081 /* Don't generate a reloc if we are writing into a variant
1084 fixp
= fix_new_exp (frag_now
, f
- frag_now
->fr_literal
, 4,
1086 reloc_type
== BFD_RELOC_16_PCREL_S2
,
1091 md_number_to_chars (f
, ip
->insn_opcode
, 4);
1093 /* Update the register mask information. */
1094 if (pinfo
& INSN_WRITE_GPR_D
)
1095 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
);
1096 if ((pinfo
& (INSN_WRITE_GPR_T
| INSN_READ_GPR_T
)) != 0)
1097 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
);
1098 if (pinfo
& INSN_READ_GPR_S
)
1099 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> OP_SH_RS
) & OP_MASK_RS
);
1100 if (pinfo
& INSN_WRITE_GPR_31
)
1101 mips_gprmask
|= 1 << 31;
1102 if (pinfo
& INSN_WRITE_FPR_D
)
1103 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FD
) & OP_MASK_FD
);
1104 if ((pinfo
& (INSN_WRITE_FPR_S
| INSN_READ_FPR_S
)) != 0)
1105 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FS
) & OP_MASK_FS
);
1106 if ((pinfo
& (INSN_WRITE_FPR_T
| INSN_READ_FPR_T
)) != 0)
1107 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FT
) & OP_MASK_FT
);
1108 if ((pinfo
& INSN_READ_FPR_R
) != 0)
1109 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FR
) & OP_MASK_FR
);
1110 if (pinfo
& INSN_COP
)
1112 /* We don't keep enough information to sort these cases out. */
1114 /* Never set the bit for $0, which is always zero. */
1115 mips_gprmask
&=~ 1 << 0;
1117 if (place
== NULL
&& ! mips_noreorder
)
1119 /* Filling the branch delay slot is more complex. We try to
1120 switch the branch with the previous instruction, which we can
1121 do if the previous instruction does not set up a condition
1122 that the branch tests and if the branch is not itself the
1123 target of any branch. */
1124 if ((pinfo
& INSN_UNCOND_BRANCH_DELAY
)
1125 || (pinfo
& INSN_COND_BRANCH_DELAY
))
1127 if (mips_optimize
< 2
1128 /* If we have seen .set volatile or .set nomove, don't
1131 /* If we had to emit any NOP instructions, then we
1132 already know we can not swap. */
1134 /* If we don't even know the previous insn, we can not
1136 || ! prev_insn_valid
1137 /* If the previous insn is already in a branch delay
1138 slot, then we can not swap. */
1139 || prev_insn_is_delay_slot
1140 /* If the previous previous insn was in a .set
1141 noreorder, we can't swap. Actually, the MIPS
1142 assembler will swap in this situation. However, gcc
1143 configured -with-gnu-as will generate code like
1149 in which we can not swap the bne and INSN. If gcc is
1150 not configured -with-gnu-as, it does not output the
1151 .set pseudo-ops. We don't have to check
1152 prev_insn_unreordered, because prev_insn_valid will
1153 be 0 in that case. We don't want to use
1154 prev_prev_insn_valid, because we do want to be able
1155 to swap at the start of a function. */
1156 || prev_prev_insn_unreordered
1157 /* If the branch is itself the target of a branch, we
1158 can not swap. We cheat on this; all we check for is
1159 whether there is a label on this instruction. If
1160 there are any branches to anything other than a
1161 label, users must use .set noreorder. */
1162 || insn_label
!= NULL
1163 /* If the previous instruction is in a variant frag, we
1164 can not do the swap. */
1165 || prev_insn_frag
->fr_type
== rs_machine_dependent
1166 /* If the branch reads the condition codes, we don't
1167 even try to swap, because in the sequence
1172 we can not swap, and I don't feel like handling that
1175 && (pinfo
& INSN_READ_COND_CODE
))
1176 /* We can not swap with an instruction that requires a
1177 delay slot, becase the target of the branch might
1178 interfere with that instruction. */
1181 & (INSN_LOAD_COPROC_DELAY
1182 | INSN_COPROC_MOVE_DELAY
1183 | INSN_WRITE_COND_CODE
)))
1190 & (INSN_LOAD_MEMORY_DELAY
1191 | INSN_COPROC_MEMORY_DELAY
)))
1192 /* We can not swap with a branch instruction. */
1194 & (INSN_UNCOND_BRANCH_DELAY
1195 | INSN_COND_BRANCH_DELAY
1196 | INSN_COND_BRANCH_LIKELY
))
1197 /* We do not swap with a trap instruction, since it
1198 complicates trap handlers to have the trap
1199 instruction be in a delay slot. */
1200 || (prev_pinfo
& INSN_TRAP
)
1201 /* If the branch reads a register that the previous
1202 instruction sets, we can not swap. */
1203 || ((prev_pinfo
& INSN_WRITE_GPR_T
)
1204 && insn_uses_reg (ip
,
1205 ((prev_insn
.insn_opcode
>> OP_SH_RT
)
1208 || ((prev_pinfo
& INSN_WRITE_GPR_D
)
1209 && insn_uses_reg (ip
,
1210 ((prev_insn
.insn_opcode
>> OP_SH_RD
)
1213 /* If the branch writes a register that the previous
1214 instruction sets, we can not swap (we know that
1215 branches write only to RD or to $31). */
1216 || ((prev_pinfo
& INSN_WRITE_GPR_T
)
1217 && (((pinfo
& INSN_WRITE_GPR_D
)
1218 && (((prev_insn
.insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
)
1219 == ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)))
1220 || ((pinfo
& INSN_WRITE_GPR_31
)
1221 && (((prev_insn
.insn_opcode
>> OP_SH_RT
)
1224 || ((prev_pinfo
& INSN_WRITE_GPR_D
)
1225 && (((pinfo
& INSN_WRITE_GPR_D
)
1226 && (((prev_insn
.insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)
1227 == ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)))
1228 || ((pinfo
& INSN_WRITE_GPR_31
)
1229 && (((prev_insn
.insn_opcode
>> OP_SH_RD
)
1232 /* If the branch writes a register that the previous
1233 instruction reads, we can not swap (we know that
1234 branches only write to RD or to $31). */
1235 || ((pinfo
& INSN_WRITE_GPR_D
)
1236 && insn_uses_reg (&prev_insn
,
1237 ((ip
->insn_opcode
>> OP_SH_RD
)
1240 || ((pinfo
& INSN_WRITE_GPR_31
)
1241 && insn_uses_reg (&prev_insn
, 31, 0))
1242 /* If we are generating embedded PIC code, the branch
1243 might be expanded into a sequence which uses $at, so
1244 we can't swap with an instruction which reads it. */
1245 || (mips_pic
== EMBEDDED_PIC
1246 && insn_uses_reg (&prev_insn
, AT
, 0))
1247 /* If the previous previous instruction has a load
1248 delay, and sets a register that the branch reads, we
1251 && ((prev_prev_insn
.insn_mo
->pinfo
& INSN_LOAD_COPROC_DELAY
)
1253 && (prev_prev_insn
.insn_mo
->pinfo
1254 & INSN_LOAD_MEMORY_DELAY
)))
1255 && insn_uses_reg (ip
,
1256 ((prev_prev_insn
.insn_opcode
>> OP_SH_RT
)
1260 /* We could do even better for unconditional branches to
1261 portions of this object file; we could pick up the
1262 instruction at the destination, put it in the delay
1263 slot, and bump the destination address. */
1265 /* Update the previous insn information. */
1266 prev_prev_insn
= *ip
;
1267 prev_insn
.insn_mo
= &dummy_opcode
;
1274 /* It looks like we can actually do the swap. */
1275 prev_f
= prev_insn_frag
->fr_literal
+ prev_insn_where
;
1276 memcpy (temp
, prev_f
, 4);
1277 memcpy (prev_f
, f
, 4);
1278 memcpy (f
, temp
, 4);
1281 prev_insn_fixp
->fx_frag
= frag_now
;
1282 prev_insn_fixp
->fx_where
= f
- frag_now
->fr_literal
;
1286 fixp
->fx_frag
= prev_insn_frag
;
1287 fixp
->fx_where
= prev_insn_where
;
1289 /* Update the previous insn information; leave prev_insn
1291 prev_prev_insn
= *ip
;
1293 prev_insn_is_delay_slot
= 1;
1295 /* If that was an unconditional branch, forget the previous
1296 insn information. */
1297 if (pinfo
& INSN_UNCOND_BRANCH_DELAY
)
1299 prev_prev_insn
.insn_mo
= &dummy_opcode
;
1300 prev_insn
.insn_mo
= &dummy_opcode
;
1303 else if (pinfo
& INSN_COND_BRANCH_LIKELY
)
1305 /* We don't yet optimize a branch likely. What we should do
1306 is look at the target, copy the instruction found there
1307 into the delay slot, and increment the branch to jump to
1308 the next instruction. */
1310 /* Update the previous insn information. */
1311 prev_prev_insn
= *ip
;
1312 prev_insn
.insn_mo
= &dummy_opcode
;
1316 /* Update the previous insn information. */
1318 prev_prev_insn
.insn_mo
= &dummy_opcode
;
1320 prev_prev_insn
= prev_insn
;
1323 /* Any time we see a branch, we always fill the delay slot
1324 immediately; since this insn is not a branch, we know it
1325 is not in a delay slot. */
1326 prev_insn_is_delay_slot
= 0;
1329 prev_prev_insn_unreordered
= prev_insn_unreordered
;
1330 prev_insn_unreordered
= 0;
1331 prev_insn_frag
= frag_now
;
1332 prev_insn_where
= f
- frag_now
->fr_literal
;
1333 prev_insn_fixp
= fixp
;
1334 prev_insn_valid
= 1;
1337 /* We just output an insn, so the next one doesn't have a label. */
1341 /* This function forgets that there was any previous instruction or
1345 mips_no_prev_insn ()
1347 prev_insn
.insn_mo
= &dummy_opcode
;
1348 prev_prev_insn
.insn_mo
= &dummy_opcode
;
1349 prev_insn_valid
= 0;
1350 prev_insn_is_delay_slot
= 0;
1351 prev_insn_unreordered
= 0;
1352 prev_prev_insn_unreordered
= 0;
1356 /* This function must be called whenever we turn on noreorder or emit
1357 something other than instructions. It inserts any NOPS which might
1358 be needed by the previous instruction, and clears the information
1359 kept for the previous instructions. */
1364 if (! mips_noreorder
)
1370 && (prev_insn
.insn_mo
->pinfo
1371 & (INSN_LOAD_COPROC_DELAY
1372 | INSN_COPROC_MOVE_DELAY
1373 | INSN_WRITE_COND_CODE
)))
1375 && (prev_insn
.insn_mo
->pinfo
1379 && (prev_insn
.insn_mo
->pinfo
1380 & (INSN_LOAD_MEMORY_DELAY
1381 | INSN_COPROC_MEMORY_DELAY
))))
1385 && (prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
))
1387 && ((prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
1388 || (prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
))))
1391 else if ((mips_isa
< 4
1392 && (prev_prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
))
1394 && ((prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
1395 || (prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
))))
1400 if (insn_label
!= NULL
)
1402 assert (S_GET_SEGMENT (insn_label
) == now_seg
);
1403 insn_label
->sy_frag
= frag_now
;
1404 S_SET_VALUE (insn_label
, (valueT
) frag_now_fix ());
1409 mips_no_prev_insn ();
1412 /* Build an instruction created by a macro expansion. This is passed
1413 a pointer to the count of instructions created so far, an
1414 expression, the name of the instruction to build, an operand format
1415 string, and corresponding arguments. */
1419 macro_build (char *place
,
1427 macro_build (place
, counter
, ep
, name
, fmt
, va_alist
)
1436 struct mips_cl_insn insn
;
1437 bfd_reloc_code_real_type r
;
1441 va_start (args
, fmt
);
1447 * If the macro is about to expand into a second instruction,
1448 * print a warning if needed. We need to pass ip as a parameter
1449 * to generate a better warning message here...
1451 if (mips_warn_about_macros
&& place
== NULL
&& *counter
== 1)
1452 as_warn ("Macro instruction expanded into multiple instructions");
1455 *counter
+= 1; /* bump instruction counter */
1457 r
= BFD_RELOC_UNUSED
;
1458 insn
.insn_mo
= (struct mips_opcode
*) hash_find (op_hash
, name
);
1459 assert (insn
.insn_mo
);
1460 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
1462 while (strcmp (fmt
, insn
.insn_mo
->args
) != 0
1463 || insn
.insn_mo
->pinfo
== INSN_MACRO
1464 || ((insn
.insn_mo
->pinfo
& INSN_ISA
) == INSN_ISA2
1466 || ((insn
.insn_mo
->pinfo
& INSN_ISA
) == INSN_ISA3
1468 || ((insn
.insn_mo
->pinfo
& INSN_ISA
) == INSN_ISA4
1470 || ((insn
.insn_mo
->pinfo
& INSN_ISA
) == INSN_4650
1472 || ((insn
.insn_mo
->pinfo
& INSN_ISA
) == INSN_4010
1474 || ((insn
.insn_mo
->pinfo
& INSN_ISA
) == INSN_4100
1478 assert (insn
.insn_mo
->name
);
1479 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
1481 insn
.insn_opcode
= insn
.insn_mo
->match
;
1497 insn
.insn_opcode
|= va_arg (args
, int) << 16;
1503 insn
.insn_opcode
|= va_arg (args
, int) << 16;
1508 insn
.insn_opcode
|= va_arg (args
, int) << 11;
1513 insn
.insn_opcode
|= va_arg (args
, int) << 11;
1520 insn
.insn_opcode
|= va_arg (args
, int) << 6;
1524 insn
.insn_opcode
|= va_arg (args
, int) << 6;
1528 insn
.insn_opcode
|= va_arg (args
, int) << 6;
1535 insn
.insn_opcode
|= va_arg (args
, int) << 21;
1541 r
= (bfd_reloc_code_real_type
) va_arg (args
, int);
1542 assert (r
== BFD_RELOC_MIPS_GPREL
1543 || r
== BFD_RELOC_MIPS_LITERAL
1544 || r
== BFD_RELOC_LO16
1545 || r
== BFD_RELOC_MIPS_GOT16
1546 || r
== BFD_RELOC_MIPS_CALL16
1547 || (ep
->X_op
== O_subtract
1548 && now_seg
== text_section
1549 && r
== BFD_RELOC_PCREL_LO16
));
1553 r
= (bfd_reloc_code_real_type
) va_arg (args
, int);
1555 && (ep
->X_op
== O_constant
1556 || (ep
->X_op
== O_symbol
1557 && (r
== BFD_RELOC_HI16_S
1558 || r
== BFD_RELOC_HI16
))
1559 || (ep
->X_op
== O_subtract
1560 && now_seg
== text_section
1561 && r
== BFD_RELOC_PCREL_HI16_S
)));
1562 if (ep
->X_op
== O_constant
)
1564 insn
.insn_opcode
|= (ep
->X_add_number
>> 16) & 0xffff;
1566 r
= BFD_RELOC_UNUSED
;
1571 assert (ep
!= NULL
);
1573 * This allows macro() to pass an immediate expression for
1574 * creating short branches without creating a symbol.
1575 * Note that the expression still might come from the assembly
1576 * input, in which case the value is not checked for range nor
1577 * is a relocation entry generated (yuck).
1579 if (ep
->X_op
== O_constant
)
1581 insn
.insn_opcode
|= (ep
->X_add_number
>> 2) & 0xffff;
1585 r
= BFD_RELOC_16_PCREL_S2
;
1589 assert (ep
!= NULL
);
1590 r
= BFD_RELOC_MIPS_JMP
;
1599 assert (r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
1601 append_insn (place
, &insn
, ep
, r
);
1605 * Generate a "lui" instruction.
1608 macro_build_lui (place
, counter
, ep
, regnum
)
1614 expressionS high_expr
;
1615 struct mips_cl_insn insn
;
1616 bfd_reloc_code_real_type r
;
1617 CONST
char *name
= "lui";
1618 CONST
char *fmt
= "t,u";
1624 high_expr
.X_op
= O_constant
;
1625 high_expr
.X_add_number
= 0;
1628 if (high_expr
.X_op
== O_constant
)
1630 /* we can compute the instruction now without a relocation entry */
1631 if (high_expr
.X_add_number
& 0x8000)
1632 high_expr
.X_add_number
+= 0x10000;
1633 high_expr
.X_add_number
=
1634 ((unsigned long) high_expr
.X_add_number
>> 16) & 0xffff;
1635 r
= BFD_RELOC_UNUSED
;
1639 assert (ep
->X_op
== O_symbol
);
1640 /* _gp_disp is a special case, used from s_cpload. */
1641 assert (mips_pic
== NO_PIC
1642 || strcmp (S_GET_NAME (ep
->X_add_symbol
), "_gp_disp") == 0);
1643 r
= BFD_RELOC_HI16_S
;
1647 * If the macro is about to expand into a second instruction,
1648 * print a warning if needed. We need to pass ip as a parameter
1649 * to generate a better warning message here...
1651 if (mips_warn_about_macros
&& place
== NULL
&& *counter
== 1)
1652 as_warn ("Macro instruction expanded into multiple instructions");
1655 *counter
+= 1; /* bump instruction counter */
1657 insn
.insn_mo
= (struct mips_opcode
*) hash_find (op_hash
, name
);
1658 assert (insn
.insn_mo
);
1659 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
1660 assert (strcmp (fmt
, insn
.insn_mo
->args
) == 0);
1662 insn
.insn_opcode
= insn
.insn_mo
->match
| (regnum
<< OP_SH_RT
);
1663 if (r
== BFD_RELOC_UNUSED
)
1665 insn
.insn_opcode
|= high_expr
.X_add_number
;
1666 append_insn (place
, &insn
, NULL
, r
);
1669 append_insn (place
, &insn
, &high_expr
, r
);
1673 * Generates code to set the $at register to true (one)
1674 * if reg is less than the immediate expression.
1677 set_at (counter
, reg
, unsignedp
)
1682 if (imm_expr
.X_add_number
>= -0x8000 && imm_expr
.X_add_number
< 0x8000)
1683 macro_build ((char *) NULL
, counter
, &imm_expr
,
1684 unsignedp
? "sltiu" : "slti",
1685 "t,r,j", AT
, reg
, (int) BFD_RELOC_LO16
);
1688 load_register (counter
, AT
, &imm_expr
, 0);
1689 macro_build ((char *) NULL
, counter
, NULL
,
1690 unsignedp
? "sltu" : "slt",
1691 "d,v,t", AT
, reg
, AT
);
1695 /* Warn if an expression is not a constant. */
1698 check_absolute_expr (ip
, ex
)
1699 struct mips_cl_insn
*ip
;
1702 if (ex
->X_op
!= O_constant
)
1703 as_warn ("Instruction %s requires absolute expression", ip
->insn_mo
->name
);
1707 * This routine generates the least number of instructions neccessary to load
1708 * an absolute expression value into a register.
1711 load_register (counter
, reg
, ep
, dbl
)
1718 expressionS hi32
, lo32
, tmp
;
1720 if (ep
->X_op
!= O_big
)
1722 assert (ep
->X_op
== O_constant
);
1723 if (ep
->X_add_number
< 0x8000
1724 && (ep
->X_add_number
>= 0
1725 || (ep
->X_add_number
>= -0x8000
1728 || sizeof (ep
->X_add_number
) > 4))))
1730 /* We can handle 16 bit signed values with an addiu to
1731 $zero. No need to ever use daddiu here, since $zero and
1732 the result are always correct in 32 bit mode. */
1733 macro_build ((char *) NULL
, counter
, ep
, "addiu", "t,r,j", reg
, 0,
1734 (int) BFD_RELOC_LO16
);
1737 else if (ep
->X_add_number
>= 0 && ep
->X_add_number
< 0x10000)
1739 /* We can handle 16 bit unsigned values with an ori to
1741 macro_build ((char *) NULL
, counter
, ep
, "ori", "t,r,i", reg
, 0,
1742 (int) BFD_RELOC_LO16
);
1745 else if (((ep
->X_add_number
&~ (offsetT
) 0x7fffffff) == 0
1746 || ((ep
->X_add_number
&~ (offsetT
) 0x7fffffff)
1747 == ~ (offsetT
) 0x7fffffff))
1750 || sizeof (ep
->X_add_number
) > 4
1751 || (ep
->X_add_number
& 0x80000000) == 0))
1753 /* 32 bit values require an lui. */
1754 macro_build ((char *) NULL
, counter
, ep
, "lui", "t,u", reg
,
1755 (int) BFD_RELOC_HI16
);
1756 if ((ep
->X_add_number
& 0xffff) != 0)
1757 macro_build ((char *) NULL
, counter
, ep
, "ori", "t,r,i", reg
, reg
,
1758 (int) BFD_RELOC_LO16
);
1763 /* 32 bit value with high bit set being loaded into a 64 bit
1764 register. We can't use lui, because that would
1765 incorrectly set the 32 high bits. */
1766 generic_bignum
[3] = 0;
1767 generic_bignum
[2] = 0;
1768 generic_bignum
[1] = (ep
->X_add_number
>> 16) & 0xffff;
1769 generic_bignum
[0] = ep
->X_add_number
& 0xffff;
1771 tmp
.X_add_number
= 4;
1776 /* The value is larger than 32 bits. */
1780 as_bad ("Number larger than 32 bits");
1781 macro_build ((char *) NULL
, counter
, ep
, "addiu", "t,r,j", reg
, 0,
1782 (int) BFD_RELOC_LO16
);
1786 if (ep
->X_op
!= O_big
)
1790 hi32
.X_add_number
>>= shift
;
1791 hi32
.X_add_number
&= 0xffffffff;
1792 if ((hi32
.X_add_number
& 0x80000000) != 0)
1793 hi32
.X_add_number
|= ~ (offsetT
) 0xffffffff;
1795 lo32
.X_add_number
&= 0xffffffff;
1799 assert (ep
->X_add_number
> 2);
1800 if (ep
->X_add_number
== 3)
1801 generic_bignum
[3] = 0;
1802 else if (ep
->X_add_number
> 4)
1803 as_bad ("Number larger than 64 bits");
1804 lo32
.X_op
= O_constant
;
1805 lo32
.X_add_number
= generic_bignum
[0] + (generic_bignum
[1] << 16);
1806 hi32
.X_op
= O_constant
;
1807 hi32
.X_add_number
= generic_bignum
[2] + (generic_bignum
[3] << 16);
1810 if (hi32
.X_add_number
== 0)
1814 load_register (counter
, reg
, &hi32
, 0);
1817 if ((lo32
.X_add_number
& 0xffff0000) == 0)
1821 macro_build ((char *) NULL
, counter
, NULL
, "dsll32", "d,w,<", reg
,
1832 macro_build ((char *) NULL
, counter
, NULL
, "dsll", "d,w,<", reg
,
1837 mid16
.X_add_number
>>= 16;
1838 macro_build ((char *) NULL
, counter
, &mid16
, "ori", "t,r,i", reg
,
1839 freg
, (int) BFD_RELOC_LO16
);
1840 macro_build ((char *) NULL
, counter
, NULL
, "dsll", "d,w,<", reg
,
1844 if ((lo32
.X_add_number
& 0xffff) != 0)
1845 macro_build ((char *) NULL
, counter
, &lo32
, "ori", "t,r,i", reg
, freg
,
1846 (int) BFD_RELOC_LO16
);
1849 /* Load an address into a register. */
1852 load_address (counter
, reg
, ep
)
1859 if (ep
->X_op
!= O_constant
1860 && ep
->X_op
!= O_symbol
)
1862 as_bad ("expression too complex");
1863 ep
->X_op
= O_constant
;
1866 if (ep
->X_op
== O_constant
)
1868 load_register (counter
, reg
, ep
, 0);
1872 if (mips_pic
== NO_PIC
)
1874 /* If this is a reference to a GP relative symbol, we want
1875 addiu $reg,$gp,<sym> (BFD_RELOC_MIPS_GPREL)
1877 lui $reg,<sym> (BFD_RELOC_HI16_S)
1878 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
1879 If we have an addend, we always use the latter form. */
1880 if (ep
->X_add_number
!= 0 || nopic_need_relax (ep
->X_add_symbol
))
1885 macro_build ((char *) NULL
, counter
, ep
,
1886 mips_isa
< 3 ? "addiu" : "daddiu",
1887 "t,r,j", reg
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
1888 p
= frag_var (rs_machine_dependent
, 8, 0,
1889 RELAX_ENCODE (4, 8, 0, 4, 0, mips_warn_about_macros
),
1890 ep
->X_add_symbol
, (long) 0, (char *) NULL
);
1892 macro_build_lui (p
, counter
, ep
, reg
);
1895 macro_build (p
, counter
, ep
,
1896 mips_isa
< 3 ? "addiu" : "daddiu",
1897 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
1899 else if (mips_pic
== SVR4_PIC
)
1903 /* If this is a reference to an external symbol, we want
1904 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
1906 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
1908 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
1909 If there is a constant, it must be added in after. */
1910 ex
.X_add_number
= ep
->X_add_number
;
1911 ep
->X_add_number
= 0;
1913 macro_build ((char *) NULL
, counter
, ep
,
1914 mips_isa
< 3 ? "lw" : "ld",
1915 "t,o(b)", reg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
1916 macro_build ((char *) NULL
, counter
, (expressionS
*) NULL
, "nop", "");
1917 p
= frag_var (rs_machine_dependent
, 4, 0,
1918 RELAX_ENCODE (0, 4, -8, 0, 0, mips_warn_about_macros
),
1919 ep
->X_add_symbol
, (long) 0, (char *) NULL
);
1920 macro_build (p
, counter
, ep
,
1921 mips_isa
< 3 ? "addiu" : "daddiu",
1922 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
1923 if (ex
.X_add_number
!= 0)
1925 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
1926 as_bad ("PIC code offset overflow (max 16 signed bits)");
1927 ex
.X_op
= O_constant
;
1928 macro_build (p
, counter
, &ex
,
1929 mips_isa
< 3 ? "addiu" : "daddiu",
1930 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
1933 else if (mips_pic
== EMBEDDED_PIC
)
1936 addiu $reg,$gp,<sym> (BFD_RELOC_MIPS_GPREL)
1938 macro_build ((char *) NULL
, counter
, ep
,
1939 mips_isa
< 3 ? "addiu" : "daddiu",
1940 "t,r,j", reg
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
1948 * This routine implements the seemingly endless macro or synthesized
1949 * instructions and addressing modes in the mips assembly language. Many
1950 * of these macros are simple and are similar to each other. These could
1951 * probably be handled by some kind of table or grammer aproach instead of
1952 * this verbose method. Others are not simple macros but are more like
1953 * optimizing code generation.
1954 * One interesting optimization is when several store macros appear
1955 * consecutivly that would load AT with the upper half of the same address.
1956 * The ensuing load upper instructions are ommited. This implies some kind
1957 * of global optimization. We currently only optimize within a single macro.
1958 * For many of the load and store macros if the address is specified as a
1959 * constant expression in the first 64k of memory (ie ld $2,0x4000c) we
1960 * first load register 'at' with zero and use it as the base register. The
1961 * mips assembler simply uses register $zero. Just one tiny optimization
1966 struct mips_cl_insn
*ip
;
1968 register int treg
, sreg
, dreg
, breg
;
1983 bfd_reloc_code_real_type r
;
1985 int hold_mips_optimize
;
1987 treg
= (ip
->insn_opcode
>> 16) & 0x1f;
1988 dreg
= (ip
->insn_opcode
>> 11) & 0x1f;
1989 sreg
= breg
= (ip
->insn_opcode
>> 21) & 0x1f;
1990 mask
= ip
->insn_mo
->mask
;
1992 expr1
.X_op
= O_constant
;
1993 expr1
.X_op_symbol
= NULL
;
1994 expr1
.X_add_symbol
= NULL
;
1995 expr1
.X_add_number
= 1;
2007 mips_emit_delays ();
2009 mips_any_noreorder
= 1;
2011 expr1
.X_add_number
= 8;
2012 macro_build ((char *) NULL
, &icnt
, &expr1
, "bgez", "s,p", sreg
);
2014 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
2016 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
, sreg
, 0);
2017 macro_build ((char *) NULL
, &icnt
, NULL
,
2018 dbl
? "dsub" : "sub",
2019 "d,v,t", dreg
, 0, sreg
);
2042 if (imm_expr
.X_add_number
>= -0x8000 && imm_expr
.X_add_number
< 0x8000)
2044 macro_build ((char *) NULL
, &icnt
, &imm_expr
, s
, "t,r,j", treg
, sreg
,
2045 (int) BFD_RELOC_LO16
);
2048 load_register (&icnt
, AT
, &imm_expr
, dbl
);
2049 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "d,v,t", treg
, sreg
, AT
);
2068 if (imm_expr
.X_add_number
>= 0 && imm_expr
.X_add_number
< 0x10000)
2070 if (mask
!= M_NOR_I
)
2071 macro_build ((char *) NULL
, &icnt
, &imm_expr
, s
, "t,r,i", treg
,
2072 sreg
, (int) BFD_RELOC_LO16
);
2075 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "ori", "t,r,i",
2076 treg
, sreg
, (int) BFD_RELOC_LO16
);
2077 macro_build ((char *) NULL
, &icnt
, NULL
, "nor", "d,v,t",
2083 load_register (&icnt
, AT
, &imm_expr
, 0);
2084 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "d,v,t", treg
, sreg
, AT
);
2101 if (imm_expr
.X_add_number
== 0)
2103 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "s,t,p", sreg
,
2107 load_register (&icnt
, AT
, &imm_expr
, 0);
2108 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "s,t,p", sreg
, AT
);
2116 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2117 likely
? "bgezl" : "bgez",
2123 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2124 likely
? "blezl" : "blez",
2128 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", AT
, sreg
, treg
);
2129 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2130 likely
? "beql" : "beq",
2137 /* check for > max integer */
2138 maxnum
= 0x7fffffff;
2146 if (imm_expr
.X_add_number
>= maxnum
2147 && (mips_isa
< 3 || sizeof (maxnum
) > 4))
2150 /* result is always false */
2153 as_warn ("Branch %s is always false (nop)", ip
->insn_mo
->name
);
2154 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
2158 as_warn ("Branch likely %s is always false", ip
->insn_mo
->name
);
2159 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "bnel",
2164 imm_expr
.X_add_number
++;
2168 if (mask
== M_BGEL_I
)
2170 if (imm_expr
.X_add_number
== 0)
2172 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2173 likely
? "bgezl" : "bgez",
2177 if (imm_expr
.X_add_number
== 1)
2179 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2180 likely
? "bgtzl" : "bgtz",
2184 maxnum
= 0x7fffffff;
2192 maxnum
= - maxnum
- 1;
2193 if (imm_expr
.X_add_number
<= maxnum
2194 && (mips_isa
< 3 || sizeof (maxnum
) > 4))
2197 /* result is always true */
2198 as_warn ("Branch %s is always true", ip
->insn_mo
->name
);
2199 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "b", "p");
2202 set_at (&icnt
, sreg
, 0);
2203 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2204 likely
? "beql" : "beq",
2215 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2216 likely
? "beql" : "beq",
2220 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", AT
, sreg
,
2222 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2223 likely
? "beql" : "beq",
2230 if (sreg
== 0 || imm_expr
.X_add_number
== -1)
2232 imm_expr
.X_add_number
++;
2236 if (mask
== M_BGEUL_I
)
2238 if (imm_expr
.X_add_number
== 0)
2240 if (imm_expr
.X_add_number
== 1)
2242 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2243 likely
? "bnel" : "bne",
2247 set_at (&icnt
, sreg
, 1);
2248 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2249 likely
? "beql" : "beq",
2258 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2259 likely
? "bgtzl" : "bgtz",
2265 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2266 likely
? "bltzl" : "bltz",
2270 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", AT
, treg
, sreg
);
2271 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2272 likely
? "bnel" : "bne",
2281 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2282 likely
? "bnel" : "bne",
2288 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", AT
, treg
,
2290 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2291 likely
? "bnel" : "bne",
2300 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2301 likely
? "blezl" : "blez",
2307 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2308 likely
? "bgezl" : "bgez",
2312 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", AT
, treg
, sreg
);
2313 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2314 likely
? "beql" : "beq",
2321 maxnum
= 0x7fffffff;
2329 if (imm_expr
.X_add_number
>= maxnum
2330 && (mips_isa
< 3 || sizeof (maxnum
) > 4))
2332 imm_expr
.X_add_number
++;
2336 if (mask
== M_BLTL_I
)
2338 if (imm_expr
.X_add_number
== 0)
2340 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2341 likely
? "bltzl" : "bltz",
2345 if (imm_expr
.X_add_number
== 1)
2347 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2348 likely
? "blezl" : "blez",
2352 set_at (&icnt
, sreg
, 0);
2353 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2354 likely
? "bnel" : "bne",
2363 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2364 likely
? "beql" : "beq",
2370 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", AT
, treg
,
2372 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2373 likely
? "beql" : "beq",
2380 if (sreg
== 0 || imm_expr
.X_add_number
== -1)
2382 imm_expr
.X_add_number
++;
2386 if (mask
== M_BLTUL_I
)
2388 if (imm_expr
.X_add_number
== 0)
2390 if (imm_expr
.X_add_number
== 1)
2392 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2393 likely
? "beql" : "beq",
2397 set_at (&icnt
, sreg
, 1);
2398 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2399 likely
? "bnel" : "bne",
2408 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2409 likely
? "bltzl" : "bltz",
2415 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2416 likely
? "bgtzl" : "bgtz",
2420 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", AT
, sreg
, treg
);
2421 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2422 likely
? "bnel" : "bne",
2433 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2434 likely
? "bnel" : "bne",
2438 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", AT
, sreg
,
2440 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2441 likely
? "bnel" : "bne",
2457 as_warn ("Divide by zero.");
2459 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", 0, 0);
2461 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 7);
2465 mips_emit_delays ();
2467 mips_any_noreorder
= 1;
2468 macro_build ((char *) NULL
, &icnt
, NULL
,
2469 dbl
? "ddiv" : "div",
2470 "z,s,t", sreg
, treg
);
2472 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", treg
, 0);
2475 expr1
.X_add_number
= 8;
2476 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", treg
, 0);
2477 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
2478 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 7);
2480 expr1
.X_add_number
= -1;
2481 macro_build ((char *) NULL
, &icnt
, &expr1
,
2482 dbl
? "daddiu" : "addiu",
2483 "t,r,j", AT
, 0, (int) BFD_RELOC_LO16
);
2484 expr1
.X_add_number
= mips_trap
? (dbl
? 12 : 8) : (dbl
? 20 : 16);
2485 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", treg
, AT
);
2488 expr1
.X_add_number
= 1;
2489 macro_build ((char *) NULL
, &icnt
, &expr1
, "daddiu", "t,r,j", AT
, 0,
2490 (int) BFD_RELOC_LO16
);
2491 macro_build ((char *) NULL
, &icnt
, NULL
, "dsll32", "d,w,<", AT
, AT
,
2496 expr1
.X_add_number
= 0x80000000;
2497 macro_build ((char *) NULL
, &icnt
, &expr1
, "lui", "t,u", AT
,
2498 (int) BFD_RELOC_HI16
);
2501 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", sreg
, AT
);
2504 expr1
.X_add_number
= 8;
2505 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", sreg
, AT
);
2506 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
2507 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 6);
2510 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d", dreg
);
2549 if (imm_expr
.X_add_number
== 0)
2551 as_warn ("Divide by zero.");
2553 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", 0, 0);
2555 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 7);
2558 if (imm_expr
.X_add_number
== 1)
2560 if (strcmp (s2
, "mflo") == 0)
2561 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
,
2564 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
, 0);
2567 if (imm_expr
.X_add_number
== -1
2568 && s
[strlen (s
) - 1] != 'u')
2570 if (strcmp (s2
, "mflo") == 0)
2573 macro_build ((char *) NULL
, &icnt
, NULL
, "dneg", "d,w", dreg
,
2576 macro_build ((char *) NULL
, &icnt
, NULL
, "neg", "d,w", dreg
,
2580 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
, 0);
2584 load_register (&icnt
, AT
, &imm_expr
, dbl
);
2585 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "z,s,t", sreg
, AT
);
2586 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "d", dreg
);
2605 mips_emit_delays ();
2607 mips_any_noreorder
= 1;
2608 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "z,s,t", sreg
, treg
);
2610 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", treg
, 0);
2613 expr1
.X_add_number
= 8;
2614 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", treg
, 0);
2615 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
2616 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 7);
2619 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "d", dreg
);
2625 /* Load the address of a symbol into a register. If breg is not
2626 zero, we then add a base register to it. */
2628 /* When generating embedded PIC code, we permit expressions of
2631 where bar is an address in the .text section. These are used
2632 when getting the addresses of functions. We don't permit
2633 X_add_number to be non-zero, because if the symbol is
2634 external the relaxing code needs to know that any addend is
2635 purely the offset to X_op_symbol. */
2636 if (mips_pic
== EMBEDDED_PIC
2637 && offset_expr
.X_op
== O_subtract
2638 && now_seg
== text_section
2639 && (offset_expr
.X_op_symbol
->sy_value
.X_op
== O_constant
2640 ? S_GET_SEGMENT (offset_expr
.X_op_symbol
) == text_section
2641 : (offset_expr
.X_op_symbol
->sy_value
.X_op
== O_symbol
2642 && (S_GET_SEGMENT (offset_expr
.X_op_symbol
2643 ->sy_value
.X_add_symbol
)
2646 && offset_expr
.X_add_number
== 0)
2648 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
2649 treg
, (int) BFD_RELOC_PCREL_HI16_S
);
2650 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2651 mips_isa
< 3 ? "addiu" : "daddiu",
2652 "t,r,j", treg
, treg
, (int) BFD_RELOC_PCREL_LO16
);
2656 if (offset_expr
.X_op
!= O_symbol
2657 && offset_expr
.X_op
!= O_constant
)
2659 as_bad ("expression too complex");
2660 offset_expr
.X_op
= O_constant
;
2674 if (offset_expr
.X_op
== O_constant
)
2675 load_register (&icnt
, tempreg
, &offset_expr
, dbl
);
2676 else if (mips_pic
== NO_PIC
)
2678 /* If this is a reference to an GP relative symbol, we want
2679 addiu $tempreg,$gp,<sym> (BFD_RELOC_MIPS_GPREL)
2681 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
2682 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
2683 If we have a constant, we need two instructions anyhow,
2684 so we may as well always use the latter form. */
2685 if (offset_expr
.X_add_number
!= 0
2686 || nopic_need_relax (offset_expr
.X_add_symbol
))
2691 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2692 mips_isa
< 3 ? "addiu" : "daddiu",
2693 "t,r,j", tempreg
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
2694 p
= frag_var (rs_machine_dependent
, 8, 0,
2695 RELAX_ENCODE (4, 8, 0, 4, 0,
2696 mips_warn_about_macros
),
2697 offset_expr
.X_add_symbol
, (long) 0,
2700 macro_build_lui (p
, &icnt
, &offset_expr
, tempreg
);
2703 macro_build (p
, &icnt
, &offset_expr
,
2704 mips_isa
< 3 ? "addiu" : "daddiu",
2705 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
2707 else if (mips_pic
== SVR4_PIC
)
2709 /* If this is a reference to an external symbol, and there
2710 is no constant, we want
2711 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
2712 For a local symbol, we want
2713 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
2715 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
2717 If we have a small constant, and this is a reference to
2718 an external symbol, we want
2719 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
2721 addiu $tempreg,$tempreg,<constant>
2722 For a local symbol, we want the same instruction
2723 sequence, but we output a BFD_RELOC_LO16 reloc on the
2726 If we have a large constant, and this is a reference to
2727 an external symbol, we want
2728 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
2729 lui $at,<hiconstant>
2730 addiu $at,$at,<loconstant>
2731 addu $tempreg,$tempreg,$at
2732 For a local symbol, we want the same instruction
2733 sequence, but we output a BFD_RELOC_LO16 reloc on the
2734 addiu instruction. */
2735 expr1
.X_add_number
= offset_expr
.X_add_number
;
2736 offset_expr
.X_add_number
= 0;
2738 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2740 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
2741 if (expr1
.X_add_number
== 0)
2749 /* We're going to put in an addu instruction using
2750 tempreg, so we may as well insert the nop right
2752 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
2756 p
= frag_var (rs_machine_dependent
, 8 - off
, 0,
2757 RELAX_ENCODE (0, 8 - off
, -4 - off
, 4 - off
, 0,
2759 ? mips_warn_about_macros
2761 offset_expr
.X_add_symbol
, (long) 0,
2765 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
2768 macro_build (p
, &icnt
, &expr1
,
2769 mips_isa
< 3 ? "addiu" : "daddiu",
2770 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
2771 /* FIXME: If breg == 0, and the next instruction uses
2772 $tempreg, then if this variant case is used an extra
2773 nop will be generated. */
2775 else if (expr1
.X_add_number
>= -0x8000
2776 && expr1
.X_add_number
< 0x8000)
2778 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
2780 macro_build ((char *) NULL
, &icnt
, &expr1
,
2781 mips_isa
< 3 ? "addiu" : "daddiu",
2782 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
2783 (void) frag_var (rs_machine_dependent
, 0, 0,
2784 RELAX_ENCODE (0, 0, -12, -4, 0, 0),
2785 offset_expr
.X_add_symbol
, (long) 0,
2792 /* If we are going to add in a base register, and the
2793 target register and the base register are the same,
2794 then we are using AT as a temporary register. Since
2795 we want to load the constant into AT, we add our
2796 current AT (from the global offset table) and the
2797 register into the register now, and pretend we were
2798 not using a base register. */
2803 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
2805 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
2806 mips_isa
< 3 ? "addu" : "daddu",
2807 "d,v,t", treg
, AT
, breg
);
2813 /* Set mips_optimize around the lui instruction to avoid
2814 inserting an unnecessary nop after the lw. */
2815 hold_mips_optimize
= mips_optimize
;
2817 macro_build_lui ((char *) NULL
, &icnt
, &expr1
, AT
);
2818 mips_optimize
= hold_mips_optimize
;
2820 macro_build ((char *) NULL
, &icnt
, &expr1
,
2821 mips_isa
< 3 ? "addiu" : "daddiu",
2822 "t,r,j", AT
, AT
, (int) BFD_RELOC_LO16
);
2823 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
2824 mips_isa
< 3 ? "addu" : "daddu",
2825 "d,v,t", tempreg
, tempreg
, AT
);
2826 (void) frag_var (rs_machine_dependent
, 0, 0,
2827 RELAX_ENCODE (0, 0, -16 + off1
, -8, 0, 0),
2828 offset_expr
.X_add_symbol
, (long) 0,
2833 else if (mips_pic
== EMBEDDED_PIC
)
2836 addiu $tempreg,$gp,<sym> (BFD_RELOC_MIPS_GPREL)
2838 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2839 mips_isa
< 3 ? "addiu" : "daddiu",
2840 "t,r,j", tempreg
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
2846 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
2847 mips_isa
< 3 ? "addu" : "daddu",
2848 "d,v,t", treg
, tempreg
, breg
);
2856 /* The j instruction may not be used in PIC code, since it
2857 requires an absolute address. We convert it to a b
2859 if (mips_pic
== NO_PIC
)
2860 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "j", "a");
2862 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "b", "p");
2865 /* The jal instructions must be handled as macros because when
2866 generating PIC code they expand to multi-instruction
2867 sequences. Normally they are simple instructions. */
2872 if (mips_pic
== NO_PIC
2873 || mips_pic
== EMBEDDED_PIC
)
2874 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "jalr",
2876 else if (mips_pic
== SVR4_PIC
)
2878 if (sreg
!= PIC_CALL_REG
)
2879 as_warn ("MIPS PIC call to register other than $25");
2881 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "jalr",
2883 if (mips_cprestore_offset
< 0)
2884 as_warn ("No .cprestore pseudo-op used in PIC code");
2887 expr1
.X_add_number
= mips_cprestore_offset
;
2888 macro_build ((char *) NULL
, &icnt
, &expr1
,
2889 mips_isa
< 3 ? "lw" : "ld",
2890 "t,o(b)", GP
, (int) BFD_RELOC_LO16
, mips_frame_reg
);
2899 if (mips_pic
== NO_PIC
)
2900 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "jal", "a");
2901 else if (mips_pic
== SVR4_PIC
)
2903 /* If this is a reference to an external symbol, we want
2904 lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
2908 lw $gp,cprestore($sp)
2909 The cprestore value is set using the .cprestore
2910 pseudo-op. If the symbol is not external, we want
2911 lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
2913 addiu $25,$25,<sym> (BFD_RELOC_LO16)
2916 lw $gp,cprestore($sp)
2919 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2920 mips_isa
< 3 ? "lw" : "ld",
2921 "t,o(b)", PIC_CALL_REG
,
2922 (int) BFD_RELOC_MIPS_CALL16
, GP
);
2923 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
2924 p
= frag_var (rs_machine_dependent
, 4, 0,
2925 RELAX_ENCODE (0, 4, -8, 0, 0, 0),
2926 offset_expr
.X_add_symbol
, (long) 0, (char *) NULL
);
2927 macro_build (p
, &icnt
, &offset_expr
,
2928 mips_isa
< 3 ? "addiu" : "daddiu",
2929 "t,r,j", PIC_CALL_REG
, PIC_CALL_REG
,
2930 (int) BFD_RELOC_LO16
);
2931 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
2932 "jalr", "s", PIC_CALL_REG
);
2933 if (mips_cprestore_offset
< 0)
2934 as_warn ("No .cprestore pseudo-op used in PIC code");
2938 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
2940 expr1
.X_add_number
= mips_cprestore_offset
;
2941 macro_build ((char *) NULL
, &icnt
, &expr1
,
2942 mips_isa
< 3 ? "lw" : "ld",
2943 "t,o(b)", GP
, (int) BFD_RELOC_LO16
,
2947 else if (mips_pic
== EMBEDDED_PIC
)
2949 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "bal", "p");
2950 /* The linker may expand the call to a longer sequence which
2951 uses $at, so we must break rather than return. */
3027 if (breg
== treg
|| coproc
|| lr
)
3096 if (mask
== M_LWC1_AB
3097 || mask
== M_SWC1_AB
3098 || mask
== M_LDC1_AB
3099 || mask
== M_SDC1_AB
3108 if (offset_expr
.X_op
!= O_constant
3109 && offset_expr
.X_op
!= O_symbol
)
3111 as_bad ("expression too complex");
3112 offset_expr
.X_op
= O_constant
;
3115 /* A constant expression in PIC code can be handled just as it
3116 is in non PIC code. */
3117 if (mips_pic
== NO_PIC
3118 || offset_expr
.X_op
== O_constant
)
3120 /* If this is a reference to a GP relative symbol, and there
3121 is no base register, we want
3122 <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL)
3123 Otherwise, if there is no base register, we want
3124 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
3125 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
3126 If we have a constant, we need two instructions anyhow,
3127 so we always use the latter form.
3129 If we have a base register, and this is a reference to a
3130 GP relative symbol, we want
3131 addu $tempreg,$breg,$gp
3132 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GPREL)
3134 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
3135 addu $tempreg,$tempreg,$breg
3136 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
3137 With a constant we always use the latter case. */
3140 if (offset_expr
.X_add_number
!= 0
3141 || nopic_need_relax (offset_expr
.X_add_symbol
))
3146 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
3147 treg
, (int) BFD_RELOC_MIPS_GPREL
, GP
);
3148 p
= frag_var (rs_machine_dependent
, 8, 0,
3149 RELAX_ENCODE (4, 8, 0, 4, 0,
3150 (mips_warn_about_macros
3151 || (used_at
&& mips_noat
))),
3152 offset_expr
.X_add_symbol
, (long) 0,
3156 macro_build_lui (p
, &icnt
, &offset_expr
, tempreg
);
3159 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
, treg
,
3160 (int) BFD_RELOC_LO16
, tempreg
);
3164 if (offset_expr
.X_add_number
!= 0
3165 || nopic_need_relax (offset_expr
.X_add_symbol
))
3170 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3171 mips_isa
< 3 ? "addu" : "daddu",
3172 "d,v,t", tempreg
, breg
, GP
);
3173 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
3174 treg
, (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
3175 p
= frag_var (rs_machine_dependent
, 12, 0,
3176 RELAX_ENCODE (8, 12, 0, 8, 0, 0),
3177 offset_expr
.X_add_symbol
, (long) 0,
3180 macro_build_lui (p
, &icnt
, &offset_expr
, tempreg
);
3183 macro_build (p
, &icnt
, (expressionS
*) NULL
,
3184 mips_isa
< 3 ? "addu" : "daddu",
3185 "d,v,t", tempreg
, tempreg
, breg
);
3188 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
, treg
,
3189 (int) BFD_RELOC_LO16
, tempreg
);
3192 else if (mips_pic
== SVR4_PIC
)
3194 /* If this is a reference to an external symbol, we want
3195 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3197 <op> $treg,0($tempreg)
3199 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3201 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
3202 <op> $treg,0($tempreg)
3203 If there is a base register, we add it to $tempreg before
3204 the <op>. If there is a constant, we stick it in the
3205 <op> instruction. We don't handle constants larger than
3206 16 bits, because we have no way to load the upper 16 bits
3207 (actually, we could handle them for the subset of cases
3208 in which we are not using $at). */
3209 assert (offset_expr
.X_op
== O_symbol
);
3210 expr1
.X_add_number
= offset_expr
.X_add_number
;
3211 offset_expr
.X_add_number
= 0;
3212 if (expr1
.X_add_number
< -0x8000
3213 || expr1
.X_add_number
>= 0x8000)
3214 as_bad ("PIC code offset overflow (max 16 signed bits)");
3216 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3217 mips_isa
< 3 ? "lw" : "ld",
3218 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
3219 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
3220 p
= frag_var (rs_machine_dependent
, 4, 0,
3221 RELAX_ENCODE (0, 4, -8, 0, 0, 0),
3222 offset_expr
.X_add_symbol
, (long) 0,
3224 macro_build (p
, &icnt
, &offset_expr
,
3225 mips_isa
< 3 ? "addiu" : "daddiu",
3226 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
3228 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3229 mips_isa
< 3 ? "addu" : "daddu",
3230 "d,v,t", tempreg
, tempreg
, breg
);
3231 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
, treg
,
3232 (int) BFD_RELOC_LO16
, tempreg
);
3234 else if (mips_pic
== EMBEDDED_PIC
)
3236 /* If there is no base register, we want
3237 <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL)
3238 If there is a base register, we want
3239 addu $tempreg,$breg,$gp
3240 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GPREL)
3242 assert (offset_expr
.X_op
== O_symbol
);
3245 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
3246 treg
, (int) BFD_RELOC_MIPS_GPREL
, GP
);
3251 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3252 mips_isa
< 3 ? "addu" : "daddu",
3253 "d,v,t", tempreg
, breg
, GP
);
3254 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
3255 treg
, (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
3268 load_register (&icnt
, treg
, &imm_expr
, 0);
3272 load_register (&icnt
, treg
, &imm_expr
, 1);
3276 if (imm_expr
.X_op
== O_constant
)
3278 load_register (&icnt
, AT
, &imm_expr
, 0);
3279 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3280 "mtc1", "t,G", AT
, treg
);
3285 assert (offset_expr
.X_op
== O_symbol
3286 && strcmp (segment_name (S_GET_SEGMENT
3287 (offset_expr
.X_add_symbol
)),
3289 && offset_expr
.X_add_number
== 0);
3290 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lwc1", "T,o(b)",
3291 treg
, (int) BFD_RELOC_MIPS_LITERAL
, GP
);
3296 /* We know that sym is in the .rdata section. First we get the
3297 upper 16 bits of the address. */
3298 if (mips_pic
== NO_PIC
)
3300 /* FIXME: This won't work for a 64 bit address. */
3301 macro_build_lui ((char *) NULL
, &icnt
, &offset_expr
, AT
);
3303 else if (mips_pic
== SVR4_PIC
)
3305 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3306 mips_isa
< 3 ? "lw" : "ld",
3307 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
3309 else if (mips_pic
== EMBEDDED_PIC
)
3311 /* For embedded PIC we pick up the entire address off $gp in
3312 a single instruction. */
3313 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3314 mips_isa
< 3 ? "addiu" : "daddiu",
3315 "t,r,j", AT
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
3316 offset_expr
.X_op
= O_constant
;
3317 offset_expr
.X_add_number
= 0;
3322 /* Now we load the register(s). */
3324 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "ld", "t,o(b)",
3325 treg
, (int) BFD_RELOC_LO16
, AT
);
3328 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lw", "t,o(b)",
3329 treg
, (int) BFD_RELOC_LO16
, AT
);
3332 /* FIXME: How in the world do we deal with the possible
3334 offset_expr
.X_add_number
+= 4;
3335 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lw", "t,o(b)",
3336 treg
+ 1, (int) BFD_RELOC_LO16
, AT
);
3340 /* To avoid confusion in tc_gen_reloc, we must ensure that this
3341 does not become a variant frag. */
3342 frag_wane (frag_now
);
3348 assert (offset_expr
.X_op
== O_symbol
3349 && offset_expr
.X_add_number
== 0);
3350 s
= segment_name (S_GET_SEGMENT (offset_expr
.X_add_symbol
));
3351 if (strcmp (s
, ".lit8") == 0)
3355 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "ldc1",
3356 "T,o(b)", treg
, (int) BFD_RELOC_MIPS_LITERAL
, GP
);
3360 r
= BFD_RELOC_MIPS_LITERAL
;
3365 assert (strcmp (s
, RDATA_SECTION_NAME
) == 0);
3366 if (mips_pic
== SVR4_PIC
)
3367 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3368 mips_isa
< 3 ? "lw" : "ld",
3369 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
3372 /* FIXME: This won't work for a 64 bit address. */
3373 macro_build_lui ((char *) NULL
, &icnt
, &offset_expr
, AT
);
3378 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "ldc1",
3379 "T,o(b)", treg
, (int) BFD_RELOC_LO16
, AT
);
3381 /* To avoid confusion in tc_gen_reloc, we must ensure
3382 that this does not become a variant frag. */
3383 frag_wane (frag_now
);
3394 /* Even on a big endian machine $fn comes before $fn+1. We have
3395 to adjust when loading from memory. */
3398 assert (mips_isa
< 2);
3399 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lwc1", "T,o(b)",
3400 byte_order
== LITTLE_ENDIAN
? treg
: treg
+ 1,
3402 /* FIXME: A possible overflow which I don't know how to deal
3404 offset_expr
.X_add_number
+= 4;
3405 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lwc1", "T,o(b)",
3406 byte_order
== LITTLE_ENDIAN
? treg
+ 1 : treg
,
3409 /* To avoid confusion in tc_gen_reloc, we must ensure that this
3410 does not become a variant frag. */
3411 frag_wane (frag_now
);
3420 * The MIPS assembler seems to check for X_add_number not
3421 * being double aligned and generating:
3424 * addiu at,at,%lo(foo+1)
3427 * But, the resulting address is the same after relocation so why
3428 * generate the extra instruction?
3475 if (offset_expr
.X_op
!= O_symbol
3476 && offset_expr
.X_op
!= O_constant
)
3478 as_bad ("expression too complex");
3479 offset_expr
.X_op
= O_constant
;
3482 /* Even on a big endian machine $fn comes before $fn+1. We have
3483 to adjust when loading from memory. We set coproc if we must
3484 load $fn+1 first. */
3485 if (byte_order
== LITTLE_ENDIAN
)
3488 if (mips_pic
== NO_PIC
3489 || offset_expr
.X_op
== O_constant
)
3491 /* If this is a reference to a GP relative symbol, we want
3492 <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL)
3493 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_MIPS_GPREL)
3494 If we have a base register, we use this
3496 <op> $treg,<sym>($at) (BFD_RELOC_MIPS_GPREL)
3497 <op> $treg+1,<sym>+4($at) (BFD_RELOC_MIPS_GPREL)
3498 If this is not a GP relative symbol, we want
3499 lui $at,<sym> (BFD_RELOC_HI16_S)
3500 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
3501 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
3502 If there is a base register, we add it to $at after the
3503 lui instruction. If there is a constant, we always use
3505 if (offset_expr
.X_add_number
!= 0
3506 || nopic_need_relax (offset_expr
.X_add_symbol
))
3525 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3526 mips_isa
< 3 ? "addu" : "daddu",
3527 "d,v,t", AT
, breg
, GP
);
3533 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
3534 coproc
? treg
+ 1 : treg
,
3535 (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
3536 offset_expr
.X_add_number
+= 4;
3538 /* Set mips_optimize to 2 to avoid inserting an
3540 hold_mips_optimize
= mips_optimize
;
3542 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
3543 coproc
? treg
: treg
+ 1,
3544 (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
3545 mips_optimize
= hold_mips_optimize
;
3547 p
= frag_var (rs_machine_dependent
, 12 + off
, 0,
3548 RELAX_ENCODE (8 + off
, 12 + off
, 0, 4 + off
, 1,
3549 used_at
&& mips_noat
),
3550 offset_expr
.X_add_symbol
, (long) 0,
3553 /* We just generated two relocs. When tc_gen_reloc
3554 handles this case, it will skip the first reloc and
3555 handle the second. The second reloc already has an
3556 extra addend of 4, which we added above. We must
3557 subtract it out, and then subtract another 4 to make
3558 the first reloc come out right. The second reloc
3559 will come out right because we are going to add 4 to
3560 offset_expr when we build its instruction below. */
3561 offset_expr
.X_add_number
-= 8;
3562 offset_expr
.X_op
= O_constant
;
3564 macro_build_lui (p
, &icnt
, &offset_expr
, AT
);
3569 macro_build (p
, &icnt
, (expressionS
*) NULL
,
3570 mips_isa
< 3 ? "addu" : "daddu",
3571 "d,v,t", AT
, breg
, AT
);
3575 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
,
3576 coproc
? treg
+ 1 : treg
,
3577 (int) BFD_RELOC_LO16
, AT
);
3580 /* FIXME: How do we handle overflow here? */
3581 offset_expr
.X_add_number
+= 4;
3582 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
,
3583 coproc
? treg
: treg
+ 1,
3584 (int) BFD_RELOC_LO16
, AT
);
3586 else if (mips_pic
== SVR4_PIC
)
3590 /* If this is a reference to an external symbol, we want
3591 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3596 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3598 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
3599 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
3600 If there is a base register we add it to $at before the
3601 lwc1 instructions. If there is a constant we include it
3602 in the lwc1 instructions. */
3604 expr1
.X_add_number
= offset_expr
.X_add_number
;
3605 offset_expr
.X_add_number
= 0;
3606 if (expr1
.X_add_number
< -0x8000
3607 || expr1
.X_add_number
>= 0x8000 - 4)
3608 as_bad ("PIC code offset overflow (max 16 signed bits)");
3613 frag_grow (24 + off
);
3614 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3615 mips_isa
< 3 ? "lw" : "ld",
3616 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
3617 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
3619 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3620 mips_isa
< 3 ? "addu" : "daddu",
3621 "d,v,t", AT
, breg
, AT
);
3622 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
3623 coproc
? treg
+ 1 : treg
,
3624 (int) BFD_RELOC_LO16
, AT
);
3625 expr1
.X_add_number
+= 4;
3627 /* Set mips_optimize to 2 to avoid inserting an undesired
3629 hold_mips_optimize
= mips_optimize
;
3631 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
3632 coproc
? treg
: treg
+ 1,
3633 (int) BFD_RELOC_LO16
, AT
);
3634 mips_optimize
= hold_mips_optimize
;
3636 (void) frag_var (rs_machine_dependent
, 0, 0,
3637 RELAX_ENCODE (0, 0, -16 - off
, -8, 1, 0),
3638 offset_expr
.X_add_symbol
, (long) 0,
3641 else if (mips_pic
== EMBEDDED_PIC
)
3643 /* If there is no base register, we use
3644 <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL)
3645 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_MIPS_GPREL)
3646 If we have a base register, we use
3648 <op> $treg,<sym>($at) (BFD_RELOC_MIPS_GPREL)
3649 <op> $treg+1,<sym>+4($at) (BFD_RELOC_MIPS_GPREL)
3658 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3659 mips_isa
< 3 ? "addu" : "daddu",
3660 "d,v,t", AT
, breg
, GP
);
3665 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
3666 coproc
? treg
+ 1 : treg
,
3667 (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
3668 offset_expr
.X_add_number
+= 4;
3669 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
3670 coproc
? treg
: treg
+ 1,
3671 (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
3687 assert (mips_isa
< 3);
3688 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
3689 (int) BFD_RELOC_LO16
, breg
);
3690 offset_expr
.X_add_number
+= 4;
3691 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
+ 1,
3692 (int) BFD_RELOC_LO16
, breg
);
3694 #ifdef LOSING_COMPILER
3700 as_warn ("Macro used $at after \".set noat\"");
3705 struct mips_cl_insn
*ip
;
3707 register int treg
, sreg
, dreg
, breg
;
3722 bfd_reloc_code_real_type r
;
3725 treg
= (ip
->insn_opcode
>> 16) & 0x1f;
3726 dreg
= (ip
->insn_opcode
>> 11) & 0x1f;
3727 sreg
= breg
= (ip
->insn_opcode
>> 21) & 0x1f;
3728 mask
= ip
->insn_mo
->mask
;
3730 expr1
.X_op
= O_constant
;
3731 expr1
.X_op_symbol
= NULL
;
3732 expr1
.X_add_symbol
= NULL
;
3733 expr1
.X_add_number
= 1;
3737 #endif /* LOSING_COMPILER */
3742 macro_build ((char *) NULL
, &icnt
, NULL
,
3743 dbl
? "dmultu" : "multu",
3745 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
3751 /* The MIPS assembler some times generates shifts and adds. I'm
3752 not trying to be that fancy. GCC should do this for us
3754 load_register (&icnt
, AT
, &imm_expr
, dbl
);
3755 macro_build ((char *) NULL
, &icnt
, NULL
,
3756 dbl
? "dmult" : "mult",
3758 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
3764 mips_emit_delays ();
3766 mips_any_noreorder
= 1;
3767 macro_build ((char *) NULL
, &icnt
, NULL
,
3768 dbl
? "dmult" : "mult",
3770 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
3771 macro_build ((char *) NULL
, &icnt
, NULL
,
3772 dbl
? "dsra32" : "sra",
3773 "d,w,<", dreg
, dreg
, 31);
3774 macro_build ((char *) NULL
, &icnt
, NULL
, "mfhi", "d", AT
);
3776 macro_build ((char *) NULL
, &icnt
, NULL
, "tne", "s,t", dreg
, AT
);
3779 expr1
.X_add_number
= 8;
3780 macro_build ((char *) NULL
, &icnt
, &expr1
, "beq", "s,t,p", dreg
, AT
);
3781 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
3782 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 6);
3785 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
3791 mips_emit_delays ();
3793 mips_any_noreorder
= 1;
3794 macro_build ((char *) NULL
, &icnt
, NULL
,
3795 dbl
? "dmultu" : "multu",
3797 macro_build ((char *) NULL
, &icnt
, NULL
, "mfhi", "d", AT
);
3798 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
3800 macro_build ((char *) NULL
, &icnt
, NULL
, "tne", "s,t", AT
, 0);
3803 expr1
.X_add_number
= 8;
3804 macro_build ((char *) NULL
, &icnt
, &expr1
, "beq", "s,t,p", AT
, 0);
3805 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
3806 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 6);
3812 macro_build ((char *) NULL
, &icnt
, NULL
, "subu", "d,v,t", AT
, 0, treg
);
3813 macro_build ((char *) NULL
, &icnt
, NULL
, "srlv", "d,t,s", AT
, sreg
, AT
);
3814 macro_build ((char *) NULL
, &icnt
, NULL
, "sllv", "d,t,s", dreg
, sreg
,
3816 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
3820 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", AT
, sreg
,
3821 imm_expr
.X_add_number
& 0x1f);
3822 macro_build ((char *) NULL
, &icnt
, NULL
, "srl", "d,w,<", dreg
, sreg
,
3823 (0 - imm_expr
.X_add_number
) & 0x1f);
3824 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
3828 macro_build ((char *) NULL
, &icnt
, NULL
, "subu", "d,v,t", AT
, 0, treg
);
3829 macro_build ((char *) NULL
, &icnt
, NULL
, "sllv", "d,t,s", AT
, sreg
, AT
);
3830 macro_build ((char *) NULL
, &icnt
, NULL
, "srlv", "d,t,s", dreg
, sreg
,
3832 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
3836 macro_build ((char *) NULL
, &icnt
, NULL
, "srl", "d,w,<", AT
, sreg
,
3837 imm_expr
.X_add_number
& 0x1f);
3838 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", dreg
, sreg
,
3839 (0 - imm_expr
.X_add_number
) & 0x1f);
3840 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
3844 assert (mips_isa
< 2);
3845 /* Even on a big endian machine $fn comes before $fn+1. We have
3846 to adjust when storing to memory. */
3847 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "swc1", "T,o(b)",
3848 byte_order
== LITTLE_ENDIAN
? treg
: treg
+ 1,
3849 (int) BFD_RELOC_LO16
, breg
);
3850 offset_expr
.X_add_number
+= 4;
3851 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "swc1", "T,o(b)",
3852 byte_order
== LITTLE_ENDIAN
? treg
+ 1 : treg
,
3853 (int) BFD_RELOC_LO16
, breg
);
3858 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
3859 treg
, (int) BFD_RELOC_LO16
);
3861 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
3862 sreg
, (int) BFD_RELOC_LO16
);
3865 macro_build ((char *) NULL
, &icnt
, NULL
, "xor", "d,v,t", dreg
,
3867 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
3868 dreg
, (int) BFD_RELOC_LO16
);
3873 if (imm_expr
.X_add_number
== 0)
3875 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
3876 sreg
, (int) BFD_RELOC_LO16
);
3881 as_warn ("Instruction %s: result is always false",
3883 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
, 0);
3886 if (imm_expr
.X_add_number
>= 0 && imm_expr
.X_add_number
< 0x10000)
3888 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "xori", "t,r,i", dreg
,
3889 sreg
, (int) BFD_RELOC_LO16
);
3892 else if (imm_expr
.X_add_number
> -0x8000 && imm_expr
.X_add_number
< 0)
3894 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
3895 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
3896 mips_isa
< 3 ? "addiu" : "daddiu",
3897 "t,r,j", dreg
, sreg
,
3898 (int) BFD_RELOC_LO16
);
3903 load_register (&icnt
, AT
, &imm_expr
, 0);
3904 macro_build ((char *) NULL
, &icnt
, NULL
, "xor", "d,v,t", dreg
,
3908 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
, dreg
,
3909 (int) BFD_RELOC_LO16
);
3914 case M_SGE
: /* sreg >= treg <==> not (sreg < treg) */
3920 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, sreg
, treg
);
3921 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
3922 (int) BFD_RELOC_LO16
);
3925 case M_SGE_I
: /* sreg >= I <==> not (sreg < I) */
3927 if (imm_expr
.X_add_number
>= -0x8000 && imm_expr
.X_add_number
< 0x8000)
3929 macro_build ((char *) NULL
, &icnt
, &expr1
,
3930 mask
== M_SGE_I
? "slti" : "sltiu",
3931 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
3936 load_register (&icnt
, AT
, &imm_expr
, 0);
3937 macro_build ((char *) NULL
, &icnt
, NULL
,
3938 mask
== M_SGE_I
? "slt" : "sltu",
3939 "d,v,t", dreg
, sreg
, AT
);
3942 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
3943 (int) BFD_RELOC_LO16
);
3948 case M_SGT
: /* sreg > treg <==> treg < sreg */
3954 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, treg
, sreg
);
3957 case M_SGT_I
: /* sreg > I <==> I < sreg */
3963 load_register (&icnt
, AT
, &imm_expr
, 0);
3964 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, AT
, sreg
);
3967 case M_SLE
: /* sreg <= treg <==> treg >= sreg <==> not (treg < sreg) */
3973 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, treg
, sreg
);
3974 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
3975 (int) BFD_RELOC_LO16
);
3978 case M_SLE_I
: /* sreg <= I <==> I >= sreg <==> not (I < sreg) */
3984 load_register (&icnt
, AT
, &imm_expr
, 0);
3985 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, AT
, sreg
);
3986 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
3987 (int) BFD_RELOC_LO16
);
3991 if (imm_expr
.X_add_number
>= -0x8000 && imm_expr
.X_add_number
< 0x8000)
3993 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "slti", "t,r,j",
3994 dreg
, sreg
, (int) BFD_RELOC_LO16
);
3997 load_register (&icnt
, AT
, &imm_expr
, 0);
3998 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", dreg
, sreg
, AT
);
4002 if (imm_expr
.X_add_number
>= -0x8000 && imm_expr
.X_add_number
< 0x8000)
4004 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "sltiu", "t,r,j",
4005 dreg
, sreg
, (int) BFD_RELOC_LO16
);
4008 load_register (&icnt
, AT
, &imm_expr
, 0);
4009 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, sreg
,
4015 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0,
4018 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0,
4022 macro_build ((char *) NULL
, &icnt
, NULL
, "xor", "d,v,t", dreg
,
4024 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0,
4030 if (imm_expr
.X_add_number
== 0)
4032 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0,
4038 as_warn ("Instruction %s: result is always true",
4040 macro_build ((char *) NULL
, &icnt
, &expr1
,
4041 mips_isa
< 3 ? "addiu" : "daddiu",
4042 "t,r,j", dreg
, 0, (int) BFD_RELOC_LO16
);
4045 if (imm_expr
.X_add_number
>= 0 && imm_expr
.X_add_number
< 0x10000)
4047 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "xori", "t,r,i",
4048 dreg
, sreg
, (int) BFD_RELOC_LO16
);
4051 else if (imm_expr
.X_add_number
> -0x8000 && imm_expr
.X_add_number
< 0)
4053 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
4054 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
4055 mips_isa
< 3 ? "addiu" : "daddiu",
4056 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
4061 load_register (&icnt
, AT
, &imm_expr
, 0);
4062 macro_build ((char *) NULL
, &icnt
, NULL
, "xor", "d,v,t", dreg
,
4066 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0, dreg
);
4074 if (imm_expr
.X_add_number
> -0x8000 && imm_expr
.X_add_number
<= 0x8000)
4076 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
4077 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
4078 dbl
? "daddi" : "addi",
4079 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
4082 load_register (&icnt
, AT
, &imm_expr
, dbl
);
4083 macro_build ((char *) NULL
, &icnt
, NULL
,
4084 dbl
? "dsub" : "sub",
4085 "d,v,t", dreg
, sreg
, AT
);
4091 if (imm_expr
.X_add_number
> -0x8000 && imm_expr
.X_add_number
<= 0x8000)
4093 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
4094 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
4095 dbl
? "daddiu" : "addiu",
4096 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
4099 load_register (&icnt
, AT
, &imm_expr
, dbl
);
4100 macro_build ((char *) NULL
, &icnt
, NULL
,
4101 dbl
? "dsubu" : "subu",
4102 "d,v,t", dreg
, sreg
, AT
);
4123 load_register (&icnt
, AT
, &imm_expr
, 0);
4124 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "s,t", sreg
, AT
);
4129 assert (mips_isa
< 2);
4130 sreg
= (ip
->insn_opcode
>> 11) & 0x1f; /* floating reg */
4131 dreg
= (ip
->insn_opcode
>> 06) & 0x1f; /* floating reg */
4134 * Is the double cfc1 instruction a bug in the mips assembler;
4135 * or is there a reason for it?
4137 mips_emit_delays ();
4139 mips_any_noreorder
= 1;
4140 macro_build ((char *) NULL
, &icnt
, NULL
, "cfc1", "t,G", treg
, 31);
4141 macro_build ((char *) NULL
, &icnt
, NULL
, "cfc1", "t,G", treg
, 31);
4142 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "");
4143 expr1
.X_add_number
= 3;
4144 macro_build ((char *) NULL
, &icnt
, &expr1
, "ori", "t,r,i", AT
, treg
,
4145 (int) BFD_RELOC_LO16
);
4146 expr1
.X_add_number
= 2;
4147 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", AT
, AT
,
4148 (int) BFD_RELOC_LO16
);
4149 macro_build ((char *) NULL
, &icnt
, NULL
, "ctc1", "t,G", AT
, 31);
4150 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "");
4151 macro_build ((char *) NULL
, &icnt
, NULL
,
4152 mask
== M_TRUNCWD
? "cvt.w.d" : "cvt.w.s", "D,S", dreg
, sreg
);
4153 macro_build ((char *) NULL
, &icnt
, NULL
, "ctc1", "t,G", treg
, 31);
4154 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "");
4164 if (offset_expr
.X_add_number
>= 0x7fff)
4165 as_bad ("operand overflow");
4166 /* avoid load delay */
4167 if (byte_order
== LITTLE_ENDIAN
)
4168 offset_expr
.X_add_number
+= 1;
4169 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
4170 (int) BFD_RELOC_LO16
, breg
);
4171 if (byte_order
== LITTLE_ENDIAN
)
4172 offset_expr
.X_add_number
-= 1;
4174 offset_expr
.X_add_number
+= 1;
4175 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lbu", "t,o(b)", AT
,
4176 (int) BFD_RELOC_LO16
, breg
);
4177 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", treg
, treg
, 8);
4178 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", treg
, treg
, AT
);
4191 if (offset_expr
.X_add_number
>= 0x8000 - off
)
4192 as_bad ("operand overflow");
4193 if (byte_order
== LITTLE_ENDIAN
)
4194 offset_expr
.X_add_number
+= off
;
4195 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
4196 (int) BFD_RELOC_LO16
, breg
);
4197 if (byte_order
== LITTLE_ENDIAN
)
4198 offset_expr
.X_add_number
-= off
;
4200 offset_expr
.X_add_number
+= off
;
4201 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s2
, "t,o(b)", treg
,
4202 (int) BFD_RELOC_LO16
, breg
);
4215 load_address (&icnt
, AT
, &offset_expr
);
4217 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4218 mips_isa
< 3 ? "addu" : "daddu",
4219 "d,v,t", AT
, AT
, breg
);
4220 if (byte_order
== LITTLE_ENDIAN
)
4221 expr1
.X_add_number
= off
;
4223 expr1
.X_add_number
= 0;
4224 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, "t,o(b)", treg
,
4225 (int) BFD_RELOC_LO16
, AT
);
4226 if (byte_order
== LITTLE_ENDIAN
)
4227 expr1
.X_add_number
= 0;
4229 expr1
.X_add_number
= off
;
4230 macro_build ((char *) NULL
, &icnt
, &expr1
, s2
, "t,o(b)", treg
,
4231 (int) BFD_RELOC_LO16
, AT
);
4236 load_address (&icnt
, AT
, &offset_expr
);
4238 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4239 mips_isa
< 3 ? "addu" : "daddu",
4240 "d,v,t", AT
, AT
, breg
);
4241 if (byte_order
== BIG_ENDIAN
)
4242 expr1
.X_add_number
= 0;
4243 macro_build ((char *) NULL
, &icnt
, &expr1
,
4244 mask
== M_ULH_A
? "lb" : "lbu", "t,o(b)", treg
,
4245 (int) BFD_RELOC_LO16
, AT
);
4246 if (byte_order
== BIG_ENDIAN
)
4247 expr1
.X_add_number
= 1;
4249 expr1
.X_add_number
= 0;
4250 macro_build ((char *) NULL
, &icnt
, &expr1
, "lbu", "t,o(b)", AT
,
4251 (int) BFD_RELOC_LO16
, AT
);
4252 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", treg
,
4254 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", treg
,
4259 if (offset_expr
.X_add_number
>= 0x7fff)
4260 as_bad ("operand overflow");
4261 if (byte_order
== BIG_ENDIAN
)
4262 offset_expr
.X_add_number
+= 1;
4263 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "sb", "t,o(b)", treg
,
4264 (int) BFD_RELOC_LO16
, breg
);
4265 macro_build ((char *) NULL
, &icnt
, NULL
, "srl", "d,w,<", AT
, treg
, 8);
4266 if (byte_order
== BIG_ENDIAN
)
4267 offset_expr
.X_add_number
-= 1;
4269 offset_expr
.X_add_number
+= 1;
4270 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "sb", "t,o(b)", AT
,
4271 (int) BFD_RELOC_LO16
, breg
);
4284 if (offset_expr
.X_add_number
>= 0x8000 - off
)
4285 as_bad ("operand overflow");
4286 if (byte_order
== LITTLE_ENDIAN
)
4287 offset_expr
.X_add_number
+= off
;
4288 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
4289 (int) BFD_RELOC_LO16
, breg
);
4290 if (byte_order
== LITTLE_ENDIAN
)
4291 offset_expr
.X_add_number
-= off
;
4293 offset_expr
.X_add_number
+= off
;
4294 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s2
, "t,o(b)", treg
,
4295 (int) BFD_RELOC_LO16
, breg
);
4308 load_address (&icnt
, AT
, &offset_expr
);
4310 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4311 mips_isa
< 3 ? "addu" : "daddu",
4312 "d,v,t", AT
, AT
, breg
);
4313 if (byte_order
== LITTLE_ENDIAN
)
4314 expr1
.X_add_number
= off
;
4316 expr1
.X_add_number
= 0;
4317 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, "t,o(b)", treg
,
4318 (int) BFD_RELOC_LO16
, AT
);
4319 if (byte_order
== LITTLE_ENDIAN
)
4320 expr1
.X_add_number
= 0;
4322 expr1
.X_add_number
= off
;
4323 macro_build ((char *) NULL
, &icnt
, &expr1
, s2
, "t,o(b)", treg
,
4324 (int) BFD_RELOC_LO16
, AT
);
4328 load_address (&icnt
, AT
, &offset_expr
);
4330 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4331 mips_isa
< 3 ? "addu" : "daddu",
4332 "d,v,t", AT
, AT
, breg
);
4333 if (byte_order
== LITTLE_ENDIAN
)
4334 expr1
.X_add_number
= 0;
4335 macro_build ((char *) NULL
, &icnt
, &expr1
, "sb", "t,o(b)", treg
,
4336 (int) BFD_RELOC_LO16
, AT
);
4337 macro_build ((char *) NULL
, &icnt
, NULL
, "srl", "d,w,<", treg
,
4339 if (byte_order
== LITTLE_ENDIAN
)
4340 expr1
.X_add_number
= 1;
4342 expr1
.X_add_number
= 0;
4343 macro_build ((char *) NULL
, &icnt
, &expr1
, "sb", "t,o(b)", treg
,
4344 (int) BFD_RELOC_LO16
, AT
);
4345 if (byte_order
== LITTLE_ENDIAN
)
4346 expr1
.X_add_number
= 0;
4348 expr1
.X_add_number
= 1;
4349 macro_build ((char *) NULL
, &icnt
, &expr1
, "lbu", "t,o(b)", AT
,
4350 (int) BFD_RELOC_LO16
, AT
);
4351 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", treg
,
4353 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", treg
,
4358 as_bad ("Macro %s not implemented yet", ip
->insn_mo
->name
);
4362 as_warn ("Macro used $at after \".set noat\"");
4367 This routine assembles an instruction into its binary format. As a side
4368 effect it sets one of the global variables imm_reloc or offset_reloc to the
4369 type of relocation to do if one of the operands is an address expression.
4374 struct mips_cl_insn
*ip
;
4379 struct mips_opcode
*insn
;
4382 unsigned int lastregno
= 0;
4387 for (s
= str
; islower (*s
) || (*s
>= '0' && *s
<= '3') || *s
== '6' || *s
== '.'; ++s
)
4399 as_fatal ("Unknown opcode: `%s'", str
);
4401 if ((insn
= (struct mips_opcode
*) hash_find (op_hash
, str
)) == NULL
)
4403 as_warn ("`%s' not in hash table.", str
);
4404 insn_error
= "ERROR: Unrecognized opcode";
4412 assert (strcmp (insn
->name
, str
) == 0);
4414 if (insn
->pinfo
== INSN_MACRO
)
4415 insn_isa
= insn
->match
;
4416 else if ((insn
->pinfo
& INSN_ISA
) == INSN_ISA2
)
4418 else if ((insn
->pinfo
& INSN_ISA
) == INSN_ISA3
)
4420 else if ((insn
->pinfo
& INSN_ISA
) == INSN_ISA4
)
4425 if (insn_isa
> mips_isa
4426 || ((insn
->pinfo
& INSN_ISA
) == INSN_4650
4428 || ((insn
->pinfo
& INSN_ISA
) == INSN_4010
4430 || ((insn
->pinfo
& INSN_ISA
) == INSN_4100
4433 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
]
4434 && strcmp (insn
->name
, insn
[1].name
) == 0)
4439 as_warn ("Instruction not supported on this processor");
4443 ip
->insn_opcode
= insn
->match
;
4444 for (args
= insn
->args
;; ++args
)
4450 case '\0': /* end of args */
4463 ip
->insn_opcode
|= lastregno
<< 21;
4468 ip
->insn_opcode
|= lastregno
<< 16;
4472 ip
->insn_opcode
|= lastregno
<< 11;
4478 /* handle optional base register.
4479 Either the base register is omitted or
4480 we must have a left paren. */
4481 /* this is dependent on the next operand specifier
4482 is a 'b' for base register */
4483 assert (args
[1] == 'b');
4487 case ')': /* these must match exactly */
4492 case '<': /* must be at least one digit */
4494 * According to the manual, if the shift amount is greater
4495 * than 31 or less than 0 the the shift amount should be
4496 * mod 32. In reality the mips assembler issues an error.
4497 * We issue a warning and mask out all but the low 5 bits.
4499 my_getExpression (&imm_expr
, s
);
4500 check_absolute_expr (ip
, &imm_expr
);
4501 if ((unsigned long) imm_expr
.X_add_number
> 31)
4503 as_warn ("Improper shift amount (%ld)",
4504 (long) imm_expr
.X_add_number
);
4505 imm_expr
.X_add_number
= imm_expr
.X_add_number
& 0x1f;
4507 ip
->insn_opcode
|= imm_expr
.X_add_number
<< 6;
4508 imm_expr
.X_op
= O_absent
;
4512 case '>': /* shift amount minus 32 */
4513 my_getExpression (&imm_expr
, s
);
4514 check_absolute_expr (ip
, &imm_expr
);
4515 if ((unsigned long) imm_expr
.X_add_number
< 32
4516 || (unsigned long) imm_expr
.X_add_number
> 63)
4518 ip
->insn_opcode
|= (imm_expr
.X_add_number
- 32) << 6;
4519 imm_expr
.X_op
= O_absent
;
4523 case 'k': /* cache code */
4524 case 'h': /* prefx code */
4525 my_getExpression (&imm_expr
, s
);
4526 check_absolute_expr (ip
, &imm_expr
);
4527 if ((unsigned long) imm_expr
.X_add_number
> 31)
4529 as_warn ("Invalid value for `%s' (%lu)",
4531 (unsigned long) imm_expr
.X_add_number
);
4532 imm_expr
.X_add_number
&= 0x1f;
4535 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_CACHE
;
4537 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_PREFX
;
4538 imm_expr
.X_op
= O_absent
;
4542 case 'c': /* break code */
4543 my_getExpression (&imm_expr
, s
);
4544 check_absolute_expr (ip
, &imm_expr
);
4545 if ((unsigned) imm_expr
.X_add_number
> 1023)
4546 as_warn ("Illegal break code (%ld)",
4547 (long) imm_expr
.X_add_number
);
4548 ip
->insn_opcode
|= imm_expr
.X_add_number
<< 16;
4549 imm_expr
.X_op
= O_absent
;
4553 case 'B': /* syscall code */
4554 my_getExpression (&imm_expr
, s
);
4555 check_absolute_expr (ip
, &imm_expr
);
4556 if ((unsigned) imm_expr
.X_add_number
> 0xfffff)
4557 as_warn ("Illegal syscall code (%ld)",
4558 (long) imm_expr
.X_add_number
);
4559 ip
->insn_opcode
|= imm_expr
.X_add_number
<< 6;
4560 imm_expr
.X_op
= O_absent
;
4564 case 'C': /* Coprocessor code */
4565 my_getExpression (&imm_expr
, s
);
4566 check_absolute_expr (ip
, &imm_expr
);
4567 if ((unsigned long) imm_expr
.X_add_number
>= (1<<25))
4569 as_warn ("Coproccesor code > 25 bits (%ld)",
4570 (long) imm_expr
.X_add_number
);
4571 imm_expr
.X_add_number
&= ((1<<25) - 1);
4573 ip
->insn_opcode
|= imm_expr
.X_add_number
;
4574 imm_expr
.X_op
= O_absent
;
4578 case 'b': /* base register */
4579 case 'd': /* destination register */
4580 case 's': /* source register */
4581 case 't': /* target register */
4582 case 'r': /* both target and source */
4583 case 'v': /* both dest and source */
4584 case 'w': /* both dest and target */
4585 case 'E': /* coprocessor target register */
4586 case 'G': /* coprocessor destination register */
4587 case 'x': /* ignore register name */
4588 case 'z': /* must be zero register */
4602 while (isdigit (*s
));
4604 as_bad ("Invalid register number (%d)", regno
);
4606 else if (*args
== 'E' || *args
== 'G')
4610 if (s
[1] == 'f' && s
[2] == 'p')
4615 else if (s
[1] == 's' && s
[2] == 'p')
4620 else if (s
[1] == 'g' && s
[2] == 'p')
4625 else if (s
[1] == 'a' && s
[2] == 't')
4630 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '0')
4635 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '1')
4643 if (regno
== AT
&& ! mips_noat
)
4644 as_warn ("Used $at without \".set noat\"");
4650 if (c
== 'r' || c
== 'v' || c
== 'w')
4657 /* 'z' only matches $0. */
4658 if (c
== 'z' && regno
!= 0)
4666 ip
->insn_opcode
|= regno
<< 21;
4670 ip
->insn_opcode
|= regno
<< 11;
4675 ip
->insn_opcode
|= regno
<< 16;
4678 /* This case exists because on the r3000 trunc
4679 expands into a macro which requires a gp
4680 register. On the r6000 or r4000 it is
4681 assembled into a single instruction which
4682 ignores the register. Thus the insn version
4683 is MIPS_ISA2 and uses 'x', and the macro
4684 version is MIPS_ISA1 and uses 't'. */
4687 /* This case is for the div instruction, which
4688 acts differently if the destination argument
4689 is $0. This only matches $0, and is checked
4690 outside the switch. */
4701 ip
->insn_opcode
|= lastregno
<< 21;
4704 ip
->insn_opcode
|= lastregno
<< 16;
4709 case 'D': /* floating point destination register */
4710 case 'S': /* floating point source register */
4711 case 'T': /* floating point target register */
4712 case 'R': /* floating point source register */
4716 if (s
[0] == '$' && s
[1] == 'f' && isdigit (s
[2]))
4726 while (isdigit (*s
));
4729 as_bad ("Invalid float register number (%d)", regno
);
4731 if ((regno
& 1) != 0
4733 && ! (strcmp (str
, "mtc1") == 0 ||
4734 strcmp (str
, "mfc1") == 0 ||
4735 strcmp (str
, "lwc1") == 0 ||
4736 strcmp (str
, "swc1") == 0))
4737 as_warn ("Float register should be even, was %d",
4745 if (c
== 'V' || c
== 'W')
4755 ip
->insn_opcode
|= regno
<< 6;
4759 ip
->insn_opcode
|= regno
<< 11;
4763 ip
->insn_opcode
|= regno
<< 16;
4766 ip
->insn_opcode
|= regno
<< 21;
4775 ip
->insn_opcode
|= lastregno
<< 11;
4778 ip
->insn_opcode
|= lastregno
<< 16;
4784 my_getExpression (&imm_expr
, s
);
4785 if (imm_expr
.X_op
!= O_big
)
4786 check_absolute_expr (ip
, &imm_expr
);
4791 my_getExpression (&offset_expr
, s
);
4792 imm_reloc
= BFD_RELOC_32
;
4804 unsigned char temp
[8];
4806 unsigned int length
;
4811 /* These only appear as the last operand in an
4812 instruction, and every instruction that accepts
4813 them in any variant accepts them in all variants.
4814 This means we don't have to worry about backing out
4815 any changes if the instruction does not match.
4817 The difference between them is the size of the
4818 floating point constant and where it goes. For 'F'
4819 and 'L' the constant is 64 bits; for 'f' and 'l' it
4820 is 32 bits. Where the constant is placed is based
4821 on how the MIPS assembler does things:
4824 f -- immediate value
4827 The .lit4 and .lit8 sections are only used if
4828 permitted by the -G argument.
4830 When generating embedded PIC code, we use the
4831 .lit8 section but not the .lit4 section (we can do
4832 .lit4 inline easily; we need to put .lit8
4833 somewhere in the data segment, and using .lit8
4834 permits the linker to eventually combine identical
4837 f64
= *args
== 'F' || *args
== 'L';
4839 save_in
= input_line_pointer
;
4840 input_line_pointer
= s
;
4841 err
= md_atof (f64
? 'd' : 'f', (char *) temp
, &len
);
4843 s
= input_line_pointer
;
4844 input_line_pointer
= save_in
;
4845 if (err
!= NULL
&& *err
!= '\0')
4847 as_bad ("Bad floating point constant: %s", err
);
4848 memset (temp
, '\0', sizeof temp
);
4849 length
= f64
? 8 : 4;
4852 assert (length
== (f64
? 8 : 4));
4856 && (! USE_GLOBAL_POINTER_OPT
4857 || mips_pic
== EMBEDDED_PIC
4858 || g_switch_value
< 4)
4861 imm_expr
.X_op
= O_constant
;
4862 if (byte_order
== LITTLE_ENDIAN
)
4863 imm_expr
.X_add_number
=
4864 (((((((int) temp
[3] << 8)
4869 imm_expr
.X_add_number
=
4870 (((((((int) temp
[0] << 8)
4877 const char *newname
;
4880 /* Switch to the right section. */
4882 subseg
= now_subseg
;
4885 default: /* unused default case avoids warnings. */
4887 newname
= RDATA_SECTION_NAME
;
4888 if (USE_GLOBAL_POINTER_OPT
&& g_switch_value
>= 8)
4892 newname
= RDATA_SECTION_NAME
;
4895 assert (!USE_GLOBAL_POINTER_OPT
4896 || g_switch_value
>= 4);
4900 new_seg
= subseg_new (newname
, (subsegT
) 0);
4901 frag_align (*args
== 'l' ? 2 : 3, 0);
4902 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
4903 record_alignment (new_seg
, 4);
4905 record_alignment (new_seg
, *args
== 'l' ? 2 : 3);
4907 as_bad ("Can't use floating point insn in this section");
4909 /* Set the argument to the current address in the
4911 offset_expr
.X_op
= O_symbol
;
4912 offset_expr
.X_add_symbol
=
4913 symbol_new ("L0\001", now_seg
,
4914 (valueT
) frag_now_fix (), frag_now
);
4915 offset_expr
.X_add_number
= 0;
4917 /* Put the floating point number into the section. */
4918 p
= frag_more ((int) length
);
4919 memcpy (p
, temp
, length
);
4921 /* Switch back to the original section. */
4922 subseg_set (seg
, subseg
);
4927 case 'i': /* 16 bit unsigned immediate */
4928 case 'j': /* 16 bit signed immediate */
4929 imm_reloc
= BFD_RELOC_LO16
;
4930 c
= my_getSmallExpression (&imm_expr
, s
);
4935 if (imm_expr
.X_op
== O_constant
)
4936 imm_expr
.X_add_number
=
4937 (imm_expr
.X_add_number
>> 16) & 0xffff;
4939 imm_reloc
= BFD_RELOC_HI16_S
;
4941 imm_reloc
= BFD_RELOC_HI16
;
4944 else if (imm_expr
.X_op
!= O_big
)
4945 check_absolute_expr (ip
, &imm_expr
);
4948 if (imm_expr
.X_op
== O_big
4949 || imm_expr
.X_add_number
< 0
4950 || imm_expr
.X_add_number
>= 0x10000)
4952 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
4953 !strcmp (insn
->name
, insn
[1].name
))
4955 as_bad ("16 bit expression not in range 0..65535");
4963 /* The upper bound should be 0x8000, but
4964 unfortunately the MIPS assembler accepts numbers
4965 from 0x8000 to 0xffff and sign extends them, and
4966 we want to be compatible. We only permit this
4967 extended range for an instruction which does not
4968 provide any further alternates, since those
4969 alternates may handle other cases. People should
4970 use the numbers they mean, rather than relying on
4971 a mysterious sign extension. */
4972 more
= (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
4973 strcmp (insn
->name
, insn
[1].name
) == 0);
4978 if (imm_expr
.X_op
== O_big
4979 || imm_expr
.X_add_number
< -0x8000
4980 || imm_expr
.X_add_number
>= max
4982 && imm_expr
.X_add_number
< 0
4984 && imm_expr
.X_unsigned
4985 && sizeof (imm_expr
.X_add_number
) <= 4))
4989 as_bad ("16 bit expression not in range -32768..32767");
4995 case 'o': /* 16 bit offset */
4996 c
= my_getSmallExpression (&offset_expr
, s
);
4998 /* If this value won't fit into a 16 bit offset, then go
4999 find a macro that will generate the 32 bit offset
5000 code pattern. As a special hack, we accept the
5001 difference of two local symbols as a constant. This
5002 is required to suppose embedded PIC switches, which
5003 use an instruction which looks like
5004 lw $4,$L12-$LS12($4)
5005 The problem with handling this in a more general
5006 fashion is that the macro function doesn't expect to
5007 see anything which can be handled in a single
5008 constant instruction. */
5010 && (offset_expr
.X_op
!= O_constant
5011 || offset_expr
.X_add_number
>= 0x8000
5012 || offset_expr
.X_add_number
< -0x8000)
5013 && (mips_pic
!= EMBEDDED_PIC
5014 || offset_expr
.X_op
!= O_subtract
5015 || now_seg
!= text_section
5016 || (S_GET_SEGMENT (offset_expr
.X_op_symbol
)
5020 offset_reloc
= BFD_RELOC_LO16
;
5021 if (c
== 'h' || c
== 'H')
5023 assert (offset_expr
.X_op
== O_constant
);
5024 offset_expr
.X_add_number
=
5025 (offset_expr
.X_add_number
>> 16) & 0xffff;
5030 case 'p': /* pc relative offset */
5031 offset_reloc
= BFD_RELOC_16_PCREL_S2
;
5032 my_getExpression (&offset_expr
, s
);
5036 case 'u': /* upper 16 bits */
5037 c
= my_getSmallExpression (&imm_expr
, s
);
5038 if (imm_expr
.X_op
== O_constant
5039 && (imm_expr
.X_add_number
< 0
5040 || imm_expr
.X_add_number
>= 0x10000))
5041 as_bad ("lui expression not in range 0..65535");
5042 imm_reloc
= BFD_RELOC_LO16
;
5047 if (imm_expr
.X_op
== O_constant
)
5048 imm_expr
.X_add_number
=
5049 (imm_expr
.X_add_number
>> 16) & 0xffff;
5051 imm_reloc
= BFD_RELOC_HI16_S
;
5053 imm_reloc
= BFD_RELOC_HI16
;
5059 case 'a': /* 26 bit address */
5060 my_getExpression (&offset_expr
, s
);
5062 offset_reloc
= BFD_RELOC_MIPS_JMP
;
5065 case 'N': /* 3 bit branch condition code */
5066 case 'M': /* 3 bit compare condition code */
5067 my_getExpression (&imm_expr
, s
);
5068 check_absolute_expr (ip
, &imm_expr
);
5069 if ((unsigned long) imm_expr
.X_add_number
> 7)
5071 as_warn ("Condition code > 7 (%ld)",
5072 (long) imm_expr
.X_add_number
);
5073 imm_expr
.X_add_number
&= 7;
5076 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_BCC
;
5078 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_CCC
;
5079 imm_expr
.X_op
= O_absent
;
5084 fprintf (stderr
, "bad char = '%c'\n", *args
);
5089 /* Args don't match. */
5090 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
5091 !strcmp (insn
->name
, insn
[1].name
))
5097 insn_error
= "ERROR: Illegal operands";
5106 my_getSmallExpression (ep
, str
)
5117 ((str
[1] == 'h' && str
[2] == 'i')
5118 || (str
[1] == 'H' && str
[2] == 'I')
5119 || (str
[1] == 'l' && str
[2] == 'o'))
5131 * A small expression may be followed by a base register.
5132 * Scan to the end of this operand, and then back over a possible
5133 * base register. Then scan the small expression up to that
5134 * point. (Based on code in sparc.c...)
5136 for (sp
= str
; *sp
&& *sp
!= ','; sp
++)
5138 if (sp
- 4 >= str
&& sp
[-1] == RP
)
5140 if (isdigit (sp
[-2]))
5142 for (sp
-= 3; sp
>= str
&& isdigit (*sp
); sp
--)
5144 if (*sp
== '$' && sp
> str
&& sp
[-1] == LP
)
5150 else if (sp
- 5 >= str
5153 && ((sp
[-3] == 'f' && sp
[-2] == 'p')
5154 || (sp
[-3] == 's' && sp
[-2] == 'p')
5155 || (sp
[-3] == 'g' && sp
[-2] == 'p')
5156 || (sp
[-3] == 'a' && sp
[-2] == 't')))
5162 /* no expression means zero offset */
5165 /* %xx(reg) is an error */
5166 ep
->X_op
= O_absent
;
5171 ep
->X_op
= O_constant
;
5174 ep
->X_add_symbol
= NULL
;
5175 ep
->X_op_symbol
= NULL
;
5176 ep
->X_add_number
= 0;
5181 my_getExpression (ep
, str
);
5188 my_getExpression (ep
, str
);
5189 return c
; /* => %hi or %lo encountered */
5193 my_getExpression (ep
, str
)
5199 save_in
= input_line_pointer
;
5200 input_line_pointer
= str
;
5202 expr_end
= input_line_pointer
;
5203 input_line_pointer
= save_in
;
5206 /* Turn a string in input_line_pointer into a floating point constant
5207 of type type, and store the appropriate bytes in *litP. The number
5208 of LITTLENUMS emitted is stored in *sizeP . An error message is
5209 returned, or NULL on OK. */
5212 md_atof (type
, litP
, sizeP
)
5218 LITTLENUM_TYPE words
[4];
5234 return "bad call to md_atof";
5237 t
= atof_ieee (input_line_pointer
, type
, words
);
5239 input_line_pointer
= t
;
5243 if (byte_order
== LITTLE_ENDIAN
)
5245 for (i
= prec
- 1; i
>= 0; i
--)
5247 md_number_to_chars (litP
, (valueT
) words
[i
], 2);
5253 for (i
= 0; i
< prec
; i
++)
5255 md_number_to_chars (litP
, (valueT
) words
[i
], 2);
5264 md_number_to_chars (buf
, val
, n
)
5272 number_to_chars_littleendian (buf
, val
, n
);
5276 number_to_chars_bigendian (buf
, val
, n
);
5284 CONST
char *md_shortopts
= "O::g::G:";
5286 struct option md_longopts
[] = {
5287 #define OPTION_MIPS1 (OPTION_MD_BASE + 1)
5288 {"mips0", no_argument
, NULL
, OPTION_MIPS1
},
5289 {"mips1", no_argument
, NULL
, OPTION_MIPS1
},
5290 #define OPTION_MIPS2 (OPTION_MD_BASE + 2)
5291 {"mips2", no_argument
, NULL
, OPTION_MIPS2
},
5292 #define OPTION_MIPS3 (OPTION_MD_BASE + 3)
5293 {"mips3", no_argument
, NULL
, OPTION_MIPS3
},
5294 #define OPTION_MIPS4 (OPTION_MD_BASE + 4)
5295 {"mips4", no_argument
, NULL
, OPTION_MIPS4
},
5296 #define OPTION_MCPU (OPTION_MD_BASE + 5)
5297 {"mcpu", required_argument
, NULL
, OPTION_MCPU
},
5298 #define OPTION_MEMBEDDED_PIC (OPTION_MD_BASE + 6)
5299 {"membedded-pic", no_argument
, NULL
, OPTION_MEMBEDDED_PIC
},
5300 #define OPTION_TRAP (OPTION_MD_BASE + 9)
5301 {"trap", no_argument
, NULL
, OPTION_TRAP
},
5302 {"no-break", no_argument
, NULL
, OPTION_TRAP
},
5303 #define OPTION_BREAK (OPTION_MD_BASE + 10)
5304 {"break", no_argument
, NULL
, OPTION_BREAK
},
5305 {"no-trap", no_argument
, NULL
, OPTION_BREAK
},
5306 #define OPTION_EB (OPTION_MD_BASE + 11)
5307 {"EB", no_argument
, NULL
, OPTION_EB
},
5308 #define OPTION_EL (OPTION_MD_BASE + 12)
5309 {"EL", no_argument
, NULL
, OPTION_EL
},
5310 #define OPTION_M4650 (OPTION_MD_BASE + 13)
5311 {"m4650", no_argument
, NULL
, OPTION_M4650
},
5312 #define OPTION_NO_M4650 (OPTION_MD_BASE + 14)
5313 {"no-m4650", no_argument
, NULL
, OPTION_NO_M4650
},
5314 #define OPTION_M4010 (OPTION_MD_BASE + 15)
5315 {"m4010", no_argument
, NULL
, OPTION_M4010
},
5316 #define OPTION_NO_M4010 (OPTION_MD_BASE + 16)
5317 {"no-m4010", no_argument
, NULL
, OPTION_NO_M4010
},
5318 #define OPTION_M4100 (OPTION_MD_BASE + 17)
5319 {"m4100", no_argument
, NULL
, OPTION_M4100
},
5320 #define OPTION_NO_M4100 (OPTION_MD_BASE + 18)
5321 {"no-m4100", no_argument
, NULL
, OPTION_NO_M4100
},
5323 #define OPTION_CALL_SHARED (OPTION_MD_BASE + 7)
5324 #define OPTION_NON_SHARED (OPTION_MD_BASE + 8)
5326 {"KPIC", no_argument
, NULL
, OPTION_CALL_SHARED
},
5327 {"call_shared", no_argument
, NULL
, OPTION_CALL_SHARED
},
5328 {"non_shared", no_argument
, NULL
, OPTION_NON_SHARED
},
5331 {NULL
, no_argument
, NULL
, 0}
5333 size_t md_longopts_size
= sizeof(md_longopts
);
5336 md_parse_option (c
, arg
)
5351 target_big_endian
= 1;
5355 target_big_endian
= 0;
5359 if (arg
&& arg
[1] == '0')
5369 mips_debug
= atoi (arg
);
5370 /* When the MIPS assembler sees -g or -g2, it does not do
5371 optimizations which limit full symbolic debugging. We take
5372 that to be equivalent to -O0. */
5373 if (mips_debug
== 2)
5405 /* Identify the processor type */
5407 if (strcmp (p
, "default") == 0
5408 || strcmp (p
, "DEFAULT") == 0)
5414 /* We need to cope with the various "vr" prefixes for the 4300
5416 if (*p
== 'v' || *p
== 'V')
5422 if (*p
== 'r' || *p
== 'R')
5429 if (strcmp (p
, "10000") == 0
5430 || strcmp (p
, "10k") == 0
5431 || strcmp (p
, "10K") == 0)
5436 if (strcmp (p
, "2000") == 0
5437 || strcmp (p
, "2k") == 0
5438 || strcmp (p
, "2K") == 0)
5443 if (strcmp (p
, "3000") == 0
5444 || strcmp (p
, "3k") == 0
5445 || strcmp (p
, "3K") == 0)
5450 if (strcmp (p
, "4000") == 0
5451 || strcmp (p
, "4k") == 0
5452 || strcmp (p
, "4K") == 0)
5454 else if (strcmp (p
, "4100") == 0)
5460 else if (strcmp (p
, "4300") == 0)
5462 else if (strcmp (p
, "4400") == 0)
5464 else if (strcmp (p
, "4600") == 0)
5466 else if (strcmp (p
, "4650") == 0)
5472 else if (strcmp (p
, "4010") == 0)
5481 if (strcmp (p
, "6000") == 0
5482 || strcmp (p
, "6k") == 0
5483 || strcmp (p
, "6K") == 0)
5488 if (strcmp (p
, "8000") == 0
5489 || strcmp (p
, "8k") == 0
5490 || strcmp (p
, "8K") == 0)
5495 if (strcmp (p
, "orion") == 0)
5500 if (sv
&& mips_cpu
!= 4300 && mips_cpu
!= 4100)
5502 as_bad ("ignoring invalid leading 'v' in -mcpu=%s switch", arg
);
5508 as_bad ("invalid architecture -mcpu=%s", arg
);
5519 case OPTION_NO_M4650
:
5527 case OPTION_NO_M4010
:
5535 case OPTION_NO_M4100
:
5539 case OPTION_MEMBEDDED_PIC
:
5540 mips_pic
= EMBEDDED_PIC
;
5541 if (USE_GLOBAL_POINTER_OPT
&& g_switch_seen
)
5543 as_bad ("-G may not be used with embedded PIC code");
5546 g_switch_value
= 0x7fffffff;
5549 /* When generating ELF code, we permit -KPIC and -call_shared to
5550 select SVR4_PIC, and -non_shared to select no PIC. This is
5551 intended to be compatible with Irix 5. */
5552 case OPTION_CALL_SHARED
:
5553 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
5555 as_bad ("-call_shared is supported only for ELF format");
5558 mips_pic
= SVR4_PIC
;
5559 if (g_switch_seen
&& g_switch_value
!= 0)
5561 as_bad ("-G may not be used with SVR4 PIC code");
5567 case OPTION_NON_SHARED
:
5568 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
5570 as_bad ("-non_shared is supported only for ELF format");
5577 if (! USE_GLOBAL_POINTER_OPT
)
5579 as_bad ("-G is not supported for this configuration");
5582 else if (mips_pic
== SVR4_PIC
|| mips_pic
== EMBEDDED_PIC
)
5584 as_bad ("-G may not be used with SVR4 or embedded PIC code");
5588 g_switch_value
= atoi (arg
);
5600 md_show_usage (stream
)
5605 -membedded-pic generate embedded position independent code\n\
5606 -EB generate big endian output\n\
5607 -EL generate little endian output\n\
5608 -g, -g2 do not remove uneeded NOPs or swap branches\n\
5609 -G NUM allow referencing objects up to NUM bytes\n\
5610 implicitly with the gp register [default 8]\n");
5612 -mips1, -mcpu=r{2,3}000 generate code for r2000 and r3000\n\
5613 -mips2, -mcpu=r6000 generate code for r6000\n\
5614 -mips3, -mcpu=r4000 generate code for r4000\n\
5615 -mips4, -mcpu=r8000 generate code for r8000\n\
5616 -mcpu=vr4300 generate code for vr4300\n\
5617 -m4650 permit R4650 instructions\n\
5618 -no-m4650 do not permit R4650 instructions\n\
5619 -m4010 permit R4010 instructions\n\
5620 -no-m4010 do not permit R4010 instructions\n\
5621 -m4100 permit VR4100 instructions\n\
5622 -no-m4100 do not permit VR4100 instructions\n");
5624 -O0 remove unneeded NOPs, do not swap branches\n\
5625 -O remove unneeded NOPs and swap branches\n\
5626 --trap, --no-break trap exception on div by 0 and mult overflow\n\
5627 --break, --no-trap break exception on div by 0 and mult overflow\n");
5630 -KPIC, -call_shared generate SVR4 position independent code\n\
5631 -non_shared do not generate position independent code\n");
5636 mips_init_after_args ()
5638 if (target_big_endian
)
5639 byte_order
= BIG_ENDIAN
;
5641 byte_order
= LITTLE_ENDIAN
;
5645 md_pcrel_from (fixP
)
5648 if (OUTPUT_FLAVOR
!= bfd_target_aout_flavour
5649 && fixP
->fx_addsy
!= (symbolS
*) NULL
5650 && ! S_IS_DEFINED (fixP
->fx_addsy
))
5652 /* This makes a branch to an undefined symbol be a branch to the
5653 current location. */
5657 /* return the address of the delay slot */
5658 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
5661 /* This is called by emit_expr via TC_CONS_FIX_NEW when creating a
5662 reloc for a cons. We could use the definition there, except that
5663 we want to handle 64 bit relocs specially. */
5666 cons_fix_new_mips (frag
, where
, nbytes
, exp
)
5669 unsigned int nbytes
;
5672 /* If we are assembling in 32 bit mode, turn an 8 byte reloc into a
5674 FIXME: There is no way to select anything but 32 bit mode right
5678 if (byte_order
== BIG_ENDIAN
)
5683 if (nbytes
!= 2 && nbytes
!= 4)
5684 as_bad ("Unsupported reloc size %d", nbytes
);
5686 fix_new_exp (frag_now
, where
, (int) nbytes
, exp
, 0,
5687 nbytes
== 2 ? BFD_RELOC_16
: BFD_RELOC_32
);
5690 /* When generating embedded PIC code we need to use a special
5691 relocation to represent the difference of two symbols in the .text
5692 section (switch tables use a difference of this sort). See
5693 include/coff/mips.h for details. This macro checks whether this
5694 fixup requires the special reloc. */
5695 #define SWITCH_TABLE(fixp) \
5696 ((fixp)->fx_r_type == BFD_RELOC_32 \
5697 && (fixp)->fx_addsy != NULL \
5698 && (fixp)->fx_subsy != NULL \
5699 && S_GET_SEGMENT ((fixp)->fx_addsy) == text_section \
5700 && S_GET_SEGMENT ((fixp)->fx_subsy) == text_section)
5702 /* When generating embedded PIC code we must keep all PC relative
5703 relocations, in case the linker has to relax a call. We also need
5704 to keep relocations for switch table entries. */
5708 mips_force_relocation (fixp
)
5711 return (mips_pic
== EMBEDDED_PIC
5713 || SWITCH_TABLE (fixp
)
5714 || fixp
->fx_r_type
== BFD_RELOC_PCREL_HI16_S
5715 || fixp
->fx_r_type
== BFD_RELOC_PCREL_LO16
));
5718 /* Apply a fixup to the object file. */
5721 md_apply_fix (fixP
, valueP
)
5728 assert (fixP
->fx_size
== 4 || fixP
->fx_r_type
== BFD_RELOC_16
);
5731 fixP
->fx_addnumber
= value
; /* Remember value for tc_gen_reloc */
5733 if (fixP
->fx_addsy
== NULL
&& ! fixP
->fx_pcrel
)
5736 switch (fixP
->fx_r_type
)
5738 case BFD_RELOC_MIPS_JMP
:
5739 case BFD_RELOC_HI16
:
5740 case BFD_RELOC_HI16_S
:
5741 case BFD_RELOC_MIPS_GPREL
:
5742 case BFD_RELOC_MIPS_LITERAL
:
5743 case BFD_RELOC_MIPS_CALL16
:
5744 case BFD_RELOC_MIPS_GOT16
:
5745 case BFD_RELOC_MIPS_GPREL32
:
5747 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
5748 "Invalid PC relative reloc");
5749 /* Nothing needed to do. The value comes from the reloc entry */
5752 case BFD_RELOC_PCREL_HI16_S
:
5753 /* The addend for this is tricky if it is internal, so we just
5754 do everything here rather than in bfd_perform_relocation. */
5755 if ((fixP
->fx_addsy
->bsym
->flags
& BSF_SECTION_SYM
) == 0)
5757 /* For an external symbol adjust by the address to make it
5758 pcrel_offset. We use the address of the RELLO reloc
5759 which follows this one. */
5760 value
+= (fixP
->fx_next
->fx_frag
->fr_address
5761 + fixP
->fx_next
->fx_where
);
5766 buf
= (unsigned char *) fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
5767 if (byte_order
== BIG_ENDIAN
)
5769 md_number_to_chars (buf
, value
, 2);
5772 case BFD_RELOC_PCREL_LO16
:
5773 /* The addend for this is tricky if it is internal, so we just
5774 do everything here rather than in bfd_perform_relocation. */
5775 if ((fixP
->fx_addsy
->bsym
->flags
& BSF_SECTION_SYM
) == 0)
5776 value
+= fixP
->fx_frag
->fr_address
+ fixP
->fx_where
;
5777 buf
= (unsigned char *) fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
5778 if (byte_order
== BIG_ENDIAN
)
5780 md_number_to_chars (buf
, value
, 2);
5784 /* If we are deleting this reloc entry, we must fill in the
5785 value now. This can happen if we have a .word which is not
5786 resolved when it appears but is later defined. We also need
5787 to fill in the value if this is an embedded PIC switch table
5790 || (mips_pic
== EMBEDDED_PIC
&& SWITCH_TABLE (fixP
)))
5791 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
,
5796 /* If we are deleting this reloc entry, we must fill in the
5798 assert (fixP
->fx_size
== 2);
5800 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
,
5804 case BFD_RELOC_LO16
:
5805 /* When handling an embedded PIC switch statement, we can wind
5806 up deleting a LO16 reloc. See the 'o' case in mips_ip. */
5809 if (value
< -0x8000 || value
> 0x7fff)
5810 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
5811 "relocation overflow");
5812 buf
= (unsigned char *) fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
5813 if (byte_order
== BIG_ENDIAN
)
5815 md_number_to_chars (buf
, value
, 2);
5819 case BFD_RELOC_16_PCREL_S2
:
5821 * We need to save the bits in the instruction since fixup_segment()
5822 * might be deleting the relocation entry (i.e., a branch within
5823 * the current segment).
5826 as_warn_where (fixP
->fx_file
, fixP
->fx_line
,
5827 "Branch to odd address (%lx)", value
);
5830 /* update old instruction data */
5831 buf
= (unsigned char *) (fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
);
5835 insn
= (buf
[3] << 24) | (buf
[2] << 16) | (buf
[1] << 8) | buf
[0];
5839 insn
= (buf
[0] << 24) | (buf
[1] << 16) | (buf
[2] << 8) | buf
[3];
5847 if (value
>= -0x8000 && value
< 0x8000)
5848 insn
|= value
& 0xffff;
5851 /* The branch offset is too large. If this is an
5852 unconditional branch, and we are not generating PIC code,
5853 we can convert it to an absolute jump instruction. */
5854 if (mips_pic
== NO_PIC
5856 && fixP
->fx_frag
->fr_address
>= text_section
->vma
5857 && (fixP
->fx_frag
->fr_address
5858 < text_section
->vma
+ text_section
->_raw_size
)
5859 && ((insn
& 0xffff0000) == 0x10000000 /* beq $0,$0 */
5860 || (insn
& 0xffff0000) == 0x04010000 /* bgez $0 */
5861 || (insn
& 0xffff0000) == 0x04110000)) /* bgezal $0 */
5863 if ((insn
& 0xffff0000) == 0x04110000) /* bgezal $0 */
5864 insn
= 0x0c000000; /* jal */
5866 insn
= 0x08000000; /* j */
5867 fixP
->fx_r_type
= BFD_RELOC_MIPS_JMP
;
5869 fixP
->fx_addsy
= section_symbol (text_section
);
5870 fixP
->fx_addnumber
= (value
<< 2) + md_pcrel_from (fixP
);
5874 /* FIXME. It would be possible in principle to handle
5875 conditional branches which overflow. They could be
5876 transformed into a branch around a jump. This would
5877 require setting up variant frags for each different
5878 branch type. The native MIPS assembler attempts to
5879 handle these cases, but it appears to do it
5881 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
5882 "Relocation overflow");
5886 md_number_to_chars ((char *) buf
, (valueT
) insn
, 4);
5901 const struct mips_opcode
*p
;
5902 int treg
, sreg
, dreg
, shamt
;
5907 for (i
= 0; i
< NUMOPCODES
; ++i
)
5909 p
= &mips_opcodes
[i
];
5910 if (((oc
& p
->mask
) == p
->match
) && (p
->pinfo
!= INSN_MACRO
))
5912 printf ("%08lx %s\t", oc
, p
->name
);
5913 treg
= (oc
>> 16) & 0x1f;
5914 sreg
= (oc
>> 21) & 0x1f;
5915 dreg
= (oc
>> 11) & 0x1f;
5916 shamt
= (oc
>> 6) & 0x1f;
5918 for (args
= p
->args
;; ++args
)
5929 printf ("%c", *args
);
5933 assert (treg
== sreg
);
5934 printf ("$%d,$%d", treg
, sreg
);
5939 printf ("$%d", dreg
);
5944 printf ("$%d", treg
);
5948 printf ("0x%x", treg
);
5953 printf ("$%d", sreg
);
5957 printf ("0x%08lx", oc
& 0x1ffffff);
5969 printf ("$%d", shamt
);
5980 printf ("%08lx UNDEFINED\n", oc
);
5991 name
= input_line_pointer
;
5992 c
= get_symbol_end ();
5993 p
= (symbolS
*) symbol_find_or_make (name
);
5994 *input_line_pointer
= c
;
5998 /* Align the current frag to a given power of two. The MIPS assembler
5999 also automatically adjusts any preceding label. */
6002 mips_align (to
, fill
, label
)
6007 mips_emit_delays ();
6008 frag_align (to
, fill
);
6009 record_alignment (now_seg
, to
);
6012 assert (S_GET_SEGMENT (label
) == now_seg
);
6013 label
->sy_frag
= frag_now
;
6014 S_SET_VALUE (label
, (valueT
) frag_now_fix ());
6018 /* Align to a given power of two. .align 0 turns off the automatic
6019 alignment used by the data creating pseudo-ops. */
6026 register long temp_fill
;
6027 long max_alignment
= 15;
6031 o Note that the assembler pulls down any immediately preceeding label
6032 to the aligned address.
6033 o It's not documented but auto alignment is reinstated by
6034 a .align pseudo instruction.
6035 o Note also that after auto alignment is turned off the mips assembler
6036 issues an error on attempt to assemble an improperly aligned data item.
6041 temp
= get_absolute_expression ();
6042 if (temp
> max_alignment
)
6043 as_bad ("Alignment too large: %d. assumed.", temp
= max_alignment
);
6046 as_warn ("Alignment negative: 0 assumed.");
6049 if (*input_line_pointer
== ',')
6051 input_line_pointer
++;
6052 temp_fill
= get_absolute_expression ();
6059 mips_align (temp
, (int) temp_fill
, insn_label
);
6066 demand_empty_rest_of_line ();
6070 mips_flush_pending_output ()
6072 mips_emit_delays ();
6082 /* When generating embedded PIC code, we only use the .text, .lit8,
6083 .sdata and .sbss sections. We change the .data and .rdata
6084 pseudo-ops to use .sdata. */
6085 if (mips_pic
== EMBEDDED_PIC
6086 && (sec
== 'd' || sec
== 'r'))
6089 mips_emit_delays ();
6099 subseg_set (bss_section
, (subsegT
) get_absolute_expression ());
6100 demand_empty_rest_of_line ();
6104 if (USE_GLOBAL_POINTER_OPT
)
6106 seg
= subseg_new (RDATA_SECTION_NAME
,
6107 (subsegT
) get_absolute_expression ());
6108 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
6110 bfd_set_section_flags (stdoutput
, seg
,
6116 bfd_set_section_alignment (stdoutput
, seg
, 4);
6118 demand_empty_rest_of_line ();
6122 as_bad ("No read only data section in this object file format");
6123 demand_empty_rest_of_line ();
6129 if (USE_GLOBAL_POINTER_OPT
)
6131 seg
= subseg_new (".sdata", (subsegT
) get_absolute_expression ());
6132 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
6134 bfd_set_section_flags (stdoutput
, seg
,
6135 SEC_ALLOC
| SEC_LOAD
| SEC_RELOC
6137 bfd_set_section_alignment (stdoutput
, seg
, 4);
6139 demand_empty_rest_of_line ();
6144 as_bad ("Global pointers not supported; recompile -G 0");
6145 demand_empty_rest_of_line ();
6154 mips_enable_auto_align ()
6166 mips_emit_delays ();
6167 if (log_size
> 0 && auto_align
)
6168 mips_align (log_size
, 0, label
);
6170 cons (1 << log_size
);
6177 as_fatal ("Encountered `.err', aborting assembly");
6187 symbolP
= get_symbol ();
6188 if (*input_line_pointer
== ',')
6189 input_line_pointer
++;
6190 size
= get_absolute_expression ();
6191 S_SET_EXTERNAL (symbolP
);
6193 #ifndef NO_ECOFF_DEBUGGING
6194 if (ECOFF_DEBUGGING
)
6195 symbolP
->ecoff_extern_size
= size
;
6207 mips_emit_delays ();
6211 mips_align (3, 0, label
);
6213 mips_align (2, 0, label
);
6220 /* Handle .globl. We need to override it because on Irix 5 you are
6223 where foo is an undefined symbol, to mean that foo should be
6224 considered to be the address of a function. */
6234 name
= input_line_pointer
;
6235 c
= get_symbol_end ();
6236 symbolP
= symbol_find_or_make (name
);
6237 *input_line_pointer
= c
;
6239 if (! is_end_of_line
[(unsigned char) *input_line_pointer
])
6244 secname
= input_line_pointer
;
6245 c
= get_symbol_end ();
6246 sec
= bfd_get_section_by_name (stdoutput
, secname
);
6248 as_bad ("%s: no such section", secname
);
6249 *input_line_pointer
= c
;
6251 if (sec
!= NULL
&& (sec
->flags
& SEC_CODE
) != 0)
6252 symbolP
->bsym
->flags
|= BSF_FUNCTION
;
6255 S_SET_EXTERNAL (symbolP
);
6256 demand_empty_rest_of_line ();
6266 opt
= input_line_pointer
;
6267 c
= get_symbol_end ();
6271 /* FIXME: What does this mean? */
6273 else if (strncmp (opt
, "pic", 3) == 0)
6281 mips_pic
= SVR4_PIC
;
6283 as_bad (".option pic%d not supported", i
);
6285 if (USE_GLOBAL_POINTER_OPT
&& mips_pic
== SVR4_PIC
)
6287 if (g_switch_seen
&& g_switch_value
!= 0)
6288 as_warn ("-G may not be used with SVR4 PIC code");
6290 bfd_set_gp_size (stdoutput
, 0);
6294 as_warn ("Unrecognized option \"%s\"", opt
);
6296 *input_line_pointer
= c
;
6297 demand_empty_rest_of_line ();
6304 char *name
= input_line_pointer
, ch
;
6306 while (!is_end_of_line
[(unsigned char) *input_line_pointer
])
6307 input_line_pointer
++;
6308 ch
= *input_line_pointer
;
6309 *input_line_pointer
= '\0';
6311 if (strcmp (name
, "reorder") == 0)
6315 prev_insn_unreordered
= 1;
6316 prev_prev_insn_unreordered
= 1;
6320 else if (strcmp (name
, "noreorder") == 0)
6322 mips_emit_delays ();
6324 mips_any_noreorder
= 1;
6326 else if (strcmp (name
, "at") == 0)
6330 else if (strcmp (name
, "noat") == 0)
6334 else if (strcmp (name
, "macro") == 0)
6336 mips_warn_about_macros
= 0;
6338 else if (strcmp (name
, "nomacro") == 0)
6340 if (mips_noreorder
== 0)
6341 as_bad ("`noreorder' must be set before `nomacro'");
6342 mips_warn_about_macros
= 1;
6344 else if (strcmp (name
, "move") == 0 || strcmp (name
, "novolatile") == 0)
6348 else if (strcmp (name
, "nomove") == 0 || strcmp (name
, "volatile") == 0)
6352 else if (strcmp (name
, "bopt") == 0)
6356 else if (strcmp (name
, "nobopt") == 0)
6360 else if (strncmp (name
, "mips", 4) == 0)
6364 /* Permit the user to change the ISA on the fly. Needless to
6365 say, misuse can cause serious problems. */
6366 isa
= atoi (name
+ 4);
6368 mips_isa
= file_mips_isa
;
6369 else if (isa
< 1 || isa
> 4)
6370 as_bad ("unknown ISA level");
6376 as_warn ("Tried to set unrecognized symbol: %s\n", name
);
6378 *input_line_pointer
= ch
;
6379 demand_empty_rest_of_line ();
6382 /* Handle the .abicalls pseudo-op. I believe this is equivalent to
6383 .option pic2. It means to generate SVR4 PIC calls. */
6389 mips_pic
= SVR4_PIC
;
6390 if (USE_GLOBAL_POINTER_OPT
)
6392 if (g_switch_seen
&& g_switch_value
!= 0)
6393 as_warn ("-G may not be used with SVR4 PIC code");
6396 bfd_set_gp_size (stdoutput
, 0);
6397 demand_empty_rest_of_line ();
6400 /* Handle the .cpload pseudo-op. This is used when generating SVR4
6401 PIC code. It sets the $gp register for the function based on the
6402 function address, which is in the register named in the argument.
6403 This uses a relocation against _gp_disp, which is handled specially
6404 by the linker. The result is:
6405 lui $gp,%hi(_gp_disp)
6406 addiu $gp,$gp,%lo(_gp_disp)
6407 addu $gp,$gp,.cpload argument
6408 The .cpload argument is normally $25 == $t9. */
6417 /* If we are not generating SVR4 PIC code, .cpload is ignored. */
6418 if (mips_pic
!= SVR4_PIC
)
6424 /* .cpload should be a in .set noreorder section. */
6425 if (mips_noreorder
== 0)
6426 as_warn (".cpload not in noreorder section");
6429 ex
.X_add_symbol
= symbol_find_or_make ("_gp_disp");
6430 ex
.X_op_symbol
= NULL
;
6431 ex
.X_add_number
= 0;
6433 macro_build_lui ((char *) NULL
, &icnt
, &ex
, GP
);
6434 macro_build ((char *) NULL
, &icnt
, &ex
, "addiu", "t,r,j", GP
, GP
,
6435 (int) BFD_RELOC_LO16
);
6437 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "addu", "d,v,t",
6438 GP
, GP
, tc_get_register (0));
6440 demand_empty_rest_of_line ();
6443 /* Handle the .cprestore pseudo-op. This stores $gp into a given
6444 offset from $sp. The offset is remembered, and after making a PIC
6445 call $gp is restored from that location. */
6448 s_cprestore (ignore
)
6454 /* If we are not generating SVR4 PIC code, .cprestore is ignored. */
6455 if (mips_pic
!= SVR4_PIC
)
6461 mips_cprestore_offset
= get_absolute_expression ();
6463 ex
.X_op
= O_constant
;
6464 ex
.X_add_symbol
= NULL
;
6465 ex
.X_op_symbol
= NULL
;
6466 ex
.X_add_number
= mips_cprestore_offset
;
6468 macro_build ((char *) NULL
, &icnt
, &ex
,
6469 mips_isa
< 3 ? "sw" : "sd",
6470 "t,o(b)", GP
, (int) BFD_RELOC_LO16
, SP
);
6472 demand_empty_rest_of_line ();
6475 /* Handle the .gpword pseudo-op. This is used when generating PIC
6476 code. It generates a 32 bit GP relative reloc. */
6486 /* When not generating PIC code, this is treated as .word. */
6487 if (mips_pic
!= SVR4_PIC
)
6494 mips_emit_delays ();
6496 mips_align (2, 0, label
);
6501 if (ex
.X_op
!= O_symbol
|| ex
.X_add_number
!= 0)
6503 as_bad ("Unsupported use of .gpword");
6504 ignore_rest_of_line ();
6508 md_number_to_chars (p
, (valueT
) 0, 4);
6509 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 4, &ex
, 0,
6510 BFD_RELOC_MIPS_GPREL32
);
6512 demand_empty_rest_of_line ();
6515 /* Handle the .cpadd pseudo-op. This is used when dealing with switch
6516 tables in SVR4 PIC code. */
6525 /* This is ignored when not generating SVR4 PIC code. */
6526 if (mips_pic
!= SVR4_PIC
)
6532 /* Add $gp to the register named as an argument. */
6533 reg
= tc_get_register (0);
6534 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6535 mips_isa
< 3 ? "addu" : "daddu",
6536 "d,v,t", reg
, reg
, GP
);
6538 demand_empty_rest_of_line ();
6541 /* Parse a register string into a number. Called from the ECOFF code
6542 to parse .frame. The argument is non-zero if this is the frame
6543 register, so that we can record it in mips_frame_reg. */
6546 tc_get_register (frame
)
6552 if (*input_line_pointer
++ != '$')
6554 as_warn ("expected `$'");
6557 else if (isdigit ((unsigned char) *input_line_pointer
))
6559 reg
= get_absolute_expression ();
6560 if (reg
< 0 || reg
>= 32)
6562 as_warn ("Bad register number");
6568 if (strncmp (input_line_pointer
, "fp", 2) == 0)
6570 else if (strncmp (input_line_pointer
, "sp", 2) == 0)
6572 else if (strncmp (input_line_pointer
, "gp", 2) == 0)
6574 else if (strncmp (input_line_pointer
, "at", 2) == 0)
6578 as_warn ("Unrecognized register name");
6581 input_line_pointer
+= 2;
6584 mips_frame_reg
= reg
!= 0 ? reg
: SP
;
6589 md_section_align (seg
, addr
)
6593 int align
= bfd_get_section_alignment (stdoutput
, seg
);
6595 return ((addr
+ (1 << align
) - 1) & (-1 << align
));
6598 /* Utility routine, called from above as well. If called while the
6599 input file is still being read, it's only an approximation. (For
6600 example, a symbol may later become defined which appeared to be
6601 undefined earlier.) */
6604 nopic_need_relax (sym
)
6610 if (USE_GLOBAL_POINTER_OPT
)
6612 const char *symname
;
6615 /* Find out whether this symbol can be referenced off the GP
6616 register. It can be if it is smaller than the -G size or if
6617 it is in the .sdata or .sbss section. Certain symbols can
6618 not be referenced off the GP, although it appears as though
6620 symname
= S_GET_NAME (sym
);
6621 if (symname
!= (const char *) NULL
6622 && (strcmp (symname
, "eprol") == 0
6623 || strcmp (symname
, "etext") == 0
6624 || strcmp (symname
, "_gp") == 0
6625 || strcmp (symname
, "edata") == 0
6626 || strcmp (symname
, "_fbss") == 0
6627 || strcmp (symname
, "_fdata") == 0
6628 || strcmp (symname
, "_ftext") == 0
6629 || strcmp (symname
, "end") == 0
6630 || strcmp (symname
, "_gp_disp") == 0))
6632 else if (! S_IS_DEFINED (sym
)
6634 #ifndef NO_ECOFF_DEBUGGING
6635 || (sym
->ecoff_extern_size
!= 0
6636 && sym
->ecoff_extern_size
<= g_switch_value
)
6638 || (S_GET_VALUE (sym
) != 0
6639 && S_GET_VALUE (sym
) <= g_switch_value
)))
6643 const char *segname
;
6645 segname
= segment_name (S_GET_SEGMENT (sym
));
6646 assert (strcmp (segname
, ".lit8") != 0
6647 && strcmp (segname
, ".lit4") != 0);
6648 change
= (strcmp (segname
, ".sdata") != 0
6649 && strcmp (segname
, ".sbss") != 0);
6654 /* We are not optimizing for the GP register. */
6658 /* Estimate the size of a frag before relaxing. We are not really
6659 relaxing here, and the final size is encoded in the subtype
6664 md_estimate_size_before_relax (fragp
, segtype
)
6670 if (mips_pic
== NO_PIC
)
6672 change
= nopic_need_relax (fragp
->fr_symbol
);
6674 else if (mips_pic
== SVR4_PIC
)
6676 asection
*symsec
= fragp
->fr_symbol
->bsym
->section
;
6678 /* This must duplicate the test in adjust_reloc_syms. */
6679 change
= (symsec
!= &bfd_und_section
6680 && symsec
!= &bfd_abs_section
6681 && ! bfd_is_com_section (symsec
));
6688 /* Record the offset to the first reloc in the fr_opcode field.
6689 This lets md_convert_frag and tc_gen_reloc know that the code
6690 must be expanded. */
6691 fragp
->fr_opcode
= (fragp
->fr_literal
6693 - RELAX_OLD (fragp
->fr_subtype
)
6694 + RELAX_RELOC1 (fragp
->fr_subtype
));
6695 /* FIXME: This really needs as_warn_where. */
6696 if (RELAX_WARN (fragp
->fr_subtype
))
6697 as_warn ("AT used after \".set noat\" or macro used after \".set nomacro\"");
6703 return RELAX_NEW (fragp
->fr_subtype
) - RELAX_OLD (fragp
->fr_subtype
);
6706 /* Translate internal representation of relocation info to BFD target
6710 tc_gen_reloc (section
, fixp
)
6714 static arelent
*retval
[4];
6717 reloc
= retval
[0] = (arelent
*) xmalloc (sizeof (arelent
));
6720 reloc
->sym_ptr_ptr
= &fixp
->fx_addsy
->bsym
;
6721 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
6723 if (mips_pic
== EMBEDDED_PIC
6724 && SWITCH_TABLE (fixp
))
6726 /* For a switch table entry we use a special reloc. The addend
6727 is actually the difference between the reloc address and the
6729 reloc
->addend
= reloc
->address
- S_GET_VALUE (fixp
->fx_subsy
);
6730 if (OUTPUT_FLAVOR
!= bfd_target_ecoff_flavour
)
6731 as_fatal ("Double check fx_r_type in tc-mips.c:tc_gen_reloc");
6732 fixp
->fx_r_type
= BFD_RELOC_GPREL32
;
6734 else if (fixp
->fx_r_type
== BFD_RELOC_PCREL_LO16
)
6736 /* We use a special addend for an internal RELLO reloc. */
6737 if (fixp
->fx_addsy
->bsym
->flags
& BSF_SECTION_SYM
)
6738 reloc
->addend
= reloc
->address
- S_GET_VALUE (fixp
->fx_subsy
);
6740 reloc
->addend
= fixp
->fx_addnumber
+ reloc
->address
;
6742 else if (fixp
->fx_r_type
== BFD_RELOC_PCREL_HI16_S
)
6744 assert (fixp
->fx_next
!= NULL
6745 && fixp
->fx_next
->fx_r_type
== BFD_RELOC_PCREL_LO16
);
6746 /* We use a special addend for an internal RELHI reloc. The
6747 reloc is relative to the RELLO; adjust the addend
6749 if (fixp
->fx_addsy
->bsym
->flags
& BSF_SECTION_SYM
)
6750 reloc
->addend
= (fixp
->fx_next
->fx_frag
->fr_address
6751 + fixp
->fx_next
->fx_where
6752 - S_GET_VALUE (fixp
->fx_subsy
));
6754 reloc
->addend
= (fixp
->fx_addnumber
6755 + fixp
->fx_next
->fx_frag
->fr_address
6756 + fixp
->fx_next
->fx_where
);
6758 else if (fixp
->fx_pcrel
== 0)
6759 reloc
->addend
= fixp
->fx_addnumber
;
6762 if (OUTPUT_FLAVOR
!= bfd_target_aout_flavour
)
6763 /* A gruesome hack which is a result of the gruesome gas reloc
6765 reloc
->addend
= reloc
->address
;
6767 reloc
->addend
= -reloc
->address
;
6770 /* If this is a variant frag, we may need to adjust the existing
6771 reloc and generate a new one. */
6772 if (fixp
->fx_frag
->fr_opcode
!= NULL
6773 && (fixp
->fx_r_type
== BFD_RELOC_MIPS_GPREL
6774 || fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT16
6775 || fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL16
))
6779 /* If this is not the last reloc in this frag, then we have two
6780 GPREL relocs, both of which are being replaced. Let the
6781 second one handle all of them. */
6782 if (fixp
->fx_next
!= NULL
6783 && fixp
->fx_frag
== fixp
->fx_next
->fx_frag
)
6785 assert (fixp
->fx_r_type
== BFD_RELOC_MIPS_GPREL
6786 && fixp
->fx_next
->fx_r_type
== BFD_RELOC_MIPS_GPREL
);
6791 fixp
->fx_where
= fixp
->fx_frag
->fr_opcode
- fixp
->fx_frag
->fr_literal
;
6792 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
6793 reloc2
= retval
[1] = (arelent
*) xmalloc (sizeof (arelent
));
6795 reloc2
->sym_ptr_ptr
= &fixp
->fx_addsy
->bsym
;
6796 reloc2
->address
= (reloc
->address
6797 + (RELAX_RELOC2 (fixp
->fx_frag
->fr_subtype
)
6798 - RELAX_RELOC1 (fixp
->fx_frag
->fr_subtype
)));
6799 reloc2
->addend
= fixp
->fx_addnumber
;
6800 reloc2
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_LO16
);
6801 assert (reloc2
->howto
!= NULL
);
6803 if (RELAX_RELOC3 (fixp
->fx_frag
->fr_subtype
))
6807 reloc3
= retval
[2] = (arelent
*) xmalloc (sizeof (arelent
));
6810 reloc3
->address
+= 4;
6813 if (mips_pic
== NO_PIC
)
6815 assert (fixp
->fx_r_type
== BFD_RELOC_MIPS_GPREL
);
6816 fixp
->fx_r_type
= BFD_RELOC_HI16_S
;
6818 else if (mips_pic
== SVR4_PIC
)
6820 if (fixp
->fx_r_type
!= BFD_RELOC_MIPS_GOT16
)
6822 assert (fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL16
);
6823 fixp
->fx_r_type
= BFD_RELOC_MIPS_GOT16
;
6830 /* To support a PC relative reloc when generating embedded PIC code
6831 for ECOFF, we use a Cygnus extension. We check for that here to
6832 make sure that we don't let such a reloc escape normally. */
6833 if (OUTPUT_FLAVOR
== bfd_target_ecoff_flavour
6834 && fixp
->fx_r_type
== BFD_RELOC_16_PCREL_S2
6835 && mips_pic
!= EMBEDDED_PIC
)
6836 reloc
->howto
= NULL
;
6838 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, fixp
->fx_r_type
);
6840 if (reloc
->howto
== NULL
)
6842 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
6843 "Can not represent relocation in this object file format");
6850 /* Convert a machine dependent frag. */
6853 md_convert_frag (abfd
, asec
, fragp
)
6861 if (fragp
->fr_opcode
== NULL
)
6864 old
= RELAX_OLD (fragp
->fr_subtype
);
6865 new = RELAX_NEW (fragp
->fr_subtype
);
6866 fixptr
= fragp
->fr_literal
+ fragp
->fr_fix
;
6869 memcpy (fixptr
- old
, fixptr
, new);
6871 fragp
->fr_fix
+= new - old
;
6874 /* This function is called whenever a label is defined. It is used
6875 when handling branch delays; if a branch has a label, we assume we
6879 mips_define_label (sym
)
6885 /* Decide whether a label is local. This is called by LOCAL_LABEL.
6886 In order to work with gcc when using mips-tfile, we must keep all
6887 local labels. However, in other cases, we want to discard them,
6888 since they are useless. */
6891 mips_local_label (name
)
6894 #ifndef NO_ECOFF_DEBUGGING
6897 && ! ecoff_debugging_seen
)
6899 /* We were called with -g, but we didn't see any debugging
6900 information. That may mean that gcc is smuggling debugging
6901 information through to mips-tfile, in which case we must
6902 generate all local labels. */
6907 /* Here it's OK to discard local labels. */
6909 return name
[0] == '$';
6912 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
6914 /* Some special processing for a MIPS ELF file. */
6917 mips_elf_final_processing ()
6921 /* Write out the .reginfo section. */
6922 s
.ri_gprmask
= mips_gprmask
;
6923 s
.ri_cprmask
[0] = mips_cprmask
[0];
6924 s
.ri_cprmask
[1] = mips_cprmask
[1];
6925 s
.ri_cprmask
[2] = mips_cprmask
[2];
6926 s
.ri_cprmask
[3] = mips_cprmask
[3];
6927 /* The gp_value field is set by the MIPS ELF backend. */
6929 bfd_mips_elf32_swap_reginfo_out (stdoutput
, &s
,
6930 ((Elf32_External_RegInfo
*)
6931 mips_regmask_frag
));
6933 /* Set the MIPS ELF flag bits. FIXME: There should probably be some
6934 sort of BFD interface for this. */
6935 if (mips_any_noreorder
)
6936 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_NOREORDER
;
6937 if (mips_pic
!= NO_PIC
)
6938 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_PIC
;
6941 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */
6943 /* These functions should really be defined by the object file format,
6944 since they are related to debugging information. However, this
6945 code has to work for the a.out format, which does not define them,
6946 so we provide simple versions here. These don't actually generate
6947 any debugging information, but they do simple checking and someday
6948 somebody may make them useful. */
6952 struct loc
*loc_next
;
6953 unsigned long loc_fileno
;
6954 unsigned long loc_lineno
;
6955 unsigned long loc_offset
;
6956 unsigned short loc_delta
;
6957 unsigned short loc_count
;
6966 struct proc
*proc_next
;
6967 struct symbol
*proc_isym
;
6968 struct symbol
*proc_end
;
6969 unsigned long proc_reg_mask
;
6970 unsigned long proc_reg_offset
;
6971 unsigned long proc_fpreg_mask
;
6972 unsigned long proc_fpreg_offset
;
6973 unsigned long proc_frameoffset
;
6974 unsigned long proc_framereg
;
6975 unsigned long proc_pcreg
;
6977 struct file
*proc_file
;
6984 struct file
*file_next
;
6985 unsigned long file_fileno
;
6986 struct symbol
*file_symbol
;
6987 struct symbol
*file_end
;
6988 struct proc
*file_proc
;
6993 static struct obstack proc_frags
;
6994 static procS
*proc_lastP
;
6995 static procS
*proc_rootP
;
6996 static int numprocs
;
7001 obstack_begin (&proc_frags
, 0x2000);
7007 /* check for premature end, nesting errors, etc */
7008 if (proc_lastP
&& proc_lastP
->proc_end
== NULL
)
7009 as_warn ("missing `.end' at end of assembly");
7018 if (*input_line_pointer
== '-')
7020 ++input_line_pointer
;
7023 if (!isdigit (*input_line_pointer
))
7024 as_bad ("Expected simple number.");
7025 if (input_line_pointer
[0] == '0')
7027 if (input_line_pointer
[1] == 'x')
7029 input_line_pointer
+= 2;
7030 while (isxdigit (*input_line_pointer
))
7033 val
|= hex_value (*input_line_pointer
++);
7035 return negative
? -val
: val
;
7039 ++input_line_pointer
;
7040 while (isdigit (*input_line_pointer
))
7043 val
|= *input_line_pointer
++ - '0';
7045 return negative
? -val
: val
;
7048 if (!isdigit (*input_line_pointer
))
7050 printf (" *input_line_pointer == '%c' 0x%02x\n",
7051 *input_line_pointer
, *input_line_pointer
);
7052 as_warn ("Invalid number");
7055 while (isdigit (*input_line_pointer
))
7058 val
+= *input_line_pointer
++ - '0';
7060 return negative
? -val
: val
;
7063 /* The .file directive; just like the usual .file directive, but there
7064 is an initial number which is the ECOFF file index. */
7072 line
= get_number ();
7077 /* The .end directive. */
7085 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
7088 demand_empty_rest_of_line ();
7092 if (now_seg
!= text_section
)
7093 as_warn (".end not in text section");
7096 as_warn (".end and no .ent seen yet.");
7102 assert (S_GET_NAME (p
));
7103 if (strcmp (S_GET_NAME (p
), S_GET_NAME (proc_lastP
->proc_isym
)))
7104 as_warn (".end symbol does not match .ent symbol.");
7107 proc_lastP
->proc_end
= (symbolS
*) 1;
7110 /* The .aent and .ent directives. */
7120 symbolP
= get_symbol ();
7121 if (*input_line_pointer
== ',')
7122 input_line_pointer
++;
7124 if (isdigit (*input_line_pointer
) || *input_line_pointer
== '-')
7125 number
= get_number ();
7126 if (now_seg
!= text_section
)
7127 as_warn (".ent or .aent not in text section.");
7129 if (!aent
&& proc_lastP
&& proc_lastP
->proc_end
== NULL
)
7130 as_warn ("missing `.end'");
7134 procP
= (procS
*) obstack_alloc (&proc_frags
, sizeof (*procP
));
7135 procP
->proc_isym
= symbolP
;
7136 procP
->proc_reg_mask
= 0;
7137 procP
->proc_reg_offset
= 0;
7138 procP
->proc_fpreg_mask
= 0;
7139 procP
->proc_fpreg_offset
= 0;
7140 procP
->proc_frameoffset
= 0;
7141 procP
->proc_framereg
= 0;
7142 procP
->proc_pcreg
= 0;
7143 procP
->proc_end
= NULL
;
7144 procP
->proc_next
= NULL
;
7146 proc_lastP
->proc_next
= procP
;
7152 demand_empty_rest_of_line ();
7155 /* The .frame directive. */
7168 frame_reg
= tc_get_register (1);
7169 if (*input_line_pointer
== ',')
7170 input_line_pointer
++;
7171 frame_off
= get_absolute_expression ();
7172 if (*input_line_pointer
== ',')
7173 input_line_pointer
++;
7174 pcreg
= tc_get_register (0);
7177 assert (proc_rootP
);
7178 proc_rootP
->proc_framereg
= frame_reg
;
7179 proc_rootP
->proc_frameoffset
= frame_off
;
7180 proc_rootP
->proc_pcreg
= pcreg
;
7181 /* bob macho .frame */
7183 /* We don't have to write out a frame stab for unoptimized code. */
7184 if (!(frame_reg
== FP
&& frame_off
== 0))
7187 as_warn ("No .ent for .frame to use.");
7188 (void) sprintf (str
, "R%d;%d", frame_reg
, frame_off
);
7189 symP
= symbol_new (str
, N_VFP
, 0, frag_now
);
7190 S_SET_TYPE (symP
, N_RMASK
);
7191 S_SET_OTHER (symP
, 0);
7192 S_SET_DESC (symP
, 0);
7193 symP
->sy_forward
= proc_lastP
->proc_isym
;
7194 /* bob perhaps I should have used pseudo set */
7196 demand_empty_rest_of_line ();
7200 /* The .fmask and .mask directives. */
7207 char str
[100], *strP
;
7213 mask
= get_number ();
7214 if (*input_line_pointer
== ',')
7215 input_line_pointer
++;
7216 off
= get_absolute_expression ();
7218 /* bob only for coff */
7219 assert (proc_rootP
);
7220 if (reg_type
== 'F')
7222 proc_rootP
->proc_fpreg_mask
= mask
;
7223 proc_rootP
->proc_fpreg_offset
= off
;
7227 proc_rootP
->proc_reg_mask
= mask
;
7228 proc_rootP
->proc_reg_offset
= off
;
7231 /* bob macho .mask + .fmask */
7233 /* We don't have to write out a mask stab if no saved regs. */
7237 as_warn ("No .ent for .mask to use.");
7239 for (i
= 0; i
< 32; i
++)
7243 sprintf (strP
, "%c%d,", reg_type
, i
);
7244 strP
+= strlen (strP
);
7248 sprintf (strP
, ";%d,", off
);
7249 symP
= symbol_new (str
, N_RMASK
, 0, frag_now
);
7250 S_SET_TYPE (symP
, N_RMASK
);
7251 S_SET_OTHER (symP
, 0);
7252 S_SET_DESC (symP
, 0);
7253 symP
->sy_forward
= proc_lastP
->proc_isym
;
7254 /* bob perhaps I should have used pseudo set */
7259 /* The .loc directive. */
7270 assert (now_seg
== text_section
);
7272 lineno
= get_number ();
7273 addroff
= frag_now_fix ();
7275 symbolP
= symbol_new ("", N_SLINE
, addroff
, frag_now
);
7276 S_SET_TYPE (symbolP
, N_SLINE
);
7277 S_SET_OTHER (symbolP
, 0);
7278 S_SET_DESC (symbolP
, lineno
);
7279 symbolP
->sy_segment
= now_seg
;