1 /* tc-mips.c -- assemble code for a MIPS chip.
2 Copyright (C) 1993, 1995, 1996 Free Software Foundation, Inc.
3 Contributed by the OSF and Ralph Campbell.
4 Written by Keith Knowles and Ralph Campbell, working independently.
5 Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus
8 This file is part of GAS.
10 GAS is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 2, or (at your option)
15 GAS is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with GAS; see the file COPYING. If not, write to the Free
22 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
28 #include "libiberty.h"
39 #include "opcode/mips.h"
42 /* Clean up namespace so we can include obj-elf.h too. */
43 static int mips_output_flavor () { return OUTPUT_FLAVOR
; }
44 #undef OBJ_PROCESS_STAB
50 #undef TARGET_SYMBOL_FIELDS
52 #undef obj_frob_symbol
54 #undef obj_sec_sym_ok_for_reloc
57 /* Fix any of them that we actually care about. */
59 #define OUTPUT_FLAVOR mips_output_flavor()
66 #ifndef ECOFF_DEBUGGING
67 #define NO_ECOFF_DEBUGGING
68 #define ECOFF_DEBUGGING 0
73 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
74 static char *mips_regmask_frag
;
78 #define PIC_CALL_REG 25
86 extern int target_big_endian
;
88 /* 1 is we should use the 64 bit MIPS ELF ABI, 0 if we should use the
89 32 bit ABI. This has no meaning for ECOFF. */
92 /* The default target format to use. */
96 switch (OUTPUT_FLAVOR
)
98 case bfd_target_aout_flavour
:
99 return target_big_endian
? "a.out-mips-big" : "a.out-mips-little";
100 case bfd_target_ecoff_flavour
:
101 return target_big_endian
? "ecoff-bigmips" : "ecoff-littlemips";
102 case bfd_target_elf_flavour
:
103 return (target_big_endian
104 ? (mips_64
? "elf64-bigmips" : "elf32-bigmips")
105 : (mips_64
? "elf64-littlemips" : "elf32-littlemips"));
111 /* The name of the readonly data section. */
112 #define RDATA_SECTION_NAME (OUTPUT_FLAVOR == bfd_target_aout_flavour \
114 : OUTPUT_FLAVOR == bfd_target_ecoff_flavour \
116 : OUTPUT_FLAVOR == bfd_target_elf_flavour \
120 /* These variables are filled in with the masks of registers used.
121 The object format code reads them and puts them in the appropriate
123 unsigned long mips_gprmask
;
124 unsigned long mips_cprmask
[4];
126 /* MIPS ISA (Instruction Set Architecture) level (may be changed
127 temporarily using .set mipsN). */
128 static int mips_isa
= -1;
130 /* MIPS ISA we are using for this output file. */
131 static int file_mips_isa
;
133 /* The CPU type as a number: 2000, 3000, 4000, 4400, etc. */
134 static int mips_cpu
= -1;
136 /* Whether the 4650 instructions (mad/madu) are permitted. */
137 static int mips_4650
= -1;
139 /* Whether the 4010 instructions are permitted. */
140 static int mips_4010
= -1;
142 /* Whether the 4100 MADD16 and DMADD16 are permitted. */
143 static int mips_4100
= -1;
145 /* Whether the processor uses hardware interlocks, and thus does not
146 require nops to be inserted. */
147 static int interlocks
= -1;
149 /* As with "interlocks" this is used by hardware that has FP
150 (co-processor) interlocks. */
151 static int cop_interlocks
= -1;
153 /* MIPS PIC level. */
157 /* Do not generate PIC code. */
160 /* Generate PIC code as in Irix 4. This is not implemented, and I'm
161 not sure what it is supposed to do. */
164 /* Generate PIC code as in the SVR4 MIPS ABI. */
167 /* Generate PIC code without using a global offset table: the data
168 segment has a maximum size of 64K, all data references are off
169 the $gp register, and all text references are PC relative. This
170 is used on some embedded systems. */
174 static enum mips_pic_level mips_pic
;
176 /* 1 if we should generate 32 bit offsets from the GP register in
177 SVR4_PIC mode. Currently has no meaning in other modes. */
178 static int mips_big_got
;
180 /* 1 if trap instructions should used for overflow rather than break
182 static int mips_trap
;
184 static int mips_warn_about_macros
;
185 static int mips_noreorder
;
186 static int mips_any_noreorder
;
187 static int mips_nomove
;
188 static int mips_noat
;
189 static int mips_nobopt
;
191 /* The size of the small data section. */
192 static int g_switch_value
= 8;
193 /* Whether the -G option was used. */
194 static int g_switch_seen
= 0;
199 /* If we can determine in advance that GP optimization won't be
200 possible, we can skip the relaxation stuff that tries to produce
201 GP-relative references. This makes delay slot optimization work
204 This function can only provide a guess, but it seems to work for
205 gcc output. If it guesses wrong, the only loss should be in
206 efficiency; it shouldn't introduce any bugs.
208 I don't know if a fix is needed for the SVR4_PIC mode. I've only
209 fixed it for the non-PIC mode. KR 95/04/07 */
210 static int nopic_need_relax
PARAMS ((symbolS
*));
212 /* handle of the OPCODE hash table */
213 static struct hash_control
*op_hash
= NULL
;
215 /* This array holds the chars that always start a comment. If the
216 pre-processor is disabled, these aren't very useful */
217 const char comment_chars
[] = "#";
219 /* This array holds the chars that only start a comment at the beginning of
220 a line. If the line seems to have the form '# 123 filename'
221 .line and .file directives will appear in the pre-processed output */
222 /* Note that input_file.c hand checks for '#' at the beginning of the
223 first line of the input file. This is because the compiler outputs
224 #NO_APP at the beginning of its output. */
225 /* Also note that C style comments are always supported. */
226 const char line_comment_chars
[] = "#";
228 /* This array holds machine specific line separator characters. */
229 const char line_separator_chars
[] = "";
231 /* Chars that can be used to separate mant from exp in floating point nums */
232 const char EXP_CHARS
[] = "eE";
234 /* Chars that mean this number is a floating point constant */
237 const char FLT_CHARS
[] = "rRsSfFdDxXpP";
239 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
240 changed in read.c . Ideally it shouldn't have to know about it at all,
241 but nothing is ideal around here.
244 static char *insn_error
;
246 static int byte_order
;
248 static int auto_align
= 1;
250 /* Symbol labelling the current insn. */
251 static symbolS
*insn_label
;
253 /* When outputting SVR4 PIC code, the assembler needs to know the
254 offset in the stack frame from which to restore the $gp register.
255 This is set by the .cprestore pseudo-op, and saved in this
257 static offsetT mips_cprestore_offset
= -1;
259 /* This is the register which holds the stack frame, as set by the
260 .frame pseudo-op. This is needed to implement .cprestore. */
261 static int mips_frame_reg
= SP
;
263 /* To output NOP instructions correctly, we need to keep information
264 about the previous two instructions. */
266 /* Whether we are optimizing. The default value of 2 means to remove
267 unneeded NOPs and swap branch instructions when possible. A value
268 of 1 means to not swap branches. A value of 0 means to always
270 static int mips_optimize
= 2;
272 /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is
273 equivalent to seeing no -g option at all. */
274 static int mips_debug
= 0;
276 /* The previous instruction. */
277 static struct mips_cl_insn prev_insn
;
279 /* The instruction before prev_insn. */
280 static struct mips_cl_insn prev_prev_insn
;
282 /* If we don't want information for prev_insn or prev_prev_insn, we
283 point the insn_mo field at this dummy integer. */
284 static const struct mips_opcode dummy_opcode
= { 0 };
286 /* Non-zero if prev_insn is valid. */
287 static int prev_insn_valid
;
289 /* The frag for the previous instruction. */
290 static struct frag
*prev_insn_frag
;
292 /* The offset into prev_insn_frag for the previous instruction. */
293 static long prev_insn_where
;
295 /* The reloc for the previous instruction, if any. */
296 static fixS
*prev_insn_fixp
;
298 /* Non-zero if the previous instruction was in a delay slot. */
299 static int prev_insn_is_delay_slot
;
301 /* Non-zero if the previous instruction was in a .set noreorder. */
302 static int prev_insn_unreordered
;
304 /* Non-zero if the previous previous instruction was in a .set
306 static int prev_prev_insn_unreordered
;
308 /* For ECOFF and ELF, relocations against symbols are done in two
309 parts, with a HI relocation and a LO relocation. Each relocation
310 has only 16 bits of space to store an addend. This means that in
311 order for the linker to handle carries correctly, it must be able
312 to locate both the HI and the LO relocation. This means that the
313 relocations must appear in order in the relocation table.
315 In order to implement this, we keep track of each unmatched HI
316 relocation. We then sort them so that they immediately precede the
317 corresponding LO relocation. */
322 struct mips_hi_fixup
*next
;
325 /* The section this fixup is in. */
329 /* The list of unmatched HI relocs. */
331 static struct mips_hi_fixup
*mips_hi_fixup_list
;
333 /* Since the MIPS does not have multiple forms of PC relative
334 instructions, we do not have to do relaxing as is done on other
335 platforms. However, we do have to handle GP relative addressing
336 correctly, which turns out to be a similar problem.
338 Every macro that refers to a symbol can occur in (at least) two
339 forms, one with GP relative addressing and one without. For
340 example, loading a global variable into a register generally uses
341 a macro instruction like this:
343 If i can be addressed off the GP register (this is true if it is in
344 the .sbss or .sdata section, or if it is known to be smaller than
345 the -G argument) this will generate the following instruction:
347 This instruction will use a GPREL reloc. If i can not be addressed
348 off the GP register, the following instruction sequence will be used:
351 In this case the first instruction will have a HI16 reloc, and the
352 second reloc will have a LO16 reloc. Both relocs will be against
355 The issue here is that we may not know whether i is GP addressable
356 until after we see the instruction that uses it. Therefore, we
357 want to be able to choose the final instruction sequence only at
358 the end of the assembly. This is similar to the way other
359 platforms choose the size of a PC relative instruction only at the
362 When generating position independent code we do not use GP
363 addressing in quite the same way, but the issue still arises as
364 external symbols and local symbols must be handled differently.
366 We handle these issues by actually generating both possible
367 instruction sequences. The longer one is put in a frag_var with
368 type rs_machine_dependent. We encode what to do with the frag in
369 the subtype field. We encode (1) the number of existing bytes to
370 replace, (2) the number of new bytes to use, (3) the offset from
371 the start of the existing bytes to the first reloc we must generate
372 (that is, the offset is applied from the start of the existing
373 bytes after they are replaced by the new bytes, if any), (4) the
374 offset from the start of the existing bytes to the second reloc,
375 (5) whether a third reloc is needed (the third reloc is always four
376 bytes after the second reloc), and (6) whether to warn if this
377 variant is used (this is sometimes needed if .set nomacro or .set
378 noat is in effect). All these numbers are reasonably small.
380 Generating two instruction sequences must be handled carefully to
381 ensure that delay slots are handled correctly. Fortunately, there
382 are a limited number of cases. When the second instruction
383 sequence is generated, append_insn is directed to maintain the
384 existing delay slot information, so it continues to apply to any
385 code after the second instruction sequence. This means that the
386 second instruction sequence must not impose any requirements not
387 required by the first instruction sequence.
389 These variant frags are then handled in functions called by the
390 machine independent code. md_estimate_size_before_relax returns
391 the final size of the frag. md_convert_frag sets up the final form
392 of the frag. tc_gen_reloc adjust the first reloc and adds a second
394 #define RELAX_ENCODE(old, new, reloc1, reloc2, reloc3, warn) \
398 | (((reloc1) + 64) << 9) \
399 | (((reloc2) + 64) << 2) \
400 | ((reloc3) ? (1 << 1) : 0) \
402 #define RELAX_OLD(i) (((i) >> 24) & 0xff)
403 #define RELAX_NEW(i) (((i) >> 16) & 0xff)
404 #define RELAX_RELOC1(i) ((bfd_vma)(((i) >> 9) & 0x7f) - 64)
405 #define RELAX_RELOC2(i) ((bfd_vma)(((i) >> 2) & 0x7f) - 64)
406 #define RELAX_RELOC3(i) (((i) >> 1) & 1)
407 #define RELAX_WARN(i) ((i) & 1)
409 /* Prototypes for static functions. */
412 #define internalError() \
413 as_fatal ("internal Error, line %d, %s", __LINE__, __FILE__)
415 #define internalError() as_fatal ("MIPS internal Error");
418 static int insn_uses_reg
PARAMS ((struct mips_cl_insn
*ip
,
419 unsigned int reg
, int fpr
));
420 static int reg_needs_delay
PARAMS ((int));
421 static void append_insn
PARAMS ((char *place
,
422 struct mips_cl_insn
* ip
,
424 bfd_reloc_code_real_type r
,
426 static void mips_no_prev_insn
PARAMS ((void));
427 static void mips_emit_delays
PARAMS ((void));
429 static void macro_build
PARAMS ((char *place
, int *counter
, expressionS
* ep
,
430 const char *name
, const char *fmt
,
433 static void macro_build ();
435 static void macro_build_lui
PARAMS ((char *place
, int *counter
,
436 expressionS
* ep
, int regnum
));
437 static void set_at
PARAMS ((int *counter
, int reg
, int unsignedp
));
438 static void check_absolute_expr
PARAMS ((struct mips_cl_insn
* ip
,
440 static void load_register
PARAMS ((int *, int, expressionS
*, int));
441 static void load_address
PARAMS ((int *counter
, int reg
, expressionS
*ep
));
442 static void macro
PARAMS ((struct mips_cl_insn
* ip
));
443 #ifdef LOSING_COMPILER
444 static void macro2
PARAMS ((struct mips_cl_insn
* ip
));
446 static void mips_ip
PARAMS ((char *str
, struct mips_cl_insn
* ip
));
447 static int my_getSmallExpression
PARAMS ((expressionS
* ep
, char *str
));
448 static void my_getExpression
PARAMS ((expressionS
* ep
, char *str
));
449 static symbolS
*get_symbol
PARAMS ((void));
450 static void mips_align
PARAMS ((int to
, int fill
, symbolS
*label
));
451 static void s_align
PARAMS ((int));
452 static void s_change_sec
PARAMS ((int));
453 static void s_cons
PARAMS ((int));
454 static void s_float_cons
PARAMS ((int));
455 static void s_mips_globl
PARAMS ((int));
456 static void s_option
PARAMS ((int));
457 static void s_mipsset
PARAMS ((int));
458 static void s_abicalls
PARAMS ((int));
459 static void s_cpload
PARAMS ((int));
460 static void s_cprestore
PARAMS ((int));
461 static void s_gpword
PARAMS ((int));
462 static void s_cpadd
PARAMS ((int));
463 static void md_obj_begin
PARAMS ((void));
464 static void md_obj_end
PARAMS ((void));
465 static long get_number
PARAMS ((void));
466 static void s_ent
PARAMS ((int));
467 static void s_mipsend
PARAMS ((int));
468 static void s_file
PARAMS ((int));
472 The following pseudo-ops from the Kane and Heinrich MIPS book
473 should be defined here, but are currently unsupported: .alias,
474 .galive, .gjaldef, .gjrlive, .livereg, .noalias.
476 The following pseudo-ops from the Kane and Heinrich MIPS book are
477 specific to the type of debugging information being generated, and
478 should be defined by the object format: .aent, .begin, .bend,
479 .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp,
482 The following pseudo-ops from the Kane and Heinrich MIPS book are
483 not MIPS CPU specific, but are also not specific to the object file
484 format. This file is probably the best place to define them, but
485 they are not currently supported: .asm0, .endr, .lab, .repeat,
486 .struct, .weakext. */
488 static const pseudo_typeS mips_pseudo_table
[] =
490 /* MIPS specific pseudo-ops. */
491 {"option", s_option
, 0},
492 {"set", s_mipsset
, 0},
493 {"rdata", s_change_sec
, 'r'},
494 {"sdata", s_change_sec
, 's'},
495 {"livereg", s_ignore
, 0},
496 {"abicalls", s_abicalls
, 0},
497 {"cpload", s_cpload
, 0},
498 {"cprestore", s_cprestore
, 0},
499 {"gpword", s_gpword
, 0},
500 {"cpadd", s_cpadd
, 0},
502 /* Relatively generic pseudo-ops that happen to be used on MIPS
504 {"asciiz", stringer
, 1},
505 {"bss", s_change_sec
, 'b'},
508 {"dword", s_cons
, 3},
510 /* These pseudo-ops are defined in read.c, but must be overridden
511 here for one reason or another. */
512 {"align", s_align
, 0},
514 {"data", s_change_sec
, 'd'},
515 {"double", s_float_cons
, 'd'},
516 {"float", s_float_cons
, 'f'},
517 {"globl", s_mips_globl
, 0},
518 {"global", s_mips_globl
, 0},
519 {"hword", s_cons
, 1},
524 {"short", s_cons
, 1},
525 {"single", s_float_cons
, 'f'},
526 {"text", s_change_sec
, 't'},
531 static const pseudo_typeS mips_nonecoff_pseudo_table
[] = {
532 /* These pseudo-ops should be defined by the object file format.
533 However, a.out doesn't support them, so we have versions here. */
535 {"bgnb", s_ignore
, 0},
536 {"end", s_mipsend
, 0},
537 {"endb", s_ignore
, 0},
540 {"fmask", s_ignore
, 'F'},
541 {"frame", s_ignore
, 0},
542 {"loc", s_ignore
, 0},
543 {"mask", s_ignore
, 'R'},
544 {"verstamp", s_ignore
, 0},
548 extern void pop_insert
PARAMS ((const pseudo_typeS
*));
553 pop_insert (mips_pseudo_table
);
554 if (! ECOFF_DEBUGGING
)
555 pop_insert (mips_nonecoff_pseudo_table
);
558 static char *expr_end
;
560 /* Expressions which appear in instructions. These are set by
563 static expressionS imm_expr
;
564 static expressionS offset_expr
;
566 /* Relocs associated with imm_expr and offset_expr. */
568 static bfd_reloc_code_real_type imm_reloc
;
569 static bfd_reloc_code_real_type offset_reloc
;
571 /* This is set by mips_ip if imm_reloc is an unmatched HI16_S reloc. */
573 static boolean imm_unmatched_hi
;
576 * This function is called once, at assembler startup time. It should
577 * set up all the tables, etc. that the MD part of the assembler will need.
583 register const char *retval
= NULL
;
584 register unsigned int i
= 0;
592 if (strcmp (cpu
+ (sizeof TARGET_CPU
) - 3, "el") == 0)
594 a
= xmalloc (sizeof TARGET_CPU
);
595 strcpy (a
, TARGET_CPU
);
596 a
[(sizeof TARGET_CPU
) - 3] = '\0';
600 if (strcmp (cpu
, "mips") == 0)
606 else if (strcmp (cpu
, "r6000") == 0
607 || strcmp (cpu
, "mips2") == 0)
613 else if (strcmp (cpu
, "mips64") == 0
614 || strcmp (cpu
, "r4000") == 0
615 || strcmp (cpu
, "mips3") == 0)
621 else if (strcmp (cpu
, "r4400") == 0)
627 else if (strcmp (cpu
, "mips64orion") == 0
628 || strcmp (cpu
, "r4600") == 0)
634 else if (strcmp (cpu
, "r4650") == 0)
642 else if (strcmp (cpu
, "mips64vr4300") == 0)
648 else if (strcmp (cpu
, "mips64vr4100") == 0)
656 else if (strcmp (cpu
, "r4010") == 0)
664 else if (strcmp (cpu
, "r5000") == 0
665 || strcmp (cpu
, "mips64vr5000") == 0)
671 else if (strcmp (cpu
, "r8000") == 0
672 || strcmp (cpu
, "mips4") == 0)
678 else if (strcmp (cpu
, "r10000") == 0)
704 if (mips_4650
|| mips_4010
|| mips_4100
|| mips_cpu
== 4300)
709 if (mips_cpu
== 4300)
714 if (mips_isa
< 2 && mips_trap
)
715 as_bad ("trap exception not supported at ISA 1");
720 ok
= bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, 3000);
723 ok
= bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, 6000);
726 ok
= bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, 4000);
729 ok
= bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, 8000);
733 as_warn ("Could not set architecture and machine");
735 file_mips_isa
= mips_isa
;
737 op_hash
= hash_new ();
739 for (i
= 0; i
< NUMOPCODES
;)
741 const char *name
= mips_opcodes
[i
].name
;
743 retval
= hash_insert (op_hash
, name
, (PTR
) &mips_opcodes
[i
]);
746 fprintf (stderr
, "internal error: can't hash `%s': %s\n",
747 mips_opcodes
[i
].name
, retval
);
748 as_fatal ("Broken assembler. No assembly attempted.");
752 if (mips_opcodes
[i
].pinfo
!= INSN_MACRO
753 && ((mips_opcodes
[i
].match
& mips_opcodes
[i
].mask
)
754 != mips_opcodes
[i
].match
))
756 fprintf (stderr
, "internal error: bad opcode: `%s' \"%s\"\n",
757 mips_opcodes
[i
].name
, mips_opcodes
[i
].args
);
758 as_fatal ("Broken assembler. No assembly attempted.");
762 while ((i
< NUMOPCODES
) && !strcmp (mips_opcodes
[i
].name
, name
));
765 mips_no_prev_insn ();
773 /* set the default alignment for the text section (2**2) */
774 record_alignment (text_section
, 2);
776 if (USE_GLOBAL_POINTER_OPT
)
777 bfd_set_gp_size (stdoutput
, g_switch_value
);
779 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
781 /* Sections must be aligned to 16 byte boundaries. */
782 (void) bfd_set_section_alignment (stdoutput
, text_section
, 4);
783 (void) bfd_set_section_alignment (stdoutput
, data_section
, 4);
784 (void) bfd_set_section_alignment (stdoutput
, bss_section
, 4);
786 /* Create a .reginfo section for register masks and a .mdebug
787 section for debugging information. */
798 sec
= subseg_new (".reginfo", (subsegT
) 0);
800 /* The ABI says this section should be loaded so that the
801 running program can access it. */
802 (void) bfd_set_section_flags (stdoutput
, sec
,
803 (SEC_ALLOC
| SEC_LOAD
804 | SEC_READONLY
| SEC_DATA
));
805 (void) bfd_set_section_alignment (stdoutput
, sec
, 2);
808 mips_regmask_frag
= frag_more (sizeof (Elf32_External_RegInfo
));
813 /* The 64-bit ABI uses a .MIPS.options section rather than
815 sec
= subseg_new (".MIPS.options", (subsegT
) 0);
816 (void) bfd_set_section_flags (stdoutput
, sec
,
817 (SEC_ALLOC
| SEC_LOAD
818 | SEC_READONLY
| SEC_DATA
));
819 (void) bfd_set_section_alignment (stdoutput
, sec
, 3);
822 /* Set up the option header. */
824 Elf_Internal_Options opthdr
;
827 opthdr
.kind
= ODK_REGINFO
;
828 opthdr
.size
= (sizeof (Elf_External_Options
)
829 + sizeof (Elf64_External_RegInfo
));
832 f
= frag_more (sizeof (Elf_External_Options
));
833 bfd_mips_elf_swap_options_out (stdoutput
, &opthdr
,
834 (Elf_External_Options
*) f
);
836 mips_regmask_frag
= frag_more (sizeof (Elf64_External_RegInfo
));
843 sec
= subseg_new (".mdebug", (subsegT
) 0);
844 (void) bfd_set_section_flags (stdoutput
, sec
,
845 SEC_HAS_CONTENTS
| SEC_READONLY
);
846 (void) bfd_set_section_alignment (stdoutput
, sec
, 2);
849 subseg_set (seg
, subseg
);
853 if (! ECOFF_DEBUGGING
)
860 if (! ECOFF_DEBUGGING
)
868 struct mips_cl_insn insn
;
870 imm_expr
.X_op
= O_absent
;
871 imm_reloc
= BFD_RELOC_UNUSED
;
872 imm_unmatched_hi
= false;
873 offset_expr
.X_op
= O_absent
;
874 offset_reloc
= BFD_RELOC_UNUSED
;
876 mips_ip (str
, &insn
);
879 as_bad ("%s `%s'", insn_error
, str
);
882 if (insn
.insn_mo
->pinfo
== INSN_MACRO
)
888 if (imm_expr
.X_op
!= O_absent
)
889 append_insn ((char *) NULL
, &insn
, &imm_expr
, imm_reloc
,
891 else if (offset_expr
.X_op
!= O_absent
)
892 append_insn ((char *) NULL
, &insn
, &offset_expr
, offset_reloc
, false);
894 append_insn ((char *) NULL
, &insn
, NULL
, BFD_RELOC_UNUSED
, false);
898 /* See whether instruction IP reads register REG. If FPR is non-zero,
899 REG is a floating point register. */
902 insn_uses_reg (ip
, reg
, fpr
)
903 struct mips_cl_insn
*ip
;
907 /* Don't report on general register 0, since it never changes. */
908 if (! fpr
&& reg
== 0)
913 /* If we are called with either $f0 or $f1, we must check $f0.
914 This is not optimal, because it will introduce an unnecessary
915 NOP between "lwc1 $f0" and "swc1 $f1". To fix this we would
916 need to distinguish reading both $f0 and $f1 or just one of
917 them. Note that we don't have to check the other way,
918 because there is no instruction that sets both $f0 and $f1
919 and requires a delay. */
920 if ((ip
->insn_mo
->pinfo
& INSN_READ_FPR_S
)
921 && (((ip
->insn_opcode
>> OP_SH_FS
) & OP_MASK_FS
)
922 == (reg
&~ (unsigned) 1)))
924 if ((ip
->insn_mo
->pinfo
& INSN_READ_FPR_T
)
925 && (((ip
->insn_opcode
>> OP_SH_FT
) & OP_MASK_FT
)
926 == (reg
&~ (unsigned) 1)))
931 if ((ip
->insn_mo
->pinfo
& INSN_READ_GPR_S
)
932 && ((ip
->insn_opcode
>> OP_SH_RS
) & OP_MASK_RS
) == reg
)
934 if ((ip
->insn_mo
->pinfo
& INSN_READ_GPR_T
)
935 && ((ip
->insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
) == reg
)
942 /* This function returns true if modifying a register requires a
946 reg_needs_delay (reg
)
949 unsigned long prev_pinfo
;
951 prev_pinfo
= prev_insn
.insn_mo
->pinfo
;
954 && ((prev_pinfo
& INSN_LOAD_COPROC_DELAY
)
956 && (prev_pinfo
& INSN_LOAD_MEMORY_DELAY
))))
958 /* A load from a coprocessor or from memory. All load
959 delays delay the use of general register rt for one
960 instruction on the r3000. The r6000 and r4000 use
962 know (prev_pinfo
& INSN_WRITE_GPR_T
);
963 if (reg
== ((prev_insn
.insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
))
970 /* Output an instruction. PLACE is where to put the instruction; if
971 it is NULL, this uses frag_more to get room. IP is the instruction
972 information. ADDRESS_EXPR is an operand of the instruction to be
973 used with RELOC_TYPE. */
976 append_insn (place
, ip
, address_expr
, reloc_type
, unmatched_hi
)
978 struct mips_cl_insn
*ip
;
979 expressionS
*address_expr
;
980 bfd_reloc_code_real_type reloc_type
;
981 boolean unmatched_hi
;
983 register unsigned long prev_pinfo
, pinfo
;
988 prev_pinfo
= prev_insn
.insn_mo
->pinfo
;
989 pinfo
= ip
->insn_mo
->pinfo
;
991 if (place
== NULL
&& ! mips_noreorder
)
993 /* If the previous insn required any delay slots, see if we need
994 to insert a NOP or two. There are eight kinds of possible
995 hazards, of which an instruction can have at most one type.
996 (1) a load from memory delay
997 (2) a load from a coprocessor delay
998 (3) an unconditional branch delay
999 (4) a conditional branch delay
1000 (5) a move to coprocessor register delay
1001 (6) a load coprocessor register from memory delay
1002 (7) a coprocessor condition code delay
1003 (8) a HI/LO special register delay
1005 There are a lot of optimizations we could do that we don't.
1006 In particular, we do not, in general, reorder instructions.
1007 If you use gcc with optimization, it will reorder
1008 instructions and generally do much more optimization then we
1009 do here; repeating all that work in the assembler would only
1010 benefit hand written assembly code, and does not seem worth
1013 /* This is how a NOP is emitted. */
1014 #define emit_nop() md_number_to_chars (frag_more (4), 0, 4)
1016 /* The previous insn might require a delay slot, depending upon
1017 the contents of the current insn. */
1019 && (((prev_pinfo
& INSN_LOAD_COPROC_DELAY
)
1020 && ! cop_interlocks
)
1022 && (prev_pinfo
& INSN_LOAD_MEMORY_DELAY
))))
1024 /* A load from a coprocessor or from memory. All load
1025 delays delay the use of general register rt for one
1026 instruction on the r3000. The r6000 and r4000 use
1028 know (prev_pinfo
& INSN_WRITE_GPR_T
);
1029 if (mips_optimize
== 0
1030 || insn_uses_reg (ip
,
1031 ((prev_insn
.insn_opcode
>> OP_SH_RT
)
1036 else if (mips_isa
< 4
1037 && (((prev_pinfo
& INSN_COPROC_MOVE_DELAY
)
1038 && ! cop_interlocks
)
1040 && (prev_pinfo
& INSN_COPROC_MEMORY_DELAY
))))
1042 /* A generic coprocessor delay. The previous instruction
1043 modified a coprocessor general or control register. If
1044 it modified a control register, we need to avoid any
1045 coprocessor instruction (this is probably not always
1046 required, but it sometimes is). If it modified a general
1047 register, we avoid using that register.
1049 On the r6000 and r4000 loading a coprocessor register
1050 from memory is interlocked, and does not require a delay.
1052 This case is not handled very well. There is no special
1053 knowledge of CP0 handling, and the coprocessors other
1054 than the floating point unit are not distinguished at
1056 if (prev_pinfo
& INSN_WRITE_FPR_T
)
1058 if (mips_optimize
== 0
1059 || insn_uses_reg (ip
,
1060 ((prev_insn
.insn_opcode
>> OP_SH_FT
)
1065 else if (prev_pinfo
& INSN_WRITE_FPR_S
)
1067 if (mips_optimize
== 0
1068 || insn_uses_reg (ip
,
1069 ((prev_insn
.insn_opcode
>> OP_SH_FS
)
1076 /* We don't know exactly what the previous instruction
1077 does. If the current instruction uses a coprocessor
1078 register, we must insert a NOP. If previous
1079 instruction may set the condition codes, and the
1080 current instruction uses them, we must insert two
1082 if (mips_optimize
== 0
1083 || ((prev_pinfo
& INSN_WRITE_COND_CODE
)
1084 && (pinfo
& INSN_READ_COND_CODE
)))
1086 else if (pinfo
& INSN_COP
)
1090 else if (mips_isa
< 4
1091 && (prev_pinfo
& INSN_WRITE_COND_CODE
)
1092 && ! cop_interlocks
)
1094 /* The previous instruction sets the coprocessor condition
1095 codes, but does not require a general coprocessor delay
1096 (this means it is a floating point comparison
1097 instruction). If this instruction uses the condition
1098 codes, we need to insert a single NOP. */
1099 if (mips_optimize
== 0
1100 || (pinfo
& INSN_READ_COND_CODE
))
1103 else if (prev_pinfo
& INSN_READ_LO
)
1105 /* The previous instruction reads the LO register; if the
1106 current instruction writes to the LO register, we must
1107 insert two NOPS. Some newer processors have interlocks. */
1109 && (mips_optimize
== 0
1110 || (pinfo
& INSN_WRITE_LO
)))
1113 else if (prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
1115 /* The previous instruction reads the HI register; if the
1116 current instruction writes to the HI register, we must
1117 insert a NOP. Some newer processors have interlocks. */
1119 && (mips_optimize
== 0
1120 || (pinfo
& INSN_WRITE_HI
)))
1124 /* There are two cases which require two intervening
1125 instructions: 1) setting the condition codes using a move to
1126 coprocessor instruction which requires a general coprocessor
1127 delay and then reading the condition codes 2) reading the HI
1128 or LO register and then writing to it (except on processors
1129 which have interlocks). If we are not already emitting a NOP
1130 instruction, we must check for these cases compared to the
1131 instruction previous to the previous instruction. */
1134 && (prev_prev_insn
.insn_mo
->pinfo
& INSN_COPROC_MOVE_DELAY
)
1135 && (prev_prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
)
1136 && (pinfo
& INSN_READ_COND_CODE
)
1137 && ! cop_interlocks
)
1138 || ((prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
)
1139 && (pinfo
& INSN_WRITE_LO
)
1141 || ((prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
1142 && (pinfo
& INSN_WRITE_HI
)
1146 /* If we are being given a nop instruction, don't bother with
1147 one of the nops we would otherwise output. This will only
1148 happen when a nop instruction is used with mips_optimize set
1150 if (nops
> 0 && ip
->insn_opcode
== 0)
1153 /* Now emit the right number of NOP instructions. */
1157 unsigned long old_frag_offset
;
1160 old_frag
= frag_now
;
1161 old_frag_offset
= frag_now_fix ();
1163 for (i
= 0; i
< nops
; i
++)
1168 listing_prev_line ();
1169 /* We may be at the start of a variant frag. In case we
1170 are, make sure there is enough space for the frag
1171 after the frags created by listing_prev_line. The
1172 argument to frag_grow here must be at least as large
1173 as the argument to all other calls to frag_grow in
1174 this file. We don't have to worry about being in the
1175 middle of a variant frag, because the variants insert
1176 all needed nop instructions themselves. */
1180 if (insn_label
!= NULL
)
1182 assert (S_GET_SEGMENT (insn_label
) == now_seg
);
1183 insn_label
->sy_frag
= frag_now
;
1184 S_SET_VALUE (insn_label
, (valueT
) frag_now_fix ());
1187 #ifndef NO_ECOFF_DEBUGGING
1188 if (ECOFF_DEBUGGING
)
1189 ecoff_fix_loc (old_frag
, old_frag_offset
);
1199 if (address_expr
!= NULL
)
1201 if (address_expr
->X_op
== O_constant
)
1206 ip
->insn_opcode
|= address_expr
->X_add_number
;
1209 case BFD_RELOC_LO16
:
1210 ip
->insn_opcode
|= address_expr
->X_add_number
& 0xffff;
1213 case BFD_RELOC_MIPS_JMP
:
1214 case BFD_RELOC_16_PCREL_S2
:
1223 assert (reloc_type
!= BFD_RELOC_UNUSED
);
1225 /* Don't generate a reloc if we are writing into a variant
1229 fixp
= fix_new_exp (frag_now
, f
- frag_now
->fr_literal
, 4,
1231 reloc_type
== BFD_RELOC_16_PCREL_S2
,
1235 struct mips_hi_fixup
*hi_fixup
;
1237 assert (reloc_type
== BFD_RELOC_HI16_S
);
1238 hi_fixup
= ((struct mips_hi_fixup
*)
1239 xmalloc (sizeof (struct mips_hi_fixup
)));
1240 hi_fixup
->fixp
= fixp
;
1241 hi_fixup
->seg
= now_seg
;
1242 hi_fixup
->next
= mips_hi_fixup_list
;
1243 mips_hi_fixup_list
= hi_fixup
;
1249 md_number_to_chars (f
, ip
->insn_opcode
, 4);
1251 /* Update the register mask information. */
1252 if (pinfo
& INSN_WRITE_GPR_D
)
1253 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
);
1254 if ((pinfo
& (INSN_WRITE_GPR_T
| INSN_READ_GPR_T
)) != 0)
1255 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
);
1256 if (pinfo
& INSN_READ_GPR_S
)
1257 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> OP_SH_RS
) & OP_MASK_RS
);
1258 if (pinfo
& INSN_WRITE_GPR_31
)
1259 mips_gprmask
|= 1 << 31;
1260 if (pinfo
& INSN_WRITE_FPR_D
)
1261 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FD
) & OP_MASK_FD
);
1262 if ((pinfo
& (INSN_WRITE_FPR_S
| INSN_READ_FPR_S
)) != 0)
1263 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FS
) & OP_MASK_FS
);
1264 if ((pinfo
& (INSN_WRITE_FPR_T
| INSN_READ_FPR_T
)) != 0)
1265 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FT
) & OP_MASK_FT
);
1266 if ((pinfo
& INSN_READ_FPR_R
) != 0)
1267 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FR
) & OP_MASK_FR
);
1268 if (pinfo
& INSN_COP
)
1270 /* We don't keep enough information to sort these cases out. */
1272 /* Never set the bit for $0, which is always zero. */
1273 mips_gprmask
&=~ 1 << 0;
1275 if (place
== NULL
&& ! mips_noreorder
)
1277 /* Filling the branch delay slot is more complex. We try to
1278 switch the branch with the previous instruction, which we can
1279 do if the previous instruction does not set up a condition
1280 that the branch tests and if the branch is not itself the
1281 target of any branch. */
1282 if ((pinfo
& INSN_UNCOND_BRANCH_DELAY
)
1283 || (pinfo
& INSN_COND_BRANCH_DELAY
))
1285 if (mips_optimize
< 2
1286 /* If we have seen .set volatile or .set nomove, don't
1289 /* If we had to emit any NOP instructions, then we
1290 already know we can not swap. */
1292 /* If we don't even know the previous insn, we can not
1294 || ! prev_insn_valid
1295 /* If the previous insn is already in a branch delay
1296 slot, then we can not swap. */
1297 || prev_insn_is_delay_slot
1298 /* If the previous previous insn was in a .set
1299 noreorder, we can't swap. Actually, the MIPS
1300 assembler will swap in this situation. However, gcc
1301 configured -with-gnu-as will generate code like
1307 in which we can not swap the bne and INSN. If gcc is
1308 not configured -with-gnu-as, it does not output the
1309 .set pseudo-ops. We don't have to check
1310 prev_insn_unreordered, because prev_insn_valid will
1311 be 0 in that case. We don't want to use
1312 prev_prev_insn_valid, because we do want to be able
1313 to swap at the start of a function. */
1314 || prev_prev_insn_unreordered
1315 /* If the branch is itself the target of a branch, we
1316 can not swap. We cheat on this; all we check for is
1317 whether there is a label on this instruction. If
1318 there are any branches to anything other than a
1319 label, users must use .set noreorder. */
1320 || insn_label
!= NULL
1321 /* If the previous instruction is in a variant frag, we
1322 can not do the swap. */
1323 || prev_insn_frag
->fr_type
== rs_machine_dependent
1324 /* If the branch reads the condition codes, we don't
1325 even try to swap, because in the sequence
1330 we can not swap, and I don't feel like handling that
1333 && (pinfo
& INSN_READ_COND_CODE
))
1334 /* We can not swap with an instruction that requires a
1335 delay slot, becase the target of the branch might
1336 interfere with that instruction. */
1339 & (INSN_LOAD_COPROC_DELAY
1340 | INSN_COPROC_MOVE_DELAY
1341 | INSN_WRITE_COND_CODE
)))
1348 & (INSN_LOAD_MEMORY_DELAY
1349 | INSN_COPROC_MEMORY_DELAY
)))
1350 /* We can not swap with a branch instruction. */
1352 & (INSN_UNCOND_BRANCH_DELAY
1353 | INSN_COND_BRANCH_DELAY
1354 | INSN_COND_BRANCH_LIKELY
))
1355 /* We do not swap with a trap instruction, since it
1356 complicates trap handlers to have the trap
1357 instruction be in a delay slot. */
1358 || (prev_pinfo
& INSN_TRAP
)
1359 /* If the branch reads a register that the previous
1360 instruction sets, we can not swap. */
1361 || ((prev_pinfo
& INSN_WRITE_GPR_T
)
1362 && insn_uses_reg (ip
,
1363 ((prev_insn
.insn_opcode
>> OP_SH_RT
)
1366 || ((prev_pinfo
& INSN_WRITE_GPR_D
)
1367 && insn_uses_reg (ip
,
1368 ((prev_insn
.insn_opcode
>> OP_SH_RD
)
1371 /* If the branch writes a register that the previous
1372 instruction sets, we can not swap (we know that
1373 branches write only to RD or to $31). */
1374 || ((prev_pinfo
& INSN_WRITE_GPR_T
)
1375 && (((pinfo
& INSN_WRITE_GPR_D
)
1376 && (((prev_insn
.insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
)
1377 == ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)))
1378 || ((pinfo
& INSN_WRITE_GPR_31
)
1379 && (((prev_insn
.insn_opcode
>> OP_SH_RT
)
1382 || ((prev_pinfo
& INSN_WRITE_GPR_D
)
1383 && (((pinfo
& INSN_WRITE_GPR_D
)
1384 && (((prev_insn
.insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)
1385 == ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)))
1386 || ((pinfo
& INSN_WRITE_GPR_31
)
1387 && (((prev_insn
.insn_opcode
>> OP_SH_RD
)
1390 /* If the branch writes a register that the previous
1391 instruction reads, we can not swap (we know that
1392 branches only write to RD or to $31). */
1393 || ((pinfo
& INSN_WRITE_GPR_D
)
1394 && insn_uses_reg (&prev_insn
,
1395 ((ip
->insn_opcode
>> OP_SH_RD
)
1398 || ((pinfo
& INSN_WRITE_GPR_31
)
1399 && insn_uses_reg (&prev_insn
, 31, 0))
1400 /* If we are generating embedded PIC code, the branch
1401 might be expanded into a sequence which uses $at, so
1402 we can't swap with an instruction which reads it. */
1403 || (mips_pic
== EMBEDDED_PIC
1404 && insn_uses_reg (&prev_insn
, AT
, 0))
1405 /* If the previous previous instruction has a load
1406 delay, and sets a register that the branch reads, we
1409 && ((prev_prev_insn
.insn_mo
->pinfo
& INSN_LOAD_COPROC_DELAY
)
1411 && (prev_prev_insn
.insn_mo
->pinfo
1412 & INSN_LOAD_MEMORY_DELAY
)))
1413 && insn_uses_reg (ip
,
1414 ((prev_prev_insn
.insn_opcode
>> OP_SH_RT
)
1417 /* If one instruction sets a condition code and the
1418 other one uses a condition code, we can not swap. */
1419 || ((pinfo
& INSN_READ_COND_CODE
)
1420 && (prev_pinfo
& INSN_WRITE_COND_CODE
))
1421 || ((pinfo
& INSN_WRITE_COND_CODE
)
1422 && (prev_pinfo
& INSN_READ_COND_CODE
)))
1424 /* We could do even better for unconditional branches to
1425 portions of this object file; we could pick up the
1426 instruction at the destination, put it in the delay
1427 slot, and bump the destination address. */
1429 /* Update the previous insn information. */
1430 prev_prev_insn
= *ip
;
1431 prev_insn
.insn_mo
= &dummy_opcode
;
1438 /* It looks like we can actually do the swap. */
1439 prev_f
= prev_insn_frag
->fr_literal
+ prev_insn_where
;
1440 memcpy (temp
, prev_f
, 4);
1441 memcpy (prev_f
, f
, 4);
1442 memcpy (f
, temp
, 4);
1445 prev_insn_fixp
->fx_frag
= frag_now
;
1446 prev_insn_fixp
->fx_where
= f
- frag_now
->fr_literal
;
1450 fixp
->fx_frag
= prev_insn_frag
;
1451 fixp
->fx_where
= prev_insn_where
;
1453 /* Update the previous insn information; leave prev_insn
1455 prev_prev_insn
= *ip
;
1457 prev_insn_is_delay_slot
= 1;
1459 /* If that was an unconditional branch, forget the previous
1460 insn information. */
1461 if (pinfo
& INSN_UNCOND_BRANCH_DELAY
)
1463 prev_prev_insn
.insn_mo
= &dummy_opcode
;
1464 prev_insn
.insn_mo
= &dummy_opcode
;
1467 else if (pinfo
& INSN_COND_BRANCH_LIKELY
)
1469 /* We don't yet optimize a branch likely. What we should do
1470 is look at the target, copy the instruction found there
1471 into the delay slot, and increment the branch to jump to
1472 the next instruction. */
1474 /* Update the previous insn information. */
1475 prev_prev_insn
= *ip
;
1476 prev_insn
.insn_mo
= &dummy_opcode
;
1480 /* Update the previous insn information. */
1482 prev_prev_insn
.insn_mo
= &dummy_opcode
;
1484 prev_prev_insn
= prev_insn
;
1487 /* Any time we see a branch, we always fill the delay slot
1488 immediately; since this insn is not a branch, we know it
1489 is not in a delay slot. */
1490 prev_insn_is_delay_slot
= 0;
1493 prev_prev_insn_unreordered
= prev_insn_unreordered
;
1494 prev_insn_unreordered
= 0;
1495 prev_insn_frag
= frag_now
;
1496 prev_insn_where
= f
- frag_now
->fr_literal
;
1497 prev_insn_fixp
= fixp
;
1498 prev_insn_valid
= 1;
1501 /* We just output an insn, so the next one doesn't have a label. */
1505 /* This function forgets that there was any previous instruction or
1509 mips_no_prev_insn ()
1511 prev_insn
.insn_mo
= &dummy_opcode
;
1512 prev_prev_insn
.insn_mo
= &dummy_opcode
;
1513 prev_insn_valid
= 0;
1514 prev_insn_is_delay_slot
= 0;
1515 prev_insn_unreordered
= 0;
1516 prev_prev_insn_unreordered
= 0;
1520 /* This function must be called whenever we turn on noreorder or emit
1521 something other than instructions. It inserts any NOPS which might
1522 be needed by the previous instruction, and clears the information
1523 kept for the previous instructions. */
1528 if (! mips_noreorder
)
1534 && (! cop_interlocks
1535 && (prev_insn
.insn_mo
->pinfo
1536 & (INSN_LOAD_COPROC_DELAY
1537 | INSN_COPROC_MOVE_DELAY
1538 | INSN_WRITE_COND_CODE
))))
1540 && (prev_insn
.insn_mo
->pinfo
1544 && (prev_insn
.insn_mo
->pinfo
1545 & (INSN_LOAD_MEMORY_DELAY
1546 | INSN_COPROC_MEMORY_DELAY
))))
1550 && (! cop_interlocks
1551 && prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
))
1553 && ((prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
1554 || (prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
))))
1557 else if ((mips_isa
< 4
1558 && (! cop_interlocks
1559 && prev_prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
))
1561 && ((prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
1562 || (prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
))))
1567 if (insn_label
!= NULL
)
1569 assert (S_GET_SEGMENT (insn_label
) == now_seg
);
1570 insn_label
->sy_frag
= frag_now
;
1571 S_SET_VALUE (insn_label
, (valueT
) frag_now_fix ());
1576 mips_no_prev_insn ();
1579 /* Build an instruction created by a macro expansion. This is passed
1580 a pointer to the count of instructions created so far, an
1581 expression, the name of the instruction to build, an operand format
1582 string, and corresponding arguments. */
1586 macro_build (char *place
,
1594 macro_build (place
, counter
, ep
, name
, fmt
, va_alist
)
1603 struct mips_cl_insn insn
;
1604 bfd_reloc_code_real_type r
;
1608 va_start (args
, fmt
);
1614 * If the macro is about to expand into a second instruction,
1615 * print a warning if needed. We need to pass ip as a parameter
1616 * to generate a better warning message here...
1618 if (mips_warn_about_macros
&& place
== NULL
&& *counter
== 1)
1619 as_warn ("Macro instruction expanded into multiple instructions");
1622 *counter
+= 1; /* bump instruction counter */
1624 r
= BFD_RELOC_UNUSED
;
1625 insn
.insn_mo
= (struct mips_opcode
*) hash_find (op_hash
, name
);
1626 assert (insn
.insn_mo
);
1627 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
1629 while (strcmp (fmt
, insn
.insn_mo
->args
) != 0
1630 || insn
.insn_mo
->pinfo
== INSN_MACRO
1631 || ((insn
.insn_mo
->pinfo
& INSN_ISA
) == INSN_ISA2
1633 || ((insn
.insn_mo
->pinfo
& INSN_ISA
) == INSN_ISA3
1635 || ((insn
.insn_mo
->pinfo
& INSN_ISA
) == INSN_ISA4
1637 || ((insn
.insn_mo
->pinfo
& INSN_ISA
) == INSN_4650
1639 || ((insn
.insn_mo
->pinfo
& INSN_ISA
) == INSN_4010
1641 || ((insn
.insn_mo
->pinfo
& INSN_ISA
) == INSN_4100
1645 assert (insn
.insn_mo
->name
);
1646 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
1648 insn
.insn_opcode
= insn
.insn_mo
->match
;
1664 insn
.insn_opcode
|= va_arg (args
, int) << 16;
1670 insn
.insn_opcode
|= va_arg (args
, int) << 16;
1675 insn
.insn_opcode
|= va_arg (args
, int) << 11;
1680 insn
.insn_opcode
|= va_arg (args
, int) << 11;
1687 insn
.insn_opcode
|= va_arg (args
, int) << 6;
1691 insn
.insn_opcode
|= va_arg (args
, int) << 6;
1695 insn
.insn_opcode
|= va_arg (args
, int) << 6;
1702 insn
.insn_opcode
|= va_arg (args
, int) << 21;
1708 r
= (bfd_reloc_code_real_type
) va_arg (args
, int);
1709 assert (r
== BFD_RELOC_MIPS_GPREL
1710 || r
== BFD_RELOC_MIPS_LITERAL
1711 || r
== BFD_RELOC_LO16
1712 || r
== BFD_RELOC_MIPS_GOT16
1713 || r
== BFD_RELOC_MIPS_CALL16
1714 || r
== BFD_RELOC_MIPS_GOT_LO16
1715 || r
== BFD_RELOC_MIPS_CALL_LO16
1716 || (ep
->X_op
== O_subtract
1717 && now_seg
== text_section
1718 && r
== BFD_RELOC_PCREL_LO16
));
1722 r
= (bfd_reloc_code_real_type
) va_arg (args
, int);
1724 && (ep
->X_op
== O_constant
1725 || (ep
->X_op
== O_symbol
1726 && (r
== BFD_RELOC_HI16_S
1727 || r
== BFD_RELOC_HI16
1728 || r
== BFD_RELOC_MIPS_GOT_HI16
1729 || r
== BFD_RELOC_MIPS_CALL_HI16
))
1730 || (ep
->X_op
== O_subtract
1731 && now_seg
== text_section
1732 && r
== BFD_RELOC_PCREL_HI16_S
)));
1733 if (ep
->X_op
== O_constant
)
1735 insn
.insn_opcode
|= (ep
->X_add_number
>> 16) & 0xffff;
1737 r
= BFD_RELOC_UNUSED
;
1742 assert (ep
!= NULL
);
1744 * This allows macro() to pass an immediate expression for
1745 * creating short branches without creating a symbol.
1746 * Note that the expression still might come from the assembly
1747 * input, in which case the value is not checked for range nor
1748 * is a relocation entry generated (yuck).
1750 if (ep
->X_op
== O_constant
)
1752 insn
.insn_opcode
|= (ep
->X_add_number
>> 2) & 0xffff;
1756 r
= BFD_RELOC_16_PCREL_S2
;
1760 assert (ep
!= NULL
);
1761 r
= BFD_RELOC_MIPS_JMP
;
1770 assert (r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
1772 append_insn (place
, &insn
, ep
, r
, false);
1776 * Generate a "lui" instruction.
1779 macro_build_lui (place
, counter
, ep
, regnum
)
1785 expressionS high_expr
;
1786 struct mips_cl_insn insn
;
1787 bfd_reloc_code_real_type r
;
1788 CONST
char *name
= "lui";
1789 CONST
char *fmt
= "t,u";
1795 high_expr
.X_op
= O_constant
;
1796 high_expr
.X_add_number
= ep
->X_add_number
;
1799 if (high_expr
.X_op
== O_constant
)
1801 /* we can compute the instruction now without a relocation entry */
1802 if (high_expr
.X_add_number
& 0x8000)
1803 high_expr
.X_add_number
+= 0x10000;
1804 high_expr
.X_add_number
=
1805 ((unsigned long) high_expr
.X_add_number
>> 16) & 0xffff;
1806 r
= BFD_RELOC_UNUSED
;
1810 assert (ep
->X_op
== O_symbol
);
1811 /* _gp_disp is a special case, used from s_cpload. */
1812 assert (mips_pic
== NO_PIC
1813 || strcmp (S_GET_NAME (ep
->X_add_symbol
), "_gp_disp") == 0);
1814 r
= BFD_RELOC_HI16_S
;
1818 * If the macro is about to expand into a second instruction,
1819 * print a warning if needed. We need to pass ip as a parameter
1820 * to generate a better warning message here...
1822 if (mips_warn_about_macros
&& place
== NULL
&& *counter
== 1)
1823 as_warn ("Macro instruction expanded into multiple instructions");
1826 *counter
+= 1; /* bump instruction counter */
1828 insn
.insn_mo
= (struct mips_opcode
*) hash_find (op_hash
, name
);
1829 assert (insn
.insn_mo
);
1830 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
1831 assert (strcmp (fmt
, insn
.insn_mo
->args
) == 0);
1833 insn
.insn_opcode
= insn
.insn_mo
->match
| (regnum
<< OP_SH_RT
);
1834 if (r
== BFD_RELOC_UNUSED
)
1836 insn
.insn_opcode
|= high_expr
.X_add_number
;
1837 append_insn (place
, &insn
, NULL
, r
, false);
1840 append_insn (place
, &insn
, &high_expr
, r
, false);
1844 * Generates code to set the $at register to true (one)
1845 * if reg is less than the immediate expression.
1848 set_at (counter
, reg
, unsignedp
)
1853 if (imm_expr
.X_add_number
>= -0x8000 && imm_expr
.X_add_number
< 0x8000)
1854 macro_build ((char *) NULL
, counter
, &imm_expr
,
1855 unsignedp
? "sltiu" : "slti",
1856 "t,r,j", AT
, reg
, (int) BFD_RELOC_LO16
);
1859 load_register (counter
, AT
, &imm_expr
, 0);
1860 macro_build ((char *) NULL
, counter
, NULL
,
1861 unsignedp
? "sltu" : "slt",
1862 "d,v,t", AT
, reg
, AT
);
1866 /* Warn if an expression is not a constant. */
1869 check_absolute_expr (ip
, ex
)
1870 struct mips_cl_insn
*ip
;
1873 if (ex
->X_op
!= O_constant
)
1874 as_warn ("Instruction %s requires absolute expression", ip
->insn_mo
->name
);
1877 /* Count the leading zeroes by performing a binary chop. This is a
1878 bulky bit of source, but performance is a LOT better for the
1879 majority of values than a simple loop to count the bits:
1880 for (lcnt = 0; (lcnt < 32); lcnt++)
1881 if ((v) & (1 << (31 - lcnt)))
1883 However it is not code size friendly, and the gain will drop a bit
1884 on certain cached systems.
1886 #define COUNT_TOP_ZEROES(v) \
1887 (((v) & ~0xffff) == 0 \
1888 ? ((v) & ~0xff) == 0 \
1889 ? ((v) & ~0xf) == 0 \
1890 ? ((v) & ~0x3) == 0 \
1891 ? ((v) & ~0x1) == 0 \
1896 : ((v) & ~0x7) == 0 \
1899 : ((v) & ~0x3f) == 0 \
1900 ? ((v) & ~0x1f) == 0 \
1903 : ((v) & ~0x7f) == 0 \
1906 : ((v) & ~0xfff) == 0 \
1907 ? ((v) & ~0x3ff) == 0 \
1908 ? ((v) & ~0x1ff) == 0 \
1911 : ((v) & ~0x7ff) == 0 \
1914 : ((v) & ~0x3fff) == 0 \
1915 ? ((v) & ~0x1fff) == 0 \
1918 : ((v) & ~0x7fff) == 0 \
1921 : ((v) & ~0xffffff) == 0 \
1922 ? ((v) & ~0xfffff) == 0 \
1923 ? ((v) & ~0x3ffff) == 0 \
1924 ? ((v) & ~0x1ffff) == 0 \
1927 : ((v) & ~0x7ffff) == 0 \
1930 : ((v) & ~0x3fffff) == 0 \
1931 ? ((v) & ~0x1fffff) == 0 \
1934 : ((v) & ~0x7fffff) == 0 \
1937 : ((v) & ~0xfffffff) == 0 \
1938 ? ((v) & ~0x3ffffff) == 0 \
1939 ? ((v) & ~0x1ffffff) == 0 \
1942 : ((v) & ~0x7ffffff) == 0 \
1945 : ((v) & ~0x3fffffff) == 0 \
1946 ? ((v) & ~0x1fffffff) == 0 \
1949 : ((v) & ~0x7fffffff) == 0 \
1954 * This routine generates the least number of instructions neccessary to load
1955 * an absolute expression value into a register.
1958 load_register (counter
, reg
, ep
, dbl
)
1965 expressionS hi32
, lo32
, tmp
;
1967 if (ep
->X_op
!= O_big
)
1969 assert (ep
->X_op
== O_constant
);
1970 if (ep
->X_add_number
< 0x8000
1971 && (ep
->X_add_number
>= 0
1972 || (ep
->X_add_number
>= -0x8000
1975 || sizeof (ep
->X_add_number
) > 4))))
1977 /* We can handle 16 bit signed values with an addiu to
1978 $zero. No need to ever use daddiu here, since $zero and
1979 the result are always correct in 32 bit mode. */
1980 macro_build ((char *) NULL
, counter
, ep
, "addiu", "t,r,j", reg
, 0,
1981 (int) BFD_RELOC_LO16
);
1984 else if (ep
->X_add_number
>= 0 && ep
->X_add_number
< 0x10000)
1986 /* We can handle 16 bit unsigned values with an ori to
1988 macro_build ((char *) NULL
, counter
, ep
, "ori", "t,r,i", reg
, 0,
1989 (int) BFD_RELOC_LO16
);
1992 else if ((((ep
->X_add_number
&~ (offsetT
) 0x7fffffff) == 0
1993 || ((ep
->X_add_number
&~ (offsetT
) 0x7fffffff)
1994 == ~ (offsetT
) 0x7fffffff))
1997 || sizeof (ep
->X_add_number
) > 4
1998 || (ep
->X_add_number
& 0x80000000) == 0))
1999 || ((mips_isa
< 3 || !dbl
)
2000 && (ep
->X_add_number
&~ 0xffffffff) == 0))
2002 /* 32 bit values require an lui. */
2003 macro_build ((char *) NULL
, counter
, ep
, "lui", "t,u", reg
,
2004 (int) BFD_RELOC_HI16
);
2005 if ((ep
->X_add_number
& 0xffff) != 0)
2006 macro_build ((char *) NULL
, counter
, ep
, "ori", "t,r,i", reg
, reg
,
2007 (int) BFD_RELOC_LO16
);
2012 /* The value is larger than 32 bits. */
2016 as_bad ("Number larger than 32 bits");
2017 macro_build ((char *) NULL
, counter
, ep
, "addiu", "t,r,j", reg
, 0,
2018 (int) BFD_RELOC_LO16
);
2022 if (ep
->X_op
!= O_big
)
2026 hi32
.X_add_number
>>= shift
;
2027 hi32
.X_add_number
&= 0xffffffff;
2028 if ((hi32
.X_add_number
& 0x80000000) != 0)
2029 hi32
.X_add_number
|= ~ (offsetT
) 0xffffffff;
2031 lo32
.X_add_number
&= 0xffffffff;
2035 assert (ep
->X_add_number
> 2);
2036 if (ep
->X_add_number
== 3)
2037 generic_bignum
[3] = 0;
2038 else if (ep
->X_add_number
> 4)
2039 as_bad ("Number larger than 64 bits");
2040 lo32
.X_op
= O_constant
;
2041 lo32
.X_add_number
= generic_bignum
[0] + (generic_bignum
[1] << 16);
2042 hi32
.X_op
= O_constant
;
2043 hi32
.X_add_number
= generic_bignum
[2] + (generic_bignum
[3] << 16);
2046 if (hi32
.X_add_number
== 0)
2050 if (hi32
.X_add_number
== 0xffffffff)
2052 if ((lo32
.X_add_number
& 0xffff8000) == 0xffff8000)
2054 macro_build ((char *) NULL
, counter
, &lo32
, "addiu", "t,r,j", reg
, 0,
2055 (int) BFD_RELOC_LO16
);
2058 if (lo32
.X_add_number
& 0x80000000)
2060 macro_build ((char *) NULL
, counter
, &lo32
, "lui", "t,u", reg
,
2061 (int) BFD_RELOC_HI16
);
2062 macro_build ((char *) NULL
, counter
, &lo32
, "ori", "t,r,i", reg
, reg
,
2063 (int) BFD_RELOC_LO16
);
2068 /* Check for 16bit shifted constant: */
2070 tmp
.X_add_number
= hi32
.X_add_number
<< shift
| lo32
.X_add_number
;
2071 /* We know that hi32 is non-zero, so start the mask on the first
2072 bit of the hi32 value: */
2076 if ((tmp
.X_add_number
& ~((offsetT
)0xffff << shift
)) == 0)
2078 tmp
.X_op
= O_constant
;
2079 tmp
.X_add_number
>>= shift
;
2080 macro_build ((char *) NULL
, counter
, &tmp
, "ori", "t,r,i", reg
, 0,
2081 (int) BFD_RELOC_LO16
);
2082 macro_build ((char *) NULL
, counter
, NULL
,
2083 (shift
>= 32) ? "dsll32" : "dsll",
2084 "d,w,<", reg
, reg
, (shift
>= 32) ? shift
- 32 : shift
);
2088 } while (shift
<= (64 - 16));
2092 tmp
.X_add_number
= hi32
.X_add_number
<< shift
| lo32
.X_add_number
;
2093 while ((tmp
.X_add_number
& 1) == 0)
2095 tmp
.X_add_number
>>= 1;
2098 if (((tmp
.X_add_number
+ 1) & tmp
.X_add_number
) == 0) /* (power-of-2 - 1) */
2100 shift
= COUNT_TOP_ZEROES((unsigned int)hi32
.X_add_number
);
2103 tmp
.X_op
= O_constant
;
2104 tmp
.X_add_number
= (offsetT
)-1;
2105 macro_build ((char *) NULL
, counter
, &tmp
, "addiu", "t,r,j", reg
, 0,
2106 (int) BFD_RELOC_LO16
); /* set all ones */
2110 macro_build ((char *) NULL
, counter
, NULL
,
2111 (freg
>= 32) ? "dsll32" : "dsll",
2113 (freg
>= 32) ? freg
- 32 : freg
);
2115 macro_build ((char *) NULL
, counter
, NULL
, (shift
>= 32) ? "dsrl32" : "dsrl",
2116 "d,w,<", reg
, reg
, (shift
>= 32) ? shift
- 32 : shift
);
2120 load_register (counter
, reg
, &hi32
, 0);
2123 if ((lo32
.X_add_number
& 0xffff0000) == 0)
2127 macro_build ((char *) NULL
, counter
, NULL
, "dsll32", "d,w,<", reg
,
2136 if ((freg
== 0) && (lo32
.X_add_number
== 0xffffffff))
2138 macro_build ((char *) NULL
, counter
, &lo32
, "lui", "t,u", reg
,
2139 (int) BFD_RELOC_HI16
);
2140 macro_build ((char *) NULL
, counter
, NULL
, "dsrl32", "d,w,<", reg
,
2147 macro_build ((char *) NULL
, counter
, NULL
, "dsll", "d,w,<", reg
,
2152 mid16
.X_add_number
>>= 16;
2153 macro_build ((char *) NULL
, counter
, &mid16
, "ori", "t,r,i", reg
,
2154 freg
, (int) BFD_RELOC_LO16
);
2155 macro_build ((char *) NULL
, counter
, NULL
, "dsll", "d,w,<", reg
,
2159 if ((lo32
.X_add_number
& 0xffff) != 0)
2160 macro_build ((char *) NULL
, counter
, &lo32
, "ori", "t,r,i", reg
, freg
,
2161 (int) BFD_RELOC_LO16
);
2164 /* Load an address into a register. */
2167 load_address (counter
, reg
, ep
)
2174 if (ep
->X_op
!= O_constant
2175 && ep
->X_op
!= O_symbol
)
2177 as_bad ("expression too complex");
2178 ep
->X_op
= O_constant
;
2181 if (ep
->X_op
== O_constant
)
2183 load_register (counter
, reg
, ep
, 0);
2187 if (mips_pic
== NO_PIC
)
2189 /* If this is a reference to a GP relative symbol, we want
2190 addiu $reg,$gp,<sym> (BFD_RELOC_MIPS_GPREL)
2192 lui $reg,<sym> (BFD_RELOC_HI16_S)
2193 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
2194 If we have an addend, we always use the latter form. */
2195 if ((valueT
) ep
->X_add_number
>= MAX_GPREL_OFFSET
2196 || nopic_need_relax (ep
->X_add_symbol
))
2201 macro_build ((char *) NULL
, counter
, ep
,
2202 mips_isa
< 3 ? "addiu" : "daddiu",
2203 "t,r,j", reg
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
2204 p
= frag_var (rs_machine_dependent
, 8, 0,
2205 RELAX_ENCODE (4, 8, 0, 4, 0, mips_warn_about_macros
),
2206 ep
->X_add_symbol
, (long) 0, (char *) NULL
);
2208 macro_build_lui (p
, counter
, ep
, reg
);
2211 macro_build (p
, counter
, ep
,
2212 mips_isa
< 3 ? "addiu" : "daddiu",
2213 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
2215 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
2219 /* If this is a reference to an external symbol, we want
2220 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
2222 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
2224 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
2225 If there is a constant, it must be added in after. */
2226 ex
.X_add_number
= ep
->X_add_number
;
2227 ep
->X_add_number
= 0;
2229 macro_build ((char *) NULL
, counter
, ep
,
2230 mips_isa
< 3 ? "lw" : "ld",
2231 "t,o(b)", reg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
2232 macro_build ((char *) NULL
, counter
, (expressionS
*) NULL
, "nop", "");
2233 p
= frag_var (rs_machine_dependent
, 4, 0,
2234 RELAX_ENCODE (0, 4, -8, 0, 0, mips_warn_about_macros
),
2235 ep
->X_add_symbol
, (long) 0, (char *) NULL
);
2236 macro_build (p
, counter
, ep
,
2237 mips_isa
< 3 ? "addiu" : "daddiu",
2238 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
2239 if (ex
.X_add_number
!= 0)
2241 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
2242 as_bad ("PIC code offset overflow (max 16 signed bits)");
2243 ex
.X_op
= O_constant
;
2244 macro_build ((char *) NULL
, counter
, &ex
,
2245 mips_isa
< 3 ? "addiu" : "daddiu",
2246 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
2249 else if (mips_pic
== SVR4_PIC
)
2254 /* This is the large GOT case. If this is a reference to an
2255 external symbol, we want
2256 lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
2258 lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16)
2259 Otherwise, for a reference to a local symbol, we want
2260 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
2262 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
2263 If there is a constant, it must be added in after. */
2264 ex
.X_add_number
= ep
->X_add_number
;
2265 ep
->X_add_number
= 0;
2266 if (reg_needs_delay (GP
))
2271 macro_build ((char *) NULL
, counter
, ep
, "lui", "t,u", reg
,
2272 (int) BFD_RELOC_MIPS_GOT_HI16
);
2273 macro_build ((char *) NULL
, counter
, (expressionS
*) NULL
,
2274 mips_isa
< 3 ? "addu" : "daddu",
2275 "d,v,t", reg
, reg
, GP
);
2276 macro_build ((char *) NULL
, counter
, ep
,
2277 mips_isa
< 3 ? "lw" : "ld",
2278 "t,o(b)", reg
, (int) BFD_RELOC_MIPS_GOT_LO16
, reg
);
2279 p
= frag_var (rs_machine_dependent
, 12 + off
, 0,
2280 RELAX_ENCODE (12, 12 + off
, off
, 8 + off
, 0,
2281 mips_warn_about_macros
),
2282 ep
->X_add_symbol
, (long) 0, (char *) NULL
);
2285 /* We need a nop before loading from $gp. This special
2286 check is required because the lui which starts the main
2287 instruction stream does not refer to $gp, and so will not
2288 insert the nop which may be required. */
2289 macro_build (p
, counter
, (expressionS
*) NULL
, "nop", "");
2292 macro_build (p
, counter
, ep
,
2293 mips_isa
< 3 ? "lw" : "ld",
2294 "t,o(b)", reg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
2296 macro_build (p
, counter
, (expressionS
*) NULL
, "nop", "");
2298 macro_build (p
, counter
, ep
,
2299 mips_isa
< 3 ? "addiu" : "daddiu",
2300 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
2301 if (ex
.X_add_number
!= 0)
2303 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
2304 as_bad ("PIC code offset overflow (max 16 signed bits)");
2305 ex
.X_op
= O_constant
;
2306 macro_build ((char *) NULL
, counter
, &ex
,
2307 mips_isa
< 3 ? "addiu" : "daddiu",
2308 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
2311 else if (mips_pic
== EMBEDDED_PIC
)
2314 addiu $reg,$gp,<sym> (BFD_RELOC_MIPS_GPREL)
2316 macro_build ((char *) NULL
, counter
, ep
,
2317 mips_isa
< 3 ? "addiu" : "daddiu",
2318 "t,r,j", reg
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
2326 * This routine implements the seemingly endless macro or synthesized
2327 * instructions and addressing modes in the mips assembly language. Many
2328 * of these macros are simple and are similar to each other. These could
2329 * probably be handled by some kind of table or grammer aproach instead of
2330 * this verbose method. Others are not simple macros but are more like
2331 * optimizing code generation.
2332 * One interesting optimization is when several store macros appear
2333 * consecutivly that would load AT with the upper half of the same address.
2334 * The ensuing load upper instructions are ommited. This implies some kind
2335 * of global optimization. We currently only optimize within a single macro.
2336 * For many of the load and store macros if the address is specified as a
2337 * constant expression in the first 64k of memory (ie ld $2,0x4000c) we
2338 * first load register 'at' with zero and use it as the base register. The
2339 * mips assembler simply uses register $zero. Just one tiny optimization
2344 struct mips_cl_insn
*ip
;
2346 register int treg
, sreg
, dreg
, breg
;
2361 bfd_reloc_code_real_type r
;
2363 int hold_mips_optimize
;
2365 treg
= (ip
->insn_opcode
>> 16) & 0x1f;
2366 dreg
= (ip
->insn_opcode
>> 11) & 0x1f;
2367 sreg
= breg
= (ip
->insn_opcode
>> 21) & 0x1f;
2368 mask
= ip
->insn_mo
->mask
;
2370 expr1
.X_op
= O_constant
;
2371 expr1
.X_op_symbol
= NULL
;
2372 expr1
.X_add_symbol
= NULL
;
2373 expr1
.X_add_number
= 1;
2385 mips_emit_delays ();
2387 mips_any_noreorder
= 1;
2389 expr1
.X_add_number
= 8;
2390 macro_build ((char *) NULL
, &icnt
, &expr1
, "bgez", "s,p", sreg
);
2392 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
2394 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
, sreg
, 0);
2395 macro_build ((char *) NULL
, &icnt
, NULL
,
2396 dbl
? "dsub" : "sub",
2397 "d,v,t", dreg
, 0, sreg
);
2420 if (imm_expr
.X_add_number
>= -0x8000 && imm_expr
.X_add_number
< 0x8000)
2422 macro_build ((char *) NULL
, &icnt
, &imm_expr
, s
, "t,r,j", treg
, sreg
,
2423 (int) BFD_RELOC_LO16
);
2426 load_register (&icnt
, AT
, &imm_expr
, dbl
);
2427 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "d,v,t", treg
, sreg
, AT
);
2446 if (imm_expr
.X_add_number
>= 0 && imm_expr
.X_add_number
< 0x10000)
2448 if (mask
!= M_NOR_I
)
2449 macro_build ((char *) NULL
, &icnt
, &imm_expr
, s
, "t,r,i", treg
,
2450 sreg
, (int) BFD_RELOC_LO16
);
2453 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "ori", "t,r,i",
2454 treg
, sreg
, (int) BFD_RELOC_LO16
);
2455 macro_build ((char *) NULL
, &icnt
, NULL
, "nor", "d,v,t",
2461 load_register (&icnt
, AT
, &imm_expr
, 0);
2462 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "d,v,t", treg
, sreg
, AT
);
2479 if (imm_expr
.X_add_number
== 0)
2481 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "s,t,p", sreg
,
2485 load_register (&icnt
, AT
, &imm_expr
, 0);
2486 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "s,t,p", sreg
, AT
);
2494 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2495 likely
? "bgezl" : "bgez",
2501 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2502 likely
? "blezl" : "blez",
2506 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", AT
, sreg
, treg
);
2507 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2508 likely
? "beql" : "beq",
2515 /* check for > max integer */
2516 maxnum
= 0x7fffffff;
2524 if (imm_expr
.X_add_number
>= maxnum
2525 && (mips_isa
< 3 || sizeof (maxnum
) > 4))
2528 /* result is always false */
2531 as_warn ("Branch %s is always false (nop)", ip
->insn_mo
->name
);
2532 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
2536 as_warn ("Branch likely %s is always false", ip
->insn_mo
->name
);
2537 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "bnel",
2542 imm_expr
.X_add_number
++;
2546 if (mask
== M_BGEL_I
)
2548 if (imm_expr
.X_add_number
== 0)
2550 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2551 likely
? "bgezl" : "bgez",
2555 if (imm_expr
.X_add_number
== 1)
2557 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2558 likely
? "bgtzl" : "bgtz",
2562 maxnum
= 0x7fffffff;
2570 maxnum
= - maxnum
- 1;
2571 if (imm_expr
.X_add_number
<= maxnum
2572 && (mips_isa
< 3 || sizeof (maxnum
) > 4))
2575 /* result is always true */
2576 as_warn ("Branch %s is always true", ip
->insn_mo
->name
);
2577 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "b", "p");
2580 set_at (&icnt
, sreg
, 0);
2581 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2582 likely
? "beql" : "beq",
2593 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2594 likely
? "beql" : "beq",
2598 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", AT
, sreg
,
2600 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2601 likely
? "beql" : "beq",
2608 if (sreg
== 0 || imm_expr
.X_add_number
== -1)
2610 imm_expr
.X_add_number
++;
2614 if (mask
== M_BGEUL_I
)
2616 if (imm_expr
.X_add_number
== 0)
2618 if (imm_expr
.X_add_number
== 1)
2620 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2621 likely
? "bnel" : "bne",
2625 set_at (&icnt
, sreg
, 1);
2626 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2627 likely
? "beql" : "beq",
2636 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2637 likely
? "bgtzl" : "bgtz",
2643 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2644 likely
? "bltzl" : "bltz",
2648 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", AT
, treg
, sreg
);
2649 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2650 likely
? "bnel" : "bne",
2659 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2660 likely
? "bnel" : "bne",
2666 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", AT
, treg
,
2668 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2669 likely
? "bnel" : "bne",
2678 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2679 likely
? "blezl" : "blez",
2685 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2686 likely
? "bgezl" : "bgez",
2690 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", AT
, treg
, sreg
);
2691 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2692 likely
? "beql" : "beq",
2699 maxnum
= 0x7fffffff;
2707 if (imm_expr
.X_add_number
>= maxnum
2708 && (mips_isa
< 3 || sizeof (maxnum
) > 4))
2710 imm_expr
.X_add_number
++;
2714 if (mask
== M_BLTL_I
)
2716 if (imm_expr
.X_add_number
== 0)
2718 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2719 likely
? "bltzl" : "bltz",
2723 if (imm_expr
.X_add_number
== 1)
2725 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2726 likely
? "blezl" : "blez",
2730 set_at (&icnt
, sreg
, 0);
2731 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2732 likely
? "bnel" : "bne",
2741 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2742 likely
? "beql" : "beq",
2748 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", AT
, treg
,
2750 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2751 likely
? "beql" : "beq",
2758 if (sreg
== 0 || imm_expr
.X_add_number
== -1)
2760 imm_expr
.X_add_number
++;
2764 if (mask
== M_BLTUL_I
)
2766 if (imm_expr
.X_add_number
== 0)
2768 if (imm_expr
.X_add_number
== 1)
2770 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2771 likely
? "beql" : "beq",
2775 set_at (&icnt
, sreg
, 1);
2776 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2777 likely
? "bnel" : "bne",
2786 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2787 likely
? "bltzl" : "bltz",
2793 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2794 likely
? "bgtzl" : "bgtz",
2798 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", AT
, sreg
, treg
);
2799 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2800 likely
? "bnel" : "bne",
2811 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2812 likely
? "bnel" : "bne",
2816 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", AT
, sreg
,
2818 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2819 likely
? "bnel" : "bne",
2835 as_warn ("Divide by zero.");
2837 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", 0, 0);
2839 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 7);
2843 mips_emit_delays ();
2845 mips_any_noreorder
= 1;
2846 macro_build ((char *) NULL
, &icnt
, NULL
,
2847 dbl
? "ddiv" : "div",
2848 "z,s,t", sreg
, treg
);
2850 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", treg
, 0);
2853 expr1
.X_add_number
= 8;
2854 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", treg
, 0);
2855 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
2856 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 7);
2858 expr1
.X_add_number
= -1;
2859 macro_build ((char *) NULL
, &icnt
, &expr1
,
2860 dbl
? "daddiu" : "addiu",
2861 "t,r,j", AT
, 0, (int) BFD_RELOC_LO16
);
2862 expr1
.X_add_number
= mips_trap
? (dbl
? 12 : 8) : (dbl
? 20 : 16);
2863 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", treg
, AT
);
2866 expr1
.X_add_number
= 1;
2867 macro_build ((char *) NULL
, &icnt
, &expr1
, "daddiu", "t,r,j", AT
, 0,
2868 (int) BFD_RELOC_LO16
);
2869 macro_build ((char *) NULL
, &icnt
, NULL
, "dsll32", "d,w,<", AT
, AT
,
2874 expr1
.X_add_number
= 0x80000000;
2875 macro_build ((char *) NULL
, &icnt
, &expr1
, "lui", "t,u", AT
,
2876 (int) BFD_RELOC_HI16
);
2879 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", sreg
, AT
);
2882 expr1
.X_add_number
= 8;
2883 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", sreg
, AT
);
2884 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
2885 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 6);
2888 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d", dreg
);
2927 if (imm_expr
.X_add_number
== 0)
2929 as_warn ("Divide by zero.");
2931 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", 0, 0);
2933 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 7);
2936 if (imm_expr
.X_add_number
== 1)
2938 if (strcmp (s2
, "mflo") == 0)
2939 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
,
2942 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
, 0);
2945 if (imm_expr
.X_add_number
== -1
2946 && s
[strlen (s
) - 1] != 'u')
2948 if (strcmp (s2
, "mflo") == 0)
2951 macro_build ((char *) NULL
, &icnt
, NULL
, "dneg", "d,w", dreg
,
2954 macro_build ((char *) NULL
, &icnt
, NULL
, "neg", "d,w", dreg
,
2958 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
, 0);
2962 load_register (&icnt
, AT
, &imm_expr
, dbl
);
2963 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "z,s,t", sreg
, AT
);
2964 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "d", dreg
);
2983 mips_emit_delays ();
2985 mips_any_noreorder
= 1;
2986 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "z,s,t", sreg
, treg
);
2988 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", treg
, 0);
2991 expr1
.X_add_number
= 8;
2992 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", treg
, 0);
2993 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
2994 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 7);
2997 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "d", dreg
);
3003 /* Load the address of a symbol into a register. If breg is not
3004 zero, we then add a base register to it. */
3006 /* When generating embedded PIC code, we permit expressions of
3009 where bar is an address in the .text section. These are used
3010 when getting the addresses of functions. We don't permit
3011 X_add_number to be non-zero, because if the symbol is
3012 external the relaxing code needs to know that any addend is
3013 purely the offset to X_op_symbol. */
3014 if (mips_pic
== EMBEDDED_PIC
3015 && offset_expr
.X_op
== O_subtract
3016 && now_seg
== text_section
3017 && (offset_expr
.X_op_symbol
->sy_value
.X_op
== O_constant
3018 ? S_GET_SEGMENT (offset_expr
.X_op_symbol
) == text_section
3019 : (offset_expr
.X_op_symbol
->sy_value
.X_op
== O_symbol
3020 && (S_GET_SEGMENT (offset_expr
.X_op_symbol
3021 ->sy_value
.X_add_symbol
)
3024 && offset_expr
.X_add_number
== 0)
3026 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
3027 treg
, (int) BFD_RELOC_PCREL_HI16_S
);
3028 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3029 mips_isa
< 3 ? "addiu" : "daddiu",
3030 "t,r,j", treg
, treg
, (int) BFD_RELOC_PCREL_LO16
);
3034 if (offset_expr
.X_op
!= O_symbol
3035 && offset_expr
.X_op
!= O_constant
)
3037 as_bad ("expression too complex");
3038 offset_expr
.X_op
= O_constant
;
3052 if (offset_expr
.X_op
== O_constant
)
3053 load_register (&icnt
, tempreg
, &offset_expr
, dbl
);
3054 else if (mips_pic
== NO_PIC
)
3056 /* If this is a reference to an GP relative symbol, we want
3057 addiu $tempreg,$gp,<sym> (BFD_RELOC_MIPS_GPREL)
3059 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
3060 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
3061 If we have a constant, we need two instructions anyhow,
3062 so we may as well always use the latter form. */
3063 if ((valueT
) offset_expr
.X_add_number
>= MAX_GPREL_OFFSET
3064 || nopic_need_relax (offset_expr
.X_add_symbol
))
3069 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3070 mips_isa
< 3 ? "addiu" : "daddiu",
3071 "t,r,j", tempreg
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
3072 p
= frag_var (rs_machine_dependent
, 8, 0,
3073 RELAX_ENCODE (4, 8, 0, 4, 0,
3074 mips_warn_about_macros
),
3075 offset_expr
.X_add_symbol
, (long) 0,
3078 macro_build_lui (p
, &icnt
, &offset_expr
, tempreg
);
3081 macro_build (p
, &icnt
, &offset_expr
,
3082 mips_isa
< 3 ? "addiu" : "daddiu",
3083 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
3085 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
3087 /* If this is a reference to an external symbol, and there
3088 is no constant, we want
3089 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3090 For a local symbol, we want
3091 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3093 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
3095 If we have a small constant, and this is a reference to
3096 an external symbol, we want
3097 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3099 addiu $tempreg,$tempreg,<constant>
3100 For a local symbol, we want the same instruction
3101 sequence, but we output a BFD_RELOC_LO16 reloc on the
3104 If we have a large constant, and this is a reference to
3105 an external symbol, we want
3106 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3107 lui $at,<hiconstant>
3108 addiu $at,$at,<loconstant>
3109 addu $tempreg,$tempreg,$at
3110 For a local symbol, we want the same instruction
3111 sequence, but we output a BFD_RELOC_LO16 reloc on the
3112 addiu instruction. */
3113 expr1
.X_add_number
= offset_expr
.X_add_number
;
3114 offset_expr
.X_add_number
= 0;
3116 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3118 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
3119 if (expr1
.X_add_number
== 0)
3127 /* We're going to put in an addu instruction using
3128 tempreg, so we may as well insert the nop right
3130 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3134 p
= frag_var (rs_machine_dependent
, 8 - off
, 0,
3135 RELAX_ENCODE (0, 8 - off
, -4 - off
, 4 - off
, 0,
3137 ? mips_warn_about_macros
3139 offset_expr
.X_add_symbol
, (long) 0,
3143 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
3146 macro_build (p
, &icnt
, &expr1
,
3147 mips_isa
< 3 ? "addiu" : "daddiu",
3148 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
3149 /* FIXME: If breg == 0, and the next instruction uses
3150 $tempreg, then if this variant case is used an extra
3151 nop will be generated. */
3153 else if (expr1
.X_add_number
>= -0x8000
3154 && expr1
.X_add_number
< 0x8000)
3156 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3158 macro_build ((char *) NULL
, &icnt
, &expr1
,
3159 mips_isa
< 3 ? "addiu" : "daddiu",
3160 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
3161 (void) frag_var (rs_machine_dependent
, 0, 0,
3162 RELAX_ENCODE (0, 0, -12, -4, 0, 0),
3163 offset_expr
.X_add_symbol
, (long) 0,
3170 /* If we are going to add in a base register, and the
3171 target register and the base register are the same,
3172 then we are using AT as a temporary register. Since
3173 we want to load the constant into AT, we add our
3174 current AT (from the global offset table) and the
3175 register into the register now, and pretend we were
3176 not using a base register. */
3181 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3183 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3184 mips_isa
< 3 ? "addu" : "daddu",
3185 "d,v,t", treg
, AT
, breg
);
3191 /* Set mips_optimize around the lui instruction to avoid
3192 inserting an unnecessary nop after the lw. */
3193 hold_mips_optimize
= mips_optimize
;
3195 macro_build_lui ((char *) NULL
, &icnt
, &expr1
, AT
);
3196 mips_optimize
= hold_mips_optimize
;
3198 macro_build ((char *) NULL
, &icnt
, &expr1
,
3199 mips_isa
< 3 ? "addiu" : "daddiu",
3200 "t,r,j", AT
, AT
, (int) BFD_RELOC_LO16
);
3201 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3202 mips_isa
< 3 ? "addu" : "daddu",
3203 "d,v,t", tempreg
, tempreg
, AT
);
3204 (void) frag_var (rs_machine_dependent
, 0, 0,
3205 RELAX_ENCODE (0, 0, -16 + off1
, -8, 0, 0),
3206 offset_expr
.X_add_symbol
, (long) 0,
3211 else if (mips_pic
== SVR4_PIC
)
3215 /* This is the large GOT case. If this is a reference to an
3216 external symbol, and there is no constant, we want
3217 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
3218 addu $tempreg,$tempreg,$gp
3219 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
3220 For a local symbol, we want
3221 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3223 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
3225 If we have a small constant, and this is a reference to
3226 an external symbol, we want
3227 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
3228 addu $tempreg,$tempreg,$gp
3229 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
3231 addiu $tempreg,$tempreg,<constant>
3232 For a local symbol, we want
3233 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3235 addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16)
3237 If we have a large constant, and this is a reference to
3238 an external symbol, we want
3239 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
3240 addu $tempreg,$tempreg,$gp
3241 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
3242 lui $at,<hiconstant>
3243 addiu $at,$at,<loconstant>
3244 addu $tempreg,$tempreg,$at
3245 For a local symbol, we want
3246 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3247 lui $at,<hiconstant>
3248 addiu $at,$at,<loconstant> (BFD_RELOC_LO16)
3249 addu $tempreg,$tempreg,$at
3251 expr1
.X_add_number
= offset_expr
.X_add_number
;
3252 offset_expr
.X_add_number
= 0;
3254 if (reg_needs_delay (GP
))
3258 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
3259 tempreg
, (int) BFD_RELOC_MIPS_GOT_HI16
);
3260 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3261 mips_isa
< 3 ? "addu" : "daddu",
3262 "d,v,t", tempreg
, tempreg
, GP
);
3263 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3265 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT_LO16
,
3267 if (expr1
.X_add_number
== 0)
3275 /* We're going to put in an addu instruction using
3276 tempreg, so we may as well insert the nop right
3278 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3283 p
= frag_var (rs_machine_dependent
, 12 + gpdel
, 0,
3284 RELAX_ENCODE (12 + off
, 12 + gpdel
, gpdel
,
3287 ? mips_warn_about_macros
3289 offset_expr
.X_add_symbol
, (long) 0,
3292 else if (expr1
.X_add_number
>= -0x8000
3293 && expr1
.X_add_number
< 0x8000)
3295 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3297 macro_build ((char *) NULL
, &icnt
, &expr1
,
3298 mips_isa
< 3 ? "addiu" : "daddiu",
3299 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
3301 p
= frag_var (rs_machine_dependent
, 12 + gpdel
, 0,
3302 RELAX_ENCODE (20, 12 + gpdel
, gpdel
, 8 + gpdel
, 0,
3304 ? mips_warn_about_macros
3306 offset_expr
.X_add_symbol
, (long) 0,
3313 /* If we are going to add in a base register, and the
3314 target register and the base register are the same,
3315 then we are using AT as a temporary register. Since
3316 we want to load the constant into AT, we add our
3317 current AT (from the global offset table) and the
3318 register into the register now, and pretend we were
3319 not using a base register. */
3327 assert (tempreg
== AT
);
3328 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3330 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3331 mips_isa
< 3 ? "addu" : "daddu",
3332 "d,v,t", treg
, AT
, breg
);
3337 /* Set mips_optimize around the lui instruction to avoid
3338 inserting an unnecessary nop after the lw. */
3339 hold_mips_optimize
= mips_optimize
;
3341 macro_build_lui ((char *) NULL
, &icnt
, &expr1
, AT
);
3342 mips_optimize
= hold_mips_optimize
;
3344 macro_build ((char *) NULL
, &icnt
, &expr1
,
3345 mips_isa
< 3 ? "addiu" : "daddiu",
3346 "t,r,j", AT
, AT
, (int) BFD_RELOC_LO16
);
3347 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3348 mips_isa
< 3 ? "addu" : "daddu",
3349 "d,v,t", dreg
, dreg
, AT
);
3351 p
= frag_var (rs_machine_dependent
, 16 + gpdel
+ adj
, 0,
3352 RELAX_ENCODE (24 + adj
, 16 + gpdel
+ adj
, gpdel
,
3355 ? mips_warn_about_macros
3357 offset_expr
.X_add_symbol
, (long) 0,
3365 /* This is needed because this instruction uses $gp, but
3366 the first instruction on the main stream does not. */
3367 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
3370 macro_build (p
, &icnt
, &offset_expr
,
3372 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
3374 if (expr1
.X_add_number
>= -0x8000
3375 && expr1
.X_add_number
< 0x8000)
3377 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
3379 macro_build (p
, &icnt
, &expr1
,
3380 mips_isa
< 3 ? "addiu" : "daddiu",
3381 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
3382 /* FIXME: If add_number is 0, and there was no base
3383 register, the external symbol case ended with a load,
3384 so if the symbol turns out to not be external, and
3385 the next instruction uses tempreg, an unnecessary nop
3386 will be inserted. */
3392 /* We must add in the base register now, as in the
3393 external symbol case. */
3394 assert (tempreg
== AT
);
3395 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
3397 macro_build (p
, &icnt
, (expressionS
*) NULL
,
3398 mips_isa
< 3 ? "addu" : "daddu",
3399 "d,v,t", treg
, AT
, breg
);
3402 /* We set breg to 0 because we have arranged to add
3403 it in in both cases. */
3407 macro_build_lui (p
, &icnt
, &expr1
, AT
);
3409 macro_build (p
, &icnt
, &expr1
,
3410 mips_isa
< 3 ? "addiu" : "daddiu",
3411 "t,r,j", AT
, AT
, (int) BFD_RELOC_LO16
);
3413 macro_build (p
, &icnt
, (expressionS
*) NULL
,
3414 mips_isa
< 3 ? "addu" : "daddu",
3415 "d,v,t", tempreg
, tempreg
, AT
);
3419 else if (mips_pic
== EMBEDDED_PIC
)
3422 addiu $tempreg,$gp,<sym> (BFD_RELOC_MIPS_GPREL)
3424 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3425 mips_isa
< 3 ? "addiu" : "daddiu",
3426 "t,r,j", tempreg
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
3432 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3433 mips_isa
< 3 ? "addu" : "daddu",
3434 "d,v,t", treg
, tempreg
, breg
);
3442 /* The j instruction may not be used in PIC code, since it
3443 requires an absolute address. We convert it to a b
3445 if (mips_pic
== NO_PIC
)
3446 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "j", "a");
3448 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "b", "p");
3451 /* The jal instructions must be handled as macros because when
3452 generating PIC code they expand to multi-instruction
3453 sequences. Normally they are simple instructions. */
3458 if (mips_pic
== NO_PIC
3459 || mips_pic
== EMBEDDED_PIC
)
3460 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "jalr",
3462 else if (mips_pic
== SVR4_PIC
)
3464 if (sreg
!= PIC_CALL_REG
)
3465 as_warn ("MIPS PIC call to register other than $25");
3467 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "jalr",
3469 if (mips_cprestore_offset
< 0)
3470 as_warn ("No .cprestore pseudo-op used in PIC code");
3473 expr1
.X_add_number
= mips_cprestore_offset
;
3474 macro_build ((char *) NULL
, &icnt
, &expr1
,
3475 mips_isa
< 3 ? "lw" : "ld",
3476 "t,o(b)", GP
, (int) BFD_RELOC_LO16
, mips_frame_reg
);
3485 if (mips_pic
== NO_PIC
)
3486 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "jal", "a");
3487 else if (mips_pic
== SVR4_PIC
)
3489 /* If this is a reference to an external symbol, and we are
3490 using a small GOT, we want
3491 lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
3495 lw $gp,cprestore($sp)
3496 The cprestore value is set using the .cprestore
3497 pseudo-op. If we are using a big GOT, we want
3498 lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16)
3500 lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16)
3504 lw $gp,cprestore($sp)
3505 If the symbol is not external, we want
3506 lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3508 addiu $25,$25,<sym> (BFD_RELOC_LO16)
3511 lw $gp,cprestore($sp) */
3515 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3516 mips_isa
< 3 ? "lw" : "ld",
3517 "t,o(b)", PIC_CALL_REG
,
3518 (int) BFD_RELOC_MIPS_CALL16
, GP
);
3519 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3521 p
= frag_var (rs_machine_dependent
, 4, 0,
3522 RELAX_ENCODE (0, 4, -8, 0, 0, 0),
3523 offset_expr
.X_add_symbol
, (long) 0, (char *) NULL
);
3529 if (reg_needs_delay (GP
))
3533 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
3534 PIC_CALL_REG
, (int) BFD_RELOC_MIPS_CALL_HI16
);
3535 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3536 mips_isa
< 3 ? "addu" : "daddu",
3537 "d,v,t", PIC_CALL_REG
, PIC_CALL_REG
, GP
);
3538 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3539 mips_isa
< 3 ? "lw" : "ld",
3540 "t,o(b)", PIC_CALL_REG
,
3541 (int) BFD_RELOC_MIPS_CALL_LO16
, PIC_CALL_REG
);
3542 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3544 p
= frag_var (rs_machine_dependent
, 12 + gpdel
, 0,
3545 RELAX_ENCODE (16, 12 + gpdel
, gpdel
, 8 + gpdel
,
3547 offset_expr
.X_add_symbol
, (long) 0, (char *) NULL
);
3550 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
3553 macro_build (p
, &icnt
, &offset_expr
,
3554 mips_isa
< 3 ? "lw" : "ld",
3555 "t,o(b)", PIC_CALL_REG
,
3556 (int) BFD_RELOC_MIPS_GOT16
, GP
);
3558 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
3561 macro_build (p
, &icnt
, &offset_expr
,
3562 mips_isa
< 3 ? "addiu" : "daddiu",
3563 "t,r,j", PIC_CALL_REG
, PIC_CALL_REG
,
3564 (int) BFD_RELOC_LO16
);
3565 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3566 "jalr", "s", PIC_CALL_REG
);
3567 if (mips_cprestore_offset
< 0)
3568 as_warn ("No .cprestore pseudo-op used in PIC code");
3572 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3574 expr1
.X_add_number
= mips_cprestore_offset
;
3575 macro_build ((char *) NULL
, &icnt
, &expr1
,
3576 mips_isa
< 3 ? "lw" : "ld",
3577 "t,o(b)", GP
, (int) BFD_RELOC_LO16
,
3581 else if (mips_pic
== EMBEDDED_PIC
)
3583 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "bal", "p");
3584 /* The linker may expand the call to a longer sequence which
3585 uses $at, so we must break rather than return. */
3661 if (breg
== treg
|| coproc
|| lr
)
3730 if (mask
== M_LWC1_AB
3731 || mask
== M_SWC1_AB
3732 || mask
== M_LDC1_AB
3733 || mask
== M_SDC1_AB
3742 if (offset_expr
.X_op
!= O_constant
3743 && offset_expr
.X_op
!= O_symbol
)
3745 as_bad ("expression too complex");
3746 offset_expr
.X_op
= O_constant
;
3749 /* A constant expression in PIC code can be handled just as it
3750 is in non PIC code. */
3751 if (mips_pic
== NO_PIC
3752 || offset_expr
.X_op
== O_constant
)
3754 /* If this is a reference to a GP relative symbol, and there
3755 is no base register, we want
3756 <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL)
3757 Otherwise, if there is no base register, we want
3758 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
3759 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
3760 If we have a constant, we need two instructions anyhow,
3761 so we always use the latter form.
3763 If we have a base register, and this is a reference to a
3764 GP relative symbol, we want
3765 addu $tempreg,$breg,$gp
3766 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GPREL)
3768 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
3769 addu $tempreg,$tempreg,$breg
3770 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
3771 With a constant we always use the latter case. */
3774 if ((valueT
) offset_expr
.X_add_number
>= MAX_GPREL_OFFSET
3775 || nopic_need_relax (offset_expr
.X_add_symbol
))
3780 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
3781 treg
, (int) BFD_RELOC_MIPS_GPREL
, GP
);
3782 p
= frag_var (rs_machine_dependent
, 8, 0,
3783 RELAX_ENCODE (4, 8, 0, 4, 0,
3784 (mips_warn_about_macros
3785 || (used_at
&& mips_noat
))),
3786 offset_expr
.X_add_symbol
, (long) 0,
3790 macro_build_lui (p
, &icnt
, &offset_expr
, tempreg
);
3793 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
, treg
,
3794 (int) BFD_RELOC_LO16
, tempreg
);
3798 if ((valueT
) offset_expr
.X_add_number
>= MAX_GPREL_OFFSET
3799 || nopic_need_relax (offset_expr
.X_add_symbol
))
3804 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3805 mips_isa
< 3 ? "addu" : "daddu",
3806 "d,v,t", tempreg
, breg
, GP
);
3807 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
3808 treg
, (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
3809 p
= frag_var (rs_machine_dependent
, 12, 0,
3810 RELAX_ENCODE (8, 12, 0, 8, 0, 0),
3811 offset_expr
.X_add_symbol
, (long) 0,
3814 macro_build_lui (p
, &icnt
, &offset_expr
, tempreg
);
3817 macro_build (p
, &icnt
, (expressionS
*) NULL
,
3818 mips_isa
< 3 ? "addu" : "daddu",
3819 "d,v,t", tempreg
, tempreg
, breg
);
3822 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
, treg
,
3823 (int) BFD_RELOC_LO16
, tempreg
);
3826 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
3828 /* If this is a reference to an external symbol, we want
3829 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3831 <op> $treg,0($tempreg)
3833 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3835 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
3836 <op> $treg,0($tempreg)
3837 If there is a base register, we add it to $tempreg before
3838 the <op>. If there is a constant, we stick it in the
3839 <op> instruction. We don't handle constants larger than
3840 16 bits, because we have no way to load the upper 16 bits
3841 (actually, we could handle them for the subset of cases
3842 in which we are not using $at). */
3843 assert (offset_expr
.X_op
== O_symbol
);
3844 expr1
.X_add_number
= offset_expr
.X_add_number
;
3845 offset_expr
.X_add_number
= 0;
3846 if (expr1
.X_add_number
< -0x8000
3847 || expr1
.X_add_number
>= 0x8000)
3848 as_bad ("PIC code offset overflow (max 16 signed bits)");
3850 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3851 mips_isa
< 3 ? "lw" : "ld",
3852 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
3853 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
3854 p
= frag_var (rs_machine_dependent
, 4, 0,
3855 RELAX_ENCODE (0, 4, -8, 0, 0, 0),
3856 offset_expr
.X_add_symbol
, (long) 0,
3858 macro_build (p
, &icnt
, &offset_expr
,
3859 mips_isa
< 3 ? "addiu" : "daddiu",
3860 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
3862 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3863 mips_isa
< 3 ? "addu" : "daddu",
3864 "d,v,t", tempreg
, tempreg
, breg
);
3865 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
, treg
,
3866 (int) BFD_RELOC_LO16
, tempreg
);
3868 else if (mips_pic
== SVR4_PIC
)
3872 /* If this is a reference to an external symbol, we want
3873 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
3874 addu $tempreg,$tempreg,$gp
3875 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
3876 <op> $treg,0($tempreg)
3878 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3880 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
3881 <op> $treg,0($tempreg)
3882 If there is a base register, we add it to $tempreg before
3883 the <op>. If there is a constant, we stick it in the
3884 <op> instruction. We don't handle constants larger than
3885 16 bits, because we have no way to load the upper 16 bits
3886 (actually, we could handle them for the subset of cases
3887 in which we are not using $at). */
3888 assert (offset_expr
.X_op
== O_symbol
);
3889 expr1
.X_add_number
= offset_expr
.X_add_number
;
3890 offset_expr
.X_add_number
= 0;
3891 if (expr1
.X_add_number
< -0x8000
3892 || expr1
.X_add_number
>= 0x8000)
3893 as_bad ("PIC code offset overflow (max 16 signed bits)");
3894 if (reg_needs_delay (GP
))
3899 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
3900 tempreg
, (int) BFD_RELOC_MIPS_GOT_HI16
);
3901 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3902 mips_isa
< 3 ? "addu" : "daddu",
3903 "d,v,t", tempreg
, tempreg
, GP
);
3904 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3905 mips_isa
< 3 ? "lw" : "ld",
3906 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT_LO16
,
3908 p
= frag_var (rs_machine_dependent
, 12 + gpdel
, 0,
3909 RELAX_ENCODE (12, 12 + gpdel
, gpdel
, 8 + gpdel
, 0, 0),
3910 offset_expr
.X_add_symbol
, (long) 0, (char *) NULL
);
3913 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
3916 macro_build (p
, &icnt
, &offset_expr
,
3917 mips_isa
< 3 ? "lw" : "ld",
3918 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
3920 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
3922 macro_build (p
, &icnt
, &offset_expr
,
3923 mips_isa
< 3 ? "addiu" : "daddiu",
3924 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
3926 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3927 mips_isa
< 3 ? "addu" : "daddu",
3928 "d,v,t", tempreg
, tempreg
, breg
);
3929 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
, treg
,
3930 (int) BFD_RELOC_LO16
, tempreg
);
3932 else if (mips_pic
== EMBEDDED_PIC
)
3934 /* If there is no base register, we want
3935 <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL)
3936 If there is a base register, we want
3937 addu $tempreg,$breg,$gp
3938 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GPREL)
3940 assert (offset_expr
.X_op
== O_symbol
);
3943 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
3944 treg
, (int) BFD_RELOC_MIPS_GPREL
, GP
);
3949 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3950 mips_isa
< 3 ? "addu" : "daddu",
3951 "d,v,t", tempreg
, breg
, GP
);
3952 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
3953 treg
, (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
3966 load_register (&icnt
, treg
, &imm_expr
, 0);
3970 load_register (&icnt
, treg
, &imm_expr
, 1);
3974 if (imm_expr
.X_op
== O_constant
)
3976 load_register (&icnt
, AT
, &imm_expr
, 0);
3977 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3978 "mtc1", "t,G", AT
, treg
);
3983 assert (offset_expr
.X_op
== O_symbol
3984 && strcmp (segment_name (S_GET_SEGMENT
3985 (offset_expr
.X_add_symbol
)),
3987 && offset_expr
.X_add_number
== 0);
3988 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lwc1", "T,o(b)",
3989 treg
, (int) BFD_RELOC_MIPS_LITERAL
, GP
);
3994 /* We know that sym is in the .rdata section. First we get the
3995 upper 16 bits of the address. */
3996 if (mips_pic
== NO_PIC
)
3998 /* FIXME: This won't work for a 64 bit address. */
3999 macro_build_lui ((char *) NULL
, &icnt
, &offset_expr
, AT
);
4001 else if (mips_pic
== SVR4_PIC
)
4003 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4004 mips_isa
< 3 ? "lw" : "ld",
4005 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
4007 else if (mips_pic
== EMBEDDED_PIC
)
4009 /* For embedded PIC we pick up the entire address off $gp in
4010 a single instruction. */
4011 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4012 mips_isa
< 3 ? "addiu" : "daddiu",
4013 "t,r,j", AT
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
4014 offset_expr
.X_op
= O_constant
;
4015 offset_expr
.X_add_number
= 0;
4020 /* Now we load the register(s). */
4022 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "ld", "t,o(b)",
4023 treg
, (int) BFD_RELOC_LO16
, AT
);
4026 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lw", "t,o(b)",
4027 treg
, (int) BFD_RELOC_LO16
, AT
);
4030 /* FIXME: How in the world do we deal with the possible
4032 offset_expr
.X_add_number
+= 4;
4033 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lw", "t,o(b)",
4034 treg
+ 1, (int) BFD_RELOC_LO16
, AT
);
4038 /* To avoid confusion in tc_gen_reloc, we must ensure that this
4039 does not become a variant frag. */
4040 frag_wane (frag_now
);
4046 assert (offset_expr
.X_op
== O_symbol
4047 && offset_expr
.X_add_number
== 0);
4048 s
= segment_name (S_GET_SEGMENT (offset_expr
.X_add_symbol
));
4049 if (strcmp (s
, ".lit8") == 0)
4053 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "ldc1",
4054 "T,o(b)", treg
, (int) BFD_RELOC_MIPS_LITERAL
, GP
);
4058 r
= BFD_RELOC_MIPS_LITERAL
;
4063 assert (strcmp (s
, RDATA_SECTION_NAME
) == 0);
4064 if (mips_pic
== SVR4_PIC
)
4065 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4066 mips_isa
< 3 ? "lw" : "ld",
4067 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
4070 /* FIXME: This won't work for a 64 bit address. */
4071 macro_build_lui ((char *) NULL
, &icnt
, &offset_expr
, AT
);
4076 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "ldc1",
4077 "T,o(b)", treg
, (int) BFD_RELOC_LO16
, AT
);
4079 /* To avoid confusion in tc_gen_reloc, we must ensure
4080 that this does not become a variant frag. */
4081 frag_wane (frag_now
);
4092 /* Even on a big endian machine $fn comes before $fn+1. We have
4093 to adjust when loading from memory. */
4096 assert (mips_isa
< 2);
4097 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lwc1", "T,o(b)",
4098 byte_order
== LITTLE_ENDIAN
? treg
: treg
+ 1,
4100 /* FIXME: A possible overflow which I don't know how to deal
4102 offset_expr
.X_add_number
+= 4;
4103 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lwc1", "T,o(b)",
4104 byte_order
== LITTLE_ENDIAN
? treg
+ 1 : treg
,
4107 /* To avoid confusion in tc_gen_reloc, we must ensure that this
4108 does not become a variant frag. */
4109 frag_wane (frag_now
);
4118 * The MIPS assembler seems to check for X_add_number not
4119 * being double aligned and generating:
4122 * addiu at,at,%lo(foo+1)
4125 * But, the resulting address is the same after relocation so why
4126 * generate the extra instruction?
4173 if (offset_expr
.X_op
!= O_symbol
4174 && offset_expr
.X_op
!= O_constant
)
4176 as_bad ("expression too complex");
4177 offset_expr
.X_op
= O_constant
;
4180 /* Even on a big endian machine $fn comes before $fn+1. We have
4181 to adjust when loading from memory. We set coproc if we must
4182 load $fn+1 first. */
4183 if (byte_order
== LITTLE_ENDIAN
)
4186 if (mips_pic
== NO_PIC
4187 || offset_expr
.X_op
== O_constant
)
4189 /* If this is a reference to a GP relative symbol, we want
4190 <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL)
4191 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_MIPS_GPREL)
4192 If we have a base register, we use this
4194 <op> $treg,<sym>($at) (BFD_RELOC_MIPS_GPREL)
4195 <op> $treg+1,<sym>+4($at) (BFD_RELOC_MIPS_GPREL)
4196 If this is not a GP relative symbol, we want
4197 lui $at,<sym> (BFD_RELOC_HI16_S)
4198 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
4199 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
4200 If there is a base register, we add it to $at after the
4201 lui instruction. If there is a constant, we always use
4203 if ((valueT
) offset_expr
.X_add_number
>= MAX_GPREL_OFFSET
4204 || nopic_need_relax (offset_expr
.X_add_symbol
))
4223 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4224 mips_isa
< 3 ? "addu" : "daddu",
4225 "d,v,t", AT
, breg
, GP
);
4231 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
4232 coproc
? treg
+ 1 : treg
,
4233 (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
4234 offset_expr
.X_add_number
+= 4;
4236 /* Set mips_optimize to 2 to avoid inserting an
4238 hold_mips_optimize
= mips_optimize
;
4240 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
4241 coproc
? treg
: treg
+ 1,
4242 (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
4243 mips_optimize
= hold_mips_optimize
;
4245 p
= frag_var (rs_machine_dependent
, 12 + off
, 0,
4246 RELAX_ENCODE (8 + off
, 12 + off
, 0, 4 + off
, 1,
4247 used_at
&& mips_noat
),
4248 offset_expr
.X_add_symbol
, (long) 0,
4251 /* We just generated two relocs. When tc_gen_reloc
4252 handles this case, it will skip the first reloc and
4253 handle the second. The second reloc already has an
4254 extra addend of 4, which we added above. We must
4255 subtract it out, and then subtract another 4 to make
4256 the first reloc come out right. The second reloc
4257 will come out right because we are going to add 4 to
4258 offset_expr when we build its instruction below. */
4259 offset_expr
.X_add_number
-= 8;
4260 offset_expr
.X_op
= O_constant
;
4262 macro_build_lui (p
, &icnt
, &offset_expr
, AT
);
4267 macro_build (p
, &icnt
, (expressionS
*) NULL
,
4268 mips_isa
< 3 ? "addu" : "daddu",
4269 "d,v,t", AT
, breg
, AT
);
4273 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
,
4274 coproc
? treg
+ 1 : treg
,
4275 (int) BFD_RELOC_LO16
, AT
);
4278 /* FIXME: How do we handle overflow here? */
4279 offset_expr
.X_add_number
+= 4;
4280 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
,
4281 coproc
? treg
: treg
+ 1,
4282 (int) BFD_RELOC_LO16
, AT
);
4284 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
4288 /* If this is a reference to an external symbol, we want
4289 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4294 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4296 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
4297 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
4298 If there is a base register we add it to $at before the
4299 lwc1 instructions. If there is a constant we include it
4300 in the lwc1 instructions. */
4302 expr1
.X_add_number
= offset_expr
.X_add_number
;
4303 offset_expr
.X_add_number
= 0;
4304 if (expr1
.X_add_number
< -0x8000
4305 || expr1
.X_add_number
>= 0x8000 - 4)
4306 as_bad ("PIC code offset overflow (max 16 signed bits)");
4311 frag_grow (24 + off
);
4312 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4313 mips_isa
< 3 ? "lw" : "ld",
4314 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
4315 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
4317 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4318 mips_isa
< 3 ? "addu" : "daddu",
4319 "d,v,t", AT
, breg
, AT
);
4320 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
4321 coproc
? treg
+ 1 : treg
,
4322 (int) BFD_RELOC_LO16
, AT
);
4323 expr1
.X_add_number
+= 4;
4325 /* Set mips_optimize to 2 to avoid inserting an undesired
4327 hold_mips_optimize
= mips_optimize
;
4329 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
4330 coproc
? treg
: treg
+ 1,
4331 (int) BFD_RELOC_LO16
, AT
);
4332 mips_optimize
= hold_mips_optimize
;
4334 (void) frag_var (rs_machine_dependent
, 0, 0,
4335 RELAX_ENCODE (0, 0, -16 - off
, -8, 1, 0),
4336 offset_expr
.X_add_symbol
, (long) 0,
4339 else if (mips_pic
== SVR4_PIC
)
4343 /* If this is a reference to an external symbol, we want
4344 lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16)
4346 lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16)
4351 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4353 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
4354 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
4355 If there is a base register we add it to $at before the
4356 lwc1 instructions. If there is a constant we include it
4357 in the lwc1 instructions. */
4359 expr1
.X_add_number
= offset_expr
.X_add_number
;
4360 offset_expr
.X_add_number
= 0;
4361 if (expr1
.X_add_number
< -0x8000
4362 || expr1
.X_add_number
>= 0x8000 - 4)
4363 as_bad ("PIC code offset overflow (max 16 signed bits)");
4364 if (reg_needs_delay (GP
))
4373 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
4374 AT
, (int) BFD_RELOC_MIPS_GOT_HI16
);
4375 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4376 mips_isa
< 3 ? "addu" : "daddu",
4377 "d,v,t", AT
, AT
, GP
);
4378 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4379 mips_isa
< 3 ? "lw" : "ld",
4380 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT_LO16
, AT
);
4381 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
4383 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4384 mips_isa
< 3 ? "addu" : "daddu",
4385 "d,v,t", AT
, breg
, AT
);
4386 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
4387 coproc
? treg
+ 1 : treg
,
4388 (int) BFD_RELOC_LO16
, AT
);
4389 expr1
.X_add_number
+= 4;
4391 /* Set mips_optimize to 2 to avoid inserting an undesired
4393 hold_mips_optimize
= mips_optimize
;
4395 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
4396 coproc
? treg
: treg
+ 1,
4397 (int) BFD_RELOC_LO16
, AT
);
4398 mips_optimize
= hold_mips_optimize
;
4399 expr1
.X_add_number
-= 4;
4401 p
= frag_var (rs_machine_dependent
, 16 + gpdel
+ off
, 0,
4402 RELAX_ENCODE (24 + off
, 16 + gpdel
+ off
, gpdel
,
4403 8 + gpdel
+ off
, 1, 0),
4404 offset_expr
.X_add_symbol
, (long) 0,
4408 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4411 macro_build (p
, &icnt
, &offset_expr
,
4412 mips_isa
< 3 ? "lw" : "ld",
4413 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
4415 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4419 macro_build (p
, &icnt
, (expressionS
*) NULL
,
4420 mips_isa
< 3 ? "addu" : "daddu",
4421 "d,v,t", AT
, breg
, AT
);
4424 macro_build (p
, &icnt
, &expr1
, s
, fmt
,
4425 coproc
? treg
+ 1 : treg
,
4426 (int) BFD_RELOC_LO16
, AT
);
4428 expr1
.X_add_number
+= 4;
4430 /* Set mips_optimize to 2 to avoid inserting an undesired
4432 hold_mips_optimize
= mips_optimize
;
4434 macro_build (p
, &icnt
, &expr1
, s
, fmt
,
4435 coproc
? treg
: treg
+ 1,
4436 (int) BFD_RELOC_LO16
, AT
);
4437 mips_optimize
= hold_mips_optimize
;
4439 else if (mips_pic
== EMBEDDED_PIC
)
4441 /* If there is no base register, we use
4442 <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL)
4443 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_MIPS_GPREL)
4444 If we have a base register, we use
4446 <op> $treg,<sym>($at) (BFD_RELOC_MIPS_GPREL)
4447 <op> $treg+1,<sym>+4($at) (BFD_RELOC_MIPS_GPREL)
4456 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4457 mips_isa
< 3 ? "addu" : "daddu",
4458 "d,v,t", AT
, breg
, GP
);
4463 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
4464 coproc
? treg
+ 1 : treg
,
4465 (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
4466 offset_expr
.X_add_number
+= 4;
4467 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
4468 coproc
? treg
: treg
+ 1,
4469 (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
4485 assert (mips_isa
< 3);
4486 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
4487 (int) BFD_RELOC_LO16
, breg
);
4488 offset_expr
.X_add_number
+= 4;
4489 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
+ 1,
4490 (int) BFD_RELOC_LO16
, breg
);
4492 #ifdef LOSING_COMPILER
4498 as_warn ("Macro used $at after \".set noat\"");
4503 struct mips_cl_insn
*ip
;
4505 register int treg
, sreg
, dreg
, breg
;
4520 bfd_reloc_code_real_type r
;
4523 treg
= (ip
->insn_opcode
>> 16) & 0x1f;
4524 dreg
= (ip
->insn_opcode
>> 11) & 0x1f;
4525 sreg
= breg
= (ip
->insn_opcode
>> 21) & 0x1f;
4526 mask
= ip
->insn_mo
->mask
;
4528 expr1
.X_op
= O_constant
;
4529 expr1
.X_op_symbol
= NULL
;
4530 expr1
.X_add_symbol
= NULL
;
4531 expr1
.X_add_number
= 1;
4535 #endif /* LOSING_COMPILER */
4540 macro_build ((char *) NULL
, &icnt
, NULL
,
4541 dbl
? "dmultu" : "multu",
4543 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
4549 /* The MIPS assembler some times generates shifts and adds. I'm
4550 not trying to be that fancy. GCC should do this for us
4552 load_register (&icnt
, AT
, &imm_expr
, dbl
);
4553 macro_build ((char *) NULL
, &icnt
, NULL
,
4554 dbl
? "dmult" : "mult",
4556 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
4562 mips_emit_delays ();
4564 mips_any_noreorder
= 1;
4565 macro_build ((char *) NULL
, &icnt
, NULL
,
4566 dbl
? "dmult" : "mult",
4568 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
4569 macro_build ((char *) NULL
, &icnt
, NULL
,
4570 dbl
? "dsra32" : "sra",
4571 "d,w,<", dreg
, dreg
, 31);
4572 macro_build ((char *) NULL
, &icnt
, NULL
, "mfhi", "d", AT
);
4574 macro_build ((char *) NULL
, &icnt
, NULL
, "tne", "s,t", dreg
, AT
);
4577 expr1
.X_add_number
= 8;
4578 macro_build ((char *) NULL
, &icnt
, &expr1
, "beq", "s,t,p", dreg
, AT
);
4579 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
4580 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 6);
4583 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
4589 mips_emit_delays ();
4591 mips_any_noreorder
= 1;
4592 macro_build ((char *) NULL
, &icnt
, NULL
,
4593 dbl
? "dmultu" : "multu",
4595 macro_build ((char *) NULL
, &icnt
, NULL
, "mfhi", "d", AT
);
4596 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
4598 macro_build ((char *) NULL
, &icnt
, NULL
, "tne", "s,t", AT
, 0);
4601 expr1
.X_add_number
= 8;
4602 macro_build ((char *) NULL
, &icnt
, &expr1
, "beq", "s,t,p", AT
, 0);
4603 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
4604 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 6);
4610 macro_build ((char *) NULL
, &icnt
, NULL
, "subu", "d,v,t", AT
, 0, treg
);
4611 macro_build ((char *) NULL
, &icnt
, NULL
, "srlv", "d,t,s", AT
, sreg
, AT
);
4612 macro_build ((char *) NULL
, &icnt
, NULL
, "sllv", "d,t,s", dreg
, sreg
,
4614 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
4618 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", AT
, sreg
,
4619 (int) (imm_expr
.X_add_number
& 0x1f));
4620 macro_build ((char *) NULL
, &icnt
, NULL
, "srl", "d,w,<", dreg
, sreg
,
4621 (int) ((0 - imm_expr
.X_add_number
) & 0x1f));
4622 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
4626 macro_build ((char *) NULL
, &icnt
, NULL
, "subu", "d,v,t", AT
, 0, treg
);
4627 macro_build ((char *) NULL
, &icnt
, NULL
, "sllv", "d,t,s", AT
, sreg
, AT
);
4628 macro_build ((char *) NULL
, &icnt
, NULL
, "srlv", "d,t,s", dreg
, sreg
,
4630 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
4634 macro_build ((char *) NULL
, &icnt
, NULL
, "srl", "d,w,<", AT
, sreg
,
4635 (int) (imm_expr
.X_add_number
& 0x1f));
4636 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", dreg
, sreg
,
4637 (int) ((0 - imm_expr
.X_add_number
) & 0x1f));
4638 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
4642 assert (mips_isa
< 2);
4643 /* Even on a big endian machine $fn comes before $fn+1. We have
4644 to adjust when storing to memory. */
4645 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "swc1", "T,o(b)",
4646 byte_order
== LITTLE_ENDIAN
? treg
: treg
+ 1,
4647 (int) BFD_RELOC_LO16
, breg
);
4648 offset_expr
.X_add_number
+= 4;
4649 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "swc1", "T,o(b)",
4650 byte_order
== LITTLE_ENDIAN
? treg
+ 1 : treg
,
4651 (int) BFD_RELOC_LO16
, breg
);
4656 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
4657 treg
, (int) BFD_RELOC_LO16
);
4659 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
4660 sreg
, (int) BFD_RELOC_LO16
);
4663 macro_build ((char *) NULL
, &icnt
, NULL
, "xor", "d,v,t", dreg
,
4665 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
4666 dreg
, (int) BFD_RELOC_LO16
);
4671 if (imm_expr
.X_add_number
== 0)
4673 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
4674 sreg
, (int) BFD_RELOC_LO16
);
4679 as_warn ("Instruction %s: result is always false",
4681 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
, 0);
4684 if (imm_expr
.X_add_number
>= 0 && imm_expr
.X_add_number
< 0x10000)
4686 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "xori", "t,r,i", dreg
,
4687 sreg
, (int) BFD_RELOC_LO16
);
4690 else if (imm_expr
.X_add_number
> -0x8000 && imm_expr
.X_add_number
< 0)
4692 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
4693 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
4694 mips_isa
< 3 ? "addiu" : "daddiu",
4695 "t,r,j", dreg
, sreg
,
4696 (int) BFD_RELOC_LO16
);
4701 load_register (&icnt
, AT
, &imm_expr
, 0);
4702 macro_build ((char *) NULL
, &icnt
, NULL
, "xor", "d,v,t", dreg
,
4706 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
, dreg
,
4707 (int) BFD_RELOC_LO16
);
4712 case M_SGE
: /* sreg >= treg <==> not (sreg < treg) */
4718 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, sreg
, treg
);
4719 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
4720 (int) BFD_RELOC_LO16
);
4723 case M_SGE_I
: /* sreg >= I <==> not (sreg < I) */
4725 if (imm_expr
.X_add_number
>= -0x8000 && imm_expr
.X_add_number
< 0x8000)
4727 macro_build ((char *) NULL
, &icnt
, &expr1
,
4728 mask
== M_SGE_I
? "slti" : "sltiu",
4729 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
4734 load_register (&icnt
, AT
, &imm_expr
, 0);
4735 macro_build ((char *) NULL
, &icnt
, NULL
,
4736 mask
== M_SGE_I
? "slt" : "sltu",
4737 "d,v,t", dreg
, sreg
, AT
);
4740 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
4741 (int) BFD_RELOC_LO16
);
4746 case M_SGT
: /* sreg > treg <==> treg < sreg */
4752 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, treg
, sreg
);
4755 case M_SGT_I
: /* sreg > I <==> I < sreg */
4761 load_register (&icnt
, AT
, &imm_expr
, 0);
4762 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, AT
, sreg
);
4765 case M_SLE
: /* sreg <= treg <==> treg >= sreg <==> not (treg < sreg) */
4771 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, treg
, sreg
);
4772 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
4773 (int) BFD_RELOC_LO16
);
4776 case M_SLE_I
: /* sreg <= I <==> I >= sreg <==> not (I < sreg) */
4782 load_register (&icnt
, AT
, &imm_expr
, 0);
4783 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, AT
, sreg
);
4784 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
4785 (int) BFD_RELOC_LO16
);
4789 if (imm_expr
.X_add_number
>= -0x8000 && imm_expr
.X_add_number
< 0x8000)
4791 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "slti", "t,r,j",
4792 dreg
, sreg
, (int) BFD_RELOC_LO16
);
4795 load_register (&icnt
, AT
, &imm_expr
, 0);
4796 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", dreg
, sreg
, AT
);
4800 if (imm_expr
.X_add_number
>= -0x8000 && imm_expr
.X_add_number
< 0x8000)
4802 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "sltiu", "t,r,j",
4803 dreg
, sreg
, (int) BFD_RELOC_LO16
);
4806 load_register (&icnt
, AT
, &imm_expr
, 0);
4807 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, sreg
,
4813 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0,
4816 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0,
4820 macro_build ((char *) NULL
, &icnt
, NULL
, "xor", "d,v,t", dreg
,
4822 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0,
4828 if (imm_expr
.X_add_number
== 0)
4830 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0,
4836 as_warn ("Instruction %s: result is always true",
4838 macro_build ((char *) NULL
, &icnt
, &expr1
,
4839 mips_isa
< 3 ? "addiu" : "daddiu",
4840 "t,r,j", dreg
, 0, (int) BFD_RELOC_LO16
);
4843 if (imm_expr
.X_add_number
>= 0 && imm_expr
.X_add_number
< 0x10000)
4845 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "xori", "t,r,i",
4846 dreg
, sreg
, (int) BFD_RELOC_LO16
);
4849 else if (imm_expr
.X_add_number
> -0x8000 && imm_expr
.X_add_number
< 0)
4851 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
4852 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
4853 mips_isa
< 3 ? "addiu" : "daddiu",
4854 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
4859 load_register (&icnt
, AT
, &imm_expr
, 0);
4860 macro_build ((char *) NULL
, &icnt
, NULL
, "xor", "d,v,t", dreg
,
4864 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0, dreg
);
4872 if (imm_expr
.X_add_number
> -0x8000 && imm_expr
.X_add_number
<= 0x8000)
4874 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
4875 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
4876 dbl
? "daddi" : "addi",
4877 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
4880 load_register (&icnt
, AT
, &imm_expr
, dbl
);
4881 macro_build ((char *) NULL
, &icnt
, NULL
,
4882 dbl
? "dsub" : "sub",
4883 "d,v,t", dreg
, sreg
, AT
);
4889 if (imm_expr
.X_add_number
> -0x8000 && imm_expr
.X_add_number
<= 0x8000)
4891 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
4892 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
4893 dbl
? "daddiu" : "addiu",
4894 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
4897 load_register (&icnt
, AT
, &imm_expr
, dbl
);
4898 macro_build ((char *) NULL
, &icnt
, NULL
,
4899 dbl
? "dsubu" : "subu",
4900 "d,v,t", dreg
, sreg
, AT
);
4921 load_register (&icnt
, AT
, &imm_expr
, 0);
4922 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "s,t", sreg
, AT
);
4927 assert (mips_isa
< 2);
4928 sreg
= (ip
->insn_opcode
>> 11) & 0x1f; /* floating reg */
4929 dreg
= (ip
->insn_opcode
>> 06) & 0x1f; /* floating reg */
4932 * Is the double cfc1 instruction a bug in the mips assembler;
4933 * or is there a reason for it?
4935 mips_emit_delays ();
4937 mips_any_noreorder
= 1;
4938 macro_build ((char *) NULL
, &icnt
, NULL
, "cfc1", "t,G", treg
, 31);
4939 macro_build ((char *) NULL
, &icnt
, NULL
, "cfc1", "t,G", treg
, 31);
4940 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "");
4941 expr1
.X_add_number
= 3;
4942 macro_build ((char *) NULL
, &icnt
, &expr1
, "ori", "t,r,i", AT
, treg
,
4943 (int) BFD_RELOC_LO16
);
4944 expr1
.X_add_number
= 2;
4945 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", AT
, AT
,
4946 (int) BFD_RELOC_LO16
);
4947 macro_build ((char *) NULL
, &icnt
, NULL
, "ctc1", "t,G", AT
, 31);
4948 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "");
4949 macro_build ((char *) NULL
, &icnt
, NULL
,
4950 mask
== M_TRUNCWD
? "cvt.w.d" : "cvt.w.s", "D,S", dreg
, sreg
);
4951 macro_build ((char *) NULL
, &icnt
, NULL
, "ctc1", "t,G", treg
, 31);
4952 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "");
4962 if (offset_expr
.X_add_number
>= 0x7fff)
4963 as_bad ("operand overflow");
4964 /* avoid load delay */
4965 if (byte_order
== LITTLE_ENDIAN
)
4966 offset_expr
.X_add_number
+= 1;
4967 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
4968 (int) BFD_RELOC_LO16
, breg
);
4969 if (byte_order
== LITTLE_ENDIAN
)
4970 offset_expr
.X_add_number
-= 1;
4972 offset_expr
.X_add_number
+= 1;
4973 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lbu", "t,o(b)", AT
,
4974 (int) BFD_RELOC_LO16
, breg
);
4975 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", treg
, treg
, 8);
4976 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", treg
, treg
, AT
);
4989 if (offset_expr
.X_add_number
>= 0x8000 - off
)
4990 as_bad ("operand overflow");
4991 if (byte_order
== LITTLE_ENDIAN
)
4992 offset_expr
.X_add_number
+= off
;
4993 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
4994 (int) BFD_RELOC_LO16
, breg
);
4995 if (byte_order
== LITTLE_ENDIAN
)
4996 offset_expr
.X_add_number
-= off
;
4998 offset_expr
.X_add_number
+= off
;
4999 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s2
, "t,o(b)", treg
,
5000 (int) BFD_RELOC_LO16
, breg
);
5013 load_address (&icnt
, AT
, &offset_expr
);
5015 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5016 mips_isa
< 3 ? "addu" : "daddu",
5017 "d,v,t", AT
, AT
, breg
);
5018 if (byte_order
== LITTLE_ENDIAN
)
5019 expr1
.X_add_number
= off
;
5021 expr1
.X_add_number
= 0;
5022 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, "t,o(b)", treg
,
5023 (int) BFD_RELOC_LO16
, AT
);
5024 if (byte_order
== LITTLE_ENDIAN
)
5025 expr1
.X_add_number
= 0;
5027 expr1
.X_add_number
= off
;
5028 macro_build ((char *) NULL
, &icnt
, &expr1
, s2
, "t,o(b)", treg
,
5029 (int) BFD_RELOC_LO16
, AT
);
5034 load_address (&icnt
, AT
, &offset_expr
);
5036 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5037 mips_isa
< 3 ? "addu" : "daddu",
5038 "d,v,t", AT
, AT
, breg
);
5039 if (byte_order
== BIG_ENDIAN
)
5040 expr1
.X_add_number
= 0;
5041 macro_build ((char *) NULL
, &icnt
, &expr1
,
5042 mask
== M_ULH_A
? "lb" : "lbu", "t,o(b)", treg
,
5043 (int) BFD_RELOC_LO16
, AT
);
5044 if (byte_order
== BIG_ENDIAN
)
5045 expr1
.X_add_number
= 1;
5047 expr1
.X_add_number
= 0;
5048 macro_build ((char *) NULL
, &icnt
, &expr1
, "lbu", "t,o(b)", AT
,
5049 (int) BFD_RELOC_LO16
, AT
);
5050 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", treg
,
5052 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", treg
,
5057 if (offset_expr
.X_add_number
>= 0x7fff)
5058 as_bad ("operand overflow");
5059 if (byte_order
== BIG_ENDIAN
)
5060 offset_expr
.X_add_number
+= 1;
5061 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "sb", "t,o(b)", treg
,
5062 (int) BFD_RELOC_LO16
, breg
);
5063 macro_build ((char *) NULL
, &icnt
, NULL
, "srl", "d,w,<", AT
, treg
, 8);
5064 if (byte_order
== BIG_ENDIAN
)
5065 offset_expr
.X_add_number
-= 1;
5067 offset_expr
.X_add_number
+= 1;
5068 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "sb", "t,o(b)", AT
,
5069 (int) BFD_RELOC_LO16
, breg
);
5082 if (offset_expr
.X_add_number
>= 0x8000 - off
)
5083 as_bad ("operand overflow");
5084 if (byte_order
== LITTLE_ENDIAN
)
5085 offset_expr
.X_add_number
+= off
;
5086 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
5087 (int) BFD_RELOC_LO16
, breg
);
5088 if (byte_order
== LITTLE_ENDIAN
)
5089 offset_expr
.X_add_number
-= off
;
5091 offset_expr
.X_add_number
+= off
;
5092 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s2
, "t,o(b)", treg
,
5093 (int) BFD_RELOC_LO16
, breg
);
5106 load_address (&icnt
, AT
, &offset_expr
);
5108 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5109 mips_isa
< 3 ? "addu" : "daddu",
5110 "d,v,t", AT
, AT
, breg
);
5111 if (byte_order
== LITTLE_ENDIAN
)
5112 expr1
.X_add_number
= off
;
5114 expr1
.X_add_number
= 0;
5115 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, "t,o(b)", treg
,
5116 (int) BFD_RELOC_LO16
, AT
);
5117 if (byte_order
== LITTLE_ENDIAN
)
5118 expr1
.X_add_number
= 0;
5120 expr1
.X_add_number
= off
;
5121 macro_build ((char *) NULL
, &icnt
, &expr1
, s2
, "t,o(b)", treg
,
5122 (int) BFD_RELOC_LO16
, AT
);
5126 load_address (&icnt
, AT
, &offset_expr
);
5128 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5129 mips_isa
< 3 ? "addu" : "daddu",
5130 "d,v,t", AT
, AT
, breg
);
5131 if (byte_order
== LITTLE_ENDIAN
)
5132 expr1
.X_add_number
= 0;
5133 macro_build ((char *) NULL
, &icnt
, &expr1
, "sb", "t,o(b)", treg
,
5134 (int) BFD_RELOC_LO16
, AT
);
5135 macro_build ((char *) NULL
, &icnt
, NULL
, "srl", "d,w,<", treg
,
5137 if (byte_order
== LITTLE_ENDIAN
)
5138 expr1
.X_add_number
= 1;
5140 expr1
.X_add_number
= 0;
5141 macro_build ((char *) NULL
, &icnt
, &expr1
, "sb", "t,o(b)", treg
,
5142 (int) BFD_RELOC_LO16
, AT
);
5143 if (byte_order
== LITTLE_ENDIAN
)
5144 expr1
.X_add_number
= 0;
5146 expr1
.X_add_number
= 1;
5147 macro_build ((char *) NULL
, &icnt
, &expr1
, "lbu", "t,o(b)", AT
,
5148 (int) BFD_RELOC_LO16
, AT
);
5149 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", treg
,
5151 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", treg
,
5156 as_bad ("Macro %s not implemented yet", ip
->insn_mo
->name
);
5160 as_warn ("Macro used $at after \".set noat\"");
5163 /* This routine assembles an instruction into its binary format. As a
5164 side effect, it sets one of the global variables imm_reloc or
5165 offset_reloc to the type of relocation to do if one of the operands
5166 is an address expression. */
5171 struct mips_cl_insn
*ip
;
5176 struct mips_opcode
*insn
;
5179 unsigned int lastregno
= 0;
5184 for (s
= str
; islower (*s
) || (*s
>= '0' && *s
<= '3') || *s
== '6' || *s
== '.'; ++s
)
5196 as_fatal ("Unknown opcode: `%s'", str
);
5198 if ((insn
= (struct mips_opcode
*) hash_find (op_hash
, str
)) == NULL
)
5200 insn_error
= "unrecognized opcode";
5208 assert (strcmp (insn
->name
, str
) == 0);
5210 if (insn
->pinfo
== INSN_MACRO
)
5211 insn_isa
= insn
->match
;
5212 else if ((insn
->pinfo
& INSN_ISA
) == INSN_ISA2
)
5214 else if ((insn
->pinfo
& INSN_ISA
) == INSN_ISA3
)
5216 else if ((insn
->pinfo
& INSN_ISA
) == INSN_ISA4
)
5221 if (insn_isa
> mips_isa
5222 || ((insn
->pinfo
& INSN_ISA
) == INSN_4650
5224 || ((insn
->pinfo
& INSN_ISA
) == INSN_4010
5226 || ((insn
->pinfo
& INSN_ISA
) == INSN_4100
5229 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
]
5230 && strcmp (insn
->name
, insn
[1].name
) == 0)
5235 if (insn_isa
<= mips_isa
)
5236 insn_error
= "opcode not supported on this processor";
5239 static char buf
[100];
5241 sprintf (buf
, "opcode requires -mips%d or greater", insn_isa
);
5248 ip
->insn_opcode
= insn
->match
;
5249 for (args
= insn
->args
;; ++args
)
5255 case '\0': /* end of args */
5268 ip
->insn_opcode
|= lastregno
<< 21;
5273 ip
->insn_opcode
|= lastregno
<< 16;
5277 ip
->insn_opcode
|= lastregno
<< 11;
5283 /* handle optional base register.
5284 Either the base register is omitted or
5285 we must have a left paren. */
5286 /* this is dependent on the next operand specifier
5287 is a 'b' for base register */
5288 assert (args
[1] == 'b');
5292 case ')': /* these must match exactly */
5297 case '<': /* must be at least one digit */
5299 * According to the manual, if the shift amount is greater
5300 * than 31 or less than 0 the the shift amount should be
5301 * mod 32. In reality the mips assembler issues an error.
5302 * We issue a warning and mask out all but the low 5 bits.
5304 my_getExpression (&imm_expr
, s
);
5305 check_absolute_expr (ip
, &imm_expr
);
5306 if ((unsigned long) imm_expr
.X_add_number
> 31)
5308 as_warn ("Improper shift amount (%ld)",
5309 (long) imm_expr
.X_add_number
);
5310 imm_expr
.X_add_number
= imm_expr
.X_add_number
& 0x1f;
5312 ip
->insn_opcode
|= imm_expr
.X_add_number
<< 6;
5313 imm_expr
.X_op
= O_absent
;
5317 case '>': /* shift amount minus 32 */
5318 my_getExpression (&imm_expr
, s
);
5319 check_absolute_expr (ip
, &imm_expr
);
5320 if ((unsigned long) imm_expr
.X_add_number
< 32
5321 || (unsigned long) imm_expr
.X_add_number
> 63)
5323 ip
->insn_opcode
|= (imm_expr
.X_add_number
- 32) << 6;
5324 imm_expr
.X_op
= O_absent
;
5328 case 'k': /* cache code */
5329 case 'h': /* prefx code */
5330 my_getExpression (&imm_expr
, s
);
5331 check_absolute_expr (ip
, &imm_expr
);
5332 if ((unsigned long) imm_expr
.X_add_number
> 31)
5334 as_warn ("Invalid value for `%s' (%lu)",
5336 (unsigned long) imm_expr
.X_add_number
);
5337 imm_expr
.X_add_number
&= 0x1f;
5340 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_CACHE
;
5342 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_PREFX
;
5343 imm_expr
.X_op
= O_absent
;
5347 case 'c': /* break code */
5348 my_getExpression (&imm_expr
, s
);
5349 check_absolute_expr (ip
, &imm_expr
);
5350 if ((unsigned) imm_expr
.X_add_number
> 1023)
5351 as_warn ("Illegal break code (%ld)",
5352 (long) imm_expr
.X_add_number
);
5353 ip
->insn_opcode
|= imm_expr
.X_add_number
<< 16;
5354 imm_expr
.X_op
= O_absent
;
5358 case 'B': /* syscall code */
5359 my_getExpression (&imm_expr
, s
);
5360 check_absolute_expr (ip
, &imm_expr
);
5361 if ((unsigned) imm_expr
.X_add_number
> 0xfffff)
5362 as_warn ("Illegal syscall code (%ld)",
5363 (long) imm_expr
.X_add_number
);
5364 ip
->insn_opcode
|= imm_expr
.X_add_number
<< 6;
5365 imm_expr
.X_op
= O_absent
;
5369 case 'C': /* Coprocessor code */
5370 my_getExpression (&imm_expr
, s
);
5371 check_absolute_expr (ip
, &imm_expr
);
5372 if ((unsigned long) imm_expr
.X_add_number
>= (1<<25))
5374 as_warn ("Coproccesor code > 25 bits (%ld)",
5375 (long) imm_expr
.X_add_number
);
5376 imm_expr
.X_add_number
&= ((1<<25) - 1);
5378 ip
->insn_opcode
|= imm_expr
.X_add_number
;
5379 imm_expr
.X_op
= O_absent
;
5383 case 'b': /* base register */
5384 case 'd': /* destination register */
5385 case 's': /* source register */
5386 case 't': /* target register */
5387 case 'r': /* both target and source */
5388 case 'v': /* both dest and source */
5389 case 'w': /* both dest and target */
5390 case 'E': /* coprocessor target register */
5391 case 'G': /* coprocessor destination register */
5392 case 'x': /* ignore register name */
5393 case 'z': /* must be zero register */
5407 while (isdigit (*s
));
5409 as_bad ("Invalid register number (%d)", regno
);
5411 else if (*args
== 'E' || *args
== 'G')
5415 if (s
[1] == 'f' && s
[2] == 'p')
5420 else if (s
[1] == 's' && s
[2] == 'p')
5425 else if (s
[1] == 'g' && s
[2] == 'p')
5430 else if (s
[1] == 'a' && s
[2] == 't')
5435 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '0')
5440 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '1')
5452 as_warn ("Used $at without \".set noat\"");
5458 if (c
== 'r' || c
== 'v' || c
== 'w')
5465 /* 'z' only matches $0. */
5466 if (c
== 'z' && regno
!= 0)
5474 ip
->insn_opcode
|= regno
<< 21;
5478 ip
->insn_opcode
|= regno
<< 11;
5483 ip
->insn_opcode
|= regno
<< 16;
5486 /* This case exists because on the r3000 trunc
5487 expands into a macro which requires a gp
5488 register. On the r6000 or r4000 it is
5489 assembled into a single instruction which
5490 ignores the register. Thus the insn version
5491 is MIPS_ISA2 and uses 'x', and the macro
5492 version is MIPS_ISA1 and uses 't'. */
5495 /* This case is for the div instruction, which
5496 acts differently if the destination argument
5497 is $0. This only matches $0, and is checked
5498 outside the switch. */
5509 ip
->insn_opcode
|= lastregno
<< 21;
5512 ip
->insn_opcode
|= lastregno
<< 16;
5517 case 'D': /* floating point destination register */
5518 case 'S': /* floating point source register */
5519 case 'T': /* floating point target register */
5520 case 'R': /* floating point source register */
5524 if (s
[0] == '$' && s
[1] == 'f' && isdigit (s
[2]))
5534 while (isdigit (*s
));
5537 as_bad ("Invalid float register number (%d)", regno
);
5539 if ((regno
& 1) != 0
5541 && ! (strcmp (str
, "mtc1") == 0 ||
5542 strcmp (str
, "mfc1") == 0 ||
5543 strcmp (str
, "lwc1") == 0 ||
5544 strcmp (str
, "swc1") == 0))
5545 as_warn ("Float register should be even, was %d",
5553 if (c
== 'V' || c
== 'W')
5563 ip
->insn_opcode
|= regno
<< 6;
5567 ip
->insn_opcode
|= regno
<< 11;
5571 ip
->insn_opcode
|= regno
<< 16;
5574 ip
->insn_opcode
|= regno
<< 21;
5583 ip
->insn_opcode
|= lastregno
<< 11;
5586 ip
->insn_opcode
|= lastregno
<< 16;
5592 my_getExpression (&imm_expr
, s
);
5593 if (imm_expr
.X_op
!= O_big
5594 && imm_expr
.X_op
!= O_constant
)
5595 insn_error
= "absolute expression required";
5600 my_getExpression (&offset_expr
, s
);
5601 imm_reloc
= BFD_RELOC_32
;
5613 unsigned char temp
[8];
5615 unsigned int length
;
5620 /* These only appear as the last operand in an
5621 instruction, and every instruction that accepts
5622 them in any variant accepts them in all variants.
5623 This means we don't have to worry about backing out
5624 any changes if the instruction does not match.
5626 The difference between them is the size of the
5627 floating point constant and where it goes. For 'F'
5628 and 'L' the constant is 64 bits; for 'f' and 'l' it
5629 is 32 bits. Where the constant is placed is based
5630 on how the MIPS assembler does things:
5633 f -- immediate value
5636 The .lit4 and .lit8 sections are only used if
5637 permitted by the -G argument.
5639 When generating embedded PIC code, we use the
5640 .lit8 section but not the .lit4 section (we can do
5641 .lit4 inline easily; we need to put .lit8
5642 somewhere in the data segment, and using .lit8
5643 permits the linker to eventually combine identical
5646 f64
= *args
== 'F' || *args
== 'L';
5648 save_in
= input_line_pointer
;
5649 input_line_pointer
= s
;
5650 err
= md_atof (f64
? 'd' : 'f', (char *) temp
, &len
);
5652 s
= input_line_pointer
;
5653 input_line_pointer
= save_in
;
5654 if (err
!= NULL
&& *err
!= '\0')
5656 as_bad ("Bad floating point constant: %s", err
);
5657 memset (temp
, '\0', sizeof temp
);
5658 length
= f64
? 8 : 4;
5661 assert (length
== (f64
? 8 : 4));
5665 && (! USE_GLOBAL_POINTER_OPT
5666 || mips_pic
== EMBEDDED_PIC
5667 || g_switch_value
< 4)
5670 imm_expr
.X_op
= O_constant
;
5671 if (byte_order
== LITTLE_ENDIAN
)
5672 imm_expr
.X_add_number
=
5673 (((((((int) temp
[3] << 8)
5678 imm_expr
.X_add_number
=
5679 (((((((int) temp
[0] << 8)
5686 const char *newname
;
5689 /* Switch to the right section. */
5691 subseg
= now_subseg
;
5694 default: /* unused default case avoids warnings. */
5696 newname
= RDATA_SECTION_NAME
;
5697 if (USE_GLOBAL_POINTER_OPT
&& g_switch_value
>= 8)
5701 newname
= RDATA_SECTION_NAME
;
5704 assert (!USE_GLOBAL_POINTER_OPT
5705 || g_switch_value
>= 4);
5709 new_seg
= subseg_new (newname
, (subsegT
) 0);
5710 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
5711 bfd_set_section_flags (stdoutput
, new_seg
,
5716 frag_align (*args
== 'l' ? 2 : 3, 0);
5717 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
5718 record_alignment (new_seg
, 4);
5720 record_alignment (new_seg
, *args
== 'l' ? 2 : 3);
5722 as_bad ("Can't use floating point insn in this section");
5724 /* Set the argument to the current address in the
5726 offset_expr
.X_op
= O_symbol
;
5727 offset_expr
.X_add_symbol
=
5728 symbol_new ("L0\001", now_seg
,
5729 (valueT
) frag_now_fix (), frag_now
);
5730 offset_expr
.X_add_number
= 0;
5732 /* Put the floating point number into the section. */
5733 p
= frag_more ((int) length
);
5734 memcpy (p
, temp
, length
);
5736 /* Switch back to the original section. */
5737 subseg_set (seg
, subseg
);
5742 case 'i': /* 16 bit unsigned immediate */
5743 case 'j': /* 16 bit signed immediate */
5744 imm_reloc
= BFD_RELOC_LO16
;
5745 c
= my_getSmallExpression (&imm_expr
, s
);
5750 if (imm_expr
.X_op
== O_constant
)
5751 imm_expr
.X_add_number
=
5752 (imm_expr
.X_add_number
>> 16) & 0xffff;
5755 imm_reloc
= BFD_RELOC_HI16_S
;
5756 imm_unmatched_hi
= true;
5759 imm_reloc
= BFD_RELOC_HI16
;
5764 if ((c
== '\0' && imm_expr
.X_op
!= O_constant
)
5765 || ((imm_expr
.X_add_number
< 0
5766 || imm_expr
.X_add_number
>= 0x10000)
5767 && imm_expr
.X_op
== O_constant
))
5769 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
5770 !strcmp (insn
->name
, insn
[1].name
))
5772 if (imm_expr
.X_op
!= O_constant
5773 && imm_expr
.X_op
!= O_big
)
5774 insn_error
= "absolute expression required";
5776 as_bad ("16 bit expression not in range 0..65535");
5784 /* The upper bound should be 0x8000, but
5785 unfortunately the MIPS assembler accepts numbers
5786 from 0x8000 to 0xffff and sign extends them, and
5787 we want to be compatible. We only permit this
5788 extended range for an instruction which does not
5789 provide any further alternates, since those
5790 alternates may handle other cases. People should
5791 use the numbers they mean, rather than relying on
5792 a mysterious sign extension. */
5793 more
= (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
5794 strcmp (insn
->name
, insn
[1].name
) == 0);
5799 if ((c
== '\0' && imm_expr
.X_op
!= O_constant
)
5800 || ((imm_expr
.X_add_number
< -0x8000
5801 || imm_expr
.X_add_number
>= max
)
5802 && imm_expr
.X_op
== O_constant
)
5804 && imm_expr
.X_add_number
< 0
5806 && imm_expr
.X_unsigned
5807 && sizeof (imm_expr
.X_add_number
) <= 4))
5811 if (imm_expr
.X_op
!= O_constant
5812 && imm_expr
.X_op
!= O_big
)
5813 insn_error
= "absolute expression required";
5815 as_bad ("16 bit expression not in range -32768..32767");
5821 case 'o': /* 16 bit offset */
5822 c
= my_getSmallExpression (&offset_expr
, s
);
5824 /* If this value won't fit into a 16 bit offset, then go
5825 find a macro that will generate the 32 bit offset
5826 code pattern. As a special hack, we accept the
5827 difference of two local symbols as a constant. This
5828 is required to suppose embedded PIC switches, which
5829 use an instruction which looks like
5830 lw $4,$L12-$LS12($4)
5831 The problem with handling this in a more general
5832 fashion is that the macro function doesn't expect to
5833 see anything which can be handled in a single
5834 constant instruction. */
5836 && (offset_expr
.X_op
!= O_constant
5837 || offset_expr
.X_add_number
>= 0x8000
5838 || offset_expr
.X_add_number
< -0x8000)
5839 && (mips_pic
!= EMBEDDED_PIC
5840 || offset_expr
.X_op
!= O_subtract
5841 || now_seg
!= text_section
5842 || (S_GET_SEGMENT (offset_expr
.X_op_symbol
)
5846 offset_reloc
= BFD_RELOC_LO16
;
5847 if (c
== 'h' || c
== 'H')
5849 assert (offset_expr
.X_op
== O_constant
);
5850 offset_expr
.X_add_number
=
5851 (offset_expr
.X_add_number
>> 16) & 0xffff;
5856 case 'p': /* pc relative offset */
5857 offset_reloc
= BFD_RELOC_16_PCREL_S2
;
5858 my_getExpression (&offset_expr
, s
);
5862 case 'u': /* upper 16 bits */
5863 c
= my_getSmallExpression (&imm_expr
, s
);
5864 if (imm_expr
.X_op
== O_constant
5865 && (imm_expr
.X_add_number
< 0
5866 || imm_expr
.X_add_number
>= 0x10000))
5867 as_bad ("lui expression not in range 0..65535");
5868 imm_reloc
= BFD_RELOC_LO16
;
5873 if (imm_expr
.X_op
== O_constant
)
5874 imm_expr
.X_add_number
=
5875 (imm_expr
.X_add_number
>> 16) & 0xffff;
5878 imm_reloc
= BFD_RELOC_HI16_S
;
5879 imm_unmatched_hi
= true;
5882 imm_reloc
= BFD_RELOC_HI16
;
5888 case 'a': /* 26 bit address */
5889 my_getExpression (&offset_expr
, s
);
5891 offset_reloc
= BFD_RELOC_MIPS_JMP
;
5894 case 'N': /* 3 bit branch condition code */
5895 case 'M': /* 3 bit compare condition code */
5896 if (strncmp (s
, "$fcc", 4) != 0)
5906 while (isdigit (*s
));
5908 as_bad ("invalid condition code register $fcc%d", regno
);
5910 ip
->insn_opcode
|= regno
<< OP_SH_BCC
;
5912 ip
->insn_opcode
|= regno
<< OP_SH_CCC
;
5916 fprintf (stderr
, "bad char = '%c'\n", *args
);
5921 /* Args don't match. */
5922 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
5923 !strcmp (insn
->name
, insn
[1].name
))
5929 insn_error
= "illegal operands";
5938 my_getSmallExpression (ep
, str
)
5949 ((str
[1] == 'h' && str
[2] == 'i')
5950 || (str
[1] == 'H' && str
[2] == 'I')
5951 || (str
[1] == 'l' && str
[2] == 'o'))
5963 * A small expression may be followed by a base register.
5964 * Scan to the end of this operand, and then back over a possible
5965 * base register. Then scan the small expression up to that
5966 * point. (Based on code in sparc.c...)
5968 for (sp
= str
; *sp
&& *sp
!= ','; sp
++)
5970 if (sp
- 4 >= str
&& sp
[-1] == RP
)
5972 if (isdigit (sp
[-2]))
5974 for (sp
-= 3; sp
>= str
&& isdigit (*sp
); sp
--)
5976 if (*sp
== '$' && sp
> str
&& sp
[-1] == LP
)
5982 else if (sp
- 5 >= str
5985 && ((sp
[-3] == 'f' && sp
[-2] == 'p')
5986 || (sp
[-3] == 's' && sp
[-2] == 'p')
5987 || (sp
[-3] == 'g' && sp
[-2] == 'p')
5988 || (sp
[-3] == 'a' && sp
[-2] == 't')))
5994 /* no expression means zero offset */
5997 /* %xx(reg) is an error */
5998 ep
->X_op
= O_absent
;
6003 ep
->X_op
= O_constant
;
6006 ep
->X_add_symbol
= NULL
;
6007 ep
->X_op_symbol
= NULL
;
6008 ep
->X_add_number
= 0;
6013 my_getExpression (ep
, str
);
6020 my_getExpression (ep
, str
);
6021 return c
; /* => %hi or %lo encountered */
6025 my_getExpression (ep
, str
)
6031 save_in
= input_line_pointer
;
6032 input_line_pointer
= str
;
6034 expr_end
= input_line_pointer
;
6035 input_line_pointer
= save_in
;
6038 /* Turn a string in input_line_pointer into a floating point constant
6039 of type type, and store the appropriate bytes in *litP. The number
6040 of LITTLENUMS emitted is stored in *sizeP . An error message is
6041 returned, or NULL on OK. */
6044 md_atof (type
, litP
, sizeP
)
6050 LITTLENUM_TYPE words
[4];
6066 return "bad call to md_atof";
6069 t
= atof_ieee (input_line_pointer
, type
, words
);
6071 input_line_pointer
= t
;
6075 if (byte_order
== LITTLE_ENDIAN
)
6077 for (i
= prec
- 1; i
>= 0; i
--)
6079 md_number_to_chars (litP
, (valueT
) words
[i
], 2);
6085 for (i
= 0; i
< prec
; i
++)
6087 md_number_to_chars (litP
, (valueT
) words
[i
], 2);
6096 md_number_to_chars (buf
, val
, n
)
6104 number_to_chars_littleendian (buf
, val
, n
);
6108 number_to_chars_bigendian (buf
, val
, n
);
6116 CONST
char *md_shortopts
= "O::g::G:";
6118 struct option md_longopts
[] = {
6119 #define OPTION_MIPS1 (OPTION_MD_BASE + 1)
6120 {"mips0", no_argument
, NULL
, OPTION_MIPS1
},
6121 {"mips1", no_argument
, NULL
, OPTION_MIPS1
},
6122 #define OPTION_MIPS2 (OPTION_MD_BASE + 2)
6123 {"mips2", no_argument
, NULL
, OPTION_MIPS2
},
6124 #define OPTION_MIPS3 (OPTION_MD_BASE + 3)
6125 {"mips3", no_argument
, NULL
, OPTION_MIPS3
},
6126 #define OPTION_MIPS4 (OPTION_MD_BASE + 4)
6127 {"mips4", no_argument
, NULL
, OPTION_MIPS4
},
6128 #define OPTION_MCPU (OPTION_MD_BASE + 5)
6129 {"mcpu", required_argument
, NULL
, OPTION_MCPU
},
6130 #define OPTION_MEMBEDDED_PIC (OPTION_MD_BASE + 6)
6131 {"membedded-pic", no_argument
, NULL
, OPTION_MEMBEDDED_PIC
},
6132 #define OPTION_TRAP (OPTION_MD_BASE + 9)
6133 {"trap", no_argument
, NULL
, OPTION_TRAP
},
6134 {"no-break", no_argument
, NULL
, OPTION_TRAP
},
6135 #define OPTION_BREAK (OPTION_MD_BASE + 10)
6136 {"break", no_argument
, NULL
, OPTION_BREAK
},
6137 {"no-trap", no_argument
, NULL
, OPTION_BREAK
},
6138 #define OPTION_EB (OPTION_MD_BASE + 11)
6139 {"EB", no_argument
, NULL
, OPTION_EB
},
6140 #define OPTION_EL (OPTION_MD_BASE + 12)
6141 {"EL", no_argument
, NULL
, OPTION_EL
},
6142 #define OPTION_M4650 (OPTION_MD_BASE + 13)
6143 {"m4650", no_argument
, NULL
, OPTION_M4650
},
6144 #define OPTION_NO_M4650 (OPTION_MD_BASE + 14)
6145 {"no-m4650", no_argument
, NULL
, OPTION_NO_M4650
},
6146 #define OPTION_M4010 (OPTION_MD_BASE + 15)
6147 {"m4010", no_argument
, NULL
, OPTION_M4010
},
6148 #define OPTION_NO_M4010 (OPTION_MD_BASE + 16)
6149 {"no-m4010", no_argument
, NULL
, OPTION_NO_M4010
},
6150 #define OPTION_M4100 (OPTION_MD_BASE + 17)
6151 {"m4100", no_argument
, NULL
, OPTION_M4100
},
6152 #define OPTION_NO_M4100 (OPTION_MD_BASE + 18)
6153 {"no-m4100", no_argument
, NULL
, OPTION_NO_M4100
},
6155 #define OPTION_CALL_SHARED (OPTION_MD_BASE + 7)
6156 #define OPTION_NON_SHARED (OPTION_MD_BASE + 8)
6157 #define OPTION_XGOT (OPTION_MD_BASE + 19)
6158 #define OPTION_32 (OPTION_MD_BASE + 20)
6159 #define OPTION_64 (OPTION_MD_BASE + 21)
6161 {"KPIC", no_argument
, NULL
, OPTION_CALL_SHARED
},
6162 {"xgot", no_argument
, NULL
, OPTION_XGOT
},
6163 {"call_shared", no_argument
, NULL
, OPTION_CALL_SHARED
},
6164 {"non_shared", no_argument
, NULL
, OPTION_NON_SHARED
},
6165 {"32", no_argument
, NULL
, OPTION_32
},
6166 {"64", no_argument
, NULL
, OPTION_64
},
6169 {NULL
, no_argument
, NULL
, 0}
6171 size_t md_longopts_size
= sizeof(md_longopts
);
6174 md_parse_option (c
, arg
)
6189 target_big_endian
= 1;
6193 target_big_endian
= 0;
6197 if (arg
&& arg
[1] == '0')
6207 mips_debug
= atoi (arg
);
6208 /* When the MIPS assembler sees -g or -g2, it does not do
6209 optimizations which limit full symbolic debugging. We take
6210 that to be equivalent to -O0. */
6211 if (mips_debug
== 2)
6243 /* Identify the processor type */
6245 if (strcmp (p
, "default") == 0
6246 || strcmp (p
, "DEFAULT") == 0)
6252 /* We need to cope with the various "vr" prefixes for the 4300
6254 if (*p
== 'v' || *p
== 'V')
6260 if (*p
== 'r' || *p
== 'R')
6267 if (strcmp (p
, "10000") == 0
6268 || strcmp (p
, "10k") == 0
6269 || strcmp (p
, "10K") == 0)
6274 if (strcmp (p
, "2000") == 0
6275 || strcmp (p
, "2k") == 0
6276 || strcmp (p
, "2K") == 0)
6281 if (strcmp (p
, "3000") == 0
6282 || strcmp (p
, "3k") == 0
6283 || strcmp (p
, "3K") == 0)
6288 if (strcmp (p
, "4000") == 0
6289 || strcmp (p
, "4k") == 0
6290 || strcmp (p
, "4K") == 0)
6292 else if (strcmp (p
, "4100") == 0)
6298 else if (strcmp (p
, "4300") == 0)
6300 else if (strcmp (p
, "4400") == 0)
6302 else if (strcmp (p
, "4600") == 0)
6304 else if (strcmp (p
, "4650") == 0)
6310 else if (strcmp (p
, "4010") == 0)
6319 if (strcmp (p
, "5000") == 0
6320 || strcmp (p
, "5k") == 0
6321 || strcmp (p
, "5K") == 0)
6326 if (strcmp (p
, "6000") == 0
6327 || strcmp (p
, "6k") == 0
6328 || strcmp (p
, "6K") == 0)
6333 if (strcmp (p
, "8000") == 0
6334 || strcmp (p
, "8k") == 0
6335 || strcmp (p
, "8K") == 0)
6340 if (strcmp (p
, "orion") == 0)
6345 if (sv
&& mips_cpu
!= 4300 && mips_cpu
!= 4100 && mips_cpu
!= 5000)
6347 as_bad ("ignoring invalid leading 'v' in -mcpu=%s switch", arg
);
6353 as_bad ("invalid architecture -mcpu=%s", arg
);
6364 case OPTION_NO_M4650
:
6372 case OPTION_NO_M4010
:
6380 case OPTION_NO_M4100
:
6384 case OPTION_MEMBEDDED_PIC
:
6385 mips_pic
= EMBEDDED_PIC
;
6386 if (USE_GLOBAL_POINTER_OPT
&& g_switch_seen
)
6388 as_bad ("-G may not be used with embedded PIC code");
6391 g_switch_value
= 0x7fffffff;
6394 /* When generating ELF code, we permit -KPIC and -call_shared to
6395 select SVR4_PIC, and -non_shared to select no PIC. This is
6396 intended to be compatible with Irix 5. */
6397 case OPTION_CALL_SHARED
:
6398 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
6400 as_bad ("-call_shared is supported only for ELF format");
6403 mips_pic
= SVR4_PIC
;
6404 if (g_switch_seen
&& g_switch_value
!= 0)
6406 as_bad ("-G may not be used with SVR4 PIC code");
6412 case OPTION_NON_SHARED
:
6413 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
6415 as_bad ("-non_shared is supported only for ELF format");
6421 /* The -xgot option tells the assembler to use 32 offsets when
6422 accessing the got in SVR4_PIC mode. It is for Irix
6429 if (! USE_GLOBAL_POINTER_OPT
)
6431 as_bad ("-G is not supported for this configuration");
6434 else if (mips_pic
== SVR4_PIC
|| mips_pic
== EMBEDDED_PIC
)
6436 as_bad ("-G may not be used with SVR4 or embedded PIC code");
6440 g_switch_value
= atoi (arg
);
6444 /* The -32 and -64 options tell the assembler to output the 32
6445 bit or the 64 bit MIPS ELF format. */
6452 const char **list
, **l
;
6454 list
= bfd_target_list ();
6455 for (l
= list
; *l
!= NULL
; l
++)
6456 if (strcmp (*l
, "elf64-bigmips") == 0
6457 || strcmp (*l
, "elf64-littlemips") == 0)
6460 as_fatal ("No compiled in support for 64 bit object file format");
6474 md_show_usage (stream
)
6479 -membedded-pic generate embedded position independent code\n\
6480 -EB generate big endian output\n\
6481 -EL generate little endian output\n\
6482 -g, -g2 do not remove uneeded NOPs or swap branches\n\
6483 -G NUM allow referencing objects up to NUM bytes\n\
6484 implicitly with the gp register [default 8]\n");
6486 -mips1, -mcpu=r{2,3}000 generate code for r2000 and r3000\n\
6487 -mips2, -mcpu=r6000 generate code for r6000\n\
6488 -mips3, -mcpu=r4000 generate code for r4000\n\
6489 -mips4, -mcpu=r8000 generate code for r8000\n\
6490 -mcpu=vr4300 generate code for vr4300\n\
6491 -mcpu=vr4100 generate code for vr4100\n\
6492 -m4650 permit R4650 instructions\n\
6493 -no-m4650 do not permit R4650 instructions\n\
6494 -m4010 permit R4010 instructions\n\
6495 -no-m4010 do not permit R4010 instructions\n\
6496 -m4100 permit VR4100 instructions\n\
6497 -no-m4100 do not permit VR4100 instructions\n");
6499 -O0 remove unneeded NOPs, do not swap branches\n\
6500 -O remove unneeded NOPs and swap branches\n\
6501 --trap, --no-break trap exception on div by 0 and mult overflow\n\
6502 --break, --no-trap break exception on div by 0 and mult overflow\n");
6505 -KPIC, -call_shared generate SVR4 position independent code\n\
6506 -non_shared do not generate position independent code\n\
6507 -xgot assume a 32 bit GOT\n\
6508 -32 create 32 bit object file (default)\n\
6509 -64 create 64 bit object file\n");
6514 mips_init_after_args ()
6516 if (target_big_endian
)
6517 byte_order
= BIG_ENDIAN
;
6519 byte_order
= LITTLE_ENDIAN
;
6523 md_pcrel_from (fixP
)
6526 if (OUTPUT_FLAVOR
!= bfd_target_aout_flavour
6527 && fixP
->fx_addsy
!= (symbolS
*) NULL
6528 && ! S_IS_DEFINED (fixP
->fx_addsy
))
6530 /* This makes a branch to an undefined symbol be a branch to the
6531 current location. */
6535 /* return the address of the delay slot */
6536 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
6539 /* This is called by emit_expr via TC_CONS_FIX_NEW when creating a
6540 reloc for a cons. We could use the definition there, except that
6541 we want to handle 64 bit relocs specially. */
6544 cons_fix_new_mips (frag
, where
, nbytes
, exp
)
6547 unsigned int nbytes
;
6550 /* If we are assembling in 32 bit mode, turn an 8 byte reloc into a
6552 if (nbytes
== 8 && ! mips_64
)
6554 if (byte_order
== BIG_ENDIAN
)
6559 if (nbytes
!= 2 && nbytes
!= 4 && nbytes
!= 8)
6560 as_bad ("Unsupported reloc size %d", nbytes
);
6562 fix_new_exp (frag_now
, where
, (int) nbytes
, exp
, 0,
6565 : (nbytes
== 4 ? BFD_RELOC_32
: BFD_RELOC_64
)));
6568 /* Sort any unmatched HI16_S relocs so that they immediately precede
6569 the corresponding LO reloc. This is called before md_apply_fix and
6570 tc_gen_reloc. Unmatched HI16_S relocs can only be generated by
6571 explicit use of the %hi modifier. */
6576 struct mips_hi_fixup
*l
;
6578 for (l
= mips_hi_fixup_list
; l
!= NULL
; l
= l
->next
)
6580 segment_info_type
*seginfo
;
6583 assert (l
->fixp
->fx_r_type
== BFD_RELOC_HI16_S
);
6585 /* Check quickly whether the next fixup happens to be a matching
6587 if (l
->fixp
->fx_next
!= NULL
6588 && l
->fixp
->fx_next
->fx_r_type
== BFD_RELOC_LO16
6589 && l
->fixp
->fx_addsy
== l
->fixp
->fx_next
->fx_addsy
6590 && l
->fixp
->fx_offset
== l
->fixp
->fx_next
->fx_offset
)
6593 /* Look through the fixups for this segment for a matching %lo.
6594 When we find one, move the %hi just in front of it. We do
6595 this in two passes. In the first pass, we try to find a
6596 unique %lo. In the second pass, we permit multiple %hi
6597 relocs for a single %lo (this is a GNU extension). */
6598 seginfo
= seg_info (l
->seg
);
6599 for (pass
= 0; pass
< 2; pass
++)
6604 for (f
= seginfo
->fix_root
; f
!= NULL
; f
= f
->fx_next
)
6606 /* Check whether this is a %lo fixup which matches l->fixp. */
6607 if (f
->fx_r_type
== BFD_RELOC_LO16
6608 && f
->fx_addsy
== l
->fixp
->fx_addsy
6609 && f
->fx_offset
== l
->fixp
->fx_offset
6612 || prev
->fx_r_type
!= BFD_RELOC_HI16_S
6613 || prev
->fx_addsy
!= f
->fx_addsy
6614 || prev
->fx_offset
!= f
->fx_offset
))
6618 /* Move l->fixp before f. */
6619 for (pf
= &seginfo
->fix_root
;
6621 pf
= &(*pf
)->fx_next
)
6622 assert (*pf
!= NULL
);
6624 *pf
= l
->fixp
->fx_next
;
6626 l
->fixp
->fx_next
= f
;
6628 seginfo
->fix_root
= l
->fixp
;
6630 prev
->fx_next
= l
->fixp
;
6642 as_warn_where (l
->fixp
->fx_file
, l
->fixp
->fx_line
,
6643 "Unmatched %%hi reloc");
6648 /* When generating embedded PIC code we need to use a special
6649 relocation to represent the difference of two symbols in the .text
6650 section (switch tables use a difference of this sort). See
6651 include/coff/mips.h for details. This macro checks whether this
6652 fixup requires the special reloc. */
6653 #define SWITCH_TABLE(fixp) \
6654 ((fixp)->fx_r_type == BFD_RELOC_32 \
6655 && (fixp)->fx_addsy != NULL \
6656 && (fixp)->fx_subsy != NULL \
6657 && S_GET_SEGMENT ((fixp)->fx_addsy) == text_section \
6658 && S_GET_SEGMENT ((fixp)->fx_subsy) == text_section)
6660 /* When generating embedded PIC code we must keep all PC relative
6661 relocations, in case the linker has to relax a call. We also need
6662 to keep relocations for switch table entries. */
6666 mips_force_relocation (fixp
)
6669 return (mips_pic
== EMBEDDED_PIC
6671 || SWITCH_TABLE (fixp
)
6672 || fixp
->fx_r_type
== BFD_RELOC_PCREL_HI16_S
6673 || fixp
->fx_r_type
== BFD_RELOC_PCREL_LO16
));
6676 /* Apply a fixup to the object file. */
6679 md_apply_fix (fixP
, valueP
)
6686 assert (fixP
->fx_size
== 4 || fixP
->fx_r_type
== BFD_RELOC_16
);
6689 fixP
->fx_addnumber
= value
; /* Remember value for tc_gen_reloc */
6691 if (fixP
->fx_addsy
== NULL
&& ! fixP
->fx_pcrel
)
6694 switch (fixP
->fx_r_type
)
6696 case BFD_RELOC_MIPS_JMP
:
6697 case BFD_RELOC_HI16
:
6698 case BFD_RELOC_HI16_S
:
6699 case BFD_RELOC_MIPS_GPREL
:
6700 case BFD_RELOC_MIPS_LITERAL
:
6701 case BFD_RELOC_MIPS_CALL16
:
6702 case BFD_RELOC_MIPS_GOT16
:
6703 case BFD_RELOC_MIPS_GPREL32
:
6704 case BFD_RELOC_MIPS_GOT_HI16
:
6705 case BFD_RELOC_MIPS_GOT_LO16
:
6706 case BFD_RELOC_MIPS_CALL_HI16
:
6707 case BFD_RELOC_MIPS_CALL_LO16
:
6709 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
6710 "Invalid PC relative reloc");
6711 /* Nothing needed to do. The value comes from the reloc entry */
6714 case BFD_RELOC_PCREL_HI16_S
:
6715 /* The addend for this is tricky if it is internal, so we just
6716 do everything here rather than in bfd_perform_relocation. */
6717 if ((fixP
->fx_addsy
->bsym
->flags
& BSF_SECTION_SYM
) == 0)
6719 /* For an external symbol adjust by the address to make it
6720 pcrel_offset. We use the address of the RELLO reloc
6721 which follows this one. */
6722 value
+= (fixP
->fx_next
->fx_frag
->fr_address
6723 + fixP
->fx_next
->fx_where
);
6728 buf
= (unsigned char *) fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
6729 if (byte_order
== BIG_ENDIAN
)
6731 md_number_to_chars (buf
, value
, 2);
6734 case BFD_RELOC_PCREL_LO16
:
6735 /* The addend for this is tricky if it is internal, so we just
6736 do everything here rather than in bfd_perform_relocation. */
6737 if ((fixP
->fx_addsy
->bsym
->flags
& BSF_SECTION_SYM
) == 0)
6738 value
+= fixP
->fx_frag
->fr_address
+ fixP
->fx_where
;
6739 buf
= (unsigned char *) fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
6740 if (byte_order
== BIG_ENDIAN
)
6742 md_number_to_chars (buf
, value
, 2);
6746 /* If we are deleting this reloc entry, we must fill in the
6747 value now. This can happen if we have a .word which is not
6748 resolved when it appears but is later defined. We also need
6749 to fill in the value if this is an embedded PIC switch table
6752 || (mips_pic
== EMBEDDED_PIC
&& SWITCH_TABLE (fixP
)))
6753 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
,
6758 /* If we are deleting this reloc entry, we must fill in the
6760 assert (fixP
->fx_size
== 2);
6762 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
,
6766 case BFD_RELOC_LO16
:
6767 /* When handling an embedded PIC switch statement, we can wind
6768 up deleting a LO16 reloc. See the 'o' case in mips_ip. */
6771 if (value
< -0x8000 || value
> 0x7fff)
6772 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
6773 "relocation overflow");
6774 buf
= (unsigned char *) fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
6775 if (byte_order
== BIG_ENDIAN
)
6777 md_number_to_chars (buf
, value
, 2);
6781 case BFD_RELOC_16_PCREL_S2
:
6783 * We need to save the bits in the instruction since fixup_segment()
6784 * might be deleting the relocation entry (i.e., a branch within
6785 * the current segment).
6788 as_warn_where (fixP
->fx_file
, fixP
->fx_line
,
6789 "Branch to odd address (%lx)", value
);
6792 /* update old instruction data */
6793 buf
= (unsigned char *) (fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
);
6797 insn
= (buf
[3] << 24) | (buf
[2] << 16) | (buf
[1] << 8) | buf
[0];
6801 insn
= (buf
[0] << 24) | (buf
[1] << 16) | (buf
[2] << 8) | buf
[3];
6809 if (value
>= -0x8000 && value
< 0x8000)
6810 insn
|= value
& 0xffff;
6813 /* The branch offset is too large. If this is an
6814 unconditional branch, and we are not generating PIC code,
6815 we can convert it to an absolute jump instruction. */
6816 if (mips_pic
== NO_PIC
6818 && fixP
->fx_frag
->fr_address
>= text_section
->vma
6819 && (fixP
->fx_frag
->fr_address
6820 < text_section
->vma
+ text_section
->_raw_size
)
6821 && ((insn
& 0xffff0000) == 0x10000000 /* beq $0,$0 */
6822 || (insn
& 0xffff0000) == 0x04010000 /* bgez $0 */
6823 || (insn
& 0xffff0000) == 0x04110000)) /* bgezal $0 */
6825 if ((insn
& 0xffff0000) == 0x04110000) /* bgezal $0 */
6826 insn
= 0x0c000000; /* jal */
6828 insn
= 0x08000000; /* j */
6829 fixP
->fx_r_type
= BFD_RELOC_MIPS_JMP
;
6831 fixP
->fx_addsy
= section_symbol (text_section
);
6832 fixP
->fx_addnumber
= (value
<< 2) + md_pcrel_from (fixP
);
6836 /* FIXME. It would be possible in principle to handle
6837 conditional branches which overflow. They could be
6838 transformed into a branch around a jump. This would
6839 require setting up variant frags for each different
6840 branch type. The native MIPS assembler attempts to
6841 handle these cases, but it appears to do it
6843 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
6844 "Relocation overflow");
6848 md_number_to_chars ((char *) buf
, (valueT
) insn
, 4);
6863 const struct mips_opcode
*p
;
6864 int treg
, sreg
, dreg
, shamt
;
6869 for (i
= 0; i
< NUMOPCODES
; ++i
)
6871 p
= &mips_opcodes
[i
];
6872 if (((oc
& p
->mask
) == p
->match
) && (p
->pinfo
!= INSN_MACRO
))
6874 printf ("%08lx %s\t", oc
, p
->name
);
6875 treg
= (oc
>> 16) & 0x1f;
6876 sreg
= (oc
>> 21) & 0x1f;
6877 dreg
= (oc
>> 11) & 0x1f;
6878 shamt
= (oc
>> 6) & 0x1f;
6880 for (args
= p
->args
;; ++args
)
6891 printf ("%c", *args
);
6895 assert (treg
== sreg
);
6896 printf ("$%d,$%d", treg
, sreg
);
6901 printf ("$%d", dreg
);
6906 printf ("$%d", treg
);
6910 printf ("0x%x", treg
);
6915 printf ("$%d", sreg
);
6919 printf ("0x%08lx", oc
& 0x1ffffff);
6931 printf ("$%d", shamt
);
6942 printf ("%08lx UNDEFINED\n", oc
);
6953 name
= input_line_pointer
;
6954 c
= get_symbol_end ();
6955 p
= (symbolS
*) symbol_find_or_make (name
);
6956 *input_line_pointer
= c
;
6960 /* Align the current frag to a given power of two. The MIPS assembler
6961 also automatically adjusts any preceding label. */
6964 mips_align (to
, fill
, label
)
6969 mips_emit_delays ();
6970 frag_align (to
, fill
);
6971 record_alignment (now_seg
, to
);
6974 assert (S_GET_SEGMENT (label
) == now_seg
);
6975 label
->sy_frag
= frag_now
;
6976 S_SET_VALUE (label
, (valueT
) frag_now_fix ());
6980 /* Align to a given power of two. .align 0 turns off the automatic
6981 alignment used by the data creating pseudo-ops. */
6988 register long temp_fill
;
6989 long max_alignment
= 15;
6993 o Note that the assembler pulls down any immediately preceeding label
6994 to the aligned address.
6995 o It's not documented but auto alignment is reinstated by
6996 a .align pseudo instruction.
6997 o Note also that after auto alignment is turned off the mips assembler
6998 issues an error on attempt to assemble an improperly aligned data item.
7003 temp
= get_absolute_expression ();
7004 if (temp
> max_alignment
)
7005 as_bad ("Alignment too large: %d. assumed.", temp
= max_alignment
);
7008 as_warn ("Alignment negative: 0 assumed.");
7011 if (*input_line_pointer
== ',')
7013 input_line_pointer
++;
7014 temp_fill
= get_absolute_expression ();
7021 mips_align (temp
, (int) temp_fill
, insn_label
);
7028 demand_empty_rest_of_line ();
7032 mips_flush_pending_output ()
7034 mips_emit_delays ();
7044 /* When generating embedded PIC code, we only use the .text, .lit8,
7045 .sdata and .sbss sections. We change the .data and .rdata
7046 pseudo-ops to use .sdata. */
7047 if (mips_pic
== EMBEDDED_PIC
7048 && (sec
== 'd' || sec
== 'r'))
7051 mips_emit_delays ();
7061 subseg_set (bss_section
, (subsegT
) get_absolute_expression ());
7062 demand_empty_rest_of_line ();
7066 if (USE_GLOBAL_POINTER_OPT
)
7068 seg
= subseg_new (RDATA_SECTION_NAME
,
7069 (subsegT
) get_absolute_expression ());
7070 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
7072 bfd_set_section_flags (stdoutput
, seg
,
7078 bfd_set_section_alignment (stdoutput
, seg
, 4);
7080 demand_empty_rest_of_line ();
7084 as_bad ("No read only data section in this object file format");
7085 demand_empty_rest_of_line ();
7091 if (USE_GLOBAL_POINTER_OPT
)
7093 seg
= subseg_new (".sdata", (subsegT
) get_absolute_expression ());
7094 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
7096 bfd_set_section_flags (stdoutput
, seg
,
7097 SEC_ALLOC
| SEC_LOAD
| SEC_RELOC
7099 bfd_set_section_alignment (stdoutput
, seg
, 4);
7101 demand_empty_rest_of_line ();
7106 as_bad ("Global pointers not supported; recompile -G 0");
7107 demand_empty_rest_of_line ();
7116 mips_enable_auto_align ()
7128 mips_emit_delays ();
7129 if (log_size
> 0 && auto_align
)
7130 mips_align (log_size
, 0, label
);
7132 cons (1 << log_size
);
7143 mips_emit_delays ();
7147 mips_align (3, 0, label
);
7149 mips_align (2, 0, label
);
7156 /* Handle .globl. We need to override it because on Irix 5 you are
7159 where foo is an undefined symbol, to mean that foo should be
7160 considered to be the address of a function. */
7171 name
= input_line_pointer
;
7172 c
= get_symbol_end ();
7173 symbolP
= symbol_find_or_make (name
);
7174 *input_line_pointer
= c
;
7177 /* On Irix 5, every global symbol that is not explicitly labelled as
7178 being a function is apparently labelled as being an object. */
7181 if (! is_end_of_line
[(unsigned char) *input_line_pointer
])
7186 secname
= input_line_pointer
;
7187 c
= get_symbol_end ();
7188 sec
= bfd_get_section_by_name (stdoutput
, secname
);
7190 as_bad ("%s: no such section", secname
);
7191 *input_line_pointer
= c
;
7193 if (sec
!= NULL
&& (sec
->flags
& SEC_CODE
) != 0)
7194 flag
= BSF_FUNCTION
;
7197 symbolP
->bsym
->flags
|= flag
;
7199 S_SET_EXTERNAL (symbolP
);
7200 demand_empty_rest_of_line ();
7210 opt
= input_line_pointer
;
7211 c
= get_symbol_end ();
7215 /* FIXME: What does this mean? */
7217 else if (strncmp (opt
, "pic", 3) == 0)
7225 mips_pic
= SVR4_PIC
;
7227 as_bad (".option pic%d not supported", i
);
7229 if (USE_GLOBAL_POINTER_OPT
&& mips_pic
== SVR4_PIC
)
7231 if (g_switch_seen
&& g_switch_value
!= 0)
7232 as_warn ("-G may not be used with SVR4 PIC code");
7234 bfd_set_gp_size (stdoutput
, 0);
7238 as_warn ("Unrecognized option \"%s\"", opt
);
7240 *input_line_pointer
= c
;
7241 demand_empty_rest_of_line ();
7248 char *name
= input_line_pointer
, ch
;
7250 while (!is_end_of_line
[(unsigned char) *input_line_pointer
])
7251 input_line_pointer
++;
7252 ch
= *input_line_pointer
;
7253 *input_line_pointer
= '\0';
7255 if (strcmp (name
, "reorder") == 0)
7259 prev_insn_unreordered
= 1;
7260 prev_prev_insn_unreordered
= 1;
7264 else if (strcmp (name
, "noreorder") == 0)
7266 mips_emit_delays ();
7268 mips_any_noreorder
= 1;
7270 else if (strcmp (name
, "at") == 0)
7274 else if (strcmp (name
, "noat") == 0)
7278 else if (strcmp (name
, "macro") == 0)
7280 mips_warn_about_macros
= 0;
7282 else if (strcmp (name
, "nomacro") == 0)
7284 if (mips_noreorder
== 0)
7285 as_bad ("`noreorder' must be set before `nomacro'");
7286 mips_warn_about_macros
= 1;
7288 else if (strcmp (name
, "move") == 0 || strcmp (name
, "novolatile") == 0)
7292 else if (strcmp (name
, "nomove") == 0 || strcmp (name
, "volatile") == 0)
7296 else if (strcmp (name
, "bopt") == 0)
7300 else if (strcmp (name
, "nobopt") == 0)
7304 else if (strncmp (name
, "mips", 4) == 0)
7308 /* Permit the user to change the ISA on the fly. Needless to
7309 say, misuse can cause serious problems. */
7310 isa
= atoi (name
+ 4);
7312 mips_isa
= file_mips_isa
;
7313 else if (isa
< 1 || isa
> 4)
7314 as_bad ("unknown ISA level");
7320 as_warn ("Tried to set unrecognized symbol: %s\n", name
);
7322 *input_line_pointer
= ch
;
7323 demand_empty_rest_of_line ();
7326 /* Handle the .abicalls pseudo-op. I believe this is equivalent to
7327 .option pic2. It means to generate SVR4 PIC calls. */
7333 mips_pic
= SVR4_PIC
;
7334 if (USE_GLOBAL_POINTER_OPT
)
7336 if (g_switch_seen
&& g_switch_value
!= 0)
7337 as_warn ("-G may not be used with SVR4 PIC code");
7340 bfd_set_gp_size (stdoutput
, 0);
7341 demand_empty_rest_of_line ();
7344 /* Handle the .cpload pseudo-op. This is used when generating SVR4
7345 PIC code. It sets the $gp register for the function based on the
7346 function address, which is in the register named in the argument.
7347 This uses a relocation against _gp_disp, which is handled specially
7348 by the linker. The result is:
7349 lui $gp,%hi(_gp_disp)
7350 addiu $gp,$gp,%lo(_gp_disp)
7351 addu $gp,$gp,.cpload argument
7352 The .cpload argument is normally $25 == $t9. */
7361 /* If we are not generating SVR4 PIC code, .cpload is ignored. */
7362 if (mips_pic
!= SVR4_PIC
)
7368 /* .cpload should be a in .set noreorder section. */
7369 if (mips_noreorder
== 0)
7370 as_warn (".cpload not in noreorder section");
7373 ex
.X_add_symbol
= symbol_find_or_make ("_gp_disp");
7374 ex
.X_op_symbol
= NULL
;
7375 ex
.X_add_number
= 0;
7377 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
7378 ex
.X_add_symbol
->bsym
->flags
|= BSF_OBJECT
;
7380 macro_build_lui ((char *) NULL
, &icnt
, &ex
, GP
);
7381 macro_build ((char *) NULL
, &icnt
, &ex
, "addiu", "t,r,j", GP
, GP
,
7382 (int) BFD_RELOC_LO16
);
7384 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "addu", "d,v,t",
7385 GP
, GP
, tc_get_register (0));
7387 demand_empty_rest_of_line ();
7390 /* Handle the .cprestore pseudo-op. This stores $gp into a given
7391 offset from $sp. The offset is remembered, and after making a PIC
7392 call $gp is restored from that location. */
7395 s_cprestore (ignore
)
7401 /* If we are not generating SVR4 PIC code, .cprestore is ignored. */
7402 if (mips_pic
!= SVR4_PIC
)
7408 mips_cprestore_offset
= get_absolute_expression ();
7410 ex
.X_op
= O_constant
;
7411 ex
.X_add_symbol
= NULL
;
7412 ex
.X_op_symbol
= NULL
;
7413 ex
.X_add_number
= mips_cprestore_offset
;
7415 macro_build ((char *) NULL
, &icnt
, &ex
,
7416 mips_isa
< 3 ? "sw" : "sd",
7417 "t,o(b)", GP
, (int) BFD_RELOC_LO16
, SP
);
7419 demand_empty_rest_of_line ();
7422 /* Handle the .gpword pseudo-op. This is used when generating PIC
7423 code. It generates a 32 bit GP relative reloc. */
7433 /* When not generating PIC code, this is treated as .word. */
7434 if (mips_pic
!= SVR4_PIC
)
7441 mips_emit_delays ();
7443 mips_align (2, 0, label
);
7448 if (ex
.X_op
!= O_symbol
|| ex
.X_add_number
!= 0)
7450 as_bad ("Unsupported use of .gpword");
7451 ignore_rest_of_line ();
7455 md_number_to_chars (p
, (valueT
) 0, 4);
7456 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 4, &ex
, 0,
7457 BFD_RELOC_MIPS_GPREL32
);
7459 demand_empty_rest_of_line ();
7462 /* Handle the .cpadd pseudo-op. This is used when dealing with switch
7463 tables in SVR4 PIC code. */
7472 /* This is ignored when not generating SVR4 PIC code. */
7473 if (mips_pic
!= SVR4_PIC
)
7479 /* Add $gp to the register named as an argument. */
7480 reg
= tc_get_register (0);
7481 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
7482 mips_isa
< 3 ? "addu" : "daddu",
7483 "d,v,t", reg
, reg
, GP
);
7485 demand_empty_rest_of_line ();
7488 /* Parse a register string into a number. Called from the ECOFF code
7489 to parse .frame. The argument is non-zero if this is the frame
7490 register, so that we can record it in mips_frame_reg. */
7493 tc_get_register (frame
)
7499 if (*input_line_pointer
++ != '$')
7501 as_warn ("expected `$'");
7504 else if (isdigit ((unsigned char) *input_line_pointer
))
7506 reg
= get_absolute_expression ();
7507 if (reg
< 0 || reg
>= 32)
7509 as_warn ("Bad register number");
7515 if (strncmp (input_line_pointer
, "fp", 2) == 0)
7517 else if (strncmp (input_line_pointer
, "sp", 2) == 0)
7519 else if (strncmp (input_line_pointer
, "gp", 2) == 0)
7521 else if (strncmp (input_line_pointer
, "at", 2) == 0)
7525 as_warn ("Unrecognized register name");
7528 input_line_pointer
+= 2;
7531 mips_frame_reg
= reg
!= 0 ? reg
: SP
;
7536 md_section_align (seg
, addr
)
7540 int align
= bfd_get_section_alignment (stdoutput
, seg
);
7543 /* We don't need to align ELF sections to the full alignment.
7544 However, Irix 5 may prefer that we align them at least to a 16
7550 return ((addr
+ (1 << align
) - 1) & (-1 << align
));
7553 /* Utility routine, called from above as well. If called while the
7554 input file is still being read, it's only an approximation. (For
7555 example, a symbol may later become defined which appeared to be
7556 undefined earlier.) */
7559 nopic_need_relax (sym
)
7565 if (USE_GLOBAL_POINTER_OPT
)
7567 const char *symname
;
7570 /* Find out whether this symbol can be referenced off the GP
7571 register. It can be if it is smaller than the -G size or if
7572 it is in the .sdata or .sbss section. Certain symbols can
7573 not be referenced off the GP, although it appears as though
7575 symname
= S_GET_NAME (sym
);
7576 if (symname
!= (const char *) NULL
7577 && (strcmp (symname
, "eprol") == 0
7578 || strcmp (symname
, "etext") == 0
7579 || strcmp (symname
, "_gp") == 0
7580 || strcmp (symname
, "edata") == 0
7581 || strcmp (symname
, "_fbss") == 0
7582 || strcmp (symname
, "_fdata") == 0
7583 || strcmp (symname
, "_ftext") == 0
7584 || strcmp (symname
, "end") == 0
7585 || strcmp (symname
, "_gp_disp") == 0))
7587 else if (! S_IS_DEFINED (sym
)
7589 #ifndef NO_ECOFF_DEBUGGING
7590 || (sym
->ecoff_extern_size
!= 0
7591 && sym
->ecoff_extern_size
<= g_switch_value
)
7593 || (S_GET_VALUE (sym
) != 0
7594 && S_GET_VALUE (sym
) <= g_switch_value
)))
7598 const char *segname
;
7600 segname
= segment_name (S_GET_SEGMENT (sym
));
7601 assert (strcmp (segname
, ".lit8") != 0
7602 && strcmp (segname
, ".lit4") != 0);
7603 change
= (strcmp (segname
, ".sdata") != 0
7604 && strcmp (segname
, ".sbss") != 0);
7609 /* We are not optimizing for the GP register. */
7613 /* Estimate the size of a frag before relaxing. We are not really
7614 relaxing here, and the final size is encoded in the subtype
7619 md_estimate_size_before_relax (fragp
, segtype
)
7625 if (mips_pic
== NO_PIC
)
7627 change
= nopic_need_relax (fragp
->fr_symbol
);
7629 else if (mips_pic
== SVR4_PIC
)
7631 asection
*symsec
= fragp
->fr_symbol
->bsym
->section
;
7633 /* This must duplicate the test in adjust_reloc_syms. */
7634 change
= (symsec
!= &bfd_und_section
7635 && symsec
!= &bfd_abs_section
7636 && ! bfd_is_com_section (symsec
));
7643 /* Record the offset to the first reloc in the fr_opcode field.
7644 This lets md_convert_frag and tc_gen_reloc know that the code
7645 must be expanded. */
7646 fragp
->fr_opcode
= (fragp
->fr_literal
7648 - RELAX_OLD (fragp
->fr_subtype
)
7649 + RELAX_RELOC1 (fragp
->fr_subtype
));
7650 /* FIXME: This really needs as_warn_where. */
7651 if (RELAX_WARN (fragp
->fr_subtype
))
7652 as_warn ("AT used after \".set noat\" or macro used after \".set nomacro\"");
7658 return RELAX_NEW (fragp
->fr_subtype
) - RELAX_OLD (fragp
->fr_subtype
);
7661 /* Translate internal representation of relocation info to BFD target
7665 tc_gen_reloc (section
, fixp
)
7669 static arelent
*retval
[4];
7671 bfd_reloc_code_real_type code
;
7673 reloc
= retval
[0] = (arelent
*) xmalloc (sizeof (arelent
));
7676 reloc
->sym_ptr_ptr
= &fixp
->fx_addsy
->bsym
;
7677 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
7679 if (mips_pic
== EMBEDDED_PIC
7680 && SWITCH_TABLE (fixp
))
7682 /* For a switch table entry we use a special reloc. The addend
7683 is actually the difference between the reloc address and the
7685 reloc
->addend
= reloc
->address
- S_GET_VALUE (fixp
->fx_subsy
);
7686 if (OUTPUT_FLAVOR
!= bfd_target_ecoff_flavour
)
7687 as_fatal ("Double check fx_r_type in tc-mips.c:tc_gen_reloc");
7688 fixp
->fx_r_type
= BFD_RELOC_GPREL32
;
7690 else if (fixp
->fx_r_type
== BFD_RELOC_PCREL_LO16
)
7692 /* We use a special addend for an internal RELLO reloc. */
7693 if (fixp
->fx_addsy
->bsym
->flags
& BSF_SECTION_SYM
)
7694 reloc
->addend
= reloc
->address
- S_GET_VALUE (fixp
->fx_subsy
);
7696 reloc
->addend
= fixp
->fx_addnumber
+ reloc
->address
;
7698 else if (fixp
->fx_r_type
== BFD_RELOC_PCREL_HI16_S
)
7700 assert (fixp
->fx_next
!= NULL
7701 && fixp
->fx_next
->fx_r_type
== BFD_RELOC_PCREL_LO16
);
7702 /* We use a special addend for an internal RELHI reloc. The
7703 reloc is relative to the RELLO; adjust the addend
7705 if (fixp
->fx_addsy
->bsym
->flags
& BSF_SECTION_SYM
)
7706 reloc
->addend
= (fixp
->fx_next
->fx_frag
->fr_address
7707 + fixp
->fx_next
->fx_where
7708 - S_GET_VALUE (fixp
->fx_subsy
));
7710 reloc
->addend
= (fixp
->fx_addnumber
7711 + fixp
->fx_next
->fx_frag
->fr_address
7712 + fixp
->fx_next
->fx_where
);
7714 else if (fixp
->fx_pcrel
== 0)
7715 reloc
->addend
= fixp
->fx_addnumber
;
7718 if (OUTPUT_FLAVOR
!= bfd_target_aout_flavour
)
7719 /* A gruesome hack which is a result of the gruesome gas reloc
7721 reloc
->addend
= reloc
->address
;
7723 reloc
->addend
= -reloc
->address
;
7726 /* If this is a variant frag, we may need to adjust the existing
7727 reloc and generate a new one. */
7728 if (fixp
->fx_frag
->fr_opcode
!= NULL
7729 && (fixp
->fx_r_type
== BFD_RELOC_MIPS_GPREL
7730 || fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT16
7731 || fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL16
7732 || fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT_HI16
7733 || fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT_LO16
7734 || fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL_HI16
7735 || fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL_LO16
))
7739 /* If this is not the last reloc in this frag, then we have two
7740 GPREL relocs, or a GOT_HI16/GOT_LO16 pair, or a
7741 CALL_HI16/CALL_LO16, both of which are being replaced. Let
7742 the second one handle all of them. */
7743 if (fixp
->fx_next
!= NULL
7744 && fixp
->fx_frag
== fixp
->fx_next
->fx_frag
)
7746 assert ((fixp
->fx_r_type
== BFD_RELOC_MIPS_GPREL
7747 && fixp
->fx_next
->fx_r_type
== BFD_RELOC_MIPS_GPREL
)
7748 || (fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT_HI16
7749 && (fixp
->fx_next
->fx_r_type
7750 == BFD_RELOC_MIPS_GOT_LO16
))
7751 || (fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL_HI16
7752 && (fixp
->fx_next
->fx_r_type
7753 == BFD_RELOC_MIPS_CALL_LO16
)));
7758 fixp
->fx_where
= fixp
->fx_frag
->fr_opcode
- fixp
->fx_frag
->fr_literal
;
7759 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
7760 reloc2
= retval
[1] = (arelent
*) xmalloc (sizeof (arelent
));
7762 reloc2
->sym_ptr_ptr
= &fixp
->fx_addsy
->bsym
;
7763 reloc2
->address
= (reloc
->address
7764 + (RELAX_RELOC2 (fixp
->fx_frag
->fr_subtype
)
7765 - RELAX_RELOC1 (fixp
->fx_frag
->fr_subtype
)));
7766 reloc2
->addend
= fixp
->fx_addnumber
;
7767 reloc2
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_LO16
);
7768 assert (reloc2
->howto
!= NULL
);
7770 if (RELAX_RELOC3 (fixp
->fx_frag
->fr_subtype
))
7774 reloc3
= retval
[2] = (arelent
*) xmalloc (sizeof (arelent
));
7777 reloc3
->address
+= 4;
7780 if (mips_pic
== NO_PIC
)
7782 assert (fixp
->fx_r_type
== BFD_RELOC_MIPS_GPREL
);
7783 fixp
->fx_r_type
= BFD_RELOC_HI16_S
;
7785 else if (mips_pic
== SVR4_PIC
)
7787 switch (fixp
->fx_r_type
)
7791 case BFD_RELOC_MIPS_GOT16
:
7793 case BFD_RELOC_MIPS_CALL16
:
7794 case BFD_RELOC_MIPS_GOT_LO16
:
7795 case BFD_RELOC_MIPS_CALL_LO16
:
7796 fixp
->fx_r_type
= BFD_RELOC_MIPS_GOT16
;
7804 /* Since DIFF_EXPR_OK is defined in tc-mips.h, it is possible that
7805 fixup_segment converted a non-PC relative reloc into a PC
7806 relative reloc. In such a case, we need to convert the reloc
7808 code
= fixp
->fx_r_type
;
7814 code
= BFD_RELOC_8_PCREL
;
7817 code
= BFD_RELOC_16_PCREL
;
7820 code
= BFD_RELOC_32_PCREL
;
7822 case BFD_RELOC_8_PCREL
:
7823 case BFD_RELOC_16_PCREL
:
7824 case BFD_RELOC_32_PCREL
:
7825 case BFD_RELOC_16_PCREL_S2
:
7826 case BFD_RELOC_PCREL_HI16_S
:
7827 case BFD_RELOC_PCREL_LO16
:
7830 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
7831 "Cannot make %s relocation PC relative",
7832 bfd_get_reloc_code_name (code
));
7836 /* To support a PC relative reloc when generating embedded PIC code
7837 for ECOFF, we use a Cygnus extension. We check for that here to
7838 make sure that we don't let such a reloc escape normally. */
7839 if (OUTPUT_FLAVOR
== bfd_target_ecoff_flavour
7840 && code
== BFD_RELOC_16_PCREL_S2
7841 && mips_pic
!= EMBEDDED_PIC
)
7842 reloc
->howto
= NULL
;
7844 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
7846 if (reloc
->howto
== NULL
)
7848 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
7849 "Can not represent %s relocation in this object file format",
7850 bfd_get_reloc_code_name (code
));
7857 /* Convert a machine dependent frag. */
7860 md_convert_frag (abfd
, asec
, fragp
)
7868 if (fragp
->fr_opcode
== NULL
)
7871 old
= RELAX_OLD (fragp
->fr_subtype
);
7872 new = RELAX_NEW (fragp
->fr_subtype
);
7873 fixptr
= fragp
->fr_literal
+ fragp
->fr_fix
;
7876 memcpy (fixptr
- old
, fixptr
, new);
7878 fragp
->fr_fix
+= new - old
;
7881 /* This function is called whenever a label is defined. It is used
7882 when handling branch delays; if a branch has a label, we assume we
7886 mips_define_label (sym
)
7892 /* Decide whether a label is local. This is called by LOCAL_LABEL.
7893 In order to work with gcc when using mips-tfile, we must keep all
7894 local labels. However, in other cases, we want to discard them,
7895 since they are useless. */
7898 mips_local_label (name
)
7901 #ifndef NO_ECOFF_DEBUGGING
7904 && ! ecoff_debugging_seen
)
7906 /* We were called with -g, but we didn't see any debugging
7907 information. That may mean that gcc is smuggling debugging
7908 information through to mips-tfile, in which case we must
7909 generate all local labels. */
7914 /* Here it's OK to discard local labels. */
7916 return name
[0] == '$';
7919 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7921 /* Some special processing for a MIPS ELF file. */
7924 mips_elf_final_processing ()
7926 /* Write out the register information. */
7931 s
.ri_gprmask
= mips_gprmask
;
7932 s
.ri_cprmask
[0] = mips_cprmask
[0];
7933 s
.ri_cprmask
[1] = mips_cprmask
[1];
7934 s
.ri_cprmask
[2] = mips_cprmask
[2];
7935 s
.ri_cprmask
[3] = mips_cprmask
[3];
7936 /* The gp_value field is set by the MIPS ELF backend. */
7938 bfd_mips_elf32_swap_reginfo_out (stdoutput
, &s
,
7939 ((Elf32_External_RegInfo
*)
7940 mips_regmask_frag
));
7944 Elf64_Internal_RegInfo s
;
7946 s
.ri_gprmask
= mips_gprmask
;
7948 s
.ri_cprmask
[0] = mips_cprmask
[0];
7949 s
.ri_cprmask
[1] = mips_cprmask
[1];
7950 s
.ri_cprmask
[2] = mips_cprmask
[2];
7951 s
.ri_cprmask
[3] = mips_cprmask
[3];
7952 /* The gp_value field is set by the MIPS ELF backend. */
7954 bfd_mips_elf64_swap_reginfo_out (stdoutput
, &s
,
7955 ((Elf64_External_RegInfo
*)
7956 mips_regmask_frag
));
7959 /* Set the MIPS ELF flag bits. FIXME: There should probably be some
7960 sort of BFD interface for this. */
7961 if (mips_any_noreorder
)
7962 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_NOREORDER
;
7963 if (mips_pic
!= NO_PIC
)
7964 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_PIC
;
7967 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */
7969 /* These functions should really be defined by the object file format,
7970 since they are related to debugging information. However, this
7971 code has to work for the a.out format, which does not define them,
7972 so we provide simple versions here. These don't actually generate
7973 any debugging information, but they do simple checking and someday
7974 somebody may make them useful. */
7978 struct loc
*loc_next
;
7979 unsigned long loc_fileno
;
7980 unsigned long loc_lineno
;
7981 unsigned long loc_offset
;
7982 unsigned short loc_delta
;
7983 unsigned short loc_count
;
7992 struct proc
*proc_next
;
7993 struct symbol
*proc_isym
;
7994 struct symbol
*proc_end
;
7995 unsigned long proc_reg_mask
;
7996 unsigned long proc_reg_offset
;
7997 unsigned long proc_fpreg_mask
;
7998 unsigned long proc_fpreg_offset
;
7999 unsigned long proc_frameoffset
;
8000 unsigned long proc_framereg
;
8001 unsigned long proc_pcreg
;
8003 struct file
*proc_file
;
8010 struct file
*file_next
;
8011 unsigned long file_fileno
;
8012 struct symbol
*file_symbol
;
8013 struct symbol
*file_end
;
8014 struct proc
*file_proc
;
8019 static struct obstack proc_frags
;
8020 static procS
*proc_lastP
;
8021 static procS
*proc_rootP
;
8022 static int numprocs
;
8027 obstack_begin (&proc_frags
, 0x2000);
8033 /* check for premature end, nesting errors, etc */
8034 if (proc_lastP
&& proc_lastP
->proc_end
== NULL
)
8035 as_warn ("missing `.end' at end of assembly");
8044 if (*input_line_pointer
== '-')
8046 ++input_line_pointer
;
8049 if (!isdigit (*input_line_pointer
))
8050 as_bad ("Expected simple number.");
8051 if (input_line_pointer
[0] == '0')
8053 if (input_line_pointer
[1] == 'x')
8055 input_line_pointer
+= 2;
8056 while (isxdigit (*input_line_pointer
))
8059 val
|= hex_value (*input_line_pointer
++);
8061 return negative
? -val
: val
;
8065 ++input_line_pointer
;
8066 while (isdigit (*input_line_pointer
))
8069 val
|= *input_line_pointer
++ - '0';
8071 return negative
? -val
: val
;
8074 if (!isdigit (*input_line_pointer
))
8076 printf (" *input_line_pointer == '%c' 0x%02x\n",
8077 *input_line_pointer
, *input_line_pointer
);
8078 as_warn ("Invalid number");
8081 while (isdigit (*input_line_pointer
))
8084 val
+= *input_line_pointer
++ - '0';
8086 return negative
? -val
: val
;
8089 /* The .file directive; just like the usual .file directive, but there
8090 is an initial number which is the ECOFF file index. */
8098 line
= get_number ();
8103 /* The .end directive. */
8111 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
8114 demand_empty_rest_of_line ();
8118 if (now_seg
!= text_section
)
8119 as_warn (".end not in text section");
8122 as_warn (".end and no .ent seen yet.");
8128 assert (S_GET_NAME (p
));
8129 if (strcmp (S_GET_NAME (p
), S_GET_NAME (proc_lastP
->proc_isym
)))
8130 as_warn (".end symbol does not match .ent symbol.");
8133 proc_lastP
->proc_end
= (symbolS
*) 1;
8136 /* The .aent and .ent directives. */
8146 symbolP
= get_symbol ();
8147 if (*input_line_pointer
== ',')
8148 input_line_pointer
++;
8150 if (isdigit (*input_line_pointer
) || *input_line_pointer
== '-')
8151 number
= get_number ();
8152 if (now_seg
!= text_section
)
8153 as_warn (".ent or .aent not in text section.");
8155 if (!aent
&& proc_lastP
&& proc_lastP
->proc_end
== NULL
)
8156 as_warn ("missing `.end'");
8160 procP
= (procS
*) obstack_alloc (&proc_frags
, sizeof (*procP
));
8161 procP
->proc_isym
= symbolP
;
8162 procP
->proc_reg_mask
= 0;
8163 procP
->proc_reg_offset
= 0;
8164 procP
->proc_fpreg_mask
= 0;
8165 procP
->proc_fpreg_offset
= 0;
8166 procP
->proc_frameoffset
= 0;
8167 procP
->proc_framereg
= 0;
8168 procP
->proc_pcreg
= 0;
8169 procP
->proc_end
= NULL
;
8170 procP
->proc_next
= NULL
;
8172 proc_lastP
->proc_next
= procP
;
8178 demand_empty_rest_of_line ();
8181 /* The .frame directive. */
8194 frame_reg
= tc_get_register (1);
8195 if (*input_line_pointer
== ',')
8196 input_line_pointer
++;
8197 frame_off
= get_absolute_expression ();
8198 if (*input_line_pointer
== ',')
8199 input_line_pointer
++;
8200 pcreg
= tc_get_register (0);
8203 assert (proc_rootP
);
8204 proc_rootP
->proc_framereg
= frame_reg
;
8205 proc_rootP
->proc_frameoffset
= frame_off
;
8206 proc_rootP
->proc_pcreg
= pcreg
;
8207 /* bob macho .frame */
8209 /* We don't have to write out a frame stab for unoptimized code. */
8210 if (!(frame_reg
== FP
&& frame_off
== 0))
8213 as_warn ("No .ent for .frame to use.");
8214 (void) sprintf (str
, "R%d;%d", frame_reg
, frame_off
);
8215 symP
= symbol_new (str
, N_VFP
, 0, frag_now
);
8216 S_SET_TYPE (symP
, N_RMASK
);
8217 S_SET_OTHER (symP
, 0);
8218 S_SET_DESC (symP
, 0);
8219 symP
->sy_forward
= proc_lastP
->proc_isym
;
8220 /* bob perhaps I should have used pseudo set */
8222 demand_empty_rest_of_line ();
8226 /* The .fmask and .mask directives. */
8233 char str
[100], *strP
;
8239 mask
= get_number ();
8240 if (*input_line_pointer
== ',')
8241 input_line_pointer
++;
8242 off
= get_absolute_expression ();
8244 /* bob only for coff */
8245 assert (proc_rootP
);
8246 if (reg_type
== 'F')
8248 proc_rootP
->proc_fpreg_mask
= mask
;
8249 proc_rootP
->proc_fpreg_offset
= off
;
8253 proc_rootP
->proc_reg_mask
= mask
;
8254 proc_rootP
->proc_reg_offset
= off
;
8257 /* bob macho .mask + .fmask */
8259 /* We don't have to write out a mask stab if no saved regs. */
8263 as_warn ("No .ent for .mask to use.");
8265 for (i
= 0; i
< 32; i
++)
8269 sprintf (strP
, "%c%d,", reg_type
, i
);
8270 strP
+= strlen (strP
);
8274 sprintf (strP
, ";%d,", off
);
8275 symP
= symbol_new (str
, N_RMASK
, 0, frag_now
);
8276 S_SET_TYPE (symP
, N_RMASK
);
8277 S_SET_OTHER (symP
, 0);
8278 S_SET_DESC (symP
, 0);
8279 symP
->sy_forward
= proc_lastP
->proc_isym
;
8280 /* bob perhaps I should have used pseudo set */
8285 /* The .loc directive. */
8296 assert (now_seg
== text_section
);
8298 lineno
= get_number ();
8299 addroff
= frag_now_fix ();
8301 symbolP
= symbol_new ("", N_SLINE
, addroff
, frag_now
);
8302 S_SET_TYPE (symbolP
, N_SLINE
);
8303 S_SET_OTHER (symbolP
, 0);
8304 S_SET_DESC (symbolP
, lineno
);
8305 symbolP
->sy_segment
= now_seg
;