1 /* tc-mips.c -- assemble code for a MIPS chip.
2 Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001
3 Free Software Foundation, Inc.
4 Contributed by the OSF and Ralph Campbell.
5 Written by Keith Knowles and Ralph Campbell, working independently.
6 Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus
9 This file is part of GAS.
11 GAS is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 2, or (at your option)
16 GAS is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
21 You should have received a copy of the GNU General Public License
22 along with GAS; see the file COPYING. If not, write to the Free
23 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
29 #include "safe-ctype.h"
38 #include "opcode/mips.h"
42 #define DBG(x) printf x
48 /* Clean up namespace so we can include obj-elf.h too. */
49 static int mips_output_flavor
PARAMS ((void));
50 static int mips_output_flavor () { return OUTPUT_FLAVOR
; }
51 #undef OBJ_PROCESS_STAB
58 #undef obj_frob_file_after_relocs
59 #undef obj_frob_symbol
61 #undef obj_sec_sym_ok_for_reloc
62 #undef OBJ_COPY_SYMBOL_ATTRIBUTES
65 /* Fix any of them that we actually care about. */
67 #define OUTPUT_FLAVOR mips_output_flavor()
74 #ifndef ECOFF_DEBUGGING
75 #define NO_ECOFF_DEBUGGING
76 #define ECOFF_DEBUGGING 0
81 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
82 static char *mips_regmask_frag
;
87 #define PIC_CALL_REG 25
95 #define ILLEGAL_REG (32)
97 /* Allow override of standard little-endian ECOFF format. */
99 #ifndef ECOFF_LITTLE_FORMAT
100 #define ECOFF_LITTLE_FORMAT "ecoff-littlemips"
103 extern int target_big_endian
;
105 /* The name of the readonly data section. */
106 #define RDATA_SECTION_NAME (OUTPUT_FLAVOR == bfd_target_aout_flavour \
108 : OUTPUT_FLAVOR == bfd_target_ecoff_flavour \
110 : OUTPUT_FLAVOR == bfd_target_coff_flavour \
112 : OUTPUT_FLAVOR == bfd_target_elf_flavour \
116 /* The ABI to use. */
127 /* MIPS ABI we are using for this output file. */
128 static enum mips_abi_level file_mips_abi
= NO_ABI
;
130 /* This is the set of options which may be modified by the .set
131 pseudo-op. We use a struct so that .set push and .set pop are more
134 struct mips_set_options
136 /* MIPS ISA (Instruction Set Architecture) level. This is set to -1
137 if it has not been initialized. Changed by `.set mipsN', and the
138 -mipsN command line option, and the default CPU. */
140 /* Whether we are assembling for the mips16 processor. 0 if we are
141 not, 1 if we are, and -1 if the value has not been initialized.
142 Changed by `.set mips16' and `.set nomips16', and the -mips16 and
143 -nomips16 command line options, and the default CPU. */
145 /* Non-zero if we should not reorder instructions. Changed by `.set
146 reorder' and `.set noreorder'. */
148 /* Non-zero if we should not permit the $at ($1) register to be used
149 in instructions. Changed by `.set at' and `.set noat'. */
151 /* Non-zero if we should warn when a macro instruction expands into
152 more than one machine instruction. Changed by `.set nomacro' and
154 int warn_about_macros
;
155 /* Non-zero if we should not move instructions. Changed by `.set
156 move', `.set volatile', `.set nomove', and `.set novolatile'. */
158 /* Non-zero if we should not optimize branches by moving the target
159 of the branch into the delay slot. Actually, we don't perform
160 this optimization anyhow. Changed by `.set bopt' and `.set
163 /* Non-zero if we should not autoextend mips16 instructions.
164 Changed by `.set autoextend' and `.set noautoextend'. */
166 /* Restrict general purpose registers and floating point registers
167 to 32 bit. This is initially determined when -mgp32 or -mfp32
168 is passed but can changed if the assembler code uses .set mipsN. */
171 /* The ABI currently in use. This is changed by .set mipsN to loosen
172 restrictions and doesn't affect the whole file. */
173 enum mips_abi_level abi
;
176 /* True if -mgp32 was passed. */
177 static int file_mips_gp32
= 0;
179 /* True if -mfp32 was passed. */
180 static int file_mips_fp32
= 0;
182 /* This is the struct we use to hold the current set of options. Note
183 that we must set the isa field to ISA_UNKNOWN and the mips16 field to
184 -1 to indicate that they have not been initialized. */
186 static struct mips_set_options mips_opts
=
188 ISA_UNKNOWN
, -1, 0, 0, 0, 0, 0, 0, 0, 0, NO_ABI
191 /* These variables are filled in with the masks of registers used.
192 The object format code reads them and puts them in the appropriate
194 unsigned long mips_gprmask
;
195 unsigned long mips_cprmask
[4];
197 /* MIPS ISA we are using for this output file. */
198 static int file_mips_isa
= ISA_UNKNOWN
;
200 /* The argument of the -mcpu= flag. Historical for code generation. */
201 static int mips_cpu
= CPU_UNKNOWN
;
203 /* The argument of the -march= flag. The architecture we are assembling. */
204 static int mips_arch
= CPU_UNKNOWN
;
206 /* The argument of the -mtune= flag. The architecture for which we
208 static int mips_tune
= CPU_UNKNOWN
;
210 /* Whether we should mark the file EABI64 or EABI32. */
211 static int mips_eabi64
= 0;
213 /* If they asked for mips1 or mips2 and a cpu that is
214 mips3 or greater, then mark the object file 32BITMODE. */
215 static int mips_32bitmode
= 0;
217 /* Some ISA's have delay slots for instructions which read or write
218 from a coprocessor (eg. mips1-mips3); some don't (eg mips4).
219 Return true if instructions marked INSN_LOAD_COPROC_DELAY,
220 INSN_COPROC_MOVE_DELAY, or INSN_WRITE_COND_CODE actually have a
221 delay slot in this ISA. The uses of this macro assume that any
222 ISA that has delay slots for one of these, has them for all. They
223 also assume that ISAs which don't have delays for these insns, don't
224 have delays for the INSN_LOAD_MEMORY_DELAY instructions either. */
225 #define ISA_HAS_COPROC_DELAYS(ISA) ( \
227 || (ISA) == ISA_MIPS2 \
228 || (ISA) == ISA_MIPS3 \
231 /* Return true if ISA supports 64 bit gp register instructions. */
232 #define ISA_HAS_64BIT_REGS(ISA) ( \
234 || (ISA) == ISA_MIPS4 \
235 || (ISA) == ISA_MIPS5 \
236 || (ISA) == ISA_MIPS64 \
239 #define HAVE_32BIT_GPRS \
241 || mips_opts.abi == O32_ABI \
242 || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
244 #define HAVE_32BIT_FPRS \
246 || mips_opts.abi == O32_ABI \
247 || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
249 #define HAVE_64BIT_GPRS (! HAVE_32BIT_GPRS)
250 #define HAVE_64BIT_FPRS (! HAVE_32BIT_FPRS)
252 #define HAVE_NEWABI (mips_opts.abi == N32_ABI || mips_opts.abi == N64_ABI)
254 #define HAVE_64BIT_OBJECTS (mips_opts.abi == N64_ABI)
256 /* We can only have 64bit addresses if the object file format
258 #define HAVE_32BIT_ADDRESSES \
260 || ((bfd_arch_bits_per_address (stdoutput) == 32 \
261 || ! HAVE_64BIT_OBJECTS) \
262 && mips_pic != EMBEDDED_PIC))
264 #define HAVE_64BIT_ADDRESSES (! HAVE_32BIT_ADDRESSES)
266 /* Whether the processor uses hardware interlocks to protect
267 reads from the HI and LO registers, and thus does not
268 require nops to be inserted. */
270 #define hilo_interlocks (mips_arch == CPU_R4010 \
271 || mips_arch == CPU_SB1 \
274 /* Whether the processor uses hardware interlocks to protect reads
275 from the GPRs, and thus does not require nops to be inserted. */
276 #define gpr_interlocks \
277 (mips_opts.isa != ISA_MIPS1 \
278 || mips_arch == CPU_R3900)
280 /* As with other "interlocks" this is used by hardware that has FP
281 (co-processor) interlocks. */
282 /* Itbl support may require additional care here. */
283 #define cop_interlocks (mips_arch == CPU_R4300 \
284 || mips_arch == CPU_SB1 \
287 /* Is this a mfhi or mflo instruction? */
288 #define MF_HILO_INSN(PINFO) \
289 ((PINFO & INSN_READ_HI) || (PINFO & INSN_READ_LO))
291 /* MIPS PIC level. */
295 /* Do not generate PIC code. */
298 /* Generate PIC code as in Irix 4. This is not implemented, and I'm
299 not sure what it is supposed to do. */
302 /* Generate PIC code as in the SVR4 MIPS ABI. */
305 /* Generate PIC code without using a global offset table: the data
306 segment has a maximum size of 64K, all data references are off
307 the $gp register, and all text references are PC relative. This
308 is used on some embedded systems. */
312 static enum mips_pic_level mips_pic
;
314 /* Warn about all NOPS that the assembler generates. */
315 static int warn_nops
= 0;
317 /* 1 if we should generate 32 bit offsets from the GP register in
318 SVR4_PIC mode. Currently has no meaning in other modes. */
319 static int mips_big_got
;
321 /* 1 if trap instructions should used for overflow rather than break
323 static int mips_trap
;
325 /* 1 if double width floating point constants should not be constructed
326 by assembling two single width halves into two single width floating
327 point registers which just happen to alias the double width destination
328 register. On some architectures this aliasing can be disabled by a bit
329 in the status register, and the setting of this bit cannot be determined
330 automatically at assemble time. */
331 static int mips_disable_float_construction
;
333 /* Non-zero if any .set noreorder directives were used. */
335 static int mips_any_noreorder
;
337 /* Non-zero if nops should be inserted when the register referenced in
338 an mfhi/mflo instruction is read in the next two instructions. */
339 static int mips_7000_hilo_fix
;
341 /* The size of the small data section. */
342 static unsigned int g_switch_value
= 8;
343 /* Whether the -G option was used. */
344 static int g_switch_seen
= 0;
349 /* If we can determine in advance that GP optimization won't be
350 possible, we can skip the relaxation stuff that tries to produce
351 GP-relative references. This makes delay slot optimization work
354 This function can only provide a guess, but it seems to work for
355 gcc output. It needs to guess right for gcc, otherwise gcc
356 will put what it thinks is a GP-relative instruction in a branch
359 I don't know if a fix is needed for the SVR4_PIC mode. I've only
360 fixed it for the non-PIC mode. KR 95/04/07 */
361 static int nopic_need_relax
PARAMS ((symbolS
*, int));
363 /* handle of the OPCODE hash table */
364 static struct hash_control
*op_hash
= NULL
;
366 /* The opcode hash table we use for the mips16. */
367 static struct hash_control
*mips16_op_hash
= NULL
;
369 /* This array holds the chars that always start a comment. If the
370 pre-processor is disabled, these aren't very useful */
371 const char comment_chars
[] = "#";
373 /* This array holds the chars that only start a comment at the beginning of
374 a line. If the line seems to have the form '# 123 filename'
375 .line and .file directives will appear in the pre-processed output */
376 /* Note that input_file.c hand checks for '#' at the beginning of the
377 first line of the input file. This is because the compiler outputs
378 #NO_APP at the beginning of its output. */
379 /* Also note that C style comments are always supported. */
380 const char line_comment_chars
[] = "#";
382 /* This array holds machine specific line separator characters. */
383 const char line_separator_chars
[] = ";";
385 /* Chars that can be used to separate mant from exp in floating point nums */
386 const char EXP_CHARS
[] = "eE";
388 /* Chars that mean this number is a floating point constant */
391 const char FLT_CHARS
[] = "rRsSfFdDxXpP";
393 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
394 changed in read.c . Ideally it shouldn't have to know about it at all,
395 but nothing is ideal around here.
398 static char *insn_error
;
400 static int auto_align
= 1;
402 /* When outputting SVR4 PIC code, the assembler needs to know the
403 offset in the stack frame from which to restore the $gp register.
404 This is set by the .cprestore pseudo-op, and saved in this
406 static offsetT mips_cprestore_offset
= -1;
408 /* Similiar for NewABI PIC code, where $gp is callee-saved. NewABI has some
409 more optimizations, it can use a register value instead of a memory-saved
410 offset and even an other than GP as global pointer. */
411 static offsetT mips_cpreturn_offset
= -1;
412 static int mips_cpreturn_register
= -1;
413 static int mips_gp_register
= GP
;
415 /* This is the register which holds the stack frame, as set by the
416 .frame pseudo-op. This is needed to implement .cprestore. */
417 static int mips_frame_reg
= SP
;
419 /* To output NOP instructions correctly, we need to keep information
420 about the previous two instructions. */
422 /* Whether we are optimizing. The default value of 2 means to remove
423 unneeded NOPs and swap branch instructions when possible. A value
424 of 1 means to not swap branches. A value of 0 means to always
426 static int mips_optimize
= 2;
428 /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is
429 equivalent to seeing no -g option at all. */
430 static int mips_debug
= 0;
432 /* The previous instruction. */
433 static struct mips_cl_insn prev_insn
;
435 /* The instruction before prev_insn. */
436 static struct mips_cl_insn prev_prev_insn
;
438 /* If we don't want information for prev_insn or prev_prev_insn, we
439 point the insn_mo field at this dummy integer. */
440 static const struct mips_opcode dummy_opcode
= { NULL
, NULL
, 0, 0, 0, 0 };
442 /* Non-zero if prev_insn is valid. */
443 static int prev_insn_valid
;
445 /* The frag for the previous instruction. */
446 static struct frag
*prev_insn_frag
;
448 /* The offset into prev_insn_frag for the previous instruction. */
449 static long prev_insn_where
;
451 /* The reloc type for the previous instruction, if any. */
452 static bfd_reloc_code_real_type prev_insn_reloc_type
[3];
454 /* The reloc for the previous instruction, if any. */
455 static fixS
*prev_insn_fixp
[3];
457 /* Non-zero if the previous instruction was in a delay slot. */
458 static int prev_insn_is_delay_slot
;
460 /* Non-zero if the previous instruction was in a .set noreorder. */
461 static int prev_insn_unreordered
;
463 /* Non-zero if the previous instruction uses an extend opcode (if
465 static int prev_insn_extended
;
467 /* Non-zero if the previous previous instruction was in a .set
469 static int prev_prev_insn_unreordered
;
471 /* If this is set, it points to a frag holding nop instructions which
472 were inserted before the start of a noreorder section. If those
473 nops turn out to be unnecessary, the size of the frag can be
475 static fragS
*prev_nop_frag
;
477 /* The number of nop instructions we created in prev_nop_frag. */
478 static int prev_nop_frag_holds
;
480 /* The number of nop instructions that we know we need in
482 static int prev_nop_frag_required
;
484 /* The number of instructions we've seen since prev_nop_frag. */
485 static int prev_nop_frag_since
;
487 /* For ECOFF and ELF, relocations against symbols are done in two
488 parts, with a HI relocation and a LO relocation. Each relocation
489 has only 16 bits of space to store an addend. This means that in
490 order for the linker to handle carries correctly, it must be able
491 to locate both the HI and the LO relocation. This means that the
492 relocations must appear in order in the relocation table.
494 In order to implement this, we keep track of each unmatched HI
495 relocation. We then sort them so that they immediately precede the
496 corresponding LO relocation. */
501 struct mips_hi_fixup
*next
;
504 /* The section this fixup is in. */
508 /* The list of unmatched HI relocs. */
510 static struct mips_hi_fixup
*mips_hi_fixup_list
;
512 /* Map normal MIPS register numbers to mips16 register numbers. */
514 #define X ILLEGAL_REG
515 static const int mips32_to_16_reg_map
[] =
517 X
, X
, 2, 3, 4, 5, 6, 7,
518 X
, X
, X
, X
, X
, X
, X
, X
,
519 0, 1, X
, X
, X
, X
, X
, X
,
520 X
, X
, X
, X
, X
, X
, X
, X
524 /* Map mips16 register numbers to normal MIPS register numbers. */
526 static const unsigned int mips16_to_32_reg_map
[] =
528 16, 17, 2, 3, 4, 5, 6, 7
531 /* Since the MIPS does not have multiple forms of PC relative
532 instructions, we do not have to do relaxing as is done on other
533 platforms. However, we do have to handle GP relative addressing
534 correctly, which turns out to be a similar problem.
536 Every macro that refers to a symbol can occur in (at least) two
537 forms, one with GP relative addressing and one without. For
538 example, loading a global variable into a register generally uses
539 a macro instruction like this:
541 If i can be addressed off the GP register (this is true if it is in
542 the .sbss or .sdata section, or if it is known to be smaller than
543 the -G argument) this will generate the following instruction:
545 This instruction will use a GPREL reloc. If i can not be addressed
546 off the GP register, the following instruction sequence will be used:
549 In this case the first instruction will have a HI16 reloc, and the
550 second reloc will have a LO16 reloc. Both relocs will be against
553 The issue here is that we may not know whether i is GP addressable
554 until after we see the instruction that uses it. Therefore, we
555 want to be able to choose the final instruction sequence only at
556 the end of the assembly. This is similar to the way other
557 platforms choose the size of a PC relative instruction only at the
560 When generating position independent code we do not use GP
561 addressing in quite the same way, but the issue still arises as
562 external symbols and local symbols must be handled differently.
564 We handle these issues by actually generating both possible
565 instruction sequences. The longer one is put in a frag_var with
566 type rs_machine_dependent. We encode what to do with the frag in
567 the subtype field. We encode (1) the number of existing bytes to
568 replace, (2) the number of new bytes to use, (3) the offset from
569 the start of the existing bytes to the first reloc we must generate
570 (that is, the offset is applied from the start of the existing
571 bytes after they are replaced by the new bytes, if any), (4) the
572 offset from the start of the existing bytes to the second reloc,
573 (5) whether a third reloc is needed (the third reloc is always four
574 bytes after the second reloc), and (6) whether to warn if this
575 variant is used (this is sometimes needed if .set nomacro or .set
576 noat is in effect). All these numbers are reasonably small.
578 Generating two instruction sequences must be handled carefully to
579 ensure that delay slots are handled correctly. Fortunately, there
580 are a limited number of cases. When the second instruction
581 sequence is generated, append_insn is directed to maintain the
582 existing delay slot information, so it continues to apply to any
583 code after the second instruction sequence. This means that the
584 second instruction sequence must not impose any requirements not
585 required by the first instruction sequence.
587 These variant frags are then handled in functions called by the
588 machine independent code. md_estimate_size_before_relax returns
589 the final size of the frag. md_convert_frag sets up the final form
590 of the frag. tc_gen_reloc adjust the first reloc and adds a second
592 #define RELAX_ENCODE(old, new, reloc1, reloc2, reloc3, warn) \
596 | (((reloc1) + 64) << 9) \
597 | (((reloc2) + 64) << 2) \
598 | ((reloc3) ? (1 << 1) : 0) \
600 #define RELAX_OLD(i) (((i) >> 23) & 0x7f)
601 #define RELAX_NEW(i) (((i) >> 16) & 0x7f)
602 #define RELAX_RELOC1(i) ((valueT) (((i) >> 9) & 0x7f) - 64)
603 #define RELAX_RELOC2(i) ((valueT) (((i) >> 2) & 0x7f) - 64)
604 #define RELAX_RELOC3(i) (((i) >> 1) & 1)
605 #define RELAX_WARN(i) ((i) & 1)
607 /* For mips16 code, we use an entirely different form of relaxation.
608 mips16 supports two versions of most instructions which take
609 immediate values: a small one which takes some small value, and a
610 larger one which takes a 16 bit value. Since branches also follow
611 this pattern, relaxing these values is required.
613 We can assemble both mips16 and normal MIPS code in a single
614 object. Therefore, we need to support this type of relaxation at
615 the same time that we support the relaxation described above. We
616 use the high bit of the subtype field to distinguish these cases.
618 The information we store for this type of relaxation is the
619 argument code found in the opcode file for this relocation, whether
620 the user explicitly requested a small or extended form, and whether
621 the relocation is in a jump or jal delay slot. That tells us the
622 size of the value, and how it should be stored. We also store
623 whether the fragment is considered to be extended or not. We also
624 store whether this is known to be a branch to a different section,
625 whether we have tried to relax this frag yet, and whether we have
626 ever extended a PC relative fragment because of a shift count. */
627 #define RELAX_MIPS16_ENCODE(type, small, ext, dslot, jal_dslot) \
630 | ((small) ? 0x100 : 0) \
631 | ((ext) ? 0x200 : 0) \
632 | ((dslot) ? 0x400 : 0) \
633 | ((jal_dslot) ? 0x800 : 0))
634 #define RELAX_MIPS16_P(i) (((i) & 0x80000000) != 0)
635 #define RELAX_MIPS16_TYPE(i) ((i) & 0xff)
636 #define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x100) != 0)
637 #define RELAX_MIPS16_USER_EXT(i) (((i) & 0x200) != 0)
638 #define RELAX_MIPS16_DSLOT(i) (((i) & 0x400) != 0)
639 #define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x800) != 0)
640 #define RELAX_MIPS16_EXTENDED(i) (((i) & 0x1000) != 0)
641 #define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x1000)
642 #define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) &~ 0x1000)
643 #define RELAX_MIPS16_LONG_BRANCH(i) (((i) & 0x2000) != 0)
644 #define RELAX_MIPS16_MARK_LONG_BRANCH(i) ((i) | 0x2000)
645 #define RELAX_MIPS16_CLEAR_LONG_BRANCH(i) ((i) &~ 0x2000)
647 /* Prototypes for static functions. */
650 #define internalError() \
651 as_fatal (_("internal Error, line %d, %s"), __LINE__, __FILE__)
653 #define internalError() as_fatal (_("MIPS internal Error"));
656 enum mips_regclass
{ MIPS_GR_REG
, MIPS_FP_REG
, MIPS16_REG
};
658 static int insn_uses_reg
PARAMS ((struct mips_cl_insn
*ip
,
659 unsigned int reg
, enum mips_regclass
class));
660 static int reg_needs_delay
PARAMS ((unsigned int));
661 static void mips16_mark_labels
PARAMS ((void));
662 static void append_insn
PARAMS ((char *place
,
663 struct mips_cl_insn
* ip
,
665 bfd_reloc_code_real_type
*r
,
667 static void mips_no_prev_insn
PARAMS ((int));
668 static void mips_emit_delays
PARAMS ((boolean
));
670 static void macro_build
PARAMS ((char *place
, int *counter
, expressionS
* ep
,
671 const char *name
, const char *fmt
,
674 static void macro_build ();
676 static void mips16_macro_build
PARAMS ((char *, int *, expressionS
*,
677 const char *, const char *,
679 static void macro_build_lui
PARAMS ((char *place
, int *counter
,
680 expressionS
* ep
, int regnum
));
681 static void set_at
PARAMS ((int *counter
, int reg
, int unsignedp
));
682 static void check_absolute_expr
PARAMS ((struct mips_cl_insn
* ip
,
684 static void load_register
PARAMS ((int *, int, expressionS
*, int));
685 static void load_address
PARAMS ((int *, int, expressionS
*, int, int *));
686 static void move_register
PARAMS ((int *, int, int));
687 static void macro
PARAMS ((struct mips_cl_insn
* ip
));
688 static void mips16_macro
PARAMS ((struct mips_cl_insn
* ip
));
689 #ifdef LOSING_COMPILER
690 static void macro2
PARAMS ((struct mips_cl_insn
* ip
));
692 static void mips_ip
PARAMS ((char *str
, struct mips_cl_insn
* ip
));
693 static void mips16_ip
PARAMS ((char *str
, struct mips_cl_insn
* ip
));
694 static void mips16_immed
PARAMS ((char *, unsigned int, int, offsetT
, boolean
,
695 boolean
, boolean
, unsigned long *,
696 boolean
*, unsigned short *));
697 static int my_getSmallParser
PARAMS ((char **, unsigned int *, int *));
698 static int my_getSmallExpression
PARAMS ((expressionS
*, char *));
699 static void my_getExpression
PARAMS ((expressionS
*, char *));
701 static int support_64bit_objects
PARAMS((void));
703 static symbolS
*get_symbol
PARAMS ((void));
704 static void mips_align
PARAMS ((int to
, int fill
, symbolS
*label
));
705 static void s_align
PARAMS ((int));
706 static void s_change_sec
PARAMS ((int));
707 static void s_cons
PARAMS ((int));
708 static void s_float_cons
PARAMS ((int));
709 static void s_mips_globl
PARAMS ((int));
710 static void s_option
PARAMS ((int));
711 static void s_mipsset
PARAMS ((int));
712 static void s_abicalls
PARAMS ((int));
713 static void s_cpload
PARAMS ((int));
714 static void s_cpsetup
PARAMS ((int));
715 static void s_cplocal
PARAMS ((int));
716 static void s_cprestore
PARAMS ((int));
717 static void s_cpreturn
PARAMS ((int));
718 static void s_gpvalue
PARAMS ((int));
719 static void s_gpword
PARAMS ((int));
720 static void s_cpadd
PARAMS ((int));
721 static void s_insn
PARAMS ((int));
722 static void md_obj_begin
PARAMS ((void));
723 static void md_obj_end
PARAMS ((void));
724 static long get_number
PARAMS ((void));
725 static void s_mips_ent
PARAMS ((int));
726 static void s_mips_end
PARAMS ((int));
727 static void s_mips_frame
PARAMS ((int));
728 static void s_mips_mask
PARAMS ((int));
729 static void s_mips_stab
PARAMS ((int));
730 static void s_mips_weakext
PARAMS ((int));
731 static void s_file
PARAMS ((int));
732 static int mips16_extended_frag
PARAMS ((fragS
*, asection
*, long));
733 static const char *mips_isa_to_str
PARAMS ((int));
734 static const char *mips_cpu_to_str
PARAMS ((int));
735 static int validate_mips_insn
PARAMS ((const struct mips_opcode
*));
736 static void show
PARAMS ((FILE *, char *, int *, int *));
738 static int mips_need_elf_addend_fixup
PARAMS ((fixS
*));
741 /* Return values of my_getSmallExpression(). */
748 /* Direct relocation creation by %percent_op(). */
767 /* Table and functions used to map between CPU/ISA names, and
768 ISA levels, and CPU numbers. */
772 const char *name
; /* CPU or ISA name. */
773 int is_isa
; /* Is this an ISA? (If 0, a CPU.) */
774 int isa
; /* ISA level. */
775 int cpu
; /* CPU number (default CPU if ISA). */
778 static const struct mips_cpu_info
*mips_cpu_info_from_name
PARAMS ((const char *));
779 static const struct mips_cpu_info
*mips_cpu_info_from_isa
PARAMS ((int));
780 static const struct mips_cpu_info
*mips_cpu_info_from_cpu
PARAMS ((int));
784 The following pseudo-ops from the Kane and Heinrich MIPS book
785 should be defined here, but are currently unsupported: .alias,
786 .galive, .gjaldef, .gjrlive, .livereg, .noalias.
788 The following pseudo-ops from the Kane and Heinrich MIPS book are
789 specific to the type of debugging information being generated, and
790 should be defined by the object format: .aent, .begin, .bend,
791 .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp,
794 The following pseudo-ops from the Kane and Heinrich MIPS book are
795 not MIPS CPU specific, but are also not specific to the object file
796 format. This file is probably the best place to define them, but
797 they are not currently supported: .asm0, .endr, .lab, .repeat,
800 static const pseudo_typeS mips_pseudo_table
[] =
802 /* MIPS specific pseudo-ops. */
803 {"option", s_option
, 0},
804 {"set", s_mipsset
, 0},
805 {"rdata", s_change_sec
, 'r'},
806 {"sdata", s_change_sec
, 's'},
807 {"livereg", s_ignore
, 0},
808 {"abicalls", s_abicalls
, 0},
809 {"cpload", s_cpload
, 0},
810 {"cpsetup", s_cpsetup
, 0},
811 {"cplocal", s_cplocal
, 0},
812 {"cprestore", s_cprestore
, 0},
813 {"cpreturn", s_cpreturn
, 0},
814 {"gpvalue", s_gpvalue
, 0},
815 {"gpword", s_gpword
, 0},
816 {"cpadd", s_cpadd
, 0},
819 /* Relatively generic pseudo-ops that happen to be used on MIPS
821 {"asciiz", stringer
, 1},
822 {"bss", s_change_sec
, 'b'},
825 {"dword", s_cons
, 3},
826 {"weakext", s_mips_weakext
, 0},
828 /* These pseudo-ops are defined in read.c, but must be overridden
829 here for one reason or another. */
830 {"align", s_align
, 0},
832 {"data", s_change_sec
, 'd'},
833 {"double", s_float_cons
, 'd'},
834 {"float", s_float_cons
, 'f'},
835 {"globl", s_mips_globl
, 0},
836 {"global", s_mips_globl
, 0},
837 {"hword", s_cons
, 1},
842 {"short", s_cons
, 1},
843 {"single", s_float_cons
, 'f'},
844 {"stabn", s_mips_stab
, 'n'},
845 {"text", s_change_sec
, 't'},
848 #ifdef MIPS_STABS_ELF
849 { "extern", ecoff_directive_extern
, 0},
855 static const pseudo_typeS mips_nonecoff_pseudo_table
[] =
857 /* These pseudo-ops should be defined by the object file format.
858 However, a.out doesn't support them, so we have versions here. */
859 {"aent", s_mips_ent
, 1},
860 {"bgnb", s_ignore
, 0},
861 {"end", s_mips_end
, 0},
862 {"endb", s_ignore
, 0},
863 {"ent", s_mips_ent
, 0},
865 {"fmask", s_mips_mask
, 'F'},
866 {"frame", s_mips_frame
, 0},
867 {"loc", s_ignore
, 0},
868 {"mask", s_mips_mask
, 'R'},
869 {"verstamp", s_ignore
, 0},
873 extern void pop_insert
PARAMS ((const pseudo_typeS
*));
878 pop_insert (mips_pseudo_table
);
879 if (! ECOFF_DEBUGGING
)
880 pop_insert (mips_nonecoff_pseudo_table
);
883 /* Symbols labelling the current insn. */
885 struct insn_label_list
887 struct insn_label_list
*next
;
891 static struct insn_label_list
*insn_labels
;
892 static struct insn_label_list
*free_insn_labels
;
894 static void mips_clear_insn_labels
PARAMS ((void));
897 mips_clear_insn_labels ()
899 register struct insn_label_list
**pl
;
901 for (pl
= &free_insn_labels
; *pl
!= NULL
; pl
= &(*pl
)->next
)
907 static char *expr_end
;
909 /* Expressions which appear in instructions. These are set by
912 static expressionS imm_expr
;
913 static expressionS offset_expr
;
915 /* Relocs associated with imm_expr and offset_expr. */
917 static bfd_reloc_code_real_type imm_reloc
[3]
918 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
919 static bfd_reloc_code_real_type offset_reloc
[3]
920 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
922 /* This is set by mips_ip if imm_reloc is an unmatched HI16_S reloc. */
924 static boolean imm_unmatched_hi
;
926 /* These are set by mips16_ip if an explicit extension is used. */
928 static boolean mips16_small
, mips16_ext
;
930 #ifdef MIPS_STABS_ELF
931 /* The pdr segment for per procedure frame/regmask info */
937 mips_isa_to_str (isa
)
940 const struct mips_cpu_info
*ci
;
943 ci
= mips_cpu_info_from_isa (isa
);
947 sprintf (s
, "ISA#%d", isa
);
952 mips_cpu_to_str (cpu
)
955 const struct mips_cpu_info
*ci
;
958 ci
= mips_cpu_info_from_cpu (cpu
);
962 sprintf (s
, "CPU#%d", cpu
);
966 /* The default target format to use. */
969 mips_target_format ()
971 switch (OUTPUT_FLAVOR
)
973 case bfd_target_aout_flavour
:
974 return target_big_endian
? "a.out-mips-big" : "a.out-mips-little";
975 case bfd_target_ecoff_flavour
:
976 return target_big_endian
? "ecoff-bigmips" : ECOFF_LITTLE_FORMAT
;
977 case bfd_target_coff_flavour
:
979 case bfd_target_elf_flavour
:
981 /* This is traditional mips */
982 return (target_big_endian
983 ? (HAVE_64BIT_OBJECTS
? "elf64-tradbigmips"
984 : "elf32-tradbigmips")
985 : (HAVE_64BIT_OBJECTS
? "elf64-tradlittlemips"
986 : "elf32-tradlittlemips"));
988 return (target_big_endian
989 ? (HAVE_64BIT_OBJECTS
? "elf64-bigmips" : "elf32-bigmips")
990 : (HAVE_64BIT_OBJECTS
? "elf64-littlemips"
991 : "elf32-littlemips"));
999 /* This function is called once, at assembler startup time. It should
1000 set up all the tables, etc. that the MD part of the assembler will need. */
1005 register const char *retval
= NULL
;
1010 int mips_isa_from_cpu
;
1011 int target_cpu_had_mips16
= 0;
1012 const struct mips_cpu_info
*ci
;
1014 /* GP relative stuff not working for PE */
1015 if (strncmp (TARGET_OS
, "pe", 2) == 0
1016 && g_switch_value
!= 0)
1019 as_bad (_("-G not supported in this configuration."));
1024 if (strcmp (cpu
+ (sizeof TARGET_CPU
) - 3, "el") == 0)
1026 a
= xmalloc (sizeof TARGET_CPU
);
1027 strcpy (a
, TARGET_CPU
);
1028 a
[(sizeof TARGET_CPU
) - 3] = '\0';
1032 if (strncmp (cpu
, "mips16", sizeof "mips16" - 1) == 0)
1034 target_cpu_had_mips16
= 1;
1035 cpu
+= sizeof "mips16" - 1;
1038 if (mips_opts
.mips16
< 0)
1039 mips_opts
.mips16
= target_cpu_had_mips16
;
1041 /* Backward compatibility for historic -mcpu= option. Check for
1042 incompatible options, warn if -mcpu is used. */
1043 if (mips_cpu
!= CPU_UNKNOWN
1044 && mips_arch
!= CPU_UNKNOWN
1045 && mips_cpu
!= mips_arch
)
1047 as_fatal (_("The -mcpu option can't be used together with -march. "
1048 "Use -mtune instead of -mcpu."));
1051 if (mips_cpu
!= CPU_UNKNOWN
1052 && mips_tune
!= CPU_UNKNOWN
1053 && mips_cpu
!= mips_tune
)
1055 as_fatal (_("The -mcpu option can't be used together with -mtune. "
1056 "Use -march instead of -mcpu."));
1059 if (mips_arch
== CPU_UNKNOWN
&& mips_cpu
!= CPU_UNKNOWN
)
1061 ci
= mips_cpu_info_from_cpu (mips_cpu
);
1062 assert (ci
!= NULL
);
1063 mips_arch
= ci
->cpu
;
1064 as_warn (_("The -mcpu option is deprecated. Please use -march and "
1065 "-mtune instead."));
1068 /* At this point, mips_arch will either be CPU_UNKNOWN if no ARCH was
1069 specified on the command line, or some other value if one was.
1070 Similarly, mips_opts.isa will be ISA_UNKNOWN if not specified on
1071 the command line, or will be set otherwise if one was. */
1072 if (mips_arch
!= CPU_UNKNOWN
&& mips_opts
.isa
!= ISA_UNKNOWN
)
1074 /* We have to check if the isa is the default isa of arch. Otherwise
1075 we'll get invalid object file headers. */
1076 ci
= mips_cpu_info_from_cpu (mips_arch
);
1077 assert (ci
!= NULL
);
1078 if (mips_opts
.isa
!= ci
->isa
)
1080 /* This really should be an error instead of a warning, but old
1081 compilers only have -mcpu which sets both arch and tune. For
1082 now, we discard arch and preserve tune. */
1083 as_warn (_("The -march option is incompatible to -mipsN and "
1084 "therefore ignored."));
1085 if (mips_tune
== CPU_UNKNOWN
)
1086 mips_tune
= mips_arch
;
1087 ci
= mips_cpu_info_from_isa (mips_opts
.isa
);
1088 assert (ci
!= NULL
);
1089 mips_arch
= ci
->cpu
;
1092 else if (mips_arch
!= CPU_UNKNOWN
&& mips_opts
.isa
== ISA_UNKNOWN
)
1094 /* We have ARCH, we need ISA. */
1095 ci
= mips_cpu_info_from_cpu (mips_arch
);
1096 assert (ci
!= NULL
);
1097 mips_opts
.isa
= ci
->isa
;
1099 else if (mips_arch
== CPU_UNKNOWN
&& mips_opts
.isa
!= ISA_UNKNOWN
)
1101 /* We have ISA, we need default ARCH. */
1102 ci
= mips_cpu_info_from_isa (mips_opts
.isa
);
1103 assert (ci
!= NULL
);
1104 mips_arch
= ci
->cpu
;
1108 /* We need to set both ISA and ARCH from target cpu. */
1109 ci
= mips_cpu_info_from_name (cpu
);
1111 ci
= mips_cpu_info_from_cpu (CPU_R3000
);
1112 assert (ci
!= NULL
);
1113 mips_opts
.isa
= ci
->isa
;
1114 mips_arch
= ci
->cpu
;
1117 if (mips_tune
== CPU_UNKNOWN
)
1118 mips_tune
= mips_arch
;
1120 ci
= mips_cpu_info_from_cpu (mips_arch
);
1121 assert (ci
!= NULL
);
1122 mips_isa_from_cpu
= ci
->isa
;
1124 /* End of TARGET_CPU processing, get rid of malloced memory
1133 if (mips_opts
.isa
== ISA_MIPS1
&& mips_trap
)
1134 as_bad (_("trap exception not supported at ISA 1"));
1136 /* Set the EABI kind based on the ISA before the user gets
1137 to change the ISA with directives. This isn't really
1138 the best, but then neither is basing the abi on the isa. */
1139 if (ISA_HAS_64BIT_REGS (mips_opts
.isa
)
1140 && mips_opts
.abi
== EABI_ABI
)
1143 /* If they asked for mips1 or mips2 and a cpu that is
1144 mips3 or greater, then mark the object file 32BITMODE. */
1145 if (mips_isa_from_cpu
!= ISA_UNKNOWN
1146 && ! ISA_HAS_64BIT_REGS (mips_opts
.isa
)
1147 && ISA_HAS_64BIT_REGS (mips_isa_from_cpu
))
1150 if (! bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, mips_arch
))
1151 as_warn (_("Could not set architecture and machine"));
1153 file_mips_isa
= mips_opts
.isa
;
1154 file_mips_abi
= mips_opts
.abi
;
1155 mips_opts
.gp32
= file_mips_gp32
;
1156 mips_opts
.fp32
= file_mips_fp32
;
1158 op_hash
= hash_new ();
1160 for (i
= 0; i
< NUMOPCODES
;)
1162 const char *name
= mips_opcodes
[i
].name
;
1164 retval
= hash_insert (op_hash
, name
, (PTR
) &mips_opcodes
[i
]);
1167 fprintf (stderr
, _("internal error: can't hash `%s': %s\n"),
1168 mips_opcodes
[i
].name
, retval
);
1169 /* Probably a memory allocation problem? Give up now. */
1170 as_fatal (_("Broken assembler. No assembly attempted."));
1174 if (mips_opcodes
[i
].pinfo
!= INSN_MACRO
)
1176 if (!validate_mips_insn (&mips_opcodes
[i
]))
1181 while ((i
< NUMOPCODES
) && !strcmp (mips_opcodes
[i
].name
, name
));
1184 mips16_op_hash
= hash_new ();
1187 while (i
< bfd_mips16_num_opcodes
)
1189 const char *name
= mips16_opcodes
[i
].name
;
1191 retval
= hash_insert (mips16_op_hash
, name
, (PTR
) &mips16_opcodes
[i
]);
1193 as_fatal (_("internal: can't hash `%s': %s"),
1194 mips16_opcodes
[i
].name
, retval
);
1197 if (mips16_opcodes
[i
].pinfo
!= INSN_MACRO
1198 && ((mips16_opcodes
[i
].match
& mips16_opcodes
[i
].mask
)
1199 != mips16_opcodes
[i
].match
))
1201 fprintf (stderr
, _("internal error: bad mips16 opcode: %s %s\n"),
1202 mips16_opcodes
[i
].name
, mips16_opcodes
[i
].args
);
1207 while (i
< bfd_mips16_num_opcodes
1208 && strcmp (mips16_opcodes
[i
].name
, name
) == 0);
1212 as_fatal (_("Broken assembler. No assembly attempted."));
1214 /* We add all the general register names to the symbol table. This
1215 helps us detect invalid uses of them. */
1216 for (i
= 0; i
< 32; i
++)
1220 sprintf (buf
, "$%d", i
);
1221 symbol_table_insert (symbol_new (buf
, reg_section
, i
,
1222 &zero_address_frag
));
1224 symbol_table_insert (symbol_new ("$fp", reg_section
, FP
,
1225 &zero_address_frag
));
1226 symbol_table_insert (symbol_new ("$sp", reg_section
, SP
,
1227 &zero_address_frag
));
1228 symbol_table_insert (symbol_new ("$gp", reg_section
, GP
,
1229 &zero_address_frag
));
1230 symbol_table_insert (symbol_new ("$at", reg_section
, AT
,
1231 &zero_address_frag
));
1232 symbol_table_insert (symbol_new ("$kt0", reg_section
, KT0
,
1233 &zero_address_frag
));
1234 symbol_table_insert (symbol_new ("$kt1", reg_section
, KT1
,
1235 &zero_address_frag
));
1236 symbol_table_insert (symbol_new ("$pc", reg_section
, -1,
1237 &zero_address_frag
));
1239 mips_no_prev_insn (false);
1242 mips_cprmask
[0] = 0;
1243 mips_cprmask
[1] = 0;
1244 mips_cprmask
[2] = 0;
1245 mips_cprmask
[3] = 0;
1247 /* set the default alignment for the text section (2**2) */
1248 record_alignment (text_section
, 2);
1250 if (USE_GLOBAL_POINTER_OPT
)
1251 bfd_set_gp_size (stdoutput
, g_switch_value
);
1253 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
1255 /* On a native system, sections must be aligned to 16 byte
1256 boundaries. When configured for an embedded ELF target, we
1258 if (strcmp (TARGET_OS
, "elf") != 0)
1260 (void) bfd_set_section_alignment (stdoutput
, text_section
, 4);
1261 (void) bfd_set_section_alignment (stdoutput
, data_section
, 4);
1262 (void) bfd_set_section_alignment (stdoutput
, bss_section
, 4);
1265 /* Create a .reginfo section for register masks and a .mdebug
1266 section for debugging information. */
1274 subseg
= now_subseg
;
1276 /* The ABI says this section should be loaded so that the
1277 running program can access it. However, we don't load it
1278 if we are configured for an embedded target */
1279 flags
= SEC_READONLY
| SEC_DATA
;
1280 if (strcmp (TARGET_OS
, "elf") != 0)
1281 flags
|= SEC_ALLOC
| SEC_LOAD
;
1285 sec
= subseg_new (".reginfo", (subsegT
) 0);
1287 (void) bfd_set_section_flags (stdoutput
, sec
, flags
);
1288 (void) bfd_set_section_alignment (stdoutput
, sec
, 2);
1291 mips_regmask_frag
= frag_more (sizeof (Elf32_External_RegInfo
));
1296 /* The 64-bit ABI uses a .MIPS.options section rather than
1297 .reginfo section. */
1298 sec
= subseg_new (".MIPS.options", (subsegT
) 0);
1299 (void) bfd_set_section_flags (stdoutput
, sec
, flags
);
1300 (void) bfd_set_section_alignment (stdoutput
, sec
, 3);
1303 /* Set up the option header. */
1305 Elf_Internal_Options opthdr
;
1308 opthdr
.kind
= ODK_REGINFO
;
1309 opthdr
.size
= (sizeof (Elf_External_Options
)
1310 + sizeof (Elf64_External_RegInfo
));
1313 f
= frag_more (sizeof (Elf_External_Options
));
1314 bfd_mips_elf_swap_options_out (stdoutput
, &opthdr
,
1315 (Elf_External_Options
*) f
);
1317 mips_regmask_frag
= frag_more (sizeof (Elf64_External_RegInfo
));
1322 if (ECOFF_DEBUGGING
)
1324 sec
= subseg_new (".mdebug", (subsegT
) 0);
1325 (void) bfd_set_section_flags (stdoutput
, sec
,
1326 SEC_HAS_CONTENTS
| SEC_READONLY
);
1327 (void) bfd_set_section_alignment (stdoutput
, sec
, 2);
1330 #ifdef MIPS_STABS_ELF
1331 pdr_seg
= subseg_new (".pdr", (subsegT
) 0);
1332 (void) bfd_set_section_flags (stdoutput
, pdr_seg
,
1333 SEC_READONLY
| SEC_RELOC
| SEC_DEBUGGING
);
1334 (void) bfd_set_section_alignment (stdoutput
, pdr_seg
, 2);
1337 subseg_set (seg
, subseg
);
1341 if (! ECOFF_DEBUGGING
)
1348 if (! ECOFF_DEBUGGING
)
1356 struct mips_cl_insn insn
;
1357 bfd_reloc_code_real_type unused_reloc
[3]
1358 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
1360 imm_expr
.X_op
= O_absent
;
1361 imm_unmatched_hi
= false;
1362 offset_expr
.X_op
= O_absent
;
1363 imm_reloc
[0] = BFD_RELOC_UNUSED
;
1364 imm_reloc
[1] = BFD_RELOC_UNUSED
;
1365 imm_reloc
[2] = BFD_RELOC_UNUSED
;
1366 offset_reloc
[0] = BFD_RELOC_UNUSED
;
1367 offset_reloc
[1] = BFD_RELOC_UNUSED
;
1368 offset_reloc
[2] = BFD_RELOC_UNUSED
;
1370 if (mips_opts
.mips16
)
1371 mips16_ip (str
, &insn
);
1374 mips_ip (str
, &insn
);
1375 DBG ((_("returned from mips_ip(%s) insn_opcode = 0x%x\n"),
1376 str
, insn
.insn_opcode
));
1381 as_bad ("%s `%s'", insn_error
, str
);
1385 if (insn
.insn_mo
->pinfo
== INSN_MACRO
)
1387 if (mips_opts
.mips16
)
1388 mips16_macro (&insn
);
1394 if (imm_expr
.X_op
!= O_absent
)
1395 append_insn (NULL
, &insn
, &imm_expr
, imm_reloc
, imm_unmatched_hi
);
1396 else if (offset_expr
.X_op
!= O_absent
)
1397 append_insn (NULL
, &insn
, &offset_expr
, offset_reloc
, false);
1399 append_insn (NULL
, &insn
, NULL
, unused_reloc
, false);
1403 /* See whether instruction IP reads register REG. CLASS is the type
1407 insn_uses_reg (ip
, reg
, class)
1408 struct mips_cl_insn
*ip
;
1410 enum mips_regclass
class;
1412 if (class == MIPS16_REG
)
1414 assert (mips_opts
.mips16
);
1415 reg
= mips16_to_32_reg_map
[reg
];
1416 class = MIPS_GR_REG
;
1419 /* Don't report on general register 0, since it never changes. */
1420 if (class == MIPS_GR_REG
&& reg
== 0)
1423 if (class == MIPS_FP_REG
)
1425 assert (! mips_opts
.mips16
);
1426 /* If we are called with either $f0 or $f1, we must check $f0.
1427 This is not optimal, because it will introduce an unnecessary
1428 NOP between "lwc1 $f0" and "swc1 $f1". To fix this we would
1429 need to distinguish reading both $f0 and $f1 or just one of
1430 them. Note that we don't have to check the other way,
1431 because there is no instruction that sets both $f0 and $f1
1432 and requires a delay. */
1433 if ((ip
->insn_mo
->pinfo
& INSN_READ_FPR_S
)
1434 && ((((ip
->insn_opcode
>> OP_SH_FS
) & OP_MASK_FS
) &~(unsigned)1)
1435 == (reg
&~ (unsigned) 1)))
1437 if ((ip
->insn_mo
->pinfo
& INSN_READ_FPR_T
)
1438 && ((((ip
->insn_opcode
>> OP_SH_FT
) & OP_MASK_FT
) &~(unsigned)1)
1439 == (reg
&~ (unsigned) 1)))
1442 else if (! mips_opts
.mips16
)
1444 if ((ip
->insn_mo
->pinfo
& INSN_READ_GPR_S
)
1445 && ((ip
->insn_opcode
>> OP_SH_RS
) & OP_MASK_RS
) == reg
)
1447 if ((ip
->insn_mo
->pinfo
& INSN_READ_GPR_T
)
1448 && ((ip
->insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
) == reg
)
1453 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_X
)
1454 && (mips16_to_32_reg_map
[((ip
->insn_opcode
>> MIPS16OP_SH_RX
)
1455 & MIPS16OP_MASK_RX
)]
1458 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_Y
)
1459 && (mips16_to_32_reg_map
[((ip
->insn_opcode
>> MIPS16OP_SH_RY
)
1460 & MIPS16OP_MASK_RY
)]
1463 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_Z
)
1464 && (mips16_to_32_reg_map
[((ip
->insn_opcode
>> MIPS16OP_SH_MOVE32Z
)
1465 & MIPS16OP_MASK_MOVE32Z
)]
1468 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_T
) && reg
== TREG
)
1470 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_SP
) && reg
== SP
)
1472 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_31
) && reg
== RA
)
1474 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_GPR_X
)
1475 && ((ip
->insn_opcode
>> MIPS16OP_SH_REGR32
)
1476 & MIPS16OP_MASK_REGR32
) == reg
)
1483 /* This function returns true if modifying a register requires a
1487 reg_needs_delay (reg
)
1490 unsigned long prev_pinfo
;
1492 prev_pinfo
= prev_insn
.insn_mo
->pinfo
;
1493 if (! mips_opts
.noreorder
1494 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
1495 && ((prev_pinfo
& INSN_LOAD_COPROC_DELAY
)
1496 || (! gpr_interlocks
1497 && (prev_pinfo
& INSN_LOAD_MEMORY_DELAY
))))
1499 /* A load from a coprocessor or from memory. All load
1500 delays delay the use of general register rt for one
1501 instruction on the r3000. The r6000 and r4000 use
1503 /* Itbl support may require additional care here. */
1504 know (prev_pinfo
& INSN_WRITE_GPR_T
);
1505 if (reg
== ((prev_insn
.insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
))
1512 /* Mark instruction labels in mips16 mode. This permits the linker to
1513 handle them specially, such as generating jalx instructions when
1514 needed. We also make them odd for the duration of the assembly, in
1515 order to generate the right sort of code. We will make them even
1516 in the adjust_symtab routine, while leaving them marked. This is
1517 convenient for the debugger and the disassembler. The linker knows
1518 to make them odd again. */
1521 mips16_mark_labels ()
1523 if (mips_opts
.mips16
)
1525 struct insn_label_list
*l
;
1528 for (l
= insn_labels
; l
!= NULL
; l
= l
->next
)
1531 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
1532 S_SET_OTHER (l
->label
, STO_MIPS16
);
1534 val
= S_GET_VALUE (l
->label
);
1536 S_SET_VALUE (l
->label
, val
+ 1);
1541 /* Output an instruction. PLACE is where to put the instruction; if
1542 it is NULL, this uses frag_more to get room. IP is the instruction
1543 information. ADDRESS_EXPR is an operand of the instruction to be
1544 used with RELOC_TYPE. */
1547 append_insn (place
, ip
, address_expr
, reloc_type
, unmatched_hi
)
1549 struct mips_cl_insn
*ip
;
1550 expressionS
*address_expr
;
1551 bfd_reloc_code_real_type
*reloc_type
;
1552 boolean unmatched_hi
;
1554 register unsigned long prev_pinfo
, pinfo
;
1559 /* Mark instruction labels in mips16 mode. */
1560 if (mips_opts
.mips16
)
1561 mips16_mark_labels ();
1563 prev_pinfo
= prev_insn
.insn_mo
->pinfo
;
1564 pinfo
= ip
->insn_mo
->pinfo
;
1566 if (place
== NULL
&& (! mips_opts
.noreorder
|| prev_nop_frag
!= NULL
))
1570 /* If the previous insn required any delay slots, see if we need
1571 to insert a NOP or two. There are eight kinds of possible
1572 hazards, of which an instruction can have at most one type.
1573 (1) a load from memory delay
1574 (2) a load from a coprocessor delay
1575 (3) an unconditional branch delay
1576 (4) a conditional branch delay
1577 (5) a move to coprocessor register delay
1578 (6) a load coprocessor register from memory delay
1579 (7) a coprocessor condition code delay
1580 (8) a HI/LO special register delay
1582 There are a lot of optimizations we could do that we don't.
1583 In particular, we do not, in general, reorder instructions.
1584 If you use gcc with optimization, it will reorder
1585 instructions and generally do much more optimization then we
1586 do here; repeating all that work in the assembler would only
1587 benefit hand written assembly code, and does not seem worth
1590 /* This is how a NOP is emitted. */
1591 #define emit_nop() \
1593 ? md_number_to_chars (frag_more (2), 0x6500, 2) \
1594 : md_number_to_chars (frag_more (4), 0, 4))
1596 /* The previous insn might require a delay slot, depending upon
1597 the contents of the current insn. */
1598 if (! mips_opts
.mips16
1599 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
1600 && (((prev_pinfo
& INSN_LOAD_COPROC_DELAY
)
1601 && ! cop_interlocks
)
1602 || (! gpr_interlocks
1603 && (prev_pinfo
& INSN_LOAD_MEMORY_DELAY
))))
1605 /* A load from a coprocessor or from memory. All load
1606 delays delay the use of general register rt for one
1607 instruction on the r3000. The r6000 and r4000 use
1609 /* Itbl support may require additional care here. */
1610 know (prev_pinfo
& INSN_WRITE_GPR_T
);
1611 if (mips_optimize
== 0
1612 || insn_uses_reg (ip
,
1613 ((prev_insn
.insn_opcode
>> OP_SH_RT
)
1618 else if (! mips_opts
.mips16
1619 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
1620 && (((prev_pinfo
& INSN_COPROC_MOVE_DELAY
)
1621 && ! cop_interlocks
)
1622 || (mips_opts
.isa
== ISA_MIPS1
1623 && (prev_pinfo
& INSN_COPROC_MEMORY_DELAY
))))
1625 /* A generic coprocessor delay. The previous instruction
1626 modified a coprocessor general or control register. If
1627 it modified a control register, we need to avoid any
1628 coprocessor instruction (this is probably not always
1629 required, but it sometimes is). If it modified a general
1630 register, we avoid using that register.
1632 On the r6000 and r4000 loading a coprocessor register
1633 from memory is interlocked, and does not require a delay.
1635 This case is not handled very well. There is no special
1636 knowledge of CP0 handling, and the coprocessors other
1637 than the floating point unit are not distinguished at
1639 /* Itbl support may require additional care here. FIXME!
1640 Need to modify this to include knowledge about
1641 user specified delays! */
1642 if (prev_pinfo
& INSN_WRITE_FPR_T
)
1644 if (mips_optimize
== 0
1645 || insn_uses_reg (ip
,
1646 ((prev_insn
.insn_opcode
>> OP_SH_FT
)
1651 else if (prev_pinfo
& INSN_WRITE_FPR_S
)
1653 if (mips_optimize
== 0
1654 || insn_uses_reg (ip
,
1655 ((prev_insn
.insn_opcode
>> OP_SH_FS
)
1662 /* We don't know exactly what the previous instruction
1663 does. If the current instruction uses a coprocessor
1664 register, we must insert a NOP. If previous
1665 instruction may set the condition codes, and the
1666 current instruction uses them, we must insert two
1668 /* Itbl support may require additional care here. */
1669 if (mips_optimize
== 0
1670 || ((prev_pinfo
& INSN_WRITE_COND_CODE
)
1671 && (pinfo
& INSN_READ_COND_CODE
)))
1673 else if (pinfo
& INSN_COP
)
1677 else if (! mips_opts
.mips16
1678 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
1679 && (prev_pinfo
& INSN_WRITE_COND_CODE
)
1680 && ! cop_interlocks
)
1682 /* The previous instruction sets the coprocessor condition
1683 codes, but does not require a general coprocessor delay
1684 (this means it is a floating point comparison
1685 instruction). If this instruction uses the condition
1686 codes, we need to insert a single NOP. */
1687 /* Itbl support may require additional care here. */
1688 if (mips_optimize
== 0
1689 || (pinfo
& INSN_READ_COND_CODE
))
1693 /* If we're fixing up mfhi/mflo for the r7000 and the
1694 previous insn was an mfhi/mflo and the current insn
1695 reads the register that the mfhi/mflo wrote to, then
1698 else if (mips_7000_hilo_fix
1699 && MF_HILO_INSN (prev_pinfo
)
1700 && insn_uses_reg (ip
, ((prev_insn
.insn_opcode
>> OP_SH_RD
)
1707 /* If we're fixing up mfhi/mflo for the r7000 and the
1708 2nd previous insn was an mfhi/mflo and the current insn
1709 reads the register that the mfhi/mflo wrote to, then
1712 else if (mips_7000_hilo_fix
1713 && MF_HILO_INSN (prev_prev_insn
.insn_opcode
)
1714 && insn_uses_reg (ip
, ((prev_prev_insn
.insn_opcode
>> OP_SH_RD
)
1722 else if (prev_pinfo
& INSN_READ_LO
)
1724 /* The previous instruction reads the LO register; if the
1725 current instruction writes to the LO register, we must
1726 insert two NOPS. Some newer processors have interlocks.
1727 Also the tx39's multiply instructions can be exectuted
1728 immediatly after a read from HI/LO (without the delay),
1729 though the tx39's divide insns still do require the
1731 if (! (hilo_interlocks
1732 || (mips_tune
== CPU_R3900
&& (pinfo
& INSN_MULT
)))
1733 && (mips_optimize
== 0
1734 || (pinfo
& INSN_WRITE_LO
)))
1736 /* Most mips16 branch insns don't have a delay slot.
1737 If a read from LO is immediately followed by a branch
1738 to a write to LO we have a read followed by a write
1739 less than 2 insns away. We assume the target of
1740 a branch might be a write to LO, and insert a nop
1741 between a read and an immediately following branch. */
1742 else if (mips_opts
.mips16
1743 && (mips_optimize
== 0
1744 || (pinfo
& MIPS16_INSN_BRANCH
)))
1747 else if (prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
1749 /* The previous instruction reads the HI register; if the
1750 current instruction writes to the HI register, we must
1751 insert a NOP. Some newer processors have interlocks.
1752 Also the note tx39's multiply above. */
1753 if (! (hilo_interlocks
1754 || (mips_tune
== CPU_R3900
&& (pinfo
& INSN_MULT
)))
1755 && (mips_optimize
== 0
1756 || (pinfo
& INSN_WRITE_HI
)))
1758 /* Most mips16 branch insns don't have a delay slot.
1759 If a read from HI is immediately followed by a branch
1760 to a write to HI we have a read followed by a write
1761 less than 2 insns away. We assume the target of
1762 a branch might be a write to HI, and insert a nop
1763 between a read and an immediately following branch. */
1764 else if (mips_opts
.mips16
1765 && (mips_optimize
== 0
1766 || (pinfo
& MIPS16_INSN_BRANCH
)))
1770 /* If the previous instruction was in a noreorder section, then
1771 we don't want to insert the nop after all. */
1772 /* Itbl support may require additional care here. */
1773 if (prev_insn_unreordered
)
1776 /* There are two cases which require two intervening
1777 instructions: 1) setting the condition codes using a move to
1778 coprocessor instruction which requires a general coprocessor
1779 delay and then reading the condition codes 2) reading the HI
1780 or LO register and then writing to it (except on processors
1781 which have interlocks). If we are not already emitting a NOP
1782 instruction, we must check for these cases compared to the
1783 instruction previous to the previous instruction. */
1784 if ((! mips_opts
.mips16
1785 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
1786 && (prev_prev_insn
.insn_mo
->pinfo
& INSN_COPROC_MOVE_DELAY
)
1787 && (prev_prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
)
1788 && (pinfo
& INSN_READ_COND_CODE
)
1789 && ! cop_interlocks
)
1790 || ((prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
)
1791 && (pinfo
& INSN_WRITE_LO
)
1792 && ! (hilo_interlocks
1793 || (mips_tune
== CPU_R3900
&& (pinfo
& INSN_MULT
))))
1794 || ((prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
1795 && (pinfo
& INSN_WRITE_HI
)
1796 && ! (hilo_interlocks
1797 || (mips_tune
== CPU_R3900
&& (pinfo
& INSN_MULT
)))))
1802 if (prev_prev_insn_unreordered
)
1805 if (prev_prev_nop
&& nops
== 0)
1808 /* If we are being given a nop instruction, don't bother with
1809 one of the nops we would otherwise output. This will only
1810 happen when a nop instruction is used with mips_optimize set
1813 && ! mips_opts
.noreorder
1814 && ip
->insn_opcode
== (unsigned) (mips_opts
.mips16
? 0x6500 : 0))
1817 /* Now emit the right number of NOP instructions. */
1818 if (nops
> 0 && ! mips_opts
.noreorder
)
1821 unsigned long old_frag_offset
;
1823 struct insn_label_list
*l
;
1825 old_frag
= frag_now
;
1826 old_frag_offset
= frag_now_fix ();
1828 for (i
= 0; i
< nops
; i
++)
1833 listing_prev_line ();
1834 /* We may be at the start of a variant frag. In case we
1835 are, make sure there is enough space for the frag
1836 after the frags created by listing_prev_line. The
1837 argument to frag_grow here must be at least as large
1838 as the argument to all other calls to frag_grow in
1839 this file. We don't have to worry about being in the
1840 middle of a variant frag, because the variants insert
1841 all needed nop instructions themselves. */
1845 for (l
= insn_labels
; l
!= NULL
; l
= l
->next
)
1849 assert (S_GET_SEGMENT (l
->label
) == now_seg
);
1850 symbol_set_frag (l
->label
, frag_now
);
1851 val
= (valueT
) frag_now_fix ();
1852 /* mips16 text labels are stored as odd. */
1853 if (mips_opts
.mips16
)
1855 S_SET_VALUE (l
->label
, val
);
1858 #ifndef NO_ECOFF_DEBUGGING
1859 if (ECOFF_DEBUGGING
)
1860 ecoff_fix_loc (old_frag
, old_frag_offset
);
1863 else if (prev_nop_frag
!= NULL
)
1865 /* We have a frag holding nops we may be able to remove. If
1866 we don't need any nops, we can decrease the size of
1867 prev_nop_frag by the size of one instruction. If we do
1868 need some nops, we count them in prev_nops_required. */
1869 if (prev_nop_frag_since
== 0)
1873 prev_nop_frag
->fr_fix
-= mips_opts
.mips16
? 2 : 4;
1874 --prev_nop_frag_holds
;
1877 prev_nop_frag_required
+= nops
;
1881 if (prev_prev_nop
== 0)
1883 prev_nop_frag
->fr_fix
-= mips_opts
.mips16
? 2 : 4;
1884 --prev_nop_frag_holds
;
1887 ++prev_nop_frag_required
;
1890 if (prev_nop_frag_holds
<= prev_nop_frag_required
)
1891 prev_nop_frag
= NULL
;
1893 ++prev_nop_frag_since
;
1895 /* Sanity check: by the time we reach the second instruction
1896 after prev_nop_frag, we should have used up all the nops
1897 one way or another. */
1898 assert (prev_nop_frag_since
<= 1 || prev_nop_frag
== NULL
);
1902 if (*reloc_type
> BFD_RELOC_UNUSED
)
1904 /* We need to set up a variant frag. */
1905 assert (mips_opts
.mips16
&& address_expr
!= NULL
);
1906 f
= frag_var (rs_machine_dependent
, 4, 0,
1907 RELAX_MIPS16_ENCODE (*reloc_type
- BFD_RELOC_UNUSED
,
1908 mips16_small
, mips16_ext
,
1910 & INSN_UNCOND_BRANCH_DELAY
),
1911 (*prev_insn_reloc_type
1912 == BFD_RELOC_MIPS16_JMP
)),
1913 make_expr_symbol (address_expr
), 0, NULL
);
1915 else if (place
!= NULL
)
1917 else if (mips_opts
.mips16
1919 && *reloc_type
!= BFD_RELOC_MIPS16_JMP
)
1921 /* Make sure there is enough room to swap this instruction with
1922 a following jump instruction. */
1928 if (mips_opts
.mips16
1929 && mips_opts
.noreorder
1930 && (prev_pinfo
& INSN_UNCOND_BRANCH_DELAY
) != 0)
1931 as_warn (_("extended instruction in delay slot"));
1936 fixp
[0] = fixp
[1] = fixp
[2] = NULL
;
1937 if (address_expr
!= NULL
&& *reloc_type
< BFD_RELOC_UNUSED
)
1939 if (address_expr
->X_op
== O_constant
)
1943 switch (*reloc_type
)
1946 ip
->insn_opcode
|= address_expr
->X_add_number
;
1949 case BFD_RELOC_MIPS_HIGHEST
:
1950 tmp
= (address_expr
->X_add_number
+ 0x800080008000) >> 16;
1952 ip
->insn_opcode
|= (tmp
>> 16) & 0xffff;
1955 case BFD_RELOC_MIPS_HIGHER
:
1956 tmp
= (address_expr
->X_add_number
+ 0x80008000) >> 16;
1957 ip
->insn_opcode
|= (tmp
>> 16) & 0xffff;
1960 case BFD_RELOC_HI16_S
:
1961 ip
->insn_opcode
|= ((address_expr
->X_add_number
+ 0x8000)
1965 case BFD_RELOC_HI16
:
1966 ip
->insn_opcode
|= (address_expr
->X_add_number
>> 16) & 0xffff;
1969 case BFD_RELOC_LO16
:
1970 ip
->insn_opcode
|= address_expr
->X_add_number
& 0xffff;
1973 case BFD_RELOC_MIPS_JMP
:
1974 if ((address_expr
->X_add_number
& 3) != 0)
1975 as_bad (_("jump to misaligned address (0x%lx)"),
1976 (unsigned long) address_expr
->X_add_number
);
1977 ip
->insn_opcode
|= (address_expr
->X_add_number
>> 2) & 0x3ffffff;
1980 case BFD_RELOC_MIPS16_JMP
:
1981 if ((address_expr
->X_add_number
& 3) != 0)
1982 as_bad (_("jump to misaligned address (0x%lx)"),
1983 (unsigned long) address_expr
->X_add_number
);
1985 (((address_expr
->X_add_number
& 0x7c0000) << 3)
1986 | ((address_expr
->X_add_number
& 0xf800000) >> 7)
1987 | ((address_expr
->X_add_number
& 0x3fffc) >> 2));
1990 case BFD_RELOC_16_PCREL
:
1991 ip
->insn_opcode
|= address_expr
->X_add_number
& 0xffff;
1994 case BFD_RELOC_16_PCREL_S2
:
2004 /* Don't generate a reloc if we are writing into a variant frag. */
2007 fixp
[0] = fix_new_exp (frag_now
, f
- frag_now
->fr_literal
, 4,
2009 (*reloc_type
== BFD_RELOC_16_PCREL
2010 || *reloc_type
== BFD_RELOC_16_PCREL_S2
),
2013 /* These relocations can have an addend that won't fit in
2014 4 octets for 64bit assembly. */
2015 if (HAVE_64BIT_GPRS
&&
2016 (*reloc_type
== BFD_RELOC_16
2017 || *reloc_type
== BFD_RELOC_32
2018 || *reloc_type
== BFD_RELOC_MIPS_JMP
2019 || *reloc_type
== BFD_RELOC_HI16_S
2020 || *reloc_type
== BFD_RELOC_LO16
2021 || *reloc_type
== BFD_RELOC_GPREL16
2022 || *reloc_type
== BFD_RELOC_MIPS_LITERAL
2023 || *reloc_type
== BFD_RELOC_GPREL32
2024 || *reloc_type
== BFD_RELOC_64
2025 || *reloc_type
== BFD_RELOC_CTOR
2026 || *reloc_type
== BFD_RELOC_MIPS_SUB
2027 || *reloc_type
== BFD_RELOC_MIPS_HIGHEST
2028 || *reloc_type
== BFD_RELOC_MIPS_HIGHER
2029 || *reloc_type
== BFD_RELOC_MIPS_SCN_DISP
2030 || *reloc_type
== BFD_RELOC_MIPS_REL16
2031 || *reloc_type
== BFD_RELOC_MIPS_RELGOT
))
2032 fixp
[0]->fx_no_overflow
= 1;
2036 struct mips_hi_fixup
*hi_fixup
;
2038 assert (*reloc_type
== BFD_RELOC_HI16_S
);
2039 hi_fixup
= ((struct mips_hi_fixup
*)
2040 xmalloc (sizeof (struct mips_hi_fixup
)));
2041 hi_fixup
->fixp
= fixp
[0];
2042 hi_fixup
->seg
= now_seg
;
2043 hi_fixup
->next
= mips_hi_fixup_list
;
2044 mips_hi_fixup_list
= hi_fixup
;
2047 if (reloc_type
[1] != BFD_RELOC_UNUSED
)
2049 /* FIXME: This symbol can be one of
2050 RSS_UNDEF, RSS_GP, RSS_GP0, RSS_LOC. */
2051 address_expr
->X_op
= O_absent
;
2052 address_expr
->X_add_symbol
= 0;
2053 address_expr
->X_add_number
= 0;
2055 fixp
[1] = fix_new_exp (frag_now
, f
- frag_now
->fr_literal
,
2056 4, address_expr
, false,
2059 /* These relocations can have an addend that won't fit in
2060 4 octets for 64bit assembly. */
2061 if (HAVE_64BIT_GPRS
&&
2062 (*reloc_type
== BFD_RELOC_16
2063 || *reloc_type
== BFD_RELOC_32
2064 || *reloc_type
== BFD_RELOC_MIPS_JMP
2065 || *reloc_type
== BFD_RELOC_HI16_S
2066 || *reloc_type
== BFD_RELOC_LO16
2067 || *reloc_type
== BFD_RELOC_GPREL16
2068 || *reloc_type
== BFD_RELOC_MIPS_LITERAL
2069 || *reloc_type
== BFD_RELOC_GPREL32
2070 || *reloc_type
== BFD_RELOC_64
2071 || *reloc_type
== BFD_RELOC_CTOR
2072 || *reloc_type
== BFD_RELOC_MIPS_SUB
2073 || *reloc_type
== BFD_RELOC_MIPS_HIGHEST
2074 || *reloc_type
== BFD_RELOC_MIPS_HIGHER
2075 || *reloc_type
== BFD_RELOC_MIPS_SCN_DISP
2076 || *reloc_type
== BFD_RELOC_MIPS_REL16
2077 || *reloc_type
== BFD_RELOC_MIPS_RELGOT
))
2078 fixp
[1]->fx_no_overflow
= 1;
2080 if (reloc_type
[2] != BFD_RELOC_UNUSED
)
2082 address_expr
->X_op
= O_absent
;
2083 address_expr
->X_add_symbol
= 0;
2084 address_expr
->X_add_number
= 0;
2086 fixp
[2] = fix_new_exp (frag_now
,
2087 f
- frag_now
->fr_literal
, 4,
2088 address_expr
, false,
2091 /* These relocations can have an addend that won't fit in
2092 4 octets for 64bit assembly. */
2093 if (HAVE_64BIT_GPRS
&&
2094 (*reloc_type
== BFD_RELOC_16
2095 || *reloc_type
== BFD_RELOC_32
2096 || *reloc_type
== BFD_RELOC_MIPS_JMP
2097 || *reloc_type
== BFD_RELOC_HI16_S
2098 || *reloc_type
== BFD_RELOC_LO16
2099 || *reloc_type
== BFD_RELOC_GPREL16
2100 || *reloc_type
== BFD_RELOC_MIPS_LITERAL
2101 || *reloc_type
== BFD_RELOC_GPREL32
2102 || *reloc_type
== BFD_RELOC_64
2103 || *reloc_type
== BFD_RELOC_CTOR
2104 || *reloc_type
== BFD_RELOC_MIPS_SUB
2105 || *reloc_type
== BFD_RELOC_MIPS_HIGHEST
2106 || *reloc_type
== BFD_RELOC_MIPS_HIGHER
2107 || *reloc_type
== BFD_RELOC_MIPS_SCN_DISP
2108 || *reloc_type
== BFD_RELOC_MIPS_REL16
2109 || *reloc_type
== BFD_RELOC_MIPS_RELGOT
))
2110 fixp
[2]->fx_no_overflow
= 1;
2117 if (! mips_opts
.mips16
)
2118 md_number_to_chars (f
, ip
->insn_opcode
, 4);
2119 else if (*reloc_type
== BFD_RELOC_MIPS16_JMP
)
2121 md_number_to_chars (f
, ip
->insn_opcode
>> 16, 2);
2122 md_number_to_chars (f
+ 2, ip
->insn_opcode
& 0xffff, 2);
2128 md_number_to_chars (f
, 0xf000 | ip
->extend
, 2);
2131 md_number_to_chars (f
, ip
->insn_opcode
, 2);
2134 /* Update the register mask information. */
2135 if (! mips_opts
.mips16
)
2137 if (pinfo
& INSN_WRITE_GPR_D
)
2138 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
);
2139 if ((pinfo
& (INSN_WRITE_GPR_T
| INSN_READ_GPR_T
)) != 0)
2140 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
);
2141 if (pinfo
& INSN_READ_GPR_S
)
2142 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> OP_SH_RS
) & OP_MASK_RS
);
2143 if (pinfo
& INSN_WRITE_GPR_31
)
2144 mips_gprmask
|= 1 << 31;
2145 if (pinfo
& INSN_WRITE_FPR_D
)
2146 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FD
) & OP_MASK_FD
);
2147 if ((pinfo
& (INSN_WRITE_FPR_S
| INSN_READ_FPR_S
)) != 0)
2148 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FS
) & OP_MASK_FS
);
2149 if ((pinfo
& (INSN_WRITE_FPR_T
| INSN_READ_FPR_T
)) != 0)
2150 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FT
) & OP_MASK_FT
);
2151 if ((pinfo
& INSN_READ_FPR_R
) != 0)
2152 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FR
) & OP_MASK_FR
);
2153 if (pinfo
& INSN_COP
)
2155 /* We don't keep enough information to sort these cases out.
2156 The itbl support does keep this information however, although
2157 we currently don't support itbl fprmats as part of the cop
2158 instruction. May want to add this support in the future. */
2160 /* Never set the bit for $0, which is always zero. */
2161 mips_gprmask
&= ~1 << 0;
2165 if (pinfo
& (MIPS16_INSN_WRITE_X
| MIPS16_INSN_READ_X
))
2166 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_RX
)
2167 & MIPS16OP_MASK_RX
);
2168 if (pinfo
& (MIPS16_INSN_WRITE_Y
| MIPS16_INSN_READ_Y
))
2169 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_RY
)
2170 & MIPS16OP_MASK_RY
);
2171 if (pinfo
& MIPS16_INSN_WRITE_Z
)
2172 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_RZ
)
2173 & MIPS16OP_MASK_RZ
);
2174 if (pinfo
& (MIPS16_INSN_WRITE_T
| MIPS16_INSN_READ_T
))
2175 mips_gprmask
|= 1 << TREG
;
2176 if (pinfo
& (MIPS16_INSN_WRITE_SP
| MIPS16_INSN_READ_SP
))
2177 mips_gprmask
|= 1 << SP
;
2178 if (pinfo
& (MIPS16_INSN_WRITE_31
| MIPS16_INSN_READ_31
))
2179 mips_gprmask
|= 1 << RA
;
2180 if (pinfo
& MIPS16_INSN_WRITE_GPR_Y
)
2181 mips_gprmask
|= 1 << MIPS16OP_EXTRACT_REG32R (ip
->insn_opcode
);
2182 if (pinfo
& MIPS16_INSN_READ_Z
)
2183 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_MOVE32Z
)
2184 & MIPS16OP_MASK_MOVE32Z
);
2185 if (pinfo
& MIPS16_INSN_READ_GPR_X
)
2186 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_REGR32
)
2187 & MIPS16OP_MASK_REGR32
);
2190 if (place
== NULL
&& ! mips_opts
.noreorder
)
2192 /* Filling the branch delay slot is more complex. We try to
2193 switch the branch with the previous instruction, which we can
2194 do if the previous instruction does not set up a condition
2195 that the branch tests and if the branch is not itself the
2196 target of any branch. */
2197 if ((pinfo
& INSN_UNCOND_BRANCH_DELAY
)
2198 || (pinfo
& INSN_COND_BRANCH_DELAY
))
2200 if (mips_optimize
< 2
2201 /* If we have seen .set volatile or .set nomove, don't
2203 || mips_opts
.nomove
!= 0
2204 /* If we had to emit any NOP instructions, then we
2205 already know we can not swap. */
2207 /* If we don't even know the previous insn, we can not
2209 || ! prev_insn_valid
2210 /* If the previous insn is already in a branch delay
2211 slot, then we can not swap. */
2212 || prev_insn_is_delay_slot
2213 /* If the previous previous insn was in a .set
2214 noreorder, we can't swap. Actually, the MIPS
2215 assembler will swap in this situation. However, gcc
2216 configured -with-gnu-as will generate code like
2222 in which we can not swap the bne and INSN. If gcc is
2223 not configured -with-gnu-as, it does not output the
2224 .set pseudo-ops. We don't have to check
2225 prev_insn_unreordered, because prev_insn_valid will
2226 be 0 in that case. We don't want to use
2227 prev_prev_insn_valid, because we do want to be able
2228 to swap at the start of a function. */
2229 || prev_prev_insn_unreordered
2230 /* If the branch is itself the target of a branch, we
2231 can not swap. We cheat on this; all we check for is
2232 whether there is a label on this instruction. If
2233 there are any branches to anything other than a
2234 label, users must use .set noreorder. */
2235 || insn_labels
!= NULL
2236 /* If the previous instruction is in a variant frag, we
2237 can not do the swap. This does not apply to the
2238 mips16, which uses variant frags for different
2240 || (! mips_opts
.mips16
2241 && prev_insn_frag
->fr_type
== rs_machine_dependent
)
2242 /* If the branch reads the condition codes, we don't
2243 even try to swap, because in the sequence
2248 we can not swap, and I don't feel like handling that
2250 || (! mips_opts
.mips16
2251 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
2252 && (pinfo
& INSN_READ_COND_CODE
))
2253 /* We can not swap with an instruction that requires a
2254 delay slot, becase the target of the branch might
2255 interfere with that instruction. */
2256 || (! mips_opts
.mips16
2257 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
2259 /* Itbl support may require additional care here. */
2260 & (INSN_LOAD_COPROC_DELAY
2261 | INSN_COPROC_MOVE_DELAY
2262 | INSN_WRITE_COND_CODE
)))
2263 || (! (hilo_interlocks
2264 || (mips_tune
== CPU_R3900
&& (pinfo
& INSN_MULT
)))
2268 || (! mips_opts
.mips16
2270 && (prev_pinfo
& INSN_LOAD_MEMORY_DELAY
))
2271 || (! mips_opts
.mips16
2272 && mips_opts
.isa
== ISA_MIPS1
2273 /* Itbl support may require additional care here. */
2274 && (prev_pinfo
& INSN_COPROC_MEMORY_DELAY
))
2275 /* We can not swap with a branch instruction. */
2277 & (INSN_UNCOND_BRANCH_DELAY
2278 | INSN_COND_BRANCH_DELAY
2279 | INSN_COND_BRANCH_LIKELY
))
2280 /* We do not swap with a trap instruction, since it
2281 complicates trap handlers to have the trap
2282 instruction be in a delay slot. */
2283 || (prev_pinfo
& INSN_TRAP
)
2284 /* If the branch reads a register that the previous
2285 instruction sets, we can not swap. */
2286 || (! mips_opts
.mips16
2287 && (prev_pinfo
& INSN_WRITE_GPR_T
)
2288 && insn_uses_reg (ip
,
2289 ((prev_insn
.insn_opcode
>> OP_SH_RT
)
2292 || (! mips_opts
.mips16
2293 && (prev_pinfo
& INSN_WRITE_GPR_D
)
2294 && insn_uses_reg (ip
,
2295 ((prev_insn
.insn_opcode
>> OP_SH_RD
)
2298 || (mips_opts
.mips16
2299 && (((prev_pinfo
& MIPS16_INSN_WRITE_X
)
2300 && insn_uses_reg (ip
,
2301 ((prev_insn
.insn_opcode
2303 & MIPS16OP_MASK_RX
),
2305 || ((prev_pinfo
& MIPS16_INSN_WRITE_Y
)
2306 && insn_uses_reg (ip
,
2307 ((prev_insn
.insn_opcode
2309 & MIPS16OP_MASK_RY
),
2311 || ((prev_pinfo
& MIPS16_INSN_WRITE_Z
)
2312 && insn_uses_reg (ip
,
2313 ((prev_insn
.insn_opcode
2315 & MIPS16OP_MASK_RZ
),
2317 || ((prev_pinfo
& MIPS16_INSN_WRITE_T
)
2318 && insn_uses_reg (ip
, TREG
, MIPS_GR_REG
))
2319 || ((prev_pinfo
& MIPS16_INSN_WRITE_31
)
2320 && insn_uses_reg (ip
, RA
, MIPS_GR_REG
))
2321 || ((prev_pinfo
& MIPS16_INSN_WRITE_GPR_Y
)
2322 && insn_uses_reg (ip
,
2323 MIPS16OP_EXTRACT_REG32R (prev_insn
.
2326 /* If the branch writes a register that the previous
2327 instruction sets, we can not swap (we know that
2328 branches write only to RD or to $31). */
2329 || (! mips_opts
.mips16
2330 && (prev_pinfo
& INSN_WRITE_GPR_T
)
2331 && (((pinfo
& INSN_WRITE_GPR_D
)
2332 && (((prev_insn
.insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
)
2333 == ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)))
2334 || ((pinfo
& INSN_WRITE_GPR_31
)
2335 && (((prev_insn
.insn_opcode
>> OP_SH_RT
)
2338 || (! mips_opts
.mips16
2339 && (prev_pinfo
& INSN_WRITE_GPR_D
)
2340 && (((pinfo
& INSN_WRITE_GPR_D
)
2341 && (((prev_insn
.insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)
2342 == ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)))
2343 || ((pinfo
& INSN_WRITE_GPR_31
)
2344 && (((prev_insn
.insn_opcode
>> OP_SH_RD
)
2347 || (mips_opts
.mips16
2348 && (pinfo
& MIPS16_INSN_WRITE_31
)
2349 && ((prev_pinfo
& MIPS16_INSN_WRITE_31
)
2350 || ((prev_pinfo
& MIPS16_INSN_WRITE_GPR_Y
)
2351 && (MIPS16OP_EXTRACT_REG32R (prev_insn
.insn_opcode
)
2353 /* If the branch writes a register that the previous
2354 instruction reads, we can not swap (we know that
2355 branches only write to RD or to $31). */
2356 || (! mips_opts
.mips16
2357 && (pinfo
& INSN_WRITE_GPR_D
)
2358 && insn_uses_reg (&prev_insn
,
2359 ((ip
->insn_opcode
>> OP_SH_RD
)
2362 || (! mips_opts
.mips16
2363 && (pinfo
& INSN_WRITE_GPR_31
)
2364 && insn_uses_reg (&prev_insn
, 31, MIPS_GR_REG
))
2365 || (mips_opts
.mips16
2366 && (pinfo
& MIPS16_INSN_WRITE_31
)
2367 && insn_uses_reg (&prev_insn
, RA
, MIPS_GR_REG
))
2368 /* If we are generating embedded PIC code, the branch
2369 might be expanded into a sequence which uses $at, so
2370 we can't swap with an instruction which reads it. */
2371 || (mips_pic
== EMBEDDED_PIC
2372 && insn_uses_reg (&prev_insn
, AT
, MIPS_GR_REG
))
2373 /* If the previous previous instruction has a load
2374 delay, and sets a register that the branch reads, we
2376 || (! mips_opts
.mips16
2377 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
2378 /* Itbl support may require additional care here. */
2379 && ((prev_prev_insn
.insn_mo
->pinfo
& INSN_LOAD_COPROC_DELAY
)
2380 || (! gpr_interlocks
2381 && (prev_prev_insn
.insn_mo
->pinfo
2382 & INSN_LOAD_MEMORY_DELAY
)))
2383 && insn_uses_reg (ip
,
2384 ((prev_prev_insn
.insn_opcode
>> OP_SH_RT
)
2387 /* If one instruction sets a condition code and the
2388 other one uses a condition code, we can not swap. */
2389 || ((pinfo
& INSN_READ_COND_CODE
)
2390 && (prev_pinfo
& INSN_WRITE_COND_CODE
))
2391 || ((pinfo
& INSN_WRITE_COND_CODE
)
2392 && (prev_pinfo
& INSN_READ_COND_CODE
))
2393 /* If the previous instruction uses the PC, we can not
2395 || (mips_opts
.mips16
2396 && (prev_pinfo
& MIPS16_INSN_READ_PC
))
2397 /* If the previous instruction was extended, we can not
2399 || (mips_opts
.mips16
&& prev_insn_extended
)
2400 /* If the previous instruction had a fixup in mips16
2401 mode, we can not swap. This normally means that the
2402 previous instruction was a 4 byte branch anyhow. */
2403 || (mips_opts
.mips16
&& prev_insn_fixp
[0])
2404 /* If the previous instruction is a sync, sync.l, or
2405 sync.p, we can not swap. */
2406 || (prev_pinfo
& INSN_SYNC
))
2408 /* We could do even better for unconditional branches to
2409 portions of this object file; we could pick up the
2410 instruction at the destination, put it in the delay
2411 slot, and bump the destination address. */
2413 /* Update the previous insn information. */
2414 prev_prev_insn
= *ip
;
2415 prev_insn
.insn_mo
= &dummy_opcode
;
2419 /* It looks like we can actually do the swap. */
2420 if (! mips_opts
.mips16
)
2425 prev_f
= prev_insn_frag
->fr_literal
+ prev_insn_where
;
2426 memcpy (temp
, prev_f
, 4);
2427 memcpy (prev_f
, f
, 4);
2428 memcpy (f
, temp
, 4);
2429 if (prev_insn_fixp
[0])
2431 prev_insn_fixp
[0]->fx_frag
= frag_now
;
2432 prev_insn_fixp
[0]->fx_where
= f
- frag_now
->fr_literal
;
2434 if (prev_insn_fixp
[1])
2436 prev_insn_fixp
[1]->fx_frag
= frag_now
;
2437 prev_insn_fixp
[1]->fx_where
= f
- frag_now
->fr_literal
;
2439 if (prev_insn_fixp
[2])
2441 prev_insn_fixp
[2]->fx_frag
= frag_now
;
2442 prev_insn_fixp
[2]->fx_where
= f
- frag_now
->fr_literal
;
2446 fixp
[0]->fx_frag
= prev_insn_frag
;
2447 fixp
[0]->fx_where
= prev_insn_where
;
2451 fixp
[1]->fx_frag
= prev_insn_frag
;
2452 fixp
[1]->fx_where
= prev_insn_where
;
2456 fixp
[2]->fx_frag
= prev_insn_frag
;
2457 fixp
[2]->fx_where
= prev_insn_where
;
2465 assert (prev_insn_fixp
[0] == NULL
);
2466 assert (prev_insn_fixp
[1] == NULL
);
2467 assert (prev_insn_fixp
[2] == NULL
);
2468 prev_f
= prev_insn_frag
->fr_literal
+ prev_insn_where
;
2469 memcpy (temp
, prev_f
, 2);
2470 memcpy (prev_f
, f
, 2);
2471 if (*reloc_type
!= BFD_RELOC_MIPS16_JMP
)
2473 assert (*reloc_type
== BFD_RELOC_UNUSED
);
2474 memcpy (f
, temp
, 2);
2478 memcpy (f
, f
+ 2, 2);
2479 memcpy (f
+ 2, temp
, 2);
2483 fixp
[0]->fx_frag
= prev_insn_frag
;
2484 fixp
[0]->fx_where
= prev_insn_where
;
2488 fixp
[1]->fx_frag
= prev_insn_frag
;
2489 fixp
[1]->fx_where
= prev_insn_where
;
2493 fixp
[2]->fx_frag
= prev_insn_frag
;
2494 fixp
[2]->fx_where
= prev_insn_where
;
2498 /* Update the previous insn information; leave prev_insn
2500 prev_prev_insn
= *ip
;
2502 prev_insn_is_delay_slot
= 1;
2504 /* If that was an unconditional branch, forget the previous
2505 insn information. */
2506 if (pinfo
& INSN_UNCOND_BRANCH_DELAY
)
2508 prev_prev_insn
.insn_mo
= &dummy_opcode
;
2509 prev_insn
.insn_mo
= &dummy_opcode
;
2512 prev_insn_fixp
[0] = NULL
;
2513 prev_insn_fixp
[1] = NULL
;
2514 prev_insn_fixp
[2] = NULL
;
2515 prev_insn_reloc_type
[0] = BFD_RELOC_UNUSED
;
2516 prev_insn_reloc_type
[1] = BFD_RELOC_UNUSED
;
2517 prev_insn_reloc_type
[2] = BFD_RELOC_UNUSED
;
2518 prev_insn_extended
= 0;
2520 else if (pinfo
& INSN_COND_BRANCH_LIKELY
)
2522 /* We don't yet optimize a branch likely. What we should do
2523 is look at the target, copy the instruction found there
2524 into the delay slot, and increment the branch to jump to
2525 the next instruction. */
2527 /* Update the previous insn information. */
2528 prev_prev_insn
= *ip
;
2529 prev_insn
.insn_mo
= &dummy_opcode
;
2530 prev_insn_fixp
[0] = NULL
;
2531 prev_insn_fixp
[1] = NULL
;
2532 prev_insn_fixp
[2] = NULL
;
2533 prev_insn_reloc_type
[0] = BFD_RELOC_UNUSED
;
2534 prev_insn_reloc_type
[1] = BFD_RELOC_UNUSED
;
2535 prev_insn_reloc_type
[2] = BFD_RELOC_UNUSED
;
2536 prev_insn_extended
= 0;
2540 /* Update the previous insn information. */
2542 prev_prev_insn
.insn_mo
= &dummy_opcode
;
2544 prev_prev_insn
= prev_insn
;
2547 /* Any time we see a branch, we always fill the delay slot
2548 immediately; since this insn is not a branch, we know it
2549 is not in a delay slot. */
2550 prev_insn_is_delay_slot
= 0;
2552 prev_insn_fixp
[0] = fixp
[0];
2553 prev_insn_fixp
[1] = fixp
[1];
2554 prev_insn_fixp
[2] = fixp
[2];
2555 prev_insn_reloc_type
[0] = reloc_type
[0];
2556 prev_insn_reloc_type
[1] = reloc_type
[1];
2557 prev_insn_reloc_type
[2] = reloc_type
[2];
2558 if (mips_opts
.mips16
)
2559 prev_insn_extended
= (ip
->use_extend
2560 || *reloc_type
> BFD_RELOC_UNUSED
);
2563 prev_prev_insn_unreordered
= prev_insn_unreordered
;
2564 prev_insn_unreordered
= 0;
2565 prev_insn_frag
= frag_now
;
2566 prev_insn_where
= f
- frag_now
->fr_literal
;
2567 prev_insn_valid
= 1;
2569 else if (place
== NULL
)
2571 /* We need to record a bit of information even when we are not
2572 reordering, in order to determine the base address for mips16
2573 PC relative relocs. */
2574 prev_prev_insn
= prev_insn
;
2576 prev_insn_reloc_type
[0] = reloc_type
[0];
2577 prev_insn_reloc_type
[1] = reloc_type
[1];
2578 prev_insn_reloc_type
[2] = reloc_type
[2];
2579 prev_prev_insn_unreordered
= prev_insn_unreordered
;
2580 prev_insn_unreordered
= 1;
2583 /* We just output an insn, so the next one doesn't have a label. */
2584 mips_clear_insn_labels ();
2586 /* We must ensure that a fixup associated with an unmatched %hi
2587 reloc does not become a variant frag. Otherwise, the
2588 rearrangement of %hi relocs in frob_file may confuse
2592 frag_wane (frag_now
);
2597 /* This function forgets that there was any previous instruction or
2598 label. If PRESERVE is non-zero, it remembers enough information to
2599 know whether nops are needed before a noreorder section. */
2602 mips_no_prev_insn (preserve
)
2607 prev_insn
.insn_mo
= &dummy_opcode
;
2608 prev_prev_insn
.insn_mo
= &dummy_opcode
;
2609 prev_nop_frag
= NULL
;
2610 prev_nop_frag_holds
= 0;
2611 prev_nop_frag_required
= 0;
2612 prev_nop_frag_since
= 0;
2614 prev_insn_valid
= 0;
2615 prev_insn_is_delay_slot
= 0;
2616 prev_insn_unreordered
= 0;
2617 prev_insn_extended
= 0;
2618 prev_insn_reloc_type
[0] = BFD_RELOC_UNUSED
;
2619 prev_insn_reloc_type
[1] = BFD_RELOC_UNUSED
;
2620 prev_insn_reloc_type
[2] = BFD_RELOC_UNUSED
;
2621 prev_prev_insn_unreordered
= 0;
2622 mips_clear_insn_labels ();
2625 /* This function must be called whenever we turn on noreorder or emit
2626 something other than instructions. It inserts any NOPS which might
2627 be needed by the previous instruction, and clears the information
2628 kept for the previous instructions. The INSNS parameter is true if
2629 instructions are to follow. */
2632 mips_emit_delays (insns
)
2635 if (! mips_opts
.noreorder
)
2640 if ((! mips_opts
.mips16
2641 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
2642 && (! cop_interlocks
2643 && (prev_insn
.insn_mo
->pinfo
2644 & (INSN_LOAD_COPROC_DELAY
2645 | INSN_COPROC_MOVE_DELAY
2646 | INSN_WRITE_COND_CODE
))))
2647 || (! hilo_interlocks
2648 && (prev_insn
.insn_mo
->pinfo
2651 || (! mips_opts
.mips16
2653 && (prev_insn
.insn_mo
->pinfo
2654 & INSN_LOAD_MEMORY_DELAY
))
2655 || (! mips_opts
.mips16
2656 && mips_opts
.isa
== ISA_MIPS1
2657 && (prev_insn
.insn_mo
->pinfo
2658 & INSN_COPROC_MEMORY_DELAY
)))
2660 /* Itbl support may require additional care here. */
2662 if ((! mips_opts
.mips16
2663 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
2664 && (! cop_interlocks
2665 && prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
))
2666 || (! hilo_interlocks
2667 && ((prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
2668 || (prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
))))
2671 if (prev_insn_unreordered
)
2674 else if ((! mips_opts
.mips16
2675 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
2676 && (! cop_interlocks
2677 && prev_prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
))
2678 || (! hilo_interlocks
2679 && ((prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
2680 || (prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
))))
2682 /* Itbl support may require additional care here. */
2683 if (! prev_prev_insn_unreordered
)
2689 struct insn_label_list
*l
;
2693 /* Record the frag which holds the nop instructions, so
2694 that we can remove them if we don't need them. */
2695 frag_grow (mips_opts
.mips16
? nops
* 2 : nops
* 4);
2696 prev_nop_frag
= frag_now
;
2697 prev_nop_frag_holds
= nops
;
2698 prev_nop_frag_required
= 0;
2699 prev_nop_frag_since
= 0;
2702 for (; nops
> 0; --nops
)
2707 /* Move on to a new frag, so that it is safe to simply
2708 decrease the size of prev_nop_frag. */
2709 frag_wane (frag_now
);
2713 for (l
= insn_labels
; l
!= NULL
; l
= l
->next
)
2717 assert (S_GET_SEGMENT (l
->label
) == now_seg
);
2718 symbol_set_frag (l
->label
, frag_now
);
2719 val
= (valueT
) frag_now_fix ();
2720 /* mips16 text labels are stored as odd. */
2721 if (mips_opts
.mips16
)
2723 S_SET_VALUE (l
->label
, val
);
2728 /* Mark instruction labels in mips16 mode. */
2729 if (mips_opts
.mips16
&& insns
)
2730 mips16_mark_labels ();
2732 mips_no_prev_insn (insns
);
2735 /* Build an instruction created by a macro expansion. This is passed
2736 a pointer to the count of instructions created so far, an
2737 expression, the name of the instruction to build, an operand format
2738 string, and corresponding arguments. */
2742 macro_build (char *place
,
2750 macro_build (place
, counter
, ep
, name
, fmt
, va_alist
)
2759 struct mips_cl_insn insn
;
2760 bfd_reloc_code_real_type r
[3];
2764 va_start (args
, fmt
);
2770 * If the macro is about to expand into a second instruction,
2771 * print a warning if needed. We need to pass ip as a parameter
2772 * to generate a better warning message here...
2774 if (mips_opts
.warn_about_macros
&& place
== NULL
&& *counter
== 1)
2775 as_warn (_("Macro instruction expanded into multiple instructions"));
2778 *counter
+= 1; /* bump instruction counter */
2780 if (mips_opts
.mips16
)
2782 mips16_macro_build (place
, counter
, ep
, name
, fmt
, args
);
2787 r
[0] = BFD_RELOC_UNUSED
;
2788 r
[1] = BFD_RELOC_UNUSED
;
2789 r
[2] = BFD_RELOC_UNUSED
;
2790 insn
.insn_mo
= (struct mips_opcode
*) hash_find (op_hash
, name
);
2791 assert (insn
.insn_mo
);
2792 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
2794 /* Search until we get a match for NAME. */
2797 if (strcmp (fmt
, insn
.insn_mo
->args
) == 0
2798 && insn
.insn_mo
->pinfo
!= INSN_MACRO
2799 && OPCODE_IS_MEMBER (insn
.insn_mo
, mips_opts
.isa
, mips_arch
)
2800 && (mips_arch
!= CPU_R4650
|| (insn
.insn_mo
->pinfo
& FP_D
) == 0))
2804 assert (insn
.insn_mo
->name
);
2805 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
2808 insn
.insn_opcode
= insn
.insn_mo
->match
;
2824 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_RT
;
2828 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_CODE
;
2833 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_FT
;
2838 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_RD
;
2843 int tmp
= va_arg (args
, int);
2845 insn
.insn_opcode
|= tmp
<< OP_SH_RT
;
2846 insn
.insn_opcode
|= tmp
<< OP_SH_RD
;
2852 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_FS
;
2859 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_SHAMT
;
2863 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_FD
;
2867 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_CODE20
;
2871 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_CODE19
;
2875 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_CODE2
;
2882 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_RS
;
2888 *r
= (bfd_reloc_code_real_type
) va_arg (args
, int);
2889 assert (*r
== BFD_RELOC_GPREL16
2890 || *r
== BFD_RELOC_MIPS_LITERAL
2891 || *r
== BFD_RELOC_MIPS_HIGHER
2892 || *r
== BFD_RELOC_HI16_S
2893 || *r
== BFD_RELOC_LO16
2894 || *r
== BFD_RELOC_MIPS_GOT16
2895 || *r
== BFD_RELOC_MIPS_CALL16
2896 || *r
== BFD_RELOC_MIPS_GOT_LO16
2897 || *r
== BFD_RELOC_MIPS_CALL_LO16
2898 || (ep
->X_op
== O_subtract
2899 && *r
== BFD_RELOC_PCREL_LO16
));
2903 *r
= (bfd_reloc_code_real_type
) va_arg (args
, int);
2905 && (ep
->X_op
== O_constant
2906 || (ep
->X_op
== O_symbol
2907 && (*r
== BFD_RELOC_MIPS_HIGHEST
2908 || *r
== BFD_RELOC_HI16_S
2909 || *r
== BFD_RELOC_HI16
2910 || *r
== BFD_RELOC_GPREL16
2911 || *r
== BFD_RELOC_MIPS_GOT_HI16
2912 || *r
== BFD_RELOC_MIPS_CALL_HI16
))
2913 || (ep
->X_op
== O_subtract
2914 && *r
== BFD_RELOC_PCREL_HI16_S
)));
2918 assert (ep
!= NULL
);
2920 * This allows macro() to pass an immediate expression for
2921 * creating short branches without creating a symbol.
2922 * Note that the expression still might come from the assembly
2923 * input, in which case the value is not checked for range nor
2924 * is a relocation entry generated (yuck).
2926 if (ep
->X_op
== O_constant
)
2928 insn
.insn_opcode
|= (ep
->X_add_number
>> 2) & 0xffff;
2932 if (mips_pic
== EMBEDDED_PIC
)
2933 *r
= BFD_RELOC_16_PCREL_S2
;
2935 *r
= BFD_RELOC_16_PCREL
;
2939 assert (ep
!= NULL
);
2940 *r
= BFD_RELOC_MIPS_JMP
;
2944 insn
.insn_opcode
|= va_arg (args
, unsigned long);
2953 assert (*r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
2955 append_insn (place
, &insn
, ep
, r
, false);
2959 mips16_macro_build (place
, counter
, ep
, name
, fmt
, args
)
2961 int *counter ATTRIBUTE_UNUSED
;
2967 struct mips_cl_insn insn
;
2968 bfd_reloc_code_real_type r
[3]
2969 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
2971 insn
.insn_mo
= (struct mips_opcode
*) hash_find (mips16_op_hash
, name
);
2972 assert (insn
.insn_mo
);
2973 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
2975 while (strcmp (fmt
, insn
.insn_mo
->args
) != 0
2976 || insn
.insn_mo
->pinfo
== INSN_MACRO
)
2979 assert (insn
.insn_mo
->name
);
2980 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
2983 insn
.insn_opcode
= insn
.insn_mo
->match
;
2984 insn
.use_extend
= false;
3003 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_RY
;
3008 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_RX
;
3012 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_RZ
;
3016 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_MOVE32Z
;
3026 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_REGR32
;
3033 regno
= va_arg (args
, int);
3034 regno
= ((regno
& 7) << 2) | ((regno
& 0x18) >> 3);
3035 insn
.insn_opcode
|= regno
<< MIPS16OP_SH_REG32R
;
3056 assert (ep
!= NULL
);
3058 if (ep
->X_op
!= O_constant
)
3059 *r
= BFD_RELOC_UNUSED
+ c
;
3062 mips16_immed (NULL
, 0, c
, ep
->X_add_number
, false, false,
3063 false, &insn
.insn_opcode
, &insn
.use_extend
,
3066 *r
= BFD_RELOC_UNUSED
;
3072 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_IMM6
;
3079 assert (*r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
3081 append_insn (place
, &insn
, ep
, r
, false);
3085 * Generate a "lui" instruction.
3088 macro_build_lui (place
, counter
, ep
, regnum
)
3094 expressionS high_expr
;
3095 struct mips_cl_insn insn
;
3096 bfd_reloc_code_real_type r
[3]
3097 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
3098 CONST
char *name
= "lui";
3099 CONST
char *fmt
= "t,u";
3101 assert (! mips_opts
.mips16
);
3107 high_expr
.X_op
= O_constant
;
3108 high_expr
.X_add_number
= ep
->X_add_number
;
3111 if (high_expr
.X_op
== O_constant
)
3113 /* we can compute the instruction now without a relocation entry */
3114 high_expr
.X_add_number
= ((high_expr
.X_add_number
+ 0x8000)
3116 *r
= BFD_RELOC_UNUSED
;
3118 else if (! HAVE_NEWABI
)
3120 assert (ep
->X_op
== O_symbol
);
3121 /* _gp_disp is a special case, used from s_cpload. */
3122 assert (mips_pic
== NO_PIC
3123 || strcmp (S_GET_NAME (ep
->X_add_symbol
), "_gp_disp") == 0);
3124 *r
= BFD_RELOC_HI16_S
;
3128 * If the macro is about to expand into a second instruction,
3129 * print a warning if needed. We need to pass ip as a parameter
3130 * to generate a better warning message here...
3132 if (mips_opts
.warn_about_macros
&& place
== NULL
&& *counter
== 1)
3133 as_warn (_("Macro instruction expanded into multiple instructions"));
3136 *counter
+= 1; /* bump instruction counter */
3138 insn
.insn_mo
= (struct mips_opcode
*) hash_find (op_hash
, name
);
3139 assert (insn
.insn_mo
);
3140 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
3141 assert (strcmp (fmt
, insn
.insn_mo
->args
) == 0);
3143 insn
.insn_opcode
= insn
.insn_mo
->match
| (regnum
<< OP_SH_RT
);
3144 if (*r
== BFD_RELOC_UNUSED
)
3146 insn
.insn_opcode
|= high_expr
.X_add_number
;
3147 append_insn (place
, &insn
, NULL
, r
, false);
3150 append_insn (place
, &insn
, &high_expr
, r
, false);
3154 * Generates code to set the $at register to true (one)
3155 * if reg is less than the immediate expression.
3158 set_at (counter
, reg
, unsignedp
)
3163 if (imm_expr
.X_op
== O_constant
3164 && imm_expr
.X_add_number
>= -0x8000
3165 && imm_expr
.X_add_number
< 0x8000)
3166 macro_build ((char *) NULL
, counter
, &imm_expr
,
3167 unsignedp
? "sltiu" : "slti",
3168 "t,r,j", AT
, reg
, (int) BFD_RELOC_LO16
);
3171 load_register (counter
, AT
, &imm_expr
, 0);
3172 macro_build ((char *) NULL
, counter
, (expressionS
*) NULL
,
3173 unsignedp
? "sltu" : "slt",
3174 "d,v,t", AT
, reg
, AT
);
3178 /* Warn if an expression is not a constant. */
3181 check_absolute_expr (ip
, ex
)
3182 struct mips_cl_insn
*ip
;
3185 if (ex
->X_op
== O_big
)
3186 as_bad (_("unsupported large constant"));
3187 else if (ex
->X_op
!= O_constant
)
3188 as_bad (_("Instruction %s requires absolute expression"), ip
->insn_mo
->name
);
3191 /* Count the leading zeroes by performing a binary chop. This is a
3192 bulky bit of source, but performance is a LOT better for the
3193 majority of values than a simple loop to count the bits:
3194 for (lcnt = 0; (lcnt < 32); lcnt++)
3195 if ((v) & (1 << (31 - lcnt)))
3197 However it is not code size friendly, and the gain will drop a bit
3198 on certain cached systems.
3200 #define COUNT_TOP_ZEROES(v) \
3201 (((v) & ~0xffff) == 0 \
3202 ? ((v) & ~0xff) == 0 \
3203 ? ((v) & ~0xf) == 0 \
3204 ? ((v) & ~0x3) == 0 \
3205 ? ((v) & ~0x1) == 0 \
3210 : ((v) & ~0x7) == 0 \
3213 : ((v) & ~0x3f) == 0 \
3214 ? ((v) & ~0x1f) == 0 \
3217 : ((v) & ~0x7f) == 0 \
3220 : ((v) & ~0xfff) == 0 \
3221 ? ((v) & ~0x3ff) == 0 \
3222 ? ((v) & ~0x1ff) == 0 \
3225 : ((v) & ~0x7ff) == 0 \
3228 : ((v) & ~0x3fff) == 0 \
3229 ? ((v) & ~0x1fff) == 0 \
3232 : ((v) & ~0x7fff) == 0 \
3235 : ((v) & ~0xffffff) == 0 \
3236 ? ((v) & ~0xfffff) == 0 \
3237 ? ((v) & ~0x3ffff) == 0 \
3238 ? ((v) & ~0x1ffff) == 0 \
3241 : ((v) & ~0x7ffff) == 0 \
3244 : ((v) & ~0x3fffff) == 0 \
3245 ? ((v) & ~0x1fffff) == 0 \
3248 : ((v) & ~0x7fffff) == 0 \
3251 : ((v) & ~0xfffffff) == 0 \
3252 ? ((v) & ~0x3ffffff) == 0 \
3253 ? ((v) & ~0x1ffffff) == 0 \
3256 : ((v) & ~0x7ffffff) == 0 \
3259 : ((v) & ~0x3fffffff) == 0 \
3260 ? ((v) & ~0x1fffffff) == 0 \
3263 : ((v) & ~0x7fffffff) == 0 \
3268 * This routine generates the least number of instructions neccessary to load
3269 * an absolute expression value into a register.
3272 load_register (counter
, reg
, ep
, dbl
)
3279 expressionS hi32
, lo32
;
3281 if (ep
->X_op
!= O_big
)
3283 assert (ep
->X_op
== O_constant
);
3284 if (ep
->X_add_number
< 0x8000
3285 && (ep
->X_add_number
>= 0
3286 || (ep
->X_add_number
>= -0x8000
3289 || sizeof (ep
->X_add_number
) > 4))))
3291 /* We can handle 16 bit signed values with an addiu to
3292 $zero. No need to ever use daddiu here, since $zero and
3293 the result are always correct in 32 bit mode. */
3294 macro_build ((char *) NULL
, counter
, ep
, "addiu", "t,r,j", reg
, 0,
3295 (int) BFD_RELOC_LO16
);
3298 else if (ep
->X_add_number
>= 0 && ep
->X_add_number
< 0x10000)
3300 /* We can handle 16 bit unsigned values with an ori to
3302 macro_build ((char *) NULL
, counter
, ep
, "ori", "t,r,i", reg
, 0,
3303 (int) BFD_RELOC_LO16
);
3306 else if ((((ep
->X_add_number
&~ (offsetT
) 0x7fffffff) == 0
3307 || ((ep
->X_add_number
&~ (offsetT
) 0x7fffffff)
3308 == ~ (offsetT
) 0x7fffffff))
3311 || sizeof (ep
->X_add_number
) > 4
3312 || (ep
->X_add_number
& 0x80000000) == 0))
3313 || ((HAVE_32BIT_GPRS
|| ! dbl
)
3314 && (ep
->X_add_number
&~ (offsetT
) 0xffffffff) == 0)
3317 && ((ep
->X_add_number
&~ (offsetT
) 0xffffffff)
3318 == ~ (offsetT
) 0xffffffff)))
3320 /* 32 bit values require an lui. */
3321 macro_build ((char *) NULL
, counter
, ep
, "lui", "t,u", reg
,
3322 (int) BFD_RELOC_HI16
);
3323 if ((ep
->X_add_number
& 0xffff) != 0)
3324 macro_build ((char *) NULL
, counter
, ep
, "ori", "t,r,i", reg
, reg
,
3325 (int) BFD_RELOC_LO16
);
3330 /* The value is larger than 32 bits. */
3332 if (HAVE_32BIT_GPRS
)
3334 as_bad (_("Number larger than 32 bits"));
3335 macro_build ((char *) NULL
, counter
, ep
, "addiu", "t,r,j", reg
, 0,
3336 (int) BFD_RELOC_LO16
);
3340 if (ep
->X_op
!= O_big
)
3343 hi32
.X_add_number
= (valueT
) hi32
.X_add_number
>> 16;
3344 hi32
.X_add_number
= (valueT
) hi32
.X_add_number
>> 16;
3345 hi32
.X_add_number
&= 0xffffffff;
3347 lo32
.X_add_number
&= 0xffffffff;
3351 assert (ep
->X_add_number
> 2);
3352 if (ep
->X_add_number
== 3)
3353 generic_bignum
[3] = 0;
3354 else if (ep
->X_add_number
> 4)
3355 as_bad (_("Number larger than 64 bits"));
3356 lo32
.X_op
= O_constant
;
3357 lo32
.X_add_number
= generic_bignum
[0] + (generic_bignum
[1] << 16);
3358 hi32
.X_op
= O_constant
;
3359 hi32
.X_add_number
= generic_bignum
[2] + (generic_bignum
[3] << 16);
3362 if (hi32
.X_add_number
== 0)
3367 unsigned long hi
, lo
;
3369 if (hi32
.X_add_number
== 0xffffffff)
3371 if ((lo32
.X_add_number
& 0xffff8000) == 0xffff8000)
3373 macro_build ((char *) NULL
, counter
, &lo32
, "addiu", "t,r,j",
3374 reg
, 0, (int) BFD_RELOC_LO16
);
3377 if (lo32
.X_add_number
& 0x80000000)
3379 macro_build ((char *) NULL
, counter
, &lo32
, "lui", "t,u", reg
,
3380 (int) BFD_RELOC_HI16
);
3381 if (lo32
.X_add_number
& 0xffff)
3382 macro_build ((char *) NULL
, counter
, &lo32
, "ori", "t,r,i",
3383 reg
, reg
, (int) BFD_RELOC_LO16
);
3388 /* Check for 16bit shifted constant. We know that hi32 is
3389 non-zero, so start the mask on the first bit of the hi32
3394 unsigned long himask
, lomask
;
3398 himask
= 0xffff >> (32 - shift
);
3399 lomask
= (0xffff << shift
) & 0xffffffff;
3403 himask
= 0xffff << (shift
- 32);
3406 if ((hi32
.X_add_number
& ~(offsetT
) himask
) == 0
3407 && (lo32
.X_add_number
& ~(offsetT
) lomask
) == 0)
3411 tmp
.X_op
= O_constant
;
3413 tmp
.X_add_number
= ((hi32
.X_add_number
<< (32 - shift
))
3414 | (lo32
.X_add_number
>> shift
));
3416 tmp
.X_add_number
= hi32
.X_add_number
>> (shift
- 32);
3417 macro_build ((char *) NULL
, counter
, &tmp
,
3418 "ori", "t,r,i", reg
, 0,
3419 (int) BFD_RELOC_LO16
);
3420 macro_build ((char *) NULL
, counter
, (expressionS
*) NULL
,
3421 (shift
>= 32) ? "dsll32" : "dsll",
3423 (shift
>= 32) ? shift
- 32 : shift
);
3428 while (shift
<= (64 - 16));
3430 /* Find the bit number of the lowest one bit, and store the
3431 shifted value in hi/lo. */
3432 hi
= (unsigned long) (hi32
.X_add_number
& 0xffffffff);
3433 lo
= (unsigned long) (lo32
.X_add_number
& 0xffffffff);
3437 while ((lo
& 1) == 0)
3442 lo
|= (hi
& (((unsigned long) 1 << bit
) - 1)) << (32 - bit
);
3448 while ((hi
& 1) == 0)
3457 /* Optimize if the shifted value is a (power of 2) - 1. */
3458 if ((hi
== 0 && ((lo
+ 1) & lo
) == 0)
3459 || (lo
== 0xffffffff && ((hi
+ 1) & hi
) == 0))
3461 shift
= COUNT_TOP_ZEROES ((unsigned int) hi32
.X_add_number
);
3466 /* This instruction will set the register to be all
3468 tmp
.X_op
= O_constant
;
3469 tmp
.X_add_number
= (offsetT
) -1;
3470 macro_build ((char *) NULL
, counter
, &tmp
, "addiu", "t,r,j",
3471 reg
, 0, (int) BFD_RELOC_LO16
);
3475 macro_build ((char *) NULL
, counter
, (expressionS
*) NULL
,
3476 (bit
>= 32) ? "dsll32" : "dsll",
3478 (bit
>= 32) ? bit
- 32 : bit
);
3480 macro_build ((char *) NULL
, counter
, (expressionS
*) NULL
,
3481 (shift
>= 32) ? "dsrl32" : "dsrl",
3483 (shift
>= 32) ? shift
- 32 : shift
);
3488 /* Sign extend hi32 before calling load_register, because we can
3489 generally get better code when we load a sign extended value. */
3490 if ((hi32
.X_add_number
& 0x80000000) != 0)
3491 hi32
.X_add_number
|= ~(offsetT
) 0xffffffff;
3492 load_register (counter
, reg
, &hi32
, 0);
3495 if ((lo32
.X_add_number
& 0xffff0000) == 0)
3499 macro_build ((char *) NULL
, counter
, (expressionS
*) NULL
,
3500 "dsll32", "d,w,<", reg
, freg
, 0);
3508 if ((freg
== 0) && (lo32
.X_add_number
== 0xffffffff))
3510 macro_build ((char *) NULL
, counter
, &lo32
, "lui", "t,u", reg
,
3511 (int) BFD_RELOC_HI16
);
3512 macro_build ((char *) NULL
, counter
, NULL
, "dsrl32", "d,w,<", reg
,
3519 macro_build ((char *) NULL
, counter
, NULL
, "dsll", "d,w,<", reg
,
3524 mid16
.X_add_number
>>= 16;
3525 macro_build ((char *) NULL
, counter
, &mid16
, "ori", "t,r,i", reg
,
3526 freg
, (int) BFD_RELOC_LO16
);
3527 macro_build ((char *) NULL
, counter
, NULL
, "dsll", "d,w,<", reg
,
3531 if ((lo32
.X_add_number
& 0xffff) != 0)
3532 macro_build ((char *) NULL
, counter
, &lo32
, "ori", "t,r,i", reg
, freg
,
3533 (int) BFD_RELOC_LO16
);
3536 /* Load an address into a register. */
3539 load_address (counter
, reg
, ep
, dbl
, used_at
)
3548 if (ep
->X_op
!= O_constant
3549 && ep
->X_op
!= O_symbol
)
3551 as_bad (_("expression too complex"));
3552 ep
->X_op
= O_constant
;
3555 if (ep
->X_op
== O_constant
)
3557 load_register (counter
, reg
, ep
, dbl
);
3561 if (mips_pic
== NO_PIC
)
3563 /* If this is a reference to a GP relative symbol, we want
3564 addiu $reg,$gp,<sym> (BFD_RELOC_GPREL16)
3566 lui $reg,<sym> (BFD_RELOC_HI16_S)
3567 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
3568 If we have an addend, we always use the latter form.
3570 With 64bit address space and a usable $at we want
3571 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
3572 lui $at,<sym> (BFD_RELOC_HI16_S)
3573 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
3574 daddiu $at,<sym> (BFD_RELOC_LO16)
3578 If $at is already in use, we use an path which is suboptimal
3579 on superscalar processors.
3580 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
3581 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
3583 daddiu $reg,<sym> (BFD_RELOC_HI16_S)
3585 daddiu $reg,<sym> (BFD_RELOC_LO16)
3587 if (HAVE_64BIT_ADDRESSES
)
3591 /* We don't do GP optimization for now because RELAX_ENCODE can't
3592 hold the data for such large chunks. */
3596 macro_build (p
, counter
, ep
, "lui", "t,u",
3597 reg
, (int) BFD_RELOC_MIPS_HIGHEST
);
3598 macro_build (p
, counter
, ep
, "lui", "t,u",
3599 AT
, (int) BFD_RELOC_HI16_S
);
3600 macro_build (p
, counter
, ep
, "daddiu", "t,r,j",
3601 reg
, reg
, (int) BFD_RELOC_MIPS_HIGHER
);
3602 macro_build (p
, counter
, ep
, "daddiu", "t,r,j",
3603 AT
, AT
, (int) BFD_RELOC_LO16
);
3604 macro_build (p
, counter
, (expressionS
*) NULL
, "dsll32",
3605 "d,w,<", reg
, reg
, 0);
3606 macro_build (p
, counter
, (expressionS
*) NULL
, "dadd",
3607 "d,v,t", reg
, reg
, AT
);
3612 macro_build (p
, counter
, ep
, "lui", "t,u",
3613 reg
, (int) BFD_RELOC_MIPS_HIGHEST
);
3614 macro_build (p
, counter
, ep
, "daddiu", "t,r,j",
3615 reg
, reg
, (int) BFD_RELOC_MIPS_HIGHER
);
3616 macro_build (p
, counter
, (expressionS
*) NULL
, "dsll",
3617 "d,w,<", reg
, reg
, 16);
3618 macro_build (p
, counter
, ep
, "daddiu", "t,r,j",
3619 reg
, reg
, (int) BFD_RELOC_HI16_S
);
3620 macro_build (p
, counter
, (expressionS
*) NULL
, "dsll",
3621 "d,w,<", reg
, reg
, 16);
3622 macro_build (p
, counter
, ep
, "daddiu", "t,r,j",
3623 reg
, reg
, (int) BFD_RELOC_LO16
);
3629 if ((valueT
) ep
->X_add_number
<= MAX_GPREL_OFFSET
3630 && ! nopic_need_relax (ep
->X_add_symbol
, 1))
3633 macro_build ((char *) NULL
, counter
, ep
,
3634 dbl
? "daddiu" : "addiu", "t,r,j", reg
, GP
,
3635 (int) BFD_RELOC_GPREL16
);
3636 p
= frag_var (rs_machine_dependent
, 8, 0,
3637 RELAX_ENCODE (4, 8, 0, 4, 0,
3638 mips_opts
.warn_about_macros
),
3639 ep
->X_add_symbol
, (offsetT
) 0, (char *) NULL
);
3641 macro_build_lui (p
, counter
, ep
, reg
);
3644 macro_build (p
, counter
, ep
,
3645 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
3646 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
3649 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
3653 /* If this is a reference to an external symbol, we want
3654 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3656 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3658 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
3659 If there is a constant, it must be added in after. */
3660 ex
.X_add_number
= ep
->X_add_number
;
3661 ep
->X_add_number
= 0;
3663 macro_build ((char *) NULL
, counter
, ep
,
3664 HAVE_32BIT_ADDRESSES
? "lw" : "ld",
3665 "t,o(b)", reg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
3666 macro_build ((char *) NULL
, counter
, (expressionS
*) NULL
, "nop", "");
3667 p
= frag_var (rs_machine_dependent
, 4, 0,
3668 RELAX_ENCODE (0, 4, -8, 0, 0, mips_opts
.warn_about_macros
),
3669 ep
->X_add_symbol
, (offsetT
) 0, (char *) NULL
);
3670 macro_build (p
, counter
, ep
,
3671 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
3672 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
3673 if (ex
.X_add_number
!= 0)
3675 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
3676 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
3677 ex
.X_op
= O_constant
;
3678 macro_build ((char *) NULL
, counter
, &ex
,
3679 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
3680 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
3683 else if (mips_pic
== SVR4_PIC
)
3688 /* This is the large GOT case. If this is a reference to an
3689 external symbol, we want
3690 lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
3692 lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16)
3693 Otherwise, for a reference to a local symbol, we want
3694 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3696 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
3697 If there is a constant, it must be added in after. */
3698 ex
.X_add_number
= ep
->X_add_number
;
3699 ep
->X_add_number
= 0;
3700 if (reg_needs_delay (GP
))
3705 macro_build ((char *) NULL
, counter
, ep
, "lui", "t,u", reg
,
3706 (int) BFD_RELOC_MIPS_GOT_HI16
);
3707 macro_build ((char *) NULL
, counter
, (expressionS
*) NULL
,
3708 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
3709 "d,v,t", reg
, reg
, GP
);
3710 macro_build ((char *) NULL
, counter
, ep
,
3711 HAVE_32BIT_ADDRESSES
? "lw" : "ld",
3712 "t,o(b)", reg
, (int) BFD_RELOC_MIPS_GOT_LO16
, reg
);
3713 p
= frag_var (rs_machine_dependent
, 12 + off
, 0,
3714 RELAX_ENCODE (12, 12 + off
, off
, 8 + off
, 0,
3715 mips_opts
.warn_about_macros
),
3716 ep
->X_add_symbol
, (offsetT
) 0, (char *) NULL
);
3719 /* We need a nop before loading from $gp. This special
3720 check is required because the lui which starts the main
3721 instruction stream does not refer to $gp, and so will not
3722 insert the nop which may be required. */
3723 macro_build (p
, counter
, (expressionS
*) NULL
, "nop", "");
3726 macro_build (p
, counter
, ep
, HAVE_32BIT_ADDRESSES
? "lw" : "ld",
3727 "t,o(b)", reg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
3729 macro_build (p
, counter
, (expressionS
*) NULL
, "nop", "");
3731 macro_build (p
, counter
, ep
, HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
3732 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
3733 if (ex
.X_add_number
!= 0)
3735 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
3736 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
3737 ex
.X_op
= O_constant
;
3738 macro_build ((char *) NULL
, counter
, &ex
,
3739 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
3740 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
3743 else if (mips_pic
== EMBEDDED_PIC
)
3746 addiu $reg,$gp,<sym> (BFD_RELOC_GPREL16)
3748 macro_build ((char *) NULL
, counter
, ep
, dbl
? "daddiu" : "addiu",
3749 "t,r,j", reg
, GP
, (int) BFD_RELOC_GPREL16
);
3755 /* Move the contents of register SOURCE into register DEST. */
3758 move_register (counter
, dest
, source
)
3763 macro_build ((char *) NULL
, counter
, (expressionS
*) NULL
,
3764 HAVE_32BIT_GPRS
? "addu" : "daddu",
3765 "d,v,t", dest
, source
, 0);
3770 * This routine implements the seemingly endless macro or synthesized
3771 * instructions and addressing modes in the mips assembly language. Many
3772 * of these macros are simple and are similar to each other. These could
3773 * probably be handled by some kind of table or grammer aproach instead of
3774 * this verbose method. Others are not simple macros but are more like
3775 * optimizing code generation.
3776 * One interesting optimization is when several store macros appear
3777 * consecutivly that would load AT with the upper half of the same address.
3778 * The ensuing load upper instructions are ommited. This implies some kind
3779 * of global optimization. We currently only optimize within a single macro.
3780 * For many of the load and store macros if the address is specified as a
3781 * constant expression in the first 64k of memory (ie ld $2,0x4000c) we
3782 * first load register 'at' with zero and use it as the base register. The
3783 * mips assembler simply uses register $zero. Just one tiny optimization
3788 struct mips_cl_insn
*ip
;
3790 register int treg
, sreg
, dreg
, breg
;
3806 bfd_reloc_code_real_type r
;
3808 int hold_mips_optimize
;
3810 assert (! mips_opts
.mips16
);
3812 treg
= (ip
->insn_opcode
>> 16) & 0x1f;
3813 dreg
= (ip
->insn_opcode
>> 11) & 0x1f;
3814 sreg
= breg
= (ip
->insn_opcode
>> 21) & 0x1f;
3815 mask
= ip
->insn_mo
->mask
;
3817 expr1
.X_op
= O_constant
;
3818 expr1
.X_op_symbol
= NULL
;
3819 expr1
.X_add_symbol
= NULL
;
3820 expr1
.X_add_number
= 1;
3832 mips_emit_delays (true);
3833 ++mips_opts
.noreorder
;
3834 mips_any_noreorder
= 1;
3836 expr1
.X_add_number
= 8;
3837 macro_build ((char *) NULL
, &icnt
, &expr1
, "bgez", "s,p", sreg
);
3839 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "",
3842 move_register (&icnt
, dreg
, sreg
);
3843 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3844 dbl
? "dsub" : "sub", "d,v,t", dreg
, 0, sreg
);
3846 --mips_opts
.noreorder
;
3867 if (imm_expr
.X_op
== O_constant
3868 && imm_expr
.X_add_number
>= -0x8000
3869 && imm_expr
.X_add_number
< 0x8000)
3871 macro_build ((char *) NULL
, &icnt
, &imm_expr
, s
, "t,r,j", treg
, sreg
,
3872 (int) BFD_RELOC_LO16
);
3875 load_register (&icnt
, AT
, &imm_expr
, dbl
);
3876 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s2
, "d,v,t",
3896 if (imm_expr
.X_op
== O_constant
3897 && imm_expr
.X_add_number
>= 0
3898 && imm_expr
.X_add_number
< 0x10000)
3900 if (mask
!= M_NOR_I
)
3901 macro_build ((char *) NULL
, &icnt
, &imm_expr
, s
, "t,r,i", treg
,
3902 sreg
, (int) BFD_RELOC_LO16
);
3905 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "ori", "t,r,i",
3906 treg
, sreg
, (int) BFD_RELOC_LO16
);
3907 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nor",
3908 "d,v,t", treg
, treg
, 0);
3913 load_register (&icnt
, AT
, &imm_expr
, HAVE_64BIT_GPRS
);
3914 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s2
, "d,v,t",
3932 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
3934 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "s,t,p", sreg
,
3938 load_register (&icnt
, AT
, &imm_expr
, 0);
3939 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "s,t,p", sreg
, AT
);
3947 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3948 likely
? "bgezl" : "bgez", "s,p", sreg
);
3953 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3954 likely
? "blezl" : "blez", "s,p", treg
);
3957 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "slt", "d,v,t",
3959 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3960 likely
? "beql" : "beq", "s,t,p", AT
, 0);
3966 /* check for > max integer */
3967 maxnum
= 0x7fffffff;
3968 if (HAVE_64BIT_GPRS
&& sizeof (maxnum
) > 4)
3975 if (imm_expr
.X_op
== O_constant
3976 && imm_expr
.X_add_number
>= maxnum
3977 && (HAVE_32BIT_GPRS
|| sizeof (maxnum
) > 4))
3980 /* result is always false */
3984 as_warn (_("Branch %s is always false (nop)"),
3986 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop",
3992 as_warn (_("Branch likely %s is always false"),
3994 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "bnel",
3999 if (imm_expr
.X_op
!= O_constant
)
4000 as_bad (_("Unsupported large constant"));
4001 imm_expr
.X_add_number
++;
4005 if (mask
== M_BGEL_I
)
4007 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
4009 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4010 likely
? "bgezl" : "bgez", "s,p", sreg
);
4013 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
4015 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4016 likely
? "bgtzl" : "bgtz", "s,p", sreg
);
4019 maxnum
= 0x7fffffff;
4020 if (HAVE_64BIT_GPRS
&& sizeof (maxnum
) > 4)
4027 maxnum
= - maxnum
- 1;
4028 if (imm_expr
.X_op
== O_constant
4029 && imm_expr
.X_add_number
<= maxnum
4030 && (HAVE_32BIT_GPRS
|| sizeof (maxnum
) > 4))
4033 /* result is always true */
4034 as_warn (_("Branch %s is always true"), ip
->insn_mo
->name
);
4035 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "b", "p");
4038 set_at (&icnt
, sreg
, 0);
4039 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4040 likely
? "beql" : "beq", "s,t,p", AT
, 0);
4050 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4051 likely
? "beql" : "beq", "s,t,p", 0, treg
);
4054 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "sltu",
4055 "d,v,t", AT
, sreg
, treg
);
4056 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4057 likely
? "beql" : "beq", "s,t,p", AT
, 0);
4065 && imm_expr
.X_op
== O_constant
4066 && imm_expr
.X_add_number
== 0xffffffff))
4068 if (imm_expr
.X_op
!= O_constant
)
4069 as_bad (_("Unsupported large constant"));
4070 imm_expr
.X_add_number
++;
4074 if (mask
== M_BGEUL_I
)
4076 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
4078 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
4080 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4081 likely
? "bnel" : "bne", "s,t,p", sreg
, 0);
4084 set_at (&icnt
, sreg
, 1);
4085 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4086 likely
? "beql" : "beq", "s,t,p", AT
, 0);
4094 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4095 likely
? "bgtzl" : "bgtz", "s,p", sreg
);
4100 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4101 likely
? "bltzl" : "bltz", "s,p", treg
);
4104 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "slt", "d,v,t",
4106 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4107 likely
? "bnel" : "bne", "s,t,p", AT
, 0);
4115 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4116 likely
? "bnel" : "bne", "s,t,p", sreg
, 0);
4121 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "sltu",
4122 "d,v,t", AT
, treg
, sreg
);
4123 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4124 likely
? "bnel" : "bne", "s,t,p", AT
, 0);
4132 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4133 likely
? "blezl" : "blez", "s,p", sreg
);
4138 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4139 likely
? "bgezl" : "bgez", "s,p", treg
);
4142 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "slt", "d,v,t",
4144 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4145 likely
? "beql" : "beq", "s,t,p", AT
, 0);
4151 maxnum
= 0x7fffffff;
4152 if (HAVE_64BIT_GPRS
&& sizeof (maxnum
) > 4)
4159 if (imm_expr
.X_op
== O_constant
4160 && imm_expr
.X_add_number
>= maxnum
4161 && (HAVE_32BIT_GPRS
|| sizeof (maxnum
) > 4))
4163 if (imm_expr
.X_op
!= O_constant
)
4164 as_bad (_("Unsupported large constant"));
4165 imm_expr
.X_add_number
++;
4169 if (mask
== M_BLTL_I
)
4171 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
4173 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4174 likely
? "bltzl" : "bltz", "s,p", sreg
);
4177 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
4179 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4180 likely
? "blezl" : "blez", "s,p", sreg
);
4183 set_at (&icnt
, sreg
, 0);
4184 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4185 likely
? "bnel" : "bne", "s,t,p", AT
, 0);
4193 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4194 likely
? "beql" : "beq", "s,t,p", sreg
, 0);
4199 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "sltu",
4200 "d,v,t", AT
, treg
, sreg
);
4201 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4202 likely
? "beql" : "beq", "s,t,p", AT
, 0);
4210 && imm_expr
.X_op
== O_constant
4211 && imm_expr
.X_add_number
== 0xffffffff))
4213 if (imm_expr
.X_op
!= O_constant
)
4214 as_bad (_("Unsupported large constant"));
4215 imm_expr
.X_add_number
++;
4219 if (mask
== M_BLTUL_I
)
4221 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
4223 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
4225 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4226 likely
? "beql" : "beq",
4230 set_at (&icnt
, sreg
, 1);
4231 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4232 likely
? "bnel" : "bne", "s,t,p", AT
, 0);
4240 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4241 likely
? "bltzl" : "bltz", "s,p", sreg
);
4246 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4247 likely
? "bgtzl" : "bgtz", "s,p", treg
);
4250 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "slt", "d,v,t",
4252 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4253 likely
? "bnel" : "bne", "s,t,p", AT
, 0);
4263 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4264 likely
? "bnel" : "bne", "s,t,p", 0, treg
);
4267 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "sltu",
4270 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4271 likely
? "bnel" : "bne", "s,t,p", AT
, 0);
4286 as_warn (_("Divide by zero."));
4288 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "teq",
4291 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "break",
4296 mips_emit_delays (true);
4297 ++mips_opts
.noreorder
;
4298 mips_any_noreorder
= 1;
4301 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "teq",
4303 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4304 dbl
? "ddiv" : "div", "z,s,t", sreg
, treg
);
4308 expr1
.X_add_number
= 8;
4309 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", treg
, 0);
4310 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4311 dbl
? "ddiv" : "div", "z,s,t", sreg
, treg
);
4312 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "break",
4315 expr1
.X_add_number
= -1;
4316 macro_build ((char *) NULL
, &icnt
, &expr1
,
4317 dbl
? "daddiu" : "addiu",
4318 "t,r,j", AT
, 0, (int) BFD_RELOC_LO16
);
4319 expr1
.X_add_number
= mips_trap
? (dbl
? 12 : 8) : (dbl
? 20 : 16);
4320 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", treg
, AT
);
4323 expr1
.X_add_number
= 1;
4324 macro_build ((char *) NULL
, &icnt
, &expr1
, "daddiu", "t,r,j", AT
, 0,
4325 (int) BFD_RELOC_LO16
);
4326 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "dsll32",
4327 "d,w,<", AT
, AT
, 31);
4331 expr1
.X_add_number
= 0x80000000;
4332 macro_build ((char *) NULL
, &icnt
, &expr1
, "lui", "t,u", AT
,
4333 (int) BFD_RELOC_HI16
);
4337 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "teq",
4339 /* We want to close the noreorder block as soon as possible, so
4340 that later insns are available for delay slot filling. */
4341 --mips_opts
.noreorder
;
4345 expr1
.X_add_number
= 8;
4346 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", sreg
, AT
);
4347 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "",
4350 /* We want to close the noreorder block as soon as possible, so
4351 that later insns are available for delay slot filling. */
4352 --mips_opts
.noreorder
;
4354 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "break",
4357 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s
, "d", dreg
);
4396 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
4398 as_warn (_("Divide by zero."));
4400 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "teq",
4403 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "break",
4407 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
4409 if (strcmp (s2
, "mflo") == 0)
4410 move_register (&icnt
, dreg
, sreg
);
4412 move_register (&icnt
, dreg
, 0);
4415 if (imm_expr
.X_op
== O_constant
4416 && imm_expr
.X_add_number
== -1
4417 && s
[strlen (s
) - 1] != 'u')
4419 if (strcmp (s2
, "mflo") == 0)
4421 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4422 dbl
? "dneg" : "neg", "d,w", dreg
, sreg
);
4425 move_register (&icnt
, dreg
, 0);
4429 load_register (&icnt
, AT
, &imm_expr
, dbl
);
4430 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s
, "z,s,t",
4432 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s2
, "d", dreg
);
4451 mips_emit_delays (true);
4452 ++mips_opts
.noreorder
;
4453 mips_any_noreorder
= 1;
4456 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "teq",
4458 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s
, "z,s,t",
4460 /* We want to close the noreorder block as soon as possible, so
4461 that later insns are available for delay slot filling. */
4462 --mips_opts
.noreorder
;
4466 expr1
.X_add_number
= 8;
4467 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", treg
, 0);
4468 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s
, "z,s,t",
4471 /* We want to close the noreorder block as soon as possible, so
4472 that later insns are available for delay slot filling. */
4473 --mips_opts
.noreorder
;
4474 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "break",
4477 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s2
, "d", dreg
);
4483 /* Load the address of a symbol into a register. If breg is not
4484 zero, we then add a base register to it. */
4497 /* When generating embedded PIC code, we permit expressions of
4500 la $treg,foo-bar($breg)
4501 where bar is an address in the current section. These are used
4502 when getting the addresses of functions. We don't permit
4503 X_add_number to be non-zero, because if the symbol is
4504 external the relaxing code needs to know that any addend is
4505 purely the offset to X_op_symbol. */
4506 if (mips_pic
== EMBEDDED_PIC
4507 && offset_expr
.X_op
== O_subtract
4508 && (symbol_constant_p (offset_expr
.X_op_symbol
)
4509 ? S_GET_SEGMENT (offset_expr
.X_op_symbol
) == now_seg
4510 : (symbol_equated_p (offset_expr
.X_op_symbol
)
4512 (symbol_get_value_expression (offset_expr
.X_op_symbol
)
4515 && (offset_expr
.X_add_number
== 0
4516 || OUTPUT_FLAVOR
== bfd_target_elf_flavour
))
4522 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
4523 tempreg
, (int) BFD_RELOC_PCREL_HI16_S
);
4527 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
4528 tempreg
, (int) BFD_RELOC_PCREL_HI16_S
);
4529 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4530 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
4531 "d,v,t", tempreg
, tempreg
, breg
);
4533 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4534 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
4535 "t,r,j", treg
, tempreg
, (int) BFD_RELOC_PCREL_LO16
);
4541 if (offset_expr
.X_op
!= O_symbol
4542 && offset_expr
.X_op
!= O_constant
)
4544 as_bad (_("expression too complex"));
4545 offset_expr
.X_op
= O_constant
;
4548 if (offset_expr
.X_op
== O_constant
)
4549 load_register (&icnt
, tempreg
, &offset_expr
, dbl
);
4550 else if (mips_pic
== NO_PIC
)
4552 /* If this is a reference to a GP relative symbol, we want
4553 addiu $tempreg,$gp,<sym> (BFD_RELOC_GPREL16)
4555 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
4556 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
4557 If we have a constant, we need two instructions anyhow,
4558 so we may as well always use the latter form.
4560 With 64bit address space and a usable $at we want
4561 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
4562 lui $at,<sym> (BFD_RELOC_HI16_S)
4563 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
4564 daddiu $at,<sym> (BFD_RELOC_LO16)
4566 dadd $tempreg,$tempreg,$at
4568 If $at is already in use, we use an path which is suboptimal
4569 on superscalar processors.
4570 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
4571 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
4573 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
4575 daddiu $tempreg,<sym> (BFD_RELOC_LO16)
4578 if (HAVE_64BIT_ADDRESSES
)
4580 /* We don't do GP optimization for now because RELAX_ENCODE can't
4581 hold the data for such large chunks. */
4585 macro_build (p
, &icnt
, &offset_expr
, "lui", "t,u",
4586 tempreg
, (int) BFD_RELOC_MIPS_HIGHEST
);
4587 macro_build (p
, &icnt
, &offset_expr
, "lui", "t,u",
4588 AT
, (int) BFD_RELOC_HI16_S
);
4589 macro_build (p
, &icnt
, &offset_expr
, "daddiu", "t,r,j",
4590 tempreg
, tempreg
, (int) BFD_RELOC_MIPS_HIGHER
);
4591 macro_build (p
, &icnt
, &offset_expr
, "daddiu", "t,r,j",
4592 AT
, AT
, (int) BFD_RELOC_LO16
);
4593 macro_build (p
, &icnt
, (expressionS
*) NULL
, "dsll32",
4594 "d,w,<", tempreg
, tempreg
, 0);
4595 macro_build (p
, &icnt
, (expressionS
*) NULL
, "dadd", "d,v,t",
4596 tempreg
, tempreg
, AT
);
4601 macro_build (p
, &icnt
, &offset_expr
, "lui", "t,u",
4602 tempreg
, (int) BFD_RELOC_MIPS_HIGHEST
);
4603 macro_build (p
, &icnt
, &offset_expr
, "daddiu", "t,r,j",
4604 tempreg
, tempreg
, (int) BFD_RELOC_MIPS_HIGHER
);
4605 macro_build (p
, &icnt
, (expressionS
*) NULL
, "dsll", "d,w,<",
4606 tempreg
, tempreg
, 16);
4607 macro_build (p
, &icnt
, &offset_expr
, "daddiu", "t,r,j",
4608 tempreg
, tempreg
, (int) BFD_RELOC_HI16_S
);
4609 macro_build (p
, &icnt
, (expressionS
*) NULL
, "dsll", "d,w,<",
4610 tempreg
, tempreg
, 16);
4611 macro_build (p
, &icnt
, &offset_expr
, "daddiu", "t,r,j",
4612 tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
4617 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
4618 && ! nopic_need_relax (offset_expr
.X_add_symbol
, 1))
4621 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4622 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
4623 "t,r,j", tempreg
, GP
, (int) BFD_RELOC_GPREL16
);
4624 p
= frag_var (rs_machine_dependent
, 8, 0,
4625 RELAX_ENCODE (4, 8, 0, 4, 0,
4626 mips_opts
.warn_about_macros
),
4627 offset_expr
.X_add_symbol
, (offsetT
) 0,
4630 macro_build_lui (p
, &icnt
, &offset_expr
, tempreg
);
4633 macro_build (p
, &icnt
, &offset_expr
,
4634 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
4635 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
4638 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
4640 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT16
;
4642 /* If this is a reference to an external symbol, and there
4643 is no constant, we want
4644 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4645 or if tempreg is PIC_CALL_REG
4646 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
4647 For a local symbol, we want
4648 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4650 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
4652 If we have a small constant, and this is a reference to
4653 an external symbol, we want
4654 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4656 addiu $tempreg,$tempreg,<constant>
4657 For a local symbol, we want the same instruction
4658 sequence, but we output a BFD_RELOC_LO16 reloc on the
4661 If we have a large constant, and this is a reference to
4662 an external symbol, we want
4663 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4664 lui $at,<hiconstant>
4665 addiu $at,$at,<loconstant>
4666 addu $tempreg,$tempreg,$at
4667 For a local symbol, we want the same instruction
4668 sequence, but we output a BFD_RELOC_LO16 reloc on the
4669 addiu instruction. */
4670 expr1
.X_add_number
= offset_expr
.X_add_number
;
4671 offset_expr
.X_add_number
= 0;
4673 if (expr1
.X_add_number
== 0 && tempreg
== PIC_CALL_REG
)
4674 lw_reloc_type
= (int) BFD_RELOC_MIPS_CALL16
;
4675 macro_build ((char *) NULL
, &icnt
, &offset_expr
, dbl
? "ld" : "lw",
4676 "t,o(b)", tempreg
, lw_reloc_type
, GP
);
4677 if (expr1
.X_add_number
== 0)
4685 /* We're going to put in an addu instruction using
4686 tempreg, so we may as well insert the nop right
4688 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4692 p
= frag_var (rs_machine_dependent
, 8 - off
, 0,
4693 RELAX_ENCODE (0, 8 - off
, -4 - off
, 4 - off
, 0,
4695 ? mips_opts
.warn_about_macros
4697 offset_expr
.X_add_symbol
, 0, NULL
);
4700 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4703 macro_build (p
, &icnt
, &expr1
,
4704 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
4705 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
4706 /* FIXME: If breg == 0, and the next instruction uses
4707 $tempreg, then if this variant case is used an extra
4708 nop will be generated. */
4710 else if (expr1
.X_add_number
>= -0x8000
4711 && expr1
.X_add_number
< 0x8000)
4713 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4715 macro_build ((char *) NULL
, &icnt
, &expr1
,
4716 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
4717 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
4718 frag_var (rs_machine_dependent
, 0, 0,
4719 RELAX_ENCODE (0, 0, -12, -4, 0, 0),
4720 offset_expr
.X_add_symbol
, 0, NULL
);
4726 /* If we are going to add in a base register, and the
4727 target register and the base register are the same,
4728 then we are using AT as a temporary register. Since
4729 we want to load the constant into AT, we add our
4730 current AT (from the global offset table) and the
4731 register into the register now, and pretend we were
4732 not using a base register. */
4737 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4739 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4740 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
4741 "d,v,t", treg
, AT
, breg
);
4747 /* Set mips_optimize around the lui instruction to avoid
4748 inserting an unnecessary nop after the lw. */
4749 hold_mips_optimize
= mips_optimize
;
4751 macro_build_lui (NULL
, &icnt
, &expr1
, AT
);
4752 mips_optimize
= hold_mips_optimize
;
4754 macro_build ((char *) NULL
, &icnt
, &expr1
,
4755 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
4756 "t,r,j", AT
, AT
, (int) BFD_RELOC_LO16
);
4757 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4758 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
4759 "d,v,t", tempreg
, tempreg
, AT
);
4760 frag_var (rs_machine_dependent
, 0, 0,
4761 RELAX_ENCODE (0, 0, -16 + off1
, -8, 0, 0),
4762 offset_expr
.X_add_symbol
, 0, NULL
);
4766 else if (mips_pic
== SVR4_PIC
)
4769 int lui_reloc_type
= (int) BFD_RELOC_MIPS_GOT_HI16
;
4770 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT_LO16
;
4772 /* This is the large GOT case. If this is a reference to an
4773 external symbol, and there is no constant, we want
4774 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
4775 addu $tempreg,$tempreg,$gp
4776 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
4777 or if tempreg is PIC_CALL_REG
4778 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
4779 addu $tempreg,$tempreg,$gp
4780 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
4781 For a local symbol, we want
4782 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4784 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
4786 If we have a small constant, and this is a reference to
4787 an external symbol, we want
4788 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
4789 addu $tempreg,$tempreg,$gp
4790 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
4792 addiu $tempreg,$tempreg,<constant>
4793 For a local symbol, we want
4794 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4796 addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16)
4798 If we have a large constant, and this is a reference to
4799 an external symbol, we want
4800 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
4801 addu $tempreg,$tempreg,$gp
4802 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
4803 lui $at,<hiconstant>
4804 addiu $at,$at,<loconstant>
4805 addu $tempreg,$tempreg,$at
4806 For a local symbol, we want
4807 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4808 lui $at,<hiconstant>
4809 addiu $at,$at,<loconstant> (BFD_RELOC_LO16)
4810 addu $tempreg,$tempreg,$at
4812 expr1
.X_add_number
= offset_expr
.X_add_number
;
4813 offset_expr
.X_add_number
= 0;
4815 if (reg_needs_delay (GP
))
4819 if (expr1
.X_add_number
== 0 && tempreg
== PIC_CALL_REG
)
4821 lui_reloc_type
= (int) BFD_RELOC_MIPS_CALL_HI16
;
4822 lw_reloc_type
= (int) BFD_RELOC_MIPS_CALL_LO16
;
4824 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
4825 tempreg
, lui_reloc_type
);
4826 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4827 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
4828 "d,v,t", tempreg
, tempreg
, GP
);
4829 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4831 "t,o(b)", tempreg
, lw_reloc_type
, tempreg
);
4832 if (expr1
.X_add_number
== 0)
4840 /* We're going to put in an addu instruction using
4841 tempreg, so we may as well insert the nop right
4843 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4848 p
= frag_var (rs_machine_dependent
, 12 + gpdel
, 0,
4849 RELAX_ENCODE (12 + off
, 12 + gpdel
, gpdel
,
4852 ? mips_opts
.warn_about_macros
4854 offset_expr
.X_add_symbol
, 0, NULL
);
4856 else if (expr1
.X_add_number
>= -0x8000
4857 && expr1
.X_add_number
< 0x8000)
4859 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4861 macro_build ((char *) NULL
, &icnt
, &expr1
,
4862 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
4863 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
4865 p
= frag_var (rs_machine_dependent
, 12 + gpdel
, 0,
4866 RELAX_ENCODE (20, 12 + gpdel
, gpdel
, 8 + gpdel
, 0,
4868 ? mips_opts
.warn_about_macros
4870 offset_expr
.X_add_symbol
, 0, NULL
);
4876 /* If we are going to add in a base register, and the
4877 target register and the base register are the same,
4878 then we are using AT as a temporary register. Since
4879 we want to load the constant into AT, we add our
4880 current AT (from the global offset table) and the
4881 register into the register now, and pretend we were
4882 not using a base register. */
4890 assert (tempreg
== AT
);
4891 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4893 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4894 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
4895 "d,v,t", treg
, AT
, breg
);
4900 /* Set mips_optimize around the lui instruction to avoid
4901 inserting an unnecessary nop after the lw. */
4902 hold_mips_optimize
= mips_optimize
;
4904 macro_build_lui (NULL
, &icnt
, &expr1
, AT
);
4905 mips_optimize
= hold_mips_optimize
;
4907 macro_build ((char *) NULL
, &icnt
, &expr1
,
4908 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
4909 "t,r,j", AT
, AT
, (int) BFD_RELOC_LO16
);
4910 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4911 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
4912 "d,v,t", dreg
, dreg
, AT
);
4914 p
= frag_var (rs_machine_dependent
, 16 + gpdel
+ adj
, 0,
4915 RELAX_ENCODE (24 + adj
, 16 + gpdel
+ adj
, gpdel
,
4918 ? mips_opts
.warn_about_macros
4920 offset_expr
.X_add_symbol
, 0, NULL
);
4927 /* This is needed because this instruction uses $gp, but
4928 the first instruction on the main stream does not. */
4929 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4932 macro_build (p
, &icnt
, &offset_expr
,
4934 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
4936 if (expr1
.X_add_number
>= -0x8000
4937 && expr1
.X_add_number
< 0x8000)
4939 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4941 macro_build (p
, &icnt
, &expr1
,
4942 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
4943 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
4944 /* FIXME: If add_number is 0, and there was no base
4945 register, the external symbol case ended with a load,
4946 so if the symbol turns out to not be external, and
4947 the next instruction uses tempreg, an unnecessary nop
4948 will be inserted. */
4954 /* We must add in the base register now, as in the
4955 external symbol case. */
4956 assert (tempreg
== AT
);
4957 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4959 macro_build (p
, &icnt
, (expressionS
*) NULL
,
4960 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
4961 "d,v,t", treg
, AT
, breg
);
4964 /* We set breg to 0 because we have arranged to add
4965 it in in both cases. */
4969 macro_build_lui (p
, &icnt
, &expr1
, AT
);
4971 macro_build (p
, &icnt
, &expr1
,
4972 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
4973 "t,r,j", AT
, AT
, (int) BFD_RELOC_LO16
);
4975 macro_build (p
, &icnt
, (expressionS
*) NULL
,
4976 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
4977 "d,v,t", tempreg
, tempreg
, AT
);
4981 else if (mips_pic
== EMBEDDED_PIC
)
4984 addiu $tempreg,$gp,<sym> (BFD_RELOC_GPREL16)
4986 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4987 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
4988 "t,r,j", tempreg
, GP
, (int) BFD_RELOC_GPREL16
);
4994 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4995 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
4996 "d,v,t", treg
, tempreg
, breg
);
5004 /* The j instruction may not be used in PIC code, since it
5005 requires an absolute address. We convert it to a b
5007 if (mips_pic
== NO_PIC
)
5008 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "j", "a");
5010 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "b", "p");
5013 /* The jal instructions must be handled as macros because when
5014 generating PIC code they expand to multi-instruction
5015 sequences. Normally they are simple instructions. */
5020 if (mips_pic
== NO_PIC
5021 || mips_pic
== EMBEDDED_PIC
)
5022 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "jalr",
5024 else if (mips_pic
== SVR4_PIC
)
5026 if (sreg
!= PIC_CALL_REG
)
5027 as_warn (_("MIPS PIC call to register other than $25"));
5029 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "jalr",
5033 if (mips_cprestore_offset
< 0)
5034 as_warn (_("No .cprestore pseudo-op used in PIC code"));
5037 expr1
.X_add_number
= mips_cprestore_offset
;
5038 macro_build ((char *) NULL
, &icnt
, &expr1
,
5039 HAVE_32BIT_ADDRESSES
? "lw" : "ld", "t,o(b)",
5040 GP
, (int) BFD_RELOC_LO16
, mips_frame_reg
);
5050 if (mips_pic
== NO_PIC
)
5051 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "jal", "a");
5052 else if (mips_pic
== SVR4_PIC
)
5054 /* If this is a reference to an external symbol, and we are
5055 using a small GOT, we want
5056 lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
5060 lw $gp,cprestore($sp)
5061 The cprestore value is set using the .cprestore
5062 pseudo-op. If we are using a big GOT, we want
5063 lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16)
5065 lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16)
5069 lw $gp,cprestore($sp)
5070 If the symbol is not external, we want
5071 lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5073 addiu $25,$25,<sym> (BFD_RELOC_LO16)
5076 lw $gp,cprestore($sp) */
5080 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5081 HAVE_32BIT_ADDRESSES
? "lw" : "ld",
5082 "t,o(b)", PIC_CALL_REG
,
5083 (int) BFD_RELOC_MIPS_CALL16
, GP
);
5084 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5086 p
= frag_var (rs_machine_dependent
, 4, 0,
5087 RELAX_ENCODE (0, 4, -8, 0, 0, 0),
5088 offset_expr
.X_add_symbol
, 0, NULL
);
5094 if (reg_needs_delay (GP
))
5098 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
5099 PIC_CALL_REG
, (int) BFD_RELOC_MIPS_CALL_HI16
);
5100 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5101 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
5102 "d,v,t", PIC_CALL_REG
, PIC_CALL_REG
, GP
);
5103 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5104 HAVE_32BIT_ADDRESSES
? "lw" : "ld",
5105 "t,o(b)", PIC_CALL_REG
,
5106 (int) BFD_RELOC_MIPS_CALL_LO16
, PIC_CALL_REG
);
5107 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5109 p
= frag_var (rs_machine_dependent
, 12 + gpdel
, 0,
5110 RELAX_ENCODE (16, 12 + gpdel
, gpdel
, 8 + gpdel
,
5112 offset_expr
.X_add_symbol
, 0, NULL
);
5115 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
5118 macro_build (p
, &icnt
, &offset_expr
,
5119 HAVE_32BIT_ADDRESSES
? "lw" : "ld",
5120 "t,o(b)", PIC_CALL_REG
,
5121 (int) BFD_RELOC_MIPS_GOT16
, GP
);
5123 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
5126 macro_build (p
, &icnt
, &offset_expr
,
5127 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
5128 "t,r,j", PIC_CALL_REG
, PIC_CALL_REG
,
5129 (int) BFD_RELOC_LO16
);
5130 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5131 "jalr", "s", PIC_CALL_REG
);
5134 if (mips_cprestore_offset
< 0)
5135 as_warn (_("No .cprestore pseudo-op used in PIC code"));
5138 if (mips_opts
.noreorder
)
5139 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5141 expr1
.X_add_number
= mips_cprestore_offset
;
5142 macro_build ((char *) NULL
, &icnt
, &expr1
,
5143 HAVE_32BIT_ADDRESSES
? "lw" : "ld", "t,o(b)",
5144 GP
, (int) BFD_RELOC_LO16
, mips_frame_reg
);
5148 else if (mips_pic
== EMBEDDED_PIC
)
5150 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "bal", "p");
5151 /* The linker may expand the call to a longer sequence which
5152 uses $at, so we must break rather than return. */
5177 /* Itbl support may require additional care here. */
5182 /* Itbl support may require additional care here. */
5187 /* Itbl support may require additional care here. */
5192 /* Itbl support may require additional care here. */
5204 if (mips_arch
== CPU_R4650
)
5206 as_bad (_("opcode not supported on this processor"));
5210 /* Itbl support may require additional care here. */
5215 /* Itbl support may require additional care here. */
5220 /* Itbl support may require additional care here. */
5240 if (breg
== treg
|| coproc
|| lr
)
5262 /* Itbl support may require additional care here. */
5267 /* Itbl support may require additional care here. */
5272 /* Itbl support may require additional care here. */
5277 /* Itbl support may require additional care here. */
5293 if (mips_arch
== CPU_R4650
)
5295 as_bad (_("opcode not supported on this processor"));
5300 /* Itbl support may require additional care here. */
5304 /* Itbl support may require additional care here. */
5309 /* Itbl support may require additional care here. */
5321 /* Itbl support may require additional care here. */
5322 if (mask
== M_LWC1_AB
5323 || mask
== M_SWC1_AB
5324 || mask
== M_LDC1_AB
5325 || mask
== M_SDC1_AB
5334 /* For embedded PIC, we allow loads where the offset is calculated
5335 by subtracting a symbol in the current segment from an unknown
5336 symbol, relative to a base register, e.g.:
5337 <op> $treg, <sym>-<localsym>($breg)
5338 This is used by the compiler for switch statements. */
5339 if (mips_pic
== EMBEDDED_PIC
5340 && offset_expr
.X_op
== O_subtract
5341 && (symbol_constant_p (offset_expr
.X_op_symbol
)
5342 ? S_GET_SEGMENT (offset_expr
.X_op_symbol
) == now_seg
5343 : (symbol_equated_p (offset_expr
.X_op_symbol
)
5345 (symbol_get_value_expression (offset_expr
.X_op_symbol
)
5349 && (offset_expr
.X_add_number
== 0
5350 || OUTPUT_FLAVOR
== bfd_target_elf_flavour
))
5352 /* For this case, we output the instructions:
5353 lui $tempreg,<sym> (BFD_RELOC_PCREL_HI16_S)
5354 addiu $tempreg,$tempreg,$breg
5355 <op> $treg,<sym>($tempreg) (BFD_RELOC_PCREL_LO16)
5356 If the relocation would fit entirely in 16 bits, it would be
5358 <op> $treg,<sym>($breg) (BFD_RELOC_PCREL_LO16)
5359 instead, but that seems quite difficult. */
5360 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
5361 tempreg
, (int) BFD_RELOC_PCREL_HI16_S
);
5362 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5363 ((bfd_arch_bits_per_address (stdoutput
) == 32
5364 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5365 ? "addu" : "daddu"),
5366 "d,v,t", tempreg
, tempreg
, breg
);
5367 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
, treg
,
5368 (int) BFD_RELOC_PCREL_LO16
, tempreg
);
5374 if (offset_expr
.X_op
!= O_constant
5375 && offset_expr
.X_op
!= O_symbol
)
5377 as_bad (_("expression too complex"));
5378 offset_expr
.X_op
= O_constant
;
5381 /* A constant expression in PIC code can be handled just as it
5382 is in non PIC code. */
5383 if (mips_pic
== NO_PIC
5384 || offset_expr
.X_op
== O_constant
)
5386 /* If this is a reference to a GP relative symbol, and there
5387 is no base register, we want
5388 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
5389 Otherwise, if there is no base register, we want
5390 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
5391 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5392 If we have a constant, we need two instructions anyhow,
5393 so we always use the latter form.
5395 If we have a base register, and this is a reference to a
5396 GP relative symbol, we want
5397 addu $tempreg,$breg,$gp
5398 <op> $treg,<sym>($tempreg) (BFD_RELOC_GPREL16)
5400 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
5401 addu $tempreg,$tempreg,$breg
5402 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5403 With a constant we always use the latter case.
5405 With 64bit address space and no base register and $at usable,
5407 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5408 lui $at,<sym> (BFD_RELOC_HI16_S)
5409 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
5412 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5413 If we have a base register, we want
5414 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5415 lui $at,<sym> (BFD_RELOC_HI16_S)
5416 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
5420 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5422 Without $at we can't generate the optimal path for superscalar
5423 processors here since this would require two temporary registers.
5424 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5425 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
5427 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
5429 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5430 If we have a base register, we want
5431 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5432 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
5434 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
5436 daddu $tempreg,$tempreg,$breg
5437 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5439 if (HAVE_64BIT_ADDRESSES
)
5443 /* We don't do GP optimization for now because RELAX_ENCODE can't
5444 hold the data for such large chunks. */
5448 macro_build (p
, &icnt
, &offset_expr
, "lui", "t,u",
5449 tempreg
, (int) BFD_RELOC_MIPS_HIGHEST
);
5450 macro_build (p
, &icnt
, &offset_expr
, "lui", "t,u",
5451 AT
, (int) BFD_RELOC_HI16_S
);
5452 macro_build (p
, &icnt
, &offset_expr
, "daddiu", "t,r,j",
5453 tempreg
, tempreg
, (int) BFD_RELOC_MIPS_HIGHER
);
5455 macro_build (p
, &icnt
, (expressionS
*) NULL
, "daddu",
5456 "d,v,t", AT
, AT
, breg
);
5457 macro_build (p
, &icnt
, (expressionS
*) NULL
, "dsll32",
5458 "d,w,<", tempreg
, tempreg
, 0);
5459 macro_build (p
, &icnt
, (expressionS
*) NULL
, "daddu",
5460 "d,v,t", tempreg
, tempreg
, AT
);
5461 macro_build (p
, &icnt
, &offset_expr
, s
,
5462 fmt
, treg
, (int) BFD_RELOC_LO16
, tempreg
);
5467 macro_build (p
, &icnt
, &offset_expr
, "lui", "t,u",
5468 tempreg
, (int) BFD_RELOC_MIPS_HIGHEST
);
5469 macro_build (p
, &icnt
, &offset_expr
, "daddiu", "t,r,j",
5470 tempreg
, tempreg
, (int) BFD_RELOC_MIPS_HIGHER
);
5471 macro_build (p
, &icnt
, (expressionS
*) NULL
, "dsll",
5472 "d,w,<", tempreg
, tempreg
, 16);
5473 macro_build (p
, &icnt
, &offset_expr
, "daddiu", "t,r,j",
5474 tempreg
, tempreg
, (int) BFD_RELOC_HI16_S
);
5475 macro_build (p
, &icnt
, (expressionS
*) NULL
, "dsll",
5476 "d,w,<", tempreg
, tempreg
, 16);
5478 macro_build (p
, &icnt
, (expressionS
*) NULL
, "daddu",
5479 "d,v,t", tempreg
, tempreg
, breg
);
5480 macro_build (p
, &icnt
, &offset_expr
, s
,
5481 fmt
, treg
, (int) BFD_RELOC_LO16
, tempreg
);
5489 if ((valueT
) offset_expr
.X_add_number
> MAX_GPREL_OFFSET
5490 || nopic_need_relax (offset_expr
.X_add_symbol
, 1))
5495 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
5496 treg
, (int) BFD_RELOC_GPREL16
, GP
);
5497 p
= frag_var (rs_machine_dependent
, 8, 0,
5498 RELAX_ENCODE (4, 8, 0, 4, 0,
5499 (mips_opts
.warn_about_macros
5501 && mips_opts
.noat
))),
5502 offset_expr
.X_add_symbol
, (offsetT
) 0,
5506 macro_build_lui (p
, &icnt
, &offset_expr
, tempreg
);
5509 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
, treg
,
5510 (int) BFD_RELOC_LO16
, tempreg
);
5514 if ((valueT
) offset_expr
.X_add_number
> MAX_GPREL_OFFSET
5515 || nopic_need_relax (offset_expr
.X_add_symbol
, 1))
5520 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5521 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
5522 "d,v,t", tempreg
, breg
, GP
);
5523 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
5524 treg
, (int) BFD_RELOC_GPREL16
, tempreg
);
5525 p
= frag_var (rs_machine_dependent
, 12, 0,
5526 RELAX_ENCODE (8, 12, 0, 8, 0, 0),
5527 offset_expr
.X_add_symbol
, (offsetT
) 0,
5530 macro_build_lui (p
, &icnt
, &offset_expr
, tempreg
);
5533 macro_build (p
, &icnt
, (expressionS
*) NULL
,
5534 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
5535 "d,v,t", tempreg
, tempreg
, breg
);
5538 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
, treg
,
5539 (int) BFD_RELOC_LO16
, tempreg
);
5542 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
5544 /* If this is a reference to an external symbol, we want
5545 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5547 <op> $treg,0($tempreg)
5549 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5551 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
5552 <op> $treg,0($tempreg)
5553 If there is a base register, we add it to $tempreg before
5554 the <op>. If there is a constant, we stick it in the
5555 <op> instruction. We don't handle constants larger than
5556 16 bits, because we have no way to load the upper 16 bits
5557 (actually, we could handle them for the subset of cases
5558 in which we are not using $at). */
5559 assert (offset_expr
.X_op
== O_symbol
);
5560 expr1
.X_add_number
= offset_expr
.X_add_number
;
5561 offset_expr
.X_add_number
= 0;
5562 if (expr1
.X_add_number
< -0x8000
5563 || expr1
.X_add_number
>= 0x8000)
5564 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
5566 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5567 HAVE_32BIT_ADDRESSES
? "lw" : "ld",
5568 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
5569 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
5570 p
= frag_var (rs_machine_dependent
, 4, 0,
5571 RELAX_ENCODE (0, 4, -8, 0, 0, 0),
5572 offset_expr
.X_add_symbol
, 0, NULL
);
5573 macro_build (p
, &icnt
, &offset_expr
,
5574 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
5575 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
5577 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5578 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
5579 "d,v,t", tempreg
, tempreg
, breg
);
5580 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
, treg
,
5581 (int) BFD_RELOC_LO16
, tempreg
);
5583 else if (mips_pic
== SVR4_PIC
)
5587 /* If this is a reference to an external symbol, we want
5588 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5589 addu $tempreg,$tempreg,$gp
5590 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5591 <op> $treg,0($tempreg)
5593 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5595 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
5596 <op> $treg,0($tempreg)
5597 If there is a base register, we add it to $tempreg before
5598 the <op>. If there is a constant, we stick it in the
5599 <op> instruction. We don't handle constants larger than
5600 16 bits, because we have no way to load the upper 16 bits
5601 (actually, we could handle them for the subset of cases
5602 in which we are not using $at). */
5603 assert (offset_expr
.X_op
== O_symbol
);
5604 expr1
.X_add_number
= offset_expr
.X_add_number
;
5605 offset_expr
.X_add_number
= 0;
5606 if (expr1
.X_add_number
< -0x8000
5607 || expr1
.X_add_number
>= 0x8000)
5608 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
5609 if (reg_needs_delay (GP
))
5614 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
5615 tempreg
, (int) BFD_RELOC_MIPS_GOT_HI16
);
5616 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5617 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
5618 "d,v,t", tempreg
, tempreg
, GP
);
5619 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5620 HAVE_32BIT_ADDRESSES
? "lw" : "ld",
5621 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT_LO16
,
5623 p
= frag_var (rs_machine_dependent
, 12 + gpdel
, 0,
5624 RELAX_ENCODE (12, 12 + gpdel
, gpdel
, 8 + gpdel
, 0, 0),
5625 offset_expr
.X_add_symbol
, 0, NULL
);
5628 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
5631 macro_build (p
, &icnt
, &offset_expr
,
5632 HAVE_32BIT_ADDRESSES
? "lw" : "ld",
5633 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
5635 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
5637 macro_build (p
, &icnt
, &offset_expr
,
5638 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
5639 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
5641 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5642 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
5643 "d,v,t", tempreg
, tempreg
, breg
);
5644 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
, treg
,
5645 (int) BFD_RELOC_LO16
, tempreg
);
5647 else if (mips_pic
== EMBEDDED_PIC
)
5649 /* If there is no base register, we want
5650 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
5651 If there is a base register, we want
5652 addu $tempreg,$breg,$gp
5653 <op> $treg,<sym>($tempreg) (BFD_RELOC_GPREL16)
5655 assert (offset_expr
.X_op
== O_symbol
);
5658 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
5659 treg
, (int) BFD_RELOC_GPREL16
, GP
);
5664 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5665 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
5666 "d,v,t", tempreg
, breg
, GP
);
5667 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
5668 treg
, (int) BFD_RELOC_GPREL16
, tempreg
);
5681 load_register (&icnt
, treg
, &imm_expr
, 0);
5685 load_register (&icnt
, treg
, &imm_expr
, 1);
5689 if (imm_expr
.X_op
== O_constant
)
5691 load_register (&icnt
, AT
, &imm_expr
, 0);
5692 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5693 "mtc1", "t,G", AT
, treg
);
5698 assert (offset_expr
.X_op
== O_symbol
5699 && strcmp (segment_name (S_GET_SEGMENT
5700 (offset_expr
.X_add_symbol
)),
5702 && offset_expr
.X_add_number
== 0);
5703 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lwc1", "T,o(b)",
5704 treg
, (int) BFD_RELOC_MIPS_LITERAL
, GP
);
5709 /* Check if we have a constant in IMM_EXPR. If the GPRs are 64 bits
5710 wide, IMM_EXPR is the entire value. Otherwise IMM_EXPR is the high
5711 order 32 bits of the value and the low order 32 bits are either
5712 zero or in OFFSET_EXPR. */
5713 if (imm_expr
.X_op
== O_constant
|| imm_expr
.X_op
== O_big
)
5715 if (HAVE_64BIT_GPRS
)
5716 load_register (&icnt
, treg
, &imm_expr
, 1);
5721 if (target_big_endian
)
5733 load_register (&icnt
, hreg
, &imm_expr
, 0);
5736 if (offset_expr
.X_op
== O_absent
)
5737 move_register (&icnt
, lreg
, 0);
5740 assert (offset_expr
.X_op
== O_constant
);
5741 load_register (&icnt
, lreg
, &offset_expr
, 0);
5748 /* We know that sym is in the .rdata section. First we get the
5749 upper 16 bits of the address. */
5750 if (mips_pic
== NO_PIC
)
5752 /* FIXME: This won't work for a 64 bit address. */
5753 macro_build_lui ((char *) NULL
, &icnt
, &offset_expr
, AT
);
5755 else if (mips_pic
== SVR4_PIC
)
5757 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5758 HAVE_32BIT_ADDRESSES
? "lw" : "ld",
5759 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
5761 else if (mips_pic
== EMBEDDED_PIC
)
5763 /* For embedded PIC we pick up the entire address off $gp in
5764 a single instruction. */
5765 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5766 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
5767 "t,r,j", AT
, GP
, (int) BFD_RELOC_GPREL16
);
5768 offset_expr
.X_op
= O_constant
;
5769 offset_expr
.X_add_number
= 0;
5774 /* Now we load the register(s). */
5775 if (HAVE_64BIT_GPRS
)
5776 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "ld", "t,o(b)",
5777 treg
, (int) BFD_RELOC_LO16
, AT
);
5780 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lw", "t,o(b)",
5781 treg
, (int) BFD_RELOC_LO16
, AT
);
5784 /* FIXME: How in the world do we deal with the possible
5786 offset_expr
.X_add_number
+= 4;
5787 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lw", "t,o(b)",
5788 treg
+ 1, (int) BFD_RELOC_LO16
, AT
);
5792 /* To avoid confusion in tc_gen_reloc, we must ensure that this
5793 does not become a variant frag. */
5794 frag_wane (frag_now
);
5800 /* Check if we have a constant in IMM_EXPR. If the FPRs are 64 bits
5801 wide, IMM_EXPR is the entire value and the GPRs are known to be 64
5802 bits wide as well. Otherwise IMM_EXPR is the high order 32 bits of
5803 the value and the low order 32 bits are either zero or in
5805 if (imm_expr
.X_op
== O_constant
|| imm_expr
.X_op
== O_big
)
5807 load_register (&icnt
, AT
, &imm_expr
, HAVE_64BIT_FPRS
);
5808 if (HAVE_64BIT_FPRS
)
5810 assert (HAVE_64BIT_GPRS
);
5811 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5812 "dmtc1", "t,S", AT
, treg
);
5816 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5817 "mtc1", "t,G", AT
, treg
+ 1);
5818 if (offset_expr
.X_op
== O_absent
)
5819 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5820 "mtc1", "t,G", 0, treg
);
5823 assert (offset_expr
.X_op
== O_constant
);
5824 load_register (&icnt
, AT
, &offset_expr
, 0);
5825 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5826 "mtc1", "t,G", AT
, treg
);
5832 assert (offset_expr
.X_op
== O_symbol
5833 && offset_expr
.X_add_number
== 0);
5834 s
= segment_name (S_GET_SEGMENT (offset_expr
.X_add_symbol
));
5835 if (strcmp (s
, ".lit8") == 0)
5837 if (mips_opts
.isa
!= ISA_MIPS1
)
5839 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "ldc1",
5840 "T,o(b)", treg
, (int) BFD_RELOC_MIPS_LITERAL
, GP
);
5844 r
= BFD_RELOC_MIPS_LITERAL
;
5849 assert (strcmp (s
, RDATA_SECTION_NAME
) == 0);
5850 if (mips_pic
== SVR4_PIC
)
5851 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5852 HAVE_32BIT_ADDRESSES
? "lw" : "ld",
5853 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
5856 /* FIXME: This won't work for a 64 bit address. */
5857 macro_build_lui ((char *) NULL
, &icnt
, &offset_expr
, AT
);
5860 if (mips_opts
.isa
!= ISA_MIPS1
)
5862 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "ldc1",
5863 "T,o(b)", treg
, (int) BFD_RELOC_LO16
, AT
);
5865 /* To avoid confusion in tc_gen_reloc, we must ensure
5866 that this does not become a variant frag. */
5867 frag_wane (frag_now
);
5878 if (mips_arch
== CPU_R4650
)
5880 as_bad (_("opcode not supported on this processor"));
5883 /* Even on a big endian machine $fn comes before $fn+1. We have
5884 to adjust when loading from memory. */
5887 assert (mips_opts
.isa
== ISA_MIPS1
);
5888 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lwc1", "T,o(b)",
5889 target_big_endian
? treg
+ 1 : treg
,
5891 /* FIXME: A possible overflow which I don't know how to deal
5893 offset_expr
.X_add_number
+= 4;
5894 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lwc1", "T,o(b)",
5895 target_big_endian
? treg
: treg
+ 1,
5898 /* To avoid confusion in tc_gen_reloc, we must ensure that this
5899 does not become a variant frag. */
5900 frag_wane (frag_now
);
5909 * The MIPS assembler seems to check for X_add_number not
5910 * being double aligned and generating:
5913 * addiu at,at,%lo(foo+1)
5916 * But, the resulting address is the same after relocation so why
5917 * generate the extra instruction?
5919 if (mips_arch
== CPU_R4650
)
5921 as_bad (_("opcode not supported on this processor"));
5924 /* Itbl support may require additional care here. */
5926 if (mips_opts
.isa
!= ISA_MIPS1
)
5937 if (mips_arch
== CPU_R4650
)
5939 as_bad (_("opcode not supported on this processor"));
5943 if (mips_opts
.isa
!= ISA_MIPS1
)
5951 /* Itbl support may require additional care here. */
5956 if (HAVE_64BIT_GPRS
)
5967 if (HAVE_64BIT_GPRS
)
5977 /* We do _not_ bother to allow embedded PIC (symbol-local_symbol)
5978 loads for the case of doing a pair of loads to simulate an 'ld'.
5979 This is not currently done by the compiler, and assembly coders
5980 writing embedded-pic code can cope. */
5982 if (offset_expr
.X_op
!= O_symbol
5983 && offset_expr
.X_op
!= O_constant
)
5985 as_bad (_("expression too complex"));
5986 offset_expr
.X_op
= O_constant
;
5989 /* Even on a big endian machine $fn comes before $fn+1. We have
5990 to adjust when loading from memory. We set coproc if we must
5991 load $fn+1 first. */
5992 /* Itbl support may require additional care here. */
5993 if (! target_big_endian
)
5996 if (mips_pic
== NO_PIC
5997 || offset_expr
.X_op
== O_constant
)
5999 /* If this is a reference to a GP relative symbol, we want
6000 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
6001 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_GPREL16)
6002 If we have a base register, we use this
6004 <op> $treg,<sym>($at) (BFD_RELOC_GPREL16)
6005 <op> $treg+1,<sym>+4($at) (BFD_RELOC_GPREL16)
6006 If this is not a GP relative symbol, we want
6007 lui $at,<sym> (BFD_RELOC_HI16_S)
6008 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
6009 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
6010 If there is a base register, we add it to $at after the
6011 lui instruction. If there is a constant, we always use
6013 if ((valueT
) offset_expr
.X_add_number
> MAX_GPREL_OFFSET
6014 || nopic_need_relax (offset_expr
.X_add_symbol
, 1))
6033 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6034 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
6035 "d,v,t", AT
, breg
, GP
);
6041 /* Itbl support may require additional care here. */
6042 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
6043 coproc
? treg
+ 1 : treg
,
6044 (int) BFD_RELOC_GPREL16
, tempreg
);
6045 offset_expr
.X_add_number
+= 4;
6047 /* Set mips_optimize to 2 to avoid inserting an
6049 hold_mips_optimize
= mips_optimize
;
6051 /* Itbl support may require additional care here. */
6052 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
6053 coproc
? treg
: treg
+ 1,
6054 (int) BFD_RELOC_GPREL16
, tempreg
);
6055 mips_optimize
= hold_mips_optimize
;
6057 p
= frag_var (rs_machine_dependent
, 12 + off
, 0,
6058 RELAX_ENCODE (8 + off
, 12 + off
, 0, 4 + off
, 1,
6059 used_at
&& mips_opts
.noat
),
6060 offset_expr
.X_add_symbol
, (offsetT
) 0,
6063 /* We just generated two relocs. When tc_gen_reloc
6064 handles this case, it will skip the first reloc and
6065 handle the second. The second reloc already has an
6066 extra addend of 4, which we added above. We must
6067 subtract it out, and then subtract another 4 to make
6068 the first reloc come out right. The second reloc
6069 will come out right because we are going to add 4 to
6070 offset_expr when we build its instruction below.
6072 If we have a symbol, then we don't want to include
6073 the offset, because it will wind up being included
6074 when we generate the reloc. */
6076 if (offset_expr
.X_op
== O_constant
)
6077 offset_expr
.X_add_number
-= 8;
6080 offset_expr
.X_add_number
= -4;
6081 offset_expr
.X_op
= O_constant
;
6084 macro_build_lui (p
, &icnt
, &offset_expr
, AT
);
6089 macro_build (p
, &icnt
, (expressionS
*) NULL
,
6090 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
6091 "d,v,t", AT
, breg
, AT
);
6095 /* Itbl support may require additional care here. */
6096 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
,
6097 coproc
? treg
+ 1 : treg
,
6098 (int) BFD_RELOC_LO16
, AT
);
6101 /* FIXME: How do we handle overflow here? */
6102 offset_expr
.X_add_number
+= 4;
6103 /* Itbl support may require additional care here. */
6104 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
,
6105 coproc
? treg
: treg
+ 1,
6106 (int) BFD_RELOC_LO16
, AT
);
6108 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
6112 /* If this is a reference to an external symbol, we want
6113 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6118 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6120 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
6121 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
6122 If there is a base register we add it to $at before the
6123 lwc1 instructions. If there is a constant we include it
6124 in the lwc1 instructions. */
6126 expr1
.X_add_number
= offset_expr
.X_add_number
;
6127 offset_expr
.X_add_number
= 0;
6128 if (expr1
.X_add_number
< -0x8000
6129 || expr1
.X_add_number
>= 0x8000 - 4)
6130 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6135 frag_grow (24 + off
);
6136 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
6137 HAVE_32BIT_ADDRESSES
? "lw" : "ld",
6138 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
6139 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
6141 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6142 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
6143 "d,v,t", AT
, breg
, AT
);
6144 /* Itbl support may require additional care here. */
6145 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
6146 coproc
? treg
+ 1 : treg
,
6147 (int) BFD_RELOC_LO16
, AT
);
6148 expr1
.X_add_number
+= 4;
6150 /* Set mips_optimize to 2 to avoid inserting an undesired
6152 hold_mips_optimize
= mips_optimize
;
6154 /* Itbl support may require additional care here. */
6155 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
6156 coproc
? treg
: treg
+ 1,
6157 (int) BFD_RELOC_LO16
, AT
);
6158 mips_optimize
= hold_mips_optimize
;
6160 (void) frag_var (rs_machine_dependent
, 0, 0,
6161 RELAX_ENCODE (0, 0, -16 - off
, -8, 1, 0),
6162 offset_expr
.X_add_symbol
, 0, NULL
);
6164 else if (mips_pic
== SVR4_PIC
)
6168 /* If this is a reference to an external symbol, we want
6169 lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16)
6171 lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16)
6176 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6178 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
6179 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
6180 If there is a base register we add it to $at before the
6181 lwc1 instructions. If there is a constant we include it
6182 in the lwc1 instructions. */
6184 expr1
.X_add_number
= offset_expr
.X_add_number
;
6185 offset_expr
.X_add_number
= 0;
6186 if (expr1
.X_add_number
< -0x8000
6187 || expr1
.X_add_number
>= 0x8000 - 4)
6188 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6189 if (reg_needs_delay (GP
))
6198 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
6199 AT
, (int) BFD_RELOC_MIPS_GOT_HI16
);
6200 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6201 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
6202 "d,v,t", AT
, AT
, GP
);
6203 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
6204 HAVE_32BIT_ADDRESSES
? "lw" : "ld",
6205 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT_LO16
, AT
);
6206 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
6208 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6209 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
6210 "d,v,t", AT
, breg
, AT
);
6211 /* Itbl support may require additional care here. */
6212 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
6213 coproc
? treg
+ 1 : treg
,
6214 (int) BFD_RELOC_LO16
, AT
);
6215 expr1
.X_add_number
+= 4;
6217 /* Set mips_optimize to 2 to avoid inserting an undesired
6219 hold_mips_optimize
= mips_optimize
;
6221 /* Itbl support may require additional care here. */
6222 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
6223 coproc
? treg
: treg
+ 1,
6224 (int) BFD_RELOC_LO16
, AT
);
6225 mips_optimize
= hold_mips_optimize
;
6226 expr1
.X_add_number
-= 4;
6228 p
= frag_var (rs_machine_dependent
, 16 + gpdel
+ off
, 0,
6229 RELAX_ENCODE (24 + off
, 16 + gpdel
+ off
, gpdel
,
6230 8 + gpdel
+ off
, 1, 0),
6231 offset_expr
.X_add_symbol
, 0, NULL
);
6234 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
6237 macro_build (p
, &icnt
, &offset_expr
,
6238 HAVE_32BIT_ADDRESSES
? "lw" : "ld",
6239 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
6241 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
6245 macro_build (p
, &icnt
, (expressionS
*) NULL
,
6246 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
6247 "d,v,t", AT
, breg
, AT
);
6250 /* Itbl support may require additional care here. */
6251 macro_build (p
, &icnt
, &expr1
, s
, fmt
,
6252 coproc
? treg
+ 1 : treg
,
6253 (int) BFD_RELOC_LO16
, AT
);
6255 expr1
.X_add_number
+= 4;
6257 /* Set mips_optimize to 2 to avoid inserting an undesired
6259 hold_mips_optimize
= mips_optimize
;
6261 /* Itbl support may require additional care here. */
6262 macro_build (p
, &icnt
, &expr1
, s
, fmt
,
6263 coproc
? treg
: treg
+ 1,
6264 (int) BFD_RELOC_LO16
, AT
);
6265 mips_optimize
= hold_mips_optimize
;
6267 else if (mips_pic
== EMBEDDED_PIC
)
6269 /* If there is no base register, we use
6270 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
6271 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_GPREL16)
6272 If we have a base register, we use
6274 <op> $treg,<sym>($at) (BFD_RELOC_GPREL16)
6275 <op> $treg+1,<sym>+4($at) (BFD_RELOC_GPREL16)
6284 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6285 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
6286 "d,v,t", AT
, breg
, GP
);
6291 /* Itbl support may require additional care here. */
6292 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
6293 coproc
? treg
+ 1 : treg
,
6294 (int) BFD_RELOC_GPREL16
, tempreg
);
6295 offset_expr
.X_add_number
+= 4;
6296 /* Itbl support may require additional care here. */
6297 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
6298 coproc
? treg
: treg
+ 1,
6299 (int) BFD_RELOC_GPREL16
, tempreg
);
6315 assert (HAVE_32BIT_ADDRESSES
);
6316 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
6317 (int) BFD_RELOC_LO16
, breg
);
6318 offset_expr
.X_add_number
+= 4;
6319 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
+ 1,
6320 (int) BFD_RELOC_LO16
, breg
);
6323 /* New code added to support COPZ instructions.
6324 This code builds table entries out of the macros in mip_opcodes.
6325 R4000 uses interlocks to handle coproc delays.
6326 Other chips (like the R3000) require nops to be inserted for delays.
6328 FIXME: Currently, we require that the user handle delays.
6329 In order to fill delay slots for non-interlocked chips,
6330 we must have a way to specify delays based on the coprocessor.
6331 Eg. 4 cycles if load coproc reg from memory, 1 if in cache, etc.
6332 What are the side-effects of the cop instruction?
6333 What cache support might we have and what are its effects?
6334 Both coprocessor & memory require delays. how long???
6335 What registers are read/set/modified?
6337 If an itbl is provided to interpret cop instructions,
6338 this knowledge can be encoded in the itbl spec. */
6352 /* For now we just do C (same as Cz). The parameter will be
6353 stored in insn_opcode by mips_ip. */
6354 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s
, "C",
6359 move_register (&icnt
, dreg
, sreg
);
6362 #ifdef LOSING_COMPILER
6364 /* Try and see if this is a new itbl instruction.
6365 This code builds table entries out of the macros in mip_opcodes.
6366 FIXME: For now we just assemble the expression and pass it's
6367 value along as a 32-bit immediate.
6368 We may want to have the assembler assemble this value,
6369 so that we gain the assembler's knowledge of delay slots,
6371 Would it be more efficient to use mask (id) here? */
6372 if (itbl_have_entries
6373 && (immed_expr
= itbl_assemble (ip
->insn_mo
->name
, "")))
6375 s
= ip
->insn_mo
->name
;
6377 coproc
= ITBL_DECODE_PNUM (immed_expr
);;
6378 macro_build ((char *) NULL
, &icnt
, &immed_expr
, s
, "C");
6385 as_warn (_("Macro used $at after \".set noat\""));
6390 struct mips_cl_insn
*ip
;
6392 register int treg
, sreg
, dreg
, breg
;
6408 bfd_reloc_code_real_type r
;
6411 treg
= (ip
->insn_opcode
>> 16) & 0x1f;
6412 dreg
= (ip
->insn_opcode
>> 11) & 0x1f;
6413 sreg
= breg
= (ip
->insn_opcode
>> 21) & 0x1f;
6414 mask
= ip
->insn_mo
->mask
;
6416 expr1
.X_op
= O_constant
;
6417 expr1
.X_op_symbol
= NULL
;
6418 expr1
.X_add_symbol
= NULL
;
6419 expr1
.X_add_number
= 1;
6423 #endif /* LOSING_COMPILER */
6428 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6429 dbl
? "dmultu" : "multu", "s,t", sreg
, treg
);
6430 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "mflo", "d",
6437 /* The MIPS assembler some times generates shifts and adds. I'm
6438 not trying to be that fancy. GCC should do this for us
6440 load_register (&icnt
, AT
, &imm_expr
, dbl
);
6441 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6442 dbl
? "dmult" : "mult", "s,t", sreg
, AT
);
6443 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "mflo", "d",
6457 mips_emit_delays (true);
6458 ++mips_opts
.noreorder
;
6459 mips_any_noreorder
= 1;
6461 load_register (&icnt
, AT
, &imm_expr
, dbl
);
6462 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6463 dbl
? "dmult" : "mult", "s,t", sreg
, imm
? AT
: treg
);
6464 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "mflo", "d",
6466 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6467 dbl
? "dsra32" : "sra", "d,w,<", dreg
, dreg
, 31);
6468 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "mfhi", "d",
6471 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "tne", "s,t",
6475 expr1
.X_add_number
= 8;
6476 macro_build ((char *) NULL
, &icnt
, &expr1
, "beq", "s,t,p", dreg
,
6478 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "",
6480 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "break",
6483 --mips_opts
.noreorder
;
6484 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "mflo", "d", dreg
);
6497 mips_emit_delays (true);
6498 ++mips_opts
.noreorder
;
6499 mips_any_noreorder
= 1;
6501 load_register (&icnt
, AT
, &imm_expr
, dbl
);
6502 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6503 dbl
? "dmultu" : "multu",
6504 "s,t", sreg
, imm
? AT
: treg
);
6505 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "mfhi", "d",
6507 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "mflo", "d",
6510 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "tne", "s,t",
6514 expr1
.X_add_number
= 8;
6515 macro_build ((char *) NULL
, &icnt
, &expr1
, "beq", "s,t,p", AT
, 0);
6516 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "",
6518 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "break",
6521 --mips_opts
.noreorder
;
6525 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "subu",
6526 "d,v,t", AT
, 0, treg
);
6527 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "srlv",
6528 "d,t,s", AT
, sreg
, AT
);
6529 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "sllv",
6530 "d,t,s", dreg
, sreg
, treg
);
6531 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "or",
6532 "d,v,t", dreg
, dreg
, AT
);
6536 if (imm_expr
.X_op
!= O_constant
)
6537 as_bad (_("rotate count too large"));
6538 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "sll", "d,w,<",
6539 AT
, sreg
, (int) (imm_expr
.X_add_number
& 0x1f));
6540 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "srl", "d,w,<",
6541 dreg
, sreg
, (int) ((0 - imm_expr
.X_add_number
) & 0x1f));
6542 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "or", "d,v,t",
6547 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "subu",
6548 "d,v,t", AT
, 0, treg
);
6549 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "sllv",
6550 "d,t,s", AT
, sreg
, AT
);
6551 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "srlv",
6552 "d,t,s", dreg
, sreg
, treg
);
6553 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "or",
6554 "d,v,t", dreg
, dreg
, AT
);
6558 if (imm_expr
.X_op
!= O_constant
)
6559 as_bad (_("rotate count too large"));
6560 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "srl", "d,w,<",
6561 AT
, sreg
, (int) (imm_expr
.X_add_number
& 0x1f));
6562 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "sll", "d,w,<",
6563 dreg
, sreg
, (int) ((0 - imm_expr
.X_add_number
) & 0x1f));
6564 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "or", "d,v,t",
6569 if (mips_arch
== CPU_R4650
)
6571 as_bad (_("opcode not supported on this processor"));
6574 assert (mips_opts
.isa
== ISA_MIPS1
);
6575 /* Even on a big endian machine $fn comes before $fn+1. We have
6576 to adjust when storing to memory. */
6577 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "swc1", "T,o(b)",
6578 target_big_endian
? treg
+ 1 : treg
,
6579 (int) BFD_RELOC_LO16
, breg
);
6580 offset_expr
.X_add_number
+= 4;
6581 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "swc1", "T,o(b)",
6582 target_big_endian
? treg
: treg
+ 1,
6583 (int) BFD_RELOC_LO16
, breg
);
6588 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
6589 treg
, (int) BFD_RELOC_LO16
);
6591 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
6592 sreg
, (int) BFD_RELOC_LO16
);
6595 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "xor",
6596 "d,v,t", dreg
, sreg
, treg
);
6597 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
6598 dreg
, (int) BFD_RELOC_LO16
);
6603 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
6605 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
6606 sreg
, (int) BFD_RELOC_LO16
);
6611 as_warn (_("Instruction %s: result is always false"),
6613 move_register (&icnt
, dreg
, 0);
6616 if (imm_expr
.X_op
== O_constant
6617 && imm_expr
.X_add_number
>= 0
6618 && imm_expr
.X_add_number
< 0x10000)
6620 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "xori", "t,r,i", dreg
,
6621 sreg
, (int) BFD_RELOC_LO16
);
6624 else if (imm_expr
.X_op
== O_constant
6625 && imm_expr
.X_add_number
> -0x8000
6626 && imm_expr
.X_add_number
< 0)
6628 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
6629 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
6630 HAVE_32BIT_GPRS
? "addiu" : "daddiu",
6631 "t,r,j", dreg
, sreg
,
6632 (int) BFD_RELOC_LO16
);
6637 load_register (&icnt
, AT
, &imm_expr
, 0);
6638 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "xor",
6639 "d,v,t", dreg
, sreg
, AT
);
6642 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
, dreg
,
6643 (int) BFD_RELOC_LO16
);
6648 case M_SGE
: /* sreg >= treg <==> not (sreg < treg) */
6654 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s
, "d,v,t",
6656 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
6657 (int) BFD_RELOC_LO16
);
6660 case M_SGE_I
: /* sreg >= I <==> not (sreg < I) */
6662 if (imm_expr
.X_op
== O_constant
6663 && imm_expr
.X_add_number
>= -0x8000
6664 && imm_expr
.X_add_number
< 0x8000)
6666 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
6667 mask
== M_SGE_I
? "slti" : "sltiu",
6668 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
6673 load_register (&icnt
, AT
, &imm_expr
, 0);
6674 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6675 mask
== M_SGE_I
? "slt" : "sltu", "d,v,t", dreg
, sreg
,
6679 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
6680 (int) BFD_RELOC_LO16
);
6685 case M_SGT
: /* sreg > treg <==> treg < sreg */
6691 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s
, "d,v,t",
6695 case M_SGT_I
: /* sreg > I <==> I < sreg */
6701 load_register (&icnt
, AT
, &imm_expr
, 0);
6702 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s
, "d,v,t",
6706 case M_SLE
: /* sreg <= treg <==> treg >= sreg <==> not (treg < sreg) */
6712 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s
, "d,v,t",
6714 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
6715 (int) BFD_RELOC_LO16
);
6718 case M_SLE_I
: /* sreg <= I <==> I >= sreg <==> not (I < sreg) */
6724 load_register (&icnt
, AT
, &imm_expr
, 0);
6725 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s
, "d,v,t",
6727 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
6728 (int) BFD_RELOC_LO16
);
6732 if (imm_expr
.X_op
== O_constant
6733 && imm_expr
.X_add_number
>= -0x8000
6734 && imm_expr
.X_add_number
< 0x8000)
6736 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "slti", "t,r,j",
6737 dreg
, sreg
, (int) BFD_RELOC_LO16
);
6740 load_register (&icnt
, AT
, &imm_expr
, 0);
6741 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "slt", "d,v,t",
6746 if (imm_expr
.X_op
== O_constant
6747 && imm_expr
.X_add_number
>= -0x8000
6748 && imm_expr
.X_add_number
< 0x8000)
6750 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "sltiu", "t,r,j",
6751 dreg
, sreg
, (int) BFD_RELOC_LO16
);
6754 load_register (&icnt
, AT
, &imm_expr
, 0);
6755 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "sltu",
6756 "d,v,t", dreg
, sreg
, AT
);
6761 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "sltu",
6762 "d,v,t", dreg
, 0, treg
);
6764 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "sltu",
6765 "d,v,t", dreg
, 0, sreg
);
6768 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "xor",
6769 "d,v,t", dreg
, sreg
, treg
);
6770 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "sltu",
6771 "d,v,t", dreg
, 0, dreg
);
6776 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
6778 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "sltu",
6779 "d,v,t", dreg
, 0, sreg
);
6784 as_warn (_("Instruction %s: result is always true"),
6786 macro_build ((char *) NULL
, &icnt
, &expr1
,
6787 HAVE_32BIT_GPRS
? "addiu" : "daddiu",
6788 "t,r,j", dreg
, 0, (int) BFD_RELOC_LO16
);
6791 if (imm_expr
.X_op
== O_constant
6792 && imm_expr
.X_add_number
>= 0
6793 && imm_expr
.X_add_number
< 0x10000)
6795 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "xori", "t,r,i",
6796 dreg
, sreg
, (int) BFD_RELOC_LO16
);
6799 else if (imm_expr
.X_op
== O_constant
6800 && imm_expr
.X_add_number
> -0x8000
6801 && imm_expr
.X_add_number
< 0)
6803 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
6804 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
6805 HAVE_32BIT_GPRS
? "addiu" : "daddiu",
6806 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
6811 load_register (&icnt
, AT
, &imm_expr
, 0);
6812 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "xor",
6813 "d,v,t", dreg
, sreg
, AT
);
6816 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "sltu",
6817 "d,v,t", dreg
, 0, dreg
);
6825 if (imm_expr
.X_op
== O_constant
6826 && imm_expr
.X_add_number
> -0x8000
6827 && imm_expr
.X_add_number
<= 0x8000)
6829 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
6830 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
6831 dbl
? "daddi" : "addi",
6832 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
6835 load_register (&icnt
, AT
, &imm_expr
, dbl
);
6836 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6837 dbl
? "dsub" : "sub", "d,v,t", dreg
, sreg
, AT
);
6843 if (imm_expr
.X_op
== O_constant
6844 && imm_expr
.X_add_number
> -0x8000
6845 && imm_expr
.X_add_number
<= 0x8000)
6847 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
6848 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
6849 dbl
? "daddiu" : "addiu",
6850 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
6853 load_register (&icnt
, AT
, &imm_expr
, dbl
);
6854 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6855 dbl
? "dsubu" : "subu", "d,v,t", dreg
, sreg
, AT
);
6876 load_register (&icnt
, AT
, &imm_expr
, 0);
6877 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s
, "s,t", sreg
,
6883 assert (mips_opts
.isa
== ISA_MIPS1
);
6884 sreg
= (ip
->insn_opcode
>> 11) & 0x1f; /* floating reg */
6885 dreg
= (ip
->insn_opcode
>> 06) & 0x1f; /* floating reg */
6888 * Is the double cfc1 instruction a bug in the mips assembler;
6889 * or is there a reason for it?
6891 mips_emit_delays (true);
6892 ++mips_opts
.noreorder
;
6893 mips_any_noreorder
= 1;
6894 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "cfc1", "t,G",
6896 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "cfc1", "t,G",
6898 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
6899 expr1
.X_add_number
= 3;
6900 macro_build ((char *) NULL
, &icnt
, &expr1
, "ori", "t,r,i", AT
, treg
,
6901 (int) BFD_RELOC_LO16
);
6902 expr1
.X_add_number
= 2;
6903 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", AT
, AT
,
6904 (int) BFD_RELOC_LO16
);
6905 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "ctc1", "t,G",
6907 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
6908 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6909 mask
== M_TRUNCWD
? "cvt.w.d" : "cvt.w.s", "D,S", dreg
, sreg
);
6910 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "ctc1", "t,G",
6912 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
6913 --mips_opts
.noreorder
;
6922 if (offset_expr
.X_add_number
>= 0x7fff)
6923 as_bad (_("operand overflow"));
6924 /* avoid load delay */
6925 if (! target_big_endian
)
6926 offset_expr
.X_add_number
+= 1;
6927 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
6928 (int) BFD_RELOC_LO16
, breg
);
6929 if (! target_big_endian
)
6930 offset_expr
.X_add_number
-= 1;
6932 offset_expr
.X_add_number
+= 1;
6933 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lbu", "t,o(b)", AT
,
6934 (int) BFD_RELOC_LO16
, breg
);
6935 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "sll", "d,w,<",
6937 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "or", "d,v,t",
6951 if (offset_expr
.X_add_number
>= 0x8000 - off
)
6952 as_bad (_("operand overflow"));
6953 if (! target_big_endian
)
6954 offset_expr
.X_add_number
+= off
;
6955 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
6956 (int) BFD_RELOC_LO16
, breg
);
6957 if (! target_big_endian
)
6958 offset_expr
.X_add_number
-= off
;
6960 offset_expr
.X_add_number
+= off
;
6961 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s2
, "t,o(b)", treg
,
6962 (int) BFD_RELOC_LO16
, breg
);
6976 load_address (&icnt
, AT
, &offset_expr
, HAVE_64BIT_ADDRESSES
, &used_at
);
6978 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6979 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
6980 "d,v,t", AT
, AT
, breg
);
6981 if (! target_big_endian
)
6982 expr1
.X_add_number
= off
;
6984 expr1
.X_add_number
= 0;
6985 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, "t,o(b)", treg
,
6986 (int) BFD_RELOC_LO16
, AT
);
6987 if (! target_big_endian
)
6988 expr1
.X_add_number
= 0;
6990 expr1
.X_add_number
= off
;
6991 macro_build ((char *) NULL
, &icnt
, &expr1
, s2
, "t,o(b)", treg
,
6992 (int) BFD_RELOC_LO16
, AT
);
6998 load_address (&icnt
, AT
, &offset_expr
, HAVE_64BIT_ADDRESSES
, &used_at
);
7000 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
7001 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
7002 "d,v,t", AT
, AT
, breg
);
7003 if (target_big_endian
)
7004 expr1
.X_add_number
= 0;
7005 macro_build ((char *) NULL
, &icnt
, &expr1
,
7006 mask
== M_ULH_A
? "lb" : "lbu", "t,o(b)", treg
,
7007 (int) BFD_RELOC_LO16
, AT
);
7008 if (target_big_endian
)
7009 expr1
.X_add_number
= 1;
7011 expr1
.X_add_number
= 0;
7012 macro_build ((char *) NULL
, &icnt
, &expr1
, "lbu", "t,o(b)", AT
,
7013 (int) BFD_RELOC_LO16
, AT
);
7014 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "sll", "d,w,<",
7016 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "or", "d,v,t",
7021 if (offset_expr
.X_add_number
>= 0x7fff)
7022 as_bad (_("operand overflow"));
7023 if (target_big_endian
)
7024 offset_expr
.X_add_number
+= 1;
7025 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "sb", "t,o(b)", treg
,
7026 (int) BFD_RELOC_LO16
, breg
);
7027 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "srl", "d,w,<",
7029 if (target_big_endian
)
7030 offset_expr
.X_add_number
-= 1;
7032 offset_expr
.X_add_number
+= 1;
7033 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "sb", "t,o(b)", AT
,
7034 (int) BFD_RELOC_LO16
, breg
);
7047 if (offset_expr
.X_add_number
>= 0x8000 - off
)
7048 as_bad (_("operand overflow"));
7049 if (! target_big_endian
)
7050 offset_expr
.X_add_number
+= off
;
7051 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
7052 (int) BFD_RELOC_LO16
, breg
);
7053 if (! target_big_endian
)
7054 offset_expr
.X_add_number
-= off
;
7056 offset_expr
.X_add_number
+= off
;
7057 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s2
, "t,o(b)", treg
,
7058 (int) BFD_RELOC_LO16
, breg
);
7072 load_address (&icnt
, AT
, &offset_expr
, HAVE_64BIT_ADDRESSES
, &used_at
);
7074 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
7075 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
7076 "d,v,t", AT
, AT
, breg
);
7077 if (! target_big_endian
)
7078 expr1
.X_add_number
= off
;
7080 expr1
.X_add_number
= 0;
7081 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, "t,o(b)", treg
,
7082 (int) BFD_RELOC_LO16
, AT
);
7083 if (! target_big_endian
)
7084 expr1
.X_add_number
= 0;
7086 expr1
.X_add_number
= off
;
7087 macro_build ((char *) NULL
, &icnt
, &expr1
, s2
, "t,o(b)", treg
,
7088 (int) BFD_RELOC_LO16
, AT
);
7093 load_address (&icnt
, AT
, &offset_expr
, HAVE_64BIT_ADDRESSES
, &used_at
);
7095 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
7096 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
7097 "d,v,t", AT
, AT
, breg
);
7098 if (! target_big_endian
)
7099 expr1
.X_add_number
= 0;
7100 macro_build ((char *) NULL
, &icnt
, &expr1
, "sb", "t,o(b)", treg
,
7101 (int) BFD_RELOC_LO16
, AT
);
7102 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "srl", "d,w,<",
7104 if (! target_big_endian
)
7105 expr1
.X_add_number
= 1;
7107 expr1
.X_add_number
= 0;
7108 macro_build ((char *) NULL
, &icnt
, &expr1
, "sb", "t,o(b)", treg
,
7109 (int) BFD_RELOC_LO16
, AT
);
7110 if (! target_big_endian
)
7111 expr1
.X_add_number
= 0;
7113 expr1
.X_add_number
= 1;
7114 macro_build ((char *) NULL
, &icnt
, &expr1
, "lbu", "t,o(b)", AT
,
7115 (int) BFD_RELOC_LO16
, AT
);
7116 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "sll", "d,w,<",
7118 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "or", "d,v,t",
7123 /* FIXME: Check if this is one of the itbl macros, since they
7124 are added dynamically. */
7125 as_bad (_("Macro %s not implemented yet"), ip
->insn_mo
->name
);
7129 as_warn (_("Macro used $at after \".set noat\""));
7132 /* Implement macros in mips16 mode. */
7136 struct mips_cl_insn
*ip
;
7139 int xreg
, yreg
, zreg
, tmp
;
7143 const char *s
, *s2
, *s3
;
7145 mask
= ip
->insn_mo
->mask
;
7147 xreg
= (ip
->insn_opcode
>> MIPS16OP_SH_RX
) & MIPS16OP_MASK_RX
;
7148 yreg
= (ip
->insn_opcode
>> MIPS16OP_SH_RY
) & MIPS16OP_MASK_RY
;
7149 zreg
= (ip
->insn_opcode
>> MIPS16OP_SH_RZ
) & MIPS16OP_MASK_RZ
;
7153 expr1
.X_op
= O_constant
;
7154 expr1
.X_op_symbol
= NULL
;
7155 expr1
.X_add_symbol
= NULL
;
7156 expr1
.X_add_number
= 1;
7175 mips_emit_delays (true);
7176 ++mips_opts
.noreorder
;
7177 mips_any_noreorder
= 1;
7178 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
7179 dbl
? "ddiv" : "div",
7180 "0,x,y", xreg
, yreg
);
7181 expr1
.X_add_number
= 2;
7182 macro_build ((char *) NULL
, &icnt
, &expr1
, "bnez", "x,p", yreg
);
7183 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "break", "6",
7186 /* FIXME: The normal code checks for of -1 / -0x80000000 here,
7187 since that causes an overflow. We should do that as well,
7188 but I don't see how to do the comparisons without a temporary
7190 --mips_opts
.noreorder
;
7191 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s
, "x", zreg
);
7210 mips_emit_delays (true);
7211 ++mips_opts
.noreorder
;
7212 mips_any_noreorder
= 1;
7213 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s
, "0,x,y",
7215 expr1
.X_add_number
= 2;
7216 macro_build ((char *) NULL
, &icnt
, &expr1
, "bnez", "x,p", yreg
);
7217 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "break",
7219 --mips_opts
.noreorder
;
7220 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s2
, "x", zreg
);
7226 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
7227 dbl
? "dmultu" : "multu", "x,y", xreg
, yreg
);
7228 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "mflo", "x",
7237 if (imm_expr
.X_op
!= O_constant
)
7238 as_bad (_("Unsupported large constant"));
7239 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
7240 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
7241 dbl
? "daddiu" : "addiu", "y,x,4", yreg
, xreg
);
7245 if (imm_expr
.X_op
!= O_constant
)
7246 as_bad (_("Unsupported large constant"));
7247 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
7248 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "addiu",
7253 if (imm_expr
.X_op
!= O_constant
)
7254 as_bad (_("Unsupported large constant"));
7255 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
7256 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "daddiu",
7279 goto do_reverse_branch
;
7283 goto do_reverse_branch
;
7295 goto do_reverse_branch
;
7306 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s
, "x,y",
7308 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s2
, "p");
7335 goto do_addone_branch_i
;
7340 goto do_addone_branch_i
;
7355 goto do_addone_branch_i
;
7362 if (imm_expr
.X_op
!= O_constant
)
7363 as_bad (_("Unsupported large constant"));
7364 ++imm_expr
.X_add_number
;
7367 macro_build ((char *) NULL
, &icnt
, &imm_expr
, s
, s3
, xreg
);
7368 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s2
, "p");
7372 expr1
.X_add_number
= 0;
7373 macro_build ((char *) NULL
, &icnt
, &expr1
, "slti", "x,8", yreg
);
7375 move_register (&icnt
, xreg
, yreg
);
7376 expr1
.X_add_number
= 2;
7377 macro_build ((char *) NULL
, &icnt
, &expr1
, "bteqz", "p");
7378 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
7379 "neg", "x,w", xreg
, xreg
);
7383 /* For consistency checking, verify that all bits are specified either
7384 by the match/mask part of the instruction definition, or by the
7387 validate_mips_insn (opc
)
7388 const struct mips_opcode
*opc
;
7390 const char *p
= opc
->args
;
7392 unsigned long used_bits
= opc
->mask
;
7394 if ((used_bits
& opc
->match
) != opc
->match
)
7396 as_bad (_("internal: bad mips opcode (mask error): %s %s"),
7397 opc
->name
, opc
->args
);
7400 #define USE_BITS(mask,shift) (used_bits |= ((mask) << (shift)))
7407 case '<': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
7408 case '>': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
7410 case 'B': USE_BITS (OP_MASK_CODE20
, OP_SH_CODE20
); break;
7411 case 'C': USE_BITS (OP_MASK_COPZ
, OP_SH_COPZ
); break;
7412 case 'D': USE_BITS (OP_MASK_FD
, OP_SH_FD
); break;
7413 case 'E': USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
7415 case 'G': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
7416 case 'H': USE_BITS (OP_MASK_SEL
, OP_SH_SEL
); break;
7418 case 'J': USE_BITS (OP_MASK_CODE19
, OP_SH_CODE19
); break;
7420 case 'M': USE_BITS (OP_MASK_CCC
, OP_SH_CCC
); break;
7421 case 'N': USE_BITS (OP_MASK_BCC
, OP_SH_BCC
); break;
7422 case 'R': USE_BITS (OP_MASK_FR
, OP_SH_FR
); break;
7423 case 'S': USE_BITS (OP_MASK_FS
, OP_SH_FS
); break;
7424 case 'T': USE_BITS (OP_MASK_FT
, OP_SH_FT
); break;
7425 case 'V': USE_BITS (OP_MASK_FS
, OP_SH_FS
); break;
7426 case 'W': USE_BITS (OP_MASK_FT
, OP_SH_FT
); break;
7427 case 'a': USE_BITS (OP_MASK_TARGET
, OP_SH_TARGET
); break;
7428 case 'b': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
7429 case 'c': USE_BITS (OP_MASK_CODE
, OP_SH_CODE
); break;
7430 case 'd': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
7432 case 'h': USE_BITS (OP_MASK_PREFX
, OP_SH_PREFX
); break;
7433 case 'i': USE_BITS (OP_MASK_IMMEDIATE
, OP_SH_IMMEDIATE
); break;
7434 case 'j': USE_BITS (OP_MASK_DELTA
, OP_SH_DELTA
); break;
7435 case 'k': USE_BITS (OP_MASK_CACHE
, OP_SH_CACHE
); break;
7437 case 'o': USE_BITS (OP_MASK_DELTA
, OP_SH_DELTA
); break;
7438 case 'p': USE_BITS (OP_MASK_DELTA
, OP_SH_DELTA
); break;
7439 case 'q': USE_BITS (OP_MASK_CODE2
, OP_SH_CODE2
); break;
7440 case 'r': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
7441 case 's': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
7442 case 't': USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
7443 case 'u': USE_BITS (OP_MASK_IMMEDIATE
, OP_SH_IMMEDIATE
); break;
7444 case 'v': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
7445 case 'w': USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
7448 case 'P': USE_BITS (OP_MASK_PERFREG
, OP_SH_PERFREG
); break;
7449 case 'U': USE_BITS (OP_MASK_RD
, OP_SH_RD
);
7450 USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
7452 as_bad (_("internal: bad mips opcode (unknown operand type `%c'): %s %s"),
7453 c
, opc
->name
, opc
->args
);
7457 if (used_bits
!= 0xffffffff)
7459 as_bad (_("internal: bad mips opcode (bits 0x%lx undefined): %s %s"),
7460 ~used_bits
& 0xffffffff, opc
->name
, opc
->args
);
7466 /* This routine assembles an instruction into its binary format. As a
7467 side effect, it sets one of the global variables imm_reloc or
7468 offset_reloc to the type of relocation to do if one of the operands
7469 is an address expression. */
7474 struct mips_cl_insn
*ip
;
7479 struct mips_opcode
*insn
;
7482 unsigned int lastregno
= 0;
7485 int full_opcode_match
= 1;
7489 /* If the instruction contains a '.', we first try to match an instruction
7490 including the '.'. Then we try again without the '.'. */
7492 for (s
= str
; *s
!= '\0' && !ISSPACE (*s
); ++s
)
7495 /* If we stopped on whitespace, then replace the whitespace with null for
7496 the call to hash_find. Save the character we replaced just in case we
7497 have to re-parse the instruction. */
7504 insn
= (struct mips_opcode
*) hash_find (op_hash
, str
);
7506 /* If we didn't find the instruction in the opcode table, try again, but
7507 this time with just the instruction up to, but not including the
7511 /* Restore the character we overwrite above (if any). */
7515 /* Scan up to the first '.' or whitespace. */
7517 *s
!= '\0' && *s
!= '.' && !ISSPACE (*s
);
7521 /* If we did not find a '.', then we can quit now. */
7524 insn_error
= "unrecognized opcode";
7528 /* Lookup the instruction in the hash table. */
7530 if ((insn
= (struct mips_opcode
*) hash_find (op_hash
, str
)) == NULL
)
7532 insn_error
= "unrecognized opcode";
7536 full_opcode_match
= 0;
7544 assert (strcmp (insn
->name
, str
) == 0);
7546 if (OPCODE_IS_MEMBER (insn
, mips_opts
.isa
, mips_arch
))
7551 if (insn
->pinfo
!= INSN_MACRO
)
7553 if (mips_arch
== CPU_R4650
&& (insn
->pinfo
& FP_D
) != 0)
7559 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
]
7560 && strcmp (insn
->name
, insn
[1].name
) == 0)
7569 static char buf
[100];
7571 _("opcode not supported on this processor: %s (%s)"),
7572 mips_cpu_to_str (mips_arch
),
7573 mips_isa_to_str (mips_opts
.isa
));
7584 ip
->insn_opcode
= insn
->match
;
7586 for (args
= insn
->args
;; ++args
)
7588 s
+= strspn (s
, " \t");
7591 case '\0': /* end of args */
7604 ip
->insn_opcode
|= lastregno
<< OP_SH_RS
;
7608 ip
->insn_opcode
|= lastregno
<< OP_SH_RT
;
7612 ip
->insn_opcode
|= lastregno
<< OP_SH_FT
;
7616 ip
->insn_opcode
|= lastregno
<< OP_SH_FS
;
7622 /* Handle optional base register.
7623 Either the base register is omitted or
7624 we must have a left paren. */
7625 /* This is dependent on the next operand specifier
7626 is a base register specification. */
7627 assert (args
[1] == 'b' || args
[1] == '5'
7628 || args
[1] == '-' || args
[1] == '4');
7632 case ')': /* these must match exactly */
7637 case '<': /* must be at least one digit */
7639 * According to the manual, if the shift amount is greater
7640 * than 31 or less than 0, then the shift amount should be
7641 * mod 32. In reality the mips assembler issues an error.
7642 * We issue a warning and mask out all but the low 5 bits.
7644 my_getExpression (&imm_expr
, s
);
7645 check_absolute_expr (ip
, &imm_expr
);
7646 if ((unsigned long) imm_expr
.X_add_number
> 31)
7648 as_warn (_("Improper shift amount (%ld)"),
7649 (long) imm_expr
.X_add_number
);
7650 imm_expr
.X_add_number
&= OP_MASK_SHAMT
;
7652 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_SHAMT
;
7653 imm_expr
.X_op
= O_absent
;
7657 case '>': /* shift amount minus 32 */
7658 my_getExpression (&imm_expr
, s
);
7659 check_absolute_expr (ip
, &imm_expr
);
7660 if ((unsigned long) imm_expr
.X_add_number
< 32
7661 || (unsigned long) imm_expr
.X_add_number
> 63)
7663 ip
->insn_opcode
|= (imm_expr
.X_add_number
- 32) << OP_SH_SHAMT
;
7664 imm_expr
.X_op
= O_absent
;
7668 case 'k': /* cache code */
7669 case 'h': /* prefx code */
7670 my_getExpression (&imm_expr
, s
);
7671 check_absolute_expr (ip
, &imm_expr
);
7672 if ((unsigned long) imm_expr
.X_add_number
> 31)
7674 as_warn (_("Invalid value for `%s' (%lu)"),
7676 (unsigned long) imm_expr
.X_add_number
);
7677 imm_expr
.X_add_number
&= 0x1f;
7680 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_CACHE
;
7682 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_PREFX
;
7683 imm_expr
.X_op
= O_absent
;
7687 case 'c': /* break code */
7688 my_getExpression (&imm_expr
, s
);
7689 check_absolute_expr (ip
, &imm_expr
);
7690 if ((unsigned) imm_expr
.X_add_number
> 1023)
7692 as_warn (_("Illegal break code (%ld)"),
7693 (long) imm_expr
.X_add_number
);
7694 imm_expr
.X_add_number
&= OP_MASK_CODE
;
7696 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_CODE
;
7697 imm_expr
.X_op
= O_absent
;
7701 case 'q': /* lower break code */
7702 my_getExpression (&imm_expr
, s
);
7703 check_absolute_expr (ip
, &imm_expr
);
7704 if ((unsigned) imm_expr
.X_add_number
> 1023)
7706 as_warn (_("Illegal lower break code (%ld)"),
7707 (long) imm_expr
.X_add_number
);
7708 imm_expr
.X_add_number
&= OP_MASK_CODE2
;
7710 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_CODE2
;
7711 imm_expr
.X_op
= O_absent
;
7715 case 'B': /* 20-bit syscall/break code. */
7716 my_getExpression (&imm_expr
, s
);
7717 check_absolute_expr (ip
, &imm_expr
);
7718 if ((unsigned) imm_expr
.X_add_number
> OP_MASK_CODE20
)
7719 as_warn (_("Illegal 20-bit code (%ld)"),
7720 (long) imm_expr
.X_add_number
);
7721 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_CODE20
;
7722 imm_expr
.X_op
= O_absent
;
7726 case 'C': /* Coprocessor code */
7727 my_getExpression (&imm_expr
, s
);
7728 check_absolute_expr (ip
, &imm_expr
);
7729 if ((unsigned long) imm_expr
.X_add_number
>= (1<<25))
7731 as_warn (_("Coproccesor code > 25 bits (%ld)"),
7732 (long) imm_expr
.X_add_number
);
7733 imm_expr
.X_add_number
&= ((1<<25) - 1);
7735 ip
->insn_opcode
|= imm_expr
.X_add_number
;
7736 imm_expr
.X_op
= O_absent
;
7740 case 'J': /* 19-bit wait code. */
7741 my_getExpression (&imm_expr
, s
);
7742 check_absolute_expr (ip
, &imm_expr
);
7743 if ((unsigned) imm_expr
.X_add_number
> OP_MASK_CODE19
)
7744 as_warn (_("Illegal 19-bit code (%ld)"),
7745 (long) imm_expr
.X_add_number
);
7746 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_CODE19
;
7747 imm_expr
.X_op
= O_absent
;
7751 case 'P': /* Performance register */
7752 my_getExpression (&imm_expr
, s
);
7753 check_absolute_expr (ip
, &imm_expr
);
7754 if (imm_expr
.X_add_number
!= 0 && imm_expr
.X_add_number
!= 1)
7756 as_warn (_("Invalid performance register (%ld)"),
7757 (long) imm_expr
.X_add_number
);
7758 imm_expr
.X_add_number
&= OP_MASK_PERFREG
;
7760 ip
->insn_opcode
|= (imm_expr
.X_add_number
<< OP_SH_PERFREG
);
7761 imm_expr
.X_op
= O_absent
;
7765 case 'b': /* base register */
7766 case 'd': /* destination register */
7767 case 's': /* source register */
7768 case 't': /* target register */
7769 case 'r': /* both target and source */
7770 case 'v': /* both dest and source */
7771 case 'w': /* both dest and target */
7772 case 'E': /* coprocessor target register */
7773 case 'G': /* coprocessor destination register */
7774 case 'x': /* ignore register name */
7775 case 'z': /* must be zero register */
7776 case 'U': /* destination register (clo/clz). */
7791 while (ISDIGIT (*s
));
7793 as_bad (_("Invalid register number (%d)"), regno
);
7795 else if (*args
== 'E' || *args
== 'G')
7799 if (s
[1] == 'f' && s
[2] == 'p')
7804 else if (s
[1] == 's' && s
[2] == 'p')
7809 else if (s
[1] == 'g' && s
[2] == 'p')
7814 else if (s
[1] == 'a' && s
[2] == 't')
7819 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '0')
7824 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '1')
7829 else if (itbl_have_entries
)
7834 p
= s
+ 1; /* advance past '$' */
7835 n
= itbl_get_field (&p
); /* n is name */
7837 /* See if this is a register defined in an
7839 if (itbl_get_reg_val (n
, &r
))
7841 /* Get_field advances to the start of
7842 the next field, so we need to back
7843 rack to the end of the last field. */
7847 s
= strchr (s
, '\0');
7860 as_warn (_("Used $at without \".set noat\""));
7866 if (c
== 'r' || c
== 'v' || c
== 'w')
7873 /* 'z' only matches $0. */
7874 if (c
== 'z' && regno
!= 0)
7877 /* Now that we have assembled one operand, we use the args string
7878 * to figure out where it goes in the instruction. */
7885 ip
->insn_opcode
|= regno
<< OP_SH_RS
;
7889 ip
->insn_opcode
|= regno
<< OP_SH_RD
;
7892 ip
->insn_opcode
|= regno
<< OP_SH_RD
;
7893 ip
->insn_opcode
|= regno
<< OP_SH_RT
;
7898 ip
->insn_opcode
|= regno
<< OP_SH_RT
;
7901 /* This case exists because on the r3000 trunc
7902 expands into a macro which requires a gp
7903 register. On the r6000 or r4000 it is
7904 assembled into a single instruction which
7905 ignores the register. Thus the insn version
7906 is MIPS_ISA2 and uses 'x', and the macro
7907 version is MIPS_ISA1 and uses 't'. */
7910 /* This case is for the div instruction, which
7911 acts differently if the destination argument
7912 is $0. This only matches $0, and is checked
7913 outside the switch. */
7916 /* Itbl operand; not yet implemented. FIXME ?? */
7918 /* What about all other operands like 'i', which
7919 can be specified in the opcode table? */
7929 ip
->insn_opcode
|= lastregno
<< OP_SH_RS
;
7932 ip
->insn_opcode
|= lastregno
<< OP_SH_RT
;
7937 case 'D': /* floating point destination register */
7938 case 'S': /* floating point source register */
7939 case 'T': /* floating point target register */
7940 case 'R': /* floating point source register */
7944 if (s
[0] == '$' && s
[1] == 'f'
7955 while (ISDIGIT (*s
));
7958 as_bad (_("Invalid float register number (%d)"), regno
);
7960 if ((regno
& 1) != 0
7962 && ! (strcmp (str
, "mtc1") == 0
7963 || strcmp (str
, "mfc1") == 0
7964 || strcmp (str
, "lwc1") == 0
7965 || strcmp (str
, "swc1") == 0
7966 || strcmp (str
, "l.s") == 0
7967 || strcmp (str
, "s.s") == 0))
7968 as_warn (_("Float register should be even, was %d"),
7976 if (c
== 'V' || c
== 'W')
7986 ip
->insn_opcode
|= regno
<< OP_SH_FD
;
7990 ip
->insn_opcode
|= regno
<< OP_SH_FS
;
7994 ip
->insn_opcode
|= regno
<< OP_SH_FT
;
7997 ip
->insn_opcode
|= regno
<< OP_SH_FR
;
8007 ip
->insn_opcode
|= lastregno
<< OP_SH_FS
;
8010 ip
->insn_opcode
|= lastregno
<< OP_SH_FT
;
8016 my_getExpression (&imm_expr
, s
);
8017 if (imm_expr
.X_op
!= O_big
8018 && imm_expr
.X_op
!= O_constant
)
8019 insn_error
= _("absolute expression required");
8024 my_getExpression (&offset_expr
, s
);
8025 *imm_reloc
= BFD_RELOC_32
;
8038 unsigned char temp
[8];
8040 unsigned int length
;
8045 /* These only appear as the last operand in an
8046 instruction, and every instruction that accepts
8047 them in any variant accepts them in all variants.
8048 This means we don't have to worry about backing out
8049 any changes if the instruction does not match.
8051 The difference between them is the size of the
8052 floating point constant and where it goes. For 'F'
8053 and 'L' the constant is 64 bits; for 'f' and 'l' it
8054 is 32 bits. Where the constant is placed is based
8055 on how the MIPS assembler does things:
8058 f -- immediate value
8061 The .lit4 and .lit8 sections are only used if
8062 permitted by the -G argument.
8064 When generating embedded PIC code, we use the
8065 .lit8 section but not the .lit4 section (we can do
8066 .lit4 inline easily; we need to put .lit8
8067 somewhere in the data segment, and using .lit8
8068 permits the linker to eventually combine identical
8071 The code below needs to know whether the target register
8072 is 32 or 64 bits wide. It relies on the fact 'f' and
8073 'F' are used with GPR-based instructions and 'l' and
8074 'L' are used with FPR-based instructions. */
8076 f64
= *args
== 'F' || *args
== 'L';
8077 using_gprs
= *args
== 'F' || *args
== 'f';
8079 save_in
= input_line_pointer
;
8080 input_line_pointer
= s
;
8081 err
= md_atof (f64
? 'd' : 'f', (char *) temp
, &len
);
8083 s
= input_line_pointer
;
8084 input_line_pointer
= save_in
;
8085 if (err
!= NULL
&& *err
!= '\0')
8087 as_bad (_("Bad floating point constant: %s"), err
);
8088 memset (temp
, '\0', sizeof temp
);
8089 length
= f64
? 8 : 4;
8092 assert (length
== (unsigned) (f64
? 8 : 4));
8096 && (! USE_GLOBAL_POINTER_OPT
8097 || mips_pic
== EMBEDDED_PIC
8098 || g_switch_value
< 4
8099 || (temp
[0] == 0 && temp
[1] == 0)
8100 || (temp
[2] == 0 && temp
[3] == 0))))
8102 imm_expr
.X_op
= O_constant
;
8103 if (! target_big_endian
)
8104 imm_expr
.X_add_number
= bfd_getl32 (temp
);
8106 imm_expr
.X_add_number
= bfd_getb32 (temp
);
8109 && ! mips_disable_float_construction
8110 /* Constants can only be constructed in GPRs and
8111 copied to FPRs if the GPRs are at least as wide
8112 as the FPRs. Force the constant into memory if
8113 we are using 64-bit FPRs but the GPRs are only
8116 || ! (HAVE_64BIT_FPRS
&& HAVE_32BIT_GPRS
))
8117 && ((temp
[0] == 0 && temp
[1] == 0)
8118 || (temp
[2] == 0 && temp
[3] == 0))
8119 && ((temp
[4] == 0 && temp
[5] == 0)
8120 || (temp
[6] == 0 && temp
[7] == 0)))
8122 /* The value is simple enough to load with a couple of
8123 instructions. If using 32-bit registers, set
8124 imm_expr to the high order 32 bits and offset_expr to
8125 the low order 32 bits. Otherwise, set imm_expr to
8126 the entire 64 bit constant. */
8127 if (using_gprs
? HAVE_32BIT_GPRS
: HAVE_32BIT_FPRS
)
8129 imm_expr
.X_op
= O_constant
;
8130 offset_expr
.X_op
= O_constant
;
8131 if (! target_big_endian
)
8133 imm_expr
.X_add_number
= bfd_getl32 (temp
+ 4);
8134 offset_expr
.X_add_number
= bfd_getl32 (temp
);
8138 imm_expr
.X_add_number
= bfd_getb32 (temp
);
8139 offset_expr
.X_add_number
= bfd_getb32 (temp
+ 4);
8141 if (offset_expr
.X_add_number
== 0)
8142 offset_expr
.X_op
= O_absent
;
8144 else if (sizeof (imm_expr
.X_add_number
) > 4)
8146 imm_expr
.X_op
= O_constant
;
8147 if (! target_big_endian
)
8148 imm_expr
.X_add_number
= bfd_getl64 (temp
);
8150 imm_expr
.X_add_number
= bfd_getb64 (temp
);
8154 imm_expr
.X_op
= O_big
;
8155 imm_expr
.X_add_number
= 4;
8156 if (! target_big_endian
)
8158 generic_bignum
[0] = bfd_getl16 (temp
);
8159 generic_bignum
[1] = bfd_getl16 (temp
+ 2);
8160 generic_bignum
[2] = bfd_getl16 (temp
+ 4);
8161 generic_bignum
[3] = bfd_getl16 (temp
+ 6);
8165 generic_bignum
[0] = bfd_getb16 (temp
+ 6);
8166 generic_bignum
[1] = bfd_getb16 (temp
+ 4);
8167 generic_bignum
[2] = bfd_getb16 (temp
+ 2);
8168 generic_bignum
[3] = bfd_getb16 (temp
);
8174 const char *newname
;
8177 /* Switch to the right section. */
8179 subseg
= now_subseg
;
8182 default: /* unused default case avoids warnings. */
8184 newname
= RDATA_SECTION_NAME
;
8185 if ((USE_GLOBAL_POINTER_OPT
&& g_switch_value
>= 8)
8186 || mips_pic
== EMBEDDED_PIC
)
8190 if (mips_pic
== EMBEDDED_PIC
)
8193 newname
= RDATA_SECTION_NAME
;
8196 assert (!USE_GLOBAL_POINTER_OPT
8197 || g_switch_value
>= 4);
8201 new_seg
= subseg_new (newname
, (subsegT
) 0);
8202 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
8203 bfd_set_section_flags (stdoutput
, new_seg
,
8208 frag_align (*args
== 'l' ? 2 : 3, 0, 0);
8209 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
8210 && strcmp (TARGET_OS
, "elf") != 0)
8211 record_alignment (new_seg
, 4);
8213 record_alignment (new_seg
, *args
== 'l' ? 2 : 3);
8215 as_bad (_("Can't use floating point insn in this section"));
8217 /* Set the argument to the current address in the
8219 offset_expr
.X_op
= O_symbol
;
8220 offset_expr
.X_add_symbol
=
8221 symbol_new ("L0\001", now_seg
,
8222 (valueT
) frag_now_fix (), frag_now
);
8223 offset_expr
.X_add_number
= 0;
8225 /* Put the floating point number into the section. */
8226 p
= frag_more ((int) length
);
8227 memcpy (p
, temp
, length
);
8229 /* Switch back to the original section. */
8230 subseg_set (seg
, subseg
);
8235 case 'i': /* 16 bit unsigned immediate */
8236 case 'j': /* 16 bit signed immediate */
8237 *imm_reloc
= BFD_RELOC_LO16
;
8238 c
= my_getSmallExpression (&imm_expr
, s
);
8243 if (imm_expr
.X_op
== O_constant
)
8244 imm_expr
.X_add_number
=
8245 (imm_expr
.X_add_number
>> 16) & 0xffff;
8247 else if (c
== S_EX_HIGHEST
)
8248 *imm_reloc
= BFD_RELOC_MIPS_HIGHEST
;
8249 else if (c
== S_EX_HIGHER
)
8250 *imm_reloc
= BFD_RELOC_MIPS_HIGHER
;
8251 else if (c
== S_EX_GP_REL
)
8253 /* This occurs in NewABI only. */
8254 c
= my_getSmallExpression (&imm_expr
, s
);
8256 as_bad (_("bad composition of relocations"));
8259 c
= my_getSmallExpression (&imm_expr
, s
);
8261 as_bad (_("bad composition of relocations"));
8264 imm_reloc
[0] = BFD_RELOC_GPREL16
;
8265 imm_reloc
[1] = BFD_RELOC_MIPS_SUB
;
8266 imm_reloc
[2] = BFD_RELOC_LO16
;
8271 else if (c
== S_EX_HI
)
8273 *imm_reloc
= BFD_RELOC_HI16_S
;
8274 imm_unmatched_hi
= true;
8277 *imm_reloc
= BFD_RELOC_HI16
;
8279 else if (imm_expr
.X_op
== O_constant
)
8280 imm_expr
.X_add_number
&= 0xffff;
8284 if ((c
== S_EX_NONE
&& imm_expr
.X_op
!= O_constant
)
8285 || ((imm_expr
.X_add_number
< 0
8286 || imm_expr
.X_add_number
>= 0x10000)
8287 && imm_expr
.X_op
== O_constant
))
8289 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
8290 !strcmp (insn
->name
, insn
[1].name
))
8292 if (imm_expr
.X_op
== O_constant
8293 || imm_expr
.X_op
== O_big
)
8294 as_bad (_("16 bit expression not in range 0..65535"));
8302 /* The upper bound should be 0x8000, but
8303 unfortunately the MIPS assembler accepts numbers
8304 from 0x8000 to 0xffff and sign extends them, and
8305 we want to be compatible. We only permit this
8306 extended range for an instruction which does not
8307 provide any further alternates, since those
8308 alternates may handle other cases. People should
8309 use the numbers they mean, rather than relying on
8310 a mysterious sign extension. */
8311 more
= (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
8312 strcmp (insn
->name
, insn
[1].name
) == 0);
8317 if ((c
== S_EX_NONE
&& imm_expr
.X_op
!= O_constant
)
8318 || ((imm_expr
.X_add_number
< -0x8000
8319 || imm_expr
.X_add_number
>= max
)
8320 && imm_expr
.X_op
== O_constant
)
8322 && imm_expr
.X_add_number
< 0
8324 && imm_expr
.X_unsigned
8325 && sizeof (imm_expr
.X_add_number
) <= 4))
8329 if (imm_expr
.X_op
== O_constant
8330 || imm_expr
.X_op
== O_big
)
8331 as_bad (_("16 bit expression not in range -32768..32767"));
8337 case 'o': /* 16 bit offset */
8338 c
= my_getSmallExpression (&offset_expr
, s
);
8340 /* If this value won't fit into a 16 bit offset, then go
8341 find a macro that will generate the 32 bit offset
8344 && (offset_expr
.X_op
!= O_constant
8345 || offset_expr
.X_add_number
>= 0x8000
8346 || offset_expr
.X_add_number
< -0x8000))
8351 if (offset_expr
.X_op
!= O_constant
)
8353 offset_expr
.X_add_number
=
8354 (offset_expr
.X_add_number
>> 16) & 0xffff;
8356 *offset_reloc
= BFD_RELOC_LO16
;
8360 case 'p': /* pc relative offset */
8361 if (mips_pic
== EMBEDDED_PIC
)
8362 *offset_reloc
= BFD_RELOC_16_PCREL_S2
;
8364 *offset_reloc
= BFD_RELOC_16_PCREL
;
8365 my_getExpression (&offset_expr
, s
);
8369 case 'u': /* upper 16 bits */
8370 c
= my_getSmallExpression (&imm_expr
, s
);
8371 *imm_reloc
= BFD_RELOC_LO16
;
8376 if (imm_expr
.X_op
== O_constant
)
8377 imm_expr
.X_add_number
=
8378 (imm_expr
.X_add_number
>> 16) & 0xffff;
8379 else if (c
== S_EX_HI
)
8381 *imm_reloc
= BFD_RELOC_HI16_S
;
8382 imm_unmatched_hi
= true;
8385 else if (c
== S_EX_HIGHEST
)
8386 *imm_reloc
= BFD_RELOC_MIPS_HIGHEST
;
8387 else if (c
== S_EX_GP_REL
)
8389 /* This occurs in NewABI only. */
8390 c
= my_getSmallExpression (&imm_expr
, s
);
8392 as_bad (_("bad composition of relocations"));
8395 c
= my_getSmallExpression (&imm_expr
, s
);
8397 as_bad (_("bad composition of relocations"));
8400 imm_reloc
[0] = BFD_RELOC_GPREL16
;
8401 imm_reloc
[1] = BFD_RELOC_MIPS_SUB
;
8402 imm_reloc
[2] = BFD_RELOC_HI16_S
;
8408 *imm_reloc
= BFD_RELOC_HI16
;
8410 else if (imm_expr
.X_op
== O_constant
)
8411 imm_expr
.X_add_number
&= 0xffff;
8413 if (imm_expr
.X_op
== O_constant
8414 && (imm_expr
.X_add_number
< 0
8415 || imm_expr
.X_add_number
>= 0x10000))
8416 as_bad (_("lui expression not in range 0..65535"));
8420 case 'a': /* 26 bit address */
8421 my_getExpression (&offset_expr
, s
);
8423 *offset_reloc
= BFD_RELOC_MIPS_JMP
;
8426 case 'N': /* 3 bit branch condition code */
8427 case 'M': /* 3 bit compare condition code */
8428 if (strncmp (s
, "$fcc", 4) != 0)
8438 while (ISDIGIT (*s
));
8440 as_bad (_("invalid condition code register $fcc%d"), regno
);
8442 ip
->insn_opcode
|= regno
<< OP_SH_BCC
;
8444 ip
->insn_opcode
|= regno
<< OP_SH_CCC
;
8448 if (s
[0] == '0' && (s
[1] == 'x' || s
[1] == 'X'))
8459 while (ISDIGIT (*s
));
8462 c
= 8; /* Invalid sel value. */
8465 as_bad (_("invalid coprocessor sub-selection value (0-7)"));
8466 ip
->insn_opcode
|= c
;
8470 as_bad (_("bad char = '%c'\n"), *args
);
8475 /* Args don't match. */
8476 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
8477 !strcmp (insn
->name
, insn
[1].name
))
8481 insn_error
= _("illegal operands");
8486 insn_error
= _("illegal operands");
8491 /* This routine assembles an instruction into its binary format when
8492 assembling for the mips16. As a side effect, it sets one of the
8493 global variables imm_reloc or offset_reloc to the type of
8494 relocation to do if one of the operands is an address expression.
8495 It also sets mips16_small and mips16_ext if the user explicitly
8496 requested a small or extended instruction. */
8501 struct mips_cl_insn
*ip
;
8505 struct mips_opcode
*insn
;
8508 unsigned int lastregno
= 0;
8513 mips16_small
= false;
8516 for (s
= str
; ISLOWER (*s
); ++s
)
8528 if (s
[1] == 't' && s
[2] == ' ')
8531 mips16_small
= true;
8535 else if (s
[1] == 'e' && s
[2] == ' ')
8544 insn_error
= _("unknown opcode");
8548 if (mips_opts
.noautoextend
&& ! mips16_ext
)
8549 mips16_small
= true;
8551 if ((insn
= (struct mips_opcode
*) hash_find (mips16_op_hash
, str
)) == NULL
)
8553 insn_error
= _("unrecognized opcode");
8560 assert (strcmp (insn
->name
, str
) == 0);
8563 ip
->insn_opcode
= insn
->match
;
8564 ip
->use_extend
= false;
8565 imm_expr
.X_op
= O_absent
;
8566 imm_reloc
[0] = BFD_RELOC_UNUSED
;
8567 imm_reloc
[1] = BFD_RELOC_UNUSED
;
8568 imm_reloc
[2] = BFD_RELOC_UNUSED
;
8569 offset_expr
.X_op
= O_absent
;
8570 offset_reloc
[0] = BFD_RELOC_UNUSED
;
8571 offset_reloc
[1] = BFD_RELOC_UNUSED
;
8572 offset_reloc
[2] = BFD_RELOC_UNUSED
;
8573 for (args
= insn
->args
; 1; ++args
)
8580 /* In this switch statement we call break if we did not find
8581 a match, continue if we did find a match, or return if we
8590 /* Stuff the immediate value in now, if we can. */
8591 if (imm_expr
.X_op
== O_constant
8592 && *imm_reloc
> BFD_RELOC_UNUSED
8593 && insn
->pinfo
!= INSN_MACRO
)
8595 mips16_immed (NULL
, 0, *imm_reloc
- BFD_RELOC_UNUSED
,
8596 imm_expr
.X_add_number
, true, mips16_small
,
8597 mips16_ext
, &ip
->insn_opcode
,
8598 &ip
->use_extend
, &ip
->extend
);
8599 imm_expr
.X_op
= O_absent
;
8600 *imm_reloc
= BFD_RELOC_UNUSED
;
8614 ip
->insn_opcode
|= lastregno
<< MIPS16OP_SH_RX
;
8617 ip
->insn_opcode
|= lastregno
<< MIPS16OP_SH_RY
;
8633 ip
->insn_opcode
|= lastregno
<< MIPS16OP_SH_RX
;
8635 ip
->insn_opcode
|= lastregno
<< MIPS16OP_SH_RY
;
8662 while (ISDIGIT (*s
));
8665 as_bad (_("invalid register number (%d)"), regno
);
8671 if (s
[1] == 'f' && s
[2] == 'p')
8676 else if (s
[1] == 's' && s
[2] == 'p')
8681 else if (s
[1] == 'g' && s
[2] == 'p')
8686 else if (s
[1] == 'a' && s
[2] == 't')
8691 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '0')
8696 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '1')
8709 if (c
== 'v' || c
== 'w')
8711 regno
= mips16_to_32_reg_map
[lastregno
];
8725 regno
= mips32_to_16_reg_map
[regno
];
8730 regno
= ILLEGAL_REG
;
8735 regno
= ILLEGAL_REG
;
8740 regno
= ILLEGAL_REG
;
8745 if (regno
== AT
&& ! mips_opts
.noat
)
8746 as_warn (_("used $at without \".set noat\""));
8753 if (regno
== ILLEGAL_REG
)
8760 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_RX
;
8764 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_RY
;
8767 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_RZ
;
8770 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_MOVE32Z
;
8776 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_REGR32
;
8779 regno
= ((regno
& 7) << 2) | ((regno
& 0x18) >> 3);
8780 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_REG32R
;
8790 if (strncmp (s
, "$pc", 3) == 0)
8814 && strncmp (s
+ 1, "gprel(", sizeof "gprel(" - 1) == 0)
8816 /* This is %gprel(SYMBOL). We need to read SYMBOL,
8817 and generate the appropriate reloc. If the text
8818 inside %gprel is not a symbol name with an
8819 optional offset, then we generate a normal reloc
8820 and will probably fail later. */
8821 my_getExpression (&imm_expr
, s
+ sizeof "%gprel" - 1);
8822 if (imm_expr
.X_op
== O_symbol
)
8825 *imm_reloc
= BFD_RELOC_MIPS16_GPREL
;
8827 ip
->use_extend
= true;
8834 /* Just pick up a normal expression. */
8835 my_getExpression (&imm_expr
, s
);
8838 if (imm_expr
.X_op
== O_register
)
8840 /* What we thought was an expression turned out to
8843 if (s
[0] == '(' && args
[1] == '(')
8845 /* It looks like the expression was omitted
8846 before a register indirection, which means
8847 that the expression is implicitly zero. We
8848 still set up imm_expr, so that we handle
8849 explicit extensions correctly. */
8850 imm_expr
.X_op
= O_constant
;
8851 imm_expr
.X_add_number
= 0;
8852 *imm_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
8859 /* We need to relax this instruction. */
8860 *imm_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
8869 /* We use offset_reloc rather than imm_reloc for the PC
8870 relative operands. This lets macros with both
8871 immediate and address operands work correctly. */
8872 my_getExpression (&offset_expr
, s
);
8874 if (offset_expr
.X_op
== O_register
)
8877 /* We need to relax this instruction. */
8878 *offset_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
8882 case '6': /* break code */
8883 my_getExpression (&imm_expr
, s
);
8884 check_absolute_expr (ip
, &imm_expr
);
8885 if ((unsigned long) imm_expr
.X_add_number
> 63)
8887 as_warn (_("Invalid value for `%s' (%lu)"),
8889 (unsigned long) imm_expr
.X_add_number
);
8890 imm_expr
.X_add_number
&= 0x3f;
8892 ip
->insn_opcode
|= imm_expr
.X_add_number
<< MIPS16OP_SH_IMM6
;
8893 imm_expr
.X_op
= O_absent
;
8897 case 'a': /* 26 bit address */
8898 my_getExpression (&offset_expr
, s
);
8900 *offset_reloc
= BFD_RELOC_MIPS16_JMP
;
8901 ip
->insn_opcode
<<= 16;
8904 case 'l': /* register list for entry macro */
8905 case 'L': /* register list for exit macro */
8915 int freg
, reg1
, reg2
;
8917 while (*s
== ' ' || *s
== ',')
8921 as_bad (_("can't parse register list"));
8933 while (ISDIGIT (*s
))
8955 as_bad (_("invalid register list"));
8960 while (ISDIGIT (*s
))
8967 if (freg
&& reg1
== 0 && reg2
== 0 && c
== 'L')
8972 else if (freg
&& reg1
== 0 && reg2
== 1 && c
== 'L')
8977 else if (reg1
== 4 && reg2
>= 4 && reg2
<= 7 && c
!= 'L')
8978 mask
|= (reg2
- 3) << 3;
8979 else if (reg1
== 16 && reg2
>= 16 && reg2
<= 17)
8980 mask
|= (reg2
- 15) << 1;
8981 else if (reg1
== 31 && reg2
== 31)
8985 as_bad (_("invalid register list"));
8989 /* The mask is filled in in the opcode table for the
8990 benefit of the disassembler. We remove it before
8991 applying the actual mask. */
8992 ip
->insn_opcode
&= ~ ((7 << 3) << MIPS16OP_SH_IMM6
);
8993 ip
->insn_opcode
|= mask
<< MIPS16OP_SH_IMM6
;
8997 case 'e': /* extend code */
8998 my_getExpression (&imm_expr
, s
);
8999 check_absolute_expr (ip
, &imm_expr
);
9000 if ((unsigned long) imm_expr
.X_add_number
> 0x7ff)
9002 as_warn (_("Invalid value for `%s' (%lu)"),
9004 (unsigned long) imm_expr
.X_add_number
);
9005 imm_expr
.X_add_number
&= 0x7ff;
9007 ip
->insn_opcode
|= imm_expr
.X_add_number
;
9008 imm_expr
.X_op
= O_absent
;
9018 /* Args don't match. */
9019 if (insn
+ 1 < &mips16_opcodes
[bfd_mips16_num_opcodes
] &&
9020 strcmp (insn
->name
, insn
[1].name
) == 0)
9027 insn_error
= _("illegal operands");
9033 /* This structure holds information we know about a mips16 immediate
9036 struct mips16_immed_operand
9038 /* The type code used in the argument string in the opcode table. */
9040 /* The number of bits in the short form of the opcode. */
9042 /* The number of bits in the extended form of the opcode. */
9044 /* The amount by which the short form is shifted when it is used;
9045 for example, the sw instruction has a shift count of 2. */
9047 /* The amount by which the short form is shifted when it is stored
9048 into the instruction code. */
9050 /* Non-zero if the short form is unsigned. */
9052 /* Non-zero if the extended form is unsigned. */
9054 /* Non-zero if the value is PC relative. */
9058 /* The mips16 immediate operand types. */
9060 static const struct mips16_immed_operand mips16_immed_operands
[] =
9062 { '<', 3, 5, 0, MIPS16OP_SH_RZ
, 1, 1, 0 },
9063 { '>', 3, 5, 0, MIPS16OP_SH_RX
, 1, 1, 0 },
9064 { '[', 3, 6, 0, MIPS16OP_SH_RZ
, 1, 1, 0 },
9065 { ']', 3, 6, 0, MIPS16OP_SH_RX
, 1, 1, 0 },
9066 { '4', 4, 15, 0, MIPS16OP_SH_IMM4
, 0, 0, 0 },
9067 { '5', 5, 16, 0, MIPS16OP_SH_IMM5
, 1, 0, 0 },
9068 { 'H', 5, 16, 1, MIPS16OP_SH_IMM5
, 1, 0, 0 },
9069 { 'W', 5, 16, 2, MIPS16OP_SH_IMM5
, 1, 0, 0 },
9070 { 'D', 5, 16, 3, MIPS16OP_SH_IMM5
, 1, 0, 0 },
9071 { 'j', 5, 16, 0, MIPS16OP_SH_IMM5
, 0, 0, 0 },
9072 { '8', 8, 16, 0, MIPS16OP_SH_IMM8
, 1, 0, 0 },
9073 { 'V', 8, 16, 2, MIPS16OP_SH_IMM8
, 1, 0, 0 },
9074 { 'C', 8, 16, 3, MIPS16OP_SH_IMM8
, 1, 0, 0 },
9075 { 'U', 8, 16, 0, MIPS16OP_SH_IMM8
, 1, 1, 0 },
9076 { 'k', 8, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 0 },
9077 { 'K', 8, 16, 3, MIPS16OP_SH_IMM8
, 0, 0, 0 },
9078 { 'p', 8, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 1 },
9079 { 'q', 11, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 1 },
9080 { 'A', 8, 16, 2, MIPS16OP_SH_IMM8
, 1, 0, 1 },
9081 { 'B', 5, 16, 3, MIPS16OP_SH_IMM5
, 1, 0, 1 },
9082 { 'E', 5, 16, 2, MIPS16OP_SH_IMM5
, 1, 0, 1 }
9085 #define MIPS16_NUM_IMMED \
9086 (sizeof mips16_immed_operands / sizeof mips16_immed_operands[0])
9088 /* Handle a mips16 instruction with an immediate value. This or's the
9089 small immediate value into *INSN. It sets *USE_EXTEND to indicate
9090 whether an extended value is needed; if one is needed, it sets
9091 *EXTEND to the value. The argument type is TYPE. The value is VAL.
9092 If SMALL is true, an unextended opcode was explicitly requested.
9093 If EXT is true, an extended opcode was explicitly requested. If
9094 WARN is true, warn if EXT does not match reality. */
9097 mips16_immed (file
, line
, type
, val
, warn
, small
, ext
, insn
, use_extend
,
9106 unsigned long *insn
;
9107 boolean
*use_extend
;
9108 unsigned short *extend
;
9110 register const struct mips16_immed_operand
*op
;
9111 int mintiny
, maxtiny
;
9114 op
= mips16_immed_operands
;
9115 while (op
->type
!= type
)
9118 assert (op
< mips16_immed_operands
+ MIPS16_NUM_IMMED
);
9123 if (type
== '<' || type
== '>' || type
== '[' || type
== ']')
9126 maxtiny
= 1 << op
->nbits
;
9131 maxtiny
= (1 << op
->nbits
) - 1;
9136 mintiny
= - (1 << (op
->nbits
- 1));
9137 maxtiny
= (1 << (op
->nbits
- 1)) - 1;
9140 /* Branch offsets have an implicit 0 in the lowest bit. */
9141 if (type
== 'p' || type
== 'q')
9144 if ((val
& ((1 << op
->shift
) - 1)) != 0
9145 || val
< (mintiny
<< op
->shift
)
9146 || val
> (maxtiny
<< op
->shift
))
9151 if (warn
&& ext
&& ! needext
)
9152 as_warn_where (file
, line
,
9153 _("extended operand requested but not required"));
9154 if (small
&& needext
)
9155 as_bad_where (file
, line
, _("invalid unextended operand value"));
9157 if (small
|| (! ext
&& ! needext
))
9161 *use_extend
= false;
9162 insnval
= ((val
>> op
->shift
) & ((1 << op
->nbits
) - 1));
9163 insnval
<<= op
->op_shift
;
9168 long minext
, maxext
;
9174 maxext
= (1 << op
->extbits
) - 1;
9178 minext
= - (1 << (op
->extbits
- 1));
9179 maxext
= (1 << (op
->extbits
- 1)) - 1;
9181 if (val
< minext
|| val
> maxext
)
9182 as_bad_where (file
, line
,
9183 _("operand value out of range for instruction"));
9186 if (op
->extbits
== 16)
9188 extval
= ((val
>> 11) & 0x1f) | (val
& 0x7e0);
9191 else if (op
->extbits
== 15)
9193 extval
= ((val
>> 11) & 0xf) | (val
& 0x7f0);
9198 extval
= ((val
& 0x1f) << 6) | (val
& 0x20);
9202 *extend
= (unsigned short) extval
;
9207 static struct percent_op_match
9210 const enum small_ex_type type
;
9214 {"%half", S_EX_HALF
},
9219 {"%gp_rel", S_EX_GP_REL
},
9221 {"%call16", S_EX_CALL16
},
9222 {"%got_disp", S_EX_GOT_DISP
},
9223 {"%got_page", S_EX_GOT_PAGE
},
9224 {"%got_ofst", S_EX_GOT_OFST
},
9225 {"%got_hi", S_EX_GOT_HI
},
9226 {"%got_lo", S_EX_GOT_LO
},
9228 {"%higher", S_EX_HIGHER
},
9229 {"%highest", S_EX_HIGHEST
},
9230 {"%call_hi", S_EX_CALL_HI
},
9231 {"%call_lo", S_EX_CALL_LO
}
9235 /* Parse small expression input. STR gets adjusted to eat up whitespace.
9236 It detects valid "%percent_op(...)" and "($reg)" strings. Percent_op's
9237 can be nested, this is handled by blanking the innermost, parsing the
9238 rest by subsequent calls. */
9241 my_getSmallParser (str
, len
, nestlevel
)
9246 int type
= S_EX_NONE
;
9249 *str
+= strspn (*str
, " \t");
9252 char *b
= *str
+ 1 + strspn (*str
+ 1, " \t");
9255 /* Check for base register. */
9259 && (e
= b
+ strcspn (b
, ") \t"))
9260 && e
- b
> 1 && e
- b
< 4)
9263 && ((b
[1] == 'f' && b
[2] == 'p')
9264 || (b
[1] == 's' && b
[2] == 'p')
9265 || (b
[1] == 'g' && b
[2] == 'p')
9266 || (b
[1] == 'a' && b
[2] == 't')
9268 && ISDIGIT (b
[2]))))
9269 || (ISDIGIT (b
[1])))
9271 *len
= strcspn (*str
, ")") + 1;
9272 return S_EX_REGISTER
;
9276 else if (b
[0] == '%')
9282 /* Some other expression in the braces. */
9283 *len
= strcspn (*str
, ")") + 1;
9285 /* Check for percent_op. */
9286 else if (*str
[0] == '%')
9295 while (ISALPHA (*tmp
) || *tmp
== '_')
9297 *tmp
= TOLOWER (*tmp
);
9300 while (i
< (sizeof (percent_op
) / sizeof (struct percent_op_match
)))
9302 if (strncmp (*str
, percent_op
[i
].str
, strlen (percent_op
[i
].str
)))
9306 type
= percent_op
[i
].type
;
9308 /* Only %hi and %lo are allowed for OldABI. */
9309 if (! HAVE_NEWABI
&& type
!= S_EX_HI
&& type
!= S_EX_LO
)
9312 *len
= strlen (percent_op
[i
].str
);
9319 /* Any other expression. */
9324 my_getSmallExpression (ep
, str
)
9328 static char *oldstr
= NULL
;
9334 /* Don't update oldstr if the last call had nested percent_op's. */
9341 c
= my_getSmallParser (&str
, &len
, &nest_level
);
9342 if (c
!= S_EX_NONE
&& c
!= S_EX_REGISTER
)
9345 while (c
!= S_EX_NONE
&& c
!= S_EX_REGISTER
);
9347 /* A percent_op was encountered. */
9350 /* Don't try to get an expression if it is already blanked out. */
9351 if (*(str
+ strspn (str
+ 1, " )")) != ')')
9355 save
= *(str
+ len
);
9356 *(str
+ len
) = '\0';
9357 my_getExpression (ep
, str
);
9358 *(str
+ len
) = save
;
9362 /* blank out including the % sign. */
9363 char *p
= strrchr (oldstr
, '%');
9364 memset (p
, ' ', str
- p
+ len
);
9369 expr_end
= strchr (str
, ')') + 1;
9373 else if (c
== S_EX_NONE
)
9375 my_getExpression (ep
, str
);
9377 else if (c
== S_EX_REGISTER
)
9379 ep
->X_op
= O_constant
;
9381 ep
->X_add_symbol
= NULL
;
9382 ep
->X_op_symbol
= NULL
;
9383 ep
->X_add_number
= 0;
9387 as_fatal(_("internal error"));
9390 if (nest_level
<= 1)
9397 my_getExpression (ep
, str
)
9404 save_in
= input_line_pointer
;
9405 input_line_pointer
= str
;
9407 expr_end
= input_line_pointer
;
9408 input_line_pointer
= save_in
;
9410 /* If we are in mips16 mode, and this is an expression based on `.',
9411 then we bump the value of the symbol by 1 since that is how other
9412 text symbols are handled. We don't bother to handle complex
9413 expressions, just `.' plus or minus a constant. */
9414 if (mips_opts
.mips16
9415 && ep
->X_op
== O_symbol
9416 && strcmp (S_GET_NAME (ep
->X_add_symbol
), FAKE_LABEL_NAME
) == 0
9417 && S_GET_SEGMENT (ep
->X_add_symbol
) == now_seg
9418 && symbol_get_frag (ep
->X_add_symbol
) == frag_now
9419 && symbol_constant_p (ep
->X_add_symbol
)
9420 && (val
= S_GET_VALUE (ep
->X_add_symbol
)) == frag_now_fix ())
9421 S_SET_VALUE (ep
->X_add_symbol
, val
+ 1);
9424 /* Turn a string in input_line_pointer into a floating point constant
9425 of type TYPE, and store the appropriate bytes in *LITP. The number
9426 of LITTLENUMS emitted is stored in *SIZEP. An error message is
9427 returned, or NULL on OK. */
9430 md_atof (type
, litP
, sizeP
)
9436 LITTLENUM_TYPE words
[4];
9452 return _("bad call to md_atof");
9455 t
= atof_ieee (input_line_pointer
, type
, words
);
9457 input_line_pointer
= t
;
9461 if (! target_big_endian
)
9463 for (i
= prec
- 1; i
>= 0; i
--)
9465 md_number_to_chars (litP
, (valueT
) words
[i
], 2);
9471 for (i
= 0; i
< prec
; i
++)
9473 md_number_to_chars (litP
, (valueT
) words
[i
], 2);
9482 md_number_to_chars (buf
, val
, n
)
9487 if (target_big_endian
)
9488 number_to_chars_bigendian (buf
, val
, n
);
9490 number_to_chars_littleendian (buf
, val
, n
);
9494 static int support_64bit_objects(void)
9496 const char **list
, **l
;
9498 list
= bfd_target_list ();
9499 for (l
= list
; *l
!= NULL
; l
++)
9501 /* This is traditional mips */
9502 if (strcmp (*l
, "elf64-tradbigmips") == 0
9503 || strcmp (*l
, "elf64-tradlittlemips") == 0)
9505 if (strcmp (*l
, "elf64-bigmips") == 0
9506 || strcmp (*l
, "elf64-littlemips") == 0)
9510 return (*l
!= NULL
);
9512 #endif /* OBJ_ELF */
9514 CONST
char *md_shortopts
= "nO::g::G:";
9516 struct option md_longopts
[] =
9518 #define OPTION_MIPS1 (OPTION_MD_BASE + 1)
9519 {"mips0", no_argument
, NULL
, OPTION_MIPS1
},
9520 {"mips1", no_argument
, NULL
, OPTION_MIPS1
},
9521 #define OPTION_MIPS2 (OPTION_MD_BASE + 2)
9522 {"mips2", no_argument
, NULL
, OPTION_MIPS2
},
9523 #define OPTION_MIPS3 (OPTION_MD_BASE + 3)
9524 {"mips3", no_argument
, NULL
, OPTION_MIPS3
},
9525 #define OPTION_MIPS4 (OPTION_MD_BASE + 4)
9526 {"mips4", no_argument
, NULL
, OPTION_MIPS4
},
9527 #define OPTION_MIPS5 (OPTION_MD_BASE + 5)
9528 {"mips5", no_argument
, NULL
, OPTION_MIPS5
},
9529 #define OPTION_MIPS32 (OPTION_MD_BASE + 6)
9530 {"mips32", no_argument
, NULL
, OPTION_MIPS32
},
9531 #define OPTION_MIPS64 (OPTION_MD_BASE + 7)
9532 {"mips64", no_argument
, NULL
, OPTION_MIPS64
},
9533 #define OPTION_MEMBEDDED_PIC (OPTION_MD_BASE + 8)
9534 {"membedded-pic", no_argument
, NULL
, OPTION_MEMBEDDED_PIC
},
9535 #define OPTION_TRAP (OPTION_MD_BASE + 9)
9536 {"trap", no_argument
, NULL
, OPTION_TRAP
},
9537 {"no-break", no_argument
, NULL
, OPTION_TRAP
},
9538 #define OPTION_BREAK (OPTION_MD_BASE + 10)
9539 {"break", no_argument
, NULL
, OPTION_BREAK
},
9540 {"no-trap", no_argument
, NULL
, OPTION_BREAK
},
9541 #define OPTION_EB (OPTION_MD_BASE + 11)
9542 {"EB", no_argument
, NULL
, OPTION_EB
},
9543 #define OPTION_EL (OPTION_MD_BASE + 12)
9544 {"EL", no_argument
, NULL
, OPTION_EL
},
9545 #define OPTION_MIPS16 (OPTION_MD_BASE + 13)
9546 {"mips16", no_argument
, NULL
, OPTION_MIPS16
},
9547 #define OPTION_NO_MIPS16 (OPTION_MD_BASE + 14)
9548 {"no-mips16", no_argument
, NULL
, OPTION_NO_MIPS16
},
9549 #define OPTION_M7000_HILO_FIX (OPTION_MD_BASE + 15)
9550 {"mfix7000", no_argument
, NULL
, OPTION_M7000_HILO_FIX
},
9551 #define OPTION_NO_M7000_HILO_FIX (OPTION_MD_BASE + 16)
9552 {"no-fix-7000", no_argument
, NULL
, OPTION_NO_M7000_HILO_FIX
},
9553 #define OPTION_FP32 (OPTION_MD_BASE + 17)
9554 {"mfp32", no_argument
, NULL
, OPTION_FP32
},
9555 #define OPTION_GP32 (OPTION_MD_BASE + 18)
9556 {"mgp32", no_argument
, NULL
, OPTION_GP32
},
9557 #define OPTION_CONSTRUCT_FLOATS (OPTION_MD_BASE + 19)
9558 {"construct-floats", no_argument
, NULL
, OPTION_CONSTRUCT_FLOATS
},
9559 #define OPTION_NO_CONSTRUCT_FLOATS (OPTION_MD_BASE + 20)
9560 {"no-construct-floats", no_argument
, NULL
, OPTION_NO_CONSTRUCT_FLOATS
},
9561 #define OPTION_MARCH (OPTION_MD_BASE + 21)
9562 {"march", required_argument
, NULL
, OPTION_MARCH
},
9563 #define OPTION_MTUNE (OPTION_MD_BASE + 22)
9564 {"mtune", required_argument
, NULL
, OPTION_MTUNE
},
9565 #define OPTION_MCPU (OPTION_MD_BASE + 23)
9566 {"mcpu", required_argument
, NULL
, OPTION_MCPU
},
9567 #define OPTION_M4650 (OPTION_MD_BASE + 24)
9568 {"m4650", no_argument
, NULL
, OPTION_M4650
},
9569 #define OPTION_NO_M4650 (OPTION_MD_BASE + 25)
9570 {"no-m4650", no_argument
, NULL
, OPTION_NO_M4650
},
9571 #define OPTION_M4010 (OPTION_MD_BASE + 26)
9572 {"m4010", no_argument
, NULL
, OPTION_M4010
},
9573 #define OPTION_NO_M4010 (OPTION_MD_BASE + 27)
9574 {"no-m4010", no_argument
, NULL
, OPTION_NO_M4010
},
9575 #define OPTION_M4100 (OPTION_MD_BASE + 28)
9576 {"m4100", no_argument
, NULL
, OPTION_M4100
},
9577 #define OPTION_NO_M4100 (OPTION_MD_BASE + 29)
9578 {"no-m4100", no_argument
, NULL
, OPTION_NO_M4100
},
9579 #define OPTION_M3900 (OPTION_MD_BASE + 30)
9580 {"m3900", no_argument
, NULL
, OPTION_M3900
},
9581 #define OPTION_NO_M3900 (OPTION_MD_BASE + 31)
9582 {"no-m3900", no_argument
, NULL
, OPTION_NO_M3900
},
9583 #define OPTION_GP64 (OPTION_MD_BASE + 32)
9584 {"mgp64", no_argument
, NULL
, OPTION_GP64
},
9586 #define OPTION_ELF_BASE (OPTION_MD_BASE + 33)
9587 #define OPTION_CALL_SHARED (OPTION_ELF_BASE + 0)
9588 {"KPIC", no_argument
, NULL
, OPTION_CALL_SHARED
},
9589 {"call_shared", no_argument
, NULL
, OPTION_CALL_SHARED
},
9590 #define OPTION_NON_SHARED (OPTION_ELF_BASE + 1)
9591 {"non_shared", no_argument
, NULL
, OPTION_NON_SHARED
},
9592 #define OPTION_XGOT (OPTION_ELF_BASE + 2)
9593 {"xgot", no_argument
, NULL
, OPTION_XGOT
},
9594 #define OPTION_MABI (OPTION_ELF_BASE + 3)
9595 {"mabi", required_argument
, NULL
, OPTION_MABI
},
9596 #define OPTION_32 (OPTION_ELF_BASE + 4)
9597 {"32", no_argument
, NULL
, OPTION_32
},
9598 #define OPTION_N32 (OPTION_ELF_BASE + 5)
9599 {"n32", no_argument
, NULL
, OPTION_N32
},
9600 #define OPTION_64 (OPTION_ELF_BASE + 6)
9601 {"64", no_argument
, NULL
, OPTION_64
},
9602 #endif /* OBJ_ELF */
9603 {NULL
, no_argument
, NULL
, 0}
9605 size_t md_longopts_size
= sizeof (md_longopts
);
9608 md_parse_option (c
, arg
)
9614 case OPTION_CONSTRUCT_FLOATS
:
9615 mips_disable_float_construction
= 0;
9618 case OPTION_NO_CONSTRUCT_FLOATS
:
9619 mips_disable_float_construction
= 1;
9631 target_big_endian
= 1;
9635 target_big_endian
= 0;
9643 if (arg
&& arg
[1] == '0')
9653 mips_debug
= atoi (arg
);
9654 /* When the MIPS assembler sees -g or -g2, it does not do
9655 optimizations which limit full symbolic debugging. We take
9656 that to be equivalent to -O0. */
9657 if (mips_debug
== 2)
9662 mips_opts
.isa
= ISA_MIPS1
;
9666 mips_opts
.isa
= ISA_MIPS2
;
9670 mips_opts
.isa
= ISA_MIPS3
;
9674 mips_opts
.isa
= ISA_MIPS4
;
9678 mips_opts
.isa
= ISA_MIPS5
;
9682 mips_opts
.isa
= ISA_MIPS32
;
9686 mips_opts
.isa
= ISA_MIPS64
;
9693 int cpu
= CPU_UNKNOWN
;
9695 /* Identify the processor type. */
9696 if (strcasecmp (arg
, "default") != 0)
9698 const struct mips_cpu_info
*ci
;
9700 ci
= mips_cpu_info_from_name (arg
);
9701 if (ci
== NULL
|| ci
->is_isa
)
9706 as_fatal (_("invalid architecture -mtune=%s"), arg
);
9709 as_fatal (_("invalid architecture -march=%s"), arg
);
9712 as_fatal (_("invalid architecture -mcpu=%s"), arg
);
9723 if (mips_tune
!= CPU_UNKNOWN
&& mips_tune
!= cpu
)
9724 as_warn(_("A different -mtune= was already specified, is now "
9729 if (mips_arch
!= CPU_UNKNOWN
&& mips_arch
!= cpu
)
9730 as_warn(_("A different -march= was already specified, is now "
9735 if (mips_cpu
!= CPU_UNKNOWN
&& mips_cpu
!= cpu
)
9736 as_warn(_("A different -mcpu= was already specified, is now "
9744 if ((mips_arch
!= CPU_UNKNOWN
&& mips_arch
!= CPU_R4650
)
9745 || (mips_tune
!= CPU_UNKNOWN
&& mips_tune
!= CPU_R4650
))
9746 as_warn(_("A different -march= or -mtune= was already specified, "
9748 mips_arch
= CPU_R4650
;
9749 mips_tune
= CPU_R4650
;
9752 case OPTION_NO_M4650
:
9756 if ((mips_arch
!= CPU_UNKNOWN
&& mips_arch
!= CPU_R4010
)
9757 || (mips_tune
!= CPU_UNKNOWN
&& mips_tune
!= CPU_R4010
))
9758 as_warn(_("A different -march= or -mtune= was already specified, "
9760 mips_arch
= CPU_R4010
;
9761 mips_tune
= CPU_R4010
;
9764 case OPTION_NO_M4010
:
9768 if ((mips_arch
!= CPU_UNKNOWN
&& mips_arch
!= CPU_VR4100
)
9769 || (mips_tune
!= CPU_UNKNOWN
&& mips_tune
!= CPU_VR4100
))
9770 as_warn(_("A different -march= or -mtune= was already specified, "
9772 mips_arch
= CPU_VR4100
;
9773 mips_tune
= CPU_VR4100
;
9776 case OPTION_NO_M4100
:
9780 if ((mips_arch
!= CPU_UNKNOWN
&& mips_arch
!= CPU_R3900
)
9781 || (mips_tune
!= CPU_UNKNOWN
&& mips_tune
!= CPU_R3900
))
9782 as_warn(_("A different -march= or -mtune= was already specified, "
9784 mips_arch
= CPU_R3900
;
9785 mips_tune
= CPU_R3900
;
9788 case OPTION_NO_M3900
:
9792 mips_opts
.mips16
= 1;
9793 mips_no_prev_insn (false);
9796 case OPTION_NO_MIPS16
:
9797 mips_opts
.mips16
= 0;
9798 mips_no_prev_insn (false);
9801 case OPTION_MEMBEDDED_PIC
:
9802 mips_pic
= EMBEDDED_PIC
;
9803 if (USE_GLOBAL_POINTER_OPT
&& g_switch_seen
)
9805 as_bad (_("-G may not be used with embedded PIC code"));
9808 g_switch_value
= 0x7fffffff;
9812 /* When generating ELF code, we permit -KPIC and -call_shared to
9813 select SVR4_PIC, and -non_shared to select no PIC. This is
9814 intended to be compatible with Irix 5. */
9815 case OPTION_CALL_SHARED
:
9816 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
9818 as_bad (_("-call_shared is supported only for ELF format"));
9821 mips_pic
= SVR4_PIC
;
9822 if (g_switch_seen
&& g_switch_value
!= 0)
9824 as_bad (_("-G may not be used with SVR4 PIC code"));
9830 case OPTION_NON_SHARED
:
9831 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
9833 as_bad (_("-non_shared is supported only for ELF format"));
9839 /* The -xgot option tells the assembler to use 32 offsets when
9840 accessing the got in SVR4_PIC mode. It is for Irix
9845 #endif /* OBJ_ELF */
9848 if (! USE_GLOBAL_POINTER_OPT
)
9850 as_bad (_("-G is not supported for this configuration"));
9853 else if (mips_pic
== SVR4_PIC
|| mips_pic
== EMBEDDED_PIC
)
9855 as_bad (_("-G may not be used with SVR4 or embedded PIC code"));
9859 g_switch_value
= atoi (arg
);
9864 /* The -32 and -64 options tell the assembler to output the 32
9865 bit or the 64 bit MIPS ELF format. */
9867 mips_opts
.abi
= O32_ABI
;
9871 mips_opts
.abi
= N32_ABI
;
9875 mips_opts
.abi
= N64_ABI
;
9876 if (! support_64bit_objects())
9877 as_fatal (_("No compiled in support for 64 bit object file format"));
9879 #endif /* OBJ_ELF */
9883 if (mips_opts
.abi
!= O32_ABI
)
9884 mips_opts
.abi
= NO_ABI
;
9889 if (mips_opts
.abi
== O32_ABI
)
9890 mips_opts
.abi
= NO_ABI
;
9895 if (mips_opts
.abi
!= O32_ABI
)
9896 mips_opts
.abi
= NO_ABI
;
9901 if (strcmp (arg
, "32") == 0)
9902 mips_opts
.abi
= O32_ABI
;
9903 else if (strcmp (arg
, "o64") == 0)
9904 mips_opts
.abi
= O64_ABI
;
9905 else if (strcmp (arg
, "n32") == 0)
9906 mips_opts
.abi
= N32_ABI
;
9907 else if (strcmp (arg
, "64") == 0)
9909 mips_opts
.abi
= N64_ABI
;
9910 if (! support_64bit_objects())
9911 as_fatal (_("No compiled in support for 64 bit object file "
9914 else if (strcmp (arg
, "eabi") == 0)
9915 mips_opts
.abi
= EABI_ABI
;
9917 mips_opts
.abi
= NO_ABI
;
9919 #endif /* OBJ_ELF */
9921 case OPTION_M7000_HILO_FIX
:
9922 mips_7000_hilo_fix
= true;
9925 case OPTION_NO_M7000_HILO_FIX
:
9926 mips_7000_hilo_fix
= false;
9937 show (stream
, string
, col_p
, first_p
)
9945 fprintf (stream
, "%24s", "");
9950 fprintf (stream
, ", ");
9954 if (*col_p
+ strlen (string
) > 72)
9956 fprintf (stream
, "\n%24s", "");
9960 fprintf (stream
, "%s", string
);
9961 *col_p
+= strlen (string
);
9967 md_show_usage (stream
)
9972 fprintf (stream
, _("\
9974 -membedded-pic generate embedded position independent code\n\
9975 -EB generate big endian output\n\
9976 -EL generate little endian output\n\
9977 -g, -g2 do not remove unneeded NOPs or swap branches\n\
9978 -G NUM allow referencing objects up to NUM bytes\n\
9979 implicitly with the gp register [default 8]\n"));
9980 fprintf (stream
, _("\
9981 -mips1 generate MIPS ISA I instructions\n\
9982 -mips2 generate MIPS ISA II instructions\n\
9983 -mips3 generate MIPS ISA III instructions\n\
9984 -mips4 generate MIPS ISA IV instructions\n\
9985 -mips5 generate MIPS ISA V instructions\n\
9986 -mips32 generate MIPS32 ISA instructions\n\
9987 -mips64 generate MIPS64 ISA instructions\n\
9988 -march=CPU/-mtune=CPU generate code/schedule for CPU, where CPU is one of:\n"));
9992 show (stream
, "2000", &column
, &first
);
9993 show (stream
, "3000", &column
, &first
);
9994 show (stream
, "3900", &column
, &first
);
9995 show (stream
, "4000", &column
, &first
);
9996 show (stream
, "4010", &column
, &first
);
9997 show (stream
, "4100", &column
, &first
);
9998 show (stream
, "4111", &column
, &first
);
9999 show (stream
, "4300", &column
, &first
);
10000 show (stream
, "4400", &column
, &first
);
10001 show (stream
, "4600", &column
, &first
);
10002 show (stream
, "4650", &column
, &first
);
10003 show (stream
, "5000", &column
, &first
);
10004 show (stream
, "5200", &column
, &first
);
10005 show (stream
, "5230", &column
, &first
);
10006 show (stream
, "5231", &column
, &first
);
10007 show (stream
, "5261", &column
, &first
);
10008 show (stream
, "5721", &column
, &first
);
10009 show (stream
, "6000", &column
, &first
);
10010 show (stream
, "8000", &column
, &first
);
10011 show (stream
, "10000", &column
, &first
);
10012 show (stream
, "12000", &column
, &first
);
10013 show (stream
, "sb1", &column
, &first
);
10014 fputc ('\n', stream
);
10016 fprintf (stream
, _("\
10017 -mCPU equivalent to -march=CPU -mtune=CPU. Deprecated.\n\
10018 -no-mCPU don't generate code specific to CPU.\n\
10019 For -mCPU and -no-mCPU, CPU must be one of:\n"));
10023 show (stream
, "3900", &column
, &first
);
10024 show (stream
, "4010", &column
, &first
);
10025 show (stream
, "4100", &column
, &first
);
10026 show (stream
, "4650", &column
, &first
);
10027 fputc ('\n', stream
);
10029 fprintf (stream
, _("\
10030 -mips16 generate mips16 instructions\n\
10031 -no-mips16 do not generate mips16 instructions\n"));
10032 fprintf (stream
, _("\
10033 -mgp32 use 32-bit GPRs, regardless of the chosen ISA\n\
10034 -mfp32 use 32-bit FPRs, regardless of the chosen ISA\n\
10035 -O0 remove unneeded NOPs, do not swap branches\n\
10036 -O remove unneeded NOPs and swap branches\n\
10037 -n warn about NOPs generated from macros\n\
10038 --[no-]construct-floats [dis]allow floating point values to be constructed\n\
10039 --trap, --no-break trap exception on div by 0 and mult overflow\n\
10040 --break, --no-trap break exception on div by 0 and mult overflow\n"));
10042 fprintf (stream
, _("\
10043 -KPIC, -call_shared generate SVR4 position independent code\n\
10044 -non_shared do not generate position independent code\n\
10045 -xgot assume a 32 bit GOT\n\
10046 -32 create o32 ABI object file (default)\n\
10047 -n32 create n32 ABI object file\n\
10048 -64 create 64 ABI object file\n"));
10053 mips_init_after_args ()
10055 /* initialize opcodes */
10056 bfd_mips_num_opcodes
= bfd_mips_num_builtin_opcodes
;
10057 mips_opcodes
= (struct mips_opcode
*) mips_builtin_opcodes
;
10061 md_pcrel_from (fixP
)
10064 if (OUTPUT_FLAVOR
!= bfd_target_aout_flavour
10065 && fixP
->fx_addsy
!= (symbolS
*) NULL
10066 && ! S_IS_DEFINED (fixP
->fx_addsy
))
10068 /* This makes a branch to an undefined symbol be a branch to the
10069 current location. */
10070 if (mips_pic
== EMBEDDED_PIC
)
10076 /* return the address of the delay slot */
10077 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
10080 /* This is called before the symbol table is processed. In order to
10081 work with gcc when using mips-tfile, we must keep all local labels.
10082 However, in other cases, we want to discard them. If we were
10083 called with -g, but we didn't see any debugging information, it may
10084 mean that gcc is smuggling debugging information through to
10085 mips-tfile, in which case we must generate all local labels. */
10088 mips_frob_file_before_adjust ()
10090 #ifndef NO_ECOFF_DEBUGGING
10091 if (ECOFF_DEBUGGING
10093 && ! ecoff_debugging_seen
)
10094 flag_keep_locals
= 1;
10098 /* Sort any unmatched HI16_S relocs so that they immediately precede
10099 the corresponding LO reloc. This is called before md_apply_fix3 and
10100 tc_gen_reloc. Unmatched HI16_S relocs can only be generated by
10101 explicit use of the %hi modifier. */
10106 struct mips_hi_fixup
*l
;
10108 for (l
= mips_hi_fixup_list
; l
!= NULL
; l
= l
->next
)
10110 segment_info_type
*seginfo
;
10113 assert (l
->fixp
->fx_r_type
== BFD_RELOC_HI16_S
);
10115 /* Check quickly whether the next fixup happens to be a matching
10117 if (l
->fixp
->fx_next
!= NULL
10118 && l
->fixp
->fx_next
->fx_r_type
== BFD_RELOC_LO16
10119 && l
->fixp
->fx_addsy
== l
->fixp
->fx_next
->fx_addsy
10120 && l
->fixp
->fx_offset
== l
->fixp
->fx_next
->fx_offset
)
10123 /* Look through the fixups for this segment for a matching %lo.
10124 When we find one, move the %hi just in front of it. We do
10125 this in two passes. In the first pass, we try to find a
10126 unique %lo. In the second pass, we permit multiple %hi
10127 relocs for a single %lo (this is a GNU extension). */
10128 seginfo
= seg_info (l
->seg
);
10129 for (pass
= 0; pass
< 2; pass
++)
10134 for (f
= seginfo
->fix_root
; f
!= NULL
; f
= f
->fx_next
)
10136 /* Check whether this is a %lo fixup which matches l->fixp. */
10137 if (f
->fx_r_type
== BFD_RELOC_LO16
10138 && f
->fx_addsy
== l
->fixp
->fx_addsy
10139 && f
->fx_offset
== l
->fixp
->fx_offset
10142 || prev
->fx_r_type
!= BFD_RELOC_HI16_S
10143 || prev
->fx_addsy
!= f
->fx_addsy
10144 || prev
->fx_offset
!= f
->fx_offset
))
10148 /* Move l->fixp before f. */
10149 for (pf
= &seginfo
->fix_root
;
10151 pf
= &(*pf
)->fx_next
)
10152 assert (*pf
!= NULL
);
10154 *pf
= l
->fixp
->fx_next
;
10156 l
->fixp
->fx_next
= f
;
10158 seginfo
->fix_root
= l
->fixp
;
10160 prev
->fx_next
= l
->fixp
;
10171 #if 0 /* GCC code motion plus incomplete dead code elimination
10172 can leave a %hi without a %lo. */
10174 as_warn_where (l
->fixp
->fx_file
, l
->fixp
->fx_line
,
10175 _("Unmatched %%hi reloc"));
10181 /* When generating embedded PIC code we need to use a special
10182 relocation to represent the difference of two symbols in the .text
10183 section (switch tables use a difference of this sort). See
10184 include/coff/mips.h for details. This macro checks whether this
10185 fixup requires the special reloc. */
10186 #define SWITCH_TABLE(fixp) \
10187 ((fixp)->fx_r_type == BFD_RELOC_32 \
10188 && OUTPUT_FLAVOR != bfd_target_elf_flavour \
10189 && (fixp)->fx_addsy != NULL \
10190 && (fixp)->fx_subsy != NULL \
10191 && S_GET_SEGMENT ((fixp)->fx_addsy) == text_section \
10192 && S_GET_SEGMENT ((fixp)->fx_subsy) == text_section)
10194 /* When generating embedded PIC code we must keep all PC relative
10195 relocations, in case the linker has to relax a call. We also need
10196 to keep relocations for switch table entries.
10198 We may have combined relocations without symbols in the N32/N64 ABI.
10199 We have to prevent gas from dropping them. */
10202 mips_force_relocation (fixp
)
10205 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
10206 || fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
10210 && S_GET_SEGMENT (fixp
->fx_addsy
) == bfd_abs_section_ptr
10211 && (fixp
->fx_r_type
== BFD_RELOC_MIPS_SUB
10212 || fixp
->fx_r_type
== BFD_RELOC_HI16_S
10213 || fixp
->fx_r_type
== BFD_RELOC_LO16
))
10216 return (mips_pic
== EMBEDDED_PIC
10218 || SWITCH_TABLE (fixp
)
10219 || fixp
->fx_r_type
== BFD_RELOC_PCREL_HI16_S
10220 || fixp
->fx_r_type
== BFD_RELOC_PCREL_LO16
));
10225 mips_need_elf_addend_fixup (fixP
)
10228 return (S_GET_OTHER (fixP
->fx_addsy
) == STO_MIPS16
10229 || ((S_IS_WEAK (fixP
->fx_addsy
)
10230 || S_IS_EXTERN (fixP
->fx_addsy
))
10231 && !S_IS_COMMON (fixP
->fx_addsy
))
10232 || (symbol_used_in_reloc_p (fixP
->fx_addsy
)
10233 && (((bfd_get_section_flags (stdoutput
,
10234 S_GET_SEGMENT (fixP
->fx_addsy
))
10235 & SEC_LINK_ONCE
) != 0)
10236 || !strncmp (segment_name (S_GET_SEGMENT (fixP
->fx_addsy
)),
10238 sizeof (".gnu.linkonce") - 1))));
10242 /* Apply a fixup to the object file. */
10245 md_apply_fix3 (fixP
, valP
, seg
)
10248 segT seg ATTRIBUTE_UNUSED
;
10250 unsigned char *buf
;
10254 assert (fixP
->fx_size
== 4
10255 || fixP
->fx_r_type
== BFD_RELOC_16
10256 || fixP
->fx_r_type
== BFD_RELOC_32
10257 || fixP
->fx_r_type
== BFD_RELOC_MIPS_JMP
10258 || fixP
->fx_r_type
== BFD_RELOC_HI16_S
10259 || fixP
->fx_r_type
== BFD_RELOC_LO16
10260 || fixP
->fx_r_type
== BFD_RELOC_GPREL16
10261 || fixP
->fx_r_type
== BFD_RELOC_MIPS_LITERAL
10262 || fixP
->fx_r_type
== BFD_RELOC_GPREL32
10263 || fixP
->fx_r_type
== BFD_RELOC_64
10264 || fixP
->fx_r_type
== BFD_RELOC_CTOR
10265 || fixP
->fx_r_type
== BFD_RELOC_MIPS_SUB
10266 || fixP
->fx_r_type
== BFD_RELOC_MIPS_HIGHEST
10267 || fixP
->fx_r_type
== BFD_RELOC_MIPS_HIGHER
10268 || fixP
->fx_r_type
== BFD_RELOC_MIPS_SCN_DISP
10269 || fixP
->fx_r_type
== BFD_RELOC_MIPS_REL16
10270 || fixP
->fx_r_type
== BFD_RELOC_MIPS_RELGOT
10271 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
10272 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
);
10276 /* If we aren't adjusting this fixup to be against the section
10277 symbol, we need to adjust the value. */
10279 if (fixP
->fx_addsy
!= NULL
&& OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
10281 if (mips_need_elf_addend_fixup (fixP
))
10283 valueT symval
= S_GET_VALUE (fixP
->fx_addsy
);
10286 if (value
!= 0 && ! fixP
->fx_pcrel
)
10288 /* In this case, the bfd_install_relocation routine will
10289 incorrectly add the symbol value back in. We just want
10290 the addend to appear in the object file. */
10293 /* Make sure the addend is still non-zero. If it became zero
10294 after the last operation, set it to a spurious value and
10295 subtract the same value from the object file's contents. */
10300 /* The in-place addends for LO16 relocations are signed;
10301 leave the matching HI16 in-place addends as zero. */
10302 if (fixP
->fx_r_type
!= BFD_RELOC_HI16_S
)
10304 reloc_howto_type
*howto
;
10305 bfd_vma contents
, mask
, field
;
10307 howto
= bfd_reloc_type_lookup (stdoutput
,
10310 contents
= bfd_get_bits (fixP
->fx_frag
->fr_literal
10313 target_big_endian
);
10315 /* MASK has bits set where the relocation should go.
10316 FIELD is -value, shifted into the appropriate place
10317 for this relocation. */
10318 mask
= 1 << (howto
->bitsize
- 1);
10319 mask
= (((mask
- 1) << 1) | 1) << howto
->bitpos
;
10320 field
= (-value
>> howto
->rightshift
) << howto
->bitpos
;
10322 bfd_put_bits ((field
& mask
) | (contents
& ~mask
),
10323 fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
,
10325 target_big_endian
);
10331 /* This code was generated using trial and error and so is
10332 fragile and not trustworthy. If you change it, you should
10333 rerun the elf-rel, elf-rel2, and empic testcases and ensure
10334 they still pass. */
10335 if (fixP
->fx_pcrel
|| fixP
->fx_subsy
!= NULL
)
10337 value
+= fixP
->fx_frag
->fr_address
+ fixP
->fx_where
;
10339 /* BFD's REL handling, for MIPS, is _very_ weird.
10340 This gives the right results, but it can't possibly
10341 be the way things are supposed to work. */
10342 if ((fixP
->fx_r_type
!= BFD_RELOC_16_PCREL
10343 && fixP
->fx_r_type
!= BFD_RELOC_16_PCREL_S2
)
10344 || S_GET_SEGMENT (fixP
->fx_addsy
) != undefined_section
)
10345 value
+= fixP
->fx_frag
->fr_address
+ fixP
->fx_where
;
10350 fixP
->fx_addnumber
= value
; /* Remember value for tc_gen_reloc. */
10352 if (fixP
->fx_addsy
== NULL
&& ! fixP
->fx_pcrel
)
10355 switch (fixP
->fx_r_type
)
10357 case BFD_RELOC_MIPS_JMP
:
10358 case BFD_RELOC_MIPS_SHIFT5
:
10359 case BFD_RELOC_MIPS_SHIFT6
:
10360 case BFD_RELOC_MIPS_GOT_DISP
:
10361 case BFD_RELOC_MIPS_GOT_PAGE
:
10362 case BFD_RELOC_MIPS_GOT_OFST
:
10363 case BFD_RELOC_MIPS_SUB
:
10364 case BFD_RELOC_MIPS_INSERT_A
:
10365 case BFD_RELOC_MIPS_INSERT_B
:
10366 case BFD_RELOC_MIPS_DELETE
:
10367 case BFD_RELOC_MIPS_HIGHEST
:
10368 case BFD_RELOC_MIPS_HIGHER
:
10369 case BFD_RELOC_MIPS_SCN_DISP
:
10370 case BFD_RELOC_MIPS_REL16
:
10371 case BFD_RELOC_MIPS_RELGOT
:
10372 case BFD_RELOC_MIPS_JALR
:
10373 case BFD_RELOC_HI16
:
10374 case BFD_RELOC_HI16_S
:
10375 case BFD_RELOC_GPREL16
:
10376 case BFD_RELOC_MIPS_LITERAL
:
10377 case BFD_RELOC_MIPS_CALL16
:
10378 case BFD_RELOC_MIPS_GOT16
:
10379 case BFD_RELOC_GPREL32
:
10380 case BFD_RELOC_MIPS_GOT_HI16
:
10381 case BFD_RELOC_MIPS_GOT_LO16
:
10382 case BFD_RELOC_MIPS_CALL_HI16
:
10383 case BFD_RELOC_MIPS_CALL_LO16
:
10384 case BFD_RELOC_MIPS16_GPREL
:
10385 if (fixP
->fx_pcrel
)
10386 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
10387 _("Invalid PC relative reloc"));
10388 /* Nothing needed to do. The value comes from the reloc entry */
10391 case BFD_RELOC_MIPS16_JMP
:
10392 /* We currently always generate a reloc against a symbol, which
10393 means that we don't want an addend even if the symbol is
10395 fixP
->fx_addnumber
= 0;
10398 case BFD_RELOC_PCREL_HI16_S
:
10399 /* The addend for this is tricky if it is internal, so we just
10400 do everything here rather than in bfd_install_relocation. */
10401 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
10406 && (symbol_get_bfdsym (fixP
->fx_addsy
)->flags
& BSF_SECTION_SYM
) == 0)
10408 /* For an external symbol adjust by the address to make it
10409 pcrel_offset. We use the address of the RELLO reloc
10410 which follows this one. */
10411 value
+= (fixP
->fx_next
->fx_frag
->fr_address
10412 + fixP
->fx_next
->fx_where
);
10414 value
= ((value
+ 0x8000) >> 16) & 0xffff;
10415 buf
= (unsigned char *) fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
10416 if (target_big_endian
)
10418 md_number_to_chars (buf
, value
, 2);
10421 case BFD_RELOC_PCREL_LO16
:
10422 /* The addend for this is tricky if it is internal, so we just
10423 do everything here rather than in bfd_install_relocation. */
10424 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
10429 && (symbol_get_bfdsym (fixP
->fx_addsy
)->flags
& BSF_SECTION_SYM
) == 0)
10430 value
+= fixP
->fx_frag
->fr_address
+ fixP
->fx_where
;
10431 buf
= (unsigned char *) fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
10432 if (target_big_endian
)
10434 md_number_to_chars (buf
, value
, 2);
10438 /* This is handled like BFD_RELOC_32, but we output a sign
10439 extended value if we are only 32 bits. */
10441 || (mips_pic
== EMBEDDED_PIC
&& SWITCH_TABLE (fixP
)))
10443 if (8 <= sizeof (valueT
))
10444 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
,
10451 w1
= w2
= fixP
->fx_where
;
10452 if (target_big_endian
)
10456 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ w1
, value
, 4);
10457 if ((value
& 0x80000000) != 0)
10461 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ w2
, hiv
, 4);
10466 case BFD_RELOC_RVA
:
10468 /* If we are deleting this reloc entry, we must fill in the
10469 value now. This can happen if we have a .word which is not
10470 resolved when it appears but is later defined. We also need
10471 to fill in the value if this is an embedded PIC switch table
10474 || (mips_pic
== EMBEDDED_PIC
&& SWITCH_TABLE (fixP
)))
10475 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
,
10480 /* If we are deleting this reloc entry, we must fill in the
10482 assert (fixP
->fx_size
== 2);
10484 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
,
10488 case BFD_RELOC_LO16
:
10489 /* When handling an embedded PIC switch statement, we can wind
10490 up deleting a LO16 reloc. See the 'o' case in mips_ip. */
10493 if (value
+ 0x8000 > 0xffff)
10494 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
10495 _("relocation overflow"));
10496 buf
= (unsigned char *) fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
10497 if (target_big_endian
)
10499 md_number_to_chars (buf
, value
, 2);
10503 case BFD_RELOC_16_PCREL_S2
:
10504 if ((value
& 0x3) != 0)
10505 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
10506 _("Branch to odd address (%lx)"), (long) value
);
10508 /* Fall through. */
10510 case BFD_RELOC_16_PCREL
:
10512 * We need to save the bits in the instruction since fixup_segment()
10513 * might be deleting the relocation entry (i.e., a branch within
10514 * the current segment).
10516 if (!fixP
->fx_done
&& value
!= 0)
10518 /* If 'value' is zero, the remaining reloc code won't actually
10519 do the store, so it must be done here. This is probably
10520 a bug somewhere. */
10521 if (!fixP
->fx_done
)
10522 value
-= fixP
->fx_frag
->fr_address
+ fixP
->fx_where
;
10524 value
= (offsetT
) value
>> 2;
10526 /* update old instruction data */
10527 buf
= (unsigned char *) (fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
);
10528 if (target_big_endian
)
10529 insn
= (buf
[0] << 24) | (buf
[1] << 16) | (buf
[2] << 8) | buf
[3];
10531 insn
= (buf
[3] << 24) | (buf
[2] << 16) | (buf
[1] << 8) | buf
[0];
10533 if (value
+ 0x8000 <= 0xffff)
10534 insn
|= value
& 0xffff;
10537 /* The branch offset is too large. If this is an
10538 unconditional branch, and we are not generating PIC code,
10539 we can convert it to an absolute jump instruction. */
10540 if (mips_pic
== NO_PIC
10542 && fixP
->fx_frag
->fr_address
>= text_section
->vma
10543 && (fixP
->fx_frag
->fr_address
10544 < text_section
->vma
+ text_section
->_raw_size
)
10545 && ((insn
& 0xffff0000) == 0x10000000 /* beq $0,$0 */
10546 || (insn
& 0xffff0000) == 0x04010000 /* bgez $0 */
10547 || (insn
& 0xffff0000) == 0x04110000)) /* bgezal $0 */
10549 if ((insn
& 0xffff0000) == 0x04110000) /* bgezal $0 */
10550 insn
= 0x0c000000; /* jal */
10552 insn
= 0x08000000; /* j */
10553 fixP
->fx_r_type
= BFD_RELOC_MIPS_JMP
;
10555 fixP
->fx_addsy
= section_symbol (text_section
);
10556 fixP
->fx_addnumber
= (value
<< 2) + md_pcrel_from (fixP
);
10560 /* FIXME. It would be possible in principle to handle
10561 conditional branches which overflow. They could be
10562 transformed into a branch around a jump. This would
10563 require setting up variant frags for each different
10564 branch type. The native MIPS assembler attempts to
10565 handle these cases, but it appears to do it
10567 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
10568 _("Branch out of range"));
10572 md_number_to_chars ((char *) buf
, (valueT
) insn
, 4);
10575 case BFD_RELOC_VTABLE_INHERIT
:
10578 && !S_IS_DEFINED (fixP
->fx_addsy
)
10579 && !S_IS_WEAK (fixP
->fx_addsy
))
10580 S_SET_WEAK (fixP
->fx_addsy
);
10583 case BFD_RELOC_VTABLE_ENTRY
:
10597 const struct mips_opcode
*p
;
10598 int treg
, sreg
, dreg
, shamt
;
10603 for (i
= 0; i
< NUMOPCODES
; ++i
)
10605 p
= &mips_opcodes
[i
];
10606 if (((oc
& p
->mask
) == p
->match
) && (p
->pinfo
!= INSN_MACRO
))
10608 printf ("%08lx %s\t", oc
, p
->name
);
10609 treg
= (oc
>> 16) & 0x1f;
10610 sreg
= (oc
>> 21) & 0x1f;
10611 dreg
= (oc
>> 11) & 0x1f;
10612 shamt
= (oc
>> 6) & 0x1f;
10614 for (args
= p
->args
;; ++args
)
10625 printf ("%c", *args
);
10629 assert (treg
== sreg
);
10630 printf ("$%d,$%d", treg
, sreg
);
10635 printf ("$%d", dreg
);
10640 printf ("$%d", treg
);
10644 printf ("0x%x", treg
);
10649 printf ("$%d", sreg
);
10653 printf ("0x%08lx", oc
& 0x1ffffff);
10660 printf ("%d", imm
);
10665 printf ("$%d", shamt
);
10676 printf (_("%08lx UNDEFINED\n"), oc
);
10687 name
= input_line_pointer
;
10688 c
= get_symbol_end ();
10689 p
= (symbolS
*) symbol_find_or_make (name
);
10690 *input_line_pointer
= c
;
10694 /* Align the current frag to a given power of two. The MIPS assembler
10695 also automatically adjusts any preceding label. */
10698 mips_align (to
, fill
, label
)
10703 mips_emit_delays (false);
10704 frag_align (to
, fill
, 0);
10705 record_alignment (now_seg
, to
);
10708 assert (S_GET_SEGMENT (label
) == now_seg
);
10709 symbol_set_frag (label
, frag_now
);
10710 S_SET_VALUE (label
, (valueT
) frag_now_fix ());
10714 /* Align to a given power of two. .align 0 turns off the automatic
10715 alignment used by the data creating pseudo-ops. */
10719 int x ATTRIBUTE_UNUSED
;
10722 register long temp_fill
;
10723 long max_alignment
= 15;
10727 o Note that the assembler pulls down any immediately preceeding label
10728 to the aligned address.
10729 o It's not documented but auto alignment is reinstated by
10730 a .align pseudo instruction.
10731 o Note also that after auto alignment is turned off the mips assembler
10732 issues an error on attempt to assemble an improperly aligned data item.
10737 temp
= get_absolute_expression ();
10738 if (temp
> max_alignment
)
10739 as_bad (_("Alignment too large: %d. assumed."), temp
= max_alignment
);
10742 as_warn (_("Alignment negative: 0 assumed."));
10745 if (*input_line_pointer
== ',')
10747 input_line_pointer
++;
10748 temp_fill
= get_absolute_expression ();
10755 mips_align (temp
, (int) temp_fill
,
10756 insn_labels
!= NULL
? insn_labels
->label
: NULL
);
10763 demand_empty_rest_of_line ();
10767 mips_flush_pending_output ()
10769 mips_emit_delays (false);
10770 mips_clear_insn_labels ();
10779 /* When generating embedded PIC code, we only use the .text, .lit8,
10780 .sdata and .sbss sections. We change the .data and .rdata
10781 pseudo-ops to use .sdata. */
10782 if (mips_pic
== EMBEDDED_PIC
10783 && (sec
== 'd' || sec
== 'r'))
10787 /* The ELF backend needs to know that we are changing sections, so
10788 that .previous works correctly. We could do something like check
10789 for an obj_section_change_hook macro, but that might be confusing
10790 as it would not be appropriate to use it in the section changing
10791 functions in read.c, since obj-elf.c intercepts those. FIXME:
10792 This should be cleaner, somehow. */
10793 obj_elf_section_change_hook ();
10796 mips_emit_delays (false);
10806 subseg_set (bss_section
, (subsegT
) get_absolute_expression ());
10807 demand_empty_rest_of_line ();
10811 if (USE_GLOBAL_POINTER_OPT
)
10813 seg
= subseg_new (RDATA_SECTION_NAME
,
10814 (subsegT
) get_absolute_expression ());
10815 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
10817 bfd_set_section_flags (stdoutput
, seg
,
10823 if (strcmp (TARGET_OS
, "elf") != 0)
10824 record_alignment (seg
, 4);
10826 demand_empty_rest_of_line ();
10830 as_bad (_("No read only data section in this object file format"));
10831 demand_empty_rest_of_line ();
10837 if (USE_GLOBAL_POINTER_OPT
)
10839 seg
= subseg_new (".sdata", (subsegT
) get_absolute_expression ());
10840 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
10842 bfd_set_section_flags (stdoutput
, seg
,
10843 SEC_ALLOC
| SEC_LOAD
| SEC_RELOC
10845 if (strcmp (TARGET_OS
, "elf") != 0)
10846 record_alignment (seg
, 4);
10848 demand_empty_rest_of_line ();
10853 as_bad (_("Global pointers not supported; recompile -G 0"));
10854 demand_empty_rest_of_line ();
10863 mips_enable_auto_align ()
10874 label
= insn_labels
!= NULL
? insn_labels
->label
: NULL
;
10875 mips_emit_delays (false);
10876 if (log_size
> 0 && auto_align
)
10877 mips_align (log_size
, 0, label
);
10878 mips_clear_insn_labels ();
10879 cons (1 << log_size
);
10883 s_float_cons (type
)
10888 label
= insn_labels
!= NULL
? insn_labels
->label
: NULL
;
10890 mips_emit_delays (false);
10895 mips_align (3, 0, label
);
10897 mips_align (2, 0, label
);
10900 mips_clear_insn_labels ();
10905 /* Handle .globl. We need to override it because on Irix 5 you are
10908 where foo is an undefined symbol, to mean that foo should be
10909 considered to be the address of a function. */
10913 int x ATTRIBUTE_UNUSED
;
10920 name
= input_line_pointer
;
10921 c
= get_symbol_end ();
10922 symbolP
= symbol_find_or_make (name
);
10923 *input_line_pointer
= c
;
10924 SKIP_WHITESPACE ();
10926 /* On Irix 5, every global symbol that is not explicitly labelled as
10927 being a function is apparently labelled as being an object. */
10930 if (! is_end_of_line
[(unsigned char) *input_line_pointer
])
10935 secname
= input_line_pointer
;
10936 c
= get_symbol_end ();
10937 sec
= bfd_get_section_by_name (stdoutput
, secname
);
10939 as_bad (_("%s: no such section"), secname
);
10940 *input_line_pointer
= c
;
10942 if (sec
!= NULL
&& (sec
->flags
& SEC_CODE
) != 0)
10943 flag
= BSF_FUNCTION
;
10946 symbol_get_bfdsym (symbolP
)->flags
|= flag
;
10948 S_SET_EXTERNAL (symbolP
);
10949 demand_empty_rest_of_line ();
10954 int x ATTRIBUTE_UNUSED
;
10959 opt
= input_line_pointer
;
10960 c
= get_symbol_end ();
10964 /* FIXME: What does this mean? */
10966 else if (strncmp (opt
, "pic", 3) == 0)
10970 i
= atoi (opt
+ 3);
10974 mips_pic
= SVR4_PIC
;
10976 as_bad (_(".option pic%d not supported"), i
);
10978 if (USE_GLOBAL_POINTER_OPT
&& mips_pic
== SVR4_PIC
)
10980 if (g_switch_seen
&& g_switch_value
!= 0)
10981 as_warn (_("-G may not be used with SVR4 PIC code"));
10982 g_switch_value
= 0;
10983 bfd_set_gp_size (stdoutput
, 0);
10987 as_warn (_("Unrecognized option \"%s\""), opt
);
10989 *input_line_pointer
= c
;
10990 demand_empty_rest_of_line ();
10993 /* This structure is used to hold a stack of .set values. */
10995 struct mips_option_stack
10997 struct mips_option_stack
*next
;
10998 struct mips_set_options options
;
11001 static struct mips_option_stack
*mips_opts_stack
;
11003 /* Handle the .set pseudo-op. */
11007 int x ATTRIBUTE_UNUSED
;
11009 char *name
= input_line_pointer
, ch
;
11011 while (!is_end_of_line
[(unsigned char) *input_line_pointer
])
11012 input_line_pointer
++;
11013 ch
= *input_line_pointer
;
11014 *input_line_pointer
= '\0';
11016 if (strcmp (name
, "reorder") == 0)
11018 if (mips_opts
.noreorder
&& prev_nop_frag
!= NULL
)
11020 /* If we still have pending nops, we can discard them. The
11021 usual nop handling will insert any that are still
11023 prev_nop_frag
->fr_fix
-= (prev_nop_frag_holds
11024 * (mips_opts
.mips16
? 2 : 4));
11025 prev_nop_frag
= NULL
;
11027 mips_opts
.noreorder
= 0;
11029 else if (strcmp (name
, "noreorder") == 0)
11031 mips_emit_delays (true);
11032 mips_opts
.noreorder
= 1;
11033 mips_any_noreorder
= 1;
11035 else if (strcmp (name
, "at") == 0)
11037 mips_opts
.noat
= 0;
11039 else if (strcmp (name
, "noat") == 0)
11041 mips_opts
.noat
= 1;
11043 else if (strcmp (name
, "macro") == 0)
11045 mips_opts
.warn_about_macros
= 0;
11047 else if (strcmp (name
, "nomacro") == 0)
11049 if (mips_opts
.noreorder
== 0)
11050 as_bad (_("`noreorder' must be set before `nomacro'"));
11051 mips_opts
.warn_about_macros
= 1;
11053 else if (strcmp (name
, "move") == 0 || strcmp (name
, "novolatile") == 0)
11055 mips_opts
.nomove
= 0;
11057 else if (strcmp (name
, "nomove") == 0 || strcmp (name
, "volatile") == 0)
11059 mips_opts
.nomove
= 1;
11061 else if (strcmp (name
, "bopt") == 0)
11063 mips_opts
.nobopt
= 0;
11065 else if (strcmp (name
, "nobopt") == 0)
11067 mips_opts
.nobopt
= 1;
11069 else if (strcmp (name
, "mips16") == 0
11070 || strcmp (name
, "MIPS-16") == 0)
11071 mips_opts
.mips16
= 1;
11072 else if (strcmp (name
, "nomips16") == 0
11073 || strcmp (name
, "noMIPS-16") == 0)
11074 mips_opts
.mips16
= 0;
11075 else if (strncmp (name
, "mips", 4) == 0)
11079 /* Permit the user to change the ISA on the fly. Needless to
11080 say, misuse can cause serious problems. */
11081 isa
= atoi (name
+ 4);
11085 mips_opts
.gp32
= file_mips_gp32
;
11086 mips_opts
.fp32
= file_mips_fp32
;
11087 mips_opts
.abi
= file_mips_abi
;
11092 mips_opts
.gp32
= 1;
11093 mips_opts
.fp32
= 1;
11099 /* Loosen ABI register width restriction. */
11100 if (mips_opts
.abi
== O32_ABI
)
11101 mips_opts
.abi
= NO_ABI
;
11102 mips_opts
.gp32
= 0;
11103 mips_opts
.fp32
= 0;
11106 as_bad (_("unknown ISA level %s"), name
+ 4);
11112 case 0: mips_opts
.isa
= file_mips_isa
; break;
11113 case 1: mips_opts
.isa
= ISA_MIPS1
; break;
11114 case 2: mips_opts
.isa
= ISA_MIPS2
; break;
11115 case 3: mips_opts
.isa
= ISA_MIPS3
; break;
11116 case 4: mips_opts
.isa
= ISA_MIPS4
; break;
11117 case 5: mips_opts
.isa
= ISA_MIPS5
; break;
11118 case 32: mips_opts
.isa
= ISA_MIPS32
; break;
11119 case 64: mips_opts
.isa
= ISA_MIPS64
; break;
11120 default: as_bad (_("unknown ISA level %s"), name
+ 4); break;
11123 else if (strcmp (name
, "autoextend") == 0)
11124 mips_opts
.noautoextend
= 0;
11125 else if (strcmp (name
, "noautoextend") == 0)
11126 mips_opts
.noautoextend
= 1;
11127 else if (strcmp (name
, "push") == 0)
11129 struct mips_option_stack
*s
;
11131 s
= (struct mips_option_stack
*) xmalloc (sizeof *s
);
11132 s
->next
= mips_opts_stack
;
11133 s
->options
= mips_opts
;
11134 mips_opts_stack
= s
;
11136 else if (strcmp (name
, "pop") == 0)
11138 struct mips_option_stack
*s
;
11140 s
= mips_opts_stack
;
11142 as_bad (_(".set pop with no .set push"));
11145 /* If we're changing the reorder mode we need to handle
11146 delay slots correctly. */
11147 if (s
->options
.noreorder
&& ! mips_opts
.noreorder
)
11148 mips_emit_delays (true);
11149 else if (! s
->options
.noreorder
&& mips_opts
.noreorder
)
11151 if (prev_nop_frag
!= NULL
)
11153 prev_nop_frag
->fr_fix
-= (prev_nop_frag_holds
11154 * (mips_opts
.mips16
? 2 : 4));
11155 prev_nop_frag
= NULL
;
11159 mips_opts
= s
->options
;
11160 mips_opts_stack
= s
->next
;
11166 as_warn (_("Tried to set unrecognized symbol: %s\n"), name
);
11168 *input_line_pointer
= ch
;
11169 demand_empty_rest_of_line ();
11172 /* Handle the .abicalls pseudo-op. I believe this is equivalent to
11173 .option pic2. It means to generate SVR4 PIC calls. */
11176 s_abicalls (ignore
)
11177 int ignore ATTRIBUTE_UNUSED
;
11179 mips_pic
= SVR4_PIC
;
11180 if (USE_GLOBAL_POINTER_OPT
)
11182 if (g_switch_seen
&& g_switch_value
!= 0)
11183 as_warn (_("-G may not be used with SVR4 PIC code"));
11184 g_switch_value
= 0;
11186 bfd_set_gp_size (stdoutput
, 0);
11187 demand_empty_rest_of_line ();
11190 /* Handle the .cpload pseudo-op. This is used when generating SVR4
11191 PIC code. It sets the $gp register for the function based on the
11192 function address, which is in the register named in the argument.
11193 This uses a relocation against _gp_disp, which is handled specially
11194 by the linker. The result is:
11195 lui $gp,%hi(_gp_disp)
11196 addiu $gp,$gp,%lo(_gp_disp)
11197 addu $gp,$gp,.cpload argument
11198 The .cpload argument is normally $25 == $t9. */
11202 int ignore ATTRIBUTE_UNUSED
;
11207 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
11208 .cpload is ignored. */
11209 if (mips_pic
!= SVR4_PIC
|| HAVE_NEWABI
)
11215 /* .cpload should be in a .set noreorder section. */
11216 if (mips_opts
.noreorder
== 0)
11217 as_warn (_(".cpload not in noreorder section"));
11219 ex
.X_op
= O_symbol
;
11220 ex
.X_add_symbol
= symbol_find_or_make ("_gp_disp");
11221 ex
.X_op_symbol
= NULL
;
11222 ex
.X_add_number
= 0;
11224 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
11225 symbol_get_bfdsym (ex
.X_add_symbol
)->flags
|= BSF_OBJECT
;
11227 macro_build_lui (NULL
, &icnt
, &ex
, GP
);
11228 macro_build ((char *) NULL
, &icnt
, &ex
, "addiu", "t,r,j", GP
, GP
,
11229 (int) BFD_RELOC_LO16
);
11231 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "addu", "d,v,t",
11232 GP
, GP
, tc_get_register (0));
11234 demand_empty_rest_of_line ();
11237 /* Handle the .cpsetup pseudo-op defined for NewABI PIC code. The syntax is:
11238 .cpsetup $reg1, offset|$reg2, label
11240 If offset is given, this results in:
11241 sd $gp, offset($sp)
11242 lui $gp, %gp_rel(%neg(%hi(label)))
11243 daddiu $gp, $gp, %gp_rel(%neg(%lo(label)))
11244 addu $gp, $gp, $reg1
11246 If $reg2 is given, this results in:
11247 daddu $reg2, $gp, $0
11248 lui $gp, %gp_rel(%neg(%hi(label)))
11249 daddiu $gp, $gp, %gp_rel(%neg(%lo(label)))
11250 addu $gp, $gp, $reg1
11254 int ignore ATTRIBUTE_UNUSED
;
11256 expressionS ex_off
;
11257 expressionS ex_sym
;
11262 /* If we are not generating SVR4 PIC code, .cpload is ignored.
11263 We also need NewABI support. */
11264 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
11270 reg1
= tc_get_register (0);
11271 SKIP_WHITESPACE ();
11272 if (*input_line_pointer
!= ',')
11274 as_bad (_("missing argument separator ',' for .cpsetup"));
11278 input_line_pointer
++;
11279 SKIP_WHITESPACE ();
11280 if (*input_line_pointer
== '$')
11281 mips_cpreturn_register
= tc_get_register (0);
11283 mips_cpreturn_offset
= get_absolute_expression ();
11284 SKIP_WHITESPACE ();
11285 if (*input_line_pointer
!= ',')
11287 as_bad (_("missing argument separator ',' for .cpsetup"));
11291 input_line_pointer
++;
11292 SKIP_WHITESPACE ();
11293 sym
= input_line_pointer
;
11294 while (ISALNUM (*input_line_pointer
))
11295 input_line_pointer
++;
11296 *input_line_pointer
= 0;
11298 ex_sym
.X_op
= O_symbol
;
11299 ex_sym
.X_add_symbol
= symbol_find_or_make (sym
);
11300 ex_sym
.X_op_symbol
= NULL
;
11301 ex_sym
.X_add_number
= 0;
11303 if (mips_cpreturn_register
== -1)
11305 ex_off
.X_op
= O_constant
;
11306 ex_off
.X_add_symbol
= NULL
;
11307 ex_off
.X_op_symbol
= NULL
;
11308 ex_off
.X_add_number
= mips_cpreturn_offset
;
11310 macro_build ((char *) NULL
, &icnt
, &ex_off
, "sd", "t,o(b)",
11311 mips_gp_register
, (int) BFD_RELOC_LO16
, SP
);
11314 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "daddu",
11315 "d,v,t", mips_cpreturn_register
, mips_gp_register
, 0);
11317 macro_build ((char *) NULL
, &icnt
, &ex_sym
, "lui", "t,u", mips_gp_register
,
11318 (int) BFD_RELOC_GPREL16
);
11319 fix_new (frag_now
, (char *) prev_insn_fixp
- 4 - frag_now
->fr_literal
, 0,
11320 NULL
, 0, 0, BFD_RELOC_MIPS_SUB
);
11321 fix_new (frag_now
, (char *) prev_insn_fixp
- 4 - frag_now
->fr_literal
, 0,
11322 NULL
, 0, 0, BFD_RELOC_HI16_S
);
11323 macro_build ((char *) NULL
, &icnt
, &ex_sym
, "addiu", "t,r,j",
11324 mips_gp_register
, mips_gp_register
, (int) BFD_RELOC_GPREL16
);
11325 fix_new (frag_now
, (char *) prev_insn_fixp
- 4 - frag_now
->fr_literal
, 0,
11326 NULL
, 0, 0, BFD_RELOC_MIPS_SUB
);
11327 fix_new (frag_now
, (char *) prev_insn_fixp
- 4 - frag_now
->fr_literal
, 0,
11328 NULL
, 0, 0, BFD_RELOC_LO16
);
11329 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "daddu",
11330 "d,v,t", mips_gp_register
, mips_gp_register
, reg1
);
11332 demand_empty_rest_of_line ();
11337 int ignore ATTRIBUTE_UNUSED
;
11339 /* If we are not generating SVR4 PIC code, or if this is not NewABI code,
11340 .cplocal is ignored. */
11341 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
11347 mips_gp_register
= tc_get_register (0);
11350 /* Handle the .cprestore pseudo-op. This stores $gp into a given
11351 offset from $sp. The offset is remembered, and after making a PIC
11352 call $gp is restored from that location. */
11355 s_cprestore (ignore
)
11356 int ignore ATTRIBUTE_UNUSED
;
11361 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
11362 .cprestore is ignored. */
11363 if (mips_pic
!= SVR4_PIC
|| HAVE_NEWABI
)
11369 mips_cprestore_offset
= get_absolute_expression ();
11371 ex
.X_op
= O_constant
;
11372 ex
.X_add_symbol
= NULL
;
11373 ex
.X_op_symbol
= NULL
;
11374 ex
.X_add_number
= mips_cprestore_offset
;
11376 macro_build ((char *) NULL
, &icnt
, &ex
,
11377 HAVE_32BIT_ADDRESSES
? "sw" : "sd",
11378 "t,o(b)", GP
, (int) BFD_RELOC_LO16
, SP
);
11380 demand_empty_rest_of_line ();
11383 /* Handle the .cpreturn pseudo-op defined for NewABI PIC code. If an offset
11384 was given in the preceeding .gpsetup, it results in:
11385 ld $gp, offset($sp)
11387 If a register $reg2 was given there, it results in:
11388 daddiu $gp, $gp, $reg2
11391 s_cpreturn (ignore
)
11392 int ignore ATTRIBUTE_UNUSED
;
11397 /* If we are not generating SVR4 PIC code, .cpreturn is ignored.
11398 We also need NewABI support. */
11399 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
11405 if (mips_cpreturn_register
== -1)
11407 ex
.X_op
= O_constant
;
11408 ex
.X_add_symbol
= NULL
;
11409 ex
.X_op_symbol
= NULL
;
11410 ex
.X_add_number
= mips_cpreturn_offset
;
11412 macro_build ((char *) NULL
, &icnt
, &ex
, "ld", "t,o(b)",
11413 mips_gp_register
, (int) BFD_RELOC_LO16
, SP
);
11416 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "daddu",
11417 "d,v,t", mips_gp_register
, mips_cpreturn_register
, 0);
11419 demand_empty_rest_of_line ();
11422 /* Handle the .gpvalue pseudo-op. This is used when generating NewABI PIC
11423 code. It sets the offset to use in gp_rel relocations. */
11427 int ignore ATTRIBUTE_UNUSED
;
11429 /* If we are not generating SVR4 PIC code, .gpvalue is ignored.
11430 We also need NewABI support. */
11431 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
11437 mips_cpreturn_offset
= get_absolute_expression ();
11439 demand_empty_rest_of_line ();
11442 /* Handle the .gpword pseudo-op. This is used when generating PIC
11443 code. It generates a 32 bit GP relative reloc. */
11447 int ignore ATTRIBUTE_UNUSED
;
11453 /* When not generating PIC code, this is treated as .word. */
11454 if (mips_pic
!= SVR4_PIC
)
11460 label
= insn_labels
!= NULL
? insn_labels
->label
: NULL
;
11461 mips_emit_delays (true);
11463 mips_align (2, 0, label
);
11464 mips_clear_insn_labels ();
11468 if (ex
.X_op
!= O_symbol
|| ex
.X_add_number
!= 0)
11470 as_bad (_("Unsupported use of .gpword"));
11471 ignore_rest_of_line ();
11475 md_number_to_chars (p
, (valueT
) 0, 4);
11476 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 4, &ex
, 0,
11477 BFD_RELOC_GPREL32
);
11479 demand_empty_rest_of_line ();
11482 /* Handle the .cpadd pseudo-op. This is used when dealing with switch
11483 tables in SVR4 PIC code. */
11487 int ignore ATTRIBUTE_UNUSED
;
11492 /* This is ignored when not generating SVR4 PIC code or if this is NewABI
11494 if (mips_pic
!= SVR4_PIC
|| HAVE_NEWABI
)
11500 /* Add $gp to the register named as an argument. */
11501 reg
= tc_get_register (0);
11502 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
11503 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
11504 "d,v,t", reg
, reg
, GP
);
11506 demand_empty_rest_of_line ();
11509 /* Handle the .insn pseudo-op. This marks instruction labels in
11510 mips16 mode. This permits the linker to handle them specially,
11511 such as generating jalx instructions when needed. We also make
11512 them odd for the duration of the assembly, in order to generate the
11513 right sort of code. We will make them even in the adjust_symtab
11514 routine, while leaving them marked. This is convenient for the
11515 debugger and the disassembler. The linker knows to make them odd
11520 int ignore ATTRIBUTE_UNUSED
;
11522 if (mips_opts
.mips16
)
11523 mips16_mark_labels ();
11525 demand_empty_rest_of_line ();
11528 /* Handle a .stabn directive. We need these in order to mark a label
11529 as being a mips16 text label correctly. Sometimes the compiler
11530 will emit a label, followed by a .stabn, and then switch sections.
11531 If the label and .stabn are in mips16 mode, then the label is
11532 really a mips16 text label. */
11538 if (type
== 'n' && mips_opts
.mips16
)
11539 mips16_mark_labels ();
11544 /* Handle the .weakext pseudo-op as defined in Kane and Heinrich.
11548 s_mips_weakext (ignore
)
11549 int ignore ATTRIBUTE_UNUSED
;
11556 name
= input_line_pointer
;
11557 c
= get_symbol_end ();
11558 symbolP
= symbol_find_or_make (name
);
11559 S_SET_WEAK (symbolP
);
11560 *input_line_pointer
= c
;
11562 SKIP_WHITESPACE ();
11564 if (! is_end_of_line
[(unsigned char) *input_line_pointer
])
11566 if (S_IS_DEFINED (symbolP
))
11568 as_bad ("Ignoring attempt to redefine symbol `%s'.",
11569 S_GET_NAME (symbolP
));
11570 ignore_rest_of_line ();
11574 if (*input_line_pointer
== ',')
11576 ++input_line_pointer
;
11577 SKIP_WHITESPACE ();
11581 if (exp
.X_op
!= O_symbol
)
11583 as_bad ("bad .weakext directive");
11584 ignore_rest_of_line();
11587 symbol_set_value_expression (symbolP
, &exp
);
11590 demand_empty_rest_of_line ();
11593 /* Parse a register string into a number. Called from the ECOFF code
11594 to parse .frame. The argument is non-zero if this is the frame
11595 register, so that we can record it in mips_frame_reg. */
11598 tc_get_register (frame
)
11603 SKIP_WHITESPACE ();
11604 if (*input_line_pointer
++ != '$')
11606 as_warn (_("expected `$'"));
11609 else if (ISDIGIT (*input_line_pointer
))
11611 reg
= get_absolute_expression ();
11612 if (reg
< 0 || reg
>= 32)
11614 as_warn (_("Bad register number"));
11620 if (strncmp (input_line_pointer
, "fp", 2) == 0)
11622 else if (strncmp (input_line_pointer
, "sp", 2) == 0)
11624 else if (strncmp (input_line_pointer
, "gp", 2) == 0)
11626 else if (strncmp (input_line_pointer
, "at", 2) == 0)
11630 as_warn (_("Unrecognized register name"));
11633 input_line_pointer
+= 2;
11636 mips_frame_reg
= reg
!= 0 ? reg
: SP
;
11641 md_section_align (seg
, addr
)
11645 int align
= bfd_get_section_alignment (stdoutput
, seg
);
11648 /* We don't need to align ELF sections to the full alignment.
11649 However, Irix 5 may prefer that we align them at least to a 16
11650 byte boundary. We don't bother to align the sections if we are
11651 targeted for an embedded system. */
11652 if (strcmp (TARGET_OS
, "elf") == 0)
11658 return ((addr
+ (1 << align
) - 1) & (-1 << align
));
11661 /* Utility routine, called from above as well. If called while the
11662 input file is still being read, it's only an approximation. (For
11663 example, a symbol may later become defined which appeared to be
11664 undefined earlier.) */
11667 nopic_need_relax (sym
, before_relaxing
)
11669 int before_relaxing
;
11674 if (USE_GLOBAL_POINTER_OPT
&& g_switch_value
> 0)
11676 const char *symname
;
11679 /* Find out whether this symbol can be referenced off the GP
11680 register. It can be if it is smaller than the -G size or if
11681 it is in the .sdata or .sbss section. Certain symbols can
11682 not be referenced off the GP, although it appears as though
11684 symname
= S_GET_NAME (sym
);
11685 if (symname
!= (const char *) NULL
11686 && (strcmp (symname
, "eprol") == 0
11687 || strcmp (symname
, "etext") == 0
11688 || strcmp (symname
, "_gp") == 0
11689 || strcmp (symname
, "edata") == 0
11690 || strcmp (symname
, "_fbss") == 0
11691 || strcmp (symname
, "_fdata") == 0
11692 || strcmp (symname
, "_ftext") == 0
11693 || strcmp (symname
, "end") == 0
11694 || strcmp (symname
, "_gp_disp") == 0))
11696 else if ((! S_IS_DEFINED (sym
) || S_IS_COMMON (sym
))
11698 #ifndef NO_ECOFF_DEBUGGING
11699 || (symbol_get_obj (sym
)->ecoff_extern_size
!= 0
11700 && (symbol_get_obj (sym
)->ecoff_extern_size
11701 <= g_switch_value
))
11703 /* We must defer this decision until after the whole
11704 file has been read, since there might be a .extern
11705 after the first use of this symbol. */
11706 || (before_relaxing
11707 #ifndef NO_ECOFF_DEBUGGING
11708 && symbol_get_obj (sym
)->ecoff_extern_size
== 0
11710 && S_GET_VALUE (sym
) == 0)
11711 || (S_GET_VALUE (sym
) != 0
11712 && S_GET_VALUE (sym
) <= g_switch_value
)))
11716 const char *segname
;
11718 segname
= segment_name (S_GET_SEGMENT (sym
));
11719 assert (strcmp (segname
, ".lit8") != 0
11720 && strcmp (segname
, ".lit4") != 0);
11721 change
= (strcmp (segname
, ".sdata") != 0
11722 && strcmp (segname
, ".sbss") != 0
11723 && strncmp (segname
, ".sdata.", 7) != 0
11724 && strncmp (segname
, ".gnu.linkonce.s.", 16) != 0);
11729 /* We are not optimizing for the GP register. */
11733 /* Given a mips16 variant frag FRAGP, return non-zero if it needs an
11734 extended opcode. SEC is the section the frag is in. */
11737 mips16_extended_frag (fragp
, sec
, stretch
)
11743 register const struct mips16_immed_operand
*op
;
11745 int mintiny
, maxtiny
;
11749 if (RELAX_MIPS16_USER_SMALL (fragp
->fr_subtype
))
11751 if (RELAX_MIPS16_USER_EXT (fragp
->fr_subtype
))
11754 type
= RELAX_MIPS16_TYPE (fragp
->fr_subtype
);
11755 op
= mips16_immed_operands
;
11756 while (op
->type
!= type
)
11759 assert (op
< mips16_immed_operands
+ MIPS16_NUM_IMMED
);
11764 if (type
== '<' || type
== '>' || type
== '[' || type
== ']')
11767 maxtiny
= 1 << op
->nbits
;
11772 maxtiny
= (1 << op
->nbits
) - 1;
11777 mintiny
= - (1 << (op
->nbits
- 1));
11778 maxtiny
= (1 << (op
->nbits
- 1)) - 1;
11781 sym_frag
= symbol_get_frag (fragp
->fr_symbol
);
11782 val
= S_GET_VALUE (fragp
->fr_symbol
);
11783 symsec
= S_GET_SEGMENT (fragp
->fr_symbol
);
11789 /* We won't have the section when we are called from
11790 mips_relax_frag. However, we will always have been called
11791 from md_estimate_size_before_relax first. If this is a
11792 branch to a different section, we mark it as such. If SEC is
11793 NULL, and the frag is not marked, then it must be a branch to
11794 the same section. */
11797 if (RELAX_MIPS16_LONG_BRANCH (fragp
->fr_subtype
))
11802 /* Must have been called from md_estimate_size_before_relax. */
11805 fragp
->fr_subtype
=
11806 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
11808 /* FIXME: We should support this, and let the linker
11809 catch branches and loads that are out of range. */
11810 as_bad_where (fragp
->fr_file
, fragp
->fr_line
,
11811 _("unsupported PC relative reference to different section"));
11815 if (fragp
!= sym_frag
&& sym_frag
->fr_address
== 0)
11816 /* Assume non-extended on the first relaxation pass.
11817 The address we have calculated will be bogus if this is
11818 a forward branch to another frag, as the forward frag
11819 will have fr_address == 0. */
11823 /* In this case, we know for sure that the symbol fragment is in
11824 the same section. If the relax_marker of the symbol fragment
11825 differs from the relax_marker of this fragment, we have not
11826 yet adjusted the symbol fragment fr_address. We want to add
11827 in STRETCH in order to get a better estimate of the address.
11828 This particularly matters because of the shift bits. */
11830 && sym_frag
->relax_marker
!= fragp
->relax_marker
)
11834 /* Adjust stretch for any alignment frag. Note that if have
11835 been expanding the earlier code, the symbol may be
11836 defined in what appears to be an earlier frag. FIXME:
11837 This doesn't handle the fr_subtype field, which specifies
11838 a maximum number of bytes to skip when doing an
11840 for (f
= fragp
; f
!= NULL
&& f
!= sym_frag
; f
= f
->fr_next
)
11842 if (f
->fr_type
== rs_align
|| f
->fr_type
== rs_align_code
)
11845 stretch
= - ((- stretch
)
11846 & ~ ((1 << (int) f
->fr_offset
) - 1));
11848 stretch
&= ~ ((1 << (int) f
->fr_offset
) - 1);
11857 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
11859 /* The base address rules are complicated. The base address of
11860 a branch is the following instruction. The base address of a
11861 PC relative load or add is the instruction itself, but if it
11862 is in a delay slot (in which case it can not be extended) use
11863 the address of the instruction whose delay slot it is in. */
11864 if (type
== 'p' || type
== 'q')
11868 /* If we are currently assuming that this frag should be
11869 extended, then, the current address is two bytes
11871 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
11874 /* Ignore the low bit in the target, since it will be set
11875 for a text label. */
11876 if ((val
& 1) != 0)
11879 else if (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
))
11881 else if (RELAX_MIPS16_DSLOT (fragp
->fr_subtype
))
11884 val
-= addr
& ~ ((1 << op
->shift
) - 1);
11886 /* Branch offsets have an implicit 0 in the lowest bit. */
11887 if (type
== 'p' || type
== 'q')
11890 /* If any of the shifted bits are set, we must use an extended
11891 opcode. If the address depends on the size of this
11892 instruction, this can lead to a loop, so we arrange to always
11893 use an extended opcode. We only check this when we are in
11894 the main relaxation loop, when SEC is NULL. */
11895 if ((val
& ((1 << op
->shift
) - 1)) != 0 && sec
== NULL
)
11897 fragp
->fr_subtype
=
11898 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
11902 /* If we are about to mark a frag as extended because the value
11903 is precisely maxtiny + 1, then there is a chance of an
11904 infinite loop as in the following code:
11909 In this case when the la is extended, foo is 0x3fc bytes
11910 away, so the la can be shrunk, but then foo is 0x400 away, so
11911 the la must be extended. To avoid this loop, we mark the
11912 frag as extended if it was small, and is about to become
11913 extended with a value of maxtiny + 1. */
11914 if (val
== ((maxtiny
+ 1) << op
->shift
)
11915 && ! RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
)
11918 fragp
->fr_subtype
=
11919 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
11923 else if (symsec
!= absolute_section
&& sec
!= NULL
)
11924 as_bad_where (fragp
->fr_file
, fragp
->fr_line
, _("unsupported relocation"));
11926 if ((val
& ((1 << op
->shift
) - 1)) != 0
11927 || val
< (mintiny
<< op
->shift
)
11928 || val
> (maxtiny
<< op
->shift
))
11934 /* Estimate the size of a frag before relaxing. Unless this is the
11935 mips16, we are not really relaxing here, and the final size is
11936 encoded in the subtype information. For the mips16, we have to
11937 decide whether we are using an extended opcode or not. */
11940 md_estimate_size_before_relax (fragp
, segtype
)
11945 boolean linkonce
= false;
11947 if (RELAX_MIPS16_P (fragp
->fr_subtype
))
11949 if (mips16_extended_frag (fragp
, segtype
, 0))
11951 fragp
->fr_subtype
= RELAX_MIPS16_MARK_EXTENDED (fragp
->fr_subtype
);
11956 fragp
->fr_subtype
= RELAX_MIPS16_CLEAR_EXTENDED (fragp
->fr_subtype
);
11961 if (mips_pic
== NO_PIC
)
11963 change
= nopic_need_relax (fragp
->fr_symbol
, 0);
11965 else if (mips_pic
== SVR4_PIC
)
11970 sym
= fragp
->fr_symbol
;
11972 /* Handle the case of a symbol equated to another symbol. */
11973 while (symbol_equated_reloc_p (sym
))
11977 /* It's possible to get a loop here in a badly written
11979 n
= symbol_get_value_expression (sym
)->X_add_symbol
;
11985 symsec
= S_GET_SEGMENT (sym
);
11987 /* duplicate the test for LINK_ONCE sections as in adjust_reloc_syms */
11988 if (symsec
!= segtype
&& ! S_IS_LOCAL (sym
))
11990 if ((bfd_get_section_flags (stdoutput
, symsec
) & SEC_LINK_ONCE
)
11994 /* The GNU toolchain uses an extension for ELF: a section
11995 beginning with the magic string .gnu.linkonce is a linkonce
11997 if (strncmp (segment_name (symsec
), ".gnu.linkonce",
11998 sizeof ".gnu.linkonce" - 1) == 0)
12002 /* This must duplicate the test in adjust_reloc_syms. */
12003 change
= (symsec
!= &bfd_und_section
12004 && symsec
!= &bfd_abs_section
12005 && ! bfd_is_com_section (symsec
)
12008 /* A global or weak symbol is treated as external. */
12009 && (OUTPUT_FLAVOR
== bfd_target_elf_flavour
12010 && ! (S_IS_EXTERN (sym
) || S_IS_WEAK (sym
)))
12019 /* Record the offset to the first reloc in the fr_opcode field.
12020 This lets md_convert_frag and tc_gen_reloc know that the code
12021 must be expanded. */
12022 fragp
->fr_opcode
= (fragp
->fr_literal
12024 - RELAX_OLD (fragp
->fr_subtype
)
12025 + RELAX_RELOC1 (fragp
->fr_subtype
));
12026 /* FIXME: This really needs as_warn_where. */
12027 if (RELAX_WARN (fragp
->fr_subtype
))
12028 as_warn (_("AT used after \".set noat\" or macro used after "
12029 "\".set nomacro\""));
12031 return RELAX_NEW (fragp
->fr_subtype
) - RELAX_OLD (fragp
->fr_subtype
);
12037 /* This is called to see whether a reloc against a defined symbol
12038 should be converted into a reloc against a section. Don't adjust
12039 MIPS16 jump relocations, so we don't have to worry about the format
12040 of the offset in the .o file. Don't adjust relocations against
12041 mips16 symbols, so that the linker can find them if it needs to set
12045 mips_fix_adjustable (fixp
)
12049 /* Prevent all adjustments to global symbols. */
12050 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
12051 && (S_IS_EXTERN (fixp
->fx_addsy
) || S_IS_WEAK (fixp
->fx_addsy
)))
12054 if (fixp
->fx_r_type
== BFD_RELOC_MIPS16_JMP
)
12056 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
12057 || fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
12059 if (fixp
->fx_addsy
== NULL
)
12062 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
12063 && S_GET_OTHER (fixp
->fx_addsy
) == STO_MIPS16
12064 && fixp
->fx_subsy
== NULL
)
12070 /* Translate internal representation of relocation info to BFD target
12074 tc_gen_reloc (section
, fixp
)
12075 asection
*section ATTRIBUTE_UNUSED
;
12078 static arelent
*retval
[4];
12080 bfd_reloc_code_real_type code
;
12082 reloc
= retval
[0] = (arelent
*) xmalloc (sizeof (arelent
));
12085 reloc
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
12086 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
12087 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
12089 if (mips_pic
== EMBEDDED_PIC
12090 && SWITCH_TABLE (fixp
))
12092 /* For a switch table entry we use a special reloc. The addend
12093 is actually the difference between the reloc address and the
12095 reloc
->addend
= reloc
->address
- S_GET_VALUE (fixp
->fx_subsy
);
12096 if (OUTPUT_FLAVOR
!= bfd_target_ecoff_flavour
)
12097 as_fatal (_("Double check fx_r_type in tc-mips.c:tc_gen_reloc"));
12098 fixp
->fx_r_type
= BFD_RELOC_GPREL32
;
12100 else if (fixp
->fx_pcrel
== 0 || OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
12101 reloc
->addend
= fixp
->fx_addnumber
;
12102 else if (fixp
->fx_r_type
== BFD_RELOC_PCREL_LO16
)
12104 /* We use a special addend for an internal RELLO reloc. */
12105 if (symbol_section_p (fixp
->fx_addsy
))
12106 reloc
->addend
= reloc
->address
- S_GET_VALUE (fixp
->fx_subsy
);
12108 reloc
->addend
= fixp
->fx_addnumber
+ reloc
->address
;
12110 else if (fixp
->fx_r_type
== BFD_RELOC_PCREL_HI16_S
)
12112 assert (fixp
->fx_next
!= NULL
12113 && fixp
->fx_next
->fx_r_type
== BFD_RELOC_PCREL_LO16
);
12114 /* We use a special addend for an internal RELHI reloc. The
12115 reloc is relative to the RELLO; adjust the addend
12117 if (symbol_section_p (fixp
->fx_addsy
))
12118 reloc
->addend
= (fixp
->fx_next
->fx_frag
->fr_address
12119 + fixp
->fx_next
->fx_where
12120 - S_GET_VALUE (fixp
->fx_subsy
));
12122 reloc
->addend
= (fixp
->fx_addnumber
12123 + fixp
->fx_next
->fx_frag
->fr_address
12124 + fixp
->fx_next
->fx_where
);
12128 if (OUTPUT_FLAVOR
!= bfd_target_aout_flavour
)
12129 /* A gruesome hack which is a result of the gruesome gas reloc
12131 reloc
->addend
= reloc
->address
;
12133 reloc
->addend
= -reloc
->address
;
12136 /* If this is a variant frag, we may need to adjust the existing
12137 reloc and generate a new one. */
12138 if (fixp
->fx_frag
->fr_opcode
!= NULL
12139 && (fixp
->fx_r_type
== BFD_RELOC_GPREL16
12140 || fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT16
12141 || fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL16
12142 || fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT_HI16
12143 || fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT_LO16
12144 || fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL_HI16
12145 || fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL_LO16
)
12150 assert (! RELAX_MIPS16_P (fixp
->fx_frag
->fr_subtype
));
12152 /* If this is not the last reloc in this frag, then we have two
12153 GPREL relocs, or a GOT_HI16/GOT_LO16 pair, or a
12154 CALL_HI16/CALL_LO16, both of which are being replaced. Let
12155 the second one handle all of them. */
12156 if (fixp
->fx_next
!= NULL
12157 && fixp
->fx_frag
== fixp
->fx_next
->fx_frag
)
12159 assert ((fixp
->fx_r_type
== BFD_RELOC_GPREL16
12160 && fixp
->fx_next
->fx_r_type
== BFD_RELOC_GPREL16
)
12161 || (fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT_HI16
12162 && (fixp
->fx_next
->fx_r_type
12163 == BFD_RELOC_MIPS_GOT_LO16
))
12164 || (fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL_HI16
12165 && (fixp
->fx_next
->fx_r_type
12166 == BFD_RELOC_MIPS_CALL_LO16
)));
12171 fixp
->fx_where
= fixp
->fx_frag
->fr_opcode
- fixp
->fx_frag
->fr_literal
;
12172 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
12173 reloc2
= retval
[1] = (arelent
*) xmalloc (sizeof (arelent
));
12175 reloc2
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
12176 *reloc2
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
12177 reloc2
->address
= (reloc
->address
12178 + (RELAX_RELOC2 (fixp
->fx_frag
->fr_subtype
)
12179 - RELAX_RELOC1 (fixp
->fx_frag
->fr_subtype
)));
12180 reloc2
->addend
= fixp
->fx_addnumber
;
12181 reloc2
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_LO16
);
12182 assert (reloc2
->howto
!= NULL
);
12184 if (RELAX_RELOC3 (fixp
->fx_frag
->fr_subtype
))
12188 reloc3
= retval
[2] = (arelent
*) xmalloc (sizeof (arelent
));
12191 reloc3
->address
+= 4;
12194 if (mips_pic
== NO_PIC
)
12196 assert (fixp
->fx_r_type
== BFD_RELOC_GPREL16
);
12197 fixp
->fx_r_type
= BFD_RELOC_HI16_S
;
12199 else if (mips_pic
== SVR4_PIC
)
12201 switch (fixp
->fx_r_type
)
12205 case BFD_RELOC_MIPS_GOT16
:
12207 case BFD_RELOC_MIPS_CALL16
:
12208 case BFD_RELOC_MIPS_GOT_LO16
:
12209 case BFD_RELOC_MIPS_CALL_LO16
:
12210 fixp
->fx_r_type
= BFD_RELOC_MIPS_GOT16
;
12218 /* Since MIPS ELF uses Rel instead of Rela, encode the vtable entry
12219 to be used in the relocation's section offset. */
12220 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
12222 reloc
->address
= reloc
->addend
;
12226 /* Since DIFF_EXPR_OK is defined in tc-mips.h, it is possible that
12227 fixup_segment converted a non-PC relative reloc into a PC
12228 relative reloc. In such a case, we need to convert the reloc
12230 code
= fixp
->fx_r_type
;
12231 if (fixp
->fx_pcrel
)
12236 code
= BFD_RELOC_8_PCREL
;
12239 code
= BFD_RELOC_16_PCREL
;
12242 code
= BFD_RELOC_32_PCREL
;
12245 code
= BFD_RELOC_64_PCREL
;
12247 case BFD_RELOC_8_PCREL
:
12248 case BFD_RELOC_16_PCREL
:
12249 case BFD_RELOC_32_PCREL
:
12250 case BFD_RELOC_64_PCREL
:
12251 case BFD_RELOC_16_PCREL_S2
:
12252 case BFD_RELOC_PCREL_HI16_S
:
12253 case BFD_RELOC_PCREL_LO16
:
12256 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
12257 _("Cannot make %s relocation PC relative"),
12258 bfd_get_reloc_code_name (code
));
12263 /* md_apply_fix3 has a double-subtraction hack to get
12264 bfd_install_relocation to behave nicely. GPREL relocations are
12265 handled correctly without this hack, so undo it here. We can't
12266 stop md_apply_fix3 from subtracting twice in the first place since
12267 the fake addend is required for variant frags above. */
12268 if (fixp
->fx_addsy
!= NULL
&& OUTPUT_FLAVOR
== bfd_target_elf_flavour
12269 && code
== BFD_RELOC_GPREL16
12270 && reloc
->addend
!= 0
12271 && mips_need_elf_addend_fixup (fixp
))
12272 reloc
->addend
+= S_GET_VALUE (fixp
->fx_addsy
);
12275 /* To support a PC relative reloc when generating embedded PIC code
12276 for ECOFF, we use a Cygnus extension. We check for that here to
12277 make sure that we don't let such a reloc escape normally. */
12278 if ((OUTPUT_FLAVOR
== bfd_target_ecoff_flavour
12279 || OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
12280 && code
== BFD_RELOC_16_PCREL_S2
12281 && mips_pic
!= EMBEDDED_PIC
)
12282 reloc
->howto
= NULL
;
12284 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
12286 if (reloc
->howto
== NULL
)
12288 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
12289 _("Can not represent %s relocation in this object file format"),
12290 bfd_get_reloc_code_name (code
));
12297 /* Relax a machine dependent frag. This returns the amount by which
12298 the current size of the frag should change. */
12301 mips_relax_frag (fragp
, stretch
)
12305 if (! RELAX_MIPS16_P (fragp
->fr_subtype
))
12308 if (mips16_extended_frag (fragp
, NULL
, stretch
))
12310 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
12312 fragp
->fr_subtype
= RELAX_MIPS16_MARK_EXTENDED (fragp
->fr_subtype
);
12317 if (! RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
12319 fragp
->fr_subtype
= RELAX_MIPS16_CLEAR_EXTENDED (fragp
->fr_subtype
);
12326 /* Convert a machine dependent frag. */
12329 md_convert_frag (abfd
, asec
, fragp
)
12330 bfd
*abfd ATTRIBUTE_UNUSED
;
12337 if (RELAX_MIPS16_P (fragp
->fr_subtype
))
12340 register const struct mips16_immed_operand
*op
;
12341 boolean small
, ext
;
12344 unsigned long insn
;
12345 boolean use_extend
;
12346 unsigned short extend
;
12348 type
= RELAX_MIPS16_TYPE (fragp
->fr_subtype
);
12349 op
= mips16_immed_operands
;
12350 while (op
->type
!= type
)
12353 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
12364 resolve_symbol_value (fragp
->fr_symbol
);
12365 val
= S_GET_VALUE (fragp
->fr_symbol
);
12370 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
12372 /* The rules for the base address of a PC relative reloc are
12373 complicated; see mips16_extended_frag. */
12374 if (type
== 'p' || type
== 'q')
12379 /* Ignore the low bit in the target, since it will be
12380 set for a text label. */
12381 if ((val
& 1) != 0)
12384 else if (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
))
12386 else if (RELAX_MIPS16_DSLOT (fragp
->fr_subtype
))
12389 addr
&= ~ (addressT
) ((1 << op
->shift
) - 1);
12392 /* Make sure the section winds up with the alignment we have
12395 record_alignment (asec
, op
->shift
);
12399 && (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
)
12400 || RELAX_MIPS16_DSLOT (fragp
->fr_subtype
)))
12401 as_warn_where (fragp
->fr_file
, fragp
->fr_line
,
12402 _("extended instruction in delay slot"));
12404 buf
= (bfd_byte
*) (fragp
->fr_literal
+ fragp
->fr_fix
);
12406 if (target_big_endian
)
12407 insn
= bfd_getb16 (buf
);
12409 insn
= bfd_getl16 (buf
);
12411 mips16_immed (fragp
->fr_file
, fragp
->fr_line
, type
, val
,
12412 RELAX_MIPS16_USER_EXT (fragp
->fr_subtype
),
12413 small
, ext
, &insn
, &use_extend
, &extend
);
12417 md_number_to_chars (buf
, 0xf000 | extend
, 2);
12418 fragp
->fr_fix
+= 2;
12422 md_number_to_chars (buf
, insn
, 2);
12423 fragp
->fr_fix
+= 2;
12428 if (fragp
->fr_opcode
== NULL
)
12431 old
= RELAX_OLD (fragp
->fr_subtype
);
12432 new = RELAX_NEW (fragp
->fr_subtype
);
12433 fixptr
= fragp
->fr_literal
+ fragp
->fr_fix
;
12436 memcpy (fixptr
- old
, fixptr
, new);
12438 fragp
->fr_fix
+= new - old
;
12444 /* This function is called after the relocs have been generated.
12445 We've been storing mips16 text labels as odd. Here we convert them
12446 back to even for the convenience of the debugger. */
12449 mips_frob_file_after_relocs ()
12452 unsigned int count
, i
;
12454 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
12457 syms
= bfd_get_outsymbols (stdoutput
);
12458 count
= bfd_get_symcount (stdoutput
);
12459 for (i
= 0; i
< count
; i
++, syms
++)
12461 if (elf_symbol (*syms
)->internal_elf_sym
.st_other
== STO_MIPS16
12462 && ((*syms
)->value
& 1) != 0)
12464 (*syms
)->value
&= ~1;
12465 /* If the symbol has an odd size, it was probably computed
12466 incorrectly, so adjust that as well. */
12467 if ((elf_symbol (*syms
)->internal_elf_sym
.st_size
& 1) != 0)
12468 ++elf_symbol (*syms
)->internal_elf_sym
.st_size
;
12475 /* This function is called whenever a label is defined. It is used
12476 when handling branch delays; if a branch has a label, we assume we
12477 can not move it. */
12480 mips_define_label (sym
)
12483 struct insn_label_list
*l
;
12485 if (free_insn_labels
== NULL
)
12486 l
= (struct insn_label_list
*) xmalloc (sizeof *l
);
12489 l
= free_insn_labels
;
12490 free_insn_labels
= l
->next
;
12494 l
->next
= insn_labels
;
12498 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12500 /* Some special processing for a MIPS ELF file. */
12503 mips_elf_final_processing ()
12505 /* Write out the register information. */
12510 s
.ri_gprmask
= mips_gprmask
;
12511 s
.ri_cprmask
[0] = mips_cprmask
[0];
12512 s
.ri_cprmask
[1] = mips_cprmask
[1];
12513 s
.ri_cprmask
[2] = mips_cprmask
[2];
12514 s
.ri_cprmask
[3] = mips_cprmask
[3];
12515 /* The gp_value field is set by the MIPS ELF backend. */
12517 bfd_mips_elf32_swap_reginfo_out (stdoutput
, &s
,
12518 ((Elf32_External_RegInfo
*)
12519 mips_regmask_frag
));
12523 Elf64_Internal_RegInfo s
;
12525 s
.ri_gprmask
= mips_gprmask
;
12527 s
.ri_cprmask
[0] = mips_cprmask
[0];
12528 s
.ri_cprmask
[1] = mips_cprmask
[1];
12529 s
.ri_cprmask
[2] = mips_cprmask
[2];
12530 s
.ri_cprmask
[3] = mips_cprmask
[3];
12531 /* The gp_value field is set by the MIPS ELF backend. */
12533 bfd_mips_elf64_swap_reginfo_out (stdoutput
, &s
,
12534 ((Elf64_External_RegInfo
*)
12535 mips_regmask_frag
));
12538 /* Set the MIPS ELF flag bits. FIXME: There should probably be some
12539 sort of BFD interface for this. */
12540 if (mips_any_noreorder
)
12541 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_NOREORDER
;
12542 if (mips_pic
!= NO_PIC
)
12543 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_PIC
;
12545 /* Set the MIPS ELF ABI flags. */
12546 if (file_mips_abi
== NO_ABI
)
12548 else if (file_mips_abi
== O32_ABI
)
12549 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_O32
;
12550 else if (file_mips_abi
== O64_ABI
)
12551 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_O64
;
12552 else if (file_mips_abi
== EABI_ABI
)
12555 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_EABI64
;
12557 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_EABI32
;
12559 else if (file_mips_abi
== N32_ABI
)
12560 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ABI2
;
12562 /* Nothing to do for "64". */
12564 if (mips_32bitmode
)
12565 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_32BITMODE
;
12568 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */
12570 typedef struct proc
{
12572 unsigned long reg_mask
;
12573 unsigned long reg_offset
;
12574 unsigned long fpreg_mask
;
12575 unsigned long fpreg_offset
;
12576 unsigned long frame_offset
;
12577 unsigned long frame_reg
;
12578 unsigned long pc_reg
;
12581 static procS cur_proc
;
12582 static procS
*cur_proc_ptr
;
12583 static int numprocs
;
12585 /* Fill in an rs_align_code fragment. */
12588 mips_handle_align (fragp
)
12591 if (fragp
->fr_type
!= rs_align_code
)
12594 if (mips_opts
.mips16
)
12596 static const unsigned char be_nop
[] = { 0x65, 0x00 };
12597 static const unsigned char le_nop
[] = { 0x00, 0x65 };
12602 bytes
= fragp
->fr_next
->fr_address
- fragp
->fr_address
- fragp
->fr_fix
;
12603 p
= fragp
->fr_literal
+ fragp
->fr_fix
;
12608 fragp
->fr_fix
+= 1;
12611 memcpy (p
, (target_big_endian
? be_nop
: le_nop
), 2);
12615 /* For mips32, a nop is a zero, which we trivially get by doing nothing. */
12626 /* check for premature end, nesting errors, etc */
12628 as_warn (_("missing .end at end of assembly"));
12637 if (*input_line_pointer
== '-')
12639 ++input_line_pointer
;
12642 if (!ISDIGIT (*input_line_pointer
))
12643 as_bad (_("Expected simple number."));
12644 if (input_line_pointer
[0] == '0')
12646 if (input_line_pointer
[1] == 'x')
12648 input_line_pointer
+= 2;
12649 while (ISXDIGIT (*input_line_pointer
))
12652 val
|= hex_value (*input_line_pointer
++);
12654 return negative
? -val
: val
;
12658 ++input_line_pointer
;
12659 while (ISDIGIT (*input_line_pointer
))
12662 val
|= *input_line_pointer
++ - '0';
12664 return negative
? -val
: val
;
12667 if (!ISDIGIT (*input_line_pointer
))
12669 printf (_(" *input_line_pointer == '%c' 0x%02x\n"),
12670 *input_line_pointer
, *input_line_pointer
);
12671 as_warn (_("Invalid number"));
12674 while (ISDIGIT (*input_line_pointer
))
12677 val
+= *input_line_pointer
++ - '0';
12679 return negative
? -val
: val
;
12682 /* The .file directive; just like the usual .file directive, but there
12683 is an initial number which is the ECOFF file index. */
12687 int x ATTRIBUTE_UNUSED
;
12691 line
= get_number ();
12695 /* The .end directive. */
12699 int x ATTRIBUTE_UNUSED
;
12704 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
12707 demand_empty_rest_of_line ();
12712 #ifdef BFD_ASSEMBLER
12713 if ((bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) != 0)
12718 if (now_seg
!= data_section
&& now_seg
!= bss_section
)
12725 as_warn (_(".end not in text section"));
12729 as_warn (_(".end directive without a preceding .ent directive."));
12730 demand_empty_rest_of_line ();
12736 assert (S_GET_NAME (p
));
12737 if (strcmp (S_GET_NAME (p
), S_GET_NAME (cur_proc_ptr
->isym
)))
12738 as_warn (_(".end symbol does not match .ent symbol."));
12741 as_warn (_(".end directive missing or unknown symbol"));
12743 #ifdef MIPS_STABS_ELF
12745 segT saved_seg
= now_seg
;
12746 subsegT saved_subseg
= now_subseg
;
12751 dot
= frag_now_fix ();
12753 #ifdef md_flush_pending_output
12754 md_flush_pending_output ();
12758 subseg_set (pdr_seg
, 0);
12760 /* Write the symbol. */
12761 exp
.X_op
= O_symbol
;
12762 exp
.X_add_symbol
= p
;
12763 exp
.X_add_number
= 0;
12764 emit_expr (&exp
, 4);
12766 fragp
= frag_more (7 * 4);
12768 md_number_to_chars (fragp
, (valueT
) cur_proc_ptr
->reg_mask
, 4);
12769 md_number_to_chars (fragp
+ 4, (valueT
) cur_proc_ptr
->reg_offset
, 4);
12770 md_number_to_chars (fragp
+ 8, (valueT
) cur_proc_ptr
->fpreg_mask
, 4);
12771 md_number_to_chars (fragp
+ 12, (valueT
) cur_proc_ptr
->fpreg_offset
, 4);
12772 md_number_to_chars (fragp
+ 16, (valueT
) cur_proc_ptr
->frame_offset
, 4);
12773 md_number_to_chars (fragp
+ 20, (valueT
) cur_proc_ptr
->frame_reg
, 4);
12774 md_number_to_chars (fragp
+ 24, (valueT
) cur_proc_ptr
->pc_reg
, 4);
12776 subseg_set (saved_seg
, saved_subseg
);
12780 cur_proc_ptr
= NULL
;
12783 /* The .aent and .ent directives. */
12793 symbolP
= get_symbol ();
12794 if (*input_line_pointer
== ',')
12795 input_line_pointer
++;
12796 SKIP_WHITESPACE ();
12797 if (ISDIGIT (*input_line_pointer
)
12798 || *input_line_pointer
== '-')
12799 number
= get_number ();
12801 #ifdef BFD_ASSEMBLER
12802 if ((bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) != 0)
12807 if (now_seg
!= data_section
&& now_seg
!= bss_section
)
12814 as_warn (_(".ent or .aent not in text section."));
12816 if (!aent
&& cur_proc_ptr
)
12817 as_warn (_("missing .end"));
12821 cur_proc_ptr
= &cur_proc
;
12822 memset (cur_proc_ptr
, '\0', sizeof (procS
));
12824 cur_proc_ptr
->isym
= symbolP
;
12826 symbol_get_bfdsym (symbolP
)->flags
|= BSF_FUNCTION
;
12831 demand_empty_rest_of_line ();
12834 /* The .frame directive. If the mdebug section is present (IRIX 5 native)
12835 then ecoff.c (ecoff_directive_frame) is used. For embedded targets,
12836 s_mips_frame is used so that we can set the PDR information correctly.
12837 We can't use the ecoff routines because they make reference to the ecoff
12838 symbol table (in the mdebug section). */
12841 s_mips_frame (ignore
)
12842 int ignore ATTRIBUTE_UNUSED
;
12844 #ifdef MIPS_STABS_ELF
12848 if (cur_proc_ptr
== (procS
*) NULL
)
12850 as_warn (_(".frame outside of .ent"));
12851 demand_empty_rest_of_line ();
12855 cur_proc_ptr
->frame_reg
= tc_get_register (1);
12857 SKIP_WHITESPACE ();
12858 if (*input_line_pointer
++ != ','
12859 || get_absolute_expression_and_terminator (&val
) != ',')
12861 as_warn (_("Bad .frame directive"));
12862 --input_line_pointer
;
12863 demand_empty_rest_of_line ();
12867 cur_proc_ptr
->frame_offset
= val
;
12868 cur_proc_ptr
->pc_reg
= tc_get_register (0);
12870 demand_empty_rest_of_line ();
12873 #endif /* MIPS_STABS_ELF */
12876 /* The .fmask and .mask directives. If the mdebug section is present
12877 (IRIX 5 native) then ecoff.c (ecoff_directive_mask) is used. For
12878 embedded targets, s_mips_mask is used so that we can set the PDR
12879 information correctly. We can't use the ecoff routines because they
12880 make reference to the ecoff symbol table (in the mdebug section). */
12883 s_mips_mask (reg_type
)
12886 #ifdef MIPS_STABS_ELF
12889 if (cur_proc_ptr
== (procS
*) NULL
)
12891 as_warn (_(".mask/.fmask outside of .ent"));
12892 demand_empty_rest_of_line ();
12896 if (get_absolute_expression_and_terminator (&mask
) != ',')
12898 as_warn (_("Bad .mask/.fmask directive"));
12899 --input_line_pointer
;
12900 demand_empty_rest_of_line ();
12904 off
= get_absolute_expression ();
12906 if (reg_type
== 'F')
12908 cur_proc_ptr
->fpreg_mask
= mask
;
12909 cur_proc_ptr
->fpreg_offset
= off
;
12913 cur_proc_ptr
->reg_mask
= mask
;
12914 cur_proc_ptr
->reg_offset
= off
;
12917 demand_empty_rest_of_line ();
12919 s_ignore (reg_type
);
12920 #endif /* MIPS_STABS_ELF */
12923 /* The .loc directive. */
12934 assert (now_seg
== text_section
);
12936 lineno
= get_number ();
12937 addroff
= frag_now_fix ();
12939 symbolP
= symbol_new ("", N_SLINE
, addroff
, frag_now
);
12940 S_SET_TYPE (symbolP
, N_SLINE
);
12941 S_SET_OTHER (symbolP
, 0);
12942 S_SET_DESC (symbolP
, lineno
);
12943 symbolP
->sy_segment
= now_seg
;
12947 /* CPU name/ISA/number mapping table.
12949 Entries are grouped by type. The first matching CPU or ISA entry
12950 gets chosen by CPU or ISA, so it should be the 'canonical' name
12951 for that type. Entries after that within the type are sorted
12954 Case is ignored in comparison, so put the canonical entry in the
12955 appropriate case but everything else in lower case to ease eye pain. */
12956 static const struct mips_cpu_info mips_cpu_info_table
[] =
12959 { "MIPS1", 1, ISA_MIPS1
, CPU_R3000
, },
12960 { "mips", 1, ISA_MIPS1
, CPU_R3000
, },
12963 { "MIPS2", 1, ISA_MIPS2
, CPU_R6000
, },
12966 { "MIPS3", 1, ISA_MIPS3
, CPU_R4000
, },
12969 { "MIPS4", 1, ISA_MIPS4
, CPU_R8000
, },
12972 { "MIPS5", 1, ISA_MIPS5
, CPU_MIPS5
, },
12973 { "Generic-MIPS5", 0, ISA_MIPS5
, CPU_MIPS5
, },
12976 { "MIPS32", 1, ISA_MIPS32
, CPU_MIPS32
, },
12977 { "mipsisa32", 0, ISA_MIPS32
, CPU_MIPS32
, },
12978 { "Generic-MIPS32", 0, ISA_MIPS32
, CPU_MIPS32
, },
12979 { "4kc", 0, ISA_MIPS32
, CPU_MIPS32
, },
12980 { "4km", 0, ISA_MIPS32
, CPU_MIPS32
, },
12981 { "4kp", 0, ISA_MIPS32
, CPU_MIPS32
, },
12983 /* For historical reasons. */
12984 { "MIPS64", 1, ISA_MIPS3
, CPU_R4000
, },
12987 { "mipsisa64", 1, ISA_MIPS64
, CPU_MIPS64
, },
12988 { "Generic-MIPS64", 0, ISA_MIPS64
, CPU_MIPS64
, },
12989 { "5kc", 0, ISA_MIPS64
, CPU_MIPS64
, },
12990 { "20kc", 0, ISA_MIPS64
, CPU_MIPS64
, },
12993 { "R2000", 0, ISA_MIPS1
, CPU_R2000
, },
12994 { "2000", 0, ISA_MIPS1
, CPU_R2000
, },
12995 { "2k", 0, ISA_MIPS1
, CPU_R2000
, },
12996 { "r2k", 0, ISA_MIPS1
, CPU_R2000
, },
12999 { "R3000", 0, ISA_MIPS1
, CPU_R3000
, },
13000 { "3000", 0, ISA_MIPS1
, CPU_R3000
, },
13001 { "3k", 0, ISA_MIPS1
, CPU_R3000
, },
13002 { "r3k", 0, ISA_MIPS1
, CPU_R3000
, },
13005 { "R3900", 0, ISA_MIPS1
, CPU_R3900
, },
13006 { "3900", 0, ISA_MIPS1
, CPU_R3900
, },
13007 { "mipstx39", 0, ISA_MIPS1
, CPU_R3900
, },
13010 { "R4000", 0, ISA_MIPS3
, CPU_R4000
, },
13011 { "4000", 0, ISA_MIPS3
, CPU_R4000
, },
13012 { "4k", 0, ISA_MIPS3
, CPU_R4000
, }, /* beware */
13013 { "r4k", 0, ISA_MIPS3
, CPU_R4000
, },
13016 { "R4010", 0, ISA_MIPS2
, CPU_R4010
, },
13017 { "4010", 0, ISA_MIPS2
, CPU_R4010
, },
13020 { "R4400", 0, ISA_MIPS3
, CPU_R4400
, },
13021 { "4400", 0, ISA_MIPS3
, CPU_R4400
, },
13024 { "R4600", 0, ISA_MIPS3
, CPU_R4600
, },
13025 { "4600", 0, ISA_MIPS3
, CPU_R4600
, },
13026 { "mips64orion", 0, ISA_MIPS3
, CPU_R4600
, },
13027 { "orion", 0, ISA_MIPS3
, CPU_R4600
, },
13030 { "R4650", 0, ISA_MIPS3
, CPU_R4650
, },
13031 { "4650", 0, ISA_MIPS3
, CPU_R4650
, },
13034 { "R6000", 0, ISA_MIPS2
, CPU_R6000
, },
13035 { "6000", 0, ISA_MIPS2
, CPU_R6000
, },
13036 { "6k", 0, ISA_MIPS2
, CPU_R6000
, },
13037 { "r6k", 0, ISA_MIPS2
, CPU_R6000
, },
13040 { "R8000", 0, ISA_MIPS4
, CPU_R8000
, },
13041 { "8000", 0, ISA_MIPS4
, CPU_R8000
, },
13042 { "8k", 0, ISA_MIPS4
, CPU_R8000
, },
13043 { "r8k", 0, ISA_MIPS4
, CPU_R8000
, },
13046 { "R10000", 0, ISA_MIPS4
, CPU_R10000
, },
13047 { "10000", 0, ISA_MIPS4
, CPU_R10000
, },
13048 { "10k", 0, ISA_MIPS4
, CPU_R10000
, },
13049 { "r10k", 0, ISA_MIPS4
, CPU_R10000
, },
13052 { "R12000", 0, ISA_MIPS4
, CPU_R12000
, },
13053 { "12000", 0, ISA_MIPS4
, CPU_R12000
, },
13054 { "12k", 0, ISA_MIPS4
, CPU_R12000
, },
13055 { "r12k", 0, ISA_MIPS4
, CPU_R12000
, },
13058 { "VR4100", 0, ISA_MIPS3
, CPU_VR4100
, },
13059 { "4100", 0, ISA_MIPS3
, CPU_VR4100
, },
13060 { "mips64vr4100", 0, ISA_MIPS3
, CPU_VR4100
, },
13061 { "r4100", 0, ISA_MIPS3
, CPU_VR4100
, },
13064 { "VR4111", 0, ISA_MIPS3
, CPU_R4111
, },
13065 { "4111", 0, ISA_MIPS3
, CPU_R4111
, },
13066 { "mips64vr4111", 0, ISA_MIPS3
, CPU_R4111
, },
13067 { "r4111", 0, ISA_MIPS3
, CPU_R4111
, },
13070 { "VR4300", 0, ISA_MIPS3
, CPU_R4300
, },
13071 { "4300", 0, ISA_MIPS3
, CPU_R4300
, },
13072 { "mips64vr4300", 0, ISA_MIPS3
, CPU_R4300
, },
13073 { "r4300", 0, ISA_MIPS3
, CPU_R4300
, },
13076 { "VR5000", 0, ISA_MIPS4
, CPU_R5000
, },
13077 { "5000", 0, ISA_MIPS4
, CPU_R5000
, },
13078 { "5k", 0, ISA_MIPS4
, CPU_R5000
, },
13079 { "mips64vr5000", 0, ISA_MIPS4
, CPU_R5000
, },
13080 { "r5000", 0, ISA_MIPS4
, CPU_R5000
, },
13081 { "r5200", 0, ISA_MIPS4
, CPU_R5000
, },
13082 { "rm5200", 0, ISA_MIPS4
, CPU_R5000
, },
13083 { "r5230", 0, ISA_MIPS4
, CPU_R5000
, },
13084 { "rm5230", 0, ISA_MIPS4
, CPU_R5000
, },
13085 { "r5231", 0, ISA_MIPS4
, CPU_R5000
, },
13086 { "rm5231", 0, ISA_MIPS4
, CPU_R5000
, },
13087 { "r5261", 0, ISA_MIPS4
, CPU_R5000
, },
13088 { "rm5261", 0, ISA_MIPS4
, CPU_R5000
, },
13089 { "r5721", 0, ISA_MIPS4
, CPU_R5000
, },
13090 { "rm5721", 0, ISA_MIPS4
, CPU_R5000
, },
13091 { "r5k", 0, ISA_MIPS4
, CPU_R5000
, },
13092 { "r7000", 0, ISA_MIPS4
, CPU_R5000
, },
13094 /* Broadcom SB-1 CPU */
13095 { "SB-1", 0, ISA_MIPS64
, CPU_SB1
, },
13096 { "sb-1250", 0, ISA_MIPS64
, CPU_SB1
, },
13097 { "sb1", 0, ISA_MIPS64
, CPU_SB1
, },
13098 { "sb1250", 0, ISA_MIPS64
, CPU_SB1
, },
13101 { NULL
, 0, 0, 0, },
13104 static const struct mips_cpu_info
*
13105 mips_cpu_info_from_name (name
)
13110 for (i
= 0; mips_cpu_info_table
[i
].name
!= NULL
; i
++)
13111 if (strcasecmp (name
, mips_cpu_info_table
[i
].name
) == 0)
13112 return (&mips_cpu_info_table
[i
]);
13117 static const struct mips_cpu_info
*
13118 mips_cpu_info_from_isa (isa
)
13123 for (i
= 0; mips_cpu_info_table
[i
].name
!= NULL
; i
++)
13124 if (mips_cpu_info_table
[i
].is_isa
13125 && isa
== mips_cpu_info_table
[i
].isa
)
13126 return (&mips_cpu_info_table
[i
]);
13131 static const struct mips_cpu_info
*
13132 mips_cpu_info_from_cpu (cpu
)
13137 for (i
= 0; mips_cpu_info_table
[i
].name
!= NULL
; i
++)
13138 if (!mips_cpu_info_table
[i
].is_isa
13139 && cpu
== mips_cpu_info_table
[i
].cpu
)
13140 return (&mips_cpu_info_table
[i
]);