1 /* tc-mips.c -- assemble code for a MIPS chip.
2 Copyright (C) 1993 Free Software Foundation, Inc.
3 Contributed by the OSF and Ralph Campbell.
4 Written by Keith Knowles and Ralph Campbell, working independently.
5 Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus
8 This file is part of GAS.
10 GAS is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 2, or (at your option)
15 GAS is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with GAS; see the file COPYING. If not, write to
22 the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */
27 #include "libiberty.h"
42 #endif /* NO_VARARGS */
43 #endif /* NO_STDARG */
45 #include "opcode/mips.h"
50 static char *mips_regmask_frag
;
54 #define PIC_CALL_REG 25
62 /* Decide whether to do GP reference optimizations based on the object
72 /* The default target format to use. */
74 #ifdef TARGET_BYTES_BIG_ENDIAN
75 #define DEFAULT_TARGET_FORMAT "a.out-mips-big"
77 #define DEFAULT_TARGET_FORMAT "a.out-mips-little"
81 #ifdef TARGET_BYTES_BIG_ENDIAN
82 #define DEFAULT_TARGET_FORMAT "ecoff-bigmips"
84 #define DEFAULT_TARGET_FORMAT "ecoff-littlemips"
86 #endif /* OBJ_ECOFF */
88 #ifdef TARGET_BYTES_BIG_ENDIAN
89 #define DEFAULT_TARGET_FORMAT "elf32-bigmips"
91 #define DEFAULT_TARGET_FORMAT "elf32-littlemips"
95 const char *mips_target_format
= DEFAULT_TARGET_FORMAT
;
97 /* The name of the readonly data section. */
99 #define RDATA_SECTION_NAME ".data"
102 #define RDATA_SECTION_NAME ".rdata"
105 #define RDATA_SECTION_NAME ".rodata"
108 /* These variables are filled in with the masks of registers used.
109 The object format code reads them and puts them in the appropriate
111 unsigned long mips_gprmask
;
112 unsigned long mips_cprmask
[4];
114 /* MIPS ISA (Instruction Set Architecture) level (may be changed
115 temporarily using .set mipsN). */
116 static int mips_isa
= -1;
118 /* MIPS ISA we are using for this output file. */
119 static int file_mips_isa
;
121 /* The CPU type as a number: 2000, 3000, 4000, 4400, etc. */
122 static int mips_cpu
= -1;
124 /* Whether the 4650 instructions (mad/madu) are permitted. */
125 static int mips_4650
= -1;
127 /* MIPS PIC level. */
131 /* Do not generate PIC code. */
134 /* Generate PIC code as in Irix 4. This is not implemented, and I'm
135 not sure what it is supposed to do. */
138 /* Generate PIC code as in the SVR4 MIPS ABI. */
141 /* Generate PIC code without using a global offset table: the data
142 segment has a maximum size of 64K, all data references are off
143 the $gp register, and all text references are PC relative. This
144 is used on some embedded systems. */
148 static enum mips_pic_level mips_pic
;
150 /* 1 if trap instructions should used for overflow rather than break
152 static int mips_trap
;
154 static int mips_warn_about_macros
;
155 static int mips_noreorder
;
156 static int mips_any_noreorder
;
157 static int mips_nomove
;
158 static int mips_noat
;
159 static int mips_nobopt
;
162 /* The size of the small data section. */
163 static int g_switch_value
= 8;
164 /* Whether the -G option was used. */
165 static int g_switch_seen
= 0;
171 /* If we can determine in advance that GP optimization won't be
172 possible, we can skip the relaxation stuff that tries to produce
173 GP-relative references. This makes delay slot optimization work
176 This function can only provide a guess, but it seems to work for
177 gcc output. If it guesses wrong, the only loss should be in
178 efficiency; it shouldn't introduce any bugs.
180 I don't know if a fix is needed for the SVR4_PIC mode. I've only
181 fixed it for the non-PIC mode. KR 95/04/07 */
182 static int nopic_need_relax
PARAMS ((symbolS
*));
184 /* handle of the OPCODE hash table */
185 static struct hash_control
*op_hash
= NULL
;
187 /* This array holds the chars that always start a comment. If the
188 pre-processor is disabled, these aren't very useful */
189 const char comment_chars
[] = "#";
191 /* This array holds the chars that only start a comment at the beginning of
192 a line. If the line seems to have the form '# 123 filename'
193 .line and .file directives will appear in the pre-processed output */
194 /* Note that input_file.c hand checks for '#' at the beginning of the
195 first line of the input file. This is because the compiler outputs
196 #NO_APP at the beginning of its output. */
197 /* Also note that C style comments are always supported. */
198 const char line_comment_chars
[] = "#";
200 /* This array holds machine specific line separator characters. */
201 const char line_separator_chars
[] = "";
203 /* Chars that can be used to separate mant from exp in floating point nums */
204 const char EXP_CHARS
[] = "eE";
206 /* Chars that mean this number is a floating point constant */
209 const char FLT_CHARS
[] = "rRsSfFdDxXpP";
211 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
212 changed in read.c . Ideally it shouldn't have to know about it at all,
213 but nothing is ideal around here.
216 static char *insn_error
;
218 static int byte_order
= BYTE_ORDER
;
220 static int auto_align
= 1;
222 /* Symbol labelling the current insn. */
223 static symbolS
*insn_label
;
225 /* When outputting SVR4 PIC code, the assembler needs to know the
226 offset in the stack frame from which to restore the $gp register.
227 This is set by the .cprestore pseudo-op, and saved in this
229 static offsetT mips_cprestore_offset
= -1;
231 /* This is the register which holds the stack frame, as set by the
232 .frame pseudo-op. This is needed to implement .cprestore. */
233 static int mips_frame_reg
= SP
;
235 /* To output NOP instructions correctly, we need to keep information
236 about the previous two instructions. */
238 /* Whether we are optimizing. The default value of 2 means to remove
239 unneeded NOPs and swap branch instructions when possible. A value
240 of 1 means to not swap branches. A value of 0 means to always
242 static int mips_optimize
= 2;
244 /* The previous instruction. */
245 static struct mips_cl_insn prev_insn
;
247 /* The instruction before prev_insn. */
248 static struct mips_cl_insn prev_prev_insn
;
250 /* If we don't want information for prev_insn or prev_prev_insn, we
251 point the insn_mo field at this dummy integer. */
252 static const struct mips_opcode dummy_opcode
= { 0 };
254 /* Non-zero if prev_insn is valid. */
255 static int prev_insn_valid
;
257 /* The frag for the previous instruction. */
258 static struct frag
*prev_insn_frag
;
260 /* The offset into prev_insn_frag for the previous instruction. */
261 static long prev_insn_where
;
263 /* The reloc for the previous instruction, if any. */
264 static fixS
*prev_insn_fixp
;
266 /* Non-zero if the previous instruction was in a delay slot. */
267 static int prev_insn_is_delay_slot
;
269 /* Non-zero if the previous instruction was in a .set noreorder. */
270 static int prev_insn_unreordered
;
272 /* Non-zero if the previous previous instruction was in a .set
274 static int prev_prev_insn_unreordered
;
276 /* Since the MIPS does not have multiple forms of PC relative
277 instructions, we do not have to do relaxing as is done on other
278 platforms. However, we do have to handle GP relative addressing
279 correctly, which turns out to be a similar problem.
281 Every macro that refers to a symbol can occur in (at least) two
282 forms, one with GP relative addressing and one without. For
283 example, loading a global variable into a register generally uses
284 a macro instruction like this:
286 If i can be addressed off the GP register (this is true if it is in
287 the .sbss or .sdata section, or if it is known to be smaller than
288 the -G argument) this will generate the following instruction:
290 This instruction will use a GPREL reloc. If i can not be addressed
291 off the GP register, the following instruction sequence will be used:
294 In this case the first instruction will have a HI16 reloc, and the
295 second reloc will have a LO16 reloc. Both relocs will be against
298 The issue here is that we may not know whether i is GP addressable
299 until after we see the instruction that uses it. Therefore, we
300 want to be able to choose the final instruction sequence only at
301 the end of the assembly. This is similar to the way other
302 platforms choose the size of a PC relative instruction only at the
305 When generating position independent code we do not use GP
306 addressing in quite the same way, but the issue still arises as
307 external symbols and local symbols must be handled differently.
309 We handle these issues by actually generating both possible
310 instruction sequences. The longer one is put in a frag_var with
311 type rs_machine_dependent. We encode what to do with the frag in
312 the subtype field. We encode (1) the number of existing bytes to
313 replace, (2) the number of new bytes to use, (3) the offset from
314 the start of the existing bytes to the first reloc we must generate
315 (that is, the offset is applied from the start of the existing
316 bytes after they are replaced by the new bytes, if any), (4) the
317 offset from the start of the existing bytes to the second reloc,
318 (5) whether a third reloc is needed (the third reloc is always four
319 bytes after the second reloc), and (6) whether to warn if this
320 variant is used (this is sometimes needed if .set nomacro or .set
321 noat is in effect). All these numbers are reasonably small.
323 Generating two instruction sequences must be handled carefully to
324 ensure that delay slots are handled correctly. Fortunately, there
325 are a limited number of cases. When the second instruction
326 sequence is generated, append_insn is directed to maintain the
327 existing delay slot information, so it continues to apply to any
328 code after the second instruction sequence. This means that the
329 second instruction sequence must not impose any requirements not
330 required by the first instruction sequence.
332 These variant frags are then handled in functions called by the
333 machine independent code. md_estimate_size_before_relax returns
334 the final size of the frag. md_convert_frag sets up the final form
335 of the frag. tc_gen_reloc adjust the first reloc and adds a second
337 #define RELAX_ENCODE(old, new, reloc1, reloc2, reloc3, warn) \
341 | (((reloc1) + 64) << 9) \
342 | (((reloc2) + 64) << 2) \
343 | ((reloc3) ? (1 << 1) : 0) \
345 #define RELAX_OLD(i) (((i) >> 24) & 0xff)
346 #define RELAX_NEW(i) (((i) >> 16) & 0xff)
347 #define RELAX_RELOC1(i) ((bfd_vma)(((i) >> 9) & 0x7f) - 64)
348 #define RELAX_RELOC2(i) ((bfd_vma)(((i) >> 2) & 0x7f) - 64)
349 #define RELAX_RELOC3(i) (((i) >> 1) & 1)
350 #define RELAX_WARN(i) ((i) & 1)
352 /* Prototypes for static functions. */
355 #define internalError() \
356 as_fatal ("internal Error, line %d, %s", __LINE__, __FILE__)
358 #define internalError() as_fatal ("MIPS internal Error");
361 static int insn_uses_reg
PARAMS ((struct mips_cl_insn
*ip
,
362 unsigned int reg
, int fpr
));
363 static void append_insn
PARAMS ((char *place
,
364 struct mips_cl_insn
* ip
,
366 bfd_reloc_code_real_type r
));
367 static void mips_no_prev_insn
PARAMS ((void));
368 static void mips_emit_delays
PARAMS ((void));
369 static void macro_build
PARAMS ((char *place
, int *counter
, expressionS
* ep
,
370 const char *name
, const char *fmt
,
372 static void macro_build_lui
PARAMS ((char *place
, int *counter
,
373 expressionS
* ep
, int regnum
));
374 static void set_at
PARAMS ((int *counter
, int reg
, int unsignedp
));
375 static void check_absolute_expr
PARAMS ((struct mips_cl_insn
* ip
,
377 static void load_register
PARAMS ((int *, int, expressionS
*, int));
378 static void load_address
PARAMS ((int *counter
, int reg
, expressionS
*ep
));
379 static void macro
PARAMS ((struct mips_cl_insn
* ip
));
380 #ifdef LOSING_COMPILER
381 static void macro2
PARAMS ((struct mips_cl_insn
* ip
));
383 static void mips_ip
PARAMS ((char *str
, struct mips_cl_insn
* ip
));
384 static int my_getSmallExpression
PARAMS ((expressionS
* ep
, char *str
));
385 static void my_getExpression
PARAMS ((expressionS
* ep
, char *str
));
386 static symbolS
*get_symbol
PARAMS ((void));
387 static void mips_align
PARAMS ((int to
, int fill
, symbolS
*label
));
388 static void s_align
PARAMS ((int));
389 static void s_stringer
PARAMS ((int));
390 static void s_change_sec
PARAMS ((int));
391 static void s_cons
PARAMS ((int));
392 static void s_err
PARAMS ((int));
393 static void s_extern
PARAMS ((int));
394 static void s_float_cons
PARAMS ((int));
395 static void s_mips_globl
PARAMS ((int));
396 static void s_option
PARAMS ((int));
397 static void s_mipsset
PARAMS ((int));
398 static void s_mips_space
PARAMS ((int));
399 static void s_abicalls
PARAMS ((int));
400 static void s_cpload
PARAMS ((int));
401 static void s_cprestore
PARAMS ((int));
402 static void s_gpword
PARAMS ((int));
403 static void s_cpadd
PARAMS ((int));
404 #ifndef ECOFF_DEBUGGING
405 static void md_obj_begin
PARAMS ((void));
406 static void md_obj_end
PARAMS ((void));
407 static long get_number
PARAMS ((void));
408 static void s_ent
PARAMS ((int));
409 static void s_mipsend
PARAMS ((int));
410 static void s_file
PARAMS ((int));
412 static void s_frame
PARAMS ((int));
413 static void s_loc
PARAMS ((int));
414 static void s_mask
PARAMS ((char));
418 static void s_elf_section
PARAMS ((int));
423 The following pseudo-ops from the Kane and Heinrich MIPS book
424 should be defined here, but are currently unsupported: .alias,
425 .galive, .gjaldef, .gjrlive, .livereg, .noalias.
427 The following pseudo-ops from the Kane and Heinrich MIPS book are
428 specific to the type of debugging information being generated, and
429 should be defined by the object format: .aent, .begin, .bend,
430 .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp,
433 The following pseudo-ops from the Kane and Heinrich MIPS book are
434 not MIPS CPU specific, but are also not specific to the object file
435 format. This file is probably the best place to define them, but
436 they are not currently supported: .asm0, .endr, .lab, .repeat,
437 .struct, .weakext. */
439 const pseudo_typeS md_pseudo_table
[] =
441 /* MIPS specific pseudo-ops. */
442 {"option", s_option
, 0},
443 {"set", s_mipsset
, 0},
444 {"rdata", s_change_sec
, 'r'},
445 {"sdata", s_change_sec
, 's'},
446 {"livereg", s_ignore
, 0},
447 { "abicalls", s_abicalls
, 0},
448 { "cpload", s_cpload
, 0},
449 { "cprestore", s_cprestore
, 0},
450 { "gpword", s_gpword
, 0},
451 { "cpadd", s_cpadd
, 0},
453 /* Relatively generic pseudo-ops that happen to be used on MIPS
455 {"asciiz", s_stringer
, 1},
456 {"bss", s_change_sec
, 'b'},
459 {"dword", s_cons
, 3},
461 /* These pseudo-ops are defined in read.c, but must be overridden
462 here for one reason or another. */
463 {"align", s_align
, 0},
464 {"ascii", s_stringer
, 0},
465 {"asciz", s_stringer
, 1},
467 {"data", s_change_sec
, 'd'},
468 {"double", s_float_cons
, 'd'},
469 {"extern", s_extern
, 0},
470 {"float", s_float_cons
, 'f'},
471 {"globl", s_mips_globl
, 0},
472 {"global", s_mips_globl
, 0},
473 {"hword", s_cons
, 1},
478 {"short", s_cons
, 1},
479 {"single", s_float_cons
, 'f'},
480 {"space", s_mips_space
, 0},
481 {"text", s_change_sec
, 't'},
484 #ifndef ECOFF_DEBUGGING
485 /* These pseudo-ops should be defined by the object file format.
486 However, a.out doesn't support them, so we have versions here. */
488 {"bgnb", s_ignore
, 0},
489 {"end", s_mipsend
, 0},
490 {"endb", s_ignore
, 0},
493 {"fmask", s_ignore
, 'F'},
494 {"frame", s_ignore
, 0},
495 {"loc", s_ignore
, 0},
496 {"mask", s_ignore
, 'R'},
497 {"verstamp", s_ignore
, 0},
501 /* We need to tweak the ELF ".section" pseudo-op a bit. */
502 {"section", s_elf_section
, 0},
504 /* Redirect additional ELF data allocation pseudo-ops. */
505 {"2byte", s_cons
, 2},
506 {"4byte", s_cons
, 4},
507 {"8byte", s_cons
, 8},
514 const relax_typeS md_relax_table
[] =
519 static char *expr_end
;
521 static expressionS imm_expr
;
522 static expressionS offset_expr
;
523 static bfd_reloc_code_real_type imm_reloc
;
524 static bfd_reloc_code_real_type offset_reloc
;
526 /* FIXME: This should be handled in a different way. */
527 extern int target_big_endian
;
530 * This function is called once, at assembler startup time. It should
531 * set up all the tables, etc. that the MD part of the assembler will need.
537 register const char *retval
= NULL
;
538 register unsigned int i
= 0;
546 if (strcmp (cpu
+ (sizeof TARGET_CPU
) - 3, "el") == 0)
548 a
= xmalloc (sizeof TARGET_CPU
);
549 strcpy (a
, TARGET_CPU
);
550 a
[(sizeof TARGET_CPU
) - 3] = '\0';
554 if (strcmp (cpu
, "mips") == 0)
560 else if (strcmp (cpu
, "r6000") == 0
561 || strcmp (cpu
, "mips2") == 0)
567 else if (strcmp (cpu
, "mips64") == 0
568 || strcmp (cpu
, "r4000") == 0
569 || strcmp (cpu
, "mips3") == 0)
575 else if (strcmp (cpu
, "r4400") == 0)
581 else if (strcmp (cpu
, "mips64orion") == 0
582 || strcmp (cpu
, "r4600") == 0)
588 else if (strcmp (cpu
, "r4650") == 0)
596 else if (strcmp (cpu
, "r8000") == 0
597 || strcmp (cpu
, "mips4") == 0)
603 else if (strcmp (cpu
, "r10000") == 0)
623 if (mips_isa
< 2 && mips_trap
)
624 as_bad ("trap exception not supported at ISA 1");
629 ok
= bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, 3000);
632 ok
= bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, 6000);
635 ok
= bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, 4000);
638 ok
= bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, 8000);
642 as_warn ("Could not set architecture and machine");
644 file_mips_isa
= mips_isa
;
646 op_hash
= hash_new ();
648 for (i
= 0; i
< NUMOPCODES
;)
650 const char *name
= mips_opcodes
[i
].name
;
652 retval
= hash_insert (op_hash
, name
, (PTR
) &mips_opcodes
[i
]);
655 fprintf (stderr
, "internal error: can't hash `%s': %s\n",
656 mips_opcodes
[i
].name
, retval
);
657 as_fatal ("Broken assembler. No assembly attempted.");
661 if (mips_opcodes
[i
].pinfo
!= INSN_MACRO
662 && ((mips_opcodes
[i
].match
& mips_opcodes
[i
].mask
)
663 != mips_opcodes
[i
].match
))
665 fprintf (stderr
, "internal error: bad opcode: `%s' \"%s\"\n",
666 mips_opcodes
[i
].name
, mips_opcodes
[i
].args
);
667 as_fatal ("Broken assembler. No assembly attempted.");
671 while ((i
< NUMOPCODES
) && !strcmp (mips_opcodes
[i
].name
, name
));
674 mips_no_prev_insn ();
682 /* set the default alignment for the text section (2**2) */
683 record_alignment (text_section
, 2);
685 /* FIXME: This should be handled in a different way. */
686 target_big_endian
= byte_order
== BIG_ENDIAN
;
689 bfd_set_gp_size (stdoutput
, g_switch_value
);
693 /* Sections must be aligned to 16 byte boundaries. */
694 (void) bfd_set_section_alignment (stdoutput
, text_section
, 4);
695 (void) bfd_set_section_alignment (stdoutput
, data_section
, 4);
696 (void) bfd_set_section_alignment (stdoutput
, bss_section
, 4);
698 /* Create a .reginfo section for register masks and a .mdebug
699 section for debugging information. */
707 sec
= subseg_new (".reginfo", (subsegT
) 0);
709 /* The ABI says this section should be loaded so that the running
710 program can access it. */
711 (void) bfd_set_section_flags (stdoutput
, sec
,
712 (SEC_ALLOC
| SEC_LOAD
713 | SEC_READONLY
| SEC_DATA
));
714 (void) bfd_set_section_alignment (stdoutput
, sec
, 2);
716 mips_regmask_frag
= frag_more (sizeof (Elf32_External_RegInfo
));
718 #ifdef ECOFF_DEBUGGING
719 sec
= subseg_new (".mdebug", (subsegT
) 0);
720 (void) bfd_set_section_flags (stdoutput
, sec
,
721 SEC_HAS_CONTENTS
| SEC_READONLY
);
722 (void) bfd_set_section_alignment (stdoutput
, sec
, 2);
725 subseg_set (seg
, subseg
);
729 #ifndef ECOFF_DEBUGGING
737 #ifndef ECOFF_DEBUGGING
746 struct mips_cl_insn insn
;
748 imm_expr
.X_op
= O_absent
;
749 offset_expr
.X_op
= O_absent
;
751 mips_ip (str
, &insn
);
754 as_bad ("%s `%s'", insn_error
, str
);
757 if (insn
.insn_mo
->pinfo
== INSN_MACRO
)
763 if (imm_expr
.X_op
!= O_absent
)
764 append_insn ((char *) NULL
, &insn
, &imm_expr
, imm_reloc
);
765 else if (offset_expr
.X_op
!= O_absent
)
766 append_insn ((char *) NULL
, &insn
, &offset_expr
, offset_reloc
);
768 append_insn ((char *) NULL
, &insn
, NULL
, BFD_RELOC_UNUSED
);
772 /* See whether instruction IP reads register REG. If FPR is non-zero,
773 REG is a floating point register. */
776 insn_uses_reg (ip
, reg
, fpr
)
777 struct mips_cl_insn
*ip
;
781 /* Don't report on general register 0, since it never changes. */
782 if (! fpr
&& reg
== 0)
787 /* If we are called with either $f0 or $f1, we must check $f0.
788 This is not optimal, because it will introduce an unnecessary
789 NOP between "lwc1 $f0" and "swc1 $f1". To fix this we would
790 need to distinguish reading both $f0 and $f1 or just one of
791 them. Note that we don't have to check the other way,
792 because there is no instruction that sets both $f0 and $f1
793 and requires a delay. */
794 if ((ip
->insn_mo
->pinfo
& INSN_READ_FPR_S
)
795 && (((ip
->insn_opcode
>> OP_SH_FS
) & OP_MASK_FS
)
796 == (reg
&~ (unsigned) 1)))
798 if ((ip
->insn_mo
->pinfo
& INSN_READ_FPR_T
)
799 && (((ip
->insn_opcode
>> OP_SH_FT
) & OP_MASK_FT
)
800 == (reg
&~ (unsigned) 1)))
805 if ((ip
->insn_mo
->pinfo
& INSN_READ_GPR_S
)
806 && ((ip
->insn_opcode
>> OP_SH_RS
) & OP_MASK_RS
) == reg
)
808 if ((ip
->insn_mo
->pinfo
& INSN_READ_GPR_T
)
809 && ((ip
->insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
) == reg
)
816 /* Output an instruction. PLACE is where to put the instruction; if
817 it is NULL, this uses frag_more to get room. IP is the instruction
818 information. ADDRESS_EXPR is an operand of the instruction to be
819 used with RELOC_TYPE. */
822 append_insn (place
, ip
, address_expr
, reloc_type
)
824 struct mips_cl_insn
*ip
;
825 expressionS
*address_expr
;
826 bfd_reloc_code_real_type reloc_type
;
828 register unsigned long prev_pinfo
, pinfo
;
833 prev_pinfo
= prev_insn
.insn_mo
->pinfo
;
834 pinfo
= ip
->insn_mo
->pinfo
;
836 if (place
== NULL
&& ! mips_noreorder
)
838 /* If the previous insn required any delay slots, see if we need
839 to insert a NOP or two. There are eight kinds of possible
840 hazards, of which an instruction can have at most one type.
841 (1) a load from memory delay
842 (2) a load from a coprocessor delay
843 (3) an unconditional branch delay
844 (4) a conditional branch delay
845 (5) a move to coprocessor register delay
846 (6) a load coprocessor register from memory delay
847 (7) a coprocessor condition code delay
848 (8) a HI/LO special register delay
850 There are a lot of optimizations we could do that we don't.
851 In particular, we do not, in general, reorder instructions.
852 If you use gcc with optimization, it will reorder
853 instructions and generally do much more optimization then we
854 do here; repeating all that work in the assembler would only
855 benefit hand written assembly code, and does not seem worth
858 /* This is how a NOP is emitted. */
859 #define emit_nop() md_number_to_chars (frag_more (4), 0, 4)
861 /* The previous insn might require a delay slot, depending upon
862 the contents of the current insn. */
864 && ((prev_pinfo
& INSN_LOAD_COPROC_DELAY
)
866 && (prev_pinfo
& INSN_LOAD_MEMORY_DELAY
))))
868 /* A load from a coprocessor or from memory. All load
869 delays delay the use of general register rt for one
870 instruction on the r3000. The r6000 and r4000 use
872 know (prev_pinfo
& INSN_WRITE_GPR_T
);
873 if (mips_optimize
== 0
874 || insn_uses_reg (ip
,
875 ((prev_insn
.insn_opcode
>> OP_SH_RT
)
880 else if (mips_isa
< 4
881 && ((prev_pinfo
& INSN_COPROC_MOVE_DELAY
)
883 && (prev_pinfo
& INSN_COPROC_MEMORY_DELAY
))))
885 /* A generic coprocessor delay. The previous instruction
886 modified a coprocessor general or control register. If
887 it modified a control register, we need to avoid any
888 coprocessor instruction (this is probably not always
889 required, but it sometimes is). If it modified a general
890 register, we avoid using that register.
892 On the r6000 and r4000 loading a coprocessor register
893 from memory is interlocked, and does not require a delay.
895 This case is not handled very well. There is no special
896 knowledge of CP0 handling, and the coprocessors other
897 than the floating point unit are not distinguished at
899 if (prev_pinfo
& INSN_WRITE_FPR_T
)
901 if (mips_optimize
== 0
902 || insn_uses_reg (ip
,
903 ((prev_insn
.insn_opcode
>> OP_SH_FT
)
908 else if (prev_pinfo
& INSN_WRITE_FPR_S
)
910 if (mips_optimize
== 0
911 || insn_uses_reg (ip
,
912 ((prev_insn
.insn_opcode
>> OP_SH_FS
)
919 /* We don't know exactly what the previous instruction
920 does. If the current instruction uses a coprocessor
921 register, we must insert a NOP. If previous
922 instruction may set the condition codes, and the
923 current instruction uses them, we must insert two
925 if (mips_optimize
== 0
926 || ((prev_pinfo
& INSN_WRITE_COND_CODE
)
927 && (pinfo
& INSN_READ_COND_CODE
)))
929 else if (pinfo
& INSN_COP
)
933 else if (mips_isa
< 4
934 && (prev_pinfo
& INSN_WRITE_COND_CODE
))
936 /* The previous instruction sets the coprocessor condition
937 codes, but does not require a general coprocessor delay
938 (this means it is a floating point comparison
939 instruction). If this instruction uses the condition
940 codes, we need to insert a single NOP. */
941 if (mips_optimize
== 0
942 || (pinfo
& INSN_READ_COND_CODE
))
945 else if (prev_pinfo
& INSN_READ_LO
)
947 /* The previous instruction reads the LO register; if the
948 current instruction writes to the LO register, we must
949 insert two NOPS. The R4650 has interlocks. */
951 && (mips_optimize
== 0
952 || (pinfo
& INSN_WRITE_LO
)))
955 else if (prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
957 /* The previous instruction reads the HI register; if the
958 current instruction writes to the HI register, we must
959 insert a NOP. The R4650 has interlocks. */
961 && (mips_optimize
== 0
962 || (pinfo
& INSN_WRITE_HI
)))
966 /* There are two cases which require two intervening
967 instructions: 1) setting the condition codes using a move to
968 coprocessor instruction which requires a general coprocessor
969 delay and then reading the condition codes 2) reading the HI
970 or LO register and then writing to it (except on the R4650,
971 which has interlocks). If we are not already emitting a NOP
972 instruction, we must check for these cases compared to the
973 instruction previous to the previous instruction. */
976 && (prev_prev_insn
.insn_mo
->pinfo
& INSN_COPROC_MOVE_DELAY
)
977 && (prev_prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
)
978 && (pinfo
& INSN_READ_COND_CODE
))
979 || ((prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
)
980 && (pinfo
& INSN_WRITE_LO
)
982 || ((prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
983 && (pinfo
& INSN_WRITE_HI
)
987 /* If we are being given a nop instruction, don't bother with
988 one of the nops we would otherwise output. This will only
989 happen when a nop instruction is used with mips_optimize set
991 if (nops
> 0 && ip
->insn_opcode
== 0)
994 /* Now emit the right number of NOP instructions. */
999 for (i
= 0; i
< nops
; i
++)
1003 listing_prev_line ();
1004 /* We may be at the start of a variant frag. In case we
1005 are, make sure there is enough space for the frag
1006 after the frags created by listing_prev_line. The
1007 argument to frag_grow here must be at least as large
1008 as the argument to all other calls to frag_grow in
1009 this file. We don't have to worry about being in the
1010 middle of a variant frag, because the variants insert
1011 all needed nop instructions themselves. */
1014 if (insn_label
!= NULL
)
1016 assert (S_GET_SEGMENT (insn_label
) == now_seg
);
1017 insn_label
->sy_frag
= frag_now
;
1018 S_SET_VALUE (insn_label
, (valueT
) frag_now_fix ());
1028 if (address_expr
!= NULL
)
1030 if (address_expr
->X_op
== O_constant
)
1035 ip
->insn_opcode
|= address_expr
->X_add_number
;
1038 case BFD_RELOC_LO16
:
1039 ip
->insn_opcode
|= address_expr
->X_add_number
& 0xffff;
1042 case BFD_RELOC_MIPS_JMP
:
1043 case BFD_RELOC_16_PCREL_S2
:
1052 assert (reloc_type
!= BFD_RELOC_UNUSED
);
1054 /* Don't generate a reloc if we are writing into a variant
1057 fixp
= fix_new_exp (frag_now
, f
- frag_now
->fr_literal
, 4,
1059 reloc_type
== BFD_RELOC_16_PCREL_S2
,
1064 md_number_to_chars (f
, ip
->insn_opcode
, 4);
1066 /* Update the register mask information. */
1067 if (pinfo
& INSN_WRITE_GPR_D
)
1068 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
);
1069 if ((pinfo
& (INSN_WRITE_GPR_T
| INSN_READ_GPR_T
)) != 0)
1070 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
);
1071 if (pinfo
& INSN_READ_GPR_S
)
1072 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> OP_SH_RS
) & OP_MASK_RS
);
1073 if (pinfo
& INSN_WRITE_GPR_31
)
1074 mips_gprmask
|= 1 << 31;
1075 if (pinfo
& INSN_WRITE_FPR_D
)
1076 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FD
) & OP_MASK_FD
);
1077 if ((pinfo
& (INSN_WRITE_FPR_S
| INSN_READ_FPR_S
)) != 0)
1078 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FS
) & OP_MASK_FS
);
1079 if ((pinfo
& (INSN_WRITE_FPR_T
| INSN_READ_FPR_T
)) != 0)
1080 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FT
) & OP_MASK_FT
);
1081 if ((pinfo
& INSN_READ_FPR_R
) != 0)
1082 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FR
) & OP_MASK_FR
);
1083 if (pinfo
& INSN_COP
)
1085 /* We don't keep enough information to sort these cases out. */
1087 /* Never set the bit for $0, which is always zero. */
1088 mips_gprmask
&=~ 1 << 0;
1090 if (place
== NULL
&& ! mips_noreorder
)
1092 /* Filling the branch delay slot is more complex. We try to
1093 switch the branch with the previous instruction, which we can
1094 do if the previous instruction does not set up a condition
1095 that the branch tests and if the branch is not itself the
1096 target of any branch. */
1097 if ((pinfo
& INSN_UNCOND_BRANCH_DELAY
)
1098 || (pinfo
& INSN_COND_BRANCH_DELAY
))
1100 if (mips_optimize
< 2
1101 /* If we have seen .set volatile or .set nomove, don't
1104 /* If we had to emit any NOP instructions, then we
1105 already know we can not swap. */
1107 /* If we don't even know the previous insn, we can not
1109 || ! prev_insn_valid
1110 /* If the previous insn is already in a branch delay
1111 slot, then we can not swap. */
1112 || prev_insn_is_delay_slot
1113 /* If the previous previous insn was in a .set
1114 noreorder, we can't swap. Actually, the MIPS
1115 assembler will swap in this situation. However, gcc
1116 configured -with-gnu-as will generate code like
1122 in which we can not swap the bne and INSN. If gcc is
1123 not configured -with-gnu-as, it does not output the
1124 .set pseudo-ops. We don't have to check
1125 prev_insn_unreordered, because prev_insn_valid will
1126 be 0 in that case. We don't want to use
1127 prev_prev_insn_valid, because we do want to be able
1128 to swap at the start of a function. */
1129 || prev_prev_insn_unreordered
1130 /* If the branch is itself the target of a branch, we
1131 can not swap. We cheat on this; all we check for is
1132 whether there is a label on this instruction. If
1133 there are any branches to anything other than a
1134 label, users must use .set noreorder. */
1135 || insn_label
!= NULL
1136 /* If the previous instruction is in a variant frag, we
1137 can not do the swap. */
1138 || prev_insn_frag
->fr_type
== rs_machine_dependent
1139 /* If the branch reads the condition codes, we don't
1140 even try to swap, because in the sequence
1145 we can not swap, and I don't feel like handling that
1148 && (pinfo
& INSN_READ_COND_CODE
))
1149 /* We can not swap with an instruction that requires a
1150 delay slot, becase the target of the branch might
1151 interfere with that instruction. */
1154 & (INSN_LOAD_COPROC_DELAY
1155 | INSN_COPROC_MOVE_DELAY
1156 | INSN_WRITE_COND_CODE
)))
1163 & (INSN_LOAD_MEMORY_DELAY
1164 | INSN_COPROC_MEMORY_DELAY
)))
1165 /* We can not swap with a branch instruction. */
1167 & (INSN_UNCOND_BRANCH_DELAY
1168 | INSN_COND_BRANCH_DELAY
1169 | INSN_COND_BRANCH_LIKELY
))
1170 /* We do not swap with a trap instruction, since it
1171 complicates trap handlers to have the trap
1172 instruction be in a delay slot. */
1173 || (prev_pinfo
& INSN_TRAP
)
1174 /* If the branch reads a register that the previous
1175 instruction sets, we can not swap. */
1176 || ((prev_pinfo
& INSN_WRITE_GPR_T
)
1177 && insn_uses_reg (ip
,
1178 ((prev_insn
.insn_opcode
>> OP_SH_RT
)
1181 || ((prev_pinfo
& INSN_WRITE_GPR_D
)
1182 && insn_uses_reg (ip
,
1183 ((prev_insn
.insn_opcode
>> OP_SH_RD
)
1186 /* If the branch writes a register that the previous
1187 instruction sets, we can not swap (we know that
1188 branches write only to RD or to $31). */
1189 || ((prev_pinfo
& INSN_WRITE_GPR_T
)
1190 && (((pinfo
& INSN_WRITE_GPR_D
)
1191 && (((prev_insn
.insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
)
1192 == ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)))
1193 || ((pinfo
& INSN_WRITE_GPR_31
)
1194 && (((prev_insn
.insn_opcode
>> OP_SH_RT
)
1197 || ((prev_pinfo
& INSN_WRITE_GPR_D
)
1198 && (((pinfo
& INSN_WRITE_GPR_D
)
1199 && (((prev_insn
.insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)
1200 == ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)))
1201 || ((pinfo
& INSN_WRITE_GPR_31
)
1202 && (((prev_insn
.insn_opcode
>> OP_SH_RD
)
1205 /* If the branch writes a register that the previous
1206 instruction reads, we can not swap (we know that
1207 branches only write to RD or to $31). */
1208 || ((pinfo
& INSN_WRITE_GPR_D
)
1209 && insn_uses_reg (&prev_insn
,
1210 ((ip
->insn_opcode
>> OP_SH_RD
)
1213 || ((pinfo
& INSN_WRITE_GPR_31
)
1214 && insn_uses_reg (&prev_insn
, 31, 0))
1215 /* If we are generating embedded PIC code, the branch
1216 might be expanded into a sequence which uses $at, so
1217 we can't swap with an instruction which reads it. */
1218 || (mips_pic
== EMBEDDED_PIC
1219 && insn_uses_reg (&prev_insn
, AT
, 0))
1220 /* If the previous previous instruction has a load
1221 delay, and sets a register that the branch reads, we
1224 && ((prev_prev_insn
.insn_mo
->pinfo
& INSN_LOAD_COPROC_DELAY
)
1226 && (prev_prev_insn
.insn_mo
->pinfo
1227 & INSN_LOAD_MEMORY_DELAY
)))
1228 && insn_uses_reg (ip
,
1229 ((prev_prev_insn
.insn_opcode
>> OP_SH_RT
)
1233 /* We could do even better for unconditional branches to
1234 portions of this object file; we could pick up the
1235 instruction at the destination, put it in the delay
1236 slot, and bump the destination address. */
1238 /* Update the previous insn information. */
1239 prev_prev_insn
= *ip
;
1240 prev_insn
.insn_mo
= &dummy_opcode
;
1247 /* It looks like we can actually do the swap. */
1248 prev_f
= prev_insn_frag
->fr_literal
+ prev_insn_where
;
1249 memcpy (temp
, prev_f
, 4);
1250 memcpy (prev_f
, f
, 4);
1251 memcpy (f
, temp
, 4);
1254 prev_insn_fixp
->fx_frag
= frag_now
;
1255 prev_insn_fixp
->fx_where
= f
- frag_now
->fr_literal
;
1259 fixp
->fx_frag
= prev_insn_frag
;
1260 fixp
->fx_where
= prev_insn_where
;
1262 /* Update the previous insn information; leave prev_insn
1264 prev_prev_insn
= *ip
;
1266 prev_insn_is_delay_slot
= 1;
1268 /* If that was an unconditional branch, forget the previous
1269 insn information. */
1270 if (pinfo
& INSN_UNCOND_BRANCH_DELAY
)
1272 prev_prev_insn
.insn_mo
= &dummy_opcode
;
1273 prev_insn
.insn_mo
= &dummy_opcode
;
1276 else if (pinfo
& INSN_COND_BRANCH_LIKELY
)
1278 /* We don't yet optimize a branch likely. What we should do
1279 is look at the target, copy the instruction found there
1280 into the delay slot, and increment the branch to jump to
1281 the next instruction. */
1283 /* Update the previous insn information. */
1284 prev_prev_insn
= *ip
;
1285 prev_insn
.insn_mo
= &dummy_opcode
;
1289 /* Update the previous insn information. */
1291 prev_prev_insn
.insn_mo
= &dummy_opcode
;
1293 prev_prev_insn
= prev_insn
;
1296 /* Any time we see a branch, we always fill the delay slot
1297 immediately; since this insn is not a branch, we know it
1298 is not in a delay slot. */
1299 prev_insn_is_delay_slot
= 0;
1302 prev_prev_insn_unreordered
= prev_insn_unreordered
;
1303 prev_insn_unreordered
= 0;
1304 prev_insn_frag
= frag_now
;
1305 prev_insn_where
= f
- frag_now
->fr_literal
;
1306 prev_insn_fixp
= fixp
;
1307 prev_insn_valid
= 1;
1310 /* We just output an insn, so the next one doesn't have a label. */
1314 /* This function forgets that there was any previous instruction or
1318 mips_no_prev_insn ()
1320 prev_insn
.insn_mo
= &dummy_opcode
;
1321 prev_prev_insn
.insn_mo
= &dummy_opcode
;
1322 prev_insn_valid
= 0;
1323 prev_insn_is_delay_slot
= 0;
1324 prev_insn_unreordered
= 0;
1325 prev_prev_insn_unreordered
= 0;
1329 /* This function must be called whenever we turn on noreorder or emit
1330 something other than instructions. It inserts any NOPS which might
1331 be needed by the previous instruction, and clears the information
1332 kept for the previous instructions. */
1337 if (! mips_noreorder
)
1343 && (prev_insn
.insn_mo
->pinfo
1344 & (INSN_LOAD_COPROC_DELAY
1345 | INSN_COPROC_MOVE_DELAY
1346 | INSN_WRITE_COND_CODE
)))
1348 && (prev_insn
.insn_mo
->pinfo
1352 && (prev_insn
.insn_mo
->pinfo
1353 & (INSN_LOAD_MEMORY_DELAY
1354 | INSN_COPROC_MEMORY_DELAY
))))
1358 && (prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
))
1360 && ((prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
1361 || (prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
))))
1364 else if ((mips_isa
< 4
1365 && (prev_prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
))
1367 && ((prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
1368 || (prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
))))
1373 if (insn_label
!= NULL
)
1375 assert (S_GET_SEGMENT (insn_label
) == now_seg
);
1376 insn_label
->sy_frag
= frag_now
;
1377 S_SET_VALUE (insn_label
, (valueT
) frag_now_fix ());
1382 mips_no_prev_insn ();
1385 /* Build an instruction created by a macro expansion. This is passed
1386 a pointer to the count of instructions created so far, an
1387 expression, the name of the instruction to build, an operand format
1388 string, and corresponding arguments. */
1392 macro_build (char *place
,
1398 #else /* ! defined (NO_STDARG) */
1400 macro_build (place
, counter
, ep
, name
, fmt
, va_alist
)
1407 #endif /* ! defined (NO_STDARG) */
1409 struct mips_cl_insn insn
;
1410 bfd_reloc_code_real_type r
;
1414 va_start (args
, fmt
);
1420 * If the macro is about to expand into a second instruction,
1421 * print a warning if needed. We need to pass ip as a parameter
1422 * to generate a better warning message here...
1424 if (mips_warn_about_macros
&& place
== NULL
&& *counter
== 1)
1425 as_warn ("Macro instruction expanded into multiple instructions");
1428 *counter
+= 1; /* bump instruction counter */
1430 r
= BFD_RELOC_UNUSED
;
1431 insn
.insn_mo
= (struct mips_opcode
*) hash_find (op_hash
, name
);
1432 assert (insn
.insn_mo
);
1433 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
1435 while (strcmp (fmt
, insn
.insn_mo
->args
) != 0
1436 || insn
.insn_mo
->pinfo
== INSN_MACRO
)
1439 assert (insn
.insn_mo
->name
);
1440 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
1442 insn
.insn_opcode
= insn
.insn_mo
->match
;
1458 insn
.insn_opcode
|= va_arg (args
, int) << 16;
1464 insn
.insn_opcode
|= va_arg (args
, int) << 16;
1469 insn
.insn_opcode
|= va_arg (args
, int) << 11;
1474 insn
.insn_opcode
|= va_arg (args
, int) << 11;
1481 insn
.insn_opcode
|= va_arg (args
, int) << 6;
1485 insn
.insn_opcode
|= va_arg (args
, int) << 6;
1489 insn
.insn_opcode
|= va_arg (args
, int) << 6;
1496 insn
.insn_opcode
|= va_arg (args
, int) << 21;
1502 r
= (bfd_reloc_code_real_type
) va_arg (args
, int);
1503 assert (r
== BFD_RELOC_MIPS_GPREL
1504 || r
== BFD_RELOC_MIPS_LITERAL
1505 || r
== BFD_RELOC_LO16
1506 || r
== BFD_RELOC_MIPS_GOT16
1507 || r
== BFD_RELOC_MIPS_CALL16
1508 || (ep
->X_op
== O_subtract
1509 && now_seg
== text_section
1510 && r
== BFD_RELOC_PCREL_LO16
));
1514 r
= (bfd_reloc_code_real_type
) va_arg (args
, int);
1516 && (ep
->X_op
== O_constant
1517 || (ep
->X_op
== O_symbol
1518 && (r
== BFD_RELOC_HI16_S
1519 || r
== BFD_RELOC_HI16
))
1520 || (ep
->X_op
== O_subtract
1521 && now_seg
== text_section
1522 && r
== BFD_RELOC_PCREL_HI16_S
)));
1523 if (ep
->X_op
== O_constant
)
1525 insn
.insn_opcode
|= (ep
->X_add_number
>> 16) & 0xffff;
1527 r
= BFD_RELOC_UNUSED
;
1532 assert (ep
!= NULL
);
1534 * This allows macro() to pass an immediate expression for
1535 * creating short branches without creating a symbol.
1536 * Note that the expression still might come from the assembly
1537 * input, in which case the value is not checked for range nor
1538 * is a relocation entry generated (yuck).
1540 if (ep
->X_op
== O_constant
)
1542 insn
.insn_opcode
|= (ep
->X_add_number
>> 2) & 0xffff;
1546 r
= BFD_RELOC_16_PCREL_S2
;
1550 assert (ep
!= NULL
);
1551 r
= BFD_RELOC_MIPS_JMP
;
1560 assert (r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
1562 append_insn (place
, &insn
, ep
, r
);
1566 * Generate a "lui" instruction.
1569 macro_build_lui (place
, counter
, ep
, regnum
)
1575 expressionS high_expr
;
1576 struct mips_cl_insn insn
;
1577 bfd_reloc_code_real_type r
;
1578 CONST
char *name
= "lui";
1579 CONST
char *fmt
= "t,u";
1585 high_expr
.X_op
= O_constant
;
1586 high_expr
.X_add_number
= 0;
1589 if (high_expr
.X_op
== O_constant
)
1591 /* we can compute the instruction now without a relocation entry */
1592 if (high_expr
.X_add_number
& 0x8000)
1593 high_expr
.X_add_number
+= 0x10000;
1594 high_expr
.X_add_number
=
1595 ((unsigned long) high_expr
.X_add_number
>> 16) & 0xffff;
1596 r
= BFD_RELOC_UNUSED
;
1600 assert (ep
->X_op
== O_symbol
);
1601 /* _gp_disp is a special case, used from s_cpload. */
1602 assert (mips_pic
== NO_PIC
1603 || strcmp (S_GET_NAME (ep
->X_add_symbol
), "_gp_disp") == 0);
1604 r
= BFD_RELOC_HI16_S
;
1608 * If the macro is about to expand into a second instruction,
1609 * print a warning if needed. We need to pass ip as a parameter
1610 * to generate a better warning message here...
1612 if (mips_warn_about_macros
&& place
== NULL
&& *counter
== 1)
1613 as_warn ("Macro instruction expanded into multiple instructions");
1616 *counter
+= 1; /* bump instruction counter */
1618 insn
.insn_mo
= (struct mips_opcode
*) hash_find (op_hash
, name
);
1619 assert (insn
.insn_mo
);
1620 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
1621 assert (strcmp (fmt
, insn
.insn_mo
->args
) == 0);
1623 insn
.insn_opcode
= insn
.insn_mo
->match
| (regnum
<< OP_SH_RT
);
1624 if (r
== BFD_RELOC_UNUSED
)
1626 insn
.insn_opcode
|= high_expr
.X_add_number
;
1627 append_insn (place
, &insn
, NULL
, r
);
1630 append_insn (place
, &insn
, &high_expr
, r
);
1634 * Generates code to set the $at register to true (one)
1635 * if reg is less than the immediate expression.
1638 set_at (counter
, reg
, unsignedp
)
1643 if (imm_expr
.X_add_number
>= -0x8000 && imm_expr
.X_add_number
< 0x8000)
1644 macro_build ((char *) NULL
, counter
, &imm_expr
,
1645 unsignedp
? "sltiu" : "slti",
1646 "t,r,j", AT
, reg
, (int) BFD_RELOC_LO16
);
1649 load_register (counter
, AT
, &imm_expr
, 0);
1650 macro_build ((char *) NULL
, counter
, NULL
,
1651 unsignedp
? "sltu" : "slt",
1652 "d,v,t", AT
, reg
, AT
);
1656 /* Warn if an expression is not a constant. */
1659 check_absolute_expr (ip
, ex
)
1660 struct mips_cl_insn
*ip
;
1663 if (ex
->X_op
!= O_constant
)
1664 as_warn ("Instruction %s requires absolute expression", ip
->insn_mo
->name
);
1668 * This routine generates the least number of instructions neccessary to load
1669 * an absolute expression value into a register.
1672 load_register (counter
, reg
, ep
, dbl
)
1679 expressionS hi32
, lo32
, tmp
;
1681 if (ep
->X_op
!= O_big
)
1683 assert (ep
->X_op
== O_constant
);
1684 if (ep
->X_add_number
< 0x8000
1685 && (ep
->X_add_number
>= 0
1686 || (ep
->X_add_number
>= -0x8000
1689 || sizeof (ep
->X_add_number
) > 4))))
1691 /* We can handle 16 bit signed values with an addiu to
1692 $zero. No need to ever use daddiu here, since $zero and
1693 the result are always correct in 32 bit mode. */
1694 macro_build ((char *) NULL
, counter
, ep
, "addiu", "t,r,j", reg
, 0,
1695 (int) BFD_RELOC_LO16
);
1698 else if (ep
->X_add_number
>= 0 && ep
->X_add_number
< 0x10000)
1700 /* We can handle 16 bit unsigned values with an ori to
1702 macro_build ((char *) NULL
, counter
, ep
, "ori", "t,r,i", reg
, 0,
1703 (int) BFD_RELOC_LO16
);
1706 else if (((ep
->X_add_number
&~ (offsetT
) 0x7fffffff) == 0
1707 || ((ep
->X_add_number
&~ (offsetT
) 0x7fffffff)
1708 == ~ (offsetT
) 0x7fffffff))
1711 || sizeof (ep
->X_add_number
) > 4
1712 || (ep
->X_add_number
& 0x80000000) == 0))
1714 /* 32 bit values require an lui. */
1715 macro_build ((char *) NULL
, counter
, ep
, "lui", "t,u", reg
,
1716 (int) BFD_RELOC_HI16
);
1717 if ((ep
->X_add_number
& 0xffff) != 0)
1718 macro_build ((char *) NULL
, counter
, ep
, "ori", "t,r,i", reg
, reg
,
1719 (int) BFD_RELOC_LO16
);
1724 /* 32 bit value with high bit set being loaded into a 64 bit
1725 register. We can't use lui, because that would
1726 incorrectly set the 32 high bits. */
1727 generic_bignum
[3] = 0;
1728 generic_bignum
[2] = 0;
1729 generic_bignum
[1] = (ep
->X_add_number
>> 16) & 0xffff;
1730 generic_bignum
[0] = ep
->X_add_number
& 0xffff;
1732 tmp
.X_add_number
= 4;
1737 /* The value is larger than 32 bits. */
1741 as_bad ("Number larger than 32 bits");
1742 macro_build ((char *) NULL
, counter
, ep
, "addiu", "t,r,j", reg
, 0,
1743 (int) BFD_RELOC_LO16
);
1747 if (ep
->X_op
!= O_big
)
1751 hi32
.X_add_number
>>= shift
;
1752 hi32
.X_add_number
&= 0xffffffff;
1753 if ((hi32
.X_add_number
& 0x80000000) != 0)
1754 hi32
.X_add_number
|= ~ (offsetT
) 0xffffffff;
1756 lo32
.X_add_number
&= 0xffffffff;
1760 assert (ep
->X_add_number
> 2);
1761 if (ep
->X_add_number
== 3)
1762 generic_bignum
[3] = 0;
1763 else if (ep
->X_add_number
> 4)
1764 as_bad ("Number larger than 64 bits");
1765 lo32
.X_op
= O_constant
;
1766 lo32
.X_add_number
= generic_bignum
[0] + (generic_bignum
[1] << 16);
1767 hi32
.X_op
= O_constant
;
1768 hi32
.X_add_number
= generic_bignum
[2] + (generic_bignum
[3] << 16);
1771 if (hi32
.X_add_number
== 0)
1775 load_register (counter
, reg
, &hi32
, 0);
1778 if ((lo32
.X_add_number
& 0xffff0000) == 0)
1782 macro_build ((char *) NULL
, counter
, NULL
, "dsll32", "d,w,<", reg
,
1793 macro_build ((char *) NULL
, counter
, NULL
, "dsll", "d,w,<", reg
,
1798 mid16
.X_add_number
>>= 16;
1799 macro_build ((char *) NULL
, counter
, &mid16
, "ori", "t,r,i", reg
,
1800 freg
, (int) BFD_RELOC_LO16
);
1801 macro_build ((char *) NULL
, counter
, NULL
, "dsll", "d,w,<", reg
,
1805 if ((lo32
.X_add_number
& 0xffff) != 0)
1806 macro_build ((char *) NULL
, counter
, &lo32
, "ori", "t,r,i", reg
, freg
,
1807 (int) BFD_RELOC_LO16
);
1810 /* Load an address into a register. */
1813 load_address (counter
, reg
, ep
)
1820 if (ep
->X_op
!= O_constant
1821 && ep
->X_op
!= O_symbol
)
1823 as_bad ("expression too complex");
1824 ep
->X_op
= O_constant
;
1827 if (ep
->X_op
== O_constant
)
1829 load_register (counter
, reg
, ep
, 0);
1833 if (mips_pic
== NO_PIC
)
1835 /* If this is a reference to a GP relative symbol, we want
1836 addiu $reg,$gp,<sym> (BFD_RELOC_MIPS_GPREL)
1838 lui $reg,<sym> (BFD_RELOC_HI16_S)
1839 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
1840 If we have an addend, we always use the latter form. */
1841 if (ep
->X_add_number
!= 0 || nopic_need_relax (ep
->X_add_symbol
))
1846 macro_build ((char *) NULL
, counter
, ep
,
1847 mips_isa
< 3 ? "addiu" : "daddiu",
1848 "t,r,j", reg
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
1849 p
= frag_var (rs_machine_dependent
, 8, 0,
1850 RELAX_ENCODE (4, 8, 0, 4, 0, mips_warn_about_macros
),
1851 ep
->X_add_symbol
, (long) 0, (char *) NULL
);
1853 macro_build_lui (p
, counter
, ep
, reg
);
1856 macro_build (p
, counter
, ep
,
1857 mips_isa
< 3 ? "addiu" : "daddiu",
1858 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
1860 else if (mips_pic
== SVR4_PIC
)
1864 /* If this is a reference to an external symbol, we want
1865 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
1867 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
1869 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
1870 If there is a constant, it must be added in after. */
1871 ex
.X_add_number
= ep
->X_add_number
;
1872 ep
->X_add_number
= 0;
1874 macro_build ((char *) NULL
, counter
, ep
,
1875 mips_isa
< 3 ? "lw" : "ld",
1876 "t,o(b)", reg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
1877 macro_build ((char *) NULL
, counter
, (expressionS
*) NULL
, "nop", "");
1878 p
= frag_var (rs_machine_dependent
, 4, 0,
1879 RELAX_ENCODE (0, 4, -8, 0, 0, mips_warn_about_macros
),
1880 ep
->X_add_symbol
, (long) 0, (char *) NULL
);
1881 macro_build (p
, counter
, ep
,
1882 mips_isa
< 3 ? "addiu" : "daddiu",
1883 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
1884 if (ex
.X_add_number
!= 0)
1886 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
1887 as_bad ("PIC code offset overflow (max 16 signed bits)");
1888 ex
.X_op
= O_constant
;
1889 macro_build (p
, counter
, &ex
,
1890 mips_isa
< 3 ? "addiu" : "daddiu",
1891 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
1894 else if (mips_pic
== EMBEDDED_PIC
)
1897 addiu $reg,$gp,<sym> (BFD_RELOC_MIPS_GPREL)
1899 macro_build ((char *) NULL
, counter
, ep
,
1900 mips_isa
< 3 ? "addiu" : "daddiu",
1901 "t,r,j", reg
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
1909 * This routine implements the seemingly endless macro or synthesized
1910 * instructions and addressing modes in the mips assembly language. Many
1911 * of these macros are simple and are similar to each other. These could
1912 * probably be handled by some kind of table or grammer aproach instead of
1913 * this verbose method. Others are not simple macros but are more like
1914 * optimizing code generation.
1915 * One interesting optimization is when several store macros appear
1916 * consecutivly that would load AT with the upper half of the same address.
1917 * The ensuing load upper instructions are ommited. This implies some kind
1918 * of global optimization. We currently only optimize within a single macro.
1919 * For many of the load and store macros if the address is specified as a
1920 * constant expression in the first 64k of memory (ie ld $2,0x4000c) we
1921 * first load register 'at' with zero and use it as the base register. The
1922 * mips assembler simply uses register $zero. Just one tiny optimization
1927 struct mips_cl_insn
*ip
;
1929 register int treg
, sreg
, dreg
, breg
;
1944 bfd_reloc_code_real_type r
;
1946 int hold_mips_optimize
;
1948 treg
= (ip
->insn_opcode
>> 16) & 0x1f;
1949 dreg
= (ip
->insn_opcode
>> 11) & 0x1f;
1950 sreg
= breg
= (ip
->insn_opcode
>> 21) & 0x1f;
1951 mask
= ip
->insn_mo
->mask
;
1953 expr1
.X_op
= O_constant
;
1954 expr1
.X_op_symbol
= NULL
;
1955 expr1
.X_add_symbol
= NULL
;
1956 expr1
.X_add_number
= 1;
1968 mips_emit_delays ();
1970 mips_any_noreorder
= 1;
1972 expr1
.X_add_number
= 8;
1973 macro_build ((char *) NULL
, &icnt
, &expr1
, "bgez", "s,p", sreg
);
1975 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
1977 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
, sreg
, 0);
1978 macro_build ((char *) NULL
, &icnt
, NULL
,
1979 dbl
? "dsub" : "sub",
1980 "d,v,t", dreg
, 0, sreg
);
2003 if (imm_expr
.X_add_number
>= -0x8000 && imm_expr
.X_add_number
< 0x8000)
2005 macro_build ((char *) NULL
, &icnt
, &imm_expr
, s
, "t,r,j", treg
, sreg
,
2006 (int) BFD_RELOC_LO16
);
2009 load_register (&icnt
, AT
, &imm_expr
, dbl
);
2010 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "d,v,t", treg
, sreg
, AT
);
2029 if (imm_expr
.X_add_number
>= 0 && imm_expr
.X_add_number
< 0x10000)
2031 if (mask
!= M_NOR_I
)
2032 macro_build ((char *) NULL
, &icnt
, &imm_expr
, s
, "t,r,i", treg
,
2033 sreg
, (int) BFD_RELOC_LO16
);
2036 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "ori", "t,r,i",
2037 treg
, sreg
, (int) BFD_RELOC_LO16
);
2038 macro_build ((char *) NULL
, &icnt
, NULL
, "nor", "d,v,t",
2044 load_register (&icnt
, AT
, &imm_expr
, 0);
2045 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "d,v,t", treg
, sreg
, AT
);
2062 if (imm_expr
.X_add_number
== 0)
2064 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "s,t,p", sreg
,
2068 load_register (&icnt
, AT
, &imm_expr
, 0);
2069 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "s,t,p", sreg
, AT
);
2077 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2078 likely
? "bgezl" : "bgez",
2084 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2085 likely
? "blezl" : "blez",
2089 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", AT
, sreg
, treg
);
2090 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2091 likely
? "beql" : "beq",
2098 /* check for > max integer */
2099 maxnum
= 0x7fffffff;
2107 if (imm_expr
.X_add_number
>= maxnum
2108 && (mips_isa
< 3 || sizeof (maxnum
) > 4))
2111 /* result is always false */
2114 as_warn ("Branch %s is always false (nop)", ip
->insn_mo
->name
);
2115 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
2119 as_warn ("Branch likely %s is always false", ip
->insn_mo
->name
);
2120 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "bnel",
2125 imm_expr
.X_add_number
++;
2129 if (mask
== M_BGEL_I
)
2131 if (imm_expr
.X_add_number
== 0)
2133 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2134 likely
? "bgezl" : "bgez",
2138 if (imm_expr
.X_add_number
== 1)
2140 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2141 likely
? "bgtzl" : "bgtz",
2145 maxnum
= 0x7fffffff;
2153 maxnum
= - maxnum
- 1;
2154 if (imm_expr
.X_add_number
<= maxnum
2155 && (mips_isa
< 3 || sizeof (maxnum
) > 4))
2158 /* result is always true */
2159 as_warn ("Branch %s is always true", ip
->insn_mo
->name
);
2160 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "b", "p");
2163 set_at (&icnt
, sreg
, 0);
2164 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2165 likely
? "beql" : "beq",
2176 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2177 likely
? "beql" : "beq",
2181 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", AT
, sreg
,
2183 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2184 likely
? "beql" : "beq",
2191 if (sreg
== 0 || imm_expr
.X_add_number
== -1)
2193 imm_expr
.X_add_number
++;
2197 if (mask
== M_BGEUL_I
)
2199 if (imm_expr
.X_add_number
== 0)
2201 if (imm_expr
.X_add_number
== 1)
2203 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2204 likely
? "bnel" : "bne",
2208 set_at (&icnt
, sreg
, 1);
2209 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2210 likely
? "beql" : "beq",
2219 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2220 likely
? "bgtzl" : "bgtz",
2226 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2227 likely
? "bltzl" : "bltz",
2231 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", AT
, treg
, sreg
);
2232 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2233 likely
? "bnel" : "bne",
2242 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2243 likely
? "bnel" : "bne",
2249 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", AT
, treg
,
2251 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2252 likely
? "bnel" : "bne",
2261 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2262 likely
? "blezl" : "blez",
2268 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2269 likely
? "bgezl" : "bgez",
2273 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", AT
, treg
, sreg
);
2274 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2275 likely
? "beql" : "beq",
2282 maxnum
= 0x7fffffff;
2290 if (imm_expr
.X_add_number
>= maxnum
2291 && (mips_isa
< 3 || sizeof (maxnum
) > 4))
2293 imm_expr
.X_add_number
++;
2297 if (mask
== M_BLTL_I
)
2299 if (imm_expr
.X_add_number
== 0)
2301 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2302 likely
? "bltzl" : "bltz",
2306 if (imm_expr
.X_add_number
== 1)
2308 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2309 likely
? "blezl" : "blez",
2313 set_at (&icnt
, sreg
, 0);
2314 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2315 likely
? "bnel" : "bne",
2324 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2325 likely
? "beql" : "beq",
2331 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", AT
, treg
,
2333 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2334 likely
? "beql" : "beq",
2341 if (sreg
== 0 || imm_expr
.X_add_number
== -1)
2343 imm_expr
.X_add_number
++;
2347 if (mask
== M_BLTUL_I
)
2349 if (imm_expr
.X_add_number
== 0)
2351 if (imm_expr
.X_add_number
== 1)
2353 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2354 likely
? "beql" : "beq",
2358 set_at (&icnt
, sreg
, 1);
2359 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2360 likely
? "bnel" : "bne",
2369 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2370 likely
? "bltzl" : "bltz",
2376 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2377 likely
? "bgtzl" : "bgtz",
2381 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", AT
, sreg
, treg
);
2382 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2383 likely
? "bnel" : "bne",
2394 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2395 likely
? "bnel" : "bne",
2399 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", AT
, sreg
,
2401 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2402 likely
? "bnel" : "bne",
2418 as_warn ("Divide by zero.");
2420 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", 0, 0);
2422 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 7);
2426 mips_emit_delays ();
2428 mips_any_noreorder
= 1;
2429 macro_build ((char *) NULL
, &icnt
, NULL
,
2430 dbl
? "ddiv" : "div",
2431 "z,s,t", sreg
, treg
);
2433 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", treg
, 0);
2436 expr1
.X_add_number
= 8;
2437 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", treg
, 0);
2438 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
2439 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 7);
2441 expr1
.X_add_number
= -1;
2442 macro_build ((char *) NULL
, &icnt
, &expr1
,
2443 dbl
? "daddiu" : "addiu",
2444 "t,r,j", AT
, 0, (int) BFD_RELOC_LO16
);
2445 expr1
.X_add_number
= mips_trap
? (dbl
? 12 : 8) : (dbl
? 20 : 16);
2446 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", treg
, AT
);
2449 expr1
.X_add_number
= 1;
2450 macro_build ((char *) NULL
, &icnt
, &expr1
, "daddiu", "t,r,j", AT
, 0,
2451 (int) BFD_RELOC_LO16
);
2452 macro_build ((char *) NULL
, &icnt
, NULL
, "dsll32", "d,w,<", AT
, AT
,
2457 expr1
.X_add_number
= 0x80000000;
2458 macro_build ((char *) NULL
, &icnt
, &expr1
, "lui", "t,u", AT
,
2459 (int) BFD_RELOC_HI16
);
2462 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", sreg
, AT
);
2465 expr1
.X_add_number
= 8;
2466 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", sreg
, AT
);
2467 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
2468 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 6);
2471 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d", dreg
);
2510 if (imm_expr
.X_add_number
== 0)
2512 as_warn ("Divide by zero.");
2514 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", 0, 0);
2516 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 7);
2519 if (imm_expr
.X_add_number
== 1)
2521 if (strcmp (s2
, "mflo") == 0)
2522 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
,
2525 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
, 0);
2528 if (imm_expr
.X_add_number
== -1
2529 && s
[strlen (s
) - 1] != 'u')
2531 if (strcmp (s2
, "mflo") == 0)
2534 macro_build ((char *) NULL
, &icnt
, NULL
, "dneg", "d,w", dreg
,
2537 macro_build ((char *) NULL
, &icnt
, NULL
, "neg", "d,w", dreg
,
2541 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
, 0);
2545 load_register (&icnt
, AT
, &imm_expr
, dbl
);
2546 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "z,s,t", sreg
, AT
);
2547 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "d", dreg
);
2566 mips_emit_delays ();
2568 mips_any_noreorder
= 1;
2569 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "z,s,t", sreg
, treg
);
2571 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", treg
, 0);
2574 expr1
.X_add_number
= 8;
2575 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", treg
, 0);
2576 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
2577 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 7);
2580 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "d", dreg
);
2586 /* Load the address of a symbol into a register. If breg is not
2587 zero, we then add a base register to it. */
2589 /* When generating embedded PIC code, we permit expressions of
2592 where bar is an address in the .text section. These are used
2593 when getting the addresses of functions. We don't permit
2594 X_add_number to be non-zero, because if the symbol is
2595 external the relaxing code needs to know that any addend is
2596 purely the offset to X_op_symbol. */
2597 if (mips_pic
== EMBEDDED_PIC
2598 && offset_expr
.X_op
== O_subtract
2599 && now_seg
== text_section
2600 && (offset_expr
.X_op_symbol
->sy_value
.X_op
== O_constant
2601 ? S_GET_SEGMENT (offset_expr
.X_op_symbol
) == text_section
2602 : (offset_expr
.X_op_symbol
->sy_value
.X_op
== O_symbol
2603 && (S_GET_SEGMENT (offset_expr
.X_op_symbol
2604 ->sy_value
.X_add_symbol
)
2607 && offset_expr
.X_add_number
== 0)
2609 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
2610 treg
, (int) BFD_RELOC_PCREL_HI16_S
);
2611 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2612 mips_isa
< 3 ? "addiu" : "daddiu",
2613 "t,r,j", treg
, treg
, (int) BFD_RELOC_PCREL_LO16
);
2617 if (offset_expr
.X_op
!= O_symbol
2618 && offset_expr
.X_op
!= O_constant
)
2620 as_bad ("expression too complex");
2621 offset_expr
.X_op
= O_constant
;
2635 if (offset_expr
.X_op
== O_constant
)
2636 load_register (&icnt
, tempreg
, &offset_expr
, dbl
);
2637 else if (mips_pic
== NO_PIC
)
2639 /* If this is a reference to an GP relative symbol, we want
2640 addiu $tempreg,$gp,<sym> (BFD_RELOC_MIPS_GPREL)
2642 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
2643 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
2644 If we have a constant, we need two instructions anyhow,
2645 so we may as well always use the latter form. */
2646 if (offset_expr
.X_add_number
!= 0
2647 || nopic_need_relax (offset_expr
.X_add_symbol
))
2652 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2653 mips_isa
< 3 ? "addiu" : "daddiu",
2654 "t,r,j", tempreg
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
2655 p
= frag_var (rs_machine_dependent
, 8, 0,
2656 RELAX_ENCODE (4, 8, 0, 4, 0,
2657 mips_warn_about_macros
),
2658 offset_expr
.X_add_symbol
, (long) 0,
2661 macro_build_lui (p
, &icnt
, &offset_expr
, tempreg
);
2664 macro_build (p
, &icnt
, &offset_expr
,
2665 mips_isa
< 3 ? "addiu" : "daddiu",
2666 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
2668 else if (mips_pic
== SVR4_PIC
)
2670 /* If this is a reference to an external symbol, and there
2671 is no constant, we want
2672 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
2673 For a local symbol, we want
2674 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
2676 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
2678 If we have a small constant, and this is a reference to
2679 an external symbol, we want
2680 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
2682 addiu $tempreg,$tempreg,<constant>
2683 For a local symbol, we want the same instruction
2684 sequence, but we output a BFD_RELOC_LO16 reloc on the
2687 If we have a large constant, and this is a reference to
2688 an external symbol, we want
2689 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
2690 lui $at,<hiconstant>
2691 addiu $at,$at,<loconstant>
2692 addu $tempreg,$tempreg,$at
2693 For a local symbol, we want the same instruction
2694 sequence, but we output a BFD_RELOC_LO16 reloc on the
2695 addiu instruction. */
2696 expr1
.X_add_number
= offset_expr
.X_add_number
;
2697 offset_expr
.X_add_number
= 0;
2699 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2701 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
2702 if (expr1
.X_add_number
== 0)
2710 /* We're going to put in an addu instruction using
2711 tempreg, so we may as well insert the nop right
2713 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
2717 p
= frag_var (rs_machine_dependent
, 8 - off
, 0,
2718 RELAX_ENCODE (0, 8 - off
, -4 - off
, 4 - off
, 0,
2720 ? mips_warn_about_macros
2722 offset_expr
.X_add_symbol
, (long) 0,
2726 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
2729 macro_build (p
, &icnt
, &expr1
,
2730 mips_isa
< 3 ? "addiu" : "daddiu",
2731 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
2732 /* FIXME: If breg == 0, and the next instruction uses
2733 $tempreg, then if this variant case is used an extra
2734 nop will be generated. */
2736 else if (expr1
.X_add_number
>= -0x8000
2737 && expr1
.X_add_number
< 0x8000)
2739 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
2741 macro_build ((char *) NULL
, &icnt
, &expr1
,
2742 mips_isa
< 3 ? "addiu" : "daddiu",
2743 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
2744 (void) frag_var (rs_machine_dependent
, 0, 0,
2745 RELAX_ENCODE (0, 0, -12, -4, 0, 0),
2746 offset_expr
.X_add_symbol
, (long) 0,
2753 /* If we are going to add in a base register, and the
2754 target register and the base register are the same,
2755 then we are using AT as a temporary register. Since
2756 we want to load the constant into AT, we add our
2757 current AT (from the global offset table) and the
2758 register into the register now, and pretend we were
2759 not using a base register. */
2764 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
2766 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
2767 mips_isa
< 3 ? "addu" : "daddu",
2768 "d,v,t", treg
, AT
, breg
);
2774 /* Set mips_optimize around the lui instruction to avoid
2775 inserting an unnecessary nop after the lw. */
2776 hold_mips_optimize
= mips_optimize
;
2778 macro_build_lui ((char *) NULL
, &icnt
, &expr1
, AT
);
2779 mips_optimize
= hold_mips_optimize
;
2781 macro_build ((char *) NULL
, &icnt
, &expr1
,
2782 mips_isa
< 3 ? "addiu" : "daddiu",
2783 "t,r,j", AT
, AT
, (int) BFD_RELOC_LO16
);
2784 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
2785 mips_isa
< 3 ? "addu" : "daddu",
2786 "d,v,t", tempreg
, tempreg
, AT
);
2787 (void) frag_var (rs_machine_dependent
, 0, 0,
2788 RELAX_ENCODE (0, 0, -16 + off1
, -8, 0, 0),
2789 offset_expr
.X_add_symbol
, (long) 0,
2794 else if (mips_pic
== EMBEDDED_PIC
)
2797 addiu $tempreg,$gp,<sym> (BFD_RELOC_MIPS_GPREL)
2799 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2800 mips_isa
< 3 ? "addiu" : "daddiu",
2801 "t,r,j", tempreg
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
2807 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
2808 mips_isa
< 3 ? "addu" : "daddu",
2809 "d,v,t", treg
, tempreg
, breg
);
2817 /* The j instruction may not be used in PIC code, since it
2818 requires an absolute address. We convert it to a b
2820 if (mips_pic
== NO_PIC
)
2821 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "j", "a");
2823 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "b", "p");
2826 /* The jal instructions must be handled as macros because when
2827 generating PIC code they expand to multi-instruction
2828 sequences. Normally they are simple instructions. */
2833 if (mips_pic
== NO_PIC
2834 || mips_pic
== EMBEDDED_PIC
)
2835 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "jalr",
2837 else if (mips_pic
== SVR4_PIC
)
2839 if (sreg
!= PIC_CALL_REG
)
2840 as_warn ("MIPS PIC call to register other than $25");
2842 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "jalr",
2844 if (mips_cprestore_offset
< 0)
2845 as_warn ("No .cprestore pseudo-op used in PIC code");
2848 expr1
.X_add_number
= mips_cprestore_offset
;
2849 macro_build ((char *) NULL
, &icnt
, &expr1
,
2850 mips_isa
< 3 ? "lw" : "ld",
2851 "t,o(b)", GP
, (int) BFD_RELOC_LO16
, mips_frame_reg
);
2860 if (mips_pic
== NO_PIC
)
2861 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "jal", "a");
2862 else if (mips_pic
== SVR4_PIC
)
2864 /* If this is a reference to an external symbol, we want
2865 lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
2869 lw $gp,cprestore($sp)
2870 The cprestore value is set using the .cprestore
2871 pseudo-op. If the symbol is not external, we want
2872 lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
2874 addiu $25,$25,<sym> (BFD_RELOC_LO16)
2877 lw $gp,cprestore($sp)
2880 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2881 mips_isa
< 3 ? "lw" : "ld",
2882 "t,o(b)", PIC_CALL_REG
,
2883 (int) BFD_RELOC_MIPS_CALL16
, GP
);
2884 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
2885 p
= frag_var (rs_machine_dependent
, 4, 0,
2886 RELAX_ENCODE (0, 4, -8, 0, 0, 0),
2887 offset_expr
.X_add_symbol
, (long) 0, (char *) NULL
);
2888 macro_build (p
, &icnt
, &offset_expr
,
2889 mips_isa
< 3 ? "addiu" : "daddiu",
2890 "t,r,j", PIC_CALL_REG
, PIC_CALL_REG
,
2891 (int) BFD_RELOC_LO16
);
2892 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
2893 "jalr", "s", PIC_CALL_REG
);
2894 if (mips_cprestore_offset
< 0)
2895 as_warn ("No .cprestore pseudo-op used in PIC code");
2899 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
2901 expr1
.X_add_number
= mips_cprestore_offset
;
2902 macro_build ((char *) NULL
, &icnt
, &expr1
,
2903 mips_isa
< 3 ? "lw" : "ld",
2904 "t,o(b)", GP
, (int) BFD_RELOC_LO16
,
2908 else if (mips_pic
== EMBEDDED_PIC
)
2910 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "bal", "p");
2911 /* The linker may expand the call to a longer sequence which
2912 uses $at, so we must break rather than return. */
2988 if (breg
== treg
|| coproc
|| lr
)
3057 if (mask
== M_LWC1_AB
3058 || mask
== M_SWC1_AB
3059 || mask
== M_LDC1_AB
3060 || mask
== M_SDC1_AB
3069 if (offset_expr
.X_op
!= O_constant
3070 && offset_expr
.X_op
!= O_symbol
)
3072 as_bad ("expression too complex");
3073 offset_expr
.X_op
= O_constant
;
3076 /* A constant expression in PIC code can be handled just as it
3077 is in non PIC code. */
3078 if (mips_pic
== NO_PIC
3079 || offset_expr
.X_op
== O_constant
)
3081 /* If this is a reference to a GP relative symbol, and there
3082 is no base register, we want
3083 <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL)
3084 Otherwise, if there is no base register, we want
3085 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
3086 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
3087 If we have a constant, we need two instructions anyhow,
3088 so we always use the latter form.
3090 If we have a base register, and this is a reference to a
3091 GP relative symbol, we want
3092 addu $tempreg,$breg,$gp
3093 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GPREL)
3095 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
3096 addu $tempreg,$tempreg,$breg
3097 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
3098 With a constant we always use the latter case. */
3101 if (offset_expr
.X_add_number
!= 0
3102 || nopic_need_relax (offset_expr
.X_add_symbol
))
3107 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
3108 treg
, (int) BFD_RELOC_MIPS_GPREL
, GP
);
3109 p
= frag_var (rs_machine_dependent
, 8, 0,
3110 RELAX_ENCODE (4, 8, 0, 4, 0,
3111 (mips_warn_about_macros
3112 || (used_at
&& mips_noat
))),
3113 offset_expr
.X_add_symbol
, (long) 0,
3117 macro_build_lui (p
, &icnt
, &offset_expr
, tempreg
);
3120 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
, treg
,
3121 (int) BFD_RELOC_LO16
, tempreg
);
3125 if (offset_expr
.X_add_number
!= 0
3126 || nopic_need_relax (offset_expr
.X_add_symbol
))
3131 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3132 mips_isa
< 3 ? "addu" : "daddu",
3133 "d,v,t", tempreg
, breg
, GP
);
3134 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
3135 treg
, (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
3136 p
= frag_var (rs_machine_dependent
, 12, 0,
3137 RELAX_ENCODE (8, 12, 0, 8, 0, 0),
3138 offset_expr
.X_add_symbol
, (long) 0,
3141 macro_build_lui (p
, &icnt
, &offset_expr
, tempreg
);
3144 macro_build (p
, &icnt
, (expressionS
*) NULL
,
3145 mips_isa
< 3 ? "addu" : "daddu",
3146 "d,v,t", tempreg
, tempreg
, breg
);
3149 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
, treg
,
3150 (int) BFD_RELOC_LO16
, tempreg
);
3153 else if (mips_pic
== SVR4_PIC
)
3155 /* If this is a reference to an external symbol, we want
3156 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3158 <op> $treg,0($tempreg)
3160 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3162 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
3163 <op> $treg,0($tempreg)
3164 If there is a base register, we add it to $tempreg before
3165 the <op>. If there is a constant, we stick it in the
3166 <op> instruction. We don't handle constants larger than
3167 16 bits, because we have no way to load the upper 16 bits
3168 (actually, we could handle them for the subset of cases
3169 in which we are not using $at). */
3170 assert (offset_expr
.X_op
== O_symbol
);
3171 expr1
.X_add_number
= offset_expr
.X_add_number
;
3172 offset_expr
.X_add_number
= 0;
3173 if (expr1
.X_add_number
< -0x8000
3174 || expr1
.X_add_number
>= 0x8000)
3175 as_bad ("PIC code offset overflow (max 16 signed bits)");
3177 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3178 mips_isa
< 3 ? "lw" : "ld",
3179 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
3180 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
3181 p
= frag_var (rs_machine_dependent
, 4, 0,
3182 RELAX_ENCODE (0, 4, -8, 0, 0, 0),
3183 offset_expr
.X_add_symbol
, (long) 0,
3185 macro_build (p
, &icnt
, &offset_expr
,
3186 mips_isa
< 3 ? "addiu" : "daddiu",
3187 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
3189 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3190 mips_isa
< 3 ? "addu" : "daddu",
3191 "d,v,t", tempreg
, tempreg
, breg
);
3192 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
, treg
,
3193 (int) BFD_RELOC_LO16
, tempreg
);
3195 else if (mips_pic
== EMBEDDED_PIC
)
3197 /* If there is no base register, we want
3198 <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL)
3199 If there is a base register, we want
3200 addu $tempreg,$breg,$gp
3201 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GPREL)
3203 assert (offset_expr
.X_op
== O_symbol
);
3206 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
3207 treg
, (int) BFD_RELOC_MIPS_GPREL
, GP
);
3212 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3213 mips_isa
< 3 ? "addu" : "daddu",
3214 "d,v,t", tempreg
, breg
, GP
);
3215 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
3216 treg
, (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
3229 load_register (&icnt
, treg
, &imm_expr
, 0);
3233 load_register (&icnt
, treg
, &imm_expr
, 1);
3237 if (imm_expr
.X_op
== O_constant
)
3239 load_register (&icnt
, AT
, &imm_expr
, 0);
3240 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3241 "mtc1", "t,G", AT
, treg
);
3246 assert (offset_expr
.X_op
== O_symbol
3247 && strcmp (segment_name (S_GET_SEGMENT
3248 (offset_expr
.X_add_symbol
)),
3250 && offset_expr
.X_add_number
== 0);
3251 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lwc1", "T,o(b)",
3252 treg
, (int) BFD_RELOC_MIPS_LITERAL
, GP
);
3257 /* We know that sym is in the .rdata section. First we get the
3258 upper 16 bits of the address. */
3259 if (mips_pic
== NO_PIC
)
3261 /* FIXME: This won't work for a 64 bit address. */
3262 macro_build_lui ((char *) NULL
, &icnt
, &offset_expr
, AT
);
3264 else if (mips_pic
== SVR4_PIC
)
3266 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3267 mips_isa
< 3 ? "lw" : "ld",
3268 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
3270 else if (mips_pic
== EMBEDDED_PIC
)
3272 /* For embedded PIC we pick up the entire address off $gp in
3273 a single instruction. */
3274 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3275 mips_isa
< 3 ? "addiu" : "daddiu",
3276 "t,r,j", AT
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
3277 offset_expr
.X_op
= O_constant
;
3278 offset_expr
.X_add_number
= 0;
3283 /* Now we load the register(s). */
3285 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "ld", "t,o(b)",
3286 treg
, (int) BFD_RELOC_LO16
, AT
);
3289 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lw", "t,o(b)",
3290 treg
, (int) BFD_RELOC_LO16
, AT
);
3293 /* FIXME: How in the world do we deal with the possible
3295 offset_expr
.X_add_number
+= 4;
3296 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lw", "t,o(b)",
3297 treg
+ 1, (int) BFD_RELOC_LO16
, AT
);
3301 /* To avoid confusion in tc_gen_reloc, we must ensure that this
3302 does not become a variant frag. */
3303 frag_wane (frag_now
);
3309 assert (offset_expr
.X_op
== O_symbol
3310 && offset_expr
.X_add_number
== 0);
3311 s
= segment_name (S_GET_SEGMENT (offset_expr
.X_add_symbol
));
3312 if (strcmp (s
, ".lit8") == 0)
3316 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "ldc1",
3317 "T,o(b)", treg
, (int) BFD_RELOC_MIPS_LITERAL
, GP
);
3321 r
= BFD_RELOC_MIPS_LITERAL
;
3326 assert (strcmp (s
, RDATA_SECTION_NAME
) == 0);
3327 if (mips_pic
== SVR4_PIC
)
3328 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3329 mips_isa
< 3 ? "lw" : "ld",
3330 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
3333 /* FIXME: This won't work for a 64 bit address. */
3334 macro_build_lui ((char *) NULL
, &icnt
, &offset_expr
, AT
);
3339 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "ldc1",
3340 "T,o(b)", treg
, (int) BFD_RELOC_LO16
, AT
);
3342 /* To avoid confusion in tc_gen_reloc, we must ensure
3343 that this does not become a variant frag. */
3344 frag_wane (frag_now
);
3355 /* Even on a big endian machine $fn comes before $fn+1. We have
3356 to adjust when loading from memory. */
3359 assert (mips_isa
< 2);
3360 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lwc1", "T,o(b)",
3361 byte_order
== LITTLE_ENDIAN
? treg
: treg
+ 1,
3363 /* FIXME: A possible overflow which I don't know how to deal
3365 offset_expr
.X_add_number
+= 4;
3366 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lwc1", "T,o(b)",
3367 byte_order
== LITTLE_ENDIAN
? treg
+ 1 : treg
,
3370 /* To avoid confusion in tc_gen_reloc, we must ensure that this
3371 does not become a variant frag. */
3372 frag_wane (frag_now
);
3381 * The MIPS assembler seems to check for X_add_number not
3382 * being double aligned and generating:
3385 * addiu at,at,%lo(foo+1)
3388 * But, the resulting address is the same after relocation so why
3389 * generate the extra instruction?
3436 if (offset_expr
.X_op
!= O_symbol
3437 && offset_expr
.X_op
!= O_constant
)
3439 as_bad ("expression too complex");
3440 offset_expr
.X_op
= O_constant
;
3443 /* Even on a big endian machine $fn comes before $fn+1. We have
3444 to adjust when loading from memory. We set coproc if we must
3445 load $fn+1 first. */
3446 if (byte_order
== LITTLE_ENDIAN
)
3449 if (mips_pic
== NO_PIC
3450 || offset_expr
.X_op
== O_constant
)
3452 /* If this is a reference to a GP relative symbol, we want
3453 <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL)
3454 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_MIPS_GPREL)
3455 If we have a base register, we use this
3457 <op> $treg,<sym>($at) (BFD_RELOC_MIPS_GPREL)
3458 <op> $treg+1,<sym>+4($at) (BFD_RELOC_MIPS_GPREL)
3459 If this is not a GP relative symbol, we want
3460 lui $at,<sym> (BFD_RELOC_HI16_S)
3461 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
3462 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
3463 If there is a base register, we add it to $at after the
3464 lui instruction. If there is a constant, we always use
3466 if (offset_expr
.X_add_number
!= 0
3467 || nopic_need_relax (offset_expr
.X_add_symbol
))
3486 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3487 mips_isa
< 3 ? "addu" : "daddu",
3488 "d,v,t", AT
, breg
, GP
);
3494 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
3495 coproc
? treg
+ 1 : treg
,
3496 (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
3497 offset_expr
.X_add_number
+= 4;
3499 /* Set mips_optimize to 2 to avoid inserting an
3501 hold_mips_optimize
= mips_optimize
;
3503 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
3504 coproc
? treg
: treg
+ 1,
3505 (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
3506 mips_optimize
= hold_mips_optimize
;
3508 p
= frag_var (rs_machine_dependent
, 12 + off
, 0,
3509 RELAX_ENCODE (8 + off
, 12 + off
, 0, 4 + off
, 1,
3510 used_at
&& mips_noat
),
3511 offset_expr
.X_add_symbol
, (long) 0,
3514 /* We just generated two relocs. When tc_gen_reloc
3515 handles this case, it will skip the first reloc and
3516 handle the second. The second reloc already has an
3517 extra addend of 4, which we added above. We must
3518 subtract it out, and then subtract another 4 to make
3519 the first reloc come out right. The second reloc
3520 will come out right because we are going to add 4 to
3521 offset_expr when we build its instruction below. */
3522 offset_expr
.X_add_number
-= 8;
3523 offset_expr
.X_op
= O_constant
;
3525 macro_build_lui (p
, &icnt
, &offset_expr
, AT
);
3530 macro_build (p
, &icnt
, (expressionS
*) NULL
,
3531 mips_isa
< 3 ? "addu" : "daddu",
3532 "d,v,t", AT
, breg
, AT
);
3536 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
,
3537 coproc
? treg
+ 1 : treg
,
3538 (int) BFD_RELOC_LO16
, AT
);
3541 /* FIXME: How do we handle overflow here? */
3542 offset_expr
.X_add_number
+= 4;
3543 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
,
3544 coproc
? treg
: treg
+ 1,
3545 (int) BFD_RELOC_LO16
, AT
);
3547 else if (mips_pic
== SVR4_PIC
)
3551 /* If this is a reference to an external symbol, we want
3552 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3557 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3559 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
3560 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
3561 If there is a base register we add it to $at before the
3562 lwc1 instructions. If there is a constant we include it
3563 in the lwc1 instructions. */
3565 expr1
.X_add_number
= offset_expr
.X_add_number
;
3566 offset_expr
.X_add_number
= 0;
3567 if (expr1
.X_add_number
< -0x8000
3568 || expr1
.X_add_number
>= 0x8000 - 4)
3569 as_bad ("PIC code offset overflow (max 16 signed bits)");
3574 frag_grow (24 + off
);
3575 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3576 mips_isa
< 3 ? "lw" : "ld",
3577 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
3578 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
3580 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3581 mips_isa
< 3 ? "addu" : "daddu",
3582 "d,v,t", AT
, breg
, AT
);
3583 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
3584 coproc
? treg
+ 1 : treg
,
3585 (int) BFD_RELOC_LO16
, AT
);
3586 expr1
.X_add_number
+= 4;
3588 /* Set mips_optimize to 2 to avoid inserting an undesired
3590 hold_mips_optimize
= mips_optimize
;
3592 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
3593 coproc
? treg
: treg
+ 1,
3594 (int) BFD_RELOC_LO16
, AT
);
3595 mips_optimize
= hold_mips_optimize
;
3597 (void) frag_var (rs_machine_dependent
, 0, 0,
3598 RELAX_ENCODE (0, 0, -16 - off
, -8, 1, 0),
3599 offset_expr
.X_add_symbol
, (long) 0,
3602 else if (mips_pic
== EMBEDDED_PIC
)
3604 /* If there is no base register, we use
3605 <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL)
3606 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_MIPS_GPREL)
3607 If we have a base register, we use
3609 <op> $treg,<sym>($at) (BFD_RELOC_MIPS_GPREL)
3610 <op> $treg+1,<sym>+4($at) (BFD_RELOC_MIPS_GPREL)
3619 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3620 mips_isa
< 3 ? "addu" : "daddu",
3621 "d,v,t", AT
, breg
, GP
);
3626 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
3627 coproc
? treg
+ 1 : treg
,
3628 (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
3629 offset_expr
.X_add_number
+= 4;
3630 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
3631 coproc
? treg
: treg
+ 1,
3632 (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
3648 assert (mips_isa
< 3);
3649 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
3650 (int) BFD_RELOC_LO16
, breg
);
3651 offset_expr
.X_add_number
+= 4;
3652 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
+ 1,
3653 (int) BFD_RELOC_LO16
, breg
);
3655 #ifdef LOSING_COMPILER
3661 as_warn ("Macro used $at after \".set noat\"");
3666 struct mips_cl_insn
*ip
;
3668 register int treg
, sreg
, dreg
, breg
;
3683 bfd_reloc_code_real_type r
;
3686 treg
= (ip
->insn_opcode
>> 16) & 0x1f;
3687 dreg
= (ip
->insn_opcode
>> 11) & 0x1f;
3688 sreg
= breg
= (ip
->insn_opcode
>> 21) & 0x1f;
3689 mask
= ip
->insn_mo
->mask
;
3691 expr1
.X_op
= O_constant
;
3692 expr1
.X_op_symbol
= NULL
;
3693 expr1
.X_add_symbol
= NULL
;
3694 expr1
.X_add_number
= 1;
3698 #endif /* LOSING_COMPILER */
3703 macro_build ((char *) NULL
, &icnt
, NULL
,
3704 dbl
? "dmultu" : "multu",
3706 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
3712 /* The MIPS assembler some times generates shifts and adds. I'm
3713 not trying to be that fancy. GCC should do this for us
3715 load_register (&icnt
, AT
, &imm_expr
, dbl
);
3716 macro_build ((char *) NULL
, &icnt
, NULL
,
3717 dbl
? "dmult" : "mult",
3719 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
3725 mips_emit_delays ();
3727 mips_any_noreorder
= 1;
3728 macro_build ((char *) NULL
, &icnt
, NULL
,
3729 dbl
? "dmult" : "mult",
3731 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
3732 macro_build ((char *) NULL
, &icnt
, NULL
,
3733 dbl
? "dsra32" : "sra",
3734 "d,w,<", dreg
, dreg
, 31);
3735 macro_build ((char *) NULL
, &icnt
, NULL
, "mfhi", "d", AT
);
3737 macro_build ((char *) NULL
, &icnt
, NULL
, "tne", "s,t", dreg
, AT
);
3740 expr1
.X_add_number
= 8;
3741 macro_build ((char *) NULL
, &icnt
, &expr1
, "beq", "s,t,p", dreg
, AT
);
3742 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
3743 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 6);
3746 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
3752 mips_emit_delays ();
3754 mips_any_noreorder
= 1;
3755 macro_build ((char *) NULL
, &icnt
, NULL
,
3756 dbl
? "dmultu" : "multu",
3758 macro_build ((char *) NULL
, &icnt
, NULL
, "mfhi", "d", AT
);
3759 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
3761 macro_build ((char *) NULL
, &icnt
, NULL
, "tne", "s,t", AT
, 0);
3764 expr1
.X_add_number
= 8;
3765 macro_build ((char *) NULL
, &icnt
, &expr1
, "beq", "s,t,p", AT
, 0);
3766 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
3767 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 6);
3773 macro_build ((char *) NULL
, &icnt
, NULL
, "subu", "d,v,t", AT
, 0, treg
);
3774 macro_build ((char *) NULL
, &icnt
, NULL
, "srlv", "d,t,s", AT
, sreg
, AT
);
3775 macro_build ((char *) NULL
, &icnt
, NULL
, "sllv", "d,t,s", dreg
, sreg
,
3777 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
3781 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", AT
, sreg
,
3782 imm_expr
.X_add_number
& 0x1f);
3783 macro_build ((char *) NULL
, &icnt
, NULL
, "srl", "d,w,<", dreg
, sreg
,
3784 (0 - imm_expr
.X_add_number
) & 0x1f);
3785 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
3789 macro_build ((char *) NULL
, &icnt
, NULL
, "subu", "d,v,t", AT
, 0, treg
);
3790 macro_build ((char *) NULL
, &icnt
, NULL
, "sllv", "d,t,s", AT
, sreg
, AT
);
3791 macro_build ((char *) NULL
, &icnt
, NULL
, "srlv", "d,t,s", dreg
, sreg
,
3793 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
3797 macro_build ((char *) NULL
, &icnt
, NULL
, "srl", "d,w,<", AT
, sreg
,
3798 imm_expr
.X_add_number
& 0x1f);
3799 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", dreg
, sreg
,
3800 (0 - imm_expr
.X_add_number
) & 0x1f);
3801 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
3805 assert (mips_isa
< 2);
3806 /* Even on a big endian machine $fn comes before $fn+1. We have
3807 to adjust when storing to memory. */
3808 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "swc1", "T,o(b)",
3809 byte_order
== LITTLE_ENDIAN
? treg
: treg
+ 1,
3810 (int) BFD_RELOC_LO16
, breg
);
3811 offset_expr
.X_add_number
+= 4;
3812 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "swc1", "T,o(b)",
3813 byte_order
== LITTLE_ENDIAN
? treg
+ 1 : treg
,
3814 (int) BFD_RELOC_LO16
, breg
);
3819 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
3820 treg
, (int) BFD_RELOC_LO16
);
3822 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
3823 sreg
, (int) BFD_RELOC_LO16
);
3826 macro_build ((char *) NULL
, &icnt
, NULL
, "xor", "d,v,t", dreg
,
3828 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
3829 dreg
, (int) BFD_RELOC_LO16
);
3834 if (imm_expr
.X_add_number
== 0)
3836 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
3837 sreg
, (int) BFD_RELOC_LO16
);
3842 as_warn ("Instruction %s: result is always false",
3844 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
, 0);
3847 if (imm_expr
.X_add_number
>= 0 && imm_expr
.X_add_number
< 0x10000)
3849 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "xori", "t,r,i", dreg
,
3850 sreg
, (int) BFD_RELOC_LO16
);
3853 else if (imm_expr
.X_add_number
> -0x8000 && imm_expr
.X_add_number
< 0)
3855 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
3856 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
3857 mips_isa
< 3 ? "addiu" : "daddiu",
3858 "t,r,j", dreg
, sreg
,
3859 (int) BFD_RELOC_LO16
);
3864 load_register (&icnt
, AT
, &imm_expr
, 0);
3865 macro_build ((char *) NULL
, &icnt
, NULL
, "xor", "d,v,t", dreg
,
3869 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
, dreg
,
3870 (int) BFD_RELOC_LO16
);
3875 case M_SGE
: /* sreg >= treg <==> not (sreg < treg) */
3881 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, sreg
, treg
);
3882 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
3883 (int) BFD_RELOC_LO16
);
3886 case M_SGE_I
: /* sreg >= I <==> not (sreg < I) */
3888 if (imm_expr
.X_add_number
>= -0x8000 && imm_expr
.X_add_number
< 0x8000)
3890 macro_build ((char *) NULL
, &icnt
, &expr1
,
3891 mask
== M_SGE_I
? "slti" : "sltiu",
3892 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
3897 load_register (&icnt
, AT
, &imm_expr
, 0);
3898 macro_build ((char *) NULL
, &icnt
, NULL
,
3899 mask
== M_SGE_I
? "slt" : "sltu",
3900 "d,v,t", dreg
, sreg
, AT
);
3903 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
3904 (int) BFD_RELOC_LO16
);
3909 case M_SGT
: /* sreg > treg <==> treg < sreg */
3915 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, treg
, sreg
);
3918 case M_SGT_I
: /* sreg > I <==> I < sreg */
3924 load_register (&icnt
, AT
, &imm_expr
, 0);
3925 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, AT
, sreg
);
3928 case M_SLE
: /* sreg <= treg <==> treg >= sreg <==> not (treg < sreg) */
3934 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, treg
, sreg
);
3935 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
3936 (int) BFD_RELOC_LO16
);
3939 case M_SLE_I
: /* sreg <= I <==> I >= sreg <==> not (I < sreg) */
3945 load_register (&icnt
, AT
, &imm_expr
, 0);
3946 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, AT
, sreg
);
3947 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
3948 (int) BFD_RELOC_LO16
);
3952 if (imm_expr
.X_add_number
>= -0x8000 && imm_expr
.X_add_number
< 0x8000)
3954 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "slti", "t,r,j",
3955 dreg
, sreg
, (int) BFD_RELOC_LO16
);
3958 load_register (&icnt
, AT
, &imm_expr
, 0);
3959 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", dreg
, sreg
, AT
);
3963 if (imm_expr
.X_add_number
>= -0x8000 && imm_expr
.X_add_number
< 0x8000)
3965 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "sltiu", "t,r,j",
3966 dreg
, sreg
, (int) BFD_RELOC_LO16
);
3969 load_register (&icnt
, AT
, &imm_expr
, 0);
3970 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, sreg
,
3976 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0,
3979 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0,
3983 macro_build ((char *) NULL
, &icnt
, NULL
, "xor", "d,v,t", dreg
,
3985 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0,
3991 if (imm_expr
.X_add_number
== 0)
3993 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0,
3999 as_warn ("Instruction %s: result is always true",
4001 macro_build ((char *) NULL
, &icnt
, &expr1
,
4002 mips_isa
< 3 ? "addiu" : "daddiu",
4003 "t,r,j", dreg
, 0, (int) BFD_RELOC_LO16
);
4006 if (imm_expr
.X_add_number
>= 0 && imm_expr
.X_add_number
< 0x10000)
4008 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "xori", "t,r,i",
4009 dreg
, sreg
, (int) BFD_RELOC_LO16
);
4012 else if (imm_expr
.X_add_number
> -0x8000 && imm_expr
.X_add_number
< 0)
4014 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
4015 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
4016 mips_isa
< 3 ? "addiu" : "daddiu",
4017 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
4022 load_register (&icnt
, AT
, &imm_expr
, 0);
4023 macro_build ((char *) NULL
, &icnt
, NULL
, "xor", "d,v,t", dreg
,
4027 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0, dreg
);
4035 if (imm_expr
.X_add_number
> -0x8000 && imm_expr
.X_add_number
<= 0x8000)
4037 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
4038 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
4039 dbl
? "daddi" : "addi",
4040 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
4043 load_register (&icnt
, AT
, &imm_expr
, dbl
);
4044 macro_build ((char *) NULL
, &icnt
, NULL
,
4045 dbl
? "dsub" : "sub",
4046 "d,v,t", dreg
, sreg
, AT
);
4052 if (imm_expr
.X_add_number
> -0x8000 && imm_expr
.X_add_number
<= 0x8000)
4054 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
4055 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
4056 dbl
? "daddiu" : "addiu",
4057 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
4060 load_register (&icnt
, AT
, &imm_expr
, dbl
);
4061 macro_build ((char *) NULL
, &icnt
, NULL
,
4062 dbl
? "dsubu" : "subu",
4063 "d,v,t", dreg
, sreg
, AT
);
4084 load_register (&icnt
, AT
, &imm_expr
, 0);
4085 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "s,t", sreg
, AT
);
4090 assert (mips_isa
< 2);
4091 sreg
= (ip
->insn_opcode
>> 11) & 0x1f; /* floating reg */
4092 dreg
= (ip
->insn_opcode
>> 06) & 0x1f; /* floating reg */
4095 * Is the double cfc1 instruction a bug in the mips assembler;
4096 * or is there a reason for it?
4098 mips_emit_delays ();
4100 mips_any_noreorder
= 1;
4101 macro_build ((char *) NULL
, &icnt
, NULL
, "cfc1", "t,G", treg
, 31);
4102 macro_build ((char *) NULL
, &icnt
, NULL
, "cfc1", "t,G", treg
, 31);
4103 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "");
4104 expr1
.X_add_number
= 3;
4105 macro_build ((char *) NULL
, &icnt
, &expr1
, "ori", "t,r,i", AT
, treg
,
4106 (int) BFD_RELOC_LO16
);
4107 expr1
.X_add_number
= 2;
4108 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", AT
, AT
,
4109 (int) BFD_RELOC_LO16
);
4110 macro_build ((char *) NULL
, &icnt
, NULL
, "ctc1", "t,G", AT
, 31);
4111 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "");
4112 macro_build ((char *) NULL
, &icnt
, NULL
,
4113 mask
== M_TRUNCWD
? "cvt.w.d" : "cvt.w.s", "D,S", dreg
, sreg
);
4114 macro_build ((char *) NULL
, &icnt
, NULL
, "ctc1", "t,G", treg
, 31);
4115 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "");
4125 if (offset_expr
.X_add_number
>= 0x7fff)
4126 as_bad ("operand overflow");
4127 /* avoid load delay */
4128 if (byte_order
== LITTLE_ENDIAN
)
4129 offset_expr
.X_add_number
+= 1;
4130 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
4131 (int) BFD_RELOC_LO16
, breg
);
4132 if (byte_order
== LITTLE_ENDIAN
)
4133 offset_expr
.X_add_number
-= 1;
4135 offset_expr
.X_add_number
+= 1;
4136 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lbu", "t,o(b)", AT
,
4137 (int) BFD_RELOC_LO16
, breg
);
4138 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", treg
, treg
, 8);
4139 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", treg
, treg
, AT
);
4152 if (offset_expr
.X_add_number
>= 0x8000 - off
)
4153 as_bad ("operand overflow");
4154 if (byte_order
== LITTLE_ENDIAN
)
4155 offset_expr
.X_add_number
+= off
;
4156 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
4157 (int) BFD_RELOC_LO16
, breg
);
4158 if (byte_order
== LITTLE_ENDIAN
)
4159 offset_expr
.X_add_number
-= off
;
4161 offset_expr
.X_add_number
+= off
;
4162 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s2
, "t,o(b)", treg
,
4163 (int) BFD_RELOC_LO16
, breg
);
4176 load_address (&icnt
, AT
, &offset_expr
);
4177 if (byte_order
== LITTLE_ENDIAN
)
4178 expr1
.X_add_number
= off
;
4180 expr1
.X_add_number
= 0;
4181 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, "t,o(b)", treg
,
4182 (int) BFD_RELOC_LO16
, AT
);
4183 if (byte_order
== LITTLE_ENDIAN
)
4184 expr1
.X_add_number
= 0;
4186 expr1
.X_add_number
= off
;
4187 macro_build ((char *) NULL
, &icnt
, &expr1
, s2
, "t,o(b)", treg
,
4188 (int) BFD_RELOC_LO16
, AT
);
4193 load_address (&icnt
, AT
, &offset_expr
);
4194 if (byte_order
== BIG_ENDIAN
)
4195 expr1
.X_add_number
= 0;
4196 macro_build ((char *) NULL
, &icnt
, &expr1
,
4197 mask
== M_ULH_A
? "lb" : "lbu", "t,o(b)", treg
,
4198 (int) BFD_RELOC_LO16
, AT
);
4199 if (byte_order
== BIG_ENDIAN
)
4200 expr1
.X_add_number
= 1;
4202 expr1
.X_add_number
= 0;
4203 macro_build ((char *) NULL
, &icnt
, &expr1
, "lbu", "t,o(b)", AT
,
4204 (int) BFD_RELOC_LO16
, AT
);
4205 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", treg
,
4207 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", treg
,
4212 if (offset_expr
.X_add_number
>= 0x7fff)
4213 as_bad ("operand overflow");
4214 if (byte_order
== BIG_ENDIAN
)
4215 offset_expr
.X_add_number
+= 1;
4216 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "sb", "t,o(b)", treg
,
4217 (int) BFD_RELOC_LO16
, breg
);
4218 macro_build ((char *) NULL
, &icnt
, NULL
, "srl", "d,w,<", AT
, treg
, 8);
4219 if (byte_order
== BIG_ENDIAN
)
4220 offset_expr
.X_add_number
-= 1;
4222 offset_expr
.X_add_number
+= 1;
4223 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "sb", "t,o(b)", AT
,
4224 (int) BFD_RELOC_LO16
, breg
);
4237 if (offset_expr
.X_add_number
>= 0x8000 - off
)
4238 as_bad ("operand overflow");
4239 if (byte_order
== LITTLE_ENDIAN
)
4240 offset_expr
.X_add_number
+= off
;
4241 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
4242 (int) BFD_RELOC_LO16
, breg
);
4243 if (byte_order
== LITTLE_ENDIAN
)
4244 offset_expr
.X_add_number
-= off
;
4246 offset_expr
.X_add_number
+= off
;
4247 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s2
, "t,o(b)", treg
,
4248 (int) BFD_RELOC_LO16
, breg
);
4261 load_address (&icnt
, AT
, &offset_expr
);
4262 if (byte_order
== LITTLE_ENDIAN
)
4263 expr1
.X_add_number
= off
;
4265 expr1
.X_add_number
= 0;
4266 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, "t,o(b)", treg
,
4267 (int) BFD_RELOC_LO16
, AT
);
4268 if (byte_order
== LITTLE_ENDIAN
)
4269 expr1
.X_add_number
= 0;
4271 expr1
.X_add_number
= off
;
4272 macro_build ((char *) NULL
, &icnt
, &expr1
, s2
, "t,o(b)", treg
,
4273 (int) BFD_RELOC_LO16
, AT
);
4277 load_address (&icnt
, AT
, &offset_expr
);
4278 if (byte_order
== LITTLE_ENDIAN
)
4279 expr1
.X_add_number
= 0;
4280 macro_build ((char *) NULL
, &icnt
, &expr1
, "sb", "t,o(b)", treg
,
4281 (int) BFD_RELOC_LO16
, AT
);
4282 macro_build ((char *) NULL
, &icnt
, NULL
, "srl", "d,w,<", treg
,
4284 if (byte_order
== LITTLE_ENDIAN
)
4285 expr1
.X_add_number
= 1;
4287 expr1
.X_add_number
= 0;
4288 macro_build ((char *) NULL
, &icnt
, &expr1
, "sb", "t,o(b)", treg
,
4289 (int) BFD_RELOC_LO16
, AT
);
4290 if (byte_order
== LITTLE_ENDIAN
)
4291 expr1
.X_add_number
= 0;
4293 expr1
.X_add_number
= 1;
4294 macro_build ((char *) NULL
, &icnt
, &expr1
, "lbu", "t,o(b)", AT
,
4295 (int) BFD_RELOC_LO16
, AT
);
4296 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", treg
,
4298 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", treg
,
4303 as_bad ("Macro %s not implemented yet", ip
->insn_mo
->name
);
4307 as_warn ("Macro used $at after \".set noat\"");
4312 This routine assembles an instruction into its binary format. As a side
4313 effect it sets one of the global variables imm_reloc or offset_reloc to the
4314 type of relocation to do if one of the operands is an address expression.
4319 struct mips_cl_insn
*ip
;
4324 struct mips_opcode
*insn
;
4327 unsigned int lastregno
= 0;
4332 for (s
= str
; islower (*s
) || (*s
>= '0' && *s
<= '3') || *s
== '.'; ++s
)
4344 as_fatal ("Unknown opcode: `%s'", str
);
4346 if ((insn
= (struct mips_opcode
*) hash_find (op_hash
, str
)) == NULL
)
4348 as_warn ("`%s' not in hash table.", str
);
4349 insn_error
= "ERROR: Unrecognized opcode";
4357 assert (strcmp (insn
->name
, str
) == 0);
4359 if (insn
->pinfo
== INSN_MACRO
)
4360 insn_isa
= insn
->match
;
4361 else if ((insn
->pinfo
& INSN_ISA
) == INSN_ISA2
)
4363 else if ((insn
->pinfo
& INSN_ISA
) == INSN_ISA3
)
4365 else if ((insn
->pinfo
& INSN_ISA
) == INSN_ISA4
)
4370 if (insn_isa
> mips_isa
4371 || ((insn
->pinfo
& INSN_ISA
) == INSN_4650
4374 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
]
4375 && strcmp (insn
->name
, insn
[1].name
) == 0)
4380 as_warn ("Instruction not supported on this processor");
4384 ip
->insn_opcode
= insn
->match
;
4385 for (args
= insn
->args
;; ++args
)
4391 case '\0': /* end of args */
4404 ip
->insn_opcode
|= lastregno
<< 21;
4409 ip
->insn_opcode
|= lastregno
<< 16;
4413 ip
->insn_opcode
|= lastregno
<< 11;
4419 /* handle optional base register.
4420 Either the base register is omitted or
4421 we must have a left paren. */
4422 /* this is dependent on the next operand specifier
4423 is a 'b' for base register */
4424 assert (args
[1] == 'b');
4428 case ')': /* these must match exactly */
4433 case '<': /* must be at least one digit */
4435 * According to the manual, if the shift amount is greater
4436 * than 31 or less than 0 the the shift amount should be
4437 * mod 32. In reality the mips assembler issues an error.
4438 * We issue a warning and mask out all but the low 5 bits.
4440 my_getExpression (&imm_expr
, s
);
4441 check_absolute_expr (ip
, &imm_expr
);
4442 if ((unsigned long) imm_expr
.X_add_number
> 31)
4444 as_warn ("Improper shift amount (%ld)",
4445 (long) imm_expr
.X_add_number
);
4446 imm_expr
.X_add_number
= imm_expr
.X_add_number
& 0x1f;
4448 ip
->insn_opcode
|= imm_expr
.X_add_number
<< 6;
4449 imm_expr
.X_op
= O_absent
;
4453 case '>': /* shift amount minus 32 */
4454 my_getExpression (&imm_expr
, s
);
4455 check_absolute_expr (ip
, &imm_expr
);
4456 if ((unsigned long) imm_expr
.X_add_number
< 32
4457 || (unsigned long) imm_expr
.X_add_number
> 63)
4459 ip
->insn_opcode
|= (imm_expr
.X_add_number
- 32) << 6;
4460 imm_expr
.X_op
= O_absent
;
4464 case 'k': /* cache code */
4465 case 'h': /* prefx code */
4466 my_getExpression (&imm_expr
, s
);
4467 check_absolute_expr (ip
, &imm_expr
);
4468 if ((unsigned long) imm_expr
.X_add_number
> 31)
4470 as_warn ("Invalid value for `%s' (%lu)",
4472 (unsigned long) imm_expr
.X_add_number
);
4473 imm_expr
.X_add_number
&= 0x1f;
4476 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_CACHE
;
4478 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_PREFX
;
4479 imm_expr
.X_op
= O_absent
;
4483 case 'c': /* break code */
4484 my_getExpression (&imm_expr
, s
);
4485 check_absolute_expr (ip
, &imm_expr
);
4486 if ((unsigned) imm_expr
.X_add_number
> 1023)
4487 as_warn ("Illegal break code (%ld)",
4488 (long) imm_expr
.X_add_number
);
4489 ip
->insn_opcode
|= imm_expr
.X_add_number
<< 16;
4490 imm_expr
.X_op
= O_absent
;
4494 case 'B': /* syscall code */
4495 my_getExpression (&imm_expr
, s
);
4496 check_absolute_expr (ip
, &imm_expr
);
4497 if ((unsigned) imm_expr
.X_add_number
> 0xfffff)
4498 as_warn ("Illegal syscall code (%ld)",
4499 (long) imm_expr
.X_add_number
);
4500 ip
->insn_opcode
|= imm_expr
.X_add_number
<< 6;
4501 imm_expr
.X_op
= O_absent
;
4505 case 'C': /* Coprocessor code */
4506 my_getExpression (&imm_expr
, s
);
4507 check_absolute_expr (ip
, &imm_expr
);
4508 if ((unsigned long) imm_expr
.X_add_number
>= (1<<25))
4510 as_warn ("Coproccesor code > 25 bits (%ld)",
4511 (long) imm_expr
.X_add_number
);
4512 imm_expr
.X_add_number
&= ((1<<25) - 1);
4514 ip
->insn_opcode
|= imm_expr
.X_add_number
;
4515 imm_expr
.X_op
= O_absent
;
4519 case 'b': /* base register */
4520 case 'd': /* destination register */
4521 case 's': /* source register */
4522 case 't': /* target register */
4523 case 'r': /* both target and source */
4524 case 'v': /* both dest and source */
4525 case 'w': /* both dest and target */
4526 case 'E': /* coprocessor target register */
4527 case 'G': /* coprocessor destination register */
4528 case 'x': /* ignore register name */
4529 case 'z': /* must be zero register */
4543 while (isdigit (*s
));
4545 as_bad ("Invalid register number (%d)", regno
);
4547 else if (*args
== 'E' || *args
== 'G')
4551 if (s
[1] == 'f' && s
[2] == 'p')
4556 else if (s
[1] == 's' && s
[2] == 'p')
4561 else if (s
[1] == 'g' && s
[2] == 'p')
4566 else if (s
[1] == 'a' && s
[2] == 't')
4571 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '0')
4576 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '1')
4584 if (regno
== AT
&& ! mips_noat
)
4585 as_warn ("Used $at without \".set noat\"");
4591 if (c
== 'r' || c
== 'v' || c
== 'w')
4598 /* 'z' only matches $0. */
4599 if (c
== 'z' && regno
!= 0)
4607 ip
->insn_opcode
|= regno
<< 21;
4611 ip
->insn_opcode
|= regno
<< 11;
4616 ip
->insn_opcode
|= regno
<< 16;
4619 /* This case exists because on the r3000 trunc
4620 expands into a macro which requires a gp
4621 register. On the r6000 or r4000 it is
4622 assembled into a single instruction which
4623 ignores the register. Thus the insn version
4624 is MIPS_ISA2 and uses 'x', and the macro
4625 version is MIPS_ISA1 and uses 't'. */
4628 /* This case is for the div instruction, which
4629 acts differently if the destination argument
4630 is $0. This only matches $0, and is checked
4631 outside the switch. */
4642 ip
->insn_opcode
|= lastregno
<< 21;
4645 ip
->insn_opcode
|= lastregno
<< 16;
4650 case 'D': /* floating point destination register */
4651 case 'S': /* floating point source register */
4652 case 'T': /* floating point target register */
4653 case 'R': /* floating point source register */
4657 if (s
[0] == '$' && s
[1] == 'f' && isdigit (s
[2]))
4667 while (isdigit (*s
));
4670 as_bad ("Invalid float register number (%d)", regno
);
4672 if ((regno
& 1) != 0
4674 && ! (strcmp (str
, "mtc1") == 0 ||
4675 strcmp (str
, "mfc1") == 0 ||
4676 strcmp (str
, "lwc1") == 0 ||
4677 strcmp (str
, "swc1") == 0))
4678 as_warn ("Float register should be even, was %d",
4686 if (c
== 'V' || c
== 'W')
4696 ip
->insn_opcode
|= regno
<< 6;
4700 ip
->insn_opcode
|= regno
<< 11;
4704 ip
->insn_opcode
|= regno
<< 16;
4707 ip
->insn_opcode
|= regno
<< 21;
4716 ip
->insn_opcode
|= lastregno
<< 11;
4719 ip
->insn_opcode
|= lastregno
<< 16;
4725 my_getExpression (&imm_expr
, s
);
4726 if (imm_expr
.X_op
!= O_big
)
4727 check_absolute_expr (ip
, &imm_expr
);
4732 my_getExpression (&offset_expr
, s
);
4733 imm_reloc
= BFD_RELOC_32
;
4745 unsigned char temp
[8];
4747 unsigned int length
;
4752 /* These only appear as the last operand in an
4753 instruction, and every instruction that accepts
4754 them in any variant accepts them in all variants.
4755 This means we don't have to worry about backing out
4756 any changes if the instruction does not match.
4758 The difference between them is the size of the
4759 floating point constant and where it goes. For 'F'
4760 and 'L' the constant is 64 bits; for 'f' and 'l' it
4761 is 32 bits. Where the constant is placed is based
4762 on how the MIPS assembler does things:
4765 f -- immediate value
4768 The .lit4 and .lit8 sections are only used if
4769 permitted by the -G argument.
4771 When generating embedded PIC code, we use the
4772 .lit8 section but not the .lit4 section (we can do
4773 .lit4 inline easily; we need to put .lit8
4774 somewhere in the data segment, and using .lit8
4775 permits the linker to eventually combine identical
4778 f64
= *args
== 'F' || *args
== 'L';
4780 save_in
= input_line_pointer
;
4781 input_line_pointer
= s
;
4782 err
= md_atof (f64
? 'd' : 'f', (char *) temp
, &len
);
4784 s
= input_line_pointer
;
4785 input_line_pointer
= save_in
;
4786 if (err
!= NULL
&& *err
!= '\0')
4788 as_bad ("Bad floating point constant: %s", err
);
4789 memset (temp
, '\0', sizeof temp
);
4790 length
= f64
? 8 : 4;
4793 assert (length
== (f64
? 8 : 4));
4798 && (mips_pic
== EMBEDDED_PIC
4799 || g_switch_value
< 4)
4803 imm_expr
.X_op
= O_constant
;
4804 if (byte_order
== LITTLE_ENDIAN
)
4805 imm_expr
.X_add_number
=
4806 (((((((int) temp
[3] << 8)
4811 imm_expr
.X_add_number
=
4812 (((((((int) temp
[0] << 8)
4819 const char *newname
;
4822 /* Switch to the right section. */
4824 subseg
= now_subseg
;
4827 default: /* unused default case avoids warnings. */
4829 newname
= RDATA_SECTION_NAME
;
4831 if (g_switch_value
>= 8)
4836 newname
= RDATA_SECTION_NAME
;
4840 assert (g_switch_value
>= 4);
4845 new_seg
= subseg_new (newname
, (subsegT
) 0);
4846 frag_align (*args
== 'l' ? 2 : 3, 0);
4848 record_alignment (new_seg
, 4);
4850 record_alignment (new_seg
, *args
== 'l' ? 2 : 3);
4853 as_bad ("Can't use floating point insn in this section");
4855 /* Set the argument to the current address in the
4857 offset_expr
.X_op
= O_symbol
;
4858 offset_expr
.X_add_symbol
=
4859 symbol_new ("L0\001", now_seg
,
4860 (valueT
) frag_now_fix (), frag_now
);
4861 offset_expr
.X_add_number
= 0;
4863 /* Put the floating point number into the section. */
4864 p
= frag_more ((int) length
);
4865 memcpy (p
, temp
, length
);
4867 /* Switch back to the original section. */
4868 subseg_set (seg
, subseg
);
4873 case 'i': /* 16 bit unsigned immediate */
4874 case 'j': /* 16 bit signed immediate */
4875 imm_reloc
= BFD_RELOC_LO16
;
4876 c
= my_getSmallExpression (&imm_expr
, s
);
4881 if (imm_expr
.X_op
== O_constant
)
4882 imm_expr
.X_add_number
=
4883 (imm_expr
.X_add_number
>> 16) & 0xffff;
4885 imm_reloc
= BFD_RELOC_HI16_S
;
4887 imm_reloc
= BFD_RELOC_HI16
;
4890 else if (imm_expr
.X_op
!= O_big
)
4891 check_absolute_expr (ip
, &imm_expr
);
4894 if (imm_expr
.X_op
== O_big
4895 || imm_expr
.X_add_number
< 0
4896 || imm_expr
.X_add_number
>= 0x10000)
4898 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
4899 !strcmp (insn
->name
, insn
[1].name
))
4901 as_bad ("16 bit expression not in range 0..65535");
4909 /* The upper bound should be 0x8000, but
4910 unfortunately the MIPS assembler accepts numbers
4911 from 0x8000 to 0xffff and sign extends them, and
4912 we want to be compatible. We only permit this
4913 extended range for an instruction which does not
4914 provide any further alternates, since those
4915 alternates may handle other cases. People should
4916 use the numbers they mean, rather than relying on
4917 a mysterious sign extension. */
4918 more
= (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
4919 strcmp (insn
->name
, insn
[1].name
) == 0);
4924 if (imm_expr
.X_op
== O_big
4925 || imm_expr
.X_add_number
< -0x8000
4926 || imm_expr
.X_add_number
>= max
4928 && imm_expr
.X_add_number
< 0
4930 && imm_expr
.X_unsigned
4931 && sizeof (imm_expr
.X_add_number
) <= 4))
4935 as_bad ("16 bit expression not in range -32768..32767");
4941 case 'o': /* 16 bit offset */
4942 c
= my_getSmallExpression (&offset_expr
, s
);
4944 /* If this value won't fit into a 16 bit offset, then go
4945 find a macro that will generate the 32 bit offset
4946 code pattern. As a special hack, we accept the
4947 difference of two local symbols as a constant. This
4948 is required to suppose embedded PIC switches, which
4949 use an instruction which looks like
4950 lw $4,$L12-$LS12($4)
4951 The problem with handling this in a more general
4952 fashion is that the macro function doesn't expect to
4953 see anything which can be handled in a single
4954 constant instruction. */
4956 && (offset_expr
.X_op
!= O_constant
4957 || offset_expr
.X_add_number
>= 0x8000
4958 || offset_expr
.X_add_number
< -0x8000)
4959 && (mips_pic
!= EMBEDDED_PIC
4960 || offset_expr
.X_op
!= O_subtract
4961 || now_seg
!= text_section
4962 || (S_GET_SEGMENT (offset_expr
.X_op_symbol
)
4966 offset_reloc
= BFD_RELOC_LO16
;
4967 if (c
== 'h' || c
== 'H')
4969 assert (offset_expr
.X_op
== O_constant
);
4970 offset_expr
.X_add_number
=
4971 (offset_expr
.X_add_number
>> 16) & 0xffff;
4976 case 'p': /* pc relative offset */
4977 offset_reloc
= BFD_RELOC_16_PCREL_S2
;
4978 my_getExpression (&offset_expr
, s
);
4982 case 'u': /* upper 16 bits */
4983 c
= my_getSmallExpression (&imm_expr
, s
);
4984 if (imm_expr
.X_op
== O_constant
4985 && (imm_expr
.X_add_number
< 0
4986 || imm_expr
.X_add_number
>= 0x10000))
4987 as_bad ("lui expression not in range 0..65535");
4988 imm_reloc
= BFD_RELOC_LO16
;
4993 if (imm_expr
.X_op
== O_constant
)
4994 imm_expr
.X_add_number
=
4995 (imm_expr
.X_add_number
>> 16) & 0xffff;
4997 imm_reloc
= BFD_RELOC_HI16_S
;
4999 imm_reloc
= BFD_RELOC_HI16
;
5005 case 'a': /* 26 bit address */
5006 my_getExpression (&offset_expr
, s
);
5008 offset_reloc
= BFD_RELOC_MIPS_JMP
;
5011 case 'N': /* 3 bit branch condition code */
5012 case 'M': /* 3 bit compare condition code */
5013 my_getExpression (&imm_expr
, s
);
5014 check_absolute_expr (ip
, &imm_expr
);
5015 if ((unsigned long) imm_expr
.X_add_number
> 7)
5017 as_warn ("Condition code > 7 (%ld)",
5018 (long) imm_expr
.X_add_number
);
5019 imm_expr
.X_add_number
&= 7;
5022 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_BCC
;
5024 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_CCC
;
5025 imm_expr
.X_op
= O_absent
;
5030 fprintf (stderr
, "bad char = '%c'\n", *args
);
5035 /* Args don't match. */
5036 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
5037 !strcmp (insn
->name
, insn
[1].name
))
5043 insn_error
= "ERROR: Illegal operands";
5052 my_getSmallExpression (ep
, str
)
5063 ((str
[1] == 'h' && str
[2] == 'i')
5064 || (str
[1] == 'H' && str
[2] == 'I')
5065 || (str
[1] == 'l' && str
[2] == 'o'))
5077 * A small expression may be followed by a base register.
5078 * Scan to the end of this operand, and then back over a possible
5079 * base register. Then scan the small expression up to that
5080 * point. (Based on code in sparc.c...)
5082 for (sp
= str
; *sp
&& *sp
!= ','; sp
++)
5084 if (sp
- 4 >= str
&& sp
[-1] == RP
)
5086 if (isdigit (sp
[-2]))
5088 for (sp
-= 3; sp
>= str
&& isdigit (*sp
); sp
--)
5090 if (*sp
== '$' && sp
> str
&& sp
[-1] == LP
)
5096 else if (sp
- 5 >= str
5099 && ((sp
[-3] == 'f' && sp
[-2] == 'p')
5100 || (sp
[-3] == 's' && sp
[-2] == 'p')
5101 || (sp
[-3] == 'g' && sp
[-2] == 'p')
5102 || (sp
[-3] == 'a' && sp
[-2] == 't')))
5108 /* no expression means zero offset */
5111 /* %xx(reg) is an error */
5112 ep
->X_op
= O_absent
;
5117 ep
->X_op
= O_constant
;
5120 ep
->X_add_symbol
= NULL
;
5121 ep
->X_op_symbol
= NULL
;
5122 ep
->X_add_number
= 0;
5127 my_getExpression (ep
, str
);
5134 my_getExpression (ep
, str
);
5135 return c
; /* => %hi or %lo encountered */
5139 my_getExpression (ep
, str
)
5145 save_in
= input_line_pointer
;
5146 input_line_pointer
= str
;
5148 expr_end
= input_line_pointer
;
5149 input_line_pointer
= save_in
;
5152 /* Turn a string in input_line_pointer into a floating point constant
5153 of type type, and store the appropriate bytes in *litP. The number
5154 of LITTLENUMS emitted is stored in *sizeP . An error message is
5155 returned, or NULL on OK. */
5158 md_atof (type
, litP
, sizeP
)
5164 LITTLENUM_TYPE words
[4];
5180 return "bad call to md_atof";
5183 t
= atof_ieee (input_line_pointer
, type
, words
);
5185 input_line_pointer
= t
;
5189 if (byte_order
== LITTLE_ENDIAN
)
5191 for (i
= prec
- 1; i
>= 0; i
--)
5193 md_number_to_chars (litP
, (valueT
) words
[i
], 2);
5199 for (i
= 0; i
< prec
; i
++)
5201 md_number_to_chars (litP
, (valueT
) words
[i
], 2);
5210 md_number_to_chars (buf
, val
, n
)
5218 number_to_chars_littleendian (buf
, val
, n
);
5222 number_to_chars_bigendian (buf
, val
, n
);
5231 CONST
char *md_shortopts
= "O::g::G:";
5233 CONST
char *md_shortopts
= "O::g::";
5235 struct option md_longopts
[] = {
5236 #define OPTION_MIPS1 (OPTION_MD_BASE + 1)
5237 {"mips0", no_argument
, NULL
, OPTION_MIPS1
},
5238 {"mips1", no_argument
, NULL
, OPTION_MIPS1
},
5239 #define OPTION_MIPS2 (OPTION_MD_BASE + 2)
5240 {"mips2", no_argument
, NULL
, OPTION_MIPS2
},
5241 #define OPTION_MIPS3 (OPTION_MD_BASE + 3)
5242 {"mips3", no_argument
, NULL
, OPTION_MIPS3
},
5243 #define OPTION_MIPS4 (OPTION_MD_BASE + 4)
5244 {"mips4", no_argument
, NULL
, OPTION_MIPS4
},
5245 #define OPTION_MCPU (OPTION_MD_BASE + 5)
5246 {"mcpu", required_argument
, NULL
, OPTION_MCPU
},
5247 #define OPTION_MEMBEDDED_PIC (OPTION_MD_BASE + 6)
5248 {"membedded-pic", no_argument
, NULL
, OPTION_MEMBEDDED_PIC
},
5249 #define OPTION_TRAP (OPTION_MD_BASE + 9)
5250 {"trap", no_argument
, NULL
, OPTION_TRAP
},
5251 {"no-break", no_argument
, NULL
, OPTION_TRAP
},
5252 #define OPTION_BREAK (OPTION_MD_BASE + 10)
5253 {"break", no_argument
, NULL
, OPTION_BREAK
},
5254 {"no-trap", no_argument
, NULL
, OPTION_BREAK
},
5255 #define OPTION_EB (OPTION_MD_BASE + 11)
5256 {"EB", no_argument
, NULL
, OPTION_EB
},
5257 #define OPTION_EL (OPTION_MD_BASE + 12)
5258 {"EL", no_argument
, NULL
, OPTION_EL
},
5259 #define OPTION_M4650 (OPTION_MD_BASE + 13)
5260 {"m4650", no_argument
, NULL
, OPTION_M4650
},
5261 #define OPTION_NO_M4650 (OPTION_MD_BASE + 14)
5262 {"no-m4650", no_argument
, NULL
, OPTION_NO_M4650
},
5265 #define OPTION_CALL_SHARED (OPTION_MD_BASE + 7)
5266 {"KPIC", no_argument
, NULL
, OPTION_CALL_SHARED
},
5267 {"call_shared", no_argument
, NULL
, OPTION_CALL_SHARED
},
5268 #define OPTION_NON_SHARED (OPTION_MD_BASE + 8)
5269 {"non_shared", no_argument
, NULL
, OPTION_NON_SHARED
},
5272 {NULL
, no_argument
, NULL
, 0}
5274 size_t md_longopts_size
= sizeof(md_longopts
);
5277 md_parse_option (c
, arg
)
5292 byte_order
= BIG_ENDIAN
;
5294 mips_target_format
= "a.out-mips-big";
5297 mips_target_format
= "ecoff-bigmips";
5300 mips_target_format
= "elf32-bigmips";
5305 byte_order
= LITTLE_ENDIAN
;
5307 mips_target_format
= "a.out-mips-little";
5310 mips_target_format
= "ecoff-littlemips";
5313 mips_target_format
= "elf32-littlemips";
5318 if (arg
&& arg
[1] == '0')
5325 if (arg
== NULL
|| arg
[1] == '2')
5357 /* Identify the processor type */
5359 if (strcmp (p
, "default") == 0
5360 || strcmp (p
, "DEFAULT") == 0)
5364 if (*p
== 'r' || *p
== 'R')
5371 if (strcmp (p
, "10000") == 0
5372 || strcmp (p
, "10k") == 0
5373 || strcmp (p
, "10K") == 0)
5378 if (strcmp (p
, "2000") == 0
5379 || strcmp (p
, "2k") == 0
5380 || strcmp (p
, "2K") == 0)
5385 if (strcmp (p
, "3000") == 0
5386 || strcmp (p
, "3k") == 0
5387 || strcmp (p
, "3K") == 0)
5392 if (strcmp (p
, "4000") == 0
5393 || strcmp (p
, "4k") == 0
5394 || strcmp (p
, "4K") == 0)
5396 else if (strcmp (p
, "4400") == 0)
5398 else if (strcmp (p
, "4600") == 0)
5400 else if (strcmp (p
, "4650") == 0)
5409 if (strcmp (p
, "6000") == 0
5410 || strcmp (p
, "6k") == 0
5411 || strcmp (p
, "6K") == 0)
5416 if (strcmp (p
, "8000") == 0
5417 || strcmp (p
, "8k") == 0
5418 || strcmp (p
, "8K") == 0)
5423 if (strcmp (p
, "orion") == 0)
5430 as_bad ("invalid architecture -mcpu=%s", arg
);
5441 case OPTION_NO_M4650
:
5445 case OPTION_MEMBEDDED_PIC
:
5446 mips_pic
= EMBEDDED_PIC
;
5450 as_bad ("-G may not be used with embedded PIC code");
5453 g_switch_value
= 0x7fffffff;
5458 /* When generating ELF code, we permit -KPIC and -call_shared to
5459 select SVR4_PIC, and -non_shared to select no PIC. This is
5460 intended to be compatible with Irix 5. */
5461 case OPTION_CALL_SHARED
:
5462 mips_pic
= SVR4_PIC
;
5463 if (g_switch_seen
&& g_switch_value
!= 0)
5465 as_bad ("-G may not be used with SVR4 PIC code");
5471 case OPTION_NON_SHARED
:
5474 #endif /* OBJ_ELF */
5478 if (mips_pic
== SVR4_PIC
|| mips_pic
== EMBEDDED_PIC
)
5480 as_bad ("-G may not be used with SVR4 or embedded PIC code");
5484 g_switch_value
= atoi (arg
);
5497 md_show_usage (stream
)
5502 -membedded-pic generate embedded position independent code\n\
5503 -EB generate big endian output\n\
5504 -EL generate little endian output\n\
5505 -g, -g2 do not remove uneeded NOPs or swap branches\n\
5506 -G NUM allow referencing objects up to NUM bytes\n\
5507 implicitly with the gp register [default 8]\n");
5509 -mips1, -mcpu=r{2,3}000 generate code for r2000 and r3000\n\
5510 -mips2, -mcpu=r6000 generate code for r6000\n\
5511 -mips3, -mcpu=r4000 generate code for r4000\n\
5512 -mips4, -mcpu=r8000 generate code for r8000\n\
5513 -m4650 permit -m4650 instructions\n\
5514 -no-m4650 do not permit -m4650 instructions\n\
5515 -O0 remove unneeded NOPs, do not swap branches\n\
5516 -O remove unneeded NOPs and swap branches\n\
5517 --trap, --no-break trap exception on div by 0 and mult overflow\n\
5518 --break, --no-trap break exception on div by 0 and mult overflow\n");
5521 -KPIC, -call_shared generate SVR4 position independent code\n\
5522 -non_shared do not generate position independent code\n");
5527 md_pcrel_from (fixP
)
5531 if (fixP
->fx_addsy
!= (symbolS
*) NULL
5532 && ! S_IS_DEFINED (fixP
->fx_addsy
))
5534 /* This makes a branch to an undefined symbol be a branch to the
5535 current location. */
5540 /* return the address of the delay slot */
5541 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
5544 /* This is called by emit_expr via TC_CONS_FIX_NEW when creating a
5545 reloc for a cons. We could use the definition there, except that
5546 we want to handle 64 bit relocs specially. */
5549 cons_fix_new_mips (frag
, where
, nbytes
, exp
)
5552 unsigned int nbytes
;
5555 /* If we are assembling in 32 bit mode, turn an 8 byte reloc into a
5557 FIXME: There is no way to select anything but 32 bit mode right
5561 if (byte_order
== BIG_ENDIAN
)
5566 if (nbytes
!= 2 && nbytes
!= 4)
5567 as_bad ("Unsupported reloc size %d", nbytes
);
5569 fix_new_exp (frag_now
, where
, (int) nbytes
, exp
, 0,
5570 nbytes
== 2 ? BFD_RELOC_16
: BFD_RELOC_32
);
5573 /* When generating embedded PIC code we need to use a special
5574 relocation to represent the difference of two symbols in the .text
5575 section (switch tables use a difference of this sort). See
5576 include/coff/mips.h for details. This macro checks whether this
5577 fixup requires the special reloc. */
5578 #define SWITCH_TABLE(fixp) \
5579 ((fixp)->fx_r_type == BFD_RELOC_32 \
5580 && (fixp)->fx_addsy != NULL \
5581 && (fixp)->fx_subsy != NULL \
5582 && S_GET_SEGMENT ((fixp)->fx_addsy) == text_section \
5583 && S_GET_SEGMENT ((fixp)->fx_subsy) == text_section)
5585 /* When generating embedded PIC code we must keep all PC relative
5586 relocations, in case the linker has to relax a call. We also need
5587 to keep relocations for switch table entries. */
5591 mips_force_relocation (fixp
)
5594 return (mips_pic
== EMBEDDED_PIC
5596 || SWITCH_TABLE (fixp
)
5597 || fixp
->fx_r_type
== BFD_RELOC_PCREL_HI16_S
5598 || fixp
->fx_r_type
== BFD_RELOC_PCREL_LO16
));
5601 /* Apply a fixup to the object file. */
5604 md_apply_fix (fixP
, valueP
)
5611 assert (fixP
->fx_size
== 4 || fixP
->fx_r_type
== BFD_RELOC_16
);
5614 fixP
->fx_addnumber
= value
; /* Remember value for tc_gen_reloc */
5616 if (fixP
->fx_addsy
== NULL
&& ! fixP
->fx_pcrel
)
5619 switch (fixP
->fx_r_type
)
5621 case BFD_RELOC_MIPS_JMP
:
5622 case BFD_RELOC_HI16
:
5623 case BFD_RELOC_HI16_S
:
5624 case BFD_RELOC_MIPS_GPREL
:
5625 case BFD_RELOC_MIPS_LITERAL
:
5626 case BFD_RELOC_MIPS_CALL16
:
5627 case BFD_RELOC_MIPS_GOT16
:
5628 case BFD_RELOC_MIPS_GPREL32
:
5630 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
5631 "Invalid PC relative reloc");
5632 /* Nothing needed to do. The value comes from the reloc entry */
5635 case BFD_RELOC_PCREL_HI16_S
:
5636 /* The addend for this is tricky if it is internal, so we just
5637 do everything here rather than in bfd_perform_relocation. */
5638 if ((fixP
->fx_addsy
->bsym
->flags
& BSF_SECTION_SYM
) == 0)
5640 /* For an external symbol adjust by the address to make it
5641 pcrel_offset. We use the address of the RELLO reloc
5642 which follows this one. */
5643 value
+= (fixP
->fx_next
->fx_frag
->fr_address
5644 + fixP
->fx_next
->fx_where
);
5649 buf
= (unsigned char *) fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
5650 if (byte_order
== BIG_ENDIAN
)
5652 md_number_to_chars (buf
, value
, 2);
5655 case BFD_RELOC_PCREL_LO16
:
5656 /* The addend for this is tricky if it is internal, so we just
5657 do everything here rather than in bfd_perform_relocation. */
5658 if ((fixP
->fx_addsy
->bsym
->flags
& BSF_SECTION_SYM
) == 0)
5659 value
+= fixP
->fx_frag
->fr_address
+ fixP
->fx_where
;
5660 buf
= (unsigned char *) fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
5661 if (byte_order
== BIG_ENDIAN
)
5663 md_number_to_chars (buf
, value
, 2);
5667 /* If we are deleting this reloc entry, we must fill in the
5668 value now. This can happen if we have a .word which is not
5669 resolved when it appears but is later defined. We also need
5670 to fill in the value if this is an embedded PIC switch table
5673 || (mips_pic
== EMBEDDED_PIC
&& SWITCH_TABLE (fixP
)))
5674 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
,
5679 /* If we are deleting this reloc entry, we must fill in the
5681 assert (fixP
->fx_size
== 2);
5683 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
,
5687 case BFD_RELOC_LO16
:
5688 /* When handling an embedded PIC switch statement, we can wind
5689 up deleting a LO16 reloc. See the 'o' case in mips_ip. */
5692 if (value
< -0x8000 || value
> 0x7fff)
5693 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
5694 "relocation overflow");
5695 buf
= (unsigned char *) fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
5696 if (byte_order
== BIG_ENDIAN
)
5698 md_number_to_chars (buf
, value
, 2);
5702 case BFD_RELOC_16_PCREL_S2
:
5704 * We need to save the bits in the instruction since fixup_segment()
5705 * might be deleting the relocation entry (i.e., a branch within
5706 * the current segment).
5709 as_warn_where (fixP
->fx_file
, fixP
->fx_line
,
5710 "Branch to odd address (%lx)", value
);
5713 /* update old instruction data */
5714 buf
= (unsigned char *) (fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
);
5718 insn
= (buf
[3] << 24) | (buf
[2] << 16) | (buf
[1] << 8) | buf
[0];
5722 insn
= (buf
[0] << 24) | (buf
[1] << 16) | (buf
[2] << 8) | buf
[3];
5730 if (value
>= -0x8000 && value
< 0x8000)
5731 insn
|= value
& 0xffff;
5734 /* The branch offset is too large. If this is an
5735 unconditional branch, and we are not generating PIC code,
5736 we can convert it to an absolute jump instruction. */
5737 if (mips_pic
== NO_PIC
5739 && fixP
->fx_frag
->fr_address
>= text_section
->vma
5740 && (fixP
->fx_frag
->fr_address
5741 < text_section
->vma
+ text_section
->_raw_size
)
5742 && ((insn
& 0xffff0000) == 0x10000000 /* beq $0,$0 */
5743 || (insn
& 0xffff0000) == 0x04010000 /* bgez $0 */
5744 || (insn
& 0xffff0000) == 0x04110000)) /* bgezal $0 */
5746 if ((insn
& 0xffff0000) == 0x04110000) /* bgezal $0 */
5747 insn
= 0x0c000000; /* jal */
5749 insn
= 0x08000000; /* j */
5750 fixP
->fx_r_type
= BFD_RELOC_MIPS_JMP
;
5752 fixP
->fx_addsy
= section_symbol (text_section
);
5753 fixP
->fx_addnumber
= (value
<< 2) + md_pcrel_from (fixP
);
5757 /* FIXME. It would be possible in principle to handle
5758 conditional branches which overflow. They could be
5759 transformed into a branch around a jump. This would
5760 require setting up variant frags for each different
5761 branch type. The native MIPS assembler attempts to
5762 handle these cases, but it appears to do it
5764 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
5765 "Relocation overflow");
5769 md_number_to_chars ((char *) buf
, (valueT
) insn
, 4);
5784 const struct mips_opcode
*p
;
5785 int treg
, sreg
, dreg
, shamt
;
5790 for (i
= 0; i
< NUMOPCODES
; ++i
)
5792 p
= &mips_opcodes
[i
];
5793 if (((oc
& p
->mask
) == p
->match
) && (p
->pinfo
!= INSN_MACRO
))
5795 printf ("%08lx %s\t", oc
, p
->name
);
5796 treg
= (oc
>> 16) & 0x1f;
5797 sreg
= (oc
>> 21) & 0x1f;
5798 dreg
= (oc
>> 11) & 0x1f;
5799 shamt
= (oc
>> 6) & 0x1f;
5801 for (args
= p
->args
;; ++args
)
5812 printf ("%c", *args
);
5816 assert (treg
== sreg
);
5817 printf ("$%d,$%d", treg
, sreg
);
5822 printf ("$%d", dreg
);
5827 printf ("$%d", treg
);
5831 printf ("0x%x", treg
);
5836 printf ("$%d", sreg
);
5840 printf ("0x%08lx", oc
& 0x1ffffff);
5852 printf ("$%d", shamt
);
5863 printf ("%08lx UNDEFINED\n", oc
);
5874 name
= input_line_pointer
;
5875 c
= get_symbol_end ();
5876 p
= (symbolS
*) symbol_find_or_make (name
);
5877 *input_line_pointer
= c
;
5881 /* Align the current frag to a given power of two. The MIPS assembler
5882 also automatically adjusts any preceding label. */
5885 mips_align (to
, fill
, label
)
5890 mips_emit_delays ();
5891 frag_align (to
, fill
);
5892 record_alignment (now_seg
, to
);
5895 assert (S_GET_SEGMENT (label
) == now_seg
);
5896 label
->sy_frag
= frag_now
;
5897 S_SET_VALUE (label
, (valueT
) frag_now_fix ());
5901 /* Align to a given power of two. .align 0 turns off the automatic
5902 alignment used by the data creating pseudo-ops. */
5909 register long temp_fill
;
5910 long max_alignment
= 15;
5914 o Note that the assembler pulls down any immediately preceeding label
5915 to the aligned address.
5916 o It's not documented but auto alignment is reinstated by
5917 a .align pseudo instruction.
5918 o Note also that after auto alignment is turned off the mips assembler
5919 issues an error on attempt to assemble an improperly aligned data item.
5924 temp
= get_absolute_expression ();
5925 if (temp
> max_alignment
)
5926 as_bad ("Alignment too large: %d. assumed.", temp
= max_alignment
);
5929 as_warn ("Alignment negative: 0 assumed.");
5932 if (*input_line_pointer
== ',')
5934 input_line_pointer
++;
5935 temp_fill
= get_absolute_expression ();
5942 mips_align (temp
, (int) temp_fill
, insn_label
);
5949 demand_empty_rest_of_line ();
5952 /* Handle .ascii and .asciiz. This just calls stringer and forgets
5953 that there was a previous instruction. */
5956 s_stringer (append_zero
)
5959 mips_emit_delays ();
5961 stringer (append_zero
);
5972 /* When generating embedded PIC code, we only use the .text, .lit8,
5973 .sdata and .sbss sections. We change the .data and .rdata
5974 pseudo-ops to use .sdata. */
5975 if (mips_pic
== EMBEDDED_PIC
5976 && (sec
== 'd' || sec
== 'r'))
5979 mips_emit_delays ();
5989 subseg_set (bss_section
, (subsegT
) get_absolute_expression ());
5990 demand_empty_rest_of_line ();
5995 seg
= subseg_new (RDATA_SECTION_NAME
,
5996 (subsegT
) get_absolute_expression ());
5998 bfd_set_section_flags (stdoutput
, seg
,
6004 bfd_set_section_alignment (stdoutput
, seg
, 4);
6006 demand_empty_rest_of_line ();
6007 #else /* ! defined (GPOPT) */
6008 as_bad ("No read only data section in this object file format");
6009 demand_empty_rest_of_line ();
6011 #endif /* ! defined (GPOPT) */
6016 seg
= subseg_new (".sdata", (subsegT
) get_absolute_expression ());
6018 bfd_set_section_flags (stdoutput
, seg
,
6019 SEC_ALLOC
| SEC_LOAD
| SEC_RELOC
| SEC_DATA
);
6020 bfd_set_section_alignment (stdoutput
, seg
, 4);
6022 demand_empty_rest_of_line ();
6024 #else /* ! defined (GPOPT) */
6025 as_bad ("Global pointers not supported; recompile -G 0");
6026 demand_empty_rest_of_line ();
6028 #endif /* ! defined (GPOPT) */
6036 /* Handle the ELF .section pseudo-op. This is a wrapper around
6043 mips_emit_delays ();
6044 obj_elf_section (x
);
6048 #endif /* OBJ_ELF */
6057 mips_emit_delays ();
6058 if (log_size
> 0 && auto_align
)
6059 mips_align (log_size
, 0, label
);
6061 cons (1 << log_size
);
6068 as_fatal ("Encountered `.err', aborting assembly");
6078 symbolP
= get_symbol ();
6079 if (*input_line_pointer
== ',')
6080 input_line_pointer
++;
6081 size
= get_absolute_expression ();
6082 S_SET_EXTERNAL (symbolP
);
6084 #ifdef ECOFF_DEBUGGING
6085 symbolP
->ecoff_extern_size
= size
;
6097 mips_emit_delays ();
6101 mips_align (3, 0, label
);
6103 mips_align (2, 0, label
);
6110 /* Handle .globl. We need to override it because on Irix 5 you are
6113 where foo is an undefined symbol, to mean that foo should be
6114 considered to be the address of a function. */
6124 name
= input_line_pointer
;
6125 c
= get_symbol_end ();
6126 symbolP
= symbol_find_or_make (name
);
6127 *input_line_pointer
= c
;
6129 if (! is_end_of_line
[(unsigned char) *input_line_pointer
])
6134 secname
= input_line_pointer
;
6135 c
= get_symbol_end ();
6136 sec
= bfd_get_section_by_name (stdoutput
, secname
);
6138 as_bad ("%s: no such section", secname
);
6139 *input_line_pointer
= c
;
6141 if (sec
!= NULL
&& (sec
->flags
& SEC_CODE
) != 0)
6142 symbolP
->bsym
->flags
|= BSF_FUNCTION
;
6145 S_SET_EXTERNAL (symbolP
);
6146 demand_empty_rest_of_line ();
6156 opt
= input_line_pointer
;
6157 c
= get_symbol_end ();
6161 /* FIXME: What does this mean? */
6163 else if (strncmp (opt
, "pic", 3) == 0)
6171 mips_pic
= SVR4_PIC
;
6173 as_bad (".option pic%d not supported", i
);
6176 if (mips_pic
== SVR4_PIC
)
6178 if (g_switch_seen
&& g_switch_value
!= 0)
6179 as_warn ("-G may not be used with SVR4 PIC code");
6181 bfd_set_gp_size (stdoutput
, 0);
6186 as_warn ("Unrecognized option \"%s\"", opt
);
6188 *input_line_pointer
= c
;
6189 demand_empty_rest_of_line ();
6196 char *name
= input_line_pointer
, ch
;
6198 while (!is_end_of_line
[(unsigned char) *input_line_pointer
])
6199 input_line_pointer
++;
6200 ch
= *input_line_pointer
;
6201 *input_line_pointer
= '\0';
6203 if (strcmp (name
, "reorder") == 0)
6207 prev_insn_unreordered
= 1;
6208 prev_prev_insn_unreordered
= 1;
6212 else if (strcmp (name
, "noreorder") == 0)
6214 mips_emit_delays ();
6216 mips_any_noreorder
= 1;
6218 else if (strcmp (name
, "at") == 0)
6222 else if (strcmp (name
, "noat") == 0)
6226 else if (strcmp (name
, "macro") == 0)
6228 mips_warn_about_macros
= 0;
6230 else if (strcmp (name
, "nomacro") == 0)
6232 if (mips_noreorder
== 0)
6233 as_bad ("`noreorder' must be set before `nomacro'");
6234 mips_warn_about_macros
= 1;
6236 else if (strcmp (name
, "move") == 0 || strcmp (name
, "novolatile") == 0)
6240 else if (strcmp (name
, "nomove") == 0 || strcmp (name
, "volatile") == 0)
6244 else if (strcmp (name
, "bopt") == 0)
6248 else if (strcmp (name
, "nobopt") == 0)
6252 else if (strncmp (name
, "mips", 4) == 0)
6256 /* Permit the user to change the ISA on the fly. Needless to
6257 say, misuse can cause serious problems. */
6258 isa
= atoi (name
+ 4);
6260 mips_isa
= file_mips_isa
;
6261 else if (isa
< 1 || isa
> 4)
6262 as_bad ("unknown ISA level");
6268 as_warn ("Tried to set unrecognized symbol: %s\n", name
);
6270 *input_line_pointer
= ch
;
6271 demand_empty_rest_of_line ();
6274 /* The same as the usual .space directive, except that we have to
6275 forget about any previous instruction. */
6278 s_mips_space (param
)
6281 mips_emit_delays ();
6286 /* Handle the .abicalls pseudo-op. I believe this is equivalent to
6287 .option pic2. It means to generate SVR4 PIC calls. */
6293 mips_pic
= SVR4_PIC
;
6295 if (g_switch_seen
&& g_switch_value
!= 0)
6296 as_warn ("-G may not be used with SVR4 PIC code");
6299 bfd_set_gp_size (stdoutput
, 0);
6300 demand_empty_rest_of_line ();
6303 /* Handle the .cpload pseudo-op. This is used when generating SVR4
6304 PIC code. It sets the $gp register for the function based on the
6305 function address, which is in the register named in the argument.
6306 This uses a relocation against _gp_disp, which is handled specially
6307 by the linker. The result is:
6308 lui $gp,%hi(_gp_disp)
6309 addiu $gp,$gp,%lo(_gp_disp)
6310 addu $gp,$gp,.cpload argument
6311 The .cpload argument is normally $25 == $t9. */
6320 /* If we are not generating SVR4 PIC code, .cpload is ignored. */
6321 if (mips_pic
!= SVR4_PIC
)
6327 /* .cpload should be a in .set noreorder section. */
6328 if (mips_noreorder
== 0)
6329 as_warn (".cpload not in noreorder section");
6332 ex
.X_add_symbol
= symbol_find_or_make ("_gp_disp");
6333 ex
.X_op_symbol
= NULL
;
6334 ex
.X_add_number
= 0;
6336 macro_build_lui ((char *) NULL
, &icnt
, &ex
, GP
);
6337 macro_build ((char *) NULL
, &icnt
, &ex
, "addiu", "t,r,j", GP
, GP
,
6338 (int) BFD_RELOC_LO16
);
6340 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "addu", "d,v,t",
6341 GP
, GP
, tc_get_register (0));
6343 demand_empty_rest_of_line ();
6346 /* Handle the .cprestore pseudo-op. This stores $gp into a given
6347 offset from $sp. The offset is remembered, and after making a PIC
6348 call $gp is restored from that location. */
6351 s_cprestore (ignore
)
6357 /* If we are not generating SVR4 PIC code, .cprestore is ignored. */
6358 if (mips_pic
!= SVR4_PIC
)
6364 mips_cprestore_offset
= get_absolute_expression ();
6366 ex
.X_op
= O_constant
;
6367 ex
.X_add_symbol
= NULL
;
6368 ex
.X_op_symbol
= NULL
;
6369 ex
.X_add_number
= mips_cprestore_offset
;
6371 macro_build ((char *) NULL
, &icnt
, &ex
,
6372 mips_isa
< 3 ? "sw" : "sd",
6373 "t,o(b)", GP
, (int) BFD_RELOC_LO16
, SP
);
6375 demand_empty_rest_of_line ();
6378 /* Handle the .gpword pseudo-op. This is used when generating PIC
6379 code. It generates a 32 bit GP relative reloc. */
6389 /* When not generating PIC code, this is treated as .word. */
6390 if (mips_pic
!= SVR4_PIC
)
6397 mips_emit_delays ();
6399 mips_align (2, 0, label
);
6404 if (ex
.X_op
!= O_symbol
|| ex
.X_add_number
!= 0)
6406 as_bad ("Unsupported use of .gpword");
6407 ignore_rest_of_line ();
6411 md_number_to_chars (p
, (valueT
) 0, 4);
6412 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 4, &ex
, 0,
6413 BFD_RELOC_MIPS_GPREL32
);
6415 demand_empty_rest_of_line ();
6418 /* Handle the .cpadd pseudo-op. This is used when dealing with switch
6419 tables in SVR4 PIC code. */
6428 /* This is ignored when not generating SVR4 PIC code. */
6429 if (mips_pic
!= SVR4_PIC
)
6435 /* Add $gp to the register named as an argument. */
6436 reg
= tc_get_register (0);
6437 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6438 mips_isa
< 3 ? "addu" : "daddu",
6439 "d,v,t", reg
, reg
, GP
);
6441 demand_empty_rest_of_line ();
6444 /* Parse a register string into a number. Called from the ECOFF code
6445 to parse .frame. The argument is non-zero if this is the frame
6446 register, so that we can record it in mips_frame_reg. */
6449 tc_get_register (frame
)
6455 if (*input_line_pointer
++ != '$')
6457 as_warn ("expected `$'");
6460 else if (isdigit ((unsigned char) *input_line_pointer
))
6462 reg
= get_absolute_expression ();
6463 if (reg
< 0 || reg
>= 32)
6465 as_warn ("Bad register number");
6471 if (strncmp (input_line_pointer
, "fp", 2) == 0)
6473 else if (strncmp (input_line_pointer
, "sp", 2) == 0)
6475 else if (strncmp (input_line_pointer
, "gp", 2) == 0)
6477 else if (strncmp (input_line_pointer
, "at", 2) == 0)
6481 as_warn ("Unrecognized register name");
6484 input_line_pointer
+= 2;
6487 mips_frame_reg
= reg
!= 0 ? reg
: SP
;
6492 md_section_align (seg
, addr
)
6496 int align
= bfd_get_section_alignment (stdoutput
, seg
);
6498 return ((addr
+ (1 << align
) - 1) & (-1 << align
));
6501 /* Estimate the size of a frag before relaxing. We are not really
6502 relaxing here, and the final size is encoded in the subtype
6505 /* Utility routine, called from above as well. If called while the
6506 input file is still being read, it's only an approximation. (For
6507 example, a symbol may later become defined which appeared to be
6508 undefined earlier.) */
6509 static int nopic_need_relax (sym
)
6517 const char *symname
;
6520 /* Find out whether this symbol can be referenced off the GP
6521 register. It can be if it is smaller than the -G size or if it
6522 is in the .sdata or .sbss section. Certain symbols can not be
6523 referenced off the GP, although it appears as though they can. */
6524 symname
= S_GET_NAME (sym
);
6525 if (symname
!= (const char *) NULL
6526 && (strcmp (symname
, "eprol") == 0
6527 || strcmp (symname
, "etext") == 0
6528 || strcmp (symname
, "_gp") == 0
6529 || strcmp (symname
, "edata") == 0
6530 || strcmp (symname
, "_fbss") == 0
6531 || strcmp (symname
, "_fdata") == 0
6532 || strcmp (symname
, "_ftext") == 0
6533 || strcmp (symname
, "end") == 0
6534 || strcmp (symname
, "_gp_disp") == 0))
6536 else if (! S_IS_DEFINED (sym
)
6537 && ((sym
->ecoff_extern_size
!= 0
6538 && sym
->ecoff_extern_size
<= g_switch_value
)
6539 || (S_GET_VALUE (sym
) != 0
6540 && S_GET_VALUE (sym
) <= g_switch_value
)))
6544 const char *segname
;
6546 segname
= segment_name (S_GET_SEGMENT (sym
));
6547 assert (strcmp (segname
, ".lit8") != 0
6548 && strcmp (segname
, ".lit4") != 0);
6549 change
= (strcmp (segname
, ".sdata") != 0
6550 && strcmp (segname
, ".sbss") != 0);
6554 #else /* ! defined (GPOPT) */
6555 /* We are not optimizing for the GP register. */
6557 #endif /* ! defined (GPOPT) */
6562 md_estimate_size_before_relax (fragp
, segtype
)
6568 if (mips_pic
== NO_PIC
)
6570 change
= nopic_need_relax (fragp
->fr_symbol
);
6572 else if (mips_pic
== SVR4_PIC
)
6574 asection
*symsec
= fragp
->fr_symbol
->bsym
->section
;
6576 /* This must duplicate the test in adjust_reloc_syms. */
6577 change
= (symsec
!= &bfd_und_section
6578 && symsec
!= &bfd_abs_section
6579 && ! bfd_is_com_section (symsec
));
6586 /* Record the offset to the first reloc in the fr_opcode field.
6587 This lets md_convert_frag and tc_gen_reloc know that the code
6588 must be expanded. */
6589 fragp
->fr_opcode
= (fragp
->fr_literal
6591 - RELAX_OLD (fragp
->fr_subtype
)
6592 + RELAX_RELOC1 (fragp
->fr_subtype
));
6593 /* FIXME: This really needs as_warn_where. */
6594 if (RELAX_WARN (fragp
->fr_subtype
))
6595 as_warn ("AT used after \".set noat\" or macro used after \".set nomacro\"");
6601 return RELAX_NEW (fragp
->fr_subtype
) - RELAX_OLD (fragp
->fr_subtype
);
6604 /* Translate internal representation of relocation info to BFD target
6608 tc_gen_reloc (section
, fixp
)
6612 static arelent
*retval
[4];
6615 reloc
= retval
[0] = (arelent
*) xmalloc (sizeof (arelent
));
6618 reloc
->sym_ptr_ptr
= &fixp
->fx_addsy
->bsym
;
6619 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
6621 if (mips_pic
== EMBEDDED_PIC
6622 && SWITCH_TABLE (fixp
))
6624 /* For a switch table entry we use a special reloc. The addend
6625 is actually the difference between the reloc address and the
6627 reloc
->addend
= reloc
->address
- S_GET_VALUE (fixp
->fx_subsy
);
6629 as_fatal ("Double check fx_r_type in tc-mips.c:tc_gen_reloc");
6631 fixp
->fx_r_type
= BFD_RELOC_GPREL32
;
6633 else if (fixp
->fx_r_type
== BFD_RELOC_PCREL_LO16
)
6635 /* We use a special addend for an internal RELLO reloc. */
6636 if (fixp
->fx_addsy
->bsym
->flags
& BSF_SECTION_SYM
)
6637 reloc
->addend
= reloc
->address
- S_GET_VALUE (fixp
->fx_subsy
);
6639 reloc
->addend
= fixp
->fx_addnumber
+ reloc
->address
;
6641 else if (fixp
->fx_r_type
== BFD_RELOC_PCREL_HI16_S
)
6643 assert (fixp
->fx_next
!= NULL
6644 && fixp
->fx_next
->fx_r_type
== BFD_RELOC_PCREL_LO16
);
6645 /* We use a special addend for an internal RELHI reloc. The
6646 reloc is relative to the RELLO; adjust the addend
6648 if (fixp
->fx_addsy
->bsym
->flags
& BSF_SECTION_SYM
)
6649 reloc
->addend
= (fixp
->fx_next
->fx_frag
->fr_address
6650 + fixp
->fx_next
->fx_where
6651 - S_GET_VALUE (fixp
->fx_subsy
));
6653 reloc
->addend
= (fixp
->fx_addnumber
6654 + fixp
->fx_next
->fx_frag
->fr_address
6655 + fixp
->fx_next
->fx_where
);
6657 else if (fixp
->fx_pcrel
== 0)
6658 reloc
->addend
= fixp
->fx_addnumber
;
6662 /* A gruesome hack which is a result of the gruesome gas reloc
6664 reloc
->addend
= reloc
->address
;
6666 reloc
->addend
= -reloc
->address
;
6670 /* If this is a variant frag, we may need to adjust the existing
6671 reloc and generate a new one. */
6672 if (fixp
->fx_frag
->fr_opcode
!= NULL
6673 && (fixp
->fx_r_type
== BFD_RELOC_MIPS_GPREL
6674 || fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT16
6675 || fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL16
))
6679 /* If this is not the last reloc in this frag, then we have two
6680 GPREL relocs, both of which are being replaced. Let the
6681 second one handle all of them. */
6682 if (fixp
->fx_next
!= NULL
6683 && fixp
->fx_frag
== fixp
->fx_next
->fx_frag
)
6685 assert (fixp
->fx_r_type
== BFD_RELOC_MIPS_GPREL
6686 && fixp
->fx_next
->fx_r_type
== BFD_RELOC_MIPS_GPREL
);
6691 fixp
->fx_where
= fixp
->fx_frag
->fr_opcode
- fixp
->fx_frag
->fr_literal
;
6692 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
6693 reloc2
= retval
[1] = (arelent
*) xmalloc (sizeof (arelent
));
6695 reloc2
->sym_ptr_ptr
= &fixp
->fx_addsy
->bsym
;
6696 reloc2
->address
= (reloc
->address
6697 + (RELAX_RELOC2 (fixp
->fx_frag
->fr_subtype
)
6698 - RELAX_RELOC1 (fixp
->fx_frag
->fr_subtype
)));
6699 reloc2
->addend
= fixp
->fx_addnumber
;
6700 reloc2
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_LO16
);
6701 assert (reloc2
->howto
!= NULL
);
6703 if (RELAX_RELOC3 (fixp
->fx_frag
->fr_subtype
))
6707 reloc3
= retval
[2] = (arelent
*) xmalloc (sizeof (arelent
));
6710 reloc3
->address
+= 4;
6713 if (mips_pic
== NO_PIC
)
6715 assert (fixp
->fx_r_type
== BFD_RELOC_MIPS_GPREL
);
6716 fixp
->fx_r_type
= BFD_RELOC_HI16_S
;
6718 else if (mips_pic
== SVR4_PIC
)
6720 if (fixp
->fx_r_type
!= BFD_RELOC_MIPS_GOT16
)
6722 assert (fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL16
);
6723 fixp
->fx_r_type
= BFD_RELOC_MIPS_GOT16
;
6730 /* To support a PC relative reloc when generating embedded PIC code
6731 for ECOFF, we use a Cygnus extension. We check for that here to
6732 make sure that we don't let such a reloc escape normally. */
6734 if (fixp
->fx_r_type
== BFD_RELOC_16_PCREL_S2
6735 && mips_pic
!= EMBEDDED_PIC
)
6736 reloc
->howto
= NULL
;
6739 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, fixp
->fx_r_type
);
6741 if (reloc
->howto
== NULL
)
6743 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
6744 "Can not represent relocation in this object file format");
6751 /* Convert a machine dependent frag. */
6754 md_convert_frag (abfd
, asec
, fragp
)
6762 if (fragp
->fr_opcode
== NULL
)
6765 old
= RELAX_OLD (fragp
->fr_subtype
);
6766 new = RELAX_NEW (fragp
->fr_subtype
);
6767 fixptr
= fragp
->fr_literal
+ fragp
->fr_fix
;
6770 memcpy (fixptr
- old
, fixptr
, new);
6772 fragp
->fr_fix
+= new - old
;
6775 /* This function is called whenever a label is defined. It is used
6776 when handling branch delays; if a branch has a label, we assume we
6780 mips_define_label (sym
)
6788 /* Some special processing for a MIPS ELF file. */
6791 mips_elf_final_processing ()
6795 /* Write out the .reginfo section. */
6796 s
.ri_gprmask
= mips_gprmask
;
6797 s
.ri_cprmask
[0] = mips_cprmask
[0];
6798 s
.ri_cprmask
[1] = mips_cprmask
[1];
6799 s
.ri_cprmask
[2] = mips_cprmask
[2];
6800 s
.ri_cprmask
[3] = mips_cprmask
[3];
6801 /* The gp_value field is set by the MIPS ELF backend. */
6803 bfd_mips_elf32_swap_reginfo_out (stdoutput
, &s
,
6804 ((Elf32_External_RegInfo
*)
6805 mips_regmask_frag
));
6807 /* Set the MIPS ELF flag bits. FIXME: There should probably be some
6808 sort of BFD interface for this. */
6809 if (mips_any_noreorder
)
6810 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_NOREORDER
;
6811 if (mips_pic
!= NO_PIC
)
6812 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_PIC
;
6815 #endif /* OBJ_ELF */
6817 #ifndef ECOFF_DEBUGGING
6819 /* These functions should really be defined by the object file format,
6820 since they are related to debugging information. However, this
6821 code has to work for the a.out format, which does not define them,
6822 so we provide simple versions here. These don't actually generate
6823 any debugging information, but they do simple checking and someday
6824 somebody may make them useful. */
6828 struct loc
*loc_next
;
6829 unsigned long loc_fileno
;
6830 unsigned long loc_lineno
;
6831 unsigned long loc_offset
;
6832 unsigned short loc_delta
;
6833 unsigned short loc_count
;
6842 struct proc
*proc_next
;
6843 struct symbol
*proc_isym
;
6844 struct symbol
*proc_end
;
6845 unsigned long proc_reg_mask
;
6846 unsigned long proc_reg_offset
;
6847 unsigned long proc_fpreg_mask
;
6848 unsigned long proc_fpreg_offset
;
6849 unsigned long proc_frameoffset
;
6850 unsigned long proc_framereg
;
6851 unsigned long proc_pcreg
;
6853 struct file
*proc_file
;
6860 struct file
*file_next
;
6861 unsigned long file_fileno
;
6862 struct symbol
*file_symbol
;
6863 struct symbol
*file_end
;
6864 struct proc
*file_proc
;
6869 static struct obstack proc_frags
;
6870 static procS
*proc_lastP
;
6871 static procS
*proc_rootP
;
6872 static int numprocs
;
6877 obstack_begin (&proc_frags
, 0x2000);
6883 /* check for premature end, nesting errors, etc */
6884 if (proc_lastP
&& proc_lastP
->proc_end
== NULL
)
6885 as_warn ("missing `.end' at end of assembly");
6894 if (*input_line_pointer
== '-')
6896 ++input_line_pointer
;
6899 if (!isdigit (*input_line_pointer
))
6900 as_bad ("Expected simple number.");
6901 if (input_line_pointer
[0] == '0')
6903 if (input_line_pointer
[1] == 'x')
6905 input_line_pointer
+= 2;
6906 while (isxdigit (*input_line_pointer
))
6909 val
|= hex_value (*input_line_pointer
++);
6911 return negative
? -val
: val
;
6915 ++input_line_pointer
;
6916 while (isdigit (*input_line_pointer
))
6919 val
|= *input_line_pointer
++ - '0';
6921 return negative
? -val
: val
;
6924 if (!isdigit (*input_line_pointer
))
6926 printf (" *input_line_pointer == '%c' 0x%02x\n",
6927 *input_line_pointer
, *input_line_pointer
);
6928 as_warn ("Invalid number");
6931 while (isdigit (*input_line_pointer
))
6934 val
+= *input_line_pointer
++ - '0';
6936 return negative
? -val
: val
;
6939 /* The .file directive; just like the usual .file directive, but there
6940 is an initial number which is the ECOFF file index. */
6948 line
= get_number ();
6953 /* The .end directive. */
6961 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
6964 demand_empty_rest_of_line ();
6968 if (now_seg
!= text_section
)
6969 as_warn (".end not in text section");
6972 as_warn (".end and no .ent seen yet.");
6978 assert (S_GET_NAME (p
));
6979 if (strcmp (S_GET_NAME (p
), S_GET_NAME (proc_lastP
->proc_isym
)))
6980 as_warn (".end symbol does not match .ent symbol.");
6983 proc_lastP
->proc_end
= (symbolS
*) 1;
6986 /* The .aent and .ent directives. */
6996 symbolP
= get_symbol ();
6997 if (*input_line_pointer
== ',')
6998 input_line_pointer
++;
7000 if (isdigit (*input_line_pointer
) || *input_line_pointer
== '-')
7001 number
= get_number ();
7002 if (now_seg
!= text_section
)
7003 as_warn (".ent or .aent not in text section.");
7005 if (!aent
&& proc_lastP
&& proc_lastP
->proc_end
== NULL
)
7006 as_warn ("missing `.end'");
7010 procP
= (procS
*) obstack_alloc (&proc_frags
, sizeof (*procP
));
7011 procP
->proc_isym
= symbolP
;
7012 procP
->proc_reg_mask
= 0;
7013 procP
->proc_reg_offset
= 0;
7014 procP
->proc_fpreg_mask
= 0;
7015 procP
->proc_fpreg_offset
= 0;
7016 procP
->proc_frameoffset
= 0;
7017 procP
->proc_framereg
= 0;
7018 procP
->proc_pcreg
= 0;
7019 procP
->proc_end
= NULL
;
7020 procP
->proc_next
= NULL
;
7022 proc_lastP
->proc_next
= procP
;
7028 demand_empty_rest_of_line ();
7031 /* The .frame directive. */
7044 frame_reg
= tc_get_register (1);
7045 if (*input_line_pointer
== ',')
7046 input_line_pointer
++;
7047 frame_off
= get_absolute_expression ();
7048 if (*input_line_pointer
== ',')
7049 input_line_pointer
++;
7050 pcreg
= tc_get_register (0);
7053 assert (proc_rootP
);
7054 proc_rootP
->proc_framereg
= frame_reg
;
7055 proc_rootP
->proc_frameoffset
= frame_off
;
7056 proc_rootP
->proc_pcreg
= pcreg
;
7057 /* bob macho .frame */
7059 /* We don't have to write out a frame stab for unoptimized code. */
7060 if (!(frame_reg
== FP
&& frame_off
== 0))
7063 as_warn ("No .ent for .frame to use.");
7064 (void) sprintf (str
, "R%d;%d", frame_reg
, frame_off
);
7065 symP
= symbol_new (str
, N_VFP
, 0, frag_now
);
7066 S_SET_TYPE (symP
, N_RMASK
);
7067 S_SET_OTHER (symP
, 0);
7068 S_SET_DESC (symP
, 0);
7069 symP
->sy_forward
= proc_lastP
->proc_isym
;
7070 /* bob perhaps I should have used pseudo set */
7072 demand_empty_rest_of_line ();
7076 /* The .fmask and .mask directives. */
7083 char str
[100], *strP
;
7089 mask
= get_number ();
7090 if (*input_line_pointer
== ',')
7091 input_line_pointer
++;
7092 off
= get_absolute_expression ();
7094 /* bob only for coff */
7095 assert (proc_rootP
);
7096 if (reg_type
== 'F')
7098 proc_rootP
->proc_fpreg_mask
= mask
;
7099 proc_rootP
->proc_fpreg_offset
= off
;
7103 proc_rootP
->proc_reg_mask
= mask
;
7104 proc_rootP
->proc_reg_offset
= off
;
7107 /* bob macho .mask + .fmask */
7109 /* We don't have to write out a mask stab if no saved regs. */
7113 as_warn ("No .ent for .mask to use.");
7115 for (i
= 0; i
< 32; i
++)
7119 sprintf (strP
, "%c%d,", reg_type
, i
);
7120 strP
+= strlen (strP
);
7124 sprintf (strP
, ";%d,", off
);
7125 symP
= symbol_new (str
, N_RMASK
, 0, frag_now
);
7126 S_SET_TYPE (symP
, N_RMASK
);
7127 S_SET_OTHER (symP
, 0);
7128 S_SET_DESC (symP
, 0);
7129 symP
->sy_forward
= proc_lastP
->proc_isym
;
7130 /* bob perhaps I should have used pseudo set */
7135 /* The .loc directive. */
7146 assert (now_seg
== text_section
);
7148 lineno
= get_number ();
7149 addroff
= frag_now_fix ();
7151 symbolP
= symbol_new ("", N_SLINE
, addroff
, frag_now
);
7152 S_SET_TYPE (symbolP
, N_SLINE
);
7153 S_SET_OTHER (symbolP
, 0);
7154 S_SET_DESC (symbolP
, lineno
);
7155 symbolP
->sy_segment
= now_seg
;
7159 #endif /* ! defined (ECOFF_DEBUGGING) */