1 /* tc-mips.c -- assemble code for a MIPS chip.
2 Copyright (C) 1993 Free Software Foundation, Inc.
3 Contributed by the OSF and Ralph Campbell.
4 Written by Keith Knowles and Ralph Campbell, working independently.
5 Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus
8 This file is part of GAS.
10 GAS is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 2, or (at your option)
15 GAS is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with GAS; see the file COPYING. If not, write to
22 the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */
41 #endif /* NO_VARARGS */
42 #endif /* NO_STDARG */
44 #include "opcode/mips.h"
49 static char *mips_regmask_frag
;
53 #define PIC_CALL_REG 25
59 /* Decide whether to do GP reference optimizations based on the object
69 /* The default target format to use. */
71 #ifdef TARGET_BYTES_BIG_ENDIAN
72 #define DEFAULT_TARGET_FORMAT "a.out-mips-big"
74 #define DEFAULT_TARGET_FORMAT "a.out-mips-little"
78 #ifdef TARGET_BYTES_BIG_ENDIAN
79 #define DEFAULT_TARGET_FORMAT "ecoff-bigmips"
81 #define DEFAULT_TARGET_FORMAT "ecoff-littlemips"
83 #endif /* OBJ_ECOFF */
85 #ifdef TARGET_BYTES_BIG_ENDIAN
86 #define DEFAULT_TARGET_FORMAT "elf32-bigmips"
88 #define DEFAULT_TARGET_FORMAT "elf32-littlemips"
92 const char *mips_target_format
= DEFAULT_TARGET_FORMAT
;
94 /* The name of the readonly data section. */
96 #define RDATA_SECTION_NAME ".data"
99 #define RDATA_SECTION_NAME ".rdata"
102 #define RDATA_SECTION_NAME ".rodata"
105 /* These variables are filled in with the masks of registers used.
106 The object format code reads them and puts them in the appropriate
108 unsigned long mips_gprmask
;
109 unsigned long mips_cprmask
[4];
111 /* MIPS ISA (Instruction Set Architecture) level (may be changed
112 temporarily using .set mipsN). */
113 static int mips_isa
= -1;
115 /* MIPS ISA we are using for this output file. */
116 static int file_mips_isa
;
118 /* The CPU type as a number: 2000, 3000, 4000, 4400, etc. */
119 static int mips_cpu
= -1;
121 /* MIPS PIC level. */
125 /* Do not generate PIC code. */
128 /* Generate PIC code as in Irix 4. This is not implemented, and I'm
129 not sure what it is supposed to do. */
132 /* Generate PIC code as in the SVR4 MIPS ABI. */
135 /* Generate PIC code without using a global offset table: the data
136 segment has a maximum size of 64K, all data references are off
137 the $gp register, and all text references are PC relative. This
138 is used on some embedded systems. */
142 static enum mips_pic_level mips_pic
;
144 /* 1 if trap instructions should used for overflow rather than break
146 static int mips_trap
;
148 static int mips_warn_about_macros
;
149 static int mips_noreorder
;
150 static int mips_any_noreorder
;
151 static int mips_nomove
;
152 static int mips_noat
;
153 static int mips_nobopt
;
156 /* The size of the small data section. */
157 static int g_switch_value
= 8;
158 /* Whether the -G option was used. */
159 static int g_switch_seen
= 0;
165 /* handle of the OPCODE hash table */
166 static struct hash_control
*op_hash
= NULL
;
168 /* This array holds the chars that always start a comment. If the
169 pre-processor is disabled, these aren't very useful */
170 const char comment_chars
[] = "#";
172 /* This array holds the chars that only start a comment at the beginning of
173 a line. If the line seems to have the form '# 123 filename'
174 .line and .file directives will appear in the pre-processed output */
175 /* Note that input_file.c hand checks for '#' at the beginning of the
176 first line of the input file. This is because the compiler outputs
177 #NO_APP at the beginning of its output. */
178 /* Also note that C style comments are always supported. */
179 const char line_comment_chars
[] = "#";
181 /* This array holds machine specific line separator characters. */
182 const char line_separator_chars
[] = "";
184 /* Chars that can be used to separate mant from exp in floating point nums */
185 const char EXP_CHARS
[] = "eE";
187 /* Chars that mean this number is a floating point constant */
190 const char FLT_CHARS
[] = "rRsSfFdDxXpP";
192 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
193 changed in read.c . Ideally it shouldn't have to know about it at all,
194 but nothing is ideal around here.
197 static char *insn_error
;
199 static int byte_order
= BYTE_ORDER
;
201 static int auto_align
= 1;
203 /* Symbol labelling the current insn. */
204 static symbolS
*insn_label
;
206 /* When outputting SVR4 PIC code, the assembler needs to know the
207 offset in the stack frame from which to restore the $gp register.
208 This is set by the .cprestore pseudo-op, and saved in this
210 static offsetT mips_cprestore_offset
= -1;
212 /* This is the register which holds the stack frame, as set by the
213 .frame pseudo-op. This is needed to implement .cprestore. */
214 static int mips_frame_reg
= SP
;
216 /* To output NOP instructions correctly, we need to keep information
217 about the previous two instructions. */
219 /* Whether we are optimizing. The default value of 2 means to remove
220 unneeded NOPs and swap branch instructions when possible. A value
221 of 1 means to not swap branches. A value of 0 means to always
223 static int mips_optimize
= 2;
225 /* The previous instruction. */
226 static struct mips_cl_insn prev_insn
;
228 /* The instruction before prev_insn. */
229 static struct mips_cl_insn prev_prev_insn
;
231 /* If we don't want information for prev_insn or prev_prev_insn, we
232 point the insn_mo field at this dummy integer. */
233 static const struct mips_opcode dummy_opcode
= { 0 };
235 /* Non-zero if prev_insn is valid. */
236 static int prev_insn_valid
;
238 /* The frag for the previous instruction. */
239 static struct frag
*prev_insn_frag
;
241 /* The offset into prev_insn_frag for the previous instruction. */
242 static long prev_insn_where
;
244 /* The reloc for the previous instruction, if any. */
245 static fixS
*prev_insn_fixp
;
247 /* Non-zero if the previous instruction was in a delay slot. */
248 static int prev_insn_is_delay_slot
;
250 /* Non-zero if the previous instruction was in a .set noreorder. */
251 static int prev_insn_unreordered
;
253 /* Non-zero if the previous previous instruction was in a .set
255 static int prev_prev_insn_unreordered
;
257 /* Since the MIPS does not have multiple forms of PC relative
258 instructions, we do not have to do relaxing as is done on other
259 platforms. However, we do have to handle GP relative addressing
260 correctly, which turns out to be a similar problem.
262 Every macro that refers to a symbol can occur in (at least) two
263 forms, one with GP relative addressing and one without. For
264 example, loading a global variable into a register generally uses
265 a macro instruction like this:
267 If i can be addressed off the GP register (this is true if it is in
268 the .sbss or .sdata section, or if it is known to be smaller than
269 the -G argument) this will generate the following instruction:
271 This instruction will use a GPREL reloc. If i can not be addressed
272 off the GP register, the following instruction sequence will be used:
275 In this case the first instruction will have a HI16 reloc, and the
276 second reloc will have a LO16 reloc. Both relocs will be against
279 The issue here is that we may not know whether i is GP addressable
280 until after we see the instruction that uses it. Therefore, we
281 want to be able to choose the final instruction sequence only at
282 the end of the assembly. This is similar to the way other
283 platforms choose the size of a PC relative instruction only at the
286 When generating position independent code we do not use GP
287 addressing in quite the same way, but the issue still arises as
288 external symbols and local symbols must be handled differently.
290 We handle these issues by actually generating both possible
291 instruction sequences. The longer one is put in a frag_var with
292 type rs_machine_dependent. We encode what to do with the frag in
293 the subtype field. We encode (1) the number of existing bytes to
294 replace, (2) the number of new bytes to use, (3) the offset from
295 the start of the existing bytes to the first reloc we must generate
296 (that is, the offset is applied from the start of the existing
297 bytes after they are replaced by the new bytes, if any), (4) the
298 offset from the start of the existing bytes to the second reloc,
299 (5) whether a third reloc is needed (the third reloc is always four
300 bytes after the second reloc), and (6) whether to warn if this
301 variant is used (this is sometimes needed if .set nomacro or .set
302 noat is in effect). All these numbers are reasonably small.
304 Generating two instruction sequences must be handled carefully to
305 ensure that delay slots are handled correctly. Fortunately, there
306 are a limited number of cases. When the second instruction
307 sequence is generated, append_insn is directed to maintain the
308 existing delay slot information, so it continues to apply to any
309 code after the second instruction sequence. This means that the
310 second instruction sequence must not impose any requirements not
311 required by the first instruction sequence.
313 These variant frags are then handled in functions called by the
314 machine independent code. md_estimate_size_before_relax returns
315 the final size of the frag. md_convert_frag sets up the final form
316 of the frag. tc_gen_reloc adjust the first reloc and adds a second
318 #define RELAX_ENCODE(old, new, reloc1, reloc2, reloc3, warn) \
322 | (((reloc1) + 64) << 9) \
323 | (((reloc2) + 64) << 2) \
324 | ((reloc3) ? (1 << 1) : 0) \
326 #define RELAX_OLD(i) (((i) >> 24) & 0xff)
327 #define RELAX_NEW(i) (((i) >> 16) & 0xff)
328 #define RELAX_RELOC1(i) ((((i) >> 9) & 0x7f) - 64)
329 #define RELAX_RELOC2(i) ((((i) >> 2) & 0x7f) - 64)
330 #define RELAX_RELOC3(i) (((i) >> 1) & 1)
331 #define RELAX_WARN(i) ((i) & 1)
333 /* Prototypes for static functions. */
336 #define internalError() \
337 as_fatal ("internal Error, line %d, %s", __LINE__, __FILE__)
339 #define internalError() as_fatal ("MIPS internal Error");
342 static int insn_uses_reg
PARAMS ((struct mips_cl_insn
*ip
,
343 unsigned int reg
, int fpr
));
344 static void append_insn
PARAMS ((char *place
,
345 struct mips_cl_insn
* ip
,
347 bfd_reloc_code_real_type r
));
348 static void mips_no_prev_insn
PARAMS ((void));
349 static void mips_emit_delays
PARAMS ((void));
350 static void macro_build
PARAMS ((char *place
, int *counter
, expressionS
* ep
,
351 const char *name
, const char *fmt
,
353 static void macro_build_lui
PARAMS ((char *place
, int *counter
,
354 expressionS
* ep
, int regnum
));
355 static void set_at
PARAMS ((int *counter
, int reg
, int unsignedp
));
356 static void check_absolute_expr
PARAMS ((struct mips_cl_insn
* ip
,
358 static void load_register
PARAMS ((int *counter
, int reg
, expressionS
* ep
));
359 static void load_address
PARAMS ((int *counter
, int reg
, expressionS
*ep
));
360 static void macro
PARAMS ((struct mips_cl_insn
* ip
));
361 #ifdef LOSING_COMPILER
362 static void macro2
PARAMS ((struct mips_cl_insn
* ip
));
364 static void mips_ip
PARAMS ((char *str
, struct mips_cl_insn
* ip
));
365 static int my_getSmallExpression
PARAMS ((expressionS
* ep
, char *str
));
366 static void my_getExpression
PARAMS ((expressionS
* ep
, char *str
));
367 static symbolS
*get_symbol
PARAMS ((void));
368 static void mips_align
PARAMS ((int to
, int fill
, symbolS
*label
));
369 static void s_align
PARAMS ((int));
370 static void s_stringer
PARAMS ((int));
371 static void s_change_sec
PARAMS ((int));
372 static void s_cons
PARAMS ((int));
373 static void s_err
PARAMS ((int));
374 static void s_extern
PARAMS ((int));
375 static void s_float_cons
PARAMS ((int));
376 static void s_mips_globl
PARAMS ((int));
377 static void s_option
PARAMS ((int));
378 static void s_mipsset
PARAMS ((int));
379 static void s_mips_space
PARAMS ((int));
380 static void s_abicalls
PARAMS ((int));
381 static void s_cpload
PARAMS ((int));
382 static void s_cprestore
PARAMS ((int));
383 static void s_gpword
PARAMS ((int));
384 static void s_cpadd
PARAMS ((int));
385 #ifndef ECOFF_DEBUGGING
386 static void md_obj_begin
PARAMS ((void));
387 static void md_obj_end
PARAMS ((void));
388 static long get_number
PARAMS ((void));
389 static void s_ent
PARAMS ((int));
390 static void s_mipsend
PARAMS ((int));
391 static void s_file
PARAMS ((int));
393 static void s_frame
PARAMS ((int));
394 static void s_loc
PARAMS ((int));
395 static void s_mask
PARAMS ((char));
399 static void s_elf_section
PARAMS ((int));
404 The following pseudo-ops from the Kane and Heinrich MIPS book
405 should be defined here, but are currently unsupported: .alias,
406 .galive, .gjaldef, .gjrlive, .livereg, .noalias.
408 The following pseudo-ops from the Kane and Heinrich MIPS book are
409 specific to the type of debugging information being generated, and
410 should be defined by the object format: .aent, .begin, .bend,
411 .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp,
414 The following pseudo-ops from the Kane and Heinrich MIPS book are
415 not MIPS CPU specific, but are also not specific to the object file
416 format. This file is probably the best place to define them, but
417 they are not currently supported: .asm0, .endr, .lab, .repeat,
418 .struct, .weakext. */
420 const pseudo_typeS md_pseudo_table
[] =
422 /* MIPS specific pseudo-ops. */
423 {"option", s_option
, 0},
424 {"set", s_mipsset
, 0},
425 {"rdata", s_change_sec
, 'r'},
426 {"sdata", s_change_sec
, 's'},
427 {"livereg", s_ignore
, 0},
428 { "abicalls", s_abicalls
, 0},
429 { "cpload", s_cpload
, 0},
430 { "cprestore", s_cprestore
, 0},
431 { "gpword", s_gpword
, 0},
432 { "cpadd", s_cpadd
, 0},
434 /* Relatively generic pseudo-ops that happen to be used on MIPS
436 {"asciiz", s_stringer
, 1},
437 {"bss", s_change_sec
, 'b'},
440 {"dword", s_cons
, 3},
442 /* These pseudo-ops are defined in read.c, but must be overridden
443 here for one reason or another. */
444 {"align", s_align
, 0},
445 {"ascii", s_stringer
, 0},
446 {"asciz", s_stringer
, 1},
448 {"data", s_change_sec
, 'd'},
449 {"double", s_float_cons
, 'd'},
450 {"extern", s_extern
, 0},
451 {"float", s_float_cons
, 'f'},
452 {"globl", s_mips_globl
, 0},
453 {"global", s_mips_globl
, 0},
454 {"hword", s_cons
, 1},
459 {"short", s_cons
, 1},
460 {"single", s_float_cons
, 'f'},
461 {"space", s_mips_space
, 0},
462 {"text", s_change_sec
, 't'},
465 #ifndef ECOFF_DEBUGGING
466 /* These pseudo-ops should be defined by the object file format.
467 However, a.out doesn't support them, so we have versions here. */
469 {"bgnb", s_ignore
, 0},
470 {"end", s_mipsend
, 0},
471 {"endb", s_ignore
, 0},
474 {"fmask", s_ignore
, 'F'},
475 {"frame", s_ignore
, 0},
476 {"loc", s_ignore
, 0},
477 {"mask", s_ignore
, 'R'},
478 {"verstamp", s_ignore
, 0},
482 /* We need to tweak the ELF ".section" pseudo-op a bit. */
483 {"section", s_elf_section
, 0},
490 const relax_typeS md_relax_table
[] =
495 static char *expr_end
;
497 static expressionS imm_expr
;
498 static expressionS offset_expr
;
499 static bfd_reloc_code_real_type imm_reloc
;
500 static bfd_reloc_code_real_type offset_reloc
;
502 /* FIXME: This should be handled in a different way. */
503 extern int target_big_endian
;
506 * This function is called once, at assembler startup time. It should
507 * set up all the tables, etc. that the MD part of the assembler will need.
513 register const char *retval
= NULL
;
514 register unsigned int i
= 0;
522 if (strcmp (cpu
+ (sizeof TARGET_CPU
) - 3, "el") == 0)
524 a
= xmalloc (sizeof TARGET_CPU
);
525 strcpy (a
, TARGET_CPU
);
526 a
[(sizeof TARGET_CPU
) - 3] = '\0';
530 if (strcmp (cpu
, "mips") == 0)
536 else if (strcmp (cpu
, "r6000") == 0
537 || strcmp (cpu
, "mips2") == 0)
543 else if (strcmp (cpu
, "mips64") == 0
544 || strcmp (cpu
, "r4000") == 0
545 || strcmp (cpu
, "mips3") == 0)
551 else if (strcmp (cpu
, "r4400") == 0)
557 else if (strcmp (cpu
, "mips64orion") == 0
558 || strcmp (cpu
, "r4600") == 0)
575 if (mips_isa
< 2 && mips_trap
)
576 as_bad ("trap exception not supported at ISA 1");
581 ok
= bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, 3000);
584 ok
= bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, 6000);
587 ok
= bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, 4000);
591 as_warn ("Could not set architecture and machine");
593 file_mips_isa
= mips_isa
;
595 op_hash
= hash_new ();
597 for (i
= 0; i
< NUMOPCODES
;)
599 const char *name
= mips_opcodes
[i
].name
;
601 retval
= hash_insert (op_hash
, name
, (PTR
) &mips_opcodes
[i
]);
604 fprintf (stderr
, "internal error: can't hash `%s': %s\n",
605 mips_opcodes
[i
].name
, retval
);
606 as_fatal ("Broken assembler. No assembly attempted.");
610 if (mips_opcodes
[i
].pinfo
!= INSN_MACRO
611 && ((mips_opcodes
[i
].match
& mips_opcodes
[i
].mask
)
612 != mips_opcodes
[i
].match
))
614 fprintf (stderr
, "internal error: bad opcode: `%s' \"%s\"\n",
615 mips_opcodes
[i
].name
, mips_opcodes
[i
].args
);
616 as_fatal ("Broken assembler. No assembly attempted.");
620 while ((i
< NUMOPCODES
) && !strcmp (mips_opcodes
[i
].name
, name
));
623 mips_no_prev_insn ();
631 /* set the default alignment for the text section (2**2) */
632 record_alignment (text_section
, 2);
634 /* FIXME: This should be handled in a different way. */
635 target_big_endian
= byte_order
== BIG_ENDIAN
;
638 bfd_set_gp_size (stdoutput
, g_switch_value
);
642 /* Sections must be aligned to 16 byte boundaries. */
643 (void) bfd_set_section_alignment (stdoutput
, text_section
, 4);
644 (void) bfd_set_section_alignment (stdoutput
, data_section
, 4);
645 (void) bfd_set_section_alignment (stdoutput
, bss_section
, 4);
647 /* Create a .reginfo section for register masks and a .mdebug
648 section for debugging information. */
656 sec
= subseg_new (".reginfo", (subsegT
) 0);
658 /* The ABI says this section should be loaded so that the running
659 program can access it. */
660 (void) bfd_set_section_flags (stdoutput
, sec
,
661 (SEC_ALLOC
| SEC_LOAD
662 | SEC_READONLY
| SEC_DATA
));
663 (void) bfd_set_section_alignment (stdoutput
, sec
, 2);
665 mips_regmask_frag
= frag_more (sizeof (Elf32_External_RegInfo
));
667 #ifdef ECOFF_DEBUGGING
668 sec
= subseg_new (".mdebug", (subsegT
) 0);
669 (void) bfd_set_section_flags (stdoutput
, sec
,
670 SEC_HAS_CONTENTS
| SEC_READONLY
);
671 (void) bfd_set_section_alignment (stdoutput
, sec
, 2);
674 subseg_set (seg
, subseg
);
678 #ifndef ECOFF_DEBUGGING
686 #ifndef ECOFF_DEBUGGING
695 struct mips_cl_insn insn
;
697 imm_expr
.X_op
= O_absent
;
698 offset_expr
.X_op
= O_absent
;
700 mips_ip (str
, &insn
);
703 as_bad ("%s `%s'", insn_error
, str
);
706 if (insn
.insn_mo
->pinfo
== INSN_MACRO
)
712 if (imm_expr
.X_op
!= O_absent
)
713 append_insn ((char *) NULL
, &insn
, &imm_expr
, imm_reloc
);
714 else if (offset_expr
.X_op
!= O_absent
)
715 append_insn ((char *) NULL
, &insn
, &offset_expr
, offset_reloc
);
717 append_insn ((char *) NULL
, &insn
, NULL
, BFD_RELOC_UNUSED
);
721 /* See whether instruction IP reads register REG. If FPR is non-zero,
722 REG is a floating point register. */
725 insn_uses_reg (ip
, reg
, fpr
)
726 struct mips_cl_insn
*ip
;
730 /* Don't report on general register 0, since it never changes. */
731 if (! fpr
&& reg
== 0)
736 /* If we are called with either $f0 or $f1, we must check $f0.
737 This is not optimal, because it will introduce an unnecessary
738 NOP between "lwc1 $f0" and "swc1 $f1". To fix this we would
739 need to distinguish reading both $f0 and $f1 or just one of
740 them. Note that we don't have to check the other way,
741 because there is no instruction that sets both $f0 and $f1
742 and requires a delay. */
743 if ((ip
->insn_mo
->pinfo
& INSN_READ_FPR_S
)
744 && (((ip
->insn_opcode
>> OP_SH_FS
) & OP_MASK_FS
)
745 == (reg
&~ (unsigned) 1)))
747 if ((ip
->insn_mo
->pinfo
& INSN_READ_FPR_T
)
748 && (((ip
->insn_opcode
>> OP_SH_FT
) & OP_MASK_FT
)
749 == (reg
&~ (unsigned) 1)))
754 if ((ip
->insn_mo
->pinfo
& INSN_READ_GPR_S
)
755 && ((ip
->insn_opcode
>> OP_SH_RS
) & OP_MASK_RS
) == reg
)
757 if ((ip
->insn_mo
->pinfo
& INSN_READ_GPR_T
)
758 && ((ip
->insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
) == reg
)
765 /* Output an instruction. PLACE is where to put the instruction; if
766 it is NULL, this uses frag_more to get room. IP is the instruction
767 information. ADDRESS_EXPR is an operand of the instruction to be
768 used with RELOC_TYPE. */
771 append_insn (place
, ip
, address_expr
, reloc_type
)
773 struct mips_cl_insn
*ip
;
774 expressionS
*address_expr
;
775 bfd_reloc_code_real_type reloc_type
;
777 register unsigned long prev_pinfo
, pinfo
;
782 prev_pinfo
= prev_insn
.insn_mo
->pinfo
;
783 pinfo
= ip
->insn_mo
->pinfo
;
785 if (place
== NULL
&& ! mips_noreorder
)
787 /* If the previous insn required any delay slots, see if we need
788 to insert a NOP or two. There are eight kinds of possible
789 hazards, of which an instruction can have at most one type.
790 (1) a load from memory delay
791 (2) a load from a coprocessor delay
792 (3) an unconditional branch delay
793 (4) a conditional branch delay
794 (5) a move to coprocessor register delay
795 (6) a load coprocessor register from memory delay
796 (7) a coprocessor condition code delay
797 (8) a HI/LO special register delay
799 There are a lot of optimizations we could do that we don't.
800 In particular, we do not, in general, reorder instructions.
801 If you use gcc with optimization, it will reorder
802 instructions and generally do much more optimization then we
803 do here; repeating all that work in the assembler would only
804 benefit hand written assembly code, and does not seem worth
807 /* This is how a NOP is emitted. */
808 #define emit_nop() md_number_to_chars (frag_more (4), 0, 4)
810 /* The previous insn might require a delay slot, depending upon
811 the contents of the current insn. */
812 if ((prev_pinfo
& INSN_LOAD_COPROC_DELAY
)
814 && (prev_pinfo
& INSN_LOAD_MEMORY_DELAY
)))
816 /* A load from a coprocessor or from memory. All load
817 delays delay the use of general register rt for one
818 instruction on the r3000. The r6000 and r4000 use
820 know (prev_pinfo
& INSN_WRITE_GPR_T
);
821 if (mips_optimize
== 0
822 || insn_uses_reg (ip
,
823 ((prev_insn
.insn_opcode
>> OP_SH_RT
)
828 else if ((prev_pinfo
& INSN_COPROC_MOVE_DELAY
)
830 && (prev_pinfo
& INSN_COPROC_MEMORY_DELAY
)))
832 /* A generic coprocessor delay. The previous instruction
833 modified a coprocessor general or control register. If
834 it modified a control register, we need to avoid any
835 coprocessor instruction (this is probably not always
836 required, but it sometimes is). If it modified a general
837 register, we avoid using that register.
839 On the r6000 and r4000 loading a coprocessor register
840 from memory is interlocked, and does not require a delay.
842 This case is not handled very well. There is no special
843 knowledge of CP0 handling, and the coprocessors other
844 than the floating point unit are not distinguished at
846 if (prev_pinfo
& INSN_WRITE_FPR_T
)
848 if (mips_optimize
== 0
849 || insn_uses_reg (ip
,
850 ((prev_insn
.insn_opcode
>> OP_SH_FT
)
855 else if (prev_pinfo
& INSN_WRITE_FPR_S
)
857 if (mips_optimize
== 0
858 || insn_uses_reg (ip
,
859 ((prev_insn
.insn_opcode
>> OP_SH_FS
)
866 /* We don't know exactly what the previous instruction
867 does. If the current instruction uses a coprocessor
868 register, we must insert a NOP. If previous
869 instruction may set the condition codes, and the
870 current instruction uses them, we must insert two
872 if (mips_optimize
== 0
873 || ((prev_pinfo
& INSN_WRITE_COND_CODE
)
874 && (pinfo
& INSN_READ_COND_CODE
)))
876 else if (pinfo
& INSN_COP
)
880 else if (prev_pinfo
& INSN_WRITE_COND_CODE
)
882 /* The previous instruction sets the coprocessor condition
883 codes, but does not require a general coprocessor delay
884 (this means it is a floating point comparison
885 instruction). If this instruction uses the condition
886 codes, we need to insert a single NOP. */
887 if (mips_optimize
== 0
888 || (pinfo
& INSN_READ_COND_CODE
))
891 else if (prev_pinfo
& INSN_READ_LO
)
893 /* The previous instruction reads the LO register; if the
894 current instruction writes to the LO register, we must
896 if (mips_optimize
== 0
897 || (pinfo
& INSN_WRITE_LO
))
900 else if (prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
902 /* The previous instruction reads the HI register; if the
903 current instruction writes to the HI register, we must
905 if (mips_optimize
== 0
906 || (pinfo
& INSN_WRITE_HI
))
910 /* There are two cases which require two intervening
911 instructions: 1) setting the condition codes using a move to
912 coprocessor instruction which requires a general coprocessor
913 delay and then reading the condition codes 2) reading the HI
914 or LO register and then writing to it. If we are not already
915 emitting a NOP instruction, we must check for these cases
916 compared to the instruction previous to the previous
919 && (((prev_prev_insn
.insn_mo
->pinfo
& INSN_COPROC_MOVE_DELAY
)
920 && (prev_prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
)
921 && (pinfo
& INSN_READ_COND_CODE
))
922 || ((prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
)
923 && (pinfo
& INSN_WRITE_LO
))
924 || ((prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
925 && (pinfo
& INSN_WRITE_HI
))))
928 /* If we are being given a nop instruction, don't bother with
929 one of the nops we would otherwise output. This will only
930 happen when a nop instruction is used with mips_optimize set
932 if (nops
> 0 && ip
->insn_opcode
== 0)
935 /* Now emit the right number of NOP instructions. */
940 for (i
= 0; i
< nops
; i
++)
943 listing_prev_line ();
944 if (insn_label
!= NULL
)
946 assert (S_GET_SEGMENT (insn_label
) == now_seg
);
947 insn_label
->sy_frag
= frag_now
;
948 S_SET_VALUE (insn_label
, (valueT
) frag_now_fix ());
958 if (address_expr
!= NULL
)
960 if (address_expr
->X_op
== O_constant
)
965 ip
->insn_opcode
|= address_expr
->X_add_number
;
969 ip
->insn_opcode
|= address_expr
->X_add_number
& 0xffff;
972 case BFD_RELOC_MIPS_JMP
:
973 case BFD_RELOC_16_PCREL_S2
:
982 assert (reloc_type
!= BFD_RELOC_UNUSED
);
984 /* Don't generate a reloc if we are writing into a variant
987 fixp
= fix_new_exp (frag_now
, f
- frag_now
->fr_literal
, 4,
989 reloc_type
== BFD_RELOC_16_PCREL_S2
,
994 md_number_to_chars (f
, ip
->insn_opcode
, 4);
996 /* Update the register mask information. */
997 if (pinfo
& INSN_WRITE_GPR_D
)
998 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
);
999 if ((pinfo
& (INSN_WRITE_GPR_T
| INSN_READ_GPR_T
)) != 0)
1000 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
);
1001 if (pinfo
& INSN_READ_GPR_S
)
1002 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> OP_SH_RS
) & OP_MASK_RS
);
1003 if (pinfo
& INSN_WRITE_GPR_31
)
1004 mips_gprmask
|= 1 << 31;
1005 if (pinfo
& INSN_WRITE_FPR_D
)
1006 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FD
) & OP_MASK_FD
);
1007 if ((pinfo
& (INSN_WRITE_FPR_S
| INSN_READ_FPR_S
)) != 0)
1008 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FS
) & OP_MASK_FS
);
1009 if ((pinfo
& (INSN_WRITE_FPR_T
| INSN_READ_FPR_T
)) != 0)
1010 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FT
) & OP_MASK_FT
);
1011 if (pinfo
& INSN_COP
)
1013 /* We don't keep enough information to sort these cases out. */
1015 /* Never set the bit for $0, which is always zero. */
1016 mips_gprmask
&=~ 1 << 0;
1018 if (place
== NULL
&& ! mips_noreorder
)
1020 /* Filling the branch delay slot is more complex. We try to
1021 switch the branch with the previous instruction, which we can
1022 do if the previous instruction does not set up a condition
1023 that the branch tests and if the branch is not itself the
1024 target of any branch. */
1025 if ((pinfo
& INSN_UNCOND_BRANCH_DELAY
)
1026 || (pinfo
& INSN_COND_BRANCH_DELAY
))
1028 if (mips_optimize
< 2
1029 /* If we have seen .set volatile or .set nomove, don't
1032 /* If we had to emit any NOP instructions, then we
1033 already know we can not swap. */
1035 /* If we don't even know the previous insn, we can not
1037 || ! prev_insn_valid
1038 /* If the previous insn is already in a branch delay
1039 slot, then we can not swap. */
1040 || prev_insn_is_delay_slot
1041 /* If the previous previous insn was in a .set
1042 noreorder, we can't swap. Actually, the MIPS
1043 assembler will swap in this situation. However, gcc
1044 configured -with-gnu-as will generate code like
1050 in which we can not swap the bne and INSN. If gcc is
1051 not configured -with-gnu-as, it does not output the
1052 .set pseudo-ops. We don't have to check
1053 prev_insn_unreordered, because prev_insn_valid will
1054 be 0 in that case. We don't want to use
1055 prev_prev_insn_valid, because we do want to be able
1056 to swap at the start of a function. */
1057 || prev_prev_insn_unreordered
1058 /* If the branch is itself the target of a branch, we
1059 can not swap. We cheat on this; all we check for is
1060 whether there is a label on this instruction. If
1061 there are any branches to anything other than a
1062 label, users must use .set noreorder. */
1063 || insn_label
!= NULL
1064 /* If the previous instruction is in a variant frag, we
1065 can not do the swap. */
1066 || prev_insn_frag
->fr_type
== rs_machine_dependent
1067 /* If the branch reads the condition codes, we don't
1068 even try to swap, because in the sequence
1073 we can not swap, and I don't feel like handling that
1075 || (pinfo
& INSN_READ_COND_CODE
)
1076 /* We can not swap with an instruction that requires a
1077 delay slot, becase the target of the branch might
1078 interfere with that instruction. */
1080 & (INSN_LOAD_COPROC_DELAY
1081 | INSN_COPROC_MOVE_DELAY
1082 | INSN_WRITE_COND_CODE
1087 & (INSN_LOAD_MEMORY_DELAY
1088 | INSN_COPROC_MEMORY_DELAY
)))
1089 /* We can not swap with a branch instruction. */
1091 & (INSN_UNCOND_BRANCH_DELAY
1092 | INSN_COND_BRANCH_DELAY
1093 | INSN_COND_BRANCH_LIKELY
))
1094 /* We do not swap with a trap instruction, since it
1095 complicates trap handlers to have the trap
1096 instruction be in a delay slot. */
1097 || (prev_pinfo
& INSN_TRAP
)
1098 /* If the branch reads a register that the previous
1099 instruction sets, we can not swap. */
1100 || ((prev_pinfo
& INSN_WRITE_GPR_T
)
1101 && insn_uses_reg (ip
,
1102 ((prev_insn
.insn_opcode
>> OP_SH_RT
)
1105 || ((prev_pinfo
& INSN_WRITE_GPR_D
)
1106 && insn_uses_reg (ip
,
1107 ((prev_insn
.insn_opcode
>> OP_SH_RD
)
1110 /* If the branch writes a register that the previous
1111 instruction sets, we can not swap (we know that
1112 branches write only to RD or to $31). */
1113 || ((prev_pinfo
& INSN_WRITE_GPR_T
)
1114 && (((pinfo
& INSN_WRITE_GPR_D
)
1115 && (((prev_insn
.insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
)
1116 == ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)))
1117 || ((pinfo
& INSN_WRITE_GPR_31
)
1118 && (((prev_insn
.insn_opcode
>> OP_SH_RT
)
1121 || ((prev_pinfo
& INSN_WRITE_GPR_D
)
1122 && (((pinfo
& INSN_WRITE_GPR_D
)
1123 && (((prev_insn
.insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)
1124 == ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)))
1125 || ((pinfo
& INSN_WRITE_GPR_31
)
1126 && (((prev_insn
.insn_opcode
>> OP_SH_RD
)
1129 /* If the branch writes a register that the previous
1130 instruction reads, we can not swap (we know that
1131 branches only write to RD or to $31). */
1132 || ((pinfo
& INSN_WRITE_GPR_D
)
1133 && insn_uses_reg (&prev_insn
,
1134 ((ip
->insn_opcode
>> OP_SH_RD
)
1137 || ((pinfo
& INSN_WRITE_GPR_31
)
1138 && insn_uses_reg (&prev_insn
, 31, 0))
1139 /* If we are generating embedded PIC code, the branch
1140 might be expanded into a sequence which uses $at, so
1141 we can't swap with an instruction which reads it. */
1142 || (mips_pic
== EMBEDDED_PIC
1143 && insn_uses_reg (&prev_insn
, AT
, 0))
1144 /* If the previous previous instruction has a load
1145 delay, and sets a register that the branch reads, we
1147 || (((prev_prev_insn
.insn_mo
->pinfo
& INSN_LOAD_COPROC_DELAY
)
1149 && (prev_prev_insn
.insn_mo
->pinfo
1150 & INSN_LOAD_MEMORY_DELAY
)))
1151 && insn_uses_reg (ip
,
1152 ((prev_prev_insn
.insn_opcode
>> OP_SH_RT
)
1156 /* We could do even better for unconditional branches to
1157 portions of this object file; we could pick up the
1158 instruction at the destination, put it in the delay
1159 slot, and bump the destination address. */
1161 /* Update the previous insn information. */
1162 prev_prev_insn
= *ip
;
1163 prev_insn
.insn_mo
= &dummy_opcode
;
1170 /* It looks like we can actually do the swap. */
1171 prev_f
= prev_insn_frag
->fr_literal
+ prev_insn_where
;
1172 memcpy (temp
, prev_f
, 4);
1173 memcpy (prev_f
, f
, 4);
1174 memcpy (f
, temp
, 4);
1177 prev_insn_fixp
->fx_frag
= frag_now
;
1178 prev_insn_fixp
->fx_where
= f
- frag_now
->fr_literal
;
1182 fixp
->fx_frag
= prev_insn_frag
;
1183 fixp
->fx_where
= prev_insn_where
;
1185 /* Update the previous insn information; leave prev_insn
1187 prev_prev_insn
= *ip
;
1189 prev_insn_is_delay_slot
= 1;
1191 /* If that was an unconditional branch, forget the previous
1192 insn information. */
1193 if (pinfo
& INSN_UNCOND_BRANCH_DELAY
)
1195 prev_prev_insn
.insn_mo
= &dummy_opcode
;
1196 prev_insn
.insn_mo
= &dummy_opcode
;
1199 else if (pinfo
& INSN_COND_BRANCH_LIKELY
)
1201 /* We don't yet optimize a branch likely. What we should do
1202 is look at the target, copy the instruction found there
1203 into the delay slot, and increment the branch to jump to
1204 the next instruction. */
1206 /* Update the previous insn information. */
1207 prev_prev_insn
= *ip
;
1208 prev_insn
.insn_mo
= &dummy_opcode
;
1212 /* Update the previous insn information. */
1214 prev_prev_insn
.insn_mo
= &dummy_opcode
;
1216 prev_prev_insn
= prev_insn
;
1219 /* Any time we see a branch, we always fill the delay slot
1220 immediately; since this insn is not a branch, we know it
1221 is not in a delay slot. */
1222 prev_insn_is_delay_slot
= 0;
1225 prev_prev_insn_unreordered
= prev_insn_unreordered
;
1226 prev_insn_unreordered
= 0;
1227 prev_insn_frag
= frag_now
;
1228 prev_insn_where
= f
- frag_now
->fr_literal
;
1229 prev_insn_fixp
= fixp
;
1230 prev_insn_valid
= 1;
1233 /* We just output an insn, so the next one doesn't have a label. */
1237 /* This function forgets that there was any previous instruction or
1241 mips_no_prev_insn ()
1243 prev_insn
.insn_mo
= &dummy_opcode
;
1244 prev_prev_insn
.insn_mo
= &dummy_opcode
;
1245 prev_insn_valid
= 0;
1246 prev_insn_is_delay_slot
= 0;
1247 prev_insn_unreordered
= 0;
1248 prev_prev_insn_unreordered
= 0;
1252 /* This function must be called whenever we turn on noreorder or emit
1253 something other than instructions. It inserts any NOPS which might
1254 be needed by the previous instruction, and clears the information
1255 kept for the previous instructions. */
1260 if (! mips_noreorder
)
1265 if ((prev_insn
.insn_mo
->pinfo
1266 & (INSN_LOAD_COPROC_DELAY
1267 | INSN_COPROC_MOVE_DELAY
1268 | INSN_WRITE_COND_CODE
1272 && (prev_insn
.insn_mo
->pinfo
1273 & (INSN_LOAD_MEMORY_DELAY
1274 | INSN_COPROC_MEMORY_DELAY
))))
1277 if ((prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
)
1278 || (prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
1279 || (prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
))
1282 else if ((prev_prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
)
1283 || (prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
1284 || (prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
))
1289 if (insn_label
!= NULL
)
1291 assert (S_GET_SEGMENT (insn_label
) == now_seg
);
1292 insn_label
->sy_frag
= frag_now
;
1293 S_SET_VALUE (insn_label
, (valueT
) frag_now_fix ());
1298 mips_no_prev_insn ();
1301 /* Build an instruction created by a macro expansion. This is passed
1302 a pointer to the count of instructions created so far, an
1303 expression, the name of the instruction to build, an operand format
1304 string, and corresponding arguments. */
1308 macro_build (char *place
,
1314 #else /* ! defined (NO_STDARG) */
1316 macro_build (place
, counter
, ep
, name
, fmt
, va_alist
)
1323 #endif /* ! defined (NO_STDARG) */
1325 struct mips_cl_insn insn
;
1326 bfd_reloc_code_real_type r
;
1330 va_start (args
, fmt
);
1336 * If the macro is about to expand into a second instruction,
1337 * print a warning if needed. We need to pass ip as a parameter
1338 * to generate a better warning message here...
1340 if (mips_warn_about_macros
&& place
== NULL
&& *counter
== 1)
1341 as_warn ("Macro instruction expanded into multiple instructions");
1344 *counter
+= 1; /* bump instruction counter */
1346 r
= BFD_RELOC_UNUSED
;
1347 insn
.insn_mo
= (struct mips_opcode
*) hash_find (op_hash
, name
);
1348 assert (insn
.insn_mo
);
1349 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
1351 while (strcmp (fmt
, insn
.insn_mo
->args
) != 0
1352 || insn
.insn_mo
->pinfo
== INSN_MACRO
)
1355 assert (insn
.insn_mo
->name
);
1356 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
1358 insn
.insn_opcode
= insn
.insn_mo
->match
;
1374 insn
.insn_opcode
|= va_arg (args
, int) << 16;
1380 insn
.insn_opcode
|= va_arg (args
, int) << 16;
1385 insn
.insn_opcode
|= va_arg (args
, int) << 11;
1390 insn
.insn_opcode
|= va_arg (args
, int) << 11;
1397 insn
.insn_opcode
|= va_arg (args
, int) << 6;
1401 insn
.insn_opcode
|= va_arg (args
, int) << 6;
1405 insn
.insn_opcode
|= va_arg (args
, int) << 6;
1412 insn
.insn_opcode
|= va_arg (args
, int) << 21;
1418 r
= (bfd_reloc_code_real_type
) va_arg (args
, int);
1419 assert (r
== BFD_RELOC_MIPS_GPREL
1420 || r
== BFD_RELOC_MIPS_LITERAL
1421 || r
== BFD_RELOC_LO16
1422 || r
== BFD_RELOC_MIPS_GOT16
1423 || r
== BFD_RELOC_MIPS_CALL16
1424 || (ep
->X_op
== O_subtract
1425 && now_seg
== text_section
1426 && S_GET_SEGMENT (ep
->X_op_symbol
) == text_section
1427 && r
== BFD_RELOC_PCREL_LO16
));
1431 r
= (bfd_reloc_code_real_type
) va_arg (args
, int);
1433 && (ep
->X_op
== O_constant
1434 || (ep
->X_op
== O_symbol
1435 && (r
== BFD_RELOC_HI16_S
1436 || r
== BFD_RELOC_HI16
))
1437 || (ep
->X_op
== O_subtract
1438 && now_seg
== text_section
1439 && S_GET_SEGMENT (ep
->X_op_symbol
) == text_section
1440 && r
== BFD_RELOC_PCREL_HI16_S
)));
1441 if (ep
->X_op
== O_constant
)
1443 insn
.insn_opcode
|= (ep
->X_add_number
>> 16) & 0xffff;
1445 r
= BFD_RELOC_UNUSED
;
1450 assert (ep
!= NULL
);
1452 * This allows macro() to pass an immediate expression for
1453 * creating short branches without creating a symbol.
1454 * Note that the expression still might come from the assembly
1455 * input, in which case the value is not checked for range nor
1456 * is a relocation entry generated (yuck).
1458 if (ep
->X_op
== O_constant
)
1460 insn
.insn_opcode
|= (ep
->X_add_number
>> 2) & 0xffff;
1464 r
= BFD_RELOC_16_PCREL_S2
;
1468 assert (ep
!= NULL
);
1469 r
= BFD_RELOC_MIPS_JMP
;
1478 assert (r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
1480 append_insn (place
, &insn
, ep
, r
);
1484 * Generate a "lui" instruction.
1487 macro_build_lui (place
, counter
, ep
, regnum
)
1493 expressionS high_expr
;
1494 struct mips_cl_insn insn
;
1495 bfd_reloc_code_real_type r
;
1496 CONST
char *name
= "lui";
1497 CONST
char *fmt
= "t,u";
1503 high_expr
.X_op
= O_constant
;
1504 high_expr
.X_add_number
= 0;
1507 if (high_expr
.X_op
== O_constant
)
1509 /* we can compute the instruction now without a relocation entry */
1510 if (high_expr
.X_add_number
& 0x8000)
1511 high_expr
.X_add_number
+= 0x10000;
1512 high_expr
.X_add_number
=
1513 ((unsigned long) high_expr
.X_add_number
>> 16) & 0xffff;
1514 r
= BFD_RELOC_UNUSED
;
1518 assert (ep
->X_op
== O_symbol
);
1519 /* _gp_disp is a special case, used from s_cpload. */
1520 assert (mips_pic
== NO_PIC
1521 || strcmp (S_GET_NAME (ep
->X_add_symbol
), "_gp_disp") == 0);
1522 r
= BFD_RELOC_HI16_S
;
1526 * If the macro is about to expand into a second instruction,
1527 * print a warning if needed. We need to pass ip as a parameter
1528 * to generate a better warning message here...
1530 if (mips_warn_about_macros
&& place
== NULL
&& *counter
== 1)
1531 as_warn ("Macro instruction expanded into multiple instructions");
1534 *counter
+= 1; /* bump instruction counter */
1536 insn
.insn_mo
= (struct mips_opcode
*) hash_find (op_hash
, name
);
1537 assert (insn
.insn_mo
);
1538 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
1539 assert (strcmp (fmt
, insn
.insn_mo
->args
) == 0);
1541 insn
.insn_opcode
= insn
.insn_mo
->match
| (regnum
<< OP_SH_RT
);
1542 if (r
== BFD_RELOC_UNUSED
)
1544 insn
.insn_opcode
|= high_expr
.X_add_number
;
1545 append_insn (place
, &insn
, NULL
, r
);
1548 append_insn (place
, &insn
, &high_expr
, r
);
1552 * Generates code to set the $at register to true (one)
1553 * if reg is less than the immediate expression.
1556 set_at (counter
, reg
, unsignedp
)
1561 if (imm_expr
.X_add_number
>= -0x8000 && imm_expr
.X_add_number
< 0x8000)
1562 macro_build ((char *) NULL
, counter
, &imm_expr
,
1563 unsignedp
? "sltiu" : "slti",
1564 "t,r,j", AT
, reg
, (int) BFD_RELOC_LO16
);
1567 load_register (counter
, AT
, &imm_expr
);
1568 macro_build ((char *) NULL
, counter
, NULL
,
1569 unsignedp
? "sltu" : "slt",
1570 "d,v,t", AT
, reg
, AT
);
1574 /* Warn if an expression is not a constant. */
1577 check_absolute_expr (ip
, ex
)
1578 struct mips_cl_insn
*ip
;
1581 if (ex
->X_op
!= O_constant
)
1582 as_warn ("Instruction %s requires absolute expression", ip
->insn_mo
->name
);
1586 * This routine generates the least number of instructions neccessary to load
1587 * an absolute expression value into a register.
1590 load_register (counter
, reg
, ep
)
1595 assert (ep
->X_op
== O_constant
);
1596 if (ep
->X_add_number
>= -0x8000 && ep
->X_add_number
< 0x8000)
1598 /* No need to ever use daddiu here, since we are adding in
1600 macro_build ((char *) NULL
, counter
, ep
, "addiu", "t,r,j", reg
, 0,
1601 (int) BFD_RELOC_LO16
);
1603 else if (ep
->X_add_number
>= 0 && ep
->X_add_number
< 0x10000)
1604 macro_build ((char *) NULL
, counter
, ep
, "ori", "t,r,i", reg
, 0,
1605 (int) BFD_RELOC_LO16
);
1606 else if ((ep
->X_add_number
&~ (offsetT
) 0x7fffffff) == 0
1607 || ((ep
->X_add_number
&~ (offsetT
) 0x7fffffff)
1608 == ~ (offsetT
) 0x7fffffff))
1610 macro_build ((char *) NULL
, counter
, ep
, "lui", "t,u", reg
,
1611 (int) BFD_RELOC_HI16
);
1612 if ((ep
->X_add_number
& 0xffff) != 0)
1613 macro_build ((char *) NULL
, counter
, ep
, "ori", "t,r,i", reg
, reg
,
1614 (int) BFD_RELOC_LO16
);
1616 else if (mips_isa
< 3)
1618 as_bad ("Number larger than 32 bits");
1619 macro_build ((char *) NULL
, counter
, ep
, "addiu", "t,r,j", reg
, 0,
1620 (int) BFD_RELOC_LO16
);
1625 expressionS hi32
, lo32
;
1629 hi32
.X_add_number
>>= shift
;
1630 hi32
.X_add_number
&= 0xffffffff;
1631 if ((hi32
.X_add_number
& 0x80000000) != 0)
1632 hi32
.X_add_number
|= ~ (offsetT
) 0xffffffff;
1633 load_register (counter
, reg
, &hi32
);
1635 lo32
.X_add_number
&= 0xffffffff;
1636 if ((lo32
.X_add_number
& 0xffff0000) == 0)
1637 macro_build ((char *) NULL
, counter
, NULL
, "dsll32", "d,w,<", reg
,
1643 macro_build ((char *) NULL
, counter
, NULL
, "dsll", "d,w,<", reg
,
1646 mid16
.X_add_number
>>= 16;
1647 macro_build ((char *) NULL
, counter
, &mid16
, "ori", "t,r,i", reg
,
1648 reg
, (int) BFD_RELOC_LO16
);
1649 macro_build ((char *) NULL
, counter
, NULL
, "dsll", "d,w,<", reg
,
1652 if ((lo32
.X_add_number
& 0xffff) != 0)
1653 macro_build ((char *) NULL
, counter
, &lo32
, "ori", "t,r,i", reg
, reg
,
1654 (int) BFD_RELOC_LO16
);
1658 /* Load an address into a register. */
1661 load_address (counter
, reg
, ep
)
1668 if (ep
->X_op
!= O_constant
1669 && ep
->X_op
!= O_symbol
)
1671 as_bad ("expression too complex");
1672 ep
->X_op
= O_constant
;
1675 if (ep
->X_op
== O_constant
)
1677 load_register (counter
, reg
, ep
);
1681 if (mips_pic
== NO_PIC
)
1683 /* If this is a reference to a GP relative symbol, we want
1684 addiu $reg,$gp,<sym> (BFD_RELOC_MIPS_GPREL)
1686 lui $reg,<sym> (BFD_RELOC_HI16_S)
1687 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
1688 If we have an addend, we always use the latter form. */
1689 if (ep
->X_add_number
!= 0)
1694 macro_build ((char *) NULL
, counter
, ep
,
1695 mips_isa
< 3 ? "addiu" : "daddiu",
1696 "t,r,j", reg
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
1697 p
= frag_var (rs_machine_dependent
, 8, 0,
1698 RELAX_ENCODE (4, 8, -4, 0, 0, mips_warn_about_macros
),
1699 ep
->X_add_symbol
, (long) 0, (char *) NULL
);
1701 macro_build_lui (p
, counter
, ep
, reg
);
1704 macro_build (p
, counter
, ep
,
1705 mips_isa
< 3 ? "addiu" : "daddiu",
1706 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
1708 else if (mips_pic
== SVR4_PIC
)
1712 /* If this is a reference to an external symbol, we want
1713 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
1715 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
1717 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
1718 If there is a constant, it must be added in after. */
1719 ex
.X_add_number
= ep
->X_add_number
;
1720 ep
->X_add_number
= 0;
1722 macro_build ((char *) NULL
, counter
, ep
,
1723 mips_isa
< 3 ? "lw" : "ld",
1724 "t,o(b)", reg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
1725 macro_build ((char *) NULL
, counter
, (expressionS
*) NULL
, "nop", "");
1726 p
= frag_var (rs_machine_dependent
, 4, 0,
1727 RELAX_ENCODE (0, 4, -8, 0, 0, mips_warn_about_macros
),
1728 ep
->X_add_symbol
, (long) 0, (char *) NULL
);
1729 macro_build (p
, counter
, ep
,
1730 mips_isa
< 3 ? "addiu" : "daddiu",
1731 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
1732 if (ex
.X_add_number
!= 0)
1734 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
1735 as_bad ("PIC code offset overflow (max 16 signed bits)");
1736 ex
.X_op
= O_constant
;
1737 macro_build (p
, counter
, &ex
,
1738 mips_isa
< 3 ? "addiu" : "daddiu",
1739 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
1742 else if (mips_pic
== EMBEDDED_PIC
)
1745 addiu $reg,$gp,<sym> (BFD_RELOC_MIPS_GPREL)
1747 macro_build ((char *) NULL
, counter
, ep
,
1748 mips_isa
< 3 ? "addiu" : "daddiu",
1749 "t,r,j", reg
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
1757 * This routine implements the seemingly endless macro or synthesized
1758 * instructions and addressing modes in the mips assembly language. Many
1759 * of these macros are simple and are similar to each other. These could
1760 * probably be handled by some kind of table or grammer aproach instead of
1761 * this verbose method. Others are not simple macros but are more like
1762 * optimizing code generation.
1763 * One interesting optimization is when several store macros appear
1764 * consecutivly that would load AT with the upper half of the same address.
1765 * The ensuing load upper instructions are ommited. This implies some kind
1766 * of global optimization. We currently only optimize within a single macro.
1767 * For many of the load and store macros if the address is specified as a
1768 * constant expression in the first 64k of memory (ie ld $2,0x4000c) we
1769 * first load register 'at' with zero and use it as the base register. The
1770 * mips assembler simply uses register $zero. Just one tiny optimization
1775 struct mips_cl_insn
*ip
;
1777 register int treg
, sreg
, dreg
, breg
;
1790 bfd_reloc_code_real_type r
;
1792 int hold_mips_optimize
;
1794 treg
= (ip
->insn_opcode
>> 16) & 0x1f;
1795 dreg
= (ip
->insn_opcode
>> 11) & 0x1f;
1796 sreg
= breg
= (ip
->insn_opcode
>> 21) & 0x1f;
1797 mask
= ip
->insn_mo
->mask
;
1799 expr1
.X_op
= O_constant
;
1800 expr1
.X_op_symbol
= NULL
;
1801 expr1
.X_add_symbol
= NULL
;
1802 expr1
.X_add_number
= 1;
1814 mips_emit_delays ();
1816 mips_any_noreorder
= 1;
1818 expr1
.X_add_number
= 8;
1819 macro_build ((char *) NULL
, &icnt
, &expr1
, "bgez", "s,p", sreg
);
1821 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
1823 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
, sreg
, 0);
1824 macro_build ((char *) NULL
, &icnt
, NULL
,
1825 dbl
? "dsub" : "sub",
1826 "d,v,t", dreg
, 0, sreg
);
1849 if (imm_expr
.X_add_number
>= -0x8000 && imm_expr
.X_add_number
< 0x8000)
1851 macro_build ((char *) NULL
, &icnt
, &imm_expr
, s
, "t,r,j", treg
, sreg
,
1852 (int) BFD_RELOC_LO16
);
1855 load_register (&icnt
, AT
, &imm_expr
);
1856 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "d,v,t", treg
, sreg
, AT
);
1875 if (imm_expr
.X_add_number
>= 0 && imm_expr
.X_add_number
< 0x10000)
1877 if (mask
!= M_NOR_I
)
1878 macro_build ((char *) NULL
, &icnt
, &imm_expr
, s
, "t,r,i", treg
,
1879 sreg
, (int) BFD_RELOC_LO16
);
1882 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "ori", "t,r,i",
1883 treg
, sreg
, (int) BFD_RELOC_LO16
);
1884 macro_build ((char *) NULL
, &icnt
, NULL
, "nor", "d,v,t",
1890 load_register (&icnt
, AT
, &imm_expr
);
1891 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "d,v,t", treg
, sreg
, AT
);
1908 if (imm_expr
.X_add_number
== 0)
1910 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "s,t,p", sreg
,
1914 load_register (&icnt
, AT
, &imm_expr
);
1915 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "s,t,p", sreg
, AT
);
1923 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
1924 likely
? "bgezl" : "bgez",
1930 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
1931 likely
? "blezl" : "blez",
1935 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", AT
, sreg
, treg
);
1936 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
1937 likely
? "beql" : "beq",
1944 /* check for > max integer */
1945 maxnum
= 0x7fffffff;
1953 if (imm_expr
.X_add_number
>= maxnum
1954 && (mips_isa
< 3 || sizeof (maxnum
) > 4))
1957 /* result is always false */
1960 as_warn ("Branch %s is always false (nop)", ip
->insn_mo
->name
);
1961 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
1965 as_warn ("Branch likely %s is always false", ip
->insn_mo
->name
);
1966 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "bnel",
1971 imm_expr
.X_add_number
++;
1975 if (mask
== M_BGEL_I
)
1977 if (imm_expr
.X_add_number
== 0)
1979 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
1980 likely
? "bgezl" : "bgez",
1984 if (imm_expr
.X_add_number
== 1)
1986 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
1987 likely
? "bgtzl" : "bgtz",
1991 maxnum
= 0x7fffffff;
1999 maxnum
= - maxnum
- 1;
2000 if (imm_expr
.X_add_number
<= maxnum
2001 && (mips_isa
< 3 || sizeof (maxnum
) > 4))
2004 /* result is always true */
2005 as_warn ("Branch %s is always true", ip
->insn_mo
->name
);
2006 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "b", "p");
2009 set_at (&icnt
, sreg
, 0);
2010 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2011 likely
? "beql" : "beq",
2022 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2023 likely
? "beql" : "beq",
2027 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", AT
, sreg
,
2029 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2030 likely
? "beql" : "beq",
2037 if (sreg
== 0 || imm_expr
.X_add_number
== -1)
2039 imm_expr
.X_add_number
++;
2043 if (mask
== M_BGEUL_I
)
2045 if (imm_expr
.X_add_number
== 0)
2047 if (imm_expr
.X_add_number
== 1)
2049 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2050 likely
? "bnel" : "bne",
2054 set_at (&icnt
, sreg
, 1);
2055 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2056 likely
? "beql" : "beq",
2065 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2066 likely
? "bgtzl" : "bgtz",
2072 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2073 likely
? "bltzl" : "bltz",
2077 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", AT
, treg
, sreg
);
2078 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2079 likely
? "bnel" : "bne",
2088 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2089 likely
? "bnel" : "bne",
2095 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", AT
, treg
,
2097 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2098 likely
? "bnel" : "bne",
2107 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2108 likely
? "blezl" : "blez",
2114 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2115 likely
? "bgezl" : "bgez",
2119 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", AT
, treg
, sreg
);
2120 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2121 likely
? "beql" : "beq",
2128 maxnum
= 0x7fffffff;
2136 if (imm_expr
.X_add_number
>= maxnum
2137 && (mips_isa
< 3 || sizeof (maxnum
) > 4))
2139 imm_expr
.X_add_number
++;
2143 if (mask
== M_BLTL_I
)
2145 if (imm_expr
.X_add_number
== 0)
2147 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2148 likely
? "bltzl" : "bltz",
2152 if (imm_expr
.X_add_number
== 1)
2154 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2155 likely
? "blezl" : "blez",
2159 set_at (&icnt
, sreg
, 0);
2160 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2161 likely
? "bnel" : "bne",
2170 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2171 likely
? "beql" : "beq",
2177 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", AT
, treg
,
2179 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2180 likely
? "beql" : "beq",
2187 if (sreg
== 0 || imm_expr
.X_add_number
== -1)
2189 imm_expr
.X_add_number
++;
2193 if (mask
== M_BLTUL_I
)
2195 if (imm_expr
.X_add_number
== 0)
2197 if (imm_expr
.X_add_number
== 1)
2199 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2200 likely
? "beql" : "beq",
2204 set_at (&icnt
, sreg
, 1);
2205 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2206 likely
? "bnel" : "bne",
2215 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2216 likely
? "bltzl" : "bltz",
2222 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2223 likely
? "bgtzl" : "bgtz",
2227 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", AT
, sreg
, treg
);
2228 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2229 likely
? "bnel" : "bne",
2240 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2241 likely
? "bnel" : "bne",
2245 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", AT
, sreg
,
2247 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2248 likely
? "bnel" : "bne",
2264 as_warn ("Divide by zero.");
2266 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", 0, 0);
2268 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 7);
2272 mips_emit_delays ();
2274 mips_any_noreorder
= 1;
2275 macro_build ((char *) NULL
, &icnt
, NULL
,
2276 dbl
? "ddiv" : "div",
2277 "z,s,t", sreg
, treg
);
2279 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", treg
, 0);
2282 expr1
.X_add_number
= 8;
2283 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", treg
, 0);
2284 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
2285 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 7);
2287 expr1
.X_add_number
= -1;
2288 macro_build ((char *) NULL
, &icnt
, &expr1
,
2289 dbl
? "daddiu" : "addiu",
2290 "t,r,j", AT
, 0, (int) BFD_RELOC_LO16
);
2291 expr1
.X_add_number
= mips_trap
? (dbl
? 12 : 8) : (dbl
? 20 : 16);
2292 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", treg
, AT
);
2295 expr1
.X_add_number
= 1;
2296 macro_build ((char *) NULL
, &icnt
, &expr1
, "daddiu", "t,r,j", AT
, 0,
2297 (int) BFD_RELOC_LO16
);
2298 macro_build ((char *) NULL
, &icnt
, NULL
, "dsll32", "d,w,<", AT
, AT
,
2303 expr1
.X_add_number
= 0x80000000;
2304 macro_build ((char *) NULL
, &icnt
, &expr1
, "lui", "t,u", AT
,
2305 (int) BFD_RELOC_HI16
);
2308 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", sreg
, AT
);
2311 expr1
.X_add_number
= 8;
2312 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", sreg
, AT
);
2313 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
2314 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 6);
2317 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d", dreg
);
2356 if (imm_expr
.X_add_number
== 0)
2358 as_warn ("Divide by zero.");
2360 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", 0, 0);
2362 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 7);
2365 if (imm_expr
.X_add_number
== 1)
2367 if (strcmp (s2
, "mflo") == 0)
2368 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
,
2371 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
, 0);
2374 if (imm_expr
.X_add_number
== -1
2375 && s
[strlen (s
) - 1] != 'u')
2377 if (strcmp (s2
, "mflo") == 0)
2380 macro_build ((char *) NULL
, &icnt
, NULL
, "dneg", "d,w", dreg
,
2383 macro_build ((char *) NULL
, &icnt
, NULL
, "neg", "d,w", dreg
,
2387 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
, 0);
2391 load_register (&icnt
, AT
, &imm_expr
);
2392 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "z,s,t", sreg
, AT
);
2393 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "d", dreg
);
2412 mips_emit_delays ();
2414 mips_any_noreorder
= 1;
2415 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "z,s,t", sreg
, treg
);
2417 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", treg
, 0);
2420 expr1
.X_add_number
= 8;
2421 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", treg
, 0);
2422 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
2423 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 7);
2426 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "d", dreg
);
2430 /* Load the address of a symbol into a register. If breg is not
2431 zero, we then add a base register to it. */
2433 /* When generating embedded PIC code, we permit expressions of
2436 where bar is an address in the .text section. These are used
2437 when getting the addresses of functions. We don't permit
2438 X_add_number to be non-zero, because if the symbol is
2439 external the relaxing code needs to know that any addend is
2440 purely the offset to X_op_symbol. */
2441 if (mips_pic
== EMBEDDED_PIC
2442 && offset_expr
.X_op
== O_subtract
2443 && now_seg
== text_section
2444 && S_GET_SEGMENT (offset_expr
.X_op_symbol
) == text_section
2446 && offset_expr
.X_add_number
== 0)
2448 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
2449 treg
, (int) BFD_RELOC_PCREL_HI16_S
);
2450 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2451 mips_isa
< 3 ? "addiu" : "daddiu",
2452 "t,r,j", treg
, treg
, (int) BFD_RELOC_PCREL_LO16
);
2456 if (offset_expr
.X_op
!= O_symbol
2457 && offset_expr
.X_op
!= O_constant
)
2459 as_bad ("expression too complex");
2460 offset_expr
.X_op
= O_constant
;
2474 if (offset_expr
.X_op
== O_constant
)
2475 load_register (&icnt
, tempreg
, &offset_expr
);
2476 else if (mips_pic
== NO_PIC
)
2478 /* If this is a reference to an GP relative symbol, we want
2479 addiu $tempreg,$gp,<sym> (BFD_RELOC_MIPS_GPREL)
2481 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
2482 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
2483 If we have a constant, we need two instructions anyhow,
2484 so we may as well always use the latter form. */
2485 if (offset_expr
.X_add_number
!= 0)
2490 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2491 mips_isa
< 3 ? "addiu" : "daddiu",
2492 "t,r,j", tempreg
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
2493 p
= frag_var (rs_machine_dependent
, 8, 0,
2494 RELAX_ENCODE (4, 8, 0, 4, 0,
2495 mips_warn_about_macros
),
2496 offset_expr
.X_add_symbol
, (long) 0,
2499 macro_build_lui (p
, &icnt
, &offset_expr
, tempreg
);
2502 macro_build (p
, &icnt
, &offset_expr
,
2503 mips_isa
< 3 ? "addiu" : "daddiu",
2504 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
2506 else if (mips_pic
== SVR4_PIC
)
2508 /* If this is a reference to an external symbol, and there
2509 is no constant, we want
2510 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
2511 For a local symbol, we want
2512 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
2514 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
2516 If we have a small constant, and this is a reference to
2517 an external symbol, we want
2518 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
2520 addiu $tempreg,$tempreg,<constant>
2521 For a local symbol, we want the same instruction
2522 sequence, but we output a BFD_RELOC_LO16 reloc on the
2525 If we have a large constant, and this is a reference to
2526 an external symbol, we want
2527 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
2528 lui $at,<hiconstant>
2529 addiu $at,$at,<loconstant>
2530 addu $tempreg,$tempreg,$at
2531 For a local symbol, we want the same instruction
2532 sequence, but we output a BFD_RELOC_LO16 reloc on the
2533 addiu instruction. */
2534 expr1
.X_add_number
= offset_expr
.X_add_number
;
2535 offset_expr
.X_add_number
= 0;
2537 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2538 mips_isa
< 3 ? "lw" : "ld",
2539 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
2540 if (expr1
.X_add_number
== 0)
2548 /* We're going to put in an addu instruction using
2549 tempreg, so we may as well insert the nop right
2551 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
2555 p
= frag_var (rs_machine_dependent
, 8 - off
, 0,
2556 RELAX_ENCODE (0, 8 - off
, -4 - off
, 4 - off
, 0,
2558 ? mips_warn_about_macros
2560 offset_expr
.X_add_symbol
, (long) 0,
2564 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
2567 macro_build (p
, &icnt
, &expr1
,
2568 mips_isa
< 3 ? "addiu" : "daddiu",
2569 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
2570 /* FIXME: If breg == 0, and the next instruction uses
2571 $tempreg, then if this variant case is used an extra
2572 nop will be generated. */
2574 else if (expr1
.X_add_number
>= -0x8000
2575 && expr1
.X_add_number
< 0x8000)
2577 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
2579 macro_build ((char *) NULL
, &icnt
, &expr1
,
2580 mips_isa
< 3 ? "addiu" : "daddiu",
2581 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
2582 (void) frag_var (rs_machine_dependent
, 0, 0,
2583 RELAX_ENCODE (0, 0, -12, -4, 0, 0),
2584 offset_expr
.X_add_symbol
, (long) 0,
2591 /* If we are going to add in a base register, and the
2592 target register and the base register are the same,
2593 then we are using AT as a temporary register. Since
2594 we want to load the constant into AT, we add our
2595 current AT (from the global offset table) and the
2596 register into the register now, and pretend we were
2597 not using a base register. */
2602 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
2604 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
2605 mips_isa
< 3 ? "addu" : "daddu",
2606 "d,v,t", treg
, AT
, breg
);
2612 /* Set mips_optimize around the lui instruction to avoid
2613 inserting an unnecessary nop after the lw. */
2614 hold_mips_optimize
= mips_optimize
;
2616 macro_build_lui ((char *) NULL
, &icnt
, &expr1
, AT
);
2617 mips_optimize
= hold_mips_optimize
;
2619 macro_build ((char *) NULL
, &icnt
, &expr1
,
2620 mips_isa
< 3 ? "addiu" : "daddiu",
2621 "t,r,j", AT
, AT
, (int) BFD_RELOC_LO16
);
2622 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
2623 mips_isa
< 3 ? "addu" : "daddu",
2624 "d,v,t", tempreg
, tempreg
, AT
);
2625 (void) frag_var (rs_machine_dependent
, 0, 0,
2626 RELAX_ENCODE (0, 0, -16 + off1
, -8, 0, 0),
2627 offset_expr
.X_add_symbol
, (long) 0,
2632 else if (mips_pic
== EMBEDDED_PIC
)
2635 addiu $tempreg,$gp,<sym> (BFD_RELOC_MIPS_GPREL)
2637 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2638 mips_isa
< 3 ? "addiu" : "daddiu",
2639 "t,r,j", tempreg
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
2645 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
2646 mips_isa
< 3 ? "addu" : "daddu",
2647 "d,v,t", treg
, tempreg
, breg
);
2655 /* The j instruction may not be used in PIC code, since it
2656 requires an absolute address. We convert it to a b
2658 if (mips_pic
== NO_PIC
)
2659 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "j", "a");
2661 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "b", "p");
2664 /* The jal instructions must be handled as macros because when
2665 generating PIC code they expand to multi-instruction
2666 sequences. Normally they are simple instructions. */
2671 if (mips_pic
== NO_PIC
2672 || mips_pic
== EMBEDDED_PIC
)
2673 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "jalr",
2675 else if (mips_pic
== SVR4_PIC
)
2677 if (sreg
!= PIC_CALL_REG
)
2678 as_warn ("MIPS PIC call to register other than $25");
2680 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "jalr",
2682 if (mips_cprestore_offset
< 0)
2683 as_warn ("No .cprestore pseudo-op used in PIC code");
2686 expr1
.X_add_number
= mips_cprestore_offset
;
2687 macro_build ((char *) NULL
, &icnt
, &expr1
,
2688 mips_isa
< 3 ? "lw" : "ld",
2689 "t,o(b)", GP
, (int) BFD_RELOC_LO16
, mips_frame_reg
);
2698 if (mips_pic
== NO_PIC
)
2699 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "jal", "a");
2700 else if (mips_pic
== SVR4_PIC
)
2702 /* If this is a reference to an external symbol, we want
2703 lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
2707 lw $gp,cprestore($sp)
2708 The cprestore value is set using the .cprestore
2709 pseudo-op. If the symbol is not external, we want
2710 lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
2712 addiu $25,$25,<sym> (BFD_RELOC_LO16)
2715 lw $gp,cprestore($sp)
2718 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2719 mips_isa
< 3 ? "lw" : "ld",
2720 "t,o(b)", PIC_CALL_REG
,
2721 (int) BFD_RELOC_MIPS_CALL16
, GP
);
2722 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
2723 p
= frag_var (rs_machine_dependent
, 4, 0,
2724 RELAX_ENCODE (0, 4, -8, 0, 0, 0),
2725 offset_expr
.X_add_symbol
, (long) 0, (char *) NULL
);
2726 macro_build (p
, &icnt
, &offset_expr
,
2727 mips_isa
< 3 ? "addiu" : "daddiu",
2728 "t,r,j", PIC_CALL_REG
, PIC_CALL_REG
,
2729 (int) BFD_RELOC_LO16
);
2730 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
2731 "jalr", "s", PIC_CALL_REG
);
2732 if (mips_cprestore_offset
< 0)
2733 as_warn ("No .cprestore pseudo-op used in PIC code");
2737 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
2739 expr1
.X_add_number
= mips_cprestore_offset
;
2740 macro_build ((char *) NULL
, &icnt
, &expr1
,
2741 mips_isa
< 3 ? "lw" : "ld",
2742 "t,o(b)", GP
, (int) BFD_RELOC_LO16
,
2746 else if (mips_pic
== EMBEDDED_PIC
)
2748 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "bal", "p");
2749 /* The linker may expand the call to a longer sequence which
2750 uses $at, so we must break rather than return. */
2822 if (breg
== treg
|| coproc
)
2891 if (mask
== M_LWC1_AB
2892 || mask
== M_SWC1_AB
2893 || mask
== M_LDC1_AB
2894 || mask
== M_SDC1_AB
2903 if (offset_expr
.X_op
!= O_constant
2904 && offset_expr
.X_op
!= O_symbol
)
2906 as_bad ("expression too complex");
2907 offset_expr
.X_op
= O_constant
;
2910 /* A constant expression in PIC code can be handled just as it
2911 is in non PIC code. */
2912 if (mips_pic
== NO_PIC
2913 || offset_expr
.X_op
== O_constant
)
2915 /* If this is a reference to a GP relative symbol, and there
2916 is no base register, we want
2917 <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL)
2918 Otherwise, if there is no base register, we want
2919 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
2920 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
2921 If we have a constant, we need two instructions anyhow,
2922 so we always use the latter form.
2924 If we have a base register, and this is a reference to a
2925 GP relative symbol, we want
2926 addu $tempreg,$breg,$gp
2927 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GPREL)
2929 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
2930 addu $tempreg,$tempreg,$breg
2931 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
2932 With a constant we always use the latter case. */
2935 if (offset_expr
.X_add_number
!= 0)
2940 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
2941 treg
, (int) BFD_RELOC_MIPS_GPREL
, GP
);
2942 p
= frag_var (rs_machine_dependent
, 8, 0,
2943 RELAX_ENCODE (4, 8, 0, 4, 0,
2944 (mips_warn_about_macros
2945 || (used_at
&& mips_noat
))),
2946 offset_expr
.X_add_symbol
, (long) 0,
2950 macro_build_lui (p
, &icnt
, &offset_expr
, tempreg
);
2953 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
, treg
,
2954 (int) BFD_RELOC_LO16
, tempreg
);
2958 if (offset_expr
.X_add_number
!= 0)
2963 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
2964 mips_isa
< 3 ? "addu" : "daddu",
2965 "d,v,t", tempreg
, breg
, GP
);
2966 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
2967 treg
, (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
2968 p
= frag_var (rs_machine_dependent
, 12, 0,
2969 RELAX_ENCODE (8, 12, 0, 8, 0, 0),
2970 offset_expr
.X_add_symbol
, (long) 0,
2973 macro_build_lui (p
, &icnt
, &offset_expr
, tempreg
);
2976 macro_build (p
, &icnt
, (expressionS
*) NULL
,
2977 mips_isa
< 3 ? "addu" : "daddu",
2978 "d,v,t", tempreg
, tempreg
, breg
);
2981 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
, treg
,
2982 (int) BFD_RELOC_LO16
, tempreg
);
2985 else if (mips_pic
== SVR4_PIC
)
2987 /* If this is a reference to an external symbol, we want
2988 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
2990 <op> $treg,0($tempreg)
2992 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
2994 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
2995 <op> $treg,0($tempreg)
2996 If there is a base register, we add it to $tempreg before
2997 the <op>. If there is a constant, we stick it in the
2998 <op> instruction. We don't handle constants larger than
2999 16 bits, because we have no way to load the upper 16 bits
3000 (actually, we could handle them for the subset of cases
3001 in which we are not using $at). */
3002 assert (offset_expr
.X_op
== O_symbol
);
3003 expr1
.X_add_number
= offset_expr
.X_add_number
;
3004 offset_expr
.X_add_number
= 0;
3005 if (expr1
.X_add_number
< -0x8000
3006 || expr1
.X_add_number
>= 0x8000)
3007 as_bad ("PIC code offset overflow (max 16 signed bits)");
3009 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3010 mips_isa
< 3 ? "lw" : "ld",
3011 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
3012 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
3013 p
= frag_var (rs_machine_dependent
, 4, 0,
3014 RELAX_ENCODE (0, 4, -8, 0, 0, 0),
3015 offset_expr
.X_add_symbol
, (long) 0,
3017 macro_build (p
, &icnt
, &offset_expr
,
3018 mips_isa
< 3 ? "addiu" : "daddiu",
3019 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
3021 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3022 mips_isa
< 3 ? "addu" : "daddu",
3023 "d,v,t", tempreg
, tempreg
, breg
);
3024 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
, treg
,
3025 (int) BFD_RELOC_LO16
, tempreg
);
3027 else if (mips_pic
== EMBEDDED_PIC
)
3029 /* If there is no base register, we want
3030 <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL)
3031 If there is a base register, we want
3032 addu $tempreg,$breg,$gp
3033 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GPREL)
3035 assert (offset_expr
.X_op
== O_symbol
);
3038 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
3039 treg
, (int) BFD_RELOC_MIPS_GPREL
, GP
);
3044 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3045 mips_isa
< 3 ? "addu" : "daddu",
3046 "d,v,t", tempreg
, breg
, GP
);
3047 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
3048 treg
, (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
3061 load_register (&icnt
, treg
, &imm_expr
);
3065 if (imm_expr
.X_op
== O_constant
)
3067 load_register (&icnt
, AT
, &imm_expr
);
3068 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3069 "mtc1", "t,G", AT
, treg
);
3074 assert (offset_expr
.X_op
== O_symbol
3075 && strcmp (segment_name (S_GET_SEGMENT
3076 (offset_expr
.X_add_symbol
)),
3078 && offset_expr
.X_add_number
== 0);
3079 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lwc1", "T,o(b)",
3080 treg
, (int) BFD_RELOC_MIPS_LITERAL
, GP
);
3085 /* We know that sym is in the .rdata section. First we get the
3086 upper 16 bits of the address. */
3087 if (mips_pic
== NO_PIC
)
3089 /* FIXME: This won't work for a 64 bit address. */
3090 macro_build_lui ((char *) NULL
, &icnt
, &offset_expr
, AT
);
3092 else if (mips_pic
== SVR4_PIC
)
3094 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3095 mips_isa
< 3 ? "lw" : "ld",
3096 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
3098 else if (mips_pic
== EMBEDDED_PIC
)
3100 /* For embedded PIC we pick up the entire address off $gp in
3101 a single instruction. */
3102 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3103 mips_isa
< 3 ? "addiu" : "daddiu",
3104 "t,r,j", AT
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
3105 offset_expr
.X_op
= O_constant
;
3106 offset_expr
.X_add_number
= 0;
3111 /* Now we load the register(s). */
3113 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "ld", "t,o(b)",
3114 treg
, (int) BFD_RELOC_LO16
, AT
);
3117 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lw", "t,o(b)",
3118 treg
, (int) BFD_RELOC_LO16
, AT
);
3121 /* FIXME: How in the world do we deal with the possible
3123 offset_expr
.X_add_number
+= 4;
3124 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lw", "t,o(b)",
3125 treg
+ 1, (int) BFD_RELOC_LO16
, AT
);
3129 /* To avoid confusion in tc_gen_reloc, we must ensure that this
3130 does not become a variant frag. */
3131 frag_wane (frag_now
);
3137 assert (offset_expr
.X_op
== O_symbol
3138 && offset_expr
.X_add_number
== 0);
3139 s
= segment_name (S_GET_SEGMENT (offset_expr
.X_add_symbol
));
3140 if (strcmp (s
, ".lit8") == 0)
3144 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "ldc1",
3145 "T,o(b)", treg
, (int) BFD_RELOC_MIPS_LITERAL
, GP
);
3149 r
= BFD_RELOC_MIPS_LITERAL
;
3154 assert (strcmp (s
, RDATA_SECTION_NAME
) == 0);
3155 if (mips_pic
== SVR4_PIC
)
3156 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3157 mips_isa
< 3 ? "lw" : "ld",
3158 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
3161 /* FIXME: This won't work for a 64 bit address. */
3162 macro_build_lui ((char *) NULL
, &icnt
, &offset_expr
, AT
);
3167 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "ldc1",
3168 "T,o(b)", treg
, (int) BFD_RELOC_LO16
, AT
);
3170 /* To avoid confusion in tc_gen_reloc, we must ensure
3171 that this does not become a variant frag. */
3172 frag_wane (frag_now
);
3183 /* Even on a big endian machine $fn comes before $fn+1. We have
3184 to adjust when loading from memory. */
3187 assert (mips_isa
< 2);
3188 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lwc1", "T,o(b)",
3189 byte_order
== LITTLE_ENDIAN
? treg
: treg
+ 1,
3191 /* FIXME: A possible overflow which I don't know how to deal
3193 offset_expr
.X_add_number
+= 4;
3194 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lwc1", "T,o(b)",
3195 byte_order
== LITTLE_ENDIAN
? treg
+ 1 : treg
,
3198 /* To avoid confusion in tc_gen_reloc, we must ensure that this
3199 does not become a variant frag. */
3200 frag_wane (frag_now
);
3209 * The MIPS assembler seems to check for X_add_number not
3210 * being double aligned and generating:
3213 * addiu at,at,%lo(foo+1)
3216 * But, the resulting address is the same after relocation so why
3217 * generate the extra instruction?
3264 if (offset_expr
.X_op
!= O_symbol
3265 && offset_expr
.X_op
!= O_constant
)
3267 as_bad ("expression too complex");
3268 offset_expr
.X_op
= O_constant
;
3271 /* Even on a big endian machine $fn comes before $fn+1. We have
3272 to adjust when loading from memory. We set coproc if we must
3273 load $fn+1 first. */
3274 if (byte_order
== LITTLE_ENDIAN
)
3277 if (mips_pic
== NO_PIC
3278 || offset_expr
.X_op
== O_constant
)
3280 /* If this is a reference to a GP relative symbol, we want
3281 <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL)
3282 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_MIPS_GPREL)
3283 If we have a base register, we use this
3285 <op> $treg,<sym>($at) (BFD_RELOC_MIPS_GPREL)
3286 <op> $treg+1,<sym>+4($at) (BFD_RELOC_MIPS_GPREL)
3287 If this is not a GP relative symbol, we want
3288 lui $at,<sym> (BFD_RELOC_HI16_S)
3289 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
3290 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
3291 If there is a base register, we add it to $at after the
3292 lui instruction. If there is a constant, we always use
3294 if (offset_expr
.X_add_number
!= 0)
3313 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3314 mips_isa
< 3 ? "addu" : "daddu",
3315 "d,v,t", AT
, breg
, GP
);
3321 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
3322 coproc
? treg
+ 1 : treg
,
3323 (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
3324 offset_expr
.X_add_number
+= 4;
3326 /* Set mips_optimize to 2 to avoid inserting an
3328 hold_mips_optimize
= mips_optimize
;
3330 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
3331 coproc
? treg
: treg
+ 1,
3332 (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
3333 mips_optimize
= hold_mips_optimize
;
3335 p
= frag_var (rs_machine_dependent
, 12 + off
, 0,
3336 RELAX_ENCODE (8 + off
, 12 + off
, 0, 4 + off
, 1,
3337 used_at
&& mips_noat
),
3338 offset_expr
.X_add_symbol
, (long) 0,
3341 /* We just generated two relocs. When tc_gen_reloc
3342 handles this case, it will skip the first reloc and
3343 handle the second. The second reloc already has an
3344 extra addend of 4, which we added above. We must
3345 subtract it out, and then subtract another 4 to make
3346 the first reloc come out right. The second reloc
3347 will come out right because we are going to add 4 to
3348 offset_expr when we build its instruction below. */
3349 offset_expr
.X_add_number
-= 8;
3350 offset_expr
.X_op
= O_constant
;
3352 macro_build_lui (p
, &icnt
, &offset_expr
, AT
);
3357 macro_build (p
, &icnt
, (expressionS
*) NULL
,
3358 mips_isa
< 3 ? "addu" : "daddu",
3359 "d,v,t", AT
, breg
, AT
);
3363 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
,
3364 coproc
? treg
+ 1 : treg
,
3365 (int) BFD_RELOC_LO16
, AT
);
3368 /* FIXME: How do we handle overflow here? */
3369 offset_expr
.X_add_number
+= 4;
3370 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
,
3371 coproc
? treg
: treg
+ 1,
3372 (int) BFD_RELOC_LO16
, AT
);
3374 else if (mips_pic
== SVR4_PIC
)
3378 /* If this is a reference to an external symbol, we want
3379 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3384 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3386 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
3387 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
3388 If there is a base register we add it to $at before the
3389 lwc1 instructions. If there is a constant we include it
3390 in the lwc1 instructions. */
3392 expr1
.X_add_number
= offset_expr
.X_add_number
;
3393 offset_expr
.X_add_number
= 0;
3394 if (expr1
.X_add_number
< -0x8000
3395 || expr1
.X_add_number
>= 0x8000 - 4)
3396 as_bad ("PIC code offset overflow (max 16 signed bits)");
3401 frag_grow (24 + off
);
3402 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3403 mips_isa
< 3 ? "lw" : "ld",
3404 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
3405 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
3407 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3408 mips_isa
< 3 ? "addu" : "daddu",
3409 "d,v,t", AT
, breg
, AT
);
3410 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
3411 coproc
? treg
+ 1 : treg
,
3412 (int) BFD_RELOC_LO16
, AT
);
3413 expr1
.X_add_number
+= 4;
3415 /* Set mips_optimize to 2 to avoid inserting an undesired
3417 hold_mips_optimize
= mips_optimize
;
3419 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
3420 coproc
? treg
: treg
+ 1,
3421 (int) BFD_RELOC_LO16
, AT
);
3422 mips_optimize
= hold_mips_optimize
;
3424 (void) frag_var (rs_machine_dependent
, 0, 0,
3425 RELAX_ENCODE (0, 0, -16 - off
, -8, 1, 0),
3426 offset_expr
.X_add_symbol
, (long) 0,
3429 else if (mips_pic
== EMBEDDED_PIC
)
3431 /* If there is no base register, we use
3432 <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL)
3433 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_MIPS_GPREL)
3434 If we have a base register, we use
3436 <op> $treg,<sym>($at) (BFD_RELOC_MIPS_GPREL)
3437 <op> $treg+1,<sym>+4($at) (BFD_RELOC_MIPS_GPREL)
3446 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3447 mips_isa
< 3 ? "addu" : "daddu",
3448 "d,v,t", AT
, breg
, GP
);
3453 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
3454 coproc
? treg
+ 1 : treg
,
3455 (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
3456 offset_expr
.X_add_number
+= 4;
3457 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
3458 coproc
? treg
: treg
+ 1,
3459 (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
3475 assert (mips_isa
< 3);
3476 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
3477 (int) BFD_RELOC_LO16
, breg
);
3478 offset_expr
.X_add_number
+= 4;
3479 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
+ 1,
3480 (int) BFD_RELOC_LO16
, breg
);
3482 #ifdef LOSING_COMPILER
3488 as_warn ("Macro used $at after \".set noat\"");
3493 struct mips_cl_insn
*ip
;
3495 register int treg
, sreg
, dreg
, breg
;
3508 bfd_reloc_code_real_type r
;
3511 treg
= (ip
->insn_opcode
>> 16) & 0x1f;
3512 dreg
= (ip
->insn_opcode
>> 11) & 0x1f;
3513 sreg
= breg
= (ip
->insn_opcode
>> 21) & 0x1f;
3514 mask
= ip
->insn_mo
->mask
;
3516 expr1
.X_op
= O_constant
;
3517 expr1
.X_op_symbol
= NULL
;
3518 expr1
.X_add_symbol
= NULL
;
3519 expr1
.X_add_number
= 1;
3523 #endif /* LOSING_COMPILER */
3528 macro_build ((char *) NULL
, &icnt
, NULL
,
3529 dbl
? "dmultu" : "multu",
3531 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
3537 /* The MIPS assembler some times generates shifts and adds. I'm
3538 not trying to be that fancy. GCC should do this for us
3540 load_register (&icnt
, AT
, &imm_expr
);
3541 macro_build ((char *) NULL
, &icnt
, NULL
,
3542 dbl
? "dmult" : "mult",
3544 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
3550 mips_emit_delays ();
3552 mips_any_noreorder
= 1;
3553 macro_build ((char *) NULL
, &icnt
, NULL
,
3554 dbl
? "dmult" : "mult",
3556 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
3557 macro_build ((char *) NULL
, &icnt
, NULL
,
3558 dbl
? "dsra32" : "sra",
3559 "d,w,<", dreg
, dreg
, 31);
3560 macro_build ((char *) NULL
, &icnt
, NULL
, "mfhi", "d", AT
);
3562 macro_build ((char *) NULL
, &icnt
, NULL
, "tne", "s,t", dreg
, AT
);
3565 expr1
.X_add_number
= 8;
3566 macro_build ((char *) NULL
, &icnt
, &expr1
, "beq", "s,t,p", dreg
, AT
);
3567 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
3568 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 6);
3571 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
3577 mips_emit_delays ();
3579 mips_any_noreorder
= 1;
3580 macro_build ((char *) NULL
, &icnt
, NULL
,
3581 dbl
? "dmultu" : "multu",
3583 macro_build ((char *) NULL
, &icnt
, NULL
, "mfhi", "d", AT
);
3584 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
3586 macro_build ((char *) NULL
, &icnt
, NULL
, "tne", "s,t", AT
, 0);
3589 expr1
.X_add_number
= 8;
3590 macro_build ((char *) NULL
, &icnt
, &expr1
, "beq", "s,t,p", AT
, 0);
3591 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
3592 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 6);
3598 macro_build ((char *) NULL
, &icnt
, NULL
, "subu", "d,v,t", AT
, 0, treg
);
3599 macro_build ((char *) NULL
, &icnt
, NULL
, "srlv", "d,t,s", AT
, sreg
, AT
);
3600 macro_build ((char *) NULL
, &icnt
, NULL
, "sllv", "d,t,s", dreg
, sreg
,
3602 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
3606 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", AT
, sreg
,
3607 imm_expr
.X_add_number
& 0x1f);
3608 macro_build ((char *) NULL
, &icnt
, NULL
, "srl", "d,w,<", dreg
, sreg
,
3609 (0 - imm_expr
.X_add_number
) & 0x1f);
3610 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
3614 macro_build ((char *) NULL
, &icnt
, NULL
, "subu", "d,v,t", AT
, 0, treg
);
3615 macro_build ((char *) NULL
, &icnt
, NULL
, "sllv", "d,t,s", AT
, sreg
, AT
);
3616 macro_build ((char *) NULL
, &icnt
, NULL
, "srlv", "d,t,s", dreg
, sreg
,
3618 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
3622 macro_build ((char *) NULL
, &icnt
, NULL
, "srl", "d,w,<", AT
, sreg
,
3623 imm_expr
.X_add_number
& 0x1f);
3624 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", dreg
, sreg
,
3625 (0 - imm_expr
.X_add_number
) & 0x1f);
3626 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
3630 assert (mips_isa
< 2);
3631 /* Even on a big endian machine $fn comes before $fn+1. We have
3632 to adjust when storing to memory. */
3633 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "swc1", "T,o(b)",
3634 byte_order
== LITTLE_ENDIAN
? treg
: treg
+ 1,
3635 (int) BFD_RELOC_LO16
, breg
);
3636 offset_expr
.X_add_number
+= 4;
3637 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "swc1", "T,o(b)",
3638 byte_order
== LITTLE_ENDIAN
? treg
+ 1 : treg
,
3639 (int) BFD_RELOC_LO16
, breg
);
3644 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
3645 treg
, (int) BFD_RELOC_LO16
);
3647 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
3648 sreg
, (int) BFD_RELOC_LO16
);
3651 macro_build ((char *) NULL
, &icnt
, NULL
, "xor", "d,v,t", dreg
,
3653 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
3654 dreg
, (int) BFD_RELOC_LO16
);
3659 if (imm_expr
.X_add_number
== 0)
3661 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
3662 sreg
, (int) BFD_RELOC_LO16
);
3667 as_warn ("Instruction %s: result is always false",
3669 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
, 0);
3672 if (imm_expr
.X_add_number
>= 0 && imm_expr
.X_add_number
< 0x10000)
3674 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "xori", "t,r,i", dreg
,
3675 sreg
, (int) BFD_RELOC_LO16
);
3678 else if (imm_expr
.X_add_number
> -0x8000 && imm_expr
.X_add_number
< 0)
3680 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
3681 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
3682 mips_isa
< 3 ? "addiu" : "daddiu",
3683 "t,r,j", dreg
, sreg
,
3684 (int) BFD_RELOC_LO16
);
3689 load_register (&icnt
, AT
, &imm_expr
);
3690 macro_build ((char *) NULL
, &icnt
, NULL
, "xor", "d,v,t", dreg
,
3694 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
, dreg
,
3695 (int) BFD_RELOC_LO16
);
3700 case M_SGE
: /* sreg >= treg <==> not (sreg < treg) */
3706 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, sreg
, treg
);
3707 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
3708 (int) BFD_RELOC_LO16
);
3711 case M_SGE_I
: /* sreg >= I <==> not (sreg < I) */
3713 if (imm_expr
.X_add_number
>= -0x8000 && imm_expr
.X_add_number
< 0x8000)
3715 macro_build ((char *) NULL
, &icnt
, &expr1
,
3716 mask
== M_SGE_I
? "slti" : "sltiu",
3717 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
3722 load_register (&icnt
, AT
, &imm_expr
);
3723 macro_build ((char *) NULL
, &icnt
, NULL
,
3724 mask
== M_SGE_I
? "slt" : "sltu",
3725 "d,v,t", dreg
, sreg
, AT
);
3728 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
3729 (int) BFD_RELOC_LO16
);
3734 case M_SGT
: /* sreg > treg <==> treg < sreg */
3740 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, treg
, sreg
);
3743 case M_SGT_I
: /* sreg > I <==> I < sreg */
3749 load_register (&icnt
, AT
, &imm_expr
);
3750 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, AT
, sreg
);
3753 case M_SLE
: /* sreg <= treg <==> treg >= sreg <==> not (treg < sreg) */
3759 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, treg
, sreg
);
3760 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
3761 (int) BFD_RELOC_LO16
);
3764 case M_SLE_I
: /* sreg <= I <==> I >= sreg <==> not (I < sreg) */
3770 load_register (&icnt
, AT
, &imm_expr
);
3771 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, AT
, sreg
);
3772 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
3773 (int) BFD_RELOC_LO16
);
3777 if (imm_expr
.X_add_number
>= -0x8000 && imm_expr
.X_add_number
< 0x8000)
3779 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "slti", "t,r,j",
3780 dreg
, sreg
, (int) BFD_RELOC_LO16
);
3783 load_register (&icnt
, AT
, &imm_expr
);
3784 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", dreg
, sreg
, AT
);
3788 if (imm_expr
.X_add_number
>= -0x8000 && imm_expr
.X_add_number
< 0x8000)
3790 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "sltiu", "t,r,j",
3791 dreg
, sreg
, (int) BFD_RELOC_LO16
);
3794 load_register (&icnt
, AT
, &imm_expr
);
3795 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, sreg
,
3801 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0,
3804 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0,
3808 macro_build ((char *) NULL
, &icnt
, NULL
, "xor", "d,v,t", dreg
,
3810 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0,
3816 if (imm_expr
.X_add_number
== 0)
3818 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0,
3824 as_warn ("Instruction %s: result is always true",
3826 macro_build ((char *) NULL
, &icnt
, &expr1
,
3827 mips_isa
< 3 ? "addiu" : "daddiu",
3828 "t,r,j", dreg
, 0, (int) BFD_RELOC_LO16
);
3831 if (imm_expr
.X_add_number
>= 0 && imm_expr
.X_add_number
< 0x10000)
3833 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "xori", "t,r,i",
3834 dreg
, sreg
, (int) BFD_RELOC_LO16
);
3837 else if (imm_expr
.X_add_number
> -0x8000 && imm_expr
.X_add_number
< 0)
3839 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
3840 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
3841 mips_isa
< 3 ? "addiu" : "daddiu",
3842 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
3847 load_register (&icnt
, AT
, &imm_expr
);
3848 macro_build ((char *) NULL
, &icnt
, NULL
, "xor", "d,v,t", dreg
,
3852 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0, dreg
);
3860 if (imm_expr
.X_add_number
> -0x8000 && imm_expr
.X_add_number
<= 0x8000)
3862 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
3863 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
3864 dbl
? "daddi" : "addi",
3865 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
3868 load_register (&icnt
, AT
, &imm_expr
);
3869 macro_build ((char *) NULL
, &icnt
, NULL
,
3870 dbl
? "dsub" : "sub",
3871 "d,v,t", dreg
, sreg
, AT
);
3877 if (imm_expr
.X_add_number
> -0x8000 && imm_expr
.X_add_number
<= 0x8000)
3879 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
3880 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
3881 dbl
? "daddiu" : "addiu",
3882 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
3885 load_register (&icnt
, AT
, &imm_expr
);
3886 macro_build ((char *) NULL
, &icnt
, NULL
,
3887 dbl
? "dsubu" : "subu",
3888 "d,v,t", dreg
, sreg
, AT
);
3909 load_register (&icnt
, AT
, &imm_expr
);
3910 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "s,t", sreg
, AT
);
3915 assert (mips_isa
< 2);
3916 sreg
= (ip
->insn_opcode
>> 11) & 0x1f; /* floating reg */
3917 dreg
= (ip
->insn_opcode
>> 06) & 0x1f; /* floating reg */
3920 * Is the double cfc1 instruction a bug in the mips assembler;
3921 * or is there a reason for it?
3923 mips_emit_delays ();
3925 mips_any_noreorder
= 1;
3926 macro_build ((char *) NULL
, &icnt
, NULL
, "cfc1", "t,G", treg
, 31);
3927 macro_build ((char *) NULL
, &icnt
, NULL
, "cfc1", "t,G", treg
, 31);
3928 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "");
3929 expr1
.X_add_number
= 3;
3930 macro_build ((char *) NULL
, &icnt
, &expr1
, "ori", "t,r,i", AT
, treg
,
3931 (int) BFD_RELOC_LO16
);
3932 expr1
.X_add_number
= 2;
3933 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", AT
, AT
,
3934 (int) BFD_RELOC_LO16
);
3935 macro_build ((char *) NULL
, &icnt
, NULL
, "ctc1", "t,G", AT
, 31);
3936 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "");
3937 macro_build ((char *) NULL
, &icnt
, NULL
,
3938 mask
== M_TRUNCWD
? "cvt.w.d" : "cvt.w.s", "D,S", dreg
, sreg
);
3939 macro_build ((char *) NULL
, &icnt
, NULL
, "ctc1", "t,G", treg
, 31);
3940 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "");
3950 if (offset_expr
.X_add_number
>= 0x7fff)
3951 as_bad ("operand overflow");
3952 /* avoid load delay */
3953 if (byte_order
== LITTLE_ENDIAN
)
3954 offset_expr
.X_add_number
+= 1;
3955 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
3956 (int) BFD_RELOC_LO16
, breg
);
3957 if (byte_order
== LITTLE_ENDIAN
)
3958 offset_expr
.X_add_number
-= 1;
3960 offset_expr
.X_add_number
+= 1;
3961 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lbu", "t,o(b)", AT
,
3962 (int) BFD_RELOC_LO16
, breg
);
3963 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", treg
, treg
, 8);
3964 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", treg
, treg
, AT
);
3968 if (offset_expr
.X_add_number
>= 0x7ffd)
3969 as_bad ("operand overflow");
3970 if (byte_order
== LITTLE_ENDIAN
)
3971 offset_expr
.X_add_number
+= 3;
3972 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lwl", "t,o(b)", treg
,
3973 (int) BFD_RELOC_LO16
, breg
);
3974 if (byte_order
== LITTLE_ENDIAN
)
3975 offset_expr
.X_add_number
-= 3;
3977 offset_expr
.X_add_number
+= 3;
3978 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lwr", "t,o(b)", treg
,
3979 (int) BFD_RELOC_LO16
, breg
);
3985 load_address (&icnt
, AT
, &offset_expr
);
3986 if (mask
== M_ULW_A
)
3988 if (byte_order
== LITTLE_ENDIAN
)
3989 expr1
.X_add_number
= 3;
3991 expr1
.X_add_number
= 0;
3992 macro_build ((char *) NULL
, &icnt
, &expr1
, "lwl", "t,o(b)", treg
,
3993 (int) BFD_RELOC_LO16
, AT
);
3994 if (byte_order
== LITTLE_ENDIAN
)
3995 expr1
.X_add_number
= 0;
3997 expr1
.X_add_number
= 3;
3998 macro_build ((char *) NULL
, &icnt
, &expr1
, "lwr", "t,o(b)", treg
,
3999 (int) BFD_RELOC_LO16
, AT
);
4003 if (byte_order
== BIG_ENDIAN
)
4004 expr1
.X_add_number
= 0;
4005 macro_build ((char *) NULL
, &icnt
, &expr1
,
4006 mask
== M_ULH_A
? "lb" : "lbu", "t,o(b)", treg
,
4007 (int) BFD_RELOC_LO16
, AT
);
4008 if (byte_order
== BIG_ENDIAN
)
4009 expr1
.X_add_number
= 1;
4011 expr1
.X_add_number
= 0;
4012 macro_build ((char *) NULL
, &icnt
, &expr1
, "lbu", "t,o(b)", AT
,
4013 (int) BFD_RELOC_LO16
, AT
);
4014 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", treg
,
4016 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", treg
,
4022 if (offset_expr
.X_add_number
>= 0x7fff)
4023 as_bad ("operand overflow");
4024 if (byte_order
== BIG_ENDIAN
)
4025 offset_expr
.X_add_number
+= 1;
4026 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "sb", "t,o(b)", treg
,
4027 (int) BFD_RELOC_LO16
, breg
);
4028 macro_build ((char *) NULL
, &icnt
, NULL
, "srl", "d,w,<", AT
, treg
, 8);
4029 if (byte_order
== BIG_ENDIAN
)
4030 offset_expr
.X_add_number
-= 1;
4032 offset_expr
.X_add_number
+= 1;
4033 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "sb", "t,o(b)", AT
,
4034 (int) BFD_RELOC_LO16
, breg
);
4038 if (offset_expr
.X_add_number
>= 0x7ffd)
4039 as_bad ("operand overflow");
4040 if (byte_order
== LITTLE_ENDIAN
)
4041 offset_expr
.X_add_number
+= 3;
4042 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "swl", "t,o(b)", treg
,
4043 (int) BFD_RELOC_LO16
, breg
);
4044 if (byte_order
== LITTLE_ENDIAN
)
4045 offset_expr
.X_add_number
-= 3;
4047 offset_expr
.X_add_number
+= 3;
4048 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "swr", "t,o(b)", treg
,
4049 (int) BFD_RELOC_LO16
, breg
);
4054 load_address (&icnt
, AT
, &offset_expr
);
4055 if (mask
== M_USW_A
)
4057 if (byte_order
== LITTLE_ENDIAN
)
4058 expr1
.X_add_number
= 3;
4060 expr1
.X_add_number
= 0;
4061 macro_build ((char *) NULL
, &icnt
, &expr1
, "swl", "t,o(b)", treg
,
4062 (int) BFD_RELOC_LO16
, AT
);
4063 if (byte_order
== LITTLE_ENDIAN
)
4064 expr1
.X_add_number
= 0;
4066 expr1
.X_add_number
= 3;
4067 macro_build ((char *) NULL
, &icnt
, &expr1
, "swr", "t,o(b)", treg
,
4068 (int) BFD_RELOC_LO16
, AT
);
4072 if (byte_order
== LITTLE_ENDIAN
)
4073 expr1
.X_add_number
= 0;
4074 macro_build ((char *) NULL
, &icnt
, &expr1
, "sb", "t,o(b)", treg
,
4075 (int) BFD_RELOC_LO16
, AT
);
4076 macro_build ((char *) NULL
, &icnt
, NULL
, "srl", "d,w,<", treg
,
4078 if (byte_order
== LITTLE_ENDIAN
)
4079 expr1
.X_add_number
= 1;
4081 expr1
.X_add_number
= 0;
4082 macro_build ((char *) NULL
, &icnt
, &expr1
, "sb", "t,o(b)", treg
,
4083 (int) BFD_RELOC_LO16
, AT
);
4084 if (byte_order
== LITTLE_ENDIAN
)
4085 expr1
.X_add_number
= 0;
4087 expr1
.X_add_number
= 1;
4088 macro_build ((char *) NULL
, &icnt
, &expr1
, "lbu", "t,o(b)", AT
,
4089 (int) BFD_RELOC_LO16
, AT
);
4090 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", treg
,
4092 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", treg
,
4098 as_bad ("Macro %s not implemented yet", ip
->insn_mo
->name
);
4102 as_warn ("Macro used $at after \".set noat\"");
4107 This routine assembles an instruction into its binary format. As a side
4108 effect it sets one of the global variables imm_reloc or offset_reloc to the
4109 type of relocation to do if one of the operands is an address expression.
4114 struct mips_cl_insn
*ip
;
4119 struct mips_opcode
*insn
;
4122 unsigned int lastregno
= 0;
4127 for (s
= str
; islower (*s
) || (*s
>= '0' && *s
<= '3') || *s
== '.'; ++s
)
4139 as_fatal ("Unknown opcode: `%s'", str
);
4141 if ((insn
= (struct mips_opcode
*) hash_find (op_hash
, str
)) == NULL
)
4143 as_warn ("`%s' not in hash table.", str
);
4144 insn_error
= "ERROR: Unrecognized opcode";
4152 assert (strcmp (insn
->name
, str
) == 0);
4154 if (insn
->pinfo
== INSN_MACRO
)
4155 insn_isa
= insn
->match
;
4156 else if (insn
->pinfo
& INSN_ISA2
)
4158 else if (insn
->pinfo
& INSN_ISA3
)
4163 if (insn_isa
> mips_isa
)
4165 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
]
4166 && strcmp (insn
->name
, insn
[1].name
) == 0)
4171 as_warn ("Instruction not supported on this processor");
4175 ip
->insn_opcode
= insn
->match
;
4176 for (args
= insn
->args
;; ++args
)
4182 case '\0': /* end of args */
4195 ip
->insn_opcode
|= lastregno
<< 21;
4200 ip
->insn_opcode
|= lastregno
<< 16;
4204 ip
->insn_opcode
|= lastregno
<< 11;
4210 /* handle optional base register.
4211 Either the base register is omitted or
4212 we must have a left paren. */
4213 /* this is dependent on the next operand specifier
4214 is a 'b' for base register */
4215 assert (args
[1] == 'b');
4219 case ')': /* these must match exactly */
4224 case '<': /* must be at least one digit */
4226 * According to the manual, if the shift amount is greater
4227 * than 31 or less than 0 the the shift amount should be
4228 * mod 32. In reality the mips assembler issues an error.
4229 * We issue a warning and mask out all but the low 5 bits.
4231 my_getExpression (&imm_expr
, s
);
4232 check_absolute_expr (ip
, &imm_expr
);
4233 if ((unsigned long) imm_expr
.X_add_number
> 31)
4235 as_warn ("Improper shift amount (%ld)",
4236 (long) imm_expr
.X_add_number
);
4237 imm_expr
.X_add_number
= imm_expr
.X_add_number
& 0x1f;
4239 ip
->insn_opcode
|= imm_expr
.X_add_number
<< 6;
4240 imm_expr
.X_op
= O_absent
;
4244 case '>': /* shift amount minus 32 */
4245 my_getExpression (&imm_expr
, s
);
4246 check_absolute_expr (ip
, &imm_expr
);
4247 if ((unsigned long) imm_expr
.X_add_number
< 32
4248 || (unsigned long) imm_expr
.X_add_number
> 63)
4250 ip
->insn_opcode
|= (imm_expr
.X_add_number
- 32) << 6;
4251 imm_expr
.X_op
= O_absent
;
4255 case 'k': /* cache code */
4256 my_getExpression (&imm_expr
, s
);
4257 check_absolute_expr (ip
, &imm_expr
);
4258 if ((unsigned long) imm_expr
.X_add_number
> 31)
4260 as_warn ("Invalid cahce opcode (%lu)",
4261 (unsigned long) imm_expr
.X_add_number
);
4262 imm_expr
.X_add_number
&= 0x1f;
4264 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_CACHE
;
4265 imm_expr
.X_op
= O_absent
;
4269 case 'c': /* break code */
4270 my_getExpression (&imm_expr
, s
);
4271 check_absolute_expr (ip
, &imm_expr
);
4272 if ((unsigned) imm_expr
.X_add_number
> 1023)
4273 as_warn ("Illegal break code (%ld)",
4274 (long) imm_expr
.X_add_number
);
4275 ip
->insn_opcode
|= imm_expr
.X_add_number
<< 16;
4276 imm_expr
.X_op
= O_absent
;
4280 case 'B': /* syscall code */
4281 my_getExpression (&imm_expr
, s
);
4282 check_absolute_expr (ip
, &imm_expr
);
4283 if ((unsigned) imm_expr
.X_add_number
> 0xfffff)
4284 as_warn ("Illegal syscall code (%ld)",
4285 (long) imm_expr
.X_add_number
);
4286 ip
->insn_opcode
|= imm_expr
.X_add_number
<< 6;
4287 imm_expr
.X_op
= O_absent
;
4291 case 'C': /* Coprocessor code */
4292 my_getExpression (&imm_expr
, s
);
4293 check_absolute_expr (ip
, &imm_expr
);
4294 if ((unsigned long) imm_expr
.X_add_number
>= (1<<25))
4296 as_warn ("Coproccesor code > 25 bits (%ld)",
4297 (long) imm_expr
.X_add_number
);
4298 imm_expr
.X_add_number
&= ((1<<25) - 1);
4300 ip
->insn_opcode
|= imm_expr
.X_add_number
;
4301 imm_expr
.X_op
= O_absent
;
4305 case 'b': /* base register */
4306 case 'd': /* destination register */
4307 case 's': /* source register */
4308 case 't': /* target register */
4309 case 'r': /* both target and source */
4310 case 'v': /* both dest and source */
4311 case 'w': /* both dest and target */
4312 case 'E': /* coprocessor target register */
4313 case 'G': /* coprocessor destination register */
4314 case 'x': /* ignore register name */
4315 case 'z': /* must be zero register */
4329 while (isdigit (*s
));
4331 as_bad ("Invalid register number (%d)", regno
);
4333 else if (*args
== 'E' || *args
== 'G')
4337 if (s
[1] == 'f' && s
[2] == 'p')
4342 else if (s
[1] == 's' && s
[2] == 'p')
4347 else if (s
[1] == 'g' && s
[2] == 'p')
4352 else if (s
[1] == 'a' && s
[2] == 't')
4360 if (regno
== AT
&& ! mips_noat
)
4361 as_warn ("Used $at without \".set noat\"");
4367 if (c
== 'r' || c
== 'v' || c
== 'w')
4374 /* 'z' only matches $0. */
4375 if (c
== 'z' && regno
!= 0)
4383 ip
->insn_opcode
|= regno
<< 21;
4387 ip
->insn_opcode
|= regno
<< 11;
4392 ip
->insn_opcode
|= regno
<< 16;
4395 /* This case exists because on the r3000 trunc
4396 expands into a macro which requires a gp
4397 register. On the r6000 or r4000 it is
4398 assembled into a single instruction which
4399 ignores the register. Thus the insn version
4400 is MIPS_ISA2 and uses 'x', and the macro
4401 version is MIPS_ISA1 and uses 't'. */
4404 /* This case is for the div instruction, which
4405 acts differently if the destination argument
4406 is $0. This only matches $0, and is checked
4407 outside the switch. */
4418 ip
->insn_opcode
|= lastregno
<< 21;
4421 ip
->insn_opcode
|= lastregno
<< 16;
4426 case 'D': /* floating point destination register */
4427 case 'S': /* floating point source register */
4428 case 'T': /* floating point target register */
4432 if (s
[0] == '$' && s
[1] == 'f' && isdigit (s
[2]))
4442 while (isdigit (*s
));
4445 as_bad ("Invalid float register number (%d)", regno
);
4447 if ((regno
& 1) != 0
4449 && ! (strcmp (str
, "mtc1") == 0 ||
4450 strcmp (str
, "mfc1") == 0 ||
4451 strcmp (str
, "lwc1") == 0 ||
4452 strcmp (str
, "swc1") == 0))
4453 as_warn ("Float register should be even, was %d",
4461 if (c
== 'V' || c
== 'W')
4471 ip
->insn_opcode
|= regno
<< 6;
4475 ip
->insn_opcode
|= regno
<< 11;
4479 ip
->insn_opcode
|= regno
<< 16;
4487 ip
->insn_opcode
|= lastregno
<< 11;
4490 ip
->insn_opcode
|= lastregno
<< 16;
4496 my_getExpression (&imm_expr
, s
);
4497 check_absolute_expr (ip
, &imm_expr
);
4502 my_getExpression (&offset_expr
, s
);
4503 imm_reloc
= BFD_RELOC_32
;
4515 unsigned char temp
[8];
4517 unsigned int length
;
4522 /* These only appear as the last operand in an
4523 instruction, and every instruction that accepts
4524 them in any variant accepts them in all variants.
4525 This means we don't have to worry about backing out
4526 any changes if the instruction does not match.
4528 The difference between them is the size of the
4529 floating point constant and where it goes. For 'F'
4530 and 'L' the constant is 64 bits; for 'f' and 'l' it
4531 is 32 bits. Where the constant is placed is based
4532 on how the MIPS assembler does things:
4535 f -- immediate value
4538 The .lit4 and .lit8 sections are only used if
4539 permitted by the -G argument.
4541 When generating embedded PIC code, we use the
4542 .lit8 section but not the .lit4 section (we can do
4543 .lit4 inline easily; we need to put .lit8
4544 somewhere in the data segment, and using .lit8
4545 permits the linker to eventually combine identical
4548 f64
= *args
== 'F' || *args
== 'L';
4550 save_in
= input_line_pointer
;
4551 input_line_pointer
= s
;
4552 err
= md_atof (f64
? 'd' : 'f', (char *) temp
, &len
);
4554 s
= input_line_pointer
;
4555 input_line_pointer
= save_in
;
4556 if (err
!= NULL
&& *err
!= '\0')
4558 as_bad ("Bad floating point constant: %s", err
);
4559 memset (temp
, '\0', sizeof temp
);
4560 length
= f64
? 8 : 4;
4563 assert (length
== (f64
? 8 : 4));
4567 && (mips_pic
== EMBEDDED_PIC
4569 || g_switch_value
< 4
4573 imm_expr
.X_op
= O_constant
;
4574 if (byte_order
== LITTLE_ENDIAN
)
4575 imm_expr
.X_add_number
=
4576 (((((((int) temp
[3] << 8)
4581 imm_expr
.X_add_number
=
4582 (((((((int) temp
[0] << 8)
4589 const char *newname
;
4592 /* Switch to the right section. */
4594 subseg
= now_subseg
;
4597 default: /* unused default case avoids warnings. */
4601 if (g_switch_value
< 8)
4602 newname
= RDATA_SECTION_NAME
;
4606 newname
= RDATA_SECTION_NAME
;
4610 assert (g_switch_value
>= 4);
4615 new_seg
= subseg_new (newname
, (subsegT
) 0);
4616 frag_align (*args
== 'l' ? 2 : 3, 0);
4618 record_alignment (new_seg
, 4);
4620 record_alignment (new_seg
, *args
== 'l' ? 2 : 3);
4623 as_bad ("Can't use floating point insn in this section");
4625 /* Set the argument to the current address in the
4627 offset_expr
.X_op
= O_symbol
;
4628 offset_expr
.X_add_symbol
=
4629 symbol_new ("L0\001", now_seg
,
4630 (valueT
) frag_now_fix (), frag_now
);
4631 offset_expr
.X_add_number
= 0;
4633 /* Put the floating point number into the section. */
4634 p
= frag_more ((int) length
);
4635 memcpy (p
, temp
, length
);
4637 /* Switch back to the original section. */
4638 subseg_set (seg
, subseg
);
4643 case 'i': /* 16 bit unsigned immediate */
4644 case 'j': /* 16 bit signed immediate */
4645 imm_reloc
= BFD_RELOC_LO16
;
4646 c
= my_getSmallExpression (&imm_expr
, s
);
4651 if (imm_expr
.X_op
== O_constant
)
4652 imm_expr
.X_add_number
=
4653 (imm_expr
.X_add_number
>> 16) & 0xffff;
4655 imm_reloc
= BFD_RELOC_HI16_S
;
4657 imm_reloc
= BFD_RELOC_HI16
;
4661 check_absolute_expr (ip
, &imm_expr
);
4664 if (imm_expr
.X_add_number
< 0
4665 || imm_expr
.X_add_number
>= 0x10000)
4667 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
4668 !strcmp (insn
->name
, insn
[1].name
))
4670 as_bad ("16 bit expression not in range 0..65535");
4678 /* The upper bound should be 0x8000, but
4679 unfortunately the MIPS assembler accepts numbers
4680 from 0x8000 to 0xffff and sign extends them, and
4681 we want to be compatible. We only permit this
4682 extended range for an instruction which does not
4683 provide any further alternates, since those
4684 alternates may handle other cases. People should
4685 use the numbers they mean, rather than relying on
4686 a mysterious sign extension. */
4687 more
= (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
4688 strcmp (insn
->name
, insn
[1].name
) == 0);
4693 if (imm_expr
.X_add_number
< -0x8000 ||
4694 imm_expr
.X_add_number
>= max
)
4698 as_bad ("16 bit expression not in range -32768..32767");
4704 case 'o': /* 16 bit offset */
4705 c
= my_getSmallExpression (&offset_expr
, s
);
4707 /* If this value won't fit into a 16 bit offset, then go
4708 find a macro that will generate the 32 bit offset
4709 code pattern. As a special hack, we accept the
4710 difference of two local symbols as a constant. This
4711 is required to suppose embedded PIC switches, which
4712 use an instruction which looks like
4713 lw $4,$L12-$LS12($4)
4714 The problem with handling this in a more general
4715 fashion is that the macro function doesn't expect to
4716 see anything which can be handled in a single
4717 constant instruction. */
4719 && (offset_expr
.X_op
!= O_constant
4720 || offset_expr
.X_add_number
>= 0x8000
4721 || offset_expr
.X_add_number
< -0x8000)
4722 && (mips_pic
!= EMBEDDED_PIC
4723 || offset_expr
.X_op
!= O_subtract
4724 || now_seg
!= text_section
4725 || (S_GET_SEGMENT (offset_expr
.X_op_symbol
)
4729 offset_reloc
= BFD_RELOC_LO16
;
4730 if (c
== 'h' || c
== 'H')
4732 assert (offset_expr
.X_op
== O_constant
);
4733 offset_expr
.X_add_number
=
4734 (offset_expr
.X_add_number
>> 16) & 0xffff;
4739 case 'p': /* pc relative offset */
4740 offset_reloc
= BFD_RELOC_16_PCREL_S2
;
4741 my_getExpression (&offset_expr
, s
);
4745 case 'u': /* upper 16 bits */
4746 c
= my_getSmallExpression (&imm_expr
, s
);
4747 if (imm_expr
.X_op
== O_constant
4748 && (imm_expr
.X_add_number
< 0
4749 || imm_expr
.X_add_number
>= 0x10000))
4750 as_bad ("lui expression not in range 0..65535");
4751 imm_reloc
= BFD_RELOC_LO16
;
4756 if (imm_expr
.X_op
== O_constant
)
4757 imm_expr
.X_add_number
=
4758 (imm_expr
.X_add_number
>> 16) & 0xffff;
4760 imm_reloc
= BFD_RELOC_HI16_S
;
4762 imm_reloc
= BFD_RELOC_HI16
;
4768 case 'a': /* 26 bit address */
4769 my_getExpression (&offset_expr
, s
);
4771 offset_reloc
= BFD_RELOC_MIPS_JMP
;
4775 fprintf (stderr
, "bad char = '%c'\n", *args
);
4780 /* Args don't match. */
4781 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
4782 !strcmp (insn
->name
, insn
[1].name
))
4788 insn_error
= "ERROR: Illegal operands";
4797 my_getSmallExpression (ep
, str
)
4808 ((str
[1] == 'h' && str
[2] == 'i')
4809 || (str
[1] == 'H' && str
[2] == 'I')
4810 || (str
[1] == 'l' && str
[2] == 'o'))
4822 * A small expression may be followed by a base register.
4823 * Scan to the end of this operand, and then back over a possible
4824 * base register. Then scan the small expression up to that
4825 * point. (Based on code in sparc.c...)
4827 for (sp
= str
; *sp
&& *sp
!= ','; sp
++)
4829 if (sp
- 4 >= str
&& sp
[-1] == RP
)
4831 if (isdigit (sp
[-2]))
4833 for (sp
-= 3; sp
>= str
&& isdigit (*sp
); sp
--)
4835 if (*sp
== '$' && sp
> str
&& sp
[-1] == LP
)
4841 else if (sp
- 5 >= str
4844 && ((sp
[-3] == 'f' && sp
[-2] == 'p')
4845 || (sp
[-3] == 's' && sp
[-2] == 'p')
4846 || (sp
[-3] == 'g' && sp
[-2] == 'p')
4847 || (sp
[-3] == 'a' && sp
[-2] == 't')))
4853 /* no expression means zero offset */
4856 /* %xx(reg) is an error */
4857 ep
->X_op
= O_absent
;
4862 ep
->X_op
= O_constant
;
4865 ep
->X_add_symbol
= NULL
;
4866 ep
->X_op_symbol
= NULL
;
4867 ep
->X_add_number
= 0;
4872 my_getExpression (ep
, str
);
4879 my_getExpression (ep
, str
);
4880 return c
; /* => %hi or %lo encountered */
4884 my_getExpression (ep
, str
)
4890 save_in
= input_line_pointer
;
4891 input_line_pointer
= str
;
4893 expr_end
= input_line_pointer
;
4894 input_line_pointer
= save_in
;
4897 /* Turn a string in input_line_pointer into a floating point constant
4898 of type type, and store the appropriate bytes in *litP. The number
4899 of LITTLENUMS emitted is stored in *sizeP . An error message is
4900 returned, or NULL on OK. */
4903 md_atof (type
, litP
, sizeP
)
4909 LITTLENUM_TYPE words
[4];
4925 return "bad call to md_atof";
4928 t
= atof_ieee (input_line_pointer
, type
, words
);
4930 input_line_pointer
= t
;
4934 if (byte_order
== LITTLE_ENDIAN
)
4936 for (i
= prec
- 1; i
>= 0; i
--)
4938 md_number_to_chars (litP
, (valueT
) words
[i
], 2);
4944 for (i
= 0; i
< prec
; i
++)
4946 md_number_to_chars (litP
, (valueT
) words
[i
], 2);
4955 md_number_to_chars (buf
, val
, n
)
4963 number_to_chars_littleendian (buf
, val
, n
);
4967 number_to_chars_bigendian (buf
, val
, n
);
4976 CONST
char *md_shortopts
= "O::g::G:";
4978 CONST
char *md_shortopts
= "O::g::";
4980 struct option md_longopts
[] = {
4981 #define OPTION_MIPS1 (OPTION_MD_BASE + 1)
4982 {"mips0", no_argument
, NULL
, OPTION_MIPS1
},
4983 {"mips1", no_argument
, NULL
, OPTION_MIPS1
},
4984 #define OPTION_MIPS2 (OPTION_MD_BASE + 2)
4985 {"mips2", no_argument
, NULL
, OPTION_MIPS2
},
4986 #define OPTION_MIPS3 (OPTION_MD_BASE + 3)
4987 {"mips3", no_argument
, NULL
, OPTION_MIPS3
},
4988 #define OPTION_MCPU (OPTION_MD_BASE + 4)
4989 {"mcpu", required_argument
, NULL
, OPTION_MCPU
},
4990 #define OPTION_MEMBEDDED_PIC (OPTION_MD_BASE + 5)
4991 {"membedded-pic", no_argument
, NULL
, OPTION_MEMBEDDED_PIC
},
4992 #define OPTION_TRAP (OPTION_MD_BASE + 8)
4993 {"trap", no_argument
, NULL
, OPTION_TRAP
},
4994 {"no-break", no_argument
, NULL
, OPTION_TRAP
},
4995 #define OPTION_BREAK (OPTION_MD_BASE + 9)
4996 {"break", no_argument
, NULL
, OPTION_BREAK
},
4997 {"no-trap", no_argument
, NULL
, OPTION_BREAK
},
4998 #define OPTION_EB (OPTION_MD_BASE + 10)
4999 {"EB", no_argument
, NULL
, OPTION_EB
},
5000 #define OPTION_EL (OPTION_MD_BASE + 11)
5001 {"EL", no_argument
, NULL
, OPTION_EL
},
5004 #define OPTION_CALL_SHARED (OPTION_MD_BASE + 6)
5005 {"KPIC", no_argument
, NULL
, OPTION_CALL_SHARED
},
5006 {"call_shared", no_argument
, NULL
, OPTION_CALL_SHARED
},
5007 #define OPTION_NON_SHARED (OPTION_MD_BASE + 7)
5008 {"non_shared", no_argument
, NULL
, OPTION_NON_SHARED
},
5011 {NULL
, no_argument
, NULL
, 0}
5013 size_t md_longopts_size
= sizeof(md_longopts
);
5016 md_parse_option (c
, arg
)
5031 byte_order
= BIG_ENDIAN
;
5033 mips_target_format
= "a.out-mips-big";
5036 mips_target_format
= "ecoff-bigmips";
5039 mips_target_format
= "elf32-bigmips";
5044 byte_order
= LITTLE_ENDIAN
;
5046 mips_target_format
= "a.out-mips-little";
5049 mips_target_format
= "ecoff-littlemips";
5052 mips_target_format
= "elf32-littlemips";
5057 if (arg
&& arg
[1] == '0')
5064 if (arg
== NULL
|| arg
[1] == '2')
5090 /* Identify the processor type */
5092 if (strcmp (p
, "default") == 0
5093 || strcmp (p
, "DEFAULT") == 0)
5097 if (*p
== 'r' || *p
== 'R')
5104 if (strcmp (p
, "2000") == 0
5105 || strcmp (p
, "2k") == 0
5106 || strcmp (p
, "2K") == 0)
5111 if (strcmp (p
, "3000") == 0
5112 || strcmp (p
, "3k") == 0
5113 || strcmp (p
, "3K") == 0)
5118 if (strcmp (p
, "4000") == 0
5119 || strcmp (p
, "4k") == 0
5120 || strcmp (p
, "4K") == 0)
5122 else if (strcmp (p
, "4400") == 0)
5124 else if (strcmp (p
, "4600") == 0)
5129 if (strcmp (p
, "6000") == 0
5130 || strcmp (p
, "6k") == 0
5131 || strcmp (p
, "6K") == 0)
5136 if (strcmp (p
, "orion") == 0)
5143 as_bad ("invalid architecture -mcpu=%s", arg
);
5150 case OPTION_MEMBEDDED_PIC
:
5151 mips_pic
= EMBEDDED_PIC
;
5155 as_bad ("-G may not be used with embedded PIC code");
5158 g_switch_value
= 0x7fffffff;
5163 /* When generating ELF code, we permit -KPIC and -call_shared to
5164 select SVR4_PIC, and -non_shared to select no PIC. This is
5165 intended to be compatible with Irix 5. */
5166 case OPTION_CALL_SHARED
:
5167 mips_pic
= SVR4_PIC
;
5168 if (g_switch_seen
&& g_switch_value
!= 0)
5170 as_bad ("-G may not be used with SVR4 PIC code");
5176 case OPTION_NON_SHARED
:
5179 #endif /* OBJ_ELF */
5183 if (mips_pic
== SVR4_PIC
|| mips_pic
== EMBEDDED_PIC
)
5185 as_bad ("-G may not be used with SVR4 or embedded PIC code");
5189 g_switch_value
= atoi (arg
);
5202 md_show_usage (stream
)
5207 -membedded-pic generate embedded position independent code\n\
5208 -EB generate big endian output\n\
5209 -EL generate little endian output\n\
5210 -g, -g2 do not remove uneeded NOPs or swap branches\n\
5211 -G NUM allow referencing objects up to NUM bytes\n\
5212 implicitly with the gp register [default 8]\n");
5214 -mips1, -mcpu=r{2,3}000 generate code for r2000 and r3000\n\
5215 -mips2, -mcpu=r6000 generate code for r6000\n\
5216 -mips3, -mcpu=r4000 generate code for r4000\n\
5217 -O0 remove unneeded NOPs, do not swap branches\n\
5218 -O remove unneeded NOPs and swap branches\n\
5219 --trap, --no-break trap exception on div by 0 and mult overflow\n\
5220 --break, --no-trap break exception on div by 0 and mult overflow\n");
5223 -KPIC, -call_shared generate SVR4 position independent code\n\
5224 -non_shared do not generate position independent code\n");
5229 md_pcrel_from (fixP
)
5233 if (fixP
->fx_addsy
!= (symbolS
*) NULL
5234 && ! S_IS_DEFINED (fixP
->fx_addsy
))
5236 /* This makes a branch to an undefined symbol be a branch to the
5237 current location. */
5242 /* return the address of the delay slot */
5243 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
5246 /* This is called by emit_expr via TC_CONS_FIX_NEW when creating a
5247 reloc for a cons. We could use the definition there, except that
5248 we want to handle 64 bit relocs specially. */
5251 cons_fix_new_mips (frag
, where
, nbytes
, exp
)
5254 unsigned int nbytes
;
5257 /* If we are assembling in 32 bit mode, turn an 8 byte reloc into a
5259 FIXME: There is no way to select anything but 32 bit mode right
5263 if (byte_order
== BIG_ENDIAN
)
5268 if (nbytes
!= 2 && nbytes
!= 4)
5269 as_bad ("Unsupported reloc size %d", nbytes
);
5271 fix_new_exp (frag_now
, where
, (int) nbytes
, exp
, 0,
5272 nbytes
== 2 ? BFD_RELOC_16
: BFD_RELOC_32
);
5275 /* When generating embedded PIC code we need to use a special
5276 relocation to represent the difference of two symbols in the .text
5277 section (switch tables use a difference of this sort). See
5278 include/coff/mips.h for details. This macro checks whether this
5279 fixup requires the special reloc. */
5280 #define SWITCH_TABLE(fixp) \
5281 ((fixp)->fx_r_type == BFD_RELOC_32 \
5282 && (fixp)->fx_addsy != NULL \
5283 && (fixp)->fx_subsy != NULL \
5284 && S_GET_SEGMENT ((fixp)->fx_addsy) == text_section \
5285 && S_GET_SEGMENT ((fixp)->fx_subsy) == text_section)
5287 /* When generating embedded PIC code we must keep all PC relative
5288 relocations, in case the linker has to relax a call. We also need
5289 to keep relocations for switch table entries. */
5293 mips_force_relocation (fixp
)
5296 return (mips_pic
== EMBEDDED_PIC
5298 || SWITCH_TABLE (fixp
)
5299 || fixp
->fx_r_type
== BFD_RELOC_PCREL_HI16_S
5300 || fixp
->fx_r_type
== BFD_RELOC_PCREL_LO16
));
5303 /* Apply a fixup to the object file. */
5306 md_apply_fix (fixP
, valueP
)
5313 assert (fixP
->fx_size
== 4);
5316 fixP
->fx_addnumber
= value
; /* Remember value for tc_gen_reloc */
5318 if (fixP
->fx_addsy
== NULL
&& ! fixP
->fx_pcrel
)
5321 switch (fixP
->fx_r_type
)
5323 case BFD_RELOC_MIPS_JMP
:
5324 case BFD_RELOC_HI16
:
5325 case BFD_RELOC_HI16_S
:
5326 case BFD_RELOC_MIPS_GPREL
:
5327 case BFD_RELOC_MIPS_LITERAL
:
5328 case BFD_RELOC_MIPS_CALL16
:
5329 case BFD_RELOC_MIPS_GOT16
:
5330 case BFD_RELOC_MIPS_GPREL32
:
5332 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
5333 "Invalid PC relative reloc");
5334 /* Nothing needed to do. The value comes from the reloc entry */
5337 case BFD_RELOC_PCREL_HI16_S
:
5338 /* The addend for this is tricky if it is internal, so we just
5339 do everything here rather than in bfd_perform_relocation. */
5340 if ((fixP
->fx_addsy
->bsym
->flags
& BSF_SECTION_SYM
) == 0)
5342 /* For an external symbol adjust by the address to make it
5343 pcrel_offset. We use the address of the RELLO reloc
5344 which follows this one. */
5345 value
+= (fixP
->fx_next
->fx_frag
->fr_address
5346 + fixP
->fx_next
->fx_where
);
5351 buf
= (unsigned char *) fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
5352 if (byte_order
== BIG_ENDIAN
)
5354 md_number_to_chars (buf
, value
, 2);
5357 case BFD_RELOC_PCREL_LO16
:
5358 /* The addend for this is tricky if it is internal, so we just
5359 do everything here rather than in bfd_perform_relocation. */
5360 if ((fixP
->fx_addsy
->bsym
->flags
& BSF_SECTION_SYM
) == 0)
5361 value
+= fixP
->fx_frag
->fr_address
+ fixP
->fx_where
;
5362 buf
= (unsigned char *) fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
5363 if (byte_order
== BIG_ENDIAN
)
5365 md_number_to_chars (buf
, value
, 2);
5369 /* If we are deleting this reloc entry, we must fill in the
5370 value now. This can happen if we have a .word which is not
5371 resolved when it appears but is later defined. We also need
5372 to fill in the value if this is an embedded PIC switch table
5375 || (mips_pic
== EMBEDDED_PIC
&& SWITCH_TABLE (fixP
)))
5376 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
,
5380 case BFD_RELOC_LO16
:
5381 /* When handling an embedded PIC switch statement, we can wind
5382 up deleting a LO16 reloc. See the 'o' case in mips_ip. */
5385 if (value
< -0x8000 || value
> 0x7fff)
5386 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
5387 "relocation overflow");
5388 buf
= (unsigned char *) fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
5389 if (byte_order
== BIG_ENDIAN
)
5391 md_number_to_chars (buf
, value
, 2);
5395 case BFD_RELOC_16_PCREL_S2
:
5397 * We need to save the bits in the instruction since fixup_segment()
5398 * might be deleting the relocation entry (i.e., a branch within
5399 * the current segment).
5402 as_warn_where (fixP
->fx_file
, fixP
->fx_line
,
5403 "Branch to odd address (%lx)", value
);
5406 /* update old instruction data */
5407 buf
= (unsigned char *) (fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
);
5411 insn
= (buf
[3] << 24) | (buf
[2] << 16) | (buf
[1] << 8) | buf
[0];
5415 insn
= (buf
[0] << 24) | (buf
[1] << 16) | (buf
[2] << 8) | buf
[3];
5423 if (value
>= -0x8000 && value
< 0x8000)
5424 insn
|= value
& 0xffff;
5427 /* The branch offset is too large. If this is an
5428 unconditional branch, and we are not generating PIC code,
5429 we can convert it to an absolute jump instruction. */
5430 if (mips_pic
== NO_PIC
5432 && fixP
->fx_frag
->fr_address
>= text_section
->vma
5433 && (fixP
->fx_frag
->fr_address
5434 < text_section
->vma
+ text_section
->_raw_size
)
5435 && ((insn
& 0xffff0000) == 0x10000000 /* beq $0,$0 */
5436 || (insn
& 0xffff0000) == 0x04010000 /* bgez $0 */
5437 || (insn
& 0xffff0000) == 0x04110000)) /* bgezal $0 */
5439 if ((insn
& 0xffff0000) == 0x04110000) /* bgezal $0 */
5440 insn
= 0x0c000000; /* jal */
5442 insn
= 0x08000000; /* j */
5443 fixP
->fx_r_type
= BFD_RELOC_MIPS_JMP
;
5445 fixP
->fx_addsy
= section_symbol (text_section
);
5446 fixP
->fx_addnumber
= (value
<< 2) + md_pcrel_from (fixP
);
5450 /* FIXME. It would be possible in principle to handle
5451 conditional branches which overflow. They could be
5452 transformed into a branch around a jump. This would
5453 require setting up variant frags for each different
5454 branch type. The native MIPS assembler attempts to
5455 handle these cases, but it appears to do it
5457 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
5458 "Relocation overflow");
5462 md_number_to_chars ((char *) buf
, (valueT
) insn
, 4);
5477 const struct mips_opcode
*p
;
5478 int treg
, sreg
, dreg
, shamt
;
5483 for (i
= 0; i
< NUMOPCODES
; ++i
)
5485 p
= &mips_opcodes
[i
];
5486 if (((oc
& p
->mask
) == p
->match
) && (p
->pinfo
!= INSN_MACRO
))
5488 printf ("%08lx %s\t", oc
, p
->name
);
5489 treg
= (oc
>> 16) & 0x1f;
5490 sreg
= (oc
>> 21) & 0x1f;
5491 dreg
= (oc
>> 11) & 0x1f;
5492 shamt
= (oc
>> 6) & 0x1f;
5494 for (args
= p
->args
;; ++args
)
5505 printf ("%c", *args
);
5509 assert (treg
== sreg
);
5510 printf ("$%d,$%d", treg
, sreg
);
5515 printf ("$%d", dreg
);
5520 printf ("$%d", treg
);
5524 printf ("0x%x", treg
);
5529 printf ("$%d", sreg
);
5533 printf ("0x%08lx", oc
& 0x1ffffff);
5545 printf ("$%d", shamt
);
5556 printf ("%08lx UNDEFINED\n", oc
);
5567 name
= input_line_pointer
;
5568 c
= get_symbol_end ();
5569 p
= (symbolS
*) symbol_find_or_make (name
);
5570 *input_line_pointer
= c
;
5574 /* Align the current frag to a given power of two. The MIPS assembler
5575 also automatically adjusts any preceding label. */
5578 mips_align (to
, fill
, label
)
5583 mips_emit_delays ();
5584 frag_align (to
, fill
);
5585 record_alignment (now_seg
, to
);
5588 assert (S_GET_SEGMENT (label
) == now_seg
);
5589 label
->sy_frag
= frag_now
;
5590 S_SET_VALUE (label
, (valueT
) frag_now_fix ());
5594 /* Align to a given power of two. .align 0 turns off the automatic
5595 alignment used by the data creating pseudo-ops. */
5602 register long temp_fill
;
5603 long max_alignment
= 15;
5607 o Note that the assembler pulls down any immediately preceeding label
5608 to the aligned address.
5609 o It's not documented but auto alignment is reinstated by
5610 a .align pseudo instruction.
5611 o Note also that after auto alignment is turned off the mips assembler
5612 issues an error on attempt to assemble an improperly aligned data item.
5617 temp
= get_absolute_expression ();
5618 if (temp
> max_alignment
)
5619 as_bad ("Alignment too large: %d. assumed.", temp
= max_alignment
);
5622 as_warn ("Alignment negative: 0 assumed.");
5625 if (*input_line_pointer
== ',')
5627 input_line_pointer
++;
5628 temp_fill
= get_absolute_expression ();
5635 mips_align (temp
, (int) temp_fill
, insn_label
);
5642 demand_empty_rest_of_line ();
5645 /* Handle .ascii and .asciiz. This just calls stringer and forgets
5646 that there was a previous instruction. */
5649 s_stringer (append_zero
)
5652 mips_emit_delays ();
5654 stringer (append_zero
);
5665 /* When generating embedded PIC code, we only use the .text, .lit8,
5666 .sdata and .sbss sections. We change the .data and .rdata
5667 pseudo-ops to use .sdata. */
5668 if (mips_pic
== EMBEDDED_PIC
5669 && (sec
== 'd' || sec
== 'r'))
5672 mips_emit_delays ();
5682 subseg_set (bss_section
, (subsegT
) get_absolute_expression ());
5683 demand_empty_rest_of_line ();
5688 seg
= subseg_new (RDATA_SECTION_NAME
,
5689 (subsegT
) get_absolute_expression ());
5691 bfd_set_section_flags (stdoutput
, seg
,
5697 bfd_set_section_alignment (stdoutput
, seg
, 4);
5699 demand_empty_rest_of_line ();
5700 #else /* ! defined (GPOPT) */
5701 as_bad ("No read only data section in this object file format");
5702 demand_empty_rest_of_line ();
5704 #endif /* ! defined (GPOPT) */
5709 seg
= subseg_new (".sdata", (subsegT
) get_absolute_expression ());
5711 bfd_set_section_flags (stdoutput
, seg
,
5712 SEC_ALLOC
| SEC_LOAD
| SEC_RELOC
| SEC_DATA
);
5713 bfd_set_section_alignment (stdoutput
, seg
, 4);
5715 demand_empty_rest_of_line ();
5717 #else /* ! defined (GPOPT) */
5718 as_bad ("Global pointers not supported; recompile -G 0");
5719 demand_empty_rest_of_line ();
5721 #endif /* ! defined (GPOPT) */
5729 /* Handle the ELF .section pseudo-op. This is a wrapper around
5736 mips_emit_delays ();
5737 obj_elf_section (x
);
5741 #endif /* OBJ_ELF */
5750 mips_emit_delays ();
5751 if (log_size
> 0 && auto_align
)
5752 mips_align (log_size
, 0, label
);
5754 cons (1 << log_size
);
5761 as_fatal ("Encountered `.err', aborting assembly");
5771 symbolP
= get_symbol ();
5772 if (*input_line_pointer
== ',')
5773 input_line_pointer
++;
5774 size
= get_absolute_expression ();
5775 S_SET_EXTERNAL (symbolP
);
5777 #ifdef ECOFF_DEBUGGING
5778 symbolP
->ecoff_extern_size
= size
;
5790 mips_emit_delays ();
5794 mips_align (3, 0, label
);
5796 mips_align (2, 0, label
);
5803 /* Handle .globl. We need to override it because on Irix 5 you are
5806 where foo is an undefined symbol, to mean that foo should be
5807 considered to be the address of a function. */
5817 name
= input_line_pointer
;
5818 c
= get_symbol_end ();
5819 symbolP
= symbol_find_or_make (name
);
5820 *input_line_pointer
= c
;
5822 if (! is_end_of_line
[(unsigned char) *input_line_pointer
])
5827 secname
= input_line_pointer
;
5828 c
= get_symbol_end ();
5829 sec
= bfd_get_section_by_name (stdoutput
, secname
);
5831 as_bad ("%s: no such section", secname
);
5832 *input_line_pointer
= c
;
5834 if (sec
!= NULL
&& (sec
->flags
& SEC_CODE
) != 0)
5835 symbolP
->bsym
->flags
|= BSF_FUNCTION
;
5838 S_SET_EXTERNAL (symbolP
);
5839 demand_empty_rest_of_line ();
5849 opt
= input_line_pointer
;
5850 c
= get_symbol_end ();
5854 /* FIXME: What does this mean? */
5856 else if (strncmp (opt
, "pic", 3) == 0)
5864 mips_pic
= SVR4_PIC
;
5866 as_bad (".option pic%d not supported", i
);
5869 if (mips_pic
== SVR4_PIC
)
5871 if (g_switch_seen
&& g_switch_value
!= 0)
5872 as_warn ("-G may not be used with SVR4 PIC code");
5874 bfd_set_gp_size (stdoutput
, 0);
5879 as_warn ("Unrecognized option \"%s\"", opt
);
5881 *input_line_pointer
= c
;
5882 demand_empty_rest_of_line ();
5889 char *name
= input_line_pointer
, ch
;
5891 while (!is_end_of_line
[(unsigned char) *input_line_pointer
])
5892 input_line_pointer
++;
5893 ch
= *input_line_pointer
;
5894 *input_line_pointer
= '\0';
5896 if (strcmp (name
, "reorder") == 0)
5900 prev_insn_unreordered
= 1;
5901 prev_prev_insn_unreordered
= 1;
5905 else if (strcmp (name
, "noreorder") == 0)
5907 mips_emit_delays ();
5909 mips_any_noreorder
= 1;
5911 else if (strcmp (name
, "at") == 0)
5915 else if (strcmp (name
, "noat") == 0)
5919 else if (strcmp (name
, "macro") == 0)
5921 mips_warn_about_macros
= 0;
5923 else if (strcmp (name
, "nomacro") == 0)
5925 if (mips_noreorder
== 0)
5926 as_bad ("`noreorder' must be set before `nomacro'");
5927 mips_warn_about_macros
= 1;
5929 else if (strcmp (name
, "move") == 0 || strcmp (name
, "novolatile") == 0)
5933 else if (strcmp (name
, "nomove") == 0 || strcmp (name
, "volatile") == 0)
5937 else if (strcmp (name
, "bopt") == 0)
5941 else if (strcmp (name
, "nobopt") == 0)
5945 else if (strncmp (name
, "mips", 4) == 0)
5949 /* Permit the user to change the ISA on the fly. Needless to
5950 say, misuse can cause serious problems. */
5951 isa
= atoi (name
+ 4);
5953 mips_isa
= file_mips_isa
;
5954 else if (isa
< 1 || isa
> 3)
5955 as_bad ("unknown ISA level");
5961 as_warn ("Tried to set unrecognized symbol: %s\n", name
);
5963 *input_line_pointer
= ch
;
5964 demand_empty_rest_of_line ();
5967 /* The same as the usual .space directive, except that we have to
5968 forget about any previous instruction. */
5971 s_mips_space (param
)
5974 mips_emit_delays ();
5979 /* Handle the .abicalls pseudo-op. I believe this is equivalent to
5980 .option pic2. It means to generate SVR4 PIC calls. */
5986 mips_pic
= SVR4_PIC
;
5988 if (g_switch_seen
&& g_switch_value
!= 0)
5989 as_warn ("-G may not be used with SVR4 PIC code");
5992 bfd_set_gp_size (stdoutput
, 0);
5993 demand_empty_rest_of_line ();
5996 /* Handle the .cpload pseudo-op. This is used when generating SVR4
5997 PIC code. It sets the $gp register for the function based on the
5998 function address, which is in the register named in the argument.
5999 This uses a relocation against _gp_disp, which is handled specially
6000 by the linker. The result is:
6001 lui $gp,%hi(_gp_disp)
6002 addiu $gp,$gp,%lo(_gp_disp)
6003 addu $gp,$gp,.cpload argument
6004 The .cpload argument is normally $25 == $t9. */
6013 /* If we are not generating SVR4 PIC code, .cpload is ignored. */
6014 if (mips_pic
!= SVR4_PIC
)
6020 /* .cpload should be a in .set noreorder section. */
6021 if (mips_noreorder
== 0)
6022 as_warn (".cpload not in noreorder section");
6025 ex
.X_add_symbol
= symbol_find_or_make ("_gp_disp");
6026 ex
.X_op_symbol
= NULL
;
6027 ex
.X_add_number
= 0;
6029 macro_build_lui ((char *) NULL
, &icnt
, &ex
, GP
);
6030 macro_build ((char *) NULL
, &icnt
, &ex
, "addiu", "t,r,j", GP
, GP
,
6031 (int) BFD_RELOC_LO16
);
6033 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "addu", "d,v,t",
6034 GP
, GP
, tc_get_register (0));
6036 demand_empty_rest_of_line ();
6039 /* Handle the .cprestore pseudo-op. This stores $gp into a given
6040 offset from $sp. The offset is remembered, and after making a PIC
6041 call $gp is restored from that location. */
6044 s_cprestore (ignore
)
6050 /* If we are not generating SVR4 PIC code, .cprestore is ignored. */
6051 if (mips_pic
!= SVR4_PIC
)
6057 mips_cprestore_offset
= get_absolute_expression ();
6059 ex
.X_op
= O_constant
;
6060 ex
.X_add_symbol
= NULL
;
6061 ex
.X_op_symbol
= NULL
;
6062 ex
.X_add_number
= mips_cprestore_offset
;
6064 macro_build ((char *) NULL
, &icnt
, &ex
,
6065 mips_isa
< 3 ? "sw" : "sd",
6066 "t,o(b)", GP
, (int) BFD_RELOC_LO16
, SP
);
6068 demand_empty_rest_of_line ();
6071 /* Handle the .gpword pseudo-op. This is used when generating PIC
6072 code. It generates a 32 bit GP relative reloc. */
6082 /* When not generating PIC code, this is treated as .word. */
6083 if (mips_pic
!= SVR4_PIC
)
6090 mips_emit_delays ();
6092 mips_align (2, 0, label
);
6097 if (ex
.X_op
!= O_symbol
|| ex
.X_add_number
!= 0)
6099 as_bad ("Unsupported use of .gpword");
6100 ignore_rest_of_line ();
6104 md_number_to_chars (p
, (valueT
) 0, 4);
6105 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 4, &ex
, 0,
6106 BFD_RELOC_MIPS_GPREL32
);
6108 demand_empty_rest_of_line ();
6111 /* Handle the .cpadd pseudo-op. This is used when dealing with switch
6112 tables in SVR4 PIC code. */
6121 /* This is ignored when not generating SVR4 PIC code. */
6122 if (mips_pic
!= SVR4_PIC
)
6128 /* Add $gp to the register named as an argument. */
6129 reg
= tc_get_register (0);
6130 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6131 mips_isa
< 3 ? "addu" : "daddu",
6132 "d,v,t", reg
, reg
, GP
);
6134 demand_empty_rest_of_line ();
6137 /* Parse a register string into a number. Called from the ECOFF code
6138 to parse .frame. The argument is non-zero if this is the frame
6139 register, so that we can record it in mips_frame_reg. */
6142 tc_get_register (frame
)
6148 if (*input_line_pointer
++ != '$')
6150 as_warn ("expected `$'");
6153 else if (isdigit ((unsigned char) *input_line_pointer
))
6155 reg
= get_absolute_expression ();
6156 if (reg
< 0 || reg
>= 32)
6158 as_warn ("Bad register number");
6164 if (strncmp (input_line_pointer
, "fp", 2) == 0)
6166 else if (strncmp (input_line_pointer
, "sp", 2) == 0)
6168 else if (strncmp (input_line_pointer
, "gp", 2) == 0)
6170 else if (strncmp (input_line_pointer
, "at", 2) == 0)
6174 as_warn ("Unrecognized register name");
6177 input_line_pointer
+= 2;
6180 mips_frame_reg
= reg
!= 0 ? reg
: SP
;
6185 md_section_align (seg
, addr
)
6189 int align
= bfd_get_section_alignment (stdoutput
, seg
);
6191 return ((addr
+ (1 << align
) - 1) & (-1 << align
));
6194 /* Estimate the size of a frag before relaxing. We are not really
6195 relaxing here, and the final size is encoded in the subtype
6200 md_estimate_size_before_relax (fragp
, segtype
)
6206 if (mips_pic
== NO_PIC
)
6209 const char *symname
;
6211 /* Find out whether this symbol can be referenced off the GP
6212 register. It can be if it is smaller than the -G size or if
6213 it is in the .sdata or .sbss section. Certain symbols can
6214 not be referenced off the GP, although it appears as though
6216 symname
= S_GET_NAME (fragp
->fr_symbol
);
6217 if (symname
!= (const char *) NULL
6218 && (strcmp (symname
, "eprol") == 0
6219 || strcmp (symname
, "etext") == 0
6220 || strcmp (symname
, "_gp") == 0
6221 || strcmp (symname
, "edata") == 0
6222 || strcmp (symname
, "_fbss") == 0
6223 || strcmp (symname
, "_fdata") == 0
6224 || strcmp (symname
, "_ftext") == 0
6225 || strcmp (symname
, "end") == 0
6226 || strcmp (symname
, "_gp_disp") == 0))
6228 else if (! S_IS_DEFINED (fragp
->fr_symbol
)
6229 && ((fragp
->fr_symbol
->ecoff_extern_size
!= 0
6230 && fragp
->fr_symbol
->ecoff_extern_size
<= g_switch_value
)
6231 || (S_GET_VALUE (fragp
->fr_symbol
) != 0
6232 && S_GET_VALUE (fragp
->fr_symbol
) <= g_switch_value
)))
6236 const char *segname
;
6238 segname
= segment_name (S_GET_SEGMENT (fragp
->fr_symbol
));
6239 assert (strcmp (segname
, ".lit8") != 0
6240 && strcmp (segname
, ".lit4") != 0);
6241 change
= (strcmp (segname
, ".sdata") != 0
6242 && strcmp (segname
, ".sbss") != 0);
6244 #else /* ! defined (GPOPT) */
6245 /* We are not optimizing for the GP register. */
6247 #endif /* ! defined (GPOPT) */
6249 else if (mips_pic
== SVR4_PIC
)
6251 asection
*symsec
= fragp
->fr_symbol
->bsym
->section
;
6253 /* This must duplicate the test in adjust_reloc_syms. */
6254 change
= (symsec
!= &bfd_und_section
6255 && symsec
!= &bfd_abs_section
6256 && ! bfd_is_com_section (symsec
));
6263 /* Record the offset to the first reloc in the fr_opcode field.
6264 This lets md_convert_frag and tc_gen_reloc know that the code
6265 must be expanded. */
6266 fragp
->fr_opcode
= (fragp
->fr_literal
6268 - RELAX_OLD (fragp
->fr_subtype
)
6269 + RELAX_RELOC1 (fragp
->fr_subtype
));
6270 /* FIXME: This really needs as_warn_where. */
6271 if (RELAX_WARN (fragp
->fr_subtype
))
6272 as_warn ("AT used after \".set noat\" or macro used after \".set nomacro\"");
6278 return RELAX_NEW (fragp
->fr_subtype
) - RELAX_OLD (fragp
->fr_subtype
);
6281 /* Translate internal representation of relocation info to BFD target
6285 tc_gen_reloc (section
, fixp
)
6289 static arelent
*retval
[4];
6292 reloc
= retval
[0] = (arelent
*) xmalloc (sizeof (arelent
));
6295 reloc
->sym_ptr_ptr
= &fixp
->fx_addsy
->bsym
;
6296 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
6298 if (mips_pic
== EMBEDDED_PIC
6299 && SWITCH_TABLE (fixp
))
6301 /* For a switch table entry we use a special reloc. The addend
6302 is actually the difference between the reloc address and the
6304 reloc
->addend
= reloc
->address
- S_GET_VALUE (fixp
->fx_subsy
);
6306 as_fatal ("Double check fx_r_type in tc-mips.c:tc_gen_reloc");
6308 fixp
->fx_r_type
= BFD_RELOC_GPREL32
;
6310 else if (fixp
->fx_r_type
== BFD_RELOC_PCREL_LO16
)
6312 /* We use a special addend for an internal RELLO reloc. */
6313 if (fixp
->fx_addsy
->bsym
->flags
& BSF_SECTION_SYM
)
6314 reloc
->addend
= reloc
->address
- S_GET_VALUE (fixp
->fx_subsy
);
6316 reloc
->addend
= fixp
->fx_addnumber
+ reloc
->address
;
6318 else if (fixp
->fx_r_type
== BFD_RELOC_PCREL_HI16_S
)
6320 assert (fixp
->fx_next
!= NULL
6321 && fixp
->fx_next
->fx_r_type
== BFD_RELOC_PCREL_LO16
);
6322 /* We use a special addend for an internal RELHI reloc. The
6323 reloc is relative to the RELLO; adjust the addend
6325 if (fixp
->fx_addsy
->bsym
->flags
& BSF_SECTION_SYM
)
6326 reloc
->addend
= (fixp
->fx_next
->fx_frag
->fr_address
6327 + fixp
->fx_next
->fx_where
6328 - S_GET_VALUE (fixp
->fx_subsy
));
6330 reloc
->addend
= (fixp
->fx_addnumber
6331 + fixp
->fx_next
->fx_frag
->fr_address
6332 + fixp
->fx_next
->fx_where
);
6334 else if (fixp
->fx_pcrel
== 0)
6335 reloc
->addend
= fixp
->fx_addnumber
;
6339 /* A gruesome hack which is a result of the gruesome gas reloc
6341 reloc
->addend
= reloc
->address
;
6343 reloc
->addend
= -reloc
->address
;
6347 /* If this is a variant frag, we may need to adjust the existing
6348 reloc and generate a new one. */
6349 if (fixp
->fx_frag
->fr_opcode
!= NULL
6350 && (fixp
->fx_r_type
== BFD_RELOC_MIPS_GPREL
6351 || fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT16
6352 || fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL16
))
6356 /* If this is not the last reloc in this frag, then we have two
6357 GPREL relocs, both of which are being replaced. Let the
6358 second one handle all of them. */
6359 if (fixp
->fx_next
!= NULL
6360 && fixp
->fx_frag
== fixp
->fx_next
->fx_frag
)
6362 assert (fixp
->fx_r_type
== BFD_RELOC_MIPS_GPREL
6363 && fixp
->fx_next
->fx_r_type
== BFD_RELOC_MIPS_GPREL
);
6368 fixp
->fx_where
= fixp
->fx_frag
->fr_opcode
- fixp
->fx_frag
->fr_literal
;
6369 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
6370 reloc2
= retval
[1] = (arelent
*) xmalloc (sizeof (arelent
));
6372 reloc2
->sym_ptr_ptr
= &fixp
->fx_addsy
->bsym
;
6373 reloc2
->address
= (reloc
->address
6374 + (RELAX_RELOC2 (fixp
->fx_frag
->fr_subtype
)
6375 - RELAX_RELOC1 (fixp
->fx_frag
->fr_subtype
)));
6376 reloc2
->addend
= fixp
->fx_addnumber
;
6377 reloc2
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_LO16
);
6378 assert (reloc2
->howto
!= NULL
);
6380 if (RELAX_RELOC3 (fixp
->fx_frag
->fr_subtype
))
6384 reloc3
= retval
[2] = (arelent
*) xmalloc (sizeof (arelent
));
6387 reloc3
->address
+= 4;
6390 if (mips_pic
== NO_PIC
)
6392 assert (fixp
->fx_r_type
== BFD_RELOC_MIPS_GPREL
);
6393 fixp
->fx_r_type
= BFD_RELOC_HI16_S
;
6395 else if (mips_pic
== SVR4_PIC
)
6397 if (fixp
->fx_r_type
!= BFD_RELOC_MIPS_GOT16
)
6399 assert (fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL16
);
6400 fixp
->fx_r_type
= BFD_RELOC_MIPS_GOT16
;
6407 /* To support a PC relative reloc when generating embedded PIC code
6408 for ECOFF, we use a Cygnus extension. We check for that here to
6409 make sure that we don't let such a reloc escape normally. */
6411 if (fixp
->fx_r_type
== BFD_RELOC_16_PCREL_S2
6412 && mips_pic
!= EMBEDDED_PIC
)
6413 reloc
->howto
= NULL
;
6416 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, fixp
->fx_r_type
);
6418 if (reloc
->howto
== NULL
)
6420 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
6421 "Can not represent relocation in this object file format");
6428 /* Convert a machine dependent frag. */
6431 md_convert_frag (abfd
, asec
, fragp
)
6439 if (fragp
->fr_opcode
== NULL
)
6442 old
= RELAX_OLD (fragp
->fr_subtype
);
6443 new = RELAX_NEW (fragp
->fr_subtype
);
6444 fixptr
= fragp
->fr_literal
+ fragp
->fr_fix
;
6447 memcpy (fixptr
- old
, fixptr
, new);
6449 fragp
->fr_fix
+= new - old
;
6452 /* This function is called whenever a label is defined. It is used
6453 when handling branch delays; if a branch has a label, we assume we
6457 mips_define_label (sym
)
6465 /* Some special processing for a MIPS ELF file. */
6468 mips_elf_final_processing ()
6472 /* Write out the .reginfo section. */
6473 s
.ri_gprmask
= mips_gprmask
;
6474 s
.ri_cprmask
[0] = mips_cprmask
[0];
6475 s
.ri_cprmask
[1] = mips_cprmask
[1];
6476 s
.ri_cprmask
[2] = mips_cprmask
[2];
6477 s
.ri_cprmask
[3] = mips_cprmask
[3];
6478 /* The gp_value field is set by the MIPS ELF backend. */
6480 bfd_mips_elf32_swap_reginfo_out (stdoutput
, &s
,
6481 ((Elf32_External_RegInfo
*)
6482 mips_regmask_frag
));
6484 /* Set the MIPS ELF flag bits. FIXME: There should probably be some
6485 sort of BFD interface for this. */
6486 if (mips_any_noreorder
)
6487 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_NOREORDER
;
6488 if (mips_pic
!= NO_PIC
)
6489 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_PIC
;
6492 #endif /* OBJ_ELF */
6494 #ifndef ECOFF_DEBUGGING
6496 /* These functions should really be defined by the object file format,
6497 since they are related to debugging information. However, this
6498 code has to work for the a.out format, which does not define them,
6499 so we provide simple versions here. These don't actually generate
6500 any debugging information, but they do simple checking and someday
6501 somebody may make them useful. */
6505 struct loc
*loc_next
;
6506 unsigned long loc_fileno
;
6507 unsigned long loc_lineno
;
6508 unsigned long loc_offset
;
6509 unsigned short loc_delta
;
6510 unsigned short loc_count
;
6519 struct proc
*proc_next
;
6520 struct symbol
*proc_isym
;
6521 struct symbol
*proc_end
;
6522 unsigned long proc_reg_mask
;
6523 unsigned long proc_reg_offset
;
6524 unsigned long proc_fpreg_mask
;
6525 unsigned long proc_fpreg_offset
;
6526 unsigned long proc_frameoffset
;
6527 unsigned long proc_framereg
;
6528 unsigned long proc_pcreg
;
6530 struct file
*proc_file
;
6537 struct file
*file_next
;
6538 unsigned long file_fileno
;
6539 struct symbol
*file_symbol
;
6540 struct symbol
*file_end
;
6541 struct proc
*file_proc
;
6546 static struct obstack proc_frags
;
6547 static procS
*proc_lastP
;
6548 static procS
*proc_rootP
;
6549 static int numprocs
;
6554 obstack_begin (&proc_frags
, 0x2000);
6560 /* check for premature end, nesting errors, etc */
6561 if (proc_lastP
&& proc_lastP
->proc_end
== NULL
)
6562 as_warn ("missing `.end' at end of assembly");
6565 extern char hex_value
[];
6573 if (*input_line_pointer
== '-')
6575 ++input_line_pointer
;
6578 if (!isdigit (*input_line_pointer
))
6579 as_bad ("Expected simple number.");
6580 if (input_line_pointer
[0] == '0')
6582 if (input_line_pointer
[1] == 'x')
6584 input_line_pointer
+= 2;
6585 while (isxdigit (*input_line_pointer
))
6588 val
|= hex_value
[(int) *input_line_pointer
++];
6590 return negative
? -val
: val
;
6594 ++input_line_pointer
;
6595 while (isdigit (*input_line_pointer
))
6598 val
|= *input_line_pointer
++ - '0';
6600 return negative
? -val
: val
;
6603 if (!isdigit (*input_line_pointer
))
6605 printf (" *input_line_pointer == '%c' 0x%02x\n",
6606 *input_line_pointer
, *input_line_pointer
);
6607 as_warn ("Invalid number");
6610 while (isdigit (*input_line_pointer
))
6613 val
+= *input_line_pointer
++ - '0';
6615 return negative
? -val
: val
;
6618 /* The .file directive; just like the usual .file directive, but there
6619 is an initial number which is the ECOFF file index. */
6627 line
= get_number ();
6632 /* The .end directive. */
6640 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
6643 demand_empty_rest_of_line ();
6647 if (now_seg
!= text_section
)
6648 as_warn (".end not in text section");
6651 as_warn (".end and no .ent seen yet.");
6657 assert (S_GET_NAME (p
));
6658 if (strcmp (S_GET_NAME (p
), S_GET_NAME (proc_lastP
->proc_isym
)))
6659 as_warn (".end symbol does not match .ent symbol.");
6662 proc_lastP
->proc_end
= (symbolS
*) 1;
6665 /* The .aent and .ent directives. */
6675 symbolP
= get_symbol ();
6676 if (*input_line_pointer
== ',')
6677 input_line_pointer
++;
6679 if (isdigit (*input_line_pointer
) || *input_line_pointer
== '-')
6680 number
= get_number ();
6681 if (now_seg
!= text_section
)
6682 as_warn (".ent or .aent not in text section.");
6684 if (!aent
&& proc_lastP
&& proc_lastP
->proc_end
== NULL
)
6685 as_warn ("missing `.end'");
6689 procP
= (procS
*) obstack_alloc (&proc_frags
, sizeof (*procP
));
6690 procP
->proc_isym
= symbolP
;
6691 procP
->proc_reg_mask
= 0;
6692 procP
->proc_reg_offset
= 0;
6693 procP
->proc_fpreg_mask
= 0;
6694 procP
->proc_fpreg_offset
= 0;
6695 procP
->proc_frameoffset
= 0;
6696 procP
->proc_framereg
= 0;
6697 procP
->proc_pcreg
= 0;
6698 procP
->proc_end
= NULL
;
6699 procP
->proc_next
= NULL
;
6701 proc_lastP
->proc_next
= procP
;
6707 demand_empty_rest_of_line ();
6710 /* The .frame directive. */
6723 frame_reg
= tc_get_register (1);
6724 if (*input_line_pointer
== ',')
6725 input_line_pointer
++;
6726 frame_off
= get_absolute_expression ();
6727 if (*input_line_pointer
== ',')
6728 input_line_pointer
++;
6729 pcreg
= tc_get_register (0);
6732 assert (proc_rootP
);
6733 proc_rootP
->proc_framereg
= frame_reg
;
6734 proc_rootP
->proc_frameoffset
= frame_off
;
6735 proc_rootP
->proc_pcreg
= pcreg
;
6736 /* bob macho .frame */
6738 /* We don't have to write out a frame stab for unoptimized code. */
6739 if (!(frame_reg
== FP
&& frame_off
== 0))
6742 as_warn ("No .ent for .frame to use.");
6743 (void) sprintf (str
, "R%d;%d", frame_reg
, frame_off
);
6744 symP
= symbol_new (str
, N_VFP
, 0, frag_now
);
6745 S_SET_TYPE (symP
, N_RMASK
);
6746 S_SET_OTHER (symP
, 0);
6747 S_SET_DESC (symP
, 0);
6748 symP
->sy_forward
= proc_lastP
->proc_isym
;
6749 /* bob perhaps I should have used pseudo set */
6751 demand_empty_rest_of_line ();
6755 /* The .fmask and .mask directives. */
6762 char str
[100], *strP
;
6768 mask
= get_number ();
6769 if (*input_line_pointer
== ',')
6770 input_line_pointer
++;
6771 off
= get_absolute_expression ();
6773 /* bob only for coff */
6774 assert (proc_rootP
);
6775 if (reg_type
== 'F')
6777 proc_rootP
->proc_fpreg_mask
= mask
;
6778 proc_rootP
->proc_fpreg_offset
= off
;
6782 proc_rootP
->proc_reg_mask
= mask
;
6783 proc_rootP
->proc_reg_offset
= off
;
6786 /* bob macho .mask + .fmask */
6788 /* We don't have to write out a mask stab if no saved regs. */
6792 as_warn ("No .ent for .mask to use.");
6794 for (i
= 0; i
< 32; i
++)
6798 sprintf (strP
, "%c%d,", reg_type
, i
);
6799 strP
+= strlen (strP
);
6803 sprintf (strP
, ";%d,", off
);
6804 symP
= symbol_new (str
, N_RMASK
, 0, frag_now
);
6805 S_SET_TYPE (symP
, N_RMASK
);
6806 S_SET_OTHER (symP
, 0);
6807 S_SET_DESC (symP
, 0);
6808 symP
->sy_forward
= proc_lastP
->proc_isym
;
6809 /* bob perhaps I should have used pseudo set */
6814 /* The .loc directive. */
6825 assert (now_seg
== text_section
);
6827 lineno
= get_number ();
6828 addroff
= obstack_next_free (&frags
) - frag_now
->fr_literal
;
6830 symbolP
= symbol_new ("", N_SLINE
, addroff
, frag_now
);
6831 S_SET_TYPE (symbolP
, N_SLINE
);
6832 S_SET_OTHER (symbolP
, 0);
6833 S_SET_DESC (symbolP
, lineno
);
6834 symbolP
->sy_segment
= now_seg
;
6838 #endif /* ! defined (ECOFF_DEBUGGING) */