1 /* tc-mips.c -- assemble code for a MIPS chip.
2 Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,
3 2003, 2004, 2005 Free Software Foundation, Inc.
4 Contributed by the OSF and Ralph Campbell.
5 Written by Keith Knowles and Ralph Campbell, working independently.
6 Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus
9 This file is part of GAS.
11 GAS is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 2, or (at your option)
16 GAS is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
21 You should have received a copy of the GNU General Public License
22 along with GAS; see the file COPYING. If not, write to the Free
23 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
29 #include "safe-ctype.h"
33 #include "opcode/mips.h"
35 #include "dwarf2dbg.h"
38 #define DBG(x) printf x
44 /* Clean up namespace so we can include obj-elf.h too. */
45 static int mips_output_flavor (void);
46 static int mips_output_flavor (void) { return OUTPUT_FLAVOR
; }
47 #undef OBJ_PROCESS_STAB
54 #undef obj_frob_file_after_relocs
55 #undef obj_frob_symbol
57 #undef obj_sec_sym_ok_for_reloc
58 #undef OBJ_COPY_SYMBOL_ATTRIBUTES
61 /* Fix any of them that we actually care about. */
63 #define OUTPUT_FLAVOR mips_output_flavor()
70 #ifndef ECOFF_DEBUGGING
71 #define NO_ECOFF_DEBUGGING
72 #define ECOFF_DEBUGGING 0
75 int mips_flag_mdebug
= -1;
77 /* Control generation of .pdr sections. Off by default on IRIX: the native
78 linker doesn't know about and discards them, but relocations against them
79 remain, leading to rld crashes. */
81 int mips_flag_pdr
= FALSE
;
83 int mips_flag_pdr
= TRUE
;
88 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
89 static char *mips_regmask_frag
;
95 #define PIC_CALL_REG 25
103 #define ILLEGAL_REG (32)
105 /* Allow override of standard little-endian ECOFF format. */
107 #ifndef ECOFF_LITTLE_FORMAT
108 #define ECOFF_LITTLE_FORMAT "ecoff-littlemips"
111 extern int target_big_endian
;
113 /* The name of the readonly data section. */
114 #define RDATA_SECTION_NAME (OUTPUT_FLAVOR == bfd_target_ecoff_flavour \
116 : OUTPUT_FLAVOR == bfd_target_coff_flavour \
118 : OUTPUT_FLAVOR == bfd_target_elf_flavour \
122 /* Information about an instruction, including its format, operands
126 /* The opcode's entry in mips_opcodes or mips16_opcodes. */
127 const struct mips_opcode
*insn_mo
;
129 /* True if this is a mips16 instruction and if we want the extended
131 bfd_boolean use_extend
;
133 /* The 16-bit extension instruction to use when USE_EXTEND is true. */
134 unsigned short extend
;
136 /* The 16-bit or 32-bit bitstring of the instruction itself. This is
137 a copy of INSN_MO->match with the operands filled in. */
138 unsigned long insn_opcode
;
140 /* The frag that contains the instruction. */
143 /* The offset into FRAG of the first instruction byte. */
146 /* The relocs associated with the instruction, if any. */
149 /* True if this entry cannot be moved from its current position. */
150 unsigned int fixed_p
: 1;
152 /* True if this instruction occured in a .set noreorder block. */
153 unsigned int noreorder_p
: 1;
155 /* True for mips16 instructions that jump to an absolute address. */
156 unsigned int mips16_absolute_jump_p
: 1;
159 /* The ABI to use. */
170 /* MIPS ABI we are using for this output file. */
171 static enum mips_abi_level mips_abi
= NO_ABI
;
173 /* Whether or not we have code that can call pic code. */
174 int mips_abicalls
= FALSE
;
176 /* Whether or not we have code which can be put into a shared
178 static bfd_boolean mips_in_shared
= TRUE
;
180 /* This is the set of options which may be modified by the .set
181 pseudo-op. We use a struct so that .set push and .set pop are more
184 struct mips_set_options
186 /* MIPS ISA (Instruction Set Architecture) level. This is set to -1
187 if it has not been initialized. Changed by `.set mipsN', and the
188 -mipsN command line option, and the default CPU. */
190 /* Enabled Application Specific Extensions (ASEs). These are set to -1
191 if they have not been initialized. Changed by `.set <asename>', by
192 command line options, and based on the default architecture. */
195 /* Whether we are assembling for the mips16 processor. 0 if we are
196 not, 1 if we are, and -1 if the value has not been initialized.
197 Changed by `.set mips16' and `.set nomips16', and the -mips16 and
198 -nomips16 command line options, and the default CPU. */
200 /* Non-zero if we should not reorder instructions. Changed by `.set
201 reorder' and `.set noreorder'. */
203 /* Non-zero if we should not permit the $at ($1) register to be used
204 in instructions. Changed by `.set at' and `.set noat'. */
206 /* Non-zero if we should warn when a macro instruction expands into
207 more than one machine instruction. Changed by `.set nomacro' and
209 int warn_about_macros
;
210 /* Non-zero if we should not move instructions. Changed by `.set
211 move', `.set volatile', `.set nomove', and `.set novolatile'. */
213 /* Non-zero if we should not optimize branches by moving the target
214 of the branch into the delay slot. Actually, we don't perform
215 this optimization anyhow. Changed by `.set bopt' and `.set
218 /* Non-zero if we should not autoextend mips16 instructions.
219 Changed by `.set autoextend' and `.set noautoextend'. */
221 /* Restrict general purpose registers and floating point registers
222 to 32 bit. This is initially determined when -mgp32 or -mfp32
223 is passed but can changed if the assembler code uses .set mipsN. */
226 /* MIPS architecture (CPU) type. Changed by .set arch=FOO, the -march
227 command line option, and the default CPU. */
229 /* True if ".set sym32" is in effect. */
233 /* True if -mgp32 was passed. */
234 static int file_mips_gp32
= -1;
236 /* True if -mfp32 was passed. */
237 static int file_mips_fp32
= -1;
239 /* This is the struct we use to hold the current set of options. Note
240 that we must set the isa field to ISA_UNKNOWN and the ASE fields to
241 -1 to indicate that they have not been initialized. */
243 static struct mips_set_options mips_opts
=
245 ISA_UNKNOWN
, -1, -1, -1, 0, 0, 0, 0, 0, 0, 0, 0, CPU_UNKNOWN
, FALSE
248 /* These variables are filled in with the masks of registers used.
249 The object format code reads them and puts them in the appropriate
251 unsigned long mips_gprmask
;
252 unsigned long mips_cprmask
[4];
254 /* MIPS ISA we are using for this output file. */
255 static int file_mips_isa
= ISA_UNKNOWN
;
257 /* True if -mips16 was passed or implied by arguments passed on the
258 command line (e.g., by -march). */
259 static int file_ase_mips16
;
261 /* True if -mips3d was passed or implied by arguments passed on the
262 command line (e.g., by -march). */
263 static int file_ase_mips3d
;
265 /* True if -mdmx was passed or implied by arguments passed on the
266 command line (e.g., by -march). */
267 static int file_ase_mdmx
;
269 /* The argument of the -march= flag. The architecture we are assembling. */
270 static int file_mips_arch
= CPU_UNKNOWN
;
271 static const char *mips_arch_string
;
273 /* The argument of the -mtune= flag. The architecture for which we
275 static int mips_tune
= CPU_UNKNOWN
;
276 static const char *mips_tune_string
;
278 /* True when generating 32-bit code for a 64-bit processor. */
279 static int mips_32bitmode
= 0;
281 /* True if the given ABI requires 32-bit registers. */
282 #define ABI_NEEDS_32BIT_REGS(ABI) ((ABI) == O32_ABI)
284 /* Likewise 64-bit registers. */
285 #define ABI_NEEDS_64BIT_REGS(ABI) \
287 || (ABI) == N64_ABI \
290 /* Return true if ISA supports 64 bit gp register instructions. */
291 #define ISA_HAS_64BIT_REGS(ISA) ( \
293 || (ISA) == ISA_MIPS4 \
294 || (ISA) == ISA_MIPS5 \
295 || (ISA) == ISA_MIPS64 \
296 || (ISA) == ISA_MIPS64R2 \
299 /* Return true if ISA supports 64-bit right rotate (dror et al.)
301 #define ISA_HAS_DROR(ISA) ( \
302 (ISA) == ISA_MIPS64R2 \
305 /* Return true if ISA supports 32-bit right rotate (ror et al.)
307 #define ISA_HAS_ROR(ISA) ( \
308 (ISA) == ISA_MIPS32R2 \
309 || (ISA) == ISA_MIPS64R2 \
312 #define HAVE_32BIT_GPRS \
313 (mips_opts.gp32 || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
315 #define HAVE_32BIT_FPRS \
316 (mips_opts.fp32 || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
318 #define HAVE_64BIT_GPRS (! HAVE_32BIT_GPRS)
319 #define HAVE_64BIT_FPRS (! HAVE_32BIT_FPRS)
321 #define HAVE_NEWABI (mips_abi == N32_ABI || mips_abi == N64_ABI)
323 #define HAVE_64BIT_OBJECTS (mips_abi == N64_ABI)
325 /* True if relocations are stored in-place. */
326 #define HAVE_IN_PLACE_ADDENDS (!HAVE_NEWABI)
328 /* The ABI-derived address size. */
329 #define HAVE_64BIT_ADDRESSES \
330 (HAVE_64BIT_GPRS && (mips_abi == EABI_ABI || mips_abi == N64_ABI))
331 #define HAVE_32BIT_ADDRESSES (!HAVE_64BIT_ADDRESSES)
333 /* The size of symbolic constants (i.e., expressions of the form
334 "SYMBOL" or "SYMBOL + OFFSET"). */
335 #define HAVE_32BIT_SYMBOLS \
336 (HAVE_32BIT_ADDRESSES || !HAVE_64BIT_OBJECTS || mips_opts.sym32)
337 #define HAVE_64BIT_SYMBOLS (!HAVE_32BIT_SYMBOLS)
339 /* Addresses are loaded in different ways, depending on the address size
340 in use. The n32 ABI Documentation also mandates the use of additions
341 with overflow checking, but existing implementations don't follow it. */
342 #define ADDRESS_ADD_INSN \
343 (HAVE_32BIT_ADDRESSES ? "addu" : "daddu")
345 #define ADDRESS_ADDI_INSN \
346 (HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu")
348 #define ADDRESS_LOAD_INSN \
349 (HAVE_32BIT_ADDRESSES ? "lw" : "ld")
351 #define ADDRESS_STORE_INSN \
352 (HAVE_32BIT_ADDRESSES ? "sw" : "sd")
354 /* Return true if the given CPU supports the MIPS16 ASE. */
355 #define CPU_HAS_MIPS16(cpu) \
356 (strncmp (TARGET_CPU, "mips16", sizeof ("mips16") - 1) == 0 \
357 || strncmp (TARGET_CANONICAL, "mips-lsi-elf", sizeof ("mips-lsi-elf") - 1) == 0)
359 /* Return true if the given CPU supports the MIPS3D ASE. */
360 #define CPU_HAS_MIPS3D(cpu) ((cpu) == CPU_SB1 \
363 /* Return true if the given CPU supports the MDMX ASE. */
364 #define CPU_HAS_MDMX(cpu) (FALSE \
367 /* True if CPU has a dror instruction. */
368 #define CPU_HAS_DROR(CPU) ((CPU) == CPU_VR5400 || (CPU) == CPU_VR5500)
370 /* True if CPU has a ror instruction. */
371 #define CPU_HAS_ROR(CPU) CPU_HAS_DROR (CPU)
373 /* True if mflo and mfhi can be immediately followed by instructions
374 which write to the HI and LO registers.
376 According to MIPS specifications, MIPS ISAs I, II, and III need
377 (at least) two instructions between the reads of HI/LO and
378 instructions which write them, and later ISAs do not. Contradicting
379 the MIPS specifications, some MIPS IV processor user manuals (e.g.
380 the UM for the NEC Vr5000) document needing the instructions between
381 HI/LO reads and writes, as well. Therefore, we declare only MIPS32,
382 MIPS64 and later ISAs to have the interlocks, plus any specific
383 earlier-ISA CPUs for which CPU documentation declares that the
384 instructions are really interlocked. */
385 #define hilo_interlocks \
386 (mips_opts.isa == ISA_MIPS32 \
387 || mips_opts.isa == ISA_MIPS32R2 \
388 || mips_opts.isa == ISA_MIPS64 \
389 || mips_opts.isa == ISA_MIPS64R2 \
390 || mips_opts.arch == CPU_R4010 \
391 || mips_opts.arch == CPU_R10000 \
392 || mips_opts.arch == CPU_R12000 \
393 || mips_opts.arch == CPU_RM7000 \
394 || mips_opts.arch == CPU_VR5500 \
397 /* Whether the processor uses hardware interlocks to protect reads
398 from the GPRs after they are loaded from memory, and thus does not
399 require nops to be inserted. This applies to instructions marked
400 INSN_LOAD_MEMORY_DELAY. These nops are only required at MIPS ISA
402 #define gpr_interlocks \
403 (mips_opts.isa != ISA_MIPS1 \
404 || mips_opts.arch == CPU_R3900)
406 /* Whether the processor uses hardware interlocks to avoid delays
407 required by coprocessor instructions, and thus does not require
408 nops to be inserted. This applies to instructions marked
409 INSN_LOAD_COPROC_DELAY, INSN_COPROC_MOVE_DELAY, and to delays
410 between instructions marked INSN_WRITE_COND_CODE and ones marked
411 INSN_READ_COND_CODE. These nops are only required at MIPS ISA
412 levels I, II, and III. */
413 /* Itbl support may require additional care here. */
414 #define cop_interlocks \
415 ((mips_opts.isa != ISA_MIPS1 \
416 && mips_opts.isa != ISA_MIPS2 \
417 && mips_opts.isa != ISA_MIPS3) \
418 || mips_opts.arch == CPU_R4300 \
421 /* Whether the processor uses hardware interlocks to protect reads
422 from coprocessor registers after they are loaded from memory, and
423 thus does not require nops to be inserted. This applies to
424 instructions marked INSN_COPROC_MEMORY_DELAY. These nops are only
425 requires at MIPS ISA level I. */
426 #define cop_mem_interlocks (mips_opts.isa != ISA_MIPS1)
428 /* Is this a mfhi or mflo instruction? */
429 #define MF_HILO_INSN(PINFO) \
430 ((PINFO & INSN_READ_HI) || (PINFO & INSN_READ_LO))
432 /* MIPS PIC level. */
434 enum mips_pic_level mips_pic
;
436 /* 1 if we should generate 32 bit offsets from the $gp register in
437 SVR4_PIC mode. Currently has no meaning in other modes. */
438 static int mips_big_got
= 0;
440 /* 1 if trap instructions should used for overflow rather than break
442 static int mips_trap
= 0;
444 /* 1 if double width floating point constants should not be constructed
445 by assembling two single width halves into two single width floating
446 point registers which just happen to alias the double width destination
447 register. On some architectures this aliasing can be disabled by a bit
448 in the status register, and the setting of this bit cannot be determined
449 automatically at assemble time. */
450 static int mips_disable_float_construction
;
452 /* Non-zero if any .set noreorder directives were used. */
454 static int mips_any_noreorder
;
456 /* Non-zero if nops should be inserted when the register referenced in
457 an mfhi/mflo instruction is read in the next two instructions. */
458 static int mips_7000_hilo_fix
;
460 /* The size of the small data section. */
461 static unsigned int g_switch_value
= 8;
462 /* Whether the -G option was used. */
463 static int g_switch_seen
= 0;
468 /* If we can determine in advance that GP optimization won't be
469 possible, we can skip the relaxation stuff that tries to produce
470 GP-relative references. This makes delay slot optimization work
473 This function can only provide a guess, but it seems to work for
474 gcc output. It needs to guess right for gcc, otherwise gcc
475 will put what it thinks is a GP-relative instruction in a branch
478 I don't know if a fix is needed for the SVR4_PIC mode. I've only
479 fixed it for the non-PIC mode. KR 95/04/07 */
480 static int nopic_need_relax (symbolS
*, int);
482 /* handle of the OPCODE hash table */
483 static struct hash_control
*op_hash
= NULL
;
485 /* The opcode hash table we use for the mips16. */
486 static struct hash_control
*mips16_op_hash
= NULL
;
488 /* This array holds the chars that always start a comment. If the
489 pre-processor is disabled, these aren't very useful */
490 const char comment_chars
[] = "#";
492 /* This array holds the chars that only start a comment at the beginning of
493 a line. If the line seems to have the form '# 123 filename'
494 .line and .file directives will appear in the pre-processed output */
495 /* Note that input_file.c hand checks for '#' at the beginning of the
496 first line of the input file. This is because the compiler outputs
497 #NO_APP at the beginning of its output. */
498 /* Also note that C style comments are always supported. */
499 const char line_comment_chars
[] = "#";
501 /* This array holds machine specific line separator characters. */
502 const char line_separator_chars
[] = ";";
504 /* Chars that can be used to separate mant from exp in floating point nums */
505 const char EXP_CHARS
[] = "eE";
507 /* Chars that mean this number is a floating point constant */
510 const char FLT_CHARS
[] = "rRsSfFdDxXpP";
512 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
513 changed in read.c . Ideally it shouldn't have to know about it at all,
514 but nothing is ideal around here.
517 static char *insn_error
;
519 static int auto_align
= 1;
521 /* When outputting SVR4 PIC code, the assembler needs to know the
522 offset in the stack frame from which to restore the $gp register.
523 This is set by the .cprestore pseudo-op, and saved in this
525 static offsetT mips_cprestore_offset
= -1;
527 /* Similar for NewABI PIC code, where $gp is callee-saved. NewABI has some
528 more optimizations, it can use a register value instead of a memory-saved
529 offset and even an other register than $gp as global pointer. */
530 static offsetT mips_cpreturn_offset
= -1;
531 static int mips_cpreturn_register
= -1;
532 static int mips_gp_register
= GP
;
533 static int mips_gprel_offset
= 0;
535 /* Whether mips_cprestore_offset has been set in the current function
536 (or whether it has already been warned about, if not). */
537 static int mips_cprestore_valid
= 0;
539 /* This is the register which holds the stack frame, as set by the
540 .frame pseudo-op. This is needed to implement .cprestore. */
541 static int mips_frame_reg
= SP
;
543 /* Whether mips_frame_reg has been set in the current function
544 (or whether it has already been warned about, if not). */
545 static int mips_frame_reg_valid
= 0;
547 /* To output NOP instructions correctly, we need to keep information
548 about the previous two instructions. */
550 /* Whether we are optimizing. The default value of 2 means to remove
551 unneeded NOPs and swap branch instructions when possible. A value
552 of 1 means to not swap branches. A value of 0 means to always
554 static int mips_optimize
= 2;
556 /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is
557 equivalent to seeing no -g option at all. */
558 static int mips_debug
= 0;
560 /* The maximum number of NOPs needed to satisfy a hardware hazard
561 or processor errata. */
564 /* A list of previous instructions, with index 0 being the most recent.
565 We need to look back MAX_NOPS instructions when filling delay slots
566 or working around processor errata. We need to look back one
567 instruction further if we're thinking about using history[0] to
568 fill a branch delay slot. */
569 static struct mips_cl_insn history
[1 + MAX_NOPS
];
571 /* Nop instructions used by emit_nop. */
572 static struct mips_cl_insn nop_insn
, mips16_nop_insn
;
574 /* The appropriate nop for the current mode. */
575 #define NOP_INSN (mips_opts.mips16 ? &mips16_nop_insn : &nop_insn)
577 /* If this is set, it points to a frag holding nop instructions which
578 were inserted before the start of a noreorder section. If those
579 nops turn out to be unnecessary, the size of the frag can be
581 static fragS
*prev_nop_frag
;
583 /* The number of nop instructions we created in prev_nop_frag. */
584 static int prev_nop_frag_holds
;
586 /* The number of nop instructions that we know we need in
588 static int prev_nop_frag_required
;
590 /* The number of instructions we've seen since prev_nop_frag. */
591 static int prev_nop_frag_since
;
593 /* For ECOFF and ELF, relocations against symbols are done in two
594 parts, with a HI relocation and a LO relocation. Each relocation
595 has only 16 bits of space to store an addend. This means that in
596 order for the linker to handle carries correctly, it must be able
597 to locate both the HI and the LO relocation. This means that the
598 relocations must appear in order in the relocation table.
600 In order to implement this, we keep track of each unmatched HI
601 relocation. We then sort them so that they immediately precede the
602 corresponding LO relocation. */
607 struct mips_hi_fixup
*next
;
610 /* The section this fixup is in. */
614 /* The list of unmatched HI relocs. */
616 static struct mips_hi_fixup
*mips_hi_fixup_list
;
618 /* The frag containing the last explicit relocation operator.
619 Null if explicit relocations have not been used. */
621 static fragS
*prev_reloc_op_frag
;
623 /* Map normal MIPS register numbers to mips16 register numbers. */
625 #define X ILLEGAL_REG
626 static const int mips32_to_16_reg_map
[] =
628 X
, X
, 2, 3, 4, 5, 6, 7,
629 X
, X
, X
, X
, X
, X
, X
, X
,
630 0, 1, X
, X
, X
, X
, X
, X
,
631 X
, X
, X
, X
, X
, X
, X
, X
635 /* Map mips16 register numbers to normal MIPS register numbers. */
637 static const unsigned int mips16_to_32_reg_map
[] =
639 16, 17, 2, 3, 4, 5, 6, 7
642 /* Classifies the kind of instructions we're interested in when
643 implementing -mfix-vr4120. */
644 enum fix_vr4120_class
{
651 NUM_FIX_VR4120_CLASSES
654 /* Given two FIX_VR4120_* values X and Y, bit Y of element X is set if
655 there must be at least one other instruction between an instruction
656 of type X and an instruction of type Y. */
657 static unsigned int vr4120_conflicts
[NUM_FIX_VR4120_CLASSES
];
659 /* True if -mfix-vr4120 is in force. */
660 static int mips_fix_vr4120
;
662 /* We don't relax branches by default, since this causes us to expand
663 `la .l2 - .l1' if there's a branch between .l1 and .l2, because we
664 fail to compute the offset before expanding the macro to the most
665 efficient expansion. */
667 static int mips_relax_branch
;
669 /* The expansion of many macros depends on the type of symbol that
670 they refer to. For example, when generating position-dependent code,
671 a macro that refers to a symbol may have two different expansions,
672 one which uses GP-relative addresses and one which uses absolute
673 addresses. When generating SVR4-style PIC, a macro may have
674 different expansions for local and global symbols.
676 We handle these situations by generating both sequences and putting
677 them in variant frags. In position-dependent code, the first sequence
678 will be the GP-relative one and the second sequence will be the
679 absolute one. In SVR4 PIC, the first sequence will be for global
680 symbols and the second will be for local symbols.
682 The frag's "subtype" is RELAX_ENCODE (FIRST, SECOND), where FIRST and
683 SECOND are the lengths of the two sequences in bytes. These fields
684 can be extracted using RELAX_FIRST() and RELAX_SECOND(). In addition,
685 the subtype has the following flags:
688 Set if it has been decided that we should use the second
689 sequence instead of the first.
692 Set in the first variant frag if the macro's second implementation
693 is longer than its first. This refers to the macro as a whole,
694 not an individual relaxation.
697 Set in the first variant frag if the macro appeared in a .set nomacro
698 block and if one alternative requires a warning but the other does not.
701 Like RELAX_NOMACRO, but indicates that the macro appears in a branch
704 The frag's "opcode" points to the first fixup for relaxable code.
706 Relaxable macros are generated using a sequence such as:
708 relax_start (SYMBOL);
709 ... generate first expansion ...
711 ... generate second expansion ...
714 The code and fixups for the unwanted alternative are discarded
715 by md_convert_frag. */
716 #define RELAX_ENCODE(FIRST, SECOND) (((FIRST) << 8) | (SECOND))
718 #define RELAX_FIRST(X) (((X) >> 8) & 0xff)
719 #define RELAX_SECOND(X) ((X) & 0xff)
720 #define RELAX_USE_SECOND 0x10000
721 #define RELAX_SECOND_LONGER 0x20000
722 #define RELAX_NOMACRO 0x40000
723 #define RELAX_DELAY_SLOT 0x80000
725 /* Branch without likely bit. If label is out of range, we turn:
727 beq reg1, reg2, label
737 with the following opcode replacements:
744 bltzal <-> bgezal (with jal label instead of j label)
746 Even though keeping the delay slot instruction in the delay slot of
747 the branch would be more efficient, it would be very tricky to do
748 correctly, because we'd have to introduce a variable frag *after*
749 the delay slot instruction, and expand that instead. Let's do it
750 the easy way for now, even if the branch-not-taken case now costs
751 one additional instruction. Out-of-range branches are not supposed
752 to be common, anyway.
754 Branch likely. If label is out of range, we turn:
756 beql reg1, reg2, label
757 delay slot (annulled if branch not taken)
766 delay slot (executed only if branch taken)
769 It would be possible to generate a shorter sequence by losing the
770 likely bit, generating something like:
775 delay slot (executed only if branch taken)
787 bltzall -> bgezal (with jal label instead of j label)
788 bgezall -> bltzal (ditto)
791 but it's not clear that it would actually improve performance. */
792 #define RELAX_BRANCH_ENCODE(uncond, likely, link, toofar) \
795 | ((toofar) ? 1 : 0) \
797 | ((likely) ? 4 : 0) \
798 | ((uncond) ? 8 : 0)))
799 #define RELAX_BRANCH_P(i) (((i) & 0xf0000000) == 0xc0000000)
800 #define RELAX_BRANCH_UNCOND(i) (((i) & 8) != 0)
801 #define RELAX_BRANCH_LIKELY(i) (((i) & 4) != 0)
802 #define RELAX_BRANCH_LINK(i) (((i) & 2) != 0)
803 #define RELAX_BRANCH_TOOFAR(i) (((i) & 1) != 0)
805 /* For mips16 code, we use an entirely different form of relaxation.
806 mips16 supports two versions of most instructions which take
807 immediate values: a small one which takes some small value, and a
808 larger one which takes a 16 bit value. Since branches also follow
809 this pattern, relaxing these values is required.
811 We can assemble both mips16 and normal MIPS code in a single
812 object. Therefore, we need to support this type of relaxation at
813 the same time that we support the relaxation described above. We
814 use the high bit of the subtype field to distinguish these cases.
816 The information we store for this type of relaxation is the
817 argument code found in the opcode file for this relocation, whether
818 the user explicitly requested a small or extended form, and whether
819 the relocation is in a jump or jal delay slot. That tells us the
820 size of the value, and how it should be stored. We also store
821 whether the fragment is considered to be extended or not. We also
822 store whether this is known to be a branch to a different section,
823 whether we have tried to relax this frag yet, and whether we have
824 ever extended a PC relative fragment because of a shift count. */
825 #define RELAX_MIPS16_ENCODE(type, small, ext, dslot, jal_dslot) \
828 | ((small) ? 0x100 : 0) \
829 | ((ext) ? 0x200 : 0) \
830 | ((dslot) ? 0x400 : 0) \
831 | ((jal_dslot) ? 0x800 : 0))
832 #define RELAX_MIPS16_P(i) (((i) & 0xc0000000) == 0x80000000)
833 #define RELAX_MIPS16_TYPE(i) ((i) & 0xff)
834 #define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x100) != 0)
835 #define RELAX_MIPS16_USER_EXT(i) (((i) & 0x200) != 0)
836 #define RELAX_MIPS16_DSLOT(i) (((i) & 0x400) != 0)
837 #define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x800) != 0)
838 #define RELAX_MIPS16_EXTENDED(i) (((i) & 0x1000) != 0)
839 #define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x1000)
840 #define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) &~ 0x1000)
841 #define RELAX_MIPS16_LONG_BRANCH(i) (((i) & 0x2000) != 0)
842 #define RELAX_MIPS16_MARK_LONG_BRANCH(i) ((i) | 0x2000)
843 #define RELAX_MIPS16_CLEAR_LONG_BRANCH(i) ((i) &~ 0x2000)
845 /* Is the given value a sign-extended 32-bit value? */
846 #define IS_SEXT_32BIT_NUM(x) \
847 (((x) &~ (offsetT) 0x7fffffff) == 0 \
848 || (((x) &~ (offsetT) 0x7fffffff) == ~ (offsetT) 0x7fffffff))
850 /* Is the given value a sign-extended 16-bit value? */
851 #define IS_SEXT_16BIT_NUM(x) \
852 (((x) &~ (offsetT) 0x7fff) == 0 \
853 || (((x) &~ (offsetT) 0x7fff) == ~ (offsetT) 0x7fff))
855 /* Replace bits MASK << SHIFT of STRUCT with the equivalent bits in
856 VALUE << SHIFT. VALUE is evaluated exactly once. */
857 #define INSERT_BITS(STRUCT, VALUE, MASK, SHIFT) \
858 (STRUCT) = (((STRUCT) & ~((MASK) << (SHIFT))) \
859 | (((VALUE) & (MASK)) << (SHIFT)))
861 /* Extract bits MASK << SHIFT from STRUCT and shift them right
863 #define EXTRACT_BITS(STRUCT, MASK, SHIFT) \
864 (((STRUCT) >> (SHIFT)) & (MASK))
866 /* Change INSN's opcode so that the operand given by FIELD has value VALUE.
867 INSN is a mips_cl_insn structure and VALUE is evaluated exactly once.
869 include/opcode/mips.h specifies operand fields using the macros
870 OP_MASK_<FIELD> and OP_SH_<FIELD>. The MIPS16 equivalents start
871 with "MIPS16OP" instead of "OP". */
872 #define INSERT_OPERAND(FIELD, INSN, VALUE) \
873 INSERT_BITS ((INSN).insn_opcode, VALUE, OP_MASK_##FIELD, OP_SH_##FIELD)
874 #define MIPS16_INSERT_OPERAND(FIELD, INSN, VALUE) \
875 INSERT_BITS ((INSN).insn_opcode, VALUE, \
876 MIPS16OP_MASK_##FIELD, MIPS16OP_SH_##FIELD)
878 /* Extract the operand given by FIELD from mips_cl_insn INSN. */
879 #define EXTRACT_OPERAND(FIELD, INSN) \
880 EXTRACT_BITS ((INSN).insn_opcode, OP_MASK_##FIELD, OP_SH_##FIELD)
881 #define MIPS16_EXTRACT_OPERAND(FIELD, INSN) \
882 EXTRACT_BITS ((INSN).insn_opcode, \
883 MIPS16OP_MASK_##FIELD, \
886 /* Global variables used when generating relaxable macros. See the
887 comment above RELAX_ENCODE for more details about how relaxation
890 /* 0 if we're not emitting a relaxable macro.
891 1 if we're emitting the first of the two relaxation alternatives.
892 2 if we're emitting the second alternative. */
895 /* The first relaxable fixup in the current frag. (In other words,
896 the first fixup that refers to relaxable code.) */
899 /* sizes[0] says how many bytes of the first alternative are stored in
900 the current frag. Likewise sizes[1] for the second alternative. */
901 unsigned int sizes
[2];
903 /* The symbol on which the choice of sequence depends. */
907 /* Global variables used to decide whether a macro needs a warning. */
909 /* True if the macro is in a branch delay slot. */
910 bfd_boolean delay_slot_p
;
912 /* For relaxable macros, sizes[0] is the length of the first alternative
913 in bytes and sizes[1] is the length of the second alternative.
914 For non-relaxable macros, both elements give the length of the
916 unsigned int sizes
[2];
918 /* The first variant frag for this macro. */
920 } mips_macro_warning
;
922 /* Prototypes for static functions. */
924 #define internalError() \
925 as_fatal (_("internal Error, line %d, %s"), __LINE__, __FILE__)
927 enum mips_regclass
{ MIPS_GR_REG
, MIPS_FP_REG
, MIPS16_REG
};
929 static void append_insn
930 (struct mips_cl_insn
*ip
, expressionS
*p
, bfd_reloc_code_real_type
*r
);
931 static void mips_no_prev_insn (void);
932 static void mips16_macro_build
933 (expressionS
*, const char *, const char *, va_list);
934 static void load_register (int, expressionS
*, int);
935 static void macro_start (void);
936 static void macro_end (void);
937 static void macro (struct mips_cl_insn
* ip
);
938 static void mips16_macro (struct mips_cl_insn
* ip
);
939 #ifdef LOSING_COMPILER
940 static void macro2 (struct mips_cl_insn
* ip
);
942 static void mips_ip (char *str
, struct mips_cl_insn
* ip
);
943 static void mips16_ip (char *str
, struct mips_cl_insn
* ip
);
944 static void mips16_immed
945 (char *, unsigned int, int, offsetT
, bfd_boolean
, bfd_boolean
, bfd_boolean
,
946 unsigned long *, bfd_boolean
*, unsigned short *);
947 static size_t my_getSmallExpression
948 (expressionS
*, bfd_reloc_code_real_type
*, char *);
949 static void my_getExpression (expressionS
*, char *);
950 static void s_align (int);
951 static void s_change_sec (int);
952 static void s_change_section (int);
953 static void s_cons (int);
954 static void s_float_cons (int);
955 static void s_mips_globl (int);
956 static void s_option (int);
957 static void s_mipsset (int);
958 static void s_abicalls (int);
959 static void s_cpload (int);
960 static void s_cpsetup (int);
961 static void s_cplocal (int);
962 static void s_cprestore (int);
963 static void s_cpreturn (int);
964 static void s_gpvalue (int);
965 static void s_gpword (int);
966 static void s_gpdword (int);
967 static void s_cpadd (int);
968 static void s_insn (int);
969 static void md_obj_begin (void);
970 static void md_obj_end (void);
971 static void s_mips_ent (int);
972 static void s_mips_end (int);
973 static void s_mips_frame (int);
974 static void s_mips_mask (int reg_type
);
975 static void s_mips_stab (int);
976 static void s_mips_weakext (int);
977 static void s_mips_file (int);
978 static void s_mips_loc (int);
979 static bfd_boolean
pic_need_relax (symbolS
*, asection
*);
980 static int relaxed_branch_length (fragS
*, asection
*, int);
981 static int validate_mips_insn (const struct mips_opcode
*);
983 /* Table and functions used to map between CPU/ISA names, and
984 ISA levels, and CPU numbers. */
988 const char *name
; /* CPU or ISA name. */
989 int is_isa
; /* Is this an ISA? (If 0, a CPU.) */
990 int isa
; /* ISA level. */
991 int cpu
; /* CPU number (default CPU if ISA). */
994 static const struct mips_cpu_info
*mips_parse_cpu (const char *, const char *);
995 static const struct mips_cpu_info
*mips_cpu_info_from_isa (int);
996 static const struct mips_cpu_info
*mips_cpu_info_from_arch (int);
1000 The following pseudo-ops from the Kane and Heinrich MIPS book
1001 should be defined here, but are currently unsupported: .alias,
1002 .galive, .gjaldef, .gjrlive, .livereg, .noalias.
1004 The following pseudo-ops from the Kane and Heinrich MIPS book are
1005 specific to the type of debugging information being generated, and
1006 should be defined by the object format: .aent, .begin, .bend,
1007 .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp,
1010 The following pseudo-ops from the Kane and Heinrich MIPS book are
1011 not MIPS CPU specific, but are also not specific to the object file
1012 format. This file is probably the best place to define them, but
1013 they are not currently supported: .asm0, .endr, .lab, .repeat,
1016 static const pseudo_typeS mips_pseudo_table
[] =
1018 /* MIPS specific pseudo-ops. */
1019 {"option", s_option
, 0},
1020 {"set", s_mipsset
, 0},
1021 {"rdata", s_change_sec
, 'r'},
1022 {"sdata", s_change_sec
, 's'},
1023 {"livereg", s_ignore
, 0},
1024 {"abicalls", s_abicalls
, 0},
1025 {"cpload", s_cpload
, 0},
1026 {"cpsetup", s_cpsetup
, 0},
1027 {"cplocal", s_cplocal
, 0},
1028 {"cprestore", s_cprestore
, 0},
1029 {"cpreturn", s_cpreturn
, 0},
1030 {"gpvalue", s_gpvalue
, 0},
1031 {"gpword", s_gpword
, 0},
1032 {"gpdword", s_gpdword
, 0},
1033 {"cpadd", s_cpadd
, 0},
1034 {"insn", s_insn
, 0},
1036 /* Relatively generic pseudo-ops that happen to be used on MIPS
1038 {"asciiz", stringer
, 1},
1039 {"bss", s_change_sec
, 'b'},
1041 {"half", s_cons
, 1},
1042 {"dword", s_cons
, 3},
1043 {"weakext", s_mips_weakext
, 0},
1045 /* These pseudo-ops are defined in read.c, but must be overridden
1046 here for one reason or another. */
1047 {"align", s_align
, 0},
1048 {"byte", s_cons
, 0},
1049 {"data", s_change_sec
, 'd'},
1050 {"double", s_float_cons
, 'd'},
1051 {"float", s_float_cons
, 'f'},
1052 {"globl", s_mips_globl
, 0},
1053 {"global", s_mips_globl
, 0},
1054 {"hword", s_cons
, 1},
1056 {"long", s_cons
, 2},
1057 {"octa", s_cons
, 4},
1058 {"quad", s_cons
, 3},
1059 {"section", s_change_section
, 0},
1060 {"short", s_cons
, 1},
1061 {"single", s_float_cons
, 'f'},
1062 {"stabn", s_mips_stab
, 'n'},
1063 {"text", s_change_sec
, 't'},
1064 {"word", s_cons
, 2},
1066 { "extern", ecoff_directive_extern
, 0},
1071 static const pseudo_typeS mips_nonecoff_pseudo_table
[] =
1073 /* These pseudo-ops should be defined by the object file format.
1074 However, a.out doesn't support them, so we have versions here. */
1075 {"aent", s_mips_ent
, 1},
1076 {"bgnb", s_ignore
, 0},
1077 {"end", s_mips_end
, 0},
1078 {"endb", s_ignore
, 0},
1079 {"ent", s_mips_ent
, 0},
1080 {"file", s_mips_file
, 0},
1081 {"fmask", s_mips_mask
, 'F'},
1082 {"frame", s_mips_frame
, 0},
1083 {"loc", s_mips_loc
, 0},
1084 {"mask", s_mips_mask
, 'R'},
1085 {"verstamp", s_ignore
, 0},
1089 extern void pop_insert (const pseudo_typeS
*);
1092 mips_pop_insert (void)
1094 pop_insert (mips_pseudo_table
);
1095 if (! ECOFF_DEBUGGING
)
1096 pop_insert (mips_nonecoff_pseudo_table
);
1099 /* Symbols labelling the current insn. */
1101 struct insn_label_list
1103 struct insn_label_list
*next
;
1107 static struct insn_label_list
*insn_labels
;
1108 static struct insn_label_list
*free_insn_labels
;
1110 static void mips_clear_insn_labels (void);
1113 mips_clear_insn_labels (void)
1115 register struct insn_label_list
**pl
;
1117 for (pl
= &free_insn_labels
; *pl
!= NULL
; pl
= &(*pl
)->next
)
1123 static char *expr_end
;
1125 /* Expressions which appear in instructions. These are set by
1128 static expressionS imm_expr
;
1129 static expressionS imm2_expr
;
1130 static expressionS offset_expr
;
1132 /* Relocs associated with imm_expr and offset_expr. */
1134 static bfd_reloc_code_real_type imm_reloc
[3]
1135 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
1136 static bfd_reloc_code_real_type offset_reloc
[3]
1137 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
1139 /* These are set by mips16_ip if an explicit extension is used. */
1141 static bfd_boolean mips16_small
, mips16_ext
;
1144 /* The pdr segment for per procedure frame/regmask info. Not used for
1147 static segT pdr_seg
;
1150 /* The default target format to use. */
1153 mips_target_format (void)
1155 switch (OUTPUT_FLAVOR
)
1157 case bfd_target_ecoff_flavour
:
1158 return target_big_endian
? "ecoff-bigmips" : ECOFF_LITTLE_FORMAT
;
1159 case bfd_target_coff_flavour
:
1161 case bfd_target_elf_flavour
:
1163 /* This is traditional mips. */
1164 return (target_big_endian
1165 ? (HAVE_64BIT_OBJECTS
1166 ? "elf64-tradbigmips"
1168 ? "elf32-ntradbigmips" : "elf32-tradbigmips"))
1169 : (HAVE_64BIT_OBJECTS
1170 ? "elf64-tradlittlemips"
1172 ? "elf32-ntradlittlemips" : "elf32-tradlittlemips")));
1174 return (target_big_endian
1175 ? (HAVE_64BIT_OBJECTS
1178 ? "elf32-nbigmips" : "elf32-bigmips"))
1179 : (HAVE_64BIT_OBJECTS
1180 ? "elf64-littlemips"
1182 ? "elf32-nlittlemips" : "elf32-littlemips")));
1190 /* Return the length of instruction INSN. */
1192 static inline unsigned int
1193 insn_length (const struct mips_cl_insn
*insn
)
1195 if (!mips_opts
.mips16
)
1197 return insn
->mips16_absolute_jump_p
|| insn
->use_extend
? 4 : 2;
1200 /* Initialise INSN from opcode entry MO. Leave its position unspecified. */
1203 create_insn (struct mips_cl_insn
*insn
, const struct mips_opcode
*mo
)
1208 insn
->use_extend
= FALSE
;
1210 insn
->insn_opcode
= mo
->match
;
1213 for (i
= 0; i
< ARRAY_SIZE (insn
->fixp
); i
++)
1214 insn
->fixp
[i
] = NULL
;
1215 insn
->fixed_p
= (mips_opts
.noreorder
> 0);
1216 insn
->noreorder_p
= (mips_opts
.noreorder
> 0);
1217 insn
->mips16_absolute_jump_p
= 0;
1220 /* Install INSN at the location specified by its "frag" and "where" fields. */
1223 install_insn (const struct mips_cl_insn
*insn
)
1225 char *f
= insn
->frag
->fr_literal
+ insn
->where
;
1226 if (!mips_opts
.mips16
)
1227 md_number_to_chars (f
, insn
->insn_opcode
, 4);
1228 else if (insn
->mips16_absolute_jump_p
)
1230 md_number_to_chars (f
, insn
->insn_opcode
>> 16, 2);
1231 md_number_to_chars (f
+ 2, insn
->insn_opcode
& 0xffff, 2);
1235 if (insn
->use_extend
)
1237 md_number_to_chars (f
, 0xf000 | insn
->extend
, 2);
1240 md_number_to_chars (f
, insn
->insn_opcode
, 2);
1244 /* Move INSN to offset WHERE in FRAG. Adjust the fixups accordingly
1245 and install the opcode in the new location. */
1248 move_insn (struct mips_cl_insn
*insn
, fragS
*frag
, long where
)
1253 insn
->where
= where
;
1254 for (i
= 0; i
< ARRAY_SIZE (insn
->fixp
); i
++)
1255 if (insn
->fixp
[i
] != NULL
)
1257 insn
->fixp
[i
]->fx_frag
= frag
;
1258 insn
->fixp
[i
]->fx_where
= where
;
1260 install_insn (insn
);
1263 /* Add INSN to the end of the output. */
1266 add_fixed_insn (struct mips_cl_insn
*insn
)
1268 char *f
= frag_more (insn_length (insn
));
1269 move_insn (insn
, frag_now
, f
- frag_now
->fr_literal
);
1272 /* Start a variant frag and move INSN to the start of the variant part,
1273 marking it as fixed. The other arguments are as for frag_var. */
1276 add_relaxed_insn (struct mips_cl_insn
*insn
, int max_chars
, int var
,
1277 relax_substateT subtype
, symbolS
*symbol
, offsetT offset
)
1279 frag_grow (max_chars
);
1280 move_insn (insn
, frag_now
, frag_more (0) - frag_now
->fr_literal
);
1282 frag_var (rs_machine_dependent
, max_chars
, var
,
1283 subtype
, symbol
, offset
, NULL
);
1286 /* Insert N copies of INSN into the history buffer, starting at
1287 position FIRST. Neither FIRST nor N need to be clipped. */
1290 insert_into_history (unsigned int first
, unsigned int n
,
1291 const struct mips_cl_insn
*insn
)
1293 if (mips_relax
.sequence
!= 2)
1297 for (i
= ARRAY_SIZE (history
); i
-- > first
;)
1299 history
[i
] = history
[i
- n
];
1305 /* Emit a nop instruction, recording it in the history buffer. */
1310 add_fixed_insn (NOP_INSN
);
1311 insert_into_history (0, 1, NOP_INSN
);
1314 /* Initialize vr4120_conflicts. There is a bit of duplication here:
1315 the idea is to make it obvious at a glance that each errata is
1319 init_vr4120_conflicts (void)
1321 #define CONFLICT(FIRST, SECOND) \
1322 vr4120_conflicts[FIX_VR4120_##FIRST] |= 1 << FIX_VR4120_##SECOND
1324 /* Errata 21 - [D]DIV[U] after [D]MACC */
1325 CONFLICT (MACC
, DIV
);
1326 CONFLICT (DMACC
, DIV
);
1328 /* Errata 23 - Continuous DMULT[U]/DMACC instructions. */
1329 CONFLICT (DMULT
, DMULT
);
1330 CONFLICT (DMULT
, DMACC
);
1331 CONFLICT (DMACC
, DMULT
);
1332 CONFLICT (DMACC
, DMACC
);
1334 /* Errata 24 - MT{LO,HI} after [D]MACC */
1335 CONFLICT (MACC
, MTHILO
);
1336 CONFLICT (DMACC
, MTHILO
);
1338 /* VR4181A errata MD(1): "If a MULT, MULTU, DMULT or DMULTU
1339 instruction is executed immediately after a MACC or DMACC
1340 instruction, the result of [either instruction] is incorrect." */
1341 CONFLICT (MACC
, MULT
);
1342 CONFLICT (MACC
, DMULT
);
1343 CONFLICT (DMACC
, MULT
);
1344 CONFLICT (DMACC
, DMULT
);
1346 /* VR4181A errata MD(4): "If a MACC or DMACC instruction is
1347 executed immediately after a DMULT, DMULTU, DIV, DIVU,
1348 DDIV or DDIVU instruction, the result of the MACC or
1349 DMACC instruction is incorrect.". */
1350 CONFLICT (DMULT
, MACC
);
1351 CONFLICT (DMULT
, DMACC
);
1352 CONFLICT (DIV
, MACC
);
1353 CONFLICT (DIV
, DMACC
);
1358 /* This function is called once, at assembler startup time. It should
1359 set up all the tables, etc. that the MD part of the assembler will need. */
1364 register const char *retval
= NULL
;
1368 if (! bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, file_mips_arch
))
1369 as_warn (_("Could not set architecture and machine"));
1371 op_hash
= hash_new ();
1373 for (i
= 0; i
< NUMOPCODES
;)
1375 const char *name
= mips_opcodes
[i
].name
;
1377 retval
= hash_insert (op_hash
, name
, (void *) &mips_opcodes
[i
]);
1380 fprintf (stderr
, _("internal error: can't hash `%s': %s\n"),
1381 mips_opcodes
[i
].name
, retval
);
1382 /* Probably a memory allocation problem? Give up now. */
1383 as_fatal (_("Broken assembler. No assembly attempted."));
1387 if (mips_opcodes
[i
].pinfo
!= INSN_MACRO
)
1389 if (!validate_mips_insn (&mips_opcodes
[i
]))
1391 if (nop_insn
.insn_mo
== NULL
&& strcmp (name
, "nop") == 0)
1393 create_insn (&nop_insn
, mips_opcodes
+ i
);
1394 nop_insn
.fixed_p
= 1;
1399 while ((i
< NUMOPCODES
) && !strcmp (mips_opcodes
[i
].name
, name
));
1402 mips16_op_hash
= hash_new ();
1405 while (i
< bfd_mips16_num_opcodes
)
1407 const char *name
= mips16_opcodes
[i
].name
;
1409 retval
= hash_insert (mips16_op_hash
, name
, (void *) &mips16_opcodes
[i
]);
1411 as_fatal (_("internal: can't hash `%s': %s"),
1412 mips16_opcodes
[i
].name
, retval
);
1415 if (mips16_opcodes
[i
].pinfo
!= INSN_MACRO
1416 && ((mips16_opcodes
[i
].match
& mips16_opcodes
[i
].mask
)
1417 != mips16_opcodes
[i
].match
))
1419 fprintf (stderr
, _("internal error: bad mips16 opcode: %s %s\n"),
1420 mips16_opcodes
[i
].name
, mips16_opcodes
[i
].args
);
1423 if (mips16_nop_insn
.insn_mo
== NULL
&& strcmp (name
, "nop") == 0)
1425 create_insn (&mips16_nop_insn
, mips16_opcodes
+ i
);
1426 mips16_nop_insn
.fixed_p
= 1;
1430 while (i
< bfd_mips16_num_opcodes
1431 && strcmp (mips16_opcodes
[i
].name
, name
) == 0);
1435 as_fatal (_("Broken assembler. No assembly attempted."));
1437 /* We add all the general register names to the symbol table. This
1438 helps us detect invalid uses of them. */
1439 for (i
= 0; i
< 32; i
++)
1443 sprintf (buf
, "$%d", i
);
1444 symbol_table_insert (symbol_new (buf
, reg_section
, i
,
1445 &zero_address_frag
));
1447 symbol_table_insert (symbol_new ("$ra", reg_section
, RA
,
1448 &zero_address_frag
));
1449 symbol_table_insert (symbol_new ("$fp", reg_section
, FP
,
1450 &zero_address_frag
));
1451 symbol_table_insert (symbol_new ("$sp", reg_section
, SP
,
1452 &zero_address_frag
));
1453 symbol_table_insert (symbol_new ("$gp", reg_section
, GP
,
1454 &zero_address_frag
));
1455 symbol_table_insert (symbol_new ("$at", reg_section
, AT
,
1456 &zero_address_frag
));
1457 symbol_table_insert (symbol_new ("$kt0", reg_section
, KT0
,
1458 &zero_address_frag
));
1459 symbol_table_insert (symbol_new ("$kt1", reg_section
, KT1
,
1460 &zero_address_frag
));
1461 symbol_table_insert (symbol_new ("$zero", reg_section
, ZERO
,
1462 &zero_address_frag
));
1463 symbol_table_insert (symbol_new ("$pc", reg_section
, -1,
1464 &zero_address_frag
));
1466 /* If we don't add these register names to the symbol table, they
1467 may end up being added as regular symbols by operand(), and then
1468 make it to the object file as undefined in case they're not
1469 regarded as local symbols. They're local in o32, since `$' is a
1470 local symbol prefix, but not in n32 or n64. */
1471 for (i
= 0; i
< 8; i
++)
1475 sprintf (buf
, "$fcc%i", i
);
1476 symbol_table_insert (symbol_new (buf
, reg_section
, -1,
1477 &zero_address_frag
));
1480 mips_no_prev_insn ();
1483 mips_cprmask
[0] = 0;
1484 mips_cprmask
[1] = 0;
1485 mips_cprmask
[2] = 0;
1486 mips_cprmask
[3] = 0;
1488 /* set the default alignment for the text section (2**2) */
1489 record_alignment (text_section
, 2);
1491 bfd_set_gp_size (stdoutput
, g_switch_value
);
1493 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
1495 /* On a native system, sections must be aligned to 16 byte
1496 boundaries. When configured for an embedded ELF target, we
1498 if (strcmp (TARGET_OS
, "elf") != 0)
1500 (void) bfd_set_section_alignment (stdoutput
, text_section
, 4);
1501 (void) bfd_set_section_alignment (stdoutput
, data_section
, 4);
1502 (void) bfd_set_section_alignment (stdoutput
, bss_section
, 4);
1505 /* Create a .reginfo section for register masks and a .mdebug
1506 section for debugging information. */
1514 subseg
= now_subseg
;
1516 /* The ABI says this section should be loaded so that the
1517 running program can access it. However, we don't load it
1518 if we are configured for an embedded target */
1519 flags
= SEC_READONLY
| SEC_DATA
;
1520 if (strcmp (TARGET_OS
, "elf") != 0)
1521 flags
|= SEC_ALLOC
| SEC_LOAD
;
1523 if (mips_abi
!= N64_ABI
)
1525 sec
= subseg_new (".reginfo", (subsegT
) 0);
1527 bfd_set_section_flags (stdoutput
, sec
, flags
);
1528 bfd_set_section_alignment (stdoutput
, sec
, HAVE_NEWABI
? 3 : 2);
1531 mips_regmask_frag
= frag_more (sizeof (Elf32_External_RegInfo
));
1536 /* The 64-bit ABI uses a .MIPS.options section rather than
1537 .reginfo section. */
1538 sec
= subseg_new (".MIPS.options", (subsegT
) 0);
1539 bfd_set_section_flags (stdoutput
, sec
, flags
);
1540 bfd_set_section_alignment (stdoutput
, sec
, 3);
1543 /* Set up the option header. */
1545 Elf_Internal_Options opthdr
;
1548 opthdr
.kind
= ODK_REGINFO
;
1549 opthdr
.size
= (sizeof (Elf_External_Options
)
1550 + sizeof (Elf64_External_RegInfo
));
1553 f
= frag_more (sizeof (Elf_External_Options
));
1554 bfd_mips_elf_swap_options_out (stdoutput
, &opthdr
,
1555 (Elf_External_Options
*) f
);
1557 mips_regmask_frag
= frag_more (sizeof (Elf64_External_RegInfo
));
1562 if (ECOFF_DEBUGGING
)
1564 sec
= subseg_new (".mdebug", (subsegT
) 0);
1565 (void) bfd_set_section_flags (stdoutput
, sec
,
1566 SEC_HAS_CONTENTS
| SEC_READONLY
);
1567 (void) bfd_set_section_alignment (stdoutput
, sec
, 2);
1570 else if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
&& mips_flag_pdr
)
1572 pdr_seg
= subseg_new (".pdr", (subsegT
) 0);
1573 (void) bfd_set_section_flags (stdoutput
, pdr_seg
,
1574 SEC_READONLY
| SEC_RELOC
1576 (void) bfd_set_section_alignment (stdoutput
, pdr_seg
, 2);
1580 subseg_set (seg
, subseg
);
1584 if (! ECOFF_DEBUGGING
)
1587 if (mips_fix_vr4120
)
1588 init_vr4120_conflicts ();
1594 if (! ECOFF_DEBUGGING
)
1599 md_assemble (char *str
)
1601 struct mips_cl_insn insn
;
1602 bfd_reloc_code_real_type unused_reloc
[3]
1603 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
1605 imm_expr
.X_op
= O_absent
;
1606 imm2_expr
.X_op
= O_absent
;
1607 offset_expr
.X_op
= O_absent
;
1608 imm_reloc
[0] = BFD_RELOC_UNUSED
;
1609 imm_reloc
[1] = BFD_RELOC_UNUSED
;
1610 imm_reloc
[2] = BFD_RELOC_UNUSED
;
1611 offset_reloc
[0] = BFD_RELOC_UNUSED
;
1612 offset_reloc
[1] = BFD_RELOC_UNUSED
;
1613 offset_reloc
[2] = BFD_RELOC_UNUSED
;
1615 if (mips_opts
.mips16
)
1616 mips16_ip (str
, &insn
);
1619 mips_ip (str
, &insn
);
1620 DBG ((_("returned from mips_ip(%s) insn_opcode = 0x%x\n"),
1621 str
, insn
.insn_opcode
));
1626 as_bad ("%s `%s'", insn_error
, str
);
1630 if (insn
.insn_mo
->pinfo
== INSN_MACRO
)
1633 if (mips_opts
.mips16
)
1634 mips16_macro (&insn
);
1641 if (imm_expr
.X_op
!= O_absent
)
1642 append_insn (&insn
, &imm_expr
, imm_reloc
);
1643 else if (offset_expr
.X_op
!= O_absent
)
1644 append_insn (&insn
, &offset_expr
, offset_reloc
);
1646 append_insn (&insn
, NULL
, unused_reloc
);
1650 /* Return true if the given relocation might need a matching %lo().
1651 Note that R_MIPS_GOT16 relocations only need a matching %lo() when
1652 applied to local symbols. */
1654 static inline bfd_boolean
1655 reloc_needs_lo_p (bfd_reloc_code_real_type reloc
)
1657 return (HAVE_IN_PLACE_ADDENDS
1658 && (reloc
== BFD_RELOC_HI16_S
1659 || reloc
== BFD_RELOC_MIPS_GOT16
1660 || reloc
== BFD_RELOC_MIPS16_HI16_S
));
1663 /* Return true if the given fixup is followed by a matching R_MIPS_LO16
1666 static inline bfd_boolean
1667 fixup_has_matching_lo_p (fixS
*fixp
)
1669 return (fixp
->fx_next
!= NULL
1670 && (fixp
->fx_next
->fx_r_type
== BFD_RELOC_LO16
1671 || fixp
->fx_next
->fx_r_type
== BFD_RELOC_MIPS16_LO16
)
1672 && fixp
->fx_addsy
== fixp
->fx_next
->fx_addsy
1673 && fixp
->fx_offset
== fixp
->fx_next
->fx_offset
);
1676 /* See whether instruction IP reads register REG. CLASS is the type
1680 insn_uses_reg (const struct mips_cl_insn
*ip
, unsigned int reg
,
1681 enum mips_regclass
class)
1683 if (class == MIPS16_REG
)
1685 assert (mips_opts
.mips16
);
1686 reg
= mips16_to_32_reg_map
[reg
];
1687 class = MIPS_GR_REG
;
1690 /* Don't report on general register ZERO, since it never changes. */
1691 if (class == MIPS_GR_REG
&& reg
== ZERO
)
1694 if (class == MIPS_FP_REG
)
1696 assert (! mips_opts
.mips16
);
1697 /* If we are called with either $f0 or $f1, we must check $f0.
1698 This is not optimal, because it will introduce an unnecessary
1699 NOP between "lwc1 $f0" and "swc1 $f1". To fix this we would
1700 need to distinguish reading both $f0 and $f1 or just one of
1701 them. Note that we don't have to check the other way,
1702 because there is no instruction that sets both $f0 and $f1
1703 and requires a delay. */
1704 if ((ip
->insn_mo
->pinfo
& INSN_READ_FPR_S
)
1705 && ((EXTRACT_OPERAND (FS
, *ip
) & ~(unsigned) 1)
1706 == (reg
&~ (unsigned) 1)))
1708 if ((ip
->insn_mo
->pinfo
& INSN_READ_FPR_T
)
1709 && ((EXTRACT_OPERAND (FT
, *ip
) & ~(unsigned) 1)
1710 == (reg
&~ (unsigned) 1)))
1713 else if (! mips_opts
.mips16
)
1715 if ((ip
->insn_mo
->pinfo
& INSN_READ_GPR_S
)
1716 && EXTRACT_OPERAND (RS
, *ip
) == reg
)
1718 if ((ip
->insn_mo
->pinfo
& INSN_READ_GPR_T
)
1719 && EXTRACT_OPERAND (RT
, *ip
) == reg
)
1724 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_X
)
1725 && mips16_to_32_reg_map
[MIPS16_EXTRACT_OPERAND (RX
, *ip
)] == reg
)
1727 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_Y
)
1728 && mips16_to_32_reg_map
[MIPS16_EXTRACT_OPERAND (RY
, *ip
)] == reg
)
1730 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_Z
)
1731 && (mips16_to_32_reg_map
[MIPS16_EXTRACT_OPERAND (MOVE32Z
, *ip
)]
1734 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_T
) && reg
== TREG
)
1736 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_SP
) && reg
== SP
)
1738 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_31
) && reg
== RA
)
1740 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_GPR_X
)
1741 && MIPS16_EXTRACT_OPERAND (REGR32
, *ip
) == reg
)
1748 /* This function returns true if modifying a register requires a
1752 reg_needs_delay (unsigned int reg
)
1754 unsigned long prev_pinfo
;
1756 prev_pinfo
= history
[0].insn_mo
->pinfo
;
1757 if (! mips_opts
.noreorder
1758 && (((prev_pinfo
& INSN_LOAD_MEMORY_DELAY
)
1759 && ! gpr_interlocks
)
1760 || ((prev_pinfo
& INSN_LOAD_COPROC_DELAY
)
1761 && ! cop_interlocks
)))
1763 /* A load from a coprocessor or from memory. All load delays
1764 delay the use of general register rt for one instruction. */
1765 /* Itbl support may require additional care here. */
1766 know (prev_pinfo
& INSN_WRITE_GPR_T
);
1767 if (reg
== EXTRACT_OPERAND (RT
, history
[0]))
1774 /* Move all labels in insn_labels to the current insertion point. */
1777 mips_move_labels (void)
1779 struct insn_label_list
*l
;
1782 for (l
= insn_labels
; l
!= NULL
; l
= l
->next
)
1784 assert (S_GET_SEGMENT (l
->label
) == now_seg
);
1785 symbol_set_frag (l
->label
, frag_now
);
1786 val
= (valueT
) frag_now_fix ();
1787 /* mips16 text labels are stored as odd. */
1788 if (mips_opts
.mips16
)
1790 S_SET_VALUE (l
->label
, val
);
1794 /* Mark instruction labels in mips16 mode. This permits the linker to
1795 handle them specially, such as generating jalx instructions when
1796 needed. We also make them odd for the duration of the assembly, in
1797 order to generate the right sort of code. We will make them even
1798 in the adjust_symtab routine, while leaving them marked. This is
1799 convenient for the debugger and the disassembler. The linker knows
1800 to make them odd again. */
1803 mips16_mark_labels (void)
1805 if (mips_opts
.mips16
)
1807 struct insn_label_list
*l
;
1810 for (l
= insn_labels
; l
!= NULL
; l
= l
->next
)
1813 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
1814 S_SET_OTHER (l
->label
, STO_MIPS16
);
1816 val
= S_GET_VALUE (l
->label
);
1818 S_SET_VALUE (l
->label
, val
+ 1);
1823 /* End the current frag. Make it a variant frag and record the
1827 relax_close_frag (void)
1829 mips_macro_warning
.first_frag
= frag_now
;
1830 frag_var (rs_machine_dependent
, 0, 0,
1831 RELAX_ENCODE (mips_relax
.sizes
[0], mips_relax
.sizes
[1]),
1832 mips_relax
.symbol
, 0, (char *) mips_relax
.first_fixup
);
1834 memset (&mips_relax
.sizes
, 0, sizeof (mips_relax
.sizes
));
1835 mips_relax
.first_fixup
= 0;
1838 /* Start a new relaxation sequence whose expansion depends on SYMBOL.
1839 See the comment above RELAX_ENCODE for more details. */
1842 relax_start (symbolS
*symbol
)
1844 assert (mips_relax
.sequence
== 0);
1845 mips_relax
.sequence
= 1;
1846 mips_relax
.symbol
= symbol
;
1849 /* Start generating the second version of a relaxable sequence.
1850 See the comment above RELAX_ENCODE for more details. */
1855 assert (mips_relax
.sequence
== 1);
1856 mips_relax
.sequence
= 2;
1859 /* End the current relaxable sequence. */
1864 assert (mips_relax
.sequence
== 2);
1865 relax_close_frag ();
1866 mips_relax
.sequence
= 0;
1869 /* Classify an instruction according to the FIX_VR4120_* enumeration.
1870 Return NUM_FIX_VR4120_CLASSES if the instruction isn't affected
1871 by VR4120 errata. */
1874 classify_vr4120_insn (const char *name
)
1876 if (strncmp (name
, "macc", 4) == 0)
1877 return FIX_VR4120_MACC
;
1878 if (strncmp (name
, "dmacc", 5) == 0)
1879 return FIX_VR4120_DMACC
;
1880 if (strncmp (name
, "mult", 4) == 0)
1881 return FIX_VR4120_MULT
;
1882 if (strncmp (name
, "dmult", 5) == 0)
1883 return FIX_VR4120_DMULT
;
1884 if (strstr (name
, "div"))
1885 return FIX_VR4120_DIV
;
1886 if (strcmp (name
, "mtlo") == 0 || strcmp (name
, "mthi") == 0)
1887 return FIX_VR4120_MTHILO
;
1888 return NUM_FIX_VR4120_CLASSES
;
1891 /* Return the number of instructions that must separate INSN1 and INSN2,
1892 where INSN1 is the earlier instruction. Return the worst-case value
1893 for any INSN2 if INSN2 is null. */
1896 insns_between (const struct mips_cl_insn
*insn1
,
1897 const struct mips_cl_insn
*insn2
)
1899 unsigned long pinfo1
, pinfo2
;
1901 /* This function needs to know which pinfo flags are set for INSN2
1902 and which registers INSN2 uses. The former is stored in PINFO2 and
1903 the latter is tested via INSN2_USES_REG. If INSN2 is null, PINFO2
1904 will have every flag set and INSN2_USES_REG will always return true. */
1905 pinfo1
= insn1
->insn_mo
->pinfo
;
1906 pinfo2
= insn2
? insn2
->insn_mo
->pinfo
: ~0U;
1908 #define INSN2_USES_REG(REG, CLASS) \
1909 (insn2 == NULL || insn_uses_reg (insn2, REG, CLASS))
1911 /* For most targets, write-after-read dependencies on the HI and LO
1912 registers must be separated by at least two instructions. */
1913 if (!hilo_interlocks
)
1915 if ((pinfo1
& INSN_READ_LO
) && (pinfo2
& INSN_WRITE_LO
))
1917 if ((pinfo1
& INSN_READ_HI
) && (pinfo2
& INSN_WRITE_HI
))
1921 /* If we're working around r7000 errata, there must be two instructions
1922 between an mfhi or mflo and any instruction that uses the result. */
1923 if (mips_7000_hilo_fix
1924 && MF_HILO_INSN (pinfo1
)
1925 && INSN2_USES_REG (EXTRACT_OPERAND (RD
, *insn1
), MIPS_GR_REG
))
1928 /* If working around VR4120 errata, check for combinations that need
1929 a single intervening instruction. */
1930 if (mips_fix_vr4120
)
1932 unsigned int class1
, class2
;
1934 class1
= classify_vr4120_insn (insn1
->insn_mo
->name
);
1935 if (class1
!= NUM_FIX_VR4120_CLASSES
&& vr4120_conflicts
[class1
] != 0)
1939 class2
= classify_vr4120_insn (insn2
->insn_mo
->name
);
1940 if (vr4120_conflicts
[class1
] & (1 << class2
))
1945 if (!mips_opts
.mips16
)
1947 /* Check for GPR or coprocessor load delays. All such delays
1948 are on the RT register. */
1949 /* Itbl support may require additional care here. */
1950 if ((!gpr_interlocks
&& (pinfo1
& INSN_LOAD_MEMORY_DELAY
))
1951 || (!cop_interlocks
&& (pinfo1
& INSN_LOAD_COPROC_DELAY
)))
1953 know (pinfo1
& INSN_WRITE_GPR_T
);
1954 if (INSN2_USES_REG (EXTRACT_OPERAND (RT
, *insn1
), MIPS_GR_REG
))
1958 /* Check for generic coprocessor hazards.
1960 This case is not handled very well. There is no special
1961 knowledge of CP0 handling, and the coprocessors other than
1962 the floating point unit are not distinguished at all. */
1963 /* Itbl support may require additional care here. FIXME!
1964 Need to modify this to include knowledge about
1965 user specified delays! */
1966 else if ((!cop_interlocks
&& (pinfo1
& INSN_COPROC_MOVE_DELAY
))
1967 || (!cop_mem_interlocks
&& (pinfo1
& INSN_COPROC_MEMORY_DELAY
)))
1969 /* Handle cases where INSN1 writes to a known general coprocessor
1970 register. There must be a one instruction delay before INSN2
1971 if INSN2 reads that register, otherwise no delay is needed. */
1972 if (pinfo1
& INSN_WRITE_FPR_T
)
1974 if (INSN2_USES_REG (EXTRACT_OPERAND (FT
, *insn1
), MIPS_FP_REG
))
1977 else if (pinfo1
& INSN_WRITE_FPR_S
)
1979 if (INSN2_USES_REG (EXTRACT_OPERAND (FS
, *insn1
), MIPS_FP_REG
))
1984 /* Read-after-write dependencies on the control registers
1985 require a two-instruction gap. */
1986 if ((pinfo1
& INSN_WRITE_COND_CODE
)
1987 && (pinfo2
& INSN_READ_COND_CODE
))
1990 /* We don't know exactly what INSN1 does. If INSN2 is
1991 also a coprocessor instruction, assume there must be
1992 a one instruction gap. */
1993 if (pinfo2
& INSN_COP
)
1998 /* Check for read-after-write dependencies on the coprocessor
1999 control registers in cases where INSN1 does not need a general
2000 coprocessor delay. This means that INSN1 is a floating point
2001 comparison instruction. */
2002 /* Itbl support may require additional care here. */
2003 else if (!cop_interlocks
2004 && (pinfo1
& INSN_WRITE_COND_CODE
)
2005 && (pinfo2
& INSN_READ_COND_CODE
))
2009 #undef INSN2_USES_REG
2014 /* Return the number of nops that would be needed if instruction INSN
2015 immediately followed the MAX_NOPS instructions given by HISTORY,
2016 where HISTORY[0] is the most recent instruction. If INSN is null,
2017 return the worse-case number of nops for any instruction. */
2020 nops_for_insn (const struct mips_cl_insn
*history
,
2021 const struct mips_cl_insn
*insn
)
2023 int i
, nops
, tmp_nops
;
2026 for (i
= 0; i
< MAX_NOPS
; i
++)
2027 if (!history
[i
].noreorder_p
)
2029 tmp_nops
= insns_between (history
+ i
, insn
) - i
;
2030 if (tmp_nops
> nops
)
2036 /* The variable arguments provide NUM_INSNS extra instructions that
2037 might be added to HISTORY. Return the largest number of nops that
2038 would be needed after the extended sequence. */
2041 nops_for_sequence (int num_insns
, const struct mips_cl_insn
*history
, ...)
2044 struct mips_cl_insn buffer
[MAX_NOPS
];
2045 struct mips_cl_insn
*cursor
;
2048 va_start (args
, history
);
2049 cursor
= buffer
+ num_insns
;
2050 memcpy (cursor
, history
, (MAX_NOPS
- num_insns
) * sizeof (*cursor
));
2051 while (cursor
> buffer
)
2052 *--cursor
= *va_arg (args
, const struct mips_cl_insn
*);
2054 nops
= nops_for_insn (buffer
, NULL
);
2059 /* Like nops_for_insn, but if INSN is a branch, take into account the
2060 worst-case delay for the branch target. */
2063 nops_for_insn_or_target (const struct mips_cl_insn
*history
,
2064 const struct mips_cl_insn
*insn
)
2068 nops
= nops_for_insn (history
, insn
);
2069 if (insn
->insn_mo
->pinfo
& (INSN_UNCOND_BRANCH_DELAY
2070 | INSN_COND_BRANCH_DELAY
2071 | INSN_COND_BRANCH_LIKELY
))
2073 tmp_nops
= nops_for_sequence (2, history
, insn
, NOP_INSN
);
2074 if (tmp_nops
> nops
)
2077 else if (mips_opts
.mips16
&& (insn
->insn_mo
->pinfo
& MIPS16_INSN_BRANCH
))
2079 tmp_nops
= nops_for_sequence (1, history
, insn
);
2080 if (tmp_nops
> nops
)
2086 /* Output an instruction. IP is the instruction information.
2087 ADDRESS_EXPR is an operand of the instruction to be used with
2091 append_insn (struct mips_cl_insn
*ip
, expressionS
*address_expr
,
2092 bfd_reloc_code_real_type
*reloc_type
)
2094 register unsigned long prev_pinfo
, pinfo
;
2095 relax_stateT prev_insn_frag_type
= 0;
2096 bfd_boolean relaxed_branch
= FALSE
;
2098 /* Mark instruction labels in mips16 mode. */
2099 mips16_mark_labels ();
2101 prev_pinfo
= history
[0].insn_mo
->pinfo
;
2102 pinfo
= ip
->insn_mo
->pinfo
;
2104 if (mips_relax
.sequence
!= 2 && !mips_opts
.noreorder
)
2106 /* There are a lot of optimizations we could do that we don't.
2107 In particular, we do not, in general, reorder instructions.
2108 If you use gcc with optimization, it will reorder
2109 instructions and generally do much more optimization then we
2110 do here; repeating all that work in the assembler would only
2111 benefit hand written assembly code, and does not seem worth
2113 int nops
= (mips_optimize
== 0
2114 ? nops_for_insn (history
, NULL
)
2115 : nops_for_insn_or_target (history
, ip
));
2119 unsigned long old_frag_offset
;
2122 old_frag
= frag_now
;
2123 old_frag_offset
= frag_now_fix ();
2125 for (i
= 0; i
< nops
; i
++)
2130 listing_prev_line ();
2131 /* We may be at the start of a variant frag. In case we
2132 are, make sure there is enough space for the frag
2133 after the frags created by listing_prev_line. The
2134 argument to frag_grow here must be at least as large
2135 as the argument to all other calls to frag_grow in
2136 this file. We don't have to worry about being in the
2137 middle of a variant frag, because the variants insert
2138 all needed nop instructions themselves. */
2142 mips_move_labels ();
2144 #ifndef NO_ECOFF_DEBUGGING
2145 if (ECOFF_DEBUGGING
)
2146 ecoff_fix_loc (old_frag
, old_frag_offset
);
2150 else if (mips_relax
.sequence
!= 2 && prev_nop_frag
!= NULL
)
2152 /* Work out how many nops in prev_nop_frag are needed by IP. */
2153 int nops
= nops_for_insn_or_target (history
, ip
);
2154 assert (nops
<= prev_nop_frag_holds
);
2156 /* Enforce NOPS as a minimum. */
2157 if (nops
> prev_nop_frag_required
)
2158 prev_nop_frag_required
= nops
;
2160 if (prev_nop_frag_holds
== prev_nop_frag_required
)
2162 /* Settle for the current number of nops. Update the history
2163 accordingly (for the benefit of any future .set reorder code). */
2164 prev_nop_frag
= NULL
;
2165 insert_into_history (prev_nop_frag_since
,
2166 prev_nop_frag_holds
, NOP_INSN
);
2170 /* Allow this instruction to replace one of the nops that was
2171 tentatively added to prev_nop_frag. */
2172 prev_nop_frag
->fr_fix
-= mips_opts
.mips16
? 2 : 4;
2173 prev_nop_frag_holds
--;
2174 prev_nop_frag_since
++;
2179 /* The value passed to dwarf2_emit_insn is the distance between
2180 the beginning of the current instruction and the address that
2181 should be recorded in the debug tables. For MIPS16 debug info
2182 we want to use ISA-encoded addresses, so we pass -1 for an
2183 address higher by one than the current. */
2184 dwarf2_emit_insn (mips_opts
.mips16
? -1 : 0);
2187 /* Record the frag type before frag_var. */
2188 if (history
[0].frag
)
2189 prev_insn_frag_type
= history
[0].frag
->fr_type
;
2192 && *reloc_type
== BFD_RELOC_16_PCREL_S2
2193 && (pinfo
& INSN_UNCOND_BRANCH_DELAY
|| pinfo
& INSN_COND_BRANCH_DELAY
2194 || pinfo
& INSN_COND_BRANCH_LIKELY
)
2195 && mips_relax_branch
2196 /* Don't try branch relaxation within .set nomacro, or within
2197 .set noat if we use $at for PIC computations. If it turns
2198 out that the branch was out-of-range, we'll get an error. */
2199 && !mips_opts
.warn_about_macros
2200 && !(mips_opts
.noat
&& mips_pic
!= NO_PIC
)
2201 && !mips_opts
.mips16
)
2203 relaxed_branch
= TRUE
;
2204 add_relaxed_insn (ip
, (relaxed_branch_length
2206 (pinfo
& INSN_UNCOND_BRANCH_DELAY
) ? -1
2207 : (pinfo
& INSN_COND_BRANCH_LIKELY
) ? 1
2210 (pinfo
& INSN_UNCOND_BRANCH_DELAY
,
2211 pinfo
& INSN_COND_BRANCH_LIKELY
,
2212 pinfo
& INSN_WRITE_GPR_31
,
2214 address_expr
->X_add_symbol
,
2215 address_expr
->X_add_number
);
2216 *reloc_type
= BFD_RELOC_UNUSED
;
2218 else if (*reloc_type
> BFD_RELOC_UNUSED
)
2220 /* We need to set up a variant frag. */
2221 assert (mips_opts
.mips16
&& address_expr
!= NULL
);
2222 add_relaxed_insn (ip
, 4, 0,
2224 (*reloc_type
- BFD_RELOC_UNUSED
,
2225 mips16_small
, mips16_ext
,
2226 prev_pinfo
& INSN_UNCOND_BRANCH_DELAY
,
2227 history
[0].mips16_absolute_jump_p
),
2228 make_expr_symbol (address_expr
), 0);
2230 else if (mips_opts
.mips16
2232 && *reloc_type
!= BFD_RELOC_MIPS16_JMP
)
2234 /* Make sure there is enough room to swap this instruction with
2235 a following jump instruction. */
2237 add_fixed_insn (ip
);
2241 if (mips_opts
.mips16
2242 && mips_opts
.noreorder
2243 && (prev_pinfo
& INSN_UNCOND_BRANCH_DELAY
) != 0)
2244 as_warn (_("extended instruction in delay slot"));
2246 if (mips_relax
.sequence
)
2248 /* If we've reached the end of this frag, turn it into a variant
2249 frag and record the information for the instructions we've
2251 if (frag_room () < 4)
2252 relax_close_frag ();
2253 mips_relax
.sizes
[mips_relax
.sequence
- 1] += 4;
2256 if (mips_relax
.sequence
!= 2)
2257 mips_macro_warning
.sizes
[0] += 4;
2258 if (mips_relax
.sequence
!= 1)
2259 mips_macro_warning
.sizes
[1] += 4;
2261 if (mips_opts
.mips16
)
2264 ip
->mips16_absolute_jump_p
= (*reloc_type
== BFD_RELOC_MIPS16_JMP
);
2266 add_fixed_insn (ip
);
2269 if (address_expr
!= NULL
&& *reloc_type
<= BFD_RELOC_UNUSED
)
2271 if (address_expr
->X_op
== O_constant
)
2275 switch (*reloc_type
)
2278 ip
->insn_opcode
|= address_expr
->X_add_number
;
2281 case BFD_RELOC_MIPS_HIGHEST
:
2282 tmp
= (address_expr
->X_add_number
+ 0x800080008000ull
) >> 48;
2283 ip
->insn_opcode
|= tmp
& 0xffff;
2286 case BFD_RELOC_MIPS_HIGHER
:
2287 tmp
= (address_expr
->X_add_number
+ 0x80008000ull
) >> 32;
2288 ip
->insn_opcode
|= tmp
& 0xffff;
2291 case BFD_RELOC_HI16_S
:
2292 tmp
= (address_expr
->X_add_number
+ 0x8000) >> 16;
2293 ip
->insn_opcode
|= tmp
& 0xffff;
2296 case BFD_RELOC_HI16
:
2297 ip
->insn_opcode
|= (address_expr
->X_add_number
>> 16) & 0xffff;
2300 case BFD_RELOC_UNUSED
:
2301 case BFD_RELOC_LO16
:
2302 case BFD_RELOC_MIPS_GOT_DISP
:
2303 ip
->insn_opcode
|= address_expr
->X_add_number
& 0xffff;
2306 case BFD_RELOC_MIPS_JMP
:
2307 if ((address_expr
->X_add_number
& 3) != 0)
2308 as_bad (_("jump to misaligned address (0x%lx)"),
2309 (unsigned long) address_expr
->X_add_number
);
2310 if (address_expr
->X_add_number
& ~0xfffffff)
2311 as_bad (_("jump address range overflow (0x%lx)"),
2312 (unsigned long) address_expr
->X_add_number
);
2313 ip
->insn_opcode
|= (address_expr
->X_add_number
>> 2) & 0x3ffffff;
2316 case BFD_RELOC_MIPS16_JMP
:
2317 if ((address_expr
->X_add_number
& 3) != 0)
2318 as_bad (_("jump to misaligned address (0x%lx)"),
2319 (unsigned long) address_expr
->X_add_number
);
2320 if (address_expr
->X_add_number
& ~0xfffffff)
2321 as_bad (_("jump address range overflow (0x%lx)"),
2322 (unsigned long) address_expr
->X_add_number
);
2324 (((address_expr
->X_add_number
& 0x7c0000) << 3)
2325 | ((address_expr
->X_add_number
& 0xf800000) >> 7)
2326 | ((address_expr
->X_add_number
& 0x3fffc) >> 2));
2329 case BFD_RELOC_16_PCREL_S2
:
2336 else if (*reloc_type
< BFD_RELOC_UNUSED
)
2339 reloc_howto_type
*howto
;
2342 /* In a compound relocation, it is the final (outermost)
2343 operator that determines the relocated field. */
2344 for (i
= 1; i
< 3; i
++)
2345 if (reloc_type
[i
] == BFD_RELOC_UNUSED
)
2348 howto
= bfd_reloc_type_lookup (stdoutput
, reloc_type
[i
- 1]);
2349 ip
->fixp
[0] = fix_new_exp (ip
->frag
, ip
->where
,
2350 bfd_get_reloc_size (howto
),
2352 reloc_type
[0] == BFD_RELOC_16_PCREL_S2
,
2355 /* These relocations can have an addend that won't fit in
2356 4 octets for 64bit assembly. */
2358 && ! howto
->partial_inplace
2359 && (reloc_type
[0] == BFD_RELOC_16
2360 || reloc_type
[0] == BFD_RELOC_32
2361 || reloc_type
[0] == BFD_RELOC_MIPS_JMP
2362 || reloc_type
[0] == BFD_RELOC_HI16_S
2363 || reloc_type
[0] == BFD_RELOC_LO16
2364 || reloc_type
[0] == BFD_RELOC_GPREL16
2365 || reloc_type
[0] == BFD_RELOC_MIPS_LITERAL
2366 || reloc_type
[0] == BFD_RELOC_GPREL32
2367 || reloc_type
[0] == BFD_RELOC_64
2368 || reloc_type
[0] == BFD_RELOC_CTOR
2369 || reloc_type
[0] == BFD_RELOC_MIPS_SUB
2370 || reloc_type
[0] == BFD_RELOC_MIPS_HIGHEST
2371 || reloc_type
[0] == BFD_RELOC_MIPS_HIGHER
2372 || reloc_type
[0] == BFD_RELOC_MIPS_SCN_DISP
2373 || reloc_type
[0] == BFD_RELOC_MIPS_REL16
2374 || reloc_type
[0] == BFD_RELOC_MIPS_RELGOT
2375 || reloc_type
[0] == BFD_RELOC_MIPS16_GPREL
2376 || reloc_type
[0] == BFD_RELOC_MIPS16_HI16_S
2377 || reloc_type
[0] == BFD_RELOC_MIPS16_LO16
))
2378 ip
->fixp
[0]->fx_no_overflow
= 1;
2380 if (mips_relax
.sequence
)
2382 if (mips_relax
.first_fixup
== 0)
2383 mips_relax
.first_fixup
= ip
->fixp
[0];
2385 else if (reloc_needs_lo_p (*reloc_type
))
2387 struct mips_hi_fixup
*hi_fixup
;
2389 /* Reuse the last entry if it already has a matching %lo. */
2390 hi_fixup
= mips_hi_fixup_list
;
2392 || !fixup_has_matching_lo_p (hi_fixup
->fixp
))
2394 hi_fixup
= ((struct mips_hi_fixup
*)
2395 xmalloc (sizeof (struct mips_hi_fixup
)));
2396 hi_fixup
->next
= mips_hi_fixup_list
;
2397 mips_hi_fixup_list
= hi_fixup
;
2399 hi_fixup
->fixp
= ip
->fixp
[0];
2400 hi_fixup
->seg
= now_seg
;
2403 /* Add fixups for the second and third relocations, if given.
2404 Note that the ABI allows the second relocation to be
2405 against RSS_UNDEF, RSS_GP, RSS_GP0 or RSS_LOC. At the
2406 moment we only use RSS_UNDEF, but we could add support
2407 for the others if it ever becomes necessary. */
2408 for (i
= 1; i
< 3; i
++)
2409 if (reloc_type
[i
] != BFD_RELOC_UNUSED
)
2411 ip
->fixp
[i
] = fix_new (ip
->frag
, ip
->where
,
2412 ip
->fixp
[0]->fx_size
, NULL
, 0,
2413 FALSE
, reloc_type
[i
]);
2415 /* Use fx_tcbit to mark compound relocs. */
2416 ip
->fixp
[0]->fx_tcbit
= 1;
2417 ip
->fixp
[i
]->fx_tcbit
= 1;
2423 /* Update the register mask information. */
2424 if (! mips_opts
.mips16
)
2426 if (pinfo
& INSN_WRITE_GPR_D
)
2427 mips_gprmask
|= 1 << EXTRACT_OPERAND (RD
, *ip
);
2428 if ((pinfo
& (INSN_WRITE_GPR_T
| INSN_READ_GPR_T
)) != 0)
2429 mips_gprmask
|= 1 << EXTRACT_OPERAND (RT
, *ip
);
2430 if (pinfo
& INSN_READ_GPR_S
)
2431 mips_gprmask
|= 1 << EXTRACT_OPERAND (RS
, *ip
);
2432 if (pinfo
& INSN_WRITE_GPR_31
)
2433 mips_gprmask
|= 1 << RA
;
2434 if (pinfo
& INSN_WRITE_FPR_D
)
2435 mips_cprmask
[1] |= 1 << EXTRACT_OPERAND (FD
, *ip
);
2436 if ((pinfo
& (INSN_WRITE_FPR_S
| INSN_READ_FPR_S
)) != 0)
2437 mips_cprmask
[1] |= 1 << EXTRACT_OPERAND (FS
, *ip
);
2438 if ((pinfo
& (INSN_WRITE_FPR_T
| INSN_READ_FPR_T
)) != 0)
2439 mips_cprmask
[1] |= 1 << EXTRACT_OPERAND (FT
, *ip
);
2440 if ((pinfo
& INSN_READ_FPR_R
) != 0)
2441 mips_cprmask
[1] |= 1 << EXTRACT_OPERAND (FR
, *ip
);
2442 if (pinfo
& INSN_COP
)
2444 /* We don't keep enough information to sort these cases out.
2445 The itbl support does keep this information however, although
2446 we currently don't support itbl fprmats as part of the cop
2447 instruction. May want to add this support in the future. */
2449 /* Never set the bit for $0, which is always zero. */
2450 mips_gprmask
&= ~1 << 0;
2454 if (pinfo
& (MIPS16_INSN_WRITE_X
| MIPS16_INSN_READ_X
))
2455 mips_gprmask
|= 1 << MIPS16_EXTRACT_OPERAND (RX
, *ip
);
2456 if (pinfo
& (MIPS16_INSN_WRITE_Y
| MIPS16_INSN_READ_Y
))
2457 mips_gprmask
|= 1 << MIPS16_EXTRACT_OPERAND (RY
, *ip
);
2458 if (pinfo
& MIPS16_INSN_WRITE_Z
)
2459 mips_gprmask
|= 1 << MIPS16_EXTRACT_OPERAND (RZ
, *ip
);
2460 if (pinfo
& (MIPS16_INSN_WRITE_T
| MIPS16_INSN_READ_T
))
2461 mips_gprmask
|= 1 << TREG
;
2462 if (pinfo
& (MIPS16_INSN_WRITE_SP
| MIPS16_INSN_READ_SP
))
2463 mips_gprmask
|= 1 << SP
;
2464 if (pinfo
& (MIPS16_INSN_WRITE_31
| MIPS16_INSN_READ_31
))
2465 mips_gprmask
|= 1 << RA
;
2466 if (pinfo
& MIPS16_INSN_WRITE_GPR_Y
)
2467 mips_gprmask
|= 1 << MIPS16OP_EXTRACT_REG32R (ip
->insn_opcode
);
2468 if (pinfo
& MIPS16_INSN_READ_Z
)
2469 mips_gprmask
|= 1 << MIPS16_EXTRACT_OPERAND (MOVE32Z
, *ip
);
2470 if (pinfo
& MIPS16_INSN_READ_GPR_X
)
2471 mips_gprmask
|= 1 << MIPS16_EXTRACT_OPERAND (REGR32
, *ip
);
2474 if (mips_relax
.sequence
!= 2 && !mips_opts
.noreorder
)
2476 /* Filling the branch delay slot is more complex. We try to
2477 switch the branch with the previous instruction, which we can
2478 do if the previous instruction does not set up a condition
2479 that the branch tests and if the branch is not itself the
2480 target of any branch. */
2481 if ((pinfo
& INSN_UNCOND_BRANCH_DELAY
)
2482 || (pinfo
& INSN_COND_BRANCH_DELAY
))
2484 if (mips_optimize
< 2
2485 /* If we have seen .set volatile or .set nomove, don't
2487 || mips_opts
.nomove
!= 0
2488 /* We can't swap if the previous instruction's position
2490 || history
[0].fixed_p
2491 /* If the previous previous insn was in a .set
2492 noreorder, we can't swap. Actually, the MIPS
2493 assembler will swap in this situation. However, gcc
2494 configured -with-gnu-as will generate code like
2500 in which we can not swap the bne and INSN. If gcc is
2501 not configured -with-gnu-as, it does not output the
2503 || history
[1].noreorder_p
2504 /* If the branch is itself the target of a branch, we
2505 can not swap. We cheat on this; all we check for is
2506 whether there is a label on this instruction. If
2507 there are any branches to anything other than a
2508 label, users must use .set noreorder. */
2509 || insn_labels
!= NULL
2510 /* If the previous instruction is in a variant frag
2511 other than this branch's one, we cannot do the swap.
2512 This does not apply to the mips16, which uses variant
2513 frags for different purposes. */
2514 || (! mips_opts
.mips16
2515 && prev_insn_frag_type
== rs_machine_dependent
)
2516 /* Check for conflicts between the branch and the instructions
2517 before the candidate delay slot. */
2518 || nops_for_insn (history
+ 1, ip
) > 0
2519 /* Check for conflicts between the swapped sequence and the
2520 target of the branch. */
2521 || nops_for_sequence (2, history
+ 1, ip
, history
) > 0
2522 /* We do not swap with a trap instruction, since it
2523 complicates trap handlers to have the trap
2524 instruction be in a delay slot. */
2525 || (prev_pinfo
& INSN_TRAP
)
2526 /* If the branch reads a register that the previous
2527 instruction sets, we can not swap. */
2528 || (! mips_opts
.mips16
2529 && (prev_pinfo
& INSN_WRITE_GPR_T
)
2530 && insn_uses_reg (ip
, EXTRACT_OPERAND (RT
, history
[0]),
2532 || (! mips_opts
.mips16
2533 && (prev_pinfo
& INSN_WRITE_GPR_D
)
2534 && insn_uses_reg (ip
, EXTRACT_OPERAND (RD
, history
[0]),
2536 || (mips_opts
.mips16
2537 && (((prev_pinfo
& MIPS16_INSN_WRITE_X
)
2539 (ip
, MIPS16_EXTRACT_OPERAND (RX
, history
[0]),
2541 || ((prev_pinfo
& MIPS16_INSN_WRITE_Y
)
2543 (ip
, MIPS16_EXTRACT_OPERAND (RY
, history
[0]),
2545 || ((prev_pinfo
& MIPS16_INSN_WRITE_Z
)
2547 (ip
, MIPS16_EXTRACT_OPERAND (RZ
, history
[0]),
2549 || ((prev_pinfo
& MIPS16_INSN_WRITE_T
)
2550 && insn_uses_reg (ip
, TREG
, MIPS_GR_REG
))
2551 || ((prev_pinfo
& MIPS16_INSN_WRITE_31
)
2552 && insn_uses_reg (ip
, RA
, MIPS_GR_REG
))
2553 || ((prev_pinfo
& MIPS16_INSN_WRITE_GPR_Y
)
2554 && insn_uses_reg (ip
,
2555 MIPS16OP_EXTRACT_REG32R
2556 (history
[0].insn_opcode
),
2558 /* If the branch writes a register that the previous
2559 instruction sets, we can not swap (we know that
2560 branches write only to RD or to $31). */
2561 || (! mips_opts
.mips16
2562 && (prev_pinfo
& INSN_WRITE_GPR_T
)
2563 && (((pinfo
& INSN_WRITE_GPR_D
)
2564 && (EXTRACT_OPERAND (RT
, history
[0])
2565 == EXTRACT_OPERAND (RD
, *ip
)))
2566 || ((pinfo
& INSN_WRITE_GPR_31
)
2567 && EXTRACT_OPERAND (RT
, history
[0]) == RA
)))
2568 || (! mips_opts
.mips16
2569 && (prev_pinfo
& INSN_WRITE_GPR_D
)
2570 && (((pinfo
& INSN_WRITE_GPR_D
)
2571 && (EXTRACT_OPERAND (RD
, history
[0])
2572 == EXTRACT_OPERAND (RD
, *ip
)))
2573 || ((pinfo
& INSN_WRITE_GPR_31
)
2574 && EXTRACT_OPERAND (RD
, history
[0]) == RA
)))
2575 || (mips_opts
.mips16
2576 && (pinfo
& MIPS16_INSN_WRITE_31
)
2577 && ((prev_pinfo
& MIPS16_INSN_WRITE_31
)
2578 || ((prev_pinfo
& MIPS16_INSN_WRITE_GPR_Y
)
2579 && (MIPS16OP_EXTRACT_REG32R (history
[0].insn_opcode
)
2581 /* If the branch writes a register that the previous
2582 instruction reads, we can not swap (we know that
2583 branches only write to RD or to $31). */
2584 || (! mips_opts
.mips16
2585 && (pinfo
& INSN_WRITE_GPR_D
)
2586 && insn_uses_reg (&history
[0],
2587 EXTRACT_OPERAND (RD
, *ip
),
2589 || (! mips_opts
.mips16
2590 && (pinfo
& INSN_WRITE_GPR_31
)
2591 && insn_uses_reg (&history
[0], RA
, MIPS_GR_REG
))
2592 || (mips_opts
.mips16
2593 && (pinfo
& MIPS16_INSN_WRITE_31
)
2594 && insn_uses_reg (&history
[0], RA
, MIPS_GR_REG
))
2595 /* If one instruction sets a condition code and the
2596 other one uses a condition code, we can not swap. */
2597 || ((pinfo
& INSN_READ_COND_CODE
)
2598 && (prev_pinfo
& INSN_WRITE_COND_CODE
))
2599 || ((pinfo
& INSN_WRITE_COND_CODE
)
2600 && (prev_pinfo
& INSN_READ_COND_CODE
))
2601 /* If the previous instruction uses the PC, we can not
2603 || (mips_opts
.mips16
2604 && (prev_pinfo
& MIPS16_INSN_READ_PC
))
2605 /* If the previous instruction had a fixup in mips16
2606 mode, we can not swap. This normally means that the
2607 previous instruction was a 4 byte branch anyhow. */
2608 || (mips_opts
.mips16
&& history
[0].fixp
[0])
2609 /* If the previous instruction is a sync, sync.l, or
2610 sync.p, we can not swap. */
2611 || (prev_pinfo
& INSN_SYNC
))
2613 /* We could do even better for unconditional branches to
2614 portions of this object file; we could pick up the
2615 instruction at the destination, put it in the delay
2616 slot, and bump the destination address. */
2617 insert_into_history (0, 1, ip
);
2619 if (mips_relax
.sequence
)
2620 mips_relax
.sizes
[mips_relax
.sequence
- 1] += 4;
2624 /* It looks like we can actually do the swap. */
2625 struct mips_cl_insn delay
= history
[0];
2626 if (mips_opts
.mips16
)
2628 know (delay
.frag
== ip
->frag
);
2629 move_insn (ip
, delay
.frag
, delay
.where
);
2630 move_insn (&delay
, ip
->frag
, ip
->where
+ insn_length (ip
));
2632 else if (relaxed_branch
)
2634 /* Add the delay slot instruction to the end of the
2635 current frag and shrink the fixed part of the
2636 original frag. If the branch occupies the tail of
2637 the latter, move it backwards to cover the gap. */
2638 delay
.frag
->fr_fix
-= 4;
2639 if (delay
.frag
== ip
->frag
)
2640 move_insn (ip
, ip
->frag
, ip
->where
- 4);
2641 add_fixed_insn (&delay
);
2645 move_insn (&delay
, ip
->frag
, ip
->where
);
2646 move_insn (ip
, history
[0].frag
, history
[0].where
);
2650 insert_into_history (0, 1, &delay
);
2653 /* If that was an unconditional branch, forget the previous
2654 insn information. */
2655 if (pinfo
& INSN_UNCOND_BRANCH_DELAY
)
2656 mips_no_prev_insn ();
2658 else if (pinfo
& INSN_COND_BRANCH_LIKELY
)
2660 /* We don't yet optimize a branch likely. What we should do
2661 is look at the target, copy the instruction found there
2662 into the delay slot, and increment the branch to jump to
2663 the next instruction. */
2664 insert_into_history (0, 1, ip
);
2668 insert_into_history (0, 1, ip
);
2671 insert_into_history (0, 1, ip
);
2673 /* We just output an insn, so the next one doesn't have a label. */
2674 mips_clear_insn_labels ();
2677 /* Forget that there was any previous instruction or label. */
2680 mips_no_prev_insn (void)
2682 prev_nop_frag
= NULL
;
2683 insert_into_history (0, ARRAY_SIZE (history
), NOP_INSN
);
2684 mips_clear_insn_labels ();
2687 /* This function must be called before we emit something other than
2688 instructions. It is like mips_no_prev_insn except that it inserts
2689 any NOPS that might be needed by previous instructions. */
2692 mips_emit_delays (void)
2694 if (! mips_opts
.noreorder
)
2696 int nops
= nops_for_insn (history
, NULL
);
2700 add_fixed_insn (NOP_INSN
);
2701 mips_move_labels ();
2704 mips_no_prev_insn ();
2707 /* Start a (possibly nested) noreorder block. */
2710 start_noreorder (void)
2712 if (mips_opts
.noreorder
== 0)
2717 /* None of the instructions before the .set noreorder can be moved. */
2718 for (i
= 0; i
< ARRAY_SIZE (history
); i
++)
2719 history
[i
].fixed_p
= 1;
2721 /* Insert any nops that might be needed between the .set noreorder
2722 block and the previous instructions. We will later remove any
2723 nops that turn out not to be needed. */
2724 nops
= nops_for_insn (history
, NULL
);
2727 if (mips_optimize
!= 0)
2729 /* Record the frag which holds the nop instructions, so
2730 that we can remove them if we don't need them. */
2731 frag_grow (mips_opts
.mips16
? nops
* 2 : nops
* 4);
2732 prev_nop_frag
= frag_now
;
2733 prev_nop_frag_holds
= nops
;
2734 prev_nop_frag_required
= 0;
2735 prev_nop_frag_since
= 0;
2738 for (; nops
> 0; --nops
)
2739 add_fixed_insn (NOP_INSN
);
2741 /* Move on to a new frag, so that it is safe to simply
2742 decrease the size of prev_nop_frag. */
2743 frag_wane (frag_now
);
2745 mips_move_labels ();
2747 mips16_mark_labels ();
2748 mips_clear_insn_labels ();
2750 mips_opts
.noreorder
++;
2751 mips_any_noreorder
= 1;
2754 /* End a nested noreorder block. */
2757 end_noreorder (void)
2759 mips_opts
.noreorder
--;
2760 if (mips_opts
.noreorder
== 0 && prev_nop_frag
!= NULL
)
2762 /* Commit to inserting prev_nop_frag_required nops and go back to
2763 handling nop insertion the .set reorder way. */
2764 prev_nop_frag
->fr_fix
-= ((prev_nop_frag_holds
- prev_nop_frag_required
)
2765 * (mips_opts
.mips16
? 2 : 4));
2766 insert_into_history (prev_nop_frag_since
,
2767 prev_nop_frag_required
, NOP_INSN
);
2768 prev_nop_frag
= NULL
;
2772 /* Set up global variables for the start of a new macro. */
2777 memset (&mips_macro_warning
.sizes
, 0, sizeof (mips_macro_warning
.sizes
));
2778 mips_macro_warning
.delay_slot_p
= (mips_opts
.noreorder
2779 && (history
[0].insn_mo
->pinfo
2780 & (INSN_UNCOND_BRANCH_DELAY
2781 | INSN_COND_BRANCH_DELAY
2782 | INSN_COND_BRANCH_LIKELY
)) != 0);
2785 /* Given that a macro is longer than 4 bytes, return the appropriate warning
2786 for it. Return null if no warning is needed. SUBTYPE is a bitmask of
2787 RELAX_DELAY_SLOT and RELAX_NOMACRO. */
2790 macro_warning (relax_substateT subtype
)
2792 if (subtype
& RELAX_DELAY_SLOT
)
2793 return _("Macro instruction expanded into multiple instructions"
2794 " in a branch delay slot");
2795 else if (subtype
& RELAX_NOMACRO
)
2796 return _("Macro instruction expanded into multiple instructions");
2801 /* Finish up a macro. Emit warnings as appropriate. */
2806 if (mips_macro_warning
.sizes
[0] > 4 || mips_macro_warning
.sizes
[1] > 4)
2808 relax_substateT subtype
;
2810 /* Set up the relaxation warning flags. */
2812 if (mips_macro_warning
.sizes
[1] > mips_macro_warning
.sizes
[0])
2813 subtype
|= RELAX_SECOND_LONGER
;
2814 if (mips_opts
.warn_about_macros
)
2815 subtype
|= RELAX_NOMACRO
;
2816 if (mips_macro_warning
.delay_slot_p
)
2817 subtype
|= RELAX_DELAY_SLOT
;
2819 if (mips_macro_warning
.sizes
[0] > 4 && mips_macro_warning
.sizes
[1] > 4)
2821 /* Either the macro has a single implementation or both
2822 implementations are longer than 4 bytes. Emit the
2824 const char *msg
= macro_warning (subtype
);
2830 /* One implementation might need a warning but the other
2831 definitely doesn't. */
2832 mips_macro_warning
.first_frag
->fr_subtype
|= subtype
;
2837 /* Read a macro's relocation codes from *ARGS and store them in *R.
2838 The first argument in *ARGS will be either the code for a single
2839 relocation or -1 followed by the three codes that make up a
2840 composite relocation. */
2843 macro_read_relocs (va_list *args
, bfd_reloc_code_real_type
*r
)
2847 next
= va_arg (*args
, int);
2849 r
[0] = (bfd_reloc_code_real_type
) next
;
2851 for (i
= 0; i
< 3; i
++)
2852 r
[i
] = (bfd_reloc_code_real_type
) va_arg (*args
, int);
2855 /* Build an instruction created by a macro expansion. This is passed
2856 a pointer to the count of instructions created so far, an
2857 expression, the name of the instruction to build, an operand format
2858 string, and corresponding arguments. */
2861 macro_build (expressionS
*ep
, const char *name
, const char *fmt
, ...)
2863 const struct mips_opcode
*mo
;
2864 struct mips_cl_insn insn
;
2865 bfd_reloc_code_real_type r
[3];
2868 va_start (args
, fmt
);
2870 if (mips_opts
.mips16
)
2872 mips16_macro_build (ep
, name
, fmt
, args
);
2877 r
[0] = BFD_RELOC_UNUSED
;
2878 r
[1] = BFD_RELOC_UNUSED
;
2879 r
[2] = BFD_RELOC_UNUSED
;
2880 mo
= (struct mips_opcode
*) hash_find (op_hash
, name
);
2882 assert (strcmp (name
, mo
->name
) == 0);
2884 /* Search until we get a match for NAME. It is assumed here that
2885 macros will never generate MDMX or MIPS-3D instructions. */
2886 while (strcmp (fmt
, mo
->args
) != 0
2887 || mo
->pinfo
== INSN_MACRO
2888 || !OPCODE_IS_MEMBER (mo
,
2890 | (file_ase_mips16
? INSN_MIPS16
: 0)),
2892 || (mips_opts
.arch
== CPU_R4650
&& (mo
->pinfo
& FP_D
) != 0))
2896 assert (strcmp (name
, mo
->name
) == 0);
2899 create_insn (&insn
, mo
);
2917 INSERT_OPERAND (SHAMT
, insn
, va_arg (args
, int));
2922 /* Note that in the macro case, these arguments are already
2923 in MSB form. (When handling the instruction in the
2924 non-macro case, these arguments are sizes from which
2925 MSB values must be calculated.) */
2926 INSERT_OPERAND (INSMSB
, insn
, va_arg (args
, int));
2932 /* Note that in the macro case, these arguments are already
2933 in MSBD form. (When handling the instruction in the
2934 non-macro case, these arguments are sizes from which
2935 MSBD values must be calculated.) */
2936 INSERT_OPERAND (EXTMSBD
, insn
, va_arg (args
, int));
2947 INSERT_OPERAND (RT
, insn
, va_arg (args
, int));
2951 INSERT_OPERAND (CODE
, insn
, va_arg (args
, int));
2956 INSERT_OPERAND (FT
, insn
, va_arg (args
, int));
2962 INSERT_OPERAND (RD
, insn
, va_arg (args
, int));
2967 int tmp
= va_arg (args
, int);
2969 INSERT_OPERAND (RT
, insn
, tmp
);
2970 INSERT_OPERAND (RD
, insn
, tmp
);
2976 INSERT_OPERAND (FS
, insn
, va_arg (args
, int));
2983 INSERT_OPERAND (SHAMT
, insn
, va_arg (args
, int));
2987 INSERT_OPERAND (FD
, insn
, va_arg (args
, int));
2991 INSERT_OPERAND (CODE20
, insn
, va_arg (args
, int));
2995 INSERT_OPERAND (CODE19
, insn
, va_arg (args
, int));
2999 INSERT_OPERAND (CODE2
, insn
, va_arg (args
, int));
3006 INSERT_OPERAND (RS
, insn
, va_arg (args
, int));
3012 macro_read_relocs (&args
, r
);
3013 assert (*r
== BFD_RELOC_GPREL16
3014 || *r
== BFD_RELOC_MIPS_LITERAL
3015 || *r
== BFD_RELOC_MIPS_HIGHER
3016 || *r
== BFD_RELOC_HI16_S
3017 || *r
== BFD_RELOC_LO16
3018 || *r
== BFD_RELOC_MIPS_GOT16
3019 || *r
== BFD_RELOC_MIPS_CALL16
3020 || *r
== BFD_RELOC_MIPS_GOT_DISP
3021 || *r
== BFD_RELOC_MIPS_GOT_PAGE
3022 || *r
== BFD_RELOC_MIPS_GOT_OFST
3023 || *r
== BFD_RELOC_MIPS_GOT_LO16
3024 || *r
== BFD_RELOC_MIPS_CALL_LO16
);
3028 macro_read_relocs (&args
, r
);
3030 && (ep
->X_op
== O_constant
3031 || (ep
->X_op
== O_symbol
3032 && (*r
== BFD_RELOC_MIPS_HIGHEST
3033 || *r
== BFD_RELOC_HI16_S
3034 || *r
== BFD_RELOC_HI16
3035 || *r
== BFD_RELOC_GPREL16
3036 || *r
== BFD_RELOC_MIPS_GOT_HI16
3037 || *r
== BFD_RELOC_MIPS_CALL_HI16
))));
3041 assert (ep
!= NULL
);
3043 * This allows macro() to pass an immediate expression for
3044 * creating short branches without creating a symbol.
3045 * Note that the expression still might come from the assembly
3046 * input, in which case the value is not checked for range nor
3047 * is a relocation entry generated (yuck).
3049 if (ep
->X_op
== O_constant
)
3051 insn
.insn_opcode
|= (ep
->X_add_number
>> 2) & 0xffff;
3055 *r
= BFD_RELOC_16_PCREL_S2
;
3059 assert (ep
!= NULL
);
3060 *r
= BFD_RELOC_MIPS_JMP
;
3064 insn
.insn_opcode
|= va_arg (args
, unsigned long);
3073 assert (*r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
3075 append_insn (&insn
, ep
, r
);
3079 mips16_macro_build (expressionS
*ep
, const char *name
, const char *fmt
,
3082 struct mips_opcode
*mo
;
3083 struct mips_cl_insn insn
;
3084 bfd_reloc_code_real_type r
[3]
3085 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
3087 mo
= (struct mips_opcode
*) hash_find (mips16_op_hash
, name
);
3089 assert (strcmp (name
, mo
->name
) == 0);
3091 while (strcmp (fmt
, mo
->args
) != 0 || mo
->pinfo
== INSN_MACRO
)
3095 assert (strcmp (name
, mo
->name
) == 0);
3098 create_insn (&insn
, mo
);
3116 MIPS16_INSERT_OPERAND (RY
, insn
, va_arg (args
, int));
3121 MIPS16_INSERT_OPERAND (RX
, insn
, va_arg (args
, int));
3125 MIPS16_INSERT_OPERAND (RZ
, insn
, va_arg (args
, int));
3129 MIPS16_INSERT_OPERAND (MOVE32Z
, insn
, va_arg (args
, int));
3139 MIPS16_INSERT_OPERAND (REGR32
, insn
, va_arg (args
, int));
3146 regno
= va_arg (args
, int);
3147 regno
= ((regno
& 7) << 2) | ((regno
& 0x18) >> 3);
3148 insn
.insn_opcode
|= regno
<< MIPS16OP_SH_REG32R
;
3169 assert (ep
!= NULL
);
3171 if (ep
->X_op
!= O_constant
)
3172 *r
= (int) BFD_RELOC_UNUSED
+ c
;
3175 mips16_immed (NULL
, 0, c
, ep
->X_add_number
, FALSE
, FALSE
,
3176 FALSE
, &insn
.insn_opcode
, &insn
.use_extend
,
3179 *r
= BFD_RELOC_UNUSED
;
3185 MIPS16_INSERT_OPERAND (IMM6
, insn
, va_arg (args
, int));
3192 assert (*r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
3194 append_insn (&insn
, ep
, r
);
3198 * Generate a "jalr" instruction with a relocation hint to the called
3199 * function. This occurs in NewABI PIC code.
3202 macro_build_jalr (expressionS
*ep
)
3211 macro_build (NULL
, "jalr", "d,s", RA
, PIC_CALL_REG
);
3213 fix_new_exp (frag_now
, f
- frag_now
->fr_literal
,
3214 4, ep
, FALSE
, BFD_RELOC_MIPS_JALR
);
3218 * Generate a "lui" instruction.
3221 macro_build_lui (expressionS
*ep
, int regnum
)
3223 expressionS high_expr
;
3224 const struct mips_opcode
*mo
;
3225 struct mips_cl_insn insn
;
3226 bfd_reloc_code_real_type r
[3]
3227 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
3228 const char *name
= "lui";
3229 const char *fmt
= "t,u";
3231 assert (! mips_opts
.mips16
);
3235 if (high_expr
.X_op
== O_constant
)
3237 /* we can compute the instruction now without a relocation entry */
3238 high_expr
.X_add_number
= ((high_expr
.X_add_number
+ 0x8000)
3240 *r
= BFD_RELOC_UNUSED
;
3244 assert (ep
->X_op
== O_symbol
);
3245 /* _gp_disp is a special case, used from s_cpload.
3246 __gnu_local_gp is used if mips_no_shared. */
3247 assert (mips_pic
== NO_PIC
3249 && strcmp (S_GET_NAME (ep
->X_add_symbol
), "_gp_disp") == 0)
3250 || (! mips_in_shared
3251 && strcmp (S_GET_NAME (ep
->X_add_symbol
),
3252 "__gnu_local_gp") == 0));
3253 *r
= BFD_RELOC_HI16_S
;
3256 mo
= hash_find (op_hash
, name
);
3257 assert (strcmp (name
, mo
->name
) == 0);
3258 assert (strcmp (fmt
, mo
->args
) == 0);
3259 create_insn (&insn
, mo
);
3261 insn
.insn_opcode
= insn
.insn_mo
->match
;
3262 INSERT_OPERAND (RT
, insn
, regnum
);
3263 if (*r
== BFD_RELOC_UNUSED
)
3265 insn
.insn_opcode
|= high_expr
.X_add_number
;
3266 append_insn (&insn
, NULL
, r
);
3269 append_insn (&insn
, &high_expr
, r
);
3272 /* Generate a sequence of instructions to do a load or store from a constant
3273 offset off of a base register (breg) into/from a target register (treg),
3274 using AT if necessary. */
3276 macro_build_ldst_constoffset (expressionS
*ep
, const char *op
,
3277 int treg
, int breg
, int dbl
)
3279 assert (ep
->X_op
== O_constant
);
3281 /* Sign-extending 32-bit constants makes their handling easier. */
3282 if (! dbl
&& ! ((ep
->X_add_number
& ~((bfd_vma
) 0x7fffffff))
3283 == ~((bfd_vma
) 0x7fffffff)))
3285 if (ep
->X_add_number
& ~((bfd_vma
) 0xffffffff))
3286 as_bad (_("constant too large"));
3288 ep
->X_add_number
= (((ep
->X_add_number
& 0xffffffff) ^ 0x80000000)
3292 /* Right now, this routine can only handle signed 32-bit constants. */
3293 if (! IS_SEXT_32BIT_NUM(ep
->X_add_number
+ 0x8000))
3294 as_warn (_("operand overflow"));
3296 if (IS_SEXT_16BIT_NUM(ep
->X_add_number
))
3298 /* Signed 16-bit offset will fit in the op. Easy! */
3299 macro_build (ep
, op
, "t,o(b)", treg
, BFD_RELOC_LO16
, breg
);
3303 /* 32-bit offset, need multiple instructions and AT, like:
3304 lui $tempreg,const_hi (BFD_RELOC_HI16_S)
3305 addu $tempreg,$tempreg,$breg
3306 <op> $treg,const_lo($tempreg) (BFD_RELOC_LO16)
3307 to handle the complete offset. */
3308 macro_build_lui (ep
, AT
);
3309 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, AT
, breg
);
3310 macro_build (ep
, op
, "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
3313 as_bad (_("Macro used $at after \".set noat\""));
3318 * Generates code to set the $at register to true (one)
3319 * if reg is less than the immediate expression.
3322 set_at (int reg
, int unsignedp
)
3324 if (imm_expr
.X_op
== O_constant
3325 && imm_expr
.X_add_number
>= -0x8000
3326 && imm_expr
.X_add_number
< 0x8000)
3327 macro_build (&imm_expr
, unsignedp
? "sltiu" : "slti", "t,r,j",
3328 AT
, reg
, BFD_RELOC_LO16
);
3331 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
3332 macro_build (NULL
, unsignedp
? "sltu" : "slt", "d,v,t", AT
, reg
, AT
);
3337 normalize_constant_expr (expressionS
*ex
)
3339 if (ex
->X_op
== O_constant
&& HAVE_32BIT_GPRS
)
3340 ex
->X_add_number
= (((ex
->X_add_number
& 0xffffffff) ^ 0x80000000)
3344 /* Warn if an expression is not a constant. */
3347 check_absolute_expr (struct mips_cl_insn
*ip
, expressionS
*ex
)
3349 if (ex
->X_op
== O_big
)
3350 as_bad (_("unsupported large constant"));
3351 else if (ex
->X_op
!= O_constant
)
3352 as_bad (_("Instruction %s requires absolute expression"), ip
->insn_mo
->name
);
3354 normalize_constant_expr (ex
);
3357 /* Count the leading zeroes by performing a binary chop. This is a
3358 bulky bit of source, but performance is a LOT better for the
3359 majority of values than a simple loop to count the bits:
3360 for (lcnt = 0; (lcnt < 32); lcnt++)
3361 if ((v) & (1 << (31 - lcnt)))
3363 However it is not code size friendly, and the gain will drop a bit
3364 on certain cached systems.
3366 #define COUNT_TOP_ZEROES(v) \
3367 (((v) & ~0xffff) == 0 \
3368 ? ((v) & ~0xff) == 0 \
3369 ? ((v) & ~0xf) == 0 \
3370 ? ((v) & ~0x3) == 0 \
3371 ? ((v) & ~0x1) == 0 \
3376 : ((v) & ~0x7) == 0 \
3379 : ((v) & ~0x3f) == 0 \
3380 ? ((v) & ~0x1f) == 0 \
3383 : ((v) & ~0x7f) == 0 \
3386 : ((v) & ~0xfff) == 0 \
3387 ? ((v) & ~0x3ff) == 0 \
3388 ? ((v) & ~0x1ff) == 0 \
3391 : ((v) & ~0x7ff) == 0 \
3394 : ((v) & ~0x3fff) == 0 \
3395 ? ((v) & ~0x1fff) == 0 \
3398 : ((v) & ~0x7fff) == 0 \
3401 : ((v) & ~0xffffff) == 0 \
3402 ? ((v) & ~0xfffff) == 0 \
3403 ? ((v) & ~0x3ffff) == 0 \
3404 ? ((v) & ~0x1ffff) == 0 \
3407 : ((v) & ~0x7ffff) == 0 \
3410 : ((v) & ~0x3fffff) == 0 \
3411 ? ((v) & ~0x1fffff) == 0 \
3414 : ((v) & ~0x7fffff) == 0 \
3417 : ((v) & ~0xfffffff) == 0 \
3418 ? ((v) & ~0x3ffffff) == 0 \
3419 ? ((v) & ~0x1ffffff) == 0 \
3422 : ((v) & ~0x7ffffff) == 0 \
3425 : ((v) & ~0x3fffffff) == 0 \
3426 ? ((v) & ~0x1fffffff) == 0 \
3429 : ((v) & ~0x7fffffff) == 0 \
3434 * This routine generates the least number of instructions necessary to load
3435 * an absolute expression value into a register.
3438 load_register (int reg
, expressionS
*ep
, int dbl
)
3441 expressionS hi32
, lo32
;
3443 if (ep
->X_op
!= O_big
)
3445 assert (ep
->X_op
== O_constant
);
3447 /* Sign-extending 32-bit constants makes their handling easier. */
3448 if (! dbl
&& ! ((ep
->X_add_number
& ~((bfd_vma
) 0x7fffffff))
3449 == ~((bfd_vma
) 0x7fffffff)))
3451 if (ep
->X_add_number
& ~((bfd_vma
) 0xffffffff))
3452 as_bad (_("constant too large"));
3454 ep
->X_add_number
= (((ep
->X_add_number
& 0xffffffff) ^ 0x80000000)
3458 if (IS_SEXT_16BIT_NUM (ep
->X_add_number
))
3460 /* We can handle 16 bit signed values with an addiu to
3461 $zero. No need to ever use daddiu here, since $zero and
3462 the result are always correct in 32 bit mode. */
3463 macro_build (ep
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
3466 else if (ep
->X_add_number
>= 0 && ep
->X_add_number
< 0x10000)
3468 /* We can handle 16 bit unsigned values with an ori to
3470 macro_build (ep
, "ori", "t,r,i", reg
, 0, BFD_RELOC_LO16
);
3473 else if ((IS_SEXT_32BIT_NUM (ep
->X_add_number
)))
3475 /* 32 bit values require an lui. */
3476 macro_build (ep
, "lui", "t,u", reg
, BFD_RELOC_HI16
);
3477 if ((ep
->X_add_number
& 0xffff) != 0)
3478 macro_build (ep
, "ori", "t,r,i", reg
, reg
, BFD_RELOC_LO16
);
3483 /* The value is larger than 32 bits. */
3485 if (HAVE_32BIT_GPRS
)
3487 as_bad (_("Number (0x%lx) larger than 32 bits"),
3488 (unsigned long) ep
->X_add_number
);
3489 macro_build (ep
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
3493 if (ep
->X_op
!= O_big
)
3496 hi32
.X_add_number
= (valueT
) hi32
.X_add_number
>> 16;
3497 hi32
.X_add_number
= (valueT
) hi32
.X_add_number
>> 16;
3498 hi32
.X_add_number
&= 0xffffffff;
3500 lo32
.X_add_number
&= 0xffffffff;
3504 assert (ep
->X_add_number
> 2);
3505 if (ep
->X_add_number
== 3)
3506 generic_bignum
[3] = 0;
3507 else if (ep
->X_add_number
> 4)
3508 as_bad (_("Number larger than 64 bits"));
3509 lo32
.X_op
= O_constant
;
3510 lo32
.X_add_number
= generic_bignum
[0] + (generic_bignum
[1] << 16);
3511 hi32
.X_op
= O_constant
;
3512 hi32
.X_add_number
= generic_bignum
[2] + (generic_bignum
[3] << 16);
3515 if (hi32
.X_add_number
== 0)
3520 unsigned long hi
, lo
;
3522 if (hi32
.X_add_number
== (offsetT
) 0xffffffff)
3524 if ((lo32
.X_add_number
& 0xffff8000) == 0xffff8000)
3526 macro_build (&lo32
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
3529 if (lo32
.X_add_number
& 0x80000000)
3531 macro_build (&lo32
, "lui", "t,u", reg
, BFD_RELOC_HI16
);
3532 if (lo32
.X_add_number
& 0xffff)
3533 macro_build (&lo32
, "ori", "t,r,i", reg
, reg
, BFD_RELOC_LO16
);
3538 /* Check for 16bit shifted constant. We know that hi32 is
3539 non-zero, so start the mask on the first bit of the hi32
3544 unsigned long himask
, lomask
;
3548 himask
= 0xffff >> (32 - shift
);
3549 lomask
= (0xffff << shift
) & 0xffffffff;
3553 himask
= 0xffff << (shift
- 32);
3556 if ((hi32
.X_add_number
& ~(offsetT
) himask
) == 0
3557 && (lo32
.X_add_number
& ~(offsetT
) lomask
) == 0)
3561 tmp
.X_op
= O_constant
;
3563 tmp
.X_add_number
= ((hi32
.X_add_number
<< (32 - shift
))
3564 | (lo32
.X_add_number
>> shift
));
3566 tmp
.X_add_number
= hi32
.X_add_number
>> (shift
- 32);
3567 macro_build (&tmp
, "ori", "t,r,i", reg
, 0, BFD_RELOC_LO16
);
3568 macro_build (NULL
, (shift
>= 32) ? "dsll32" : "dsll", "d,w,<",
3569 reg
, reg
, (shift
>= 32) ? shift
- 32 : shift
);
3574 while (shift
<= (64 - 16));
3576 /* Find the bit number of the lowest one bit, and store the
3577 shifted value in hi/lo. */
3578 hi
= (unsigned long) (hi32
.X_add_number
& 0xffffffff);
3579 lo
= (unsigned long) (lo32
.X_add_number
& 0xffffffff);
3583 while ((lo
& 1) == 0)
3588 lo
|= (hi
& (((unsigned long) 1 << bit
) - 1)) << (32 - bit
);
3594 while ((hi
& 1) == 0)
3603 /* Optimize if the shifted value is a (power of 2) - 1. */
3604 if ((hi
== 0 && ((lo
+ 1) & lo
) == 0)
3605 || (lo
== 0xffffffff && ((hi
+ 1) & hi
) == 0))
3607 shift
= COUNT_TOP_ZEROES ((unsigned int) hi32
.X_add_number
);
3612 /* This instruction will set the register to be all
3614 tmp
.X_op
= O_constant
;
3615 tmp
.X_add_number
= (offsetT
) -1;
3616 macro_build (&tmp
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
3620 macro_build (NULL
, (bit
>= 32) ? "dsll32" : "dsll", "d,w,<",
3621 reg
, reg
, (bit
>= 32) ? bit
- 32 : bit
);
3623 macro_build (NULL
, (shift
>= 32) ? "dsrl32" : "dsrl", "d,w,<",
3624 reg
, reg
, (shift
>= 32) ? shift
- 32 : shift
);
3629 /* Sign extend hi32 before calling load_register, because we can
3630 generally get better code when we load a sign extended value. */
3631 if ((hi32
.X_add_number
& 0x80000000) != 0)
3632 hi32
.X_add_number
|= ~(offsetT
) 0xffffffff;
3633 load_register (reg
, &hi32
, 0);
3636 if ((lo32
.X_add_number
& 0xffff0000) == 0)
3640 macro_build (NULL
, "dsll32", "d,w,<", reg
, freg
, 0);
3648 if ((freg
== 0) && (lo32
.X_add_number
== (offsetT
) 0xffffffff))
3650 macro_build (&lo32
, "lui", "t,u", reg
, BFD_RELOC_HI16
);
3651 macro_build (NULL
, "dsrl32", "d,w,<", reg
, reg
, 0);
3657 macro_build (NULL
, "dsll", "d,w,<", reg
, freg
, 16);
3661 mid16
.X_add_number
>>= 16;
3662 macro_build (&mid16
, "ori", "t,r,i", reg
, freg
, BFD_RELOC_LO16
);
3663 macro_build (NULL
, "dsll", "d,w,<", reg
, reg
, 16);
3666 if ((lo32
.X_add_number
& 0xffff) != 0)
3667 macro_build (&lo32
, "ori", "t,r,i", reg
, freg
, BFD_RELOC_LO16
);
3671 load_delay_nop (void)
3673 if (!gpr_interlocks
)
3674 macro_build (NULL
, "nop", "");
3677 /* Load an address into a register. */
3680 load_address (int reg
, expressionS
*ep
, int *used_at
)
3682 if (ep
->X_op
!= O_constant
3683 && ep
->X_op
!= O_symbol
)
3685 as_bad (_("expression too complex"));
3686 ep
->X_op
= O_constant
;
3689 if (ep
->X_op
== O_constant
)
3691 load_register (reg
, ep
, HAVE_64BIT_ADDRESSES
);
3695 if (mips_pic
== NO_PIC
)
3697 /* If this is a reference to a GP relative symbol, we want
3698 addiu $reg,$gp,<sym> (BFD_RELOC_GPREL16)
3700 lui $reg,<sym> (BFD_RELOC_HI16_S)
3701 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
3702 If we have an addend, we always use the latter form.
3704 With 64bit address space and a usable $at we want
3705 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
3706 lui $at,<sym> (BFD_RELOC_HI16_S)
3707 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
3708 daddiu $at,<sym> (BFD_RELOC_LO16)
3712 If $at is already in use, we use a path which is suboptimal
3713 on superscalar processors.
3714 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
3715 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
3717 daddiu $reg,<sym> (BFD_RELOC_HI16_S)
3719 daddiu $reg,<sym> (BFD_RELOC_LO16)
3721 For GP relative symbols in 64bit address space we can use
3722 the same sequence as in 32bit address space. */
3723 if (HAVE_64BIT_SYMBOLS
)
3725 if ((valueT
) ep
->X_add_number
<= MAX_GPREL_OFFSET
3726 && !nopic_need_relax (ep
->X_add_symbol
, 1))
3728 relax_start (ep
->X_add_symbol
);
3729 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
,
3730 mips_gp_register
, BFD_RELOC_GPREL16
);
3734 if (*used_at
== 0 && !mips_opts
.noat
)
3736 macro_build (ep
, "lui", "t,u", reg
, BFD_RELOC_MIPS_HIGHEST
);
3737 macro_build (ep
, "lui", "t,u", AT
, BFD_RELOC_HI16_S
);
3738 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
,
3739 BFD_RELOC_MIPS_HIGHER
);
3740 macro_build (ep
, "daddiu", "t,r,j", AT
, AT
, BFD_RELOC_LO16
);
3741 macro_build (NULL
, "dsll32", "d,w,<", reg
, reg
, 0);
3742 macro_build (NULL
, "daddu", "d,v,t", reg
, reg
, AT
);
3747 macro_build (ep
, "lui", "t,u", reg
, BFD_RELOC_MIPS_HIGHEST
);
3748 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
,
3749 BFD_RELOC_MIPS_HIGHER
);
3750 macro_build (NULL
, "dsll", "d,w,<", reg
, reg
, 16);
3751 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
, BFD_RELOC_HI16_S
);
3752 macro_build (NULL
, "dsll", "d,w,<", reg
, reg
, 16);
3753 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
, BFD_RELOC_LO16
);
3756 if (mips_relax
.sequence
)
3761 if ((valueT
) ep
->X_add_number
<= MAX_GPREL_OFFSET
3762 && !nopic_need_relax (ep
->X_add_symbol
, 1))
3764 relax_start (ep
->X_add_symbol
);
3765 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
,
3766 mips_gp_register
, BFD_RELOC_GPREL16
);
3769 macro_build_lui (ep
, reg
);
3770 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j",
3771 reg
, reg
, BFD_RELOC_LO16
);
3772 if (mips_relax
.sequence
)
3776 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
3780 /* If this is a reference to an external symbol, we want
3781 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3783 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3785 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
3786 If there is a constant, it must be added in after.
3788 If we have NewABI, we want
3789 lw $reg,<sym+cst>($gp) (BFD_RELOC_MIPS_GOT_DISP)
3790 unless we're referencing a global symbol with a non-zero
3791 offset, in which case cst must be added separately. */
3794 if (ep
->X_add_number
)
3796 ex
.X_add_number
= ep
->X_add_number
;
3797 ep
->X_add_number
= 0;
3798 relax_start (ep
->X_add_symbol
);
3799 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
3800 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
3801 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
3802 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
3803 ex
.X_op
= O_constant
;
3804 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j",
3805 reg
, reg
, BFD_RELOC_LO16
);
3806 ep
->X_add_number
= ex
.X_add_number
;
3809 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
3810 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
3811 if (mips_relax
.sequence
)
3816 ex
.X_add_number
= ep
->X_add_number
;
3817 ep
->X_add_number
= 0;
3818 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
3819 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
3821 relax_start (ep
->X_add_symbol
);
3823 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
3827 if (ex
.X_add_number
!= 0)
3829 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
3830 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
3831 ex
.X_op
= O_constant
;
3832 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j",
3833 reg
, reg
, BFD_RELOC_LO16
);
3837 else if (mips_pic
== SVR4_PIC
)
3841 /* This is the large GOT case. If this is a reference to an
3842 external symbol, we want
3843 lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
3845 lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16)
3847 Otherwise, for a reference to a local symbol in old ABI, we want
3848 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3850 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
3851 If there is a constant, it must be added in after.
3853 In the NewABI, for local symbols, with or without offsets, we want:
3854 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
3855 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
3859 ex
.X_add_number
= ep
->X_add_number
;
3860 ep
->X_add_number
= 0;
3861 relax_start (ep
->X_add_symbol
);
3862 macro_build (ep
, "lui", "t,u", reg
, BFD_RELOC_MIPS_GOT_HI16
);
3863 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
3864 reg
, reg
, mips_gp_register
);
3865 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)",
3866 reg
, BFD_RELOC_MIPS_GOT_LO16
, reg
);
3867 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
3868 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
3869 else if (ex
.X_add_number
)
3871 ex
.X_op
= O_constant
;
3872 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
3876 ep
->X_add_number
= ex
.X_add_number
;
3878 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
3879 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
3880 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
3881 BFD_RELOC_MIPS_GOT_OFST
);
3886 ex
.X_add_number
= ep
->X_add_number
;
3887 ep
->X_add_number
= 0;
3888 relax_start (ep
->X_add_symbol
);
3889 macro_build (ep
, "lui", "t,u", reg
, BFD_RELOC_MIPS_GOT_HI16
);
3890 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
3891 reg
, reg
, mips_gp_register
);
3892 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)",
3893 reg
, BFD_RELOC_MIPS_GOT_LO16
, reg
);
3895 if (reg_needs_delay (mips_gp_register
))
3897 /* We need a nop before loading from $gp. This special
3898 check is required because the lui which starts the main
3899 instruction stream does not refer to $gp, and so will not
3900 insert the nop which may be required. */
3901 macro_build (NULL
, "nop", "");
3903 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
3904 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
3906 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
3910 if (ex
.X_add_number
!= 0)
3912 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
3913 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
3914 ex
.X_op
= O_constant
;
3915 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
3923 if (mips_opts
.noat
&& *used_at
== 1)
3924 as_bad (_("Macro used $at after \".set noat\""));
3927 /* Move the contents of register SOURCE into register DEST. */
3930 move_register (int dest
, int source
)
3932 macro_build (NULL
, HAVE_32BIT_GPRS
? "addu" : "daddu", "d,v,t",
3936 /* Emit an SVR4 PIC sequence to load address LOCAL into DEST, where
3937 LOCAL is the sum of a symbol and a 16-bit or 32-bit displacement.
3938 The two alternatives are:
3940 Global symbol Local sybmol
3941 ------------- ------------
3942 lw DEST,%got(SYMBOL) lw DEST,%got(SYMBOL + OFFSET)
3944 addiu DEST,DEST,OFFSET addiu DEST,DEST,%lo(SYMBOL + OFFSET)
3946 load_got_offset emits the first instruction and add_got_offset
3947 emits the second for a 16-bit offset or add_got_offset_hilo emits
3948 a sequence to add a 32-bit offset using a scratch register. */
3951 load_got_offset (int dest
, expressionS
*local
)
3956 global
.X_add_number
= 0;
3958 relax_start (local
->X_add_symbol
);
3959 macro_build (&global
, ADDRESS_LOAD_INSN
, "t,o(b)", dest
,
3960 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
3962 macro_build (local
, ADDRESS_LOAD_INSN
, "t,o(b)", dest
,
3963 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
3968 add_got_offset (int dest
, expressionS
*local
)
3972 global
.X_op
= O_constant
;
3973 global
.X_op_symbol
= NULL
;
3974 global
.X_add_symbol
= NULL
;
3975 global
.X_add_number
= local
->X_add_number
;
3977 relax_start (local
->X_add_symbol
);
3978 macro_build (&global
, ADDRESS_ADDI_INSN
, "t,r,j",
3979 dest
, dest
, BFD_RELOC_LO16
);
3981 macro_build (local
, ADDRESS_ADDI_INSN
, "t,r,j", dest
, dest
, BFD_RELOC_LO16
);
3986 add_got_offset_hilo (int dest
, expressionS
*local
, int tmp
)
3989 int hold_mips_optimize
;
3991 global
.X_op
= O_constant
;
3992 global
.X_op_symbol
= NULL
;
3993 global
.X_add_symbol
= NULL
;
3994 global
.X_add_number
= local
->X_add_number
;
3996 relax_start (local
->X_add_symbol
);
3997 load_register (tmp
, &global
, HAVE_64BIT_ADDRESSES
);
3999 /* Set mips_optimize around the lui instruction to avoid
4000 inserting an unnecessary nop after the lw. */
4001 hold_mips_optimize
= mips_optimize
;
4003 macro_build_lui (&global
, tmp
);
4004 mips_optimize
= hold_mips_optimize
;
4005 macro_build (local
, ADDRESS_ADDI_INSN
, "t,r,j", tmp
, tmp
, BFD_RELOC_LO16
);
4008 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", dest
, dest
, tmp
);
4013 * This routine implements the seemingly endless macro or synthesized
4014 * instructions and addressing modes in the mips assembly language. Many
4015 * of these macros are simple and are similar to each other. These could
4016 * probably be handled by some kind of table or grammar approach instead of
4017 * this verbose method. Others are not simple macros but are more like
4018 * optimizing code generation.
4019 * One interesting optimization is when several store macros appear
4020 * consecutively that would load AT with the upper half of the same address.
4021 * The ensuing load upper instructions are ommited. This implies some kind
4022 * of global optimization. We currently only optimize within a single macro.
4023 * For many of the load and store macros if the address is specified as a
4024 * constant expression in the first 64k of memory (ie ld $2,0x4000c) we
4025 * first load register 'at' with zero and use it as the base register. The
4026 * mips assembler simply uses register $zero. Just one tiny optimization
4030 macro (struct mips_cl_insn
*ip
)
4032 register int treg
, sreg
, dreg
, breg
;
4048 bfd_reloc_code_real_type r
;
4049 int hold_mips_optimize
;
4051 assert (! mips_opts
.mips16
);
4053 treg
= (ip
->insn_opcode
>> 16) & 0x1f;
4054 dreg
= (ip
->insn_opcode
>> 11) & 0x1f;
4055 sreg
= breg
= (ip
->insn_opcode
>> 21) & 0x1f;
4056 mask
= ip
->insn_mo
->mask
;
4058 expr1
.X_op
= O_constant
;
4059 expr1
.X_op_symbol
= NULL
;
4060 expr1
.X_add_symbol
= NULL
;
4061 expr1
.X_add_number
= 1;
4075 expr1
.X_add_number
= 8;
4076 macro_build (&expr1
, "bgez", "s,p", sreg
);
4078 macro_build (NULL
, "nop", "", 0);
4080 move_register (dreg
, sreg
);
4081 macro_build (NULL
, dbl
? "dsub" : "sub", "d,v,t", dreg
, 0, sreg
);
4104 if (imm_expr
.X_op
== O_constant
4105 && imm_expr
.X_add_number
>= -0x8000
4106 && imm_expr
.X_add_number
< 0x8000)
4108 macro_build (&imm_expr
, s
, "t,r,j", treg
, sreg
, BFD_RELOC_LO16
);
4112 load_register (AT
, &imm_expr
, dbl
);
4113 macro_build (NULL
, s2
, "d,v,t", treg
, sreg
, AT
);
4132 if (imm_expr
.X_op
== O_constant
4133 && imm_expr
.X_add_number
>= 0
4134 && imm_expr
.X_add_number
< 0x10000)
4136 if (mask
!= M_NOR_I
)
4137 macro_build (&imm_expr
, s
, "t,r,i", treg
, sreg
, BFD_RELOC_LO16
);
4140 macro_build (&imm_expr
, "ori", "t,r,i",
4141 treg
, sreg
, BFD_RELOC_LO16
);
4142 macro_build (NULL
, "nor", "d,v,t", treg
, treg
, 0);
4148 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
4149 macro_build (NULL
, s2
, "d,v,t", treg
, sreg
, AT
);
4166 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
4168 macro_build (&offset_expr
, s
, "s,t,p", sreg
, 0);
4172 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
4173 macro_build (&offset_expr
, s
, "s,t,p", sreg
, AT
);
4181 macro_build (&offset_expr
, likely
? "bgezl" : "bgez", "s,p", sreg
);
4186 macro_build (&offset_expr
, likely
? "blezl" : "blez", "s,p", treg
);
4190 macro_build (NULL
, "slt", "d,v,t", AT
, sreg
, treg
);
4191 macro_build (&offset_expr
, likely
? "beql" : "beq", "s,t,p", AT
, 0);
4197 /* check for > max integer */
4198 maxnum
= 0x7fffffff;
4199 if (HAVE_64BIT_GPRS
&& sizeof (maxnum
) > 4)
4206 if (imm_expr
.X_op
== O_constant
4207 && imm_expr
.X_add_number
>= maxnum
4208 && (HAVE_32BIT_GPRS
|| sizeof (maxnum
) > 4))
4211 /* result is always false */
4213 macro_build (NULL
, "nop", "", 0);
4215 macro_build (&offset_expr
, "bnel", "s,t,p", 0, 0);
4218 if (imm_expr
.X_op
!= O_constant
)
4219 as_bad (_("Unsupported large constant"));
4220 ++imm_expr
.X_add_number
;
4224 if (mask
== M_BGEL_I
)
4226 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
4228 macro_build (&offset_expr
, likely
? "bgezl" : "bgez", "s,p", sreg
);
4231 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
4233 macro_build (&offset_expr
, likely
? "bgtzl" : "bgtz", "s,p", sreg
);
4236 maxnum
= 0x7fffffff;
4237 if (HAVE_64BIT_GPRS
&& sizeof (maxnum
) > 4)
4244 maxnum
= - maxnum
- 1;
4245 if (imm_expr
.X_op
== O_constant
4246 && imm_expr
.X_add_number
<= maxnum
4247 && (HAVE_32BIT_GPRS
|| sizeof (maxnum
) > 4))
4250 /* result is always true */
4251 as_warn (_("Branch %s is always true"), ip
->insn_mo
->name
);
4252 macro_build (&offset_expr
, "b", "p");
4257 macro_build (&offset_expr
, likely
? "beql" : "beq", "s,t,p", AT
, 0);
4267 macro_build (&offset_expr
, likely
? "beql" : "beq",
4272 macro_build (NULL
, "sltu", "d,v,t", AT
, sreg
, treg
);
4273 macro_build (&offset_expr
, likely
? "beql" : "beq", "s,t,p", AT
, 0);
4281 && imm_expr
.X_op
== O_constant
4282 && imm_expr
.X_add_number
== (offsetT
) 0xffffffff))
4284 if (imm_expr
.X_op
!= O_constant
)
4285 as_bad (_("Unsupported large constant"));
4286 ++imm_expr
.X_add_number
;
4290 if (mask
== M_BGEUL_I
)
4292 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
4294 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
4296 macro_build (&offset_expr
, likely
? "bnel" : "bne",
4302 macro_build (&offset_expr
, likely
? "beql" : "beq", "s,t,p", AT
, 0);
4310 macro_build (&offset_expr
, likely
? "bgtzl" : "bgtz", "s,p", sreg
);
4315 macro_build (&offset_expr
, likely
? "bltzl" : "bltz", "s,p", treg
);
4319 macro_build (NULL
, "slt", "d,v,t", AT
, treg
, sreg
);
4320 macro_build (&offset_expr
, likely
? "bnel" : "bne", "s,t,p", AT
, 0);
4328 macro_build (&offset_expr
, likely
? "bnel" : "bne",
4335 macro_build (NULL
, "sltu", "d,v,t", AT
, treg
, sreg
);
4336 macro_build (&offset_expr
, likely
? "bnel" : "bne", "s,t,p", AT
, 0);
4344 macro_build (&offset_expr
, likely
? "blezl" : "blez", "s,p", sreg
);
4349 macro_build (&offset_expr
, likely
? "bgezl" : "bgez", "s,p", treg
);
4353 macro_build (NULL
, "slt", "d,v,t", AT
, treg
, sreg
);
4354 macro_build (&offset_expr
, likely
? "beql" : "beq", "s,t,p", AT
, 0);
4360 maxnum
= 0x7fffffff;
4361 if (HAVE_64BIT_GPRS
&& sizeof (maxnum
) > 4)
4368 if (imm_expr
.X_op
== O_constant
4369 && imm_expr
.X_add_number
>= maxnum
4370 && (HAVE_32BIT_GPRS
|| sizeof (maxnum
) > 4))
4372 if (imm_expr
.X_op
!= O_constant
)
4373 as_bad (_("Unsupported large constant"));
4374 ++imm_expr
.X_add_number
;
4378 if (mask
== M_BLTL_I
)
4380 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
4382 macro_build (&offset_expr
, likely
? "bltzl" : "bltz", "s,p", sreg
);
4385 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
4387 macro_build (&offset_expr
, likely
? "blezl" : "blez", "s,p", sreg
);
4392 macro_build (&offset_expr
, likely
? "bnel" : "bne", "s,t,p", AT
, 0);
4400 macro_build (&offset_expr
, likely
? "beql" : "beq",
4407 macro_build (NULL
, "sltu", "d,v,t", AT
, treg
, sreg
);
4408 macro_build (&offset_expr
, likely
? "beql" : "beq", "s,t,p", AT
, 0);
4416 && imm_expr
.X_op
== O_constant
4417 && imm_expr
.X_add_number
== (offsetT
) 0xffffffff))
4419 if (imm_expr
.X_op
!= O_constant
)
4420 as_bad (_("Unsupported large constant"));
4421 ++imm_expr
.X_add_number
;
4425 if (mask
== M_BLTUL_I
)
4427 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
4429 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
4431 macro_build (&offset_expr
, likely
? "beql" : "beq",
4437 macro_build (&offset_expr
, likely
? "bnel" : "bne", "s,t,p", AT
, 0);
4445 macro_build (&offset_expr
, likely
? "bltzl" : "bltz", "s,p", sreg
);
4450 macro_build (&offset_expr
, likely
? "bgtzl" : "bgtz", "s,p", treg
);
4454 macro_build (NULL
, "slt", "d,v,t", AT
, sreg
, treg
);
4455 macro_build (&offset_expr
, likely
? "bnel" : "bne", "s,t,p", AT
, 0);
4465 macro_build (&offset_expr
, likely
? "bnel" : "bne",
4470 macro_build (NULL
, "sltu", "d,v,t", AT
, sreg
, treg
);
4471 macro_build (&offset_expr
, likely
? "bnel" : "bne", "s,t,p", AT
, 0);
4479 if (imm_expr
.X_op
!= O_constant
|| imm2_expr
.X_op
!= O_constant
)
4481 as_bad (_("Unsupported large constant"));
4486 pos
= (unsigned long) imm_expr
.X_add_number
;
4487 size
= (unsigned long) imm2_expr
.X_add_number
;
4492 as_bad (_("Improper position (%lu)"), pos
);
4495 if (size
== 0 || size
> 64
4496 || (pos
+ size
- 1) > 63)
4498 as_bad (_("Improper extract size (%lu, position %lu)"),
4503 if (size
<= 32 && pos
< 32)
4508 else if (size
<= 32)
4518 macro_build ((expressionS
*) NULL
, s
, fmt
, treg
, sreg
, pos
, size
- 1);
4527 if (imm_expr
.X_op
!= O_constant
|| imm2_expr
.X_op
!= O_constant
)
4529 as_bad (_("Unsupported large constant"));
4534 pos
= (unsigned long) imm_expr
.X_add_number
;
4535 size
= (unsigned long) imm2_expr
.X_add_number
;
4540 as_bad (_("Improper position (%lu)"), pos
);
4543 if (size
== 0 || size
> 64
4544 || (pos
+ size
- 1) > 63)
4546 as_bad (_("Improper insert size (%lu, position %lu)"),
4551 if (pos
< 32 && (pos
+ size
- 1) < 32)
4566 macro_build ((expressionS
*) NULL
, s
, fmt
, treg
, sreg
, pos
,
4583 as_warn (_("Divide by zero."));
4585 macro_build (NULL
, "teq", "s,t,q", 0, 0, 7);
4587 macro_build (NULL
, "break", "c", 7);
4594 macro_build (NULL
, "teq", "s,t,q", treg
, 0, 7);
4595 macro_build (NULL
, dbl
? "ddiv" : "div", "z,s,t", sreg
, treg
);
4599 expr1
.X_add_number
= 8;
4600 macro_build (&expr1
, "bne", "s,t,p", treg
, 0);
4601 macro_build (NULL
, dbl
? "ddiv" : "div", "z,s,t", sreg
, treg
);
4602 macro_build (NULL
, "break", "c", 7);
4604 expr1
.X_add_number
= -1;
4606 load_register (AT
, &expr1
, dbl
);
4607 expr1
.X_add_number
= mips_trap
? (dbl
? 12 : 8) : (dbl
? 20 : 16);
4608 macro_build (&expr1
, "bne", "s,t,p", treg
, AT
);
4611 expr1
.X_add_number
= 1;
4612 load_register (AT
, &expr1
, dbl
);
4613 macro_build (NULL
, "dsll32", "d,w,<", AT
, AT
, 31);
4617 expr1
.X_add_number
= 0x80000000;
4618 macro_build (&expr1
, "lui", "t,u", AT
, BFD_RELOC_HI16
);
4622 macro_build (NULL
, "teq", "s,t,q", sreg
, AT
, 6);
4623 /* We want to close the noreorder block as soon as possible, so
4624 that later insns are available for delay slot filling. */
4629 expr1
.X_add_number
= 8;
4630 macro_build (&expr1
, "bne", "s,t,p", sreg
, AT
);
4631 macro_build (NULL
, "nop", "", 0);
4633 /* We want to close the noreorder block as soon as possible, so
4634 that later insns are available for delay slot filling. */
4637 macro_build (NULL
, "break", "c", 6);
4639 macro_build (NULL
, s
, "d", dreg
);
4678 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
4680 as_warn (_("Divide by zero."));
4682 macro_build (NULL
, "teq", "s,t,q", 0, 0, 7);
4684 macro_build (NULL
, "break", "c", 7);
4687 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
4689 if (strcmp (s2
, "mflo") == 0)
4690 move_register (dreg
, sreg
);
4692 move_register (dreg
, 0);
4695 if (imm_expr
.X_op
== O_constant
4696 && imm_expr
.X_add_number
== -1
4697 && s
[strlen (s
) - 1] != 'u')
4699 if (strcmp (s2
, "mflo") == 0)
4701 macro_build (NULL
, dbl
? "dneg" : "neg", "d,w", dreg
, sreg
);
4704 move_register (dreg
, 0);
4709 load_register (AT
, &imm_expr
, dbl
);
4710 macro_build (NULL
, s
, "z,s,t", sreg
, AT
);
4711 macro_build (NULL
, s2
, "d", dreg
);
4733 macro_build (NULL
, "teq", "s,t,q", treg
, 0, 7);
4734 macro_build (NULL
, s
, "z,s,t", sreg
, treg
);
4735 /* We want to close the noreorder block as soon as possible, so
4736 that later insns are available for delay slot filling. */
4741 expr1
.X_add_number
= 8;
4742 macro_build (&expr1
, "bne", "s,t,p", treg
, 0);
4743 macro_build (NULL
, s
, "z,s,t", sreg
, treg
);
4745 /* We want to close the noreorder block as soon as possible, so
4746 that later insns are available for delay slot filling. */
4748 macro_build (NULL
, "break", "c", 7);
4750 macro_build (NULL
, s2
, "d", dreg
);
4762 /* Load the address of a symbol into a register. If breg is not
4763 zero, we then add a base register to it. */
4765 if (dbl
&& HAVE_32BIT_GPRS
)
4766 as_warn (_("dla used to load 32-bit register"));
4768 if (! dbl
&& HAVE_64BIT_OBJECTS
)
4769 as_warn (_("la used to load 64-bit address"));
4771 if (offset_expr
.X_op
== O_constant
4772 && offset_expr
.X_add_number
>= -0x8000
4773 && offset_expr
.X_add_number
< 0x8000)
4775 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
,
4776 "t,r,j", treg
, sreg
, BFD_RELOC_LO16
);
4780 if (!mips_opts
.noat
&& (treg
== breg
))
4790 if (offset_expr
.X_op
!= O_symbol
4791 && offset_expr
.X_op
!= O_constant
)
4793 as_bad (_("expression too complex"));
4794 offset_expr
.X_op
= O_constant
;
4797 if (offset_expr
.X_op
== O_constant
)
4798 load_register (tempreg
, &offset_expr
, HAVE_64BIT_ADDRESSES
);
4799 else if (mips_pic
== NO_PIC
)
4801 /* If this is a reference to a GP relative symbol, we want
4802 addiu $tempreg,$gp,<sym> (BFD_RELOC_GPREL16)
4804 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
4805 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
4806 If we have a constant, we need two instructions anyhow,
4807 so we may as well always use the latter form.
4809 With 64bit address space and a usable $at we want
4810 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
4811 lui $at,<sym> (BFD_RELOC_HI16_S)
4812 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
4813 daddiu $at,<sym> (BFD_RELOC_LO16)
4815 daddu $tempreg,$tempreg,$at
4817 If $at is already in use, we use a path which is suboptimal
4818 on superscalar processors.
4819 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
4820 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
4822 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
4824 daddiu $tempreg,<sym> (BFD_RELOC_LO16)
4826 For GP relative symbols in 64bit address space we can use
4827 the same sequence as in 32bit address space. */
4828 if (HAVE_64BIT_SYMBOLS
)
4830 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
4831 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
4833 relax_start (offset_expr
.X_add_symbol
);
4834 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
4835 tempreg
, mips_gp_register
, BFD_RELOC_GPREL16
);
4839 if (used_at
== 0 && !mips_opts
.noat
)
4841 macro_build (&offset_expr
, "lui", "t,u",
4842 tempreg
, BFD_RELOC_MIPS_HIGHEST
);
4843 macro_build (&offset_expr
, "lui", "t,u",
4844 AT
, BFD_RELOC_HI16_S
);
4845 macro_build (&offset_expr
, "daddiu", "t,r,j",
4846 tempreg
, tempreg
, BFD_RELOC_MIPS_HIGHER
);
4847 macro_build (&offset_expr
, "daddiu", "t,r,j",
4848 AT
, AT
, BFD_RELOC_LO16
);
4849 macro_build (NULL
, "dsll32", "d,w,<", tempreg
, tempreg
, 0);
4850 macro_build (NULL
, "daddu", "d,v,t", tempreg
, tempreg
, AT
);
4855 macro_build (&offset_expr
, "lui", "t,u",
4856 tempreg
, BFD_RELOC_MIPS_HIGHEST
);
4857 macro_build (&offset_expr
, "daddiu", "t,r,j",
4858 tempreg
, tempreg
, BFD_RELOC_MIPS_HIGHER
);
4859 macro_build (NULL
, "dsll", "d,w,<", tempreg
, tempreg
, 16);
4860 macro_build (&offset_expr
, "daddiu", "t,r,j",
4861 tempreg
, tempreg
, BFD_RELOC_HI16_S
);
4862 macro_build (NULL
, "dsll", "d,w,<", tempreg
, tempreg
, 16);
4863 macro_build (&offset_expr
, "daddiu", "t,r,j",
4864 tempreg
, tempreg
, BFD_RELOC_LO16
);
4867 if (mips_relax
.sequence
)
4872 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
4873 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
4875 relax_start (offset_expr
.X_add_symbol
);
4876 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
4877 tempreg
, mips_gp_register
, BFD_RELOC_GPREL16
);
4880 if (!IS_SEXT_32BIT_NUM (offset_expr
.X_add_number
))
4881 as_bad (_("offset too large"));
4882 macro_build_lui (&offset_expr
, tempreg
);
4883 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
4884 tempreg
, tempreg
, BFD_RELOC_LO16
);
4885 if (mips_relax
.sequence
)
4889 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
&& ! HAVE_NEWABI
)
4891 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT16
;
4893 /* If this is a reference to an external symbol, and there
4894 is no constant, we want
4895 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4896 or for lca or if tempreg is PIC_CALL_REG
4897 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
4898 For a local symbol, we want
4899 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4901 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
4903 If we have a small constant, and this is a reference to
4904 an external symbol, we want
4905 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4907 addiu $tempreg,$tempreg,<constant>
4908 For a local symbol, we want the same instruction
4909 sequence, but we output a BFD_RELOC_LO16 reloc on the
4912 If we have a large constant, and this is a reference to
4913 an external symbol, we want
4914 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4915 lui $at,<hiconstant>
4916 addiu $at,$at,<loconstant>
4917 addu $tempreg,$tempreg,$at
4918 For a local symbol, we want the same instruction
4919 sequence, but we output a BFD_RELOC_LO16 reloc on the
4923 if (offset_expr
.X_add_number
== 0)
4925 if (breg
== 0 && (call
|| tempreg
== PIC_CALL_REG
))
4926 lw_reloc_type
= (int) BFD_RELOC_MIPS_CALL16
;
4928 relax_start (offset_expr
.X_add_symbol
);
4929 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
4930 lw_reloc_type
, mips_gp_register
);
4933 /* We're going to put in an addu instruction using
4934 tempreg, so we may as well insert the nop right
4939 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
4940 tempreg
, BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
4942 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
4943 tempreg
, tempreg
, BFD_RELOC_LO16
);
4945 /* FIXME: If breg == 0, and the next instruction uses
4946 $tempreg, then if this variant case is used an extra
4947 nop will be generated. */
4949 else if (offset_expr
.X_add_number
>= -0x8000
4950 && offset_expr
.X_add_number
< 0x8000)
4952 load_got_offset (tempreg
, &offset_expr
);
4954 add_got_offset (tempreg
, &offset_expr
);
4958 expr1
.X_add_number
= offset_expr
.X_add_number
;
4959 offset_expr
.X_add_number
=
4960 ((offset_expr
.X_add_number
+ 0x8000) & 0xffff) - 0x8000;
4961 load_got_offset (tempreg
, &offset_expr
);
4962 offset_expr
.X_add_number
= expr1
.X_add_number
;
4963 /* If we are going to add in a base register, and the
4964 target register and the base register are the same,
4965 then we are using AT as a temporary register. Since
4966 we want to load the constant into AT, we add our
4967 current AT (from the global offset table) and the
4968 register into the register now, and pretend we were
4969 not using a base register. */
4973 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
4978 add_got_offset_hilo (tempreg
, &offset_expr
, AT
);
4982 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
&& HAVE_NEWABI
)
4984 int add_breg_early
= 0;
4986 /* If this is a reference to an external, and there is no
4987 constant, or local symbol (*), with or without a
4989 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
4990 or for lca or if tempreg is PIC_CALL_REG
4991 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
4993 If we have a small constant, and this is a reference to
4994 an external symbol, we want
4995 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
4996 addiu $tempreg,$tempreg,<constant>
4998 If we have a large constant, and this is a reference to
4999 an external symbol, we want
5000 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
5001 lui $at,<hiconstant>
5002 addiu $at,$at,<loconstant>
5003 addu $tempreg,$tempreg,$at
5005 (*) Other assemblers seem to prefer GOT_PAGE/GOT_OFST for
5006 local symbols, even though it introduces an additional
5009 if (offset_expr
.X_add_number
)
5011 expr1
.X_add_number
= offset_expr
.X_add_number
;
5012 offset_expr
.X_add_number
= 0;
5014 relax_start (offset_expr
.X_add_symbol
);
5015 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
5016 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
5018 if (expr1
.X_add_number
>= -0x8000
5019 && expr1
.X_add_number
< 0x8000)
5021 macro_build (&expr1
, ADDRESS_ADDI_INSN
, "t,r,j",
5022 tempreg
, tempreg
, BFD_RELOC_LO16
);
5024 else if (IS_SEXT_32BIT_NUM (expr1
.X_add_number
+ 0x8000))
5028 /* If we are going to add in a base register, and the
5029 target register and the base register are the same,
5030 then we are using AT as a temporary register. Since
5031 we want to load the constant into AT, we add our
5032 current AT (from the global offset table) and the
5033 register into the register now, and pretend we were
5034 not using a base register. */
5039 assert (tempreg
== AT
);
5040 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5046 load_register (AT
, &expr1
, HAVE_64BIT_ADDRESSES
);
5047 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5053 as_bad (_("PIC code offset overflow (max 32 signed bits)"));
5056 offset_expr
.X_add_number
= expr1
.X_add_number
;
5058 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
5059 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
5062 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5063 treg
, tempreg
, breg
);
5069 else if (breg
== 0 && (call
|| tempreg
== PIC_CALL_REG
))
5071 relax_start (offset_expr
.X_add_symbol
);
5072 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
5073 BFD_RELOC_MIPS_CALL16
, mips_gp_register
);
5075 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
5076 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
5081 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
5082 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
5085 else if (mips_pic
== SVR4_PIC
&& ! HAVE_NEWABI
)
5088 int lui_reloc_type
= (int) BFD_RELOC_MIPS_GOT_HI16
;
5089 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT_LO16
;
5090 int local_reloc_type
= (int) BFD_RELOC_MIPS_GOT16
;
5092 /* This is the large GOT case. If this is a reference to an
5093 external symbol, and there is no constant, we want
5094 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5095 addu $tempreg,$tempreg,$gp
5096 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5097 or for lca or if tempreg is PIC_CALL_REG
5098 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
5099 addu $tempreg,$tempreg,$gp
5100 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
5101 For a local symbol, we want
5102 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5104 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
5106 If we have a small constant, and this is a reference to
5107 an external symbol, we want
5108 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5109 addu $tempreg,$tempreg,$gp
5110 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5112 addiu $tempreg,$tempreg,<constant>
5113 For a local symbol, we want
5114 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5116 addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16)
5118 If we have a large constant, and this is a reference to
5119 an external symbol, we want
5120 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5121 addu $tempreg,$tempreg,$gp
5122 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5123 lui $at,<hiconstant>
5124 addiu $at,$at,<loconstant>
5125 addu $tempreg,$tempreg,$at
5126 For a local symbol, we want
5127 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5128 lui $at,<hiconstant>
5129 addiu $at,$at,<loconstant> (BFD_RELOC_LO16)
5130 addu $tempreg,$tempreg,$at
5133 expr1
.X_add_number
= offset_expr
.X_add_number
;
5134 offset_expr
.X_add_number
= 0;
5135 relax_start (offset_expr
.X_add_symbol
);
5136 gpdelay
= reg_needs_delay (mips_gp_register
);
5137 if (expr1
.X_add_number
== 0 && breg
== 0
5138 && (call
|| tempreg
== PIC_CALL_REG
))
5140 lui_reloc_type
= (int) BFD_RELOC_MIPS_CALL_HI16
;
5141 lw_reloc_type
= (int) BFD_RELOC_MIPS_CALL_LO16
;
5143 macro_build (&offset_expr
, "lui", "t,u", tempreg
, lui_reloc_type
);
5144 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5145 tempreg
, tempreg
, mips_gp_register
);
5146 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
5147 tempreg
, lw_reloc_type
, tempreg
);
5148 if (expr1
.X_add_number
== 0)
5152 /* We're going to put in an addu instruction using
5153 tempreg, so we may as well insert the nop right
5158 else if (expr1
.X_add_number
>= -0x8000
5159 && expr1
.X_add_number
< 0x8000)
5162 macro_build (&expr1
, ADDRESS_ADDI_INSN
, "t,r,j",
5163 tempreg
, tempreg
, BFD_RELOC_LO16
);
5169 /* If we are going to add in a base register, and the
5170 target register and the base register are the same,
5171 then we are using AT as a temporary register. Since
5172 we want to load the constant into AT, we add our
5173 current AT (from the global offset table) and the
5174 register into the register now, and pretend we were
5175 not using a base register. */
5180 assert (tempreg
== AT
);
5182 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5187 load_register (AT
, &expr1
, HAVE_64BIT_ADDRESSES
);
5188 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", dreg
, dreg
, AT
);
5192 offset_expr
.X_add_number
=
5193 ((expr1
.X_add_number
+ 0x8000) & 0xffff) - 0x8000;
5198 /* This is needed because this instruction uses $gp, but
5199 the first instruction on the main stream does not. */
5200 macro_build (NULL
, "nop", "");
5203 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
5204 local_reloc_type
, mips_gp_register
);
5205 if (expr1
.X_add_number
>= -0x8000
5206 && expr1
.X_add_number
< 0x8000)
5209 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
5210 tempreg
, tempreg
, BFD_RELOC_LO16
);
5211 /* FIXME: If add_number is 0, and there was no base
5212 register, the external symbol case ended with a load,
5213 so if the symbol turns out to not be external, and
5214 the next instruction uses tempreg, an unnecessary nop
5215 will be inserted. */
5221 /* We must add in the base register now, as in the
5222 external symbol case. */
5223 assert (tempreg
== AT
);
5225 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5228 /* We set breg to 0 because we have arranged to add
5229 it in in both cases. */
5233 macro_build_lui (&expr1
, AT
);
5234 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
5235 AT
, AT
, BFD_RELOC_LO16
);
5236 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5237 tempreg
, tempreg
, AT
);
5242 else if (mips_pic
== SVR4_PIC
&& HAVE_NEWABI
)
5244 int lui_reloc_type
= (int) BFD_RELOC_MIPS_GOT_HI16
;
5245 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT_LO16
;
5246 int add_breg_early
= 0;
5248 /* This is the large GOT case. If this is a reference to an
5249 external symbol, and there is no constant, we want
5250 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5251 add $tempreg,$tempreg,$gp
5252 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5253 or for lca or if tempreg is PIC_CALL_REG
5254 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
5255 add $tempreg,$tempreg,$gp
5256 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
5258 If we have a small constant, and this is a reference to
5259 an external symbol, we want
5260 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5261 add $tempreg,$tempreg,$gp
5262 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5263 addi $tempreg,$tempreg,<constant>
5265 If we have a large constant, and this is a reference to
5266 an external symbol, we want
5267 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5268 addu $tempreg,$tempreg,$gp
5269 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5270 lui $at,<hiconstant>
5271 addi $at,$at,<loconstant>
5272 add $tempreg,$tempreg,$at
5274 If we have NewABI, and we know it's a local symbol, we want
5275 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
5276 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
5277 otherwise we have to resort to GOT_HI16/GOT_LO16. */
5279 relax_start (offset_expr
.X_add_symbol
);
5281 expr1
.X_add_number
= offset_expr
.X_add_number
;
5282 offset_expr
.X_add_number
= 0;
5284 if (expr1
.X_add_number
== 0 && breg
== 0
5285 && (call
|| tempreg
== PIC_CALL_REG
))
5287 lui_reloc_type
= (int) BFD_RELOC_MIPS_CALL_HI16
;
5288 lw_reloc_type
= (int) BFD_RELOC_MIPS_CALL_LO16
;
5290 macro_build (&offset_expr
, "lui", "t,u", tempreg
, lui_reloc_type
);
5291 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5292 tempreg
, tempreg
, mips_gp_register
);
5293 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
5294 tempreg
, lw_reloc_type
, tempreg
);
5296 if (expr1
.X_add_number
== 0)
5298 else if (expr1
.X_add_number
>= -0x8000
5299 && expr1
.X_add_number
< 0x8000)
5301 macro_build (&expr1
, ADDRESS_ADDI_INSN
, "t,r,j",
5302 tempreg
, tempreg
, BFD_RELOC_LO16
);
5304 else if (IS_SEXT_32BIT_NUM (expr1
.X_add_number
+ 0x8000))
5308 /* If we are going to add in a base register, and the
5309 target register and the base register are the same,
5310 then we are using AT as a temporary register. Since
5311 we want to load the constant into AT, we add our
5312 current AT (from the global offset table) and the
5313 register into the register now, and pretend we were
5314 not using a base register. */
5319 assert (tempreg
== AT
);
5320 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5326 load_register (AT
, &expr1
, HAVE_64BIT_ADDRESSES
);
5327 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", dreg
, dreg
, AT
);
5332 as_bad (_("PIC code offset overflow (max 32 signed bits)"));
5335 offset_expr
.X_add_number
= expr1
.X_add_number
;
5336 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
5337 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
5338 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j", tempreg
,
5339 tempreg
, BFD_RELOC_MIPS_GOT_OFST
);
5342 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5343 treg
, tempreg
, breg
);
5353 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", treg
, tempreg
, breg
);
5357 /* The j instruction may not be used in PIC code, since it
5358 requires an absolute address. We convert it to a b
5360 if (mips_pic
== NO_PIC
)
5361 macro_build (&offset_expr
, "j", "a");
5363 macro_build (&offset_expr
, "b", "p");
5366 /* The jal instructions must be handled as macros because when
5367 generating PIC code they expand to multi-instruction
5368 sequences. Normally they are simple instructions. */
5373 if (mips_pic
== NO_PIC
)
5374 macro_build (NULL
, "jalr", "d,s", dreg
, sreg
);
5375 else if (mips_pic
== SVR4_PIC
)
5377 if (sreg
!= PIC_CALL_REG
)
5378 as_warn (_("MIPS PIC call to register other than $25"));
5380 macro_build (NULL
, "jalr", "d,s", dreg
, sreg
);
5383 if (mips_cprestore_offset
< 0)
5384 as_warn (_("No .cprestore pseudo-op used in PIC code"));
5387 if (! mips_frame_reg_valid
)
5389 as_warn (_("No .frame pseudo-op used in PIC code"));
5390 /* Quiet this warning. */
5391 mips_frame_reg_valid
= 1;
5393 if (! mips_cprestore_valid
)
5395 as_warn (_("No .cprestore pseudo-op used in PIC code"));
5396 /* Quiet this warning. */
5397 mips_cprestore_valid
= 1;
5399 expr1
.X_add_number
= mips_cprestore_offset
;
5400 macro_build_ldst_constoffset (&expr1
, ADDRESS_LOAD_INSN
,
5403 HAVE_64BIT_ADDRESSES
);
5413 if (mips_pic
== NO_PIC
)
5414 macro_build (&offset_expr
, "jal", "a");
5415 else if (mips_pic
== SVR4_PIC
)
5417 /* If this is a reference to an external symbol, and we are
5418 using a small GOT, we want
5419 lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
5423 lw $gp,cprestore($sp)
5424 The cprestore value is set using the .cprestore
5425 pseudo-op. If we are using a big GOT, we want
5426 lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16)
5428 lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16)
5432 lw $gp,cprestore($sp)
5433 If the symbol is not external, we want
5434 lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5436 addiu $25,$25,<sym> (BFD_RELOC_LO16)
5439 lw $gp,cprestore($sp)
5441 For NewABI, we use the same CALL16 or CALL_HI16/CALL_LO16
5442 sequences above, minus nops, unless the symbol is local,
5443 which enables us to use GOT_PAGE/GOT_OFST (big got) or
5449 relax_start (offset_expr
.X_add_symbol
);
5450 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
5451 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL16
,
5454 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
5455 PIC_CALL_REG
, BFD_RELOC_MIPS_GOT_DISP
,
5461 relax_start (offset_expr
.X_add_symbol
);
5462 macro_build (&offset_expr
, "lui", "t,u", PIC_CALL_REG
,
5463 BFD_RELOC_MIPS_CALL_HI16
);
5464 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", PIC_CALL_REG
,
5465 PIC_CALL_REG
, mips_gp_register
);
5466 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
5467 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL_LO16
,
5470 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
5471 PIC_CALL_REG
, BFD_RELOC_MIPS_GOT_PAGE
,
5473 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
5474 PIC_CALL_REG
, PIC_CALL_REG
,
5475 BFD_RELOC_MIPS_GOT_OFST
);
5479 macro_build_jalr (&offset_expr
);
5483 relax_start (offset_expr
.X_add_symbol
);
5486 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
5487 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL16
,
5496 gpdelay
= reg_needs_delay (mips_gp_register
);
5497 macro_build (&offset_expr
, "lui", "t,u", PIC_CALL_REG
,
5498 BFD_RELOC_MIPS_CALL_HI16
);
5499 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", PIC_CALL_REG
,
5500 PIC_CALL_REG
, mips_gp_register
);
5501 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
5502 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL_LO16
,
5507 macro_build (NULL
, "nop", "");
5509 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
5510 PIC_CALL_REG
, BFD_RELOC_MIPS_GOT16
,
5513 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
5514 PIC_CALL_REG
, PIC_CALL_REG
, BFD_RELOC_LO16
);
5516 macro_build_jalr (&offset_expr
);
5518 if (mips_cprestore_offset
< 0)
5519 as_warn (_("No .cprestore pseudo-op used in PIC code"));
5522 if (! mips_frame_reg_valid
)
5524 as_warn (_("No .frame pseudo-op used in PIC code"));
5525 /* Quiet this warning. */
5526 mips_frame_reg_valid
= 1;
5528 if (! mips_cprestore_valid
)
5530 as_warn (_("No .cprestore pseudo-op used in PIC code"));
5531 /* Quiet this warning. */
5532 mips_cprestore_valid
= 1;
5534 if (mips_opts
.noreorder
)
5535 macro_build (NULL
, "nop", "");
5536 expr1
.X_add_number
= mips_cprestore_offset
;
5537 macro_build_ldst_constoffset (&expr1
, ADDRESS_LOAD_INSN
,
5540 HAVE_64BIT_ADDRESSES
);
5566 /* Itbl support may require additional care here. */
5571 /* Itbl support may require additional care here. */
5576 /* Itbl support may require additional care here. */
5581 /* Itbl support may require additional care here. */
5593 if (mips_opts
.arch
== CPU_R4650
)
5595 as_bad (_("opcode not supported on this processor"));
5599 /* Itbl support may require additional care here. */
5604 /* Itbl support may require additional care here. */
5609 /* Itbl support may require additional care here. */
5629 if (breg
== treg
|| coproc
|| lr
)
5650 /* Itbl support may require additional care here. */
5655 /* Itbl support may require additional care here. */
5660 /* Itbl support may require additional care here. */
5665 /* Itbl support may require additional care here. */
5681 if (mips_opts
.arch
== CPU_R4650
)
5683 as_bad (_("opcode not supported on this processor"));
5688 /* Itbl support may require additional care here. */
5692 /* Itbl support may require additional care here. */
5697 /* Itbl support may require additional care here. */
5709 /* Itbl support may require additional care here. */
5710 if (mask
== M_LWC1_AB
5711 || mask
== M_SWC1_AB
5712 || mask
== M_LDC1_AB
5713 || mask
== M_SDC1_AB
5722 if (offset_expr
.X_op
!= O_constant
5723 && offset_expr
.X_op
!= O_symbol
)
5725 as_bad (_("expression too complex"));
5726 offset_expr
.X_op
= O_constant
;
5729 /* A constant expression in PIC code can be handled just as it
5730 is in non PIC code. */
5731 if (offset_expr
.X_op
== O_constant
)
5733 if (HAVE_32BIT_ADDRESSES
5734 && !IS_SEXT_32BIT_NUM (offset_expr
.X_add_number
))
5735 as_bad (_("constant too large"));
5737 expr1
.X_add_number
= ((offset_expr
.X_add_number
+ 0x8000)
5738 & ~(bfd_vma
) 0xffff);
5739 load_register (tempreg
, &expr1
, HAVE_64BIT_ADDRESSES
);
5741 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5742 tempreg
, tempreg
, breg
);
5743 macro_build (&offset_expr
, s
, fmt
, treg
, BFD_RELOC_LO16
, tempreg
);
5745 else if (mips_pic
== NO_PIC
)
5747 /* If this is a reference to a GP relative symbol, and there
5748 is no base register, we want
5749 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
5750 Otherwise, if there is no base register, we want
5751 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
5752 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5753 If we have a constant, we need two instructions anyhow,
5754 so we always use the latter form.
5756 If we have a base register, and this is a reference to a
5757 GP relative symbol, we want
5758 addu $tempreg,$breg,$gp
5759 <op> $treg,<sym>($tempreg) (BFD_RELOC_GPREL16)
5761 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
5762 addu $tempreg,$tempreg,$breg
5763 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5764 With a constant we always use the latter case.
5766 With 64bit address space and no base register and $at usable,
5768 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5769 lui $at,<sym> (BFD_RELOC_HI16_S)
5770 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
5773 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5774 If we have a base register, we want
5775 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5776 lui $at,<sym> (BFD_RELOC_HI16_S)
5777 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
5781 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5783 Without $at we can't generate the optimal path for superscalar
5784 processors here since this would require two temporary registers.
5785 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5786 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
5788 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
5790 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5791 If we have a base register, we want
5792 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5793 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
5795 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
5797 daddu $tempreg,$tempreg,$breg
5798 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5800 For GP relative symbols in 64bit address space we can use
5801 the same sequence as in 32bit address space. */
5802 if (HAVE_64BIT_SYMBOLS
)
5804 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
5805 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
5807 relax_start (offset_expr
.X_add_symbol
);
5810 macro_build (&offset_expr
, s
, fmt
, treg
,
5811 BFD_RELOC_GPREL16
, mips_gp_register
);
5815 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5816 tempreg
, breg
, mips_gp_register
);
5817 macro_build (&offset_expr
, s
, fmt
, treg
,
5818 BFD_RELOC_GPREL16
, tempreg
);
5823 if (used_at
== 0 && !mips_opts
.noat
)
5825 macro_build (&offset_expr
, "lui", "t,u", tempreg
,
5826 BFD_RELOC_MIPS_HIGHEST
);
5827 macro_build (&offset_expr
, "lui", "t,u", AT
,
5829 macro_build (&offset_expr
, "daddiu", "t,r,j", tempreg
,
5830 tempreg
, BFD_RELOC_MIPS_HIGHER
);
5832 macro_build (NULL
, "daddu", "d,v,t", AT
, AT
, breg
);
5833 macro_build (NULL
, "dsll32", "d,w,<", tempreg
, tempreg
, 0);
5834 macro_build (NULL
, "daddu", "d,v,t", tempreg
, tempreg
, AT
);
5835 macro_build (&offset_expr
, s
, fmt
, treg
, BFD_RELOC_LO16
,
5841 macro_build (&offset_expr
, "lui", "t,u", tempreg
,
5842 BFD_RELOC_MIPS_HIGHEST
);
5843 macro_build (&offset_expr
, "daddiu", "t,r,j", tempreg
,
5844 tempreg
, BFD_RELOC_MIPS_HIGHER
);
5845 macro_build (NULL
, "dsll", "d,w,<", tempreg
, tempreg
, 16);
5846 macro_build (&offset_expr
, "daddiu", "t,r,j", tempreg
,
5847 tempreg
, BFD_RELOC_HI16_S
);
5848 macro_build (NULL
, "dsll", "d,w,<", tempreg
, tempreg
, 16);
5850 macro_build (NULL
, "daddu", "d,v,t",
5851 tempreg
, tempreg
, breg
);
5852 macro_build (&offset_expr
, s
, fmt
, treg
,
5853 BFD_RELOC_LO16
, tempreg
);
5856 if (mips_relax
.sequence
)
5863 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
5864 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
5866 relax_start (offset_expr
.X_add_symbol
);
5867 macro_build (&offset_expr
, s
, fmt
, treg
, BFD_RELOC_GPREL16
,
5871 macro_build_lui (&offset_expr
, tempreg
);
5872 macro_build (&offset_expr
, s
, fmt
, treg
,
5873 BFD_RELOC_LO16
, tempreg
);
5874 if (mips_relax
.sequence
)
5879 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
5880 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
5882 relax_start (offset_expr
.X_add_symbol
);
5883 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5884 tempreg
, breg
, mips_gp_register
);
5885 macro_build (&offset_expr
, s
, fmt
, treg
,
5886 BFD_RELOC_GPREL16
, tempreg
);
5889 macro_build_lui (&offset_expr
, tempreg
);
5890 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5891 tempreg
, tempreg
, breg
);
5892 macro_build (&offset_expr
, s
, fmt
, treg
,
5893 BFD_RELOC_LO16
, tempreg
);
5894 if (mips_relax
.sequence
)
5898 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
5900 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT16
;
5902 /* If this is a reference to an external symbol, we want
5903 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5905 <op> $treg,0($tempreg)
5907 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5909 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
5910 <op> $treg,0($tempreg)
5913 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
5914 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST)
5916 If there is a base register, we add it to $tempreg before
5917 the <op>. If there is a constant, we stick it in the
5918 <op> instruction. We don't handle constants larger than
5919 16 bits, because we have no way to load the upper 16 bits
5920 (actually, we could handle them for the subset of cases
5921 in which we are not using $at). */
5922 assert (offset_expr
.X_op
== O_symbol
);
5925 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
5926 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
5928 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5929 tempreg
, tempreg
, breg
);
5930 macro_build (&offset_expr
, s
, fmt
, treg
,
5931 BFD_RELOC_MIPS_GOT_OFST
, tempreg
);
5934 expr1
.X_add_number
= offset_expr
.X_add_number
;
5935 offset_expr
.X_add_number
= 0;
5936 if (expr1
.X_add_number
< -0x8000
5937 || expr1
.X_add_number
>= 0x8000)
5938 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
5939 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
5940 lw_reloc_type
, mips_gp_register
);
5942 relax_start (offset_expr
.X_add_symbol
);
5944 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j", tempreg
,
5945 tempreg
, BFD_RELOC_LO16
);
5948 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5949 tempreg
, tempreg
, breg
);
5950 macro_build (&expr1
, s
, fmt
, treg
, BFD_RELOC_LO16
, tempreg
);
5952 else if (mips_pic
== SVR4_PIC
&& ! HAVE_NEWABI
)
5956 /* If this is a reference to an external symbol, we want
5957 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5958 addu $tempreg,$tempreg,$gp
5959 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5960 <op> $treg,0($tempreg)
5962 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5964 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
5965 <op> $treg,0($tempreg)
5966 If there is a base register, we add it to $tempreg before
5967 the <op>. If there is a constant, we stick it in the
5968 <op> instruction. We don't handle constants larger than
5969 16 bits, because we have no way to load the upper 16 bits
5970 (actually, we could handle them for the subset of cases
5971 in which we are not using $at). */
5972 assert (offset_expr
.X_op
== O_symbol
);
5973 expr1
.X_add_number
= offset_expr
.X_add_number
;
5974 offset_expr
.X_add_number
= 0;
5975 if (expr1
.X_add_number
< -0x8000
5976 || expr1
.X_add_number
>= 0x8000)
5977 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
5978 gpdelay
= reg_needs_delay (mips_gp_register
);
5979 relax_start (offset_expr
.X_add_symbol
);
5980 macro_build (&offset_expr
, "lui", "t,u", tempreg
,
5981 BFD_RELOC_MIPS_GOT_HI16
);
5982 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", tempreg
, tempreg
,
5984 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
5985 BFD_RELOC_MIPS_GOT_LO16
, tempreg
);
5988 macro_build (NULL
, "nop", "");
5989 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
5990 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
5992 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j", tempreg
,
5993 tempreg
, BFD_RELOC_LO16
);
5997 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5998 tempreg
, tempreg
, breg
);
5999 macro_build (&expr1
, s
, fmt
, treg
, BFD_RELOC_LO16
, tempreg
);
6001 else if (mips_pic
== SVR4_PIC
&& HAVE_NEWABI
)
6003 /* If this is a reference to an external symbol, we want
6004 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
6005 add $tempreg,$tempreg,$gp
6006 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
6007 <op> $treg,<ofst>($tempreg)
6008 Otherwise, for local symbols, we want:
6009 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
6010 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST) */
6011 assert (offset_expr
.X_op
== O_symbol
);
6012 expr1
.X_add_number
= offset_expr
.X_add_number
;
6013 offset_expr
.X_add_number
= 0;
6014 if (expr1
.X_add_number
< -0x8000
6015 || expr1
.X_add_number
>= 0x8000)
6016 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6017 relax_start (offset_expr
.X_add_symbol
);
6018 macro_build (&offset_expr
, "lui", "t,u", tempreg
,
6019 BFD_RELOC_MIPS_GOT_HI16
);
6020 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", tempreg
, tempreg
,
6022 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
6023 BFD_RELOC_MIPS_GOT_LO16
, tempreg
);
6025 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6026 tempreg
, tempreg
, breg
);
6027 macro_build (&expr1
, s
, fmt
, treg
, BFD_RELOC_LO16
, tempreg
);
6030 offset_expr
.X_add_number
= expr1
.X_add_number
;
6031 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
6032 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
6034 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6035 tempreg
, tempreg
, breg
);
6036 macro_build (&offset_expr
, s
, fmt
, treg
,
6037 BFD_RELOC_MIPS_GOT_OFST
, tempreg
);
6047 load_register (treg
, &imm_expr
, 0);
6051 load_register (treg
, &imm_expr
, 1);
6055 if (imm_expr
.X_op
== O_constant
)
6058 load_register (AT
, &imm_expr
, 0);
6059 macro_build (NULL
, "mtc1", "t,G", AT
, treg
);
6064 assert (offset_expr
.X_op
== O_symbol
6065 && strcmp (segment_name (S_GET_SEGMENT
6066 (offset_expr
.X_add_symbol
)),
6068 && offset_expr
.X_add_number
== 0);
6069 macro_build (&offset_expr
, "lwc1", "T,o(b)", treg
,
6070 BFD_RELOC_MIPS_LITERAL
, mips_gp_register
);
6075 /* Check if we have a constant in IMM_EXPR. If the GPRs are 64 bits
6076 wide, IMM_EXPR is the entire value. Otherwise IMM_EXPR is the high
6077 order 32 bits of the value and the low order 32 bits are either
6078 zero or in OFFSET_EXPR. */
6079 if (imm_expr
.X_op
== O_constant
|| imm_expr
.X_op
== O_big
)
6081 if (HAVE_64BIT_GPRS
)
6082 load_register (treg
, &imm_expr
, 1);
6087 if (target_big_endian
)
6099 load_register (hreg
, &imm_expr
, 0);
6102 if (offset_expr
.X_op
== O_absent
)
6103 move_register (lreg
, 0);
6106 assert (offset_expr
.X_op
== O_constant
);
6107 load_register (lreg
, &offset_expr
, 0);
6114 /* We know that sym is in the .rdata section. First we get the
6115 upper 16 bits of the address. */
6116 if (mips_pic
== NO_PIC
)
6118 macro_build_lui (&offset_expr
, AT
);
6121 else if (mips_pic
== SVR4_PIC
)
6123 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", AT
,
6124 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
6130 /* Now we load the register(s). */
6131 if (HAVE_64BIT_GPRS
)
6134 macro_build (&offset_expr
, "ld", "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
6139 macro_build (&offset_expr
, "lw", "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
6142 /* FIXME: How in the world do we deal with the possible
6144 offset_expr
.X_add_number
+= 4;
6145 macro_build (&offset_expr
, "lw", "t,o(b)",
6146 treg
+ 1, BFD_RELOC_LO16
, AT
);
6152 /* Check if we have a constant in IMM_EXPR. If the FPRs are 64 bits
6153 wide, IMM_EXPR is the entire value and the GPRs are known to be 64
6154 bits wide as well. Otherwise IMM_EXPR is the high order 32 bits of
6155 the value and the low order 32 bits are either zero or in
6157 if (imm_expr
.X_op
== O_constant
|| imm_expr
.X_op
== O_big
)
6160 load_register (AT
, &imm_expr
, HAVE_64BIT_FPRS
);
6161 if (HAVE_64BIT_FPRS
)
6163 assert (HAVE_64BIT_GPRS
);
6164 macro_build (NULL
, "dmtc1", "t,S", AT
, treg
);
6168 macro_build (NULL
, "mtc1", "t,G", AT
, treg
+ 1);
6169 if (offset_expr
.X_op
== O_absent
)
6170 macro_build (NULL
, "mtc1", "t,G", 0, treg
);
6173 assert (offset_expr
.X_op
== O_constant
);
6174 load_register (AT
, &offset_expr
, 0);
6175 macro_build (NULL
, "mtc1", "t,G", AT
, treg
);
6181 assert (offset_expr
.X_op
== O_symbol
6182 && offset_expr
.X_add_number
== 0);
6183 s
= segment_name (S_GET_SEGMENT (offset_expr
.X_add_symbol
));
6184 if (strcmp (s
, ".lit8") == 0)
6186 if (mips_opts
.isa
!= ISA_MIPS1
)
6188 macro_build (&offset_expr
, "ldc1", "T,o(b)", treg
,
6189 BFD_RELOC_MIPS_LITERAL
, mips_gp_register
);
6192 breg
= mips_gp_register
;
6193 r
= BFD_RELOC_MIPS_LITERAL
;
6198 assert (strcmp (s
, RDATA_SECTION_NAME
) == 0);
6200 if (mips_pic
== SVR4_PIC
)
6201 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", AT
,
6202 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
6205 /* FIXME: This won't work for a 64 bit address. */
6206 macro_build_lui (&offset_expr
, AT
);
6209 if (mips_opts
.isa
!= ISA_MIPS1
)
6211 macro_build (&offset_expr
, "ldc1", "T,o(b)",
6212 treg
, BFD_RELOC_LO16
, AT
);
6221 if (mips_opts
.arch
== CPU_R4650
)
6223 as_bad (_("opcode not supported on this processor"));
6226 /* Even on a big endian machine $fn comes before $fn+1. We have
6227 to adjust when loading from memory. */
6230 assert (mips_opts
.isa
== ISA_MIPS1
);
6231 macro_build (&offset_expr
, "lwc1", "T,o(b)",
6232 target_big_endian
? treg
+ 1 : treg
, r
, breg
);
6233 /* FIXME: A possible overflow which I don't know how to deal
6235 offset_expr
.X_add_number
+= 4;
6236 macro_build (&offset_expr
, "lwc1", "T,o(b)",
6237 target_big_endian
? treg
: treg
+ 1, r
, breg
);
6242 * The MIPS assembler seems to check for X_add_number not
6243 * being double aligned and generating:
6246 * addiu at,at,%lo(foo+1)
6249 * But, the resulting address is the same after relocation so why
6250 * generate the extra instruction?
6252 if (mips_opts
.arch
== CPU_R4650
)
6254 as_bad (_("opcode not supported on this processor"));
6257 /* Itbl support may require additional care here. */
6259 if (mips_opts
.isa
!= ISA_MIPS1
)
6270 if (mips_opts
.arch
== CPU_R4650
)
6272 as_bad (_("opcode not supported on this processor"));
6276 if (mips_opts
.isa
!= ISA_MIPS1
)
6284 /* Itbl support may require additional care here. */
6289 if (HAVE_64BIT_GPRS
)
6300 if (HAVE_64BIT_GPRS
)
6310 if (offset_expr
.X_op
!= O_symbol
6311 && offset_expr
.X_op
!= O_constant
)
6313 as_bad (_("expression too complex"));
6314 offset_expr
.X_op
= O_constant
;
6317 /* Even on a big endian machine $fn comes before $fn+1. We have
6318 to adjust when loading from memory. We set coproc if we must
6319 load $fn+1 first. */
6320 /* Itbl support may require additional care here. */
6321 if (! target_big_endian
)
6324 if (mips_pic
== NO_PIC
6325 || offset_expr
.X_op
== O_constant
)
6327 /* If this is a reference to a GP relative symbol, we want
6328 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
6329 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_GPREL16)
6330 If we have a base register, we use this
6332 <op> $treg,<sym>($at) (BFD_RELOC_GPREL16)
6333 <op> $treg+1,<sym>+4($at) (BFD_RELOC_GPREL16)
6334 If this is not a GP relative symbol, we want
6335 lui $at,<sym> (BFD_RELOC_HI16_S)
6336 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
6337 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
6338 If there is a base register, we add it to $at after the
6339 lui instruction. If there is a constant, we always use
6341 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
6342 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
6344 relax_start (offset_expr
.X_add_symbol
);
6347 tempreg
= mips_gp_register
;
6351 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6352 AT
, breg
, mips_gp_register
);
6357 /* Itbl support may require additional care here. */
6358 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
+ 1 : treg
,
6359 BFD_RELOC_GPREL16
, tempreg
);
6360 offset_expr
.X_add_number
+= 4;
6362 /* Set mips_optimize to 2 to avoid inserting an
6364 hold_mips_optimize
= mips_optimize
;
6366 /* Itbl support may require additional care here. */
6367 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
: treg
+ 1,
6368 BFD_RELOC_GPREL16
, tempreg
);
6369 mips_optimize
= hold_mips_optimize
;
6373 /* We just generated two relocs. When tc_gen_reloc
6374 handles this case, it will skip the first reloc and
6375 handle the second. The second reloc already has an
6376 extra addend of 4, which we added above. We must
6377 subtract it out, and then subtract another 4 to make
6378 the first reloc come out right. The second reloc
6379 will come out right because we are going to add 4 to
6380 offset_expr when we build its instruction below.
6382 If we have a symbol, then we don't want to include
6383 the offset, because it will wind up being included
6384 when we generate the reloc. */
6386 if (offset_expr
.X_op
== O_constant
)
6387 offset_expr
.X_add_number
-= 8;
6390 offset_expr
.X_add_number
= -4;
6391 offset_expr
.X_op
= O_constant
;
6395 macro_build_lui (&offset_expr
, AT
);
6397 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
6398 /* Itbl support may require additional care here. */
6399 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
+ 1 : treg
,
6400 BFD_RELOC_LO16
, AT
);
6401 /* FIXME: How do we handle overflow here? */
6402 offset_expr
.X_add_number
+= 4;
6403 /* Itbl support may require additional care here. */
6404 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
: treg
+ 1,
6405 BFD_RELOC_LO16
, AT
);
6406 if (mips_relax
.sequence
)
6409 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
6411 /* If this is a reference to an external symbol, we want
6412 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6417 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6419 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
6420 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
6421 If there is a base register we add it to $at before the
6422 lwc1 instructions. If there is a constant we include it
6423 in the lwc1 instructions. */
6425 expr1
.X_add_number
= offset_expr
.X_add_number
;
6426 if (expr1
.X_add_number
< -0x8000
6427 || expr1
.X_add_number
>= 0x8000 - 4)
6428 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6429 load_got_offset (AT
, &offset_expr
);
6432 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
6434 /* Set mips_optimize to 2 to avoid inserting an undesired
6436 hold_mips_optimize
= mips_optimize
;
6439 /* Itbl support may require additional care here. */
6440 relax_start (offset_expr
.X_add_symbol
);
6441 macro_build (&expr1
, s
, fmt
, coproc
? treg
+ 1 : treg
,
6442 BFD_RELOC_LO16
, AT
);
6443 expr1
.X_add_number
+= 4;
6444 macro_build (&expr1
, s
, fmt
, coproc
? treg
: treg
+ 1,
6445 BFD_RELOC_LO16
, AT
);
6447 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
+ 1 : treg
,
6448 BFD_RELOC_LO16
, AT
);
6449 offset_expr
.X_add_number
+= 4;
6450 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
: treg
+ 1,
6451 BFD_RELOC_LO16
, AT
);
6454 mips_optimize
= hold_mips_optimize
;
6456 else if (mips_pic
== SVR4_PIC
)
6460 /* If this is a reference to an external symbol, we want
6461 lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16)
6463 lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16)
6468 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6470 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
6471 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
6472 If there is a base register we add it to $at before the
6473 lwc1 instructions. If there is a constant we include it
6474 in the lwc1 instructions. */
6476 expr1
.X_add_number
= offset_expr
.X_add_number
;
6477 offset_expr
.X_add_number
= 0;
6478 if (expr1
.X_add_number
< -0x8000
6479 || expr1
.X_add_number
>= 0x8000 - 4)
6480 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6481 gpdelay
= reg_needs_delay (mips_gp_register
);
6482 relax_start (offset_expr
.X_add_symbol
);
6483 macro_build (&offset_expr
, "lui", "t,u",
6484 AT
, BFD_RELOC_MIPS_GOT_HI16
);
6485 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6486 AT
, AT
, mips_gp_register
);
6487 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
6488 AT
, BFD_RELOC_MIPS_GOT_LO16
, AT
);
6491 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
6492 /* Itbl support may require additional care here. */
6493 macro_build (&expr1
, s
, fmt
, coproc
? treg
+ 1 : treg
,
6494 BFD_RELOC_LO16
, AT
);
6495 expr1
.X_add_number
+= 4;
6497 /* Set mips_optimize to 2 to avoid inserting an undesired
6499 hold_mips_optimize
= mips_optimize
;
6501 /* Itbl support may require additional care here. */
6502 macro_build (&expr1
, s
, fmt
, coproc
? treg
: treg
+ 1,
6503 BFD_RELOC_LO16
, AT
);
6504 mips_optimize
= hold_mips_optimize
;
6505 expr1
.X_add_number
-= 4;
6508 offset_expr
.X_add_number
= expr1
.X_add_number
;
6510 macro_build (NULL
, "nop", "");
6511 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", AT
,
6512 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
6515 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
6516 /* Itbl support may require additional care here. */
6517 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
+ 1 : treg
,
6518 BFD_RELOC_LO16
, AT
);
6519 offset_expr
.X_add_number
+= 4;
6521 /* Set mips_optimize to 2 to avoid inserting an undesired
6523 hold_mips_optimize
= mips_optimize
;
6525 /* Itbl support may require additional care here. */
6526 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
: treg
+ 1,
6527 BFD_RELOC_LO16
, AT
);
6528 mips_optimize
= hold_mips_optimize
;
6542 assert (HAVE_32BIT_ADDRESSES
);
6543 macro_build (&offset_expr
, s
, "t,o(b)", treg
, BFD_RELOC_LO16
, breg
);
6544 offset_expr
.X_add_number
+= 4;
6545 macro_build (&offset_expr
, s
, "t,o(b)", treg
+ 1, BFD_RELOC_LO16
, breg
);
6548 /* New code added to support COPZ instructions.
6549 This code builds table entries out of the macros in mip_opcodes.
6550 R4000 uses interlocks to handle coproc delays.
6551 Other chips (like the R3000) require nops to be inserted for delays.
6553 FIXME: Currently, we require that the user handle delays.
6554 In order to fill delay slots for non-interlocked chips,
6555 we must have a way to specify delays based on the coprocessor.
6556 Eg. 4 cycles if load coproc reg from memory, 1 if in cache, etc.
6557 What are the side-effects of the cop instruction?
6558 What cache support might we have and what are its effects?
6559 Both coprocessor & memory require delays. how long???
6560 What registers are read/set/modified?
6562 If an itbl is provided to interpret cop instructions,
6563 this knowledge can be encoded in the itbl spec. */
6577 /* For now we just do C (same as Cz). The parameter will be
6578 stored in insn_opcode by mips_ip. */
6579 macro_build (NULL
, s
, "C", ip
->insn_opcode
);
6583 move_register (dreg
, sreg
);
6586 #ifdef LOSING_COMPILER
6588 /* Try and see if this is a new itbl instruction.
6589 This code builds table entries out of the macros in mip_opcodes.
6590 FIXME: For now we just assemble the expression and pass it's
6591 value along as a 32-bit immediate.
6592 We may want to have the assembler assemble this value,
6593 so that we gain the assembler's knowledge of delay slots,
6595 Would it be more efficient to use mask (id) here? */
6596 if (itbl_have_entries
6597 && (immed_expr
= itbl_assemble (ip
->insn_mo
->name
, "")))
6599 s
= ip
->insn_mo
->name
;
6601 coproc
= ITBL_DECODE_PNUM (immed_expr
);;
6602 macro_build (&immed_expr
, s
, "C");
6608 if (mips_opts
.noat
&& used_at
)
6609 as_bad (_("Macro used $at after \".set noat\""));
6613 macro2 (struct mips_cl_insn
*ip
)
6615 register int treg
, sreg
, dreg
, breg
;
6630 bfd_reloc_code_real_type r
;
6632 treg
= (ip
->insn_opcode
>> 16) & 0x1f;
6633 dreg
= (ip
->insn_opcode
>> 11) & 0x1f;
6634 sreg
= breg
= (ip
->insn_opcode
>> 21) & 0x1f;
6635 mask
= ip
->insn_mo
->mask
;
6637 expr1
.X_op
= O_constant
;
6638 expr1
.X_op_symbol
= NULL
;
6639 expr1
.X_add_symbol
= NULL
;
6640 expr1
.X_add_number
= 1;
6644 #endif /* LOSING_COMPILER */
6649 macro_build (NULL
, dbl
? "dmultu" : "multu", "s,t", sreg
, treg
);
6650 macro_build (NULL
, "mflo", "d", dreg
);
6656 /* The MIPS assembler some times generates shifts and adds. I'm
6657 not trying to be that fancy. GCC should do this for us
6660 load_register (AT
, &imm_expr
, dbl
);
6661 macro_build (NULL
, dbl
? "dmult" : "mult", "s,t", sreg
, AT
);
6662 macro_build (NULL
, "mflo", "d", dreg
);
6678 load_register (AT
, &imm_expr
, dbl
);
6679 macro_build (NULL
, dbl
? "dmult" : "mult", "s,t", sreg
, imm
? AT
: treg
);
6680 macro_build (NULL
, "mflo", "d", dreg
);
6681 macro_build (NULL
, dbl
? "dsra32" : "sra", "d,w,<", dreg
, dreg
, RA
);
6682 macro_build (NULL
, "mfhi", "d", AT
);
6684 macro_build (NULL
, "tne", "s,t,q", dreg
, AT
, 6);
6687 expr1
.X_add_number
= 8;
6688 macro_build (&expr1
, "beq", "s,t,p", dreg
, AT
);
6689 macro_build (NULL
, "nop", "", 0);
6690 macro_build (NULL
, "break", "c", 6);
6693 macro_build (NULL
, "mflo", "d", dreg
);
6709 load_register (AT
, &imm_expr
, dbl
);
6710 macro_build (NULL
, dbl
? "dmultu" : "multu", "s,t",
6711 sreg
, imm
? AT
: treg
);
6712 macro_build (NULL
, "mfhi", "d", AT
);
6713 macro_build (NULL
, "mflo", "d", dreg
);
6715 macro_build (NULL
, "tne", "s,t,q", AT
, 0, 6);
6718 expr1
.X_add_number
= 8;
6719 macro_build (&expr1
, "beq", "s,t,p", AT
, 0);
6720 macro_build (NULL
, "nop", "", 0);
6721 macro_build (NULL
, "break", "c", 6);
6727 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
6738 macro_build (NULL
, "dnegu", "d,w", tempreg
, treg
);
6739 macro_build (NULL
, "drorv", "d,t,s", dreg
, sreg
, tempreg
);
6743 macro_build (NULL
, "dsubu", "d,v,t", AT
, 0, treg
);
6744 macro_build (NULL
, "dsrlv", "d,t,s", AT
, sreg
, AT
);
6745 macro_build (NULL
, "dsllv", "d,t,s", dreg
, sreg
, treg
);
6746 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
6750 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
6761 macro_build (NULL
, "negu", "d,w", tempreg
, treg
);
6762 macro_build (NULL
, "rorv", "d,t,s", dreg
, sreg
, tempreg
);
6766 macro_build (NULL
, "subu", "d,v,t", AT
, 0, treg
);
6767 macro_build (NULL
, "srlv", "d,t,s", AT
, sreg
, AT
);
6768 macro_build (NULL
, "sllv", "d,t,s", dreg
, sreg
, treg
);
6769 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
6777 if (imm_expr
.X_op
!= O_constant
)
6778 as_bad (_("Improper rotate count"));
6779 rot
= imm_expr
.X_add_number
& 0x3f;
6780 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
6782 rot
= (64 - rot
) & 0x3f;
6784 macro_build (NULL
, "dror32", "d,w,<", dreg
, sreg
, rot
- 32);
6786 macro_build (NULL
, "dror", "d,w,<", dreg
, sreg
, rot
);
6791 macro_build (NULL
, "dsrl", "d,w,<", dreg
, sreg
, 0);
6794 l
= (rot
< 0x20) ? "dsll" : "dsll32";
6795 r
= ((0x40 - rot
) < 0x20) ? "dsrl" : "dsrl32";
6798 macro_build (NULL
, l
, "d,w,<", AT
, sreg
, rot
);
6799 macro_build (NULL
, r
, "d,w,<", dreg
, sreg
, (0x20 - rot
) & 0x1f);
6800 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
6808 if (imm_expr
.X_op
!= O_constant
)
6809 as_bad (_("Improper rotate count"));
6810 rot
= imm_expr
.X_add_number
& 0x1f;
6811 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
6813 macro_build (NULL
, "ror", "d,w,<", dreg
, sreg
, (32 - rot
) & 0x1f);
6818 macro_build (NULL
, "srl", "d,w,<", dreg
, sreg
, 0);
6822 macro_build (NULL
, "sll", "d,w,<", AT
, sreg
, rot
);
6823 macro_build (NULL
, "srl", "d,w,<", dreg
, sreg
, (0x20 - rot
) & 0x1f);
6824 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
6829 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
6831 macro_build (NULL
, "drorv", "d,t,s", dreg
, sreg
, treg
);
6835 macro_build (NULL
, "dsubu", "d,v,t", AT
, 0, treg
);
6836 macro_build (NULL
, "dsllv", "d,t,s", AT
, sreg
, AT
);
6837 macro_build (NULL
, "dsrlv", "d,t,s", dreg
, sreg
, treg
);
6838 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
6842 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
6844 macro_build (NULL
, "rorv", "d,t,s", dreg
, sreg
, treg
);
6848 macro_build (NULL
, "subu", "d,v,t", AT
, 0, treg
);
6849 macro_build (NULL
, "sllv", "d,t,s", AT
, sreg
, AT
);
6850 macro_build (NULL
, "srlv", "d,t,s", dreg
, sreg
, treg
);
6851 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
6859 if (imm_expr
.X_op
!= O_constant
)
6860 as_bad (_("Improper rotate count"));
6861 rot
= imm_expr
.X_add_number
& 0x3f;
6862 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
6865 macro_build (NULL
, "dror32", "d,w,<", dreg
, sreg
, rot
- 32);
6867 macro_build (NULL
, "dror", "d,w,<", dreg
, sreg
, rot
);
6872 macro_build (NULL
, "dsrl", "d,w,<", dreg
, sreg
, 0);
6875 r
= (rot
< 0x20) ? "dsrl" : "dsrl32";
6876 l
= ((0x40 - rot
) < 0x20) ? "dsll" : "dsll32";
6879 macro_build (NULL
, r
, "d,w,<", AT
, sreg
, rot
);
6880 macro_build (NULL
, l
, "d,w,<", dreg
, sreg
, (0x20 - rot
) & 0x1f);
6881 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
6889 if (imm_expr
.X_op
!= O_constant
)
6890 as_bad (_("Improper rotate count"));
6891 rot
= imm_expr
.X_add_number
& 0x1f;
6892 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
6894 macro_build (NULL
, "ror", "d,w,<", dreg
, sreg
, rot
);
6899 macro_build (NULL
, "srl", "d,w,<", dreg
, sreg
, 0);
6903 macro_build (NULL
, "srl", "d,w,<", AT
, sreg
, rot
);
6904 macro_build (NULL
, "sll", "d,w,<", dreg
, sreg
, (0x20 - rot
) & 0x1f);
6905 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
6910 if (mips_opts
.arch
== CPU_R4650
)
6912 as_bad (_("opcode not supported on this processor"));
6915 assert (mips_opts
.isa
== ISA_MIPS1
);
6916 /* Even on a big endian machine $fn comes before $fn+1. We have
6917 to adjust when storing to memory. */
6918 macro_build (&offset_expr
, "swc1", "T,o(b)",
6919 target_big_endian
? treg
+ 1 : treg
, BFD_RELOC_LO16
, breg
);
6920 offset_expr
.X_add_number
+= 4;
6921 macro_build (&offset_expr
, "swc1", "T,o(b)",
6922 target_big_endian
? treg
: treg
+ 1, BFD_RELOC_LO16
, breg
);
6927 macro_build (&expr1
, "sltiu", "t,r,j", dreg
, treg
, BFD_RELOC_LO16
);
6929 macro_build (&expr1
, "sltiu", "t,r,j", dreg
, sreg
, BFD_RELOC_LO16
);
6932 macro_build (NULL
, "xor", "d,v,t", dreg
, sreg
, treg
);
6933 macro_build (&expr1
, "sltiu", "t,r,j", dreg
, dreg
, BFD_RELOC_LO16
);
6938 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
6940 macro_build (&expr1
, "sltiu", "t,r,j", dreg
, sreg
, BFD_RELOC_LO16
);
6945 as_warn (_("Instruction %s: result is always false"),
6947 move_register (dreg
, 0);
6950 if (imm_expr
.X_op
== O_constant
6951 && imm_expr
.X_add_number
>= 0
6952 && imm_expr
.X_add_number
< 0x10000)
6954 macro_build (&imm_expr
, "xori", "t,r,i", dreg
, sreg
, BFD_RELOC_LO16
);
6956 else if (imm_expr
.X_op
== O_constant
6957 && imm_expr
.X_add_number
> -0x8000
6958 && imm_expr
.X_add_number
< 0)
6960 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
6961 macro_build (&imm_expr
, HAVE_32BIT_GPRS
? "addiu" : "daddiu",
6962 "t,r,j", dreg
, sreg
, BFD_RELOC_LO16
);
6966 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
6967 macro_build (NULL
, "xor", "d,v,t", dreg
, sreg
, AT
);
6970 macro_build (&expr1
, "sltiu", "t,r,j", dreg
, dreg
, BFD_RELOC_LO16
);
6973 case M_SGE
: /* sreg >= treg <==> not (sreg < treg) */
6979 macro_build (NULL
, s
, "d,v,t", dreg
, sreg
, treg
);
6980 macro_build (&expr1
, "xori", "t,r,i", dreg
, dreg
, BFD_RELOC_LO16
);
6983 case M_SGE_I
: /* sreg >= I <==> not (sreg < I) */
6985 if (imm_expr
.X_op
== O_constant
6986 && imm_expr
.X_add_number
>= -0x8000
6987 && imm_expr
.X_add_number
< 0x8000)
6989 macro_build (&imm_expr
, mask
== M_SGE_I
? "slti" : "sltiu", "t,r,j",
6990 dreg
, sreg
, BFD_RELOC_LO16
);
6994 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
6995 macro_build (NULL
, mask
== M_SGE_I
? "slt" : "sltu", "d,v,t",
6999 macro_build (&expr1
, "xori", "t,r,i", dreg
, dreg
, BFD_RELOC_LO16
);
7002 case M_SGT
: /* sreg > treg <==> treg < sreg */
7008 macro_build (NULL
, s
, "d,v,t", dreg
, treg
, sreg
);
7011 case M_SGT_I
: /* sreg > I <==> I < sreg */
7018 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7019 macro_build (NULL
, s
, "d,v,t", dreg
, AT
, sreg
);
7022 case M_SLE
: /* sreg <= treg <==> treg >= sreg <==> not (treg < sreg) */
7028 macro_build (NULL
, s
, "d,v,t", dreg
, treg
, sreg
);
7029 macro_build (&expr1
, "xori", "t,r,i", dreg
, dreg
, BFD_RELOC_LO16
);
7032 case M_SLE_I
: /* sreg <= I <==> I >= sreg <==> not (I < sreg) */
7039 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7040 macro_build (NULL
, s
, "d,v,t", dreg
, AT
, sreg
);
7041 macro_build (&expr1
, "xori", "t,r,i", dreg
, dreg
, BFD_RELOC_LO16
);
7045 if (imm_expr
.X_op
== O_constant
7046 && imm_expr
.X_add_number
>= -0x8000
7047 && imm_expr
.X_add_number
< 0x8000)
7049 macro_build (&imm_expr
, "slti", "t,r,j", dreg
, sreg
, BFD_RELOC_LO16
);
7053 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7054 macro_build (NULL
, "slt", "d,v,t", dreg
, sreg
, AT
);
7058 if (imm_expr
.X_op
== O_constant
7059 && imm_expr
.X_add_number
>= -0x8000
7060 && imm_expr
.X_add_number
< 0x8000)
7062 macro_build (&imm_expr
, "sltiu", "t,r,j", dreg
, sreg
,
7067 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7068 macro_build (NULL
, "sltu", "d,v,t", dreg
, sreg
, AT
);
7073 macro_build (NULL
, "sltu", "d,v,t", dreg
, 0, treg
);
7075 macro_build (NULL
, "sltu", "d,v,t", dreg
, 0, sreg
);
7078 macro_build (NULL
, "xor", "d,v,t", dreg
, sreg
, treg
);
7079 macro_build (NULL
, "sltu", "d,v,t", dreg
, 0, dreg
);
7084 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
7086 macro_build (NULL
, "sltu", "d,v,t", dreg
, 0, sreg
);
7091 as_warn (_("Instruction %s: result is always true"),
7093 macro_build (&expr1
, HAVE_32BIT_GPRS
? "addiu" : "daddiu", "t,r,j",
7094 dreg
, 0, BFD_RELOC_LO16
);
7097 if (imm_expr
.X_op
== O_constant
7098 && imm_expr
.X_add_number
>= 0
7099 && imm_expr
.X_add_number
< 0x10000)
7101 macro_build (&imm_expr
, "xori", "t,r,i", dreg
, sreg
, BFD_RELOC_LO16
);
7103 else if (imm_expr
.X_op
== O_constant
7104 && imm_expr
.X_add_number
> -0x8000
7105 && imm_expr
.X_add_number
< 0)
7107 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
7108 macro_build (&imm_expr
, HAVE_32BIT_GPRS
? "addiu" : "daddiu",
7109 "t,r,j", dreg
, sreg
, BFD_RELOC_LO16
);
7113 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7114 macro_build (NULL
, "xor", "d,v,t", dreg
, sreg
, AT
);
7117 macro_build (NULL
, "sltu", "d,v,t", dreg
, 0, dreg
);
7123 if (imm_expr
.X_op
== O_constant
7124 && imm_expr
.X_add_number
> -0x8000
7125 && imm_expr
.X_add_number
<= 0x8000)
7127 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
7128 macro_build (&imm_expr
, dbl
? "daddi" : "addi", "t,r,j",
7129 dreg
, sreg
, BFD_RELOC_LO16
);
7133 load_register (AT
, &imm_expr
, dbl
);
7134 macro_build (NULL
, dbl
? "dsub" : "sub", "d,v,t", dreg
, sreg
, AT
);
7140 if (imm_expr
.X_op
== O_constant
7141 && imm_expr
.X_add_number
> -0x8000
7142 && imm_expr
.X_add_number
<= 0x8000)
7144 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
7145 macro_build (&imm_expr
, dbl
? "daddiu" : "addiu", "t,r,j",
7146 dreg
, sreg
, BFD_RELOC_LO16
);
7150 load_register (AT
, &imm_expr
, dbl
);
7151 macro_build (NULL
, dbl
? "dsubu" : "subu", "d,v,t", dreg
, sreg
, AT
);
7173 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7174 macro_build (NULL
, s
, "s,t", sreg
, AT
);
7179 assert (mips_opts
.isa
== ISA_MIPS1
);
7181 sreg
= (ip
->insn_opcode
>> 11) & 0x1f; /* floating reg */
7182 dreg
= (ip
->insn_opcode
>> 06) & 0x1f; /* floating reg */
7185 * Is the double cfc1 instruction a bug in the mips assembler;
7186 * or is there a reason for it?
7189 macro_build (NULL
, "cfc1", "t,G", treg
, RA
);
7190 macro_build (NULL
, "cfc1", "t,G", treg
, RA
);
7191 macro_build (NULL
, "nop", "");
7192 expr1
.X_add_number
= 3;
7193 macro_build (&expr1
, "ori", "t,r,i", AT
, treg
, BFD_RELOC_LO16
);
7194 expr1
.X_add_number
= 2;
7195 macro_build (&expr1
, "xori", "t,r,i", AT
, AT
, BFD_RELOC_LO16
);
7196 macro_build (NULL
, "ctc1", "t,G", AT
, RA
);
7197 macro_build (NULL
, "nop", "");
7198 macro_build (NULL
, mask
== M_TRUNCWD
? "cvt.w.d" : "cvt.w.s", "D,S",
7200 macro_build (NULL
, "ctc1", "t,G", treg
, RA
);
7201 macro_build (NULL
, "nop", "");
7212 if (offset_expr
.X_add_number
>= 0x7fff)
7213 as_bad (_("operand overflow"));
7214 if (! target_big_endian
)
7215 ++offset_expr
.X_add_number
;
7216 macro_build (&offset_expr
, s
, "t,o(b)", AT
, BFD_RELOC_LO16
, breg
);
7217 if (! target_big_endian
)
7218 --offset_expr
.X_add_number
;
7220 ++offset_expr
.X_add_number
;
7221 macro_build (&offset_expr
, "lbu", "t,o(b)", treg
, BFD_RELOC_LO16
, breg
);
7222 macro_build (NULL
, "sll", "d,w,<", AT
, AT
, 8);
7223 macro_build (NULL
, "or", "d,v,t", treg
, treg
, AT
);
7236 if (offset_expr
.X_add_number
>= 0x8000 - off
)
7237 as_bad (_("operand overflow"));
7245 if (! target_big_endian
)
7246 offset_expr
.X_add_number
+= off
;
7247 macro_build (&offset_expr
, s
, "t,o(b)", tempreg
, BFD_RELOC_LO16
, breg
);
7248 if (! target_big_endian
)
7249 offset_expr
.X_add_number
-= off
;
7251 offset_expr
.X_add_number
+= off
;
7252 macro_build (&offset_expr
, s2
, "t,o(b)", tempreg
, BFD_RELOC_LO16
, breg
);
7254 /* If necessary, move the result in tempreg the final destination. */
7255 if (treg
== tempreg
)
7257 /* Protect second load's delay slot. */
7259 move_register (treg
, tempreg
);
7273 load_address (AT
, &offset_expr
, &used_at
);
7275 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, AT
, breg
);
7276 if (! target_big_endian
)
7277 expr1
.X_add_number
= off
;
7279 expr1
.X_add_number
= 0;
7280 macro_build (&expr1
, s
, "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
7281 if (! target_big_endian
)
7282 expr1
.X_add_number
= 0;
7284 expr1
.X_add_number
= off
;
7285 macro_build (&expr1
, s2
, "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
7291 load_address (AT
, &offset_expr
, &used_at
);
7293 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, AT
, breg
);
7294 if (target_big_endian
)
7295 expr1
.X_add_number
= 0;
7296 macro_build (&expr1
, mask
== M_ULH_A
? "lb" : "lbu", "t,o(b)",
7297 treg
, BFD_RELOC_LO16
, AT
);
7298 if (target_big_endian
)
7299 expr1
.X_add_number
= 1;
7301 expr1
.X_add_number
= 0;
7302 macro_build (&expr1
, "lbu", "t,o(b)", AT
, BFD_RELOC_LO16
, AT
);
7303 macro_build (NULL
, "sll", "d,w,<", treg
, treg
, 8);
7304 macro_build (NULL
, "or", "d,v,t", treg
, treg
, AT
);
7309 if (offset_expr
.X_add_number
>= 0x7fff)
7310 as_bad (_("operand overflow"));
7311 if (target_big_endian
)
7312 ++offset_expr
.X_add_number
;
7313 macro_build (&offset_expr
, "sb", "t,o(b)", treg
, BFD_RELOC_LO16
, breg
);
7314 macro_build (NULL
, "srl", "d,w,<", AT
, treg
, 8);
7315 if (target_big_endian
)
7316 --offset_expr
.X_add_number
;
7318 ++offset_expr
.X_add_number
;
7319 macro_build (&offset_expr
, "sb", "t,o(b)", AT
, BFD_RELOC_LO16
, breg
);
7332 if (offset_expr
.X_add_number
>= 0x8000 - off
)
7333 as_bad (_("operand overflow"));
7334 if (! target_big_endian
)
7335 offset_expr
.X_add_number
+= off
;
7336 macro_build (&offset_expr
, s
, "t,o(b)", treg
, BFD_RELOC_LO16
, breg
);
7337 if (! target_big_endian
)
7338 offset_expr
.X_add_number
-= off
;
7340 offset_expr
.X_add_number
+= off
;
7341 macro_build (&offset_expr
, s2
, "t,o(b)", treg
, BFD_RELOC_LO16
, breg
);
7355 load_address (AT
, &offset_expr
, &used_at
);
7357 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, AT
, breg
);
7358 if (! target_big_endian
)
7359 expr1
.X_add_number
= off
;
7361 expr1
.X_add_number
= 0;
7362 macro_build (&expr1
, s
, "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
7363 if (! target_big_endian
)
7364 expr1
.X_add_number
= 0;
7366 expr1
.X_add_number
= off
;
7367 macro_build (&expr1
, s2
, "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
7372 load_address (AT
, &offset_expr
, &used_at
);
7374 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, AT
, breg
);
7375 if (! target_big_endian
)
7376 expr1
.X_add_number
= 0;
7377 macro_build (&expr1
, "sb", "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
7378 macro_build (NULL
, "srl", "d,w,<", treg
, treg
, 8);
7379 if (! target_big_endian
)
7380 expr1
.X_add_number
= 1;
7382 expr1
.X_add_number
= 0;
7383 macro_build (&expr1
, "sb", "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
7384 if (! target_big_endian
)
7385 expr1
.X_add_number
= 0;
7387 expr1
.X_add_number
= 1;
7388 macro_build (&expr1
, "lbu", "t,o(b)", AT
, BFD_RELOC_LO16
, AT
);
7389 macro_build (NULL
, "sll", "d,w,<", treg
, treg
, 8);
7390 macro_build (NULL
, "or", "d,v,t", treg
, treg
, AT
);
7394 /* FIXME: Check if this is one of the itbl macros, since they
7395 are added dynamically. */
7396 as_bad (_("Macro %s not implemented yet"), ip
->insn_mo
->name
);
7399 if (mips_opts
.noat
&& used_at
)
7400 as_bad (_("Macro used $at after \".set noat\""));
7403 /* Implement macros in mips16 mode. */
7406 mips16_macro (struct mips_cl_insn
*ip
)
7409 int xreg
, yreg
, zreg
, tmp
;
7412 const char *s
, *s2
, *s3
;
7414 mask
= ip
->insn_mo
->mask
;
7416 xreg
= MIPS16_EXTRACT_OPERAND (RX
, *ip
);
7417 yreg
= MIPS16_EXTRACT_OPERAND (RY
, *ip
);
7418 zreg
= MIPS16_EXTRACT_OPERAND (RZ
, *ip
);
7420 expr1
.X_op
= O_constant
;
7421 expr1
.X_op_symbol
= NULL
;
7422 expr1
.X_add_symbol
= NULL
;
7423 expr1
.X_add_number
= 1;
7443 macro_build (NULL
, dbl
? "ddiv" : "div", "0,x,y", xreg
, yreg
);
7444 expr1
.X_add_number
= 2;
7445 macro_build (&expr1
, "bnez", "x,p", yreg
);
7446 macro_build (NULL
, "break", "6", 7);
7448 /* FIXME: The normal code checks for of -1 / -0x80000000 here,
7449 since that causes an overflow. We should do that as well,
7450 but I don't see how to do the comparisons without a temporary
7453 macro_build (NULL
, s
, "x", zreg
);
7473 macro_build (NULL
, s
, "0,x,y", xreg
, yreg
);
7474 expr1
.X_add_number
= 2;
7475 macro_build (&expr1
, "bnez", "x,p", yreg
);
7476 macro_build (NULL
, "break", "6", 7);
7478 macro_build (NULL
, s2
, "x", zreg
);
7484 macro_build (NULL
, dbl
? "dmultu" : "multu", "x,y", xreg
, yreg
);
7485 macro_build (NULL
, "mflo", "x", zreg
);
7493 if (imm_expr
.X_op
!= O_constant
)
7494 as_bad (_("Unsupported large constant"));
7495 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
7496 macro_build (&imm_expr
, dbl
? "daddiu" : "addiu", "y,x,4", yreg
, xreg
);
7500 if (imm_expr
.X_op
!= O_constant
)
7501 as_bad (_("Unsupported large constant"));
7502 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
7503 macro_build (&imm_expr
, "addiu", "x,k", xreg
);
7507 if (imm_expr
.X_op
!= O_constant
)
7508 as_bad (_("Unsupported large constant"));
7509 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
7510 macro_build (&imm_expr
, "daddiu", "y,j", yreg
);
7532 goto do_reverse_branch
;
7536 goto do_reverse_branch
;
7548 goto do_reverse_branch
;
7559 macro_build (NULL
, s
, "x,y", xreg
, yreg
);
7560 macro_build (&offset_expr
, s2
, "p");
7587 goto do_addone_branch_i
;
7592 goto do_addone_branch_i
;
7607 goto do_addone_branch_i
;
7614 if (imm_expr
.X_op
!= O_constant
)
7615 as_bad (_("Unsupported large constant"));
7616 ++imm_expr
.X_add_number
;
7619 macro_build (&imm_expr
, s
, s3
, xreg
);
7620 macro_build (&offset_expr
, s2
, "p");
7624 expr1
.X_add_number
= 0;
7625 macro_build (&expr1
, "slti", "x,8", yreg
);
7627 move_register (xreg
, yreg
);
7628 expr1
.X_add_number
= 2;
7629 macro_build (&expr1
, "bteqz", "p");
7630 macro_build (NULL
, "neg", "x,w", xreg
, xreg
);
7634 /* For consistency checking, verify that all bits are specified either
7635 by the match/mask part of the instruction definition, or by the
7638 validate_mips_insn (const struct mips_opcode
*opc
)
7640 const char *p
= opc
->args
;
7642 unsigned long used_bits
= opc
->mask
;
7644 if ((used_bits
& opc
->match
) != opc
->match
)
7646 as_bad (_("internal: bad mips opcode (mask error): %s %s"),
7647 opc
->name
, opc
->args
);
7650 #define USE_BITS(mask,shift) (used_bits |= ((mask) << (shift)))
7660 case 'A': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
7661 case 'B': USE_BITS (OP_MASK_INSMSB
, OP_SH_INSMSB
); break;
7662 case 'C': USE_BITS (OP_MASK_EXTMSBD
, OP_SH_EXTMSBD
); break;
7663 case 'D': USE_BITS (OP_MASK_RD
, OP_SH_RD
);
7664 USE_BITS (OP_MASK_SEL
, OP_SH_SEL
); break;
7665 case 'E': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
7666 case 'F': USE_BITS (OP_MASK_INSMSB
, OP_SH_INSMSB
); break;
7667 case 'G': USE_BITS (OP_MASK_EXTMSBD
, OP_SH_EXTMSBD
); break;
7668 case 'H': USE_BITS (OP_MASK_EXTMSBD
, OP_SH_EXTMSBD
); break;
7671 as_bad (_("internal: bad mips opcode (unknown extension operand type `+%c'): %s %s"),
7672 c
, opc
->name
, opc
->args
);
7676 case '<': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
7677 case '>': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
7679 case 'B': USE_BITS (OP_MASK_CODE20
, OP_SH_CODE20
); break;
7680 case 'C': USE_BITS (OP_MASK_COPZ
, OP_SH_COPZ
); break;
7681 case 'D': USE_BITS (OP_MASK_FD
, OP_SH_FD
); break;
7682 case 'E': USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
7684 case 'G': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
7685 case 'H': USE_BITS (OP_MASK_SEL
, OP_SH_SEL
); break;
7687 case 'J': USE_BITS (OP_MASK_CODE19
, OP_SH_CODE19
); break;
7688 case 'K': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
7690 case 'M': USE_BITS (OP_MASK_CCC
, OP_SH_CCC
); break;
7691 case 'N': USE_BITS (OP_MASK_BCC
, OP_SH_BCC
); break;
7692 case 'O': USE_BITS (OP_MASK_ALN
, OP_SH_ALN
); break;
7693 case 'Q': USE_BITS (OP_MASK_VSEL
, OP_SH_VSEL
);
7694 USE_BITS (OP_MASK_FT
, OP_SH_FT
); break;
7695 case 'R': USE_BITS (OP_MASK_FR
, OP_SH_FR
); break;
7696 case 'S': USE_BITS (OP_MASK_FS
, OP_SH_FS
); break;
7697 case 'T': USE_BITS (OP_MASK_FT
, OP_SH_FT
); break;
7698 case 'V': USE_BITS (OP_MASK_FS
, OP_SH_FS
); break;
7699 case 'W': USE_BITS (OP_MASK_FT
, OP_SH_FT
); break;
7700 case 'X': USE_BITS (OP_MASK_FD
, OP_SH_FD
); break;
7701 case 'Y': USE_BITS (OP_MASK_FS
, OP_SH_FS
); break;
7702 case 'Z': USE_BITS (OP_MASK_FT
, OP_SH_FT
); break;
7703 case 'a': USE_BITS (OP_MASK_TARGET
, OP_SH_TARGET
); break;
7704 case 'b': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
7705 case 'c': USE_BITS (OP_MASK_CODE
, OP_SH_CODE
); break;
7706 case 'd': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
7708 case 'h': USE_BITS (OP_MASK_PREFX
, OP_SH_PREFX
); break;
7709 case 'i': USE_BITS (OP_MASK_IMMEDIATE
, OP_SH_IMMEDIATE
); break;
7710 case 'j': USE_BITS (OP_MASK_DELTA
, OP_SH_DELTA
); break;
7711 case 'k': USE_BITS (OP_MASK_CACHE
, OP_SH_CACHE
); break;
7713 case 'o': USE_BITS (OP_MASK_DELTA
, OP_SH_DELTA
); break;
7714 case 'p': USE_BITS (OP_MASK_DELTA
, OP_SH_DELTA
); break;
7715 case 'q': USE_BITS (OP_MASK_CODE2
, OP_SH_CODE2
); break;
7716 case 'r': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
7717 case 's': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
7718 case 't': USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
7719 case 'u': USE_BITS (OP_MASK_IMMEDIATE
, OP_SH_IMMEDIATE
); break;
7720 case 'v': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
7721 case 'w': USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
7724 case 'P': USE_BITS (OP_MASK_PERFREG
, OP_SH_PERFREG
); break;
7725 case 'U': USE_BITS (OP_MASK_RD
, OP_SH_RD
);
7726 USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
7727 case 'e': USE_BITS (OP_MASK_VECBYTE
, OP_SH_VECBYTE
); break;
7728 case '%': USE_BITS (OP_MASK_VECALIGN
, OP_SH_VECALIGN
); break;
7732 as_bad (_("internal: bad mips opcode (unknown operand type `%c'): %s %s"),
7733 c
, opc
->name
, opc
->args
);
7737 if (used_bits
!= 0xffffffff)
7739 as_bad (_("internal: bad mips opcode (bits 0x%lx undefined): %s %s"),
7740 ~used_bits
& 0xffffffff, opc
->name
, opc
->args
);
7746 /* This routine assembles an instruction into its binary format. As a
7747 side effect, it sets one of the global variables imm_reloc or
7748 offset_reloc to the type of relocation to do if one of the operands
7749 is an address expression. */
7752 mips_ip (char *str
, struct mips_cl_insn
*ip
)
7757 struct mips_opcode
*insn
;
7760 unsigned int lastregno
= 0;
7761 unsigned int lastpos
= 0;
7762 unsigned int limlo
, limhi
;
7768 /* If the instruction contains a '.', we first try to match an instruction
7769 including the '.'. Then we try again without the '.'. */
7771 for (s
= str
; *s
!= '\0' && !ISSPACE (*s
); ++s
)
7774 /* If we stopped on whitespace, then replace the whitespace with null for
7775 the call to hash_find. Save the character we replaced just in case we
7776 have to re-parse the instruction. */
7783 insn
= (struct mips_opcode
*) hash_find (op_hash
, str
);
7785 /* If we didn't find the instruction in the opcode table, try again, but
7786 this time with just the instruction up to, but not including the
7790 /* Restore the character we overwrite above (if any). */
7794 /* Scan up to the first '.' or whitespace. */
7796 *s
!= '\0' && *s
!= '.' && !ISSPACE (*s
);
7800 /* If we did not find a '.', then we can quit now. */
7803 insn_error
= "unrecognized opcode";
7807 /* Lookup the instruction in the hash table. */
7809 if ((insn
= (struct mips_opcode
*) hash_find (op_hash
, str
)) == NULL
)
7811 insn_error
= "unrecognized opcode";
7821 assert (strcmp (insn
->name
, str
) == 0);
7823 if (OPCODE_IS_MEMBER (insn
,
7825 | (file_ase_mips16
? INSN_MIPS16
: 0)
7826 | (mips_opts
.ase_mdmx
? INSN_MDMX
: 0)
7827 | (mips_opts
.ase_mips3d
? INSN_MIPS3D
: 0)),
7833 if (insn
->pinfo
!= INSN_MACRO
)
7835 if (mips_opts
.arch
== CPU_R4650
&& (insn
->pinfo
& FP_D
) != 0)
7841 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
]
7842 && strcmp (insn
->name
, insn
[1].name
) == 0)
7851 static char buf
[100];
7853 _("opcode not supported on this processor: %s (%s)"),
7854 mips_cpu_info_from_arch (mips_opts
.arch
)->name
,
7855 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
7864 create_insn (ip
, insn
);
7866 for (args
= insn
->args
;; ++args
)
7870 s
+= strspn (s
, " \t");
7874 case '\0': /* end of args */
7887 INSERT_OPERAND (RS
, *ip
, lastregno
);
7891 INSERT_OPERAND (RT
, *ip
, lastregno
);
7895 INSERT_OPERAND (FT
, *ip
, lastregno
);
7899 INSERT_OPERAND (FS
, *ip
, lastregno
);
7905 /* Handle optional base register.
7906 Either the base register is omitted or
7907 we must have a left paren. */
7908 /* This is dependent on the next operand specifier
7909 is a base register specification. */
7910 assert (args
[1] == 'b' || args
[1] == '5'
7911 || args
[1] == '-' || args
[1] == '4');
7915 case ')': /* these must match exactly */
7922 case '+': /* Opcode extension character. */
7925 case 'A': /* ins/ext position, becomes LSB. */
7934 my_getExpression (&imm_expr
, s
);
7935 check_absolute_expr (ip
, &imm_expr
);
7936 if ((unsigned long) imm_expr
.X_add_number
< limlo
7937 || (unsigned long) imm_expr
.X_add_number
> limhi
)
7939 as_bad (_("Improper position (%lu)"),
7940 (unsigned long) imm_expr
.X_add_number
);
7941 imm_expr
.X_add_number
= limlo
;
7943 lastpos
= imm_expr
.X_add_number
;
7944 INSERT_OPERAND (SHAMT
, *ip
, imm_expr
.X_add_number
);
7945 imm_expr
.X_op
= O_absent
;
7949 case 'B': /* ins size, becomes MSB. */
7958 my_getExpression (&imm_expr
, s
);
7959 check_absolute_expr (ip
, &imm_expr
);
7960 /* Check for negative input so that small negative numbers
7961 will not succeed incorrectly. The checks against
7962 (pos+size) transitively check "size" itself,
7963 assuming that "pos" is reasonable. */
7964 if ((long) imm_expr
.X_add_number
< 0
7965 || ((unsigned long) imm_expr
.X_add_number
7967 || ((unsigned long) imm_expr
.X_add_number
7970 as_bad (_("Improper insert size (%lu, position %lu)"),
7971 (unsigned long) imm_expr
.X_add_number
,
7972 (unsigned long) lastpos
);
7973 imm_expr
.X_add_number
= limlo
- lastpos
;
7975 INSERT_OPERAND (INSMSB
, *ip
,
7976 lastpos
+ imm_expr
.X_add_number
- 1);
7977 imm_expr
.X_op
= O_absent
;
7981 case 'C': /* ext size, becomes MSBD. */
7994 my_getExpression (&imm_expr
, s
);
7995 check_absolute_expr (ip
, &imm_expr
);
7996 /* Check for negative input so that small negative numbers
7997 will not succeed incorrectly. The checks against
7998 (pos+size) transitively check "size" itself,
7999 assuming that "pos" is reasonable. */
8000 if ((long) imm_expr
.X_add_number
< 0
8001 || ((unsigned long) imm_expr
.X_add_number
8003 || ((unsigned long) imm_expr
.X_add_number
8006 as_bad (_("Improper extract size (%lu, position %lu)"),
8007 (unsigned long) imm_expr
.X_add_number
,
8008 (unsigned long) lastpos
);
8009 imm_expr
.X_add_number
= limlo
- lastpos
;
8011 INSERT_OPERAND (EXTMSBD
, *ip
, imm_expr
.X_add_number
- 1);
8012 imm_expr
.X_op
= O_absent
;
8017 /* +D is for disassembly only; never match. */
8021 /* "+I" is like "I", except that imm2_expr is used. */
8022 my_getExpression (&imm2_expr
, s
);
8023 if (imm2_expr
.X_op
!= O_big
8024 && imm2_expr
.X_op
!= O_constant
)
8025 insn_error
= _("absolute expression required");
8026 normalize_constant_expr (&imm2_expr
);
8031 as_bad (_("internal: bad mips opcode (unknown extension operand type `+%c'): %s %s"),
8032 *args
, insn
->name
, insn
->args
);
8033 /* Further processing is fruitless. */
8038 case '<': /* must be at least one digit */
8040 * According to the manual, if the shift amount is greater
8041 * than 31 or less than 0, then the shift amount should be
8042 * mod 32. In reality the mips assembler issues an error.
8043 * We issue a warning and mask out all but the low 5 bits.
8045 my_getExpression (&imm_expr
, s
);
8046 check_absolute_expr (ip
, &imm_expr
);
8047 if ((unsigned long) imm_expr
.X_add_number
> 31)
8048 as_warn (_("Improper shift amount (%lu)"),
8049 (unsigned long) imm_expr
.X_add_number
);
8050 INSERT_OPERAND (SHAMT
, *ip
, imm_expr
.X_add_number
);
8051 imm_expr
.X_op
= O_absent
;
8055 case '>': /* shift amount minus 32 */
8056 my_getExpression (&imm_expr
, s
);
8057 check_absolute_expr (ip
, &imm_expr
);
8058 if ((unsigned long) imm_expr
.X_add_number
< 32
8059 || (unsigned long) imm_expr
.X_add_number
> 63)
8061 INSERT_OPERAND (SHAMT
, *ip
, imm_expr
.X_add_number
- 32);
8062 imm_expr
.X_op
= O_absent
;
8066 case 'k': /* cache code */
8067 case 'h': /* prefx code */
8068 my_getExpression (&imm_expr
, s
);
8069 check_absolute_expr (ip
, &imm_expr
);
8070 if ((unsigned long) imm_expr
.X_add_number
> 31)
8071 as_warn (_("Invalid value for `%s' (%lu)"),
8073 (unsigned long) imm_expr
.X_add_number
);
8075 INSERT_OPERAND (CACHE
, *ip
, imm_expr
.X_add_number
);
8077 INSERT_OPERAND (PREFX
, *ip
, imm_expr
.X_add_number
);
8078 imm_expr
.X_op
= O_absent
;
8082 case 'c': /* break code */
8083 my_getExpression (&imm_expr
, s
);
8084 check_absolute_expr (ip
, &imm_expr
);
8085 if ((unsigned long) imm_expr
.X_add_number
> 1023)
8086 as_warn (_("Illegal break code (%lu)"),
8087 (unsigned long) imm_expr
.X_add_number
);
8088 INSERT_OPERAND (CODE
, *ip
, imm_expr
.X_add_number
);
8089 imm_expr
.X_op
= O_absent
;
8093 case 'q': /* lower break code */
8094 my_getExpression (&imm_expr
, s
);
8095 check_absolute_expr (ip
, &imm_expr
);
8096 if ((unsigned long) imm_expr
.X_add_number
> 1023)
8097 as_warn (_("Illegal lower break code (%lu)"),
8098 (unsigned long) imm_expr
.X_add_number
);
8099 INSERT_OPERAND (CODE2
, *ip
, imm_expr
.X_add_number
);
8100 imm_expr
.X_op
= O_absent
;
8104 case 'B': /* 20-bit syscall/break code. */
8105 my_getExpression (&imm_expr
, s
);
8106 check_absolute_expr (ip
, &imm_expr
);
8107 if ((unsigned long) imm_expr
.X_add_number
> OP_MASK_CODE20
)
8108 as_warn (_("Illegal 20-bit code (%lu)"),
8109 (unsigned long) imm_expr
.X_add_number
);
8110 INSERT_OPERAND (CODE20
, *ip
, imm_expr
.X_add_number
);
8111 imm_expr
.X_op
= O_absent
;
8115 case 'C': /* Coprocessor code */
8116 my_getExpression (&imm_expr
, s
);
8117 check_absolute_expr (ip
, &imm_expr
);
8118 if ((unsigned long) imm_expr
.X_add_number
>= (1 << 25))
8120 as_warn (_("Coproccesor code > 25 bits (%lu)"),
8121 (unsigned long) imm_expr
.X_add_number
);
8122 imm_expr
.X_add_number
&= ((1 << 25) - 1);
8124 ip
->insn_opcode
|= imm_expr
.X_add_number
;
8125 imm_expr
.X_op
= O_absent
;
8129 case 'J': /* 19-bit wait code. */
8130 my_getExpression (&imm_expr
, s
);
8131 check_absolute_expr (ip
, &imm_expr
);
8132 if ((unsigned long) imm_expr
.X_add_number
> OP_MASK_CODE19
)
8133 as_warn (_("Illegal 19-bit code (%lu)"),
8134 (unsigned long) imm_expr
.X_add_number
);
8135 INSERT_OPERAND (CODE19
, *ip
, imm_expr
.X_add_number
);
8136 imm_expr
.X_op
= O_absent
;
8140 case 'P': /* Performance register */
8141 my_getExpression (&imm_expr
, s
);
8142 check_absolute_expr (ip
, &imm_expr
);
8143 if (imm_expr
.X_add_number
!= 0 && imm_expr
.X_add_number
!= 1)
8144 as_warn (_("Invalid performance register (%lu)"),
8145 (unsigned long) imm_expr
.X_add_number
);
8146 INSERT_OPERAND (PERFREG
, *ip
, imm_expr
.X_add_number
);
8147 imm_expr
.X_op
= O_absent
;
8151 case 'b': /* base register */
8152 case 'd': /* destination register */
8153 case 's': /* source register */
8154 case 't': /* target register */
8155 case 'r': /* both target and source */
8156 case 'v': /* both dest and source */
8157 case 'w': /* both dest and target */
8158 case 'E': /* coprocessor target register */
8159 case 'G': /* coprocessor destination register */
8160 case 'K': /* 'rdhwr' destination register */
8161 case 'x': /* ignore register name */
8162 case 'z': /* must be zero register */
8163 case 'U': /* destination register (clo/clz). */
8178 while (ISDIGIT (*s
));
8180 as_bad (_("Invalid register number (%d)"), regno
);
8182 else if (*args
== 'E' || *args
== 'G' || *args
== 'K')
8186 if (s
[1] == 'r' && s
[2] == 'a')
8191 else if (s
[1] == 'f' && s
[2] == 'p')
8196 else if (s
[1] == 's' && s
[2] == 'p')
8201 else if (s
[1] == 'g' && s
[2] == 'p')
8206 else if (s
[1] == 'a' && s
[2] == 't')
8211 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '0')
8216 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '1')
8221 else if (s
[1] == 'z' && s
[2] == 'e' && s
[3] == 'r' && s
[4] == 'o')
8226 else if (itbl_have_entries
)
8231 p
= s
+ 1; /* advance past '$' */
8232 n
= itbl_get_field (&p
); /* n is name */
8234 /* See if this is a register defined in an
8236 if (itbl_get_reg_val (n
, &r
))
8238 /* Get_field advances to the start of
8239 the next field, so we need to back
8240 rack to the end of the last field. */
8244 s
= strchr (s
, '\0');
8258 as_warn (_("Used $at without \".set noat\""));
8264 if (c
== 'r' || c
== 'v' || c
== 'w')
8271 /* 'z' only matches $0. */
8272 if (c
== 'z' && regno
!= 0)
8275 /* Now that we have assembled one operand, we use the args string
8276 * to figure out where it goes in the instruction. */
8283 INSERT_OPERAND (RS
, *ip
, regno
);
8288 INSERT_OPERAND (RD
, *ip
, regno
);
8291 INSERT_OPERAND (RD
, *ip
, regno
);
8292 INSERT_OPERAND (RT
, *ip
, regno
);
8297 INSERT_OPERAND (RT
, *ip
, regno
);
8300 /* This case exists because on the r3000 trunc
8301 expands into a macro which requires a gp
8302 register. On the r6000 or r4000 it is
8303 assembled into a single instruction which
8304 ignores the register. Thus the insn version
8305 is MIPS_ISA2 and uses 'x', and the macro
8306 version is MIPS_ISA1 and uses 't'. */
8309 /* This case is for the div instruction, which
8310 acts differently if the destination argument
8311 is $0. This only matches $0, and is checked
8312 outside the switch. */
8315 /* Itbl operand; not yet implemented. FIXME ?? */
8317 /* What about all other operands like 'i', which
8318 can be specified in the opcode table? */
8328 INSERT_OPERAND (RS
, *ip
, lastregno
);
8331 INSERT_OPERAND (RT
, *ip
, lastregno
);
8336 case 'O': /* MDMX alignment immediate constant. */
8337 my_getExpression (&imm_expr
, s
);
8338 check_absolute_expr (ip
, &imm_expr
);
8339 if ((unsigned long) imm_expr
.X_add_number
> OP_MASK_ALN
)
8340 as_warn ("Improper align amount (%ld), using low bits",
8341 (long) imm_expr
.X_add_number
);
8342 INSERT_OPERAND (ALN
, *ip
, imm_expr
.X_add_number
);
8343 imm_expr
.X_op
= O_absent
;
8347 case 'Q': /* MDMX vector, element sel, or const. */
8350 /* MDMX Immediate. */
8351 my_getExpression (&imm_expr
, s
);
8352 check_absolute_expr (ip
, &imm_expr
);
8353 if ((unsigned long) imm_expr
.X_add_number
> OP_MASK_FT
)
8354 as_warn (_("Invalid MDMX Immediate (%ld)"),
8355 (long) imm_expr
.X_add_number
);
8356 INSERT_OPERAND (FT
, *ip
, imm_expr
.X_add_number
);
8357 if (ip
->insn_opcode
& (OP_MASK_VSEL
<< OP_SH_VSEL
))
8358 ip
->insn_opcode
|= MDMX_FMTSEL_IMM_QH
<< OP_SH_VSEL
;
8360 ip
->insn_opcode
|= MDMX_FMTSEL_IMM_OB
<< OP_SH_VSEL
;
8361 imm_expr
.X_op
= O_absent
;
8365 /* Not MDMX Immediate. Fall through. */
8366 case 'X': /* MDMX destination register. */
8367 case 'Y': /* MDMX source register. */
8368 case 'Z': /* MDMX target register. */
8370 case 'D': /* floating point destination register */
8371 case 'S': /* floating point source register */
8372 case 'T': /* floating point target register */
8373 case 'R': /* floating point source register */
8377 /* Accept $fN for FP and MDMX register numbers, and in
8378 addition accept $vN for MDMX register numbers. */
8379 if ((s
[0] == '$' && s
[1] == 'f' && ISDIGIT (s
[2]))
8380 || (is_mdmx
!= 0 && s
[0] == '$' && s
[1] == 'v'
8391 while (ISDIGIT (*s
));
8394 as_bad (_("Invalid float register number (%d)"), regno
);
8396 if ((regno
& 1) != 0
8398 && ! (strcmp (str
, "mtc1") == 0
8399 || strcmp (str
, "mfc1") == 0
8400 || strcmp (str
, "lwc1") == 0
8401 || strcmp (str
, "swc1") == 0
8402 || strcmp (str
, "l.s") == 0
8403 || strcmp (str
, "s.s") == 0))
8404 as_warn (_("Float register should be even, was %d"),
8412 if (c
== 'V' || c
== 'W')
8423 INSERT_OPERAND (FD
, *ip
, regno
);
8428 INSERT_OPERAND (FS
, *ip
, regno
);
8431 /* This is like 'Z', but also needs to fix the MDMX
8432 vector/scalar select bits. Note that the
8433 scalar immediate case is handled above. */
8436 int is_qh
= (ip
->insn_opcode
& (1 << OP_SH_VSEL
));
8437 int max_el
= (is_qh
? 3 : 7);
8439 my_getExpression(&imm_expr
, s
);
8440 check_absolute_expr (ip
, &imm_expr
);
8442 if (imm_expr
.X_add_number
> max_el
)
8443 as_bad(_("Bad element selector %ld"),
8444 (long) imm_expr
.X_add_number
);
8445 imm_expr
.X_add_number
&= max_el
;
8446 ip
->insn_opcode
|= (imm_expr
.X_add_number
8449 imm_expr
.X_op
= O_absent
;
8451 as_warn(_("Expecting ']' found '%s'"), s
);
8457 if (ip
->insn_opcode
& (OP_MASK_VSEL
<< OP_SH_VSEL
))
8458 ip
->insn_opcode
|= (MDMX_FMTSEL_VEC_QH
8461 ip
->insn_opcode
|= (MDMX_FMTSEL_VEC_OB
<<
8468 INSERT_OPERAND (FT
, *ip
, regno
);
8471 INSERT_OPERAND (FR
, *ip
, regno
);
8481 INSERT_OPERAND (FS
, *ip
, lastregno
);
8484 INSERT_OPERAND (FT
, *ip
, lastregno
);
8490 my_getExpression (&imm_expr
, s
);
8491 if (imm_expr
.X_op
!= O_big
8492 && imm_expr
.X_op
!= O_constant
)
8493 insn_error
= _("absolute expression required");
8494 normalize_constant_expr (&imm_expr
);
8499 my_getExpression (&offset_expr
, s
);
8500 *imm_reloc
= BFD_RELOC_32
;
8513 unsigned char temp
[8];
8515 unsigned int length
;
8520 /* These only appear as the last operand in an
8521 instruction, and every instruction that accepts
8522 them in any variant accepts them in all variants.
8523 This means we don't have to worry about backing out
8524 any changes if the instruction does not match.
8526 The difference between them is the size of the
8527 floating point constant and where it goes. For 'F'
8528 and 'L' the constant is 64 bits; for 'f' and 'l' it
8529 is 32 bits. Where the constant is placed is based
8530 on how the MIPS assembler does things:
8533 f -- immediate value
8536 The .lit4 and .lit8 sections are only used if
8537 permitted by the -G argument.
8539 The code below needs to know whether the target register
8540 is 32 or 64 bits wide. It relies on the fact 'f' and
8541 'F' are used with GPR-based instructions and 'l' and
8542 'L' are used with FPR-based instructions. */
8544 f64
= *args
== 'F' || *args
== 'L';
8545 using_gprs
= *args
== 'F' || *args
== 'f';
8547 save_in
= input_line_pointer
;
8548 input_line_pointer
= s
;
8549 err
= md_atof (f64
? 'd' : 'f', (char *) temp
, &len
);
8551 s
= input_line_pointer
;
8552 input_line_pointer
= save_in
;
8553 if (err
!= NULL
&& *err
!= '\0')
8555 as_bad (_("Bad floating point constant: %s"), err
);
8556 memset (temp
, '\0', sizeof temp
);
8557 length
= f64
? 8 : 4;
8560 assert (length
== (unsigned) (f64
? 8 : 4));
8564 && (g_switch_value
< 4
8565 || (temp
[0] == 0 && temp
[1] == 0)
8566 || (temp
[2] == 0 && temp
[3] == 0))))
8568 imm_expr
.X_op
= O_constant
;
8569 if (! target_big_endian
)
8570 imm_expr
.X_add_number
= bfd_getl32 (temp
);
8572 imm_expr
.X_add_number
= bfd_getb32 (temp
);
8575 && ! mips_disable_float_construction
8576 /* Constants can only be constructed in GPRs and
8577 copied to FPRs if the GPRs are at least as wide
8578 as the FPRs. Force the constant into memory if
8579 we are using 64-bit FPRs but the GPRs are only
8582 || ! (HAVE_64BIT_FPRS
&& HAVE_32BIT_GPRS
))
8583 && ((temp
[0] == 0 && temp
[1] == 0)
8584 || (temp
[2] == 0 && temp
[3] == 0))
8585 && ((temp
[4] == 0 && temp
[5] == 0)
8586 || (temp
[6] == 0 && temp
[7] == 0)))
8588 /* The value is simple enough to load with a couple of
8589 instructions. If using 32-bit registers, set
8590 imm_expr to the high order 32 bits and offset_expr to
8591 the low order 32 bits. Otherwise, set imm_expr to
8592 the entire 64 bit constant. */
8593 if (using_gprs
? HAVE_32BIT_GPRS
: HAVE_32BIT_FPRS
)
8595 imm_expr
.X_op
= O_constant
;
8596 offset_expr
.X_op
= O_constant
;
8597 if (! target_big_endian
)
8599 imm_expr
.X_add_number
= bfd_getl32 (temp
+ 4);
8600 offset_expr
.X_add_number
= bfd_getl32 (temp
);
8604 imm_expr
.X_add_number
= bfd_getb32 (temp
);
8605 offset_expr
.X_add_number
= bfd_getb32 (temp
+ 4);
8607 if (offset_expr
.X_add_number
== 0)
8608 offset_expr
.X_op
= O_absent
;
8610 else if (sizeof (imm_expr
.X_add_number
) > 4)
8612 imm_expr
.X_op
= O_constant
;
8613 if (! target_big_endian
)
8614 imm_expr
.X_add_number
= bfd_getl64 (temp
);
8616 imm_expr
.X_add_number
= bfd_getb64 (temp
);
8620 imm_expr
.X_op
= O_big
;
8621 imm_expr
.X_add_number
= 4;
8622 if (! target_big_endian
)
8624 generic_bignum
[0] = bfd_getl16 (temp
);
8625 generic_bignum
[1] = bfd_getl16 (temp
+ 2);
8626 generic_bignum
[2] = bfd_getl16 (temp
+ 4);
8627 generic_bignum
[3] = bfd_getl16 (temp
+ 6);
8631 generic_bignum
[0] = bfd_getb16 (temp
+ 6);
8632 generic_bignum
[1] = bfd_getb16 (temp
+ 4);
8633 generic_bignum
[2] = bfd_getb16 (temp
+ 2);
8634 generic_bignum
[3] = bfd_getb16 (temp
);
8640 const char *newname
;
8643 /* Switch to the right section. */
8645 subseg
= now_subseg
;
8648 default: /* unused default case avoids warnings. */
8650 newname
= RDATA_SECTION_NAME
;
8651 if (g_switch_value
>= 8)
8655 newname
= RDATA_SECTION_NAME
;
8658 assert (g_switch_value
>= 4);
8662 new_seg
= subseg_new (newname
, (subsegT
) 0);
8663 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
8664 bfd_set_section_flags (stdoutput
, new_seg
,
8669 frag_align (*args
== 'l' ? 2 : 3, 0, 0);
8670 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
8671 && strcmp (TARGET_OS
, "elf") != 0)
8672 record_alignment (new_seg
, 4);
8674 record_alignment (new_seg
, *args
== 'l' ? 2 : 3);
8676 as_bad (_("Can't use floating point insn in this section"));
8678 /* Set the argument to the current address in the
8680 offset_expr
.X_op
= O_symbol
;
8681 offset_expr
.X_add_symbol
=
8682 symbol_new ("L0\001", now_seg
,
8683 (valueT
) frag_now_fix (), frag_now
);
8684 offset_expr
.X_add_number
= 0;
8686 /* Put the floating point number into the section. */
8687 p
= frag_more ((int) length
);
8688 memcpy (p
, temp
, length
);
8690 /* Switch back to the original section. */
8691 subseg_set (seg
, subseg
);
8696 case 'i': /* 16 bit unsigned immediate */
8697 case 'j': /* 16 bit signed immediate */
8698 *imm_reloc
= BFD_RELOC_LO16
;
8699 if (my_getSmallExpression (&imm_expr
, imm_reloc
, s
) == 0)
8702 offsetT minval
, maxval
;
8704 more
= (insn
+ 1 < &mips_opcodes
[NUMOPCODES
]
8705 && strcmp (insn
->name
, insn
[1].name
) == 0);
8707 /* If the expression was written as an unsigned number,
8708 only treat it as signed if there are no more
8712 && sizeof (imm_expr
.X_add_number
) <= 4
8713 && imm_expr
.X_op
== O_constant
8714 && imm_expr
.X_add_number
< 0
8715 && imm_expr
.X_unsigned
8719 /* For compatibility with older assemblers, we accept
8720 0x8000-0xffff as signed 16-bit numbers when only
8721 signed numbers are allowed. */
8723 minval
= 0, maxval
= 0xffff;
8725 minval
= -0x8000, maxval
= 0x7fff;
8727 minval
= -0x8000, maxval
= 0xffff;
8729 if (imm_expr
.X_op
!= O_constant
8730 || imm_expr
.X_add_number
< minval
8731 || imm_expr
.X_add_number
> maxval
)
8735 if (imm_expr
.X_op
== O_constant
8736 || imm_expr
.X_op
== O_big
)
8737 as_bad (_("expression out of range"));
8743 case 'o': /* 16 bit offset */
8744 /* Check whether there is only a single bracketed expression
8745 left. If so, it must be the base register and the
8746 constant must be zero. */
8747 if (*s
== '(' && strchr (s
+ 1, '(') == 0)
8749 offset_expr
.X_op
= O_constant
;
8750 offset_expr
.X_add_number
= 0;
8754 /* If this value won't fit into a 16 bit offset, then go
8755 find a macro that will generate the 32 bit offset
8757 if (my_getSmallExpression (&offset_expr
, offset_reloc
, s
) == 0
8758 && (offset_expr
.X_op
!= O_constant
8759 || offset_expr
.X_add_number
>= 0x8000
8760 || offset_expr
.X_add_number
< -0x8000))
8766 case 'p': /* pc relative offset */
8767 *offset_reloc
= BFD_RELOC_16_PCREL_S2
;
8768 my_getExpression (&offset_expr
, s
);
8772 case 'u': /* upper 16 bits */
8773 if (my_getSmallExpression (&imm_expr
, imm_reloc
, s
) == 0
8774 && imm_expr
.X_op
== O_constant
8775 && (imm_expr
.X_add_number
< 0
8776 || imm_expr
.X_add_number
>= 0x10000))
8777 as_bad (_("lui expression not in range 0..65535"));
8781 case 'a': /* 26 bit address */
8782 my_getExpression (&offset_expr
, s
);
8784 *offset_reloc
= BFD_RELOC_MIPS_JMP
;
8787 case 'N': /* 3 bit branch condition code */
8788 case 'M': /* 3 bit compare condition code */
8789 if (strncmp (s
, "$fcc", 4) != 0)
8799 while (ISDIGIT (*s
));
8801 as_bad (_("Invalid condition code register $fcc%d"), regno
);
8802 if ((strcmp(str
+ strlen(str
) - 3, ".ps") == 0
8803 || strcmp(str
+ strlen(str
) - 5, "any2f") == 0
8804 || strcmp(str
+ strlen(str
) - 5, "any2t") == 0)
8805 && (regno
& 1) != 0)
8806 as_warn(_("Condition code register should be even for %s, was %d"),
8808 if ((strcmp(str
+ strlen(str
) - 5, "any4f") == 0
8809 || strcmp(str
+ strlen(str
) - 5, "any4t") == 0)
8810 && (regno
& 3) != 0)
8811 as_warn(_("Condition code register should be 0 or 4 for %s, was %d"),
8814 INSERT_OPERAND (BCC
, *ip
, regno
);
8816 INSERT_OPERAND (CCC
, *ip
, regno
);
8820 if (s
[0] == '0' && (s
[1] == 'x' || s
[1] == 'X'))
8831 while (ISDIGIT (*s
));
8834 c
= 8; /* Invalid sel value. */
8837 as_bad (_("invalid coprocessor sub-selection value (0-7)"));
8838 ip
->insn_opcode
|= c
;
8842 /* Must be at least one digit. */
8843 my_getExpression (&imm_expr
, s
);
8844 check_absolute_expr (ip
, &imm_expr
);
8846 if ((unsigned long) imm_expr
.X_add_number
8847 > (unsigned long) OP_MASK_VECBYTE
)
8849 as_bad (_("bad byte vector index (%ld)"),
8850 (long) imm_expr
.X_add_number
);
8851 imm_expr
.X_add_number
= 0;
8854 INSERT_OPERAND (VECBYTE
, *ip
, imm_expr
.X_add_number
);
8855 imm_expr
.X_op
= O_absent
;
8860 my_getExpression (&imm_expr
, s
);
8861 check_absolute_expr (ip
, &imm_expr
);
8863 if ((unsigned long) imm_expr
.X_add_number
8864 > (unsigned long) OP_MASK_VECALIGN
)
8866 as_bad (_("bad byte vector index (%ld)"),
8867 (long) imm_expr
.X_add_number
);
8868 imm_expr
.X_add_number
= 0;
8871 INSERT_OPERAND (VECALIGN
, *ip
, imm_expr
.X_add_number
);
8872 imm_expr
.X_op
= O_absent
;
8877 as_bad (_("bad char = '%c'\n"), *args
);
8882 /* Args don't match. */
8883 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
8884 !strcmp (insn
->name
, insn
[1].name
))
8888 insn_error
= _("illegal operands");
8893 insn_error
= _("illegal operands");
8898 /* This routine assembles an instruction into its binary format when
8899 assembling for the mips16. As a side effect, it sets one of the
8900 global variables imm_reloc or offset_reloc to the type of
8901 relocation to do if one of the operands is an address expression.
8902 It also sets mips16_small and mips16_ext if the user explicitly
8903 requested a small or extended instruction. */
8906 mips16_ip (char *str
, struct mips_cl_insn
*ip
)
8910 struct mips_opcode
*insn
;
8913 unsigned int lastregno
= 0;
8919 mips16_small
= FALSE
;
8922 for (s
= str
; ISLOWER (*s
); ++s
)
8934 if (s
[1] == 't' && s
[2] == ' ')
8937 mips16_small
= TRUE
;
8941 else if (s
[1] == 'e' && s
[2] == ' ')
8950 insn_error
= _("unknown opcode");
8954 if (mips_opts
.noautoextend
&& ! mips16_ext
)
8955 mips16_small
= TRUE
;
8957 if ((insn
= (struct mips_opcode
*) hash_find (mips16_op_hash
, str
)) == NULL
)
8959 insn_error
= _("unrecognized opcode");
8966 assert (strcmp (insn
->name
, str
) == 0);
8968 create_insn (ip
, insn
);
8969 imm_expr
.X_op
= O_absent
;
8970 imm_reloc
[0] = BFD_RELOC_UNUSED
;
8971 imm_reloc
[1] = BFD_RELOC_UNUSED
;
8972 imm_reloc
[2] = BFD_RELOC_UNUSED
;
8973 imm2_expr
.X_op
= O_absent
;
8974 offset_expr
.X_op
= O_absent
;
8975 offset_reloc
[0] = BFD_RELOC_UNUSED
;
8976 offset_reloc
[1] = BFD_RELOC_UNUSED
;
8977 offset_reloc
[2] = BFD_RELOC_UNUSED
;
8978 for (args
= insn
->args
; 1; ++args
)
8985 /* In this switch statement we call break if we did not find
8986 a match, continue if we did find a match, or return if we
8995 /* Stuff the immediate value in now, if we can. */
8996 if (imm_expr
.X_op
== O_constant
8997 && *imm_reloc
> BFD_RELOC_UNUSED
8998 && insn
->pinfo
!= INSN_MACRO
)
9002 switch (*offset_reloc
)
9004 case BFD_RELOC_MIPS16_HI16_S
:
9005 tmp
= (imm_expr
.X_add_number
+ 0x8000) >> 16;
9008 case BFD_RELOC_MIPS16_HI16
:
9009 tmp
= imm_expr
.X_add_number
>> 16;
9012 case BFD_RELOC_MIPS16_LO16
:
9013 tmp
= ((imm_expr
.X_add_number
+ 0x8000) & 0xffff)
9017 case BFD_RELOC_UNUSED
:
9018 tmp
= imm_expr
.X_add_number
;
9024 *offset_reloc
= BFD_RELOC_UNUSED
;
9026 mips16_immed (NULL
, 0, *imm_reloc
- BFD_RELOC_UNUSED
,
9027 tmp
, TRUE
, mips16_small
,
9028 mips16_ext
, &ip
->insn_opcode
,
9029 &ip
->use_extend
, &ip
->extend
);
9030 imm_expr
.X_op
= O_absent
;
9031 *imm_reloc
= BFD_RELOC_UNUSED
;
9045 MIPS16_INSERT_OPERAND (RX
, *ip
, lastregno
);
9048 MIPS16_INSERT_OPERAND (RY
, *ip
, lastregno
);
9064 MIPS16_INSERT_OPERAND (RX
, *ip
, lastregno
);
9066 MIPS16_INSERT_OPERAND (RY
, *ip
, lastregno
);
9093 while (ISDIGIT (*s
));
9096 as_bad (_("invalid register number (%d)"), regno
);
9102 if (s
[1] == 'r' && s
[2] == 'a')
9107 else if (s
[1] == 'f' && s
[2] == 'p')
9112 else if (s
[1] == 's' && s
[2] == 'p')
9117 else if (s
[1] == 'g' && s
[2] == 'p')
9122 else if (s
[1] == 'a' && s
[2] == 't')
9127 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '0')
9132 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '1')
9137 else if (s
[1] == 'z' && s
[2] == 'e' && s
[3] == 'r' && s
[4] == 'o')
9150 if (c
== 'v' || c
== 'w')
9152 regno
= mips16_to_32_reg_map
[lastregno
];
9166 regno
= mips32_to_16_reg_map
[regno
];
9171 regno
= ILLEGAL_REG
;
9176 regno
= ILLEGAL_REG
;
9181 regno
= ILLEGAL_REG
;
9186 if (regno
== AT
&& ! mips_opts
.noat
)
9187 as_warn (_("used $at without \".set noat\""));
9194 if (regno
== ILLEGAL_REG
)
9201 MIPS16_INSERT_OPERAND (RX
, *ip
, regno
);
9205 MIPS16_INSERT_OPERAND (RY
, *ip
, regno
);
9208 MIPS16_INSERT_OPERAND (RZ
, *ip
, regno
);
9211 MIPS16_INSERT_OPERAND (MOVE32Z
, *ip
, regno
);
9217 MIPS16_INSERT_OPERAND (REGR32
, *ip
, regno
);
9220 regno
= ((regno
& 7) << 2) | ((regno
& 0x18) >> 3);
9221 MIPS16_INSERT_OPERAND (REG32R
, *ip
, regno
);
9231 if (strncmp (s
, "$pc", 3) == 0)
9248 i
= my_getSmallExpression (&imm_expr
, imm_reloc
, s
);
9251 if (imm_expr
.X_op
!= O_constant
)
9254 ip
->use_extend
= TRUE
;
9259 /* We need to relax this instruction. */
9260 *offset_reloc
= *imm_reloc
;
9261 *imm_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
9266 *imm_reloc
= BFD_RELOC_UNUSED
;
9274 my_getExpression (&imm_expr
, s
);
9275 if (imm_expr
.X_op
== O_register
)
9277 /* What we thought was an expression turned out to
9280 if (s
[0] == '(' && args
[1] == '(')
9282 /* It looks like the expression was omitted
9283 before a register indirection, which means
9284 that the expression is implicitly zero. We
9285 still set up imm_expr, so that we handle
9286 explicit extensions correctly. */
9287 imm_expr
.X_op
= O_constant
;
9288 imm_expr
.X_add_number
= 0;
9289 *imm_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
9296 /* We need to relax this instruction. */
9297 *imm_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
9306 /* We use offset_reloc rather than imm_reloc for the PC
9307 relative operands. This lets macros with both
9308 immediate and address operands work correctly. */
9309 my_getExpression (&offset_expr
, s
);
9311 if (offset_expr
.X_op
== O_register
)
9314 /* We need to relax this instruction. */
9315 *offset_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
9319 case '6': /* break code */
9320 my_getExpression (&imm_expr
, s
);
9321 check_absolute_expr (ip
, &imm_expr
);
9322 if ((unsigned long) imm_expr
.X_add_number
> 63)
9323 as_warn (_("Invalid value for `%s' (%lu)"),
9325 (unsigned long) imm_expr
.X_add_number
);
9326 MIPS16_INSERT_OPERAND (IMM6
, *ip
, imm_expr
.X_add_number
);
9327 imm_expr
.X_op
= O_absent
;
9331 case 'a': /* 26 bit address */
9332 my_getExpression (&offset_expr
, s
);
9334 *offset_reloc
= BFD_RELOC_MIPS16_JMP
;
9335 ip
->insn_opcode
<<= 16;
9338 case 'l': /* register list for entry macro */
9339 case 'L': /* register list for exit macro */
9349 int freg
, reg1
, reg2
;
9351 while (*s
== ' ' || *s
== ',')
9355 as_bad (_("can't parse register list"));
9367 while (ISDIGIT (*s
))
9389 as_bad (_("invalid register list"));
9394 while (ISDIGIT (*s
))
9401 if (freg
&& reg1
== 0 && reg2
== 0 && c
== 'L')
9406 else if (freg
&& reg1
== 0 && reg2
== 1 && c
== 'L')
9411 else if (reg1
== 4 && reg2
>= 4 && reg2
<= 7 && c
!= 'L')
9412 mask
|= (reg2
- 3) << 3;
9413 else if (reg1
== 16 && reg2
>= 16 && reg2
<= 17)
9414 mask
|= (reg2
- 15) << 1;
9415 else if (reg1
== RA
&& reg2
== RA
)
9419 as_bad (_("invalid register list"));
9423 /* The mask is filled in in the opcode table for the
9424 benefit of the disassembler. We remove it before
9425 applying the actual mask. */
9426 ip
->insn_opcode
&= ~ ((7 << 3) << MIPS16OP_SH_IMM6
);
9427 ip
->insn_opcode
|= mask
<< MIPS16OP_SH_IMM6
;
9431 case 'e': /* extend code */
9432 my_getExpression (&imm_expr
, s
);
9433 check_absolute_expr (ip
, &imm_expr
);
9434 if ((unsigned long) imm_expr
.X_add_number
> 0x7ff)
9436 as_warn (_("Invalid value for `%s' (%lu)"),
9438 (unsigned long) imm_expr
.X_add_number
);
9439 imm_expr
.X_add_number
&= 0x7ff;
9441 ip
->insn_opcode
|= imm_expr
.X_add_number
;
9442 imm_expr
.X_op
= O_absent
;
9452 /* Args don't match. */
9453 if (insn
+ 1 < &mips16_opcodes
[bfd_mips16_num_opcodes
] &&
9454 strcmp (insn
->name
, insn
[1].name
) == 0)
9461 insn_error
= _("illegal operands");
9467 /* This structure holds information we know about a mips16 immediate
9470 struct mips16_immed_operand
9472 /* The type code used in the argument string in the opcode table. */
9474 /* The number of bits in the short form of the opcode. */
9476 /* The number of bits in the extended form of the opcode. */
9478 /* The amount by which the short form is shifted when it is used;
9479 for example, the sw instruction has a shift count of 2. */
9481 /* The amount by which the short form is shifted when it is stored
9482 into the instruction code. */
9484 /* Non-zero if the short form is unsigned. */
9486 /* Non-zero if the extended form is unsigned. */
9488 /* Non-zero if the value is PC relative. */
9492 /* The mips16 immediate operand types. */
9494 static const struct mips16_immed_operand mips16_immed_operands
[] =
9496 { '<', 3, 5, 0, MIPS16OP_SH_RZ
, 1, 1, 0 },
9497 { '>', 3, 5, 0, MIPS16OP_SH_RX
, 1, 1, 0 },
9498 { '[', 3, 6, 0, MIPS16OP_SH_RZ
, 1, 1, 0 },
9499 { ']', 3, 6, 0, MIPS16OP_SH_RX
, 1, 1, 0 },
9500 { '4', 4, 15, 0, MIPS16OP_SH_IMM4
, 0, 0, 0 },
9501 { '5', 5, 16, 0, MIPS16OP_SH_IMM5
, 1, 0, 0 },
9502 { 'H', 5, 16, 1, MIPS16OP_SH_IMM5
, 1, 0, 0 },
9503 { 'W', 5, 16, 2, MIPS16OP_SH_IMM5
, 1, 0, 0 },
9504 { 'D', 5, 16, 3, MIPS16OP_SH_IMM5
, 1, 0, 0 },
9505 { 'j', 5, 16, 0, MIPS16OP_SH_IMM5
, 0, 0, 0 },
9506 { '8', 8, 16, 0, MIPS16OP_SH_IMM8
, 1, 0, 0 },
9507 { 'V', 8, 16, 2, MIPS16OP_SH_IMM8
, 1, 0, 0 },
9508 { 'C', 8, 16, 3, MIPS16OP_SH_IMM8
, 1, 0, 0 },
9509 { 'U', 8, 16, 0, MIPS16OP_SH_IMM8
, 1, 1, 0 },
9510 { 'k', 8, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 0 },
9511 { 'K', 8, 16, 3, MIPS16OP_SH_IMM8
, 0, 0, 0 },
9512 { 'p', 8, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 1 },
9513 { 'q', 11, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 1 },
9514 { 'A', 8, 16, 2, MIPS16OP_SH_IMM8
, 1, 0, 1 },
9515 { 'B', 5, 16, 3, MIPS16OP_SH_IMM5
, 1, 0, 1 },
9516 { 'E', 5, 16, 2, MIPS16OP_SH_IMM5
, 1, 0, 1 }
9519 #define MIPS16_NUM_IMMED \
9520 (sizeof mips16_immed_operands / sizeof mips16_immed_operands[0])
9522 /* Handle a mips16 instruction with an immediate value. This or's the
9523 small immediate value into *INSN. It sets *USE_EXTEND to indicate
9524 whether an extended value is needed; if one is needed, it sets
9525 *EXTEND to the value. The argument type is TYPE. The value is VAL.
9526 If SMALL is true, an unextended opcode was explicitly requested.
9527 If EXT is true, an extended opcode was explicitly requested. If
9528 WARN is true, warn if EXT does not match reality. */
9531 mips16_immed (char *file
, unsigned int line
, int type
, offsetT val
,
9532 bfd_boolean warn
, bfd_boolean small
, bfd_boolean ext
,
9533 unsigned long *insn
, bfd_boolean
*use_extend
,
9534 unsigned short *extend
)
9536 register const struct mips16_immed_operand
*op
;
9537 int mintiny
, maxtiny
;
9538 bfd_boolean needext
;
9540 op
= mips16_immed_operands
;
9541 while (op
->type
!= type
)
9544 assert (op
< mips16_immed_operands
+ MIPS16_NUM_IMMED
);
9549 if (type
== '<' || type
== '>' || type
== '[' || type
== ']')
9552 maxtiny
= 1 << op
->nbits
;
9557 maxtiny
= (1 << op
->nbits
) - 1;
9562 mintiny
= - (1 << (op
->nbits
- 1));
9563 maxtiny
= (1 << (op
->nbits
- 1)) - 1;
9566 /* Branch offsets have an implicit 0 in the lowest bit. */
9567 if (type
== 'p' || type
== 'q')
9570 if ((val
& ((1 << op
->shift
) - 1)) != 0
9571 || val
< (mintiny
<< op
->shift
)
9572 || val
> (maxtiny
<< op
->shift
))
9577 if (warn
&& ext
&& ! needext
)
9578 as_warn_where (file
, line
,
9579 _("extended operand requested but not required"));
9580 if (small
&& needext
)
9581 as_bad_where (file
, line
, _("invalid unextended operand value"));
9583 if (small
|| (! ext
&& ! needext
))
9587 *use_extend
= FALSE
;
9588 insnval
= ((val
>> op
->shift
) & ((1 << op
->nbits
) - 1));
9589 insnval
<<= op
->op_shift
;
9594 long minext
, maxext
;
9600 maxext
= (1 << op
->extbits
) - 1;
9604 minext
= - (1 << (op
->extbits
- 1));
9605 maxext
= (1 << (op
->extbits
- 1)) - 1;
9607 if (val
< minext
|| val
> maxext
)
9608 as_bad_where (file
, line
,
9609 _("operand value out of range for instruction"));
9612 if (op
->extbits
== 16)
9614 extval
= ((val
>> 11) & 0x1f) | (val
& 0x7e0);
9617 else if (op
->extbits
== 15)
9619 extval
= ((val
>> 11) & 0xf) | (val
& 0x7f0);
9624 extval
= ((val
& 0x1f) << 6) | (val
& 0x20);
9628 *extend
= (unsigned short) extval
;
9633 struct percent_op_match
9636 bfd_reloc_code_real_type reloc
;
9639 static const struct percent_op_match mips_percent_op
[] =
9641 {"%lo", BFD_RELOC_LO16
},
9643 {"%call_hi", BFD_RELOC_MIPS_CALL_HI16
},
9644 {"%call_lo", BFD_RELOC_MIPS_CALL_LO16
},
9645 {"%call16", BFD_RELOC_MIPS_CALL16
},
9646 {"%got_disp", BFD_RELOC_MIPS_GOT_DISP
},
9647 {"%got_page", BFD_RELOC_MIPS_GOT_PAGE
},
9648 {"%got_ofst", BFD_RELOC_MIPS_GOT_OFST
},
9649 {"%got_hi", BFD_RELOC_MIPS_GOT_HI16
},
9650 {"%got_lo", BFD_RELOC_MIPS_GOT_LO16
},
9651 {"%got", BFD_RELOC_MIPS_GOT16
},
9652 {"%gp_rel", BFD_RELOC_GPREL16
},
9653 {"%half", BFD_RELOC_16
},
9654 {"%highest", BFD_RELOC_MIPS_HIGHEST
},
9655 {"%higher", BFD_RELOC_MIPS_HIGHER
},
9656 {"%neg", BFD_RELOC_MIPS_SUB
},
9657 {"%tlsgd", BFD_RELOC_MIPS_TLS_GD
},
9658 {"%tlsldm", BFD_RELOC_MIPS_TLS_LDM
},
9659 {"%dtprel_hi", BFD_RELOC_MIPS_TLS_DTPREL_HI16
},
9660 {"%dtprel_lo", BFD_RELOC_MIPS_TLS_DTPREL_LO16
},
9661 {"%tprel_hi", BFD_RELOC_MIPS_TLS_TPREL_HI16
},
9662 {"%tprel_lo", BFD_RELOC_MIPS_TLS_TPREL_LO16
},
9663 {"%gottprel", BFD_RELOC_MIPS_TLS_GOTTPREL
},
9665 {"%hi", BFD_RELOC_HI16_S
}
9668 static const struct percent_op_match mips16_percent_op
[] =
9670 {"%lo", BFD_RELOC_MIPS16_LO16
},
9671 {"%gprel", BFD_RELOC_MIPS16_GPREL
},
9672 {"%hi", BFD_RELOC_MIPS16_HI16_S
}
9676 /* Return true if *STR points to a relocation operator. When returning true,
9677 move *STR over the operator and store its relocation code in *RELOC.
9678 Leave both *STR and *RELOC alone when returning false. */
9681 parse_relocation (char **str
, bfd_reloc_code_real_type
*reloc
)
9683 const struct percent_op_match
*percent_op
;
9686 if (mips_opts
.mips16
)
9688 percent_op
= mips16_percent_op
;
9689 limit
= ARRAY_SIZE (mips16_percent_op
);
9693 percent_op
= mips_percent_op
;
9694 limit
= ARRAY_SIZE (mips_percent_op
);
9697 for (i
= 0; i
< limit
; i
++)
9698 if (strncasecmp (*str
, percent_op
[i
].str
, strlen (percent_op
[i
].str
)) == 0)
9700 int len
= strlen (percent_op
[i
].str
);
9702 if (!ISSPACE ((*str
)[len
]) && (*str
)[len
] != '(')
9705 *str
+= strlen (percent_op
[i
].str
);
9706 *reloc
= percent_op
[i
].reloc
;
9708 /* Check whether the output BFD supports this relocation.
9709 If not, issue an error and fall back on something safe. */
9710 if (!bfd_reloc_type_lookup (stdoutput
, percent_op
[i
].reloc
))
9712 as_bad ("relocation %s isn't supported by the current ABI",
9714 *reloc
= BFD_RELOC_UNUSED
;
9722 /* Parse string STR as a 16-bit relocatable operand. Store the
9723 expression in *EP and the relocations in the array starting
9724 at RELOC. Return the number of relocation operators used.
9726 On exit, EXPR_END points to the first character after the expression. */
9729 my_getSmallExpression (expressionS
*ep
, bfd_reloc_code_real_type
*reloc
,
9732 bfd_reloc_code_real_type reversed_reloc
[3];
9733 size_t reloc_index
, i
;
9734 int crux_depth
, str_depth
;
9737 /* Search for the start of the main expression, recoding relocations
9738 in REVERSED_RELOC. End the loop with CRUX pointing to the start
9739 of the main expression and with CRUX_DEPTH containing the number
9740 of open brackets at that point. */
9747 crux_depth
= str_depth
;
9749 /* Skip over whitespace and brackets, keeping count of the number
9751 while (*str
== ' ' || *str
== '\t' || *str
== '(')
9756 && reloc_index
< (HAVE_NEWABI
? 3 : 1)
9757 && parse_relocation (&str
, &reversed_reloc
[reloc_index
]));
9759 my_getExpression (ep
, crux
);
9762 /* Match every open bracket. */
9763 while (crux_depth
> 0 && (*str
== ')' || *str
== ' ' || *str
== '\t'))
9768 as_bad ("unclosed '('");
9772 if (reloc_index
!= 0)
9774 prev_reloc_op_frag
= frag_now
;
9775 for (i
= 0; i
< reloc_index
; i
++)
9776 reloc
[i
] = reversed_reloc
[reloc_index
- 1 - i
];
9783 my_getExpression (expressionS
*ep
, char *str
)
9788 save_in
= input_line_pointer
;
9789 input_line_pointer
= str
;
9791 expr_end
= input_line_pointer
;
9792 input_line_pointer
= save_in
;
9794 /* If we are in mips16 mode, and this is an expression based on `.',
9795 then we bump the value of the symbol by 1 since that is how other
9796 text symbols are handled. We don't bother to handle complex
9797 expressions, just `.' plus or minus a constant. */
9798 if (mips_opts
.mips16
9799 && ep
->X_op
== O_symbol
9800 && strcmp (S_GET_NAME (ep
->X_add_symbol
), FAKE_LABEL_NAME
) == 0
9801 && S_GET_SEGMENT (ep
->X_add_symbol
) == now_seg
9802 && symbol_get_frag (ep
->X_add_symbol
) == frag_now
9803 && symbol_constant_p (ep
->X_add_symbol
)
9804 && (val
= S_GET_VALUE (ep
->X_add_symbol
)) == frag_now_fix ())
9805 S_SET_VALUE (ep
->X_add_symbol
, val
+ 1);
9808 /* Turn a string in input_line_pointer into a floating point constant
9809 of type TYPE, and store the appropriate bytes in *LITP. The number
9810 of LITTLENUMS emitted is stored in *SIZEP. An error message is
9811 returned, or NULL on OK. */
9814 md_atof (int type
, char *litP
, int *sizeP
)
9817 LITTLENUM_TYPE words
[4];
9833 return _("bad call to md_atof");
9836 t
= atof_ieee (input_line_pointer
, type
, words
);
9838 input_line_pointer
= t
;
9842 if (! target_big_endian
)
9844 for (i
= prec
- 1; i
>= 0; i
--)
9846 md_number_to_chars (litP
, words
[i
], 2);
9852 for (i
= 0; i
< prec
; i
++)
9854 md_number_to_chars (litP
, words
[i
], 2);
9863 md_number_to_chars (char *buf
, valueT val
, int n
)
9865 if (target_big_endian
)
9866 number_to_chars_bigendian (buf
, val
, n
);
9868 number_to_chars_littleendian (buf
, val
, n
);
9872 static int support_64bit_objects(void)
9874 const char **list
, **l
;
9877 list
= bfd_target_list ();
9878 for (l
= list
; *l
!= NULL
; l
++)
9880 /* This is traditional mips */
9881 if (strcmp (*l
, "elf64-tradbigmips") == 0
9882 || strcmp (*l
, "elf64-tradlittlemips") == 0)
9884 if (strcmp (*l
, "elf64-bigmips") == 0
9885 || strcmp (*l
, "elf64-littlemips") == 0)
9892 #endif /* OBJ_ELF */
9894 const char *md_shortopts
= "O::g::G:";
9896 struct option md_longopts
[] =
9898 /* Options which specify architecture. */
9899 #define OPTION_ARCH_BASE (OPTION_MD_BASE)
9900 #define OPTION_MARCH (OPTION_ARCH_BASE + 0)
9901 {"march", required_argument
, NULL
, OPTION_MARCH
},
9902 #define OPTION_MTUNE (OPTION_ARCH_BASE + 1)
9903 {"mtune", required_argument
, NULL
, OPTION_MTUNE
},
9904 #define OPTION_MIPS1 (OPTION_ARCH_BASE + 2)
9905 {"mips0", no_argument
, NULL
, OPTION_MIPS1
},
9906 {"mips1", no_argument
, NULL
, OPTION_MIPS1
},
9907 #define OPTION_MIPS2 (OPTION_ARCH_BASE + 3)
9908 {"mips2", no_argument
, NULL
, OPTION_MIPS2
},
9909 #define OPTION_MIPS3 (OPTION_ARCH_BASE + 4)
9910 {"mips3", no_argument
, NULL
, OPTION_MIPS3
},
9911 #define OPTION_MIPS4 (OPTION_ARCH_BASE + 5)
9912 {"mips4", no_argument
, NULL
, OPTION_MIPS4
},
9913 #define OPTION_MIPS5 (OPTION_ARCH_BASE + 6)
9914 {"mips5", no_argument
, NULL
, OPTION_MIPS5
},
9915 #define OPTION_MIPS32 (OPTION_ARCH_BASE + 7)
9916 {"mips32", no_argument
, NULL
, OPTION_MIPS32
},
9917 #define OPTION_MIPS64 (OPTION_ARCH_BASE + 8)
9918 {"mips64", no_argument
, NULL
, OPTION_MIPS64
},
9919 #define OPTION_MIPS32R2 (OPTION_ARCH_BASE + 9)
9920 {"mips32r2", no_argument
, NULL
, OPTION_MIPS32R2
},
9921 #define OPTION_MIPS64R2 (OPTION_ARCH_BASE + 10)
9922 {"mips64r2", no_argument
, NULL
, OPTION_MIPS64R2
},
9924 /* Options which specify Application Specific Extensions (ASEs). */
9925 #define OPTION_ASE_BASE (OPTION_ARCH_BASE + 11)
9926 #define OPTION_MIPS16 (OPTION_ASE_BASE + 0)
9927 {"mips16", no_argument
, NULL
, OPTION_MIPS16
},
9928 #define OPTION_NO_MIPS16 (OPTION_ASE_BASE + 1)
9929 {"no-mips16", no_argument
, NULL
, OPTION_NO_MIPS16
},
9930 #define OPTION_MIPS3D (OPTION_ASE_BASE + 2)
9931 {"mips3d", no_argument
, NULL
, OPTION_MIPS3D
},
9932 #define OPTION_NO_MIPS3D (OPTION_ASE_BASE + 3)
9933 {"no-mips3d", no_argument
, NULL
, OPTION_NO_MIPS3D
},
9934 #define OPTION_MDMX (OPTION_ASE_BASE + 4)
9935 {"mdmx", no_argument
, NULL
, OPTION_MDMX
},
9936 #define OPTION_NO_MDMX (OPTION_ASE_BASE + 5)
9937 {"no-mdmx", no_argument
, NULL
, OPTION_NO_MDMX
},
9939 /* Old-style architecture options. Don't add more of these. */
9940 #define OPTION_COMPAT_ARCH_BASE (OPTION_ASE_BASE + 6)
9941 #define OPTION_M4650 (OPTION_COMPAT_ARCH_BASE + 0)
9942 {"m4650", no_argument
, NULL
, OPTION_M4650
},
9943 #define OPTION_NO_M4650 (OPTION_COMPAT_ARCH_BASE + 1)
9944 {"no-m4650", no_argument
, NULL
, OPTION_NO_M4650
},
9945 #define OPTION_M4010 (OPTION_COMPAT_ARCH_BASE + 2)
9946 {"m4010", no_argument
, NULL
, OPTION_M4010
},
9947 #define OPTION_NO_M4010 (OPTION_COMPAT_ARCH_BASE + 3)
9948 {"no-m4010", no_argument
, NULL
, OPTION_NO_M4010
},
9949 #define OPTION_M4100 (OPTION_COMPAT_ARCH_BASE + 4)
9950 {"m4100", no_argument
, NULL
, OPTION_M4100
},
9951 #define OPTION_NO_M4100 (OPTION_COMPAT_ARCH_BASE + 5)
9952 {"no-m4100", no_argument
, NULL
, OPTION_NO_M4100
},
9953 #define OPTION_M3900 (OPTION_COMPAT_ARCH_BASE + 6)
9954 {"m3900", no_argument
, NULL
, OPTION_M3900
},
9955 #define OPTION_NO_M3900 (OPTION_COMPAT_ARCH_BASE + 7)
9956 {"no-m3900", no_argument
, NULL
, OPTION_NO_M3900
},
9958 /* Options which enable bug fixes. */
9959 #define OPTION_FIX_BASE (OPTION_COMPAT_ARCH_BASE + 8)
9960 #define OPTION_M7000_HILO_FIX (OPTION_FIX_BASE + 0)
9961 {"mfix7000", no_argument
, NULL
, OPTION_M7000_HILO_FIX
},
9962 #define OPTION_MNO_7000_HILO_FIX (OPTION_FIX_BASE + 1)
9963 {"no-fix-7000", no_argument
, NULL
, OPTION_MNO_7000_HILO_FIX
},
9964 {"mno-fix7000", no_argument
, NULL
, OPTION_MNO_7000_HILO_FIX
},
9965 #define OPTION_FIX_VR4120 (OPTION_FIX_BASE + 2)
9966 #define OPTION_NO_FIX_VR4120 (OPTION_FIX_BASE + 3)
9967 {"mfix-vr4120", no_argument
, NULL
, OPTION_FIX_VR4120
},
9968 {"mno-fix-vr4120", no_argument
, NULL
, OPTION_NO_FIX_VR4120
},
9970 /* Miscellaneous options. */
9971 #define OPTION_MISC_BASE (OPTION_FIX_BASE + 4)
9972 #define OPTION_TRAP (OPTION_MISC_BASE + 0)
9973 {"trap", no_argument
, NULL
, OPTION_TRAP
},
9974 {"no-break", no_argument
, NULL
, OPTION_TRAP
},
9975 #define OPTION_BREAK (OPTION_MISC_BASE + 1)
9976 {"break", no_argument
, NULL
, OPTION_BREAK
},
9977 {"no-trap", no_argument
, NULL
, OPTION_BREAK
},
9978 #define OPTION_EB (OPTION_MISC_BASE + 2)
9979 {"EB", no_argument
, NULL
, OPTION_EB
},
9980 #define OPTION_EL (OPTION_MISC_BASE + 3)
9981 {"EL", no_argument
, NULL
, OPTION_EL
},
9982 #define OPTION_FP32 (OPTION_MISC_BASE + 4)
9983 {"mfp32", no_argument
, NULL
, OPTION_FP32
},
9984 #define OPTION_GP32 (OPTION_MISC_BASE + 5)
9985 {"mgp32", no_argument
, NULL
, OPTION_GP32
},
9986 #define OPTION_CONSTRUCT_FLOATS (OPTION_MISC_BASE + 6)
9987 {"construct-floats", no_argument
, NULL
, OPTION_CONSTRUCT_FLOATS
},
9988 #define OPTION_NO_CONSTRUCT_FLOATS (OPTION_MISC_BASE + 7)
9989 {"no-construct-floats", no_argument
, NULL
, OPTION_NO_CONSTRUCT_FLOATS
},
9990 #define OPTION_FP64 (OPTION_MISC_BASE + 8)
9991 {"mfp64", no_argument
, NULL
, OPTION_FP64
},
9992 #define OPTION_GP64 (OPTION_MISC_BASE + 9)
9993 {"mgp64", no_argument
, NULL
, OPTION_GP64
},
9994 #define OPTION_RELAX_BRANCH (OPTION_MISC_BASE + 10)
9995 #define OPTION_NO_RELAX_BRANCH (OPTION_MISC_BASE + 11)
9996 {"relax-branch", no_argument
, NULL
, OPTION_RELAX_BRANCH
},
9997 {"no-relax-branch", no_argument
, NULL
, OPTION_NO_RELAX_BRANCH
},
9998 #define OPTION_MSHARED (OPTION_MISC_BASE + 12)
9999 #define OPTION_MNO_SHARED (OPTION_MISC_BASE + 13)
10000 {"mshared", no_argument
, NULL
, OPTION_MSHARED
},
10001 {"mno-shared", no_argument
, NULL
, OPTION_MNO_SHARED
},
10002 #define OPTION_MSYM32 (OPTION_MISC_BASE + 14)
10003 #define OPTION_MNO_SYM32 (OPTION_MISC_BASE + 15)
10004 {"msym32", no_argument
, NULL
, OPTION_MSYM32
},
10005 {"mno-sym32", no_argument
, NULL
, OPTION_MNO_SYM32
},
10007 /* ELF-specific options. */
10009 #define OPTION_ELF_BASE (OPTION_MISC_BASE + 16)
10010 #define OPTION_CALL_SHARED (OPTION_ELF_BASE + 0)
10011 {"KPIC", no_argument
, NULL
, OPTION_CALL_SHARED
},
10012 {"call_shared", no_argument
, NULL
, OPTION_CALL_SHARED
},
10013 #define OPTION_NON_SHARED (OPTION_ELF_BASE + 1)
10014 {"non_shared", no_argument
, NULL
, OPTION_NON_SHARED
},
10015 #define OPTION_XGOT (OPTION_ELF_BASE + 2)
10016 {"xgot", no_argument
, NULL
, OPTION_XGOT
},
10017 #define OPTION_MABI (OPTION_ELF_BASE + 3)
10018 {"mabi", required_argument
, NULL
, OPTION_MABI
},
10019 #define OPTION_32 (OPTION_ELF_BASE + 4)
10020 {"32", no_argument
, NULL
, OPTION_32
},
10021 #define OPTION_N32 (OPTION_ELF_BASE + 5)
10022 {"n32", no_argument
, NULL
, OPTION_N32
},
10023 #define OPTION_64 (OPTION_ELF_BASE + 6)
10024 {"64", no_argument
, NULL
, OPTION_64
},
10025 #define OPTION_MDEBUG (OPTION_ELF_BASE + 7)
10026 {"mdebug", no_argument
, NULL
, OPTION_MDEBUG
},
10027 #define OPTION_NO_MDEBUG (OPTION_ELF_BASE + 8)
10028 {"no-mdebug", no_argument
, NULL
, OPTION_NO_MDEBUG
},
10029 #define OPTION_PDR (OPTION_ELF_BASE + 9)
10030 {"mpdr", no_argument
, NULL
, OPTION_PDR
},
10031 #define OPTION_NO_PDR (OPTION_ELF_BASE + 10)
10032 {"mno-pdr", no_argument
, NULL
, OPTION_NO_PDR
},
10033 #endif /* OBJ_ELF */
10035 {NULL
, no_argument
, NULL
, 0}
10037 size_t md_longopts_size
= sizeof (md_longopts
);
10039 /* Set STRING_PTR (either &mips_arch_string or &mips_tune_string) to
10040 NEW_VALUE. Warn if another value was already specified. Note:
10041 we have to defer parsing the -march and -mtune arguments in order
10042 to handle 'from-abi' correctly, since the ABI might be specified
10043 in a later argument. */
10046 mips_set_option_string (const char **string_ptr
, const char *new_value
)
10048 if (*string_ptr
!= 0 && strcasecmp (*string_ptr
, new_value
) != 0)
10049 as_warn (_("A different %s was already specified, is now %s"),
10050 string_ptr
== &mips_arch_string
? "-march" : "-mtune",
10053 *string_ptr
= new_value
;
10057 md_parse_option (int c
, char *arg
)
10061 case OPTION_CONSTRUCT_FLOATS
:
10062 mips_disable_float_construction
= 0;
10065 case OPTION_NO_CONSTRUCT_FLOATS
:
10066 mips_disable_float_construction
= 1;
10078 target_big_endian
= 1;
10082 target_big_endian
= 0;
10086 if (arg
&& arg
[1] == '0')
10096 mips_debug
= atoi (arg
);
10097 /* When the MIPS assembler sees -g or -g2, it does not do
10098 optimizations which limit full symbolic debugging. We take
10099 that to be equivalent to -O0. */
10100 if (mips_debug
== 2)
10105 file_mips_isa
= ISA_MIPS1
;
10109 file_mips_isa
= ISA_MIPS2
;
10113 file_mips_isa
= ISA_MIPS3
;
10117 file_mips_isa
= ISA_MIPS4
;
10121 file_mips_isa
= ISA_MIPS5
;
10124 case OPTION_MIPS32
:
10125 file_mips_isa
= ISA_MIPS32
;
10128 case OPTION_MIPS32R2
:
10129 file_mips_isa
= ISA_MIPS32R2
;
10132 case OPTION_MIPS64R2
:
10133 file_mips_isa
= ISA_MIPS64R2
;
10136 case OPTION_MIPS64
:
10137 file_mips_isa
= ISA_MIPS64
;
10141 mips_set_option_string (&mips_tune_string
, arg
);
10145 mips_set_option_string (&mips_arch_string
, arg
);
10149 mips_set_option_string (&mips_arch_string
, "4650");
10150 mips_set_option_string (&mips_tune_string
, "4650");
10153 case OPTION_NO_M4650
:
10157 mips_set_option_string (&mips_arch_string
, "4010");
10158 mips_set_option_string (&mips_tune_string
, "4010");
10161 case OPTION_NO_M4010
:
10165 mips_set_option_string (&mips_arch_string
, "4100");
10166 mips_set_option_string (&mips_tune_string
, "4100");
10169 case OPTION_NO_M4100
:
10173 mips_set_option_string (&mips_arch_string
, "3900");
10174 mips_set_option_string (&mips_tune_string
, "3900");
10177 case OPTION_NO_M3900
:
10181 mips_opts
.ase_mdmx
= 1;
10184 case OPTION_NO_MDMX
:
10185 mips_opts
.ase_mdmx
= 0;
10188 case OPTION_MIPS16
:
10189 mips_opts
.mips16
= 1;
10190 mips_no_prev_insn ();
10193 case OPTION_NO_MIPS16
:
10194 mips_opts
.mips16
= 0;
10195 mips_no_prev_insn ();
10198 case OPTION_MIPS3D
:
10199 mips_opts
.ase_mips3d
= 1;
10202 case OPTION_NO_MIPS3D
:
10203 mips_opts
.ase_mips3d
= 0;
10206 case OPTION_FIX_VR4120
:
10207 mips_fix_vr4120
= 1;
10210 case OPTION_NO_FIX_VR4120
:
10211 mips_fix_vr4120
= 0;
10214 case OPTION_RELAX_BRANCH
:
10215 mips_relax_branch
= 1;
10218 case OPTION_NO_RELAX_BRANCH
:
10219 mips_relax_branch
= 0;
10222 case OPTION_MSHARED
:
10223 mips_in_shared
= TRUE
;
10226 case OPTION_MNO_SHARED
:
10227 mips_in_shared
= FALSE
;
10230 case OPTION_MSYM32
:
10231 mips_opts
.sym32
= TRUE
;
10234 case OPTION_MNO_SYM32
:
10235 mips_opts
.sym32
= FALSE
;
10239 /* When generating ELF code, we permit -KPIC and -call_shared to
10240 select SVR4_PIC, and -non_shared to select no PIC. This is
10241 intended to be compatible with Irix 5. */
10242 case OPTION_CALL_SHARED
:
10243 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
10245 as_bad (_("-call_shared is supported only for ELF format"));
10248 mips_pic
= SVR4_PIC
;
10249 mips_abicalls
= TRUE
;
10250 if (g_switch_seen
&& g_switch_value
!= 0)
10252 as_bad (_("-G may not be used with SVR4 PIC code"));
10255 g_switch_value
= 0;
10258 case OPTION_NON_SHARED
:
10259 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
10261 as_bad (_("-non_shared is supported only for ELF format"));
10265 mips_abicalls
= FALSE
;
10268 /* The -xgot option tells the assembler to use 32 offsets when
10269 accessing the got in SVR4_PIC mode. It is for Irix
10274 #endif /* OBJ_ELF */
10277 g_switch_value
= atoi (arg
);
10279 if (mips_pic
== SVR4_PIC
&& g_switch_value
!= 0)
10281 as_bad (_("-G may not be used with SVR4 PIC code"));
10287 /* The -32, -n32 and -64 options are shortcuts for -mabi=32, -mabi=n32
10290 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
10292 as_bad (_("-32 is supported for ELF format only"));
10295 mips_abi
= O32_ABI
;
10299 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
10301 as_bad (_("-n32 is supported for ELF format only"));
10304 mips_abi
= N32_ABI
;
10308 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
10310 as_bad (_("-64 is supported for ELF format only"));
10313 mips_abi
= N64_ABI
;
10314 if (! support_64bit_objects())
10315 as_fatal (_("No compiled in support for 64 bit object file format"));
10317 #endif /* OBJ_ELF */
10320 file_mips_gp32
= 1;
10324 file_mips_gp32
= 0;
10328 file_mips_fp32
= 1;
10332 file_mips_fp32
= 0;
10337 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
10339 as_bad (_("-mabi is supported for ELF format only"));
10342 if (strcmp (arg
, "32") == 0)
10343 mips_abi
= O32_ABI
;
10344 else if (strcmp (arg
, "o64") == 0)
10345 mips_abi
= O64_ABI
;
10346 else if (strcmp (arg
, "n32") == 0)
10347 mips_abi
= N32_ABI
;
10348 else if (strcmp (arg
, "64") == 0)
10350 mips_abi
= N64_ABI
;
10351 if (! support_64bit_objects())
10352 as_fatal (_("No compiled in support for 64 bit object file "
10355 else if (strcmp (arg
, "eabi") == 0)
10356 mips_abi
= EABI_ABI
;
10359 as_fatal (_("invalid abi -mabi=%s"), arg
);
10363 #endif /* OBJ_ELF */
10365 case OPTION_M7000_HILO_FIX
:
10366 mips_7000_hilo_fix
= TRUE
;
10369 case OPTION_MNO_7000_HILO_FIX
:
10370 mips_7000_hilo_fix
= FALSE
;
10374 case OPTION_MDEBUG
:
10375 mips_flag_mdebug
= TRUE
;
10378 case OPTION_NO_MDEBUG
:
10379 mips_flag_mdebug
= FALSE
;
10383 mips_flag_pdr
= TRUE
;
10386 case OPTION_NO_PDR
:
10387 mips_flag_pdr
= FALSE
;
10389 #endif /* OBJ_ELF */
10398 /* Set up globals to generate code for the ISA or processor
10399 described by INFO. */
10402 mips_set_architecture (const struct mips_cpu_info
*info
)
10406 file_mips_arch
= info
->cpu
;
10407 mips_opts
.arch
= info
->cpu
;
10408 mips_opts
.isa
= info
->isa
;
10413 /* Likewise for tuning. */
10416 mips_set_tune (const struct mips_cpu_info
*info
)
10419 mips_tune
= info
->cpu
;
10424 mips_after_parse_args (void)
10426 const struct mips_cpu_info
*arch_info
= 0;
10427 const struct mips_cpu_info
*tune_info
= 0;
10429 /* GP relative stuff not working for PE */
10430 if (strncmp (TARGET_OS
, "pe", 2) == 0)
10432 if (g_switch_seen
&& g_switch_value
!= 0)
10433 as_bad (_("-G not supported in this configuration."));
10434 g_switch_value
= 0;
10437 if (mips_abi
== NO_ABI
)
10438 mips_abi
= MIPS_DEFAULT_ABI
;
10440 /* The following code determines the architecture and register size.
10441 Similar code was added to GCC 3.3 (see override_options() in
10442 config/mips/mips.c). The GAS and GCC code should be kept in sync
10443 as much as possible. */
10445 if (mips_arch_string
!= 0)
10446 arch_info
= mips_parse_cpu ("-march", mips_arch_string
);
10448 if (file_mips_isa
!= ISA_UNKNOWN
)
10450 /* Handle -mipsN. At this point, file_mips_isa contains the
10451 ISA level specified by -mipsN, while arch_info->isa contains
10452 the -march selection (if any). */
10453 if (arch_info
!= 0)
10455 /* -march takes precedence over -mipsN, since it is more descriptive.
10456 There's no harm in specifying both as long as the ISA levels
10458 if (file_mips_isa
!= arch_info
->isa
)
10459 as_bad (_("-%s conflicts with the other architecture options, which imply -%s"),
10460 mips_cpu_info_from_isa (file_mips_isa
)->name
,
10461 mips_cpu_info_from_isa (arch_info
->isa
)->name
);
10464 arch_info
= mips_cpu_info_from_isa (file_mips_isa
);
10467 if (arch_info
== 0)
10468 arch_info
= mips_parse_cpu ("default CPU", MIPS_CPU_STRING_DEFAULT
);
10470 if (ABI_NEEDS_64BIT_REGS (mips_abi
) && !ISA_HAS_64BIT_REGS (arch_info
->isa
))
10471 as_bad ("-march=%s is not compatible with the selected ABI",
10474 mips_set_architecture (arch_info
);
10476 /* Optimize for file_mips_arch, unless -mtune selects a different processor. */
10477 if (mips_tune_string
!= 0)
10478 tune_info
= mips_parse_cpu ("-mtune", mips_tune_string
);
10480 if (tune_info
== 0)
10481 mips_set_tune (arch_info
);
10483 mips_set_tune (tune_info
);
10485 if (file_mips_gp32
>= 0)
10487 /* The user specified the size of the integer registers. Make sure
10488 it agrees with the ABI and ISA. */
10489 if (file_mips_gp32
== 0 && !ISA_HAS_64BIT_REGS (mips_opts
.isa
))
10490 as_bad (_("-mgp64 used with a 32-bit processor"));
10491 else if (file_mips_gp32
== 1 && ABI_NEEDS_64BIT_REGS (mips_abi
))
10492 as_bad (_("-mgp32 used with a 64-bit ABI"));
10493 else if (file_mips_gp32
== 0 && ABI_NEEDS_32BIT_REGS (mips_abi
))
10494 as_bad (_("-mgp64 used with a 32-bit ABI"));
10498 /* Infer the integer register size from the ABI and processor.
10499 Restrict ourselves to 32-bit registers if that's all the
10500 processor has, or if the ABI cannot handle 64-bit registers. */
10501 file_mips_gp32
= (ABI_NEEDS_32BIT_REGS (mips_abi
)
10502 || !ISA_HAS_64BIT_REGS (mips_opts
.isa
));
10505 /* ??? GAS treats single-float processors as though they had 64-bit
10506 float registers (although it complains when double-precision
10507 instructions are used). As things stand, saying they have 32-bit
10508 registers would lead to spurious "register must be even" messages.
10509 So here we assume float registers are always the same size as
10510 integer ones, unless the user says otherwise. */
10511 if (file_mips_fp32
< 0)
10512 file_mips_fp32
= file_mips_gp32
;
10514 /* End of GCC-shared inference code. */
10516 /* This flag is set when we have a 64-bit capable CPU but use only
10517 32-bit wide registers. Note that EABI does not use it. */
10518 if (ISA_HAS_64BIT_REGS (mips_opts
.isa
)
10519 && ((mips_abi
== NO_ABI
&& file_mips_gp32
== 1)
10520 || mips_abi
== O32_ABI
))
10521 mips_32bitmode
= 1;
10523 if (mips_opts
.isa
== ISA_MIPS1
&& mips_trap
)
10524 as_bad (_("trap exception not supported at ISA 1"));
10526 /* If the selected architecture includes support for ASEs, enable
10527 generation of code for them. */
10528 if (mips_opts
.mips16
== -1)
10529 mips_opts
.mips16
= (CPU_HAS_MIPS16 (file_mips_arch
)) ? 1 : 0;
10530 if (mips_opts
.ase_mips3d
== -1)
10531 mips_opts
.ase_mips3d
= (CPU_HAS_MIPS3D (file_mips_arch
)) ? 1 : 0;
10532 if (mips_opts
.ase_mdmx
== -1)
10533 mips_opts
.ase_mdmx
= (CPU_HAS_MDMX (file_mips_arch
)) ? 1 : 0;
10535 file_mips_isa
= mips_opts
.isa
;
10536 file_ase_mips16
= mips_opts
.mips16
;
10537 file_ase_mips3d
= mips_opts
.ase_mips3d
;
10538 file_ase_mdmx
= mips_opts
.ase_mdmx
;
10539 mips_opts
.gp32
= file_mips_gp32
;
10540 mips_opts
.fp32
= file_mips_fp32
;
10542 if (mips_flag_mdebug
< 0)
10544 #ifdef OBJ_MAYBE_ECOFF
10545 if (OUTPUT_FLAVOR
== bfd_target_ecoff_flavour
)
10546 mips_flag_mdebug
= 1;
10548 #endif /* OBJ_MAYBE_ECOFF */
10549 mips_flag_mdebug
= 0;
10554 mips_init_after_args (void)
10556 /* initialize opcodes */
10557 bfd_mips_num_opcodes
= bfd_mips_num_builtin_opcodes
;
10558 mips_opcodes
= (struct mips_opcode
*) mips_builtin_opcodes
;
10562 md_pcrel_from (fixS
*fixP
)
10564 valueT addr
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
10565 switch (fixP
->fx_r_type
)
10567 case BFD_RELOC_16_PCREL_S2
:
10568 case BFD_RELOC_MIPS_JMP
:
10569 /* Return the address of the delay slot. */
10576 /* This is called before the symbol table is processed. In order to
10577 work with gcc when using mips-tfile, we must keep all local labels.
10578 However, in other cases, we want to discard them. If we were
10579 called with -g, but we didn't see any debugging information, it may
10580 mean that gcc is smuggling debugging information through to
10581 mips-tfile, in which case we must generate all local labels. */
10584 mips_frob_file_before_adjust (void)
10586 #ifndef NO_ECOFF_DEBUGGING
10587 if (ECOFF_DEBUGGING
10589 && ! ecoff_debugging_seen
)
10590 flag_keep_locals
= 1;
10594 /* Sort any unmatched HI16 and GOT16 relocs so that they immediately precede
10595 the corresponding LO16 reloc. This is called before md_apply_fix3 and
10596 tc_gen_reloc. Unmatched relocs can only be generated by use of explicit
10597 relocation operators.
10599 For our purposes, a %lo() expression matches a %got() or %hi()
10602 (a) it refers to the same symbol; and
10603 (b) the offset applied in the %lo() expression is no lower than
10604 the offset applied in the %got() or %hi().
10606 (b) allows us to cope with code like:
10609 lh $4,%lo(foo+2)($4)
10611 ...which is legal on RELA targets, and has a well-defined behaviour
10612 if the user knows that adding 2 to "foo" will not induce a carry to
10615 When several %lo()s match a particular %got() or %hi(), we use the
10616 following rules to distinguish them:
10618 (1) %lo()s with smaller offsets are a better match than %lo()s with
10621 (2) %lo()s with no matching %got() or %hi() are better than those
10622 that already have a matching %got() or %hi().
10624 (3) later %lo()s are better than earlier %lo()s.
10626 These rules are applied in order.
10628 (1) means, among other things, that %lo()s with identical offsets are
10629 chosen if they exist.
10631 (2) means that we won't associate several high-part relocations with
10632 the same low-part relocation unless there's no alternative. Having
10633 several high parts for the same low part is a GNU extension; this rule
10634 allows careful users to avoid it.
10636 (3) is purely cosmetic. mips_hi_fixup_list is is in reverse order,
10637 with the last high-part relocation being at the front of the list.
10638 It therefore makes sense to choose the last matching low-part
10639 relocation, all other things being equal. It's also easier
10640 to code that way. */
10643 mips_frob_file (void)
10645 struct mips_hi_fixup
*l
;
10647 for (l
= mips_hi_fixup_list
; l
!= NULL
; l
= l
->next
)
10649 segment_info_type
*seginfo
;
10650 bfd_boolean matched_lo_p
;
10651 fixS
**hi_pos
, **lo_pos
, **pos
;
10653 assert (reloc_needs_lo_p (l
->fixp
->fx_r_type
));
10655 /* If a GOT16 relocation turns out to be against a global symbol,
10656 there isn't supposed to be a matching LO. */
10657 if (l
->fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT16
10658 && !pic_need_relax (l
->fixp
->fx_addsy
, l
->seg
))
10661 /* Check quickly whether the next fixup happens to be a matching %lo. */
10662 if (fixup_has_matching_lo_p (l
->fixp
))
10665 seginfo
= seg_info (l
->seg
);
10667 /* Set HI_POS to the position of this relocation in the chain.
10668 Set LO_POS to the position of the chosen low-part relocation.
10669 MATCHED_LO_P is true on entry to the loop if *POS is a low-part
10670 relocation that matches an immediately-preceding high-part
10674 matched_lo_p
= FALSE
;
10675 for (pos
= &seginfo
->fix_root
; *pos
!= NULL
; pos
= &(*pos
)->fx_next
)
10677 if (*pos
== l
->fixp
)
10680 if ((*pos
)->fx_r_type
== BFD_RELOC_LO16
10681 && (*pos
)->fx_addsy
== l
->fixp
->fx_addsy
10682 && (*pos
)->fx_offset
>= l
->fixp
->fx_offset
10684 || (*pos
)->fx_offset
< (*lo_pos
)->fx_offset
10686 && (*pos
)->fx_offset
== (*lo_pos
)->fx_offset
)))
10689 matched_lo_p
= (reloc_needs_lo_p ((*pos
)->fx_r_type
)
10690 && fixup_has_matching_lo_p (*pos
));
10693 /* If we found a match, remove the high-part relocation from its
10694 current position and insert it before the low-part relocation.
10695 Make the offsets match so that fixup_has_matching_lo_p()
10698 We don't warn about unmatched high-part relocations since some
10699 versions of gcc have been known to emit dead "lui ...%hi(...)"
10701 if (lo_pos
!= NULL
)
10703 l
->fixp
->fx_offset
= (*lo_pos
)->fx_offset
;
10704 if (l
->fixp
->fx_next
!= *lo_pos
)
10706 *hi_pos
= l
->fixp
->fx_next
;
10707 l
->fixp
->fx_next
= *lo_pos
;
10714 /* We may have combined relocations without symbols in the N32/N64 ABI.
10715 We have to prevent gas from dropping them. */
10718 mips_force_relocation (fixS
*fixp
)
10720 if (generic_force_reloc (fixp
))
10724 && S_GET_SEGMENT (fixp
->fx_addsy
) == bfd_abs_section_ptr
10725 && (fixp
->fx_r_type
== BFD_RELOC_MIPS_SUB
10726 || fixp
->fx_r_type
== BFD_RELOC_HI16_S
10727 || fixp
->fx_r_type
== BFD_RELOC_LO16
))
10733 /* This hook is called before a fix is simplified. We don't really
10734 decide whether to skip a fix here. Rather, we turn global symbols
10735 used as branch targets into local symbols, such that they undergo
10736 simplification. We can only do this if the symbol is defined and
10737 it is in the same section as the branch. If this doesn't hold, we
10738 emit a better error message than just saying the relocation is not
10739 valid for the selected object format.
10741 FIXP is the fix-up we're going to try to simplify, SEG is the
10742 segment in which the fix up occurs. The return value should be
10743 non-zero to indicate the fix-up is valid for further
10744 simplifications. */
10747 mips_validate_fix (struct fix
*fixP
, asection
*seg
)
10749 /* There's a lot of discussion on whether it should be possible to
10750 use R_MIPS_PC16 to represent branch relocations. The outcome
10751 seems to be that it can, but gas/bfd are very broken in creating
10752 RELA relocations for this, so for now we only accept branches to
10753 symbols in the same section. Anything else is of dubious value,
10754 since there's no guarantee that at link time the symbol would be
10755 in range. Even for branches to local symbols this is arguably
10756 wrong, since it we assume the symbol is not going to be
10757 overridden, which should be possible per ELF library semantics,
10758 but then, there isn't a dynamic relocation that could be used to
10759 this effect, and the target would likely be out of range as well.
10761 Unfortunately, it seems that there is too much code out there
10762 that relies on branches to symbols that are global to be resolved
10763 as if they were local, like the IRIX tools do, so we do it as
10764 well, but with a warning so that people are reminded to fix their
10765 code. If we ever get back to using R_MIPS_PC16 for branch
10766 targets, this entire block should go away (and probably the
10767 whole function). */
10769 if (fixP
->fx_r_type
== BFD_RELOC_16_PCREL_S2
10770 && ((OUTPUT_FLAVOR
== bfd_target_ecoff_flavour
10771 || OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
10772 || bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_16_PCREL_S2
) == NULL
)
10775 if (! S_IS_DEFINED (fixP
->fx_addsy
))
10777 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
10778 _("Cannot branch to undefined symbol."));
10779 /* Avoid any further errors about this fixup. */
10782 else if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
10784 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
10785 _("Cannot branch to symbol in another section."));
10788 else if (S_IS_EXTERNAL (fixP
->fx_addsy
))
10790 symbolS
*sym
= fixP
->fx_addsy
;
10792 if (mips_pic
== SVR4_PIC
)
10793 as_warn_where (fixP
->fx_file
, fixP
->fx_line
,
10794 _("Pretending global symbol used as branch target is local."));
10796 fixP
->fx_addsy
= symbol_create (S_GET_NAME (sym
),
10797 S_GET_SEGMENT (sym
),
10799 symbol_get_frag (sym
));
10800 copy_symbol_attributes (fixP
->fx_addsy
, sym
);
10801 S_CLEAR_EXTERNAL (fixP
->fx_addsy
);
10802 assert (symbol_resolved_p (sym
));
10803 symbol_mark_resolved (fixP
->fx_addsy
);
10810 /* Apply a fixup to the object file. */
10813 md_apply_fix3 (fixS
*fixP
, valueT
*valP
, segT seg ATTRIBUTE_UNUSED
)
10817 reloc_howto_type
*howto
;
10819 /* We ignore generic BFD relocations we don't know about. */
10820 howto
= bfd_reloc_type_lookup (stdoutput
, fixP
->fx_r_type
);
10824 assert (fixP
->fx_size
== 4
10825 || fixP
->fx_r_type
== BFD_RELOC_16
10826 || fixP
->fx_r_type
== BFD_RELOC_64
10827 || fixP
->fx_r_type
== BFD_RELOC_CTOR
10828 || fixP
->fx_r_type
== BFD_RELOC_MIPS_SUB
10829 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
10830 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
);
10832 buf
= (bfd_byte
*) (fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
);
10834 assert (! fixP
->fx_pcrel
);
10836 /* Don't treat parts of a composite relocation as done. There are two
10839 (1) The second and third parts will be against 0 (RSS_UNDEF) but
10840 should nevertheless be emitted if the first part is.
10842 (2) In normal usage, composite relocations are never assembly-time
10843 constants. The easiest way of dealing with the pathological
10844 exceptions is to generate a relocation against STN_UNDEF and
10845 leave everything up to the linker. */
10846 if (fixP
->fx_addsy
== NULL
&& fixP
->fx_tcbit
== 0)
10849 switch (fixP
->fx_r_type
)
10851 case BFD_RELOC_MIPS_TLS_GD
:
10852 case BFD_RELOC_MIPS_TLS_LDM
:
10853 case BFD_RELOC_MIPS_TLS_DTPREL_HI16
:
10854 case BFD_RELOC_MIPS_TLS_DTPREL_LO16
:
10855 case BFD_RELOC_MIPS_TLS_GOTTPREL
:
10856 case BFD_RELOC_MIPS_TLS_TPREL_HI16
:
10857 case BFD_RELOC_MIPS_TLS_TPREL_LO16
:
10858 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
10861 case BFD_RELOC_MIPS_JMP
:
10862 case BFD_RELOC_MIPS_SHIFT5
:
10863 case BFD_RELOC_MIPS_SHIFT6
:
10864 case BFD_RELOC_MIPS_GOT_DISP
:
10865 case BFD_RELOC_MIPS_GOT_PAGE
:
10866 case BFD_RELOC_MIPS_GOT_OFST
:
10867 case BFD_RELOC_MIPS_SUB
:
10868 case BFD_RELOC_MIPS_INSERT_A
:
10869 case BFD_RELOC_MIPS_INSERT_B
:
10870 case BFD_RELOC_MIPS_DELETE
:
10871 case BFD_RELOC_MIPS_HIGHEST
:
10872 case BFD_RELOC_MIPS_HIGHER
:
10873 case BFD_RELOC_MIPS_SCN_DISP
:
10874 case BFD_RELOC_MIPS_REL16
:
10875 case BFD_RELOC_MIPS_RELGOT
:
10876 case BFD_RELOC_MIPS_JALR
:
10877 case BFD_RELOC_HI16
:
10878 case BFD_RELOC_HI16_S
:
10879 case BFD_RELOC_GPREL16
:
10880 case BFD_RELOC_MIPS_LITERAL
:
10881 case BFD_RELOC_MIPS_CALL16
:
10882 case BFD_RELOC_MIPS_GOT16
:
10883 case BFD_RELOC_GPREL32
:
10884 case BFD_RELOC_MIPS_GOT_HI16
:
10885 case BFD_RELOC_MIPS_GOT_LO16
:
10886 case BFD_RELOC_MIPS_CALL_HI16
:
10887 case BFD_RELOC_MIPS_CALL_LO16
:
10888 case BFD_RELOC_MIPS16_GPREL
:
10889 case BFD_RELOC_MIPS16_HI16
:
10890 case BFD_RELOC_MIPS16_HI16_S
:
10891 assert (! fixP
->fx_pcrel
);
10892 /* Nothing needed to do. The value comes from the reloc entry */
10895 case BFD_RELOC_MIPS16_JMP
:
10896 /* We currently always generate a reloc against a symbol, which
10897 means that we don't want an addend even if the symbol is
10903 /* This is handled like BFD_RELOC_32, but we output a sign
10904 extended value if we are only 32 bits. */
10907 if (8 <= sizeof (valueT
))
10908 md_number_to_chars ((char *) buf
, *valP
, 8);
10913 if ((*valP
& 0x80000000) != 0)
10917 md_number_to_chars ((char *)(buf
+ target_big_endian
? 4 : 0),
10919 md_number_to_chars ((char *)(buf
+ target_big_endian
? 0 : 4),
10925 case BFD_RELOC_RVA
:
10927 /* If we are deleting this reloc entry, we must fill in the
10928 value now. This can happen if we have a .word which is not
10929 resolved when it appears but is later defined. */
10931 md_number_to_chars ((char *) buf
, *valP
, 4);
10935 /* If we are deleting this reloc entry, we must fill in the
10938 md_number_to_chars ((char *) buf
, *valP
, 2);
10941 case BFD_RELOC_LO16
:
10942 case BFD_RELOC_MIPS16_LO16
:
10943 /* FIXME: Now that embedded-PIC is gone, some of this code/comment
10944 may be safe to remove, but if so it's not obvious. */
10945 /* When handling an embedded PIC switch statement, we can wind
10946 up deleting a LO16 reloc. See the 'o' case in mips_ip. */
10949 if (*valP
+ 0x8000 > 0xffff)
10950 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
10951 _("relocation overflow"));
10952 if (target_big_endian
)
10954 md_number_to_chars ((char *) buf
, *valP
, 2);
10958 case BFD_RELOC_16_PCREL_S2
:
10959 if ((*valP
& 0x3) != 0)
10960 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
10961 _("Branch to odd address (%lx)"), (long) *valP
);
10964 * We need to save the bits in the instruction since fixup_segment()
10965 * might be deleting the relocation entry (i.e., a branch within
10966 * the current segment).
10968 if (! fixP
->fx_done
)
10971 /* update old instruction data */
10972 if (target_big_endian
)
10973 insn
= (buf
[0] << 24) | (buf
[1] << 16) | (buf
[2] << 8) | buf
[3];
10975 insn
= (buf
[3] << 24) | (buf
[2] << 16) | (buf
[1] << 8) | buf
[0];
10977 if (*valP
+ 0x20000 <= 0x3ffff)
10979 insn
|= (*valP
>> 2) & 0xffff;
10980 md_number_to_chars ((char *) buf
, insn
, 4);
10982 else if (mips_pic
== NO_PIC
10984 && fixP
->fx_frag
->fr_address
>= text_section
->vma
10985 && (fixP
->fx_frag
->fr_address
10986 < text_section
->vma
+ bfd_get_section_size (text_section
))
10987 && ((insn
& 0xffff0000) == 0x10000000 /* beq $0,$0 */
10988 || (insn
& 0xffff0000) == 0x04010000 /* bgez $0 */
10989 || (insn
& 0xffff0000) == 0x04110000)) /* bgezal $0 */
10991 /* The branch offset is too large. If this is an
10992 unconditional branch, and we are not generating PIC code,
10993 we can convert it to an absolute jump instruction. */
10994 if ((insn
& 0xffff0000) == 0x04110000) /* bgezal $0 */
10995 insn
= 0x0c000000; /* jal */
10997 insn
= 0x08000000; /* j */
10998 fixP
->fx_r_type
= BFD_RELOC_MIPS_JMP
;
11000 fixP
->fx_addsy
= section_symbol (text_section
);
11001 *valP
+= md_pcrel_from (fixP
);
11002 md_number_to_chars ((char *) buf
, insn
, 4);
11006 /* If we got here, we have branch-relaxation disabled,
11007 and there's nothing we can do to fix this instruction
11008 without turning it into a longer sequence. */
11009 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
11010 _("Branch out of range"));
11014 case BFD_RELOC_VTABLE_INHERIT
:
11017 && !S_IS_DEFINED (fixP
->fx_addsy
)
11018 && !S_IS_WEAK (fixP
->fx_addsy
))
11019 S_SET_WEAK (fixP
->fx_addsy
);
11022 case BFD_RELOC_VTABLE_ENTRY
:
11030 /* Remember value for tc_gen_reloc. */
11031 fixP
->fx_addnumber
= *valP
;
11041 name
= input_line_pointer
;
11042 c
= get_symbol_end ();
11043 p
= (symbolS
*) symbol_find_or_make (name
);
11044 *input_line_pointer
= c
;
11048 /* Align the current frag to a given power of two. The MIPS assembler
11049 also automatically adjusts any preceding label. */
11052 mips_align (int to
, int fill
, symbolS
*label
)
11054 mips_emit_delays ();
11055 frag_align (to
, fill
, 0);
11056 record_alignment (now_seg
, to
);
11059 assert (S_GET_SEGMENT (label
) == now_seg
);
11060 symbol_set_frag (label
, frag_now
);
11061 S_SET_VALUE (label
, (valueT
) frag_now_fix ());
11065 /* Align to a given power of two. .align 0 turns off the automatic
11066 alignment used by the data creating pseudo-ops. */
11069 s_align (int x ATTRIBUTE_UNUSED
)
11072 register long temp_fill
;
11073 long max_alignment
= 15;
11077 o Note that the assembler pulls down any immediately preceding label
11078 to the aligned address.
11079 o It's not documented but auto alignment is reinstated by
11080 a .align pseudo instruction.
11081 o Note also that after auto alignment is turned off the mips assembler
11082 issues an error on attempt to assemble an improperly aligned data item.
11087 temp
= get_absolute_expression ();
11088 if (temp
> max_alignment
)
11089 as_bad (_("Alignment too large: %d. assumed."), temp
= max_alignment
);
11092 as_warn (_("Alignment negative: 0 assumed."));
11095 if (*input_line_pointer
== ',')
11097 ++input_line_pointer
;
11098 temp_fill
= get_absolute_expression ();
11105 mips_align (temp
, (int) temp_fill
,
11106 insn_labels
!= NULL
? insn_labels
->label
: NULL
);
11113 demand_empty_rest_of_line ();
11117 s_change_sec (int sec
)
11122 /* The ELF backend needs to know that we are changing sections, so
11123 that .previous works correctly. We could do something like check
11124 for an obj_section_change_hook macro, but that might be confusing
11125 as it would not be appropriate to use it in the section changing
11126 functions in read.c, since obj-elf.c intercepts those. FIXME:
11127 This should be cleaner, somehow. */
11128 obj_elf_section_change_hook ();
11131 mips_emit_delays ();
11141 subseg_set (bss_section
, (subsegT
) get_absolute_expression ());
11142 demand_empty_rest_of_line ();
11146 seg
= subseg_new (RDATA_SECTION_NAME
,
11147 (subsegT
) get_absolute_expression ());
11148 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
11150 bfd_set_section_flags (stdoutput
, seg
, (SEC_ALLOC
| SEC_LOAD
11151 | SEC_READONLY
| SEC_RELOC
11153 if (strcmp (TARGET_OS
, "elf") != 0)
11154 record_alignment (seg
, 4);
11156 demand_empty_rest_of_line ();
11160 seg
= subseg_new (".sdata", (subsegT
) get_absolute_expression ());
11161 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
11163 bfd_set_section_flags (stdoutput
, seg
,
11164 SEC_ALLOC
| SEC_LOAD
| SEC_RELOC
| SEC_DATA
);
11165 if (strcmp (TARGET_OS
, "elf") != 0)
11166 record_alignment (seg
, 4);
11168 demand_empty_rest_of_line ();
11176 s_change_section (int ignore ATTRIBUTE_UNUSED
)
11179 char *section_name
;
11184 int section_entry_size
;
11185 int section_alignment
;
11187 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
11190 section_name
= input_line_pointer
;
11191 c
= get_symbol_end ();
11193 next_c
= *(input_line_pointer
+ 1);
11195 /* Do we have .section Name<,"flags">? */
11196 if (c
!= ',' || (c
== ',' && next_c
== '"'))
11198 /* just after name is now '\0'. */
11199 *input_line_pointer
= c
;
11200 input_line_pointer
= section_name
;
11201 obj_elf_section (ignore
);
11204 input_line_pointer
++;
11206 /* Do we have .section Name<,type><,flag><,entry_size><,alignment> */
11208 section_type
= get_absolute_expression ();
11211 if (*input_line_pointer
++ == ',')
11212 section_flag
= get_absolute_expression ();
11215 if (*input_line_pointer
++ == ',')
11216 section_entry_size
= get_absolute_expression ();
11218 section_entry_size
= 0;
11219 if (*input_line_pointer
++ == ',')
11220 section_alignment
= get_absolute_expression ();
11222 section_alignment
= 0;
11224 section_name
= xstrdup (section_name
);
11226 /* When using the generic form of .section (as implemented by obj-elf.c),
11227 there's no way to set the section type to SHT_MIPS_DWARF. Users have
11228 traditionally had to fall back on the more common @progbits instead.
11230 There's nothing really harmful in this, since bfd will correct
11231 SHT_PROGBITS to SHT_MIPS_DWARF before writing out the file. But it
11232 means that, for backwards compatibiltiy, the special_section entries
11233 for dwarf sections must use SHT_PROGBITS rather than SHT_MIPS_DWARF.
11235 Even so, we shouldn't force users of the MIPS .section syntax to
11236 incorrectly label the sections as SHT_PROGBITS. The best compromise
11237 seems to be to map SHT_MIPS_DWARF to SHT_PROGBITS before calling the
11238 generic type-checking code. */
11239 if (section_type
== SHT_MIPS_DWARF
)
11240 section_type
= SHT_PROGBITS
;
11242 obj_elf_change_section (section_name
, section_type
, section_flag
,
11243 section_entry_size
, 0, 0, 0);
11245 if (now_seg
->name
!= section_name
)
11246 free (section_name
);
11247 #endif /* OBJ_ELF */
11251 mips_enable_auto_align (void)
11257 s_cons (int log_size
)
11261 label
= insn_labels
!= NULL
? insn_labels
->label
: NULL
;
11262 mips_emit_delays ();
11263 if (log_size
> 0 && auto_align
)
11264 mips_align (log_size
, 0, label
);
11265 mips_clear_insn_labels ();
11266 cons (1 << log_size
);
11270 s_float_cons (int type
)
11274 label
= insn_labels
!= NULL
? insn_labels
->label
: NULL
;
11276 mips_emit_delays ();
11281 mips_align (3, 0, label
);
11283 mips_align (2, 0, label
);
11286 mips_clear_insn_labels ();
11291 /* Handle .globl. We need to override it because on Irix 5 you are
11294 where foo is an undefined symbol, to mean that foo should be
11295 considered to be the address of a function. */
11298 s_mips_globl (int x ATTRIBUTE_UNUSED
)
11305 name
= input_line_pointer
;
11306 c
= get_symbol_end ();
11307 symbolP
= symbol_find_or_make (name
);
11308 *input_line_pointer
= c
;
11309 SKIP_WHITESPACE ();
11311 /* On Irix 5, every global symbol that is not explicitly labelled as
11312 being a function is apparently labelled as being an object. */
11315 if (! is_end_of_line
[(unsigned char) *input_line_pointer
])
11320 secname
= input_line_pointer
;
11321 c
= get_symbol_end ();
11322 sec
= bfd_get_section_by_name (stdoutput
, secname
);
11324 as_bad (_("%s: no such section"), secname
);
11325 *input_line_pointer
= c
;
11327 if (sec
!= NULL
&& (sec
->flags
& SEC_CODE
) != 0)
11328 flag
= BSF_FUNCTION
;
11331 symbol_get_bfdsym (symbolP
)->flags
|= flag
;
11333 S_SET_EXTERNAL (symbolP
);
11334 demand_empty_rest_of_line ();
11338 s_option (int x ATTRIBUTE_UNUSED
)
11343 opt
= input_line_pointer
;
11344 c
= get_symbol_end ();
11348 /* FIXME: What does this mean? */
11350 else if (strncmp (opt
, "pic", 3) == 0)
11354 i
= atoi (opt
+ 3);
11359 mips_pic
= SVR4_PIC
;
11360 mips_abicalls
= TRUE
;
11363 as_bad (_(".option pic%d not supported"), i
);
11365 if (mips_pic
== SVR4_PIC
)
11367 if (g_switch_seen
&& g_switch_value
!= 0)
11368 as_warn (_("-G may not be used with SVR4 PIC code"));
11369 g_switch_value
= 0;
11370 bfd_set_gp_size (stdoutput
, 0);
11374 as_warn (_("Unrecognized option \"%s\""), opt
);
11376 *input_line_pointer
= c
;
11377 demand_empty_rest_of_line ();
11380 /* This structure is used to hold a stack of .set values. */
11382 struct mips_option_stack
11384 struct mips_option_stack
*next
;
11385 struct mips_set_options options
;
11388 static struct mips_option_stack
*mips_opts_stack
;
11390 /* Handle the .set pseudo-op. */
11393 s_mipsset (int x ATTRIBUTE_UNUSED
)
11395 char *name
= input_line_pointer
, ch
;
11397 while (!is_end_of_line
[(unsigned char) *input_line_pointer
])
11398 ++input_line_pointer
;
11399 ch
= *input_line_pointer
;
11400 *input_line_pointer
= '\0';
11402 if (strcmp (name
, "reorder") == 0)
11404 if (mips_opts
.noreorder
)
11407 else if (strcmp (name
, "noreorder") == 0)
11409 if (!mips_opts
.noreorder
)
11410 start_noreorder ();
11412 else if (strcmp (name
, "at") == 0)
11414 mips_opts
.noat
= 0;
11416 else if (strcmp (name
, "noat") == 0)
11418 mips_opts
.noat
= 1;
11420 else if (strcmp (name
, "macro") == 0)
11422 mips_opts
.warn_about_macros
= 0;
11424 else if (strcmp (name
, "nomacro") == 0)
11426 if (mips_opts
.noreorder
== 0)
11427 as_bad (_("`noreorder' must be set before `nomacro'"));
11428 mips_opts
.warn_about_macros
= 1;
11430 else if (strcmp (name
, "move") == 0 || strcmp (name
, "novolatile") == 0)
11432 mips_opts
.nomove
= 0;
11434 else if (strcmp (name
, "nomove") == 0 || strcmp (name
, "volatile") == 0)
11436 mips_opts
.nomove
= 1;
11438 else if (strcmp (name
, "bopt") == 0)
11440 mips_opts
.nobopt
= 0;
11442 else if (strcmp (name
, "nobopt") == 0)
11444 mips_opts
.nobopt
= 1;
11446 else if (strcmp (name
, "mips16") == 0
11447 || strcmp (name
, "MIPS-16") == 0)
11448 mips_opts
.mips16
= 1;
11449 else if (strcmp (name
, "nomips16") == 0
11450 || strcmp (name
, "noMIPS-16") == 0)
11451 mips_opts
.mips16
= 0;
11452 else if (strcmp (name
, "mips3d") == 0)
11453 mips_opts
.ase_mips3d
= 1;
11454 else if (strcmp (name
, "nomips3d") == 0)
11455 mips_opts
.ase_mips3d
= 0;
11456 else if (strcmp (name
, "mdmx") == 0)
11457 mips_opts
.ase_mdmx
= 1;
11458 else if (strcmp (name
, "nomdmx") == 0)
11459 mips_opts
.ase_mdmx
= 0;
11460 else if (strncmp (name
, "mips", 4) == 0 || strncmp (name
, "arch=", 5) == 0)
11464 /* Permit the user to change the ISA and architecture on the fly.
11465 Needless to say, misuse can cause serious problems. */
11466 if (strcmp (name
, "mips0") == 0 || strcmp (name
, "arch=default") == 0)
11469 mips_opts
.isa
= file_mips_isa
;
11470 mips_opts
.arch
= file_mips_arch
;
11472 else if (strncmp (name
, "arch=", 5) == 0)
11474 const struct mips_cpu_info
*p
;
11476 p
= mips_parse_cpu("internal use", name
+ 5);
11478 as_bad (_("unknown architecture %s"), name
+ 5);
11481 mips_opts
.arch
= p
->cpu
;
11482 mips_opts
.isa
= p
->isa
;
11485 else if (strncmp (name
, "mips", 4) == 0)
11487 const struct mips_cpu_info
*p
;
11489 p
= mips_parse_cpu("internal use", name
);
11491 as_bad (_("unknown ISA level %s"), name
+ 4);
11494 mips_opts
.arch
= p
->cpu
;
11495 mips_opts
.isa
= p
->isa
;
11499 as_bad (_("unknown ISA or architecture %s"), name
);
11501 switch (mips_opts
.isa
)
11509 mips_opts
.gp32
= 1;
11510 mips_opts
.fp32
= 1;
11517 mips_opts
.gp32
= 0;
11518 mips_opts
.fp32
= 0;
11521 as_bad (_("unknown ISA level %s"), name
+ 4);
11526 mips_opts
.gp32
= file_mips_gp32
;
11527 mips_opts
.fp32
= file_mips_fp32
;
11530 else if (strcmp (name
, "autoextend") == 0)
11531 mips_opts
.noautoextend
= 0;
11532 else if (strcmp (name
, "noautoextend") == 0)
11533 mips_opts
.noautoextend
= 1;
11534 else if (strcmp (name
, "push") == 0)
11536 struct mips_option_stack
*s
;
11538 s
= (struct mips_option_stack
*) xmalloc (sizeof *s
);
11539 s
->next
= mips_opts_stack
;
11540 s
->options
= mips_opts
;
11541 mips_opts_stack
= s
;
11543 else if (strcmp (name
, "pop") == 0)
11545 struct mips_option_stack
*s
;
11547 s
= mips_opts_stack
;
11549 as_bad (_(".set pop with no .set push"));
11552 /* If we're changing the reorder mode we need to handle
11553 delay slots correctly. */
11554 if (s
->options
.noreorder
&& ! mips_opts
.noreorder
)
11555 start_noreorder ();
11556 else if (! s
->options
.noreorder
&& mips_opts
.noreorder
)
11559 mips_opts
= s
->options
;
11560 mips_opts_stack
= s
->next
;
11564 else if (strcmp (name
, "sym32") == 0)
11565 mips_opts
.sym32
= TRUE
;
11566 else if (strcmp (name
, "nosym32") == 0)
11567 mips_opts
.sym32
= FALSE
;
11570 as_warn (_("Tried to set unrecognized symbol: %s\n"), name
);
11572 *input_line_pointer
= ch
;
11573 demand_empty_rest_of_line ();
11576 /* Handle the .abicalls pseudo-op. I believe this is equivalent to
11577 .option pic2. It means to generate SVR4 PIC calls. */
11580 s_abicalls (int ignore ATTRIBUTE_UNUSED
)
11582 mips_pic
= SVR4_PIC
;
11583 mips_abicalls
= TRUE
;
11585 if (g_switch_seen
&& g_switch_value
!= 0)
11586 as_warn (_("-G may not be used with SVR4 PIC code"));
11587 g_switch_value
= 0;
11589 bfd_set_gp_size (stdoutput
, 0);
11590 demand_empty_rest_of_line ();
11593 /* Handle the .cpload pseudo-op. This is used when generating SVR4
11594 PIC code. It sets the $gp register for the function based on the
11595 function address, which is in the register named in the argument.
11596 This uses a relocation against _gp_disp, which is handled specially
11597 by the linker. The result is:
11598 lui $gp,%hi(_gp_disp)
11599 addiu $gp,$gp,%lo(_gp_disp)
11600 addu $gp,$gp,.cpload argument
11601 The .cpload argument is normally $25 == $t9.
11603 The -mno-shared option changes this to:
11604 lui $gp,%hi(__gnu_local_gp)
11605 addiu $gp,$gp,%lo(__gnu_local_gp)
11606 and the argument is ignored. This saves an instruction, but the
11607 resulting code is not position independent; it uses an absolute
11608 address for __gnu_local_gp. Thus code assembled with -mno-shared
11609 can go into an ordinary executable, but not into a shared library. */
11612 s_cpload (int ignore ATTRIBUTE_UNUSED
)
11618 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
11619 .cpload is ignored. */
11620 if (mips_pic
!= SVR4_PIC
|| HAVE_NEWABI
)
11626 /* .cpload should be in a .set noreorder section. */
11627 if (mips_opts
.noreorder
== 0)
11628 as_warn (_(".cpload not in noreorder section"));
11630 reg
= tc_get_register (0);
11632 /* If we need to produce a 64-bit address, we are better off using
11633 the default instruction sequence. */
11634 in_shared
= mips_in_shared
|| HAVE_64BIT_SYMBOLS
;
11636 ex
.X_op
= O_symbol
;
11637 ex
.X_add_symbol
= symbol_find_or_make (in_shared
? "_gp_disp" :
11639 ex
.X_op_symbol
= NULL
;
11640 ex
.X_add_number
= 0;
11642 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
11643 symbol_get_bfdsym (ex
.X_add_symbol
)->flags
|= BSF_OBJECT
;
11646 macro_build_lui (&ex
, mips_gp_register
);
11647 macro_build (&ex
, "addiu", "t,r,j", mips_gp_register
,
11648 mips_gp_register
, BFD_RELOC_LO16
);
11650 macro_build (NULL
, "addu", "d,v,t", mips_gp_register
,
11651 mips_gp_register
, reg
);
11654 demand_empty_rest_of_line ();
11657 /* Handle the .cpsetup pseudo-op defined for NewABI PIC code. The syntax is:
11658 .cpsetup $reg1, offset|$reg2, label
11660 If offset is given, this results in:
11661 sd $gp, offset($sp)
11662 lui $gp, %hi(%neg(%gp_rel(label)))
11663 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
11664 daddu $gp, $gp, $reg1
11666 If $reg2 is given, this results in:
11667 daddu $reg2, $gp, $0
11668 lui $gp, %hi(%neg(%gp_rel(label)))
11669 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
11670 daddu $gp, $gp, $reg1
11671 $reg1 is normally $25 == $t9.
11673 The -mno-shared option replaces the last three instructions with
11675 addiu $gp,$gp,%lo(_gp)
11679 s_cpsetup (int ignore ATTRIBUTE_UNUSED
)
11681 expressionS ex_off
;
11682 expressionS ex_sym
;
11685 /* If we are not generating SVR4 PIC code, .cpsetup is ignored.
11686 We also need NewABI support. */
11687 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
11693 reg1
= tc_get_register (0);
11694 SKIP_WHITESPACE ();
11695 if (*input_line_pointer
!= ',')
11697 as_bad (_("missing argument separator ',' for .cpsetup"));
11701 ++input_line_pointer
;
11702 SKIP_WHITESPACE ();
11703 if (*input_line_pointer
== '$')
11705 mips_cpreturn_register
= tc_get_register (0);
11706 mips_cpreturn_offset
= -1;
11710 mips_cpreturn_offset
= get_absolute_expression ();
11711 mips_cpreturn_register
= -1;
11713 SKIP_WHITESPACE ();
11714 if (*input_line_pointer
!= ',')
11716 as_bad (_("missing argument separator ',' for .cpsetup"));
11720 ++input_line_pointer
;
11721 SKIP_WHITESPACE ();
11722 expression (&ex_sym
);
11725 if (mips_cpreturn_register
== -1)
11727 ex_off
.X_op
= O_constant
;
11728 ex_off
.X_add_symbol
= NULL
;
11729 ex_off
.X_op_symbol
= NULL
;
11730 ex_off
.X_add_number
= mips_cpreturn_offset
;
11732 macro_build (&ex_off
, "sd", "t,o(b)", mips_gp_register
,
11733 BFD_RELOC_LO16
, SP
);
11736 macro_build (NULL
, "daddu", "d,v,t", mips_cpreturn_register
,
11737 mips_gp_register
, 0);
11739 if (mips_in_shared
|| HAVE_64BIT_SYMBOLS
)
11741 macro_build (&ex_sym
, "lui", "t,u", mips_gp_register
,
11742 -1, BFD_RELOC_GPREL16
, BFD_RELOC_MIPS_SUB
,
11745 macro_build (&ex_sym
, "addiu", "t,r,j", mips_gp_register
,
11746 mips_gp_register
, -1, BFD_RELOC_GPREL16
,
11747 BFD_RELOC_MIPS_SUB
, BFD_RELOC_LO16
);
11749 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", mips_gp_register
,
11750 mips_gp_register
, reg1
);
11756 ex
.X_op
= O_symbol
;
11757 ex
.X_add_symbol
= symbol_find_or_make ("_gp");
11758 ex
.X_op_symbol
= NULL
;
11759 ex
.X_add_number
= 0;
11761 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
11762 symbol_get_bfdsym (ex
.X_add_symbol
)->flags
|= BSF_OBJECT
;
11764 macro_build_lui (&ex
, mips_gp_register
);
11765 macro_build (&ex
, "addiu", "t,r,j", mips_gp_register
,
11766 mips_gp_register
, BFD_RELOC_LO16
);
11771 demand_empty_rest_of_line ();
11775 s_cplocal (int ignore ATTRIBUTE_UNUSED
)
11777 /* If we are not generating SVR4 PIC code, or if this is not NewABI code,
11778 .cplocal is ignored. */
11779 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
11785 mips_gp_register
= tc_get_register (0);
11786 demand_empty_rest_of_line ();
11789 /* Handle the .cprestore pseudo-op. This stores $gp into a given
11790 offset from $sp. The offset is remembered, and after making a PIC
11791 call $gp is restored from that location. */
11794 s_cprestore (int ignore ATTRIBUTE_UNUSED
)
11798 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
11799 .cprestore is ignored. */
11800 if (mips_pic
!= SVR4_PIC
|| HAVE_NEWABI
)
11806 mips_cprestore_offset
= get_absolute_expression ();
11807 mips_cprestore_valid
= 1;
11809 ex
.X_op
= O_constant
;
11810 ex
.X_add_symbol
= NULL
;
11811 ex
.X_op_symbol
= NULL
;
11812 ex
.X_add_number
= mips_cprestore_offset
;
11815 macro_build_ldst_constoffset (&ex
, ADDRESS_STORE_INSN
, mips_gp_register
,
11816 SP
, HAVE_64BIT_ADDRESSES
);
11819 demand_empty_rest_of_line ();
11822 /* Handle the .cpreturn pseudo-op defined for NewABI PIC code. If an offset
11823 was given in the preceding .cpsetup, it results in:
11824 ld $gp, offset($sp)
11826 If a register $reg2 was given there, it results in:
11827 daddu $gp, $reg2, $0
11830 s_cpreturn (int ignore ATTRIBUTE_UNUSED
)
11834 /* If we are not generating SVR4 PIC code, .cpreturn is ignored.
11835 We also need NewABI support. */
11836 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
11843 if (mips_cpreturn_register
== -1)
11845 ex
.X_op
= O_constant
;
11846 ex
.X_add_symbol
= NULL
;
11847 ex
.X_op_symbol
= NULL
;
11848 ex
.X_add_number
= mips_cpreturn_offset
;
11850 macro_build (&ex
, "ld", "t,o(b)", mips_gp_register
, BFD_RELOC_LO16
, SP
);
11853 macro_build (NULL
, "daddu", "d,v,t", mips_gp_register
,
11854 mips_cpreturn_register
, 0);
11857 demand_empty_rest_of_line ();
11860 /* Handle the .gpvalue pseudo-op. This is used when generating NewABI PIC
11861 code. It sets the offset to use in gp_rel relocations. */
11864 s_gpvalue (int ignore ATTRIBUTE_UNUSED
)
11866 /* If we are not generating SVR4 PIC code, .gpvalue is ignored.
11867 We also need NewABI support. */
11868 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
11874 mips_gprel_offset
= get_absolute_expression ();
11876 demand_empty_rest_of_line ();
11879 /* Handle the .gpword pseudo-op. This is used when generating PIC
11880 code. It generates a 32 bit GP relative reloc. */
11883 s_gpword (int ignore ATTRIBUTE_UNUSED
)
11889 /* When not generating PIC code, this is treated as .word. */
11890 if (mips_pic
!= SVR4_PIC
)
11896 label
= insn_labels
!= NULL
? insn_labels
->label
: NULL
;
11897 mips_emit_delays ();
11899 mips_align (2, 0, label
);
11900 mips_clear_insn_labels ();
11904 if (ex
.X_op
!= O_symbol
|| ex
.X_add_number
!= 0)
11906 as_bad (_("Unsupported use of .gpword"));
11907 ignore_rest_of_line ();
11911 md_number_to_chars (p
, 0, 4);
11912 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 4, &ex
, FALSE
,
11913 BFD_RELOC_GPREL32
);
11915 demand_empty_rest_of_line ();
11919 s_gpdword (int ignore ATTRIBUTE_UNUSED
)
11925 /* When not generating PIC code, this is treated as .dword. */
11926 if (mips_pic
!= SVR4_PIC
)
11932 label
= insn_labels
!= NULL
? insn_labels
->label
: NULL
;
11933 mips_emit_delays ();
11935 mips_align (3, 0, label
);
11936 mips_clear_insn_labels ();
11940 if (ex
.X_op
!= O_symbol
|| ex
.X_add_number
!= 0)
11942 as_bad (_("Unsupported use of .gpdword"));
11943 ignore_rest_of_line ();
11947 md_number_to_chars (p
, 0, 8);
11948 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 4, &ex
, FALSE
,
11949 BFD_RELOC_GPREL32
)->fx_tcbit
= 1;
11951 /* GPREL32 composed with 64 gives a 64-bit GP offset. */
11952 fix_new (frag_now
, p
- frag_now
->fr_literal
, 8, NULL
, 0,
11953 FALSE
, BFD_RELOC_64
)->fx_tcbit
= 1;
11955 demand_empty_rest_of_line ();
11958 /* Handle the .cpadd pseudo-op. This is used when dealing with switch
11959 tables in SVR4 PIC code. */
11962 s_cpadd (int ignore ATTRIBUTE_UNUSED
)
11966 /* This is ignored when not generating SVR4 PIC code. */
11967 if (mips_pic
!= SVR4_PIC
)
11973 /* Add $gp to the register named as an argument. */
11975 reg
= tc_get_register (0);
11976 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", reg
, reg
, mips_gp_register
);
11979 demand_empty_rest_of_line ();
11982 /* Handle the .insn pseudo-op. This marks instruction labels in
11983 mips16 mode. This permits the linker to handle them specially,
11984 such as generating jalx instructions when needed. We also make
11985 them odd for the duration of the assembly, in order to generate the
11986 right sort of code. We will make them even in the adjust_symtab
11987 routine, while leaving them marked. This is convenient for the
11988 debugger and the disassembler. The linker knows to make them odd
11992 s_insn (int ignore ATTRIBUTE_UNUSED
)
11994 mips16_mark_labels ();
11996 demand_empty_rest_of_line ();
11999 /* Handle a .stabn directive. We need these in order to mark a label
12000 as being a mips16 text label correctly. Sometimes the compiler
12001 will emit a label, followed by a .stabn, and then switch sections.
12002 If the label and .stabn are in mips16 mode, then the label is
12003 really a mips16 text label. */
12006 s_mips_stab (int type
)
12009 mips16_mark_labels ();
12014 /* Handle the .weakext pseudo-op as defined in Kane and Heinrich.
12018 s_mips_weakext (int ignore ATTRIBUTE_UNUSED
)
12025 name
= input_line_pointer
;
12026 c
= get_symbol_end ();
12027 symbolP
= symbol_find_or_make (name
);
12028 S_SET_WEAK (symbolP
);
12029 *input_line_pointer
= c
;
12031 SKIP_WHITESPACE ();
12033 if (! is_end_of_line
[(unsigned char) *input_line_pointer
])
12035 if (S_IS_DEFINED (symbolP
))
12037 as_bad ("ignoring attempt to redefine symbol %s",
12038 S_GET_NAME (symbolP
));
12039 ignore_rest_of_line ();
12043 if (*input_line_pointer
== ',')
12045 ++input_line_pointer
;
12046 SKIP_WHITESPACE ();
12050 if (exp
.X_op
!= O_symbol
)
12052 as_bad ("bad .weakext directive");
12053 ignore_rest_of_line ();
12056 symbol_set_value_expression (symbolP
, &exp
);
12059 demand_empty_rest_of_line ();
12062 /* Parse a register string into a number. Called from the ECOFF code
12063 to parse .frame. The argument is non-zero if this is the frame
12064 register, so that we can record it in mips_frame_reg. */
12067 tc_get_register (int frame
)
12071 SKIP_WHITESPACE ();
12072 if (*input_line_pointer
++ != '$')
12074 as_warn (_("expected `$'"));
12077 else if (ISDIGIT (*input_line_pointer
))
12079 reg
= get_absolute_expression ();
12080 if (reg
< 0 || reg
>= 32)
12082 as_warn (_("Bad register number"));
12088 if (strncmp (input_line_pointer
, "ra", 2) == 0)
12091 input_line_pointer
+= 2;
12093 else if (strncmp (input_line_pointer
, "fp", 2) == 0)
12096 input_line_pointer
+= 2;
12098 else if (strncmp (input_line_pointer
, "sp", 2) == 0)
12101 input_line_pointer
+= 2;
12103 else if (strncmp (input_line_pointer
, "gp", 2) == 0)
12106 input_line_pointer
+= 2;
12108 else if (strncmp (input_line_pointer
, "at", 2) == 0)
12111 input_line_pointer
+= 2;
12113 else if (strncmp (input_line_pointer
, "kt0", 3) == 0)
12116 input_line_pointer
+= 3;
12118 else if (strncmp (input_line_pointer
, "kt1", 3) == 0)
12121 input_line_pointer
+= 3;
12123 else if (strncmp (input_line_pointer
, "zero", 4) == 0)
12126 input_line_pointer
+= 4;
12130 as_warn (_("Unrecognized register name"));
12132 while (ISALNUM(*input_line_pointer
))
12133 input_line_pointer
++;
12138 mips_frame_reg
= reg
!= 0 ? reg
: SP
;
12139 mips_frame_reg_valid
= 1;
12140 mips_cprestore_valid
= 0;
12146 md_section_align (asection
*seg
, valueT addr
)
12148 int align
= bfd_get_section_alignment (stdoutput
, seg
);
12151 /* We don't need to align ELF sections to the full alignment.
12152 However, Irix 5 may prefer that we align them at least to a 16
12153 byte boundary. We don't bother to align the sections if we are
12154 targeted for an embedded system. */
12155 if (strcmp (TARGET_OS
, "elf") == 0)
12161 return ((addr
+ (1 << align
) - 1) & (-1 << align
));
12164 /* Utility routine, called from above as well. If called while the
12165 input file is still being read, it's only an approximation. (For
12166 example, a symbol may later become defined which appeared to be
12167 undefined earlier.) */
12170 nopic_need_relax (symbolS
*sym
, int before_relaxing
)
12175 if (g_switch_value
> 0)
12177 const char *symname
;
12180 /* Find out whether this symbol can be referenced off the $gp
12181 register. It can be if it is smaller than the -G size or if
12182 it is in the .sdata or .sbss section. Certain symbols can
12183 not be referenced off the $gp, although it appears as though
12185 symname
= S_GET_NAME (sym
);
12186 if (symname
!= (const char *) NULL
12187 && (strcmp (symname
, "eprol") == 0
12188 || strcmp (symname
, "etext") == 0
12189 || strcmp (symname
, "_gp") == 0
12190 || strcmp (symname
, "edata") == 0
12191 || strcmp (symname
, "_fbss") == 0
12192 || strcmp (symname
, "_fdata") == 0
12193 || strcmp (symname
, "_ftext") == 0
12194 || strcmp (symname
, "end") == 0
12195 || strcmp (symname
, "_gp_disp") == 0))
12197 else if ((! S_IS_DEFINED (sym
) || S_IS_COMMON (sym
))
12199 #ifndef NO_ECOFF_DEBUGGING
12200 || (symbol_get_obj (sym
)->ecoff_extern_size
!= 0
12201 && (symbol_get_obj (sym
)->ecoff_extern_size
12202 <= g_switch_value
))
12204 /* We must defer this decision until after the whole
12205 file has been read, since there might be a .extern
12206 after the first use of this symbol. */
12207 || (before_relaxing
12208 #ifndef NO_ECOFF_DEBUGGING
12209 && symbol_get_obj (sym
)->ecoff_extern_size
== 0
12211 && S_GET_VALUE (sym
) == 0)
12212 || (S_GET_VALUE (sym
) != 0
12213 && S_GET_VALUE (sym
) <= g_switch_value
)))
12217 const char *segname
;
12219 segname
= segment_name (S_GET_SEGMENT (sym
));
12220 assert (strcmp (segname
, ".lit8") != 0
12221 && strcmp (segname
, ".lit4") != 0);
12222 change
= (strcmp (segname
, ".sdata") != 0
12223 && strcmp (segname
, ".sbss") != 0
12224 && strncmp (segname
, ".sdata.", 7) != 0
12225 && strncmp (segname
, ".gnu.linkonce.s.", 16) != 0);
12230 /* We are not optimizing for the $gp register. */
12235 /* Return true if the given symbol should be considered local for SVR4 PIC. */
12238 pic_need_relax (symbolS
*sym
, asection
*segtype
)
12241 bfd_boolean linkonce
;
12243 /* Handle the case of a symbol equated to another symbol. */
12244 while (symbol_equated_reloc_p (sym
))
12248 /* It's possible to get a loop here in a badly written
12250 n
= symbol_get_value_expression (sym
)->X_add_symbol
;
12256 symsec
= S_GET_SEGMENT (sym
);
12258 /* duplicate the test for LINK_ONCE sections as in adjust_reloc_syms */
12260 if (symsec
!= segtype
&& ! S_IS_LOCAL (sym
))
12262 if ((bfd_get_section_flags (stdoutput
, symsec
) & SEC_LINK_ONCE
)
12266 /* The GNU toolchain uses an extension for ELF: a section
12267 beginning with the magic string .gnu.linkonce is a linkonce
12269 if (strncmp (segment_name (symsec
), ".gnu.linkonce",
12270 sizeof ".gnu.linkonce" - 1) == 0)
12274 /* This must duplicate the test in adjust_reloc_syms. */
12275 return (symsec
!= &bfd_und_section
12276 && symsec
!= &bfd_abs_section
12277 && ! bfd_is_com_section (symsec
)
12280 /* A global or weak symbol is treated as external. */
12281 && (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
12282 || (! S_IS_WEAK (sym
) && ! S_IS_EXTERNAL (sym
)))
12288 /* Given a mips16 variant frag FRAGP, return non-zero if it needs an
12289 extended opcode. SEC is the section the frag is in. */
12292 mips16_extended_frag (fragS
*fragp
, asection
*sec
, long stretch
)
12295 register const struct mips16_immed_operand
*op
;
12297 int mintiny
, maxtiny
;
12301 if (RELAX_MIPS16_USER_SMALL (fragp
->fr_subtype
))
12303 if (RELAX_MIPS16_USER_EXT (fragp
->fr_subtype
))
12306 type
= RELAX_MIPS16_TYPE (fragp
->fr_subtype
);
12307 op
= mips16_immed_operands
;
12308 while (op
->type
!= type
)
12311 assert (op
< mips16_immed_operands
+ MIPS16_NUM_IMMED
);
12316 if (type
== '<' || type
== '>' || type
== '[' || type
== ']')
12319 maxtiny
= 1 << op
->nbits
;
12324 maxtiny
= (1 << op
->nbits
) - 1;
12329 mintiny
= - (1 << (op
->nbits
- 1));
12330 maxtiny
= (1 << (op
->nbits
- 1)) - 1;
12333 sym_frag
= symbol_get_frag (fragp
->fr_symbol
);
12334 val
= S_GET_VALUE (fragp
->fr_symbol
);
12335 symsec
= S_GET_SEGMENT (fragp
->fr_symbol
);
12341 /* We won't have the section when we are called from
12342 mips_relax_frag. However, we will always have been called
12343 from md_estimate_size_before_relax first. If this is a
12344 branch to a different section, we mark it as such. If SEC is
12345 NULL, and the frag is not marked, then it must be a branch to
12346 the same section. */
12349 if (RELAX_MIPS16_LONG_BRANCH (fragp
->fr_subtype
))
12354 /* Must have been called from md_estimate_size_before_relax. */
12357 fragp
->fr_subtype
=
12358 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
12360 /* FIXME: We should support this, and let the linker
12361 catch branches and loads that are out of range. */
12362 as_bad_where (fragp
->fr_file
, fragp
->fr_line
,
12363 _("unsupported PC relative reference to different section"));
12367 if (fragp
!= sym_frag
&& sym_frag
->fr_address
== 0)
12368 /* Assume non-extended on the first relaxation pass.
12369 The address we have calculated will be bogus if this is
12370 a forward branch to another frag, as the forward frag
12371 will have fr_address == 0. */
12375 /* In this case, we know for sure that the symbol fragment is in
12376 the same section. If the relax_marker of the symbol fragment
12377 differs from the relax_marker of this fragment, we have not
12378 yet adjusted the symbol fragment fr_address. We want to add
12379 in STRETCH in order to get a better estimate of the address.
12380 This particularly matters because of the shift bits. */
12382 && sym_frag
->relax_marker
!= fragp
->relax_marker
)
12386 /* Adjust stretch for any alignment frag. Note that if have
12387 been expanding the earlier code, the symbol may be
12388 defined in what appears to be an earlier frag. FIXME:
12389 This doesn't handle the fr_subtype field, which specifies
12390 a maximum number of bytes to skip when doing an
12392 for (f
= fragp
; f
!= NULL
&& f
!= sym_frag
; f
= f
->fr_next
)
12394 if (f
->fr_type
== rs_align
|| f
->fr_type
== rs_align_code
)
12397 stretch
= - ((- stretch
)
12398 & ~ ((1 << (int) f
->fr_offset
) - 1));
12400 stretch
&= ~ ((1 << (int) f
->fr_offset
) - 1);
12409 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
12411 /* The base address rules are complicated. The base address of
12412 a branch is the following instruction. The base address of a
12413 PC relative load or add is the instruction itself, but if it
12414 is in a delay slot (in which case it can not be extended) use
12415 the address of the instruction whose delay slot it is in. */
12416 if (type
== 'p' || type
== 'q')
12420 /* If we are currently assuming that this frag should be
12421 extended, then, the current address is two bytes
12423 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
12426 /* Ignore the low bit in the target, since it will be set
12427 for a text label. */
12428 if ((val
& 1) != 0)
12431 else if (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
))
12433 else if (RELAX_MIPS16_DSLOT (fragp
->fr_subtype
))
12436 val
-= addr
& ~ ((1 << op
->shift
) - 1);
12438 /* Branch offsets have an implicit 0 in the lowest bit. */
12439 if (type
== 'p' || type
== 'q')
12442 /* If any of the shifted bits are set, we must use an extended
12443 opcode. If the address depends on the size of this
12444 instruction, this can lead to a loop, so we arrange to always
12445 use an extended opcode. We only check this when we are in
12446 the main relaxation loop, when SEC is NULL. */
12447 if ((val
& ((1 << op
->shift
) - 1)) != 0 && sec
== NULL
)
12449 fragp
->fr_subtype
=
12450 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
12454 /* If we are about to mark a frag as extended because the value
12455 is precisely maxtiny + 1, then there is a chance of an
12456 infinite loop as in the following code:
12461 In this case when the la is extended, foo is 0x3fc bytes
12462 away, so the la can be shrunk, but then foo is 0x400 away, so
12463 the la must be extended. To avoid this loop, we mark the
12464 frag as extended if it was small, and is about to become
12465 extended with a value of maxtiny + 1. */
12466 if (val
== ((maxtiny
+ 1) << op
->shift
)
12467 && ! RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
)
12470 fragp
->fr_subtype
=
12471 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
12475 else if (symsec
!= absolute_section
&& sec
!= NULL
)
12476 as_bad_where (fragp
->fr_file
, fragp
->fr_line
, _("unsupported relocation"));
12478 if ((val
& ((1 << op
->shift
) - 1)) != 0
12479 || val
< (mintiny
<< op
->shift
)
12480 || val
> (maxtiny
<< op
->shift
))
12486 /* Compute the length of a branch sequence, and adjust the
12487 RELAX_BRANCH_TOOFAR bit accordingly. If FRAGP is NULL, the
12488 worst-case length is computed, with UPDATE being used to indicate
12489 whether an unconditional (-1), branch-likely (+1) or regular (0)
12490 branch is to be computed. */
12492 relaxed_branch_length (fragS
*fragp
, asection
*sec
, int update
)
12494 bfd_boolean toofar
;
12498 && S_IS_DEFINED (fragp
->fr_symbol
)
12499 && sec
== S_GET_SEGMENT (fragp
->fr_symbol
))
12504 val
= S_GET_VALUE (fragp
->fr_symbol
) + fragp
->fr_offset
;
12506 addr
= fragp
->fr_address
+ fragp
->fr_fix
+ 4;
12510 toofar
= val
< - (0x8000 << 2) || val
>= (0x8000 << 2);
12513 /* If the symbol is not defined or it's in a different segment,
12514 assume the user knows what's going on and emit a short
12520 if (fragp
&& update
&& toofar
!= RELAX_BRANCH_TOOFAR (fragp
->fr_subtype
))
12522 = RELAX_BRANCH_ENCODE (RELAX_BRANCH_UNCOND (fragp
->fr_subtype
),
12523 RELAX_BRANCH_LIKELY (fragp
->fr_subtype
),
12524 RELAX_BRANCH_LINK (fragp
->fr_subtype
),
12530 if (fragp
? RELAX_BRANCH_LIKELY (fragp
->fr_subtype
) : (update
> 0))
12533 if (mips_pic
!= NO_PIC
)
12535 /* Additional space for PIC loading of target address. */
12537 if (mips_opts
.isa
== ISA_MIPS1
)
12538 /* Additional space for $at-stabilizing nop. */
12542 /* If branch is conditional. */
12543 if (fragp
? !RELAX_BRANCH_UNCOND (fragp
->fr_subtype
) : (update
>= 0))
12550 /* Estimate the size of a frag before relaxing. Unless this is the
12551 mips16, we are not really relaxing here, and the final size is
12552 encoded in the subtype information. For the mips16, we have to
12553 decide whether we are using an extended opcode or not. */
12556 md_estimate_size_before_relax (fragS
*fragp
, asection
*segtype
)
12560 if (RELAX_BRANCH_P (fragp
->fr_subtype
))
12563 fragp
->fr_var
= relaxed_branch_length (fragp
, segtype
, FALSE
);
12565 return fragp
->fr_var
;
12568 if (RELAX_MIPS16_P (fragp
->fr_subtype
))
12569 /* We don't want to modify the EXTENDED bit here; it might get us
12570 into infinite loops. We change it only in mips_relax_frag(). */
12571 return (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
) ? 4 : 2);
12573 if (mips_pic
== NO_PIC
)
12574 change
= nopic_need_relax (fragp
->fr_symbol
, 0);
12575 else if (mips_pic
== SVR4_PIC
)
12576 change
= pic_need_relax (fragp
->fr_symbol
, segtype
);
12582 fragp
->fr_subtype
|= RELAX_USE_SECOND
;
12583 return -RELAX_FIRST (fragp
->fr_subtype
);
12586 return -RELAX_SECOND (fragp
->fr_subtype
);
12589 /* This is called to see whether a reloc against a defined symbol
12590 should be converted into a reloc against a section. */
12593 mips_fix_adjustable (fixS
*fixp
)
12595 /* Don't adjust MIPS16 jump relocations, so we don't have to worry
12596 about the format of the offset in the .o file. */
12597 if (fixp
->fx_r_type
== BFD_RELOC_MIPS16_JMP
)
12600 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
12601 || fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
12604 if (fixp
->fx_addsy
== NULL
)
12607 /* If symbol SYM is in a mergeable section, relocations of the form
12608 SYM + 0 can usually be made section-relative. The mergeable data
12609 is then identified by the section offset rather than by the symbol.
12611 However, if we're generating REL LO16 relocations, the offset is split
12612 between the LO16 and parterning high part relocation. The linker will
12613 need to recalculate the complete offset in order to correctly identify
12616 The linker has traditionally not looked for the parterning high part
12617 relocation, and has thus allowed orphaned R_MIPS_LO16 relocations to be
12618 placed anywhere. Rather than break backwards compatibility by changing
12619 this, it seems better not to force the issue, and instead keep the
12620 original symbol. This will work with either linker behavior. */
12621 if ((fixp
->fx_r_type
== BFD_RELOC_LO16
|| reloc_needs_lo_p (fixp
->fx_r_type
))
12622 && HAVE_IN_PLACE_ADDENDS
12623 && (S_GET_SEGMENT (fixp
->fx_addsy
)->flags
& SEC_MERGE
) != 0)
12627 /* Don't adjust relocations against mips16 symbols, so that the linker
12628 can find them if it needs to set up a stub. */
12629 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
12630 && S_GET_OTHER (fixp
->fx_addsy
) == STO_MIPS16
12631 && fixp
->fx_subsy
== NULL
)
12638 /* Translate internal representation of relocation info to BFD target
12642 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
, fixS
*fixp
)
12644 static arelent
*retval
[4];
12646 bfd_reloc_code_real_type code
;
12648 memset (retval
, 0, sizeof(retval
));
12649 reloc
= retval
[0] = (arelent
*) xcalloc (1, sizeof (arelent
));
12650 reloc
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
12651 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
12652 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
12654 assert (! fixp
->fx_pcrel
);
12655 reloc
->addend
= fixp
->fx_addnumber
;
12657 /* Since the old MIPS ELF ABI uses Rel instead of Rela, encode the vtable
12658 entry to be used in the relocation's section offset. */
12659 if (! HAVE_NEWABI
&& fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
12661 reloc
->address
= reloc
->addend
;
12665 code
= fixp
->fx_r_type
;
12667 /* To support a PC relative reloc, we used a Cygnus extension.
12668 We check for that here to make sure that we don't let such a
12669 reloc escape normally. (FIXME: This was formerly used by
12670 embedded-PIC support, but is now used by branch handling in
12671 general. That probably should be fixed.) */
12672 if ((OUTPUT_FLAVOR
== bfd_target_ecoff_flavour
12673 || OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
12674 && code
== BFD_RELOC_16_PCREL_S2
)
12675 reloc
->howto
= NULL
;
12677 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
12679 if (reloc
->howto
== NULL
)
12681 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
12682 _("Can not represent %s relocation in this object file format"),
12683 bfd_get_reloc_code_name (code
));
12690 /* Relax a machine dependent frag. This returns the amount by which
12691 the current size of the frag should change. */
12694 mips_relax_frag (asection
*sec
, fragS
*fragp
, long stretch
)
12696 if (RELAX_BRANCH_P (fragp
->fr_subtype
))
12698 offsetT old_var
= fragp
->fr_var
;
12700 fragp
->fr_var
= relaxed_branch_length (fragp
, sec
, TRUE
);
12702 return fragp
->fr_var
- old_var
;
12705 if (! RELAX_MIPS16_P (fragp
->fr_subtype
))
12708 if (mips16_extended_frag (fragp
, NULL
, stretch
))
12710 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
12712 fragp
->fr_subtype
= RELAX_MIPS16_MARK_EXTENDED (fragp
->fr_subtype
);
12717 if (! RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
12719 fragp
->fr_subtype
= RELAX_MIPS16_CLEAR_EXTENDED (fragp
->fr_subtype
);
12726 /* Convert a machine dependent frag. */
12729 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
, segT asec
, fragS
*fragp
)
12731 if (RELAX_BRANCH_P (fragp
->fr_subtype
))
12734 unsigned long insn
;
12738 buf
= (bfd_byte
*)fragp
->fr_literal
+ fragp
->fr_fix
;
12740 if (target_big_endian
)
12741 insn
= bfd_getb32 (buf
);
12743 insn
= bfd_getl32 (buf
);
12745 if (!RELAX_BRANCH_TOOFAR (fragp
->fr_subtype
))
12747 /* We generate a fixup instead of applying it right now
12748 because, if there are linker relaxations, we're going to
12749 need the relocations. */
12750 exp
.X_op
= O_symbol
;
12751 exp
.X_add_symbol
= fragp
->fr_symbol
;
12752 exp
.X_add_number
= fragp
->fr_offset
;
12754 fixp
= fix_new_exp (fragp
, buf
- (bfd_byte
*)fragp
->fr_literal
,
12756 BFD_RELOC_16_PCREL_S2
);
12757 fixp
->fx_file
= fragp
->fr_file
;
12758 fixp
->fx_line
= fragp
->fr_line
;
12760 md_number_to_chars ((char *) buf
, insn
, 4);
12767 as_warn_where (fragp
->fr_file
, fragp
->fr_line
,
12768 _("relaxed out-of-range branch into a jump"));
12770 if (RELAX_BRANCH_UNCOND (fragp
->fr_subtype
))
12773 if (!RELAX_BRANCH_LIKELY (fragp
->fr_subtype
))
12775 /* Reverse the branch. */
12776 switch ((insn
>> 28) & 0xf)
12779 /* bc[0-3][tf]l? and bc1any[24][ft] instructions can
12780 have the condition reversed by tweaking a single
12781 bit, and their opcodes all have 0x4???????. */
12782 assert ((insn
& 0xf1000000) == 0x41000000);
12783 insn
^= 0x00010000;
12787 /* bltz 0x04000000 bgez 0x04010000
12788 bltzal 0x04100000 bgezal 0x04110000 */
12789 assert ((insn
& 0xfc0e0000) == 0x04000000);
12790 insn
^= 0x00010000;
12794 /* beq 0x10000000 bne 0x14000000
12795 blez 0x18000000 bgtz 0x1c000000 */
12796 insn
^= 0x04000000;
12804 if (RELAX_BRANCH_LINK (fragp
->fr_subtype
))
12806 /* Clear the and-link bit. */
12807 assert ((insn
& 0xfc1c0000) == 0x04100000);
12809 /* bltzal 0x04100000 bgezal 0x04110000
12810 bltzall 0x04120000 bgezall 0x04130000 */
12811 insn
&= ~0x00100000;
12814 /* Branch over the branch (if the branch was likely) or the
12815 full jump (not likely case). Compute the offset from the
12816 current instruction to branch to. */
12817 if (RELAX_BRANCH_LIKELY (fragp
->fr_subtype
))
12821 /* How many bytes in instructions we've already emitted? */
12822 i
= buf
- (bfd_byte
*)fragp
->fr_literal
- fragp
->fr_fix
;
12823 /* How many bytes in instructions from here to the end? */
12824 i
= fragp
->fr_var
- i
;
12826 /* Convert to instruction count. */
12828 /* Branch counts from the next instruction. */
12831 /* Branch over the jump. */
12832 md_number_to_chars ((char *) buf
, insn
, 4);
12836 md_number_to_chars ((char *) buf
, 0, 4);
12839 if (RELAX_BRANCH_LIKELY (fragp
->fr_subtype
))
12841 /* beql $0, $0, 2f */
12843 /* Compute the PC offset from the current instruction to
12844 the end of the variable frag. */
12845 /* How many bytes in instructions we've already emitted? */
12846 i
= buf
- (bfd_byte
*)fragp
->fr_literal
- fragp
->fr_fix
;
12847 /* How many bytes in instructions from here to the end? */
12848 i
= fragp
->fr_var
- i
;
12849 /* Convert to instruction count. */
12851 /* Don't decrement i, because we want to branch over the
12855 md_number_to_chars ((char *) buf
, insn
, 4);
12858 md_number_to_chars ((char *) buf
, 0, 4);
12863 if (mips_pic
== NO_PIC
)
12866 insn
= (RELAX_BRANCH_LINK (fragp
->fr_subtype
)
12867 ? 0x0c000000 : 0x08000000);
12868 exp
.X_op
= O_symbol
;
12869 exp
.X_add_symbol
= fragp
->fr_symbol
;
12870 exp
.X_add_number
= fragp
->fr_offset
;
12872 fixp
= fix_new_exp (fragp
, buf
- (bfd_byte
*)fragp
->fr_literal
,
12873 4, &exp
, 0, BFD_RELOC_MIPS_JMP
);
12874 fixp
->fx_file
= fragp
->fr_file
;
12875 fixp
->fx_line
= fragp
->fr_line
;
12877 md_number_to_chars ((char *) buf
, insn
, 4);
12882 /* lw/ld $at, <sym>($gp) R_MIPS_GOT16 */
12883 insn
= HAVE_64BIT_ADDRESSES
? 0xdf810000 : 0x8f810000;
12884 exp
.X_op
= O_symbol
;
12885 exp
.X_add_symbol
= fragp
->fr_symbol
;
12886 exp
.X_add_number
= fragp
->fr_offset
;
12888 if (fragp
->fr_offset
)
12890 exp
.X_add_symbol
= make_expr_symbol (&exp
);
12891 exp
.X_add_number
= 0;
12894 fixp
= fix_new_exp (fragp
, buf
- (bfd_byte
*)fragp
->fr_literal
,
12895 4, &exp
, 0, BFD_RELOC_MIPS_GOT16
);
12896 fixp
->fx_file
= fragp
->fr_file
;
12897 fixp
->fx_line
= fragp
->fr_line
;
12899 md_number_to_chars ((char *) buf
, insn
, 4);
12902 if (mips_opts
.isa
== ISA_MIPS1
)
12905 md_number_to_chars ((char *) buf
, 0, 4);
12909 /* d/addiu $at, $at, <sym> R_MIPS_LO16 */
12910 insn
= HAVE_64BIT_ADDRESSES
? 0x64210000 : 0x24210000;
12912 fixp
= fix_new_exp (fragp
, buf
- (bfd_byte
*)fragp
->fr_literal
,
12913 4, &exp
, 0, BFD_RELOC_LO16
);
12914 fixp
->fx_file
= fragp
->fr_file
;
12915 fixp
->fx_line
= fragp
->fr_line
;
12917 md_number_to_chars ((char *) buf
, insn
, 4);
12921 if (RELAX_BRANCH_LINK (fragp
->fr_subtype
))
12926 md_number_to_chars ((char *) buf
, insn
, 4);
12931 assert (buf
== (bfd_byte
*)fragp
->fr_literal
12932 + fragp
->fr_fix
+ fragp
->fr_var
);
12934 fragp
->fr_fix
+= fragp
->fr_var
;
12939 if (RELAX_MIPS16_P (fragp
->fr_subtype
))
12942 register const struct mips16_immed_operand
*op
;
12943 bfd_boolean small
, ext
;
12946 unsigned long insn
;
12947 bfd_boolean use_extend
;
12948 unsigned short extend
;
12950 type
= RELAX_MIPS16_TYPE (fragp
->fr_subtype
);
12951 op
= mips16_immed_operands
;
12952 while (op
->type
!= type
)
12955 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
12966 resolve_symbol_value (fragp
->fr_symbol
);
12967 val
= S_GET_VALUE (fragp
->fr_symbol
);
12972 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
12974 /* The rules for the base address of a PC relative reloc are
12975 complicated; see mips16_extended_frag. */
12976 if (type
== 'p' || type
== 'q')
12981 /* Ignore the low bit in the target, since it will be
12982 set for a text label. */
12983 if ((val
& 1) != 0)
12986 else if (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
))
12988 else if (RELAX_MIPS16_DSLOT (fragp
->fr_subtype
))
12991 addr
&= ~ (addressT
) ((1 << op
->shift
) - 1);
12994 /* Make sure the section winds up with the alignment we have
12997 record_alignment (asec
, op
->shift
);
13001 && (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
)
13002 || RELAX_MIPS16_DSLOT (fragp
->fr_subtype
)))
13003 as_warn_where (fragp
->fr_file
, fragp
->fr_line
,
13004 _("extended instruction in delay slot"));
13006 buf
= (bfd_byte
*) (fragp
->fr_literal
+ fragp
->fr_fix
);
13008 if (target_big_endian
)
13009 insn
= bfd_getb16 (buf
);
13011 insn
= bfd_getl16 (buf
);
13013 mips16_immed (fragp
->fr_file
, fragp
->fr_line
, type
, val
,
13014 RELAX_MIPS16_USER_EXT (fragp
->fr_subtype
),
13015 small
, ext
, &insn
, &use_extend
, &extend
);
13019 md_number_to_chars ((char *) buf
, 0xf000 | extend
, 2);
13020 fragp
->fr_fix
+= 2;
13024 md_number_to_chars ((char *) buf
, insn
, 2);
13025 fragp
->fr_fix
+= 2;
13033 first
= RELAX_FIRST (fragp
->fr_subtype
);
13034 second
= RELAX_SECOND (fragp
->fr_subtype
);
13035 fixp
= (fixS
*) fragp
->fr_opcode
;
13037 /* Possibly emit a warning if we've chosen the longer option. */
13038 if (((fragp
->fr_subtype
& RELAX_USE_SECOND
) != 0)
13039 == ((fragp
->fr_subtype
& RELAX_SECOND_LONGER
) != 0))
13041 const char *msg
= macro_warning (fragp
->fr_subtype
);
13043 as_warn_where (fragp
->fr_file
, fragp
->fr_line
, msg
);
13046 /* Go through all the fixups for the first sequence. Disable them
13047 (by marking them as done) if we're going to use the second
13048 sequence instead. */
13050 && fixp
->fx_frag
== fragp
13051 && fixp
->fx_where
< fragp
->fr_fix
- second
)
13053 if (fragp
->fr_subtype
& RELAX_USE_SECOND
)
13055 fixp
= fixp
->fx_next
;
13058 /* Go through the fixups for the second sequence. Disable them if
13059 we're going to use the first sequence, otherwise adjust their
13060 addresses to account for the relaxation. */
13061 while (fixp
&& fixp
->fx_frag
== fragp
)
13063 if (fragp
->fr_subtype
& RELAX_USE_SECOND
)
13064 fixp
->fx_where
-= first
;
13067 fixp
= fixp
->fx_next
;
13070 /* Now modify the frag contents. */
13071 if (fragp
->fr_subtype
& RELAX_USE_SECOND
)
13075 start
= fragp
->fr_literal
+ fragp
->fr_fix
- first
- second
;
13076 memmove (start
, start
+ first
, second
);
13077 fragp
->fr_fix
-= first
;
13080 fragp
->fr_fix
-= second
;
13086 /* This function is called after the relocs have been generated.
13087 We've been storing mips16 text labels as odd. Here we convert them
13088 back to even for the convenience of the debugger. */
13091 mips_frob_file_after_relocs (void)
13094 unsigned int count
, i
;
13096 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
13099 syms
= bfd_get_outsymbols (stdoutput
);
13100 count
= bfd_get_symcount (stdoutput
);
13101 for (i
= 0; i
< count
; i
++, syms
++)
13103 if (elf_symbol (*syms
)->internal_elf_sym
.st_other
== STO_MIPS16
13104 && ((*syms
)->value
& 1) != 0)
13106 (*syms
)->value
&= ~1;
13107 /* If the symbol has an odd size, it was probably computed
13108 incorrectly, so adjust that as well. */
13109 if ((elf_symbol (*syms
)->internal_elf_sym
.st_size
& 1) != 0)
13110 ++elf_symbol (*syms
)->internal_elf_sym
.st_size
;
13117 /* This function is called whenever a label is defined. It is used
13118 when handling branch delays; if a branch has a label, we assume we
13119 can not move it. */
13122 mips_define_label (symbolS
*sym
)
13124 struct insn_label_list
*l
;
13126 if (free_insn_labels
== NULL
)
13127 l
= (struct insn_label_list
*) xmalloc (sizeof *l
);
13130 l
= free_insn_labels
;
13131 free_insn_labels
= l
->next
;
13135 l
->next
= insn_labels
;
13139 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13141 /* Some special processing for a MIPS ELF file. */
13144 mips_elf_final_processing (void)
13146 /* Write out the register information. */
13147 if (mips_abi
!= N64_ABI
)
13151 s
.ri_gprmask
= mips_gprmask
;
13152 s
.ri_cprmask
[0] = mips_cprmask
[0];
13153 s
.ri_cprmask
[1] = mips_cprmask
[1];
13154 s
.ri_cprmask
[2] = mips_cprmask
[2];
13155 s
.ri_cprmask
[3] = mips_cprmask
[3];
13156 /* The gp_value field is set by the MIPS ELF backend. */
13158 bfd_mips_elf32_swap_reginfo_out (stdoutput
, &s
,
13159 ((Elf32_External_RegInfo
*)
13160 mips_regmask_frag
));
13164 Elf64_Internal_RegInfo s
;
13166 s
.ri_gprmask
= mips_gprmask
;
13168 s
.ri_cprmask
[0] = mips_cprmask
[0];
13169 s
.ri_cprmask
[1] = mips_cprmask
[1];
13170 s
.ri_cprmask
[2] = mips_cprmask
[2];
13171 s
.ri_cprmask
[3] = mips_cprmask
[3];
13172 /* The gp_value field is set by the MIPS ELF backend. */
13174 bfd_mips_elf64_swap_reginfo_out (stdoutput
, &s
,
13175 ((Elf64_External_RegInfo
*)
13176 mips_regmask_frag
));
13179 /* Set the MIPS ELF flag bits. FIXME: There should probably be some
13180 sort of BFD interface for this. */
13181 if (mips_any_noreorder
)
13182 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_NOREORDER
;
13183 if (mips_pic
!= NO_PIC
)
13185 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_PIC
;
13186 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_CPIC
;
13189 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_CPIC
;
13191 /* Set MIPS ELF flags for ASEs. */
13192 if (file_ase_mips16
)
13193 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ARCH_ASE_M16
;
13194 #if 0 /* XXX FIXME */
13195 if (file_ase_mips3d
)
13196 elf_elfheader (stdoutput
)->e_flags
|= ???;
13199 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ARCH_ASE_MDMX
;
13201 /* Set the MIPS ELF ABI flags. */
13202 if (mips_abi
== O32_ABI
&& USE_E_MIPS_ABI_O32
)
13203 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_O32
;
13204 else if (mips_abi
== O64_ABI
)
13205 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_O64
;
13206 else if (mips_abi
== EABI_ABI
)
13208 if (!file_mips_gp32
)
13209 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_EABI64
;
13211 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_EABI32
;
13213 else if (mips_abi
== N32_ABI
)
13214 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ABI2
;
13216 /* Nothing to do for N64_ABI. */
13218 if (mips_32bitmode
)
13219 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_32BITMODE
;
13222 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */
13224 typedef struct proc
{
13226 symbolS
*func_end_sym
;
13227 unsigned long reg_mask
;
13228 unsigned long reg_offset
;
13229 unsigned long fpreg_mask
;
13230 unsigned long fpreg_offset
;
13231 unsigned long frame_offset
;
13232 unsigned long frame_reg
;
13233 unsigned long pc_reg
;
13236 static procS cur_proc
;
13237 static procS
*cur_proc_ptr
;
13238 static int numprocs
;
13240 /* Fill in an rs_align_code fragment. */
13243 mips_handle_align (fragS
*fragp
)
13245 if (fragp
->fr_type
!= rs_align_code
)
13248 if (mips_opts
.mips16
)
13250 static const unsigned char be_nop
[] = { 0x65, 0x00 };
13251 static const unsigned char le_nop
[] = { 0x00, 0x65 };
13256 bytes
= fragp
->fr_next
->fr_address
- fragp
->fr_address
- fragp
->fr_fix
;
13257 p
= fragp
->fr_literal
+ fragp
->fr_fix
;
13265 memcpy (p
, (target_big_endian
? be_nop
: le_nop
), 2);
13269 /* For mips32, a nop is a zero, which we trivially get by doing nothing. */
13273 md_obj_begin (void)
13280 /* check for premature end, nesting errors, etc */
13282 as_warn (_("missing .end at end of assembly"));
13291 if (*input_line_pointer
== '-')
13293 ++input_line_pointer
;
13296 if (!ISDIGIT (*input_line_pointer
))
13297 as_bad (_("expected simple number"));
13298 if (input_line_pointer
[0] == '0')
13300 if (input_line_pointer
[1] == 'x')
13302 input_line_pointer
+= 2;
13303 while (ISXDIGIT (*input_line_pointer
))
13306 val
|= hex_value (*input_line_pointer
++);
13308 return negative
? -val
: val
;
13312 ++input_line_pointer
;
13313 while (ISDIGIT (*input_line_pointer
))
13316 val
|= *input_line_pointer
++ - '0';
13318 return negative
? -val
: val
;
13321 if (!ISDIGIT (*input_line_pointer
))
13323 printf (_(" *input_line_pointer == '%c' 0x%02x\n"),
13324 *input_line_pointer
, *input_line_pointer
);
13325 as_warn (_("invalid number"));
13328 while (ISDIGIT (*input_line_pointer
))
13331 val
+= *input_line_pointer
++ - '0';
13333 return negative
? -val
: val
;
13336 /* The .file directive; just like the usual .file directive, but there
13337 is an initial number which is the ECOFF file index. In the non-ECOFF
13338 case .file implies DWARF-2. */
13341 s_mips_file (int x ATTRIBUTE_UNUSED
)
13343 static int first_file_directive
= 0;
13345 if (ECOFF_DEBUGGING
)
13354 filename
= dwarf2_directive_file (0);
13356 /* Versions of GCC up to 3.1 start files with a ".file"
13357 directive even for stabs output. Make sure that this
13358 ".file" is handled. Note that you need a version of GCC
13359 after 3.1 in order to support DWARF-2 on MIPS. */
13360 if (filename
!= NULL
&& ! first_file_directive
)
13362 (void) new_logical_line (filename
, -1);
13363 s_app_file_string (filename
, 0);
13365 first_file_directive
= 1;
13369 /* The .loc directive, implying DWARF-2. */
13372 s_mips_loc (int x ATTRIBUTE_UNUSED
)
13374 if (!ECOFF_DEBUGGING
)
13375 dwarf2_directive_loc (0);
13378 /* The .end directive. */
13381 s_mips_end (int x ATTRIBUTE_UNUSED
)
13385 /* Following functions need their own .frame and .cprestore directives. */
13386 mips_frame_reg_valid
= 0;
13387 mips_cprestore_valid
= 0;
13389 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
13392 demand_empty_rest_of_line ();
13397 if ((bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) == 0)
13398 as_warn (_(".end not in text section"));
13402 as_warn (_(".end directive without a preceding .ent directive."));
13403 demand_empty_rest_of_line ();
13409 assert (S_GET_NAME (p
));
13410 if (strcmp (S_GET_NAME (p
), S_GET_NAME (cur_proc_ptr
->func_sym
)))
13411 as_warn (_(".end symbol does not match .ent symbol."));
13413 if (debug_type
== DEBUG_STABS
)
13414 stabs_generate_asm_endfunc (S_GET_NAME (p
),
13418 as_warn (_(".end directive missing or unknown symbol"));
13421 /* Create an expression to calculate the size of the function. */
13422 if (p
&& cur_proc_ptr
)
13424 OBJ_SYMFIELD_TYPE
*obj
= symbol_get_obj (p
);
13425 expressionS
*exp
= xmalloc (sizeof (expressionS
));
13428 exp
->X_op
= O_subtract
;
13429 exp
->X_add_symbol
= symbol_temp_new_now ();
13430 exp
->X_op_symbol
= p
;
13431 exp
->X_add_number
= 0;
13433 cur_proc_ptr
->func_end_sym
= exp
->X_add_symbol
;
13436 /* Generate a .pdr section. */
13437 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
&& ! ECOFF_DEBUGGING
13440 segT saved_seg
= now_seg
;
13441 subsegT saved_subseg
= now_subseg
;
13446 dot
= frag_now_fix ();
13448 #ifdef md_flush_pending_output
13449 md_flush_pending_output ();
13453 subseg_set (pdr_seg
, 0);
13455 /* Write the symbol. */
13456 exp
.X_op
= O_symbol
;
13457 exp
.X_add_symbol
= p
;
13458 exp
.X_add_number
= 0;
13459 emit_expr (&exp
, 4);
13461 fragp
= frag_more (7 * 4);
13463 md_number_to_chars (fragp
, cur_proc_ptr
->reg_mask
, 4);
13464 md_number_to_chars (fragp
+ 4, cur_proc_ptr
->reg_offset
, 4);
13465 md_number_to_chars (fragp
+ 8, cur_proc_ptr
->fpreg_mask
, 4);
13466 md_number_to_chars (fragp
+ 12, cur_proc_ptr
->fpreg_offset
, 4);
13467 md_number_to_chars (fragp
+ 16, cur_proc_ptr
->frame_offset
, 4);
13468 md_number_to_chars (fragp
+ 20, cur_proc_ptr
->frame_reg
, 4);
13469 md_number_to_chars (fragp
+ 24, cur_proc_ptr
->pc_reg
, 4);
13471 subseg_set (saved_seg
, saved_subseg
);
13473 #endif /* OBJ_ELF */
13475 cur_proc_ptr
= NULL
;
13478 /* The .aent and .ent directives. */
13481 s_mips_ent (int aent
)
13485 symbolP
= get_symbol ();
13486 if (*input_line_pointer
== ',')
13487 ++input_line_pointer
;
13488 SKIP_WHITESPACE ();
13489 if (ISDIGIT (*input_line_pointer
)
13490 || *input_line_pointer
== '-')
13493 if ((bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) == 0)
13494 as_warn (_(".ent or .aent not in text section."));
13496 if (!aent
&& cur_proc_ptr
)
13497 as_warn (_("missing .end"));
13501 /* This function needs its own .frame and .cprestore directives. */
13502 mips_frame_reg_valid
= 0;
13503 mips_cprestore_valid
= 0;
13505 cur_proc_ptr
= &cur_proc
;
13506 memset (cur_proc_ptr
, '\0', sizeof (procS
));
13508 cur_proc_ptr
->func_sym
= symbolP
;
13510 symbol_get_bfdsym (symbolP
)->flags
|= BSF_FUNCTION
;
13514 if (debug_type
== DEBUG_STABS
)
13515 stabs_generate_asm_func (S_GET_NAME (symbolP
),
13516 S_GET_NAME (symbolP
));
13519 demand_empty_rest_of_line ();
13522 /* The .frame directive. If the mdebug section is present (IRIX 5 native)
13523 then ecoff.c (ecoff_directive_frame) is used. For embedded targets,
13524 s_mips_frame is used so that we can set the PDR information correctly.
13525 We can't use the ecoff routines because they make reference to the ecoff
13526 symbol table (in the mdebug section). */
13529 s_mips_frame (int ignore ATTRIBUTE_UNUSED
)
13532 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
&& ! ECOFF_DEBUGGING
)
13536 if (cur_proc_ptr
== (procS
*) NULL
)
13538 as_warn (_(".frame outside of .ent"));
13539 demand_empty_rest_of_line ();
13543 cur_proc_ptr
->frame_reg
= tc_get_register (1);
13545 SKIP_WHITESPACE ();
13546 if (*input_line_pointer
++ != ','
13547 || get_absolute_expression_and_terminator (&val
) != ',')
13549 as_warn (_("Bad .frame directive"));
13550 --input_line_pointer
;
13551 demand_empty_rest_of_line ();
13555 cur_proc_ptr
->frame_offset
= val
;
13556 cur_proc_ptr
->pc_reg
= tc_get_register (0);
13558 demand_empty_rest_of_line ();
13561 #endif /* OBJ_ELF */
13565 /* The .fmask and .mask directives. If the mdebug section is present
13566 (IRIX 5 native) then ecoff.c (ecoff_directive_mask) is used. For
13567 embedded targets, s_mips_mask is used so that we can set the PDR
13568 information correctly. We can't use the ecoff routines because they
13569 make reference to the ecoff symbol table (in the mdebug section). */
13572 s_mips_mask (int reg_type
)
13575 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
&& ! ECOFF_DEBUGGING
)
13579 if (cur_proc_ptr
== (procS
*) NULL
)
13581 as_warn (_(".mask/.fmask outside of .ent"));
13582 demand_empty_rest_of_line ();
13586 if (get_absolute_expression_and_terminator (&mask
) != ',')
13588 as_warn (_("Bad .mask/.fmask directive"));
13589 --input_line_pointer
;
13590 demand_empty_rest_of_line ();
13594 off
= get_absolute_expression ();
13596 if (reg_type
== 'F')
13598 cur_proc_ptr
->fpreg_mask
= mask
;
13599 cur_proc_ptr
->fpreg_offset
= off
;
13603 cur_proc_ptr
->reg_mask
= mask
;
13604 cur_proc_ptr
->reg_offset
= off
;
13607 demand_empty_rest_of_line ();
13610 #endif /* OBJ_ELF */
13611 s_ignore (reg_type
);
13614 /* A table describing all the processors gas knows about. Names are
13615 matched in the order listed.
13617 To ease comparison, please keep this table in the same order as
13618 gcc's mips_cpu_info_table[]. */
13619 static const struct mips_cpu_info mips_cpu_info_table
[] =
13621 /* Entries for generic ISAs */
13622 { "mips1", 1, ISA_MIPS1
, CPU_R3000
},
13623 { "mips2", 1, ISA_MIPS2
, CPU_R6000
},
13624 { "mips3", 1, ISA_MIPS3
, CPU_R4000
},
13625 { "mips4", 1, ISA_MIPS4
, CPU_R8000
},
13626 { "mips5", 1, ISA_MIPS5
, CPU_MIPS5
},
13627 { "mips32", 1, ISA_MIPS32
, CPU_MIPS32
},
13628 { "mips32r2", 1, ISA_MIPS32R2
, CPU_MIPS32R2
},
13629 { "mips64", 1, ISA_MIPS64
, CPU_MIPS64
},
13630 { "mips64r2", 1, ISA_MIPS64R2
, CPU_MIPS64R2
},
13633 { "r3000", 0, ISA_MIPS1
, CPU_R3000
},
13634 { "r2000", 0, ISA_MIPS1
, CPU_R3000
},
13635 { "r3900", 0, ISA_MIPS1
, CPU_R3900
},
13638 { "r6000", 0, ISA_MIPS2
, CPU_R6000
},
13641 { "r4000", 0, ISA_MIPS3
, CPU_R4000
},
13642 { "r4010", 0, ISA_MIPS2
, CPU_R4010
},
13643 { "vr4100", 0, ISA_MIPS3
, CPU_VR4100
},
13644 { "vr4111", 0, ISA_MIPS3
, CPU_R4111
},
13645 { "vr4120", 0, ISA_MIPS3
, CPU_VR4120
},
13646 { "vr4130", 0, ISA_MIPS3
, CPU_VR4120
},
13647 { "vr4181", 0, ISA_MIPS3
, CPU_R4111
},
13648 { "vr4300", 0, ISA_MIPS3
, CPU_R4300
},
13649 { "r4400", 0, ISA_MIPS3
, CPU_R4400
},
13650 { "r4600", 0, ISA_MIPS3
, CPU_R4600
},
13651 { "orion", 0, ISA_MIPS3
, CPU_R4600
},
13652 { "r4650", 0, ISA_MIPS3
, CPU_R4650
},
13655 { "r8000", 0, ISA_MIPS4
, CPU_R8000
},
13656 { "r10000", 0, ISA_MIPS4
, CPU_R10000
},
13657 { "r12000", 0, ISA_MIPS4
, CPU_R12000
},
13658 { "vr5000", 0, ISA_MIPS4
, CPU_R5000
},
13659 { "vr5400", 0, ISA_MIPS4
, CPU_VR5400
},
13660 { "vr5500", 0, ISA_MIPS4
, CPU_VR5500
},
13661 { "rm5200", 0, ISA_MIPS4
, CPU_R5000
},
13662 { "rm5230", 0, ISA_MIPS4
, CPU_R5000
},
13663 { "rm5231", 0, ISA_MIPS4
, CPU_R5000
},
13664 { "rm5261", 0, ISA_MIPS4
, CPU_R5000
},
13665 { "rm5721", 0, ISA_MIPS4
, CPU_R5000
},
13666 { "rm7000", 0, ISA_MIPS4
, CPU_RM7000
},
13667 { "rm9000", 0, ISA_MIPS4
, CPU_RM9000
},
13670 { "4kc", 0, ISA_MIPS32
, CPU_MIPS32
},
13671 { "4km", 0, ISA_MIPS32
, CPU_MIPS32
},
13672 { "4kp", 0, ISA_MIPS32
, CPU_MIPS32
},
13675 { "5kc", 0, ISA_MIPS64
, CPU_MIPS64
},
13676 { "20kc", 0, ISA_MIPS64
, CPU_MIPS64
},
13678 /* Broadcom SB-1 CPU core */
13679 { "sb1", 0, ISA_MIPS64
, CPU_SB1
},
13686 /* Return true if GIVEN is the same as CANONICAL, or if it is CANONICAL
13687 with a final "000" replaced by "k". Ignore case.
13689 Note: this function is shared between GCC and GAS. */
13692 mips_strict_matching_cpu_name_p (const char *canonical
, const char *given
)
13694 while (*given
!= 0 && TOLOWER (*given
) == TOLOWER (*canonical
))
13695 given
++, canonical
++;
13697 return ((*given
== 0 && *canonical
== 0)
13698 || (strcmp (canonical
, "000") == 0 && strcasecmp (given
, "k") == 0));
13702 /* Return true if GIVEN matches CANONICAL, where GIVEN is a user-supplied
13703 CPU name. We've traditionally allowed a lot of variation here.
13705 Note: this function is shared between GCC and GAS. */
13708 mips_matching_cpu_name_p (const char *canonical
, const char *given
)
13710 /* First see if the name matches exactly, or with a final "000"
13711 turned into "k". */
13712 if (mips_strict_matching_cpu_name_p (canonical
, given
))
13715 /* If not, try comparing based on numerical designation alone.
13716 See if GIVEN is an unadorned number, or 'r' followed by a number. */
13717 if (TOLOWER (*given
) == 'r')
13719 if (!ISDIGIT (*given
))
13722 /* Skip over some well-known prefixes in the canonical name,
13723 hoping to find a number there too. */
13724 if (TOLOWER (canonical
[0]) == 'v' && TOLOWER (canonical
[1]) == 'r')
13726 else if (TOLOWER (canonical
[0]) == 'r' && TOLOWER (canonical
[1]) == 'm')
13728 else if (TOLOWER (canonical
[0]) == 'r')
13731 return mips_strict_matching_cpu_name_p (canonical
, given
);
13735 /* Parse an option that takes the name of a processor as its argument.
13736 OPTION is the name of the option and CPU_STRING is the argument.
13737 Return the corresponding processor enumeration if the CPU_STRING is
13738 recognized, otherwise report an error and return null.
13740 A similar function exists in GCC. */
13742 static const struct mips_cpu_info
*
13743 mips_parse_cpu (const char *option
, const char *cpu_string
)
13745 const struct mips_cpu_info
*p
;
13747 /* 'from-abi' selects the most compatible architecture for the given
13748 ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit ABIs. For the
13749 EABIs, we have to decide whether we're using the 32-bit or 64-bit
13750 version. Look first at the -mgp options, if given, otherwise base
13751 the choice on MIPS_DEFAULT_64BIT.
13753 Treat NO_ABI like the EABIs. One reason to do this is that the
13754 plain 'mips' and 'mips64' configs have 'from-abi' as their default
13755 architecture. This code picks MIPS I for 'mips' and MIPS III for
13756 'mips64', just as we did in the days before 'from-abi'. */
13757 if (strcasecmp (cpu_string
, "from-abi") == 0)
13759 if (ABI_NEEDS_32BIT_REGS (mips_abi
))
13760 return mips_cpu_info_from_isa (ISA_MIPS1
);
13762 if (ABI_NEEDS_64BIT_REGS (mips_abi
))
13763 return mips_cpu_info_from_isa (ISA_MIPS3
);
13765 if (file_mips_gp32
>= 0)
13766 return mips_cpu_info_from_isa (file_mips_gp32
? ISA_MIPS1
: ISA_MIPS3
);
13768 return mips_cpu_info_from_isa (MIPS_DEFAULT_64BIT
13773 /* 'default' has traditionally been a no-op. Probably not very useful. */
13774 if (strcasecmp (cpu_string
, "default") == 0)
13777 for (p
= mips_cpu_info_table
; p
->name
!= 0; p
++)
13778 if (mips_matching_cpu_name_p (p
->name
, cpu_string
))
13781 as_bad ("Bad value (%s) for %s", cpu_string
, option
);
13785 /* Return the canonical processor information for ISA (a member of the
13786 ISA_MIPS* enumeration). */
13788 static const struct mips_cpu_info
*
13789 mips_cpu_info_from_isa (int isa
)
13793 for (i
= 0; mips_cpu_info_table
[i
].name
!= NULL
; i
++)
13794 if (mips_cpu_info_table
[i
].is_isa
13795 && isa
== mips_cpu_info_table
[i
].isa
)
13796 return (&mips_cpu_info_table
[i
]);
13801 static const struct mips_cpu_info
*
13802 mips_cpu_info_from_arch (int arch
)
13806 for (i
= 0; mips_cpu_info_table
[i
].name
!= NULL
; i
++)
13807 if (arch
== mips_cpu_info_table
[i
].cpu
)
13808 return (&mips_cpu_info_table
[i
]);
13814 show (FILE *stream
, const char *string
, int *col_p
, int *first_p
)
13818 fprintf (stream
, "%24s", "");
13823 fprintf (stream
, ", ");
13827 if (*col_p
+ strlen (string
) > 72)
13829 fprintf (stream
, "\n%24s", "");
13833 fprintf (stream
, "%s", string
);
13834 *col_p
+= strlen (string
);
13840 md_show_usage (FILE *stream
)
13845 fprintf (stream
, _("\
13847 -EB generate big endian output\n\
13848 -EL generate little endian output\n\
13849 -g, -g2 do not remove unneeded NOPs or swap branches\n\
13850 -G NUM allow referencing objects up to NUM bytes\n\
13851 implicitly with the gp register [default 8]\n"));
13852 fprintf (stream
, _("\
13853 -mips1 generate MIPS ISA I instructions\n\
13854 -mips2 generate MIPS ISA II instructions\n\
13855 -mips3 generate MIPS ISA III instructions\n\
13856 -mips4 generate MIPS ISA IV instructions\n\
13857 -mips5 generate MIPS ISA V instructions\n\
13858 -mips32 generate MIPS32 ISA instructions\n\
13859 -mips32r2 generate MIPS32 release 2 ISA instructions\n\
13860 -mips64 generate MIPS64 ISA instructions\n\
13861 -mips64r2 generate MIPS64 release 2 ISA instructions\n\
13862 -march=CPU/-mtune=CPU generate code/schedule for CPU, where CPU is one of:\n"));
13866 for (i
= 0; mips_cpu_info_table
[i
].name
!= NULL
; i
++)
13867 show (stream
, mips_cpu_info_table
[i
].name
, &column
, &first
);
13868 show (stream
, "from-abi", &column
, &first
);
13869 fputc ('\n', stream
);
13871 fprintf (stream
, _("\
13872 -mCPU equivalent to -march=CPU -mtune=CPU. Deprecated.\n\
13873 -no-mCPU don't generate code specific to CPU.\n\
13874 For -mCPU and -no-mCPU, CPU must be one of:\n"));
13878 show (stream
, "3900", &column
, &first
);
13879 show (stream
, "4010", &column
, &first
);
13880 show (stream
, "4100", &column
, &first
);
13881 show (stream
, "4650", &column
, &first
);
13882 fputc ('\n', stream
);
13884 fprintf (stream
, _("\
13885 -mips16 generate mips16 instructions\n\
13886 -no-mips16 do not generate mips16 instructions\n"));
13887 fprintf (stream
, _("\
13888 -mfix-vr4120 work around certain VR4120 errata\n\
13889 -mgp32 use 32-bit GPRs, regardless of the chosen ISA\n\
13890 -mfp32 use 32-bit FPRs, regardless of the chosen ISA\n\
13891 -mno-shared optimize output for executables\n\
13892 -msym32 assume all symbols have 32-bit values\n\
13893 -O0 remove unneeded NOPs, do not swap branches\n\
13894 -O remove unneeded NOPs and swap branches\n\
13895 --[no-]construct-floats [dis]allow floating point values to be constructed\n\
13896 --trap, --no-break trap exception on div by 0 and mult overflow\n\
13897 --break, --no-trap break exception on div by 0 and mult overflow\n"));
13899 fprintf (stream
, _("\
13900 -KPIC, -call_shared generate SVR4 position independent code\n\
13901 -non_shared do not generate position independent code\n\
13902 -xgot assume a 32 bit GOT\n\
13903 -mpdr, -mno-pdr enable/disable creation of .pdr sections\n\
13904 -mshared, -mno-shared disable/enable .cpload optimization for\n\
13906 -mabi=ABI create ABI conformant object file for:\n"));
13910 show (stream
, "32", &column
, &first
);
13911 show (stream
, "o64", &column
, &first
);
13912 show (stream
, "n32", &column
, &first
);
13913 show (stream
, "64", &column
, &first
);
13914 show (stream
, "eabi", &column
, &first
);
13916 fputc ('\n', stream
);
13918 fprintf (stream
, _("\
13919 -32 create o32 ABI object file (default)\n\
13920 -n32 create n32 ABI object file\n\
13921 -64 create 64 ABI object file\n"));
13926 mips_dwarf2_format (void)
13928 if (mips_abi
== N64_ABI
)
13931 return dwarf2_format_64bit_irix
;
13933 return dwarf2_format_64bit
;
13937 return dwarf2_format_32bit
;
13941 mips_dwarf2_addr_size (void)
13943 if (mips_abi
== N64_ABI
)