1 /* tc-mips.c -- assemble code for a MIPS chip.
2 Copyright (C) 1993 Free Software Foundation, Inc.
3 Contributed by the OSF and Ralph Campbell.
4 Written by Keith Knowles and Ralph Campbell, working independently.
5 Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus
8 This file is part of GAS.
10 GAS is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 2, or (at your option)
15 GAS is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with GAS; see the file COPYING. If not, write to
22 the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */
40 #endif /* NO_VARARGS */
41 #endif /* NO_STDARG */
43 #include "opcode/mips.h"
48 static char *mips_regmask_frag
;
52 #define PIC_CALL_REG 25
58 /* Decide whether to do GP reference optimizations based on the object
68 /* The default target format to use. */
70 #ifdef TARGET_BYTES_BIG_ENDIAN
71 #define DEFAULT_TARGET_FORMAT "a.out-mips-big"
73 #define DEFAULT_TARGET_FORMAT "a.out-mips-little"
77 #ifdef TARGET_BYTES_BIG_ENDIAN
78 #define DEFAULT_TARGET_FORMAT "ecoff-bigmips"
80 #define DEFAULT_TARGET_FORMAT "ecoff-littlemips"
82 #endif /* OBJ_ECOFF */
84 #ifdef TARGET_BYTES_BIG_ENDIAN
85 #define DEFAULT_TARGET_FORMAT "elf32-bigmips"
87 #define DEFAULT_TARGET_FORMAT "elf32-littlemips"
91 const char *mips_target_format
= DEFAULT_TARGET_FORMAT
;
93 /* These variables are filled in with the masks of registers used.
94 The object format code reads them and puts them in the appropriate
96 unsigned long mips_gprmask
;
97 unsigned long mips_cprmask
[4];
99 /* MIPS ISA (Instruction Set Architecture) level (may be changed
100 temporarily using .set mipsN). */
101 static int mips_isa
= -1;
103 /* MIPS ISA we are using for this output file. */
104 static int file_mips_isa
;
106 /* MIPS PIC level. */
110 /* Do not generate PIC code. */
113 /* Generate PIC code as in Irix 4. This is not implemented, and I'm
114 not sure what it is supposed to do. */
117 /* Generate PIC code as in the SVR4 MIPS ABI. */
120 /* Generate PIC code without using a global offset table: the data
121 segment has a maximum size of 64K, all data references are off
122 the $gp register, and all text references are PC relative. This
123 is used on some embedded systems. */
127 static enum mips_pic_level mips_pic
;
129 /* 1 if trap instructions should used for overflow rather than break
131 static int mips_trap
;
133 static int mips_warn_about_macros
;
134 static int mips_noreorder
;
135 static int mips_any_noreorder
;
136 static int mips_nomove
;
137 static int mips_noat
;
138 static int mips_nobopt
;
141 /* The size of the small data section. */
142 static int g_switch_value
= 8;
143 /* Whether the -G option was used. */
144 static int g_switch_seen
= 0;
150 /* handle of the OPCODE hash table */
151 static struct hash_control
*op_hash
= NULL
;
153 /* This array holds the chars that always start a comment. If the
154 pre-processor is disabled, these aren't very useful */
155 const char comment_chars
[] = "#";
157 /* This array holds the chars that only start a comment at the beginning of
158 a line. If the line seems to have the form '# 123 filename'
159 .line and .file directives will appear in the pre-processed output */
160 /* Note that input_file.c hand checks for '#' at the beginning of the
161 first line of the input file. This is because the compiler outputs
162 #NO_APP at the beginning of its output. */
163 /* Also note that C style comments are always supported. */
164 const char line_comment_chars
[] = "#";
166 /* This array holds machine specific line separator characters. */
167 const char line_separator_chars
[] = "";
169 /* Chars that can be used to separate mant from exp in floating point nums */
170 const char EXP_CHARS
[] = "eE";
172 /* Chars that mean this number is a floating point constant */
175 const char FLT_CHARS
[] = "rRsSfFdDxXpP";
177 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
178 changed in read.c . Ideally it shouldn't have to know about it at all,
179 but nothing is ideal around here.
182 static char *insn_error
;
184 static int byte_order
= BYTE_ORDER
;
186 static int auto_align
= 1;
188 /* Symbol labelling the current insn. */
189 static symbolS
*insn_label
;
191 /* When outputting SVR4 PIC code, the assembler needs to know the
192 offset in the stack frame from which to restore the $gp register.
193 This is set by the .cprestore pseudo-op, and saved in this
195 static offsetT mips_cprestore_offset
= -1;
197 /* This is the register which holds the stack frame, as set by the
198 .frame pseudo-op. This is needed to implement .cprestore. */
199 static int mips_frame_reg
= SP
;
201 /* To output NOP instructions correctly, we need to keep information
202 about the previous two instructions. */
204 /* Whether we are optimizing. The default value of 2 means to remove
205 unneeded NOPs and swap branch instructions when possible. A value
206 of 1 means to not swap branches. A value of 0 means to always
208 static int mips_optimize
= 2;
210 /* The previous instruction. */
211 static struct mips_cl_insn prev_insn
;
213 /* The instruction before prev_insn. */
214 static struct mips_cl_insn prev_prev_insn
;
216 /* If we don't want information for prev_insn or prev_prev_insn, we
217 point the insn_mo field at this dummy integer. */
218 static const struct mips_opcode dummy_opcode
= { 0 };
220 /* Non-zero if prev_insn is valid. */
221 static int prev_insn_valid
;
223 /* The frag for the previous instruction. */
224 static struct frag
*prev_insn_frag
;
226 /* The offset into prev_insn_frag for the previous instruction. */
227 static long prev_insn_where
;
229 /* The reloc for the previous instruction, if any. */
230 static fixS
*prev_insn_fixp
;
232 /* Non-zero if the previous instruction was in a delay slot. */
233 static int prev_insn_is_delay_slot
;
235 /* Non-zero if the previous instruction was in a .set noreorder. */
236 static int prev_insn_unreordered
;
238 /* Non-zero if the previous previous instruction was in a .set
240 static int prev_prev_insn_unreordered
;
242 /* Since the MIPS does not have multiple forms of PC relative
243 instructions, we do not have to do relaxing as is done on other
244 platforms. However, we do have to handle GP relative addressing
245 correctly, which turns out to be a similar problem.
247 Every macro that refers to a symbol can occur in (at least) two
248 forms, one with GP relative addressing and one without. For
249 example, loading a global variable into a register generally uses
250 a macro instruction like this:
252 If i can be addressed off the GP register (this is true if it is in
253 the .sbss or .sdata section, or if it is known to be smaller than
254 the -G argument) this will generate the following instruction:
256 This instruction will use a GPREL reloc. If i can not be addressed
257 off the GP register, the following instruction sequence will be used:
260 In this case the first instruction will have a HI16 reloc, and the
261 second reloc will have a LO16 reloc. Both relocs will be against
264 The issue here is that we may not know whether i is GP addressable
265 until after we see the instruction that uses it. Therefore, we
266 want to be able to choose the final instruction sequence only at
267 the end of the assembly. This is similar to the way other
268 platforms choose the size of a PC relative instruction only at the
271 When generating position independent code we do not use GP
272 addressing in quite the same way, but the issue still arises as
273 external symbols and local symbols must be handled differently.
275 We handle these issues by actually generating both possible
276 instruction sequences. The longer one is put in a frag_var with
277 type rs_machine_dependent. We encode what to do with the frag in
278 the subtype field. We encode (1) the number of existing bytes to
279 replace, (2) the number of new bytes to use, (3) the offset from
280 the start of the existing bytes to the first reloc we must generate
281 (that is, the offset is applied from the start of the existing
282 bytes after they are replaced by the new bytes, if any), (4) the
283 offset from the start of the existing bytes to the second reloc,
284 (5) whether a third reloc is needed (the third reloc is always four
285 bytes after the second reloc), and (6) whether to warn if this
286 variant is used (this is sometimes needed if .set nomacro or .set
287 noat is in effect). All these numbers are reasonably small.
289 Generating two instruction sequences must be handled carefully to
290 ensure that delay slots are handled correctly. Fortunately, there
291 are a limited number of cases. When the second instruction
292 sequence is generated, append_insn is directed to maintain the
293 existing delay slot information, so it continues to apply to any
294 code after the second instruction sequence. This means that the
295 second instruction sequence must not impose any requirements not
296 required by the first instruction sequence.
298 These variant frags are then handled in functions called by the
299 machine independent code. md_estimate_size_before_relax returns
300 the final size of the frag. md_convert_frag sets up the final form
301 of the frag. tc_gen_reloc adjust the first reloc and adds a second
303 #define RELAX_ENCODE(old, new, reloc1, reloc2, reloc3, warn) \
307 | (((reloc1) + 64) << 9) \
308 | (((reloc2) + 64) << 2) \
309 | ((reloc3) ? (1 << 1) : 0) \
311 #define RELAX_OLD(i) (((i) >> 24) & 0xff)
312 #define RELAX_NEW(i) (((i) >> 16) & 0xff)
313 #define RELAX_RELOC1(i) ((((i) >> 9) & 0x7f) - 64)
314 #define RELAX_RELOC2(i) ((((i) >> 2) & 0x7f) - 64)
315 #define RELAX_RELOC3(i) (((i) >> 1) & 1)
316 #define RELAX_WARN(i) ((i) & 1)
318 /* Prototypes for static functions. */
321 #define internalError() \
322 as_fatal ("internal Error, line %d, %s", __LINE__, __FILE__)
324 #define internalError() as_fatal ("MIPS internal Error");
327 static int insn_uses_reg
PARAMS ((struct mips_cl_insn
*ip
,
328 unsigned int reg
, int fpr
));
329 static void append_insn
PARAMS ((char *place
,
330 struct mips_cl_insn
* ip
,
332 bfd_reloc_code_real_type r
));
333 static void mips_no_prev_insn
PARAMS ((void));
334 static void mips_emit_delays
PARAMS ((void));
335 static void macro_build
PARAMS ((char *place
, int *counter
, expressionS
* ep
,
336 const char *name
, const char *fmt
,
338 static void macro_build_lui
PARAMS ((char *place
, int *counter
,
339 expressionS
* ep
, int regnum
));
340 static void set_at
PARAMS ((int *counter
, int reg
, int unsignedp
));
341 static void check_absolute_expr
PARAMS ((struct mips_cl_insn
* ip
,
343 static void load_register
PARAMS ((int *counter
, int reg
, expressionS
* ep
));
344 static void load_address
PARAMS ((int *counter
, int reg
, expressionS
*ep
));
345 static void macro
PARAMS ((struct mips_cl_insn
* ip
));
346 #ifdef LOSING_COMPILER
347 static void macro2
PARAMS ((struct mips_cl_insn
* ip
));
349 static void mips_ip
PARAMS ((char *str
, struct mips_cl_insn
* ip
));
350 static int my_getSmallExpression
PARAMS ((expressionS
* ep
, char *str
));
351 static void my_getExpression
PARAMS ((expressionS
* ep
, char *str
));
352 static symbolS
*get_symbol
PARAMS ((void));
353 static void mips_align
PARAMS ((int to
, int fill
, symbolS
*label
));
354 static void s_align
PARAMS ((int));
355 static void s_stringer
PARAMS ((int));
356 static void s_change_sec
PARAMS ((int));
357 static void s_cons
PARAMS ((int));
358 static void s_err
PARAMS ((int));
359 static void s_extern
PARAMS ((int));
360 static void s_float_cons
PARAMS ((int));
361 static void s_option
PARAMS ((int));
362 static void s_mipsset
PARAMS ((int));
363 static void s_mips_space
PARAMS ((int));
364 static void s_abicalls
PARAMS ((int));
365 static void s_cpload
PARAMS ((int));
366 static void s_cprestore
PARAMS ((int));
367 static void s_gpword
PARAMS ((int));
368 static void s_cpadd
PARAMS ((int));
369 #ifndef ECOFF_DEBUGGING
370 static void md_obj_begin
PARAMS ((void));
371 static void md_obj_end
PARAMS ((void));
372 static long get_number
PARAMS ((void));
373 static void s_ent
PARAMS ((int));
374 static void s_mipsend
PARAMS ((int));
375 static void s_file
PARAMS ((int));
377 static void s_frame
PARAMS ((int));
378 static void s_loc
PARAMS ((int));
379 static void s_mask
PARAMS ((char));
385 The following pseudo-ops from the Kane and Heinrich MIPS book
386 should be defined here, but are currently unsupported: .alias,
387 .galive, .gjaldef, .gjrlive, .livereg, .noalias.
389 The following pseudo-ops from the Kane and Heinrich MIPS book are
390 specific to the type of debugging information being generated, and
391 should be defined by the object format: .aent, .begin, .bend,
392 .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp,
395 The following pseudo-ops from the Kane and Heinrich MIPS book are
396 not MIPS CPU specific, but are also not specific to the object file
397 format. This file is probably the best place to define them, but
398 they are not currently supported: .asm0, .endr, .lab, .repeat,
399 .struct, .weakext. */
401 const pseudo_typeS md_pseudo_table
[] =
403 /* MIPS specific pseudo-ops. */
404 {"option", s_option
, 0},
405 {"set", s_mipsset
, 0},
406 {"rdata", s_change_sec
, 'r'},
407 {"sdata", s_change_sec
, 's'},
408 {"livereg", s_ignore
, 0},
409 { "abicalls", s_abicalls
, 0},
410 { "cpload", s_cpload
, 0},
411 { "cprestore", s_cprestore
, 0},
412 { "gpword", s_gpword
, 0},
413 { "cpadd", s_cpadd
, 0},
415 /* Relatively generic pseudo-ops that happen to be used on MIPS
417 {"asciiz", s_stringer
, 1},
418 {"bss", s_change_sec
, 'b'},
421 {"dword", s_cons
, 3},
423 /* These pseudo-ops are defined in read.c, but must be overridden
424 here for one reason or another. */
425 {"align", s_align
, 0},
426 {"ascii", s_stringer
, 0},
427 {"asciz", s_stringer
, 1},
429 {"data", s_change_sec
, 'd'},
430 {"double", s_float_cons
, 'd'},
431 {"extern", s_extern
, 0},
432 {"float", s_float_cons
, 'f'},
433 {"hword", s_cons
, 1},
438 {"short", s_cons
, 1},
439 {"single", s_float_cons
, 'f'},
440 {"space", s_mips_space
, 0},
441 {"text", s_change_sec
, 't'},
444 #ifndef ECOFF_DEBUGGING
445 /* These pseudo-ops should be defined by the object file format.
446 However, a.out doesn't support them, so we have versions here. */
448 {"bgnb", s_ignore
, 0},
449 {"end", s_mipsend
, 0},
450 {"endb", s_ignore
, 0},
453 {"fmask", s_ignore
, 'F'},
454 {"frame", s_ignore
, 0},
455 {"loc", s_ignore
, 0},
456 {"mask", s_ignore
, 'R'},
457 {"verstamp", s_ignore
, 0},
464 const relax_typeS md_relax_table
[] =
469 static char *expr_end
;
471 static expressionS imm_expr
;
472 static expressionS offset_expr
;
473 static bfd_reloc_code_real_type imm_reloc
;
474 static bfd_reloc_code_real_type offset_reloc
;
476 /* FIXME: This should be handled in a different way. */
477 extern int target_big_endian
;
480 * This function is called once, at assembler startup time. It should
481 * set up all the tables, etc. that the MD part of the assembler will need.
487 register const char *retval
= NULL
;
488 register unsigned int i
= 0;
492 if (strcmp (TARGET_CPU
, "mips") == 0)
494 else if (strcmp (TARGET_CPU
, "r6000") == 0
495 || strcmp (TARGET_CPU
, "mips2") == 0)
497 else if (strcmp (TARGET_CPU
, "mips64") == 0
498 || strcmp (TARGET_CPU
, "r4000") == 0
499 || strcmp (TARGET_CPU
, "mips3") == 0)
505 if (mips_isa
< 2 && mips_trap
)
506 as_bad ("trap exception not supported at ISA 1");
511 ok
= bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, 3000);
514 ok
= bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, 6000);
517 ok
= bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, 4000);
521 as_warn ("Could not set architecture and machine");
523 file_mips_isa
= mips_isa
;
525 op_hash
= hash_new ();
527 for (i
= 0; i
< NUMOPCODES
;)
529 const char *name
= mips_opcodes
[i
].name
;
531 retval
= hash_insert (op_hash
, name
, (PTR
) &mips_opcodes
[i
]);
534 fprintf (stderr
, "internal error: can't hash `%s': %s\n",
535 mips_opcodes
[i
].name
, retval
);
536 as_fatal ("Broken assembler. No assembly attempted.");
540 if (mips_opcodes
[i
].pinfo
!= INSN_MACRO
541 && ((mips_opcodes
[i
].match
& mips_opcodes
[i
].mask
)
542 != mips_opcodes
[i
].match
))
544 fprintf (stderr
, "internal error: bad opcode: `%s' \"%s\"\n",
545 mips_opcodes
[i
].name
, mips_opcodes
[i
].args
);
546 as_fatal ("Broken assembler. No assembly attempted.");
550 while ((i
< NUMOPCODES
) && !strcmp (mips_opcodes
[i
].name
, name
));
553 mips_no_prev_insn ();
561 /* set the default alignment for the text section (2**2) */
562 record_alignment (text_section
, 2);
564 /* FIXME: This should be handled in a different way. */
565 target_big_endian
= byte_order
== BIG_ENDIAN
;
568 bfd_set_gp_size (stdoutput
, g_switch_value
);
572 /* Sections must be aligned to 16 byte boundaries. */
573 (void) bfd_set_section_alignment (stdoutput
, text_section
, 4);
574 (void) bfd_set_section_alignment (stdoutput
, data_section
, 4);
575 (void) bfd_set_section_alignment (stdoutput
, bss_section
, 4);
577 /* Create a .reginfo section for register masks and a .mdebug
578 section for debugging information. */
586 sec
= subseg_new (".reginfo", (subsegT
) 0);
588 /* The ABI says this section should be loaded so that the running
589 program can access it. */
590 (void) bfd_set_section_flags (stdoutput
, sec
,
591 (SEC_ALLOC
| SEC_LOAD
592 | SEC_READONLY
| SEC_DATA
));
593 (void) bfd_set_section_alignment (stdoutput
, sec
, 2);
595 mips_regmask_frag
= frag_more (sizeof (Elf32_External_RegInfo
));
597 #ifdef ECOFF_DEBUGGING
598 sec
= subseg_new (".mdebug", (subsegT
) 0);
599 (void) bfd_set_section_flags (stdoutput
, sec
,
600 SEC_HAS_CONTENTS
| SEC_READONLY
);
601 (void) bfd_set_section_alignment (stdoutput
, sec
, 2);
604 subseg_set (seg
, subseg
);
608 #ifndef ECOFF_DEBUGGING
616 #ifndef ECOFF_DEBUGGING
625 struct mips_cl_insn insn
;
627 imm_expr
.X_op
= O_absent
;
628 offset_expr
.X_op
= O_absent
;
630 mips_ip (str
, &insn
);
633 as_bad ("%s `%s'", insn_error
, str
);
636 if (insn
.insn_mo
->pinfo
== INSN_MACRO
)
642 if (imm_expr
.X_op
!= O_absent
)
643 append_insn ((char *) NULL
, &insn
, &imm_expr
, imm_reloc
);
644 else if (offset_expr
.X_op
!= O_absent
)
645 append_insn ((char *) NULL
, &insn
, &offset_expr
, offset_reloc
);
647 append_insn ((char *) NULL
, &insn
, NULL
, BFD_RELOC_UNUSED
);
651 /* See whether instruction IP reads register REG. If FPR is non-zero,
652 REG is a floating point register. */
655 insn_uses_reg (ip
, reg
, fpr
)
656 struct mips_cl_insn
*ip
;
660 /* Don't report on general register 0, since it never changes. */
661 if (! fpr
&& reg
== 0)
666 /* If we are called with either $f0 or $f1, we must check $f0.
667 This is not optimal, because it will introduce an unnecessary
668 NOP between "lwc1 $f0" and "swc1 $f1". To fix this we would
669 need to distinguish reading both $f0 and $f1 or just one of
670 them. Note that we don't have to check the other way,
671 because there is no instruction that sets both $f0 and $f1
672 and requires a delay. */
673 if ((ip
->insn_mo
->pinfo
& INSN_READ_FPR_S
)
674 && (((ip
->insn_opcode
>> OP_SH_FS
) & OP_MASK_FS
)
675 == (reg
&~ (unsigned) 1)))
677 if ((ip
->insn_mo
->pinfo
& INSN_READ_FPR_T
)
678 && (((ip
->insn_opcode
>> OP_SH_FT
) & OP_MASK_FT
)
679 == (reg
&~ (unsigned) 1)))
684 if ((ip
->insn_mo
->pinfo
& INSN_READ_GPR_S
)
685 && ((ip
->insn_opcode
>> OP_SH_RS
) & OP_MASK_RS
) == reg
)
687 if ((ip
->insn_mo
->pinfo
& INSN_READ_GPR_T
)
688 && ((ip
->insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
) == reg
)
695 /* Output an instruction. PLACE is where to put the instruction; if
696 it is NULL, this uses frag_more to get room. IP is the instruction
697 information. ADDRESS_EXPR is an operand of the instruction to be
698 used with RELOC_TYPE. */
701 append_insn (place
, ip
, address_expr
, reloc_type
)
703 struct mips_cl_insn
*ip
;
704 expressionS
*address_expr
;
705 bfd_reloc_code_real_type reloc_type
;
707 register unsigned long prev_pinfo
, pinfo
;
712 prev_pinfo
= prev_insn
.insn_mo
->pinfo
;
713 pinfo
= ip
->insn_mo
->pinfo
;
715 if (place
== NULL
&& ! mips_noreorder
)
717 /* If the previous insn required any delay slots, see if we need
718 to insert a NOP or two. There are eight kinds of possible
719 hazards, of which an instruction can have at most one type.
720 (1) a load from memory delay
721 (2) a load from a coprocessor delay
722 (3) an unconditional branch delay
723 (4) a conditional branch delay
724 (5) a move to coprocessor register delay
725 (6) a load coprocessor register from memory delay
726 (7) a coprocessor condition code delay
727 (8) a HI/LO special register delay
729 There are a lot of optimizations we could do that we don't.
730 In particular, we do not, in general, reorder instructions.
731 If you use gcc with optimization, it will reorder
732 instructions and generally do much more optimization then we
733 do here; repeating all that work in the assembler would only
734 benefit hand written assembly code, and does not seem worth
737 /* This is how a NOP is emitted. */
738 #define emit_nop() md_number_to_chars (frag_more (4), 0, 4)
740 /* The previous insn might require a delay slot, depending upon
741 the contents of the current insn. */
742 if ((prev_pinfo
& INSN_LOAD_COPROC_DELAY
)
744 && (prev_pinfo
& INSN_LOAD_MEMORY_DELAY
)))
746 /* A load from a coprocessor or from memory. All load
747 delays delay the use of general register rt for one
748 instruction on the r3000. The r6000 and r4000 use
750 know (prev_pinfo
& INSN_WRITE_GPR_T
);
751 if (mips_optimize
== 0
752 || insn_uses_reg (ip
,
753 ((prev_insn
.insn_opcode
>> OP_SH_RT
)
758 else if ((prev_pinfo
& INSN_COPROC_MOVE_DELAY
)
760 && (prev_pinfo
& INSN_COPROC_MEMORY_DELAY
)))
762 /* A generic coprocessor delay. The previous instruction
763 modified a coprocessor general or control register. If
764 it modified a control register, we need to avoid any
765 coprocessor instruction (this is probably not always
766 required, but it sometimes is). If it modified a general
767 register, we avoid using that register.
769 On the r6000 and r4000 loading a coprocessor register
770 from memory is interlocked, and does not require a delay.
772 This case is not handled very well. There is no special
773 knowledge of CP0 handling, and the coprocessors other
774 than the floating point unit are not distinguished at
776 if (prev_pinfo
& INSN_WRITE_FPR_T
)
778 if (mips_optimize
== 0
779 || insn_uses_reg (ip
,
780 ((prev_insn
.insn_opcode
>> OP_SH_FT
)
785 else if (prev_pinfo
& INSN_WRITE_FPR_S
)
787 if (mips_optimize
== 0
788 || insn_uses_reg (ip
,
789 ((prev_insn
.insn_opcode
>> OP_SH_FS
)
796 /* We don't know exactly what the previous instruction
797 does. If the current instruction uses a coprocessor
798 register, we must insert a NOP. If previous
799 instruction may set the condition codes, and the
800 current instruction uses them, we must insert two
802 if (mips_optimize
== 0
803 || ((prev_pinfo
& INSN_WRITE_COND_CODE
)
804 && (pinfo
& INSN_READ_COND_CODE
)))
806 else if (pinfo
& INSN_COP
)
810 else if (prev_pinfo
& INSN_WRITE_COND_CODE
)
812 /* The previous instruction sets the coprocessor condition
813 codes, but does not require a general coprocessor delay
814 (this means it is a floating point comparison
815 instruction). If this instruction uses the condition
816 codes, we need to insert a single NOP. */
817 if (mips_optimize
== 0
818 || (pinfo
& INSN_READ_COND_CODE
))
821 else if (prev_pinfo
& INSN_READ_LO
)
823 /* The previous instruction reads the LO register; if the
824 current instruction writes to the LO register, we must
826 if (mips_optimize
== 0
827 || (pinfo
& INSN_WRITE_LO
))
830 else if (prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
832 /* The previous instruction reads the HI register; if the
833 current instruction writes to the HI register, we must
835 if (mips_optimize
== 0
836 || (pinfo
& INSN_WRITE_HI
))
840 /* There are two cases which require two intervening
841 instructions: 1) setting the condition codes using a move to
842 coprocessor instruction which requires a general coprocessor
843 delay and then reading the condition codes 2) reading the HI
844 or LO register and then writing to it. If we are not already
845 emitting a NOP instruction, we must check for these cases
846 compared to the instruction previous to the previous
849 && (((prev_prev_insn
.insn_mo
->pinfo
& INSN_COPROC_MOVE_DELAY
)
850 && (prev_prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
)
851 && (pinfo
& INSN_READ_COND_CODE
))
852 || ((prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
)
853 && (pinfo
& INSN_WRITE_LO
))
854 || ((prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
855 && (pinfo
& INSN_WRITE_HI
))))
858 /* If we are being given a nop instruction, don't bother with
859 one of the nops we would otherwise output. This will only
860 happen when a nop instruction is used with mips_optimize set
862 if (nops
> 0 && ip
->insn_opcode
== 0)
865 /* Now emit the right number of NOP instructions. */
872 listing_prev_line ();
873 if (insn_label
!= NULL
)
875 assert (S_GET_SEGMENT (insn_label
) == now_seg
);
876 insn_label
->sy_frag
= frag_now
;
877 S_SET_VALUE (insn_label
, (valueT
) frag_now_fix ());
887 if (address_expr
!= NULL
)
889 if (address_expr
->X_op
== O_constant
)
894 ip
->insn_opcode
|= address_expr
->X_add_number
;
898 ip
->insn_opcode
|= address_expr
->X_add_number
& 0xffff;
901 case BFD_RELOC_MIPS_JMP
:
902 case BFD_RELOC_16_PCREL_S2
:
911 assert (reloc_type
!= BFD_RELOC_UNUSED
);
913 /* Don't generate a reloc if we are writing into a variant
916 fixp
= fix_new_exp (frag_now
, f
- frag_now
->fr_literal
, 4,
918 reloc_type
== BFD_RELOC_16_PCREL_S2
,
923 md_number_to_chars (f
, ip
->insn_opcode
, 4);
925 /* Update the register mask information. */
926 if (pinfo
& INSN_WRITE_GPR_D
)
927 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
);
928 if ((pinfo
& (INSN_WRITE_GPR_T
| INSN_READ_GPR_T
)) != 0)
929 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
);
930 if (pinfo
& INSN_READ_GPR_S
)
931 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> OP_SH_RS
) & OP_MASK_RS
);
932 if (pinfo
& INSN_WRITE_GPR_31
)
933 mips_gprmask
|= 1 << 31;
934 if (pinfo
& INSN_WRITE_FPR_D
)
935 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FD
) & OP_MASK_FD
);
936 if ((pinfo
& (INSN_WRITE_FPR_S
| INSN_READ_FPR_S
)) != 0)
937 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FS
) & OP_MASK_FS
);
938 if ((pinfo
& (INSN_WRITE_FPR_T
| INSN_READ_FPR_T
)) != 0)
939 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FT
) & OP_MASK_FT
);
940 if (pinfo
& INSN_COP
)
942 /* We don't keep enough information to sort these cases out. */
944 /* Never set the bit for $0, which is always zero. */
945 mips_gprmask
&=~ 1 << 0;
947 if (place
== NULL
&& ! mips_noreorder
)
949 /* Filling the branch delay slot is more complex. We try to
950 switch the branch with the previous instruction, which we can
951 do if the previous instruction does not set up a condition
952 that the branch tests and if the branch is not itself the
953 target of any branch. */
954 if ((pinfo
& INSN_UNCOND_BRANCH_DELAY
)
955 || (pinfo
& INSN_COND_BRANCH_DELAY
))
957 if (mips_optimize
< 2
958 /* If we have seen .set volatile or .set nomove, don't
961 /* If we had to emit any NOP instructions, then we
962 already know we can not swap. */
964 /* If we don't even know the previous insn, we can not
967 /* If the previous insn is already in a branch delay
968 slot, then we can not swap. */
969 || prev_insn_is_delay_slot
970 /* If the previous previous insn was in a .set
971 noreorder, we can't swap. Actually, the MIPS
972 assembler will swap in this situation. However, gcc
973 configured -with-gnu-as will generate code like
979 in which we can not swap the bne and INSN. If gcc is
980 not configured -with-gnu-as, it does not output the
981 .set pseudo-ops. We don't have to check
982 prev_insn_unreordered, because prev_insn_valid will
983 be 0 in that case. We don't want to use
984 prev_prev_insn_valid, because we do want to be able
985 to swap at the start of a function. */
986 || prev_prev_insn_unreordered
987 /* If the branch is itself the target of a branch, we
988 can not swap. We cheat on this; all we check for is
989 whether there is a label on this instruction. If
990 there are any branches to anything other than a
991 label, users must use .set noreorder. */
992 || insn_label
!= NULL
993 /* If the previous instruction is in a variant frag, we
994 can not do the swap. */
995 || prev_insn_frag
->fr_type
== rs_machine_dependent
996 /* If the branch reads the condition codes, we don't
997 even try to swap, because in the sequence
1002 we can not swap, and I don't feel like handling that
1004 || (pinfo
& INSN_READ_COND_CODE
)
1005 /* We can not swap with an instruction that requires a
1006 delay slot, becase the target of the branch might
1007 interfere with that instruction. */
1009 & (INSN_LOAD_COPROC_DELAY
1010 | INSN_COPROC_MOVE_DELAY
1011 | INSN_WRITE_COND_CODE
1016 & (INSN_LOAD_MEMORY_DELAY
1017 | INSN_COPROC_MEMORY_DELAY
)))
1018 /* We can not swap with a branch instruction. */
1020 & (INSN_UNCOND_BRANCH_DELAY
1021 | INSN_COND_BRANCH_DELAY
1022 | INSN_COND_BRANCH_LIKELY
))
1023 /* We do not swap with a trap instruction, since it
1024 complicates trap handlers to have the trap
1025 instruction be in a delay slot. */
1026 || (prev_pinfo
& INSN_TRAP
)
1027 /* If the branch reads a register that the previous
1028 instruction sets, we can not swap. */
1029 || ((prev_pinfo
& INSN_WRITE_GPR_T
)
1030 && insn_uses_reg (ip
,
1031 ((prev_insn
.insn_opcode
>> OP_SH_RT
)
1034 || ((prev_pinfo
& INSN_WRITE_GPR_D
)
1035 && insn_uses_reg (ip
,
1036 ((prev_insn
.insn_opcode
>> OP_SH_RD
)
1039 /* If the branch writes a register that the previous
1040 instruction sets, we can not swap (we know that
1041 branches write only to RD or to $31). */
1042 || ((prev_pinfo
& INSN_WRITE_GPR_T
)
1043 && (((pinfo
& INSN_WRITE_GPR_D
)
1044 && (((prev_insn
.insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
)
1045 == ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)))
1046 || ((pinfo
& INSN_WRITE_GPR_31
)
1047 && (((prev_insn
.insn_opcode
>> OP_SH_RT
)
1050 || ((prev_pinfo
& INSN_WRITE_GPR_D
)
1051 && (((pinfo
& INSN_WRITE_GPR_D
)
1052 && (((prev_insn
.insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)
1053 == ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)))
1054 || ((pinfo
& INSN_WRITE_GPR_31
)
1055 && (((prev_insn
.insn_opcode
>> OP_SH_RD
)
1058 /* If the branch writes a register that the previous
1059 instruction reads, we can not swap (we know that
1060 branches only write to RD or to $31). */
1061 || ((pinfo
& INSN_WRITE_GPR_D
)
1062 && insn_uses_reg (&prev_insn
,
1063 ((ip
->insn_opcode
>> OP_SH_RD
)
1066 || ((pinfo
& INSN_WRITE_GPR_31
)
1067 && insn_uses_reg (&prev_insn
, 31, 0))
1068 /* If we are generating embedded PIC code, the branch
1069 might be expanded into a sequence which uses $at, so
1070 we can't swap with an instruction which reads it. */
1071 || (mips_pic
== EMBEDDED_PIC
1072 && insn_uses_reg (&prev_insn
, AT
, 0))
1073 /* If the previous previous instruction has a load
1074 delay, and sets a register that the branch reads, we
1076 || (((prev_prev_insn
.insn_mo
->pinfo
& INSN_LOAD_COPROC_DELAY
)
1078 && (prev_prev_insn
.insn_mo
->pinfo
1079 & INSN_LOAD_MEMORY_DELAY
)))
1080 && insn_uses_reg (ip
,
1081 ((prev_prev_insn
.insn_opcode
>> OP_SH_RT
)
1085 /* We could do even better for unconditional branches to
1086 portions of this object file; we could pick up the
1087 instruction at the destination, put it in the delay
1088 slot, and bump the destination address. */
1090 /* Update the previous insn information. */
1091 prev_prev_insn
= *ip
;
1092 prev_insn
.insn_mo
= &dummy_opcode
;
1099 /* It looks like we can actually do the swap. */
1100 prev_f
= prev_insn_frag
->fr_literal
+ prev_insn_where
;
1101 memcpy (temp
, prev_f
, 4);
1102 memcpy (prev_f
, f
, 4);
1103 memcpy (f
, temp
, 4);
1106 prev_insn_fixp
->fx_frag
= frag_now
;
1107 prev_insn_fixp
->fx_where
= f
- frag_now
->fr_literal
;
1111 fixp
->fx_frag
= prev_insn_frag
;
1112 fixp
->fx_where
= prev_insn_where
;
1114 /* Update the previous insn information; leave prev_insn
1116 prev_prev_insn
= *ip
;
1118 prev_insn_is_delay_slot
= 1;
1120 /* If that was an unconditional branch, forget the previous
1121 insn information. */
1122 if (pinfo
& INSN_UNCOND_BRANCH_DELAY
)
1124 prev_prev_insn
.insn_mo
= &dummy_opcode
;
1125 prev_insn
.insn_mo
= &dummy_opcode
;
1128 else if (pinfo
& INSN_COND_BRANCH_LIKELY
)
1130 /* We don't yet optimize a branch likely. What we should do
1131 is look at the target, copy the instruction found there
1132 into the delay slot, and increment the branch to jump to
1133 the next instruction. */
1135 /* Update the previous insn information. */
1136 prev_prev_insn
= *ip
;
1137 prev_insn
.insn_mo
= &dummy_opcode
;
1141 /* Update the previous insn information. */
1143 prev_prev_insn
.insn_mo
= &dummy_opcode
;
1145 prev_prev_insn
= prev_insn
;
1148 /* Any time we see a branch, we always fill the delay slot
1149 immediately; since this insn is not a branch, we know it
1150 is not in a delay slot. */
1151 prev_insn_is_delay_slot
= 0;
1154 prev_prev_insn_unreordered
= prev_insn_unreordered
;
1155 prev_insn_unreordered
= 0;
1156 prev_insn_frag
= frag_now
;
1157 prev_insn_where
= f
- frag_now
->fr_literal
;
1158 prev_insn_fixp
= fixp
;
1159 prev_insn_valid
= 1;
1162 /* We just output an insn, so the next one doesn't have a label. */
1166 /* This function forgets that there was any previous instruction or
1170 mips_no_prev_insn ()
1172 prev_insn
.insn_mo
= &dummy_opcode
;
1173 prev_prev_insn
.insn_mo
= &dummy_opcode
;
1174 prev_insn_valid
= 0;
1175 prev_insn_is_delay_slot
= 0;
1176 prev_insn_unreordered
= 0;
1177 prev_prev_insn_unreordered
= 0;
1181 /* This function must be called whenever we turn on noreorder or emit
1182 something other than instructions. It inserts any NOPS which might
1183 be needed by the previous instruction, and clears the information
1184 kept for the previous instructions. */
1189 if (! mips_noreorder
)
1194 if ((prev_insn
.insn_mo
->pinfo
1195 & (INSN_LOAD_COPROC_DELAY
1196 | INSN_COPROC_MOVE_DELAY
1197 | INSN_WRITE_COND_CODE
1201 && (prev_insn
.insn_mo
->pinfo
1202 & (INSN_LOAD_MEMORY_DELAY
1203 | INSN_COPROC_MEMORY_DELAY
))))
1206 if ((prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
)
1207 || (prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
1208 || (prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
))
1211 else if ((prev_prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
)
1212 || (prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
1213 || (prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
))
1218 if (insn_label
!= NULL
)
1220 assert (S_GET_SEGMENT (insn_label
) == now_seg
);
1221 insn_label
->sy_frag
= frag_now
;
1222 S_SET_VALUE (insn_label
, (valueT
) frag_now_fix ());
1227 mips_no_prev_insn ();
1230 /* Build an instruction created by a macro expansion. This is passed
1231 a pointer to the count of instructions created so far, an
1232 expression, the name of the instruction to build, an operand format
1233 string, and corresponding arguments. */
1237 macro_build (char *place
,
1243 #else /* ! defined (NO_STDARG) */
1245 macro_build (place
, counter
, ep
, name
, fmt
, va_alist
)
1252 #endif /* ! defined (NO_STDARG) */
1254 struct mips_cl_insn insn
;
1255 bfd_reloc_code_real_type r
;
1259 va_start (args
, fmt
);
1265 * If the macro is about to expand into a second instruction,
1266 * print a warning if needed. We need to pass ip as a parameter
1267 * to generate a better warning message here...
1269 if (mips_warn_about_macros
&& place
== NULL
&& *counter
== 1)
1270 as_warn ("Macro instruction expanded into multiple instructions");
1273 *counter
+= 1; /* bump instruction counter */
1275 r
= BFD_RELOC_UNUSED
;
1276 insn
.insn_mo
= (struct mips_opcode
*) hash_find (op_hash
, name
);
1277 assert (insn
.insn_mo
);
1278 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
1280 while (strcmp (fmt
, insn
.insn_mo
->args
) != 0
1281 || insn
.insn_mo
->pinfo
== INSN_MACRO
)
1284 assert (insn
.insn_mo
->name
);
1285 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
1287 insn
.insn_opcode
= insn
.insn_mo
->match
;
1303 insn
.insn_opcode
|= va_arg (args
, int) << 16;
1309 insn
.insn_opcode
|= va_arg (args
, int) << 16;
1314 insn
.insn_opcode
|= va_arg (args
, int) << 11;
1319 insn
.insn_opcode
|= va_arg (args
, int) << 11;
1326 insn
.insn_opcode
|= va_arg (args
, int) << 6;
1330 insn
.insn_opcode
|= va_arg (args
, int) << 6;
1334 insn
.insn_opcode
|= va_arg (args
, int) << 6;
1341 insn
.insn_opcode
|= va_arg (args
, int) << 21;
1347 r
= (bfd_reloc_code_real_type
) va_arg (args
, int);
1348 assert (r
== BFD_RELOC_MIPS_GPREL
1349 || r
== BFD_RELOC_MIPS_LITERAL
1350 || r
== BFD_RELOC_LO16
1351 || r
== BFD_RELOC_MIPS_GOT16
1352 || r
== BFD_RELOC_MIPS_CALL16
1353 || (ep
->X_op
== O_subtract
1354 && now_seg
== text_section
1355 && S_GET_SEGMENT (ep
->X_op_symbol
) == text_section
1356 && r
== BFD_RELOC_PCREL_LO16
));
1360 r
= (bfd_reloc_code_real_type
) va_arg (args
, int);
1362 && (ep
->X_op
== O_constant
1363 || (ep
->X_op
== O_symbol
1364 && (r
== BFD_RELOC_HI16_S
1365 || r
== BFD_RELOC_HI16
))
1366 || (ep
->X_op
== O_subtract
1367 && now_seg
== text_section
1368 && S_GET_SEGMENT (ep
->X_op_symbol
) == text_section
1369 && r
== BFD_RELOC_PCREL_HI16_S
)));
1370 if (ep
->X_op
== O_constant
)
1372 insn
.insn_opcode
|= (ep
->X_add_number
>> 16) & 0xffff;
1374 r
= BFD_RELOC_UNUSED
;
1379 assert (ep
!= NULL
);
1381 * This allows macro() to pass an immediate expression for
1382 * creating short branches without creating a symbol.
1383 * Note that the expression still might come from the assembly
1384 * input, in which case the value is not checked for range nor
1385 * is a relocation entry generated (yuck).
1387 if (ep
->X_op
== O_constant
)
1389 insn
.insn_opcode
|= (ep
->X_add_number
>> 2) & 0xffff;
1393 r
= BFD_RELOC_16_PCREL_S2
;
1397 assert (ep
!= NULL
);
1398 r
= BFD_RELOC_MIPS_JMP
;
1407 assert (r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
1409 append_insn (place
, &insn
, ep
, r
);
1413 * Generate a "lui" instruction.
1416 macro_build_lui (place
, counter
, ep
, regnum
)
1422 expressionS high_expr
;
1423 struct mips_cl_insn insn
;
1424 bfd_reloc_code_real_type r
;
1425 CONST
char *name
= "lui";
1426 CONST
char *fmt
= "t,u";
1432 high_expr
.X_op
= O_constant
;
1433 high_expr
.X_add_number
= 0;
1436 if (high_expr
.X_op
== O_constant
)
1438 /* we can compute the instruction now without a relocation entry */
1439 if (high_expr
.X_add_number
& 0x8000)
1440 high_expr
.X_add_number
+= 0x10000;
1441 high_expr
.X_add_number
=
1442 ((unsigned long) high_expr
.X_add_number
>> 16) & 0xffff;
1443 r
= BFD_RELOC_UNUSED
;
1447 assert (ep
->X_op
== O_symbol
);
1448 /* _gp_disp is a special case, used from s_cpload. */
1449 assert (mips_pic
== NO_PIC
1450 || strcmp (S_GET_NAME (ep
->X_add_symbol
), "_gp_disp") == 0);
1451 r
= BFD_RELOC_HI16_S
;
1455 * If the macro is about to expand into a second instruction,
1456 * print a warning if needed. We need to pass ip as a parameter
1457 * to generate a better warning message here...
1459 if (mips_warn_about_macros
&& place
== NULL
&& *counter
== 1)
1460 as_warn ("Macro instruction expanded into multiple instructions");
1463 *counter
+= 1; /* bump instruction counter */
1465 insn
.insn_mo
= (struct mips_opcode
*) hash_find (op_hash
, name
);
1466 assert (insn
.insn_mo
);
1467 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
1468 assert (strcmp (fmt
, insn
.insn_mo
->args
) == 0);
1470 insn
.insn_opcode
= insn
.insn_mo
->match
| (regnum
<< OP_SH_RT
);
1471 if (r
== BFD_RELOC_UNUSED
)
1473 insn
.insn_opcode
|= high_expr
.X_add_number
;
1474 append_insn (place
, &insn
, NULL
, r
);
1477 append_insn (place
, &insn
, &high_expr
, r
);
1481 * Generates code to set the $at register to true (one)
1482 * if reg is less than the immediate expression.
1485 set_at (counter
, reg
, unsignedp
)
1490 if (imm_expr
.X_add_number
>= -0x8000 && imm_expr
.X_add_number
< 0x8000)
1491 macro_build ((char *) NULL
, counter
, &imm_expr
,
1492 unsignedp
? "sltiu" : "slti",
1493 "t,r,j", AT
, reg
, (int) BFD_RELOC_LO16
);
1496 load_register (counter
, AT
, &imm_expr
);
1497 macro_build ((char *) NULL
, counter
, NULL
,
1498 unsignedp
? "sltu" : "slt",
1499 "d,v,t", AT
, reg
, AT
);
1503 /* Warn if an expression is not a constant. */
1506 check_absolute_expr (ip
, ex
)
1507 struct mips_cl_insn
*ip
;
1510 if (ex
->X_op
!= O_constant
)
1511 as_warn ("Instruction %s requires absolute expression", ip
->insn_mo
->name
);
1515 * This routine generates the least number of instructions neccessary to load
1516 * an absolute expression value into a register.
1519 load_register (counter
, reg
, ep
)
1524 assert (ep
->X_op
== O_constant
);
1525 if (ep
->X_add_number
>= -0x8000 && ep
->X_add_number
< 0x8000)
1526 macro_build ((char *) NULL
, counter
, ep
,
1527 mips_isa
< 3 ? "addiu" : "daddiu",
1528 "t,r,j", reg
, 0, (int) BFD_RELOC_LO16
);
1529 else if (ep
->X_add_number
>= 0 && ep
->X_add_number
< 0x10000)
1530 macro_build ((char *) NULL
, counter
, ep
, "ori", "t,r,i", reg
, 0,
1531 (int) BFD_RELOC_LO16
);
1532 else if ((ep
->X_add_number
&~ (offsetT
) 0x7fffffff) == 0
1533 || ((ep
->X_add_number
&~ (offsetT
) 0x7fffffff)
1534 == ~ (offsetT
) 0x7fffffff))
1536 macro_build ((char *) NULL
, counter
, ep
, "lui", "t,u", reg
,
1537 (int) BFD_RELOC_HI16
);
1538 if ((ep
->X_add_number
& 0xffff) != 0)
1539 macro_build ((char *) NULL
, counter
, ep
, "ori", "t,r,i", reg
, reg
,
1540 (int) BFD_RELOC_LO16
);
1542 else if (mips_isa
< 3)
1544 as_bad ("Number larger than 32 bits");
1545 macro_build ((char *) NULL
, counter
, ep
, "addiu", "t,r,j", reg
, 0,
1546 (int) BFD_RELOC_LO16
);
1551 expressionS hi32
, lo32
;
1555 hi32
.X_add_number
>>= shift
;
1556 hi32
.X_add_number
&= 0xffffffff;
1557 if ((hi32
.X_add_number
& 0x80000000) != 0)
1558 hi32
.X_add_number
|= ~ (offsetT
) 0xffffffff;
1559 load_register (counter
, reg
, &hi32
);
1561 lo32
.X_add_number
&= 0xffffffff;
1562 if ((lo32
.X_add_number
& 0xffff0000) == 0)
1563 macro_build ((char *) NULL
, counter
, NULL
, "dsll32", "d,w,<", reg
,
1569 macro_build ((char *) NULL
, counter
, NULL
, "dsll", "d,w,<", reg
,
1572 mid16
.X_add_number
>>= 16;
1573 macro_build ((char *) NULL
, counter
, &mid16
, "ori", "t,r,i", reg
,
1574 reg
, (int) BFD_RELOC_LO16
);
1575 macro_build ((char *) NULL
, counter
, NULL
, "dsll", "d,w,<", reg
,
1578 if ((lo32
.X_add_number
& 0xffff) != 0)
1579 macro_build ((char *) NULL
, counter
, &lo32
, "ori", "t,r,i", reg
, reg
,
1580 (int) BFD_RELOC_LO16
);
1584 /* Load an address into a register. */
1587 load_address (counter
, reg
, ep
)
1594 if (ep
->X_op
!= O_constant
1595 && ep
->X_op
!= O_symbol
)
1597 as_bad ("expression too complex");
1598 ep
->X_op
= O_constant
;
1601 if (ep
->X_op
== O_constant
)
1603 load_register (counter
, reg
, ep
);
1607 if (mips_pic
== NO_PIC
)
1609 /* If this is a reference to a GP relative symbol, we want
1610 addiu $reg,$gp,<sym> (BFD_RELOC_MIPS_GPREL)
1612 lui $reg,<sym> (BFD_RELOC_HI16_S)
1613 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
1614 If we have an addend, we always use the latter form. */
1615 if (ep
->X_add_number
!= 0)
1620 macro_build ((char *) NULL
, counter
, ep
,
1621 mips_isa
< 3 ? "addiu" : "daddiu",
1622 "t,r,j", reg
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
1623 p
= frag_var (rs_machine_dependent
, 8, 0,
1624 RELAX_ENCODE (4, 8, -4, 0, 0, mips_warn_about_macros
),
1625 ep
->X_add_symbol
, (long) 0, (char *) NULL
);
1627 macro_build_lui (p
, counter
, ep
, reg
);
1630 macro_build (p
, counter
, ep
,
1631 mips_isa
< 3 ? "addiu" : "daddiu",
1632 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
1634 else if (mips_pic
== SVR4_PIC
)
1638 /* If this is a reference to an external symbol, we want
1639 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
1641 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
1643 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
1644 If there is a constant, it must be added in after. */
1645 ex
.X_add_number
= ep
->X_add_number
;
1646 ep
->X_add_number
= 0;
1648 macro_build ((char *) NULL
, counter
, ep
,
1649 mips_isa
< 3 ? "lw" : "ld",
1650 "t,o(b)", reg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
1651 macro_build ((char *) NULL
, counter
, (expressionS
*) NULL
, "nop", "");
1652 p
= frag_var (rs_machine_dependent
, 4, 0,
1653 RELAX_ENCODE (0, 4, -8, 0, 0, mips_warn_about_macros
),
1654 ep
->X_add_symbol
, (long) 0, (char *) NULL
);
1655 macro_build (p
, counter
, ep
,
1656 mips_isa
< 3 ? "addiu" : "daddiu",
1657 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
1658 if (ex
.X_add_number
!= 0)
1660 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
1661 as_bad ("PIC code offset overflow (max 16 signed bits)");
1662 ex
.X_op
= O_constant
;
1663 macro_build (p
, counter
, &ex
,
1664 mips_isa
< 3 ? "addiu" : "daddiu",
1665 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
1668 else if (mips_pic
== EMBEDDED_PIC
)
1671 addiu $reg,$gp,<sym> (BFD_RELOC_MIPS_GPREL)
1673 macro_build ((char *) NULL
, counter
, ep
,
1674 mips_isa
< 3 ? "addiu" : "daddiu",
1675 "t,r,j", reg
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
1683 * This routine implements the seemingly endless macro or synthesized
1684 * instructions and addressing modes in the mips assembly language. Many
1685 * of these macros are simple and are similar to each other. These could
1686 * probably be handled by some kind of table or grammer aproach instead of
1687 * this verbose method. Others are not simple macros but are more like
1688 * optimizing code generation.
1689 * One interesting optimization is when several store macros appear
1690 * consecutivly that would load AT with the upper half of the same address.
1691 * The ensuing load upper instructions are ommited. This implies some kind
1692 * of global optimization. We currently only optimize within a single macro.
1693 * For many of the load and store macros if the address is specified as a
1694 * constant expression in the first 64k of memory (ie ld $2,0x4000c) we
1695 * first load register 'at' with zero and use it as the base register. The
1696 * mips assembler simply uses register $zero. Just one tiny optimization
1701 struct mips_cl_insn
*ip
;
1703 register int treg
, sreg
, dreg
, breg
;
1716 bfd_reloc_code_real_type r
;
1719 treg
= (ip
->insn_opcode
>> 16) & 0x1f;
1720 dreg
= (ip
->insn_opcode
>> 11) & 0x1f;
1721 sreg
= breg
= (ip
->insn_opcode
>> 21) & 0x1f;
1722 mask
= ip
->insn_mo
->mask
;
1724 expr1
.X_op
= O_constant
;
1725 expr1
.X_op_symbol
= NULL
;
1726 expr1
.X_add_symbol
= NULL
;
1727 expr1
.X_add_number
= 1;
1739 mips_emit_delays ();
1741 mips_any_noreorder
= 1;
1743 expr1
.X_add_number
= 8;
1744 macro_build ((char *) NULL
, &icnt
, &expr1
, "bgez", "s,p", sreg
);
1746 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
1748 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
, sreg
, 0);
1749 macro_build ((char *) NULL
, &icnt
, NULL
,
1750 dbl
? "dsub" : "sub",
1751 "d,v,t", dreg
, 0, sreg
);
1774 if (imm_expr
.X_add_number
>= -0x8000 && imm_expr
.X_add_number
< 0x8000)
1776 macro_build ((char *) NULL
, &icnt
, &imm_expr
, s
, "t,r,j", treg
, sreg
,
1777 (int) BFD_RELOC_LO16
);
1780 load_register (&icnt
, AT
, &imm_expr
);
1781 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "d,v,t", treg
, sreg
, AT
);
1800 if (imm_expr
.X_add_number
>= 0 && imm_expr
.X_add_number
< 0x10000)
1802 if (mask
!= M_NOR_I
)
1803 macro_build ((char *) NULL
, &icnt
, &imm_expr
, s
, "t,r,i", treg
,
1804 sreg
, (int) BFD_RELOC_LO16
);
1807 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "ori", "t,r,i",
1808 treg
, sreg
, (int) BFD_RELOC_LO16
);
1809 macro_build ((char *) NULL
, &icnt
, NULL
, "nor", "d,v,t",
1815 load_register (&icnt
, AT
, &imm_expr
);
1816 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "d,v,t", treg
, sreg
, AT
);
1833 if (imm_expr
.X_add_number
== 0)
1835 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "s,t,p", sreg
,
1839 load_register (&icnt
, AT
, &imm_expr
);
1840 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "s,t,p", sreg
, AT
);
1848 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
1849 likely
? "bgezl" : "bgez",
1855 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
1856 likely
? "blezl" : "blez",
1860 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", AT
, sreg
, treg
);
1861 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
1862 likely
? "beql" : "beq",
1869 /* check for > max integer */
1870 maxnum
= 0x7fffffff;
1878 if (imm_expr
.X_add_number
>= maxnum
)
1881 /* result is always false */
1884 as_warn ("Branch %s is always false (nop)", ip
->insn_mo
->name
);
1885 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
1889 as_warn ("Branch likely %s is always false", ip
->insn_mo
->name
);
1890 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "bnel",
1895 imm_expr
.X_add_number
++;
1899 if (mask
== M_BGEL_I
)
1901 if (imm_expr
.X_add_number
== 0)
1903 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
1904 likely
? "bgezl" : "bgez",
1908 if (imm_expr
.X_add_number
== 1)
1910 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
1911 likely
? "bgtzl" : "bgtz",
1915 maxnum
= 0x7fffffff;
1923 maxnum
= - maxnum
- 1;
1924 if (imm_expr
.X_add_number
<= maxnum
)
1927 /* result is always true */
1928 as_warn ("Branch %s is always true", ip
->insn_mo
->name
);
1929 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "b", "p");
1932 set_at (&icnt
, sreg
, 0);
1933 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
1934 likely
? "beql" : "beq",
1945 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
1946 likely
? "beql" : "beq",
1950 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", AT
, sreg
,
1952 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
1953 likely
? "beql" : "beq",
1960 if (sreg
== 0 || imm_expr
.X_add_number
== -1)
1962 imm_expr
.X_add_number
++;
1966 if (mask
== M_BGEUL_I
)
1968 if (imm_expr
.X_add_number
== 0)
1970 if (imm_expr
.X_add_number
== 1)
1972 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
1973 likely
? "bnel" : "bne",
1977 set_at (&icnt
, sreg
, 1);
1978 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
1979 likely
? "beql" : "beq",
1988 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
1989 likely
? "bgtzl" : "bgtz",
1995 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
1996 likely
? "bltzl" : "bltz",
2000 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", AT
, treg
, sreg
);
2001 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2002 likely
? "bnel" : "bne",
2011 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2012 likely
? "bnel" : "bne",
2018 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", AT
, treg
,
2020 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2021 likely
? "bnel" : "bne",
2030 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2031 likely
? "blezl" : "blez",
2037 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2038 likely
? "bgezl" : "bgez",
2042 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", AT
, treg
, sreg
);
2043 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2044 likely
? "beql" : "beq",
2051 maxnum
= 0x7fffffff;
2059 if (imm_expr
.X_add_number
>= maxnum
)
2061 imm_expr
.X_add_number
++;
2065 if (mask
== M_BLTL_I
)
2067 if (imm_expr
.X_add_number
== 0)
2069 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2070 likely
? "bltzl" : "bltz",
2074 if (imm_expr
.X_add_number
== 1)
2076 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2077 likely
? "blezl" : "blez",
2081 set_at (&icnt
, sreg
, 0);
2082 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2083 likely
? "bnel" : "bne",
2092 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2093 likely
? "beql" : "beq",
2099 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", AT
, treg
,
2101 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2102 likely
? "beql" : "beq",
2109 if (sreg
== 0 || imm_expr
.X_add_number
== -1)
2111 imm_expr
.X_add_number
++;
2115 if (mask
== M_BLTUL_I
)
2117 if (imm_expr
.X_add_number
== 0)
2119 if (imm_expr
.X_add_number
== 1)
2121 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2122 likely
? "beql" : "beq",
2126 set_at (&icnt
, sreg
, 1);
2127 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2128 likely
? "bnel" : "bne",
2137 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2138 likely
? "bltzl" : "bltz",
2144 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2145 likely
? "bgtzl" : "bgtz",
2149 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", AT
, sreg
, treg
);
2150 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2151 likely
? "bnel" : "bne",
2162 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2163 likely
? "bnel" : "bne",
2167 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", AT
, sreg
,
2169 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2170 likely
? "bnel" : "bne",
2186 as_warn ("Divide by zero.");
2188 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", 0, 0);
2190 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 7);
2194 mips_emit_delays ();
2196 mips_any_noreorder
= 1;
2197 macro_build ((char *) NULL
, &icnt
, NULL
,
2198 dbl
? "ddiv" : "div",
2199 "z,s,t", sreg
, treg
);
2201 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", treg
, 0);
2204 expr1
.X_add_number
= 8;
2205 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", treg
, 0);
2206 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
2207 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 7);
2209 expr1
.X_add_number
= -1;
2210 macro_build ((char *) NULL
, &icnt
, &expr1
,
2211 dbl
? "daddiu" : "addiu",
2212 "t,r,j", AT
, 0, (int) BFD_RELOC_LO16
);
2213 expr1
.X_add_number
= mips_trap
? (dbl
? 12 : 8) : (dbl
? 20 : 16);
2214 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", treg
, AT
);
2217 expr1
.X_add_number
= 1;
2218 macro_build ((char *) NULL
, &icnt
, &expr1
, "daddiu", "t,r,j", AT
, 0,
2219 (int) BFD_RELOC_LO16
);
2220 macro_build ((char *) NULL
, &icnt
, NULL
, "dsll32", "d,w,<", AT
, AT
,
2225 expr1
.X_add_number
= 0x80000000;
2226 macro_build ((char *) NULL
, &icnt
, &expr1
, "lui", "t,u", AT
,
2227 (int) BFD_RELOC_HI16
);
2230 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", sreg
, AT
);
2233 expr1
.X_add_number
= 8;
2234 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", sreg
, AT
);
2235 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
2236 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 6);
2239 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d", dreg
);
2278 if (imm_expr
.X_add_number
== 0)
2280 as_warn ("Divide by zero.");
2282 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", 0, 0);
2284 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 7);
2287 if (imm_expr
.X_add_number
== 1)
2289 if (strcmp (s2
, "mflo") == 0)
2290 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
,
2293 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
, 0);
2296 if (imm_expr
.X_add_number
== -1
2297 && s
[strlen (s
) - 1] != 'u')
2299 if (strcmp (s2
, "mflo") == 0)
2302 macro_build ((char *) NULL
, &icnt
, NULL
, "dneg", "d,w", dreg
,
2305 macro_build ((char *) NULL
, &icnt
, NULL
, "neg", "d,w", dreg
,
2309 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
, 0);
2313 load_register (&icnt
, AT
, &imm_expr
);
2314 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "z,s,t", sreg
, AT
);
2315 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "d", dreg
);
2334 mips_emit_delays ();
2336 mips_any_noreorder
= 1;
2337 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "z,s,t", sreg
, treg
);
2339 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", treg
, 0);
2342 expr1
.X_add_number
= 8;
2343 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", treg
, 0);
2344 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
2345 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 7);
2348 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "d", dreg
);
2352 /* Load the address of a symbol into a register. If breg is not
2353 zero, we then add a base register to it. */
2355 /* When generating embedded PIC code, we permit expressions of
2358 where bar is an address in the .text section. These are used
2359 when getting the addresses of functions. We don't permit
2360 X_add_number to be non-zero, because if the symbol is
2361 external the relaxing code needs to know that any addend is
2362 purely the offset to X_op_symbol. */
2363 if (mips_pic
== EMBEDDED_PIC
2364 && offset_expr
.X_op
== O_subtract
2365 && now_seg
== text_section
2366 && S_GET_SEGMENT (offset_expr
.X_op_symbol
) == text_section
2368 && offset_expr
.X_add_number
== 0)
2370 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
2371 treg
, (int) BFD_RELOC_PCREL_HI16_S
);
2372 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2373 mips_isa
< 3 ? "addiu" : "daddiu",
2374 "t,r,j", treg
, treg
, (int) BFD_RELOC_PCREL_LO16
);
2378 if (offset_expr
.X_op
!= O_symbol
2379 && offset_expr
.X_op
!= O_constant
)
2381 as_bad ("expression too complex");
2382 offset_expr
.X_op
= O_constant
;
2396 if (offset_expr
.X_op
== O_constant
)
2397 load_register (&icnt
, tempreg
, &offset_expr
);
2398 else if (mips_pic
== NO_PIC
)
2400 /* If this is a reference to an GP relative symbol, we want
2401 addiu $tempreg,$gp,<sym> (BFD_RELOC_MIPS_GPREL)
2403 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
2404 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
2405 If we have a constant, we need two instructions anyhow,
2406 so we may as well always use the latter form. */
2407 if (offset_expr
.X_add_number
!= 0)
2412 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2413 mips_isa
< 3 ? "addiu" : "daddiu",
2414 "t,r,j", tempreg
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
2415 p
= frag_var (rs_machine_dependent
, 8, 0,
2416 RELAX_ENCODE (4, 8, 0, 4, 0,
2417 mips_warn_about_macros
),
2418 offset_expr
.X_add_symbol
, (long) 0,
2421 macro_build_lui (p
, &icnt
, &offset_expr
, tempreg
);
2424 macro_build (p
, &icnt
, &offset_expr
,
2425 mips_isa
< 3 ? "addiu" : "daddiu",
2426 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
2428 else if (mips_pic
== SVR4_PIC
)
2430 /* If this is a reference to an external symbol, and there
2431 is no constant, we want
2432 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
2433 For a local symbol, we want
2434 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
2436 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
2438 If we have a small constant, and this is a reference to
2439 an external symbol, we want
2440 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
2442 addiu $tempreg,$tempreg,<constant>
2443 For a local symbol, we want the same instruction
2444 sequence, but we output a BFD_RELOC_LO16 reloc on the
2447 If we have a large constant, and this is a reference to
2448 an external symbol, we want
2449 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
2450 lui $at,<hiconstant>
2451 addiu $at,$at,<loconstant>
2452 addu $tempreg,$tempreg,$at
2453 For a local symbol, we want the same instruction
2454 sequence, but we output a BFD_RELOC_LO16 reloc on the
2455 addiu instruction. */
2456 expr1
.X_add_number
= offset_expr
.X_add_number
;
2457 offset_expr
.X_add_number
= 0;
2459 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2460 mips_isa
< 3 ? "lw" : "ld",
2461 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
2462 if (expr1
.X_add_number
== 0)
2470 /* We're going to put in an addu instruction using
2471 tempreg, so we may as well insert the nop right
2473 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
2477 p
= frag_var (rs_machine_dependent
, 8 - off
, 0,
2478 RELAX_ENCODE (0, 8 - off
, -4 - off
, 4 - off
, 0,
2480 ? mips_warn_about_macros
2482 offset_expr
.X_add_symbol
, (long) 0,
2486 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
2489 macro_build (p
, &icnt
, &expr1
,
2490 mips_isa
< 3 ? "addiu" : "daddiu",
2491 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
2492 /* FIXME: If breg == 0, and the next instruction uses
2493 $tempreg, then if this variant case is used an extra
2494 nop will be generated. */
2496 else if (expr1
.X_add_number
>= -0x8000
2497 && expr1
.X_add_number
< 0x8000)
2499 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
2501 macro_build ((char *) NULL
, &icnt
, &expr1
,
2502 mips_isa
< 3 ? "addiu" : "daddiu",
2503 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
2504 (void) frag_var (rs_machine_dependent
, 0, 0,
2505 RELAX_ENCODE (0, 0, -12, -4, 0, 0),
2506 offset_expr
.X_add_symbol
, (long) 0,
2513 /* If we are going to add in a base register, and the
2514 target register and the base register are the same,
2515 then we are using AT as a temporary register. Since
2516 we want to load the constant into AT, we add our
2517 current AT (from the global offset table) and the
2518 register into the register now, and pretend we were
2519 not using a base register. */
2524 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
2526 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
2527 mips_isa
< 3 ? "addu" : "daddu",
2528 "d,v,t", treg
, AT
, breg
);
2534 macro_build_lui ((char *) NULL
, &icnt
, &expr1
, AT
);
2535 macro_build ((char *) NULL
, &icnt
, &expr1
,
2536 mips_isa
< 3 ? "addiu" : "daddiu",
2537 "t,r,j", AT
, AT
, (int) BFD_RELOC_LO16
);
2538 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
2539 mips_isa
< 3 ? "addu" : "daddu",
2540 "d,v,t", tempreg
, tempreg
, AT
);
2541 (void) frag_var (rs_machine_dependent
, 0, 0,
2542 RELAX_ENCODE (0, 0, -16 + off1
, -8, 0, 0),
2543 offset_expr
.X_add_symbol
, (long) 0,
2548 else if (mips_pic
== EMBEDDED_PIC
)
2551 addiu $tempreg,$gp,<sym> (BFD_RELOC_MIPS_GPREL)
2553 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2554 mips_isa
< 3 ? "addiu" : "daddiu",
2555 "t,r,j", tempreg
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
2561 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
2562 mips_isa
< 3 ? "addu" : "daddu",
2563 "d,v,t", treg
, tempreg
, breg
);
2571 /* The j instruction may not be used in PIC code, since it
2572 requires an absolute address. We convert it to a b
2574 if (mips_pic
== NO_PIC
)
2575 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "j", "a");
2577 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "b", "p");
2580 /* The jal instructions must be handled as macros because when
2581 generating PIC code they expand to multi-instruction
2582 sequences. Normally they are simple instructions. */
2587 if (mips_pic
== NO_PIC
2588 || mips_pic
== EMBEDDED_PIC
)
2589 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "jalr",
2591 else if (mips_pic
== SVR4_PIC
)
2593 if (sreg
!= PIC_CALL_REG
)
2594 as_warn ("MIPS PIC call to register other than $25");
2596 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "jalr",
2598 if (mips_cprestore_offset
< 0)
2599 as_warn ("No .cprestore pseudo-op used in PIC code");
2602 expr1
.X_add_number
= mips_cprestore_offset
;
2603 macro_build ((char *) NULL
, &icnt
, &expr1
,
2604 mips_isa
< 3 ? "lw" : "ld",
2605 "t,o(b)", GP
, (int) BFD_RELOC_LO16
, mips_frame_reg
);
2614 if (mips_pic
== NO_PIC
)
2615 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "jal", "a");
2616 else if (mips_pic
== SVR4_PIC
)
2618 /* If this is a reference to an external symbol, we want
2619 lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
2623 lw $gp,cprestore($sp)
2624 The cprestore value is set using the .cprestore
2625 pseudo-op. If the symbol is not external, we want
2626 lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
2628 addiu $25,$25,<sym> (BFD_RELOC_LO16)
2631 lw $gp,cprestore($sp)
2634 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2635 mips_isa
< 3 ? "lw" : "ld",
2636 "t,o(b)", PIC_CALL_REG
,
2637 (int) BFD_RELOC_MIPS_CALL16
, GP
);
2638 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
2639 p
= frag_var (rs_machine_dependent
, 4, 0,
2640 RELAX_ENCODE (0, 4, -8, 0, 0, 0),
2641 offset_expr
.X_add_symbol
, (long) 0, (char *) NULL
);
2642 macro_build (p
, &icnt
, &offset_expr
,
2643 mips_isa
< 3 ? "addiu" : "daddiu",
2644 "t,r,j", PIC_CALL_REG
, PIC_CALL_REG
,
2645 (int) BFD_RELOC_LO16
);
2646 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
2647 "jalr", "s", PIC_CALL_REG
);
2648 if (mips_cprestore_offset
< 0)
2649 as_warn ("No .cprestore pseudo-op used in PIC code");
2653 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
2655 expr1
.X_add_number
= mips_cprestore_offset
;
2656 macro_build ((char *) NULL
, &icnt
, &expr1
,
2657 mips_isa
< 3 ? "lw" : "ld",
2658 "t,o(b)", GP
, (int) BFD_RELOC_LO16
,
2662 else if (mips_pic
== EMBEDDED_PIC
)
2664 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "bal", "p");
2665 /* The linker may expand the call to a longer sequence which
2666 uses $at, so we must break rather than return. */
2738 if (breg
== treg
|| coproc
)
2807 if (mask
== M_LWC1_AB
2808 || mask
== M_SWC1_AB
2809 || mask
== M_LDC1_AB
2810 || mask
== M_SDC1_AB
2819 if (offset_expr
.X_op
!= O_constant
2820 && offset_expr
.X_op
!= O_symbol
)
2822 as_bad ("expression too complex");
2823 offset_expr
.X_op
= O_constant
;
2826 /* A constant expression in PIC code can be handled just as it
2827 is in non PIC code. */
2828 if (mips_pic
== NO_PIC
2829 || offset_expr
.X_op
== O_constant
)
2831 /* If this is a reference to a GP relative symbol, and there
2832 is no base register, we want
2833 <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL)
2834 Otherwise, if there is no base register, we want
2835 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
2836 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
2837 If we have a constant, we need two instructions anyhow,
2838 so we always use the latter form.
2840 If we have a base register, and this is a reference to a
2841 GP relative symbol, we want
2842 addu $tempreg,$breg,$gp
2843 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GPREL)
2845 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
2846 addu $tempreg,$tempreg,$breg
2847 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
2848 With a constant we always use the latter case. */
2851 if (offset_expr
.X_add_number
!= 0)
2856 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
2857 treg
, (int) BFD_RELOC_MIPS_GPREL
, GP
);
2858 p
= frag_var (rs_machine_dependent
, 8, 0,
2859 RELAX_ENCODE (4, 8, 0, 4, 0,
2860 (mips_warn_about_macros
2861 || (used_at
&& mips_noat
))),
2862 offset_expr
.X_add_symbol
, (long) 0,
2866 macro_build_lui (p
, &icnt
, &offset_expr
, tempreg
);
2869 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
, treg
,
2870 (int) BFD_RELOC_LO16
, tempreg
);
2874 if (offset_expr
.X_add_number
!= 0)
2879 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
2880 mips_isa
< 3 ? "addu" : "daddu",
2881 "d,v,t", tempreg
, breg
, GP
);
2882 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
2883 treg
, (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
2884 p
= frag_var (rs_machine_dependent
, 12, 0,
2885 RELAX_ENCODE (8, 12, 0, 8, 0, 0),
2886 offset_expr
.X_add_symbol
, (long) 0,
2889 macro_build_lui (p
, &icnt
, &offset_expr
, tempreg
);
2892 macro_build (p
, &icnt
, (expressionS
*) NULL
,
2893 mips_isa
< 3 ? "addu" : "daddu",
2894 "d,v,t", tempreg
, tempreg
, breg
);
2897 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
, treg
,
2898 (int) BFD_RELOC_LO16
, tempreg
);
2901 else if (mips_pic
== SVR4_PIC
)
2903 /* If this is a reference to an external symbol, we want
2904 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
2906 <op> $treg,0($tempreg)
2908 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
2910 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
2911 <op> $treg,0($tempreg)
2912 If there is a base register, we add it to $tempreg before
2913 the <op>. If there is a constant, we stick it in the
2914 <op> instruction. We don't handle constants larger than
2915 16 bits, because we have no way to load the upper 16 bits
2916 (actually, we could handle them for the subset of cases
2917 in which we are not using $at). */
2918 assert (offset_expr
.X_op
== O_symbol
);
2919 expr1
.X_add_number
= offset_expr
.X_add_number
;
2920 offset_expr
.X_add_number
= 0;
2921 if (expr1
.X_add_number
< -0x8000
2922 || expr1
.X_add_number
>= 0x8000)
2923 as_bad ("PIC code offset overflow (max 16 signed bits)");
2925 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2926 mips_isa
< 3 ? "lw" : "ld",
2927 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
2928 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
2929 p
= frag_var (rs_machine_dependent
, 4, 0,
2930 RELAX_ENCODE (0, 4, -8, 0, 0, 0),
2931 offset_expr
.X_add_symbol
, (long) 0,
2933 macro_build (p
, &icnt
, &offset_expr
,
2934 mips_isa
< 3 ? "addiu" : "daddiu",
2935 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
2937 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
2938 mips_isa
< 3 ? "addu" : "daddu",
2939 "d,v,t", tempreg
, tempreg
, breg
);
2940 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
, treg
,
2941 (int) BFD_RELOC_LO16
, tempreg
);
2943 else if (mips_pic
== EMBEDDED_PIC
)
2945 /* If there is no base register, we want
2946 <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL)
2947 If there is a base register, we want
2948 addu $tempreg,$breg,$gp
2949 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GPREL)
2951 assert (offset_expr
.X_op
== O_symbol
);
2954 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
2955 treg
, (int) BFD_RELOC_MIPS_GPREL
, GP
);
2960 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
2961 mips_isa
< 3 ? "addu" : "daddu",
2962 "d,v,t", tempreg
, breg
, GP
);
2963 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
2964 treg
, (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
2977 load_register (&icnt
, treg
, &imm_expr
);
2981 if (mips_pic
== NO_PIC
)
2983 assert (offset_expr
.X_op
== O_symbol
2984 && strcmp (segment_name (S_GET_SEGMENT
2985 (offset_expr
.X_add_symbol
)),
2987 && offset_expr
.X_add_number
== 0);
2988 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lwc1", "T,o(b)",
2989 treg
, (int) BFD_RELOC_MIPS_LITERAL
, GP
);
2991 else if (mips_pic
== SVR4_PIC
2992 || mips_pic
== EMBEDDED_PIC
)
2994 assert (imm_expr
.X_op
== O_constant
);
2995 load_register (&icnt
, treg
, &imm_expr
);
3003 /* We know that sym is in the .rdata section. First we get the
3004 upper 16 bits of the address. */
3005 if (mips_pic
== NO_PIC
)
3007 /* FIXME: This won't work for a 64 bit address. */
3008 macro_build_lui ((char *) NULL
, &icnt
, &offset_expr
, AT
);
3010 else if (mips_pic
== SVR4_PIC
)
3012 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3013 mips_isa
< 3 ? "lw" : "ld",
3014 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
3016 else if (mips_pic
== EMBEDDED_PIC
)
3018 /* For embedded PIC we pick up the entire address off $gp in
3019 a single instruction. */
3020 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3021 mips_isa
< 3 ? "addiu" : "daddiu",
3022 "t,r,j", AT
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
3023 offset_expr
.X_op
= O_constant
;
3024 offset_expr
.X_add_number
= 0;
3029 /* Now we load the register(s). */
3031 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "ld", "t,o(b)",
3032 treg
, (int) BFD_RELOC_LO16
, AT
);
3035 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lw", "t,o(b)",
3036 treg
, (int) BFD_RELOC_LO16
, AT
);
3039 /* FIXME: How in the world do we deal with the possible
3041 offset_expr
.X_add_number
+= 4;
3042 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lw", "t,o(b)",
3043 treg
+ 1, (int) BFD_RELOC_LO16
, AT
);
3050 if (mips_pic
== NO_PIC
3051 || mips_pic
== EMBEDDED_PIC
)
3053 /* Load a floating point number from the .lit8 section. */
3054 assert (offset_expr
.X_op
== O_symbol
3055 && strcmp (segment_name (S_GET_SEGMENT
3056 (offset_expr
.X_add_symbol
)),
3058 && offset_expr
.X_add_number
== 0);
3061 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "ldc1",
3062 "T,o(b)", treg
, (int) BFD_RELOC_MIPS_LITERAL
, GP
);
3066 r
= BFD_RELOC_MIPS_LITERAL
;
3069 else if (mips_pic
== SVR4_PIC
)
3071 /* Load the double from the .rdata section. */
3072 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3073 mips_isa
< 3 ? "lw" : "ld",
3074 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
3077 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "ldc1",
3078 "T,o(b)", treg
, (int) BFD_RELOC_LO16
, GP
);
3089 /* Even on a big endian machine $fn comes before $fn+1. We have
3090 to adjust when loading from memory. */
3093 assert (mips_isa
< 2);
3094 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lwc1", "T,o(b)",
3095 byte_order
== LITTLE_ENDIAN
? treg
: treg
+ 1,
3097 /* FIXME: A possible overflow which I don't know how to deal
3099 offset_expr
.X_add_number
+= 4;
3100 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lwc1", "T,o(b)",
3101 byte_order
== LITTLE_ENDIAN
? treg
+ 1 : treg
,
3109 * The MIPS assembler seems to check for X_add_number not
3110 * being double aligned and generating:
3113 * addiu at,at,%lo(foo+1)
3116 * But, the resulting address is the same after relocation so why
3117 * generate the extra instruction?
3164 if (offset_expr
.X_op
!= O_symbol
3165 && offset_expr
.X_op
!= O_constant
)
3167 as_bad ("expression too complex");
3168 offset_expr
.X_op
= O_constant
;
3171 /* Even on a big endian machine $fn comes before $fn+1. We have
3172 to adjust when loading from memory. We set coproc if we must
3173 load $fn+1 first. */
3174 if (byte_order
== LITTLE_ENDIAN
)
3177 if (mips_pic
== NO_PIC
3178 || offset_expr
.X_op
== O_constant
)
3180 /* If this is a reference to a GP relative symbol, we want
3181 <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL)
3182 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_MIPS_GPREL)
3183 If we have a base register, we use this
3185 <op> $treg,<sym>($at) (BFD_RELOC_MIPS_GPREL)
3186 <op> $treg+1,<sym>+4($at) (BFD_RELOC_MIPS_GPREL)
3187 If this is not a GP relative symbol, we want
3188 lui $at,<sym> (BFD_RELOC_HI16_S)
3189 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
3190 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
3191 If there is a base register, we add it to $at after the
3192 lui instruction. If there is a constant, we always use
3194 if (offset_expr
.X_add_number
!= 0)
3213 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3214 mips_isa
< 3 ? "addu" : "daddu",
3215 "d,v,t", AT
, breg
, GP
);
3221 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
3222 coproc
? treg
+ 1 : treg
,
3223 (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
3224 offset_expr
.X_add_number
+= 4;
3225 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
3226 coproc
? treg
: treg
+ 1,
3227 (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
3228 p
= frag_var (rs_machine_dependent
, 12 + off
, 0,
3229 RELAX_ENCODE (8 + off
, 12 + off
, 0, 4 + off
, 1,
3230 used_at
&& mips_noat
),
3231 offset_expr
.X_add_symbol
, (long) 0,
3234 /* We just generated two relocs. When tc_gen_reloc
3235 handles this case, it will skip the first reloc and
3236 handle the second. The second reloc already has an
3237 extra addend of 4, which we added above. We must
3238 subtract it out, and then subtract another 4 to make
3239 the first reloc come out right. The second reloc
3240 will come out right because we are going to add 4 to
3241 offset_expr when we build its instruction below. */
3242 offset_expr
.X_add_number
-= 8;
3243 offset_expr
.X_op
= O_constant
;
3245 macro_build_lui (p
, &icnt
, &offset_expr
, AT
);
3250 macro_build (p
, &icnt
, (expressionS
*) NULL
,
3251 mips_isa
< 3 ? "addu" : "daddu",
3252 "d,v,t", AT
, breg
, AT
);
3256 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
,
3257 coproc
? treg
+ 1 : treg
,
3258 (int) BFD_RELOC_LO16
, AT
);
3261 /* FIXME: How do we handle overflow here? */
3262 offset_expr
.X_add_number
+= 4;
3263 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
,
3264 coproc
? treg
: treg
+ 1,
3265 (int) BFD_RELOC_LO16
, AT
);
3267 else if (mips_pic
== SVR4_PIC
)
3271 /* If this is a reference to an external symbol, we want
3272 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3277 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3279 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
3280 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
3281 If there is a base register we add it to $at before the
3282 lwc1 instructions. If there is a constant we include it
3283 in the lwc1 instructions. */
3285 expr1
.X_add_number
= offset_expr
.X_add_number
;
3286 offset_expr
.X_add_number
= 0;
3287 if (expr1
.X_add_number
< -0x8000
3288 || expr1
.X_add_number
>= 0x8000 - 4)
3289 as_bad ("PIC code offset overflow (max 16 signed bits)");
3294 frag_grow (24 + off
);
3295 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3296 mips_isa
< 3 ? "lw" : "ld",
3297 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
3298 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
3300 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3301 mips_isa
< 3 ? "addu" : "daddu",
3302 "d,v,t", AT
, breg
, AT
);
3303 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
3304 coproc
? treg
+ 1 : treg
,
3305 (int) BFD_RELOC_LO16
, AT
);
3306 expr1
.X_add_number
+= 4;
3307 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
3308 coproc
? treg
: treg
+ 1,
3309 (int) BFD_RELOC_LO16
, AT
);
3310 (void) frag_var (rs_machine_dependent
, 0, 0,
3311 RELAX_ENCODE (0, 0, -16 - off
, -8, 1, 0),
3312 offset_expr
.X_add_symbol
, (long) 0,
3315 else if (mips_pic
== EMBEDDED_PIC
)
3317 /* If there is no base register, we use
3318 <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL)
3319 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_MIPS_GPREL)
3320 If we have a base register, we use
3322 <op> $treg,<sym>($at) (BFD_RELOC_MIPS_GPREL)
3323 <op> $treg+1,<sym>+4($at) (BFD_RELOC_MIPS_GPREL)
3332 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3333 mips_isa
< 3 ? "addu" : "daddu",
3334 "d,v,t", AT
, breg
, GP
);
3339 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
3340 coproc
? treg
+ 1 : treg
,
3341 (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
3342 offset_expr
.X_add_number
+= 4;
3343 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
3344 coproc
? treg
: treg
+ 1,
3345 (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
3361 assert (mips_isa
< 3);
3362 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
3363 (int) BFD_RELOC_LO16
, breg
);
3364 offset_expr
.X_add_number
+= 4;
3365 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
+ 1,
3366 (int) BFD_RELOC_LO16
, breg
);
3368 #ifdef LOSING_COMPILER
3374 as_warn ("Macro used $at after \".set noat\"");
3379 struct mips_cl_insn
*ip
;
3381 register int treg
, sreg
, dreg
, breg
;
3394 bfd_reloc_code_real_type r
;
3397 treg
= (ip
->insn_opcode
>> 16) & 0x1f;
3398 dreg
= (ip
->insn_opcode
>> 11) & 0x1f;
3399 sreg
= breg
= (ip
->insn_opcode
>> 21) & 0x1f;
3400 mask
= ip
->insn_mo
->mask
;
3402 expr1
.X_op
= O_constant
;
3403 expr1
.X_op_symbol
= NULL
;
3404 expr1
.X_add_symbol
= NULL
;
3405 expr1
.X_add_number
= 1;
3409 #endif /* LOSING_COMPILER */
3414 macro_build ((char *) NULL
, &icnt
, NULL
,
3415 dbl
? "dmultu" : "multu",
3417 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
3423 /* The MIPS assembler some times generates shifts and adds. I'm
3424 not trying to be that fancy. GCC should do this for us
3426 load_register (&icnt
, AT
, &imm_expr
);
3427 macro_build ((char *) NULL
, &icnt
, NULL
,
3428 dbl
? "dmult" : "mult",
3430 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
3436 mips_emit_delays ();
3438 mips_any_noreorder
= 1;
3439 macro_build ((char *) NULL
, &icnt
, NULL
,
3440 dbl
? "dmult" : "mult",
3442 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
3443 macro_build ((char *) NULL
, &icnt
, NULL
,
3444 dbl
? "dsra32" : "sra",
3445 "d,w,<", dreg
, dreg
, 31);
3446 macro_build ((char *) NULL
, &icnt
, NULL
, "mfhi", "d", AT
);
3448 macro_build ((char *) NULL
, &icnt
, NULL
, "tne", "s,t", dreg
, AT
);
3451 expr1
.X_add_number
= 8;
3452 macro_build ((char *) NULL
, &icnt
, &expr1
, "beq", "s,t,p", dreg
, AT
);
3453 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
3454 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 6);
3457 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
3463 mips_emit_delays ();
3465 mips_any_noreorder
= 1;
3466 macro_build ((char *) NULL
, &icnt
, NULL
,
3467 dbl
? "dmultu" : "multu",
3469 macro_build ((char *) NULL
, &icnt
, NULL
, "mfhi", "d", AT
);
3470 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
3472 macro_build ((char *) NULL
, &icnt
, NULL
, "tne", "s,t", AT
, 0);
3475 expr1
.X_add_number
= 8;
3476 macro_build ((char *) NULL
, &icnt
, &expr1
, "beq", "s,t,p", AT
, 0);
3477 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
3478 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 6);
3484 macro_build ((char *) NULL
, &icnt
, NULL
, "subu", "d,v,t", AT
, 0, treg
);
3485 macro_build ((char *) NULL
, &icnt
, NULL
, "srlv", "d,t,s", AT
, sreg
, AT
);
3486 macro_build ((char *) NULL
, &icnt
, NULL
, "sllv", "d,t,s", dreg
, sreg
,
3488 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
3492 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", AT
, sreg
,
3493 imm_expr
.X_add_number
& 0x1f);
3494 macro_build ((char *) NULL
, &icnt
, NULL
, "srl", "d,w,<", dreg
, sreg
,
3495 (0 - imm_expr
.X_add_number
) & 0x1f);
3496 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
3500 macro_build ((char *) NULL
, &icnt
, NULL
, "subu", "d,v,t", AT
, 0, treg
);
3501 macro_build ((char *) NULL
, &icnt
, NULL
, "sllv", "d,t,s", AT
, sreg
, AT
);
3502 macro_build ((char *) NULL
, &icnt
, NULL
, "srlv", "d,t,s", dreg
, sreg
,
3504 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
3508 macro_build ((char *) NULL
, &icnt
, NULL
, "srl", "d,w,<", AT
, sreg
,
3509 imm_expr
.X_add_number
& 0x1f);
3510 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", dreg
, sreg
,
3511 (0 - imm_expr
.X_add_number
) & 0x1f);
3512 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
3516 assert (mips_isa
< 2);
3517 /* Even on a big endian machine $fn comes before $fn+1. We have
3518 to adjust when storing to memory. */
3519 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "swc1", "T,o(b)",
3520 byte_order
== LITTLE_ENDIAN
? treg
: treg
+ 1,
3521 (int) BFD_RELOC_LO16
, breg
);
3522 offset_expr
.X_add_number
+= 4;
3523 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "swc1", "T,o(b)",
3524 byte_order
== LITTLE_ENDIAN
? treg
+ 1 : treg
,
3525 (int) BFD_RELOC_LO16
, breg
);
3530 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
3531 treg
, (int) BFD_RELOC_LO16
);
3533 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
3534 sreg
, (int) BFD_RELOC_LO16
);
3537 macro_build ((char *) NULL
, &icnt
, NULL
, "xor", "d,v,t", dreg
,
3539 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
3540 dreg
, (int) BFD_RELOC_LO16
);
3545 if (imm_expr
.X_add_number
== 0)
3547 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
3548 sreg
, (int) BFD_RELOC_LO16
);
3553 as_warn ("Instruction %s: result is always false",
3555 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
, 0);
3558 if (imm_expr
.X_add_number
>= 0 && imm_expr
.X_add_number
< 0x10000)
3560 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "xori", "t,r,i", dreg
,
3561 sreg
, (int) BFD_RELOC_LO16
);
3564 else if (imm_expr
.X_add_number
> -0x8000 && imm_expr
.X_add_number
< 0)
3566 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
3567 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
3568 mips_isa
< 3 ? "addiu" : "daddiu",
3569 "t,r,j", dreg
, sreg
,
3570 (int) BFD_RELOC_LO16
);
3575 load_register (&icnt
, AT
, &imm_expr
);
3576 macro_build ((char *) NULL
, &icnt
, NULL
, "xor", "d,v,t", dreg
,
3580 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
, dreg
,
3581 (int) BFD_RELOC_LO16
);
3586 case M_SGE
: /* sreg >= treg <==> not (sreg < treg) */
3592 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, sreg
, treg
);
3593 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
3594 (int) BFD_RELOC_LO16
);
3597 case M_SGE_I
: /* sreg >= I <==> not (sreg < I) */
3599 if (imm_expr
.X_add_number
>= -0x8000 && imm_expr
.X_add_number
< 0x8000)
3601 macro_build ((char *) NULL
, &icnt
, &expr1
,
3602 mask
== M_SGE_I
? "slti" : "sltiu",
3603 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
3608 load_register (&icnt
, AT
, &imm_expr
);
3609 macro_build ((char *) NULL
, &icnt
, NULL
,
3610 mask
== M_SGE_I
? "slt" : "sltu",
3611 "d,v,t", dreg
, sreg
, AT
);
3614 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
3615 (int) BFD_RELOC_LO16
);
3620 case M_SGT
: /* sreg > treg <==> treg < sreg */
3626 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, treg
, sreg
);
3629 case M_SGT_I
: /* sreg > I <==> I < sreg */
3635 load_register (&icnt
, AT
, &imm_expr
);
3636 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, AT
, sreg
);
3639 case M_SLE
: /* sreg <= treg <==> treg >= sreg <==> not (treg < sreg) */
3645 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, treg
, sreg
);
3646 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
3647 (int) BFD_RELOC_LO16
);
3650 case M_SLE_I
: /* sreg <= I <==> I >= sreg <==> not (I < sreg) */
3656 load_register (&icnt
, AT
, &imm_expr
);
3657 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, AT
, sreg
);
3658 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
3659 (int) BFD_RELOC_LO16
);
3663 if (imm_expr
.X_add_number
>= -0x8000 && imm_expr
.X_add_number
< 0x8000)
3665 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "slti", "t,r,j",
3666 dreg
, sreg
, (int) BFD_RELOC_LO16
);
3669 load_register (&icnt
, AT
, &imm_expr
);
3670 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", dreg
, sreg
, AT
);
3674 if (imm_expr
.X_add_number
>= -0x8000 && imm_expr
.X_add_number
< 0x8000)
3676 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "sltiu", "t,r,j",
3677 dreg
, sreg
, (int) BFD_RELOC_LO16
);
3680 load_register (&icnt
, AT
, &imm_expr
);
3681 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, sreg
,
3687 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0,
3690 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0,
3694 macro_build ((char *) NULL
, &icnt
, NULL
, "xor", "d,v,t", dreg
,
3696 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0,
3702 if (imm_expr
.X_add_number
== 0)
3704 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0,
3710 as_warn ("Instruction %s: result is always true",
3712 macro_build ((char *) NULL
, &icnt
, &expr1
,
3713 mips_isa
< 3 ? "addiu" : "daddiu",
3714 "t,r,j", dreg
, 0, (int) BFD_RELOC_LO16
);
3717 if (imm_expr
.X_add_number
>= 0 && imm_expr
.X_add_number
< 0x10000)
3719 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "xori", "t,r,i",
3720 dreg
, sreg
, (int) BFD_RELOC_LO16
);
3723 else if (imm_expr
.X_add_number
> -0x8000 && imm_expr
.X_add_number
< 0)
3725 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
3726 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
3727 mips_isa
< 3 ? "addiu" : "daddiu",
3728 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
3733 load_register (&icnt
, AT
, &imm_expr
);
3734 macro_build ((char *) NULL
, &icnt
, NULL
, "xor", "d,v,t", dreg
,
3738 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0, dreg
);
3746 if (imm_expr
.X_add_number
> -0x8000 && imm_expr
.X_add_number
<= 0x8000)
3748 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
3749 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
3750 dbl
? "daddi" : "addi",
3751 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
3754 load_register (&icnt
, AT
, &imm_expr
);
3755 macro_build ((char *) NULL
, &icnt
, NULL
,
3756 dbl
? "dsub" : "sub",
3757 "d,v,t", dreg
, sreg
, AT
);
3763 if (imm_expr
.X_add_number
> -0x8000 && imm_expr
.X_add_number
<= 0x8000)
3765 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
3766 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
3767 dbl
? "daddiu" : "addiu",
3768 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
3771 load_register (&icnt
, AT
, &imm_expr
);
3772 macro_build ((char *) NULL
, &icnt
, NULL
,
3773 dbl
? "dsubu" : "subu",
3774 "d,v,t", dreg
, sreg
, AT
);
3795 load_register (&icnt
, AT
, &imm_expr
);
3796 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "s,t", sreg
, AT
);
3801 assert (mips_isa
< 2);
3802 sreg
= (ip
->insn_opcode
>> 11) & 0x1f; /* floating reg */
3803 dreg
= (ip
->insn_opcode
>> 06) & 0x1f; /* floating reg */
3806 * Is the double cfc1 instruction a bug in the mips assembler;
3807 * or is there a reason for it?
3809 mips_emit_delays ();
3811 mips_any_noreorder
= 1;
3812 macro_build ((char *) NULL
, &icnt
, NULL
, "cfc1", "t,G", treg
, 31);
3813 macro_build ((char *) NULL
, &icnt
, NULL
, "cfc1", "t,G", treg
, 31);
3814 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "");
3815 expr1
.X_add_number
= 3;
3816 macro_build ((char *) NULL
, &icnt
, &expr1
, "ori", "t,r,i", AT
, treg
,
3817 (int) BFD_RELOC_LO16
);
3818 expr1
.X_add_number
= 2;
3819 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", AT
, AT
,
3820 (int) BFD_RELOC_LO16
);
3821 macro_build ((char *) NULL
, &icnt
, NULL
, "ctc1", "t,G", AT
, 31);
3822 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "");
3823 macro_build ((char *) NULL
, &icnt
, NULL
,
3824 mask
== M_TRUNCWD
? "cvt.w.d" : "cvt.w.s", "D,S", dreg
, sreg
);
3825 macro_build ((char *) NULL
, &icnt
, NULL
, "ctc1", "t,G", treg
, 31);
3826 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "");
3836 if (offset_expr
.X_add_number
>= 0x7fff)
3837 as_bad ("operand overflow");
3838 /* avoid load delay */
3839 if (byte_order
== LITTLE_ENDIAN
)
3840 offset_expr
.X_add_number
+= 1;
3841 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
3842 (int) BFD_RELOC_LO16
, breg
);
3843 if (byte_order
== LITTLE_ENDIAN
)
3844 offset_expr
.X_add_number
-= 1;
3846 offset_expr
.X_add_number
+= 1;
3847 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lbu", "t,o(b)", AT
,
3848 (int) BFD_RELOC_LO16
, breg
);
3849 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", treg
, treg
, 8);
3850 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", treg
, treg
, AT
);
3854 if (offset_expr
.X_add_number
>= 0x7ffd)
3855 as_bad ("operand overflow");
3856 if (byte_order
== LITTLE_ENDIAN
)
3857 offset_expr
.X_add_number
+= 3;
3858 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lwl", "t,o(b)", treg
,
3859 (int) BFD_RELOC_LO16
, breg
);
3860 if (byte_order
== LITTLE_ENDIAN
)
3861 offset_expr
.X_add_number
-= 3;
3863 offset_expr
.X_add_number
+= 3;
3864 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lwr", "t,o(b)", treg
,
3865 (int) BFD_RELOC_LO16
, breg
);
3871 load_address (&icnt
, AT
, &offset_expr
);
3872 if (mask
== M_ULW_A
)
3874 if (byte_order
== LITTLE_ENDIAN
)
3875 expr1
.X_add_number
= 3;
3877 expr1
.X_add_number
= 0;
3878 macro_build ((char *) NULL
, &icnt
, &expr1
, "lwl", "t,o(b)", treg
,
3879 (int) BFD_RELOC_LO16
, AT
);
3880 if (byte_order
== LITTLE_ENDIAN
)
3881 expr1
.X_add_number
= 0;
3883 expr1
.X_add_number
= 3;
3884 macro_build ((char *) NULL
, &icnt
, &expr1
, "lwr", "t,o(b)", treg
,
3885 (int) BFD_RELOC_LO16
, AT
);
3889 if (byte_order
== BIG_ENDIAN
)
3890 expr1
.X_add_number
= 0;
3891 macro_build ((char *) NULL
, &icnt
, &expr1
,
3892 mask
== M_ULH_A
? "lb" : "lbu", "t,o(b)", treg
,
3893 (int) BFD_RELOC_LO16
, AT
);
3894 if (byte_order
== BIG_ENDIAN
)
3895 expr1
.X_add_number
= 1;
3897 expr1
.X_add_number
= 0;
3898 macro_build ((char *) NULL
, &icnt
, &expr1
, "lbu", "t,o(b)", AT
,
3899 (int) BFD_RELOC_LO16
, AT
);
3900 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", treg
,
3902 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", treg
,
3908 if (offset_expr
.X_add_number
>= 0x7fff)
3909 as_bad ("operand overflow");
3910 if (byte_order
== BIG_ENDIAN
)
3911 offset_expr
.X_add_number
+= 1;
3912 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "sb", "t,o(b)", treg
,
3913 (int) BFD_RELOC_LO16
, breg
);
3914 macro_build ((char *) NULL
, &icnt
, NULL
, "srl", "d,w,<", AT
, treg
, 8);
3915 if (byte_order
== BIG_ENDIAN
)
3916 offset_expr
.X_add_number
-= 1;
3918 offset_expr
.X_add_number
+= 1;
3919 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "sb", "t,o(b)", AT
,
3920 (int) BFD_RELOC_LO16
, breg
);
3924 if (offset_expr
.X_add_number
>= 0x7ffd)
3925 as_bad ("operand overflow");
3926 if (byte_order
== LITTLE_ENDIAN
)
3927 offset_expr
.X_add_number
+= 3;
3928 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "swl", "t,o(b)", treg
,
3929 (int) BFD_RELOC_LO16
, breg
);
3930 if (byte_order
== LITTLE_ENDIAN
)
3931 offset_expr
.X_add_number
-= 3;
3933 offset_expr
.X_add_number
+= 3;
3934 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "swr", "t,o(b)", treg
,
3935 (int) BFD_RELOC_LO16
, breg
);
3940 load_address (&icnt
, AT
, &offset_expr
);
3941 if (mask
== M_USW_A
)
3943 if (byte_order
== LITTLE_ENDIAN
)
3944 expr1
.X_add_number
= 3;
3946 expr1
.X_add_number
= 0;
3947 macro_build ((char *) NULL
, &icnt
, &expr1
, "swl", "t,o(b)", treg
,
3948 (int) BFD_RELOC_LO16
, AT
);
3949 if (byte_order
== LITTLE_ENDIAN
)
3950 expr1
.X_add_number
= 0;
3952 expr1
.X_add_number
= 3;
3953 macro_build ((char *) NULL
, &icnt
, &expr1
, "swr", "t,o(b)", treg
,
3954 (int) BFD_RELOC_LO16
, AT
);
3958 if (byte_order
== LITTLE_ENDIAN
)
3959 expr1
.X_add_number
= 0;
3960 macro_build ((char *) NULL
, &icnt
, &expr1
, "sb", "t,o(b)", treg
,
3961 (int) BFD_RELOC_LO16
, AT
);
3962 macro_build ((char *) NULL
, &icnt
, NULL
, "srl", "d,w,<", treg
,
3964 if (byte_order
== LITTLE_ENDIAN
)
3965 expr1
.X_add_number
= 1;
3967 expr1
.X_add_number
= 0;
3968 macro_build ((char *) NULL
, &icnt
, &expr1
, "sb", "t,o(b)", treg
,
3969 (int) BFD_RELOC_LO16
, AT
);
3970 if (byte_order
== LITTLE_ENDIAN
)
3971 expr1
.X_add_number
= 0;
3973 expr1
.X_add_number
= 1;
3974 macro_build ((char *) NULL
, &icnt
, &expr1
, "lbu", "t,o(b)", AT
,
3975 (int) BFD_RELOC_LO16
, AT
);
3976 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", treg
,
3978 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", treg
,
3984 as_bad ("Macro %s not implemented yet", ip
->insn_mo
->name
);
3988 as_warn ("Macro used $at after \".set noat\"");
3993 This routine assembles an instruction into its binary format. As a side
3994 effect it sets one of the global variables imm_reloc or offset_reloc to the
3995 type of relocation to do if one of the operands is an address expression.
4000 struct mips_cl_insn
*ip
;
4005 struct mips_opcode
*insn
;
4008 unsigned int lastregno
= 0;
4013 for (s
= str
; islower (*s
) || (*s
>= '0' && *s
<= '3') || *s
== '.'; ++s
)
4025 as_warn ("Unknown opcode: `%s'", str
);
4028 if ((insn
= (struct mips_opcode
*) hash_find (op_hash
, str
)) == NULL
)
4030 as_warn ("`%s' not in hash table.", str
);
4031 insn_error
= "ERROR: Unrecognized opcode";
4039 assert (strcmp (insn
->name
, str
) == 0);
4041 if (insn
->pinfo
== INSN_MACRO
)
4042 insn_isa
= insn
->match
;
4043 else if (insn
->pinfo
& INSN_ISA2
)
4045 else if (insn
->pinfo
& INSN_ISA3
)
4050 if (insn_isa
> mips_isa
)
4052 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
]
4053 && strcmp (insn
->name
, insn
[1].name
) == 0)
4058 as_warn ("Instruction not supported on this processor");
4062 ip
->insn_opcode
= insn
->match
;
4063 for (args
= insn
->args
;; ++args
)
4069 case '\0': /* end of args */
4082 ip
->insn_opcode
|= lastregno
<< 21;
4087 ip
->insn_opcode
|= lastregno
<< 16;
4091 ip
->insn_opcode
|= lastregno
<< 11;
4097 /* handle optional base register.
4098 Either the base register is omitted or
4099 we must have a left paren. */
4100 /* this is dependent on the next operand specifier
4101 is a 'b' for base register */
4102 assert (args
[1] == 'b');
4106 case ')': /* these must match exactly */
4111 case '<': /* must be at least one digit */
4113 * According to the manual, if the shift amount is greater
4114 * than 31 or less than 0 the the shift amount should be
4115 * mod 32. In reality the mips assembler issues an error.
4116 * We issue a warning and mask out all but the low 5 bits.
4118 my_getExpression (&imm_expr
, s
);
4119 check_absolute_expr (ip
, &imm_expr
);
4120 if ((unsigned long) imm_expr
.X_add_number
> 31)
4122 as_warn ("Improper shift amount (%ld)",
4123 (long) imm_expr
.X_add_number
);
4124 imm_expr
.X_add_number
= imm_expr
.X_add_number
& 0x1f;
4126 ip
->insn_opcode
|= imm_expr
.X_add_number
<< 6;
4127 imm_expr
.X_op
= O_absent
;
4131 case '>': /* shift amount minus 32 */
4132 my_getExpression (&imm_expr
, s
);
4133 check_absolute_expr (ip
, &imm_expr
);
4134 if ((unsigned long) imm_expr
.X_add_number
< 32
4135 || (unsigned long) imm_expr
.X_add_number
> 63)
4137 ip
->insn_opcode
|= (imm_expr
.X_add_number
- 32) << 6;
4138 imm_expr
.X_op
= O_absent
;
4142 case 'k': /* cache code */
4143 my_getExpression (&imm_expr
, s
);
4144 check_absolute_expr (ip
, &imm_expr
);
4145 if ((unsigned long) imm_expr
.X_add_number
> 31)
4147 as_warn ("Invalid cahce opcode (%lu)",
4148 (unsigned long) imm_expr
.X_add_number
);
4149 imm_expr
.X_add_number
&= 0x1f;
4151 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_CACHE
;
4152 imm_expr
.X_op
= O_absent
;
4156 case 'c': /* break code */
4157 my_getExpression (&imm_expr
, s
);
4158 check_absolute_expr (ip
, &imm_expr
);
4159 if ((unsigned) imm_expr
.X_add_number
> 1023)
4160 as_warn ("Illegal break code (%ld)",
4161 (long) imm_expr
.X_add_number
);
4162 ip
->insn_opcode
|= imm_expr
.X_add_number
<< 16;
4163 imm_expr
.X_op
= O_absent
;
4167 case 'B': /* syscall code */
4168 my_getExpression (&imm_expr
, s
);
4169 check_absolute_expr (ip
, &imm_expr
);
4170 if ((unsigned) imm_expr
.X_add_number
> 0xfffff)
4171 as_warn ("Illegal syscall code (%ld)",
4172 (long) imm_expr
.X_add_number
);
4173 ip
->insn_opcode
|= imm_expr
.X_add_number
<< 6;
4174 imm_expr
.X_op
= O_absent
;
4178 case 'C': /* Coprocessor code */
4179 my_getExpression (&imm_expr
, s
);
4180 check_absolute_expr (ip
, &imm_expr
);
4181 if ((unsigned long) imm_expr
.X_add_number
>= (1<<25))
4183 as_warn ("Coproccesor code > 25 bits (%ld)",
4184 (long) imm_expr
.X_add_number
);
4185 imm_expr
.X_add_number
&= ((1<<25) - 1);
4187 ip
->insn_opcode
|= imm_expr
.X_add_number
;
4188 imm_expr
.X_op
= O_absent
;
4192 case 'b': /* base register */
4193 case 'd': /* destination register */
4194 case 's': /* source register */
4195 case 't': /* target register */
4196 case 'r': /* both target and source */
4197 case 'v': /* both dest and source */
4198 case 'w': /* both dest and target */
4199 case 'E': /* coprocessor target register */
4200 case 'G': /* coprocessor destination register */
4201 case 'x': /* ignore register name */
4202 case 'z': /* must be zero register */
4216 while (isdigit (*s
));
4218 as_bad ("Invalid register number (%d)", regno
);
4220 else if (*args
== 'E' || *args
== 'G')
4224 if (s
[1] == 'f' && s
[2] == 'p')
4229 else if (s
[1] == 's' && s
[2] == 'p')
4234 else if (s
[1] == 'g' && s
[2] == 'p')
4239 else if (s
[1] == 'a' && s
[2] == 't')
4247 if (regno
== AT
&& ! mips_noat
)
4248 as_warn ("Used $at without \".set noat\"");
4254 if (c
== 'r' || c
== 'v' || c
== 'w')
4261 /* 'z' only matches $0. */
4262 if (c
== 'z' && regno
!= 0)
4270 ip
->insn_opcode
|= regno
<< 21;
4274 ip
->insn_opcode
|= regno
<< 11;
4279 ip
->insn_opcode
|= regno
<< 16;
4282 /* This case exists because on the r3000 trunc
4283 expands into a macro which requires a gp
4284 register. On the r6000 or r4000 it is
4285 assembled into a single instruction which
4286 ignores the register. Thus the insn version
4287 is MIPS_ISA2 and uses 'x', and the macro
4288 version is MIPS_ISA1 and uses 't'. */
4291 /* This case is for the div instruction, which
4292 acts differently if the destination argument
4293 is $0. This only matches $0, and is checked
4294 outside the switch. */
4305 ip
->insn_opcode
|= lastregno
<< 21;
4308 ip
->insn_opcode
|= lastregno
<< 16;
4313 case 'D': /* floating point destination register */
4314 case 'S': /* floating point source register */
4315 case 'T': /* floating point target register */
4319 if (s
[0] == '$' && s
[1] == 'f' && isdigit (s
[2]))
4329 while (isdigit (*s
));
4332 as_bad ("Invalid float register number (%d)", regno
);
4334 if ((regno
& 1) != 0
4336 && ! (strcmp (str
, "mtc1") == 0 ||
4337 strcmp (str
, "mfc1") == 0 ||
4338 strcmp (str
, "lwc1") == 0 ||
4339 strcmp (str
, "swc1") == 0))
4340 as_warn ("Float register should be even, was %d",
4348 if (c
== 'V' || c
== 'W')
4358 ip
->insn_opcode
|= regno
<< 6;
4362 ip
->insn_opcode
|= regno
<< 11;
4366 ip
->insn_opcode
|= regno
<< 16;
4374 ip
->insn_opcode
|= lastregno
<< 11;
4377 ip
->insn_opcode
|= lastregno
<< 16;
4383 my_getExpression (&imm_expr
, s
);
4384 check_absolute_expr (ip
, &imm_expr
);
4389 my_getExpression (&offset_expr
, s
);
4390 imm_reloc
= BFD_RELOC_32
;
4402 unsigned char temp
[8];
4404 unsigned int length
;
4409 /* These only appear as the last operand in an
4410 instruction, and every instruction that accepts
4411 them in any variant accepts them in all variants.
4412 This means we don't have to worry about backing out
4413 any changes if the instruction does not match.
4415 The difference between them is the size of the
4416 floating point constant and where it goes. For 'F'
4417 and 'L' the constant is 64 bits; for 'f' and 'l' it
4418 is 32 bits. Where the constant is placed is based
4419 on how the MIPS assembler does things:
4422 f -- immediate value
4425 When generating SVR4 PIC code, we do not use the
4426 .lit8 or .lit4 sections at all, in order to
4427 reserve the entire global offset table. When
4428 generating embedded PIC code, we use the .lit8
4429 section but not the .lit4 section (we can do .lit4
4430 inline easily; we need to put .lit8 somewhere in
4431 the data segment, and using .lit8 permits the
4432 linker to eventually combine identical .lit8
4435 f64
= *args
== 'F' || *args
== 'L';
4437 save_in
= input_line_pointer
;
4438 input_line_pointer
= s
;
4439 err
= md_atof (f64
? 'd' : 'f', (char *) temp
, &len
);
4441 s
= input_line_pointer
;
4442 input_line_pointer
= save_in
;
4443 if (err
!= NULL
&& *err
!= '\0')
4445 as_bad ("Bad floating point constant: %s", err
);
4446 memset (temp
, '\0', sizeof temp
);
4447 length
= f64
? 8 : 4;
4450 assert (length
== (f64
? 8 : 4));
4453 || (mips_pic
!= NO_PIC
&& *args
== 'l'))
4455 imm_expr
.X_op
= O_constant
;
4456 if (byte_order
== LITTLE_ENDIAN
)
4457 imm_expr
.X_add_number
=
4458 (((((((int) temp
[3] << 8)
4463 imm_expr
.X_add_number
=
4464 (((((((int) temp
[0] << 8)
4471 const char *newname
;
4474 /* Switch to the right section. */
4476 subseg
= now_subseg
;
4479 default: /* unused default case avoids warnings. */
4481 newname
= (mips_pic
!= SVR4_PIC
? ".lit8" : ".rdata");
4487 assert (mips_pic
== NO_PIC
);
4491 new_seg
= subseg_new (newname
, (subsegT
) 0);
4492 frag_align (*args
== 'l' ? 2 : 3, 0);
4494 record_alignment (new_seg
, 4);
4496 record_alignment (new_seg
, *args
== 'l' ? 2 : 3);
4499 as_bad ("Can't use floating point insn in this section");
4501 /* Set the argument to the current address in the
4503 offset_expr
.X_op
= O_symbol
;
4504 offset_expr
.X_add_symbol
=
4505 symbol_new ("L0\001", now_seg
,
4506 (valueT
) frag_now_fix (), frag_now
);
4507 offset_expr
.X_add_number
= 0;
4509 /* Put the floating point number into the section. */
4510 p
= frag_more ((int) length
);
4511 memcpy (p
, temp
, length
);
4513 /* Switch back to the original section. */
4514 subseg_set (seg
, subseg
);
4519 case 'i': /* 16 bit unsigned immediate */
4520 case 'j': /* 16 bit signed immediate */
4521 imm_reloc
= BFD_RELOC_LO16
;
4522 c
= my_getSmallExpression (&imm_expr
, s
);
4527 if (imm_expr
.X_op
== O_constant
)
4528 imm_expr
.X_add_number
=
4529 (imm_expr
.X_add_number
>> 16) & 0xffff;
4531 imm_reloc
= BFD_RELOC_HI16_S
;
4533 imm_reloc
= BFD_RELOC_HI16
;
4537 check_absolute_expr (ip
, &imm_expr
);
4540 if (imm_expr
.X_add_number
< 0
4541 || imm_expr
.X_add_number
>= 0x10000)
4543 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
4544 !strcmp (insn
->name
, insn
[1].name
))
4546 as_bad ("16 bit expression not in range 0..65535");
4554 /* The upper bound should be 0x8000, but
4555 unfortunately the MIPS assembler accepts numbers
4556 from 0x8000 to 0xffff and sign extends them, and
4557 we want to be compatible. We only permit this
4558 extended range for an instruction which does not
4559 provide any further alternates, since those
4560 alternates may handle other cases. People should
4561 use the numbers they mean, rather than relying on
4562 a mysterious sign extension. */
4563 more
= (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
4564 strcmp (insn
->name
, insn
[1].name
) == 0);
4569 if (imm_expr
.X_add_number
< -0x8000 ||
4570 imm_expr
.X_add_number
>= max
)
4574 as_bad ("16 bit expression not in range -32768..32767");
4580 case 'o': /* 16 bit offset */
4581 c
= my_getSmallExpression (&offset_expr
, s
);
4583 /* If this value won't fit into a 16 bit offset, then go
4584 find a macro that will generate the 32 bit offset
4585 code pattern. As a special hack, we accept the
4586 difference of two local symbols as a constant. This
4587 is required to suppose embedded PIC switches, which
4588 use an instruction which looks like
4589 lw $4,$L12-$LS12($4)
4590 The problem with handling this in a more general
4591 fashion is that the macro function doesn't expect to
4592 see anything which can be handled in a single
4593 constant instruction. */
4594 if ((offset_expr
.X_op
!= O_constant
4595 || offset_expr
.X_add_number
>= 0x8000
4596 || offset_expr
.X_add_number
< -0x8000)
4597 && (mips_pic
!= EMBEDDED_PIC
4598 || offset_expr
.X_op
!= O_subtract
4599 || ! S_IS_LOCAL (offset_expr
.X_add_symbol
)
4600 || ! S_IS_LOCAL (offset_expr
.X_op_symbol
)))
4603 offset_reloc
= BFD_RELOC_LO16
;
4604 if (c
== 'h' || c
== 'H')
4606 assert (offset_expr
.X_op
== O_constant
);
4607 offset_expr
.X_add_number
=
4608 (offset_expr
.X_add_number
>> 16) & 0xffff;
4613 case 'p': /* pc relative offset */
4614 offset_reloc
= BFD_RELOC_16_PCREL_S2
;
4615 my_getExpression (&offset_expr
, s
);
4619 case 'u': /* upper 16 bits */
4620 c
= my_getSmallExpression (&imm_expr
, s
);
4621 if (imm_expr
.X_op
!= O_constant
4622 || imm_expr
.X_add_number
< 0
4623 || imm_expr
.X_add_number
>= 0x10000)
4624 as_bad ("lui expression not in range 0..65535");
4625 imm_reloc
= BFD_RELOC_LO16
;
4630 if (imm_expr
.X_op
== O_constant
)
4631 imm_expr
.X_add_number
=
4632 (imm_expr
.X_add_number
>> 16) & 0xffff;
4634 imm_reloc
= BFD_RELOC_HI16_S
;
4636 imm_reloc
= BFD_RELOC_HI16
;
4642 case 'a': /* 26 bit address */
4643 my_getExpression (&offset_expr
, s
);
4645 offset_reloc
= BFD_RELOC_MIPS_JMP
;
4649 fprintf (stderr
, "bad char = '%c'\n", *args
);
4654 /* Args don't match. */
4655 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
4656 !strcmp (insn
->name
, insn
[1].name
))
4662 insn_error
= "ERROR: Illegal operands";
4671 my_getSmallExpression (ep
, str
)
4682 ((str
[1] == 'h' && str
[2] == 'i')
4683 || (str
[1] == 'H' && str
[2] == 'I')
4684 || (str
[1] == 'l' && str
[2] == 'o'))
4696 * A small expression may be followed by a base register.
4697 * Scan to the end of this operand, and then back over a possible
4698 * base register. Then scan the small expression up to that
4699 * point. (Based on code in sparc.c...)
4701 for (sp
= str
; *sp
&& *sp
!= ','; sp
++)
4703 if (sp
- 4 >= str
&& sp
[-1] == RP
)
4705 if (isdigit (sp
[-2]))
4707 for (sp
-= 3; sp
>= str
&& isdigit (*sp
); sp
--)
4709 if (*sp
== '$' && sp
> str
&& sp
[-1] == LP
)
4715 else if (sp
- 5 >= str
4718 && ((sp
[-3] == 'f' && sp
[-2] == 'p')
4719 || (sp
[-3] == 's' && sp
[-2] == 'p')
4720 || (sp
[-3] == 'g' && sp
[-2] == 'p')
4721 || (sp
[-3] == 'a' && sp
[-2] == 't')))
4727 /* no expression means zero offset */
4730 /* %xx(reg) is an error */
4731 ep
->X_op
= O_absent
;
4736 ep
->X_op
= O_constant
;
4739 ep
->X_add_symbol
= NULL
;
4740 ep
->X_op_symbol
= NULL
;
4741 ep
->X_add_number
= 0;
4746 my_getExpression (ep
, str
);
4753 my_getExpression (ep
, str
);
4754 return c
; /* => %hi or %lo encountered */
4758 my_getExpression (ep
, str
)
4764 save_in
= input_line_pointer
;
4765 input_line_pointer
= str
;
4767 expr_end
= input_line_pointer
;
4768 input_line_pointer
= save_in
;
4771 /* Turn a string in input_line_pointer into a floating point constant
4772 of type type, and store the appropriate bytes in *litP. The number
4773 of LITTLENUMS emitted is stored in *sizeP . An error message is
4774 returned, or NULL on OK. */
4777 md_atof (type
, litP
, sizeP
)
4783 LITTLENUM_TYPE words
[4];
4799 return "bad call to md_atof";
4802 t
= atof_ieee (input_line_pointer
, type
, words
);
4804 input_line_pointer
= t
;
4808 if (byte_order
== LITTLE_ENDIAN
)
4810 for (i
= prec
- 1; i
>= 0; i
--)
4812 md_number_to_chars (litP
, (valueT
) words
[i
], 2);
4818 for (i
= 0; i
< prec
; i
++)
4820 md_number_to_chars (litP
, (valueT
) words
[i
], 2);
4829 md_number_to_chars (buf
, val
, n
)
4837 number_to_chars_littleendian (buf
, val
, n
);
4841 number_to_chars_bigendian (buf
, val
, n
);
4850 CONST
char *md_shortopts
= "E:O::g::G:";
4852 CONST
char *md_shortopts
= "E:O::g::";
4854 struct option md_longopts
[] = {
4855 #define OPTION_MIPS1 (OPTION_MD_BASE + 1)
4856 {"mips0", no_argument
, NULL
, OPTION_MIPS1
},
4857 {"mips1", no_argument
, NULL
, OPTION_MIPS1
},
4858 #define OPTION_MIPS2 (OPTION_MD_BASE + 2)
4859 {"mips2", no_argument
, NULL
, OPTION_MIPS2
},
4860 #define OPTION_MIPS3 (OPTION_MD_BASE + 3)
4861 {"mips3", no_argument
, NULL
, OPTION_MIPS3
},
4862 #define OPTION_MCPU (OPTION_MD_BASE + 4)
4863 {"mcpu", required_argument
, NULL
, OPTION_MCPU
},
4864 #define OPTION_MEMBEDDED_PIC (OPTION_MD_BASE + 5)
4865 {"membedded-pic", no_argument
, NULL
, OPTION_MEMBEDDED_PIC
},
4866 #define OPTION_TRAP (OPTION_MD_BASE + 8)
4867 {"trap", no_argument
, NULL
, OPTION_TRAP
},
4868 {"no-break", no_argument
, NULL
, OPTION_TRAP
},
4869 #define OPTION_BREAK (OPTION_MD_BASE + 9)
4870 {"break", no_argument
, NULL
, OPTION_BREAK
},
4871 {"no-trap", no_argument
, NULL
, OPTION_BREAK
},
4874 #define OPTION_CALL_SHARED (OPTION_MD_BASE + 6)
4875 {"KPIC", no_argument
, NULL
, OPTION_CALL_SHARED
},
4876 {"call_shared", no_argument
, NULL
, OPTION_CALL_SHARED
},
4877 #define OPTION_NON_SHARED (OPTION_MD_BASE + 7)
4878 {"non_shared", no_argument
, NULL
, OPTION_NON_SHARED
},
4881 {NULL
, no_argument
, NULL
, 0}
4883 size_t md_longopts_size
= sizeof(md_longopts
);
4886 md_parse_option (c
, arg
)
4902 byte_order
= BIG_ENDIAN
;
4903 else if (arg
[1] == 'L')
4904 byte_order
= LITTLE_ENDIAN
;
4907 as_bad("invalid endianness -E%c", arg
[1]);
4913 mips_target_format
= "a.out-mips-big";
4915 mips_target_format
= "a.out-mips-little";
4919 mips_target_format
= "ecoff-bigmips";
4921 mips_target_format
= "ecoff-littlemips";
4925 mips_target_format
= "elf32-bigmips";
4927 mips_target_format
= "elf32-littlemips";
4930 /* FIXME: This breaks -L -EL. */
4931 flag_keep_locals
= 0;
4935 if (arg
&& arg
[1] == '0')
4942 if (arg
== NULL
|| arg
[1] == '2')
4962 /* Identify the processor type */
4964 if (strcmp (p
, "default") == 0
4965 || strcmp (p
, "DEFAULT") == 0)
4969 if (*p
== 'r' || *p
== 'R')
4976 if (strcmp (p
, "2000") == 0
4977 || strcmp (p
, "2k") == 0
4978 || strcmp (p
, "2K") == 0)
4983 if (strcmp (p
, "3000") == 0
4984 || strcmp (p
, "3k") == 0
4985 || strcmp (p
, "3K") == 0)
4990 if (strcmp (p
, "4000") == 0
4991 || strcmp (p
, "4k") == 0
4992 || strcmp (p
, "4K") == 0)
4997 if (strcmp (p
, "6000") == 0
4998 || strcmp (p
, "6k") == 0
4999 || strcmp (p
, "6K") == 0)
5006 as_bad ("invalid architecture -mcpu=%s", arg
);
5013 case OPTION_MEMBEDDED_PIC
:
5014 mips_pic
= EMBEDDED_PIC
;
5018 as_bad ("-G may not be used with embedded PIC code");
5021 g_switch_value
= 0x7fffffff;
5026 /* When generating ELF code, we permit -KPIC and -call_shared to
5027 select SVR4_PIC, and -non_shared to select no PIC. This is
5028 intended to be compatible with Irix 5. */
5029 case OPTION_CALL_SHARED
:
5030 mips_pic
= SVR4_PIC
;
5031 if (g_switch_seen
&& g_switch_value
!= 0)
5033 as_bad ("-G may not be used with SVR4 PIC code");
5039 case OPTION_NON_SHARED
:
5042 #endif /* OBJ_ELF */
5046 if (mips_pic
== SVR4_PIC
|| mips_pic
== EMBEDDED_PIC
)
5048 as_bad ("-G may not be used with SVR4 or embedded PIC code");
5052 g_switch_value
= atoi (arg
);
5065 md_show_usage (stream
)
5070 -membedded-pic generate embedded position independent code\n\
5072 -EB generate big endian output\n\
5073 -EL generate little endian output\n\
5074 -g, -g2 do not remove uneeded NOPs or swap branches\n\
5075 -G NUM allow referencing objects up to NUM bytes\n\
5076 implicitly with the gp register [default 8]\n\
5077 -mips1, -mcpu=r{2,3}000 generate code for r2000 and r3000\n\
5078 -mips2, -mcpu=r6000 generate code for r6000\n\
5079 -mips3, -mcpu=r4000 generate code for r4000\n\
5080 -O0 remove unneeded NOPs, do not swap branches\n\
5081 -O remove unneeded NOPs and swap branches\n\
5082 --trap, --no-break trap exception on div by 0 and mult overflow\n\
5083 --break, --no-trap break exception on div by 0 and mult overflow\n");
5086 -KPIC, -call_shared generate SVR4 position independent code\n\
5087 -non_shared do not generate position independent code\n");
5092 md_pcrel_from (fixP
)
5096 if (fixP
->fx_addsy
!= (symbolS
*) NULL
5097 && ! S_IS_DEFINED (fixP
->fx_addsy
))
5099 /* This makes a branch to an undefined symbol be a branch to the
5100 current location. */
5105 /* return the address of the delay slot */
5106 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
5109 /* This is called by emit_expr via TC_CONS_FIX_NEW when creating a
5110 reloc for a cons. We could use the definition there, except that
5111 we want to handle 64 bit relocs specially. */
5114 cons_fix_new_mips (frag
, where
, nbytes
, exp
)
5117 unsigned int nbytes
;
5120 /* If we are assembling in 32 bit mode, turn an 8 byte reloc into a
5122 FIXME: There is no way to select anything but 32 bit mode right
5126 if (byte_order
== BIG_ENDIAN
)
5131 if (nbytes
!= 2 && nbytes
!= 4)
5132 as_bad ("Unsupported reloc size %d", nbytes
);
5134 fix_new_exp (frag_now
, where
, (int) nbytes
, exp
, 0,
5135 nbytes
== 2 ? BFD_RELOC_16
: BFD_RELOC_32
);
5138 /* When generating embedded PIC code we need to use a special
5139 relocation to represent the difference of two symbols in the .text
5140 section (switch tables use a difference of this sort). See
5141 include/coff/mips.h for details. This macro checks whether this
5142 fixup requires the special reloc. */
5143 #define SWITCH_TABLE(fixp) \
5144 ((fixp)->fx_r_type == BFD_RELOC_32 \
5145 && (fixp)->fx_addsy != NULL \
5146 && (fixp)->fx_subsy != NULL \
5147 && S_GET_SEGMENT ((fixp)->fx_addsy) == text_section \
5148 && S_GET_SEGMENT ((fixp)->fx_subsy) == text_section)
5150 /* When generating embedded PIC code we must keep all PC relative
5151 relocations, in case the linker has to relax a call. We also need
5152 to keep relocations for switch table entries. */
5156 mips_force_relocation (fixp
)
5159 return (mips_pic
== EMBEDDED_PIC
5161 || SWITCH_TABLE (fixp
)
5162 || fixp
->fx_r_type
== BFD_RELOC_PCREL_HI16_S
5163 || fixp
->fx_r_type
== BFD_RELOC_PCREL_LO16
));
5166 /* Apply a fixup to the object file. */
5169 md_apply_fix (fixP
, valueP
)
5176 assert (fixP
->fx_size
== 4);
5179 fixP
->fx_addnumber
= value
; /* Remember value for tc_gen_reloc */
5181 if (fixP
->fx_addsy
== NULL
&& ! fixP
->fx_pcrel
)
5184 switch (fixP
->fx_r_type
)
5186 case BFD_RELOC_MIPS_JMP
:
5187 case BFD_RELOC_HI16
:
5188 case BFD_RELOC_HI16_S
:
5189 case BFD_RELOC_MIPS_GPREL
:
5190 case BFD_RELOC_MIPS_LITERAL
:
5191 case BFD_RELOC_MIPS_CALL16
:
5192 case BFD_RELOC_MIPS_GOT16
:
5193 case BFD_RELOC_MIPS_GPREL32
:
5195 as_bad ("Invalid PC relative reloc");
5196 /* Nothing needed to do. The value comes from the reloc entry */
5199 case BFD_RELOC_PCREL_HI16_S
:
5200 /* The addend for this is tricky if it is internal, so we just
5201 do everything here rather than in bfd_perform_relocation. */
5202 if ((fixP
->fx_addsy
->bsym
->flags
& BSF_SECTION_SYM
) == 0)
5204 /* For an external symbol adjust by the address to make it
5205 pcrel_offset. We use the address of the RELLO reloc
5206 which follows this one. */
5207 value
+= (fixP
->fx_next
->fx_frag
->fr_address
5208 + fixP
->fx_next
->fx_where
);
5213 buf
= (unsigned char *) fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
5214 if (byte_order
== BIG_ENDIAN
)
5216 md_number_to_chars (buf
, value
, 2);
5219 case BFD_RELOC_PCREL_LO16
:
5220 /* The addend for this is tricky if it is internal, so we just
5221 do everything here rather than in bfd_perform_relocation. */
5222 if ((fixP
->fx_addsy
->bsym
->flags
& BSF_SECTION_SYM
) == 0)
5223 value
+= fixP
->fx_frag
->fr_address
+ fixP
->fx_where
;
5224 buf
= (unsigned char *) fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
5225 if (byte_order
== BIG_ENDIAN
)
5227 md_number_to_chars (buf
, value
, 2);
5231 /* If we are deleting this reloc entry, we must fill in the
5232 value now. This can happen if we have a .word which is not
5233 resolved when it appears but is later defined. We also need
5234 to fill in the value if this is an embedded PIC switch table
5237 || (mips_pic
== EMBEDDED_PIC
&& SWITCH_TABLE (fixP
)))
5238 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
,
5242 case BFD_RELOC_LO16
:
5243 /* When handling an embedded PIC switch statement, we can wind
5244 up deleting a LO16 reloc. See the 'o' case in mips_ip. */
5247 if (value
< -0x8000 || value
> 0x7fff)
5248 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
5249 "relocation overflow");
5250 buf
= (unsigned char *) fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
5251 if (byte_order
== BIG_ENDIAN
)
5253 md_number_to_chars (buf
, value
, 2);
5257 case BFD_RELOC_16_PCREL_S2
:
5259 * We need to save the bits in the instruction since fixup_segment()
5260 * might be deleting the relocation entry (i.e., a branch within
5261 * the current segment).
5264 as_warn ("Branch to odd address (%lx)", value
);
5266 if ((value
& ~0xFFFF) && (value
& ~0xFFFF) != (-1 & ~0xFFFF))
5267 as_bad ("Relocation overflow");
5269 /* update old instruction data */
5270 buf
= (unsigned char *) (fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
);
5274 insn
= (buf
[3] << 24) | (buf
[2] << 16) | (buf
[1] << 8) | buf
[0];
5278 insn
= (buf
[0] << 24) | (buf
[1] << 16) | (buf
[2] << 8) | buf
[3];
5285 insn
|= value
& 0xFFFF;
5286 md_number_to_chars ((char *) buf
, (valueT
) insn
, 4);
5301 const struct mips_opcode
*p
;
5302 int treg
, sreg
, dreg
, shamt
;
5307 for (i
= 0; i
< NUMOPCODES
; ++i
)
5309 p
= &mips_opcodes
[i
];
5310 if (((oc
& p
->mask
) == p
->match
) && (p
->pinfo
!= INSN_MACRO
))
5312 printf ("%08lx %s\t", oc
, p
->name
);
5313 treg
= (oc
>> 16) & 0x1f;
5314 sreg
= (oc
>> 21) & 0x1f;
5315 dreg
= (oc
>> 11) & 0x1f;
5316 shamt
= (oc
>> 6) & 0x1f;
5318 for (args
= p
->args
;; ++args
)
5329 printf ("%c", *args
);
5333 assert (treg
== sreg
);
5334 printf ("$%d,$%d", treg
, sreg
);
5339 printf ("$%d", dreg
);
5344 printf ("$%d", treg
);
5348 printf ("0x%x", treg
);
5353 printf ("$%d", sreg
);
5357 printf ("0x%08lx", oc
& 0x1ffffff);
5369 printf ("$%d", shamt
);
5380 printf ("%08lx UNDEFINED\n", oc
);
5391 name
= input_line_pointer
;
5392 c
= get_symbol_end ();
5393 p
= (symbolS
*) symbol_find_or_make (name
);
5394 *input_line_pointer
= c
;
5398 /* Align the current frag to a given power of two. The MIPS assembler
5399 also automatically adjusts any preceding label. */
5402 mips_align (to
, fill
, label
)
5407 mips_emit_delays ();
5408 frag_align (to
, fill
);
5409 record_alignment (now_seg
, to
);
5412 assert (S_GET_SEGMENT (label
) == now_seg
);
5413 label
->sy_frag
= frag_now
;
5414 S_SET_VALUE (label
, (valueT
) frag_now_fix ());
5418 /* Align to a given power of two. .align 0 turns off the automatic
5419 alignment used by the data creating pseudo-ops. */
5426 register long temp_fill
;
5427 long max_alignment
= 15;
5431 o Note that the assembler pulls down any immediately preceeding label
5432 to the aligned address.
5433 o It's not documented but auto alignment is reinstated by
5434 a .align pseudo instruction.
5435 o Note also that after auto alignment is turned off the mips assembler
5436 issues an error on attempt to assemble an improperly aligned data item.
5441 temp
= get_absolute_expression ();
5442 if (temp
> max_alignment
)
5443 as_bad ("Alignment too large: %d. assumed.", temp
= max_alignment
);
5446 as_warn ("Alignment negative: 0 assumed.");
5449 if (*input_line_pointer
== ',')
5451 input_line_pointer
++;
5452 temp_fill
= get_absolute_expression ();
5459 mips_align (temp
, (int) temp_fill
, insn_label
);
5466 demand_empty_rest_of_line ();
5469 /* Handle .ascii and .asciiz. This just calls stringer and forgets
5470 that there was a previous instruction. */
5473 s_stringer (append_zero
)
5476 mips_emit_delays ();
5478 stringer (append_zero
);
5489 /* When generating embedded PIC code, we only use the .text, .lit8,
5490 .sdata and .sbss sections. We change the .data and .rdata
5491 pseudo-ops to use .sdata. */
5492 if (mips_pic
== EMBEDDED_PIC
5493 && (sec
== 'd' || sec
== 'r'))
5496 mips_emit_delays ();
5506 subseg_set (bss_section
, (subsegT
) get_absolute_expression ());
5507 demand_empty_rest_of_line ();
5512 subseg_new (".rdata", (subsegT
) get_absolute_expression ());
5513 demand_empty_rest_of_line ();
5515 #else /* ! defined (OBJ_ECOFF) */
5517 seg
= subseg_new (".rodata", (subsegT
) get_absolute_expression ());
5518 bfd_set_section_flags (stdoutput
, seg
,
5524 bfd_set_section_alignment (stdoutput
, seg
, 4);
5525 demand_empty_rest_of_line ();
5527 #else /* ! defined (OBJ_ELF) */
5530 #endif /* ! defined (OBJ_ELF) */
5531 #endif /* ! defined (OBJ_ECOFF) */
5535 seg
= subseg_new (".sdata", (subsegT
) get_absolute_expression ());
5537 bfd_set_section_flags (stdoutput
, seg
,
5538 SEC_ALLOC
| SEC_LOAD
| SEC_RELOC
| SEC_DATA
);
5539 bfd_set_section_alignment (stdoutput
, seg
, 4);
5541 demand_empty_rest_of_line ();
5543 #else /* ! defined (GPOPT) */
5544 as_bad ("Global pointers not supported; recompile -G 0");
5545 demand_empty_rest_of_line ();
5547 #endif /* ! defined (GPOPT) */
5560 mips_emit_delays ();
5561 if (log_size
> 0 && auto_align
)
5562 mips_align (log_size
, 0, label
);
5564 cons (1 << log_size
);
5571 as_fatal ("Encountered `.err', aborting assembly");
5581 symbolP
= get_symbol ();
5582 if (*input_line_pointer
== ',')
5583 input_line_pointer
++;
5584 size
= get_absolute_expression ();
5585 S_SET_EXTERNAL (symbolP
);
5587 #ifdef ECOFF_DEBUGGING
5588 symbolP
->ecoff_extern_size
= size
;
5600 mips_emit_delays ();
5604 mips_align (3, 0, label
);
5606 mips_align (2, 0, label
);
5620 opt
= input_line_pointer
;
5621 c
= get_symbol_end ();
5625 /* FIXME: What does this mean? */
5627 else if (strncmp (opt
, "pic", 3) == 0)
5635 mips_pic
= SVR4_PIC
;
5637 as_bad (".option pic%d not supported", i
);
5640 if (mips_pic
== SVR4_PIC
)
5642 if (g_switch_seen
&& g_switch_value
!= 0)
5643 as_warn ("-G may not be used with SVR4 PIC code");
5645 bfd_set_gp_size (stdoutput
, 0);
5650 as_warn ("Unrecognized option \"%s\"", opt
);
5652 *input_line_pointer
= c
;
5653 demand_empty_rest_of_line ();
5660 char *name
= input_line_pointer
, ch
;
5662 while (!is_end_of_line
[(unsigned char) *input_line_pointer
])
5663 input_line_pointer
++;
5664 ch
= *input_line_pointer
;
5665 *input_line_pointer
= '\0';
5667 if (strcmp (name
, "reorder") == 0)
5671 prev_insn_unreordered
= 1;
5672 prev_prev_insn_unreordered
= 1;
5676 else if (strcmp (name
, "noreorder") == 0)
5678 mips_emit_delays ();
5680 mips_any_noreorder
= 1;
5682 else if (strcmp (name
, "at") == 0)
5686 else if (strcmp (name
, "noat") == 0)
5690 else if (strcmp (name
, "macro") == 0)
5692 mips_warn_about_macros
= 0;
5694 else if (strcmp (name
, "nomacro") == 0)
5696 if (mips_noreorder
== 0)
5697 as_bad ("`noreorder' must be set before `nomacro'");
5698 mips_warn_about_macros
= 1;
5700 else if (strcmp (name
, "move") == 0 || strcmp (name
, "novolatile") == 0)
5704 else if (strcmp (name
, "nomove") == 0 || strcmp (name
, "volatile") == 0)
5708 else if (strcmp (name
, "bopt") == 0)
5712 else if (strcmp (name
, "nobopt") == 0)
5716 else if (strncmp (name
, "mips", 4) == 0)
5720 /* Permit the user to change the ISA on the fly. Needless to
5721 say, misuse can cause serious problems. */
5722 isa
= atoi (name
+ 4);
5724 mips_isa
= file_mips_isa
;
5725 else if (isa
< 1 || isa
> 3)
5726 as_bad ("unknown ISA level");
5732 as_warn ("Tried to set unrecognized symbol: %s\n", name
);
5734 *input_line_pointer
= ch
;
5735 demand_empty_rest_of_line ();
5738 /* The same as the usual .space directive, except that we have to
5739 forget about any previous instruction. */
5742 s_mips_space (param
)
5745 mips_emit_delays ();
5750 /* Handle the .abicalls pseudo-op. I believe this is equivalent to
5751 .option pic2. It means to generate SVR4 PIC calls. */
5757 mips_pic
= SVR4_PIC
;
5759 if (g_switch_seen
&& g_switch_value
!= 0)
5760 as_warn ("-G may not be used with SVR4 PIC code");
5763 bfd_set_gp_size (stdoutput
, 0);
5764 demand_empty_rest_of_line ();
5767 /* Handle the .cpload pseudo-op. This is used when generating SVR4
5768 PIC code. It sets the $gp register for the function based on the
5769 function address, which is in the register named in the argument.
5770 This uses a relocation against _gp_disp, which is handled specially
5771 by the linker. The result is:
5772 lui $gp,%hi(_gp_disp)
5773 addiu $gp,$gp,%lo(_gp_disp)
5774 addu $gp,$gp,.cpload argument
5775 The .cpload argument is normally $25 == $t9. */
5784 /* If we are not generating SVR4 PIC code, .cpload is ignored. */
5785 if (mips_pic
!= SVR4_PIC
)
5791 /* .cpload should be a in .set noreorder section. */
5792 if (mips_noreorder
== 0)
5793 as_warn (".cpload not in noreorder section");
5796 ex
.X_add_symbol
= symbol_find_or_make ("_gp_disp");
5797 ex
.X_op_symbol
= NULL
;
5798 ex
.X_add_number
= 0;
5800 macro_build_lui ((char *) NULL
, &icnt
, &ex
, GP
);
5801 macro_build ((char *) NULL
, &icnt
, &ex
, "addiu", "t,r,j", GP
, GP
,
5802 (int) BFD_RELOC_LO16
);
5804 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "addu", "d,v,t",
5805 GP
, GP
, tc_get_register (0));
5807 demand_empty_rest_of_line ();
5810 /* Handle the .cprestore pseudo-op. This stores $gp into a given
5811 offset from $sp. The offset is remembered, and after making a PIC
5812 call $gp is restored from that location. */
5815 s_cprestore (ignore
)
5821 /* If we are not generating SVR4 PIC code, .cprestore is ignored. */
5822 if (mips_pic
!= SVR4_PIC
)
5828 mips_cprestore_offset
= get_absolute_expression ();
5830 ex
.X_op
= O_constant
;
5831 ex
.X_add_symbol
= NULL
;
5832 ex
.X_op_symbol
= NULL
;
5833 ex
.X_add_number
= mips_cprestore_offset
;
5835 macro_build ((char *) NULL
, &icnt
, &ex
,
5836 mips_isa
< 3 ? "sw" : "sd",
5837 "t,o(b)", GP
, (int) BFD_RELOC_LO16
, SP
);
5839 demand_empty_rest_of_line ();
5842 /* Handle the .gpword pseudo-op. This is used when generating PIC
5843 code. It generates a 32 bit GP relative reloc. */
5853 /* When not generating PIC code, this is treated as .word. */
5854 if (mips_pic
!= SVR4_PIC
)
5861 mips_emit_delays ();
5863 mips_align (2, 0, label
);
5868 if (ex
.X_op
!= O_symbol
|| ex
.X_add_number
!= 0)
5870 as_bad ("Unsupported use of .gpword");
5871 ignore_rest_of_line ();
5875 md_number_to_chars (p
, (valueT
) 0, 4);
5876 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 4, &ex
, 0,
5877 BFD_RELOC_MIPS_GPREL32
);
5879 demand_empty_rest_of_line ();
5882 /* Handle the .cpadd pseudo-op. This is used when dealing with switch
5883 tables in SVR4 PIC code. */
5892 /* This is ignored when not generating SVR4 PIC code. */
5893 if (mips_pic
!= SVR4_PIC
)
5899 /* Add $gp to the register named as an argument. */
5900 reg
= tc_get_register (0);
5901 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5902 mips_isa
< 3 ? "addu" : "daddu",
5903 "d,v,t", reg
, reg
, GP
);
5905 demand_empty_rest_of_line ();
5908 /* Parse a register string into a number. Called from the ECOFF code
5909 to parse .frame. The argument is non-zero if this is the frame
5910 register, so that we can record it in mips_frame_reg. */
5913 tc_get_register (frame
)
5919 if (*input_line_pointer
++ != '$')
5921 as_warn ("expected `$'");
5924 else if (isdigit ((unsigned char) *input_line_pointer
))
5926 reg
= get_absolute_expression ();
5927 if (reg
< 0 || reg
>= 32)
5929 as_warn ("Bad register number");
5935 if (strncmp (input_line_pointer
, "fp", 2) == 0)
5937 else if (strncmp (input_line_pointer
, "sp", 2) == 0)
5939 else if (strncmp (input_line_pointer
, "gp", 2) == 0)
5941 else if (strncmp (input_line_pointer
, "at", 2) == 0)
5945 as_warn ("Unrecognized register name");
5948 input_line_pointer
+= 2;
5951 mips_frame_reg
= reg
!= 0 ? reg
: SP
;
5956 md_section_align (seg
, addr
)
5960 int align
= bfd_get_section_alignment (stdoutput
, seg
);
5962 return ((addr
+ (1 << align
) - 1) & (-1 << align
));
5965 /* Estimate the size of a frag before relaxing. We are not really
5966 relaxing here, and the final size is encoded in the subtype
5971 md_estimate_size_before_relax (fragp
, segtype
)
5977 if (mips_pic
== NO_PIC
)
5980 const char *symname
;
5982 /* Find out whether this symbol can be referenced off the GP
5983 register. It can be if it is smaller than the -G size or if
5984 it is in the .sdata or .sbss section. Certain symbols can
5985 not be referenced off the GP, although it appears as though
5987 symname
= S_GET_NAME (fragp
->fr_symbol
);
5988 if (symname
!= (const char *) NULL
5989 && (strcmp (symname
, "eprol") == 0
5990 || strcmp (symname
, "etext") == 0
5991 || strcmp (symname
, "_gp") == 0
5992 || strcmp (symname
, "edata") == 0
5993 || strcmp (symname
, "_fbss") == 0
5994 || strcmp (symname
, "_fdata") == 0
5995 || strcmp (symname
, "_ftext") == 0
5996 || strcmp (symname
, "end") == 0
5997 || strcmp (symname
, "_gp_disp") == 0))
5999 else if (! S_IS_DEFINED (fragp
->fr_symbol
)
6000 && ((fragp
->fr_symbol
->ecoff_extern_size
!= 0
6001 && fragp
->fr_symbol
->ecoff_extern_size
<= g_switch_value
)
6002 || (S_GET_VALUE (fragp
->fr_symbol
) != 0
6003 && S_GET_VALUE (fragp
->fr_symbol
) <= g_switch_value
)))
6007 const char *segname
;
6009 segname
= segment_name (S_GET_SEGMENT (fragp
->fr_symbol
));
6010 assert (strcmp (segname
, ".lit8") != 0
6011 && strcmp (segname
, ".lit4") != 0);
6012 change
= (strcmp (segname
, ".sdata") != 0
6013 && strcmp (segname
, ".sbss") != 0);
6015 #else /* ! defined (GPOPT) */
6016 /* We are not optimizing for the GP register. */
6018 #endif /* ! defined (GPOPT) */
6020 else if (mips_pic
== SVR4_PIC
)
6022 asection
*symsec
= fragp
->fr_symbol
->bsym
->section
;
6024 /* This must duplicate the test in adjust_reloc_syms. */
6025 change
= (symsec
!= &bfd_und_section
6026 && symsec
!= &bfd_abs_section
6027 && ! bfd_is_com_section (symsec
));
6034 /* Record the offset to the first reloc in the fr_opcode field.
6035 This lets md_convert_frag and tc_gen_reloc know that the code
6036 must be expanded. */
6037 fragp
->fr_opcode
= (fragp
->fr_literal
6039 - RELAX_OLD (fragp
->fr_subtype
)
6040 + RELAX_RELOC1 (fragp
->fr_subtype
));
6041 /* FIXME: This really needs as_warn_where. */
6042 if (RELAX_WARN (fragp
->fr_subtype
))
6043 as_warn ("AT used after \".set noat\" or macro used after \".set nomacro\"");
6049 return RELAX_NEW (fragp
->fr_subtype
) - RELAX_OLD (fragp
->fr_subtype
);
6052 /* Translate internal representation of relocation info to BFD target
6056 tc_gen_reloc (section
, fixp
)
6060 static arelent
*retval
[4];
6063 reloc
= retval
[0] = (arelent
*) xmalloc (sizeof (arelent
));
6066 reloc
->sym_ptr_ptr
= &fixp
->fx_addsy
->bsym
;
6067 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
6069 if (mips_pic
== EMBEDDED_PIC
6070 && SWITCH_TABLE (fixp
))
6072 /* For a switch table entry we use a special reloc. The addend
6073 is actually the difference between the reloc address and the
6075 reloc
->addend
= reloc
->address
- S_GET_VALUE (fixp
->fx_subsy
);
6077 as_fatal ("Double check fx_r_type in tc-mips.c:tc_gen_reloc");
6079 fixp
->fx_r_type
= BFD_RELOC_GPREL32
;
6081 else if (fixp
->fx_r_type
== BFD_RELOC_PCREL_LO16
)
6083 /* We use a special addend for an internal RELLO reloc. */
6084 if (fixp
->fx_addsy
->bsym
->flags
& BSF_SECTION_SYM
)
6085 reloc
->addend
= reloc
->address
- S_GET_VALUE (fixp
->fx_subsy
);
6087 reloc
->addend
= fixp
->fx_addnumber
+ reloc
->address
;
6089 else if (fixp
->fx_r_type
== BFD_RELOC_PCREL_HI16_S
)
6091 assert (fixp
->fx_next
!= NULL
6092 && fixp
->fx_next
->fx_r_type
== BFD_RELOC_PCREL_LO16
);
6093 /* We use a special addend for an internal RELHI reloc. The
6094 reloc is relative to the RELLO; adjust the addend
6096 if (fixp
->fx_addsy
->bsym
->flags
& BSF_SECTION_SYM
)
6097 reloc
->addend
= (fixp
->fx_next
->fx_frag
->fr_address
6098 + fixp
->fx_next
->fx_where
6099 - S_GET_VALUE (fixp
->fx_subsy
));
6101 reloc
->addend
= (fixp
->fx_addnumber
6102 + fixp
->fx_next
->fx_frag
->fr_address
6103 + fixp
->fx_next
->fx_where
);
6105 else if (fixp
->fx_pcrel
== 0)
6106 reloc
->addend
= fixp
->fx_addnumber
;
6110 /* A gruesome hack which is a result of the gruesome gas reloc
6112 reloc
->addend
= reloc
->address
;
6114 reloc
->addend
= -reloc
->address
;
6118 /* If this is a variant frag, we may need to adjust the existing
6119 reloc and generate a new one. */
6120 if (fixp
->fx_frag
->fr_opcode
!= NULL
6121 && (fixp
->fx_r_type
== BFD_RELOC_MIPS_GPREL
6122 || fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT16
6123 || fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL16
))
6127 /* If this is not the last reloc in this frag, then we have two
6128 GPREL relocs, both of which are being replaced. Let the
6129 second one handle all of them. */
6130 if (fixp
->fx_next
!= NULL
6131 && fixp
->fx_frag
== fixp
->fx_next
->fx_frag
)
6133 assert (fixp
->fx_r_type
== BFD_RELOC_MIPS_GPREL
6134 && fixp
->fx_next
->fx_r_type
== BFD_RELOC_MIPS_GPREL
);
6139 fixp
->fx_where
= fixp
->fx_frag
->fr_opcode
- fixp
->fx_frag
->fr_literal
;
6140 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
6141 reloc2
= retval
[1] = (arelent
*) xmalloc (sizeof (arelent
));
6143 reloc2
->sym_ptr_ptr
= &fixp
->fx_addsy
->bsym
;
6144 reloc2
->address
= (reloc
->address
6145 + (RELAX_RELOC2 (fixp
->fx_frag
->fr_subtype
)
6146 - RELAX_RELOC1 (fixp
->fx_frag
->fr_subtype
)));
6147 reloc2
->addend
= fixp
->fx_addnumber
;
6148 reloc2
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_LO16
);
6149 assert (reloc2
->howto
!= NULL
);
6151 if (RELAX_RELOC3 (fixp
->fx_frag
->fr_subtype
))
6155 reloc3
= retval
[2] = (arelent
*) xmalloc (sizeof (arelent
));
6158 reloc3
->address
+= 4;
6161 if (mips_pic
== NO_PIC
)
6163 assert (fixp
->fx_r_type
== BFD_RELOC_MIPS_GPREL
);
6164 fixp
->fx_r_type
= BFD_RELOC_HI16_S
;
6166 else if (mips_pic
== SVR4_PIC
)
6168 if (fixp
->fx_r_type
!= BFD_RELOC_MIPS_GOT16
)
6170 assert (fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL16
);
6171 fixp
->fx_r_type
= BFD_RELOC_MIPS_GOT16
;
6178 /* To support a PC relative reloc when generating embedded PIC code
6179 for ECOFF, we use a Cygnus extension. We check for that here to
6180 make sure that we don't let such a reloc escape normally. */
6182 if (fixp
->fx_r_type
== BFD_RELOC_16_PCREL_S2
6183 && mips_pic
!= EMBEDDED_PIC
)
6184 reloc
->howto
= NULL
;
6187 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, fixp
->fx_r_type
);
6189 if (reloc
->howto
== NULL
)
6191 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
6192 "Can not represent relocation in this object file format");
6199 /* Convert a machine dependent frag. */
6202 md_convert_frag (abfd
, asec
, fragp
)
6210 if (fragp
->fr_opcode
== NULL
)
6213 old
= RELAX_OLD (fragp
->fr_subtype
);
6214 new = RELAX_NEW (fragp
->fr_subtype
);
6215 fixptr
= fragp
->fr_literal
+ fragp
->fr_fix
;
6218 memcpy (fixptr
- old
, fixptr
, new);
6220 fragp
->fr_fix
+= new - old
;
6223 /* This function is called whenever a label is defined. It is used
6224 when handling branch delays; if a branch has a label, we assume we
6228 mips_define_label (sym
)
6236 /* Some special processing for a MIPS ELF file. */
6239 mips_elf_final_processing ()
6243 /* Write out the .reginfo section. */
6244 s
.ri_gprmask
= mips_gprmask
;
6245 s
.ri_cprmask
[0] = mips_cprmask
[0];
6246 s
.ri_cprmask
[1] = mips_cprmask
[1];
6247 s
.ri_cprmask
[2] = mips_cprmask
[2];
6248 s
.ri_cprmask
[3] = mips_cprmask
[3];
6249 /* The gp_value field is set by the MIPS ELF backend. */
6251 bfd_mips_elf32_swap_reginfo_out (stdoutput
, &s
,
6252 ((Elf32_External_RegInfo
*)
6253 mips_regmask_frag
));
6255 /* Set the MIPS ELF flag bits. FIXME: There should probably be some
6256 sort of BFD interface for this. */
6257 if (mips_any_noreorder
)
6258 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_NOREORDER
;
6259 if (mips_pic
!= NO_PIC
)
6260 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_PIC
;
6263 #endif /* OBJ_ELF */
6265 #ifndef ECOFF_DEBUGGING
6267 /* These functions should really be defined by the object file format,
6268 since they are related to debugging information. However, this
6269 code has to work for the a.out format, which does not define them,
6270 so we provide simple versions here. These don't actually generate
6271 any debugging information, but they do simple checking and someday
6272 somebody may make them useful. */
6276 struct loc
*loc_next
;
6277 unsigned long loc_fileno
;
6278 unsigned long loc_lineno
;
6279 unsigned long loc_offset
;
6280 unsigned short loc_delta
;
6281 unsigned short loc_count
;
6290 struct proc
*proc_next
;
6291 struct symbol
*proc_isym
;
6292 struct symbol
*proc_end
;
6293 unsigned long proc_reg_mask
;
6294 unsigned long proc_reg_offset
;
6295 unsigned long proc_fpreg_mask
;
6296 unsigned long proc_fpreg_offset
;
6297 unsigned long proc_frameoffset
;
6298 unsigned long proc_framereg
;
6299 unsigned long proc_pcreg
;
6301 struct file
*proc_file
;
6308 struct file
*file_next
;
6309 unsigned long file_fileno
;
6310 struct symbol
*file_symbol
;
6311 struct symbol
*file_end
;
6312 struct proc
*file_proc
;
6317 static struct obstack proc_frags
;
6318 static procS
*proc_lastP
;
6319 static procS
*proc_rootP
;
6320 static int numprocs
;
6325 obstack_begin (&proc_frags
, 0x2000);
6331 /* check for premature end, nesting errors, etc */
6332 if (proc_lastP
&& proc_lastP
->proc_end
== NULL
)
6333 as_warn ("missing `.end' at end of assembly");
6336 extern char hex_value
[];
6344 if (*input_line_pointer
== '-')
6346 ++input_line_pointer
;
6349 if (!isdigit (*input_line_pointer
))
6350 as_bad ("Expected simple number.");
6351 if (input_line_pointer
[0] == '0')
6353 if (input_line_pointer
[1] == 'x')
6355 input_line_pointer
+= 2;
6356 while (isxdigit (*input_line_pointer
))
6359 val
|= hex_value
[(int) *input_line_pointer
++];
6361 return negative
? -val
: val
;
6365 ++input_line_pointer
;
6366 while (isdigit (*input_line_pointer
))
6369 val
|= *input_line_pointer
++ - '0';
6371 return negative
? -val
: val
;
6374 if (!isdigit (*input_line_pointer
))
6376 printf (" *input_line_pointer == '%c' 0x%02x\n",
6377 *input_line_pointer
, *input_line_pointer
);
6378 as_warn ("Invalid number");
6381 while (isdigit (*input_line_pointer
))
6384 val
+= *input_line_pointer
++ - '0';
6386 return negative
? -val
: val
;
6389 /* The .file directive; just like the usual .file directive, but there
6390 is an initial number which is the ECOFF file index. */
6398 line
= get_number ();
6403 /* The .end directive. */
6411 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
6414 demand_empty_rest_of_line ();
6418 if (now_seg
!= text_section
)
6419 as_warn (".end not in text section");
6422 as_warn (".end and no .ent seen yet.");
6428 assert (S_GET_NAME (p
));
6429 if (strcmp (S_GET_NAME (p
), S_GET_NAME (proc_lastP
->proc_isym
)))
6430 as_warn (".end symbol does not match .ent symbol.");
6433 proc_lastP
->proc_end
= (symbolS
*) 1;
6436 /* The .aent and .ent directives. */
6446 symbolP
= get_symbol ();
6447 if (*input_line_pointer
== ',')
6448 input_line_pointer
++;
6450 if (isdigit (*input_line_pointer
) || *input_line_pointer
== '-')
6451 number
= get_number ();
6452 if (now_seg
!= text_section
)
6453 as_warn (".ent or .aent not in text section.");
6455 if (!aent
&& proc_lastP
&& proc_lastP
->proc_end
== NULL
)
6456 as_warn ("missing `.end'");
6460 procP
= (procS
*) obstack_alloc (&proc_frags
, sizeof (*procP
));
6461 procP
->proc_isym
= symbolP
;
6462 procP
->proc_reg_mask
= 0;
6463 procP
->proc_reg_offset
= 0;
6464 procP
->proc_fpreg_mask
= 0;
6465 procP
->proc_fpreg_offset
= 0;
6466 procP
->proc_frameoffset
= 0;
6467 procP
->proc_framereg
= 0;
6468 procP
->proc_pcreg
= 0;
6469 procP
->proc_end
= NULL
;
6470 procP
->proc_next
= NULL
;
6472 proc_lastP
->proc_next
= procP
;
6478 demand_empty_rest_of_line ();
6481 /* The .frame directive. */
6494 frame_reg
= tc_get_register (1);
6495 if (*input_line_pointer
== ',')
6496 input_line_pointer
++;
6497 frame_off
= get_absolute_expression ();
6498 if (*input_line_pointer
== ',')
6499 input_line_pointer
++;
6500 pcreg
= tc_get_register (0);
6503 assert (proc_rootP
);
6504 proc_rootP
->proc_framereg
= frame_reg
;
6505 proc_rootP
->proc_frameoffset
= frame_off
;
6506 proc_rootP
->proc_pcreg
= pcreg
;
6507 /* bob macho .frame */
6509 /* We don't have to write out a frame stab for unoptimized code. */
6510 if (!(frame_reg
== FP
&& frame_off
== 0))
6513 as_warn ("No .ent for .frame to use.");
6514 (void) sprintf (str
, "R%d;%d", frame_reg
, frame_off
);
6515 symP
= symbol_new (str
, N_VFP
, 0, frag_now
);
6516 S_SET_TYPE (symP
, N_RMASK
);
6517 S_SET_OTHER (symP
, 0);
6518 S_SET_DESC (symP
, 0);
6519 symP
->sy_forward
= proc_lastP
->proc_isym
;
6520 /* bob perhaps I should have used pseudo set */
6522 demand_empty_rest_of_line ();
6526 /* The .fmask and .mask directives. */
6533 char str
[100], *strP
;
6539 mask
= get_number ();
6540 if (*input_line_pointer
== ',')
6541 input_line_pointer
++;
6542 off
= get_absolute_expression ();
6544 /* bob only for coff */
6545 assert (proc_rootP
);
6546 if (reg_type
== 'F')
6548 proc_rootP
->proc_fpreg_mask
= mask
;
6549 proc_rootP
->proc_fpreg_offset
= off
;
6553 proc_rootP
->proc_reg_mask
= mask
;
6554 proc_rootP
->proc_reg_offset
= off
;
6557 /* bob macho .mask + .fmask */
6559 /* We don't have to write out a mask stab if no saved regs. */
6563 as_warn ("No .ent for .mask to use.");
6565 for (i
= 0; i
< 32; i
++)
6569 sprintf (strP
, "%c%d,", reg_type
, i
);
6570 strP
+= strlen (strP
);
6574 sprintf (strP
, ";%d,", off
);
6575 symP
= symbol_new (str
, N_RMASK
, 0, frag_now
);
6576 S_SET_TYPE (symP
, N_RMASK
);
6577 S_SET_OTHER (symP
, 0);
6578 S_SET_DESC (symP
, 0);
6579 symP
->sy_forward
= proc_lastP
->proc_isym
;
6580 /* bob perhaps I should have used pseudo set */
6585 /* The .loc directive. */
6596 assert (now_seg
== text_section
);
6598 lineno
= get_number ();
6599 addroff
= obstack_next_free (&frags
) - frag_now
->fr_literal
;
6601 symbolP
= symbol_new ("", N_SLINE
, addroff
, frag_now
);
6602 S_SET_TYPE (symbolP
, N_SLINE
);
6603 S_SET_OTHER (symbolP
, 0);
6604 S_SET_DESC (symbolP
, lineno
);
6605 symbolP
->sy_segment
= now_seg
;
6609 #endif /* ! defined (ECOFF_DEBUGGING) */