1 /* tc-mips.c -- assemble code for a MIPS chip.
2 Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,
3 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011, 2012
4 Free Software Foundation, Inc.
5 Contributed by the OSF and Ralph Campbell.
6 Written by Keith Knowles and Ralph Campbell, working independently.
7 Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus
10 This file is part of GAS.
12 GAS is free software; you can redistribute it and/or modify
13 it under the terms of the GNU General Public License as published by
14 the Free Software Foundation; either version 3, or (at your option)
17 GAS is distributed in the hope that it will be useful,
18 but WITHOUT ANY WARRANTY; without even the implied warranty of
19 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 GNU General Public License for more details.
22 You should have received a copy of the GNU General Public License
23 along with GAS; see the file COPYING. If not, write to the Free
24 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
30 #include "safe-ctype.h"
32 #include "opcode/mips.h"
34 #include "dwarf2dbg.h"
35 #include "dw2gencfi.h"
38 #define DBG(x) printf x
44 /* Clean up namespace so we can include obj-elf.h too. */
45 static int mips_output_flavor (void);
46 static int mips_output_flavor (void) { return OUTPUT_FLAVOR
; }
47 #undef OBJ_PROCESS_STAB
54 #undef obj_frob_file_after_relocs
55 #undef obj_frob_symbol
57 #undef obj_sec_sym_ok_for_reloc
58 #undef OBJ_COPY_SYMBOL_ATTRIBUTES
61 /* Fix any of them that we actually care about. */
63 #define OUTPUT_FLAVOR mips_output_flavor()
70 #ifndef ECOFF_DEBUGGING
71 #define NO_ECOFF_DEBUGGING
72 #define ECOFF_DEBUGGING 0
75 int mips_flag_mdebug
= -1;
77 /* Control generation of .pdr sections. Off by default on IRIX: the native
78 linker doesn't know about and discards them, but relocations against them
79 remain, leading to rld crashes. */
81 int mips_flag_pdr
= FALSE
;
83 int mips_flag_pdr
= TRUE
;
88 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
89 static char *mips_regmask_frag
;
97 #define PIC_CALL_REG 25
105 #define ILLEGAL_REG (32)
107 #define AT mips_opts.at
109 /* Allow override of standard little-endian ECOFF format. */
111 #ifndef ECOFF_LITTLE_FORMAT
112 #define ECOFF_LITTLE_FORMAT "ecoff-littlemips"
115 extern int target_big_endian
;
117 /* The name of the readonly data section. */
118 #define RDATA_SECTION_NAME (OUTPUT_FLAVOR == bfd_target_ecoff_flavour \
120 : OUTPUT_FLAVOR == bfd_target_coff_flavour \
122 : OUTPUT_FLAVOR == bfd_target_elf_flavour \
126 /* Ways in which an instruction can be "appended" to the output. */
128 /* Just add it normally. */
131 /* Add it normally and then add a nop. */
134 /* Turn an instruction with a delay slot into a "compact" version. */
137 /* Insert the instruction before the last one. */
141 /* Information about an instruction, including its format, operands
145 /* The opcode's entry in mips_opcodes or mips16_opcodes. */
146 const struct mips_opcode
*insn_mo
;
148 /* The 16-bit or 32-bit bitstring of the instruction itself. This is
149 a copy of INSN_MO->match with the operands filled in. If we have
150 decided to use an extended MIPS16 instruction, this includes the
152 unsigned long insn_opcode
;
154 /* The frag that contains the instruction. */
157 /* The offset into FRAG of the first instruction byte. */
160 /* The relocs associated with the instruction, if any. */
163 /* True if this entry cannot be moved from its current position. */
164 unsigned int fixed_p
: 1;
166 /* True if this instruction occurred in a .set noreorder block. */
167 unsigned int noreorder_p
: 1;
169 /* True for mips16 instructions that jump to an absolute address. */
170 unsigned int mips16_absolute_jump_p
: 1;
172 /* True if this instruction is complete. */
173 unsigned int complete_p
: 1;
176 /* The ABI to use. */
187 /* MIPS ABI we are using for this output file. */
188 static enum mips_abi_level mips_abi
= NO_ABI
;
190 /* Whether or not we have code that can call pic code. */
191 int mips_abicalls
= FALSE
;
193 /* Whether or not we have code which can be put into a shared
195 static bfd_boolean mips_in_shared
= TRUE
;
197 /* This is the set of options which may be modified by the .set
198 pseudo-op. We use a struct so that .set push and .set pop are more
201 struct mips_set_options
203 /* MIPS ISA (Instruction Set Architecture) level. This is set to -1
204 if it has not been initialized. Changed by `.set mipsN', and the
205 -mipsN command line option, and the default CPU. */
207 /* Enabled Application Specific Extensions (ASEs). These are set to -1
208 if they have not been initialized. Changed by `.set <asename>', by
209 command line options, and based on the default architecture. */
217 /* Whether we are assembling for the mips16 processor. 0 if we are
218 not, 1 if we are, and -1 if the value has not been initialized.
219 Changed by `.set mips16' and `.set nomips16', and the -mips16 and
220 -nomips16 command line options, and the default CPU. */
222 /* Whether we are assembling for the mipsMIPS ASE. 0 if we are not,
223 1 if we are, and -1 if the value has not been initialized. Changed
224 by `.set micromips' and `.set nomicromips', and the -mmicromips
225 and -mno-micromips command line options, and the default CPU. */
227 /* Non-zero if we should not reorder instructions. Changed by `.set
228 reorder' and `.set noreorder'. */
230 /* Non-zero if we should not permit the register designated "assembler
231 temporary" to be used in instructions. The value is the register
232 number, normally $at ($1). Changed by `.set at=REG', `.set noat'
233 (same as `.set at=$0') and `.set at' (same as `.set at=$1'). */
235 /* Non-zero if we should warn when a macro instruction expands into
236 more than one machine instruction. Changed by `.set nomacro' and
238 int warn_about_macros
;
239 /* Non-zero if we should not move instructions. Changed by `.set
240 move', `.set volatile', `.set nomove', and `.set novolatile'. */
242 /* Non-zero if we should not optimize branches by moving the target
243 of the branch into the delay slot. Actually, we don't perform
244 this optimization anyhow. Changed by `.set bopt' and `.set
247 /* Non-zero if we should not autoextend mips16 instructions.
248 Changed by `.set autoextend' and `.set noautoextend'. */
250 /* Restrict general purpose registers and floating point registers
251 to 32 bit. This is initially determined when -mgp32 or -mfp32
252 is passed but can changed if the assembler code uses .set mipsN. */
255 /* MIPS architecture (CPU) type. Changed by .set arch=FOO, the -march
256 command line option, and the default CPU. */
258 /* True if ".set sym32" is in effect. */
260 /* True if floating-point operations are not allowed. Changed by .set
261 softfloat or .set hardfloat, by command line options -msoft-float or
262 -mhard-float. The default is false. */
263 bfd_boolean soft_float
;
265 /* True if only single-precision floating-point operations are allowed.
266 Changed by .set singlefloat or .set doublefloat, command-line options
267 -msingle-float or -mdouble-float. The default is false. */
268 bfd_boolean single_float
;
271 /* This is the struct we use to hold the current set of options. Note
272 that we must set the isa field to ISA_UNKNOWN and the ASE fields to
273 -1 to indicate that they have not been initialized. */
275 /* True if -mgp32 was passed. */
276 static int file_mips_gp32
= -1;
278 /* True if -mfp32 was passed. */
279 static int file_mips_fp32
= -1;
281 /* 1 if -msoft-float, 0 if -mhard-float. The default is 0. */
282 static int file_mips_soft_float
= 0;
284 /* 1 if -msingle-float, 0 if -mdouble-float. The default is 0. */
285 static int file_mips_single_float
= 0;
287 static struct mips_set_options mips_opts
=
289 /* isa */ ISA_UNKNOWN
, /* ase_mips3d */ -1, /* ase_mdmx */ -1,
290 /* ase_smartmips */ 0, /* ase_dsp */ -1, /* ase_dspr2 */ -1, /* ase_mt */ -1,
291 /* ase_mcu */ -1, /* mips16 */ -1, /* micromips */ -1, /* noreorder */ 0,
292 /* at */ ATREG
, /* warn_about_macros */ 0, /* nomove */ 0, /* nobopt */ 0,
293 /* noautoextend */ 0, /* gp32 */ 0, /* fp32 */ 0, /* arch */ CPU_UNKNOWN
,
294 /* sym32 */ FALSE
, /* soft_float */ FALSE
, /* single_float */ FALSE
297 /* These variables are filled in with the masks of registers used.
298 The object format code reads them and puts them in the appropriate
300 unsigned long mips_gprmask
;
301 unsigned long mips_cprmask
[4];
303 /* MIPS ISA we are using for this output file. */
304 static int file_mips_isa
= ISA_UNKNOWN
;
306 /* True if any MIPS16 code was produced. */
307 static int file_ase_mips16
;
309 #define ISA_SUPPORTS_MIPS16E (mips_opts.isa == ISA_MIPS32 \
310 || mips_opts.isa == ISA_MIPS32R2 \
311 || mips_opts.isa == ISA_MIPS64 \
312 || mips_opts.isa == ISA_MIPS64R2)
314 /* True if any microMIPS code was produced. */
315 static int file_ase_micromips
;
317 /* True if we want to create R_MIPS_JALR for jalr $25. */
319 #define MIPS_JALR_HINT_P(EXPR) HAVE_NEWABI
321 /* As a GNU extension, we use R_MIPS_JALR for o32 too. However,
322 because there's no place for any addend, the only acceptable
323 expression is a bare symbol. */
324 #define MIPS_JALR_HINT_P(EXPR) \
325 (!HAVE_IN_PLACE_ADDENDS \
326 || ((EXPR)->X_op == O_symbol && (EXPR)->X_add_number == 0))
329 /* True if -mips3d was passed or implied by arguments passed on the
330 command line (e.g., by -march). */
331 static int file_ase_mips3d
;
333 /* True if -mdmx was passed or implied by arguments passed on the
334 command line (e.g., by -march). */
335 static int file_ase_mdmx
;
337 /* True if -msmartmips was passed or implied by arguments passed on the
338 command line (e.g., by -march). */
339 static int file_ase_smartmips
;
341 #define ISA_SUPPORTS_SMARTMIPS (mips_opts.isa == ISA_MIPS32 \
342 || mips_opts.isa == ISA_MIPS32R2)
344 /* True if -mdsp was passed or implied by arguments passed on the
345 command line (e.g., by -march). */
346 static int file_ase_dsp
;
348 #define ISA_SUPPORTS_DSP_ASE (mips_opts.isa == ISA_MIPS32R2 \
349 || mips_opts.isa == ISA_MIPS64R2 \
350 || mips_opts.micromips)
352 #define ISA_SUPPORTS_DSP64_ASE (mips_opts.isa == ISA_MIPS64R2)
354 /* True if -mdspr2 was passed or implied by arguments passed on the
355 command line (e.g., by -march). */
356 static int file_ase_dspr2
;
358 #define ISA_SUPPORTS_DSPR2_ASE (mips_opts.isa == ISA_MIPS32R2 \
359 || mips_opts.isa == ISA_MIPS64R2 \
360 || mips_opts.micromips)
362 /* True if -mmt was passed or implied by arguments passed on the
363 command line (e.g., by -march). */
364 static int file_ase_mt
;
366 #define ISA_SUPPORTS_MT_ASE (mips_opts.isa == ISA_MIPS32R2 \
367 || mips_opts.isa == ISA_MIPS64R2)
369 #define ISA_SUPPORTS_MCU_ASE (mips_opts.isa == ISA_MIPS32R2 \
370 || mips_opts.isa == ISA_MIPS64R2 \
371 || mips_opts.micromips)
373 /* The argument of the -march= flag. The architecture we are assembling. */
374 static int file_mips_arch
= CPU_UNKNOWN
;
375 static const char *mips_arch_string
;
377 /* The argument of the -mtune= flag. The architecture for which we
379 static int mips_tune
= CPU_UNKNOWN
;
380 static const char *mips_tune_string
;
382 /* True when generating 32-bit code for a 64-bit processor. */
383 static int mips_32bitmode
= 0;
385 /* True if the given ABI requires 32-bit registers. */
386 #define ABI_NEEDS_32BIT_REGS(ABI) ((ABI) == O32_ABI)
388 /* Likewise 64-bit registers. */
389 #define ABI_NEEDS_64BIT_REGS(ABI) \
391 || (ABI) == N64_ABI \
394 /* Return true if ISA supports 64 bit wide gp registers. */
395 #define ISA_HAS_64BIT_REGS(ISA) \
396 ((ISA) == ISA_MIPS3 \
397 || (ISA) == ISA_MIPS4 \
398 || (ISA) == ISA_MIPS5 \
399 || (ISA) == ISA_MIPS64 \
400 || (ISA) == ISA_MIPS64R2)
402 /* Return true if ISA supports 64 bit wide float registers. */
403 #define ISA_HAS_64BIT_FPRS(ISA) \
404 ((ISA) == ISA_MIPS3 \
405 || (ISA) == ISA_MIPS4 \
406 || (ISA) == ISA_MIPS5 \
407 || (ISA) == ISA_MIPS32R2 \
408 || (ISA) == ISA_MIPS64 \
409 || (ISA) == ISA_MIPS64R2)
411 /* Return true if ISA supports 64-bit right rotate (dror et al.)
413 #define ISA_HAS_DROR(ISA) \
414 ((ISA) == ISA_MIPS64R2 \
415 || (mips_opts.micromips \
416 && ISA_HAS_64BIT_REGS (ISA)) \
419 /* Return true if ISA supports 32-bit right rotate (ror et al.)
421 #define ISA_HAS_ROR(ISA) \
422 ((ISA) == ISA_MIPS32R2 \
423 || (ISA) == ISA_MIPS64R2 \
424 || mips_opts.ase_smartmips \
425 || mips_opts.micromips \
428 /* Return true if ISA supports single-precision floats in odd registers. */
429 #define ISA_HAS_ODD_SINGLE_FPR(ISA) \
430 ((ISA) == ISA_MIPS32 \
431 || (ISA) == ISA_MIPS32R2 \
432 || (ISA) == ISA_MIPS64 \
433 || (ISA) == ISA_MIPS64R2)
435 /* Return true if ISA supports move to/from high part of a 64-bit
436 floating-point register. */
437 #define ISA_HAS_MXHC1(ISA) \
438 ((ISA) == ISA_MIPS32R2 \
439 || (ISA) == ISA_MIPS64R2)
441 #define HAVE_32BIT_GPRS \
442 (mips_opts.gp32 || !ISA_HAS_64BIT_REGS (mips_opts.isa))
444 #define HAVE_32BIT_FPRS \
445 (mips_opts.fp32 || !ISA_HAS_64BIT_FPRS (mips_opts.isa))
447 #define HAVE_64BIT_GPRS (!HAVE_32BIT_GPRS)
448 #define HAVE_64BIT_FPRS (!HAVE_32BIT_FPRS)
450 #define HAVE_NEWABI (mips_abi == N32_ABI || mips_abi == N64_ABI)
452 #define HAVE_64BIT_OBJECTS (mips_abi == N64_ABI)
454 /* True if relocations are stored in-place. */
455 #define HAVE_IN_PLACE_ADDENDS (!HAVE_NEWABI)
457 /* The ABI-derived address size. */
458 #define HAVE_64BIT_ADDRESSES \
459 (HAVE_64BIT_GPRS && (mips_abi == EABI_ABI || mips_abi == N64_ABI))
460 #define HAVE_32BIT_ADDRESSES (!HAVE_64BIT_ADDRESSES)
462 /* The size of symbolic constants (i.e., expressions of the form
463 "SYMBOL" or "SYMBOL + OFFSET"). */
464 #define HAVE_32BIT_SYMBOLS \
465 (HAVE_32BIT_ADDRESSES || !HAVE_64BIT_OBJECTS || mips_opts.sym32)
466 #define HAVE_64BIT_SYMBOLS (!HAVE_32BIT_SYMBOLS)
468 /* Addresses are loaded in different ways, depending on the address size
469 in use. The n32 ABI Documentation also mandates the use of additions
470 with overflow checking, but existing implementations don't follow it. */
471 #define ADDRESS_ADD_INSN \
472 (HAVE_32BIT_ADDRESSES ? "addu" : "daddu")
474 #define ADDRESS_ADDI_INSN \
475 (HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu")
477 #define ADDRESS_LOAD_INSN \
478 (HAVE_32BIT_ADDRESSES ? "lw" : "ld")
480 #define ADDRESS_STORE_INSN \
481 (HAVE_32BIT_ADDRESSES ? "sw" : "sd")
483 /* Return true if the given CPU supports the MIPS16 ASE. */
484 #define CPU_HAS_MIPS16(cpu) \
485 (strncmp (TARGET_CPU, "mips16", sizeof ("mips16") - 1) == 0 \
486 || strncmp (TARGET_CANONICAL, "mips-lsi-elf", sizeof ("mips-lsi-elf") - 1) == 0)
488 /* Return true if the given CPU supports the microMIPS ASE. */
489 #define CPU_HAS_MICROMIPS(cpu) 0
491 /* True if CPU has a dror instruction. */
492 #define CPU_HAS_DROR(CPU) ((CPU) == CPU_VR5400 || (CPU) == CPU_VR5500)
494 /* True if CPU has a ror instruction. */
495 #define CPU_HAS_ROR(CPU) CPU_HAS_DROR (CPU)
497 /* True if CPU is in the Octeon family */
498 #define CPU_IS_OCTEON(CPU) ((CPU) == CPU_OCTEON || (CPU) == CPU_OCTEONP || (CPU) == CPU_OCTEON2)
500 /* True if CPU has seq/sne and seqi/snei instructions. */
501 #define CPU_HAS_SEQ(CPU) (CPU_IS_OCTEON (CPU))
503 /* True if mflo and mfhi can be immediately followed by instructions
504 which write to the HI and LO registers.
506 According to MIPS specifications, MIPS ISAs I, II, and III need
507 (at least) two instructions between the reads of HI/LO and
508 instructions which write them, and later ISAs do not. Contradicting
509 the MIPS specifications, some MIPS IV processor user manuals (e.g.
510 the UM for the NEC Vr5000) document needing the instructions between
511 HI/LO reads and writes, as well. Therefore, we declare only MIPS32,
512 MIPS64 and later ISAs to have the interlocks, plus any specific
513 earlier-ISA CPUs for which CPU documentation declares that the
514 instructions are really interlocked. */
515 #define hilo_interlocks \
516 (mips_opts.isa == ISA_MIPS32 \
517 || mips_opts.isa == ISA_MIPS32R2 \
518 || mips_opts.isa == ISA_MIPS64 \
519 || mips_opts.isa == ISA_MIPS64R2 \
520 || mips_opts.arch == CPU_R4010 \
521 || mips_opts.arch == CPU_R10000 \
522 || mips_opts.arch == CPU_R12000 \
523 || mips_opts.arch == CPU_R14000 \
524 || mips_opts.arch == CPU_R16000 \
525 || mips_opts.arch == CPU_RM7000 \
526 || mips_opts.arch == CPU_VR5500 \
527 || mips_opts.micromips \
530 /* Whether the processor uses hardware interlocks to protect reads
531 from the GPRs after they are loaded from memory, and thus does not
532 require nops to be inserted. This applies to instructions marked
533 INSN_LOAD_MEMORY_DELAY. These nops are only required at MIPS ISA
534 level I and microMIPS mode instructions are always interlocked. */
535 #define gpr_interlocks \
536 (mips_opts.isa != ISA_MIPS1 \
537 || mips_opts.arch == CPU_R3900 \
538 || mips_opts.micromips \
541 /* Whether the processor uses hardware interlocks to avoid delays
542 required by coprocessor instructions, and thus does not require
543 nops to be inserted. This applies to instructions marked
544 INSN_LOAD_COPROC_DELAY, INSN_COPROC_MOVE_DELAY, and to delays
545 between instructions marked INSN_WRITE_COND_CODE and ones marked
546 INSN_READ_COND_CODE. These nops are only required at MIPS ISA
547 levels I, II, and III and microMIPS mode instructions are always
549 /* Itbl support may require additional care here. */
550 #define cop_interlocks \
551 ((mips_opts.isa != ISA_MIPS1 \
552 && mips_opts.isa != ISA_MIPS2 \
553 && mips_opts.isa != ISA_MIPS3) \
554 || mips_opts.arch == CPU_R4300 \
555 || mips_opts.micromips \
558 /* Whether the processor uses hardware interlocks to protect reads
559 from coprocessor registers after they are loaded from memory, and
560 thus does not require nops to be inserted. This applies to
561 instructions marked INSN_COPROC_MEMORY_DELAY. These nops are only
562 requires at MIPS ISA level I and microMIPS mode instructions are
563 always interlocked. */
564 #define cop_mem_interlocks \
565 (mips_opts.isa != ISA_MIPS1 \
566 || mips_opts.micromips \
569 /* Is this a mfhi or mflo instruction? */
570 #define MF_HILO_INSN(PINFO) \
571 ((PINFO & INSN_READ_HI) || (PINFO & INSN_READ_LO))
573 /* Whether code compression (either of the MIPS16 or the microMIPS ASEs)
574 has been selected. This implies, in particular, that addresses of text
575 labels have their LSB set. */
576 #define HAVE_CODE_COMPRESSION \
577 ((mips_opts.mips16 | mips_opts.micromips) != 0)
579 /* MIPS PIC level. */
581 enum mips_pic_level mips_pic
;
583 /* 1 if we should generate 32 bit offsets from the $gp register in
584 SVR4_PIC mode. Currently has no meaning in other modes. */
585 static int mips_big_got
= 0;
587 /* 1 if trap instructions should used for overflow rather than break
589 static int mips_trap
= 0;
591 /* 1 if double width floating point constants should not be constructed
592 by assembling two single width halves into two single width floating
593 point registers which just happen to alias the double width destination
594 register. On some architectures this aliasing can be disabled by a bit
595 in the status register, and the setting of this bit cannot be determined
596 automatically at assemble time. */
597 static int mips_disable_float_construction
;
599 /* Non-zero if any .set noreorder directives were used. */
601 static int mips_any_noreorder
;
603 /* Non-zero if nops should be inserted when the register referenced in
604 an mfhi/mflo instruction is read in the next two instructions. */
605 static int mips_7000_hilo_fix
;
607 /* The size of objects in the small data section. */
608 static unsigned int g_switch_value
= 8;
609 /* Whether the -G option was used. */
610 static int g_switch_seen
= 0;
615 /* If we can determine in advance that GP optimization won't be
616 possible, we can skip the relaxation stuff that tries to produce
617 GP-relative references. This makes delay slot optimization work
620 This function can only provide a guess, but it seems to work for
621 gcc output. It needs to guess right for gcc, otherwise gcc
622 will put what it thinks is a GP-relative instruction in a branch
625 I don't know if a fix is needed for the SVR4_PIC mode. I've only
626 fixed it for the non-PIC mode. KR 95/04/07 */
627 static int nopic_need_relax (symbolS
*, int);
629 /* handle of the OPCODE hash table */
630 static struct hash_control
*op_hash
= NULL
;
632 /* The opcode hash table we use for the mips16. */
633 static struct hash_control
*mips16_op_hash
= NULL
;
635 /* The opcode hash table we use for the microMIPS ASE. */
636 static struct hash_control
*micromips_op_hash
= NULL
;
638 /* This array holds the chars that always start a comment. If the
639 pre-processor is disabled, these aren't very useful */
640 const char comment_chars
[] = "#";
642 /* This array holds the chars that only start a comment at the beginning of
643 a line. If the line seems to have the form '# 123 filename'
644 .line and .file directives will appear in the pre-processed output */
645 /* Note that input_file.c hand checks for '#' at the beginning of the
646 first line of the input file. This is because the compiler outputs
647 #NO_APP at the beginning of its output. */
648 /* Also note that C style comments are always supported. */
649 const char line_comment_chars
[] = "#";
651 /* This array holds machine specific line separator characters. */
652 const char line_separator_chars
[] = ";";
654 /* Chars that can be used to separate mant from exp in floating point nums */
655 const char EXP_CHARS
[] = "eE";
657 /* Chars that mean this number is a floating point constant */
660 const char FLT_CHARS
[] = "rRsSfFdDxXpP";
662 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
663 changed in read.c . Ideally it shouldn't have to know about it at all,
664 but nothing is ideal around here.
667 static char *insn_error
;
669 static int auto_align
= 1;
671 /* When outputting SVR4 PIC code, the assembler needs to know the
672 offset in the stack frame from which to restore the $gp register.
673 This is set by the .cprestore pseudo-op, and saved in this
675 static offsetT mips_cprestore_offset
= -1;
677 /* Similar for NewABI PIC code, where $gp is callee-saved. NewABI has some
678 more optimizations, it can use a register value instead of a memory-saved
679 offset and even an other register than $gp as global pointer. */
680 static offsetT mips_cpreturn_offset
= -1;
681 static int mips_cpreturn_register
= -1;
682 static int mips_gp_register
= GP
;
683 static int mips_gprel_offset
= 0;
685 /* Whether mips_cprestore_offset has been set in the current function
686 (or whether it has already been warned about, if not). */
687 static int mips_cprestore_valid
= 0;
689 /* This is the register which holds the stack frame, as set by the
690 .frame pseudo-op. This is needed to implement .cprestore. */
691 static int mips_frame_reg
= SP
;
693 /* Whether mips_frame_reg has been set in the current function
694 (or whether it has already been warned about, if not). */
695 static int mips_frame_reg_valid
= 0;
697 /* To output NOP instructions correctly, we need to keep information
698 about the previous two instructions. */
700 /* Whether we are optimizing. The default value of 2 means to remove
701 unneeded NOPs and swap branch instructions when possible. A value
702 of 1 means to not swap branches. A value of 0 means to always
704 static int mips_optimize
= 2;
706 /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is
707 equivalent to seeing no -g option at all. */
708 static int mips_debug
= 0;
710 /* The maximum number of NOPs needed to avoid the VR4130 mflo/mfhi errata. */
711 #define MAX_VR4130_NOPS 4
713 /* The maximum number of NOPs needed to fill delay slots. */
714 #define MAX_DELAY_NOPS 2
716 /* The maximum number of NOPs needed for any purpose. */
719 /* A list of previous instructions, with index 0 being the most recent.
720 We need to look back MAX_NOPS instructions when filling delay slots
721 or working around processor errata. We need to look back one
722 instruction further if we're thinking about using history[0] to
723 fill a branch delay slot. */
724 static struct mips_cl_insn history
[1 + MAX_NOPS
];
726 /* Nop instructions used by emit_nop. */
727 static struct mips_cl_insn nop_insn
;
728 static struct mips_cl_insn mips16_nop_insn
;
729 static struct mips_cl_insn micromips_nop16_insn
;
730 static struct mips_cl_insn micromips_nop32_insn
;
732 /* The appropriate nop for the current mode. */
733 #define NOP_INSN (mips_opts.mips16 ? &mips16_nop_insn \
734 : (mips_opts.micromips ? µmips_nop16_insn : &nop_insn))
736 /* The size of NOP_INSN in bytes. */
737 #define NOP_INSN_SIZE (HAVE_CODE_COMPRESSION ? 2 : 4)
739 /* If this is set, it points to a frag holding nop instructions which
740 were inserted before the start of a noreorder section. If those
741 nops turn out to be unnecessary, the size of the frag can be
743 static fragS
*prev_nop_frag
;
745 /* The number of nop instructions we created in prev_nop_frag. */
746 static int prev_nop_frag_holds
;
748 /* The number of nop instructions that we know we need in
750 static int prev_nop_frag_required
;
752 /* The number of instructions we've seen since prev_nop_frag. */
753 static int prev_nop_frag_since
;
755 /* For ECOFF and ELF, relocations against symbols are done in two
756 parts, with a HI relocation and a LO relocation. Each relocation
757 has only 16 bits of space to store an addend. This means that in
758 order for the linker to handle carries correctly, it must be able
759 to locate both the HI and the LO relocation. This means that the
760 relocations must appear in order in the relocation table.
762 In order to implement this, we keep track of each unmatched HI
763 relocation. We then sort them so that they immediately precede the
764 corresponding LO relocation. */
769 struct mips_hi_fixup
*next
;
772 /* The section this fixup is in. */
776 /* The list of unmatched HI relocs. */
778 static struct mips_hi_fixup
*mips_hi_fixup_list
;
780 /* The frag containing the last explicit relocation operator.
781 Null if explicit relocations have not been used. */
783 static fragS
*prev_reloc_op_frag
;
785 /* Map normal MIPS register numbers to mips16 register numbers. */
787 #define X ILLEGAL_REG
788 static const int mips32_to_16_reg_map
[] =
790 X
, X
, 2, 3, 4, 5, 6, 7,
791 X
, X
, X
, X
, X
, X
, X
, X
,
792 0, 1, X
, X
, X
, X
, X
, X
,
793 X
, X
, X
, X
, X
, X
, X
, X
797 /* Map mips16 register numbers to normal MIPS register numbers. */
799 static const unsigned int mips16_to_32_reg_map
[] =
801 16, 17, 2, 3, 4, 5, 6, 7
804 /* Map normal MIPS register numbers to microMIPS register numbers. */
806 #define mips32_to_micromips_reg_b_map mips32_to_16_reg_map
807 #define mips32_to_micromips_reg_c_map mips32_to_16_reg_map
808 #define mips32_to_micromips_reg_d_map mips32_to_16_reg_map
809 #define mips32_to_micromips_reg_e_map mips32_to_16_reg_map
810 #define mips32_to_micromips_reg_f_map mips32_to_16_reg_map
811 #define mips32_to_micromips_reg_g_map mips32_to_16_reg_map
812 #define mips32_to_micromips_reg_l_map mips32_to_16_reg_map
814 #define X ILLEGAL_REG
815 /* reg type h: 4, 5, 6. */
816 static const int mips32_to_micromips_reg_h_map
[] =
818 X
, X
, X
, X
, 4, 5, 6, X
,
819 X
, X
, X
, X
, X
, X
, X
, X
,
820 X
, X
, X
, X
, X
, X
, X
, X
,
821 X
, X
, X
, X
, X
, X
, X
, X
824 /* reg type m: 0, 17, 2, 3, 16, 18, 19, 20. */
825 static const int mips32_to_micromips_reg_m_map
[] =
827 0, X
, 2, 3, X
, X
, X
, X
,
828 X
, X
, X
, X
, X
, X
, X
, X
,
829 4, 1, 5, 6, 7, X
, X
, X
,
830 X
, X
, X
, X
, X
, X
, X
, X
833 /* reg type q: 0, 2-7. 17. */
834 static const int mips32_to_micromips_reg_q_map
[] =
836 0, X
, 2, 3, 4, 5, 6, 7,
837 X
, X
, X
, X
, X
, X
, X
, X
,
838 X
, 1, X
, X
, X
, X
, X
, X
,
839 X
, X
, X
, X
, X
, X
, X
, X
842 #define mips32_to_micromips_reg_n_map mips32_to_micromips_reg_m_map
845 /* Map microMIPS register numbers to normal MIPS register numbers. */
847 #define micromips_to_32_reg_b_map mips16_to_32_reg_map
848 #define micromips_to_32_reg_c_map mips16_to_32_reg_map
849 #define micromips_to_32_reg_d_map mips16_to_32_reg_map
850 #define micromips_to_32_reg_e_map mips16_to_32_reg_map
851 #define micromips_to_32_reg_f_map mips16_to_32_reg_map
852 #define micromips_to_32_reg_g_map mips16_to_32_reg_map
854 /* The microMIPS registers with type h. */
855 static const unsigned int micromips_to_32_reg_h_map
[] =
857 5, 5, 6, 4, 4, 4, 4, 4
860 /* The microMIPS registers with type i. */
861 static const unsigned int micromips_to_32_reg_i_map
[] =
863 6, 7, 7, 21, 22, 5, 6, 7
866 #define micromips_to_32_reg_l_map mips16_to_32_reg_map
868 /* The microMIPS registers with type m. */
869 static const unsigned int micromips_to_32_reg_m_map
[] =
871 0, 17, 2, 3, 16, 18, 19, 20
874 #define micromips_to_32_reg_n_map micromips_to_32_reg_m_map
876 /* The microMIPS registers with type q. */
877 static const unsigned int micromips_to_32_reg_q_map
[] =
879 0, 17, 2, 3, 4, 5, 6, 7
882 /* microMIPS imm type B. */
883 static const int micromips_imm_b_map
[] =
885 1, 4, 8, 12, 16, 20, 24, -1
888 /* microMIPS imm type C. */
889 static const int micromips_imm_c_map
[] =
891 128, 1, 2, 3, 4, 7, 8, 15, 16, 31, 32, 63, 64, 255, 32768, 65535
894 /* Classifies the kind of instructions we're interested in when
895 implementing -mfix-vr4120. */
896 enum fix_vr4120_class
904 NUM_FIX_VR4120_CLASSES
907 /* ...likewise -mfix-loongson2f-jump. */
908 static bfd_boolean mips_fix_loongson2f_jump
;
910 /* ...likewise -mfix-loongson2f-nop. */
911 static bfd_boolean mips_fix_loongson2f_nop
;
913 /* True if -mfix-loongson2f-nop or -mfix-loongson2f-jump passed. */
914 static bfd_boolean mips_fix_loongson2f
;
916 /* Given two FIX_VR4120_* values X and Y, bit Y of element X is set if
917 there must be at least one other instruction between an instruction
918 of type X and an instruction of type Y. */
919 static unsigned int vr4120_conflicts
[NUM_FIX_VR4120_CLASSES
];
921 /* True if -mfix-vr4120 is in force. */
922 static int mips_fix_vr4120
;
924 /* ...likewise -mfix-vr4130. */
925 static int mips_fix_vr4130
;
927 /* ...likewise -mfix-24k. */
928 static int mips_fix_24k
;
930 /* ...likewise -mfix-cn63xxp1 */
931 static bfd_boolean mips_fix_cn63xxp1
;
933 /* We don't relax branches by default, since this causes us to expand
934 `la .l2 - .l1' if there's a branch between .l1 and .l2, because we
935 fail to compute the offset before expanding the macro to the most
936 efficient expansion. */
938 static int mips_relax_branch
;
940 /* The expansion of many macros depends on the type of symbol that
941 they refer to. For example, when generating position-dependent code,
942 a macro that refers to a symbol may have two different expansions,
943 one which uses GP-relative addresses and one which uses absolute
944 addresses. When generating SVR4-style PIC, a macro may have
945 different expansions for local and global symbols.
947 We handle these situations by generating both sequences and putting
948 them in variant frags. In position-dependent code, the first sequence
949 will be the GP-relative one and the second sequence will be the
950 absolute one. In SVR4 PIC, the first sequence will be for global
951 symbols and the second will be for local symbols.
953 The frag's "subtype" is RELAX_ENCODE (FIRST, SECOND), where FIRST and
954 SECOND are the lengths of the two sequences in bytes. These fields
955 can be extracted using RELAX_FIRST() and RELAX_SECOND(). In addition,
956 the subtype has the following flags:
959 Set if it has been decided that we should use the second
960 sequence instead of the first.
963 Set in the first variant frag if the macro's second implementation
964 is longer than its first. This refers to the macro as a whole,
965 not an individual relaxation.
968 Set in the first variant frag if the macro appeared in a .set nomacro
969 block and if one alternative requires a warning but the other does not.
972 Like RELAX_NOMACRO, but indicates that the macro appears in a branch
975 RELAX_DELAY_SLOT_16BIT
976 Like RELAX_DELAY_SLOT, but indicates that the delay slot requires a
979 RELAX_DELAY_SLOT_SIZE_FIRST
980 Like RELAX_DELAY_SLOT, but indicates that the first implementation of
981 the macro is of the wrong size for the branch delay slot.
983 RELAX_DELAY_SLOT_SIZE_SECOND
984 Like RELAX_DELAY_SLOT, but indicates that the second implementation of
985 the macro is of the wrong size for the branch delay slot.
987 The frag's "opcode" points to the first fixup for relaxable code.
989 Relaxable macros are generated using a sequence such as:
991 relax_start (SYMBOL);
992 ... generate first expansion ...
994 ... generate second expansion ...
997 The code and fixups for the unwanted alternative are discarded
998 by md_convert_frag. */
999 #define RELAX_ENCODE(FIRST, SECOND) (((FIRST) << 8) | (SECOND))
1001 #define RELAX_FIRST(X) (((X) >> 8) & 0xff)
1002 #define RELAX_SECOND(X) ((X) & 0xff)
1003 #define RELAX_USE_SECOND 0x10000
1004 #define RELAX_SECOND_LONGER 0x20000
1005 #define RELAX_NOMACRO 0x40000
1006 #define RELAX_DELAY_SLOT 0x80000
1007 #define RELAX_DELAY_SLOT_16BIT 0x100000
1008 #define RELAX_DELAY_SLOT_SIZE_FIRST 0x200000
1009 #define RELAX_DELAY_SLOT_SIZE_SECOND 0x400000
1011 /* Branch without likely bit. If label is out of range, we turn:
1013 beq reg1, reg2, label
1023 with the following opcode replacements:
1030 bltzal <-> bgezal (with jal label instead of j label)
1032 Even though keeping the delay slot instruction in the delay slot of
1033 the branch would be more efficient, it would be very tricky to do
1034 correctly, because we'd have to introduce a variable frag *after*
1035 the delay slot instruction, and expand that instead. Let's do it
1036 the easy way for now, even if the branch-not-taken case now costs
1037 one additional instruction. Out-of-range branches are not supposed
1038 to be common, anyway.
1040 Branch likely. If label is out of range, we turn:
1042 beql reg1, reg2, label
1043 delay slot (annulled if branch not taken)
1052 delay slot (executed only if branch taken)
1055 It would be possible to generate a shorter sequence by losing the
1056 likely bit, generating something like:
1061 delay slot (executed only if branch taken)
1073 bltzall -> bgezal (with jal label instead of j label)
1074 bgezall -> bltzal (ditto)
1077 but it's not clear that it would actually improve performance. */
1078 #define RELAX_BRANCH_ENCODE(at, uncond, likely, link, toofar) \
1079 ((relax_substateT) \
1082 | ((toofar) ? 0x20 : 0) \
1083 | ((link) ? 0x40 : 0) \
1084 | ((likely) ? 0x80 : 0) \
1085 | ((uncond) ? 0x100 : 0)))
1086 #define RELAX_BRANCH_P(i) (((i) & 0xf0000000) == 0xc0000000)
1087 #define RELAX_BRANCH_UNCOND(i) (((i) & 0x100) != 0)
1088 #define RELAX_BRANCH_LIKELY(i) (((i) & 0x80) != 0)
1089 #define RELAX_BRANCH_LINK(i) (((i) & 0x40) != 0)
1090 #define RELAX_BRANCH_TOOFAR(i) (((i) & 0x20) != 0)
1091 #define RELAX_BRANCH_AT(i) ((i) & 0x1f)
1093 /* For mips16 code, we use an entirely different form of relaxation.
1094 mips16 supports two versions of most instructions which take
1095 immediate values: a small one which takes some small value, and a
1096 larger one which takes a 16 bit value. Since branches also follow
1097 this pattern, relaxing these values is required.
1099 We can assemble both mips16 and normal MIPS code in a single
1100 object. Therefore, we need to support this type of relaxation at
1101 the same time that we support the relaxation described above. We
1102 use the high bit of the subtype field to distinguish these cases.
1104 The information we store for this type of relaxation is the
1105 argument code found in the opcode file for this relocation, whether
1106 the user explicitly requested a small or extended form, and whether
1107 the relocation is in a jump or jal delay slot. That tells us the
1108 size of the value, and how it should be stored. We also store
1109 whether the fragment is considered to be extended or not. We also
1110 store whether this is known to be a branch to a different section,
1111 whether we have tried to relax this frag yet, and whether we have
1112 ever extended a PC relative fragment because of a shift count. */
1113 #define RELAX_MIPS16_ENCODE(type, small, ext, dslot, jal_dslot) \
1116 | ((small) ? 0x100 : 0) \
1117 | ((ext) ? 0x200 : 0) \
1118 | ((dslot) ? 0x400 : 0) \
1119 | ((jal_dslot) ? 0x800 : 0))
1120 #define RELAX_MIPS16_P(i) (((i) & 0xc0000000) == 0x80000000)
1121 #define RELAX_MIPS16_TYPE(i) ((i) & 0xff)
1122 #define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x100) != 0)
1123 #define RELAX_MIPS16_USER_EXT(i) (((i) & 0x200) != 0)
1124 #define RELAX_MIPS16_DSLOT(i) (((i) & 0x400) != 0)
1125 #define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x800) != 0)
1126 #define RELAX_MIPS16_EXTENDED(i) (((i) & 0x1000) != 0)
1127 #define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x1000)
1128 #define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) &~ 0x1000)
1129 #define RELAX_MIPS16_LONG_BRANCH(i) (((i) & 0x2000) != 0)
1130 #define RELAX_MIPS16_MARK_LONG_BRANCH(i) ((i) | 0x2000)
1131 #define RELAX_MIPS16_CLEAR_LONG_BRANCH(i) ((i) &~ 0x2000)
1133 /* For microMIPS code, we use relaxation similar to one we use for
1134 MIPS16 code. Some instructions that take immediate values support
1135 two encodings: a small one which takes some small value, and a
1136 larger one which takes a 16 bit value. As some branches also follow
1137 this pattern, relaxing these values is required.
1139 We can assemble both microMIPS and normal MIPS code in a single
1140 object. Therefore, we need to support this type of relaxation at
1141 the same time that we support the relaxation described above. We
1142 use one of the high bits of the subtype field to distinguish these
1145 The information we store for this type of relaxation is the argument
1146 code found in the opcode file for this relocation, the register
1147 selected as the assembler temporary, whether the branch is
1148 unconditional, whether it is compact, whether it stores the link
1149 address implicitly in $ra, whether relaxation of out-of-range 32-bit
1150 branches to a sequence of instructions is enabled, and whether the
1151 displacement of a branch is too large to fit as an immediate argument
1152 of a 16-bit and a 32-bit branch, respectively. */
1153 #define RELAX_MICROMIPS_ENCODE(type, at, uncond, compact, link, \
1154 relax32, toofar16, toofar32) \
1157 | (((at) & 0x1f) << 8) \
1158 | ((uncond) ? 0x2000 : 0) \
1159 | ((compact) ? 0x4000 : 0) \
1160 | ((link) ? 0x8000 : 0) \
1161 | ((relax32) ? 0x10000 : 0) \
1162 | ((toofar16) ? 0x20000 : 0) \
1163 | ((toofar32) ? 0x40000 : 0))
1164 #define RELAX_MICROMIPS_P(i) (((i) & 0xc0000000) == 0x40000000)
1165 #define RELAX_MICROMIPS_TYPE(i) ((i) & 0xff)
1166 #define RELAX_MICROMIPS_AT(i) (((i) >> 8) & 0x1f)
1167 #define RELAX_MICROMIPS_UNCOND(i) (((i) & 0x2000) != 0)
1168 #define RELAX_MICROMIPS_COMPACT(i) (((i) & 0x4000) != 0)
1169 #define RELAX_MICROMIPS_LINK(i) (((i) & 0x8000) != 0)
1170 #define RELAX_MICROMIPS_RELAX32(i) (((i) & 0x10000) != 0)
1172 #define RELAX_MICROMIPS_TOOFAR16(i) (((i) & 0x20000) != 0)
1173 #define RELAX_MICROMIPS_MARK_TOOFAR16(i) ((i) | 0x20000)
1174 #define RELAX_MICROMIPS_CLEAR_TOOFAR16(i) ((i) & ~0x20000)
1175 #define RELAX_MICROMIPS_TOOFAR32(i) (((i) & 0x40000) != 0)
1176 #define RELAX_MICROMIPS_MARK_TOOFAR32(i) ((i) | 0x40000)
1177 #define RELAX_MICROMIPS_CLEAR_TOOFAR32(i) ((i) & ~0x40000)
1179 /* Sign-extend 16-bit value X. */
1180 #define SEXT_16BIT(X) ((((X) + 0x8000) & 0xffff) - 0x8000)
1182 /* Is the given value a sign-extended 32-bit value? */
1183 #define IS_SEXT_32BIT_NUM(x) \
1184 (((x) &~ (offsetT) 0x7fffffff) == 0 \
1185 || (((x) &~ (offsetT) 0x7fffffff) == ~ (offsetT) 0x7fffffff))
1187 /* Is the given value a sign-extended 16-bit value? */
1188 #define IS_SEXT_16BIT_NUM(x) \
1189 (((x) &~ (offsetT) 0x7fff) == 0 \
1190 || (((x) &~ (offsetT) 0x7fff) == ~ (offsetT) 0x7fff))
1192 /* Is the given value a sign-extended 12-bit value? */
1193 #define IS_SEXT_12BIT_NUM(x) \
1194 (((((x) & 0xfff) ^ 0x800LL) - 0x800LL) == (x))
1196 /* Is the given value a zero-extended 32-bit value? Or a negated one? */
1197 #define IS_ZEXT_32BIT_NUM(x) \
1198 (((x) &~ (offsetT) 0xffffffff) == 0 \
1199 || (((x) &~ (offsetT) 0xffffffff) == ~ (offsetT) 0xffffffff))
1201 /* Replace bits MASK << SHIFT of STRUCT with the equivalent bits in
1202 VALUE << SHIFT. VALUE is evaluated exactly once. */
1203 #define INSERT_BITS(STRUCT, VALUE, MASK, SHIFT) \
1204 (STRUCT) = (((STRUCT) & ~((MASK) << (SHIFT))) \
1205 | (((VALUE) & (MASK)) << (SHIFT)))
1207 /* Extract bits MASK << SHIFT from STRUCT and shift them right
1209 #define EXTRACT_BITS(STRUCT, MASK, SHIFT) \
1210 (((STRUCT) >> (SHIFT)) & (MASK))
1212 /* Change INSN's opcode so that the operand given by FIELD has value VALUE.
1213 INSN is a mips_cl_insn structure and VALUE is evaluated exactly once.
1215 include/opcode/mips.h specifies operand fields using the macros
1216 OP_MASK_<FIELD> and OP_SH_<FIELD>. The MIPS16 equivalents start
1217 with "MIPS16OP" instead of "OP". */
1218 #define INSERT_OPERAND(MICROMIPS, FIELD, INSN, VALUE) \
1221 INSERT_BITS ((INSN).insn_opcode, VALUE, \
1222 OP_MASK_##FIELD, OP_SH_##FIELD); \
1224 INSERT_BITS ((INSN).insn_opcode, VALUE, \
1225 MICROMIPSOP_MASK_##FIELD, MICROMIPSOP_SH_##FIELD); \
1227 #define MIPS16_INSERT_OPERAND(FIELD, INSN, VALUE) \
1228 INSERT_BITS ((INSN).insn_opcode, VALUE, \
1229 MIPS16OP_MASK_##FIELD, MIPS16OP_SH_##FIELD)
1231 /* Extract the operand given by FIELD from mips_cl_insn INSN. */
1232 #define EXTRACT_OPERAND(MICROMIPS, FIELD, INSN) \
1234 ? EXTRACT_BITS ((INSN).insn_opcode, OP_MASK_##FIELD, OP_SH_##FIELD) \
1235 : EXTRACT_BITS ((INSN).insn_opcode, \
1236 MICROMIPSOP_MASK_##FIELD, MICROMIPSOP_SH_##FIELD))
1237 #define MIPS16_EXTRACT_OPERAND(FIELD, INSN) \
1238 EXTRACT_BITS ((INSN).insn_opcode, \
1239 MIPS16OP_MASK_##FIELD, \
1240 MIPS16OP_SH_##FIELD)
1242 /* The MIPS16 EXTEND opcode, shifted left 16 places. */
1243 #define MIPS16_EXTEND (0xf000U << 16)
1245 /* Whether or not we are emitting a branch-likely macro. */
1246 static bfd_boolean emit_branch_likely_macro
= FALSE
;
1248 /* Global variables used when generating relaxable macros. See the
1249 comment above RELAX_ENCODE for more details about how relaxation
1252 /* 0 if we're not emitting a relaxable macro.
1253 1 if we're emitting the first of the two relaxation alternatives.
1254 2 if we're emitting the second alternative. */
1257 /* The first relaxable fixup in the current frag. (In other words,
1258 the first fixup that refers to relaxable code.) */
1261 /* sizes[0] says how many bytes of the first alternative are stored in
1262 the current frag. Likewise sizes[1] for the second alternative. */
1263 unsigned int sizes
[2];
1265 /* The symbol on which the choice of sequence depends. */
1269 /* Global variables used to decide whether a macro needs a warning. */
1271 /* True if the macro is in a branch delay slot. */
1272 bfd_boolean delay_slot_p
;
1274 /* Set to the length in bytes required if the macro is in a delay slot
1275 that requires a specific length of instruction, otherwise zero. */
1276 unsigned int delay_slot_length
;
1278 /* For relaxable macros, sizes[0] is the length of the first alternative
1279 in bytes and sizes[1] is the length of the second alternative.
1280 For non-relaxable macros, both elements give the length of the
1282 unsigned int sizes
[2];
1284 /* For relaxable macros, first_insn_sizes[0] is the length of the first
1285 instruction of the first alternative in bytes and first_insn_sizes[1]
1286 is the length of the first instruction of the second alternative.
1287 For non-relaxable macros, both elements give the length of the first
1288 instruction in bytes.
1290 Set to zero if we haven't yet seen the first instruction. */
1291 unsigned int first_insn_sizes
[2];
1293 /* For relaxable macros, insns[0] is the number of instructions for the
1294 first alternative and insns[1] is the number of instructions for the
1297 For non-relaxable macros, both elements give the number of
1298 instructions for the macro. */
1299 unsigned int insns
[2];
1301 /* The first variant frag for this macro. */
1303 } mips_macro_warning
;
1305 /* Prototypes for static functions. */
1307 #define internalError() \
1308 as_fatal (_("internal Error, line %d, %s"), __LINE__, __FILE__)
1310 enum mips_regclass
{ MIPS_GR_REG
, MIPS_FP_REG
, MIPS16_REG
};
1312 static void append_insn
1313 (struct mips_cl_insn
*, expressionS
*, bfd_reloc_code_real_type
*,
1314 bfd_boolean expansionp
);
1315 static void mips_no_prev_insn (void);
1316 static void macro_build (expressionS
*, const char *, const char *, ...);
1317 static void mips16_macro_build
1318 (expressionS
*, const char *, const char *, va_list *);
1319 static void load_register (int, expressionS
*, int);
1320 static void macro_start (void);
1321 static void macro_end (void);
1322 static void macro (struct mips_cl_insn
* ip
);
1323 static void mips16_macro (struct mips_cl_insn
* ip
);
1324 static void mips_ip (char *str
, struct mips_cl_insn
* ip
);
1325 static void mips16_ip (char *str
, struct mips_cl_insn
* ip
);
1326 static void mips16_immed
1327 (char *, unsigned int, int, bfd_reloc_code_real_type
, offsetT
,
1328 unsigned int, unsigned long *);
1329 static size_t my_getSmallExpression
1330 (expressionS
*, bfd_reloc_code_real_type
*, char *);
1331 static void my_getExpression (expressionS
*, char *);
1332 static void s_align (int);
1333 static void s_change_sec (int);
1334 static void s_change_section (int);
1335 static void s_cons (int);
1336 static void s_float_cons (int);
1337 static void s_mips_globl (int);
1338 static void s_option (int);
1339 static void s_mipsset (int);
1340 static void s_abicalls (int);
1341 static void s_cpload (int);
1342 static void s_cpsetup (int);
1343 static void s_cplocal (int);
1344 static void s_cprestore (int);
1345 static void s_cpreturn (int);
1346 static void s_dtprelword (int);
1347 static void s_dtpreldword (int);
1348 static void s_tprelword (int);
1349 static void s_tpreldword (int);
1350 static void s_gpvalue (int);
1351 static void s_gpword (int);
1352 static void s_gpdword (int);
1353 static void s_cpadd (int);
1354 static void s_insn (int);
1355 static void md_obj_begin (void);
1356 static void md_obj_end (void);
1357 static void s_mips_ent (int);
1358 static void s_mips_end (int);
1359 static void s_mips_frame (int);
1360 static void s_mips_mask (int reg_type
);
1361 static void s_mips_stab (int);
1362 static void s_mips_weakext (int);
1363 static void s_mips_file (int);
1364 static void s_mips_loc (int);
1365 static bfd_boolean
pic_need_relax (symbolS
*, asection
*);
1366 static int relaxed_branch_length (fragS
*, asection
*, int);
1367 static int validate_mips_insn (const struct mips_opcode
*);
1368 static int validate_micromips_insn (const struct mips_opcode
*);
1369 static int relaxed_micromips_16bit_branch_length (fragS
*, asection
*, int);
1370 static int relaxed_micromips_32bit_branch_length (fragS
*, asection
*, int);
1372 /* Table and functions used to map between CPU/ISA names, and
1373 ISA levels, and CPU numbers. */
1375 struct mips_cpu_info
1377 const char *name
; /* CPU or ISA name. */
1378 int flags
; /* ASEs available, or ISA flag. */
1379 int isa
; /* ISA level. */
1380 int cpu
; /* CPU number (default CPU if ISA). */
1383 #define MIPS_CPU_IS_ISA 0x0001 /* Is this an ISA? (If 0, a CPU.) */
1384 #define MIPS_CPU_ASE_SMARTMIPS 0x0002 /* CPU implements SmartMIPS ASE */
1385 #define MIPS_CPU_ASE_DSP 0x0004 /* CPU implements DSP ASE */
1386 #define MIPS_CPU_ASE_MT 0x0008 /* CPU implements MT ASE */
1387 #define MIPS_CPU_ASE_MIPS3D 0x0010 /* CPU implements MIPS-3D ASE */
1388 #define MIPS_CPU_ASE_MDMX 0x0020 /* CPU implements MDMX ASE */
1389 #define MIPS_CPU_ASE_DSPR2 0x0040 /* CPU implements DSP R2 ASE */
1390 #define MIPS_CPU_ASE_MCU 0x0080 /* CPU implements MCU ASE */
1392 static const struct mips_cpu_info
*mips_parse_cpu (const char *, const char *);
1393 static const struct mips_cpu_info
*mips_cpu_info_from_isa (int);
1394 static const struct mips_cpu_info
*mips_cpu_info_from_arch (int);
1398 The following pseudo-ops from the Kane and Heinrich MIPS book
1399 should be defined here, but are currently unsupported: .alias,
1400 .galive, .gjaldef, .gjrlive, .livereg, .noalias.
1402 The following pseudo-ops from the Kane and Heinrich MIPS book are
1403 specific to the type of debugging information being generated, and
1404 should be defined by the object format: .aent, .begin, .bend,
1405 .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp,
1408 The following pseudo-ops from the Kane and Heinrich MIPS book are
1409 not MIPS CPU specific, but are also not specific to the object file
1410 format. This file is probably the best place to define them, but
1411 they are not currently supported: .asm0, .endr, .lab, .struct. */
1413 static const pseudo_typeS mips_pseudo_table
[] =
1415 /* MIPS specific pseudo-ops. */
1416 {"option", s_option
, 0},
1417 {"set", s_mipsset
, 0},
1418 {"rdata", s_change_sec
, 'r'},
1419 {"sdata", s_change_sec
, 's'},
1420 {"livereg", s_ignore
, 0},
1421 {"abicalls", s_abicalls
, 0},
1422 {"cpload", s_cpload
, 0},
1423 {"cpsetup", s_cpsetup
, 0},
1424 {"cplocal", s_cplocal
, 0},
1425 {"cprestore", s_cprestore
, 0},
1426 {"cpreturn", s_cpreturn
, 0},
1427 {"dtprelword", s_dtprelword
, 0},
1428 {"dtpreldword", s_dtpreldword
, 0},
1429 {"tprelword", s_tprelword
, 0},
1430 {"tpreldword", s_tpreldword
, 0},
1431 {"gpvalue", s_gpvalue
, 0},
1432 {"gpword", s_gpword
, 0},
1433 {"gpdword", s_gpdword
, 0},
1434 {"cpadd", s_cpadd
, 0},
1435 {"insn", s_insn
, 0},
1437 /* Relatively generic pseudo-ops that happen to be used on MIPS
1439 {"asciiz", stringer
, 8 + 1},
1440 {"bss", s_change_sec
, 'b'},
1442 {"half", s_cons
, 1},
1443 {"dword", s_cons
, 3},
1444 {"weakext", s_mips_weakext
, 0},
1445 {"origin", s_org
, 0},
1446 {"repeat", s_rept
, 0},
1448 /* For MIPS this is non-standard, but we define it for consistency. */
1449 {"sbss", s_change_sec
, 'B'},
1451 /* These pseudo-ops are defined in read.c, but must be overridden
1452 here for one reason or another. */
1453 {"align", s_align
, 0},
1454 {"byte", s_cons
, 0},
1455 {"data", s_change_sec
, 'd'},
1456 {"double", s_float_cons
, 'd'},
1457 {"float", s_float_cons
, 'f'},
1458 {"globl", s_mips_globl
, 0},
1459 {"global", s_mips_globl
, 0},
1460 {"hword", s_cons
, 1},
1462 {"long", s_cons
, 2},
1463 {"octa", s_cons
, 4},
1464 {"quad", s_cons
, 3},
1465 {"section", s_change_section
, 0},
1466 {"short", s_cons
, 1},
1467 {"single", s_float_cons
, 'f'},
1468 {"stabn", s_mips_stab
, 'n'},
1469 {"text", s_change_sec
, 't'},
1470 {"word", s_cons
, 2},
1472 { "extern", ecoff_directive_extern
, 0},
1477 static const pseudo_typeS mips_nonecoff_pseudo_table
[] =
1479 /* These pseudo-ops should be defined by the object file format.
1480 However, a.out doesn't support them, so we have versions here. */
1481 {"aent", s_mips_ent
, 1},
1482 {"bgnb", s_ignore
, 0},
1483 {"end", s_mips_end
, 0},
1484 {"endb", s_ignore
, 0},
1485 {"ent", s_mips_ent
, 0},
1486 {"file", s_mips_file
, 0},
1487 {"fmask", s_mips_mask
, 'F'},
1488 {"frame", s_mips_frame
, 0},
1489 {"loc", s_mips_loc
, 0},
1490 {"mask", s_mips_mask
, 'R'},
1491 {"verstamp", s_ignore
, 0},
1495 /* Export the ABI address size for use by TC_ADDRESS_BYTES for the
1496 purpose of the `.dc.a' internal pseudo-op. */
1499 mips_address_bytes (void)
1501 return HAVE_64BIT_ADDRESSES
? 8 : 4;
1504 extern void pop_insert (const pseudo_typeS
*);
1507 mips_pop_insert (void)
1509 pop_insert (mips_pseudo_table
);
1510 if (! ECOFF_DEBUGGING
)
1511 pop_insert (mips_nonecoff_pseudo_table
);
1514 /* Symbols labelling the current insn. */
1516 struct insn_label_list
1518 struct insn_label_list
*next
;
1522 static struct insn_label_list
*free_insn_labels
;
1523 #define label_list tc_segment_info_data.labels
1525 static void mips_clear_insn_labels (void);
1526 static void mips_mark_labels (void);
1527 static void mips_compressed_mark_labels (void);
1530 mips_clear_insn_labels (void)
1532 register struct insn_label_list
**pl
;
1533 segment_info_type
*si
;
1537 for (pl
= &free_insn_labels
; *pl
!= NULL
; pl
= &(*pl
)->next
)
1540 si
= seg_info (now_seg
);
1541 *pl
= si
->label_list
;
1542 si
->label_list
= NULL
;
1546 /* Mark instruction labels in MIPS16/microMIPS mode. */
1549 mips_mark_labels (void)
1551 if (HAVE_CODE_COMPRESSION
)
1552 mips_compressed_mark_labels ();
1555 static char *expr_end
;
1557 /* Expressions which appear in instructions. These are set by
1560 static expressionS imm_expr
;
1561 static expressionS imm2_expr
;
1562 static expressionS offset_expr
;
1564 /* Relocs associated with imm_expr and offset_expr. */
1566 static bfd_reloc_code_real_type imm_reloc
[3]
1567 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
1568 static bfd_reloc_code_real_type offset_reloc
[3]
1569 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
1571 /* This is set to the resulting size of the instruction to be produced
1572 by mips16_ip if an explicit extension is used or by mips_ip if an
1573 explicit size is supplied. */
1575 static unsigned int forced_insn_length
;
1577 /* True if we are assembling an instruction. All dot symbols defined during
1578 this time should be treated as code labels. */
1580 static bfd_boolean mips_assembling_insn
;
1583 /* The pdr segment for per procedure frame/regmask info. Not used for
1586 static segT pdr_seg
;
1589 /* The default target format to use. */
1591 #if defined (TE_FreeBSD)
1592 #define ELF_TARGET(PREFIX, ENDIAN) PREFIX "trad" ENDIAN "mips-freebsd"
1593 #elif defined (TE_TMIPS)
1594 #define ELF_TARGET(PREFIX, ENDIAN) PREFIX "trad" ENDIAN "mips"
1596 #define ELF_TARGET(PREFIX, ENDIAN) PREFIX ENDIAN "mips"
1600 mips_target_format (void)
1602 switch (OUTPUT_FLAVOR
)
1604 case bfd_target_ecoff_flavour
:
1605 return target_big_endian
? "ecoff-bigmips" : ECOFF_LITTLE_FORMAT
;
1606 case bfd_target_coff_flavour
:
1608 case bfd_target_elf_flavour
:
1610 if (!HAVE_64BIT_OBJECTS
&& !HAVE_NEWABI
)
1611 return (target_big_endian
1612 ? "elf32-bigmips-vxworks"
1613 : "elf32-littlemips-vxworks");
1615 return (target_big_endian
1616 ? (HAVE_64BIT_OBJECTS
1617 ? ELF_TARGET ("elf64-", "big")
1619 ? ELF_TARGET ("elf32-n", "big")
1620 : ELF_TARGET ("elf32-", "big")))
1621 : (HAVE_64BIT_OBJECTS
1622 ? ELF_TARGET ("elf64-", "little")
1624 ? ELF_TARGET ("elf32-n", "little")
1625 : ELF_TARGET ("elf32-", "little"))));
1632 /* Return the length of a microMIPS instruction in bytes. If bits of
1633 the mask beyond the low 16 are 0, then it is a 16-bit instruction.
1634 Otherwise assume a 32-bit instruction; 48-bit instructions (0x1f
1635 major opcode) will require further modifications to the opcode
1638 static inline unsigned int
1639 micromips_insn_length (const struct mips_opcode
*mo
)
1641 return (mo
->mask
>> 16) == 0 ? 2 : 4;
1644 /* Return the length of MIPS16 instruction OPCODE. */
1646 static inline unsigned int
1647 mips16_opcode_length (unsigned long opcode
)
1649 return (opcode
>> 16) == 0 ? 2 : 4;
1652 /* Return the length of instruction INSN. */
1654 static inline unsigned int
1655 insn_length (const struct mips_cl_insn
*insn
)
1657 if (mips_opts
.micromips
)
1658 return micromips_insn_length (insn
->insn_mo
);
1659 else if (mips_opts
.mips16
)
1660 return mips16_opcode_length (insn
->insn_opcode
);
1665 /* Initialise INSN from opcode entry MO. Leave its position unspecified. */
1668 create_insn (struct mips_cl_insn
*insn
, const struct mips_opcode
*mo
)
1673 insn
->insn_opcode
= mo
->match
;
1676 for (i
= 0; i
< ARRAY_SIZE (insn
->fixp
); i
++)
1677 insn
->fixp
[i
] = NULL
;
1678 insn
->fixed_p
= (mips_opts
.noreorder
> 0);
1679 insn
->noreorder_p
= (mips_opts
.noreorder
> 0);
1680 insn
->mips16_absolute_jump_p
= 0;
1681 insn
->complete_p
= 0;
1684 /* Record the current MIPS16/microMIPS mode in now_seg. */
1687 mips_record_compressed_mode (void)
1689 segment_info_type
*si
;
1691 si
= seg_info (now_seg
);
1692 if (si
->tc_segment_info_data
.mips16
!= mips_opts
.mips16
)
1693 si
->tc_segment_info_data
.mips16
= mips_opts
.mips16
;
1694 if (si
->tc_segment_info_data
.micromips
!= mips_opts
.micromips
)
1695 si
->tc_segment_info_data
.micromips
= mips_opts
.micromips
;
1698 /* Read a standard MIPS instruction from BUF. */
1700 static unsigned long
1701 read_insn (char *buf
)
1703 if (target_big_endian
)
1704 return bfd_getb32 ((bfd_byte
*) buf
);
1706 return bfd_getl32 ((bfd_byte
*) buf
);
1709 /* Write standard MIPS instruction INSN to BUF. Return a pointer to
1713 write_insn (char *buf
, unsigned int insn
)
1715 md_number_to_chars (buf
, insn
, 4);
1719 /* Read a microMIPS or MIPS16 opcode from BUF, given that it
1720 has length LENGTH. */
1722 static unsigned long
1723 read_compressed_insn (char *buf
, unsigned int length
)
1729 for (i
= 0; i
< length
; i
+= 2)
1732 if (target_big_endian
)
1733 insn
|= bfd_getb16 ((char *) buf
);
1735 insn
|= bfd_getl16 ((char *) buf
);
1741 /* Write microMIPS or MIPS16 instruction INSN to BUF, given that the
1742 instruction is LENGTH bytes long. Return a pointer to the next byte. */
1745 write_compressed_insn (char *buf
, unsigned int insn
, unsigned int length
)
1749 for (i
= 0; i
< length
; i
+= 2)
1750 md_number_to_chars (buf
+ i
, insn
>> ((length
- i
- 2) * 8), 2);
1751 return buf
+ length
;
1754 /* Install INSN at the location specified by its "frag" and "where" fields. */
1757 install_insn (const struct mips_cl_insn
*insn
)
1759 char *f
= insn
->frag
->fr_literal
+ insn
->where
;
1760 if (HAVE_CODE_COMPRESSION
)
1761 write_compressed_insn (f
, insn
->insn_opcode
, insn_length (insn
));
1763 write_insn (f
, insn
->insn_opcode
);
1764 mips_record_compressed_mode ();
1767 /* Move INSN to offset WHERE in FRAG. Adjust the fixups accordingly
1768 and install the opcode in the new location. */
1771 move_insn (struct mips_cl_insn
*insn
, fragS
*frag
, long where
)
1776 insn
->where
= where
;
1777 for (i
= 0; i
< ARRAY_SIZE (insn
->fixp
); i
++)
1778 if (insn
->fixp
[i
] != NULL
)
1780 insn
->fixp
[i
]->fx_frag
= frag
;
1781 insn
->fixp
[i
]->fx_where
= where
;
1783 install_insn (insn
);
1786 /* Add INSN to the end of the output. */
1789 add_fixed_insn (struct mips_cl_insn
*insn
)
1791 char *f
= frag_more (insn_length (insn
));
1792 move_insn (insn
, frag_now
, f
- frag_now
->fr_literal
);
1795 /* Start a variant frag and move INSN to the start of the variant part,
1796 marking it as fixed. The other arguments are as for frag_var. */
1799 add_relaxed_insn (struct mips_cl_insn
*insn
, int max_chars
, int var
,
1800 relax_substateT subtype
, symbolS
*symbol
, offsetT offset
)
1802 frag_grow (max_chars
);
1803 move_insn (insn
, frag_now
, frag_more (0) - frag_now
->fr_literal
);
1805 frag_var (rs_machine_dependent
, max_chars
, var
,
1806 subtype
, symbol
, offset
, NULL
);
1809 /* Insert N copies of INSN into the history buffer, starting at
1810 position FIRST. Neither FIRST nor N need to be clipped. */
1813 insert_into_history (unsigned int first
, unsigned int n
,
1814 const struct mips_cl_insn
*insn
)
1816 if (mips_relax
.sequence
!= 2)
1820 for (i
= ARRAY_SIZE (history
); i
-- > first
;)
1822 history
[i
] = history
[i
- n
];
1828 /* Initialize vr4120_conflicts. There is a bit of duplication here:
1829 the idea is to make it obvious at a glance that each errata is
1833 init_vr4120_conflicts (void)
1835 #define CONFLICT(FIRST, SECOND) \
1836 vr4120_conflicts[FIX_VR4120_##FIRST] |= 1 << FIX_VR4120_##SECOND
1838 /* Errata 21 - [D]DIV[U] after [D]MACC */
1839 CONFLICT (MACC
, DIV
);
1840 CONFLICT (DMACC
, DIV
);
1842 /* Errata 23 - Continuous DMULT[U]/DMACC instructions. */
1843 CONFLICT (DMULT
, DMULT
);
1844 CONFLICT (DMULT
, DMACC
);
1845 CONFLICT (DMACC
, DMULT
);
1846 CONFLICT (DMACC
, DMACC
);
1848 /* Errata 24 - MT{LO,HI} after [D]MACC */
1849 CONFLICT (MACC
, MTHILO
);
1850 CONFLICT (DMACC
, MTHILO
);
1852 /* VR4181A errata MD(1): "If a MULT, MULTU, DMULT or DMULTU
1853 instruction is executed immediately after a MACC or DMACC
1854 instruction, the result of [either instruction] is incorrect." */
1855 CONFLICT (MACC
, MULT
);
1856 CONFLICT (MACC
, DMULT
);
1857 CONFLICT (DMACC
, MULT
);
1858 CONFLICT (DMACC
, DMULT
);
1860 /* VR4181A errata MD(4): "If a MACC or DMACC instruction is
1861 executed immediately after a DMULT, DMULTU, DIV, DIVU,
1862 DDIV or DDIVU instruction, the result of the MACC or
1863 DMACC instruction is incorrect.". */
1864 CONFLICT (DMULT
, MACC
);
1865 CONFLICT (DMULT
, DMACC
);
1866 CONFLICT (DIV
, MACC
);
1867 CONFLICT (DIV
, DMACC
);
1877 #define RTYPE_MASK 0x1ff00
1878 #define RTYPE_NUM 0x00100
1879 #define RTYPE_FPU 0x00200
1880 #define RTYPE_FCC 0x00400
1881 #define RTYPE_VEC 0x00800
1882 #define RTYPE_GP 0x01000
1883 #define RTYPE_CP0 0x02000
1884 #define RTYPE_PC 0x04000
1885 #define RTYPE_ACC 0x08000
1886 #define RTYPE_CCC 0x10000
1887 #define RNUM_MASK 0x000ff
1888 #define RWARN 0x80000
1890 #define GENERIC_REGISTER_NUMBERS \
1891 {"$0", RTYPE_NUM | 0}, \
1892 {"$1", RTYPE_NUM | 1}, \
1893 {"$2", RTYPE_NUM | 2}, \
1894 {"$3", RTYPE_NUM | 3}, \
1895 {"$4", RTYPE_NUM | 4}, \
1896 {"$5", RTYPE_NUM | 5}, \
1897 {"$6", RTYPE_NUM | 6}, \
1898 {"$7", RTYPE_NUM | 7}, \
1899 {"$8", RTYPE_NUM | 8}, \
1900 {"$9", RTYPE_NUM | 9}, \
1901 {"$10", RTYPE_NUM | 10}, \
1902 {"$11", RTYPE_NUM | 11}, \
1903 {"$12", RTYPE_NUM | 12}, \
1904 {"$13", RTYPE_NUM | 13}, \
1905 {"$14", RTYPE_NUM | 14}, \
1906 {"$15", RTYPE_NUM | 15}, \
1907 {"$16", RTYPE_NUM | 16}, \
1908 {"$17", RTYPE_NUM | 17}, \
1909 {"$18", RTYPE_NUM | 18}, \
1910 {"$19", RTYPE_NUM | 19}, \
1911 {"$20", RTYPE_NUM | 20}, \
1912 {"$21", RTYPE_NUM | 21}, \
1913 {"$22", RTYPE_NUM | 22}, \
1914 {"$23", RTYPE_NUM | 23}, \
1915 {"$24", RTYPE_NUM | 24}, \
1916 {"$25", RTYPE_NUM | 25}, \
1917 {"$26", RTYPE_NUM | 26}, \
1918 {"$27", RTYPE_NUM | 27}, \
1919 {"$28", RTYPE_NUM | 28}, \
1920 {"$29", RTYPE_NUM | 29}, \
1921 {"$30", RTYPE_NUM | 30}, \
1922 {"$31", RTYPE_NUM | 31}
1924 #define FPU_REGISTER_NAMES \
1925 {"$f0", RTYPE_FPU | 0}, \
1926 {"$f1", RTYPE_FPU | 1}, \
1927 {"$f2", RTYPE_FPU | 2}, \
1928 {"$f3", RTYPE_FPU | 3}, \
1929 {"$f4", RTYPE_FPU | 4}, \
1930 {"$f5", RTYPE_FPU | 5}, \
1931 {"$f6", RTYPE_FPU | 6}, \
1932 {"$f7", RTYPE_FPU | 7}, \
1933 {"$f8", RTYPE_FPU | 8}, \
1934 {"$f9", RTYPE_FPU | 9}, \
1935 {"$f10", RTYPE_FPU | 10}, \
1936 {"$f11", RTYPE_FPU | 11}, \
1937 {"$f12", RTYPE_FPU | 12}, \
1938 {"$f13", RTYPE_FPU | 13}, \
1939 {"$f14", RTYPE_FPU | 14}, \
1940 {"$f15", RTYPE_FPU | 15}, \
1941 {"$f16", RTYPE_FPU | 16}, \
1942 {"$f17", RTYPE_FPU | 17}, \
1943 {"$f18", RTYPE_FPU | 18}, \
1944 {"$f19", RTYPE_FPU | 19}, \
1945 {"$f20", RTYPE_FPU | 20}, \
1946 {"$f21", RTYPE_FPU | 21}, \
1947 {"$f22", RTYPE_FPU | 22}, \
1948 {"$f23", RTYPE_FPU | 23}, \
1949 {"$f24", RTYPE_FPU | 24}, \
1950 {"$f25", RTYPE_FPU | 25}, \
1951 {"$f26", RTYPE_FPU | 26}, \
1952 {"$f27", RTYPE_FPU | 27}, \
1953 {"$f28", RTYPE_FPU | 28}, \
1954 {"$f29", RTYPE_FPU | 29}, \
1955 {"$f30", RTYPE_FPU | 30}, \
1956 {"$f31", RTYPE_FPU | 31}
1958 #define FPU_CONDITION_CODE_NAMES \
1959 {"$fcc0", RTYPE_FCC | 0}, \
1960 {"$fcc1", RTYPE_FCC | 1}, \
1961 {"$fcc2", RTYPE_FCC | 2}, \
1962 {"$fcc3", RTYPE_FCC | 3}, \
1963 {"$fcc4", RTYPE_FCC | 4}, \
1964 {"$fcc5", RTYPE_FCC | 5}, \
1965 {"$fcc6", RTYPE_FCC | 6}, \
1966 {"$fcc7", RTYPE_FCC | 7}
1968 #define COPROC_CONDITION_CODE_NAMES \
1969 {"$cc0", RTYPE_FCC | RTYPE_CCC | 0}, \
1970 {"$cc1", RTYPE_FCC | RTYPE_CCC | 1}, \
1971 {"$cc2", RTYPE_FCC | RTYPE_CCC | 2}, \
1972 {"$cc3", RTYPE_FCC | RTYPE_CCC | 3}, \
1973 {"$cc4", RTYPE_FCC | RTYPE_CCC | 4}, \
1974 {"$cc5", RTYPE_FCC | RTYPE_CCC | 5}, \
1975 {"$cc6", RTYPE_FCC | RTYPE_CCC | 6}, \
1976 {"$cc7", RTYPE_FCC | RTYPE_CCC | 7}
1978 #define N32N64_SYMBOLIC_REGISTER_NAMES \
1979 {"$a4", RTYPE_GP | 8}, \
1980 {"$a5", RTYPE_GP | 9}, \
1981 {"$a6", RTYPE_GP | 10}, \
1982 {"$a7", RTYPE_GP | 11}, \
1983 {"$ta0", RTYPE_GP | 8}, /* alias for $a4 */ \
1984 {"$ta1", RTYPE_GP | 9}, /* alias for $a5 */ \
1985 {"$ta2", RTYPE_GP | 10}, /* alias for $a6 */ \
1986 {"$ta3", RTYPE_GP | 11}, /* alias for $a7 */ \
1987 {"$t0", RTYPE_GP | 12}, \
1988 {"$t1", RTYPE_GP | 13}, \
1989 {"$t2", RTYPE_GP | 14}, \
1990 {"$t3", RTYPE_GP | 15}
1992 #define O32_SYMBOLIC_REGISTER_NAMES \
1993 {"$t0", RTYPE_GP | 8}, \
1994 {"$t1", RTYPE_GP | 9}, \
1995 {"$t2", RTYPE_GP | 10}, \
1996 {"$t3", RTYPE_GP | 11}, \
1997 {"$t4", RTYPE_GP | 12}, \
1998 {"$t5", RTYPE_GP | 13}, \
1999 {"$t6", RTYPE_GP | 14}, \
2000 {"$t7", RTYPE_GP | 15}, \
2001 {"$ta0", RTYPE_GP | 12}, /* alias for $t4 */ \
2002 {"$ta1", RTYPE_GP | 13}, /* alias for $t5 */ \
2003 {"$ta2", RTYPE_GP | 14}, /* alias for $t6 */ \
2004 {"$ta3", RTYPE_GP | 15} /* alias for $t7 */
2006 /* Remaining symbolic register names */
2007 #define SYMBOLIC_REGISTER_NAMES \
2008 {"$zero", RTYPE_GP | 0}, \
2009 {"$at", RTYPE_GP | 1}, \
2010 {"$AT", RTYPE_GP | 1}, \
2011 {"$v0", RTYPE_GP | 2}, \
2012 {"$v1", RTYPE_GP | 3}, \
2013 {"$a0", RTYPE_GP | 4}, \
2014 {"$a1", RTYPE_GP | 5}, \
2015 {"$a2", RTYPE_GP | 6}, \
2016 {"$a3", RTYPE_GP | 7}, \
2017 {"$s0", RTYPE_GP | 16}, \
2018 {"$s1", RTYPE_GP | 17}, \
2019 {"$s2", RTYPE_GP | 18}, \
2020 {"$s3", RTYPE_GP | 19}, \
2021 {"$s4", RTYPE_GP | 20}, \
2022 {"$s5", RTYPE_GP | 21}, \
2023 {"$s6", RTYPE_GP | 22}, \
2024 {"$s7", RTYPE_GP | 23}, \
2025 {"$t8", RTYPE_GP | 24}, \
2026 {"$t9", RTYPE_GP | 25}, \
2027 {"$k0", RTYPE_GP | 26}, \
2028 {"$kt0", RTYPE_GP | 26}, \
2029 {"$k1", RTYPE_GP | 27}, \
2030 {"$kt1", RTYPE_GP | 27}, \
2031 {"$gp", RTYPE_GP | 28}, \
2032 {"$sp", RTYPE_GP | 29}, \
2033 {"$s8", RTYPE_GP | 30}, \
2034 {"$fp", RTYPE_GP | 30}, \
2035 {"$ra", RTYPE_GP | 31}
2037 #define MIPS16_SPECIAL_REGISTER_NAMES \
2038 {"$pc", RTYPE_PC | 0}
2040 #define MDMX_VECTOR_REGISTER_NAMES \
2041 /* {"$v0", RTYPE_VEC | 0}, clash with REG 2 above */ \
2042 /* {"$v1", RTYPE_VEC | 1}, clash with REG 3 above */ \
2043 {"$v2", RTYPE_VEC | 2}, \
2044 {"$v3", RTYPE_VEC | 3}, \
2045 {"$v4", RTYPE_VEC | 4}, \
2046 {"$v5", RTYPE_VEC | 5}, \
2047 {"$v6", RTYPE_VEC | 6}, \
2048 {"$v7", RTYPE_VEC | 7}, \
2049 {"$v8", RTYPE_VEC | 8}, \
2050 {"$v9", RTYPE_VEC | 9}, \
2051 {"$v10", RTYPE_VEC | 10}, \
2052 {"$v11", RTYPE_VEC | 11}, \
2053 {"$v12", RTYPE_VEC | 12}, \
2054 {"$v13", RTYPE_VEC | 13}, \
2055 {"$v14", RTYPE_VEC | 14}, \
2056 {"$v15", RTYPE_VEC | 15}, \
2057 {"$v16", RTYPE_VEC | 16}, \
2058 {"$v17", RTYPE_VEC | 17}, \
2059 {"$v18", RTYPE_VEC | 18}, \
2060 {"$v19", RTYPE_VEC | 19}, \
2061 {"$v20", RTYPE_VEC | 20}, \
2062 {"$v21", RTYPE_VEC | 21}, \
2063 {"$v22", RTYPE_VEC | 22}, \
2064 {"$v23", RTYPE_VEC | 23}, \
2065 {"$v24", RTYPE_VEC | 24}, \
2066 {"$v25", RTYPE_VEC | 25}, \
2067 {"$v26", RTYPE_VEC | 26}, \
2068 {"$v27", RTYPE_VEC | 27}, \
2069 {"$v28", RTYPE_VEC | 28}, \
2070 {"$v29", RTYPE_VEC | 29}, \
2071 {"$v30", RTYPE_VEC | 30}, \
2072 {"$v31", RTYPE_VEC | 31}
2074 #define MIPS_DSP_ACCUMULATOR_NAMES \
2075 {"$ac0", RTYPE_ACC | 0}, \
2076 {"$ac1", RTYPE_ACC | 1}, \
2077 {"$ac2", RTYPE_ACC | 2}, \
2078 {"$ac3", RTYPE_ACC | 3}
2080 static const struct regname reg_names
[] = {
2081 GENERIC_REGISTER_NUMBERS
,
2083 FPU_CONDITION_CODE_NAMES
,
2084 COPROC_CONDITION_CODE_NAMES
,
2086 /* The $txx registers depends on the abi,
2087 these will be added later into the symbol table from
2088 one of the tables below once mips_abi is set after
2089 parsing of arguments from the command line. */
2090 SYMBOLIC_REGISTER_NAMES
,
2092 MIPS16_SPECIAL_REGISTER_NAMES
,
2093 MDMX_VECTOR_REGISTER_NAMES
,
2094 MIPS_DSP_ACCUMULATOR_NAMES
,
2098 static const struct regname reg_names_o32
[] = {
2099 O32_SYMBOLIC_REGISTER_NAMES
,
2103 static const struct regname reg_names_n32n64
[] = {
2104 N32N64_SYMBOLIC_REGISTER_NAMES
,
2108 /* Check if S points at a valid register specifier according to TYPES.
2109 If so, then return 1, advance S to consume the specifier and store
2110 the register's number in REGNOP, otherwise return 0. */
2113 reg_lookup (char **s
, unsigned int types
, unsigned int *regnop
)
2120 /* Find end of name. */
2122 if (is_name_beginner (*e
))
2124 while (is_part_of_name (*e
))
2127 /* Terminate name. */
2131 /* Look for a register symbol. */
2132 if ((symbolP
= symbol_find (*s
)) && S_GET_SEGMENT (symbolP
) == reg_section
)
2134 int r
= S_GET_VALUE (symbolP
);
2136 reg
= r
& RNUM_MASK
;
2137 else if ((types
& RTYPE_VEC
) && (r
& ~1) == (RTYPE_GP
| 2))
2138 /* Convert GP reg $v0/1 to MDMX reg $v0/1! */
2139 reg
= (r
& RNUM_MASK
) - 2;
2141 /* Else see if this is a register defined in an itbl entry. */
2142 else if ((types
& RTYPE_GP
) && itbl_have_entries
)
2149 if (itbl_get_reg_val (n
, &r
))
2150 reg
= r
& RNUM_MASK
;
2153 /* Advance to next token if a register was recognised. */
2156 else if (types
& RWARN
)
2157 as_warn (_("Unrecognized register name `%s'"), *s
);
2165 /* Check if S points at a valid register list according to TYPES.
2166 If so, then return 1, advance S to consume the list and store
2167 the registers present on the list as a bitmask of ones in REGLISTP,
2168 otherwise return 0. A valid list comprises a comma-separated
2169 enumeration of valid single registers and/or dash-separated
2170 contiguous register ranges as determined by their numbers.
2172 As a special exception if one of s0-s7 registers is specified as
2173 the range's lower delimiter and s8 (fp) is its upper one, then no
2174 registers whose numbers place them between s7 and s8 (i.e. $24-$29)
2175 are selected; they have to be listed separately if needed. */
2178 reglist_lookup (char **s
, unsigned int types
, unsigned int *reglistp
)
2180 unsigned int reglist
= 0;
2181 unsigned int lastregno
;
2182 bfd_boolean ok
= TRUE
;
2183 unsigned int regmask
;
2184 char *s_endlist
= *s
;
2188 while (reg_lookup (s
, types
, ®no
))
2194 ok
= reg_lookup (s
, types
, &lastregno
);
2195 if (ok
&& lastregno
< regno
)
2201 if (lastregno
== FP
&& regno
>= S0
&& regno
<= S7
)
2206 regmask
= 1 << lastregno
;
2207 regmask
= (regmask
<< 1) - 1;
2208 regmask
^= (1 << regno
) - 1;
2222 *reglistp
= reglist
;
2223 return ok
&& reglist
!= 0;
2226 /* Return TRUE if opcode MO is valid on the currently selected ISA and
2227 architecture. Use is_opcode_valid_16 for MIPS16 opcodes. */
2230 is_opcode_valid (const struct mips_opcode
*mo
)
2232 int isa
= mips_opts
.isa
;
2235 if (mips_opts
.ase_mdmx
)
2237 if (mips_opts
.ase_dsp
)
2239 if (mips_opts
.ase_dsp
&& ISA_SUPPORTS_DSP64_ASE
)
2241 if (mips_opts
.ase_dspr2
)
2243 if (mips_opts
.ase_mt
)
2245 if (mips_opts
.ase_mips3d
)
2247 if (mips_opts
.ase_smartmips
)
2248 isa
|= INSN_SMARTMIPS
;
2249 if (mips_opts
.ase_mcu
)
2252 if (!opcode_is_member (mo
, isa
, mips_opts
.arch
))
2255 /* Check whether the instruction or macro requires single-precision or
2256 double-precision floating-point support. Note that this information is
2257 stored differently in the opcode table for insns and macros. */
2258 if (mo
->pinfo
== INSN_MACRO
)
2260 fp_s
= mo
->pinfo2
& INSN2_M_FP_S
;
2261 fp_d
= mo
->pinfo2
& INSN2_M_FP_D
;
2265 fp_s
= mo
->pinfo
& FP_S
;
2266 fp_d
= mo
->pinfo
& FP_D
;
2269 if (fp_d
&& (mips_opts
.soft_float
|| mips_opts
.single_float
))
2272 if (fp_s
&& mips_opts
.soft_float
)
2278 /* Return TRUE if the MIPS16 opcode MO is valid on the currently
2279 selected ISA and architecture. */
2282 is_opcode_valid_16 (const struct mips_opcode
*mo
)
2284 return opcode_is_member (mo
, mips_opts
.isa
, mips_opts
.arch
);
2287 /* Return TRUE if the size of the microMIPS opcode MO matches one
2288 explicitly requested. Always TRUE in the standard MIPS mode. */
2291 is_size_valid (const struct mips_opcode
*mo
)
2293 if (!mips_opts
.micromips
)
2296 if (!forced_insn_length
)
2298 if (mo
->pinfo
== INSN_MACRO
)
2300 return forced_insn_length
== micromips_insn_length (mo
);
2303 /* Return TRUE if the microMIPS opcode MO is valid for the delay slot
2304 of the preceding instruction. Always TRUE in the standard MIPS mode. */
2307 is_delay_slot_valid (const struct mips_opcode
*mo
)
2309 if (!mips_opts
.micromips
)
2312 if (mo
->pinfo
== INSN_MACRO
)
2314 if ((history
[0].insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_32BIT
) != 0
2315 && micromips_insn_length (mo
) != 4)
2317 if ((history
[0].insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_16BIT
) != 0
2318 && micromips_insn_length (mo
) != 2)
2324 /* This function is called once, at assembler startup time. It should set up
2325 all the tables, etc. that the MD part of the assembler will need. */
2330 const char *retval
= NULL
;
2334 if (mips_pic
!= NO_PIC
)
2336 if (g_switch_seen
&& g_switch_value
!= 0)
2337 as_bad (_("-G may not be used in position-independent code"));
2341 if (! bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, file_mips_arch
))
2342 as_warn (_("Could not set architecture and machine"));
2344 op_hash
= hash_new ();
2346 for (i
= 0; i
< NUMOPCODES
;)
2348 const char *name
= mips_opcodes
[i
].name
;
2350 retval
= hash_insert (op_hash
, name
, (void *) &mips_opcodes
[i
]);
2353 fprintf (stderr
, _("internal error: can't hash `%s': %s\n"),
2354 mips_opcodes
[i
].name
, retval
);
2355 /* Probably a memory allocation problem? Give up now. */
2356 as_fatal (_("Broken assembler. No assembly attempted."));
2360 if (mips_opcodes
[i
].pinfo
!= INSN_MACRO
)
2362 if (!validate_mips_insn (&mips_opcodes
[i
]))
2364 if (nop_insn
.insn_mo
== NULL
&& strcmp (name
, "nop") == 0)
2366 create_insn (&nop_insn
, mips_opcodes
+ i
);
2367 if (mips_fix_loongson2f_nop
)
2368 nop_insn
.insn_opcode
= LOONGSON2F_NOP_INSN
;
2369 nop_insn
.fixed_p
= 1;
2374 while ((i
< NUMOPCODES
) && !strcmp (mips_opcodes
[i
].name
, name
));
2377 mips16_op_hash
= hash_new ();
2380 while (i
< bfd_mips16_num_opcodes
)
2382 const char *name
= mips16_opcodes
[i
].name
;
2384 retval
= hash_insert (mips16_op_hash
, name
, (void *) &mips16_opcodes
[i
]);
2386 as_fatal (_("internal: can't hash `%s': %s"),
2387 mips16_opcodes
[i
].name
, retval
);
2390 if (mips16_opcodes
[i
].pinfo
!= INSN_MACRO
2391 && ((mips16_opcodes
[i
].match
& mips16_opcodes
[i
].mask
)
2392 != mips16_opcodes
[i
].match
))
2394 fprintf (stderr
, _("internal error: bad mips16 opcode: %s %s\n"),
2395 mips16_opcodes
[i
].name
, mips16_opcodes
[i
].args
);
2398 if (mips16_nop_insn
.insn_mo
== NULL
&& strcmp (name
, "nop") == 0)
2400 create_insn (&mips16_nop_insn
, mips16_opcodes
+ i
);
2401 mips16_nop_insn
.fixed_p
= 1;
2405 while (i
< bfd_mips16_num_opcodes
2406 && strcmp (mips16_opcodes
[i
].name
, name
) == 0);
2409 micromips_op_hash
= hash_new ();
2412 while (i
< bfd_micromips_num_opcodes
)
2414 const char *name
= micromips_opcodes
[i
].name
;
2416 retval
= hash_insert (micromips_op_hash
, name
,
2417 (void *) µmips_opcodes
[i
]);
2419 as_fatal (_("internal: can't hash `%s': %s"),
2420 micromips_opcodes
[i
].name
, retval
);
2422 if (micromips_opcodes
[i
].pinfo
!= INSN_MACRO
)
2424 struct mips_cl_insn
*micromips_nop_insn
;
2426 if (!validate_micromips_insn (µmips_opcodes
[i
]))
2429 if (micromips_insn_length (micromips_opcodes
+ i
) == 2)
2430 micromips_nop_insn
= µmips_nop16_insn
;
2431 else if (micromips_insn_length (micromips_opcodes
+ i
) == 4)
2432 micromips_nop_insn
= µmips_nop32_insn
;
2436 if (micromips_nop_insn
->insn_mo
== NULL
2437 && strcmp (name
, "nop") == 0)
2439 create_insn (micromips_nop_insn
, micromips_opcodes
+ i
);
2440 micromips_nop_insn
->fixed_p
= 1;
2443 while (++i
< bfd_micromips_num_opcodes
2444 && strcmp (micromips_opcodes
[i
].name
, name
) == 0);
2448 as_fatal (_("Broken assembler. No assembly attempted."));
2450 /* We add all the general register names to the symbol table. This
2451 helps us detect invalid uses of them. */
2452 for (i
= 0; reg_names
[i
].name
; i
++)
2453 symbol_table_insert (symbol_new (reg_names
[i
].name
, reg_section
,
2454 reg_names
[i
].num
, /* & RNUM_MASK, */
2455 &zero_address_frag
));
2457 for (i
= 0; reg_names_n32n64
[i
].name
; i
++)
2458 symbol_table_insert (symbol_new (reg_names_n32n64
[i
].name
, reg_section
,
2459 reg_names_n32n64
[i
].num
, /* & RNUM_MASK, */
2460 &zero_address_frag
));
2462 for (i
= 0; reg_names_o32
[i
].name
; i
++)
2463 symbol_table_insert (symbol_new (reg_names_o32
[i
].name
, reg_section
,
2464 reg_names_o32
[i
].num
, /* & RNUM_MASK, */
2465 &zero_address_frag
));
2467 mips_no_prev_insn ();
2470 mips_cprmask
[0] = 0;
2471 mips_cprmask
[1] = 0;
2472 mips_cprmask
[2] = 0;
2473 mips_cprmask
[3] = 0;
2475 /* set the default alignment for the text section (2**2) */
2476 record_alignment (text_section
, 2);
2478 bfd_set_gp_size (stdoutput
, g_switch_value
);
2483 /* On a native system other than VxWorks, sections must be aligned
2484 to 16 byte boundaries. When configured for an embedded ELF
2485 target, we don't bother. */
2486 if (strncmp (TARGET_OS
, "elf", 3) != 0
2487 && strncmp (TARGET_OS
, "vxworks", 7) != 0)
2489 (void) bfd_set_section_alignment (stdoutput
, text_section
, 4);
2490 (void) bfd_set_section_alignment (stdoutput
, data_section
, 4);
2491 (void) bfd_set_section_alignment (stdoutput
, bss_section
, 4);
2494 /* Create a .reginfo section for register masks and a .mdebug
2495 section for debugging information. */
2503 subseg
= now_subseg
;
2505 /* The ABI says this section should be loaded so that the
2506 running program can access it. However, we don't load it
2507 if we are configured for an embedded target */
2508 flags
= SEC_READONLY
| SEC_DATA
;
2509 if (strncmp (TARGET_OS
, "elf", 3) != 0)
2510 flags
|= SEC_ALLOC
| SEC_LOAD
;
2512 if (mips_abi
!= N64_ABI
)
2514 sec
= subseg_new (".reginfo", (subsegT
) 0);
2516 bfd_set_section_flags (stdoutput
, sec
, flags
);
2517 bfd_set_section_alignment (stdoutput
, sec
, HAVE_NEWABI
? 3 : 2);
2519 mips_regmask_frag
= frag_more (sizeof (Elf32_External_RegInfo
));
2523 /* The 64-bit ABI uses a .MIPS.options section rather than
2524 .reginfo section. */
2525 sec
= subseg_new (".MIPS.options", (subsegT
) 0);
2526 bfd_set_section_flags (stdoutput
, sec
, flags
);
2527 bfd_set_section_alignment (stdoutput
, sec
, 3);
2529 /* Set up the option header. */
2531 Elf_Internal_Options opthdr
;
2534 opthdr
.kind
= ODK_REGINFO
;
2535 opthdr
.size
= (sizeof (Elf_External_Options
)
2536 + sizeof (Elf64_External_RegInfo
));
2539 f
= frag_more (sizeof (Elf_External_Options
));
2540 bfd_mips_elf_swap_options_out (stdoutput
, &opthdr
,
2541 (Elf_External_Options
*) f
);
2543 mips_regmask_frag
= frag_more (sizeof (Elf64_External_RegInfo
));
2547 if (ECOFF_DEBUGGING
)
2549 sec
= subseg_new (".mdebug", (subsegT
) 0);
2550 (void) bfd_set_section_flags (stdoutput
, sec
,
2551 SEC_HAS_CONTENTS
| SEC_READONLY
);
2552 (void) bfd_set_section_alignment (stdoutput
, sec
, 2);
2554 else if (mips_flag_pdr
)
2556 pdr_seg
= subseg_new (".pdr", (subsegT
) 0);
2557 (void) bfd_set_section_flags (stdoutput
, pdr_seg
,
2558 SEC_READONLY
| SEC_RELOC
2560 (void) bfd_set_section_alignment (stdoutput
, pdr_seg
, 2);
2563 subseg_set (seg
, subseg
);
2566 #endif /* OBJ_ELF */
2568 if (! ECOFF_DEBUGGING
)
2571 if (mips_fix_vr4120
)
2572 init_vr4120_conflicts ();
2578 mips_emit_delays ();
2579 if (! ECOFF_DEBUGGING
)
2584 md_assemble (char *str
)
2586 struct mips_cl_insn insn
;
2587 bfd_reloc_code_real_type unused_reloc
[3]
2588 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
2590 imm_expr
.X_op
= O_absent
;
2591 imm2_expr
.X_op
= O_absent
;
2592 offset_expr
.X_op
= O_absent
;
2593 imm_reloc
[0] = BFD_RELOC_UNUSED
;
2594 imm_reloc
[1] = BFD_RELOC_UNUSED
;
2595 imm_reloc
[2] = BFD_RELOC_UNUSED
;
2596 offset_reloc
[0] = BFD_RELOC_UNUSED
;
2597 offset_reloc
[1] = BFD_RELOC_UNUSED
;
2598 offset_reloc
[2] = BFD_RELOC_UNUSED
;
2600 mips_mark_labels ();
2601 mips_assembling_insn
= TRUE
;
2603 if (mips_opts
.mips16
)
2604 mips16_ip (str
, &insn
);
2607 mips_ip (str
, &insn
);
2608 DBG ((_("returned from mips_ip(%s) insn_opcode = 0x%x\n"),
2609 str
, insn
.insn_opcode
));
2613 as_bad ("%s `%s'", insn_error
, str
);
2614 else if (insn
.insn_mo
->pinfo
== INSN_MACRO
)
2617 if (mips_opts
.mips16
)
2618 mips16_macro (&insn
);
2625 if (imm_expr
.X_op
!= O_absent
)
2626 append_insn (&insn
, &imm_expr
, imm_reloc
, FALSE
);
2627 else if (offset_expr
.X_op
!= O_absent
)
2628 append_insn (&insn
, &offset_expr
, offset_reloc
, FALSE
);
2630 append_insn (&insn
, NULL
, unused_reloc
, FALSE
);
2633 mips_assembling_insn
= FALSE
;
2636 /* Convenience functions for abstracting away the differences between
2637 MIPS16 and non-MIPS16 relocations. */
2639 static inline bfd_boolean
2640 mips16_reloc_p (bfd_reloc_code_real_type reloc
)
2644 case BFD_RELOC_MIPS16_JMP
:
2645 case BFD_RELOC_MIPS16_GPREL
:
2646 case BFD_RELOC_MIPS16_GOT16
:
2647 case BFD_RELOC_MIPS16_CALL16
:
2648 case BFD_RELOC_MIPS16_HI16_S
:
2649 case BFD_RELOC_MIPS16_HI16
:
2650 case BFD_RELOC_MIPS16_LO16
:
2658 static inline bfd_boolean
2659 micromips_reloc_p (bfd_reloc_code_real_type reloc
)
2663 case BFD_RELOC_MICROMIPS_7_PCREL_S1
:
2664 case BFD_RELOC_MICROMIPS_10_PCREL_S1
:
2665 case BFD_RELOC_MICROMIPS_16_PCREL_S1
:
2666 case BFD_RELOC_MICROMIPS_GPREL16
:
2667 case BFD_RELOC_MICROMIPS_JMP
:
2668 case BFD_RELOC_MICROMIPS_HI16
:
2669 case BFD_RELOC_MICROMIPS_HI16_S
:
2670 case BFD_RELOC_MICROMIPS_LO16
:
2671 case BFD_RELOC_MICROMIPS_LITERAL
:
2672 case BFD_RELOC_MICROMIPS_GOT16
:
2673 case BFD_RELOC_MICROMIPS_CALL16
:
2674 case BFD_RELOC_MICROMIPS_GOT_HI16
:
2675 case BFD_RELOC_MICROMIPS_GOT_LO16
:
2676 case BFD_RELOC_MICROMIPS_CALL_HI16
:
2677 case BFD_RELOC_MICROMIPS_CALL_LO16
:
2678 case BFD_RELOC_MICROMIPS_SUB
:
2679 case BFD_RELOC_MICROMIPS_GOT_PAGE
:
2680 case BFD_RELOC_MICROMIPS_GOT_OFST
:
2681 case BFD_RELOC_MICROMIPS_GOT_DISP
:
2682 case BFD_RELOC_MICROMIPS_HIGHEST
:
2683 case BFD_RELOC_MICROMIPS_HIGHER
:
2684 case BFD_RELOC_MICROMIPS_SCN_DISP
:
2685 case BFD_RELOC_MICROMIPS_JALR
:
2693 static inline bfd_boolean
2694 jmp_reloc_p (bfd_reloc_code_real_type reloc
)
2696 return reloc
== BFD_RELOC_MIPS_JMP
|| reloc
== BFD_RELOC_MICROMIPS_JMP
;
2699 static inline bfd_boolean
2700 got16_reloc_p (bfd_reloc_code_real_type reloc
)
2702 return (reloc
== BFD_RELOC_MIPS_GOT16
|| reloc
== BFD_RELOC_MIPS16_GOT16
2703 || reloc
== BFD_RELOC_MICROMIPS_GOT16
);
2706 static inline bfd_boolean
2707 hi16_reloc_p (bfd_reloc_code_real_type reloc
)
2709 return (reloc
== BFD_RELOC_HI16_S
|| reloc
== BFD_RELOC_MIPS16_HI16_S
2710 || reloc
== BFD_RELOC_MICROMIPS_HI16_S
);
2713 static inline bfd_boolean
2714 lo16_reloc_p (bfd_reloc_code_real_type reloc
)
2716 return (reloc
== BFD_RELOC_LO16
|| reloc
== BFD_RELOC_MIPS16_LO16
2717 || reloc
== BFD_RELOC_MICROMIPS_LO16
);
2720 static inline bfd_boolean
2721 jalr_reloc_p (bfd_reloc_code_real_type reloc
)
2723 return reloc
== BFD_RELOC_MIPS_JALR
|| reloc
== BFD_RELOC_MICROMIPS_JALR
;
2726 /* Return true if the given relocation might need a matching %lo().
2727 This is only "might" because SVR4 R_MIPS_GOT16 relocations only
2728 need a matching %lo() when applied to local symbols. */
2730 static inline bfd_boolean
2731 reloc_needs_lo_p (bfd_reloc_code_real_type reloc
)
2733 return (HAVE_IN_PLACE_ADDENDS
2734 && (hi16_reloc_p (reloc
)
2735 /* VxWorks R_MIPS_GOT16 relocs never need a matching %lo();
2736 all GOT16 relocations evaluate to "G". */
2737 || (got16_reloc_p (reloc
) && mips_pic
!= VXWORKS_PIC
)));
2740 /* Return the type of %lo() reloc needed by RELOC, given that
2741 reloc_needs_lo_p. */
2743 static inline bfd_reloc_code_real_type
2744 matching_lo_reloc (bfd_reloc_code_real_type reloc
)
2746 return (mips16_reloc_p (reloc
) ? BFD_RELOC_MIPS16_LO16
2747 : (micromips_reloc_p (reloc
) ? BFD_RELOC_MICROMIPS_LO16
2751 /* Return true if the given fixup is followed by a matching R_MIPS_LO16
2754 static inline bfd_boolean
2755 fixup_has_matching_lo_p (fixS
*fixp
)
2757 return (fixp
->fx_next
!= NULL
2758 && fixp
->fx_next
->fx_r_type
== matching_lo_reloc (fixp
->fx_r_type
)
2759 && fixp
->fx_addsy
== fixp
->fx_next
->fx_addsy
2760 && fixp
->fx_offset
== fixp
->fx_next
->fx_offset
);
2763 /* This function returns true if modifying a register requires a
2767 reg_needs_delay (unsigned int reg
)
2769 unsigned long prev_pinfo
;
2771 prev_pinfo
= history
[0].insn_mo
->pinfo
;
2772 if (! mips_opts
.noreorder
2773 && (((prev_pinfo
& INSN_LOAD_MEMORY_DELAY
)
2774 && ! gpr_interlocks
)
2775 || ((prev_pinfo
& INSN_LOAD_COPROC_DELAY
)
2776 && ! cop_interlocks
)))
2778 /* A load from a coprocessor or from memory. All load delays
2779 delay the use of general register rt for one instruction. */
2780 /* Itbl support may require additional care here. */
2781 know (prev_pinfo
& INSN_WRITE_GPR_T
);
2782 if (reg
== EXTRACT_OPERAND (mips_opts
.micromips
, RT
, history
[0]))
2789 /* Move all labels in LABELS to the current insertion point. TEXT_P
2790 says whether the labels refer to text or data. */
2793 mips_move_labels (struct insn_label_list
*labels
, bfd_boolean text_p
)
2795 struct insn_label_list
*l
;
2798 for (l
= labels
; l
!= NULL
; l
= l
->next
)
2800 gas_assert (S_GET_SEGMENT (l
->label
) == now_seg
);
2801 symbol_set_frag (l
->label
, frag_now
);
2802 val
= (valueT
) frag_now_fix ();
2803 /* MIPS16/microMIPS text labels are stored as odd. */
2804 if (text_p
&& HAVE_CODE_COMPRESSION
)
2806 S_SET_VALUE (l
->label
, val
);
2810 /* Move all labels in insn_labels to the current insertion point
2811 and treat them as text labels. */
2814 mips_move_text_labels (void)
2816 mips_move_labels (seg_info (now_seg
)->label_list
, TRUE
);
2820 s_is_linkonce (symbolS
*sym
, segT from_seg
)
2822 bfd_boolean linkonce
= FALSE
;
2823 segT symseg
= S_GET_SEGMENT (sym
);
2825 if (symseg
!= from_seg
&& !S_IS_LOCAL (sym
))
2827 if ((bfd_get_section_flags (stdoutput
, symseg
) & SEC_LINK_ONCE
))
2830 /* The GNU toolchain uses an extension for ELF: a section
2831 beginning with the magic string .gnu.linkonce is a
2832 linkonce section. */
2833 if (strncmp (segment_name (symseg
), ".gnu.linkonce",
2834 sizeof ".gnu.linkonce" - 1) == 0)
2841 /* Mark MIPS16 or microMIPS instruction label LABEL. This permits the
2842 linker to handle them specially, such as generating jalx instructions
2843 when needed. We also make them odd for the duration of the assembly,
2844 in order to generate the right sort of code. We will make them even
2845 in the adjust_symtab routine, while leaving them marked. This is
2846 convenient for the debugger and the disassembler. The linker knows
2847 to make them odd again. */
2850 mips_compressed_mark_label (symbolS
*label
)
2852 gas_assert (HAVE_CODE_COMPRESSION
);
2854 #if defined(OBJ_ELF) || defined(OBJ_MAYBE_ELF)
2857 if (mips_opts
.mips16
)
2858 S_SET_OTHER (label
, ELF_ST_SET_MIPS16 (S_GET_OTHER (label
)));
2860 S_SET_OTHER (label
, ELF_ST_SET_MICROMIPS (S_GET_OTHER (label
)));
2863 if ((S_GET_VALUE (label
) & 1) == 0
2864 /* Don't adjust the address if the label is global or weak, or
2865 in a link-once section, since we'll be emitting symbol reloc
2866 references to it which will be patched up by the linker, and
2867 the final value of the symbol may or may not be MIPS16/microMIPS. */
2868 && !S_IS_WEAK (label
)
2869 && !S_IS_EXTERNAL (label
)
2870 && !s_is_linkonce (label
, now_seg
))
2871 S_SET_VALUE (label
, S_GET_VALUE (label
) | 1);
2874 /* Mark preceding MIPS16 or microMIPS instruction labels. */
2877 mips_compressed_mark_labels (void)
2879 struct insn_label_list
*l
;
2881 for (l
= seg_info (now_seg
)->label_list
; l
!= NULL
; l
= l
->next
)
2882 mips_compressed_mark_label (l
->label
);
2885 /* End the current frag. Make it a variant frag and record the
2889 relax_close_frag (void)
2891 mips_macro_warning
.first_frag
= frag_now
;
2892 frag_var (rs_machine_dependent
, 0, 0,
2893 RELAX_ENCODE (mips_relax
.sizes
[0], mips_relax
.sizes
[1]),
2894 mips_relax
.symbol
, 0, (char *) mips_relax
.first_fixup
);
2896 memset (&mips_relax
.sizes
, 0, sizeof (mips_relax
.sizes
));
2897 mips_relax
.first_fixup
= 0;
2900 /* Start a new relaxation sequence whose expansion depends on SYMBOL.
2901 See the comment above RELAX_ENCODE for more details. */
2904 relax_start (symbolS
*symbol
)
2906 gas_assert (mips_relax
.sequence
== 0);
2907 mips_relax
.sequence
= 1;
2908 mips_relax
.symbol
= symbol
;
2911 /* Start generating the second version of a relaxable sequence.
2912 See the comment above RELAX_ENCODE for more details. */
2917 gas_assert (mips_relax
.sequence
== 1);
2918 mips_relax
.sequence
= 2;
2921 /* End the current relaxable sequence. */
2926 gas_assert (mips_relax
.sequence
== 2);
2927 relax_close_frag ();
2928 mips_relax
.sequence
= 0;
2931 /* Return true if IP is a delayed branch or jump. */
2933 static inline bfd_boolean
2934 delayed_branch_p (const struct mips_cl_insn
*ip
)
2936 return (ip
->insn_mo
->pinfo
& (INSN_UNCOND_BRANCH_DELAY
2937 | INSN_COND_BRANCH_DELAY
2938 | INSN_COND_BRANCH_LIKELY
)) != 0;
2941 /* Return true if IP is a compact branch or jump. */
2943 static inline bfd_boolean
2944 compact_branch_p (const struct mips_cl_insn
*ip
)
2946 if (mips_opts
.mips16
)
2947 return (ip
->insn_mo
->pinfo
& (MIPS16_INSN_UNCOND_BRANCH
2948 | MIPS16_INSN_COND_BRANCH
)) != 0;
2950 return (ip
->insn_mo
->pinfo2
& (INSN2_UNCOND_BRANCH
2951 | INSN2_COND_BRANCH
)) != 0;
2954 /* Return true if IP is an unconditional branch or jump. */
2956 static inline bfd_boolean
2957 uncond_branch_p (const struct mips_cl_insn
*ip
)
2959 return ((ip
->insn_mo
->pinfo
& INSN_UNCOND_BRANCH_DELAY
) != 0
2960 || (mips_opts
.mips16
2961 ? (ip
->insn_mo
->pinfo
& MIPS16_INSN_UNCOND_BRANCH
) != 0
2962 : (ip
->insn_mo
->pinfo2
& INSN2_UNCOND_BRANCH
) != 0));
2965 /* Return true if IP is a branch-likely instruction. */
2967 static inline bfd_boolean
2968 branch_likely_p (const struct mips_cl_insn
*ip
)
2970 return (ip
->insn_mo
->pinfo
& INSN_COND_BRANCH_LIKELY
) != 0;
2973 /* Return the type of nop that should be used to fill the delay slot
2974 of delayed branch IP. */
2976 static struct mips_cl_insn
*
2977 get_delay_slot_nop (const struct mips_cl_insn
*ip
)
2979 if (mips_opts
.micromips
2980 && (ip
->insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_32BIT
))
2981 return µmips_nop32_insn
;
2985 /* Return the mask of core registers that IP reads or writes. */
2988 gpr_mod_mask (const struct mips_cl_insn
*ip
)
2990 unsigned long pinfo2
;
2994 pinfo2
= ip
->insn_mo
->pinfo2
;
2995 if (mips_opts
.micromips
)
2997 if (pinfo2
& INSN2_MOD_GPR_MD
)
2998 mask
|= 1 << micromips_to_32_reg_d_map
[EXTRACT_OPERAND (1, MD
, *ip
)];
2999 if (pinfo2
& INSN2_MOD_GPR_MF
)
3000 mask
|= 1 << micromips_to_32_reg_f_map
[EXTRACT_OPERAND (1, MF
, *ip
)];
3001 if (pinfo2
& INSN2_MOD_SP
)
3007 /* Return the mask of core registers that IP reads. */
3010 gpr_read_mask (const struct mips_cl_insn
*ip
)
3012 unsigned long pinfo
, pinfo2
;
3015 mask
= gpr_mod_mask (ip
);
3016 pinfo
= ip
->insn_mo
->pinfo
;
3017 pinfo2
= ip
->insn_mo
->pinfo2
;
3018 if (mips_opts
.mips16
)
3020 if (pinfo
& MIPS16_INSN_READ_X
)
3021 mask
|= 1 << mips16_to_32_reg_map
[MIPS16_EXTRACT_OPERAND (RX
, *ip
)];
3022 if (pinfo
& MIPS16_INSN_READ_Y
)
3023 mask
|= 1 << mips16_to_32_reg_map
[MIPS16_EXTRACT_OPERAND (RY
, *ip
)];
3024 if (pinfo
& MIPS16_INSN_READ_T
)
3026 if (pinfo
& MIPS16_INSN_READ_SP
)
3028 if (pinfo
& MIPS16_INSN_READ_31
)
3030 if (pinfo
& MIPS16_INSN_READ_Z
)
3031 mask
|= 1 << (mips16_to_32_reg_map
3032 [MIPS16_EXTRACT_OPERAND (MOVE32Z
, *ip
)]);
3033 if (pinfo
& MIPS16_INSN_READ_GPR_X
)
3034 mask
|= 1 << MIPS16_EXTRACT_OPERAND (REGR32
, *ip
);
3038 if (pinfo2
& INSN2_READ_GPR_D
)
3039 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, RD
, *ip
);
3040 if (pinfo
& INSN_READ_GPR_T
)
3041 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, RT
, *ip
);
3042 if (pinfo
& INSN_READ_GPR_S
)
3043 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, RS
, *ip
);
3044 if (pinfo2
& INSN2_READ_GP
)
3046 if (pinfo2
& INSN2_READ_GPR_31
)
3048 if (pinfo2
& INSN2_READ_GPR_Z
)
3049 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, RZ
, *ip
);
3051 if (mips_opts
.micromips
)
3053 if (pinfo2
& INSN2_READ_GPR_MC
)
3054 mask
|= 1 << micromips_to_32_reg_c_map
[EXTRACT_OPERAND (1, MC
, *ip
)];
3055 if (pinfo2
& INSN2_READ_GPR_ME
)
3056 mask
|= 1 << micromips_to_32_reg_e_map
[EXTRACT_OPERAND (1, ME
, *ip
)];
3057 if (pinfo2
& INSN2_READ_GPR_MG
)
3058 mask
|= 1 << micromips_to_32_reg_g_map
[EXTRACT_OPERAND (1, MG
, *ip
)];
3059 if (pinfo2
& INSN2_READ_GPR_MJ
)
3060 mask
|= 1 << EXTRACT_OPERAND (1, MJ
, *ip
);
3061 if (pinfo2
& INSN2_READ_GPR_MMN
)
3063 mask
|= 1 << micromips_to_32_reg_m_map
[EXTRACT_OPERAND (1, MM
, *ip
)];
3064 mask
|= 1 << micromips_to_32_reg_n_map
[EXTRACT_OPERAND (1, MN
, *ip
)];
3066 if (pinfo2
& INSN2_READ_GPR_MP
)
3067 mask
|= 1 << EXTRACT_OPERAND (1, MP
, *ip
);
3068 if (pinfo2
& INSN2_READ_GPR_MQ
)
3069 mask
|= 1 << micromips_to_32_reg_q_map
[EXTRACT_OPERAND (1, MQ
, *ip
)];
3071 /* Don't include register 0. */
3075 /* Return the mask of core registers that IP writes. */
3078 gpr_write_mask (const struct mips_cl_insn
*ip
)
3080 unsigned long pinfo
, pinfo2
;
3083 mask
= gpr_mod_mask (ip
);
3084 pinfo
= ip
->insn_mo
->pinfo
;
3085 pinfo2
= ip
->insn_mo
->pinfo2
;
3086 if (mips_opts
.mips16
)
3088 if (pinfo
& MIPS16_INSN_WRITE_X
)
3089 mask
|= 1 << mips16_to_32_reg_map
[MIPS16_EXTRACT_OPERAND (RX
, *ip
)];
3090 if (pinfo
& MIPS16_INSN_WRITE_Y
)
3091 mask
|= 1 << mips16_to_32_reg_map
[MIPS16_EXTRACT_OPERAND (RY
, *ip
)];
3092 if (pinfo
& MIPS16_INSN_WRITE_Z
)
3093 mask
|= 1 << mips16_to_32_reg_map
[MIPS16_EXTRACT_OPERAND (RZ
, *ip
)];
3094 if (pinfo
& MIPS16_INSN_WRITE_T
)
3096 if (pinfo
& MIPS16_INSN_WRITE_SP
)
3098 if (pinfo
& MIPS16_INSN_WRITE_31
)
3100 if (pinfo
& MIPS16_INSN_WRITE_GPR_Y
)
3101 mask
|= 1 << MIPS16OP_EXTRACT_REG32R (ip
->insn_opcode
);
3105 if (pinfo
& INSN_WRITE_GPR_D
)
3106 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, RD
, *ip
);
3107 if (pinfo
& INSN_WRITE_GPR_T
)
3108 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, RT
, *ip
);
3109 if (pinfo
& INSN_WRITE_GPR_S
)
3110 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, RS
, *ip
);
3111 if (pinfo
& INSN_WRITE_GPR_31
)
3113 if (pinfo2
& INSN2_WRITE_GPR_Z
)
3114 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, RZ
, *ip
);
3116 if (mips_opts
.micromips
)
3118 if (pinfo2
& INSN2_WRITE_GPR_MB
)
3119 mask
|= 1 << micromips_to_32_reg_b_map
[EXTRACT_OPERAND (1, MB
, *ip
)];
3120 if (pinfo2
& INSN2_WRITE_GPR_MHI
)
3122 mask
|= 1 << micromips_to_32_reg_h_map
[EXTRACT_OPERAND (1, MH
, *ip
)];
3123 mask
|= 1 << micromips_to_32_reg_i_map
[EXTRACT_OPERAND (1, MI
, *ip
)];
3125 if (pinfo2
& INSN2_WRITE_GPR_MJ
)
3126 mask
|= 1 << EXTRACT_OPERAND (1, MJ
, *ip
);
3127 if (pinfo2
& INSN2_WRITE_GPR_MP
)
3128 mask
|= 1 << EXTRACT_OPERAND (1, MP
, *ip
);
3130 /* Don't include register 0. */
3134 /* Return the mask of floating-point registers that IP reads. */
3137 fpr_read_mask (const struct mips_cl_insn
*ip
)
3139 unsigned long pinfo
, pinfo2
;
3143 pinfo
= ip
->insn_mo
->pinfo
;
3144 pinfo2
= ip
->insn_mo
->pinfo2
;
3145 if (!mips_opts
.mips16
)
3147 if (pinfo2
& INSN2_READ_FPR_D
)
3148 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, FD
, *ip
);
3149 if (pinfo
& INSN_READ_FPR_S
)
3150 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, FS
, *ip
);
3151 if (pinfo
& INSN_READ_FPR_T
)
3152 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, FT
, *ip
);
3153 if (pinfo
& INSN_READ_FPR_R
)
3154 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, FR
, *ip
);
3155 if (pinfo2
& INSN2_READ_FPR_Z
)
3156 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, FZ
, *ip
);
3158 /* Conservatively treat all operands to an FP_D instruction are doubles.
3159 (This is overly pessimistic for things like cvt.d.s.) */
3160 if (HAVE_32BIT_FPRS
&& (pinfo
& FP_D
))
3165 /* Return the mask of floating-point registers that IP writes. */
3168 fpr_write_mask (const struct mips_cl_insn
*ip
)
3170 unsigned long pinfo
, pinfo2
;
3174 pinfo
= ip
->insn_mo
->pinfo
;
3175 pinfo2
= ip
->insn_mo
->pinfo2
;
3176 if (!mips_opts
.mips16
)
3178 if (pinfo
& INSN_WRITE_FPR_D
)
3179 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, FD
, *ip
);
3180 if (pinfo
& INSN_WRITE_FPR_S
)
3181 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, FS
, *ip
);
3182 if (pinfo
& INSN_WRITE_FPR_T
)
3183 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, FT
, *ip
);
3184 if (pinfo2
& INSN2_WRITE_FPR_Z
)
3185 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, FZ
, *ip
);
3187 /* Conservatively treat all operands to an FP_D instruction are doubles.
3188 (This is overly pessimistic for things like cvt.s.d.) */
3189 if (HAVE_32BIT_FPRS
&& (pinfo
& FP_D
))
3194 /* Classify an instruction according to the FIX_VR4120_* enumeration.
3195 Return NUM_FIX_VR4120_CLASSES if the instruction isn't affected
3196 by VR4120 errata. */
3199 classify_vr4120_insn (const char *name
)
3201 if (strncmp (name
, "macc", 4) == 0)
3202 return FIX_VR4120_MACC
;
3203 if (strncmp (name
, "dmacc", 5) == 0)
3204 return FIX_VR4120_DMACC
;
3205 if (strncmp (name
, "mult", 4) == 0)
3206 return FIX_VR4120_MULT
;
3207 if (strncmp (name
, "dmult", 5) == 0)
3208 return FIX_VR4120_DMULT
;
3209 if (strstr (name
, "div"))
3210 return FIX_VR4120_DIV
;
3211 if (strcmp (name
, "mtlo") == 0 || strcmp (name
, "mthi") == 0)
3212 return FIX_VR4120_MTHILO
;
3213 return NUM_FIX_VR4120_CLASSES
;
3216 #define INSN_ERET 0x42000018
3217 #define INSN_DERET 0x4200001f
3219 /* Return the number of instructions that must separate INSN1 and INSN2,
3220 where INSN1 is the earlier instruction. Return the worst-case value
3221 for any INSN2 if INSN2 is null. */
3224 insns_between (const struct mips_cl_insn
*insn1
,
3225 const struct mips_cl_insn
*insn2
)
3227 unsigned long pinfo1
, pinfo2
;
3230 /* This function needs to know which pinfo flags are set for INSN2
3231 and which registers INSN2 uses. The former is stored in PINFO2 and
3232 the latter is tested via INSN2_USES_GPR. If INSN2 is null, PINFO2
3233 will have every flag set and INSN2_USES_GPR will always return true. */
3234 pinfo1
= insn1
->insn_mo
->pinfo
;
3235 pinfo2
= insn2
? insn2
->insn_mo
->pinfo
: ~0U;
3237 #define INSN2_USES_GPR(REG) \
3238 (insn2 == NULL || (gpr_read_mask (insn2) & (1U << (REG))) != 0)
3240 /* For most targets, write-after-read dependencies on the HI and LO
3241 registers must be separated by at least two instructions. */
3242 if (!hilo_interlocks
)
3244 if ((pinfo1
& INSN_READ_LO
) && (pinfo2
& INSN_WRITE_LO
))
3246 if ((pinfo1
& INSN_READ_HI
) && (pinfo2
& INSN_WRITE_HI
))
3250 /* If we're working around r7000 errata, there must be two instructions
3251 between an mfhi or mflo and any instruction that uses the result. */
3252 if (mips_7000_hilo_fix
3253 && !mips_opts
.micromips
3254 && MF_HILO_INSN (pinfo1
)
3255 && INSN2_USES_GPR (EXTRACT_OPERAND (0, RD
, *insn1
)))
3258 /* If we're working around 24K errata, one instruction is required
3259 if an ERET or DERET is followed by a branch instruction. */
3260 if (mips_fix_24k
&& !mips_opts
.micromips
)
3262 if (insn1
->insn_opcode
== INSN_ERET
3263 || insn1
->insn_opcode
== INSN_DERET
)
3266 || insn2
->insn_opcode
== INSN_ERET
3267 || insn2
->insn_opcode
== INSN_DERET
3268 || delayed_branch_p (insn2
))
3273 /* If working around VR4120 errata, check for combinations that need
3274 a single intervening instruction. */
3275 if (mips_fix_vr4120
&& !mips_opts
.micromips
)
3277 unsigned int class1
, class2
;
3279 class1
= classify_vr4120_insn (insn1
->insn_mo
->name
);
3280 if (class1
!= NUM_FIX_VR4120_CLASSES
&& vr4120_conflicts
[class1
] != 0)
3284 class2
= classify_vr4120_insn (insn2
->insn_mo
->name
);
3285 if (vr4120_conflicts
[class1
] & (1 << class2
))
3290 if (!HAVE_CODE_COMPRESSION
)
3292 /* Check for GPR or coprocessor load delays. All such delays
3293 are on the RT register. */
3294 /* Itbl support may require additional care here. */
3295 if ((!gpr_interlocks
&& (pinfo1
& INSN_LOAD_MEMORY_DELAY
))
3296 || (!cop_interlocks
&& (pinfo1
& INSN_LOAD_COPROC_DELAY
)))
3298 know (pinfo1
& INSN_WRITE_GPR_T
);
3299 if (INSN2_USES_GPR (EXTRACT_OPERAND (0, RT
, *insn1
)))
3303 /* Check for generic coprocessor hazards.
3305 This case is not handled very well. There is no special
3306 knowledge of CP0 handling, and the coprocessors other than
3307 the floating point unit are not distinguished at all. */
3308 /* Itbl support may require additional care here. FIXME!
3309 Need to modify this to include knowledge about
3310 user specified delays! */
3311 else if ((!cop_interlocks
&& (pinfo1
& INSN_COPROC_MOVE_DELAY
))
3312 || (!cop_mem_interlocks
&& (pinfo1
& INSN_COPROC_MEMORY_DELAY
)))
3314 /* Handle cases where INSN1 writes to a known general coprocessor
3315 register. There must be a one instruction delay before INSN2
3316 if INSN2 reads that register, otherwise no delay is needed. */
3317 mask
= fpr_write_mask (insn1
);
3320 if (!insn2
|| (mask
& fpr_read_mask (insn2
)) != 0)
3325 /* Read-after-write dependencies on the control registers
3326 require a two-instruction gap. */
3327 if ((pinfo1
& INSN_WRITE_COND_CODE
)
3328 && (pinfo2
& INSN_READ_COND_CODE
))
3331 /* We don't know exactly what INSN1 does. If INSN2 is
3332 also a coprocessor instruction, assume there must be
3333 a one instruction gap. */
3334 if (pinfo2
& INSN_COP
)
3339 /* Check for read-after-write dependencies on the coprocessor
3340 control registers in cases where INSN1 does not need a general
3341 coprocessor delay. This means that INSN1 is a floating point
3342 comparison instruction. */
3343 /* Itbl support may require additional care here. */
3344 else if (!cop_interlocks
3345 && (pinfo1
& INSN_WRITE_COND_CODE
)
3346 && (pinfo2
& INSN_READ_COND_CODE
))
3350 #undef INSN2_USES_GPR
3355 /* Return the number of nops that would be needed to work around the
3356 VR4130 mflo/mfhi errata if instruction INSN immediately followed
3357 the MAX_VR4130_NOPS instructions described by HIST. Ignore hazards
3358 that are contained within the first IGNORE instructions of HIST. */
3361 nops_for_vr4130 (int ignore
, const struct mips_cl_insn
*hist
,
3362 const struct mips_cl_insn
*insn
)
3367 /* Check if the instruction writes to HI or LO. MTHI and MTLO
3368 are not affected by the errata. */
3370 && ((insn
->insn_mo
->pinfo
& (INSN_WRITE_HI
| INSN_WRITE_LO
)) == 0
3371 || strcmp (insn
->insn_mo
->name
, "mtlo") == 0
3372 || strcmp (insn
->insn_mo
->name
, "mthi") == 0))
3375 /* Search for the first MFLO or MFHI. */
3376 for (i
= 0; i
< MAX_VR4130_NOPS
; i
++)
3377 if (MF_HILO_INSN (hist
[i
].insn_mo
->pinfo
))
3379 /* Extract the destination register. */
3380 mask
= gpr_write_mask (&hist
[i
]);
3382 /* No nops are needed if INSN reads that register. */
3383 if (insn
!= NULL
&& (gpr_read_mask (insn
) & mask
) != 0)
3386 /* ...or if any of the intervening instructions do. */
3387 for (j
= 0; j
< i
; j
++)
3388 if (gpr_read_mask (&hist
[j
]) & mask
)
3392 return MAX_VR4130_NOPS
- i
;
3397 #define BASE_REG_EQ(INSN1, INSN2) \
3398 ((((INSN1) >> OP_SH_RS) & OP_MASK_RS) \
3399 == (((INSN2) >> OP_SH_RS) & OP_MASK_RS))
3401 /* Return the minimum alignment for this store instruction. */
3404 fix_24k_align_to (const struct mips_opcode
*mo
)
3406 if (strcmp (mo
->name
, "sh") == 0)
3409 if (strcmp (mo
->name
, "swc1") == 0
3410 || strcmp (mo
->name
, "swc2") == 0
3411 || strcmp (mo
->name
, "sw") == 0
3412 || strcmp (mo
->name
, "sc") == 0
3413 || strcmp (mo
->name
, "s.s") == 0)
3416 if (strcmp (mo
->name
, "sdc1") == 0
3417 || strcmp (mo
->name
, "sdc2") == 0
3418 || strcmp (mo
->name
, "s.d") == 0)
3425 struct fix_24k_store_info
3427 /* Immediate offset, if any, for this store instruction. */
3429 /* Alignment required by this store instruction. */
3431 /* True for register offsets. */
3432 int register_offset
;
3435 /* Comparison function used by qsort. */
3438 fix_24k_sort (const void *a
, const void *b
)
3440 const struct fix_24k_store_info
*pos1
= a
;
3441 const struct fix_24k_store_info
*pos2
= b
;
3443 return (pos1
->off
- pos2
->off
);
3446 /* INSN is a store instruction. Try to record the store information
3447 in STINFO. Return false if the information isn't known. */
3450 fix_24k_record_store_info (struct fix_24k_store_info
*stinfo
,
3451 const struct mips_cl_insn
*insn
)
3453 /* The instruction must have a known offset. */
3454 if (!insn
->complete_p
|| !strstr (insn
->insn_mo
->args
, "o("))
3457 stinfo
->off
= (insn
->insn_opcode
>> OP_SH_IMMEDIATE
) & OP_MASK_IMMEDIATE
;
3458 stinfo
->align_to
= fix_24k_align_to (insn
->insn_mo
);
3462 /* Return the number of nops that would be needed to work around the 24k
3463 "lost data on stores during refill" errata if instruction INSN
3464 immediately followed the 2 instructions described by HIST.
3465 Ignore hazards that are contained within the first IGNORE
3466 instructions of HIST.
3468 Problem: The FSB (fetch store buffer) acts as an intermediate buffer
3469 for the data cache refills and store data. The following describes
3470 the scenario where the store data could be lost.
3472 * A data cache miss, due to either a load or a store, causing fill
3473 data to be supplied by the memory subsystem
3474 * The first three doublewords of fill data are returned and written
3476 * A sequence of four stores occurs in consecutive cycles around the
3477 final doubleword of the fill:
3481 * Zero, One or more instructions
3484 The four stores A-D must be to different doublewords of the line that
3485 is being filled. The fourth instruction in the sequence above permits
3486 the fill of the final doubleword to be transferred from the FSB into
3487 the cache. In the sequence above, the stores may be either integer
3488 (sb, sh, sw, swr, swl, sc) or coprocessor (swc1/swc2, sdc1/sdc2,
3489 swxc1, sdxc1, suxc1) stores, as long as the four stores are to
3490 different doublewords on the line. If the floating point unit is
3491 running in 1:2 mode, it is not possible to create the sequence above
3492 using only floating point store instructions.
3494 In this case, the cache line being filled is incorrectly marked
3495 invalid, thereby losing the data from any store to the line that
3496 occurs between the original miss and the completion of the five
3497 cycle sequence shown above.
3499 The workarounds are:
3501 * Run the data cache in write-through mode.
3502 * Insert a non-store instruction between
3503 Store A and Store B or Store B and Store C. */
3506 nops_for_24k (int ignore
, const struct mips_cl_insn
*hist
,
3507 const struct mips_cl_insn
*insn
)
3509 struct fix_24k_store_info pos
[3];
3510 int align
, i
, base_offset
;
3515 /* If the previous instruction wasn't a store, there's nothing to
3517 if ((hist
[0].insn_mo
->pinfo
& INSN_STORE_MEMORY
) == 0)
3520 /* If the instructions after the previous one are unknown, we have
3521 to assume the worst. */
3525 /* Check whether we are dealing with three consecutive stores. */
3526 if ((insn
->insn_mo
->pinfo
& INSN_STORE_MEMORY
) == 0
3527 || (hist
[1].insn_mo
->pinfo
& INSN_STORE_MEMORY
) == 0)
3530 /* If we don't know the relationship between the store addresses,
3531 assume the worst. */
3532 if (!BASE_REG_EQ (insn
->insn_opcode
, hist
[0].insn_opcode
)
3533 || !BASE_REG_EQ (insn
->insn_opcode
, hist
[1].insn_opcode
))
3536 if (!fix_24k_record_store_info (&pos
[0], insn
)
3537 || !fix_24k_record_store_info (&pos
[1], &hist
[0])
3538 || !fix_24k_record_store_info (&pos
[2], &hist
[1]))
3541 qsort (&pos
, 3, sizeof (struct fix_24k_store_info
), fix_24k_sort
);
3543 /* Pick a value of ALIGN and X such that all offsets are adjusted by
3544 X bytes and such that the base register + X is known to be aligned
3547 if (((insn
->insn_opcode
>> OP_SH_RS
) & OP_MASK_RS
) == SP
)
3551 align
= pos
[0].align_to
;
3552 base_offset
= pos
[0].off
;
3553 for (i
= 1; i
< 3; i
++)
3554 if (align
< pos
[i
].align_to
)
3556 align
= pos
[i
].align_to
;
3557 base_offset
= pos
[i
].off
;
3559 for (i
= 0; i
< 3; i
++)
3560 pos
[i
].off
-= base_offset
;
3563 pos
[0].off
&= ~align
+ 1;
3564 pos
[1].off
&= ~align
+ 1;
3565 pos
[2].off
&= ~align
+ 1;
3567 /* If any two stores write to the same chunk, they also write to the
3568 same doubleword. The offsets are still sorted at this point. */
3569 if (pos
[0].off
== pos
[1].off
|| pos
[1].off
== pos
[2].off
)
3572 /* A range of at least 9 bytes is needed for the stores to be in
3573 non-overlapping doublewords. */
3574 if (pos
[2].off
- pos
[0].off
<= 8)
3577 if (pos
[2].off
- pos
[1].off
>= 24
3578 || pos
[1].off
- pos
[0].off
>= 24
3579 || pos
[2].off
- pos
[0].off
>= 32)
3585 /* Return the number of nops that would be needed if instruction INSN
3586 immediately followed the MAX_NOPS instructions given by HIST,
3587 where HIST[0] is the most recent instruction. Ignore hazards
3588 between INSN and the first IGNORE instructions in HIST.
3590 If INSN is null, return the worse-case number of nops for any
3594 nops_for_insn (int ignore
, const struct mips_cl_insn
*hist
,
3595 const struct mips_cl_insn
*insn
)
3597 int i
, nops
, tmp_nops
;
3600 for (i
= ignore
; i
< MAX_DELAY_NOPS
; i
++)
3602 tmp_nops
= insns_between (hist
+ i
, insn
) - i
;
3603 if (tmp_nops
> nops
)
3607 if (mips_fix_vr4130
&& !mips_opts
.micromips
)
3609 tmp_nops
= nops_for_vr4130 (ignore
, hist
, insn
);
3610 if (tmp_nops
> nops
)
3614 if (mips_fix_24k
&& !mips_opts
.micromips
)
3616 tmp_nops
= nops_for_24k (ignore
, hist
, insn
);
3617 if (tmp_nops
> nops
)
3624 /* The variable arguments provide NUM_INSNS extra instructions that
3625 might be added to HIST. Return the largest number of nops that
3626 would be needed after the extended sequence, ignoring hazards
3627 in the first IGNORE instructions. */
3630 nops_for_sequence (int num_insns
, int ignore
,
3631 const struct mips_cl_insn
*hist
, ...)
3634 struct mips_cl_insn buffer
[MAX_NOPS
];
3635 struct mips_cl_insn
*cursor
;
3638 va_start (args
, hist
);
3639 cursor
= buffer
+ num_insns
;
3640 memcpy (cursor
, hist
, (MAX_NOPS
- num_insns
) * sizeof (*cursor
));
3641 while (cursor
> buffer
)
3642 *--cursor
= *va_arg (args
, const struct mips_cl_insn
*);
3644 nops
= nops_for_insn (ignore
, buffer
, NULL
);
3649 /* Like nops_for_insn, but if INSN is a branch, take into account the
3650 worst-case delay for the branch target. */
3653 nops_for_insn_or_target (int ignore
, const struct mips_cl_insn
*hist
,
3654 const struct mips_cl_insn
*insn
)
3658 nops
= nops_for_insn (ignore
, hist
, insn
);
3659 if (delayed_branch_p (insn
))
3661 tmp_nops
= nops_for_sequence (2, ignore
? ignore
+ 2 : 0,
3662 hist
, insn
, get_delay_slot_nop (insn
));
3663 if (tmp_nops
> nops
)
3666 else if (compact_branch_p (insn
))
3668 tmp_nops
= nops_for_sequence (1, ignore
? ignore
+ 1 : 0, hist
, insn
);
3669 if (tmp_nops
> nops
)
3675 /* Fix NOP issue: Replace nops by "or at,at,zero". */
3678 fix_loongson2f_nop (struct mips_cl_insn
* ip
)
3680 gas_assert (!HAVE_CODE_COMPRESSION
);
3681 if (strcmp (ip
->insn_mo
->name
, "nop") == 0)
3682 ip
->insn_opcode
= LOONGSON2F_NOP_INSN
;
3685 /* Fix Jump Issue: Eliminate instruction fetch from outside 256M region
3686 jr target pc &= 'hffff_ffff_cfff_ffff. */
3689 fix_loongson2f_jump (struct mips_cl_insn
* ip
)
3691 gas_assert (!HAVE_CODE_COMPRESSION
);
3692 if (strcmp (ip
->insn_mo
->name
, "j") == 0
3693 || strcmp (ip
->insn_mo
->name
, "jr") == 0
3694 || strcmp (ip
->insn_mo
->name
, "jalr") == 0)
3702 sreg
= EXTRACT_OPERAND (0, RS
, *ip
);
3703 if (sreg
== ZERO
|| sreg
== KT0
|| sreg
== KT1
|| sreg
== ATREG
)
3706 ep
.X_op
= O_constant
;
3707 ep
.X_add_number
= 0xcfff0000;
3708 macro_build (&ep
, "lui", "t,u", ATREG
, BFD_RELOC_HI16
);
3709 ep
.X_add_number
= 0xffff;
3710 macro_build (&ep
, "ori", "t,r,i", ATREG
, ATREG
, BFD_RELOC_LO16
);
3711 macro_build (NULL
, "and", "d,v,t", sreg
, sreg
, ATREG
);
3716 fix_loongson2f (struct mips_cl_insn
* ip
)
3718 if (mips_fix_loongson2f_nop
)
3719 fix_loongson2f_nop (ip
);
3721 if (mips_fix_loongson2f_jump
)
3722 fix_loongson2f_jump (ip
);
3725 /* IP is a branch that has a delay slot, and we need to fill it
3726 automatically. Return true if we can do that by swapping IP
3727 with the previous instruction. */
3730 can_swap_branch_p (struct mips_cl_insn
*ip
)
3732 unsigned long pinfo
, pinfo2
, prev_pinfo
, prev_pinfo2
;
3733 unsigned int gpr_read
, gpr_write
, prev_gpr_read
, prev_gpr_write
;
3735 /* -O2 and above is required for this optimization. */
3736 if (mips_optimize
< 2)
3739 /* If we have seen .set volatile or .set nomove, don't optimize. */
3740 if (mips_opts
.nomove
)
3743 /* We can't swap if the previous instruction's position is fixed. */
3744 if (history
[0].fixed_p
)
3747 /* If the previous previous insn was in a .set noreorder, we can't
3748 swap. Actually, the MIPS assembler will swap in this situation.
3749 However, gcc configured -with-gnu-as will generate code like
3757 in which we can not swap the bne and INSN. If gcc is not configured
3758 -with-gnu-as, it does not output the .set pseudo-ops. */
3759 if (history
[1].noreorder_p
)
3762 /* If the previous instruction had a fixup in mips16 mode, we can not swap.
3763 This means that the previous instruction was a 4-byte one anyhow. */
3764 if (mips_opts
.mips16
&& history
[0].fixp
[0])
3767 /* If the branch is itself the target of a branch, we can not swap.
3768 We cheat on this; all we check for is whether there is a label on
3769 this instruction. If there are any branches to anything other than
3770 a label, users must use .set noreorder. */
3771 if (seg_info (now_seg
)->label_list
)
3774 /* If the previous instruction is in a variant frag other than this
3775 branch's one, we cannot do the swap. This does not apply to
3776 MIPS16 code, which uses variant frags for different purposes. */
3777 if (!mips_opts
.mips16
3779 && history
[0].frag
->fr_type
== rs_machine_dependent
)
3782 /* We do not swap with instructions that cannot architecturally
3783 be placed in a branch delay slot, such as SYNC or ERET. We
3784 also refrain from swapping with a trap instruction, since it
3785 complicates trap handlers to have the trap instruction be in
3787 prev_pinfo
= history
[0].insn_mo
->pinfo
;
3788 if (prev_pinfo
& INSN_NO_DELAY_SLOT
)
3791 /* Check for conflicts between the branch and the instructions
3792 before the candidate delay slot. */
3793 if (nops_for_insn (0, history
+ 1, ip
) > 0)
3796 /* Check for conflicts between the swapped sequence and the
3797 target of the branch. */
3798 if (nops_for_sequence (2, 0, history
+ 1, ip
, history
) > 0)
3801 /* If the branch reads a register that the previous
3802 instruction sets, we can not swap. */
3803 gpr_read
= gpr_read_mask (ip
);
3804 prev_gpr_write
= gpr_write_mask (&history
[0]);
3805 if (gpr_read
& prev_gpr_write
)
3808 /* If the branch writes a register that the previous
3809 instruction sets, we can not swap. */
3810 gpr_write
= gpr_write_mask (ip
);
3811 if (gpr_write
& prev_gpr_write
)
3814 /* If the branch writes a register that the previous
3815 instruction reads, we can not swap. */
3816 prev_gpr_read
= gpr_read_mask (&history
[0]);
3817 if (gpr_write
& prev_gpr_read
)
3820 /* If one instruction sets a condition code and the
3821 other one uses a condition code, we can not swap. */
3822 pinfo
= ip
->insn_mo
->pinfo
;
3823 if ((pinfo
& INSN_READ_COND_CODE
)
3824 && (prev_pinfo
& INSN_WRITE_COND_CODE
))
3826 if ((pinfo
& INSN_WRITE_COND_CODE
)
3827 && (prev_pinfo
& INSN_READ_COND_CODE
))
3830 /* If the previous instruction uses the PC, we can not swap. */
3831 prev_pinfo2
= history
[0].insn_mo
->pinfo2
;
3832 if (mips_opts
.mips16
&& (prev_pinfo
& MIPS16_INSN_READ_PC
))
3834 if (mips_opts
.micromips
&& (prev_pinfo2
& INSN2_READ_PC
))
3837 /* If the previous instruction has an incorrect size for a fixed
3838 branch delay slot in microMIPS mode, we cannot swap. */
3839 pinfo2
= ip
->insn_mo
->pinfo2
;
3840 if (mips_opts
.micromips
3841 && (pinfo2
& INSN2_BRANCH_DELAY_16BIT
)
3842 && insn_length (history
) != 2)
3844 if (mips_opts
.micromips
3845 && (pinfo2
& INSN2_BRANCH_DELAY_32BIT
)
3846 && insn_length (history
) != 4)
3852 /* Decide how we should add IP to the instruction stream. */
3854 static enum append_method
3855 get_append_method (struct mips_cl_insn
*ip
)
3857 unsigned long pinfo
;
3859 /* The relaxed version of a macro sequence must be inherently
3861 if (mips_relax
.sequence
== 2)
3864 /* We must not dabble with instructions in a ".set norerorder" block. */
3865 if (mips_opts
.noreorder
)
3868 /* Otherwise, it's our responsibility to fill branch delay slots. */
3869 if (delayed_branch_p (ip
))
3871 if (!branch_likely_p (ip
) && can_swap_branch_p (ip
))
3874 pinfo
= ip
->insn_mo
->pinfo
;
3875 if (mips_opts
.mips16
3876 && ISA_SUPPORTS_MIPS16E
3877 && (pinfo
& (MIPS16_INSN_READ_X
| MIPS16_INSN_READ_31
)))
3878 return APPEND_ADD_COMPACT
;
3880 return APPEND_ADD_WITH_NOP
;
3886 /* IP is a MIPS16 instruction whose opcode we have just changed.
3887 Point IP->insn_mo to the new opcode's definition. */
3890 find_altered_mips16_opcode (struct mips_cl_insn
*ip
)
3892 const struct mips_opcode
*mo
, *end
;
3894 end
= &mips16_opcodes
[bfd_mips16_num_opcodes
];
3895 for (mo
= ip
->insn_mo
; mo
< end
; mo
++)
3896 if ((ip
->insn_opcode
& mo
->mask
) == mo
->match
)
3904 /* For microMIPS macros, we need to generate a local number label
3905 as the target of branches. */
3906 #define MICROMIPS_LABEL_CHAR '\037'
3907 static unsigned long micromips_target_label
;
3908 static char micromips_target_name
[32];
3911 micromips_label_name (void)
3913 char *p
= micromips_target_name
;
3914 char symbol_name_temporary
[24];
3922 l
= micromips_target_label
;
3923 #ifdef LOCAL_LABEL_PREFIX
3924 *p
++ = LOCAL_LABEL_PREFIX
;
3927 *p
++ = MICROMIPS_LABEL_CHAR
;
3930 symbol_name_temporary
[i
++] = l
% 10 + '0';
3935 *p
++ = symbol_name_temporary
[--i
];
3938 return micromips_target_name
;
3942 micromips_label_expr (expressionS
*label_expr
)
3944 label_expr
->X_op
= O_symbol
;
3945 label_expr
->X_add_symbol
= symbol_find_or_make (micromips_label_name ());
3946 label_expr
->X_add_number
= 0;
3950 micromips_label_inc (void)
3952 micromips_target_label
++;
3953 *micromips_target_name
= '\0';
3957 micromips_add_label (void)
3961 s
= colon (micromips_label_name ());
3962 micromips_label_inc ();
3963 #if defined(OBJ_ELF) || defined(OBJ_MAYBE_ELF)
3965 S_SET_OTHER (s
, ELF_ST_SET_MICROMIPS (S_GET_OTHER (s
)));
3971 /* If assembling microMIPS code, then return the microMIPS reloc
3972 corresponding to the requested one if any. Otherwise return
3973 the reloc unchanged. */
3975 static bfd_reloc_code_real_type
3976 micromips_map_reloc (bfd_reloc_code_real_type reloc
)
3978 static const bfd_reloc_code_real_type relocs
[][2] =
3980 /* Keep sorted incrementally by the left-hand key. */
3981 { BFD_RELOC_16_PCREL_S2
, BFD_RELOC_MICROMIPS_16_PCREL_S1
},
3982 { BFD_RELOC_GPREL16
, BFD_RELOC_MICROMIPS_GPREL16
},
3983 { BFD_RELOC_MIPS_JMP
, BFD_RELOC_MICROMIPS_JMP
},
3984 { BFD_RELOC_HI16
, BFD_RELOC_MICROMIPS_HI16
},
3985 { BFD_RELOC_HI16_S
, BFD_RELOC_MICROMIPS_HI16_S
},
3986 { BFD_RELOC_LO16
, BFD_RELOC_MICROMIPS_LO16
},
3987 { BFD_RELOC_MIPS_LITERAL
, BFD_RELOC_MICROMIPS_LITERAL
},
3988 { BFD_RELOC_MIPS_GOT16
, BFD_RELOC_MICROMIPS_GOT16
},
3989 { BFD_RELOC_MIPS_CALL16
, BFD_RELOC_MICROMIPS_CALL16
},
3990 { BFD_RELOC_MIPS_GOT_HI16
, BFD_RELOC_MICROMIPS_GOT_HI16
},
3991 { BFD_RELOC_MIPS_GOT_LO16
, BFD_RELOC_MICROMIPS_GOT_LO16
},
3992 { BFD_RELOC_MIPS_CALL_HI16
, BFD_RELOC_MICROMIPS_CALL_HI16
},
3993 { BFD_RELOC_MIPS_CALL_LO16
, BFD_RELOC_MICROMIPS_CALL_LO16
},
3994 { BFD_RELOC_MIPS_SUB
, BFD_RELOC_MICROMIPS_SUB
},
3995 { BFD_RELOC_MIPS_GOT_PAGE
, BFD_RELOC_MICROMIPS_GOT_PAGE
},
3996 { BFD_RELOC_MIPS_GOT_OFST
, BFD_RELOC_MICROMIPS_GOT_OFST
},
3997 { BFD_RELOC_MIPS_GOT_DISP
, BFD_RELOC_MICROMIPS_GOT_DISP
},
3998 { BFD_RELOC_MIPS_HIGHEST
, BFD_RELOC_MICROMIPS_HIGHEST
},
3999 { BFD_RELOC_MIPS_HIGHER
, BFD_RELOC_MICROMIPS_HIGHER
},
4000 { BFD_RELOC_MIPS_SCN_DISP
, BFD_RELOC_MICROMIPS_SCN_DISP
},
4001 { BFD_RELOC_MIPS_TLS_GD
, BFD_RELOC_MICROMIPS_TLS_GD
},
4002 { BFD_RELOC_MIPS_TLS_LDM
, BFD_RELOC_MICROMIPS_TLS_LDM
},
4003 { BFD_RELOC_MIPS_TLS_DTPREL_HI16
, BFD_RELOC_MICROMIPS_TLS_DTPREL_HI16
},
4004 { BFD_RELOC_MIPS_TLS_DTPREL_LO16
, BFD_RELOC_MICROMIPS_TLS_DTPREL_LO16
},
4005 { BFD_RELOC_MIPS_TLS_GOTTPREL
, BFD_RELOC_MICROMIPS_TLS_GOTTPREL
},
4006 { BFD_RELOC_MIPS_TLS_TPREL_HI16
, BFD_RELOC_MICROMIPS_TLS_TPREL_HI16
},
4007 { BFD_RELOC_MIPS_TLS_TPREL_LO16
, BFD_RELOC_MICROMIPS_TLS_TPREL_LO16
}
4009 bfd_reloc_code_real_type r
;
4012 if (!mips_opts
.micromips
)
4014 for (i
= 0; i
< ARRAY_SIZE (relocs
); i
++)
4020 return relocs
[i
][1];
4025 /* Output an instruction. IP is the instruction information.
4026 ADDRESS_EXPR is an operand of the instruction to be used with
4027 RELOC_TYPE. EXPANSIONP is true if the instruction is part of
4028 a macro expansion. */
4031 append_insn (struct mips_cl_insn
*ip
, expressionS
*address_expr
,
4032 bfd_reloc_code_real_type
*reloc_type
, bfd_boolean expansionp
)
4034 unsigned long prev_pinfo2
, pinfo
;
4035 bfd_boolean relaxed_branch
= FALSE
;
4036 enum append_method method
;
4037 bfd_boolean relax32
;
4040 if (mips_fix_loongson2f
&& !HAVE_CODE_COMPRESSION
)
4041 fix_loongson2f (ip
);
4043 file_ase_mips16
|= mips_opts
.mips16
;
4044 file_ase_micromips
|= mips_opts
.micromips
;
4046 prev_pinfo2
= history
[0].insn_mo
->pinfo2
;
4047 pinfo
= ip
->insn_mo
->pinfo
;
4049 if (mips_opts
.micromips
4051 && (((prev_pinfo2
& INSN2_BRANCH_DELAY_16BIT
) != 0
4052 && micromips_insn_length (ip
->insn_mo
) != 2)
4053 || ((prev_pinfo2
& INSN2_BRANCH_DELAY_32BIT
) != 0
4054 && micromips_insn_length (ip
->insn_mo
) != 4)))
4055 as_warn (_("Wrong size instruction in a %u-bit branch delay slot"),
4056 (prev_pinfo2
& INSN2_BRANCH_DELAY_16BIT
) != 0 ? 16 : 32);
4058 if (address_expr
== NULL
)
4060 else if (*reloc_type
<= BFD_RELOC_UNUSED
4061 && address_expr
->X_op
== O_constant
)
4066 switch (*reloc_type
)
4069 ip
->insn_opcode
|= address_expr
->X_add_number
;
4072 case BFD_RELOC_MIPS_HIGHEST
:
4073 tmp
= (address_expr
->X_add_number
+ 0x800080008000ull
) >> 48;
4074 ip
->insn_opcode
|= tmp
& 0xffff;
4077 case BFD_RELOC_MIPS_HIGHER
:
4078 tmp
= (address_expr
->X_add_number
+ 0x80008000ull
) >> 32;
4079 ip
->insn_opcode
|= tmp
& 0xffff;
4082 case BFD_RELOC_HI16_S
:
4083 tmp
= (address_expr
->X_add_number
+ 0x8000) >> 16;
4084 ip
->insn_opcode
|= tmp
& 0xffff;
4087 case BFD_RELOC_HI16
:
4088 ip
->insn_opcode
|= (address_expr
->X_add_number
>> 16) & 0xffff;
4091 case BFD_RELOC_UNUSED
:
4092 case BFD_RELOC_LO16
:
4093 case BFD_RELOC_MIPS_GOT_DISP
:
4094 ip
->insn_opcode
|= address_expr
->X_add_number
& 0xffff;
4097 case BFD_RELOC_MIPS_JMP
:
4101 shift
= mips_opts
.micromips
? 1 : 2;
4102 if ((address_expr
->X_add_number
& ((1 << shift
) - 1)) != 0)
4103 as_bad (_("jump to misaligned address (0x%lx)"),
4104 (unsigned long) address_expr
->X_add_number
);
4105 ip
->insn_opcode
|= ((address_expr
->X_add_number
>> shift
)
4111 case BFD_RELOC_MIPS16_JMP
:
4112 if ((address_expr
->X_add_number
& 3) != 0)
4113 as_bad (_("jump to misaligned address (0x%lx)"),
4114 (unsigned long) address_expr
->X_add_number
);
4116 (((address_expr
->X_add_number
& 0x7c0000) << 3)
4117 | ((address_expr
->X_add_number
& 0xf800000) >> 7)
4118 | ((address_expr
->X_add_number
& 0x3fffc) >> 2));
4122 case BFD_RELOC_16_PCREL_S2
:
4126 shift
= mips_opts
.micromips
? 1 : 2;
4127 if ((address_expr
->X_add_number
& ((1 << shift
) - 1)) != 0)
4128 as_bad (_("branch to misaligned address (0x%lx)"),
4129 (unsigned long) address_expr
->X_add_number
);
4130 if (!mips_relax_branch
)
4132 if ((address_expr
->X_add_number
+ (1 << (shift
+ 15)))
4133 & ~((1 << (shift
+ 16)) - 1))
4134 as_bad (_("branch address range overflow (0x%lx)"),
4135 (unsigned long) address_expr
->X_add_number
);
4136 ip
->insn_opcode
|= ((address_expr
->X_add_number
>> shift
)
4148 if (mips_relax
.sequence
!= 2 && !mips_opts
.noreorder
)
4150 /* There are a lot of optimizations we could do that we don't.
4151 In particular, we do not, in general, reorder instructions.
4152 If you use gcc with optimization, it will reorder
4153 instructions and generally do much more optimization then we
4154 do here; repeating all that work in the assembler would only
4155 benefit hand written assembly code, and does not seem worth
4157 int nops
= (mips_optimize
== 0
4158 ? nops_for_insn (0, history
, NULL
)
4159 : nops_for_insn_or_target (0, history
, ip
));
4163 unsigned long old_frag_offset
;
4166 old_frag
= frag_now
;
4167 old_frag_offset
= frag_now_fix ();
4169 for (i
= 0; i
< nops
; i
++)
4170 add_fixed_insn (NOP_INSN
);
4171 insert_into_history (0, nops
, NOP_INSN
);
4175 listing_prev_line ();
4176 /* We may be at the start of a variant frag. In case we
4177 are, make sure there is enough space for the frag
4178 after the frags created by listing_prev_line. The
4179 argument to frag_grow here must be at least as large
4180 as the argument to all other calls to frag_grow in
4181 this file. We don't have to worry about being in the
4182 middle of a variant frag, because the variants insert
4183 all needed nop instructions themselves. */
4187 mips_move_text_labels ();
4189 #ifndef NO_ECOFF_DEBUGGING
4190 if (ECOFF_DEBUGGING
)
4191 ecoff_fix_loc (old_frag
, old_frag_offset
);
4195 else if (mips_relax
.sequence
!= 2 && prev_nop_frag
!= NULL
)
4199 /* Work out how many nops in prev_nop_frag are needed by IP,
4200 ignoring hazards generated by the first prev_nop_frag_since
4202 nops
= nops_for_insn_or_target (prev_nop_frag_since
, history
, ip
);
4203 gas_assert (nops
<= prev_nop_frag_holds
);
4205 /* Enforce NOPS as a minimum. */
4206 if (nops
> prev_nop_frag_required
)
4207 prev_nop_frag_required
= nops
;
4209 if (prev_nop_frag_holds
== prev_nop_frag_required
)
4211 /* Settle for the current number of nops. Update the history
4212 accordingly (for the benefit of any future .set reorder code). */
4213 prev_nop_frag
= NULL
;
4214 insert_into_history (prev_nop_frag_since
,
4215 prev_nop_frag_holds
, NOP_INSN
);
4219 /* Allow this instruction to replace one of the nops that was
4220 tentatively added to prev_nop_frag. */
4221 prev_nop_frag
->fr_fix
-= NOP_INSN_SIZE
;
4222 prev_nop_frag_holds
--;
4223 prev_nop_frag_since
++;
4227 method
= get_append_method (ip
);
4228 branch_disp
= method
== APPEND_SWAP
? insn_length (history
) : 0;
4231 /* The value passed to dwarf2_emit_insn is the distance between
4232 the beginning of the current instruction and the address that
4233 should be recorded in the debug tables. This is normally the
4236 For MIPS16/microMIPS debug info we want to use ISA-encoded
4237 addresses, so we use -1 for an address higher by one than the
4240 If the instruction produced is a branch that we will swap with
4241 the preceding instruction, then we add the displacement by which
4242 the branch will be moved backwards. This is more appropriate
4243 and for MIPS16/microMIPS code also prevents a debugger from
4244 placing a breakpoint in the middle of the branch (and corrupting
4245 code if software breakpoints are used). */
4246 dwarf2_emit_insn ((HAVE_CODE_COMPRESSION
? -1 : 0) + branch_disp
);
4249 relax32
= (mips_relax_branch
4250 /* Don't try branch relaxation within .set nomacro, or within
4251 .set noat if we use $at for PIC computations. If it turns
4252 out that the branch was out-of-range, we'll get an error. */
4253 && !mips_opts
.warn_about_macros
4254 && (mips_opts
.at
|| mips_pic
== NO_PIC
)
4255 /* Don't relax BPOSGE32/64 as they have no complementing
4257 && !(ip
->insn_mo
->membership
& (INSN_DSP64
| INSN_DSP
)));
4259 if (!HAVE_CODE_COMPRESSION
4262 && *reloc_type
== BFD_RELOC_16_PCREL_S2
4263 && delayed_branch_p (ip
))
4265 relaxed_branch
= TRUE
;
4266 add_relaxed_insn (ip
, (relaxed_branch_length
4268 uncond_branch_p (ip
) ? -1
4269 : branch_likely_p (ip
) ? 1
4273 uncond_branch_p (ip
),
4274 branch_likely_p (ip
),
4275 pinfo
& INSN_WRITE_GPR_31
,
4277 address_expr
->X_add_symbol
,
4278 address_expr
->X_add_number
);
4279 *reloc_type
= BFD_RELOC_UNUSED
;
4281 else if (mips_opts
.micromips
4283 && ((relax32
&& *reloc_type
== BFD_RELOC_16_PCREL_S2
)
4284 || *reloc_type
> BFD_RELOC_UNUSED
)
4285 && (delayed_branch_p (ip
) || compact_branch_p (ip
))
4286 /* Don't try branch relaxation when users specify
4287 16-bit/32-bit instructions. */
4288 && !forced_insn_length
)
4290 bfd_boolean relax16
= *reloc_type
> BFD_RELOC_UNUSED
;
4291 int type
= relax16
? *reloc_type
- BFD_RELOC_UNUSED
: 0;
4292 int uncond
= uncond_branch_p (ip
) ? -1 : 0;
4293 int compact
= compact_branch_p (ip
);
4294 int al
= pinfo
& INSN_WRITE_GPR_31
;
4297 gas_assert (address_expr
!= NULL
);
4298 gas_assert (!mips_relax
.sequence
);
4300 relaxed_branch
= TRUE
;
4301 length32
= relaxed_micromips_32bit_branch_length (NULL
, NULL
, uncond
);
4302 add_relaxed_insn (ip
, relax32
? length32
: 4, relax16
? 2 : 4,
4303 RELAX_MICROMIPS_ENCODE (type
, AT
, uncond
, compact
, al
,
4305 address_expr
->X_add_symbol
,
4306 address_expr
->X_add_number
);
4307 *reloc_type
= BFD_RELOC_UNUSED
;
4309 else if (mips_opts
.mips16
&& *reloc_type
> BFD_RELOC_UNUSED
)
4311 /* We need to set up a variant frag. */
4312 gas_assert (address_expr
!= NULL
);
4313 add_relaxed_insn (ip
, 4, 0,
4315 (*reloc_type
- BFD_RELOC_UNUSED
,
4316 forced_insn_length
== 2, forced_insn_length
== 4,
4317 delayed_branch_p (&history
[0]),
4318 history
[0].mips16_absolute_jump_p
),
4319 make_expr_symbol (address_expr
), 0);
4321 else if (mips_opts
.mips16
&& insn_length (ip
) == 2)
4323 if (!delayed_branch_p (ip
))
4324 /* Make sure there is enough room to swap this instruction with
4325 a following jump instruction. */
4327 add_fixed_insn (ip
);
4331 if (mips_opts
.mips16
4332 && mips_opts
.noreorder
4333 && delayed_branch_p (&history
[0]))
4334 as_warn (_("extended instruction in delay slot"));
4336 if (mips_relax
.sequence
)
4338 /* If we've reached the end of this frag, turn it into a variant
4339 frag and record the information for the instructions we've
4341 if (frag_room () < 4)
4342 relax_close_frag ();
4343 mips_relax
.sizes
[mips_relax
.sequence
- 1] += insn_length (ip
);
4346 if (mips_relax
.sequence
!= 2)
4348 if (mips_macro_warning
.first_insn_sizes
[0] == 0)
4349 mips_macro_warning
.first_insn_sizes
[0] = insn_length (ip
);
4350 mips_macro_warning
.sizes
[0] += insn_length (ip
);
4351 mips_macro_warning
.insns
[0]++;
4353 if (mips_relax
.sequence
!= 1)
4355 if (mips_macro_warning
.first_insn_sizes
[1] == 0)
4356 mips_macro_warning
.first_insn_sizes
[1] = insn_length (ip
);
4357 mips_macro_warning
.sizes
[1] += insn_length (ip
);
4358 mips_macro_warning
.insns
[1]++;
4361 if (mips_opts
.mips16
)
4364 ip
->mips16_absolute_jump_p
= (*reloc_type
== BFD_RELOC_MIPS16_JMP
);
4366 add_fixed_insn (ip
);
4369 if (!ip
->complete_p
&& *reloc_type
< BFD_RELOC_UNUSED
)
4371 bfd_reloc_code_real_type final_type
[3];
4372 reloc_howto_type
*howto0
;
4373 reloc_howto_type
*howto
;
4376 /* Perform any necessary conversion to microMIPS relocations
4377 and find out how many relocations there actually are. */
4378 for (i
= 0; i
< 3 && reloc_type
[i
] != BFD_RELOC_UNUSED
; i
++)
4379 final_type
[i
] = micromips_map_reloc (reloc_type
[i
]);
4381 /* In a compound relocation, it is the final (outermost)
4382 operator that determines the relocated field. */
4383 howto
= howto0
= bfd_reloc_type_lookup (stdoutput
, final_type
[i
- 1]);
4387 /* To reproduce this failure try assembling gas/testsuites/
4388 gas/mips/mips16-intermix.s with a mips-ecoff targeted
4390 as_bad (_("Unsupported MIPS relocation number %d"),
4392 howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_16
);
4396 howto0
= bfd_reloc_type_lookup (stdoutput
, final_type
[0]);
4397 ip
->fixp
[0] = fix_new_exp (ip
->frag
, ip
->where
,
4398 bfd_get_reloc_size (howto
),
4400 howto0
&& howto0
->pc_relative
,
4403 /* Tag symbols that have a R_MIPS16_26 relocation against them. */
4404 if (final_type
[0] == BFD_RELOC_MIPS16_JMP
&& ip
->fixp
[0]->fx_addsy
)
4405 *symbol_get_tc (ip
->fixp
[0]->fx_addsy
) = 1;
4407 /* These relocations can have an addend that won't fit in
4408 4 octets for 64bit assembly. */
4410 && ! howto
->partial_inplace
4411 && (reloc_type
[0] == BFD_RELOC_16
4412 || reloc_type
[0] == BFD_RELOC_32
4413 || reloc_type
[0] == BFD_RELOC_MIPS_JMP
4414 || reloc_type
[0] == BFD_RELOC_GPREL16
4415 || reloc_type
[0] == BFD_RELOC_MIPS_LITERAL
4416 || reloc_type
[0] == BFD_RELOC_GPREL32
4417 || reloc_type
[0] == BFD_RELOC_64
4418 || reloc_type
[0] == BFD_RELOC_CTOR
4419 || reloc_type
[0] == BFD_RELOC_MIPS_SUB
4420 || reloc_type
[0] == BFD_RELOC_MIPS_HIGHEST
4421 || reloc_type
[0] == BFD_RELOC_MIPS_HIGHER
4422 || reloc_type
[0] == BFD_RELOC_MIPS_SCN_DISP
4423 || reloc_type
[0] == BFD_RELOC_MIPS_REL16
4424 || reloc_type
[0] == BFD_RELOC_MIPS_RELGOT
4425 || reloc_type
[0] == BFD_RELOC_MIPS16_GPREL
4426 || hi16_reloc_p (reloc_type
[0])
4427 || lo16_reloc_p (reloc_type
[0])))
4428 ip
->fixp
[0]->fx_no_overflow
= 1;
4430 if (mips_relax
.sequence
)
4432 if (mips_relax
.first_fixup
== 0)
4433 mips_relax
.first_fixup
= ip
->fixp
[0];
4435 else if (reloc_needs_lo_p (*reloc_type
))
4437 struct mips_hi_fixup
*hi_fixup
;
4439 /* Reuse the last entry if it already has a matching %lo. */
4440 hi_fixup
= mips_hi_fixup_list
;
4442 || !fixup_has_matching_lo_p (hi_fixup
->fixp
))
4444 hi_fixup
= ((struct mips_hi_fixup
*)
4445 xmalloc (sizeof (struct mips_hi_fixup
)));
4446 hi_fixup
->next
= mips_hi_fixup_list
;
4447 mips_hi_fixup_list
= hi_fixup
;
4449 hi_fixup
->fixp
= ip
->fixp
[0];
4450 hi_fixup
->seg
= now_seg
;
4453 /* Add fixups for the second and third relocations, if given.
4454 Note that the ABI allows the second relocation to be
4455 against RSS_UNDEF, RSS_GP, RSS_GP0 or RSS_LOC. At the
4456 moment we only use RSS_UNDEF, but we could add support
4457 for the others if it ever becomes necessary. */
4458 for (i
= 1; i
< 3; i
++)
4459 if (reloc_type
[i
] != BFD_RELOC_UNUSED
)
4461 ip
->fixp
[i
] = fix_new (ip
->frag
, ip
->where
,
4462 ip
->fixp
[0]->fx_size
, NULL
, 0,
4463 FALSE
, final_type
[i
]);
4465 /* Use fx_tcbit to mark compound relocs. */
4466 ip
->fixp
[0]->fx_tcbit
= 1;
4467 ip
->fixp
[i
]->fx_tcbit
= 1;
4472 /* Update the register mask information. */
4473 mips_gprmask
|= gpr_read_mask (ip
) | gpr_write_mask (ip
);
4474 mips_cprmask
[1] |= fpr_read_mask (ip
) | fpr_write_mask (ip
);
4479 insert_into_history (0, 1, ip
);
4482 case APPEND_ADD_WITH_NOP
:
4484 struct mips_cl_insn
*nop
;
4486 insert_into_history (0, 1, ip
);
4487 nop
= get_delay_slot_nop (ip
);
4488 add_fixed_insn (nop
);
4489 insert_into_history (0, 1, nop
);
4490 if (mips_relax
.sequence
)
4491 mips_relax
.sizes
[mips_relax
.sequence
- 1] += insn_length (nop
);
4495 case APPEND_ADD_COMPACT
:
4496 /* Convert MIPS16 jr/jalr into a "compact" jump. */
4497 gas_assert (mips_opts
.mips16
);
4498 ip
->insn_opcode
|= 0x0080;
4499 find_altered_mips16_opcode (ip
);
4501 insert_into_history (0, 1, ip
);
4506 struct mips_cl_insn delay
= history
[0];
4507 if (mips_opts
.mips16
)
4509 know (delay
.frag
== ip
->frag
);
4510 move_insn (ip
, delay
.frag
, delay
.where
);
4511 move_insn (&delay
, ip
->frag
, ip
->where
+ insn_length (ip
));
4513 else if (relaxed_branch
|| delay
.frag
!= ip
->frag
)
4515 /* Add the delay slot instruction to the end of the
4516 current frag and shrink the fixed part of the
4517 original frag. If the branch occupies the tail of
4518 the latter, move it backwards to cover the gap. */
4519 delay
.frag
->fr_fix
-= branch_disp
;
4520 if (delay
.frag
== ip
->frag
)
4521 move_insn (ip
, ip
->frag
, ip
->where
- branch_disp
);
4522 add_fixed_insn (&delay
);
4526 move_insn (&delay
, ip
->frag
,
4527 ip
->where
- branch_disp
+ insn_length (ip
));
4528 move_insn (ip
, history
[0].frag
, history
[0].where
);
4532 insert_into_history (0, 1, &delay
);
4537 /* If we have just completed an unconditional branch, clear the history. */
4538 if ((delayed_branch_p (&history
[1]) && uncond_branch_p (&history
[1]))
4539 || (compact_branch_p (&history
[0]) && uncond_branch_p (&history
[0])))
4540 mips_no_prev_insn ();
4542 /* We need to emit a label at the end of branch-likely macros. */
4543 if (emit_branch_likely_macro
)
4545 emit_branch_likely_macro
= FALSE
;
4546 micromips_add_label ();
4549 /* We just output an insn, so the next one doesn't have a label. */
4550 mips_clear_insn_labels ();
4553 /* Forget that there was any previous instruction or label. */
4556 mips_no_prev_insn (void)
4558 prev_nop_frag
= NULL
;
4559 insert_into_history (0, ARRAY_SIZE (history
), NOP_INSN
);
4560 mips_clear_insn_labels ();
4563 /* This function must be called before we emit something other than
4564 instructions. It is like mips_no_prev_insn except that it inserts
4565 any NOPS that might be needed by previous instructions. */
4568 mips_emit_delays (void)
4570 if (! mips_opts
.noreorder
)
4572 int nops
= nops_for_insn (0, history
, NULL
);
4576 add_fixed_insn (NOP_INSN
);
4577 mips_move_text_labels ();
4580 mips_no_prev_insn ();
4583 /* Start a (possibly nested) noreorder block. */
4586 start_noreorder (void)
4588 if (mips_opts
.noreorder
== 0)
4593 /* None of the instructions before the .set noreorder can be moved. */
4594 for (i
= 0; i
< ARRAY_SIZE (history
); i
++)
4595 history
[i
].fixed_p
= 1;
4597 /* Insert any nops that might be needed between the .set noreorder
4598 block and the previous instructions. We will later remove any
4599 nops that turn out not to be needed. */
4600 nops
= nops_for_insn (0, history
, NULL
);
4603 if (mips_optimize
!= 0)
4605 /* Record the frag which holds the nop instructions, so
4606 that we can remove them if we don't need them. */
4607 frag_grow (nops
* NOP_INSN_SIZE
);
4608 prev_nop_frag
= frag_now
;
4609 prev_nop_frag_holds
= nops
;
4610 prev_nop_frag_required
= 0;
4611 prev_nop_frag_since
= 0;
4614 for (; nops
> 0; --nops
)
4615 add_fixed_insn (NOP_INSN
);
4617 /* Move on to a new frag, so that it is safe to simply
4618 decrease the size of prev_nop_frag. */
4619 frag_wane (frag_now
);
4621 mips_move_text_labels ();
4623 mips_mark_labels ();
4624 mips_clear_insn_labels ();
4626 mips_opts
.noreorder
++;
4627 mips_any_noreorder
= 1;
4630 /* End a nested noreorder block. */
4633 end_noreorder (void)
4635 mips_opts
.noreorder
--;
4636 if (mips_opts
.noreorder
== 0 && prev_nop_frag
!= NULL
)
4638 /* Commit to inserting prev_nop_frag_required nops and go back to
4639 handling nop insertion the .set reorder way. */
4640 prev_nop_frag
->fr_fix
-= ((prev_nop_frag_holds
- prev_nop_frag_required
)
4642 insert_into_history (prev_nop_frag_since
,
4643 prev_nop_frag_required
, NOP_INSN
);
4644 prev_nop_frag
= NULL
;
4648 /* Set up global variables for the start of a new macro. */
4653 memset (&mips_macro_warning
.sizes
, 0, sizeof (mips_macro_warning
.sizes
));
4654 memset (&mips_macro_warning
.first_insn_sizes
, 0,
4655 sizeof (mips_macro_warning
.first_insn_sizes
));
4656 memset (&mips_macro_warning
.insns
, 0, sizeof (mips_macro_warning
.insns
));
4657 mips_macro_warning
.delay_slot_p
= (mips_opts
.noreorder
4658 && delayed_branch_p (&history
[0]));
4659 switch (history
[0].insn_mo
->pinfo2
4660 & (INSN2_BRANCH_DELAY_32BIT
| INSN2_BRANCH_DELAY_16BIT
))
4662 case INSN2_BRANCH_DELAY_32BIT
:
4663 mips_macro_warning
.delay_slot_length
= 4;
4665 case INSN2_BRANCH_DELAY_16BIT
:
4666 mips_macro_warning
.delay_slot_length
= 2;
4669 mips_macro_warning
.delay_slot_length
= 0;
4672 mips_macro_warning
.first_frag
= NULL
;
4675 /* Given that a macro is longer than one instruction or of the wrong size,
4676 return the appropriate warning for it. Return null if no warning is
4677 needed. SUBTYPE is a bitmask of RELAX_DELAY_SLOT, RELAX_DELAY_SLOT_16BIT,
4678 RELAX_DELAY_SLOT_SIZE_FIRST, RELAX_DELAY_SLOT_SIZE_SECOND,
4679 and RELAX_NOMACRO. */
4682 macro_warning (relax_substateT subtype
)
4684 if (subtype
& RELAX_DELAY_SLOT
)
4685 return _("Macro instruction expanded into multiple instructions"
4686 " in a branch delay slot");
4687 else if (subtype
& RELAX_NOMACRO
)
4688 return _("Macro instruction expanded into multiple instructions");
4689 else if (subtype
& (RELAX_DELAY_SLOT_SIZE_FIRST
4690 | RELAX_DELAY_SLOT_SIZE_SECOND
))
4691 return ((subtype
& RELAX_DELAY_SLOT_16BIT
)
4692 ? _("Macro instruction expanded into a wrong size instruction"
4693 " in a 16-bit branch delay slot")
4694 : _("Macro instruction expanded into a wrong size instruction"
4695 " in a 32-bit branch delay slot"));
4700 /* Finish up a macro. Emit warnings as appropriate. */
4705 /* Relaxation warning flags. */
4706 relax_substateT subtype
= 0;
4708 /* Check delay slot size requirements. */
4709 if (mips_macro_warning
.delay_slot_length
== 2)
4710 subtype
|= RELAX_DELAY_SLOT_16BIT
;
4711 if (mips_macro_warning
.delay_slot_length
!= 0)
4713 if (mips_macro_warning
.delay_slot_length
4714 != mips_macro_warning
.first_insn_sizes
[0])
4715 subtype
|= RELAX_DELAY_SLOT_SIZE_FIRST
;
4716 if (mips_macro_warning
.delay_slot_length
4717 != mips_macro_warning
.first_insn_sizes
[1])
4718 subtype
|= RELAX_DELAY_SLOT_SIZE_SECOND
;
4721 /* Check instruction count requirements. */
4722 if (mips_macro_warning
.insns
[0] > 1 || mips_macro_warning
.insns
[1] > 1)
4724 if (mips_macro_warning
.insns
[1] > mips_macro_warning
.insns
[0])
4725 subtype
|= RELAX_SECOND_LONGER
;
4726 if (mips_opts
.warn_about_macros
)
4727 subtype
|= RELAX_NOMACRO
;
4728 if (mips_macro_warning
.delay_slot_p
)
4729 subtype
|= RELAX_DELAY_SLOT
;
4732 /* If both alternatives fail to fill a delay slot correctly,
4733 emit the warning now. */
4734 if ((subtype
& RELAX_DELAY_SLOT_SIZE_FIRST
) != 0
4735 && (subtype
& RELAX_DELAY_SLOT_SIZE_SECOND
) != 0)
4740 s
= subtype
& (RELAX_DELAY_SLOT_16BIT
4741 | RELAX_DELAY_SLOT_SIZE_FIRST
4742 | RELAX_DELAY_SLOT_SIZE_SECOND
);
4743 msg
= macro_warning (s
);
4745 as_warn ("%s", msg
);
4749 /* If both implementations are longer than 1 instruction, then emit the
4751 if (mips_macro_warning
.insns
[0] > 1 && mips_macro_warning
.insns
[1] > 1)
4756 s
= subtype
& (RELAX_SECOND_LONGER
| RELAX_NOMACRO
| RELAX_DELAY_SLOT
);
4757 msg
= macro_warning (s
);
4759 as_warn ("%s", msg
);
4763 /* If any flags still set, then one implementation might need a warning
4764 and the other either will need one of a different kind or none at all.
4765 Pass any remaining flags over to relaxation. */
4766 if (mips_macro_warning
.first_frag
!= NULL
)
4767 mips_macro_warning
.first_frag
->fr_subtype
|= subtype
;
4770 /* Instruction operand formats used in macros that vary between
4771 standard MIPS and microMIPS code. */
4773 static const char * const brk_fmt
[2] = { "c", "mF" };
4774 static const char * const cop12_fmt
[2] = { "E,o(b)", "E,~(b)" };
4775 static const char * const jalr_fmt
[2] = { "d,s", "t,s" };
4776 static const char * const lui_fmt
[2] = { "t,u", "s,u" };
4777 static const char * const mem12_fmt
[2] = { "t,o(b)", "t,~(b)" };
4778 static const char * const mfhl_fmt
[2] = { "d", "mj" };
4779 static const char * const shft_fmt
[2] = { "d,w,<", "t,r,<" };
4780 static const char * const trap_fmt
[2] = { "s,t,q", "s,t,|" };
4782 #define BRK_FMT (brk_fmt[mips_opts.micromips])
4783 #define COP12_FMT (cop12_fmt[mips_opts.micromips])
4784 #define JALR_FMT (jalr_fmt[mips_opts.micromips])
4785 #define LUI_FMT (lui_fmt[mips_opts.micromips])
4786 #define MEM12_FMT (mem12_fmt[mips_opts.micromips])
4787 #define MFHL_FMT (mfhl_fmt[mips_opts.micromips])
4788 #define SHFT_FMT (shft_fmt[mips_opts.micromips])
4789 #define TRAP_FMT (trap_fmt[mips_opts.micromips])
4791 /* Read a macro's relocation codes from *ARGS and store them in *R.
4792 The first argument in *ARGS will be either the code for a single
4793 relocation or -1 followed by the three codes that make up a
4794 composite relocation. */
4797 macro_read_relocs (va_list *args
, bfd_reloc_code_real_type
*r
)
4801 next
= va_arg (*args
, int);
4803 r
[0] = (bfd_reloc_code_real_type
) next
;
4805 for (i
= 0; i
< 3; i
++)
4806 r
[i
] = (bfd_reloc_code_real_type
) va_arg (*args
, int);
4809 /* Build an instruction created by a macro expansion. This is passed
4810 a pointer to the count of instructions created so far, an
4811 expression, the name of the instruction to build, an operand format
4812 string, and corresponding arguments. */
4815 macro_build (expressionS
*ep
, const char *name
, const char *fmt
, ...)
4817 const struct mips_opcode
*mo
= NULL
;
4818 bfd_reloc_code_real_type r
[3];
4819 const struct mips_opcode
*amo
;
4820 struct hash_control
*hash
;
4821 struct mips_cl_insn insn
;
4824 va_start (args
, fmt
);
4826 if (mips_opts
.mips16
)
4828 mips16_macro_build (ep
, name
, fmt
, &args
);
4833 r
[0] = BFD_RELOC_UNUSED
;
4834 r
[1] = BFD_RELOC_UNUSED
;
4835 r
[2] = BFD_RELOC_UNUSED
;
4836 hash
= mips_opts
.micromips
? micromips_op_hash
: op_hash
;
4837 amo
= (struct mips_opcode
*) hash_find (hash
, name
);
4839 gas_assert (strcmp (name
, amo
->name
) == 0);
4843 /* Search until we get a match for NAME. It is assumed here that
4844 macros will never generate MDMX, MIPS-3D, or MT instructions.
4845 We try to match an instruction that fulfils the branch delay
4846 slot instruction length requirement (if any) of the previous
4847 instruction. While doing this we record the first instruction
4848 seen that matches all the other conditions and use it anyway
4849 if the requirement cannot be met; we will issue an appropriate
4850 warning later on. */
4851 if (strcmp (fmt
, amo
->args
) == 0
4852 && amo
->pinfo
!= INSN_MACRO
4853 && is_opcode_valid (amo
)
4854 && is_size_valid (amo
))
4856 if (is_delay_slot_valid (amo
))
4866 gas_assert (amo
->name
);
4868 while (strcmp (name
, amo
->name
) == 0);
4871 create_insn (&insn
, mo
);
4889 INSERT_OPERAND (mips_opts
.micromips
,
4890 EXTLSB
, insn
, va_arg (args
, int));
4895 /* Note that in the macro case, these arguments are already
4896 in MSB form. (When handling the instruction in the
4897 non-macro case, these arguments are sizes from which
4898 MSB values must be calculated.) */
4899 INSERT_OPERAND (mips_opts
.micromips
,
4900 INSMSB
, insn
, va_arg (args
, int));
4906 /* Note that in the macro case, these arguments are already
4907 in MSBD form. (When handling the instruction in the
4908 non-macro case, these arguments are sizes from which
4909 MSBD values must be calculated.) */
4910 INSERT_OPERAND (mips_opts
.micromips
,
4911 EXTMSBD
, insn
, va_arg (args
, int));
4915 gas_assert (!mips_opts
.micromips
);
4916 INSERT_OPERAND (0, SEQI
, insn
, va_arg (args
, int));
4925 INSERT_OPERAND (mips_opts
.micromips
, BP
, insn
, va_arg (args
, int));
4929 gas_assert (mips_opts
.micromips
);
4933 INSERT_OPERAND (mips_opts
.micromips
, RT
, insn
, va_arg (args
, int));
4937 gas_assert (!mips_opts
.micromips
);
4938 INSERT_OPERAND (0, CODE
, insn
, va_arg (args
, int));
4942 gas_assert (!mips_opts
.micromips
);
4944 INSERT_OPERAND (mips_opts
.micromips
, FT
, insn
, va_arg (args
, int));
4948 if (mips_opts
.micromips
)
4949 INSERT_OPERAND (1, RS
, insn
, va_arg (args
, int));
4951 INSERT_OPERAND (0, RD
, insn
, va_arg (args
, int));
4955 gas_assert (!mips_opts
.micromips
);
4957 INSERT_OPERAND (mips_opts
.micromips
, RD
, insn
, va_arg (args
, int));
4961 gas_assert (!mips_opts
.micromips
);
4963 int tmp
= va_arg (args
, int);
4965 INSERT_OPERAND (0, RT
, insn
, tmp
);
4966 INSERT_OPERAND (0, RD
, insn
, tmp
);
4972 gas_assert (!mips_opts
.micromips
);
4973 INSERT_OPERAND (0, FS
, insn
, va_arg (args
, int));
4980 INSERT_OPERAND (mips_opts
.micromips
,
4981 SHAMT
, insn
, va_arg (args
, int));
4985 gas_assert (!mips_opts
.micromips
);
4986 INSERT_OPERAND (0, FD
, insn
, va_arg (args
, int));
4990 gas_assert (!mips_opts
.micromips
);
4991 INSERT_OPERAND (0, CODE20
, insn
, va_arg (args
, int));
4995 gas_assert (!mips_opts
.micromips
);
4996 INSERT_OPERAND (0, CODE19
, insn
, va_arg (args
, int));
5000 gas_assert (!mips_opts
.micromips
);
5001 INSERT_OPERAND (0, CODE2
, insn
, va_arg (args
, int));
5008 INSERT_OPERAND (mips_opts
.micromips
, RS
, insn
, va_arg (args
, int));
5013 macro_read_relocs (&args
, r
);
5014 gas_assert (*r
== BFD_RELOC_GPREL16
5015 || *r
== BFD_RELOC_MIPS_HIGHER
5016 || *r
== BFD_RELOC_HI16_S
5017 || *r
== BFD_RELOC_LO16
5018 || *r
== BFD_RELOC_MIPS_GOT_OFST
);
5022 macro_read_relocs (&args
, r
);
5026 macro_read_relocs (&args
, r
);
5027 gas_assert (ep
!= NULL
5028 && (ep
->X_op
== O_constant
5029 || (ep
->X_op
== O_symbol
5030 && (*r
== BFD_RELOC_MIPS_HIGHEST
5031 || *r
== BFD_RELOC_HI16_S
5032 || *r
== BFD_RELOC_HI16
5033 || *r
== BFD_RELOC_GPREL16
5034 || *r
== BFD_RELOC_MIPS_GOT_HI16
5035 || *r
== BFD_RELOC_MIPS_CALL_HI16
))));
5039 gas_assert (ep
!= NULL
);
5042 * This allows macro() to pass an immediate expression for
5043 * creating short branches without creating a symbol.
5045 * We don't allow branch relaxation for these branches, as
5046 * they should only appear in ".set nomacro" anyway.
5048 if (ep
->X_op
== O_constant
)
5050 /* For microMIPS we always use relocations for branches.
5051 So we should not resolve immediate values. */
5052 gas_assert (!mips_opts
.micromips
);
5054 if ((ep
->X_add_number
& 3) != 0)
5055 as_bad (_("branch to misaligned address (0x%lx)"),
5056 (unsigned long) ep
->X_add_number
);
5057 if ((ep
->X_add_number
+ 0x20000) & ~0x3ffff)
5058 as_bad (_("branch address range overflow (0x%lx)"),
5059 (unsigned long) ep
->X_add_number
);
5060 insn
.insn_opcode
|= (ep
->X_add_number
>> 2) & 0xffff;
5064 *r
= BFD_RELOC_16_PCREL_S2
;
5068 gas_assert (ep
!= NULL
);
5069 *r
= BFD_RELOC_MIPS_JMP
;
5073 gas_assert (!mips_opts
.micromips
);
5074 INSERT_OPERAND (0, COPZ
, insn
, va_arg (args
, unsigned long));
5078 INSERT_OPERAND (mips_opts
.micromips
,
5079 CACHE
, insn
, va_arg (args
, unsigned long));
5083 gas_assert (mips_opts
.micromips
);
5084 INSERT_OPERAND (1, TRAP
, insn
, va_arg (args
, int));
5088 gas_assert (mips_opts
.micromips
);
5089 INSERT_OPERAND (1, OFFSET10
, insn
, va_arg (args
, int));
5093 INSERT_OPERAND (mips_opts
.micromips
,
5094 3BITPOS
, insn
, va_arg (args
, unsigned int));
5098 INSERT_OPERAND (mips_opts
.micromips
,
5099 OFFSET12
, insn
, va_arg (args
, unsigned long));
5103 gas_assert (mips_opts
.micromips
);
5104 INSERT_OPERAND (1, BCC
, insn
, va_arg (args
, int));
5107 case 'm': /* Opcode extension character. */
5108 gas_assert (mips_opts
.micromips
);
5112 INSERT_OPERAND (1, MJ
, insn
, va_arg (args
, int));
5116 INSERT_OPERAND (1, MP
, insn
, va_arg (args
, int));
5120 INSERT_OPERAND (1, IMMF
, insn
, va_arg (args
, int));
5134 gas_assert (*r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
5136 append_insn (&insn
, ep
, r
, TRUE
);
5140 mips16_macro_build (expressionS
*ep
, const char *name
, const char *fmt
,
5143 struct mips_opcode
*mo
;
5144 struct mips_cl_insn insn
;
5145 bfd_reloc_code_real_type r
[3]
5146 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
5148 mo
= (struct mips_opcode
*) hash_find (mips16_op_hash
, name
);
5150 gas_assert (strcmp (name
, mo
->name
) == 0);
5152 while (strcmp (fmt
, mo
->args
) != 0 || mo
->pinfo
== INSN_MACRO
)
5155 gas_assert (mo
->name
);
5156 gas_assert (strcmp (name
, mo
->name
) == 0);
5159 create_insn (&insn
, mo
);
5177 MIPS16_INSERT_OPERAND (RY
, insn
, va_arg (*args
, int));
5182 MIPS16_INSERT_OPERAND (RX
, insn
, va_arg (*args
, int));
5186 MIPS16_INSERT_OPERAND (RZ
, insn
, va_arg (*args
, int));
5190 MIPS16_INSERT_OPERAND (MOVE32Z
, insn
, va_arg (*args
, int));
5200 MIPS16_INSERT_OPERAND (REGR32
, insn
, va_arg (*args
, int));
5207 regno
= va_arg (*args
, int);
5208 regno
= ((regno
& 7) << 2) | ((regno
& 0x18) >> 3);
5209 MIPS16_INSERT_OPERAND (REG32R
, insn
, regno
);
5230 gas_assert (ep
!= NULL
);
5232 if (ep
->X_op
!= O_constant
)
5233 *r
= (int) BFD_RELOC_UNUSED
+ c
;
5236 mips16_immed (NULL
, 0, c
, *r
, ep
->X_add_number
,
5237 0, &insn
.insn_opcode
);
5239 *r
= BFD_RELOC_UNUSED
;
5245 MIPS16_INSERT_OPERAND (IMM6
, insn
, va_arg (*args
, int));
5252 gas_assert (*r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
5254 append_insn (&insn
, ep
, r
, TRUE
);
5258 * Sign-extend 32-bit mode constants that have bit 31 set and all
5259 * higher bits unset.
5262 normalize_constant_expr (expressionS
*ex
)
5264 if (ex
->X_op
== O_constant
5265 && IS_ZEXT_32BIT_NUM (ex
->X_add_number
))
5266 ex
->X_add_number
= (((ex
->X_add_number
& 0xffffffff) ^ 0x80000000)
5271 * Sign-extend 32-bit mode address offsets that have bit 31 set and
5272 * all higher bits unset.
5275 normalize_address_expr (expressionS
*ex
)
5277 if (((ex
->X_op
== O_constant
&& HAVE_32BIT_ADDRESSES
)
5278 || (ex
->X_op
== O_symbol
&& HAVE_32BIT_SYMBOLS
))
5279 && IS_ZEXT_32BIT_NUM (ex
->X_add_number
))
5280 ex
->X_add_number
= (((ex
->X_add_number
& 0xffffffff) ^ 0x80000000)
5285 * Generate a "jalr" instruction with a relocation hint to the called
5286 * function. This occurs in NewABI PIC code.
5289 macro_build_jalr (expressionS
*ep
, int cprestore
)
5291 static const bfd_reloc_code_real_type jalr_relocs
[2]
5292 = { BFD_RELOC_MIPS_JALR
, BFD_RELOC_MICROMIPS_JALR
};
5293 bfd_reloc_code_real_type jalr_reloc
= jalr_relocs
[mips_opts
.micromips
];
5297 if (MIPS_JALR_HINT_P (ep
))
5302 if (mips_opts
.micromips
)
5304 jalr
= mips_opts
.noreorder
&& !cprestore
? "jalr" : "jalrs";
5305 if (MIPS_JALR_HINT_P (ep
))
5306 macro_build (NULL
, jalr
, "t,s", RA
, PIC_CALL_REG
);
5308 macro_build (NULL
, jalr
, "mj", PIC_CALL_REG
);
5311 macro_build (NULL
, "jalr", "d,s", RA
, PIC_CALL_REG
);
5312 if (MIPS_JALR_HINT_P (ep
))
5313 fix_new_exp (frag_now
, f
- frag_now
->fr_literal
, 4, ep
, FALSE
, jalr_reloc
);
5317 * Generate a "lui" instruction.
5320 macro_build_lui (expressionS
*ep
, int regnum
)
5322 gas_assert (! mips_opts
.mips16
);
5324 if (ep
->X_op
!= O_constant
)
5326 gas_assert (ep
->X_op
== O_symbol
);
5327 /* _gp_disp is a special case, used from s_cpload.
5328 __gnu_local_gp is used if mips_no_shared. */
5329 gas_assert (mips_pic
== NO_PIC
5331 && strcmp (S_GET_NAME (ep
->X_add_symbol
), "_gp_disp") == 0)
5332 || (! mips_in_shared
5333 && strcmp (S_GET_NAME (ep
->X_add_symbol
),
5334 "__gnu_local_gp") == 0));
5337 macro_build (ep
, "lui", LUI_FMT
, regnum
, BFD_RELOC_HI16_S
);
5340 /* Generate a sequence of instructions to do a load or store from a constant
5341 offset off of a base register (breg) into/from a target register (treg),
5342 using AT if necessary. */
5344 macro_build_ldst_constoffset (expressionS
*ep
, const char *op
,
5345 int treg
, int breg
, int dbl
)
5347 gas_assert (ep
->X_op
== O_constant
);
5349 /* Sign-extending 32-bit constants makes their handling easier. */
5351 normalize_constant_expr (ep
);
5353 /* Right now, this routine can only handle signed 32-bit constants. */
5354 if (! IS_SEXT_32BIT_NUM(ep
->X_add_number
+ 0x8000))
5355 as_warn (_("operand overflow"));
5357 if (IS_SEXT_16BIT_NUM(ep
->X_add_number
))
5359 /* Signed 16-bit offset will fit in the op. Easy! */
5360 macro_build (ep
, op
, "t,o(b)", treg
, BFD_RELOC_LO16
, breg
);
5364 /* 32-bit offset, need multiple instructions and AT, like:
5365 lui $tempreg,const_hi (BFD_RELOC_HI16_S)
5366 addu $tempreg,$tempreg,$breg
5367 <op> $treg,const_lo($tempreg) (BFD_RELOC_LO16)
5368 to handle the complete offset. */
5369 macro_build_lui (ep
, AT
);
5370 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, AT
, breg
);
5371 macro_build (ep
, op
, "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
5374 as_bad (_("Macro used $at after \".set noat\""));
5379 * Generates code to set the $at register to true (one)
5380 * if reg is less than the immediate expression.
5383 set_at (int reg
, int unsignedp
)
5385 if (imm_expr
.X_op
== O_constant
5386 && imm_expr
.X_add_number
>= -0x8000
5387 && imm_expr
.X_add_number
< 0x8000)
5388 macro_build (&imm_expr
, unsignedp
? "sltiu" : "slti", "t,r,j",
5389 AT
, reg
, BFD_RELOC_LO16
);
5392 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
5393 macro_build (NULL
, unsignedp
? "sltu" : "slt", "d,v,t", AT
, reg
, AT
);
5397 /* Warn if an expression is not a constant. */
5400 check_absolute_expr (struct mips_cl_insn
*ip
, expressionS
*ex
)
5402 if (ex
->X_op
== O_big
)
5403 as_bad (_("unsupported large constant"));
5404 else if (ex
->X_op
!= O_constant
)
5405 as_bad (_("Instruction %s requires absolute expression"),
5408 if (HAVE_32BIT_GPRS
)
5409 normalize_constant_expr (ex
);
5412 /* Count the leading zeroes by performing a binary chop. This is a
5413 bulky bit of source, but performance is a LOT better for the
5414 majority of values than a simple loop to count the bits:
5415 for (lcnt = 0; (lcnt < 32); lcnt++)
5416 if ((v) & (1 << (31 - lcnt)))
5418 However it is not code size friendly, and the gain will drop a bit
5419 on certain cached systems.
5421 #define COUNT_TOP_ZEROES(v) \
5422 (((v) & ~0xffff) == 0 \
5423 ? ((v) & ~0xff) == 0 \
5424 ? ((v) & ~0xf) == 0 \
5425 ? ((v) & ~0x3) == 0 \
5426 ? ((v) & ~0x1) == 0 \
5431 : ((v) & ~0x7) == 0 \
5434 : ((v) & ~0x3f) == 0 \
5435 ? ((v) & ~0x1f) == 0 \
5438 : ((v) & ~0x7f) == 0 \
5441 : ((v) & ~0xfff) == 0 \
5442 ? ((v) & ~0x3ff) == 0 \
5443 ? ((v) & ~0x1ff) == 0 \
5446 : ((v) & ~0x7ff) == 0 \
5449 : ((v) & ~0x3fff) == 0 \
5450 ? ((v) & ~0x1fff) == 0 \
5453 : ((v) & ~0x7fff) == 0 \
5456 : ((v) & ~0xffffff) == 0 \
5457 ? ((v) & ~0xfffff) == 0 \
5458 ? ((v) & ~0x3ffff) == 0 \
5459 ? ((v) & ~0x1ffff) == 0 \
5462 : ((v) & ~0x7ffff) == 0 \
5465 : ((v) & ~0x3fffff) == 0 \
5466 ? ((v) & ~0x1fffff) == 0 \
5469 : ((v) & ~0x7fffff) == 0 \
5472 : ((v) & ~0xfffffff) == 0 \
5473 ? ((v) & ~0x3ffffff) == 0 \
5474 ? ((v) & ~0x1ffffff) == 0 \
5477 : ((v) & ~0x7ffffff) == 0 \
5480 : ((v) & ~0x3fffffff) == 0 \
5481 ? ((v) & ~0x1fffffff) == 0 \
5484 : ((v) & ~0x7fffffff) == 0 \
5489 * This routine generates the least number of instructions necessary to load
5490 * an absolute expression value into a register.
5493 load_register (int reg
, expressionS
*ep
, int dbl
)
5496 expressionS hi32
, lo32
;
5498 if (ep
->X_op
!= O_big
)
5500 gas_assert (ep
->X_op
== O_constant
);
5502 /* Sign-extending 32-bit constants makes their handling easier. */
5504 normalize_constant_expr (ep
);
5506 if (IS_SEXT_16BIT_NUM (ep
->X_add_number
))
5508 /* We can handle 16 bit signed values with an addiu to
5509 $zero. No need to ever use daddiu here, since $zero and
5510 the result are always correct in 32 bit mode. */
5511 macro_build (ep
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
5514 else if (ep
->X_add_number
>= 0 && ep
->X_add_number
< 0x10000)
5516 /* We can handle 16 bit unsigned values with an ori to
5518 macro_build (ep
, "ori", "t,r,i", reg
, 0, BFD_RELOC_LO16
);
5521 else if ((IS_SEXT_32BIT_NUM (ep
->X_add_number
)))
5523 /* 32 bit values require an lui. */
5524 macro_build (ep
, "lui", LUI_FMT
, reg
, BFD_RELOC_HI16
);
5525 if ((ep
->X_add_number
& 0xffff) != 0)
5526 macro_build (ep
, "ori", "t,r,i", reg
, reg
, BFD_RELOC_LO16
);
5531 /* The value is larger than 32 bits. */
5533 if (!dbl
|| HAVE_32BIT_GPRS
)
5537 sprintf_vma (value
, ep
->X_add_number
);
5538 as_bad (_("Number (0x%s) larger than 32 bits"), value
);
5539 macro_build (ep
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
5543 if (ep
->X_op
!= O_big
)
5546 hi32
.X_add_number
= (valueT
) hi32
.X_add_number
>> 16;
5547 hi32
.X_add_number
= (valueT
) hi32
.X_add_number
>> 16;
5548 hi32
.X_add_number
&= 0xffffffff;
5550 lo32
.X_add_number
&= 0xffffffff;
5554 gas_assert (ep
->X_add_number
> 2);
5555 if (ep
->X_add_number
== 3)
5556 generic_bignum
[3] = 0;
5557 else if (ep
->X_add_number
> 4)
5558 as_bad (_("Number larger than 64 bits"));
5559 lo32
.X_op
= O_constant
;
5560 lo32
.X_add_number
= generic_bignum
[0] + (generic_bignum
[1] << 16);
5561 hi32
.X_op
= O_constant
;
5562 hi32
.X_add_number
= generic_bignum
[2] + (generic_bignum
[3] << 16);
5565 if (hi32
.X_add_number
== 0)
5570 unsigned long hi
, lo
;
5572 if (hi32
.X_add_number
== (offsetT
) 0xffffffff)
5574 if ((lo32
.X_add_number
& 0xffff8000) == 0xffff8000)
5576 macro_build (&lo32
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
5579 if (lo32
.X_add_number
& 0x80000000)
5581 macro_build (&lo32
, "lui", LUI_FMT
, reg
, BFD_RELOC_HI16
);
5582 if (lo32
.X_add_number
& 0xffff)
5583 macro_build (&lo32
, "ori", "t,r,i", reg
, reg
, BFD_RELOC_LO16
);
5588 /* Check for 16bit shifted constant. We know that hi32 is
5589 non-zero, so start the mask on the first bit of the hi32
5594 unsigned long himask
, lomask
;
5598 himask
= 0xffff >> (32 - shift
);
5599 lomask
= (0xffff << shift
) & 0xffffffff;
5603 himask
= 0xffff << (shift
- 32);
5606 if ((hi32
.X_add_number
& ~(offsetT
) himask
) == 0
5607 && (lo32
.X_add_number
& ~(offsetT
) lomask
) == 0)
5611 tmp
.X_op
= O_constant
;
5613 tmp
.X_add_number
= ((hi32
.X_add_number
<< (32 - shift
))
5614 | (lo32
.X_add_number
>> shift
));
5616 tmp
.X_add_number
= hi32
.X_add_number
>> (shift
- 32);
5617 macro_build (&tmp
, "ori", "t,r,i", reg
, 0, BFD_RELOC_LO16
);
5618 macro_build (NULL
, (shift
>= 32) ? "dsll32" : "dsll", SHFT_FMT
,
5619 reg
, reg
, (shift
>= 32) ? shift
- 32 : shift
);
5624 while (shift
<= (64 - 16));
5626 /* Find the bit number of the lowest one bit, and store the
5627 shifted value in hi/lo. */
5628 hi
= (unsigned long) (hi32
.X_add_number
& 0xffffffff);
5629 lo
= (unsigned long) (lo32
.X_add_number
& 0xffffffff);
5633 while ((lo
& 1) == 0)
5638 lo
|= (hi
& (((unsigned long) 1 << bit
) - 1)) << (32 - bit
);
5644 while ((hi
& 1) == 0)
5653 /* Optimize if the shifted value is a (power of 2) - 1. */
5654 if ((hi
== 0 && ((lo
+ 1) & lo
) == 0)
5655 || (lo
== 0xffffffff && ((hi
+ 1) & hi
) == 0))
5657 shift
= COUNT_TOP_ZEROES ((unsigned int) hi32
.X_add_number
);
5662 /* This instruction will set the register to be all
5664 tmp
.X_op
= O_constant
;
5665 tmp
.X_add_number
= (offsetT
) -1;
5666 macro_build (&tmp
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
5670 macro_build (NULL
, (bit
>= 32) ? "dsll32" : "dsll", SHFT_FMT
,
5671 reg
, reg
, (bit
>= 32) ? bit
- 32 : bit
);
5673 macro_build (NULL
, (shift
>= 32) ? "dsrl32" : "dsrl", SHFT_FMT
,
5674 reg
, reg
, (shift
>= 32) ? shift
- 32 : shift
);
5679 /* Sign extend hi32 before calling load_register, because we can
5680 generally get better code when we load a sign extended value. */
5681 if ((hi32
.X_add_number
& 0x80000000) != 0)
5682 hi32
.X_add_number
|= ~(offsetT
) 0xffffffff;
5683 load_register (reg
, &hi32
, 0);
5686 if ((lo32
.X_add_number
& 0xffff0000) == 0)
5690 macro_build (NULL
, "dsll32", SHFT_FMT
, reg
, freg
, 0);
5698 if ((freg
== 0) && (lo32
.X_add_number
== (offsetT
) 0xffffffff))
5700 macro_build (&lo32
, "lui", LUI_FMT
, reg
, BFD_RELOC_HI16
);
5701 macro_build (NULL
, "dsrl32", SHFT_FMT
, reg
, reg
, 0);
5707 macro_build (NULL
, "dsll", SHFT_FMT
, reg
, freg
, 16);
5711 mid16
.X_add_number
>>= 16;
5712 macro_build (&mid16
, "ori", "t,r,i", reg
, freg
, BFD_RELOC_LO16
);
5713 macro_build (NULL
, "dsll", SHFT_FMT
, reg
, reg
, 16);
5716 if ((lo32
.X_add_number
& 0xffff) != 0)
5717 macro_build (&lo32
, "ori", "t,r,i", reg
, freg
, BFD_RELOC_LO16
);
5721 load_delay_nop (void)
5723 if (!gpr_interlocks
)
5724 macro_build (NULL
, "nop", "");
5727 /* Load an address into a register. */
5730 load_address (int reg
, expressionS
*ep
, int *used_at
)
5732 if (ep
->X_op
!= O_constant
5733 && ep
->X_op
!= O_symbol
)
5735 as_bad (_("expression too complex"));
5736 ep
->X_op
= O_constant
;
5739 if (ep
->X_op
== O_constant
)
5741 load_register (reg
, ep
, HAVE_64BIT_ADDRESSES
);
5745 if (mips_pic
== NO_PIC
)
5747 /* If this is a reference to a GP relative symbol, we want
5748 addiu $reg,$gp,<sym> (BFD_RELOC_GPREL16)
5750 lui $reg,<sym> (BFD_RELOC_HI16_S)
5751 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
5752 If we have an addend, we always use the latter form.
5754 With 64bit address space and a usable $at we want
5755 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5756 lui $at,<sym> (BFD_RELOC_HI16_S)
5757 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
5758 daddiu $at,<sym> (BFD_RELOC_LO16)
5762 If $at is already in use, we use a path which is suboptimal
5763 on superscalar processors.
5764 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5765 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
5767 daddiu $reg,<sym> (BFD_RELOC_HI16_S)
5769 daddiu $reg,<sym> (BFD_RELOC_LO16)
5771 For GP relative symbols in 64bit address space we can use
5772 the same sequence as in 32bit address space. */
5773 if (HAVE_64BIT_SYMBOLS
)
5775 if ((valueT
) ep
->X_add_number
<= MAX_GPREL_OFFSET
5776 && !nopic_need_relax (ep
->X_add_symbol
, 1))
5778 relax_start (ep
->X_add_symbol
);
5779 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
,
5780 mips_gp_register
, BFD_RELOC_GPREL16
);
5784 if (*used_at
== 0 && mips_opts
.at
)
5786 macro_build (ep
, "lui", LUI_FMT
, reg
, BFD_RELOC_MIPS_HIGHEST
);
5787 macro_build (ep
, "lui", LUI_FMT
, AT
, BFD_RELOC_HI16_S
);
5788 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
,
5789 BFD_RELOC_MIPS_HIGHER
);
5790 macro_build (ep
, "daddiu", "t,r,j", AT
, AT
, BFD_RELOC_LO16
);
5791 macro_build (NULL
, "dsll32", SHFT_FMT
, reg
, reg
, 0);
5792 macro_build (NULL
, "daddu", "d,v,t", reg
, reg
, AT
);
5797 macro_build (ep
, "lui", LUI_FMT
, reg
, BFD_RELOC_MIPS_HIGHEST
);
5798 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
,
5799 BFD_RELOC_MIPS_HIGHER
);
5800 macro_build (NULL
, "dsll", SHFT_FMT
, reg
, reg
, 16);
5801 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
, BFD_RELOC_HI16_S
);
5802 macro_build (NULL
, "dsll", SHFT_FMT
, reg
, reg
, 16);
5803 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
, BFD_RELOC_LO16
);
5806 if (mips_relax
.sequence
)
5811 if ((valueT
) ep
->X_add_number
<= MAX_GPREL_OFFSET
5812 && !nopic_need_relax (ep
->X_add_symbol
, 1))
5814 relax_start (ep
->X_add_symbol
);
5815 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
,
5816 mips_gp_register
, BFD_RELOC_GPREL16
);
5819 macro_build_lui (ep
, reg
);
5820 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j",
5821 reg
, reg
, BFD_RELOC_LO16
);
5822 if (mips_relax
.sequence
)
5826 else if (!mips_big_got
)
5830 /* If this is a reference to an external symbol, we want
5831 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5833 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5835 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
5836 If there is a constant, it must be added in after.
5838 If we have NewABI, we want
5839 lw $reg,<sym+cst>($gp) (BFD_RELOC_MIPS_GOT_DISP)
5840 unless we're referencing a global symbol with a non-zero
5841 offset, in which case cst must be added separately. */
5844 if (ep
->X_add_number
)
5846 ex
.X_add_number
= ep
->X_add_number
;
5847 ep
->X_add_number
= 0;
5848 relax_start (ep
->X_add_symbol
);
5849 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
5850 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
5851 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
5852 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
5853 ex
.X_op
= O_constant
;
5854 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j",
5855 reg
, reg
, BFD_RELOC_LO16
);
5856 ep
->X_add_number
= ex
.X_add_number
;
5859 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
5860 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
5861 if (mips_relax
.sequence
)
5866 ex
.X_add_number
= ep
->X_add_number
;
5867 ep
->X_add_number
= 0;
5868 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
5869 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
5871 relax_start (ep
->X_add_symbol
);
5873 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
5877 if (ex
.X_add_number
!= 0)
5879 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
5880 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
5881 ex
.X_op
= O_constant
;
5882 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j",
5883 reg
, reg
, BFD_RELOC_LO16
);
5887 else if (mips_big_got
)
5891 /* This is the large GOT case. If this is a reference to an
5892 external symbol, we want
5893 lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5895 lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16)
5897 Otherwise, for a reference to a local symbol in old ABI, we want
5898 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5900 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
5901 If there is a constant, it must be added in after.
5903 In the NewABI, for local symbols, with or without offsets, we want:
5904 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
5905 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
5909 ex
.X_add_number
= ep
->X_add_number
;
5910 ep
->X_add_number
= 0;
5911 relax_start (ep
->X_add_symbol
);
5912 macro_build (ep
, "lui", LUI_FMT
, reg
, BFD_RELOC_MIPS_GOT_HI16
);
5913 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5914 reg
, reg
, mips_gp_register
);
5915 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)",
5916 reg
, BFD_RELOC_MIPS_GOT_LO16
, reg
);
5917 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
5918 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
5919 else if (ex
.X_add_number
)
5921 ex
.X_op
= O_constant
;
5922 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
5926 ep
->X_add_number
= ex
.X_add_number
;
5928 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
5929 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
5930 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
5931 BFD_RELOC_MIPS_GOT_OFST
);
5936 ex
.X_add_number
= ep
->X_add_number
;
5937 ep
->X_add_number
= 0;
5938 relax_start (ep
->X_add_symbol
);
5939 macro_build (ep
, "lui", LUI_FMT
, reg
, BFD_RELOC_MIPS_GOT_HI16
);
5940 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5941 reg
, reg
, mips_gp_register
);
5942 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)",
5943 reg
, BFD_RELOC_MIPS_GOT_LO16
, reg
);
5945 if (reg_needs_delay (mips_gp_register
))
5947 /* We need a nop before loading from $gp. This special
5948 check is required because the lui which starts the main
5949 instruction stream does not refer to $gp, and so will not
5950 insert the nop which may be required. */
5951 macro_build (NULL
, "nop", "");
5953 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
5954 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
5956 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
5960 if (ex
.X_add_number
!= 0)
5962 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
5963 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
5964 ex
.X_op
= O_constant
;
5965 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
5973 if (!mips_opts
.at
&& *used_at
== 1)
5974 as_bad (_("Macro used $at after \".set noat\""));
5977 /* Move the contents of register SOURCE into register DEST. */
5980 move_register (int dest
, int source
)
5982 /* Prefer to use a 16-bit microMIPS instruction unless the previous
5983 instruction specifically requires a 32-bit one. */
5984 if (mips_opts
.micromips
5985 && !(history
[0].insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_32BIT
))
5986 macro_build (NULL
, "move", "mp,mj", dest
, source
);
5988 macro_build (NULL
, HAVE_32BIT_GPRS
? "addu" : "daddu", "d,v,t",
5992 /* Emit an SVR4 PIC sequence to load address LOCAL into DEST, where
5993 LOCAL is the sum of a symbol and a 16-bit or 32-bit displacement.
5994 The two alternatives are:
5996 Global symbol Local sybmol
5997 ------------- ------------
5998 lw DEST,%got(SYMBOL) lw DEST,%got(SYMBOL + OFFSET)
6000 addiu DEST,DEST,OFFSET addiu DEST,DEST,%lo(SYMBOL + OFFSET)
6002 load_got_offset emits the first instruction and add_got_offset
6003 emits the second for a 16-bit offset or add_got_offset_hilo emits
6004 a sequence to add a 32-bit offset using a scratch register. */
6007 load_got_offset (int dest
, expressionS
*local
)
6012 global
.X_add_number
= 0;
6014 relax_start (local
->X_add_symbol
);
6015 macro_build (&global
, ADDRESS_LOAD_INSN
, "t,o(b)", dest
,
6016 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
6018 macro_build (local
, ADDRESS_LOAD_INSN
, "t,o(b)", dest
,
6019 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
6024 add_got_offset (int dest
, expressionS
*local
)
6028 global
.X_op
= O_constant
;
6029 global
.X_op_symbol
= NULL
;
6030 global
.X_add_symbol
= NULL
;
6031 global
.X_add_number
= local
->X_add_number
;
6033 relax_start (local
->X_add_symbol
);
6034 macro_build (&global
, ADDRESS_ADDI_INSN
, "t,r,j",
6035 dest
, dest
, BFD_RELOC_LO16
);
6037 macro_build (local
, ADDRESS_ADDI_INSN
, "t,r,j", dest
, dest
, BFD_RELOC_LO16
);
6042 add_got_offset_hilo (int dest
, expressionS
*local
, int tmp
)
6045 int hold_mips_optimize
;
6047 global
.X_op
= O_constant
;
6048 global
.X_op_symbol
= NULL
;
6049 global
.X_add_symbol
= NULL
;
6050 global
.X_add_number
= local
->X_add_number
;
6052 relax_start (local
->X_add_symbol
);
6053 load_register (tmp
, &global
, HAVE_64BIT_ADDRESSES
);
6055 /* Set mips_optimize around the lui instruction to avoid
6056 inserting an unnecessary nop after the lw. */
6057 hold_mips_optimize
= mips_optimize
;
6059 macro_build_lui (&global
, tmp
);
6060 mips_optimize
= hold_mips_optimize
;
6061 macro_build (local
, ADDRESS_ADDI_INSN
, "t,r,j", tmp
, tmp
, BFD_RELOC_LO16
);
6064 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", dest
, dest
, tmp
);
6067 /* Emit a sequence of instructions to emulate a branch likely operation.
6068 BR is an ordinary branch corresponding to one to be emulated. BRNEG
6069 is its complementing branch with the original condition negated.
6070 CALL is set if the original branch specified the link operation.
6071 EP, FMT, SREG and TREG specify the usual macro_build() parameters.
6073 Code like this is produced in the noreorder mode:
6078 delay slot (executed only if branch taken)
6086 delay slot (executed only if branch taken)
6089 In the reorder mode the delay slot would be filled with a nop anyway,
6090 so code produced is simply:
6095 This function is used when producing code for the microMIPS ASE that
6096 does not implement branch likely instructions in hardware. */
6099 macro_build_branch_likely (const char *br
, const char *brneg
,
6100 int call
, expressionS
*ep
, const char *fmt
,
6101 unsigned int sreg
, unsigned int treg
)
6103 int noreorder
= mips_opts
.noreorder
;
6106 gas_assert (mips_opts
.micromips
);
6110 micromips_label_expr (&expr1
);
6111 macro_build (&expr1
, brneg
, fmt
, sreg
, treg
);
6112 macro_build (NULL
, "nop", "");
6113 macro_build (ep
, call
? "bal" : "b", "p");
6115 /* Set to true so that append_insn adds a label. */
6116 emit_branch_likely_macro
= TRUE
;
6120 macro_build (ep
, br
, fmt
, sreg
, treg
);
6121 macro_build (NULL
, "nop", "");
6126 /* Emit a coprocessor branch-likely macro specified by TYPE, using CC as
6127 the condition code tested. EP specifies the branch target. */
6130 macro_build_branch_ccl (int type
, expressionS
*ep
, unsigned int cc
)
6157 macro_build_branch_likely (br
, brneg
, call
, ep
, "N,p", cc
, ZERO
);
6160 /* Emit a two-argument branch macro specified by TYPE, using SREG as
6161 the register tested. EP specifies the branch target. */
6164 macro_build_branch_rs (int type
, expressionS
*ep
, unsigned int sreg
)
6166 const char *brneg
= NULL
;
6176 br
= mips_opts
.micromips
? "bgez" : "bgezl";
6180 gas_assert (mips_opts
.micromips
);
6189 br
= mips_opts
.micromips
? "bgtz" : "bgtzl";
6196 br
= mips_opts
.micromips
? "blez" : "blezl";
6203 br
= mips_opts
.micromips
? "bltz" : "bltzl";
6207 gas_assert (mips_opts
.micromips
);
6215 if (mips_opts
.micromips
&& brneg
)
6216 macro_build_branch_likely (br
, brneg
, call
, ep
, "s,p", sreg
, ZERO
);
6218 macro_build (ep
, br
, "s,p", sreg
);
6221 /* Emit a three-argument branch macro specified by TYPE, using SREG and
6222 TREG as the registers tested. EP specifies the branch target. */
6225 macro_build_branch_rsrt (int type
, expressionS
*ep
,
6226 unsigned int sreg
, unsigned int treg
)
6228 const char *brneg
= NULL
;
6240 br
= mips_opts
.micromips
? "beq" : "beql";
6249 br
= mips_opts
.micromips
? "bne" : "bnel";
6255 if (mips_opts
.micromips
&& brneg
)
6256 macro_build_branch_likely (br
, brneg
, call
, ep
, "s,t,p", sreg
, treg
);
6258 macro_build (ep
, br
, "s,t,p", sreg
, treg
);
6263 * This routine implements the seemingly endless macro or synthesized
6264 * instructions and addressing modes in the mips assembly language. Many
6265 * of these macros are simple and are similar to each other. These could
6266 * probably be handled by some kind of table or grammar approach instead of
6267 * this verbose method. Others are not simple macros but are more like
6268 * optimizing code generation.
6269 * One interesting optimization is when several store macros appear
6270 * consecutively that would load AT with the upper half of the same address.
6271 * The ensuing load upper instructions are ommited. This implies some kind
6272 * of global optimization. We currently only optimize within a single macro.
6273 * For many of the load and store macros if the address is specified as a
6274 * constant expression in the first 64k of memory (ie ld $2,0x4000c) we
6275 * first load register 'at' with zero and use it as the base register. The
6276 * mips assembler simply uses register $zero. Just one tiny optimization
6280 macro (struct mips_cl_insn
*ip
)
6282 unsigned int treg
, sreg
, dreg
, breg
;
6283 unsigned int tempreg
;
6286 expressionS label_expr
;
6305 bfd_reloc_code_real_type r
;
6306 int hold_mips_optimize
;
6308 gas_assert (! mips_opts
.mips16
);
6310 treg
= EXTRACT_OPERAND (mips_opts
.micromips
, RT
, *ip
);
6311 dreg
= EXTRACT_OPERAND (mips_opts
.micromips
, RD
, *ip
);
6312 sreg
= breg
= EXTRACT_OPERAND (mips_opts
.micromips
, RS
, *ip
);
6313 mask
= ip
->insn_mo
->mask
;
6315 label_expr
.X_op
= O_constant
;
6316 label_expr
.X_op_symbol
= NULL
;
6317 label_expr
.X_add_symbol
= NULL
;
6318 label_expr
.X_add_number
= 0;
6320 expr1
.X_op
= O_constant
;
6321 expr1
.X_op_symbol
= NULL
;
6322 expr1
.X_add_symbol
= NULL
;
6323 expr1
.X_add_number
= 1;
6338 if (mips_opts
.micromips
)
6339 micromips_label_expr (&label_expr
);
6341 label_expr
.X_add_number
= 8;
6342 macro_build (&label_expr
, "bgez", "s,p", sreg
);
6344 macro_build (NULL
, "nop", "");
6346 move_register (dreg
, sreg
);
6347 macro_build (NULL
, dbl
? "dsub" : "sub", "d,v,t", dreg
, 0, sreg
);
6348 if (mips_opts
.micromips
)
6349 micromips_add_label ();
6366 if (!mips_opts
.micromips
)
6368 if (imm_expr
.X_op
== O_constant
6369 && imm_expr
.X_add_number
>= -0x200
6370 && imm_expr
.X_add_number
< 0x200)
6372 macro_build (NULL
, s
, "t,r,.", treg
, sreg
, imm_expr
.X_add_number
);
6381 if (imm_expr
.X_op
== O_constant
6382 && imm_expr
.X_add_number
>= -0x8000
6383 && imm_expr
.X_add_number
< 0x8000)
6385 macro_build (&imm_expr
, s
, "t,r,j", treg
, sreg
, BFD_RELOC_LO16
);
6390 load_register (AT
, &imm_expr
, dbl
);
6391 macro_build (NULL
, s2
, "d,v,t", treg
, sreg
, AT
);
6410 if (imm_expr
.X_op
== O_constant
6411 && imm_expr
.X_add_number
>= 0
6412 && imm_expr
.X_add_number
< 0x10000)
6414 if (mask
!= M_NOR_I
)
6415 macro_build (&imm_expr
, s
, "t,r,i", treg
, sreg
, BFD_RELOC_LO16
);
6418 macro_build (&imm_expr
, "ori", "t,r,i",
6419 treg
, sreg
, BFD_RELOC_LO16
);
6420 macro_build (NULL
, "nor", "d,v,t", treg
, treg
, 0);
6426 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
6427 macro_build (NULL
, s2
, "d,v,t", treg
, sreg
, AT
);
6431 switch (imm_expr
.X_add_number
)
6434 macro_build (NULL
, "nop", "");
6437 macro_build (NULL
, "packrl.ph", "d,s,t", treg
, treg
, sreg
);
6441 macro_build (NULL
, "balign", "t,s,2", treg
, sreg
,
6442 (int) imm_expr
.X_add_number
);
6445 as_bad (_("BALIGN immediate not 0, 1, 2 or 3 (%lu)"),
6446 (unsigned long) imm_expr
.X_add_number
);
6455 gas_assert (mips_opts
.micromips
);
6456 macro_build_branch_ccl (mask
, &offset_expr
,
6457 EXTRACT_OPERAND (1, BCC
, *ip
));
6464 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
6470 load_register (treg
, &imm_expr
, HAVE_64BIT_GPRS
);
6475 macro_build_branch_rsrt (mask
, &offset_expr
, sreg
, treg
);
6482 macro_build_branch_rs (likely
? M_BGEZL
: M_BGEZ
, &offset_expr
, sreg
);
6484 macro_build_branch_rs (likely
? M_BLEZL
: M_BLEZ
, &offset_expr
, treg
);
6488 macro_build (NULL
, "slt", "d,v,t", AT
, sreg
, treg
);
6489 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
6490 &offset_expr
, AT
, ZERO
);
6500 macro_build_branch_rs (mask
, &offset_expr
, sreg
);
6506 /* Check for > max integer. */
6507 maxnum
= 0x7fffffff;
6508 if (HAVE_64BIT_GPRS
&& sizeof (maxnum
) > 4)
6515 if (imm_expr
.X_op
== O_constant
6516 && imm_expr
.X_add_number
>= maxnum
6517 && (HAVE_32BIT_GPRS
|| sizeof (maxnum
) > 4))
6520 /* Result is always false. */
6522 macro_build (NULL
, "nop", "");
6524 macro_build_branch_rsrt (M_BNEL
, &offset_expr
, ZERO
, ZERO
);
6527 if (imm_expr
.X_op
!= O_constant
)
6528 as_bad (_("Unsupported large constant"));
6529 ++imm_expr
.X_add_number
;
6533 if (mask
== M_BGEL_I
)
6535 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
6537 macro_build_branch_rs (likely
? M_BGEZL
: M_BGEZ
,
6538 &offset_expr
, sreg
);
6541 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
6543 macro_build_branch_rs (likely
? M_BGTZL
: M_BGTZ
,
6544 &offset_expr
, sreg
);
6547 maxnum
= 0x7fffffff;
6548 if (HAVE_64BIT_GPRS
&& sizeof (maxnum
) > 4)
6555 maxnum
= - maxnum
- 1;
6556 if (imm_expr
.X_op
== O_constant
6557 && imm_expr
.X_add_number
<= maxnum
6558 && (HAVE_32BIT_GPRS
|| sizeof (maxnum
) > 4))
6561 /* result is always true */
6562 as_warn (_("Branch %s is always true"), ip
->insn_mo
->name
);
6563 macro_build (&offset_expr
, "b", "p");
6568 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
6569 &offset_expr
, AT
, ZERO
);
6578 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
6579 &offset_expr
, ZERO
, treg
);
6583 macro_build (NULL
, "sltu", "d,v,t", AT
, sreg
, treg
);
6584 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
6585 &offset_expr
, AT
, ZERO
);
6594 && imm_expr
.X_op
== O_constant
6595 && imm_expr
.X_add_number
== -1))
6597 if (imm_expr
.X_op
!= O_constant
)
6598 as_bad (_("Unsupported large constant"));
6599 ++imm_expr
.X_add_number
;
6603 if (mask
== M_BGEUL_I
)
6605 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
6607 else if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
6608 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
6609 &offset_expr
, sreg
, ZERO
);
6614 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
6615 &offset_expr
, AT
, ZERO
);
6623 macro_build_branch_rs (likely
? M_BGTZL
: M_BGTZ
, &offset_expr
, sreg
);
6625 macro_build_branch_rs (likely
? M_BLTZL
: M_BLTZ
, &offset_expr
, treg
);
6629 macro_build (NULL
, "slt", "d,v,t", AT
, treg
, sreg
);
6630 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
6631 &offset_expr
, AT
, ZERO
);
6639 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
6640 &offset_expr
, sreg
, ZERO
);
6646 macro_build (NULL
, "sltu", "d,v,t", AT
, treg
, sreg
);
6647 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
6648 &offset_expr
, AT
, ZERO
);
6656 macro_build_branch_rs (likely
? M_BLEZL
: M_BLEZ
, &offset_expr
, sreg
);
6658 macro_build_branch_rs (likely
? M_BGEZL
: M_BGEZ
, &offset_expr
, treg
);
6662 macro_build (NULL
, "slt", "d,v,t", AT
, treg
, sreg
);
6663 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
6664 &offset_expr
, AT
, ZERO
);
6671 maxnum
= 0x7fffffff;
6672 if (HAVE_64BIT_GPRS
&& sizeof (maxnum
) > 4)
6679 if (imm_expr
.X_op
== O_constant
6680 && imm_expr
.X_add_number
>= maxnum
6681 && (HAVE_32BIT_GPRS
|| sizeof (maxnum
) > 4))
6683 if (imm_expr
.X_op
!= O_constant
)
6684 as_bad (_("Unsupported large constant"));
6685 ++imm_expr
.X_add_number
;
6689 if (mask
== M_BLTL_I
)
6691 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
6692 macro_build_branch_rs (likely
? M_BLTZL
: M_BLTZ
, &offset_expr
, sreg
);
6693 else if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
6694 macro_build_branch_rs (likely
? M_BLEZL
: M_BLEZ
, &offset_expr
, sreg
);
6699 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
6700 &offset_expr
, AT
, ZERO
);
6708 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
6709 &offset_expr
, sreg
, ZERO
);
6715 macro_build (NULL
, "sltu", "d,v,t", AT
, treg
, sreg
);
6716 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
6717 &offset_expr
, AT
, ZERO
);
6726 && imm_expr
.X_op
== O_constant
6727 && imm_expr
.X_add_number
== -1))
6729 if (imm_expr
.X_op
!= O_constant
)
6730 as_bad (_("Unsupported large constant"));
6731 ++imm_expr
.X_add_number
;
6735 if (mask
== M_BLTUL_I
)
6737 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
6739 else if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
6740 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
6741 &offset_expr
, sreg
, ZERO
);
6746 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
6747 &offset_expr
, AT
, ZERO
);
6755 macro_build_branch_rs (likely
? M_BLTZL
: M_BLTZ
, &offset_expr
, sreg
);
6757 macro_build_branch_rs (likely
? M_BGTZL
: M_BGTZ
, &offset_expr
, treg
);
6761 macro_build (NULL
, "slt", "d,v,t", AT
, sreg
, treg
);
6762 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
6763 &offset_expr
, AT
, ZERO
);
6773 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
6774 &offset_expr
, ZERO
, treg
);
6778 macro_build (NULL
, "sltu", "d,v,t", AT
, sreg
, treg
);
6779 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
6780 &offset_expr
, AT
, ZERO
);
6786 /* Use unsigned arithmetic. */
6790 if (imm_expr
.X_op
!= O_constant
|| imm2_expr
.X_op
!= O_constant
)
6792 as_bad (_("Unsupported large constant"));
6797 pos
= imm_expr
.X_add_number
;
6798 size
= imm2_expr
.X_add_number
;
6803 as_bad (_("Improper position (%lu)"), (unsigned long) pos
);
6806 if (size
== 0 || size
> 64 || (pos
+ size
- 1) > 63)
6808 as_bad (_("Improper extract size (%lu, position %lu)"),
6809 (unsigned long) size
, (unsigned long) pos
);
6813 if (size
<= 32 && pos
< 32)
6818 else if (size
<= 32)
6828 macro_build ((expressionS
*) NULL
, s
, fmt
, treg
, sreg
, (int) pos
,
6835 /* Use unsigned arithmetic. */
6839 if (imm_expr
.X_op
!= O_constant
|| imm2_expr
.X_op
!= O_constant
)
6841 as_bad (_("Unsupported large constant"));
6846 pos
= imm_expr
.X_add_number
;
6847 size
= imm2_expr
.X_add_number
;
6852 as_bad (_("Improper position (%lu)"), (unsigned long) pos
);
6855 if (size
== 0 || size
> 64 || (pos
+ size
- 1) > 63)
6857 as_bad (_("Improper insert size (%lu, position %lu)"),
6858 (unsigned long) size
, (unsigned long) pos
);
6862 if (pos
< 32 && (pos
+ size
- 1) < 32)
6877 macro_build ((expressionS
*) NULL
, s
, fmt
, treg
, sreg
, (int) pos
,
6878 (int) (pos
+ size
- 1));
6894 as_warn (_("Divide by zero."));
6896 macro_build (NULL
, "teq", TRAP_FMT
, ZERO
, ZERO
, 7);
6898 macro_build (NULL
, "break", BRK_FMT
, 7);
6905 macro_build (NULL
, "teq", TRAP_FMT
, treg
, ZERO
, 7);
6906 macro_build (NULL
, dbl
? "ddiv" : "div", "z,s,t", sreg
, treg
);
6910 if (mips_opts
.micromips
)
6911 micromips_label_expr (&label_expr
);
6913 label_expr
.X_add_number
= 8;
6914 macro_build (&label_expr
, "bne", "s,t,p", treg
, ZERO
);
6915 macro_build (NULL
, dbl
? "ddiv" : "div", "z,s,t", sreg
, treg
);
6916 macro_build (NULL
, "break", BRK_FMT
, 7);
6917 if (mips_opts
.micromips
)
6918 micromips_add_label ();
6920 expr1
.X_add_number
= -1;
6922 load_register (AT
, &expr1
, dbl
);
6923 if (mips_opts
.micromips
)
6924 micromips_label_expr (&label_expr
);
6926 label_expr
.X_add_number
= mips_trap
? (dbl
? 12 : 8) : (dbl
? 20 : 16);
6927 macro_build (&label_expr
, "bne", "s,t,p", treg
, AT
);
6930 expr1
.X_add_number
= 1;
6931 load_register (AT
, &expr1
, dbl
);
6932 macro_build (NULL
, "dsll32", SHFT_FMT
, AT
, AT
, 31);
6936 expr1
.X_add_number
= 0x80000000;
6937 macro_build (&expr1
, "lui", LUI_FMT
, AT
, BFD_RELOC_HI16
);
6941 macro_build (NULL
, "teq", TRAP_FMT
, sreg
, AT
, 6);
6942 /* We want to close the noreorder block as soon as possible, so
6943 that later insns are available for delay slot filling. */
6948 if (mips_opts
.micromips
)
6949 micromips_label_expr (&label_expr
);
6951 label_expr
.X_add_number
= 8;
6952 macro_build (&label_expr
, "bne", "s,t,p", sreg
, AT
);
6953 macro_build (NULL
, "nop", "");
6955 /* We want to close the noreorder block as soon as possible, so
6956 that later insns are available for delay slot filling. */
6959 macro_build (NULL
, "break", BRK_FMT
, 6);
6961 if (mips_opts
.micromips
)
6962 micromips_add_label ();
6963 macro_build (NULL
, s
, MFHL_FMT
, dreg
);
7002 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
7004 as_warn (_("Divide by zero."));
7006 macro_build (NULL
, "teq", TRAP_FMT
, ZERO
, ZERO
, 7);
7008 macro_build (NULL
, "break", BRK_FMT
, 7);
7011 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
7013 if (strcmp (s2
, "mflo") == 0)
7014 move_register (dreg
, sreg
);
7016 move_register (dreg
, ZERO
);
7019 if (imm_expr
.X_op
== O_constant
7020 && imm_expr
.X_add_number
== -1
7021 && s
[strlen (s
) - 1] != 'u')
7023 if (strcmp (s2
, "mflo") == 0)
7025 macro_build (NULL
, dbl
? "dneg" : "neg", "d,w", dreg
, sreg
);
7028 move_register (dreg
, ZERO
);
7033 load_register (AT
, &imm_expr
, dbl
);
7034 macro_build (NULL
, s
, "z,s,t", sreg
, AT
);
7035 macro_build (NULL
, s2
, MFHL_FMT
, dreg
);
7057 macro_build (NULL
, "teq", TRAP_FMT
, treg
, ZERO
, 7);
7058 macro_build (NULL
, s
, "z,s,t", sreg
, treg
);
7059 /* We want to close the noreorder block as soon as possible, so
7060 that later insns are available for delay slot filling. */
7065 if (mips_opts
.micromips
)
7066 micromips_label_expr (&label_expr
);
7068 label_expr
.X_add_number
= 8;
7069 macro_build (&label_expr
, "bne", "s,t,p", treg
, ZERO
);
7070 macro_build (NULL
, s
, "z,s,t", sreg
, treg
);
7072 /* We want to close the noreorder block as soon as possible, so
7073 that later insns are available for delay slot filling. */
7075 macro_build (NULL
, "break", BRK_FMT
, 7);
7076 if (mips_opts
.micromips
)
7077 micromips_add_label ();
7079 macro_build (NULL
, s2
, MFHL_FMT
, dreg
);
7091 /* Load the address of a symbol into a register. If breg is not
7092 zero, we then add a base register to it. */
7094 if (dbl
&& HAVE_32BIT_GPRS
)
7095 as_warn (_("dla used to load 32-bit register"));
7097 if (!dbl
&& HAVE_64BIT_OBJECTS
)
7098 as_warn (_("la used to load 64-bit address"));
7100 if (offset_expr
.X_op
== O_constant
7101 && offset_expr
.X_add_number
>= -0x8000
7102 && offset_expr
.X_add_number
< 0x8000)
7104 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
,
7105 "t,r,j", treg
, sreg
, BFD_RELOC_LO16
);
7109 if (mips_opts
.at
&& (treg
== breg
))
7119 if (offset_expr
.X_op
!= O_symbol
7120 && offset_expr
.X_op
!= O_constant
)
7122 as_bad (_("Expression too complex"));
7123 offset_expr
.X_op
= O_constant
;
7126 if (offset_expr
.X_op
== O_constant
)
7127 load_register (tempreg
, &offset_expr
, HAVE_64BIT_ADDRESSES
);
7128 else if (mips_pic
== NO_PIC
)
7130 /* If this is a reference to a GP relative symbol, we want
7131 addiu $tempreg,$gp,<sym> (BFD_RELOC_GPREL16)
7133 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
7134 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
7135 If we have a constant, we need two instructions anyhow,
7136 so we may as well always use the latter form.
7138 With 64bit address space and a usable $at we want
7139 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
7140 lui $at,<sym> (BFD_RELOC_HI16_S)
7141 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
7142 daddiu $at,<sym> (BFD_RELOC_LO16)
7144 daddu $tempreg,$tempreg,$at
7146 If $at is already in use, we use a path which is suboptimal
7147 on superscalar processors.
7148 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
7149 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
7151 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
7153 daddiu $tempreg,<sym> (BFD_RELOC_LO16)
7155 For GP relative symbols in 64bit address space we can use
7156 the same sequence as in 32bit address space. */
7157 if (HAVE_64BIT_SYMBOLS
)
7159 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
7160 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
7162 relax_start (offset_expr
.X_add_symbol
);
7163 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
7164 tempreg
, mips_gp_register
, BFD_RELOC_GPREL16
);
7168 if (used_at
== 0 && mips_opts
.at
)
7170 macro_build (&offset_expr
, "lui", LUI_FMT
,
7171 tempreg
, BFD_RELOC_MIPS_HIGHEST
);
7172 macro_build (&offset_expr
, "lui", LUI_FMT
,
7173 AT
, BFD_RELOC_HI16_S
);
7174 macro_build (&offset_expr
, "daddiu", "t,r,j",
7175 tempreg
, tempreg
, BFD_RELOC_MIPS_HIGHER
);
7176 macro_build (&offset_expr
, "daddiu", "t,r,j",
7177 AT
, AT
, BFD_RELOC_LO16
);
7178 macro_build (NULL
, "dsll32", SHFT_FMT
, tempreg
, tempreg
, 0);
7179 macro_build (NULL
, "daddu", "d,v,t", tempreg
, tempreg
, AT
);
7184 macro_build (&offset_expr
, "lui", LUI_FMT
,
7185 tempreg
, BFD_RELOC_MIPS_HIGHEST
);
7186 macro_build (&offset_expr
, "daddiu", "t,r,j",
7187 tempreg
, tempreg
, BFD_RELOC_MIPS_HIGHER
);
7188 macro_build (NULL
, "dsll", SHFT_FMT
, tempreg
, tempreg
, 16);
7189 macro_build (&offset_expr
, "daddiu", "t,r,j",
7190 tempreg
, tempreg
, BFD_RELOC_HI16_S
);
7191 macro_build (NULL
, "dsll", SHFT_FMT
, tempreg
, tempreg
, 16);
7192 macro_build (&offset_expr
, "daddiu", "t,r,j",
7193 tempreg
, tempreg
, BFD_RELOC_LO16
);
7196 if (mips_relax
.sequence
)
7201 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
7202 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
7204 relax_start (offset_expr
.X_add_symbol
);
7205 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
7206 tempreg
, mips_gp_register
, BFD_RELOC_GPREL16
);
7209 if (!IS_SEXT_32BIT_NUM (offset_expr
.X_add_number
))
7210 as_bad (_("Offset too large"));
7211 macro_build_lui (&offset_expr
, tempreg
);
7212 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
7213 tempreg
, tempreg
, BFD_RELOC_LO16
);
7214 if (mips_relax
.sequence
)
7218 else if (!mips_big_got
&& !HAVE_NEWABI
)
7220 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT16
;
7222 /* If this is a reference to an external symbol, and there
7223 is no constant, we want
7224 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7225 or for lca or if tempreg is PIC_CALL_REG
7226 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
7227 For a local symbol, we want
7228 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7230 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
7232 If we have a small constant, and this is a reference to
7233 an external symbol, we want
7234 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7236 addiu $tempreg,$tempreg,<constant>
7237 For a local symbol, we want the same instruction
7238 sequence, but we output a BFD_RELOC_LO16 reloc on the
7241 If we have a large constant, and this is a reference to
7242 an external symbol, we want
7243 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7244 lui $at,<hiconstant>
7245 addiu $at,$at,<loconstant>
7246 addu $tempreg,$tempreg,$at
7247 For a local symbol, we want the same instruction
7248 sequence, but we output a BFD_RELOC_LO16 reloc on the
7252 if (offset_expr
.X_add_number
== 0)
7254 if (mips_pic
== SVR4_PIC
7256 && (call
|| tempreg
== PIC_CALL_REG
))
7257 lw_reloc_type
= (int) BFD_RELOC_MIPS_CALL16
;
7259 relax_start (offset_expr
.X_add_symbol
);
7260 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
7261 lw_reloc_type
, mips_gp_register
);
7264 /* We're going to put in an addu instruction using
7265 tempreg, so we may as well insert the nop right
7270 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
7271 tempreg
, BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
7273 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
7274 tempreg
, tempreg
, BFD_RELOC_LO16
);
7276 /* FIXME: If breg == 0, and the next instruction uses
7277 $tempreg, then if this variant case is used an extra
7278 nop will be generated. */
7280 else if (offset_expr
.X_add_number
>= -0x8000
7281 && offset_expr
.X_add_number
< 0x8000)
7283 load_got_offset (tempreg
, &offset_expr
);
7285 add_got_offset (tempreg
, &offset_expr
);
7289 expr1
.X_add_number
= offset_expr
.X_add_number
;
7290 offset_expr
.X_add_number
=
7291 SEXT_16BIT (offset_expr
.X_add_number
);
7292 load_got_offset (tempreg
, &offset_expr
);
7293 offset_expr
.X_add_number
= expr1
.X_add_number
;
7294 /* If we are going to add in a base register, and the
7295 target register and the base register are the same,
7296 then we are using AT as a temporary register. Since
7297 we want to load the constant into AT, we add our
7298 current AT (from the global offset table) and the
7299 register into the register now, and pretend we were
7300 not using a base register. */
7304 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
7309 add_got_offset_hilo (tempreg
, &offset_expr
, AT
);
7313 else if (!mips_big_got
&& HAVE_NEWABI
)
7315 int add_breg_early
= 0;
7317 /* If this is a reference to an external, and there is no
7318 constant, or local symbol (*), with or without a
7320 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
7321 or for lca or if tempreg is PIC_CALL_REG
7322 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
7324 If we have a small constant, and this is a reference to
7325 an external symbol, we want
7326 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
7327 addiu $tempreg,$tempreg,<constant>
7329 If we have a large constant, and this is a reference to
7330 an external symbol, we want
7331 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
7332 lui $at,<hiconstant>
7333 addiu $at,$at,<loconstant>
7334 addu $tempreg,$tempreg,$at
7336 (*) Other assemblers seem to prefer GOT_PAGE/GOT_OFST for
7337 local symbols, even though it introduces an additional
7340 if (offset_expr
.X_add_number
)
7342 expr1
.X_add_number
= offset_expr
.X_add_number
;
7343 offset_expr
.X_add_number
= 0;
7345 relax_start (offset_expr
.X_add_symbol
);
7346 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
7347 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
7349 if (expr1
.X_add_number
>= -0x8000
7350 && expr1
.X_add_number
< 0x8000)
7352 macro_build (&expr1
, ADDRESS_ADDI_INSN
, "t,r,j",
7353 tempreg
, tempreg
, BFD_RELOC_LO16
);
7355 else if (IS_SEXT_32BIT_NUM (expr1
.X_add_number
+ 0x8000))
7357 /* If we are going to add in a base register, and the
7358 target register and the base register are the same,
7359 then we are using AT as a temporary register. Since
7360 we want to load the constant into AT, we add our
7361 current AT (from the global offset table) and the
7362 register into the register now, and pretend we were
7363 not using a base register. */
7368 gas_assert (tempreg
== AT
);
7369 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
7375 load_register (AT
, &expr1
, HAVE_64BIT_ADDRESSES
);
7376 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
7382 as_bad (_("PIC code offset overflow (max 32 signed bits)"));
7385 offset_expr
.X_add_number
= expr1
.X_add_number
;
7387 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
7388 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
7391 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
7392 treg
, tempreg
, breg
);
7398 else if (breg
== 0 && (call
|| tempreg
== PIC_CALL_REG
))
7400 relax_start (offset_expr
.X_add_symbol
);
7401 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
7402 BFD_RELOC_MIPS_CALL16
, mips_gp_register
);
7404 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
7405 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
7410 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
7411 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
7414 else if (mips_big_got
&& !HAVE_NEWABI
)
7417 int lui_reloc_type
= (int) BFD_RELOC_MIPS_GOT_HI16
;
7418 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT_LO16
;
7419 int local_reloc_type
= (int) BFD_RELOC_MIPS_GOT16
;
7421 /* This is the large GOT case. If this is a reference to an
7422 external symbol, and there is no constant, we want
7423 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
7424 addu $tempreg,$tempreg,$gp
7425 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
7426 or for lca or if tempreg is PIC_CALL_REG
7427 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
7428 addu $tempreg,$tempreg,$gp
7429 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
7430 For a local symbol, we want
7431 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7433 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
7435 If we have a small constant, and this is a reference to
7436 an external symbol, we want
7437 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
7438 addu $tempreg,$tempreg,$gp
7439 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
7441 addiu $tempreg,$tempreg,<constant>
7442 For a local symbol, we want
7443 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7445 addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16)
7447 If we have a large constant, and this is a reference to
7448 an external symbol, we want
7449 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
7450 addu $tempreg,$tempreg,$gp
7451 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
7452 lui $at,<hiconstant>
7453 addiu $at,$at,<loconstant>
7454 addu $tempreg,$tempreg,$at
7455 For a local symbol, we want
7456 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7457 lui $at,<hiconstant>
7458 addiu $at,$at,<loconstant> (BFD_RELOC_LO16)
7459 addu $tempreg,$tempreg,$at
7462 expr1
.X_add_number
= offset_expr
.X_add_number
;
7463 offset_expr
.X_add_number
= 0;
7464 relax_start (offset_expr
.X_add_symbol
);
7465 gpdelay
= reg_needs_delay (mips_gp_register
);
7466 if (expr1
.X_add_number
== 0 && breg
== 0
7467 && (call
|| tempreg
== PIC_CALL_REG
))
7469 lui_reloc_type
= (int) BFD_RELOC_MIPS_CALL_HI16
;
7470 lw_reloc_type
= (int) BFD_RELOC_MIPS_CALL_LO16
;
7472 macro_build (&offset_expr
, "lui", LUI_FMT
, tempreg
, lui_reloc_type
);
7473 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
7474 tempreg
, tempreg
, mips_gp_register
);
7475 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
7476 tempreg
, lw_reloc_type
, tempreg
);
7477 if (expr1
.X_add_number
== 0)
7481 /* We're going to put in an addu instruction using
7482 tempreg, so we may as well insert the nop right
7487 else if (expr1
.X_add_number
>= -0x8000
7488 && expr1
.X_add_number
< 0x8000)
7491 macro_build (&expr1
, ADDRESS_ADDI_INSN
, "t,r,j",
7492 tempreg
, tempreg
, BFD_RELOC_LO16
);
7496 /* If we are going to add in a base register, and the
7497 target register and the base register are the same,
7498 then we are using AT as a temporary register. Since
7499 we want to load the constant into AT, we add our
7500 current AT (from the global offset table) and the
7501 register into the register now, and pretend we were
7502 not using a base register. */
7507 gas_assert (tempreg
== AT
);
7509 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
7514 load_register (AT
, &expr1
, HAVE_64BIT_ADDRESSES
);
7515 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", dreg
, dreg
, AT
);
7519 offset_expr
.X_add_number
= SEXT_16BIT (expr1
.X_add_number
);
7524 /* This is needed because this instruction uses $gp, but
7525 the first instruction on the main stream does not. */
7526 macro_build (NULL
, "nop", "");
7529 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
7530 local_reloc_type
, mips_gp_register
);
7531 if (expr1
.X_add_number
>= -0x8000
7532 && expr1
.X_add_number
< 0x8000)
7535 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
7536 tempreg
, tempreg
, BFD_RELOC_LO16
);
7537 /* FIXME: If add_number is 0, and there was no base
7538 register, the external symbol case ended with a load,
7539 so if the symbol turns out to not be external, and
7540 the next instruction uses tempreg, an unnecessary nop
7541 will be inserted. */
7547 /* We must add in the base register now, as in the
7548 external symbol case. */
7549 gas_assert (tempreg
== AT
);
7551 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
7554 /* We set breg to 0 because we have arranged to add
7555 it in in both cases. */
7559 macro_build_lui (&expr1
, AT
);
7560 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
7561 AT
, AT
, BFD_RELOC_LO16
);
7562 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
7563 tempreg
, tempreg
, AT
);
7568 else if (mips_big_got
&& HAVE_NEWABI
)
7570 int lui_reloc_type
= (int) BFD_RELOC_MIPS_GOT_HI16
;
7571 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT_LO16
;
7572 int add_breg_early
= 0;
7574 /* This is the large GOT case. If this is a reference to an
7575 external symbol, and there is no constant, we want
7576 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
7577 add $tempreg,$tempreg,$gp
7578 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
7579 or for lca or if tempreg is PIC_CALL_REG
7580 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
7581 add $tempreg,$tempreg,$gp
7582 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
7584 If we have a small constant, and this is a reference to
7585 an external symbol, we want
7586 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
7587 add $tempreg,$tempreg,$gp
7588 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
7589 addi $tempreg,$tempreg,<constant>
7591 If we have a large constant, and this is a reference to
7592 an external symbol, we want
7593 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
7594 addu $tempreg,$tempreg,$gp
7595 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
7596 lui $at,<hiconstant>
7597 addi $at,$at,<loconstant>
7598 add $tempreg,$tempreg,$at
7600 If we have NewABI, and we know it's a local symbol, we want
7601 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
7602 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
7603 otherwise we have to resort to GOT_HI16/GOT_LO16. */
7605 relax_start (offset_expr
.X_add_symbol
);
7607 expr1
.X_add_number
= offset_expr
.X_add_number
;
7608 offset_expr
.X_add_number
= 0;
7610 if (expr1
.X_add_number
== 0 && breg
== 0
7611 && (call
|| tempreg
== PIC_CALL_REG
))
7613 lui_reloc_type
= (int) BFD_RELOC_MIPS_CALL_HI16
;
7614 lw_reloc_type
= (int) BFD_RELOC_MIPS_CALL_LO16
;
7616 macro_build (&offset_expr
, "lui", LUI_FMT
, tempreg
, lui_reloc_type
);
7617 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
7618 tempreg
, tempreg
, mips_gp_register
);
7619 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
7620 tempreg
, lw_reloc_type
, tempreg
);
7622 if (expr1
.X_add_number
== 0)
7624 else if (expr1
.X_add_number
>= -0x8000
7625 && expr1
.X_add_number
< 0x8000)
7627 macro_build (&expr1
, ADDRESS_ADDI_INSN
, "t,r,j",
7628 tempreg
, tempreg
, BFD_RELOC_LO16
);
7630 else if (IS_SEXT_32BIT_NUM (expr1
.X_add_number
+ 0x8000))
7632 /* If we are going to add in a base register, and the
7633 target register and the base register are the same,
7634 then we are using AT as a temporary register. Since
7635 we want to load the constant into AT, we add our
7636 current AT (from the global offset table) and the
7637 register into the register now, and pretend we were
7638 not using a base register. */
7643 gas_assert (tempreg
== AT
);
7644 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
7650 load_register (AT
, &expr1
, HAVE_64BIT_ADDRESSES
);
7651 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", dreg
, dreg
, AT
);
7656 as_bad (_("PIC code offset overflow (max 32 signed bits)"));
7659 offset_expr
.X_add_number
= expr1
.X_add_number
;
7660 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
7661 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
7662 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j", tempreg
,
7663 tempreg
, BFD_RELOC_MIPS_GOT_OFST
);
7666 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
7667 treg
, tempreg
, breg
);
7677 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", treg
, tempreg
, breg
);
7681 gas_assert (!mips_opts
.micromips
);
7683 unsigned long temp
= (treg
<< 16) | (0x01);
7684 macro_build (NULL
, "c2", "C", temp
);
7689 gas_assert (!mips_opts
.micromips
);
7691 unsigned long temp
= (0x02);
7692 macro_build (NULL
, "c2", "C", temp
);
7697 gas_assert (!mips_opts
.micromips
);
7699 unsigned long temp
= (treg
<< 16) | (0x02);
7700 macro_build (NULL
, "c2", "C", temp
);
7705 gas_assert (!mips_opts
.micromips
);
7706 macro_build (NULL
, "c2", "C", 3);
7710 gas_assert (!mips_opts
.micromips
);
7712 unsigned long temp
= (treg
<< 16) | 0x03;
7713 macro_build (NULL
, "c2", "C", temp
);
7718 /* The j instruction may not be used in PIC code, since it
7719 requires an absolute address. We convert it to a b
7721 if (mips_pic
== NO_PIC
)
7722 macro_build (&offset_expr
, "j", "a");
7724 macro_build (&offset_expr
, "b", "p");
7727 /* The jal instructions must be handled as macros because when
7728 generating PIC code they expand to multi-instruction
7729 sequences. Normally they are simple instructions. */
7734 gas_assert (mips_opts
.micromips
);
7742 if (mips_pic
== NO_PIC
)
7744 s
= jals
? "jalrs" : "jalr";
7745 if (mips_opts
.micromips
&& dreg
== RA
)
7746 macro_build (NULL
, s
, "mj", sreg
);
7748 macro_build (NULL
, s
, JALR_FMT
, dreg
, sreg
);
7752 int cprestore
= (mips_pic
== SVR4_PIC
&& !HAVE_NEWABI
7753 && mips_cprestore_offset
>= 0);
7755 if (sreg
!= PIC_CALL_REG
)
7756 as_warn (_("MIPS PIC call to register other than $25"));
7758 s
= (mips_opts
.micromips
&& (!mips_opts
.noreorder
|| cprestore
)
7759 ? "jalrs" : "jalr");
7760 if (mips_opts
.micromips
&& dreg
== RA
)
7761 macro_build (NULL
, s
, "mj", sreg
);
7763 macro_build (NULL
, s
, JALR_FMT
, dreg
, sreg
);
7764 if (mips_pic
== SVR4_PIC
&& !HAVE_NEWABI
)
7766 if (mips_cprestore_offset
< 0)
7767 as_warn (_("No .cprestore pseudo-op used in PIC code"));
7770 if (!mips_frame_reg_valid
)
7772 as_warn (_("No .frame pseudo-op used in PIC code"));
7773 /* Quiet this warning. */
7774 mips_frame_reg_valid
= 1;
7776 if (!mips_cprestore_valid
)
7778 as_warn (_("No .cprestore pseudo-op used in PIC code"));
7779 /* Quiet this warning. */
7780 mips_cprestore_valid
= 1;
7782 if (mips_opts
.noreorder
)
7783 macro_build (NULL
, "nop", "");
7784 expr1
.X_add_number
= mips_cprestore_offset
;
7785 macro_build_ldst_constoffset (&expr1
, ADDRESS_LOAD_INSN
,
7788 HAVE_64BIT_ADDRESSES
);
7796 gas_assert (mips_opts
.micromips
);
7800 if (mips_pic
== NO_PIC
)
7801 macro_build (&offset_expr
, jals
? "jals" : "jal", "a");
7802 else if (mips_pic
== SVR4_PIC
)
7804 /* If this is a reference to an external symbol, and we are
7805 using a small GOT, we want
7806 lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
7810 lw $gp,cprestore($sp)
7811 The cprestore value is set using the .cprestore
7812 pseudo-op. If we are using a big GOT, we want
7813 lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16)
7815 lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16)
7819 lw $gp,cprestore($sp)
7820 If the symbol is not external, we want
7821 lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7823 addiu $25,$25,<sym> (BFD_RELOC_LO16)
7826 lw $gp,cprestore($sp)
7828 For NewABI, we use the same CALL16 or CALL_HI16/CALL_LO16
7829 sequences above, minus nops, unless the symbol is local,
7830 which enables us to use GOT_PAGE/GOT_OFST (big got) or
7836 relax_start (offset_expr
.X_add_symbol
);
7837 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
7838 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL16
,
7841 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
7842 PIC_CALL_REG
, BFD_RELOC_MIPS_GOT_DISP
,
7848 relax_start (offset_expr
.X_add_symbol
);
7849 macro_build (&offset_expr
, "lui", LUI_FMT
, PIC_CALL_REG
,
7850 BFD_RELOC_MIPS_CALL_HI16
);
7851 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", PIC_CALL_REG
,
7852 PIC_CALL_REG
, mips_gp_register
);
7853 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
7854 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL_LO16
,
7857 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
7858 PIC_CALL_REG
, BFD_RELOC_MIPS_GOT_PAGE
,
7860 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
7861 PIC_CALL_REG
, PIC_CALL_REG
,
7862 BFD_RELOC_MIPS_GOT_OFST
);
7866 macro_build_jalr (&offset_expr
, 0);
7870 relax_start (offset_expr
.X_add_symbol
);
7873 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
7874 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL16
,
7883 gpdelay
= reg_needs_delay (mips_gp_register
);
7884 macro_build (&offset_expr
, "lui", LUI_FMT
, PIC_CALL_REG
,
7885 BFD_RELOC_MIPS_CALL_HI16
);
7886 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", PIC_CALL_REG
,
7887 PIC_CALL_REG
, mips_gp_register
);
7888 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
7889 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL_LO16
,
7894 macro_build (NULL
, "nop", "");
7896 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
7897 PIC_CALL_REG
, BFD_RELOC_MIPS_GOT16
,
7900 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
7901 PIC_CALL_REG
, PIC_CALL_REG
, BFD_RELOC_LO16
);
7903 macro_build_jalr (&offset_expr
, mips_cprestore_offset
>= 0);
7905 if (mips_cprestore_offset
< 0)
7906 as_warn (_("No .cprestore pseudo-op used in PIC code"));
7909 if (!mips_frame_reg_valid
)
7911 as_warn (_("No .frame pseudo-op used in PIC code"));
7912 /* Quiet this warning. */
7913 mips_frame_reg_valid
= 1;
7915 if (!mips_cprestore_valid
)
7917 as_warn (_("No .cprestore pseudo-op used in PIC code"));
7918 /* Quiet this warning. */
7919 mips_cprestore_valid
= 1;
7921 if (mips_opts
.noreorder
)
7922 macro_build (NULL
, "nop", "");
7923 expr1
.X_add_number
= mips_cprestore_offset
;
7924 macro_build_ldst_constoffset (&expr1
, ADDRESS_LOAD_INSN
,
7927 HAVE_64BIT_ADDRESSES
);
7931 else if (mips_pic
== VXWORKS_PIC
)
7932 as_bad (_("Non-PIC jump used in PIC library"));
7942 treg
= EXTRACT_OPERAND (mips_opts
.micromips
, 3BITPOS
, *ip
);
7950 treg
= EXTRACT_OPERAND (mips_opts
.micromips
, 3BITPOS
, *ip
);
7981 gas_assert (!mips_opts
.micromips
);
7984 /* Itbl support may require additional care here. */
7991 /* Itbl support may require additional care here. */
7999 off12
= mips_opts
.micromips
;
8000 /* Itbl support may require additional care here. */
8005 gas_assert (!mips_opts
.micromips
);
8008 /* Itbl support may require additional care here. */
8016 off12
= mips_opts
.micromips
;
8023 off12
= mips_opts
.micromips
;
8029 /* Itbl support may require additional care here. */
8037 off12
= mips_opts
.micromips
;
8038 /* Itbl support may require additional care here. */
8045 /* Itbl support may require additional care here. */
8053 off12
= mips_opts
.micromips
;
8060 off12
= mips_opts
.micromips
;
8067 off12
= mips_opts
.micromips
;
8074 off12
= mips_opts
.micromips
;
8081 off12
= mips_opts
.micromips
;
8086 gas_assert (mips_opts
.micromips
);
8095 gas_assert (mips_opts
.micromips
);
8104 gas_assert (mips_opts
.micromips
);
8112 gas_assert (mips_opts
.micromips
);
8119 if (breg
== treg
+ lp
)
8122 tempreg
= treg
+ lp
;
8142 gas_assert (!mips_opts
.micromips
);
8145 /* Itbl support may require additional care here. */
8152 /* Itbl support may require additional care here. */
8160 off12
= mips_opts
.micromips
;
8161 /* Itbl support may require additional care here. */
8166 gas_assert (!mips_opts
.micromips
);
8169 /* Itbl support may require additional care here. */
8177 off12
= mips_opts
.micromips
;
8184 off12
= mips_opts
.micromips
;
8191 off12
= mips_opts
.micromips
;
8198 off12
= mips_opts
.micromips
;
8204 fmt
= mips_opts
.micromips
? "k,~(b)" : "k,o(b)";
8205 off12
= mips_opts
.micromips
;
8211 fmt
= !mips_opts
.micromips
? "k,o(b)" : "k,~(b)";
8212 off12
= mips_opts
.micromips
;
8219 /* Itbl support may require additional care here. */
8226 off12
= mips_opts
.micromips
;
8227 /* Itbl support may require additional care here. */
8232 gas_assert (!mips_opts
.micromips
);
8235 /* Itbl support may require additional care here. */
8243 off12
= mips_opts
.micromips
;
8250 off12
= mips_opts
.micromips
;
8255 gas_assert (mips_opts
.micromips
);
8263 gas_assert (mips_opts
.micromips
);
8271 gas_assert (mips_opts
.micromips
);
8279 gas_assert (mips_opts
.micromips
);
8288 if (offset_expr
.X_op
!= O_constant
8289 && offset_expr
.X_op
!= O_symbol
)
8291 as_bad (_("Expression too complex"));
8292 offset_expr
.X_op
= O_constant
;
8295 if (HAVE_32BIT_ADDRESSES
8296 && !IS_SEXT_32BIT_NUM (offset_expr
.X_add_number
))
8300 sprintf_vma (value
, offset_expr
.X_add_number
);
8301 as_bad (_("Number (0x%s) larger than 32 bits"), value
);
8304 /* A constant expression in PIC code can be handled just as it
8305 is in non PIC code. */
8306 if (offset_expr
.X_op
== O_constant
)
8310 expr1
.X_add_number
= offset_expr
.X_add_number
;
8311 normalize_address_expr (&expr1
);
8312 if (!off12
&& !IS_SEXT_16BIT_NUM (expr1
.X_add_number
))
8314 expr1
.X_add_number
= ((expr1
.X_add_number
+ 0x8000)
8315 & ~(bfd_vma
) 0xffff);
8318 else if (off12
&& !IS_SEXT_12BIT_NUM (expr1
.X_add_number
))
8320 expr1
.X_add_number
= ((expr1
.X_add_number
+ 0x800)
8321 & ~(bfd_vma
) 0xfff);
8326 load_register (tempreg
, &expr1
, HAVE_64BIT_ADDRESSES
);
8328 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
8329 tempreg
, tempreg
, breg
);
8334 if (offset_expr
.X_add_number
== 0)
8337 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
,
8338 "t,r,j", tempreg
, breg
, BFD_RELOC_LO16
);
8339 macro_build (NULL
, s
, fmt
, treg
, tempreg
);
8342 macro_build (&offset_expr
, s
, fmt
, treg
, BFD_RELOC_LO16
, breg
);
8344 macro_build (NULL
, s
, fmt
,
8345 treg
, (unsigned long) offset_expr
.X_add_number
, breg
);
8347 else if (off12
|| off0
)
8349 /* A 12-bit or 0-bit offset field is too narrow to be used
8350 for a low-part relocation, so load the whole address into
8351 the auxillary register. In the case of "A(b)" addresses,
8352 we first load absolute address "A" into the register and
8353 then add base register "b". In the case of "o(b)" addresses,
8354 we simply need to add 16-bit offset "o" to base register "b", and
8355 offset_reloc already contains the relocations associated
8359 load_address (tempreg
, &offset_expr
, &used_at
);
8361 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
8362 tempreg
, tempreg
, breg
);
8365 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
8367 offset_reloc
[0], offset_reloc
[1], offset_reloc
[2]);
8368 expr1
.X_add_number
= 0;
8370 macro_build (NULL
, s
, fmt
, treg
, tempreg
);
8372 macro_build (NULL
, s
, fmt
,
8373 treg
, (unsigned long) expr1
.X_add_number
, tempreg
);
8375 else if (mips_pic
== NO_PIC
)
8377 /* If this is a reference to a GP relative symbol, and there
8378 is no base register, we want
8379 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
8380 Otherwise, if there is no base register, we want
8381 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
8382 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
8383 If we have a constant, we need two instructions anyhow,
8384 so we always use the latter form.
8386 If we have a base register, and this is a reference to a
8387 GP relative symbol, we want
8388 addu $tempreg,$breg,$gp
8389 <op> $treg,<sym>($tempreg) (BFD_RELOC_GPREL16)
8391 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
8392 addu $tempreg,$tempreg,$breg
8393 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
8394 With a constant we always use the latter case.
8396 With 64bit address space and no base register and $at usable,
8398 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
8399 lui $at,<sym> (BFD_RELOC_HI16_S)
8400 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
8403 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
8404 If we have a base register, we want
8405 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
8406 lui $at,<sym> (BFD_RELOC_HI16_S)
8407 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
8411 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
8413 Without $at we can't generate the optimal path for superscalar
8414 processors here since this would require two temporary registers.
8415 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
8416 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
8418 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
8420 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
8421 If we have a base register, we want
8422 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
8423 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
8425 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
8427 daddu $tempreg,$tempreg,$breg
8428 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
8430 For GP relative symbols in 64bit address space we can use
8431 the same sequence as in 32bit address space. */
8432 if (HAVE_64BIT_SYMBOLS
)
8434 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
8435 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
8437 relax_start (offset_expr
.X_add_symbol
);
8440 macro_build (&offset_expr
, s
, fmt
, treg
,
8441 BFD_RELOC_GPREL16
, mips_gp_register
);
8445 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
8446 tempreg
, breg
, mips_gp_register
);
8447 macro_build (&offset_expr
, s
, fmt
, treg
,
8448 BFD_RELOC_GPREL16
, tempreg
);
8453 if (used_at
== 0 && mips_opts
.at
)
8455 macro_build (&offset_expr
, "lui", LUI_FMT
, tempreg
,
8456 BFD_RELOC_MIPS_HIGHEST
);
8457 macro_build (&offset_expr
, "lui", LUI_FMT
, AT
,
8459 macro_build (&offset_expr
, "daddiu", "t,r,j", tempreg
,
8460 tempreg
, BFD_RELOC_MIPS_HIGHER
);
8462 macro_build (NULL
, "daddu", "d,v,t", AT
, AT
, breg
);
8463 macro_build (NULL
, "dsll32", SHFT_FMT
, tempreg
, tempreg
, 0);
8464 macro_build (NULL
, "daddu", "d,v,t", tempreg
, tempreg
, AT
);
8465 macro_build (&offset_expr
, s
, fmt
, treg
, BFD_RELOC_LO16
,
8471 macro_build (&offset_expr
, "lui", LUI_FMT
, tempreg
,
8472 BFD_RELOC_MIPS_HIGHEST
);
8473 macro_build (&offset_expr
, "daddiu", "t,r,j", tempreg
,
8474 tempreg
, BFD_RELOC_MIPS_HIGHER
);
8475 macro_build (NULL
, "dsll", SHFT_FMT
, tempreg
, tempreg
, 16);
8476 macro_build (&offset_expr
, "daddiu", "t,r,j", tempreg
,
8477 tempreg
, BFD_RELOC_HI16_S
);
8478 macro_build (NULL
, "dsll", SHFT_FMT
, tempreg
, tempreg
, 16);
8480 macro_build (NULL
, "daddu", "d,v,t",
8481 tempreg
, tempreg
, breg
);
8482 macro_build (&offset_expr
, s
, fmt
, treg
,
8483 BFD_RELOC_LO16
, tempreg
);
8486 if (mips_relax
.sequence
)
8493 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
8494 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
8496 relax_start (offset_expr
.X_add_symbol
);
8497 macro_build (&offset_expr
, s
, fmt
, treg
, BFD_RELOC_GPREL16
,
8501 macro_build_lui (&offset_expr
, tempreg
);
8502 macro_build (&offset_expr
, s
, fmt
, treg
,
8503 BFD_RELOC_LO16
, tempreg
);
8504 if (mips_relax
.sequence
)
8509 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
8510 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
8512 relax_start (offset_expr
.X_add_symbol
);
8513 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
8514 tempreg
, breg
, mips_gp_register
);
8515 macro_build (&offset_expr
, s
, fmt
, treg
,
8516 BFD_RELOC_GPREL16
, tempreg
);
8519 macro_build_lui (&offset_expr
, tempreg
);
8520 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
8521 tempreg
, tempreg
, breg
);
8522 macro_build (&offset_expr
, s
, fmt
, treg
,
8523 BFD_RELOC_LO16
, tempreg
);
8524 if (mips_relax
.sequence
)
8528 else if (!mips_big_got
)
8530 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT16
;
8532 /* If this is a reference to an external symbol, we want
8533 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
8535 <op> $treg,0($tempreg)
8537 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
8539 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
8540 <op> $treg,0($tempreg)
8543 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
8544 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST)
8546 If there is a base register, we add it to $tempreg before
8547 the <op>. If there is a constant, we stick it in the
8548 <op> instruction. We don't handle constants larger than
8549 16 bits, because we have no way to load the upper 16 bits
8550 (actually, we could handle them for the subset of cases
8551 in which we are not using $at). */
8552 gas_assert (offset_expr
.X_op
== O_symbol
);
8555 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
8556 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
8558 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
8559 tempreg
, tempreg
, breg
);
8560 macro_build (&offset_expr
, s
, fmt
, treg
,
8561 BFD_RELOC_MIPS_GOT_OFST
, tempreg
);
8564 expr1
.X_add_number
= offset_expr
.X_add_number
;
8565 offset_expr
.X_add_number
= 0;
8566 if (expr1
.X_add_number
< -0x8000
8567 || expr1
.X_add_number
>= 0x8000)
8568 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
8569 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
8570 lw_reloc_type
, mips_gp_register
);
8572 relax_start (offset_expr
.X_add_symbol
);
8574 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j", tempreg
,
8575 tempreg
, BFD_RELOC_LO16
);
8578 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
8579 tempreg
, tempreg
, breg
);
8580 macro_build (&expr1
, s
, fmt
, treg
, BFD_RELOC_LO16
, tempreg
);
8582 else if (mips_big_got
&& !HAVE_NEWABI
)
8586 /* If this is a reference to an external symbol, we want
8587 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
8588 addu $tempreg,$tempreg,$gp
8589 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
8590 <op> $treg,0($tempreg)
8592 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
8594 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
8595 <op> $treg,0($tempreg)
8596 If there is a base register, we add it to $tempreg before
8597 the <op>. If there is a constant, we stick it in the
8598 <op> instruction. We don't handle constants larger than
8599 16 bits, because we have no way to load the upper 16 bits
8600 (actually, we could handle them for the subset of cases
8601 in which we are not using $at). */
8602 gas_assert (offset_expr
.X_op
== O_symbol
);
8603 expr1
.X_add_number
= offset_expr
.X_add_number
;
8604 offset_expr
.X_add_number
= 0;
8605 if (expr1
.X_add_number
< -0x8000
8606 || expr1
.X_add_number
>= 0x8000)
8607 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
8608 gpdelay
= reg_needs_delay (mips_gp_register
);
8609 relax_start (offset_expr
.X_add_symbol
);
8610 macro_build (&offset_expr
, "lui", LUI_FMT
, tempreg
,
8611 BFD_RELOC_MIPS_GOT_HI16
);
8612 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", tempreg
, tempreg
,
8614 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
8615 BFD_RELOC_MIPS_GOT_LO16
, tempreg
);
8618 macro_build (NULL
, "nop", "");
8619 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
8620 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
8622 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j", tempreg
,
8623 tempreg
, BFD_RELOC_LO16
);
8627 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
8628 tempreg
, tempreg
, breg
);
8629 macro_build (&expr1
, s
, fmt
, treg
, BFD_RELOC_LO16
, tempreg
);
8631 else if (mips_big_got
&& HAVE_NEWABI
)
8633 /* If this is a reference to an external symbol, we want
8634 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
8635 add $tempreg,$tempreg,$gp
8636 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
8637 <op> $treg,<ofst>($tempreg)
8638 Otherwise, for local symbols, we want:
8639 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
8640 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST) */
8641 gas_assert (offset_expr
.X_op
== O_symbol
);
8642 expr1
.X_add_number
= offset_expr
.X_add_number
;
8643 offset_expr
.X_add_number
= 0;
8644 if (expr1
.X_add_number
< -0x8000
8645 || expr1
.X_add_number
>= 0x8000)
8646 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
8647 relax_start (offset_expr
.X_add_symbol
);
8648 macro_build (&offset_expr
, "lui", LUI_FMT
, tempreg
,
8649 BFD_RELOC_MIPS_GOT_HI16
);
8650 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", tempreg
, tempreg
,
8652 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
8653 BFD_RELOC_MIPS_GOT_LO16
, tempreg
);
8655 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
8656 tempreg
, tempreg
, breg
);
8657 macro_build (&expr1
, s
, fmt
, treg
, BFD_RELOC_LO16
, tempreg
);
8660 offset_expr
.X_add_number
= expr1
.X_add_number
;
8661 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
8662 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
8664 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
8665 tempreg
, tempreg
, breg
);
8666 macro_build (&offset_expr
, s
, fmt
, treg
,
8667 BFD_RELOC_MIPS_GOT_OFST
, tempreg
);
8677 load_register (treg
, &imm_expr
, 0);
8681 load_register (treg
, &imm_expr
, 1);
8685 if (imm_expr
.X_op
== O_constant
)
8688 load_register (AT
, &imm_expr
, 0);
8689 macro_build (NULL
, "mtc1", "t,G", AT
, treg
);
8694 gas_assert (offset_expr
.X_op
== O_symbol
8695 && strcmp (segment_name (S_GET_SEGMENT
8696 (offset_expr
.X_add_symbol
)),
8698 && offset_expr
.X_add_number
== 0);
8699 macro_build (&offset_expr
, "lwc1", "T,o(b)", treg
,
8700 BFD_RELOC_MIPS_LITERAL
, mips_gp_register
);
8705 /* Check if we have a constant in IMM_EXPR. If the GPRs are 64 bits
8706 wide, IMM_EXPR is the entire value. Otherwise IMM_EXPR is the high
8707 order 32 bits of the value and the low order 32 bits are either
8708 zero or in OFFSET_EXPR. */
8709 if (imm_expr
.X_op
== O_constant
|| imm_expr
.X_op
== O_big
)
8711 if (HAVE_64BIT_GPRS
)
8712 load_register (treg
, &imm_expr
, 1);
8717 if (target_big_endian
)
8729 load_register (hreg
, &imm_expr
, 0);
8732 if (offset_expr
.X_op
== O_absent
)
8733 move_register (lreg
, 0);
8736 gas_assert (offset_expr
.X_op
== O_constant
);
8737 load_register (lreg
, &offset_expr
, 0);
8744 /* We know that sym is in the .rdata section. First we get the
8745 upper 16 bits of the address. */
8746 if (mips_pic
== NO_PIC
)
8748 macro_build_lui (&offset_expr
, AT
);
8753 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", AT
,
8754 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
8758 /* Now we load the register(s). */
8759 if (HAVE_64BIT_GPRS
)
8762 macro_build (&offset_expr
, "ld", "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
8767 macro_build (&offset_expr
, "lw", "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
8770 /* FIXME: How in the world do we deal with the possible
8772 offset_expr
.X_add_number
+= 4;
8773 macro_build (&offset_expr
, "lw", "t,o(b)",
8774 treg
+ 1, BFD_RELOC_LO16
, AT
);
8780 /* Check if we have a constant in IMM_EXPR. If the FPRs are 64 bits
8781 wide, IMM_EXPR is the entire value and the GPRs are known to be 64
8782 bits wide as well. Otherwise IMM_EXPR is the high order 32 bits of
8783 the value and the low order 32 bits are either zero or in
8785 if (imm_expr
.X_op
== O_constant
|| imm_expr
.X_op
== O_big
)
8788 load_register (AT
, &imm_expr
, HAVE_64BIT_FPRS
);
8789 if (HAVE_64BIT_FPRS
)
8791 gas_assert (HAVE_64BIT_GPRS
);
8792 macro_build (NULL
, "dmtc1", "t,S", AT
, treg
);
8796 macro_build (NULL
, "mtc1", "t,G", AT
, treg
+ 1);
8797 if (offset_expr
.X_op
== O_absent
)
8798 macro_build (NULL
, "mtc1", "t,G", 0, treg
);
8801 gas_assert (offset_expr
.X_op
== O_constant
);
8802 load_register (AT
, &offset_expr
, 0);
8803 macro_build (NULL
, "mtc1", "t,G", AT
, treg
);
8809 gas_assert (offset_expr
.X_op
== O_symbol
8810 && offset_expr
.X_add_number
== 0);
8811 s
= segment_name (S_GET_SEGMENT (offset_expr
.X_add_symbol
));
8812 if (strcmp (s
, ".lit8") == 0)
8814 if (mips_opts
.isa
!= ISA_MIPS1
|| mips_opts
.micromips
)
8816 macro_build (&offset_expr
, "ldc1", "T,o(b)", treg
,
8817 BFD_RELOC_MIPS_LITERAL
, mips_gp_register
);
8820 breg
= mips_gp_register
;
8821 r
= BFD_RELOC_MIPS_LITERAL
;
8826 gas_assert (strcmp (s
, RDATA_SECTION_NAME
) == 0);
8828 if (mips_pic
!= NO_PIC
)
8829 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", AT
,
8830 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
8833 /* FIXME: This won't work for a 64 bit address. */
8834 macro_build_lui (&offset_expr
, AT
);
8837 if (mips_opts
.isa
!= ISA_MIPS1
|| mips_opts
.micromips
)
8839 macro_build (&offset_expr
, "ldc1", "T,o(b)",
8840 treg
, BFD_RELOC_LO16
, AT
);
8849 /* Even on a big endian machine $fn comes before $fn+1. We have
8850 to adjust when loading from memory. */
8853 gas_assert (!mips_opts
.micromips
);
8854 gas_assert (mips_opts
.isa
== ISA_MIPS1
);
8855 macro_build (&offset_expr
, "lwc1", "T,o(b)",
8856 target_big_endian
? treg
+ 1 : treg
, r
, breg
);
8857 /* FIXME: A possible overflow which I don't know how to deal
8859 offset_expr
.X_add_number
+= 4;
8860 macro_build (&offset_expr
, "lwc1", "T,o(b)",
8861 target_big_endian
? treg
: treg
+ 1, r
, breg
);
8865 gas_assert (!mips_opts
.micromips
);
8866 gas_assert (mips_opts
.isa
== ISA_MIPS1
);
8867 /* Even on a big endian machine $fn comes before $fn+1. We have
8868 to adjust when storing to memory. */
8869 macro_build (&offset_expr
, "swc1", "T,o(b)",
8870 target_big_endian
? treg
+ 1 : treg
, BFD_RELOC_LO16
, breg
);
8871 offset_expr
.X_add_number
+= 4;
8872 macro_build (&offset_expr
, "swc1", "T,o(b)",
8873 target_big_endian
? treg
: treg
+ 1, BFD_RELOC_LO16
, breg
);
8877 gas_assert (!mips_opts
.micromips
);
8879 * The MIPS assembler seems to check for X_add_number not
8880 * being double aligned and generating:
8883 * addiu at,at,%lo(foo+1)
8886 * But, the resulting address is the same after relocation so why
8887 * generate the extra instruction?
8889 /* Itbl support may require additional care here. */
8892 if (mips_opts
.isa
!= ISA_MIPS1
)
8901 gas_assert (!mips_opts
.micromips
);
8902 /* Itbl support may require additional care here. */
8905 if (mips_opts
.isa
!= ISA_MIPS1
)
8915 if (HAVE_64BIT_GPRS
)
8925 if (HAVE_64BIT_GPRS
)
8933 if (offset_expr
.X_op
!= O_symbol
8934 && offset_expr
.X_op
!= O_constant
)
8936 as_bad (_("Expression too complex"));
8937 offset_expr
.X_op
= O_constant
;
8940 if (HAVE_32BIT_ADDRESSES
8941 && !IS_SEXT_32BIT_NUM (offset_expr
.X_add_number
))
8945 sprintf_vma (value
, offset_expr
.X_add_number
);
8946 as_bad (_("Number (0x%s) larger than 32 bits"), value
);
8949 /* Even on a big endian machine $fn comes before $fn+1. We have
8950 to adjust when loading from memory. We set coproc if we must
8951 load $fn+1 first. */
8952 /* Itbl support may require additional care here. */
8953 if (!target_big_endian
)
8956 if (mips_pic
== NO_PIC
|| offset_expr
.X_op
== O_constant
)
8958 /* If this is a reference to a GP relative symbol, we want
8959 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
8960 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_GPREL16)
8961 If we have a base register, we use this
8963 <op> $treg,<sym>($at) (BFD_RELOC_GPREL16)
8964 <op> $treg+1,<sym>+4($at) (BFD_RELOC_GPREL16)
8965 If this is not a GP relative symbol, we want
8966 lui $at,<sym> (BFD_RELOC_HI16_S)
8967 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
8968 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
8969 If there is a base register, we add it to $at after the
8970 lui instruction. If there is a constant, we always use
8972 if (offset_expr
.X_op
== O_symbol
8973 && (valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
8974 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
8976 relax_start (offset_expr
.X_add_symbol
);
8979 tempreg
= mips_gp_register
;
8983 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
8984 AT
, breg
, mips_gp_register
);
8989 /* Itbl support may require additional care here. */
8990 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
+ 1 : treg
,
8991 BFD_RELOC_GPREL16
, tempreg
);
8992 offset_expr
.X_add_number
+= 4;
8994 /* Set mips_optimize to 2 to avoid inserting an
8996 hold_mips_optimize
= mips_optimize
;
8998 /* Itbl support may require additional care here. */
8999 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
: treg
+ 1,
9000 BFD_RELOC_GPREL16
, tempreg
);
9001 mips_optimize
= hold_mips_optimize
;
9005 offset_expr
.X_add_number
-= 4;
9008 macro_build_lui (&offset_expr
, AT
);
9010 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
9011 /* Itbl support may require additional care here. */
9012 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
+ 1 : treg
,
9013 BFD_RELOC_LO16
, AT
);
9014 /* FIXME: How do we handle overflow here? */
9015 offset_expr
.X_add_number
+= 4;
9016 /* Itbl support may require additional care here. */
9017 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
: treg
+ 1,
9018 BFD_RELOC_LO16
, AT
);
9019 if (mips_relax
.sequence
)
9022 else if (!mips_big_got
)
9024 /* If this is a reference to an external symbol, we want
9025 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
9030 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
9032 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
9033 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
9034 If there is a base register we add it to $at before the
9035 lwc1 instructions. If there is a constant we include it
9036 in the lwc1 instructions. */
9038 expr1
.X_add_number
= offset_expr
.X_add_number
;
9039 if (expr1
.X_add_number
< -0x8000
9040 || expr1
.X_add_number
>= 0x8000 - 4)
9041 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
9042 load_got_offset (AT
, &offset_expr
);
9045 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
9047 /* Set mips_optimize to 2 to avoid inserting an undesired
9049 hold_mips_optimize
= mips_optimize
;
9052 /* Itbl support may require additional care here. */
9053 relax_start (offset_expr
.X_add_symbol
);
9054 macro_build (&expr1
, s
, fmt
, coproc
? treg
+ 1 : treg
,
9055 BFD_RELOC_LO16
, AT
);
9056 expr1
.X_add_number
+= 4;
9057 macro_build (&expr1
, s
, fmt
, coproc
? treg
: treg
+ 1,
9058 BFD_RELOC_LO16
, AT
);
9060 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
+ 1 : treg
,
9061 BFD_RELOC_LO16
, AT
);
9062 offset_expr
.X_add_number
+= 4;
9063 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
: treg
+ 1,
9064 BFD_RELOC_LO16
, AT
);
9067 mips_optimize
= hold_mips_optimize
;
9069 else if (mips_big_got
)
9073 /* If this is a reference to an external symbol, we want
9074 lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16)
9076 lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16)
9081 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
9083 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
9084 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
9085 If there is a base register we add it to $at before the
9086 lwc1 instructions. If there is a constant we include it
9087 in the lwc1 instructions. */
9089 expr1
.X_add_number
= offset_expr
.X_add_number
;
9090 offset_expr
.X_add_number
= 0;
9091 if (expr1
.X_add_number
< -0x8000
9092 || expr1
.X_add_number
>= 0x8000 - 4)
9093 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
9094 gpdelay
= reg_needs_delay (mips_gp_register
);
9095 relax_start (offset_expr
.X_add_symbol
);
9096 macro_build (&offset_expr
, "lui", LUI_FMT
,
9097 AT
, BFD_RELOC_MIPS_GOT_HI16
);
9098 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
9099 AT
, AT
, mips_gp_register
);
9100 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
9101 AT
, BFD_RELOC_MIPS_GOT_LO16
, AT
);
9104 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
9105 /* Itbl support may require additional care here. */
9106 macro_build (&expr1
, s
, fmt
, coproc
? treg
+ 1 : treg
,
9107 BFD_RELOC_LO16
, AT
);
9108 expr1
.X_add_number
+= 4;
9110 /* Set mips_optimize to 2 to avoid inserting an undesired
9112 hold_mips_optimize
= mips_optimize
;
9114 /* Itbl support may require additional care here. */
9115 macro_build (&expr1
, s
, fmt
, coproc
? treg
: treg
+ 1,
9116 BFD_RELOC_LO16
, AT
);
9117 mips_optimize
= hold_mips_optimize
;
9118 expr1
.X_add_number
-= 4;
9121 offset_expr
.X_add_number
= expr1
.X_add_number
;
9123 macro_build (NULL
, "nop", "");
9124 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", AT
,
9125 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
9128 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
9129 /* Itbl support may require additional care here. */
9130 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
+ 1 : treg
,
9131 BFD_RELOC_LO16
, AT
);
9132 offset_expr
.X_add_number
+= 4;
9134 /* Set mips_optimize to 2 to avoid inserting an undesired
9136 hold_mips_optimize
= mips_optimize
;
9138 /* Itbl support may require additional care here. */
9139 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
: treg
+ 1,
9140 BFD_RELOC_LO16
, AT
);
9141 mips_optimize
= hold_mips_optimize
;
9150 s
= HAVE_64BIT_GPRS
? "ld" : "lw";
9153 s
= HAVE_64BIT_GPRS
? "sd" : "sw";
9155 macro_build (&offset_expr
, s
, "t,o(b)", treg
,
9156 -1, offset_reloc
[0], offset_reloc
[1], offset_reloc
[2],
9158 if (!HAVE_64BIT_GPRS
)
9160 offset_expr
.X_add_number
+= 4;
9161 macro_build (&offset_expr
, s
, "t,o(b)", treg
+ 1,
9162 -1, offset_reloc
[0], offset_reloc
[1], offset_reloc
[2],
9183 /* New code added to support COPZ instructions.
9184 This code builds table entries out of the macros in mip_opcodes.
9185 R4000 uses interlocks to handle coproc delays.
9186 Other chips (like the R3000) require nops to be inserted for delays.
9188 FIXME: Currently, we require that the user handle delays.
9189 In order to fill delay slots for non-interlocked chips,
9190 we must have a way to specify delays based on the coprocessor.
9191 Eg. 4 cycles if load coproc reg from memory, 1 if in cache, etc.
9192 What are the side-effects of the cop instruction?
9193 What cache support might we have and what are its effects?
9194 Both coprocessor & memory require delays. how long???
9195 What registers are read/set/modified?
9197 If an itbl is provided to interpret cop instructions,
9198 this knowledge can be encoded in the itbl spec. */
9212 gas_assert (!mips_opts
.micromips
);
9213 /* For now we just do C (same as Cz). The parameter will be
9214 stored in insn_opcode by mips_ip. */
9215 macro_build (NULL
, s
, "C", ip
->insn_opcode
);
9219 move_register (dreg
, sreg
);
9225 macro_build (NULL
, dbl
? "dmultu" : "multu", "s,t", sreg
, treg
);
9226 macro_build (NULL
, "mflo", MFHL_FMT
, dreg
);
9232 /* The MIPS assembler some times generates shifts and adds. I'm
9233 not trying to be that fancy. GCC should do this for us
9236 load_register (AT
, &imm_expr
, dbl
);
9237 macro_build (NULL
, dbl
? "dmult" : "mult", "s,t", sreg
, AT
);
9238 macro_build (NULL
, "mflo", MFHL_FMT
, dreg
);
9254 load_register (AT
, &imm_expr
, dbl
);
9255 macro_build (NULL
, dbl
? "dmult" : "mult", "s,t", sreg
, imm
? AT
: treg
);
9256 macro_build (NULL
, "mflo", MFHL_FMT
, dreg
);
9257 macro_build (NULL
, dbl
? "dsra32" : "sra", SHFT_FMT
, dreg
, dreg
, RA
);
9258 macro_build (NULL
, "mfhi", MFHL_FMT
, AT
);
9260 macro_build (NULL
, "tne", TRAP_FMT
, dreg
, AT
, 6);
9263 if (mips_opts
.micromips
)
9264 micromips_label_expr (&label_expr
);
9266 label_expr
.X_add_number
= 8;
9267 macro_build (&label_expr
, "beq", "s,t,p", dreg
, AT
);
9268 macro_build (NULL
, "nop", "");
9269 macro_build (NULL
, "break", BRK_FMT
, 6);
9270 if (mips_opts
.micromips
)
9271 micromips_add_label ();
9274 macro_build (NULL
, "mflo", MFHL_FMT
, dreg
);
9290 load_register (AT
, &imm_expr
, dbl
);
9291 macro_build (NULL
, dbl
? "dmultu" : "multu", "s,t",
9292 sreg
, imm
? AT
: treg
);
9293 macro_build (NULL
, "mfhi", MFHL_FMT
, AT
);
9294 macro_build (NULL
, "mflo", MFHL_FMT
, dreg
);
9296 macro_build (NULL
, "tne", TRAP_FMT
, AT
, ZERO
, 6);
9299 if (mips_opts
.micromips
)
9300 micromips_label_expr (&label_expr
);
9302 label_expr
.X_add_number
= 8;
9303 macro_build (&label_expr
, "beq", "s,t,p", AT
, ZERO
);
9304 macro_build (NULL
, "nop", "");
9305 macro_build (NULL
, "break", BRK_FMT
, 6);
9306 if (mips_opts
.micromips
)
9307 micromips_add_label ();
9313 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
9324 macro_build (NULL
, "dnegu", "d,w", tempreg
, treg
);
9325 macro_build (NULL
, "drorv", "d,t,s", dreg
, sreg
, tempreg
);
9329 macro_build (NULL
, "dsubu", "d,v,t", AT
, ZERO
, treg
);
9330 macro_build (NULL
, "dsrlv", "d,t,s", AT
, sreg
, AT
);
9331 macro_build (NULL
, "dsllv", "d,t,s", dreg
, sreg
, treg
);
9332 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
9336 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
9347 macro_build (NULL
, "negu", "d,w", tempreg
, treg
);
9348 macro_build (NULL
, "rorv", "d,t,s", dreg
, sreg
, tempreg
);
9352 macro_build (NULL
, "subu", "d,v,t", AT
, ZERO
, treg
);
9353 macro_build (NULL
, "srlv", "d,t,s", AT
, sreg
, AT
);
9354 macro_build (NULL
, "sllv", "d,t,s", dreg
, sreg
, treg
);
9355 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
9364 if (imm_expr
.X_op
!= O_constant
)
9365 as_bad (_("Improper rotate count"));
9366 rot
= imm_expr
.X_add_number
& 0x3f;
9367 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
9369 rot
= (64 - rot
) & 0x3f;
9371 macro_build (NULL
, "dror32", SHFT_FMT
, dreg
, sreg
, rot
- 32);
9373 macro_build (NULL
, "dror", SHFT_FMT
, dreg
, sreg
, rot
);
9378 macro_build (NULL
, "dsrl", SHFT_FMT
, dreg
, sreg
, 0);
9381 l
= (rot
< 0x20) ? "dsll" : "dsll32";
9382 rr
= ((0x40 - rot
) < 0x20) ? "dsrl" : "dsrl32";
9385 macro_build (NULL
, l
, SHFT_FMT
, AT
, sreg
, rot
);
9386 macro_build (NULL
, rr
, SHFT_FMT
, dreg
, sreg
, (0x20 - rot
) & 0x1f);
9387 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
9395 if (imm_expr
.X_op
!= O_constant
)
9396 as_bad (_("Improper rotate count"));
9397 rot
= imm_expr
.X_add_number
& 0x1f;
9398 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
9400 macro_build (NULL
, "ror", SHFT_FMT
, dreg
, sreg
, (32 - rot
) & 0x1f);
9405 macro_build (NULL
, "srl", SHFT_FMT
, dreg
, sreg
, 0);
9409 macro_build (NULL
, "sll", SHFT_FMT
, AT
, sreg
, rot
);
9410 macro_build (NULL
, "srl", SHFT_FMT
, dreg
, sreg
, (0x20 - rot
) & 0x1f);
9411 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
9416 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
9418 macro_build (NULL
, "drorv", "d,t,s", dreg
, sreg
, treg
);
9422 macro_build (NULL
, "dsubu", "d,v,t", AT
, ZERO
, treg
);
9423 macro_build (NULL
, "dsllv", "d,t,s", AT
, sreg
, AT
);
9424 macro_build (NULL
, "dsrlv", "d,t,s", dreg
, sreg
, treg
);
9425 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
9429 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
9431 macro_build (NULL
, "rorv", "d,t,s", dreg
, sreg
, treg
);
9435 macro_build (NULL
, "subu", "d,v,t", AT
, ZERO
, treg
);
9436 macro_build (NULL
, "sllv", "d,t,s", AT
, sreg
, AT
);
9437 macro_build (NULL
, "srlv", "d,t,s", dreg
, sreg
, treg
);
9438 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
9447 if (imm_expr
.X_op
!= O_constant
)
9448 as_bad (_("Improper rotate count"));
9449 rot
= imm_expr
.X_add_number
& 0x3f;
9450 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
9453 macro_build (NULL
, "dror32", SHFT_FMT
, dreg
, sreg
, rot
- 32);
9455 macro_build (NULL
, "dror", SHFT_FMT
, dreg
, sreg
, rot
);
9460 macro_build (NULL
, "dsrl", SHFT_FMT
, dreg
, sreg
, 0);
9463 rr
= (rot
< 0x20) ? "dsrl" : "dsrl32";
9464 l
= ((0x40 - rot
) < 0x20) ? "dsll" : "dsll32";
9467 macro_build (NULL
, rr
, SHFT_FMT
, AT
, sreg
, rot
);
9468 macro_build (NULL
, l
, SHFT_FMT
, dreg
, sreg
, (0x20 - rot
) & 0x1f);
9469 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
9477 if (imm_expr
.X_op
!= O_constant
)
9478 as_bad (_("Improper rotate count"));
9479 rot
= imm_expr
.X_add_number
& 0x1f;
9480 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
9482 macro_build (NULL
, "ror", SHFT_FMT
, dreg
, sreg
, rot
);
9487 macro_build (NULL
, "srl", SHFT_FMT
, dreg
, sreg
, 0);
9491 macro_build (NULL
, "srl", SHFT_FMT
, AT
, sreg
, rot
);
9492 macro_build (NULL
, "sll", SHFT_FMT
, dreg
, sreg
, (0x20 - rot
) & 0x1f);
9493 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
9499 macro_build (&expr1
, "sltiu", "t,r,j", dreg
, treg
, BFD_RELOC_LO16
);
9501 macro_build (&expr1
, "sltiu", "t,r,j", dreg
, sreg
, BFD_RELOC_LO16
);
9504 macro_build (NULL
, "xor", "d,v,t", dreg
, sreg
, treg
);
9505 macro_build (&expr1
, "sltiu", "t,r,j", dreg
, dreg
, BFD_RELOC_LO16
);
9510 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
9512 macro_build (&expr1
, "sltiu", "t,r,j", dreg
, sreg
, BFD_RELOC_LO16
);
9517 as_warn (_("Instruction %s: result is always false"),
9519 move_register (dreg
, 0);
9522 if (CPU_HAS_SEQ (mips_opts
.arch
)
9523 && -512 <= imm_expr
.X_add_number
9524 && imm_expr
.X_add_number
< 512)
9526 macro_build (NULL
, "seqi", "t,r,+Q", dreg
, sreg
,
9527 (int) imm_expr
.X_add_number
);
9530 if (imm_expr
.X_op
== O_constant
9531 && imm_expr
.X_add_number
>= 0
9532 && imm_expr
.X_add_number
< 0x10000)
9534 macro_build (&imm_expr
, "xori", "t,r,i", dreg
, sreg
, BFD_RELOC_LO16
);
9536 else if (imm_expr
.X_op
== O_constant
9537 && imm_expr
.X_add_number
> -0x8000
9538 && imm_expr
.X_add_number
< 0)
9540 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
9541 macro_build (&imm_expr
, HAVE_32BIT_GPRS
? "addiu" : "daddiu",
9542 "t,r,j", dreg
, sreg
, BFD_RELOC_LO16
);
9544 else if (CPU_HAS_SEQ (mips_opts
.arch
))
9547 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
9548 macro_build (NULL
, "seq", "d,v,t", dreg
, sreg
, AT
);
9553 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
9554 macro_build (NULL
, "xor", "d,v,t", dreg
, sreg
, AT
);
9557 macro_build (&expr1
, "sltiu", "t,r,j", dreg
, dreg
, BFD_RELOC_LO16
);
9560 case M_SGE
: /* sreg >= treg <==> not (sreg < treg) */
9566 macro_build (NULL
, s
, "d,v,t", dreg
, sreg
, treg
);
9567 macro_build (&expr1
, "xori", "t,r,i", dreg
, dreg
, BFD_RELOC_LO16
);
9570 case M_SGE_I
: /* sreg >= I <==> not (sreg < I) */
9572 if (imm_expr
.X_op
== O_constant
9573 && imm_expr
.X_add_number
>= -0x8000
9574 && imm_expr
.X_add_number
< 0x8000)
9576 macro_build (&imm_expr
, mask
== M_SGE_I
? "slti" : "sltiu", "t,r,j",
9577 dreg
, sreg
, BFD_RELOC_LO16
);
9581 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
9582 macro_build (NULL
, mask
== M_SGE_I
? "slt" : "sltu", "d,v,t",
9586 macro_build (&expr1
, "xori", "t,r,i", dreg
, dreg
, BFD_RELOC_LO16
);
9589 case M_SGT
: /* sreg > treg <==> treg < sreg */
9595 macro_build (NULL
, s
, "d,v,t", dreg
, treg
, sreg
);
9598 case M_SGT_I
: /* sreg > I <==> I < sreg */
9605 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
9606 macro_build (NULL
, s
, "d,v,t", dreg
, AT
, sreg
);
9609 case M_SLE
: /* sreg <= treg <==> treg >= sreg <==> not (treg < sreg) */
9615 macro_build (NULL
, s
, "d,v,t", dreg
, treg
, sreg
);
9616 macro_build (&expr1
, "xori", "t,r,i", dreg
, dreg
, BFD_RELOC_LO16
);
9619 case M_SLE_I
: /* sreg <= I <==> I >= sreg <==> not (I < sreg) */
9626 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
9627 macro_build (NULL
, s
, "d,v,t", dreg
, AT
, sreg
);
9628 macro_build (&expr1
, "xori", "t,r,i", dreg
, dreg
, BFD_RELOC_LO16
);
9632 if (imm_expr
.X_op
== O_constant
9633 && imm_expr
.X_add_number
>= -0x8000
9634 && imm_expr
.X_add_number
< 0x8000)
9636 macro_build (&imm_expr
, "slti", "t,r,j", dreg
, sreg
, BFD_RELOC_LO16
);
9640 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
9641 macro_build (NULL
, "slt", "d,v,t", dreg
, sreg
, AT
);
9645 if (imm_expr
.X_op
== O_constant
9646 && imm_expr
.X_add_number
>= -0x8000
9647 && imm_expr
.X_add_number
< 0x8000)
9649 macro_build (&imm_expr
, "sltiu", "t,r,j", dreg
, sreg
,
9654 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
9655 macro_build (NULL
, "sltu", "d,v,t", dreg
, sreg
, AT
);
9660 macro_build (NULL
, "sltu", "d,v,t", dreg
, 0, treg
);
9662 macro_build (NULL
, "sltu", "d,v,t", dreg
, 0, sreg
);
9665 macro_build (NULL
, "xor", "d,v,t", dreg
, sreg
, treg
);
9666 macro_build (NULL
, "sltu", "d,v,t", dreg
, 0, dreg
);
9671 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
9673 macro_build (NULL
, "sltu", "d,v,t", dreg
, 0, sreg
);
9678 as_warn (_("Instruction %s: result is always true"),
9680 macro_build (&expr1
, HAVE_32BIT_GPRS
? "addiu" : "daddiu", "t,r,j",
9681 dreg
, 0, BFD_RELOC_LO16
);
9684 if (CPU_HAS_SEQ (mips_opts
.arch
)
9685 && -512 <= imm_expr
.X_add_number
9686 && imm_expr
.X_add_number
< 512)
9688 macro_build (NULL
, "snei", "t,r,+Q", dreg
, sreg
,
9689 (int) imm_expr
.X_add_number
);
9692 if (imm_expr
.X_op
== O_constant
9693 && imm_expr
.X_add_number
>= 0
9694 && imm_expr
.X_add_number
< 0x10000)
9696 macro_build (&imm_expr
, "xori", "t,r,i", dreg
, sreg
, BFD_RELOC_LO16
);
9698 else if (imm_expr
.X_op
== O_constant
9699 && imm_expr
.X_add_number
> -0x8000
9700 && imm_expr
.X_add_number
< 0)
9702 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
9703 macro_build (&imm_expr
, HAVE_32BIT_GPRS
? "addiu" : "daddiu",
9704 "t,r,j", dreg
, sreg
, BFD_RELOC_LO16
);
9706 else if (CPU_HAS_SEQ (mips_opts
.arch
))
9709 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
9710 macro_build (NULL
, "sne", "d,v,t", dreg
, sreg
, AT
);
9715 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
9716 macro_build (NULL
, "xor", "d,v,t", dreg
, sreg
, AT
);
9719 macro_build (NULL
, "sltu", "d,v,t", dreg
, 0, dreg
);
9734 if (!mips_opts
.micromips
)
9736 if (imm_expr
.X_op
== O_constant
9737 && imm_expr
.X_add_number
> -0x200
9738 && imm_expr
.X_add_number
<= 0x200)
9740 macro_build (NULL
, s
, "t,r,.", dreg
, sreg
, -imm_expr
.X_add_number
);
9749 if (imm_expr
.X_op
== O_constant
9750 && imm_expr
.X_add_number
> -0x8000
9751 && imm_expr
.X_add_number
<= 0x8000)
9753 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
9754 macro_build (&imm_expr
, s
, "t,r,j", dreg
, sreg
, BFD_RELOC_LO16
);
9759 load_register (AT
, &imm_expr
, dbl
);
9760 macro_build (NULL
, s2
, "d,v,t", dreg
, sreg
, AT
);
9782 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
9783 macro_build (NULL
, s
, "s,t", sreg
, AT
);
9788 gas_assert (!mips_opts
.micromips
);
9789 gas_assert (mips_opts
.isa
== ISA_MIPS1
);
9791 sreg
= (ip
->insn_opcode
>> 11) & 0x1f; /* floating reg */
9792 dreg
= (ip
->insn_opcode
>> 06) & 0x1f; /* floating reg */
9795 * Is the double cfc1 instruction a bug in the mips assembler;
9796 * or is there a reason for it?
9799 macro_build (NULL
, "cfc1", "t,G", treg
, RA
);
9800 macro_build (NULL
, "cfc1", "t,G", treg
, RA
);
9801 macro_build (NULL
, "nop", "");
9802 expr1
.X_add_number
= 3;
9803 macro_build (&expr1
, "ori", "t,r,i", AT
, treg
, BFD_RELOC_LO16
);
9804 expr1
.X_add_number
= 2;
9805 macro_build (&expr1
, "xori", "t,r,i", AT
, AT
, BFD_RELOC_LO16
);
9806 macro_build (NULL
, "ctc1", "t,G", AT
, RA
);
9807 macro_build (NULL
, "nop", "");
9808 macro_build (NULL
, mask
== M_TRUNCWD
? "cvt.w.d" : "cvt.w.s", "D,S",
9810 macro_build (NULL
, "ctc1", "t,G", treg
, RA
);
9811 macro_build (NULL
, "nop", "");
9834 off12
= mips_opts
.micromips
;
9842 off12
= mips_opts
.micromips
;
9858 off12
= mips_opts
.micromips
;
9867 off12
= mips_opts
.micromips
;
9872 if (!ab
&& offset_expr
.X_add_number
>= 0x8000 - off
)
9873 as_bad (_("Operand overflow"));
9876 expr1
.X_add_number
= 0;
9881 load_address (tempreg
, ep
, &used_at
);
9883 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
9884 tempreg
, tempreg
, breg
);
9890 && (offset_expr
.X_op
!= O_constant
9891 || !IS_SEXT_12BIT_NUM (offset_expr
.X_add_number
)
9892 || !IS_SEXT_12BIT_NUM (offset_expr
.X_add_number
+ off
)))
9896 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", tempreg
, breg
,
9897 -1, offset_reloc
[0], offset_reloc
[1], offset_reloc
[2]);
9902 else if (!ust
&& treg
== breg
)
9913 if (!target_big_endian
)
9914 ep
->X_add_number
+= off
;
9916 macro_build (ep
, s
, "t,o(b)", tempreg
, BFD_RELOC_LO16
, breg
);
9918 macro_build (NULL
, s
, "t,~(b)",
9919 tempreg
, (unsigned long) ep
->X_add_number
, breg
);
9921 if (!target_big_endian
)
9922 ep
->X_add_number
-= off
;
9924 ep
->X_add_number
+= off
;
9926 macro_build (ep
, s2
, "t,o(b)", tempreg
, BFD_RELOC_LO16
, breg
);
9928 macro_build (NULL
, s2
, "t,~(b)",
9929 tempreg
, (unsigned long) ep
->X_add_number
, breg
);
9931 /* If necessary, move the result in tempreg to the final destination. */
9932 if (!ust
&& treg
!= tempreg
)
9934 /* Protect second load's delay slot. */
9936 move_register (treg
, tempreg
);
9942 if (target_big_endian
== ust
)
9943 ep
->X_add_number
+= off
;
9944 tempreg
= ust
|| ab
? treg
: AT
;
9945 macro_build (ep
, s
, "t,o(b)", tempreg
, BFD_RELOC_LO16
, breg
);
9947 /* For halfword transfers we need a temporary register to shuffle
9948 bytes. Unfortunately for M_USH_A we have none available before
9949 the next store as AT holds the base address. We deal with this
9950 case by clobbering TREG and then restoring it as with ULH. */
9951 tempreg
= ust
== ab
? treg
: AT
;
9953 macro_build (NULL
, "srl", SHFT_FMT
, tempreg
, treg
, 8);
9955 if (target_big_endian
== ust
)
9956 ep
->X_add_number
-= off
;
9958 ep
->X_add_number
+= off
;
9959 macro_build (ep
, s2
, "t,o(b)", tempreg
, BFD_RELOC_LO16
, breg
);
9961 /* For M_USH_A re-retrieve the LSB. */
9964 if (target_big_endian
)
9965 ep
->X_add_number
+= off
;
9967 ep
->X_add_number
-= off
;
9968 macro_build (&expr1
, "lbu", "t,o(b)", AT
, BFD_RELOC_LO16
, AT
);
9970 /* For ULH and M_USH_A OR the LSB in. */
9973 tempreg
= !ab
? AT
: treg
;
9974 macro_build (NULL
, "sll", SHFT_FMT
, tempreg
, tempreg
, 8);
9975 macro_build (NULL
, "or", "d,v,t", treg
, treg
, AT
);
9980 /* FIXME: Check if this is one of the itbl macros, since they
9981 are added dynamically. */
9982 as_bad (_("Macro %s not implemented yet"), ip
->insn_mo
->name
);
9985 if (!mips_opts
.at
&& used_at
)
9986 as_bad (_("Macro used $at after \".set noat\""));
9989 /* Implement macros in mips16 mode. */
9992 mips16_macro (struct mips_cl_insn
*ip
)
9995 int xreg
, yreg
, zreg
, tmp
;
9998 const char *s
, *s2
, *s3
;
10000 mask
= ip
->insn_mo
->mask
;
10002 xreg
= MIPS16_EXTRACT_OPERAND (RX
, *ip
);
10003 yreg
= MIPS16_EXTRACT_OPERAND (RY
, *ip
);
10004 zreg
= MIPS16_EXTRACT_OPERAND (RZ
, *ip
);
10006 expr1
.X_op
= O_constant
;
10007 expr1
.X_op_symbol
= NULL
;
10008 expr1
.X_add_symbol
= NULL
;
10009 expr1
.X_add_number
= 1;
10028 start_noreorder ();
10029 macro_build (NULL
, dbl
? "ddiv" : "div", "0,x,y", xreg
, yreg
);
10030 expr1
.X_add_number
= 2;
10031 macro_build (&expr1
, "bnez", "x,p", yreg
);
10032 macro_build (NULL
, "break", "6", 7);
10034 /* FIXME: The normal code checks for of -1 / -0x80000000 here,
10035 since that causes an overflow. We should do that as well,
10036 but I don't see how to do the comparisons without a temporary
10039 macro_build (NULL
, s
, "x", zreg
);
10058 start_noreorder ();
10059 macro_build (NULL
, s
, "0,x,y", xreg
, yreg
);
10060 expr1
.X_add_number
= 2;
10061 macro_build (&expr1
, "bnez", "x,p", yreg
);
10062 macro_build (NULL
, "break", "6", 7);
10064 macro_build (NULL
, s2
, "x", zreg
);
10070 macro_build (NULL
, dbl
? "dmultu" : "multu", "x,y", xreg
, yreg
);
10071 macro_build (NULL
, "mflo", "x", zreg
);
10079 if (imm_expr
.X_op
!= O_constant
)
10080 as_bad (_("Unsupported large constant"));
10081 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
10082 macro_build (&imm_expr
, dbl
? "daddiu" : "addiu", "y,x,4", yreg
, xreg
);
10086 if (imm_expr
.X_op
!= O_constant
)
10087 as_bad (_("Unsupported large constant"));
10088 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
10089 macro_build (&imm_expr
, "addiu", "x,k", xreg
);
10093 if (imm_expr
.X_op
!= O_constant
)
10094 as_bad (_("Unsupported large constant"));
10095 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
10096 macro_build (&imm_expr
, "daddiu", "y,j", yreg
);
10118 goto do_reverse_branch
;
10122 goto do_reverse_branch
;
10134 goto do_reverse_branch
;
10145 macro_build (NULL
, s
, "x,y", xreg
, yreg
);
10146 macro_build (&offset_expr
, s2
, "p");
10173 goto do_addone_branch_i
;
10178 goto do_addone_branch_i
;
10193 goto do_addone_branch_i
;
10199 do_addone_branch_i
:
10200 if (imm_expr
.X_op
!= O_constant
)
10201 as_bad (_("Unsupported large constant"));
10202 ++imm_expr
.X_add_number
;
10205 macro_build (&imm_expr
, s
, s3
, xreg
);
10206 macro_build (&offset_expr
, s2
, "p");
10210 expr1
.X_add_number
= 0;
10211 macro_build (&expr1
, "slti", "x,8", yreg
);
10213 move_register (xreg
, yreg
);
10214 expr1
.X_add_number
= 2;
10215 macro_build (&expr1
, "bteqz", "p");
10216 macro_build (NULL
, "neg", "x,w", xreg
, xreg
);
10220 /* For consistency checking, verify that all bits are specified either
10221 by the match/mask part of the instruction definition, or by the
10224 validate_mips_insn (const struct mips_opcode
*opc
)
10226 const char *p
= opc
->args
;
10228 unsigned long used_bits
= opc
->mask
;
10230 if ((used_bits
& opc
->match
) != opc
->match
)
10232 as_bad (_("internal: bad mips opcode (mask error): %s %s"),
10233 opc
->name
, opc
->args
);
10236 #define USE_BITS(mask,shift) (used_bits |= ((mask) << (shift)))
10246 case '1': USE_BITS (OP_MASK_UDI1
, OP_SH_UDI1
); break;
10247 case '2': USE_BITS (OP_MASK_UDI2
, OP_SH_UDI2
); break;
10248 case '3': USE_BITS (OP_MASK_UDI3
, OP_SH_UDI3
); break;
10249 case '4': USE_BITS (OP_MASK_UDI4
, OP_SH_UDI4
); break;
10250 case 'A': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
10251 case 'B': USE_BITS (OP_MASK_INSMSB
, OP_SH_INSMSB
); break;
10252 case 'C': USE_BITS (OP_MASK_EXTMSBD
, OP_SH_EXTMSBD
); break;
10253 case 'D': USE_BITS (OP_MASK_RD
, OP_SH_RD
);
10254 USE_BITS (OP_MASK_SEL
, OP_SH_SEL
); break;
10255 case 'E': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
10256 case 'F': USE_BITS (OP_MASK_INSMSB
, OP_SH_INSMSB
); break;
10257 case 'G': USE_BITS (OP_MASK_EXTMSBD
, OP_SH_EXTMSBD
); break;
10258 case 'H': USE_BITS (OP_MASK_EXTMSBD
, OP_SH_EXTMSBD
); break;
10260 case 't': USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
10261 case 'T': USE_BITS (OP_MASK_RT
, OP_SH_RT
);
10262 USE_BITS (OP_MASK_SEL
, OP_SH_SEL
); break;
10263 case 'x': USE_BITS (OP_MASK_BBITIND
, OP_SH_BBITIND
); break;
10264 case 'X': USE_BITS (OP_MASK_BBITIND
, OP_SH_BBITIND
); break;
10265 case 'p': USE_BITS (OP_MASK_CINSPOS
, OP_SH_CINSPOS
); break;
10266 case 'P': USE_BITS (OP_MASK_CINSPOS
, OP_SH_CINSPOS
); break;
10267 case 'Q': USE_BITS (OP_MASK_SEQI
, OP_SH_SEQI
); break;
10268 case 's': USE_BITS (OP_MASK_CINSLM1
, OP_SH_CINSLM1
); break;
10269 case 'S': USE_BITS (OP_MASK_CINSLM1
, OP_SH_CINSLM1
); break;
10270 case 'z': USE_BITS (OP_MASK_RZ
, OP_SH_RZ
); break;
10271 case 'Z': USE_BITS (OP_MASK_FZ
, OP_SH_FZ
); break;
10272 case 'a': USE_BITS (OP_MASK_OFFSET_A
, OP_SH_OFFSET_A
); break;
10273 case 'b': USE_BITS (OP_MASK_OFFSET_B
, OP_SH_OFFSET_B
); break;
10274 case 'c': USE_BITS (OP_MASK_OFFSET_C
, OP_SH_OFFSET_C
); break;
10277 as_bad (_("internal: bad mips opcode (unknown extension operand type `+%c'): %s %s"),
10278 c
, opc
->name
, opc
->args
);
10282 case '<': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
10283 case '>': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
10285 case 'B': USE_BITS (OP_MASK_CODE20
, OP_SH_CODE20
); break;
10286 case 'C': USE_BITS (OP_MASK_COPZ
, OP_SH_COPZ
); break;
10287 case 'D': USE_BITS (OP_MASK_FD
, OP_SH_FD
); break;
10288 case 'E': USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
10290 case 'G': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
10291 case 'H': USE_BITS (OP_MASK_SEL
, OP_SH_SEL
); break;
10293 case 'J': USE_BITS (OP_MASK_CODE19
, OP_SH_CODE19
); break;
10294 case 'K': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
10296 case 'M': USE_BITS (OP_MASK_CCC
, OP_SH_CCC
); break;
10297 case 'N': USE_BITS (OP_MASK_BCC
, OP_SH_BCC
); break;
10298 case 'O': USE_BITS (OP_MASK_ALN
, OP_SH_ALN
); break;
10299 case 'Q': USE_BITS (OP_MASK_VSEL
, OP_SH_VSEL
);
10300 USE_BITS (OP_MASK_FT
, OP_SH_FT
); break;
10301 case 'R': USE_BITS (OP_MASK_FR
, OP_SH_FR
); break;
10302 case 'S': USE_BITS (OP_MASK_FS
, OP_SH_FS
); break;
10303 case 'T': USE_BITS (OP_MASK_FT
, OP_SH_FT
); break;
10304 case 'V': USE_BITS (OP_MASK_FS
, OP_SH_FS
); break;
10305 case 'W': USE_BITS (OP_MASK_FT
, OP_SH_FT
); break;
10306 case 'X': USE_BITS (OP_MASK_FD
, OP_SH_FD
); break;
10307 case 'Y': USE_BITS (OP_MASK_FS
, OP_SH_FS
); break;
10308 case 'Z': USE_BITS (OP_MASK_FT
, OP_SH_FT
); break;
10309 case 'a': USE_BITS (OP_MASK_TARGET
, OP_SH_TARGET
); break;
10310 case 'b': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
10311 case 'c': USE_BITS (OP_MASK_CODE
, OP_SH_CODE
); break;
10312 case 'd': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
10314 case 'h': USE_BITS (OP_MASK_PREFX
, OP_SH_PREFX
); break;
10315 case 'i': USE_BITS (OP_MASK_IMMEDIATE
, OP_SH_IMMEDIATE
); break;
10316 case 'j': USE_BITS (OP_MASK_DELTA
, OP_SH_DELTA
); break;
10317 case 'k': USE_BITS (OP_MASK_CACHE
, OP_SH_CACHE
); break;
10319 case 'o': USE_BITS (OP_MASK_DELTA
, OP_SH_DELTA
); break;
10320 case 'p': USE_BITS (OP_MASK_DELTA
, OP_SH_DELTA
); break;
10321 case 'q': USE_BITS (OP_MASK_CODE2
, OP_SH_CODE2
); break;
10322 case 'r': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
10323 case 's': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
10324 case 't': USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
10325 case 'u': USE_BITS (OP_MASK_IMMEDIATE
, OP_SH_IMMEDIATE
); break;
10326 case 'v': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
10327 case 'w': USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
10330 case 'P': USE_BITS (OP_MASK_PERFREG
, OP_SH_PERFREG
); break;
10331 case 'U': USE_BITS (OP_MASK_RD
, OP_SH_RD
);
10332 USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
10333 case 'e': USE_BITS (OP_MASK_VECBYTE
, OP_SH_VECBYTE
); break;
10334 case '%': USE_BITS (OP_MASK_VECALIGN
, OP_SH_VECALIGN
); break;
10337 case '1': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
10338 case '2': USE_BITS (OP_MASK_BP
, OP_SH_BP
); break;
10339 case '3': USE_BITS (OP_MASK_SA3
, OP_SH_SA3
); break;
10340 case '4': USE_BITS (OP_MASK_SA4
, OP_SH_SA4
); break;
10341 case '5': USE_BITS (OP_MASK_IMM8
, OP_SH_IMM8
); break;
10342 case '6': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
10343 case '7': USE_BITS (OP_MASK_DSPACC
, OP_SH_DSPACC
); break;
10344 case '8': USE_BITS (OP_MASK_WRDSP
, OP_SH_WRDSP
); break;
10345 case '9': USE_BITS (OP_MASK_DSPACC_S
, OP_SH_DSPACC_S
);break;
10346 case '0': USE_BITS (OP_MASK_DSPSFT
, OP_SH_DSPSFT
); break;
10347 case '\'': USE_BITS (OP_MASK_RDDSP
, OP_SH_RDDSP
); break;
10348 case ':': USE_BITS (OP_MASK_DSPSFT_7
, OP_SH_DSPSFT_7
);break;
10349 case '@': USE_BITS (OP_MASK_IMM10
, OP_SH_IMM10
); break;
10350 case '!': USE_BITS (OP_MASK_MT_U
, OP_SH_MT_U
); break;
10351 case '$': USE_BITS (OP_MASK_MT_H
, OP_SH_MT_H
); break;
10352 case '*': USE_BITS (OP_MASK_MTACC_T
, OP_SH_MTACC_T
); break;
10353 case '&': USE_BITS (OP_MASK_MTACC_D
, OP_SH_MTACC_D
); break;
10354 case '\\': USE_BITS (OP_MASK_3BITPOS
, OP_SH_3BITPOS
); break;
10355 case '~': USE_BITS (OP_MASK_OFFSET12
, OP_SH_OFFSET12
); break;
10356 case 'g': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
10358 as_bad (_("internal: bad mips opcode (unknown operand type `%c'): %s %s"),
10359 c
, opc
->name
, opc
->args
);
10363 if (used_bits
!= 0xffffffff)
10365 as_bad (_("internal: bad mips opcode (bits 0x%lx undefined): %s %s"),
10366 ~used_bits
& 0xffffffff, opc
->name
, opc
->args
);
10372 /* For consistency checking, verify that the length implied matches the
10373 major opcode and that all bits are specified either by the match/mask
10374 part of the instruction definition, or by the operand list. */
10377 validate_micromips_insn (const struct mips_opcode
*opc
)
10379 unsigned long match
= opc
->match
;
10380 unsigned long mask
= opc
->mask
;
10381 const char *p
= opc
->args
;
10382 unsigned long insn_bits
;
10383 unsigned long used_bits
;
10384 unsigned long major
;
10385 unsigned int length
;
10389 if ((mask
& match
) != match
)
10391 as_bad (_("Internal error: bad microMIPS opcode (mask error): %s %s"),
10392 opc
->name
, opc
->args
);
10395 length
= micromips_insn_length (opc
);
10396 if (length
!= 2 && length
!= 4)
10398 as_bad (_("Internal error: bad microMIPS opcode (incorrect length: %u): "
10399 "%s %s"), length
, opc
->name
, opc
->args
);
10402 major
= match
>> (10 + 8 * (length
- 2));
10403 if ((length
== 2 && (major
& 7) != 1 && (major
& 6) != 2)
10404 || (length
== 4 && (major
& 7) != 0 && (major
& 4) != 4))
10406 as_bad (_("Internal error: bad microMIPS opcode "
10407 "(opcode/length mismatch): %s %s"), opc
->name
, opc
->args
);
10411 /* Shift piecewise to avoid an overflow where unsigned long is 32-bit. */
10412 insn_bits
= 1 << 4 * length
;
10413 insn_bits
<<= 4 * length
;
10416 #define USE_BITS(field) \
10417 (used_bits |= MICROMIPSOP_MASK_##field << MICROMIPSOP_SH_##field)
10428 case 'A': USE_BITS (EXTLSB
); break;
10429 case 'B': USE_BITS (INSMSB
); break;
10430 case 'C': USE_BITS (EXTMSBD
); break;
10431 case 'D': USE_BITS (RS
); USE_BITS (SEL
); break;
10432 case 'E': USE_BITS (EXTLSB
); break;
10433 case 'F': USE_BITS (INSMSB
); break;
10434 case 'G': USE_BITS (EXTMSBD
); break;
10435 case 'H': USE_BITS (EXTMSBD
); break;
10437 as_bad (_("Internal error: bad mips opcode "
10438 "(unknown extension operand type `%c%c'): %s %s"),
10439 e
, c
, opc
->name
, opc
->args
);
10447 case 'A': USE_BITS (IMMA
); break;
10448 case 'B': USE_BITS (IMMB
); break;
10449 case 'C': USE_BITS (IMMC
); break;
10450 case 'D': USE_BITS (IMMD
); break;
10451 case 'E': USE_BITS (IMME
); break;
10452 case 'F': USE_BITS (IMMF
); break;
10453 case 'G': USE_BITS (IMMG
); break;
10454 case 'H': USE_BITS (IMMH
); break;
10455 case 'I': USE_BITS (IMMI
); break;
10456 case 'J': USE_BITS (IMMJ
); break;
10457 case 'L': USE_BITS (IMML
); break;
10458 case 'M': USE_BITS (IMMM
); break;
10459 case 'N': USE_BITS (IMMN
); break;
10460 case 'O': USE_BITS (IMMO
); break;
10461 case 'P': USE_BITS (IMMP
); break;
10462 case 'Q': USE_BITS (IMMQ
); break;
10463 case 'U': USE_BITS (IMMU
); break;
10464 case 'W': USE_BITS (IMMW
); break;
10465 case 'X': USE_BITS (IMMX
); break;
10466 case 'Y': USE_BITS (IMMY
); break;
10469 case 'b': USE_BITS (MB
); break;
10470 case 'c': USE_BITS (MC
); break;
10471 case 'd': USE_BITS (MD
); break;
10472 case 'e': USE_BITS (ME
); break;
10473 case 'f': USE_BITS (MF
); break;
10474 case 'g': USE_BITS (MG
); break;
10475 case 'h': USE_BITS (MH
); break;
10476 case 'i': USE_BITS (MI
); break;
10477 case 'j': USE_BITS (MJ
); break;
10478 case 'l': USE_BITS (ML
); break;
10479 case 'm': USE_BITS (MM
); break;
10480 case 'n': USE_BITS (MN
); break;
10481 case 'p': USE_BITS (MP
); break;
10482 case 'q': USE_BITS (MQ
); break;
10490 as_bad (_("Internal error: bad mips opcode "
10491 "(unknown extension operand type `%c%c'): %s %s"),
10492 e
, c
, opc
->name
, opc
->args
);
10496 case '.': USE_BITS (OFFSET10
); break;
10497 case '1': USE_BITS (STYPE
); break;
10498 case '2': USE_BITS (BP
); break;
10499 case '3': USE_BITS (SA3
); break;
10500 case '4': USE_BITS (SA4
); break;
10501 case '5': USE_BITS (IMM8
); break;
10502 case '6': USE_BITS (RS
); break;
10503 case '7': USE_BITS (DSPACC
); break;
10504 case '8': USE_BITS (WRDSP
); break;
10505 case '0': USE_BITS (DSPSFT
); break;
10506 case '<': USE_BITS (SHAMT
); break;
10507 case '>': USE_BITS (SHAMT
); break;
10508 case '@': USE_BITS (IMM10
); break;
10509 case 'B': USE_BITS (CODE10
); break;
10510 case 'C': USE_BITS (COPZ
); break;
10511 case 'D': USE_BITS (FD
); break;
10512 case 'E': USE_BITS (RT
); break;
10513 case 'G': USE_BITS (RS
); break;
10514 case 'H': USE_BITS (SEL
); break;
10515 case 'K': USE_BITS (RS
); break;
10516 case 'M': USE_BITS (CCC
); break;
10517 case 'N': USE_BITS (BCC
); break;
10518 case 'R': USE_BITS (FR
); break;
10519 case 'S': USE_BITS (FS
); break;
10520 case 'T': USE_BITS (FT
); break;
10521 case 'V': USE_BITS (FS
); break;
10522 case '\\': USE_BITS (3BITPOS
); break;
10523 case '^': USE_BITS (RD
); break;
10524 case 'a': USE_BITS (TARGET
); break;
10525 case 'b': USE_BITS (RS
); break;
10526 case 'c': USE_BITS (CODE
); break;
10527 case 'd': USE_BITS (RD
); break;
10528 case 'h': USE_BITS (PREFX
); break;
10529 case 'i': USE_BITS (IMMEDIATE
); break;
10530 case 'j': USE_BITS (DELTA
); break;
10531 case 'k': USE_BITS (CACHE
); break;
10532 case 'n': USE_BITS (RT
); break;
10533 case 'o': USE_BITS (DELTA
); break;
10534 case 'p': USE_BITS (DELTA
); break;
10535 case 'q': USE_BITS (CODE2
); break;
10536 case 'r': USE_BITS (RS
); break;
10537 case 's': USE_BITS (RS
); break;
10538 case 't': USE_BITS (RT
); break;
10539 case 'u': USE_BITS (IMMEDIATE
); break;
10540 case 'v': USE_BITS (RS
); break;
10541 case 'w': USE_BITS (RT
); break;
10542 case 'y': USE_BITS (RS3
); break;
10544 case '|': USE_BITS (TRAP
); break;
10545 case '~': USE_BITS (OFFSET12
); break;
10547 as_bad (_("Internal error: bad microMIPS opcode "
10548 "(unknown operand type `%c'): %s %s"),
10549 c
, opc
->name
, opc
->args
);
10553 if (used_bits
!= insn_bits
)
10555 if (~used_bits
& insn_bits
)
10556 as_bad (_("Internal error: bad microMIPS opcode "
10557 "(bits 0x%lx undefined): %s %s"),
10558 ~used_bits
& insn_bits
, opc
->name
, opc
->args
);
10559 if (used_bits
& ~insn_bits
)
10560 as_bad (_("Internal error: bad microMIPS opcode "
10561 "(bits 0x%lx defined): %s %s"),
10562 used_bits
& ~insn_bits
, opc
->name
, opc
->args
);
10568 /* UDI immediates. */
10569 struct mips_immed
{
10571 unsigned int shift
;
10572 unsigned long mask
;
10576 static const struct mips_immed mips_immed
[] = {
10577 { '1', OP_SH_UDI1
, OP_MASK_UDI1
, 0},
10578 { '2', OP_SH_UDI2
, OP_MASK_UDI2
, 0},
10579 { '3', OP_SH_UDI3
, OP_MASK_UDI3
, 0},
10580 { '4', OP_SH_UDI4
, OP_MASK_UDI4
, 0},
10584 /* Check whether an odd floating-point register is allowed. */
10586 mips_oddfpreg_ok (const struct mips_opcode
*insn
, int argnum
)
10588 const char *s
= insn
->name
;
10590 if (insn
->pinfo
== INSN_MACRO
)
10591 /* Let a macro pass, we'll catch it later when it is expanded. */
10594 if (ISA_HAS_ODD_SINGLE_FPR (mips_opts
.isa
))
10596 /* Allow odd registers for single-precision ops. */
10597 switch (insn
->pinfo
& (FP_S
| FP_D
))
10601 return 1; /* both single precision - ok */
10603 return 0; /* both double precision - fail */
10608 /* Cvt.w.x and cvt.x.w allow an odd register for a 'w' or 's' operand. */
10609 s
= strchr (insn
->name
, '.');
10611 s
= s
!= NULL
? strchr (s
+ 1, '.') : NULL
;
10612 return (s
!= NULL
&& (s
[1] == 'w' || s
[1] == 's'));
10615 /* Single-precision coprocessor loads and moves are OK too. */
10616 if ((insn
->pinfo
& FP_S
)
10617 && (insn
->pinfo
& (INSN_COPROC_MEMORY_DELAY
| INSN_STORE_MEMORY
10618 | INSN_LOAD_COPROC_DELAY
| INSN_COPROC_MOVE_DELAY
)))
10624 /* Check if EXPR is a constant between MIN (inclusive) and MAX (exclusive)
10625 taking bits from BIT up. */
10627 expr_const_in_range (expressionS
*ep
, offsetT min
, offsetT max
, int bit
)
10629 return (ep
->X_op
== O_constant
10630 && (ep
->X_add_number
& ((1 << bit
) - 1)) == 0
10631 && ep
->X_add_number
>= min
<< bit
10632 && ep
->X_add_number
< max
<< bit
);
10635 /* This routine assembles an instruction into its binary format. As a
10636 side effect, it sets one of the global variables imm_reloc or
10637 offset_reloc to the type of relocation to do if one of the operands
10638 is an address expression. */
10641 mips_ip (char *str
, struct mips_cl_insn
*ip
)
10643 bfd_boolean wrong_delay_slot_insns
= FALSE
;
10644 bfd_boolean need_delay_slot_ok
= TRUE
;
10645 struct mips_opcode
*firstinsn
= NULL
;
10646 const struct mips_opcode
*past
;
10647 struct hash_control
*hash
;
10651 struct mips_opcode
*insn
;
10653 unsigned int regno
;
10654 unsigned int lastregno
;
10655 unsigned int destregno
= 0;
10656 unsigned int lastpos
= 0;
10657 unsigned int limlo
, limhi
;
10659 offsetT min_range
, max_range
;
10663 unsigned int rtype
;
10669 if (mips_opts
.micromips
)
10671 hash
= micromips_op_hash
;
10672 past
= µmips_opcodes
[bfd_micromips_num_opcodes
];
10677 past
= &mips_opcodes
[NUMOPCODES
];
10679 forced_insn_length
= 0;
10682 /* We first try to match an instruction up to a space or to the end. */
10683 for (end
= 0; str
[end
] != '\0' && !ISSPACE (str
[end
]); end
++)
10686 /* Make a copy of the instruction so that we can fiddle with it. */
10687 name
= alloca (end
+ 1);
10688 memcpy (name
, str
, end
);
10693 insn
= (struct mips_opcode
*) hash_find (hash
, name
);
10695 if (insn
!= NULL
|| !mips_opts
.micromips
)
10697 if (forced_insn_length
)
10700 /* See if there's an instruction size override suffix,
10701 either `16' or `32', at the end of the mnemonic proper,
10702 that defines the operation, i.e. before the first `.'
10703 character if any. Strip it and retry. */
10704 dot
= strchr (name
, '.');
10705 opend
= dot
!= NULL
? dot
- name
: end
;
10708 if (name
[opend
- 2] == '1' && name
[opend
- 1] == '6')
10709 forced_insn_length
= 2;
10710 else if (name
[opend
- 2] == '3' && name
[opend
- 1] == '2')
10711 forced_insn_length
= 4;
10714 memcpy (name
+ opend
- 2, name
+ opend
, end
- opend
+ 1);
10718 insn_error
= _("Unrecognized opcode");
10722 /* For microMIPS instructions placed in a fixed-length branch delay slot
10723 we make up to two passes over the relevant fragment of the opcode
10724 table. First we try instructions that meet the delay slot's length
10725 requirement. If none matched, then we retry with the remaining ones
10726 and if one matches, then we use it and then issue an appropriate
10727 warning later on. */
10728 argsStart
= s
= str
+ end
;
10731 bfd_boolean delay_slot_ok
;
10732 bfd_boolean size_ok
;
10735 gas_assert (strcmp (insn
->name
, name
) == 0);
10737 ok
= is_opcode_valid (insn
);
10738 size_ok
= is_size_valid (insn
);
10739 delay_slot_ok
= is_delay_slot_valid (insn
);
10740 if (!delay_slot_ok
&& !wrong_delay_slot_insns
)
10743 wrong_delay_slot_insns
= TRUE
;
10745 if (!ok
|| !size_ok
|| delay_slot_ok
!= need_delay_slot_ok
)
10747 static char buf
[256];
10749 if (insn
+ 1 < past
&& strcmp (insn
->name
, insn
[1].name
) == 0)
10754 if (wrong_delay_slot_insns
&& need_delay_slot_ok
)
10756 gas_assert (firstinsn
);
10757 need_delay_slot_ok
= FALSE
;
10767 sprintf (buf
, _("Opcode not supported on this processor: %s (%s)"),
10768 mips_cpu_info_from_arch (mips_opts
.arch
)->name
,
10769 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
10771 sprintf (buf
, _("Unrecognized %u-bit version of microMIPS opcode"),
10772 8 * forced_insn_length
);
10778 create_insn (ip
, insn
);
10781 lastregno
= 0xffffffff;
10782 for (args
= insn
->args
;; ++args
)
10786 s
+= strspn (s
, " \t");
10790 case '\0': /* end of args */
10796 /* DSP 2-bit unsigned immediate in bit 11 (for standard MIPS
10797 code) or 14 (for microMIPS code). */
10798 my_getExpression (&imm_expr
, s
);
10799 check_absolute_expr (ip
, &imm_expr
);
10800 if ((unsigned long) imm_expr
.X_add_number
!= 1
10801 && (unsigned long) imm_expr
.X_add_number
!= 3)
10803 as_bad (_("BALIGN immediate not 1 or 3 (%lu)"),
10804 (unsigned long) imm_expr
.X_add_number
);
10806 INSERT_OPERAND (mips_opts
.micromips
,
10807 BP
, *ip
, imm_expr
.X_add_number
);
10808 imm_expr
.X_op
= O_absent
;
10813 /* DSP 3-bit unsigned immediate in bit 13 (for standard MIPS
10814 code) or 21 (for microMIPS code). */
10816 unsigned long mask
= (mips_opts
.micromips
10817 ? MICROMIPSOP_MASK_SA3
: OP_MASK_SA3
);
10819 my_getExpression (&imm_expr
, s
);
10820 check_absolute_expr (ip
, &imm_expr
);
10821 if ((unsigned long) imm_expr
.X_add_number
> mask
)
10822 as_bad (_("DSP immediate not in range 0..%lu (%lu)"),
10823 mask
, (unsigned long) imm_expr
.X_add_number
);
10824 INSERT_OPERAND (mips_opts
.micromips
,
10825 SA3
, *ip
, imm_expr
.X_add_number
);
10826 imm_expr
.X_op
= O_absent
;
10832 /* DSP 4-bit unsigned immediate in bit 12 (for standard MIPS
10833 code) or 21 (for microMIPS code). */
10835 unsigned long mask
= (mips_opts
.micromips
10836 ? MICROMIPSOP_MASK_SA4
: OP_MASK_SA4
);
10838 my_getExpression (&imm_expr
, s
);
10839 check_absolute_expr (ip
, &imm_expr
);
10840 if ((unsigned long) imm_expr
.X_add_number
> mask
)
10841 as_bad (_("DSP immediate not in range 0..%lu (%lu)"),
10842 mask
, (unsigned long) imm_expr
.X_add_number
);
10843 INSERT_OPERAND (mips_opts
.micromips
,
10844 SA4
, *ip
, imm_expr
.X_add_number
);
10845 imm_expr
.X_op
= O_absent
;
10851 /* DSP 8-bit unsigned immediate in bit 13 (for standard MIPS
10852 code) or 16 (for microMIPS code). */
10854 unsigned long mask
= (mips_opts
.micromips
10855 ? MICROMIPSOP_MASK_IMM8
: OP_MASK_IMM8
);
10857 my_getExpression (&imm_expr
, s
);
10858 check_absolute_expr (ip
, &imm_expr
);
10859 if ((unsigned long) imm_expr
.X_add_number
> mask
)
10860 as_bad (_("DSP immediate not in range 0..%lu (%lu)"),
10861 mask
, (unsigned long) imm_expr
.X_add_number
);
10862 INSERT_OPERAND (mips_opts
.micromips
,
10863 IMM8
, *ip
, imm_expr
.X_add_number
);
10864 imm_expr
.X_op
= O_absent
;
10870 /* DSP 5-bit unsigned immediate in bit 16 (for standard MIPS
10871 code) or 21 (for microMIPS code). */
10873 unsigned long mask
= (mips_opts
.micromips
10874 ? MICROMIPSOP_MASK_RS
: OP_MASK_RS
);
10876 my_getExpression (&imm_expr
, s
);
10877 check_absolute_expr (ip
, &imm_expr
);
10878 if ((unsigned long) imm_expr
.X_add_number
> mask
)
10879 as_bad (_("DSP immediate not in range 0..%lu (%lu)"),
10880 mask
, (unsigned long) imm_expr
.X_add_number
);
10881 INSERT_OPERAND (mips_opts
.micromips
,
10882 RS
, *ip
, imm_expr
.X_add_number
);
10883 imm_expr
.X_op
= O_absent
;
10888 case '7': /* Four DSP accumulators in bits 11,12. */
10889 if (s
[0] == '$' && s
[1] == 'a' && s
[2] == 'c'
10890 && s
[3] >= '0' && s
[3] <= '3')
10892 regno
= s
[3] - '0';
10894 INSERT_OPERAND (mips_opts
.micromips
, DSPACC
, *ip
, regno
);
10898 as_bad (_("Invalid dsp acc register"));
10902 /* DSP 6-bit unsigned immediate in bit 11 (for standard MIPS
10903 code) or 14 (for microMIPS code). */
10905 unsigned long mask
= (mips_opts
.micromips
10906 ? MICROMIPSOP_MASK_WRDSP
10909 my_getExpression (&imm_expr
, s
);
10910 check_absolute_expr (ip
, &imm_expr
);
10911 if ((unsigned long) imm_expr
.X_add_number
> mask
)
10912 as_bad (_("DSP immediate not in range 0..%lu (%lu)"),
10913 mask
, (unsigned long) imm_expr
.X_add_number
);
10914 INSERT_OPERAND (mips_opts
.micromips
,
10915 WRDSP
, *ip
, imm_expr
.X_add_number
);
10916 imm_expr
.X_op
= O_absent
;
10921 case '9': /* Four DSP accumulators in bits 21,22. */
10922 gas_assert (!mips_opts
.micromips
);
10923 if (s
[0] == '$' && s
[1] == 'a' && s
[2] == 'c'
10924 && s
[3] >= '0' && s
[3] <= '3')
10926 regno
= s
[3] - '0';
10928 INSERT_OPERAND (0, DSPACC_S
, *ip
, regno
);
10932 as_bad (_("Invalid dsp acc register"));
10936 /* DSP 6-bit signed immediate in bit 16 (for standard MIPS
10937 code) or 20 (for microMIPS code). */
10939 long mask
= (mips_opts
.micromips
10940 ? MICROMIPSOP_MASK_DSPSFT
: OP_MASK_DSPSFT
);
10942 my_getExpression (&imm_expr
, s
);
10943 check_absolute_expr (ip
, &imm_expr
);
10944 min_range
= -((mask
+ 1) >> 1);
10945 max_range
= ((mask
+ 1) >> 1) - 1;
10946 if (imm_expr
.X_add_number
< min_range
10947 || imm_expr
.X_add_number
> max_range
)
10948 as_bad (_("DSP immediate not in range %ld..%ld (%ld)"),
10949 (long) min_range
, (long) max_range
,
10950 (long) imm_expr
.X_add_number
);
10951 INSERT_OPERAND (mips_opts
.micromips
,
10952 DSPSFT
, *ip
, imm_expr
.X_add_number
);
10953 imm_expr
.X_op
= O_absent
;
10958 case '\'': /* DSP 6-bit unsigned immediate in bit 16. */
10959 gas_assert (!mips_opts
.micromips
);
10960 my_getExpression (&imm_expr
, s
);
10961 check_absolute_expr (ip
, &imm_expr
);
10962 if (imm_expr
.X_add_number
& ~OP_MASK_RDDSP
)
10964 as_bad (_("DSP immediate not in range 0..%d (%lu)"),
10966 (unsigned long) imm_expr
.X_add_number
);
10968 INSERT_OPERAND (0, RDDSP
, *ip
, imm_expr
.X_add_number
);
10969 imm_expr
.X_op
= O_absent
;
10973 case ':': /* DSP 7-bit signed immediate in bit 19. */
10974 gas_assert (!mips_opts
.micromips
);
10975 my_getExpression (&imm_expr
, s
);
10976 check_absolute_expr (ip
, &imm_expr
);
10977 min_range
= -((OP_MASK_DSPSFT_7
+ 1) >> 1);
10978 max_range
= ((OP_MASK_DSPSFT_7
+ 1) >> 1) - 1;
10979 if (imm_expr
.X_add_number
< min_range
||
10980 imm_expr
.X_add_number
> max_range
)
10982 as_bad (_("DSP immediate not in range %ld..%ld (%ld)"),
10983 (long) min_range
, (long) max_range
,
10984 (long) imm_expr
.X_add_number
);
10986 INSERT_OPERAND (0, DSPSFT_7
, *ip
, imm_expr
.X_add_number
);
10987 imm_expr
.X_op
= O_absent
;
10991 case '@': /* DSP 10-bit signed immediate in bit 16. */
10993 long mask
= (mips_opts
.micromips
10994 ? MICROMIPSOP_MASK_IMM10
: OP_MASK_IMM10
);
10996 my_getExpression (&imm_expr
, s
);
10997 check_absolute_expr (ip
, &imm_expr
);
10998 min_range
= -((mask
+ 1) >> 1);
10999 max_range
= ((mask
+ 1) >> 1) - 1;
11000 if (imm_expr
.X_add_number
< min_range
11001 || imm_expr
.X_add_number
> max_range
)
11002 as_bad (_("DSP immediate not in range %ld..%ld (%ld)"),
11003 (long) min_range
, (long) max_range
,
11004 (long) imm_expr
.X_add_number
);
11005 INSERT_OPERAND (mips_opts
.micromips
,
11006 IMM10
, *ip
, imm_expr
.X_add_number
);
11007 imm_expr
.X_op
= O_absent
;
11012 case '^': /* DSP 5-bit unsigned immediate in bit 11. */
11013 gas_assert (mips_opts
.micromips
);
11014 my_getExpression (&imm_expr
, s
);
11015 check_absolute_expr (ip
, &imm_expr
);
11016 if (imm_expr
.X_add_number
& ~MICROMIPSOP_MASK_RD
)
11017 as_bad (_("DSP immediate not in range 0..%d (%lu)"),
11018 MICROMIPSOP_MASK_RD
,
11019 (unsigned long) imm_expr
.X_add_number
);
11020 INSERT_OPERAND (1, RD
, *ip
, imm_expr
.X_add_number
);
11021 imm_expr
.X_op
= O_absent
;
11025 case '!': /* MT usermode flag bit. */
11026 gas_assert (!mips_opts
.micromips
);
11027 my_getExpression (&imm_expr
, s
);
11028 check_absolute_expr (ip
, &imm_expr
);
11029 if (imm_expr
.X_add_number
& ~OP_MASK_MT_U
)
11030 as_bad (_("MT usermode bit not 0 or 1 (%lu)"),
11031 (unsigned long) imm_expr
.X_add_number
);
11032 INSERT_OPERAND (0, MT_U
, *ip
, imm_expr
.X_add_number
);
11033 imm_expr
.X_op
= O_absent
;
11037 case '$': /* MT load high flag bit. */
11038 gas_assert (!mips_opts
.micromips
);
11039 my_getExpression (&imm_expr
, s
);
11040 check_absolute_expr (ip
, &imm_expr
);
11041 if (imm_expr
.X_add_number
& ~OP_MASK_MT_H
)
11042 as_bad (_("MT load high bit not 0 or 1 (%lu)"),
11043 (unsigned long) imm_expr
.X_add_number
);
11044 INSERT_OPERAND (0, MT_H
, *ip
, imm_expr
.X_add_number
);
11045 imm_expr
.X_op
= O_absent
;
11049 case '*': /* Four DSP accumulators in bits 18,19. */
11050 gas_assert (!mips_opts
.micromips
);
11051 if (s
[0] == '$' && s
[1] == 'a' && s
[2] == 'c' &&
11052 s
[3] >= '0' && s
[3] <= '3')
11054 regno
= s
[3] - '0';
11056 INSERT_OPERAND (0, MTACC_T
, *ip
, regno
);
11060 as_bad (_("Invalid dsp/smartmips acc register"));
11063 case '&': /* Four DSP accumulators in bits 13,14. */
11064 gas_assert (!mips_opts
.micromips
);
11065 if (s
[0] == '$' && s
[1] == 'a' && s
[2] == 'c' &&
11066 s
[3] >= '0' && s
[3] <= '3')
11068 regno
= s
[3] - '0';
11070 INSERT_OPERAND (0, MTACC_D
, *ip
, regno
);
11074 as_bad (_("Invalid dsp/smartmips acc register"));
11077 case '\\': /* 3-bit bit position. */
11079 unsigned long mask
= (mips_opts
.micromips
11080 ? MICROMIPSOP_MASK_3BITPOS
11081 : OP_MASK_3BITPOS
);
11083 my_getExpression (&imm_expr
, s
);
11084 check_absolute_expr (ip
, &imm_expr
);
11085 if ((unsigned long) imm_expr
.X_add_number
> mask
)
11086 as_warn (_("Bit position for %s not in range 0..%lu (%lu)"),
11088 mask
, (unsigned long) imm_expr
.X_add_number
);
11089 INSERT_OPERAND (mips_opts
.micromips
,
11090 3BITPOS
, *ip
, imm_expr
.X_add_number
);
11091 imm_expr
.X_op
= O_absent
;
11105 INSERT_OPERAND (mips_opts
.micromips
, RS
, *ip
, lastregno
);
11109 INSERT_OPERAND (mips_opts
.micromips
, RT
, *ip
, lastregno
);
11113 gas_assert (!mips_opts
.micromips
);
11114 INSERT_OPERAND (0, FT
, *ip
, lastregno
);
11118 INSERT_OPERAND (mips_opts
.micromips
, FS
, *ip
, lastregno
);
11124 /* Handle optional base register.
11125 Either the base register is omitted or
11126 we must have a left paren. */
11127 /* This is dependent on the next operand specifier
11128 is a base register specification. */
11129 gas_assert (args
[1] == 'b'
11130 || (mips_opts
.micromips
11132 && (args
[2] == 'l' || args
[2] == 'n'
11133 || args
[2] == 's' || args
[2] == 'a')));
11134 if (*s
== '\0' && args
[1] == 'b')
11136 /* Fall through. */
11138 case ')': /* These must match exactly. */
11143 case '[': /* These must match exactly. */
11145 gas_assert (!mips_opts
.micromips
);
11150 case '+': /* Opcode extension character. */
11153 case '1': /* UDI immediates. */
11157 gas_assert (!mips_opts
.micromips
);
11159 const struct mips_immed
*imm
= mips_immed
;
11161 while (imm
->type
&& imm
->type
!= *args
)
11165 my_getExpression (&imm_expr
, s
);
11166 check_absolute_expr (ip
, &imm_expr
);
11167 if ((unsigned long) imm_expr
.X_add_number
& ~imm
->mask
)
11169 as_warn (_("Illegal %s number (%lu, 0x%lx)"),
11170 imm
->desc
? imm
->desc
: ip
->insn_mo
->name
,
11171 (unsigned long) imm_expr
.X_add_number
,
11172 (unsigned long) imm_expr
.X_add_number
);
11173 imm_expr
.X_add_number
&= imm
->mask
;
11175 ip
->insn_opcode
|= ((unsigned long) imm_expr
.X_add_number
11177 imm_expr
.X_op
= O_absent
;
11182 case 'A': /* ins/ext position, becomes LSB. */
11191 my_getExpression (&imm_expr
, s
);
11192 check_absolute_expr (ip
, &imm_expr
);
11193 if ((unsigned long) imm_expr
.X_add_number
< limlo
11194 || (unsigned long) imm_expr
.X_add_number
> limhi
)
11196 as_bad (_("Improper position (%lu)"),
11197 (unsigned long) imm_expr
.X_add_number
);
11198 imm_expr
.X_add_number
= limlo
;
11200 lastpos
= imm_expr
.X_add_number
;
11201 INSERT_OPERAND (mips_opts
.micromips
,
11202 EXTLSB
, *ip
, imm_expr
.X_add_number
);
11203 imm_expr
.X_op
= O_absent
;
11207 case 'B': /* ins size, becomes MSB. */
11216 my_getExpression (&imm_expr
, s
);
11217 check_absolute_expr (ip
, &imm_expr
);
11218 /* Check for negative input so that small negative numbers
11219 will not succeed incorrectly. The checks against
11220 (pos+size) transitively check "size" itself,
11221 assuming that "pos" is reasonable. */
11222 if ((long) imm_expr
.X_add_number
< 0
11223 || ((unsigned long) imm_expr
.X_add_number
11225 || ((unsigned long) imm_expr
.X_add_number
11226 + lastpos
) > limhi
)
11228 as_bad (_("Improper insert size (%lu, position %lu)"),
11229 (unsigned long) imm_expr
.X_add_number
,
11230 (unsigned long) lastpos
);
11231 imm_expr
.X_add_number
= limlo
- lastpos
;
11233 INSERT_OPERAND (mips_opts
.micromips
, INSMSB
, *ip
,
11234 lastpos
+ imm_expr
.X_add_number
- 1);
11235 imm_expr
.X_op
= O_absent
;
11239 case 'C': /* ext size, becomes MSBD. */
11252 my_getExpression (&imm_expr
, s
);
11253 check_absolute_expr (ip
, &imm_expr
);
11254 /* Check for negative input so that small negative numbers
11255 will not succeed incorrectly. The checks against
11256 (pos+size) transitively check "size" itself,
11257 assuming that "pos" is reasonable. */
11258 if ((long) imm_expr
.X_add_number
< 0
11259 || ((unsigned long) imm_expr
.X_add_number
11261 || ((unsigned long) imm_expr
.X_add_number
11262 + lastpos
) > limhi
)
11264 as_bad (_("Improper extract size (%lu, position %lu)"),
11265 (unsigned long) imm_expr
.X_add_number
,
11266 (unsigned long) lastpos
);
11267 imm_expr
.X_add_number
= limlo
- lastpos
;
11269 INSERT_OPERAND (mips_opts
.micromips
,
11270 EXTMSBD
, *ip
, imm_expr
.X_add_number
- 1);
11271 imm_expr
.X_op
= O_absent
;
11276 /* +D is for disassembly only; never match. */
11280 /* "+I" is like "I", except that imm2_expr is used. */
11281 my_getExpression (&imm2_expr
, s
);
11282 if (imm2_expr
.X_op
!= O_big
11283 && imm2_expr
.X_op
!= O_constant
)
11284 insn_error
= _("absolute expression required");
11285 if (HAVE_32BIT_GPRS
)
11286 normalize_constant_expr (&imm2_expr
);
11290 case 'T': /* Coprocessor register. */
11291 gas_assert (!mips_opts
.micromips
);
11292 /* +T is for disassembly only; never match. */
11295 case 't': /* Coprocessor register number. */
11296 gas_assert (!mips_opts
.micromips
);
11297 if (s
[0] == '$' && ISDIGIT (s
[1]))
11307 while (ISDIGIT (*s
));
11309 as_bad (_("Invalid register number (%d)"), regno
);
11312 INSERT_OPERAND (0, RT
, *ip
, regno
);
11317 as_bad (_("Invalid coprocessor 0 register number"));
11321 /* bbit[01] and bbit[01]32 bit index. Give error if index
11322 is not in the valid range. */
11323 gas_assert (!mips_opts
.micromips
);
11324 my_getExpression (&imm_expr
, s
);
11325 check_absolute_expr (ip
, &imm_expr
);
11326 if ((unsigned) imm_expr
.X_add_number
> 31)
11328 as_bad (_("Improper bit index (%lu)"),
11329 (unsigned long) imm_expr
.X_add_number
);
11330 imm_expr
.X_add_number
= 0;
11332 INSERT_OPERAND (0, BBITIND
, *ip
, imm_expr
.X_add_number
);
11333 imm_expr
.X_op
= O_absent
;
11338 /* bbit[01] bit index when bbit is used but we generate
11339 bbit[01]32 because the index is over 32. Move to the
11340 next candidate if index is not in the valid range. */
11341 gas_assert (!mips_opts
.micromips
);
11342 my_getExpression (&imm_expr
, s
);
11343 check_absolute_expr (ip
, &imm_expr
);
11344 if ((unsigned) imm_expr
.X_add_number
< 32
11345 || (unsigned) imm_expr
.X_add_number
> 63)
11347 INSERT_OPERAND (0, BBITIND
, *ip
, imm_expr
.X_add_number
- 32);
11348 imm_expr
.X_op
= O_absent
;
11353 /* cins, cins32, exts and exts32 position field. Give error
11354 if it's not in the valid range. */
11355 gas_assert (!mips_opts
.micromips
);
11356 my_getExpression (&imm_expr
, s
);
11357 check_absolute_expr (ip
, &imm_expr
);
11358 if ((unsigned) imm_expr
.X_add_number
> 31)
11360 as_bad (_("Improper position (%lu)"),
11361 (unsigned long) imm_expr
.X_add_number
);
11362 imm_expr
.X_add_number
= 0;
11364 /* Make the pos explicit to simplify +S. */
11365 lastpos
= imm_expr
.X_add_number
+ 32;
11366 INSERT_OPERAND (0, CINSPOS
, *ip
, imm_expr
.X_add_number
);
11367 imm_expr
.X_op
= O_absent
;
11372 /* cins, cins32, exts and exts32 position field. Move to
11373 the next candidate if it's not in the valid range. */
11374 gas_assert (!mips_opts
.micromips
);
11375 my_getExpression (&imm_expr
, s
);
11376 check_absolute_expr (ip
, &imm_expr
);
11377 if ((unsigned) imm_expr
.X_add_number
< 32
11378 || (unsigned) imm_expr
.X_add_number
> 63)
11380 lastpos
= imm_expr
.X_add_number
;
11381 INSERT_OPERAND (0, CINSPOS
, *ip
, imm_expr
.X_add_number
- 32);
11382 imm_expr
.X_op
= O_absent
;
11387 /* cins and exts length-minus-one field. */
11388 gas_assert (!mips_opts
.micromips
);
11389 my_getExpression (&imm_expr
, s
);
11390 check_absolute_expr (ip
, &imm_expr
);
11391 if ((unsigned long) imm_expr
.X_add_number
> 31)
11393 as_bad (_("Improper size (%lu)"),
11394 (unsigned long) imm_expr
.X_add_number
);
11395 imm_expr
.X_add_number
= 0;
11397 INSERT_OPERAND (0, CINSLM1
, *ip
, imm_expr
.X_add_number
);
11398 imm_expr
.X_op
= O_absent
;
11403 /* cins32/exts32 and cins/exts aliasing cint32/exts32
11404 length-minus-one field. */
11405 gas_assert (!mips_opts
.micromips
);
11406 my_getExpression (&imm_expr
, s
);
11407 check_absolute_expr (ip
, &imm_expr
);
11408 if ((long) imm_expr
.X_add_number
< 0
11409 || (unsigned long) imm_expr
.X_add_number
+ lastpos
> 63)
11411 as_bad (_("Improper size (%lu)"),
11412 (unsigned long) imm_expr
.X_add_number
);
11413 imm_expr
.X_add_number
= 0;
11415 INSERT_OPERAND (0, CINSLM1
, *ip
, imm_expr
.X_add_number
);
11416 imm_expr
.X_op
= O_absent
;
11421 /* seqi/snei immediate field. */
11422 gas_assert (!mips_opts
.micromips
);
11423 my_getExpression (&imm_expr
, s
);
11424 check_absolute_expr (ip
, &imm_expr
);
11425 if ((long) imm_expr
.X_add_number
< -512
11426 || (long) imm_expr
.X_add_number
>= 512)
11428 as_bad (_("Improper immediate (%ld)"),
11429 (long) imm_expr
.X_add_number
);
11430 imm_expr
.X_add_number
= 0;
11432 INSERT_OPERAND (0, SEQI
, *ip
, imm_expr
.X_add_number
);
11433 imm_expr
.X_op
= O_absent
;
11437 case 'a': /* 8-bit signed offset in bit 6 */
11438 gas_assert (!mips_opts
.micromips
);
11439 my_getExpression (&imm_expr
, s
);
11440 check_absolute_expr (ip
, &imm_expr
);
11441 min_range
= -((OP_MASK_OFFSET_A
+ 1) >> 1);
11442 max_range
= ((OP_MASK_OFFSET_A
+ 1) >> 1) - 1;
11443 if (imm_expr
.X_add_number
< min_range
11444 || imm_expr
.X_add_number
> max_range
)
11446 as_bad (_("Offset not in range %ld..%ld (%ld)"),
11447 (long) min_range
, (long) max_range
,
11448 (long) imm_expr
.X_add_number
);
11450 INSERT_OPERAND (0, OFFSET_A
, *ip
, imm_expr
.X_add_number
);
11451 imm_expr
.X_op
= O_absent
;
11455 case 'b': /* 8-bit signed offset in bit 3 */
11456 gas_assert (!mips_opts
.micromips
);
11457 my_getExpression (&imm_expr
, s
);
11458 check_absolute_expr (ip
, &imm_expr
);
11459 min_range
= -((OP_MASK_OFFSET_B
+ 1) >> 1);
11460 max_range
= ((OP_MASK_OFFSET_B
+ 1) >> 1) - 1;
11461 if (imm_expr
.X_add_number
< min_range
11462 || imm_expr
.X_add_number
> max_range
)
11464 as_bad (_("Offset not in range %ld..%ld (%ld)"),
11465 (long) min_range
, (long) max_range
,
11466 (long) imm_expr
.X_add_number
);
11468 INSERT_OPERAND (0, OFFSET_B
, *ip
, imm_expr
.X_add_number
);
11469 imm_expr
.X_op
= O_absent
;
11473 case 'c': /* 9-bit signed offset in bit 6 */
11474 gas_assert (!mips_opts
.micromips
);
11475 my_getExpression (&imm_expr
, s
);
11476 check_absolute_expr (ip
, &imm_expr
);
11477 min_range
= -((OP_MASK_OFFSET_C
+ 1) >> 1);
11478 max_range
= ((OP_MASK_OFFSET_C
+ 1) >> 1) - 1;
11479 /* We check the offset range before adjusted. */
11482 if (imm_expr
.X_add_number
< min_range
11483 || imm_expr
.X_add_number
> max_range
)
11485 as_bad (_("Offset not in range %ld..%ld (%ld)"),
11486 (long) min_range
, (long) max_range
,
11487 (long) imm_expr
.X_add_number
);
11489 if (imm_expr
.X_add_number
& 0xf)
11491 as_bad (_("Offset not 16 bytes alignment (%ld)"),
11492 (long) imm_expr
.X_add_number
);
11494 /* Right shift 4 bits to adjust the offset operand. */
11495 INSERT_OPERAND (0, OFFSET_C
, *ip
,
11496 imm_expr
.X_add_number
>> 4);
11497 imm_expr
.X_op
= O_absent
;
11502 gas_assert (!mips_opts
.micromips
);
11503 if (!reg_lookup (&s
, RTYPE_NUM
| RTYPE_GP
, ®no
))
11505 if (regno
== AT
&& mips_opts
.at
)
11507 if (mips_opts
.at
== ATREG
)
11508 as_warn (_("used $at without \".set noat\""));
11510 as_warn (_("used $%u with \".set at=$%u\""),
11511 regno
, mips_opts
.at
);
11513 INSERT_OPERAND (0, RZ
, *ip
, regno
);
11517 gas_assert (!mips_opts
.micromips
);
11518 if (!reg_lookup (&s
, RTYPE_FPU
, ®no
))
11520 INSERT_OPERAND (0, FZ
, *ip
, regno
);
11524 as_bad (_("Internal error: bad %s opcode "
11525 "(unknown extension operand type `+%c'): %s %s"),
11526 mips_opts
.micromips
? "microMIPS" : "MIPS",
11527 *args
, insn
->name
, insn
->args
);
11528 /* Further processing is fruitless. */
11533 case '.': /* 10-bit offset. */
11534 gas_assert (mips_opts
.micromips
);
11535 case '~': /* 12-bit offset. */
11537 int shift
= *args
== '.' ? 9 : 11;
11540 /* Check whether there is only a single bracketed expression
11541 left. If so, it must be the base register and the
11542 constant must be zero. */
11543 if (*s
== '(' && strchr (s
+ 1, '(') == 0)
11546 /* If this value won't fit into the offset, then go find
11547 a macro that will generate a 16- or 32-bit offset code
11549 i
= my_getSmallExpression (&imm_expr
, imm_reloc
, s
);
11550 if ((i
== 0 && (imm_expr
.X_op
!= O_constant
11551 || imm_expr
.X_add_number
>= 1 << shift
11552 || imm_expr
.X_add_number
< -1 << shift
))
11555 imm_expr
.X_op
= O_absent
;
11559 INSERT_OPERAND (1, OFFSET10
, *ip
, imm_expr
.X_add_number
);
11561 INSERT_OPERAND (mips_opts
.micromips
,
11562 OFFSET12
, *ip
, imm_expr
.X_add_number
);
11563 imm_expr
.X_op
= O_absent
;
11568 case '<': /* must be at least one digit */
11570 * According to the manual, if the shift amount is greater
11571 * than 31 or less than 0, then the shift amount should be
11572 * mod 32. In reality the mips assembler issues an error.
11573 * We issue a warning and mask out all but the low 5 bits.
11575 my_getExpression (&imm_expr
, s
);
11576 check_absolute_expr (ip
, &imm_expr
);
11577 if ((unsigned long) imm_expr
.X_add_number
> 31)
11578 as_warn (_("Improper shift amount (%lu)"),
11579 (unsigned long) imm_expr
.X_add_number
);
11580 INSERT_OPERAND (mips_opts
.micromips
,
11581 SHAMT
, *ip
, imm_expr
.X_add_number
);
11582 imm_expr
.X_op
= O_absent
;
11586 case '>': /* shift amount minus 32 */
11587 my_getExpression (&imm_expr
, s
);
11588 check_absolute_expr (ip
, &imm_expr
);
11589 if ((unsigned long) imm_expr
.X_add_number
< 32
11590 || (unsigned long) imm_expr
.X_add_number
> 63)
11592 INSERT_OPERAND (mips_opts
.micromips
,
11593 SHAMT
, *ip
, imm_expr
.X_add_number
- 32);
11594 imm_expr
.X_op
= O_absent
;
11598 case 'k': /* CACHE code. */
11599 case 'h': /* PREFX code. */
11600 case '1': /* SYNC type. */
11601 my_getExpression (&imm_expr
, s
);
11602 check_absolute_expr (ip
, &imm_expr
);
11603 if ((unsigned long) imm_expr
.X_add_number
> 31)
11604 as_warn (_("Invalid value for `%s' (%lu)"),
11606 (unsigned long) imm_expr
.X_add_number
);
11610 if (mips_fix_cn63xxp1
11611 && !mips_opts
.micromips
11612 && strcmp ("pref", insn
->name
) == 0)
11613 switch (imm_expr
.X_add_number
)
11622 case 31: /* These are ok. */
11625 default: /* The rest must be changed to 28. */
11626 imm_expr
.X_add_number
= 28;
11629 INSERT_OPERAND (mips_opts
.micromips
,
11630 CACHE
, *ip
, imm_expr
.X_add_number
);
11633 INSERT_OPERAND (mips_opts
.micromips
,
11634 PREFX
, *ip
, imm_expr
.X_add_number
);
11637 INSERT_OPERAND (mips_opts
.micromips
,
11638 STYPE
, *ip
, imm_expr
.X_add_number
);
11641 imm_expr
.X_op
= O_absent
;
11645 case 'c': /* BREAK code. */
11647 unsigned long mask
= (mips_opts
.micromips
11648 ? MICROMIPSOP_MASK_CODE
11651 my_getExpression (&imm_expr
, s
);
11652 check_absolute_expr (ip
, &imm_expr
);
11653 if ((unsigned long) imm_expr
.X_add_number
> mask
)
11654 as_warn (_("Code for %s not in range 0..%lu (%lu)"),
11656 mask
, (unsigned long) imm_expr
.X_add_number
);
11657 INSERT_OPERAND (mips_opts
.micromips
,
11658 CODE
, *ip
, imm_expr
.X_add_number
);
11659 imm_expr
.X_op
= O_absent
;
11664 case 'q': /* Lower BREAK code. */
11666 unsigned long mask
= (mips_opts
.micromips
11667 ? MICROMIPSOP_MASK_CODE2
11670 my_getExpression (&imm_expr
, s
);
11671 check_absolute_expr (ip
, &imm_expr
);
11672 if ((unsigned long) imm_expr
.X_add_number
> mask
)
11673 as_warn (_("Lower code for %s not in range 0..%lu (%lu)"),
11675 mask
, (unsigned long) imm_expr
.X_add_number
);
11676 INSERT_OPERAND (mips_opts
.micromips
,
11677 CODE2
, *ip
, imm_expr
.X_add_number
);
11678 imm_expr
.X_op
= O_absent
;
11683 case 'B': /* 20- or 10-bit syscall/break/wait code. */
11685 unsigned long mask
= (mips_opts
.micromips
11686 ? MICROMIPSOP_MASK_CODE10
11689 my_getExpression (&imm_expr
, s
);
11690 check_absolute_expr (ip
, &imm_expr
);
11691 if ((unsigned long) imm_expr
.X_add_number
> mask
)
11692 as_warn (_("Code for %s not in range 0..%lu (%lu)"),
11694 mask
, (unsigned long) imm_expr
.X_add_number
);
11695 if (mips_opts
.micromips
)
11696 INSERT_OPERAND (1, CODE10
, *ip
, imm_expr
.X_add_number
);
11698 INSERT_OPERAND (0, CODE20
, *ip
, imm_expr
.X_add_number
);
11699 imm_expr
.X_op
= O_absent
;
11704 case 'C': /* 25- or 23-bit coprocessor code. */
11706 unsigned long mask
= (mips_opts
.micromips
11707 ? MICROMIPSOP_MASK_COPZ
11710 my_getExpression (&imm_expr
, s
);
11711 check_absolute_expr (ip
, &imm_expr
);
11712 if ((unsigned long) imm_expr
.X_add_number
> mask
)
11713 as_warn (_("Coproccesor code > %u bits (%lu)"),
11714 mips_opts
.micromips
? 23U : 25U,
11715 (unsigned long) imm_expr
.X_add_number
);
11716 INSERT_OPERAND (mips_opts
.micromips
,
11717 COPZ
, *ip
, imm_expr
.X_add_number
);
11718 imm_expr
.X_op
= O_absent
;
11723 case 'J': /* 19-bit WAIT code. */
11724 gas_assert (!mips_opts
.micromips
);
11725 my_getExpression (&imm_expr
, s
);
11726 check_absolute_expr (ip
, &imm_expr
);
11727 if ((unsigned long) imm_expr
.X_add_number
> OP_MASK_CODE19
)
11729 as_warn (_("Illegal 19-bit code (%lu)"),
11730 (unsigned long) imm_expr
.X_add_number
);
11731 imm_expr
.X_add_number
&= OP_MASK_CODE19
;
11733 INSERT_OPERAND (0, CODE19
, *ip
, imm_expr
.X_add_number
);
11734 imm_expr
.X_op
= O_absent
;
11738 case 'P': /* Performance register. */
11739 gas_assert (!mips_opts
.micromips
);
11740 my_getExpression (&imm_expr
, s
);
11741 check_absolute_expr (ip
, &imm_expr
);
11742 if (imm_expr
.X_add_number
!= 0 && imm_expr
.X_add_number
!= 1)
11743 as_warn (_("Invalid performance register (%lu)"),
11744 (unsigned long) imm_expr
.X_add_number
);
11745 INSERT_OPERAND (0, PERFREG
, *ip
, imm_expr
.X_add_number
);
11746 imm_expr
.X_op
= O_absent
;
11750 case 'G': /* Coprocessor destination register. */
11752 unsigned long opcode
= ip
->insn_opcode
;
11753 unsigned long mask
;
11754 unsigned int types
;
11757 if (mips_opts
.micromips
)
11759 mask
= ~((MICROMIPSOP_MASK_RT
<< MICROMIPSOP_SH_RT
)
11760 | (MICROMIPSOP_MASK_RS
<< MICROMIPSOP_SH_RS
)
11761 | (MICROMIPSOP_MASK_SEL
<< MICROMIPSOP_SH_SEL
));
11765 case 0x000000fc: /* mfc0 */
11766 case 0x000002fc: /* mtc0 */
11767 case 0x580000fc: /* dmfc0 */
11768 case 0x580002fc: /* dmtc0 */
11778 opcode
= (opcode
>> OP_SH_OP
) & OP_MASK_OP
;
11779 cop0
= opcode
== OP_OP_COP0
;
11781 types
= RTYPE_NUM
| (cop0
? RTYPE_CP0
: RTYPE_GP
);
11782 ok
= reg_lookup (&s
, types
, ®no
);
11783 if (mips_opts
.micromips
)
11784 INSERT_OPERAND (1, RS
, *ip
, regno
);
11786 INSERT_OPERAND (0, RD
, *ip
, regno
);
11795 case 'y': /* ALNV.PS source register. */
11796 gas_assert (mips_opts
.micromips
);
11798 case 'x': /* Ignore register name. */
11799 case 'U': /* Destination register (CLO/CLZ). */
11800 case 'g': /* Coprocessor destination register. */
11801 gas_assert (!mips_opts
.micromips
);
11802 case 'b': /* Base register. */
11803 case 'd': /* Destination register. */
11804 case 's': /* Source register. */
11805 case 't': /* Target register. */
11806 case 'r': /* Both target and source. */
11807 case 'v': /* Both dest and source. */
11808 case 'w': /* Both dest and target. */
11809 case 'E': /* Coprocessor target register. */
11810 case 'K': /* RDHWR destination register. */
11811 case 'z': /* Must be zero register. */
11814 if (*args
== 'E' || *args
== 'K')
11815 ok
= reg_lookup (&s
, RTYPE_NUM
, ®no
);
11818 ok
= reg_lookup (&s
, RTYPE_NUM
| RTYPE_GP
, ®no
);
11819 if (regno
== AT
&& mips_opts
.at
)
11821 if (mips_opts
.at
== ATREG
)
11822 as_warn (_("Used $at without \".set noat\""));
11824 as_warn (_("Used $%u with \".set at=$%u\""),
11825 regno
, mips_opts
.at
);
11835 if (c
== 'r' || c
== 'v' || c
== 'w')
11842 /* 'z' only matches $0. */
11843 if (c
== 'z' && regno
!= 0)
11846 if (c
== 's' && !strncmp (ip
->insn_mo
->name
, "jalr", 4))
11848 if (regno
== lastregno
)
11851 = _("Source and destination must be different");
11854 if (regno
== 31 && lastregno
== 0xffffffff)
11857 = _("A destination register must be supplied");
11861 /* Now that we have assembled one operand, we use the args
11862 string to figure out where it goes in the instruction. */
11869 INSERT_OPERAND (mips_opts
.micromips
, RS
, *ip
, regno
);
11873 if (mips_opts
.micromips
)
11874 INSERT_OPERAND (1, RS
, *ip
, regno
);
11876 INSERT_OPERAND (0, RD
, *ip
, regno
);
11881 INSERT_OPERAND (mips_opts
.micromips
, RD
, *ip
, regno
);
11885 gas_assert (!mips_opts
.micromips
);
11886 INSERT_OPERAND (0, RD
, *ip
, regno
);
11887 INSERT_OPERAND (0, RT
, *ip
, regno
);
11893 INSERT_OPERAND (mips_opts
.micromips
, RT
, *ip
, regno
);
11897 gas_assert (mips_opts
.micromips
);
11898 INSERT_OPERAND (1, RS3
, *ip
, regno
);
11902 /* This case exists because on the r3000 trunc
11903 expands into a macro which requires a gp
11904 register. On the r6000 or r4000 it is
11905 assembled into a single instruction which
11906 ignores the register. Thus the insn version
11907 is MIPS_ISA2 and uses 'x', and the macro
11908 version is MIPS_ISA1 and uses 't'. */
11912 /* This case is for the div instruction, which
11913 acts differently if the destination argument
11914 is $0. This only matches $0, and is checked
11915 outside the switch. */
11925 INSERT_OPERAND (mips_opts
.micromips
, RS
, *ip
, lastregno
);
11929 INSERT_OPERAND (mips_opts
.micromips
, RT
, *ip
, lastregno
);
11934 case 'O': /* MDMX alignment immediate constant. */
11935 gas_assert (!mips_opts
.micromips
);
11936 my_getExpression (&imm_expr
, s
);
11937 check_absolute_expr (ip
, &imm_expr
);
11938 if ((unsigned long) imm_expr
.X_add_number
> OP_MASK_ALN
)
11939 as_warn (_("Improper align amount (%ld), using low bits"),
11940 (long) imm_expr
.X_add_number
);
11941 INSERT_OPERAND (0, ALN
, *ip
, imm_expr
.X_add_number
);
11942 imm_expr
.X_op
= O_absent
;
11946 case 'Q': /* MDMX vector, element sel, or const. */
11949 /* MDMX Immediate. */
11950 gas_assert (!mips_opts
.micromips
);
11951 my_getExpression (&imm_expr
, s
);
11952 check_absolute_expr (ip
, &imm_expr
);
11953 if ((unsigned long) imm_expr
.X_add_number
> OP_MASK_FT
)
11954 as_warn (_("Invalid MDMX Immediate (%ld)"),
11955 (long) imm_expr
.X_add_number
);
11956 INSERT_OPERAND (0, FT
, *ip
, imm_expr
.X_add_number
);
11957 if (ip
->insn_opcode
& (OP_MASK_VSEL
<< OP_SH_VSEL
))
11958 ip
->insn_opcode
|= MDMX_FMTSEL_IMM_QH
<< OP_SH_VSEL
;
11960 ip
->insn_opcode
|= MDMX_FMTSEL_IMM_OB
<< OP_SH_VSEL
;
11961 imm_expr
.X_op
= O_absent
;
11965 /* Not MDMX Immediate. Fall through. */
11966 case 'X': /* MDMX destination register. */
11967 case 'Y': /* MDMX source register. */
11968 case 'Z': /* MDMX target register. */
11971 gas_assert (!mips_opts
.micromips
);
11972 case 'D': /* Floating point destination register. */
11973 case 'S': /* Floating point source register. */
11974 case 'T': /* Floating point target register. */
11975 case 'R': /* Floating point source register. */
11979 || (mips_opts
.ase_mdmx
11980 && (ip
->insn_mo
->pinfo
& FP_D
)
11981 && (ip
->insn_mo
->pinfo
& (INSN_COPROC_MOVE_DELAY
11982 | INSN_COPROC_MEMORY_DELAY
11983 | INSN_LOAD_COPROC_DELAY
11984 | INSN_LOAD_MEMORY_DELAY
11985 | INSN_STORE_MEMORY
))))
11986 rtype
|= RTYPE_VEC
;
11988 if (reg_lookup (&s
, rtype
, ®no
))
11990 if ((regno
& 1) != 0
11992 && !mips_oddfpreg_ok (ip
->insn_mo
, argnum
))
11993 as_warn (_("Float register should be even, was %d"),
12001 if (c
== 'V' || c
== 'W')
12012 INSERT_OPERAND (mips_opts
.micromips
, FD
, *ip
, regno
);
12018 INSERT_OPERAND (mips_opts
.micromips
, FS
, *ip
, regno
);
12022 /* This is like 'Z', but also needs to fix the MDMX
12023 vector/scalar select bits. Note that the
12024 scalar immediate case is handled above. */
12027 int is_qh
= (ip
->insn_opcode
& (1 << OP_SH_VSEL
));
12028 int max_el
= (is_qh
? 3 : 7);
12030 my_getExpression(&imm_expr
, s
);
12031 check_absolute_expr (ip
, &imm_expr
);
12033 if (imm_expr
.X_add_number
> max_el
)
12034 as_bad (_("Bad element selector %ld"),
12035 (long) imm_expr
.X_add_number
);
12036 imm_expr
.X_add_number
&= max_el
;
12037 ip
->insn_opcode
|= (imm_expr
.X_add_number
12040 imm_expr
.X_op
= O_absent
;
12042 as_warn (_("Expecting ']' found '%s'"), s
);
12048 if (ip
->insn_opcode
& (OP_MASK_VSEL
<< OP_SH_VSEL
))
12049 ip
->insn_opcode
|= (MDMX_FMTSEL_VEC_QH
12052 ip
->insn_opcode
|= (MDMX_FMTSEL_VEC_OB
<<
12055 /* Fall through. */
12059 INSERT_OPERAND (mips_opts
.micromips
, FT
, *ip
, regno
);
12063 INSERT_OPERAND (mips_opts
.micromips
, FR
, *ip
, regno
);
12073 INSERT_OPERAND (mips_opts
.micromips
, FS
, *ip
, lastregno
);
12077 INSERT_OPERAND (mips_opts
.micromips
, FT
, *ip
, lastregno
);
12083 my_getExpression (&imm_expr
, s
);
12084 if (imm_expr
.X_op
!= O_big
12085 && imm_expr
.X_op
!= O_constant
)
12086 insn_error
= _("absolute expression required");
12087 if (HAVE_32BIT_GPRS
)
12088 normalize_constant_expr (&imm_expr
);
12093 my_getExpression (&offset_expr
, s
);
12094 normalize_address_expr (&offset_expr
);
12095 *imm_reloc
= BFD_RELOC_32
;
12108 unsigned char temp
[8];
12110 unsigned int length
;
12115 /* These only appear as the last operand in an
12116 instruction, and every instruction that accepts
12117 them in any variant accepts them in all variants.
12118 This means we don't have to worry about backing out
12119 any changes if the instruction does not match.
12121 The difference between them is the size of the
12122 floating point constant and where it goes. For 'F'
12123 and 'L' the constant is 64 bits; for 'f' and 'l' it
12124 is 32 bits. Where the constant is placed is based
12125 on how the MIPS assembler does things:
12128 f -- immediate value
12131 The .lit4 and .lit8 sections are only used if
12132 permitted by the -G argument.
12134 The code below needs to know whether the target register
12135 is 32 or 64 bits wide. It relies on the fact 'f' and
12136 'F' are used with GPR-based instructions and 'l' and
12137 'L' are used with FPR-based instructions. */
12139 f64
= *args
== 'F' || *args
== 'L';
12140 using_gprs
= *args
== 'F' || *args
== 'f';
12142 save_in
= input_line_pointer
;
12143 input_line_pointer
= s
;
12144 err
= md_atof (f64
? 'd' : 'f', (char *) temp
, &len
);
12146 s
= input_line_pointer
;
12147 input_line_pointer
= save_in
;
12148 if (err
!= NULL
&& *err
!= '\0')
12150 as_bad (_("Bad floating point constant: %s"), err
);
12151 memset (temp
, '\0', sizeof temp
);
12152 length
= f64
? 8 : 4;
12155 gas_assert (length
== (unsigned) (f64
? 8 : 4));
12159 && (g_switch_value
< 4
12160 || (temp
[0] == 0 && temp
[1] == 0)
12161 || (temp
[2] == 0 && temp
[3] == 0))))
12163 imm_expr
.X_op
= O_constant
;
12164 if (!target_big_endian
)
12165 imm_expr
.X_add_number
= bfd_getl32 (temp
);
12167 imm_expr
.X_add_number
= bfd_getb32 (temp
);
12169 else if (length
> 4
12170 && !mips_disable_float_construction
12171 /* Constants can only be constructed in GPRs and
12172 copied to FPRs if the GPRs are at least as wide
12173 as the FPRs. Force the constant into memory if
12174 we are using 64-bit FPRs but the GPRs are only
12177 || !(HAVE_64BIT_FPRS
&& HAVE_32BIT_GPRS
))
12178 && ((temp
[0] == 0 && temp
[1] == 0)
12179 || (temp
[2] == 0 && temp
[3] == 0))
12180 && ((temp
[4] == 0 && temp
[5] == 0)
12181 || (temp
[6] == 0 && temp
[7] == 0)))
12183 /* The value is simple enough to load with a couple of
12184 instructions. If using 32-bit registers, set
12185 imm_expr to the high order 32 bits and offset_expr to
12186 the low order 32 bits. Otherwise, set imm_expr to
12187 the entire 64 bit constant. */
12188 if (using_gprs
? HAVE_32BIT_GPRS
: HAVE_32BIT_FPRS
)
12190 imm_expr
.X_op
= O_constant
;
12191 offset_expr
.X_op
= O_constant
;
12192 if (!target_big_endian
)
12194 imm_expr
.X_add_number
= bfd_getl32 (temp
+ 4);
12195 offset_expr
.X_add_number
= bfd_getl32 (temp
);
12199 imm_expr
.X_add_number
= bfd_getb32 (temp
);
12200 offset_expr
.X_add_number
= bfd_getb32 (temp
+ 4);
12202 if (offset_expr
.X_add_number
== 0)
12203 offset_expr
.X_op
= O_absent
;
12205 else if (sizeof (imm_expr
.X_add_number
) > 4)
12207 imm_expr
.X_op
= O_constant
;
12208 if (!target_big_endian
)
12209 imm_expr
.X_add_number
= bfd_getl64 (temp
);
12211 imm_expr
.X_add_number
= bfd_getb64 (temp
);
12215 imm_expr
.X_op
= O_big
;
12216 imm_expr
.X_add_number
= 4;
12217 if (!target_big_endian
)
12219 generic_bignum
[0] = bfd_getl16 (temp
);
12220 generic_bignum
[1] = bfd_getl16 (temp
+ 2);
12221 generic_bignum
[2] = bfd_getl16 (temp
+ 4);
12222 generic_bignum
[3] = bfd_getl16 (temp
+ 6);
12226 generic_bignum
[0] = bfd_getb16 (temp
+ 6);
12227 generic_bignum
[1] = bfd_getb16 (temp
+ 4);
12228 generic_bignum
[2] = bfd_getb16 (temp
+ 2);
12229 generic_bignum
[3] = bfd_getb16 (temp
);
12235 const char *newname
;
12238 /* Switch to the right section. */
12240 subseg
= now_subseg
;
12243 default: /* unused default case avoids warnings. */
12245 newname
= RDATA_SECTION_NAME
;
12246 if (g_switch_value
>= 8)
12250 newname
= RDATA_SECTION_NAME
;
12253 gas_assert (g_switch_value
>= 4);
12257 new_seg
= subseg_new (newname
, (subsegT
) 0);
12259 bfd_set_section_flags (stdoutput
, new_seg
,
12264 frag_align (*args
== 'l' ? 2 : 3, 0, 0);
12265 if (IS_ELF
&& strncmp (TARGET_OS
, "elf", 3) != 0)
12266 record_alignment (new_seg
, 4);
12268 record_alignment (new_seg
, *args
== 'l' ? 2 : 3);
12269 if (seg
== now_seg
)
12270 as_bad (_("Can't use floating point insn in this section"));
12272 /* Set the argument to the current address in the
12274 offset_expr
.X_op
= O_symbol
;
12275 offset_expr
.X_add_symbol
= symbol_temp_new_now ();
12276 offset_expr
.X_add_number
= 0;
12278 /* Put the floating point number into the section. */
12279 p
= frag_more ((int) length
);
12280 memcpy (p
, temp
, length
);
12282 /* Switch back to the original section. */
12283 subseg_set (seg
, subseg
);
12288 case 'i': /* 16-bit unsigned immediate. */
12289 case 'j': /* 16-bit signed immediate. */
12290 *imm_reloc
= BFD_RELOC_LO16
;
12291 if (my_getSmallExpression (&imm_expr
, imm_reloc
, s
) == 0)
12294 offsetT minval
, maxval
;
12296 more
= (insn
+ 1 < past
12297 && strcmp (insn
->name
, insn
[1].name
) == 0);
12299 /* If the expression was written as an unsigned number,
12300 only treat it as signed if there are no more
12304 && sizeof (imm_expr
.X_add_number
) <= 4
12305 && imm_expr
.X_op
== O_constant
12306 && imm_expr
.X_add_number
< 0
12307 && imm_expr
.X_unsigned
12308 && HAVE_64BIT_GPRS
)
12311 /* For compatibility with older assemblers, we accept
12312 0x8000-0xffff as signed 16-bit numbers when only
12313 signed numbers are allowed. */
12315 minval
= 0, maxval
= 0xffff;
12317 minval
= -0x8000, maxval
= 0x7fff;
12319 minval
= -0x8000, maxval
= 0xffff;
12321 if (imm_expr
.X_op
!= O_constant
12322 || imm_expr
.X_add_number
< minval
12323 || imm_expr
.X_add_number
> maxval
)
12327 if (imm_expr
.X_op
== O_constant
12328 || imm_expr
.X_op
== O_big
)
12329 as_bad (_("Expression out of range"));
12335 case 'o': /* 16-bit offset. */
12336 offset_reloc
[0] = BFD_RELOC_LO16
;
12337 offset_reloc
[1] = BFD_RELOC_UNUSED
;
12338 offset_reloc
[2] = BFD_RELOC_UNUSED
;
12340 /* Check whether there is only a single bracketed expression
12341 left. If so, it must be the base register and the
12342 constant must be zero. */
12343 if (*s
== '(' && strchr (s
+ 1, '(') == 0)
12345 offset_expr
.X_op
= O_constant
;
12346 offset_expr
.X_add_number
= 0;
12350 /* If this value won't fit into a 16 bit offset, then go
12351 find a macro that will generate the 32 bit offset
12353 if (my_getSmallExpression (&offset_expr
, offset_reloc
, s
) == 0
12354 && (offset_expr
.X_op
!= O_constant
12355 || offset_expr
.X_add_number
>= 0x8000
12356 || offset_expr
.X_add_number
< -0x8000))
12362 case 'p': /* PC-relative offset. */
12363 *offset_reloc
= BFD_RELOC_16_PCREL_S2
;
12364 my_getExpression (&offset_expr
, s
);
12368 case 'u': /* Upper 16 bits. */
12369 if (my_getSmallExpression (&imm_expr
, imm_reloc
, s
) == 0
12370 && imm_expr
.X_op
== O_constant
12371 && (imm_expr
.X_add_number
< 0
12372 || imm_expr
.X_add_number
>= 0x10000))
12373 as_bad (_("lui expression (%lu) not in range 0..65535"),
12374 (unsigned long) imm_expr
.X_add_number
);
12378 case 'a': /* 26-bit address. */
12379 *offset_reloc
= BFD_RELOC_MIPS_JMP
;
12380 my_getExpression (&offset_expr
, s
);
12384 case 'N': /* 3-bit branch condition code. */
12385 case 'M': /* 3-bit compare condition code. */
12387 if (ip
->insn_mo
->pinfo
& (FP_D
| FP_S
))
12388 rtype
|= RTYPE_FCC
;
12389 if (!reg_lookup (&s
, rtype
, ®no
))
12391 if ((strcmp (str
+ strlen (str
) - 3, ".ps") == 0
12392 || strcmp (str
+ strlen (str
) - 5, "any2f") == 0
12393 || strcmp (str
+ strlen (str
) - 5, "any2t") == 0)
12394 && (regno
& 1) != 0)
12395 as_warn (_("Condition code register should be even for %s, "
12398 if ((strcmp (str
+ strlen (str
) - 5, "any4f") == 0
12399 || strcmp (str
+ strlen (str
) - 5, "any4t") == 0)
12400 && (regno
& 3) != 0)
12401 as_warn (_("Condition code register should be 0 or 4 for %s, "
12405 INSERT_OPERAND (mips_opts
.micromips
, BCC
, *ip
, regno
);
12407 INSERT_OPERAND (mips_opts
.micromips
, CCC
, *ip
, regno
);
12411 if (s
[0] == '0' && (s
[1] == 'x' || s
[1] == 'X'))
12422 while (ISDIGIT (*s
));
12425 c
= 8; /* Invalid sel value. */
12428 as_bad (_("Invalid coprocessor sub-selection value (0-7)"));
12429 INSERT_OPERAND (mips_opts
.micromips
, SEL
, *ip
, c
);
12433 gas_assert (!mips_opts
.micromips
);
12434 /* Must be at least one digit. */
12435 my_getExpression (&imm_expr
, s
);
12436 check_absolute_expr (ip
, &imm_expr
);
12438 if ((unsigned long) imm_expr
.X_add_number
12439 > (unsigned long) OP_MASK_VECBYTE
)
12441 as_bad (_("bad byte vector index (%ld)"),
12442 (long) imm_expr
.X_add_number
);
12443 imm_expr
.X_add_number
= 0;
12446 INSERT_OPERAND (0, VECBYTE
, *ip
, imm_expr
.X_add_number
);
12447 imm_expr
.X_op
= O_absent
;
12452 gas_assert (!mips_opts
.micromips
);
12453 my_getExpression (&imm_expr
, s
);
12454 check_absolute_expr (ip
, &imm_expr
);
12456 if ((unsigned long) imm_expr
.X_add_number
12457 > (unsigned long) OP_MASK_VECALIGN
)
12459 as_bad (_("bad byte vector index (%ld)"),
12460 (long) imm_expr
.X_add_number
);
12461 imm_expr
.X_add_number
= 0;
12464 INSERT_OPERAND (0, VECALIGN
, *ip
, imm_expr
.X_add_number
);
12465 imm_expr
.X_op
= O_absent
;
12469 case 'm': /* Opcode extension character. */
12470 gas_assert (mips_opts
.micromips
);
12475 if (strncmp (s
, "$pc", 3) == 0)
12503 ok
= reg_lookup (&s
, RTYPE_NUM
| RTYPE_GP
, ®no
);
12504 if (regno
== AT
&& mips_opts
.at
)
12506 if (mips_opts
.at
== ATREG
)
12507 as_warn (_("Used $at without \".set noat\""));
12509 as_warn (_("Used $%u with \".set at=$%u\""),
12510 regno
, mips_opts
.at
);
12516 gas_assert (args
[1] == ',');
12522 gas_assert (args
[1] == ',');
12524 continue; /* Nothing to do. */
12530 if (c
== 'j' && !strncmp (ip
->insn_mo
->name
, "jalr", 4))
12532 if (regno
== lastregno
)
12535 = _("Source and destination must be different");
12538 if (regno
== 31 && lastregno
== 0xffffffff)
12541 = _("A destination register must be supplied");
12552 gas_assert (args
[1] == ',');
12559 gas_assert (args
[1] == ',');
12562 continue; /* Nothing to do. */
12566 /* Make sure regno is the same as lastregno. */
12567 if (c
== 't' && regno
!= lastregno
)
12570 /* Make sure regno is the same as destregno. */
12571 if (c
== 'x' && regno
!= destregno
)
12574 /* We need to save regno, before regno maps to the
12575 microMIPS register encoding. */
12585 regno
= ILLEGAL_REG
;
12589 regno
= mips32_to_micromips_reg_b_map
[regno
];
12593 regno
= mips32_to_micromips_reg_c_map
[regno
];
12597 regno
= mips32_to_micromips_reg_d_map
[regno
];
12601 regno
= mips32_to_micromips_reg_e_map
[regno
];
12605 regno
= mips32_to_micromips_reg_f_map
[regno
];
12609 regno
= mips32_to_micromips_reg_g_map
[regno
];
12613 regno
= mips32_to_micromips_reg_h_map
[regno
];
12617 switch (EXTRACT_OPERAND (1, MI
, *ip
))
12622 else if (regno
== 22)
12624 else if (regno
== 5)
12626 else if (regno
== 6)
12628 else if (regno
== 7)
12631 regno
= ILLEGAL_REG
;
12637 else if (regno
== 7)
12640 regno
= ILLEGAL_REG
;
12647 regno
= ILLEGAL_REG
;
12651 regno
= ILLEGAL_REG
;
12657 regno
= mips32_to_micromips_reg_l_map
[regno
];
12661 regno
= mips32_to_micromips_reg_m_map
[regno
];
12665 regno
= mips32_to_micromips_reg_n_map
[regno
];
12669 regno
= mips32_to_micromips_reg_q_map
[regno
];
12674 regno
= ILLEGAL_REG
;
12679 regno
= ILLEGAL_REG
;
12684 regno
= ILLEGAL_REG
;
12687 case 'j': /* Do nothing. */
12697 if (regno
== ILLEGAL_REG
)
12703 INSERT_OPERAND (1, MB
, *ip
, regno
);
12707 INSERT_OPERAND (1, MC
, *ip
, regno
);
12711 INSERT_OPERAND (1, MD
, *ip
, regno
);
12715 INSERT_OPERAND (1, ME
, *ip
, regno
);
12719 INSERT_OPERAND (1, MF
, *ip
, regno
);
12723 INSERT_OPERAND (1, MG
, *ip
, regno
);
12727 INSERT_OPERAND (1, MH
, *ip
, regno
);
12731 INSERT_OPERAND (1, MI
, *ip
, regno
);
12735 INSERT_OPERAND (1, MJ
, *ip
, regno
);
12739 INSERT_OPERAND (1, ML
, *ip
, regno
);
12743 INSERT_OPERAND (1, MM
, *ip
, regno
);
12747 INSERT_OPERAND (1, MN
, *ip
, regno
);
12751 INSERT_OPERAND (1, MP
, *ip
, regno
);
12755 INSERT_OPERAND (1, MQ
, *ip
, regno
);
12758 case 'a': /* Do nothing. */
12759 case 's': /* Do nothing. */
12760 case 't': /* Do nothing. */
12761 case 'x': /* Do nothing. */
12762 case 'y': /* Do nothing. */
12763 case 'z': /* Do nothing. */
12773 bfd_reloc_code_real_type r
[3];
12777 /* Check whether there is only a single bracketed
12778 expression left. If so, it must be the base register
12779 and the constant must be zero. */
12780 if (*s
== '(' && strchr (s
+ 1, '(') == 0)
12782 INSERT_OPERAND (1, IMMA
, *ip
, 0);
12786 if (my_getSmallExpression (&ep
, r
, s
) > 0
12787 || !expr_const_in_range (&ep
, -64, 64, 2))
12790 imm
= ep
.X_add_number
>> 2;
12791 INSERT_OPERAND (1, IMMA
, *ip
, imm
);
12798 bfd_reloc_code_real_type r
[3];
12802 if (my_getSmallExpression (&ep
, r
, s
) > 0
12803 || ep
.X_op
!= O_constant
)
12806 for (imm
= 0; imm
< 8; imm
++)
12807 if (micromips_imm_b_map
[imm
] == ep
.X_add_number
)
12812 INSERT_OPERAND (1, IMMB
, *ip
, imm
);
12819 bfd_reloc_code_real_type r
[3];
12823 if (my_getSmallExpression (&ep
, r
, s
) > 0
12824 || ep
.X_op
!= O_constant
)
12827 for (imm
= 0; imm
< 16; imm
++)
12828 if (micromips_imm_c_map
[imm
] == ep
.X_add_number
)
12833 INSERT_OPERAND (1, IMMC
, *ip
, imm
);
12838 case 'D': /* pc relative offset */
12839 case 'E': /* pc relative offset */
12840 my_getExpression (&offset_expr
, s
);
12841 if (offset_expr
.X_op
== O_register
)
12844 if (!forced_insn_length
)
12845 *offset_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
12847 *offset_reloc
= BFD_RELOC_MICROMIPS_10_PCREL_S1
;
12849 *offset_reloc
= BFD_RELOC_MICROMIPS_7_PCREL_S1
;
12855 bfd_reloc_code_real_type r
[3];
12859 if (my_getSmallExpression (&ep
, r
, s
) > 0
12860 || !expr_const_in_range (&ep
, 0, 16, 0))
12863 imm
= ep
.X_add_number
;
12864 INSERT_OPERAND (1, IMMF
, *ip
, imm
);
12871 bfd_reloc_code_real_type r
[3];
12875 /* Check whether there is only a single bracketed
12876 expression left. If so, it must be the base register
12877 and the constant must be zero. */
12878 if (*s
== '(' && strchr (s
+ 1, '(') == 0)
12880 INSERT_OPERAND (1, IMMG
, *ip
, 0);
12884 if (my_getSmallExpression (&ep
, r
, s
) > 0
12885 || !expr_const_in_range (&ep
, -1, 15, 0))
12888 imm
= ep
.X_add_number
& 15;
12889 INSERT_OPERAND (1, IMMG
, *ip
, imm
);
12896 bfd_reloc_code_real_type r
[3];
12900 /* Check whether there is only a single bracketed
12901 expression left. If so, it must be the base register
12902 and the constant must be zero. */
12903 if (*s
== '(' && strchr (s
+ 1, '(') == 0)
12905 INSERT_OPERAND (1, IMMH
, *ip
, 0);
12909 if (my_getSmallExpression (&ep
, r
, s
) > 0
12910 || !expr_const_in_range (&ep
, 0, 16, 1))
12913 imm
= ep
.X_add_number
>> 1;
12914 INSERT_OPERAND (1, IMMH
, *ip
, imm
);
12921 bfd_reloc_code_real_type r
[3];
12925 if (my_getSmallExpression (&ep
, r
, s
) > 0
12926 || !expr_const_in_range (&ep
, -1, 127, 0))
12929 imm
= ep
.X_add_number
& 127;
12930 INSERT_OPERAND (1, IMMI
, *ip
, imm
);
12937 bfd_reloc_code_real_type r
[3];
12941 /* Check whether there is only a single bracketed
12942 expression left. If so, it must be the base register
12943 and the constant must be zero. */
12944 if (*s
== '(' && strchr (s
+ 1, '(') == 0)
12946 INSERT_OPERAND (1, IMMJ
, *ip
, 0);
12950 if (my_getSmallExpression (&ep
, r
, s
) > 0
12951 || !expr_const_in_range (&ep
, 0, 16, 2))
12954 imm
= ep
.X_add_number
>> 2;
12955 INSERT_OPERAND (1, IMMJ
, *ip
, imm
);
12962 bfd_reloc_code_real_type r
[3];
12966 /* Check whether there is only a single bracketed
12967 expression left. If so, it must be the base register
12968 and the constant must be zero. */
12969 if (*s
== '(' && strchr (s
+ 1, '(') == 0)
12971 INSERT_OPERAND (1, IMML
, *ip
, 0);
12975 if (my_getSmallExpression (&ep
, r
, s
) > 0
12976 || !expr_const_in_range (&ep
, 0, 16, 0))
12979 imm
= ep
.X_add_number
;
12980 INSERT_OPERAND (1, IMML
, *ip
, imm
);
12987 bfd_reloc_code_real_type r
[3];
12991 if (my_getSmallExpression (&ep
, r
, s
) > 0
12992 || !expr_const_in_range (&ep
, 1, 9, 0))
12995 imm
= ep
.X_add_number
& 7;
12996 INSERT_OPERAND (1, IMMM
, *ip
, imm
);
13001 case 'N': /* Register list for lwm and swm. */
13003 /* A comma-separated list of registers and/or
13004 dash-separated contiguous ranges including
13005 both ra and a set of one or more registers
13006 starting at s0 up to s3 which have to be
13013 and any permutations of these. */
13014 unsigned int reglist
;
13017 if (!reglist_lookup (&s
, RTYPE_NUM
| RTYPE_GP
, ®list
))
13020 if ((reglist
& 0xfff1ffff) != 0x80010000)
13023 reglist
= (reglist
>> 17) & 7;
13025 if ((reglist
& -reglist
) != reglist
)
13028 imm
= ffs (reglist
) - 1;
13029 INSERT_OPERAND (1, IMMN
, *ip
, imm
);
13033 case 'O': /* sdbbp 4-bit code. */
13035 bfd_reloc_code_real_type r
[3];
13039 if (my_getSmallExpression (&ep
, r
, s
) > 0
13040 || !expr_const_in_range (&ep
, 0, 16, 0))
13043 imm
= ep
.X_add_number
;
13044 INSERT_OPERAND (1, IMMO
, *ip
, imm
);
13051 bfd_reloc_code_real_type r
[3];
13055 if (my_getSmallExpression (&ep
, r
, s
) > 0
13056 || !expr_const_in_range (&ep
, 0, 32, 2))
13059 imm
= ep
.X_add_number
>> 2;
13060 INSERT_OPERAND (1, IMMP
, *ip
, imm
);
13067 bfd_reloc_code_real_type r
[3];
13071 if (my_getSmallExpression (&ep
, r
, s
) > 0
13072 || !expr_const_in_range (&ep
, -0x400000, 0x400000, 2))
13075 imm
= ep
.X_add_number
>> 2;
13076 INSERT_OPERAND (1, IMMQ
, *ip
, imm
);
13083 bfd_reloc_code_real_type r
[3];
13087 /* Check whether there is only a single bracketed
13088 expression left. If so, it must be the base register
13089 and the constant must be zero. */
13090 if (*s
== '(' && strchr (s
+ 1, '(') == 0)
13092 INSERT_OPERAND (1, IMMU
, *ip
, 0);
13096 if (my_getSmallExpression (&ep
, r
, s
) > 0
13097 || !expr_const_in_range (&ep
, 0, 32, 2))
13100 imm
= ep
.X_add_number
>> 2;
13101 INSERT_OPERAND (1, IMMU
, *ip
, imm
);
13108 bfd_reloc_code_real_type r
[3];
13112 if (my_getSmallExpression (&ep
, r
, s
) > 0
13113 || !expr_const_in_range (&ep
, 0, 64, 2))
13116 imm
= ep
.X_add_number
>> 2;
13117 INSERT_OPERAND (1, IMMW
, *ip
, imm
);
13124 bfd_reloc_code_real_type r
[3];
13128 if (my_getSmallExpression (&ep
, r
, s
) > 0
13129 || !expr_const_in_range (&ep
, -8, 8, 0))
13132 imm
= ep
.X_add_number
;
13133 INSERT_OPERAND (1, IMMX
, *ip
, imm
);
13140 bfd_reloc_code_real_type r
[3];
13144 if (my_getSmallExpression (&ep
, r
, s
) > 0
13145 || expr_const_in_range (&ep
, -2, 2, 2)
13146 || !expr_const_in_range (&ep
, -258, 258, 2))
13149 imm
= ep
.X_add_number
>> 2;
13150 imm
= ((imm
>> 1) & ~0xff) | (imm
& 0xff);
13151 INSERT_OPERAND (1, IMMY
, *ip
, imm
);
13158 bfd_reloc_code_real_type r
[3];
13161 if (my_getSmallExpression (&ep
, r
, s
) > 0
13162 || !expr_const_in_range (&ep
, 0, 1, 0))
13169 as_bad (_("Internal error: bad microMIPS opcode "
13170 "(unknown extension operand type `m%c'): %s %s"),
13171 *args
, insn
->name
, insn
->args
);
13172 /* Further processing is fruitless. */
13177 case 'n': /* Register list for 32-bit lwm and swm. */
13178 gas_assert (mips_opts
.micromips
);
13180 /* A comma-separated list of registers and/or
13181 dash-separated contiguous ranges including
13182 at least one of ra and a set of one or more
13183 registers starting at s0 up to s7 and then
13184 s8 which have to be consecutive, e.g.:
13192 and any permutations of these. */
13193 unsigned int reglist
;
13197 if (!reglist_lookup (&s
, RTYPE_NUM
| RTYPE_GP
, ®list
))
13200 if ((reglist
& 0x3f00ffff) != 0)
13203 ra
= (reglist
>> 27) & 0x10;
13204 reglist
= ((reglist
>> 22) & 0x100) | ((reglist
>> 16) & 0xff);
13206 if ((reglist
& -reglist
) != reglist
)
13209 imm
= (ffs (reglist
) - 1) | ra
;
13210 INSERT_OPERAND (1, RT
, *ip
, imm
);
13211 imm_expr
.X_op
= O_absent
;
13215 case '|': /* 4-bit trap code. */
13216 gas_assert (mips_opts
.micromips
);
13217 my_getExpression (&imm_expr
, s
);
13218 check_absolute_expr (ip
, &imm_expr
);
13219 if ((unsigned long) imm_expr
.X_add_number
13220 > MICROMIPSOP_MASK_TRAP
)
13221 as_bad (_("Trap code (%lu) for %s not in 0..15 range"),
13222 (unsigned long) imm_expr
.X_add_number
,
13223 ip
->insn_mo
->name
);
13224 INSERT_OPERAND (1, TRAP
, *ip
, imm_expr
.X_add_number
);
13225 imm_expr
.X_op
= O_absent
;
13230 as_bad (_("Bad char = '%c'\n"), *args
);
13235 /* Args don't match. */
13237 insn_error
= _("Illegal operands");
13238 if (insn
+ 1 < past
&& !strcmp (insn
->name
, insn
[1].name
))
13243 else if (wrong_delay_slot_insns
&& need_delay_slot_ok
)
13245 gas_assert (firstinsn
);
13246 need_delay_slot_ok
= FALSE
;
13255 #define SKIP_SPACE_TABS(S) { while (*(S) == ' ' || *(S) == '\t') ++(S); }
13257 /* This routine assembles an instruction into its binary format when
13258 assembling for the mips16. As a side effect, it sets one of the
13259 global variables imm_reloc or offset_reloc to the type of relocation
13260 to do if one of the operands is an address expression. It also sets
13261 forced_insn_length to the resulting instruction size in bytes if the
13262 user explicitly requested a small or extended instruction. */
13265 mips16_ip (char *str
, struct mips_cl_insn
*ip
)
13269 struct mips_opcode
*insn
;
13271 unsigned int regno
;
13272 unsigned int lastregno
= 0;
13278 forced_insn_length
= 0;
13280 for (s
= str
; ISLOWER (*s
); ++s
)
13292 if (s
[1] == 't' && s
[2] == ' ')
13295 forced_insn_length
= 2;
13299 else if (s
[1] == 'e' && s
[2] == ' ')
13302 forced_insn_length
= 4;
13306 /* Fall through. */
13308 insn_error
= _("unknown opcode");
13312 if (mips_opts
.noautoextend
&& !forced_insn_length
)
13313 forced_insn_length
= 2;
13315 if ((insn
= (struct mips_opcode
*) hash_find (mips16_op_hash
, str
)) == NULL
)
13317 insn_error
= _("unrecognized opcode");
13326 gas_assert (strcmp (insn
->name
, str
) == 0);
13328 ok
= is_opcode_valid_16 (insn
);
13331 if (insn
+ 1 < &mips16_opcodes
[bfd_mips16_num_opcodes
]
13332 && strcmp (insn
->name
, insn
[1].name
) == 0)
13341 static char buf
[100];
13343 _("Opcode not supported on this processor: %s (%s)"),
13344 mips_cpu_info_from_arch (mips_opts
.arch
)->name
,
13345 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
13352 create_insn (ip
, insn
);
13353 imm_expr
.X_op
= O_absent
;
13354 imm_reloc
[0] = BFD_RELOC_UNUSED
;
13355 imm_reloc
[1] = BFD_RELOC_UNUSED
;
13356 imm_reloc
[2] = BFD_RELOC_UNUSED
;
13357 imm2_expr
.X_op
= O_absent
;
13358 offset_expr
.X_op
= O_absent
;
13359 offset_reloc
[0] = BFD_RELOC_UNUSED
;
13360 offset_reloc
[1] = BFD_RELOC_UNUSED
;
13361 offset_reloc
[2] = BFD_RELOC_UNUSED
;
13362 for (args
= insn
->args
; 1; ++args
)
13369 /* In this switch statement we call break if we did not find
13370 a match, continue if we did find a match, or return if we
13379 /* Stuff the immediate value in now, if we can. */
13380 if (imm_expr
.X_op
== O_constant
13381 && *imm_reloc
> BFD_RELOC_UNUSED
13382 && *imm_reloc
!= BFD_RELOC_MIPS16_GOT16
13383 && *imm_reloc
!= BFD_RELOC_MIPS16_CALL16
13384 && insn
->pinfo
!= INSN_MACRO
)
13388 switch (*offset_reloc
)
13390 case BFD_RELOC_MIPS16_HI16_S
:
13391 tmp
= (imm_expr
.X_add_number
+ 0x8000) >> 16;
13394 case BFD_RELOC_MIPS16_HI16
:
13395 tmp
= imm_expr
.X_add_number
>> 16;
13398 case BFD_RELOC_MIPS16_LO16
:
13399 tmp
= ((imm_expr
.X_add_number
+ 0x8000) & 0xffff)
13403 case BFD_RELOC_UNUSED
:
13404 tmp
= imm_expr
.X_add_number
;
13411 mips16_immed (NULL
, 0, *imm_reloc
- BFD_RELOC_UNUSED
,
13412 *offset_reloc
, tmp
, forced_insn_length
,
13414 imm_expr
.X_op
= O_absent
;
13415 *imm_reloc
= BFD_RELOC_UNUSED
;
13416 *offset_reloc
= BFD_RELOC_UNUSED
;
13430 MIPS16_INSERT_OPERAND (RX
, *ip
, lastregno
);
13433 MIPS16_INSERT_OPERAND (RY
, *ip
, lastregno
);
13449 MIPS16_INSERT_OPERAND (RX
, *ip
, lastregno
);
13451 MIPS16_INSERT_OPERAND (RY
, *ip
, lastregno
);
13455 /* Fall through. */
13466 if (!reg_lookup (&s
, RTYPE_NUM
| RTYPE_GP
, ®no
))
13468 if (c
== 'v' || c
== 'w')
13471 MIPS16_INSERT_OPERAND (RX
, *ip
, lastregno
);
13473 MIPS16_INSERT_OPERAND (RY
, *ip
, lastregno
);
13484 if (c
== 'v' || c
== 'w')
13486 regno
= mips16_to_32_reg_map
[lastregno
];
13500 regno
= mips32_to_16_reg_map
[regno
];
13505 regno
= ILLEGAL_REG
;
13510 regno
= ILLEGAL_REG
;
13515 regno
= ILLEGAL_REG
;
13520 if (regno
== AT
&& mips_opts
.at
)
13522 if (mips_opts
.at
== ATREG
)
13523 as_warn (_("used $at without \".set noat\""));
13525 as_warn (_("used $%u with \".set at=$%u\""),
13526 regno
, mips_opts
.at
);
13534 if (regno
== ILLEGAL_REG
)
13541 MIPS16_INSERT_OPERAND (RX
, *ip
, regno
);
13545 MIPS16_INSERT_OPERAND (RY
, *ip
, regno
);
13548 MIPS16_INSERT_OPERAND (RZ
, *ip
, regno
);
13551 MIPS16_INSERT_OPERAND (MOVE32Z
, *ip
, regno
);
13557 MIPS16_INSERT_OPERAND (REGR32
, *ip
, regno
);
13560 regno
= ((regno
& 7) << 2) | ((regno
& 0x18) >> 3);
13561 MIPS16_INSERT_OPERAND (REG32R
, *ip
, regno
);
13571 if (strncmp (s
, "$pc", 3) == 0)
13588 i
= my_getSmallExpression (&imm_expr
, imm_reloc
, s
);
13591 if (imm_expr
.X_op
!= O_constant
)
13593 forced_insn_length
= 4;
13594 ip
->insn_opcode
|= MIPS16_EXTEND
;
13598 /* We need to relax this instruction. */
13599 *offset_reloc
= *imm_reloc
;
13600 *imm_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
13605 *imm_reloc
= BFD_RELOC_UNUSED
;
13606 /* Fall through. */
13613 my_getExpression (&imm_expr
, s
);
13614 if (imm_expr
.X_op
== O_register
)
13616 /* What we thought was an expression turned out to
13619 if (s
[0] == '(' && args
[1] == '(')
13621 /* It looks like the expression was omitted
13622 before a register indirection, which means
13623 that the expression is implicitly zero. We
13624 still set up imm_expr, so that we handle
13625 explicit extensions correctly. */
13626 imm_expr
.X_op
= O_constant
;
13627 imm_expr
.X_add_number
= 0;
13628 *imm_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
13635 /* We need to relax this instruction. */
13636 *imm_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
13645 /* We use offset_reloc rather than imm_reloc for the PC
13646 relative operands. This lets macros with both
13647 immediate and address operands work correctly. */
13648 my_getExpression (&offset_expr
, s
);
13650 if (offset_expr
.X_op
== O_register
)
13653 /* We need to relax this instruction. */
13654 *offset_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
13658 case '6': /* break code */
13659 my_getExpression (&imm_expr
, s
);
13660 check_absolute_expr (ip
, &imm_expr
);
13661 if ((unsigned long) imm_expr
.X_add_number
> 63)
13662 as_warn (_("Invalid value for `%s' (%lu)"),
13664 (unsigned long) imm_expr
.X_add_number
);
13665 MIPS16_INSERT_OPERAND (IMM6
, *ip
, imm_expr
.X_add_number
);
13666 imm_expr
.X_op
= O_absent
;
13670 case 'a': /* 26 bit address */
13671 my_getExpression (&offset_expr
, s
);
13673 *offset_reloc
= BFD_RELOC_MIPS16_JMP
;
13674 ip
->insn_opcode
<<= 16;
13677 case 'l': /* register list for entry macro */
13678 case 'L': /* register list for exit macro */
13688 unsigned int freg
, reg1
, reg2
;
13690 while (*s
== ' ' || *s
== ',')
13692 if (reg_lookup (&s
, RTYPE_GP
| RTYPE_NUM
, ®1
))
13694 else if (reg_lookup (&s
, RTYPE_FPU
, ®1
))
13698 as_bad (_("can't parse register list"));
13708 if (!reg_lookup (&s
, freg
? RTYPE_FPU
13709 : (RTYPE_GP
| RTYPE_NUM
), ®2
))
13711 as_bad (_("invalid register list"));
13715 if (freg
&& reg1
== 0 && reg2
== 0 && c
== 'L')
13717 mask
&= ~ (7 << 3);
13720 else if (freg
&& reg1
== 0 && reg2
== 1 && c
== 'L')
13722 mask
&= ~ (7 << 3);
13725 else if (reg1
== 4 && reg2
>= 4 && reg2
<= 7 && c
!= 'L')
13726 mask
|= (reg2
- 3) << 3;
13727 else if (reg1
== 16 && reg2
>= 16 && reg2
<= 17)
13728 mask
|= (reg2
- 15) << 1;
13729 else if (reg1
== RA
&& reg2
== RA
)
13733 as_bad (_("invalid register list"));
13737 /* The mask is filled in in the opcode table for the
13738 benefit of the disassembler. We remove it before
13739 applying the actual mask. */
13740 ip
->insn_opcode
&= ~ ((7 << 3) << MIPS16OP_SH_IMM6
);
13741 ip
->insn_opcode
|= mask
<< MIPS16OP_SH_IMM6
;
13745 case 'm': /* Register list for save insn. */
13746 case 'M': /* Register list for restore insn. */
13748 int opcode
= ip
->insn_opcode
;
13749 int framesz
= 0, seen_framesz
= 0;
13750 int nargs
= 0, statics
= 0, sregs
= 0;
13754 unsigned int reg1
, reg2
;
13756 SKIP_SPACE_TABS (s
);
13759 SKIP_SPACE_TABS (s
);
13761 my_getExpression (&imm_expr
, s
);
13762 if (imm_expr
.X_op
== O_constant
)
13764 /* Handle the frame size. */
13767 as_bad (_("more than one frame size in list"));
13771 framesz
= imm_expr
.X_add_number
;
13772 imm_expr
.X_op
= O_absent
;
13777 if (! reg_lookup (&s
, RTYPE_GP
| RTYPE_NUM
, ®1
))
13779 as_bad (_("can't parse register list"));
13791 if (! reg_lookup (&s
, RTYPE_GP
| RTYPE_NUM
, ®2
)
13794 as_bad (_("can't parse register list"));
13799 while (reg1
<= reg2
)
13801 if (reg1
>= 4 && reg1
<= 7)
13805 nargs
|= 1 << (reg1
- 4);
13807 /* statics $a0-$a3 */
13808 statics
|= 1 << (reg1
- 4);
13810 else if ((reg1
>= 16 && reg1
<= 23) || reg1
== 30)
13813 sregs
|= 1 << ((reg1
== 30) ? 8 : (reg1
- 16));
13815 else if (reg1
== 31)
13817 /* Add $ra to insn. */
13822 as_bad (_("unexpected register in list"));
13830 /* Encode args/statics combination. */
13831 if (nargs
& statics
)
13832 as_bad (_("arg/static registers overlap"));
13833 else if (nargs
== 0xf)
13834 /* All $a0-$a3 are args. */
13835 opcode
|= MIPS16_ALL_ARGS
<< 16;
13836 else if (statics
== 0xf)
13837 /* All $a0-$a3 are statics. */
13838 opcode
|= MIPS16_ALL_STATICS
<< 16;
13841 int narg
= 0, nstat
= 0;
13843 /* Count arg registers. */
13844 while (nargs
& 0x1)
13850 as_bad (_("invalid arg register list"));
13852 /* Count static registers. */
13853 while (statics
& 0x8)
13855 statics
= (statics
<< 1) & 0xf;
13859 as_bad (_("invalid static register list"));
13861 /* Encode args/statics. */
13862 opcode
|= ((narg
<< 2) | nstat
) << 16;
13865 /* Encode $s0/$s1. */
13866 if (sregs
& (1 << 0)) /* $s0 */
13868 if (sregs
& (1 << 1)) /* $s1 */
13874 /* Count regs $s2-$s8. */
13882 as_bad (_("invalid static register list"));
13883 /* Encode $s2-$s8. */
13884 opcode
|= nsreg
<< 24;
13887 /* Encode frame size. */
13889 as_bad (_("missing frame size"));
13890 else if ((framesz
& 7) != 0 || framesz
< 0
13891 || framesz
> 0xff * 8)
13892 as_bad (_("invalid frame size"));
13893 else if (framesz
!= 128 || (opcode
>> 16) != 0)
13896 opcode
|= (((framesz
& 0xf0) << 16)
13897 | (framesz
& 0x0f));
13900 /* Finally build the instruction. */
13901 if ((opcode
>> 16) != 0 || framesz
== 0)
13902 opcode
|= MIPS16_EXTEND
;
13903 ip
->insn_opcode
= opcode
;
13907 case 'e': /* extend code */
13908 my_getExpression (&imm_expr
, s
);
13909 check_absolute_expr (ip
, &imm_expr
);
13910 if ((unsigned long) imm_expr
.X_add_number
> 0x7ff)
13912 as_warn (_("Invalid value for `%s' (%lu)"),
13914 (unsigned long) imm_expr
.X_add_number
);
13915 imm_expr
.X_add_number
&= 0x7ff;
13917 ip
->insn_opcode
|= imm_expr
.X_add_number
;
13918 imm_expr
.X_op
= O_absent
;
13928 /* Args don't match. */
13929 if (insn
+ 1 < &mips16_opcodes
[bfd_mips16_num_opcodes
] &&
13930 strcmp (insn
->name
, insn
[1].name
) == 0)
13937 insn_error
= _("illegal operands");
13943 /* This structure holds information we know about a mips16 immediate
13946 struct mips16_immed_operand
13948 /* The type code used in the argument string in the opcode table. */
13950 /* The number of bits in the short form of the opcode. */
13952 /* The number of bits in the extended form of the opcode. */
13954 /* The amount by which the short form is shifted when it is used;
13955 for example, the sw instruction has a shift count of 2. */
13957 /* The amount by which the short form is shifted when it is stored
13958 into the instruction code. */
13960 /* Non-zero if the short form is unsigned. */
13962 /* Non-zero if the extended form is unsigned. */
13964 /* Non-zero if the value is PC relative. */
13968 /* The mips16 immediate operand types. */
13970 static const struct mips16_immed_operand mips16_immed_operands
[] =
13972 { '<', 3, 5, 0, MIPS16OP_SH_RZ
, 1, 1, 0 },
13973 { '>', 3, 5, 0, MIPS16OP_SH_RX
, 1, 1, 0 },
13974 { '[', 3, 6, 0, MIPS16OP_SH_RZ
, 1, 1, 0 },
13975 { ']', 3, 6, 0, MIPS16OP_SH_RX
, 1, 1, 0 },
13976 { '4', 4, 15, 0, MIPS16OP_SH_IMM4
, 0, 0, 0 },
13977 { '5', 5, 16, 0, MIPS16OP_SH_IMM5
, 1, 0, 0 },
13978 { 'H', 5, 16, 1, MIPS16OP_SH_IMM5
, 1, 0, 0 },
13979 { 'W', 5, 16, 2, MIPS16OP_SH_IMM5
, 1, 0, 0 },
13980 { 'D', 5, 16, 3, MIPS16OP_SH_IMM5
, 1, 0, 0 },
13981 { 'j', 5, 16, 0, MIPS16OP_SH_IMM5
, 0, 0, 0 },
13982 { '8', 8, 16, 0, MIPS16OP_SH_IMM8
, 1, 0, 0 },
13983 { 'V', 8, 16, 2, MIPS16OP_SH_IMM8
, 1, 0, 0 },
13984 { 'C', 8, 16, 3, MIPS16OP_SH_IMM8
, 1, 0, 0 },
13985 { 'U', 8, 16, 0, MIPS16OP_SH_IMM8
, 1, 1, 0 },
13986 { 'k', 8, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 0 },
13987 { 'K', 8, 16, 3, MIPS16OP_SH_IMM8
, 0, 0, 0 },
13988 { 'p', 8, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 1 },
13989 { 'q', 11, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 1 },
13990 { 'A', 8, 16, 2, MIPS16OP_SH_IMM8
, 1, 0, 1 },
13991 { 'B', 5, 16, 3, MIPS16OP_SH_IMM5
, 1, 0, 1 },
13992 { 'E', 5, 16, 2, MIPS16OP_SH_IMM5
, 1, 0, 1 }
13995 #define MIPS16_NUM_IMMED \
13996 (sizeof mips16_immed_operands / sizeof mips16_immed_operands[0])
13998 /* Install immediate value VAL into MIPS16 instruction *INSN,
13999 extending it if necessary. The instruction in *INSN may
14000 already be extended.
14002 RELOC is the relocation that produced VAL, or BFD_RELOC_UNUSED
14003 if none. In the former case, VAL is a 16-bit number with no
14004 defined signedness.
14006 TYPE is the type of the immediate field. USER_INSN_LENGTH
14007 is the length that the user requested, or 0 if none. */
14010 mips16_immed (char *file
, unsigned int line
, int type
,
14011 bfd_reloc_code_real_type reloc
, offsetT val
,
14012 unsigned int user_insn_length
, unsigned long *insn
)
14014 const struct mips16_immed_operand
*op
;
14015 int mintiny
, maxtiny
;
14017 op
= mips16_immed_operands
;
14018 while (op
->type
!= type
)
14021 gas_assert (op
< mips16_immed_operands
+ MIPS16_NUM_IMMED
);
14026 if (type
== '<' || type
== '>' || type
== '[' || type
== ']')
14029 maxtiny
= 1 << op
->nbits
;
14034 maxtiny
= (1 << op
->nbits
) - 1;
14036 if (reloc
!= BFD_RELOC_UNUSED
)
14041 mintiny
= - (1 << (op
->nbits
- 1));
14042 maxtiny
= (1 << (op
->nbits
- 1)) - 1;
14043 if (reloc
!= BFD_RELOC_UNUSED
)
14044 val
= SEXT_16BIT (val
);
14047 /* Branch offsets have an implicit 0 in the lowest bit. */
14048 if (type
== 'p' || type
== 'q')
14051 if ((val
& ((1 << op
->shift
) - 1)) != 0
14052 || val
< (mintiny
<< op
->shift
)
14053 || val
> (maxtiny
<< op
->shift
))
14055 /* We need an extended instruction. */
14056 if (user_insn_length
== 2)
14057 as_bad_where (file
, line
, _("invalid unextended operand value"));
14059 *insn
|= MIPS16_EXTEND
;
14061 else if (user_insn_length
== 4)
14063 /* The operand doesn't force an unextended instruction to be extended.
14064 Warn if the user wanted an extended instruction anyway. */
14065 *insn
|= MIPS16_EXTEND
;
14066 as_warn_where (file
, line
,
14067 _("extended operand requested but not required"));
14070 if (mips16_opcode_length (*insn
) == 2)
14074 insnval
= ((val
>> op
->shift
) & ((1 << op
->nbits
) - 1));
14075 insnval
<<= op
->op_shift
;
14080 long minext
, maxext
;
14083 if (reloc
== BFD_RELOC_UNUSED
)
14088 maxext
= (1 << op
->extbits
) - 1;
14092 minext
= - (1 << (op
->extbits
- 1));
14093 maxext
= (1 << (op
->extbits
- 1)) - 1;
14095 if (val
< minext
|| val
> maxext
)
14096 as_bad_where (file
, line
,
14097 _("operand value out of range for instruction"));
14100 if (op
->extbits
== 16)
14102 extval
= ((val
>> 11) & 0x1f) | (val
& 0x7e0);
14105 else if (op
->extbits
== 15)
14107 extval
= ((val
>> 11) & 0xf) | (val
& 0x7f0);
14112 extval
= ((val
& 0x1f) << 6) | (val
& 0x20);
14116 *insn
|= (extval
<< 16) | val
;
14120 struct percent_op_match
14123 bfd_reloc_code_real_type reloc
;
14126 static const struct percent_op_match mips_percent_op
[] =
14128 {"%lo", BFD_RELOC_LO16
},
14130 {"%call_hi", BFD_RELOC_MIPS_CALL_HI16
},
14131 {"%call_lo", BFD_RELOC_MIPS_CALL_LO16
},
14132 {"%call16", BFD_RELOC_MIPS_CALL16
},
14133 {"%got_disp", BFD_RELOC_MIPS_GOT_DISP
},
14134 {"%got_page", BFD_RELOC_MIPS_GOT_PAGE
},
14135 {"%got_ofst", BFD_RELOC_MIPS_GOT_OFST
},
14136 {"%got_hi", BFD_RELOC_MIPS_GOT_HI16
},
14137 {"%got_lo", BFD_RELOC_MIPS_GOT_LO16
},
14138 {"%got", BFD_RELOC_MIPS_GOT16
},
14139 {"%gp_rel", BFD_RELOC_GPREL16
},
14140 {"%half", BFD_RELOC_16
},
14141 {"%highest", BFD_RELOC_MIPS_HIGHEST
},
14142 {"%higher", BFD_RELOC_MIPS_HIGHER
},
14143 {"%neg", BFD_RELOC_MIPS_SUB
},
14144 {"%tlsgd", BFD_RELOC_MIPS_TLS_GD
},
14145 {"%tlsldm", BFD_RELOC_MIPS_TLS_LDM
},
14146 {"%dtprel_hi", BFD_RELOC_MIPS_TLS_DTPREL_HI16
},
14147 {"%dtprel_lo", BFD_RELOC_MIPS_TLS_DTPREL_LO16
},
14148 {"%tprel_hi", BFD_RELOC_MIPS_TLS_TPREL_HI16
},
14149 {"%tprel_lo", BFD_RELOC_MIPS_TLS_TPREL_LO16
},
14150 {"%gottprel", BFD_RELOC_MIPS_TLS_GOTTPREL
},
14152 {"%hi", BFD_RELOC_HI16_S
}
14155 static const struct percent_op_match mips16_percent_op
[] =
14157 {"%lo", BFD_RELOC_MIPS16_LO16
},
14158 {"%gprel", BFD_RELOC_MIPS16_GPREL
},
14159 {"%got", BFD_RELOC_MIPS16_GOT16
},
14160 {"%call16", BFD_RELOC_MIPS16_CALL16
},
14161 {"%hi", BFD_RELOC_MIPS16_HI16_S
},
14162 {"%tlsgd", BFD_RELOC_MIPS16_TLS_GD
},
14163 {"%tlsldm", BFD_RELOC_MIPS16_TLS_LDM
},
14164 {"%dtprel_hi", BFD_RELOC_MIPS16_TLS_DTPREL_HI16
},
14165 {"%dtprel_lo", BFD_RELOC_MIPS16_TLS_DTPREL_LO16
},
14166 {"%tprel_hi", BFD_RELOC_MIPS16_TLS_TPREL_HI16
},
14167 {"%tprel_lo", BFD_RELOC_MIPS16_TLS_TPREL_LO16
},
14168 {"%gottprel", BFD_RELOC_MIPS16_TLS_GOTTPREL
}
14172 /* Return true if *STR points to a relocation operator. When returning true,
14173 move *STR over the operator and store its relocation code in *RELOC.
14174 Leave both *STR and *RELOC alone when returning false. */
14177 parse_relocation (char **str
, bfd_reloc_code_real_type
*reloc
)
14179 const struct percent_op_match
*percent_op
;
14182 if (mips_opts
.mips16
)
14184 percent_op
= mips16_percent_op
;
14185 limit
= ARRAY_SIZE (mips16_percent_op
);
14189 percent_op
= mips_percent_op
;
14190 limit
= ARRAY_SIZE (mips_percent_op
);
14193 for (i
= 0; i
< limit
; i
++)
14194 if (strncasecmp (*str
, percent_op
[i
].str
, strlen (percent_op
[i
].str
)) == 0)
14196 int len
= strlen (percent_op
[i
].str
);
14198 if (!ISSPACE ((*str
)[len
]) && (*str
)[len
] != '(')
14201 *str
+= strlen (percent_op
[i
].str
);
14202 *reloc
= percent_op
[i
].reloc
;
14204 /* Check whether the output BFD supports this relocation.
14205 If not, issue an error and fall back on something safe. */
14206 if (!bfd_reloc_type_lookup (stdoutput
, percent_op
[i
].reloc
))
14208 as_bad (_("relocation %s isn't supported by the current ABI"),
14209 percent_op
[i
].str
);
14210 *reloc
= BFD_RELOC_UNUSED
;
14218 /* Parse string STR as a 16-bit relocatable operand. Store the
14219 expression in *EP and the relocations in the array starting
14220 at RELOC. Return the number of relocation operators used.
14222 On exit, EXPR_END points to the first character after the expression. */
14225 my_getSmallExpression (expressionS
*ep
, bfd_reloc_code_real_type
*reloc
,
14228 bfd_reloc_code_real_type reversed_reloc
[3];
14229 size_t reloc_index
, i
;
14230 int crux_depth
, str_depth
;
14233 /* Search for the start of the main expression, recoding relocations
14234 in REVERSED_RELOC. End the loop with CRUX pointing to the start
14235 of the main expression and with CRUX_DEPTH containing the number
14236 of open brackets at that point. */
14243 crux_depth
= str_depth
;
14245 /* Skip over whitespace and brackets, keeping count of the number
14247 while (*str
== ' ' || *str
== '\t' || *str
== '(')
14252 && reloc_index
< (HAVE_NEWABI
? 3 : 1)
14253 && parse_relocation (&str
, &reversed_reloc
[reloc_index
]));
14255 my_getExpression (ep
, crux
);
14258 /* Match every open bracket. */
14259 while (crux_depth
> 0 && (*str
== ')' || *str
== ' ' || *str
== '\t'))
14263 if (crux_depth
> 0)
14264 as_bad (_("unclosed '('"));
14268 if (reloc_index
!= 0)
14270 prev_reloc_op_frag
= frag_now
;
14271 for (i
= 0; i
< reloc_index
; i
++)
14272 reloc
[i
] = reversed_reloc
[reloc_index
- 1 - i
];
14275 return reloc_index
;
14279 my_getExpression (expressionS
*ep
, char *str
)
14283 save_in
= input_line_pointer
;
14284 input_line_pointer
= str
;
14286 expr_end
= input_line_pointer
;
14287 input_line_pointer
= save_in
;
14291 md_atof (int type
, char *litP
, int *sizeP
)
14293 return ieee_md_atof (type
, litP
, sizeP
, target_big_endian
);
14297 md_number_to_chars (char *buf
, valueT val
, int n
)
14299 if (target_big_endian
)
14300 number_to_chars_bigendian (buf
, val
, n
);
14302 number_to_chars_littleendian (buf
, val
, n
);
14306 static int support_64bit_objects(void)
14308 const char **list
, **l
;
14311 list
= bfd_target_list ();
14312 for (l
= list
; *l
!= NULL
; l
++)
14313 if (strcmp (*l
, ELF_TARGET ("elf64-", "big")) == 0
14314 || strcmp (*l
, ELF_TARGET ("elf64-", "little")) == 0)
14316 yes
= (*l
!= NULL
);
14320 #endif /* OBJ_ELF */
14322 const char *md_shortopts
= "O::g::G:";
14326 OPTION_MARCH
= OPTION_MD_BASE
,
14348 OPTION_NO_SMARTMIPS
,
14352 OPTION_NO_MICROMIPS
,
14355 OPTION_COMPAT_ARCH_BASE
,
14364 OPTION_M7000_HILO_FIX
,
14365 OPTION_MNO_7000_HILO_FIX
,
14368 OPTION_FIX_LOONGSON2F_JUMP
,
14369 OPTION_NO_FIX_LOONGSON2F_JUMP
,
14370 OPTION_FIX_LOONGSON2F_NOP
,
14371 OPTION_NO_FIX_LOONGSON2F_NOP
,
14373 OPTION_NO_FIX_VR4120
,
14375 OPTION_NO_FIX_VR4130
,
14376 OPTION_FIX_CN63XXP1
,
14377 OPTION_NO_FIX_CN63XXP1
,
14384 OPTION_CONSTRUCT_FLOATS
,
14385 OPTION_NO_CONSTRUCT_FLOATS
,
14388 OPTION_RELAX_BRANCH
,
14389 OPTION_NO_RELAX_BRANCH
,
14396 OPTION_SINGLE_FLOAT
,
14397 OPTION_DOUBLE_FLOAT
,
14400 OPTION_CALL_SHARED
,
14401 OPTION_CALL_NONPIC
,
14411 OPTION_MVXWORKS_PIC
,
14412 #endif /* OBJ_ELF */
14416 struct option md_longopts
[] =
14418 /* Options which specify architecture. */
14419 {"march", required_argument
, NULL
, OPTION_MARCH
},
14420 {"mtune", required_argument
, NULL
, OPTION_MTUNE
},
14421 {"mips0", no_argument
, NULL
, OPTION_MIPS1
},
14422 {"mips1", no_argument
, NULL
, OPTION_MIPS1
},
14423 {"mips2", no_argument
, NULL
, OPTION_MIPS2
},
14424 {"mips3", no_argument
, NULL
, OPTION_MIPS3
},
14425 {"mips4", no_argument
, NULL
, OPTION_MIPS4
},
14426 {"mips5", no_argument
, NULL
, OPTION_MIPS5
},
14427 {"mips32", no_argument
, NULL
, OPTION_MIPS32
},
14428 {"mips64", no_argument
, NULL
, OPTION_MIPS64
},
14429 {"mips32r2", no_argument
, NULL
, OPTION_MIPS32R2
},
14430 {"mips64r2", no_argument
, NULL
, OPTION_MIPS64R2
},
14432 /* Options which specify Application Specific Extensions (ASEs). */
14433 {"mips16", no_argument
, NULL
, OPTION_MIPS16
},
14434 {"no-mips16", no_argument
, NULL
, OPTION_NO_MIPS16
},
14435 {"mips3d", no_argument
, NULL
, OPTION_MIPS3D
},
14436 {"no-mips3d", no_argument
, NULL
, OPTION_NO_MIPS3D
},
14437 {"mdmx", no_argument
, NULL
, OPTION_MDMX
},
14438 {"no-mdmx", no_argument
, NULL
, OPTION_NO_MDMX
},
14439 {"mdsp", no_argument
, NULL
, OPTION_DSP
},
14440 {"mno-dsp", no_argument
, NULL
, OPTION_NO_DSP
},
14441 {"mmt", no_argument
, NULL
, OPTION_MT
},
14442 {"mno-mt", no_argument
, NULL
, OPTION_NO_MT
},
14443 {"msmartmips", no_argument
, NULL
, OPTION_SMARTMIPS
},
14444 {"mno-smartmips", no_argument
, NULL
, OPTION_NO_SMARTMIPS
},
14445 {"mdspr2", no_argument
, NULL
, OPTION_DSPR2
},
14446 {"mno-dspr2", no_argument
, NULL
, OPTION_NO_DSPR2
},
14447 {"mmicromips", no_argument
, NULL
, OPTION_MICROMIPS
},
14448 {"mno-micromips", no_argument
, NULL
, OPTION_NO_MICROMIPS
},
14449 {"mmcu", no_argument
, NULL
, OPTION_MCU
},
14450 {"mno-mcu", no_argument
, NULL
, OPTION_NO_MCU
},
14452 /* Old-style architecture options. Don't add more of these. */
14453 {"m4650", no_argument
, NULL
, OPTION_M4650
},
14454 {"no-m4650", no_argument
, NULL
, OPTION_NO_M4650
},
14455 {"m4010", no_argument
, NULL
, OPTION_M4010
},
14456 {"no-m4010", no_argument
, NULL
, OPTION_NO_M4010
},
14457 {"m4100", no_argument
, NULL
, OPTION_M4100
},
14458 {"no-m4100", no_argument
, NULL
, OPTION_NO_M4100
},
14459 {"m3900", no_argument
, NULL
, OPTION_M3900
},
14460 {"no-m3900", no_argument
, NULL
, OPTION_NO_M3900
},
14462 /* Options which enable bug fixes. */
14463 {"mfix7000", no_argument
, NULL
, OPTION_M7000_HILO_FIX
},
14464 {"no-fix-7000", no_argument
, NULL
, OPTION_MNO_7000_HILO_FIX
},
14465 {"mno-fix7000", no_argument
, NULL
, OPTION_MNO_7000_HILO_FIX
},
14466 {"mfix-loongson2f-jump", no_argument
, NULL
, OPTION_FIX_LOONGSON2F_JUMP
},
14467 {"mno-fix-loongson2f-jump", no_argument
, NULL
, OPTION_NO_FIX_LOONGSON2F_JUMP
},
14468 {"mfix-loongson2f-nop", no_argument
, NULL
, OPTION_FIX_LOONGSON2F_NOP
},
14469 {"mno-fix-loongson2f-nop", no_argument
, NULL
, OPTION_NO_FIX_LOONGSON2F_NOP
},
14470 {"mfix-vr4120", no_argument
, NULL
, OPTION_FIX_VR4120
},
14471 {"mno-fix-vr4120", no_argument
, NULL
, OPTION_NO_FIX_VR4120
},
14472 {"mfix-vr4130", no_argument
, NULL
, OPTION_FIX_VR4130
},
14473 {"mno-fix-vr4130", no_argument
, NULL
, OPTION_NO_FIX_VR4130
},
14474 {"mfix-24k", no_argument
, NULL
, OPTION_FIX_24K
},
14475 {"mno-fix-24k", no_argument
, NULL
, OPTION_NO_FIX_24K
},
14476 {"mfix-cn63xxp1", no_argument
, NULL
, OPTION_FIX_CN63XXP1
},
14477 {"mno-fix-cn63xxp1", no_argument
, NULL
, OPTION_NO_FIX_CN63XXP1
},
14479 /* Miscellaneous options. */
14480 {"trap", no_argument
, NULL
, OPTION_TRAP
},
14481 {"no-break", no_argument
, NULL
, OPTION_TRAP
},
14482 {"break", no_argument
, NULL
, OPTION_BREAK
},
14483 {"no-trap", no_argument
, NULL
, OPTION_BREAK
},
14484 {"EB", no_argument
, NULL
, OPTION_EB
},
14485 {"EL", no_argument
, NULL
, OPTION_EL
},
14486 {"mfp32", no_argument
, NULL
, OPTION_FP32
},
14487 {"mgp32", no_argument
, NULL
, OPTION_GP32
},
14488 {"construct-floats", no_argument
, NULL
, OPTION_CONSTRUCT_FLOATS
},
14489 {"no-construct-floats", no_argument
, NULL
, OPTION_NO_CONSTRUCT_FLOATS
},
14490 {"mfp64", no_argument
, NULL
, OPTION_FP64
},
14491 {"mgp64", no_argument
, NULL
, OPTION_GP64
},
14492 {"relax-branch", no_argument
, NULL
, OPTION_RELAX_BRANCH
},
14493 {"no-relax-branch", no_argument
, NULL
, OPTION_NO_RELAX_BRANCH
},
14494 {"mshared", no_argument
, NULL
, OPTION_MSHARED
},
14495 {"mno-shared", no_argument
, NULL
, OPTION_MNO_SHARED
},
14496 {"msym32", no_argument
, NULL
, OPTION_MSYM32
},
14497 {"mno-sym32", no_argument
, NULL
, OPTION_MNO_SYM32
},
14498 {"msoft-float", no_argument
, NULL
, OPTION_SOFT_FLOAT
},
14499 {"mhard-float", no_argument
, NULL
, OPTION_HARD_FLOAT
},
14500 {"msingle-float", no_argument
, NULL
, OPTION_SINGLE_FLOAT
},
14501 {"mdouble-float", no_argument
, NULL
, OPTION_DOUBLE_FLOAT
},
14503 /* Strictly speaking this next option is ELF specific,
14504 but we allow it for other ports as well in order to
14505 make testing easier. */
14506 {"32", no_argument
, NULL
, OPTION_32
},
14508 /* ELF-specific options. */
14510 {"KPIC", no_argument
, NULL
, OPTION_CALL_SHARED
},
14511 {"call_shared", no_argument
, NULL
, OPTION_CALL_SHARED
},
14512 {"call_nonpic", no_argument
, NULL
, OPTION_CALL_NONPIC
},
14513 {"non_shared", no_argument
, NULL
, OPTION_NON_SHARED
},
14514 {"xgot", no_argument
, NULL
, OPTION_XGOT
},
14515 {"mabi", required_argument
, NULL
, OPTION_MABI
},
14516 {"n32", no_argument
, NULL
, OPTION_N32
},
14517 {"64", no_argument
, NULL
, OPTION_64
},
14518 {"mdebug", no_argument
, NULL
, OPTION_MDEBUG
},
14519 {"no-mdebug", no_argument
, NULL
, OPTION_NO_MDEBUG
},
14520 {"mpdr", no_argument
, NULL
, OPTION_PDR
},
14521 {"mno-pdr", no_argument
, NULL
, OPTION_NO_PDR
},
14522 {"mvxworks-pic", no_argument
, NULL
, OPTION_MVXWORKS_PIC
},
14523 #endif /* OBJ_ELF */
14525 {NULL
, no_argument
, NULL
, 0}
14527 size_t md_longopts_size
= sizeof (md_longopts
);
14529 /* Set STRING_PTR (either &mips_arch_string or &mips_tune_string) to
14530 NEW_VALUE. Warn if another value was already specified. Note:
14531 we have to defer parsing the -march and -mtune arguments in order
14532 to handle 'from-abi' correctly, since the ABI might be specified
14533 in a later argument. */
14536 mips_set_option_string (const char **string_ptr
, const char *new_value
)
14538 if (*string_ptr
!= 0 && strcasecmp (*string_ptr
, new_value
) != 0)
14539 as_warn (_("A different %s was already specified, is now %s"),
14540 string_ptr
== &mips_arch_string
? "-march" : "-mtune",
14543 *string_ptr
= new_value
;
14547 md_parse_option (int c
, char *arg
)
14551 case OPTION_CONSTRUCT_FLOATS
:
14552 mips_disable_float_construction
= 0;
14555 case OPTION_NO_CONSTRUCT_FLOATS
:
14556 mips_disable_float_construction
= 1;
14568 target_big_endian
= 1;
14572 target_big_endian
= 0;
14578 else if (arg
[0] == '0')
14580 else if (arg
[0] == '1')
14590 mips_debug
= atoi (arg
);
14594 file_mips_isa
= ISA_MIPS1
;
14598 file_mips_isa
= ISA_MIPS2
;
14602 file_mips_isa
= ISA_MIPS3
;
14606 file_mips_isa
= ISA_MIPS4
;
14610 file_mips_isa
= ISA_MIPS5
;
14613 case OPTION_MIPS32
:
14614 file_mips_isa
= ISA_MIPS32
;
14617 case OPTION_MIPS32R2
:
14618 file_mips_isa
= ISA_MIPS32R2
;
14621 case OPTION_MIPS64R2
:
14622 file_mips_isa
= ISA_MIPS64R2
;
14625 case OPTION_MIPS64
:
14626 file_mips_isa
= ISA_MIPS64
;
14630 mips_set_option_string (&mips_tune_string
, arg
);
14634 mips_set_option_string (&mips_arch_string
, arg
);
14638 mips_set_option_string (&mips_arch_string
, "4650");
14639 mips_set_option_string (&mips_tune_string
, "4650");
14642 case OPTION_NO_M4650
:
14646 mips_set_option_string (&mips_arch_string
, "4010");
14647 mips_set_option_string (&mips_tune_string
, "4010");
14650 case OPTION_NO_M4010
:
14654 mips_set_option_string (&mips_arch_string
, "4100");
14655 mips_set_option_string (&mips_tune_string
, "4100");
14658 case OPTION_NO_M4100
:
14662 mips_set_option_string (&mips_arch_string
, "3900");
14663 mips_set_option_string (&mips_tune_string
, "3900");
14666 case OPTION_NO_M3900
:
14670 mips_opts
.ase_mdmx
= 1;
14673 case OPTION_NO_MDMX
:
14674 mips_opts
.ase_mdmx
= 0;
14678 mips_opts
.ase_dsp
= 1;
14679 mips_opts
.ase_dspr2
= 0;
14682 case OPTION_NO_DSP
:
14683 mips_opts
.ase_dsp
= 0;
14684 mips_opts
.ase_dspr2
= 0;
14688 mips_opts
.ase_dspr2
= 1;
14689 mips_opts
.ase_dsp
= 1;
14692 case OPTION_NO_DSPR2
:
14693 mips_opts
.ase_dspr2
= 0;
14694 mips_opts
.ase_dsp
= 0;
14698 mips_opts
.ase_mt
= 1;
14702 mips_opts
.ase_mt
= 0;
14706 mips_opts
.ase_mcu
= 1;
14709 case OPTION_NO_MCU
:
14710 mips_opts
.ase_mcu
= 0;
14713 case OPTION_MICROMIPS
:
14714 if (mips_opts
.mips16
== 1)
14716 as_bad (_("-mmicromips cannot be used with -mips16"));
14719 mips_opts
.micromips
= 1;
14720 mips_no_prev_insn ();
14723 case OPTION_NO_MICROMIPS
:
14724 mips_opts
.micromips
= 0;
14725 mips_no_prev_insn ();
14728 case OPTION_MIPS16
:
14729 if (mips_opts
.micromips
== 1)
14731 as_bad (_("-mips16 cannot be used with -micromips"));
14734 mips_opts
.mips16
= 1;
14735 mips_no_prev_insn ();
14738 case OPTION_NO_MIPS16
:
14739 mips_opts
.mips16
= 0;
14740 mips_no_prev_insn ();
14743 case OPTION_MIPS3D
:
14744 mips_opts
.ase_mips3d
= 1;
14747 case OPTION_NO_MIPS3D
:
14748 mips_opts
.ase_mips3d
= 0;
14751 case OPTION_SMARTMIPS
:
14752 mips_opts
.ase_smartmips
= 1;
14755 case OPTION_NO_SMARTMIPS
:
14756 mips_opts
.ase_smartmips
= 0;
14759 case OPTION_FIX_24K
:
14763 case OPTION_NO_FIX_24K
:
14767 case OPTION_FIX_LOONGSON2F_JUMP
:
14768 mips_fix_loongson2f_jump
= TRUE
;
14771 case OPTION_NO_FIX_LOONGSON2F_JUMP
:
14772 mips_fix_loongson2f_jump
= FALSE
;
14775 case OPTION_FIX_LOONGSON2F_NOP
:
14776 mips_fix_loongson2f_nop
= TRUE
;
14779 case OPTION_NO_FIX_LOONGSON2F_NOP
:
14780 mips_fix_loongson2f_nop
= FALSE
;
14783 case OPTION_FIX_VR4120
:
14784 mips_fix_vr4120
= 1;
14787 case OPTION_NO_FIX_VR4120
:
14788 mips_fix_vr4120
= 0;
14791 case OPTION_FIX_VR4130
:
14792 mips_fix_vr4130
= 1;
14795 case OPTION_NO_FIX_VR4130
:
14796 mips_fix_vr4130
= 0;
14799 case OPTION_FIX_CN63XXP1
:
14800 mips_fix_cn63xxp1
= TRUE
;
14803 case OPTION_NO_FIX_CN63XXP1
:
14804 mips_fix_cn63xxp1
= FALSE
;
14807 case OPTION_RELAX_BRANCH
:
14808 mips_relax_branch
= 1;
14811 case OPTION_NO_RELAX_BRANCH
:
14812 mips_relax_branch
= 0;
14815 case OPTION_MSHARED
:
14816 mips_in_shared
= TRUE
;
14819 case OPTION_MNO_SHARED
:
14820 mips_in_shared
= FALSE
;
14823 case OPTION_MSYM32
:
14824 mips_opts
.sym32
= TRUE
;
14827 case OPTION_MNO_SYM32
:
14828 mips_opts
.sym32
= FALSE
;
14832 /* When generating ELF code, we permit -KPIC and -call_shared to
14833 select SVR4_PIC, and -non_shared to select no PIC. This is
14834 intended to be compatible with Irix 5. */
14835 case OPTION_CALL_SHARED
:
14838 as_bad (_("-call_shared is supported only for ELF format"));
14841 mips_pic
= SVR4_PIC
;
14842 mips_abicalls
= TRUE
;
14845 case OPTION_CALL_NONPIC
:
14848 as_bad (_("-call_nonpic is supported only for ELF format"));
14852 mips_abicalls
= TRUE
;
14855 case OPTION_NON_SHARED
:
14858 as_bad (_("-non_shared is supported only for ELF format"));
14862 mips_abicalls
= FALSE
;
14865 /* The -xgot option tells the assembler to use 32 bit offsets
14866 when accessing the got in SVR4_PIC mode. It is for Irix
14871 #endif /* OBJ_ELF */
14874 g_switch_value
= atoi (arg
);
14878 /* The -32, -n32 and -64 options are shortcuts for -mabi=32, -mabi=n32
14882 mips_abi
= O32_ABI
;
14883 /* We silently ignore -32 for non-ELF targets. This greatly
14884 simplifies the construction of the MIPS GAS test cases. */
14891 as_bad (_("-n32 is supported for ELF format only"));
14894 mips_abi
= N32_ABI
;
14900 as_bad (_("-64 is supported for ELF format only"));
14903 mips_abi
= N64_ABI
;
14904 if (!support_64bit_objects())
14905 as_fatal (_("No compiled in support for 64 bit object file format"));
14907 #endif /* OBJ_ELF */
14910 file_mips_gp32
= 1;
14914 file_mips_gp32
= 0;
14918 file_mips_fp32
= 1;
14922 file_mips_fp32
= 0;
14925 case OPTION_SINGLE_FLOAT
:
14926 file_mips_single_float
= 1;
14929 case OPTION_DOUBLE_FLOAT
:
14930 file_mips_single_float
= 0;
14933 case OPTION_SOFT_FLOAT
:
14934 file_mips_soft_float
= 1;
14937 case OPTION_HARD_FLOAT
:
14938 file_mips_soft_float
= 0;
14945 as_bad (_("-mabi is supported for ELF format only"));
14948 if (strcmp (arg
, "32") == 0)
14949 mips_abi
= O32_ABI
;
14950 else if (strcmp (arg
, "o64") == 0)
14951 mips_abi
= O64_ABI
;
14952 else if (strcmp (arg
, "n32") == 0)
14953 mips_abi
= N32_ABI
;
14954 else if (strcmp (arg
, "64") == 0)
14956 mips_abi
= N64_ABI
;
14957 if (! support_64bit_objects())
14958 as_fatal (_("No compiled in support for 64 bit object file "
14961 else if (strcmp (arg
, "eabi") == 0)
14962 mips_abi
= EABI_ABI
;
14965 as_fatal (_("invalid abi -mabi=%s"), arg
);
14969 #endif /* OBJ_ELF */
14971 case OPTION_M7000_HILO_FIX
:
14972 mips_7000_hilo_fix
= TRUE
;
14975 case OPTION_MNO_7000_HILO_FIX
:
14976 mips_7000_hilo_fix
= FALSE
;
14980 case OPTION_MDEBUG
:
14981 mips_flag_mdebug
= TRUE
;
14984 case OPTION_NO_MDEBUG
:
14985 mips_flag_mdebug
= FALSE
;
14989 mips_flag_pdr
= TRUE
;
14992 case OPTION_NO_PDR
:
14993 mips_flag_pdr
= FALSE
;
14996 case OPTION_MVXWORKS_PIC
:
14997 mips_pic
= VXWORKS_PIC
;
14999 #endif /* OBJ_ELF */
15005 mips_fix_loongson2f
= mips_fix_loongson2f_nop
|| mips_fix_loongson2f_jump
;
15010 /* Set up globals to generate code for the ISA or processor
15011 described by INFO. */
15014 mips_set_architecture (const struct mips_cpu_info
*info
)
15018 file_mips_arch
= info
->cpu
;
15019 mips_opts
.arch
= info
->cpu
;
15020 mips_opts
.isa
= info
->isa
;
15025 /* Likewise for tuning. */
15028 mips_set_tune (const struct mips_cpu_info
*info
)
15031 mips_tune
= info
->cpu
;
15036 mips_after_parse_args (void)
15038 const struct mips_cpu_info
*arch_info
= 0;
15039 const struct mips_cpu_info
*tune_info
= 0;
15041 /* GP relative stuff not working for PE */
15042 if (strncmp (TARGET_OS
, "pe", 2) == 0)
15044 if (g_switch_seen
&& g_switch_value
!= 0)
15045 as_bad (_("-G not supported in this configuration."));
15046 g_switch_value
= 0;
15049 if (mips_abi
== NO_ABI
)
15050 mips_abi
= MIPS_DEFAULT_ABI
;
15052 /* The following code determines the architecture and register size.
15053 Similar code was added to GCC 3.3 (see override_options() in
15054 config/mips/mips.c). The GAS and GCC code should be kept in sync
15055 as much as possible. */
15057 if (mips_arch_string
!= 0)
15058 arch_info
= mips_parse_cpu ("-march", mips_arch_string
);
15060 if (file_mips_isa
!= ISA_UNKNOWN
)
15062 /* Handle -mipsN. At this point, file_mips_isa contains the
15063 ISA level specified by -mipsN, while arch_info->isa contains
15064 the -march selection (if any). */
15065 if (arch_info
!= 0)
15067 /* -march takes precedence over -mipsN, since it is more descriptive.
15068 There's no harm in specifying both as long as the ISA levels
15070 if (file_mips_isa
!= arch_info
->isa
)
15071 as_bad (_("-%s conflicts with the other architecture options, which imply -%s"),
15072 mips_cpu_info_from_isa (file_mips_isa
)->name
,
15073 mips_cpu_info_from_isa (arch_info
->isa
)->name
);
15076 arch_info
= mips_cpu_info_from_isa (file_mips_isa
);
15079 if (arch_info
== 0)
15081 arch_info
= mips_parse_cpu ("default CPU", MIPS_CPU_STRING_DEFAULT
);
15082 gas_assert (arch_info
);
15085 if (ABI_NEEDS_64BIT_REGS (mips_abi
) && !ISA_HAS_64BIT_REGS (arch_info
->isa
))
15086 as_bad (_("-march=%s is not compatible with the selected ABI"),
15089 mips_set_architecture (arch_info
);
15091 /* Optimize for file_mips_arch, unless -mtune selects a different processor. */
15092 if (mips_tune_string
!= 0)
15093 tune_info
= mips_parse_cpu ("-mtune", mips_tune_string
);
15095 if (tune_info
== 0)
15096 mips_set_tune (arch_info
);
15098 mips_set_tune (tune_info
);
15100 if (file_mips_gp32
>= 0)
15102 /* The user specified the size of the integer registers. Make sure
15103 it agrees with the ABI and ISA. */
15104 if (file_mips_gp32
== 0 && !ISA_HAS_64BIT_REGS (mips_opts
.isa
))
15105 as_bad (_("-mgp64 used with a 32-bit processor"));
15106 else if (file_mips_gp32
== 1 && ABI_NEEDS_64BIT_REGS (mips_abi
))
15107 as_bad (_("-mgp32 used with a 64-bit ABI"));
15108 else if (file_mips_gp32
== 0 && ABI_NEEDS_32BIT_REGS (mips_abi
))
15109 as_bad (_("-mgp64 used with a 32-bit ABI"));
15113 /* Infer the integer register size from the ABI and processor.
15114 Restrict ourselves to 32-bit registers if that's all the
15115 processor has, or if the ABI cannot handle 64-bit registers. */
15116 file_mips_gp32
= (ABI_NEEDS_32BIT_REGS (mips_abi
)
15117 || !ISA_HAS_64BIT_REGS (mips_opts
.isa
));
15120 switch (file_mips_fp32
)
15124 /* No user specified float register size.
15125 ??? GAS treats single-float processors as though they had 64-bit
15126 float registers (although it complains when double-precision
15127 instructions are used). As things stand, saying they have 32-bit
15128 registers would lead to spurious "register must be even" messages.
15129 So here we assume float registers are never smaller than the
15131 if (file_mips_gp32
== 0)
15132 /* 64-bit integer registers implies 64-bit float registers. */
15133 file_mips_fp32
= 0;
15134 else if ((mips_opts
.ase_mips3d
> 0 || mips_opts
.ase_mdmx
> 0)
15135 && ISA_HAS_64BIT_FPRS (mips_opts
.isa
))
15136 /* -mips3d and -mdmx imply 64-bit float registers, if possible. */
15137 file_mips_fp32
= 0;
15139 /* 32-bit float registers. */
15140 file_mips_fp32
= 1;
15143 /* The user specified the size of the float registers. Check if it
15144 agrees with the ABI and ISA. */
15146 if (!ISA_HAS_64BIT_FPRS (mips_opts
.isa
))
15147 as_bad (_("-mfp64 used with a 32-bit fpu"));
15148 else if (ABI_NEEDS_32BIT_REGS (mips_abi
)
15149 && !ISA_HAS_MXHC1 (mips_opts
.isa
))
15150 as_warn (_("-mfp64 used with a 32-bit ABI"));
15153 if (ABI_NEEDS_64BIT_REGS (mips_abi
))
15154 as_warn (_("-mfp32 used with a 64-bit ABI"));
15158 /* End of GCC-shared inference code. */
15160 /* This flag is set when we have a 64-bit capable CPU but use only
15161 32-bit wide registers. Note that EABI does not use it. */
15162 if (ISA_HAS_64BIT_REGS (mips_opts
.isa
)
15163 && ((mips_abi
== NO_ABI
&& file_mips_gp32
== 1)
15164 || mips_abi
== O32_ABI
))
15165 mips_32bitmode
= 1;
15167 if (mips_opts
.isa
== ISA_MIPS1
&& mips_trap
)
15168 as_bad (_("trap exception not supported at ISA 1"));
15170 /* If the selected architecture includes support for ASEs, enable
15171 generation of code for them. */
15172 if (mips_opts
.mips16
== -1)
15173 mips_opts
.mips16
= (CPU_HAS_MIPS16 (file_mips_arch
)) ? 1 : 0;
15174 if (mips_opts
.micromips
== -1)
15175 mips_opts
.micromips
= (CPU_HAS_MICROMIPS (file_mips_arch
)) ? 1 : 0;
15176 if (mips_opts
.ase_mips3d
== -1)
15177 mips_opts
.ase_mips3d
= ((arch_info
->flags
& MIPS_CPU_ASE_MIPS3D
)
15178 && file_mips_fp32
== 0) ? 1 : 0;
15179 if (mips_opts
.ase_mips3d
&& file_mips_fp32
== 1)
15180 as_bad (_("-mfp32 used with -mips3d"));
15182 if (mips_opts
.ase_mdmx
== -1)
15183 mips_opts
.ase_mdmx
= ((arch_info
->flags
& MIPS_CPU_ASE_MDMX
)
15184 && file_mips_fp32
== 0) ? 1 : 0;
15185 if (mips_opts
.ase_mdmx
&& file_mips_fp32
== 1)
15186 as_bad (_("-mfp32 used with -mdmx"));
15188 if (mips_opts
.ase_smartmips
== -1)
15189 mips_opts
.ase_smartmips
= (arch_info
->flags
& MIPS_CPU_ASE_SMARTMIPS
) ? 1 : 0;
15190 if (mips_opts
.ase_smartmips
&& !ISA_SUPPORTS_SMARTMIPS
)
15191 as_warn (_("%s ISA does not support SmartMIPS"),
15192 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
15194 if (mips_opts
.ase_dsp
== -1)
15195 mips_opts
.ase_dsp
= (arch_info
->flags
& MIPS_CPU_ASE_DSP
) ? 1 : 0;
15196 if (mips_opts
.ase_dsp
&& !ISA_SUPPORTS_DSP_ASE
)
15197 as_warn (_("%s ISA does not support DSP ASE"),
15198 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
15200 if (mips_opts
.ase_dspr2
== -1)
15202 mips_opts
.ase_dspr2
= (arch_info
->flags
& MIPS_CPU_ASE_DSPR2
) ? 1 : 0;
15203 mips_opts
.ase_dsp
= (arch_info
->flags
& MIPS_CPU_ASE_DSP
) ? 1 : 0;
15205 if (mips_opts
.ase_dspr2
&& !ISA_SUPPORTS_DSPR2_ASE
)
15206 as_warn (_("%s ISA does not support DSP R2 ASE"),
15207 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
15209 if (mips_opts
.ase_mt
== -1)
15210 mips_opts
.ase_mt
= (arch_info
->flags
& MIPS_CPU_ASE_MT
) ? 1 : 0;
15211 if (mips_opts
.ase_mt
&& !ISA_SUPPORTS_MT_ASE
)
15212 as_warn (_("%s ISA does not support MT ASE"),
15213 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
15215 if (mips_opts
.ase_mcu
== -1)
15216 mips_opts
.ase_mcu
= (arch_info
->flags
& MIPS_CPU_ASE_MCU
) ? 1 : 0;
15217 if (mips_opts
.ase_mcu
&& !ISA_SUPPORTS_MCU_ASE
)
15218 as_warn (_("%s ISA does not support MCU ASE"),
15219 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
15221 file_mips_isa
= mips_opts
.isa
;
15222 file_ase_mips3d
= mips_opts
.ase_mips3d
;
15223 file_ase_mdmx
= mips_opts
.ase_mdmx
;
15224 file_ase_smartmips
= mips_opts
.ase_smartmips
;
15225 file_ase_dsp
= mips_opts
.ase_dsp
;
15226 file_ase_dspr2
= mips_opts
.ase_dspr2
;
15227 file_ase_mt
= mips_opts
.ase_mt
;
15228 mips_opts
.gp32
= file_mips_gp32
;
15229 mips_opts
.fp32
= file_mips_fp32
;
15230 mips_opts
.soft_float
= file_mips_soft_float
;
15231 mips_opts
.single_float
= file_mips_single_float
;
15233 if (mips_flag_mdebug
< 0)
15235 #ifdef OBJ_MAYBE_ECOFF
15236 if (OUTPUT_FLAVOR
== bfd_target_ecoff_flavour
)
15237 mips_flag_mdebug
= 1;
15239 #endif /* OBJ_MAYBE_ECOFF */
15240 mips_flag_mdebug
= 0;
15245 mips_init_after_args (void)
15247 /* initialize opcodes */
15248 bfd_mips_num_opcodes
= bfd_mips_num_builtin_opcodes
;
15249 mips_opcodes
= (struct mips_opcode
*) mips_builtin_opcodes
;
15253 md_pcrel_from (fixS
*fixP
)
15255 valueT addr
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
15256 switch (fixP
->fx_r_type
)
15258 case BFD_RELOC_MICROMIPS_7_PCREL_S1
:
15259 case BFD_RELOC_MICROMIPS_10_PCREL_S1
:
15260 /* Return the address of the delay slot. */
15263 case BFD_RELOC_MICROMIPS_16_PCREL_S1
:
15264 case BFD_RELOC_MICROMIPS_JMP
:
15265 case BFD_RELOC_16_PCREL_S2
:
15266 case BFD_RELOC_MIPS_JMP
:
15267 /* Return the address of the delay slot. */
15271 /* We have no relocation type for PC relative MIPS16 instructions. */
15272 if (fixP
->fx_addsy
&& S_GET_SEGMENT (fixP
->fx_addsy
) != now_seg
)
15273 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15274 _("PC relative MIPS16 instruction references a different section"));
15279 /* This is called before the symbol table is processed. In order to
15280 work with gcc when using mips-tfile, we must keep all local labels.
15281 However, in other cases, we want to discard them. If we were
15282 called with -g, but we didn't see any debugging information, it may
15283 mean that gcc is smuggling debugging information through to
15284 mips-tfile, in which case we must generate all local labels. */
15287 mips_frob_file_before_adjust (void)
15289 #ifndef NO_ECOFF_DEBUGGING
15290 if (ECOFF_DEBUGGING
15292 && ! ecoff_debugging_seen
)
15293 flag_keep_locals
= 1;
15297 /* Sort any unmatched HI16 and GOT16 relocs so that they immediately precede
15298 the corresponding LO16 reloc. This is called before md_apply_fix and
15299 tc_gen_reloc. Unmatched relocs can only be generated by use of explicit
15300 relocation operators.
15302 For our purposes, a %lo() expression matches a %got() or %hi()
15305 (a) it refers to the same symbol; and
15306 (b) the offset applied in the %lo() expression is no lower than
15307 the offset applied in the %got() or %hi().
15309 (b) allows us to cope with code like:
15312 lh $4,%lo(foo+2)($4)
15314 ...which is legal on RELA targets, and has a well-defined behaviour
15315 if the user knows that adding 2 to "foo" will not induce a carry to
15318 When several %lo()s match a particular %got() or %hi(), we use the
15319 following rules to distinguish them:
15321 (1) %lo()s with smaller offsets are a better match than %lo()s with
15324 (2) %lo()s with no matching %got() or %hi() are better than those
15325 that already have a matching %got() or %hi().
15327 (3) later %lo()s are better than earlier %lo()s.
15329 These rules are applied in order.
15331 (1) means, among other things, that %lo()s with identical offsets are
15332 chosen if they exist.
15334 (2) means that we won't associate several high-part relocations with
15335 the same low-part relocation unless there's no alternative. Having
15336 several high parts for the same low part is a GNU extension; this rule
15337 allows careful users to avoid it.
15339 (3) is purely cosmetic. mips_hi_fixup_list is is in reverse order,
15340 with the last high-part relocation being at the front of the list.
15341 It therefore makes sense to choose the last matching low-part
15342 relocation, all other things being equal. It's also easier
15343 to code that way. */
15346 mips_frob_file (void)
15348 struct mips_hi_fixup
*l
;
15349 bfd_reloc_code_real_type looking_for_rtype
= BFD_RELOC_UNUSED
;
15351 for (l
= mips_hi_fixup_list
; l
!= NULL
; l
= l
->next
)
15353 segment_info_type
*seginfo
;
15354 bfd_boolean matched_lo_p
;
15355 fixS
**hi_pos
, **lo_pos
, **pos
;
15357 gas_assert (reloc_needs_lo_p (l
->fixp
->fx_r_type
));
15359 /* If a GOT16 relocation turns out to be against a global symbol,
15360 there isn't supposed to be a matching LO. */
15361 if (got16_reloc_p (l
->fixp
->fx_r_type
)
15362 && !pic_need_relax (l
->fixp
->fx_addsy
, l
->seg
))
15365 /* Check quickly whether the next fixup happens to be a matching %lo. */
15366 if (fixup_has_matching_lo_p (l
->fixp
))
15369 seginfo
= seg_info (l
->seg
);
15371 /* Set HI_POS to the position of this relocation in the chain.
15372 Set LO_POS to the position of the chosen low-part relocation.
15373 MATCHED_LO_P is true on entry to the loop if *POS is a low-part
15374 relocation that matches an immediately-preceding high-part
15378 matched_lo_p
= FALSE
;
15379 looking_for_rtype
= matching_lo_reloc (l
->fixp
->fx_r_type
);
15381 for (pos
= &seginfo
->fix_root
; *pos
!= NULL
; pos
= &(*pos
)->fx_next
)
15383 if (*pos
== l
->fixp
)
15386 if ((*pos
)->fx_r_type
== looking_for_rtype
15387 && symbol_same_p ((*pos
)->fx_addsy
, l
->fixp
->fx_addsy
)
15388 && (*pos
)->fx_offset
>= l
->fixp
->fx_offset
15390 || (*pos
)->fx_offset
< (*lo_pos
)->fx_offset
15392 && (*pos
)->fx_offset
== (*lo_pos
)->fx_offset
)))
15395 matched_lo_p
= (reloc_needs_lo_p ((*pos
)->fx_r_type
)
15396 && fixup_has_matching_lo_p (*pos
));
15399 /* If we found a match, remove the high-part relocation from its
15400 current position and insert it before the low-part relocation.
15401 Make the offsets match so that fixup_has_matching_lo_p()
15404 We don't warn about unmatched high-part relocations since some
15405 versions of gcc have been known to emit dead "lui ...%hi(...)"
15407 if (lo_pos
!= NULL
)
15409 l
->fixp
->fx_offset
= (*lo_pos
)->fx_offset
;
15410 if (l
->fixp
->fx_next
!= *lo_pos
)
15412 *hi_pos
= l
->fixp
->fx_next
;
15413 l
->fixp
->fx_next
= *lo_pos
;
15420 /* We may have combined relocations without symbols in the N32/N64 ABI.
15421 We have to prevent gas from dropping them. */
15424 mips_force_relocation (fixS
*fixp
)
15426 if (generic_force_reloc (fixp
))
15429 /* We want to keep BFD_RELOC_MICROMIPS_*_PCREL_S1 relocation,
15430 so that the linker relaxation can update targets. */
15431 if (fixp
->fx_r_type
== BFD_RELOC_MICROMIPS_7_PCREL_S1
15432 || fixp
->fx_r_type
== BFD_RELOC_MICROMIPS_10_PCREL_S1
15433 || fixp
->fx_r_type
== BFD_RELOC_MICROMIPS_16_PCREL_S1
)
15437 && S_GET_SEGMENT (fixp
->fx_addsy
) == bfd_abs_section_ptr
15438 && (fixp
->fx_r_type
== BFD_RELOC_MIPS_SUB
15439 || hi16_reloc_p (fixp
->fx_r_type
)
15440 || lo16_reloc_p (fixp
->fx_r_type
)))
15446 /* Apply a fixup to the object file. */
15449 md_apply_fix (fixS
*fixP
, valueT
*valP
, segT seg ATTRIBUTE_UNUSED
)
15453 reloc_howto_type
*howto
;
15455 /* We ignore generic BFD relocations we don't know about. */
15456 howto
= bfd_reloc_type_lookup (stdoutput
, fixP
->fx_r_type
);
15460 gas_assert (fixP
->fx_size
== 2
15461 || fixP
->fx_size
== 4
15462 || fixP
->fx_r_type
== BFD_RELOC_16
15463 || fixP
->fx_r_type
== BFD_RELOC_64
15464 || fixP
->fx_r_type
== BFD_RELOC_CTOR
15465 || fixP
->fx_r_type
== BFD_RELOC_MIPS_SUB
15466 || fixP
->fx_r_type
== BFD_RELOC_MICROMIPS_SUB
15467 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
15468 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
15469 || fixP
->fx_r_type
== BFD_RELOC_MIPS_TLS_DTPREL64
);
15471 buf
= fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
15473 gas_assert (!fixP
->fx_pcrel
|| fixP
->fx_r_type
== BFD_RELOC_16_PCREL_S2
15474 || fixP
->fx_r_type
== BFD_RELOC_MICROMIPS_7_PCREL_S1
15475 || fixP
->fx_r_type
== BFD_RELOC_MICROMIPS_10_PCREL_S1
15476 || fixP
->fx_r_type
== BFD_RELOC_MICROMIPS_16_PCREL_S1
);
15478 /* Don't treat parts of a composite relocation as done. There are two
15481 (1) The second and third parts will be against 0 (RSS_UNDEF) but
15482 should nevertheless be emitted if the first part is.
15484 (2) In normal usage, composite relocations are never assembly-time
15485 constants. The easiest way of dealing with the pathological
15486 exceptions is to generate a relocation against STN_UNDEF and
15487 leave everything up to the linker. */
15488 if (fixP
->fx_addsy
== NULL
&& !fixP
->fx_pcrel
&& fixP
->fx_tcbit
== 0)
15491 switch (fixP
->fx_r_type
)
15493 case BFD_RELOC_MIPS_TLS_GD
:
15494 case BFD_RELOC_MIPS_TLS_LDM
:
15495 case BFD_RELOC_MIPS_TLS_DTPREL32
:
15496 case BFD_RELOC_MIPS_TLS_DTPREL64
:
15497 case BFD_RELOC_MIPS_TLS_DTPREL_HI16
:
15498 case BFD_RELOC_MIPS_TLS_DTPREL_LO16
:
15499 case BFD_RELOC_MIPS_TLS_GOTTPREL
:
15500 case BFD_RELOC_MIPS_TLS_TPREL32
:
15501 case BFD_RELOC_MIPS_TLS_TPREL64
:
15502 case BFD_RELOC_MIPS_TLS_TPREL_HI16
:
15503 case BFD_RELOC_MIPS_TLS_TPREL_LO16
:
15504 case BFD_RELOC_MICROMIPS_TLS_GD
:
15505 case BFD_RELOC_MICROMIPS_TLS_LDM
:
15506 case BFD_RELOC_MICROMIPS_TLS_DTPREL_HI16
:
15507 case BFD_RELOC_MICROMIPS_TLS_DTPREL_LO16
:
15508 case BFD_RELOC_MICROMIPS_TLS_GOTTPREL
:
15509 case BFD_RELOC_MICROMIPS_TLS_TPREL_HI16
:
15510 case BFD_RELOC_MICROMIPS_TLS_TPREL_LO16
:
15511 case BFD_RELOC_MIPS16_TLS_GD
:
15512 case BFD_RELOC_MIPS16_TLS_LDM
:
15513 case BFD_RELOC_MIPS16_TLS_DTPREL_HI16
:
15514 case BFD_RELOC_MIPS16_TLS_DTPREL_LO16
:
15515 case BFD_RELOC_MIPS16_TLS_GOTTPREL
:
15516 case BFD_RELOC_MIPS16_TLS_TPREL_HI16
:
15517 case BFD_RELOC_MIPS16_TLS_TPREL_LO16
:
15518 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
15521 case BFD_RELOC_MIPS_JMP
:
15522 case BFD_RELOC_MIPS_SHIFT5
:
15523 case BFD_RELOC_MIPS_SHIFT6
:
15524 case BFD_RELOC_MIPS_GOT_DISP
:
15525 case BFD_RELOC_MIPS_GOT_PAGE
:
15526 case BFD_RELOC_MIPS_GOT_OFST
:
15527 case BFD_RELOC_MIPS_SUB
:
15528 case BFD_RELOC_MIPS_INSERT_A
:
15529 case BFD_RELOC_MIPS_INSERT_B
:
15530 case BFD_RELOC_MIPS_DELETE
:
15531 case BFD_RELOC_MIPS_HIGHEST
:
15532 case BFD_RELOC_MIPS_HIGHER
:
15533 case BFD_RELOC_MIPS_SCN_DISP
:
15534 case BFD_RELOC_MIPS_REL16
:
15535 case BFD_RELOC_MIPS_RELGOT
:
15536 case BFD_RELOC_MIPS_JALR
:
15537 case BFD_RELOC_HI16
:
15538 case BFD_RELOC_HI16_S
:
15539 case BFD_RELOC_GPREL16
:
15540 case BFD_RELOC_MIPS_LITERAL
:
15541 case BFD_RELOC_MIPS_CALL16
:
15542 case BFD_RELOC_MIPS_GOT16
:
15543 case BFD_RELOC_GPREL32
:
15544 case BFD_RELOC_MIPS_GOT_HI16
:
15545 case BFD_RELOC_MIPS_GOT_LO16
:
15546 case BFD_RELOC_MIPS_CALL_HI16
:
15547 case BFD_RELOC_MIPS_CALL_LO16
:
15548 case BFD_RELOC_MIPS16_GPREL
:
15549 case BFD_RELOC_MIPS16_GOT16
:
15550 case BFD_RELOC_MIPS16_CALL16
:
15551 case BFD_RELOC_MIPS16_HI16
:
15552 case BFD_RELOC_MIPS16_HI16_S
:
15553 case BFD_RELOC_MIPS16_JMP
:
15554 case BFD_RELOC_MICROMIPS_JMP
:
15555 case BFD_RELOC_MICROMIPS_GOT_DISP
:
15556 case BFD_RELOC_MICROMIPS_GOT_PAGE
:
15557 case BFD_RELOC_MICROMIPS_GOT_OFST
:
15558 case BFD_RELOC_MICROMIPS_SUB
:
15559 case BFD_RELOC_MICROMIPS_HIGHEST
:
15560 case BFD_RELOC_MICROMIPS_HIGHER
:
15561 case BFD_RELOC_MICROMIPS_SCN_DISP
:
15562 case BFD_RELOC_MICROMIPS_JALR
:
15563 case BFD_RELOC_MICROMIPS_HI16
:
15564 case BFD_RELOC_MICROMIPS_HI16_S
:
15565 case BFD_RELOC_MICROMIPS_GPREL16
:
15566 case BFD_RELOC_MICROMIPS_LITERAL
:
15567 case BFD_RELOC_MICROMIPS_CALL16
:
15568 case BFD_RELOC_MICROMIPS_GOT16
:
15569 case BFD_RELOC_MICROMIPS_GOT_HI16
:
15570 case BFD_RELOC_MICROMIPS_GOT_LO16
:
15571 case BFD_RELOC_MICROMIPS_CALL_HI16
:
15572 case BFD_RELOC_MICROMIPS_CALL_LO16
:
15573 /* Nothing needed to do. The value comes from the reloc entry. */
15577 /* This is handled like BFD_RELOC_32, but we output a sign
15578 extended value if we are only 32 bits. */
15581 if (8 <= sizeof (valueT
))
15582 md_number_to_chars (buf
, *valP
, 8);
15587 if ((*valP
& 0x80000000) != 0)
15591 md_number_to_chars (buf
+ (target_big_endian
? 4 : 0), *valP
, 4);
15592 md_number_to_chars (buf
+ (target_big_endian
? 0 : 4), hiv
, 4);
15597 case BFD_RELOC_RVA
:
15600 /* If we are deleting this reloc entry, we must fill in the
15601 value now. This can happen if we have a .word which is not
15602 resolved when it appears but is later defined. */
15604 md_number_to_chars (buf
, *valP
, fixP
->fx_size
);
15607 case BFD_RELOC_LO16
:
15608 case BFD_RELOC_MIPS16_LO16
:
15609 case BFD_RELOC_MICROMIPS_LO16
:
15610 /* FIXME: Now that embedded-PIC is gone, some of this code/comment
15611 may be safe to remove, but if so it's not obvious. */
15612 /* When handling an embedded PIC switch statement, we can wind
15613 up deleting a LO16 reloc. See the 'o' case in mips_ip. */
15616 if (*valP
+ 0x8000 > 0xffff)
15617 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15618 _("relocation overflow"));
15619 /* 32-bit microMIPS instructions are divided into two halfwords.
15620 Relocations always refer to the second halfword, regardless
15622 if (target_big_endian
|| fixP
->fx_r_type
== BFD_RELOC_MICROMIPS_LO16
)
15624 md_number_to_chars (buf
, *valP
, 2);
15628 case BFD_RELOC_16_PCREL_S2
:
15629 if ((*valP
& 0x3) != 0)
15630 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15631 _("Branch to misaligned address (%lx)"), (long) *valP
);
15633 /* We need to save the bits in the instruction since fixup_segment()
15634 might be deleting the relocation entry (i.e., a branch within
15635 the current segment). */
15636 if (! fixP
->fx_done
)
15639 /* Update old instruction data. */
15640 insn
= read_insn (buf
);
15642 if (*valP
+ 0x20000 <= 0x3ffff)
15644 insn
|= (*valP
>> 2) & 0xffff;
15645 write_insn (buf
, insn
);
15647 else if (mips_pic
== NO_PIC
15649 && fixP
->fx_frag
->fr_address
>= text_section
->vma
15650 && (fixP
->fx_frag
->fr_address
15651 < text_section
->vma
+ bfd_get_section_size (text_section
))
15652 && ((insn
& 0xffff0000) == 0x10000000 /* beq $0,$0 */
15653 || (insn
& 0xffff0000) == 0x04010000 /* bgez $0 */
15654 || (insn
& 0xffff0000) == 0x04110000)) /* bgezal $0 */
15656 /* The branch offset is too large. If this is an
15657 unconditional branch, and we are not generating PIC code,
15658 we can convert it to an absolute jump instruction. */
15659 if ((insn
& 0xffff0000) == 0x04110000) /* bgezal $0 */
15660 insn
= 0x0c000000; /* jal */
15662 insn
= 0x08000000; /* j */
15663 fixP
->fx_r_type
= BFD_RELOC_MIPS_JMP
;
15665 fixP
->fx_addsy
= section_symbol (text_section
);
15666 *valP
+= md_pcrel_from (fixP
);
15667 write_insn (buf
, insn
);
15671 /* If we got here, we have branch-relaxation disabled,
15672 and there's nothing we can do to fix this instruction
15673 without turning it into a longer sequence. */
15674 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15675 _("Branch out of range"));
15679 case BFD_RELOC_MICROMIPS_7_PCREL_S1
:
15680 case BFD_RELOC_MICROMIPS_10_PCREL_S1
:
15681 case BFD_RELOC_MICROMIPS_16_PCREL_S1
:
15682 /* We adjust the offset back to even. */
15683 if ((*valP
& 0x1) != 0)
15686 if (! fixP
->fx_done
)
15689 /* Should never visit here, because we keep the relocation. */
15693 case BFD_RELOC_VTABLE_INHERIT
:
15696 && !S_IS_DEFINED (fixP
->fx_addsy
)
15697 && !S_IS_WEAK (fixP
->fx_addsy
))
15698 S_SET_WEAK (fixP
->fx_addsy
);
15701 case BFD_RELOC_VTABLE_ENTRY
:
15709 /* Remember value for tc_gen_reloc. */
15710 fixP
->fx_addnumber
= *valP
;
15720 name
= input_line_pointer
;
15721 c
= get_symbol_end ();
15722 p
= (symbolS
*) symbol_find_or_make (name
);
15723 *input_line_pointer
= c
;
15727 /* Align the current frag to a given power of two. If a particular
15728 fill byte should be used, FILL points to an integer that contains
15729 that byte, otherwise FILL is null.
15731 This function used to have the comment:
15733 The MIPS assembler also automatically adjusts any preceding label.
15735 The implementation therefore applied the adjustment to a maximum of
15736 one label. However, other label adjustments are applied to batches
15737 of labels, and adjusting just one caused problems when new labels
15738 were added for the sake of debugging or unwind information.
15739 We therefore adjust all preceding labels (given as LABELS) instead. */
15742 mips_align (int to
, int *fill
, struct insn_label_list
*labels
)
15744 mips_emit_delays ();
15745 mips_record_compressed_mode ();
15746 if (fill
== NULL
&& subseg_text_p (now_seg
))
15747 frag_align_code (to
, 0);
15749 frag_align (to
, fill
? *fill
: 0, 0);
15750 record_alignment (now_seg
, to
);
15751 mips_move_labels (labels
, FALSE
);
15754 /* Align to a given power of two. .align 0 turns off the automatic
15755 alignment used by the data creating pseudo-ops. */
15758 s_align (int x ATTRIBUTE_UNUSED
)
15760 int temp
, fill_value
, *fill_ptr
;
15761 long max_alignment
= 28;
15763 /* o Note that the assembler pulls down any immediately preceding label
15764 to the aligned address.
15765 o It's not documented but auto alignment is reinstated by
15766 a .align pseudo instruction.
15767 o Note also that after auto alignment is turned off the mips assembler
15768 issues an error on attempt to assemble an improperly aligned data item.
15771 temp
= get_absolute_expression ();
15772 if (temp
> max_alignment
)
15773 as_bad (_("Alignment too large: %d. assumed."), temp
= max_alignment
);
15776 as_warn (_("Alignment negative: 0 assumed."));
15779 if (*input_line_pointer
== ',')
15781 ++input_line_pointer
;
15782 fill_value
= get_absolute_expression ();
15783 fill_ptr
= &fill_value
;
15789 segment_info_type
*si
= seg_info (now_seg
);
15790 struct insn_label_list
*l
= si
->label_list
;
15791 /* Auto alignment should be switched on by next section change. */
15793 mips_align (temp
, fill_ptr
, l
);
15800 demand_empty_rest_of_line ();
15804 s_change_sec (int sec
)
15809 /* The ELF backend needs to know that we are changing sections, so
15810 that .previous works correctly. We could do something like check
15811 for an obj_section_change_hook macro, but that might be confusing
15812 as it would not be appropriate to use it in the section changing
15813 functions in read.c, since obj-elf.c intercepts those. FIXME:
15814 This should be cleaner, somehow. */
15816 obj_elf_section_change_hook ();
15819 mips_emit_delays ();
15830 subseg_set (bss_section
, (subsegT
) get_absolute_expression ());
15831 demand_empty_rest_of_line ();
15835 seg
= subseg_new (RDATA_SECTION_NAME
,
15836 (subsegT
) get_absolute_expression ());
15839 bfd_set_section_flags (stdoutput
, seg
, (SEC_ALLOC
| SEC_LOAD
15840 | SEC_READONLY
| SEC_RELOC
15842 if (strncmp (TARGET_OS
, "elf", 3) != 0)
15843 record_alignment (seg
, 4);
15845 demand_empty_rest_of_line ();
15849 seg
= subseg_new (".sdata", (subsegT
) get_absolute_expression ());
15852 bfd_set_section_flags (stdoutput
, seg
,
15853 SEC_ALLOC
| SEC_LOAD
| SEC_RELOC
| SEC_DATA
);
15854 if (strncmp (TARGET_OS
, "elf", 3) != 0)
15855 record_alignment (seg
, 4);
15857 demand_empty_rest_of_line ();
15861 seg
= subseg_new (".sbss", (subsegT
) get_absolute_expression ());
15864 bfd_set_section_flags (stdoutput
, seg
, SEC_ALLOC
);
15865 if (strncmp (TARGET_OS
, "elf", 3) != 0)
15866 record_alignment (seg
, 4);
15868 demand_empty_rest_of_line ();
15876 s_change_section (int ignore ATTRIBUTE_UNUSED
)
15879 char *section_name
;
15884 int section_entry_size
;
15885 int section_alignment
;
15890 section_name
= input_line_pointer
;
15891 c
= get_symbol_end ();
15893 next_c
= *(input_line_pointer
+ 1);
15895 /* Do we have .section Name<,"flags">? */
15896 if (c
!= ',' || (c
== ',' && next_c
== '"'))
15898 /* just after name is now '\0'. */
15899 *input_line_pointer
= c
;
15900 input_line_pointer
= section_name
;
15901 obj_elf_section (ignore
);
15904 input_line_pointer
++;
15906 /* Do we have .section Name<,type><,flag><,entry_size><,alignment> */
15908 section_type
= get_absolute_expression ();
15911 if (*input_line_pointer
++ == ',')
15912 section_flag
= get_absolute_expression ();
15915 if (*input_line_pointer
++ == ',')
15916 section_entry_size
= get_absolute_expression ();
15918 section_entry_size
= 0;
15919 if (*input_line_pointer
++ == ',')
15920 section_alignment
= get_absolute_expression ();
15922 section_alignment
= 0;
15923 /* FIXME: really ignore? */
15924 (void) section_alignment
;
15926 section_name
= xstrdup (section_name
);
15928 /* When using the generic form of .section (as implemented by obj-elf.c),
15929 there's no way to set the section type to SHT_MIPS_DWARF. Users have
15930 traditionally had to fall back on the more common @progbits instead.
15932 There's nothing really harmful in this, since bfd will correct
15933 SHT_PROGBITS to SHT_MIPS_DWARF before writing out the file. But it
15934 means that, for backwards compatibility, the special_section entries
15935 for dwarf sections must use SHT_PROGBITS rather than SHT_MIPS_DWARF.
15937 Even so, we shouldn't force users of the MIPS .section syntax to
15938 incorrectly label the sections as SHT_PROGBITS. The best compromise
15939 seems to be to map SHT_MIPS_DWARF to SHT_PROGBITS before calling the
15940 generic type-checking code. */
15941 if (section_type
== SHT_MIPS_DWARF
)
15942 section_type
= SHT_PROGBITS
;
15944 obj_elf_change_section (section_name
, section_type
, section_flag
,
15945 section_entry_size
, 0, 0, 0);
15947 if (now_seg
->name
!= section_name
)
15948 free (section_name
);
15949 #endif /* OBJ_ELF */
15953 mips_enable_auto_align (void)
15959 s_cons (int log_size
)
15961 segment_info_type
*si
= seg_info (now_seg
);
15962 struct insn_label_list
*l
= si
->label_list
;
15964 mips_emit_delays ();
15965 if (log_size
> 0 && auto_align
)
15966 mips_align (log_size
, 0, l
);
15967 cons (1 << log_size
);
15968 mips_clear_insn_labels ();
15972 s_float_cons (int type
)
15974 segment_info_type
*si
= seg_info (now_seg
);
15975 struct insn_label_list
*l
= si
->label_list
;
15977 mips_emit_delays ();
15982 mips_align (3, 0, l
);
15984 mips_align (2, 0, l
);
15988 mips_clear_insn_labels ();
15991 /* Handle .globl. We need to override it because on Irix 5 you are
15994 where foo is an undefined symbol, to mean that foo should be
15995 considered to be the address of a function. */
15998 s_mips_globl (int x ATTRIBUTE_UNUSED
)
16007 name
= input_line_pointer
;
16008 c
= get_symbol_end ();
16009 symbolP
= symbol_find_or_make (name
);
16010 S_SET_EXTERNAL (symbolP
);
16012 *input_line_pointer
= c
;
16013 SKIP_WHITESPACE ();
16015 /* On Irix 5, every global symbol that is not explicitly labelled as
16016 being a function is apparently labelled as being an object. */
16019 if (!is_end_of_line
[(unsigned char) *input_line_pointer
]
16020 && (*input_line_pointer
!= ','))
16025 secname
= input_line_pointer
;
16026 c
= get_symbol_end ();
16027 sec
= bfd_get_section_by_name (stdoutput
, secname
);
16029 as_bad (_("%s: no such section"), secname
);
16030 *input_line_pointer
= c
;
16032 if (sec
!= NULL
&& (sec
->flags
& SEC_CODE
) != 0)
16033 flag
= BSF_FUNCTION
;
16036 symbol_get_bfdsym (symbolP
)->flags
|= flag
;
16038 c
= *input_line_pointer
;
16041 input_line_pointer
++;
16042 SKIP_WHITESPACE ();
16043 if (is_end_of_line
[(unsigned char) *input_line_pointer
])
16049 demand_empty_rest_of_line ();
16053 s_option (int x ATTRIBUTE_UNUSED
)
16058 opt
= input_line_pointer
;
16059 c
= get_symbol_end ();
16063 /* FIXME: What does this mean? */
16065 else if (strncmp (opt
, "pic", 3) == 0)
16069 i
= atoi (opt
+ 3);
16074 mips_pic
= SVR4_PIC
;
16075 mips_abicalls
= TRUE
;
16078 as_bad (_(".option pic%d not supported"), i
);
16080 if (mips_pic
== SVR4_PIC
)
16082 if (g_switch_seen
&& g_switch_value
!= 0)
16083 as_warn (_("-G may not be used with SVR4 PIC code"));
16084 g_switch_value
= 0;
16085 bfd_set_gp_size (stdoutput
, 0);
16089 as_warn (_("Unrecognized option \"%s\""), opt
);
16091 *input_line_pointer
= c
;
16092 demand_empty_rest_of_line ();
16095 /* This structure is used to hold a stack of .set values. */
16097 struct mips_option_stack
16099 struct mips_option_stack
*next
;
16100 struct mips_set_options options
;
16103 static struct mips_option_stack
*mips_opts_stack
;
16105 /* Handle the .set pseudo-op. */
16108 s_mipsset (int x ATTRIBUTE_UNUSED
)
16110 char *name
= input_line_pointer
, ch
;
16112 while (!is_end_of_line
[(unsigned char) *input_line_pointer
])
16113 ++input_line_pointer
;
16114 ch
= *input_line_pointer
;
16115 *input_line_pointer
= '\0';
16117 if (strcmp (name
, "reorder") == 0)
16119 if (mips_opts
.noreorder
)
16122 else if (strcmp (name
, "noreorder") == 0)
16124 if (!mips_opts
.noreorder
)
16125 start_noreorder ();
16127 else if (strncmp (name
, "at=", 3) == 0)
16129 char *s
= name
+ 3;
16131 if (!reg_lookup (&s
, RTYPE_NUM
| RTYPE_GP
, &mips_opts
.at
))
16132 as_bad (_("Unrecognized register name `%s'"), s
);
16134 else if (strcmp (name
, "at") == 0)
16136 mips_opts
.at
= ATREG
;
16138 else if (strcmp (name
, "noat") == 0)
16140 mips_opts
.at
= ZERO
;
16142 else if (strcmp (name
, "macro") == 0)
16144 mips_opts
.warn_about_macros
= 0;
16146 else if (strcmp (name
, "nomacro") == 0)
16148 if (mips_opts
.noreorder
== 0)
16149 as_bad (_("`noreorder' must be set before `nomacro'"));
16150 mips_opts
.warn_about_macros
= 1;
16152 else if (strcmp (name
, "move") == 0 || strcmp (name
, "novolatile") == 0)
16154 mips_opts
.nomove
= 0;
16156 else if (strcmp (name
, "nomove") == 0 || strcmp (name
, "volatile") == 0)
16158 mips_opts
.nomove
= 1;
16160 else if (strcmp (name
, "bopt") == 0)
16162 mips_opts
.nobopt
= 0;
16164 else if (strcmp (name
, "nobopt") == 0)
16166 mips_opts
.nobopt
= 1;
16168 else if (strcmp (name
, "gp=default") == 0)
16169 mips_opts
.gp32
= file_mips_gp32
;
16170 else if (strcmp (name
, "gp=32") == 0)
16171 mips_opts
.gp32
= 1;
16172 else if (strcmp (name
, "gp=64") == 0)
16174 if (!ISA_HAS_64BIT_REGS (mips_opts
.isa
))
16175 as_warn (_("%s isa does not support 64-bit registers"),
16176 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
16177 mips_opts
.gp32
= 0;
16179 else if (strcmp (name
, "fp=default") == 0)
16180 mips_opts
.fp32
= file_mips_fp32
;
16181 else if (strcmp (name
, "fp=32") == 0)
16182 mips_opts
.fp32
= 1;
16183 else if (strcmp (name
, "fp=64") == 0)
16185 if (!ISA_HAS_64BIT_FPRS (mips_opts
.isa
))
16186 as_warn (_("%s isa does not support 64-bit floating point registers"),
16187 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
16188 mips_opts
.fp32
= 0;
16190 else if (strcmp (name
, "softfloat") == 0)
16191 mips_opts
.soft_float
= 1;
16192 else if (strcmp (name
, "hardfloat") == 0)
16193 mips_opts
.soft_float
= 0;
16194 else if (strcmp (name
, "singlefloat") == 0)
16195 mips_opts
.single_float
= 1;
16196 else if (strcmp (name
, "doublefloat") == 0)
16197 mips_opts
.single_float
= 0;
16198 else if (strcmp (name
, "mips16") == 0
16199 || strcmp (name
, "MIPS-16") == 0)
16201 if (mips_opts
.micromips
== 1)
16202 as_fatal (_("`mips16' cannot be used with `micromips'"));
16203 mips_opts
.mips16
= 1;
16205 else if (strcmp (name
, "nomips16") == 0
16206 || strcmp (name
, "noMIPS-16") == 0)
16207 mips_opts
.mips16
= 0;
16208 else if (strcmp (name
, "micromips") == 0)
16210 if (mips_opts
.mips16
== 1)
16211 as_fatal (_("`micromips' cannot be used with `mips16'"));
16212 mips_opts
.micromips
= 1;
16214 else if (strcmp (name
, "nomicromips") == 0)
16215 mips_opts
.micromips
= 0;
16216 else if (strcmp (name
, "smartmips") == 0)
16218 if (!ISA_SUPPORTS_SMARTMIPS
)
16219 as_warn (_("%s ISA does not support SmartMIPS ASE"),
16220 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
16221 mips_opts
.ase_smartmips
= 1;
16223 else if (strcmp (name
, "nosmartmips") == 0)
16224 mips_opts
.ase_smartmips
= 0;
16225 else if (strcmp (name
, "mips3d") == 0)
16226 mips_opts
.ase_mips3d
= 1;
16227 else if (strcmp (name
, "nomips3d") == 0)
16228 mips_opts
.ase_mips3d
= 0;
16229 else if (strcmp (name
, "mdmx") == 0)
16230 mips_opts
.ase_mdmx
= 1;
16231 else if (strcmp (name
, "nomdmx") == 0)
16232 mips_opts
.ase_mdmx
= 0;
16233 else if (strcmp (name
, "dsp") == 0)
16235 if (!ISA_SUPPORTS_DSP_ASE
)
16236 as_warn (_("%s ISA does not support DSP ASE"),
16237 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
16238 mips_opts
.ase_dsp
= 1;
16239 mips_opts
.ase_dspr2
= 0;
16241 else if (strcmp (name
, "nodsp") == 0)
16243 mips_opts
.ase_dsp
= 0;
16244 mips_opts
.ase_dspr2
= 0;
16246 else if (strcmp (name
, "dspr2") == 0)
16248 if (!ISA_SUPPORTS_DSPR2_ASE
)
16249 as_warn (_("%s ISA does not support DSP R2 ASE"),
16250 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
16251 mips_opts
.ase_dspr2
= 1;
16252 mips_opts
.ase_dsp
= 1;
16254 else if (strcmp (name
, "nodspr2") == 0)
16256 mips_opts
.ase_dspr2
= 0;
16257 mips_opts
.ase_dsp
= 0;
16259 else if (strcmp (name
, "mt") == 0)
16261 if (!ISA_SUPPORTS_MT_ASE
)
16262 as_warn (_("%s ISA does not support MT ASE"),
16263 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
16264 mips_opts
.ase_mt
= 1;
16266 else if (strcmp (name
, "nomt") == 0)
16267 mips_opts
.ase_mt
= 0;
16268 else if (strcmp (name
, "mcu") == 0)
16269 mips_opts
.ase_mcu
= 1;
16270 else if (strcmp (name
, "nomcu") == 0)
16271 mips_opts
.ase_mcu
= 0;
16272 else if (strncmp (name
, "mips", 4) == 0 || strncmp (name
, "arch=", 5) == 0)
16276 /* Permit the user to change the ISA and architecture on the fly.
16277 Needless to say, misuse can cause serious problems. */
16278 if (strcmp (name
, "mips0") == 0 || strcmp (name
, "arch=default") == 0)
16281 mips_opts
.isa
= file_mips_isa
;
16282 mips_opts
.arch
= file_mips_arch
;
16284 else if (strncmp (name
, "arch=", 5) == 0)
16286 const struct mips_cpu_info
*p
;
16288 p
= mips_parse_cpu("internal use", name
+ 5);
16290 as_bad (_("unknown architecture %s"), name
+ 5);
16293 mips_opts
.arch
= p
->cpu
;
16294 mips_opts
.isa
= p
->isa
;
16297 else if (strncmp (name
, "mips", 4) == 0)
16299 const struct mips_cpu_info
*p
;
16301 p
= mips_parse_cpu("internal use", name
);
16303 as_bad (_("unknown ISA level %s"), name
+ 4);
16306 mips_opts
.arch
= p
->cpu
;
16307 mips_opts
.isa
= p
->isa
;
16311 as_bad (_("unknown ISA or architecture %s"), name
);
16313 switch (mips_opts
.isa
)
16321 mips_opts
.gp32
= 1;
16322 mips_opts
.fp32
= 1;
16329 mips_opts
.gp32
= 0;
16330 mips_opts
.fp32
= 0;
16333 as_bad (_("unknown ISA level %s"), name
+ 4);
16338 mips_opts
.gp32
= file_mips_gp32
;
16339 mips_opts
.fp32
= file_mips_fp32
;
16342 else if (strcmp (name
, "autoextend") == 0)
16343 mips_opts
.noautoextend
= 0;
16344 else if (strcmp (name
, "noautoextend") == 0)
16345 mips_opts
.noautoextend
= 1;
16346 else if (strcmp (name
, "push") == 0)
16348 struct mips_option_stack
*s
;
16350 s
= (struct mips_option_stack
*) xmalloc (sizeof *s
);
16351 s
->next
= mips_opts_stack
;
16352 s
->options
= mips_opts
;
16353 mips_opts_stack
= s
;
16355 else if (strcmp (name
, "pop") == 0)
16357 struct mips_option_stack
*s
;
16359 s
= mips_opts_stack
;
16361 as_bad (_(".set pop with no .set push"));
16364 /* If we're changing the reorder mode we need to handle
16365 delay slots correctly. */
16366 if (s
->options
.noreorder
&& ! mips_opts
.noreorder
)
16367 start_noreorder ();
16368 else if (! s
->options
.noreorder
&& mips_opts
.noreorder
)
16371 mips_opts
= s
->options
;
16372 mips_opts_stack
= s
->next
;
16376 else if (strcmp (name
, "sym32") == 0)
16377 mips_opts
.sym32
= TRUE
;
16378 else if (strcmp (name
, "nosym32") == 0)
16379 mips_opts
.sym32
= FALSE
;
16380 else if (strchr (name
, ','))
16382 /* Generic ".set" directive; use the generic handler. */
16383 *input_line_pointer
= ch
;
16384 input_line_pointer
= name
;
16390 as_warn (_("Tried to set unrecognized symbol: %s\n"), name
);
16392 *input_line_pointer
= ch
;
16393 demand_empty_rest_of_line ();
16396 /* Handle the .abicalls pseudo-op. I believe this is equivalent to
16397 .option pic2. It means to generate SVR4 PIC calls. */
16400 s_abicalls (int ignore ATTRIBUTE_UNUSED
)
16402 mips_pic
= SVR4_PIC
;
16403 mips_abicalls
= TRUE
;
16405 if (g_switch_seen
&& g_switch_value
!= 0)
16406 as_warn (_("-G may not be used with SVR4 PIC code"));
16407 g_switch_value
= 0;
16409 bfd_set_gp_size (stdoutput
, 0);
16410 demand_empty_rest_of_line ();
16413 /* Handle the .cpload pseudo-op. This is used when generating SVR4
16414 PIC code. It sets the $gp register for the function based on the
16415 function address, which is in the register named in the argument.
16416 This uses a relocation against _gp_disp, which is handled specially
16417 by the linker. The result is:
16418 lui $gp,%hi(_gp_disp)
16419 addiu $gp,$gp,%lo(_gp_disp)
16420 addu $gp,$gp,.cpload argument
16421 The .cpload argument is normally $25 == $t9.
16423 The -mno-shared option changes this to:
16424 lui $gp,%hi(__gnu_local_gp)
16425 addiu $gp,$gp,%lo(__gnu_local_gp)
16426 and the argument is ignored. This saves an instruction, but the
16427 resulting code is not position independent; it uses an absolute
16428 address for __gnu_local_gp. Thus code assembled with -mno-shared
16429 can go into an ordinary executable, but not into a shared library. */
16432 s_cpload (int ignore ATTRIBUTE_UNUSED
)
16438 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
16439 .cpload is ignored. */
16440 if (mips_pic
!= SVR4_PIC
|| HAVE_NEWABI
)
16446 if (mips_opts
.mips16
)
16448 as_bad (_("%s not supported in MIPS16 mode"), ".cpload");
16449 ignore_rest_of_line ();
16453 /* .cpload should be in a .set noreorder section. */
16454 if (mips_opts
.noreorder
== 0)
16455 as_warn (_(".cpload not in noreorder section"));
16457 reg
= tc_get_register (0);
16459 /* If we need to produce a 64-bit address, we are better off using
16460 the default instruction sequence. */
16461 in_shared
= mips_in_shared
|| HAVE_64BIT_SYMBOLS
;
16463 ex
.X_op
= O_symbol
;
16464 ex
.X_add_symbol
= symbol_find_or_make (in_shared
? "_gp_disp" :
16466 ex
.X_op_symbol
= NULL
;
16467 ex
.X_add_number
= 0;
16469 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
16470 symbol_get_bfdsym (ex
.X_add_symbol
)->flags
|= BSF_OBJECT
;
16473 macro_build_lui (&ex
, mips_gp_register
);
16474 macro_build (&ex
, "addiu", "t,r,j", mips_gp_register
,
16475 mips_gp_register
, BFD_RELOC_LO16
);
16477 macro_build (NULL
, "addu", "d,v,t", mips_gp_register
,
16478 mips_gp_register
, reg
);
16481 demand_empty_rest_of_line ();
16484 /* Handle the .cpsetup pseudo-op defined for NewABI PIC code. The syntax is:
16485 .cpsetup $reg1, offset|$reg2, label
16487 If offset is given, this results in:
16488 sd $gp, offset($sp)
16489 lui $gp, %hi(%neg(%gp_rel(label)))
16490 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
16491 daddu $gp, $gp, $reg1
16493 If $reg2 is given, this results in:
16494 daddu $reg2, $gp, $0
16495 lui $gp, %hi(%neg(%gp_rel(label)))
16496 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
16497 daddu $gp, $gp, $reg1
16498 $reg1 is normally $25 == $t9.
16500 The -mno-shared option replaces the last three instructions with
16502 addiu $gp,$gp,%lo(_gp) */
16505 s_cpsetup (int ignore ATTRIBUTE_UNUSED
)
16507 expressionS ex_off
;
16508 expressionS ex_sym
;
16511 /* If we are not generating SVR4 PIC code, .cpsetup is ignored.
16512 We also need NewABI support. */
16513 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
16519 if (mips_opts
.mips16
)
16521 as_bad (_("%s not supported in MIPS16 mode"), ".cpsetup");
16522 ignore_rest_of_line ();
16526 reg1
= tc_get_register (0);
16527 SKIP_WHITESPACE ();
16528 if (*input_line_pointer
!= ',')
16530 as_bad (_("missing argument separator ',' for .cpsetup"));
16534 ++input_line_pointer
;
16535 SKIP_WHITESPACE ();
16536 if (*input_line_pointer
== '$')
16538 mips_cpreturn_register
= tc_get_register (0);
16539 mips_cpreturn_offset
= -1;
16543 mips_cpreturn_offset
= get_absolute_expression ();
16544 mips_cpreturn_register
= -1;
16546 SKIP_WHITESPACE ();
16547 if (*input_line_pointer
!= ',')
16549 as_bad (_("missing argument separator ',' for .cpsetup"));
16553 ++input_line_pointer
;
16554 SKIP_WHITESPACE ();
16555 expression (&ex_sym
);
16558 if (mips_cpreturn_register
== -1)
16560 ex_off
.X_op
= O_constant
;
16561 ex_off
.X_add_symbol
= NULL
;
16562 ex_off
.X_op_symbol
= NULL
;
16563 ex_off
.X_add_number
= mips_cpreturn_offset
;
16565 macro_build (&ex_off
, "sd", "t,o(b)", mips_gp_register
,
16566 BFD_RELOC_LO16
, SP
);
16569 macro_build (NULL
, "daddu", "d,v,t", mips_cpreturn_register
,
16570 mips_gp_register
, 0);
16572 if (mips_in_shared
|| HAVE_64BIT_SYMBOLS
)
16574 macro_build (&ex_sym
, "lui", LUI_FMT
, mips_gp_register
,
16575 -1, BFD_RELOC_GPREL16
, BFD_RELOC_MIPS_SUB
,
16578 macro_build (&ex_sym
, "addiu", "t,r,j", mips_gp_register
,
16579 mips_gp_register
, -1, BFD_RELOC_GPREL16
,
16580 BFD_RELOC_MIPS_SUB
, BFD_RELOC_LO16
);
16582 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", mips_gp_register
,
16583 mips_gp_register
, reg1
);
16589 ex
.X_op
= O_symbol
;
16590 ex
.X_add_symbol
= symbol_find_or_make ("__gnu_local_gp");
16591 ex
.X_op_symbol
= NULL
;
16592 ex
.X_add_number
= 0;
16594 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
16595 symbol_get_bfdsym (ex
.X_add_symbol
)->flags
|= BSF_OBJECT
;
16597 macro_build_lui (&ex
, mips_gp_register
);
16598 macro_build (&ex
, "addiu", "t,r,j", mips_gp_register
,
16599 mips_gp_register
, BFD_RELOC_LO16
);
16604 demand_empty_rest_of_line ();
16608 s_cplocal (int ignore ATTRIBUTE_UNUSED
)
16610 /* If we are not generating SVR4 PIC code, or if this is not NewABI code,
16611 .cplocal is ignored. */
16612 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
16618 if (mips_opts
.mips16
)
16620 as_bad (_("%s not supported in MIPS16 mode"), ".cplocal");
16621 ignore_rest_of_line ();
16625 mips_gp_register
= tc_get_register (0);
16626 demand_empty_rest_of_line ();
16629 /* Handle the .cprestore pseudo-op. This stores $gp into a given
16630 offset from $sp. The offset is remembered, and after making a PIC
16631 call $gp is restored from that location. */
16634 s_cprestore (int ignore ATTRIBUTE_UNUSED
)
16638 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
16639 .cprestore is ignored. */
16640 if (mips_pic
!= SVR4_PIC
|| HAVE_NEWABI
)
16646 if (mips_opts
.mips16
)
16648 as_bad (_("%s not supported in MIPS16 mode"), ".cprestore");
16649 ignore_rest_of_line ();
16653 mips_cprestore_offset
= get_absolute_expression ();
16654 mips_cprestore_valid
= 1;
16656 ex
.X_op
= O_constant
;
16657 ex
.X_add_symbol
= NULL
;
16658 ex
.X_op_symbol
= NULL
;
16659 ex
.X_add_number
= mips_cprestore_offset
;
16662 macro_build_ldst_constoffset (&ex
, ADDRESS_STORE_INSN
, mips_gp_register
,
16663 SP
, HAVE_64BIT_ADDRESSES
);
16666 demand_empty_rest_of_line ();
16669 /* Handle the .cpreturn pseudo-op defined for NewABI PIC code. If an offset
16670 was given in the preceding .cpsetup, it results in:
16671 ld $gp, offset($sp)
16673 If a register $reg2 was given there, it results in:
16674 daddu $gp, $reg2, $0 */
16677 s_cpreturn (int ignore ATTRIBUTE_UNUSED
)
16681 /* If we are not generating SVR4 PIC code, .cpreturn is ignored.
16682 We also need NewABI support. */
16683 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
16689 if (mips_opts
.mips16
)
16691 as_bad (_("%s not supported in MIPS16 mode"), ".cpreturn");
16692 ignore_rest_of_line ();
16697 if (mips_cpreturn_register
== -1)
16699 ex
.X_op
= O_constant
;
16700 ex
.X_add_symbol
= NULL
;
16701 ex
.X_op_symbol
= NULL
;
16702 ex
.X_add_number
= mips_cpreturn_offset
;
16704 macro_build (&ex
, "ld", "t,o(b)", mips_gp_register
, BFD_RELOC_LO16
, SP
);
16707 macro_build (NULL
, "daddu", "d,v,t", mips_gp_register
,
16708 mips_cpreturn_register
, 0);
16711 demand_empty_rest_of_line ();
16714 /* Handle a .dtprelword, .dtpreldword, .tprelword, or .tpreldword
16715 pseudo-op; DIRSTR says which. The pseudo-op generates a BYTES-size
16716 DTP- or TP-relative relocation of type RTYPE, for use in either DWARF
16717 debug information or MIPS16 TLS. */
16720 s_tls_rel_directive (const size_t bytes
, const char *dirstr
,
16721 bfd_reloc_code_real_type rtype
)
16728 if (ex
.X_op
!= O_symbol
)
16730 as_bad (_("Unsupported use of %s"), dirstr
);
16731 ignore_rest_of_line ();
16734 p
= frag_more (bytes
);
16735 md_number_to_chars (p
, 0, bytes
);
16736 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, bytes
, &ex
, FALSE
, rtype
);
16737 demand_empty_rest_of_line ();
16738 mips_clear_insn_labels ();
16741 /* Handle .dtprelword. */
16744 s_dtprelword (int ignore ATTRIBUTE_UNUSED
)
16746 s_tls_rel_directive (4, ".dtprelword", BFD_RELOC_MIPS_TLS_DTPREL32
);
16749 /* Handle .dtpreldword. */
16752 s_dtpreldword (int ignore ATTRIBUTE_UNUSED
)
16754 s_tls_rel_directive (8, ".dtpreldword", BFD_RELOC_MIPS_TLS_DTPREL64
);
16757 /* Handle .tprelword. */
16760 s_tprelword (int ignore ATTRIBUTE_UNUSED
)
16762 s_tls_rel_directive (4, ".tprelword", BFD_RELOC_MIPS_TLS_TPREL32
);
16765 /* Handle .tpreldword. */
16768 s_tpreldword (int ignore ATTRIBUTE_UNUSED
)
16770 s_tls_rel_directive (8, ".tpreldword", BFD_RELOC_MIPS_TLS_TPREL64
);
16773 /* Handle the .gpvalue pseudo-op. This is used when generating NewABI PIC
16774 code. It sets the offset to use in gp_rel relocations. */
16777 s_gpvalue (int ignore ATTRIBUTE_UNUSED
)
16779 /* If we are not generating SVR4 PIC code, .gpvalue is ignored.
16780 We also need NewABI support. */
16781 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
16787 mips_gprel_offset
= get_absolute_expression ();
16789 demand_empty_rest_of_line ();
16792 /* Handle the .gpword pseudo-op. This is used when generating PIC
16793 code. It generates a 32 bit GP relative reloc. */
16796 s_gpword (int ignore ATTRIBUTE_UNUSED
)
16798 segment_info_type
*si
;
16799 struct insn_label_list
*l
;
16803 /* When not generating PIC code, this is treated as .word. */
16804 if (mips_pic
!= SVR4_PIC
)
16810 si
= seg_info (now_seg
);
16811 l
= si
->label_list
;
16812 mips_emit_delays ();
16814 mips_align (2, 0, l
);
16817 mips_clear_insn_labels ();
16819 if (ex
.X_op
!= O_symbol
|| ex
.X_add_number
!= 0)
16821 as_bad (_("Unsupported use of .gpword"));
16822 ignore_rest_of_line ();
16826 md_number_to_chars (p
, 0, 4);
16827 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 4, &ex
, FALSE
,
16828 BFD_RELOC_GPREL32
);
16830 demand_empty_rest_of_line ();
16834 s_gpdword (int ignore ATTRIBUTE_UNUSED
)
16836 segment_info_type
*si
;
16837 struct insn_label_list
*l
;
16841 /* When not generating PIC code, this is treated as .dword. */
16842 if (mips_pic
!= SVR4_PIC
)
16848 si
= seg_info (now_seg
);
16849 l
= si
->label_list
;
16850 mips_emit_delays ();
16852 mips_align (3, 0, l
);
16855 mips_clear_insn_labels ();
16857 if (ex
.X_op
!= O_symbol
|| ex
.X_add_number
!= 0)
16859 as_bad (_("Unsupported use of .gpdword"));
16860 ignore_rest_of_line ();
16864 md_number_to_chars (p
, 0, 8);
16865 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 4, &ex
, FALSE
,
16866 BFD_RELOC_GPREL32
)->fx_tcbit
= 1;
16868 /* GPREL32 composed with 64 gives a 64-bit GP offset. */
16869 fix_new (frag_now
, p
- frag_now
->fr_literal
, 8, NULL
, 0,
16870 FALSE
, BFD_RELOC_64
)->fx_tcbit
= 1;
16872 demand_empty_rest_of_line ();
16875 /* Handle the .cpadd pseudo-op. This is used when dealing with switch
16876 tables in SVR4 PIC code. */
16879 s_cpadd (int ignore ATTRIBUTE_UNUSED
)
16883 /* This is ignored when not generating SVR4 PIC code. */
16884 if (mips_pic
!= SVR4_PIC
)
16890 /* Add $gp to the register named as an argument. */
16892 reg
= tc_get_register (0);
16893 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", reg
, reg
, mips_gp_register
);
16896 demand_empty_rest_of_line ();
16899 /* Handle the .insn pseudo-op. This marks instruction labels in
16900 mips16/micromips mode. This permits the linker to handle them specially,
16901 such as generating jalx instructions when needed. We also make
16902 them odd for the duration of the assembly, in order to generate the
16903 right sort of code. We will make them even in the adjust_symtab
16904 routine, while leaving them marked. This is convenient for the
16905 debugger and the disassembler. The linker knows to make them odd
16909 s_insn (int ignore ATTRIBUTE_UNUSED
)
16911 mips_mark_labels ();
16913 demand_empty_rest_of_line ();
16916 /* Handle a .stabn directive. We need these in order to mark a label
16917 as being a mips16 text label correctly. Sometimes the compiler
16918 will emit a label, followed by a .stabn, and then switch sections.
16919 If the label and .stabn are in mips16 mode, then the label is
16920 really a mips16 text label. */
16923 s_mips_stab (int type
)
16926 mips_mark_labels ();
16931 /* Handle the .weakext pseudo-op as defined in Kane and Heinrich. */
16934 s_mips_weakext (int ignore ATTRIBUTE_UNUSED
)
16941 name
= input_line_pointer
;
16942 c
= get_symbol_end ();
16943 symbolP
= symbol_find_or_make (name
);
16944 S_SET_WEAK (symbolP
);
16945 *input_line_pointer
= c
;
16947 SKIP_WHITESPACE ();
16949 if (! is_end_of_line
[(unsigned char) *input_line_pointer
])
16951 if (S_IS_DEFINED (symbolP
))
16953 as_bad (_("ignoring attempt to redefine symbol %s"),
16954 S_GET_NAME (symbolP
));
16955 ignore_rest_of_line ();
16959 if (*input_line_pointer
== ',')
16961 ++input_line_pointer
;
16962 SKIP_WHITESPACE ();
16966 if (exp
.X_op
!= O_symbol
)
16968 as_bad (_("bad .weakext directive"));
16969 ignore_rest_of_line ();
16972 symbol_set_value_expression (symbolP
, &exp
);
16975 demand_empty_rest_of_line ();
16978 /* Parse a register string into a number. Called from the ECOFF code
16979 to parse .frame. The argument is non-zero if this is the frame
16980 register, so that we can record it in mips_frame_reg. */
16983 tc_get_register (int frame
)
16987 SKIP_WHITESPACE ();
16988 if (! reg_lookup (&input_line_pointer
, RWARN
| RTYPE_NUM
| RTYPE_GP
, ®
))
16992 mips_frame_reg
= reg
!= 0 ? reg
: SP
;
16993 mips_frame_reg_valid
= 1;
16994 mips_cprestore_valid
= 0;
17000 md_section_align (asection
*seg
, valueT addr
)
17002 int align
= bfd_get_section_alignment (stdoutput
, seg
);
17006 /* We don't need to align ELF sections to the full alignment.
17007 However, Irix 5 may prefer that we align them at least to a 16
17008 byte boundary. We don't bother to align the sections if we
17009 are targeted for an embedded system. */
17010 if (strncmp (TARGET_OS
, "elf", 3) == 0)
17016 return ((addr
+ (1 << align
) - 1) & (-1 << align
));
17019 /* Utility routine, called from above as well. If called while the
17020 input file is still being read, it's only an approximation. (For
17021 example, a symbol may later become defined which appeared to be
17022 undefined earlier.) */
17025 nopic_need_relax (symbolS
*sym
, int before_relaxing
)
17030 if (g_switch_value
> 0)
17032 const char *symname
;
17035 /* Find out whether this symbol can be referenced off the $gp
17036 register. It can be if it is smaller than the -G size or if
17037 it is in the .sdata or .sbss section. Certain symbols can
17038 not be referenced off the $gp, although it appears as though
17040 symname
= S_GET_NAME (sym
);
17041 if (symname
!= (const char *) NULL
17042 && (strcmp (symname
, "eprol") == 0
17043 || strcmp (symname
, "etext") == 0
17044 || strcmp (symname
, "_gp") == 0
17045 || strcmp (symname
, "edata") == 0
17046 || strcmp (symname
, "_fbss") == 0
17047 || strcmp (symname
, "_fdata") == 0
17048 || strcmp (symname
, "_ftext") == 0
17049 || strcmp (symname
, "end") == 0
17050 || strcmp (symname
, "_gp_disp") == 0))
17052 else if ((! S_IS_DEFINED (sym
) || S_IS_COMMON (sym
))
17054 #ifndef NO_ECOFF_DEBUGGING
17055 || (symbol_get_obj (sym
)->ecoff_extern_size
!= 0
17056 && (symbol_get_obj (sym
)->ecoff_extern_size
17057 <= g_switch_value
))
17059 /* We must defer this decision until after the whole
17060 file has been read, since there might be a .extern
17061 after the first use of this symbol. */
17062 || (before_relaxing
17063 #ifndef NO_ECOFF_DEBUGGING
17064 && symbol_get_obj (sym
)->ecoff_extern_size
== 0
17066 && S_GET_VALUE (sym
) == 0)
17067 || (S_GET_VALUE (sym
) != 0
17068 && S_GET_VALUE (sym
) <= g_switch_value
)))
17072 const char *segname
;
17074 segname
= segment_name (S_GET_SEGMENT (sym
));
17075 gas_assert (strcmp (segname
, ".lit8") != 0
17076 && strcmp (segname
, ".lit4") != 0);
17077 change
= (strcmp (segname
, ".sdata") != 0
17078 && strcmp (segname
, ".sbss") != 0
17079 && strncmp (segname
, ".sdata.", 7) != 0
17080 && strncmp (segname
, ".sbss.", 6) != 0
17081 && strncmp (segname
, ".gnu.linkonce.sb.", 17) != 0
17082 && strncmp (segname
, ".gnu.linkonce.s.", 16) != 0);
17087 /* We are not optimizing for the $gp register. */
17092 /* Return true if the given symbol should be considered local for SVR4 PIC. */
17095 pic_need_relax (symbolS
*sym
, asection
*segtype
)
17099 /* Handle the case of a symbol equated to another symbol. */
17100 while (symbol_equated_reloc_p (sym
))
17104 /* It's possible to get a loop here in a badly written program. */
17105 n
= symbol_get_value_expression (sym
)->X_add_symbol
;
17111 if (symbol_section_p (sym
))
17114 symsec
= S_GET_SEGMENT (sym
);
17116 /* This must duplicate the test in adjust_reloc_syms. */
17117 return (!bfd_is_und_section (symsec
)
17118 && !bfd_is_abs_section (symsec
)
17119 && !bfd_is_com_section (symsec
)
17120 && !s_is_linkonce (sym
, segtype
)
17122 /* A global or weak symbol is treated as external. */
17123 && (!IS_ELF
|| (! S_IS_WEAK (sym
) && ! S_IS_EXTERNAL (sym
)))
17129 /* Given a mips16 variant frag FRAGP, return non-zero if it needs an
17130 extended opcode. SEC is the section the frag is in. */
17133 mips16_extended_frag (fragS
*fragp
, asection
*sec
, long stretch
)
17136 const struct mips16_immed_operand
*op
;
17138 int mintiny
, maxtiny
;
17142 if (RELAX_MIPS16_USER_SMALL (fragp
->fr_subtype
))
17144 if (RELAX_MIPS16_USER_EXT (fragp
->fr_subtype
))
17147 type
= RELAX_MIPS16_TYPE (fragp
->fr_subtype
);
17148 op
= mips16_immed_operands
;
17149 while (op
->type
!= type
)
17152 gas_assert (op
< mips16_immed_operands
+ MIPS16_NUM_IMMED
);
17157 if (type
== '<' || type
== '>' || type
== '[' || type
== ']')
17160 maxtiny
= 1 << op
->nbits
;
17165 maxtiny
= (1 << op
->nbits
) - 1;
17170 mintiny
= - (1 << (op
->nbits
- 1));
17171 maxtiny
= (1 << (op
->nbits
- 1)) - 1;
17174 sym_frag
= symbol_get_frag (fragp
->fr_symbol
);
17175 val
= S_GET_VALUE (fragp
->fr_symbol
);
17176 symsec
= S_GET_SEGMENT (fragp
->fr_symbol
);
17182 /* We won't have the section when we are called from
17183 mips_relax_frag. However, we will always have been called
17184 from md_estimate_size_before_relax first. If this is a
17185 branch to a different section, we mark it as such. If SEC is
17186 NULL, and the frag is not marked, then it must be a branch to
17187 the same section. */
17190 if (RELAX_MIPS16_LONG_BRANCH (fragp
->fr_subtype
))
17195 /* Must have been called from md_estimate_size_before_relax. */
17198 fragp
->fr_subtype
=
17199 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
17201 /* FIXME: We should support this, and let the linker
17202 catch branches and loads that are out of range. */
17203 as_bad_where (fragp
->fr_file
, fragp
->fr_line
,
17204 _("unsupported PC relative reference to different section"));
17208 if (fragp
!= sym_frag
&& sym_frag
->fr_address
== 0)
17209 /* Assume non-extended on the first relaxation pass.
17210 The address we have calculated will be bogus if this is
17211 a forward branch to another frag, as the forward frag
17212 will have fr_address == 0. */
17216 /* In this case, we know for sure that the symbol fragment is in
17217 the same section. If the relax_marker of the symbol fragment
17218 differs from the relax_marker of this fragment, we have not
17219 yet adjusted the symbol fragment fr_address. We want to add
17220 in STRETCH in order to get a better estimate of the address.
17221 This particularly matters because of the shift bits. */
17223 && sym_frag
->relax_marker
!= fragp
->relax_marker
)
17227 /* Adjust stretch for any alignment frag. Note that if have
17228 been expanding the earlier code, the symbol may be
17229 defined in what appears to be an earlier frag. FIXME:
17230 This doesn't handle the fr_subtype field, which specifies
17231 a maximum number of bytes to skip when doing an
17233 for (f
= fragp
; f
!= NULL
&& f
!= sym_frag
; f
= f
->fr_next
)
17235 if (f
->fr_type
== rs_align
|| f
->fr_type
== rs_align_code
)
17238 stretch
= - ((- stretch
)
17239 & ~ ((1 << (int) f
->fr_offset
) - 1));
17241 stretch
&= ~ ((1 << (int) f
->fr_offset
) - 1);
17250 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
17252 /* The base address rules are complicated. The base address of
17253 a branch is the following instruction. The base address of a
17254 PC relative load or add is the instruction itself, but if it
17255 is in a delay slot (in which case it can not be extended) use
17256 the address of the instruction whose delay slot it is in. */
17257 if (type
== 'p' || type
== 'q')
17261 /* If we are currently assuming that this frag should be
17262 extended, then, the current address is two bytes
17264 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
17267 /* Ignore the low bit in the target, since it will be set
17268 for a text label. */
17269 if ((val
& 1) != 0)
17272 else if (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
))
17274 else if (RELAX_MIPS16_DSLOT (fragp
->fr_subtype
))
17277 val
-= addr
& ~ ((1 << op
->shift
) - 1);
17279 /* Branch offsets have an implicit 0 in the lowest bit. */
17280 if (type
== 'p' || type
== 'q')
17283 /* If any of the shifted bits are set, we must use an extended
17284 opcode. If the address depends on the size of this
17285 instruction, this can lead to a loop, so we arrange to always
17286 use an extended opcode. We only check this when we are in
17287 the main relaxation loop, when SEC is NULL. */
17288 if ((val
& ((1 << op
->shift
) - 1)) != 0 && sec
== NULL
)
17290 fragp
->fr_subtype
=
17291 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
17295 /* If we are about to mark a frag as extended because the value
17296 is precisely maxtiny + 1, then there is a chance of an
17297 infinite loop as in the following code:
17302 In this case when the la is extended, foo is 0x3fc bytes
17303 away, so the la can be shrunk, but then foo is 0x400 away, so
17304 the la must be extended. To avoid this loop, we mark the
17305 frag as extended if it was small, and is about to become
17306 extended with a value of maxtiny + 1. */
17307 if (val
== ((maxtiny
+ 1) << op
->shift
)
17308 && ! RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
)
17311 fragp
->fr_subtype
=
17312 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
17316 else if (symsec
!= absolute_section
&& sec
!= NULL
)
17317 as_bad_where (fragp
->fr_file
, fragp
->fr_line
, _("unsupported relocation"));
17319 if ((val
& ((1 << op
->shift
) - 1)) != 0
17320 || val
< (mintiny
<< op
->shift
)
17321 || val
> (maxtiny
<< op
->shift
))
17327 /* Compute the length of a branch sequence, and adjust the
17328 RELAX_BRANCH_TOOFAR bit accordingly. If FRAGP is NULL, the
17329 worst-case length is computed, with UPDATE being used to indicate
17330 whether an unconditional (-1), branch-likely (+1) or regular (0)
17331 branch is to be computed. */
17333 relaxed_branch_length (fragS
*fragp
, asection
*sec
, int update
)
17335 bfd_boolean toofar
;
17339 && S_IS_DEFINED (fragp
->fr_symbol
)
17340 && sec
== S_GET_SEGMENT (fragp
->fr_symbol
))
17345 val
= S_GET_VALUE (fragp
->fr_symbol
) + fragp
->fr_offset
;
17347 addr
= fragp
->fr_address
+ fragp
->fr_fix
+ 4;
17351 toofar
= val
< - (0x8000 << 2) || val
>= (0x8000 << 2);
17354 /* If the symbol is not defined or it's in a different segment,
17355 assume the user knows what's going on and emit a short
17361 if (fragp
&& update
&& toofar
!= RELAX_BRANCH_TOOFAR (fragp
->fr_subtype
))
17363 = RELAX_BRANCH_ENCODE (RELAX_BRANCH_AT (fragp
->fr_subtype
),
17364 RELAX_BRANCH_UNCOND (fragp
->fr_subtype
),
17365 RELAX_BRANCH_LIKELY (fragp
->fr_subtype
),
17366 RELAX_BRANCH_LINK (fragp
->fr_subtype
),
17372 if (fragp
? RELAX_BRANCH_LIKELY (fragp
->fr_subtype
) : (update
> 0))
17375 if (mips_pic
!= NO_PIC
)
17377 /* Additional space for PIC loading of target address. */
17379 if (mips_opts
.isa
== ISA_MIPS1
)
17380 /* Additional space for $at-stabilizing nop. */
17384 /* If branch is conditional. */
17385 if (fragp
? !RELAX_BRANCH_UNCOND (fragp
->fr_subtype
) : (update
>= 0))
17392 /* Compute the length of a branch sequence, and adjust the
17393 RELAX_MICROMIPS_TOOFAR32 bit accordingly. If FRAGP is NULL, the
17394 worst-case length is computed, with UPDATE being used to indicate
17395 whether an unconditional (-1), or regular (0) branch is to be
17399 relaxed_micromips_32bit_branch_length (fragS
*fragp
, asection
*sec
, int update
)
17401 bfd_boolean toofar
;
17405 && S_IS_DEFINED (fragp
->fr_symbol
)
17406 && sec
== S_GET_SEGMENT (fragp
->fr_symbol
))
17411 val
= S_GET_VALUE (fragp
->fr_symbol
) + fragp
->fr_offset
;
17412 /* Ignore the low bit in the target, since it will be set
17413 for a text label. */
17414 if ((val
& 1) != 0)
17417 addr
= fragp
->fr_address
+ fragp
->fr_fix
+ 4;
17421 toofar
= val
< - (0x8000 << 1) || val
>= (0x8000 << 1);
17424 /* If the symbol is not defined or it's in a different segment,
17425 assume the user knows what's going on and emit a short
17431 if (fragp
&& update
17432 && toofar
!= RELAX_MICROMIPS_TOOFAR32 (fragp
->fr_subtype
))
17433 fragp
->fr_subtype
= (toofar
17434 ? RELAX_MICROMIPS_MARK_TOOFAR32 (fragp
->fr_subtype
)
17435 : RELAX_MICROMIPS_CLEAR_TOOFAR32 (fragp
->fr_subtype
));
17440 bfd_boolean compact_known
= fragp
!= NULL
;
17441 bfd_boolean compact
= FALSE
;
17442 bfd_boolean uncond
;
17445 compact
= RELAX_MICROMIPS_COMPACT (fragp
->fr_subtype
);
17447 uncond
= RELAX_MICROMIPS_UNCOND (fragp
->fr_subtype
);
17449 uncond
= update
< 0;
17451 /* If label is out of range, we turn branch <br>:
17453 <br> label # 4 bytes
17459 nop # 2 bytes if compact && !PIC
17462 if (mips_pic
== NO_PIC
&& (!compact_known
|| compact
))
17465 /* If assembling PIC code, we further turn:
17471 lw/ld at, %got(label)(gp) # 4 bytes
17472 d/addiu at, %lo(label) # 4 bytes
17475 if (mips_pic
!= NO_PIC
)
17478 /* If branch <br> is conditional, we prepend negated branch <brneg>:
17480 <brneg> 0f # 4 bytes
17481 nop # 2 bytes if !compact
17484 length
+= (compact_known
&& compact
) ? 4 : 6;
17490 /* Compute the length of a branch, and adjust the RELAX_MICROMIPS_TOOFAR16
17491 bit accordingly. */
17494 relaxed_micromips_16bit_branch_length (fragS
*fragp
, asection
*sec
, int update
)
17496 bfd_boolean toofar
;
17499 && S_IS_DEFINED (fragp
->fr_symbol
)
17500 && sec
== S_GET_SEGMENT (fragp
->fr_symbol
))
17506 val
= S_GET_VALUE (fragp
->fr_symbol
) + fragp
->fr_offset
;
17507 /* Ignore the low bit in the target, since it will be set
17508 for a text label. */
17509 if ((val
& 1) != 0)
17512 /* Assume this is a 2-byte branch. */
17513 addr
= fragp
->fr_address
+ fragp
->fr_fix
+ 2;
17515 /* We try to avoid the infinite loop by not adding 2 more bytes for
17520 type
= RELAX_MICROMIPS_TYPE (fragp
->fr_subtype
);
17522 toofar
= val
< - (0x200 << 1) || val
>= (0x200 << 1);
17523 else if (type
== 'E')
17524 toofar
= val
< - (0x40 << 1) || val
>= (0x40 << 1);
17529 /* If the symbol is not defined or it's in a different segment,
17530 we emit a normal 32-bit branch. */
17533 if (fragp
&& update
17534 && toofar
!= RELAX_MICROMIPS_TOOFAR16 (fragp
->fr_subtype
))
17536 = toofar
? RELAX_MICROMIPS_MARK_TOOFAR16 (fragp
->fr_subtype
)
17537 : RELAX_MICROMIPS_CLEAR_TOOFAR16 (fragp
->fr_subtype
);
17545 /* Estimate the size of a frag before relaxing. Unless this is the
17546 mips16, we are not really relaxing here, and the final size is
17547 encoded in the subtype information. For the mips16, we have to
17548 decide whether we are using an extended opcode or not. */
17551 md_estimate_size_before_relax (fragS
*fragp
, asection
*segtype
)
17555 if (RELAX_BRANCH_P (fragp
->fr_subtype
))
17558 fragp
->fr_var
= relaxed_branch_length (fragp
, segtype
, FALSE
);
17560 return fragp
->fr_var
;
17563 if (RELAX_MIPS16_P (fragp
->fr_subtype
))
17564 /* We don't want to modify the EXTENDED bit here; it might get us
17565 into infinite loops. We change it only in mips_relax_frag(). */
17566 return (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
) ? 4 : 2);
17568 if (RELAX_MICROMIPS_P (fragp
->fr_subtype
))
17572 if (RELAX_MICROMIPS_TYPE (fragp
->fr_subtype
) != 0)
17573 length
= relaxed_micromips_16bit_branch_length (fragp
, segtype
, FALSE
);
17574 if (length
== 4 && RELAX_MICROMIPS_RELAX32 (fragp
->fr_subtype
))
17575 length
= relaxed_micromips_32bit_branch_length (fragp
, segtype
, FALSE
);
17576 fragp
->fr_var
= length
;
17581 if (mips_pic
== NO_PIC
)
17582 change
= nopic_need_relax (fragp
->fr_symbol
, 0);
17583 else if (mips_pic
== SVR4_PIC
)
17584 change
= pic_need_relax (fragp
->fr_symbol
, segtype
);
17585 else if (mips_pic
== VXWORKS_PIC
)
17586 /* For vxworks, GOT16 relocations never have a corresponding LO16. */
17593 fragp
->fr_subtype
|= RELAX_USE_SECOND
;
17594 return -RELAX_FIRST (fragp
->fr_subtype
);
17597 return -RELAX_SECOND (fragp
->fr_subtype
);
17600 /* This is called to see whether a reloc against a defined symbol
17601 should be converted into a reloc against a section. */
17604 mips_fix_adjustable (fixS
*fixp
)
17606 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
17607 || fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
17610 if (fixp
->fx_addsy
== NULL
)
17613 /* If symbol SYM is in a mergeable section, relocations of the form
17614 SYM + 0 can usually be made section-relative. The mergeable data
17615 is then identified by the section offset rather than by the symbol.
17617 However, if we're generating REL LO16 relocations, the offset is split
17618 between the LO16 and parterning high part relocation. The linker will
17619 need to recalculate the complete offset in order to correctly identify
17622 The linker has traditionally not looked for the parterning high part
17623 relocation, and has thus allowed orphaned R_MIPS_LO16 relocations to be
17624 placed anywhere. Rather than break backwards compatibility by changing
17625 this, it seems better not to force the issue, and instead keep the
17626 original symbol. This will work with either linker behavior. */
17627 if ((lo16_reloc_p (fixp
->fx_r_type
)
17628 || reloc_needs_lo_p (fixp
->fx_r_type
))
17629 && HAVE_IN_PLACE_ADDENDS
17630 && (S_GET_SEGMENT (fixp
->fx_addsy
)->flags
& SEC_MERGE
) != 0)
17633 /* There is no place to store an in-place offset for JALR relocations.
17634 Likewise an in-range offset of PC-relative relocations may overflow
17635 the in-place relocatable field if recalculated against the start
17636 address of the symbol's containing section. */
17637 if (HAVE_IN_PLACE_ADDENDS
17638 && (fixp
->fx_pcrel
|| jalr_reloc_p (fixp
->fx_r_type
)))
17642 /* R_MIPS16_26 relocations against non-MIPS16 functions might resolve
17643 to a floating-point stub. The same is true for non-R_MIPS16_26
17644 relocations against MIPS16 functions; in this case, the stub becomes
17645 the function's canonical address.
17647 Floating-point stubs are stored in unique .mips16.call.* or
17648 .mips16.fn.* sections. If a stub T for function F is in section S,
17649 the first relocation in section S must be against F; this is how the
17650 linker determines the target function. All relocations that might
17651 resolve to T must also be against F. We therefore have the following
17652 restrictions, which are given in an intentionally-redundant way:
17654 1. We cannot reduce R_MIPS16_26 relocations against non-MIPS16
17657 2. We cannot reduce a stub's relocations against non-MIPS16 symbols
17658 if that stub might be used.
17660 3. We cannot reduce non-R_MIPS16_26 relocations against MIPS16
17663 4. We cannot reduce a stub's relocations against MIPS16 symbols if
17664 that stub might be used.
17666 There is a further restriction:
17668 5. We cannot reduce jump relocations (R_MIPS_26, R_MIPS16_26 or
17669 R_MICROMIPS_26_S1) against MIPS16 or microMIPS symbols on
17670 targets with in-place addends; the relocation field cannot
17671 encode the low bit.
17673 For simplicity, we deal with (3)-(4) by not reducing _any_ relocation
17674 against a MIPS16 symbol. We deal with (5) by by not reducing any
17675 such relocations on REL targets.
17677 We deal with (1)-(2) by saying that, if there's a R_MIPS16_26
17678 relocation against some symbol R, no relocation against R may be
17679 reduced. (Note that this deals with (2) as well as (1) because
17680 relocations against global symbols will never be reduced on ELF
17681 targets.) This approach is a little simpler than trying to detect
17682 stub sections, and gives the "all or nothing" per-symbol consistency
17683 that we have for MIPS16 symbols. */
17685 && fixp
->fx_subsy
== NULL
17686 && (ELF_ST_IS_MIPS16 (S_GET_OTHER (fixp
->fx_addsy
))
17687 || *symbol_get_tc (fixp
->fx_addsy
)
17688 || (HAVE_IN_PLACE_ADDENDS
17689 && ELF_ST_IS_MICROMIPS (S_GET_OTHER (fixp
->fx_addsy
))
17690 && jmp_reloc_p (fixp
->fx_r_type
))))
17697 /* Translate internal representation of relocation info to BFD target
17701 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
, fixS
*fixp
)
17703 static arelent
*retval
[4];
17705 bfd_reloc_code_real_type code
;
17707 memset (retval
, 0, sizeof(retval
));
17708 reloc
= retval
[0] = (arelent
*) xcalloc (1, sizeof (arelent
));
17709 reloc
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
17710 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
17711 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
17713 if (fixp
->fx_pcrel
)
17715 gas_assert (fixp
->fx_r_type
== BFD_RELOC_16_PCREL_S2
17716 || fixp
->fx_r_type
== BFD_RELOC_MICROMIPS_7_PCREL_S1
17717 || fixp
->fx_r_type
== BFD_RELOC_MICROMIPS_10_PCREL_S1
17718 || fixp
->fx_r_type
== BFD_RELOC_MICROMIPS_16_PCREL_S1
);
17720 /* At this point, fx_addnumber is "symbol offset - pcrel address".
17721 Relocations want only the symbol offset. */
17722 reloc
->addend
= fixp
->fx_addnumber
+ reloc
->address
;
17725 /* A gruesome hack which is a result of the gruesome gas
17726 reloc handling. What's worse, for COFF (as opposed to
17727 ECOFF), we might need yet another copy of reloc->address.
17728 See bfd_install_relocation. */
17729 reloc
->addend
+= reloc
->address
;
17733 reloc
->addend
= fixp
->fx_addnumber
;
17735 /* Since the old MIPS ELF ABI uses Rel instead of Rela, encode the vtable
17736 entry to be used in the relocation's section offset. */
17737 if (! HAVE_NEWABI
&& fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
17739 reloc
->address
= reloc
->addend
;
17743 code
= fixp
->fx_r_type
;
17745 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
17746 if (reloc
->howto
== NULL
)
17748 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
17749 _("Can not represent %s relocation in this object file format"),
17750 bfd_get_reloc_code_name (code
));
17757 /* Relax a machine dependent frag. This returns the amount by which
17758 the current size of the frag should change. */
17761 mips_relax_frag (asection
*sec
, fragS
*fragp
, long stretch
)
17763 if (RELAX_BRANCH_P (fragp
->fr_subtype
))
17765 offsetT old_var
= fragp
->fr_var
;
17767 fragp
->fr_var
= relaxed_branch_length (fragp
, sec
, TRUE
);
17769 return fragp
->fr_var
- old_var
;
17772 if (RELAX_MICROMIPS_P (fragp
->fr_subtype
))
17774 offsetT old_var
= fragp
->fr_var
;
17775 offsetT new_var
= 4;
17777 if (RELAX_MICROMIPS_TYPE (fragp
->fr_subtype
) != 0)
17778 new_var
= relaxed_micromips_16bit_branch_length (fragp
, sec
, TRUE
);
17779 if (new_var
== 4 && RELAX_MICROMIPS_RELAX32 (fragp
->fr_subtype
))
17780 new_var
= relaxed_micromips_32bit_branch_length (fragp
, sec
, TRUE
);
17781 fragp
->fr_var
= new_var
;
17783 return new_var
- old_var
;
17786 if (! RELAX_MIPS16_P (fragp
->fr_subtype
))
17789 if (mips16_extended_frag (fragp
, NULL
, stretch
))
17791 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
17793 fragp
->fr_subtype
= RELAX_MIPS16_MARK_EXTENDED (fragp
->fr_subtype
);
17798 if (! RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
17800 fragp
->fr_subtype
= RELAX_MIPS16_CLEAR_EXTENDED (fragp
->fr_subtype
);
17807 /* Convert a machine dependent frag. */
17810 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
, segT asec
, fragS
*fragp
)
17812 if (RELAX_BRANCH_P (fragp
->fr_subtype
))
17815 unsigned long insn
;
17819 buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
17820 insn
= read_insn (buf
);
17822 if (!RELAX_BRANCH_TOOFAR (fragp
->fr_subtype
))
17824 /* We generate a fixup instead of applying it right now
17825 because, if there are linker relaxations, we're going to
17826 need the relocations. */
17827 exp
.X_op
= O_symbol
;
17828 exp
.X_add_symbol
= fragp
->fr_symbol
;
17829 exp
.X_add_number
= fragp
->fr_offset
;
17831 fixp
= fix_new_exp (fragp
, buf
- fragp
->fr_literal
, 4, &exp
, TRUE
,
17832 BFD_RELOC_16_PCREL_S2
);
17833 fixp
->fx_file
= fragp
->fr_file
;
17834 fixp
->fx_line
= fragp
->fr_line
;
17836 buf
= write_insn (buf
, insn
);
17842 as_warn_where (fragp
->fr_file
, fragp
->fr_line
,
17843 _("Relaxed out-of-range branch into a jump"));
17845 if (RELAX_BRANCH_UNCOND (fragp
->fr_subtype
))
17848 if (!RELAX_BRANCH_LIKELY (fragp
->fr_subtype
))
17850 /* Reverse the branch. */
17851 switch ((insn
>> 28) & 0xf)
17854 /* bc[0-3][tf]l? and bc1any[24][ft] instructions can
17855 have the condition reversed by tweaking a single
17856 bit, and their opcodes all have 0x4???????. */
17857 gas_assert ((insn
& 0xf1000000) == 0x41000000);
17858 insn
^= 0x00010000;
17862 /* bltz 0x04000000 bgez 0x04010000
17863 bltzal 0x04100000 bgezal 0x04110000 */
17864 gas_assert ((insn
& 0xfc0e0000) == 0x04000000);
17865 insn
^= 0x00010000;
17869 /* beq 0x10000000 bne 0x14000000
17870 blez 0x18000000 bgtz 0x1c000000 */
17871 insn
^= 0x04000000;
17879 if (RELAX_BRANCH_LINK (fragp
->fr_subtype
))
17881 /* Clear the and-link bit. */
17882 gas_assert ((insn
& 0xfc1c0000) == 0x04100000);
17884 /* bltzal 0x04100000 bgezal 0x04110000
17885 bltzall 0x04120000 bgezall 0x04130000 */
17886 insn
&= ~0x00100000;
17889 /* Branch over the branch (if the branch was likely) or the
17890 full jump (not likely case). Compute the offset from the
17891 current instruction to branch to. */
17892 if (RELAX_BRANCH_LIKELY (fragp
->fr_subtype
))
17896 /* How many bytes in instructions we've already emitted? */
17897 i
= buf
- fragp
->fr_literal
- fragp
->fr_fix
;
17898 /* How many bytes in instructions from here to the end? */
17899 i
= fragp
->fr_var
- i
;
17901 /* Convert to instruction count. */
17903 /* Branch counts from the next instruction. */
17906 /* Branch over the jump. */
17907 buf
= write_insn (buf
, insn
);
17910 buf
= write_insn (buf
, 0);
17912 if (RELAX_BRANCH_LIKELY (fragp
->fr_subtype
))
17914 /* beql $0, $0, 2f */
17916 /* Compute the PC offset from the current instruction to
17917 the end of the variable frag. */
17918 /* How many bytes in instructions we've already emitted? */
17919 i
= buf
- fragp
->fr_literal
- fragp
->fr_fix
;
17920 /* How many bytes in instructions from here to the end? */
17921 i
= fragp
->fr_var
- i
;
17922 /* Convert to instruction count. */
17924 /* Don't decrement i, because we want to branch over the
17928 buf
= write_insn (buf
, insn
);
17929 buf
= write_insn (buf
, 0);
17933 if (mips_pic
== NO_PIC
)
17936 insn
= (RELAX_BRANCH_LINK (fragp
->fr_subtype
)
17937 ? 0x0c000000 : 0x08000000);
17938 exp
.X_op
= O_symbol
;
17939 exp
.X_add_symbol
= fragp
->fr_symbol
;
17940 exp
.X_add_number
= fragp
->fr_offset
;
17942 fixp
= fix_new_exp (fragp
, buf
- fragp
->fr_literal
, 4, &exp
,
17943 FALSE
, BFD_RELOC_MIPS_JMP
);
17944 fixp
->fx_file
= fragp
->fr_file
;
17945 fixp
->fx_line
= fragp
->fr_line
;
17947 buf
= write_insn (buf
, insn
);
17951 unsigned long at
= RELAX_BRANCH_AT (fragp
->fr_subtype
);
17953 /* lw/ld $at, <sym>($gp) R_MIPS_GOT16 */
17954 insn
= HAVE_64BIT_ADDRESSES
? 0xdf800000 : 0x8f800000;
17955 insn
|= at
<< OP_SH_RT
;
17956 exp
.X_op
= O_symbol
;
17957 exp
.X_add_symbol
= fragp
->fr_symbol
;
17958 exp
.X_add_number
= fragp
->fr_offset
;
17960 if (fragp
->fr_offset
)
17962 exp
.X_add_symbol
= make_expr_symbol (&exp
);
17963 exp
.X_add_number
= 0;
17966 fixp
= fix_new_exp (fragp
, buf
- fragp
->fr_literal
, 4, &exp
,
17967 FALSE
, BFD_RELOC_MIPS_GOT16
);
17968 fixp
->fx_file
= fragp
->fr_file
;
17969 fixp
->fx_line
= fragp
->fr_line
;
17971 buf
= write_insn (buf
, insn
);
17973 if (mips_opts
.isa
== ISA_MIPS1
)
17975 buf
= write_insn (buf
, 0);
17977 /* d/addiu $at, $at, <sym> R_MIPS_LO16 */
17978 insn
= HAVE_64BIT_ADDRESSES
? 0x64000000 : 0x24000000;
17979 insn
|= at
<< OP_SH_RS
| at
<< OP_SH_RT
;
17981 fixp
= fix_new_exp (fragp
, buf
- fragp
->fr_literal
, 4, &exp
,
17982 FALSE
, BFD_RELOC_LO16
);
17983 fixp
->fx_file
= fragp
->fr_file
;
17984 fixp
->fx_line
= fragp
->fr_line
;
17986 buf
= write_insn (buf
, insn
);
17989 if (RELAX_BRANCH_LINK (fragp
->fr_subtype
))
17993 insn
|= at
<< OP_SH_RS
;
17995 buf
= write_insn (buf
, insn
);
17999 fragp
->fr_fix
+= fragp
->fr_var
;
18000 gas_assert (buf
== fragp
->fr_literal
+ fragp
->fr_fix
);
18004 /* Relax microMIPS branches. */
18005 if (RELAX_MICROMIPS_P (fragp
->fr_subtype
))
18007 char *buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
18008 bfd_boolean compact
= RELAX_MICROMIPS_COMPACT (fragp
->fr_subtype
);
18009 bfd_boolean al
= RELAX_MICROMIPS_LINK (fragp
->fr_subtype
);
18010 int type
= RELAX_MICROMIPS_TYPE (fragp
->fr_subtype
);
18011 bfd_boolean short_ds
;
18012 unsigned long insn
;
18016 exp
.X_op
= O_symbol
;
18017 exp
.X_add_symbol
= fragp
->fr_symbol
;
18018 exp
.X_add_number
= fragp
->fr_offset
;
18020 fragp
->fr_fix
+= fragp
->fr_var
;
18022 /* Handle 16-bit branches that fit or are forced to fit. */
18023 if (type
!= 0 && !RELAX_MICROMIPS_TOOFAR16 (fragp
->fr_subtype
))
18025 /* We generate a fixup instead of applying it right now,
18026 because if there is linker relaxation, we're going to
18027 need the relocations. */
18029 fixp
= fix_new_exp (fragp
, buf
- fragp
->fr_literal
, 2, &exp
, TRUE
,
18030 BFD_RELOC_MICROMIPS_10_PCREL_S1
);
18031 else if (type
== 'E')
18032 fixp
= fix_new_exp (fragp
, buf
- fragp
->fr_literal
, 2, &exp
, TRUE
,
18033 BFD_RELOC_MICROMIPS_7_PCREL_S1
);
18037 fixp
->fx_file
= fragp
->fr_file
;
18038 fixp
->fx_line
= fragp
->fr_line
;
18040 /* These relocations can have an addend that won't fit in
18042 fixp
->fx_no_overflow
= 1;
18047 /* Handle 32-bit branches that fit or are forced to fit. */
18048 if (!RELAX_MICROMIPS_RELAX32 (fragp
->fr_subtype
)
18049 || !RELAX_MICROMIPS_TOOFAR32 (fragp
->fr_subtype
))
18051 /* We generate a fixup instead of applying it right now,
18052 because if there is linker relaxation, we're going to
18053 need the relocations. */
18054 fixp
= fix_new_exp (fragp
, buf
- fragp
->fr_literal
, 4, &exp
, TRUE
,
18055 BFD_RELOC_MICROMIPS_16_PCREL_S1
);
18056 fixp
->fx_file
= fragp
->fr_file
;
18057 fixp
->fx_line
= fragp
->fr_line
;
18063 /* Relax 16-bit branches to 32-bit branches. */
18066 insn
= read_compressed_insn (buf
, 2);
18068 if ((insn
& 0xfc00) == 0xcc00) /* b16 */
18069 insn
= 0x94000000; /* beq */
18070 else if ((insn
& 0xdc00) == 0x8c00) /* beqz16/bnez16 */
18072 unsigned long regno
;
18074 regno
= (insn
>> MICROMIPSOP_SH_MD
) & MICROMIPSOP_MASK_MD
;
18075 regno
= micromips_to_32_reg_d_map
[regno
];
18076 insn
= ((insn
& 0x2000) << 16) | 0x94000000; /* beq/bne */
18077 insn
|= regno
<< MICROMIPSOP_SH_RS
;
18082 /* Nothing else to do, just write it out. */
18083 if (!RELAX_MICROMIPS_RELAX32 (fragp
->fr_subtype
)
18084 || !RELAX_MICROMIPS_TOOFAR32 (fragp
->fr_subtype
))
18086 buf
= write_compressed_insn (buf
, insn
, 4);
18087 gas_assert (buf
== fragp
->fr_literal
+ fragp
->fr_fix
);
18092 insn
= read_compressed_insn (buf
, 4);
18094 /* Relax 32-bit branches to a sequence of instructions. */
18095 as_warn_where (fragp
->fr_file
, fragp
->fr_line
,
18096 _("Relaxed out-of-range branch into a jump"));
18098 /* Set the short-delay-slot bit. */
18099 short_ds
= al
&& (insn
& 0x02000000) != 0;
18101 if (!RELAX_MICROMIPS_UNCOND (fragp
->fr_subtype
))
18105 /* Reverse the branch. */
18106 if ((insn
& 0xfc000000) == 0x94000000 /* beq */
18107 || (insn
& 0xfc000000) == 0xb4000000) /* bne */
18108 insn
^= 0x20000000;
18109 else if ((insn
& 0xffe00000) == 0x40000000 /* bltz */
18110 || (insn
& 0xffe00000) == 0x40400000 /* bgez */
18111 || (insn
& 0xffe00000) == 0x40800000 /* blez */
18112 || (insn
& 0xffe00000) == 0x40c00000 /* bgtz */
18113 || (insn
& 0xffe00000) == 0x40a00000 /* bnezc */
18114 || (insn
& 0xffe00000) == 0x40e00000 /* beqzc */
18115 || (insn
& 0xffe00000) == 0x40200000 /* bltzal */
18116 || (insn
& 0xffe00000) == 0x40600000 /* bgezal */
18117 || (insn
& 0xffe00000) == 0x42200000 /* bltzals */
18118 || (insn
& 0xffe00000) == 0x42600000) /* bgezals */
18119 insn
^= 0x00400000;
18120 else if ((insn
& 0xffe30000) == 0x43800000 /* bc1f */
18121 || (insn
& 0xffe30000) == 0x43a00000 /* bc1t */
18122 || (insn
& 0xffe30000) == 0x42800000 /* bc2f */
18123 || (insn
& 0xffe30000) == 0x42a00000) /* bc2t */
18124 insn
^= 0x00200000;
18130 /* Clear the and-link and short-delay-slot bits. */
18131 gas_assert ((insn
& 0xfda00000) == 0x40200000);
18133 /* bltzal 0x40200000 bgezal 0x40600000 */
18134 /* bltzals 0x42200000 bgezals 0x42600000 */
18135 insn
&= ~0x02200000;
18138 /* Make a label at the end for use with the branch. */
18139 l
= symbol_new (micromips_label_name (), asec
, fragp
->fr_fix
, fragp
);
18140 micromips_label_inc ();
18141 #if defined(OBJ_ELF) || defined(OBJ_MAYBE_ELF)
18143 S_SET_OTHER (l
, ELF_ST_SET_MICROMIPS (S_GET_OTHER (l
)));
18147 fixp
= fix_new (fragp
, buf
- fragp
->fr_literal
, 4, l
, 0, TRUE
,
18148 BFD_RELOC_MICROMIPS_16_PCREL_S1
);
18149 fixp
->fx_file
= fragp
->fr_file
;
18150 fixp
->fx_line
= fragp
->fr_line
;
18152 /* Branch over the jump. */
18153 buf
= write_compressed_insn (buf
, insn
, 4);
18156 buf
= write_compressed_insn (buf
, 0x0c00, 2);
18159 if (mips_pic
== NO_PIC
)
18161 unsigned long jal
= short_ds
? 0x74000000 : 0xf4000000; /* jal/s */
18163 /* j/jal/jals <sym> R_MICROMIPS_26_S1 */
18164 insn
= al
? jal
: 0xd4000000;
18166 fixp
= fix_new_exp (fragp
, buf
- fragp
->fr_literal
, 4, &exp
, FALSE
,
18167 BFD_RELOC_MICROMIPS_JMP
);
18168 fixp
->fx_file
= fragp
->fr_file
;
18169 fixp
->fx_line
= fragp
->fr_line
;
18171 buf
= write_compressed_insn (buf
, insn
, 4);
18174 buf
= write_compressed_insn (buf
, 0x0c00, 2);
18178 unsigned long at
= RELAX_MICROMIPS_AT (fragp
->fr_subtype
);
18179 unsigned long jalr
= short_ds
? 0x45e0 : 0x45c0; /* jalr/s */
18180 unsigned long jr
= compact
? 0x45a0 : 0x4580; /* jr/c */
18182 /* lw/ld $at, <sym>($gp) R_MICROMIPS_GOT16 */
18183 insn
= HAVE_64BIT_ADDRESSES
? 0xdc1c0000 : 0xfc1c0000;
18184 insn
|= at
<< MICROMIPSOP_SH_RT
;
18186 if (exp
.X_add_number
)
18188 exp
.X_add_symbol
= make_expr_symbol (&exp
);
18189 exp
.X_add_number
= 0;
18192 fixp
= fix_new_exp (fragp
, buf
- fragp
->fr_literal
, 4, &exp
, FALSE
,
18193 BFD_RELOC_MICROMIPS_GOT16
);
18194 fixp
->fx_file
= fragp
->fr_file
;
18195 fixp
->fx_line
= fragp
->fr_line
;
18197 buf
= write_compressed_insn (buf
, insn
, 4);
18199 /* d/addiu $at, $at, <sym> R_MICROMIPS_LO16 */
18200 insn
= HAVE_64BIT_ADDRESSES
? 0x5c000000 : 0x30000000;
18201 insn
|= at
<< MICROMIPSOP_SH_RT
| at
<< MICROMIPSOP_SH_RS
;
18203 fixp
= fix_new_exp (fragp
, buf
- fragp
->fr_literal
, 4, &exp
, FALSE
,
18204 BFD_RELOC_MICROMIPS_LO16
);
18205 fixp
->fx_file
= fragp
->fr_file
;
18206 fixp
->fx_line
= fragp
->fr_line
;
18208 buf
= write_compressed_insn (buf
, insn
, 4);
18210 /* jr/jrc/jalr/jalrs $at */
18211 insn
= al
? jalr
: jr
;
18212 insn
|= at
<< MICROMIPSOP_SH_MJ
;
18214 buf
= write_compressed_insn (buf
, insn
, 2);
18217 gas_assert (buf
== fragp
->fr_literal
+ fragp
->fr_fix
);
18221 if (RELAX_MIPS16_P (fragp
->fr_subtype
))
18224 const struct mips16_immed_operand
*op
;
18227 unsigned int user_length
, length
;
18228 unsigned long insn
;
18231 type
= RELAX_MIPS16_TYPE (fragp
->fr_subtype
);
18232 op
= mips16_immed_operands
;
18233 while (op
->type
!= type
)
18236 ext
= RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
);
18237 val
= resolve_symbol_value (fragp
->fr_symbol
);
18242 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
18244 /* The rules for the base address of a PC relative reloc are
18245 complicated; see mips16_extended_frag. */
18246 if (type
== 'p' || type
== 'q')
18251 /* Ignore the low bit in the target, since it will be
18252 set for a text label. */
18253 if ((val
& 1) != 0)
18256 else if (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
))
18258 else if (RELAX_MIPS16_DSLOT (fragp
->fr_subtype
))
18261 addr
&= ~ (addressT
) ((1 << op
->shift
) - 1);
18264 /* Make sure the section winds up with the alignment we have
18267 record_alignment (asec
, op
->shift
);
18271 && (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
)
18272 || RELAX_MIPS16_DSLOT (fragp
->fr_subtype
)))
18273 as_warn_where (fragp
->fr_file
, fragp
->fr_line
,
18274 _("extended instruction in delay slot"));
18276 buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
18278 insn
= read_compressed_insn (buf
, 2);
18280 insn
|= MIPS16_EXTEND
;
18282 if (RELAX_MIPS16_USER_EXT (fragp
->fr_subtype
))
18284 else if (RELAX_MIPS16_USER_SMALL (fragp
->fr_subtype
))
18289 mips16_immed (fragp
->fr_file
, fragp
->fr_line
, type
,
18290 BFD_RELOC_UNUSED
, val
, user_length
, &insn
);
18292 length
= (ext
? 4 : 2);
18293 gas_assert (mips16_opcode_length (insn
) == length
);
18294 write_compressed_insn (buf
, insn
, length
);
18295 fragp
->fr_fix
+= length
;
18299 relax_substateT subtype
= fragp
->fr_subtype
;
18300 bfd_boolean second_longer
= (subtype
& RELAX_SECOND_LONGER
) != 0;
18301 bfd_boolean use_second
= (subtype
& RELAX_USE_SECOND
) != 0;
18305 first
= RELAX_FIRST (subtype
);
18306 second
= RELAX_SECOND (subtype
);
18307 fixp
= (fixS
*) fragp
->fr_opcode
;
18309 /* If the delay slot chosen does not match the size of the instruction,
18310 then emit a warning. */
18311 if ((!use_second
&& (subtype
& RELAX_DELAY_SLOT_SIZE_FIRST
) != 0)
18312 || (use_second
&& (subtype
& RELAX_DELAY_SLOT_SIZE_SECOND
) != 0))
18317 s
= subtype
& (RELAX_DELAY_SLOT_16BIT
18318 | RELAX_DELAY_SLOT_SIZE_FIRST
18319 | RELAX_DELAY_SLOT_SIZE_SECOND
);
18320 msg
= macro_warning (s
);
18322 as_warn_where (fragp
->fr_file
, fragp
->fr_line
, "%s", msg
);
18326 /* Possibly emit a warning if we've chosen the longer option. */
18327 if (use_second
== second_longer
)
18333 & (RELAX_SECOND_LONGER
| RELAX_NOMACRO
| RELAX_DELAY_SLOT
));
18334 msg
= macro_warning (s
);
18336 as_warn_where (fragp
->fr_file
, fragp
->fr_line
, "%s", msg
);
18340 /* Go through all the fixups for the first sequence. Disable them
18341 (by marking them as done) if we're going to use the second
18342 sequence instead. */
18344 && fixp
->fx_frag
== fragp
18345 && fixp
->fx_where
< fragp
->fr_fix
- second
)
18347 if (subtype
& RELAX_USE_SECOND
)
18349 fixp
= fixp
->fx_next
;
18352 /* Go through the fixups for the second sequence. Disable them if
18353 we're going to use the first sequence, otherwise adjust their
18354 addresses to account for the relaxation. */
18355 while (fixp
&& fixp
->fx_frag
== fragp
)
18357 if (subtype
& RELAX_USE_SECOND
)
18358 fixp
->fx_where
-= first
;
18361 fixp
= fixp
->fx_next
;
18364 /* Now modify the frag contents. */
18365 if (subtype
& RELAX_USE_SECOND
)
18369 start
= fragp
->fr_literal
+ fragp
->fr_fix
- first
- second
;
18370 memmove (start
, start
+ first
, second
);
18371 fragp
->fr_fix
-= first
;
18374 fragp
->fr_fix
-= second
;
18380 /* This function is called after the relocs have been generated.
18381 We've been storing mips16 text labels as odd. Here we convert them
18382 back to even for the convenience of the debugger. */
18385 mips_frob_file_after_relocs (void)
18388 unsigned int count
, i
;
18393 syms
= bfd_get_outsymbols (stdoutput
);
18394 count
= bfd_get_symcount (stdoutput
);
18395 for (i
= 0; i
< count
; i
++, syms
++)
18396 if (ELF_ST_IS_COMPRESSED (elf_symbol (*syms
)->internal_elf_sym
.st_other
)
18397 && ((*syms
)->value
& 1) != 0)
18399 (*syms
)->value
&= ~1;
18400 /* If the symbol has an odd size, it was probably computed
18401 incorrectly, so adjust that as well. */
18402 if ((elf_symbol (*syms
)->internal_elf_sym
.st_size
& 1) != 0)
18403 ++elf_symbol (*syms
)->internal_elf_sym
.st_size
;
18409 /* This function is called whenever a label is defined, including fake
18410 labels instantiated off the dot special symbol. It is used when
18411 handling branch delays; if a branch has a label, we assume we cannot
18412 move it. This also bumps the value of the symbol by 1 in compressed
18416 mips_record_label (symbolS
*sym
)
18418 segment_info_type
*si
= seg_info (now_seg
);
18419 struct insn_label_list
*l
;
18421 if (free_insn_labels
== NULL
)
18422 l
= (struct insn_label_list
*) xmalloc (sizeof *l
);
18425 l
= free_insn_labels
;
18426 free_insn_labels
= l
->next
;
18430 l
->next
= si
->label_list
;
18431 si
->label_list
= l
;
18434 /* This function is called as tc_frob_label() whenever a label is defined
18435 and adds a DWARF-2 record we only want for true labels. */
18438 mips_define_label (symbolS
*sym
)
18440 mips_record_label (sym
);
18442 dwarf2_emit_label (sym
);
18446 /* This function is called by tc_new_dot_label whenever a new dot symbol
18450 mips_add_dot_label (symbolS
*sym
)
18452 mips_record_label (sym
);
18453 if (mips_assembling_insn
&& HAVE_CODE_COMPRESSION
)
18454 mips_compressed_mark_label (sym
);
18457 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
18459 /* Some special processing for a MIPS ELF file. */
18462 mips_elf_final_processing (void)
18464 /* Write out the register information. */
18465 if (mips_abi
!= N64_ABI
)
18469 s
.ri_gprmask
= mips_gprmask
;
18470 s
.ri_cprmask
[0] = mips_cprmask
[0];
18471 s
.ri_cprmask
[1] = mips_cprmask
[1];
18472 s
.ri_cprmask
[2] = mips_cprmask
[2];
18473 s
.ri_cprmask
[3] = mips_cprmask
[3];
18474 /* The gp_value field is set by the MIPS ELF backend. */
18476 bfd_mips_elf32_swap_reginfo_out (stdoutput
, &s
,
18477 ((Elf32_External_RegInfo
*)
18478 mips_regmask_frag
));
18482 Elf64_Internal_RegInfo s
;
18484 s
.ri_gprmask
= mips_gprmask
;
18486 s
.ri_cprmask
[0] = mips_cprmask
[0];
18487 s
.ri_cprmask
[1] = mips_cprmask
[1];
18488 s
.ri_cprmask
[2] = mips_cprmask
[2];
18489 s
.ri_cprmask
[3] = mips_cprmask
[3];
18490 /* The gp_value field is set by the MIPS ELF backend. */
18492 bfd_mips_elf64_swap_reginfo_out (stdoutput
, &s
,
18493 ((Elf64_External_RegInfo
*)
18494 mips_regmask_frag
));
18497 /* Set the MIPS ELF flag bits. FIXME: There should probably be some
18498 sort of BFD interface for this. */
18499 if (mips_any_noreorder
)
18500 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_NOREORDER
;
18501 if (mips_pic
!= NO_PIC
)
18503 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_PIC
;
18504 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_CPIC
;
18507 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_CPIC
;
18509 /* Set MIPS ELF flags for ASEs. */
18510 /* We may need to define a new flag for DSP ASE, and set this flag when
18511 file_ase_dsp is true. */
18512 /* Same for DSP R2. */
18513 /* We may need to define a new flag for MT ASE, and set this flag when
18514 file_ase_mt is true. */
18515 if (file_ase_mips16
)
18516 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ARCH_ASE_M16
;
18517 if (file_ase_micromips
)
18518 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ARCH_ASE_MICROMIPS
;
18519 #if 0 /* XXX FIXME */
18520 if (file_ase_mips3d
)
18521 elf_elfheader (stdoutput
)->e_flags
|= ???;
18524 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ARCH_ASE_MDMX
;
18526 /* Set the MIPS ELF ABI flags. */
18527 if (mips_abi
== O32_ABI
&& USE_E_MIPS_ABI_O32
)
18528 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_O32
;
18529 else if (mips_abi
== O64_ABI
)
18530 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_O64
;
18531 else if (mips_abi
== EABI_ABI
)
18533 if (!file_mips_gp32
)
18534 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_EABI64
;
18536 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_EABI32
;
18538 else if (mips_abi
== N32_ABI
)
18539 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ABI2
;
18541 /* Nothing to do for N64_ABI. */
18543 if (mips_32bitmode
)
18544 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_32BITMODE
;
18546 #if 0 /* XXX FIXME */
18547 /* 32 bit code with 64 bit FP registers. */
18548 if (!file_mips_fp32
&& ABI_NEEDS_32BIT_REGS (mips_abi
))
18549 elf_elfheader (stdoutput
)->e_flags
|= ???;
18553 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */
18555 typedef struct proc
{
18557 symbolS
*func_end_sym
;
18558 unsigned long reg_mask
;
18559 unsigned long reg_offset
;
18560 unsigned long fpreg_mask
;
18561 unsigned long fpreg_offset
;
18562 unsigned long frame_offset
;
18563 unsigned long frame_reg
;
18564 unsigned long pc_reg
;
18567 static procS cur_proc
;
18568 static procS
*cur_proc_ptr
;
18569 static int numprocs
;
18571 /* Implement NOP_OPCODE. We encode a MIPS16 nop as "1", a microMIPS nop
18572 as "2", and a normal nop as "0". */
18574 #define NOP_OPCODE_MIPS 0
18575 #define NOP_OPCODE_MIPS16 1
18576 #define NOP_OPCODE_MICROMIPS 2
18579 mips_nop_opcode (void)
18581 if (seg_info (now_seg
)->tc_segment_info_data
.micromips
)
18582 return NOP_OPCODE_MICROMIPS
;
18583 else if (seg_info (now_seg
)->tc_segment_info_data
.mips16
)
18584 return NOP_OPCODE_MIPS16
;
18586 return NOP_OPCODE_MIPS
;
18589 /* Fill in an rs_align_code fragment. Unlike elsewhere we want to use
18590 32-bit microMIPS NOPs here (if applicable). */
18593 mips_handle_align (fragS
*fragp
)
18597 int bytes
, size
, excess
;
18600 if (fragp
->fr_type
!= rs_align_code
)
18603 p
= fragp
->fr_literal
+ fragp
->fr_fix
;
18605 switch (nop_opcode
)
18607 case NOP_OPCODE_MICROMIPS
:
18608 opcode
= micromips_nop32_insn
.insn_opcode
;
18611 case NOP_OPCODE_MIPS16
:
18612 opcode
= mips16_nop_insn
.insn_opcode
;
18615 case NOP_OPCODE_MIPS
:
18617 opcode
= nop_insn
.insn_opcode
;
18622 bytes
= fragp
->fr_next
->fr_address
- fragp
->fr_address
- fragp
->fr_fix
;
18623 excess
= bytes
% size
;
18625 /* Handle the leading part if we're not inserting a whole number of
18626 instructions, and make it the end of the fixed part of the frag.
18627 Try to fit in a short microMIPS NOP if applicable and possible,
18628 and use zeroes otherwise. */
18629 gas_assert (excess
< 4);
18630 fragp
->fr_fix
+= excess
;
18635 /* Fall through. */
18637 if (nop_opcode
== NOP_OPCODE_MICROMIPS
)
18639 p
= write_compressed_insn (p
, micromips_nop16_insn
.insn_opcode
, 2);
18643 /* Fall through. */
18646 /* Fall through. */
18651 md_number_to_chars (p
, opcode
, size
);
18652 fragp
->fr_var
= size
;
18656 md_obj_begin (void)
18663 /* Check for premature end, nesting errors, etc. */
18665 as_warn (_("missing .end at end of assembly"));
18674 if (*input_line_pointer
== '-')
18676 ++input_line_pointer
;
18679 if (!ISDIGIT (*input_line_pointer
))
18680 as_bad (_("expected simple number"));
18681 if (input_line_pointer
[0] == '0')
18683 if (input_line_pointer
[1] == 'x')
18685 input_line_pointer
+= 2;
18686 while (ISXDIGIT (*input_line_pointer
))
18689 val
|= hex_value (*input_line_pointer
++);
18691 return negative
? -val
: val
;
18695 ++input_line_pointer
;
18696 while (ISDIGIT (*input_line_pointer
))
18699 val
|= *input_line_pointer
++ - '0';
18701 return negative
? -val
: val
;
18704 if (!ISDIGIT (*input_line_pointer
))
18706 printf (_(" *input_line_pointer == '%c' 0x%02x\n"),
18707 *input_line_pointer
, *input_line_pointer
);
18708 as_warn (_("invalid number"));
18711 while (ISDIGIT (*input_line_pointer
))
18714 val
+= *input_line_pointer
++ - '0';
18716 return negative
? -val
: val
;
18719 /* The .file directive; just like the usual .file directive, but there
18720 is an initial number which is the ECOFF file index. In the non-ECOFF
18721 case .file implies DWARF-2. */
18724 s_mips_file (int x ATTRIBUTE_UNUSED
)
18726 static int first_file_directive
= 0;
18728 if (ECOFF_DEBUGGING
)
18737 filename
= dwarf2_directive_file (0);
18739 /* Versions of GCC up to 3.1 start files with a ".file"
18740 directive even for stabs output. Make sure that this
18741 ".file" is handled. Note that you need a version of GCC
18742 after 3.1 in order to support DWARF-2 on MIPS. */
18743 if (filename
!= NULL
&& ! first_file_directive
)
18745 (void) new_logical_line (filename
, -1);
18746 s_app_file_string (filename
, 0);
18748 first_file_directive
= 1;
18752 /* The .loc directive, implying DWARF-2. */
18755 s_mips_loc (int x ATTRIBUTE_UNUSED
)
18757 if (!ECOFF_DEBUGGING
)
18758 dwarf2_directive_loc (0);
18761 /* The .end directive. */
18764 s_mips_end (int x ATTRIBUTE_UNUSED
)
18768 /* Following functions need their own .frame and .cprestore directives. */
18769 mips_frame_reg_valid
= 0;
18770 mips_cprestore_valid
= 0;
18772 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
18775 demand_empty_rest_of_line ();
18780 if ((bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) == 0)
18781 as_warn (_(".end not in text section"));
18785 as_warn (_(".end directive without a preceding .ent directive."));
18786 demand_empty_rest_of_line ();
18792 gas_assert (S_GET_NAME (p
));
18793 if (strcmp (S_GET_NAME (p
), S_GET_NAME (cur_proc_ptr
->func_sym
)))
18794 as_warn (_(".end symbol does not match .ent symbol."));
18796 if (debug_type
== DEBUG_STABS
)
18797 stabs_generate_asm_endfunc (S_GET_NAME (p
),
18801 as_warn (_(".end directive missing or unknown symbol"));
18804 /* Create an expression to calculate the size of the function. */
18805 if (p
&& cur_proc_ptr
)
18807 OBJ_SYMFIELD_TYPE
*obj
= symbol_get_obj (p
);
18808 expressionS
*exp
= xmalloc (sizeof (expressionS
));
18811 exp
->X_op
= O_subtract
;
18812 exp
->X_add_symbol
= symbol_temp_new_now ();
18813 exp
->X_op_symbol
= p
;
18814 exp
->X_add_number
= 0;
18816 cur_proc_ptr
->func_end_sym
= exp
->X_add_symbol
;
18819 /* Generate a .pdr section. */
18820 if (IS_ELF
&& !ECOFF_DEBUGGING
&& mips_flag_pdr
)
18822 segT saved_seg
= now_seg
;
18823 subsegT saved_subseg
= now_subseg
;
18827 #ifdef md_flush_pending_output
18828 md_flush_pending_output ();
18831 gas_assert (pdr_seg
);
18832 subseg_set (pdr_seg
, 0);
18834 /* Write the symbol. */
18835 exp
.X_op
= O_symbol
;
18836 exp
.X_add_symbol
= p
;
18837 exp
.X_add_number
= 0;
18838 emit_expr (&exp
, 4);
18840 fragp
= frag_more (7 * 4);
18842 md_number_to_chars (fragp
, cur_proc_ptr
->reg_mask
, 4);
18843 md_number_to_chars (fragp
+ 4, cur_proc_ptr
->reg_offset
, 4);
18844 md_number_to_chars (fragp
+ 8, cur_proc_ptr
->fpreg_mask
, 4);
18845 md_number_to_chars (fragp
+ 12, cur_proc_ptr
->fpreg_offset
, 4);
18846 md_number_to_chars (fragp
+ 16, cur_proc_ptr
->frame_offset
, 4);
18847 md_number_to_chars (fragp
+ 20, cur_proc_ptr
->frame_reg
, 4);
18848 md_number_to_chars (fragp
+ 24, cur_proc_ptr
->pc_reg
, 4);
18850 subseg_set (saved_seg
, saved_subseg
);
18852 #endif /* OBJ_ELF */
18854 cur_proc_ptr
= NULL
;
18857 /* The .aent and .ent directives. */
18860 s_mips_ent (int aent
)
18864 symbolP
= get_symbol ();
18865 if (*input_line_pointer
== ',')
18866 ++input_line_pointer
;
18867 SKIP_WHITESPACE ();
18868 if (ISDIGIT (*input_line_pointer
)
18869 || *input_line_pointer
== '-')
18872 if ((bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) == 0)
18873 as_warn (_(".ent or .aent not in text section."));
18875 if (!aent
&& cur_proc_ptr
)
18876 as_warn (_("missing .end"));
18880 /* This function needs its own .frame and .cprestore directives. */
18881 mips_frame_reg_valid
= 0;
18882 mips_cprestore_valid
= 0;
18884 cur_proc_ptr
= &cur_proc
;
18885 memset (cur_proc_ptr
, '\0', sizeof (procS
));
18887 cur_proc_ptr
->func_sym
= symbolP
;
18891 if (debug_type
== DEBUG_STABS
)
18892 stabs_generate_asm_func (S_GET_NAME (symbolP
),
18893 S_GET_NAME (symbolP
));
18896 symbol_get_bfdsym (symbolP
)->flags
|= BSF_FUNCTION
;
18898 demand_empty_rest_of_line ();
18901 /* The .frame directive. If the mdebug section is present (IRIX 5 native)
18902 then ecoff.c (ecoff_directive_frame) is used. For embedded targets,
18903 s_mips_frame is used so that we can set the PDR information correctly.
18904 We can't use the ecoff routines because they make reference to the ecoff
18905 symbol table (in the mdebug section). */
18908 s_mips_frame (int ignore ATTRIBUTE_UNUSED
)
18911 if (IS_ELF
&& !ECOFF_DEBUGGING
)
18915 if (cur_proc_ptr
== (procS
*) NULL
)
18917 as_warn (_(".frame outside of .ent"));
18918 demand_empty_rest_of_line ();
18922 cur_proc_ptr
->frame_reg
= tc_get_register (1);
18924 SKIP_WHITESPACE ();
18925 if (*input_line_pointer
++ != ','
18926 || get_absolute_expression_and_terminator (&val
) != ',')
18928 as_warn (_("Bad .frame directive"));
18929 --input_line_pointer
;
18930 demand_empty_rest_of_line ();
18934 cur_proc_ptr
->frame_offset
= val
;
18935 cur_proc_ptr
->pc_reg
= tc_get_register (0);
18937 demand_empty_rest_of_line ();
18940 #endif /* OBJ_ELF */
18944 /* The .fmask and .mask directives. If the mdebug section is present
18945 (IRIX 5 native) then ecoff.c (ecoff_directive_mask) is used. For
18946 embedded targets, s_mips_mask is used so that we can set the PDR
18947 information correctly. We can't use the ecoff routines because they
18948 make reference to the ecoff symbol table (in the mdebug section). */
18951 s_mips_mask (int reg_type
)
18954 if (IS_ELF
&& !ECOFF_DEBUGGING
)
18958 if (cur_proc_ptr
== (procS
*) NULL
)
18960 as_warn (_(".mask/.fmask outside of .ent"));
18961 demand_empty_rest_of_line ();
18965 if (get_absolute_expression_and_terminator (&mask
) != ',')
18967 as_warn (_("Bad .mask/.fmask directive"));
18968 --input_line_pointer
;
18969 demand_empty_rest_of_line ();
18973 off
= get_absolute_expression ();
18975 if (reg_type
== 'F')
18977 cur_proc_ptr
->fpreg_mask
= mask
;
18978 cur_proc_ptr
->fpreg_offset
= off
;
18982 cur_proc_ptr
->reg_mask
= mask
;
18983 cur_proc_ptr
->reg_offset
= off
;
18986 demand_empty_rest_of_line ();
18989 #endif /* OBJ_ELF */
18990 s_ignore (reg_type
);
18993 /* A table describing all the processors gas knows about. Names are
18994 matched in the order listed.
18996 To ease comparison, please keep this table in the same order as
18997 gcc's mips_cpu_info_table[]. */
18998 static const struct mips_cpu_info mips_cpu_info_table
[] =
19000 /* Entries for generic ISAs */
19001 { "mips1", MIPS_CPU_IS_ISA
, ISA_MIPS1
, CPU_R3000
},
19002 { "mips2", MIPS_CPU_IS_ISA
, ISA_MIPS2
, CPU_R6000
},
19003 { "mips3", MIPS_CPU_IS_ISA
, ISA_MIPS3
, CPU_R4000
},
19004 { "mips4", MIPS_CPU_IS_ISA
, ISA_MIPS4
, CPU_R8000
},
19005 { "mips5", MIPS_CPU_IS_ISA
, ISA_MIPS5
, CPU_MIPS5
},
19006 { "mips32", MIPS_CPU_IS_ISA
, ISA_MIPS32
, CPU_MIPS32
},
19007 { "mips32r2", MIPS_CPU_IS_ISA
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19008 { "mips64", MIPS_CPU_IS_ISA
, ISA_MIPS64
, CPU_MIPS64
},
19009 { "mips64r2", MIPS_CPU_IS_ISA
, ISA_MIPS64R2
, CPU_MIPS64R2
},
19012 { "r3000", 0, ISA_MIPS1
, CPU_R3000
},
19013 { "r2000", 0, ISA_MIPS1
, CPU_R3000
},
19014 { "r3900", 0, ISA_MIPS1
, CPU_R3900
},
19017 { "r6000", 0, ISA_MIPS2
, CPU_R6000
},
19020 { "r4000", 0, ISA_MIPS3
, CPU_R4000
},
19021 { "r4010", 0, ISA_MIPS2
, CPU_R4010
},
19022 { "vr4100", 0, ISA_MIPS3
, CPU_VR4100
},
19023 { "vr4111", 0, ISA_MIPS3
, CPU_R4111
},
19024 { "vr4120", 0, ISA_MIPS3
, CPU_VR4120
},
19025 { "vr4130", 0, ISA_MIPS3
, CPU_VR4120
},
19026 { "vr4181", 0, ISA_MIPS3
, CPU_R4111
},
19027 { "vr4300", 0, ISA_MIPS3
, CPU_R4300
},
19028 { "r4400", 0, ISA_MIPS3
, CPU_R4400
},
19029 { "r4600", 0, ISA_MIPS3
, CPU_R4600
},
19030 { "orion", 0, ISA_MIPS3
, CPU_R4600
},
19031 { "r4650", 0, ISA_MIPS3
, CPU_R4650
},
19032 /* ST Microelectronics Loongson 2E and 2F cores */
19033 { "loongson2e", 0, ISA_MIPS3
, CPU_LOONGSON_2E
},
19034 { "loongson2f", 0, ISA_MIPS3
, CPU_LOONGSON_2F
},
19037 { "r8000", 0, ISA_MIPS4
, CPU_R8000
},
19038 { "r10000", 0, ISA_MIPS4
, CPU_R10000
},
19039 { "r12000", 0, ISA_MIPS4
, CPU_R12000
},
19040 { "r14000", 0, ISA_MIPS4
, CPU_R14000
},
19041 { "r16000", 0, ISA_MIPS4
, CPU_R16000
},
19042 { "vr5000", 0, ISA_MIPS4
, CPU_R5000
},
19043 { "vr5400", 0, ISA_MIPS4
, CPU_VR5400
},
19044 { "vr5500", 0, ISA_MIPS4
, CPU_VR5500
},
19045 { "rm5200", 0, ISA_MIPS4
, CPU_R5000
},
19046 { "rm5230", 0, ISA_MIPS4
, CPU_R5000
},
19047 { "rm5231", 0, ISA_MIPS4
, CPU_R5000
},
19048 { "rm5261", 0, ISA_MIPS4
, CPU_R5000
},
19049 { "rm5721", 0, ISA_MIPS4
, CPU_R5000
},
19050 { "rm7000", 0, ISA_MIPS4
, CPU_RM7000
},
19051 { "rm9000", 0, ISA_MIPS4
, CPU_RM9000
},
19054 { "4kc", 0, ISA_MIPS32
, CPU_MIPS32
},
19055 { "4km", 0, ISA_MIPS32
, CPU_MIPS32
},
19056 { "4kp", 0, ISA_MIPS32
, CPU_MIPS32
},
19057 { "4ksc", MIPS_CPU_ASE_SMARTMIPS
, ISA_MIPS32
, CPU_MIPS32
},
19059 /* MIPS 32 Release 2 */
19060 { "4kec", 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
19061 { "4kem", 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
19062 { "4kep", 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
19063 { "4ksd", MIPS_CPU_ASE_SMARTMIPS
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19064 { "m4k", 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
19065 { "m4kp", 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
19066 { "m14k", MIPS_CPU_ASE_MCU
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19067 { "m14kc", MIPS_CPU_ASE_MCU
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19068 { "m14ke", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_DSPR2
| MIPS_CPU_ASE_MCU
,
19069 ISA_MIPS32R2
, CPU_MIPS32R2
},
19070 { "m14kec", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_DSPR2
| MIPS_CPU_ASE_MCU
,
19071 ISA_MIPS32R2
, CPU_MIPS32R2
},
19072 { "24kc", 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
19073 { "24kf2_1", 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
19074 { "24kf", 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
19075 { "24kf1_1", 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
19076 /* Deprecated forms of the above. */
19077 { "24kfx", 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
19078 { "24kx", 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
19079 /* 24KE is a 24K with DSP ASE, other ASEs are optional. */
19080 { "24kec", MIPS_CPU_ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19081 { "24kef2_1", MIPS_CPU_ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19082 { "24kef", MIPS_CPU_ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19083 { "24kef1_1", MIPS_CPU_ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19084 /* Deprecated forms of the above. */
19085 { "24kefx", MIPS_CPU_ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19086 { "24kex", MIPS_CPU_ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19087 /* 34K is a 24K with DSP and MT ASE, other ASEs are optional. */
19088 { "34kc", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_MT
,
19089 ISA_MIPS32R2
, CPU_MIPS32R2
},
19090 { "34kf2_1", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_MT
,
19091 ISA_MIPS32R2
, CPU_MIPS32R2
},
19092 { "34kf", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_MT
,
19093 ISA_MIPS32R2
, CPU_MIPS32R2
},
19094 { "34kf1_1", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_MT
,
19095 ISA_MIPS32R2
, CPU_MIPS32R2
},
19096 /* Deprecated forms of the above. */
19097 { "34kfx", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_MT
,
19098 ISA_MIPS32R2
, CPU_MIPS32R2
},
19099 { "34kx", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_MT
,
19100 ISA_MIPS32R2
, CPU_MIPS32R2
},
19101 /* 34Kn is a 34kc without DSP. */
19102 { "34kn", MIPS_CPU_ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19103 /* 74K with DSP and DSPR2 ASE, other ASEs are optional. */
19104 { "74kc", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_DSPR2
,
19105 ISA_MIPS32R2
, CPU_MIPS32R2
},
19106 { "74kf2_1", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_DSPR2
,
19107 ISA_MIPS32R2
, CPU_MIPS32R2
},
19108 { "74kf", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_DSPR2
,
19109 ISA_MIPS32R2
, CPU_MIPS32R2
},
19110 { "74kf1_1", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_DSPR2
,
19111 ISA_MIPS32R2
, CPU_MIPS32R2
},
19112 { "74kf3_2", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_DSPR2
,
19113 ISA_MIPS32R2
, CPU_MIPS32R2
},
19114 /* Deprecated forms of the above. */
19115 { "74kfx", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_DSPR2
,
19116 ISA_MIPS32R2
, CPU_MIPS32R2
},
19117 { "74kx", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_DSPR2
,
19118 ISA_MIPS32R2
, CPU_MIPS32R2
},
19119 /* 1004K cores are multiprocessor versions of the 34K. */
19120 { "1004kc", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_MT
,
19121 ISA_MIPS32R2
, CPU_MIPS32R2
},
19122 { "1004kf2_1", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_MT
,
19123 ISA_MIPS32R2
, CPU_MIPS32R2
},
19124 { "1004kf", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_MT
,
19125 ISA_MIPS32R2
, CPU_MIPS32R2
},
19126 { "1004kf1_1", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_MT
,
19127 ISA_MIPS32R2
, CPU_MIPS32R2
},
19130 { "5kc", 0, ISA_MIPS64
, CPU_MIPS64
},
19131 { "5kf", 0, ISA_MIPS64
, CPU_MIPS64
},
19132 { "20kc", MIPS_CPU_ASE_MIPS3D
, ISA_MIPS64
, CPU_MIPS64
},
19133 { "25kf", MIPS_CPU_ASE_MIPS3D
, ISA_MIPS64
, CPU_MIPS64
},
19135 /* Broadcom SB-1 CPU core */
19136 { "sb1", MIPS_CPU_ASE_MIPS3D
| MIPS_CPU_ASE_MDMX
,
19137 ISA_MIPS64
, CPU_SB1
},
19138 /* Broadcom SB-1A CPU core */
19139 { "sb1a", MIPS_CPU_ASE_MIPS3D
| MIPS_CPU_ASE_MDMX
,
19140 ISA_MIPS64
, CPU_SB1
},
19142 { "loongson3a", 0, ISA_MIPS64
, CPU_LOONGSON_3A
},
19144 /* MIPS 64 Release 2 */
19146 /* Cavium Networks Octeon CPU core */
19147 { "octeon", 0, ISA_MIPS64R2
, CPU_OCTEON
},
19148 { "octeon+", 0, ISA_MIPS64R2
, CPU_OCTEONP
},
19149 { "octeon2", 0, ISA_MIPS64R2
, CPU_OCTEON2
},
19152 { "xlr", 0, ISA_MIPS64
, CPU_XLR
},
19155 XLP is mostly like XLR, with the prominent exception that it is
19156 MIPS64R2 rather than MIPS64. */
19157 { "xlp", 0, ISA_MIPS64R2
, CPU_XLR
},
19164 /* Return true if GIVEN is the same as CANONICAL, or if it is CANONICAL
19165 with a final "000" replaced by "k". Ignore case.
19167 Note: this function is shared between GCC and GAS. */
19170 mips_strict_matching_cpu_name_p (const char *canonical
, const char *given
)
19172 while (*given
!= 0 && TOLOWER (*given
) == TOLOWER (*canonical
))
19173 given
++, canonical
++;
19175 return ((*given
== 0 && *canonical
== 0)
19176 || (strcmp (canonical
, "000") == 0 && strcasecmp (given
, "k") == 0));
19180 /* Return true if GIVEN matches CANONICAL, where GIVEN is a user-supplied
19181 CPU name. We've traditionally allowed a lot of variation here.
19183 Note: this function is shared between GCC and GAS. */
19186 mips_matching_cpu_name_p (const char *canonical
, const char *given
)
19188 /* First see if the name matches exactly, or with a final "000"
19189 turned into "k". */
19190 if (mips_strict_matching_cpu_name_p (canonical
, given
))
19193 /* If not, try comparing based on numerical designation alone.
19194 See if GIVEN is an unadorned number, or 'r' followed by a number. */
19195 if (TOLOWER (*given
) == 'r')
19197 if (!ISDIGIT (*given
))
19200 /* Skip over some well-known prefixes in the canonical name,
19201 hoping to find a number there too. */
19202 if (TOLOWER (canonical
[0]) == 'v' && TOLOWER (canonical
[1]) == 'r')
19204 else if (TOLOWER (canonical
[0]) == 'r' && TOLOWER (canonical
[1]) == 'm')
19206 else if (TOLOWER (canonical
[0]) == 'r')
19209 return mips_strict_matching_cpu_name_p (canonical
, given
);
19213 /* Parse an option that takes the name of a processor as its argument.
19214 OPTION is the name of the option and CPU_STRING is the argument.
19215 Return the corresponding processor enumeration if the CPU_STRING is
19216 recognized, otherwise report an error and return null.
19218 A similar function exists in GCC. */
19220 static const struct mips_cpu_info
*
19221 mips_parse_cpu (const char *option
, const char *cpu_string
)
19223 const struct mips_cpu_info
*p
;
19225 /* 'from-abi' selects the most compatible architecture for the given
19226 ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit ABIs. For the
19227 EABIs, we have to decide whether we're using the 32-bit or 64-bit
19228 version. Look first at the -mgp options, if given, otherwise base
19229 the choice on MIPS_DEFAULT_64BIT.
19231 Treat NO_ABI like the EABIs. One reason to do this is that the
19232 plain 'mips' and 'mips64' configs have 'from-abi' as their default
19233 architecture. This code picks MIPS I for 'mips' and MIPS III for
19234 'mips64', just as we did in the days before 'from-abi'. */
19235 if (strcasecmp (cpu_string
, "from-abi") == 0)
19237 if (ABI_NEEDS_32BIT_REGS (mips_abi
))
19238 return mips_cpu_info_from_isa (ISA_MIPS1
);
19240 if (ABI_NEEDS_64BIT_REGS (mips_abi
))
19241 return mips_cpu_info_from_isa (ISA_MIPS3
);
19243 if (file_mips_gp32
>= 0)
19244 return mips_cpu_info_from_isa (file_mips_gp32
? ISA_MIPS1
: ISA_MIPS3
);
19246 return mips_cpu_info_from_isa (MIPS_DEFAULT_64BIT
19251 /* 'default' has traditionally been a no-op. Probably not very useful. */
19252 if (strcasecmp (cpu_string
, "default") == 0)
19255 for (p
= mips_cpu_info_table
; p
->name
!= 0; p
++)
19256 if (mips_matching_cpu_name_p (p
->name
, cpu_string
))
19259 as_bad (_("Bad value (%s) for %s"), cpu_string
, option
);
19263 /* Return the canonical processor information for ISA (a member of the
19264 ISA_MIPS* enumeration). */
19266 static const struct mips_cpu_info
*
19267 mips_cpu_info_from_isa (int isa
)
19271 for (i
= 0; mips_cpu_info_table
[i
].name
!= NULL
; i
++)
19272 if ((mips_cpu_info_table
[i
].flags
& MIPS_CPU_IS_ISA
)
19273 && isa
== mips_cpu_info_table
[i
].isa
)
19274 return (&mips_cpu_info_table
[i
]);
19279 static const struct mips_cpu_info
*
19280 mips_cpu_info_from_arch (int arch
)
19284 for (i
= 0; mips_cpu_info_table
[i
].name
!= NULL
; i
++)
19285 if (arch
== mips_cpu_info_table
[i
].cpu
)
19286 return (&mips_cpu_info_table
[i
]);
19292 show (FILE *stream
, const char *string
, int *col_p
, int *first_p
)
19296 fprintf (stream
, "%24s", "");
19301 fprintf (stream
, ", ");
19305 if (*col_p
+ strlen (string
) > 72)
19307 fprintf (stream
, "\n%24s", "");
19311 fprintf (stream
, "%s", string
);
19312 *col_p
+= strlen (string
);
19318 md_show_usage (FILE *stream
)
19323 fprintf (stream
, _("\
19325 -EB generate big endian output\n\
19326 -EL generate little endian output\n\
19327 -g, -g2 do not remove unneeded NOPs or swap branches\n\
19328 -G NUM allow referencing objects up to NUM bytes\n\
19329 implicitly with the gp register [default 8]\n"));
19330 fprintf (stream
, _("\
19331 -mips1 generate MIPS ISA I instructions\n\
19332 -mips2 generate MIPS ISA II instructions\n\
19333 -mips3 generate MIPS ISA III instructions\n\
19334 -mips4 generate MIPS ISA IV instructions\n\
19335 -mips5 generate MIPS ISA V instructions\n\
19336 -mips32 generate MIPS32 ISA instructions\n\
19337 -mips32r2 generate MIPS32 release 2 ISA instructions\n\
19338 -mips64 generate MIPS64 ISA instructions\n\
19339 -mips64r2 generate MIPS64 release 2 ISA instructions\n\
19340 -march=CPU/-mtune=CPU generate code/schedule for CPU, where CPU is one of:\n"));
19344 for (i
= 0; mips_cpu_info_table
[i
].name
!= NULL
; i
++)
19345 show (stream
, mips_cpu_info_table
[i
].name
, &column
, &first
);
19346 show (stream
, "from-abi", &column
, &first
);
19347 fputc ('\n', stream
);
19349 fprintf (stream
, _("\
19350 -mCPU equivalent to -march=CPU -mtune=CPU. Deprecated.\n\
19351 -no-mCPU don't generate code specific to CPU.\n\
19352 For -mCPU and -no-mCPU, CPU must be one of:\n"));
19356 show (stream
, "3900", &column
, &first
);
19357 show (stream
, "4010", &column
, &first
);
19358 show (stream
, "4100", &column
, &first
);
19359 show (stream
, "4650", &column
, &first
);
19360 fputc ('\n', stream
);
19362 fprintf (stream
, _("\
19363 -mips16 generate mips16 instructions\n\
19364 -no-mips16 do not generate mips16 instructions\n"));
19365 fprintf (stream
, _("\
19366 -mmicromips generate microMIPS instructions\n\
19367 -mno-micromips do not generate microMIPS instructions\n"));
19368 fprintf (stream
, _("\
19369 -msmartmips generate smartmips instructions\n\
19370 -mno-smartmips do not generate smartmips instructions\n"));
19371 fprintf (stream
, _("\
19372 -mdsp generate DSP instructions\n\
19373 -mno-dsp do not generate DSP instructions\n"));
19374 fprintf (stream
, _("\
19375 -mdspr2 generate DSP R2 instructions\n\
19376 -mno-dspr2 do not generate DSP R2 instructions\n"));
19377 fprintf (stream
, _("\
19378 -mmt generate MT instructions\n\
19379 -mno-mt do not generate MT instructions\n"));
19380 fprintf (stream
, _("\
19381 -mmcu generate MCU instructions\n\
19382 -mno-mcu do not generate MCU instructions\n"));
19383 fprintf (stream
, _("\
19384 -mfix-loongson2f-jump work around Loongson2F JUMP instructions\n\
19385 -mfix-loongson2f-nop work around Loongson2F NOP errata\n\
19386 -mfix-vr4120 work around certain VR4120 errata\n\
19387 -mfix-vr4130 work around VR4130 mflo/mfhi errata\n\
19388 -mfix-24k insert a nop after ERET and DERET instructions\n\
19389 -mfix-cn63xxp1 work around CN63XXP1 PREF errata\n\
19390 -mgp32 use 32-bit GPRs, regardless of the chosen ISA\n\
19391 -mfp32 use 32-bit FPRs, regardless of the chosen ISA\n\
19392 -msym32 assume all symbols have 32-bit values\n\
19393 -O0 remove unneeded NOPs, do not swap branches\n\
19394 -O remove unneeded NOPs and swap branches\n\
19395 --trap, --no-break trap exception on div by 0 and mult overflow\n\
19396 --break, --no-trap break exception on div by 0 and mult overflow\n"));
19397 fprintf (stream
, _("\
19398 -mhard-float allow floating-point instructions\n\
19399 -msoft-float do not allow floating-point instructions\n\
19400 -msingle-float only allow 32-bit floating-point operations\n\
19401 -mdouble-float allow 32-bit and 64-bit floating-point operations\n\
19402 --[no-]construct-floats [dis]allow floating point values to be constructed\n"
19405 fprintf (stream
, _("\
19406 -KPIC, -call_shared generate SVR4 position independent code\n\
19407 -call_nonpic generate non-PIC code that can operate with DSOs\n\
19408 -mvxworks-pic generate VxWorks position independent code\n\
19409 -non_shared do not generate code that can operate with DSOs\n\
19410 -xgot assume a 32 bit GOT\n\
19411 -mpdr, -mno-pdr enable/disable creation of .pdr sections\n\
19412 -mshared, -mno-shared disable/enable .cpload optimization for\n\
19413 position dependent (non shared) code\n\
19414 -mabi=ABI create ABI conformant object file for:\n"));
19418 show (stream
, "32", &column
, &first
);
19419 show (stream
, "o64", &column
, &first
);
19420 show (stream
, "n32", &column
, &first
);
19421 show (stream
, "64", &column
, &first
);
19422 show (stream
, "eabi", &column
, &first
);
19424 fputc ('\n', stream
);
19426 fprintf (stream
, _("\
19427 -32 create o32 ABI object file (default)\n\
19428 -n32 create n32 ABI object file\n\
19429 -64 create 64 ABI object file\n"));
19435 mips_dwarf2_format (asection
*sec ATTRIBUTE_UNUSED
)
19437 if (HAVE_64BIT_SYMBOLS
)
19438 return dwarf2_format_64bit_irix
;
19440 return dwarf2_format_32bit
;
19445 mips_dwarf2_addr_size (void)
19447 if (HAVE_64BIT_OBJECTS
)
19453 /* Standard calling conventions leave the CFA at SP on entry. */
19455 mips_cfi_frame_initial_instructions (void)
19457 cfi_add_CFA_def_cfa_register (SP
);
19461 tc_mips_regname_to_dw2regnum (char *regname
)
19463 unsigned int regnum
= -1;
19466 if (reg_lookup (®name
, RTYPE_GP
| RTYPE_NUM
, ®
))